From 828096ce6e2959d2672d9a9746ee3247bcd4cc97 Mon Sep 17 00:00:00 2001 From: Duncan Ogilvie Date: Sat, 12 Aug 2023 23:07:54 +0200 Subject: [PATCH] Attempt at Python packaging --- .gitattributes | 1 + .github/workflows/CI.yml | 195 +- .gitignore | 8 +- Cargo.lock | 33 +- Cargo.toml | 4 +- LICENSE | 23 + MANIFEST.in | 12 + copy-ghidra.py | 39 + pyproject.toml | 18 +- .../Processors/6502/data/languages/6502.cspec | 34 + .../Processors/6502/data/languages/6502.ldefs | 33 + .../Processors/6502/data/languages/6502.pspec | 16 + .../6502/data/languages/6502.slaspec | 499 + .../6502/data/languages/65c02.slaspec | 222 + .../68000/data/languages/68000.cspec | 69 + .../68000/data/languages/68000.dwarf | 10 + .../68000/data/languages/68000.ldefs | 67 + .../68000/data/languages/68000.opinion | 17 + .../68000/data/languages/68000.pspec | 9 + .../68000/data/languages/68000.sinc | 2954 ++ .../68000/data/languages/68020.slaspec | 1 + .../68000/data/languages/68030.slaspec | 2 + .../68000/data/languages/68040.slaspec | 2 + .../68000/data/languages/coldfire.slaspec | 6 + .../Processors/8048/data/languages/8048.cspec | 31 + .../Processors/8048/data/languages/8048.ldefs | 18 + .../Processors/8048/data/languages/8048.pspec | 49 + .../8048/data/languages/8048.slaspec | 539 + .../8051/data/languages/80251.cspec | 54 + .../8051/data/languages/80251.pspec | 1070 + .../Processors/8051/data/languages/80251.sinc | 662 + .../8051/data/languages/80251.slaspec | 5 + .../8051/data/languages/80390.cspec | 62 + .../8051/data/languages/80390.slaspec | 3 + .../Processors/8051/data/languages/8051.cspec | 72 + .../Processors/8051/data/languages/8051.ldefs | 53 + .../Processors/8051/data/languages/8051.pspec | 413 + .../8051/data/languages/8051.slaspec | 3 + .../8051/data/languages/8051_archimedes.cspec | 99 + .../8051/data/languages/8051_main.sinc | 917 + .../Processors/8051/data/languages/mx51.cspec | 73 + .../Processors/8051/data/languages/mx51.pspec | 423 + .../Processors/8051/data/languages/mx51.sinc | 332 + .../8051/data/languages/mx51.slaspec | 7 + .../8051/data/languages/old/8051v1.lang | 44 + .../8051/data/languages/old/8051v1.trans | 8 + .../Processors/8085/data/languages/8085.cspec | 28 + .../Processors/8085/data/languages/8085.ldefs | 15 + .../Processors/8085/data/languages/8085.pspec | 30 + .../8085/data/languages/8085.slaspec | 551 + .../AARCH64/data/languages/AARCH64.cspec | 205 + .../AARCH64/data/languages/AARCH64.dwarf | 8 + .../AARCH64/data/languages/AARCH64.ldefs | 64 + .../AARCH64/data/languages/AARCH64.opinion | 17 + .../AARCH64/data/languages/AARCH64.pspec | 101 + .../AARCH64/data/languages/AARCH64.slaspec | 5 + .../AARCH64/data/languages/AARCH64BE.slaspec | 5 + .../data/languages/AARCH64_AMXext.sinc | 171 + .../languages/AARCH64_AppleSilicon.slaspec | 6 + .../languages/AARCH64_base_PACoptions.sinc | 164 + .../data/languages/AARCH64_ilp32.cspec | 207 + .../AARCH64/data/languages/AARCH64_win.cspec | 214 + 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.../ARM/data/languages/ARM5t_le.slaspec | 8 + .../ARM/data/languages/ARM6_be.slaspec | 12 + .../ARM/data/languages/ARM6_le.slaspec | 12 + .../ARM/data/languages/ARM7_be.slaspec | 16 + .../ARM/data/languages/ARM7_le.slaspec | 16 + .../ARM/data/languages/ARM8_be.slaspec | 17 + .../ARM/data/languages/ARM8_le.slaspec | 17 + .../ARM/data/languages/ARMCortex.pspec | 42 + .../data/languages/ARMTHUMBinstructions.sinc | 5331 +++ .../ARM/data/languages/ARM_v45.cspec | 209 + .../ARM/data/languages/ARM_v45.pspec | 40 + .../ARM/data/languages/ARM_win.cspec | 131 + .../ARM/data/languages/ARMinstructions.sinc | 6488 ++++ .../ARM/data/languages/ARMneon.dwarf | 14 + .../ARM/data/languages/ARMneon.sinc | 6141 ++++ .../Processors/ARM/data/languages/ARMt.pspec | 64 + .../ARM/data/languages/ARMtTHUMB.pspec | 65 + .../ARM/data/languages/ARMt_v45.pspec | 43 + .../ARM/data/languages/ARMt_v6.pspec | 44 + .../Processors/ARM/data/languages/ARMv8.sinc | 1348 + .../ARM/data/languages/old/ARMv5.lang | 62 + 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.../HCS08/data/languages/HC05.pspec | 33 + .../HCS08/data/languages/HC05.slaspec | 5 + .../data/languages/HC08-MC68HC908QY4.pspec | 127 + .../HCS08/data/languages/HC08.ldefs | 28 + .../HCS08/data/languages/HC08.pspec | 17 + .../HCS08/data/languages/HC08.slaspec | 5 + .../data/languages/HCS08-MC9S08GB60.pspec | 244 + .../HCS08/data/languages/HCS08.cspec | 50 + .../HCS08/data/languages/HCS08.ldefs | 28 + .../HCS08/data/languages/HCS08.opinion | 6 + .../HCS08/data/languages/HCS08.pspec | 28 + .../HCS08/data/languages/HCS08.slaspec | 5 + .../HCS08/data/languages/HCS_HC.sinc | 2083 ++ .../HCS12/data/languages/HC12.cspec | 58 + .../HCS12/data/languages/HC12.pspec | 75 + .../HCS12/data/languages/HC12.slaspec | 9 + .../HCS12/data/languages/HCS12.cspec | 102 + .../HCS12/data/languages/HCS12.ldefs | 59 + .../HCS12/data/languages/HCS12.opinion | 8 + .../HCS12/data/languages/HCS12.pspec | 94 + .../HCS12/data/languages/HCS12.slaspec | 9 + .../HCS12/data/languages/HCS12X.cspec | 156 + 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.../MC6800/data/languages/6809.pspec | 5 + .../MC6800/data/languages/6809.slaspec | 8 + .../MC6800/data/languages/6x09.sinc | 1397 + .../MC6800/data/languages/6x09_exg_tfr.sinc | 170 + .../MC6800/data/languages/6x09_pull.sinc | 48 + .../MC6800/data/languages/6x09_push.sinc | 47 + .../MC6800/data/languages/H6309.slaspec | 10 + .../MCS96/data/languages/MCS96.cspec | 31 + .../MCS96/data/languages/MCS96.ldefs | 16 + .../MCS96/data/languages/MCS96.pspec | 11 + .../MCS96/data/languages/MCS96.sinc | 1368 + .../MCS96/data/languages/MCS96.slaspec | 4 + .../MIPS/data/languages/MIPS.opinion | 179 + .../Processors/MIPS/data/languages/mips.dwarf | 21 + .../Processors/MIPS/data/languages/mips.ldefs | 309 + .../Processors/MIPS/data/languages/mips.sinc | 1014 + .../MIPS/data/languages/mips16.sinc | 761 + .../MIPS/data/languages/mips32.pspec | 78 + .../data/languages/mips32Instructions.sinc | 1744 + .../MIPS/data/languages/mips32R6.pspec | 79 + .../MIPS/data/languages/mips32R6be.slaspec | 11 + .../MIPS/data/languages/mips32R6le.slaspec | 11 + .../MIPS/data/languages/mips32_fp64.cspec | 88 + .../MIPS/data/languages/mips32be.cspec | 107 + .../MIPS/data/languages/mips32be.slaspec | 12 + .../MIPS/data/languages/mips32be_eabi.cspec | 123 + .../MIPS/data/languages/mips32le.cspec | 106 + .../MIPS/data/languages/mips32le.slaspec | 12 + .../MIPS/data/languages/mips32le_eabi.cspec | 123 + .../MIPS/data/languages/mips32micro.pspec | 79 + .../MIPS/data/languages/mips64.cspec | 111 + .../MIPS/data/languages/mips64.pspec | 79 + .../data/languages/mips64Instructions.sinc | 444 + .../MIPS/data/languages/mips64R6.pspec | 79 + .../MIPS/data/languages/mips64_32_n32.cspec | 136 + .../MIPS/data/languages/mips64_32_o32.cspec | 128 + .../MIPS/data/languages/mips64_32_o64.cspec | 98 + .../MIPS/data/languages/mips64be.slaspec | 12 + .../MIPS/data/languages/mips64le.slaspec | 13 + .../MIPS/data/languages/mips64micro.pspec | 77 + .../MIPS/data/languages/mips_dsp.sinc | 1242 + .../MIPS/data/languages/mips_mt.sinc | 152 + .../MIPS/data/languages/mipsfloat.sinc | 1243 + .../MIPS/data/languages/mipsmicro.sinc | 3883 ++ .../PA-RISC/data/languages/pa-risc.ldefs | 18 + .../PA-RISC/data/languages/pa-risc.opinion | 5 + .../PA-RISC/data/languages/pa-risc.sinc | 1746 + .../PA-RISC/data/languages/pa-risc32.cspec | 70 + .../PA-RISC/data/languages/pa-risc32.pspec | 9 + .../data/languages/pa-risc32be.slaspec | 8 + .../data/languages/pa-riscInstructions.sinc | 1884 + .../Processors/PIC/data/languages/PIC24.cspec | 112 + .../Processors/PIC/data/languages/PIC24.ldefs | 92 + .../PIC/data/languages/PIC24.opinion | 15 + .../Processors/PIC/data/languages/PIC24.pspec | 28 + .../Processors/PIC/data/languages/PIC24.sinc | 8029 +++++ .../PIC/data/languages/PIC24E.slaspec | 9 + .../PIC/data/languages/PIC24F.slaspec | 9 + .../PIC/data/languages/PIC24H.slaspec | 9 + .../Processors/PIC/data/languages/PIC30.dwarf | 21 + .../Processors/PIC/data/languages/PIC33.dwarf | 21 + .../PIC/data/languages/dsPIC30F.slaspec | 9 + .../PIC/data/languages/dsPIC33C.slaspec | 7 + .../PIC/data/languages/dsPIC33E.slaspec | 9 + .../PIC/data/languages/dsPIC33F.slaspec | 9 + .../Processors/PIC/data/languages/pic12.sinc | 63 + .../data/languages/pic12_instructions.sinc | 624 + .../PIC/data/languages/pic12c5xx.cspec | 40 + .../PIC/data/languages/pic12c5xx.ldefs | 17 + .../PIC/data/languages/pic12c5xx.pspec | 25 + .../PIC/data/languages/pic12c5xx.slaspec | 28 + .../Processors/PIC/data/languages/pic16.cspec | 45 + .../Processors/PIC/data/languages/pic16.ldefs | 31 + .../Processors/PIC/data/languages/pic16.pspec | 96 + .../Processors/PIC/data/languages/pic16.sinc | 95 + .../PIC/data/languages/pic16.slaspec | 5 + .../data/languages/pic16_instructions.sinc | 969 + .../PIC/data/languages/pic16c5x.cspec | 37 + .../PIC/data/languages/pic16c5x.ldefs | 17 + .../PIC/data/languages/pic16c5x.pspec | 22 + .../PIC/data/languages/pic16c5x.slaspec | 30 + .../PIC/data/languages/pic16f.cspec | 45 + .../PIC/data/languages/pic16f.pspec | 179 + .../PIC/data/languages/pic16f.slaspec | 5 + .../PIC/data/languages/pic17c7xx.cspec | 52 + .../PIC/data/languages/pic17c7xx.ldefs | 16 + .../PIC/data/languages/pic17c7xx.pspec | 59 + .../PIC/data/languages/pic17c7xx.sinc | 55 + .../PIC/data/languages/pic17c7xx.slaspec | 67 + .../languages/pic17c7xx_instructions.sinc | 916 + .../Processors/PIC/data/languages/pic18.cspec | 45 + .../Processors/PIC/data/languages/pic18.ldefs | 17 + .../Processors/PIC/data/languages/pic18.pspec | 47 + .../Processors/PIC/data/languages/pic18.sinc | 78 + .../PIC/data/languages/pic18.slaspec | 40 + .../data/languages/pic18_instructions.sinc | 1700 + .../PowerPC/data/languages/4xx.sinc | 7 + .../PowerPC/data/languages/FPRC.sinc | 210 + .../PowerPC/data/languages/PowerPC.opinion | 21 + .../PowerPC/data/languages/SPEF_SCR.sinc | 130 + .../PowerPC/data/languages/SPE_APU.sinc | 3125 ++ .../PowerPC/data/languages/SPE_EFSD.sinc | 798 + .../PowerPC/data/languages/SPE_EFV.sinc | 1491 + .../PowerPC/data/languages/Scalar_SPFP.sinc | 472 + .../PowerPC/data/languages/altivec.sinc | 1852 + .../PowerPC/data/languages/evx.sinc | 129 + .../Processors/PowerPC/data/languages/g2.sinc | 14 + .../data/languages/lmwInstructions.sinc | 101 + .../data/languages/lswInstructions.sinc | 185 + .../PowerPC/data/languages/old/oldPPC.lang | 1196 + .../PowerPC/data/languages/old/oldPPC.trans | 7 + .../PowerPC/data/languages/ppc.dwarf | 19 + .../PowerPC/data/languages/ppc.ldefs | 335 + .../PowerPC/data/languages/ppc_32.pspec | 1223 + .../data/languages/ppc_32_4xx_be.slaspec | 13 + .../data/languages/ppc_32_4xx_le.slaspec | 13 + .../PowerPC/data/languages/ppc_32_be.cspec | 126 + .../PowerPC/data/languages/ppc_32_be.slaspec | 14 + .../data/languages/ppc_32_be_Mac.cspec | 74 + .../data/languages/ppc_32_e500_be.cspec | 80 + .../data/languages/ppc_32_e500_be.slaspec | 29 + .../data/languages/ppc_32_e500_le.cspec | 79 + .../data/languages/ppc_32_e500_le.slaspec | 29 + .../PowerPC/data/languages/ppc_32_le.cspec | 126 + .../PowerPC/data/languages/ppc_32_le.slaspec | 11 + .../data/languages/ppc_32_mpc8270.pspec | 1156 + .../data/languages/ppc_32_quicciii_be.slaspec | 14 + .../data/languages/ppc_32_quicciii_le.slaspec | 14 + .../PowerPC/data/languages/ppc_64.cspec | 124 + .../PowerPC/data/languages/ppc_64.pspec | 1220 + .../PowerPC/data/languages/ppc_64_32.cspec | 129 + .../PowerPC/data/languages/ppc_64_be.slaspec | 11 + .../data/languages/ppc_64_be_Mac.cspec | 109 + .../languages/ppc_64_isa_altivec_be.slaspec | 33 + .../languages/ppc_64_isa_altivec_le.slaspec | 34 + .../ppc_64_isa_altivec_vle_be.slaspec | 35 + .../data/languages/ppc_64_isa_be.slaspec | 32 + .../data/languages/ppc_64_isa_le.slaspec | 33 + .../data/languages/ppc_64_isa_vle_be.slaspec | 34 + .../PowerPC/data/languages/ppc_64_le.slaspec | 11 + .../PowerPC/data/languages/ppc_a2.sinc | 113 + .../PowerPC/data/languages/ppc_common.sinc | 2015 ++ .../PowerPC/data/languages/ppc_embedded.sinc | 216 + .../data/languages/ppc_instructions.sinc | 4534 +++ .../PowerPC/data/languages/ppc_isa.sinc | 2744 ++ .../PowerPC/data/languages/ppc_vle.sinc | 938 + .../PowerPC/data/languages/quicciii.sinc | 131 + .../data/languages/stmwInstructions.sinc | 101 + .../data/languages/stswiInstructions.sinc | 186 + .../PowerPC/data/languages/vsx.sinc | 1665 + .../RISCV/data/languages/RV32G.pspec | 19 + .../RISCV/data/languages/RV32GC.pspec | 20 + .../RISCV/data/languages/RV32I.pspec | 14 + .../RISCV/data/languages/RV32IC.pspec | 15 + .../RISCV/data/languages/RV32IMC.pspec | 16 + .../RISCV/data/languages/RV64G.pspec | 19 + .../RISCV/data/languages/RV64GC.pspec | 20 + .../RISCV/data/languages/RV64I.pspec | 14 + .../RISCV/data/languages/RV64IC.pspec | 15 + .../RISCV/data/languages/riscv.csr.sinc | 166 + .../RISCV/data/languages/riscv.custom.sinc | 155 + .../RISCV/data/languages/riscv.ilp32d.slaspec | 15 + .../RISCV/data/languages/riscv.instr.sinc | 1051 + .../RISCV/data/languages/riscv.ldefs | 149 + .../RISCV/data/languages/riscv.lp64d.slaspec | 15 + .../RISCV/data/languages/riscv.opinion | 28 + .../RISCV/data/languages/riscv.priv.sinc | 142 + .../RISCV/data/languages/riscv.reg.sinc | 1373 + .../RISCV/data/languages/riscv.rv32a.sinc | 132 + .../RISCV/data/languages/riscv.rv32b.sinc | 131 + .../RISCV/data/languages/riscv.rv32d.sinc | 246 + .../RISCV/data/languages/riscv.rv32f.sinc | 254 + .../RISCV/data/languages/riscv.rv32i.sinc | 382 + .../RISCV/data/languages/riscv.rv32k.sinc | 59 + .../RISCV/data/languages/riscv.rv32m.sinc | 65 + .../RISCV/data/languages/riscv.rv32p.sinc | 996 + .../RISCV/data/languages/riscv.rv32q.sinc | 236 + .../RISCV/data/languages/riscv.rv64a.sinc | 132 + .../RISCV/data/languages/riscv.rv64b.sinc | 109 + .../RISCV/data/languages/riscv.rv64d.sinc | 47 + .../RISCV/data/languages/riscv.rv64f.sinc | 33 + .../RISCV/data/languages/riscv.rv64i.sinc | 121 + .../RISCV/data/languages/riscv.rv64k.sinc | 35 + .../RISCV/data/languages/riscv.rv64m.sinc | 44 + .../RISCV/data/languages/riscv.rv64p.sinc | 294 + .../RISCV/data/languages/riscv.rv64q.sinc | 28 + .../RISCV/data/languages/riscv.rvc.sinc | 370 + .../RISCV/data/languages/riscv.rvv.sinc | 1955 + .../RISCV/data/languages/riscv.table.sinc | 384 + .../RISCV/data/languages/riscv.zi.sinc | 7 + .../RISCV/data/languages/riscv32-fp.cspec | 132 + .../RISCV/data/languages/riscv32.cspec | 88 + .../RISCV/data/languages/riscv32.dwarf | 22 + .../RISCV/data/languages/riscv64-fp.cspec | 132 + .../RISCV/data/languages/riscv64.cspec | 88 + .../RISCV/data/languages/riscv64.dwarf | 22 + .../Sparc/data/languages/Sparc.opinion | 13 + .../Sparc/data/languages/SparcV9.ldefs | 32 + .../Sparc/data/languages/SparcV9.pspec | 21 + .../Sparc/data/languages/SparcV9.sinc | 1401 + .../Sparc/data/languages/SparcV9_32.cspec | 103 + .../Sparc/data/languages/SparcV9_32.slaspec | 4 + .../Sparc/data/languages/SparcV9_64.cspec | 190 + .../Sparc/data/languages/SparcV9_64.slaspec | 6 + .../Sparc/data/languages/SparcVIS.sinc | 445 + .../SuperH/data/languages/sh-1.slaspec | 4 + .../SuperH/data/languages/sh-2.slaspec | 3 + .../SuperH/data/languages/sh-2a.slaspec | 4 + .../SuperH/data/languages/superh.cspec | 72 + .../SuperH/data/languages/superh.ldefs | 37 + .../SuperH/data/languages/superh.pspec | 5 + .../SuperH/data/languages/superh.sinc | 2410 ++ .../SuperH/data/languages/superh2a.cspec | 88 + .../SuperH4/data/languages/SuperH4.ldefs | 33 + .../SuperH4/data/languages/SuperH4.opinion | 12 + .../SuperH4/data/languages/SuperH4.pspec | 14 + .../SuperH4/data/languages/SuperH4.sinc | 3133 ++ .../SuperH4/data/languages/SuperH4_be.cspec | 128 + .../SuperH4/data/languages/SuperH4_be.slaspec | 8 + .../SuperH4/data/languages/SuperH4_le.cspec | 128 + .../SuperH4/data/languages/SuperH4_le.slaspec | 9 + .../data/languages/old/SuperH4-BE-16.lang | 131 + .../data/languages/old/SuperH4-BE-16.trans | 7 + .../data/languages/old/SuperH4-LE-16.lang | 131 + .../data/languages/old/SuperH4-LE-16.trans | 7 + .../TI_MSP430/data/languages/TI430Common.sinc | 1678 + .../TI_MSP430/data/languages/TI430X.sinc | 3541 ++ .../TI_MSP430/data/languages/TI_MSP430.cspec | 55 + .../TI_MSP430/data/languages/TI_MSP430.ldefs | 31 + .../TI_MSP430/data/languages/TI_MSP430.pspec | 195 + .../data/languages/TI_MSP430.slaspec | 4 + .../TI_MSP430/data/languages/TI_MSP430X.cspec | 65 + .../data/languages/TI_MSP430X.slaspec | 5 + .../data/languages/ti_msp430.opinion | 11 + .../Toy/data/languages/old/ToyV00BE64.lang | 38 + .../Toy/data/languages/old/ToyV0BE64.trans | 20 + .../Toy/data/languages/old/ToyV0LE64.lang | 38 + .../Toy/data/languages/old/ToyV0LE64.trans | 20 + .../Toy/data/languages/old/v01stuff/toy.cspec | 69 + .../data/languages/old/v01stuff/toy.ldefs_v01 | 26 + .../Toy/data/languages/old/v01stuff/toy.sinc | 25 + .../data/languages/old/v01stuff/toy64.cspec | 69 + .../old/v01stuff/toyInstructions.sinc | 200 + .../languages/old/v01stuff/toyPosStack.cspec | 69 + .../Processors/Toy/data/languages/toy.cspec | 99 + .../Processors/Toy/data/languages/toy.ldefs | 137 + .../Processors/Toy/data/languages/toy.pspec | 23 + .../Processors/Toy/data/languages/toy.sinc | 51 + .../Toy/data/languages/toy64-long8.cspec | 90 + .../Processors/Toy/data/languages/toy64.cspec | 90 + .../Toy/data/languages/toy64_be.slaspec | 8 + .../data/languages/toy64_be_harvard.slaspec | 11 + .../Toy/data/languages/toy64_le.slaspec | 8 + .../Toy/data/languages/toyInstructions.sinc | 232 + .../Toy/data/languages/toyPosStack.cspec | 69 + .../Toy/data/languages/toy_be.slaspec | 8 + .../data/languages/toy_be_posStack.slaspec | 9 + .../Toy/data/languages/toy_builder.sinc | 86 + .../Toy/data/languages/toy_builder_be.slaspec | 5 + .../languages/toy_builder_be_align2.slaspec | 6 + .../Toy/data/languages/toy_builder_le.slaspec | 5 + .../languages/toy_builder_le_align2.slaspec | 6 + .../Toy/data/languages/toy_harvard.pspec | 6 + .../Toy/data/languages/toy_le.slaspec | 8 + .../Toy/data/languages/toy_wsz_be.slaspec | 10 + .../Toy/data/languages/toy_wsz_le.slaspec | 10 + .../data/languages/Helpers/Conditions.sinc | 38 + .../V850/data/languages/Helpers/Extras.sinc | 131 + .../V850/data/languages/Helpers/Macros.sinc | 254 + .../V850/data/languages/Helpers/Register.sinc | 36 + .../V850/data/languages/Helpers/Tokens.sinc | 105 + .../data/languages/Helpers/Variables.sinc | 49 + .../languages/Instructions/Arithmetic.sinc | 336 + .../data/languages/Instructions/Float.sinc | 498 + .../languages/Instructions/Load_Store.sinc | 368 + .../data/languages/Instructions/Logic.sinc | 167 + .../data/languages/Instructions/Special.sinc | 372 + .../Processors/V850/data/languages/V850.cspec | 68 + .../Processors/V850/data/languages/V850.ldefs | 16 + .../V850/data/languages/V850.opinion | 6 + .../Processors/V850/data/languages/V850.pspec | 13 + .../V850/data/languages/V850.slaspec | 37 + .../Processors/Z80/data/languages/z180.pspec | 114 + .../Z80/data/languages/z180.slaspec | 3 + .../Processors/Z80/data/languages/z182.pspec | 153 + .../Processors/Z80/data/languages/z80.cspec | 122 + .../Processors/Z80/data/languages/z80.ldefs | 57 + .../Processors/Z80/data/languages/z80.pspec | 43 + .../Processors/Z80/data/languages/z80.slaspec | 2078 ++ .../Z80/data/languages/z8401x.pspec | 62 + .../tricore/data/languages/tc172x.pspec | 2346 ++ .../tricore/data/languages/tc176x.pspec | 1527 + .../tricore/data/languages/tc29x.pspec | 3730 ++ .../tricore/data/languages/tricore.cspec | 184 + .../tricore/data/languages/tricore.dwarf | 27 + .../tricore/data/languages/tricore.ldefs | 57 + .../tricore/data/languages/tricore.opinion | 5 + .../tricore/data/languages/tricore.pcp.sinc | 861 + .../tricore/data/languages/tricore.pspec | 13 + .../tricore/data/languages/tricore.sinc | 8548 +++++ .../tricore/data/languages/tricore.slaspec | 13 + .../Processors/x86/data/languages/adx.sinc | 33 + .../Processors/x86/data/languages/avx.sinc | 3275 ++ .../Processors/x86/data/languages/avx2.sinc | 1221 + .../x86/data/languages/avx2_manual.sinc | 252 + .../x86/data/languages/avx_manual.sinc | 287 + .../Processors/x86/data/languages/bmi1.sinc | 195 + .../Processors/x86/data/languages/bmi2.sinc | 209 + .../Processors/x86/data/languages/cet.sinc | 84 + .../Processors/x86/data/languages/clwb.sinc | 14 + .../Processors/x86/data/languages/fma.sinc | 800 + .../Processors/x86/data/languages/ia.sinc | 9100 +++++ .../x86/data/languages/lockable.sinc | 1380 + .../Processors/x86/data/languages/lzcnt.sinc | 32 + .../Processors/x86/data/languages/macros.sinc | 3 + .../Processors/x86/data/languages/mpx.sinc | 234 + .../x86/data/languages/old/x86RealV1.lang | 150 + .../x86/data/languages/old/x86RealV1.trans | 7 + .../x86/data/languages/old/x86V1.lang | 151 + .../x86/data/languages/old/x86V1.trans | 8 + .../x86/data/languages/old/x86_64bit_v1.lang | 221 + .../x86/data/languages/old/x86_64bit_v1.trans | 8 + .../x86/data/languages/old/x86smmV1.lang | 150 + .../x86/data/languages/old/x86smmV1.trans | 7 + .../x86/data/languages/pclmulqdq.sinc | 173 + .../Processors/x86/data/languages/rdrand.sinc | 51 + .../Processors/x86/data/languages/sgx.sinc | 257 + .../Processors/x86/data/languages/sha.sinc | 53 + .../Processors/x86/data/languages/smx.sinc | 67 + .../x86/data/languages/x86-16-real.pspec | 33 + .../x86/data/languages/x86-16.cspec | 174 + .../Processors/x86/data/languages/x86-16.gdis | 3 + .../x86/data/languages/x86-16.pspec | 34 + .../x86/data/languages/x86-64-gcc.cspec | 242 + .../x86/data/languages/x86-64-win.cspec | 224 + .../x86/data/languages/x86-64.dwarf | 34 + .../x86/data/languages/x86-64.pspec | 160 + .../x86/data/languages/x86-64.slaspec | 6 + .../Processors/x86/data/languages/x86.dwarf | 34 + .../Processors/x86/data/languages/x86.ldefs | 98 + .../Processors/x86/data/languages/x86.opinion | 81 + .../Processors/x86/data/languages/x86.pspec | 121 + .../Processors/x86/data/languages/x86.slaspec | 19 + .../x86/data/languages/x86borland.cspec | 150 + .../x86/data/languages/x86delphi.cspec | 99 + .../x86/data/languages/x86gcc.cspec | 377 + .../x86/data/languages/x86win.cspec | 380 + python/icicle/__init__.py | 20 + icicle.pyi => python/icicle/icicle.pyi | 0 python/icicle/py.typed | 0 requirements.txt | 4 +- setup.cfg | 28 + setup.py | 32 + src/lib.rs | 22 +- tests/example.py | 3 + 598 files changed, 255445 insertions(+), 141 deletions(-) create mode 100644 .gitattributes create mode 100644 LICENSE create mode 100644 MANIFEST.in create mode 100644 copy-ghidra.py create mode 100644 python/icicle/Ghidra/Processors/6502/data/languages/6502.cspec create mode 100644 python/icicle/Ghidra/Processors/6502/data/languages/6502.ldefs create mode 100644 python/icicle/Ghidra/Processors/6502/data/languages/6502.pspec create mode 100644 python/icicle/Ghidra/Processors/6502/data/languages/6502.slaspec create mode 100644 python/icicle/Ghidra/Processors/6502/data/languages/65c02.slaspec create mode 100644 python/icicle/Ghidra/Processors/68000/data/languages/68000.cspec create mode 100644 python/icicle/Ghidra/Processors/68000/data/languages/68000.dwarf create mode 100644 python/icicle/Ghidra/Processors/68000/data/languages/68000.ldefs create mode 100644 python/icicle/Ghidra/Processors/68000/data/languages/68000.opinion create mode 100644 python/icicle/Ghidra/Processors/68000/data/languages/68000.pspec create mode 100644 python/icicle/Ghidra/Processors/68000/data/languages/68000.sinc create mode 100644 python/icicle/Ghidra/Processors/68000/data/languages/68020.slaspec create mode 100644 python/icicle/Ghidra/Processors/68000/data/languages/68030.slaspec create mode 100644 python/icicle/Ghidra/Processors/68000/data/languages/68040.slaspec create mode 100644 python/icicle/Ghidra/Processors/68000/data/languages/coldfire.slaspec create mode 100644 python/icicle/Ghidra/Processors/8048/data/languages/8048.cspec create mode 100644 python/icicle/Ghidra/Processors/8048/data/languages/8048.ldefs create mode 100644 python/icicle/Ghidra/Processors/8048/data/languages/8048.pspec create mode 100644 python/icicle/Ghidra/Processors/8048/data/languages/8048.slaspec create mode 100644 python/icicle/Ghidra/Processors/8051/data/languages/80251.cspec create mode 100644 python/icicle/Ghidra/Processors/8051/data/languages/80251.pspec create mode 100644 python/icicle/Ghidra/Processors/8051/data/languages/80251.sinc create mode 100644 python/icicle/Ghidra/Processors/8051/data/languages/80251.slaspec create mode 100644 python/icicle/Ghidra/Processors/8051/data/languages/80390.cspec create mode 100644 python/icicle/Ghidra/Processors/8051/data/languages/80390.slaspec create mode 100644 python/icicle/Ghidra/Processors/8051/data/languages/8051.cspec create mode 100644 python/icicle/Ghidra/Processors/8051/data/languages/8051.ldefs create mode 100644 python/icicle/Ghidra/Processors/8051/data/languages/8051.pspec create mode 100644 python/icicle/Ghidra/Processors/8051/data/languages/8051.slaspec create mode 100644 python/icicle/Ghidra/Processors/8051/data/languages/8051_archimedes.cspec create mode 100644 python/icicle/Ghidra/Processors/8051/data/languages/8051_main.sinc create mode 100644 python/icicle/Ghidra/Processors/8051/data/languages/mx51.cspec create mode 100644 python/icicle/Ghidra/Processors/8051/data/languages/mx51.pspec create mode 100644 python/icicle/Ghidra/Processors/8051/data/languages/mx51.sinc create mode 100644 python/icicle/Ghidra/Processors/8051/data/languages/mx51.slaspec create mode 100644 python/icicle/Ghidra/Processors/8051/data/languages/old/8051v1.lang create mode 100644 python/icicle/Ghidra/Processors/8051/data/languages/old/8051v1.trans create mode 100644 python/icicle/Ghidra/Processors/8085/data/languages/8085.cspec create mode 100644 python/icicle/Ghidra/Processors/8085/data/languages/8085.ldefs create mode 100644 python/icicle/Ghidra/Processors/8085/data/languages/8085.pspec create mode 100644 python/icicle/Ghidra/Processors/8085/data/languages/8085.slaspec create mode 100644 python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.cspec create mode 100644 python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.dwarf create mode 100644 python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.ldefs create mode 100644 python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.opinion create mode 100644 python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.pspec create mode 100644 python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.slaspec create mode 100644 python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64BE.slaspec create mode 100644 python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_AMXext.sinc create mode 100644 python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_AppleSilicon.slaspec create mode 100644 python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_base_PACoptions.sinc create mode 100644 python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_ilp32.cspec create mode 100644 python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_win.cspec create mode 100644 python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc create mode 100644 python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64instructions.sinc create mode 100644 python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64ldst.sinc create mode 100644 python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64neon.sinc create mode 100644 python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64sve.sinc create mode 100644 python/icicle/Ghidra/Processors/AARCH64/data/languages/AppleSilicon.ldefs create mode 100644 python/icicle/Ghidra/Processors/ARM/data/languages/ARM.cspec create mode 100644 python/icicle/Ghidra/Processors/ARM/data/languages/ARM.dwarf create mode 100644 python/icicle/Ghidra/Processors/ARM/data/languages/ARM.gdis create mode 100644 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create mode 100644 python/icicle/Ghidra/Processors/x86/data/languages/x86delphi.cspec create mode 100644 python/icicle/Ghidra/Processors/x86/data/languages/x86gcc.cspec create mode 100644 python/icicle/Ghidra/Processors/x86/data/languages/x86win.cspec create mode 100644 python/icicle/__init__.py rename icicle.pyi => python/icicle/icicle.pyi (100%) create mode 100644 python/icicle/py.typed create mode 100644 setup.cfg create mode 100644 setup.py diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 0000000..36ab773 --- /dev/null +++ b/.gitattributes @@ -0,0 +1 @@ +python/Ghidra/** linguist-generated \ No newline at end of file diff --git a/.github/workflows/CI.yml b/.github/workflows/CI.yml index 8ca982d..dff158a 100644 --- a/.github/workflows/CI.yml +++ b/.github/workflows/CI.yml @@ -1,111 +1,124 @@ -# This file is autogenerated by maturin v1.0.1 -# To update, run -# -# maturin generate-ci github -# name: CI -on: - push: - branches: - - main - - master - tags: - - '*' - pull_request: - workflow_dispatch: - -permissions: - contents: read +on: [push, pull_request] jobs: - linux: - runs-on: ubuntu-latest - strategy: - matrix: - target: [x86_64, aarch64] - steps: - - uses: actions/checkout@v3 - with: - submodules: 'true' - - uses: actions/setup-python@v4 - with: - python-version: '3.10' - - name: Build wheels - uses: PyO3/maturin-action@v1 - with: - target: ${{ matrix.target }} - args: --release --out dist --find-interpreter - sccache: 'true' - manylinux: auto - - name: Upload wheels - uses: actions/upload-artifact@v3 - with: - name: wheels - path: dist + # linux: + # runs-on: ubuntu-latest + # strategy: + # matrix: + # target: [x86_64, aarch64] + # steps: + # - uses: actions/checkout@v3 + # with: + # submodules: 'true' + + # - uses: actions/setup-python@v4 + # with: + # python-version: '3.10' + + # - name: Install Rust toolchain + # uses: dtolnay/rust-toolchain@stable + # with: + # targets: aarch64-linux-gnu, x86-64-linux-gnu - windows: - runs-on: windows-latest - strategy: - matrix: - target: [x64] - steps: - - uses: actions/checkout@v3 - with: - submodules: 'true' - - uses: actions/setup-python@v4 - with: - python-version: '3.10' - architecture: ${{ matrix.target }} - - name: Build wheels - uses: PyO3/maturin-action@v1 - with: - target: ${{ matrix.target }} - args: --release --out dist --find-interpreter - sccache: 'true' - - name: Upload wheels - uses: actions/upload-artifact@v3 - with: - name: wheels - path: dist + # - name: Install Rust aarch64-apple-darwin target + # if: matrix.platform.os == 'macos-latest' + # run: rustup target add aarch64-apple-darwin + + # - name: Upload wheels + # uses: actions/upload-artifact@v3 + # with: + # name: wheels + # path: dist + + # windows: + # runs-on: windows-latest + # strategy: + # matrix: + # target: [x64] + # steps: + # - uses: actions/checkout@v3 + # with: + # submodules: 'true' + + # - uses: actions/setup-python@v4 + # with: + # python-version: '3.10' + # architecture: ${{ matrix.target }} + + # - name: Build wheels + # uses: PyO3/maturin-action@v1 + # with: + # target: ${{ matrix.target }} + # args: --release --out dist --find-interpreter + # sccache: 'true' + + # - name: Upload wheels + # uses: actions/upload-artifact@v3 + # with: + # name: wheels + # path: dist macos: + # Skip building pull requests from the same repository + if: ${{ github.event_name == 'push' || (github.event_name == 'pull_request' && github.event.pull_request.head.repo.full_name != github.repository) }} runs-on: macos-latest - strategy: - matrix: - target: [x86_64, aarch64] steps: - - uses: actions/checkout@v3 + - name: Checkout + uses: actions/checkout@v3 with: submodules: 'true' - - uses: actions/setup-python@v4 + + - name: Python environment + uses: actions/setup-python@v4 with: python-version: '3.10' - - name: Build wheels - uses: PyO3/maturin-action@v1 + + - name: Install Rust toolchain + uses: dtolnay/rust-toolchain@stable with: - target: ${{ matrix.target }} - args: --release --out dist --find-interpreter - sccache: 'true' + targets: aarch64-apple-darwin, x86_64-apple-darwin + + - name: Build + shell: bash + env: + DEVELOPER_DIR: /Applications/Xcode.app/Contents/Developer + MACOSX_DEPLOYMENT_TARGET: '10.9' + ARCHFLAGS: -arch x86_64 -arch arm64 + PYO3_CROSS_LIB_DIR: /Applications/Xcode.app/Contents/Developer/Library/Frameworks/Python3.framework/Versions/3.8/lib + run: | + pip install -r requirements.txt + python setup.py bdist_wheel --py-limited-api=cp37 + pip install --force-reinstall dist/*_universal2.whl + python -c "import icicle" + + - name: Test + run: | + pip install -r tests/requirements.txt + python tests/example.py + python tests/invalid.py + - name: Upload wheels uses: actions/upload-artifact@v3 with: name: wheels path: dist - release: - name: Release - runs-on: ubuntu-latest - if: "startsWith(github.ref, 'refs/tags/')" - needs: [linux, windows, macos] - steps: - - uses: actions/download-artifact@v3 - with: - name: wheels - - name: Publish to PyPI - uses: PyO3/maturin-action@v1 - env: - MATURIN_PYPI_TOKEN: ${{ secrets.PYPI_API_TOKEN }} - with: - command: upload - args: --skip-existing * + + # release: + # name: Release + # runs-on: ubuntu-latest + # if: "startsWith(github.ref, 'refs/tags/')" + # needs: [linux, windows, macos] + # steps: + # - uses: actions/download-artifact@v3 + # with: + # name: wheels + # - name: Publish to PyPI + # uses: PyO3/maturin-action@v1 + # env: + # MATURIN_PYPI_TOKEN: ${{ secrets.PYPI_API_TOKEN }} + # with: + # command: upload + # args: --skip-existing * diff --git a/.gitignore b/.gitignore index cc16070..00aa120 100644 --- a/.gitignore +++ b/.gitignore @@ -5,4 +5,10 @@ debug/ venv*/ .env/ dist/ -.DS_Store \ No newline at end of file +build/ +.DS_Store +__pycache__/ +*.egg-info/ +*.so +*.dll +*.dylib \ No newline at end of file diff --git a/Cargo.lock b/Cargo.lock index 2cf8cfc..387e20d 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -321,7 +321,7 @@ dependencies = [ "cranelift-module", "cranelift-native", "icicle-cpu", - "memoffset", + "memoffset 0.8.0", "pcode", "target-lexicon", "tracing", @@ -463,6 +463,15 @@ dependencies = [ "autocfg", ] +[[package]] +name = "memoffset" +version = "0.9.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5a634b1c61a95585bd15607c6ab0c4e5b226e695ff2800ba0cdccddf208c406c" +dependencies = [ + "autocfg", +] + [[package]] name = "miniz_oxide" version = "0.7.1" @@ -552,15 +561,15 @@ dependencies = [ [[package]] name = "pyo3" -version = "0.18.3" +version = "0.19.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "e3b1ac5b3731ba34fdaa9785f8d74d17448cd18f30cf19e0c7e7b1fdb5272109" +checksum = "e681a6cfdc4adcc93b4d3cf993749a4552018ee0a9b65fc0ccfad74352c72a38" dependencies = [ "cfg-if", "indexmap", "indoc", "libc", - "memoffset", + "memoffset 0.9.0", "parking_lot", "pyo3-build-config", "pyo3-ffi", @@ -570,9 +579,9 @@ dependencies = [ [[package]] name = "pyo3-build-config" -version = "0.18.3" +version = "0.19.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9cb946f5ac61bb61a5014924910d936ebd2b23b705f7a4a3c40b05c720b079a3" +checksum = "076c73d0bc438f7a4ef6fdd0c3bb4732149136abd952b110ac93e4edb13a6ba5" dependencies = [ "once_cell", "target-lexicon", @@ -580,9 +589,9 @@ dependencies = [ [[package]] name = "pyo3-ffi" -version = "0.18.3" +version = "0.19.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "fd4d7c5337821916ea2a1d21d1092e8443cf34879e53a0ac653fbb98f44ff65c" +checksum = "e53cee42e77ebe256066ba8aa77eff722b3bb91f3419177cf4cd0f304d3284d9" dependencies = [ "libc", "pyo3-build-config", @@ -590,9 +599,9 @@ dependencies = [ [[package]] name = "pyo3-macros" -version = "0.18.3" +version = "0.19.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a9d39c55dab3fc5a4b25bbd1ac10a2da452c4aca13bb450f22818a002e29648d" +checksum = "dfeb4c99597e136528c6dd7d5e3de5434d1ceaf487436a3f03b2d56b6fc9efd1" dependencies = [ "proc-macro2", "pyo3-macros-backend", @@ -602,9 +611,9 @@ dependencies = [ [[package]] name = "pyo3-macros-backend" -version = "0.18.3" +version = "0.19.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "97daff08a4c48320587b5224cc98d609e3c27b6d437315bd40b605c98eeb5918" +checksum = "947dc12175c254889edc0c02e399476c2f652b4b9ebd123aa655c224de259536" dependencies = [ "proc-macro2", "quote", diff --git a/Cargo.toml b/Cargo.toml index 554d28b..1308565 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -15,10 +15,10 @@ icicle-vm = { path = "icicle-emu/icicle-vm" } pcode = { path = "icicle-emu/sleigh/pcode" } sleigh-runtime = { path = "icicle-emu/sleigh/sleigh-runtime" } indexmap = "1.9.3" -pyo3 = { version = "0.18.3", features = ["extension-module", "indexmap"] } +pyo3 = { version = "0.19.2", features = ["extension-module", "indexmap", "abi3-py37"] } target-lexicon = "0.12.7" tracing = "*" tracing-subscriber = "0.3.17" [build-dependencies] -pyo3-build-config = "0.18.3" +pyo3-build-config = "0.19.2" diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..127a5bc --- /dev/null +++ b/LICENSE @@ -0,0 +1,23 @@ +Boost Software License - Version 1.0 - August 17th, 2003 + +Permission is hereby granted, free of charge, to any person or organization +obtaining a copy of the software and accompanying documentation covered by +this license (the "Software") to use, reproduce, display, distribute, +execute, and transmit the Software, and to prepare derivative works of the +Software, and to permit third-parties to whom the Software is furnished to +do so, all subject to the following: + +The copyright notices in the Software and this entire statement, including +the above license grant, this restriction and the following disclaimer, +must be included in all copies of the Software, in whole or in part, and +all derivative works of the Software, unless such copies or derivative +works are solely in the form of machine-executable object code generated by +a source language processor. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT +SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE +FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +DEALINGS IN THE SOFTWARE. \ No newline at end of file diff --git a/MANIFEST.in b/MANIFEST.in new file mode 100644 index 0000000..2bbea80 --- /dev/null +++ b/MANIFEST.in @@ -0,0 +1,12 @@ +include Cargo.lock +include Cargo.toml +include README.md +include build.rs +include requirements.txt +include copy-ghidra.py +recursive-include src * +recursive-include icicle-emu * +recursive-include python *.py +recursive-include python *.pyi +recursive-include python py.typed +recursive-include python/icicle/Ghidra * \ No newline at end of file diff --git a/copy-ghidra.py b/copy-ghidra.py new file mode 100644 index 0000000..15f5099 --- /dev/null +++ b/copy-ghidra.py @@ -0,0 +1,39 @@ +from os import makedirs +from pathlib import Path +from shutil import copytree, rmtree +from argparse import ArgumentParser + +def main(): + parser = ArgumentParser() + parser.add_argument("ghidra_src", help="Path to the Ghidra source code") + args = parser.parse_args() + ghidra_src = Path(args.ghidra_src) + if not ghidra_src.is_dir(): + raise FileNotFoundError(f"Not a directory: {ghidra_src}") + processors = ghidra_src.joinpath("Ghidra", "Processors") + if not ghidra_src.is_dir(): + raise FileNotFoundError(f"Not found: {processors}") + target_root = Path.cwd().joinpath("python", "icicle", "Ghidra", "Processors") + if target_root.exists(): + rmtree(target_root) + for processor in processors.glob("*"): + if not processor.is_dir(): + continue + name = processor.name + languages = processor.joinpath("data", "languages") + if not languages.is_dir(): + print(f"Processor skipped: {name}") + continue + print(f"Processor: {name}") + processor_root = target_root.joinpath(name, "data", "languages") + copytree(languages, processor_root, dirs_exist_ok=True) + continue + for file in languages.glob("*"): + if not file.is_file(): + print(f"Skip: {file}") + continue + destination = processor_root.joinpath(file.name) + print(f"Copy {file} -> {destination}") + +if __name__ == "__main__": + main() \ No newline at end of file diff --git a/pyproject.toml b/pyproject.toml index a8ecb6a..c620797 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -1,15 +1,7 @@ [build-system] -requires = ["maturin>=1.0,<2.0"] -build-backend = "maturin" - -[project] -name = "icicle-emu" -requires-python = ">=3.7" -classifiers = [ - "Programming Language :: Rust", - "Programming Language :: Python :: Implementation :: CPython", - "Programming Language :: Python :: Implementation :: PyPy", +requires = [ + "setuptools", + "wheel", + "setuptools-rust", ] - -[tool.maturin] -features = ["pyo3/extension-module"] +build-backend = "setuptools.build_meta" \ No newline at end of file diff --git a/python/icicle/Ghidra/Processors/6502/data/languages/6502.cspec b/python/icicle/Ghidra/Processors/6502/data/languages/6502.cspec new file mode 100644 index 0000000..315970d --- /dev/null +++ b/python/icicle/Ghidra/Processors/6502/data/languages/6502.cspec @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/6502/data/languages/6502.ldefs b/python/icicle/Ghidra/Processors/6502/data/languages/6502.ldefs new file mode 100644 index 0000000..bd51b55 --- /dev/null +++ b/python/icicle/Ghidra/Processors/6502/data/languages/6502.ldefs @@ -0,0 +1,33 @@ + + + + + + 6502 Microcontroller Family + + + + + + 65C02 Microcontroller Family + + + + + diff --git a/python/icicle/Ghidra/Processors/6502/data/languages/6502.pspec b/python/icicle/Ghidra/Processors/6502/data/languages/6502.pspec new file mode 100644 index 0000000..b44a7e4 --- /dev/null +++ b/python/icicle/Ghidra/Processors/6502/data/languages/6502.pspec @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/6502/data/languages/6502.slaspec b/python/icicle/Ghidra/Processors/6502/data/languages/6502.slaspec new file mode 100644 index 0000000..4b3b4cd --- /dev/null +++ b/python/icicle/Ghidra/Processors/6502/data/languages/6502.slaspec @@ -0,0 +1,499 @@ +# sleigh specification file for MOS 6502 + +define endian=little; +define alignment=1; + +define space RAM type=ram_space size=2 default; +define space register type=register_space size=1; + +define register offset=0x00 size=1 [ A X Y P ]; +define register offset=0x20 size=2 [ PC SP ]; +define register offset=0x20 size=1 [ PCL PCH S SH ]; +define register offset=0x30 size=1 [ N V B D I Z C ]; # status bits + +#TOKENS + +define token opbyte (8) + op = (0,7) + + aaa = (5,7) + bbb = (2,4) + cc = (0,1) +; + +define token data8 (8) + imm8 = (0,7) + rel = (0,7) signed +; + +define token data (16) + imm16 = (0,15) +; + +macro popSR() { + SP = SP + 1; + local ccr = *:1 SP; + N = ccr[7,1]; + V = ccr[6,1]; + B = ccr[4,1]; + D = ccr[3,1]; + I = ccr[2,1]; + Z = ccr[1,1]; + C = ccr[0,1]; +} + +macro pushSR() { + local ccr:1 = 0xff; + ccr[7,1] = N; + ccr[6,1] = V; + ccr[4,1] = B; + ccr[3,1] = D; + ccr[2,1] = I; + ccr[1,1] = Z; + ccr[0,1] = C; + *:1 (SP) = ccr; + SP = SP -1; +} + +macro resultFlags(value) { + Z = (value == 0); + N = (value s< 0); +} + +macro subtraction_flags1(register, operand, result) { + local complement_register = ~register; + + V = ( ((register & ~operand & ~result) | (complement_register & operand & result)) & 0b10000000 ) != 0; + N = (result s< 0); + Z = (result == 0); + C = ( ((complement_register & operand) | (operand & result) | (result & complement_register)) & 0b10000000 ) != 0; +} + + +################################################################ +# Pseudo Instructions +################################################################ + +define pcodeop readIRQ; + +################################################################ +REL: reloc is rel [ reloc = inst_next + rel; ] { export *:2 reloc; } + +# Immediate +OP1: "#"imm8 is bbb=2; imm8 { tmp:1 = imm8; export tmp; } +# Zero Page +OP1: imm8 is bbb=1; imm8 { export *:1 imm8; } +# Zero Page Indexed X +OP1: imm8,X is bbb=5 & X; imm8 { tmp:2 = zext(imm8 + X); export *:1 tmp; } +# Absolute +OP1: imm16 is bbb=3; imm16 { export *:1 imm16; } +# Absolute Indexed X +OP1: imm16,X is bbb=7 & X; imm16 { tmp:2 = imm16 + zext(X); export *:1 tmp; } +# Absolute Indexed Y +OP1: imm16,Y is bbb=6 & Y; imm16 { tmp:2 = imm16 + zext(Y); export *:1 tmp; } +# Indirect X +OP1: (imm8,X) is bbb=0 & X; imm8 { addr:2 = zext(imm8 + X); tmp:2 = *:2 addr; export *:1 tmp; } +# Indirect Y +OP1: (imm8),Y is bbb=4 & Y; imm8 { addr:2 = imm8; tmp:2 = *:2 addr; tmp = tmp + zext(Y); export *:1 tmp; } + +# Immediate +OP2: "#"imm8 is bbb=0; imm8 { tmp:1 = imm8; export tmp; } +# Zero Page +OP2: imm8 is bbb=1; imm8 { export *:1 imm8; } +OP2: A is bbb=2 & A { export A; } +# Absolute +OP2: imm16 is bbb=3; imm16 { export *:1 imm16; } +# Zero Page Indexed X +OP2: imm8,X is bbb=5 & X; imm8 { tmp:2 = zext(imm8 + X); export *:1 tmp; } +# Absolute Indexed X +OP2: imm16,X is bbb=7 & X; imm16 { tmp:2 = imm16 + zext(X); export *:1 tmp; } + +OP2ST: OP2 is OP2 { export OP2; } +OP2ST: imm8,Y is bbb=5 & Y; imm8 { tmp:2 = zext(imm8 + Y); export *:1 tmp; } + +OP2LD: OP2 is OP2 { export OP2; } +OP2LD: imm8,Y is bbb=5 & Y; imm8 { tmp:2 = zext(imm8 + Y); export *:1 tmp; } +OP2LD: imm16,Y is bbb=7 & Y; imm16 { tmp:2 = imm16 + zext(Y); export *:1 tmp; } + + +ADDR8: imm8 is imm8 { export *:1 imm8; } +ADDR16: imm16 is imm16 { export *:1 imm16; } +ADDRI: (imm16) is imm16 { tmp:2 = imm16; export *:2 tmp; } + + +# Instructions + + +:ADC OP1 is (cc=1 & aaa=3) ... & OP1 +{ + local op1 = OP1; + local tmpC = C; + + C = carry(A, op1); + + A = A + op1 + tmpC; + + resultFlags(A); + V = C; +} + +:AND OP1 is (cc=1 & aaa=1) ... & OP1 +{ + A = A & OP1; + resultFlags(A); +} + +:ASL OP2 is (op=0x06 | op=0x0A | op=0x0E | op=0x16 | op=0x1E) ... & OP2 +{ + local tmp = OP2; + C = tmp >> 7; + tmp = tmp << 1; + OP2 = tmp; + resultFlags(tmp); +} + +:BCC REL is op=0x90; REL +{ + if (C == 0) goto REL; +} + +:BCS REL is op=0xB0; REL +{ + if (C) goto REL; +} + +:BEQ REL is op=0xF0; REL +{ + if (Z) goto REL; +} + +:BIT OP2 is (op=0x24 | op=0x2C) ... & OP2 +{ + N = (OP2 & 0x80) == 0x80; + V = (OP2 & 0x40) == 0x40; + local value = A & OP2; + Z = (value == 0); +} + +:BMI REL is op=0x30; REL +{ + if (N) goto REL; +} + +:BNE REL is op=0xD0; REL +{ + if (Z == 0) goto REL; +} + +:BPL REL is op=0x10; REL +{ + if (N == 0) goto REL; +} + +:BRK is op=0x00 +{ + *:2 (SP - 1) = inst_next; + SP = SP - 2; + B = 1; + pushSR(); + I = 1; + local target:2 = 0xFFFE; + goto [*:2 target]; +} + +:BVC REL is op=0x50; REL +{ + if (V == 0) goto REL; +} + +:BVS REL is op=0x70; REL +{ + if (V) goto REL; +} + +:CLC is op=0x18 +{ + C = 0; +} + +:CLD is op=0xD8 +{ + D = 0; +} + +:CLI is op=0x58 +{ + I = 0; +} + +:CLV is op=0xB8 +{ + V = 0; +} + +:CMP OP1 is (cc=1 & aaa=6) ... & OP1 +{ + local op1 = OP1; + local tmp = A - op1; + resultFlags(tmp); + C = (A >= op1); +} + +:CPX OP2 is (op=0xE0 | op=0xE4 | op=0xEC) ... & OP2 +{ + local op1 = OP2; + local tmp = X - op1; + resultFlags(tmp); + C = (X >= op1); +} + +:CPY OP2 is (op=0xC0 | op=0xC4 | op=0xCC) ... & OP2 +{ + local op1 = OP2; + local tmp = Y - op1; + resultFlags(tmp); + C = (Y >= op1); +} + +:DEC OP2 is (op=0xC6 | op=0xCE | op=0xD6 | op=0xDE) ... & OP2 +{ + local tmp = OP2 - 1; + OP2 = tmp; + resultFlags(tmp); +} + +:DEX is op=0xCA +{ + X = X - 1; + resultFlags(X); +} + + +:DEY is op=0x88 +{ + Y = Y -1; + resultFlags(Y); +} + +:EOR OP1 is (cc=1 & aaa=2) ... & OP1 +{ + local op1 = OP1; + A = A ^ op1; + resultFlags(A); +} + +:INC OP2 is (op=0xE6 | op=0xEE | op=0xF6 | op=0xFE) ... & OP2 +{ + local tmp = OP2 + 1; + OP2 = tmp; + resultFlags(tmp); +} + +:INY is op=0xC8 +{ + Y = Y + 1; + resultFlags(Y); +} + +:INX is op=0xE8 +{ + X = X + 1; + resultFlags(X); +} + +:JMP ADDR16 is (op=0x4C); ADDR16 +{ + goto ADDR16; +} + +:JMP ADDRI is (op=0x6c); ADDRI +{ + goto [ADDRI]; +} + +:JSR ADDR16 is op=0x20; ADDR16 +{ + *:2 (SP-1) = inst_next; + SP=SP-2; + call ADDR16; +} + +:LDA OP1 is (cc=1 & aaa=5) ... & OP1 +{ + A = OP1; + resultFlags(A); +} + +:LDY OP2 is (op=0xA0 | op=0xA4 | op=0xAC | op=0xB4 | op=0xBC) ... & OP2 +{ + Y = OP2; + resultFlags(Y); +} + +:LDX OP2LD is (op=0xA2 | op=0xA6 | op=0xAE | op=0xB6 | op=0xBE) ... & OP2LD +{ + X = OP2LD; + resultFlags(X); +} + +:LSR OP2 is (op=0x46 | op=0x4A | op=0x4E | op=0x56 | op=0x5E) ... & OP2 +{ + local tmp = OP2; + C = tmp & 1; + tmp = tmp >> 1; + OP2 = tmp; + Z = (tmp == 0); + N = 0; +} + +:NOP is op=0xEA +{ +} + +:ORA OP1 is (cc=1 & aaa=0) ... & OP1 +{ + A = A | OP1; + resultFlags(A); +} + +:PHP is op=0x8 +{ + pushSR(); +} + +:PLP is op=0x28 +{ + popSR(); +} + +:PHA is op=0x48 +{ + *:1 (SP) = A; + SP = SP - 1; +} + +:PLA is op=0x68 +{ + SP = SP + 1; + A = *:1 (SP); + resultFlags(A); +} + +:ROL OP2 is (op=0x26 | op=0x2A | op=0x2E | op=0x36 | op=0x3E) ... & OP2 +{ + local tmpC = C; + local op2 = OP2; + C = op2 >> 7; + local result = op2 << 1; + result = result | tmpC; + OP2 = result; + resultFlags(result); +} + +:ROR OP2 is (op=0x66 | op=0x6A | op=0x6E | op=0x76 | op=0x7E) ... & OP2 +{ + local tmpC = C << 7; + local tmp = OP2; + C = tmp & 1; + tmp = tmp >> 1; + tmp = tmp | tmpC; + OP2 = tmp; + resultFlags(tmp); +} + +:RTI is op=0x40 +{ + popSR(); + + SP = SP+1; + tmp:2 = *:2 SP; + SP = SP+1; + + return [tmp]; +} + +:RTS is op=0x60 +{ + SP = SP+1; + tmp:2 = *:2 SP; + SP = SP+1; + + return [tmp]; +} + +:SBC OP1 is (cc=1 & aaa=7) ... & OP1 +{ + local op1 = OP1; + local result = A - op1 - !C; + + subtraction_flags1(A, op1, result); + A = result; + + # resultFlags(tmp); + # C = ((A <= op1) * C) | (A < op1); + # A = tmp; +} + +:SEC is op=0x38 +{ + C = 1; +} + +:SED is op=0xF8 +{ + D = 1; +} + +:SEI is op=0x78 +{ + I = 1; +} + +:STA OP1 is (cc=1 & aaa=4) ... & OP1 +{ + OP1 = A; +} + +:STX OP2ST is (op=0x86 | op=0x8E | op=0x96) ... & OP2ST +{ + OP2ST = X; +} + +:STY OP2 is (op=0x84 | op=0x8C | op=0x94) ... & OP2 +{ + OP2 = Y; +} + +:TAX is op=0xAA +{ + X = A; + resultFlags(X); +} + +:TAY is op=0xA8 +{ + Y = A; + resultFlags(Y); +} + +:TSX is op=0xBA +{ + X = S; +} + +:TXA is op=0x8A +{ + A = X; + resultFlags(A); +} + +:TXS is op=0x9A +{ + S = X; +} + +:TYA is op=0x98 +{ + A = Y; + resultFlags(A); +} diff --git a/python/icicle/Ghidra/Processors/6502/data/languages/65c02.slaspec b/python/icicle/Ghidra/Processors/6502/data/languages/65c02.slaspec new file mode 100644 index 0000000..adb21ee --- /dev/null +++ b/python/icicle/Ghidra/Processors/6502/data/languages/65c02.slaspec @@ -0,0 +1,222 @@ +@include "6502.slaspec" + +define token bitopbyte (8) + bitop = (0,7) + + action = (7,7) + bitindex = (4,6) dec + optype = (0,3) +; + +define token testopbyte (8) + top = (0, 7) + taaa = (5, 7) + td = (4, 4) + tbb = (2, 3) + tcc = (0, 1) +; + +################################################################ + +# Zero Page Indirect +ZIOP: (imm8) is bbb=4; imm8 { addr:2 = imm8; tmp:2 = *:2 addr; export *:1 tmp; } + +OPTB: imm8 is tbb=1; imm8 { export *:1 imm8; } +OPTB: imm16 is tbb=3; imm16 { export *:1 imm16; } + +# Absolute Indexed Indirect +ADDRIX: (imm16,X) is X; imm16 { addr:2 = imm16 + zext(X); tmp:2 = *:2 addr; export tmp; } + +# Instructions + +:ADC ZIOP is (cc=2 & aaa=3) ... & ZIOP +{ + local op1 = ZIOP; + local tmpC = C; + + C = carry(A, op1); + A = A + op1 + tmpC; + resultFlags(A); + V = C; +} + +:AND ZIOP is (cc=2 & aaa=1) ... & ZIOP +{ + A = A & ZIOP; + resultFlags(A); +} + +:BBR "#"bitindex, imm8, REL is (action=0 & optype=0xF) & bitindex ; imm8 ; REL { + local ptr:2 = imm8; + local value:1 = *:1 ptr; + local jump = (value & (1 << bitindex)) == 0; + if (jump) goto REL; +} + +:BBS "#"bitindex, imm8, REL is (action=1 & optype=0xF) & bitindex ; imm8 ; REL { + local ptr:2 = imm8; + local value:1 = *:1 ptr; + local jump = (value & (1 << bitindex)) != 0; + if (jump) goto REL; +} + +:BIT "#"imm8 is op=0x89; imm8 +{ + local value:1 = imm8; + N = (value & 0x80) == 0x80; + V = (value & 0x40) == 0x40; + value = A & value; + Z = (value == 0); +} + +:BIT OP2 is (op=0x34 | op=0x3C) ... & OP2 +{ + N = (OP2 & 0x80) == 0x80; + V = (OP2 & 0x40) == 0x40; + local value = A & OP2; + Z = (value == 0); +} + +:BRA REL is op=0x80; REL +{ + goto REL; +} + +:CMP ZIOP is (cc=2 & aaa=6) ... & ZIOP +{ + local op1 = ZIOP; + local tmp = A - op1; + resultFlags(tmp); + C = (A >= op1); +} + +:DEC A is op=0x3A & A +{ + local tmp = A - 1; + A = tmp; + resultFlags(tmp); +} + +:EOR ZIOP is (cc=2 & aaa=2) ... & ZIOP +{ + local op1 = ZIOP; + A = A ^ op1; + resultFlags(A); +} + +:INC A is op=0x1A & A +{ + A = A + 1; + resultFlags(A); +} + +:JMP ADDRIX is (op=0x7C); ADDRIX +{ + goto [ADDRIX]; +} + +:LDA ZIOP is (cc=2 & aaa=5) ... & ZIOP +{ + A = ZIOP; + resultFlags(A); +} + +:ORA ZIOP is (cc=2 & aaa=0) ... & ZIOP +{ + A = A | ZIOP; + resultFlags(A); +} + +:PHX is op=0xDA +{ + *:1 (SP) = X; + SP = SP - 1; +} + +:PLX is op=0xFA +{ + SP = SP + 1; + X = *:1 (SP); + resultFlags(X); +} + +:PHY is op=0x5A +{ + *:1 (SP) = Y; + SP = SP - 1; +} + +:PLY is op=0x7A +{ + SP = SP + 1; + Y = *:1 (SP); + resultFlags(Y); +} + +:RMB "#"bitindex, imm8 is (action=0 & optype=7) & bitindex ; imm8 { + local ptr:2 = imm8; + local value:1 = *:1 ptr; + value = value & ~(1 << bitindex); + *:1 ptr = value; +} + +:SBC ZIOP is (cc=2 & aaa=7) ... & ZIOP +{ + local op1 = ZIOP; + local result = A - op1 - !C; + + subtraction_flags1(A, op1, result); + A = result; +} + +:SMB "#"bitindex, imm8 is (action=1 & optype=7) & bitindex ; imm8 { + local ptr:2 = imm8; + local value:1 = *:1 ptr; + value = value | (1 << bitindex); + *:1 ptr = value; +} + +:STA ZIOP is (cc=2 & aaa=4) ... & ZIOP +{ + ZIOP = A; +} + +:STZ imm8 is op=0x64 ; imm8 +{ + local tmp:2 = imm8; + *:1 tmp = 0; +} + +:STZ imm8,X is op=0x74 & X ; imm8 +{ + local tmp:2 = zext(imm8 + X); + *:1 tmp = 0; +} + +:STZ imm16 is op=0x9C ; imm16 +{ + local tmp:2 = imm16; + *:1 tmp = 0; +} + +:STZ imm16,X is op=0x9E & X ; imm16 +{ + local tmp:2 = imm16 + zext(X); + *:1 tmp = 0; +} + +:TRB OPTB is (tcc=0 & taaa=0 & td=1) ... & OPTB +{ + local op1 = OPTB; + local result = (~A) & op1; + OPTB = result; + Z = result == 0; +} + +:TSB OPTB is (tcc=0 & taaa=0 & td=0) ... & OPTB +{ + local op1 = OPTB; + local result = A | op1; + OPTB = result; + Z = result == 0; +} diff --git a/python/icicle/Ghidra/Processors/68000/data/languages/68000.cspec b/python/icicle/Ghidra/Processors/68000/data/languages/68000.cspec new file mode 100644 index 0000000..fe7c760 --- /dev/null +++ b/python/icicle/Ghidra/Processors/68000/data/languages/68000.cspec @@ -0,0 +1,69 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/68000/data/languages/68000.dwarf b/python/icicle/Ghidra/Processors/68000/data/languages/68000.dwarf new file mode 100644 index 0000000..9fcce0b --- /dev/null +++ b/python/icicle/Ghidra/Processors/68000/data/languages/68000.dwarf @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/68000/data/languages/68000.ldefs b/python/icicle/Ghidra/Processors/68000/data/languages/68000.ldefs new file mode 100644 index 0000000..e065db0 --- /dev/null +++ b/python/icicle/Ghidra/Processors/68000/data/languages/68000.ldefs @@ -0,0 +1,67 @@ + + + + + Motorola 32-bit 68040 + + + + + + + + + Motorola 32-bit 68030 + + + + + + + Motorola 32-bit 68020 + + + + + + + + + Motorola 32-bit Coldfire + + + + + diff --git a/python/icicle/Ghidra/Processors/68000/data/languages/68000.opinion b/python/icicle/Ghidra/Processors/68000/data/languages/68000.opinion new file mode 100644 index 0000000..5ead96f --- /dev/null +++ b/python/icicle/Ghidra/Processors/68000/data/languages/68000.opinion @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/68000/data/languages/68000.pspec b/python/icicle/Ghidra/Processors/68000/data/languages/68000.pspec new file mode 100644 index 0000000..14df2cb --- /dev/null +++ b/python/icicle/Ghidra/Processors/68000/data/languages/68000.pspec @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/68000/data/languages/68000.sinc b/python/icicle/Ghidra/Processors/68000/data/languages/68000.sinc new file mode 100644 index 0000000..ff97468 --- /dev/null +++ b/python/icicle/Ghidra/Processors/68000/data/languages/68000.sinc @@ -0,0 +1,2954 @@ +# SLA specification for Motorola 68000 series + +define endian=big; +define alignment=2; + +define space ram type=ram_space size=4 default; +define space register type=register_space size=4; + +define register offset=0 size=4 [ D0 D1 D2 D3 D4 D5 D6 D7 ]; # Data registers +define register offset=0 size=2 [ D0u D0w D1u D1w D2u D2w D3u D3w D4u D4w D5u D5w D6u D6w D7u D7w]; +define register offset=0 size=1 [ _ _ _ D0b _ _ _ D1b _ _ _ D2b _ _ _ D3b _ _ _ D4b _ _ _ D5b _ _ _ D6b _ _ _ D7b ]; +define register offset=0x20 size=4 [ A0 A1 A2 A3 A4 A5 A6 SP ]; # Address registers +define register offset=0x20 size=2 [ A0u A0w A1u A1w A2u A2w A3u A3w A4u A4w A5u A5w A6u A6w A7u A7w]; +define register offset=0x20 size=1 [ _ _ _ A0b _ _ _ A1b _ _ _ A2b _ _ _ A3b _ _ _ A4b _ _ _ A5b _ _ _ A6b _ _ _ A7b ]; +define register offset=0x40 size=1 [ TF SVF IPL XF NF ZF VF CF ]; # Condition flags +define register offset=0x50 size=4 PC; # Program counter register + +# Floating point registers are 80 bits internally, but are 96 bits to/from memory. +# Note that 12-byte float needed to be added to FloatFormat.java +# Also note that the 96 bit format is not really IEEE, because it gets mapped to 80 bits. +define register offset=0x700 size=12 [ FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 ]; + +define register offset=0xb0 size=4 [ FPCR FPSR FPIAR ]; +define register offset=0xe0 size=8 [ CRP ]; +define register offset=0x100 size=4 [ ISP MSP VBR CACR CAAR AC0 AC1 USP TT0 TT1 ]; +define register offset=0x140 size=4 [ SFC DFC TC ITT0 ITT1 DTT0 DTT1 MMUSR URP SRP PCR CAC ]; +define register offset=0x180 size=4 [ BUSCR MBB RAMBAR0 RAMBAR1 ]; +define register offset=0x200 size=2 [ SR ACUSR ]; +# NOTE that SR overlaps XF, ZF, VF, CF +# NOTE that A7 refers to USP, ISP, or MSP depending on privilege level + + +define register offset=0x300 size=4 [ glbdenom movemptr ]; +define register offset=0x400 size=4 [ contextreg ]; + +@ifdef COLDFIRE +# TODO: add a pure MAC variant, for now, just do EMAC +define register offset=0x500 size=4 [ MACSR MASK ]; +define register offset=0x600 size=4 [ EMACSR ACC0 ACC1 ACC2 ACC3 ACCext01 ACCext23 EMASK ]; +@endif + +#TODO: These mode constraints do not constrain the various mode=7 sub-modes identified by regan bits +@define MEM_ALTER_ADDR_MODES "(op4=1 | op5=1)" # Memory alterable addressing modes (All modes except mode=1 and mode=0) +@define DAT_ALTER_ADDR_MODES "(mode=0 | op4=1 | op5=1)" # Data alterable addressing modes (All modes except mode=1) +@define DAT_DIR_CTL_ADDR_MODES "(mode=0 | mode=2 | mode=5 | mode=6 | mode=7)" # Data direct and control addressing modes +@define CTL_ADDR_MODES "(mode=2 | mode=5 | mode=6 | mode=7)" # Control addressing modes +@define POSTINC_CTL_ADDR_MODES "(mode=2 | mode=3 | mode=5 | mode=6 | mode=7)" # Control addressing modes +@define PREDEC_CTL_ADDR_MODES "(mode=2 | mode=4 | mode=5 | mode=6 | mode=7)" # Control addressing modes + +#TODO: These mode constraints do not constrain the various mode=7 sub-modes identified by regan bits +@define MEM_ALTER_ADDR_MODES2 "(op7=1 | op8=1)" # Memory alterable addressing modes (All modes except mode=1 and mode=0) +@define DAT_ALTER_ADDR_MODES2 "(mode2=0 | op7=1 | op8=1)" # Data alterable addressing modes (All modes except mode=1) +@define DAT_DIR_CTL_ADDR_MODES2 "(mode2=0 | mode2=2 | mode2=5 | mode2=6 | mode=7)" # Data direct and control addressing modes +@define CTL_ADDR_MODES2 "(mode2=2 | mode2=5 | mode2=6 | mode2=7)" # Control addressing modes + +# Floating-point condition code bits within FPSR +@define N_FP "FPSR[27,1]" +@define Z_FP "FPSR[26,1]" +@define I_FP "FPSR[25,1]" +@define NAN_FP "FPSR[24,1]" + +define token instr (16) + mode = (3,5) + mode2 = (6,8) + regdn = (0,2) + regdnw = (0,2) + regdnb = (0,2) + regan = (0,2) + reganw = (0,2) + reganb = (0,2) + rmbit = (3,3) + reg9dn = (9,11) + reg9dnw = (9,11) + reg9dnb = (9,11) + reg9an = (9,11) + copid = (9,11) + op = (12,15) + opbig = (8,15) + op01 = (0,1) + op02 = (0,2) + op03 = (0,3) + op08 = (0,8) + op015 = (0,15) + op34 = (3,4) + op35 = (3,5) + op37 = (3,7) + op38 = (3,8) + op45 = (4,5) + op48 = (4,8) + op69 = (6,9) + op68 = (6,8) + op67 = (6,7) + op1315 = (13,15) + op4 = (4,4) + op5 = (5,5) + op7 = (7,7) + op8 = (8,8) + op11 = (11,11) + quick = (9,11) + op811 = (8,11) + copcc1 = (0,5) + d8base = (0,7) signed +@ifdef COLDFIRE + reg03y = (0,3) + reg03ywu = (0,3) + reg03ywl = (0,3) + op47 = (4,7) + op611 = (6,11) + op6 = (6,6) + op0910 = (9,10) + acclsb = (7,7) + d911 = (9,11) + reg315 = (3, 15) + reg9dnu = (9,11) + reg9dnl = (9,11) + reg9anu = (9,11) + reg9anl = (9,11) +@endif +; + +define token extword (16) + opx015 = (0,15) + opx1315= (13,15) + opx515 = (5,15) + da = (15,15) + regda = (12,15) + regxdn = (12,14) + regxdnw = (12,14) + regxan = (12,14) + regxanw = (12,14) + wl = (11,11) + mregn = (10,12) + rwx = (9,9) + scale = (9,10) + ext_911 = (9,11) + bigopx = (8,15) + fbit = (8,8) + regdu = (6,8) + regduw = (6,8) + regdub = (6,8) + fcmask = (5,7) + aregx = (5,7) + ext_35 = (3,5) + regdc = (0,2) + regdcw = (0,2) + regdcb = (0,2) + d8 = (0,7) signed + bs = (7,7) + IS = (6,6) + bdsize = (4,5) + iis = (0,2) + odsize = (0,1) + copcc2 = (0,5) + fc4 = (4,4) + fc3 = (3,3) + fc03 = (0,3) + fc02 = (0,2) + ctl = (0,11) +@ifdef COLDFIRE + sfact = (9,10) + accmsb = (4,4) + reg03yu = (0,3) + reg03yl = (0,3) + ereg03y = (0,3) + accw = (2,3) + reg12x = (12,15) + reg12xwu = (12,15) + reg12xwl = (12,15) +@endif +; + +define token extword2 (16) + regda2 = (12,15) + ext2_911 = (9,11) + ext2_35 = (3,5) + regdu2 = (6,8) + regdu2w = (6,8) + regdc2 = (0,2) + regdc2w = (0,2) +; + +define token fpword (16) + fop = (12,15) + fcopid = (9,11) + fword = (0,15) + fcnt = (0,2) + f1515 = (15,15) + f1415 = (14,15) + f1315 = (13,15) + f1015 = (10,15) + f0009 = (0,9) + f0008 = (0,8) + f0808 = (8,8) + f0810 = (8,10) + f0707 = (7,7) + f0609 = (6,9) + f0608 = (6,8) + f0615 = (6,15) + f0308 = (3,8) + f0306 = (3,6) + fmode = (0,2) + frm = (14,14) + f1313 = (13,13) + fsrc = (10,12) # attached to FP registers + f1012 = (10,12) + f10 = (10,10) + f11 = (11,11) + f12 = (12,12) + fdcos = (0,2) # attached to FP registers + fdsin = (7,9) # attached to FP registers + ffmt = (10,12) + fdst = (7,9) # attached to FP registers + fdr = (13,13) + fsize = (6,6) + fcode = (0,5) + fopmode = (0,6) + fkfactor = (0,6) + fkfacreg = (4,6) + fromoffset = (0,6) + flmode_t = (11,11) + flmode_m = (12,12) + fldynreg = (4,6) + freglist = (0,7) + frlist0 = (0,0) + frlist1 = (1,1) + frlist2 = (2,2) + frlist3 = (3,3) + frlist4 = (4,4) + frlist5 = (5,5) + frlist6 = (6,6) + frlist7 = (7,7) +; + +define token disp16 (16) d16 = (0,15) signed; +define token disp32 (32) d32 = (0,31) signed; +define token disp64 (64) + signD = (63,63) + exponentD = (52,62) + mantissaD = (0,51) + d64 = (0,63) signed +; +define token disp96X_1 (32) + signX = (31,31) + exponentX = (16,30) +; +define token disp96X_2 (64) + expintbitX = (63,63) + mantissaX = (0,62) +; +define token bdisp16 (16) bd16 = (0,15) signed; +define token bdisp32 (32) bd32 = (0,31) signed; +define token odisp16 (16) od16 = (0,15) signed; +define token odisp32 (32) od32 = (0,31) signed; +define token fldparm (16) + flddo=(11,11) + fldoffdat=(6,10) + fldoffreg=(6,8) + flddw=(5,5) + fldwddat=(0,4) + fldwdreg=(0,2) + f_reg=(12,14) + regdr=(0,2) + regdq=(12,14) + divsgn=(11,11) + divsz=(10,10) + mvm0 = (0,0) # Bits in the register list mask for movem + mvm1 = (1,1) + mvm2 = (2,2) + mvm3 = (3,3) + mvm4 = (4,4) + mvm5 = (5,5) + mvm6 = (6,6) + mvm7 = (7,7) + mvm8 = (8,8) + mvm9 = (9,9) + mvm10 = (10,10) + mvm11 = (11,11) + mvm12 = (12,12) + mvm13 = (13,13) + mvm14 = (14,14) + mvm15 = (15,15) +; + +# Context bits for getting base register bits into the addressing mode +define context contextreg + eanum = (0,0) # Which effective address is this (the regf's or the regs's) + pcmode = (1,1) # is this a PC relative mode + regfan = (2,4) # saved base register for first effective address + regtfan = (2,4) + savmod1 = (5,7) + savmod2 = (8,10) # Mode for the second effective address + regsdn = (11,13) + regsdnw = (11,13) + regsdnb = (11,13) + regsan = (11,13) + regtsan = (11,13) + regsanw = (11,13) + regsanb = (11,13) + extGUARD = (14,14) # guard for saving off modes before starting instructions +; + +attach variables [ regdn regxdn reg9dn regdr regdq regsdn regdu regdc regdu2 regdc2 ] [ D0 D1 D2 D3 D4 D5 D6 D7 ]; +attach variables [ fldoffreg fldwdreg f_reg fcnt fkfacreg fldynreg ] [ D0 D1 D2 D3 D4 D5 D6 D7 ]; +attach variables [ regdnw regxdnw reg9dnw regsdnw regduw regdcw regdu2w regdc2w ] [ D0w D1w D2w D3w D4w D5w D6w D7w ]; +attach variables [ regdnb reg9dnb regsdnb regdub regdcb ] [ D0b D1b D2b D3b D4b D5b D6b D7b ]; +attach variables [ regda regda2 ] [ D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 SP ]; +attach variables [ regan regxan reg9an regfan regsan aregx ] [ A0 A1 A2 A3 A4 A5 A6 SP ]; +attach variables [ reganw regxanw regsanw ] [ A0w A1w A2w A3w A4w A5w A6w A7w ]; +attach variables [ reganb regsanb ] [ A0b A1b A2b A3b A4b A5b A6b A7b ]; + +attach variables [ fsrc fdst fdcos fdsin ] [ FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 ]; + +@ifdef COLDFIRE +attach variables [ reg03y ereg03y reg12x ] [ D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 SP ]; +attach variables [reg03ywu reg12xwu reg03yu ] [ D0u D1u D2u D3u D4u D5u D6u D7u A0u A1u A2u A3u A4u A5u A6u A7u ]; +attach variables [reg03ywl reg12xwl reg03yl ] [ D0w D1w D2w D3w D4w D5w D6w D7w A0w A1w A2w A3w A4w A5w A6w A7w ]; +attach variables [reg9dnu] [ D0u D1u D2u D3u D4u D5u D6u D7u ]; +attach variables [reg9dnl] [ D0w D1w D2w D3w D4w D5w D6w D7w ]; +attach variables [reg9anu] [ A0u A1u A2u A3u A4u A5u A6u A7u ]; +attach variables [reg9anl] [ A0w A1w A2w A3w A4w A5w A6w A7w ]; +attach variables [accw] [ACC0 ACC1 ACC2 ACC3]; + +attach values d911 [ -1 1 2 3 4 5 6 7 ]; +@endif + +attach values scale [ 1 2 4 8 ]; +attach values quick [ 8 1 2 3 4 5 6 7 ]; + +define pcodeop kfactor; +define pcodeop ftrap; +define pcodeop __m68k_trap; +define pcodeop __m68k_trapv; +define pcodeop reset; +define pcodeop saveFPUStateFrame; +define pcodeop restoreFPUStateFrame; +define pcodeop pushInvalidateCaches; + +define pcodeop bcdAdjust; + +define pcodeop sin; +define pcodeop cos; +define pcodeop tan; +define pcodeop asin; +define pcodeop acos; +define pcodeop atan; +define pcodeop sinh; +define pcodeop cosh; +define pcodeop tanh; + +ea_index: regxan*scale is da=1 & wl=1 & regxan & scale { tmp:4 = regxan*scale; export tmp; } +ea_index: regxanw*scale is da=1 & wl=0 & regxanw & scale { tmp:4 = sext(regxanw)*scale; export tmp; } +ea_index: regxdn*scale is da=0 & wl=1 & regxdn & scale { tmp:4 = regxdn*scale; export tmp; } +ea_index: regxdnw*scale is da=0 & wl=0 & regxdnw & scale { tmp:4 = sext(regxdnw)*scale; export tmp; } + + +breg: regfan is eanum=0 & regfan { export regfan; } +breg: regsan is eanum=1 & regsan { export regsan; } +#breg: PC is pcmode=1 & eanum & PC { tmp:4 = inst_start; } + +fl_breg: "-" is bs=1 { export 0:4; } +fl_breg: "ZPC" is bs=1 & pcmode=1 { export 0:4; } +fl_breg: breg is bs=0 & pcmode=0 & breg { export breg; } +fl_breg: PC is PC & bs=0 & pcmode=1 { tmp:4 = inst_start + 2; export tmp; } + +# shift amount parameter +cntreg: reg9dn is reg9dn & op5=1 { local tmp = reg9dn & 63; export tmp; } +cntreg: "#"^quick is quick & op5=0 { export *[const]:4 quick; } + +# Extension word forms of the effective address + # 8-bit displacement (brief extension) +extw: d8,breg,ea_index is breg; ea_index & d8 & fbit=0 { local tmp = breg+d8+ea_index; export tmp; } +extw: rela,PC,ea_index is pcmode=1 & PC; ea_index & d8 & fbit=0 + [ rela = inst_start+d8+2; ] + { tmp:4 = rela; tmp = tmp+ea_index; export tmp; } + # Base displacement (indexed) +extw: fl_breg,ea_index is ea_index & fl_breg & fbit=1 & bdsize=1 & IS=0 & iis=0 { local tmp = fl_breg+ea_index; export tmp; } +extw: bd16,fl_breg,ea_index is ea_index & fl_breg & fbit=1 & bdsize=2 & IS=0 & iis=0; bd16 { local tmp = fl_breg+ea_index+bd16; export tmp; } +extw: bd32,fl_breg,ea_index is ea_index & fl_breg & fbit=1 & bdsize=3 & IS=0 & iis=0; bd32 { local tmp = fl_breg+ea_index+bd32; export tmp; } + # Memory Indirect Postindexed Mode +extw: [fl_breg],ea_index is ea_index & fl_breg & fbit=1 & bdsize=1 & IS=0 & iis=1 { local tmp = *:4 fl_breg + ea_index; export tmp; } +extw: [bd16,fl_breg],ea_index is ea_index & fl_breg & fbit=1 & bdsize=2 & IS=0 & iis=1; bd16 { local tmp = *:4 (fl_breg+bd16) + ea_index; export tmp; } +extw: [bd32,fl_breg],ea_index is ea_index & fl_breg & fbit=1 & bdsize=3 & IS=0 & iis=1; bd32 { local tmp = *:4 (fl_breg+bd32) + ea_index; export tmp; } +extw: [fl_breg],ea_index,od16 is ea_index & fl_breg & fbit=1 & bdsize=1 & IS=0 & iis=2; od16 { local tmp = *:4 fl_breg + ea_index + od16; export tmp; } +extw: [bd16,fl_breg],ea_index,od16 is ea_index & fl_breg & fbit=1 & bdsize=2 & IS=0 & iis=2; bd16; od16 { local tmp = *:4 (fl_breg+bd16) + ea_index + od16; export tmp; } +extw: [bd32,fl_breg],ea_index,od16 is ea_index & fl_breg & fbit=1 & bdsize=3 & IS=0 & iis=2; bd32; od16 { local tmp = *:4 (fl_breg+bd32) + ea_index + od16; export tmp; } +extw: [fl_breg],ea_index,od32 is ea_index & fl_breg & fbit=1 & bdsize=1 & IS=0 & iis=3; od32 { local tmp = *:4 fl_breg + ea_index + od32; export tmp; } +extw: [bd16,fl_breg],ea_index,od32 is ea_index & fl_breg & fbit=1 & bdsize=2 & IS=0 & iis=3; bd16; od32 { local tmp = *:4 (fl_breg+bd16) + ea_index + od32; export tmp; } +extw: [bd32,fl_breg],ea_index,od32 is ea_index & fl_breg & fbit=1 & bdsize=3 & IS=0 & iis=3; bd32; od32 { local tmp = *:4 (fl_breg+bd32) + ea_index + od32; export tmp; } + # Memory Indirect Preindexed Mode +extw: [fl_breg,ea_index] is ea_index & fl_breg & fbit=1 & bdsize=1 & IS=0 & iis=5 { local tmp = *:4 (fl_breg+ea_index); export tmp; } +extw: [bd16,fl_breg,ea_index] is ea_index & fl_breg & fbit=1 & bdsize=2 & IS=0 & iis=5; bd16 { local tmp = *:4 (fl_breg+ea_index+bd16); export tmp; } +extw: [bd32,fl_breg,ea_index] is ea_index & fl_breg & fbit=1 & bdsize=3 & IS=0 & iis=5; bd32 { local tmp = *:4 (fl_breg+ea_index+bd32); export tmp; } +extw: [fl_breg,ea_index],od16 is ea_index & fl_breg & fbit=1 & bdsize=1 & IS=0 & iis=6; od16 { local tmp = *:4 (fl_breg+ea_index) + od16; export tmp; } +extw: [bd16,fl_breg,ea_index],od16 is ea_index & fl_breg & fbit=1 & bdsize=2 & IS=0 & iis=6; bd16; od16 { local tmp = *:4 (fl_breg+ea_index+bd16) + od16; export tmp; } +extw: [bd32,fl_breg,ea_index],od16 is ea_index & fl_breg & fbit=1 & bdsize=3 & IS=0 & iis=6; bd32; od16 { local tmp = *:4 (fl_breg+ea_index+bd32) + od16; export tmp; } +extw: [fl_breg,ea_index],od32 is ea_index & fl_breg & fbit=1 & bdsize=1 & IS=0 & iis=7; od32 { local tmp = *:4 (fl_breg+ea_index) + od32; export tmp; } +extw: [bd16,fl_breg,ea_index],od32 is ea_index & fl_breg & fbit=1 & bdsize=2 & IS=0 & iis=7; bd16; od32 { local tmp = *:4 (fl_breg+ea_index+bd16) + od32; export tmp; } +extw: [bd32,fl_breg,ea_index],od32 is ea_index & fl_breg & fbit=1 & bdsize=3 & IS=0 & iis=7; bd32; od32 { local tmp = *:4 (fl_breg+ea_index+bd32) + od32; export tmp; } + # Base displacement +extw: fl_breg is fl_breg & fbit=1 & bdsize=1 & IS=1 & iis=0 { export fl_breg; } +extw: bd16,fl_breg is fl_breg & fbit=1 & bdsize=2 & IS=1 & iis=0; bd16 { local tmp = fl_breg+bd16; export tmp; } +extw: bd32,fl_breg is fl_breg & fbit=1 & bdsize=3 & IS=1 & iis=0; bd32 { local tmp = fl_breg+bd32; export tmp; } + # Memory Indirect +extw: [fl_breg] is fl_breg & fbit=1 & bdsize=1 & IS=1 & iis=1 { local tmp = *:4 fl_breg; export tmp; } +extw: [bd16,fl_breg] is fl_breg & fbit=1 & bdsize=2 & IS=1 & iis=1; bd16 { local tmp = *:4 (fl_breg+bd16); export tmp; } +extw: [bd32,fl_breg] is fl_breg & fbit=1 & bdsize=3 & IS=1 & iis=1; bd32 { local tmp = *:4 (fl_breg+bd32); export tmp; } +extw: [fl_breg],od16 is fl_breg & fbit=1 & bdsize=1 & IS=1 & iis=2; od16 { local tmp = *:4 fl_breg + od16; export tmp; } +extw: [bd16,fl_breg],od16 is fl_breg & fbit=1 & bdsize=2 & IS=1 & iis=2; bd16; od16 { local tmp = *:4 (fl_breg+bd16) + od16; export tmp; } +extw: [bd32,fl_breg],od16 is fl_breg & fbit=1 & bdsize=3 & IS=1 & iis=2; bd32; od16 { local tmp = *:4 (fl_breg+bd32) + od16; export tmp; } +extw: [fl_breg],od32 is fl_breg & fbit=1 & bdsize=1 & IS=1 & iis=3; od32 { local tmp = *:4 fl_breg + od32; export tmp; } +extw: [bd16,fl_breg],od32 is fl_breg & fbit=1 & bdsize=2 & IS=1 & iis=3; bd16; od32 { local tmp = *:4 (fl_breg+bd16) + od32; export tmp; } +extw: [bd32,fl_breg],od32 is fl_breg & fbit=1 & bdsize=3 & IS=1 & iis=3; bd32; od32 { local tmp = *:4 (fl_breg+bd32) + od32; export tmp; } + + +# The main effective address table + # size=long +eal: regdn is mode=0 & regdn { export regdn; } +eal: regan is mode=1 & regan { export regan; } +eal: (regan) is mode=2 & regan { export *:4 regan; } +eal: (regan)+ is mode=3 & regan { local tmp = regan; regan = regan + 4; export *:4 tmp; } +eal: -(regan) is mode=4 & regan { regan = regan - 4; export *:4 regan; } +eal: (d16,regan) is mode=5 & regan; d16 { local tmp = regan + d16; export *:4 tmp; } +eal: (extw) is mode=6 & regan; extw [ regtfan = regan; pcmode = 0; ] { build extw; export *:4 extw; } +eal: (d16,PC) is PC & mode=7 & regan=2; d16 { tmp:4 = inst_start + 2 + d16; export *:4 tmp; } +eal: (extw) is mode=7 & regan=3; extw [ pcmode=1; ] { build extw; export *:4 extw; } +eal: (d16)".w" is mode=7 & regan=0; d16 { export *:4 d16; } +eal: (d32)".l" is mode=7 & regan=1; d32 { export *:4 d32; } +eal: "#"^d32 is mode=7 & regan=4; d32 { export *[const]:4 d32; } + # size=word +eaw: regdnw is mode=0 & regdnw { export regdnw; } +eaw: reganw is mode=1 & reganw { export reganw; } +eaw: (regan) is mode=2 & regan { export *:2 regan; } +eaw: (regan)+ is mode=3 & regan { local tmp = regan; regan = regan + 2; export *:2 tmp; } +eaw: -(regan) is mode=4 & regan { regan = regan - 2; export *:2 regan; } +eaw: (d16,regan) is mode=5 & regan; d16 { local tmp = regan + d16; export *:2 tmp; } +eaw: (extw) is mode=6 & regan; extw [ pcmode=0; regtfan=regan; ] { build extw; export *:2 extw; } +eaw: (d16,PC) is PC & mode=7 & regan=2; d16 { tmp:4 = inst_start + 2 + d16; export *:2 tmp; } +eaw: (extw) is mode=7 & regan=3; extw [ pcmode=1; ] { build extw; export *:2 extw; } +eaw: (d16)".w" is mode=7 & regan=0; d16 { export *:2 d16; } +eaw: (d32)".l" is mode=7 & regan=1; d32 { export *:2 d32; } +eaw: "#"^d16 is mode=7 & regan=4; d16 { export *[const]:2 d16; } + # size=byte +eab: regdnb is mode=0 & regdnb { export regdnb; } +eab: reganb is mode=1 & reganb { export reganb; } +eab: (regan) is mode=2 & regan { export *:1 regan; } +eab: (regan)+ is mode=3 & regan & regan=7 { local tmp = regan; regan = regan + 2; export *:1 tmp; } +eab: (regan)+ is mode=3 & regan { local tmp = regan; regan = regan + 1; export *:1 tmp; } +eab: -(regan) is mode=4 & regan & regan=7 { regan = regan - 2; export *:1 regan; } +eab: -(regan) is mode=4 & regan { regan = regan - 1; export *:1 regan; } +eab: (d16,regan) is mode=5 & regan; d16 { local tmp = regan + d16; export *:1 tmp; } +eab: (extw) is mode=6 & regan; extw [ pcmode=0; regtfan=regan; ] { build extw; export *:1 extw; } +eab: (d16,PC) is PC & mode=7 & regan=2; d16 { tmp:4 = inst_start + 2 + d16; export *:1 tmp; } +eab: (extw) is mode=7 & regan=3; extw [ pcmode=1; ] { build extw; export *:1 extw; } +eab: (d16)".w" is mode=7 & regan=0; d16 { export *:1 d16; } +eab: (d32)".l" is mode=7 & regan=1; d32 { export *:1 d32; } +eab: "#"^d8 is mode=7 & regan=4; d8 { export *[const]:1 d8; } + +# Second effective address calculation for mov + +# NB- Extended-precsion are 12 bytes, so we need to increment or decrement the reg by 12 not 4 +# + # size=extend | packed (96-bit) + # The fmovem.x insn needs the movemptr to be set here +e2x: (regsan) is savmod2=2 & regsan { movemptr = regsan; export *:12 regsan; } +e2x: (regsan)+ is savmod2=3 & regsan { movemptr = regsan; local tmp = regsan; regsan = regsan + 12; export *:12 tmp; } +e2x: -(regsan) is savmod2=4 & regsan { movemptr = regsan; regsan = regsan - 12; export *:12 regsan; } +e2x: (d16,regsan) is savmod2=5 & regsan; d16 { local tmp = regsan + d16; movemptr = tmp; export *:12 tmp; } +e2x: (extw) is savmod2=6; extw [ pcmode=0; eanum=1; ] { build extw; movemptr = extw; export *:12 extw; } +e2x: (d16,PC) is PC & savmod2=7 & regsan=2; d16 { tmp:4 = inst_start + 2 + d16; movemptr = tmp; export *:12 tmp; } +e2x: (extw) is savmod2=7 & regsan=3; extw [ pcmode=1; ] { build extw; movemptr = extw; export *:12 extw; } +e2x: (d16)".w" is savmod2=7 & regsan=0; d16 { movemptr = d16; export *:12 d16; } +e2x: (d32)".l" is savmod2=7 & regsan=1; d32 { movemptr = d32; export *:12 d32; } +e2x: "#( -1E"^signX^" * 2E"^exp^"*1."^mantissaX) is savmod1=7 & regtfan=4; signX & exponentX; expintbitX & mantissaX + [exp=exponentX-0x3FFF;] + { movemptr = mantissaX; export *[const]:12 mantissaX; } # bug: doesn't construct a real, only exports the 64-bit mantissa + # size=quad (limited mode) + +# NB- Doubles are 8 bytes, so we need to increment or decrement the reg by 8 not 4 +# +e2d: (regsan) is savmod2=2 & regsan { export *:8 regsan; } +e2d: (regsan)+ is savmod2=3 & regsan { local tmp = regsan; regsan = regsan + 8; export *:8 tmp; } +e2d: -(regsan) is savmod2=4 & regsan { regsan = regsan - 8; export *:8 regsan; } +e2d: (d16,regsan) is savmod2=5 & regsan; d16 { local tmp = regsan + d16; export *:8 tmp; } +e2d: (extw) is savmod2=6; extw [ pcmode=0; eanum=1; ] { build extw; export *:8 extw; } +e2d: (d16,PC) is PC & savmod2=7 & regsan=2; d16 { tmp:4 = inst_start + 2 + d16; export *:8 tmp; } +e2d: (extw) is savmod2=7 & regsan=3; extw [ pcmode=1; ] { build extw; export *:8 extw; } +e2d: (d16)".w" is savmod2=7 & regsan=0; d16 { export *:8 d16; } +e2d: (d32)".l" is savmod2=7 & regsan=1; d32 { export *:8 d32; } +e2d: "#"^d64 is savmod2=7 & regsan=4; d64 { export *[const]:8 d64; } + + # size=long +e2l: regsdn is savmod2=0 & regsdn { export regsdn; } +e2l: regsan is savmod2=1 & regsan { export regsan; } +e2l: (regsan) is savmod2=2 & regsan { export *:4 regsan; } +e2l: (regsan)+ is savmod2=3 & regsan { local tmp = regsan; regsan = regsan + 4; export *:4 tmp; } +e2l: -(regsan) is savmod2=4 & regsan { regsan = regsan - 4; export *:4 regsan; } +e2l: (d16,regsan) is savmod2=5 & regsan; d16 { local tmp = regsan + d16; export *:4 tmp; } +e2l: (extw) is savmod2=6; extw [ pcmode=0; eanum=1; ] { build extw; export *:4 extw; } +e2l: (d16,PC) is PC & savmod2=7 & regsan=2; d16 { tmp:4 = inst_start + 2 + d16; export *:4 tmp; } +e2l: (extw) is savmod2=7 & regsan=3; extw [ pcmode=1; ] { build extw; export *:4 extw; } +e2l: (d16)".w" is savmod2=7 & regsan=0; d16 { export *:4 d16; } +e2l: (d32)".l" is savmod2=7 & regsan=1; d32 { export *:4 d32; } +e2l: "#"^d32 is savmod2=7 & regsan=4; d32 { export *[const]:4 d32; } + # size=word +e2w: regsdnw is savmod2=0 & regsdnw { export regsdnw; } +e2w: regsanw is savmod2=1 & regsanw { export regsanw; } +e2w: (regsan) is savmod2=2 & regsan { export *:2 regsan; } +e2w: (regsan)+ is savmod2=3 & regsan { local tmp = regsan; regsan = regsan + 2; export *:2 tmp; } +e2w: -(regsan) is savmod2=4 & regsan { regsan = regsan - 2; export *:2 regsan; } +e2w: (d16,regsan) is savmod2=5 & regsan; d16 { local tmp = regsan + d16; export *:2 tmp; } +e2w: (extw) is savmod2=6; extw [ pcmode=0; eanum=1; ] { build extw; export *:2 extw; } +e2w: (d16,PC) is PC & savmod2=7 & regsan=2; d16 { tmp:4 = inst_start + 2 + d16; export *:2 tmp; } +e2w: (extw) is savmod2=7 & regsan=3; extw [ pcmode=1; ] { build extw; export *:2 extw; } +e2w: (d16)".w" is savmod2=7 & regsan=0; d16 { export *:2 d16; } +e2w: (d32)".l" is savmod2=7 & regsan=1; d32 { export *:2 d32; } +e2w: "#"^d16 is savmod2=7 & regsan=4; d16 { export *[const]:2 d16; } + + # size=byte + # NB- Manual says that if in predecrement or postincrement mode and the res is the SP, then must inc/dec by 2, not by 1 +e2b: regsdnb is savmod2=0 & regsdnb { export regsdnb; } +e2b: regsanb is savmod2=1 & regsanb { export regsanb; } +e2b: (regsan) is savmod2=2 & regsan { export *:1 regsan; } +e2b: (regsan)+ is savmod2=3 & regsan & regsan=7 { local tmp = regsan; regsan = regsan + 2; export *:1 tmp; } +e2b: (regsan)+ is savmod2=3 & regsan { local tmp = regsan; regsan = regsan + 1; export *:1 tmp; } +e2b: -(regsan) is savmod2=4 & regsan & regsan=7 { regsan = regsan - 2; export *:1 regsan; } +e2b: -(regsan) is savmod2=4 & regsan { regsan = regsan - 1; export *:1 regsan; } +e2b: (d16,regsan) is savmod2=5 & regsan; d16 { local tmp = regsan + d16; export *:1 tmp; } +e2b: (extw) is savmod2=6; extw [ pcmode=0; eanum=1; ] { build extw; export *:1 extw; } +e2b: (d16,PC) is PC & savmod2=7 & regsan=2; d16 { tmp:4 = inst_start + 2 + d16; export *:1 tmp; } +e2b: (extw) is savmod2=7 & regsan=3; extw [ pcmode=1; ] { build extw; export *:1 extw; } +e2b: (d16)".w" is savmod2=7 & regsan=0; d16 { export *:1 d16; } +e2b: (d32)".l" is savmod2=7 & regsan=1; d32 { export *:1 d32; } +e2b: "#"^d8 is savmod2=7 & regsan=4; d8 { export *[const]:1 d8; } + +# For instructions like lea and pea that manipulative the effective address +# itself rather than the data the address is pointing at +eaptr: (regan) is mode=2 & regan { export regan; } +eaptr: (d16,regan) is mode=5 & regan; d16 { local tmp = regan+d16; export tmp; } +eaptr: (extw) is mode=6 & regan; extw [ pcmode=0; regtfan=regan; ] { export extw; } +eaptr: (d16,PC) is mode=7 & regan=2; d16 & PC { tmp:4 = inst_start+2+d16; export tmp; } +eaptr: (extw) is mode=7 & regan=3; extw [ pcmode=1; ] { export extw; } +eaptr: (d16)".w" is mode=7 & regan=0; d16 { export *[const]:4 d16; } +eaptr: (d32)".l" is mode=7 & regan=1; d32 { export *[const]:4 d32; } + +# Data register or predecrement addressing +Ty: -(regan) is rmbit=1 & regan { regan = regan-4; export *:4 regan; } +Ty: regdn is rmbit=0 & regdn { export regdn; } +Tx: -(reg9an) is rmbit=1 & reg9an { reg9an = reg9an-4; export *:4 reg9an; } +Tx: reg9dn is rmbit=0 & reg9dn { export reg9dn; } +Tyw: -(regan) is rmbit=1 & regan { regan = regan-2; export *:2 regan; } +Tyw: regdnw is rmbit=0 & regdnw { export regdnw; } +Txw: -(reg9an) is rmbit=1 & reg9an { reg9an = reg9an-2; export *:2 reg9an; } +Txw: reg9dnw is rmbit=0 & reg9dnw { export reg9dnw; } +Tyb: -(regan) is rmbit=1 & regan { regan = regan-1; export *:1 regan; } +Tyb: regdnb is rmbit=0 & regdnb { export regdnb; } +Txb: -(reg9an) is rmbit=1 & reg9an { reg9an = reg9an-1; export *:1 reg9an; } +Txb: reg9dnb is rmbit=0 & reg9dnb { export reg9dnb; } + +# Bit field parameters +f_off: fldoffdat is flddo=0 & fldoffdat { export *[const]:4 fldoffdat; } +f_off: fldoffreg is flddo=1 & fldoffreg { export fldoffreg; } +f_wd: fldwddat is flddw=0 & fldwddat { export *[const]:4 fldwddat; } +f_wd: fldwdreg is flddw=1 & fldwdreg { export fldwdreg; } + +rreg: regxdn is da=0 & regxdn { export regxdn; } +rreg: regxan is da=1 & regxan { export regxan; } + +# Condition codes + +cc: "t" is op811=0 { export 1:1; } +cc: "f" is op811=1 { export 0:1; } +cc: "hi" is op811=2 { tmp:1 = !(CF || ZF); export tmp; } +cc: "ls" is op811=3 { tmp:1 = CF || ZF; export tmp; } +cc: "cc" is op811=4 { tmp:1 = !CF; export tmp; } +cc: "cs" is op811=5 { export CF; } +cc: "ne" is op811=6 { tmp:1 = !ZF; export tmp; } +cc: "eq" is op811=7 { export ZF; } +cc: "vc" is op811=8 { tmp:1 = !VF; export tmp; } +cc: "vs" is op811=9 { export VF; } +cc: "pl" is op811=10 { tmp:1 = !NF; export tmp; } +cc: "mi" is op811=11 { export NF; } +cc: "ge" is op811=12 { tmp:1 = (VF==NF); export tmp; } +cc: "lt" is op811=13 { tmp:1 = (VF!=NF); export tmp; } +cc: "gt" is op811=14 { tmp:1 = !ZF && (VF==NF); export tmp; } +cc: "le" is op811=15 { tmp:1 = ZF || (VF!=NF); export tmp; } + +const8: "#"^d8 is d8 { export *[const]:1 d8; } +const16: "#"^d16 is d16 { export *[const]:2 d16; } +const32: "#"^d32 is d32 { export *[const]:4 d32; } + +ctlreg: SFC is SFC & ctl=0x000 { export SFC; } +ctlreg: DFC is DFC & ctl=0x001 { export DFC; } +ctlreg: USP is USP & ctl=0x800 { export USP; } +ctlreg: VBR is VBR & ctl=0x801 { export VBR; } +ctlreg: CACR is CACR & ctl=0x002 { export CACR; } +ctlreg: CAAR is CAAR & ctl=0x802 { export CAAR; } +ctlreg: MSP is MSP & ctl=0x803 { export MSP; } +ctlreg: ISP is ISP & ctl=0x804 { export ISP; } +ctlreg: TC is TC & ctl=0x003 { export TC; } +ctlreg: ITT0 is ITT0 & ctl=0x004 { export ITT0; } +ctlreg: ITT1 is ITT1 & ctl=0x005 { export ITT1; } +ctlreg: DTT0 is DTT0 & ctl=0x006 { export DTT0; } +ctlreg: DTT1 is DTT1 & ctl=0x007 { export DTT1; } +ctlreg: SRP is SRP & ctl=0x008 { export BUSCR; } +ctlreg: MMUSR is MMUSR & ctl=0x805 { export MMUSR; } +ctlreg: URP is URP & ctl=0x806 { export URP; } +ctlreg: SRP is SRP & ctl=0x807 { export SRP; } +ctlreg: PCR is PCR & ctl=0x808 { export PCR; } +ctlreg: RAMBAR0 is RAMBAR0 & ctl=0xc04 { export RAMBAR0; } +ctlreg: RAMBAR1 is RAMBAR1 & ctl=0xc05 { export RAMBAR1; } +# ctlreg: PCR is PCR & ctl=0x808 { export PCR; } +ctlreg: CAC is CAC & ctl=0xffe { export CAC; } +ctlreg: MBB is MBB & ctl=0xfff { export MBB; } +ctlreg: "UNK_CTL_"^ctl is ctl { tmp:4 = 0xffffffff; export tmp; } + + +# Relative jump destinations +addr8: reloc is d8base [ reloc=inst_start+2+d8base; ] { export *[ram]:4 reloc; } +addr16: reloc is d16 [ reloc=inst_start+2+d16; ] { export *[ram]:4 reloc; } +addr32: reloc is d32 [ reloc=inst_start+2+d32; ] { export *[ram]:4 reloc; } +# Jump locations for coprocessor instructions +#caddr16: reloc is d16 [ reloc=inst_next-2+d16; ] { export *[ram]:4 reloc; } +#caddr32: reloc is d32 [ reloc=inst_next-4+d32; ] { export *[ram]:4 reloc; } + +# Macros for flags etc + +macro addflags(op1,op2) { + CF = carry(op1,op2); + VF = scarry(op1,op2); + XF = CF; +} + +macro addxflags(op1, op2) { + local opSum = op1 + op2; + CF = carry(op1, op2) || carry(opSum, zext(XF)); + VF = scarry(op1, op2) ^^ scarry(opSum, zext(XF)); +} + +macro subflags(op1,op2) { + CF = op1 < op2; + VF = sborrow(op1,op2); + XF = CF; +} + +# This macro needs to consider the XF flag when finding the CF carry flag value: op1=op1-op2-XF +# original was: CF = op1 < op2; +macro subxflags(op1,op2) { + CF = (op1 < op2) || ( (XF == 1) && (op1 == op2) ); + VF = sborrow(op1,op2); + XF = CF; +} + +macro negxsubflags(op1) { + CF = 0 s< op1; + VF = sborrow(0,op1); + XF = CF; +} + +macro logflags() { + VF=0; + CF=0; +} + +macro resflags(result) { + NF = result s< 0; + ZF = result == 0; +} + +macro resflags_fp(result) { + $(I_FP) = 0; + $(NAN_FP) = 0; + $(N_FP) = result f< 0; + $(Z_FP) = result == 0; +} + +macro clearflags_fp() { + $(N_FP) = 0; + $(Z_FP) = 0; + $(NAN_FP) = 0; +} + +macro bcdflags(result) { + XF = CF; + ZF = (result == 0) * ZF + (result != 0); +} + +macro getbit(res,in,bitnum) { + res = ((in >> bitnum) & 1) != 0; +} + +macro bitmask(res, width) { + res = (1 << width) - 1; +} + +macro bfmask (res, off, width) { + res = ((1 << width) - 1) << (32 - off - width); +} + +macro getbitfield(res, off, width) { + res = (res << off) >> (32 - width); +} + +macro resbitflags(result, bitnum) { + NF = ((result >> bitnum) & 1) != 0; + ZF = result == 0; +} + +macro packflags(res) { + res = zext((TF<<15)|(SVF<<13)|(IPL<<8)|(XF<<4)|(NF<<3)|(ZF<<2)|(VF<<1)|CF); +} + +macro unpackflags(in) { + TF = (in & 0x8000)!=0; + SVF = (in & 0x2000)!=0; + IPL = in[8,3]; + XF = (in & 0x10)!=0; + NF = (in & 8)!=0; + ZF = (in & 4)!=0; + VF = (in & 2)!=0; + CF = (in & 1)!=0; +} + +# This macro sets the NF and ZF flags for extended arithmetic insns- addx, negx, and subx +macro extendedResultFlags(result) { + NF = result s< 0; + ZF = (result == 0) && (ZF == 1); +} + +macro arithmeticShiftLeft(count, register, width) { + local modcount = count & 63; + local lbit:1 = ((register >> (width - modcount) & 1) != 0); + local msbBefore:4 = zext(register s< 0); + register = register << modcount; + resflags(register); + local msbAfter:4 = zext(register s< 0); + VF = (msbBefore ^ msbAfter) != 0; + CF = (modcount != 0) * lbit; + XF = ((modcount == 0) * XF) + ((modcount != 0) * CF); +} + +macro arithmeticShiftRight(count, register, width) { + local modcount = count & 63; + local lbit:1 = ((register >> (modcount-1) & 1) != 0); + local msbBefore:4 = zext(register s< 0); + register = register s>> modcount; + resflags(register); + local msbAfter:4 = zext(register s< 0); + VF = (msbBefore ^ msbAfter) != 0; + CF = (modcount != 0) * lbit; + XF = ((modcount == 0) * XF) + ((modcount != 0) * CF); +} + +macro logicalShiftLeft(count, register, width) { + local modcount = count & 63; + local lbit:1 = ((register >> (width - modcount) & 1) != 0); + local msbBefore:4 = zext(register s< 0); + register = register << modcount; + resflags(register); + local msbAfter:4 = zext(register s< 0); + VF = (msbBefore ^ msbAfter) != 0; + CF = (modcount != 0) * lbit; + XF = ((modcount == 0) * XF) + ((modcount != 0) * CF); +} + +macro logicalShiftRight(count, register, width) { + local modcount = count & 63; + local lbit:1 = ((register >> (modcount-1) & 1) != 0); + local msbBefore:4 = zext(register s< 0); + register = register >> modcount; + resflags(register); + local msbAfter:4 = zext(register s< 0); + VF = (msbBefore ^ msbAfter) != 0; + CF = (modcount != 0) * lbit; + XF = ((modcount == 0) * XF) + ((modcount != 0) * CF); +} + +macro rotateLeft(count, register, width) { + local modcount = count & 63; + register = (register << modcount) | (register >> (width - modcount)); + resflags(register); + CF = (register & 1) != 0; + VF = 0; +} + +macro rotateRight(count, register, width) { + local modcount = count & 63; + register = (register << (width - modcount)) | (register >> modcount); + resflags(register); + CF = zext(register s< 0); + VF = 0; +} + +macro rotateLeftExtended(count, register, width) { + local modcount = count & 63; + local xflag = (register & (1 << (width - modcount))) != 0; + local result = (register << modcount) | (zext(XF) << (modcount - 1)) | (register >> (width - modcount + 1)); + register = (zext(modcount != 0) * result) + (zext(modcount == 0) * register); + resflags(register); + XF = (zext(modcount != 0) * xflag) + (zext(modcount == 0) * XF); + CF = XF; + VF = 0; +} + +macro rotateRightExtended(count, register, width) { + local modcount = count & 63; + local xflag = (register & (1 << (modcount - 1))) != 0; + local result = (zext(XF) << (width - modcount)) | (register >> modcount) | (register << (width - modcount + 1)); + register = (zext(modcount != 0) * result) + (zext(modcount == 0) * register); + resflags(register); + XF = (zext(modcount != 0) * xflag) + (zext(modcount == 0) * XF); + CF = XF; + VF = 0; +} + +:^instruction is extGUARD=0 & mode2 & reg9an & mode & regan & instruction + [ extGUARD=1; regtfan=regan; savmod1=mode; regtsan=reg9an; savmod2=mode2; ] {} + +# Here are the instructions + +with : extGUARD=1 { + +:abcd Tyb,Txb is op=12 & op48=16 & Tyb & Txb { + CF = carry(Txb,carry(Tyb,XF)); + Txb = Txb + Tyb + XF; + XF = bcdAdjust(Txb); + bcdflags(Txb); +} + +:add.b eab,reg9dnb is (op=13 & reg9dnb & op68=0)... & eab { addflags(eab,reg9dnb); reg9dnb = reg9dnb + eab; resflags(reg9dnb); } +:add.w eaw,reg9dnw is (op=13 & reg9dnw & op68=1)... & eaw { addflags(eaw,reg9dnw); reg9dnw = reg9dnw + eaw; resflags(reg9dnw); } +:add.l eal,reg9dn is (op=13 & reg9dn & op68=2)... & eal { addflags(eal,reg9dn); reg9dn = reg9dn + eal; resflags(reg9dn); } +:add.b reg9dnb,eab is (op=13 & reg9dnb & op68=4 & $(MEM_ALTER_ADDR_MODES))... & eab { addflags(reg9dnb,eab); eab = reg9dnb + eab; resflags(eab); } +:add.w reg9dnw,eaw is (op=13 & reg9dnw & op68=5 & $(MEM_ALTER_ADDR_MODES))... & eaw { addflags(reg9dnw,eaw); eaw = reg9dnw + eaw; resflags(eaw); } +:add.l reg9dn,eal is (op=13 & reg9dn & op68=6 & $(MEM_ALTER_ADDR_MODES))... & eal { addflags(reg9dn,eal); eal = reg9dn + eal; resflags(eal); } + +:adda.w eaw,reg9an is (op=13 & reg9an & op68=3)... & eaw { reg9an = sext(eaw) + reg9an; } +:adda.l eal,reg9an is (op=13 & reg9an & op68=7)... & eal { reg9an = eal + reg9an; } + +:addi.b "#"^d8,e2b is opbig=6 & op67=0 & savmod1 & regtfan & $(DAT_ALTER_ADDR_MODES); d8; e2b [ savmod2=savmod1; regtsan=regtfan; ] { addflags(d8,e2b); e2b = d8 + e2b; resflags(e2b); } +:addi.w "#"^d16,e2w is opbig=6 & op67=1 & savmod1 & regtfan & $(DAT_ALTER_ADDR_MODES); d16; e2w [ savmod2=savmod1; regtsan=regtfan; ] { addflags(d16,e2w); e2w = d16 + e2w; resflags(e2w); } +:addi.l "#"^d32,e2l is opbig=6 & op67=2 & savmod1 & regtfan & $(DAT_ALTER_ADDR_MODES); d32; e2l [ savmod2=savmod1; regtsan=regtfan; ] { addflags(d32,e2l); e2l = d32+e2l; resflags(e2l); } + +:addq.b "#"^quick,eab is (op=5 & quick & op68=0)... & eab { addflags(quick,eab); eab = eab+quick; resflags(eab); } +:addq.w "#"^quick,eaw is (op=5 & quick & op68=1)... & eaw { addflags(quick,eaw); eaw = eaw+quick; resflags(eaw); } +:addq.l "#"^quick,eal is (op=5 & quick & op68=2)... & eal { addflags(quick,eal); eal = eal+quick; resflags(eal); } +# special case for address register destination +:addq.w "#"^quick,regan is op=5 & quick & op68=1 & mode=1 & regan { regan = regan + quick; } +:addq.l "#"^quick,regan is op=5 & quick & op68=2 & mode=1 & regan { regan = regan + quick; } + + +:addx.b Tyb,Txb is op=13 & op8=1 & op67=0 & op45=0 & Tyb & Txb + { addxflags(Tyb,Txb); Txb=Tyb+Txb+zext(XF); extendedResultFlags(Txb); } +:addx.w Tyw,Txw is op=13 & op8=1 & op67=1 & op45=0 & Tyw & Txw + { addxflags(Tyw,Txw); Txw=Tyw+Txw+zext(XF); extendedResultFlags(Txw); } +:addx.l Ty,Tx is op=13 & op8=1 & op67=2 & op45=0 & Ty & Tx + { addxflags(Ty,Tx); Tx=Ty+Tx+zext(XF); extendedResultFlags(Tx); } + +:and.b eab,reg9dnb is (op=12 & reg9dnb & op68=0 & $(DAT_ALTER_ADDR_MODES))... & eab { logflags(); reg9dnb = reg9dnb & eab; resflags(reg9dnb); } +:and.w eaw,reg9dnw is (op=12 & reg9dnw & op68=1 & $(DAT_ALTER_ADDR_MODES))... & eaw { logflags(); reg9dnw = reg9dnw & eaw; resflags(reg9dnw); } +:and.l eal,reg9dn is (op=12 & reg9dn & op68=2 & $(DAT_ALTER_ADDR_MODES))... & eal { logflags(); reg9dn = reg9dn & eal; resflags(reg9dn); } +:and.b reg9dnb,eab is (op=12 & reg9dnb & op68=4 & $(MEM_ALTER_ADDR_MODES))... & eab { logflags(); eab = reg9dnb & eab; resflags(eab); } +:and.w reg9dnw,eaw is (op=12 & reg9dnw & op68=5 & $(MEM_ALTER_ADDR_MODES))... & eaw { logflags(); eaw = reg9dnw & eaw; resflags(eaw); } +:and.l reg9dn,eal is (op=12 & reg9dn & op68=6 & $(MEM_ALTER_ADDR_MODES))... & eal { logflags(); eal = reg9dn & eal; resflags(eal); } + +:andi.b const8,e2b is opbig=2 & op67=0 & $(DAT_ALTER_ADDR_MODES); const8; e2b [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); e2b = e2b & const8; resflags(e2b); } +:andi.w const16,e2w is opbig=2 & op67=1 & $(DAT_ALTER_ADDR_MODES); const16; e2w [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); e2w = e2w & const16; resflags(e2w); } +:andi.l const32,e2l is opbig=2 & op67=2 & $(DAT_ALTER_ADDR_MODES); const32; e2l [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); e2l=e2l & const32; resflags(e2l); } +:andi const8,"CCR" is d16=0x23c; const8 { packflags(SR); SR = SR & zext(const8); unpackflags(SR); } +:andi const16,SR is opbig=0x2 & d8base=0x7c; const16 & SR { packflags(SR); SR = SR & const16; unpackflags(SR); } + +:asl.b cntreg,regdnb is op=14 & cntreg & op8=1 & op67=0 & op34=0 & regdnb { arithmeticShiftLeft(cntreg, regdnb, 8); } +:asl.w cntreg,regdnw is op=14 & cntreg & op8=1 & op67=1 & op34=0 & regdnw { arithmeticShiftLeft(cntreg, regdnw, 16); } +:asl.l cntreg,regdn is op=14 & cntreg & op8=1 & op67=2 & op34=0 & regdn { arithmeticShiftLeft(cntreg, regdn, 32); } +:asl eaw is (opbig=0xe1 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw { + local value:2 = eaw; + local msbBefore = value & 0x8000; + getbit(CF, value, 15); + value = value << 1; + resflags(value); + local msbAfter = value & 0x8000; + VF = (msbBefore ^ msbAfter) != 0; + eaw = value; + XF = CF; +} + +:asr.b cntreg,regdnb is op=14 & cntreg & op8=0 & op67=0 & op34=0 & regdnb { arithmeticShiftRight(cntreg, regdnb, 8); } +:asr.w cntreg,regdnw is op=14 & cntreg & op8=0 & op67=1 & op34=0 & regdnw { arithmeticShiftRight(cntreg, regdnw, 16); } +:asr.l cntreg,regdn is op=14 & cntreg & op8=0 & op67=2 & op34=0 & regdn { arithmeticShiftRight(cntreg, regdn, 32); } +:asr eaw is (opbig=0xe0 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw { + local value:2 = eaw; + local msbBefore = value & 0x8000; + getbit(CF, value, 0); + value = value s>> 1; + resflags(value); + local msbAfter = value & 0x8000; + VF = (msbBefore ^ msbAfter) != 0; + eaw = value; + XF = CF; +} + +:b^cc^".b" addr8 is op=6 & cc & addr8 { if (cc) goto addr8; } +:b^cc^".w" addr16 is op=6 & cc & d8base=0; addr16 { if (cc) goto addr16; } +:b^cc^".l": addr32 is op=6 & cc & d8base=255; addr32 { if (cc) goto addr32; } + +:bchg.b reg9dn,eab is (op=0 & reg9dn & op68=5 & $(MEM_ALTER_ADDR_MODES))... & eab { + mask:1 = 1<<(reg9dn&7); ZF=(eab&mask)==0; eab=eab^mask; } + +:bchg.b d8,e2b is opbig=8 & op67=1 & $(MEM_ALTER_ADDR_MODES); d8; e2b + [ savmod2=savmod1; regtsan=regtfan; ] { + mask:1 = 1<<(d8 & 7); # target is a byte in memory, so the bit number in the byte is modulo 8 + ZF=(e2b&mask)==0; + e2b=e2b^mask;} + +:bchg.l reg9dn,regdn is op=0 & reg9dn & op68=5 & mode=0 & regdn { mask:4 = 1<<(reg9dn&31); ZF=(regdn&mask)==0; regdn=regdn^mask; } +:bchg.l d8,regdn is opbig=8 & op67=1 & mode=0 & regdn; d8 { mask:4 = 1<> (32 - f_wd); f_reg = tmp; tmp2:4 = e2l; getbitfield(tmp2, f_off, f_wd); resbitflags(tmp2, f_wd-1); + +} + +:bfextu e2l{f_off:f_wd},f_reg is opbig=0xe9 & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd & f_reg; e2l [ savmod2=savmod1; regtsan=regtfan; ] { + logflags(); tmp:4 = e2l; getbitfield(tmp, f_off, f_wd); f_reg = tmp; resbitflags(f_reg, f_wd-1); +} + +:bfffo e2l{f_off:f_wd},f_reg is opbig=0xed & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd & f_reg & flddo=0 & fldoffdat=0 & flddw=0 & fldwddat=0; e2l + [ savmod2=savmod1; regtsan=regtfan; ] { + # "Find First One in Bit Field" pronounced "boo-foe" + # Set the destination f_reg with the position of the first 1 bit in the source e2l. + # f_off and f_wd specify the offset and width of the field of the source to consider. + # If f_off=0 and f_wd=0 then this means the full 32-bit source is examined (implemented here). + # + tmp:4 = e2l; + NF = (tmp & 0x80000000) != 0; + ZF = (tmp == 0); + VF = 0; + CF = 0; + tmp2:4 = lzcount(tmp); + # NB- it seems the MSB left most bit is really at offset 0, + # and the right LSB is at offset 31 + tmp3:4 = tmp2 % 32:4; # need mod for when there are all zeros, when tmp2 would = 32 + f_reg = tmp3; +} + +# TODO: complete bfffo for when f_off or f_wd !=0, and for when f_off and f_wd are in registers +:bfffo e2l{f_off:f_wd},f_reg is opbig=0xed & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd & f_reg ; e2l + [ savmod2=savmod1; regtsan=regtfan; ] unimpl + + +:bfins f_reg,e2l{f_off:f_wd} is opbig=0xef & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd & f_reg; e2l [ savmod2=savmod1; regtsan=regtfan; ] { + logflags(); mask:4 = 0; bitmask(mask, f_wd); tmp:4 = f_reg & mask; resbitflags(tmp, f_wd-1); bfmask(mask,f_off,f_wd); e2l = (e2l & ~mask) | (tmp << (32 - f_off - f_wd)); +} + +:bfset e2l{f_off:f_wd} is opbig=0xee & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd; e2l [ savmod2=savmod1; regtsan=regtfan; ] { + logflags(); tmp:4 = e2l; getbitfield(tmp, f_off, f_wd); resbitflags(tmp, f_wd-1); mask:4 = 0; bfmask(mask,f_off,f_wd); e2l = e2l & ~mask; +} + +:bftst e2l{f_off:f_wd} is opbig=0xe8 & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd; e2l [ savmod2=savmod1; regtsan=regtfan; ] { + logflags(); tmp:4 = e2l; getbitfield(tmp, f_off, f_wd); resbitflags(tmp, f_wd-1); +} + +:bkpt "#"op02 is opbig=0x48 & op67=1 & op5=0 & op34=1 & op02 unimpl + +:bra.b addr8 is opbig=0x60 & addr8 { goto addr8; } +:bra.w addr16 is opbig=0x60 & d8base=0; addr16 { goto addr16; } +:bra.l addr32 is opbig=0x60 & d8base=255; addr32 { goto addr32; } + +:bset.b reg9dn,eab is (op=0 & reg9dn & op68=7 & $(MEM_ALTER_ADDR_MODES))... & eab { mask:1 = 1<<(reg9dn&7); ZF=(eab&mask)==0; eab=eab|mask; } +:bset.b d8,e2b is opbig=8 & op67=3 & $(MEM_ALTER_ADDR_MODES); d8; e2b [ savmod2=savmod1; regtsan=regtfan; ] { mask:1=1<> 8) | ((regdn & 0xFF000000) >> 24); +} + +@endif # COLDFIRE + +:callm "#"^d8,e2l is opbig=6 & op67=3 & $(CTL_ADDR_MODES); d8; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl + +#TODO: should constrain CAS to ignore mode=7 & regan=4 (place CAS2 before CAS to avoid problem) +:cas2.w regdcw:regdc2w,regduw:regdu2w,(regda):(regda2) is op015=0x0cfc; regda & ext_911=0 & regduw & ext_35=0 & regdcw; regda2 & ext2_911=0 & regdu2w & ext2_35=0 & regdc2w { + dc1:4 = zext(regdcw); + dc2:4 = zext(regdc2w); + if(dc1!=regda) goto ; + if(dc2!=regda2) goto ; + regda = zext(regduw); + regda2 = zext(regdu2w); + ZF = 1; + NF = 0; + goto inst_next; + + regdcw = regda(2); + regdc2w = regda2(2); + ZF = 0; + NF = 1; +} +:cas2.l regdc:regdc2,regdu:regdu2,(regda):(regda2) is op015=0x0efc; regda & ext_911=0 & regdu & ext_35=0 & regdc; regda2 & ext2_911=0 & regdu2 & ext2_35=0 & regdc2 { + if(regdc!=regda) goto ; + if(regdc2!=regda2) goto ; + regda = regdu; + regda2 = regdu2; + ZF = 1; + NF = 0; + goto inst_next; + + regdc = regda; + regdc2 = regda2; + ZF = 0; + NF = 1; +} + +:cas.b regdcb,regdub,e2b is opbig=0x0a & op67=3 & $(MEM_ALTER_ADDR_MODES); regda=0 & ext_911=0 & regdub & ext_35=0 & regdcb; e2b [ savmod2=savmod1; regtsan=regtfan; ] { + if(e2b==regdcb) goto ; + regdcb = e2b; + ZF = 0; + NF = 1; + goto inst_next; + + e2b = regdub; + ZF = 1; + NF = 0; +} +:cas.w regdcw,regduw,e2w is opbig=0x0c & op67=3 & $(MEM_ALTER_ADDR_MODES); regda=0 & ext_911=0 & regduw & ext_35=0 & regdcw; e2w [ savmod2=savmod1; regtsan=regtfan; ] { + if(e2w==regdcw) goto ; + regdcw = e2w; + ZF = 0; + NF = 1; + goto inst_next; + + e2w = regduw; + ZF = 1; + NF = 0; +} +:cas.l regdc,regdu,e2l is opbig=0x0e & op67=3 & $(MEM_ALTER_ADDR_MODES); regda=0 & ext_911=0 & regdu & ext_35=0 & regdc; e2l [ savmod2=savmod1; regtsan=regtfan; ] { + if(e2l==regdc) goto ; + regdc = e2l; + ZF = 0; + NF = 1; + goto inst_next; + + e2l = regdu; + ZF = 1; + NF = 0; +} + +:chk.w eaw,reg9dnw is (op=4 & reg9dnw & op68=6 & $(DAT_ALTER_ADDR_MODES))... & eaw { + build eaw; + local address:4 = zext(eaw); + local bound:2 = *:2 address; + local signed_bound:4 = sext(bound); + local signed_register:4 = sext(reg9dnw); + + if ((signed_register s>= 0) && (signed_register s<= signed_bound)) goto inst_next; + NF = signed_register s< 0; + __m68k_trap(6:1); +} + +:chk.l eal,reg9dn is (op=4 & reg9dn & op68=4 & $(DAT_ALTER_ADDR_MODES))... & eal { + build eal; + local address:4 = zext(eal); + local bound:4 = *:4 address; + local signed_bound:4 = sext(bound); + local signed_register:4 = sext(reg9dn); + + if ((signed_register s>= 0) && (signed_register s<= signed_bound)) goto inst_next; + NF = signed_register s< 0; + __m68k_trap(6:1); +} + +:chk2.b e2b,rreg is opbig=0 & op67=3 & $(CTL_ADDR_MODES); rreg & wl=1; e2b [ savmod2=savmod1; regtsan=regtfan; ] { + build e2b; + local address:4 = zext(e2b); + local lower:1 = *:1 address; + local upper:1 = *:1 (address + 1); + local signed_lower:4 = sext(lower); + local signed_upper:4 = sext(upper); + local signed_register:4 = sext(rreg); + + ZF = ((signed_register == signed_lower) || (signed_register == signed_upper)); + CF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper)); + if (!CF) goto inst_next; + __m68k_trap(6:1); +} + +:chk2.w e2w,rreg is opbig=2 & op67=3 & $(CTL_ADDR_MODES); rreg & wl=1; e2w [ savmod2=savmod1; regtsan=regtfan; ] { + build e2w; + local address:4 = zext(e2w); + local lower:2 = *:2 address; + local upper:2 = *:2 (address + 2); + local signed_lower:4 = sext(lower); + local signed_upper:4 = sext(upper); + local signed_register:4 = sext(rreg); + + ZF = ((signed_register == signed_lower) || (signed_register == signed_upper)); + CF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper)); + if (!CF) goto inst_next; + __m68k_trap(6:1); +} + +:chk2.l e2l,rreg is opbig=4 & op67=3 & $(CTL_ADDR_MODES); rreg & wl=1; e2l [ savmod2=savmod1; regtsan=regtfan; ] { + build e2l; + local address:4 = zext(e2l); + local lower:4 = *:4 address; + local upper:4 = *:4 (address + 4); + local signed_lower:4 = sext(lower); + local signed_upper:4 = sext(upper); + local signed_register:4 = sext(rreg); + + ZF = ((signed_register == signed_lower) || (signed_register == signed_upper)); + CF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper)); + if (!CF) goto inst_next; + __m68k_trap(6:1); +} + +:cmp2.b e2b,rreg is opbig=0 & op67=3 & $(CTL_ADDR_MODES); rreg & wl=0; e2b [ savmod2=savmod1; regtsan=regtfan; ] { + build e2b; + local address:4 = zext(e2b); + local lower:1 = *:1 address; + local upper:1 = *:1 (address + 1); + local signed_lower:4 = sext(lower); + local signed_upper:4 = sext(upper); + local signed_register:4 = sext(rreg); + + ZF = ((signed_register == signed_lower) || (signed_register == signed_upper)); + CF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper)); +} + +:cmp2.w e2w,rreg is opbig=2 & op67=3 & $(CTL_ADDR_MODES); rreg & wl=0; e2w [ savmod2=savmod1; regtsan=regtfan; ] { + build e2w; + local address:4 = zext(e2w); + local lower:2 = *:2 address; + local upper:2 = *:2 (address + 2); + local signed_lower:4 = sext(lower); + local signed_upper:4 = sext(upper); + local signed_register:4 = sext(rreg); + + ZF = ((signed_register == signed_lower) || (signed_register == signed_upper)); + CF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper)); +} + +:cmp2.l e2l,rreg is opbig=4 & op67=3 & $(CTL_ADDR_MODES); rreg & wl=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { + build e2l; + local address:4 = zext(e2l); + local lower:4 = *:4 address; + local upper:4 = *:4 (address + 4); + local signed_lower:4 = sext(lower); + local signed_upper:4 = sext(upper); + local signed_register:4 = sext(rreg); + + ZF = ((signed_register == signed_lower) || (signed_register == signed_upper)); + CF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper)); +} + +@ifdef MC68040 + +cachetype: "none" is op67=0 { export 0:4; } +cachetype: "data" is op67=1 { export 1:4; } +cachetype: "instr" is op67=2 { export 2:4; } +cachetype: "both" is op67=3 { export 3:4; } +:cinvl cachetype,(regan) is opbig=0xf4 & cachetype & op5=0 & op34=1 & regan unimpl +:cinvp cachetype,(regan) is opbig=0xf4 & cachetype & op5=0 & op34=2 & regan unimpl +:cinva cachetype is opbig=0xf4 & cachetype & op5=0 & op34=3 unimpl + +@endif # MC68040 + + +@ifdef MC68040 + +:cpushl cachetype,(regan) is opbig=0xf4 & cachetype & op5=1 & op34=1 & regan {pushInvalidateCaches(regan);} +:cpushp cachetype,(regan) is opbig=0xf4 & cachetype & op5=1 & op34=2 & regan {pushInvalidateCaches(regan);} +:cpusha cachetype is opbig=0xf4 & cachetype & op5=1 & op34=3 {pushInvalidateCaches();} + +@endif # MC68040 + +:clr.b eab is (opbig=0x42 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab { eab = 0; NF=0; ZF=1; VF=0; CF=0; } +:clr.w eaw is (opbig=0x42 & op67=1 & $(DAT_ALTER_ADDR_MODES))... & eaw { eaw = 0; NF=0; ZF=1; VF=0; CF=0; } +:clr.l eal is (opbig=0x42 & op67=2 & $(DAT_ALTER_ADDR_MODES))... & eal { eal=0; NF=0; ZF=1; VF=0; CF=0; } + +:cmp.b eab,reg9dnb is (op=11 & reg9dnb & op68=0)... & eab { o2:1=eab; subflags(reg9dnb,o2); local tmp =reg9dnb-o2; resflags(tmp); } +:cmp.w eaw,reg9dnw is (op=11 & reg9dnw & op68=1)... & eaw { o2:2=eaw; subflags(reg9dnw,o2); local tmp =reg9dnw-o2; resflags(tmp); } +:cmp.l eal,reg9dn is (op=11 & reg9dn & op68=2)... & eal { o2:4=eal; subflags(reg9dn,o2); local tmp =reg9dn-o2; resflags(tmp); } + +:cmpa.w eaw,reg9an is (op=11 & reg9an & op68=3)... & eaw { tmp1:4 = sext(eaw); subflags(reg9an,tmp1); local tmp =reg9an-tmp1; resflags(tmp); } +:cmpa.l eal,reg9an is (op=11 & reg9an & op68=7)... & eal { o2:4=eal; subflags(reg9an,o2); local tmp =reg9an-o2; resflags(tmp); } + + +:cmpi.b "#"^d8,e2b is opbig=12 & op67=0 & savmod1 & regtfan & $(DAT_ALTER_ADDR_MODES); d8; e2b [ savmod2=savmod1; regtsan=regtfan; ] { o2:1=e2b; subflags(o2,d8); local tmp =o2-d8; resflags(tmp); } +:cmpi.w "#"^d16,e2w is opbig=12 & op67=1 & savmod1 & regtfan & $(DAT_ALTER_ADDR_MODES); d16; e2w [ savmod2=savmod1; regtsan=regtfan; ] { o2:2=e2w; subflags(o2,d16); local tmp =o2-d16; resflags(tmp);} +:cmpi.l "#"^d32,e2l is opbig=12 & op67=2 & savmod1 & regtfan & $(DAT_ALTER_ADDR_MODES); d32; e2l [ savmod2=savmod1; regtsan=regtfan; ] { o2:4=e2l; subflags(o2,d32); local tmp =o2-d32; resflags(tmp);} + +:cmpm.b (regan)+,(reg9an)+ is op=11 & reg9an & op8=1 & op67=0 & op5=0 & op34=1 & regan { local tmp1=*:1 regan; regan=regan+1; local tmp2=*:1 reg9an; reg9an=reg9an+1; + subflags(tmp2,tmp1); local tmp =tmp2-tmp1; resflags(tmp); } +:cmpm.w (regan)+,(reg9an)+ is op=11 & reg9an & op8=1 & op67=1 & op5=0 & op34=1 & regan { local tmp1=*:2 regan; regan=regan+2; local tmp2=*:2 reg9an; reg9an=reg9an+2; + subflags(tmp2,tmp1); local tmp =tmp2-tmp1; resflags(tmp); } +:cmpm.l (regan)+,(reg9an)+ is op=11 & reg9an & op8=1 & op67=2 & op5=0 & op34=1 & regan { local tmp1=*:4 regan; regan=regan+4; local tmp2=*:4 reg9an; reg9an=reg9an+4; + subflags(tmp2,tmp1); local tmp =tmp2-tmp1; resflags(tmp); } +# cpBcc # need to know specific copressors use copcc1 +# cpDBcc # use copcc2 +# cpGEN +# cpScc # use copcc2 +# cpTRAPcc # use copcc2 + +:db^cc regdnw,addr16 is op=5 & cc & op67=3 & op5=0 & op34=1 & regdnw; addr16 { if (cc) goto inst_next; regdnw=regdnw-1; if (regdnw!=-1) goto addr16; } + +:divs.w eaw,reg9dn is (op=8 & reg9dn & op68=7)... & eaw { local denom=sext(eaw); local div=reg9dn s/ denom; local rem=reg9dn s% denom; CF=0; resflags(div); + reg9dn = (rem<<16) | (div & 0xffff); } + +:divu.w eaw,reg9dn is (op=8 & reg9dn & op68=3)... & eaw { local denom=zext(eaw); local div=reg9dn / denom; local rem=reg9dn %denom; CF=0; resflags(div); + reg9dn = (rem<<16) | (div & 0xffff); } + +#remyes: "s" is regdq & (regdr=regdq) & divsgn=1 { } +remyes: "sl" is divsgn=1 { } +#remyes: "u" is regdq & (regdr=regdq) & divsgn=0 { } +remyes: "ul" is divsgn=0 { } + +#subdiv: regdq is regdq & regdr=regdq & divsz=0 & divsgn=0 { regdq = regdq/glbdenom; export regdq; } + +# NB- Need to be very careful with div to not clobber when regdr and regdq refer to the same reg. +# When this happens it seems the destination reg should get the quotient, not the remainder. +# +subdiv: regdr:regdq is regdq & regdr & divsz=0 & divsgn=0 { + local rem = regdq % glbdenom; local quot = regdq / glbdenom; regdr = rem; regdq = quot; export regdq; } + +subdiv: regdr:regdq is regdq & regdr & divsz=1 & divsgn=0 { divi:8 = (zext(regdr)<<32)|zext(regdq); denom:8=zext(glbdenom); + local quot=divi/denom; local rem=divi%denom; regdr=rem:4; regdq = quot:4; export regdq; } + +#subdiv: regdq is regdq & regdr=regdq & divsz=0 & divsgn=1 { regdq = regdq s/ glbdenom; export regdq; } + +subdiv: regdr:regdq is regdq & regdr & divsz=0 & divsgn=1 { + local rem = regdq s% glbdenom; local quot = regdq s/ glbdenom; regdr = rem; regdq = quot; export regdq; } + +subdiv: regdr:regdq is regdq & regdr & divsz=1 & divsgn=1 { divi:8 = (sext(regdr)<<32)|sext(regdq); denom:8=sext(glbdenom); + local quot=divi s/denom; local rem=divi s%denom; regdr=rem:4; regdq=quot:4; export regdq; } + +# when divsgn=0 +# divu.l is regdq / e2l -> regdq +# divu.l (when divsz = 1) is regdr concat regdq / el2 - > regdr and regdq +# divul.l (when divsz = 0) is regdq / el2 -> regdr and regdq +# +:div^remyes^".l" e2l,subdiv is opbig=0x4c & op67=1 & $(DAT_ALTER_ADDR_MODES); subdiv & remyes; e2l [ savmod2=savmod1; regtsan=regtfan;] { glbdenom=e2l; build subdiv; CF=0; resflags(subdiv);} + +:eor.b reg9dnb,eab is (op=11 & reg9dnb & op68=4 & $(DAT_ALTER_ADDR_MODES))... & eab { logflags(); eab = reg9dnb ^ eab; resflags(eab); } +:eor.w reg9dnw,eaw is (op=11 & reg9dnw & op68=5 & $(DAT_ALTER_ADDR_MODES))... & eaw { logflags(); eaw = reg9dnw ^ eaw; resflags(eaw); } +:eor.l reg9dn,eal is (op=11 & reg9dn & op68=6 & $(DAT_ALTER_ADDR_MODES))... & eal { logflags(); eal = reg9dn ^ eal; resflags(eal); } + +:eori.b "#"^d8,e2b is opbig=10 & op67=0 & $(DAT_ALTER_ADDR_MODES); d8; e2b [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); e2b = e2b^d8; resflags(e2b); } +:eori.w "#"^d16,e2w is opbig=10 & op67=1 & $(DAT_ALTER_ADDR_MODES); d16; e2w [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); e2w = e2w^d16; resflags(e2w); } +:eori.l "#"^d32,e2l is opbig=10 & op67=2 & $(DAT_ALTER_ADDR_MODES); d32; e2l [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); e2l=e2l^d32; resflags(e2l); } +:eori "#"^d8,"CCR" is d16=0xa3c; d8 { packflags(SR); SR = SR ^ d8; unpackflags(SR); } +:eori "#"^d16,SR is opbig=0x0a & d8base=0x7c; d16 & SR { packflags(SR); SR = SR ^ d16; unpackflags(SR); } + + +:exg reg9dn,regdn is op=12 & reg9dn & op8=1 & op37=8 & regdn { local tmp = reg9dn; reg9dn=regdn; regdn=tmp; } +:exg reg9an,regan is op=12 & reg9an & op8=1 & op37=9 & regan { local tmp = reg9an; reg9an=regan; regan=tmp; } +:exg reg9dn,regan is op=12 & reg9dn & op8=1 & op37=17 & regan { local tmp = reg9dn; reg9dn=regan; regan=tmp; } + +:ext.w regdnw is op=4 & reg9dn=4 & op68=2 & op35=0 & regdnw { local tmp =regdnw:1; regdnw = sext(tmp); } +:ext.l regdn is op=4 & reg9dn=4 & op68=3 & op35=0 & regdn { local tmp =regdn:2; regdn = sext(tmp); } +:extb.l regdn is op=4 & reg9dn=4 & op68=7 & op35=0 & regdn { local tmp =regdn:1; regdn = sext(tmp); } + +:illegal is d16=0x4afc unimpl + +# jump addresses derived from effective address calculation +addrpc16: reloc is d16 [ reloc = inst_start+2+d16; ] { export *[ram]:4 reloc; } +addrd16: d16 is d16 { export *[ram]:4 d16; } +addrd32: d32 is d32 { export *[ram]:4 d32; } + +:jmp (regan) is opbig=0x4e & op67=3 & mode=2 & regan { goto [regan]; } +:jmp (d16,regan) is opbig=0x4e & op67=3 & mode=5 & regan; d16 { local tmp = regan + d16; goto [tmp]; } +:jmp (extw) is opbig=0x4e & op67=3 & mode=6 & regan; extw [ pcmode=0; regtfan=regan; ] { build extw; goto [extw]; } +:jmp addrpc16 is opbig=0x4e & op67=3 & mode=7 & regan=2; addrpc16 { goto addrpc16; } +:jmp (extw) is opbig=0x4e & op67=3 & mode=7 & regan=3; extw [ pcmode=1; ] { build extw; goto [extw]; } +:jmp addrd16".w" is opbig=0x4e & op67=3 & mode=7 & regan=0; addrd16 { goto addrd16; } +:jmp addrd32".l" is opbig=0x4e & op67=3 & mode=7 & regan=1; addrd32 { goto addrd32; } + +:jsr (regan) is opbig=0x4e & op67=2 & mode=2 & regan { SP=SP-4; *:4 SP = inst_next; call [regan]; } +:jsr (d16,regan) is opbig=0x4e & op67=2 & mode=5 & regan; d16 { SP=SP-4; *:4 SP = inst_next; local tmp = regan + d16; call [tmp]; } +:jsr (extw) is opbig=0x4e & op67=2 & mode=6 & regan; extw [ pcmode=0; regtfan=regan;] { build extw; SP=SP-4; *:4 SP=inst_next; call [extw];} +:jsr addrpc16 is opbig=0x4e & op67=2 & mode=7 & regan=2; addrpc16 { SP=SP-4; *:4 SP = inst_next; call addrpc16; } +:jsr (extw) is opbig=0x4e & op67=2 & mode=7 & regan=3; extw [ pcmode=1; ] { build extw; SP=SP-4; *:4 SP = inst_next; call [extw]; } +:jsr addrd16".w" is opbig=0x4e & op67=2 & mode=7 & regan=0; addrd16 { SP=SP-4; *:4 SP = inst_next; call addrd16; } +:jsr addrd32".l" is opbig=0x4e & op67=2 & mode=7 & regan=1; addrd32 { SP=SP-4; *:4 SP = inst_next; call addrd32; } + +:lea eaptr,reg9an is (op=4 & reg9an & op68=7)... & eaptr { reg9an = eaptr; } + +:link.w regan,d16 is opbig=0x4e & op37=10 & regan; d16 { SP=SP-4; *:4 SP = regan; regan=SP; SP = SP + d16; } +:link.l regan,d32 is opbig=0x48 & op37=1 & regan; d32 { SP=SP-4; *:4 SP = regan; regan=SP; SP = SP + d32; } + +macro shiftCXFlags(cntreg) { + CF = CF * (cntreg != 0); + XF = CF * (cntreg != 0) + XF * (cntreg == 0); +} + +:lsl.b cntreg,regdnb is op=14 & cntreg & op8=1 & op67=0 & op34=1 & regdnb { logicalShiftLeft(cntreg, regdnb, 8); } +:lsl.w cntreg,regdnw is op=14 & cntreg & op8=1 & op67=1 & op34=1 & regdnw { logicalShiftLeft(cntreg, regdnw, 16); } +:lsl.l cntreg,regdn is op=14 & cntreg & op8=1 & op67=2 & op34=1 & regdn { logicalShiftLeft(cntreg, regdn, 32); } +:lsl eaw is (opbig=0xe3 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw { + local value:2 = eaw; + getbit(CF, value, 15); + value = value << 1; + resflags(value); + eaw = value; + VF = 0; + XF = CF; +} + +:lsr.b cntreg,regdnb is op=14 & cntreg & op8=0 & op67=0 & op34=1 & regdnb { logicalShiftRight(cntreg, regdnb, 8); } +:lsr.w cntreg,regdnw is op=14 & cntreg & op8=0 & op67=1 & op34=1 & regdnw { logicalShiftRight(cntreg, regdnw, 16); } +:lsr.l cntreg,regdn is op=14 & cntreg & op8=0 & op67=2 & op34=1 & regdn { logicalShiftRight(cntreg, regdn, 32); } +:lsr eaw is (opbig=0xe2 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw { + local value:2 = eaw; + getbit(CF, value, 0); + value = value >> 1; + resflags(value); + eaw = value; + VF = 0; + XF = CF; +} + +:move.b eab,e2b is (op=1 & $(DAT_ALTER_ADDR_MODES2))... & eab ; e2b { build eab; local tmp = eab; build e2b; e2b = tmp; resflags(tmp); logflags(); } +:move.w eaw,e2w is (op=3 & $(DAT_ALTER_ADDR_MODES2))... & eaw ; e2w { build eaw; local tmp = eaw; build e2w; e2w = tmp; resflags(tmp); logflags(); } +:move.l eal,e2l is (op=2 & $(DAT_ALTER_ADDR_MODES2))... & eal ; e2l { build eal; local tmp = eal; build e2l; e2l = tmp; resflags(tmp); logflags(); } + +:move "CCR",eaw is (opbig=0x42 & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eaw { packflags(SR); eaw = SR; } +:move eaw,"CCR" is (opbig=0x44 & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eaw { unpackflags(eaw); } +:move SR,eaw is SR; (opbig=0x40 & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eaw { packflags(SR); eaw = SR; } +:move eaw,SR is SR; (opbig=0x46 & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eaw { SR = eaw; unpackflags(SR); } +:move USP,regan is opbig=0x4e & op37=13 & regan & USP { regan = USP; } +:move regan,USP is opbig=0x4e & op37=12 & regan & USP { USP = regan; } + +:movea.w eaw,reg9an is (op=3 & reg9an & mode2=1)... & eaw { reg9an = sext(eaw); } +:movea.l eal,reg9an is (op=2 & reg9an & mode2=1)... & eal { reg9an = eal; } + +:movec ctlreg,rreg is d16=0x4e7a; rreg & ctlreg { rreg = ctlreg; } +:movec rreg,ctlreg is d16=0x4e7b; rreg & ctlreg { ctlreg = rreg; } + +@ifdef MC68040 + +:move16 (regan)+,(regxan)+ is opbig=0xf6 & op37=4 & regan; regxan & da=1 { local src=regan&0xfffffff0; local dst=regxan&0xfffffff0; regan=regan+16; regxan=regxan+16; + *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; + *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; } +:move16 (regan)+,(d32)".l" is opbig=0xf6 & op37=0 & regan; d32 { local src=regan&0xfffffff0; dst:4=d32&0xfffffff0; regan=regan+16; + *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; + *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; } +:move16 (d32)".l",(regan)+ is opbig=0xf6 & op37=1 & regan; d32 { local dst=regan&0xfffffff0; src:4=d32&0xfffffff0; regan=regan+16; + *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; + *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; } +:move16 (regan),(d32)".l" is opbig=0xf6 & op37=2 & regan; d32 { local src=regan&0xfffffff0; dst:4=d32&0xfffffff0; + *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; + *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; } +:move16 (d32)".l",(regan) is opbig=0xf6 & op37=3 & regan; d32 { local dst=regan&0xfffffff0; src:4=d32&0xfffffff0; + *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; + *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; } +@endif # MC68040 + +@ifdef COLDFIRE + +:mvs.b: eab, reg9dn is (op=0x7 & op68=4 & reg9dn )... &eab { reg9dn = sext(eab); } +:mvs.w: eaw, reg9dn is (op=0x7 & op68=5 & reg9dn )... &eaw { reg9dn = sext(eaw); } +:mvz.b: eab, reg9dn is (op=0x7 & op68=6 & reg9dn )... &eab { reg9dn = zext(eab); } +:mvz.w: eaw, reg9dn is (op=0x7 & op68=7 & reg9dn )... &eaw { reg9dn = zext(eaw); } +:mov3q "#"^d911, eal is (op=0xa & op68=5 & d911 ) ... &eal { eal = d911; } + +:sats.l regdn is opbig=0x4c & op37=0x10 & regdn { if (VF == 0) goto inst_next; regdn = (zext(regdn == 0 ) * 0x80000000) + (zext(regdn != 0) * 0x7fffffff); VF=0; CF=0; } + +skip_addr: skipAddr is op02=2 [skipAddr = inst_next + 2;] { export *[ram]:4 skipAddr; } +skip_addr: skipAddr is op02=3 [skipAddr = inst_next + 4;] { export *[ram]:4 skipAddr; } + +# TPF.w/l is occassionally used as a branch over a valid instruction. +:tpf is opbig=0x51 & op37=0x1f & op02=4 { } # nop +:tpf.w is opbig=0x51 & op37=0x1f & op02=2 & skip_addr { goto skip_addr; } # nop + 1 word +:tpf.l is opbig=0x51 & op37=0x1f & op02=3 & skip_addr { goto skip_addr; } # nop + 2 word +@endif # COLDFIRE + +# Tables for register lists, for the movem instruction + # Register to mememory, forward direction, via word +r2mfwf: D0w is D0w & mvm0=1 { *movemptr = D0w; movemptr = movemptr + 2; } +r2mfwf: is mvm0=0 { } +r2mfwe: r2mfwf" "D1w is D1w & mvm1=1 & r2mfwf { *movemptr = D1w; movemptr = movemptr + 2; } +r2mfwe: r2mfwf is mvm1=0 & r2mfwf { } +r2mfwd: r2mfwe" "D2w is D2w & mvm2=1 & r2mfwe { *movemptr = D2w; movemptr = movemptr + 2; } +r2mfwd: r2mfwe is mvm2=0 & r2mfwe { } +r2mfwc: r2mfwd" "D3w is D3w & mvm3=1 & r2mfwd { *movemptr = D3w; movemptr = movemptr + 2; } +r2mfwc: r2mfwd is mvm3=0 & r2mfwd { } +r2mfwb: r2mfwc" "D4w is D4w & mvm4=1 & r2mfwc { *movemptr = D4w; movemptr = movemptr + 2; } +r2mfwb: r2mfwc is mvm4=0 & r2mfwc { } +r2mfwa: r2mfwb" "D5w is D5w & mvm5=1 & r2mfwb { *movemptr = D5w; movemptr = movemptr + 2; } +r2mfwa: r2mfwb is mvm5=0 & r2mfwb { } +r2mfw9: r2mfwa" "D6w is D6w & mvm6=1 & r2mfwa { *movemptr = D6w; movemptr = movemptr + 2; } +r2mfw9: r2mfwa is mvm6=0 & r2mfwa { } +r2mfw8: r2mfw9" "D7w is D7w & mvm7=1 & r2mfw9 { *movemptr = D7w; movemptr = movemptr + 2; } +r2mfw8: r2mfw9 is mvm7=0 & r2mfw9 { } +r2mfw7: r2mfw8" "A0w is A0w & mvm8=1 & r2mfw8 { *movemptr = A0w; movemptr = movemptr + 2; } +r2mfw7: r2mfw8 is mvm8=0 & r2mfw8 { } +r2mfw6: r2mfw7" "A1w is A1w & mvm9=1 & r2mfw7 { *movemptr = A1w; movemptr = movemptr + 2; } +r2mfw6: r2mfw7 is mvm9=0 & r2mfw7 { } +r2mfw5: r2mfw6" "A2w is A2w & mvm10=1 & r2mfw6 { *movemptr = A2w; movemptr = movemptr + 2; } +r2mfw5: r2mfw6 is mvm10=0 & r2mfw6 { } +r2mfw4: r2mfw5" "A3w is A3w & mvm11=1 & r2mfw5 { *movemptr = A3w; movemptr = movemptr + 2; } +r2mfw4: r2mfw5 is mvm11=0 & r2mfw5 { } +r2mfw3: r2mfw4" "A4w is A4w & mvm12=1 & r2mfw4 { *movemptr = A4w; movemptr = movemptr + 2; } +r2mfw3: r2mfw4 is mvm12=0 & r2mfw4 { } +r2mfw2: r2mfw3" "A5w is A5w & mvm13=1 & r2mfw3 { *movemptr = A5w; movemptr = movemptr + 2; } +r2mfw2: r2mfw3 is mvm13=0 & r2mfw3 { } +r2mfw1: r2mfw2" "A6w is A6w & mvm14=1 & r2mfw2 { *movemptr = A6w; movemptr = movemptr + 2; } +r2mfw1: r2mfw2 is mvm14=0 & r2mfw2 { } +r2mfw0: { r2mfw1" "A7w} is A7w & mvm15=1 & r2mfw1 { *movemptr = A7w; movemptr = movemptr + 2; } +r2mfw0: { r2mfw1} is mvm15=0 & r2mfw1 { } + + + # Register to memory, forward direction, via long +r2mflf: D0 is D0 & mvm0=1 { *movemptr = D0; movemptr = movemptr + 4; } +r2mflf: is mvm0=0 { } +r2mfle: r2mflf" "D1 is D1 & mvm1=1 & r2mflf { *movemptr = D1; movemptr = movemptr + 4; } +r2mfle: r2mflf is mvm1=0 & r2mflf { } +r2mfld: r2mfle" "D2 is D2 & mvm2=1 & r2mfle { *movemptr = D2; movemptr = movemptr + 4; } +r2mfld: r2mfle is mvm2=0 & r2mfle { } +r2mflc: r2mfld" "D3 is D3 & mvm3=1 & r2mfld { *movemptr = D3; movemptr = movemptr + 4; } +r2mflc: r2mfld is mvm3=0 & r2mfld { } +r2mflb: r2mflc" "D4 is D4 & mvm4=1 & r2mflc { *movemptr = D4; movemptr = movemptr + 4; } +r2mflb: r2mflc is mvm4=0 & r2mflc { } +r2mfla: r2mflb" "D5 is D5 & mvm5=1 & r2mflb { *movemptr = D5; movemptr = movemptr + 4; } +r2mfla: r2mflb is mvm5=0 & r2mflb { } +r2mfl9: r2mfla" "D6 is D6 & mvm6=1 & r2mfla { *movemptr = D6; movemptr = movemptr + 4; } +r2mfl9: r2mfla is mvm6=0 & r2mfla { } +r2mfl8: r2mfl9" "D7 is D7 & mvm7=1 & r2mfl9 { *movemptr = D7; movemptr = movemptr + 4; } +r2mfl8: r2mfl9 is mvm7=0 & r2mfl9 { } +r2mfl7: r2mfl8" "A0 is A0 & mvm8=1 & r2mfl8 { *movemptr = A0; movemptr = movemptr + 4; } +r2mfl7: r2mfl8 is mvm8=0 & r2mfl8 { } +r2mfl6: r2mfl7" "A1 is A1 & mvm9=1 & r2mfl7 { *movemptr = A1; movemptr = movemptr + 4; } +r2mfl6: r2mfl7 is mvm9=0 & r2mfl7 { } +r2mfl5: r2mfl6" "A2 is A2 & mvm10=1 & r2mfl6 { *movemptr = A2; movemptr = movemptr + 4; } +r2mfl5: r2mfl6 is mvm10=0 & r2mfl6 { } +r2mfl4: r2mfl5" "A3 is A3 & mvm11=1 & r2mfl5 { *movemptr = A3; movemptr = movemptr + 4; } +r2mfl4: r2mfl5 is mvm11=0 & r2mfl5 { } +r2mfl3: r2mfl4" "A4 is A4 & mvm12=1 & r2mfl4 { *movemptr = A4; movemptr = movemptr + 4; } +r2mfl3: r2mfl4 is mvm12=0 & r2mfl4 { } +r2mfl2: r2mfl3" "A5 is A5 & mvm13=1 & r2mfl3 { *movemptr = A5; movemptr = movemptr + 4; } +r2mfl2: r2mfl3 is mvm13=0 & r2mfl3 { } +r2mfl1: r2mfl2" "A6 is A6 & mvm14=1 & r2mfl2 { *movemptr = A6; movemptr = movemptr + 4; } +r2mfl1: r2mfl2 is mvm14=0 & r2mfl2 { } +r2mfl0: { r2mfl1" "SP} is SP & mvm15=1 & r2mfl1 { *movemptr = SP; movemptr = movemptr + 4; } +r2mfl0: { r2mfl1} is mvm15=0 & r2mfl1 { } + + + # Register to memory, backward direction, via word +r2mbwf: A7w is A7w & mvm0=1 { movemptr = movemptr - 4; *movemptr = A7w; } +r2mbwf: is mvm0=0 { } +r2mbwe: r2mbwf" "A6w is A6w & mvm1=1 & r2mbwf { movemptr = movemptr - 4; *movemptr = A6w; } +r2mbwe: r2mbwf is mvm1=0 & r2mbwf { } +r2mbwd: r2mbwe" "A5w is A5w & mvm2=1 & r2mbwe { movemptr = movemptr - 4; *movemptr = A5w; } +r2mbwd: r2mbwe is mvm2=0 & r2mbwe { } +r2mbwc: r2mbwd" "A4w is A4w & mvm3=1 & r2mbwd { movemptr = movemptr - 4; *movemptr = A4w; } +r2mbwc: r2mbwd is mvm3=0 & r2mbwd { } +r2mbwb: r2mbwc" "A3w is A3w & mvm4=1 & r2mbwc { movemptr = movemptr - 4; *movemptr = A3w; } +r2mbwb: r2mbwc is mvm4=0 & r2mbwc { } +r2mbwa: r2mbwb" "A2w is A2w & mvm5=1 & r2mbwb { movemptr = movemptr - 4; *movemptr = A2w; } +r2mbwa: r2mbwb is mvm5=0 & r2mbwb { } +r2mbw9: r2mbwa" "A1w is A1w & mvm6=1 & r2mbwa { movemptr = movemptr - 4; *movemptr = A1w; } +r2mbw9: r2mbwa is mvm6=0 & r2mbwa { } +r2mbw8: r2mbw9" "A0w is A0w & mvm7=1 & r2mbw9 { movemptr = movemptr - 4; *movemptr = A0w; } +r2mbw8: r2mbw9 is mvm7=0 & r2mbw9 { } +r2mbw7: r2mbw8" "D7w is D7w & mvm8=1 & r2mbw8 { movemptr = movemptr - 4; *movemptr = D7w; } +r2mbw7: r2mbw8 is mvm8=0 & r2mbw8 { } +r2mbw6: r2mbw7" "D6w is D6w & mvm9=1 & r2mbw7 { movemptr = movemptr - 4; *movemptr = D6w; } +r2mbw6: r2mbw7 is mvm9=0 & r2mbw7 { } +r2mbw5: r2mbw6" "D5w is D5w & mvm10=1 & r2mbw6 { movemptr = movemptr - 4; *movemptr = D5w; } +r2mbw5: r2mbw6 is mvm10=0 & r2mbw6 { } +r2mbw4: r2mbw5" "D4w is D4w & mvm11=1 & r2mbw5 { movemptr = movemptr - 4; *movemptr = D4w; } +r2mbw4: r2mbw5 is mvm11=0 & r2mbw5 { } +r2mbw3: r2mbw4" "D3w is D3w & mvm12=1 & r2mbw4 { movemptr = movemptr - 4; *movemptr = D3w; } +r2mbw3: r2mbw4 is mvm12=0 & r2mbw4 { } +r2mbw2: r2mbw3" "D2w is D2w & mvm13=1 & r2mbw3 { movemptr = movemptr - 4; *movemptr = D2w; } +r2mbw2: r2mbw3 is mvm13=0 & r2mbw3 { } +r2mbw1: r2mbw2" "D1w is D1w & mvm14=1 & r2mbw2 { movemptr = movemptr - 4; *movemptr = D1w; } +r2mbw1: r2mbw2 is mvm14=0 & r2mbw2 { } +r2mbw0: { r2mbw1" "D0w} is D0w & mvm15=1 & r2mbw1 { movemptr = movemptr - 4; *movemptr = D0w; } +r2mbw0: { r2mbw1} is mvm15=0 & r2mbw1 { } + + + # Register to memory, backward direction, via long +r2mblf: SP is SP & mvm0=1 { movemptr = movemptr - 4; *movemptr = SP; } +r2mblf: is mvm0=0 { } +r2mble: r2mblf" "A6 is A6 & mvm1=1 & r2mblf { movemptr = movemptr - 4; *movemptr = A6; } +r2mble: r2mblf is mvm1=0 & r2mblf { } +r2mbld: r2mble" "A5 is A5 & mvm2=1 & r2mble { movemptr = movemptr - 4; *movemptr = A5; } +r2mbld: r2mble is mvm2=0 & r2mble { } +r2mblc: r2mbld" "A4 is A4 & mvm3=1 & r2mbld { movemptr = movemptr - 4; *movemptr = A4; } +r2mblc: r2mbld is mvm3=0 & r2mbld { } +r2mblb: r2mblc" "A3 is A3 & mvm4=1 & r2mblc { movemptr = movemptr - 4; *movemptr = A3; } +r2mblb: r2mblc is mvm4=0 & r2mblc { } +r2mbla: r2mblb" "A2 is A2 & mvm5=1 & r2mblb { movemptr = movemptr - 4; *movemptr = A2; } +r2mbla: r2mblb is mvm5=0 & r2mblb { } +r2mbl9: r2mbla" "A1 is A1 & mvm6=1 & r2mbla { movemptr = movemptr - 4; *movemptr = A1; } +r2mbl9: r2mbla is mvm6=0 & r2mbla { } +r2mbl8: r2mbl9" "A0 is A0 & mvm7=1 & r2mbl9 { movemptr = movemptr - 4; *movemptr = A0; } +r2mbl8: r2mbl9 is mvm7=0 & r2mbl9 { } +r2mbl7: r2mbl8" "D7 is D7 & mvm8=1 & r2mbl8 { movemptr = movemptr - 4; *movemptr = D7; } +r2mbl7: r2mbl8 is mvm8=0 & r2mbl8 { } +r2mbl6: r2mbl7" "D6 is D6 & mvm9=1 & r2mbl7 { movemptr = movemptr - 4; *movemptr = D6; } +r2mbl6: r2mbl7 is mvm9=0 & r2mbl7 { } +r2mbl5: r2mbl6" "D5 is D5 & mvm10=1 & r2mbl6 { movemptr = movemptr - 4; *movemptr = D5; } +r2mbl5: r2mbl6 is mvm10=0 & r2mbl6 { } +r2mbl4: r2mbl5" "D4 is D4 & mvm11=1 & r2mbl5 { movemptr = movemptr - 4; *movemptr = D4; } +r2mbl4: r2mbl5 is mvm11=0 & r2mbl5 { } +r2mbl3: r2mbl4" "D3 is D3 & mvm12=1 & r2mbl4 { movemptr = movemptr - 4; *movemptr = D3; } +r2mbl3: r2mbl4 is mvm12=0 & r2mbl4 { } +r2mbl2: r2mbl3" "D2 is D2 & mvm13=1 & r2mbl3 { movemptr = movemptr - 4; *movemptr = D2; } +r2mbl2: r2mbl3 is mvm13=0 & r2mbl3 { } +r2mbl1: r2mbl2" "D1 is D1 & mvm14=1 & r2mbl2 { movemptr = movemptr - 4; *movemptr = D1; } +r2mbl1: r2mbl2 is mvm14=0 & r2mbl2 { } +r2mbl0: { r2mbl1" "D0} is D0 & mvm15=1 & r2mbl1 { movemptr = movemptr - 4; *movemptr = D0; } +r2mbl0: { r2mbl1} is mvm15=0 & r2mbl1 { } + + + # Memory to register, forward direction, via word +m2rfwf: D0 is D0 & mvm0=1 { D0 = sext(*:2 movemptr); movemptr = movemptr + 2; } +m2rfwf: is mvm0=0 { } +m2rfwe: m2rfwf" "D1 is D1 & mvm1=1 & m2rfwf { D1 = sext(*:2 movemptr); movemptr = movemptr + 2; } +m2rfwe: m2rfwf is mvm1=0 & m2rfwf { } +m2rfwd: m2rfwe" "D2 is D2 & mvm2=1 & m2rfwe { D2 = sext(*:2 movemptr); movemptr = movemptr + 2; } +m2rfwd: m2rfwe is mvm2=0 & m2rfwe { } +m2rfwc: m2rfwd" "D3 is D3 & mvm3=1 & m2rfwd { D3 = sext(*:2 movemptr); movemptr = movemptr + 2; } +m2rfwc: m2rfwd is mvm3=0 & m2rfwd { } +m2rfwb: m2rfwc" "D4 is D4 & mvm4=1 & m2rfwc { D4 = sext(*:2 movemptr); movemptr = movemptr + 2; } +m2rfwb: m2rfwc is mvm4=0 & m2rfwc { } +m2rfwa: m2rfwb" "D5 is D5 & mvm5=1 & m2rfwb { D5 = sext(*:2 movemptr); movemptr = movemptr + 2; } +m2rfwa: m2rfwb is mvm5=0 & m2rfwb { } +m2rfw9: m2rfwa" "D6 is D6 & mvm6=1 & m2rfwa { D6 = sext(*:2 movemptr); movemptr = movemptr + 2; } +m2rfw9: m2rfwa is mvm6=0 & m2rfwa { } +m2rfw8: m2rfw9" "D7 is D7 & mvm7=1 & m2rfw9 { D7 = sext(*:2 movemptr); movemptr = movemptr + 2; } +m2rfw8: m2rfw9 is mvm7=0 & m2rfw9 { } +m2rfw7: m2rfw8" "A0 is A0 & mvm8=1 & m2rfw8 { A0 = sext(*:2 movemptr); movemptr = movemptr + 2; } +m2rfw7: m2rfw8 is mvm8=0 & m2rfw8 { } +m2rfw6: m2rfw7" "A1 is A1 & mvm9=1 & m2rfw7 { A1 = sext(*:2 movemptr); movemptr = movemptr + 2; } +m2rfw6: m2rfw7 is mvm9=0 & m2rfw7 { } +m2rfw5: m2rfw6" "A2 is A2 & mvm10=1 & m2rfw6 { A2 = sext(*:2 movemptr); movemptr = movemptr + 2; } +m2rfw5: m2rfw6 is mvm10=0 & m2rfw6 { } +m2rfw4: m2rfw5" "A3 is A3 & mvm11=1 & m2rfw5 { A3 = sext(*:2 movemptr); movemptr = movemptr + 2; } +m2rfw4: m2rfw5 is mvm11=0 & m2rfw5 { } +m2rfw3: m2rfw4" "A4 is A4 & mvm12=1 & m2rfw4 { A4 = sext(*:2 movemptr); movemptr = movemptr + 2; } +m2rfw3: m2rfw4 is mvm12=0 & m2rfw4 { } +m2rfw2: m2rfw3" "A5 is A5 & mvm13=1 & m2rfw3 { A5 = sext(*:2 movemptr); movemptr = movemptr + 2; } +m2rfw2: m2rfw3 is mvm13=0 & m2rfw3 { } +m2rfw1: m2rfw2" "A6 is A6 & mvm14=1 & m2rfw2 { A6 = sext(*:2 movemptr); movemptr = movemptr + 2; } +m2rfw1: m2rfw2 is mvm14=0 & m2rfw2 { } +m2rfw0: { m2rfw1" "SP} is SP & mvm15=1 & m2rfw1 { SP = sext(*:2 movemptr); movemptr = movemptr + 2; } +m2rfw0: { m2rfw1} is mvm15=0 & m2rfw1 { } + + + + # Memory to register, forward direction, via long +m2rflf: D0 is D0 & mvm0=1 { D0 = *movemptr; movemptr = movemptr + 4; } +m2rflf: is mvm0=0 { } +m2rfle: m2rflf" "D1 is D1 & mvm1=1 & m2rflf { D1 = *movemptr; movemptr = movemptr + 4; } +m2rfle: m2rflf is mvm1=0 & m2rflf { } +m2rfld: m2rfle" "D2 is D2 & mvm2=1 & m2rfle { D2 = *movemptr; movemptr = movemptr + 4; } +m2rfld: m2rfle is mvm2=0 & m2rfle { } +m2rflc: m2rfld" "D3 is D3 & mvm3=1 & m2rfld { D3 = *movemptr; movemptr = movemptr + 4; } +m2rflc: m2rfld is mvm3=0 & m2rfld { } +m2rflb: m2rflc" "D4 is D4 & mvm4=1 & m2rflc { D4 = *movemptr; movemptr = movemptr + 4; } +m2rflb: m2rflc is mvm4=0 & m2rflc { } +m2rfla: m2rflb" "D5 is D5 & mvm5=1 & m2rflb { D5 = *movemptr; movemptr = movemptr + 4; } +m2rfla: m2rflb is mvm5=0 & m2rflb { } +m2rfl9: m2rfla" "D6 is D6 & mvm6=1 & m2rfla { D6 = *movemptr; movemptr = movemptr + 4; } +m2rfl9: m2rfla is mvm6=0 & m2rfla { } +m2rfl8: m2rfl9" "D7 is D7 & mvm7=1 & m2rfl9 { D7 = *movemptr; movemptr = movemptr + 4; } +m2rfl8: m2rfl9 is mvm7=0 & m2rfl9 { } +m2rfl7: m2rfl8" "A0 is A0 & mvm8=1 & m2rfl8 { A0 = *movemptr; movemptr = movemptr + 4; } +m2rfl7: m2rfl8 is mvm8=0 & m2rfl8 { } +m2rfl6: m2rfl7" "A1 is A1 & mvm9=1 & m2rfl7 { A1 = *movemptr; movemptr = movemptr + 4; } +m2rfl6: m2rfl7 is mvm9=0 & m2rfl7 { } +m2rfl5: m2rfl6" "A2 is A2 & mvm10=1 & m2rfl6 { A2 = *movemptr; movemptr = movemptr + 4; } +m2rfl5: m2rfl6 is mvm10=0 & m2rfl6 { } +m2rfl4: m2rfl5" "A3 is A3 & mvm11=1 & m2rfl5 { A3 = *movemptr; movemptr = movemptr + 4; } +m2rfl4: m2rfl5 is mvm11=0 & m2rfl5 { } +m2rfl3: m2rfl4" "A4 is A4 & mvm12=1 & m2rfl4 { A4 = *movemptr; movemptr = movemptr + 4; } +m2rfl3: m2rfl4 is mvm12=0 & m2rfl4 { } +m2rfl2: m2rfl3" "A5 is A5 & mvm13=1 & m2rfl3 { A5 = *movemptr; movemptr = movemptr + 4; } +m2rfl2: m2rfl3 is mvm13=0 & m2rfl3 { } +m2rfl1: m2rfl2" "A6 is A6 & mvm14=1 & m2rfl2 { A6 = *movemptr; movemptr = movemptr + 4; } +m2rfl1: m2rfl2 is mvm14=0 & m2rfl2 { } +m2rfl0: { m2rfl1" "SP} is SP & mvm15=1 & m2rfl1 { SP = *movemptr; movemptr = movemptr + 4; } +m2rfl0: { m2rfl1} is mvm15=0 & m2rfl1 { } + + + +:movem.w r2mfw0,(regan) is opbig=0x48 & op67=2 & mode=2 & regan; r2mfw0 { movemptr = regan; build r2mfw0; } +:movem.w r2mbw0,-(regan) is opbig=0x48 & op67=2 & mode=4 & regan; r2mbw0 { movemptr = regan; build r2mbw0; regan = movemptr; } +:movem.w r2mfw0,(d16,regan) is opbig=0x48 & op67=2 & mode=5 & regan; r2mfw0; d16 { movemptr = regan+d16; build r2mfw0; } +:movem.w r2mfw0,(extw) is opbig=0x48 & op67=2 & mode=6 & regan; r2mfw0; extw [ pcmode=0; regtfan=regan; ] { build extw; movemptr = extw; build r2mfw0; } +:movem.w r2mfw0,(d16)".w" is opbig=0x48 & op67=2 & mode=7 & regan=0; r2mfw0; d16 { movemptr = d16; build r2mfw0; } +:movem.w r2mfw0,(d32)".l" is opbig=0x48 & op67=2 & mode=7 & regan=1; r2mfw0; d32 { movemptr = d32; build r2mfw0; } +:movem.l r2mfl0,(regan) is opbig=0x48 & op67=3 & mode=2 & regan; r2mfl0 { movemptr = regan; build r2mfl0; } +:movem.l r2mbl0,-(regan) is opbig=0x48 & op67=3 & mode=4 & regan; r2mbl0 { movemptr = regan; build r2mbl0; regan = movemptr; } +:movem.l r2mfl0,(d16,regan) is opbig=0x48 & op67=3 & mode=5 & regan; r2mfl0; d16 { movemptr = regan+d16; build r2mfl0; } +:movem.l r2mfl0,(extw) is opbig=0x48 & op67=3 & mode=6 & regan; r2mfl0; extw [ pcmode=0; regtfan=regan; ] { build extw; movemptr = extw; build r2mfl0; } +:movem.l r2mfl0,(d16)".w" is opbig=0x48 & op67=3 & mode=7 & regan=0; r2mfl0; d16 { movemptr = d16; build r2mfl0; } +:movem.l r2mfl0,(d32)".l" is opbig=0x48 & op67=3 & mode=7 & regan=1; r2mfl0; d32 { movemptr = d32; build r2mfl0; } + +:movem.w (regan),m2rfw0 is opbig=0x4c & op67=2 & mode=2 & regan; m2rfw0 { movemptr = regan; build m2rfw0; } +:movem.w (regan)+,m2rfw0 is opbig=0x4c & op67=2 & mode=3 & regan; m2rfw0 { movemptr = regan; build m2rfw0; regan = movemptr; } +:movem.w (d16,regan),m2rfw0 is opbig=0x4c & op67=2 & mode=5 & regan; m2rfw0; d16 { movemptr = regan+d16; build m2rfw0; } +:movem.w (extw),m2rfw0 is opbig=0x4c & op67=2 & mode=6 & regan; m2rfw0; extw [ pcmode=0; regtfan=regan; ] { build extw; movemptr = extw; build m2rfw0; } +:movem.w (d16,PC),m2rfw0 is opbig=0x4c & op67=2 & mode=7 & regan=2; m2rfw0; d16 & PC { movemptr = inst_start+2+d16; build m2rfw0; } +:movem.w (extw),m2rfw0 is opbig=0x4c & op67=2 & mode=7 & regan=3; m2rfw0; extw [ pcmode=1; ] { build extw; movemptr = extw; build m2rfw0; } +:movem.w (d16)".w",m2rfw0 is opbig=0x4c & op67=2 & mode=7 & regan=0; m2rfw0; d16 { movemptr = d16; build m2rfw0; } +:movem.w (d32)".l",m2rfw0 is opbig=0x4c & op67=2 & mode=7 & regan=1; m2rfw0; d32 { movemptr = d32; build m2rfw0; } +:movem.l (regan),m2rfl0 is opbig=0x4c & op67=3 & mode=2 & regan; m2rfl0 { movemptr = regan; build m2rfl0; } +:movem.l (regan)+,m2rfl0 is opbig=0x4c & op67=3 & mode=3 & regan; m2rfl0 { movemptr = regan; build m2rfl0; regan = movemptr; } +:movem.l (d16,regan),m2rfl0 is opbig=0x4c & op67=3 & mode=5 & regan; m2rfl0; d16 { movemptr = regan+d16; build m2rfl0; } +:movem.l (extw),m2rfl0 is opbig=0x4c & op67=3 & mode=6 & regan; m2rfl0; extw [ pcmode=0; regtfan=regan; ] { build extw; movemptr = extw; build m2rfl0; } +:movem.l (d16,PC),m2rfl0 is opbig=0x4c & op67=3 & mode=7 & regan=2; m2rfl0; d16 & PC { movemptr = inst_start+2+d16; build m2rfl0; } +:movem.l (extw),m2rfl0 is opbig=0x4c & op67=3 & mode=7 & regan=3; m2rfl0; extw [ pcmode=1; ] { build extw; movemptr = extw; build m2rfl0; } +:movem.l (d16)".w",m2rfl0 is opbig=0x4c & op67=3 & mode=7 & regan=0; m2rfl0; d16 { movemptr = d16; build m2rfl0; } +:movem.l (d32)".l",m2rfl0 is opbig=0x4c & op67=3 & mode=7 & regan=1; m2rfl0; d32 { movemptr = d32; build m2rfl0; } + +:movep.w (d16,regan),reg9dnw is op=0 & reg9dnw & op68=4 & op35=1 & regan; d16 { src:4 = (regan + d16); ho:1 = *:1 src; lo:1 = *:1(src+2); reg9dnw = (zext(ho) << 8) | zext(lo); } +:movep.l (d16,regan),reg9dn is op=0 & reg9dn & op68=5 & op35=1 & regan; d16 { src:4 = (regan + d16); ho:1 = *:1 src; mu:1 = *:1(src+2); ml:1 = *(src+4); lo:1 = *:1(src+6); reg9dn = (zext(ho) << 24) | (zext(mu) << 16) | (zext(ml) << 8) | zext(lo); } +:movep.w reg9dnw,(d16,regan) is op=0 & reg9dnw & op68=6 & op35=1 & regan; d16 { src:4 = (regan + d16); local tmp = (reg9dnw >> 8); *:1 src = tmp:1; src = src+2; *:1 src = reg9dnw:1; } +:movep.l reg9dn,(d16,regan) is op=0 & reg9dn & op68=7 & op35=1 & regan; d16 { src:4 = (regan + d16); local tmp = (reg9dn >> 24); *:1 src = tmp:1; src = src+2; tmp = (reg9dn >> 16); *:1 src = tmp:1; src = src+2; tmp = (reg9dn >> 8); *:1 src = tmp:1; src = src+2; *:1 src = reg9dn:1; } + + +:moveq "#"^d8base,reg9dn is op=7 & reg9dn & op8=0 & d8base { reg9dn = d8base; resflags(reg9dn); logflags(); } + +:moves.b rreg,e2b is opbig=0x0e & op67=0 & mode & regan; rreg & wl=1; e2b [ regtsan=regan; savmod2=mode; ] { e2b = rreg:1; } +:moves.w rreg,e2w is opbig=0x0e & op67=1 & mode & regan; rreg & wl=1; e2w [ regtsan=regan; savmod2=mode; ] { e2w = rreg:2; } +:moves.l rreg,e2l is opbig=0x0e & op67=2 & mode & regan; rreg & wl=1; e2l [ regtsan=regan; savmod2=mode; ] { e2l = rreg; } +:moves.b e2b,rreg is opbig=0x0e & op67=0 & mode & regan; da=0 & rreg & wl=0; e2b [ regtsan=regan; savmod2=mode; ] { rreg = (rreg & 0xffffff00) | zext(e2b); } +:moves.w e2w,rreg is opbig=0x0e & op67=1 & mode & regan; da=0 & rreg & wl=0; e2w [ regtsan=regan; savmod2=mode; ] { rreg = (rreg & 0xffff0000) | zext(e2w); } +:moves.b e2b,rreg is opbig=0x0e & op67=0 & mode & regan; da=1 & rreg & wl=0; e2b [ regtsan=regan; savmod2=mode; ] { rreg = sext(e2b); } +:moves.w e2w,rreg is opbig=0x0e & op67=1 & mode & regan; da=1 & rreg & wl=0; e2w [ regtsan=regan; savmod2=mode; ] { rreg = sext(e2w); } +:moves.l e2l,rreg is opbig=0x0e & op67=2 & mode & regan; rreg & wl=0; e2l [ regtsan=regan; savmod2=mode; ] { rreg = e2l; } + +:muls.w eaw,reg9dn is (op=12 & reg9dn & op68=7)... & eaw { tmp1:4 = sext( reg9dn:2 ); tmp2:4 = sext(eaw); + reg9dn = tmp1 * tmp2; resflags(reg9dn); CF=0; VF=0; } + +:mulu.w eaw,reg9dn is (op=12 & reg9dn & op68=3)... & eaw { tmp1:4 = zext( reg9dn:2 ); tmp2:4 = zext(eaw); + reg9dn = tmp1 * tmp2; resflags(reg9dn); CF=0; VF=0; } + +mulsize: "s.l" is divsgn=1 { } +mulsize: "u.l" is divsgn=0 { } + +submul: regdq is regdq & divsgn=1 & divsz=0 { regdq = glbdenom * regdq; resflags(regdq); CF=0; } +submul: regdr-regdq is regdq & divsgn=1 & divsz=1 & regdr { tmp1:8 = sext(glbdenom); tmp2:8 = sext(regdq); local res=tmp1*tmp2; regdq=res:4; + regdr=res(4); resflags(res); CF=0; VF=0; } +submul: regdq is regdq & divsgn=0 & divsz=0 { regdq = glbdenom * regdq; resflags(regdq); CF=0; } +submul: regdr-regdq is regdq & divsgn=0 & divsz=1 & regdr { tmp1:8 = zext(glbdenom); tmp2:8 = zext(regdq); local res=tmp1*tmp2; regdq=res:4; + regdr=res(4); resflags(res); CF=0; VF=0; } +:mul^mulsize e2l,submul is opbig=0x4c & op67=0 & $(DAT_ALTER_ADDR_MODES); submul & mulsize; e2l [ savmod2=savmod1; regtsan=regtfan; ] { glbdenom=e2l; build submul; } + +:nbcd eab is (opbig=0x48 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab +{ tmp:1 = eab; CF = (tmp != 0) || (XF == 1); tmp = 0 - tmp - XF; eab = bcdAdjust(tmp); bcdflags(tmp); } + + +# NB: For the neg insn the CF carry flag is not set like other insns, from the manual: +# XF - Set the same as the carry bit. +# NF - Set if the result is negative; cleared otherwise. +# ZF - Set if the result is zero; cleared otherwise. +# VF - Set if an overflow occurs; cleared otherwise. +# CF - Cleared if the result is zero; set otherwise. + +macro negFlags(op1) { + VF = sborrow(0, op1); +} + +macro negResFlags(result) { + NF = result s< 0; + CF = result != 0; + XF = CF; + ZF = result == 0; +} + +:neg.b eab is (opbig=0x44 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab + { o2:1=eab; negFlags(o2); o2 = -o2; eab=o2; negResFlags(o2); } +:neg.w eaw is (opbig=0x44 & op67=1 & $(DAT_ALTER_ADDR_MODES))... & eaw + { o2:2=eaw; negFlags(o2); o2 = -o2; eaw=o2; negResFlags(o2); } +:neg.l eal is (opbig=0x44 & op67=2 & $(DAT_ALTER_ADDR_MODES))... & eal + { o2:4=eal; negFlags(o2); o2 = -o2; eal=o2; negResFlags(o2); } + +# NB: For the negx insn the CF and ZF flags are not set like other insns, from the manual: +# XF - Set the same as the carry bit. +# NF - Set if the result is negative; cleared otherwise. +# ZF - Cleared if the result is nonzero; unchanged otherwise. +# VF - Set if an overflow occurs; cleared otherwise. +# CF - Set if borrow occurs; otherwise. + +:negx.b eab is (opbig=0x40 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab + { local tmp = eab + XF; negxsubflags(tmp); tmp = -tmp; eab=tmp; extendedResultFlags(tmp); } +:negx.w eaw is (opbig=0x40 & op67=1 & $(DAT_ALTER_ADDR_MODES))... & eaw + { local tmp = eaw + zext(XF); negxsubflags(tmp); tmp = -tmp; eaw=tmp; extendedResultFlags(tmp); } +:negx.l eal is (opbig=0x40 & op67=2 & $(DAT_ALTER_ADDR_MODES))... & eal + { local tmp = eal + zext(XF); negxsubflags(tmp); tmp = -tmp; eal=tmp; extendedResultFlags(tmp); } + +:nop is opbig=0x4e & op37=14 & op02=1 { } + +:not.b eab is (opbig=0x46 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab { logflags(); eab = ~eab; resflags(eab); } +:not.w eaw is (opbig=0x46 & op67=1 & $(DAT_ALTER_ADDR_MODES))... & eaw { logflags(); eaw = ~eaw; resflags(eaw); } +:not.l eal is (opbig=0x46 & op67=2 & $(DAT_ALTER_ADDR_MODES))... & eal { logflags(); eal = ~eal; resflags(eal); } + +:or.b eab,reg9dnb is (op=8 & reg9dnb & op68=0 & $(DAT_ALTER_ADDR_MODES))... & eab { logflags(); reg9dnb = reg9dnb | eab; resflags(reg9dnb); } +:or.w eaw,reg9dnw is (op=8 & reg9dnw & op68=1 & $(DAT_ALTER_ADDR_MODES))... & eaw { logflags(); reg9dnw = reg9dnw | eaw; resflags(reg9dnw); } +:or.l eal,reg9dn is (op=8 & reg9dn & op68=2 & $(DAT_ALTER_ADDR_MODES))... & eal { logflags(); reg9dn = reg9dn | eal; resflags(reg9dn); } + +:or.b reg9dnb,eab is (op=8 & reg9dnb & op68=4 & $(MEM_ALTER_ADDR_MODES))... & eab { logflags(); eab = eab | reg9dnb; resflags(eab); } +:or.w reg9dnw,eaw is (op=8 & reg9dnw & op68=5 & $(MEM_ALTER_ADDR_MODES))... & eaw { logflags(); eaw = eaw | reg9dnw; resflags(eaw); } +:or.l reg9dn,eal is (op=8 & reg9dn & op68=6 & $(MEM_ALTER_ADDR_MODES))... & eal { logflags(); eal = eal | reg9dn; resflags(eal); } + +:ori.b "#"^d8,e2b is opbig=0 & op67=0 & $(DAT_ALTER_ADDR_MODES); d8; e2b [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); e2b = e2b | d8; resflags(e2b); } +:ori.w "#"^d16,e2w is opbig=0 & op67=1 & $(DAT_ALTER_ADDR_MODES); d16; e2w [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); e2w = e2w | d16; resflags(e2w); } +:ori.l "#"^d32,e2l is opbig=0 & op67=2 & $(DAT_ALTER_ADDR_MODES); d32; e2l [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); e2l = e2l | d32; resflags(e2l); } +:ori "#"^d8,"CCR" is opbig=0 & op37=7 & op02=4; d8 { packflags(SR); SR=SR|d8; unpackflags(SR); } +:ori "#"^d16,SR is SR; opbig=0x00 & d8base=0x7c; d16 { packflags(SR); SR=SR|d16; unpackflags(SR); } + +:pack Tyw,Txw,"#"d16 is op=8 & op48=20 & Txw & Tyw & rmbit=0; d16 { + local value = (Tyw & 0x0F0F) + d16; + Txw = (Txw & 0xFF00) | ((value & 0x0F00) >> 4) | (value & 0x000F); +} + +:pack Tyw,Txb,"#"d16 is op=8 & op48=20 & Tyw & Txb & rmbit=1; d16 { + local value = (Tyw & 0x0F0F) + d16; + local result:2 = ((value & 0x0F00) >> 4) | (value & 0x000F); + Txb = result:1; +} + +:pea eaptr is (opbig=0x48 & op67=1 & $(CTL_ADDR_MODES))... & eaptr { SP = SP-4; *SP = eaptr; } + +@ifdef MC68040 + +:pflushn "("^regan^")" is opbig=0xf5 & op67=0 & op5=0 & op34=0 & regan unimpl +:pflush "("^regan^")" is opbig=0xf5 & op67=0 & op5=0 & op34=1 & regan unimpl +:pflushan is opbig=0xf5 & op67=0 & op5=0 & op34=2 & regan=0 unimpl +:pflusha is opbig=0xf5 & op67=0 & op5=0 & op34=3 & regan=0 unimpl + +@endif # MC68040 + +@ifdef MC68030 + +:pflusha is opbig=0xf0 & op67=0 & mode=0 & regan=0; opx015=0x2400 unimpl + +FC: SFC is fc4=0 & fc3=0 & fc02=0 & SFC { export SFC; } +FC: DFC is fc4=0 & fc3=0 & fc02=1 & DFC { export DFC; } +FC: regdc is fc4=0 & fc3=1 & regdc { export regdc; } +FC: "#"^fc03 is fc4=1 & fc3=0 & fc03 { export *[const]:4 fc03; } + +FCmask: "#"^fcmask is fcmask { export *[const]:1 fcmask; } + +:pflush FC,FCmask is opbig=0xf0 & op67=0 & mode=0 & regan=0; bigopx=0x30 & FCmask & FC unimpl + +:pflush FC,FCmask,e2l is opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); bigopx=0x38 & FCmask & FC; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl + +:ploadr FC,e2l is opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx515=0x110 & FC; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl + +:ploadw FC,e2l is opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx515=0x100 & FC; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl + +:pmove.l TC,e2l is TC & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=0 & rwx=1 & fbit=0 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:pmove.l e2l,TC is TC & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=0 & rwx=0 & fbit=0 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:pmovefd.l e2l,TC is TC & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=0 & rwx=0 & fbit=1 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl + +:pmove.d SRP,e2d is SRP & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=2 & rwx=1 & fbit=0 & d8=0; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:pmove.d e2d,SRP is SRP & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=2 & rwx=0 & fbit=0 & d8=0; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:pmovefd.d e2d,SRP is SRP & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=2 & rwx=0 & fbit=1 & d8=0; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl + +:pmove.d CRP,e2d is CRP & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=3 & rwx=1 & fbit=0 & d8=0; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:pmove.d e2d,CRP is CRP & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=3 & rwx=0 & fbit=0 & d8=0; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:pmovefd.d e2d,CRP is CRP & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=3 & rwx=0 & fbit=1 & d8=0; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl + +:pmove.w MMUSR,e2w is MMUSR & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=3 & mregn=0 & rwx=1 & fbit=0 & d8=0; e2w [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:pmove.w e2w,MMUSR is MMUSR & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=3 & mregn=0 & rwx=0 & fbit=0 & d8=0; e2w [ savmod2=savmod1; regtsan=regtfan; ] unimpl + +:pmove.l TT0,e2l is TT0 & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=2 & rwx=1 & fbit=0 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:pmove.l e2l,TT0 is TT0 & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=2 & rwx=0 & fbit=0 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:pmovefd.l e2l,TT0 is TT0 & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=2 & rwx=0 & fbit=1 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl + +:pmove.l TT1,e2l is TT1 & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=3 & rwx=1 & fbit=0 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:pmove.l e2l,TT1 is TT1 & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=3 & rwx=0 & fbit=0 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:pmovefd.l e2l,TT1 is TT1 & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=3 & rwx=0 & fbit=1 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl + +#TODO: MC68EC030 only - conflicts with MMUSR form above +#:pmove.w ACUSR,e2w is ACUSR & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=3 & mregn=0 & rwx=1 & fbit=0 & d8=0; e2w [ savmod2=savmod1; regtsan=regtfan; ] unimpl +#:pmove.w e2w,ACUSR is ACUSR & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=3 & mregn=0 & rwx=0 & fbit=0 & d8=0; e2w [ savmod2=savmod1; regtsan=regtfan; ] unimpl + +#TODO: MC68EC030 only - - conflicts with TTx form above +#:pmove.l ACx,e2l is ACx & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=? & rwx=1 & fbit=0 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +#:pmove.l e2l,ACx is ACx & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=? & rwx=0 & fbit=0 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +#:pmovefd.l e2l,ACx is ACx & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=? & rwx=0 & fbit=1 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl + +@endif # MC68030 + +#TODO: PMOVE PMMU Register - MC68851 only + +#TODO: PRESTORE PMMU Register - MC68851 only + +#TODO: PSAVE PMMU Register - MC68851 only + +#TODO: PScc PMMU Register - MC68851 only + +@ifdef MC68030 + +ptestLevel: "#"^mregn is mregn { export *[const]:1 mregn; } + +:ptestr FC,e2l,ptestLevel is opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=4 & ptestLevel & rwx=1 & fbit=0 & aregx=0 & FC; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:ptestr FC,e2l,ptestLevel,aregx is opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=4 & ptestLevel & rwx=1 & fbit=1 & aregx & FC; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl + +:ptestw FC,e2l,ptestLevel is opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=4 & ptestLevel & rwx=0 & fbit=0 & aregx=0 & FC; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:ptestw FC,e2l,ptestLevel,aregx is opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=4 & ptestLevel & rwx=0 & fbit=1 & aregx & FC; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl + +@endif # MC68030 + +#TODO: PTEST FC, - MC68EX030 only + +#TODO: PTEST FC,,#level,(An) - MC68851 only + +@ifdef MC68040 + +:ptestr "("^regan^")" is opbig=0xf5 & op67=1 & op35=5 & regan unimpl +:ptestw "("^regan^")" is opbig=0xf5 & op67=1 & op35=1 & regan unimpl + +@endif # MC68040 + +#TODO: PTRAPcc - MC68851 only + +#TODO: PVALID - MC68851 only + +:reset is d16=0x4e70 { reset(); } + +:rol.b cntreg,regdnb is op=14 & cntreg & op8=1 & op67=0 & op34=3 & regdnb { rotateLeft(cntreg, regdnb, 8); } +:rol.w cntreg,regdnw is op=14 & cntreg & op8=1 & op67=1 & op34=3 & regdnw { rotateLeft(cntreg, regdnw, 16); } +:rol.l cntreg,regdn is op=14 & cntreg & op8=1 & op67=2 & op34=3 & regdn { rotateLeft(cntreg, regdn, 32); } +:rol eaw is (opbig=0xe7 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw { + local value:2 = eaw; + value = (value << 1) | (value >> 15); + getbit(CF, value, 0); + resflags(value); + eaw = value; + VF = 0; +} + +:ror.b cntreg,regdnb is op=14 & cntreg & op8=0 & op67=0 & op34=3 & regdnb { rotateRight(cntreg, regdnb, 8); } +:ror.w cntreg,regdnw is op=14 & cntreg & op8=0 & op67=1 & op34=3 & regdnw { rotateRight(cntreg, regdnw, 16); } +:ror.l cntreg,regdn is op=14 & cntreg & op8=0 & op67=2 & op34=3 & regdn { rotateRight(cntreg, regdn, 32); } +:ror eaw is (opbig=0xe6 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw { + local value:2 = eaw; + value = (value << 15) | (value >> 1); + getbit(CF, value, 15); + resflags(value); + eaw = value; + VF = 0; +} + +:roxl.b cntreg,regdnb is op=14 & cntreg & op8=1 & op67=0 & op34=2 & regdnb { rotateLeftExtended(cntreg, regdnb, 8); } +:roxl.w cntreg,regdnw is op=14 & cntreg & op8=1 & op67=1 & op34=2 & regdnw { rotateLeftExtended(cntreg, regdnw, 16); } +:roxl.l cntreg,regdn is op=14 & cntreg & op8=1 & op67=2 & op34=2 & regdn { rotateLeftExtended(cntreg, regdn, 32); } +:roxl eaw is (opbig=0xe5 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw { + local value:2 = eaw; + local xflag = (value & 0x8000) != 0; + value = (value << 1) | zext(XF); + resflags(value); + eaw = value; + VF = 0; + XF = xflag; + CF = XF; +} + +:roxr.b cntreg,regdnb is op=14 & cntreg & op8=0 & op67=0 & op34=2 & regdnb { rotateRightExtended(cntreg, regdnb, 8); } +:roxr.w cntreg,regdnw is op=14 & cntreg & op8=0 & op67=1 & op34=2 & regdnw { rotateRightExtended(cntreg, regdnw, 16); } +:roxr.l cntreg,regdn is op=14 & cntreg & op8=0 & op67=2 & op34=2 & regdn { rotateRightExtended(cntreg, regdn, 32); } +:roxr eaw is (opbig=0xe4 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw { + local value:2 = eaw; + local xflag = (value & 0x0001) != 0; + value = (zext(XF) << 15) | (value >> 1); + resflags(value); + eaw = value; + VF = 0; + XF = xflag; + CF = XF; +} + +:rtd "#"^d16 is opbig=0x4e & op37=14 & op02=4; d16 { PC = *SP; SP = SP + 4 + d16; return [PC]; } +:rte is d16=0x4e73 { tmp:4 = 0; return [tmp]; } + +:rtm regdn is opbig=0x06 & op37=24 & regdn unimpl +:rtm regan is opbig=0x06 & op37=25 & regan unimpl + +:rtr is opbig=0x4e & op37=14 & op02=7 { SR = *SP; SP = SP+2; PC = *SP; SP = SP+4; unpackflags(SR); return [PC]; } + +:rts is opbig=0x4e & op37=14 & op02=5 { PC = *SP; SP = SP+4; return [PC]; } + +:sbcd Tyb,Txb is op=8 & op48=16 & Txb & Tyb { + CF = (Txb < Tyb) || ( (XF == 1) && (Txb == Tyb) ); + Txb = Txb - Tyb - XF; + Txb = bcdAdjust(Txb); + bcdflags(Txb); +} + +:s^cc eab is (op=5 & cc & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eab { eab = -cc; } + +:stop "#"^d16 is opbig=0x4e & d8base=0x72; d16 unimpl + +:sub.b eab,reg9dnb is (op=9 & reg9dnb & op68=0)... & eab + { subflags(reg9dnb, eab); reg9dnb = reg9dnb - eab; resflags(reg9dnb); } + +:sub.w eaw,reg9dnw is (op=9 & reg9dnw & op68=1)... & eaw + { subflags(reg9dnw, eaw); reg9dnw = reg9dnw - eaw; resflags(reg9dnw); } + +:sub.l eal,reg9dn is (op=9 & reg9dn & op68=2)... & eal + { subflags(reg9dn, eal); reg9dn = reg9dn - eal; resflags(reg9dn); } + +:sub.b reg9dnb,eab is (op=9 & reg9dnb & op68=4 & $(MEM_ALTER_ADDR_MODES))... & eab + { subflags(eab, reg9dnb); eab = eab - reg9dnb; resflags(eab); } + +:sub.w reg9dnw,eaw is (op=9 & reg9dnw & op68=5 & $(MEM_ALTER_ADDR_MODES))... & eaw + { subflags(eaw, reg9dnw); eaw = eaw - reg9dnw; resflags(eaw); } + +:sub.l reg9dn,eal is (op=9 & reg9dn & op68=6 & $(MEM_ALTER_ADDR_MODES))... & eal + { subflags(eal, reg9dn); eal = eal - reg9dn; resflags(eal); } + +:suba.w eaw,reg9an is (op=9 & reg9an & op68=3)... & eaw { reg9an = reg9an - sext(eaw); } +:suba.l eal,reg9an is (op=9 & reg9an & op68=7)... & eal { reg9an = reg9an - eal; } + +:subi.b "#"^d8,e2b is opbig=4 & op67=0 & $(DAT_ALTER_ADDR_MODES); d8; e2b [ savmod2=savmod1; regtsan=regtfan; ] + { subflags(e2b, d8); e2b=e2b-d8; resflags(e2b); } + +:subi.w "#"^d16,e2w is opbig=4 & op67=1 & $(DAT_ALTER_ADDR_MODES); d16; e2w [ savmod2=savmod1; regtsan=regtfan; ] + { subflags(e2w, d16); e2w=e2w-d16; resflags(e2w);} + +:subi.l "#"^d32,e2l is opbig=4 & op67=2 & $(DAT_ALTER_ADDR_MODES); d32; e2l [ savmod2=savmod1; regtsan=regtfan; ] + { subflags(e2l, d32); e2l=e2l-d32; resflags(e2l);} + +:subq.b "#"^quick,eab is (op=5 & quick & op68=4)... & eab + { subflags(eab, quick); eab = eab-quick; resflags(eab); } + +:subq.w "#"^quick,eaw is (op=5 & quick & op68=5)... & eaw + { subflags(eaw, quick); eaw = eaw-quick; resflags(eaw); } + +:subq.l "#"^quick,eal is (op=5 & quick & op68=6)... & eal + { subflags(eal, quick); eal = eal-quick; resflags(eal); } + +# special case for address register destination: condition codes not affected +:subq.w "#"^quick,regan is op=5 & quick & op68=5 & mode=1 & regan { regan = regan - quick; } +:subq.l "#"^quick,regan is op=5 & quick & op68=6 & mode=1 & regan { regan = regan - quick; } + + + +:subx.b Tyb,Txb is op=9 & op8=1 & op67=0 & op45=0 & Tyb & Txb + { tmp0:1 = zext(XF); subxflags(Txb, Tyb); local tmp =tmp0+Tyb; Txb=Txb-tmp; extendedResultFlags(Txb); } + +:subx.w Tyw,Txw is op=9 & op8=1 & op67=1 & op45=0 & Tyw & Txw + { tmp0:2 = zext(XF); subxflags(Txw, Tyw); local tmp =tmp0+Tyw; Txw=Txw-tmp; extendedResultFlags(Txw); } + +:subx.l Ty,Tx is op=9 & op8=1 & op67=2 & op45=0 & Ty & Tx + { tmp0:4 = zext(XF); subxflags(Tx, Ty); local tmp =tmp0+Ty; Tx=Tx-tmp; extendedResultFlags(Tx); } + + +:swap regdn is opbig=0x48 & op37=8 & regdn { logflags(); regdn = (regdn << 16) | (regdn>>16); resflags(regdn); } + +@ifndef COLDFIRE +:tas eab is (opbig=0x4a & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eab { logflags(); resflags(eab); eab = eab | 0x80; } +@endif # COLDFIRE + +:trap "#"^op03 is opbig=0x4e & op67=1 & op45=0 & op03 { vector:1 = op03; __m68k_trap(vector); } +:trap^cc is op=5 & cc & op37=31 & op02=4 { if (!cc) goto inst_next; SP = SP - 4; *:4 SP = PC; vector:1 = 7; __m68k_trap(vector); } +:trap^cc^".w" "#"^d16 is op=5 & cc & op37=31 & op02=2; d16 { if (!cc) goto inst_next; SP = SP - 4; *:4 SP = PC; __m68k_trapv(); } +:trap^cc^".l" "#"^d32 is op=5 & cc & op37=31 & op02=3; d32 { if (!cc) goto inst_next; SP = SP - 4; *:4 SP = PC; __m68k_trapv(); } +:trapv is opbig=0x4e & op37=14 & op02=6 { if (!VF) goto inst_next; __m68k_trapv(); } + +:tst.b eab is (opbig=0x4a & op67=0)... & eab { logflags(); resflags(eab); } +:tst.w eaw is (opbig=0x4a & op67=1)... & eaw { logflags(); resflags(eaw); } +:tst.l eal is (opbig=0x4a & op67=2)... & eal { logflags(); resflags(eal); } + +@ifdef COLDFIRE +:tas eab is (opbig=0x4a & op67=3)... & eab { logflags(); resflags(eab); eab = eab | 0x80; } +@endif # COLDFIRE + +:unlk regan is opbig=0x4e & op37=11 & regan { SP = regan; regan = *SP; SP = SP+4; } + +:unpk Tyw,Txw,"#"^d16 is op=8 & Txw & op48=24 & Tyw & rmbit=0; d16 { + Txw = (Txw & 0xF0F0) | ((((Tyw & 0x00F0) << 4) | (Tyw & 0x000F)) + d16); +} + +:unpk Tyb,Txw,"#"^d16 is op=8 & Tyb & op48=24 & Txw & rmbit=1; d16 { + local source:2 = zext(Tyb); + source = (((source & 0x00F0) << 4) | (source & 0x000F)) + d16; + Txw = (Txw & 0xF0F0) | source; +} + +# Floating Point Instructions + +# 68040 directly implements Floating Point instructions but requires Coprocessor ID be 001 +@ifdef MC68040 +@define FP_COP "copid=1" +@define FP_FCOP "fcopid=1" +@else +@define FP_COP "epsilon" +@define FP_FCOP "epsilon" +@endif + +# Condition codes +fcc: "eq" is fcode=0x01 { tmp:1 = $(Z_FP); clearflags_fp(); export tmp; } +fcc: "ne" is fcode=0x0e { tmp:1 = !($(Z_FP)); clearflags_fp(); export tmp; } # note this is wrong in the manual +fcc: "gt" is fcode=0x12 { tmp:1 = !($(NAN_FP) || $(Z_FP) || $(N_FP)); clearflags_fp(); export tmp; } +fcc: "ngt" is fcode=0x1d { tmp:1 = $(NAN_FP) || $(Z_FP) || $(N_FP); clearflags_fp(); export tmp; } +fcc: "ge" is fcode=0x13 { tmp:1 = $(Z_FP) || !($(NAN_FP) || $(N_FP)); clearflags_fp(); export tmp; } +fcc: "nge" is fcode=0x1c { tmp:1 = $(NAN_FP) || ($(N_FP) && !$(Z_FP)); clearflags_fp(); export tmp; } +fcc: "lt" is fcode=0x14 { tmp:1 = $(N_FP) && !($(NAN_FP) || $(Z_FP)); clearflags_fp(); export tmp; } +fcc: "nlt" is fcode=0x1b { tmp:1 = $(NAN_FP) || ($(Z_FP) || !$(N_FP)); clearflags_fp(); export tmp; } +fcc: "le" is fcode=0x15 { tmp:1 = $(Z_FP) || ($(N_FP) && !$(NAN_FP)); clearflags_fp(); export tmp; } +fcc: "nle" is fcode=0x1a { tmp:1 = $(NAN_FP) || !($(N_FP) || $(Z_FP)); clearflags_fp(); export tmp; } +fcc: "gl" is fcode=0x16 { tmp:1 = !($(NAN_FP) || $(Z_FP)); clearflags_fp(); export tmp; } +fcc: "ngl" is fcode=0x19 { tmp:1 = $(NAN_FP) || $(Z_FP); clearflags_fp(); export tmp; } +fcc: "gle" is fcode=0x17 { tmp:1 = $(NAN_FP); clearflags_fp(); export tmp; } +fcc: "ngle" is fcode=0x18 { tmp:1 = $(NAN_FP); clearflags_fp(); export tmp; } + +fcc: "ogt" is fcode=0x02 { tmp:1 = !($(NAN_FP) || $(Z_FP) || $(N_FP)); clearflags_fp(); export tmp; } +fcc: "ule" is fcode=0x0d { tmp:1 = $(NAN_FP) || $(Z_FP) || $(N_FP); clearflags_fp(); export tmp; } +fcc: "oge" is fcode=0x03 { tmp:1 = $(Z_FP) || !($(NAN_FP) || $(N_FP)); clearflags_fp(); export tmp; } +fcc: "ult" is fcode=0x0c { tmp:1 = $(NAN_FP) || ($(N_FP) && !$(Z_FP)); clearflags_fp(); export tmp; } +fcc: "olt" is fcode=0x04 { tmp:1 = $(N_FP) && !($(NAN_FP) || $(Z_FP)); clearflags_fp(); export tmp; } +fcc: "uge" is fcode=0x0b { tmp:1 = $(NAN_FP) || $(Z_FP) || $(N_FP); clearflags_fp(); export tmp; } +fcc: "ole" is fcode=0x05 { tmp:1 = $(Z_FP) || ($(N_FP) && !$(NAN_FP)); clearflags_fp(); export tmp; } +fcc: "ugt" is fcode=0x0a { tmp:1 = !$(NAN_FP) || !($(N_FP) || $(Z_FP)); clearflags_fp(); export tmp; } +fcc: "ogl" is fcode=0x06 { tmp:1 = !($(NAN_FP) || $(Z_FP)); clearflags_fp(); export tmp; } +fcc: "ueq" is fcode=0x09 { tmp:1 = $(NAN_FP) || $(Z_FP); clearflags_fp(); export tmp; } +fcc: "or" is fcode=0x07 { tmp:1 = $(NAN_FP); clearflags_fp(); export tmp; } +fcc: "un" is fcode=0x08 { tmp:1 = $(NAN_FP); clearflags_fp(); export tmp; } + +fcc: "f" is fcode=0x00 { export 0:1; } +fcc: "t" is fcode=0x0f { export 1:1; } +fcc: "sf" is fcode=0x10 { export 0:1; } +fcc: "st" is fcode=0x1f { export 1:1; } +fcc: "seq" is fcode=0x11 { tmp:1 = $(Z_FP); clearflags_fp(); export tmp; } +fcc: "sne" is fcode=0x1e { tmp:1 = $(Z_FP); clearflags_fp(); export tmp; } + +@define FormatByteWordLongSimple "( ffmt=0 | ffmt=1 | ffmt=4 | ffmt=6 )" + +# The following constraint should be used when using fprec +@define FPREC_BWLS "fprec & ( ffmt=0 | ffmt=1 | ffmt=4 | ffmt=6 )" # Byte,Word,Long,Simple only +@define FPREC_DXP "fprec & ( ffmt=2 | ffmt=3 | ffmt=5)" # Double,Extended,Packed only +@define FPREC_XP "fprec & ( ffmt=2 | ffmt=3)" # Extended,Packed only +@define FPREC_DX "fprec & ( ffmt=2 | ffmt=5)" # Double,Extended only +@define FPREC_X "fprec & ffmt=2" # Extended only +@define FPREC_D "fprec & ffmt=5" # Double only +@define FPREC_P "fprec & ffmt=3" # Packed only +@define FPREC_Pd "fprec & ffmt=7" # Packed-dynamic only + +fprec: "l" is ffmt=0 {} +fprec: "s" is ffmt=1 {} +fprec: "x" is ffmt=2 {} +fprec: "p" is ffmt=3 {} +fprec: "w" is ffmt=4 {} +fprec: "d" is ffmt=5 {} +fprec: "b" is ffmt=6 {} +fprec: "p" is ffmt=7 {} + + +:fabs.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x18; e2l + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = abs(tmp); } +:fabs.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x18; e2x + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = abs(tmp); } +:fabs.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x18; e2d + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = abs(tmp); } +:fabs fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x18 { fdst = abs(fsrc); } + +@ifdef MC68040 + +fabsrnd: "s" is fopmode=0x58 {} +fabsrnd: "d" is fopmode=0x5c {} + +:f^fabsrnd^"abs."^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fabsrnd & $(FPREC_BWLS) & (fopmode=0x58 | fopmode=0x5c); e2l + [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:f^fabsrnd^"abs."^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fabsrnd & $(FPREC_XP) & (fopmode=0x58 | fopmode=0x5c); e2x + [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:f^fabsrnd^"abs."^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fabsrnd & $(FPREC_D) & (fopmode=0x58 | fopmode=0x5c); e2d + [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:f^fabsrnd^"abs" fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fabsrnd & (fopmode=0x58 | fopmode=0x5c) unimpl + +@endif # MC68040 + +:facos.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x1c; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = acos(tmp);} +:facos.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x1c; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = acos(tmp);} +:facos.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x1c; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = acos(tmp);} +:facos fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1c { fdst = acos(fsrc);} + +:fadd.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x22; e2l + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = fdst f+ tmp; } +:fadd.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x22; e2x + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = fdst f+ tmp; } +:fadd.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x22; e2d + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = fdst f+ tmp; } +:fadd fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x22 { fdst = fdst f+ fsrc; } + +@ifdef MC68040 + +faddrnd: "s" is fopmode=0x62 {} +faddrnd: "d" is fopmode=0x66 {} + +:f^faddrnd^"add."^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & faddrnd & $(FPREC_BWLS) & (fopmode=0x62 | fopmode=0x66); e2l + [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:f^faddrnd^"add."^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & faddrnd & $(FPREC_XP) & (fopmode=0x62 | fopmode=0x66); e2x + [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:f^faddrnd^"add."^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & faddrnd & $(FPREC_D) & (fopmode=0x62 | fopmode=0x66); e2d + [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:f^faddrnd^"add" fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & faddrnd & (fopmode=0x62 | fopmode=0x66) unimpl + +@endif # MC68040 + +:fasin.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x0c; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = asin(tmp);} +:fasin.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x0c; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = asin(tmp);} +:fasin.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x0c; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = asin(tmp);} +:fasin fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x0c { fdst = asin(fsrc);} + +:fatan.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x0a; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = atan(tmp);} +:fatan.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x0a; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = atan(tmp);} +:fatan.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x0a; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = atan(tmp);} +:fatan fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x0a { fdst = atan(fsrc);} + +:fatanh.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x0d; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = tanh(tmp);} +:fatanh.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x0d; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = tanh(tmp);} +:fatanh.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x0d; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = tanh(tmp);} +:fatanh fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x0d { fdst = tanh(fsrc);} + +:fb^fcc^".w" addr16 is fop=15 & $(FP_FCOP) & f0808=0 & f0707=1 & fsize=0 & fcc; addr16 { if (fcc) goto addr16; } +:fb^fcc^".l" addr32 is fop=15 & $(FP_FCOP) & f0808=0 & f0707=1 & fsize=1 & fcc; addr32 { if (fcc) goto addr32; } + +:fcmp.b e2b, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & ffmt=6 & fopmode=0x38; e2b + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = int2float(e2b); local result=fdst f- tmp; resflags_fp(result); } + +:fcmp.w e2w, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & ffmt=4 & fopmode=0x38; e2w + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = int2float(e2w); local result=fdst f- tmp; resflags_fp(result); } + +:fcmp.l e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & ffmt=0 & fopmode=0x38; e2l + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = int2float(e2l); local result=fdst f- tmp; resflags_fp(result); } + +:fcmp.s e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & ffmt=1 & fopmode=0x38; e2l + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); local result=fdst f- tmp; resflags_fp(result); } + +:fcmp.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x38; e2x + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); local result=fdst f- tmp; resflags_fp(result); } + +:fcmp.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x38; e2d + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); local result=fdst f- tmp; resflags_fp(result); } + +:fcmp fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x38 + { tmp:12 = float2float(fsrc); local result=fdst f- tmp; resflags_fp(result); } + +:fcos.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x1d; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = cos(tmp);} +:fcos.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x1d; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = cos(tmp);} +:fcos.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x1d; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = cos(tmp);} +:fcos fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1d { fdst = cos(fsrc);} + +:fcosh.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x19; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = cosh(tmp);} +:fcosh.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x19; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = cosh(tmp);} +:fcosh.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x19; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = cosh(tmp);} +:fcosh fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x19 { fdst = cos(fsrc);} + +:fdb^fcc fcnt, addr16 is fop=15 & $(FP_FCOP) & f0308=9 & fcnt; f0615=0 & fcc; addr16 + { if (fcc) goto inst_next; + fcnt = fcnt - 1; + local tst = (fcnt == -1); + if (!tst) goto addr16; + } + +:fdiv.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x20; e2l + [ savmod2=savmod1; regtsan=regtfan; ] { denom:12 = float2float(e2l); fdst = fdst f/ denom;} +:fdiv.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x20; e2x + [ savmod2=savmod1; regtsan=regtfan; ] { denom:12 = float2float(e2x); fdst = fdst f/ denom;} +:fdiv.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x20; e2d + [ savmod2=savmod1; regtsan=regtfan; ] { denom:12 = float2float(e2d); fdst = fdst f/ denom;} +:fdiv fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x20 { fdst = fdst f/ fsrc;} + +@ifdef MC68040 + +fdivrnd: "s" is fopmode=0x60 {} +fdivrnd: "d" is fopmode=0x64 {} + +:f^fdivrnd^"div."^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fdivrnd & $(FPREC_BWLS) & (fopmode=0x60 | fopmode=0x64); e2l + [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:f^fdivrnd^"div."^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fdivrnd & $(FPREC_XP) & (fopmode=0x60 | fopmode=0x64); e2x + [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:f^fdivrnd^"div."^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fdivrnd & $(FPREC_D) & (fopmode=0x60 | fopmode=0x64); e2d + [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:f^fdivrnd^"div" fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fdivrnd & (fopmode=0x60 | fopmode=0x64) unimpl + +@endif # MC68040 + +:fetox.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x10; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fetox.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x10; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fetox.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x10; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fetox fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x10 unimpl + +:fetoxm1.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x08; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fetoxm1.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x08; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fetoxm1.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x08; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fetoxm1 fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x08 unimpl + +:fgetexp.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x1e; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fgetexp.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x1e; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fgetexp.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x1e; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fgetexp fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1e unimpl + +:fgetman.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x1f; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fgetman.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x1f; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fgetman.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x1f; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fgetman fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1f unimpl + +:fint.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x01; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:8 = trunc(e2l); fdst = int2float(tmp); } +:fint.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x01; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:8 = trunc(e2x); fdst = int2float(tmp); } +:fint.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x01; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:8 = trunc(e2d); fdst = int2float(tmp); } +:fint fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x01 { tmp:8 = trunc(fsrc); fdst = int2float(tmp); } + +:fintrz.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x03; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fintrz.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x03; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fintrz.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x03; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fintrz fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x03 unimpl + +:flog10.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x15; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:flog10.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x15; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:flog10.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x15; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:flog10 fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x15 unimpl + +:flog2.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x16; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:flog2.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x16; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:flog2.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x16; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:flog2 fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x16 unimpl + +:flogn.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x14; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:flogn.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x14; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:flogn.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x14; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:flogn fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x14 unimpl + +:flognp1.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x06; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:flognp1.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x06; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:flognp1.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x06; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:flognp1 fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x06 unimpl + +:fmod.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0& fdst & $(FPREC_BWLS) & fopmode=0x21; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fmod.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0& fdst & $(FPREC_XP) & fopmode=0x21; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fmod.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0& fdst & $(FPREC_D) & fopmode=0x21; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fmod fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x21 unimpl + + +:fmove.b e2b, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fopmode=0x00 & ffmt=6; e2b + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = int2float(e2b); resflags_fp(fdst); } + +:fmove.w e2w, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fopmode=0x00 & ffmt=4; e2w + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = int2float(e2w); resflags_fp(fdst); } + +:fmove.l e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fopmode=0x00 & ffmt=0; e2l + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = int2float(e2l); resflags_fp(fdst); } + +# Single float (32-bits) +:fmove.s e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fopmode=0x00 & ffmt=1; e2l + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = float2float(e2l); resflags_fp(fdst); } + +# NB- The 68k manual says floating point regs are stored internally as 80 bits, but 96 bits are moved to/from memory +# +:fmove.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x00 + & (ffmt=2 | ffmt=3); e2x + [ savmod2=savmod1; regtsan=regtfan; ] + { fdst = float2float(e2x); resflags_fp(fdst); } + +:fmove.d e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fopmode=0x00 & ffmt=5; e2d + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = float2float(e2d); resflags_fp(fdst); } + +:fmove fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x00 + { fdst = fsrc; resflags_fp(fdst); } + +@ifdef MC68040 + +fmovernd: "s" is fopmode=0x40 {} +fmovernd: "d" is fopmode=0x44 {} + +:f^fmovernd^"move."^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fmovernd & $(FPREC_BWLS) & (fopmode=0x40 | fopmode=0x44); e2l + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = int2float(e2l); } +:f^fmovernd^"move."^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fmovernd & $(FPREC_XP) & (fopmode=0x40 | fopmode=0x44); e2x + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = int2float(e2x); } +:f^fmovernd^"move."^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fmovernd & $(FPREC_D) & (fopmode=0x40 | fopmode=0x44); e2d + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = int2float(e2d); } +:f^fmovernd^"move" fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fmovernd & (fopmode=0x40 | fopmode=0x44) + { fdst = fsrc; } + +@endif # MC68040 + +#TODO: Documented decoding (w/ coprocess id in bits 10-12) conflicts with ASL instruction and differs from Instruction Format Summary +# Convert float in fdst to an int and then move to byte +:fmove.b fdst, e2b is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & ffmt=6; e2b + [ savmod2=savmod1; regtsan=regtfan; ] { e2b = trunc(fdst); } + +# Convert float in fdst to an int and then move to word 16-bits +:fmove.w fdst, e2w is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & ffmt=4; e2w + [ savmod2=savmod1; regtsan=regtfan; ] { e2w = trunc(fdst); } + +# Convert float in fdst to an int and then move to long 32-bits +:fmove.l fdst, e2l is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & ffmt=0; e2l + [ savmod2=savmod1; regtsan=regtfan; ] { e2l = trunc(fdst); } + +# destination is single float (32-bits) +:fmove.s fdst, e2l is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & ffmt=1; e2l + [ savmod2=savmod1; regtsan=regtfan; ] { e2l = float2float(fdst); resflags_fp(e2l); } + +:fmove.^fprec fdst, e2x is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & $(FPREC_X); e2x + [ savmod2=savmod1; regtsan=regtfan; ] { e2x = float2float(fdst); resflags_fp(e2x); } + +# Double float (64-bits) +:fmove.^fprec fdst, e2d is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & $(FPREC_D); e2d + [ savmod2=savmod1; regtsan=regtfan; ] { e2d = float2float(fdst); resflags_fp(e2d); } + +:fmove.p fdst, e2l {"#"fkfactor} is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfactor & $(FPREC_P); e2l + [ savmod2=savmod1; regtsan=regtfan; ] { kfact:4 = fkfactor; e2l = kfactor(fdst, kfact); } + +:fmove.p fdst, e2l {fkfacreg} is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & $(FPREC_Pd); e2l + [ savmod2=savmod1; regtsan=regtfan; ] { e2l = kfactor(fdst, fkfacreg); } + +#Special case for FMOVEM.L and must occur before it within this file +:fmove.l e2l, FPCR is op=15 & $(FP_COP) & $(DAT_ALTER_ADDR_MODES) & op68=0 & FPCR; f1415=2 & fdr=0 & f1012=4 & f0009=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { FPCR = e2l; } +:fmove.l FPCR, e2l is op=15 & $(FP_COP) & $(DAT_ALTER_ADDR_MODES) & op68=0 & FPCR; f1415=2 & fdr=1 & f1012=4 & f0009=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { e2l = FPCR; } +:fmove.l e2l, FPSR is op=15 & $(FP_COP) & $(DAT_ALTER_ADDR_MODES) & op68=0 & FPSR; f1415=2 & fdr=0 & f1012=2 & f0009=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { FPSR = e2l; } +:fmove.l FPSR, e2l is op=15 & $(FP_COP) & $(DAT_ALTER_ADDR_MODES) & op68=0 & FPSR; f1415=2 & fdr=1 & f1012=2 & f0009=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { e2l = FPSR; } +:fmove.l e2l, FPIAR is op=15 & $(FP_COP) & op68=0 & FPIAR; f1415=2 & fdr=0 & f1012=1 & f0009=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { FPIAR = e2l; } +:fmove.l FPIAR, e2l is op=15 & $(FP_COP) & op68=0 & FPIAR; f1415=2 & fdr=1 & f1012=1 & f0009=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { e2l = FPIAR; } + +# +# TODO: this table should contain all the rom constants +romconst: is fromoffset=0x00 { tmp1:8 = 0x400921FB4D12D84A:8; tmp:12 = float2float(tmp1); export tmp; } # pi=3.14... +romconst: is fromoffset=0x0f { tmp1:8 = 0x0:8; tmp:12 = int2float(tmp1); export tmp; } +romconst: is fromoffset=0x32 { tmp1:8 = 0x01:8; tmp:12 = int2float(tmp1); export tmp; } +romconst: is fromoffset=0x33 { tmp1:8 = 10:8; tmp:12 = int2float(tmp1); export tmp; } +romconst: is fromoffset=0x34 { tmp1:8 = 100:8; tmp:12 = int2float(tmp1); export tmp; } +romconst: is fromoffset=0x35 { tmp1:8 = 10000:8; tmp:12 = int2float(tmp1); export tmp; } +romconst: is fromoffset=0x36 { tmp1:8 = 100000000:8; tmp:12 = int2float(tmp1); export tmp; } +romconst: is fromoffset { tmp1:8 = 0x0:8; tmp:12 = int2float(tmp1); export tmp; } + +:fmovecr.x "#"^fromoffset, fdst is op=15 & $(FP_COP) & op08=0; f1015=0x17 & fdst & fromoffset & romconst { fdst = romconst; } + +# Memory to Floating point register, forward direction +m2fpF7: FP0 is FP0 & frlist7=1 { FP0 = *movemptr; movemptr = movemptr + 12; } +m2fpF7: is frlist7=0 { } +m2fpF6: m2fpF7" "FP1 is FP1 & frlist6=1 & m2fpF7 { FP1 = *movemptr; movemptr = movemptr + 12; } +m2fpF6: m2fpF7 is frlist6=0 & m2fpF7 { } +m2fpF5: m2fpF6" "FP2 is FP2 & frlist5=1 & m2fpF6 { FP2 = *movemptr; movemptr = movemptr + 12; } +m2fpF5: m2fpF6 is frlist5=0 & m2fpF6 { } +m2fpF4: m2fpF5" "FP3 is FP3 & frlist4=1 & m2fpF5 { FP3 = *movemptr; movemptr = movemptr + 12; } +m2fpF4: m2fpF5 is frlist4=0 & m2fpF5 { } +m2fpF3: m2fpF4" "FP4 is FP4 & frlist3=1 & m2fpF4 { FP4 = *movemptr; movemptr = movemptr + 12; } +m2fpF3: m2fpF4 is frlist3=0 & m2fpF4 { } +m2fpF2: m2fpF3" "FP5 is FP5 & frlist2=1 & m2fpF3 { FP5 = *movemptr; movemptr = movemptr + 12; } +m2fpF2: m2fpF3 is frlist2=0 & m2fpF3 { } +m2fpF1: m2fpF2" "FP6 is FP6 & frlist1=1 & m2fpF2 { FP6 = *movemptr; movemptr = movemptr + 12; } +m2fpF1: m2fpF2 is frlist1=0 & m2fpF2 { } +m2fpF0: { m2fpF1" "FP7 } is FP7 & frlist0=1 & m2fpF1 { FP7 = *movemptr; movemptr = movemptr + 12; } +m2fpF0: { m2fpF1 } is frlist0=0 & m2fpF1 { } + +# Memory to Floating point register, reverse direction +m2fpR7: FP7 is FP7 & frlist7=1 { movemptr = movemptr - 12; FP7 = *movemptr; } +m2fpR7: is frlist7=0 { } +m2fpR6: m2fpR7" "FP6 is FP6 & frlist6=1 & m2fpR7 { movemptr = movemptr - 12; FP6 = *movemptr; } +m2fpR6: m2fpR7 is frlist6=0 & m2fpR7 { } +m2fpR5: m2fpR6" "FP5 is FP5 & frlist5=1 & m2fpR6 { movemptr = movemptr - 12; FP5 = *movemptr; } +m2fpR5: m2fpR6 is frlist5=0 & m2fpR6 { } +m2fpR4: m2fpR5" "FP4 is FP4 & frlist4=1 & m2fpR5 { movemptr = movemptr - 12; FP4 = *movemptr; } +m2fpR4: m2fpR5 is frlist4=0 & m2fpR5 { } +m2fpR3: m2fpR4" "FP3 is FP3 & frlist3=1 & m2fpR4 { movemptr = movemptr - 12; FP3 = *movemptr; } +m2fpR3: m2fpR4 is frlist3=0 & m2fpR4 { } +m2fpR2: m2fpR3" "FP2 is FP2 & frlist2=1 & m2fpR3 { movemptr = movemptr - 12; FP2 = *movemptr; } +m2fpR2: m2fpR3 is frlist2=0 & m2fpR3 { } +m2fpR1: m2fpR2" "FP1 is FP1 & frlist1=1 & m2fpR2 { movemptr = movemptr - 12; FP1 = *movemptr; } +m2fpR1: m2fpR2 is frlist1=0 & m2fpR2 { } +m2fpR0: { m2fpR1" "FP0 } is FP0 & frlist0=1 & m2fpR1 { movemptr = movemptr - 12; FP0 = *movemptr; } +m2fpR0: { m2fpR1 } is frlist0=0 & m2fpR1 { } + + +# Floating point register to Memory, forward direction +fp2mF7: FP0 is FP0 & frlist7=1 { *movemptr = FP0; movemptr = movemptr + 12; } +fp2mF7: is frlist7=0 { } +fp2mF6: fp2mF7" "FP1 is FP1 & frlist6=1 & fp2mF7 { *movemptr = FP1; movemptr = movemptr + 12; } +fp2mF6: fp2mF7 is frlist6=0 & fp2mF7 { } +fp2mF5: fp2mF6" "FP2 is FP2 & frlist5=1 & fp2mF6 { *movemptr = FP2; movemptr = movemptr + 12; } +fp2mF5: fp2mF6 is frlist5=0 & fp2mF6 { } +fp2mF4: fp2mF5" "FP3 is FP3 & frlist4=1 & fp2mF5 { *movemptr = FP3; movemptr = movemptr + 12; } +fp2mF4: fp2mF5 is frlist4=0 & fp2mF5 { } +fp2mF3: fp2mF4" "FP4 is FP4 & frlist3=1 & fp2mF4 { *movemptr = FP4; movemptr = movemptr + 12; } +fp2mF3: fp2mF4 is frlist3=0 & fp2mF4 { } +fp2mF2: fp2mF3" "FP5 is FP5 & frlist2=1 & fp2mF3 { *movemptr = FP5; movemptr = movemptr + 12; } +fp2mF2: fp2mF3 is frlist2=0 & fp2mF3 { } +fp2mF1: fp2mF2" "FP6 is FP6 & frlist1=1 & fp2mF2 { *movemptr = FP6; movemptr = movemptr + 12; } +fp2mF1: fp2mF2 is frlist1=0 & fp2mF2 { } +fp2mF0: { fp2mF1" "FP7 } is FP7 & frlist0=1 & fp2mF1 { *movemptr = FP7; movemptr = movemptr + 12; } +fp2mF0: { fp2mF1 } is frlist0=0 & fp2mF1 { } + +# Floating point register to Memory, reverse direction +fp2mR7: FP7 is FP7 & frlist7=1 { movemptr = movemptr - 12; *movemptr = FP7; } +fp2mR7: is frlist7=0 { } +fp2mR6: fp2mR7" "FP6 is FP6 & frlist6=1 & fp2mR7 { movemptr = movemptr - 12; *movemptr = FP6; } +fp2mR6: fp2mR7 is frlist6=0 & fp2mR7 { } +fp2mR5: fp2mR6" "FP5 is FP5 & frlist5=1 & fp2mR6 { movemptr = movemptr - 12; *movemptr = FP5; } +fp2mR5: fp2mR6 is frlist5=0 & fp2mR6 { } +fp2mR4: fp2mR5" "FP4 is FP4 & frlist4=1 & fp2mR5 { movemptr = movemptr - 12; *movemptr = FP4; } +fp2mR4: fp2mR5 is frlist4=0 & fp2mR5 { } +fp2mR3: fp2mR4" "FP3 is FP3 & frlist3=1 & fp2mR4 { movemptr = movemptr - 12; *movemptr = FP3; } +fp2mR3: fp2mR4 is frlist3=0 & fp2mR4 { } +fp2mR2: fp2mR3" "FP2 is FP2 & frlist2=1 & fp2mR3 { movemptr = movemptr - 12; *movemptr = FP2; } +fp2mR2: fp2mR3 is frlist2=0 & fp2mR3 { } +fp2mR1: fp2mR2" "FP1 is FP1 & frlist1=1 & fp2mR2 { movemptr = movemptr - 12; *movemptr = FP1; } +fp2mR1: fp2mR2 is frlist1=0 & fp2mR2 { } +fp2mR0: { fp2mR1" "FP0 } is FP0 & frlist0=1 & fp2mR1 { movemptr = movemptr - 12; *movemptr = FP0; } +fp2mR0: { fp2mR1 } is frlist0=0 & fp2mR1 { } + + +# NB- when doing preincrement or postincrement modes, the movemptr that is set in e2x is used as the starting address for the move. +# Then at completion of the move, the reg is set to the movemptr. +# Note that movem (non-floating point) does this slightly differently) +# +# Not a predecrement or postincrement +:fmovem.x fp2mF0, e2x is op=15 & $(FP_COP) & op68=0 & (mode=2 | mode=5 | mode=6 | mode=7); + f1415=3 & fdr=1 & f0810=0 & fp2mF0 & flmode_t=0 & flmode_m=1; e2x + [ savmod2=savmod1; regtsan=regtfan; ] + { build fp2mF0; } + +# When mode=3 it's a postincrement +:fmovem.x fp2mF0, e2x is regan & op=15 & $(FP_COP) & op68=0 & mode=3; f1415=3 & fdr=1 & f0810=0 & fp2mF0 & flmode_t=0 & flmode_m=1; e2x + [ savmod2=savmod1; regtsan=regtfan; ] + { build fp2mF0; regan = movemptr; } + +# When mode=4 it's a predecrement, and also must update the address register with the new address +:fmovem.x fp2mR0, e2x is regan & op=15 & $(FP_COP) & op68=0 & mode=4; f1415=3 & fdr=1 & f0810=0 & fp2mR0 & flmode_t=0 & flmode_m=0; e2x + [ savmod2=savmod1; regtsan=regtfan; ] + { build fp2mR0; regan = movemptr; } + +# Not a predecrement or postincrement +:fmovem.x e2x, m2fpF0 is op=15 & $(FP_COP) & op68=0 & (mode=2 | mode=5 | mode=6 | mode=7); + f1415=3 & fdr=0 & f0810=0 & m2fpF0 & flmode_t=0 & flmode_m=1; e2x + [ savmod2=savmod1; regtsan=regtfan; ] + { build m2fpF0; } + +# When mode=3 it's a postincrement +:fmovem.x e2x, m2fpF0 is regan & op=15 & $(FP_COP) & op68=0 & mode=3; + f1415=3 & fdr=0 & f0810=0 & m2fpF0 & flmode_t=0 & flmode_m=1; e2x + [ savmod2=savmod1; regtsan=regtfan; ] + { build m2fpF0; regan = movemptr; } + +# When mode=4 it's a predecrement, and also must update the address register with the new address +:fmovem.x e2x, m2fpR0 is regan & op=15 & $(FP_COP) & op68=0 & mode=4; f1415=3 & fdr=0 & f0810=0 & m2fpR0 & flmode_t=0 & flmode_m=0; e2x + [ savmod2=savmod1; regtsan=regtfan; ] + { build m2fpR0; regan = movemptr; } + +# TODO: Pcode for dynamic register mask is PITA +:fmovem.x fldynreg, e2l is op=15 & $(FP_COP) & op68=0 & $(POSTINC_CTL_ADDR_MODES); f1415=3 & fdr=1 & f0810=0 & fldynreg & flmode_t=1 & flmode_m=1; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fmovem.x fldynreg, e2l is op=15 & $(FP_COP) & op68=0 & mode=4; f1415=3 & fdr=1 & f0810=0 & fldynreg & flmode_t=1 & flmode_m=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl + +:fmovem.x e2l, fldynreg is op=15 & $(FP_COP) & op68=0 & $(POSTINC_CTL_ADDR_MODES); f1415=3 & fdr=0 & f0810=0 & fldynreg & flmode_t=1 & flmode_m=1; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fmovem.x e2l, fldynreg is op=15 & $(FP_COP) & op68=0 & mode=4; f1415=3 & fdr=0 & f0810=0 & fldynreg & flmode_t=1 & flmode_m=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl + +# Memory to Floating point control register +m2fpC2: FPCR is FPCR & f12=1 { FPCR = *movemptr; movemptr = movemptr + 12; } +m2fpC2: is f12=0 { } +m2fpC1: m2fpC2" "FPSR is FPSR & f11=1 & m2fpC2 { FPSR = *movemptr; movemptr = movemptr + 12; } +m2fpC1: m2fpC2 is f11=0 & m2fpC2 { } +m2fpC0: { m2fpC1" "FPCR } is FPCR & f10=1 & m2fpC1 { FPCR = *movemptr; movemptr = movemptr + 12; } +m2fpC0: { m2fpC1 } is f10=0 & m2fpC1 { } + +# Floating point control register to Memory +fp2mC2: FPCR is FPCR & f12=1 { *movemptr = FPCR; movemptr = movemptr + 12; } +fp2mC2: is f12=0 { } +fp2mC1: fp2mC2" "FPSR is FPSR & f11=1 & fp2mC2 { *movemptr = FPSR; movemptr = movemptr + 12; } +fp2mC1: fp2mC2 is f11=0 & fp2mC2 { } +fp2mC0: { fp2mC1" "FPIAR } is FPIAR & f10=1 & fp2mC1 { *movemptr = FPIAR; movemptr = movemptr + 12; } +fp2mC0: { fp2mC1 } is f10=0 & fp2mC1 { } + +:fmovem.l fp2mC0, e2l is op=15 & $(FP_COP) & $(MEM_ALTER_ADDR_MODES) & op68=0; f1315=5 & f0009=0 & fp2mC0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { movemptr = e2l; build fp2mC0; } +:fmovem.l e2l, m2fpC0 is op=15 & $(FP_COP) & $(MEM_ALTER_ADDR_MODES) & op68=0; f1315=4 & f0009=0 & m2fpC0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { movemptr = e2l; build m2fpC0; } + +:fmul.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x23; e2l + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f* float2float(e2l); } +:fmul.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x23; e2x + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f* float2float(e2x); } +:fmul.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x23; e2d + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f* float2float(e2d); } +:fmul fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x23 + {fdst = fdst f* fsrc; } +@ifdef MC68040 + +fmulrnd: "s" is fopmode=0x63 {} +fmulrnd: "d" is fopmode=0x67 {} + +:f^fmulrnd^"mul."^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fmulrnd & (fopmode=0x63 | fopmode=0x67); e2l + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f* float2float(e2l); } +:f^fmulrnd^"mul."^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fmulrnd & (fopmode=0x63 | fopmode=0x67); e2x + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f* float2float(e2x); } +:f^fmulrnd^"mul."^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fmulrnd & (fopmode=0x63 | fopmode=0x67); e2d + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f* float2float(e2d); } +:f^fmulrnd^"mul" fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fmulrnd & (fopmode=0x63 | fopmode=0x67) + {fdst = fdst f* fsrc; } +@endif # MC68040 + +:fneg.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x1a; e2l + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = -1; fdst = int2float(tmp) f* float2float(e2l); } +:fneg.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x1a; e2x + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = -1; fdst = int2float(tmp) f* float2float(e2x); } +:fneg.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x1a; e2d + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = -1; fdst = int2float(tmp) f* float2float(e2d); } +:fneg fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1a + { tmp:12 = -1; fdst = int2float(tmp) f* fsrc; } +@ifdef MC68040 + +fnegrnd: "s" is fopmode=0x5a {} +fnegrnd: "d" is fopmode=0x5e {} + +:f^fnegrnd^"neg."^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fnegrnd & (fopmode=0x5a | fopmode=0x5e); e2l + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = -1; fdst = int2float(tmp) f* float2float(e2l); } +:f^fnegrnd^"neg."^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fnegrnd & (fopmode=0x5a | fopmode=0x5e); e2x + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = -1; fdst = int2float(tmp) f* float2float(e2x); } +:f^fnegrnd^"neg."^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fnegrnd & (fopmode=0x5a | fopmode=0x5e); e2d + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = -1; fdst = int2float(tmp) f* float2float(e2d); } +:f^fnegrnd^"neg" fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fnegrnd & (fopmode=0x5a | fopmode=0x5e) + { tmp:12 = -1; fdst = int2float(tmp) f* fsrc; } +@endif # MC68040 + +:fnop is fop=15 & $(FP_FCOP) & f0008=0x080; fword=0 { } + +:frem.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x25; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:frem.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x25; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:frem.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x25; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:frem fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x25 unimpl + +:frestore eal is (op=15 & $(FP_COP) & op68=5 & $(POSTINC_CTL_ADDR_MODES))... & eal { restoreFPUStateFrame(eal); } + +:fsave eal is (op=15 & $(FP_COP) & op68=4 & $(PREDEC_CTL_ADDR_MODES))... & eal { saveFPUStateFrame(eal); } + +:fscale.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x26; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fscale.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x26; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fscale.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x26; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fscale fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x26 unimpl + +# Need to set the destination to all 1s if the condition is true, else set to 0 +# +:fs^fcc e2b is op=15 & $(FP_COP) & op68=1 & $(DAT_ALTER_ADDR_MODES); f0615=0 & fcc; e2b + [ savmod2=savmod1; regtsan=regtfan; ] + { e2b = fcc * 0xff; } + +:fsgldiv.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x24; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fsgldiv.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x24; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fsgldiv.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x24; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fsgldiv fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x24 unimpl + +:fsglmul.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fprec & (ffmt=0 | ffmt=4 | ffmt=6) & fopmode=0x27; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl + +# Floating point single precision multiply, source is a 32-bit float, destination is an 80-bit floating point register +# TODO: set condition flags +:fsglmul.s e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & ffmt=1 & fopmode=0x27; e2l + [ savmod2=savmod1; regtsan=regtfan; ] { + tmp:12 = float2float(e2l); + fdst = tmp f* fdst; +} + +:fsglmul.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x27; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fsglmul.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x27; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:fsglmul fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x27 unimpl + +:fsin.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x0e; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = sin(tmp); } +:fsin.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x0e; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = sin(tmp); } +:fsin.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x0e; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = sin(tmp); } +:fsin fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x0e { tmp:12 = float2float(fsrc); fdst = sin(tmp); } + +:fsincos.^fprec e2l, fdcos, fdsin is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdcos & fdsin & $(FPREC_BWLS) & f0306=6; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdsin = sin(tmp); fdcos = cos(tmp); } +:fsincos.^fprec e2x, fdcos, fdsin is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdcos & fdsin & $(FPREC_XP) & f0306=6; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdsin = sin(tmp); fdcos = cos(tmp); } +:fsincos.^fprec e2d, fdcos, fdsin is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdcos & fdsin & $(FPREC_D) & f0306=6; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdsin = sin(tmp); fdcos = cos(tmp); } +:fsincos.x fsrc, fdcos, fdsin is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdcos & fdsin & f0306=6 { tmp:12 = float2float(fsrc); fdsin = sin(tmp); fdcos = cos(tmp); } + +:fsinh.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x02; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = sinh(tmp); } +:fsinh.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x02; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = sinh(tmp); } +:fsinh.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x02; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = sinh(tmp); } +:fsinh fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x02 { tmp:12 = float2float(fsrc); fdst = sinh(tmp); } + +:fsqrt.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x04; e2l + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = sqrt(tmp); } +:fsqrt.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x04; e2x + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = sqrt(tmp); } +:fsqrt.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x04; e2d + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = sqrt(tmp); } +:fsqrt.x fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x04 + { tmp:12 = float2float(fsrc); fdst = sqrt(tmp); } +@ifdef MC68040 + +fsqrtrnd: "s" is fopmode=0x41 {} +fsqrtrnd: "d" is fopmode=0x45 {} + +:f^fsqrtrnd^"sqrt."^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fsqrtrnd & (fopmode=0x41 | fopmode=0x45); e2l + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = sqrt(tmp); } +:f^fsqrtrnd^"sqrt."^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fsqrtrnd & (fopmode=0x41 | fopmode=0x45); e2x + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = sqrt(tmp); } +:f^fsqrtrnd^"sqrt."^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fsqrtrnd & (fopmode=0x41 | fopmode=0x45); e2d + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = sqrt(tmp); } +:f^fsqrtrnd^"sqrt.x" fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fsqrtrnd & (fopmode=0x41 | fopmode=0x45) + { tmp:12 = float2float(fsrc); fdst = sqrt(tmp); } +@endif # MC68040 + +:fsub.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x28; e2l + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = fdst f- tmp; } +:fsub.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x28; e2x + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = fdst f- tmp; } +:fsub.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x28; e2d + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = fdst f- tmp; } +:fsub.x fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x28 { tmp:12 = float2float(fsrc); fdst = fdst f- tmp; } + +@ifdef MC68040 + +fsubrnd: "s" is fopmode=0x68 {} +fsubrnd: "d" is fopmode=0x6c {} + +:f^fsubrnd^"sub."^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fsubrnd & $(FPREC_BWLS) & (fopmode=0x68 | fopmode=0x6c); e2l + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = fdst f- tmp; } +:f^fsubrnd^"sub."^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fsubrnd & $(FPREC_XP) & (fopmode=0x68 | fopmode=0x6c); e2x + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = fdst f- tmp; } +:f^fsubrnd^"sub."^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fsubrnd & $(FPREC_D) & (fopmode=0x68 | fopmode=0x6c); e2d + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = fdst f- tmp; } +:f^fsubrnd^"sub.x" fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fsubrnd & (fopmode=0x68 | fopmode=0x6c) { tmp:12 = float2float(fsrc); fdst = fdst f- tmp; } + +@endif # MC68040 + +:ftan.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x0f; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = tan(tmp); } +:ftan.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x0f; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = tan(tmp); } +:ftan.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x0f; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = tan(tmp); } +:ftan.x fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x0f { tmp:12 = float2float(fsrc); fdst = tan(tmp); } + +:ftanh.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x09; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = tanh(tmp); } +:ftanh.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x09; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = tanh(tmp); } +:ftanh.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x09; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = tanh(tmp); } +:ftanh.x fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x09 { tmp:12 = float2float(fsrc); fdst = tanh(tmp); } + +:ftentox.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x12; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:ftentox.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x12; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:ftentox.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x12; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:ftentox.x fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x12 unimpl + +:ftrap^fcc const16 is fop=15 & $(FP_FCOP) & f0308=0xf & fmode=2; f0615=0 & fcc; const16 { if (!fcc) goto inst_next; ftrap(const16); } +:ftrap^fcc const32 is fop=15 & $(FP_FCOP) & f0308=0xf & fmode=3; f0615=0 & fcc; const32 { if (!fcc) goto inst_next; ftrap(const32); } +:ftrap^fcc is fop=15 & $(FP_FCOP) & f0308=0xf & fmode=4; f0615=0 & fcc { if (!fcc) goto inst_next; ftrap(); } + +:ftst.^fprec e2l is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x3a; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); resflags_fp(tmp); } +:ftst.^fprec e2x is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x3a; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); resflags_fp(tmp); } +:ftst.^fprec e2d is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x3a; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); resflags_fp(tmp); } +:ftst.x fsrc is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x3a { tmp:12 = float2float(fsrc); resflags_fp(tmp); } + +:ftwotox.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x11; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:ftwotox.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x11; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:ftwotox.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x11; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:ftwotox.x fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x11 unimpl + + +@ifdef COLDFIRE + +macregy: reg03ywl is reg03ywl; IS=0 { export reg03ywl; } +macregy: reg03ywu is reg03ywu; IS=1 { export reg03ywu; } +macregx: reg9dnl is reg9dnl & op6=0; bs=0 { export reg9dnl; } +macregx: reg9dnu is reg9dnu & op6=0; bs=1 { export reg9dnu; } +macregx: reg9anl is reg9anl & op6=1; bs=0 { export reg9anl; } +macregx: reg9anu is reg9anu & op6=1; bs=1 { export reg9anu; } +macrw: reg9dn is reg9dn & op6=0 { export reg9dn; } +macrw: reg9an is reg9an & op6=1 { export reg9an; } + +macregy_e: ereg03y is ereg03y { export ereg03y; } +macregyl: reg03yl is reg03yl & IS=0 { export reg03yl; } +macregyl: reg03yu is reg03yu & IS=1 { export reg03yu; } +macregxl: reg12xwl is reg12xwl & bs=0 { export reg12xwl; } +macregxl: reg12xwu is reg12xwu & bs=1 { export reg12xwu; } + + +scalefactor: "" is sfact=0 { export 0:1; } +scalefactor: "<<1" is sfact=1 { export 1:1; } +scalefactor: ">>1" is sfact=3 { export 2:1; } + +accreg: ACC0 is ACC0 & acclsb=0 ; accmsb=0 { export ACC0; } +accreg: ACC1 is ACC1 & acclsb=1 ; accmsb=0 { export ACC1; } +accreg: ACC2 is ACC2 & acclsb=0 ; accmsb=1 { export ACC2; } +accreg: ACC3 is ACC3 & acclsb=1 ; accmsb=1 { export ACC3; } + +define pcodeop findFirstOne; + +:ff1 regdn is reg315=0x98 & regdn { + regdn = findFirstOne(regdn); + VF = 0; + CF = 0; + resflags(regdn); +} + +# MAC effective address table + # size=long +m_eal: (regan) is mode=2 & regan { export *:4 regan; } +m_eal: (regan)+ is mode=3 & regan { local tmp = regan; regan = regan + 4; export *:4 tmp; } +m_eal: -(regan) is mode=4 & regan { regan = regan - 4; export *:4 regan; } +m_eal: (d16,regan) is mode=5 & regan; d16 { local tmp = regan + d16; export *:4 tmp; } + +:maaac.l reg03y, reg9dn^scalefactor, accreg, accw is (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=0 & wl=1 & scalefactor & accw & odsize=1) ... & accreg ... +{ + local tmp = reg03y * reg9dn; + tmp = tmp << (scalefactor == 1); + tmp = tmp >> (scalefactor == 2); + accreg = accreg + tmp; + accw = accw + tmp; +} +:maaac.l reg03y, reg9an^scalefactor, accreg, accw is (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=0 & wl=1 & scalefactor & accw & odsize=1) ... & accreg ... +{ + local tmp = reg03y * reg9an; + tmp = tmp << (scalefactor == 1); + tmp = tmp >> (scalefactor == 2); + accreg = accreg + tmp; + accw = accw + tmp; +} + +:maaac.w macregy, macregx^scalefactor, accreg, accw is (op=10 & op8=0 & op45=0 ; fbit=0 & wl=0 & scalefactor & accw & odsize=1) ... & macregy ... & macregx ... & accreg ... +{ + local tmp = macregy * macregx; + tmp = tmp << (scalefactor == 1); + tmp = tmp >> (scalefactor == 2); + accreg = accreg + sext(tmp); + accw = accw + sext(tmp); +} + +:mac.l reg03y, reg9dn^scalefactor, accreg is (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=0 & wl=1 & scalefactor) ... & accreg ... +{ + local tmp = reg03y * reg9dn; + tmp = tmp << (scalefactor == 1); + tmp = tmp >> (scalefactor == 2); + accreg = accreg + tmp; +} +:mac.l reg03y, reg9an^scalefactor, accreg is (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=0 & wl=1 & scalefactor) ... & accreg ... +{ + local tmp = reg03y * reg9an; + tmp = tmp << (scalefactor == 1); + tmp = tmp >> (scalefactor == 2); + accreg = accreg + tmp; +} + +:mac.w macregy, macregx^scalefactor, accreg is (op=10 & op8=0 & op45=0 ; fbit=0 & wl=0 & scalefactor) ... & macregy ... & macregx ... & accreg ... +{ + local tmp = macregy * macregx; + tmp = tmp << (scalefactor == 1); + tmp = tmp >> (scalefactor == 2); + accreg = accreg + sext(tmp); +} + +#mac with load +:mac.w macregyl, macregxl^scalefactor, m_eal, macrw, accreg is ((op=10 & macrw & op8=0 ; macregxl & fbit=0 & macregyl & wl=0 & scalefactor) ... & accreg ...) ... & m_eal +{ + local tmp = macregyl * macregxl; + tmp = tmp << (scalefactor == 1); + tmp = tmp >> (scalefactor == 2); + accreg = accreg + sext(tmp); + macrw = m_eal; +} + +:mac.l macregy_e, reg12x^scalefactor, m_eal, macrw, accreg is ((op=10 & macrw & op6=0 & op8=0 ; reg12x & fbit=0 & wl=1 & scalefactor & macregy_e) ... & accreg ...) ... & m_eal +{ + local tmp = macregy_e * reg12x; + tmp = tmp << (scalefactor == 1); + tmp = tmp >> (scalefactor == 2); + accreg = accreg + tmp; + macrw = m_eal; +} + +:masac.l reg03y, reg9dn^scalefactor, accreg, accw is (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=0 & wl=1 & scalefactor & accw & odsize=3) ... & accreg ... +{ + local tmp = reg03y * reg9dn; + tmp = tmp << (scalefactor == 1); + tmp = tmp >> (scalefactor == 2); + accreg = accreg + tmp; + accw = accw - tmp; +} +:masac.l reg03y, reg9an^scalefactor, accreg, accw is (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=0 & wl=1 & scalefactor & accw & odsize=3) ... & accreg ... +{ + local tmp = reg03y * reg9an; + tmp = tmp << (scalefactor == 1); + tmp = tmp >> (scalefactor == 2); + accreg = accreg + tmp; + accw = accw - tmp; +} + +:masac.w macregy, macregx^scalefactor, accreg, accw is (op=10 & op8=0 & op45=0 ; fbit=0 & wl=0 & scalefactor & accw & odsize=3) ... & macregy ... & macregx ... & accreg ... +{ + local tmp = macregy * macregx; + tmp = tmp << (scalefactor == 1); + tmp = tmp >> (scalefactor == 2); + accreg = accreg + sext(tmp); + accw = accw - sext(tmp); +} + +moveaccreg: ACC0 is ACC0 & op0910=0 { export ACC0; } +moveaccreg: ACC1 is ACC1 & op0910=1 { export ACC1; } +moveaccreg: ACC2 is ACC2 & op0910=2 { export ACC2; } +moveaccreg: ACC3 is ACC3 & op0910=3 { export ACC3; } + +moveaccreg2: ACC0 is ACC0 & op01=0 { export ACC0; } +moveaccreg2: ACC1 is ACC1 & op01=1 { export ACC1; } +moveaccreg2: ACC2 is ACC2 & op01=2 { export ACC2; } +moveaccreg2: ACC3 is ACC3 & op01=3 { export ACC3; } + +:move.l moveaccreg, reg03y is op=0b1010 & op11=0 & moveaccreg & op8=1 & op47=0b1000 & reg03y { reg03y = moveaccreg; } + +:move.l ACCext01, eal is (op=0b1010 & op811=0b1011 & op67=0 & ACCext01 & (mode=0 | mode=1 | mode=7)) ... & eal { ACCext01 = eal; } +:move.l ACCext23, eal is (op=0b1010 & op811=0b1111 & op67=0 & ACCext23 & (mode=0 | mode=1 | mode=7)) ... & eal { ACCext23 = eal; } + +:move.l moveaccreg, eal is (op=0b1010 & op11=0 & moveaccreg & op8=1 & op67=0 & (mode=0 | mode=1 | mode=7)) ... & eal { moveaccreg = eal; } + +:move.l moveaccreg, moveaccreg2 is op=0b1010 & op11=0 & moveaccreg & op8=1 & op47=1 & moveaccreg2 { moveaccreg2 = moveaccreg; } + +:move.l MACSR, reg03y is op=0b1010 & op811=0b1001 & op47=0b1000 & MACSR & reg03y { reg03y = MACSR; } +:move.l ACCext01, reg03y is op=0b1010 & op811=0b1011 & op47=0b1000 & ACCext01 & reg03y { reg03y = ACCext01; } +:move.l ACCext23, reg03y is op=0b1010 & op811=0b1111 & op47=0b1000 & ACCext23 & reg03y { reg03y = ACCext23; } + +:move.l MASK, reg03y is op=10 & op811=13 & op47=8 & MASK & reg03y { reg03y = MASK; } + +:move.l MACSR, "CCR" is op=10 & op811=9 & op47=12 & MACSR { unpackflags(MACSR); } + +:move.l eal, MACSR is (op=10 & op611=36 & MACSR & (mode=0 | mode=1 | mode=7)) ... & eal { MACSR = eal; } + +:move.l eal, MASK is (op=10 & op611=52 & MASK & (mode=0 | mode=1 | mode=7)) ... & eal { MASK = eal; } + + +:msaac.l reg03y, reg9dn^scalefactor, accreg, accw is (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor & accw & odsize=1) ... & accreg ... +{ + local tmp = reg03y * reg9dn; + tmp = tmp << (scalefactor == 1); + tmp = tmp >> (scalefactor == 2); + accreg = accreg - tmp; + accw = accw + tmp; +} +:msaac.l reg03y, reg9an^scalefactor, accreg, accw is (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor & accw & odsize=1) ... & accreg ... +{ + local tmp = reg03y * reg9an; + tmp = tmp << (scalefactor == 1); + tmp = tmp >> (scalefactor == 2); + accreg = accreg - tmp; + accw = accw + tmp; +} + +:msaac.w macregy, macregx^scalefactor, accreg, accw is (op=10 & op8=0 & op45=0 ; fbit=1 & wl=0 & scalefactor & accw & odsize=1) ... & macregy ... & macregx ... & accreg ... +{ + local tmp = macregy * macregx; + tmp = tmp << (scalefactor == 1); + tmp = tmp >> (scalefactor == 2); + accreg = accreg - sext(tmp); + accw = accw + sext(tmp); +} + +:msac.l reg03y, reg9dn^scalefactor, accreg is (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor) ... & accreg ... +{ + local tmp = reg03y * reg9dn; + tmp = tmp << (scalefactor == 1); + tmp = tmp >> (scalefactor == 2); + accreg = accreg - tmp; +} +:msac.l reg03y, reg9an^scalefactor, accreg is (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor) ... & accreg ... +{ + local tmp = reg03y * reg9an; + tmp = tmp << (scalefactor == 1); + tmp = tmp >> (scalefactor == 2); + accreg = accreg - tmp; +} + +:msac.w macregy, macregx^scalefactor, accreg is (op=10 & op6=0 & op8=0 & op45=0 ; fbit=1 & wl=0 & scalefactor) ... & macregy ... & macregx ... & accreg ... +{ + local tmp = macregy * macregx; + tmp = tmp << (scalefactor == 1); + tmp = tmp >> (scalefactor == 2); + accreg = accreg - sext(tmp); +} + + +# MSAC with load + +:msac.w macregyl, macregxl^scalefactor, m_eal, macrw, accreg is ((op=10 & macrw & op8=0 ; macregxl & fbit=1 & macregyl & wl=0 & scalefactor) ... & accreg ...) ... & m_eal +{ + local tmp = macregyl * macregxl; + tmp = tmp << (scalefactor == 1); + tmp = tmp >> (scalefactor == 2); + accreg = accreg - sext(tmp); + macrw = m_eal; +} + +:msac.l macregy_e, reg12x^scalefactor, m_eal, macrw, accreg is ((op=10 & macrw & op8=0 ; reg12x & fbit=1 & wl=1 & scalefactor & macregy_e) ... & accreg ...) ... & m_eal +{ + local tmp = macregy_e * reg12x; + tmp = tmp << (scalefactor == 1); + tmp = tmp >> (scalefactor == 2); + accreg = accreg - tmp; + macrw = m_eal; +} + +:msaac.l reg03y, reg9dn^scalefactor, accreg, accw is (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor & accw & odsize=3) ... & accreg ... +{ + local tmp = reg03y * reg9dn; + tmp = tmp << (scalefactor == 1); + tmp = tmp >> (scalefactor == 2); + accreg = accreg - tmp; + accw = accw - tmp; +} +:mssac.l reg03y, reg9an^scalefactor, accreg, accw is (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor & accw & odsize=3) ... & accreg ... +{ + local tmp = reg03y * reg9an; + tmp = tmp << (scalefactor == 1); + tmp = tmp >> (scalefactor == 2); + accreg = accreg - tmp; + accw = accw - tmp; +} + +:mssac.w macregy, macregx^scalefactor, accreg, accw is (op=10 & op8=0 & op45=0 ; fbit=1 & wl=0 & scalefactor & accw & odsize=3) ... & macregy ... & macregx ... & accreg ... +{ + local tmp = macregy * macregx; + tmp = tmp << (scalefactor == 1); + tmp = tmp >> (scalefactor == 2); + accreg = accreg - sext(tmp); + accw = accw - sext(tmp); +} + +@endif + +} # end with : extGUARD=1 diff --git a/python/icicle/Ghidra/Processors/68000/data/languages/68020.slaspec b/python/icicle/Ghidra/Processors/68000/data/languages/68020.slaspec new file mode 100644 index 0000000..7148419 --- /dev/null +++ b/python/icicle/Ghidra/Processors/68000/data/languages/68020.slaspec @@ -0,0 +1 @@ +@include "68000.sinc" diff --git a/python/icicle/Ghidra/Processors/68000/data/languages/68030.slaspec b/python/icicle/Ghidra/Processors/68000/data/languages/68030.slaspec new file mode 100644 index 0000000..4c62eb2 --- /dev/null +++ b/python/icicle/Ghidra/Processors/68000/data/languages/68030.slaspec @@ -0,0 +1,2 @@ +@define MC68030 "" +@include "68000.sinc" diff --git a/python/icicle/Ghidra/Processors/68000/data/languages/68040.slaspec b/python/icicle/Ghidra/Processors/68000/data/languages/68040.slaspec new file mode 100644 index 0000000..94e2ecf --- /dev/null +++ b/python/icicle/Ghidra/Processors/68000/data/languages/68040.slaspec @@ -0,0 +1,2 @@ +@define MC68040 "" +@include "68000.sinc" diff --git a/python/icicle/Ghidra/Processors/68000/data/languages/coldfire.slaspec b/python/icicle/Ghidra/Processors/68000/data/languages/coldfire.slaspec new file mode 100644 index 0000000..d99ace5 --- /dev/null +++ b/python/icicle/Ghidra/Processors/68000/data/languages/coldfire.slaspec @@ -0,0 +1,6 @@ +# Motorola's Coldfire processor + +@define COLDFIRE "" +@define MC68040 "" + +@include "68000.sinc" diff --git a/python/icicle/Ghidra/Processors/8048/data/languages/8048.cspec b/python/icicle/Ghidra/Processors/8048/data/languages/8048.cspec new file mode 100644 index 0000000..35e8c0a --- /dev/null +++ b/python/icicle/Ghidra/Processors/8048/data/languages/8048.cspec @@ -0,0 +1,31 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/8048/data/languages/8048.ldefs b/python/icicle/Ghidra/Processors/8048/data/languages/8048.ldefs new file mode 100644 index 0000000..6533853 --- /dev/null +++ b/python/icicle/Ghidra/Processors/8048/data/languages/8048.ldefs @@ -0,0 +1,18 @@ + + + + + + 8048 Microcontroller Family + + + + diff --git a/python/icicle/Ghidra/Processors/8048/data/languages/8048.pspec b/python/icicle/Ghidra/Processors/8048/data/languages/8048.pspec new file mode 100644 index 0000000..edaef33 --- /dev/null +++ b/python/icicle/Ghidra/Processors/8048/data/languages/8048.pspec @@ -0,0 +1,49 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/8048/data/languages/8048.slaspec b/python/icicle/Ghidra/Processors/8048/data/languages/8048.slaspec new file mode 100644 index 0000000..464bb2c --- /dev/null +++ b/python/icicle/Ghidra/Processors/8048/data/languages/8048.slaspec @@ -0,0 +1,539 @@ +# sleigh specification file for Intel 8048 + + +# Do not take BS into account when decompiling +@define SINGLE_REGISTER_BANK "" + +# Treat R0-R7 as not memory mapped (implies SINGLE_REGISTER_BANK) +@define INTERNAL_REGISTERS "" + + +@ifdef INTERNAL_REGISTERS +@define SINGLE_REGISTER_BANK "" +@endif + + +define endian=little; +define alignment=1; + +define space CODE type=ram_space size=2 default; +define space INTMEM type=ram_space size=1; +define space EXTMEM type=ram_space size=1; +define space PORT type=ram_space size=1; + +define space register type=register_space size=1; + +define register offset=0x00 size=1 [ A SP ]; +@ifdef INTERNAL_REGISTERS +define register offset=0x10 size=1 [ R0 R1 R2 R3 R4 R5 R6 R7 ]; +@endif +define register offset=0x20 size=2 [ PC ]; +define register offset=0x30 size=1 [ C AC F0 F1 BS DFB ]; # single bit + + +################################################################ +# Tokens +################################################################ + +define token opbyte (8) + opfull = (0,7) + oplo = (0,3) + ophi = (4,7) + rn = (0,2) dec + rnfill = (3,3) + ri = (0,0) dec + rifill = (1,3) + opaddr = (5,7) + addrfill = (4,4) + pp = (0,1) dec + xpp = (0,1) dec + ppfill = (2,3) + abit = (5,7) dec + abfill = (4,4) + dfb = (4,4) + bs = (4,4) +; + +define token aopword (16) + aoplo = (0,3) + aaddrfill = (4,4) + aopaddr = (5,7) + adata = (8,15) +; + +define token ImmedByte (8) data=(0,7); +define token AddrOne (8) addr8=(0,7); + +@ifdef INTERNAL_REGISTERS +attach variables rn [ R0 R1 R2 R3 R4 R5 R6 R7 ]; +attach variables ri [ R0 R1 ]; +@else +attach names rn [ R0 R1 R2 R3 R4 R5 R6 R7 ]; +attach names ri [ R0 R1 ]; +@endif +attach names dfb [ MB0 MB1 ]; +attach names bs [ RB0 RB1 ]; +attach names pp [ BUS P1 P2 _ ]; +attach names xpp [ P4 P5 P6 P7 ]; + + +################################################################ +# Pseudo Instructions +################################################################ + +define pcodeop nop; +define pcodeop enableExtInt; +define pcodeop enableTCntInt; +define pcodeop enableClockOutput; +define pcodeop disableExtInt; +define pcodeop disableTCntInt; +define pcodeop startTimer; +define pcodeop startEventCounter; +define pcodeop stopTimerAndEventCounter; +define pcodeop setTmr; +define pcodeop getTmr; +define pcodeop getT0; +define pcodeop getT1; +define pcodeop getTF; +define pcodeop getExtInt; +define pcodeop readPort; +define pcodeop writePort; +define pcodeop setBank; + + +################################################################ +# Macros +################################################################ + +macro getPSW(reg) { + local tmp:1 = 0; + tmp[7,1] = C; + tmp[6,1] = AC; + tmp[5,1] = F0; + tmp[4,1] = BS; + tmp[3,1] = 1; + tmp[0,3] = (SP>>1)&7; + reg = tmp; +} + +macro setPSW(reg) { + local tmp:1 = reg; + C = tmp[7,1]; + AC = tmp[6,1]; + F0 = tmp[5,1]; + BS = tmp[4,1]; + SP = 2*tmp[0,3] + 8; +} + +macro savePSWtoPC(pc) { + pc[15,1] = C; + pc[14,1] = AC; + pc[13,1] = F0; + pc[12,1] = BS; +} + +macro restorePSWfromPC(pc) { + C = pc[15,1]; + AC = pc[14,1]; + F0 = pc[13,1]; + BS = pc[12,1]; +} + +macro push(v) { + *[INTMEM]:2 SP = v; + SP = SP + 2; +} + +macro pop(v) { + SP = SP - 2; + v = *[INTMEM]:2 SP; +} + +macro popPC(pc) { + pop(pc); + pc = pc & 0xfff; +} + +macro popPCandPSW(pc) { + pop(pc); + restorePSWfromPC(pc); + pc = pc & 0xfff; +} + +macro funcall(target) { + ret:2 = inst_next; + savePSWtoPC(ret); + push(ret); + call target; +} + +macro add(dest, op1, op2, cy_in) { + local result:1 = op1 + op2 + cy_in; + local half_result:1 = (op1 & 0xf) + (op2 & 0xf) + cy_in; + C = carry(op1, op2) || carry(op1+op2, cy_in); + AC = (half_result > 0xf); + dest = result; +} + +macro da(reg) { + local tmp:1 = reg; + local low:1 = 6*(AC || (tmp&0xf) > 9); + local cy1:1 = C || carry(tmp, low); + tmp = tmp + low; + local high:1 = 0x60*(cy1 || tmp > 0x99); + C = C || carry(tmp, high); + tmp = tmp + high; + reg = tmp; +} + +macro rotc(cy, acc) { + local tmp:1 = cy; + A = acc; + C = tmp; +} + +macro xch(node1, node2) { + local tmp:1 = node1; + node1 = node2; + node2 = tmp; +} + +@ifdef SINGLE_REGISTER_BANK +macro regbank(r) { r = r; } +macro setbank(bs) { + BS = bs; + local tmp:1 = bs; + setBank(tmp); +} +@else +macro regbank(r) { + r = r + BS*0x18; +} +macro setbank(bs) { + BS = bs; +} +@endif + + +################################################################ + +Psw: "PSW" is epsilon { } +ExtInt: "I" is epsilon { } +TCntInt: "TCNTI" is epsilon { } +Clk: "CLK" is epsilon { } +Tmr: "T" is epsilon { } +Cnt: "CNT" is epsilon { } +TmrCnt: "TCNT" is epsilon { } + +@ifdef INTERNAL_REGISTERS +Rn: rn is rn & rnfill=1 { + export rn; +} +Rind: @ri is ri & rifill=0 { + export ri; +} +@else +Rn: rn is rn & rnfill=1 { + local ptr:1 = rn; regbank(ptr); export *[INTMEM]:1 ptr; +} +Rind: @ri is ri & rifill=0 { + local ptr:1 = ri; regbank(ptr); export *[INTMEM]:1 ptr; +} +@endif +Ri: Rind is Rind { + export *[INTMEM]:1 Rind; +} +RiX: Rind is Rind { + export *[EXTMEM]:1 Rind; +} +PData: @A is A { + local addr:2 = inst_next; addr[0,7] = A; export *[CODE]:1 addr; +} +P3Data: @A is A { + local addr:2 = 0x300; addr[0,7] = A; export *[CODE]:1 addr; +} +AddrInd: PData is PData { + local addr:2 = inst_next; addr[0,7] = PData; export *[CODE]:1 addr; +} +Ab: abit is abit { + local bit:1 = (A>>abit)&1; export bit; +} +Data: "#"^data is data { + export *[const]:1 data; +} +Imm: Data is oplo=3; Data { + export Data; +} +Addr8: addr is addr8 [ addr = (inst_next $and 0xf00)+addr8; ] { + export *[CODE]:1 addr; +} +Addr12: addr is aopaddr & adata [ addr = (DFB*2048)+(aopaddr*256)+adata; ] { + export *[CODE]:1 addr; +} +Bus: "BUS" is epsilon { + local tmp:1 = 0; export *[PORT]:1 tmp; +} +Pp: pp is pp & ppfill=2 { + export *[PORT]:1 pp; +} +Xpp: xpp is xpp & ppfill=3 { + local tmp:1 = xpp+4; export *[PORT]:1 tmp; +} + +Cc: "C" is ophi=15 { + export C; +} +Cc: "F0" is ophi=11 { + export F0; +} +Cc: "F1" is ophi=7 { + export F1; +} +Cc: "NC" is ophi=14 { + tmp:1 = !C; export tmp; +} +Cc: "NI" is ophi=8 { + tmp:1 = getExtInt(); tmp = !tmp; export tmp; +} +Cc: "NT0" is ophi=2 { + tmp:1 = getT0(); tmp = !tmp; export tmp; +} +Cc: "NT1" is ophi=4 { + tmp:1 = getT1(); tmp = !tmp; export tmp; +} +Cc: "NZ" is ophi=9 { + tmp:1 = A!=0; export tmp; +} +Cc: "TF" is ophi=1 { + tmp:1 = getTF(); export tmp; +} +Cc: "T0" is ophi=3 { + tmp:1 = getT0(); export tmp; +} +Cc: "T1" is ophi=5 { + tmp:1 = getT1(); export tmp; +} +Cc: "Z" is ophi=12 { + tmp:1 = A==0; export tmp; +} + + +# Conventience tables for opcodes taking both Rn and Ri (and Imm) +Rni: Rn is Rn { + export Rn; +} +Rni: Ri is Ri { + export Ri; +} +RniI: Rni is Rni { + export Rni; +} +RniI: Imm is Imm { + export Imm; +} + + +:ADD A,Rni is ophi=6 & (rnfill=1 | rifill=0) & A & Rni { + add(A,A,Rni,0); +} +:ADD A,Imm is (ophi=0 & A)... & Imm { + add(A,A,Imm,0); +} +:ADDC A,Rni is ophi=7 & A & (rnfill=1 | rifill=0) & Rni { + add(A,A,Rni,C); +} +:ADDC A,Imm is (ophi=1 & A)... & Imm { + add(A,A,Imm,C); +} +:ANL A,RniI is (ophi=5 & (rnfill=1 | rifill=0 | oplo=3) & A)... & RniI { + A = A & RniI; +} +:ANL Pp,Data is ophi=9 & ppfill=2 & Pp; Data { + Pp = Pp & Data; +} +:ANLD Xpp,A is ophi=9 & ppfill=3 & Xpp & A { + Xpp = Xpp & (A & 0xf); +} +:CALL Addr12 is aopaddr & aaddrfill=1 & aoplo=4 & Addr12 { + funcall(Addr12); +} +:CLR A is ophi=2 & oplo=7 & A { + A = 0; +} +:CLR C is ophi=9 & oplo=7 & C { + C = 0; +} +:CLR F0 is ophi=8 & oplo=5 & F0 { + F0 = 0; +} +:CLR F1 is ophi=10 & oplo=5 & F1 { + F1 = 0; +} +:CPL A is ophi=3 & oplo=7 & A { + A = ~A; +} +:CPL C is ophi=10 & oplo=7 & C { + C = !C; +} +:CPL F0 is ophi=9 & oplo=5 & F0 { + F0 = !F0; +} +:CPL F1 is ophi=11 & oplo=5 & F1 { + F1 = !F1; +} +:DA A is ophi=5 & oplo=7 & A { + da(A); +} +:DEC A is ophi=0 & oplo=7 & A { + A = A - 1; +} +:DEC Rn is ophi=12 & Rn { + Rn = Rn - 1; +} +:DIS ExtInt is ophi=1 & oplo=5 & ExtInt { + disableExtInt(); +} +:DIS TCntInt is ophi=3 & oplo=5 & TCntInt { + disableTCntInt(); +} +:DJNZ Rn,Addr8 is ophi=14 & Rn; Addr8 { + Rn = Rn - 1; if(Rn != 0) goto Addr8; +} +:EN ExtInt is ophi=0 & oplo=5 & ExtInt { + enableExtInt(); +} +:EN TCntInt is ophi=2 & oplo=5 & TCntInt { + enableTCntInt(); +} +:ENT0 Clk is ophi=7 & oplo=5 & Clk { + enableClockOutput(); +} +:IN A,Pp is ophi=0 & pp!=0 & A & Pp { + A = Pp; +} +:INC A is ophi=1 & oplo=7 & A { + A = A + 1; +} +:INC Rni is ophi=1 & (rnfill=1 | rifill=0) & Rni { + Rni = Rni + 1; +} +:INS A,Bus is ophi=0 & oplo=8 & A & Bus { + A = Bus; +} +:JB^Ab Addr8 is oplo=2 & opaddr & abfill=1 & Ab; Addr8 { + if(Ab) goto Addr8; +} +:J^Cc Addr8 is ophi & oplo=6 & Cc; Addr8 { + if(Cc) goto Addr8; +} +:JMP Addr12 is aopaddr & aaddrfill=0 & aoplo=4 & Addr12 { + goto Addr12; +} +:JMPP AddrInd is ophi=11 & oplo=3 & AddrInd { + goto AddrInd; +} +:MOV A,Imm is (ophi=2 & A)... & Imm { + A = Imm; +} +:MOV A,Psw is ophi=12 & oplo=7 & A & Psw { + getPSW(A); +} +:MOV A,Rni is ophi=15 & A & (rnfill=1 | rifill=0) & Rni { + A = Rni; +} +:MOV A,Tmr is ophi=4 & oplo=2 & A & Tmr { + A = getTmr(); +} +:MOV Psw,A is ophi=13 & oplo=7 & Psw & A { + setPSW(A); +} +:MOV Rni,A is ophi=10 & (rnfill=1 | rifill=0) & Rni & A { + Rni = A; +} +:MOV Rni,Data is ophi=11 & (rnfill=1 | rifill=0) & Rni; Data { + Rni = Data; +} +:MOV Tmr,A is ophi=6 & oplo=2 & Tmr & A { + setTmr(A); +} +:MOVD A,Xpp is ophi=0 & Xpp & A { + A = (Xpp & 0xf); +} +:MOVD Xpp,A is ophi=3 & Xpp & A { + Xpp = (A & 0xf); +} +:MOVP A,PData is ophi=10 & oplo=3 & A & PData { + A = PData; +} +:MOVP3 A,P3Data is ophi=14 & oplo=3 & A & P3Data { + A = P3Data; +} +:MOVX A,RiX is ophi=8 & A & RiX { + A = RiX; +} +:MOVX RiX,A is ophi=9 & RiX & A { + RiX = A; +} +:NOP is ophi=0 & oplo=0 { + nop(); +} +:ORL A,RniI is (ophi=4 & (rnfill=1 | rifill=0 | oplo=3) & A)... & RniI { + A = A | RniI; +} +:ORL Pp,Data is ophi=8 & Pp; Data { + Pp = Pp | Data; +} +:ORLD Xpp,A is ophi=8 & Xpp & A { + Xpp = Xpp | (A & 0xf); +} +:OUTL Bus,A is ophi=0 & oplo=2 & Bus & A { + Bus = A; +} +:OUTL Pp,A is ophi=3 & pp!=0 & Pp & A { + Pp = A; +} +:RET is ophi=8 & oplo=3 { + pc:2 = 0; popPC(pc); return[pc]; +} +:RETR is ophi=9 & oplo=3 { + pc:2 = 0; popPCandPSW(pc); return[pc]; +} +:RL A is ophi=14 & oplo=7 & A { + A = (A<<1) | (A>>7); +} +:RLC A is ophi=15 & oplo=7 & A { + rotc((A&0x80)>>7, (A<<1)|C); +} +:RR A is ophi=7 & oplo=7 & A { + A = (A>>1) | (A<<7); +} +:RRC A is ophi=6 & oplo=7 & A { + rotc(A&1, (A>>1)|(C<<7)); +} +:SEL dfb is (ophi=14 | ophi=15) & oplo=5 & dfb { + DFB = dfb; +} +:SEL bs is (ophi=12 | ophi=13) & oplo=5 & bs { + setbank(bs); +} +:STOP TmrCnt is ophi=6 & oplo=5 & TmrCnt { + stopTimerAndEventCounter(); +} +:STRT Cnt is ophi=4 & oplo=5 & Cnt { + startEventCounter(); +} +:STRT Tmr is ophi=5 & oplo=5 & Tmr { + startTimer(); +} +:SWAP A is ophi=4 & oplo=7 & A { + A = (A<<4)|(A>>4); +} +:XCH A,Rni is ophi=2 & (rnfill=1 | rifill=0) & A & Rni { + xch(A, Rni); +} +:XCHD A,Ri is ophi=3 & A & Ri { + xch(A[0,4], Ri[0,4]); +} +:XRL A,RniI is (ophi=13 & (rnfill=1 | rifill=0 | oplo=3) & A)... & RniI { + A = A ^ RniI; +} diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/80251.cspec b/python/icicle/Ghidra/Processors/8051/data/languages/80251.cspec new file mode 100644 index 0000000..2ccf8e6 --- /dev/null +++ b/python/icicle/Ghidra/Processors/8051/data/languages/80251.cspec @@ -0,0 +1,54 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/80251.pspec b/python/icicle/Ghidra/Processors/8051/data/languages/80251.pspec new file mode 100644 index 0000000..a6b68b5 --- /dev/null +++ b/python/icicle/Ghidra/Processors/8051/data/languages/80251.pspec @@ -0,0 +1,1070 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/80251.sinc b/python/icicle/Ghidra/Processors/8051/data/languages/80251.sinc new file mode 100644 index 0000000..64f7ee5 --- /dev/null +++ b/python/icicle/Ghidra/Processors/8051/data/languages/80251.sinc @@ -0,0 +1,662 @@ +# 80251 Instructions + +# NOTE! 80251 implementation is preliminary and has not tested !! + +define token srcDestByte (8) + rm47 = (4,7) + rm47_d1 = (4,7) + rm47_d2 = (4,7) + rm03 = (0,3) + wrj47 = (4,7) + wrj47_d1 = (4,7) + wrj47_d2 = (4,7) + wrj03 = (0,3) + drk47 = (4,7) + drk03 = (0,3) + # constraint bits + d7 = (7,7) + d57 = (5,7) + d47 = (4,7) + s3 = (3,3) + s23 = (2,3) + s13 = (1,3) + s03 = (0,3) + s1 = (1,1) + s0 = (0,0) + short01 = (0,1) + bit02 = (0,2) +; + +define token srcDestByte2 (8) + rm47_ = (4,7) + rm03_ = (0,3) + wrj47_ = (4,7) + wrj03_ = (0,3) + drk47_ = (4,7) + drk03_ = (0,3) + # constraint bits + d7_ = (7,7) + d57_ = (5,7) + s3_ = (3,3) + s13_ = (1,3) + s03_ = (0,3) +; + +define token AddrThree (24) + addr24 = (0,23) +; + +define token ImmedThree (24) + data24 = (0,23) +; + +attach values short01 [ 1 2 4 _ ]; + +attach variables [ rm47 rm03 rm47_ rm03_ ] [ + R0 R1 R2 R3 R4 R5 R6 R7 + R8 R9 B ACC R12 R13 R14 R15 +]; + +attach variables [ rm47_d1 ] [ + R0 R0 R2 R2 R4 R3 R6 R6 + R8 R8 B B R12 R12 R14 R14 +]; + +attach variables [ rm47_d2 ] [ + R1 R1 R3 R3 R5 R5 R7 R7 + R9 R9 ACC ACC R13 R13 R15 R15 +]; + +attach variables [ wrj47 wrj03 wrj47_ wrj03_ ] [ + WR0 WR2 WR4 WR6 WR8 AB WR12 WR14 + WR16 WR18 WR20 WR22 WR24 WR26 WR28 WR30 +]; + +attach variables [ wrj47_d1 ] [ + WR0 WR0 WR4 WR4 WR8 WR8 WR12 WR12 + WR16 WR16 WR20 WR20 WR24 WR24 WR28 WR28 +]; + +attach variables [ wrj47_d2 ] [ + WR2 WR2 WR6 WR6 AB AB WR14 WR14 + WR18 WR18 WR22 WR22 WR26 WR26 WR30 WR30 +]; + +# NOTE: must use constraints DRK, DRKD and DRKS +attach variables [ drk47 drk03 drk47_ drk03_ ] [ + DR0 DR4 DR8 DR12 DR16 DR20 DR24 DR28 + DPX SPX _ _ _ _ _ _ +]; + +@define DRK47 "drk47 & (d7=0 | d57=4)" # constraint for using drk47 +@define DRK03 "drk03 & (s3=0 | s13=4)" # constraint for using drk03 +@define DRK47_ "drk47_ & (d7_=0 | d57_=4)" # constraint for using drk47_ + +AtWRjb: "@"^wrj47 is wrj47 { ptr:3 = zext(wrj47); export *:1 ptr; } +AtWRjw: "@"^wrj47 is wrj47 { ptr:3 = zext(wrj47); export *:2 ptr; } + +# NOTE: be sure to use the ATDRK constraint on the constructor +AtDRkb: "@"^drk47 is drk47 { ptr:3 = drk47:3; export *:1 ptr; } +AtDRkw: "@"^drk47 is drk47 { ptr:3 = drk47:3; export *:2 ptr; } +AtDRkt: "@"^drk47 is drk47 { ptr:3 = drk47:3; export *:3 ptr; } + +@define ATDRK "(d7=0 | d57=4)" + +AtWRj47Dis16b: "@"^wrj47^"+"^data16 is wrj47; data16 { ptr:3 = zext(wrj47) + data16; export *:1 ptr; } +AtWRj47Dis16w: "@"^wrj47^"+"^data16 is wrj47; data16 { ptr:3 = zext(wrj47) + data16; export *:2 ptr; } + +AtWRj03Dis16b: "@"^wrj03^"+"^data16 is wrj03; data16 { ptr:3 = zext(wrj03) + data16; export *:1 ptr; } +AtWRj03Dis16w: "@"^wrj03^"+"^data16 is wrj03; data16 { ptr:3 = zext(wrj03) + data16; export *:2 ptr; } + +AtDRk47Dis24b: "@"^drk47^"+"^data24 is drk47; data24 { ptr:3 = drk47:3 + data24; export *:1 ptr; } +AtDRk47Dis24w: "@"^drk47^"+"^data24 is drk47; data24 { ptr:3 = drk47:3 + data24; export *:2 ptr; } + +AtDRk03Dis24b: "@"^drk03^"+"^data24 is drk03; data24 { ptr:3 = drk03:3 + data24; export *:1 ptr; } +AtDRk03Dis24w: "@"^drk03^"+"^data24 is drk03; data24 { ptr:3 = drk03:3 + data24; export *:2 ptr; } + +# TODO: Verify dir8 access restriction for word/dword accesses !! +Direct8w: mainreg is bank=0 & mainreg { export *:2 mainreg; } +Direct8w: Direct is bank=1 & Direct { tmp:2 = zext(Direct); export tmp; } + +# TODO: The dir16 mode does not map into the SFR's - is this correct ?? +Direct16b: addr16 is addr16 { export *:1 addr16; } +Direct16w: addr16 is addr16 { export *:2 addr16; } +Direct16d: addr16 is addr16 { export *:4 addr16; } + +Data16x0: "#"data16 is data16 { export *[const]:4 data16; } +Data16x1: "#"val is data16 [ val = 0xffff0000 + data16; ] { export *[const]:4 val; } + +Addr24: addr24 is addr24 { export *:1 addr24; } + +# NOTE: use SHORT constraint +Short: "#"^short01 is short01 { export *[const]:1 short01; } +@define SHORT "Short & (s0=0 | s1=0)" + +#TODO: Figure out new bit addressing for 251 ... + +xBitByteAddr: is bitaddr8 { export *:1 bitaddr8; } + +xBitAddr: bitaddr^"."^bit02 is bit02; bitaddr8 [ bitaddr = (bitaddr8 << 3) + bit02; ] { export *[BITS]:1 bitaddr; } +xBitAddr2: "/"^bitaddr^"."^bit02 is bit02; bitaddr8 [ bitaddr = (bitaddr8 << 3) + bit02; ] { export *[BITS]:1 bitaddr; } + + +macro push24(val) { + al:1 = val:1; + ah:1 = val(1); + ax:1 = val(2); + + ptr:3 = SPX:3; + + ptr = ptr + 1; + *[RAM]:1 ptr = al; + ptr = ptr + 1; + *[RAM]:1 ptr = ah; + ptr = ptr + 1; + *[RAM]:1 ptr = ax; + + SPX = SPX + 3; +} + +macro pop24(val) { + + SPX = SPX - 2; + + ptr:3 = SPX:3; + al:1 = *[RAM]:1 ptr; + ah:1 = *[RAM]:1 (ptr+1); + ax:1 = *[RAM]:1 (ptr+2); + + SPX = SPX - 1; + + val = (zext(ax) << 16) | (zext(ah) << 8) | zext(al); +} + + +# s s s s Binary representation of m or md +# S S S S Binary representation of ms +# t t t t Binary representation of j or jd +# T T T T Binary representation of js +# u u u u Binary representation of k or kd +# U U U U Binary representation of ks + +# NOTE: >>>> Find MCS251 instructions by searching for "Binary Mode = [A5][Encoding]" in PDF manual <<<< +# NOTE: All instructions should include the $(GROUP3) pattern prefix + +# ADD Rmd,Rms +:ADD rm47,rm03 is $(GROUP3) & ophi=2 & oplo=12; rm47 & rm03 { addflags(rm47,rm03); rm47 = rm47 + rm03; resultflags(rm47); } + +# ADD WRjd,WRjs +:ADD wrj47,wrj03 is $(GROUP3) & ophi=2 & oplo=13; wrj47 & wrj03 { addflags(wrj47,wrj03); wrj47 = wrj47 + wrj03; resultflags(wrj47); } + +# ADD DRkd,DRks +:ADD drk47,drk03 is $(GROUP3) & ophi=2 & oplo=15; $(DRK47) & $(DRK03) { addflags(drk47,drk03); drk47 = drk47 + drk03; resultflags(drk47); } + +# ADD Rm,#data +:ADD rm47,Data is $(GROUP3) & ophi=2 & oplo=14; rm47 & s03=0; Data { addflags(rm47,Data); rm47 = rm47 + Data; resultflags(rm47); } + +# ADD WRj,#data16 +:ADD wrj47,Data16 is $(GROUP3) & ophi=2 & oplo=14; wrj47 & s03=4; Data16 { addflags(wrj47,Data16); wrj47 = wrj47 + Data16; resultflags(wrj47); } + +# ADD DRk,#0data16 +:ADD drk47,Data16x0 is $(GROUP3) & ophi=2 & oplo=14; $(DRK47) & s03=8; Data16x0 { addflags(drk47,Data16x0); drk47 = drk47 + Data16x0; resultflags(drk47); } + +# ADD Rm,dir8 +:ADD rm47,Direct is $(GROUP3) & ophi=2 & oplo=14; rm47 & s03=1; Direct { addflags(rm47,Direct); rm47 = rm47 + Direct; resultflags(rm47); } + +# ADD WRj,dir8 +:ADD wrj47,Direct8w is $(GROUP3) & ophi=2 & oplo=14; wrj47 & s03=5; Direct8w { addflags(wrj47,Direct8w); wrj47 = wrj47 + Direct8w; resultflags(wrj47); } + +# ADD Rm,dir16 +:ADD rm47,Direct16b is $(GROUP3) & ophi=2 & oplo=14; rm47 & s03=3; Direct16b { addflags(rm47,Direct16b); rm47 = rm47 + Direct16b; resultflags(rm47); } + +# ADD WRj,dir16 +:ADD wrj47,Direct16w is $(GROUP3) & ophi=2 & oplo=14; wrj47 & s03=7; Direct16w { addflags(wrj47,Direct16w); wrj47 = wrj47 + Direct16w; resultflags(wrj47); } + +# ADD Rm,@WRj +:ADD rm47_,AtWRjb is $(GROUP3) & ophi=2 & oplo=14; AtWRjb & s03=9; rm47_ & s03_=0 { addflags(rm47_,AtWRjb); rm47_ = rm47_ + AtWRjb; resultflags(rm47_); } + +# ADD Rm,@DRk +:ADD rm47_,AtDRkb is $(GROUP3) & ophi=2 & oplo=14; $(ATDRK) & AtDRkb & s03=11; rm47_ & s03_=0 { addflags(rm47_,AtDRkb); rm47_ = rm47_ + AtDRkb; resultflags(rm47_); } + +# ANL Rmd,Rms +:ANL rm47,rm03 is $(GROUP3) & ophi=5 & oplo=12; rm47 & rm03 { rm47 = rm47 & rm03; resultflags(rm47); } + +# ANL WRjd,WRjs +:ANL wrj47,wrj03 is $(GROUP3) & ophi=5 & oplo=13; wrj47 & wrj03 { wrj47 = wrj47 & wrj03; resultflags(wrj47); } + +# ANL Rm,#data +:ADD rm47,Data is $(GROUP3) & ophi=5 & oplo=14; rm47 & s03=0; Data { rm47 = rm47 & Data; resultflags(rm47); } + +# ANL WRj,#data16 +:ANL wrj47,Data16 is $(GROUP3) & ophi=5 & oplo=14; wrj47 & s03=4; Data16 { wrj47 = wrj47 & Data16; resultflags(wrj47); } + +# ANL Rm,dir8 +:ANL rm47,Direct is $(GROUP3) & ophi=5 & oplo=14; rm47 & s03=1; Direct { rm47 = rm47 & Direct; resultflags(rm47); } + +# ANL WRj,dir8 +:ANL wrj47,Direct8w is $(GROUP3) & ophi=5 & oplo=14; wrj47 & s03=5; Direct8w { wrj47 = wrj47 & Direct8w; resultflags(wrj47); } + +# ANL Rm,dir16 +:ANL rm47,Direct16b is $(GROUP3) & ophi=5 & oplo=14; rm47 & s03=3; Direct16b { rm47 = rm47 & Direct16b; resultflags(rm47); } + +# ANL WRj,dir16 +:ANL wrj47,Direct16w is $(GROUP3) & ophi=5 & oplo=14; wrj47 & s03=7; Direct16w { wrj47 = wrj47 & Direct16w; resultflags(wrj47); } + +# ANL Rm,@WRj +:ANL rm47_,AtWRjb is $(GROUP3) & ophi=5 & oplo=14; AtWRjb & s03=9; rm47_ & s03_=0 { rm47_ = rm47_ & AtWRjb; resultflags(rm47_); } + +# ANL Rm,@DRk +:ANL rm47_,AtDRkb is $(GROUP3) & ophi=5 & oplo=14; $(ATDRK) & AtDRkb & s03=11; rm47_ & s03_=0 { rm47_ = rm47_ & AtDRkb; resultflags(rm47_); } + +# ANL C,bit +:ANL "CY",xBitAddr is $(GROUP3) & ophi=10 & oplo=9; (d47=8 & s3=0 & bit02; xBitByteAddr) & xBitAddr { $(CY)=$(CY)& ((xBitByteAddr>>bit02)&1); resultflags(xBitByteAddr); } + +# ANL C,/bit +:ANL "CY",xBitAddr2 is $(GROUP3) & ophi=10 & oplo=9; (d47=15 & s3=0 & bit02; xBitByteAddr) & xBitAddr2 { $(CY)=$(CY)& (~((xBitByteAddr>>bit02)&1)); resultflags(xBitByteAddr); } + +# CLR bit +:CLR xBitAddr is $(GROUP3) & ophi=10 & oplo=9; (d47=12 & s3=0 & bit02; xBitByteAddr) & xBitAddr { tmp:1 = ~(1<>bit02)&1) == 1:1) goto Rel8; } + +# JBC bit,rel +:JBC xBitAddr,Rel8 is $(GROUP3) & ophi=10 & oplo=9; (d47=1 & s3=0 & bit02; xBitByteAddr) & xBitAddr; Rel8 { tmp:1 = 1<>bit02)&1)==0:1) goto Rel8; } + +# JNE rel +:JNE Rel8 is $(GROUP3) & ophi=7 & oplo=8; Rel8 { if ($(Z)==0) goto Rel8; } + +# JSG rel +:JSG Rel8 is $(GROUP3) & ophi=1 & oplo=8; Rel8 { if ($(Z)==0 && $(N)==$(OV)) goto Rel8; } + +# JSGE rel +:JSGE Rel8 is $(GROUP3) & ophi=5 & oplo=8; Rel8 { if ($(N)==$(OV)) goto Rel8; } + +# JSL rel +:JSL Rel8 is $(GROUP3) & ophi=4 & oplo=8; Rel8 { if ($(N)!=$(OV)) goto Rel8; } + +# JSLE rel +:JSLE Rel8 is $(GROUP3) & ophi=0 & oplo=8; Rel8 { if ($(Z)==1 || $(N)!=$(OV)) goto Rel8; } + +# LCALL @WRj +:LCALL AtWRjw is $(GROUP3) & ophi=9 & oplo=9; AtWRjw & s03=4 { ptr:3 = inst_next; push16(ptr:2); pc:3 = (ptr & 0xff0000) + zext(AtWRjw); call [pc]; } + +# LJMP @WRj +:LJMP AtWRjw is $(GROUP3) & ophi=8 & oplo=9; AtWRjw & s03=4 { ptr:3 = inst_next; pc:3 = (ptr & 0xff0000) + zext(AtWRjw); goto [pc]; } + +# MOV Rmd,Rms +:MOV rm47,rm03 is $(GROUP3) & ophi=7 & oplo=12; rm47 & rm03 { rm47 = rm03; } + +# MOV WRjd,WRjs +:MOV wrj47,wrj03 is $(GROUP3) & ophi=7 & oplo=13; wrj47 & wrj03 { wrj47 = wrj03; } + +# MOV DRkd,DRks +:MOV drk47,drk03 is $(GROUP3) & ophi=7 & oplo=15; drk47 & drk03 { drk47 = drk03; } + +# MOV Rm,#data +:MOV rm47,Data is $(GROUP3) & ophi=7 & oplo=14; rm47 & s03=0; Data { rm47 = Data; } + +# MOV WRj,#data16 +:MOV wrj47,Data16 is $(GROUP3) & ophi=7 & oplo=14; wrj47 & s03=4; Data16 { wrj47 = Data16; } + +# MOV DRk,#0data16 +:MOV drk47,Data16x0 is $(GROUP3) & ophi=7 & oplo=14; drk47 & s03=8; Data16x0 { drk47 = Data16x0; } + +# MOV DRk,#1data16 +:MOV drk47,Data16x1 is $(GROUP3) & ophi=7 & oplo=14; drk47 & s03=12; Data16x1 { drk47 = Data16x1; } + +# MOV Rm,dir8 +:MOV rm47,Direct is $(GROUP3) & ophi=7 & oplo=14; rm47 & s03=1; Direct { rm47 = Direct; } + +# MOV WRj,dir8 +:MOV wrj47,Direct8w is $(GROUP3) & ophi=7 & oplo=14; wrj47 & s03=5; Direct8w { wrj47 = Direct8w; } + +# MOV DRk,dir8 +:MOV drk47,Direct8w is $(GROUP3) & ophi=7 & oplo=14; drk47 & s03=13; Direct8w { drk47 = zext(Direct8w); } + +# MOV Rm,dir16 +:MOV rm47,Direct16b is $(GROUP3) & ophi=7 & oplo=14; rm47 & s03=3; Direct16b { rm47 = Direct16b; } + +# MOV WRj,dir16 +:MOV wrj47,Direct16w is $(GROUP3) & ophi=7 & oplo=14; wrj47 & s03=7; Direct16w { wrj47 = Direct16w; } + +# MOV DRk,dir16 +:MOV drk47,Direct16d is $(GROUP3) & ophi=7 & oplo=14; drk47 & s03=15; Direct16d { drk47 = Direct16d; } + +# MOV Rm,@WRj +:MOV rm47_,AtWRjb is $(GROUP3) & ophi=7 & oplo=14; AtWRjb & s03=9; rm47_ & s03_=0 { rm47_ = AtWRjb; } + +# MOV Rm,@DRk +:MOV rm47_,AtDRkb is $(GROUP3) & ophi=7 & oplo=14; $(ATDRK) & AtDRkb & s03=11; rm47_ & s03_=0 { rm47_ = AtDRkb; } + +# MOV WRjd,@WRjs +:MOV wrj47_,AtWRjw is $(GROUP3) & ophi=0 & oplo=11; AtWRjw & s03=8; wrj47_ & s03_=0 { wrj47_ = AtWRjw; } + +# MOV WRj,@DRk +:MOV wrj47_,AtDRkw is $(GROUP3) & ophi=0 & oplo=11; $(ATDRK) & AtDRkw & s03=10; wrj47_ & s03_=0 { wrj47_ = AtDRkw; } + +# MOV dir8,Rm +:MOV Direct,rm47 is $(GROUP3) & ophi=7 & oplo=10; rm47 & s03=1; Direct { Direct = rm47; } + +# MOV dir8,WRj +# TODO: !! Verify direct byte write restriction to SFR registers +:MOV Direct8w,wrj47 is $(GROUP3) & ophi=7 & oplo=10; wrj47 & s03=5; bank=0 & Direct8w { Direct8w = wrj47; } +:MOV Direct,wrj47 is $(GROUP3) & ophi=7 & oplo=10; wrj47 & s03=5; bank=1 & Direct { Direct = wrj47:1; } + +# MOV dir8,DRk +# TODO: !! Verify byte/word write restriction to internal memory (00-7f) +# TODO: !! Verify byte write restriction to SFR registers +:MOV Direct8w,drk47 is $(GROUP3) & ophi=7 & oplo=10; $(DRK47) & s03=13; bank=0 & Direct8w { Direct8w = drk47:2; } +:MOV Direct,drk47 is $(GROUP3) & ophi=7 & oplo=10; $(DRK47) & s03=13; bank=1 & Direct { Direct = drk47:1; } + +# MOV dir16,Rm +:MOV Direct16b,rm47 is $(GROUP3) & ophi=7 & oplo=10; rm47 & s03=3; Direct16b { Direct16b = rm47; } + +# MOV dir16,WRj +:MOV Direct16w,wrj47 is $(GROUP3) & ophi=7 & oplo=10; wrj47 & s03=7; Direct16w { Direct16w = wrj47; } + +# MOV dir16,DRk +:MOV Direct16d,drk47 is $(GROUP3) & ophi=7 & oplo=10; $(DRK47) & s03=15; Direct16d { Direct16d = drk47; } + +# MOV @WRj,Rm +:MOV AtWRjb,rm47_ is $(GROUP3) & ophi=7 & oplo=10; AtWRjb & s03=9; rm47_ & s03_=0 { AtWRjb = rm47_; } + +# MOV @DRk,Rm +:MOV AtDRkb,rm47_ is $(GROUP3) & ophi=7 & oplo=10; $(ATDRK) & AtDRkb & s03=11; rm47_ & s03_=0 { AtDRkb = rm47_; } + +# MOV @WRjd,WRjs +:MOV AtWRjw,wrj47_ is $(GROUP3) & ophi=1 & oplo=11; AtWRjw & s03=8; wrj47_ & s03_=0 { AtWRjw = wrj47_; } + +# MOV @DRk,WRj +:MOV AtDRkw,wrj47_ is $(GROUP3) & ophi=1 & oplo=11; $(ATDRK) & AtDRkw & s03=10; wrj47_ & s03_=0 { AtDRkw = wrj47_; } + +# MOV Rm,@WRj+dis16 +:MOV rm47,AtWRj03Dis16b is $(GROUP3) & ophi=0 & oplo=9; rm47 ... & AtWRj03Dis16b { AtWRj03Dis16b = rm47; } + +# MOV WRj,@WRj+dis16 +:MOV wrj47,AtWRj03Dis16w is $(GROUP3) & ophi=4 & oplo=9; wrj47 ... & AtWRj03Dis16w { AtWRj03Dis16w = wrj47; } + +# MOV Rm,@DRk+dis24 +:MOV rm47,AtDRk03Dis24b is $(GROUP3) & ophi=2 & oplo=9; (rm47 & $(DRK03)) ... & AtDRk03Dis24b { AtDRk03Dis24b = rm47; } + +# MOV WRj,@DRk+dis24 +:MOV wrj47,AtDRk03Dis24w is $(GROUP3) & ophi=6 & oplo=9; (wrj47 & $(DRK03)) ... & AtDRk03Dis24w { AtDRk03Dis24w = wrj47; } + +# MOV @WRj+dis16,Rm +:MOV AtWRj47Dis16b,rm03 is $(GROUP3) & ophi=1 & oplo=9; rm03 ... & AtWRj47Dis16b { AtWRj47Dis16b = rm03; } + +# MOV @WRj+dis16,WRj +:MOV AtWRj47Dis16w,wrj03 is $(GROUP3) & ophi=5 & oplo=9; wrj03 ... & AtWRj47Dis16w { AtWRj47Dis16w = wrj03; } + +# MOV @DRk+dis24,Rm +:MOV AtDRk47Dis24b,rm03 is $(GROUP3) & ophi=3 & oplo=9; (rm03 & $(DRK47)) ... & AtDRk47Dis24b { AtDRk47Dis24b = rm03; } + +# MOV @DRk+dis24,WRj +:MOV AtDRk47Dis24w,wrj03 is $(GROUP3) & ophi=7 & oplo=9; (wrj03 & $(DRK47)) ... & AtDRk47Dis24w { AtDRk47Dis24w = wrj03; } + +# MOV bit,C +:MOV xBitAddr,"CY" is $(GROUP3) & ophi=10 & oplo=9; (d47=9 & s3=0 & bit02; xBitByteAddr) & xBitAddr { xBitByteAddr = (xBitByteAddr) | (1<>bit02)&1); } + + +# MOVH DRk,#data16 +:MOVH drk47,Data16x0 is $(GROUP3) & ophi=7 & oplo=14; $(DRK47) & s03=12; Data16x0 { drk47 = (drk47 & 0xffff0000) | (Data16x0 << 16); } + +# MOVS WRj,Rm +:MOVZ wrj47,rm03 is $(GROUP3) & ophi=1 & oplo=10; wrj47 & rm03 { wrj47 = sext(rm03); } + +# MOVZ WRj,Rm +:MOVZ wrj47,rm03 is $(GROUP3) & ophi=0 & oplo=10; wrj47 & rm03 { wrj47 = zext(rm03); } + +# MUL Rmd,Rms +:MUL rm47,rm03 is $(GROUP3) & ophi=10 & oplo=12; rm47 & rm03 & rm47_d1 & rm47_d2 { result:2 = zext(rm47) * zext(rm03); tmp:2 = result>>8; rm47_d1 = tmp:1; rm47_d2 = result:1; } + +# MUL WRjd,WRjs +:MUL wrj47,wrj03 is $(GROUP3) & ophi=10 & oplo=13; wrj47 & wrj03 & wrj47_d1 & wrj47_d2 { result:4 = zext(wrj47) * zext(wrj03); tmp:4 = result>>16; wrj47_d1 = tmp:2; wrj47_d2 = result:2; } + +# ORL Rmd,Rms +:ORL rm47,rm03 is $(GROUP3) & ophi=4 & oplo=12; rm47 & rm03 { rm47 = rm47 | rm03; resultflags(rm47); } + +# ORL WRjd,WRjs +:ORL wrj47,wrj03 is $(GROUP3) & ophi=4 & oplo=13; wrj47 & wrj03 { wrj47 = wrj47 | wrj03; resultflags(wrj47); } + +# ORL Rm,#data +:ORL rm47,Data is $(GROUP3) & ophi=4 & oplo=14; rm47 & s03=0; Data { rm47 = rm47 | Data; resultflags(rm47); } + +# ORL WRj,#data16 +:ORL wrj47,Data16 is $(GROUP3) & ophi=4 & oplo=14; wrj47 & s03=4; Data16 { wrj47 = wrj47 | Data16; resultflags(wrj47); } + +# ORL Rm,dir8 +:ORL rm47,Direct is $(GROUP3) & ophi=4 & oplo=14; rm47 & s03=1; Direct { rm47 = rm47 | Direct; resultflags(rm47); } + +# ORL WRj,dir8 +:ORL wrj47,Direct8w is $(GROUP3) & ophi=4 & oplo=15; wrj47 & s03=5; Direct8w { wrj47 = wrj47 | Direct8w; resultflags(wrj47); } + +# ORL Rm,dir16 +:ORL rm47,Direct16b is $(GROUP3) & ophi=4 & oplo=14; rm47 & s03=3; Direct16b { rm47 = rm47 | Direct16b; resultflags(rm47); } + +# ORL WRj,dir16 +:ORL wrj47,Direct16w is $(GROUP3) & ophi=4 & oplo=14; wrj47 & s03=7; Direct16w { wrj47 = wrj47 | Direct16w; resultflags(wrj47); } + +# ORL Rm,@WRj +:ORL rm47_,AtWRjb is $(GROUP3) & ophi=4 & oplo=14; AtWRjb & s03=9; rm47_ & s03_=0 { rm47_ = rm47_ | AtWRjb; resultflags(rm47_); } + +# ORL Rm,@DRk +:ORL rm47_,AtDRkb is $(GROUP3) & ophi=4 & oplo=14; $(ATDRK) & AtDRkb & s03=11; rm47_ & s03_=0 { rm47_ = rm47_ | AtDRkb; resultflags(rm47_); } + +# ORL C,bit +:ORL "CY",xBitAddr is $(GROUP3) & ophi=10 & oplo=9; (d47=7 & s3=0 & bit02; xBitByteAddr) & xBitAddr { $(CY) = ((xBitByteAddr>>bit02)&1) | $(CY); } + +# ORL bit,C +:ORL "CY",xBitAddr2 is $(GROUP3) & ophi=10 & oplo=9; (d47=14 & s3=0 & bit02; xBitByteAddr) & xBitAddr2 { $(CY) = ((xBitByteAddr>>bit02)&1) | ($(CY) == 0); } + +# POP Rm +:POP rm47 is $(GROUP3) & ophi=13 & oplo=10; rm47 & s03=8 { pop8(rm47); } + +# POP WRj +:POP wrj47 is $(GROUP3) & ophi=13 & oplo=10; wrj47 & s03=9 { pop16(wrj47); } + +# POP DRk +:POP drk47 is $(GROUP3) & ophi=13 & oplo=10; $(DRK47) & s03=11 { pop16(drk47); } + +# PUSH #data +# TODO: manual did not specify A5 prefix, but would otherwise conflict with the XCH A,Rn instruction (8051) +:PUSH Data is $(GROUP3) & ophi=12 & oplo=10; d47=0 & s03=2; Data { push8(Data); } + +# PUSH #data16 +:PUSH Data16 is $(GROUP3) & ophi=12 & oplo=10; d47=0 & s03=6; Data16 { push16(Data16); } + +# PUSH Rm +:PUSH rm47 is $(GROUP3) & ophi=12 & oplo=10; rm47 & s03=8 { push8(rm47); } + +# PUSH WRj +:PUSH wrj47 is $(GROUP3) & ophi=12 & oplo=10; wrj47 & s03=9 { push16(wrj47); } + +# PUSH DRk +:PUSH drk47 is $(GROUP3) & ophi=12 & oplo=10; $(DRK47) & s03=11 { push16(drk47); } + +# SETB bit +:SETB xBitAddr^"."^xBitByteAddr is $(GROUP3) & ophi=10 & oplo=9; (d47=13 & s3=0 & bit02; xBitByteAddr) & xBitAddr { xBitByteAddr = (xBitByteAddr) | (1 << bit02); } + +# SLL Rm +:SLL rm47 is $(GROUP3) & ophi=3 & oplo=14; rm47 & s03=0 { $(CY) = ((rm47>>7) & 1); rm47 = rm47 << 1; resultflags(rm47); } + +# SLL WRj +:SLL wrj47 is $(GROUP3) & ophi=3 & oplo=14; wrj47 & s03=4 { $(CY) = ((wrj47>>15) & 1) == 1; wrj47 = wrj47 << 1; resultflags(wrj47); } + +# SRA Rm +:SRA rm47 is $(GROUP3) & ophi=0 & oplo=14; rm47 & s03=0 { $(CY) = rm47 & 1; rm47 = rm47 s>> 1; resultflags(rm47); } + +# SRA WRj +:SRA wrj47 is $(GROUP3) & ophi=0 & oplo=14; wrj47 & s03=4 { $(CY) = (wrj47 & 1) == 1; wrj47 = wrj47 s>> 1; resultflags(wrj47); } + +# SRL Rm +:SRL rm47 is $(GROUP3) & ophi=1 & oplo=14; rm47 & s03=0 { $(CY) = rm47 & 1; rm47 = rm47 >> 1; resultflags(rm47); } + +# SRL WRj +:SRL wrj47 is $(GROUP3) & ophi=1 & oplo=14; wrj47 & s03=4 { $(CY) = (wrj47 & 1) == 1; wrj47 = wrj47 >> 1; resultflags(wrj47); } + + +# SUB Rmd,Rms +:SUB rm47,rm03 is $(GROUP3) & ophi=9 & oplo=12; rm47 & rm03 { subflags(rm47,rm03); rm47 = rm47 - rm03; resultflags(rm47); } + +# SUB WRjd,WRjs +:SUB wrj47,wrj03 is $(GROUP3) & ophi=9 & oplo=13; wrj47 & wrj03 { subflags(wrj47,wrj03); wrj47 = wrj47 - wrj03; resultflags(wrj47); } + +# SUB DRkd,DRks +:SUB drk47,drk03 is $(GROUP3) & ophi=9 & oplo=15; $(DRK47) & $(DRK03) { subflags(drk47,drk03); drk47 = drk47 - drk03; resultflags(drk47);} + +# SUB Rm,#data +:SUB rm47,Data is $(GROUP3) & ophi=9 & oplo=14; rm47 & s03=0; Data { subflags(rm47,Data); rm47 = rm47 - Data; resultflags(rm47);} + +# SUB WRj,#data16 +:SUB wrj47,Data16 is $(GROUP3) & ophi=9 & oplo=14; wrj47 & s03=4; Data16 { subflags(wrj47,Data16); wrj47 = wrj47 - Data16; resultflags(wrj47);} + +# SUB DRk,#data16 +:SUB drk47,Data16x0 is $(GROUP3) & ophi=9 & oplo=14; $(DRK47) & s03=8; Data16x0 { subflags(drk47,Data16x0); drk47 = drk47 - Data16x0; resultflags(drk47);} + +# SUB Rm,dir8 +:SUB rm47,Direct is $(GROUP3) & ophi=9 & oplo=14; rm47 & s03=1; Direct { subflags(rm47,Direct); rm47 = rm47 - Direct; resultflags(rm47);} + +# SUB WRj,dir8 +:SUB wrj47,Direct8w is $(GROUP3) & ophi=9 & oplo=14; wrj47 & s03=5; Direct8w { subflags(wrj47,Direct8w); wrj47 = wrj47 - Direct8w; resultflags(wrj47);} + +# SUB Rm,dir16 +:SUB rm47,Direct16b is $(GROUP3) & ophi=9 & oplo=14; rm47 & s03=3; Direct16b { subflags(rm47,Direct16b); rm47 = rm47 - Direct16b; resultflags(rm47);} + +# SUB WRj,dir16 +:SUB wrj47,Direct16w is $(GROUP3) & ophi=9 & oplo=14; wrj47 & s03=7; Direct16w { subflags(wrj47,Direct16w); wrj47 = wrj47 - Direct16w; resultflags(wrj47);} + +# SUB Rm,@WRj +:SUB rm47_,AtWRjb is $(GROUP3) & ophi=9 & oplo=14; AtWRjb & s03=9; rm47_ & s03_=0 { subflags(rm47_,AtWRjb); rm47_ = rm47_ - AtWRjb; resultflags(rm47_);} + +# SUB Rm,@DRk +:SUB rm47_,AtDRkb is $(GROUP3) & ophi=9 & oplo=14; $(ATDRK) & AtDRkb & s03=11; rm47_ & s03_=0 { subflags(rm47_,AtDRkb); rm47_ = rm47_ - AtDRkb; resultflags(rm47_);} + + +# XRL Rmd,Rms +:XRL rm47,rm03 is $(GROUP3) & ophi=6 & oplo=12; rm47 & rm03 { rm47 = rm47 ^ rm03; resultflags(rm47); } + +# XRL WRjd,WRjs +:XRL wrj47,wrj03 is $(GROUP3) & ophi=6 & oplo=13; wrj47 & wrj03 { wrj47 = wrj47 ^ wrj03; resultflags(wrj47); } + +# XRL Rm,#data +:XRL rm47,Data is $(GROUP3) & ophi=6 & oplo=14; rm47 & s03=0; Data { rm47 = rm47 ^ Data; resultflags(rm47); } + +# XRL WRj,#data16 +:XRL wrj47,Data16 is $(GROUP3) & ophi=6 & oplo=14; wrj47 & s03=4; Data16 { wrj47 = wrj47 ^ Data16; resultflags(wrj47); } + +# XRL Rm,dir8 +:XRL rm47,Direct is $(GROUP3) & ophi=6 & oplo=14; rm47 & s03=1; Direct { rm47 = rm47 ^ Direct; resultflags(rm47); } + +# XRL WRj,dir8 +:XRL wrj47,Direct8w is $(GROUP3) & ophi=6 & oplo=14; wrj47 & s03=5; Direct8w { wrj47 = wrj47 ^ Direct8w; resultflags(wrj47); } + +# XRL Rm,dir16 +:XRL rm47,Direct16b is $(GROUP3) & ophi=6 & oplo=14; rm47 & s03=3; Direct16b { rm47 = rm47 ^ Direct16b; resultflags(rm47); } + +# XRL WRj,dir16 +:XRL wrj47,Direct16w is $(GROUP3) & ophi=6 & oplo=14; wrj47 & s03=7; Direct16w { wrj47 = wrj47 ^ Direct16w; resultflags(wrj47); } + +# XRL Rm,@Wrj +:XRL rm47_,AtWRjb is $(GROUP3) & ophi=6 & oplo=14; AtWRjb & s03=9; rm47_ & s03_=0 { rm47_ = rm47_ ^ AtWRjb; resultflags(rm47_); } + +# XRL Rm,@Drk +:XRL rm47_,AtDRkb is $(GROUP3) & ophi=6 & oplo=14; $(ATDRK) & AtDRkb & s03=11; rm47_ & s03_=0 { rm47_ = rm47_ ^ AtDRkb; resultflags(rm47_); } diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/80251.slaspec b/python/icicle/Ghidra/Processors/8051/data/languages/80251.slaspec new file mode 100644 index 0000000..14608a9 --- /dev/null +++ b/python/icicle/Ghidra/Processors/8051/data/languages/80251.slaspec @@ -0,0 +1,5 @@ +@define MCS251 "" + +@include "8051_main.sinc" + +@include "80251.sinc" diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/80390.cspec b/python/icicle/Ghidra/Processors/8051/data/languages/80390.cspec new file mode 100644 index 0000000..ec23f5e --- /dev/null +++ b/python/icicle/Ghidra/Processors/8051/data/languages/80390.cspec @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/80390.slaspec b/python/icicle/Ghidra/Processors/8051/data/languages/80390.slaspec new file mode 100644 index 0000000..f45e1d7 --- /dev/null +++ b/python/icicle/Ghidra/Processors/8051/data/languages/80390.slaspec @@ -0,0 +1,3 @@ +@define MCS80390 "" + +@include "8051_main.sinc" diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/8051.cspec b/python/icicle/Ghidra/Processors/8051/data/languages/8051.cspec new file mode 100644 index 0000000..ab1b883 --- /dev/null +++ b/python/icicle/Ghidra/Processors/8051/data/languages/8051.cspec @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/8051.ldefs b/python/icicle/Ghidra/Processors/8051/data/languages/8051.ldefs new file mode 100644 index 0000000..7c2700f --- /dev/null +++ b/python/icicle/Ghidra/Processors/8051/data/languages/8051.ldefs @@ -0,0 +1,53 @@ + + + + + 8051 Microcontroller Family + + + + + + 80251 Microcontroller Family + + + + 80390 in flat mode + + + + NXP/Phillips MX51 + + + + diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/8051.pspec b/python/icicle/Ghidra/Processors/8051/data/languages/8051.pspec new file mode 100644 index 0000000..8f2fbad --- /dev/null +++ b/python/icicle/Ghidra/Processors/8051/data/languages/8051.pspec @@ -0,0 +1,413 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/8051.slaspec b/python/icicle/Ghidra/Processors/8051/data/languages/8051.slaspec new file mode 100644 index 0000000..e3a4e65 --- /dev/null +++ b/python/icicle/Ghidra/Processors/8051/data/languages/8051.slaspec @@ -0,0 +1,3 @@ +@define MCS51 "" + +@include "8051_main.sinc" diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/8051_archimedes.cspec b/python/icicle/Ghidra/Processors/8051/data/languages/8051_archimedes.cspec new file mode 100644 index 0000000..5747aa6 --- /dev/null +++ b/python/icicle/Ghidra/Processors/8051/data/languages/8051_archimedes.cspec @@ -0,0 +1,99 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/8051_main.sinc b/python/icicle/Ghidra/Processors/8051/data/languages/8051_main.sinc new file mode 100644 index 0000000..d3d40e0 --- /dev/null +++ b/python/icicle/Ghidra/Processors/8051/data/languages/8051_main.sinc @@ -0,0 +1,917 @@ +# sleigh specification file for Intel 8051 + +#@define BIT_OPS "PCODEOPS" +#@define BIT_OPS "SHIFTS" +@define BIT_OPS "BIT_ADDRS" + +# It's sometimes clearer for decompilation to omit the pushing and +# restoring of the return value for function calls. +#@define OMIT_RETADDR + +# TODO !!! need to fully employ resultflags macro after resolving the use of the above BIT_OPS !!! +# TODO !!! Need to reconcile use of PSW vs. PSW1 for MCS251 !!! +# TODO !!! Need to fill-out SFR bits in 80251.pspec !!! + +@if defined(ENDIAN) +define endian=$(ENDIAN); +@else +define endian=big; +@endif + +define alignment=1; + +@if defined(MCS251) + +@define PTRSIZE 3 +@define SP_SIZE 3 + +define space RAM type=ram_space size=3 default; +define space SFR type=ram_space size=2; +define space BITS type=ram_space size=2; + +# 8051 spaces map to the following regions of the 80251 RAM space: +# CODE - 0xff0000-0xffffff +# EXTERNAL - 0x010000-0x01ffff +# INTERNAL - 0x000000-0x0000ff + +@elif defined(MCS51) + +@if defined(PTRSIZE) +@else +@define PTRSIZE 2 +@endif + +# SP stack pointer should be set to the size of the space it is used in, to avoid "issues" +# This is a minor inconsistency with the model and the actual processor in some cases +# If pristine SP sizing is required for rollover and such, the model should be changed +# +@define SP_SIZE 1 + +define space CODE type=ram_space size=$(PTRSIZE) default; +define space INTMEM type=ram_space size=1; +define space EXTMEM type=ram_space size=2; +define space SFR type=ram_space size=1; +define space BITS type=ram_space size=1; + +@elif defined(MCS80390) + +@define PTRSIZE 3 +@define SP_SIZE 1 + +define space CODE type=ram_space size=3 default; +define space INTMEM type=ram_space size=1; +define space EXTMEM type=ram_space size=3; +define space SFR type=ram_space size=1; +define space BITS type=ram_space size=1; + +@elif defined(MX51) + +@define PTRSIZE 3 +@define SP_SIZE 3 + +# The right thing for decompilation is to represent these +# as part of one uniform space, similar to the 80251. +# Remember to load code at 800000 +# +# xdata 0 (EXTMEM) +# data 7f0000 (INTMEM) +# code 800000 + +define space RAM type=ram_space size=3 default; +define space SFR type=ram_space size=1; +define space ESFR type=ram_space size=1; +define space BITS type=ram_space size=1; +define space EBITS type=ram_space size=1; + +# Unsure where stack really is, but probably don't want it on normal +# registers +#@define STACKBASE 0x7f0100 +@define STACKBASE 0 + +@else +# "error Unknown processor" +@endif + + + +define space register type=register_space size=1; + +# Register File +define register offset=0x00 size=1 [ R0 R1 R2 R3 R4 R5 R6 R7 ]; + +# for future jump table fixup +define register offset=0x70 size=1 [ jumpTableGuard1 jumpTableGuard2 ]; + +@if defined(MCS251) + +define register offset=0x08 size=1 [ R8 R9 B ACC R12 R13 R14 R15 + R16 R17 R18 R19 R20 R21 R22 R23 + R24 R25 R26 R27 R28 R29 R30 R31 +]; +define register offset=0x0 size=2 [ WR0 WR2 WR4 WR6 WR8 AB WR12 WR14 + WR16 WR18 WR20 WR22 WR24 WR26 WR28 WR30 +]; +define register offset=0x0 size=4 [ DR0 DR4 DR8 DR12 DR16 DR20 DR24 DR28 ]; + +define register offset=0x38 size=1 [ R56 DPXL DPH DPL R60 R61 SPH ]; +define register offset=0x3A size=2 [ DPTR ]; +define register offset=0x38 size=4 [ DPX SPX ]; + +@elif defined(MCS51) || defined(MCS80390) || defined(MX51) + +define register offset=0x00 size=4 [ R0R1R2R3 ]; +define register offset=0x01 size=3 [ R1R2R3 ]; # Used as R3R2R1 +define register offset=0x01 size=2 [ R2R1 ]; +define register offset=0x00 size=2 [ R0R1 R2R3 R4R5 R6R7 ]; +define register offset=0x04 size=4 [ R4R5R6R7 ]; +define register offset=0x05 size=3 [ R5R6R7 ]; + +define register offset=0x0A size=1 [ B ACC ]; # relocated to facilitate AB 16-bit access +define register offset=0x0A size=2 [ AB ]; + +@if defined(MCS51) || defined(MX51) +define register offset=0x82 size=2 [ DPTR ]; +define register offset=0x82 size=1 [ DPH DPL ]; # relocated to facilitate DPTR 16-bit access +@elif defined(MCS80390) + +# Following existing example, relocated DPX, DPH, and DPL for DPTR +# access. Rework some direct moves to compensate. Not clear that all +# cases are covered, thus might be problematic hack in the long term. +define register offset=0x82 size=3 [ DPTR ]; +define register offset=0x82 size=1 [ DPX DPH DPL ]; +@endif + +@else +# "error Unknown processor" +@endif + + +define register offset=0x40 size=$(SP_SIZE) [ SP ]; +define register offset=0x44 size=$(PTRSIZE) [ PC ]; +define register offset=0x48 size=1 [ PSW ]; +@if defined(DUAL_DPTR) +# Dual DPTR +# Rather than model it as context, we're just going +# to special case the INC and DEC instructions +# to swap the register values +define register offset=0x4a size=2 [ DPTR2 ]; +define register offset=$(DPS_REG_NUM) size=1 [ AUXR1 ]; # Bit 0 is DPS +@endif + +@define CY "PSW[7,1]" +@define AC "PSW[6,1]" +@define N "PSW[5,1]" +@define RS1 "PSW[4,1]" +@define RS0 "PSW[3,1]" +@define OV "PSW[2,1]" +@define Z "PSW[1,1]" + +@if defined(MX51) +# remap these into the normal register file for decompiler use. +# Really belong on ESFR @0xfc - 0xfe with order EPL EPM EPH +define register offset=0xc0 size=1 [ EPH EPM EPL ]; +define register offset=0xc0 size=3 [ EPTR ]; +@endif + +@if defined(MCS251) + +define register offset=0x50 size=4 contextReg; + +define context contextReg + phase = (0,0) + srcMode = (1,1) # (reflects UCONFIG0.0) 1: source mode, 0: binary mode + A5Prefix = (2,2) # reflects presence of A5 prefix +; + +# GROUP1 - MCS51 instructions in 0x00-0x5F range +@define GROUP1 "epsilon" + +# GROUP2 - MCS51 instructions in 0x60-0xff range +@define GROUP2 "((srcMode=0 & A5Prefix=0) | (srcMode=1 & A5Prefix=1))" + +# GROUP3 - MCS251 instructions in 0x60-0xff range +@define GROUP3 "((srcMode=0 & A5Prefix=1) | (srcMode=1 & A5Prefix=0))" + +@elif defined(MCS51) || defined(MCS80390) || defined(MX51) + +@define GROUP1 "epsilon" +@define GROUP2 "epsilon" +@define GROUP3 "epsilon" + +@endif + +define pcodeop decimal_adjust; +define pcodeop nop; + +@if BIT_OPS == "PCODEOPS" +define pcodeop get; +define pcodeop set; +define pcodeop set_bit_value; +define pcodeop clr; +@endif + + +#TOKENS + +define token opbyte (8) + opfull = (0,7) + oplo = (0,3) + ophi = (4,7) + rn = (0,2) + rnfill = (3,3) + ri = (0,0) + rifill = (1,3) + opaddr = (5,7) + addrfill = (4,4) + + b_0000 = (0,0) + b_0001 = (0,1) + b_0002 = (0,2) + b_0005 = (0,5) + b_0101 = (1,1) + b_0107 = (1,7) + b_0207 = (2,7) + b_0307 = (3,7) + b_0607 = (6,7) +@if defined(MX51) + PRi_sel = (2,2) + PRi_revend = (2,2) # reverse endian + emov_delta = (0,1) +@endif +; +define token AddrByte (8) + direct = (0,7) + bank = (7,7) + sfr = (0,6) + sfr6 = (6,6) + sfrlo = (0,3) + mainreg = (0,6) + direct17 = (1,7) +; +define token AddrByte2 (8) + direct2 = (0,7) + bank2 = (7,7) + sfr2 = (0,6) + sfr26 = (6,6) + sfr2lo = (0,3) + mainreg2 = (0,6) +; +define token BitByte (8) + bitaddr8 = (0,7) + bitaddr27 = (2,7) + bitbank = (7,7) + sfrbyte = (3,7) + bitaddr57 = (5,7) + sfrbit6 = (6,6) + sfrbit3 = (3,3) + sfrbit = (0,2) dec + lowbyte = (3,6) + bitaddr0 = (0,0) +; +define token AddrTwo (16) + addr16 = (0,15) +; +@if defined(MCS80390) +# todo: deconflict with 80251 version +define token AddrThree (24) + addr24 = (0,23) +; +@endif + +define token RelByte (8) rel8=(0,7) signed; +define token ImmedByte (8) data=(0,7); +define token ImmedTwo (16) + data16 = (0,15) + rel16 = (0,15) signed +; +@if defined(MCS80390) +define token ImmedThree (24) + data24 = (0,23) +; +@endif + +@if defined(MCS80390) +define token aopword (24) + aoplo = (16,19) + aopaddr = (21,23) + aaddrfill = (20,20) + adata = (0,15) +; +@else +define token aopword (16) + aoplo = (8,11) + aopaddr = (13,15) + aaddrfill = (12,12) + adata = (0,7) +; +@endif + +attach variables rn [ R0 R1 R2 R3 R4 R5 R6 R7 ]; +attach variables ri [ R0 R1 ]; + +# flags macros + +#macro addflags(op1, op2) { # Flags set by add instructions +# PSW = PSW & 0x7b; +# PSW = PSW | (carry(op1,op2)<<7) # Check for carry +# | (scarry(op1,op2)<<2); # Check for signed carry +#} + +#macro subflags(op1, op2) { # Flags set by sub instructions +# PSW = PSW & 0x7b; +# PSW = PSW | ((op1>sfrbit)&1); resultflags(tmp); } +:ANL CY,BitAddr2 is $(GROUP1) & CY & ophi=11 & oplo=0; BitAddr2 & bitaddr57=7 & sfrbit3=0 & sfrbit & BitByteAddr {tmp:1 = BitByteAddr; $(CY)=$(CY)& (~((tmp>>sfrbit)&1)); } +@if BIT_OPS == "BIT_ADDRS" +:ANL CY,BitAddr is $(GROUP1) & CY & ophi=8 & oplo=2; BitAddr & sfrbit & BitByteAddr {$(CY)=$(CY)& BitAddr; } +:ANL CY,BitAddr2 is $(GROUP1) & CY & ophi=11 & oplo=0; BitAddr2 & sfrbit & BitByteAddr {$(CY)=$(CY)& ~BitAddr2; } +@elif BIT_OPS == "PCODEOPS" +:ANL CY,BitAddr is $(GROUP1) & CY & ophi=8 & oplo=2; BitAddr & sfrbit & BitByteAddr {$(CY)=$(CY)& get(BitAddr, BitByteAddr); } +:ANL CY,BitAddr2 is $(GROUP1) & CY & ophi=11 & oplo=0; BitAddr2 & sfrbit & BitByteAddr {$(CY)=$(CY)& (get(BitAddr2, BitByteAddr)^1); } +@elif BIT_OPS == "SHIFTS" +:ANL CY,BitAddr is $(GROUP1) & CY & ophi=8 & oplo=2; BitAddr & sfrbit & BitByteAddr {$(CY)=$(CY)& ((BitByteAddr>>sfrbit)&1); } +:ANL CY,BitAddr2 is $(GROUP1) & CY & ophi=11 & oplo=0; BitAddr2 & sfrbit & BitByteAddr {$(CY)=$(CY)& (~((BitByteAddr>>sfrbit)&1)); } +@endif + +:CJNE Areg,Direct,Rel8 is $(GROUP1) & ophi=11 & oplo=5 & Areg; Direct; Rel8 { compflags(ACC,Direct); if (ACC!=Direct) goto Rel8; } +:CJNE Areg,Data,Rel8 is $(GROUP1) & ophi=11 & oplo=4 & Areg; Data; Rel8 { compflags(ACC,Data); if (ACC!=Data) goto Rel8; } +:CJNE rn,Data,Rel8 is $(GROUP2) & ophi=11 & rnfill=1 & rn; Data; Rel8 { compflags(rn,Data); if (rn!=Data) goto Rel8; } +:CJNE Ri,Data,Rel8 is $(GROUP2) & ophi=11 & rifill=3 & Ri; Data; Rel8 { compflags(Ri,Data); if (Ri!=Data) goto Rel8; } + +:CLR Areg is $(GROUP1) & ophi=14 & oplo=4 & Areg { ACC = 0; } +:CLR CY is $(GROUP1) & CY & ophi=12 & oplo=3 {$(CY)= 0; } + +:CLR BitAddr is $(GROUP1) & ophi=12 & oplo=2; BitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & BitByteAddr { local tmp = ~(1<>sfrbit)&1) == 1:1) goto Rel8; } +:JBC BitAddr,Rel8 is $(GROUP1) & ophi=1 & oplo=0; BitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & BitByteAddr; Rel8 { tmp:1 = 1<>sfrbit)&1) == 1:1) goto Rel8; } +:JBC BitAddr,Rel8 is $(GROUP1) & ophi=1 & oplo=0; BitAddr & sfrbit & BitByteAddr; Rel8 { tmp:1 = 1<>sfrbit)&1)==0:1) goto Rel8; } +@if BIT_OPS == "BIT_ADDRS" +:JNB BitAddr,Rel8 is $(GROUP1) & ophi=3 & oplo=0; BitAddr & sfrbit & BitByteAddr; Rel8 { if (BitAddr == 0:1) goto Rel8; } +@elif BIT_OPS == "PCODEOPS" +:JNB BitAddr,Rel8 is $(GROUP1) & ophi=3 & oplo=0; BitAddr & sfrbit & BitByteAddr; Rel8 { if (get(BitAddr, BitByteAddr)==0:1) goto Rel8; } +@elif BIT_OPS == "SHIFTS" +:JNB BitAddr,Rel8 is $(GROUP1) & ophi=3 & oplo=0; BitAddr & sfrbit & BitByteAddr; Rel8 { if (((BitByteAddr>>sfrbit)&1)==0:1) goto Rel8; } +@endif + +:JNC Rel8 is $(GROUP1) & ophi=5 & oplo=0; Rel8 { if ($(CY) == 0) goto Rel8; } +:JNZ Rel8 is $(GROUP1) & ophi=7 & oplo=0; Rel8 { if (ACC != 0) goto Rel8; } +:JZ Rel8 is $(GROUP1) & ophi=6 & oplo=0; Rel8 { if (ACC == 0) goto Rel8; } + +@if defined(MCS80390) +:LCALL Addr24 is $(GROUP1) & ophi=1 & oplo=2; Addr24 { ret:$(PTRSIZE) = inst_next; push24(ret); call Addr24; } +:LJMP Addr24 is $(GROUP1) & ophi=0 & oplo=2; Addr24 { goto Addr24; } +@elif defined(MX51) +:LCALL Addr16 is $(GROUP1) & ophi=1 & oplo=2; Addr16 { ret:2 = inst_next; push16(ret); call Addr16; } +:LJMP Addr16 is $(GROUP1) & ophi=0 & oplo=2; Addr16 { goto Addr16; } +@else +:LCALL Addr16 is $(GROUP1) & ophi=1 & oplo=2; Addr16 { ret:$(PTRSIZE) = inst_next; push16(ret); call Addr16; } +:LJMP Addr16 is $(GROUP1) & ophi=0 & oplo=2; Addr16 { goto Addr16; } +@endif + +:MOV Areg,rn is $(GROUP2) & ophi=14 & rnfill=1 & rn & Areg { ACC = rn; } +:MOV Areg,Direct is $(GROUP1) & ophi=14 & oplo=5 & Areg; Direct { ACC = Direct; } +:MOV Areg,Ri is $(GROUP2) & ophi=14 & Areg & rifill=3 & Ri { ACC = Ri; } +:MOV Areg,Data is $(GROUP1) & ophi=7 & oplo=4 & Areg; Data { ACC = Data; } +:MOV rn,Areg is $(GROUP2) & ophi=15 & rnfill=1 & rn & Areg { rn = ACC; } +:MOV rn,Direct is $(GROUP2) & ophi=10 & rnfill=1 & rn; Direct { rn = Direct; } +:MOV rn,Data is $(GROUP2) & ophi=7 & rnfill=1 & rn; Data { rn = Data; } +:MOV Direct,Areg is $(GROUP1) & ophi=15 & oplo=5 & Areg; Direct { Direct = ACC; } +:MOV Direct,rn is $(GROUP2) & ophi=8 & rnfill=1 & rn; Direct { Direct = rn; } +:MOV Direct2,Direct is $(GROUP1) & ophi=8 & oplo=5; Direct; Direct2 { Direct2 = Direct; } +:MOV Direct,Ri is $(GROUP2) & ophi=8 & rifill=3 & Ri; Direct { Direct = Ri; } +:MOV Direct,Data is $(GROUP1) & ophi=7 & oplo=5; Direct; Data { Direct = Data; } +:MOV Ri,Areg is $(GROUP2) & ophi=15 & rifill=3 & Ri & Areg { Ri = ACC; } +:MOV Ri,Direct is $(GROUP2) & ophi=10 & rifill=3 & Ri; Direct { Ri = Direct; } +:MOV Ri,Data is $(GROUP2) & ophi=7 & rifill=3 & Ri; Data { Ri = Data; } +@if defined(MCS80390) +:MOV DPTRreg,Data24 is $(GROUP1) & ophi=9 & oplo=0 & DPTRreg; Data24 { DPTR = Data24; } +@else +:MOV DPTRreg,Data16 is $(GROUP1) & ophi=9 & oplo=0 & DPTRreg; Data16 { DPTR = Data16; } +@endif + +:MOV CY,BitAddr is $(GROUP1) & CY & ophi=10 & oplo=2; BitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & BitByteAddr {$(CY)= (BitByteAddr>>sfrbit)&1; } +:MOV BitAddr,CY is $(GROUP1) & CY & ophi=9 & oplo=2; BitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & BitByteAddr { BitByteAddr = BitByteAddr & (~(1<>sfrbit)&1; } +:MOV BitAddr,CY is $(GROUP1) & CY & ophi=9 & oplo=2; BitAddr & sfrbit & BitByteAddr { BitByteAddr = BitByteAddr & (~(1<>sfrbit)&1); } +:ORL CY,BitAddr2 is $(GROUP1) & CY & ophi=10 & oplo=0; BitAddr2 & bitaddr57=7 & sfrbit3=0 & sfrbit & BitByteAddr {$(CY)=$(CY)| (((BitByteAddr>>sfrbit)&1)^1); } +@if BIT_OPS == "BIT_ADDRS" +:ORL CY,BitAddr is $(GROUP1) & CY & ophi=7 & oplo=2; BitAddr & sfrbit & BitByteAddr {$(CY)=$(CY)| BitAddr; } +:ORL CY,BitAddr2 is $(GROUP1) & CY & ophi=10 & oplo=0; BitAddr2 & sfrbit & BitByteAddr {$(CY)=$(CY)| (BitAddr2^1); } +@elif BIT_OPS == "PCODEOPS" +:ORL CY,BitAddr is $(GROUP1) & CY & ophi=7 & oplo=2; BitAddr & sfrbit & BitByteAddr {$(CY)=$(CY)| get(BitAddr, BitByteAddr); } +:ORL CY,BitAddr2 is $(GROUP1) & CY & ophi=10 & oplo=0; BitAddr2 & sfrbit & BitByteAddr {$(CY)=$(CY)| (get(BitAddr2, BitByteAddr)^1); } +@elif BIT_OPS == "SHIFTS" +:ORL CY,BitAddr is $(GROUP1) & CY & ophi=7 & oplo=2; BitAddr & sfrbit & BitByteAddr {$(CY)=$(CY)| ((BitByteAddr>>sfrbit)&1); } +:ORL CY,BitAddr2 is $(GROUP1) & CY & ophi=10 & oplo=0; BitAddr2 & sfrbit & BitByteAddr {$(CY)=$(CY)| (((BitByteAddr>>sfrbit)&1)^1); } +@endif + +:POP Direct is $(GROUP1) & ophi=13 & oplo=0; Direct { pop8(Direct); } + +:PUSH Direct is $(GROUP1) & ophi=12 & oplo=0; Direct { push8(Direct); } + +:RET is $(GROUP1) & ophi=2 & oplo=2 { +@if defined(MCS251) || defined(MX51) +pc:2 = 0; pop16(pc); pc3:3 = (inst_next & 0xff0000) + zext(pc); return[pc3]; +@elif defined(MCS51) +pc:2 = 0; pop16(pc); return[pc]; +@elif defined(MCS80390) +pc:3 = 0; pop24(pc); return[pc]; +@endif +} + +:RETI is $(GROUP1) & ophi=3 & oplo=2 { +@if defined(MCS251) || defined(MX51) +pc:2 = 0; pop16(pc); pc3:3 = (inst_next & 0xff0000) + zext(pc); return[pc3]; +@elif defined(MCS51) +pc:2 = 0; pop16(pc); return[pc]; +@elif defined(MCS80390) +pc:3 = 0; pop24(pc); return[pc]; +@endif +} + +:RL Areg is $(GROUP1) & ophi=2 & oplo=3 & Areg { ACC = (ACC<<1) | (ACC>>7); } +:RLC Areg is $(GROUP1) & ophi=3 & oplo=3 & Areg { tmp : 1 = (ACC&0x80)>>7; ACC = (ACC<<1) | $(CY);$(CY)= tmp; } +:RR Areg is $(GROUP1) & ophi=0 & oplo=3 & Areg { ACC = (ACC>>1) | (ACC<<7); } +:RRC Areg is $(GROUP1) & ophi=1 & oplo=3 & Areg { tmp : 1 = ACC&1; ACC = (ACC>>1) | ($(CY)<<7);$(CY)= tmp; } + +:SETB CY is $(GROUP1) & CY & ophi=13 & oplo=3 { $(CY)=1; } + +:SETB BitAddr is $(GROUP1) & ophi=13 & oplo=2; BitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & BitByteAddr { BitByteAddr = BitByteAddr | (1<>4) | (ACC<<4); } + +:XCH Areg,rn is $(GROUP2) & ophi=12 & rnfill=1 & rn & Areg { tmp : 1 = ACC; ACC = rn; rn = tmp; } +:XCH Areg,Direct is $(GROUP1) & ophi=12 & oplo=5 & Areg; Direct { tmp : 1 = ACC; ACC = Direct; Direct = tmp; } +:XCH Areg,Ri is $(GROUP2) & ophi=12 & rifill=3 & Ri & Areg { tmp : 1 = ACC; ACC = Ri; Ri = tmp; } + +# TODO: This instruction appears to be in both GROUP2 & GROUP3 (always available) +:XCHD Areg,Ri is ophi=13 & Areg & rifill=3 & Ri { tmp : 1 = ACC & 0xf; ACC = (ACC&0xf0) | (Ri&0xf); Ri = (Ri&0xf0) | tmp; } + +:XRL Areg,rn is $(GROUP2) & ophi=6 & rnfill=1 & rn & Areg { ACC = ACC ^ rn; } +:XRL Areg,Direct is $(GROUP1) & ophi=6 & oplo=5 & Areg; Direct { ACC = ACC ^ Direct; } +:XRL Areg,Ri is $(GROUP2) & ophi=6 & rifill=3 & Ri & Areg { ACC = ACC ^ Ri; } +:XRL Areg,Data is $(GROUP1) & ophi=6 & oplo=4 & Areg; Data { ACC = ACC ^ Data; } +:XRL Direct,Areg is $(GROUP1) & ophi=6 & oplo=2 & Areg; Direct { Direct = Direct ^ ACC; } +:XRL Direct,Data is $(GROUP1) & ophi=6 & oplo=3; Direct; Data { Direct = Direct ^ Data; } + diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/mx51.cspec b/python/icicle/Ghidra/Processors/8051/data/languages/mx51.cspec new file mode 100644 index 0000000..2af7a38 --- /dev/null +++ b/python/icicle/Ghidra/Processors/8051/data/languages/mx51.cspec @@ -0,0 +1,73 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/mx51.pspec b/python/icicle/Ghidra/Processors/8051/data/languages/mx51.pspec new file mode 100644 index 0000000..ea50e2c --- /dev/null +++ b/python/icicle/Ghidra/Processors/8051/data/languages/mx51.pspec @@ -0,0 +1,423 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/mx51.sinc b/python/icicle/Ghidra/Processors/8051/data/languages/mx51.sinc new file mode 100644 index 0000000..9279c1e --- /dev/null +++ b/python/icicle/Ghidra/Processors/8051/data/languages/mx51.sinc @@ -0,0 +1,332 @@ +# Extended mx51 instructions live here, so as to avoid further +# complicating the main 8051 file. + +# All have 0xa5 as prefix, so subtract one +define token TwoByteOp (8) + b2op = (0,7) +; +define token ThreeByteOp (16) + b3op = (8,15) +; +define token FourByteOp (24) + b4op = (16,23) +; + +define token EcallDispTok (24) + imm24 = (0,23) +; + +#################### + +# Note that PRi is used in little endian format, as R3 is the MSB +attach variables PRi_revend [ R1R2R3 R5R6R7 ]; +@define ENDIANSWAPFUNC "" +@if defined(ENDIANSWAPFUNC) +define pcodeop endian_swap; +PRi: PRi_revend is PRi_revend { tmp:3 = endian_swap(PRi_revend); export tmp; } +@else +PRi: PRi_revend is PRi_sel=0 & PRi_revend { tmp:3 = (zext(R3) << 16) | (zext(R2) << 8) | zext(R1); export tmp; } +PRi: PRi_revend is PRi_sel=1 & PRi_revend { tmp:3 = (zext(R7) << 16) | (zext(R6) << 8) | zext(R5); export tmp; } +@endif +#################### + +@ifdef OMIT_RETADDR +macro push24(val) { val = val; } +macro pop24(val) { val = val; } + +@else +# stack grows up. +macro push24(val) { + ptr:3 = zext(SP) + 1 + $(STACKBASE); + *[RAM]:3 ptr = val; + SP = SP + 2; +} +macro pop24(val) { + ptr:3 = zext(SP - 2) + $(STACKBASE); + val = *[RAM]:3 ptr; + SP = SP - 3; +} +@endif + +#################### + +eptrReg: EPTR is EPTR { export EPTR; } +APlusEptr: "@"Areg"+"eptrReg is Areg & eptrReg { tmp:3 = EPTR + zext(ACC); export tmp; } +ecallImmAddr: imm24 is imm24 { export *:1 imm24; } +add_with_pr_const: emov_delta is emov_delta { tmp:1 = emov_delta; export tmp; } +add_with_pr_const: "4" is emov_delta = 0 { tmp:1 = 4; export tmp; } + +EDirect: mainreg is bank=0 & mainreg { tmp:3 = mainreg + 0x7f0000; export *[RAM]:1 tmp; } +EDirect: direct is bank=1 & direct { export *[ESFR]:1 direct; } +EDirect: EPL is bank=1 & direct=0xfc & EPL { export EPL; } +EDirect: EPM is bank=1 & direct=0xfd & EPM { export EPM; } +EDirect: EPH is bank=1 & direct=0xfe & EPH { export EPH; } + +EDirect2: mainreg2 is bank2=0 & mainreg2 { tmp:3 = mainreg2 + 0x7f0000; export *[RAM]:1 tmp; } +EDirect2: direct2 is bank2=1 & direct2 { export *[ESFR]:1 direct2; } +EDirect2: EPL is bank2=1 & direct2=0xfc & EPL { export EPL; } +EDirect2: EPM is bank2=1 & direct2=0xfd & EPM { export EPM; } +EDirect2: EPH is bank2=1 & direct2=0xfe & EPH { export EPH; } + +# Continuing with pattern via copying from stock 8051 sleighspec. +# Note that there is a known bug with the Bit addressing of the SFR. +EBitAddr: bitaddr is bitbank=1 & sfrbyte & sfrbit [ bitaddr =(sfrbyte << 3)+sfrbit; ] { export *[EBITS]:1 bitaddr; } +EBitAddr: bitaddr is bitbank=0 & lowbyte & sfrbit [ bitaddr =(lowbyte << 3)+sfrbit; ] { export *[EBITS]:1 bitaddr; } +EBitAddr2: "/"bitaddr is bitbank=1 & sfrbyte & sfrbit [ bitaddr =(sfrbyte << 3)+sfrbit; ] { export *[EBITS]:1 bitaddr; } +EBitAddr2: "/"bitaddr is bitbank=0 & lowbyte & sfrbit [ bitaddr =(lowbyte << 3)+sfrbit; ] { export *[EBITS]:1 bitaddr; } + +EBitByteAddr: byteaddr is bitbank=1 & sfrbyte & sfrbit [ byteaddr =(sfrbyte << 3); ] { export *[ESFR]:1 byteaddr; } +EBitByteAddr: byteaddr is bitbank=0 & lowbyte & sfrbit [ byteaddr = lowbyte + 0x20; ] { tmp:3 = byteaddr + 0x7f0000; export *[RAM]:1 tmp; } + + +#################### + +:inc EDirect is opfull=0xa5; ophi=0 & oplo=5; EDirect { + EDirect = EDirect + 1; +} +:dec EDirect is opfull=0xa5; opfull=0x15; EDirect { + EDirect = EDirect - 1; +} +:add Areg,EDirect is opfull=0xa5; opfull=0x25 & Areg; EDirect { + addflags(ACC,EDirect); ACC = ACC + EDirect; resultflags(ACC); +} +:addc Areg,EDirect is opfull=0xa5; opfull=0x35 & Areg; EDirect { + tmp:1 =$(CY)+ EDirect; addflags(ACC,tmp); ACC = ACC + tmp; resultflags(ACC); +} +:orl Areg,EDirect is opfull=0xa5; opfull=0x45 & Areg; EDirect { + ACC = ACC | EDirect; +} +:anl Areg,EDirect is opfull=0xa5; opfull=0x55 & Areg; EDirect { + ACC = ACC & EDirect; resultflags(ACC); +} +:xrl Areg,EDirect is opfull=0xa5; opfull=0x65 & Areg; EDirect { + ACC = ACC ^ EDirect; +} +:subb Areg,EDirect is opfull=0xa5; opfull=0x95 & Areg; EDirect { + tmp:1 = EDirect+$(CY); subflags(ACC,tmp); ACC = ACC - tmp; +} +:xch Areg,EDirect is opfull=0xa5; opfull=0xc5 & Areg; EDirect { + tmp:1 = ACC; ACC = EDirect; EDirect = tmp; +} +:mov Areg,EDirect is opfull=0xa5; opfull=0xe5 & Areg; EDirect { + ACC = EDirect; +} +:mov EDirect,Areg is opfull=0xa5; opfull=0xf5 & Areg; EDirect { + EDirect = ACC; +} +:mov EDirect,rn is opfull=0xa5; ophi=0x8 & rnfill=1 & rn; EDirect { + EDirect = rn; +} +:mov rn,EDirect is opfull=0xa5; ophi=0xa & rnfill=1 & rn; EDirect { + rn = EDirect; +} +:mov EDirect2,EDirect is opfull=0xa5; ophi=8 & oplo=5; EDirect; EDirect2 { + EDirect2 = EDirect; +} +:mov EDirect,Data is opfull=0xa5; ophi=7 & oplo=5; EDirect; Data { + EDirect = Data; +} +:mov EDirect,Ri is opfull=0xa5; ophi=8 & rifill=3 & Ri; EDirect { + EDirect = Ri; +} +:mov Ri,EDirect is opfull=0xa5; ophi=10 & rifill=3 & Ri; EDirect { + Ri = EDirect; +} +:orl EDirect,Areg is opfull=0xa5; ophi=4 & oplo=2 & Areg; EDirect { + EDirect = EDirect | ACC; +} +:anl EDirect,Areg is opfull=0xa5; ophi=5 & oplo=2 & Areg; EDirect { + tmp:1 = EDirect & ACC; EDirect = tmp; resultflags(tmp); +} +:xrl EDirect,Areg is opfull=0xa5; ophi=6 & oplo=2 & Areg; EDirect { + EDirect = EDirect ^ ACC; +} +:xrl EDirect,Data is opfull=0xa5; ophi=6 & oplo=3; EDirect; Data { + EDirect = EDirect ^ Data; +} +:anl EDirect,Data is opfull=0xa5; ophi=5 & oplo=3; EDirect; Data { + tmp:1 = EDirect & Data; EDirect = tmp; resultflags(tmp); +} +:orl EDirect,Data is opfull=0xa5; ophi=4 & oplo=3 & Areg; EDirect; Data { + EDirect = EDirect | Data; +} +:push EDirect is opfull=0xa5; opfull=0xc0; EDirect { + push8(EDirect); +} +:pop EDirect is opfull=0xa5; opfull=0xd0; EDirect { + pop8(EDirect); +} +:cjne Areg,EDirect,Rel8 is opfull=0xa5; ophi=11 & oplo=5 & Areg; EDirect; Rel8 { + compflags(ACC,EDirect); if (ACC!=EDirect) goto Rel8; +} +:djnz EDirect,Rel8 is opfull=0xa5; ophi=13 & oplo=5; EDirect; Rel8 { + EDirect = EDirect - 1; + if (EDirect!=0) goto Rel8; +} + + +# EPTR operations +:ejmp ecallImmAddr is opfull=0xa5; opfull=0x02; ecallImmAddr { + goto ecallImmAddr; +} +:ecall ecallImmAddr is opfull=0xa5; opfull=0x12; ecallImmAddr { + ret:3 = inst_next; push24(ret); call ecallImmAddr; +} +:mov eptrReg,ecallImmAddr is opfull=0xa5; opfull=0x90; ecallImmAddr & eptrReg & imm24 { + EPTR = imm24; +} +:eret is opfull=0xa5; opfull=0x22 { + pc:3 = 0; pop24(pc); return[pc]; +} +:jmp APlusEptr is opfull=0xa5; opfull=0x73 & APlusEptr { + # this is correct, but causes disassembler problems + # goto APlusEptr; + # added additional indirection to stop disassembler problems. + goto [APlusEptr]; +} +:movx Areg",@"eptrReg is opfull=0xa5; opfull=0xe0 & Areg & eptrReg { + ACC = *:1 EPTR; +} +:movx "@"eptrReg,Areg is opfull=0xa5; opfull=0xf0 & Areg & eptrReg { + *:1 EPTR = ACC; +} +:movc Areg,APlusEptr is opfull=0xa5; opfull=0x93 & Areg & APlusEptr { + ACC = *:1 APlusEptr; +} +:inc EPTR is opfull=0xa5; opfull=0xa3 & EPTR { + EPTR = EPTR + 1; +} + +# PRi operations +:emov Areg",@"PRi"+"emov_delta is opfull=0xa5; ophi=4 & PRi & emov_delta & Areg { + tmp:3 = zext(PRi) + emov_delta; + ACC = *:1 tmp; +} +:emov "@"PRi"+"emov_delta,Areg is opfull=0xa5; ophi=5 & PRi & emov_delta & Areg { + tmp:3 = PRi + emov_delta; + *:1 tmp = ACC; +} +:add PRi_revend,add_with_pr_const is opfull=0xa5; ophi=6 & PRi_revend & PRi & add_with_pr_const { + x:3 = zext(add_with_pr_const); + tmp:3 = PRi + x; +@if defined(ENDIANSWAPFUNC) + y:3 = endian_swap(tmp); +@else + y:3 = (tmp << 16) | (tmp & 0x00ff00) | zext(tmp >> 16); +@endif + PRi_revend = y; +} + +# bit operations +:anl CY,EBitAddr is opfull=0xa5; CY & ophi=8 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr {tmp:1 = EBitByteAddr; $(CY)=$(CY)& ((tmp>>sfrbit)&1); resultflags(tmp); } +:anl CY,EBitAddr2 is opfull=0xa5; CY & ophi=11 & oplo=0; EBitAddr2 & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr {tmp:1 = EBitByteAddr; $(CY)=$(CY)& (~((tmp>>sfrbit)&1)); } +@if BIT_OPS == "BIT_ADDRS" +:anl CY,EBitAddr is opfull=0xa5; CY & ophi=8 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)& EBitAddr; } +:anl CY,EBitAddr2 is opfull=0xa5; CY & ophi=11 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)& ~EBitAddr2; } +@elif BIT_OPS == "PCODEOPS" +:anl CY,EBitAddr is opfull=0xa5; CY & ophi=8 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)& get(EBitAddr, EBitByteAddr); } +:anl CY,EBitAddr2 is opfull=0xa5; CY & ophi=11 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)& (get(EBitAddr2, EBitByteAddr)^1); } +@elif BIT_OPS == "SHIFTS" +:anl CY,EBitAddr is opfull=0xa5; CY & ophi=8 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)& ((EBitByteAddr>>sfrbit)&1); } +:anl CY,EBitAddr2 is opfull=0xa5; CY & ophi=11 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)& (~((EBitByteAddr>>sfrbit)&1)); } +@endif + +:clr EBitAddr is opfull=0xa5; ophi=12 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr { tmp:1 = ~(1<>sfrbit)&1) == 1:1) goto Rel8; } +:jbc EBitAddr,Rel8 is opfull=0xa5; ophi=1 & oplo=0; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr; Rel8 { tmp:1 = 1<>sfrbit)&1) == 1:1) goto Rel8; } +:jbc EBitAddr,Rel8 is opfull=0xa5; ophi=1 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { tmp:1 = 1<>sfrbit)&1)==0:1) goto Rel8; } +@if BIT_OPS == "BIT_ADDRS" +:jnb EBitAddr,Rel8 is opfull=0xa5; ophi=3 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { if (EBitAddr == 0:1) goto Rel8; } +@elif BIT_OPS == "PCODEOPS" +:jnb EBitAddr,Rel8 is opfull=0xa5; ophi=3 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { if (get(EBitAddr, EBitByteAddr)==0:1) goto Rel8; } +@elif BIT_OPS == "SHIFTS" +:jnb EBitAddr,Rel8 is opfull=0xa5; ophi=3 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { if (((EBitByteAddr>>sfrbit)&1)==0:1) goto Rel8; } +@endif + +:mov CY,EBitAddr is opfull=0xa5; CY & ophi=10 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr {$(CY)= (EBitByteAddr>>sfrbit)&1; } +:mov EBitAddr,CY is opfull=0xa5; CY & ophi=9 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr { EBitByteAddr = EBitByteAddr & (~(1<>sfrbit)&1; } +:mov EBitAddr,CY is opfull=0xa5; CY & ophi=9 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { EBitByteAddr = EBitByteAddr & (~(1<>sfrbit)&1); } +:orl CY,EBitAddr2 is opfull=0xa5; CY & ophi=10 & oplo=0; EBitAddr2 & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr {$(CY)=$(CY)| (((EBitByteAddr>>sfrbit)&1)^1); } +@if BIT_OPS == "BIT_ADDRS" +:orl CY,EBitAddr is opfull=0xa5; CY & ophi=7 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)| EBitAddr; } +:orl CY,EBitAddr2 is opfull=0xa5; CY & ophi=10 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)| (EBitAddr2^1); } +@elif BIT_OPS == "PCODEOPS" +:orl CY,EBitAddr is opfull=0xa5; CY & ophi=7 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)| get(EBitAddr, EBitByteAddr); } +:orl CY,EBitAddr2 is opfull=0xa5; CY & ophi=10 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)| (get(EBitAddr2, EBitByteAddr)^1); } +@elif BIT_OPS == "SHIFTS" +:orl CY,EBitAddr is opfull=0xa5; CY & ophi=7 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)| ((EBitByteAddr>>sfrbit)&1); } +:orl CY,EBitAddr2 is opfull=0xa5; CY & ophi=10 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)| (((EBitByteAddr>>sfrbit)&1)^1); } +@endif + +:setb EBitAddr is opfull=0xa5; ophi=13 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr { EBitByteAddr = EBitByteAddr | (1< + + + 8051:BE:16:default + 8051 + default + 16 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/old/8051v1.trans b/python/icicle/Ghidra/Processors/8051/data/languages/old/8051v1.trans new file mode 100644 index 0000000..b89b870 --- /dev/null +++ b/python/icicle/Ghidra/Processors/8051/data/languages/old/8051v1.trans @@ -0,0 +1,8 @@ + + + 8051:BE:16:default + 8051:BE:16:default + + + + diff --git a/python/icicle/Ghidra/Processors/8085/data/languages/8085.cspec b/python/icicle/Ghidra/Processors/8085/data/languages/8085.cspec new file mode 100644 index 0000000..cfd08b5 --- /dev/null +++ b/python/icicle/Ghidra/Processors/8085/data/languages/8085.cspec @@ -0,0 +1,28 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/8085/data/languages/8085.ldefs b/python/icicle/Ghidra/Processors/8085/data/languages/8085.ldefs new file mode 100644 index 0000000..85c72dc --- /dev/null +++ b/python/icicle/Ghidra/Processors/8085/data/languages/8085.ldefs @@ -0,0 +1,15 @@ + + + + + Intel 8085 + + + diff --git a/python/icicle/Ghidra/Processors/8085/data/languages/8085.pspec b/python/icicle/Ghidra/Processors/8085/data/languages/8085.pspec new file mode 100644 index 0000000..8e13263 --- /dev/null +++ b/python/icicle/Ghidra/Processors/8085/data/languages/8085.pspec @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/8085/data/languages/8085.slaspec b/python/icicle/Ghidra/Processors/8085/data/languages/8085.slaspec new file mode 100644 index 0000000..e69108a --- /dev/null +++ b/python/icicle/Ghidra/Processors/8085/data/languages/8085.slaspec @@ -0,0 +1,551 @@ +# sleigh specification file for Intel 8085 + +define endian=little; +define alignment=1; + +define space ram type=ram_space size=2 default; +define space io type=ram_space size=1; +define space register type=register_space size=1; + +define register offset=0x00 size=1 [ F A C B E D L H ]; +define register offset=0x00 size=2 [ AF BC DE HL ]; +define register offset=0x10 size=1 [ A_ F_ B_ C_ D_ E_ H_ L_ ]; # Alternate registers +define register offset=0x10 size=2 [ AF_ BC_ DE_ HL_ ]; # Alternate registers +define register offset=0x20 size=2 [ PC SP ]; + +# Flag bits +# CY: Carry +# P: Parity/Overflow +# AC: Half Carry (Auxiliary flag) +# Z: Zero +# S: Sign +define register offset=0x30 size=1 [ S_flag Z_flag AC_flag P_flag CY_flag ]; + +define token opbyte (8) + op0_8 = (0,7) + op6_2 = (6,7) + + dRegPair4_2 = (4,5) + pRegPair4_2 = (4,5) + sRegPair4_2 = (4,5) + qRegPair4_2 = (4,5) + rRegPair4_2 = (4,5) + + reg3_3 = (3,5) + bits3_3 = (3,5) + + bits0_4 = (0,3) + + reg0_3 = (0,2) + bits0_3 = (0,2) +; + +define token data8 (8) + imm8 = (0,7) + sign8 = (7,7) + simm8 = (0,7) signed +; + +define token data16 (16) + imm16 = (0,15) + sign16 = (15,15) + simm16 = (0,15) signed +; + +attach variables [ reg0_3 reg3_3 ] [ B C D E H L _ A ]; + +attach variables [ sRegPair4_2 dRegPair4_2 ] [ BC DE HL SP ]; +attach variables [ qRegPair4_2 ] [ BC DE HL AF ]; + +################################################################ +# Pseudo Instructions +################################################################ + +define pcodeop BCDadjust; +define pcodeop hasEvenParity; +define pcodeop disableMaskableInterrupts; +define pcodeop enableMaskableInterrupts; +define pcodeop readInterruptMask; +define pcodeop setInterruptMask; + +################################################################ +# Macros +################################################################ + +macro setResultFlags(result) { + Z_flag = (result == 0); + S_flag = (result s< 0); +} + +macro setAddCarryFlags(op1,op2) { + CY_flag = (carry(op1,zext(CY_flag)) || carry(op2,op1 + zext(CY_flag))); +# P_flag = (scarry(op1,CY_flag) || scarry(op2,op1 + CY_flag)); +# AC_flag = ?? +} + +macro setAddFlags(op1,op2) { + CY_flag = carry(op1,op2); +# P_flag = scarry(op1,op2); +# AC_flag = ?? +} + +macro setSubtractCarryFlags(op1,op2) { + local notC = ~CY_flag; + CY_flag = ((op1 < sext(notC)) || (op2 < (op1 - sext(notC)))); +} + +macro setSubtractFlags(op1,op2) { + CY_flag = (op1 < op2); +} + +macro push16(val16) { + SP = SP - 2; + *:2 SP = val16; +} + +macro pop16(ret16) { + ret16 = *:2 SP; + SP = SP + 2; +} + +################################################################ + +Mem8: (imm16) is imm16 { export *:1 imm16; } +Mem16: (imm16) is imm16 { export *:2 imm16; } + +Addr16: imm16 is imm16 { export *:1 imm16; } + +RstAddr: loc is bits3_3 [ loc = bits3_3 << 3; ] { export *:1 loc; } + +IOAddr8: (imm8) is imm8 { export *[io]:1 imm8; } + +cc: "NZ" is bits3_3=0x0 { c:1 = (Z_flag == 0); export c; } +cc: "Z" is bits3_3=0x1 { export Z_flag; } +cc: "NC" is bits3_3=0x2 { c:1 = (CY_flag == 0); export c; } +cc: "C" is bits3_3=0x3 { export CY_flag; } +cc: "PO" is bits3_3=0x4 { c:1 = (P_flag == 0); export c; } +cc: "PE" is bits3_3=0x5 { export P_flag; } +cc: "P" is bits3_3=0x6 { c:1 = (S_flag == 0); export c; } +cc: "M" is bits3_3=0x7 { export S_flag; } + +################################################################ + +:MOV reg3_3,reg0_3 is op6_2=0x1 & reg3_3 & reg0_3 { + reg3_3 = reg0_3; +} + +:MVI reg3_3,imm8 is op6_2=0x0 & reg3_3 & bits0_3=0x6; imm8 { + reg3_3 = imm8; +} + +:MOV reg3_3,(HL) is op6_2=0x1 & reg3_3 & bits0_3=0x6 & HL { + ptr:2 = HL; + reg3_3 = *:1 ptr; +} + +:MOV (HL),reg0_3 is op6_2=0x1 & bits3_3=0x6 & reg0_3 & HL { + ptr:2 = HL; + *:1 ptr = reg0_3; +} + +:MVI (HL),imm8 is op0_8=0x36 & HL; imm8 { + ptr:2 = HL; + *:1 ptr = imm8; +} + +:LDAX (BC) is op0_8=0x0a & BC { + ptr:2 = BC; + A = *:1 ptr; +} + +:LDAX (DE) is op0_8=0x1a & DE { + ptr:2 = DE; + A = *:1 ptr; +} + +:LDA Mem8 is op0_8=0x3a; Mem8 { + A = Mem8; +} + +:STAX (BC) is op0_8=0x2 & BC { + ptr:2 = BC; + *:1 ptr = A; +} + +:STAX (DE) is op0_8=0x12 & DE { + ptr:2 = DE; + *:1 ptr = A; +} + +:STA Mem8 is op0_8=0x32; Mem8 { + Mem8 = A; +} + +:LXI dRegPair4_2,imm16 is op6_2=0x0 & dRegPair4_2 & bits0_4=0x1; imm16 { + dRegPair4_2 = imm16; +} + +:LHLD Mem16 is op0_8=0x2a; Mem16 { + HL = Mem16; +} + +:SHLD Mem16 is op0_8=0x22; Mem16 { + Mem16 = HL; +} + +:SPHL is op0_8=0xf9 { + SP = HL; +} + +:PUSH qRegPair4_2 is op6_2=0x3 & qRegPair4_2 & bits0_4=0x5 { + push16(qRegPair4_2); +} + +:POP qRegPair4_2 is op6_2=0x3 & qRegPair4_2 & bits0_4=0x1 { + pop16(qRegPair4_2); +} + +:XCHG is op0_8=0xeb { + tmp:2 = DE; + DE = HL; + HL = tmp; +} + +:XTHL is op0_8=0xe3 { + tmp:2 = *:2 SP; + *:2 SP = HL; + HL = tmp; +} + +:ADD reg0_3 is op6_2=0x2 & bits3_3=0x0 & reg0_3 { + setAddFlags(A,reg0_3); + A = A + reg0_3; + setResultFlags(A); +} + +:ADI imm8 is op0_8=0xc6; imm8 { + setAddFlags(A,imm8); + A = A + imm8; + setResultFlags(A); +} + +:ADD (HL) is op0_8=0x86 & HL { + val:1 = *:1 HL; + setAddFlags(A,val); + A = A + val; + setResultFlags(A); +} + +:ADC reg0_3 is op6_2=0x2 & bits3_3=0x1 & reg0_3 { + setAddCarryFlags(A,reg0_3); + A = A + reg0_3 + CY_flag; + setResultFlags(A); +} + +:ACI imm8 is op0_8=0xce; imm8 { + setAddCarryFlags(A,imm8); + A = A + imm8 + CY_flag; + setResultFlags(A); +} + +:ADC (HL) is op0_8=0x8e & HL { + val:1 = *:1 HL; + setAddCarryFlags(A,val); + A = A + val + CY_flag; + setResultFlags(A); +} + +:SUB reg0_3 is op6_2=0x2 & bits3_3=0x2 & reg0_3 { + setSubtractFlags(A,reg0_3); + A = A - reg0_3; + setResultFlags(A); +} + +:SUI imm8 is op0_8=0xd6; imm8 { + setSubtractFlags(A,imm8); + A = A - imm8; + setResultFlags(A); +} + +:SUB (HL) is op0_8=0x96 & HL { + val:1 = *:1 HL; + setSubtractFlags(A,val); + A = A - val; + setResultFlags(A); +} + +:SBB reg0_3 is op6_2=0x2 & bits3_3=0x3 & reg0_3 { + setSubtractCarryFlags(A,reg0_3); + A = A - reg0_3 - CY_flag; + setResultFlags(A); +} + +:SBI imm8 is op0_8=0xde; imm8 { + setSubtractCarryFlags(A,imm8); + A = A - imm8 - CY_flag; + setResultFlags(A); +} + +:SBB (HL) is op0_8=0x9e & HL { + val:1 = *:1 HL; + setSubtractCarryFlags(A,val); + A = A - val - CY_flag; + setResultFlags(A); +} + +:ANA reg0_3 is op6_2=0x2 & bits3_3=0x4 & reg0_3 { + AC_flag = 1; + CY_flag = 0; + P_flag = 0; + A = A & reg0_3; + setResultFlags(A); +} + +:ANI imm8 is op0_8=0xe6; imm8 { + AC_flag = 1; + CY_flag = 0; + P_flag = 0; + A = A & imm8; + setResultFlags(A); +} + +:ANA (HL) is op0_8=0xa6 & HL { + AC_flag = 1; + CY_flag = 0; + P_flag = 0; + A = A & *:1 HL; + setResultFlags(A); +} + +:ORA reg0_3 is op6_2=0x2 & bits3_3=0x6 & reg0_3 { + AC_flag = 0; + CY_flag = 0; + P_flag = 0; + A = A | reg0_3; + setResultFlags(A); +} + +:ORI imm8 is op0_8=0xf6; imm8 { + AC_flag = 0; + CY_flag = 0; + P_flag = 0; + A = A | imm8; + setResultFlags(A); +} + +:ORA (HL) is op0_8=0xb6 & HL { + AC_flag = 0; + CY_flag = 0; + P_flag = 0; + A = A | *:1 HL; + setResultFlags(A); +} + +:XRA reg0_3 is op6_2=0x2 & bits3_3=0x5 & reg0_3 { + AC_flag = 0; + CY_flag = 0; + P_flag = 0; + A = A ^ reg0_3; + setResultFlags(A); +} + +:XRA (HL) is op0_8=0xae & HL { + AC_flag = 0; + CY_flag = 0; + P_flag = 0; + A = A ^ *:1 HL; + setResultFlags(A); +} + +:XRI imm8 is op0_8=0xee; imm8 { + AC_flag = 0; + CY_flag = 0; + P_flag = 0; + A = A ^ imm8; + setResultFlags(A); +} + +:CMP reg0_3 is op6_2=0x2 & bits3_3=0x7 & reg0_3 { + setSubtractFlags(A,reg0_3); + cmp:1 = A - reg0_3; + setResultFlags(cmp); +} + +:CPI imm8 is op0_8=0xfe; imm8 { + setSubtractFlags(A,imm8); + cmp:1 = A - imm8; + setResultFlags(cmp); +} + +:CMP (HL) is op0_8=0xbe & HL { + val:1 = *:1 HL; + setSubtractFlags(A,val); + cmp:1 = A - val; + setResultFlags(cmp); +} + +:INR reg3_3 is op6_2=0x0 & reg3_3 & bits0_3=0x4 { + P_flag = (reg3_3 == 0x7f); + reg3_3 = reg3_3 + 1; + setResultFlags(reg3_3); +} + +:INR (HL) is op0_8=0x34 & HL { + val:1 = *:1 HL; + P_flag = (val == 0x7f); + val = val + 1; + *:1 HL = val; + setResultFlags(val); +} + +:DCR reg3_3 is op6_2=0x0 & reg3_3 & bits0_3=0x5 { + P_flag = (reg3_3 == 0x80); + reg3_3 = reg3_3 - 1; + setResultFlags(reg3_3); +} + +:DCR (HL) is op0_8=0x35 & HL { + val:1 = *:1 HL; + P_flag = (val == 0x80); + val = val - 1; + *:1 HL = val; + setResultFlags(val); +} + +:DAA is op0_8=0x27 { + A = BCDadjust(A); + setResultFlags(A); + P_flag = hasEvenParity(A); +} + +:CMA is op0_8=0x2f { + A = ~A; +} + +:CMC is op0_8=0x3f { + CY_flag = !CY_flag; +} + +:STC is op0_8=0x37 { + CY_flag = 1; + AC_flag = 0; +} + +:NOP is op0_8=0x0 { +} + +:HALT is op0_8=0x76 { + goto inst_start; +} + +:DI is op0_8=0xf3 { +# IFF1 = 0; +# IFF2 = 0; + disableMaskableInterrupts(); +} + +:EI is op0_8=0xfb { +# IFF1 = 1; +# IFF2 = 1; + enableMaskableInterrupts(); +} + +:RIM is op0_8=0x20 { + A = readInterruptMask(); +} + +:SIM is op0_8=0x30 { + setInterruptMask(A); +} + +:DAD HL,sRegPair4_2 is op6_2=0x0 & sRegPair4_2 & bits0_4=0x9 & HL { + setAddFlags(HL,sRegPair4_2); + HL = HL + sRegPair4_2; +} + +:INX sRegPair4_2 is op6_2=0x0 & sRegPair4_2 & bits0_4=0x3 { + sRegPair4_2 = sRegPair4_2 + 1; +} + +:DCX sRegPair4_2 is op6_2=0x0 & sRegPair4_2 & bits0_4=0xb { + sRegPair4_2 = sRegPair4_2 - 1; +} + +:RLC is op0_8=0x07 { + CY_flag = (A >> 7); + A = (A << 1) | CY_flag; + AC_flag = 0; +} + +:RAL is op0_8=0x17 { + nextC:1 = (A >> 7); + A = (A << 1) | CY_flag; + CY_flag = nextC; + AC_flag = 0; +} + +:RRC is op0_8=0x0f { + CY_flag = (A & 1); + A = (A >> 1) | (CY_flag << 7); + AC_flag = 0; +} + +:RAR is op0_8=0x1f { + nextC:1 = (A & 1); + A = (A >> 1) | (CY_flag << 7); + CY_flag = nextC; + AC_flag = 0; +} + +:JMP Addr16 is op0_8=0xc3; Addr16 { + goto Addr16; +} + +:J^cc Addr16 is op6_2=0x3 & cc & bits0_3=0x2; Addr16 { + if (cc) goto Addr16; +} + +:PCHL is op0_8=0xe9 { + goto [HL]; +} + +:CALL Addr16 is op0_8=0xcd; Addr16 { + tmp:2 = inst_next; + push16(tmp); + call Addr16; +} + +:C^cc Addr16 is op6_2=0x3 & cc & bits0_3=0x4; Addr16 { + if (!cc) goto inst_next; + tmp:2 = inst_next; + push16(tmp); + call Addr16; +} + +:RET is op0_8=0xc9 { + tmp:2 = 0; + pop16(tmp); + return [tmp]; +} + +:R^cc is op6_2=0x3 & cc & bits0_3=0x0 { + if (!cc) goto inst_next; + tmp:2 = 0; + pop16(tmp); + return [tmp]; +} + +:RST RstAddr is op6_2=0x3 & RstAddr & bits0_3=0x7 { + tmp:2 = inst_next; + push16(tmp); + call RstAddr; +} + +:IN IOAddr8 is op0_8=0xdb; IOAddr8 { + A = IOAddr8; +} + +:OUT IOAddr8 is op0_8=0xd3; IOAddr8 { + IOAddr8 = A; +} + diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.cspec b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.cspec new file mode 100644 index 0000000..72c97be --- /dev/null +++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.cspec @@ -0,0 +1,205 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.dwarf b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.dwarf new file mode 100644 index 0000000..c3ba26e --- /dev/null +++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.dwarf @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.ldefs b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.ldefs new file mode 100644 index 0000000..a33d0ca --- /dev/null +++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.ldefs @@ -0,0 +1,64 @@ + + + + Generic ARM64 v8.5-A LE instructions, LE data, missing some 8.5 vector + + + + + + + Generic ARM64 v8.5-A LE instructions, BE data, missing some 8.5 vector + + + + + + Generic ARM64 v8.5-A LE instructions, LE data, ilp32 + + + + + + + Generic ARM64 v8.5-A LE instructions, BE data, ilp32 + + + + + + diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.opinion b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.opinion new file mode 100644 index 0000000..f0f5c99 --- /dev/null +++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.opinion @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.pspec b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.pspec new file mode 100644 index 0000000..47aeecd --- /dev/null +++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.pspec @@ -0,0 +1,101 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.slaspec b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.slaspec new file mode 100644 index 0000000..12cedc1 --- /dev/null +++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.slaspec @@ -0,0 +1,5 @@ + +@define DATA_ENDIAN "little" + +@include "AARCH64instructions.sinc" + diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64BE.slaspec b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64BE.slaspec new file mode 100644 index 0000000..e1f3970 --- /dev/null +++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64BE.slaspec @@ -0,0 +1,5 @@ + +@define DATA_ENDIAN "big" + +@include "AARCH64instructions.sinc" + diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_AMXext.sinc b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_AMXext.sinc new file mode 100644 index 0000000..2082b6f --- /dev/null +++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_AMXext.sinc @@ -0,0 +1,171 @@ +# +# Apple AARCH64 extended matrix instructions +# Contents based on evolving information published on Web +# +# + +define pcodeop __amx_ldx; +define pcodeop __amx_ldy; +define pcodeop __amx_stx; +define pcodeop __amx_sty; +define pcodeop __amx_ldz; +define pcodeop __amx_stz; +define pcodeop __amx_ldzi; +define pcodeop __amx_stzi; +define pcodeop __amx_extrx; +define pcodeop __amx_extry; +define pcodeop __amx_fma64; +define pcodeop __amx_fms64; +define pcodeop __amx_fma32; +define pcodeop __amx_fms32; +define pcodeop __amx_mac16; +define pcodeop __amx_fma16; +define pcodeop __amx_fms16; +define pcodeop __amx_enable; +define pcodeop __amx_disable; +define pcodeop __amx_vecint; +define pcodeop __amx_vecfp; +define pcodeop __amx_matint; +define pcodeop __amx_matfp; +define pcodeop __amx_genlut; + + +with : ImmS_ImmR_TestSet=1 { + +AMXAddr: is Rd_GPR64 { + addr:8 = Rd_GPR64 & 0x00FFFFFFFFFFFFFF; + export addr; +} + +AMXRegOff: is Rd_GPR64 { + registerOff:8 = (Rd_GPR64 >> 56) & 0x1F; + export registerOff; +} + +AMXSize: is Rd_GPR64 { + local size = ((Rd_GPR64 >> 62) & 1); + size = zext(size == 0) * 0x40 | zext(size ==1 ) * 0x80; + export size; +} + +:__amx_ldx Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=0 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64 +{ + __amx_ldx(Rd_GPR64); +} + +:__amx_ldy Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=1 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64 +{ + __amx_ldy(Rd_GPR64); +} + +:__amx_stx Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=2 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64 +{ + __amx_stx(Rd_GPR64); +} + +:__amx_sty Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=3 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64 +{ + __amx_sty(Rd_GPR64); +} + +:__amx_ldz Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=4 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64 +{ + __amx_ldz(Rd_GPR64); +} + +:__amx_stz Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=5 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64 +{ + __amx_stz(Rd_GPR64); +} + +:__amx_ldzi Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=6 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64 +{ + __amx_ldzi(Rd_GPR64); +} + +:__amx_stzi Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=7 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64 +{ + __amx_stzi(Rd_GPR64); +} + +:__amx_extrx Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=8 & Rd_GPR64 +{ + __amx_extrx(Rd_GPR64); +} + +:__amx_extry Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=9 & Rd_GPR64 +{ + __amx_extry(Rd_GPR64); +} + +:__amx_fma64 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=10 & Rd_GPR64 +{ + __amx_fma64(Rd_GPR64); +} + +:__amx_fms64 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=11 & Rd_GPR64 +{ + __amx_fms64(Rd_GPR64); +} + +:__amx_fma32 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=12 & Rd_GPR64 +{ + __amx_fma32(Rd_GPR64); +} + +:__amx_fms32 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=13 & Rd_GPR64 +{ + __amx_fms32(Rd_GPR64); +} + +:__amx_mac16 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=14 & Rd_GPR64 +{ + __amx_mac16(Rd_GPR64); +} + +:__amx_fma16 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=15 & Rd_GPR64 +{ + __amx_fma16(Rd_GPR64); +} + +:__amx_fms16 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=16 & Rd_GPR64 +{ + __amx_fms16(Rd_GPR64); +} + +:__amxdisable is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=17 & b_0004=1 +{ + __amx_disable(); +} + +:__amxenable is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=17 & b_0004=0 +{ + __amx_enable(); +} + +:__amx_vecint Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=18 & Rd_GPR64 +{ + __amx_vecint(Rd_GPR64); +} + +:__amx_vecfp Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=19 & Rd_GPR64 +{ + __amx_vecfp(Rd_GPR64); +} + +:__amx_matint Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=20 & Rd_GPR64 +{ + __amx_matint(Rd_GPR64); +} + +:__amx_matfp Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=21 & Rd_GPR64 +{ + __amx_matfp(Rd_GPR64); +} + +:__amx_genlut Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=22 & Rd_GPR64 +{ + __amx_genlut(Rd_GPR64); +} + +} \ No newline at end of file diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_AppleSilicon.slaspec b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_AppleSilicon.slaspec new file mode 100644 index 0000000..f1290bb --- /dev/null +++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_AppleSilicon.slaspec @@ -0,0 +1,6 @@ + +@define DATA_ENDIAN "little" + +@include "AARCH64instructions.sinc" +@include "AARCH64_AMXext.sinc" + diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_base_PACoptions.sinc b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_base_PACoptions.sinc new file mode 100644 index 0000000..fcefee0 --- /dev/null +++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_base_PACoptions.sinc @@ -0,0 +1,164 @@ +autda__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = AuthDA(Rd_GPR64, Rn_GPR64xsp); } +autda__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { AuthDA(Rd_GPR64, Rn_GPR64xsp); } +autda__PACpart: "hide" is ShowPAC=0 { } + +autdza__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = AuthDA(Rd_GPR64, xzr); } +autdza__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { AuthDA(Rd_GPR64, xzr); } +autdza__PACpart: "hide" is ShowPAC=0 { } + +autdb__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = AuthDB(Rd_GPR64, Rn_GPR64xsp); } +autdb__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { AuthDB(Rd_GPR64, Rn_GPR64xsp); } +autdb__PACpart: "hide" is ShowPAC=0 { } + +autdzb__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = AuthDB(Rd_GPR64, xzr); } +autdzb__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { AuthDB(Rd_GPR64, xzr); } +autdzb__PACpart: "hide" is ShowPAC=0 { } + +autia__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = AuthIA(Rd_GPR64, Rn_GPR64xsp); } +autia__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { AuthIA(Rd_GPR64, Rn_GPR64xsp); } +autia__PACpart: "hide" is ShowPAC=0 { } + +autiza__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = AuthIA(Rd_GPR64, xzr); } +autiza__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { AuthIA(Rd_GPR64, xzr); } +autiza__PACpart: "hide" is ShowPAC=0 { } + +autia1716__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x17 = AuthIA(x17, x16); } +autia1716__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIA(x17, x16); } +autia1716__PACpart: "hide" is ShowPAC=0 { } + +autiasp__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = AuthIA(x30, sp); } +autiasp__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIA(x30, sp); } +autiasp__PACpart: "hide" is ShowPAC=0 { } + +autiaz__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = AuthIA(x30, xzr); } +autiaz__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIA(x30, xzr); } +autiaz__PACpart: "hide" is ShowPAC=0 { } + +autib__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = AuthIB(Rd_GPR64, Rn_GPR64xsp); } +autib__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { AuthIB(Rd_GPR64, Rn_GPR64xsp); } +autib__PACpart: "hide" is ShowPAC=0 { } + +autizb__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = AuthIB(Rd_GPR64, xzr); } +autizb__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { AuthIB(Rd_GPR64, xzr); } +autizb__PACpart: "hide" is ShowPAC=0 { } + +autib1716__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x17 = AuthIB(x17, x16); } +autib1716__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIB(x17, x16); } +autib1716__PACpart: "hide" is ShowPAC=0 { } + +autibsp__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = AuthIB(x30, sp); } +autibsp__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIB(x30, sp); } +autibsp__PACpart: "hide" is ShowPAC=0 { } + +autibz__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = AuthIB(x30, xzr); } +autibz__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIB(x30, xzr); } +autibz__PACpart: "hide" is ShowPAC=0 { } + +b_blinkop__raaz___PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64 { AuthIA(Rn_GPR64, xzr); } +b_blinkop__raaz___PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64 { AuthIA(Rn_GPR64, xzr); } +b_blinkop__raaz___PACpart: "hide" is ShowPAC=0 { } + +b_blinkop__raa___PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64xsp & Rn_GPR64 { AuthIA(Rn_GPR64, Rd_GPR64xsp); } +b_blinkop__raa___PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64xsp & Rn_GPR64 { AuthIA(Rn_GPR64, Rd_GPR64xsp); } +b_blinkop__raa___PACpart: "hide" is ShowPAC=0 { } + +b_blinkop__rabz___PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64 { AuthIB(Rn_GPR64, xzr); } +b_blinkop__rabz___PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64 { AuthIB(Rn_GPR64, xzr); } +b_blinkop__rabz___PACpart: "hide" is ShowPAC=0 { } + +b_blinkop__rab___PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64xsp & Rn_GPR64 { AuthIB(Rn_GPR64, Rd_GPR64xsp); } +b_blinkop__rab___PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64xsp & Rn_GPR64 { AuthIB(Rn_GPR64, Rd_GPR64xsp); } +b_blinkop__rab___PACpart: "hide" is ShowPAC=0 { } + +eretaa__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { AuthIA(pc, sp); } +eretaa__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIA(pc, sp); } +eretaa__PACpart: "hide" is ShowPAC=0 { } + +eretab__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { AuthIB(pc, sp); } +eretab__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIB(pc, sp); } +eretab__PACpart: "hide" is ShowPAC=0 { } + +ldraa__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp { AuthDA(Rn_GPR64xsp, xzr); } +ldraa__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp { AuthDA(Rn_GPR64xsp, xzr); } +ldraa__PACpart: "hide" is ShowPAC=0 { } + +ldrab__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp { AuthDB(Rn_GPR64xsp, xzr); } +ldrab__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp { AuthDB(Rn_GPR64xsp, xzr); } +ldrab__PACpart: "hide" is ShowPAC=0 { } + +pacda__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = pacda(Rd_GPR64, Rn_GPR64xsp); } +pacda__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { pacda(Rd_GPR64, Rn_GPR64xsp); } +pacda__PACpart: "hide" is ShowPAC=0 { } + +pacdza__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = pacdza(Rd_GPR64); } +pacdza__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { pacdza(Rd_GPR64); } +pacdza__PACpart: "hide" is ShowPAC=0 { } + +pacdb__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = pacdb(Rd_GPR64, Rn_GPR64xsp); } +pacdb__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { pacdb(Rd_GPR64, Rn_GPR64xsp); } +pacdb__PACpart: "hide" is ShowPAC=0 { } + +pacdzb__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = pacdzb(Rd_GPR64); } +pacdzb__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { pacdzb(Rd_GPR64); } +pacdzb__PACpart: "hide" is ShowPAC=0 { } + +pacia__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = pacia(Rd_GPR64, Rn_GPR64xsp); } +pacia__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { pacia(Rd_GPR64, Rn_GPR64xsp); } +pacia__PACpart: "hide" is ShowPAC=0 { } + +paciza__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = paciza(Rd_GPR64); } +paciza__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { paciza(Rd_GPR64); } +paciza__PACpart: "hide" is ShowPAC=0 { } + +pacia1716__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x17 = pacia(x17, x16); } +pacia1716__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { pacia(x17, x16); } +pacia1716__PACpart: "hide" is ShowPAC=0 { } + +paciasp__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = pacia(x30, sp); } +paciasp__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { pacia(x30, sp); } +paciasp__PACpart: "hide" is ShowPAC=0 { } + +paciaz__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = paciza(x30); } +paciaz__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { paciza(x30); } +paciaz__PACpart: "hide" is ShowPAC=0 { } + +pacib__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = pacib(Rd_GPR64, Rn_GPR64xsp); } +pacib__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { pacib(Rd_GPR64, Rn_GPR64xsp); } +pacib__PACpart: "hide" is ShowPAC=0 { } + +pacizb__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = pacizb(Rd_GPR64); } +pacizb__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { pacizb(Rd_GPR64); } +pacizb__PACpart: "hide" is ShowPAC=0 { } + +pacib1716__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x17 = pacib(x17, x16); } +pacib1716__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { pacib(x17, x16); } +pacib1716__PACpart: "hide" is ShowPAC=0 { } + +pacibsp__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = pacib(x30, sp); } +pacibsp__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { pacib(x30, sp); } +pacibsp__PACpart: "hide" is ShowPAC=0 { } + +pacibz__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = pacizb(x30); } +pacibz__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { pacizb(x30); } +pacibz__PACpart: "hide" is ShowPAC=0 { } + +retaa__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { AuthIA(x30, sp); } +retaa__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIA(x30, sp); } +retaa__PACpart: "hide" is ShowPAC=0 { } + +retab__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { AuthIB(x30, sp); } +retab__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIB(x30, sp); } +retab__PACpart: "hide" is ShowPAC=0 { } + +xpacd__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = xpac(Rd_GPR64, 1:1); } +xpacd__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { xpac(Rd_GPR64, 1:1); } +xpacd__PACpart: "hide" is ShowPAC=0 { } + +xpaci__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = xpac(Rd_GPR64, 0:1); } +xpaci__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { xpac(Rd_GPR64, 0:1); } +xpaci__PACpart: "hide" is ShowPAC=0 { } + +xpaclri__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = xpac(x30, 0:1); } +xpaclri__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { xpac(x30, 0:1); } +xpaclri__PACpart: "hide" is ShowPAC=0 { } + diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_ilp32.cspec b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_ilp32.cspec new file mode 100644 index 0000000..4629571 --- /dev/null +++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_ilp32.cspec @@ -0,0 +1,207 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_win.cspec b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_win.cspec new file mode 100644 index 0000000..8e02453 --- /dev/null +++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_win.cspec @@ -0,0 +1,214 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc new file mode 100644 index 0000000..194b37a --- /dev/null +++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc @@ -0,0 +1,8392 @@ +# C6.2.1 ADC page C6-1144 line 67905 MATCH x1a000000/mask=x7fe0fc00 +# C6.2.2 ADCS page C6-1146 line 67991 MATCH x3a000000/mask=x7fe0fc00 +# CONSTRUCT x1a000000/mask=xdfe0fc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x1a000000/mask=xdfe0fc00 --status pass --comment "flags" + +:adc^SBIT_CZNO Rd_GPR32, Rn_GPR32, Rm_GPR32 +is sf=0 & b_30=0 & S & SBIT_CZNO & b_2428=0x1a & b_2123=0 & Rm_GPR32 & b_1015=0 & Rd_GPR32 & Rd_GPR64 & Rn_GPR32 +{ + add_with_carry_flags(Rn_GPR32, Rm_GPR32); + tmp:4 = Rm_GPR32 + Rn_GPR32 + zext(CY); + Rd_GPR64 = zext(tmp); + resultflags(tmp); + build SBIT_CZNO; +} + +# C6.2.1 ADC page C6-1144 line 67905 MATCH x1a000000/mask=x7fe0fc00 +# C6.2.2 ADCS page C6-1146 line 67991 MATCH x3a000000/mask=x7fe0fc00 +# CONSTRUCT x9a000000/mask=xdfe0fc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x9a000000/mask=xdfe0fc00 --status pass --comment "flags" + +:adc^SBIT_CZNO Rd_GPR64, Rn_GPR64, Rm_GPR64 +is sf=1 & b_30=0 & S & SBIT_CZNO & b_2428=0x1a & b_2123=0 & Rm_GPR64 & b_1015=0 & Rd_GPR64 & Rn_GPR64 +{ + add_with_carry_flags(Rn_GPR64, Rm_GPR64); + Rd_GPR64 = Rn_GPR64 + Rm_GPR64 + zext(CY); + resultflags(Rd_GPR64); + build SBIT_CZNO; +} + +# C6.2.3 ADD (extended register) page C6-1148 line 68081 MATCH x0b200000/mask=x7fe00000 +# C6.2.7 ADDS (extended register) page C6-1156 line 68516 MATCH x2b200000/mask=x7fe00000 +# C6.2.59 CMN (extended register) page C6-1246 line 73092 MATCH x2b20001f/mask=x7fe0001f +# CONSTRUCT x0b200000/mask=xdfe00000 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst x0b200000/mask=xdfe00000 --status pass --comment "flags" + +:add^SBIT_CZNO Rd_GPR32wsp, Rn_GPR32wsp, ExtendRegShift32 +is sf=0 & op=0 & S & SBIT_CZNO & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift32 & Rn_GPR32wsp & Rd_GPR32wsp & Rd_GPR64xsp +{ + tmp_2:4 = ExtendRegShift32; + addflags(Rn_GPR32wsp, tmp_2); + tmp_1:4 = Rn_GPR32wsp + tmp_2; + resultflags(tmp_1); + Rd_GPR64xsp = zext(tmp_1); + build SBIT_CZNO; +} + +# C6.2.3 ADD (extended register) page C6-1148 line 68081 MATCH x0b200000/mask=x7fe00000 +# C6.2.7 ADDS (extended register) page C6-1156 line 68516 MATCH x2b200000/mask=x7fe00000 +# C6.2.59 CMN (extended register) page C6-1246 line 73092 MATCH x2b20001f/mask=x7fe0001f +# CONSTRUCT x8b200000/mask=xdfe00000 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst x8b200000/mask=xdfe00000 --status pass --comment "flags" + +:add^SBIT_CZNO Rd_GPR64xsp, Rn_GPR64xsp, ExtendRegShift64 +is sf=1 & op=0 & S & SBIT_CZNO & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift64 & Rn_GPR64xsp & Rd_GPR64xsp +{ + tmp_2:8 = ExtendRegShift64; + addflags(Rn_GPR64xsp, tmp_2); + tmp_1:8 = Rn_GPR64xsp + tmp_2; + resultflags(tmp_1); + Rd_GPR64xsp = tmp_1; + build SBIT_CZNO; +} + +# C6.2.4 ADD (immediate) page C6-1151 line 68228 MATCH x11000000/mask=x7f800000 +# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000 +# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f +# C6.2.220 MOV (to/from SP) page C6-1668 line 98876 MATCH x11000000/mask=x7ffffc00 +# CONSTRUCT x11000000/mask=xdf000000 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst x11000000/mask=xdf000000 --status pass --comment "flags" + +:add^SBIT_CZNO Rd_GPR32xsp, Rn_GPR32xsp, ImmShift32 +is sf=0 & b_30=0 & S & SBIT_CZNO & b_2428=0x011 & ImmShift32 & Rn_GPR32xsp & Rd_GPR32xsp & Rd_GPR64xsp +{ + addflags(Rn_GPR32xsp, ImmShift32); + tmp:4 = Rn_GPR32xsp + ImmShift32; + resultflags(tmp); + build SBIT_CZNO; + Rd_GPR64xsp = zext(tmp); +} + +# C6.2.4 ADD (immediate) page C6-1151 line 68228 MATCH x11000000/mask=x7f800000 +# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000 +# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f +# C6.2.220 MOV (to/from SP) page C6-1668 line 98876 MATCH x11000000/mask=x7ffffc00 +# CONSTRUCT x91000000/mask=xdf000000 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst x91000000/mask=xdf000000 --status pass --comment "flags" + +:add^SBIT_CZNO Rd_GPR64xsp, Rn_GPR64xsp, ImmShift64 +is sf=1 & b_30=0 & S & SBIT_CZNO & b_2428=0x11 & ImmShift64 & Rn_GPR64xsp & Rd_GPR64xsp +{ + addflags(Rn_GPR64xsp, ImmShift64); + Rd_GPR64xsp = Rn_GPR64xsp + ImmShift64; + resultflags(Rd_GPR64xsp); + build SBIT_CZNO; +} + +# C6.2.4 ADD (immediate) page C6-1151 line 68228 MATCH x11000000/mask=x7f800000 +# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000 +# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f +# C6.2.220 MOV (to/from SP) page C6-1668 line 98876 MATCH x11000000/mask=x7ffffc00 +# CONSTRUCT x11000000/mask=xdfc00000 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst x11000000/mask=xdfc00000 --status pass --comment "flags" + +:add^SBIT_CZNO Rd_GPR32wsp, Rn_GPR32wsp, Imm12_addsubimm_operand_i32_posimm_lsl0 +is sf=0 & op=0 & S & SBIT_CZNO & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i32_posimm_lsl0 & Rn_GPR32wsp & Rd_GPR32wsp & Rd_GPR64xsp +{ + tmp_2:4 = Imm12_addsubimm_operand_i32_posimm_lsl0; + addflags(Rn_GPR32wsp, tmp_2); + tmp_1:4 = Rn_GPR32wsp + tmp_2; + resultflags(tmp_1); + Rd_GPR64xsp = zext(tmp_1); + build SBIT_CZNO; +} + +# C6.2.4 ADD (immediate) page C6-1151 line 68228 MATCH x11000000/mask=x7f800000 +# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000 +# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f +# CONSTRUCT x11400000/mask=xdfc00000 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst x11400000/mask=xdfc00000 --status pass --comment "flags" + +:add^SBIT_CZNO Rd_GPR32wsp, Rn_GPR32wsp, Imm12_addsubimm_operand_i32_posimm_lsl12 +is sf=0 & op=0 & S & SBIT_CZNO & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i32_posimm_lsl12 & Rn_GPR32wsp & Rd_GPR32wsp & Rd_GPR64xsp +{ + tmp_2:4 = Imm12_addsubimm_operand_i32_posimm_lsl12; + addflags(Rn_GPR32wsp, tmp_2); + tmp_1:4 = Rn_GPR32wsp + tmp_2; + resultflags(tmp_1); + Rd_GPR64xsp = zext(tmp_1); + build SBIT_CZNO; +} + +# C6.2.4 ADD (immediate) page C6-1151 line 68228 MATCH x11000000/mask=x7f800000 +# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000 +# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f +# C6.2.220 MOV (to/from SP) page C6-1668 line 98876 MATCH x11000000/mask=x7ffffc00 +# CONSTRUCT x91000000/mask=xdfc00000 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst x91000000/mask=xdfc00000 --status pass --comment "flags" + +:add^SBIT_CZNO Rd_GPR64xsp, Rn_GPR64xsp, Imm12_addsubimm_operand_i64_posimm_lsl0 +is sf=1 & op=0 & S & SBIT_CZNO & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i64_posimm_lsl0 & Rn_GPR64xsp & Rd_GPR64xsp +{ + tmp_2:8 = Imm12_addsubimm_operand_i64_posimm_lsl0; + addflags(Rn_GPR64xsp, tmp_2); + tmp_1:8 = Rn_GPR64xsp + tmp_2; + resultflags(tmp_1); + Rd_GPR64xsp = tmp_1; + build SBIT_CZNO; +} + +# C6.2.4 ADD (immediate) page C6-1151 line 68228 MATCH x11000000/mask=x7f800000 +# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000 +# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f +# CONSTRUCT x91400000/mask=xdfc00000 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst x91400000/mask=xdfc00000 --status pass --comment "flags" + +:add^SBIT_CZNO Rd_GPR64xsp, Rn_GPR64xsp, Imm12_addsubimm_operand_i64_posimm_lsl12 +is sf=1 & op=0 & S & SBIT_CZNO & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i64_posimm_lsl12 & Rn_GPR64xsp & Rd_GPR64xsp +{ + tmp_2:8 = Imm12_addsubimm_operand_i64_posimm_lsl12; + addflags(Rn_GPR64xsp, tmp_2); + tmp_1:8 = Rn_GPR64xsp + tmp_2; + resultflags(tmp_1); + Rd_GPR64xsp = tmp_1; + build SBIT_CZNO; +} + +# C6.2.5 ADD (shifted register) page C6-1153 line 68340 MATCH x0b000000/mask=x7f200000 +# C6.2.9 ADDS (shifted register) page C6-1161 line 68775 MATCH x2b000000/mask=x7f200000 +# C6.2.61 CMN (shifted register) page C6-1250 line 73309 MATCH x2b00001f/mask=x7f20001f +# CONSTRUCT x0b000000/mask=xdf208000 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst x0b000000/mask=xdf208000 --status pass --comment "flags" +# if shift == '11' then ReservedValue(); + +:add^SBIT_CZNO Rd_GPR32, Rn_GPR32, RegShift32 +is sf=0 & op=0 & S & SBIT_CZNO & b_2428=0xb & b_2121=0 & b_15=0 & RegShift32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp_2:4 = RegShift32; + addflags(Rn_GPR32, tmp_2); + tmp_1:4 = Rn_GPR32 + tmp_2; + resultflags(tmp_1); + Rd_GPR64 = zext(tmp_1); + build SBIT_CZNO; +} + +# C6.2.5 ADD (shifted register) page C6-1153 line 68340 MATCH x0b000000/mask=x7f200000 +# C6.2.9 ADDS (shifted register) page C6-1161 line 68775 MATCH x2b000000/mask=x7f200000 +# C6.2.61 CMN (shifted register) page C6-1250 line 73309 MATCH x2b00001f/mask=x7f20001f +# CONSTRUCT x8b000000/mask=xdf200000 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst x8b000000/mask=xdf200000 --status pass --comment "flags" + +:add^SBIT_CZNO Rd_GPR64, Rn_GPR64, RegShift64 +is sf=1 & op=0 & S & SBIT_CZNO & b_2428=0xb & b_2121=0 & RegShift64 & Rn_GPR64 & Rd_GPR64 +{ + tmp_2:8 = RegShift64; + addflags(Rn_GPR64, tmp_2); + tmp_1:8 = Rn_GPR64 + tmp_2; + resultflags(tmp_1); + Rd_GPR64 = tmp_1; + build SBIT_CZNO; +} + +# C6.2.10 ADR page C6-1163 line 68896 MATCH x10000000/mask=x9f000000 +# CONSTRUCT x10000000/mask=x9f000000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x10000000/mask=x9f000000 --status nodest --comment "qemuerr(illegal addresses cause qemu exit)" + +:adr Rd_GPR64, AdrReloff +is b_31=0 & AdrReloff & b_2428=0x10 & Rd_GPR64 +{ + Rd_GPR64 = &AdrReloff; +} + +# C6.2.11 ADRP page C6-1164 line 68943 MATCH x90000000/mask=x9f000000 +# CONSTRUCT x90000000/mask=x9f000000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x90000000/mask=x9f000000 --status nodest --comment "qemuerr(illegal addresses cause qemu exit)" + +:adrp Rd_GPR64, AdrReloff +is b_31=1 & AdrReloff & b_2428=0x10 & Rd_GPR64 +{ + Rd_GPR64 = &AdrReloff; +} + +# C6.2.12 AND (immediate) page C6-1165 line 68992 MATCH x12000000/mask=x7f800000 +# CONSTRUCT x12000000/mask=xff800000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x12000000/mask=xff800000 --status pass + +:and Rd_GPR32wsp, Rn_GPR32, DecodeWMask32 +is sf=0 & opc=0 & b_2428=0x12 & b_2323=0 & DecodeWMask32 & Rn_GPR32 & Rd_GPR32wsp & Rd_GPR64xsp +{ + tmp_1:4 = Rn_GPR32 & DecodeWMask32; + Rd_GPR64xsp = zext(tmp_1); +} + +# C6.2.12 AND (immediate) page C6-1165 line 68992 MATCH x12000000/mask=x7f800000 +# CONSTRUCT x92000000/mask=xff800000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x92000000/mask=xff800000 --status pass + +:and Rd_GPR64xsp, Rn_GPR64, DecodeWMask64 +is sf=1 & opc=0 & b_2428=0x12 & b_2323=0 & DecodeWMask64 & Rn_GPR64 & Rd_GPR64xsp +{ + tmp_1:8 = Rn_GPR64 & DecodeWMask64; + Rd_GPR64xsp = tmp_1; +} + +# C6.2.13 AND (shifted register) page C6-1167 line 69083 MATCH x0a000000/mask=x7f200000 +# CONSTRUCT x0a000000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x0a000000/mask=xff200000 --status pass + +:and Rd_GPR32, Rn_GPR32, RegShift32Log +is sf=0 & opc=0 & b_2428=0xa & N=0 & RegShift32Log & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp_2:4 = RegShift32Log; + tmp_1:4 = Rn_GPR32 & tmp_2; + Rd_GPR64 = zext(tmp_1); +} + +# C6.2.13 AND (shifted register) page C6-1167 line 69083 MATCH x0a000000/mask=x7f200000 +# CONSTRUCT x8a000000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x8a000000/mask=xff200000 --status pass + +:and Rd_GPR64, Rn_GPR64, RegShift64Log +is sf=1 & opc=0 & b_2428=0xa & N=0 & RegShift64Log & Rn_GPR64 & Rd_GPR64 +{ + tmp_2:8 = RegShift64Log; + tmp_1:8 = Rn_GPR64 & tmp_2; + Rd_GPR64 = tmp_1; +} + +# C6.2.14 ANDS (immediate) page C6-1169 line 69185 MATCH x72000000/mask=x7f800000 +# C6.2.382 TST (immediate) page C6-1983 line 116255 MATCH x7200001f/mask=x7f80001f +# CONSTRUCT x72000000/mask=xff800000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x72000000/mask=xff800000 --status pass --comment "flags" + +:ands Rd_GPR32, Rn_GPR32, DecodeWMask32 +is sf=0 & opc=3 & b_2428=0x12 & b_2323=0 & DecodeWMask32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp_1:4 = Rn_GPR32 & DecodeWMask32; + resultflags(tmp_1); + Rd_GPR64 = zext(tmp_1); + affectLflags(); +} + +# C6.2.14 ANDS (immediate) page C6-1169 line 69185 MATCH x72000000/mask=x7f800000 +# C6.2.382 TST (immediate) page C6-1983 line 116255 MATCH x7200001f/mask=x7f80001f +# CONSTRUCT xf2000000/mask=xff800000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xf2000000/mask=xff800000 --status pass --comment "flags" + +:ands Rd_GPR64, Rn_GPR64, DecodeWMask64 +is sf=1 & opc=3 & b_2428=0x12 & b_2323=0 & DecodeWMask64 & Rn_GPR64 & Rd_GPR64 +{ + tmp_1:8 = Rn_GPR64 & DecodeWMask64; + resultflags(tmp_1); + Rd_GPR64 = tmp_1; + affectLflags(); +} + +# C6.2.15 ANDS (shifted register) page C6-1171 line 69286 MATCH x6a000000/mask=x7f200000 +# C6.2.383 TST (shifted register) page C6-1984 line 116319 MATCH x6a00001f/mask=x7f20001f +# CONSTRUCT x6a000000/mask=xff200000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x6a000000/mask=xff200000 --status pass --comment "flags" + +:ands Rd_GPR32, Rn_GPR32, RegShift32Log +is sf=0 & opc=3 & b_2428=0xa & N=0 & RegShift32Log & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp_2:4 = RegShift32Log; + tmp_1:4 = Rn_GPR32 & tmp_2; + resultflags(tmp_1); + Rd_GPR64 = zext(tmp_1); + affectLflags(); +} + +# C6.2.15 ANDS (shifted register) page C6-1171 line 69286 MATCH x6a000000/mask=x7f200000 +# C6.2.383 TST (shifted register) page C6-1984 line 116319 MATCH x6a00001f/mask=x7f20001f +# CONSTRUCT xea000000/mask=xff200000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xea000000/mask=xff200000 --status pass --comment "flags" + +:ands Rd_GPR64, Rn_GPR64, RegShift64Log +is sf=1 & opc=3 & b_2428=0xa & N=0 & RegShift64Log & Rn_GPR64 & Rd_GPR64 +{ + tmp_2:8 = RegShift64Log; + tmp_1:8 = Rn_GPR64 & tmp_2; + resultflags(tmp_1); + Rd_GPR64 = tmp_1; + affectLflags(); +} + +# C6.2.16 ASR (register) page C6-1173 line 69404 MATCH x1ac02800/mask=x7fe0fc00 +# C6.2.18 ASRV page C6-1177 line 69588 MATCH x1ac02800/mask=x7fe0fc00 +# CONSTRUCT x1ac02800/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x1ac02800/mask=xffe0fc00 --status pass + +:asr Rd_GPR32, Rn_GPR32, Rm_GPR32 +is sf=0 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR32 & b_1015=0xa & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp_2:4 = Rm_GPR32 & 0x1f; + tmp_1:4 = Rn_GPR32 s>> tmp_2; + Rd_GPR64 = zext(tmp_1); +} + +# C6.2.16 ASR (register) page C6-1173 line 69404 MATCH x1ac02800/mask=x7fe0fc00 +# C6.2.18 ASRV page C6-1177 line 69588 MATCH x1ac02800/mask=x7fe0fc00 +# CONSTRUCT x9ac02800/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x9ac02800/mask=xffe0fc00 --status pass + +:asr Rd_GPR64, Rn_GPR64, Rm_GPR64 +is sf=1 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR64 & b_1015=0xa & Rn_GPR64 & Rd_GPR64 +{ + tmp_2:8 = Rm_GPR64 & 0x3f; + tmp_1:8 = Rn_GPR64 s>> tmp_2; + Rd_GPR64 = tmp_1; +} + +# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00 +# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000 +# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000 +# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000 +# CONSTRUCT x13007c00/mask=xffe0fc02 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst x13007c00/mask=xffe0fc02 --status pass +# Alias for sbfm when imms == '011111' +# imms is MAX_INT5, so it will never be less than immr. Note that immr is limited to [0,31] +# Ha! Two explicit cases passes -l +# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue(); + +:asr Rd_GPR32, Rn_GPR32, ImmRConst32 +is ImmS=0x1f & ImmS_LT_ImmR=0 & (ImmS_EQ_ImmR=0 | ImmS_EQ_ImmR=1) & sf=0 & opc=0 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp_2:4 = ImmRConst32; + tmp_1:4 = Rn_GPR32 s>> tmp_2; + Rd_GPR64 = zext(tmp_1); +} + +# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00 +# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000 +# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000 +# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000 +# CONSTRUCT x9340fc00/mask=xffc0fc02 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst x9340fc00/mask=xffc0fc02 --status pass +# Alias for sbfm when imms == '111111' +# imms is MAX_INT6, so it will never be less than immr (6-bit field) +# Ha! Two explicit cases passes -l + +:asr Rd_GPR64, Rn_GPR64, ImmRConst64 +is ImmS=0x3f & ImmS_LT_ImmR=0 & (ImmS_EQ_ImmR=0 | ImmS_EQ_ImmR=1) & sf=1 & opc=0 & b_2428=0x13 & b_2323=0 & n=1 & ImmRConst64 & Rn_GPR64 & Rd_GPR64 +{ + tmp_2:8 = ImmRConst64; + tmp_1:8 = Rn_GPR64 s>> tmp_2; + Rd_GPR64 = tmp_1; +} + +# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00 +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5087800/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst xd5087800/mask=xffffffe0 --status noqemu + +:at "S1E1R", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b000 & Rt_GPR64 +{ par_el1 = AT_S1E1R(Rt_GPR64); } + +# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00 +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50c7800/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst xd50c7800/mask=xffffffe0 --status noqemu + +:at "S1E2R", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b000 & Rt_GPR64 +{ par_el1 = AT_S1E2R(Rt_GPR64); } + +# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00 +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50e7800/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst xd50e7800/mask=xffffffe0 --status noqemu + +:at "S1E3R", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b110 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b000 & Rt_GPR64 +{ par_el1 = AT_S1E3R(Rt_GPR64); } + +# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00 +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5087820/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst xd5087820/mask=xffffffe0 --status noqemu + +:at "S1E1W", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b001 & Rt_GPR64 +{ par_el1 = AT_S1E1W(Rt_GPR64); } + +# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00 +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50c7820/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst xd50c7820/mask=xffffffe0 --status noqemu + +:at "S1E2W", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b001 & Rt_GPR64 +{ par_el1 = AT_S1E2W(Rt_GPR64); } + +# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00 +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50e7820/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst xd50e7820/mask=xffffffe0 --status noqemu + +:at "S1E3W", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b110 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b001 & Rt_GPR64 +{ par_el1 = AT_S1E3W(Rt_GPR64); } + +# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00 +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5087840/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst xd5087840/mask=xffffffe0 --status noqemu + +:at "S1E0R", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b010 & Rt_GPR64 +{ par_el1 = AT_S1E0R(Rt_GPR64); } + +# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00 +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5087860/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst xd5087860/mask=xffffffe0 --status noqemu + +:at "S1E0W", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b011 & Rt_GPR64 +{ par_el1 = AT_S1E0W(Rt_GPR64); } + +# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00 +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50c7880/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst xd50c7880/mask=xffffffe0 --status noqemu + +:at "S12E1R", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b100 & Rt_GPR64 +{ par_el1 = AT_S12E1R(Rt_GPR64); } + +# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00 +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50c78a0/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst xd50c78a0/mask=xffffffe0 --status noqemu + +:at "S12E1W", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b101 & Rt_GPR64 +{ par_el1 = AT_S12E1W(Rt_GPR64); } + +# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00 +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50c78c0/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst xd50c78c0/mask=xffffffe0 --status noqemu + +:at "S12E0R", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b110 & Rt_GPR64 +{ par_el1 = AT_S12E0R(Rt_GPR64); } + +# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00 +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50c78e0/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst xd50c78e0/mask=xffffffe0 --status noqemu + +:at "S12E0W", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b111 & Rt_GPR64 +{ par_el1 = AT_S12E0W(Rt_GPR64); } + +# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00 +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5087900/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst xd5087900/mask=xffffffe0 --status noqemu + +:at "S1E1RP", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1001 & b_0507=0b000 & Rt_GPR64 +{ par_el1 = AT_S1E1RP(Rt_GPR64); } + +# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00 +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5087920/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst xd5087920/mask=xffffffe0 --status noqemu + +:at "S1E1WP", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1001 & b_0507=0b001 & Rt_GPR64 +{ par_el1 = AT_S1E1WP(Rt_GPR64); } + +# C6.2.20 AUTDA, AUTDZA page C6-1181 line 69758 MATCH xdac11800/mask=xffffdc00 +# CONSTRUCT xdac11800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xdac11800/mask=xfffffc00 --status noqemu + +:autda Rd_GPR64, Rn_GPR64xsp +is autda__PACpart & b_1431=0b110110101100000100 & b_1012=0b110 & b_13=0 & Rn_GPR64xsp & Rd_GPR64 +{ + build autda__PACpart; +} + +# C6.2.20 AUTDA, AUTDZA page C6-1181 line 69758 MATCH xdac11800/mask=xffffdc00 +# CONSTRUCT xdac13be0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xdac13be0/mask=xffffffe0 --status noqemu + +:autdza Rd_GPR64 +is autdza__PACpart & b_1431=0b110110101100000100 & b_1012=0b110 & b_13=1 & b_0509=0b11111 & Rd_GPR64 +{ + build autdza__PACpart; +} + +# C6.2.21 AUTDB, AUTDZB page C6-1182 line 69833 MATCH xdac11c00/mask=xffffdc00 +# CONSTRUCT xdac11c00/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xdac11c00/mask=xfffffc00 --status noqemu + +:autdb Rd_GPR64, Rn_GPR64xsp +is autdb__PACpart & b_1431=0b110110101100000100 & b_1012=0b111 & b_13=0 & Rn_GPR64xsp & Rd_GPR64 +{ + build autdb__PACpart; +} + +# C6.2.21 AUTDB, AUTDZB page C6-1182 line 69833 MATCH xdac11c00/mask=xffffdc00 +# CONSTRUCT xdac13fe0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xdac13fe0/mask=xffffffe0 --status noqemu + +:autdzb Rd_GPR64 +is autdzb__PACpart & b_1431=0b110110101100000100 & b_1012=0b111 & b_13=1 & b_0509=0b11111 & Rd_GPR64 +{ + build autdzb__PACpart; +} + +# C6.2.22 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA page C6-1183 line 69908 MATCH xdac11000/mask=xffffdc00 +# CONSTRUCT xdac11000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xdac11000/mask=xfffffc00 --status noqemu + +:autia Rd_GPR64, Rn_GPR64xsp +is autia__PACpart & b_1431=0b110110101100000100 & b_1012=0b100 & b_13=0 & Rn_GPR64xsp & Rd_GPR64 +{ + build autia__PACpart; +} + +# C6.2.22 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA page C6-1183 line 69908 MATCH xdac11000/mask=xffffdc00 +# CONSTRUCT xdac133e0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xdac133e0/mask=xffffffe0 --status noqemu + +:autiza Rd_GPR64 +is autiza__PACpart & b_1431=0b110110101100000100 & b_1012=0b100 & b_13=1 & b_0509=0b11111 & Rd_GPR64 +{ + build autiza__PACpart; +} + +# C6.2.22 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA page C6-1183 line 69908 MATCH xd503219f/mask=xfffffddf +# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f +# CONSTRUCT xd503219f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd503219f/mask=xffffffff --status nodest + +:autia1716 +is autia1716__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0001 & b_0507=0b100 & b_0004=0b11111 +{ + build autia1716__PACpart; +} + +# C6.2.22 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA page C6-1183 line 69908 MATCH xd503219f/mask=xfffffddf +# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f +# CONSTRUCT xd50323bf/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50323bf/mask=xffffffff --status nodest + +:autiasp +is autiasp__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0011 & b_0507=0b101 & b_0004=0b11111 +{ + build autiasp__PACpart; +} + +# C6.2.22 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA page C6-1183 line 69908 MATCH xd503219f/mask=xfffffddf +# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f +# CONSTRUCT xd503239f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd503239f/mask=xffffffff --status nodest + +:autiaz +is autiaz__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0011 & b_0507=0b100 & b_0004=0b11111 +{ + build autiaz__PACpart; +} + +# C6.2.23 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB page C6-1186 line 70065 MATCH xdac11400/mask=xffffdc00 +# CONSTRUCT xdac11400/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xdac11400/mask=xfffffc00 --status noqemu + +:autib Rd_GPR64, Rn_GPR64xsp +is autib__PACpart & b_1431=0b110110101100000100 & b_1012=0b101 & b_13=0 & Rn_GPR64xsp & Rd_GPR64 +{ + build autib__PACpart; +} + +# C6.2.23 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB page C6-1186 line 70065 MATCH xdac11400/mask=xffffdc00 +# CONSTRUCT xdac137e0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xdac137e0/mask=xffffffe0 --status noqemu + +:autizb Rd_GPR64 +is autizb__PACpart & b_1431=0b110110101100000100 & b_1012=0b101 & b_13=1 & b_0509=0b11111 & Rd_GPR64 +{ + build autizb__PACpart; +} + +# C6.2.23 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB page C6-1186 line 70065 MATCH xd50321df/mask=xfffffddf +# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f +# CONSTRUCT xd50321df/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50321df/mask=xffffffff --status nodest + +:autib1716 +is autib1716__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0001 & b_0507=0b110 & b_0004=0b11111 +{ + build autib1716__PACpart; +} + +# C6.2.23 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB page C6-1186 line 70065 MATCH xd50321df/mask=xfffffddf +# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f +# CONSTRUCT xd50323ff/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50323ff/mask=xffffffff --status nodest + +:autibsp +is autibsp__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0011 & b_0507=0b111 & b_0004=0b11111 +{ + build autibsp__PACpart; +} + +# C6.2.23 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB page C6-1186 line 70065 MATCH xd50321df/mask=xfffffddf +# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f +# CONSTRUCT xd50323df/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50323df/mask=xffffffff --status nodest + +:autibz +is autibz__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0011 & b_0507=0b110 & b_0004=0b11111 +{ + build autibz__PACpart; +} + +# C6.2.26 B.cond page C6-1191 line 70305 MATCH x54000000/mask=xff000010 +# CONSTRUCT x5400000f/mask=xff00001f MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x5400000f/mask=xff00001f --status nodest --comment "noflags qemuerr(illegal addresses cause qemu exit)" + +:b^"."^BranchCondOp Addr19 +is b_2531=0x2a & o1=0 & Addr19 & o0=0 & br_cond_op=15 & BranchCondOp +{ + goto Addr19; +} + +# C6.2.26 B.cond page C6-1191 line 70305 MATCH x54000000/mask=xff000010 +# CONSTRUCT x54000000/mask=xff000010 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x54000000/mask=xff000010 --status nodest --comment "flags qemuerr(illegal addresses cause qemu exit)" + +:b^"."^BranchCondOp Addr19 +is b_2531=0x2a & o1=0 & Addr19 & o0=0 & br_cond_op & BranchCondOp +{ + if (BranchCondOp) goto Addr19; +} + +# C6.2.25 B page C6-1190 line 70265 MATCH x14000000/mask=xfc000000 +# CONSTRUCT x14000000/mask=xfc000000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x14000000/mask=xfc000000 --status nodest --comment "flags qemuerr(illegal addresses cause qemu exit)" + +:b Addr26 +is b_31=0 & b_2630=0x05 & Addr26 +{ + goto Addr26; +} + +# C6.2.27 BC.cond page C6-1192 line 70348 MATCH x54000010/mask=xff000010 +# CONSTRUCT x54000010/mask=xff000010 MATCHED 1 DOCUMENTED OPCODES +# b_0031=01010100...................1.... + +:bc^"."^BranchCondOp Addr19 +is b_2531=0x2a & o1=0 & Addr19 & o0=1 & br_cond_op=15 & BranchCondOp +{ + goto Addr19; +} + +:bc^"."^BranchCondOp Addr19 +is b_2531=0x2a & o1=0 & Addr19 & o0=1 & BranchCondOp +{ + if (BranchCondOp) goto Addr19; +} + + +# C6.2.30 BFM page C6-1197 line 70576 MATCH x33000000/mask=x7f800000 +# C6.2.28 BFC page C6-1193 line 70394 MATCH x330003e0/mask=x7f8003e0 +# C6.2.29 BFI page C6-1195 line 70484 MATCH x33000000/mask=x7f800000 +# C6.2.31 BFXIL page C6-1199 line 70700 MATCH x33000000/mask=x7f800000 +# CONSTRUCT x33000000/mask=xffe08000 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst x33000000/mask=xffe08000 --status pass +# if sf == '0' && (N != '0' || immr<5> (b_21) != '0' || imms<5> (b_15) != '0') then ReservedValue(); + +:bfm Rd_GPR32, Rn_GPR32, ImmR_bitfield32_imm, ImmS_bitfield32_imm +is sf=0 & opc=1 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmR_bitfield32_imm & ImmS_bitfield32_imm & ImmRConst32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 & DecodeWMask32 & DecodeTMask32 +{ + local wmask:4 = DecodeWMask32; + local tmask:4 = DecodeTMask32; + local dst:4 = Rd_GPR32; + local src:4 = Rn_GPR32; + local bot:4 = (dst & ~(wmask)) | (((src>>ImmRConst32)|(src<<(32-ImmRConst32))) & wmask); + Rd_GPR64 = zext((dst & ~(tmask)) | (bot & tmask)); +} + +# C6.2.30 BFM page C6-1197 line 70576 MATCH x33000000/mask=x7f800000 +# C6.2.28 BFC page C6-1193 line 70394 MATCH x330003e0/mask=x7f8003e0 +# C6.2.29 BFI page C6-1195 line 70484 MATCH x33000000/mask=x7f800000 +# C6.2.31 BFXIL page C6-1199 line 70700 MATCH x33000000/mask=x7f800000 +# CONSTRUCT xb3400002/mask=xffc00002 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst xb3400002/mask=xffc00002 --status pass + +:bfm Rd_GPR64, Rn_GPR64, ImmR_bitfield64_imm, ImmS_bitfield64_imm +is ImmS_LT_ImmR=1 & sf=1 & opc=1 & b_2428=0x13 & b_2323=0 & n=1 & ImmR_bitfield64_imm & ImmRConst64 & ImmS_bitfield64_imm & Rn_GPR64 & Rd_GPR64 & DecodeWMask64 & DecodeTMask64 +{ + local wmask:8 = DecodeWMask64; + local tmask:8 = DecodeTMask64; + local dst:8 = Rd_GPR64; + local src:8 = Rn_GPR64; + local bot:8 = (dst & ~(wmask)) | (((src>>ImmRConst64)|(src<<(64-ImmRConst64))) & wmask); + Rd_GPR64 = (dst & ~(tmask)) | (bot & tmask); +} + +# C6.2.28 BFXIL page C6-567 line 33333 KEEPWITH + +BFextractWidth32: "#"^imm is ImmR & ImmS [ imm = ImmS - ImmR + 1; ] { export *[const]:4 imm; } +BFextractWidth64: "#"^imm is ImmR & ImmS [ imm = ImmS - ImmR + 1; ] { export *[const]:8 imm; } + +# C6.2.31 BFXIL page C6-1199 line 70700 MATCH x33000000/mask=x7f800000 +# C6.2.28 BFC page C6-1193 line 70394 MATCH x330003e0/mask=x7f8003e0 +# C6.2.29 BFI page C6-1195 line 70484 MATCH x33000000/mask=x7f800000 +# C6.2.30 BFM page C6-1197 line 70576 MATCH x33000000/mask=x7f800000 +# CONSTRUCT x33000000/mask=xffe08002 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst x33000000/mask=xffe08002 --status pass + +# Alias for bfm where UInt(imms) >= UInt(immr) + +:bfxil Rd_GPR32, Rn_GPR32, ImmRConst32, BFextractWidth32 +is ImmS_LT_ImmR=0 & sf=0 & opc=1 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & BFextractWidth32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + dst:4 = Rd_GPR32; + src:4 = Rn_GPR32; + mask:4 = (0xffffffff >> (32 - BFextractWidth32)); + tmp:4 = (src >> ImmRConst32) & mask; + Rd_GPR64 = zext((dst & ~(mask)) | tmp); +} + +# C6.2.31 BFXIL page C6-1199 line 70700 MATCH x33000000/mask=x7f800000 +# C6.2.28 BFC page C6-1193 line 70394 MATCH x330003e0/mask=x7f8003e0 +# C6.2.29 BFI page C6-1195 line 70484 MATCH x33000000/mask=x7f800000 +# C6.2.30 BFM page C6-1197 line 70576 MATCH x33000000/mask=x7f800000 +# CONSTRUCT xb3400000/mask=xffc00002 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst xb3400000/mask=xffc00002 --status pass + +# Alias for bfm where UInt(imms) >= UInt(immr) + +:bfxil Rd_GPR64, Rn_GPR64, ImmRConst64, BFextractWidth64 +is ImmS_LT_ImmR=0 & sf=1 & opc=1 & b_2428=0x13 & b_2323=0 & n=1 & ImmRConst64 & BFextractWidth64 & Rn_GPR64 & Rd_GPR64 +{ + dst:8 = Rd_GPR64; + src:8 = Rn_GPR64; + mask:8 = (0xffffffffffffffff >> (64 - BFextractWidth64)); + tmp:8 = (src >> ImmRConst64) & mask; + Rd_GPR64 = ((dst & ~(mask)) | tmp); +} + +# C6.2.32 BIC (shifted register) page C6-1201 line 70793 MATCH x0a200000/mask=x7f200000 +# CONSTRUCT x0a200000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x0a200000/mask=xff200000 --status pass + +:bic Rd_GPR32, Rn_GPR32, RegShift32Log +is sf=0 & opc=0 & b_2428=0xa & N=1 & RegShift32Log & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp_3:4 = RegShift32Log; + tmp_2:4 = tmp_3 ^ -1:4; + tmp_1:4 = Rn_GPR32 & tmp_2; + Rd_GPR64 = zext(tmp_1); +} + +# C6.2.32 BIC (shifted register) page C6-1201 line 70793 MATCH x0a200000/mask=x7f200000 +# CONSTRUCT x8a200000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x8a200000/mask=xff200000 --status pass + +:bic Rd_GPR64, Rn_GPR64, RegShift64Log +is sf=1 & opc=0 & b_2428=0xa & N=1 & RegShift64Log & Rn_GPR64 & Rd_GPR64 +{ + tmp_3:8= RegShift64Log; + tmp_2:8 = tmp_3 ^ -1:8; + tmp_1:8 = Rn_GPR64 & tmp_2; + Rd_GPR64 = tmp_1; +} + +# C6.2.33 BICS (shifted register) page C6-1203 line 70897 MATCH x6a200000/mask=x7f200000 +# CONSTRUCT x6a200000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x6a200000/mask=xff200000 --status pass --comment "flags" + +:bics Rd_GPR32, Rn_GPR32, RegShift32Log +is sf=0 & opc=3 & b_2428=0xa & N=1 & RegShift32Log & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp_3:4 = RegShift32Log; + tmp_2:4 = tmp_3 ^ -1:4; + tmp_1:4 = Rn_GPR32 & tmp_2; + resultflags(tmp_1); + Rd_GPR64 = zext(tmp_1); + affectLflags(); +} + +# C6.2.33 BICS (shifted register) page C6-1203 line 70897 MATCH x6a200000/mask=x7f200000 +# CONSTRUCT xea200000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xea200000/mask=xff200000 --status pass --comment "flags" + +:bics Rd_GPR64, Rn_GPR64, RegShift64Log +is sf=1 & opc=3 & b_2428=0xa & N=1 & RegShift64Log & Rn_GPR64 & Rd_GPR64 +{ + tmp_3:8= RegShift64Log; + tmp_2:8 = tmp_3 ^ -1:8; + tmp_1:8 = Rn_GPR64 & tmp_2; + resultflags(tmp_1); + Rd_GPR64 = tmp_1; + affectLflags(); +} + +# C6.2.34 BL page C6-1205 line 71008 MATCH x94000000/mask=xfc000000 +# CONSTRUCT x94000000/mask=xfc000000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x94000000/mask=xfc000000 --status nodest --comment "qemuerr(illegal addresses cause qemu exit)" + +:bl Addr26 +is b_31=1 & b_2630=0x05 & Addr26 +{ + x30 = inst_start + 4; + call Addr26; +} + +# C6.2.35 BLR page C6-1206 line 71050 MATCH xd63f0000/mask=xfffffc1f +# CONSTRUCT xd63f0000/mask=xfffffc1f MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd63f0000/mask=xfffffc1f --status nodest --comment "qemuerr(illegal addresses cause qemu exit)" + +:blr Rn_GPR64 +is b_2531=0x6b & b_2324=0 & b_2122=1 & b_1620=0x1f & b_1015=0 & Rn_GPR64 & b_0004=0 +{ + pc = Rn_GPR64; + x30 = inst_start + 4; + call [pc]; +} + +# C6.2.33 BLRAA, BLRAAZ, BLRAB, BLRABZ page C6-574 line 33668 KEEPWITH + +# Z == 0 && M == 0 && Rm = 11111 Key A, zero modifier variant + +blinkop: "l" is b_2122=0b01 { x30 = inst_start + 4; call [pc]; } +blinkop: "" is b_2122=0b00 { goto[pc]; } + +# C6.2.36 BLRAA, BLRAAZ, BLRAB, BLRABZ page C6-1207 line 71095 MATCH xd63f0800/mask=xfefff800 +# C6.2.38 BRAA, BRAAZ, BRAB, BRABZ page C6-1210 line 71251 MATCH xd61f0800/mask=xfefff800 +# C6.2.255 RETAA, RETAB page C6-1731 line 102135 MATCH xd65f0bff/mask=xfffffbff +# CONSTRUCT xd61f081f/mask=xff9ffc1f MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst xd61f081f/mask=xff9ffc1f --status nodest + +:b^blinkop^"raaz" Rn_GPR64 +is b_blinkop__raaz___PACpart & b_2531=0b1101011 & b_24=0 & b_23=0 & blinkop & b_1220=0b111110000 & b_11=1 & b_10=0 & b_0004=0b11111 & Rn_GPR64 +{ + build b_blinkop__raaz___PACpart; + pc = Rn_GPR64; + build blinkop; +} + +# C6.2.36 BLRAA, BLRAAZ, BLRAB, BLRABZ page C6-1207 line 71095 MATCH xd63f0800/mask=xfefff800 +# C6.2.38 BRAA, BRAAZ, BRAB, BRABZ page C6-1210 line 71251 MATCH xd61f0800/mask=xfefff800 +# CONSTRUCT xd71f0800/mask=xff9ffc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd71f0800/mask=xff9ffc00 --status nodest +# Z == 1 && M == 0 Key A, register modifier variant + +:b^blinkop^"raa" Rn_GPR64, Rd_GPR64xsp +is b_blinkop__raa___PACpart & b_2531=0b1101011 & b_24=1 & b_23=0 & blinkop & b_1220=0b111110000 & b_11=1 & b_10=0 & Rd_GPR64xsp & Rn_GPR64 +{ + build b_blinkop__raa___PACpart; + pc = Rn_GPR64; + build blinkop; +} + +# C6.2.36 BLRAA, BLRAAZ, BLRAB, BLRABZ page C6-1207 line 71095 MATCH xd63f0800/mask=xfefff800 +# C6.2.38 BRAA, BRAAZ, BRAB, BRABZ page C6-1210 line 71251 MATCH xd61f0800/mask=xfefff800 +# C6.2.255 RETAA, RETAB page C6-1731 line 102135 MATCH xd65f0bff/mask=xfffffbff +# CONSTRUCT xd61f0c1f/mask=xff9ffc1f MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst xd61f0c1f/mask=xff9ffc1f --status nodest +# Z == 0 && M == 1 && Rm = 11111 Key B, zero modifier variant + +:b^blinkop^"rabz" Rn_GPR64 +is b_blinkop__rabz___PACpart & b_2531=0b1101011 & b_24=0 & b_23=0 & blinkop & b_1220=0b111110000 & b_11=1 & b_10=1 & b_0004=0b11111 & Rn_GPR64 +{ + build b_blinkop__rabz___PACpart; + pc = Rn_GPR64; + build blinkop; +} + +# C6.2.36 BLRAA, BLRAAZ, BLRAB, BLRABZ page C6-1207 line 71095 MATCH xd63f0800/mask=xfefff800 +# C6.2.38 BRAA, BRAAZ, BRAB, BRABZ page C6-1210 line 71251 MATCH xd61f0800/mask=xfefff800 +# CONSTRUCT xd71f0c00/mask=xff9ffc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd71f0c00/mask=xff9ffc00 --status nodest +# Z == 1 && M == 1 Key B, register modifier variant + +:b^blinkop^"rab" Rn_GPR64, Rd_GPR64xsp +is b_blinkop__rab___PACpart & b_2531=0b1101011 & b_24=1 & b_23=0 & blinkop & b_1220=0b111110000 & b_11=1 & b_10=1 & Rd_GPR64xsp & Rn_GPR64 +{ + build b_blinkop__rab___PACpart; + pc = Rn_GPR64; + build blinkop; +} + +# C6.2.37 BR page C6-1209 line 71202 MATCH xd61f0000/mask=xfffffc1f +# CONSTRUCT xd61f0000/mask=xfffffc1f MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd61f0000/mask=xfffffc1f --status nodest + +:br Rn_GPR64 +is b_2531=0x6b & b_2324=0 & b_2122=0 & b_1620=0x1f & b_1015=0 & Rn_GPR64 & b_0004=0 +{ + pc = Rn_GPR64; + goto [pc]; +} + +# C6.2.40 BRK page C6-1213 line 71415 MATCH xd4200000/mask=xffe0001f +# CONSTRUCT xd4200000/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd4200000/mask=xffe0001f --status nodest + +:brk "#"^imm16 +is ALL_BTITARGETS & b_2431=0xd4 & b_2123=1 & imm16 & b_0204=0 & b_0001=0 +{ + tmp:2 = imm16; + preferred_exception_return:8 = inst_next; + pc = SoftwareBreakpoint(tmp, preferred_exception_return); + goto [pc]; +} + +# C6.2.37 CASB, CASAB, CASALB, CASLB page C6-580 line 33952 KEEPWITH + +cas_var: "a" is b_22=1 & b_15=0 { } +cas_var: "al" is b_22=1 & b_15=1 { } +cas_var: "" is b_22=0 & b_15=0 { } +cas_var: "l" is b_22=0 & b_15=1 { } + +# C6.2.42 CASB, CASAB, CASALB, CASLB page C6-1216 line 71570 MATCH x08a07c00/mask=xffa07c00 +# CONSTRUCT x08a07c00/mask=xffa07c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x08a07c00/mask=xffa07c00 --status nomem + +# CAS{,A,AL,L}B size=0b10 (b_3031) + +:cas^cas_var^"b" aa_Ws, aa_Wt, [Rn_GPR64xsp] +is b_3031=0b00 & b_2329=0b0010001 & b_21=1 & b_1014=0b11111 & cas_var & aa_Wt & Rn_GPR64xsp & aa_Ws +{ + comparevalue:1 = aa_Ws:1; + newvalue:1 = aa_Wt:1; + data:1 = *:1 Rn_GPR64xsp; + if (data != comparevalue) goto ; + *:1 Rn_GPR64xsp = newvalue; + + aa_Ws = zext(data); +} + +# C6.2.43 CASH, CASAH, CASALH, CASLH page C6-1218 line 71692 MATCH x48a07c00/mask=xffa07c00 +# CONSTRUCT x48a07c00/mask=xffa07c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x48a07c00/mask=xffa07c00 --status nomem + +# CAS{,A,AL,L}H size=0b10 (b_3031) + +:cas^cas_var^"h" aa_Ws, aa_Wt, [Rn_GPR64xsp] +is b_3031=0b01 & b_2329=0b0010001 & b_21=1 & b_1014=0b11111 & cas_var & aa_Wt & Rn_GPR64xsp & aa_Ws +{ + comparevalue:2 = aa_Ws:2; + newvalue:2 = aa_Wt:2; + data:2 = *:2 Rn_GPR64xsp; + if (data != comparevalue) goto ; + *:2 Rn_GPR64xsp = newvalue; + + aa_Ws = zext(data); +} + +# C6.2.44 CASP, CASPA, CASPAL, CASPL page C6-1220 line 71814 MATCH x08207c00/mask=xbfa07c00 +# CONSTRUCT x08207c00/mask=xffa17c01 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x08207c00/mask=xffa17c01 --status nomem + +# CASP{,A,AL,L} size=0b00 (b_3031) + +:casp^cas_var aa_Ws, aa_Wss, aa_Wt, aa_Wtt, [Rn_GPR64xsp] +is b_3031=0b00 & b_2329=0b0010000 & b_21=1 & b_1014=0b11111 & b_16=0 & b_00=0 & cas_var & aa_Ws & aa_Wss & aa_Wt & aa_Wtt & Rn_GPR64xsp +{ +@if DATA_ENDIAN == "big" + comparevalue:8 = (zext(aa_Ws) << 32) | zext(aa_Wss); + newvalue:8 = (zext(aa_Wt) << 32) | zext(aa_Wtt); +@else + comparevalue:8 = (zext(aa_Wss) << 32) | zext(aa_Ws); + newvalue:8 = (zext(aa_Wtt) << 32) | zext(aa_Wt); +@endif + data:8 = *:8 Rn_GPR64xsp; + if (data != comparevalue) goto ; + *:8 Rn_GPR64xsp = newvalue; + +@if DATA_ENDIAN == "big" + aa_Ws = data(4); + aa_Wss = data:4; +@else + aa_Ws = data:4; + aa_Wss = data(4); +@endif +} + +# C6.2.44 CASP, CASPA, CASPAL, CASPL page C6-1220 line 71814 MATCH x08207c00/mask=xbfa07c00 +# CONSTRUCT x48207c00/mask=xffa17c01 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x48207c00/mask=xffa17c01 --status nomem + +# CASP{,A,AL,L} size=0b01 (b_3031) + +:casp^cas_var aa_Xs, aa_Xss, aa_Xt, aa_Xtt, [Rn_GPR64xsp] +is b_3031=0b01 & b_2329=0b0010000 & b_21=1 & b_1014=0b11111 & b_16=0 & b_00=0 & cas_var & aa_Xs & aa_Xss & aa_Xt & aa_Xtt & Rn_GPR64xsp +{ + local tmp_s:8 = aa_Xs; + local tmp_ss:8 = aa_Xss; + local tmp_t:8 = aa_Xt; + local tmp_tt:8 = aa_Xtt; + +@if DATA_ENDIAN == "little" + # for little endian, swap Xss/Xs and Xtt/Xt + tmp_s = aa_Xss; + tmp_ss = aa_Xs; + tmp_t = aa_Xtt; + tmp_tt = aa_Xt; +@endif + + local tmp_addr:8 = Rn_GPR64xsp; + local tmp_d:8 = *:8 tmp_addr; + tmp_addr = tmp_addr + 8; + local tmp_dd:8 = *:8 tmp_addr; + + if (tmp_d != tmp_s) goto ; + if (tmp_dd != tmp_ss) goto ; + + tmp_addr = Rn_GPR64xsp; + *:8 tmp_addr = tmp_t; + tmp_addr = tmp_addr + 8; + *:8 tmp_addr = tmp_tt; + + aa_Xs = tmp_d; + aa_Xss = tmp_dd; +} + +# C6.2.45 CAS, CASA, CASAL, CASL page C6-1223 line 71996 MATCH x88a07c00/mask=xbfa07c00 +# CONSTRUCT x88a07c00/mask=xffa07c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x88a07c00/mask=xffa07c00 --status nomem +# CAS{,A,AL,L} size=0b10 (b_3031) + +:cas^cas_var aa_Ws, aa_Wt, [Rn_GPR64xsp] +is b_3031=0b10 & b_2329=0b0010001 & b_21=1 & b_1014=0b11111 & cas_var & aa_Wt & Rn_GPR64xsp & aa_Ws +{ + comparevalue:4 = aa_Ws; + newvalue:4 = aa_Wt; + data:4 = *:4 Rn_GPR64xsp; + if (data != comparevalue) goto ; + *:4 Rn_GPR64xsp = newvalue; + + aa_Ws = data; +} + +# C6.2.45 CAS, CASA, CASAL, CASL page C6-1223 line 71996 MATCH x88a07c00/mask=xbfa07c00 +# CONSTRUCT xc8a07c00/mask=xffa07c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xc8a07c00/mask=xffa07c00 --status nomem + +# CAS{,A,AL,L} size=0b11 (b_3031) + +:cas^cas_var aa_Xs, aa_Xt, [Rn_GPR64xsp] +is b_3031=0b11 & b_2329=0b0010001 & b_21=1 & b_1014=0b11111 & cas_var & aa_Xt & Rn_GPR64xsp & aa_Xs +{ + comparevalue:8 = aa_Xs; + newvalue:8 = aa_Xt; + data:8 = *:8 Rn_GPR64xsp; + if (data != comparevalue) goto ; + *:8 Rn_GPR64xsp = newvalue; + + aa_Xs = data; +} + +# C6.2.41 CBNZ page C6-589 line 34530 KEEPWITH + +ZeroOp: "z" is cmpr_op=0 { export 1:1; } +ZeroOp: "nz" is cmpr_op=1 { export 0:1; } + +BitPos: "#"^bitpos is sf=1 & b_31 & b_1923 & Rt_GPR64 [ bitpos = b_31 << 5 | b_1923; ] +{ + tmp:1 = ((Rt_GPR64 >> bitpos) & 1) == 0; + export tmp; +} + +BitPos: "#"^bitpos is sf=0 & b_31 & b_1923 & Rt_GPR32 [ bitpos = b_31 << 5 | b_1923; ] +{ + tmp:1 = ((Rt_GPR32 >> bitpos) & 1) == 0; + export tmp; +} + +# C6.2.46 CBNZ page C6-1226 line 72159 MATCH x35000000/mask=x7f000000 +# C6.2.47 CBZ page C6-1227 line 72216 MATCH x34000000/mask=x7f000000 +# CONSTRUCT xb4000000/mask=xfe000000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xb4000000/mask=xfe000000 --status nodest --comment "qemuerr(illegal addresses cause qemu exit)" + +:cb^ZeroOp Rd_GPR64, Addr19 +is sf=1 & b_2530=0x1a & ZeroOp & Addr19 & Rd_GPR64 +{ + tmp:1 = Rd_GPR64 == 0; + if (tmp == ZeroOp) goto Addr19; +} + +# C6.2.46 CBNZ page C6-1226 line 72159 MATCH x35000000/mask=x7f000000 +# C6.2.47 CBZ page C6-1227 line 72216 MATCH x34000000/mask=x7f000000 +# CONSTRUCT x34000000/mask=xfe000000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x34000000/mask=xfe000000 --status nodest --comment "qemuerr(illegal addresses cause qemu exit)" + +:cb^ZeroOp Rd_GPR32, Addr19 +is sf=0 & b_2530=0x1a & ZeroOp & Addr19 & Rd_GPR32 +{ + tmp:1 = Rd_GPR32 == 0; + if (tmp == ZeroOp) goto Addr19; +} + +# C6.2.46 CBNZ page C6-1226 line 72159 MATCH x35000000/mask=x7f000000 +# CONSTRUCT x35000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x35000000/mask=xff000000 --status nodest --comment "qemuerr(illegal addresses cause qemu exit)" + +:cbnz Rt_GPR32, Addr19 +is sf=0 & b_2530=0x1a & cmpr_op=1 & Addr19 & Rt_GPR32 +{ + if (Rt_GPR32 != 0) goto Addr19; +} + +# C6.2.46 CBNZ page C6-1226 line 72159 MATCH x35000000/mask=x7f000000 +# CONSTRUCT xb5000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xb5000000/mask=xff000000 --status nodest --comment "qemuerr(illegal addresses cause qemu exit)" + +:cbnz Rt_GPR64, Addr19 +is sf=1 & b_2530=0x1a & cmpr_op=1 & Addr19 & Rt_GPR64 +{ + if (Rt_GPR64 != 0) goto Addr19; +} + +# C6.2.47 CBZ page C6-1227 line 72216 MATCH x34000000/mask=x7f000000 +# CONSTRUCT x34000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x34000000/mask=xff000000 --status nodest --comment "qemuerr(illegal addresses cause qemu exit)" + +:cbz Rt_GPR32, Addr19 +is sf=0 & b_2530=0x1a & cmpr_op=0 & Addr19 & Rt_GPR32 +{ + if (Rt_GPR32 == 0) goto Addr19; +} + +# C6.2.47 CBZ page C6-1227 line 72216 MATCH x34000000/mask=x7f000000 +# CONSTRUCT xb4000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xb4000000/mask=xff000000 --status nodest --comment "qemuerr(illegal addresses cause qemu exit)" + +:cbz Rt_GPR64, Addr19 +is sf=1 & b_2530=0x1a & cmpr_op=0 & Addr19 & Rt_GPR64 +{ + if (Rt_GPR64 == 0) goto Addr19; +} + +# C6.2.48 CCMN (immediate) page C6-1228 line 72273 MATCH x3a400800/mask=x7fe00c10 +# CONSTRUCT x3a400800/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x3a400800/mask=xffe00c10 --status pass --comment "flags" + +:ccmn Rn_GPR32, UImm5, NZCVImm_uimm4, CondOp +is sf=0 & op=0 & s=1 & b_2428=0x1a & b_2123=2 & UImm5 & CondOp & b_1111=1 & o2=0 & Rn_GPR32 & o3=0 & NZCVImm_uimm4 +{ + condition:1 = CondOp; + condMask:1 = NZCVImm_uimm4; + setCC_NZCV(condMask); + if (!condition) goto inst_next; + tmp:4 = UImm5; + addflags(Rn_GPR32, tmp); + result:4 = Rn_GPR32 + tmp; + resultflags(result); + affectflags(); +} + +# C6.2.48 CCMN (immediate) page C6-1228 line 72273 MATCH x3a400800/mask=x7fe00c10 +# CONSTRUCT xba400800/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xba400800/mask=xffe00c10 --status pass --comment "flags" + +:ccmn Rn_GPR64, UImm5, NZCVImm_uimm4, CondOp +is sf=1 & op=0 & s=1 & b_2428=0x1a & b_2123=2 & UImm5 & CondOp & b_1111=1 & o2=0 & Rn_GPR64 & o3=0 & NZCVImm_uimm4 +{ + condition:1 = CondOp; + condMask:1 = NZCVImm_uimm4; + setCC_NZCV(condMask); + if (!condition) goto inst_next; + tmp:8 = zext(UImm5); + addflags(Rn_GPR64, tmp); + result:8 = Rn_GPR64 + tmp; + resultflags(result); + affectflags(); +} + +# C6.2.49 CCMN (register) page C6-1230 line 72358 MATCH x3a400000/mask=x7fe00c10 +# CONSTRUCT x3a400000/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x3a400000/mask=xffe00c10 --status pass --comment "flags" + +:ccmn Rn_GPR32, Rm_GPR32, NZCVImm_uimm4, CondOp +is sf=0 & op=0 & s=1 & b_2428=0x1a & b_2123=2 & Rm_GPR32 & CondOp & b_1111=0 & o2=0 & Rn_GPR32 & o3=0 & NZCVImm_uimm4 +{ + condition:1 = CondOp; + condMask:1 = NZCVImm_uimm4; + setCC_NZCV(condMask); + if (!condition) goto inst_next; + tmp:4 = Rm_GPR32; + addflags(Rn_GPR32, tmp); + result:4 = Rn_GPR32 + tmp; + resultflags(result); + affectflags(); +} + +# C6.2.49 CCMN (register) page C6-1230 line 72358 MATCH x3a400000/mask=x7fe00c10 +# CONSTRUCT xba400000/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xba400000/mask=xffe00c10 --status pass --comment "flags" + +:ccmn Rn_GPR64, Rm_GPR64, NZCVImm_uimm4, CondOp +is sf=1 & op=0 & s=1 & b_2428=0x1a & b_2123=2 & Rm_GPR64 & CondOp & b_1111=0 & o2=0 & Rn_GPR64 & o3=0 & NZCVImm_uimm4 +{ + condition:1 = CondOp; + condMask:1 = NZCVImm_uimm4; + setCC_NZCV(condMask); + if (!condition) goto inst_next; + tmp:8 = Rm_GPR64; + addflags(Rn_GPR64, tmp); + result:8 = Rn_GPR64 + tmp; + resultflags(result); + affectflags(); +} + +# C6.2.50 CCMP (immediate) page C6-1232 line 72446 MATCH x7a400800/mask=x7fe00c10 +# CONSTRUCT x7a400800/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x7a400800/mask=xffe00c10 --status pass --comment "flags" + +:ccmp Rn_GPR32, UImm5, NZCVImm_uimm4, CondOp +is sf=0 & op=1 & s=1 & b_2428=0x1a & b_2123=2 & UImm5 & CondOp & b_1111=1 & o2=0 & Rn_GPR32 & o3=0 & NZCVImm_uimm4 +{ + condition:1 = CondOp; + condMask:1 = NZCVImm_uimm4; + setCC_NZCV(condMask); + if (!condition) goto inst_next; + subflags(Rn_GPR32, UImm5); + tmp:4 = Rn_GPR32 - UImm5; + resultflags(tmp); + affectflags(); +} + +# C6.2.50 CCMP (immediate) page C6-1232 line 72446 MATCH x7a400800/mask=x7fe00c10 +# CONSTRUCT xfa400800/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xfa400800/mask=xffe00c10 --status pass --comment "flags" + +:ccmp Rn_GPR64, UImm5, NZCVImm_uimm4, CondOp +is sf=1 & op=1 & s=1 & b_2428=0x1a & b_2123=2 & UImm5 & CondOp & b_1111=1 & o2=0 & Rn_GPR64 & o3=0 & NZCVImm_uimm4 +{ + condition:1 = CondOp; + condMask:1 = NZCVImm_uimm4; + setCC_NZCV(condMask); + if (!condition) goto inst_next; + tmp:8 = zext(UImm5); + subflags(Rn_GPR64, tmp); + tmp = Rn_GPR64 - tmp; + resultflags(tmp); + affectflags(); +} + +# C6.2.51 CCMP (register) page C6-1234 line 72531 MATCH x7a400000/mask=x7fe00c10 +# CONSTRUCT x7a400000/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x7a400000/mask=xffe00c10 --status pass --comment "flags" + +:ccmp Rn_GPR32, Rm_GPR32, NZCVImm_uimm4, CondOp +is sf=0 & op=1 & s=1 & b_2428=0x1a & b_2123=2 & Rm_GPR32 & CondOp & b_1111=0 & o2=0 & Rn_GPR32 & o3=0 & NZCVImm_uimm4 +{ + condition:1 = CondOp; + condMask:1 = NZCVImm_uimm4; + setCC_NZCV(condMask); + if (!condition) goto inst_next; + subflags(Rn_GPR32, Rm_GPR32); + tmp:4 = Rn_GPR32 - Rm_GPR32; + resultflags(tmp); + affectflags(); +} + +# C6.2.51 CCMP (register) page C6-1234 line 72531 MATCH x7a400000/mask=x7fe00c10 +# CONSTRUCT xfa400000/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xfa400000/mask=xffe00c10 --status pass --comment "flags" + +:ccmp Rn_GPR64, Rm_GPR64, NZCVImm_uimm4, CondOp +is sf=1 & op=1 & s=1 & b_2428=0x1a & b_2123=2 & Rm_GPR64 & CondOp & b_1111=0 & o2=0 & Rn_GPR64 & o3=0 & NZCVImm_uimm4 +{ + condition:1 = CondOp; + condMask:1 = NZCVImm_uimm4; + setCC_NZCV(condMask); + if (!condition) goto inst_next; + subflags(Rn_GPR64, Rm_GPR64); + tmp:8 = Rn_GPR64 - Rm_GPR64; + resultflags(tmp); + affectflags(); +} + +# C6.2.52 CFINV page C6-1236 line 72619 MATCH xd500401f/mask=xfffff0ff +# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f +# CONSTRUCT xd500401f/mask=xfffff0ff MATCHED 2 DOCUMENTED OPCODES +# xd500401f/mask=xfffff0ff NOT MATCHED BY ANY CONSTRUCTOR + +:cfinv +is b_1231=0b11010101000000000100 & b_0811 & b_0007=0b00011111 +{ + CY = !CY; +} + +# C6.2.54 CINC page C6-1238 line 72719 MATCH x1a800400/mask=x7fe00c00 +# C6.2.104 CSET page C6-1445 line 86209 MATCH x1a9f07e0/mask=x7fff0fe0 +# C6.2.106 CSINC page C6-1449 line 86382 MATCH x1a800400/mask=x7fe00c00 +# CONSTRUCT x1a800400/mask=xffe00c00 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst x1a800400/mask=xffe00c00 --status pass --comment "flags" + +:cinc Rd_GPR32, Rn_GPR32, InvCondOp +is sf=0 & op=0 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR32 & InvCondOp & b_1011=1 & Rn=Rm & (Rn!=0x1f) & (b_15=0 | b_14=0 | b_13=0) & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + condition:1 = InvCondOp; + tmp:4 = Rn_GPR32; + if (!condition) goto ; + tmp = Rn_GPR32 + 1; + + Rd_GPR64 = zext(tmp); +} + +# C6.2.54 CINC page C6-1238 line 72719 MATCH x1a800400/mask=x7fe00c00 +# C6.2.104 CSET page C6-1445 line 86209 MATCH x1a9f07e0/mask=x7fff0fe0 +# C6.2.106 CSINC page C6-1449 line 86382 MATCH x1a800400/mask=x7fe00c00 +# CONSTRUCT x9a800400/mask=xffe00c00 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst x9a800400/mask=xffe00c00 --status pass --comment "flags" + +:cinc Rd_GPR64, Rn_GPR64, InvCondOp +is sf=1 & op=0 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & InvCondOp & b_1011=1 & Rn=Rm & (Rn!=0x1f) & (b_15=0 | b_14=0 | b_13=0) & Rn_GPR64 & Rd_GPR64 +{ + condition:1 = InvCondOp; + tmp:8 = Rn_GPR64; + if (!condition) goto ; + tmp = Rn_GPR64 + 1; + + Rd_GPR64 = tmp; +} + +# C6.2.55 CINV page C6-1240 line 72809 MATCH x5a800000/mask=x7fe00c00 +# C6.2.105 CSETM page C6-1447 line 86295 MATCH x5a9f03e0/mask=x7fff0fe0 +# C6.2.107 CSINV page C6-1451 line 86486 MATCH x5a800000/mask=x7fe00c00 +# CONSTRUCT x5a800000/mask=xffe00c00 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst x5a800000/mask=xffe00c00 --status pass --comment "flags" + +:cinv Rd_GPR32, Rn_GPR32, InvCondOp +is sf=0 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR32 & InvCondOp & b_1011=0 & Rn=Rm & (Rn!=0x1f) & (b_15=0 | b_14=0 | b_13=0) & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + condition:1 = InvCondOp; + tmp:4 = Rn_GPR32; + if (!condition) goto ; + tmp = ~Rn_GPR32; + + Rd_GPR64 = zext(tmp); +} + +# C6.2.55 CINV page C6-1240 line 72809 MATCH x5a800000/mask=x7fe00c00 +# C6.2.105 CSETM page C6-1447 line 86295 MATCH x5a9f03e0/mask=x7fff0fe0 +# C6.2.107 CSINV page C6-1451 line 86486 MATCH x5a800000/mask=x7fe00c00 +# CONSTRUCT xda800000/mask=xffe00c00 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst xda800000/mask=xffe00c00 --status pass --comment "flags" + +:cinv Rd_GPR64, Rn_GPR64, InvCondOp +is sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & InvCondOp & b_1011=0 & Rn=Rm & (Rn!=0x1f) & (b_15=0 | b_14=0 | b_13=0) & Rn_GPR64 & Rd_GPR64 +{ + condition:1 = InvCondOp; + tmp:8 = Rn_GPR64; + if (!condition) goto ; + tmp = ~Rn_GPR64; + + Rd_GPR64 = tmp; +} + +# C6.2.56 CLREX page C6-1242 line 72899 MATCH xd503305f/mask=xfffff0ff +# CONSTRUCT xd503305f/mask=xfffff0ff MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd503305f/mask=xfffff0ff --status nodest + +:clrex CRm_uimm4_def15 +is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_uimm4_def15 & Op2=2 & Rt=0x1f +{ + ClearExclusiveLocal(); +} + +# C6.2.57 CLS page C6-1243 line 72939 MATCH x5ac01400/mask=x7ffffc00 +# CONSTRUCT x5ac01400/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x5ac01400/mask=xfffffc00 --status pass + +:cls Rd_GPR32, Rn_GPR32 +is sf=0 & b_3030=1 & S=0 & b_2428=0x1a & b_2123=6 & dp1.opcode2=0x0 & b_1015=0x5 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + local tmp:4 = (Rn_GPR32 ^ (Rn_GPR32<<1))|0x1; + # first make all lower bits =1 + tmp = tmp | (tmp >> 1); + tmp = tmp | (tmp >> 2); + tmp = tmp | (tmp >> 4); + tmp = tmp | (tmp >> 8); + tmp = tmp | (tmp >> 16); + # now add the 1 bits together, voila + tmp = ((tmp & 0xaaaaaaaa)>>1) + (tmp & 0x55555555); + tmp = ((tmp & 0xcccccccc)>>2) + (tmp & 0x33333333); + tmp = ((tmp & 0xf0f0f0f0)>>4) + (tmp & 0x0f0f0f0f); + tmp = ((tmp & 0xff00ff00)>>8) + (tmp & 0x00ff00ff); + tmp = ((tmp & 0xffff0000)>>16) + (tmp & 0x0000ffff); + Rd_GPR64 = zext(32 - (tmp & 0x3f)); +} + +# C6.2.57 CLS page C6-1243 line 72939 MATCH x5ac01400/mask=x7ffffc00 +# CONSTRUCT xdac01400/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xdac01400/mask=xfffffc00 --status pass + +:cls Rd_GPR64, Rn_GPR64 +is sf=1 & b_3030=1 & S=0 & b_2428=0x1a & b_2123=6 & dp1.opcode2=0x0 & b_1015=0x5 & Rn_GPR64 & Rd_GPR64 +{ + local tmp:8 = (Rn_GPR64 ^ (Rn_GPR64<<1))|0x1; + # first make all lower bits =1 + tmp = tmp | (tmp >> 1); + tmp = tmp | (tmp >> 2); + tmp = tmp | (tmp >> 4); + tmp = tmp | (tmp >> 8); + tmp = tmp | (tmp >> 16); + tmp = tmp | (tmp >> 32); + # now add the 1 bits together, voila + tmp = ((tmp & 0xaaaaaaaaaaaaaaaa)>>1) + (tmp & 0x5555555555555555); + tmp = ((tmp & 0xcccccccccccccccc)>>2) + (tmp & 0x3333333333333333); + tmp = ((tmp & 0xf0f0f0f0f0f0f0f0)>>4) + (tmp & 0x0f0f0f0f0f0f0f0f); + tmp = ((tmp & 0xff00ff00ff00ff00)>>8) + (tmp & 0x00ff00ff00ff00ff); + tmp = ((tmp & 0xffff0000ffff0000)>>16) + (tmp & 0x0000ffff0000ffff); + tmp = ((tmp & 0xffffffff00000000)>>32) + (tmp & 0x00000000ffffffff); + Rd_GPR64 = 64 - (tmp & 0x7f); +} + +# C6.2.58 CLZ page C6-1245 line 73022 MATCH x5ac01000/mask=x7ffffc00 +# CONSTRUCT x5ac01000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x5ac01000/mask=xfffffc00 --status pass + +:clz Rd_GPR32, Rn_GPR32 +is sf=0 & b_3030=1 & S=0 & b_2428=0x1a & b_2123=6 & dp1.opcode2=0x0 & b_1015=0x4 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + local tmp:4 = Rn_GPR32; + # first make all lower bits =1 + tmp = tmp | (tmp >> 1); + tmp = tmp | (tmp >> 2); + tmp = tmp | (tmp >> 4); + tmp = tmp | (tmp >> 8); + tmp = tmp | (tmp >> 16); + # now add the 1 bits together, voila + tmp = ((tmp & 0xaaaaaaaa)>>1) + (tmp & 0x55555555); + tmp = ((tmp & 0xcccccccc)>>2) + (tmp & 0x33333333); + tmp = ((tmp & 0xf0f0f0f0)>>4) + (tmp & 0x0f0f0f0f); + tmp = ((tmp & 0xff00ff00)>>8) + (tmp & 0x00ff00ff); + tmp = ((tmp & 0xffff0000)>>16) + (tmp & 0x0000ffff); + Rd_GPR64 = zext(32 - (tmp & 0x3f)); +} + +# C6.2.58 CLZ page C6-1245 line 73022 MATCH x5ac01000/mask=x7ffffc00 +# CONSTRUCT xdac01000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xdac01000/mask=xfffffc00 --status pass + +:clz Rd_GPR64, Rn_GPR64 +is sf=1 & b_3030=1 & S=0 & b_2428=0x1a & b_2123=6 & dp1.opcode2=0x0 & b_1015=0x4 & Rn_GPR64 & Rd_GPR64 +{ + local tmp:8 = Rn_GPR64; + # first make all lower bits =1 + tmp = tmp | (tmp >> 1); + tmp = tmp | (tmp >> 2); + tmp = tmp | (tmp >> 4); + tmp = tmp | (tmp >> 8); + tmp = tmp | (tmp >> 16); + tmp = tmp | (tmp >> 32); + # now add the 1 bits together, voila + tmp = ((tmp & 0xaaaaaaaaaaaaaaaa)>>1) + (tmp & 0x5555555555555555); + tmp = ((tmp & 0xcccccccccccccccc)>>2) + (tmp & 0x3333333333333333); + tmp = ((tmp & 0xf0f0f0f0f0f0f0f0)>>4) + (tmp & 0x0f0f0f0f0f0f0f0f); + tmp = ((tmp & 0xff00ff00ff00ff00)>>8) + (tmp & 0x00ff00ff00ff00ff); + tmp = ((tmp & 0xffff0000ffff0000)>>16) + (tmp & 0x0000ffff0000ffff); + tmp = ((tmp & 0xffffffff00000000)>>32) + (tmp & 0x00000000ffffffff); + Rd_GPR64 = 64 - (tmp & 0x7f); +} + +# C6.2.59 CMN (extended register) page C6-1246 line 73092 MATCH x2b20001f/mask=x7fe0001f +# C6.2.7 ADDS (extended register) page C6-1156 line 68516 MATCH x2b200000/mask=x7fe00000 +# CONSTRUCT x2b20001f/mask=xffe0001f MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x2b20001f/mask=xffe0001f --status pass --comment "flags" + +:cmn Rn_GPR32wsp, ExtendRegShift32 +is sf=0 & op=0 & S=1 & SBIT_CZNO & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift32 & Rn_GPR32wsp & Rd=0x1f +{ + tmp_1:4 = ExtendRegShift32; + addflags(Rn_GPR32wsp, tmp_1); + result:4 = Rn_GPR32wsp + tmp_1; + resultflags(result); + build SBIT_CZNO; +} + +# C6.2.59 CMN (extended register) page C6-1246 line 73092 MATCH x2b20001f/mask=x7fe0001f +# C6.2.7 ADDS (extended register) page C6-1156 line 68516 MATCH x2b200000/mask=x7fe00000 +# CONSTRUCT xab20001f/mask=xffe0001f MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xab20001f/mask=xffe0001f --status pass --comment "flags" + +:cmn Rn_GPR64xsp, ExtendRegShift64 +is sf=1 & op=0 & S=1 & SBIT_CZNO & b_2428=0xb & b_2121=1 & opt=0 & ExtendRegShift64 & Rn_GPR64xsp & Rd=0x1f +{ + tmp_1:8 = ExtendRegShift64; + addflags(Rn_GPR64xsp, tmp_1); + result:8 = Rn_GPR64xsp + tmp_1; + resultflags(result); + build SBIT_CZNO; +} + +# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f +# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000 +# CONSTRUCT x3100001f/mask=xff00001f MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x3100001f/mask=xff00001f --status pass --comment "flags" + +:cmn Rn_GPR32xsp, ImmShift32 +is sf=0 & b_30=0 & b_29=1 & aa_Xd=31 & b_2428=0x11 & ImmShift32 & Rn_GPR32xsp +{ + addflags(Rn_GPR32xsp, ImmShift32); + tmp:4 = Rn_GPR32xsp + ImmShift32; + resultflags(tmp); + affectflags(); +} + +# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f +# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000 +# CONSTRUCT xb100001f/mask=xff00001f MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xb100001f/mask=xff00001f --status pass --comment "flags" + +:cmn Rn_GPR64xsp, ImmShift64 +is sf=1 & b_30=0 & b_29=1 & aa_Xd=31 & b_2428=0x11 & ImmShift64 & Rn_GPR64xsp +{ + addflags(Rn_GPR64xsp, ImmShift64); + tmp:8 = Rn_GPR64xsp + ImmShift64; + resultflags(tmp); + affectflags(); +} + +# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f +# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000 +# CONSTRUCT x3100001f/mask=xffc0001f MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x3100001f/mask=xffc0001f --status pass --comment "flags" + +:cmn Rn_GPR32wsp, Imm12_addsubimm_operand_i32_posimm_lsl0 +is sf=0 & op=0 & S=1 & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i32_posimm_lsl0 & Rn_GPR32wsp & Rd=0x1f +{ + tmp_1:4 = Imm12_addsubimm_operand_i32_posimm_lsl0; + addflags(Rn_GPR32wsp, tmp_1); + result:4 = Rn_GPR32wsp + tmp_1; + resultflags(result); + affectflags(); +} + +# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f +# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000 +# CONSTRUCT x3140001f/mask=xffc0001f MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x3140001f/mask=xffc0001f --status pass --comment "flags" + +:cmn Rn_GPR32wsp, Imm12_addsubimm_operand_i32_posimm_lsl12 +is sf=0 & op=0 & S=1 & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i32_posimm_lsl12 & Rn_GPR32wsp & Rd=0x1f +{ + tmp_1:4 = Imm12_addsubimm_operand_i32_posimm_lsl12; + addflags(Rn_GPR32wsp, tmp_1); + result:4 = Rn_GPR32wsp + tmp_1; + resultflags(result); + affectflags(); +} + +# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f +# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000 +# CONSTRUCT xb100001f/mask=xffc0001f MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xb100001f/mask=xffc0001f --status pass --comment "flags" + +:cmn Rn_GPR64xsp, Imm12_addsubimm_operand_i64_posimm_lsl0 +is sf=1 & op=0 & S=1 & SBIT_CZNO & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i64_posimm_lsl0 & Rn_GPR64xsp & Rd=0x1f +{ + tmp_1:8 = Imm12_addsubimm_operand_i64_posimm_lsl0; + addflags(Rn_GPR64xsp, tmp_1); + result:8 = Rn_GPR64xsp + tmp_1; + resultflags(result); + build SBIT_CZNO; +} + +# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f +# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000 +# CONSTRUCT xb140001f/mask=xffc0001f MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xb140001f/mask=xffc0001f --status pass --comment "flags" + +:cmn Rn_GPR64xsp, Imm12_addsubimm_operand_i64_posimm_lsl12 +is sf=1 & op=0 & S=1 & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i64_posimm_lsl12 & Rn_GPR64xsp & Rd=0x1f +{ + tmp_1:8 = Imm12_addsubimm_operand_i64_posimm_lsl12; + addflags(Rn_GPR64xsp, tmp_1); + result:8 = Rn_GPR64xsp + tmp_1; + resultflags(result); + affectflags(); +} + +# C6.2.61 CMN (shifted register) page C6-1250 line 73309 MATCH x2b00001f/mask=x7f20001f +# C6.2.9 ADDS (shifted register) page C6-1161 line 68775 MATCH x2b000000/mask=x7f200000 +# CONSTRUCT x2b00001f/mask=xff20801f MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x2b00001f/mask=xff20801f --status pass --comment "flags" +# if shift == '11' then ReservedValue(); + +:cmn Rn_GPR32, RegShift32 +is sf=0 & op=0 & S=1 & SBIT_CZNO & b_2428=0xb & b_2121=0 & b_15=0 & RegShift32 & Rn_GPR32 & Rd=0x1f +{ + tmp_1:4 = RegShift32; + addflags(Rn_GPR32, tmp_1); + result:4 = Rn_GPR32 + tmp_1; + resultflags(result); + build SBIT_CZNO; +} + +# C6.2.61 CMN (shifted register) page C6-1250 line 73309 MATCH x2b00001f/mask=x7f20001f +# C6.2.9 ADDS (shifted register) page C6-1161 line 68775 MATCH x2b000000/mask=x7f200000 +# CONSTRUCT xab00001f/mask=xff20001f MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xab00001f/mask=xff20001f --status pass --comment "flags" + +:cmn Rn_GPR64, RegShift64 +is sf=1 & op=0 & S=1 & SBIT_CZNO & b_2428=0xb & b_2121=0 & RegShift64 & Rn_GPR64 & Rd=0x1f +{ + tmp_1:8 = RegShift64; + addflags(Rn_GPR64, tmp_1); + result:8 = Rn_GPR64 + tmp_1; + resultflags(result); + build SBIT_CZNO; +} + +# C6.2.62 CMP (extended register) page C6-1252 line 73406 MATCH x6b20001f/mask=x7fe0001f +# C6.2.362 SUBS (extended register) page C6-1950 line 114543 MATCH x6b200000/mask=x7fe00000 +# CONSTRUCT x6b20001f/mask=xffe0001f MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x6b20001f/mask=xffe0001f --status pass --comment "flags" + +:cmp Rn_GPR32wsp, ExtendRegShift32 +is sf=0 & op=1 & S=1 & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift32 & Rn_GPR32wsp & Rd=0x1f +{ + subflags(Rn_GPR32wsp, ExtendRegShift32); + tmp:4 = Rn_GPR32wsp - ExtendRegShift32; + resultflags(tmp); + affectflags(); +} + +# C6.2.62 CMP (extended register) page C6-1252 line 73406 MATCH x6b20001f/mask=x7fe0001f +# C6.2.362 SUBS (extended register) page C6-1950 line 114543 MATCH x6b200000/mask=x7fe00000 +# CONSTRUCT xeb20001f/mask=xffe0001f MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xeb20001f/mask=xffe0001f --status pass --comment "flags" + +:cmp Rn_GPR64xsp, ExtendRegShift64 +is sf=1 & op=1 & S=1 & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift64 & Rn_GPR64xsp & Rd=0x1f +{ + subflags(Rn_GPR64xsp, ExtendRegShift64); + tmp:8 = Rn_GPR64xsp - ExtendRegShift64; + resultflags(tmp); + affectflags(); +} + +# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f +# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000 +# CONSTRUCT x7100001f/mask=xff00001f MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x7100001f/mask=xff00001f --status pass --comment "flags" + +:cmp Rn_GPR32xsp, ImmShift32 +is sf=0 & b_30=1 & b_29=1 & b_2428=0x11 & ImmShift32 & Rn_GPR32xsp & aa_Wd=31 +{ + subflags(Rn_GPR32xsp, ImmShift32); + tmp:4 = Rn_GPR32xsp - ImmShift32; + resultflags(tmp); + affectflags(); +} + +# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f +# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000 +# CONSTRUCT xf100001f/mask=xff00001f MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xf100001f/mask=xff00001f --status pass --comment "flags" + +:cmp Rn_GPR64xsp, ImmShift64 +is sf=1 & b_30=1 & b_29=1 & b_2428=0x11 & ImmShift64 & Rn_GPR64xsp & aa_Wd=31 +{ + subflags(Rn_GPR64xsp, ImmShift64); + tmp:8 = Rn_GPR64xsp - ImmShift64; + resultflags(tmp); + affectflags(); +} + +# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f +# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000 +# CONSTRUCT x7100001f/mask=xffc0001f MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x7100001f/mask=xffc0001f --status pass --comment "flags" + +:cmp Rn_GPR32wsp, Imm12_addsubimm_operand_i32_negimm_lsl0 +is sf=0 & op=1 & S=1 & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i32_negimm_lsl0 & Rn_GPR32wsp & Rd=0x1f +{ + tmp_1:4 = Imm12_addsubimm_operand_i32_negimm_lsl0; + subflags(Rn_GPR32wsp, Imm12_addsubimm_operand_i32_negimm_lsl0); + result:4 = Rn_GPR32wsp - tmp_1; + resultflags(result); + affectflags(); +} + +# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f +# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000 +# CONSTRUCT x7140001f/mask=xffc0001f MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x7140001f/mask=xffc0001f --status pass --comment "flags" + +:cmp Rn_GPR32wsp, Imm12_addsubimm_operand_i32_negimm_lsl12 +is sf=0 & op=1 & S=1 & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i32_negimm_lsl12 & Rn_GPR32wsp & Rd=0x1f +{ + tmp_2:4 = Imm12_addsubimm_operand_i32_negimm_lsl12; + subflags(Rn_GPR32wsp, tmp_2); + tmp_1:4 = Rn_GPR32wsp - tmp_2; + resultflags(tmp_1); + affectflags(); +} + +# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f +# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000 +# CONSTRUCT xf100001f/mask=xffc0001f MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xf100001f/mask=xffc0001f --status pass --comment "flags" + +:cmp Rn_GPR64xsp, Imm12_addsubimm_operand_i64_negimm_lsl0 +is sf=1 & op=1 & S=1 & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i64_negimm_lsl0 & Rn_GPR64xsp & Rd=0x1f +{ + tmp_2:8 = Imm12_addsubimm_operand_i64_negimm_lsl0; + subflags(Rn_GPR64xsp, tmp_2); + tmp_1:8 = Rn_GPR64xsp - tmp_2; + resultflags(tmp_1); + affectflags(); +} + +# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f +# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000 +# CONSTRUCT xf140001f/mask=xffc0001f MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xf140001f/mask=xffc0001f --status pass --comment "flags" + +:cmp Rn_GPR64xsp, Imm12_addsubimm_operand_i64_negimm_lsl12 +is sf=1 & op=1 & S=1 & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i64_negimm_lsl12 & Rn_GPR64xsp & Rd=0x1f +{ + tmp_2:8 = Imm12_addsubimm_operand_i64_negimm_lsl12; + subflags(Rn_GPR64xsp, tmp_2); + tmp_1:8 = Rn_GPR64xsp - tmp_2; + resultflags(tmp_1); + affectflags(); +} + +# C6.2.64 CMP (shifted register) page C6-1256 line 73623 MATCH x6b00001f/mask=x7f20001f +# C6.2.235 NEGS page C6-1696 line 100340 MATCH x6b0003e0/mask=x7f2003e0 +# C6.2.364 SUBS (shifted register) page C6-1955 line 114807 MATCH x6b000000/mask=x7f200000 +# CONSTRUCT x6b00001f/mask=xff20001f MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst x6b00001f/mask=xff20001f --status pass --comment "flags" + +:cmp Rn_GPR32, RegShift32 +is sf=0 & op=1 & S=1 & b_2428=0xb & b_2121=0 & RegShift32 & Rn!=0x1f & Rn_GPR32 & Rd=0x1f +{ + subflags(Rn_GPR32, RegShift32); + tmp:4 = Rn_GPR32 - RegShift32; + resultflags(tmp); + affectflags(); +} + +# C6.2.64 CMP (shifted register) page C6-1256 line 73623 MATCH x6b00001f/mask=x7f20001f +# C6.2.235 NEGS page C6-1696 line 100340 MATCH x6b0003e0/mask=x7f2003e0 +# C6.2.364 SUBS (shifted register) page C6-1955 line 114807 MATCH x6b000000/mask=x7f200000 +# CONSTRUCT xeb00001f/mask=xff20001f MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst xeb00001f/mask=xff20001f --status pass --comment "flags" + +:cmp Rn_GPR64, RegShift64 +is sf=1 & op=1 & S=1 & b_2428=0xb & b_2121=0 & Rm_GPR64 & RegShift64 & Rn!=0x1f & Rn_GPR64 & Rd=0x1f +{ + subflags(Rn_GPR64, RegShift64); + tmp:8 = Rn_GPR64 - RegShift64; + resultflags(tmp); + affectflags(); +} + +# C6.2.66 CNEG page C6-1259 line 73771 MATCH x5a800400/mask=x7fe00c00 +# C6.2.108 CSNEG page C6-1453 line 86590 MATCH x5a800400/mask=x7fe00c00 +# CONSTRUCT x5a800400/mask=xffe00c00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x5a800400/mask=xffe00c00 --status pass --comment "flags" + +:cneg Rd_GPR32, Rn_GPR32, InvCondOp +is sf=0 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR32 & InvCondOp & b_1011=1 & Rn=Rm & (b_15=0 | b_14=0 | b_13=0) & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + condition:1 = InvCondOp; + tmp:4 = -Rn_GPR32; + if (condition) goto ; + tmp = Rn_GPR32; + + Rd_GPR64 = zext(tmp); +} + +# C6.2.66 CNEG page C6-1259 line 73771 MATCH x5a800400/mask=x7fe00c00 +# C6.2.108 CSNEG page C6-1453 line 86590 MATCH x5a800400/mask=x7fe00c00 +# CONSTRUCT xda800400/mask=xffe00c00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xda800400/mask=xffe00c00 --status pass --comment "flags" + +:cneg Rd_GPR64, Rn_GPR64, InvCondOp +is sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & InvCondOp & b_1011=1 & Rn=Rm & (b_15=0 | b_14=0 | b_13=0) & Rn_GPR64 & Rd_GPR64 +{ + condition:1 = InvCondOp; + tmp:8 = -Rn_GPR64; + if (condition) goto ; + tmp = Rn_GPR64; + + Rd_GPR64 = tmp; +} + +# C6.2.68 CPYFP, CPYFM, CPYFE page C6-1262 line 73913 MATCH x19000400/mask=x3f20fc00 +# C6.2.69 CPYFPN, CPYFMN, CPYFEN page C6-1267 line 74246 MATCH x1900c400/mask=x3f20fc00 +# C6.2.70 CPYFPRN, CPYFMRN, CPYFERN page C6-1272 line 74579 MATCH x19008400/mask=x3f20fc00 +# C6.2.79 CPYFPWN, CPYFMWN, CPYFEWN page C6-1317 line 77576 MATCH x19004400/mask=x3f20fc00 +# CONSTRUCT x19000400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES + +cpyPhase:"p" is opt=0 {export 0:1;} +cpyPhase:"m" is opt=1 {export 1:1;} +cpyPhase:"e" is opt=2 {export 2:1;} + +cpyType: "" is b_1015=0x01 {export 0x01:1; } +cpyType: "n" is b_1015=0x31 {export 0x31:1; } +cpyType: "rn" is b_1015=0x21 {export 0x21:1; } +cpyType: "wn" is b_1015=0x11 {export 0x11:1; } + +cpyType: "rt" is b_1015=0x09 {export 0x09:1; } +cpyType: "rtn" is b_1015=0x39 {export 0x39:1; } +cpyType: "rtrn" is b_1015=0x29 {export 0x29:1; } +cpyType: "rtwn" is b_1015=0x19 {export 0x19:1; } + +cpyType: "t" is b_1015=0x0d {export 0x0d:1; } +cpyType: "tn" is b_1015=0x3d {export 0x3d:1; } +cpyType: "trn" is b_1015=0x2d {export 0x2d:1; } +cpyType: "twn" is b_1015=0x1d {export 0x1d:1; } + +cpyType: "wt" is b_1015=0x03 {export 0x03:1; } +cpyType: "wtn" is b_1015=0x33 {export 0x33:1; } +cpyType: "wtrn" is b_1015=0x23 {export 0x23:1; } +cpyType: "wtwn" is b_1015=0x13 {export 0x13:1; } + + +define pcodeop MemoryCopyForward; +# Memory Copy Forward-only +:cpyf^cpyPhase^cpyType [Rd_GPR64]!, [Rs_GPR64]!, Rn_GPR64^"!" +is size.ldstr & b_2429=0x19 & opt != 3 & cpyPhase & b_2121=0 & Rs_GPR64 & cpyType & Rn_GPR64 & Rd_GPR64 +{ + MemoryCopyForward(Rd_GPR64, Rs_GPR64, Rn_GPR64, cpyType, cpyPhase); +} +define pcodeop MemoryCopy; +:cpy^cpyPhase^cpyType [Rd_GPR64]!, [Rs_GPR64]!, Rn_GPR64^"!" +is size.ldstr & b_2429=0x1d & opt != 3 & cpyPhase & b_2121=0 & Rs_GPR64 & cpyType & Rn_GPR64 & Rd_GPR64 +{ + MemoryCopy(Rd_GPR64, Rs_GPR64, Rn_GPR64, cpyType, cpyPhase); +} + +# C6.2.59 CRC32B, CRC32H, CRC32W, CRC32X page C6-611 line 35802 KEEPWITH +# sf == 0 && sz = 00 CRC32CB variant + +crcpoly: "" is b_12=0 {tmp:4 = 0x04C11DB7; export *[const]:4 tmp; } +crcpoly: "c" is b_12=1 { tmp:4 = 0x1EDC6F41; export *[const]:4 tmp; } + +# C6.2.100 CRC32B, CRC32H, CRC32W, CRC32X page C6-1438 line 85850 MATCH x1ac04000/mask=x7fe0f000 +# C6.2.101 CRC32CB, CRC32CH, CRC32CW, CRC32CX page C6-1440 line 85958 MATCH x1ac05000/mask=x7fe0f000 +# CONSTRUCT x1ac04000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x1ac04000/mask=xffe0ec00 --status noqemu + +:crc32^crcpoly^"b" Rd_GPR32, Rn_GPR32, Rm_GPR32 +is b_31=0 & b_2130=0b0011010110 & b_1315=0b010 & b_1011=0b00 & crcpoly & Rm_GPR32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + local tmp_Rd:4 = crc32b(Rn_GPR32, Rm_GPR32, crcpoly); + Rd_GPR64 = zext(tmp_Rd); +} + +# C6.2.100 CRC32B, CRC32H, CRC32W, CRC32X page C6-1438 line 85850 MATCH x1ac04000/mask=x7fe0f000 +# C6.2.101 CRC32CB, CRC32CH, CRC32CW, CRC32CX page C6-1440 line 85958 MATCH x1ac05000/mask=x7fe0f000 +# CONSTRUCT x1ac04400/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x1ac04400/mask=xffe0ec00 --status noqemu +# sf == 0 && sz = 01 CRC32CH variant + +:crc32^crcpoly^"h" Rd_GPR32, Rn_GPR32, Rm_GPR32 +is b_31=0 & b_2130=0b0011010110 & b_1315=0b010 & b_1011=0b01 & crcpoly & Rm_GPR32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + local tmp_Rd:4 = crc32h(Rn_GPR32, Rm_GPR32, crcpoly); + Rd_GPR64 = zext(tmp_Rd); +} + +# C6.2.100 CRC32B, CRC32H, CRC32W, CRC32X page C6-1438 line 85850 MATCH x1ac04000/mask=x7fe0f000 +# C6.2.101 CRC32CB, CRC32CH, CRC32CW, CRC32CX page C6-1440 line 85958 MATCH x1ac05000/mask=x7fe0f000 +# CONSTRUCT x1ac04800/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x1ac04800/mask=xffe0ec00 --status noqemu +# sf == 0 && sz = 10 CRC32CW variant + +:crc32^crcpoly^"w" Rd_GPR32, Rn_GPR32, Rm_GPR32 +is b_31=0 & b_2130=0b0011010110 & b_1315=0b010 & b_1011=0b10 & crcpoly & Rm_GPR32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + local tmp_Rd:4 = crc32w(Rn_GPR32, Rm_GPR32, crcpoly); + Rd_GPR64 = zext(tmp_Rd); +} + +# C6.2.100 CRC32B, CRC32H, CRC32W, CRC32X page C6-1438 line 85850 MATCH x1ac04000/mask=x7fe0f000 +# C6.2.101 CRC32CB, CRC32CH, CRC32CW, CRC32CX page C6-1440 line 85958 MATCH x1ac05000/mask=x7fe0f000 +# CONSTRUCT x9ac04c00/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x9ac04c00/mask=xffe0ec00 --status noqemu +# sf == 1 && sz = 11 CRC32CX variant + +:crc32^crcpoly^"x" Rd_GPR32, Rn_GPR32, Rm_GPR64 +is b_31=1 & b_2130=0b0011010110 & b_1315=0b010 & b_1011=0b11 & crcpoly & Rm_GPR64 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + local tmp_Rd:4 = crc32x(Rn_GPR32, Rm_GPR64, crcpoly); + Rd_GPR64 = zext(tmp_Rd); +} + +# C6.2.103 CSEL page C6-1443 line 86120 MATCH x1a800000/mask=x7fe00c00 +# CONSTRUCT x1a800000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x1a800000/mask=xffe00c00 --status pass --comment "flags" + +:csel Rd_GPR32, Rn_GPR32, Rm_GPR32, CondOp +is sf=0 & op=0 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR32 & CondOp & b_1011=0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + condition:1 = CondOp; + tmp:4 = Rn_GPR32; + if (condition) goto ; + tmp = Rm_GPR32; + + Rd_GPR64 = zext(tmp); +} + +# C6.2.103 CSEL page C6-1443 line 86120 MATCH x1a800000/mask=x7fe00c00 +# CONSTRUCT x9a800000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x9a800000/mask=xffe00c00 --status pass --comment "flags" + +:csel Rd_GPR64, Rn_GPR64, Rm_GPR64, CondOp +is sf=1 & op=0 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & CondOp & b_1011=0 & Rn_GPR64 & Rd_GPR64 +{ + condition:1 = CondOp; + tmp:8 = Rn_GPR64; + if (condition) goto ; + tmp = Rm_GPR64; + + Rd_GPR64 = tmp; +} + +# C6.2.104 CSET page C6-1445 line 86209 MATCH x1a9f07e0/mask=x7fff0fe0 +# C6.2.54 CINC page C6-1238 line 72719 MATCH x1a800400/mask=x7fe00c00 +# C6.2.106 CSINC page C6-1449 line 86382 MATCH x1a800400/mask=x7fe00c00 +# CONSTRUCT x1a9f07e0/mask=xffff0fe0 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst x1a9f07e0/mask=xffff0fe0 --status pass --comment "flags" + +:cset Rd_GPR32, InvCondOp +is sf=0 & op=0 & s=0 & b_2428=0x1a & b_2123=4 & InvCondOp & b_1011=1 & Rn=0x1f & Rm=0x1f & (b_15=0 | b_14=0 | b_13=0) & Rd_GPR32 & Rd_GPR64 +{ + condition:1 = InvCondOp; + Rd_GPR64 = zext(condition); +} + +# C6.2.104 CSET page C6-1445 line 86209 MATCH x1a9f07e0/mask=x7fff0fe0 +# C6.2.54 CINC page C6-1238 line 72719 MATCH x1a800400/mask=x7fe00c00 +# C6.2.106 CSINC page C6-1449 line 86382 MATCH x1a800400/mask=x7fe00c00 +# CONSTRUCT x9a9f07e0/mask=xffff0fe0 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst x9a9f07e0/mask=xffff0fe0 --status pass --comment "flags" + +:cset Rd_GPR64, InvCondOp +is sf=1 & op=0 & s=0 & b_2428=0x1a & b_2123=4 & InvCondOp & b_1011=1 & Rn=0x1f & Rm=0x1f & (b_15=0 | b_14=0 | b_13=0) & Rd_GPR64 +{ + condition:1 = InvCondOp; + Rd_GPR64 = zext(condition); +} + +# C6.2.105 CSETM page C6-1447 line 86295 MATCH x5a9f03e0/mask=x7fff0fe0 +# C6.2.55 CINV page C6-1240 line 72809 MATCH x5a800000/mask=x7fe00c00 +# C6.2.107 CSINV page C6-1451 line 86486 MATCH x5a800000/mask=x7fe00c00 +# CONSTRUCT x5a9f03e0/mask=xffff0fe0 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst x5a9f03e0/mask=xffff0fe0 --status pass --comment "flags" + +:csetm Rd_GPR32, InvCondOp +is sf=0 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR32 & InvCondOp & b_1011=0 & Rn=0x1f & Rm=0x1f & (b_15=0 | b_14=0 | b_13=0) & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + condition:1 = InvCondOp; + tmp:4 = zext(condition) * -1; + Rd_GPR64 = zext(tmp); +} + +# C6.2.105 CSETM page C6-1447 line 86295 MATCH x5a9f03e0/mask=x7fff0fe0 +# C6.2.55 CINV page C6-1240 line 72809 MATCH x5a800000/mask=x7fe00c00 +# C6.2.107 CSINV page C6-1451 line 86486 MATCH x5a800000/mask=x7fe00c00 +# CONSTRUCT xda9f03e0/mask=xffff0fe0 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst xda9f03e0/mask=xffff0fe0 --status pass --comment "flags" + +:csetm Rd_GPR64, InvCondOp +is sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & InvCondOp & b_1011=0 & Rn=0x1f & Rm=0x1f & (b_15=0 | b_14=0 | b_13=0) & Rn_GPR64 & Rd_GPR64 +{ + condition:1 = InvCondOp; + Rd_GPR64 = zext(condition) * -1; +} + +# C6.2.106 CSINC page C6-1449 line 86382 MATCH x1a800400/mask=x7fe00c00 +# C6.2.54 CINC page C6-1238 line 72719 MATCH x1a800400/mask=x7fe00c00 +# C6.2.104 CSET page C6-1445 line 86209 MATCH x1a9f07e0/mask=x7fff0fe0 +# CONSTRUCT x1a800400/mask=xffe00c00 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst x1a800400/mask=xffe00c00 --status pass --comment "flags" + +:csinc Rd_GPR32, Rn_GPR32, Rm_GPR32, CondOp +is sf=0 & op=0 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR32 & CondOp & b_1011=1 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + condition:1 = CondOp; + tmp:4 = Rn_GPR32; + if (condition) goto ; + tmp = Rm_GPR32 + 1; + + Rd_GPR64 = zext(tmp); +} + +# C6.2.106 CSINC page C6-1449 line 86382 MATCH x1a800400/mask=x7fe00c00 +# C6.2.54 CINC page C6-1238 line 72719 MATCH x1a800400/mask=x7fe00c00 +# C6.2.104 CSET page C6-1445 line 86209 MATCH x1a9f07e0/mask=x7fff0fe0 +# CONSTRUCT x9a800400/mask=xffe00c00 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst x9a800400/mask=xffe00c00 --status pass --comment "flags" + +:csinc Rd_GPR64, Rn_GPR64, Rm_GPR64, CondOp +is sf=1 & op=0 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & CondOp & b_1011=1 & Rn_GPR64 & Rd_GPR64 +{ + condition:1 = CondOp; + tmp:8 = Rn_GPR64; + if (condition) goto ; + tmp = Rm_GPR64 + 1; + + Rd_GPR64 = tmp; +} + +# C6.2.107 CSINV page C6-1451 line 86486 MATCH x5a800000/mask=x7fe00c00 +# C6.2.55 CINV page C6-1240 line 72809 MATCH x5a800000/mask=x7fe00c00 +# C6.2.105 CSETM page C6-1447 line 86295 MATCH x5a9f03e0/mask=x7fff0fe0 +# CONSTRUCT x5a800000/mask=xffe00c00 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst x5a800000/mask=xffe00c00 --status pass --comment "flags" + +:csinv Rd_GPR32, Rn_GPR32, Rm_GPR32, CondOp +is sf=0 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR32 & CondOp & b_1011=0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + condition:1 = CondOp; + tmp:4 = Rn_GPR32; + if (condition) goto ; + tmp = ~Rm_GPR32; + + Rd_GPR64 = zext(tmp); +} + +# C6.2.107 CSINV page C6-1451 line 86486 MATCH x5a800000/mask=x7fe00c00 +# C6.2.55 CINV page C6-1240 line 72809 MATCH x5a800000/mask=x7fe00c00 +# C6.2.105 CSETM page C6-1447 line 86295 MATCH x5a9f03e0/mask=x7fff0fe0 +# CONSTRUCT xda800000/mask=xffe00c00 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst xda800000/mask=xffe00c00 --status pass --comment "flags" + +:csinv Rd_GPR64, Rn_GPR64, Rm_GPR64, CondOp +is sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & CondOp & b_1011=0 & Rn_GPR64 & Rd_GPR64 +{ + condition:1 = CondOp; + tmp:8 = Rn_GPR64; + if (condition) goto ; + tmp = ~Rm_GPR64; + + Rd_GPR64 = tmp; +} + +# C6.2.108 CSNEG page C6-1453 line 86590 MATCH x5a800400/mask=x7fe00c00 +# C6.2.66 CNEG page C6-1259 line 73771 MATCH x5a800400/mask=x7fe00c00 +# CONSTRUCT x5a800400/mask=xffe00c00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x5a800400/mask=xffe00c00 --status pass --comment "flags" + +:csneg Rd_GPR32, Rn_GPR32, Rm_GPR32, CondOp +is sf=0 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR32 & CondOp & b_1011=1 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + condition:1 = CondOp; + tmp:4 = Rn_GPR32; + if (condition) goto ; + tmp = -Rm_GPR32; + + Rd_GPR64 = zext(tmp); +} + +# C6.2.108 CSNEG page C6-1453 line 86590 MATCH x5a800400/mask=x7fe00c00 +# C6.2.66 CNEG page C6-1259 line 73771 MATCH x5a800400/mask=x7fe00c00 +# CONSTRUCT xda800400/mask=xffe00c00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xda800400/mask=xffe00c00 --status pass --comment "flags" + +:csneg Rd_GPR64, Rn_GPR64, Rm_GPR64, CondOp +is sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & CondOp & b_1011=1 & Rn_GPR64 & Rd_GPR64 +{ + condition:1 = CondOp; + tmp:8 = Rn_GPR64; + if (condition) goto ; + tmp = -Rm_GPR64; + + Rd_GPR64 = tmp; +} + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50b7420/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst xd50b7420/mask=xffffffe0 --status nodest + +:dc "ZVA", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b0100 & b_0507=0b001 & Rt_GPR64 +{ DC_ZVA(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5087620/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst xd5087620/mask=xffffffe0 --status nodest + +:dc "IVAC", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b0110 & b_0507=0b001 & Rt_GPR64 +{ DC_IVAC(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5087640/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst xd5087640/mask=xffffffe0 --status nodest + +:dc "ISW", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b0110 & b_0507=0b010 & Rt_GPR64 +{ DC_ISW(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50b7a20/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst xd50b7a20/mask=xffffffe0 --status nopcodeop + +:dc "CVAC", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1010 & b_0507=0b001 & Rt_GPR64 +{ DC_CVAC(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5087a40/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst xd5087a40/mask=xffffffe0 --status nodest + +:dc "CSW", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1010 & b_0507=0b010 & Rt_GPR64 +{ DC_CSW(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50b7b20/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst xd50b7b20/mask=xffffffe0 --status nodest + +:dc "CVAU", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1011 & b_0507=0b001 & Rt_GPR64 +{ DC_CVAU(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50b7e20/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst xd50b7e20/mask=xffffffe0 --status nodest + +:dc "CIVAC", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1110 & b_0507=0b001 & Rt_GPR64 +{ DC_CIVAC(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5087e40/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst xd5087e40/mask=xffffffe0 --status nodest + +:dc "CISW", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1110 & b_0507=0b010 & Rt_GPR64 +{ DC_CISW(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50b7c20/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst xd50b7c20/mask=xffffffe0 --status nodest + +:dc "CVAP", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1100 & b_0507=0b001 & Rt_GPR64 +{ DC_CVAP(Rt_GPR64); } + +# C6.2.110 DCPS1 page C6-1457 line 86790 MATCH xd4a00001/mask=xffe0001f +# CONSTRUCT xd4a00001/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd4a00001/mask=xffe0001f --status nodest + +:dcps1 imm16 +is b_2431=0xd4 & excCode=5 & imm16 & excCode2=0 & ll=1 +{ + DCPSInstruction(1:2, imm16:2); +} + +# C6.2.111 DCPS2 page C6-1458 line 86856 MATCH xd4a00002/mask=xffe0001f +# CONSTRUCT xd4a00002/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd4a00002/mask=xffe0001f --status nodest + +:dcps2 imm16 +is b_2431=0xd4 & excCode=5 & imm16 & excCode2=0 & ll=2 +{ + DCPSInstruction(2:2, imm16:2); +} + +# C6.2.112 DCPS3 page C6-1459 line 86927 MATCH xd4a00003/mask=xffe0001f +# CONSTRUCT xd4a00003/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd4a00003/mask=xffe0001f --status nodest + +:dcps3 imm16 +is b_2431=0xd4 & excCode=5 & imm16 & excCode2=0 & ll=3 +{ + DCPSInstruction(3:2, imm16:2); +} + +# C6.2.114 DMB page C6-1461 line 87029 MATCH xd50330bf/mask=xfffff0ff +# CONSTRUCT xd50330bf/mask=xfffff3ff MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd50330bf/mask=xfffff3ff --status nodest + +:dmb CRm_CRx +is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CRm_CRx & CRm_32 & CRm_10=0 & Op2=5 & Rt=0x1f +{ + types:1 = 0x0; + domain:1 = CRm_32; + DataMemoryBarrier(domain, types); +} + +# C6.2.114 DMB page C6-1461 line 87029 MATCH xd50330bf/mask=xfffff0ff +# CONSTRUCT xd50330bf/mask=xfffff0ff MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd50330bf/mask=xfffff0ff --status nodest + +:dmb CRm_dbarrier_op +is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CRm_32 & CRm_10 & Op2=5 & Rt=0x1f +{ + types:1 = CRm_10; + domain:1 = CRm_32; + DataMemoryBarrier(domain, types); +} + +# C6.2.115 DRPS page C6-1463 line 87125 MATCH xd6bf03e0/mask=xffffffff +# CONSTRUCT xd6bf03e0/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd6bf03e0/mask=xffffffff --status nodest + +:drps +is b_2531=0x6b & b_2324=1 & b_2122=1 & b_1620=0x1f & b_1015=0 & aa_Xn=31 & b_0004=0 +{ + pc = DRPSInstruction(); + return [pc]; +} + +# C6.2.116 DSB page C6-1464 line 87160 MATCH xd503309f/mask=xfffff0ff +# C6.2.252 PSSBB page C6-1727 line 101951 MATCH xd503349f/mask=xffffffff +# C6.2.290 SSBB page C6-1810 line 106930 MATCH xd503309f/mask=xffffffff +# CONSTRUCT xd503309f/mask=xfffff3ff MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst xd503309f/mask=xfffff3ff --status nodest + +:dsb CRm_CRx +is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CRm_CRx & CRm_32 & CRm_10=0 & Op2=4 & Rt=0x1f +{ + types:1 = 0x0; + domain:1 = CRm_32; + DataSynchronizationBarrier(domain, types); +} + +# C6.2.116 DSB page C6-1464 line 87160 MATCH xd503309f/mask=xfffff0ff +# CONSTRUCT xd503309f/mask=xfffff0ff MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd503309f/mask=xfffff0ff --status nodest + +:dsb CRm_dbarrier_op +is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CRm_32 & CRm_10=2 & Op2=4 & Rt=0x1f +{ + types:1 = 0x3; #MBReqTypes_All + domain:1 = CRm_32; + DataSynchronizationBarrier(domain, types); +} + +# C6.2.116 DSB page C6-1464 line 87160 MATCH xd503323f/mask=xfffff3ff +# CONSTRUCT xd503323f/mask=xfffff3ff MATCHED 1 DOCUMENTED OPCODES +# xd503323f/mask=xfffff3ff NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=11010101000000110011..1000111111 + +:dsb CRm_32 +is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CRm_32 & CRm_10 & Op2=1 & Rt=0x1f +{ + types:1 = CRm_10; + domain:1 = CRm_32; + DataSynchronizationBarrier(domain, types); +} + +# C6.2.118 EON (shifted register) page C6-1468 line 87407 MATCH x4a200000/mask=x7f200000 +# CONSTRUCT x4a200000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x4a200000/mask=xff200000 --status pass + +:eon Rd_GPR32, Rn_GPR32, RegShift32Log +is sf=0 & opc=2 & b_2428=0xa & N=1 & RegShift32Log & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp_3:4 = RegShift32Log; + tmp_2:4 = tmp_3 ^ -1:4; + tmp_1:4 = Rn_GPR32 ^ tmp_2; + Rd_GPR64 = zext(tmp_1); +} + +# C6.2.118 EON (shifted register) page C6-1468 line 87407 MATCH x4a200000/mask=x7f200000 +# CONSTRUCT xca200000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xca200000/mask=xff200000 --status pass + +:eon Rd_GPR64, Rn_GPR64, RegShift64Log +is sf=1 & opc=2 & b_2428=0xa & N=1 & Rm_GPR64 & RegShift64Log & Rn_GPR64 & Rd_GPR64 +{ + tmp_3:8= RegShift64Log; + tmp_2:8 = tmp_3 ^ -1:8; + tmp_1:8 = Rn_GPR64 ^ tmp_2; + Rd_GPR64 = tmp_1; +} + +# C6.2.119 EOR (immediate) page C6-1470 line 87512 MATCH x52000000/mask=x7f800000 +# CONSTRUCT x52000000/mask=xff800000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x52000000/mask=xff800000 --status pass + +:eor Rd_GPR32wsp, Rn_GPR32, DecodeWMask32 +is sf=0 & opc=2 & b_2428=0x12 & b_2323=0 & DecodeWMask32 & Rn_GPR32 & Rd_GPR32wsp & Rd_GPR64xsp +{ + tmp_1:4 = Rn_GPR32 ^ DecodeWMask32; + Rd_GPR64xsp = zext(tmp_1); +} + +# C6.2.119 EOR (immediate) page C6-1470 line 87512 MATCH x52000000/mask=x7f800000 +# CONSTRUCT xd2000000/mask=xff800000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd2000000/mask=xff800000 --status pass + +:eor Rd_GPR64xsp, Rn_GPR64, DecodeWMask64 +is sf=1 & opc=2 & b_2428=0x12 & b_2323=0 & DecodeWMask64 & Rn_GPR64 & Rd_GPR64xsp +{ + tmp_1:8 = Rn_GPR64 ^ DecodeWMask64; + Rd_GPR64xsp = tmp_1; +} + +# C6.2.120 EOR (shifted register) page C6-1472 line 87604 MATCH x4a000000/mask=x7f200000 +# CONSTRUCT x4a000000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x4a000000/mask=xff200000 --status pass + +:eor Rd_GPR32, Rn_GPR32, RegShift32Log +is sf=0 & opc=2 & b_2428=0xa & N=0 & RegShift32Log & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp_2:4 = RegShift32Log; + tmp_1:4 = Rn_GPR32 ^ tmp_2; + Rd_GPR64 = zext(tmp_1); +} + +# C6.2.120 EOR (shifted register) page C6-1472 line 87604 MATCH x4a000000/mask=x7f200000 +# CONSTRUCT xca000000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xca000000/mask=xff200000 --status pass + +:eor Rd_GPR64, Rn_GPR64, RegShift64Log +is sf=1 & opc=2 & b_2428=0xa & N=0 & Rm_GPR64 & RegShift64Log & Rn_GPR64 & Rd_GPR64 +{ + tmp_2:8 = RegShift64Log; + tmp_1:8 = Rn_GPR64 ^ tmp_2; + Rd_GPR64 = tmp_1; +} + +# C6.2.121 ERET page C6-1474 line 87707 MATCH xd69f03e0/mask=xffffffff +# CONSTRUCT xd69f03e0/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd69f03e0/mask=xffffffff --status nodest + +:eret +is b_2531=0x6b & b_2324=1 & b_2122=0 & b_1620=0x1f & b_1015=0 & aa_Xn=31 & b_0004=0 +{ + pc = ExceptionReturn(); + return [pc]; +} + +# C6.2.122 ERETAA, ERETAB page C6-1475 line 87749 MATCH xd69f0bff/mask=xfffffbff +# CONSTRUCT xd69f0bff/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd69f0bff/mask=xffffffff --status nodest + +:eretaa +is eretaa__PACpart & b_0031=0xd69f0bff +{ + pc = ExceptionReturn(); + build eretaa__PACpart; + return [pc]; +} + +# C6.2.122 ERETAA, ERETAB page C6-1475 line 87749 MATCH xd69f0bff/mask=xfffffbff +# CONSTRUCT xd69f0fff/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd69f0fff/mask=xffffffff --status nodest + +:eretab +is eretab__PACpart & b_0031=0xd69f0fff +{ + pc = ExceptionReturn(); + build eretab__PACpart; + return [pc]; +} + +# C6.2.124 EXTR page C6-1477 line 87864 MATCH x13800000/mask=x7fa00000 +# C6.2.261 ROR (immediate) page C6-1740 line 102633 MATCH x13800000/mask=x7fa00000 +# CONSTRUCT x13800000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x13800000/mask=xffe00000 --status pass + +:extr Rd_GPR32, Rn_GPR32, Rm_GPR32, LSB_bitfield32_imm +is sf=0 & b_2930=0 & b_2428=0x13 & b_2323=1 & n=0 & b_21=0 & Rm_GPR32 & LSB_bitfield32_imm & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + lsb:8 = LSB_bitfield32_imm; + result:8 = (zext(Rn_GPR32) << 32) | zext(Rm_GPR32); + result = (result >> lsb); + Rd_GPR64 = zext(result:4); +} + +# C6.2.124 EXTR page C6-1477 line 87864 MATCH x13800000/mask=x7fa00000 +# C6.2.261 ROR (immediate) page C6-1740 line 102633 MATCH x13800000/mask=x7fa00000 +# CONSTRUCT x93c00000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x93c00000/mask=xffe00000 --status pass + +:extr Rd_GPR64, Rn_GPR64, Rm_GPR64, LSB_bitfield64_imm +is sf=1 & b_2930=0 & b_2428=0x13 & b_2323=1 & n=1 & b_21=0 & Rm_GPR64 & LSB_bitfield64_imm & Rn_GPR64 & Rd_GPR64 +{ + local tmp:8 = (Rm_GPR64 >> LSB_bitfield64_imm:1); + Rd_GPR64 = tmp | (Rn_GPR64 << (64:1 - LSB_bitfield64_imm:1)); +} + +# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f +# C6.2.22 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA page C6-1183 line 69908 MATCH xd503219f/mask=xfffffddf +# C6.2.23 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB page C6-1186 line 70065 MATCH xd50321df/mask=xfffffddf +# C6.2.102 CSDB page C6-1442 line 86066 MATCH xd503229f/mask=xffffffff +# C6.2.113 DGH page C6-1460 line 86992 MATCH xd50320df/mask=xffffffff +# C6.2.123 ESB page C6-1476 line 87816 MATCH xd503221f/mask=xffffffff +# C6.2.245 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA page C6-1712 line 101196 MATCH xd503211f/mask=xfffffddf +# C6.2.246 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB page C6-1715 line 101358 MATCH xd503215f/mask=xfffffddf +# C6.2.251 PSB CSYNC page C6-1726 line 101911 MATCH xd503223f/mask=xffffffff +# C6.2.381 TSB CSYNC page C6-1982 line 116218 MATCH xd503225f/mask=xffffffff +# CONSTRUCT xd503201f/mask=xfffff01f MATCHED 10 DOCUMENTED OPCODES +# AUNIT --inst xd503201f/mask=xfffff01f --status nodest + +:hint imm7Low +is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low & Rt=0x1f {} + +# C6.2.127 HLT page C6-1482 line 88176 MATCH xd4400000/mask=xffe0001f +# CONSTRUCT xd4400000/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd4400000/mask=xffe0001f --status nodest + +:hlt imm16 +is ALL_BTITARGETS & b_2431=0xd4 & excCode=2 & imm16 & excCode2=0 & ll=0 +{ + HaltBreakPoint(); +} + +# C6.2.128 HVC page C6-1483 line 88218 MATCH xd4000002/mask=xffe0001f +# CONSTRUCT xd4000002/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd4000002/mask=xffe0001f --status nodest + +:hvc imm16 +is b_2431=0xd4 & excCode=0 & imm16 & excCode2=0 & ll=2 +{ + CallHyperVisor(imm16:2); +} + +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5087100/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst xd5087100/mask=xffffffe0 --status nodest + +:ic "IALLUIS" +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b0001 & b_0507=0b000 +{ IC_IALLUIS(); } + +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5087500/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst xd5087500/mask=xffffffe0 --status nodest + +:ic "IALLU" +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b0101 & b_0507=0b000 +{ IC_IALLU(); } + +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50b7520/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst xd50b7520/mask=xffffffe0 --status nopcodeop + +:ic "IVAU", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b0101 & b_0507=0b001 & Rt_GPR64 +{ IC_IVAU(Rt_GPR64); } + +# C6.2.85 ISB page C6-647 line 37682 KEEPWITH + +IsbOption: "#"^CRm_isb_op is CRm_isb_op { export *[const]:4 CRm_isb_op; } +IsbOption: "" is CRm_isb_op=0xf { tmp:4 = 0xf; export tmp; } + +# C6.2.131 ISB page C6-1487 line 88428 MATCH xd50330df/mask=xfffff0ff +# CONSTRUCT xd50330df/mask=xfffff0ff MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd50330df/mask=xfffff0ff --status nodest + +:isb IsbOption +is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & IsbOption & Op2=6 & Rt=0x1f +{ + InstructionSynchronizationBarrier(); +} + +# C6.2.86 LDADDB, LDADDAB, LDADDALB, LDADDLB page C6-648 line 37726 KEEPWITH + +# variants, a=acquire, al=acquire+release, l=release +# build ls_loa to acquire and ls_lor to release + +ls_loa: "a" is b_23=1 & b_22=0 { LOAcquire(); } +ls_loa: "al" is b_23=1 & b_22=1 { LOAcquire(); } +ls_loa: "" is b_23=0 & b_22=0 { } +ls_loa: "l" is b_23=0 & b_22=1 { } + +ls_lor: "a" is b_23=1 & b_22=0 { } +ls_lor: "al" is b_23=1 & b_22=1 { LORelease(); } +ls_lor: "" is b_23=0 & b_22=0 { } +ls_lor: "l" is b_23=0 & b_22=1 { LORelease(); } + +ls_data1: is b_3031=0b00 & Rn_GPR64xsp { tmp_ldWn = zext(*:1 Rn_GPR64xsp); } +ls_data2: is b_3031=0b01 & Rn_GPR64xsp { tmp_ldWn = zext(*:2 Rn_GPR64xsp); } +ls_data4: is b_3031=0b10 & Rn_GPR64xsp { tmp_ldWn = *:4 Rn_GPR64xsp; } +ls_data8: is b_3031=0b11 & Rn_GPR64xsp { tmp_ldXn = *:8 Rn_GPR64xsp; } + +ls_mem1: is Rn_GPR64xsp { *:1 Rn_GPR64xsp = tmp_stWn:1; } +ls_mem2: is Rn_GPR64xsp { *:2 Rn_GPR64xsp = tmp_stWn:2; } +ls_mem4: is Rn_GPR64xsp { *:4 Rn_GPR64xsp = tmp_stWn; } +ls_mem8: is Rn_GPR64xsp { *:8 Rn_GPR64xsp = tmp_stXn; } + +macro ls_opc_add (data, value, dest) { dest = data + value; } +macro ls_opc_clr (data, value, dest) { dest = data & (~ value); } +macro ls_opc_eor (data, value, dest) { dest = data ^ value; } +macro ls_opc_set (data, value, dest) { dest = data | value; } +macro ls_opc_smax(data, value, dest) { dest = zext(data s> value) * data + zext(data s<= value) * value; } +macro ls_opc_smin(data, value, dest) { dest = zext(data s> value) * value + zext(data s<= value) * data; } +macro ls_opc_umax(data, value, dest) { dest = zext(data > value) * data + zext(data <= value) * value; } +macro ls_opc_umin(data, value, dest) { dest = zext(data > value) * value + zext(data <= value) * data; } +macro ls_opc_swp (data, value, dest) { dest = value; } + +ls_opc1: "add" is b_3031=0b00 & b_1215=0b0000 & aa_Ws & ls_data1 & ls_mem1 { build ls_data1; ls_opc_add(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; } +ls_opc2: "add" is b_3031=0b01 & b_1215=0b0000 & aa_Ws & ls_data2 & ls_mem2 { build ls_data2; ls_opc_add(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; } +ls_opc4: "add" is b_3031=0b10 & b_1215=0b0000 & aa_Ws & ls_data4 & ls_mem4 { build ls_data4; ls_opc_add(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; } +ls_opc8: "add" is b_3031=0b11 & b_1215=0b0000 & aa_Xs & ls_data8 & ls_mem8 { build ls_data8; ls_opc_add(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; } + +ls_opc1: "clr" is b_3031=0b00 & b_1215=0b0001 & aa_Ws & ls_data1 & ls_mem1 { build ls_data1; ls_opc_clr(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; } +ls_opc2: "clr" is b_3031=0b01 & b_1215=0b0001 & aa_Ws & ls_data2 & ls_mem2 { build ls_data2; ls_opc_clr(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; } +ls_opc4: "clr" is b_3031=0b10 & b_1215=0b0001 & aa_Ws & ls_data4 & ls_mem4 { build ls_data4; ls_opc_clr(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; } +ls_opc8: "clr" is b_3031=0b11 & b_1215=0b0001 & aa_Xs & ls_data8 & ls_mem8 { build ls_data8; ls_opc_clr(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; } + +ls_opc1: "eor" is b_3031=0b00 & b_1215=0b0010 & aa_Ws & ls_data1 & ls_mem1 { build ls_data1; ls_opc_eor(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; } +ls_opc2: "eor" is b_3031=0b01 & b_1215=0b0010 & aa_Ws & ls_data2 & ls_mem2 { build ls_data2; ls_opc_eor(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; } +ls_opc4: "eor" is b_3031=0b10 & b_1215=0b0010 & aa_Ws & ls_data4 & ls_mem4 { build ls_data4; ls_opc_eor(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; } +ls_opc8: "eor" is b_3031=0b11 & b_1215=0b0010 & aa_Xs & ls_data8 & ls_mem8 { build ls_data8; ls_opc_eor(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; } + +ls_opc1: "set" is b_3031=0b00 & b_1215=0b0011 & aa_Ws & ls_data1 & ls_mem1 { build ls_data1; ls_opc_set(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; } +ls_opc2: "set" is b_3031=0b01 & b_1215=0b0011 & aa_Ws & ls_data2 & ls_mem2 { build ls_data2; ls_opc_set(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; } +ls_opc4: "set" is b_3031=0b10 & b_1215=0b0011 & aa_Ws & ls_data4 & ls_mem4 { build ls_data4; ls_opc_set(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; } +ls_opc8: "set" is b_3031=0b11 & b_1215=0b0011 & aa_Xs & ls_data8 & ls_mem8 { build ls_data8; ls_opc_set(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; } + +ls_opc1: "smax" is b_3031=0b00 & b_1215=0b0100 & aa_Ws & ls_data1 & ls_mem1 { build ls_data1; ls_opc_smax(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; } +ls_opc2: "smax" is b_3031=0b01 & b_1215=0b0100 & aa_Ws & ls_data2 & ls_mem2 { build ls_data2; ls_opc_smax(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; } +ls_opc4: "smax" is b_3031=0b10 & b_1215=0b0100 & aa_Ws & ls_data4 & ls_mem4 { build ls_data4; ls_opc_smax(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; } +ls_opc8: "smax" is b_3031=0b11 & b_1215=0b0100 & aa_Xs & ls_data8 & ls_mem8 { build ls_data8; ls_opc_smax(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; } + +ls_opc1: "smin" is b_3031=0b00 & b_1215=0b0101 & aa_Ws & ls_data1 & ls_mem1 { build ls_data1; ls_opc_smin(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; } +ls_opc2: "smin" is b_3031=0b01 & b_1215=0b0101 & aa_Ws & ls_data2 & ls_mem2 { build ls_data2; ls_opc_smin(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; } +ls_opc4: "smin" is b_3031=0b10 & b_1215=0b0101 & aa_Ws & ls_data4 & ls_mem4 { build ls_data4; ls_opc_smin(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; } +ls_opc8: "smin" is b_3031=0b11 & b_1215=0b0101 & aa_Xs & ls_data8 & ls_mem8 { build ls_data8; ls_opc_smin(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; } + +ls_opc1: "umax" is b_3031=0b00 & b_1215=0b0110 & aa_Ws & ls_data1 & ls_mem1 { build ls_data1; ls_opc_umax(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; } +ls_opc2: "umax" is b_3031=0b01 & b_1215=0b0110 & aa_Ws & ls_data2 & ls_mem2 { build ls_data2; ls_opc_umax(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; } +ls_opc4: "umax" is b_3031=0b10 & b_1215=0b0110 & aa_Ws & ls_data4 & ls_mem4 { build ls_data4; ls_opc_umax(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; } +ls_opc8: "umax" is b_3031=0b11 & b_1215=0b0110 & aa_Xs & ls_data8 & ls_mem8 { build ls_data8; ls_opc_umax(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; } + +ls_opc1: "umin" is b_3031=0b00 & b_1215=0b0111 & aa_Ws & ls_data1 & ls_mem1 { build ls_data1; ls_opc_umin(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; } +ls_opc2: "umin" is b_3031=0b01 & b_1215=0b0111 & aa_Ws & ls_data2 & ls_mem2 { build ls_data2; ls_opc_umin(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; } +ls_opc4: "umin" is b_3031=0b10 & b_1215=0b0111 & aa_Ws & ls_data4 & ls_mem4 { build ls_data4; ls_opc_umin(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; } +ls_opc8: "umin" is b_3031=0b11 & b_1215=0b0111 & aa_Xs & ls_data8 & ls_mem8 { build ls_data8; ls_opc_umin(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; } + +# Nearly all of these instructions have the same "operation" in the +# manual, the differences being load vs store, the operation (o3:opc), +# the data size, and the load store semantics of the atomic load and +# store types (AccType). The opcode mnemonic varies, however. And to +# facilitate reading, the LD/ST/SWP variants have been separated out. + +# C6.2.133 LDADDB, LDADDAB, LDADDALB, LDADDLB page C6-1489 line 88545 MATCH x38200000/mask=xff20fc00 +# C6.2.152 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB page C6-1524 line 90495 MATCH x38201000/mask=xff20fc00 +# C6.2.155 LDEORB, LDEORAB, LDEORALB, LDEORLB page C6-1531 line 90916 MATCH x38202000/mask=xff20fc00 +# C6.2.181 LDSETB, LDSETAB, LDSETALB, LDSETLB page C6-1590 line 94403 MATCH x38203000/mask=xff20fc00 +# C6.2.184 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB page C6-1597 line 94824 MATCH x38204000/mask=xff20fc00 +# C6.2.187 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB page C6-1604 line 95245 MATCH x38205000/mask=xff20fc00 +# C6.2.196 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB page C6-1623 line 96362 MATCH x38206000/mask=xff20fc00 +# C6.2.199 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB page C6-1630 line 96783 MATCH x38207000/mask=xff20fc00 +# CONSTRUCT x38200000/mask=xff208c00 MATCHED 8 DOCUMENTED OPCODES +# AUNIT --inst x38200000/mask=xff208c00 --status nomem + +# size=0b00 (3031) + +:ld^ls_opc1^ls_lor^"b" aa_Ws, aa_Wt, [Rn_GPR64xsp] +is b_3031=0b00 & b_2429=0b111000 & b_21=1 & b_1515=0 & b_1011=0b00 & ls_opc1 & ls_loa & ls_lor & aa_Wt & aa_Ws & Rn_GPR64xsp +{ build ls_loa; build ls_opc1; aa_Wt = tmp_ldWn; build ls_lor; } + +# C6.2.134 LDADDH, LDADDAH, LDADDALH, LDADDLH page C6-1491 line 88670 MATCH x78200000/mask=xff20fc00 +# C6.2.153 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH page C6-1526 line 90621 MATCH x78201000/mask=xff20fc00 +# C6.2.156 LDEORH, LDEORAH, LDEORALH, LDEORLH page C6-1533 line 91042 MATCH x78202000/mask=xff20fc00 +# C6.2.182 LDSETH, LDSETAH, LDSETALH, LDSETLH page C6-1592 line 94529 MATCH x78203000/mask=xff20fc00 +# C6.2.185 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH page C6-1599 line 94950 MATCH x78204000/mask=xff20fc00 +# C6.2.188 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH page C6-1606 line 95371 MATCH x78205000/mask=xff20fc00 +# C6.2.197 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH page C6-1625 line 96488 MATCH x78206000/mask=xff20fc00 +# C6.2.200 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH page C6-1632 line 96909 MATCH x78207000/mask=xff20fc00 +# CONSTRUCT x78200000/mask=xff208c00 MATCHED 8 DOCUMENTED OPCODES +# AUNIT --inst x78200000/mask=xff208c00 --status nomem + +# size=0b01 (3031) + +:ld^ls_opc2^ls_lor^"h" aa_Ws, aa_Wt, [Rn_GPR64xsp] +is b_3031=0b01 & b_2429=0b111000 & b_21=1 & b_1515=0 & b_1011=0b00 & ls_opc2 & ls_loa & ls_lor & aa_Wt & aa_Ws & Rn_GPR64xsp +{ build ls_loa; build ls_opc2; aa_Wt = tmp_ldWn; build ls_lor; } + +# C6.2.135 LDADD, LDADDA, LDADDAL, LDADDL page C6-1493 line 88796 MATCH xb8200000/mask=xbf20fc00 +# C6.2.154 LDCLR, LDCLRA, LDCLRAL, LDCLRL page C6-1528 line 90747 MATCH xb8201000/mask=xbf20fc00 +# C6.2.157 LDEOR, LDEORA, LDEORAL, LDEORL page C6-1535 line 91168 MATCH xb8202000/mask=xbf20fc00 +# C6.2.183 LDSET, LDSETA, LDSETAL, LDSETL page C6-1594 line 94655 MATCH xb8203000/mask=xbf20fc00 +# C6.2.186 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL page C6-1601 line 95076 MATCH xb8204000/mask=xbf20fc00 +# C6.2.189 LDSMIN, LDSMINA, LDSMINAL, LDSMINL page C6-1608 line 95497 MATCH xb8205000/mask=xbf20fc00 +# C6.2.198 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL page C6-1627 line 96614 MATCH xb8206000/mask=xbf20fc00 +# C6.2.201 LDUMIN, LDUMINA, LDUMINAL, LDUMINL page C6-1634 line 97035 MATCH xb8207000/mask=xbf20fc00 +# C6.2.297 STADD, STADDL page C6-1822 line 107555 MATCH xb820001f/mask=xbfa0fc1f +# C6.2.300 STCLR, STCLRL page C6-1828 line 107842 MATCH xb820101f/mask=xbfa0fc1f +# C6.2.303 STEOR, STEORL page C6-1834 line 108128 MATCH xb820201f/mask=xbfa0fc1f +# C6.2.330 STSET, STSETL page C6-1890 line 111216 MATCH xb820301f/mask=xbfa0fc1f +# C6.2.333 STSMAX, STSMAXL page C6-1896 line 111508 MATCH xb820401f/mask=xbfa0fc1f +# C6.2.336 STSMIN, STSMINL page C6-1902 line 111801 MATCH xb820501f/mask=xbfa0fc1f +# C6.2.342 STUMAX, STUMAXL page C6-1914 line 112409 MATCH xb820601f/mask=xbfa0fc1f +# C6.2.345 STUMIN, STUMINL page C6-1920 line 112703 MATCH xb820701f/mask=xbfa0fc1f +# CONSTRUCT xb8200000/mask=xff208c00 MATCHED 16 DOCUMENTED OPCODES +# AUNIT --inst xb8200000/mask=xff208c00 --status nomem + +# size=0b10 (3031) + +:ld^ls_opc4^ls_lor aa_Ws, aa_Wt, [Rn_GPR64xsp] +is b_3031=0b10 & b_2429=0b111000 & b_21=1 & b_1515=0 & b_1011=0b00 & ls_opc4 & ls_loa & ls_lor & aa_Wt & aa_Ws & Rn_GPR64xsp +{ build ls_loa; build ls_opc4; aa_Wt = tmp_ldWn; build ls_lor; } + +# C6.2.135 LDADD, LDADDA, LDADDAL, LDADDL page C6-1493 line 88796 MATCH xb8200000/mask=xbf20fc00 +# C6.2.154 LDCLR, LDCLRA, LDCLRAL, LDCLRL page C6-1528 line 90747 MATCH xb8201000/mask=xbf20fc00 +# C6.2.157 LDEOR, LDEORA, LDEORAL, LDEORL page C6-1535 line 91168 MATCH xb8202000/mask=xbf20fc00 +# C6.2.183 LDSET, LDSETA, LDSETAL, LDSETL page C6-1594 line 94655 MATCH xb8203000/mask=xbf20fc00 +# C6.2.186 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL page C6-1601 line 95076 MATCH xb8204000/mask=xbf20fc00 +# C6.2.189 LDSMIN, LDSMINA, LDSMINAL, LDSMINL page C6-1608 line 95497 MATCH xb8205000/mask=xbf20fc00 +# C6.2.198 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL page C6-1627 line 96614 MATCH xb8206000/mask=xbf20fc00 +# C6.2.201 LDUMIN, LDUMINA, LDUMINAL, LDUMINL page C6-1634 line 97035 MATCH xb8207000/mask=xbf20fc00 +# C6.2.297 STADD, STADDL page C6-1822 line 107555 MATCH xb820001f/mask=xbfa0fc1f +# C6.2.300 STCLR, STCLRL page C6-1828 line 107842 MATCH xb820101f/mask=xbfa0fc1f +# C6.2.303 STEOR, STEORL page C6-1834 line 108128 MATCH xb820201f/mask=xbfa0fc1f +# C6.2.330 STSET, STSETL page C6-1890 line 111216 MATCH xb820301f/mask=xbfa0fc1f +# C6.2.333 STSMAX, STSMAXL page C6-1896 line 111508 MATCH xb820401f/mask=xbfa0fc1f +# C6.2.336 STSMIN, STSMINL page C6-1902 line 111801 MATCH xb820501f/mask=xbfa0fc1f +# C6.2.342 STUMAX, STUMAXL page C6-1914 line 112409 MATCH xb820601f/mask=xbfa0fc1f +# C6.2.345 STUMIN, STUMINL page C6-1920 line 112703 MATCH xb820701f/mask=xbfa0fc1f +# CONSTRUCT xf8200000/mask=xff208c00 MATCHED 16 DOCUMENTED OPCODES +# AUNIT --inst xf8200000/mask=xff208c00 --status nomem + +# size=0b11 (3031) + +:ld^ls_opc8^ls_lor aa_Xs, aa_Xt, [Rn_GPR64xsp] +is b_3031=0b11 & b_2429=0b111000 & b_21=1 & b_1515=0 & b_1011=0b00 & ls_opc8 & ls_loa & ls_lor & aa_Xt & aa_Xs & Rn_GPR64xsp +{ build ls_loa; build ls_opc8; aa_Xt = tmp_ldXn; build ls_lor; } + +# C6.2.136 LDAPR page C6-1496 line 88965 MATCH xb8a0c000/mask=xbfe0fc00 +# CONSTRUCT xb8a0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xb8a0c000/mask=xffe0fc00 --status nomem +# TODO unsure of load/release semantics for this instruction +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 +# size == 10 32-bit variant + +:ldapr aa_Wt, [Rn_GPR64xsp] +is b_3031=0b10 & b_2129=0b111000101 & b_1015=0b110000 & Rn_GPR64xsp & aa_Wt & ls_data4 +{ + aa_Wt = tmp_ldWn; +} + +# C6.2.136 LDAPR page C6-1496 line 88965 MATCH xb8a0c000/mask=xbfe0fc00 +# CONSTRUCT xf8a0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xf8a0c000/mask=xffe0fc00 --status nomem +# TODO unsure of load/release semantics for this instruction +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 +# size == 11 64-bit variant + +:ldapr aa_Xt, [Rn_GPR64xsp] +is b_3031=0b11 & b_2129=0b111000101 & b_1015=0b110000 & Rn_GPR64xsp & aa_Xt +{ + aa_Xt = tmp_ldXn; +} + +# C6.2.137 LDAPRB page C6-1498 line 89064 MATCH x38a0c000/mask=xffe0fc00 +# CONSTRUCT x38a0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x38a0c000/mask=xffe0fc00 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 +# TODO unsure of load/release semantics for this instruction + +:ldaprb aa_Wt, [Rn_GPR64xsp] +is b_3031=0b00 & b_2129=0b111000101 & b_1015=0b110000 & Rn_GPR64xsp & aa_Wt & ls_data1 +{ + aa_Wt = tmp_ldWn; +} + +# C6.2.138 LDAPRH page C6-1500 line 89148 MATCH x78a0c000/mask=xffe0fc00 +# CONSTRUCT x78a0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x78a0c000/mask=xffe0fc00 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 + +:ldaprh aa_Wt, [Rn_GPR64xsp] +is b_3031=0b01 & b_2129=0b111000101 & b_1015=0b110000 & Rn_GPR64xsp & aa_Wt & ls_data2 +{ + aa_Wt = tmp_ldWn; +} + + +# C6.2.139 LDAPUR page C6-1502 line 89232 MATCH x99400000/mask=xbfe00c00 +# CONSTRUCT x99400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# The following commands are not yet implemented. + + +# x99400000/mask=xbfe00c00 NOT MATCHED BY ANY CONSTRUCTOR + +:ldapur aa_Wt, addr_SIMM9 +is b_3031=0b10 & b_2129=0b011001010 & b_1011=0b00 & addr_SIMM9 & aa_Wt & aa_Xt +{ + aa_Xt = zext(*:4 addr_SIMM9); +} + +# C6.2.139 LDAPUR page C6-1502 line 89232 MATCH x99400000/mask=xbfe00c00 +# CONSTRUCT xd9400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES + +:ldapur aa_Xt, addr_SIMM9 +is b_3031=0b11 & b_2129=0b011001010 & b_1011=0b00 & addr_SIMM9 & aa_Xt +{ + aa_Xt = *addr_SIMM9; +} + +# C6.2.140 LDAPURB page C6-1504 line 89343 MATCH x19400000/mask=xffe00c00 +# CONSTRUCT x19400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# x19400000/mask=xffe00c00 NOT MATCHED BY ANY CONSTRUCTOR + +:ldapurb aa_Wt, addr_SIMM9 +is b_3031=0b00 & b_2129=0b011001010 & b_1011=0b00 & addr_SIMM9 & aa_Wt & aa_Xt +{ + aa_Xt = zext(*:1 addr_SIMM9); +} + +# C6.2.141 LDAPURH page C6-1506 line 89439 MATCH x59400000/mask=xffe00c00 +# CONSTRUCT x59400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# x59400000/mask=xffe00c00 NOT MATCHED BY ANY CONSTRUCTOR + +:ldapurh aa_Wt, addr_SIMM9 +is b_3031=0b01 & b_2129=0b011001010 & b_1011=0b00 & addr_SIMM9 & aa_Wt & aa_Xt +{ + aa_Xt = zext(*:2 addr_SIMM9); +} + + +# C6.2.142 LDAPURSB page C6-1508 line 89535 MATCH x19800000/mask=xffa00c00 +# CONSTRUCT x19c00000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# x19800000/mask=xffa00c00 NOT MATCHED BY ANY CONSTRUCTOR + +:ldapursb aa_Wt, addr_SIMM9 +is b_3031=0b00 & b_2329=0b0110011 & b_22=1 & b_2121=0b0 & b_1011=0b00 & addr_SIMM9 & aa_Wt & aa_Xt +{ + aa_Xt = 0; + aa_Wt = sext(*:1 addr_SIMM9); +} + +# C6.2.142 LDAPURSB page C6-1508 line 89535 MATCH x19800000/mask=xffa00c00 +# CONSTRUCT x19800000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES + +:ldapursb aa_Xt, addr_SIMM9 +is b_3031=0b00 & b_2329=0b0110011 & b_22=0 & b_2121=0b0 & b_1011=0b00 & addr_SIMM9 & aa_Xt +{ + aa_Xt = sext(*:1 addr_SIMM9); +} + +# C6.2.143 LDAPURSH page C6-1510 line 89667 MATCH x59800000/mask=xffa00c00 +# CONSTRUCT x59c00000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# x59800000/mask=xffa00c00 NOT MATCHED BY ANY CONSTRUCTOR + +:ldapursh aa_Wt, addr_SIMM9 +is b_3031=0b01 & b_2329=0b0110011 & b_22=1 & b_2121=0b0 & b_1011=0b00 & addr_SIMM9 & aa_Wt & aa_Xt +{ + aa_Xt = 0; + aa_Wt = sext(*:2 addr_SIMM9); +} + +# C6.2.143 LDAPURSH page C6-1510 line 89667 MATCH x59800000/mask=xffa00c00 +# CONSTRUCT x59800000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES + +:ldapursh aa_Xt, addr_SIMM9 +is b_3031=0b01 & b_2329=0b0110011 & b_22=0 & b_2121=0b0 & b_1011=0b00 & addr_SIMM9 & aa_Xt +{ + aa_Xt = sext(*:2 addr_SIMM9); +} + +# C6.2.144 LDAPURSW page C6-1512 line 89799 MATCH x99800000/mask=xffe00c00 +# CONSTRUCT x99800000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# x99800000/mask=xffe00c00 NOT MATCHED BY ANY CONSTRUCTOR + +:ldapursw aa_Xt, addr_SIMM9 +is b_3031=0b10 & b_2129=0b011001100 & b_1011=0b00 & addr_SIMM9 & aa_Xt +{ + aa_Xt = sext(*:4 addr_SIMM9); +} + +# C6.2.145 LDAR page C6-1514 line 89895 MATCH x88c08000/mask=xbfe08000 +# CONSTRUCT xc8c08000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xc8c08000/mask=xffe08000 --status nomem +# The manual states that Rs and Rt2 should be all ones, which is +# optionally enforced. +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111 + +:ldar Rt_GPR64, addrReg +is size.ldstr=3 & b_2429=0x8 & b_23=1 & L=1 & b_21=0 & b_15=1 & addrReg & Rt_GPR64 +{ + Rt_GPR64 = *addrReg; +} + +# C6.2.145 LDAR page C6-1514 line 89895 MATCH x88c08000/mask=xbfe08000 +# CONSTRUCT x88dffc00/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x88dffc00/mask=xfffffc00 --status nomem +# Enforce SHOULD BE ONE fields b_1620 & b_1014 + +:ldar Rt_GPR32, addrReg +is size.ldstr=2 & b_2429=0x8 & b_23=1 & L=1 & b_21=0 & b_1620=0b11111 & b_15=1 & b_1014=0b11111 & addrReg & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = *addrReg; +} + +# C6.2.146 LDARB page C6-1516 line 89986 MATCH x08c08000/mask=xffe08000 +# CONSTRUCT x08c08000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x08c08000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111 + +:ldarb Rt_GPR32, addrReg +is size.ldstr=0 & b_2429=0x8 & b_23=1 & L=1 & b_21=0 & b_15=1 & addrReg & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = zext(*:1 addrReg); +} + +# C6.2.147 LDARH page C6-1517 line 90054 MATCH x48c08000/mask=xffe08000 +# CONSTRUCT x48dffc00/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x48dffc00/mask=xfffffc00 --status nomem +# Enforce SHOULD BE ONE fields b_1620 & b_1014 + +:ldarh Rt_GPR32, addrReg +is size.ldstr=1 & b_2429=0x8 & b_23=1 & L=1 & b_21=0 & b_1620=0b11111 & b_15=1 & b_1014=0b11111 & addrReg & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = zext(*:2 addrReg); +} + +# C6.2.148 LDAXP page C6-1518 line 90122 MATCH x88608000/mask=xbfe08000 +# CONSTRUCT xc8608000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xc8608000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 + +:ldaxp Rt_GPR64, Rt2_GPR64, addrReg +is size.ldstr=3 & b_2429=0x8 & b_23=0 & L=1 & b_21=1 & b_15=1 & Rt2_GPR64 & addrReg & Rt_GPR64 +{ + Rt_GPR64 = *(addrReg); + Rt2_GPR64 = *(addrReg+8); +} + +# C6.2.148 LDAXP page C6-1518 line 90122 MATCH x88608000/mask=xbfe08000 +# CONSTRUCT x88608000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x88608000/mask=xffe08000 --status nomem + +:ldaxp Rt_GPR32, Rt2_GPR32, addrReg +is size.ldstr=2 & b_2429=0x8 & b_23=0 & L=1 & b_21=1 & b_1620 & b_15=1 & Rt2_GPR32 & addrReg & Rt_GPR32 & Rt_GPR64 & Rt2_GPR64 +{ + Rt_GPR64 = zext(*:4(addrReg)); + Rt2_GPR64 = zext(*:4(addrReg+4)); +} + +# C6.2.149 LDAXR page C6-1520 line 90256 MATCH x88408000/mask=xbfe08000 +# CONSTRUCT xc8408000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xc8408000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111 + +:ldaxr Rt_GPR64, addrReg +is size.ldstr=3 & b_2429=0x8 & b_23=0 & L=1 & b_21=0 & b_15=1 & addrReg & Rt_GPR64 +{ + Rt_GPR64 = *addrReg; +} + +# C6.2.149 LDAXR page C6-1520 line 90256 MATCH x88408000/mask=xbfe08000 +# CONSTRUCT x88408000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x88408000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111 + +:ldaxr Rt_GPR32, addrReg +is size.ldstr=2 & b_2429=0x8 & b_23=0 & L=1 & b_21=0 & b_15=1 & addrReg & Rt_GPR32 & Rt_GPR64 +{ + tmp:4 = *addrReg; + Rt_GPR64 = zext(tmp); +} + +# C6.2.150 LDAXRB page C6-1522 line 90351 MATCH x08408000/mask=xffe08000 +# CONSTRUCT x08408000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x08408000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111 + +:ldaxrb Rt_GPR32, addrReg +is size.ldstr=0 & b_2429=0x8 & b_23=0 & L=1 & b_21=0 & b_15=1 & addrReg & Rt_GPR32 & Rt_GPR64 +{ + tmp:1 = *addrReg; + Rt_GPR64 = zext(tmp); +} + +# C6.2.151 LDAXRH page C6-1523 line 90423 MATCH x48408000/mask=xffe08000 +# CONSTRUCT x48408000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x48408000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111 + +:ldaxrh Rt_GPR32, addrReg +is size.ldstr=1 & b_2429=0x8 & b_23=0 & L=1 & b_21=0 & b_15=1 & addrReg & Rt_GPR32 & Rt_GPR64 +{ + tmp:2 = *addrReg; + Rt_GPR64 = zext(tmp); +} + +# C6.2.160 LDLARB page C6-1540 line 91472 MATCH x08c00000/mask=xffe08000 +# CONSTRUCT x08c00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x08c00000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111 +# size=0b00 (3031) + +:ldlarb aa_Wt, [Rn_GPR64xsp] +is b_3031=0b00 & b_2329=0b0010001 & b_22=1 & b_21=0 & b_15=0 & aa_Wt & Rn_GPR64xsp +{ LOAcquire(); aa_Wt = zext(*:1 Rn_GPR64xsp); } + +# C6.2.161 LDLARH page C6-1541 line 91541 MATCH x48c00000/mask=xffe08000 +# CONSTRUCT x48c00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x48c00000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111 +# size=0b01 (3031) + +:ldlarh aa_Wt, [Rn_GPR64xsp] +is b_3031=0b01 & b_2329=0b0010001 & b_22=1 & b_21=0 & b_15=0 & aa_Wt & Rn_GPR64xsp +{ LOAcquire(); aa_Wt = zext(*:2 Rn_GPR64xsp); } + +# C6.2.162 LDLAR page C6-1542 line 91610 MATCH x88c00000/mask=xbfe08000 +# CONSTRUCT x88c00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x88c00000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111 +# size=0b10 (3031) + +:ldlar aa_Wt, [Rn_GPR64xsp] +is b_3031=0b10 & b_2329=0b0010001 & b_22=1 & b_21=0 & b_15=0 & aa_Wt & Rn_GPR64xsp +{ LOAcquire(); aa_Wt = *:4 Rn_GPR64xsp; } + +# C6.2.162 LDLAR page C6-1542 line 91610 MATCH x88c00000/mask=xbfe08000 +# CONSTRUCT xc8c00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xc8c00000/mask=xffe08000 --status nomem +# size=0b11 (3031) + +:ldlar aa_Xt, [Rn_GPR64xsp] +is b_3031=0b11 & b_2329=0b0010001 & b_22=1 & b_21=0 & b_15=0 & aa_Xt & Rn_GPR64xsp +{ LOAcquire(); aa_Xt = *:8 Rn_GPR64xsp; } + +# C6.2.163 LDNP page C6-1544 line 91702 MATCH x28400000/mask=x7fc00000 +# CONSTRUCT x28400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x28400000/mask=xffc00000 --status nomem + +:ldnp Rt_GPR32, Rt2_GPR32, addrPairIndexed +is b_3031=0b00 & b_2229=0b10100001 & Rt2_GPR32 & addrPairIndexed & Rt_GPR32 & Rt_GPR64 & Rt2_GPR64 +{ + Rt_GPR64 = zext(*:4 addrPairIndexed); + Rt2_GPR64 = zext(*:4 (addrPairIndexed + 4)); +} + +# C6.2.163 LDNP page C6-1544 line 91702 MATCH x28400000/mask=x7fc00000 +# CONSTRUCT xa8400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xa8400000/mask=xffc00000 --status nomem + +:ldnp Rt_GPR64, Rt2_GPR64, addrPairIndexed +is b_3031=0b10 & b_2229=0b10100001 & Rt2_GPR64 & addrPairIndexed & Rt_GPR64 +{ + Rt_GPR64 = *addrPairIndexed; + Rt2_GPR64 = *(addrPairIndexed + 8); +} + +# C6.2.164 LDP page C6-1546 line 91841 MATCH x28c00000/mask=x7fc00000 +# C6.2.164 LDP page C6-1546 line 91841 MATCH x29c00000/mask=x7fc00000 +# C6.2.164 LDP page C6-1546 line 91841 MATCH x29400000/mask=x7fc00000 +# C6.2.163 LDNP page C6-1544 line 91702 MATCH x28400000/mask=x7fc00000 +# CONSTRUCT x28400000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst x28400000/mask=xfe400000 --status nomem +# opc == 00 post-index, pre-index, and signed 32-bit variant + +:ldp Rt_GPR32, Rt2_GPR32, addrPairIndexed +is b_3031=0b00 & b_2529=0b10100 & (b_24=1 | b_23=1) & b_22=1 & Rt2_GPR32 & addrPairIndexed & Rt_GPR32 & Rt_GPR64 & Rt2_GPR64 +{ + Rt_GPR64 = zext(*:4 addrPairIndexed); + Rt2_GPR64 = zext(*:4 (addrPairIndexed + 4)); +} + +# C6.2.164 LDP page C6-1546 line 91841 MATCH x28c00000/mask=x7fc00000 +# C6.2.164 LDP page C6-1546 line 91841 MATCH x29c00000/mask=x7fc00000 +# C6.2.164 LDP page C6-1546 line 91841 MATCH x29400000/mask=x7fc00000 +# C6.2.163 LDNP page C6-1544 line 91702 MATCH x28400000/mask=x7fc00000 +# CONSTRUCT xa8400000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst xa8400000/mask=xfe400000 --status nomem +# opc == 10 post-index, pre-index, and signed 64-bit variant + +:ldp Rt_GPR64, Rt2_GPR64, addrPairIndexed +is b_3031=0b10 & b_2529=0b10100 & (b_24=1 | b_23=1) & b_22=1 & Rt2_GPR64 & addrPairIndexed & Rt_GPR64 +{ + Rt_GPR64 = *addrPairIndexed; + Rt2_GPR64 = *(addrPairIndexed + 8); +} + +# C6.2.165 LDPSW page C6-1550 line 92077 MATCH x68c00000/mask=xffc00000 +# C6.2.165 LDPSW page C6-1550 line 92077 MATCH x69c00000/mask=xffc00000 +# C6.2.165 LDPSW page C6-1550 line 92077 MATCH x69400000/mask=xffc00000 +# CONSTRUCT x68400000/mask=xfe400000 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst x68400000/mask=xfe400000 --status nomem + +:ldpsw Rt_GPR64, Rt2_GPR64, addrPairIndexed +is b_2531=0b0110100 & (b_24=1 | b_23=1) & b_22=1 & Rt2_GPR64 & addrPairIndexed & Rt_GPR64 +{ + Rt_GPR64 = *(addrPairIndexed); + Rt2_GPR64 = *(addrPairIndexed+8); +} + +# C6.2.166 LDR (immediate) page C6-1553 line 92262 MATCH xb9400000/mask=xbfc00000 +# CONSTRUCT xb9400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xb9400000/mask=xffc00000 --status nomem + +:ldr Rt_GPR32, addrUIMM +is size.ldstr=2 & b_2729=7 & v=0 & b_2425=1 & b_23=0 & b_2222=1 & addrUIMM & Rn_GPR64xsp & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = zext(*:4 addrUIMM); +} + +# C6.2.166 LDR (immediate) page C6-1553 line 92262 MATCH xb8400400/mask=xbfe00c00 +# C6.2.166 LDR (immediate) page C6-1553 line 92262 MATCH xb8400c00/mask=xbfe00c00 +# C6.2.190 LDTR page C6-1611 line 95666 MATCH xb8400800/mask=xbfe00c00 +# C6.2.202 LDUR page C6-1637 line 97204 MATCH xb8400000/mask=xbfe00c00 +# CONSTRUCT xb8400000/mask=xffe00000 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst xb8400000/mask=xffe00000 --status nomem + +:ld^UnscPriv^"r" Rt_GPR32, addrIndexed +is size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = zext(*:4 addrIndexed); +} + +# C6.2.166 LDR (immediate) page C6-1553 line 92262 MATCH xb8400400/mask=xbfe00c00 +# C6.2.166 LDR (immediate) page C6-1553 line 92262 MATCH xb8400c00/mask=xbfe00c00 +# CONSTRUCT xb8400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xb8400400/mask=xffe00400 --status nomem + +:ldr Rt_GPR32, addrIndexed +is size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = zext(*:4 addrIndexed); +} + +# C6.2.166 LDR (immediate) page C6-1553 line 92262 MATCH xb9400000/mask=xbfc00000 +# CONSTRUCT xf9400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xf9400000/mask=xffc00000 --status nomem + +:ldr Rt_GPR64, addrUIMM +is size.ldstr=3 & b_2729=7 & v=0 & b_2425=1 & b_23=0 & b_2222=1 & addrUIMM & Rn_GPR64xsp & Rt_GPR64 +{ + Rt_GPR64 = *addrUIMM; +} + +# C6.2.166 LDR (immediate) page C6-1553 line 92262 MATCH xb8400400/mask=xbfe00c00 +# C6.2.166 LDR (immediate) page C6-1553 line 92262 MATCH xb8400c00/mask=xbfe00c00 +# CONSTRUCT xf8400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xf8400400/mask=xffe00400 --status nomem + +:ldr Rt_GPR64, addrIndexed +is size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR64 +{ + Rt_GPR64 = *addrIndexed; +} + +# C6.2.167 LDR (literal) page C6-1556 line 92457 MATCH x18000000/mask=xbf000000 +# CONSTRUCT x18000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x18000000/mask=xff000000 --status nomem + +:ldr Rt_GPR32, AddrLoc19 +is size.ldstr=0 & b_2729=3 & v=0 & b_2425=0 & AddrLoc19 & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = zext(*:4 AddrLoc19); +} + +# C6.2.167 LDR (literal) page C6-1556 line 92457 MATCH x18000000/mask=xbf000000 +# CONSTRUCT x58000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x58000000/mask=xff000000 --status nomem + +:ldr Rt_GPR64, AddrLoc19 +is size.ldstr=1 & b_2729=3 & v=0 & b_2425=0 & AddrLoc19 & Rt_GPR64 +{ + Rt_GPR64 = *:4 AddrLoc19; +} + +# C6.2.168 LDR (register) page C6-1558 line 92557 MATCH xb8600800/mask=xbfe00c00 +# CONSTRUCT xb8600800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xb8600800/mask=xffe00c00 --status nomem + +:ldr Rt_GPR32, addrIndexed +is size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = zext(*:4 addrIndexed); +} + +# C6.2.168 LDR (register) page C6-1558 line 92557 MATCH xb8600800/mask=xbfe00c00 +# CONSTRUCT xf8600800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xf8600800/mask=xffe00c00 --status nomem + +:ldr Rt_GPR64, addrIndexed +is size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR64 +{ + Rt_GPR64 = *addrIndexed; +} + + +# C6.2.169 LDRAA, LDRAB page C6-1560 line 92679 MATCH xf8200400/mask=xff200400 +# CONSTRUCT xf8200400/mask=xffa00400 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xf8200400/mask=xffa00400 --status nomem +# M == 0 && W == 0 key A, offset variant +# M == 0 && W == 1 key A, offset variant + +:ldraa Rt_GPR64, addrIndexed +is ldraa__PACpart & b_2431=0b11111000 & b_23=0 & b_21=1 & b_10=1 & addrIndexed & Rn_GPR64xsp & Rt_GPR64 +{ + build ldraa__PACpart; + build addrIndexed; + # Note: if writeback is used, the writeback'd value doesn't have a PAC code! It's the output of AuthDA. + Rt_GPR64 = *:8 addrIndexed; +} + +# C6.2.169 LDRAA, LDRAB page C6-1560 line 92679 MATCH xf8200400/mask=xff200400 +# CONSTRUCT xf8a00400/mask=xffa00400 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xf8a00400/mask=xffa00400 --status nomem +# M == 1 && W == 0 key B, offset variant +# M == 1 && W == 1 key B, offset variant + +:ldrab Rt_GPR64, addrIndexed +is ldrab__PACpart & b_2431=0b11111000 & b_23=1 & b_21=1 & b_10=1 & addrIndexed & Rn_GPR64xsp & Rt_GPR64 +{ + build ldrab__PACpart; + build addrIndexed; + # Note: if writeback is used, the writeback'd value doesn't have a PAC code! It's the output of AuthDB. + Rt_GPR64 = *:8 addrIndexed; +} + +# C6.2.170 LDRB (immediate) page C6-1562 line 92814 MATCH x38400400/mask=xffe00c00 +# C6.2.170 LDRB (immediate) page C6-1562 line 92814 MATCH x38400c00/mask=xffe00c00 +# CONSTRUCT x38400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x38400400/mask=xffe00400 --status nomem +# post-index and pre-index variants + +:ldrb Rt_GPR32, addrIndexed +is b_2131=0b00111000010 & b_10=1 & addrIndexed & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = zext(*:1 addrIndexed); +} + +# C6.2.170 LDRB (immediate) page C6-1562 line 92814 MATCH x39400000/mask=xffc00000 +# CONSTRUCT x39400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x39400000/mask=xffc00000 --status nomem +# unsigned offset variant + +:ldrb Rt_GPR32, addrIndexed +is b_2231=0b0011100101 & addrIndexed & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = zext(*:1 addrIndexed); +} + +# C6.2.171 LDRB (register) page C6-1565 line 92976 MATCH x38600800/mask=xffe00c00 +# CONSTRUCT x38600800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x38600800/mask=xffe00c00 --status nomem +# extended register and shifted register variant +# determined in addrIndexed subtable + +:ldrb Rt_GPR32, addrIndexed +is b_2131=0b00111000011 & b_1011=2 & addrIndexed & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = zext(*:1 addrIndexed); +} + +# C6.2.172 LDRH (immediate) page C6-1567 line 93076 MATCH x79400000/mask=xffc00000 +# CONSTRUCT x79400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x79400000/mask=xffc00000 --status nomem + +:ldrh Rt_GPR32, addrUIMM +is size.ldstr=1 & b_2729=7 & v=0 & b_2425=1 & b_23=0 & b_2222=1 & addrUIMM & Rn_GPR64xsp & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = zext(*:2 addrUIMM); +} + +# C6.2.172 LDRH (immediate) page C6-1567 line 93076 MATCH x78400400/mask=xffe00c00 +# C6.2.172 LDRH (immediate) page C6-1567 line 93076 MATCH x78400c00/mask=xffe00c00 +# CONSTRUCT x78400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x78400400/mask=xffe00400 --status nomem + +:ldrh Rt_GPR32, addrIndexed +is size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = zext(*:2 addrIndexed); +} + +# C6.2.173 LDRH (register) page C6-1570 line 93238 MATCH x78600800/mask=xffe00c00 +# CONSTRUCT x78600800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x78600800/mask=xffe00c00 --status nomem + +:ldrh Rt_GPR32, addrIndexed +is size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = zext(*:2 addrIndexed); +} + +# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x39800000/mask=xff800000 +# CONSTRUCT x39c00000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x39c00000/mask=xffc00000 --status nomem + +:ldrsb Rt_GPR32, addrIndexed +is size.ldstr=0 & b_2729=7 & v=0 & b_2425=1 & b_2223=3 & addrIndexed & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = sext(*:1 addrIndexed); +} + +# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x38800400/mask=xffa00c00 +# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x38800c00/mask=xffa00c00 +# C6.2.193 LDTRSB page C6-1617 line 95984 MATCH x38800800/mask=xffa00c00 +# C6.2.205 LDURSB page C6-1641 line 97443 MATCH x38800000/mask=xffa00c00 +# CONSTRUCT x38c00000/mask=xffe00000 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst x38c00000/mask=xffe00000 --status nomem + +:ld^UnscPriv^"rsb" Rt_GPR32, addrIndexed +is size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_2223=3 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = zext(*:1 addrIndexed); +} + +# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x38800400/mask=xffa00c00 +# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x38800c00/mask=xffa00c00 +# CONSTRUCT x38c00400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x38c00400/mask=xffe00400 --status nomem + +:ldrsb Rt_GPR32, addrIndexed +is size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_2223=3 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = sext(*:1 addrIndexed); +} + +# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x39800000/mask=xff800000 +# CONSTRUCT x39800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x39800000/mask=xffc00000 --status nomem + +:ldrsb Rt_GPR64, addrIndexed +is size.ldstr=0 & b_2729=7 & v=0 & b_2425=1 & b_2223=2 & addrIndexed & Rt_GPR64 +{ + Rt_GPR64 = sext(*:1 addrIndexed); +} + +# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x38800400/mask=xffa00c00 +# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x38800c00/mask=xffa00c00 +# C6.2.193 LDTRSB page C6-1617 line 95984 MATCH x38800800/mask=xffa00c00 +# C6.2.205 LDURSB page C6-1641 line 97443 MATCH x38800000/mask=xffa00c00 +# CONSTRUCT x38800000/mask=xffe00000 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst x38800000/mask=xffe00000 --status nomem + +:ld^UnscPriv^"rsb" Rt_GPR64, addrIndexed +is size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR64 +{ + Rt_GPR64 = sext(*:1 addrIndexed); +} + +# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x38800400/mask=xffa00c00 +# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x38800c00/mask=xffa00c00 +# CONSTRUCT x38800400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x38800400/mask=xffe00400 --status nomem + +:ldrsb Rt_GPR64, addrIndexed +is size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR64 +{ + Rt_GPR64 = sext(*:1 addrIndexed); +} + +# C6.2.175 LDRSB (register) page C6-1576 line 93573 MATCH x38a00800/mask=xffa00c00 +# CONSTRUCT x38e00800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x38e00800/mask=xffe00c00 --status nomem + +:ldrsb Rt_GPR32, addrIndexed +is size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_2223=3 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = sext(*:1 addrIndexed); +} + +# C6.2.175 LDRSB (register) page C6-1576 line 93573 MATCH x38a00800/mask=xffa00c00 +# CONSTRUCT x38a00800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x38a00800/mask=xffe00c00 --status nomem + +:ldrsb Rt_GPR64, addrIndexed +is size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR64 +{ + Rt_GPR64 = sext(*:1 addrIndexed); +} + +# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x79800000/mask=xff800000 +# CONSTRUCT x79c00000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x79c00000/mask=xffc00000 --status nomem + +:ldrsh Rt_GPR32, addrUIMM +is size.ldstr=1 & b_2729=7 & v=0 & b_2425=1 & b_2223=3 & addrUIMM & Rn_GPR64xsp & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = sext(*:2 addrUIMM); +} + +# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x78800400/mask=xffa00c00 +# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x78800c00/mask=xffa00c00 +# C6.2.194 LDTRSH page C6-1619 line 96122 MATCH x78800800/mask=xffa00c00 +# C6.2.206 LDURSH page C6-1643 line 97560 MATCH x78800000/mask=xffa00c00 +# CONSTRUCT x78c00000/mask=xffe00000 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst x78c00000/mask=xffe00000 --status nomem + +:ld^UnscPriv^"rsh" Rt_GPR32, addrIndexed +is size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_2223=3 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = sext(*:2 addrIndexed); +} + +# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x78800400/mask=xffa00c00 +# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x78800c00/mask=xffa00c00 +# CONSTRUCT x78c00400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x78c00400/mask=xffe00400 --status nomem + +:ldrsh Rt_GPR32, addrIndexed +is size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_2223=3 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = sext(*:2 addrIndexed); +} + +# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x79800000/mask=xff800000 +# CONSTRUCT x79800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x79800000/mask=xffc00000 --status nomem + +:ldrsh Rt_GPR64, addrUIMM +is size.ldstr=1 & b_2729=7 & v=0 & b_2425=1 & b_2223=2 & addrUIMM & Rn_GPR64xsp & Rt_GPR64 +{ + Rt_GPR64 = sext(*:2 addrUIMM); +} + +# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x78800400/mask=xffa00c00 +# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x78800c00/mask=xffa00c00 +# C6.2.194 LDTRSH page C6-1619 line 96122 MATCH x78800800/mask=xffa00c00 +# C6.2.206 LDURSH page C6-1643 line 97560 MATCH x78800000/mask=xffa00c00 +# CONSTRUCT x78800000/mask=xffe00000 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst x78800000/mask=xffe00000 --status nomem + +:ld^UnscPriv^"rsh" Rt_GPR64, addrIndexed +is size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR64 +{ + Rt_GPR64 = sext(*:2 addrIndexed); +} + +# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x78800400/mask=xffa00c00 +# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x78800c00/mask=xffa00c00 +# CONSTRUCT x78800400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x78800400/mask=xffe00400 --status nomem + +:ldrsh Rt_GPR64, addrIndexed +is size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR64 +{ + Rt_GPR64 = sext(*:2 addrIndexed); +} + +# C6.2.177 LDRSH (register) page C6-1582 line 93951 MATCH x78a00800/mask=xffa00c00 +# CONSTRUCT x78e00800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x78e00800/mask=xffe00c00 --status nomem + +:ldrsh Rt_GPR32, addrIndexed +is size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_2223=3 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = sext(*:2 addrIndexed); +} + +# C6.2.177 LDRSH (register) page C6-1582 line 93951 MATCH x78a00800/mask=xffa00c00 +# CONSTRUCT x78a00800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x78a00800/mask=xffe00c00 --status nomem + +:ldrsh Rt_GPR64, addrIndexed +is size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR64 +{ + Rt_GPR64 = sext(*:2 addrIndexed); +} + +# C6.2.178 LDRSW (immediate) page C6-1584 line 94088 MATCH xb8800400/mask=xffe00c00 +# C6.2.178 LDRSW (immediate) page C6-1584 line 94088 MATCH xb8800c00/mask=xffe00c00 +# CONSTRUCT xb8800400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xb8800400/mask=xffe00400 --status nomem + +:ldrsw Rt_GPR64, addrIndexed +is size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR64 +{ + Rt_GPR64 = sext(*:4 addrIndexed); +} + +# C6.2.178 LDRSW (immediate) page C6-1584 line 94088 MATCH xb9800000/mask=xffc00000 +# CONSTRUCT xb9800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xb9800000/mask=xffc00000 --status nomem + +:ldrsw Rt_GPR64, addrIndexed +is size.ldstr=2 & b_2729=7 & v=0 & b_2425=1 & b_2223=2 & addrIndexed & Rt_GPR64 +{ + Rt_GPR64 = sext(*:4 addrIndexed); +} + +# C6.2.179 LDRSW (literal) page C6-1587 line 94246 MATCH x98000000/mask=xff000000 +# CONSTRUCT x98000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x98000000/mask=xff000000 --status nomem + +:ldrsw Rt_GPR64, AddrLoc19 +is b_2431=0b10011000 & AddrLoc19 & Rt_GPR64 +{ + Rt_GPR64 = sext(*:4 AddrLoc19); +} + +# C6.2.180 LDRSW (register) page C6-1588 line 94304 MATCH xb8a00800/mask=xffe00c00 +# CONSTRUCT xb8a00800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xb8a00800/mask=xffe00c00 --status nomem + +:ldrsw Rt_GPR64, addrIndexed +is size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR64 +{ + Rt_GPR64 = sext(*:4 addrIndexed); +} + +# C6.2.190 LDTR page C6-1611 line 95666 MATCH xb8400800/mask=xbfe00c00 +# CONSTRUCT xf8400800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xf8400800/mask=xffe00c00 --status nomem + +:ld^UnscPriv^"r" Rt_GPR64, addrIndexed +is size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_2223=1 & b_2121=0 & b_1011=2 & UnscPriv & addrIndexed & Rt_GPR64 +{ + Rt_GPR64 = *addrIndexed; +} + +# C6.2.191 LDTRB page C6-1613 line 95782 MATCH x38400800/mask=xffe00c00 +# C6.2.203 LDURB page C6-1639 line 97301 MATCH x38400000/mask=xffe00c00 +# CONSTRUCT x38400000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x38400000/mask=xffe00000 --status nomem + +:ld^UnscPriv^"rb" Rt_GPR32, addrIndexed +is size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = zext(*:1 addrIndexed); +} + +# C6.2.192 LDTRH page C6-1615 line 95883 MATCH x78400800/mask=xffe00c00 +# C6.2.204 LDURH page C6-1640 line 97372 MATCH x78400000/mask=xffe00c00 +# CONSTRUCT x78400000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x78400000/mask=xffe00000 --status nomem + +:ld^UnscPriv^"rh" Rt_GPR32, addrIndexed +is size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = zext(*:2 addrIndexed); +} + +# C6.2.195 LDTRSW page C6-1621 line 96261 MATCH xb8800800/mask=xffe00c00 +# C6.2.207 LDURSW page C6-1645 line 97677 MATCH xb8800000/mask=xffe00c00 +# CONSTRUCT xb8800000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xb8800000/mask=xffe00000 --status nomem + +:ld^UnscPriv^"rsw" Rt_GPR64, addrIndexed +is size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR64 +{ + Rt_GPR64 = sext(*:4 addrIndexed); +} + +# C6.2.202 LDUR page C6-1637 line 97204 MATCH xb8400000/mask=xbfe00c00 +# CONSTRUCT xf8400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xf8400000/mask=xffe00c00 --status nomem + +:ld^UnscPriv^"r" Rt_GPR64, addrIndexed +is size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2122=2 & b_1011=0 & UnscPriv & addrIndexed & Rt_GPR64 +{ + Rt_GPR64 = *addrIndexed; +} + +# C6.2.208 LDXP page C6-1646 line 97748 MATCH x88600000/mask=xbfe08000 +# CONSTRUCT xc8600000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xc8600000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 + +:ldxp Rt_GPR64, Rt2_GPR64, addrReg +is size.ldstr=3 & b_2429=0x8 & b_23=0 & L=1 & b_21=1 & b_15=0 & Rt2_GPR64 & addrReg & Rt_GPR64 +{ + Rt_GPR64 = *addrReg; + Rt2_GPR64 = *(addrReg + 8); +} + +# C6.2.208 LDXP page C6-1646 line 97748 MATCH x88600000/mask=xbfe08000 +# CONSTRUCT x88600000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x88600000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 + +:ldxp Rt_GPR32, Rt2_GPR32, addrReg +is size.ldstr=2 & b_2429=0x8 & b_23=0 & L=1 & b_21=1 & b_15=0 & Rt2_GPR32 & addrReg & Rt_GPR32 & Rt_GPR64 & Rt2_GPR64 +{ + Rt_GPR64 = zext(*:4 addrReg); + Rt2_GPR64 = zext(*:4 (addrReg + 4)); +} + +# C6.2.209 LDXR page C6-1648 line 97882 MATCH x88400000/mask=xbfe08000 +# CONSTRUCT xc8400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xc8400000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111 + +:ldxr Rt_GPR64, addrReg +is size.ldstr=3 & b_2429=0x8 & b_23=0 & L=1 & b_21=0 & b_15=0 & addrReg & Rt_GPR64 +{ + Rt_GPR64 = *addrReg; +} + +# C6.2.209 LDXR page C6-1648 line 97882 MATCH x88400000/mask=xbfe08000 +# CONSTRUCT x88400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x88400000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111 + +:ldxr Rt_GPR32, addrReg +is size.ldstr=2 & b_2429=0x8 & b_23=0 & L=1 & b_21=0 & b_15=0 & addrReg & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = zext(*:4 addrReg); +} + +# C6.2.210 LDXRB page C6-1650 line 97976 MATCH x08400000/mask=xffe08000 +# CONSTRUCT x08400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x08400000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111 + +:ldxrb Rt_GPR32, addrReg +is size.ldstr=0 & b_2429=0x8 & b_23=0 & L=1 & b_21=0 & b_15=0 & addrReg & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = zext(*:1 addrReg); +} + +# C6.2.211 LDXRH page C6-1651 line 98048 MATCH x48400000/mask=xffe08000 +# CONSTRUCT x48400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x48400000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111 + +:ldxrh Rt_GPR32, addrReg +is size.ldstr=1 & b_2429=0x8 & b_23=0 & L=1 & b_21=0 & b_15=0 & addrReg & Rt_GPR32 & Rt_GPR64 +{ + Rt_GPR64 = zext(*:2 addrReg); +} + +# C6.2.212 LSL (register) page C6-1652 line 98120 MATCH x1ac02000/mask=x7fe0fc00 +# C6.2.214 LSLV page C6-1656 line 98305 MATCH x1ac02000/mask=x7fe0fc00 +# CONSTRUCT x1ac02000/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x1ac02000/mask=xffe0fc00 --status pass + +:lsl Rd_GPR32, Rn_GPR32, Rm_GPR32 +is sf=0 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR32 & b_1015=0x8 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + shiftval:8 = zext(Rm_GPR32 & 0x1f); + tmp_1:4 = Rn_GPR32 << shiftval; + Rd_GPR64 = zext(tmp_1); +} + +# C6.2.212 LSL (register) page C6-1652 line 98120 MATCH x1ac02000/mask=x7fe0fc00 +# C6.2.214 LSLV page C6-1656 line 98305 MATCH x1ac02000/mask=x7fe0fc00 +# CONSTRUCT x9ac02000/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x9ac02000/mask=xffe0fc00 --status pass + +:lsl Rd_GPR64, Rn_GPR64, Rm_GPR64 +is sf=1 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR64 & b_1015=0x8 & Rn_GPR64 & Rd_GPR64 +{ + shiftval:8 = (Rm_GPR64 & 0x3f); + tmp_1:8 = Rn_GPR64 << shiftval; + Rd_GPR64 = tmp_1; +} + +# C6.2.158 LSL (immediate) page C6-784 line 45779 KEEPWITH + +ubfiz_lsb: "#"^imm is ImmR [ imm = 32 - ImmR; ] { export *[const]:4 imm; } +ubfiz_width: "#"^imm is ImmS [ imm = ImmS + 1; ] { export *[const]:4 imm; } +ubfiz_lsb64: "#"^imm is ImmR [ imm = 64 - ImmR; ] { export *[const]:4 imm; } +ubfx_width: "#"^imm is ImmR & ImmS [ imm = ImmS - ImmR + 1; ] { export *[const]:4 imm; } + +# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000 +# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00 +# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000 +# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000 +# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000 +# C6.2.394 UXTB page C6-2002 line 117228 MATCH x53001c00/mask=xfffffc00 +# C6.2.395 UXTH page C6-2003 line 117288 MATCH x53003c00/mask=xfffffc00 +# CONSTRUCT x53000012/mask=xffe0801e MATCHED 7 DOCUMENTED OPCODES +# AUNIT --inst x53000012/mask=xffe0801e --status pass +# Alias for ubfm where imms+1=immr and imms != '011111' +# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue(); + +:lsl Rd_GPR32, Rn_GPR32, LSB_bitfield32_imm_shift +is ImmR=ImmS+1 & ImmS_ne_1f=1 & ImmS_LT_ImmR_minus_1=0 & ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=1 & sf=0 & opc=2 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & LSB_bitfield32_imm_shift & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + local tmp:4 = Rn_GPR32 << LSB_bitfield32_imm_shift; + Rd_GPR64 = zext(tmp); +} + +# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000 +# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00 +# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000 +# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000 +# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000 +# CONSTRUCT xd3400022/mask=xffc0002e MATCHED 5 DOCUMENTED OPCODES +# AUNIT --inst xd3400022/mask=xffc0002e --status pass +# Alias for ubfm where imms+1=immr and imms != '111111' + +:lsl Rd_GPR64, Rn_GPR64, LSB_bitfield64_imm_shift +is ImmR=ImmS+1 & ImmS_ne_3f=1 & ImmS_LT_ImmR_minus_1=0 & ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=1 & sf=1 & opc=2 & b_2428=0x13 & b_2323=0 & n=1 & LSB_bitfield64_imm_shift & Rn_GPR64 & Rd_GPR64 +{ + Rd_GPR64 = Rn_GPR64 << LSB_bitfield64_imm_shift; +} + +# C6.2.215 LSR (register) page C6-1658 line 98396 MATCH x1ac02400/mask=x7fe0fc00 +# C6.2.217 LSRV page C6-1662 line 98580 MATCH x1ac02400/mask=x7fe0fc00 +# CONSTRUCT x1ac02400/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x1ac02400/mask=xffe0fc00 --status pass + +:lsr Rd_GPR32, Rn_GPR32, Rm_GPR32 +is sf=0 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR32 & b_1015=0x9 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + shiftval:8 = zext(Rm_GPR32 & 0x1f); + tmp_1:4 = Rn_GPR32 >> shiftval; + Rd_GPR64 = zext(tmp_1); +} + +# C6.2.215 LSR (register) page C6-1658 line 98396 MATCH x1ac02400/mask=x7fe0fc00 +# C6.2.217 LSRV page C6-1662 line 98580 MATCH x1ac02400/mask=x7fe0fc00 +# CONSTRUCT x9ac02400/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x9ac02400/mask=xffe0fc00 --status pass + +:lsr Rd_GPR64, Rn_GPR64, Rm_GPR64 +is sf=1 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR64 & b_1015=0x9 & Rn_GPR64 & Rd_GPR64 +{ + shiftval:8 = Rm_GPR64 & 0x3f; + tmp_1:8 = Rn_GPR64 >> shiftval; + Rd_GPR64 = tmp_1; +} + +# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00 +# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000 +# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000 +# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000 +# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000 +# CONSTRUCT x53007c00/mask=xffe0fc1a MATCHED 5 DOCUMENTED OPCODES +# AUNIT --inst x53007c00/mask=xffe0fc1a --status pass +# Alias for ubfm where imms=='011111' +# imms is MAX_INT5, so it will never be less than immr. Note that immr is limited to [0,31] +# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue(); + +:lsr Rd_GPR32, Rn_GPR32, ImmRConst32 +is ImmS=0x1f & ImmS_ne_1f=0 & ImmS_LT_ImmR=0 & ImmS_LT_ImmR_minus_1=0 & sf=0 & opc=2 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp_2:4 = ImmRConst32; + tmp_1:4 = Rn_GPR32 >> tmp_2; + Rd_GPR64 = zext(tmp_1); +} + +# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00 +# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000 +# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000 +# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000 +# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000 +# CONSTRUCT xd340fc00/mask=xffc0fc2a MATCHED 5 DOCUMENTED OPCODES +# AUNIT --inst xd340fc00/mask=xffc0fc2a --status pass +# Alias for ubfm where imms=='111111' +# imms is MAX_INT6, so it will never be less than immr. + +:lsr Rd_GPR64, Rn_GPR64, ImmRConst64 +is ImmS=0x3f & ImmS_ne_3f=0 & ImmS_LT_ImmR=0 & ImmS_LT_ImmR_minus_1=0 & sf=1 & opc=2 & b_2428=0x13 & b_2323=0 & n=1 & ImmRConst64 & Rn_GPR64 & Rd_GPR64 +{ + tmp_2:8 = ImmRConst64; + tmp_1:8 = Rn_GPR64 >> tmp_2; + Rd_GPR64 = tmp_1; +} + +# C6.2.218 MADD page C6-1664 line 98671 MATCH x1b000000/mask=x7fe08000 +# C6.2.232 MUL page C6-1691 line 100073 MATCH x1b007c00/mask=x7fe0fc00 +# CONSTRUCT x1b000000/mask=xffe08000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x1b000000/mask=xffe08000 --status pass + +:madd Rd_GPR32, Rn_GPR32, Rm_GPR32, Ra_GPR32 +is sf=0 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=0 & Rm_GPR32 & op.dp3_o0=0 & Ra_GPR32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp_2:4 = Rn_GPR32 * Rm_GPR32; + addflags(Ra_GPR32, tmp_2); + tmp_1:4 = Ra_GPR32 + tmp_2; + Rd_GPR64 = zext(tmp_1); +} + +# C6.2.218 MADD page C6-1664 line 98671 MATCH x1b000000/mask=x7fe08000 +# C6.2.232 MUL page C6-1691 line 100073 MATCH x1b007c00/mask=x7fe0fc00 +# CONSTRUCT x9b000000/mask=xffe08000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x9b000000/mask=xffe08000 --status pass + +:madd Rd_GPR64, Rn_GPR64, Rm_GPR64, Ra_GPR64 +is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=0 & Rm_GPR64 & op.dp3_o0=0 & Ra_GPR64 & Rn_GPR64 & Rd_GPR64 +{ + tmp_2:8 = Rn_GPR64 * Rm_GPR64; + tmp_1:8 = Ra_GPR64 + tmp_2; + Rd_GPR64 = tmp_1; +} + +# C6.2.219 MNEG page C6-1666 line 98782 MATCH x1b00fc00/mask=x7fe0fc00 +# C6.2.231 MSUB page C6-1689 line 99963 MATCH x1b008000/mask=x7fe08000 +# CONSTRUCT x9b00fc00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x9b00fc00/mask=xffe0fc00 --status pass + +:mneg Rd_GPR64, Rn_GPR64, Rm_GPR64 +is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=0 & Rm_GPR64 & op.dp3_o0=1 & Ra=0x1f & Rn_GPR64 & Rd_GPR64 +{ + tmp_2:8 = Rn_GPR64 * Rm_GPR64; + tmp_1:8 = -tmp_2; + Rd_GPR64 = tmp_1; +} + +# C6.2.219 MNEG page C6-1666 line 98782 MATCH x1b00fc00/mask=x7fe0fc00 +# C6.2.231 MSUB page C6-1689 line 99963 MATCH x1b008000/mask=x7fe08000 +# CONSTRUCT x1b00fc00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x1b00fc00/mask=xffe0fc00 --status pass + +:mneg Rd_GPR32, Rn_GPR32, Rm_GPR32 +is sf=0 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=0 & Rm_GPR32 & op.dp3_o0=1 & Ra=0x1f & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp_2:4 = Rn_GPR32 * Rm_GPR32; + tmp_1:4 = -tmp_2; + Rd_GPR64 = zext(tmp_1); +} + +# C6.2.220 MOV (to/from SP) page C6-1668 line 98876 MATCH x11000000/mask=x7ffffc00 +# C6.2.4 ADD (immediate) page C6-1151 line 68228 MATCH x11000000/mask=x7f800000 +# CONSTRUCT x11000000/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x11000000/mask=xfffffc00 --status pass + +:mov Rd_GPR32xsp, Rn_GPR32xsp +is sf=0 & b_30=0 & S=0 & b_2428=0x011 & (aa_Xn=31 | aa_Xd=31) & shift=0 & imm12=0 & Rn_GPR32xsp & Rd_GPR32xsp & Rd_GPR64xsp +{ + Rd_GPR64xsp = zext(Rn_GPR32xsp); +} + +# C6.2.220 MOV (to/from SP) page C6-1668 line 98876 MATCH x11000000/mask=x7ffffc00 +# C6.2.4 ADD (immediate) page C6-1151 line 68228 MATCH x11000000/mask=x7f800000 +# CONSTRUCT x91000000/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x91000000/mask=xfffffc00 --status pass + +:mov Rd_GPR64xsp, Rn_GPR64xsp +is sf=1 & b_30=0 & S=0 & b_2428=0x11 & (aa_Xn=31 | aa_Xd=31) & shift=0 & imm12=0 & Rn_GPR64xsp & Rd_GPR64xsp +{ + Rd_GPR64xsp = Rn_GPR64xsp; +} + +# C6.2.166 MOV (inverted wide immediate) page C6-793 line 46366 KEEPWITH + +FullImm_movz32_imm: "#"^val is imm16 & aa_hw=0 [ val = (imm16 << 0) & 0xffffffff; ] { export *[const]:8 val; } +FullImm_movz32_imm: "#"^val is imm16 & aa_hw=1 [ val = (imm16 << 16) & 0xffffffff; ] { export *[const]:8 val; } + +FullImm_movz64_imm: "#"^val is imm16 & aa_hw [ val = imm16 << (aa_hw * 16); ] { export *[const]:8 val; } + +FullImm_movn32_imm: "#"^val is imm16 & aa_hw=0 [ val = ~(imm16 << 0) & 0xffffffff; ] { export *[const]:8 val; } +FullImm_movn32_imm: "#"^val is imm16 & aa_hw=1 [ val = ~(imm16 << 16) & 0xffffffff; ] { export *[const]:8 val; } + +FullImm_movn64_imm: "#"^val is imm16 & aa_hw [ val = ~(imm16 << (aa_hw * 16)); ] { export *[const]:8 val; } + +FullImm_movk32_mask: mask is aa_hw [ mask = (~(0xffff << (aa_hw * 16))) & 0xffffffff; ] { export *[const]:4 mask; } +FullImm_movk32_shift: tmp is imm16 & aa_hw [ tmp = (imm16 << (aa_hw * 16)) & 0xffffffff; ] { export *[const]:4 tmp; } +FullImm_movk32_imm: "#"^imm16 is imm16 & aa_hw=0 { export *[const]:4 imm16; } +FullImm_movk32_imm: "#"^imm16, "LSL #16" is imm16 & aa_hw=1 & FullImm_movk32_shift { export FullImm_movk32_shift; } + +FullImm_movk64_mask: mask is aa_hw [ mask = ~(0xffff << (aa_hw * 16)); ] { export *[const]:8 mask; } +FullImm_movk64_shift: tmp is imm16 & aa_hw [ tmp = (imm16 << (aa_hw * 16)); ] { export *[const]:8 tmp; } +FullImm_movk64_imm: "#"^imm16 is imm16 & aa_hw=0 { export *[const]:8 imm16; } +FullImm_movk64_imm: "#"^imm16, "LSL #16" is imm16 & aa_hw=1 & FullImm_movk64_shift { export FullImm_movk64_shift; } +FullImm_movk64_imm: "#"^imm16, "LSL #32" is imm16 & aa_hw=2 & FullImm_movk64_shift { export FullImm_movk64_shift; } +FullImm_movk64_imm: "#"^imm16, "LSL #48" is imm16 & aa_hw=3 & FullImm_movk64_shift { export FullImm_movk64_shift; } + +# C6.2.221 MOV (inverted wide immediate) page C6-1669 line 98943 MATCH x12800000/mask=x7f800000 +# C6.2.226 MOVN page C6-1679 line 99388 MATCH x12800000/mask=x7f800000 +# CONSTRUCT x12800000/mask=xff800000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x12800000/mask=xff800000 --status pass + +:mov Rd_GPR32, FullImm_movn32_imm +is sf=0 & opc=0 & b_2428=0x12 & b_2323=1 & FullImm_movn32_imm & Rd_GPR32 & Rd_GPR64 +{ + # Special case MOVN + Rd_GPR64 = FullImm_movn32_imm; +} + +# C6.2.221 MOV (inverted wide immediate) page C6-1669 line 98943 MATCH x12800000/mask=x7f800000 +# C6.2.226 MOVN page C6-1679 line 99388 MATCH x12800000/mask=x7f800000 +# CONSTRUCT x92800000/mask=xff800000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x92800000/mask=xff800000 --status pass + +:mov Rd_GPR64, FullImm_movn64_imm +is sf=1 & opc=0 & b_2428=0x12 & b_2323=1 & FullImm_movn64_imm & Rd_GPR64 +{ + # Special case MOVN + Rd_GPR64 = FullImm_movn64_imm; +} + +# C6.2.222 MOV (wide immediate) page C6-1671 line 99035 MATCH x52800000/mask=x7f800000 +# C6.2.227 MOVZ page C6-1681 line 99489 MATCH x52800000/mask=x7f800000 +# CONSTRUCT x52800000/mask=xff800000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x52800000/mask=xff800000 --status pass + +:mov Rd_GPR32, FullImm_movz32_imm +is sf=0 & opc=2 & b_2428=0x12 & b_2323=1 & FullImm_movz32_imm & Rd_GPR32 & Rd_GPR64 +{ + Rd_GPR64 = FullImm_movz32_imm; +} + +# C6.2.222 MOV (wide immediate) page C6-1671 line 99035 MATCH x52800000/mask=x7f800000 +# C6.2.227 MOVZ page C6-1681 line 99489 MATCH x52800000/mask=x7f800000 +# CONSTRUCT xd2800000/mask=xff800000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd2800000/mask=xff800000 --status pass + +:mov Rd_GPR64, FullImm_movz64_imm +is sf=1 & opc=2 & b_2428=0x12 & b_2323=1 & FullImm_movz64_imm & Rd_GPR64 +{ + Rd_GPR64 = FullImm_movz64_imm; +} + +# C6.2.223 MOV (bitmask immediate) page C6-1673 line 99125 MATCH x320003e0/mask=x7f8003e0 +# C6.2.240 ORR (immediate) page C6-1705 line 100779 MATCH x32000000/mask=x7f800000 +# CONSTRUCT x320003e0/mask=xffe0ffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x320003e0/mask=xffe0ffe0 --status pass + +:mov Rd_GPR32wsp, DecodeWMask32 +is sf=0 & opc=1 & b_2428=0x12 & b_2223=0 & N=0 & imm6=0 & DecodeWMask32 & aa_Xn=31 & Rd_GPR32wsp & Rd_GPR64xsp +{ + # special case ORR + tmp_1:4 = DecodeWMask32; + Rd_GPR64xsp = zext(tmp_1); +} + +# C6.2.223 MOV (bitmask immediate) page C6-1673 line 99125 MATCH x320003e0/mask=x7f8003e0 +# C6.2.240 ORR (immediate) page C6-1705 line 100779 MATCH x32000000/mask=x7f800000 +# CONSTRUCT xb20003e0/mask=xffc0ffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xb20003e0/mask=xffc0ffe0 --status pass + +:mov Rd_GPR64xsp, DecodeWMask64 +is sf=1 & opc=1 & b_2428=0x12 & b_2223=0 & imm6=0 & DecodeWMask64 & aa_Xn=31 & Rd_GPR64xsp +{ + # special case of ORR + tmp_1:8 = DecodeWMask64; + Rd_GPR64xsp = tmp_1; +} + +# C6.2.224 MOV (register) page C6-1675 line 99214 MATCH x2a0003e0/mask=x7fe0ffe0 +# C6.2.241 ORR (shifted register) page C6-1707 line 100882 MATCH x2a000000/mask=x7f200000 +# CONSTRUCT x2a0003e0/mask=xff2003e0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x2a0003e0/mask=xff2003e0 --status pass + +:mov Rd_GPR32, RegShift32Log +is b_31=0 & b_2430=0b0101010 & b_21=0 & b_0509=0b11111 & RegShift32Log & Rd_GPR32 & Rd_GPR64 +{ + # special case ORR + tmp_1:4 = RegShift32Log; + Rd_GPR64 = zext(tmp_1); +} + +# C6.2.224 MOV (register) page C6-1675 line 99214 MATCH x2a0003e0/mask=x7fe0ffe0 +# C6.2.241 ORR (shifted register) page C6-1707 line 100882 MATCH x2a000000/mask=x7f200000 +# CONSTRUCT xaa0003e0/mask=xff2003e0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xaa0003e0/mask=xff2003e0 --status pass + +:mov Rd_GPR64, RegShift64Log +is b_31=1 & b_2430=0b0101010 & b_21=0 & b_0509=0b11111 & RegShift64Log & Rd_GPR64 +{ + # special case of ORR + tmp_1:8 = RegShift64Log; + Rd_GPR64 = tmp_1; +} + +# C6.2.225 MOVK page C6-1677 line 99301 MATCH x72800000/mask=x7f800000 +# CONSTRUCT x72800000/mask=xff800000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x72800000/mask=xff800000 --status pass + +:movk Rd_GPR32, FullImm_movk32_imm +is sf=0 & opc=3 & b_2428=0x12 & b_2323=1 & FullImm_movk32_imm & Rd_GPR32 & Rd_GPR64 & FullImm_movk32_mask +{ + local tmp:4 = Rd_GPR32 & FullImm_movk32_mask; + tmp = tmp | FullImm_movk32_imm; + Rd_GPR64 = zext(tmp); +} + +# C6.2.225 MOVK page C6-1677 line 99301 MATCH x72800000/mask=x7f800000 +# CONSTRUCT xf2800000/mask=xff800000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xf2800000/mask=xff800000 --status pass + +:movk Rd_GPR64, FullImm_movk64_imm +is sf=1 & opc=3 & b_2428=0x12 & b_2323=1 & FullImm_movk64_imm & Rd_GPR64 & FullImm_movk64_mask +{ + Rd_GPR64 = Rd_GPR64 & FullImm_movk64_mask; + Rd_GPR64 = Rd_GPR64 | FullImm_movk64_imm; +} + +# C6.2.173 MRS page C6-802 line 46877 MATCH KEEPWITH + +with : (l=0 | l=1) { +CopReg: spsr_el1 is Op0=3 & Op1_uimm3=0 & CRn=4 & CRm=0 & Op2_uimm3=0 & spsr_el1 { export spsr_el1; } +CopReg: elr_el1 is Op0=3 & Op1_uimm3=0 & CRn=4 & CRm=0 & Op2_uimm3=1 & elr_el1 { export elr_el1; } +CopReg: sp_el0 is Op0=3 & Op1_uimm3=0 & CRn=4 & CRm=1 & Op2_uimm3=0 & sp_el0 { export sp_el0; } +CopReg: spsel is Op0=3 & Op1_uimm3=0 & CRn=4 & CRm=2 & Op2_uimm3=0 & spsel { export spsel; } +CopReg: daif is Op0=3 & Op1_uimm3=3 & CRn=4 & CRm=2 & Op2_uimm3=1 & daif { export daif; } +CopReg: currentel is Op0=3 & Op1_uimm3=0 & CRn=4 & CRm=2 & Op2_uimm3=2 & currentel { export currentel; } +CopReg: nzcv is Op0=3 & Op1_uimm3=3 & CRn=4 & CRm=2 & Op2_uimm3=0 & nzcv { export nzcv; } +CopReg: fpcr is Op0=3 & Op1_uimm3=3 & CRn=4 & CRm=4 & Op2_uimm3=0 & fpcr { export fpcr; } +CopReg: fpsr is Op0=3 & Op1_uimm3=3 & CRn=4 & CRm=4 & Op2_uimm3=1 & fpsr { export fpsr; } +CopReg: dspsr_el0 is Op0=3 & Op1_uimm3=3 & CRn=4 & CRm=5 & Op2_uimm3=0 & dspsr_el0 { export dspsr_el0; } +CopReg: dlr_el0 is Op0=3 & Op1_uimm3=3 & CRn=4 & CRm=5 & Op2_uimm3=1 & dlr_el0 { export dlr_el0; } +CopReg: spsr_el2 is Op0=3 & Op1_uimm3=4 & CRn=4 & CRm=0 & Op2_uimm3=0 & spsr_el2 { export spsr_el2; } +CopReg: elr_el2 is Op0=3 & Op1_uimm3=4 & CRn=4 & CRm=0 & Op2_uimm3=1 & elr_el2 { export elr_el2; } +CopReg: sp_el1 is Op0=3 & Op1_uimm3=4 & CRn=4 & CRm=1 & Op2_uimm3=0 & sp_el1 { export sp_el1; } +CopReg: spsr_irq is Op0=3 & Op1_uimm3=4 & CRn=4 & CRm=3 & Op2_uimm3=0 & spsr_irq { export spsr_irq; } +CopReg: spsr_abt is Op0=3 & Op1_uimm3=4 & CRn=4 & CRm=3 & Op2_uimm3=1 & spsr_abt { export spsr_abt; } +CopReg: spsr_und is Op0=3 & Op1_uimm3=4 & CRn=4 & CRm=3 & Op2_uimm3=2 & spsr_und { export spsr_und; } +CopReg: spsr_fiq is Op0=3 & Op1_uimm3=4 & CRn=4 & CRm=3 & Op2_uimm3=3 & spsr_fiq { export spsr_fiq; } +CopReg: spsr_el3 is Op0=3 & Op1_uimm3=6 & CRn=4 & CRm=0 & Op2_uimm3=0 & spsr_el3 { export spsr_el3; } +CopReg: elr_el3 is Op0=3 & Op1_uimm3=6 & CRn=4 & CRm=0 & Op2_uimm3=1 & elr_el3 { export elr_el3; } +CopReg: sp_el2 is Op0=3 & Op1_uimm3=6 & CRn=4 & CRm=1 & Op2_uimm3=0 & sp_el2 { export sp_el2; } +# CopReg: spsr_svc is Op0=3 & Op1_uimm3=0 & CRn=4 & CRm=0 & Op2_uimm3=0 & spsr_svc { export spsr_svc; } +# CopReg: spsr_hyp is Op0=3 & Op1_uimm3=4 & CRn=4 & CRm=0 & Op2_uimm3=0 & spsr_hyp { export spsr_hyp; } + +CopReg: midr_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=0 & Op2_uimm3=0 & midr_el1 { export midr_el1; } +CopReg: mpidr_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=0 & Op2_uimm3=5 & mpidr_el1 { export mpidr_el1; } +CopReg: revidr_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=0 & Op2_uimm3=6 & revidr_el1 { export revidr_el1; } +CopReg: id_dfr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=2 & id_dfr0_el1 { export id_dfr0_el1; } +CopReg: id_pfr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=0 & id_pfr0_el1 { export id_pfr0_el1; } +CopReg: id_pfr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=1 & id_pfr1_el1 { export id_pfr1_el1; } +CopReg: id_afr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=3 & id_afr0_el1 { export id_afr0_el1; } +CopReg: id_mmfr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=4 & id_mmfr0_el1 { export id_mmfr0_el1; } +CopReg: id_mmfr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=5 & id_mmfr1_el1 { export id_mmfr1_el1; } +CopReg: id_mmfr2_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=6 & id_mmfr2_el1 { export id_mmfr2_el1; } +CopReg: id_mmfr3_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=7 & id_mmfr3_el1 { export id_mmfr3_el1; } +CopReg: id_isar0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=0 & id_isar0_el1 { export id_isar0_el1; } +CopReg: id_isar1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=1 & id_isar1_el1 { export id_isar1_el1; } +CopReg: id_isar2_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=2 & id_isar2_el1 { export id_isar2_el1; } +CopReg: id_isar3_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=3 & id_isar3_el1 { export id_isar3_el1; } +CopReg: id_isar4_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=4 & id_isar4_el1 { export id_isar4_el1; } +CopReg: id_isar5_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=5 & id_isar5_el1 { export id_isar5_el1; } +CopReg: mvfr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=3 & Op2_uimm3=0 & mvfr0_el1 { export mvfr0_el1; } +CopReg: mvfr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=3 & Op2_uimm3=1 & mvfr1_el1 { export mvfr1_el1; } +CopReg: mvfr2_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=3 & Op2_uimm3=2 & mvfr2_el1 { export mvfr2_el1; } +CopReg: ccsidr_el1 is Op0=3 & Op1_uimm3=1 & CRn=0 & CRm=0 & Op2_uimm3=0 & ccsidr_el1 { export ccsidr_el1; } +CopReg: id_aa64pfr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=4 & Op2_uimm3=0 & id_aa64pfr0_el1 { export id_aa64pfr0_el1; } +CopReg: id_aa64pfr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=4 & Op2_uimm3=1 & id_aa64pfr1_el1 { export id_aa64pfr1_el1; } +CopReg: id_aa64dfr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=5 & Op2_uimm3=0 & id_aa64dfr0_el1 { export id_aa64dfr0_el1; } +CopReg: id_aa64dfr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=5 & Op2_uimm3=1 & id_aa64dfr1_el1 { export id_aa64dfr1_el1; } +CopReg: id_aa64isar0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=6 & Op2_uimm3=0 & id_aa64isar0_el1 { export id_aa64isar0_el1; } +CopReg: id_aa64isar1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=6 & Op2_uimm3=1 & id_aa64isar1_el1 { export id_aa64isar1_el1; } +CopReg: id_aa64mmfr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=7 & Op2_uimm3=0 & id_aa64mmfr0_el1 { export id_aa64mmfr0_el1; } +CopReg: id_aa64mmfr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=7 & Op2_uimm3=1 & id_aa64mmfr1_el1 { export id_aa64mmfr1_el1; } +CopReg: id_aa64afr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=5 & Op2_uimm3=4 & id_aa64afr0_el1 { export id_aa64afr0_el1; } +CopReg: id_aa64afr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=5 & Op2_uimm3=5 & id_aa64afr1_el1 { export id_aa64afr1_el1; } +CopReg: clidr_el1 is Op0=3 & Op1_uimm3=1 & CRn=0 & CRm=0 & Op2_uimm3=1 & clidr_el1 { export clidr_el1; } +CopReg: aidr_el1 is Op0=3 & Op1_uimm3=1 & CRn=0 & CRm=0 & Op2_uimm3=7 & aidr_el1 { export aidr_el1; } +CopReg: csselr_el1 is Op0=3 & Op1_uimm3=2 & CRn=0 & CRm=0 & Op2_uimm3=0 & csselr_el1 { export csselr_el1; } +CopReg: ctr_el0 is Op0=3 & Op1_uimm3=3 & CRn=0 & CRm=0 & Op2_uimm3=1 & ctr_el0 { export ctr_el0; } +CopReg: dczid_el0 is Op0=3 & Op1_uimm3=3 & CRn=0 & CRm=0 & Op2_uimm3=7 & dczid_el0 { export dczid_el0; } +CopReg: vpidr_el2 is Op0=3 & Op1_uimm3=4 & CRn=0 & CRm=0 & Op2_uimm3=0 & vpidr_el2 { export vpidr_el2; } +CopReg: vmpidr_el2 is Op0=3 & Op1_uimm3=4 & CRn=0 & CRm=0 & Op2_uimm3=5 & vmpidr_el2 { export vmpidr_el2; } +CopReg: sctlr_el1 is Op0=3 & Op1_uimm3=0 & CRn=1 & CRm=0 & Op2_uimm3=0 & sctlr_el1 { export sctlr_el1; } +CopReg: actlr_el1 is Op0=3 & Op1_uimm3=0 & CRn=1 & CRm=0 & Op2_uimm3=1 & actlr_el1 { export actlr_el1; } +CopReg: cpacr_el1 is Op0=3 & Op1_uimm3=0 & CRn=1 & CRm=0 & Op2_uimm3=2 & cpacr_el1 { export cpacr_el1; } +CopReg: sctlr_el2 is Op0=3 & Op1_uimm3=4 & CRn=1 & CRm=0 & Op2_uimm3=0 & sctlr_el2 { export sctlr_el2; } +CopReg: actlr_el2 is Op0=3 & Op1_uimm3=4 & CRn=1 & CRm=0 & Op2_uimm3=1 & actlr_el2 { export actlr_el2; } +CopReg: hcr_el2 is Op0=3 & Op1_uimm3=4 & CRn=1 & CRm=1 & Op2_uimm3=0 & hcr_el2 { export hcr_el2; } +CopReg: mdcr_el2 is Op0=3 & Op1_uimm3=4 & CRn=1 & CRm=1 & Op2_uimm3=1 & mdcr_el2 { export mdcr_el2; } +CopReg: cptr_el2 is Op0=3 & Op1_uimm3=4 & CRn=1 & CRm=1 & Op2_uimm3=2 & cptr_el2 { export cptr_el2; } +CopReg: hstr_el2 is Op0=3 & Op1_uimm3=4 & CRn=1 & CRm=1 & Op2_uimm3=3 & hstr_el2 { export hstr_el2; } +CopReg: hacr_el2 is Op0=3 & Op1_uimm3=4 & CRn=1 & CRm=1 & Op2_uimm3=7 & hacr_el2 { export hacr_el2; } +CopReg: sctlr_el3 is Op0=3 & Op1_uimm3=6 & CRn=1 & CRm=0 & Op2_uimm3=0 & sctlr_el3 { export sctlr_el3; } +CopReg: actlr_el3 is Op0=3 & Op1_uimm3=6 & CRn=1 & CRm=0 & Op2_uimm3=1 & actlr_el3 { export actlr_el3; } +CopReg: scr_el3 is Op0=3 & Op1_uimm3=6 & CRn=1 & CRm=1 & Op2_uimm3=0 & scr_el3 { export scr_el3; } +CopReg: cptr_el3 is Op0=3 & Op1_uimm3=6 & CRn=1 & CRm=1 & Op2_uimm3=2 & cptr_el3 { export cptr_el3; } +CopReg: mdcr_el3 is Op0=3 & Op1_uimm3=6 & CRn=1 & CRm=3 & Op2_uimm3=1 & mdcr_el3 { export mdcr_el3; } +CopReg: ttbr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=2 & CRm=0 & Op2_uimm3=0 & ttbr0_el1 { export ttbr0_el1; } +CopReg: ttbr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=2 & CRm=0 & Op2_uimm3=1 & ttbr1_el1 { export ttbr1_el1; } +CopReg: ttbr0_el2 is Op0=3 & Op1_uimm3=4 & CRn=2 & CRm=0 & Op2_uimm3=0 & ttbr0_el2 { export ttbr0_el2; } +CopReg: ttbr0_el3 is Op0=3 & Op1_uimm3=6 & CRn=2 & CRm=0 & Op2_uimm3=0 & ttbr0_el3 { export ttbr0_el3; } +CopReg: vttbr_el2 is Op0=3 & Op1_uimm3=4 & CRn=2 & CRm=1 & Op2_uimm3=0 & vttbr_el2 { export vttbr_el2; } +CopReg: tcr_el1 is Op0=3 & Op1_uimm3=0 & CRn=2 & CRm=0 & Op2_uimm3=2 & tcr_el1 { export tcr_el1; } +CopReg: tcr_el2 is Op0=3 & Op1_uimm3=4 & CRn=2 & CRm=0 & Op2_uimm3=2 & tcr_el2 { export tcr_el2; } +CopReg: tcr_el3 is Op0=3 & Op1_uimm3=6 & CRn=2 & CRm=0 & Op2_uimm3=2 & tcr_el3 { export tcr_el3; } +CopReg: vtcr_el2 is Op0=3 & Op1_uimm3=4 & CRn=2 & CRm=1 & Op2_uimm3=2 & vtcr_el2 { export vtcr_el2; } +CopReg: afsr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=5 & CRm=1 & Op2_uimm3=0 & afsr0_el1 { export afsr0_el1; } +CopReg: afsr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=5 & CRm=1 & Op2_uimm3=1 & afsr1_el1 { export afsr1_el1; } +CopReg: afsr0_el2 is Op0=3 & Op1_uimm3=4 & CRn=5 & CRm=1 & Op2_uimm3=0 & afsr0_el2 { export afsr0_el2; } +CopReg: afsr1_el2 is Op0=3 & Op1_uimm3=4 & CRn=5 & CRm=1 & Op2_uimm3=1 & afsr1_el2 { export afsr1_el2; } +CopReg: afsr0_el3 is Op0=3 & Op1_uimm3=6 & CRn=5 & CRm=1 & Op2_uimm3=0 & afsr0_el3 { export afsr0_el3; } +CopReg: afsr1_el3 is Op0=3 & Op1_uimm3=6 & CRn=5 & CRm=1 & Op2_uimm3=1 & afsr1_el3 { export afsr1_el3; } +CopReg: esr_el1 is Op0=3 & Op1_uimm3=0 & CRn=5 & CRm=2 & Op2_uimm3=0 & esr_el1 { export esr_el1; } +CopReg: esr_el2 is Op0=3 & Op1_uimm3=4 & CRn=5 & CRm=2 & Op2_uimm3=0 & esr_el2 { export esr_el2; } +CopReg: esr_el3 is Op0=3 & Op1_uimm3=6 & CRn=5 & CRm=2 & Op2_uimm3=0 & esr_el3 { export esr_el3; } +CopReg: fpexc32_el2 is Op0=3 & Op1_uimm3=4 & CRn=5 & CRm=3 & Op2_uimm3=0 & fpexc32_el2 { export fpexc32_el2; } +CopReg: far_el1 is Op0=3 & Op1_uimm3=0 & CRn=6 & CRm=0 & Op2_uimm3=0 & far_el1 { export far_el1; } +CopReg: far_el2 is Op0=3 & Op1_uimm3=4 & CRn=6 & CRm=0 & Op2_uimm3=0 & far_el2 { export far_el2; } +CopReg: far_el3 is Op0=3 & Op1_uimm3=6 & CRn=6 & CRm=0 & Op2_uimm3=0 & far_el3 { export far_el3; } +CopReg: hpfar_el2 is Op0=3 & Op1_uimm3=4 & CRn=6 & CRm=0 & Op2_uimm3=4 & hpfar_el2 { export hpfar_el2; } +CopReg: par_el1 is Op0=3 & Op1_uimm3=0 & CRn=7 & CRm=4 & Op2_uimm3=0 & par_el1 { export par_el1; } +CopReg: pmintenset_el1 is Op0=3 & Op1_uimm3=0 & CRn=9 & CRm=14 & Op2_uimm3=1 & pmintenset_el1 { export pmintenset_el1; } +CopReg: pmintenclr_el1 is Op0=3 & Op1_uimm3=0 & CRn=9 & CRm=14 & Op2_uimm3=2 & pmintenclr_el1 { export pmintenclr_el1; } +CopReg: pmcr_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=12 & Op2_uimm3=0 & pmcr_el0 { export pmcr_el0; } +CopReg: pmcntenset_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=12 & Op2_uimm3=1 & pmcntenset_el0 { export pmcntenset_el0; } +CopReg: pmcntenclr_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=12 & Op2_uimm3=2 & pmcntenclr_el0 { export pmcntenclr_el0; } +CopReg: pmovsclr_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=12 & Op2_uimm3=3 & pmovsclr_el0 { export pmovsclr_el0; } +CopReg: pmswinc_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=12 & Op2_uimm3=4 & pmswinc_el0 { export pmswinc_el0; } +CopReg: pmselr_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=12 & Op2_uimm3=5 & pmselr_el0 { export pmselr_el0; } +CopReg: pmceid0_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=12 & Op2_uimm3=6 & pmceid0_el0 { export pmceid0_el0; } +CopReg: pmceid1_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=12 & Op2_uimm3=7 & pmceid1_el0 { export pmceid1_el0; } +CopReg: pmccntr_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=13 & Op2_uimm3=0 & pmccntr_el0 { export pmccntr_el0; } +CopReg: pmxevtyper_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=13 & Op2_uimm3=1 & pmxevtyper_el0 { export pmxevtyper_el0; } +CopReg: pmxevcntr_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=13 & Op2_uimm3=2 & pmxevcntr_el0 { export pmxevcntr_el0; } +CopReg: pmuserenr_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=14 & Op2_uimm3=0 & pmuserenr_el0 { export pmuserenr_el0; } +CopReg: pmovsset_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=14 & Op2_uimm3=3 & pmovsset_el0 { export pmovsset_el0; } +CopReg: pmevcntr0_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=8 & Op2_uimm3=0 & pmevcntr0_el0 { export pmevcntr0_el0; } +CopReg: pmevcntr1_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=8 & Op2_uimm3=1 & pmevcntr1_el0 { export pmevcntr1_el0; } +CopReg: pmevcntr2_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=8 & Op2_uimm3=2 & pmevcntr2_el0 { export pmevcntr2_el0; } +CopReg: pmevcntr3_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=8 & Op2_uimm3=3 & pmevcntr3_el0 { export pmevcntr3_el0; } +CopReg: pmevcntr4_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=8 & Op2_uimm3=4 & pmevcntr4_el0 { export pmevcntr4_el0; } +CopReg: pmevcntr5_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=8 & Op2_uimm3=5 & pmevcntr5_el0 { export pmevcntr5_el0; } +CopReg: pmevcntr6_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=8 & Op2_uimm3=6 & pmevcntr6_el0 { export pmevcntr6_el0; } +CopReg: pmevcntr7_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=8 & Op2_uimm3=7 & pmevcntr7_el0 { export pmevcntr7_el0; } +CopReg: pmevcntr8_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=9 & Op2_uimm3=0 & pmevcntr8_el0 { export pmevcntr8_el0; } +CopReg: pmevcntr9_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=9 & Op2_uimm3=1 & pmevcntr9_el0 { export pmevcntr9_el0; } +CopReg: pmevcntr10_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=9 & Op2_uimm3=2 & pmevcntr10_el0 { export pmevcntr10_el0; } +CopReg: pmevcntr11_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=9 & Op2_uimm3=3 & pmevcntr11_el0 { export pmevcntr11_el0; } +CopReg: pmevcntr12_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=9 & Op2_uimm3=4 & pmevcntr12_el0 { export pmevcntr12_el0; } +CopReg: pmevcntr13_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=9 & Op2_uimm3=5 & pmevcntr13_el0 { export pmevcntr13_el0; } +CopReg: pmevcntr14_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=9 & Op2_uimm3=6 & pmevcntr14_el0 { export pmevcntr14_el0; } +CopReg: pmevcntr15_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=9 & Op2_uimm3=7 & pmevcntr15_el0 { export pmevcntr15_el0; } +CopReg: pmevcntr16_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=10 & Op2_uimm3=0 & pmevcntr16_el0 { export pmevcntr16_el0; } +CopReg: pmevcntr17_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=10 & Op2_uimm3=1 & pmevcntr17_el0 { export pmevcntr17_el0; } +CopReg: pmevcntr18_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=10 & Op2_uimm3=2 & pmevcntr18_el0 { export pmevcntr18_el0; } +CopReg: pmevcntr19_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=10 & Op2_uimm3=3 & pmevcntr19_el0 { export pmevcntr19_el0; } +CopReg: pmevcntr20_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=10 & Op2_uimm3=4 & pmevcntr20_el0 { export pmevcntr20_el0; } +CopReg: pmevcntr21_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=10 & Op2_uimm3=5 & pmevcntr21_el0 { export pmevcntr21_el0; } +CopReg: pmevcntr22_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=10 & Op2_uimm3=6 & pmevcntr22_el0 { export pmevcntr22_el0; } +CopReg: pmevcntr23_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=10 & Op2_uimm3=7 & pmevcntr23_el0 { export pmevcntr23_el0; } +CopReg: pmevcntr24_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=11 & Op2_uimm3=0 & pmevcntr24_el0 { export pmevcntr24_el0; } +CopReg: pmevcntr25_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=11 & Op2_uimm3=1 & pmevcntr25_el0 { export pmevcntr25_el0; } +CopReg: pmevcntr26_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=11 & Op2_uimm3=2 & pmevcntr26_el0 { export pmevcntr26_el0; } +CopReg: pmevcntr27_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=11 & Op2_uimm3=3 & pmevcntr27_el0 { export pmevcntr27_el0; } +CopReg: pmevcntr28_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=11 & Op2_uimm3=4 & pmevcntr28_el0 { export pmevcntr28_el0; } +CopReg: pmevcntr29_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=11 & Op2_uimm3=5 & pmevcntr29_el0 { export pmevcntr29_el0; } +CopReg: pmevcntr30_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=11 & Op2_uimm3=6 & pmevcntr30_el0 { export pmevcntr30_el0; } +CopReg: pmevtyper0_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=12 & Op2_uimm3=0 & pmevtyper0_el0 { export pmevtyper0_el0; } +CopReg: pmevtyper1_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=12 & Op2_uimm3=1 & pmevtyper1_el0 { export pmevtyper1_el0; } +CopReg: pmevtyper2_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=12 & Op2_uimm3=2 & pmevtyper2_el0 { export pmevtyper2_el0; } +CopReg: pmevtyper3_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=12 & Op2_uimm3=3 & pmevtyper3_el0 { export pmevtyper3_el0; } +CopReg: pmevtyper4_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=12 & Op2_uimm3=4 & pmevtyper4_el0 { export pmevtyper4_el0; } +CopReg: pmevtyper5_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=12 & Op2_uimm3=5 & pmevtyper5_el0 { export pmevtyper5_el0; } +CopReg: pmevtyper6_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=12 & Op2_uimm3=6 & pmevtyper6_el0 { export pmevtyper6_el0; } +CopReg: pmevtyper7_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=12 & Op2_uimm3=7 & pmevtyper7_el0 { export pmevtyper7_el0; } +CopReg: pmevtyper8_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=13 & Op2_uimm3=0 & pmevtyper8_el0 { export pmevtyper8_el0; } +CopReg: pmevtyper9_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=13 & Op2_uimm3=1 & pmevtyper9_el0 { export pmevtyper9_el0; } +CopReg: pmevtyper10_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=13 & Op2_uimm3=2 & pmevtyper10_el0 { export pmevtyper10_el0; } +CopReg: pmevtyper11_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=13 & Op2_uimm3=3 & pmevtyper11_el0 { export pmevtyper11_el0; } +CopReg: pmevtyper12_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=13 & Op2_uimm3=4 & pmevtyper12_el0 { export pmevtyper12_el0; } +CopReg: pmevtyper13_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=13 & Op2_uimm3=5 & pmevtyper13_el0 { export pmevtyper13_el0; } +CopReg: pmevtyper14_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=13 & Op2_uimm3=6 & pmevtyper14_el0 { export pmevtyper14_el0; } +CopReg: pmevtyper15_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=13 & Op2_uimm3=7 & pmevtyper15_el0 { export pmevtyper15_el0; } +CopReg: pmevtyper16_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=14 & Op2_uimm3=0 & pmevtyper16_el0 { export pmevtyper16_el0; } +CopReg: pmevtyper17_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=14 & Op2_uimm3=1 & pmevtyper17_el0 { export pmevtyper17_el0; } +CopReg: pmevtyper18_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=14 & Op2_uimm3=2 & pmevtyper18_el0 { export pmevtyper18_el0; } +CopReg: pmevtyper19_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=14 & Op2_uimm3=3 & pmevtyper19_el0 { export pmevtyper19_el0; } +CopReg: pmevtyper20_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=14 & Op2_uimm3=4 & pmevtyper20_el0 { export pmevtyper20_el0; } +CopReg: pmevtyper21_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=14 & Op2_uimm3=5 & pmevtyper21_el0 { export pmevtyper21_el0; } +CopReg: pmevtyper22_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=14 & Op2_uimm3=6 & pmevtyper22_el0 { export pmevtyper22_el0; } +CopReg: pmevtyper23_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=14 & Op2_uimm3=7 & pmevtyper23_el0 { export pmevtyper23_el0; } +CopReg: pmevtyper24_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=15 & Op2_uimm3=0 & pmevtyper24_el0 { export pmevtyper24_el0; } +CopReg: pmevtyper25_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=15 & Op2_uimm3=1 & pmevtyper25_el0 { export pmevtyper25_el0; } +CopReg: pmevtyper26_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=15 & Op2_uimm3=2 & pmevtyper26_el0 { export pmevtyper26_el0; } +CopReg: pmevtyper27_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=15 & Op2_uimm3=3 & pmevtyper27_el0 { export pmevtyper27_el0; } +CopReg: pmevtyper28_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=15 & Op2_uimm3=4 & pmevtyper28_el0 { export pmevtyper28_el0; } +CopReg: pmevtyper29_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=15 & Op2_uimm3=5 & pmevtyper29_el0 { export pmevtyper29_el0; } +CopReg: pmevtyper30_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=15 & Op2_uimm3=6 & pmevtyper30_el0 { export pmevtyper30_el0; } +CopReg: pmccfiltr_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=15 & Op2_uimm3=7 & pmccfiltr_el0 { export pmccfiltr_el0; } +CopReg: mair_el1 is Op0=3 & Op1_uimm3=0 & CRn=10 & CRm=2 & Op2_uimm3=0 & mair_el1 { export mair_el1; } +CopReg: mair_el2 is Op0=3 & Op1_uimm3=4 & CRn=10 & CRm=2 & Op2_uimm3=0 & mair_el2 { export mair_el2; } +CopReg: mair_el3 is Op0=3 & Op1_uimm3=6 & CRn=10 & CRm=2 & Op2_uimm3=0 & mair_el3 { export mair_el3; } +CopReg: amair_el1 is Op0=3 & Op1_uimm3=0 & CRn=10 & CRm=3 & Op2_uimm3=0 & amair_el1 { export amair_el1; } +CopReg: amair_el2 is Op0=3 & Op1_uimm3=4 & CRn=10 & CRm=3 & Op2_uimm3=0 & amair_el2 { export amair_el2; } +CopReg: amair_el3 is Op0=3 & Op1_uimm3=6 & CRn=10 & CRm=3 & Op2_uimm3=0 & amair_el3 { export amair_el3; } +CopReg: vbar_el1 is Op0=3 & Op1_uimm3=0 & CRn=12 & CRm=0 & Op2_uimm3=0 & vbar_el1 { export vbar_el1; } +CopReg: vbar_el2 is Op0=3 & Op1_uimm3=4 & CRn=12 & CRm=0 & Op2_uimm3=0 & vbar_el2 { export vbar_el2; } +CopReg: vbar_el3 is Op0=3 & Op1_uimm3=6 & CRn=12 & CRm=0 & Op2_uimm3=0 & vbar_el3 { export vbar_el3; } +CopReg: rvbar_el1 is Op0=3 & Op1_uimm3=0 & CRn=12 & CRm=0 & Op2_uimm3=1 & rvbar_el1 { export rvbar_el1; } +CopReg: rvbar_el2 is Op0=3 & Op1_uimm3=4 & CRn=12 & CRm=0 & Op2_uimm3=1 & rvbar_el2 { export rvbar_el2; } +CopReg: rvbar_el3 is Op0=3 & Op1_uimm3=6 & CRn=12 & CRm=0 & Op2_uimm3=1 & rvbar_el3 { export rvbar_el3; } +CopReg: rmr_el1 is Op0=3 & Op1_uimm3=0 & CRn=12 & CRm=0 & Op2_uimm3=2 & rmr_el1 { export rmr_el1; } +CopReg: rmr_el2 is Op0=3 & Op1_uimm3=4 & CRn=12 & CRm=0 & Op2_uimm3=2 & rmr_el2 { export rmr_el2; } +CopReg: rmr_el3 is Op0=3 & Op1_uimm3=6 & CRn=12 & CRm=0 & Op2_uimm3=2 & rmr_el3 { export rmr_el3; } +CopReg: isr_el1 is Op0=3 & Op1_uimm3=0 & CRn=12 & CRm=1 & Op2_uimm3=0 & isr_el1 { export isr_el1; } +CopReg: contextidr_el1 is Op0=3 & Op1_uimm3=0 & CRn=13 & CRm=0 & Op2_uimm3=1 & contextidr_el1 { export contextidr_el1; } +CopReg: tpidr_el0 is Op0=3 & Op1_uimm3=3 & CRn=13 & CRm=0 & Op2_uimm3=2 & tpidr_el0 { export tpidr_el0; } +CopReg: tpidrro_el0 is Op0=3 & Op1_uimm3=3 & CRn=13 & CRm=0 & Op2_uimm3=3 & tpidrro_el0 { export tpidrro_el0; } +CopReg: tpidr_el1 is Op0=3 & Op1_uimm3=0 & CRn=13 & CRm=0 & Op2_uimm3=4 & tpidr_el1 { export tpidr_el1; } +CopReg: tpidr_el2 is Op0=3 & Op1_uimm3=4 & CRn=13 & CRm=0 & Op2_uimm3=2 & tpidr_el2 { export tpidr_el2; } +CopReg: tpidr_el3 is Op0=3 & Op1_uimm3=6 & CRn=13 & CRm=0 & Op2_uimm3=2 & tpidr_el3 { export tpidr_el3; } +CopReg: teecr32_el1 is Op0=2 & Op1_uimm3=2 & CRn=0 & CRm=0 & Op2_uimm3=0 & teecr32_el1 { export teecr32_el1; } +CopReg: cntfrq_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=0 & Op2_uimm3=0 & cntfrq_el0 { export cntfrq_el0; } +CopReg: cntpct_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=0 & Op2_uimm3=1 & cntpct_el0 { export cntpct_el0; } +CopReg: cntvct_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=0 & Op2_uimm3=2 & cntvct_el0 { export cntvct_el0; } +CopReg: cntvoff_el2 is Op0=3 & Op1_uimm3=4 & CRn=14 & CRm=0 & Op2_uimm3=3 & cntvoff_el2 { export cntvoff_el2; } +CopReg: cntkctl_el1 is Op0=3 & Op1_uimm3=0 & CRn=14 & CRm=1 & Op2_uimm3=0 & cntkctl_el1 { export cntkctl_el1; } +CopReg: cnthctl_el2 is Op0=3 & Op1_uimm3=4 & CRn=14 & CRm=1 & Op2_uimm3=0 & cnthctl_el2 { export cnthctl_el2; } +CopReg: cntp_tval_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=2 & Op2_uimm3=0 & cntp_tval_el0 { export cntp_tval_el0; } +CopReg: cntp_ctl_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=2 & Op2_uimm3=1 & cntp_ctl_el0 { export cntp_ctl_el0; } +CopReg: cntp_cval_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=2 & Op2_uimm3=2 & cntp_cval_el0 { export cntp_cval_el0; } +CopReg: cntv_tval_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=3 & Op2_uimm3=0 & cntv_tval_el0 { export cntv_tval_el0; } +CopReg: cntv_ctl_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=3 & Op2_uimm3=1 & cntv_ctl_el0 { export cntv_ctl_el0; } +CopReg: cntv_cval_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=3 & Op2_uimm3=2 & cntv_cval_el0 { export cntv_cval_el0; } +CopReg: cnthp_tval_el2 is Op0=3 & Op1_uimm3=4 & CRn=14 & CRm=2 & Op2_uimm3=0 & cnthp_tval_el2 { export cnthp_tval_el2; } +CopReg: cnthp_ctl_el2 is Op0=3 & Op1_uimm3=4 & CRn=14 & CRm=2 & Op2_uimm3=1 & cnthp_ctl_el2 { export cnthp_ctl_el2; } +CopReg: cnthp_cval_el2 is Op0=3 & Op1_uimm3=4 & CRn=14 & CRm=2 & Op2_uimm3=2 & cnthp_cval_el2 { export cnthp_cval_el2; } +CopReg: cntps_tval_el1 is Op0=3 & Op1_uimm3=7 & CRn=14 & CRm=2 & Op2_uimm3=0 & cntps_tval_el1 { export cntps_tval_el1; } +CopReg: cntps_ctl_el1 is Op0=3 & Op1_uimm3=7 & CRn=14 & CRm=2 & Op2_uimm3=1 & cntps_ctl_el1 { export cntps_ctl_el1; } +CopReg: cntps_cval_el1 is Op0=3 & Op1_uimm3=7 & CRn=14 & CRm=2 & Op2_uimm3=2 & cntps_cval_el1 { export cntps_cval_el1; } +CopReg: dacr32_el2 is Op0=3 & Op1_uimm3=4 & CRn=3 & CRm=0 & Op2_uimm3=0 & dacr32_el2 { export dacr32_el2; } +CopReg: ifsr32_el2 is Op0=3 & Op1_uimm3=4 & CRn=5 & CRm=0 & Op2_uimm3=1 & ifsr32_el2 { export ifsr32_el2; } +CopReg: teehbr32_el1 is Op0=2 & Op1_uimm3=2 & CRn=1 & CRm=0 & Op2_uimm3=0 & teehbr32_el1 { export teehbr32_el1; } +CopReg: sder32_el3 is Op0=3 & Op1_uimm3=6 & CRn=1 & CRm=1 & Op2_uimm3=1 & sder32_el3 { export sder32_el3; } +CopReg: osdtrrx_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=0 & Op2_uimm3=2 & osdtrrx_el1 { export osdtrrx_el1; } + +CopReg: mdccint_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=0 & mdccint_el1 { export mdccint_el1; } +CopReg: mdscr_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=2 & mdscr_el1 { export mdscr_el1; } +CopReg: osdtrtx_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=3 & Op2_uimm3=2 & osdtrtx_el1 { export osdtrtx_el1; } +CopReg: oseccr_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=6 & Op2_uimm3=2 & oseccr_el1 { export oseccr_el1; } +CopReg: dbgbvr0_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=0 & Op2_uimm3=4 & dbgbvr0_el1 { export dbgbvr0_el1; } +CopReg: dbgbvr1_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=4 & dbgbvr1_el1 { export dbgbvr1_el1; } +CopReg: dbgbvr2_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=4 & dbgbvr2_el1 { export dbgbvr2_el1; } +CopReg: dbgbvr3_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=3 & Op2_uimm3=4 & dbgbvr3_el1 { export dbgbvr3_el1; } +CopReg: dbgbvr4_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=4 & Op2_uimm3=4 & dbgbvr4_el1 { export dbgbvr4_el1; } +CopReg: dbgbvr5_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=5 & Op2_uimm3=4 & dbgbvr5_el1 { export dbgbvr5_el1; } +CopReg: dbgbvr6_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=6 & Op2_uimm3=4 & dbgbvr6_el1 { export dbgbvr6_el1; } +CopReg: dbgbvr7_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=7 & Op2_uimm3=4 & dbgbvr7_el1 { export dbgbvr7_el1; } +CopReg: dbgbvr8_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=8 & Op2_uimm3=4 & dbgbvr8_el1 { export dbgbvr8_el1; } +CopReg: dbgbvr9_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=9 & Op2_uimm3=4 & dbgbvr9_el1 { export dbgbvr9_el1; } +CopReg: dbgbvr10_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=10 & Op2_uimm3=4 & dbgbvr10_el1 { export dbgbvr10_el1; } +CopReg: dbgbvr11_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=11 & Op2_uimm3=4 & dbgbvr11_el1 { export dbgbvr11_el1; } +CopReg: dbgbvr12_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=12 & Op2_uimm3=4 & dbgbvr12_el1 { export dbgbvr12_el1; } +CopReg: dbgbvr13_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=13 & Op2_uimm3=4 & dbgbvr13_el1 { export dbgbvr13_el1; } +CopReg: dbgbvr14_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=14 & Op2_uimm3=4 & dbgbvr14_el1 { export dbgbvr14_el1; } +CopReg: dbgbvr15_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=15 & Op2_uimm3=4 & dbgbvr15_el1 { export dbgbvr15_el1; } +CopReg: dbgbcr0_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=0 & Op2_uimm3=5 & dbgbcr0_el1 { export dbgbcr0_el1; } +CopReg: dbgbcr1_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=5 & dbgbcr1_el1 { export dbgbcr1_el1; } +CopReg: dbgbcr2_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=5 & dbgbcr2_el1 { export dbgbcr2_el1; } +CopReg: dbgbcr3_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=3 & Op2_uimm3=5 & dbgbcr3_el1 { export dbgbcr3_el1; } +CopReg: dbgbcr4_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=4 & Op2_uimm3=5 & dbgbcr4_el1 { export dbgbcr4_el1; } +CopReg: dbgbcr5_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=5 & Op2_uimm3=5 & dbgbcr5_el1 { export dbgbcr5_el1; } +CopReg: dbgbcr6_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=6 & Op2_uimm3=5 & dbgbcr6_el1 { export dbgbcr6_el1; } +CopReg: dbgbcr7_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=7 & Op2_uimm3=5 & dbgbcr7_el1 { export dbgbcr7_el1; } +CopReg: dbgbcr8_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=8 & Op2_uimm3=5 & dbgbcr8_el1 { export dbgbcr8_el1; } +CopReg: dbgbcr9_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=9 & Op2_uimm3=5 & dbgbcr9_el1 { export dbgbcr9_el1; } +CopReg: dbgbcr10_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=10 & Op2_uimm3=5 & dbgbcr10_el1 { export dbgbcr10_el1; } +CopReg: dbgbcr11_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=11 & Op2_uimm3=5 & dbgbcr11_el1 { export dbgbcr11_el1; } +CopReg: dbgbcr12_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=12 & Op2_uimm3=5 & dbgbcr12_el1 { export dbgbcr12_el1; } +CopReg: dbgbcr13_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=13 & Op2_uimm3=5 & dbgbcr13_el1 { export dbgbcr13_el1; } +CopReg: dbgbcr14_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=14 & Op2_uimm3=5 & dbgbcr14_el1 { export dbgbcr14_el1; } +CopReg: dbgbcr15_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=15 & Op2_uimm3=5 & dbgbcr15_el1 { export dbgbcr15_el1; } +CopReg: dbgwvr0_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=0 & Op2_uimm3=6 & dbgwvr0_el1 { export dbgwvr0_el1; } +CopReg: dbgwvr1_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=6 & dbgwvr1_el1 { export dbgwvr1_el1; } +CopReg: dbgwvr2_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=6 & dbgwvr2_el1 { export dbgwvr2_el1; } +CopReg: dbgwvr3_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=3 & Op2_uimm3=6 & dbgwvr3_el1 { export dbgwvr3_el1; } +CopReg: dbgwvr4_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=4 & Op2_uimm3=6 & dbgwvr4_el1 { export dbgwvr4_el1; } +CopReg: dbgwvr5_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=5 & Op2_uimm3=6 & dbgwvr5_el1 { export dbgwvr5_el1; } +CopReg: dbgwvr6_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=6 & Op2_uimm3=6 & dbgwvr6_el1 { export dbgwvr6_el1; } +CopReg: dbgwvr7_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=7 & Op2_uimm3=6 & dbgwvr7_el1 { export dbgwvr7_el1; } +CopReg: dbgwvr8_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=8 & Op2_uimm3=6 & dbgwvr8_el1 { export dbgwvr8_el1; } +CopReg: dbgwvr9_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=9 & Op2_uimm3=6 & dbgwvr9_el1 { export dbgwvr9_el1; } +CopReg: dbgwvr10_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=10 & Op2_uimm3=6 & dbgwvr10_el1 { export dbgwvr10_el1; } +CopReg: dbgwvr11_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=11 & Op2_uimm3=6 & dbgwvr11_el1 { export dbgwvr11_el1; } +CopReg: dbgwvr12_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=12 & Op2_uimm3=6 & dbgwvr12_el1 { export dbgwvr12_el1; } +CopReg: dbgwvr13_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=13 & Op2_uimm3=6 & dbgwvr13_el1 { export dbgwvr13_el1; } +CopReg: dbgwvr14_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=14 & Op2_uimm3=6 & dbgwvr14_el1 { export dbgwvr14_el1; } +CopReg: dbgwvr15_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=15 & Op2_uimm3=6 & dbgwvr15_el1 { export dbgwvr15_el1; } +CopReg: dbgwcr0_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=0 & Op2_uimm3=7 & dbgwcr0_el1 { export dbgwcr0_el1; } +CopReg: dbgwcr1_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=7 & dbgwcr1_el1 { export dbgwcr1_el1; } +CopReg: dbgwcr2_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=7 & dbgwcr2_el1 { export dbgwcr2_el1; } +CopReg: dbgwcr3_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=3 & Op2_uimm3=7 & dbgwcr3_el1 { export dbgwcr3_el1; } +CopReg: dbgwcr4_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=4 & Op2_uimm3=7 & dbgwcr4_el1 { export dbgwcr4_el1; } +CopReg: dbgwcr5_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=5 & Op2_uimm3=7 & dbgwcr5_el1 { export dbgwcr5_el1; } +CopReg: dbgwcr6_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=6 & Op2_uimm3=7 & dbgwcr6_el1 { export dbgwcr6_el1; } +CopReg: dbgwcr7_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=7 & Op2_uimm3=7 & dbgwcr7_el1 { export dbgwcr7_el1; } +CopReg: dbgwcr8_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=8 & Op2_uimm3=7 & dbgwcr8_el1 { export dbgwcr8_el1; } +CopReg: dbgwcr9_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=9 & Op2_uimm3=7 & dbgwcr9_el1 { export dbgwcr9_el1; } +CopReg: dbgwcr10_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=10 & Op2_uimm3=7 & dbgwcr10_el1 { export dbgwcr10_el1; } +CopReg: dbgwcr11_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=11 & Op2_uimm3=7 & dbgwcr11_el1 { export dbgwcr11_el1; } +CopReg: dbgwcr12_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=12 & Op2_uimm3=7 & dbgwcr12_el1 { export dbgwcr12_el1; } +CopReg: dbgwcr13_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=13 & Op2_uimm3=7 & dbgwcr13_el1 { export dbgwcr13_el1; } +CopReg: dbgwcr14_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=14 & Op2_uimm3=7 & dbgwcr14_el1 { export dbgwcr14_el1; } +CopReg: dbgwcr15_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=15 & Op2_uimm3=7 & dbgwcr15_el1 { export dbgwcr15_el1; } +CopReg: mdrar_el1 is Op0=2 & Op1_uimm3=0 & CRn=1 & CRm=0 & Op2_uimm3=0 & mdrar_el1 { export mdrar_el1; } +CopReg: oslar_el1 is Op0=2 & Op1_uimm3=0 & CRn=1 & CRm=0 & Op2_uimm3=4 & oslar_el1 { export oslar_el1; } +CopReg: oslsr_el1 is Op0=2 & Op1_uimm3=0 & CRn=1 & CRm=1 & Op2_uimm3=4 & oslsr_el1 { export oslsr_el1; } +CopReg: osdlr_el1 is Op0=2 & Op1_uimm3=0 & CRn=1 & CRm=3 & Op2_uimm3=4 & osdlr_el1 { export osdlr_el1; } +CopReg: dbgprcr_el1 is Op0=2 & Op1_uimm3=0 & CRn=1 & CRm=4 & Op2_uimm3=4 & dbgprcr_el1 { export dbgprcr_el1; } +CopReg: dbgclaimset_el1 is Op0=2 & Op1_uimm3=0 & CRn=7 & CRm=8 & Op2_uimm3=6 & dbgclaimset_el1 { export dbgclaimset_el1; } +CopReg: dbgclaimclr_el1 is Op0=2 & Op1_uimm3=0 & CRn=7 & CRm=9 & Op2_uimm3=6 & dbgclaimclr_el1 { export dbgclaimclr_el1; } +CopReg: dbgauthstatus_el1 is Op0=2 & Op1_uimm3=0 & CRn=7 & CRm=14 & Op2_uimm3=6 & dbgauthstatus_el1 { export dbgauthstatus_el1; } +CopReg: mdccsr_el0 is Op0=2 & Op1_uimm3=3 & CRn=0 & CRm=1 & Op2_uimm3=0 & mdccsr_el0 { export mdccsr_el0; } +CopReg: dbgdtr_el0 is Op0=2 & Op1_uimm3=3 & CRn=0 & CRm=4 & Op2_uimm3=0 & dbgdtr_el0 { export dbgdtr_el0; } +CopReg: dbgvcr32_el2 is Op0=2 & Op1_uimm3=4 & CRn=0 & CRm=7 & Op2_uimm3=0 & dbgvcr32_el2 { export dbgvcr32_el2; } +# The SysReg document implies that GMID_EL1 can only be read - the doc only provides pseudocode for read access. +# However, the register is in this block (without a required value for 'l') because that might not be fully accurate. +CopReg: gmid_el1 is Op0=3 & Op1_uimm3=1 & CRn=0 & CRm=0 & Op2_uimm3=4 & gmid_el1 { export gmid_el1; } +CopReg: ssbs is Op0=3 & Op1_uimm3=3 & CRn=4 & CRm=2 & Op2_uimm3=6 & ssbs { export ssbs; } +} # with : (l=0 | l=1) { + +CopReg: dbgdtrrx_el0 is l=0 & Op0=2 & Op1_uimm3=3 & CRn=0 & CRm=5 & Op2_uimm3=0 & dbgdtrrx_el0 { export dbgdtrrx_el0; } +CopReg: dbgdtrtx_el0 is l=1 & Op0=2 & Op1_uimm3=3 & CRn=0 & CRm=5 & Op2_uimm3=0 & dbgdtrtx_el0 { export dbgdtrtx_el0; } + +CopReg: "sreg("^Op0^", "^Op1_uimm3^", c"^CRn^", c"^CRm^", "^Op2_uimm3^")" is l=1 & Op0 & Op1_uimm3 & CRn & CRm & Op2_uimm3 { tmp:8 = UnkSytemRegRead(Op0:1, Op1_uimm3:1, CRn:1, CRm:1, Op2_uimm3:1); export tmp; } +CopReg: "sreg("^Op0^", "^Op1_uimm3^", c"^CRn^", c"^CRm^", "^Op2_uimm3^")" is l=0 & Op0 & Op1_uimm3 & CRn & CRm & Op2_uimm3 & Rt_GPR64 { tmp:8 = UnkSytemRegWrite(Op0:1, Op1_uimm3:1, CRn:1, CRm:1, Op2_uimm3:1, Rt_GPR64); export tmp; } + +PState_pstate_op: "DAIFSet" is Op1_uimm3=3 & Op2_uimm3=6 & CRm { daif = (CRm << 6) | daif; } +PState_pstate_op: "DAIFClr" is Op1_uimm3=3 & Op2_uimm3=7 & CRm { tmp:8 = CRm; daif = (~(tmp << 6)) & daif; } +PState_pstate_op: "PState.UAO" is Op1_uimm3=0 & Op2_uimm3=3 & CRm { tmp:8 = CRm; uao = tmp & 1; } +PState_pstate_op: "PState.PAN" is Op1_uimm3=0 & Op2_uimm3=4 & CRm { tmp:8 = CRm; pan = tmp & 1; } +PState_pstate_op: "PState.SP" is Op1_uimm3=0 & Op2_uimm3=5 & CRm { tmp:8 = CRm; spsel = tmp & 1; } +PState_pstate_op: "PState.TCO" is Op1_uimm3=3 & Op2_uimm3=4 & CRm { tmp:8 = CRm; tco = tmp & 1; } +PState_pstate_op: "PState.ALLINT" is Op1_uimm3=1 & Op2_uimm3=0 & b_0911=0 & CRm { tmp:8 = CRm; allint = tmp & 1; } +PState_pstate_op: "PState.DIT" is Op1_uimm3=3 & Op2_uimm3=2 & CRm { tmp:8 = CRm; dit = tmp & 1; } +#PState_pstate_op: "PState.SVCRSM" is Op1_uimm3=3 & Op2_uimm3=3 & b_0911=1 & b_08 { tmp:8 = b_08; svcrsm = tmp & 1; } # see SMSTART/SMSTOP +#PState_pstate_op: "PState.SVCRZA" is Op1_uimm3=3 & Op2_uimm3=3 & b_0911=2 & b_08 { tmp:8 = b_08; svcrza = tmp & 1; } # see SMSTART/SMSTOP +#PState_pstate_op: "PState.SVZRMZA" is Op1_uimm3=3 & Op2_uimm3=3 & b_0911=3 & b_08 { tmp:8 = b_08; svcrsmza = tmp & 1; } # see SMSTART/SMSTOP +PState_pstate_op: "PState.SSBS" is Op1_uimm3=3 & Op2_uimm3=1 & CRm { tmp:8 = CRm; ssbs = tmp & 1; } + + + +# C6.2.228 MRS page C6-1683 line 99588 MATCH xd5300000/mask=xfff00000 +# C6.2.379 TSTART page C6-1979 line 116075 MATCH xd5233060/mask=xffffffe0 +# C6.2.380 TTEST page C6-1981 line 116175 MATCH xd5233160/mask=xffffffe0 +# CONSTRUCT xd5200000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst xd5200000/mask=xffe00000 --status noqemu + +:mrs Rt_GPR64, CopReg +is b_2431=0xd5 & b_2223=0 & l=1 & CopReg & Rt_GPR64 +{ + Rt_GPR64 = CopReg; +} + +# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f +# CONSTRUCT xd500401f/mask=xfff8f01f MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd500401f/mask=xfff8f01f --status nodest + +:msr PState_pstate_op, CRm_uimm4 +is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & PState_pstate_op & CRn=0x4 & CRm_uimm4 & Rt=0x1f +{ +} + +# CONSTRUCT xd5000000/mask=xffe00000 DID NOT MATCH ANY DOCUMENTED OPCODE +# AUNIT --inst xd5000000/mask=xffe00000 --status noqemu + +:msr CopReg, Rt_GPR64 +is b_2431=0xd5 & b_2223=0 & l=0 & CopReg & Rt_GPR64 +{ + CopReg = Rt_GPR64; +} + +# C6.2.231 MSUB page C6-1689 line 99963 MATCH x1b008000/mask=x7fe08000 +# C6.2.219 MNEG page C6-1666 line 98782 MATCH x1b00fc00/mask=x7fe0fc00 +# CONSTRUCT x1b008000/mask=xffe08000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x1b008000/mask=xffe08000 --status pass + +:msub Rd_GPR32, Rn_GPR32, Rm_GPR32, Ra_GPR32 +is sf=0 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=0 & Rm_GPR32 & op.dp3_o0=1 & Ra_GPR32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp_2:4 = Rn_GPR32 * Rm_GPR32; + tmp_1:4 = Ra_GPR32 - tmp_2; + Rd_GPR64 = zext(tmp_1); +} + +# C6.2.231 MSUB page C6-1689 line 99963 MATCH x1b008000/mask=x7fe08000 +# C6.2.219 MNEG page C6-1666 line 98782 MATCH x1b00fc00/mask=x7fe0fc00 +# CONSTRUCT x9b008000/mask=xffe08000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x9b008000/mask=xffe08000 --status pass + +:msub Rd_GPR64, Rn_GPR64, Rm_GPR64, Ra_GPR64 +is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=0 & Rm_GPR64 & op.dp3_o0=1 & Ra_GPR64 & Rn_GPR64 & Rd_GPR64 +{ + tmp_2:8 = Rn_GPR64 * Rm_GPR64; + tmp_1:8 = Ra_GPR64 - tmp_2; + Rd_GPR64 = tmp_1; +} + +# C6.2.232 MUL page C6-1691 line 100073 MATCH x1b007c00/mask=x7fe0fc00 +# C6.2.218 MADD page C6-1664 line 98671 MATCH x1b000000/mask=x7fe08000 +# CONSTRUCT x1b007c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x1b007c00/mask=xffe0fc00 --status pass + +:mul Rd_GPR32, Rn_GPR32, Rm_GPR32 +is sf=0 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=0 & Rm_GPR32 & op.dp3_o0=0 & Ra=0x1f & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp_2:4 = Rn_GPR32 * Rm_GPR32; + Rd_GPR64 = zext(tmp_2); +} + +# C6.2.232 MUL page C6-1691 line 100073 MATCH x1b007c00/mask=x7fe0fc00 +# C6.2.218 MADD page C6-1664 line 98671 MATCH x1b000000/mask=x7fe08000 +# CONSTRUCT x9b007c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x9b007c00/mask=xffe0fc00 --status pass + +:mul Rd_GPR64, Rn_GPR64, Rm_GPR64 +is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=0 & Rm_GPR64 & op.dp3_o0=0 & Ra=0x1f & Rn_GPR64 & Rd_GPR64 +{ + tmp_2:8 = Rn_GPR64 * Rm_GPR64; + Rd_GPR64 = tmp_2; +} + +# C6.2.233 MVN page C6-1692 line 100146 MATCH x2a2003e0/mask=x7f2003e0 +# C6.2.239 ORN (shifted register) page C6-1703 line 100663 MATCH x2a200000/mask=x7f200000 +# CONSTRUCT x2a2003e0/mask=xff2003e0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x2a2003e0/mask=xff2003e0 --status pass + +:mvn Rd_GPR32, RegShift32Log +is sf=0 & opc=1 & b_2428=0xa & N=1 & RegShift32Log & Rn=0x1f & Rd_GPR32 & Rd_GPR64 +{ + tmp_1:4 = ~RegShift32Log; + Rd_GPR64 = zext(tmp_1); +} + +# C6.2.233 MVN page C6-1692 line 100146 MATCH x2a2003e0/mask=x7f2003e0 +# C6.2.239 ORN (shifted register) page C6-1703 line 100663 MATCH x2a200000/mask=x7f200000 +# CONSTRUCT xaa2003e0/mask=xff2003e0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xaa2003e0/mask=xff2003e0 --status pass + +:mvn Rd_GPR64, RegShift64Log +is sf=1 & opc=1 & b_2428=0xa & N=1 & Rm_GPR64 & RegShift64Log & Rn=0x1f & Rd_GPR64 +{ + tmp_1:8 = ~RegShift64Log; + Rd_GPR64 = tmp_1; +} + +# C6.2.234 NEG (shifted register) page C6-1694 line 100243 MATCH x4b0003e0/mask=x7f2003e0 +# C6.2.358 SUB (shifted register) page C6-1945 line 114221 MATCH x4b000000/mask=x7f200000 +# CONSTRUCT x4b0003e0/mask=xff2003e0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x4b0003e0/mask=xff2003e0 --status pass + +:neg Rd_GPR32, RegShift32 +is sf=0 & op=1 & s=0 & b_2428=0xb & b_2121=0 & RegShift32 & Rn=0x1f & Rd_GPR32 & Rd_GPR64 +{ + tmp_2:4 = RegShift32; + tmp_1:4 = - tmp_2; + Rd_GPR64 = zext(tmp_1); +} + +# C6.2.234 NEG (shifted register) page C6-1694 line 100243 MATCH x4b0003e0/mask=x7f2003e0 +# C6.2.358 SUB (shifted register) page C6-1945 line 114221 MATCH x4b000000/mask=x7f200000 +# CONSTRUCT xcb0003e0/mask=xff2003e0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xcb0003e0/mask=xff2003e0 --status pass + +:neg Rd_GPR64, RegShift64 +is sf=1 & op=1 & s=0 & b_2428=0xb & b_2121=0 & RegShift64 & Rn=0x1f & Rd_GPR64 +{ + tmp_2:8 = RegShift64; + tmp_1:8 = - tmp_2; + Rd_GPR64 = tmp_1; +} + +# C6.2.235 NEGS page C6-1696 line 100340 MATCH x6b0003e0/mask=x7f2003e0 +# C6.2.64 CMP (shifted register) page C6-1256 line 73623 MATCH x6b00001f/mask=x7f20001f +# C6.2.364 SUBS (shifted register) page C6-1955 line 114807 MATCH x6b000000/mask=x7f200000 +# CONSTRUCT x6b0003e0/mask=xff2003e0 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst x6b0003e0/mask=xff2003e0 --status pass --comment "flags" + +:negs Rd_GPR32, RegShift32 +is sf=0 & op=1 & s=1 & b_2428=0xb & b_2121=0 & RegShift32 & Rn=0x1f & Rd_GPR32 & Rd & Rd_GPR64 +{ + tmp_2:4 = RegShift32; + subflags0(tmp_2); + tmp_1:4 = 0:4 - tmp_2; + resultflags(tmp_1); + Rd_GPR64 = zext(tmp_1); + affectflags(); +} + +# C6.2.235 NEGS page C6-1696 line 100340 MATCH x6b0003e0/mask=x7f2003e0 +# C6.2.64 CMP (shifted register) page C6-1256 line 73623 MATCH x6b00001f/mask=x7f20001f +# C6.2.364 SUBS (shifted register) page C6-1955 line 114807 MATCH x6b000000/mask=x7f200000 +# CONSTRUCT xeb0003e0/mask=xff2003e0 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst xeb0003e0/mask=xff2003e0 --status pass --comment "flags" + +:negs Rd_GPR64, RegShift64 +is sf=1 & op=1 & s=1 & b_2428=0xb & b_2121=0 & RegShift64 & Rn=0x1f & Rd_GPR64 & Rd +{ + tmp_2:8 = RegShift64; + subflags0(tmp_2); + tmp_1:8 = 0:8 - tmp_2; + resultflags(tmp_1); + Rd_GPR64 = tmp_1; + affectflags(); +} + +# C6.2.236 NGC page C6-1698 line 100437 MATCH x5a0003e0/mask=x7fe0ffe0 +# C6.2.265 SBC page C6-1747 line 102973 MATCH x5a000000/mask=x7fe0fc00 +# CONSTRUCT x5a0003e0/mask=xffe0ffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x5a0003e0/mask=xffe0ffe0 --status pass --comment "flags" + +:ngc Rd_GPR32, Rm_GPR32 +is sf=0 & op=1 & s=0 & b_2428=0x1a & b_2123=0 & Rm_GPR32 & opcode2=0x0 & Rn=0x1f & Rd_GPR32 & Rd_GPR64 +{ + tmp:4 = Rm_GPR32 + zext(!CY); + Rd_GPR64 = zext(-tmp); +} + +# C6.2.236 NGC page C6-1698 line 100437 MATCH x5a0003e0/mask=x7fe0ffe0 +# C6.2.265 SBC page C6-1747 line 102973 MATCH x5a000000/mask=x7fe0fc00 +# CONSTRUCT xda0003e0/mask=xffe0ffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xda0003e0/mask=xffe0ffe0 --status pass --comment "flags" + +:ngc Rd_GPR64, Rm_GPR64 +is sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=0 & Rm_GPR64 & opcode2=0x0 & Rn=0x1f & Rd_GPR64 +{ + tmp:8 = Rm_GPR64 + zext(!CY); + Rd_GPR64 = -tmp; +} + +# C6.2.237 NGCS page C6-1700 line 100524 MATCH x7a0003e0/mask=x7fe0ffe0 +# C6.2.266 SBCS page C6-1749 line 103074 MATCH x7a000000/mask=x7fe0fc00 +# CONSTRUCT x7a0003e0/mask=xffe0ffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x7a0003e0/mask=xffe0ffe0 --status pass --comment "flags" + +:ngcs Rd_GPR32, Rm_GPR32 +is sf=0 & op=1 & s=1 & b_2428=0x1a & b_2123=0 & Rn=0x1f & opcode2=0x0 & Rm_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp:4 = Rm_GPR32 + zext(!CY); + add_with_carry_flags(0,~tmp); + Rd_GPR64 = zext(-tmp); + resultflags(Rd_GPR32); + affectflags(); +} + +# C6.2.237 NGCS page C6-1700 line 100524 MATCH x7a0003e0/mask=x7fe0ffe0 +# C6.2.266 SBCS page C6-1749 line 103074 MATCH x7a000000/mask=x7fe0fc00 +# CONSTRUCT xfa0003e0/mask=xffe0ffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xfa0003e0/mask=xffe0ffe0 --status pass --comment "flags" + +:ngcs Rd_GPR64, Rm_GPR64 +is sf=1 & op=1 & s=1 & b_2428=0x1a & b_2123=0 & Rn=0x1f & opcode2=0x0 & Rm_GPR64 & Rd_GPR64 +{ + tmp:8 = Rm_GPR64 + zext(!CY); + add_with_carry_flags(0,~tmp); + Rd_GPR64 = -tmp; + resultflags(Rd_GPR64); + affectflags(); +} + +# C6.2.238 NOP page C6-1702 line 100611 MATCH xd503201f/mask=xffffffff +# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f +# CONSTRUCT xd503201f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd503201f/mask=xffffffff --status nodest + +:nop +is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low=0 & Rt=0x1f +{ +} + +# C6.2.239 ORN (shifted register) page C6-1703 line 100663 MATCH x2a200000/mask=x7f200000 +# C6.2.233 MVN page C6-1692 line 100146 MATCH x2a2003e0/mask=x7f2003e0 +# CONSTRUCT x2a200000/mask=xff200000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x2a200000/mask=xff200000 --status pass + +:orn Rd_GPR32, Rn_GPR32, RegShift32Log +is sf=0 & opc=1 & b_2428=0xa & N=1 & RegShift32Log & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp_3:4 = RegShift32Log; + tmp_2:4 = tmp_3 ^ -1:4; + tmp_1:4 = Rn_GPR32 | tmp_2; + Rd_GPR64 = zext(tmp_1); +} + +# C6.2.239 ORN (shifted register) page C6-1703 line 100663 MATCH x2a200000/mask=x7f200000 +# C6.2.233 MVN page C6-1692 line 100146 MATCH x2a2003e0/mask=x7f2003e0 +# CONSTRUCT xaa200000/mask=xff200000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xaa200000/mask=xff200000 --status pass + +:orn Rd_GPR64, Rn_GPR64, RegShift64Log +is sf=1 & opc=1 & b_2428=0xa & N=1 & RegShift64Log & Rn_GPR64 & Rd_GPR64 +{ + tmp_3:8= RegShift64Log; + tmp_2:8 = tmp_3 ^ -1:8; + tmp_1:8 = Rn_GPR64 | tmp_2; + Rd_GPR64 = tmp_1; +} + +# C6.2.240 ORR (immediate) page C6-1705 line 100779 MATCH x32000000/mask=x7f800000 +# C6.2.223 MOV (bitmask immediate) page C6-1673 line 99125 MATCH x320003e0/mask=x7f8003e0 +# CONSTRUCT x32000000/mask=xff800000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x32000000/mask=xff800000 --status pass + +:orr Rd_GPR32wsp, Rn_GPR32, DecodeWMask32 +is sf=0 & opc=1 & b_2428=0x12 & b_2323=0 & DecodeWMask32 & Rn_GPR32 & Rd_GPR32wsp & Rd_GPR64xsp +{ + tmp_1:4 = Rn_GPR32 | DecodeWMask32; + Rd_GPR64xsp = zext(tmp_1); +} + +# C6.2.240 ORR (immediate) page C6-1705 line 100779 MATCH x32000000/mask=x7f800000 +# C6.2.223 MOV (bitmask immediate) page C6-1673 line 99125 MATCH x320003e0/mask=x7f8003e0 +# CONSTRUCT xb2000000/mask=xff800000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xb2000000/mask=xff800000 --status pass + +:orr Rd_GPR64xsp, Rn_GPR64, DecodeWMask64 +is sf=1 & opc=1 & b_2428=0x12 & b_2323=0 & DecodeWMask64 & Rn_GPR64 & Rd_GPR64xsp +{ + tmp_1:8 = Rn_GPR64 | DecodeWMask64; + Rd_GPR64xsp = tmp_1; +} + +# C6.2.241 ORR (shifted register) page C6-1707 line 100882 MATCH x2a000000/mask=x7f200000 +# C6.2.224 MOV (register) page C6-1675 line 99214 MATCH x2a0003e0/mask=x7fe0ffe0 +# CONSTRUCT x2a000000/mask=xff200000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x2a000000/mask=xff200000 --status pass + +:orr Rd_GPR32, Rn_GPR32, RegShift32Log +is b_31=0 & b_2430=0b0101010 & b_21=0 & RegShift32Log & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp_2:4 = RegShift32Log; + tmp_1:4 = Rn_GPR32 | tmp_2; + Rd_GPR64 = zext(tmp_1); +} + +# C6.2.241 ORR (shifted register) page C6-1707 line 100882 MATCH x2a000000/mask=x7f200000 +# C6.2.224 MOV (register) page C6-1675 line 99214 MATCH x2a0003e0/mask=x7fe0ffe0 +# CONSTRUCT xaa000000/mask=xff200000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xaa000000/mask=xff200000 --status pass + +:orr Rd_GPR64, Rn_GPR64, RegShift64Log +is b_31=1 & b_2430=0b0101010 & b_21=0 & RegShift64Log & Rn_GPR64 & Rd_GPR64 +{ + tmp_2:8 = RegShift64Log; + tmp_1:8 = Rn_GPR64 | tmp_2; + Rd_GPR64 = tmp_1; +} + +# C6.2.242 PACDA, PACDZA page C6-1709 line 100996 MATCH xdac10800/mask=xffffdc00 +# CONSTRUCT xdac10800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xdac10800/mask=xfffffc00 --status noqemu +# z == 0 pacda variant + +:pacda Rd_GPR64, Rn_GPR64xsp +is pacda__PACpart & b_1431=0b110110101100000100 & b_1012=0b010 & b_13=0 & Rn_GPR64xsp & Rd_GPR64 +{ + build pacda__PACpart; +} + +# C6.2.242 PACDA, PACDZA page C6-1709 line 100996 MATCH xdac10800/mask=xffffdc00 +# CONSTRUCT xdac12be0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xdac12be0/mask=xffffffe0 --status noqemu +# z == 1 pacdza variant + +:pacdza Rd_GPR64 +is pacdza__PACpart & b_1431=0b110110101100000100 & b_1012=0b010 & b_13=1 & b_0509=0b11111 & Rd_GPR64 +{ + build pacdza__PACpart; +} + +# C6.2.243 PACDB, PACDZB page C6-1710 line 101067 MATCH xdac10c00/mask=xffffdc00 +# CONSTRUCT xdac10c00/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xdac10c00/mask=xfffffc00 --status noqemu +# z == 0 pacdb variant + +:pacdb Rd_GPR64, Rn_GPR64xsp +is pacdb__PACpart & b_1431=0b110110101100000100 & b_1012=0b011 & b_13=0 & Rn_GPR64xsp & Rd_GPR64 +{ + build pacdb__PACpart; +} + +# C6.2.243 PACDB, PACDZB page C6-1710 line 101067 MATCH xdac10c00/mask=xffffdc00 +# CONSTRUCT xdac12fe0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xdac12fe0/mask=xffffffe0 --status noqemu +# z == 1 pacdzb variant + +:pacdzb Rd_GPR64 +is pacdzb__PACpart & b_1431=0b110110101100000100 & b_1012=0b011 & b_13=1 & b_0509=0b11111 & Rd_GPR64 +{ + build pacdzb__PACpart; +} + +# C6.2.244 PACGA page C6-1711 line 101138 MATCH x9ac03000/mask=xffe0fc00 +# CONSTRUCT x9ac03000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x9ac03000/mask=xffe0fc00 --status noqemu + +:pacga Rd_GPR64, Rn_GPR64, Rm_GPR64xsp +is b_2131=0b10011010110 & b_1015=0b001100 & Rm_GPR64xsp & Rn_GPR64 & Rd_GPR64 +{ + # This operation, unlike all other PAC operations, does not put its output in + # the same register as its first input. This means that putting a "noclobber" + # variant on this operation would violate the definition of PACGA. + Rd_GPR64 = pacga(Rn_GPR64, Rm_GPR64xsp); +} + +# C6.2.245 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA page C6-1712 line 101196 MATCH xdac10000/mask=xffffdc00 +# CONSTRUCT xdac10000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xdac10000/mask=xfffffc00 --status noqemu +# Z == 0 PACIA variant + +:pacia Rd_GPR64, Rn_GPR64xsp +is pacia__PACpart & b_1431=0b110110101100000100 & b_1012=0b000 & b_13=0 & Rn_GPR64xsp & Rd_GPR64 +{ + build pacia__PACpart; +} + +# C6.2.245 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA page C6-1712 line 101196 MATCH xdac10000/mask=xffffdc00 +# CONSTRUCT xdac123e0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xdac123e0/mask=xffffffe0 --status noqemu +# Z == 1 && Rn == 11111 PACIZA variant + +:paciza Rd_GPR64 +is paciza__PACpart & b_1431=0b110110101100000100 & b_1012=0b000 & b_13=1 & b_0509=0b11111 & Rd_GPR64 +{ + build paciza__PACpart; +} + +# C6.2.245 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA page C6-1712 line 101196 MATCH xd503211f/mask=xfffffddf +# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f +# CONSTRUCT xd503211f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd503211f/mask=xffffffff --status nodest +# CRm == 0001 && op2 == 000 PICIA1716 variant + +:pacia1716 +is pacia1716__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0001 & b_0507=0b000 & b_0004=0b11111 +{ + build pacia1716__PACpart; +} + +# C6.2.245 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA page C6-1712 line 101196 MATCH xd503211f/mask=xfffffddf +# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f +# CONSTRUCT xd503233f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd503233f/mask=xffffffff --status nodest +# CRm == 0011 && op2 == 001 PACIASP variant + +:paciasp +is paciasp__PACpart & PACIXSP_BTITARGETS & b_1231=0b11010101000000110010 & b_0811=0b0011 & b_0507=0b001 & b_0004=0b11111 +{ + build paciasp__PACpart; +} + +# C6.2.245 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA page C6-1712 line 101196 MATCH xd503211f/mask=xfffffddf +# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f +# CONSTRUCT xd503231f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd503231f/mask=xffffffff --status nodest +# CRm == 0011 && op2 == 000 PACIAZ variant + +:paciaz +is paciaz__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0011 & b_0507=0b000 & b_0004=0b11111 +{ + build paciaz__PACpart; +} + +# C6.2.246 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB page C6-1715 line 101358 MATCH xdac10400/mask=xffffdc00 +# CONSTRUCT xdac10400/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xdac10400/mask=xfffffc00 --status noqemu +# Z == 0 PACIB variant + +:pacib Rd_GPR64, Rn_GPR64xsp +is pacib__PACpart & b_1431=0b110110101100000100 & b_1012=0b001 & b_13=0 & Rn_GPR64xsp & Rd_GPR64 +{ + build pacib__PACpart; +} + +# C6.2.246 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB page C6-1715 line 101358 MATCH xdac10400/mask=xffffdc00 +# CONSTRUCT xdac127e0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xdac127e0/mask=xffffffe0 --status noqemu +# Z == 1 && Rn = 11111 PACIZB variant + +:pacizb Rd_GPR64 +is pacizb__PACpart & b_1431=0b110110101100000100 & b_1012=0b001 & b_13=1 & b_0509=0b11111 & Rd_GPR64 +{ + build pacizb__PACpart; +} + +# C6.2.246 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB page C6-1715 line 101358 MATCH xd503215f/mask=xfffffddf +# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f +# CONSTRUCT xd503215f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd503215f/mask=xffffffff --status nodest +# CRm == 0001 && op2 == 010 PACIB1716 variant + +:pacib1716 +is pacib1716__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0001 & b_0507=0b010 & b_0004=0b11111 +{ + build pacib1716__PACpart; +} + +# C6.2.246 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB page C6-1715 line 101358 MATCH xd503215f/mask=xfffffddf +# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f +# CONSTRUCT xd503237f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd503237f/mask=xffffffff --status nodest +# CRm == 0011 && op2 == 011 PACIBSP variant + +:pacibsp +is pacibsp__PACpart & PACIXSP_BTITARGETS & b_1231=0b11010101000000110010 & b_0811=0b0011 & b_0507=0b011 & b_0004=0b11111 +{ + build pacibsp__PACpart; +} + +# C6.2.246 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB page C6-1715 line 101358 MATCH xd503215f/mask=xfffffddf +# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f +# CONSTRUCT xd503235f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd503235f/mask=xffffffff --status nodest +# CRm == 0011 && op2 == 010 PACIBZ variant + +:pacibz +is pacibz__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0011 & b_0507=0b010 & b_0004=0b11111 +{ + build pacibz__PACpart; +} + +# C6.2.247 PRFM (immediate) page C6-1718 line 101520 MATCH xf9800000/mask=xffc00000 +# CONSTRUCT xf9800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xf9800000/mask=xffc00000 --status nomem + +:prfm aa_prefetch, addrIndexed +is size.ldstr=3 & b_2729=7 & v=0 & b_2425=1 & b_2223=2 & addrIndexed & b_0304 & b_0102 & b_00 & aa_prefetch +{ + addr:8 = addrIndexed; + hint:1 = b_0304; + target:1 = b_0102; + stream:1 = b_00; + Hint_Prefetch(addr, hint, target, stream); +} + +# C6.2.248 PRFM (literal) page C6-1720 line 101616 MATCH xd8000000/mask=xff000000 +# CONSTRUCT xd8000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd8000000/mask=xff000000 --status nodest --comment "qemuerr(illegal addresses cause qemu exit)" + +:prfm aa_prefetch, Addr19 +is size.ldstr=3 & b_2729=3 & v=0 & b_2425=0 & Addr19 & b_0304 & b_0102 & b_00 & aa_prefetch +{ + addr:8 = &Addr19; + hint:1 = b_0304; + target:1 = b_0102; + stream:1 = b_00; + Hint_Prefetch(addr, hint, target, stream); +} + +# C6.2.249 PRFM (register) page C6-1722 line 101700 MATCH xf8a04800/mask=xffe04c00 +# CONSTRUCT xf8a00800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xf8a00800/mask=xffe00c00 --status nomem + +:prfm aa_prefetch, addrIndexed +is size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=1 & addrIndexed & b_1011=2 & b_0304 & b_0102 & b_00 & aa_prefetch +{ + addr:8 = addrIndexed; + hint:1 = b_0304; + target:1 = b_0102; + stream:1 = b_00; + Hint_Prefetch(addr, hint, target, stream); +} + +# C6.2.250 PRFUM page C6-1724 line 101815 MATCH xf8800000/mask=xffe00c00 +# CONSTRUCT xf8800000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xf8800000/mask=xfffffc00 --status nomem + +:prfum aa_prefetch, addr_SIMM9 +is size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=0 & addr_SIMM9 & simm9=0 & b_1011=0 & b_0304 & b_0102 & b_00 & aa_prefetch +{ + addr:8 = addr_SIMM9; + hint:1 = b_0304; + target:1 = b_0102; + stream:1 = b_00; + Hint_Prefetch(addr, hint, target, stream); +} + +# C6.2.250 PRFUM page C6-1724 line 101815 MATCH xf8800000/mask=xffe00c00 +# CONSTRUCT xf8800000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xf8800000/mask=xffe00c00 --status nomem + +:prfum aa_prefetch, addr_SIMM9 +is size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=0 & addr_SIMM9 & b_1011=0 & b_0304 & b_0102 & b_00 & aa_prefetch +{ + addr:8 = addr_SIMM9; + hint:1 = b_0304; + target:1 = b_0102; + stream:1 = b_00; + Hint_Prefetch(addr, hint, target, stream); +} + +# C6.2.253 RBIT page C6-1728 line 102006 MATCH x5ac00000/mask=x7ffffc00 +# CONSTRUCT x5ac00000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x5ac00000/mask=xfffffc00 --status pass + +:rbit Rd_GPR32, Rn_GPR32 +is sf=0 & b_3030=1 & S=0 & b_2428=0x1a & b_2123=6 & dp1.opcode2=0x0 & b_1015=0x0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + # The algorithm swaps 1, 2, 4, 8 bits, ect + local tmp:4 = Rn_GPR32; + tmp = (((tmp & 0xaaaaaaaa) >> 1) | ((tmp & 0x55555555) << 1)); + tmp = (((tmp & 0xcccccccc) >> 2) | ((tmp & 0x33333333) << 2)); + tmp = (((tmp & 0xf0f0f0f0) >> 4) | ((tmp & 0x0f0f0f0f) << 4)); + tmp = (((tmp & 0xff00ff00) >> 8) | ((tmp & 0x00ff00ff) << 8)); + tmp = ((tmp >> 16) | (tmp << 16)); + Rd_GPR64 = zext(tmp); +} + +# C6.2.253 RBIT page C6-1728 line 102006 MATCH x5ac00000/mask=x7ffffc00 +# CONSTRUCT xdac00000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xdac00000/mask=xfffffc00 --status pass + +:rbit Rd_GPR64, Rn_GPR64 +is sf=1 & b_3030=1 & S=0 & b_2428=0x1a & b_2123=6 & dp1.opcode2=0x0 & b_1015=0x0 & Rn_GPR64 & Rd_GPR64 +{ + # The algorithm swaps 1, 2, 4, 8 bits, ect + local tmp:8 = Rn_GPR64; + tmp = (((tmp & 0xaaaaaaaaaaaaaaaa) >> 1) | ((tmp & 0x5555555555555555) << 1)); + tmp = (((tmp & 0xcccccccccccccccc) >> 2) | ((tmp & 0x3333333333333333) << 2)); + tmp = (((tmp & 0xf0f0f0f0f0f0f0f0) >> 4) | ((tmp & 0x0f0f0f0f0f0f0f0f) << 4)); + tmp = (((tmp & 0xff00ff00ff00ff00) >> 8) | ((tmp & 0x00ff00ff00ff00ff) << 8)); + tmp = (((tmp & 0xffff0000ffff0000) >> 16) | ((tmp & 0x0000ffff0000ffff) << 16)); + Rd_GPR64 = ((tmp >> 32) | (tmp << 32)); +} + +# C6.2.254 RET page C6-1730 line 102090 MATCH xd65f0000/mask=xfffffc1f +# CONSTRUCT xd65f0000/mask=xfffffc1f MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd65f0000/mask=xfffffc1f --status nodest + +:ret Rn_GPR64 +is b_2531=0x6b & b_2324=0 & b_2122=2 & b_1620=0x1f & b_1015=0 & Rn_GPR64 & b_0004=0 +{ + pc = Rn_GPR64; + return [pc]; +} + +# C6.2.254 RET page C6-1730 line 102090 MATCH xd65f0000/mask=xfffffc1f +# CONSTRUCT xd65f03c0/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd65f03c0/mask=xffffffff --status nodest + +:ret +is b_2531=0x6b & b_2324=0 & b_2122=2 & b_1620=0x1f & b_1015=0 & aa_Xn=30 & b_0004=0 +{ + pc = x30; + return [pc]; +} + +# C6.2.255 RETAA, RETAB page C6-1731 line 102135 MATCH xd65f0bff/mask=xfffffbff +# CONSTRUCT xd65f0bff/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd65f0bff/mask=xffffffff --status nodest +# M == 0 RETAA variant + +:retaa +is retaa__PACpart & b_1131=0b110101100101111100001 & b_0009=0b1111111111 & b_10=0 +{ + build retaa__PACpart; + pc = x30; + return [pc]; +} + +# C6.2.255 RETAA, RETAB page C6-1731 line 102135 MATCH xd65f0bff/mask=xfffffbff +# CONSTRUCT xd65f0fff/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd65f0fff/mask=xffffffff --status nodest +# M == 1 RETAB variant + +:retab +is retab__PACpart & b_1131=0b110101100101111100001 & b_0009=0b1111111111 & b_10=1 +{ + build retab__PACpart; + pc = x30; + return [pc]; +} + +# C6.2.256 REV page C6-1732 line 102201 MATCH x5ac00800/mask=x7ffff800 +# CONSTRUCT x5ac00800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x5ac00800/mask=xfffffc00 --status pass +# sf == 0 && opc == 10 32-bit variant (3210 -> 0123) + +:rev Rd_GPR32, Rn_GPR32 +is b_1230=0b1011010110000000000 & b_31=0 & b_1011=0b10 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + local tmp:4 = Rn_GPR32; + tmp = (((tmp & 0xff00ff00) >> 8) | ((tmp & 0x00ff00ff) << 8)); + tmp = ((tmp >> 16) | (tmp << 16)); + Rd_GPR64 = zext(tmp); +} + +# C6.2.256 REV page C6-1732 line 102201 MATCH x5ac00800/mask=x7ffff800 +# C6.2.259 REV64 page C6-1738 line 102502 MATCH xdac00c00/mask=xfffffc00 +# CONSTRUCT xdac00c00/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xdac00c00/mask=xfffffc00 --status pass +# sf == 1 && opc == 11 64-bit variant (76543210 -> 01234567) +# NB equivalent to REV64, which is never the preferred disassembly + +:rev Rd_GPR64, Rn_GPR64 +is b_1230=0b1011010110000000000 & b_31=1 & b_1011=0b11 & Rn_GPR64 & Rd_GPR64 +{ + local tmp:8 = Rn_GPR64; + tmp = (((tmp & 0xff00ff00ff00ff00) >> 8) | ((tmp & 0x00ff00ff00ff00ff) << 8)); + tmp = (((tmp & 0xffff0000ffff0000) >> 16) | ((tmp & 0x0000ffff0000ffff) << 16)); + Rd_GPR64 = ((tmp >> 32) | (tmp << 32)); +} + +# C6.2.257 REV16 page C6-1734 line 102308 MATCH x5ac00400/mask=x7ffffc00 +# CONSTRUCT x5ac00400/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x5ac00400/mask=xfffffc00 --status pass +# sf == 0 (and opc == 01) 32-bit variant (3210 -> 2301) + +:rev16 Rd_GPR32, Rn_GPR32 +is b_1230=0b1011010110000000000 & b_31=0 & b_1011=0b01 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + local tmp:4 = Rn_GPR32; + tmp = (((tmp & 0xff00ff00) >> 8) | ((tmp & 0x00ff00ff) << 8)); + Rd_GPR64 = zext(tmp); +} + +# C6.2.257 REV16 page C6-1734 line 102308 MATCH x5ac00400/mask=x7ffffc00 +# CONSTRUCT xdac00400/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xdac00400/mask=xfffffc00 --status pass +# sf == 1 (and opc=01) 64-bit variant (76543210 -> 67452301) + +:rev16 Rd_GPR64, Rn_GPR64 +is b_1230=0b1011010110000000000 & b_31=1 & b_1011=0b01 & Rn_GPR64 & Rd_GPR64 +{ + local tmp:8 = Rn_GPR64; + Rd_GPR64 = (((tmp & 0xff00ff00ff00ff00) >> 8) | ((tmp & 0x00ff00ff00ff00ff) << 8)); +} + +# C6.2.258 REV32 page C6-1736 line 102412 MATCH xdac00800/mask=xfffffc00 +# C6.2.256 REV page C6-1732 line 102201 MATCH x5ac00800/mask=x7ffff800 +# CONSTRUCT xdac00800/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xdac00800/mask=xfffffc00 --status pass +# sf == 1 (and opc == 10) 64-bit variant (76543210 -> 45670123) + +:rev32 Rd_GPR64, Rn_GPR64 +is b_1230=0b1011010110000000000 & b_31=1 & b_1011=0b10 & Rn_GPR64 & Rd_GPR64 +{ + local tmp:8 = Rn_GPR64; + tmp = (((tmp & 0xff00ff00ff00ff00) >> 8) | ((tmp & 0x00ff00ff00ff00ff) << 8)); + Rd_GPR64 = (((tmp & 0xffff0000ffff0000) >> 16) | ((tmp & 0x0000ffff0000ffff) << 16)); +} + +# C6.2.260 RMIF page C6-1739 line 102566 MATCH xba000400/mask=xffe07c10 +# CONSTRUCT xba000400/mask=xffe07c10 MATCHED 1 DOCUMENTED OPCODES + +:rmif Rn_GPR64, UImm6, NZCVImm_uimm4 +is b_2131=0b10111010000 & b_1014=0b00001 & b_04=0b0 & Rn_GPR64 & UImm6 & NZCVImm_uimm4 +{ + tmp:8 = Rn_GPR64 >> UImm6; + condMask:1 = NZCVImm_uimm4; + set_NZCV(tmp,condMask); +} + +# C6.2.261 ROR (immediate) page C6-1740 line 102633 MATCH x13800000/mask=x7fa00000 +# C6.2.124 EXTR page C6-1477 line 87864 MATCH x13800000/mask=x7fa00000 +# CONSTRUCT x13800000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x13800000/mask=xffe00000 --status pass + +:ror Rd_GPR32, Rn_GPR32, LSB_bitfield32_imm +is sf=0 & b_2930=0 & b_2428=0x13 & b_2323=1 & n=0 & b_21=0 & Rn=Rm & Rm_GPR32 & LSB_bitfield32_imm & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + result:4 = (Rn_GPR32 >> LSB_bitfield32_imm) | (Rn_GPR32 << (32 - LSB_bitfield32_imm)); + Rd_GPR64 = zext(result); +} + +# C6.2.261 ROR (immediate) page C6-1740 line 102633 MATCH x13800000/mask=x7fa00000 +# C6.2.124 EXTR page C6-1477 line 87864 MATCH x13800000/mask=x7fa00000 +# CONSTRUCT x93c00000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x93c00000/mask=xffe00000 --status pass + +:ror Rd_GPR64, Rn_GPR64, LSB_bitfield64_imm +is sf=1 & b_2930=0 & b_2428=0x13 & b_2323=1 & n=1 & b_21=0 & Rn=Rm & Rm_GPR64 & LSB_bitfield64_imm & Rn_GPR64 & Rd_GPR64 +{ + result:8 = (Rn_GPR64 >> LSB_bitfield64_imm) | (Rn_GPR64 << (64 - LSB_bitfield64_imm)); + Rd_GPR64 = result; +} + +# C6.2.262 ROR (register) page C6-1742 line 102726 MATCH x1ac02c00/mask=x7fe0fc00 +# C6.2.263 RORV page C6-1744 line 102821 MATCH x1ac02c00/mask=x7fe0fc00 +# CONSTRUCT x1ac02c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x1ac02c00/mask=xffe0fc00 --status pass + +:ror Rd_GPR32, Rn_GPR32, Rm_GPR32 +is sf=0 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR32 & b_1015=0xb & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + rval:4 = Rm_GPR32 & 0x1f; + tmp_1:4 = ( Rn_GPR32 >> rval) | ( Rn_GPR32 << ( 32 - rval ) ); + Rd_GPR64 = zext(tmp_1); +} + +# C6.2.262 ROR (register) page C6-1742 line 102726 MATCH x1ac02c00/mask=x7fe0fc00 +# C6.2.263 RORV page C6-1744 line 102821 MATCH x1ac02c00/mask=x7fe0fc00 +# CONSTRUCT x9ac02c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x9ac02c00/mask=xffe0fc00 --status pass + +:ror Rd_GPR64, Rn_GPR64, Rm_GPR64 +is sf=1 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR64 & b_1015=0xb & Rn_GPR64 & Rd_GPR64 +{ + rval:8 = Rm_GPR64 & 0x3f; + tmp_1:8 = ( Rn_GPR64 >> rval ) | ( Rn_GPR64 << ( 64 - rval ) ); + Rd_GPR64 = tmp_1; +} + +# C6.2.264 SB page C6-1746 line 102913 MATCH xd50330ff/mask=xfffff0ff +# CONSTRUCT xd50330ff/mask=xfffff0ff MATCHED 1 DOCUMENTED OPCODES + +:sb +is b_1231=0xd5033 & b_0007=0xff +{ + SpeculationBarrier(); +} + +# C6.2.265 SBC page C6-1747 line 102973 MATCH x5a000000/mask=x7fe0fc00 +# C6.2.236 NGC page C6-1698 line 100437 MATCH x5a0003e0/mask=x7fe0ffe0 +# CONSTRUCT x5a000000/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x5a000000/mask=xffe0fc00 --status pass --comment "flags" + +:sbc Rd_GPR32, Rn_GPR32, Rm_GPR32 +is sf=0 & op=1 & s=0 & b_2428=0x1a & b_2123=0 & Rm_GPR32 & opcode2=0x0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp:4 = Rm_GPR32 + zext(!CY); + Rd_GPR64 = zext(Rn_GPR32 - tmp); +} + +# C6.2.265 SBC page C6-1747 line 102973 MATCH x5a000000/mask=x7fe0fc00 +# C6.2.236 NGC page C6-1698 line 100437 MATCH x5a0003e0/mask=x7fe0ffe0 +# CONSTRUCT xda000000/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xda000000/mask=xffe0fc00 --status pass --comment "flags" + +:sbc Rd_GPR64, Rn_GPR64, Rm_GPR64 +is sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=0 & Rm_GPR64 & opcode2=0x0 & Rn_GPR64 & Rd_GPR64 +{ + tmp:8 = Rm_GPR64 + zext(!CY); + Rd_GPR64 = Rn_GPR64 - tmp; +} + +# C6.2.266 SBCS page C6-1749 line 103074 MATCH x7a000000/mask=x7fe0fc00 +# C6.2.237 NGCS page C6-1700 line 100524 MATCH x7a0003e0/mask=x7fe0ffe0 +# CONSTRUCT x7a000000/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x7a000000/mask=xffe0fc00 --status pass --comment "flags" + +:sbcs Rd_GPR32, Rn_GPR32, Rm_GPR32 +is sf=0 & op=1 & s=1 & b_2428=0x1a & b_2123=0 & Rm_GPR32 & opcode2=0x0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp:4 = Rm_GPR32 + zext(!CY); + add_with_carry_flags(Rn_GPR32, ~Rm_GPR32); + Rd_GPR64 = zext(Rn_GPR32 - tmp); + resultflags(Rd_GPR32); + affectflags(); +} + +# C6.2.266 SBCS page C6-1749 line 103074 MATCH x7a000000/mask=x7fe0fc00 +# C6.2.237 NGCS page C6-1700 line 100524 MATCH x7a0003e0/mask=x7fe0ffe0 +# CONSTRUCT xfa000000/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xfa000000/mask=xffe0fc00 --status pass --comment "flags" + +:sbcs Rd_GPR64, Rn_GPR64, Rm_GPR64 +is sf=1 & op=1 & s=1 & b_2428=0x1a & b_2123=0 & Rm_GPR64 & opcode2=0x0 & Rn_GPR64 & Rd_GPR64 +{ + tmp:8 = Rm_GPR64 + zext(!CY); + add_with_carry_flags(Rn_GPR64, ~Rm_GPR64); + Rd_GPR64 = Rn_GPR64 - tmp; + resultflags(Rd_GPR64); + affectflags(); +} + +# C6.2.209 SBFIZ page C6-856 line 49751 KEEPWITH + +sbfiz_lsb: "#"^imm is ImmR [ imm = 32 - ImmR; ] { export *[const]:4 imm; } +sbfiz_width: "#"^imm is ImmS [ imm = ImmS + 1; ] { export *[const]:4 imm; } +sbfiz_lsb64: "#"^imm is ImmR [ imm = 64 - ImmR; ] { export *[const]:4 imm; } + +# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000 +# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00 +# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000 +# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000 +# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00 +# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00 +# CONSTRUCT x13000002/mask=xffe08006 MATCHED 6 DOCUMENTED OPCODES +# AUNIT --inst x13000002/mask=xffe08006 --status pass +# Special alias case of sbfm for when ImmS < ImmR-1 +# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue(); + +:sbfiz Rd_GPR32, Rn_GPR32, sbfiz_lsb, sbfiz_width +is sbfiz_lsb & sbfiz_width & ImmS_LT_ImmR=1 & ImmS_EQ_ImmR=0 & sf=0 & opc=0 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & ImmSConst32 & DecodeWMask32 & DecodeTMask32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + local wmask:4 = DecodeWMask32; + local tmask:4 = DecodeTMask32; + local src:4 = Rn_GPR32; + local bot:4 = ((src>>ImmRConst32)|(src<<(32-ImmRConst32))) & wmask; + local top:4 = (((src>>ImmSConst32)&0x1)*(-1))&0xffffffff; + Rd_GPR64 = zext((top & ~(tmask)) | (bot & tmask)); +} + +# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000 +# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00 +# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000 +# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000 +# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00 +# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00 +# C6.2.371 SXTW page C6-1968 line 115498 MATCH x93407c00/mask=xfffffc00 +# CONSTRUCT x93400002/mask=xffc00006 MATCHED 7 DOCUMENTED OPCODES +# AUNIT --inst x93400002/mask=xffc00006 --status pass +# Special alias case of sbfm for when ImmS < ImmR-1 + +:sbfiz Rd_GPR64, Rn_GPR64, sbfiz_lsb64, sbfiz_width +is sbfiz_lsb64 & sbfiz_width & ImmS_LT_ImmR=1 & ImmS_EQ_ImmR=0 & sf=1 & opc=0 & b_2428=0x13 & b_2323=0 & n=1 & ImmRConst64 & ImmSConst64 & DecodeWMask64 & DecodeTMask64 & Rn_GPR64 & Rd_GPR64 +{ + local wmask:8 = DecodeWMask64; + local tmask:8 = DecodeTMask64; + local src:8 = Rn_GPR64; + local bot:8 = ((src>>ImmRConst64)|(src<<(64-ImmRConst64))) & wmask; + local top:8 = ((src>>ImmSConst64)&0x1)*(-1); + Rd_GPR64 = (top & ~(tmask)) | (bot & tmask); +} + +# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000 +# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00 +# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000 +# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000 +# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00 +# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00 +# CONSTRUCT x13000000/mask=xffe08000 MATCHED 6 DOCUMENTED OPCODES +# AUNIT --inst x13000000/mask=xffe08000 --status pass +# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue(); + +:sbfm Rd_GPR32, Rn_GPR32, ImmRConst32, ImmSConst32 +is sf=0 & opc=0 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & ImmSConst32 & DecodeWMask32 & DecodeTMask32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + local wmask:4 = DecodeWMask32; + local tmask:4 = DecodeTMask32; + local src:4 = Rn_GPR32; + local bot:4 = ((src>>ImmRConst32)|(src<<(32-ImmRConst32))) & wmask; + local top:4 = (((src>>ImmSConst32)&0x1)*(-1))&0xffffffff; + Rd_GPR64 = zext((top & ~(tmask)) | (bot & tmask)); +} + +# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000 +# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00 +# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000 +# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000 +# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00 +# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00 +# C6.2.371 SXTW page C6-1968 line 115498 MATCH x93407c00/mask=xfffffc00 +# CONSTRUCT x93400000/mask=xffc00000 MATCHED 7 DOCUMENTED OPCODES +# AUNIT --inst x93400000/mask=xffc00000 --status pass + +:sbfm Rd_GPR64, Rn_GPR64, ImmRConst64, ImmSConst64 +is sf=1 & opc=0 & b_2428=0x13 & b_2323=0 & n=1 & ImmRConst64 & ImmSConst64 & DecodeWMask64 & DecodeTMask64 & Rn_GPR64 & Rd_GPR64 +{ + local wmask:8 = DecodeWMask64; + local tmask:8 = DecodeTMask64; + local src:8 = Rn_GPR64; + local bot:8 = ((src>>ImmRConst64)|(src<<(64-ImmRConst64))) & wmask; + local top:8 = ((src>>ImmSConst64)&0x1)*(-1); + Rd_GPR64 = (top & ~(tmask)) | (bot & tmask); +} + +# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000 +# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00 +# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000 +# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000 +# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00 +# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00 +# CONSTRUCT x13000004/mask=xffe08006 MATCHED 6 DOCUMENTED OPCODES +# AUNIT --inst x13000004/mask=xffe08006 --status pass +# Special cases when just getting the 0 bit +# >> Not sure about the above old comment one, this is actually for getting one bit from Rn +# SBFX alias of SMFM is used when ImmS >= ImmR +# We split the '>=' into two separate cases +# Here ImmS = ImmR (for 32-bit) +# Alias for sbfm as determined by BFXPreferred() +# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue(); + +:sbfx Rd_GPR32, Rn_GPR32, ImmRConst32, BFextractWidth32 +is ImmS_LT_ImmR=0 & ImmS_EQ_ImmR=1 & sf=0 & opc=0 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & BFextractWidth32 & ImmSConst32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp:4 = ((Rn_GPR32 >> ImmSConst32) & 0x1) * 0xffffffff; + Rd_GPR64 = zext(tmp); +} + +# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000 +# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00 +# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000 +# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000 +# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00 +# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00 +# C6.2.371 SXTW page C6-1968 line 115498 MATCH x93407c00/mask=xfffffc00 +# CONSTRUCT x93400004/mask=xffc00006 MATCHED 7 DOCUMENTED OPCODES +# AUNIT --inst x93400004/mask=xffc00006 --status pass +# Now, the case where ImmS = ImmR (for 64-bit) + +:sbfx Rd_GPR64, Rn_GPR64, ImmRConst64, BFextractWidth64 +is ImmS_LT_ImmR=0 & ImmS_EQ_ImmR=1 & sf=1 & opc=0 & b_2428=0x13 & b_2323=0 & n=1 & BFextractWidth64 & ImmRConst64 & ImmSConst64 & Rn_GPR64 & Rd_GPR64 +{ + tmp:8 = ((Rn_GPR64 >> ImmSConst64) & 0x1) * 0xffffffffffffffff; + Rd_GPR64 = tmp; +} + +# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000 +# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00 +# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000 +# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000 +# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00 +# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00 +# CONSTRUCT x13000000/mask=xffe08006 MATCHED 6 DOCUMENTED OPCODES +# AUNIT --inst x13000000/mask=xffe08006 --status pass +# Now, the case where ImmS > ImmR (for 32-bit) +# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue(); + +:sbfx Rd_GPR32, Rn_GPR32, ImmRConst32, BFextractWidth32 +is ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=0 & sf=0 & opc=0 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & BFextractWidth32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + src:4 = Rn_GPR32; + tmp:4 = src << (31 - (ImmRConst32 + BFextractWidth32 - 1)); + tmp = tmp s>> (32 - BFextractWidth32); + Rd_GPR64 = zext(tmp); +} + +# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000 +# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00 +# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000 +# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000 +# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00 +# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00 +# C6.2.371 SXTW page C6-1968 line 115498 MATCH x93407c00/mask=xfffffc00 +# CONSTRUCT x93400000/mask=xffc00000 MATCHED 7 DOCUMENTED OPCODES +# AUNIT --inst x93400000/mask=xffc00000 --status pass +# Finally, the case where ImmS > ImmR (for 64-bit) + +:sbfx Rd_GPR64, Rn_GPR64, ImmRConst64, BFextractWidth64 +is sf=1 & opc=0 & b_2428=0x13 & b_2323=0 & n=1 & ImmRConst64 & BFextractWidth64 & (ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=0) & Rn_GPR64 & Rd_GPR64 +{ + src:8 = Rn_GPR64; + tmp:8 = src << (63 - (ImmRConst64 + BFextractWidth64 - 1)); + tmp = tmp s>> (64 - BFextractWidth64); + Rd_GPR64 = tmp; +} + +# C6.2.270 SDIV page C6-1758 line 103515 MATCH x1ac00c00/mask=x7fe0fc00 +# CONSTRUCT x1ac00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x1ac00c00/mask=xffe0fc00 --status pass + +:sdiv Rd_GPR32, Rn_GPR32, Rm_GPR32 +is sf=0 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR32 & b_1015=0x3 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + local tmp_1:4 = 0; + if (Rm_GPR32 == 0) goto ; + tmp_1 = Rn_GPR32 s/ Rm_GPR32; + + Rd_GPR64 = zext(tmp_1); +} + +# C6.2.270 SDIV page C6-1758 line 103515 MATCH x1ac00c00/mask=x7fe0fc00 +# CONSTRUCT x9ac00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x9ac00c00/mask=xffe0fc00 --status pass + +:sdiv Rd_GPR64, Rn_GPR64, Rm_GPR64 +is sf=1 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR64 & b_1015=0x3 & Rn_GPR64 & Rd_GPR64 +{ + local tmp_1:8 = 0; + if (Rm_GPR64 == 0) goto ; + tmp_1 = Rn_GPR64 s/ Rm_GPR64; + + Rd_GPR64 = tmp_1; +} + + +# C6.2.271 SETF8, SETF16 page C6-1759 line 103584 MATCH x3a00080d/mask=xffffbc1f +# CONSTRUCT x3a00080d/mask=xfffffc1f MATCHED 1 DOCUMENTED OPCODES + +:setf8 aa_Wn +is b_1531=0b00111010000000000 & b_14=0 & b_1013=0b0010 & b_0004=0b01101 & aa_Wn +{ + NG = ((aa_Wn:1 >> 7) & 1) == 1; + ZR = (aa_Wn:1 == 0); + OV = (((aa_Wn >> 7) & 1) ^ ((aa_Wn >>8) & 1)) == 1; +} + + +# C6.2.271 SETF8, SETF16 page C6-1759 line 103584 MATCH x3a00080d/mask=xffffbc1f +# CONSTRUCT x3a00480d/mask=xfffffc1f MATCHED 1 DOCUMENTED OPCODES + +:setf16 aa_Wn +is b_1531=0b00111010000000000 & b_14=1 & b_1013=0b0010 & b_0004=0b01101 & aa_Wn +{ + NG = ((aa_Wn:2 >> 15) & 1) == 1; + ZR = (aa_Wn:2 == 0); + OV = (((aa_Wn >> 15) & 1) ^ ((aa_Wn >>16) & 1)) == 1; +} + + + + +# C6.2.276 SETP, SETM, SETE page C6-1780 line 105072 MATCH x19c00400/mask=x3fe03c00 +# C6.2.272 SETGP, SETGM, SETGE page C6-1760 line 103652 MATCH x1dc00400/mask=x3fe03c00 +# CONSTRUCT x1dc00400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES + +setPhase:"p" is b_1415=0 {export 0:1;} +setPhase:"m" is b_1415=1 {export 1:1;} +setPhase:"e" is b_1415=2 {export 2:1;} + +setType: "" is b_1013=0x1 {export 1:1; } +setType: "n" is b_1013=0x9 {export 9:1; } +setType: "t" is b_1013=0x5 {export 5:1; } +setType: "tn" is b_1013=0xd {export 13:1; } + +define pcodeop memorySetTag; +:setg^setPhase^setType [Rd_GPR64]!, Rn_GPR64!, Rs_GPR64 +is size.ldstr & b_2129=0xee & Rs_GPR64 & b_1415 <3 & setPhase & setType & Rn_GPR64 & Rd_GPR64 { + memorySetTag(Rd_GPR64, Rn_GPR64, Rs_GPR64, setPhase, setType); +} + + +# C6.2.276 SETP, SETM, SETE page C6-1780 line 105072 MATCH x19c00400/mask=x3fe03c00 +# CONSTRUCT x19c00400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES +define pcodeop memorySet; +:setp^setPhase^setType [Rd_GPR64]!, Rn_GPR64!, Rs_GPR64 +is size.ldstr & b_2129=0xce & Rs_GPR64 & b_1415 <3 & setPhase & setType & Rn_GPR64 & Rd_GPR64 { + memorySet(Rd_GPR64, Rn_GPR64, Rs_GPR64, setPhase, setType); +} + + +# C6.2.280 SEV page C6-1796 line 106224 MATCH xd503209f/mask=xffffffff +# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f +# CONSTRUCT xd503209f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd503209f/mask=xffffffff --status nodest + +:sev +is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low=4 & Rt=0x1f +{ + SendEvent(); +} + +# C6.2.281 SEVL page C6-1797 line 106259 MATCH xd50320bf/mask=xffffffff +# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f +# CONSTRUCT xd50320bf/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50320bf/mask=xffffffff --status nodest + +:sevl +is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low=5 & Rt=0x1f +{ + SendEventLocally(); +} + +# C6.2.282 SMADDL page C6-1798 line 106294 MATCH x9b200000/mask=xffe08000 +# CONSTRUCT x9b200000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x9b200000/mask=xffe08000 --status pass + +:smaddl Rd_GPR64, Rn_GPR32, Rm_GPR32, Ra_GPR64 +is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=1 & Rm_GPR32 & op.dp3_o0=0 & Ra_GPR64 & Rn_GPR32 & Rd_GPR64 +{ + tmp_3:8 = sext(Rn_GPR32); + tmp_4:8 = sext(Rm_GPR32); + tmp_2:8 = tmp_3 * tmp_4; + tmp_1:8 = Ra_GPR64 + tmp_2; + Rd_GPR64 = tmp_1; +} + +# C6.2.283 SMC page C6-1800 line 106384 MATCH xd4000003/mask=xffe0001f +# CONSTRUCT xd4000003/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd4000003/mask=xffe0001f --status nodest + +:smc imm16 +is b_2431=0xd4 & excCode=0 & imm16 & excCode2=0 & ll=3 +{ + CallSecureMonitor(imm16:2); +} + +# C6.2.284 SMNEGL page C6-1801 line 106433 MATCH x9b20fc00/mask=xffe0fc00 +# C6.2.287 SMSUBL page C6-1806 line 106711 MATCH x9b208000/mask=xffe08000 +# CONSTRUCT x9b20fc00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x9b20fc00/mask=xffe0fc00 --status pass + +:smnegl Rd_GPR64, Rn_GPR32, Rm_GPR32 +is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=1 & Rm_GPR32 & op.dp3_o0=1 & Ra=0x1f & Rn_GPR32 & Rd_GPR64 +{ + tmp_3:8 = sext(Rn_GPR32); + tmp_4:8 = sext(Rm_GPR32); + tmp_2:8 = tmp_3 * tmp_4; + subflags0(tmp_2); + tmp_1:8 = -tmp_2; + Rd_GPR64 = tmp_1; +} + +# C6.2.287 SMSUBL page C6-1806 line 106711 MATCH x9b208000/mask=xffe08000 +# CONSTRUCT x9b208000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x9b208000/mask=xffe08000 --status pass + +:smsubl Rd_GPR64, Rn_GPR32, Rm_GPR32, Ra_GPR64 +is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=1 & Rm_GPR32 & op.dp3_o0=1 & Ra_GPR64 & Rn_GPR32 & Rd_GPR64 +{ + tmp_3:8 = sext(Rn_GPR32); + tmp_4:8 = sext(Rm_GPR32); + tmp_2:8 = tmp_3 * tmp_4; + tmp_1:8 = Ra_GPR64 - tmp_2; + Rd_GPR64 = tmp_1; +} + + +# C6.2.285 SMSTART page C6-1802 line 106497 MATCH xd503417f/mask=xfffff9ff +# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f +# CONSTRUCT xd503417f/mask=xfffff9ff MATCHED 2 DOCUMENTED OPCODES +# xd503417f/mask=xfffff9ff NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=110101010000001101000..101111111 + +define pcodeop sveStreamingModeStart; +define pcodeop sveStreamingModeStop; + +SVAmodeOp: "SM" is b_0911=0x1 & b_08 { svcr[0,1] = b_08; } +SVAmodeOp: "ZA" is b_0911=0x2 & b_08 { svcr[1,1] = b_08; } +SVAmodeOp: "" is b_0911=0x3 & b_08 { svcr[0,1] = b_08; svcr[1,1] = b_08; } + +:smstart "{"^SVAmodeOp^"}" +is b_1131=0x1aa068 & SVAmodeOp & b_08=1 & b_0507=0x3 & op4=0x1f { + build SVAmodeOp; + sveStreamingModeStart(); +} + + +# C6.2.286 SMSTOP page C6-1804 line 106604 MATCH xd503407f/mask=xfffff9ff +# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f +# CONSTRUCT xd503407f/mask=xfffff9ff MATCHED 2 DOCUMENTED OPCODES +# xd503407f/mask=xfffff9ff NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=110101010000001101000..001111111 + +:smstop "{"^SVAmodeOp^"}" +is b_1131=0x1aa068 & SVAmodeOp & b_08=0 & b_0507=0x3 & op4=0x1f { + sveStreamingModeStop(); +} + + +# C6.2.288 SMULH page C6-1808 line 106800 MATCH x9b400000/mask=xffe08000 +# CONSTRUCT x9b400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x9b400000/mask=xffe08000 --status pass +# To enforce SHOULD BE ONE fields add: b_1014=0b11111 + +:smulh Rd_GPR64, Rn_GPR64, Rm_GPR64 +is sf=1 & op.dp3=0 & b_2428=0x1b & op.dp3_op31=2 & Rm_GPR64 & op.dp3_o0=0 & Ra & Rn_GPR64 & Rd_GPR64 +{ + local tmpq:16 = sext(Rn_GPR64) * sext(Rm_GPR64); + Rd_GPR64 = tmpq(8); +} + +# C6.2.289 SMULL page C6-1809 line 106867 MATCH x9b207c00/mask=xffe0fc00 +# C6.2.282 SMADDL page C6-1798 line 106294 MATCH x9b200000/mask=xffe08000 +# CONSTRUCT x9b207c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x9b207c00/mask=xffe0fc00 --status pass + +:smull Rd_GPR64, Rn_GPR32, Rm_GPR32 +is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=1 & Rm_GPR32 & op.dp3_o0=0 & Ra=0x1f & Rn_GPR32 & Rd_GPR64 +{ + tmp_3:8 = sext(Rn_GPR32); + tmp_4:8 = sext(Rm_GPR32); + tmp_2:8 = tmp_3 * tmp_4; + tmp_1:8 = tmp_2; + Rd_GPR64 = tmp_1; +} + +# C6.2.295 STADDB, STADDLB page C6-1818 line 107383 MATCH x3820001f/mask=xffa0fc1f +# C6.2.298 STCLRB, STCLRLB page C6-1824 line 107670 MATCH x3820101f/mask=xffa0fc1f +# C6.2.301 STEORB, STEORLB page C6-1830 line 107956 MATCH x3820201f/mask=xffa0fc1f +# C6.2.328 STSETB, STSETLB page C6-1886 line 111044 MATCH x3820301f/mask=xffa0fc1f +# C6.2.331 STSMAXB, STSMAXLB page C6-1892 line 111330 MATCH x3820401f/mask=xffa0fc1f +# C6.2.334 STSMINB, STSMINLB page C6-1898 line 111623 MATCH x3820501f/mask=xffa0fc1f +# C6.2.340 STUMAXB, STUMAXLB page C6-1910 line 112231 MATCH x3820601f/mask=xffa0fc1f +# C6.2.343 STUMINB, STUMINLB page C6-1916 line 112525 MATCH x3820701f/mask=xffa0fc1f +# C6.2.133 LDADDB, LDADDAB, LDADDALB, LDADDLB page C6-1489 line 88545 MATCH x38200000/mask=xff20fc00 +# C6.2.152 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB page C6-1524 line 90495 MATCH x38201000/mask=xff20fc00 +# C6.2.155 LDEORB, LDEORAB, LDEORALB, LDEORLB page C6-1531 line 90916 MATCH x38202000/mask=xff20fc00 +# C6.2.181 LDSETB, LDSETAB, LDSETALB, LDSETLB page C6-1590 line 94403 MATCH x38203000/mask=xff20fc00 +# C6.2.184 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB page C6-1597 line 94824 MATCH x38204000/mask=xff20fc00 +# C6.2.187 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB page C6-1604 line 95245 MATCH x38205000/mask=xff20fc00 +# C6.2.196 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB page C6-1623 line 96362 MATCH x38206000/mask=xff20fc00 +# C6.2.199 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB page C6-1630 line 96783 MATCH x38207000/mask=xff20fc00 +# CONSTRUCT x3820001f/mask=xffa08c1f MATCHED 16 DOCUMENTED OPCODES +# AUNIT --inst x3820001f/mask=xffa08c1f --status nomem + +# size=0b00 (3031) + +:st^ls_opc1^ls_lor^"b" aa_Ws, [Rn_GPR64xsp] +is b_3031=0b00 & b_2429=0b111000 & b_23=0 & b_21=1 & b_1515=0 & b_1011=0b00 & b_0004=0b11111 & ls_opc1 & ls_lor & aa_Ws & Rn_GPR64xsp +{ build ls_opc1; build ls_lor; } + +# C6.2.296 STADDH, STADDLH page C6-1820 line 107469 MATCH x7820001f/mask=xffa0fc1f +# C6.2.299 STCLRH, STCLRLH page C6-1826 line 107756 MATCH x7820101f/mask=xffa0fc1f +# C6.2.302 STEORH, STEORLH page C6-1832 line 108042 MATCH x7820201f/mask=xffa0fc1f +# C6.2.329 STSETH, STSETLH page C6-1888 line 111130 MATCH x7820301f/mask=xffa0fc1f +# C6.2.332 STSMAXH, STSMAXLH page C6-1894 line 111419 MATCH x7820401f/mask=xffa0fc1f +# C6.2.335 STSMINH, STSMINLH page C6-1900 line 111712 MATCH x7820501f/mask=xffa0fc1f +# C6.2.341 STUMAXH, STUMAXLH page C6-1912 line 112320 MATCH x7820601f/mask=xffa0fc1f +# C6.2.344 STUMINH, STUMINLH page C6-1918 line 112614 MATCH x7820701f/mask=xffa0fc1f +# C6.2.134 LDADDH, LDADDAH, LDADDALH, LDADDLH page C6-1491 line 88670 MATCH x78200000/mask=xff20fc00 +# C6.2.153 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH page C6-1526 line 90621 MATCH x78201000/mask=xff20fc00 +# C6.2.156 LDEORH, LDEORAH, LDEORALH, LDEORLH page C6-1533 line 91042 MATCH x78202000/mask=xff20fc00 +# C6.2.182 LDSETH, LDSETAH, LDSETALH, LDSETLH page C6-1592 line 94529 MATCH x78203000/mask=xff20fc00 +# C6.2.185 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH page C6-1599 line 94950 MATCH x78204000/mask=xff20fc00 +# C6.2.188 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH page C6-1606 line 95371 MATCH x78205000/mask=xff20fc00 +# C6.2.197 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH page C6-1625 line 96488 MATCH x78206000/mask=xff20fc00 +# C6.2.200 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH page C6-1632 line 96909 MATCH x78207000/mask=xff20fc00 +# CONSTRUCT x7820001f/mask=xffa08c1f MATCHED 16 DOCUMENTED OPCODES +# AUNIT --inst x7820001f/mask=xffa08c1f --status nomem + +# size=0b01 (3031) + +:st^ls_opc2^ls_lor^"h" aa_Ws, [Rn_GPR64xsp] +is b_3031=0b01 & b_2429=0b111000 & b_23=0 & b_21=1 & b_1515=0 & b_1011=0b00 & b_0004=0b11111 & ls_opc2 & ls_lor & aa_Ws & Rn_GPR64xsp +{ build ls_opc2; build ls_lor; } + +# C6.2.297 STADD, STADDL page C6-1822 line 107555 MATCH xb820001f/mask=xbfa0fc1f +# C6.2.300 STCLR, STCLRL page C6-1828 line 107842 MATCH xb820101f/mask=xbfa0fc1f +# C6.2.303 STEOR, STEORL page C6-1834 line 108128 MATCH xb820201f/mask=xbfa0fc1f +# C6.2.330 STSET, STSETL page C6-1890 line 111216 MATCH xb820301f/mask=xbfa0fc1f +# C6.2.333 STSMAX, STSMAXL page C6-1896 line 111508 MATCH xb820401f/mask=xbfa0fc1f +# C6.2.336 STSMIN, STSMINL page C6-1902 line 111801 MATCH xb820501f/mask=xbfa0fc1f +# C6.2.342 STUMAX, STUMAXL page C6-1914 line 112409 MATCH xb820601f/mask=xbfa0fc1f +# C6.2.345 STUMIN, STUMINL page C6-1920 line 112703 MATCH xb820701f/mask=xbfa0fc1f +# C6.2.135 LDADD, LDADDA, LDADDAL, LDADDL page C6-1493 line 88796 MATCH xb8200000/mask=xbf20fc00 +# C6.2.154 LDCLR, LDCLRA, LDCLRAL, LDCLRL page C6-1528 line 90747 MATCH xb8201000/mask=xbf20fc00 +# C6.2.157 LDEOR, LDEORA, LDEORAL, LDEORL page C6-1535 line 91168 MATCH xb8202000/mask=xbf20fc00 +# C6.2.183 LDSET, LDSETA, LDSETAL, LDSETL page C6-1594 line 94655 MATCH xb8203000/mask=xbf20fc00 +# C6.2.186 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL page C6-1601 line 95076 MATCH xb8204000/mask=xbf20fc00 +# C6.2.189 LDSMIN, LDSMINA, LDSMINAL, LDSMINL page C6-1608 line 95497 MATCH xb8205000/mask=xbf20fc00 +# C6.2.198 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL page C6-1627 line 96614 MATCH xb8206000/mask=xbf20fc00 +# C6.2.201 LDUMIN, LDUMINA, LDUMINAL, LDUMINL page C6-1634 line 97035 MATCH xb8207000/mask=xbf20fc00 +# CONSTRUCT xb820001f/mask=xffa08c1f MATCHED 16 DOCUMENTED OPCODES +# AUNIT --inst xb820001f/mask=xffa08c1f --status nomem + +# size=0b10 (3031) + +:st^ls_opc4^ls_lor aa_Ws, [Rn_GPR64xsp] +is b_3031=0b10 & b_2429=0b111000 & b_23=0 & b_21=1 & b_1515=0 & b_1011=0b00 & b_0004=0b11111 & ls_opc4 & ls_lor & aa_Ws & Rn_GPR64xsp +{ build ls_opc4; build ls_lor; } + +# C6.2.297 STADD, STADDL page C6-1822 line 107555 MATCH xb820001f/mask=xbfa0fc1f +# C6.2.300 STCLR, STCLRL page C6-1828 line 107842 MATCH xb820101f/mask=xbfa0fc1f +# C6.2.303 STEOR, STEORL page C6-1834 line 108128 MATCH xb820201f/mask=xbfa0fc1f +# C6.2.330 STSET, STSETL page C6-1890 line 111216 MATCH xb820301f/mask=xbfa0fc1f +# C6.2.333 STSMAX, STSMAXL page C6-1896 line 111508 MATCH xb820401f/mask=xbfa0fc1f +# C6.2.336 STSMIN, STSMINL page C6-1902 line 111801 MATCH xb820501f/mask=xbfa0fc1f +# C6.2.342 STUMAX, STUMAXL page C6-1914 line 112409 MATCH xb820601f/mask=xbfa0fc1f +# C6.2.345 STUMIN, STUMINL page C6-1920 line 112703 MATCH xb820701f/mask=xbfa0fc1f +# C6.2.135 LDADD, LDADDA, LDADDAL, LDADDL page C6-1493 line 88796 MATCH xb8200000/mask=xbf20fc00 +# C6.2.154 LDCLR, LDCLRA, LDCLRAL, LDCLRL page C6-1528 line 90747 MATCH xb8201000/mask=xbf20fc00 +# C6.2.157 LDEOR, LDEORA, LDEORAL, LDEORL page C6-1535 line 91168 MATCH xb8202000/mask=xbf20fc00 +# C6.2.183 LDSET, LDSETA, LDSETAL, LDSETL page C6-1594 line 94655 MATCH xb8203000/mask=xbf20fc00 +# C6.2.186 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL page C6-1601 line 95076 MATCH xb8204000/mask=xbf20fc00 +# C6.2.189 LDSMIN, LDSMINA, LDSMINAL, LDSMINL page C6-1608 line 95497 MATCH xb8205000/mask=xbf20fc00 +# C6.2.198 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL page C6-1627 line 96614 MATCH xb8206000/mask=xbf20fc00 +# C6.2.201 LDUMIN, LDUMINA, LDUMINAL, LDUMINL page C6-1634 line 97035 MATCH xb8207000/mask=xbf20fc00 +# CONSTRUCT xf820001f/mask=xffa08c1f MATCHED 16 DOCUMENTED OPCODES +# AUNIT --inst xf820001f/mask=xffa08c1f --status nomem +# size=0b11 (3031) + +:st^ls_opc8^ls_lor aa_Xs, [Rn_GPR64xsp] +is b_3031=0b11 & b_2429=0b111000 & b_23=0 & b_21=1 & b_1515=0 & b_1011=0b00 & b_0004=0b11111 & ls_opc8 & ls_lor & aa_Xs & Rn_GPR64xsp +{ build ls_opc8; build ls_lor; } + +# C6.2.307 STLLRB page C6-1842 line 108609 MATCH x08800000/mask=xffe08000 +# CONSTRUCT x08800000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x08800000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111 +# size=0b00 (3031) + +:stllrb aa_Wt, [Rn_GPR64xsp] +is b_3031=0b00 & b_2329=0b0010001 & b_22=0 & b_21=0 & b_15=0 & aa_Wt & Rn_GPR64xsp +{ *:1 Rn_GPR64xsp = aa_Wt:1; LORelease(); } + +# C6.2.308 STLLRH page C6-1843 line 108673 MATCH x48800000/mask=xffe08000 +# CONSTRUCT x48800000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x48800000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111 +# size=0b01 (3031) + +:stllrh aa_Wt, [Rn_GPR64xsp] +is b_3031=0b01 & b_2329=0b0010001 & b_22=0 & b_21=0 & b_15=0 & aa_Wt & Rn_GPR64xsp +{ *:2 Rn_GPR64xsp = aa_Wt:2; LORelease(); } + +# C6.2.309 STLLR page C6-1844 line 108737 MATCH x88800000/mask=xbfe08000 +# CONSTRUCT x88800000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x88800000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111 +# size=0b10 (3031) + +:stllr aa_Wt, [Rn_GPR64xsp] +is b_3031=0b10 & b_2329=0b0010001 & b_22=0 & b_21=0 & b_15=0 & aa_Wt & Rn_GPR64xsp +{ *:4 Rn_GPR64xsp = aa_Wt; LORelease(); } + +# C6.2.309 STLLR page C6-1844 line 108737 MATCH x88800000/mask=xbfe08000 +# CONSTRUCT xc8800000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xc8800000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111 +# size=0b11 (3031) + +:stllr aa_Xt, [Rn_GPR64xsp] +is b_3031=0b11 & b_2329=0b0010001 & b_22=0 & b_21=0 & b_15=0 & aa_Xt & Rn_GPR64xsp +{ *:8 Rn_GPR64xsp = aa_Xt; LORelease(); } + +# C6.2.310 STLR page C6-1846 line 108821 MATCH x88808000/mask=xbfe08000 +# CONSTRUCT xc8808000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xc8808000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111 + +:stlr Rt_GPR64, addrReg +is size.ldstr=3 & b_2429=0x8 & b_23=1 & L=0 & b_21=0 & b_15=1 & addrReg & Rt_GPR64 +{ + *addrReg = Rt_GPR64; +} + +# C6.2.310 STLR page C6-1846 line 108821 MATCH x88808000/mask=xbfe08000 +# CONSTRUCT x88808000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x88808000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111 + +:stlr Rt_GPR32, addrReg +is size.ldstr=2 & b_2429=0x8 & b_23=1 & L=0 & b_21=0 & b_15=1 & addrReg & Rt_GPR32 +{ + *addrReg = Rt_GPR32; +} + +# C6.2.311 STLRB page C6-1848 line 108904 MATCH x08808000/mask=xffe08000 +# CONSTRUCT x08808000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x08808000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111 + +:stlrb Rt_GPR32, addrReg +is size.ldstr=0 & b_2429=0x8 & b_23=1 & L=0 & b_21=0 & b_15=1 & addrReg & Rt_GPR32 +{ + *addrReg = Rt_GPR32; +} + +# C6.2.312 STLRH page C6-1849 line 108967 MATCH x48808000/mask=xffe08000 +# CONSTRUCT x48808000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x48808000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111 + +:stlrh Rt_GPR32, addrReg +is size.ldstr=1 & b_2429=0x8 & b_23=1 & L=0 & b_21=0 & b_15=1 & addrReg & Rt_GPR32 +{ + *addrReg = Rt_GPR32; +} + +# C6.2.313 STLUR page C6-1850 line 109030 MATCH x99000000/mask=xbfe00c00 +# CONSTRUCT x99000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES + +:stlur aa_Wt, addr_SIMM9 +is b_3031=0b10 & b_2129=0b011001000 & b_1011=0b00 & addr_SIMM9 & aa_Wt +{ + *addr_SIMM9 = aa_Wt; +} + +# C6.2.313 STLUR page C6-1850 line 109030 MATCH x99000000/mask=xbfe00c00 +# CONSTRUCT xd9000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES + +:stlur aa_Xt, addr_SIMM9 +is b_3031=0b11 & b_2129=0b011001000 & b_1011=0b00 & addr_SIMM9 & aa_Xt +{ + *addr_SIMM9 = aa_Xt; +} + +# C6.2.314 STLURB page C6-1852 line 109129 MATCH x19000000/mask=xffe00c00 +# CONSTRUCT x19000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# x19000000/mask=xffe00c00 NOT MATCHED BY ANY CONSTRUCTOR + +:stlurb aa_Wt, addr_SIMM9 +is b_2131=0b00011001000 & b_1011=0b00 & addr_SIMM9 & aa_Wt +{ + *addr_SIMM9 = aa_Wt:1; +} + +# C6.2.315 STLURH page C6-1854 line 109217 MATCH x59000000/mask=xffe00c00 +# CONSTRUCT x59000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# x59000000/mask=xffe00c00 NOT MATCHED BY ANY CONSTRUCTOR + +:stlurh aa_Wt, addr_SIMM9 +is b_2131=0b01011001000 & b_1011=0b00 & addr_SIMM9 & aa_Wt +{ + *addr_SIMM9 = aa_Wt:2; +} + +# C6.2.316 STLXP page C6-1856 line 109305 MATCH x88208000/mask=xbfe08000 +# CONSTRUCT xc8208000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xc8208000/mask=xffe08000 --status nomem + +:stlxp Rs_GPR32, Rt_GPR64, Rt2_GPR64, addrReg +is size.ldstr=3 & b_2429=0x8 & b_23=0 & L=0 & b_21=1 & Rs_GPR32 & b_15=1 & Rt2_GPR64 & addrReg & Rt_GPR64 & Rs_GPR64 +{ + status:1 = 1; + rsize:1 = 16; + check:1 = ExclusiveMonitorPass(addrReg, rsize); + if (!check) goto ; + *addrReg = Rt_GPR64; + *(addrReg + 4) = Rt2_GPR64; + status = ExclusiveMonitorsStatus(); + + Rs_GPR64 = zext(status); +} + +# C6.2.316 STLXP page C6-1856 line 109305 MATCH x88208000/mask=xbfe08000 +# CONSTRUCT x88208000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x88208000/mask=xffe08000 --status nomem + +:stlxp Rs_GPR32, Rt_GPR32, Rt2_GPR32, addrReg +is size.ldstr=2 & b_2429=0x8 & b_23=0 & L=0 & b_21=1 & Rs_GPR32 & b_15=1 & Rt2_GPR32 & addrReg & Rt_GPR32 & Rs_GPR64 +{ + status:1 = 1; + rsize:1 = 16; + check:1 = ExclusiveMonitorPass(addrReg, rsize); + if (!check) goto ; + *addrReg = Rt_GPR32; + *(addrReg + 4) = Rt2_GPR32; + status = ExclusiveMonitorsStatus(); + + Rs_GPR64 = zext(status); +} + +# C6.2.317 STLXR page C6-1859 line 109472 MATCH x88008000/mask=xbfe08000 +# CONSTRUCT xc8008000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xc8008000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1014=0b11111 + +:stlxr Rs_GPR32, Rt_GPR64, addrReg +is size.ldstr=3 & b_2429=0x8 & b_23=0 & L=0 & b_21=0 & Rs_GPR32 & b_15=1 & addrReg & Rt_GPR64 & Rs_GPR64 +{ + status:1 = 1; + rsize:1 = 16; + check:1 = ExclusiveMonitorPass(addrReg, rsize); + if (!check) goto ; + *addrReg = Rt_GPR64; + status = ExclusiveMonitorsStatus(); + + Rs_GPR64 = zext(status); +} + +# C6.2.317 STLXR page C6-1859 line 109472 MATCH x88008000/mask=xbfe08000 +# CONSTRUCT x88008000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x88008000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1014=0b11111 + +:stlxr Rs_GPR32, Rt_GPR32, addrReg +is size.ldstr=2 & b_2429=0x8 & b_23=0 & L=0 & b_21=0 & Rs_GPR32 & b_15=1 & addrReg & Rt_GPR32 & Rs_GPR64 +{ + status:1 = 1; + rsize:1 = 16; + check:1 = ExclusiveMonitorPass(addrReg, rsize); + if (!check) goto ; + *addrReg = Rt_GPR32; + status = ExclusiveMonitorsStatus(); + + Rs_GPR64 = zext(status); +} + +# C6.2.318 STLXRB page C6-1862 line 109627 MATCH x08008000/mask=xffe08000 +# CONSTRUCT x08008000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x08008000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1014=0b11111 + +:stlxrb Rs_GPR32, Rt_GPR32, addrReg +is size.ldstr=0 & b_2429=0x8 & b_23=0 & L=0 & b_21=0 & Rs_GPR32 & b_15=1 & addrReg & Rt_GPR32 & Rs_GPR64 +{ + status:1 = 1; + rsize:1 = 16; + check:1 = ExclusiveMonitorPass(addrReg, rsize); + if (!check) goto ; + local tmp:4 = Rt_GPR32; + *addrReg = tmp:1; + status = ExclusiveMonitorsStatus(); + + Rs_GPR64 = zext(status); +} + +# C6.2.319 STLXRH page C6-1864 line 109754 MATCH x48008000/mask=xffe08000 +# CONSTRUCT x48008000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x48008000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1014=0b11111 + +:stlxrh Rs_GPR32, Rt_GPR32, addrReg +is size.ldstr=1 & b_2429=0x8 & b_23=0 & L=0 & b_21=0 & Rs_GPR32 & b_15=1 & addrReg & Rt_GPR32 & Rs_GPR64 +{ + status:1 = 1; + rsize:1 = 16; + check:1 = ExclusiveMonitorPass(addrReg, rsize); + if (!check) goto ; + local tmp:4 = Rt_GPR32; + *addrReg = tmp:2; + status = ExclusiveMonitorsStatus(); + + Rs_GPR64 = zext(status); +} + +# C6.2.320 STNP page C6-1866 line 109888 MATCH x28000000/mask=x7fc00000 +# CONSTRUCT x28000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x28000000/mask=xffc00000 --status nomem + +:stnp Rt_GPR32, Rt2_GPR32, addrPairIndexed +is b_3031=0b00 & b_2229=0b10100000 & Rt2_GPR32 & addrPairIndexed & Rt_GPR32 +{ + data1:4 = Rt_GPR32; + data2:4 = Rt2_GPR32; + build addrPairIndexed; + *addrPairIndexed = data1; + *(addrPairIndexed + 4) = data2; +} + +# C6.2.320 STNP page C6-1866 line 109888 MATCH x28000000/mask=x7fc00000 +# CONSTRUCT xa8000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xa8000000/mask=xffc00000 --status nomem + +:stnp Rt_GPR64, Rt2_GPR64, addrPairIndexed +is b_3031=0b10 & b_2229=0b10100000 & Rt2_GPR64 & addrPairIndexed & Rt_GPR64 +{ + data1:8 = Rt_GPR64; + data2:8 = Rt2_GPR64; + build addrPairIndexed; + *addrPairIndexed = data1; + *(addrPairIndexed + 8) = data2; +} + +# C6.2.321 STP page C6-1868 line 109996 MATCH x28800000/mask=x7fc00000 +# C6.2.321 STP page C6-1868 line 109996 MATCH x29800000/mask=x7fc00000 +# C6.2.321 STP page C6-1868 line 109996 MATCH x29000000/mask=x7fc00000 +# C6.2.320 STNP page C6-1866 line 109888 MATCH x28000000/mask=x7fc00000 +# CONSTRUCT x28000000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst x28000000/mask=xfe400000 --status nomem + +:stp Rt_GPR32, Rt2_GPR32, addrPairIndexed +is b_3031=0b00 & b_2529=0b10100 & b_22=0b0 & Rt2_GPR32 & addrPairIndexed & Rt_GPR32 +{ + data1:4 = Rt_GPR32; + data2:4 = Rt2_GPR32; + build addrPairIndexed; + *addrPairIndexed = data1; + *(addrPairIndexed + 4) = data2; +} + +# C6.2.321 STP page C6-1868 line 109996 MATCH x28800000/mask=x7fc00000 +# C6.2.321 STP page C6-1868 line 109996 MATCH x29800000/mask=x7fc00000 +# C6.2.321 STP page C6-1868 line 109996 MATCH x29000000/mask=x7fc00000 +# C6.2.320 STNP page C6-1866 line 109888 MATCH x28000000/mask=x7fc00000 +# CONSTRUCT xa8000000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst xa8000000/mask=xfe400000 --status nomem + +:stp Rt_GPR64, Rt2_GPR64, addrPairIndexed +is b_3031=0b10 & b_2529=0b10100 & b_22=0b0 & Rt2_GPR64 & addrPairIndexed & Rt_GPR64 +{ + data1:8 = Rt_GPR64; + data2:8 = Rt2_GPR64; + build addrPairIndexed; + *addrPairIndexed = data1; + *(addrPairIndexed + 8) = data2; +} + +# C6.2.322 STR (immediate) page C6-1871 line 110209 MATCH xb9000000/mask=xbfc00000 +# CONSTRUCT xb9000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xb9000000/mask=xffc00000 --status nomem + +:str Rt_GPR32, addrUIMM +is size.ldstr=2 & b_2729=7 & v=0 & b_2425=1 & b_23=0 & b_2222=0 & addrUIMM & Rn_GPR64xsp & Rt_GPR32 +{ + *addrUIMM = Rt_GPR32; +} + +# C6.2.322 STR (immediate) page C6-1871 line 110209 MATCH xb8000400/mask=xbfe00c00 +# C6.2.322 STR (immediate) page C6-1871 line 110209 MATCH xb8000c00/mask=xbfe00c00 +# C6.2.337 STTR page C6-1904 line 111916 MATCH xb8000800/mask=xbfe00c00 +# C6.2.346 STUR page C6-1922 line 112818 MATCH xb8000000/mask=xbfe00c00 +# CONSTRUCT xb8000000/mask=xffe00000 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst xb8000000/mask=xffe00000 --status nomem + +:st^UnscPriv^"r" Rt_GPR32, addrIndexed +is size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR32 +{ + data1:4 = Rt_GPR32; + build addrIndexed; + *addrIndexed = data1; +} + +# C6.2.322 STR (immediate) page C6-1871 line 110209 MATCH xb8000400/mask=xbfe00c00 +# C6.2.322 STR (immediate) page C6-1871 line 110209 MATCH xb8000c00/mask=xbfe00c00 +# CONSTRUCT xb8000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xb8000400/mask=xffe00400 --status nomem + +:str Rt_GPR32, addrIndexed +is size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR32 +{ + data1:4 = Rt_GPR32; + build addrIndexed; + *addrIndexed = data1; +} + +# C6.2.322 STR (immediate) page C6-1871 line 110209 MATCH xb9000000/mask=xbfc00000 +# CONSTRUCT xf9000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xf9000000/mask=xffc00000 --status nomem + +:str Rt_GPR64, addrUIMM +is size.ldstr=3 & b_2729=7 & v=0 & b_2425=1 & b_23=0 & b_2222=0 & addrUIMM & Rn_GPR64xsp & Rt_GPR64 +{ + *addrUIMM = Rt_GPR64; +} + +# C6.2.322 STR (immediate) page C6-1871 line 110209 MATCH xb8000400/mask=xbfe00c00 +# C6.2.322 STR (immediate) page C6-1871 line 110209 MATCH xb8000c00/mask=xbfe00c00 +# CONSTRUCT xf8000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xf8000400/mask=xffe00400 --status nomem + +:str Rt_GPR64, addrIndexed +is size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR64 +{ + data1:8 = Rt_GPR64; + build addrIndexed; + *addrIndexed = data1; +} + +# C6.2.323 STR (register) page C6-1874 line 110394 MATCH xb8200800/mask=xbfe00c00 +# CONSTRUCT xb8200800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xb8200800/mask=xffe00c00 --status nomem + +:str Rt_GPR32, addrIndexed +is size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR32 +{ + data1:4 = Rt_GPR32; + build addrIndexed; + *addrIndexed = data1; +} + +# C6.2.323 STR (register) page C6-1874 line 110394 MATCH xb8200800/mask=xbfe00c00 +# CONSTRUCT xf8200800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xf8200800/mask=xffe00c00 --status nomem + +:str Rt_GPR64, addrIndexed +is size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR64 +{ + data1:8 = Rt_GPR64; + build addrIndexed; + *addrIndexed = data1; +} + +# C6.2.324 STRB (immediate) page C6-1876 line 110516 MATCH x39000000/mask=xffc00000 +# CONSTRUCT x39000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x39000000/mask=xffc00000 --status nomem + +:strb Rt_GPR32, addrIndexed +is size.ldstr=0 & b_2729=7 & v=0 & b_2425=1 & b_23=0 & b_2222=0 & addrIndexed & Rt_GPR32 +{ + tmp:4 = Rt_GPR32; + build addrIndexed; + *addrIndexed = tmp:1; +} + +# C6.2.324 STRB (immediate) page C6-1876 line 110516 MATCH x38000400/mask=xffe00c00 +# C6.2.324 STRB (immediate) page C6-1876 line 110516 MATCH x38000c00/mask=xffe00c00 +# CONSTRUCT x38000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x38000400/mask=xffe00400 --status nomem + +:strb Rt_GPR32, addrIndexed +is size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR32 +{ + tmp:4 = Rt_GPR32; + build addrIndexed; + *addrIndexed = tmp:1; +} + +# C6.2.325 STRB (register) page C6-1879 line 110678 MATCH x38200800/mask=xffe00c00 +# CONSTRUCT x38200800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x38200800/mask=xffe00c00 --status nomem + +:strb Rt_GPR32, addrIndexed +is size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR32 +{ + tmp:4 = Rt_GPR32; + build addrIndexed; + *addrIndexed = tmp:1; +} + +# C6.2.326 STRH (immediate) page C6-1881 line 110781 MATCH x79000000/mask=xffc00000 +# CONSTRUCT x79000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x79000000/mask=xffc00000 --status nomem + +:strh Rt_GPR32, addrUIMM +is size.ldstr=1 & b_2729=7 & v=0 & b_2425=1 & b_23=0 & b_2222=0 & addrUIMM & Rn_GPR64xsp & Rt_GPR32 +{ + tmp:4 = Rt_GPR32; + *addrUIMM = tmp:2; +} + +# C6.2.326 STRH (immediate) page C6-1881 line 110781 MATCH x78000400/mask=xffe00c00 +# C6.2.326 STRH (immediate) page C6-1881 line 110781 MATCH x78000c00/mask=xffe00c00 +# CONSTRUCT x78000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x78000400/mask=xffe00400 --status nomem + +:strh Rt_GPR32, addrIndexed +is size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR32 +{ + tmp:4 = Rt_GPR32; + build addrIndexed; + *addrIndexed = tmp:2; +} + +# C6.2.327 STRH (register) page C6-1884 line 110943 MATCH x78200800/mask=xffe00c00 +# CONSTRUCT x78200800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x78200800/mask=xffe00c00 --status nomem + +:strh Rt_GPR32, addrIndexed +is size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR32 +{ + tmp:4 = Rt_GPR32; + build addrIndexed; + *addrIndexed = tmp:2; +} + +# C6.2.337 STTR page C6-1904 line 111916 MATCH xb8000800/mask=xbfe00c00 +# CONSTRUCT xf8000800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xf8000800/mask=xffe00c00 --status nomem + +:st^UnscPriv^"r" Rt_GPR64, addrIndexed +is size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_2223=0 & b_2121=0 & b_1011=2 & UnscPriv & addrIndexed & Rt_GPR64 +{ + data1:8 = Rt_GPR64; + build addrIndexed; + *addrIndexed = data1; +} + +# C6.2.338 STTRB page C6-1906 line 112029 MATCH x38000800/mask=xffe00c00 +# C6.2.347 STURB page C6-1924 line 112913 MATCH x38000000/mask=xffe00c00 +# CONSTRUCT x38000000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x38000000/mask=xffe00000 --status nomem + +:st^UnscPriv^"rb" Rt_GPR32, addrIndexed +is size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR32 +{ + local tmp:4 = Rt_GPR32; + build addrIndexed; + *addrIndexed = tmp:1; +} + +# C6.2.339 STTRH page C6-1908 line 112130 MATCH x78000800/mask=xffe00c00 +# C6.2.348 STURH page C6-1925 line 112984 MATCH x78000000/mask=xffe00c00 +# CONSTRUCT x78000000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x78000000/mask=xffe00000 --status nomem + +:st^UnscPriv^"rh" Rt_GPR32, addrIndexed +is size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR32 +{ + local tmp:4 = Rt_GPR32; + build addrIndexed; + *addrIndexed = tmp:2; +} + +# C6.2.346 STUR page C6-1922 line 112818 MATCH xb8000000/mask=xbfe00c00 +# CONSTRUCT xf8000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xf8000000/mask=xffe00c00 --status nomem + +:st^UnscPriv^"r" Rt_GPR64, addrIndexed +is size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2122=0 & b_1011=0 & UnscPriv & addrIndexed & Rt_GPR64 +{ + data1:8 = Rt_GPR64; + build addrIndexed; + *addrIndexed = data1; +} + +# C6.2.349 STXP page C6-1926 line 113055 MATCH x88200000/mask=xbfe08000 +# CONSTRUCT xc8200000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xc8200000/mask=xffe08000 --status nomem + +:stxp Rs_GPR32, Rt_GPR64, Rt2_GPR64, addrReg +is size.ldstr=3 & b_2429=0x8 & b_23=0 & L=0 & b_21=1 & Rs_GPR32 & b_15=0 & Rt2_GPR64 & addrReg & Rt_GPR64 & Rs_GPR64 +{ + status:1 = 1; + rsize:1 = 16; + check:1 = ExclusiveMonitorPass(addrReg, rsize); + if (!check) goto ; + *addrReg = Rt_GPR64; + *(addrReg + 8) = Rt2_GPR64; + status = ExclusiveMonitorsStatus(); + + Rs_GPR64 = zext(status); +} + +# C6.2.349 STXP page C6-1926 line 113055 MATCH x88200000/mask=xbfe08000 +# CONSTRUCT x88200000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x88200000/mask=xffe08000 --status nomem + +:stxp Rs_GPR32, Rt_GPR32, Rt2_GPR32, addrReg +is size.ldstr=2 & b_2429=0x8 & b_23=0 & L=0 & b_21=1 & Rs_GPR32 & b_15=0 & Rt2_GPR32 & addrReg & Rt_GPR32 & Rs_GPR64 +{ + status:1 = 1; + rsize:1 = 16; + check:1 = ExclusiveMonitorPass(addrReg, rsize); + if (!check) goto ; + *addrReg = Rt_GPR32; + *(addrReg + 4) = Rt2_GPR32; + status = ExclusiveMonitorsStatus(); + + Rs_GPR64 = zext(status); +} + +# C6.2.350 STXR page C6-1929 line 113222 MATCH x88000000/mask=xbfe08000 +# CONSTRUCT xc8000000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xc8000000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1014=0b11111 + +:stxr Rs_GPR32, Rt_GPR64, addrReg +is size.ldstr=3 & b_2429=0x8 & b_23=0 & L=0 & b_21=0 & Rs_GPR32 & b_15=0 & addrReg & Rt_GPR64 & Rs_GPR64 +{ + status:1 = 1; + rsize:1 = 16; + check:1 = ExclusiveMonitorPass(addrReg, rsize); + if (!check) goto ; + *addrReg = Rt_GPR64; + status = ExclusiveMonitorsStatus(); + + Rs_GPR64 = zext(status); +} + +# C6.2.350 STXR page C6-1929 line 113222 MATCH x88000000/mask=xbfe08000 +# CONSTRUCT x88000000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x88000000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1014=0b11111 + +:stxr Rs_GPR32, Rt_GPR32, addrReg +is size.ldstr=2 & b_2429=0x8 & b_23=0 & L=0 & b_21=0 & Rs_GPR32 & b_15=0 & addrReg & Rt_GPR32 & Rs_GPR64 +{ + status:1 = 1; + rsize:1 = 16; + check:1 = ExclusiveMonitorPass(addrReg, rsize); + if (!check) goto ; + *addrReg = Rt_GPR32; + status = ExclusiveMonitorsStatus(); + + Rs_GPR64 = zext(status); +} + +# C6.2.351 STXRB page C6-1931 line 113368 MATCH x08000000/mask=xffe08000 +# CONSTRUCT x08000000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x08000000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1014=0b11111 + +:stxrb Rs_GPR32, Rt_GPR32, addrReg +is size.ldstr=0 & b_2429=0x8 & b_23=0 & L=0 & b_21=0 & Rs_GPR32 & b_15=0 & addrReg & Rt_GPR32 & Rs_GPR64 +{ + status:1 = 1; + rsize:1 = 16; + check:1 = ExclusiveMonitorPass(addrReg, rsize); + if (!check) goto ; + local tmp:4 = Rt_GPR32; + *addrReg = tmp:1; + status = ExclusiveMonitorsStatus(); + + Rs_GPR64 = zext(status); +} + +# C6.2.352 STXRH page C6-1933 line 113496 MATCH x48000000/mask=xffe08000 +# CONSTRUCT x48000000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x48000000/mask=xffe08000 --status nomem +# To enforce SHOULD BE ONE fields add: b_1014=0b11111 + +:stxrh Rs_GPR32, Rt_GPR32, addrReg +is size.ldstr=1 & b_2429=0x8 & b_23=0 & L=0 & b_21=0 & Rs_GPR32 & b_15=0 & addrReg & Rt_GPR32 & Rs_GPR64 +{ + status:1 = 1; + rsize:1 = 16; + check:1 = ExclusiveMonitorPass(addrReg, rsize); + if (!check) goto ; + local tmp:4 = Rt_GPR32; + *addrReg = tmp:2; + status = ExclusiveMonitorsStatus(); + + Rs_GPR64 = zext(status); +} + +# C6.2.356 SUB (extended register) page C6-1940 line 113972 MATCH x4b200000/mask=x7fe00000 +# CONSTRUCT x4b200000/mask=xffe00000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x4b200000/mask=xffe00000 --status pass + +:sub Rd_GPR32wsp, Rn_GPR32wsp, ExtendRegShift32 +is sf=0 & op=1 & S=0 & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift32 & Rn_GPR32wsp & Rd_GPR32wsp & Rd_GPR64xsp +{ + tmp_2:4 = ExtendRegShift32; + tmp_1:4 = Rn_GPR32wsp - tmp_2; + Rd_GPR64xsp = zext(tmp_1); +} + +# C6.2.356 SUB (extended register) page C6-1940 line 113972 MATCH x4b200000/mask=x7fe00000 +# CONSTRUCT xcb200000/mask=xffe00000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xcb200000/mask=xffe00000 --status pass + +:sub Rd_GPR64xsp, Rn_GPR64xsp, ExtendRegShift64 +is sf=1 & op=1 & S=0 & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift64 & Rn_GPR64xsp & Rd_GPR64xsp +{ + tmp_2:8 = ExtendRegShift64; + tmp_1:8 = Rn_GPR64xsp - tmp_2; + Rd_GPR64xsp = tmp_1; +} + +# C6.2.357 SUB (immediate) page C6-1943 line 114120 MATCH x51000000/mask=x7f800000 +# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000 +# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f +# CONSTRUCT x51000000/mask=xdf000000 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst x51000000/mask=xdf000000 --status pass --comment "flags" + +:sub^SBIT_CZNO Rd_GPR32xsp, Rn_GPR32xsp, ImmShift32 +is sf=0 & b_30=1 & S & SBIT_CZNO & b_2428=0x11 & ImmShift32 & Rn_GPR32xsp & Rd_GPR32xsp & Rd_GPR64xsp +{ + subflags(Rn_GPR32xsp, ImmShift32); + tmp:4 = Rn_GPR32xsp - ImmShift32; + resultflags(tmp); + build SBIT_CZNO; + Rd_GPR64xsp = zext(tmp); +} + +# C6.2.357 SUB (immediate) page C6-1943 line 114120 MATCH x51000000/mask=x7f800000 +# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000 +# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f +# CONSTRUCT xd1000000/mask=xdf000000 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst xd1000000/mask=xdf000000 --status pass --comment "flags" + +:sub^SBIT_CZNO Rd_GPR64xsp, Rn_GPR64xsp, ImmShift64 +is sf=1 & b_30=1 & S & SBIT_CZNO & b_2428=0x11 & ImmShift64 & Rn_GPR64xsp & Rd_GPR64xsp +{ + subflags(Rn_GPR64xsp, ImmShift64); + Rd_GPR64xsp = Rn_GPR64xsp - ImmShift64; + resultflags(Rd_GPR64xsp); + build SBIT_CZNO; +} + +# C6.2.357 SUB (immediate) page C6-1943 line 114120 MATCH x51000000/mask=x7f800000 +# CONSTRUCT x51000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x51000000/mask=xffc00000 --status pass + +:sub Rd_GPR32wsp, Rn_GPR32wsp, Imm12_addsubimm_operand_i32_negimm_lsl0 +is sf=0 & op=1 & S=0 & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i32_negimm_lsl0 & Rn_GPR32wsp & Rd_GPR32wsp & Rd_GPR64xsp +{ + tmp_2:4 = Imm12_addsubimm_operand_i32_negimm_lsl0; + tmp_1:4 = Rn_GPR32wsp - tmp_2; + Rd_GPR64xsp = zext(tmp_1); +} + +# C6.2.357 SUB (immediate) page C6-1943 line 114120 MATCH x51000000/mask=x7f800000 +# CONSTRUCT x51400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x51400000/mask=xffc00000 --status pass + +:sub Rd_GPR32wsp, Rn_GPR32wsp, Imm12_addsubimm_operand_i32_negimm_lsl12 +is sf=0 & op=1 & S=0 & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i32_negimm_lsl12 & Rn_GPR32wsp & Rd_GPR32wsp & Rd_GPR64xsp +{ + tmp_2:4 = Imm12_addsubimm_operand_i32_negimm_lsl12; + tmp_1:4 = Rn_GPR32wsp - tmp_2; + Rd_GPR64xsp = zext(tmp_1); +} + +# C6.2.357 SUB (immediate) page C6-1943 line 114120 MATCH x51000000/mask=x7f800000 +# CONSTRUCT xd1000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd1000000/mask=xffc00000 --status pass + +:sub Rd_GPR64xsp, Rn_GPR64xsp, Imm12_addsubimm_operand_i64_negimm_lsl0 +is sf=1 & op=1 & S=0 & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i64_negimm_lsl0 & Rn_GPR64xsp & Rd_GPR64xsp +{ + tmp_2:8 = Imm12_addsubimm_operand_i64_negimm_lsl0; + tmp_1:8 = Rn_GPR64xsp - tmp_2; + Rd_GPR64xsp = tmp_1; +} + +# C6.2.357 SUB (immediate) page C6-1943 line 114120 MATCH x51000000/mask=x7f800000 +# CONSTRUCT xd1400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd1400000/mask=xffc00000 --status pass + +:sub Rd_GPR64xsp, Rn_GPR64xsp, Imm12_addsubimm_operand_i64_negimm_lsl12 +is sf=1 & op=1 & S=0 & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i64_negimm_lsl12 & Rn_GPR64xsp & Rd_GPR64xsp +{ + tmp_2:8 = Imm12_addsubimm_operand_i64_negimm_lsl12; + tmp_1:8 = Rn_GPR64xsp - tmp_2; + Rd_GPR64xsp = tmp_1; +} + +# C6.2.358 SUB (shifted register) page C6-1945 line 114221 MATCH x4b000000/mask=x7f200000 +# C6.2.234 NEG (shifted register) page C6-1694 line 100243 MATCH x4b0003e0/mask=x7f2003e0 +# CONSTRUCT x4b000000/mask=xff200000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x4b000000/mask=xff200000 --status pass + +:sub Rd_GPR32, Rn_GPR32, RegShift32 +is sf=0 & op=1 & s=0 & b_2428=0xb & b_2121=0 & RegShift32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp_2:4 = RegShift32; + tmp_1:4 = Rn_GPR32 - tmp_2; + Rd_GPR64 = zext(tmp_1); +} + +# C6.2.358 SUB (shifted register) page C6-1945 line 114221 MATCH x4b000000/mask=x7f200000 +# C6.2.234 NEG (shifted register) page C6-1694 line 100243 MATCH x4b0003e0/mask=x7f2003e0 +# CONSTRUCT xcb000000/mask=xff200000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xcb000000/mask=xff200000 --status pass + +:sub Rd_GPR64, Rn_GPR64, RegShift64 +is sf=1 & op=1 & s=0 & b_2428=0xb & b_2121=0 & RegShift64 & Rn_GPR64 & Rd_GPR64 +{ + tmp_2:8 = RegShift64; + tmp_1:8 = Rn_GPR64 - tmp_2; + Rd_GPR64 = tmp_1; +} + +# C6.2.362 SUBS (extended register) page C6-1950 line 114543 MATCH x6b200000/mask=x7fe00000 +# C6.2.62 CMP (extended register) page C6-1252 line 73406 MATCH x6b20001f/mask=x7fe0001f +# CONSTRUCT x6b200000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x6b200000/mask=xffe00000 --status pass --comment "flags" + +:subs Rd_GPR32, Rn_GPR32wsp, ExtendRegShift32 +is sf=0 & op=1 & S=1 & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift32 & Rn_GPR32wsp & Rd_GPR32 & Rd_GPR64 +{ + tmp_2:4 = ExtendRegShift32; + subflags(Rn_GPR32wsp, tmp_2); + tmp_1:4 = Rn_GPR32wsp - tmp_2; + resultflags(tmp_1); + Rd_GPR64 = zext(tmp_1); + affectflags(); +} + +# C6.2.362 SUBS (extended register) page C6-1950 line 114543 MATCH x6b200000/mask=x7fe00000 +# C6.2.364 SUBS (shifted register) page C6-1955 line 114807 MATCH x6b000000/mask=x7f200000 +# C6.2.62 CMP (extended register) page C6-1252 line 73406 MATCH x6b20001f/mask=x7fe0001f +# C6.2.64 CMP (shifted register) page C6-1256 line 73623 MATCH x6b00001f/mask=x7f20001f +# C6.2.235 NEGS page C6-1696 line 100340 MATCH x6b0003e0/mask=x7f2003e0 +# CONSTRUCT xeb000000/mask=xffc00000 MATCHED 5 DOCUMENTED OPCODES +# AUNIT --inst xeb000000/mask=xffc00000 --status pass --comment "flags" + +:subs Rd_GPR64, Rn_GPR64xsp, ExtendRegShift64 +is sf=1 & op=1 & S=1 & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift64 & Rn_GPR64xsp & Rd_GPR64 +{ + tmp_2:8 = ExtendRegShift64; + subflags(Rn_GPR64xsp, tmp_2); + tmp_1:8 = Rn_GPR64xsp - tmp_2; + resultflags(tmp_1); + Rd_GPR64 = tmp_1; + affectflags(); +} + +# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000 +# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f +# CONSTRUCT x71000000/mask=xffc00000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x71000000/mask=xffc00000 --status pass --comment "flags" + +:subs Rd_GPR32, Rn_GPR32wsp, Imm12_addsubimm_operand_i32_negimm_lsl0 +is sf=0 & op=1 & S=1 & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i32_negimm_lsl0 & Rn_GPR32wsp & Rd_GPR32 & Rd_GPR64 +{ + tmp_2:4 = Imm12_addsubimm_operand_i32_negimm_lsl0; + subflags(Rn_GPR32wsp, tmp_2); + tmp_1:4 = Rn_GPR32wsp - tmp_2; + resultflags(tmp_1); + Rd_GPR64 = zext(tmp_1); + affectflags(); +} + +# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000 +# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f +# CONSTRUCT x71400000/mask=xffc00000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x71400000/mask=xffc00000 --status pass --comment "flags" + +:subs Rd_GPR32, Rn_GPR32wsp, Imm12_addsubimm_operand_i32_negimm_lsl12 +is sf=0 & op=1 & S=1 & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i32_negimm_lsl12 & Rn_GPR32wsp & Rd_GPR32 & Rd_GPR64 +{ + tmp_2:4 = Imm12_addsubimm_operand_i32_negimm_lsl12; + subflags(Rn_GPR32wsp, tmp_2); + tmp_1:4 = Rn_GPR32wsp - tmp_2; + resultflags(tmp_1); + Rd_GPR64 = zext(tmp_1); + affectflags(); +} + +# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000 +# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f +# CONSTRUCT xf1000000/mask=xffc00000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xf1000000/mask=xffc00000 --status pass --comment "flags" + +:subs Rd_GPR64, Rn_GPR64xsp, Imm12_addsubimm_operand_i64_negimm_lsl0 +is sf=1 & op=1 & S=1 & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i64_negimm_lsl0 & Rn_GPR64xsp & Rd_GPR64 +{ + tmp_2:8 = Imm12_addsubimm_operand_i64_negimm_lsl0; + subflags(Rn_GPR64xsp, tmp_2); + tmp_1:8 = Rn_GPR64xsp - tmp_2; + resultflags(tmp_1); + Rd_GPR64 = tmp_1; + affectflags(); +} + +# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000 +# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f +# CONSTRUCT xf1400000/mask=xffc00000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xf1400000/mask=xffc00000 --status pass --comment "flags" + +:subs Rd_GPR64, Rn_GPR64xsp, Imm12_addsubimm_operand_i64_negimm_lsl12 +is sf=1 & op=1 & S=1 & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i64_negimm_lsl12 & Rn_GPR64xsp & Rd_GPR64 +{ + tmp_2:8 = Imm12_addsubimm_operand_i64_negimm_lsl12; + subflags(Rn_GPR64xsp, tmp_2); + tmp_1:8 = Rn_GPR64xsp - tmp_2; + resultflags(tmp_1); + Rd_GPR64 = tmp_1; + affectflags(); +} + +# C6.2.364 SUBS (shifted register) page C6-1955 line 114807 MATCH x6b000000/mask=x7f200000 +# C6.2.64 CMP (shifted register) page C6-1256 line 73623 MATCH x6b00001f/mask=x7f20001f +# C6.2.235 NEGS page C6-1696 line 100340 MATCH x6b0003e0/mask=x7f2003e0 +# CONSTRUCT x6b000000/mask=xff200000 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst x6b000000/mask=xff200000 --status pass + +:subs Rd_GPR32, Rn_GPR32, RegShift32 +is sf=0 & op=1 & s=1 & b_2428=0xb & b_2121=0 & RegShift32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp_2:4 = RegShift32; + subflags(Rn_GPR32, tmp_2); + tmp_1:4 = Rn_GPR32 - tmp_2; + resultflags(tmp_1); + Rd_GPR64 = zext(tmp_1); + affectflags(); +} + +# C6.2.364 SUBS (shifted register) page C6-1955 line 114807 MATCH x6b000000/mask=x7f200000 +# C6.2.64 CMP (shifted register) page C6-1256 line 73623 MATCH x6b00001f/mask=x7f20001f +# C6.2.235 NEGS page C6-1696 line 100340 MATCH x6b0003e0/mask=x7f2003e0 +# CONSTRUCT xeb000000/mask=xff200000 MATCHED 3 DOCUMENTED OPCODES +# AUNIT --inst xeb000000/mask=xff200000 --status pass + +:subs Rd_GPR64, Rn_GPR64, RegShift64 +is sf=1 & op=1 & s=1 & b_2428=0xb & b_2121=0 & RegShift64 & Rn_GPR64 & Rd_GPR64 & Rd +{ + tmp_2:8 = RegShift64; + subflags(Rn_GPR64, tmp_2); + tmp_1:8 = Rn_GPR64 - tmp_2; + resultflags(tmp_1); + Rd_GPR64 = tmp_1; + affectflags(); +} + +# C6.2.365 SVC page C6-1957 line 114930 MATCH xd4000001/mask=xffe0001f +# CONSTRUCT xd4000001/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd4000001/mask=xffe0001f --status nodest + +:svc imm16 +is b_2431=0xd4 & excCode=0 & imm16 & excCode2=0 & ll=1 +{ + CallSupervisor(imm16:2); +} + +# C6.2.366 SWPB, SWPAB, SWPALB, SWPLB page C6-1958 line 114973 MATCH x38208000/mask=xff20fc00 +# CONSTRUCT x38208000/mask=xff20fc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x38208000/mask=xff20fc00 --status nomem + +# size=0b00 (3031) + +:swp^ls_lor^"b" aa_Ws, aa_Wt, [Rn_GPR64xsp] +is b_3031=0b00 & b_2429=0b111000 & b_21=1 & b_1215=0b1000 & b_1011=0b00 & ls_loa & ls_lor & aa_Wt & ls_data1 & ls_mem1 & aa_Ws & Rn_GPR64xsp +{ build ls_loa; build ls_data1; ls_opc_swp(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; aa_Wt = tmp_ldWn; build ls_lor; } + +# C6.2.367 SWPH, SWPAH, SWPALH, SWPLH page C6-1960 line 115079 MATCH x78208000/mask=xff20fc00 +# CONSTRUCT x78208000/mask=xff20fc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x78208000/mask=xff20fc00 --status nomem + +# size=0b01 (3031) + +:swp^ls_lor^"h" aa_Ws, aa_Wt, [Rn_GPR64xsp] +is b_3031=0b01 & b_2429=0b111000 & b_21=1 & b_1215=0b1000 & b_1011=0b00 & ls_loa & ls_lor & aa_Wt & ls_data2 & ls_mem2 & aa_Ws & Rn_GPR64xsp +{ build ls_loa; build ls_data2; ls_opc_swp(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; aa_Wt = tmp_ldWn; build ls_lor; } + +# C6.2.368 SWP, SWPA, SWPAL, SWPL page C6-1962 line 115186 MATCH xb8208000/mask=xbf20fc00 +# CONSTRUCT xb8208000/mask=xff20fc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xb8208000/mask=xff20fc00 --status nomem + +# size=0b10 (3031) + +:swp^ls_lor aa_Ws, aa_Wt, [Rn_GPR64xsp] +is b_3031=0b10 & b_2429=0b111000 & b_21=1 & b_1215=0b1000 & b_1011=0b00 & ls_loa & ls_lor & aa_Wt & ls_data4 & ls_mem4 & aa_Ws & Rn_GPR64xsp +{ build ls_loa; build ls_data4; ls_opc_swp(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; aa_Wt = tmp_ldWn; build ls_lor; } + +# C6.2.368 SWP, SWPA, SWPAL, SWPL page C6-1962 line 115186 MATCH xb8208000/mask=xbf20fc00 +# CONSTRUCT xf8208000/mask=xff20fc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xf8208000/mask=xff20fc00 --status nomem + +# size=0b11 (3031) + +:swp^ls_lor aa_Xs, aa_Xt, [Rn_GPR64xsp] +is b_3031=0b11 & b_2429=0b111000 & b_21=1 & b_1215=0b1000 & b_1011=0b00 & ls_loa & ls_lor & aa_Xt & ls_data8 & ls_mem8 & aa_Xs & Rn_GPR64xsp +{ build ls_loa; build ls_data8; ls_opc_swp(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; aa_Xt = tmp_ldXn; build ls_lor; } + +# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00 +# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000 +# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000 +# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000 +# CONSTRUCT x93401c00/mask=xfffffc06 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst x93401c00/mask=xfffffc06 --status pass + +# Special case of sbfm where imms='000111' and immr='000000' + +:sxtb Rd_GPR64, Rn_GPR32 +is ImmR=0x0 & ImmS=0x7 & ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=0 & sf=1 & opc=0 & b_2428=0x13 & b_2323=0 & n=1 & Rn_GPR32 & Rd_GPR64 +{ + tmp:4 = Rn_GPR32; + tmp_byte:1 = tmp:1; + result:8 = sext(tmp_byte); + Rd_GPR64 = result; +} + +# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00 +# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000 +# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000 +# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000 +# CONSTRUCT x13001c00/mask=xfffffc06 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst x13001c00/mask=xfffffc06 --status pass + +# Special case of sbfm when ImmS=7 and ImmR=0. Note that this implies ImmS > ImmR-1 +# Otherwise, this might appear to conflict with sbfiz + +:sxtb Rd_GPR32, Rn_GPR32 +is ImmR=0x0 & ImmS=0x7 & ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=0 & sf=0 & opc=0 & b_2428=0x13 & b_2323=0 & n=0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp:4 = Rn_GPR32; + tmp_byte:1 = tmp:1; + result:4 = sext(tmp_byte); + Rd_GPR64 = zext(result); +} + +# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00 +# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000 +# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000 +# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000 +# CONSTRUCT x93403c00/mask=xfffffc06 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst x93403c00/mask=xfffffc06 --status pass + +# Special case of sbfm where imms='001111' and immr='000000' + +:sxth Rd_GPR64, Rn_GPR32 +is ImmR=0x0 & ImmS=0xf & ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=0 & sf=1 & opc=0 & b_2428=0x13 & b_2323=0 & n=1 & Rn_GPR32 & Rd_GPR64 +{ + tmp:4 = Rn_GPR32; + tmp_1:2 = tmp:2; + tmp_2:8 = sext(tmp_1); + Rd_GPR64 = tmp_2; +} + +# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00 +# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000 +# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000 +# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000 +# CONSTRUCT x13003c00/mask=xfffffc06 MATCHED 4 DOCUMENTED OPCODES +# AUNIT --inst x13003c00/mask=xfffffc06 --status pass + +# Special case of sbfm where imms='001111' and immr='000000' + +:sxth Rd_GPR32, Rn_GPR32 +is ImmR=0x0 & ImmS=0xf & ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=0 & sf=0 & opc=0 & b_2428=0x13 & b_2323=0 & n=0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp:4 = Rn_GPR32; + tmp_1:2 = tmp:2; + tmp_2:4 = sext(tmp_1); + Rd_GPR64 = zext(tmp_2); +} + +# C6.2.371 SXTW page C6-1968 line 115498 MATCH x93407c00/mask=xfffffc00 +# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00 +# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000 +# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000 +# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000 +# CONSTRUCT x93407c00/mask=xfffffc06 MATCHED 5 DOCUMENTED OPCODES +# AUNIT --inst x93407c00/mask=xfffffc06 --status pass + +# Special case of sbfm where imms='011111' and immr='000000' + +:sxtw Rd_GPR64, Rn_GPR32 +is ImmR=0x0 & ImmS=0x1f & ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=0 & sf=1 & opc=0 & b_2428=0x13 & b_2323=0 & n=1 & Rn_GPR32 & Rd_GPR64 +{ + tmp:4 = Rn_GPR32; + Rd_GPR64 = sext(tmp); +} + +# C6.2.286 SYS page C6-979 line 56782 KEEPWITH + +SysArgs: Op1_uimm3, CRn_CRx, CRm_CRx, Op2_uimm3, Rt_GPR64 is Op1_uimm3 & CRn_CRx & CRm_CRx & Op2_uimm3 & aa_Xt & Rt_GPR64 { export Rt_GPR64; } +SysArgs: Op1_uimm3, CRn_CRx, CRm_CRx, Op2_uimm3 is Op1_uimm3 & CRn_CRx & CRm_CRx & Op2_uimm3 & aa_Xt=31 & Rt_GPR64 { export 0:8; } + +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00 +# C6.2.39 BRB page C6-1212 line 71361 MATCH xd5097200/mask=xffffff00 +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# CONSTRUCT xd5080000/mask=xfff80000 MATCHED 6 DOCUMENTED OPCODES +# AUNIT --inst xd5080000/mask=xfff80000 --status nodest + +:sys SysArgs +is b_1931=0b1101010100001 & Op1_uimm3 & CRn_CRx & CRm_CRx & Op2_uimm3 & SysArgs +{ + tmp1:4 = Op1_uimm3; + tmp2:4 = CRn_CRx; + tmp3:4 = CRm_CRx; + tmp4:4 = Op2_uimm3; + SysOp_W(tmp1, tmp2, tmp3, tmp4, SysArgs); +} + +# C6.2.373 SYSL page C6-1971 line 115652 MATCH xd5280000/mask=xfff80000 +# CONSTRUCT xd5280000/mask=xfff80000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd5280000/mask=xfff80000 --status nodest + +:sysl Rt_GPR64, Op1_uimm3, CRn_CRx, CRm_CRx, Op2_uimm3 +is b_2431=0xd5 & b_2223=0 & l=1 & Op0=1 & Op1_uimm3 & CRn_CRx & CRm_CRx & Op2_uimm3 & aa_Xt & Rt_GPR64 +{ + tmp1:4 = Op1_uimm3; + tmp2:4 = CRn_CRx; + tmp3:4 = CRm_CRx; + tmp4:4 = Op2_uimm3; + Rt_GPR64 = SysOp_R(tmp1, tmp2, tmp3, tmp4); +} + +# C6.2.373 SYSL page C6-1971 line 115652 MATCH xd5280000/mask=xfff80000 +# CONSTRUCT xd528001f/mask=xfff8001f MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xd528001f/mask=xfff8001f --status nodest + +:sysl Op1_uimm3, CRn_CRx, CRm_CRx, Op2_uimm3 +is b_2431=0xd5 & b_2223=0 & l=1 & Op0=1 & Op1_uimm3 & CRn_CRx & CRm_CRx & Op2_uimm3 & aa_Xt=31 & Rt_GPR64 +{ + tmp1:4 = Op1_uimm3; + tmp2:4 = CRn_CRx; + tmp3:4 = CRm_CRx; + tmp4:4 = Op2_uimm3; + SysOp_R(tmp1, tmp2, tmp3, tmp4); +} + +# C6.2.374 TBNZ page C6-1972 line 115708 MATCH x37000000/mask=x7f000000 +# C6.2.375 TBZ page C6-1973 line 115766 MATCH x36000000/mask=x7f000000 +# CONSTRUCT xb6000000/mask=xfe000000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xb6000000/mask=xfe000000 --status nodest + +:tb^ZeroOp Rd_GPR64, BitPos, Addr14 +is sf=1 & b_2530=0x1b & BitPos & ZeroOp & Addr14 & Rd_GPR64 +{ + tmp:1 = BitPos; + if (tmp == ZeroOp) goto Addr14; +} + +# C6.2.374 TBNZ page C6-1972 line 115708 MATCH x37000000/mask=x7f000000 +# C6.2.375 TBZ page C6-1973 line 115766 MATCH x36000000/mask=x7f000000 +# CONSTRUCT x36000000/mask=xfe000000 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x36000000/mask=xfe000000 --status nodest + +:tb^ZeroOp Rd_GPR32, BitPos, Addr14 +is sf=0 & b_2530=0x1b & BitPos & ZeroOp & Addr14 & Rd_GPR32 +{ + tmp:1 = BitPos; + if (tmp == ZeroOp) goto Addr14; +} + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50c8020/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50c8020/mask=xffffffe0 --status nodest + +:tlbi "IPAS2E1IS", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0000 & b_0507=0b001 & Rt_GPR64 +{ TLBI_IPAS2E1IS(Rt_GPR64); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50c80a0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50c80a0/mask=xffffffe0 --status nodest + +:tlbi "IPAS2LE1IS", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0000 & b_0507=0b101 & Rt_GPR64 +{ TLBI_IPAS2LE1IS(Rt_GPR64); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5088300/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd5088300/mask=xffffffe0 --status nodest + +:tlbi "VMALLE1IS" +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b000 +{ TLBI_VMALLE1IS(); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50c8300/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50c8300/mask=xffffffe0 --status nodest + +:tlbi "ALLE2IS" +is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b000 +{ TLBI_ALLE2IS(); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50e8300/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50e8300/mask=xffffffe0 --status nodest + +:tlbi "ALLE3IS" +is b_1931=0b1101010100001 & b_1618=0b110 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b000 +{ TLBI_ALLE3IS(); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5088320/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd5088320/mask=xffffffe0 --status nodest + +:tlbi "VAE1IS", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b001 & Rt_GPR64 +{ TLBI_VAE1IS(Rt_GPR64); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50c8320/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50c8320/mask=xffffffe0 --status nodest + +:tlbi "VAE2IS", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b001 & Rt_GPR64 +{ TLBI_VAE2IS(Rt_GPR64); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50e8320/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50e8320/mask=xffffffe0 --status nodest + +:tlbi "VAE3IS", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b110 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b001 & Rt_GPR64 +{ TLBI_VAE3IS(Rt_GPR64); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5088340/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd5088340/mask=xffffffe0 --status nodest + +:tlbi "ASIDE1IS", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b010 & Rt_GPR64 +{ TLBI_ASIDE1IS(Rt_GPR64); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5088360/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd5088360/mask=xffffffe0 --status nodest + +:tlbi "VAAE1IS", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b011 & Rt_GPR64 +{ TLBI_VAAE1IS(Rt_GPR64); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50c8380/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50c8380/mask=xffffffe0 --status nodest + +:tlbi "ALLE1IS" +is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b100 +{ TLBI_ALLE1IS(); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50883a0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50883a0/mask=xffffffe0 --status nodest + +:tlbi "VALE1IS", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b101 & Rt_GPR64 +{ TLBI_VALE1IS(Rt_GPR64); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50c83a0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50c83a0/mask=xffffffe0 --status nodest + +:tlbi "VALE2IS", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b101 & Rt_GPR64 +{ TLBI_VALE2IS(Rt_GPR64); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50e83a0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50e83a0/mask=xffffffe0 --status nodest + +:tlbi "VALE3IS", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b110 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b101 & Rt_GPR64 +{ TLBI_VALE3IS(Rt_GPR64); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50c83c0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50c83c0/mask=xffffffe0 --status nodest + +:tlbi "VMALLS12E1IS" +is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b110 +{ TLBI_VMALLS12E1IS(); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50883e0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50883e0/mask=xffffffe0 --status nodest + +:tlbi "VAALE1IS", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b111 & Rt_GPR64 +{ TLBI_VAALE1IS(Rt_GPR64); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50c8420/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50c8420/mask=xffffffe0 --status nodest + +:tlbi "IPAS2E1", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0100 & b_0507=0b001 & Rt_GPR64 +{ TLBI_IPAS2E1(Rt_GPR64); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50c84a0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50c84a0/mask=xffffffe0 --status nodest + +:tlbi "IPAS2LE1", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0100 & b_0507=0b101 & Rt_GPR64 +{ TLBI_IPAS2LE1(Rt_GPR64); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5088700/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd5088700/mask=xffffffe0 --status nodest + +:tlbi "VMALLE1" +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b000 +{ TLBI_VMALLE1(); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50c8700/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50c8700/mask=xffffffe0 --status nodest + +:tlbi "ALLE2" +is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b000 +{ TLBI_ALLE2(); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50e8700/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50e8700/mask=xffffffe0 --status nodest + +:tlbi "ALLE3" +is b_1931=0b1101010100001 & b_1618=0b110 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b000 +{ TLBI_ALLE3(); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5088720/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd5088720/mask=xffffffe0 --status nodest + +:tlbi "VAE1", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b001 & Rt_GPR64 +{ TLBI_VAE1(Rt_GPR64); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50c8720/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50c8720/mask=xffffffe0 --status nodest + +:tlbi "VAE2", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b001 & Rt_GPR64 +{ TLBI_VAE2(Rt_GPR64); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50e8720/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50e8720/mask=xffffffe0 --status nodest + +:tlbi "VAE3", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b110 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b001 & Rt_GPR64 +{ TLBI_VAE3(Rt_GPR64); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5088740/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd5088740/mask=xffffffe0 --status nodest + +:tlbi "ASIDE1", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b010 & Rt_GPR64 +{ TLBI_ASIDE1(Rt_GPR64); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5088760/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd5088760/mask=xffffffe0 --status nodest + +:tlbi "VAAE1", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b011 & Rt_GPR64 +{ TLBI_VAAE1(Rt_GPR64); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50c8780/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50c8780/mask=xffffffe0 --status nodest + +:tlbi "ALLE1" +is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b100 +{ TLBI_ALLE1(); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50887a0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50887a0/mask=xffffffe0 --status nodest + +:tlbi "VALE1", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b101 & Rt_GPR64 +{ TLBI_VALE1(Rt_GPR64); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50c87a0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50c87a0/mask=xffffffe0 --status nodest + +:tlbi "VALE2", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b101 & Rt_GPR64 +{ TLBI_VALE2(Rt_GPR64); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50e87a0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50e87a0/mask=xffffffe0 --status nodest + +:tlbi "VALE3", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b110 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b101 & Rt_GPR64 +{ TLBI_VALE3(Rt_GPR64); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50c87c0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50c87c0/mask=xffffffe0 --status nodest + +:tlbi "VMALLS12E1" +is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b110 +{ TLBI_VMALLS12E1(); } + +# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50887e0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50887e0/mask=xffffffe0 --status nodest + +:tlbi "VAALE1", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b111 & Rt_GPR64 +{ TLBI_VAALE1(Rt_GPR64); } + +# C6.2.382 TST (immediate) page C6-1983 line 116255 MATCH x7200001f/mask=x7f80001f +# C6.2.14 ANDS (immediate) page C6-1169 line 69185 MATCH x72000000/mask=x7f800000 +# CONSTRUCT x7200001f/mask=xff80001f MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x7200001f/mask=xff80001f --status pass --comment "flags" + +:tst Rn_GPR32, DecodeWMask32 +is sf=0 & opc=3 & b_2428=0x12 & b_2323=0 & DecodeWMask32 & Rn_GPR32 & Rd=0x1f +{ + tmp_2:4 = DecodeWMask32; + tmp_1:4 = Rn_GPR32 & tmp_2; + resultflags(tmp_1); + affectLflags(); +} + +# C6.2.382 TST (immediate) page C6-1983 line 116255 MATCH x7200001f/mask=x7f80001f +# C6.2.14 ANDS (immediate) page C6-1169 line 69185 MATCH x72000000/mask=x7f800000 +# CONSTRUCT xf200001f/mask=xff80001f MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xf200001f/mask=xff80001f --status pass --comment "flags" + +:tst Rn_GPR64, DecodeWMask64 +is sf=1 & opc=3 & b_2428=0x12 & b_2323=0 & DecodeWMask64 & Rn_GPR64 & Rd=0x1f +{ + tmp_2:8 = DecodeWMask64; + tmp_1:8 = Rn_GPR64 & tmp_2; + resultflags(tmp_1); + affectLflags(); +} + +# C6.2.383 TST (shifted register) page C6-1984 line 116319 MATCH x6a00001f/mask=x7f20001f +# C6.2.15 ANDS (shifted register) page C6-1171 line 69286 MATCH x6a000000/mask=x7f200000 +# CONSTRUCT x6a00001f/mask=xff20001f MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x6a00001f/mask=xff20001f --status pass --comment "flags" + +:tst Rn_GPR32, RegShift32Log +is sf=0 & opc=3 & b_2428=0xa & N=0 & RegShift32Log & Rn_GPR32 & Rd=0x1f +{ + tmp_2:4 = RegShift32Log; + tmp_1:4 = Rn_GPR32 & tmp_2; + resultflags(tmp_1); + affectLflags(); +} + +# C6.2.383 TST (shifted register) page C6-1984 line 116319 MATCH x6a00001f/mask=x7f20001f +# C6.2.15 ANDS (shifted register) page C6-1171 line 69286 MATCH x6a000000/mask=x7f200000 +# CONSTRUCT xea00001f/mask=xff20001f MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xea00001f/mask=xff20001f --status pass --comment "flags" + +:tst Rn_GPR64, RegShift64Log +is sf=1 & opc=3 & b_2428=0xa & N=0 & RegShift64Log & Rn_GPR64 & Rd=0x1f +{ + tmp_2:8 = RegShift64Log; + tmp_1:8 = Rn_GPR64 & tmp_2; + resultflags(tmp_1); + affectLflags(); +} + +# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000 +# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000 +# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00 +# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000 +# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000 +# C6.2.394 UXTB page C6-2002 line 117228 MATCH x53001c00/mask=xfffffc00 +# C6.2.395 UXTH page C6-2003 line 117288 MATCH x53003c00/mask=xfffffc00 +# CONSTRUCT x53000008/mask=xffe0800c MATCHED 7 DOCUMENTED OPCODES +# AUNIT --inst x53000008/mask=xffe0800c --status pass +# Special case of ubfm where UInt(imms) < UInt(immr). +# Note because LSL is preferred where imms + 1 == immr, we use ImmS_LT_ImmR_minus_1 +# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue(); + +:ubfiz Rd_GPR32, Rn_GPR32, ubfiz_lsb, ubfiz_width +is ImmS_LT_ImmR_minus_1=1 & ImmS_EQ_ImmR=0 & sf=0 & opc=2 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & ubfiz_lsb & ubfiz_width & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 & DecodeWMask32 & DecodeTMask32 +{ + local wmask:4 = DecodeWMask32; + local tmask:4 = DecodeTMask32; + local src:4 = Rn_GPR32; + local bot:4 = ((src>>ImmRConst32)|(src<<(32-ImmRConst32))) & wmask; + Rd_GPR64 = zext(bot & tmask); +} + +# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000 +# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000 +# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00 +# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000 +# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000 +# CONSTRUCT xd340000a/mask=xffc0000a MATCHED 5 DOCUMENTED OPCODES +# AUNIT --inst xd340000a/mask=xffc0000a --status pass +# Special case of ubfm where UInt(imms) < UInt(immr). +# Note because LSL is preferred where imms + 1 == immr, we use ImmS_LT_ImmR_minus_1 + +:ubfiz Rd_GPR64, Rn_GPR64, ubfiz_lsb64, ubfiz_width +is ImmS_LT_ImmR_minus_1=1 & ImmS_LT_ImmR=1 & sf=1 & opc=2 & b_2428=0x13 & b_2323=0 & n=1 & ImmR_bitfield64_imm & ImmS_bitfield64_imm & ImmRConst64 & ubfiz_lsb64 & ubfiz_width & Rn_GPR64 & Rd_GPR64 & DecodeWMask64 & DecodeTMask64 +{ + local wmask:8 = DecodeWMask64; + local tmask:8 = DecodeTMask64; + local src:8 = Rn_GPR64; + local bot:8 = ((src>>ImmRConst64)|(src<<(64-ImmRConst64))) & wmask; + Rd_GPR64 = bot & tmask; +} + +# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000 +# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000 +# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00 +# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000 +# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000 +# C6.2.394 UXTB page C6-2002 line 117228 MATCH x53001c00/mask=xfffffc00 +# C6.2.395 UXTH page C6-2003 line 117288 MATCH x53003c00/mask=xfffffc00 +# CONSTRUCT x53000000/mask=xffe08000 MATCHED 7 DOCUMENTED OPCODES +# AUNIT --inst x53000000/mask=xffe08000 --status pass +# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue(); + +:ubfm Rd_GPR32, Rn_GPR32, ImmRConst32, ImmSConst32 +is sf=0 & opc=2 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & ImmSConst32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 & DecodeWMask32 & DecodeTMask32 +{ + local wmask:4 = DecodeWMask32; + local tmask:4 = DecodeTMask32; + local src:4 = Rn_GPR32; + local bot:4 = ((src>>ImmRConst32)|(src<<(32-ImmRConst32))) & wmask; + Rd_GPR64 = zext(bot & tmask); +} + +# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000 +# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000 +# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00 +# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000 +# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000 +# CONSTRUCT xd3400000/mask=xffc00000 MATCHED 5 DOCUMENTED OPCODES +# AUNIT --inst xd3400000/mask=xffc00000 --status pass + +:ubfm Rd_GPR64, Rn_GPR64, ImmRConst64, ImmSConst64 +is sf=1 & opc=2 & b_2428=0x13 & b_2323=0 & n=1 & ImmR_bitfield64_imm & ImmS_bitfield64_imm & ImmRConst64 & ImmSConst64 & Rn_GPR64 & Rd_GPR64 & DecodeWMask64 & DecodeTMask64 +{ + local wmask:8 = DecodeWMask64; + local tmask:8 = DecodeTMask64; + local src:8 = Rn_GPR64; + local bot:8 = ((src>>ImmRConst64)|(src<<(64-ImmRConst64))) & wmask; + Rd_GPR64 = bot & tmask; +} + +# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000 +# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000 +# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00 +# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000 +# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000 +# C6.2.394 UXTB page C6-2002 line 117228 MATCH x53001c00/mask=xfffffc00 +# C6.2.395 UXTH page C6-2003 line 117288 MATCH x53003c00/mask=xfffffc00 +# CONSTRUCT x53000010/mask=xffe0801a MATCHED 7 DOCUMENTED OPCODES +# AUNIT --inst x53000010/mask=xffe0801a --status pass +# Special case of ubfm as determined by BFXPreferred() +# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue(); + +:ubfx Rd_GPR32, Rn_GPR32, ImmRConst32, ubfx_width +is ImmS_ne_1f=1 & ImmS_LT_ImmR=0 & ImmS_LT_ImmR_minus_1=0 & ImmRConst32 & ubfx_width & sf=0 & opc=2 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 & DecodeWMask32 & DecodeTMask32 +{ + local wmask:4 = DecodeWMask32; + local tmask:4 = DecodeTMask32; + local src:4 = Rn_GPR32; + local bot:4 = ((src>>ImmRConst32)|(src<<(32-ImmRConst32))) & wmask; + Rd_GPR64 = zext(bot & tmask); +} + +# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000 +# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000 +# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00 +# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000 +# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000 +# CONSTRUCT xd3400020/mask=xffc0002a MATCHED 5 DOCUMENTED OPCODES +# AUNIT --inst xd3400020/mask=xffc0002a --status pass + +# Special case of ubfm as determined by BFXPreferred() + +:ubfx Rd_GPR64, Rn_GPR64, ImmRConst64, ubfx_width +is ImmS_ne_3f=1 & ImmS_LT_ImmR=0 & ImmS_LT_ImmR_minus_1=0 & ImmRConst64 & ubfx_width & sf=1 & opc=2 & b_2428=0x13 & b_2323=0 & n=1 & ImmR_bitfield64_imm & ImmS_bitfield64_imm & Rn_GPR64 & Rd_GPR64 & DecodeWMask64 & DecodeTMask64 +{ + local wmask:8 = DecodeWMask64; + local tmask:8 = DecodeTMask64; + local src:8 = Rn_GPR64; + local bot:8 = ((src>>ImmRConst64)|(src<<(64-ImmRConst64))) & wmask; + Rd_GPR64 = bot & tmask; +} + +# C6.2.388 UDIV page C6-1994 line 116786 MATCH x1ac00800/mask=x7fe0fc00 +# CONSTRUCT x1ac00800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x1ac00800/mask=xffe0fc00 --status pass + +:udiv Rd_GPR32, Rn_GPR32, Rm_GPR32 +is sf=0 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR32 & b_1015=0x2 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + local tmp_1:4 = 0; + if (Rm_GPR32 == 0) goto ; + tmp_1 = Rn_GPR32 / Rm_GPR32; + + Rd_GPR64 = zext(tmp_1); +} + +# C6.2.388 UDIV page C6-1994 line 116786 MATCH x1ac00800/mask=x7fe0fc00 +# CONSTRUCT x9ac00800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x9ac00800/mask=xffe0fc00 --status pass + +:udiv Rd_GPR64, Rn_GPR64, Rm_GPR64 +is sf=1 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR64 & b_1015=0x2 & Rn_GPR64 & Rd_GPR64 +{ + local tmp_1:8 = 0; + if (Rm_GPR64 == 0) goto ; + tmp_1 = Rn_GPR64 / Rm_GPR64; + + Rd_GPR64 = tmp_1; +} + +# C6.2.389 UMADDL page C6-1995 line 116855 MATCH x9ba00000/mask=xffe08000 +# CONSTRUCT x9ba00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x9ba00000/mask=xffe08000 --status pass + +:umaddl Rd_GPR64, Rn_GPR32, Rm_GPR32, Ra_GPR64 +is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=5 & Rm_GPR32 & op.dp3_o0=0 & Ra_GPR64 & Rn_GPR32 & Rd_GPR64 +{ + tmp_3:8 = zext(Rn_GPR32); + tmp_4:8 = zext(Rm_GPR32); + tmp_2:8 = tmp_3 * tmp_4; + tmp_1:8 = Ra_GPR64 + tmp_2; + Rd_GPR64 = tmp_1; +} + +# C6.2.390 UMNEGL page C6-1997 line 116945 MATCH x9ba0fc00/mask=xffe0fc00 +# C6.2.391 UMSUBL page C6-1998 line 117009 MATCH x9ba08000/mask=xffe08000 +# CONSTRUCT x9ba0fc00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x9ba0fc00/mask=xffe0fc00 --status pass + +:umnegl Rd_GPR64, Rn_GPR32, Rm_GPR32 +is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=5 & Rm_GPR32 & op.dp3_o0=1 & Ra=0x1f & Rn_GPR32 & Rd_GPR64 +{ + tmp_3:8 = zext(Rn_GPR32); + tmp_4:8 = zext(Rm_GPR32); + tmp_2:8 = tmp_3 * tmp_4; + tmp_1:8 = - tmp_2; + Rd_GPR64 = tmp_1; +} + +# C6.2.391 UMSUBL page C6-1998 line 117009 MATCH x9ba08000/mask=xffe08000 +# CONSTRUCT x9ba08000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x9ba08000/mask=xffe08000 --status pass + +:umsubl Rd_GPR64, Rn_GPR32, Rm_GPR32, Ra_GPR64 +is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=5 & Rm_GPR32 & op.dp3_o0=1 & Ra_GPR64 & Rn_GPR32 & Rd_GPR64 +{ + tmp_3:8 = zext(Rn_GPR32); + tmp_4:8 = zext(Rm_GPR32); + tmp_2:8 = tmp_3 * tmp_4; + tmp_1:8 = Ra_GPR64 - tmp_2; + Rd_GPR64 = tmp_1; +} + +# C6.2.392 UMULH page C6-2000 line 117098 MATCH x9bc00000/mask=xffe08000 +# CONSTRUCT x9bc00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst x9bc00000/mask=xffe08000 --status pass +# To enforce SHOULD BE ONE fields add: b_1014=0b11111 + +:umulh Rd_GPR64, Rn_GPR64, Rm_GPR64 +is sf=1 & op.dp3=0 & b_2428=0x1b & op.dp3_op31=6 & Rm_GPR64 & op.dp3_o0=0 & Ra & Rn_GPR64 & Rd_GPR64 +{ + local tmpq:16 = zext(Rn_GPR64) * zext(Rm_GPR64); + Rd_GPR64 = tmpq(8); +} + +# C6.2.393 UMULL page C6-2001 line 117165 MATCH x9ba07c00/mask=xffe0fc00 +# C6.2.389 UMADDL page C6-1995 line 116855 MATCH x9ba00000/mask=xffe08000 +# CONSTRUCT x9ba07c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst x9ba07c00/mask=xffe0fc00 --status pass + +:umull Rd_GPR64, Rn_GPR32, Rm_GPR32 +is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=5 & Rm_GPR32 & op.dp3_o0=0 & Ra=0x1f & Rn_GPR32 & Rd_GPR64 +{ + tmp_3:8 = zext(Rn_GPR32); + tmp_4:8 = zext(Rm_GPR32); + tmp_2:8 = tmp_3 * tmp_4; + Rd_GPR64 = tmp_2; +} + +# C6.2.394 UXTB page C6-2002 line 117228 MATCH x53001c00/mask=xfffffc00 +# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000 +# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000 +# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000 +# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000 +# CONSTRUCT x53001c10/mask=xfffffc1e MATCHED 5 DOCUMENTED OPCODES +# AUNIT --inst x53001c10/mask=xfffffc1e --status pass + +# Alias for ubfm where immr=='000000' and imms='000111' +# These imply things about the inequalities + +:uxtb Rd_GPR32, Rn_GPR32 +is ImmR=0x0 & ImmS=0x7 & ImmS_ne_1f=1 & ImmS_LT_ImmR=0 & ImmS_LT_ImmR_minus_1=0 & ImmS_EQ_ImmR=0 & sf=0 & opc=2 & b_2428=0x13 & b_2323=0 & n=0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp:4 = Rn_GPR32; + Rd_GPR64 = zext(tmp:1); +} + +# C6.2.395 UXTH page C6-2003 line 117288 MATCH x53003c00/mask=xfffffc00 +# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000 +# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000 +# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000 +# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000 +# CONSTRUCT x53003c10/mask=xfffffc1e MATCHED 5 DOCUMENTED OPCODES +# AUNIT --inst x53003c10/mask=xfffffc1e --status pass + +# Alias for ubfm where immr=='000000' and imms='001111' +# These imply things about the inequalities + +:uxth Rd_GPR32, Rn_GPR32 +is ImmR=0x0 & ImmS=0x0f & ImmS_ne_1f=1 & ImmS_LT_ImmR=0 & ImmS_LT_ImmR_minus_1=0 & ImmS_EQ_ImmR=0 & sf=0 & opc=2 & b_2428=0x13 & b_2323=0 & n=0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 +{ + tmp:4 = Rn_GPR32; + Rd_GPR64 = zext(tmp:2); +} + +# C6.2.396 WFE page C6-2004 line 117348 MATCH xd503205f/mask=xffffffff +# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f +# CONSTRUCT xd503205f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd503205f/mask=xffffffff --status nodest + +:wfe +is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low=2 & Rt=0x1f +{ + WaitForEvent(); +} + +# C6.2.397 WFET page C6-2005 line 117387 MATCH xd5031000/mask=xffffffe0 +# CONSTRUCT xd5031000/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES +# xd5031000/mask=xffffffe0 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=110101010000001100010000000..... + +:wfet Rd_GPR64 +is b_0531=0x6a81880 & Rd_GPR64 +{ + WaitForEvent(Rd_GPR64); +} + +# C6.2.398 WFI page C6-2006 line 117439 MATCH xd503207f/mask=xffffffff +# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f +# CONSTRUCT xd503207f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd503207f/mask=xffffffff --status nodest + +:wfi +is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low=3 & Rt=0x1f +{ + WaitForInterrupt(); +} + +# C6.2.399 WFIT page C6-2007 line 117477 MATCH xd5031020/mask=xffffffe0 +# CONSTRUCT xd5031020/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES +# xd5031020/mask=xffffffe0 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=110101010000001100010000001..... + +:wfit Rd_GPR64 +is b_0531=0x6a81881 & Rd_GPR64 +{ + WaitForInterrupt(Rd_GPR64); +} + +# C6.2.401 XPACD, XPACI, XPACLRI page C6-2009 line 117573 MATCH xdac143e0/mask=xfffffbe0 +# CONSTRUCT xdac147e0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xdac147e0/mask=xffffffe0 --status noqemu +# D == 1 XPACD variant + +:xpacd Rd_GPR64 +is xpacd__PACpart & b_1131=0b110110101100000101000 & b_0509=0b11111 & b_10=1 & Rd_GPR64 +{ + build xpacd__PACpart; +} + +# C6.2.401 XPACD, XPACI, XPACLRI page C6-2009 line 117573 MATCH xdac143e0/mask=xfffffbe0 +# CONSTRUCT xdac143e0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES +# AUNIT --inst xdac143e0/mask=xffffffe0 --status noqemu +# D == 0 XPACI variant + +:xpaci Rd_GPR64 +is xpaci__PACpart & b_1131=0b110110101100000101000 & b_0509=0b11111 & b_10=0 & Rd_GPR64 +{ + build xpaci__PACpart; +} + +# C6.2.401 XPACD, XPACI, XPACLRI page C6-2009 line 117573 MATCH xd50320ff/mask=xffffffff +# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f +# CONSTRUCT xd50320ff/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd50320ff/mask=xffffffff --status nodest +# System variant + +:xpaclri +is xpaclri__PACpart & b_0031=0b11010101000000110010000011111111 +{ + build xpaclri__PACpart; +} + +# C6.2.402 YIELD page C6-2011 line 117656 MATCH xd503203f/mask=xffffffff +# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f +# CONSTRUCT xd503203f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES +# AUNIT --inst xd503203f/mask=xffffffff --status nodest + +:yield +is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low=1 & Rt=0x1f +{ + Yield(); +} + +# C6.2.6 ADDG page C6-787 line 46877 MATCH KEEPWITH + +with : ShowMemTag=1 { + +# C6.2.6 ADDG page C6-1155 line 68448 MATCH x91800000/mask=xffc00000 +# CONSTRUCT x91800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES + +:addg Rd_GPR64xsp, Rn_GPR64xsp, "#"^shifted_imm, "#"^b_1013 +is sf=1 & op=0 & S=0 & b_2328=0b100011 & b_22=0 & b_1621 & b_1013 & Rd_GPR64xsp & Rn_GPR64xsp +# " & b_1415=0" is not required by the spec (op3 doesn't have any requirements and is not used) +[ shifted_imm = b_1621 << $(LOG2_TAG_GRANULE); ] +{ + # we don't actually modify the target register, so Ghidra understands the pointer target is still the same. + # pseudo-ops let us do that, but it means that the decompiler can put an unintuitive value in the + # "CopyPtrTag_AddToPtrTag_Exclude" argument, e.g. "param_2 + 0x20". + uimm4:1 = b_1013; + exclude:2 = 0; + Or2BytesWithExcludedTags(exclude); + Rd_GPR64xsp = Rn_GPR64xsp + shifted_imm; + CopyPtrTag_AddToPtrTag_Exclude(Rd_GPR64xsp, Rn_GPR64xsp, uimm4, exclude); +} + +} + +# C6.2.6 ADDG page C6-787 line 44223 KEEPWITH +with : ShowMemTag=0 { + +# C6.2.6 ADDG page C6-1155 line 68448 MATCH x91800000/mask=xffc00000 +# CONSTRUCT x91800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES + +:addg Rd_GPR64xsp, Rn_GPR64xsp, "#"^shifted_imm, "#"^b_1013 +is sf=1 & op=0 & S=0 & b_2328=0b100011 & b_22=0 & b_1621 & b_1013 & Rd_GPR64xsp & Rn_GPR64xsp +# " & b_1415=0" is not required by the spec (op3 doesn't have any requirements and is not used) +[ shifted_imm = b_1621 << $(LOG2_TAG_GRANULE); ] +{ + Rd_GPR64xsp = Rn_GPR64xsp + shifted_imm; +} + +} + + +# C6.2.24 AXFLAG page C6-1189 line 70222 MATCH xd500405f/mask=xfffff0ff +# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f +# CONSTRUCT xd500405f/mask=xfffff0ff MATCHED 2 DOCUMENTED OPCODES +# To enforce SHOULD BE ZERO fields add: b_0811=0b0000 +:axflag +is b_1231=0b11010101000000000100 & b_0007=0b01011111 +{ + tmpZR = ZR | OV; + tmpCY = CY & !OV; + + NG = 0; + ZR = tmpZR; + CY = tmpCY; + OV = 0; +} + +# C6.2.41 BTI page C6-1214 line 71457 MATCH xd503241f/mask=xffffff3f +# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f +# CONSTRUCT xd503241f/mask=xffffff1f MATCHED 2 DOCUMENTED OPCODES + +:bti BTI_BTITARGETS +is BTI_BTITARGETS & b_1231=0xd5032 & b_0811=4 & b_0004=0x1f +{ + # This instruction is a valid target for jumps, calls, or both; see the BTI_BTITARGETS table. +} + +# C6.2.53 CFP page C6-1237 line 72667 MATCH xd50b7380/mask=xffffffe0 +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50b7380/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES + +:cfp "RCTX", Rt_GPR64 +is b_1931=0b1101010100001 & Op1_uimm3=3 & b_1215=7 & b_0811=3 & Op2_uimm3=4 & Rt_GPR64 +{ + ControlFlowPredictionRestrictionByContext(Rt_GPR64); +} + + +# C6.2.65 CMPP page C6-1258 line 73720 MATCH xbac0001f/mask=xffe0fc1f +# C6.2.361 SUBPS page C6-1949 line 114470 MATCH xbac00000/mask=xffe0fc00 +# CONSTRUCT xbac0001f/mask=xffe0fc1f MATCHED 2 DOCUMENTED OPCODES +# CMPP: Compare Pointers +# Compare two pointer 56-bit pointer values and set flags +:cmpp Rn_GPR64xsp, Rm_GPR64xsp +is sf=1 & b_30=0 & S=1 & b_2128=0b11010110 & Rm_GPR64xsp & b_1015=0b000000 & Rd=0b11111 & Rn_GPR64xsp +{ + # out of a 64-bit value, keep the lowest 56 bits, which is 7 bytes. + # sign-extend a 7-byte value to an 8-byte value. If the boundary weren't byte-aligned, + # sext() wouldn't work so well. + tmp_2:8 = Rm_GPR64xsp; + tmp_2 = sext(tmp_2:7); # if Rm:7 is used here, the decompiler considers the Rm register an int7 for the whole function. + tmp_1:8 = Rn_GPR64xsp; + tmp_1 = sext(tmp_1:7); + subflags(tmp_1, tmp_2); + tmp_1 = tmp_1 - tmp_2; + resultflags(tmp_1); + affectflags(); +} + + +# C6.2.67 CPP page C6-1261 line 73861 MATCH xd50b73e0/mask=xffffffe0 +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50b73e0/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES + +:cpp "RCTX", Rt_GPR64 +is b_1931=0b1101010100001 & Op1_uimm3=3 & b_1215=7 & b_0811=3 & Op2_uimm3=7 & Rt_GPR64 +{ + CachePrefetchPredictionRestrictionByContext(Rt_GPR64); +} + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5087660/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES +# the new DC instruction types from ARMv8.5 + +:dc "IGVAC", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b0110 & b_0507=0b011 & Rt_GPR64 +{ DC_IGVAC(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5087680/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES + +:dc "IGSW", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b0110 & b_0507=0b100 & Rt_GPR64 +{ DC_IGSW(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50876a0/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES + +:dc "IGDVAC", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b0110 & b_0507=0b101 & Rt_GPR64 +{ DC_IGDVAC(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50876c0/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES + +:dc "IGDSW", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b0110 & b_0507=0b110 & Rt_GPR64 +{ DC_IGDSW(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5087a80/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES + +:dc "CGSW", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1010 & b_0507=0b100 & Rt_GPR64 +{ DC_CGSW(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5087ac0/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES + +:dc "CGDSW", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1010 & b_0507=0b110 & Rt_GPR64 +{ DC_CGDSW(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5087e80/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES + +:dc "CIGSW", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1110 & b_0507=0b100 & Rt_GPR64 +{ DC_CIGSW(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd5087ec0/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES + +:dc "CIGDSW", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1110 & b_0507=0b110 & Rt_GPR64 +{ DC_CIGDSW(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50b7460/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES + +:dc "GVA", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b0100 & b_0507=0b011 & Rt_GPR64 +{ DC_GVA(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50b7480/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES + +:dc "GZVA", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b0100 & b_0507=0b100 & Rt_GPR64 +{ DC_GZVA(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50b7a60/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES + +:dc "CGVAC", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1010 & b_0507=0b011 & Rt_GPR64 +{ DC_CGVAC(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50b7aa0/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES + +:dc "CGDVAC", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1010 & b_0507=0b101 & Rt_GPR64 +{ DC_CGDVAC(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50b7c60/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES + +:dc "CGVAP", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1100 & b_0507=0b011 & Rt_GPR64 +{ DC_CGVAP(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50b7ca0/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES + +:dc "CGDVAP", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1100 & b_0507=0b101 & Rt_GPR64 +{ DC_CGDVAP(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50b7d60/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES + +:dc "CGVADP", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1101 & b_0507=0b011 & Rt_GPR64 +{ DC_CGVADP(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50b7da0/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES + +:dc "CGDVADP", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1101 & b_0507=0b101 & Rt_GPR64 +{ DC_CGDVADP(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50b7e60/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES + +:dc "CIGVAC", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1110 & b_0507=0b011 & Rt_GPR64 +{ DC_CIGVAC(Rt_GPR64); } + +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50b7ea0/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES + +:dc "CIGDVAC", Rt_GPR64 +is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1110 & b_0507=0b101 & Rt_GPR64 +{ DC_CIGDVAC(Rt_GPR64); } + +# C6.2.117 DVP page C6-1467 line 87355 MATCH xd50b73a0/mask=xffffffe0 +# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000 +# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000 +# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000 +# CONSTRUCT xd50b73a0/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES + +:dvp "RCTX", Rt_GPR64 +is b_1931=0b1101010100001 & Op1_uimm3=3 & b_1215=7 & b_0811=3 & Op2_uimm3=5 & Rt_GPR64 +{ + DataValuePredictionRestrictionByContext(Rt_GPR64); +} + + +# GMI: Tag Mask Insert +# Extracts tag from first source register (Xn) and adds as an excluded tag to list of excluded +# tags in second source register, writing the updated exclusion set to the destination register + +with : ShowMemTag=1 { + +# C6.2.125 GMI page C6-1479 line 87976 MATCH x9ac01400/mask=xffe0fc00 +# CONSTRUCT x9ac01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES + +:gmi Rd_GPR64, Rn_GPR64xsp, Rm_GPR64 +is sf=1 & b_30=0 & S=0 & b_2128=0b11010110 & Rm_GPR64 & b_1015=0b000101 & Rn_GPR64xsp & Rd_GPR64 +{ + # get tag from address + #tag:8 = (Rn_GPR64xsp >> 56) & 0xf; + tag:8 = 0; + AllocationTagFromAddress(tag, Rn_GPR64xsp); + Rd_GPR64 = Rm_GPR64 | (1 << tag); +} + +} +with : ShowMemTag=0 { + +# C6.2.125 GMI page C6-1479 line 87976 MATCH x9ac01400/mask=xffe0fc00 +# CONSTRUCT x9ac01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES + +:gmi Rd_GPR64, Rn_GPR64xsp, Rm_GPR64 +is sf=1 & b_30=0 & S=0 & b_2128=0b11010110 & Rm_GPR64 & b_1015=0b000101 & Rn_GPR64xsp & Rd_GPR64 +{ + # The only expected use of the output of this instruction is in "exclude" arguments, which will be totally ignored + # with ShowMemTag off anyway, so for the sake of more concise code don't set any mask bits at all. + Rd_GPR64 = Rm_GPR64; +} + +} + +# IRG: Insert Random Tag +# Generates random tag (honoring excluded tags specified in optional second source register +# and GCR_EL1.Exclude) into the address from first source register, writing the result to the +# destination register. +with : ShowMemTag=1 { + +# C6.2.130 IRG page C6-1485 line 88340 MATCH x9ac01000/mask=xffe0fc00 +# CONSTRUCT x9ac01000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES + +:irg Rd_GPR64xsp, Rn_GPR64xsp^OPTIONAL_XM +is sf=1 & b_30=0 & S=0 & b_2128=0b11010110 & OPTIONAL_XM & b_1015=0b000100 & Rn_GPR64xsp & Rd_GPR64xsp +{ + tmp:8 = OPTIONAL_XM; + exclude:2 = tmp:2; + Or2BytesWithExcludedTags(exclude); + Rd_GPR64xsp = Rn_GPR64xsp; + RandomizePtrTag_Exclude(Rd_GPR64xsp, exclude); +} + +} +with : ShowMemTag=0 { + +# C6.2.130 IRG page C6-1485 line 88340 MATCH x9ac01000/mask=xffe0fc00 +# CONSTRUCT x9ac01000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES + +:irg Rd_GPR64xsp, Rn_GPR64xsp^OPTIONAL_XM +is sf=1 & b_30=0 & S=0 & b_2128=0b11010110 & OPTIONAL_XM & b_1015=0b000100 & Rn_GPR64xsp & Rd_GPR64xsp +{ + Rd_GPR64xsp = Rn_GPR64xsp; +} + +} + + +with : ShowMemTag=1 { + +# C6.2.158 LDG page C6-1538 line 91337 MATCH xd9600000/mask=xffe00c00 +# CONSTRUCT xd9600000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES + +:ldg Rt_GPR64, addr_granuleSIMM +is b_2131=0b11011001011 & addr_granuleSIMM & b_1011=0b00 & Rt_GPR64 +{ + tmp:8 = addr_granuleSIMM; + Align(tmp, $(TAG_GRANULE)); + tag:8 = LoadMemTag(tmp); + SetPtrTag(Rt_GPR64, tag); +} + +} +with : ShowMemTag=0 { + +# C6.2.158 LDG page C6-1538 line 91337 MATCH xd9600000/mask=xffe00c00 +# CONSTRUCT xd9600000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES + +:ldg Rt_GPR64, addr_granuleSIMM +is b_2131=0b11011001011 & addr_granuleSIMM & b_1011=0b00 & Rt_GPR64 +{ +} + +} + + +with : ShowMemTag=1 { + +# C6.2.159 LDGM page C6-1539 line 91400 MATCH xd9e00000/mask=xfffffc00 +# CONSTRUCT xd9e00000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES + +:ldgm Rt_GPR64, "["^Rn_GPR64xsp^"]" +is b_1031=0b1101100111100000000000 & Rt_GPR64 & Rn_GPR64xsp +{ + sze:8 = 4 << (gmid_el1 & 0xf); # The value in parentheses (GMID_EL1.BS) varies between 2 and 6. + address:8 = Rn_GPR64xsp; + Align(address, sze); # this ensures that address will be granule-aligned, so we don't need to check it + count:8 = sze >> $(LOG2_TAG_GRANULE); + data:8 = 0:8; # output value + index:8 = (address >> $(LOG2_TAG_GRANULE)) & 0xf; + # for tmp = 0 to count-1 + tmp:8 = 0; + + tag:8 = LoadMemTag(address) & 0xf; + # The 0xf doesn't do anything to streamline the representation of this + # instruction in the decompiler, but it shows the size of a tag. + data = data | (tag << (index * 4)); + address = address + $(TAG_GRANULE); + index = index + 1; + tmp = tmp + 1; + # next tmp + if (tmp < count) goto ; + Rt_GPR64 = data; +} + +} +with : ShowMemTag=0 { + +# C6.2.159 LDGM page C6-1539 line 91400 MATCH xd9e00000/mask=xfffffc00 +# CONSTRUCT xd9e00000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES + +:ldgm Rt_GPR64, "["^Rn_GPR64xsp^"]" +is b_1031=0b1101100111100000000000 & Rt_GPR64 & Rn_GPR64xsp +{ + data:8 = 0:8; # output value + Rt_GPR64 = data; +} + +} + +# C6.2.132 LD64B page C6-1488 line 88475 MATCH xf83fd000/mask=xfffffc00 +# CONSTRUCT xf83fd000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# xf83fd000/mask=xfffffc00 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=1111100000111111110100.......... + +# Single-copy Atomic 64-byte Load +:ld64b Rn_GPR64, [Rt_GPR64xsp] +is b_1031=0x3e0ff4 & Rn_GPR64 & Rt_GPR64xsp { + Rn_GPR64 = *Rt_GPR64xsp; +} + + +# C6.2.292 ST64B page C6-1813 line 107121 MATCH xf83f9000/mask=xfffffc00 +# CONSTRUCT xf83f9000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES + +:st64b Rn_GPR64, [Rt_GPR64xsp] +is b_1031=0x3e0fe4 & Rn_GPR64 & Rt_GPR64xsp { + *Rt_GPR64xsp = Rn_GPR64; +} + + +# C6.2.293 ST64BV page C6-1814 line 107190 MATCH xf820b000/mask=xffe0fc00 +# CONSTRUCT xf820b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +define pcodeop store64ByteAtomic; +:st64bv Rs_GPR64, Rn_GPR64, [Rt_GPR64xsp] +is b_2131=0x7c1 & Rs_GPR64 & b_1015=0x2c & Rn_GPR64 & Rt_GPR64xsp { + *Rt_GPR64xsp = Rn_GPR64; + Rs_GPR64 = store64ByteAtomic(Rn_GPR64, Rt_GPR64xsp); +} + + +# C6.2.294 ST64BV0 page C6-1816 line 107284 MATCH xf820a000/mask=xffe0fc00 +# CONSTRUCT xf820a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES + +:st64bv0 +is b_2131=0b11111000001 & Rs_GPR64 & b_1015=0x28 & Rn_GPR64 & Rt_GPR64xsp { + local st64bv_addr:8 = (Rt_GPR64xsp & 0xffff0000) | (accdata & 0xffff); + *st64bv_addr = Rn_GPR64; + Rs_GPR64 = store64ByteAtomic(Rn_GPR64, st64bv_addr); +} + + +addrGranuleIndexed_checkAlignment: addrGranuleIndexed is Rn=0b11111 & addrGranuleIndexed { export addrGranuleIndexed; } # don't check alignment if we're working with the stack, it's assumed to be 16-byte-aligned, though that is technically optional +addrGranuleIndexed_checkAlignment: addrGranuleIndexed is Rn & addrGranuleIndexed { tmp:8 = addrGranuleIndexed; RequireGranuleAlignment(tmp); export tmp; } # if the address in tmp is derived from sp, the error condition in RequireGranuleAlignment can still be an unreachable block; it doesn't seem possible to avoid the decompiler message in that case + +addrPairGranuleIndexed_checkAlignment: addrPairGranuleIndexed is Rn=0b11111 & addrPairGranuleIndexed { export addrPairGranuleIndexed; } # don't check alignment if we're working with the stack, it's assumed to be 16-byte-aligned, though that is technically optional +addrPairGranuleIndexed_checkAlignment: addrPairGranuleIndexed is Rn & addrPairGranuleIndexed { tmp:8 = addrPairGranuleIndexed; RequireGranuleAlignment(tmp); export tmp; } # if the address in tmp is derived from sp, the error condition in RequireGranuleAlignment can still be an unreachable block; it doesn't seem possible to avoid the decompiler message in that case + + +with : ShowMemTag=1 { + +# C6.2.291 ST2G page C6-1811 line 106987 MATCH xd9a00400/mask=xffe00c00 +# C6.2.291 ST2G page C6-1811 line 106987 MATCH xd9a00c00/mask=xffe00c00 +# C6.2.291 ST2G page C6-1811 line 106987 MATCH xd9a00800/mask=xffe00c00 +# CONSTRUCT xd9a00000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES + +:st2g Rt_GPR64xsp, addrGranuleIndexed_checkAlignment +is b_2131=0b11011001101 & (b_10=1 | b_11=1) & Rt_GPR64xsp & addrGranuleIndexed_checkAlignment +{ + # in case Rt == Rn, get the tag first so any updates in addrGranuleIndexed_checkAlignment don't affect it + tag:8 = 0; + AllocationTagFromAddress(tag, Rt_GPR64xsp); + + build addrGranuleIndexed_checkAlignment; + + # this instruction throws an alignment fault if address is not granule-aligned + address:8 = addrGranuleIndexed_checkAlignment; + + StoreMemTag(address, tag ); + StoreMemTag(address + $(TAG_GRANULE), tag ); +} + +} +with : ShowMemTag=0 { + +# C6.2.291 ST2G page C6-1811 line 106987 MATCH xd9a00400/mask=xffe00c00 +# C6.2.291 ST2G page C6-1811 line 106987 MATCH xd9a00c00/mask=xffe00c00 +# C6.2.291 ST2G page C6-1811 line 106987 MATCH xd9a00800/mask=xffe00c00 +# CONSTRUCT xd9a00000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES + +:st2g Rt_GPR64xsp, addrGranuleIndexed +is b_2131=0b11011001101 & (b_10=1 | b_11=1) & Rt_GPR64xsp & addrGranuleIndexed +{ + # for the sake of simplified output, omit the alignment check when ShowMemTag is off +} + +} + + +with : ShowMemTag=1 { + +# C6.2.304 STG page C6-1836 line 108242 MATCH xd9200400/mask=xffe00c00 +# C6.2.304 STG page C6-1836 line 108242 MATCH xd9200c00/mask=xffe00c00 +# C6.2.304 STG page C6-1836 line 108242 MATCH xd9200800/mask=xffe00c00 +# CONSTRUCT xd9200000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES + +:stg Rt_GPR64xsp, addrGranuleIndexed_checkAlignment +is b_2131=0b11011001001 & (b_10=1 | b_11=1) & Rt_GPR64xsp & addrGranuleIndexed_checkAlignment +{ + # in case Rt == Rn, get the tag first so any updates in addrGranuleIndexed_checkAlignment don't affect it + tag:8 = 0; + AllocationTagFromAddress(tag, Rt_GPR64xsp); + + build addrGranuleIndexed_checkAlignment; + + # this instruction throws an alignment fault if address is not granule-aligned + address:8 = addrGranuleIndexed_checkAlignment; + + StoreMemTag(address, tag ); +} + +} +with : ShowMemTag=0 { + +# C6.2.304 STG page C6-1836 line 108242 MATCH xd9200400/mask=xffe00c00 +# C6.2.304 STG page C6-1836 line 108242 MATCH xd9200c00/mask=xffe00c00 +# C6.2.304 STG page C6-1836 line 108242 MATCH xd9200800/mask=xffe00c00 +# CONSTRUCT xd9200000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES + +:stg Rt_GPR64xsp, addrGranuleIndexed +is b_2131=0b11011001001 & (b_10=1 | b_11=1) & Rt_GPR64xsp & addrGranuleIndexed +{ + # for the sake of simplified output, omit the alignment check when ShowMemTag is off +} + +} + + +with : ShowMemTag=1 { + +# C6.2.305 STGM page C6-1838 line 108375 MATCH xd9a00000/mask=xfffffc00 +# CONSTRUCT xd9a00000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES + +:stgm Rt_GPR64, "["^Rn_GPR64xsp^"]" +is b_1031=0b1101100110100000000000 & Rt_GPR64 & Rn_GPR64xsp +{ + sze:8 = 4 << (gmid_el1 & 0xf); # The value of GMID_EL1.BS varies between 2 and 6. Can that be asserted somehow? + address:8 = Rn_GPR64xsp; + Align(address, sze); # this ensures that address will be granule-aligned, so we don't need to check it + count:8 = sze >> $(LOG2_TAG_GRANULE); + data:8 = Rt_GPR64; + index:8 = (address >> $(LOG2_TAG_GRANULE)) & 0xf; + # for tmp = 0 to count-1 + tmp:8 = 0; + + # This could also be done by leaving index and address constant and adding a tmp-based + # offset to them both, but that crams everything together into the StoreMemTag line in + # the decompiler and makes it harder to assign names and figure out what's going on. + # (Or at least, my opinion is that it's harder that way.) + # Also in favor of this design is that the ARM spec pseudocode describes it this way, + # so it's easier to see that this code matches the pseudocode. + tag:8 = (data >> (index * 4)) & 0xf; + StoreMemTag(address, tag ); + address = address + $(TAG_GRANULE); + index = index + 1; + tmp = tmp + 1; + # next tmp + if (tmp < count) goto ; +} + +} +with : ShowMemTag=0 { + +# C6.2.305 STGM page C6-1838 line 108375 MATCH xd9a00000/mask=xfffffc00 +# CONSTRUCT xd9a00000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES + +:stgm Rt_GPR64, "["^Rn_GPR64xsp^"]" +is b_1031=0b1101100110100000000000 & Rt_GPR64 & Rn_GPR64xsp +{ +} + +} + + +with : ShowMemTag=1 { + +# C6.2.306 STGP page C6-1839 line 108445 MATCH x68800000/mask=xffc00000 +# C6.2.306 STGP page C6-1839 line 108445 MATCH x69800000/mask=xffc00000 +# C6.2.306 STGP page C6-1839 line 108445 MATCH x69000000/mask=xffc00000 +# CONSTRUCT x68000000/mask=xfe400000 MATCHED 3 DOCUMENTED OPCODES + +:stgp Rt_GPR64, Rt2_GPR64, addrPairGranuleIndexed_checkAlignment +is b_3031=0b01 & b_2529=0b10100 & (b_23=1 | b_24=1) & b_22=0 & Rt2_GPR64 & addrPairGranuleIndexed_checkAlignment & Rt_GPR64 +{ + # Read all registers before addrPairGranuleIndexed_checkAlignment takes effect, or pre-index writeback could modify their values + # (unusually, this instruction does not have unpredictable behavior in that case). + data1:8 = Rt_GPR64; + data2:8 = Rt2_GPR64; + + build addrPairGranuleIndexed_checkAlignment; + address:8 = addrPairGranuleIndexed_checkAlignment; # StoreMemTag requires granule alignment + + tag:8 = 0; + AllocationTagFromAddress(tag, address); + + # The decompiler apparently doesn't show changes to [sp+X] unless the new values + # are used in the function. However, the changes really are happening. + *address = data1; + *(address + 8) = data2; + StoreMemTag(address, tag); +} + +} +with : ShowMemTag=0 { + +# C6.2.306 STGP page C6-1839 line 108445 MATCH x68800000/mask=xffc00000 +# C6.2.306 STGP page C6-1839 line 108445 MATCH x69800000/mask=xffc00000 +# C6.2.306 STGP page C6-1839 line 108445 MATCH x69000000/mask=xffc00000 +# CONSTRUCT x68000000/mask=xfe400000 MATCHED 3 DOCUMENTED OPCODES + +:stgp Rt_GPR64, Rt2_GPR64, addrPairGranuleIndexed +is b_3031=0b01 & b_2529=0b10100 & (b_23=1 | b_24=1) & b_22=0 & Rt2_GPR64 & addrPairGranuleIndexed & Rt_GPR64 +{ + # Read all registers before addrPairGranuleIndexed takes effect, or pre-index writeback could modify their values + # (unusually, this instruction does not have unpredictable behavior in this case). + data1:8 = Rt_GPR64; + data2:8 = Rt2_GPR64; + + # for the sake of simplified output, omit the alignment check when ShowMemTag is off + build addrPairGranuleIndexed; + address:8 = addrPairGranuleIndexed; + + # The decompiler apparently doesn't show changes to [sp+X] unless the new values + # are used in the function. However, the changes really are happening. + *address = data1; + *(address + 8) = data2; +} + +} + + +with : ShowMemTag=1 { + +# C6.2.353 STZ2G page C6-1935 line 113626 MATCH xd9e00400/mask=xffe00c00 +# C6.2.353 STZ2G page C6-1935 line 113626 MATCH xd9e00c00/mask=xffe00c00 +# C6.2.353 STZ2G page C6-1935 line 113626 MATCH xd9e00800/mask=xffe00c00 +# CONSTRUCT xd9e00000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES + +:stz2g Rt_GPR64xsp, addrGranuleIndexed_checkAlignment +is b_2131=0b11011001111 & (b_10=1 | b_11=1) & addrGranuleIndexed_checkAlignment & Rt_GPR64xsp +{ + tag:8 = 0; + AllocationTagFromAddress(tag, Rt_GPR64xsp); + + # Although the zero-storage is not required to be granule-aligned, the tag-updating is, + # so effectively the entire operation must be at a granule-aligned address. + build addrGranuleIndexed_checkAlignment; + address:8 = addrGranuleIndexed_checkAlignment; + + # store two granules worth of zeros and tag it from Rt + tmp:8 = 0; + addr:8 = 0; + count:8 = $(TAG_GRANULE) * 2; + + addr = address + tmp; + *addr = 0:8; + tmp = tmp + 8; + if (tmp < count) goto ; + + StoreMemTag(address, tag); + StoreMemTag(address + $(TAG_GRANULE), tag); +} + +} +with : ShowMemTag=0 { + +# C6.2.353 STZ2G page C6-1935 line 113626 MATCH xd9e00400/mask=xffe00c00 +# C6.2.353 STZ2G page C6-1935 line 113626 MATCH xd9e00c00/mask=xffe00c00 +# C6.2.353 STZ2G page C6-1935 line 113626 MATCH xd9e00800/mask=xffe00c00 +# CONSTRUCT xd9e00000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES + +:stz2g Rt_GPR64xsp, addrGranuleIndexed +is b_2131=0b11011001111 & (b_10=1 | b_11=1) & addrGranuleIndexed & Rt_GPR64xsp +{ + # for the sake of simplified output, omit the alignment check when ShowMemTag is off + build addrGranuleIndexed; + address:8 = addrGranuleIndexed; + + # store two granules worth of zeros + tmp:8 = 0; + addr:8 = 0; + count:8 = $(TAG_GRANULE) * 2; + + addr = address + tmp; + *addr = 0:8; + tmp = tmp + 8; + if (tmp < count) goto ; +} + +} + + +with : ShowMemTag=1 { + +# C6.2.354 STZG page C6-1937 line 113766 MATCH xd9600400/mask=xffe00c00 +# C6.2.354 STZG page C6-1937 line 113766 MATCH xd9600c00/mask=xffe00c00 +# C6.2.354 STZG page C6-1937 line 113766 MATCH xd9600800/mask=xffe00c00 +# CONSTRUCT xd9600000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES + +:stzg Rt_GPR64xsp, addrGranuleIndexed_checkAlignment +is b_2131=0b11011001011 & (b_10=1 | b_11=1) & addrGranuleIndexed_checkAlignment & Rt_GPR64xsp +{ + tag:8 = 0; + AllocationTagFromAddress(tag, Rt_GPR64xsp); + + # Although the zero-storage is not required to be granule-aligned, the tag-updating is, + # so effectively the entire operation must be at a granule-aligned address. + build addrGranuleIndexed_checkAlignment; + address:8 = addrGranuleIndexed_checkAlignment; + + # store one granule worth of zeros and tag it from Rt + tmp:8 = 0; + addr:8 = 0; + count:8 = $(TAG_GRANULE); + + addr = address + tmp; + *addr = 0:8; + tmp = tmp + 8; + if (tmp < count) goto ; + + StoreMemTag(address, tag); +} + +} +with : ShowMemTag=0 { + +# C6.2.354 STZG page C6-1937 line 113766 MATCH xd9600400/mask=xffe00c00 +# C6.2.354 STZG page C6-1937 line 113766 MATCH xd9600c00/mask=xffe00c00 +# C6.2.354 STZG page C6-1937 line 113766 MATCH xd9600800/mask=xffe00c00 +# CONSTRUCT xd9600000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES + +:stzg Rt_GPR64xsp, addrGranuleIndexed +is b_2131=0b11011001011 & (b_10=1 | b_11=1) & addrGranuleIndexed & Rt_GPR64xsp +{ + # for the sake of simplified output, omit the alignment check when ShowMemTag is off + build addrGranuleIndexed; + address:8 = addrGranuleIndexed; + + # store one granule worth of zeros + tmp:8 = 0; + addr:8 = 0; + count:8 = $(TAG_GRANULE); + + addr = address + tmp; + *addr = 0:8; + tmp = tmp + 8; + if (tmp < count) goto ; +} + +} + + + +with : ShowMemTag=1 { + +# C6.2.355 STZGM page C6-1939 line 113904 MATCH xd9200000/mask=xfffffc00 +# CONSTRUCT xd9200000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES + +:stzgm Rt_GPR64, "["^Rn_GPR64xsp^"]" +is b_1031=0b1101100100100000000000 & Rt_GPR64 & Rn_GPR64xsp +{ + sze:8 = 4 << (dczid_el0 & 0xf); # the last value (DCZID_EL0.BS) can be up to 9 (for a size of 2KB) and seems + # to be hardware-dependent and unwriteable (sysreg spec doesn't show how to write it). + # minimum is probably 2, which would make the size equal to a tag granule + address:8 = Rn_GPR64xsp; + Align(address, sze); # based on the educated guess above, address is probably granule-aligned by this, so we won't check it explicitly (compare to LDGM or STGM) + count:8 = sze >> $(LOG2_TAG_GRANULE); + data:8 = Rt_GPR64; + tag:8 = data & 0xf; + # for tmp = 0 to count-1 + tmp:8 = 0; + + StoreMemTag(address, tag ); + + # store zeros to the entire granule + tmp_zero:8 = 0; + addr_zero:8 = address; + count_zero:8 = $(TAG_GRANULE); + + addr_zero = address + tmp_zero; + *addr_zero = 0:8; + tmp_zero = tmp_zero + 8; + if (tmp_zero < count_zero) goto ; + + address = address + $(TAG_GRANULE); + # next tmp + tmp = tmp + 1; + if (tmp < count) goto ; +} + +} +with : ShowMemTag=0 { + +# C6.2.355 STZGM page C6-1939 line 113904 MATCH xd9200000/mask=xfffffc00 +# CONSTRUCT xd9200000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES + +:stzgm Rt_GPR64, "["^Rn_GPR64xsp^"]" +is b_1031=0b1101100100100000000000 & Rt_GPR64 & Rn_GPR64xsp +{ + sze:8 = 4 << (dczid_el0 & 0xf); # the last value (DCZID_EL0.BS) can be up to 9 (for a size of 2KB) and seems + # to be hardware-dependent and unwriteable (sysreg spec doesn't show how to write it). + # minimum is probably 2, which would make the size equal to a tag granule + address:8 = Rn_GPR64xsp; + Align(address, sze); # based on the educated guess above, address is probably granule-aligned by this, so we won't check it explicitly (compare to LDGM or STGM) + count:8 = sze >> $(LOG2_TAG_GRANULE); + # for tmp = 0 to count-1 + tmp:8 = 0; + + + # store zeros to the entire granule + tmp_zero:8 = 0; + addr_zero:8 = address; + count_zero:8 = $(TAG_GRANULE); + + addr_zero = address + tmp_zero; + *addr_zero = 0:8; + tmp_zero = tmp_zero + 8; + if (tmp_zero < count_zero) goto ; + + address = address + $(TAG_GRANULE); + # next tmp + tmp = tmp + 1; + if (tmp < count) goto ; +} + +} + + +# To enforce SHOULD BE ZERO fields add: b_1415=0b00 + +with : ShowMemTag=1 { + +# C6.2.359 SUBG page C6-1947 line 114340 MATCH xd1800000/mask=xffc00000 +# CONSTRUCT xd1800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES + +:subg Rd_GPR64xsp, Rn_GPR64xsp, "#"^shifted_imm, "#"^b_1013 +is sf=1 & op=1 & S=0 & b_2328=0b100011 & b_22=0 & b_1621 & b_1013 & Rd_GPR64xsp & Rn_GPR64xsp +# " & b_1415=0" is not required by the spec (op3 doesn't have any requirements and is not used) +[ shifted_imm = b_1621 << $(LOG2_TAG_GRANULE); ] +{ + # we don't actually modify the target register, so Ghidra understands the pointer target is still the same. + # pseudo-ops let us do that, but it means that the decompiler can put an unintuitive value in the + # "CopyPtrTag_AddToPtrTag_Exclude" argument, e.g. "param_2 - 0x20". + uimm4:1 = b_1013; + exclude:2 = 0; + Or2BytesWithExcludedTags(exclude); + Rd_GPR64xsp = Rn_GPR64xsp - shifted_imm; + CopyPtrTag_AddToPtrTag_Exclude(Rd_GPR64xsp, Rn_GPR64xsp, uimm4, exclude); +} + +} +with : ShowMemTag=0 { + +# C6.2.359 SUBG page C6-1947 line 114340 MATCH xd1800000/mask=xffc00000 +# CONSTRUCT xd1800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES + +:subg Rd_GPR64xsp, Rn_GPR64xsp, "#"^shifted_imm, "#"^b_1013 +is sf=1 & op=1 & S=0 & b_2328=0b100011 & b_22=0 & b_1621 & b_1013 & Rd_GPR64xsp & Rn_GPR64xsp +# " & b_1415=0" is not required by the spec (op3 doesn't have any requirements and is not used) +[ shifted_imm = b_1621 << $(LOG2_TAG_GRANULE); ] +{ + Rd_GPR64xsp = Rn_GPR64xsp - shifted_imm; +} + +} + + +# Subtract Pointer [setting Flags]: +# Subtract the 56-bit address held in the second operand from the first and store the result +# in the destination register. If the destination register is XZR, then just use as a side- +# effect of being a pointer comparison (CMPP). +# C6.2.360 SUBP page C6-1948 line 114410 MATCH x9ac00000/mask=xffe0fc00 +# C6.2.361 SUBPS page C6-1949 line 114470 MATCH xbac00000/mask=xffe0fc00 +# CONSTRUCT x9ac00000/mask=xdfe0fc00 MATCHED 2 DOCUMENTED OPCODES + +:subp^SBIT_CZNO Rd_GPR64, Rn_GPR64xsp, Rm_GPR64xsp +is sf=1 & b_30=0 & S & SBIT_CZNO & b_2128=0b11010110 & b_1015=0b000000 & Rd_GPR64 & Rn_GPR64xsp & Rm_GPR64xsp +{ + # out of a 64-bit value, keep the lowest 56 bits, which is 7 bytes. + # sign-extend a 7-byte value to an 8-byte value. If the boundary weren't byte-aligned, + # sext() wouldn't work so well. + tmp_2:8 = Rm_GPR64xsp; + tmp_2 = sext(tmp_2:7); # if Rm:7 is used here, the decompiler considers the Rm register an int7 for the whole function. + tmp_1:8 = Rn_GPR64xsp; + tmp_1 = sext(tmp_1:7); + subflags(tmp_1, tmp_2); + tmp_1 = tmp_1 - tmp_2; + resultflags(tmp_1); + Rd_GPR64 = tmp_1; + build SBIT_CZNO; +} + + +# C6.2.376 TCANCEL page C6-1974 line 115824 MATCH xd4600000/mask=xffe0001f +# CONSTRUCT xd4600000/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES + +define pcodeop cancelTransaction; +:tcancel "#"^imm16 +is b_2131=0x6a3 & imm16 & b_0519 & b_2020 & b_0004=0x0 { + local tmp:2 = imm16; + local reason:2 = b_0519; + local retry:1 = b_2020; + cancelTransaction(reason, retry); +} + + +# C6.2.377 TCOMMIT page C6-1975 line 115871 MATCH xd503307f/mask=xffffffff +# CONSTRUCT xd503307f/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES + +define pcodeop commitTransaction; +:tcommit +is b_0031=0xd503307f { + commitTransaction(); +} + + +# C6.2.379 TSTART page C6-1979 line 116075 + +define pcodeop transactionStart; +:tstart Rd_GPR64 +is b_0531=0x6a9193a & Rd_GPR64 { + transactionStart(Rd_GPR64); +} + + +# C6.2.380 TTEST page C6-1981 line 116175 + +define pcodeop transactionDepth; +:ttest Rd_GPR64 +is b_0531=0x6a9198b & Rd_GPR64 { + Rd_GPR64 = transactionDepth(); +} + + + +# C6.2.387 UDF page C6-1993 line 116744 MATCH x00000000/mask=xffff0000 +# CONSTRUCT x00000000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES +# Undefined instruction +:udf b_0015 +is b_1631=0b0000000000000000 & b_0015 +{ + local excaddr:8 = inst_start; + local id:2 = b_0015; + local target:8 = UndefinedInstructionException(id, excaddr); + goto [target]; +} + + +# C6.2.400 XAFLAG page C6-2008 line 117528 MATCH xd500403f/mask=xfffff0ff +# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f +# CONSTRUCT xd500403f/mask=xfffff0ff MATCHED 2 DOCUMENTED OPCODES + +:xaflag +is b_1231=0b11010101000000000100 & b_0007=0b00111111 +{ + tmpNG = !CY & !ZR; + tmpZR = ZR & CY; + tmpCY = CY | ZR; + tmpOV = !CY & ZR; + + NG = tmpNG; + ZR = tmpZR; + CY = tmpCY; + OV = tmpOV; +} + + diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64instructions.sinc b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64instructions.sinc new file mode 100644 index 0000000..c6bd81d --- /dev/null +++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64instructions.sinc @@ -0,0 +1,4006 @@ +# Specification for the AARCH64 64-bit ARM instruction set +# +# See "ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile" +# opcodes are always Little endian, although the data can be Big/Little Endian. + +# TODO Collapse SUB/SUBS forms +# TODO MSR/MRS's need to be specified with special registers, coproc +# TODO Many special case opcodes for UBFM and BFM, For example BFI + +# TODO? Floating point numbers don't display correctly as IEEE floats +# TODO? Many special case opcodes like + +# TODO When writing to 32-bit Rd32, the upper bits of the bigger 64-bit Rd64 are zero'ed +# Most pcode does this, but this needs to be carefully checked. There may be some +# that do not zero extend into Rd64, and some that do extend into Rd64 but shouldn't. +# If it's not done right (or naively) the decompiler gets confused. So +# the accepted pattern for doing this is: +# +# ... calculate and set destination register ... +# local tmps:SIZE = destination_register; +# big_register = zext(tmps); +# destination_register = big_register; + +# Note Implemented 2/2016 +# +# UBFM/SBFM/BFM is implemented +# +# When the destination is a 32-bit register, the upper 32 bits of the register must be set to 0. +# This includes the wsp stack pointer, which might clobber the upper part of an address. +# +# And when the destination is a Rd_VPR vector register but the operand size is less than 128 bits, +# and the destination is not the upper half of the register (ie, bit 30 q=0) +# then the unused remaining upper bits must be set to 0. + +@if DATA_ENDIAN == "little" +define endian=little; +@else +define endian=big; +@endif +define alignment=4; + +# Unlike the above, these are preprocessor macros. Use them with e.g. $(TAG_GRANULE) in SLEIGH statements. +@define LOG2_TAG_GRANULE "4" +@define TAG_GRANULE "16" + +# SECTION registers + +define space ram type=ram_space size=8 default; +define space register type=register_space size=4; + +# See "ABOUT THE ENDIAN IFDEFS" below for an explanation of the endian +# ifdefs + +@if DATA_ENDIAN == "little" +define register offset=0x0000 size=8 [ pc sp ]; +define register offset=0x0000 size=4 [ _ _ wsp _ ]; +@else +define register offset=0x0000 size=8 [ pc sp ]; +define register offset=0x0000 size=4 [ _ _ _ wsp ]; +@endif + +define register offset=0x0100 size=1 [ NG ZR CY OV shift_carry tmpCY tmpOV tmpNG tmpZR ]; + +define register offset=0x0200 size=4 [ glob_mask32 ]; +define register offset=0x0204 size=8 [ glob_mask64 ]; + +# address set to load/store a value from memory in/out of vectors +define register offset=0x0300 size=8 [ VecMemAddr VectorSelem ]; + +# register address to load/store a value from memory in/out of registers +define register offset=0x0310 size=4 [ VecRegAddr ]; + +# Special Purpose Registers - most of these are really 1 bit and part +# of a status register, however they all need to be consistent + +# 26 registers 0xd0 bytes + +define register offset=0x1000 size=8 +[ + spsr_el1 + elr_el1 + sp_el0 + spsel + daif + currentel + nzcv + fpcr + fpsr + dspsr_el0 + dlr_el0 + spsr_el2 + elr_el2 + sp_el1 + spsr_irq + spsr_abt + spsr_und + spsr_fiq + spsr_el3 + elr_el3 + sp_el2 + spsr_svc + spsr_hyp + uao + pan + tco + accdata +]; + +# System Registers + +# 202 registers 0x330 bytes +define register offset=0x1100 size=8 +[ + midr_el1 + mpidr_el1 + revidr_el1 + id_dfr0_el1 + id_pfr0_el1 + id_pfr1_el1 + id_afr0_el1 + id_mmfr0_el1 + id_mmfr1_el1 + id_mmfr2_el1 + id_mmfr3_el1 + id_isar0_el1 + id_isar1_el1 + id_isar2_el1 + id_isar3_el1 + id_isar4_el1 + id_isar5_el1 + mvfr0_el1 + mvfr1_el1 + mvfr2_el1 + ccsidr_el1 + id_aa64pfr0_el1 + id_aa64pfr1_el1 + id_aa64dfr0_el1 + id_aa64dfr1_el1 + id_aa64isar0_el1 + id_aa64isar1_el1 + id_aa64mmfr0_el1 + id_aa64mmfr1_el1 + id_aa64afr0_el1 + id_aa64afr1_el1 + clidr_el1 + aidr_el1 + csselr_el1 + ctr_el0 + dczid_el0 + vpidr_el2 + vmpidr_el2 + sctlr_el1 + actlr_el1 + cpacr_el1 + sctlr_el2 + actlr_el2 + hcr_el2 + mdcr_el2 + cptr_el2 + hstr_el2 + hacr_el2 + sctlr_el3 + actlr_el3 + scr_el3 + cptr_el3 + mdcr_el3 + ttbr0_el1 + ttbr1_el1 + ttbr0_el2 + ttbr0_el3 + vttbr_el2 + tcr_el1 + tcr_el2 + tcr_el3 + vtcr_el2 + afsr0_el1 + afsr1_el1 + afsr0_el2 + afsr1_el2 + afsr0_el3 + afsr1_el3 + esr_el1 + esr_el2 + esr_el3 + fpexc32_el2 + far_el1 + far_el2 + far_el3 + hpfar_el2 + par_el1 + pmintenset_el1 + pmintenclr_el1 + pmcr_el0 + pmcntenset_el0 + pmcntenclr_el0 + pmovsclr_el0 + pmswinc_el0 + pmselr_el0 + pmceid0_el0 + pmceid1_el0 + pmccntr_el0 + pmxevtyper_el0 + pmxevcntr_el0 + pmuserenr_el0 + pmovsset_el0 + pmevcntr0_el0 + pmevcntr1_el0 + pmevcntr2_el0 + pmevcntr3_el0 + pmevcntr4_el0 + pmevcntr5_el0 + pmevcntr6_el0 + pmevcntr7_el0 + pmevcntr8_el0 + pmevcntr9_el0 + pmevcntr10_el0 + pmevcntr11_el0 + pmevcntr12_el0 + pmevcntr13_el0 + pmevcntr14_el0 + pmevcntr15_el0 + pmevcntr16_el0 + pmevcntr17_el0 + pmevcntr18_el0 + pmevcntr19_el0 + pmevcntr20_el0 + pmevcntr21_el0 + pmevcntr22_el0 + pmevcntr23_el0 + pmevcntr24_el0 + pmevcntr25_el0 + pmevcntr26_el0 + pmevcntr27_el0 + pmevcntr28_el0 + pmevcntr29_el0 + pmevcntr30_el0 + pmevtyper0_el0 + pmevtyper1_el0 + pmevtyper2_el0 + pmevtyper3_el0 + pmevtyper4_el0 + pmevtyper5_el0 + pmevtyper6_el0 + pmevtyper7_el0 + pmevtyper8_el0 + pmevtyper9_el0 + pmevtyper10_el0 + pmevtyper11_el0 + pmevtyper12_el0 + pmevtyper13_el0 + pmevtyper14_el0 + pmevtyper15_el0 + pmevtyper16_el0 + pmevtyper17_el0 + pmevtyper18_el0 + pmevtyper19_el0 + pmevtyper20_el0 + pmevtyper21_el0 + pmevtyper22_el0 + pmevtyper23_el0 + pmevtyper24_el0 + pmevtyper25_el0 + pmevtyper26_el0 + pmevtyper27_el0 + pmevtyper28_el0 + pmevtyper29_el0 + pmevtyper30_el0 + pmccfiltr_el0 + mair_el1 + mair_el2 + mair_el3 + amair_el1 + amair_el2 + amair_el3 + vbar_el1 + vbar_el2 + vbar_el3 + rvbar_el1 + rvbar_el2 + rvbar_el3 + rmr_el1 + rmr_el2 + rmr_el3 + isr_el1 + contextidr_el1 + tpidr_el0 + tpidrro_el0 + tpidr_el1 + tpidr_el2 + tpidr_el3 + teecr32_el1 + cntfrq_el0 + cntpct_el0 + cntvct_el0 + cntvoff_el2 + cntkctl_el1 + cnthctl_el2 + cntp_tval_el0 + cntp_ctl_el0 + cntp_cval_el0 + cntv_tval_el0 + cntv_ctl_el0 + cntv_cval_el0 + cnthp_tval_el2 + cnthp_ctl_el2 + cnthp_cval_el2 + cntps_tval_el1 + cntps_ctl_el1 + cntps_cval_el1 + dacr32_el2 + ifsr32_el2 + teehbr32_el1 + sder32_el3 + gmid_el1 + gcr_el1 + ssbs + allint + dit + svcr +]; + +# bitrange definitions are [,] + +define bitrange gcr_el1.exclude=gcr_el1[0,16]; + +# Debug Registers +# 82 registers 0x290 bytes + +define register offset=0x1800 size=8 +[ + osdtrrx_el1 + mdccint_el1 + mdscr_el1 + osdtrtx_el1 + oseccr_el1 + dbgbvr0_el1 + dbgbvr1_el1 + dbgbvr2_el1 + dbgbvr3_el1 + dbgbvr4_el1 + dbgbvr5_el1 + dbgbvr6_el1 + dbgbvr7_el1 + dbgbvr8_el1 + dbgbvr9_el1 + dbgbvr10_el1 + dbgbvr11_el1 + dbgbvr12_el1 + dbgbvr13_el1 + dbgbvr14_el1 + dbgbvr15_el1 + dbgbcr0_el1 + dbgbcr1_el1 + dbgbcr2_el1 + dbgbcr3_el1 + dbgbcr4_el1 + dbgbcr5_el1 + dbgbcr6_el1 + dbgbcr7_el1 + dbgbcr8_el1 + dbgbcr9_el1 + dbgbcr10_el1 + dbgbcr11_el1 + dbgbcr12_el1 + dbgbcr13_el1 + dbgbcr14_el1 + dbgbcr15_el1 + dbgwvr0_el1 + dbgwvr1_el1 + dbgwvr2_el1 + dbgwvr3_el1 + dbgwvr4_el1 + dbgwvr5_el1 + dbgwvr6_el1 + dbgwvr7_el1 + dbgwvr8_el1 + dbgwvr9_el1 + dbgwvr10_el1 + dbgwvr11_el1 + dbgwvr12_el1 + dbgwvr13_el1 + dbgwvr14_el1 + dbgwvr15_el1 + dbgwcr0_el1 + dbgwcr1_el1 + dbgwcr2_el1 + dbgwcr3_el1 + dbgwcr4_el1 + dbgwcr5_el1 + dbgwcr6_el1 + dbgwcr7_el1 + dbgwcr8_el1 + dbgwcr9_el1 + dbgwcr10_el1 + dbgwcr11_el1 + dbgwcr12_el1 + dbgwcr13_el1 + dbgwcr14_el1 + dbgwcr15_el1 + mdrar_el1 + oslar_el1 + oslsr_el1 + osdlr_el1 + dbgprcr_el1 + dbgclaimset_el1 + dbgclaimclr_el1 + dbgauthstatus_el1 + mdccsr_el0 + dbgdtr_el0 + dbgdtrrx_el0 + dbgdtrtx_el0 + dbgvcr32_el2 +]; + +define register offset=0x3000 size=4 contextreg; + +# value loaded from memory to store in register +# or computed to store in memory +define register offset=0x3100 size=4 tmp_ldWn; +define register offset=0x3104 size=8 tmp_ldXn; +define register offset=0x310c size=4 tmp_stWn; +define register offset=0x3110 size=8 tmp_stXn; + +# General purpose and SIMD registers +# +# These will start at 0x3800 and there should be no defined registers +# after this address (this is because the size of the registers is +# potentially variable). +# +# ABOUT THE ENDIAN IFDEFS +# the *address* of the overlain registers depends on if the underlying +# memory is in big or little endian order. In little endian order, the +# LSB is byte 0, so (for example) w0 and x0 have the same address *in +# register memory*. But in big endian order, the LSB of x0 is byte 7, +# and so w0 starts at byte 4. All of that just gets at the address in +# register memory. Any time a value is loaded into a varnode and +# manipulated in sleigh code, it is always in big endian order. It is +# only byte reversed when read or written to little endian memory. All +# that means is that there are endian ifdefs for the overlain +# registers here, but that can and should be ignored when writing +# semantics. + +# General purpose registers R0-R30 (R31=zero register ZR) +# They are accessed as +# 64-bit register named X0-X30 +# 32-bit registers named W0-W30 + +define register offset=0x4000 size=8 +[ + x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 + x16 x17 x18 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28 x29 x30 xzr +]; + +@if DATA_ENDIAN == "little" +define register offset=0x4000 size=4 +[ + w0 _ + w1 _ + w2 _ + w3 _ + w4 _ + w5 _ + w6 _ + w7 _ + w8 _ + w9 _ + w10 _ + w11 _ + w12 _ + w13 _ + w14 _ + w15 _ + w16 _ + w17 _ + w18 _ + w19 _ + w20 _ + w21 _ + w22 _ + w23 _ + w24 _ + w25 _ + w26 _ + w27 _ + w28 _ + w29 _ + w30 _ + wzr _ +]; +@else +define register offset=0x4000 size=4 +[ + _ w0 + _ w1 + _ w2 + _ w3 + _ w4 + _ w5 + _ w6 + _ w7 + _ w8 + _ w9 + _ w10 + _ w11 + _ w12 + _ w13 + _ w14 + _ w15 + _ w16 + _ w17 + _ w18 + _ w19 + _ w20 + _ w21 + _ w22 + _ w23 + _ w24 + _ w25 + _ w26 + _ w27 + _ w28 + _ w29 + _ w30 + _ wzr +]; +@endif + +# SIMD&FP registers V0-V31 at 0x5000 +# They are accessed as: +# 128-bit registers named Q0-Q31 +# 64-bit registers named D0-D31 +# 32-bit registers named S0-S31 +# 16-bit registers named H0-H31 +# 8-bit registers named B0-B31 +# a 128-bit vector of elements +# a 64-bit vector of elements +# The packing is endian dependent +# For SVE, registers Z0-Z31 can be any size that is a multiple of 128 +# up to 2048 bits, and they overlap the V0-V31 registers + +# temporary SIMD registers, needed for calculations in SIMD semantics + +define register offset=0x4800 size=32 [ TMPZ1 TMPZ2 TMPZ3 TMPZ4 TMPZ5 TMPZ6 ]; + +@if DATA_ENDIAN == "little" + +define register offset=0x4800 size=16 +[ + TMPQ1 _ + TMPQ2 _ + TMPQ3 _ + TMPQ4 _ + TMPQ5 _ + TMPQ6 _ +]; + +define register offset=0x4800 size=8 +[ + TMPD1 _ _ _ + TMPD2 _ _ _ + TMPD3 _ _ _ + TMPD4 _ _ _ + TMPD5 _ _ _ + TMPD6 _ _ _ +]; + +define register offset=0x4800 size=4 +[ + TMPS1 _ _ _ _ _ _ _ + TMPS2 _ _ _ _ _ _ _ + TMPS3 _ _ _ _ _ _ _ + TMPS4 _ _ _ _ _ _ _ + TMPS5 _ _ _ _ _ _ _ + TMPS6 _ _ _ _ _ _ _ +]; + +@else # this is DATA_ENDIAN == "big" + +define register offset=0x4800 size=16 +[ + _ TMPQ1 + _ TMPQ2 + _ TMPQ3 + _ TMPQ4 + _ TMPQ5 + _ TMPQ6 +]; + +define register offset=0x4800 size=8 +[ + _ _ _ TMPD1 + _ _ _ TMPD2 + _ _ _ TMPD3 + _ _ _ TMPD4 + _ _ _ TMPD5 + _ _ _ TMPD6 +]; + +define register offset=0x4800 size=4 +[ + _ _ _ _ _ _ _ TMPS1 + _ _ _ _ _ _ _ TMPS2 + _ _ _ _ _ _ _ TMPS3 + _ _ _ _ _ _ _ TMPS4 + _ _ _ _ _ _ _ TMPS5 + _ _ _ _ _ _ _ TMPS6 +]; + +@endif + +# The size of the simd (z) register (in bytes) can be any multiple of +# 16 from 32 to 256 bytes. There are also 16 predicate registers are +# 1/8 the size of the corresponding simd registers. + +@define SIMD_SIZE "32" +@define PRED_SIZE "4" + +# In order to "move" the overlain registers to the right place, use +# these defines to locate within the z register. The __128 is for an +# 128-bit vector overlaid in a z-register, etc. For this to work +# SIMD_SIZE must be at least 32. + +define register offset=0x5000 size=$(SIMD_SIZE) +[ + z0 z1 z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15 + z16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31 +]; + +define register offset=0x6000 size=$(PRED_SIZE) +[ + p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 +]; + +# define the overlaid simd registers + +@if DATA_ENDIAN == "little" + +define register offset=0x5000 size=16 +[ + q0 _ + q1 _ + q2 _ + q3 _ + q4 _ + q5 _ + q6 _ + q7 _ + q8 _ + q9 _ + q10 _ + q11 _ + q12 _ + q13 _ + q14 _ + q15 _ + q16 _ + q17 _ + q18 _ + q19 _ + q20 _ + q21 _ + q22 _ + q23 _ + q24 _ + q25 _ + q26 _ + q27 _ + q28 _ + q29 _ + q30 _ + q31 _ +]; + +define register offset=0x5000 size=8 +[ + d0 _ _ _ + d1 _ _ _ + d2 _ _ _ + d3 _ _ _ + d4 _ _ _ + d5 _ _ _ + d6 _ _ _ + d7 _ _ _ + d8 _ _ _ + d9 _ _ _ + d10 _ _ _ + d11 _ _ _ + d12 _ _ _ + d13 _ _ _ + d14 _ _ _ + d15 _ _ _ + d16 _ _ _ + d17 _ _ _ + d18 _ _ _ + d19 _ _ _ + d20 _ _ _ + d21 _ _ _ + d22 _ _ _ + d23 _ _ _ + d24 _ _ _ + d25 _ _ _ + d26 _ _ _ + d27 _ _ _ + d28 _ _ _ + d29 _ _ _ + d30 _ _ _ + d31 _ _ _ +]; + +define register offset=0x5000 size=4 +[ + s0 _ _ _ _ _ _ _ + s1 _ _ _ _ _ _ _ + s2 _ _ _ _ _ _ _ + s3 _ _ _ _ _ _ _ + s4 _ _ _ _ _ _ _ + s5 _ _ _ _ _ _ _ + s6 _ _ _ _ _ _ _ + s7 _ _ _ _ _ _ _ + s8 _ _ _ _ _ _ _ + s9 _ _ _ _ _ _ _ + s10 _ _ _ _ _ _ _ + s11 _ _ _ _ _ _ _ + s12 _ _ _ _ _ _ _ + s13 _ _ _ _ _ _ _ + s14 _ _ _ _ _ _ _ + s15 _ _ _ _ _ _ _ + s16 _ _ _ _ _ _ _ + s17 _ _ _ _ _ _ _ + s18 _ _ _ _ _ _ _ + s19 _ _ _ _ _ _ _ + s20 _ _ _ _ _ _ _ + s21 _ _ _ _ _ _ _ + s22 _ _ _ _ _ _ _ + s23 _ _ _ _ _ _ _ + s24 _ _ _ _ _ _ _ + s25 _ _ _ _ _ _ _ + s26 _ _ _ _ _ _ _ + s27 _ _ _ _ _ _ _ + s28 _ _ _ _ _ _ _ + s29 _ _ _ _ _ _ _ + s30 _ _ _ _ _ _ _ + s31 _ _ _ _ _ _ _ +]; + +define register offset=0x5000 size=2 +[ + h0 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h2 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h3 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h4 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h5 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h6 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h7 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h8 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h9 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h10 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h11 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h12 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h13 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h14 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h15 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h16 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h17 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h18 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h19 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h20 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h21 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h22 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h23 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h24 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h25 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h26 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h27 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h28 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h29 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h30 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + h31 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ +]; + +define register offset=0x5000 size=1 +[ + b0 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b2 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b3 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b4 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b5 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b6 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b7 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b8 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b9 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b10 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b11 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b12 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b13 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b14 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b15 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b16 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b17 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b18 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b19 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b20 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b21 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b22 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b23 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b24 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b25 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b26 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b27 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b28 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b29 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b30 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + b31 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ +]; + +@else # this is DATA_ENDIAN == "big" + +define register offset=0x5000 size=16 +[ + _ q0 + _ q1 + _ q2 + _ q3 + _ q4 + _ q5 + _ q6 + _ q7 + _ q8 + _ q9 + _ q10 + _ q11 + _ q12 + _ q13 + _ q14 + _ q15 + _ q16 + _ q17 + _ q18 + _ q19 + _ q20 + _ q21 + _ q22 + _ q23 + _ q24 + _ q25 + _ q26 + _ q27 + _ q28 + _ q29 + _ q30 + _ q31 +]; + +define register offset=0x5000 size=8 +[ + _ _ _ d0 + _ _ _ d1 + _ _ _ d2 + _ _ _ d3 + _ _ _ d4 + _ _ _ d5 + _ _ _ d6 + _ _ _ d7 + _ _ _ d8 + _ _ _ d9 + _ _ _ d10 + _ _ _ d11 + _ _ _ d12 + _ _ _ d13 + _ _ _ d14 + _ _ _ d15 + _ _ _ d16 + _ _ _ d17 + _ _ _ d18 + _ _ _ d19 + _ _ _ d20 + _ _ _ d21 + _ _ _ d22 + _ _ _ d23 + _ _ _ d24 + _ _ _ d25 + _ _ _ d26 + _ _ _ d27 + _ _ _ d28 + _ _ _ d29 + _ _ _ d30 + _ _ _ d31 +]; + +define register offset=0x5000 size=4 +[ + _ _ _ _ _ _ _ s0 + _ _ _ _ _ _ _ s1 + _ _ _ _ _ _ _ s2 + _ _ _ _ _ _ _ s3 + _ _ _ _ _ _ _ s4 + _ _ _ _ _ _ _ s5 + _ _ _ _ _ _ _ s6 + _ _ _ _ _ _ _ s7 + _ _ _ _ _ _ _ s8 + _ _ _ _ _ _ _ s9 + _ _ _ _ _ _ _ s10 + _ _ _ _ _ _ _ s11 + _ _ _ _ _ _ _ s12 + _ _ _ _ _ _ _ s13 + _ _ _ _ _ _ _ s14 + _ _ _ _ _ _ _ s15 + _ _ _ _ _ _ _ s16 + _ _ _ _ _ _ _ s17 + _ _ _ _ _ _ _ s18 + _ _ _ _ _ _ _ s19 + _ _ _ _ _ _ _ s20 + _ _ _ _ _ _ _ s21 + _ _ _ _ _ _ _ s22 + _ _ _ _ _ _ _ s23 + _ _ _ _ _ _ _ s24 + _ _ _ _ _ _ _ s25 + _ _ _ _ _ _ _ s26 + _ _ _ _ _ _ _ s27 + _ _ _ _ _ _ _ s28 + _ _ _ _ _ _ _ s29 + _ _ _ _ _ _ _ s30 + _ _ _ _ _ _ _ s31 +]; + +define register offset=0x5000 size=2 +[ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h0 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h1 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h2 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h3 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h4 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h5 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h6 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h7 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h8 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h9 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h10 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h11 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h12 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h13 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h14 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h15 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h16 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h17 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h18 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h19 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h20 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h21 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h22 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h23 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h24 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h25 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h26 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h27 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h28 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h29 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h30 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h31 +]; + +define register offset=0x5000 size=1 +[ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b0 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b1 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b2 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b3 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b4 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b5 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b6 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b7 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b8 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b9 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b10 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b11 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b12 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b13 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b14 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b15 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b16 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b17 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b18 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b19 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b20 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b21 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b22 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b23 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b24 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b25 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b26 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b27 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b28 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b29 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b30 + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b31 +]; +@endif + +# SECTION token fields and context variables + +# "noflow" limits register changes to a single instruction (or a highlighted region) rather than following control flow. +# This allows the select-clear-SetRegister-disassemble procedure to be done without affecting +# any instructions other than those that are selected. +define context contextreg + ImmS_ImmR_TestSet = (0,0) + ImmS_LT_ImmR = (1,1) + ImmS_EQ_ImmR = (2,2) + ImmS_LT_ImmR_minus_1 = (3,3) + ImmS_ne_1f = (4,4) + ImmS_ne_3f = (5,5) + ShowPAC = (21,21) noflow + PAC_clobber = (22,22) noflow + ShowBTI = (23,23) noflow + ShowMemTag = (24,24) noflow +; + +define token instrAARCH64 (32) endian = little + + Rm = (16,20) + Rn = (5,9) + Rd = (0,4) + Rt = (0,4) + Ra = (10,14) + Rt2 = (10,14) + + Rm_FPR8 = (16,20) + Rn_FPR8 = (5,9) + Rd_FPR8 = (0,4) + Rd_FPR8_2 = (0,4) + Rt_FPR8 = (0,4) + Rm_FPR16 = (16,20) + Rn_FPR16 = (5,9) + Rd_FPR16 = (0,4) + Rd_FPR16_2 = (0,4) + Rt_FPR16 = (0,4) + Ra_FPR16 = (10,14) + Rm_FPR32 = (16,20) + Rn_FPR32 = (5,9) + Rd_FPR32 = (0,4) + Rd_FPR32_2 = (0,4) + Ra_FPR32 = (10,14) + Rm_FPR64 = (16,20) + Rn_FPR64 = (5,9) + Rd_FPR64 = (0,4) + Rd_FPR64_2 = (0,4) + Rt_FPR64 = (0,4) + Rt_FPR32 = (0,4) + Ra_FPR64 = (10,14) + Rt2_FPR128 = (10,14) + Rt2_FPR32 = (10,14) + Rt2_FPR64 = (10,14) + Ra_VPR128 = (10,14) + + Rm_VPR64 = (16,20) + Rn_VPR64 = (5,9) + Rd_VPR64 = (0,4) + + Re_VPR128 = (16,20) + Re_VPR128Lo = (16,19) + Rm_VPR128 = (16,20) + Rm_VPR128Lo = (16,19) + Rn_VPR128 = (5,9) + Rnn_VPR128 = (5,9) + Rnnn_VPR128 = (5,9) + Rnnnn_VPR128 = (5,9) + Rd_VPR128 = (0,4) + Rt_VPR128 = (0,4) + Rtt_VPR128 = (0,4) + Rttt_VPR128 = (0,4) + Rtttt_VPR128 = (0,4) + Rt_VPR64 = (0,4) + Rtt_VPR64 = (0,4) + Rttt_VPR64 = (0,4) + Rtttt_VPR64 = (0,4) + Rt_FPR128 = (0,4) + vRm_VPR64 = (16,20) + vRm_VPR128Lo = (16,19) + vRe_VPR128 = (16,20) + vRe_VPR128Lo = (16,19) + vRn_VPR64 = (5,9) + vRd_VPR64 = (0,4) + vRm_VPR128 = (16,20) + vRn_VPR128 = (5,9) + vRnn_VPR128 = (5,9) + vRnnn_VPR128 = (5,9) + vRnnnn_VPR128 = (5,9) + vRd_VPR128 = (0,4) + vRa_VPR128 = (10,14) + + Vt = (0,4) + Vtt = (0,4) + Vttt = (0,4) + Vtttt = (0,4) + + vVt = (0,4) + vVtt = (0,4) + vVttt = (0,4) + vVtttt = (0,4) + + aa_Xm = (16,20) + aa_Xn = (5,9) + aa_Xd = (0,4) + aa_Xs = (16,20) + aa_Xss = (16,20) + aa_Xt = (0,4) + aa_Xtt = (0,4) + aa_Xa = (10,14) + aa_Wm = (16,20) + aa_Wn = (5,9) + aa_Wd = (0,4) + aa_Ws = (16,20) + aa_Wss = (16,20) + aa_Wt = (0,4) + aa_Wtt = (0,4) + aa_Wa = (10,14) + aa_Wa2 = (10,14) + aa_CRm = (8,11) + + br_cond_op = (0,3) + cond_op = (12,15) + + aa_prefetch = (0,4) + + aa_hw = (21,22) + + aa_extreg_imm3 = (10,12) + aa_extreg_shift = (22,23) + aa_extreg_option = (13,15) + + imm6 = (10,15) + aa_imm7 = (15,21) + imm12 = (10,21) + imm16 = (5,20) + + simm7 = (15,21) signed + simm9 = (12,20) signed + simm14 = (5,18) signed + simm19 = (5,23) signed + simm26 = (0,25) signed + + immlo = (29,30) + immhi = (5,23) signed + + # Arbitrary bit fields + + b_00 = (0,0) + b_01 = (1,1) + b_02 = (2,2) + b_03 = (3,3) + b_04 = (4,4) + b_05 = (5,5) + b_06 = (6,6) + b_07 = (7,7) + b_08 = (8,8) + b_09 = (9,9) + b_10 = (10,10) + b_11 = (11,11) + b_12 = (12,12) + b_13 = (13,13) + b_14 = (14,14) + b_15 = (15,15) + b_16 = (16,16) + b_17 = (17,17) + b_18 = (18,18) + b_19 = (19,19) + b_20 = (20,20) + b_21 = (21,21) + b_22 = (22,22) + b_23 = (23,23) + b_24 = (24,24) + b_25 = (25,25) + b_26 = (26,26) + b_27 = (27,27) + b_28 = (28,28) + b_29 = (29,29) + b_30 = (30,30) + b_31 = (31,31) + + b_0001 = (0,1) + b_0003 = (0,3) + b_0004 = (0,4) + b_0006 = (0,6) + b_0007 = (0,7) + b_0009 = (0,9) + b_0011 = (0,11) + b_0015 = (0,15) + b_0027 = (0,27) + b_0031 = (0,31) + b_0102 = (1,2) + b_0103 = (1,3) + b_0204 = (2,4) + b_0304 = (3,4) + b_0405 = (4,5) + b_0406 = (4,6) + b_0407 = (4,7) + b_0409 = (4,9) + b_0411 = (4,11) + b_0427 = (4,27) + b_0431 = (4,31) + b_0506 = (5,6) + b_0507 = (5,7) + b_0508 = (5,8) + b_0509 = (5,9) + b_0510 = (5,10) + b_0515 = (5,15) + b_0519 = (5,19) + b_0531 = (5,31) + b_0607 = (6,7) + b_0609 = (6,9) + b_0610 = (6,10) + b_0611 = (6,11) + b_0708 = (7,8) + b_0709 = (7,9) + b_0710 = (7,10) + b_0711 = (7,11) + b_0809 = (8,9) + b_0810 = (8,10) + b_0811 = (8,11) + b_0910 = (9,10) + b_0911 = (9,11) + b_0916 = (9,16) + b_1010 = (10,10) + b_1011 = (10,11) + b_1012 = (10,12) + b_1013 = (10,13) + b_1014 = (10,14) + b_1015 = (10,15) + b_1021 = (10,21) + b_1022 = (10,22) + b_1028 = (10,28) + b_1029 = (10,29) + b_1031 = (10,31) + b_1111 = (11,11) + b_1112 = (11,12) + b_1113 = (11,13) + b_1114 = (11,14) + b_1115 = (11,15) + b_1116 = (11,16) + b_1131 = (11,31) + b_1212 = (12,12) + b_1213 = (12,13) + b_1214 = (12,14) + b_1215 = (12,15) + b_1216 = (12,16) + b_1217 = (12,17) + b_1220 = (12,20) + b_1223 = (12,23) + b_1229 = (12,29) + b_1230 = (12,30) + b_1231 = (12,31) + b_1313 = (13,13) + b_1314 = (13,14) + b_1315 = (13,15) + b_1317 = (13,17) + b_1321 = (13,21) + b_1322 = (13,22) + b_1414 = (14,14) + b_1417 = (14,17) + b_1415 = (14,15) + b_1431 = (14,31) + b_1515 = (15,15) + b_1517 = (15,17) + b_1520 = (15,20) + b_1531 = (15,31) + b_1616 = (16,16) + b_1617 = (16,17) + b_1618 = (16,18) + b_1619 = (16,19) + b_1620 = (16,20) + b_1621 = (16,21) + b_1623 = (16,23) + b_1627 = (16,27) + b_1629 = (16,29) + b_1631 = (16,31) + b_1718 = (17,18) + b_1719 = (17,19) + b_1720 = (17,20) + b_1721 = (17,21) + b_1722 = (17,22) + b_1818 = (18,18) + b_1819 = (18,19) + b_1820 = (18,20) + b_1821 = (18,21) + b_1920 = (19,20) + b_1921 = (19,21) + b_1922 = (19,22) + b_1923 = (19,23) + b_1928 = (19,28) + b_1929 = (19,29) + b_1931 = (19,31) + b_2020 = (20,20) + b_2021 = (20,21) + b_2022 = (20,22) + b_2023 = (20,23) + b_2024 = (20,24) + b_2027 = (20,27) + b_2121 = (21,21) + b_2122 = (21,22) + b_2123 = (21,23) + b_2124 = (21,24) + b_2125 = (21,25) + b_2127 = (21,27) + b_2128 = (21,28) + b_2129 = (21,29) + b_2130 = (21,30) + b_2131 = (21,31) + b_2222 = (22,22) + b_2223 = (22,23) + b_2224 = (22,24) + b_2225 = (22,25) + b_2229 = (22,29) + b_2231 = (22,31) + b_2323 = (23,23) + b_2324 = (23,24) + b_2325 = (23,25) + b_2327 = (23,27) + b_2328 = (23,28) + b_2329 = (23,29) + b_2331 = (23,31) + b_2425 = (24,25) + b_2427 = (24,27) + b_2428 = (24,28) + b_2429 = (24,29) + b_2430 = (24,30) + b_2431 = (24,31) + b_2525 = (25,25) + b_2527 = (25,27) + b_2529 = (25,29) + b_2530 = (25,30) + b_2531 = (25,31) + b_2627 = (26,27) + b_2629 = (26,29) + b_2630 = (26,30) + b_2631 = (26,31) + b_2729 = (27,29) + b_2929 = (29,29) + b_2930 = (29,30) + b_2931 = (29,31) + b_3030 = (30,30) + b_3031 = (30,31) + b_3131 = (31,31) + + cmpr_op = (24,24) + sf = (31,31) + + imm_neon_uimm1 = (20,20) + imm_neon_uimm2 = (19,20) + imm_neon_uimm3 = (18,20) + imm_neon_uimm4 = (17,20) + immN_neon_uimm1 = (14,14) + immN_neon_uimm2 = (13,14) + immN_neon_uimm3 = (12,14) + immN_neon_uimm4 = (11,14) + + fpOpcode = (16,18) + fpDpOpcode = (15,20) + + CRm_CRx = (8,11) + CRm_32 = (10,11) + CRm_10 = (8,9) + CRm_dbarrier_op = (8,11) + CRm_isb_op = (8,11) + + CRn = (12,15) + CRm = (8,11) + CRn_CRx = (12,15) + + Imm4 = (11,13) + + # C2.2.3 Modified immediate constants in A64 instructions page C2-158 + + Imm8_fmov_sign = (20,20) # a + Imm8_fmov_exph = (19,19) # b + Imm8_fmov_expl = (17,18) # cd + Imm8_fmov_frac = (13,16) # efgh + + ImmN = (22,22) + ImmR = (16,21) + ImmS = (10,15) + Imm_imm0_63 = (16,21) + + n_uimm8L = (5,9) + n_uimm8H = (16,18) + + Imm_uimm3 = (16,18) + Imm_uimm4 = (16,19) + Imm_uimm5 = (16,20) + Imm_uimm5_31 = (31,31) + Imm_uimm6 = (31,31) + + L = (22,22) + + N = (21,21) + + Op0 = (19,20) + Op1 = (16,18) + Op1_uimm3 = (16,18) + Op2 = (5,7) + Op2_uimm3 = (5,7) + Q = (30,30) + S = (29,29) + + Scale = (10,15) + + excCode = (21,23) + excCode2 = (2,4) + + imm7Low = (5,11) + + cmode = (12,15) + imm4 = (11,14) + imm5 = (5,9) + l = (21,21) + ll = (0,1) + m = (31,31) + mode = (19,20) + n = (22,22) + o0 = (4,4) + o1 = (24,24) + o2 = (10,10) + + o3 = (4,4) + op = (30,30) + + fpccmp.op = (4,4) + fpcmp.op = (14,15) + + op2 = (16,20) + + op3 = (10,15) + op4 = (0,4) + opc = (29,30) + opc.indexmode = (10,11) + + op.dp3 = (29,30) + op.dp3_o0 = (15,15) + op.dp3_op31 = (21,23) + op.dp3_op54 = (29,30) + + opcode2 = (10,15) + dp1.opcode2 = (16,20) + fpcmp.opcode2 = (0,4) + opt = (22,23) + option = (13,15) + optionlo = (13,13) + q = (30,30) + rmode = (19,20) + s = (29,29) + + size.ldstr = (30,31) + + shift = (22,23) + advSIMD3.size = (22,23) + size.neon = (10,11) + + size_high = (23,23) + ftype = (22,23) + u = (29,29) + v = (26,26) + + # SVE tokens + + Zd = (0,4) + Zt = (0,4) + Ztt = (0,4) + Zttt = (0,4) + Ztttt = (0,4) + Ze = (16,20) + Zm = (16,20) + Zn = (5,9) + Zt2 = (10,14) + + sve_b_00 = (0,0) + sve_b_0001 = (0,1) + sve_b_01 = (1,1) + sve_b_02 = (2,2) + sve_b_03 = (3,3) + sve_b_04 = (4,4) + sve_b_0409 = (4,9) + sve_b_0609 = (6,9) + sve_b_09 = (9,9) + sve_b_10 = (10,10) + sve_b_1015 = (10,15) + sve_b_1019 = (10,19) + sve_b_1021 = (10,21) + sve_b_11 = (11,11) + sve_b_1112 = (11,12) + sve_b_1115 = (11,15) + sve_b_12 = (12,12) + sve_b_1215 = (12,15) + sve_b_13 = (13,13) + sve_b_1315 = (13,15) + sve_b_1321 = (13,21) + sve_b_14 = (14,14) + sve_b_1415 = (14,15) + sve_b_1416 = (14,16) + sve_b_1419 = (14,19) + sve_b_1421 = (14,21) + sve_b_15 = (15,15) + sve_b_16 = (16,16) + sve_b_17 = (17,17) + sve_b_1718 = (17,18) + sve_b_1719 = (17,19) + sve_b_1720 = (17,20) + sve_b_1721 = (17,21) + sve_b_1731 = (17,31) + sve_b_18 = (18,18) + sve_b_1821 = (18,21) + sve_b_1831 = (18,31) + sve_b_1921 = (19,21) + sve_b_20 = (20,20) + sve_b_2021 = (20,21) + sve_b_2022 = (20,22) + sve_b_21 = (21,21) + sve_b_2122 = (21,22) + sve_b_2131 = (21,31) + sve_b_22 = (22,22) + sve_b_2224 = (22,24) + sve_b_2231 = (22,31) + sve_b_23 = (23,23) + sve_b_2331 = (23,31) + sve_b_24 = (24,24) + sve_b_2429 = (24,29) + sve_b_2431 = (24,31) + sve_b_2531 = (25,31) + sve_b_3031 = (30,31) + sve_float_dec = (5,8) + sve_float_exp = (9,11) + sve_i1_05 = (5,5) + sve_i1_20 = (20,20) + sve_i2_1920 = (19,20) + sve_i3h_22 = (22,22) + sve_i3l_1920 = (19,20) + sve_imm13_0517 = (5,17) + sve_imm2_2223 = (22,23) + sve_imm3_0507 = (5,7) + sve_imm3_1618 = (16,18) + sve_imm4_1619 = (16,19) + sve_imm4s_1619 = (16,19) signed + sve_imm5_0509 = (5,9) + sve_imm5s_0509 = (5,9) signed + sve_imm5_1620 = (16,20) + sve_imm5s_1620 = (16,20) signed + sve_imm5b_1620 = (16,20) signed + sve_imm6_0510 = (5,10) + sve_imm6s_0510 = (5,10) signed + sve_imm6_1621 = (16,21) + sve_imm6s_1621 = (16,21) signed + sve_imm7_1420 = (14,20) + sve_imm8_0512 = (5,12) + sve_imm8s_0512 = (5,12) signed + sve_imm8h_1620 = (16,20) + sve_imm8l_1012 = (10,12) + sve_imm9h_1621 = (16,21) + sve_imm9hs_1621 = (16,21) signed + sve_imm9l_1012 = (10,12) + sve_m_04 = (4,4) + sve_m_14 = (14,14) + sve_m_16 = (16,16) + sve_msz_1011 = (10,11) + sve_pattern_0509 = (5,9) + sve_pd_0003 = (0,3) + sve_pdm_0003 = (0,3) + sve_pdn_0003 = (0,3) + sve_pg_0508 = (5,8) + sve_pg_1012 = (10,12) + sve_pg_1013 = (10,13) + sve_pg_1619 = (16,19) + sve_pm_1619 = (16,19) + sve_pn_0508 = (5,8) + sve_prfop_0003 = (0,3) + sve_pt_0003 = (0,3) + sve_rd_0004 = (0,4) + sve_rdn_0004 = (0,4) + sve_rm_0509 = (5,9) + sve_rm_1620 = (16,20) + sve_rn_0509 = (5,9) + sve_rn_1620 = (16,20) + sve_rot_1011 = (10,11) + sve_rot_1314 = (13,14) + sve_rot_16 = (16,16) + sve_s_22 = (22,22) + sve_sf_12 = (12,12) + sve_sh_13 = (13,13) + sve_size_2122 = (21,22) + sve_size_2223 = (22,23) + sve_sz_22 = (22,22) + sve_tsz_1620 = (16,20) + sve_tszh_2223 = (22,23) + sve_tszl_0809 = (8,9) + sve_tszl_1920 = (19,20) + sve_vd_0004 = (0,4) + sve_vdn_0004 = (0,4) + sve_vm_0509 = (5,9) + sve_vn_0509 = (5,9) + sve_xs_14 = (14,14) + sve_xs_22 = (22,22) + sve_za_0509 = (5,9) + sve_za_1620 = (16,20) + sve_zd_0004 = (0,4) + sve_zda_0004 = (0,4) + sve_zdn_0004 = (0,4) + sve_zm_0509 = (5,9) + sve_zm_1618 = (16,18) + sve_zm_1619 = (16,19) + sve_zm_1620 = (16,20) + sve_zn_0509 = (5,9) + sve_zt_0004 = (0,4) + sve_ztt_0004 = (0,4) + sve_zttt_0004 = (0,4) + sve_ztttt_0004 = (0,4) +; + +# SECTION variables and variable names + +attach variables [ Zd Ze Zm Zn Zt Zt2 ] +[ + z0 z1 z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15 + z16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31 +]; + +attach variables [ Ztt ] +[ + z1 z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15 + z16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31 z0 +]; + +attach variables [ Zttt ] +[ + z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15 + z16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31 z0 z1 +]; + +attach variables [ Ztttt ] +[ + z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15 + z16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31 z0 z1 z2 +]; + +attach variables [ aa_Xn aa_Xm aa_Xs aa_Xd aa_Xt aa_Xa ] +[ + x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 + x16 x17 x18 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28 x29 x30 xzr +]; + +attach variables [ aa_Xss aa_Xtt ] +[ + x1 _ x3 _ x5 _ x7 _ x9 _ x11 _ x13 _ x15 + _ x17 _ x19 _ x21 _ x23 _ x25 _ x27 _ x29 _ xzr _ +]; + +attach variables [ aa_Wn aa_Wm aa_Ws aa_Wd aa_Wt aa_Wa ] +[ + w0 w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 w14 w15 + w16 w17 w18 w19 w20 w21 w22 w23 w24 w25 w26 w27 w28 w29 w30 wzr +]; + +attach variables [ aa_Wss aa_Wtt ] +[ + w1 _ w3 _ w5 _ w7 _ w9 _ w11 _ w13 _ w15 + _ w17 _ w19 _ w21 _ w23 _ w25 _ w27 _ w29 _ wzr _ +]; + +attach variables [ Rm_VPR128 Rn_VPR128 Rd_VPR128 Rt_VPR128 Rt2_FPR128 Re_VPR128 Rt_FPR128 Ra_VPR128 ] +[ + q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 + q16 q17 q18 q19 q20 q21 q22 q23 q24 q25 q26 q27 q28 q29 q30 q31 +]; + +attach variables [ Rnn_VPR128 Rtt_VPR128 ] +[ + q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 + q16 q17 q18 q19 q20 q21 q22 q23 q24 q25 q26 q27 q28 q29 q30 q31 + q0 +]; + +attach variables [ Rnnn_VPR128 Rttt_VPR128 ] +[ + q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 + q16 q17 q18 q19 q20 q21 q22 q23 q24 q25 q26 q27 q28 q29 q30 q31 + q0 q1 +]; + +attach variables [ Rnnnn_VPR128 Rtttt_VPR128 ] +[ + q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 + q16 q17 q18 q19 q20 q21 q22 q23 q24 q25 q26 q27 q28 q29 q30 q31 + q0 q1 q2 +]; + +attach names [ vRm_VPR128 vRn_VPR128 vRd_VPR128 vRe_VPR128 vRa_VPR128 ] +[ + v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 + v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 +]; + +attach names [ vRnn_VPR128 ] +[ + v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 + v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 + v0 +]; + +attach names [ vRnnn_VPR128 ] +[ + v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 + v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 + v0 v1 +]; + +attach names [ vRnnnn_VPR128 ] +[ + v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 + v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 + v0 v1 v2 +]; + +attach variables [ Rm_VPR128Lo Re_VPR128Lo ] [ q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 ]; + +attach names [ vRm_VPR128Lo vRe_VPR128Lo ] [ v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 ]; + +attach variables [ Rm_VPR64 Rn_VPR64 Rd_VPR64 Rt_VPR64 ] +[ + d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 + d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 +]; + +attach variables [ Rtt_VPR64 ] +[ + d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 + d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 d0 +]; + +attach variables [ Rttt_VPR64 ] +[ + d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 + d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 d0 d1 +]; + +attach variables [ Rtttt_VPR64 ] +[ + d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 + d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 d0 d1 d2 +]; + +attach names [ vRm_VPR64 vRn_VPR64 vRd_VPR64 ] +[ + v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 + v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 +]; + +attach variables [ Rm_FPR64 Rn_FPR64 Rd_FPR64 Rd_FPR64_2 Rt2_FPR64 Ra_FPR64 Rt_FPR64 ] +[ + d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 + d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 +]; + +attach variables [ Rm_FPR32 Rn_FPR32 Rd_FPR32 Rd_FPR32_2 Rt2_FPR32 Ra_FPR32 Rt_FPR32 ] +[ + s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 + s16 s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31 +]; + +attach variables [ Rm_FPR16 Rn_FPR16 Rd_FPR16 Rd_FPR16_2 Rt_FPR16 Ra_FPR16 ] +[ + h0 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14 h15 + h16 h17 h18 h19 h20 h21 h22 h23 h24 h25 h26 h27 h28 h29 h30 h31 +]; + +attach variables [ Rm_FPR8 Rn_FPR8 Rd_FPR8 Rd_FPR8_2 Rt_FPR8 ] +[ + b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 + b16 b17 b18 b19 b20 b21 b22 b23 b24 b25 b26 b27 b28 b29 b30 b31 +]; + +attach variables [ Vt ] +[ + q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 + q16 q17 q18 q19 q20 q21 q22 q23 q24 q25 q26 q27 q28 q29 q30 q31 +]; + +attach variables [ Vtt ] +[ + q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 + q16 q17 q18 q19 q20 q21 q22 q23 q24 q25 q26 q27 q28 q29 q30 q31 q0 +]; + +attach variables [ Vttt ] +[ + q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 + q16 q17 q18 q19 q20 q21 q22 q23 q24 q25 q26 q27 q28 q29 q30 q31 q0 q1 +]; + +attach variables [ Vtttt ] +[ + q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 + q16 q17 q18 q19 q20 q21 q22 q23 q24 q25 q26 q27 q28 q29 q30 q31 q0 q1 q2 +]; + +attach names [ vVt ] +[ + v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 + v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 +]; + +attach names [ vVtt ] +[ + v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 + v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 v0 +]; + +attach names [ vVttt ] +[ + v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 + v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 v0 v1 +]; + +attach names [ vVtttt ] +[ + v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 + v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 v0 v1 v2 +]; + +attach names [ aa_prefetch ] +[ + PLDL1KEEP PLDL1STRM PLDL2KEEP PLDL2STRM PLDL3KEEP PLDL3STRM P_0x06 P_0x07 + PLIL1KEEP PLIL1STRM PLIL2KEEP PLIL2STRM PLIL3KEEP PLIL3STRM P_0x0e P_0x0f + PSTL1KEEP PSTL1STRM PSTL2KEEP PSTL2STRM PSTL3KEEP PSTL3STRM + P_0x16 P_0x17 P_0x18 P_0x19 P_0x1a P_0x1b P_0x1c P_0x1d P_0x1e P_0x1f +]; + +attach names [ CRm_dbarrier_op ] [ _ OSHLD OSHST OSH _ NSHLD NSHST NSH _ ISHLD ISHST ISH _ LD ST SY ]; + +# SVE registers and names + +attach variables [ sve_zm_1618 ] +[ + z0 z1 z2 z3 z4 z5 z6 z7 +]; + +attach variables [ sve_zm_1619 ] +[ + z0 z1 z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15 +]; + +attach variables [ sve_za_0509 sve_za_1620 sve_zd_0004 sve_zda_0004 sve_zdn_0004 sve_zm_0509 sve_zm_1620 sve_zn_0509 sve_zt_0004 ] +[ + z0 z1 z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15 + z16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31 +]; + +attach variables [ sve_ztt_0004 ] +[ + z1 z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15 + z16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31 z0 +]; + +attach variables [ sve_zttt_0004 ] +[ + z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15 + z16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31 z0 z1 +]; + +attach variables [ sve_ztttt_0004 ] +[ + z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15 + z16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31 z0 z1 z2 +]; + +attach variables [ sve_pg_1012 ] +[ + p0 p1 p2 p3 p4 p5 p6 p7 +]; + +attach variables [ sve_pd_0003 sve_pdm_0003 sve_pdn_0003 sve_pg_0508 sve_pg_1013 sve_pg_1619 sve_pm_1619 sve_pn_0508 sve_pt_0003 ] +[ + p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 +]; + +attach names [ sve_sz_22 ] [ b h ]; +attach names [ sve_msz_1011 ] [ "" " #1" " #2" " #3" ]; +attach names [ sve_rot_16 ] [ "#90" "#270" ]; +attach names [ sve_rot_1314 ] [ "#0" "#90" "#180" "#270" ]; +attach names [ sve_rot_1011 ] [ "#0" "#90" "#180" "#270" ]; + +# SECTION subtables + +Rm_GPR32: aa_Wm is aa_Wm { export aa_Wm; } +Rm_GPR32: wzr is aa_Wm=31 & wzr { tmp:4 = 0; export tmp; } + +Rd_GPR32: aa_Wd is aa_Wd { export aa_Wd; } +Rd_GPR32: wzr is aa_Wd=31 & wzr { tmp:4 = 0; export tmp; } +Rd_GPR32_2: aa_Wd is aa_Wd { export aa_Wd; } +Rd_GPR32_2: wzr is aa_Wd=31 & wzr { tmp:4 = 0; export tmp; } + +Rd_GPR32xsp: aa_Wd is aa_Wd { export aa_Wd; } +Rd_GPR32xsp: wsp is aa_Wd=31 & wsp { export wsp; } + +Rd_GPR32wsp: Rd_GPR32xsp is Rd_GPR32xsp { export Rd_GPR32xsp; } + +Rn_GPR32: aa_Wn is aa_Wn { export aa_Wn; } +Rn_GPR32: wzr is aa_Wn=31 & wzr { tmp:4 = 0; export tmp; } + +Ra_GPR32: aa_Wa is aa_Wa { export aa_Wa; } +Ra_GPR32: wzr is aa_Wa=31 & wzr { tmp:4 = 0; export tmp; } + +Rt2_GPR32: aa_Wa is aa_Wa { export aa_Wa; } +Rt2_GPR32: wzr is aa_Wa=31 & wzr { tmp:4 = 0; export tmp; } + +Rn_GPR32xsp: aa_Wn is aa_Wn { export aa_Wn; } +Rn_GPR32xsp: wsp is aa_Wn=31 & wsp { export wsp; } + +Rn_GPR32wsp: aa_Wn is aa_Wn { export aa_Wn; } +Rn_GPR32wsp: wsp is aa_Wn=31 & wsp { export wsp; } + +Rt_GPR32: aa_Wt is aa_Wt { export aa_Wt; } +Rt_GPR32: wzr is aa_Wt=31 & wzr { tmp:4 = 0; export tmp; } + +Rm_GPR64: aa_Xm is aa_Xm { export aa_Xm; } +Rm_GPR64: xzr is aa_Xm=31 & xzr { export 0:8; } + +Rd_GPR64: aa_Xd is aa_Xd { export aa_Xd; } +Rd_GPR64: xzr is aa_Xd=31 & xzr { tmp:8 = 0; export tmp; } +Rd_GPR64_2: aa_Xd is aa_Xd { export aa_Xd; } +Rd_GPR64_2: xzr is aa_Xd=31 & xzr { tmp:8 = 0; export tmp; } + +Ra_GPR64: aa_Xa is aa_Xa { export aa_Xa; } +Ra_GPR64: xzr is aa_Xa=31 & xzr { tmp:8 = 0; export tmp; } + +Rt2_GPR64: aa_Xa is aa_Xa { export aa_Xa; } +Rt2_GPR64: xzr is aa_Xa=31 & xzr { tmp:8 = 0; export tmp; } + +Rd_GPR64xsp: aa_Xd is aa_Xd { export aa_Xd; } +Rd_GPR64xsp: sp is aa_Xd=31 & sp { export sp; } + +Rn_GPR64: aa_Xn is aa_Xn { export aa_Xn; } +Rn_GPR64: xzr is aa_Xn=31 & xzr { tmp:8 = 0; export tmp; } + +Rt_GPR64: aa_Xt is aa_Xt { export aa_Xt; } +Rt_GPR64: xzr is aa_Xt=31 & xzr { tmp:8 = 0; export tmp; } + +Rn_GPR64xsp: aa_Xn is aa_Xn { export aa_Xn; } +Rn_GPR64xsp: sp is aa_Xn=31 & sp { export sp; } + +Rm_GPR64xsp: aa_Xm is aa_Xm { export aa_Xm; } +Rm_GPR64xsp: sp is aa_Xm=31 & sp { export sp; } + +Rt_GPR64xsp: aa_Xt is aa_Xt { export aa_Xt; } +Rt_GPR64xsp: sp is aa_Xt=31 & sp { export sp; } + +Rs_GPR32: Rm_GPR32 is Rm_GPR32 { export Rm_GPR32; } +Rs_GPR64: Rm_GPR64 is Rm_GPR64 { export Rm_GPR64; } + +Rm_fpz16: "#0.0" is Rm { tmp:2 = int2float(0:2); export tmp; } +Rm_fpz32: "#0.0" is Rm { tmp:4 = int2float(0:4); export tmp; } +Rm_fpz64: "#0.0" is Rm { tmp:8 = int2float(0:8); export tmp; } + +Rd_VPR128.16B: vRd_VPR128^".16B" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; } +Rd_VPR128.8H: vRd_VPR128^".8H" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; } +Rd_VPR128.4S: vRd_VPR128^".4S" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; } +Rd_VPR128.2S: vRd_VPR128^".2S" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; } +Rd_VPR128.2D: vRd_VPR128^".2D" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; } +Rd_VPR128.1Q: vRd_VPR128^".1Q" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; } + +Rn_VPR128.16B: vRn_VPR128^".16B" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; } +Rnn_VPR128.16B: vRnn_VPR128^".16B" is Rnn_VPR128 & vRnn_VPR128 { export Rnn_VPR128; } +Rnnn_VPR128.16B: vRnnn_VPR128^".16B" is Rnnn_VPR128 & vRnnn_VPR128 { export Rnnn_VPR128; } +Rnnnn_VPR128.16B: vRnnnn_VPR128^".16B" is Rnnnn_VPR128 & vRnnnn_VPR128 { export Rnnnn_VPR128; } + +Rn_VPR128.8B: vRn_VPR128^".8B" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; } +Rn_VPR128.8H: vRn_VPR128^".8H" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; } +Rn_VPR128.4S: vRn_VPR128^".4S" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; } +Rn_VPR128.4H: vRn_VPR128^".4H" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; } +Rn_VPR128.2D: vRn_VPR128^".2D" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; } + +Rm_VPR128.8B: vRm_VPR128^".8B" is Rm_VPR128 & vRm_VPR128 { export Rm_VPR128; } +Rm_VPR128.16B: vRm_VPR128^".16B" is Rm_VPR128 & vRm_VPR128 { export Rm_VPR128; } +Rm_VPR128.8H: vRm_VPR128^".8H" is Rm_VPR128 & vRm_VPR128 { export Rm_VPR128; } +Rm_VPR128.4S: vRm_VPR128^".4S" is Rm_VPR128 & vRm_VPR128 { export Rm_VPR128; } +Rm_VPR128.4H: vRm_VPR128^".4H" is Rm_VPR128 & vRm_VPR128 { export Rm_VPR128; } +Rm_VPR128.2D: vRm_VPR128^".2D" is Rm_VPR128 & vRm_VPR128 { export Rm_VPR128; } + +Ra_VPR128.16B: vRa_VPR128^".16B" is Ra_VPR128 & vRa_VPR128 { export Ra_VPR128; } +# Ra_VPR128.8H: vRa_VPR128^".8H" is Ra_VPR128 & vRa_VPR128 { export Ra_VPR128; } +Ra_VPR128.4S: vRa_VPR128^".4S" is Ra_VPR128 & vRa_VPR128 { export Ra_VPR128; } +# Ra_VPR128.2D: vRa_VPR128^".2D" is Ra_VPR128 & vRa_VPR128 { export Ra_VPR128; } +# Ra_VPR128.1Q: vRa_VPR128^".1Q" is Ra_VPR128 & vRa_VPR128 { export Ra_VPR128; } + +Rd_VPR64.8B: vRd_VPR64^".8B" is Rd_VPR64 & vRd_VPR64 { export Rd_VPR64; } +Rd_VPR64.4H: vRd_VPR64^".4H" is Rd_VPR64 & vRd_VPR64 { export Rd_VPR64; } +Rd_VPR64.2S: vRd_VPR64^".2S" is Rd_VPR64 & vRd_VPR64 { export Rd_VPR64; } +Rd_VPR64.1D: vRd_VPR64^".1D" is Rd_VPR64 & vRd_VPR64 { export Rd_VPR64; } + +Rn_VPR64.8B: vRn_VPR64^".8B" is Rn_VPR64 & vRn_VPR64 { export Rn_VPR64; } +Rn_VPR64.4H: vRn_VPR64^".4H" is Rn_VPR64 & vRn_VPR64 { export Rn_VPR64; } +Rn_VPR64.2S: vRn_VPR64^".2S" is Rn_VPR64 & vRn_VPR64 { export Rn_VPR64; } +Rn_VPR64.1D: vRn_VPR64^".1D" is Rn_VPR64 & vRn_VPR64 { export Rn_VPR64; } + +Rm_VPR64.8B: vRm_VPR64^".8B" is Rm_VPR64 & vRm_VPR64 { export Rm_VPR64; } +Rm_VPR64.4H: vRm_VPR64^".4H" is Rm_VPR64 & vRm_VPR64 { export Rm_VPR64; } +Rm_VPR64.2S: vRm_VPR64^".2S" is Rm_VPR64 & vRm_VPR64 { export Rm_VPR64; } +Rm_VPR64.1D: vRm_VPR64^".1D" is Rm_VPR64 & vRm_VPR64 { export Rm_VPR64; } + +Rd_VPR128.B: vRd_VPR128^".B" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; } +Rd_VPR128.H: vRd_VPR128^".H" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; } +Rd_VPR128.S: vRd_VPR128^".S" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; } +Rd_VPR128.D: vRd_VPR128^".D" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; } + +Rn_VPR128.B: vRn_VPR128^".B" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; } +Rn_VPR128.H: vRn_VPR128^".H" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; } +Rn_VPR128.S: vRn_VPR128^".S" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; } +Rn_VPR128.D: vRn_VPR128^".D" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; } + +Re_VPR128.B: vRe_VPR128^".B" is Re_VPR128 & vRe_VPR128 { export Re_VPR128; } +Re_VPR128.H: vRe_VPR128^".H" is Re_VPR128 & vRe_VPR128 { export Re_VPR128; } +Re_VPR128.S: vRe_VPR128^".S" is Re_VPR128 & vRe_VPR128 { export Re_VPR128; } +Re_VPR128.D: vRe_VPR128^".D" is Re_VPR128 & vRe_VPR128 { export Re_VPR128; } + +Re_VPR128Lo.H: vRe_VPR128Lo^".H" is Re_VPR128Lo & vRe_VPR128Lo { export Re_VPR128Lo; } + +br_cc_op: "eq" is br_cond_op=0 { export ZR; } +br_cc_op: "ne" is br_cond_op=1 { tmp:1 = !ZR; export tmp; } +br_cc_op: "cs" is br_cond_op=2 { export CY; } +br_cc_op: "cc" is br_cond_op=3 { tmp:1 = !CY; export tmp; } +br_cc_op: "mi" is br_cond_op=4 { export NG; } +br_cc_op: "pl" is br_cond_op=5 { tmp:1 = !NG; export tmp; } +br_cc_op: "vs" is br_cond_op=6 { export OV; } +br_cc_op: "vc" is br_cond_op=7 { tmp:1 = !OV; export tmp; } +br_cc_op: "hi" is br_cond_op=8 { tmp:1 = CY && (!ZR); export tmp; } +br_cc_op: "ls" is br_cond_op=9 { tmp:1 = (!CY) || ZR; export tmp; } +br_cc_op: "ge" is br_cond_op=10 { tmp:1 = (NG==OV); export tmp; } +br_cc_op: "lt" is br_cond_op=11 { tmp:1 = (NG!=OV); export tmp; } +br_cc_op: "gt" is br_cond_op=12 { tmp:1 = (!ZR) && (NG==OV); export tmp; } +br_cc_op: "le" is br_cond_op=13 { tmp:1 = ZR || (NG!=OV); export tmp; } +br_cc_op: "al" is br_cond_op=14 { export 1:1; } +br_cc_op: "nv" is br_cond_op=15 { export 1:1; } + +BranchCondOp: br_cc_op is br_cc_op { export br_cc_op; } + +cc_op: "eq" is cond_op=0 { export ZR; } +cc_op: "ne" is cond_op=1 { tmp:1 = !ZR; export tmp; } +cc_op: "cs" is cond_op=2 { export CY; } +cc_op: "cc" is cond_op=3 { tmp:1 = !CY; export tmp; } +cc_op: "mi" is cond_op=4 { export NG; } +cc_op: "pl" is cond_op=5 { tmp:1 = !NG; export tmp; } +cc_op: "vs" is cond_op=6 { export OV; } +cc_op: "vc" is cond_op=7 { tmp:1 = !OV; export tmp; } +cc_op: "hi" is cond_op=8 { tmp:1 = CY && (!ZR); export tmp; } +cc_op: "ls" is cond_op=9 { tmp:1 = (!CY) || ZR; export tmp; } +cc_op: "ge" is cond_op=10 { tmp:1 = (NG==OV); export tmp; } +cc_op: "lt" is cond_op=11 { tmp:1 = (NG!=OV); export tmp; } +cc_op: "gt" is cond_op=12 { tmp:1 = (!ZR) && (NG==OV); export tmp; } +cc_op: "le" is cond_op=13 { tmp:1 = ZR || (NG!=OV); export tmp; } +cc_op: "al" is cond_op=14 { export 1:1; } +cc_op: "nv" is cond_op=15 { export 1:1; } + +CondOp: cc_op is cc_op { export cc_op; } + +inv_cc_op: "eq" is cond_op=1 { export ZR; } +inv_cc_op: "ne" is cond_op=0 { tmp:1 = !ZR; export tmp; } +inv_cc_op: "cs" is cond_op=3 { export CY; } +inv_cc_op: "cc" is cond_op=2 { tmp:1 = !CY; export tmp; } +inv_cc_op: "mi" is cond_op=5 { export NG; } +inv_cc_op: "pl" is cond_op=4 { tmp:1 = !NG; export tmp; } +inv_cc_op: "vs" is cond_op=7 { export OV; } +inv_cc_op: "vc" is cond_op=6 { tmp:1 = !OV; export tmp; } +inv_cc_op: "hi" is cond_op=9 { tmp:1 = CY && (!ZR); export tmp; } +inv_cc_op: "ls" is cond_op=8 { tmp:1 = (!CY) || ZR; export tmp; } +inv_cc_op: "ge" is cond_op=11 { tmp:1 = (NG==OV); export tmp; } +inv_cc_op: "lt" is cond_op=10 { tmp:1 = (NG!=OV); export tmp; } +inv_cc_op: "gt" is cond_op=13 { tmp:1 = (!ZR) && (NG==OV); export tmp; } +inv_cc_op: "le" is cond_op=12 { tmp:1 = ZR || (NG!=OV); export tmp; } +inv_cc_op: "al" is cond_op=15 { export 1:1; } +inv_cc_op: "nv" is cond_op=14 { export 1:1; } + +InvCondOp: inv_cc_op is inv_cc_op { export inv_cc_op; } + +SBIT_CZNO: is b_29=0 { } # Do nothing to the flag bits +SBIT_CZNO: "s" is b_29=1 { CY = tmpCY; ZR = tmpZR; NG = tmpNG; OV = tmpOV; } + +Imm_uimm_exact8: "#"^value is aa_extreg_shift [ value = 8 << aa_extreg_shift; ] { export *[const]:4 value; } +Imm_uimm_exact16: "#"^value is aa_extreg_shift [ value = 8 << aa_extreg_shift; ] { export *[const]:4 value; } +Imm_uimm_exact32: "#"^value is aa_extreg_shift [ value = 8 << aa_extreg_shift; ] { export *[const]:4 value; } + +Imm_shr_imm8: "#"^val is b_1922 & b_1618 [ val = (8*2) - (b_1922 << 3 | b_1618); ] { export *[const]:4 val; } +Imm_shr_imm16: "#"^val is b_1922 & b_1618 [ val = (16*2) - (b_1922 << 3 | b_1618); ] { export *[const]:4 val; } +Imm_shr_imm32: "#"^val is b_1922 & b_1618 [ val = (32*2) - (b_1922 << 3 | b_1618); ] { export *[const]:4 val; } +Imm_shr_imm64: "#"^val is b_1922 & b_1618 [ val = (64*2) - (b_1922 << 3 | b_1618); ] { export *[const]:4 val; } + +NZCVImm_uimm4: "#"^b_0003 is b_0003 { export *[const]:1 b_0003; } +UImm5: "#"^b_1620 is b_1620 { export *[const]:4 b_1620; } +UImm6: "#"^b_1520 is b_1520 { export *[const]:4 b_1520; } + +CRm_uimm4: "#"^b_0811 is b_0811 { export *[const]:1 b_0811; } + +CRm_uimm4_def15: "#"^b_0811 is b_0811 { export *[const]:1 b_0811; } +CRm_uimm4_def15: is b_0811=0xf { export 15:1; } + +LSB_bitfield32_imm: "#"^imm6 is b_1515=0 & imm6 { export *[const]:8 imm6; } +LSB_bitfield64_imm: "#"^imm6 is imm6 { export *[const]:8 imm6; } + +LSB_bitfield32_imm_shift: "#"^shift is b_1515=0 & imm6 [ shift = 31 - imm6; ] { export *[const]:4 shift; } +LSB_bitfield64_imm_shift: "#"^shift is imm6 [ shift = 63 - imm6; ] { export *[const]:8 shift; } + +AddrLoc14: reloc is simm14 [ reloc = inst_start + (4*simm14); ] { export *[const]:8 reloc; } + +AddrLoc19: reloc is simm19 [ reloc = inst_start + (4*simm19); ] { export *[const]:8 reloc; } + +AddrLoc26: reloc is simm26 [ reloc = inst_start + (4*simm26); ] { export *[const]:8 reloc; } + +Addr14: AddrLoc14 is AddrLoc14 { export *:8 AddrLoc14; } + +Addr19: AddrLoc19 is AddrLoc19 { export *:8 AddrLoc19; } + +Addr26: AddrLoc26 is AddrLoc26 { export *:8 AddrLoc26; } + +AdrReloff: reloff is b_31=1 & immlo & immhi [ reloff = ((inst_start) & ~0xfff) + ( ((immhi << 2) | immlo) << 12 ); ] { export *[const]:8 reloff; } +AdrReloff: reloff is b_31=0 & immlo & immhi [ reloff = (inst_start) + ( ((immhi << 2) | immlo) ); ] { export *[const]:8 reloff; } + +ImmShift32: "#"^imm12 is aa_extreg_shift=0 & imm12 { export *[const]:4 imm12; } +ImmShift32: "#"^imm12, "LSL #12" is aa_extreg_shift=1 & imm12 { tmp:4 = imm12 << 12; export tmp; } + +ImmShift64: "#"^imm12 is aa_extreg_shift=0 & imm12 { export *[const]:8 imm12; } +ImmShift64: "#"^imm12, "LSL #12" is aa_extreg_shift=1 & imm12 { tmp:8 = imm12 << 12; export tmp; } + +# TODO some instructions can't do ROR operation on immediate! + +RegShift32: Rm_GPR32, "LSL #"^imm6 is Rm_GPR32 & aa_extreg_shift = 0 & imm6 & b_1515=0 { tmp:4 = Rm_GPR32 << imm6; export tmp; } +RegShift32: Rm_GPR32 is Rm_GPR32 & aa_extreg_shift = 0 & imm6=0 { export Rm_GPR32; } +RegShift32: Rm_GPR32, "LSR #"^imm6 is Rm_GPR32 & aa_extreg_shift = 1 & imm6 & b_1515=0 { tmp:4 = Rm_GPR32 >> imm6; export tmp; } +RegShift32: Rm_GPR32, "ASR #"^imm6 is Rm_GPR32 & aa_extreg_shift = 2 & imm6 & b_1515=0 { tmp:4 = Rm_GPR32 s>> imm6; export tmp; } + +RegShift32Log: RegShift32 is aa_extreg_shift & RegShift32 { export RegShift32; } +RegShift32Log: Rm_GPR32, "ROR #"^imm6 is aa_extreg_shift=3 & Rm_GPR32 & imm6 & b_1515=0 { tmp:4 = (Rm_GPR32 >> imm6) | (Rm_GPR32 << (32 - imm6)); export tmp; } + +RegShift64: Rm_GPR64, "LSL #"^imm6 is Rm_GPR64 & aa_extreg_shift = 0 & imm6 { tmp:8 = Rm_GPR64 << imm6; export tmp; } +RegShift64: Rm_GPR64 is Rm_GPR64 & aa_extreg_shift = 0 & imm6=0 { export Rm_GPR64; } +RegShift64: Rm_GPR64, "LSR #"^imm6 is Rm_GPR64 & aa_extreg_shift = 1 & imm6 { tmp:8 = Rm_GPR64 >> imm6; export tmp; } +RegShift64: Rm_GPR64, "ASR #"^imm6 is Rm_GPR64 & aa_extreg_shift = 2 & imm6 { tmp:8 = Rm_GPR64 s>> imm6; export tmp; } + +RegShift64Log: RegShift64 is aa_extreg_shift & RegShift64 & aa_Xn & aa_Xm & imm6 { export RegShift64; } +RegShift64Log: Rm_GPR64, "ROR #"^imm6 is aa_extreg_shift=3 & Rm_GPR64 & aa_Xn & aa_Xm & imm6 { tmp:8 = (Rm_GPR64 >> imm6) | (Rm_GPR64 << (64 - imm6)); export tmp; } + +RegShiftVal32: " #"^b_1012 is aa_extreg_imm3=1 & b_1012 { export 1:4; } +RegShiftVal32: " #"^b_1012 is aa_extreg_imm3=2 & b_1012 { export 2:4; } +RegShiftVal32: " #"^b_1012 is aa_extreg_imm3=3 & b_1012 { export 3:4; } +RegShiftVal32: " #"^b_1012 is aa_extreg_imm3=4 & b_1012 { export 4:4; } +RegShiftVal32: "" is aa_extreg_imm3=0 { export 0:4; } + +LSL_Sp_Special32: Rm_GPR32, "LSL " is Rm_GPR32 & aa_extreg_imm3 { export Rm_GPR32; } +LSL_Sp_Special32: Rm_GPR32 is Rm_GPR32 & aa_extreg_imm3=0 { export Rm_GPR32; } + +ExtendReg32: Rm_GPR32, "UXTB " is Rm_GPR32 & b_2121=1 & aa_extreg_option=0 { tmp0:4 = Rm_GPR32; tmp:4 = zext(tmp0:1); export tmp; } +ExtendReg32: Rm_GPR32, "UXTH " is Rm_GPR32 & b_2121=1 & aa_extreg_option=1 { tmp0:4 = Rm_GPR32; tmp:4 = zext(tmp0:2); export tmp; } +ExtendReg32: LSL_Sp_Special32 is Rm_GPR32 & b_2121=1 & aa_extreg_option=2 & b_29=1 & (Rn=0x1f) & LSL_Sp_Special32 { export Rm_GPR32; } +ExtendReg32: LSL_Sp_Special32 is Rm_GPR32 & b_2121=1 & aa_extreg_option=2 & b_29=0 & (Rd=0x1f | Rn=0x1f) & LSL_Sp_Special32 { export Rm_GPR32; } +ExtendReg32: Rm_GPR32, "UXTW " is Rm_GPR32 & b_2121=1 & aa_extreg_option=2 { tmp:4 = Rm_GPR32; export tmp; } +ExtendReg32: Rm_GPR32, "UXTX " is Rm_GPR32 & b_2121=1 & aa_extreg_option=3 { tmp:4 = Rm_GPR32; export tmp; } +ExtendReg32: Rm_GPR32, "SXTB " is Rm_GPR32 & b_2121=1 & aa_extreg_option=4 { tmp0:4 = Rm_GPR32; tmp:4 = sext(tmp0:1); export tmp; } +ExtendReg32: Rm_GPR32, "SXTH " is Rm_GPR32 & b_2121=1 & aa_extreg_option=5 { tmp0:4 = Rm_GPR32; tmp:4 = sext(tmp0:2); export tmp; } + +ExtendReg32: Rm_GPR32, "SXTW " is Rm_GPR32 & b_2121=1 & aa_extreg_option=6 { tmp:4 = Rm_GPR32; export tmp; } +ExtendReg32: Rm_GPR32, "SXTX " is Rm_GPR32 & b_2121=1 & aa_extreg_option=7 { tmp:4 = Rm_GPR32; export tmp; } + +ExtendRegShift32: ExtendReg32^RegShiftVal32 is aa_extreg_shift = 0 & aa_extreg_option & aa_extreg_imm3 & ExtendReg32 & RegShiftVal32 { tmp:4 = ExtendReg32; tmp = tmp << RegShiftVal32; export tmp; } +ExtendRegShift32: ExtendReg32 is Rm_GPR32 & aa_extreg_shift = 0 & aa_extreg_option=2 & aa_extreg_imm3=0 & ExtendReg32 & RegShiftVal32 { export Rm_GPR32; } +ExtendRegShift32: ExtendReg32 is Rm_GPR32 & aa_extreg_shift = 0 & aa_extreg_option=3 & aa_extreg_imm3=0 & ExtendReg32 & RegShiftVal32 { export Rm_GPR32; } +ExtendRegShift32: ExtendReg32 is Rm_GPR32 & aa_extreg_shift = 0 & aa_extreg_option=6 & aa_extreg_imm3=0 & ExtendReg32 & RegShiftVal32 { export Rm_GPR32; } +ExtendRegShift32: ExtendReg32 is Rm_GPR32 & aa_extreg_shift = 0 & aa_extreg_option=7 & aa_extreg_imm3=0 & ExtendReg32 & RegShiftVal32 { export Rm_GPR32; } + +Imm12_addsubimm_operand_i32_negimm_lsl0: ImmShift32 is ImmShift32 { export ImmShift32; } +Imm12_addsubimm_operand_i32_negimm_lsl12: ImmShift32 is ImmShift32 { export ImmShift32; } +Imm12_addsubimm_operand_i32_posimm_lsl0: ImmShift32 is ImmShift32 { export ImmShift32; } +Imm12_addsubimm_operand_i32_posimm_lsl12: ImmShift32 is ImmShift32 { export ImmShift32; } +Imm12_addsubimm_operand_i64_negimm_lsl0: ImmShift64 is ImmShift64 { export ImmShift64; } +Imm12_addsubimm_operand_i64_negimm_lsl12: ImmShift64 is ImmShift64 { export ImmShift64; } +Imm12_addsubimm_operand_i64_posimm_lsl0: ImmShift64 is ImmShift64 { export ImmShift64; } +Imm12_addsubimm_operand_i64_posimm_lsl12: ImmShift64 is ImmShift64 { export ImmShift64; } + +RegShiftVal64: " #"^b_1012 is aa_extreg_imm3=1 & b_1012 { export 1:8; } +RegShiftVal64: " #"^b_1012 is aa_extreg_imm3=2 & b_1012 { export 2:8; } +RegShiftVal64: " #"^b_1012 is aa_extreg_imm3=3 & b_1012 { export 3:8; } +RegShiftVal64: " #"^b_1012 is aa_extreg_imm3=4 & b_1012 { export 4:8; } +RegShiftVal64: "" is aa_extreg_imm3=0 { export 0:8; } + +LSL_Sp_Special64: Rm_GPR64, "LSL " is Rm_GPR64 & aa_extreg_imm3 { export Rm_GPR64; } +LSL_Sp_Special64: Rm_GPR64 is Rm_GPR64 & aa_extreg_imm3=0 { export Rm_GPR64; } + +ExtendReg64: Rm_GPR32, "UXTB " is Rm_GPR32 & b_2121=1 & aa_extreg_option=0 { tmp0:4 = Rm_GPR32; tmp:8 = zext(tmp0:1); export tmp; } +ExtendReg64: Rm_GPR32, "UXTH " is Rm_GPR32 & b_2121=1 & aa_extreg_option=1 { tmp0:4 = Rm_GPR32; tmp:8 = zext(tmp0:2); export tmp; } +ExtendReg64: Rm_GPR32, "UXTW " is Rm_GPR32 & b_2121=1 & aa_extreg_option=2 { tmp:8 = zext(Rm_GPR32); export tmp; } +ExtendReg64: LSL_Sp_Special64 is Rm_GPR64 & b_2121=1 & aa_extreg_option=3 & b_29=1 & b_25=1 & (Rn=0x1f) & LSL_Sp_Special64 { tmp:8 = Rm_GPR64; export tmp; } +ExtendReg64: LSL_Sp_Special64 is Rm_GPR64 & b_2121=1 & aa_extreg_option=3 & b_29=0 & b_25=1 & (Rd=0x1f | Rn=0x1f) & LSL_Sp_Special64 { tmp:8 = Rm_GPR64; export tmp; } +ExtendReg64: Rm_GPR64, "LSL " is Rm_GPR64 & b_2121=1 & aa_extreg_option=3 & b_29 & b_25=0 { tmp:8 = Rm_GPR64; export tmp; } +ExtendReg64: Rm_GPR64, "UXTX " is Rm_GPR64 & b_2121=1 & aa_extreg_option=3 { tmp:8 = Rm_GPR64; export tmp; } +ExtendReg64: Rm_GPR32, "SXTB " is Rm_GPR32 & b_2121=1 & aa_extreg_option=4 { tmp0:4 = Rm_GPR32; tmp:8 = sext(tmp0:1); export tmp; } +ExtendReg64: Rm_GPR32, "SXTH " is Rm_GPR32 & b_2121=1 & aa_extreg_option=5 { tmp0:4 = Rm_GPR32; tmp:8 = sext(tmp0:2); export tmp; } +ExtendReg64: Rm_GPR32, "SXTW " is Rm_GPR32 & b_2121=1 & aa_extreg_option=6 { tmp:8 = sext(Rm_GPR32); export tmp; } +ExtendReg64: Rm_GPR64, "SXTX " is Rm_GPR64 & b_2121=1 & aa_extreg_option=7 { tmp:8 = Rm_GPR64; export tmp; } + +ExtendRegShift64: ExtendReg64^RegShiftVal64 +is aa_extreg_shift = 0 & aa_extreg_option & aa_extreg_imm3 & ExtendReg64 & RegShiftVal64 +{ + build ExtendReg64; + build RegShiftVal64; + tmp:8 = ExtendReg64; + tmp = tmp << RegShiftVal64; + export tmp; +} + +ExtendRegShift64: ExtendReg64 is Rm_GPR64 & aa_extreg_shift = 0 & aa_extreg_option=3 & aa_extreg_imm3=0 & ExtendReg64 & RegShiftVal64 { export Rm_GPR64; } +ExtendRegShift64: ExtendReg64 is Rm_GPR64 & aa_extreg_shift = 0 & aa_extreg_option=7 & aa_extreg_imm3=0 & ExtendReg64 & RegShiftVal64 { export Rm_GPR64; } + +UnscPriv: "u" is b_1011=0 { } +UnscPriv: "t" is b_1011=2 { } + +# Simple register load or store +addrReg: "["^Rn_GPR64xsp^"]" is Rn_GPR64xsp { export Rn_GPR64xsp; } + +# Scaled Offset +addrUIMM: "["^Rn_GPR64xsp, "#"^pimm^"]" is size.ldstr=0 & b_2729=7 & v & b_2425=1 & b_2323 & Rn_GPR64xsp & imm12 [ pimm = imm12 << 0; ] { tmp:8 = Rn_GPR64xsp + pimm; export tmp; } +addrUIMM: "["^Rn_GPR64xsp, "#"^pimm^"]" is size.ldstr=1 & b_2729=7 & v & b_2425=1 & b_2323 & Rn_GPR64xsp & imm12 [ pimm = imm12 << 1; ] { tmp:8 = Rn_GPR64xsp + pimm; export tmp; } +addrUIMM: "["^Rn_GPR64xsp, "#"^pimm^"]" is size.ldstr=2 & b_2729=7 & v & b_2425=1 & b_2323 & Rn_GPR64xsp & imm12 [ pimm = imm12 << 2; ] { tmp:8 = Rn_GPR64xsp + pimm; export tmp; } +addrUIMM: "["^Rn_GPR64xsp, "#"^pimm^"]" is size.ldstr=3 & b_2729=7 & v & b_2425=1 & b_2323 & Rn_GPR64xsp & imm12 [ pimm = imm12 << 3; ] { tmp:8 = Rn_GPR64xsp + pimm; export tmp; } + +addrUIMM: "["^Rn_GPR64xsp, "#"^pimm^"]" is size.ldstr=0 & b_2729=7 & v=1 & b_2425=1 & b_2323=1 & Rn_GPR64xsp & imm12 [ pimm = imm12 << 4; ] { tmp:8 = Rn_GPR64xsp + pimm; export tmp; } +addrUIMM: "["^Rn_GPR64xsp^"]" is size.ldstr=0 & b_2729=7 & v & b_2425=1 & b_2323 & Rn_GPR64xsp & imm12=0 { tmp:8 = Rn_GPR64xsp; export tmp; } +addrUIMM: "["^Rn_GPR64xsp^"]" is size.ldstr=1 & b_2729=7 & v & b_2425=1 & b_2323 & Rn_GPR64xsp & imm12=0 { tmp:8 = Rn_GPR64xsp; export tmp; } +addrUIMM: "["^Rn_GPR64xsp^"]" is size.ldstr=2 & b_2729=7 & v & b_2425=1 & b_2323 & Rn_GPR64xsp & imm12=0 { tmp:8 = Rn_GPR64xsp; export tmp; } +addrUIMM: "["^Rn_GPR64xsp^"]" is size.ldstr=3 & b_2729=7 & v & b_2425=1 & b_2323 & Rn_GPR64xsp & imm12=0 { tmp:8 = Rn_GPR64xsp; export tmp; } +addrUIMM: "["^Rn_GPR64xsp^"]" is size.ldstr=0 & b_2729=7 & v=1 & b_2425=1 & b_2323=1 & Rn_GPR64xsp & imm12=0 { tmp:8 = Rn_GPR64xsp; export tmp; } + +# Address Reg + signed offset -256 to 255 +addr_SIMM9: "["^Rn_GPR64xsp, "#"^simm9^"]" is Rn_GPR64xsp & simm9 { tmp:8 = Rn_GPR64xsp + simm9; export tmp; } +addr_SIMM9: "["^Rn_GPR64xsp^"]" is Rn_GPR64xsp & simm9=0 { tmp:8 = Rn_GPR64xsp; export tmp; } + +addrRegShift64: "#"^val is size.ldstr=0 & v=0 & opt & b_1212=1 [ val = 0 & 0xff; ] { export *[const]:8 val; } +addrRegShift64: "" is size.ldstr=0 & v=0 & opt & b_1212=0 { export 0:8; } + +addrRegShift64: "#"^val is size.ldstr=0 & v=1 & opt=0 & b_1212=1 [ val = 0 & 0xff; ] { export *[const]:8 val; } +addrRegShift64: "" is size.ldstr=0 & v=1 & opt=0 & b_1212=0 { export 0:8; } +addrRegShift64: "#"^val is size.ldstr=0 & v=1 & opt=1 & b_1212=1 [ val = 0 & 0xff; ] { export *[const]:8 val; } +addrRegShift64: "" is size.ldstr=0 & v=1 & opt=1 & b_1212=0 { export 0:8; } +addrRegShift64: "#"^val is size.ldstr=0 & v=1 & opt=2 & b_1212 [ val = b_1212 * 4; ] { export *[const]:8 val; } +addrRegShift64: "#"^val is size.ldstr=0 & v=1 & opt=3 & b_1212 [ val = b_1212 * 4; ] { export *[const]:8 val; } + +addrRegShift64: "#"^val is size.ldstr=1 & v=0 & opt & b_1212 [ val = b_1212 * 1; ] { export *[const]:8 val; } +addrRegShift64: "#"^val is size.ldstr=1 & v=1 & opt & b_1212 [ val = b_1212 * 1; ] { export *[const]:8 val; } + +addrRegShift64: "#"^val is size.ldstr=2 & v=0 & opt & b_1212 [ val = b_1212 * 2; ] { export *[const]:8 val; } +addrRegShift64: "#"^val is size.ldstr=2 & v=1 & opt & b_1212 [ val = b_1212 * 2; ] { export *[const]:8 val; } + +addrRegShift64: "#"^val is size.ldstr=3 & v=0 & opt & b_1212 [ val = b_1212 * 3; ] { export *[const]:8 val; } +addrRegShift64: "#"^val is size.ldstr=3 & v=1 & opt & b_1212 [ val = b_1212 * 3; ] { export *[const]:8 val; } + +addrExtendRegShift64: ExtendReg64^addrRegShift64 is aa_extreg_option=2 & aa_extreg_imm3 & addrRegShift64 & ExtendReg64 { tmp:8 = ExtendReg64; tmp = tmp << addrRegShift64; export tmp; } +addrExtendRegShift64: ExtendReg64^addrRegShift64 is aa_extreg_option=3 & aa_extreg_imm3 & addrRegShift64 & ExtendReg64 { tmp:8 = ExtendReg64; tmp = tmp << addrRegShift64; export tmp; } +addrExtendRegShift64: ExtendReg64^addrRegShift64 is aa_extreg_option=6 & aa_extreg_imm3 & addrRegShift64 & ExtendReg64 { tmp:8 = ExtendReg64; tmp = tmp << addrRegShift64; export tmp; } +addrExtendRegShift64: ExtendReg64^addrRegShift64 is aa_extreg_option=7 & aa_extreg_imm3 & addrRegShift64 & ExtendReg64 { tmp:8 = ExtendReg64; tmp = tmp << addrRegShift64; export tmp; } +addrExtendRegShift64: Rm_GPR64 is Rm_GPR64 & aa_extreg_option=3 & aa_extreg_imm3=0 & ExtendReg64 { export Rm_GPR64; } +addrExtendRegShift64: Rm_GPR64 is Rm_GPR64 & aa_extreg_option=7 & aa_extreg_imm3=0 & ExtendReg64 { export Rm_GPR64; } + +# unsigned offset +addrIndexed: addrUIMM is size.ldstr & b_2729=7 & b_2425=1 & addrUIMM { export addrUIMM; } + +# unsinged offset unscaled immediate +addrIndexed: addr_SIMM9 is size.ldstr & b_2729=7 & b_2425=0 & b_2121=0 & opc.indexmode=0 & addr_SIMM9 { export addr_SIMM9; } + +# register unpriviledged +addrIndexed: addr_SIMM9 is size.ldstr & b_2729=7 & b_2425=0 & b_2121=0 & opc.indexmode=2 & addr_SIMM9 { export addr_SIMM9; } + +# post indexed wback +addrIndexed: "["^Rn_GPR64xsp^"]", "#"^simm9 +is size.ldstr & b_2729=7 & b_2425=0 & b_2121=0 & Rn_GPR64xsp & simm9 & opc.indexmode=1 +{ + tmp:8 = Rn_GPR64xsp; + Rn_GPR64xsp = Rn_GPR64xsp + simm9; + export tmp; +} + +# Register, Register offset extended +addrIndexed: "["^Rn_GPR64xsp, addrExtendRegShift64^"]" +is size.ldstr & b_2729=7 & b_2425=0 & b_2121=1 & Rn_GPR64xsp & opc.indexmode=2 & addrExtendRegShift64 +{ + tmp:8 = Rn_GPR64xsp + addrExtendRegShift64; + export tmp; +} + +# pre indexed wback +addrIndexed: "["^Rn_GPR64xsp, "#"^simm9^"]!" +is size.ldstr & b_2729=7 & b_2425=0 & b_2121=0 & Rn_GPR64xsp & simm9 & opc.indexmode=3 +{ + Rn_GPR64xsp = Rn_GPR64xsp + simm9; + export Rn_GPR64xsp; +} + +# For LDRAA/LDRAB + +# no offset (with S) +addrIndexed: "["^Rn_GPR64xsp^"]" +is size.ldstr & b_2729=7 & b_2425=0 & b_22=0 & b_2121=1 & Rn_GPR64xsp & simm9=0 & opc.indexmode=1 +{ + export Rn_GPR64xsp; +} + +# offset (with S) +addrIndexed: "["^Rn_GPR64xsp, "#"^sim^"]" +is size.ldstr & b_2729=7 & b_2425=0 & b_22 & b_2121=1 & Rn_GPR64xsp & simm9 & opc.indexmode=1 +[ sim = (b_22 * (-1<<9) | (simm9 & 0x1ff)) << 3; ] +{ + tmp:8 = Rn_GPR64xsp + sim; + export tmp; +} + +# no offset writeback (with S) +addrIndexed: "["^Rn_GPR64xsp^"]!" +is size.ldstr & b_2729=7 & b_2425=0 & b_22=0 & b_2121=1 & Rn_GPR64xsp & simm9=0 & opc.indexmode=3 +{ + export Rn_GPR64xsp; +} + +# pre indexed wback (with S) +addrIndexed: "["^Rn_GPR64xsp, "#"^sim^"]!" +is size.ldstr & b_2729=7 & b_2425=0 & b_22 & b_2121=1 & Rn_GPR64xsp & simm9 & opc.indexmode=3 +[ sim = (b_22 * (-1<<9) | (simm9 & 0x1ff)) << 3; ] +{ + Rn_GPR64xsp = Rn_GPR64xsp + sim; + export Rn_GPR64xsp; +} + +addrPairScale: pimm is b_3031=0 & v=0 & simm7 [ pimm = simm7 << 2; ] { export *[const]:8 pimm; } +addrPairScale: pimm is b_3031=0 & v=1 & simm7 [ pimm = simm7 << 2; ] { export *[const]:8 pimm; } +addrPairScale: pimm is b_3031=2 & v=0 & simm7 [ pimm = simm7 << 3; ] { export *[const]:8 pimm; } +addrPairScale: pimm is b_3031=1 & v=0 & simm7 [ pimm = simm7 << 2; ] { export *[const]:8 pimm; } +addrPairScale: pimm is b_3031=1 & v=1 & simm7 [ pimm = simm7 << 3; ] { export *[const]:8 pimm; } +addrPairScale: pimm is b_3031=2 & v=1 & simm7 [ pimm = simm7 << 4; ] { export *[const]:8 pimm; } + +# Scaled Offset +addrPairUIMM: "["^Rn_GPR64xsp, "#"^addrPairScale^"]" +is sf & Rn_GPR64xsp & addrPairScale & simm7 +{ + tmp:8 = Rn_GPR64xsp + addrPairScale; + export tmp; +} + +addrPairUIMM: "["^Rn_GPR64xsp^"]" +is sf & Rn_GPR64xsp & addrPairScale & simm7=0 +{ + tmp:8 = Rn_GPR64xsp; + export tmp; +} + +# unsigned offset +addrPairIndexed: addrPairUIMM +is b_2729=0b101 & b_2325=0b010 & addrPairUIMM +{ export addrPairUIMM; } + +# unsigned offset, non-temporal hint +addrPairIndexed: addrPairUIMM +is b_2729=0b101 & b_2325=0b000 & addrPairUIMM +{ export addrPairUIMM; } + +# post indexed wback +addrPairIndexed: "["^Rn_GPR64xsp^"]", "#"^addrPairScale +is b_2729=0b101 & b_2325=0b001 & Rn_GPR64xsp & addrPairScale +{ + tmp:8 = Rn_GPR64xsp; + Rn_GPR64xsp = Rn_GPR64xsp + addrPairScale; + export tmp; +} + +# pre indexed wback +addrPairIndexed: "["^Rn_GPR64xsp, "#"^addrPairScale^"]!" +is b_2729=0b101 & b_2325=0b011 & Rn_GPR64xsp & addrPairScale +{ + Rn_GPR64xsp = Rn_GPR64xsp + addrPairScale; + export Rn_GPR64xsp; +} + +#### Undefined behavior on writeback #### +# +# Most instructions with writeback have unpredictable behavior when their address input register Rn +# is the same register as another input, e.g. Rt. For example, LDR x1, [x1, 0x8]! has unpredictable +# behavior in the ARM spec. Similarly, STR x5, [x5], 0x28 has unpredictable behavior in the spec +# (but with slightly different possibilities for what forms that unpredictable behavior might take!). +# +# One of the few exceptions is STGP, which has no mention of unpredictable behavior. In such cases, +# it's important to read all registers before addrGranuleIndexed or addrPairGranuleIndexed takes effect, +# or pre-index writeback will modify the register values used if Rn is the same register as another R. +# +# This is an example of how to code a definition for an instruction with no unpredictable behavior: +#{ +# # save the initial register values +# data1:8 = Rt_GPR64; +# data2:8 = Rt2_GPR64; +# +# build addrPairGranuleIndexed; # may modify Rt or Rt2, so use data1/data2 instead afterward +# +# ...etc... +#} + +OPTIONAL_XM: is Rm=0b11111 { export 0:8; } # default to XZR if Xm is absent +OPTIONAL_XM: ,Rm_GPR64 is Rm_GPR64 { export Rm_GPR64; } + +addr_granuleSIMM: "["^Rn_GPR64xsp, "#"^pimm^"]" is Rn_GPR64xsp & simm9 [ pimm = simm9 << $(LOG2_TAG_GRANULE); ] { tmp:8 = Rn_GPR64xsp + ( simm9 << $(LOG2_TAG_GRANULE) ); export tmp; } +addr_granuleSIMM: "["^Rn_GPR64xsp^"]" is Rn_GPR64xsp & simm9=0 { tmp:8 = Rn_GPR64xsp; export tmp; } + +# signed offset +addrGranuleIndexed: addr_granuleSIMM is opc.indexmode=2 & addr_granuleSIMM { export addr_granuleSIMM; } + +# post indexed wback +addrGranuleIndexed: "["^Rn_GPR64xsp^"]", "#"^pimm +is Rn_GPR64xsp & simm9 & opc.indexmode=1 +[ pimm = simm9 << $(LOG2_TAG_GRANULE); ] +{ + tmp:8 = Rn_GPR64xsp; + Rn_GPR64xsp = Rn_GPR64xsp + pimm; + export tmp; +} + +# pre indexed wback +addrGranuleIndexed: "["^Rn_GPR64xsp, "#"^pimm^"]!" +is Rn_GPR64xsp & simm9 & opc.indexmode=3 +[ pimm = simm9 << $(LOG2_TAG_GRANULE); ] +{ + Rn_GPR64xsp = Rn_GPR64xsp + pimm; + tmp:8 = Rn_GPR64xsp; + export tmp; +} + +addrPairGranuleScale: pimm is simm7 [ pimm = simm7 << $(LOG2_TAG_GRANULE); ] { export *[const]:8 pimm; } + +# Scaled Offset +addrPairGranuleSIMM: "["^Rn_GPR64xsp, "#"^addrPairGranuleScale^"]" +is sf & Rn_GPR64xsp & addrPairGranuleScale & simm7 +{ + tmp:8 = Rn_GPR64xsp + addrPairGranuleScale; + export tmp; +} + +addrPairGranuleSIMM: "["^Rn_GPR64xsp^"]" +is sf & Rn_GPR64xsp & addrPairGranuleScale & simm7=0 +{ + tmp:8 = Rn_GPR64xsp; + export tmp; +} + + +# signed offset +addrPairGranuleIndexed: addrPairGranuleSIMM +is b_2729=0b101 & b_2325=0b010 & addrPairGranuleSIMM +{ export addrPairGranuleSIMM; } + +# post indexed wback +addrPairGranuleIndexed: "["^Rn_GPR64xsp^"]", "#"^addrPairGranuleScale +is b_2729=0b101 & b_2325=0b001 & Rn_GPR64xsp & addrPairGranuleScale +{ + tmp:8 = Rn_GPR64xsp; + Rn_GPR64xsp = Rn_GPR64xsp + addrPairGranuleScale; + export tmp; +} + +# pre indexed wback +addrPairGranuleIndexed: "["^Rn_GPR64xsp, "#"^addrPairGranuleScale^"]!" +is b_2729=0b101 & b_2325=0b011 & Rn_GPR64xsp & addrPairGranuleScale +{ + Rn_GPR64xsp = Rn_GPR64xsp + addrPairGranuleScale; + export Rn_GPR64xsp; +} + +# esize=32, len=5, levels=0x1f: 32 bits with b_1014+1 1s; rotate right b_1620; replicate 1 time +DecodeWMask32: "#"^wmask is b_31=0 & b_22=0 & b_15=0 & b_1014 & b_1620 +[ wmask=(((~(-1<<(b_1014+1)))*0x100000001)>>b_1620)&0xffffffff; ] +{ export * [const]:4 wmask; } + +# esize=32, len=5, levels=0x1f: 32 bits with |b_1014-b_1620|+1 1s; replicate 1 time +DecodeTMask32: "#"^tmask is b_31=0 & b_22=0 & b_15=0 & b_1014 & b_1620 +[ tmask=(~(-1<<(((b_1014-b_1620)&0x1f)+1)))&0xffffffff; ] +{ export * [const]:4 tmask; } + +# esize=16, len=4, levels=0xf: 16 bits with b_1013+1 1s; rotate right b_1619; replicate 2 times +DecodeWMask32: "#"^wmask is b_31=0 & b_22=0 & b_1415=0x2 & b_1013 & b_1619 +[ wmask=((((~(-1<<(b_1013+1)))*0x10001)>>b_1619)&0xffff)*0x10001; ] +{ export * [const]:4 wmask; } + +# esize=16, len=4, levels=0xf: 16 bits with |b_1013-b_1619|+1 1s; replicate 2 times +DecodeTMask32: "#"^tmask is b_31=0 & b_22=0 & b_1415=0x2 & b_1013 & b_1619 +[ tmask=((~(-1<<(((b_1013-b_1619)&0xf)+1)))&0xffff)*0x10001; ] +{ export * [const]:4 tmask; } + +# esize=8, len=3, levels=0x7: 8 bits with b_1012+1 1s; rotate right b_1618; replicate 4 times +DecodeWMask32: "#"^wmask is b_31=0 & b_22=0 & b_1315=0x6 & b_1012 & b_1618 +[ wmask=((((~(-1<<(b_1012+1)))*0x101)>>b_1618)&0xff)*0x101*0x10001; ] +{ export * [const]:4 wmask; } + +# esize=8, len=3, levels=0x7: 8 bits with |b_1012-b_1618|+1 1s; replicate 4 times +DecodeTMask32: "#"^tmask is b_31=0 & b_22=0 & b_1315=0x6 & b_1012 & b_1618 +[ tmask=((~(-1<<(((b_1012-b_1618)&0x7)+1)))&0xff)*0x101*0x10001; ] +{ export * [const]:4 tmask; } + +# esize=4, len=2, levels=0x3: 4 bits with b_1011+1 1s; rotate right b_1617; replicate 8 times +DecodeWMask32: "#"^wmask is b_31=0 & b_22=0 & b_1215=0xe & b_1011 & b_1617 +[ wmask=((((~(-1<<(b_1011+1)))*0x11)>>b_1617)&0xf)*0x11*0x101*0x10001; ] +{ export * [const]:4 wmask; } + +# esize=4, len=2, levels=0x3: 4 bits with |b_1011-b_1617|+1 1s; replicate 8 times +DecodeTMask32: "#"^tmask is b_31=0 & b_22=0 & b_1215=0xe & b_1011 & b_1617 +[ tmask=((~(-1<<(((b_1011-b_1617)&0x7)+1)))&0xf)*0x11*0x101*0x10001; ] +{ export * [const]:4 tmask; } + +# esize=2, len=1, levels=0x1: 2 bits with b_1010+1 1s; rotate right b_1616; replicate 16 times +DecodeWMask32: "#"^wmask is b_31=0 & b_22=0 & b_1115=0x1e & b_1010 & b_1616 +[ wmask=((((~(-1<<(b_1010+1)))*0x5)>>b_1616)&0x3)*0x5*0x11*0x101*0x10001; ] +{ export * [const]:4 wmask; } + +# esize=2, len=1, levels=0x1: 2 bits with |b_1010-b_1616|+1 1s; replicate 16 times +DecodeTMask32: "#"^tmask is b_31=0 & b_22=0 & b_1115=0x1e & b_1010 & b_1616 +[ tmask=((~(-1<<(((b_1010-b_1616)&0x1)+1)))&0x3)*0x5*0x11*0x101*0x10001; ] +{ export * [const]:4 tmask; } + +# esize=64, len=6, levels=0x3f: 64 bits with b_1015+1 1s; rotate right b_1621; repeat 1 time +# can't rotate 64 bits by multiplying, and can't shift by 64 bits all at once +DecodeWMask64: "#"^wmask is b_31=1 & b_22=1 & b_1015 & b_1621 +[ wmask=((~((-1<>b_1621)|((~((-1<>b_1620)&0xffffffff)*0x100000001; ] +{ export * [const]:8 wmask; } + +# esize=32, len=5, levels=0x1f: 32 bits with |b_1014-b_1620|+1 1s; replicate 2 times +DecodeTMask64: "#"^tmask is b_31=1 & b_22=0 & b_15=0 & b_1014 & b_1620 +[ tmask=((~(-1<<(((b_1014-b_1620)&0x1f)+1)))&0xffffffff)*0x100000001; ] +{ export * [const]:8 tmask; } + +# returned 0xffcfffdefcfffcf +# shouldbe 0xffcfffcfffcfffcf +# esize=16, len=4, levels=0xf: 16 bits with b_1013+1 1s; rotate right b_1619; replicate 4 times +DecodeWMask64: "#"^wmask is b_31=1 & b_22=0 & b_1415=0x2 & b_1013 & b_1619 +[ wmask=((((~(-1<<(b_1013+1)))*0x10001)>>b_1619)&0xffff)*0x10001*0x100000001; ] +{ export * [const]:8 wmask; } + +# esize=16, len=4, levels=0xf: 16 bits with |b_1013-b_1619|+1 1s; replicate 4 times +DecodeTMask64: "#"^tmask is b_31=1 & b_22=0 & b_1415=0x2 & b_1013 & b_1619 +[ tmask=((~(-1<<(((b_1013-b_1619)&0xf)+1)))&0xffff)*0x10001*0x100000001; ] +{ export * [const]:8 tmask; } + +# esize=8, len=3, levels=0x7: 8 bits with b_1012+1 1s; rotate right b_1618; replicate 8 times +DecodeWMask64: "#"^wmask is b_31=1 & b_22=0 & b_1315=0x6 & b_1012 & b_1618 +[ wmask=((((~(-1<<(b_1012+1)))*0x101)>>b_1618)&0xff)*0x101*0x10001*0x100000001; ] +{ export * [const]:8 wmask; } + +# esize=8, len=3, levels=0x7: 8 bits with |b_1012-b_1618|+1 1s; replicate 8 times +DecodeTMask64: "#"^tmask is b_31=1 & b_22=0 & b_1315=0x6 & b_1012 & b_1618 +[ tmask=((~(-1<<(((b_1012-b_1618)&0x7)+1)))&0xff)*0x101*0x10001*0x100000001; ] +{ export * [const]:8 tmask; } + +# esize=4, len=2, levels=0x3: 4 bits with b_1011+1 1s; rotate right b_1617; replicate 16 times +DecodeWMask64: "#"^wmask is b_31=1 & b_22=0 & b_1215=0xe & b_1011 & b_1617 +[ wmask=((((~(-1<<(b_1011+1)))*0x11)>>b_1617)&0xf)*0x11*0x101*0x10001*0x100000001; ] +{ export * [const]:8 wmask; } + +# esize=4, len=2, levels=0x3: 4 bits with |b_1011-b_1617|+1 1s; replicate 16 times +DecodeTMask64: "#"^tmask is b_31=1 & b_22=0 & b_1215=0xe & b_1011 & b_1617 +[ tmask=((~(-1<<(((b_1011-b_1617)&0x3)+1)))&0xf)*0x11*0x101*0x10001*0x100000001; ] +{ export * [const]:8 tmask; } + +# esize=2, len=1, levels=0x1: 2 bits with b_1010+1 1s; rotate right b_1616; replicate 32 times +DecodeWMask64: "#"^wmask is b_31=1 & b_22=0 & b_1115=0x1e & b_1010 & b_1616 +[ wmask=((((~((-1)<<(b_1010+1)))*0x5)>>b_1616)&0x3)*0x5*0x11*0x101*0x10001*0x100000001; ] +{ export * [const]:8 wmask; } + +# esize=2, len=1, levels=0x1: 2 bits with |b_1010-b_1616|+1 1s; replicate 32 times +DecodeTMask64: "#"^tmask is b_31=1 & b_22=0 & b_1115=0x1e & b_1010 & b_1616 +[ tmask=((~(-1<<(((b_1010-b_1616)&0x1)+1)))&0x3)*0x5*0x11*0x101*0x10001*0x100000001; ] +{ export * [const]:8 tmask; } + +ImmRConst32: "#"^ImmR is ImmR { export *[const]:4 ImmR; } +ImmRConst64: "#"^ImmR is ImmR { export *[const]:8 ImmR; } + +ImmSConst32: "#"^ImmS is ImmS { export *[const]:4 ImmS; } +ImmSConst64: "#"^ImmS is ImmS { export *[const]:8 ImmS; } + +ImmR_bitfield64_imm: "#"^ImmR is ImmR & DecodeWMask64 { export DecodeWMask64; } +ImmR_bitfield32_imm: "#"^ImmR is ImmR & DecodeWMask32 { export DecodeWMask32; } + +ImmS_bitfield64_imm: "#"^ImmS is ImmS & DecodeTMask64 { export DecodeTMask64; } +ImmS_bitfield32_imm: "#"^ImmS is ImmS & DecodeTMask32 { export DecodeTMask32; } + +abcdefgh: "#"^imm is n_uimm8H & n_uimm8L [ imm = ((n_uimm8H << 5 | n_uimm8L)); ] { export *[const]:8 imm; } + +repl000: "#"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((n_uimm8H << 5 | n_uimm8L) << 32) | ((n_uimm8H << 5 | n_uimm8L)); ] { export *[const]:8 imm; } +repl001: "#"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((n_uimm8H << 5 | n_uimm8L) << 40) | ((n_uimm8H << 5 | n_uimm8L) << 8); ] { export *[const]:8 imm; } +repl010: "#"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((n_uimm8H << 5 | n_uimm8L) << 48) | ((n_uimm8H << 5 | n_uimm8L) << 16); ] { export *[const]:8 imm; } +repl011: "#"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((n_uimm8H << 5 | n_uimm8L) << 56) | ((n_uimm8H << 5 | n_uimm8L) << 24); ] { export *[const]:8 imm; } +repl100: "#"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((n_uimm8H << 5 | n_uimm8L) << 48) | ((n_uimm8H << 5 | n_uimm8L) << 32) | ((n_uimm8H << 5 | n_uimm8L) << 16) | ((n_uimm8H << 5 | n_uimm8L)); ] { export *[const]:8 imm; } +repl101: "#"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((n_uimm8H << 5 | n_uimm8L) << 56) | ((n_uimm8H << 5 | n_uimm8L) << 40) | ((n_uimm8H << 5 | n_uimm8L) << 24) | ((n_uimm8H << 5 | n_uimm8L) << 8); ] { export *[const]:8 imm; } +repl1100: "#"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((((n_uimm8H << 5 | n_uimm8L) << 8) | 0xff) << 32) | (((n_uimm8H << 5 | n_uimm8L) << 8) | 0xff); ] { export *[const]:8 imm; } +repl1101: "#"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((((n_uimm8H << 5 | n_uimm8L) << 16) | 0xffff) << 32) | (((n_uimm8H << 5 | n_uimm8L) << 16) | 0xffff); ] { export *[const]:8 imm; } +repl11100: "#"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((n_uimm8H << 5 | n_uimm8L) << 56) | ((n_uimm8H << 5 | n_uimm8L) << 48) | ((n_uimm8H << 5 | n_uimm8L) << 40) | ((n_uimm8H << 5 | n_uimm8L) << 32) | ((n_uimm8H << 5 | n_uimm8L) << 24) | ((n_uimm8H << 5 | n_uimm8L) << 16) | ((n_uimm8H << 5 | n_uimm8L) << 8) | (n_uimm8H << 5 | n_uimm8L); ] { export *[const]:8 imm; } +repl11101: "#"^imm is abcdefgh & b_18 & b_17 & b_16 & b_09 & b_08 & b_07 & b_06 & b_05 [ imm = ((b_18 * 0xff) << 56) | ((b_17 * 0xff) << 48) | ((b_16 * 0xff) << 40) | ((b_09 * 0xff) << 32) | ((b_08 * 0xff) << 24) | ((b_07 * 0xff) << 16) | ((b_06 * 0xff) << 8) | (b_05 * 0xff); ] { export *[const]:8 imm; } +repl11110: "#"^imm is abcdefgh & b_18 & b_17 & b_16 & b_09 & b_08 & b_07 & b_06 & b_05 [ imm = (b_18 << 31) | ((b_17 $xor 1) << 30) | ((b_17 * 0x1f) << 25) | (b_16 << 24) | (b_09 << 23) | (b_08 << 22) | (b_07 << 21) | (b_06 << 20) | (b_05 << 19); ] { tmp:8 = imm; tmp = (tmp << 32) | tmp; export tmp; } +repl11111: "#"^imm is abcdefgh & b_18 & b_17 & b_16 & b_09 & b_08 & b_07 & b_06 & b_05 [ imm = (b_18 << 63) | ((b_17 $xor 1) << 62) | ((b_17 * 0xff) << 54) | (b_16 << 53) | (b_09 << 52) | (b_08 << 51) | (b_07 << 50) | (b_06 << 49) | (b_05 << 48); ] { tmp:8 = imm; export tmp; } + +Imm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0x0 & b_29=0 & repl000 { export repl000; } +Imm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0x1 & b_29=0 & repl000 { export repl000; } +Imm_neon_uimm8Shift: abcdefgh^", LSL #8" is abcdefgh & cmode=0x2 & b_29=0 & repl001 { export repl001; } +Imm_neon_uimm8Shift: abcdefgh^", LSL #8" is abcdefgh & cmode=0x3 & b_29=0 & repl001 { export repl001; } +Imm_neon_uimm8Shift: abcdefgh^", LSL #16" is abcdefgh & cmode=0x4 & b_29=0 & repl010 { export repl010; } +Imm_neon_uimm8Shift: abcdefgh^", LSL #16" is abcdefgh & cmode=0x5 & b_29=0 & repl010 { export repl010; } +Imm_neon_uimm8Shift: abcdefgh^", LSL #24" is abcdefgh & cmode=0x6 & b_29=0 & repl011 { export repl011; } +Imm_neon_uimm8Shift: abcdefgh^", LSL #24" is abcdefgh & cmode=0x7 & b_29=0 & repl011 { export repl011; } +Imm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0x8 & b_29=0 & repl100 { export repl100; } +Imm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0x9 & b_29=0 & repl100 { export repl100; } +Imm_neon_uimm8Shift: abcdefgh^", LSL #8" is abcdefgh & cmode=0xa & b_29=0 & repl101 { export repl101; } +Imm_neon_uimm8Shift: abcdefgh^", LSL #8" is abcdefgh & cmode=0xb & b_29=0 & repl101 { export repl101; } +Imm_neon_uimm8Shift: abcdefgh^", MSL #8" is abcdefgh & cmode=0xc & b_29=0 & repl1100 { export repl1100; } +Imm_neon_uimm8Shift: abcdefgh^", MSL #16" is abcdefgh & cmode=0xd & b_29=0 & repl1101 { export repl1101; } +Imm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0xe & b_29=0 & repl11100 { export repl11100; } +Imm_neon_uimm8Shift: repl11101 is abcdefgh & cmode=0xe & b_29=1 & repl11101 { export repl11101; } # MOVI 64 +Imm_neon_uimm8Shift: repl11110 is abcdefgh & cmode=0xf & b_29=0 & repl11110 { export repl11110; } # FMOV +Imm_neon_uimm8Shift: repl11111 is abcdefgh & cmode=0xf & b_29=1 & repl11111 { export repl11111; } # FMOV + +Imm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0x1 & b_29=1 & repl000 { export repl000; } # BIC32 +Imm_neon_uimm8Shift: abcdefgh^", LSL 8" is abcdefgh & cmode=0x3 & b_29=1 & repl001 { export repl001; } +Imm_neon_uimm8Shift: abcdefgh^", LSL 16" is abcdefgh & cmode=0x5 & b_29=1 & repl010 { export repl010; } +Imm_neon_uimm8Shift: abcdefgh^", LSL 24" is abcdefgh & cmode=0x7 & b_29=1 & repl011 { export repl011; } # BIC16 +Imm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0x9 & b_29=1 & repl000 { export repl000; } +Imm_neon_uimm8Shift: abcdefgh^", LSL 8" is abcdefgh & cmode=0xb & b_29=1 & repl001 { export repl001; } + +Imm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0x0 & b_29=1 & repl000 { export repl000; } # MVNI +Imm_neon_uimm8Shift: abcdefgh^", LSL 8" is abcdefgh & cmode=0x2 & b_29=1 & repl001 { export repl001; } +Imm_neon_uimm8Shift: abcdefgh^", LSL 16" is abcdefgh & cmode=0x4 & b_29=1 & repl010 { export repl010; } +Imm_neon_uimm8Shift: abcdefgh^", LSL 24" is abcdefgh & cmode=0x6 & b_29=1 & repl011 { export repl011; } +Imm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0x8 & b_29=1 & repl000 { export repl000; } # MVNI +Imm_neon_uimm8Shift: abcdefgh^", LSL 8" is abcdefgh & cmode=0xa & b_29=1 & repl001 { export repl001; } +Imm_neon_uimm8Shift: abcdefgh^", MSL 8" is abcdefgh & cmode=0xc & b_29=1 & repl1100 { export repl1100; } # MVNI +Imm_neon_uimm8Shift: abcdefgh^", MSL 16" is abcdefgh & cmode=0xd & b_29=1 & repl1101 { export repl1101; } + +vIndex: val is b_2222=0 & b_2121 & b_1111 [ val = b_1111 << 1 | b_2121; ] { export *[const]:8 val; } +vIndex: val is b_2222=1 & b_2121=0 & b_1111 [ val = b_1111 & 0x1; ] { export *[const]:8 val; } + +vIndexHLM: val is b_2223=2 & b_2121 & b_1111 [ val = b_1111 << 1 | b_2121; ] { export *[const]:8 val; } +vIndexHLM: val is b_2223=1 & b_2121 & b_1111 & b_2020 [ val = b_1111 << 2 | b_2121 << 1 | b_2020; ] { export *[const]:8 val; } +vIndexHLM: val is b_2223=0 & b_2121 & b_1111 & b_2020 [ val = b_1111 << 2 | b_2121 << 1 | b_2020; ] { export *[const]:8 val; } + +vIndexHL: val is b_2223=0b01 & b_21 & b_11 [ val = b_11 << 1 | b_21; ] { export *[const]:8 val; } +vIndexHL: b_11 is b_2223=0b10 & b_11 { export *[const]:8 b_11; } + +@if DATA_ENDIAN == "little" +Re_VPR128.B.sel: Re_VPR128, val is Re_VPR128 & b_2222=0 & b_2121 & b_1111 [ val = 0x5000 + 32*Re_VPR128 + b_1111 * 2 + b_2121; ] { export *[register]:1 val; } +Re_VPR128.B.sel: Re_VPR128, val is Re_VPR128 & b_2222=1 & b_2121=0 & b_1111 [ val = 0x5000 + 32*Re_VPR128 + b_1111; ] { export *[register]:1 val; } +Re_VPR128.S.sel: Re_VPR128, val is Re_VPR128 & b_2222=0 & b_2121 & b_1111 [ val = 0x5000 + 32*Re_VPR128 + (b_1111 * 2 + b_2121) * 4; ] { export *[register]:4 val; } +Re_VPR128.S.sel: Re_VPR128, val is Re_VPR128 & b_2222=1 & b_2121=0 & b_1111 [ val = 0x5000 + 32*Re_VPR128 + b_1111 * 4; ] { export *[register]:4 val; } +Re_VPR128.D.sel: Re_VPR128, val is Re_VPR128 & b_2222=0 & b_2121 & b_1111 [ val = 0x5000 + 32*Re_VPR128 + (b_1111 * 2 + b_2121) * 8; ] { export *[register]:8 val; } +Re_VPR128.D.sel: Re_VPR128, val is Re_VPR128 & b_2222=1 & b_2121=0 & b_1111 [ val = 0x5000 + 32*Re_VPR128 + b_1111 * 8; ] { export *[register]:8 val; } +@else +Re_VPR128.B.sel: Re_VPR128, val is Re_VPR128 & b_2222=0 & b_2121 & b_1111 [ val = 0x501f + 32*Re_VPR128 - b_1111 * 2 - b_2121; ] { export *[register]:1 val; } +Re_VPR128.B.sel: Re_VPR128, val is Re_VPR128 & b_2222=1 & b_2121=0 & b_1111 [ val = 0x501f + 32*Re_VPR128 - b_1111; ] { export *[register]:1 val; } +Re_VPR128.S.sel: Re_VPR128, val is Re_VPR128 & b_2222=0 & b_2121 & b_1111 [ val = 0x501c + 32*Re_VPR128 - (b_1111 * 2 + b_2121) * 4; ] { export *[register]:4 val; } +Re_VPR128.S.sel: Re_VPR128, val is Re_VPR128 & b_2222=1 & b_2121=0 & b_1111 [ val = 0x501c + 32*Re_VPR128 - b_1111 * 4; ] { export *[register]:4 val; } +Re_VPR128.D.sel: Re_VPR128, val is Re_VPR128 & b_2222=0 & b_2121 & b_1111 [ val = 0x5018 + 32*Re_VPR128 - (b_1111 * 2 + b_2121) * 8; ] { export *[register]:8 val; } +Re_VPR128.D.sel: Re_VPR128, val is Re_VPR128 & b_2222=1 & b_2121=0 & b_1111 [ val = 0x5018 + 32*Re_VPR128 - b_1111 * 8; ] { export *[register]:8 val; } +@endif + +Re_VPR128.B.vIndex: Re_VPR128.B^"["^vIndex^"]" is Re_VPR128.B & vIndex & Re_VPR128.B.sel { export Re_VPR128.B.sel; } +Re_VPR128.S.vIndex: Re_VPR128.S^"["^vIndex^"]" is Re_VPR128.S & vIndex & Re_VPR128.S.sel { export Re_VPR128.S.sel; } +Re_VPR128.D.vIndex: Re_VPR128.D^"["^vIndex^"]" is Re_VPR128.D & vIndex & Re_VPR128.D.sel { export Re_VPR128.D.sel; } + +@if DATA_ENDIAN == "little" +Rd_VPR128.B.sel: Rd_VPR128, val is Rd_VPR128 & imm_neon_uimm4 [ val = 0x5000 + 32*Rd_VPR128 + imm_neon_uimm4; ] { export *[register]:1 val; } +Rd_VPR128.H.sel: Rd_VPR128, val is Rd_VPR128 & imm_neon_uimm3 [ val = 0x5000 + 32*Rd_VPR128 + 2*imm_neon_uimm3; ] { export *[register]:2 val; } +Rd_VPR128.S.sel: Rd_VPR128, val is Rd_VPR128 & imm_neon_uimm2 [ val = 0x5000 + 32*Rd_VPR128 + 4*imm_neon_uimm2; ] { export *[register]:4 val; } +Rd_VPR128.D.sel: Rd_VPR128, val is Rd_VPR128 & imm_neon_uimm1 [ val = 0x5000 + 32*Rd_VPR128 + 8*imm_neon_uimm1; ] { export *[register]:8 val; } +@else +Rd_VPR128.B.sel: Rd_VPR128, val is Rd_VPR128 & imm_neon_uimm4 [ val = 0x501f + 32*Rd_VPR128 - imm_neon_uimm4; ] { export *[register]:1 val; } +Rd_VPR128.H.sel: Rd_VPR128, val is Rd_VPR128 & imm_neon_uimm3 [ val = 0x501e + 32*Rd_VPR128 - 2*imm_neon_uimm3; ] { export *[register]:2 val; } +Rd_VPR128.S.sel: Rd_VPR128, val is Rd_VPR128 & imm_neon_uimm2 [ val = 0x501c + 32*Rd_VPR128 - 4*imm_neon_uimm2; ] { export *[register]:4 val; } +Rd_VPR128.D.sel: Rd_VPR128, val is Rd_VPR128 & imm_neon_uimm1 [ val = 0x5018 + 32*Rd_VPR128 - 8*imm_neon_uimm1; ] { export *[register]:8 val; } +@endif +Rd_VPR128.B.imm_neon_uimm4: Rd_VPR128.B^"["^imm_neon_uimm4^"]" is Rd_VPR128.B & imm_neon_uimm4 & Rd_VPR128.B.sel { export Rd_VPR128.B.sel; } +Rd_VPR128.H.imm_neon_uimm3: Rd_VPR128.H^"["^imm_neon_uimm3^"]" is Rd_VPR128.H & imm_neon_uimm3 & Rd_VPR128.H.sel { export Rd_VPR128.H.sel; } +Rd_VPR128.S.imm_neon_uimm2: Rd_VPR128.S^"["^imm_neon_uimm2^"]" is Rd_VPR128.S & imm_neon_uimm2 & Rd_VPR128.S.sel { export Rd_VPR128.S.sel; } +Rd_VPR128.D.imm_neon_uimm1: Rd_VPR128.D^"["^imm_neon_uimm1^"]" is Rd_VPR128.D & imm_neon_uimm1 & Rd_VPR128.D.sel { export Rd_VPR128.D.sel; } + +@if DATA_ENDIAN == "little" +Rn_VPR128.B.selN: Rn_VPR128, val is Rn_VPR128 & immN_neon_uimm4 [ val = 0x5000 + 32*Rn_VPR128 + immN_neon_uimm4; ] { export *[register]:1 val; } +Rn_VPR128.H.selN: Rn_VPR128, val is Rn_VPR128 & immN_neon_uimm3 [ val = 0x5000 + 32*Rn_VPR128 + 2*immN_neon_uimm3; ] { export *[register]:2 val; } +Rn_VPR128.S.selN: Rn_VPR128, val is Rn_VPR128 & immN_neon_uimm2 [ val = 0x5000 + 32*Rn_VPR128 + 4*immN_neon_uimm2; ] { export *[register]:4 val; } +Rn_VPR128.D.selN: Rn_VPR128, val is Rn_VPR128 & immN_neon_uimm1 [ val = 0x5000 + 32*Rn_VPR128 + 8*immN_neon_uimm1; ] { export *[register]:8 val; } +@else +Rn_VPR128.B.selN: Rn_VPR128, val is Rn_VPR128 & immN_neon_uimm4 [ val = 0x501f + 32*Rn_VPR128 - immN_neon_uimm4; ] { export *[register]:1 val; } +Rn_VPR128.H.selN: Rn_VPR128, val is Rn_VPR128 & immN_neon_uimm3 [ val = 0x501e + 32*Rn_VPR128 - 2*immN_neon_uimm3; ] { export *[register]:2 val; } +Rn_VPR128.S.selN: Rn_VPR128, val is Rn_VPR128 & immN_neon_uimm2 [ val = 0x501c + 32*Rn_VPR128 - 4*immN_neon_uimm2; ] { export *[register]:4 val; } +Rn_VPR128.D.selN: Rn_VPR128, val is Rn_VPR128 & immN_neon_uimm1 [ val = 0x5018 + 32*Rn_VPR128 - 8*immN_neon_uimm1; ] { export *[register]:8 val; } +@endif +Rn_VPR128.B.immN_neon_uimm4: Rn_VPR128.B^"["^immN_neon_uimm4^"]" is Rn_VPR128.B & immN_neon_uimm4 & Rn_VPR128.B.selN { export Rn_VPR128.B.selN; } +Rn_VPR128.H.immN_neon_uimm3: Rn_VPR128.H^"["^immN_neon_uimm3^"]" is Rn_VPR128.H & immN_neon_uimm3 & Rn_VPR128.H.selN { export Rn_VPR128.H.selN; } +Rn_VPR128.S.immN_neon_uimm2: Rn_VPR128.S^"["^immN_neon_uimm2^"]" is Rn_VPR128.S & immN_neon_uimm2 & Rn_VPR128.S.selN { export Rn_VPR128.S.selN; } +Rn_VPR128.D.immN_neon_uimm1: Rn_VPR128.D^"["^immN_neon_uimm1^"]" is Rn_VPR128.D & immN_neon_uimm1 & Rn_VPR128.D.selN { export Rn_VPR128.D.selN; } + +@if DATA_ENDIAN == "little" +Rn_VPR128.B.sel: Rn_VPR128, val is Rn_VPR128 & imm_neon_uimm4 [ val = 0x5000 + 32*Rn_VPR128 + imm_neon_uimm4; ] { export *[register]:1 val; } +Rn_VPR128.H.sel: Rn_VPR128, val is Rn_VPR128 & imm_neon_uimm3 [ val = 0x5000 + 32*Rn_VPR128 + 2*imm_neon_uimm3; ] { export *[register]:2 val; } +Rn_VPR128.S.sel: Rn_VPR128, val is Rn_VPR128 & imm_neon_uimm2 [ val = 0x5000 + 32*Rn_VPR128 + 4*imm_neon_uimm2; ] { export *[register]:4 val; } +Rn_VPR128.D.sel: Rn_VPR128, val is Rn_VPR128 & imm_neon_uimm1 [ val = 0x5000 + 32*Rn_VPR128 + 8*imm_neon_uimm1; ] { export *[register]:8 val; } +@else +Rn_VPR128.B.sel: Rn_VPR128, val is Rn_VPR128 & imm_neon_uimm4 [ val = 0x501f + 32*Rn_VPR128 - imm_neon_uimm4; ] { export *[register]:1 val; } +Rn_VPR128.H.sel: Rn_VPR128, val is Rn_VPR128 & imm_neon_uimm3 [ val = 0x501e + 32*Rn_VPR128 - 2*imm_neon_uimm3; ] { export *[register]:2 val; } +Rn_VPR128.S.sel: Rn_VPR128, val is Rn_VPR128 & imm_neon_uimm2 [ val = 0x501c + 32*Rn_VPR128 - 4*imm_neon_uimm2; ] { export *[register]:4 val; } +Rn_VPR128.D.sel: Rn_VPR128, val is Rn_VPR128 & imm_neon_uimm1 [ val = 0x5018 + 32*Rn_VPR128 - 8*imm_neon_uimm1; ] { export *[register]:8 val; } +@endif +Rn_VPR128.B.imm_neon_uimm4: Rn_VPR128.B^"["^imm_neon_uimm4^"]" is Rn_VPR128.B & imm_neon_uimm4 & Rn_VPR128.B.sel { export Rn_VPR128.B.sel; } +Rn_VPR128.H.imm_neon_uimm3: Rn_VPR128.H^"["^imm_neon_uimm3^"]" is Rn_VPR128.H & imm_neon_uimm3 & Rn_VPR128.H.sel { export Rn_VPR128.H.sel; } +Rn_VPR128.S.imm_neon_uimm2: Rn_VPR128.S^"["^imm_neon_uimm2^"]" is Rn_VPR128.S & imm_neon_uimm2 & Rn_VPR128.S.sel { export Rn_VPR128.S.sel; } +Rn_VPR128.D.imm_neon_uimm1: Rn_VPR128.D^"["^imm_neon_uimm1^"]" is Rn_VPR128.D & imm_neon_uimm1 & Rn_VPR128.D.sel { export Rn_VPR128.D.sel; } + +Re_VPR128.H.vIndexHL: Re_VPR128.H^"["^vIndexHL^"]" is Re_VPR128.H & vIndexHL { } + +@if DATA_ENDIAN == "little" +Re_VPR128Lo.H.sel: Re_VPR128, val is Re_VPR128 & b_2223=2 & b_2121 & b_1111 [ val = 0x5000 + 32*Re_VPR128 + (b_1111 * 2 + b_2121)*2; ] { export *[register]:2 val; } +Re_VPR128Lo.H.sel: Re_VPR128, val is Re_VPR128 & b_2223=1 & b_2121 & b_1111 & b_2020 [ val = 0x5000 + 32*Re_VPR128 + (b_1111*4 + b_2121*2 + b_2020)*2; ] { export *[register]:2 val; } +Re_VPR128Lo.H.sel: Re_VPR128, val is Re_VPR128 & b_2223=0 & b_2121 & b_1111 & b_2020 [ val = 0x5000 + 32*Re_VPR128 + (b_1111*4 + b_2121*2 + b_2020)*2; ] { export *[register]:2 val; } +@else +Re_VPR128Lo.H.sel: Re_VPR128, val is Re_VPR128 & b_2223=2 & b_2121 & b_1111 [ val = 0x501e + 32*Re_VPR128 - (b_1111 * 2 + b_2121)*2; ] { export *[register]:2 val; } +Re_VPR128Lo.H.sel: Re_VPR128, val is Re_VPR128 & b_2223=1 & b_2121 & b_1111 & b_2020 [ val = 0x501e + 32*Re_VPR128 - (b_1111*4 + b_2121*2 + b_2020)*2; ] { export *[register]:2 val; } +Re_VPR128Lo.H.sel: Re_VPR128, val is Re_VPR128 & b_2223=0 & b_2121 & b_1111 & b_2020 [ val = 0x501e + 32*Re_VPR128 - (b_1111*4 + b_2121*2 + b_2020)*2; ] { export *[register]:2 val; } +@endif +Re_VPR128Lo.H.vIndexHLM: Re_VPR128Lo.H^"["^vIndexHLM^"]" is Re_VPR128Lo.H & vIndexHLM & Re_VPR128Lo.H.sel { export Re_VPR128Lo.H.sel; } + +FBitsOp: "#"^fbits is Scale [ fbits = 64 - Scale; ] { export *[const]:2 fbits; } + +FBits64: factor is FBitsOp & Scale [ factor = 1 << (64 - Scale); ] { fval:8 = int2float(factor:8); export fval; } +FBits32: factor is FBitsOp & Scale [ factor = 1 << (64 - Scale); ] { fval:4 = int2float(factor:8); export fval; } +FBits16: factor is FBitsOp & Scale [ factor = 1 << (64 - Scale); ] { fval:2 = int2float(factor:8); export fval; } + +# float + +Imm8_fmov16_operand: imm is Imm8_fmov_sign & Imm8_fmov_exph & Imm8_fmov_expl & Imm8_fmov_frac & ftype=3 [ imm = (Imm8_fmov_sign << 15) | ((Imm8_fmov_exph $xor 1) << 14) | ((Imm8_fmov_exph * 0x3) << 12) | (Imm8_fmov_expl << 10) | (Imm8_fmov_frac << 6); ] { export *[const]:2 imm; } + +Imm8_fmov32_operand: imm is Imm8_fmov_sign & Imm8_fmov_exph & Imm8_fmov_expl & Imm8_fmov_frac & ftype=0 [ imm = (Imm8_fmov_sign << 31) | ((Imm8_fmov_exph $xor 1) << 30) | ((Imm8_fmov_exph * 0x1f) << 25) | (Imm8_fmov_expl << 23) | (Imm8_fmov_frac << 19); ] { export *[const]:4 imm; } + +# double +Imm8_fmov64_operand: imm is Imm8_fmov_sign & Imm8_fmov_exph & Imm8_fmov_expl & Imm8_fmov_frac & ftype=1 [ imm = (Imm8_fmov_sign << 63) | ((Imm8_fmov_exph $xor 1) << 62) | ((Imm8_fmov_exph * 0xff) << 54) | (Imm8_fmov_expl << 52) | (Imm8_fmov_frac << 48); ] { export *[const]:8 imm; } + +# SVE subtables + +# The size qualifer (T) is encoded in several different ways. The +# majority of encodings are in sve_size_2223 + +# encoded in "size" -- Is the size specifier, size 00 B 01 H 10 S 11 D + +T: "B" is sve_size_2223=0b00 { export 1:1; } +T: "H" is sve_size_2223=0b01 { export 2:1; } +T: "S" is sve_size_2223=0b10 { export 4:1; } +T: "D" is sve_size_2223=0b11 { export 8:1; } + +T_sz: "S" is sve_sz_22=0 { export 4:1; } +T_sz: "D" is sve_sz_22=1 { export 8:1; } + +# encoded in "tszh:tszl" -- Is the size specifier, tszh tszl 00 00 RESERVED 00 01 B 00 1x H 01 xx S 1x xx D +# Note that tszl is either in b_0809 (if b_21=0) or b_1920 (if b_21=1) + +T_tszh: "B" is sve_tszh_2223=0b00 & b_21=0 & sve_tszl_0809=0b01 { export 1:1; } +T_tszh: "B" is sve_tszh_2223=0b00 & b_21=1 & sve_tszl_1920=0b01 { export 1:1; } +T_tszh: "H" is sve_tszh_2223=0b00 & b_21=0 & b_09=1 { export 2:1; } +T_tszh: "H" is sve_tszh_2223=0b00 & b_21=1 & b_20=1 { export 2:1; } +T_tszh: "S" is sve_tszh_2223=0b01 { export 4:1; } +T_tszh: "D" is b_23=1 { export 8:1; } + +# encoded in "size" -- Is the size specifier, size 00 B 01 H 10 S 11 D + +T_size_2122: "B" is sve_size_2122=0b00 { export 1:1; } +T_size_2122: "H" is sve_size_2122=0b01 { export 2:1; } +T_size_2122: "S" is sve_size_2122=0b10 { export 4:1; } +T_size_2122: "D" is sve_size_2122=0b11 { export 8:1; } + +# encoded in "tsz" -- Is the size specifier, tsz 00000 RESERVED xxxx1 B xxx10 H xx100 S x1000 D 10000 Q + +T_tsz: "B" is b_16=1 { export 1:1; } +T_tsz: "H" is b_1617=0b10 { export 2:1; } +T_tsz: "S" is b_1618=0b100 { export 4:1; } +T_tsz: "D" is b_1619=0b1000 { export 8:1; } +T_tsz: "Q" is b_1620=0b10000 { export 16:1; } +sve_imm2_tsz: tmp is b_16=1 & sve_imm2_2223 & b_1720 [ tmp = sve_imm2_2223 * 16 + b_1720; ] { export *[const]:1 tmp; } +sve_imm2_tsz: tmp is b_1617=0b10 & sve_imm2_2223 & b_1820 [ tmp = sve_imm2_2223 * 8 + b_1820; ] { export *[const]:1 tmp; } +sve_imm2_tsz: tmp is b_1618=0b100 & sve_imm2_2223 & b_1920 [ tmp = sve_imm2_2223 * 4 + b_1920; ] { export *[const]:1 tmp; } +sve_imm2_tsz: tmp is b_1619=0b1000 & sve_imm2_2223 & b_20 [ tmp = sve_imm2_2223 * 2 + b_20; ] { export *[const]:1 tmp; } +sve_imm2_tsz: tmp is b_1620=0b10000 & sve_imm2_2223 [ tmp = sve_imm2_2223 + 0; ] { export *[const]:1 tmp; } + +# encoded in "imm13<12>:imm13<5:0>" -- Is the size specifier, imm13<12> imm13<5:0> 0 0xxxxx S 0 10xxxx H 0 110xxx B 0 1110xx B 0 11110x B 0 111110 RESERVED 0 111111 RESERVED 1 xxxxxx D + +T_imm13: "S" is b_17=0 & b_10=0 { export 4:1; } +T_imm13: "H" is b_17=0 & b_0910=0b10 { export 2:1; } +T_imm13: "B" is b_17=0 & b_0810=0b110 { export 1:1; } +T_imm13: "B" is b_17=0 & b_0710=0b1110 { export 1:1; } +T_imm13: "B" is b_17=0 & b_0610=0b11110 { export 1:1; } +T_imm13: "D" is b_17=1 { export 8:1; } + +Zd.T: Zd^"."^T is Zd & T { export Zd; } +Zd.T_2: Zd^"."^T is Zd & T { export Zd; } +Zd.T_tszh: Zd^"."^T_tszh is Zd & T_tszh { export Zd; } +Zd.T_tszh_2: Zd^"."^T_tszh is Zd & T_tszh { export Zd; } +Zd.T_tsz: Zd^"."^T_tsz is Zd & T_tsz { export Zd; } +Zd.T_imm13: Zd^"."^T_imm13 is Zd & T_imm13 { export Zd; } +Zd.T_imm13_2: Zd^"."^T_imm13 is Zd & T_imm13 { export Zd; } +Zd.T_sz: Zd^"."^T_sz is Zd & T_sz { export Zd; } +Zd.T_sz_2: Zd^"."^T_sz is Zd & T_sz { export Zd; } +Zd.T_size_2122: Zd^"."^T_size_2122 is Zd & T_size_2122 { export Zd; } + +Zd.B: Zd^".B" is Zd { export Zd; } +Zd.B_2: Zd^".B" is Zd { export Zd; } +Zd.H: Zd^".H" is Zd { export Zd; } +Zd.S: Zd^".S" is Zd { export Zd; } +Zd.D: Zd^".D" is Zd { export Zd; } + +Zt.B: sve_zt_0004^".B" is sve_zt_0004 { export sve_zt_0004; } +Ztt.B: sve_ztt_0004^".B" is sve_ztt_0004 { export sve_ztt_0004; } +Zttt.B: sve_zttt_0004^".B" is sve_zttt_0004 { export sve_zttt_0004; } +Ztttt.B: sve_ztttt_0004^".B" is sve_ztttt_0004 { export sve_ztttt_0004; } +Zt.H: sve_zt_0004^".H" is sve_zt_0004 { export sve_zt_0004; } +Ztt.H: sve_ztt_0004^".H" is sve_ztt_0004 { export sve_ztt_0004; } +Zttt.H: sve_zttt_0004^".H" is sve_zttt_0004 { export sve_zttt_0004; } +Ztttt.H: sve_ztttt_0004^".H" is sve_ztttt_0004 { export sve_ztttt_0004; } +Zt.S: sve_zt_0004^".S" is sve_zt_0004 { export sve_zt_0004; } +Ztt.S: sve_ztt_0004^".S" is sve_ztt_0004 { export sve_ztt_0004; } +Zttt.S: sve_zttt_0004^".S" is sve_zttt_0004 { export sve_zttt_0004; } +Ztttt.S: sve_ztttt_0004^".S" is sve_ztttt_0004 { export sve_ztttt_0004; } +Zt.D: sve_zt_0004^".D" is sve_zt_0004 { export sve_zt_0004; } +Ztt.D: sve_ztt_0004^".D" is sve_ztt_0004 { export sve_ztt_0004; } +Zttt.D: sve_zttt_0004^".D" is sve_zttt_0004 { export sve_zttt_0004; } +Ztttt.D: sve_ztttt_0004^".D" is sve_ztttt_0004 { export sve_ztttt_0004; } + +Zn.T: sve_zn_0509^"."^T is sve_zn_0509 & T { export sve_zn_0509; } +Zn.T_sz: sve_zn_0509^"."^T_sz is sve_zn_0509 & T_sz { export sve_zn_0509; } +Zn.T_tszh: sve_zn_0509^"."^T_tszh is sve_zn_0509 & T_tszh { export sve_zn_0509; } +Zn.T_tsz: sve_zn_0509^"."^T_tsz is sve_zn_0509 & T_tsz { export sve_zn_0509; } +Zn.Tb_sz: sve_zn_0509^".B" is sve_zn_0509 & sve_sz_22=0 { export sve_zn_0509; } +Zn.Tb_sz: sve_zn_0509^".H" is sve_zn_0509 & sve_sz_22=1 { export sve_zn_0509; } +Zn.Tb: sve_zn_0509^".B" is sve_zn_0509 & sve_size_2223=0b01 { export sve_zn_0509; } +Zn.Tb: sve_zn_0509^".H" is sve_zn_0509 & sve_size_2223=0b10 { export sve_zn_0509; } +Zn.Tb: sve_zn_0509^".S" is sve_zn_0509 & sve_size_2223=0b11 { export sve_zn_0509; } + +Zn.B: sve_zn_0509^".B" is sve_zn_0509 { export sve_zn_0509; } +Zn.H: sve_zn_0509^".H" is sve_zn_0509 { export sve_zn_0509; } +Zn.S: sve_zn_0509^".S" is sve_zn_0509 { export sve_zn_0509; } +Zn.D: sve_zn_0509^".D" is sve_zn_0509 { export sve_zn_0509; } + +Zm.T: sve_zm_1620^"."^T is sve_zm_1620 & T { export sve_zm_1620; } +Zm.T_sz: sve_zm_1620^"."^T_sz is sve_zm_1620 & T_sz { export sve_zm_1620; } +Zm.Tb_sz: sve_zm_1620^".B" is sve_zm_1620 & sve_sz_22=0 { export sve_zm_1620; } +Zm.Tb_sz: sve_zm_1620^".H" is sve_zm_1620 & sve_sz_22=1 { export sve_zm_1620; } +# Zm.Tb: sve_zm_1620^".B" is sve_zm_1620 & sve_size_2223=0b01 { export sve_zm_1620; } +# Zm.Tb: sve_zm_1620^".H" is sve_zm_1620 & sve_size_2223=0b10 { export sve_zm_1620; } +# Zm.Tb: sve_zm_1620^".S" is sve_zm_1620 & sve_size_2223=0b11 { export sve_zm_1620; } + +# Zm.B: sve_zm_1620^".B" is sve_zm_1620 { export sve_zm_1620; } +# Zm.H: sve_zm_1620^".H" is sve_zm_1620 { export sve_zm_1620; } +Zm.S: sve_zm_1620^".S" is sve_zm_1620 { export sve_zm_1620; } +Zm.D: sve_zm_1620^".D" is sve_zm_1620 { export sve_zm_1620; } + +Zm3.B: sve_zm_1618^".B" is sve_zm_1618 { export sve_zm_1618; } +Zm3.H: sve_zm_1618^".H" is sve_zm_1618 { export sve_zm_1618; } +Zm3.S: sve_zm_1618^".S" is sve_zm_1618 { export sve_zm_1618; } +# Zm3.D: sve_zm_1618^".D" is sve_zm_1618 { export sve_zm_1618; } + +# Zm4.B: sve_zm_1619^".B" is sve_zm_1619 { export sve_zm_1619; } +Zm4.H: sve_zm_1619^".H" is sve_zm_1619 { export sve_zm_1619; } +Zm4.S: sve_zm_1619^".S" is sve_zm_1619 { export sve_zm_1619; } +Zm4.D: sve_zm_1619^".D" is sve_zm_1619 { export sve_zm_1619; } + +Pg: sve_pg_1013 is sve_pg_1013 { export sve_pg_1013; } +Pg_z: sve_pg_1013^"/z" is sve_pg_1013 { export sve_pg_1013; } +Pg_zm: sve_pg_1013^"/z" is sve_pg_1013 & sve_m_04=0 { export sve_pg_1013; } +Pg_zm: sve_pg_1013^"/m" is sve_pg_1013 & sve_m_04=1 { export sve_pg_1013; } +Pg3: sve_pg_1012 is sve_pg_1012 { export sve_pg_1012; } +Pg3_m: sve_pg_1012^"/m" is sve_pg_1012 { export sve_pg_1012; } +Pg3_z: sve_pg_1012^"/z" is sve_pg_1012 { export sve_pg_1012; } +Pg3_zm: sve_pg_1012^"/z" is sve_pg_1012 & sve_m_16=0 { export sve_pg_1012; } +Pg3_zm: sve_pg_1012^"/m" is sve_pg_1012 & sve_m_16=1 { export sve_pg_1012; } + +Pd.T: sve_pd_0003^"."^T is sve_pd_0003 & T { export sve_pd_0003; } +Pd.T_2: sve_pd_0003^"."^T is sve_pd_0003 & T { export sve_pd_0003; } +Pd: sve_pd_0003 is sve_pd_0003 { export sve_pd_0003; } +Pd.B: sve_pd_0003^".B" is sve_pd_0003 { export sve_pd_0003; } +Pd.B_2: sve_pd_0003^".B" is sve_pd_0003 { export sve_pd_0003; } +Pd.H: sve_pd_0003^".H" is sve_pd_0003 { export sve_pd_0003; } +# Pd.S: sve_pd_0003^".S" is sve_pd_0003 { export sve_pd_0003; } +# Pd.D: sve_pd_0003^".D" is sve_pd_0003 { export sve_pd_0003; } + +Pn: sve_pn_0508 is sve_pn_0508 { export sve_pn_0508; } +Pn_z: sve_pn_0508^"/z" is sve_pn_0508 { export sve_pn_0508; } +Pn.T: sve_pn_0508^"."^T is sve_pn_0508 & T { export sve_pn_0508; } +Pn.B: sve_pn_0508^".B" is sve_pn_0508 { export sve_pn_0508; } +# Pn.H: sve_pn_0508^".H" is sve_pn_0508 { export sve_pn_0508; } +# Pn.S: sve_pn_0508^".S" is sve_pn_0508 { export sve_pn_0508; } +# Pn.D: sve_pn_0508^".D" is sve_pn_0508 { export sve_pn_0508; } + +Pm_m: sve_pm_1619^"/m" is sve_pm_1619 { export sve_pm_1619; } +Pm_zm: sve_pm_1619^"/z" is sve_pm_1619 & sve_m_14=0 { export sve_pm_1619; } +Pm_zm: sve_pm_1619^"/m" is sve_pm_1619 & sve_m_14=1 { export sve_pm_1619; } +Pm.T: sve_pm_1619^"."^T is sve_pm_1619 & T { export sve_pm_1619; } +Pm.B: sve_pm_1619^".B" is sve_pm_1619 { export sve_pm_1619; } +# Pm.H: sve_pm_1619^".H" is sve_pm_1619 { export sve_pm_1619; } +# Pm.S: sve_pm_1619^".S" is sve_pm_1619 { export sve_pm_1619; } +# Pm.D: sve_pm_1619^".D" is sve_pm_1619 { export sve_pm_1619; } + +sve_i3h_i3l: tmp is sve_i3h_22 & sve_i3l_1920 [ tmp = sve_i3h_22 * 4 + sve_i3l_1920; ] { export *[const]:1 tmp; } +sve_imm3_1_0to7: sve_imm3_1618 is sve_imm3_1618 { export *[const]:1 sve_imm3_1618; } +sve_imm4_1_1to16: tmp is sve_imm4_1619 [ tmp = sve_imm4_1619 + 1; ] { export *[const]:1 tmp; } +sve_imm4_1_m128to112: tmp is sve_imm4s_1619 [ tmp = sve_imm4s_1619 * 16; ] { export *[const]:1 tmp; } +sve_opt4_1_m128to112: "" is sve_imm4s_1619=0 { export 0:1; } +sve_opt4_1_m128to112: ", #"^sve_imm4_1_m128to112 is sve_imm4_1_m128to112 { export sve_imm4_1_m128to112; } +sve_imm4_1_m16to14: tmp is sve_imm4s_1619 [ tmp = sve_imm4s_1619 * 2; ] { export *[const]:1 tmp; } +sve_mul4_1_m16to14: "" is sve_imm4s_1619=0 { export 0:1; } +sve_mul4_1_m16to14: ", #"^sve_imm4_1_m16to14^", mul vl" is sve_imm4_1_m16to14 { export *[const]:1 sve_imm4_1_m16to14; } +sve_imm4_1_m24to21: tmp is sve_imm4s_1619 [ tmp = sve_imm4s_1619 * 3; ] { export *[const]:1 tmp; } +sve_mul4_1_m24to21: "" is sve_imm4s_1619=0 { export 0:1; } +sve_mul4_1_m24to21: ", #"^sve_imm4_1_m24to21^", mul vl" is sve_imm4_1_m24to21 { export *[const]:1 sve_imm4_1_m24to21; } +sve_imm4_1_m32to28: tmp is sve_imm4s_1619 [ tmp = sve_imm4s_1619 * 4; ] { export *[const]:1 tmp; } +sve_mul4_1_m32to28: "" is sve_imm4s_1619=0 { export 0:1; } +sve_mul4_1_m32to28: ", #"^sve_imm4_1_m32to28^", mul vl" is sve_imm4_1_m32to28 { export *[const]:1 sve_imm4_1_m32to28; } +sve_imm4_1_m8to7: tmp is sve_imm4s_1619 [ tmp = sve_imm4s_1619 * 1; ] { export *[const]:1 tmp; } +sve_mul4_1_m8to7: "" is sve_imm4s_1619=0 { export 0:1; } +sve_mul4_1_m8to7: ", #"^sve_imm4_1_m8to7^", mul vl" is sve_imm4_1_m8to7 { export *[const]:1 sve_imm4_1_m8to7; } +sve_imm5_1_0to124: tmp is sve_imm5_1620 [ tmp = sve_imm5_1620 * 4; ] { export *[const]:1 tmp; } +sve_opt5_1_0to124: "" is sve_imm5_1620=0 { export 0:1; } +sve_opt5_1_0to124: ", #"^sve_imm5_1_0to124 is sve_imm5_1_0to124 { export sve_imm5_1_0to124; } +sve_imm5_1_0to248: tmp is sve_imm5_1620 [ tmp = sve_imm5_1620 * 8; ] { export *[const]:1 tmp; } +sve_opt5_1_0to248: "" is sve_imm5_1620=0 { export 0:1; } +sve_opt5_1_0to248: ", #"^sve_imm5_1_0to248 is sve_imm5_1_0to248 { export sve_imm5_1_0to248; } +sve_imm5_1_0to31: sve_imm5_1620 is sve_imm5_1620 { export *[const]:1 sve_imm5_1620; } +sve_opt5_1_0to31: "" is sve_imm5_1620=0 { export 0:1; } +sve_opt5_1_0to31: ", #"^sve_imm5_1_0to31 is sve_imm5_1_0to31 { export sve_imm5_1_0to31; } +sve_imm5_1_0to62: tmp is sve_imm5_1620 [ tmp = sve_imm5_1620 * 2; ] { export *[const]:1 tmp; } +sve_opt5_1_0to62: "" is sve_imm5_1620=0 { export 0:1; } +sve_opt5_1_0to62: ", #"^sve_imm5_1_0to62 is sve_imm5_1_0to62 { export sve_imm5_1_0to62; } +sve_imm5_1_m16to15: sve_imm5s_1620 is sve_b_1015=0b010001 & sve_imm5s_1620 { export *[const]:1 sve_imm5s_1620; } +sve_imm5_1_m16to15: sve_imm5s_0509 is sve_b_1015=0b010010 & sve_imm5s_0509 { export *[const]:1 sve_imm5s_0509; } +sve_imm6_1_0to126: tmp is sve_imm6_1621 [ tmp = sve_imm6_1621 * 2; ] { export *[const]:1 tmp; } +sve_opt6_1_0to126: "" is sve_imm6_1621=0 { export 0:1; } +sve_opt6_1_0to126: ", #"^sve_imm6_1_0to126 is sve_imm6_1_0to126 { export sve_imm6_1_0to126; } +sve_imm6_1_0to252: tmp is sve_imm6_1621 [ tmp = sve_imm6_1621 * 4; ] { export *[const]:1 tmp; } +sve_opt6_1_0to252: "" is sve_imm6_1621=0 { export 0:1; } +sve_opt6_1_0to252: ", #"^sve_imm6_1_0to252 is sve_imm6_1_0to252 { export sve_imm6_1_0to252; } +sve_imm6_1_0to504: tmp is sve_imm6_1621 [ tmp = sve_imm6_1621 * 8; ] { export *[const]:2 tmp; } +sve_opt6_1_0to504: "" is sve_imm6_1621=0 { export 0:2; } +sve_opt6_1_0to504: ", #"^sve_imm6_1_0to504 is sve_imm6_1_0to504 { export sve_imm6_1_0to504; } +sve_imm6_1_0to63: sve_imm6_1621 is sve_imm6_1621 { export *[const]:1 sve_imm6_1621; } +sve_opt6_1_0to63: "" is sve_imm6_1621=0 { export 0:1; } +sve_opt6_1_0to63: ", #"^sve_imm6_1_0to63 is sve_imm6_1_0to63 { export sve_imm6_1_0to63; } +sve_imm6_1_m32to31: sve_imm6s_0510 is sve_imm6s_0510 { export *[const]:1 sve_imm6s_0510; } +sve_mul6_1_m32to31: "" is sve_imm6_1621=0 { export 0:1; } +sve_mul6_1_m32to31: ", #"^sve_imm6s_1621^", mul vl" is sve_imm6s_1621 { export *[const]:1 sve_imm6s_1621; } +sve_imm8_1_0to255: sve_imm8_0512 is sve_imm8_0512 { export *[const]:1 sve_imm8_0512; } +sve_shf8_1_0to255: "#0, LSL #8" is sve_imm8_0512=0 & sve_sh_13=1 { export 0:2; } +sve_shf8_1_0to255: "#"^tmp is sve_imm8_0512 & sve_sh_13 [ tmp = sve_imm8_0512 << (8 * sve_sh_13); ] { export *[const]:2 tmp; } +sve_imm8_1_m128to127: sve_imm8s_0512 is sve_imm8s_0512 { export *[const]:1 sve_imm8s_0512; } +sve_shf8_1_m128to127: "#0, LSL #8" is sve_imm8s_0512=0 & sve_sh_13=1 { export 0:2; } +sve_shf8_1_m128to127: "#"^tmp is sve_imm8s_0512 & sve_sh_13 [ tmp = sve_imm8s_0512 << (8 * sve_sh_13); ] { export *[const]:2 tmp; } +sve_imm8_2_0to255: tmp is sve_imm8h_1620 & sve_imm8l_1012 [ tmp = sve_imm8h_1620 * 8 + sve_imm8l_1012; ] { export *[const]:1 tmp; } +sve_imm9_2_m256to255: tmp is sve_imm9hs_1621 & sve_imm9l_1012 [ tmp = sve_imm9hs_1621 * 8 + sve_imm9l_1012; ] { export *[const]:2 tmp; } +sve_mul9_2_m256to255: "" is sve_imm6_1621=0 & sve_imm9l_1012=0 { export 0:2; } +sve_mul9_2_m256to255: ", #"^sve_imm9_2_m256to255^", mul vl" is sve_imm9_2_m256to255 { export sve_imm9_2_m256to255; } + +sve_pattern: "POW2" is sve_pattern_0509=0b00000 { export 0b00000:1; } +sve_pattern: "VL1" is sve_pattern_0509=0b00001 { export 0b00001:1; } +sve_pattern: "VL2" is sve_pattern_0509=0b00010 { export 0b00010:1; } +sve_pattern: "VL3" is sve_pattern_0509=0b00011 { export 0b00011:1; } +sve_pattern: "VL4" is sve_pattern_0509=0b00100 { export 0b00100:1; } +sve_pattern: "VL5" is sve_pattern_0509=0b00101 { export 0b00101:1; } +sve_pattern: "VL6" is sve_pattern_0509=0b00110 { export 0b00110:1; } +sve_pattern: "VL7" is sve_pattern_0509=0b00111 { export 0b00111:1; } +sve_pattern: "VL8" is sve_pattern_0509=0b01000 { export 0b01000:1; } +sve_pattern: "VL16" is sve_pattern_0509=0b01001 { export 0b01001:1; } +sve_pattern: "VL32" is sve_pattern_0509=0b01010 { export 0b01010:1; } +sve_pattern: "VL64" is sve_pattern_0509=0b01011 { export 0b01011:1; } +sve_pattern: "VL128" is sve_pattern_0509=0b01100 { export 0b01100:1; } +sve_pattern: "VL256" is sve_pattern_0509=0b01101 { export 0b01101:1; } +sve_pattern: "#"^sve_pattern_0509 is b_0609=0b0111 & sve_pattern_0509 { export *[const]:1 sve_pattern_0509; } +sve_pattern: "#"^sve_pattern_0509 is b_0709=0b101 & b_05=1 & sve_pattern_0509 { export *[const]:1 sve_pattern_0509; } +sve_pattern: "#"^sve_pattern_0509 is b_0509=0b10110 & sve_pattern_0509 { export *[const]:1 sve_pattern_0509; } +sve_pattern: "#"^sve_pattern_0509 is b_09=1 & b_07=0 & b_05=1 & sve_pattern_0509 { export *[const]:1 sve_pattern_0509; } +sve_pattern: "#"^sve_pattern_0509 is b_09=1 & b_0507=0b010 & sve_pattern_0509 { export *[const]:1 sve_pattern_0509; } +sve_pattern: "#"^sve_pattern_0509 is b_09=1 & b_0506=0b00 & sve_pattern_0509 { export *[const]:1 sve_pattern_0509; } +sve_pattern: "MUL4" is sve_pattern_0509=0b11101 { export 0b11101:1; } +sve_pattern: "MUL3" is sve_pattern_0509=0b11110 { export 0b11110:1; } +sve_pattern: "ALL" is sve_pattern_0509=0b11111 { export 0b11111:1; } + +sve_opt_pattern: "" is sve_pattern_0509=0b11111 { export 0b11111:1; } +sve_opt_pattern: ", "^sve_pattern is sve_pattern { export sve_pattern; } + +sve_mul_pattern: "" is sve_pattern_0509=0b11111 & sve_imm4_1619=0b0000 { export 0b11111:1; } +sve_mul_pattern: ", "^sve_pattern is sve_pattern & sve_imm4_1619=0b0000 { export sve_pattern; } +sve_mul_pattern: ", "^sve_pattern^", mul #"^sve_imm4_1_1to16 is sve_pattern & sve_imm4_1_1to16 { export sve_pattern; } + +sve_mod_amount: "" is sve_msz_1011=0b00 { export 0:1; } +sve_mod_amount: ", LSL #1" is sve_msz_1011=0b01 { export 1:1; } +sve_mod_amount: ", LSL #2" is sve_msz_1011=0b10 { export 2:1; } +sve_mod_amount: ", LSL #3" is sve_msz_1011=0b11 { export 3:1; } + +sve_mod: "UXTW" is b_15=1 & b_14=0 { export 2:1; } +sve_mod: "SXTW" is b_15=1 & b_14=1 { export 3:1; } +sve_mod: "UXTW" is b_15=0 & b_22=0 { export 0:1; } +sve_mod: "SXTW" is b_15=0 & b_22=1 { export 1:1; } + +sve_prfop: "PLDL1KEEP" is sve_prfop_0003=0b0000 { export 0b0000:1; } +sve_prfop: "PLDL1STRM" is sve_prfop_0003=0b0001 { export 0b0001:1; } +sve_prfop: "PLDL2KEEP" is sve_prfop_0003=0b0010 { export 0b0010:1; } +sve_prfop: "PLDL2STRM" is sve_prfop_0003=0b0011 { export 0b0011:1; } +sve_prfop: "PLDL3KEEP" is sve_prfop_0003=0b0100 { export 0b0100:1; } +sve_prfop: "PLDL3STRM" is sve_prfop_0003=0b0101 { export 0b0101:1; } +sve_prfop: "#"^sve_prfop_0003 is b_02 & b_01=1 & sve_prfop_0003 { export *[const]:1 sve_prfop_0003; } +sve_prfop: "PSTL1KEEP" is sve_prfop_0003=0b1000 { export 0b1000:1; } +sve_prfop: "PSTL1STRM" is sve_prfop_0003=0b1001 { export 0b1001:1; } +sve_prfop: "PSTL2KEEP" is sve_prfop_0003=0b1010 { export 0b1010:1; } +sve_prfop: "PSTL2STRM" is sve_prfop_0003=0b1011 { export 0b1011:1; } +sve_prfop: "PSTL3KEEP" is sve_prfop_0003=0b1100 { export 0b1100:1; } +sve_prfop: "PSTL3STRM" is sve_prfop_0003=0b1101 { export 0b1101:1; } + +sve_decode_bit_mask: wmask is b_17=0 & b_0510=0b111100 & b_11 [ wmask = (0x5555 >> b_11) & 0xff; ] { export *[const]:8 wmask; } +sve_decode_bit_mask: wmask is b_17=0 & b_0710=0b1110 & b_0506=0b00 & b_1112 [ wmask = (0x1111 >> b_1112) & 0xff; ] { export *[const]:8 wmask; } +sve_decode_bit_mask: wmask is b_17=0 & b_0710=0b1110 & b_0506=0b01 & b_1112 [ wmask = (0x3333 >> b_1112) & 0xff; ] { export *[const]:8 wmask; } +sve_decode_bit_mask: wmask is b_17=0 & b_0710=0b1110 & b_0506=0b10 & b_1112 [ wmask = (0x7777 >> b_1112) & 0xff; ] { export *[const]:8 wmask; } +sve_decode_bit_mask: wmask is b_17=0 & b_0810=0b110 & b_0507 & b_1113 [ wmask = (((~(-1<<(b_0507+1))) | (~(-1<<(b_0507+9)) & 0xff00)) >> b_1113) & 0xff; ] { export *[const]:8 wmask; } +sve_decode_bit_mask: wmask is b_17=0 & b_0910=0b10 & b_0508 & b_1114 [ wmask = (((~(-1<<(b_0508+1))) | (~(-1<<(b_0508+17)) & 0xffff0000)) >> b_1114) & 0xffff; ] { export *[const]:8 wmask; } +sve_decode_bit_mask: wmask is b_17=0 & b_10=0 & b_0509 & b_1115 [ wmask = (((~(-1<<(b_0509+1))) | (~(-1<<(b_0509+33)) & 0xffffffff00000000)) >> b_1115) & 0xffffffff; ] { export *[const]:8 wmask; } +sve_decode_bit_mask: wmask is b_17=1 & b_0510 & b_1116 [ wmask = ( (((~(-1<<(b_0510+1)))) >> b_1116) | (((~(-1<<(b_0510+1)))) << (64-b_1116))) & 0xffffffffffffffff; ] { export *[const]:8 wmask; } + +sve_shift_13: "" is sve_sh_13=0 { export 0:1; } +sve_shift_13: ", LSL #8" is sve_sh_13=1 { export 8:1; } + +# The immediate shift is computed from tszh, tszl, imm8. The formula +# depends on the instruction, as does the location of tszl and imm8. +# The conditions b_21=0/1 and b_17/b_11=0/1 were found by inspecting +# the differences between the instructions. + +# Instructions where the immediate shift is 2 * esize - UInt(tsz:imm3) +sve_imm_shift: tmp is b_21=0 & b_17=0 & sve_tszh_2223=0b00 & sve_tszl_0809=0b01 & sve_imm3_0507 [ tmp = 16 - ( 8 + sve_imm3_0507); ] { export *[const]:1 tmp; } +sve_imm_shift: tmp is b_21=0 & b_17=0 & sve_tszh_2223=0b00 & b_09=1 & sve_tszl_0809 & sve_imm3_0507 [ tmp = 32 - ( 8 * sve_tszl_0809 + sve_imm3_0507); ] { export *[const]:1 tmp; } +sve_imm_shift: tmp is b_21=0 & b_17=0 & sve_tszh_2223=0b01 & sve_tszl_0809 & sve_imm3_0507 [ tmp = 64 - (32 + 8 * sve_tszl_0809 + sve_imm3_0507); ] { export *[const]:1 tmp; } +sve_imm_shift: tmp is b_21=0 & b_17=0 & b_23=1 & sve_tszh_2223 & sve_tszl_0809 & sve_imm3_0507 [ tmp = 128 - (32 * sve_tszh_2223 + 8 * sve_tszl_0809 + sve_imm3_0507); ] { export *[const]:1 tmp; } +sve_imm_shift: tmp is b_21=1 & b_11=0 & sve_tszh_2223=0b00 & sve_tszl_1920=0b01 & sve_imm3_1618 [ tmp = 16 - ( 8 + sve_imm3_1618); ] { export *[const]:1 tmp; } +sve_imm_shift: tmp is b_21=1 & b_11=0 & sve_tszh_2223=0b00 & b_20=1 & sve_tszl_1920 & sve_imm3_1618 [ tmp = 32 - ( 8 * sve_tszl_1920 + sve_imm3_1618); ] { export *[const]:1 tmp; } +sve_imm_shift: tmp is b_21=1 & b_11=0 & sve_tszh_2223=0b01 & sve_tszl_1920 & sve_imm3_1618 [ tmp = 64 - (32 + 8 * sve_tszl_1920 + sve_imm3_1618); ] { export *[const]:1 tmp; } +sve_imm_shift: tmp is b_21=1 & b_11=0 & b_23=1 & sve_tszh_2223 & sve_tszl_1920 & sve_imm3_1618 [ tmp = 128 - (32 * sve_tszh_2223 + 8 * sve_tszl_1920 + sve_imm3_1618); ] { export *[const]:1 tmp; } + +# Instructions where the immediate shift is UInt(tsz:imm3) - esize +sve_imm_shift: tmp is b_21=0 & b_17=1 & sve_tszh_2223=0b00 & sve_tszl_0809=0b01 & sve_imm3_0507 [ tmp = ( 8 + sve_imm3_0507) - 8; ] { export *[const]:1 tmp; } +sve_imm_shift: tmp is b_21=0 & b_17=1 & sve_tszh_2223=0b00 & b_09=1 & sve_tszl_0809 & sve_imm3_0507 [ tmp = ( 8 * sve_tszl_0809 + sve_imm3_0507) - 16; ] { export *[const]:1 tmp; } +sve_imm_shift: tmp is b_21=0 & b_17=1 & sve_tszh_2223=0b01 & sve_tszl_0809 & sve_imm3_0507 [ tmp = (32 + 8 * sve_tszl_0809 + sve_imm3_0507) - 32; ] { export *[const]:1 tmp; } +sve_imm_shift: tmp is b_21=0 & b_17=1 & b_23=1 & sve_tszh_2223 & sve_tszl_0809 & sve_imm3_0507 [ tmp = (32 * sve_tszh_2223 + 8 * sve_tszl_0809 + sve_imm3_0507) - 64; ] { export *[const]:1 tmp; } +sve_imm_shift: tmp is b_21=1 & b_11=1 & sve_tszh_2223=0b00 & sve_tszl_1920=0b01 & sve_imm3_1618 [ tmp = ( 8 + sve_imm3_1618) - 8; ] { export *[const]:1 tmp; } +sve_imm_shift: tmp is b_21=1 & b_11=1 & sve_tszh_2223=0b00 & b_20=1 & sve_tszl_1920 & sve_imm3_1618 [ tmp = ( 8 * sve_tszl_1920 + sve_imm3_1618) - 16; ] { export *[const]:1 tmp; } +sve_imm_shift: tmp is b_21=1 & b_11=1 & sve_tszh_2223=0b01 & sve_tszl_1920 & sve_imm3_1618 [ tmp = (32 + 8 * sve_tszl_1920 + sve_imm3_1618) - 32; ] { export *[const]:1 tmp; } +sve_imm_shift: tmp is b_21=1 & b_11=1 & b_23=1 & sve_tszh_2223 & sve_tszl_1920 & sve_imm3_1618 [ tmp = (32 * sve_tszh_2223 + 8 * sve_tszl_1920 + sve_imm3_1618) - 64; ] { export *[const]:1 tmp; } + +sve_float_0510: "#0.5" is sve_i1_05=0 { export 0:1; } +sve_float_0510: "#1.0" is sve_i1_05=1 { export 1:1; } +sve_float_0520: "#0.5" is sve_i1_05=0 { export 0:1; } +sve_float_0520: "#2.0" is sve_i1_05=1 { export 1:1; } +sve_float_0010: "#0.0" is sve_i1_05=0 { export 0:1; } +sve_float_0010: "#1.0" is sve_i1_05=1 { export 1:1; } + +# there are no floating point constants in SLEIGH +# generate equivalent hex floating point constant + +attach names [ sve_float_dec ] [ "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "a" "b" "c" "d" "e" "f" ]; +attach names [ sve_float_exp ] [ "+1" "+2" "+3" "+4" "-3" "-2" "-1" "+0" ]; + +sve_float_imm8: s^"."^sve_float_dec^"p"^sve_float_exp is sve_imm8_0512 & sve_float_dec & sve_float_exp & b_12 [ s = (1 - 2 * b_12); ] { export *[const]:1 sve_imm8_0512; } + +# SECTION pcodeops + +# The following SIMD and MP versions of SLEIGH primitives are +# implemented in java for AARCH64 + +define pcodeop MP_INT_ABS; +define pcodeop MP_INT_RIGHT; +define pcodeop MP_INT_MULT; +define pcodeop MP_INT_UMULT; + +# The following AARCH64 instructions are implemented in java as a +# pcodeop + +define pcodeop a64_TBL; + +# The following pcode ops are not implemented + +define pcodeop AT_S12E0R; +define pcodeop AT_S12E0W; +define pcodeop AT_S12E1R; +define pcodeop AT_S12E1W; +define pcodeop AT_S1E0R; +define pcodeop AT_S1E0W; +define pcodeop AT_S1E1R; +define pcodeop AT_S1E1RP; +define pcodeop AT_S1E1W; +define pcodeop AT_S1E1WP; +define pcodeop AT_S1E2R; +define pcodeop AT_S1E2W; +define pcodeop AT_S1E3R; +define pcodeop AT_S1E3W; +define pcodeop AuthIA; +define pcodeop AuthIB; +define pcodeop AuthDA; +define pcodeop AuthDB; +define pcodeop CallHyperVisor; +define pcodeop CallSecureMonitor; +define pcodeop CallSupervisor; +define pcodeop ClearExclusiveLocal; +define pcodeop crc32b; define pcodeop crc32h; +define pcodeop crc32w; +define pcodeop crc32x; +define pcodeop DataMemoryBarrier; +define pcodeop DataSynchronizationBarrier; +define pcodeop DC_CISW; +define pcodeop DC_CIVAC; +define pcodeop DC_CSW; +define pcodeop DC_CVAC; +define pcodeop DC_CVAP; +define pcodeop DC_CVAU; +define pcodeop DC_ISW; +define pcodeop DC_IVAC; +define pcodeop DC_IGVAC; +define pcodeop DC_IGSW; +define pcodeop DC_IGDVAC; +define pcodeop DC_IGDSW; +define pcodeop DC_CGSW; +define pcodeop DC_CGDSW; +define pcodeop DC_CIGSW; +define pcodeop DC_CIGDSW; +define pcodeop DC_GVA; +define pcodeop DC_GZVA; +define pcodeop DC_CGVAC; +define pcodeop DC_CGDVAC; +define pcodeop DC_CGVAP; +define pcodeop DC_CGDVAP; +define pcodeop DC_CGVADP; +define pcodeop DC_CGDVADP; +define pcodeop DC_CIGVAC; +define pcodeop DC_CIGDVAC; +define pcodeop DCPSInstruction; +define pcodeop DC_ZVA; +define pcodeop DRPSInstruction; +define pcodeop ExceptionReturn; +define pcodeop ExclusiveMonitorPass; +define pcodeop ExclusiveMonitorsStatus; +define pcodeop HaltBreakPoint; +define pcodeop Hint_Prefetch; +define pcodeop IC_IALLU; +define pcodeop IC_IALLUIS; +define pcodeop IC_IVAU; +define pcodeop InstructionSynchronizationBarrier; +define pcodeop LOAcquire; +define pcodeop LORelease; +define pcodeop pacda; +define pcodeop pacdb; +define pcodeop pacdza; +define pcodeop pacdzb; +define pcodeop pacga; +define pcodeop pacia; +define pcodeop paciza; +define pcodeop pacib; +define pcodeop pacizb; +define pcodeop SendEvent; +define pcodeop SendEventLocally; +define pcodeop SoftwareBreakpoint; +define pcodeop SpeculationBarrier; +define pcodeop SysOp_R; +define pcodeop SysOp_W; +define pcodeop TLBI_ALLE1; +define pcodeop TLBI_ALLE1IS; +define pcodeop TLBI_ALLE2; +define pcodeop TLBI_ALLE2IS; +define pcodeop TLBI_ALLE3; +define pcodeop TLBI_ALLE3IS; +define pcodeop TLBI_ASIDE1; +define pcodeop TLBI_ASIDE1IS; +define pcodeop TLBI_IPAS2E1; +define pcodeop TLBI_IPAS2E1IS; +define pcodeop TLBI_IPAS2LE1; +define pcodeop TLBI_IPAS2LE1IS; +define pcodeop TLBI_VAAE1; +define pcodeop TLBI_VAALE1; +define pcodeop TLBI_VAAE1IS; +define pcodeop TLBI_VAALE1IS; +define pcodeop TLBI_VAE1; +define pcodeop TLBI_VAE1IS; +define pcodeop TLBI_VAE2; +define pcodeop TLBI_VAE2IS; +define pcodeop TLBI_VAE3; +define pcodeop TLBI_VAE3IS; +define pcodeop TLBI_VALE1; +define pcodeop TLBI_VALE1IS; +define pcodeop TLBI_VALE2; +define pcodeop TLBI_VALE2IS; +define pcodeop TLBI_VALE3; +define pcodeop TLBI_VALE3IS; +define pcodeop TLBI_VMALLE1; +define pcodeop TLBI_VMALLE1IS; +define pcodeop TLBI_VMALLS12E1; +define pcodeop TLBI_VMALLS12E1IS; +define pcodeop UndefinedInstructionException; +define pcodeop UnkSytemRegRead; +define pcodeop UnkSytemRegWrite; +define pcodeop WaitForEvent; +define pcodeop WaitForInterrupt; +define pcodeop xpac; +define pcodeop Yield; + +# BTI and MemTag pseudo ops + +define pcodeop CopyPtrTag_AddToPtrTag_Exclude; # a combination of the ARM spec's ChooseNonExcludedTag and AddressWithAllocationTag +define pcodeop ValidCallTarget; +define pcodeop ValidJumpTarget; # jumps are valid regardless of the register holding the target +define pcodeop ValidJumpTargetWhenDestIsX16OrX17; # jumps are valid if the register holding the target is x16 or x17, e.g. "br x16" +define pcodeop ValidJumpTargetIfPermittedBySCTLR; # depending on EL and SCTLR[35,36], jumps using arbitrary registers may or may not be valid. +define pcodeop ControlFlowPredictionRestrictionByContext; +define pcodeop CachePrefetchPredictionRestrictionByContext; +define pcodeop DataValuePredictionRestrictionByContext; +define pcodeop RandomizePtrTag_Exclude; +define pcodeop SetPtrTag; # this could be implemented in pcode, but it would break the data flow of the original ptr value +define pcodeop LoadMemTag; +define pcodeop StoreMemTag; +define pcodeop AlignmentFault; + +# BTI show/hide operations, which use pcodeops defined above + +# for BTI +BTI_BTITARGETS: is b_0607=0 { } # Not a valid target for jumps or calls +BTI_BTITARGETS: "c" is ShowBTI=1 & b_0607=1 { ValidCallTarget(); ValidJumpTargetWhenDestIsX16OrX17(); } # BR x16 is valid, BR x5 isn't +BTI_BTITARGETS: "j" is ShowBTI=1 & b_0607=2 { ValidJumpTarget(); } +BTI_BTITARGETS: "jc" is ShowBTI=1 & b_0607=3 { ValidJumpTarget(); ValidCallTarget(); } +# hidden versions of the above; use to prevent ValidXXXXTarget calls from cluttering decompiled code in switch statements etc. +BTI_BTITARGETS: "c" is ShowBTI=0 & b_0607=1 { } +BTI_BTITARGETS: "j" is ShowBTI=0 & b_0607=2 { } +BTI_BTITARGETS: "jc" is ShowBTI=0 & b_0607=3 { } + +# for BRK and HLT +ALL_BTITARGETS: is ShowBTI=1 { ValidJumpTarget(); ValidCallTarget(); } +ALL_BTITARGETS: is ShowBTI=0 { } + +# for PACIASP and PACIBSP +PACIXSP_BTITARGETS: is ShowBTI=1 { + ValidCallTarget(); + ValidJumpTargetWhenDestIsX16OrX17(); + # global jump target in the following cases: + # EL == 0 and SCTLR[35] == 0 + # EL != 0 and SCTLR[36] == 0 + ValidJumpTargetIfPermittedBySCTLR(); # this doesn't seem important enough to clutter decompilations with a decision tree +} +PACIXSP_BTITARGETS: is ShowBTI=0 { } + + +# These pseudo ops are used in neon + +define pcodeop SIMD_PIECE; + +define pcodeop NEON_addv; +define pcodeop NEON_aesd; +define pcodeop NEON_aese; +define pcodeop NEON_aesimc; +define pcodeop NEON_aesmc; +define pcodeop NEON_bfdot; +define pcodeop NEON_bfmlalb; +define pcodeop NEON_bfmlalt; +define pcodeop NEON_bfmmla; +define pcodeop NEON_bif; +define pcodeop NEON_bit; +define pcodeop NEON_bsl; +define pcodeop NEON_cls; +define pcodeop NEON_clz; +define pcodeop NEON_cmeq; +define pcodeop NEON_cmge; +define pcodeop NEON_cmgt; +define pcodeop NEON_cmhi; +define pcodeop NEON_cmhs; +define pcodeop NEON_cmle; +define pcodeop NEON_cmlt; +define pcodeop NEON_cmtst; +define pcodeop NEON_cnt; +define pcodeop NEON_ext; +define pcodeop NEON_facge; +define pcodeop NEON_facgt; +define pcodeop NEON_fcadd; +define pcodeop NEON_fcmeq; +define pcodeop NEON_fcmge; +define pcodeop NEON_fcmgt; +define pcodeop NEON_fcmla; +define pcodeop NEON_fcmle; +define pcodeop NEON_fcmlt; +define pcodeop NEON_fcvtzs; +define pcodeop NEON_fcvtzu; +define pcodeop NEON_fmadd; +define pcodeop NEON_fmax; +define pcodeop NEON_fmaxnm; +define pcodeop NEON_fmaxnmp; +define pcodeop NEON_fmaxnmv; +define pcodeop NEON_fmaxp; +define pcodeop NEON_fmaxv; +define pcodeop NEON_fmin; +define pcodeop NEON_fminnm; +define pcodeop NEON_fminnmp; +define pcodeop NEON_fminnmv; +define pcodeop NEON_fminp; +define pcodeop NEON_fminv; +define pcodeop NEON_fmov; +define pcodeop NEON_fmsub; +define pcodeop NEON_fmulx; +define pcodeop NEON_fnmadd; +define pcodeop NEON_fnmsub; +define pcodeop NEON_frecpe; +define pcodeop NEON_frecps; +define pcodeop NEON_frecpx; +define pcodeop NEON_frsqrte; +define pcodeop NEON_frsqrts; +define pcodeop NEON_fsqrt; +define pcodeop NEON_neg; +define pcodeop NEON_pmul; +define pcodeop NEON_pmull; +define pcodeop NEON_pmull2; +define pcodeop NEON_raddhn; +define pcodeop NEON_rbit; +define pcodeop NEON_rev16; +define pcodeop NEON_rev32; +define pcodeop NEON_rev64; +define pcodeop NEON_rshrn; +define pcodeop NEON_rshrn2; +define pcodeop NEON_rsubhn; +define pcodeop NEON_rsubhn2; +define pcodeop NEON_saba; +define pcodeop NEON_sabd; +define pcodeop NEON_saddlv; +define pcodeop NEON_scvtf; +define pcodeop NEON_sdot; +define pcodeop NEON_sha1c; +define pcodeop NEON_sha1m; +define pcodeop NEON_sha1p; +define pcodeop NEON_sha1su0; +define pcodeop NEON_sha1su1; +define pcodeop NEON_sha256h; +define pcodeop NEON_sha256h2; +define pcodeop NEON_sha256su0; +define pcodeop NEON_sha256su1; +define pcodeop NEON_sha512h; +define pcodeop NEON_sha512h2; +define pcodeop NEON_sha512su0; +define pcodeop NEON_sha512su1; +define pcodeop NEON_shadd; +define pcodeop NEON_shl; +define pcodeop NEON_shsub; +define pcodeop NEON_sli; +define pcodeop NEON_sm3partw1; +define pcodeop NEON_sm3partw2; +define pcodeop NEON_sm3ss1; +define pcodeop NEON_sm3tt1a; +define pcodeop NEON_sm3tt1b; +define pcodeop NEON_sm3tt2a; +define pcodeop NEON_sm3tt2b; +define pcodeop NEON_sm4e; +define pcodeop NEON_sm4ekey; +define pcodeop NEON_smax; +define pcodeop NEON_smaxp; +define pcodeop NEON_smaxv; +define pcodeop NEON_smin; +define pcodeop NEON_sminp; +define pcodeop NEON_sminv; +define pcodeop NEON_smmla; +define pcodeop NEON_sqadd; +define pcodeop NEON_sqdmulh; +define pcodeop NEON_sqdmull; +define pcodeop NEON_sqrdml_as_h; +define pcodeop NEON_sqrdmulh; +define pcodeop NEON_sqrshl; +define pcodeop NEON_sqrshrn; +define pcodeop NEON_sqrshrn2; +define pcodeop NEON_sqrshrun; +define pcodeop NEON_sqrshrun2; +define pcodeop NEON_sqshl; +define pcodeop NEON_sqshlu; +define pcodeop NEON_sqshrn; +define pcodeop NEON_sqshrn2; +define pcodeop NEON_sqshrun; +define pcodeop NEON_sqshrun2; +define pcodeop NEON_sqsub; +define pcodeop NEON_sqxtn; +define pcodeop NEON_sqxtn2; +define pcodeop NEON_sqxtun; +define pcodeop NEON_sqxtun2; +define pcodeop NEON_srhadd; +define pcodeop NEON_sri; +define pcodeop NEON_srshl; +define pcodeop NEON_srshr; +define pcodeop NEON_sshl; +define pcodeop NEON_sshr; +define pcodeop NEON_sudot; +define pcodeop NEON_uaba; +define pcodeop NEON_uabd; +define pcodeop NEON_uaddlv; +define pcodeop NEON_ucvtf; +define pcodeop NEON_udot; +define pcodeop NEON_uhadd; +define pcodeop NEON_uhsub; +define pcodeop NEON_umax; +define pcodeop NEON_umaxp; +define pcodeop NEON_umaxv; +define pcodeop NEON_umin; +define pcodeop NEON_uminp; +define pcodeop NEON_uminv; +define pcodeop NEON_ummla; +define pcodeop NEON_umull; +define pcodeop NEON_uqadd; +define pcodeop NEON_uqrshl; +define pcodeop NEON_uqrshrn; +define pcodeop NEON_uqrshrn2; +define pcodeop NEON_uqshl; +define pcodeop NEON_uqshrn; +define pcodeop NEON_uqshrn2; +define pcodeop NEON_uqsub; +define pcodeop NEON_uqxtn; +define pcodeop NEON_uqxtn2; +define pcodeop NEON_urecpe; +define pcodeop NEON_urhadd; +define pcodeop NEON_urshl; +define pcodeop NEON_urshr; +define pcodeop NEON_ursqrte; +define pcodeop NEON_usdot; +define pcodeop NEON_ushl; +define pcodeop NEON_usmmla; +define pcodeop NEON_usqadd; + +# These pseudo ops are automatically generated + +define pcodeop SVE_abs; +define pcodeop SVE_add; +define pcodeop SVE_addpl; +define pcodeop SVE_addvl; +define pcodeop SVE_adr; +define pcodeop SVE_and; +define pcodeop SVE_ands; +define pcodeop SVE_andv; +define pcodeop SVE_asr; +define pcodeop SVE_asrd; +define pcodeop SVE_asrr; +define pcodeop SVE_bic; +define pcodeop SVE_bics; +define pcodeop SVE_brka; +define pcodeop SVE_brkas; +define pcodeop SVE_brkb; +define pcodeop SVE_brkbs; +define pcodeop SVE_brkn; +define pcodeop SVE_brkns; +define pcodeop SVE_brkpa; +define pcodeop SVE_brkpas; +define pcodeop SVE_brkpb; +define pcodeop SVE_brkpbs; +define pcodeop SVE_clasta; +define pcodeop SVE_clastb; +define pcodeop SVE_cls; +define pcodeop SVE_clz; +define pcodeop SVE_cmpeq; +define pcodeop SVE_cmpge; +define pcodeop SVE_cmpgt; +define pcodeop SVE_cmphi; +define pcodeop SVE_cmphs; +define pcodeop SVE_cmple; +define pcodeop SVE_cmplo; +define pcodeop SVE_cmpls; +define pcodeop SVE_cmplt; +define pcodeop SVE_cmpne; +define pcodeop SVE_cnot; +define pcodeop SVE_cnt; +define pcodeop SVE_cntb; +define pcodeop SVE_cntd; +define pcodeop SVE_cnth; +define pcodeop SVE_cntp; +define pcodeop SVE_cntw; +define pcodeop SVE_compact; +define pcodeop SVE_cpy; +define pcodeop SVE_ctermeq; +define pcodeop SVE_ctermne; +define pcodeop SVE_decb; +define pcodeop SVE_decd; +define pcodeop SVE_dech; +define pcodeop SVE_decp; +define pcodeop SVE_decw; +define pcodeop SVE_dup; +define pcodeop SVE_dupm; +define pcodeop SVE_eon; +define pcodeop SVE_eor; +define pcodeop SVE_eors; +define pcodeop SVE_eorv; +define pcodeop SVE_ext; +define pcodeop SVE_fabd; +define pcodeop SVE_fabs; +define pcodeop SVE_facge; +define pcodeop SVE_facgt; +define pcodeop SVE_fadd; +define pcodeop SVE_fadda; +define pcodeop SVE_faddv; +define pcodeop SVE_fcadd; +define pcodeop SVE_fcmeq; +define pcodeop SVE_fcmge; +define pcodeop SVE_fcmgt; +define pcodeop SVE_fcmla; +define pcodeop SVE_fcmle; +define pcodeop SVE_fcmlt; +define pcodeop SVE_fcmne; +define pcodeop SVE_fcmuo; +define pcodeop SVE_fcpy; +define pcodeop SVE_fcvt; +define pcodeop SVE_fcvtzs; +define pcodeop SVE_fcvtzu; +define pcodeop SVE_fdiv; +define pcodeop SVE_fdivr; +define pcodeop SVE_fdup; +define pcodeop SVE_fexpa; +define pcodeop SVE_fmad; +define pcodeop SVE_fmax; +define pcodeop SVE_fmaxnm; +define pcodeop SVE_fmaxnmv; +define pcodeop SVE_fmaxv; +define pcodeop SVE_fmin; +define pcodeop SVE_fminnm; +define pcodeop SVE_fminnmv; +define pcodeop SVE_fminv; +define pcodeop SVE_fmla; +define pcodeop SVE_fmls; +define pcodeop SVE_fmov; +define pcodeop SVE_fmsb; +define pcodeop SVE_fmul; +define pcodeop SVE_fmulx; +define pcodeop SVE_fneg; +define pcodeop SVE_fnmad; +define pcodeop SVE_fnmla; +define pcodeop SVE_fnmls; +define pcodeop SVE_fnmsb; +define pcodeop SVE_frecpe; +define pcodeop SVE_frecps; +define pcodeop SVE_frecpx; +define pcodeop SVE_frinta; +define pcodeop SVE_frinti; +define pcodeop SVE_frintm; +define pcodeop SVE_frintn; +define pcodeop SVE_frintp; +define pcodeop SVE_frintx; +define pcodeop SVE_frintz; +define pcodeop SVE_frsqrte; +define pcodeop SVE_frsqrts; +define pcodeop SVE_fscale; +define pcodeop SVE_fsqrt; +define pcodeop SVE_fsub; +define pcodeop SVE_fsubr; +define pcodeop SVE_ftmad; +define pcodeop SVE_ftsmul; +define pcodeop SVE_ftssel; +define pcodeop SVE_incb; +define pcodeop SVE_incd; +define pcodeop SVE_inch; +define pcodeop SVE_incp; +define pcodeop SVE_incw; +define pcodeop SVE_index; +define pcodeop SVE_insr; +define pcodeop SVE_lasta; +define pcodeop SVE_lastb; +define pcodeop SVE_ld1b; +define pcodeop SVE_ld1d; +define pcodeop SVE_ld1h; +define pcodeop SVE_ld1rb; +define pcodeop SVE_ld1rd; +define pcodeop SVE_ld1rh; +define pcodeop SVE_ld1rqb; +define pcodeop SVE_ld1rqd; +define pcodeop SVE_ld1rqh; +define pcodeop SVE_ld1rqw; +define pcodeop SVE_ld1rsb; +define pcodeop SVE_ld1rsh; +define pcodeop SVE_ld1rsw; +define pcodeop SVE_ld1rw; +define pcodeop SVE_ld1sb; +define pcodeop SVE_ld1sh; +define pcodeop SVE_ld1sw; +define pcodeop SVE_ld1w; +define pcodeop SVE_ld2b; +define pcodeop SVE_ld2d; +define pcodeop SVE_ld2h; +define pcodeop SVE_ld2w; +define pcodeop SVE_ld3b; +define pcodeop SVE_ld3d; +define pcodeop SVE_ld3h; +define pcodeop SVE_ld3w; +define pcodeop SVE_ld4b; +define pcodeop SVE_ld4d; +define pcodeop SVE_ld4h; +define pcodeop SVE_ld4w; +define pcodeop SVE_ldff1b; +define pcodeop SVE_ldff1d; +define pcodeop SVE_ldff1h; +define pcodeop SVE_ldff1sb; +define pcodeop SVE_ldff1sh; +define pcodeop SVE_ldff1sw; +define pcodeop SVE_ldff1w; +define pcodeop SVE_ldnf1b; +define pcodeop SVE_ldnf1d; +define pcodeop SVE_ldnf1h; +define pcodeop SVE_ldnf1sb; +define pcodeop SVE_ldnf1sh; +define pcodeop SVE_ldnf1sw; +define pcodeop SVE_ldnf1w; +define pcodeop SVE_ldnt1b; +define pcodeop SVE_ldnt1d; +define pcodeop SVE_ldnt1h; +define pcodeop SVE_ldnt1w; +define pcodeop SVE_ldr; +define pcodeop SVE_lsl; +define pcodeop SVE_lslr; +define pcodeop SVE_lsr; +define pcodeop SVE_lsrr; +define pcodeop SVE_mad; +define pcodeop SVE_mla; +define pcodeop SVE_mls; +define pcodeop SVE_movprfx; +define pcodeop SVE_msb; +define pcodeop SVE_mul; +define pcodeop SVE_nand; +define pcodeop SVE_nands; +define pcodeop SVE_neg; +define pcodeop SVE_nor; +define pcodeop SVE_nors; +define pcodeop SVE_not; +define pcodeop SVE_orn; +define pcodeop SVE_orns; +define pcodeop SVE_orr; +define pcodeop SVE_orrs; +define pcodeop SVE_orv; +define pcodeop SVE_pfalse; +define pcodeop SVE_pfirst; +define pcodeop SVE_pnext; +define pcodeop SVE_prfb; +define pcodeop SVE_prfd; +define pcodeop SVE_prfh; +define pcodeop SVE_prfw; +define pcodeop SVE_ptest; +define pcodeop SVE_ptrue; +define pcodeop SVE_ptrues; +define pcodeop SVE_punpkhi; +define pcodeop SVE_punpklo; +define pcodeop SVE_rbit; +define pcodeop SVE_rdffr; +define pcodeop SVE_rdffrs; +define pcodeop SVE_rdvl; +define pcodeop SVE_rev; +define pcodeop SVE_revb; +define pcodeop SVE_revh; +define pcodeop SVE_revw; +define pcodeop SVE_sabd; +define pcodeop SVE_saddv; +define pcodeop SVE_scvtf; +define pcodeop SVE_sdiv; +define pcodeop SVE_sdivr; +define pcodeop SVE_sdot; +define pcodeop SVE_sel; +define pcodeop SVE_smax; +define pcodeop SVE_smaxv; +define pcodeop SVE_smin; +define pcodeop SVE_sminv; +define pcodeop SVE_smulh; +define pcodeop SVE_splice; +define pcodeop SVE_sqadd; +define pcodeop SVE_sqdecb; +define pcodeop SVE_sqdecd; +define pcodeop SVE_sqdech; +define pcodeop SVE_sqdecp; +define pcodeop SVE_sqdecw; +define pcodeop SVE_sqincb; +define pcodeop SVE_sqincd; +define pcodeop SVE_sqinch; +define pcodeop SVE_sqincp; +define pcodeop SVE_sqincw; +define pcodeop SVE_sqsub; +define pcodeop SVE_st1b; +define pcodeop SVE_st1d; +define pcodeop SVE_st1h; +define pcodeop SVE_st1w; +define pcodeop SVE_st2b; +define pcodeop SVE_st2d; +define pcodeop SVE_st2h; +define pcodeop SVE_st2w; +define pcodeop SVE_st3b; +define pcodeop SVE_st3d; +define pcodeop SVE_st3h; +define pcodeop SVE_st3w; +define pcodeop SVE_st4b; +define pcodeop SVE_st4d; +define pcodeop SVE_st4h; +define pcodeop SVE_st4w; +define pcodeop SVE_stnt1b; +define pcodeop SVE_stnt1d; +define pcodeop SVE_stnt1h; +define pcodeop SVE_stnt1w; +define pcodeop SVE_str; +define pcodeop SVE_sub; +define pcodeop SVE_subr; +define pcodeop SVE_sunpkhi; +define pcodeop SVE_sunpklo; +define pcodeop SVE_sxtb; +define pcodeop SVE_sxth; +define pcodeop SVE_sxtw; +define pcodeop SVE_tbl; +define pcodeop SVE_trn1; +define pcodeop SVE_trn2; +define pcodeop SVE_uabd; +define pcodeop SVE_uaddv; +define pcodeop SVE_ucvtf; +define pcodeop SVE_udiv; +define pcodeop SVE_udivr; +define pcodeop SVE_udot; +define pcodeop SVE_umax; +define pcodeop SVE_umaxv; +define pcodeop SVE_umin; +define pcodeop SVE_uminv; +define pcodeop SVE_umulh; +define pcodeop SVE_uqadd; +define pcodeop SVE_uqdecb; +define pcodeop SVE_uqdecd; +define pcodeop SVE_uqdech; +define pcodeop SVE_uqdecp; +define pcodeop SVE_uqdecw; +define pcodeop SVE_uqincb; +define pcodeop SVE_uqincd; +define pcodeop SVE_uqinch; +define pcodeop SVE_uqincp; +define pcodeop SVE_uqincw; +define pcodeop SVE_uqsub; +define pcodeop SVE_uunpkhi; +define pcodeop SVE_uunpklo; +define pcodeop SVE_uxtb; +define pcodeop SVE_uxth; +define pcodeop SVE_uxtw; +define pcodeop SVE_uzp1; +define pcodeop SVE_uzp2; +define pcodeop SVE_whilele; +define pcodeop SVE_whilelo; +define pcodeop SVE_whilels; +define pcodeop SVE_whilelt; +define pcodeop SVE_wrffr; +define pcodeop SVE_zip1; +define pcodeop SVE_zip2; + +# SECTION macros + +# begin macros related to memory-tagging + +macro AllocationTagFromAddress(result, op) +{ + # Summary: Sometimes the decompiler won't show this, but that's usually okay. + # + # A potential downside to actually implementing this, rather than using a pseudo-op, + # is that the whole operation can get optimized out to zero by the decompiler when + # tags are being ignored/non-populated by the user. (This zero-tagging is helped along by + # SetPtrTag being a pseudo-op rather than a macro, which is done to preserve data-flow.) + # The optimization makes it harder to tell that tag-related things are happening; + # however, it's arguably convenient to omit a bunch of tag-related stuff when tags + # are being ignored by the user. + + result = (op >> 56) & 0xf; + # decompiler output: return unaff_x30 | 1 << ((ulonglong)register0x00000008 >> 0x38 & 0xf); + # An alternate implementation is the following, which has the downside of adding at least one extra length conversion: + # result = zext(op[56,4]); + # decompiler output: return unaff_x30 | 1 << (ulonglong)((byte)((ulonglong)register0x00000008 >> 0x38) & 0xf); +} + +macro Align(value, sze) +{ + value = value & ~(sze - 1); +} + +macro RequireGranuleAlignment(addr) +{ + misalignment:8 = addr & ($(TAG_GRANULE) - 1); + if (misalignment == 0) goto ; + AlignmentFault(); + +} + +macro Or2BytesWithExcludedTags(tmp) +{ + tmp = (tmp | gcr_el1.exclude) & 0xffff; +} + +# end of memory-tagging macros + +macro addflags(op1, op2) +{ + tmpCY = carry(op1, op2); + tmpOV = scarry(op1, op2); +} + +macro add_with_carry_flags(op1,op2){ + local carry_in = zext(CY); + local tempResult = op1 + op2; + tmpCY = carry(op1,op2) || carry(tempResult, carry_in); + tmpOV = scarry(op1,op2) ^^ scarry(tempResult, carry_in); +} + +macro affectflags() +{ + NG = tmpNG; ZR = tmpZR; CY = tmpCY; OV = tmpOV; +} + +macro affectLflags() +{ + NG = tmpNG; ZR = tmpZR; CY = 0; OV = 0; +} + +# NOTE unlike x86, carry flag is SET if there is NO borrow +macro subflags(op1, op2) +{ + tmpCY = op1 >= op2; + tmpOV = sborrow(op1, op2); +} + +# Special case when the first op of the macro call is 0 +macro subflags0(op2) +{ + tmpCY = 0 == op2; + tmpOV = sborrow(0, op2); +} + +macro logicflags() +{ + tmpCY = shift_carry; + tmpOV = OV; +} + +macro CVunaffected() +{ + tmpCY = CY; + tmpOV = OV; +} + +macro resultflags(result) +{ + tmpNG = result s< 0; + tmpZR = result == 0; +} + +macro fcomp(a, b) +{ + NG = a f< b; + ZR = a f== b; + CY = a f>= b; + OV = 0; +} + +macro ftestNAN(a, b) +{ + NG = 0; + ZR = 0; + CY = 0; + OV = 0; + tst:1 = nan(a) || nan(b); + if (tst) goto inst_next; +} + +macro ROR32(out, val, rotate) +{ + out = ( val >> rotate) | ( val << ( 32 - rotate ) ); +} + +macro ROR64(out, val, rotate) +{ + out = ( val >> rotate) | ( val << ( 64 - rotate ) ); +} + +macro selectCC(result, val1, val2, condition) +{ + result = (zext(condition) * val1) + (zext(!condition) * val2); +} + +macro setCC_NZCV(condMask) +{ + NG = (condMask & 0x8) == 0x8; + ZR = (condMask & 0x4) == 0x4; + CY = (condMask & 0x2) == 0x2; + OV = (condMask & 0x1) == 0x1; +} + +macro set_NZCV(value, condMask) +{ + setNG:1 = (condMask & 0x8) == 0x8; + NG = ((setNG==0) * NG) | ((setNG==1) * (((value >> 3) & 1) ==1)); + setZR:1 = (condMask & 0x4) == 0x4; + ZR = ((setZR==0) * NG) | ((setZR==1) * (((value >> 2) & 1) ==1)); + setCY:1 = (condMask & 0x2) == 0x2; + CY = ((setCY==0) * NG) | ((setCY==1) * (((value >> 1) & 1) == 1)); + setOV:1 = (condMask & 0x1) == 0x1; + OV = ((setOV==0) * NG) | ((setOV==1) * (((value >> 0) & 1) == 1)); +} + +# Macro to access simd lanes + +# Macros to zero the high bits of the Z or Q registers +# These are friendlier to the decompiler + +macro zext_zb(reg) +{ + reg[8,56] = 0; + reg[64,64] = 0; + reg[128,64] = 0; + reg[192,64] = 0; +} + +macro zext_zh(reg) +{ + reg[16,48] = 0; + reg[64,64] = 0; + reg[128,64] = 0; + reg[192,64] = 0; +} + +macro zext_zs(reg) +{ + reg[32,32] = 0; + reg[64,64] = 0; + reg[128,64] = 0; + reg[192,64] = 0; +} + +macro zext_zd(reg) +{ + reg[64,64] = 0; + reg[128,64] = 0; + reg[192,64] = 0; +} + +macro zext_zq(reg) +{ + reg[128,64] = 0; + reg[192,64] = 0; +} + +macro zext_rb(reg) +{ + reg[8,56] = 0; +} + +macro zext_rh(reg) +{ + reg[16,48] = 0; +} + +macro zext_rs(reg) +{ + reg[32,32] = 0; +} + +# SECTION instructions + +:^instruction +is ImmS_ImmR_TestSet=0 & ImmR & ImmS & instruction +[ + ImmS_LT_ImmR = (((ImmS - ImmR) >> 6) $and 1); + ImmS_EQ_ImmR = ~((((ImmS - ImmR) >> 6) $and 1) | (((ImmR - ImmS) >> 6) $and 1)); + # For ubfm, lsl is the preferred alias when imms + 1 == immr, so we must subtract an extra one + # to determine when ubfiz is the preferred alias. + ImmS_LT_ImmR_minus_1 = (((ImmS - (ImmR - 1)) >> 6) & 0x1) & (((ImmS - (ImmR - 1)) >> 7) & 0x1); + ImmS_ne_1f = (((ImmS - 0x1f) >> 6) & 0x1) | (((0x1f - ImmS) >> 6) & 0x1); + ImmS_ne_3f = (((ImmS - 0x3f) >> 6) & 0x1) | (((0x3f - ImmS) >> 6) & 0x1); + ImmS_ImmR_TestSet=1; +]{} + +with : ImmS_ImmR_TestSet=1 { + +@include "AARCH64_base_PACoptions.sinc" + +@include "AARCH64base.sinc" +@include "AARCH64neon.sinc" +@include "AARCH64ldst.sinc" +@include "AARCH64sve.sinc" + +# TODO These are placeholders until the correction instruction implementations can be found + +:NotYetImplemented_UNK1 +is b_0031=0xe7ffdeff +unimpl + +:NotYetImplemented_UNK2 +is b_0031=0x00200820 +unimpl + +:NotYetImplemented_UNK3 +is b_0031=0x00200c20 +unimpl + +} # end with ImmS_ImmR_TestSet=1 + diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64ldst.sinc b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64ldst.sinc new file mode 100644 index 0000000..28e0b75 --- /dev/null +++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64ldst.sinc @@ -0,0 +1,10258 @@ +# C7.2.162 LD1 (multiple structures) page C7-1359 line 78995 KEEPWITH +# INFO This file automatically generated by andre on Fri Jun 8 10:47:29 2018 +# INFO Direct edits to this file may be lost in future updates +# INFO Command line arguments: ['../../../ProcessorTest/test/andre/scrape/a64ldst.py'] + +ldst_imm: tmp is b_24=1 & b_21=0 & b_15=0 & b_14=0 & b_13=0 [ tmp = 1; ] { } +ldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=1 & b_13=0 & b_12=0 & b_11=0 & b_10=0 [ tmp = 1; ] { } +ldst_imm: tmp is b_24=1 & b_21=1 & b_15=0 & b_14=0 & b_13=0 [ tmp = 2; ] { } +ldst_imm: tmp is b_24=1 & b_21=0 & b_15=0 & b_14=1 & b_13=0 & b_10=0 [ tmp = 2; ] { } +ldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=1 & b_13=0 & b_12=0 & b_11=0 & b_10=1 [ tmp = 2; ] { } +ldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=1 & b_13=0 & b_12=0 & b_11=0 & b_10=0 [ tmp = 2; ] { } +ldst_imm: tmp is b_24=1 & b_21=0 & b_15=0 & b_14=0 & b_13=1 [ tmp = 3; ] { } +ldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=1 & b_13=1 & b_12=0 & b_11=0 & b_10=0 [ tmp = 3; ] { } +ldst_imm: tmp is b_24=1 & b_21=1 & b_15=0 & b_14=0 & b_13=1 [ tmp = 4; ] { } +ldst_imm: tmp is b_24=1 & b_21=1 & b_15=0 & b_14=1 & b_13=0 & b_10=0 [ tmp = 4; ] { } +ldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=0 & b_13=0 & b_11=0 & b_10=0 [ tmp = 4; ] { } +ldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=1 & b_13=0 & b_12=0 & b_11=1 & b_10=0 [ tmp = 4; ] { } +ldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=1 & b_13=0 & b_12=0 & b_11=0 & b_10=1 [ tmp = 4; ] { } +ldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=1 & b_13=1 & b_12=0 & b_11=0 & b_10=0 [ tmp = 4; ] { } +ldst_imm: tmp is b_24=1 & b_21=0 & b_15=0 & b_14=1 & b_13=1 & b_10=0 [ tmp = 6; ] { } +ldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=1 & b_13=1 & b_12=0 & b_11=0 & b_10=1 [ tmp = 6; ] { } +ldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=0 & b_14=1 & b_13=1 & b_12=1 [ tmp = 8; ] { } +ldst_imm: tmp is b_24=1 & b_21=1 & b_15=0 & b_14=1 & b_13=1 & b_10=0 [ tmp = 8; ] { } +ldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=0 & b_13=0 & b_11=0 & b_10=0 [ tmp = 8; ] { } +ldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=0 & b_13=0 & b_12=0 & b_11=0 & b_10=1 [ tmp = 8; ] { } +ldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=1 & b_13=0 & b_12=0 & b_11=1 & b_10=1 [ tmp = 8; ] { } +ldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=1 & b_13=0 & b_12=0 & b_11=1 & b_10=0 [ tmp = 8; ] { } +ldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=1 & b_13=1 & b_12=0 & b_11=0 & b_10=1 [ tmp = 8; ] { } +ldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=0 & b_13=1 & b_11=0 & b_10=0 [ tmp = 12; ] { } +ldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=1 & b_13=1 & b_12=0 & b_11=1 & b_10=0 [ tmp = 12; ] { } +ldst_imm: tmp is b_30=1 & b_24=0 & b_21=0 & b_15=0 & b_14=1 & b_13=1 & b_12=1 [ tmp = 16; ] { } +ldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=1 & b_14=0 & b_12=0 & b_11=0 [ tmp = 16; ] { } +ldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=1 & b_14=0 & b_12=0 & b_11=1 & b_10=0 [ tmp = 16; ] { } +ldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=1 & b_14=0 & b_13=1 & b_12=0 & b_11=1 & b_10=1 [ tmp = 16; ] { } +ldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=0 & b_13=0 & b_12=0 & b_11=0 & b_10=1 [ tmp = 16; ] { } +ldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=0 & b_13=1 & b_11=0 & b_10=0 [ tmp = 16; ] { } +ldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=1 & b_13=0 & b_12=0 & b_11=1 & b_10=1 [ tmp = 16; ] { } +ldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=1 & b_13=1 & b_12=0 & b_11=1 & b_10=0 [ tmp = 16; ] { } +ldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=0 & b_14=1 & b_12=0 & b_11=0 [ tmp = 24; ] { } +ldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=0 & b_14=1 & b_12=0 & b_11=1 & b_10=0 [ tmp = 24; ] { } +ldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=0 & b_14=1 & b_13=1 & b_12=0 & b_11=1 & b_10=1 [ tmp = 24; ] { } +ldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=0 & b_13=1 & b_12=0 & b_11=0 & b_10=1 [ tmp = 24; ] { } +ldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=1 & b_13=1 & b_12=0 & b_11=1 & b_10=1 [ tmp = 24; ] { } +ldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=0 & b_14=0 & b_12=0 & b_11=0 [ tmp = 32; ] { } +ldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=0 & b_14=0 & b_12=0 & b_11=1 & b_10=0 [ tmp = 32; ] { } +ldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=0 & b_14=0 & b_13=1 & b_12=0 & b_11=1 & b_10=1 [ tmp = 32; ] { } +ldst_imm: tmp is b_30=1 & b_24=0 & b_21=0 & b_15=1 & b_14=0 & b_12=0 [ tmp = 32; ] { } +ldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=0 & b_13=1 & b_12=0 & b_11=0 & b_10=1 [ tmp = 32; ] { } +ldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=1 & b_13=1 & b_12=0 & b_11=1 & b_10=1 [ tmp = 32; ] { } +ldst_imm: tmp is b_30=1 & b_24=0 & b_21=0 & b_15=0 & b_14=1 & b_12=0 [ tmp = 48; ] { } +ldst_imm: tmp is b_30=1 & b_24=0 & b_21=0 & b_15=0 & b_14=0 & b_12=0 [ tmp = 64; ] { } + +ldst_wback: "" is b_23=0 & b_1620=0b00000 { } +ldst_wback: ", #"^ldst_imm is b_23=1 & b_1620=0b11111 & Rn_GPR64xsp & ldst_imm { Rn_GPR64xsp = tmp_ldXn; } +ldst_wback: ", "^Rm_GPR64 is b_23=1 & Rn_GPR64xsp & Rm_GPR64 { Rn_GPR64xsp = Rm_GPR64; } + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x0c402000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.8B, Vt2.8B, Vt3.8B, Vt4.8B}, [Xn|SP] [, wback] + +:ld1 {vVt^".8B", vVtt^".8B", vVttt^".8B", vVtttt^".8B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0010 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR64[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR64[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR64[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR64[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR64[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR64[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR64[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR64[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x0c402400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.4H, Vt2.4H, Vt3.4H, Vt4.4H}, [Xn|SP] [, wback] + +:ld1 {vVt^".4H", vVtt^".4H", vVttt^".4H", vVtttt^".4H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0010 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR64[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR64[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR64[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR64[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR64[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR64[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR64[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR64[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR64[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR64[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR64[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR64[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR64[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR64[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR64[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x0c402800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.2S, Vt2.2S, Vt3.2S, Vt4.2S}, [Xn|SP] [, wback] + +:ld1 {vVt^".2S", vVtt^".2S", vVttt^".2S", vVtttt^".2S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0010 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR64[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR64[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR64[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR64[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR64[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtttt_VPR64[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtttt_VPR64[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x0c402c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.1D, Vt2.1D, Vt3.1D, Vt4.1D}, [Xn|SP] [, wback] + +:ld1 {vVt^".1D", vVtt^".1D", vVttt^".1D", vVtttt^".1D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0010 & b_1011=0b11 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtt_VPR64[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rttt_VPR64[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtttt_VPR64[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x4c402000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.16B, Vt2.16B, Vt3.16B, Vt4.16B}, [Xn|SP] [, wback] + +:ld1 {vVt^".16B", vVtt^".16B", vVttt^".16B", vVtttt^".16B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0010 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x4c402400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.8H, Vt2.8H, Vt3.8H, Vt4.8H}, [Xn|SP] [, wback] + +:ld1 {vVt^".8H", vVtt^".8H", vVttt^".8H", vVtttt^".8H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0010 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x4c402800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.4S, Vt2.4S, Vt3.4S, Vt4.4S}, [Xn|SP] [, wback] + +:ld1 {vVt^".4S", vVtt^".4S", vVttt^".4S", vVtttt^".4S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0010 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtttt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtttt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtttt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtttt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x4c402c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.2D, Vt2.2D, Vt3.2D, Vt4.2D}, [Xn|SP] [, wback] + +:ld1 {vVt^".2D", vVtt^".2D", vVttt^".2D", vVtttt^".2D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0010 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rttt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rttt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtttt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtttt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x0c406000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.8B, Vt2.8B, Vt3.8B}, [Xn|SP] [, wback] + +:ld1 {vVt^".8B", vVtt^".8B", vVttt^".8B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0110 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x0c406400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.4H, Vt2.4H, Vt3.4H}, [Xn|SP] [, wback] + +:ld1 {vVt^".4H", vVtt^".4H", vVttt^".4H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0110 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR64[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR64[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR64[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR64[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR64[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR64[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR64[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR64[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR64[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR64[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR64[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x0c406800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.2S, Vt2.2S, Vt3.2S}, [Xn|SP] [, wback] + +:ld1 {vVt^".2S", vVtt^".2S", vVttt^".2S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0110 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR64[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR64[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR64[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR64[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR64[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x0c406c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.1D, Vt2.1D, Vt3.1D}, [Xn|SP] [, wback] + +:ld1 {vVt^".1D", vVtt^".1D", vVttt^".1D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0110 & b_1011=0b11 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtt_VPR64[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rttt_VPR64[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x4c406000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.16B, Vt2.16B, Vt3.16B}, [Xn|SP] [, wback] + +:ld1 {vVt^".16B", vVtt^".16B", vVttt^".16B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0110 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x4c406400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.8H, Vt2.8H, Vt3.8H}, [Xn|SP] [, wback] + +:ld1 {vVt^".8H", vVtt^".8H", vVttt^".8H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0110 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x4c406800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.4S, Vt2.4S, Vt3.4S}, [Xn|SP] [, wback] + +:ld1 {vVt^".4S", vVtt^".4S", vVttt^".4S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0110 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x4c406c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.2D, Vt2.2D, Vt3.2D}, [Xn|SP] [, wback] + +:ld1 {vVt^".2D", vVtt^".2D", vVttt^".2D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0110 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rttt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rttt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x0c407000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.8B}, [Xn|SP] [, wback] + +:ld1 {vVt^".8B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0111 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x0c407400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.4H}, [Xn|SP] [, wback] + +:ld1 {vVt^".4H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0111 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR64[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR64[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR64[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x0c407800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.2S}, [Xn|SP] [, wback] + +:ld1 {vVt^".2S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0111 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR64[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x0c407c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.1D}, [Xn|SP] [, wback] + +:ld1 {vVt^".1D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0111 & b_1011=0b11 & vVt & Rt_VPR64 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x4c407000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.16B}, [Xn|SP] [, wback] + +:ld1 {vVt^".16B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0111 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x4c407400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.8H}, [Xn|SP] [, wback] + +:ld1 {vVt^".8H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0111 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x4c407800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.4S}, [Xn|SP] [, wback] + +:ld1 {vVt^".4S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0111 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x4c407c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.2D}, [Xn|SP] [, wback] + +:ld1 {vVt^".2D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0111 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x0c40a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.8B, Vt2.8B}, [Xn|SP] [, wback] + +:ld1 {vVt^".8B", vVtt^".8B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1010 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x0c40a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.4H, Vt2.4H}, [Xn|SP] [, wback] + +:ld1 {vVt^".4H", vVtt^".4H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1010 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR64[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR64[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR64[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR64[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR64[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR64[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR64[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x0c40a800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.2S, Vt2.2S}, [Xn|SP] [, wback] + +:ld1 {vVt^".2S", vVtt^".2S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1010 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR64[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR64[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR64[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x0c40ac00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.1D, Vt2.1D}, [Xn|SP] [, wback] + +:ld1 {vVt^".1D", vVtt^".1D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1010 & b_1011=0b11 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtt_VPR64[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x4c40a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.16B, Vt2.16B}, [Xn|SP] [, wback] + +:ld1 {vVt^".16B", vVtt^".16B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1010 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x4c40a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.8H, Vt2.8H}, [Xn|SP] [, wback] + +:ld1 {vVt^".8H", vVtt^".8H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1010 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x4c40a800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.4S, Vt2.4S}, [Xn|SP] [, wback] + +:ld1 {vVt^".4S", vVtt^".4S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1010 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000 +# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000 +# CONSTRUCT x4c40ac00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.2D, Vt2.2D}, [Xn|SP] [, wback] + +:ld1 {vVt^".2D", vVtt^".2D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1010 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x0d400000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.B}[0], [Xn|SP] [, wback] + +:ld1 {vVt^".B"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x0d400400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.B}[1], [Xn|SP] [, wback] + +:ld1 {vVt^".B"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x0d400800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.B}[2], [Xn|SP] [, wback] + +:ld1 {vVt^".B"}[2], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x0d400c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.B}[3], [Xn|SP] [, wback] + +:ld1 {vVt^".B"}[3], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x0d401000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.B}[4], [Xn|SP] [, wback] + +:ld1 {vVt^".B"}[4], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x0d401400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.B}[5], [Xn|SP] [, wback] + +:ld1 {vVt^".B"}[5], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x0d401800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.B}[6], [Xn|SP] [, wback] + +:ld1 {vVt^".B"}[6], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x0d401c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.B}[7], [Xn|SP] [, wback] + +:ld1 {vVt^".B"}[7], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x4d400000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.B}[8], [Xn|SP] [, wback] + +:ld1 {vVt^".B"}[8], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x4d400400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.B}[9], [Xn|SP] [, wback] + +:ld1 {vVt^".B"}[9], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x4d400800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.B}[10], [Xn|SP] [, wback] + +:ld1 {vVt^".B"}[10], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x4d400c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.B}[11], [Xn|SP] [, wback] + +:ld1 {vVt^".B"}[11], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x4d401000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.B}[12], [Xn|SP] [, wback] + +:ld1 {vVt^".B"}[12], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x4d401400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.B}[13], [Xn|SP] [, wback] + +:ld1 {vVt^".B"}[13], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x4d401800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.B}[14], [Xn|SP] [, wback] + +:ld1 {vVt^".B"}[14], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x4d401c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.B}[15], [Xn|SP] [, wback] + +:ld1 {vVt^".B"}[15], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x0d404000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.H}[0], [Xn|SP] [, wback] + +:ld1 {vVt^".H"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b010 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x0d404800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.H}[1], [Xn|SP] [, wback] + +:ld1 {vVt^".H"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b010 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x0d405000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.H}[2], [Xn|SP] [, wback] + +:ld1 {vVt^".H"}[2], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b010 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x0d405800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.H}[3], [Xn|SP] [, wback] + +:ld1 {vVt^".H"}[3], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b010 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x4d404000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.H}[4], [Xn|SP] [, wback] + +:ld1 {vVt^".H"}[4], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b010 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x4d404800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.H}[5], [Xn|SP] [, wback] + +:ld1 {vVt^".H"}[5], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b010 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x4d405000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.H}[6], [Xn|SP] [, wback] + +:ld1 {vVt^".H"}[6], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b010 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x4d405800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.H}[7], [Xn|SP] [, wback] + +:ld1 {vVt^".H"}[7], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b010 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x0d408000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.S}[0], [Xn|SP] [, wback] + +:ld1 {vVt^".S"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b100 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x0d409000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.S}[1], [Xn|SP] [, wback] + +:ld1 {vVt^".S"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b100 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x4d408000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.S}[2], [Xn|SP] [, wback] + +:ld1 {vVt^".S"}[2], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b100 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x4d409000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.S}[3], [Xn|SP] [, wback] + +:ld1 {vVt^".S"}[3], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b100 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x0d408400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.D}[0], [Xn|SP] [, wback] + +:ld1 {vVt^".D"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b100 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x4d408400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld1 {Vt.D}[1], [Xn|SP] [, wback] + +:ld1 {vVt^".D"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b100 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0d40c000/mask=xbffff000 +# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0dc0c000/mask=xbfe0f000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x0d40c000/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld1r {Vt.8B}, [Xn|SP] [, wback] + +:ld1r {vVt^".8B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b110 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:1 = 0; + tmpv = *:1 tmp_ldXn; + Rt_VPR64[0,8] = tmpv; + Rt_VPR64[8,8] = tmpv; + Rt_VPR64[16,8] = tmpv; + Rt_VPR64[24,8] = tmpv; + Rt_VPR64[32,8] = tmpv; + Rt_VPR64[40,8] = tmpv; + Rt_VPR64[48,8] = tmpv; + Rt_VPR64[56,8] = tmpv; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0d40c000/mask=xbffff000 +# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0dc0c000/mask=xbfe0f000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x0d40c400/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld1r {Vt.4H}, [Xn|SP] [, wback] + +:ld1r {vVt^".4H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b110 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:2 = 0; + tmpv = *:2 tmp_ldXn; + Rt_VPR64[0,16] = tmpv; + Rt_VPR64[16,16] = tmpv; + Rt_VPR64[32,16] = tmpv; + Rt_VPR64[48,16] = tmpv; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0d40c000/mask=xbffff000 +# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0dc0c000/mask=xbfe0f000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x0d40c800/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld1r {Vt.2S}, [Xn|SP] [, wback] + +:ld1r {vVt^".2S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b110 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:4 = 0; + tmpv = *:4 tmp_ldXn; + Rt_VPR64[0,32] = tmpv; + Rt_VPR64[32,32] = tmpv; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0d40c000/mask=xbffff000 +# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0dc0c000/mask=xbfe0f000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x0d40cc00/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld1r {Vt.1D}, [Xn|SP] [, wback] + +:ld1r {vVt^".1D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b110 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR64 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:8 = 0; + tmpv = *:8 tmp_ldXn; + Rt_VPR64[0,64] = tmpv; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0d40c000/mask=xbffff000 +# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0dc0c000/mask=xbfe0f000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x4d40c000/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld1r {Vt.16B}, [Xn|SP] [, wback] + +:ld1r {vVt^".16B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b110 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:1 = 0; + tmpv = *:1 tmp_ldXn; + Rt_VPR128[0,8] = tmpv; + Rt_VPR128[8,8] = tmpv; + Rt_VPR128[16,8] = tmpv; + Rt_VPR128[24,8] = tmpv; + Rt_VPR128[32,8] = tmpv; + Rt_VPR128[40,8] = tmpv; + Rt_VPR128[48,8] = tmpv; + Rt_VPR128[56,8] = tmpv; + Rt_VPR128[64,8] = tmpv; + Rt_VPR128[72,8] = tmpv; + Rt_VPR128[80,8] = tmpv; + Rt_VPR128[88,8] = tmpv; + Rt_VPR128[96,8] = tmpv; + Rt_VPR128[104,8] = tmpv; + Rt_VPR128[112,8] = tmpv; + Rt_VPR128[120,8] = tmpv; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0d40c000/mask=xbffff000 +# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0dc0c000/mask=xbfe0f000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x4d40c400/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld1r {Vt.8H}, [Xn|SP] [, wback] + +:ld1r {vVt^".8H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b110 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:2 = 0; + tmpv = *:2 tmp_ldXn; + Rt_VPR128[0,16] = tmpv; + Rt_VPR128[16,16] = tmpv; + Rt_VPR128[32,16] = tmpv; + Rt_VPR128[48,16] = tmpv; + Rt_VPR128[64,16] = tmpv; + Rt_VPR128[80,16] = tmpv; + Rt_VPR128[96,16] = tmpv; + Rt_VPR128[112,16] = tmpv; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0d40c000/mask=xbffff000 +# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0dc0c000/mask=xbfe0f000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x4d40c800/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld1r {Vt.4S}, [Xn|SP] [, wback] + +:ld1r {vVt^".4S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b110 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:4 = 0; + tmpv = *:4 tmp_ldXn; + Rt_VPR128[0,32] = tmpv; + Rt_VPR128[32,32] = tmpv; + Rt_VPR128[64,32] = tmpv; + Rt_VPR128[96,32] = tmpv; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0d40c000/mask=xbffff000 +# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0dc0c000/mask=xbfe0f000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000 +# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000 +# CONSTRUCT x4d40cc00/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld1r {Vt.2D}, [Xn|SP] [, wback] + +:ld1r {vVt^".2D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b110 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:8 = 0; + tmpv = *:8 tmp_ldXn; + Rt_VPR128[0,64] = tmpv; + Rt_VPR128[64,64] = tmpv; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0c408000/mask=xbffff000 +# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0cc08000/mask=xbfe0f000 +# CONSTRUCT x0c408000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.8B, Vt2.8B}, [Xn|SP] [, wback] + +:ld2 {vVt^".8B", vVtt^".8B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1000 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0c408000/mask=xbffff000 +# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0cc08000/mask=xbfe0f000 +# CONSTRUCT x0c408400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.4H, Vt2.4H}, [Xn|SP] [, wback] + +:ld2 {vVt^".4H", vVtt^".4H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1000 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR64[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR64[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR64[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR64[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR64[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR64[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR64[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0c408000/mask=xbffff000 +# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0cc08000/mask=xbfe0f000 +# CONSTRUCT x0c408800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.2S, Vt2.2S}, [Xn|SP] [, wback] + +:ld2 {vVt^".2S", vVtt^".2S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1000 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR64[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR64[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR64[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0c408000/mask=xbffff000 +# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0cc08000/mask=xbfe0f000 +# CONSTRUCT x4c408000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.16B, Vt2.16B}, [Xn|SP] [, wback] + +:ld2 {vVt^".16B", vVtt^".16B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1000 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0c408000/mask=xbffff000 +# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0cc08000/mask=xbfe0f000 +# CONSTRUCT x4c408400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.8H, Vt2.8H}, [Xn|SP] [, wback] + +:ld2 {vVt^".8H", vVtt^".8H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1000 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0c408000/mask=xbffff000 +# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0cc08000/mask=xbfe0f000 +# CONSTRUCT x4c408800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.4S, Vt2.4S}, [Xn|SP] [, wback] + +:ld2 {vVt^".4S", vVtt^".4S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1000 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0c408000/mask=xbffff000 +# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0cc08000/mask=xbfe0f000 +# CONSTRUCT x4c408c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.2D, Vt2.2D}, [Xn|SP] [, wback] + +:ld2 {vVt^".2D", vVtt^".2D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1000 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x0d600000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.B, Vt2.B}[0], [Xn|SP] [, wback] + +:ld2 {vVt^".B", vVtt^".B"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x0d600400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.B, Vt2.B}[1], [Xn|SP] [, wback] + +:ld2 {vVt^".B", vVtt^".B"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x0d600800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.B, Vt2.B}[2], [Xn|SP] [, wback] + +:ld2 {vVt^".B", vVtt^".B"}[2], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x0d600c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.B, Vt2.B}[3], [Xn|SP] [, wback] + +:ld2 {vVt^".B", vVtt^".B"}[3], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x0d601000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.B, Vt2.B}[4], [Xn|SP] [, wback] + +:ld2 {vVt^".B", vVtt^".B"}[4], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x0d601400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.B, Vt2.B}[5], [Xn|SP] [, wback] + +:ld2 {vVt^".B", vVtt^".B"}[5], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x0d601800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.B, Vt2.B}[6], [Xn|SP] [, wback] + +:ld2 {vVt^".B", vVtt^".B"}[6], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x0d601c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.B, Vt2.B}[7], [Xn|SP] [, wback] + +:ld2 {vVt^".B", vVtt^".B"}[7], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x4d600000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.B, Vt2.B}[8], [Xn|SP] [, wback] + +:ld2 {vVt^".B", vVtt^".B"}[8], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x4d600400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.B, Vt2.B}[9], [Xn|SP] [, wback] + +:ld2 {vVt^".B", vVtt^".B"}[9], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x4d600800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.B, Vt2.B}[10], [Xn|SP] [, wback] + +:ld2 {vVt^".B", vVtt^".B"}[10], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x4d600c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.B, Vt2.B}[11], [Xn|SP] [, wback] + +:ld2 {vVt^".B", vVtt^".B"}[11], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x4d601000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.B, Vt2.B}[12], [Xn|SP] [, wback] + +:ld2 {vVt^".B", vVtt^".B"}[12], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x4d601400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.B, Vt2.B}[13], [Xn|SP] [, wback] + +:ld2 {vVt^".B", vVtt^".B"}[13], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x4d601800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.B, Vt2.B}[14], [Xn|SP] [, wback] + +:ld2 {vVt^".B", vVtt^".B"}[14], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x4d601c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.B, Vt2.B}[15], [Xn|SP] [, wback] + +:ld2 {vVt^".B", vVtt^".B"}[15], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x0d604000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.H, Vt2.H}[0], [Xn|SP] [, wback] + +:ld2 {vVt^".H", vVtt^".H"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b010 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x0d604800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.H, Vt2.H}[1], [Xn|SP] [, wback] + +:ld2 {vVt^".H", vVtt^".H"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b010 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x0d605000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.H, Vt2.H}[2], [Xn|SP] [, wback] + +:ld2 {vVt^".H", vVtt^".H"}[2], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b010 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x0d605800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.H, Vt2.H}[3], [Xn|SP] [, wback] + +:ld2 {vVt^".H", vVtt^".H"}[3], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b010 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x4d604000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.H, Vt2.H}[4], [Xn|SP] [, wback] + +:ld2 {vVt^".H", vVtt^".H"}[4], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b010 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x4d604800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.H, Vt2.H}[5], [Xn|SP] [, wback] + +:ld2 {vVt^".H", vVtt^".H"}[5], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b010 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x4d605000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.H, Vt2.H}[6], [Xn|SP] [, wback] + +:ld2 {vVt^".H", vVtt^".H"}[6], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b010 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x4d605800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.H, Vt2.H}[7], [Xn|SP] [, wback] + +:ld2 {vVt^".H", vVtt^".H"}[7], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b010 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x0d608000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.S, Vt2.S}[0], [Xn|SP] [, wback] + +:ld2 {vVt^".S", vVtt^".S"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b100 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x0d609000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.S, Vt2.S}[1], [Xn|SP] [, wback] + +:ld2 {vVt^".S", vVtt^".S"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b100 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x4d608000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.S, Vt2.S}[2], [Xn|SP] [, wback] + +:ld2 {vVt^".S", vVtt^".S"}[2], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b100 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x4d609000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.S, Vt2.S}[3], [Xn|SP] [, wback] + +:ld2 {vVt^".S", vVtt^".S"}[3], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b100 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x0d608400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.D, Vt2.D}[0], [Xn|SP] [, wback] + +:ld2 {vVt^".D", vVtt^".D"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b100 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x4d608400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld2 {Vt.D, Vt2.D}[1], [Xn|SP] [, wback] + +:ld2 {vVt^".D", vVtt^".D"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b100 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0d60c000/mask=xbffff000 +# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0de0c000/mask=xbfe0f000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x0d60c000/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld2r {Vt.8B, Vt2.8B}, [Xn|SP] [, wback] + +:ld2r {vVt^".8B", vVtt^".8B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b110 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:1 = 0; + tmpv = *:1 tmp_ldXn; + Rtt_VPR64[0,8] = tmpv; + Rtt_VPR64[8,8] = tmpv; + Rtt_VPR64[16,8] = tmpv; + Rtt_VPR64[24,8] = tmpv; + Rtt_VPR64[32,8] = tmpv; + Rtt_VPR64[40,8] = tmpv; + Rtt_VPR64[48,8] = tmpv; + Rtt_VPR64[56,8] = tmpv; + tmp_ldXn = tmp_ldXn + 1; + tmpv = *:1 tmp_ldXn; + Rtt_VPR64[0,8] = tmpv; + Rtt_VPR64[8,8] = tmpv; + Rtt_VPR64[16,8] = tmpv; + Rtt_VPR64[24,8] = tmpv; + Rtt_VPR64[32,8] = tmpv; + Rtt_VPR64[40,8] = tmpv; + Rtt_VPR64[48,8] = tmpv; + Rtt_VPR64[56,8] = tmpv; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0d60c000/mask=xbffff000 +# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0de0c000/mask=xbfe0f000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x0d60c400/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld2r {Vt.4H, Vt2.4H}, [Xn|SP] [, wback] + +:ld2r {vVt^".4H", vVtt^".4H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b110 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:2 = 0; + tmpv = *:2 tmp_ldXn; + Rtt_VPR64[0,16] = tmpv; + Rtt_VPR64[16,16] = tmpv; + Rtt_VPR64[32,16] = tmpv; + Rtt_VPR64[48,16] = tmpv; + tmp_ldXn = tmp_ldXn + 2; + tmpv = *:2 tmp_ldXn; + Rtt_VPR64[0,16] = tmpv; + Rtt_VPR64[16,16] = tmpv; + Rtt_VPR64[32,16] = tmpv; + Rtt_VPR64[48,16] = tmpv; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0d60c000/mask=xbffff000 +# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0de0c000/mask=xbfe0f000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x0d60c800/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld2r {Vt.2S, Vt2.2S}, [Xn|SP] [, wback] + +:ld2r {vVt^".2S", vVtt^".2S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b110 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:4 = 0; + tmpv = *:4 tmp_ldXn; + Rtt_VPR64[0,32] = tmpv; + Rtt_VPR64[32,32] = tmpv; + tmp_ldXn = tmp_ldXn + 4; + tmpv = *:4 tmp_ldXn; + Rtt_VPR64[0,32] = tmpv; + Rtt_VPR64[32,32] = tmpv; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0d60c000/mask=xbffff000 +# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0de0c000/mask=xbfe0f000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x0d60cc00/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld2r {Vt.1D, Vt2.1D}, [Xn|SP] [, wback] + +:ld2r {vVt^".1D", vVtt^".1D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b110 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:8 = 0; + tmpv = *:8 tmp_ldXn; + Rtt_VPR64[0,64] = tmpv; + tmp_ldXn = tmp_ldXn + 8; + tmpv = *:8 tmp_ldXn; + Rtt_VPR64[0,64] = tmpv; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0d60c000/mask=xbffff000 +# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0de0c000/mask=xbfe0f000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x4d60c000/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld2r {Vt.16B, Vt2.16B}, [Xn|SP] [, wback] + +:ld2r {vVt^".16B", vVtt^".16B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b110 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:1 = 0; + tmpv = *:1 tmp_ldXn; + Rtt_VPR128[0,8] = tmpv; + Rtt_VPR128[8,8] = tmpv; + Rtt_VPR128[16,8] = tmpv; + Rtt_VPR128[24,8] = tmpv; + Rtt_VPR128[32,8] = tmpv; + Rtt_VPR128[40,8] = tmpv; + Rtt_VPR128[48,8] = tmpv; + Rtt_VPR128[56,8] = tmpv; + Rtt_VPR128[64,8] = tmpv; + Rtt_VPR128[72,8] = tmpv; + Rtt_VPR128[80,8] = tmpv; + Rtt_VPR128[88,8] = tmpv; + Rtt_VPR128[96,8] = tmpv; + Rtt_VPR128[104,8] = tmpv; + Rtt_VPR128[112,8] = tmpv; + Rtt_VPR128[120,8] = tmpv; + tmp_ldXn = tmp_ldXn + 1; + tmpv = *:1 tmp_ldXn; + Rtt_VPR128[0,8] = tmpv; + Rtt_VPR128[8,8] = tmpv; + Rtt_VPR128[16,8] = tmpv; + Rtt_VPR128[24,8] = tmpv; + Rtt_VPR128[32,8] = tmpv; + Rtt_VPR128[40,8] = tmpv; + Rtt_VPR128[48,8] = tmpv; + Rtt_VPR128[56,8] = tmpv; + Rtt_VPR128[64,8] = tmpv; + Rtt_VPR128[72,8] = tmpv; + Rtt_VPR128[80,8] = tmpv; + Rtt_VPR128[88,8] = tmpv; + Rtt_VPR128[96,8] = tmpv; + Rtt_VPR128[104,8] = tmpv; + Rtt_VPR128[112,8] = tmpv; + Rtt_VPR128[120,8] = tmpv; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0d60c000/mask=xbffff000 +# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0de0c000/mask=xbfe0f000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x4d60c400/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld2r {Vt.8H, Vt2.8H}, [Xn|SP] [, wback] + +:ld2r {vVt^".8H", vVtt^".8H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b110 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:2 = 0; + tmpv = *:2 tmp_ldXn; + Rtt_VPR128[0,16] = tmpv; + Rtt_VPR128[16,16] = tmpv; + Rtt_VPR128[32,16] = tmpv; + Rtt_VPR128[48,16] = tmpv; + Rtt_VPR128[64,16] = tmpv; + Rtt_VPR128[80,16] = tmpv; + Rtt_VPR128[96,16] = tmpv; + Rtt_VPR128[112,16] = tmpv; + tmp_ldXn = tmp_ldXn + 2; + tmpv = *:2 tmp_ldXn; + Rtt_VPR128[0,16] = tmpv; + Rtt_VPR128[16,16] = tmpv; + Rtt_VPR128[32,16] = tmpv; + Rtt_VPR128[48,16] = tmpv; + Rtt_VPR128[64,16] = tmpv; + Rtt_VPR128[80,16] = tmpv; + Rtt_VPR128[96,16] = tmpv; + Rtt_VPR128[112,16] = tmpv; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0d60c000/mask=xbffff000 +# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0de0c000/mask=xbfe0f000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x4d60c800/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld2r {Vt.4S, Vt2.4S}, [Xn|SP] [, wback] + +:ld2r {vVt^".4S", vVtt^".4S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b110 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:4 = 0; + tmpv = *:4 tmp_ldXn; + Rtt_VPR128[0,32] = tmpv; + Rtt_VPR128[32,32] = tmpv; + Rtt_VPR128[64,32] = tmpv; + Rtt_VPR128[96,32] = tmpv; + tmp_ldXn = tmp_ldXn + 4; + tmpv = *:4 tmp_ldXn; + Rtt_VPR128[0,32] = tmpv; + Rtt_VPR128[32,32] = tmpv; + Rtt_VPR128[64,32] = tmpv; + Rtt_VPR128[96,32] = tmpv; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0d60c000/mask=xbffff000 +# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0de0c000/mask=xbfe0f000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000 +# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000 +# CONSTRUCT x4d60cc00/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld2r {Vt.2D, Vt2.2D}, [Xn|SP] [, wback] + +:ld2r {vVt^".2D", vVtt^".2D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b110 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:8 = 0; + tmpv = *:8 tmp_ldXn; + Rtt_VPR128[0,64] = tmpv; + Rtt_VPR128[64,64] = tmpv; + tmp_ldXn = tmp_ldXn + 8; + tmpv = *:8 tmp_ldXn; + Rtt_VPR128[0,64] = tmpv; + Rtt_VPR128[64,64] = tmpv; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0c404000/mask=xbffff000 +# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0cc04000/mask=xbfe0f000 +# CONSTRUCT x0c404000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.8B, Vt2.8B, Vt3.8B}, [Xn|SP] [, wback] + +:ld3 {vVt^".8B", vVtt^".8B", vVttt^".8B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0100 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0c404000/mask=xbffff000 +# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0cc04000/mask=xbfe0f000 +# CONSTRUCT x0c404400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.4H, Vt2.4H, Vt3.4H}, [Xn|SP] [, wback] + +:ld3 {vVt^".4H", vVtt^".4H", vVttt^".4H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0100 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR64[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR64[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR64[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR64[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR64[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR64[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR64[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR64[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR64[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR64[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR64[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0c404000/mask=xbffff000 +# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0cc04000/mask=xbfe0f000 +# CONSTRUCT x0c404800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.2S, Vt2.2S, Vt3.2S}, [Xn|SP] [, wback] + +:ld3 {vVt^".2S", vVtt^".2S", vVttt^".2S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0100 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR64[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR64[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR64[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR64[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR64[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0c404000/mask=xbffff000 +# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0cc04000/mask=xbfe0f000 +# CONSTRUCT x4c404000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.16B, Vt2.16B, Vt3.16B}, [Xn|SP] [, wback] + +:ld3 {vVt^".16B", vVtt^".16B", vVttt^".16B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0100 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0c404000/mask=xbffff000 +# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0cc04000/mask=xbfe0f000 +# CONSTRUCT x4c404400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.8H, Vt2.8H, Vt3.8H}, [Xn|SP] [, wback] + +:ld3 {vVt^".8H", vVtt^".8H", vVttt^".8H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0100 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0c404000/mask=xbffff000 +# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0cc04000/mask=xbfe0f000 +# CONSTRUCT x4c404800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.4S, Vt2.4S, Vt3.4S}, [Xn|SP] [, wback] + +:ld3 {vVt^".4S", vVtt^".4S", vVttt^".4S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0100 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0c404000/mask=xbffff000 +# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0cc04000/mask=xbfe0f000 +# CONSTRUCT x4c404c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.2D, Vt2.2D, Vt3.2D}, [Xn|SP] [, wback] + +:ld3 {vVt^".2D", vVtt^".2D", vVttt^".2D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0100 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rttt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rttt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x0d402000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.B, Vt2.B, Vt3.B}[0], [Xn|SP] [, wback] + +:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x0d402400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.B, Vt2.B, Vt3.B}[1], [Xn|SP] [, wback] + +:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x0d402800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.B, Vt2.B, Vt3.B}[2], [Xn|SP] [, wback] + +:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[2], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x0d402c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.B, Vt2.B, Vt3.B}[3], [Xn|SP] [, wback] + +:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[3], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x0d403000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.B, Vt2.B, Vt3.B}[4], [Xn|SP] [, wback] + +:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[4], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x0d403400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.B, Vt2.B, Vt3.B}[5], [Xn|SP] [, wback] + +:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[5], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x0d403800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.B, Vt2.B, Vt3.B}[6], [Xn|SP] [, wback] + +:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[6], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x0d403c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.B, Vt2.B, Vt3.B}[7], [Xn|SP] [, wback] + +:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[7], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x4d402000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.B, Vt2.B, Vt3.B}[8], [Xn|SP] [, wback] + +:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[8], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x4d402400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.B, Vt2.B, Vt3.B}[9], [Xn|SP] [, wback] + +:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[9], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x4d402800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.B, Vt2.B, Vt3.B}[10], [Xn|SP] [, wback] + +:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[10], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x4d402c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.B, Vt2.B, Vt3.B}[11], [Xn|SP] [, wback] + +:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[11], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x4d403000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.B, Vt2.B, Vt3.B}[12], [Xn|SP] [, wback] + +:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[12], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x4d403400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.B, Vt2.B, Vt3.B}[13], [Xn|SP] [, wback] + +:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[13], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x4d403800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.B, Vt2.B, Vt3.B}[14], [Xn|SP] [, wback] + +:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[14], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x4d403c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.B, Vt2.B, Vt3.B}[15], [Xn|SP] [, wback] + +:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[15], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x0d406000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.H, Vt2.H, Vt3.H}[0], [Xn|SP] [, wback] + +:ld3 {vVt^".H", vVtt^".H", vVttt^".H"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b011 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x0d406800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.H, Vt2.H, Vt3.H}[1], [Xn|SP] [, wback] + +:ld3 {vVt^".H", vVtt^".H", vVttt^".H"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b011 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x0d407000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.H, Vt2.H, Vt3.H}[2], [Xn|SP] [, wback] + +:ld3 {vVt^".H", vVtt^".H", vVttt^".H"}[2], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b011 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x0d407800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.H, Vt2.H, Vt3.H}[3], [Xn|SP] [, wback] + +:ld3 {vVt^".H", vVtt^".H", vVttt^".H"}[3], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b011 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x4d406000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.H, Vt2.H, Vt3.H}[4], [Xn|SP] [, wback] + +:ld3 {vVt^".H", vVtt^".H", vVttt^".H"}[4], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b011 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x4d406800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.H, Vt2.H, Vt3.H}[5], [Xn|SP] [, wback] + +:ld3 {vVt^".H", vVtt^".H", vVttt^".H"}[5], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b011 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x4d407000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.H, Vt2.H, Vt3.H}[6], [Xn|SP] [, wback] + +:ld3 {vVt^".H", vVtt^".H", vVttt^".H"}[6], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b011 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x4d407800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.H, Vt2.H, Vt3.H}[7], [Xn|SP] [, wback] + +:ld3 {vVt^".H", vVtt^".H", vVttt^".H"}[7], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b011 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x0d40a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.S, Vt2.S, Vt3.S}[0], [Xn|SP] [, wback] + +:ld3 {vVt^".S", vVtt^".S", vVttt^".S"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b101 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x0d40b000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.S, Vt2.S, Vt3.S}[1], [Xn|SP] [, wback] + +:ld3 {vVt^".S", vVtt^".S", vVttt^".S"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b101 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x4d40a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.S, Vt2.S, Vt3.S}[2], [Xn|SP] [, wback] + +:ld3 {vVt^".S", vVtt^".S", vVttt^".S"}[2], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b101 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x4d40b000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.S, Vt2.S, Vt3.S}[3], [Xn|SP] [, wback] + +:ld3 {vVt^".S", vVtt^".S", vVttt^".S"}[3], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b101 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x0d40a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.D, Vt2.D, Vt3.D}[0], [Xn|SP] [, wback] + +:ld3 {vVt^".D", vVtt^".D", vVttt^".D"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b101 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rttt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x4d40a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld3 {Vt.D, Vt2.D, Vt3.D}[1], [Xn|SP] [, wback] + +:ld3 {vVt^".D", vVtt^".D", vVttt^".D"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b101 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rttt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0d40e000/mask=xbffff000 +# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0dc0e000/mask=xbfe0f000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x0d40e000/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld3r {Vt.8B, Vt2.8B, Vt3.8B}, [Xn|SP] [, wback] + +:ld3r {vVt^".8B", vVtt^".8B", vVttt^".8B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b111 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:1 = 0; + tmpv = *:1 tmp_ldXn; + Rttt_VPR64[0,8] = tmpv; + Rttt_VPR64[8,8] = tmpv; + Rttt_VPR64[16,8] = tmpv; + Rttt_VPR64[24,8] = tmpv; + Rttt_VPR64[32,8] = tmpv; + Rttt_VPR64[40,8] = tmpv; + Rttt_VPR64[48,8] = tmpv; + Rttt_VPR64[56,8] = tmpv; + tmp_ldXn = tmp_ldXn + 1; + tmpv = *:1 tmp_ldXn; + Rttt_VPR64[0,8] = tmpv; + Rttt_VPR64[8,8] = tmpv; + Rttt_VPR64[16,8] = tmpv; + Rttt_VPR64[24,8] = tmpv; + Rttt_VPR64[32,8] = tmpv; + Rttt_VPR64[40,8] = tmpv; + Rttt_VPR64[48,8] = tmpv; + Rttt_VPR64[56,8] = tmpv; + tmp_ldXn = tmp_ldXn + 1; + tmpv = *:1 tmp_ldXn; + Rttt_VPR64[0,8] = tmpv; + Rttt_VPR64[8,8] = tmpv; + Rttt_VPR64[16,8] = tmpv; + Rttt_VPR64[24,8] = tmpv; + Rttt_VPR64[32,8] = tmpv; + Rttt_VPR64[40,8] = tmpv; + Rttt_VPR64[48,8] = tmpv; + Rttt_VPR64[56,8] = tmpv; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0d40e000/mask=xbffff000 +# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0dc0e000/mask=xbfe0f000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x0d40e400/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld3r {Vt.4H, Vt2.4H, Vt3.4H}, [Xn|SP] [, wback] + +:ld3r {vVt^".4H", vVtt^".4H", vVttt^".4H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b111 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:2 = 0; + tmpv = *:2 tmp_ldXn; + Rttt_VPR64[0,16] = tmpv; + Rttt_VPR64[16,16] = tmpv; + Rttt_VPR64[32,16] = tmpv; + Rttt_VPR64[48,16] = tmpv; + tmp_ldXn = tmp_ldXn + 2; + tmpv = *:2 tmp_ldXn; + Rttt_VPR64[0,16] = tmpv; + Rttt_VPR64[16,16] = tmpv; + Rttt_VPR64[32,16] = tmpv; + Rttt_VPR64[48,16] = tmpv; + tmp_ldXn = tmp_ldXn + 2; + tmpv = *:2 tmp_ldXn; + Rttt_VPR64[0,16] = tmpv; + Rttt_VPR64[16,16] = tmpv; + Rttt_VPR64[32,16] = tmpv; + Rttt_VPR64[48,16] = tmpv; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0d40e000/mask=xbffff000 +# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0dc0e000/mask=xbfe0f000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x0d40e800/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld3r {Vt.2S, Vt2.2S, Vt3.2S}, [Xn|SP] [, wback] + +:ld3r {vVt^".2S", vVtt^".2S", vVttt^".2S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b111 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:4 = 0; + tmpv = *:4 tmp_ldXn; + Rttt_VPR64[0,32] = tmpv; + Rttt_VPR64[32,32] = tmpv; + tmp_ldXn = tmp_ldXn + 4; + tmpv = *:4 tmp_ldXn; + Rttt_VPR64[0,32] = tmpv; + Rttt_VPR64[32,32] = tmpv; + tmp_ldXn = tmp_ldXn + 4; + tmpv = *:4 tmp_ldXn; + Rttt_VPR64[0,32] = tmpv; + Rttt_VPR64[32,32] = tmpv; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0d40e000/mask=xbffff000 +# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0dc0e000/mask=xbfe0f000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x0d40ec00/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld3r {Vt.1D, Vt2.1D, Vt3.1D}, [Xn|SP] [, wback] + +:ld3r {vVt^".1D", vVtt^".1D", vVttt^".1D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b111 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:8 = 0; + tmpv = *:8 tmp_ldXn; + Rttt_VPR64[0,64] = tmpv; + tmp_ldXn = tmp_ldXn + 8; + tmpv = *:8 tmp_ldXn; + Rttt_VPR64[0,64] = tmpv; + tmp_ldXn = tmp_ldXn + 8; + tmpv = *:8 tmp_ldXn; + Rttt_VPR64[0,64] = tmpv; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0d40e000/mask=xbffff000 +# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0dc0e000/mask=xbfe0f000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x4d40e000/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld3r {Vt.16B, Vt2.16B, Vt3.16B}, [Xn|SP] [, wback] + +:ld3r {vVt^".16B", vVtt^".16B", vVttt^".16B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b111 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:1 = 0; + tmpv = *:1 tmp_ldXn; + Rttt_VPR128[0,8] = tmpv; + Rttt_VPR128[8,8] = tmpv; + Rttt_VPR128[16,8] = tmpv; + Rttt_VPR128[24,8] = tmpv; + Rttt_VPR128[32,8] = tmpv; + Rttt_VPR128[40,8] = tmpv; + Rttt_VPR128[48,8] = tmpv; + Rttt_VPR128[56,8] = tmpv; + Rttt_VPR128[64,8] = tmpv; + Rttt_VPR128[72,8] = tmpv; + Rttt_VPR128[80,8] = tmpv; + Rttt_VPR128[88,8] = tmpv; + Rttt_VPR128[96,8] = tmpv; + Rttt_VPR128[104,8] = tmpv; + Rttt_VPR128[112,8] = tmpv; + Rttt_VPR128[120,8] = tmpv; + tmp_ldXn = tmp_ldXn + 1; + tmpv = *:1 tmp_ldXn; + Rttt_VPR128[0,8] = tmpv; + Rttt_VPR128[8,8] = tmpv; + Rttt_VPR128[16,8] = tmpv; + Rttt_VPR128[24,8] = tmpv; + Rttt_VPR128[32,8] = tmpv; + Rttt_VPR128[40,8] = tmpv; + Rttt_VPR128[48,8] = tmpv; + Rttt_VPR128[56,8] = tmpv; + Rttt_VPR128[64,8] = tmpv; + Rttt_VPR128[72,8] = tmpv; + Rttt_VPR128[80,8] = tmpv; + Rttt_VPR128[88,8] = tmpv; + Rttt_VPR128[96,8] = tmpv; + Rttt_VPR128[104,8] = tmpv; + Rttt_VPR128[112,8] = tmpv; + Rttt_VPR128[120,8] = tmpv; + tmp_ldXn = tmp_ldXn + 1; + tmpv = *:1 tmp_ldXn; + Rttt_VPR128[0,8] = tmpv; + Rttt_VPR128[8,8] = tmpv; + Rttt_VPR128[16,8] = tmpv; + Rttt_VPR128[24,8] = tmpv; + Rttt_VPR128[32,8] = tmpv; + Rttt_VPR128[40,8] = tmpv; + Rttt_VPR128[48,8] = tmpv; + Rttt_VPR128[56,8] = tmpv; + Rttt_VPR128[64,8] = tmpv; + Rttt_VPR128[72,8] = tmpv; + Rttt_VPR128[80,8] = tmpv; + Rttt_VPR128[88,8] = tmpv; + Rttt_VPR128[96,8] = tmpv; + Rttt_VPR128[104,8] = tmpv; + Rttt_VPR128[112,8] = tmpv; + Rttt_VPR128[120,8] = tmpv; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0d40e000/mask=xbffff000 +# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0dc0e000/mask=xbfe0f000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x4d40e400/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld3r {Vt.8H, Vt2.8H, Vt3.8H}, [Xn|SP] [, wback] + +:ld3r {vVt^".8H", vVtt^".8H", vVttt^".8H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b111 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:2 = 0; + tmpv = *:2 tmp_ldXn; + Rttt_VPR128[0,16] = tmpv; + Rttt_VPR128[16,16] = tmpv; + Rttt_VPR128[32,16] = tmpv; + Rttt_VPR128[48,16] = tmpv; + Rttt_VPR128[64,16] = tmpv; + Rttt_VPR128[80,16] = tmpv; + Rttt_VPR128[96,16] = tmpv; + Rttt_VPR128[112,16] = tmpv; + tmp_ldXn = tmp_ldXn + 2; + tmpv = *:2 tmp_ldXn; + Rttt_VPR128[0,16] = tmpv; + Rttt_VPR128[16,16] = tmpv; + Rttt_VPR128[32,16] = tmpv; + Rttt_VPR128[48,16] = tmpv; + Rttt_VPR128[64,16] = tmpv; + Rttt_VPR128[80,16] = tmpv; + Rttt_VPR128[96,16] = tmpv; + Rttt_VPR128[112,16] = tmpv; + tmp_ldXn = tmp_ldXn + 2; + tmpv = *:2 tmp_ldXn; + Rttt_VPR128[0,16] = tmpv; + Rttt_VPR128[16,16] = tmpv; + Rttt_VPR128[32,16] = tmpv; + Rttt_VPR128[48,16] = tmpv; + Rttt_VPR128[64,16] = tmpv; + Rttt_VPR128[80,16] = tmpv; + Rttt_VPR128[96,16] = tmpv; + Rttt_VPR128[112,16] = tmpv; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0d40e000/mask=xbffff000 +# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0dc0e000/mask=xbfe0f000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x4d40e800/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld3r {Vt.4S, Vt2.4S, Vt3.4S}, [Xn|SP] [, wback] + +:ld3r {vVt^".4S", vVtt^".4S", vVttt^".4S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b111 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:4 = 0; + tmpv = *:4 tmp_ldXn; + Rttt_VPR128[0,32] = tmpv; + Rttt_VPR128[32,32] = tmpv; + Rttt_VPR128[64,32] = tmpv; + Rttt_VPR128[96,32] = tmpv; + tmp_ldXn = tmp_ldXn + 4; + tmpv = *:4 tmp_ldXn; + Rttt_VPR128[0,32] = tmpv; + Rttt_VPR128[32,32] = tmpv; + Rttt_VPR128[64,32] = tmpv; + Rttt_VPR128[96,32] = tmpv; + tmp_ldXn = tmp_ldXn + 4; + tmpv = *:4 tmp_ldXn; + Rttt_VPR128[0,32] = tmpv; + Rttt_VPR128[32,32] = tmpv; + Rttt_VPR128[64,32] = tmpv; + Rttt_VPR128[96,32] = tmpv; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0d40e000/mask=xbffff000 +# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0dc0e000/mask=xbfe0f000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000 +# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000 +# CONSTRUCT x4d40ec00/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld3r {Vt.2D, Vt2.2D, Vt3.2D}, [Xn|SP] [, wback] + +:ld3r {vVt^".2D", vVtt^".2D", vVttt^".2D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b111 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:8 = 0; + tmpv = *:8 tmp_ldXn; + Rttt_VPR128[0,64] = tmpv; + Rttt_VPR128[64,64] = tmpv; + tmp_ldXn = tmp_ldXn + 8; + tmpv = *:8 tmp_ldXn; + Rttt_VPR128[0,64] = tmpv; + Rttt_VPR128[64,64] = tmpv; + tmp_ldXn = tmp_ldXn + 8; + tmpv = *:8 tmp_ldXn; + Rttt_VPR128[0,64] = tmpv; + Rttt_VPR128[64,64] = tmpv; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0c400000/mask=xbffff000 +# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0cc00000/mask=xbfe0f000 +# CONSTRUCT x0c400000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.8B, Vt2.8B, Vt3.8B, Vt4.8B}, [Xn|SP] [, wback] + +:ld4 {vVt^".8B", vVtt^".8B", vVttt^".8B", vVtttt^".8B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0000 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR64[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR64[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR64[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR64[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR64[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR64[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR64[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR64[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR64[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR64[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR64[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0c400000/mask=xbffff000 +# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0cc00000/mask=xbfe0f000 +# CONSTRUCT x0c400400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.4H, Vt2.4H, Vt3.4H, Vt4.4H}, [Xn|SP] [, wback] + +:ld4 {vVt^".4H", vVtt^".4H", vVttt^".4H", vVtttt^".4H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0000 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR64[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR64[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR64[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR64[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR64[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR64[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR64[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR64[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR64[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR64[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR64[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR64[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR64[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR64[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR64[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0c400000/mask=xbffff000 +# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0cc00000/mask=xbfe0f000 +# CONSTRUCT x0c400800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.2S, Vt2.2S, Vt3.2S, Vt4.2S}, [Xn|SP] [, wback] + +:ld4 {vVt^".2S", vVtt^".2S", vVttt^".2S", vVtttt^".2S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0000 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR64[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR64[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR64[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtttt_VPR64[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR64[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR64[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR64[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtttt_VPR64[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0c400000/mask=xbffff000 +# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0cc00000/mask=xbfe0f000 +# CONSTRUCT x4c400000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.16B, Vt2.16B, Vt3.16B, Vt4.16B}, [Xn|SP] [, wback] + +:ld4 {vVt^".16B", vVtt^".16B", vVttt^".16B", vVtttt^".16B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0000 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0c400000/mask=xbffff000 +# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0cc00000/mask=xbfe0f000 +# CONSTRUCT x4c400400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.8H, Vt2.8H, Vt3.8H, Vt4.8H}, [Xn|SP] [, wback] + +:ld4 {vVt^".8H", vVtt^".8H", vVttt^".8H", vVtttt^".8H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0000 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0c400000/mask=xbffff000 +# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0cc00000/mask=xbfe0f000 +# CONSTRUCT x4c400800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.4S, Vt2.4S, Vt3.4S, Vt4.4S}, [Xn|SP] [, wback] + +:ld4 {vVt^".4S", vVtt^".4S", vVttt^".4S", vVtttt^".4S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0000 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtttt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtttt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtttt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtttt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0c400000/mask=xbffff000 +# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0cc00000/mask=xbfe0f000 +# CONSTRUCT x4c400c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.2D, Vt2.2D, Vt3.2D, Vt4.2D}, [Xn|SP] [, wback] + +:ld4 {vVt^".2D", vVtt^".2D", vVttt^".2D", vVtttt^".2D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0000 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rttt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtttt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rttt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtttt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x0d602000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[0], [Xn|SP] [, wback] + +:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[0,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x0d602400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[1], [Xn|SP] [, wback] + +:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[8,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x0d602800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[2], [Xn|SP] [, wback] + +:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[2], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[16,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x0d602c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[3], [Xn|SP] [, wback] + +:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[3], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[24,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x0d603000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[4], [Xn|SP] [, wback] + +:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[4], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[32,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x0d603400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[5], [Xn|SP] [, wback] + +:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[5], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[40,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x0d603800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[6], [Xn|SP] [, wback] + +:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[6], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[48,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x0d603c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[7], [Xn|SP] [, wback] + +:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[7], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[56,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x4d602000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[8], [Xn|SP] [, wback] + +:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[8], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[64,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x4d602400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[9], [Xn|SP] [, wback] + +:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[9], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[72,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x4d602800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[10], [Xn|SP] [, wback] + +:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[10], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[80,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x4d602c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[11], [Xn|SP] [, wback] + +:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[11], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[88,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x4d603000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[12], [Xn|SP] [, wback] + +:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[12], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[96,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x4d603400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[13], [Xn|SP] [, wback] + +:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[13], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[104,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x4d603800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[14], [Xn|SP] [, wback] + +:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[14], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[112,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x4d603c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[15], [Xn|SP] [, wback] + +:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[15], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rttt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + Rtttt_VPR128[120,8] = *:1 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x0d606000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[0], [Xn|SP] [, wback] + +:ld4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b011 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR128[0,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x0d606800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[1], [Xn|SP] [, wback] + +:ld4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b011 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR128[16,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x0d607000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[2], [Xn|SP] [, wback] + +:ld4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[2], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b011 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR128[32,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x0d607800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[3], [Xn|SP] [, wback] + +:ld4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[3], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b011 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR128[48,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x4d606000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[4], [Xn|SP] [, wback] + +:ld4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[4], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b011 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR128[64,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x4d606800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[5], [Xn|SP] [, wback] + +:ld4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[5], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b011 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR128[80,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x4d607000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[6], [Xn|SP] [, wback] + +:ld4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[6], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b011 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR128[96,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x4d607800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[7], [Xn|SP] [, wback] + +:ld4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[7], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b011 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rttt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + Rtttt_VPR128[112,16] = *:2 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x0d60a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.S, Vt2.S, Vt3.S, Vt4.S}[0], [Xn|SP] [, wback] + +:ld4 {vVt^".S", vVtt^".S", vVttt^".S", vVtttt^".S"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b101 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtttt_VPR128[0,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x0d60b000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.S, Vt2.S, Vt3.S, Vt4.S}[1], [Xn|SP] [, wback] + +:ld4 {vVt^".S", vVtt^".S", vVttt^".S", vVtttt^".S"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b101 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtttt_VPR128[32,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x4d60a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.S, Vt2.S, Vt3.S, Vt4.S}[2], [Xn|SP] [, wback] + +:ld4 {vVt^".S", vVtt^".S", vVttt^".S", vVtttt^".S"}[2], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b101 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtttt_VPR128[64,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x4d60b000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.S, Vt2.S, Vt3.S, Vt4.S}[3], [Xn|SP] [, wback] + +:ld4 {vVt^".S", vVtt^".S", vVttt^".S", vVtttt^".S"}[3], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b101 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rttt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + Rtttt_VPR128[96,32] = *:4 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x0d60a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.D, Vt2.D, Vt3.D, Vt4.D}[0], [Xn|SP] [, wback] + +:ld4 {vVt^".D", vVtt^".D", vVttt^".D", vVtttt^".D"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b101 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rttt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtttt_VPR128[0,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x4d60a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# ld4 {Vt.D, Vt2.D, Vt3.D, Vt4.D}[1], [Xn|SP] [, wback] + +:ld4 {vVt^".D", vVtt^".D", vVttt^".D", vVtttt^".D"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b101 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + Rt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rttt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + Rtttt_VPR128[64,64] = *:8 tmp_ldXn; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0d60e000/mask=xbffff000 +# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0de0e000/mask=xbfe0f000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x0d60e000/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld4r {Vt.8B, Vt2.8B, Vt3.8B, Vt4.8B}, [Xn|SP] [, wback] + +:ld4r {vVt^".8B", vVtt^".8B", vVttt^".8B", vVtttt^".8B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b111 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:1 = 0; + tmpv = *:1 tmp_ldXn; + Rtttt_VPR64[0,8] = tmpv; + Rtttt_VPR64[8,8] = tmpv; + Rtttt_VPR64[16,8] = tmpv; + Rtttt_VPR64[24,8] = tmpv; + Rtttt_VPR64[32,8] = tmpv; + Rtttt_VPR64[40,8] = tmpv; + Rtttt_VPR64[48,8] = tmpv; + Rtttt_VPR64[56,8] = tmpv; + tmp_ldXn = tmp_ldXn + 1; + tmpv = *:1 tmp_ldXn; + Rtttt_VPR64[0,8] = tmpv; + Rtttt_VPR64[8,8] = tmpv; + Rtttt_VPR64[16,8] = tmpv; + Rtttt_VPR64[24,8] = tmpv; + Rtttt_VPR64[32,8] = tmpv; + Rtttt_VPR64[40,8] = tmpv; + Rtttt_VPR64[48,8] = tmpv; + Rtttt_VPR64[56,8] = tmpv; + tmp_ldXn = tmp_ldXn + 1; + tmpv = *:1 tmp_ldXn; + Rtttt_VPR64[0,8] = tmpv; + Rtttt_VPR64[8,8] = tmpv; + Rtttt_VPR64[16,8] = tmpv; + Rtttt_VPR64[24,8] = tmpv; + Rtttt_VPR64[32,8] = tmpv; + Rtttt_VPR64[40,8] = tmpv; + Rtttt_VPR64[48,8] = tmpv; + Rtttt_VPR64[56,8] = tmpv; + tmp_ldXn = tmp_ldXn + 1; + tmpv = *:1 tmp_ldXn; + Rtttt_VPR64[0,8] = tmpv; + Rtttt_VPR64[8,8] = tmpv; + Rtttt_VPR64[16,8] = tmpv; + Rtttt_VPR64[24,8] = tmpv; + Rtttt_VPR64[32,8] = tmpv; + Rtttt_VPR64[40,8] = tmpv; + Rtttt_VPR64[48,8] = tmpv; + Rtttt_VPR64[56,8] = tmpv; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0d60e000/mask=xbffff000 +# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0de0e000/mask=xbfe0f000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x0d60e400/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld4r {Vt.4H, Vt2.4H, Vt3.4H, Vt4.4H}, [Xn|SP] [, wback] + +:ld4r {vVt^".4H", vVtt^".4H", vVttt^".4H", vVtttt^".4H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b111 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:2 = 0; + tmpv = *:2 tmp_ldXn; + Rtttt_VPR64[0,16] = tmpv; + Rtttt_VPR64[16,16] = tmpv; + Rtttt_VPR64[32,16] = tmpv; + Rtttt_VPR64[48,16] = tmpv; + tmp_ldXn = tmp_ldXn + 2; + tmpv = *:2 tmp_ldXn; + Rtttt_VPR64[0,16] = tmpv; + Rtttt_VPR64[16,16] = tmpv; + Rtttt_VPR64[32,16] = tmpv; + Rtttt_VPR64[48,16] = tmpv; + tmp_ldXn = tmp_ldXn + 2; + tmpv = *:2 tmp_ldXn; + Rtttt_VPR64[0,16] = tmpv; + Rtttt_VPR64[16,16] = tmpv; + Rtttt_VPR64[32,16] = tmpv; + Rtttt_VPR64[48,16] = tmpv; + tmp_ldXn = tmp_ldXn + 2; + tmpv = *:2 tmp_ldXn; + Rtttt_VPR64[0,16] = tmpv; + Rtttt_VPR64[16,16] = tmpv; + Rtttt_VPR64[32,16] = tmpv; + Rtttt_VPR64[48,16] = tmpv; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0d60e000/mask=xbffff000 +# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0de0e000/mask=xbfe0f000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x0d60e800/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld4r {Vt.2S, Vt2.2S, Vt3.2S, Vt4.2S}, [Xn|SP] [, wback] + +:ld4r {vVt^".2S", vVtt^".2S", vVttt^".2S", vVtttt^".2S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b111 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:4 = 0; + tmpv = *:4 tmp_ldXn; + Rtttt_VPR64[0,32] = tmpv; + Rtttt_VPR64[32,32] = tmpv; + tmp_ldXn = tmp_ldXn + 4; + tmpv = *:4 tmp_ldXn; + Rtttt_VPR64[0,32] = tmpv; + Rtttt_VPR64[32,32] = tmpv; + tmp_ldXn = tmp_ldXn + 4; + tmpv = *:4 tmp_ldXn; + Rtttt_VPR64[0,32] = tmpv; + Rtttt_VPR64[32,32] = tmpv; + tmp_ldXn = tmp_ldXn + 4; + tmpv = *:4 tmp_ldXn; + Rtttt_VPR64[0,32] = tmpv; + Rtttt_VPR64[32,32] = tmpv; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0d60e000/mask=xbffff000 +# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0de0e000/mask=xbfe0f000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x0d60ec00/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld4r {Vt.1D, Vt2.1D, Vt3.1D, Vt4.1D}, [Xn|SP] [, wback] + +:ld4r {vVt^".1D", vVtt^".1D", vVttt^".1D", vVtttt^".1D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b111 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:8 = 0; + tmpv = *:8 tmp_ldXn; + Rtttt_VPR64[0,64] = tmpv; + tmp_ldXn = tmp_ldXn + 8; + tmpv = *:8 tmp_ldXn; + Rtttt_VPR64[0,64] = tmpv; + tmp_ldXn = tmp_ldXn + 8; + tmpv = *:8 tmp_ldXn; + Rtttt_VPR64[0,64] = tmpv; + tmp_ldXn = tmp_ldXn + 8; + tmpv = *:8 tmp_ldXn; + Rtttt_VPR64[0,64] = tmpv; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0d60e000/mask=xbffff000 +# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0de0e000/mask=xbfe0f000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x4d60e000/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld4r {Vt.16B, Vt2.16B, Vt3.16B, Vt4.16B}, [Xn|SP] [, wback] + +:ld4r {vVt^".16B", vVtt^".16B", vVttt^".16B", vVtttt^".16B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b111 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:1 = 0; + tmpv = *:1 tmp_ldXn; + Rtttt_VPR128[0,8] = tmpv; + Rtttt_VPR128[8,8] = tmpv; + Rtttt_VPR128[16,8] = tmpv; + Rtttt_VPR128[24,8] = tmpv; + Rtttt_VPR128[32,8] = tmpv; + Rtttt_VPR128[40,8] = tmpv; + Rtttt_VPR128[48,8] = tmpv; + Rtttt_VPR128[56,8] = tmpv; + Rtttt_VPR128[64,8] = tmpv; + Rtttt_VPR128[72,8] = tmpv; + Rtttt_VPR128[80,8] = tmpv; + Rtttt_VPR128[88,8] = tmpv; + Rtttt_VPR128[96,8] = tmpv; + Rtttt_VPR128[104,8] = tmpv; + Rtttt_VPR128[112,8] = tmpv; + Rtttt_VPR128[120,8] = tmpv; + tmp_ldXn = tmp_ldXn + 1; + tmpv = *:1 tmp_ldXn; + Rtttt_VPR128[0,8] = tmpv; + Rtttt_VPR128[8,8] = tmpv; + Rtttt_VPR128[16,8] = tmpv; + Rtttt_VPR128[24,8] = tmpv; + Rtttt_VPR128[32,8] = tmpv; + Rtttt_VPR128[40,8] = tmpv; + Rtttt_VPR128[48,8] = tmpv; + Rtttt_VPR128[56,8] = tmpv; + Rtttt_VPR128[64,8] = tmpv; + Rtttt_VPR128[72,8] = tmpv; + Rtttt_VPR128[80,8] = tmpv; + Rtttt_VPR128[88,8] = tmpv; + Rtttt_VPR128[96,8] = tmpv; + Rtttt_VPR128[104,8] = tmpv; + Rtttt_VPR128[112,8] = tmpv; + Rtttt_VPR128[120,8] = tmpv; + tmp_ldXn = tmp_ldXn + 1; + tmpv = *:1 tmp_ldXn; + Rtttt_VPR128[0,8] = tmpv; + Rtttt_VPR128[8,8] = tmpv; + Rtttt_VPR128[16,8] = tmpv; + Rtttt_VPR128[24,8] = tmpv; + Rtttt_VPR128[32,8] = tmpv; + Rtttt_VPR128[40,8] = tmpv; + Rtttt_VPR128[48,8] = tmpv; + Rtttt_VPR128[56,8] = tmpv; + Rtttt_VPR128[64,8] = tmpv; + Rtttt_VPR128[72,8] = tmpv; + Rtttt_VPR128[80,8] = tmpv; + Rtttt_VPR128[88,8] = tmpv; + Rtttt_VPR128[96,8] = tmpv; + Rtttt_VPR128[104,8] = tmpv; + Rtttt_VPR128[112,8] = tmpv; + Rtttt_VPR128[120,8] = tmpv; + tmp_ldXn = tmp_ldXn + 1; + tmpv = *:1 tmp_ldXn; + Rtttt_VPR128[0,8] = tmpv; + Rtttt_VPR128[8,8] = tmpv; + Rtttt_VPR128[16,8] = tmpv; + Rtttt_VPR128[24,8] = tmpv; + Rtttt_VPR128[32,8] = tmpv; + Rtttt_VPR128[40,8] = tmpv; + Rtttt_VPR128[48,8] = tmpv; + Rtttt_VPR128[56,8] = tmpv; + Rtttt_VPR128[64,8] = tmpv; + Rtttt_VPR128[72,8] = tmpv; + Rtttt_VPR128[80,8] = tmpv; + Rtttt_VPR128[88,8] = tmpv; + Rtttt_VPR128[96,8] = tmpv; + Rtttt_VPR128[104,8] = tmpv; + Rtttt_VPR128[112,8] = tmpv; + Rtttt_VPR128[120,8] = tmpv; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0d60e000/mask=xbffff000 +# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0de0e000/mask=xbfe0f000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x4d60e400/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld4r {Vt.8H, Vt2.8H, Vt3.8H, Vt4.8H}, [Xn|SP] [, wback] + +:ld4r {vVt^".8H", vVtt^".8H", vVttt^".8H", vVtttt^".8H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b111 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:2 = 0; + tmpv = *:2 tmp_ldXn; + Rtttt_VPR128[0,16] = tmpv; + Rtttt_VPR128[16,16] = tmpv; + Rtttt_VPR128[32,16] = tmpv; + Rtttt_VPR128[48,16] = tmpv; + Rtttt_VPR128[64,16] = tmpv; + Rtttt_VPR128[80,16] = tmpv; + Rtttt_VPR128[96,16] = tmpv; + Rtttt_VPR128[112,16] = tmpv; + tmp_ldXn = tmp_ldXn + 2; + tmpv = *:2 tmp_ldXn; + Rtttt_VPR128[0,16] = tmpv; + Rtttt_VPR128[16,16] = tmpv; + Rtttt_VPR128[32,16] = tmpv; + Rtttt_VPR128[48,16] = tmpv; + Rtttt_VPR128[64,16] = tmpv; + Rtttt_VPR128[80,16] = tmpv; + Rtttt_VPR128[96,16] = tmpv; + Rtttt_VPR128[112,16] = tmpv; + tmp_ldXn = tmp_ldXn + 2; + tmpv = *:2 tmp_ldXn; + Rtttt_VPR128[0,16] = tmpv; + Rtttt_VPR128[16,16] = tmpv; + Rtttt_VPR128[32,16] = tmpv; + Rtttt_VPR128[48,16] = tmpv; + Rtttt_VPR128[64,16] = tmpv; + Rtttt_VPR128[80,16] = tmpv; + Rtttt_VPR128[96,16] = tmpv; + Rtttt_VPR128[112,16] = tmpv; + tmp_ldXn = tmp_ldXn + 2; + tmpv = *:2 tmp_ldXn; + Rtttt_VPR128[0,16] = tmpv; + Rtttt_VPR128[16,16] = tmpv; + Rtttt_VPR128[32,16] = tmpv; + Rtttt_VPR128[48,16] = tmpv; + Rtttt_VPR128[64,16] = tmpv; + Rtttt_VPR128[80,16] = tmpv; + Rtttt_VPR128[96,16] = tmpv; + Rtttt_VPR128[112,16] = tmpv; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0d60e000/mask=xbffff000 +# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0de0e000/mask=xbfe0f000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x4d60e800/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld4r {Vt.4S, Vt2.4S, Vt3.4S, Vt4.4S}, [Xn|SP] [, wback] + +:ld4r {vVt^".4S", vVtt^".4S", vVttt^".4S", vVtttt^".4S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b111 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:4 = 0; + tmpv = *:4 tmp_ldXn; + Rtttt_VPR128[0,32] = tmpv; + Rtttt_VPR128[32,32] = tmpv; + Rtttt_VPR128[64,32] = tmpv; + Rtttt_VPR128[96,32] = tmpv; + tmp_ldXn = tmp_ldXn + 4; + tmpv = *:4 tmp_ldXn; + Rtttt_VPR128[0,32] = tmpv; + Rtttt_VPR128[32,32] = tmpv; + Rtttt_VPR128[64,32] = tmpv; + Rtttt_VPR128[96,32] = tmpv; + tmp_ldXn = tmp_ldXn + 4; + tmpv = *:4 tmp_ldXn; + Rtttt_VPR128[0,32] = tmpv; + Rtttt_VPR128[32,32] = tmpv; + Rtttt_VPR128[64,32] = tmpv; + Rtttt_VPR128[96,32] = tmpv; + tmp_ldXn = tmp_ldXn + 4; + tmpv = *:4 tmp_ldXn; + Rtttt_VPR128[0,32] = tmpv; + Rtttt_VPR128[32,32] = tmpv; + Rtttt_VPR128[64,32] = tmpv; + Rtttt_VPR128[96,32] = tmpv; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0d60e000/mask=xbffff000 +# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0de0e000/mask=xbfe0f000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000 +# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000 +# CONSTRUCT x4d60ec00/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES +# ld4r {Vt.2D, Vt2.2D, Vt3.2D, Vt4.2D}, [Xn|SP] [, wback] + +:ld4r {vVt^".2D", vVtt^".2D", vVttt^".2D", vVtttt^".2D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b111 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + local tmpv:8 = 0; + tmpv = *:8 tmp_ldXn; + Rtttt_VPR128[0,64] = tmpv; + Rtttt_VPR128[64,64] = tmpv; + tmp_ldXn = tmp_ldXn + 8; + tmpv = *:8 tmp_ldXn; + Rtttt_VPR128[0,64] = tmpv; + Rtttt_VPR128[64,64] = tmpv; + tmp_ldXn = tmp_ldXn + 8; + tmpv = *:8 tmp_ldXn; + Rtttt_VPR128[0,64] = tmpv; + Rtttt_VPR128[64,64] = tmpv; + tmp_ldXn = tmp_ldXn + 8; + tmpv = *:8 tmp_ldXn; + Rtttt_VPR128[0,64] = tmpv; + Rtttt_VPR128[64,64] = tmpv; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x0c002000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.8B, Vt2.8B, Vt3.8B, Vt4.8B}, [Xn|SP] [, wback] + +:st1 {vVt^".8B", vVtt^".8B", vVttt^".8B", vVtttt^".8B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0010 & b_1011=0b00 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & vVtttt & Rtttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR64[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR64[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR64[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR64[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR64[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR64[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR64[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR64[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR64[56,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x0c002400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.4H, Vt2.4H, Vt3.4H, Vt4.4H}, [Xn|SP] [, wback] + +:st1 {vVt^".4H", vVtt^".4H", vVttt^".4H", vVtttt^".4H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0010 & b_1011=0b01 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & vVtttt & Rtttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR64[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR64[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR64[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR64[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR64[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR64[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR64[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR64[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR64[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR64[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR64[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR64[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR64[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR64[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR64[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR64[48,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x0c002800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.2S, Vt2.2S, Vt3.2S, Vt4.2S}, [Xn|SP] [, wback] + +:st1 {vVt^".2S", vVtt^".2S", vVttt^".2S", vVtttt^".2S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0010 & b_1011=0b10 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & vVtttt & Rtttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR64[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR64[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR64[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR64[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR64[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR64[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtttt_VPR64[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtttt_VPR64[32,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x0c002c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.1D, Vt2.1D, Vt3.1D, Vt4.1D}, [Xn|SP] [, wback] + +:st1 {vVt^".1D", vVtt^".1D", vVttt^".1D", vVtttt^".1D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0010 & b_1011=0b11 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & vVtttt & Rtttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:8 tmp_ldXn = Rt_VPR64[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtt_VPR64[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rttt_VPR64[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtttt_VPR64[0,64]; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x4c002000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.16B, Vt2.16B, Vt3.16B, Vt4.16B}, [Xn|SP] [, wback] + +:st1 {vVt^".16B", vVtt^".16B", vVttt^".16B", vVtttt^".16B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0010 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x4c002400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.8H, Vt2.8H, Vt3.8H, Vt4.8H}, [Xn|SP] [, wback] + +:st1 {vVt^".8H", vVtt^".8H", vVttt^".8H", vVtttt^".8H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0010 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x4c002800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.4S, Vt2.4S, Vt3.4S, Vt4.4S}, [Xn|SP] [, wback] + +:st1 {vVt^".4S", vVtt^".4S", vVttt^".4S", vVtttt^".4S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0010 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtttt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtttt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtttt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtttt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x4c002c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.2D, Vt2.2D, Vt3.2D, Vt4.2D}, [Xn|SP] [, wback] + +:st1 {vVt^".2D", vVtt^".2D", vVttt^".2D", vVtttt^".2D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0010 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:8 tmp_ldXn = Rt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rttt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rttt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtttt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtttt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x0c006000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.8B, Vt2.8B, Vt3.8B}, [Xn|SP] [, wback] + +:st1 {vVt^".8B", vVtt^".8B", vVttt^".8B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0110 & b_1011=0b00 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR64[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[56,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x0c006400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.4H, Vt2.4H, Vt3.4H}, [Xn|SP] [, wback] + +:st1 {vVt^".4H", vVtt^".4H", vVttt^".4H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0110 & b_1011=0b01 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR64[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR64[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR64[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR64[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR64[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR64[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR64[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR64[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR64[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR64[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR64[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR64[48,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x0c006800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.2S, Vt2.2S, Vt3.2S}, [Xn|SP] [, wback] + +:st1 {vVt^".2S", vVtt^".2S", vVttt^".2S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0110 & b_1011=0b10 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR64[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR64[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR64[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR64[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR64[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR64[32,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x0c006c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.1D, Vt2.1D, Vt3.1D}, [Xn|SP] [, wback] + +:st1 {vVt^".1D", vVtt^".1D", vVttt^".1D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0110 & b_1011=0b11 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:8 tmp_ldXn = Rt_VPR64[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtt_VPR64[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rttt_VPR64[0,64]; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x4c006000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.16B, Vt2.16B, Vt3.16B}, [Xn|SP] [, wback] + +:st1 {vVt^".16B", vVtt^".16B", vVttt^".16B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0110 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x4c006400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.8H, Vt2.8H, Vt3.8H}, [Xn|SP] [, wback] + +:st1 {vVt^".8H", vVtt^".8H", vVttt^".8H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0110 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x4c006800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.4S, Vt2.4S, Vt3.4S}, [Xn|SP] [, wback] + +:st1 {vVt^".4S", vVtt^".4S", vVttt^".4S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0110 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x4c006c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.2D, Vt2.2D, Vt3.2D}, [Xn|SP] [, wback] + +:st1 {vVt^".2D", vVtt^".2D", vVttt^".2D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0110 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:8 tmp_ldXn = Rt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rttt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rttt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x0c007000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.8B}, [Xn|SP] [, wback] + +:st1 {vVt^".8B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0111 & b_1011=0b00 & vVt & Rt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR64[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[56,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x0c007400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.4H}, [Xn|SP] [, wback] + +:st1 {vVt^".4H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0111 & b_1011=0b01 & vVt & Rt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR64[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR64[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR64[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR64[48,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x0c007800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.2S}, [Xn|SP] [, wback] + +:st1 {vVt^".2S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0111 & b_1011=0b10 & vVt & Rt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR64[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR64[32,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x0c007c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.1D}, [Xn|SP] [, wback] + +:st1 {vVt^".1D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0111 & b_1011=0b11 & vVt & Rt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:8 tmp_ldXn = Rt_VPR64[0,64]; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x4c007000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.16B}, [Xn|SP] [, wback] + +:st1 {vVt^".16B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0111 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x4c007400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.8H}, [Xn|SP] [, wback] + +:st1 {vVt^".8H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0111 & b_1011=0b01 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x4c007800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.4S}, [Xn|SP] [, wback] + +:st1 {vVt^".4S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0111 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x4c007c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.2D}, [Xn|SP] [, wback] + +:st1 {vVt^".2D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0111 & b_1011=0b11 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:8 tmp_ldXn = Rt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x0c00a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.8B, Vt2.8B}, [Xn|SP] [, wback] + +:st1 {vVt^".8B", vVtt^".8B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1010 & b_1011=0b00 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR64[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[56,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x0c00a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.4H, Vt2.4H}, [Xn|SP] [, wback] + +:st1 {vVt^".4H", vVtt^".4H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1010 & b_1011=0b01 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR64[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR64[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR64[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR64[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR64[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR64[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR64[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR64[48,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x0c00a800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.2S, Vt2.2S}, [Xn|SP] [, wback] + +:st1 {vVt^".2S", vVtt^".2S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1010 & b_1011=0b10 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR64[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR64[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR64[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR64[32,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x0c00ac00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.1D, Vt2.1D}, [Xn|SP] [, wback] + +:st1 {vVt^".1D", vVtt^".1D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1010 & b_1011=0b11 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:8 tmp_ldXn = Rt_VPR64[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtt_VPR64[0,64]; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x4c00a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.16B, Vt2.16B}, [Xn|SP] [, wback] + +:st1 {vVt^".16B", vVtt^".16B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1010 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x4c00a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.8H, Vt2.8H}, [Xn|SP] [, wback] + +:st1 {vVt^".8H", vVtt^".8H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1010 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x4c00a800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.4S, Vt2.4S}, [Xn|SP] [, wback] + +:st1 {vVt^".4S", vVtt^".4S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1010 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000 +# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000 +# CONSTRUCT x4c00ac00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.2D, Vt2.2D}, [Xn|SP] [, wback] + +:st1 {vVt^".2D", vVtt^".2D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1010 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:8 tmp_ldXn = Rt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x0d000000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.B}[0], [Xn|SP] [, wback] + +:st1 {vVt^".B"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x0d000400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.B}[1], [Xn|SP] [, wback] + +:st1 {vVt^".B"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x0d000800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.B}[2], [Xn|SP] [, wback] + +:st1 {vVt^".B"}[2], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x0d000c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.B}[3], [Xn|SP] [, wback] + +:st1 {vVt^".B"}[3], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x0d001000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.B}[4], [Xn|SP] [, wback] + +:st1 {vVt^".B"}[4], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x0d001400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.B}[5], [Xn|SP] [, wback] + +:st1 {vVt^".B"}[5], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x0d001800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.B}[6], [Xn|SP] [, wback] + +:st1 {vVt^".B"}[6], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x0d001c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.B}[7], [Xn|SP] [, wback] + +:st1 {vVt^".B"}[7], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x4d000000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.B}[8], [Xn|SP] [, wback] + +:st1 {vVt^".B"}[8], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x4d000400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.B}[9], [Xn|SP] [, wback] + +:st1 {vVt^".B"}[9], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x4d000800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.B}[10], [Xn|SP] [, wback] + +:st1 {vVt^".B"}[10], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x4d000c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.B}[11], [Xn|SP] [, wback] + +:st1 {vVt^".B"}[11], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x4d001000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.B}[12], [Xn|SP] [, wback] + +:st1 {vVt^".B"}[12], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x4d001400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.B}[13], [Xn|SP] [, wback] + +:st1 {vVt^".B"}[13], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x4d001800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.B}[14], [Xn|SP] [, wback] + +:st1 {vVt^".B"}[14], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x4d001c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.B}[15], [Xn|SP] [, wback] + +:st1 {vVt^".B"}[15], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x0d004000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.H}[0], [Xn|SP] [, wback] + +:st1 {vVt^".H"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b010 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x0d004800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.H}[1], [Xn|SP] [, wback] + +:st1 {vVt^".H"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b010 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x0d005000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.H}[2], [Xn|SP] [, wback] + +:st1 {vVt^".H"}[2], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b010 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x0d005800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.H}[3], [Xn|SP] [, wback] + +:st1 {vVt^".H"}[3], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b010 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x4d004000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.H}[4], [Xn|SP] [, wback] + +:st1 {vVt^".H"}[4], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b010 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x4d004800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.H}[5], [Xn|SP] [, wback] + +:st1 {vVt^".H"}[5], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b010 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x4d005000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.H}[6], [Xn|SP] [, wback] + +:st1 {vVt^".H"}[6], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b010 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x4d005800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.H}[7], [Xn|SP] [, wback] + +:st1 {vVt^".H"}[7], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b010 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x0d008000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.S}[0], [Xn|SP] [, wback] + +:st1 {vVt^".S"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b100 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x0d009000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.S}[1], [Xn|SP] [, wback] + +:st1 {vVt^".S"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b100 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x4d008000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.S}[2], [Xn|SP] [, wback] + +:st1 {vVt^".S"}[2], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b100 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x4d009000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.S}[3], [Xn|SP] [, wback] + +:st1 {vVt^".S"}[3], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b100 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x0d008400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.D}[0], [Xn|SP] [, wback] + +:st1 {vVt^".D"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b100 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:8 tmp_ldXn = Rt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000 +# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000 +# CONSTRUCT x4d008400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st1 {Vt.D}[1], [Xn|SP] [, wback] + +:st1 {vVt^".D"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b100 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:8 tmp_ldXn = Rt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c008000/mask=xbffff000 +# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c808000/mask=xbfe0f000 +# CONSTRUCT x0c008000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.8B, Vt2.8B}, [Xn|SP] [, wback] + +:st2 {vVt^".8B", vVtt^".8B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1000 & b_1011=0b00 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR64[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[56,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c008000/mask=xbffff000 +# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c808000/mask=xbfe0f000 +# CONSTRUCT x0c008400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.4H, Vt2.4H}, [Xn|SP] [, wback] + +:st2 {vVt^".4H", vVtt^".4H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1000 & b_1011=0b01 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR64[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR64[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR64[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR64[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR64[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR64[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR64[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR64[48,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c008000/mask=xbffff000 +# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c808000/mask=xbfe0f000 +# CONSTRUCT x0c008800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.2S, Vt2.2S}, [Xn|SP] [, wback] + +:st2 {vVt^".2S", vVtt^".2S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1000 & b_1011=0b10 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR64[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR64[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR64[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR64[32,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c008000/mask=xbffff000 +# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c808000/mask=xbfe0f000 +# CONSTRUCT x4c008000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.16B, Vt2.16B}, [Xn|SP] [, wback] + +:st2 {vVt^".16B", vVtt^".16B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1000 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c008000/mask=xbffff000 +# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c808000/mask=xbfe0f000 +# CONSTRUCT x4c008400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.8H, Vt2.8H}, [Xn|SP] [, wback] + +:st2 {vVt^".8H", vVtt^".8H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1000 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c008000/mask=xbffff000 +# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c808000/mask=xbfe0f000 +# CONSTRUCT x4c008800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.4S, Vt2.4S}, [Xn|SP] [, wback] + +:st2 {vVt^".4S", vVtt^".4S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1000 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c008000/mask=xbffff000 +# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c808000/mask=xbfe0f000 +# CONSTRUCT x4c008c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.2D, Vt2.2D}, [Xn|SP] [, wback] + +:st2 {vVt^".2D", vVtt^".2D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1000 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:8 tmp_ldXn = Rt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x0d200000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.B, Vt2.B}[0], [Xn|SP] [, wback] + +:st2 {vVt^".B", vVtt^".B"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x0d200400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.B, Vt2.B}[1], [Xn|SP] [, wback] + +:st2 {vVt^".B", vVtt^".B"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x0d200800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.B, Vt2.B}[2], [Xn|SP] [, wback] + +:st2 {vVt^".B", vVtt^".B"}[2], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x0d200c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.B, Vt2.B}[3], [Xn|SP] [, wback] + +:st2 {vVt^".B", vVtt^".B"}[3], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x0d201000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.B, Vt2.B}[4], [Xn|SP] [, wback] + +:st2 {vVt^".B", vVtt^".B"}[4], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x0d201400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.B, Vt2.B}[5], [Xn|SP] [, wback] + +:st2 {vVt^".B", vVtt^".B"}[5], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x0d201800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.B, Vt2.B}[6], [Xn|SP] [, wback] + +:st2 {vVt^".B", vVtt^".B"}[6], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x0d201c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.B, Vt2.B}[7], [Xn|SP] [, wback] + +:st2 {vVt^".B", vVtt^".B"}[7], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x4d200000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.B, Vt2.B}[8], [Xn|SP] [, wback] + +:st2 {vVt^".B", vVtt^".B"}[8], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x4d200400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.B, Vt2.B}[9], [Xn|SP] [, wback] + +:st2 {vVt^".B", vVtt^".B"}[9], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x4d200800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.B, Vt2.B}[10], [Xn|SP] [, wback] + +:st2 {vVt^".B", vVtt^".B"}[10], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x4d200c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.B, Vt2.B}[11], [Xn|SP] [, wback] + +:st2 {vVt^".B", vVtt^".B"}[11], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x4d201000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.B, Vt2.B}[12], [Xn|SP] [, wback] + +:st2 {vVt^".B", vVtt^".B"}[12], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x4d201400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.B, Vt2.B}[13], [Xn|SP] [, wback] + +:st2 {vVt^".B", vVtt^".B"}[13], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x4d201800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.B, Vt2.B}[14], [Xn|SP] [, wback] + +:st2 {vVt^".B", vVtt^".B"}[14], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x4d201c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.B, Vt2.B}[15], [Xn|SP] [, wback] + +:st2 {vVt^".B", vVtt^".B"}[15], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x0d204000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.H, Vt2.H}[0], [Xn|SP] [, wback] + +:st2 {vVt^".H", vVtt^".H"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b010 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x0d204800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.H, Vt2.H}[1], [Xn|SP] [, wback] + +:st2 {vVt^".H", vVtt^".H"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b010 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x0d205000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.H, Vt2.H}[2], [Xn|SP] [, wback] + +:st2 {vVt^".H", vVtt^".H"}[2], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b010 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x0d205800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.H, Vt2.H}[3], [Xn|SP] [, wback] + +:st2 {vVt^".H", vVtt^".H"}[3], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b010 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x4d204000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.H, Vt2.H}[4], [Xn|SP] [, wback] + +:st2 {vVt^".H", vVtt^".H"}[4], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b010 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x4d204800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.H, Vt2.H}[5], [Xn|SP] [, wback] + +:st2 {vVt^".H", vVtt^".H"}[5], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b010 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x4d205000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.H, Vt2.H}[6], [Xn|SP] [, wback] + +:st2 {vVt^".H", vVtt^".H"}[6], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b010 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x4d205800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.H, Vt2.H}[7], [Xn|SP] [, wback] + +:st2 {vVt^".H", vVtt^".H"}[7], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b010 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x0d208000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.S, Vt2.S}[0], [Xn|SP] [, wback] + +:st2 {vVt^".S", vVtt^".S"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b100 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x0d209000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.S, Vt2.S}[1], [Xn|SP] [, wback] + +:st2 {vVt^".S", vVtt^".S"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b100 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x4d208000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.S, Vt2.S}[2], [Xn|SP] [, wback] + +:st2 {vVt^".S", vVtt^".S"}[2], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b100 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x4d209000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.S, Vt2.S}[3], [Xn|SP] [, wback] + +:st2 {vVt^".S", vVtt^".S"}[3], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b100 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x0d208400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.D, Vt2.D}[0], [Xn|SP] [, wback] + +:st2 {vVt^".D", vVtt^".D"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b100 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:8 tmp_ldXn = Rt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000 +# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000 +# CONSTRUCT x4d208400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st2 {Vt.D, Vt2.D}[1], [Xn|SP] [, wback] + +:st2 {vVt^".D", vVtt^".D"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b100 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:8 tmp_ldXn = Rt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c004000/mask=xbffff000 +# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c804000/mask=xbfe0f000 +# CONSTRUCT x0c004000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.8B, Vt2.8B, Vt3.8B}, [Xn|SP] [, wback] + +:st3 {vVt^".8B", vVtt^".8B", vVttt^".8B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0100 & b_1011=0b00 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR64[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[56,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c004000/mask=xbffff000 +# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c804000/mask=xbfe0f000 +# CONSTRUCT x0c004400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.4H, Vt2.4H, Vt3.4H}, [Xn|SP] [, wback] + +:st3 {vVt^".4H", vVtt^".4H", vVttt^".4H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0100 & b_1011=0b01 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR64[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR64[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR64[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR64[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR64[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR64[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR64[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR64[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR64[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR64[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR64[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR64[48,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c004000/mask=xbffff000 +# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c804000/mask=xbfe0f000 +# CONSTRUCT x0c004800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.2S, Vt2.2S, Vt3.2S}, [Xn|SP] [, wback] + +:st3 {vVt^".2S", vVtt^".2S", vVttt^".2S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0100 & b_1011=0b10 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR64[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR64[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR64[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR64[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR64[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR64[32,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c004000/mask=xbffff000 +# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c804000/mask=xbfe0f000 +# CONSTRUCT x4c004000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.16B, Vt2.16B, Vt3.16B}, [Xn|SP] [, wback] + +:st3 {vVt^".16B", vVtt^".16B", vVttt^".16B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0100 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c004000/mask=xbffff000 +# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c804000/mask=xbfe0f000 +# CONSTRUCT x4c004400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.8H, Vt2.8H, Vt3.8H}, [Xn|SP] [, wback] + +:st3 {vVt^".8H", vVtt^".8H", vVttt^".8H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0100 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c004000/mask=xbffff000 +# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c804000/mask=xbfe0f000 +# CONSTRUCT x4c004800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.4S, Vt2.4S, Vt3.4S}, [Xn|SP] [, wback] + +:st3 {vVt^".4S", vVtt^".4S", vVttt^".4S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0100 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c004000/mask=xbffff000 +# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c804000/mask=xbfe0f000 +# CONSTRUCT x4c004c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.2D, Vt2.2D, Vt3.2D}, [Xn|SP] [, wback] + +:st3 {vVt^".2D", vVtt^".2D", vVttt^".2D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0100 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:8 tmp_ldXn = Rt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rttt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rttt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x0d002000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.B, Vt2.B, Vt3.B}[0], [Xn|SP] [, wback] + +:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x0d002400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.B, Vt2.B, Vt3.B}[1], [Xn|SP] [, wback] + +:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x0d002800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.B, Vt2.B, Vt3.B}[2], [Xn|SP] [, wback] + +:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[2], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x0d002c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.B, Vt2.B, Vt3.B}[3], [Xn|SP] [, wback] + +:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[3], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x0d003000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.B, Vt2.B, Vt3.B}[4], [Xn|SP] [, wback] + +:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[4], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x0d003400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.B, Vt2.B, Vt3.B}[5], [Xn|SP] [, wback] + +:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[5], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x0d003800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.B, Vt2.B, Vt3.B}[6], [Xn|SP] [, wback] + +:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[6], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x0d003c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.B, Vt2.B, Vt3.B}[7], [Xn|SP] [, wback] + +:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[7], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x4d002000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.B, Vt2.B, Vt3.B}[8], [Xn|SP] [, wback] + +:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[8], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x4d002400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.B, Vt2.B, Vt3.B}[9], [Xn|SP] [, wback] + +:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[9], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x4d002800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.B, Vt2.B, Vt3.B}[10], [Xn|SP] [, wback] + +:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[10], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x4d002c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.B, Vt2.B, Vt3.B}[11], [Xn|SP] [, wback] + +:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[11], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x4d003000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.B, Vt2.B, Vt3.B}[12], [Xn|SP] [, wback] + +:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[12], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x4d003400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.B, Vt2.B, Vt3.B}[13], [Xn|SP] [, wback] + +:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[13], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x4d003800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.B, Vt2.B, Vt3.B}[14], [Xn|SP] [, wback] + +:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[14], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x4d003c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.B, Vt2.B, Vt3.B}[15], [Xn|SP] [, wback] + +:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[15], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x0d006000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.H, Vt2.H, Vt3.H}[0], [Xn|SP] [, wback] + +:st3 {vVt^".H", vVtt^".H", vVttt^".H"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b011 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x0d006800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.H, Vt2.H, Vt3.H}[1], [Xn|SP] [, wback] + +:st3 {vVt^".H", vVtt^".H", vVttt^".H"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b011 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x0d007000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.H, Vt2.H, Vt3.H}[2], [Xn|SP] [, wback] + +:st3 {vVt^".H", vVtt^".H", vVttt^".H"}[2], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b011 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x0d007800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.H, Vt2.H, Vt3.H}[3], [Xn|SP] [, wback] + +:st3 {vVt^".H", vVtt^".H", vVttt^".H"}[3], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b011 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x4d006000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.H, Vt2.H, Vt3.H}[4], [Xn|SP] [, wback] + +:st3 {vVt^".H", vVtt^".H", vVttt^".H"}[4], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b011 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x4d006800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.H, Vt2.H, Vt3.H}[5], [Xn|SP] [, wback] + +:st3 {vVt^".H", vVtt^".H", vVttt^".H"}[5], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b011 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x4d007000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.H, Vt2.H, Vt3.H}[6], [Xn|SP] [, wback] + +:st3 {vVt^".H", vVtt^".H", vVttt^".H"}[6], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b011 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x4d007800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.H, Vt2.H, Vt3.H}[7], [Xn|SP] [, wback] + +:st3 {vVt^".H", vVtt^".H", vVttt^".H"}[7], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b011 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x0d00a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.S, Vt2.S, Vt3.S}[0], [Xn|SP] [, wback] + +:st3 {vVt^".S", vVtt^".S", vVttt^".S"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b101 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x0d00b000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.S, Vt2.S, Vt3.S}[1], [Xn|SP] [, wback] + +:st3 {vVt^".S", vVtt^".S", vVttt^".S"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b101 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x4d00a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.S, Vt2.S, Vt3.S}[2], [Xn|SP] [, wback] + +:st3 {vVt^".S", vVtt^".S", vVttt^".S"}[2], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b101 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x4d00b000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.S, Vt2.S, Vt3.S}[3], [Xn|SP] [, wback] + +:st3 {vVt^".S", vVtt^".S", vVttt^".S"}[3], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b101 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x0d00a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.D, Vt2.D, Vt3.D}[0], [Xn|SP] [, wback] + +:st3 {vVt^".D", vVtt^".D", vVttt^".D"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b101 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:8 tmp_ldXn = Rt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rttt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000 +# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000 +# CONSTRUCT x4d00a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st3 {Vt.D, Vt2.D, Vt3.D}[1], [Xn|SP] [, wback] + +:st3 {vVt^".D", vVtt^".D", vVttt^".D"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b101 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:8 tmp_ldXn = Rt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rttt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c000000/mask=xbffff000 +# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c800000/mask=xbfe0f000 +# CONSTRUCT x0c000000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.8B, Vt2.8B, Vt3.8B, Vt4.8B}, [Xn|SP] [, wback] + +:st4 {vVt^".8B", vVtt^".8B", vVttt^".8B", vVtttt^".8B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0000 & b_1011=0b00 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & vVtttt & Rtttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR64[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR64[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR64[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR64[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR64[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR64[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR64[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR64[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR64[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR64[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR64[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR64[56,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c000000/mask=xbffff000 +# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c800000/mask=xbfe0f000 +# CONSTRUCT x0c000400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.4H, Vt2.4H, Vt3.4H, Vt4.4H}, [Xn|SP] [, wback] + +:st4 {vVt^".4H", vVtt^".4H", vVttt^".4H", vVtttt^".4H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0000 & b_1011=0b01 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & vVtttt & Rtttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR64[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR64[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR64[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR64[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR64[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR64[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR64[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR64[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR64[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR64[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR64[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR64[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR64[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR64[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR64[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR64[48,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c000000/mask=xbffff000 +# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c800000/mask=xbfe0f000 +# CONSTRUCT x0c000800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.2S, Vt2.2S, Vt3.2S, Vt4.2S}, [Xn|SP] [, wback] + +:st4 {vVt^".2S", vVtt^".2S", vVttt^".2S", vVtttt^".2S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0000 & b_1011=0b10 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & vVtttt & Rtttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR64[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR64[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR64[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtttt_VPR64[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR64[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR64[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR64[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtttt_VPR64[32,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c000000/mask=xbffff000 +# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c800000/mask=xbfe0f000 +# CONSTRUCT x4c000000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.16B, Vt2.16B, Vt3.16B, Vt4.16B}, [Xn|SP] [, wback] + +:st4 {vVt^".16B", vVtt^".16B", vVttt^".16B", vVtttt^".16B"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0000 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c000000/mask=xbffff000 +# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c800000/mask=xbfe0f000 +# CONSTRUCT x4c000400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.8H, Vt2.8H, Vt3.8H, Vt4.8H}, [Xn|SP] [, wback] + +:st4 {vVt^".8H", vVtt^".8H", vVttt^".8H", vVtttt^".8H"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0000 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c000000/mask=xbffff000 +# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c800000/mask=xbfe0f000 +# CONSTRUCT x4c000800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.4S, Vt2.4S, Vt3.4S, Vt4.4S}, [Xn|SP] [, wback] + +:st4 {vVt^".4S", vVtt^".4S", vVttt^".4S", vVtttt^".4S"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0000 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtttt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtttt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtttt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtttt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c000000/mask=xbffff000 +# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c800000/mask=xbfe0f000 +# CONSTRUCT x4c000c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.2D, Vt2.2D, Vt3.2D, Vt4.2D}, [Xn|SP] [, wback] + +:st4 {vVt^".2D", vVtt^".2D", vVttt^".2D", vVtttt^".2D"}, [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0000 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:8 tmp_ldXn = Rt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rttt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtttt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rttt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtttt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x0d202000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[0], [Xn|SP] [, wback] + +:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[0,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x0d202400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[1], [Xn|SP] [, wback] + +:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[8,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x0d202800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[2], [Xn|SP] [, wback] + +:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[2], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[16,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x0d202c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[3], [Xn|SP] [, wback] + +:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[3], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[24,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x0d203000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[4], [Xn|SP] [, wback] + +:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[4], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[32,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x0d203400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[5], [Xn|SP] [, wback] + +:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[5], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[40,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x0d203800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[6], [Xn|SP] [, wback] + +:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[6], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[48,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x0d203c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[7], [Xn|SP] [, wback] + +:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[7], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[56,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x4d202000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[8], [Xn|SP] [, wback] + +:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[8], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[64,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x4d202400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[9], [Xn|SP] [, wback] + +:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[9], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[72,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x4d202800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[10], [Xn|SP] [, wback] + +:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[10], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[80,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x4d202c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[11], [Xn|SP] [, wback] + +:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[11], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[88,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x4d203000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[12], [Xn|SP] [, wback] + +:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[12], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[96,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x4d203400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[13], [Xn|SP] [, wback] + +:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[13], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[104,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x4d203800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[14], [Xn|SP] [, wback] + +:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[14], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[112,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x4d203c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[15], [Xn|SP] [, wback] + +:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[15], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:1 tmp_ldXn = Rt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rttt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + *:1 tmp_ldXn = Rtttt_VPR128[120,8]; + tmp_ldXn = tmp_ldXn + 1; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x0d206000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[0], [Xn|SP] [, wback] + +:st4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b011 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR128[0,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x0d206800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[1], [Xn|SP] [, wback] + +:st4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b011 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR128[16,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x0d207000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[2], [Xn|SP] [, wback] + +:st4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[2], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b011 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR128[32,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x0d207800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[3], [Xn|SP] [, wback] + +:st4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[3], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b011 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR128[48,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x4d206000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[4], [Xn|SP] [, wback] + +:st4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[4], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b011 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR128[64,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x4d206800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[5], [Xn|SP] [, wback] + +:st4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[5], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b011 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR128[80,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x4d207000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[6], [Xn|SP] [, wback] + +:st4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[6], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b011 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR128[96,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x4d207800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[7], [Xn|SP] [, wback] + +:st4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[7], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b011 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:2 tmp_ldXn = Rt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rttt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + *:2 tmp_ldXn = Rtttt_VPR128[112,16]; + tmp_ldXn = tmp_ldXn + 2; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x0d20a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.S, Vt2.S, Vt3.S, Vt4.S}[0], [Xn|SP] [, wback] + +:st4 {vVt^".S", vVtt^".S", vVttt^".S", vVtttt^".S"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b101 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtttt_VPR128[0,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x0d20b000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.S, Vt2.S, Vt3.S, Vt4.S}[1], [Xn|SP] [, wback] + +:st4 {vVt^".S", vVtt^".S", vVttt^".S", vVtttt^".S"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b101 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtttt_VPR128[32,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x4d20a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.S, Vt2.S, Vt3.S, Vt4.S}[2], [Xn|SP] [, wback] + +:st4 {vVt^".S", vVtt^".S", vVttt^".S", vVtttt^".S"}[2], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b101 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtttt_VPR128[64,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x4d20b000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.S, Vt2.S, Vt3.S, Vt4.S}[3], [Xn|SP] [, wback] + +:st4 {vVt^".S", vVtt^".S", vVttt^".S", vVtttt^".S"}[3], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b101 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:4 tmp_ldXn = Rt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rttt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + *:4 tmp_ldXn = Rtttt_VPR128[96,32]; + tmp_ldXn = tmp_ldXn + 4; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x0d20a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.D, Vt2.D, Vt3.D, Vt4.D}[0], [Xn|SP] [, wback] + +:st4 {vVt^".D", vVtt^".D", vVttt^".D", vVtttt^".D"}[0], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b101 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:8 tmp_ldXn = Rt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rttt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtttt_VPR128[0,64]; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} + +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000 +# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000 +# CONSTRUCT x4d20a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES +# st4 {Vt.D, Vt2.D, Vt3.D, Vt4.D}[1], [Xn|SP] [, wback] + +:st4 {vVt^".D", vVtt^".D", vVttt^".D", vVtttt^".D"}[1], [Rn_GPR64xsp]^ldst_wback +is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b101 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64 +{ + tmp_ldXn = Rn_GPR64xsp; + *:8 tmp_ldXn = Rt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rttt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + *:8 tmp_ldXn = Rtttt_VPR128[64,64]; + tmp_ldXn = tmp_ldXn + 8; + # neglected zexts + build ldst_wback; +} diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64neon.sinc b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64neon.sinc new file mode 100644 index 0000000..58f6137 --- /dev/null +++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64neon.sinc @@ -0,0 +1,29911 @@ +# C7.2.1 ABS page C7-1009 line 58362 KEEPWITH +# +# The semantics in this file are auto-generated with armit.py script +# in the andre directory (capture output and replace file): +# +# python ../../../ProcessorTest/test/andre/scrape/armit.py --arch a64 --sort --refurb --smacro primitive --sinc languages/AARCH64neon.sinc +# +# The AUNIT tests are run using the command line options from the +# comment with the python script aunit.py in the cunit directory: +# +# (cd ../../../ProcessorTest/test/cunit; python aunit.py OPTIONS) +# +# (aunit.py may require a local copy of a current andre exhaust). + +# C7.2.1 ABS page C7-2017 line 117868 MATCH x5e20b800/mask=xff3ffc00 +# CONSTRUCT x5ee0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =abs +# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1 +# AUNIT --inst x5ee0b800/mask=xfffffc00 --status pass +# ABS Scalar + +:abs Rd_FPR64, Rn_FPR64 +is b_2431=0b01011110 & b_2223=0b11 & b_1021=0b100000101110 & Rd_FPR64 & Rn_FPR64 & Zd +{ + Rd_FPR64 = MP_INT_ABS(Rn_FPR64); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.1 ABS page C7-2017 line 117868 MATCH x0e20b800/mask=xbf3ffc00 +# CONSTRUCT x0e20b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$abs@1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@1 +# AUNIT --inst x0e20b800/mask=xfffffc00 --status pass +# ABS Vector 8B when size = 00 , Q = 0 + +:abs Rd_VPR64.8B, Rn_VPR64.8B +is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000101110 & Rd_VPR64.8B & Rn_VPR64.8B & Zd +{ + # simd unary Rd_VPR64.8B = MP_INT_ABS(Rn_VPR64.8B) on lane size 1 + Rd_VPR64.8B[0,8] = MP_INT_ABS(Rn_VPR64.8B[0,8]); + Rd_VPR64.8B[8,8] = MP_INT_ABS(Rn_VPR64.8B[8,8]); + Rd_VPR64.8B[16,8] = MP_INT_ABS(Rn_VPR64.8B[16,8]); + Rd_VPR64.8B[24,8] = MP_INT_ABS(Rn_VPR64.8B[24,8]); + Rd_VPR64.8B[32,8] = MP_INT_ABS(Rn_VPR64.8B[32,8]); + Rd_VPR64.8B[40,8] = MP_INT_ABS(Rn_VPR64.8B[40,8]); + Rd_VPR64.8B[48,8] = MP_INT_ABS(Rn_VPR64.8B[48,8]); + Rd_VPR64.8B[56,8] = MP_INT_ABS(Rn_VPR64.8B[56,8]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.1 ABS page C7-2017 line 117868 MATCH x0e20b800/mask=xbf3ffc00 +# CONSTRUCT x4e20b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$abs@1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@1 +# AUNIT --inst x4e20b800/mask=xfffffc00 --status pass +# ABS Vector SIMD 16B when size = 00 , Q = 1 + +:abs Rd_VPR128.16B, Rn_VPR128.16B +is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000101110 & Rd_VPR128.16B & Rn_VPR128.16B & Zd +{ + # simd unary Rd_VPR128.16B = MP_INT_ABS(Rn_VPR128.16B) on lane size 1 + Rd_VPR128.16B[0,8] = MP_INT_ABS(Rn_VPR128.16B[0,8]); + Rd_VPR128.16B[8,8] = MP_INT_ABS(Rn_VPR128.16B[8,8]); + Rd_VPR128.16B[16,8] = MP_INT_ABS(Rn_VPR128.16B[16,8]); + Rd_VPR128.16B[24,8] = MP_INT_ABS(Rn_VPR128.16B[24,8]); + Rd_VPR128.16B[32,8] = MP_INT_ABS(Rn_VPR128.16B[32,8]); + Rd_VPR128.16B[40,8] = MP_INT_ABS(Rn_VPR128.16B[40,8]); + Rd_VPR128.16B[48,8] = MP_INT_ABS(Rn_VPR128.16B[48,8]); + Rd_VPR128.16B[56,8] = MP_INT_ABS(Rn_VPR128.16B[56,8]); + Rd_VPR128.16B[64,8] = MP_INT_ABS(Rn_VPR128.16B[64,8]); + Rd_VPR128.16B[72,8] = MP_INT_ABS(Rn_VPR128.16B[72,8]); + Rd_VPR128.16B[80,8] = MP_INT_ABS(Rn_VPR128.16B[80,8]); + Rd_VPR128.16B[88,8] = MP_INT_ABS(Rn_VPR128.16B[88,8]); + Rd_VPR128.16B[96,8] = MP_INT_ABS(Rn_VPR128.16B[96,8]); + Rd_VPR128.16B[104,8] = MP_INT_ABS(Rn_VPR128.16B[104,8]); + Rd_VPR128.16B[112,8] = MP_INT_ABS(Rn_VPR128.16B[112,8]); + Rd_VPR128.16B[120,8] = MP_INT_ABS(Rn_VPR128.16B[120,8]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.1 ABS page C7-2017 line 117868 MATCH x0e20b800/mask=xbf3ffc00 +# CONSTRUCT x0e60b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$abs@2 +# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@2 +# AUNIT --inst x0e60b800/mask=xfffffc00 --status pass +# ABS Vector SIMD 4H when size = 01 , Q = 0 + +:abs Rd_VPR64.4H, Rn_VPR64.4H +is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000101110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd +{ + # simd unary Rd_VPR64.4H = MP_INT_ABS(Rn_VPR64.4H) on lane size 2 + Rd_VPR64.4H[0,16] = MP_INT_ABS(Rn_VPR64.4H[0,16]); + Rd_VPR64.4H[16,16] = MP_INT_ABS(Rn_VPR64.4H[16,16]); + Rd_VPR64.4H[32,16] = MP_INT_ABS(Rn_VPR64.4H[32,16]); + Rd_VPR64.4H[48,16] = MP_INT_ABS(Rn_VPR64.4H[48,16]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.1 ABS page C7-2017 line 117868 MATCH x0e20b800/mask=xbf3ffc00 +# CONSTRUCT x4e60b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$abs@2 +# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@2 +# AUNIT --inst x4e60b800/mask=xfffffc00 --status pass +# ABS Vector SIMD 8H when size = 01 , Q = 1 + +:abs Rd_VPR128.8H, Rn_VPR128.8H +is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000101110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd +{ + # simd unary Rd_VPR128.8H = MP_INT_ABS(Rn_VPR128.8H) on lane size 2 + Rd_VPR128.8H[0,16] = MP_INT_ABS(Rn_VPR128.8H[0,16]); + Rd_VPR128.8H[16,16] = MP_INT_ABS(Rn_VPR128.8H[16,16]); + Rd_VPR128.8H[32,16] = MP_INT_ABS(Rn_VPR128.8H[32,16]); + Rd_VPR128.8H[48,16] = MP_INT_ABS(Rn_VPR128.8H[48,16]); + Rd_VPR128.8H[64,16] = MP_INT_ABS(Rn_VPR128.8H[64,16]); + Rd_VPR128.8H[80,16] = MP_INT_ABS(Rn_VPR128.8H[80,16]); + Rd_VPR128.8H[96,16] = MP_INT_ABS(Rn_VPR128.8H[96,16]); + Rd_VPR128.8H[112,16] = MP_INT_ABS(Rn_VPR128.8H[112,16]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.1 ABS page C7-2017 line 117868 MATCH x0e20b800/mask=xbf3ffc00 +# CONSTRUCT x0ea0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$abs@4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@4 +# AUNIT --inst x0ea0b800/mask=xfffffc00 --status pass +# ABS Vector SIMD 2S when size = 10 , Q = 0 + +:abs Rd_VPR64.2S, Rn_VPR64.2S +is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000101110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd +{ + # simd unary Rd_VPR64.2S = MP_INT_ABS(Rn_VPR64.2S) on lane size 4 + Rd_VPR64.2S[0,32] = MP_INT_ABS(Rn_VPR64.2S[0,32]); + Rd_VPR64.2S[32,32] = MP_INT_ABS(Rn_VPR64.2S[32,32]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.1 ABS page C7-2017 line 117868 MATCH x0e20b800/mask=xbf3ffc00 +# CONSTRUCT x4ea0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$abs@4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@4 +# AUNIT --inst x4ea0b800/mask=xfffffc00 --status pass +# ABS Vector SIMD 4S when size = 10 , Q = 1 + +:abs Rd_VPR128.4S, Rn_VPR128.4S +is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000101110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd +{ + # simd unary Rd_VPR128.4S = MP_INT_ABS(Rn_VPR128.4S) on lane size 4 + Rd_VPR128.4S[0,32] = MP_INT_ABS(Rn_VPR128.4S[0,32]); + Rd_VPR128.4S[32,32] = MP_INT_ABS(Rn_VPR128.4S[32,32]); + Rd_VPR128.4S[64,32] = MP_INT_ABS(Rn_VPR128.4S[64,32]); + Rd_VPR128.4S[96,32] = MP_INT_ABS(Rn_VPR128.4S[96,32]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.1 ABS page C7-2017 line 117868 MATCH x0e20b800/mask=xbf3ffc00 +# CONSTRUCT x4ee0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$abs@8 +# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@8 +# AUNIT --inst x4ee0b800/mask=xfffffc00 --status pass +# ABS Vector SIMD 2D when size = 11 , Q = 1 + +:abs Rd_VPR128.2D, Rn_VPR128.2D +is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b11 & b_1021=0b100000101110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd +{ + # simd unary Rd_VPR128.2D = MP_INT_ABS(Rn_VPR128.2D) on lane size 8 + Rd_VPR128.2D[0,64] = MP_INT_ABS(Rn_VPR128.2D[0,64]); + Rd_VPR128.2D[64,64] = MP_INT_ABS(Rn_VPR128.2D[64,64]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.2 ADD (vector) page C7-2019 line 118000 MATCH x5e208400/mask=xff20fc00 +# CONSTRUCT x5ee08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =+ +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2 +# AUNIT --inst x5ee08400/mask=xffe0fc00 --status pass + +:add Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x10 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = Rn_FPR64 + Rm_FPR64; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.2 ADD (vector) page C7-2019 line 118000 MATCH x0e208400/mask=xbf20fc00 +# CONSTRUCT x4e208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(force-primitive) ARG1 ARG2 ARG3 =$+@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@1 +# AUNIT --inst x4e208400/mask=xffe0fc00 --status pass + +:add Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x10 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + # simd infix Rd_VPR128.16B = Rn_VPR128.16B + Rm_VPR128.16B on lane size 1 + Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] + Rm_VPR128.16B[0,8]; + Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] + Rm_VPR128.16B[8,8]; + Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] + Rm_VPR128.16B[16,8]; + Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] + Rm_VPR128.16B[24,8]; + Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] + Rm_VPR128.16B[32,8]; + Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] + Rm_VPR128.16B[40,8]; + Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] + Rm_VPR128.16B[48,8]; + Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] + Rm_VPR128.16B[56,8]; + Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] + Rm_VPR128.16B[64,8]; + Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] + Rm_VPR128.16B[72,8]; + Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] + Rm_VPR128.16B[80,8]; + Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] + Rm_VPR128.16B[88,8]; + Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] + Rm_VPR128.16B[96,8]; + Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] + Rm_VPR128.16B[104,8]; + Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] + Rm_VPR128.16B[112,8]; + Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] + Rm_VPR128.16B[120,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.2 ADD (vector) page C7-2019 line 118000 MATCH x0e208400/mask=xbf20fc00 +# CONSTRUCT x4e608400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@2 +# AUNIT --inst x4e608400/mask=xffe0fc00 --status pass + +:add Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x10 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + # simd infix Rd_VPR128.8H = Rn_VPR128.8H + Rm_VPR128.8H on lane size 2 + Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] + Rm_VPR128.8H[0,16]; + Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] + Rm_VPR128.8H[16,16]; + Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] + Rm_VPR128.8H[32,16]; + Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] + Rm_VPR128.8H[48,16]; + Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] + Rm_VPR128.8H[64,16]; + Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] + Rm_VPR128.8H[80,16]; + Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] + Rm_VPR128.8H[96,16]; + Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] + Rm_VPR128.8H[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.2 ADD (vector) page C7-2019 line 118000 MATCH x0e208400/mask=xbf20fc00 +# CONSTRUCT x4ea08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(force-primitive) ARG1 ARG2 ARG3 =$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@4 +# AUNIT --inst x4ea08400/mask=xffe0fc00 --status pass + +:add Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x10 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd infix Rd_VPR128.4S = Rn_VPR128.4S + Rm_VPR128.4S on lane size 4 + Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] + Rm_VPR128.4S[0,32]; + Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] + Rm_VPR128.4S[32,32]; + Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] + Rm_VPR128.4S[64,32]; + Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] + Rm_VPR128.4S[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.2 ADD (vector) page C7-2019 line 118000 MATCH x0e208400/mask=xbf20fc00 +# CONSTRUCT x4ee08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@8 +# AUNIT --inst x4ee08400/mask=xffe0fc00 --status pass + +:add Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x10 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + # simd infix Rd_VPR128.2D = Rn_VPR128.2D + Rm_VPR128.2D on lane size 8 + Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] + Rm_VPR128.2D[0,64]; + Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] + Rm_VPR128.2D[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.2 ADD (vector) page C7-2019 line 118000 MATCH x0e208400/mask=xbf20fc00 +# CONSTRUCT x0e208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$+@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@1 +# AUNIT --inst x0e208400/mask=xffe0fc00 --status pass + +:add Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x10 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + # simd infix Rd_VPR64.8B = Rn_VPR64.8B + Rm_VPR64.8B on lane size 1 + Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] + Rm_VPR64.8B[0,8]; + Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] + Rm_VPR64.8B[8,8]; + Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] + Rm_VPR64.8B[16,8]; + Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] + Rm_VPR64.8B[24,8]; + Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] + Rm_VPR64.8B[32,8]; + Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] + Rm_VPR64.8B[40,8]; + Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] + Rm_VPR64.8B[48,8]; + Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] + Rm_VPR64.8B[56,8]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.2 ADD (vector) page C7-2019 line 118000 MATCH x0e208400/mask=xbf20fc00 +# CONSTRUCT x0e608400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@2 +# AUNIT --inst x0e608400/mask=xffe0fc00 --status pass + +:add Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x10 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + # simd infix Rd_VPR64.4H = Rn_VPR64.4H + Rm_VPR64.4H on lane size 2 + Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] + Rm_VPR64.4H[0,16]; + Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] + Rm_VPR64.4H[16,16]; + Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] + Rm_VPR64.4H[32,16]; + Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] + Rm_VPR64.4H[48,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.2 ADD (vector) page C7-2019 line 118000 MATCH x0e208400/mask=xbf20fc00 +# CONSTRUCT x0ea08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(force-primitive) ARG1 ARG2 ARG3 =$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@4 +# AUNIT --inst x0ea08400/mask=xffe0fc00 --status pass + +:add Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x10 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + # simd infix Rd_VPR64.2S = Rn_VPR64.2S + Rm_VPR64.2S on lane size 4 + Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] + Rm_VPR64.2S[0,32]; + Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] + Rm_VPR64.2S[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.3 ADDHN, ADDHN2 page C7-2021 line 118138 MATCH x0e204000/mask=xbf20fc00 +# CONSTRUCT x0ea04000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $+@8 &=$shuffle@1-0@3-1:4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_addhn/3@8 +# AUNIT --inst x0ea04000/mask=xffe0fc00 --status pass + +:addhn Rd_VPR64.2S, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x4 & b_1011=0 & Rn_VPR128.2D & Rd_VPR64.2S & Rd_VPR128 & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.2D + Rm_VPR128.2D on lane size 8 + TMPQ1[0,64] = Rn_VPR128.2D[0,64] + Rm_VPR128.2D[0,64]; + TMPQ1[64,64] = Rn_VPR128.2D[64,64] + Rm_VPR128.2D[64,64]; + # simd shuffle Rd_VPR64.2S = TMPQ1 (@1-0@3-1) lane size 4 + Rd_VPR64.2S[0,32] = TMPQ1[32,32]; + Rd_VPR64.2S[32,32] = TMPQ1[96,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.3 ADDHN, ADDHN2 page C7-2021 line 118138 MATCH x0e204000/mask=xbf20fc00 +# CONSTRUCT x0e604000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $+@4 &=$shuffle@1-0@3-1@5-2@7-3:2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_addhn/3@4 +# AUNIT --inst x0e604000/mask=xffe0fc00 --status pass + +:addhn Rd_VPR64.4H, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x4 & b_1011=0 & Rn_VPR128.4S & Rd_VPR64.4H & Rd_VPR128 & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.4S + Rm_VPR128.4S on lane size 4 + TMPQ1[0,32] = Rn_VPR128.4S[0,32] + Rm_VPR128.4S[0,32]; + TMPQ1[32,32] = Rn_VPR128.4S[32,32] + Rm_VPR128.4S[32,32]; + TMPQ1[64,32] = Rn_VPR128.4S[64,32] + Rm_VPR128.4S[64,32]; + TMPQ1[96,32] = Rn_VPR128.4S[96,32] + Rm_VPR128.4S[96,32]; + # simd shuffle Rd_VPR64.4H = TMPQ1 (@1-0@3-1@5-2@7-3) lane size 2 + Rd_VPR64.4H[0,16] = TMPQ1[16,16]; + Rd_VPR64.4H[16,16] = TMPQ1[48,16]; + Rd_VPR64.4H[32,16] = TMPQ1[80,16]; + Rd_VPR64.4H[48,16] = TMPQ1[112,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.3 ADDHN, ADDHN2 page C7-2021 line 118138 MATCH x0e204000/mask=xbf20fc00 +# CONSTRUCT x0e204000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $+@2 &=$shuffle@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7:1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_addhn/3@2 +# AUNIT --inst x0e204000/mask=xffe0fc00 --status pass + +:addhn Rd_VPR64.8B, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x4 & b_1011=0 & Rn_VPR128.8H & Rd_VPR64.8B & Rd_VPR128 & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.8H + Rm_VPR128.8H on lane size 2 + TMPQ1[0,16] = Rn_VPR128.8H[0,16] + Rm_VPR128.8H[0,16]; + TMPQ1[16,16] = Rn_VPR128.8H[16,16] + Rm_VPR128.8H[16,16]; + TMPQ1[32,16] = Rn_VPR128.8H[32,16] + Rm_VPR128.8H[32,16]; + TMPQ1[48,16] = Rn_VPR128.8H[48,16] + Rm_VPR128.8H[48,16]; + TMPQ1[64,16] = Rn_VPR128.8H[64,16] + Rm_VPR128.8H[64,16]; + TMPQ1[80,16] = Rn_VPR128.8H[80,16] + Rm_VPR128.8H[80,16]; + TMPQ1[96,16] = Rn_VPR128.8H[96,16] + Rm_VPR128.8H[96,16]; + TMPQ1[112,16] = Rn_VPR128.8H[112,16] + Rm_VPR128.8H[112,16]; + # simd shuffle Rd_VPR64.8B = TMPQ1 (@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7) lane size 1 + Rd_VPR64.8B[0,8] = TMPQ1[8,8]; + Rd_VPR64.8B[8,8] = TMPQ1[24,8]; + Rd_VPR64.8B[16,8] = TMPQ1[40,8]; + Rd_VPR64.8B[24,8] = TMPQ1[56,8]; + Rd_VPR64.8B[32,8] = TMPQ1[72,8]; + Rd_VPR64.8B[40,8] = TMPQ1[88,8]; + Rd_VPR64.8B[48,8] = TMPQ1[104,8]; + Rd_VPR64.8B[56,8] = TMPQ1[120,8]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.3 ADDHN, ADDHN2 page C7-2021 line 118138 MATCH x0e204000/mask=xbf20fc00 +# CONSTRUCT x4e204000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $+@2 &=$shuffle@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15:1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_addhn2/3@2 +# AUNIT --inst x4e204000/mask=xffe0fc00 --status pass + +:addhn2 Rd_VPR128.16B, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x4 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.16B & Rd_VPR128 & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.8H + Rm_VPR128.8H on lane size 2 + TMPQ1[0,16] = Rn_VPR128.8H[0,16] + Rm_VPR128.8H[0,16]; + TMPQ1[16,16] = Rn_VPR128.8H[16,16] + Rm_VPR128.8H[16,16]; + TMPQ1[32,16] = Rn_VPR128.8H[32,16] + Rm_VPR128.8H[32,16]; + TMPQ1[48,16] = Rn_VPR128.8H[48,16] + Rm_VPR128.8H[48,16]; + TMPQ1[64,16] = Rn_VPR128.8H[64,16] + Rm_VPR128.8H[64,16]; + TMPQ1[80,16] = Rn_VPR128.8H[80,16] + Rm_VPR128.8H[80,16]; + TMPQ1[96,16] = Rn_VPR128.8H[96,16] + Rm_VPR128.8H[96,16]; + TMPQ1[112,16] = Rn_VPR128.8H[112,16] + Rm_VPR128.8H[112,16]; + # simd shuffle Rd_VPR128.16B = TMPQ1 (@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15) lane size 1 + Rd_VPR128.16B[64,8] = TMPQ1[8,8]; + Rd_VPR128.16B[72,8] = TMPQ1[24,8]; + Rd_VPR128.16B[80,8] = TMPQ1[40,8]; + Rd_VPR128.16B[88,8] = TMPQ1[56,8]; + Rd_VPR128.16B[96,8] = TMPQ1[72,8]; + Rd_VPR128.16B[104,8] = TMPQ1[88,8]; + Rd_VPR128.16B[112,8] = TMPQ1[104,8]; + Rd_VPR128.16B[120,8] = TMPQ1[120,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.3 ADDHN, ADDHN2 page C7-2021 line 118138 MATCH x0e204000/mask=xbf20fc00 +# CONSTRUCT x4ea04000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $+@8 &=$shuffle@1-2@3-3:4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_addhn2/3@8 +# AUNIT --inst x4ea04000/mask=xffe0fc00 --status pass + +:addhn2 Rd_VPR128.4S, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x4 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.4S & Rd_VPR128 & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.2D + Rm_VPR128.2D on lane size 8 + TMPQ1[0,64] = Rn_VPR128.2D[0,64] + Rm_VPR128.2D[0,64]; + TMPQ1[64,64] = Rn_VPR128.2D[64,64] + Rm_VPR128.2D[64,64]; + # simd shuffle Rd_VPR128.4S = TMPQ1 (@1-2@3-3) lane size 4 + Rd_VPR128.4S[64,32] = TMPQ1[32,32]; + Rd_VPR128.4S[96,32] = TMPQ1[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.3 ADDHN, ADDHN2 page C7-2021 line 118138 MATCH x0e204000/mask=xbf20fc00 +# CONSTRUCT x4e604000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $+@4 &=$shuffle@1-4@3-5@5-6@7-7:2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_addhn2/3@4 +# AUNIT --inst x4e604000/mask=xffe0fc00 --status pass + +:addhn2 Rd_VPR128.8H, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x4 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.8H & Rd_VPR128 & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.4S + Rm_VPR128.4S on lane size 4 + TMPQ1[0,32] = Rn_VPR128.4S[0,32] + Rm_VPR128.4S[0,32]; + TMPQ1[32,32] = Rn_VPR128.4S[32,32] + Rm_VPR128.4S[32,32]; + TMPQ1[64,32] = Rn_VPR128.4S[64,32] + Rm_VPR128.4S[64,32]; + TMPQ1[96,32] = Rn_VPR128.4S[96,32] + Rm_VPR128.4S[96,32]; + # simd shuffle Rd_VPR128.8H = TMPQ1 (@1-4@3-5@5-6@7-7) lane size 2 + Rd_VPR128.8H[64,16] = TMPQ1[16,16]; + Rd_VPR128.8H[80,16] = TMPQ1[48,16]; + Rd_VPR128.8H[96,16] = TMPQ1[80,16]; + Rd_VPR128.8H[112,16] = TMPQ1[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.4 ADDP (scalar) page C7-2023 line 118265 MATCH x5e31b800/mask=xff3ffc00 +# CONSTRUCT x5ef1b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =#+ +# SMACRO(pseudo) ARG1 ARG2 =NEON_addp/1@8 +# AUNIT --inst x5ef1b800/mask=xfffffc00 --status pass + +:addp Rd_FPR64, Rn_VPR128.2D +is b_3031=1 & u=0 & b_2428=0x1e & b_23=1 & b_1722=0x38 & b_1216=0x1b & b_1011=2 & Rn_VPR128.2D & Rd_FPR64 & Zd +{ + # sipd infix Rd_FPR64 = +(Rn_VPR128.2D) on pairs lane size (8 to 8) + local tmp1 = Rn_VPR128.2D[0,64]; + local tmp2 = Rn_VPR128.2D[64,64]; + Rd_FPR64 = tmp1 + tmp2; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.5 ADDP (vector) page C7-2025 line 118351 MATCH x0e20bc00/mask=xbf20fc00 +# CONSTRUCT x4e20bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 var:16 ARG2 ARG3 =#+/2 = +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@1 +# AUNIT --inst x4e20bc00/mask=xffe0fc00 --status pass + +:addp Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x17 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + TMPQ1 = 0; + # sipd infix TMPQ1 = +(Rn_VPR128.16B,Rm_VPR128.16B) on pairs lane size (1 to 1) + local tmp2 = Rn_VPR128.16B[0,8]; + local tmp3 = Rn_VPR128.16B[8,8]; + TMPQ1[0,8] = tmp2 + tmp3; + tmp2 = Rn_VPR128.16B[16,8]; + tmp3 = Rn_VPR128.16B[24,8]; + TMPQ1[8,8] = tmp2 + tmp3; + tmp2 = Rn_VPR128.16B[32,8]; + tmp3 = Rn_VPR128.16B[40,8]; + TMPQ1[16,8] = tmp2 + tmp3; + tmp2 = Rn_VPR128.16B[48,8]; + tmp3 = Rn_VPR128.16B[56,8]; + TMPQ1[24,8] = tmp2 + tmp3; + tmp2 = Rn_VPR128.16B[64,8]; + tmp3 = Rn_VPR128.16B[72,8]; + TMPQ1[32,8] = tmp2 + tmp3; + tmp2 = Rn_VPR128.16B[80,8]; + tmp3 = Rn_VPR128.16B[88,8]; + TMPQ1[40,8] = tmp2 + tmp3; + tmp2 = Rn_VPR128.16B[96,8]; + tmp3 = Rn_VPR128.16B[104,8]; + TMPQ1[48,8] = tmp2 + tmp3; + tmp2 = Rn_VPR128.16B[112,8]; + tmp3 = Rn_VPR128.16B[120,8]; + TMPQ1[56,8] = tmp2 + tmp3; + tmp2 = Rm_VPR128.16B[0,8]; + tmp3 = Rm_VPR128.16B[8,8]; + TMPQ1[64,8] = tmp2 + tmp3; + tmp2 = Rm_VPR128.16B[16,8]; + tmp3 = Rm_VPR128.16B[24,8]; + TMPQ1[72,8] = tmp2 + tmp3; + tmp2 = Rm_VPR128.16B[32,8]; + tmp3 = Rm_VPR128.16B[40,8]; + TMPQ1[80,8] = tmp2 + tmp3; + tmp2 = Rm_VPR128.16B[48,8]; + tmp3 = Rm_VPR128.16B[56,8]; + TMPQ1[88,8] = tmp2 + tmp3; + tmp2 = Rm_VPR128.16B[64,8]; + tmp3 = Rm_VPR128.16B[72,8]; + TMPQ1[96,8] = tmp2 + tmp3; + tmp2 = Rm_VPR128.16B[80,8]; + tmp3 = Rm_VPR128.16B[88,8]; + TMPQ1[104,8] = tmp2 + tmp3; + tmp2 = Rm_VPR128.16B[96,8]; + tmp3 = Rm_VPR128.16B[104,8]; + TMPQ1[112,8] = tmp2 + tmp3; + tmp2 = Rm_VPR128.16B[112,8]; + tmp3 = Rm_VPR128.16B[120,8]; + TMPQ1[120,8] = tmp2 + tmp3; + Rd_VPR128.16B = TMPQ1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.5 ADDP (vector) page C7-2025 line 118351 MATCH x0e20bc00/mask=xbf20fc00 +# CONSTRUCT x4ee0bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 var:16 ARG2 ARG3 =#+/2 = +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@8 +# AUNIT --inst x4ee0bc00/mask=xffe0fc00 --status pass + +:addp Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x17 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + TMPQ1 = 0; + # sipd infix TMPQ1 = +(Rn_VPR128.2D,Rm_VPR128.2D) on pairs lane size (8 to 8) + local tmp2 = Rn_VPR128.2D[0,64]; + local tmp3 = Rn_VPR128.2D[64,64]; + TMPQ1[0,64] = tmp2 + tmp3; + tmp2 = Rm_VPR128.2D[0,64]; + tmp3 = Rm_VPR128.2D[64,64]; + TMPQ1[64,64] = tmp2 + tmp3; + Rd_VPR128.2D = TMPQ1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.5 ADDP (vector) page C7-2025 line 118351 MATCH x0e20bc00/mask=xbf20fc00 +# CONSTRUCT x0ea0bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 var:8 ARG2 ARG3 =#+/2 = +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@4 +# AUNIT --inst x0ea0bc00/mask=xffe0fc00 --status pass + +:addp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x17 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + TMPD1 = 0; + # sipd infix TMPD1 = +(Rn_VPR64.2S,Rm_VPR64.2S) on pairs lane size (4 to 4) + local tmp2 = Rn_VPR64.2S[0,32]; + local tmp3 = Rn_VPR64.2S[32,32]; + TMPD1[0,32] = tmp2 + tmp3; + tmp2 = Rm_VPR64.2S[0,32]; + tmp3 = Rm_VPR64.2S[32,32]; + TMPD1[32,32] = tmp2 + tmp3; + Rd_VPR64.2S = TMPD1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.5 ADDP (vector) page C7-2025 line 118351 MATCH x0e20bc00/mask=xbf20fc00 +# CONSTRUCT x0e60bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 var:8 ARG2 ARG3 =#+/2 = +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@2 +# AUNIT --inst x0e60bc00/mask=xffe0fc00 --status pass + +:addp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x17 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + TMPD1 = 0; + # sipd infix TMPD1 = +(Rn_VPR64.4H,Rm_VPR64.4H) on pairs lane size (2 to 2) + local tmp2 = Rn_VPR64.4H[0,16]; + local tmp3 = Rn_VPR64.4H[16,16]; + TMPD1[0,16] = tmp2 + tmp3; + tmp2 = Rn_VPR64.4H[32,16]; + tmp3 = Rn_VPR64.4H[48,16]; + TMPD1[16,16] = tmp2 + tmp3; + tmp2 = Rm_VPR64.4H[0,16]; + tmp3 = Rm_VPR64.4H[16,16]; + TMPD1[32,16] = tmp2 + tmp3; + tmp2 = Rm_VPR64.4H[32,16]; + tmp3 = Rm_VPR64.4H[48,16]; + TMPD1[48,16] = tmp2 + tmp3; + Rd_VPR64.4H = TMPD1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.5 ADDP (vector) page C7-2025 line 118351 MATCH x0e20bc00/mask=xbf20fc00 +# CONSTRUCT x4ea0bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 var:16 ARG2 ARG3 =#+/2 = +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@4 +# AUNIT --inst x4ea0bc00/mask=xffe0fc00 --status pass + +:addp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x17 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + TMPQ1 = 0; + # sipd infix TMPQ1 = +(Rn_VPR128.4S,Rm_VPR128.4S) on pairs lane size (4 to 4) + local tmp2 = Rn_VPR128.4S[0,32]; + local tmp3 = Rn_VPR128.4S[32,32]; + TMPQ1[0,32] = tmp2 + tmp3; + tmp2 = Rn_VPR128.4S[64,32]; + tmp3 = Rn_VPR128.4S[96,32]; + TMPQ1[32,32] = tmp2 + tmp3; + tmp2 = Rm_VPR128.4S[0,32]; + tmp3 = Rm_VPR128.4S[32,32]; + TMPQ1[64,32] = tmp2 + tmp3; + tmp2 = Rm_VPR128.4S[64,32]; + tmp3 = Rm_VPR128.4S[96,32]; + TMPQ1[96,32] = tmp2 + tmp3; + Rd_VPR128.4S = TMPQ1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.5 ADDP (vector) page C7-2025 line 118351 MATCH x0e20bc00/mask=xbf20fc00 +# CONSTRUCT x0e20bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 var:8 ARG2 ARG3 =#+/2 = +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@1 +# AUNIT --inst x0e20bc00/mask=xffe0fc00 --status pass + +:addp Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x17 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + TMPD1 = 0; + # sipd infix TMPD1 = +(Rn_VPR64.8B,Rm_VPR64.8B) on pairs lane size (1 to 1) + local tmp2 = Rn_VPR64.8B[0,8]; + local tmp3 = Rn_VPR64.8B[8,8]; + TMPD1[0,8] = tmp2 + tmp3; + tmp2 = Rn_VPR64.8B[16,8]; + tmp3 = Rn_VPR64.8B[24,8]; + TMPD1[8,8] = tmp2 + tmp3; + tmp2 = Rn_VPR64.8B[32,8]; + tmp3 = Rn_VPR64.8B[40,8]; + TMPD1[16,8] = tmp2 + tmp3; + tmp2 = Rn_VPR64.8B[48,8]; + tmp3 = Rn_VPR64.8B[56,8]; + TMPD1[24,8] = tmp2 + tmp3; + tmp2 = Rm_VPR64.8B[0,8]; + tmp3 = Rm_VPR64.8B[8,8]; + TMPD1[32,8] = tmp2 + tmp3; + tmp2 = Rm_VPR64.8B[16,8]; + tmp3 = Rm_VPR64.8B[24,8]; + TMPD1[40,8] = tmp2 + tmp3; + tmp2 = Rm_VPR64.8B[32,8]; + tmp3 = Rm_VPR64.8B[40,8]; + TMPD1[48,8] = tmp2 + tmp3; + tmp2 = Rm_VPR64.8B[48,8]; + tmp3 = Rm_VPR64.8B[56,8]; + TMPD1[56,8] = tmp2 + tmp3; + Rd_VPR64.8B = TMPD1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.5 ADDP (vector) page C7-2025 line 118351 MATCH x0e20bc00/mask=xbf20fc00 +# CONSTRUCT x4e60bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 var:16 ARG2 ARG3 =#+/2 = +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@2 +# AUNIT --inst x4e60bc00/mask=xffe0fc00 --status pass + +:addp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x17 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + TMPQ1 = 0; + # sipd infix TMPQ1 = +(Rn_VPR128.8H,Rm_VPR128.8H) on pairs lane size (2 to 2) + local tmp2 = Rn_VPR128.8H[0,16]; + local tmp3 = Rn_VPR128.8H[16,16]; + TMPQ1[0,16] = tmp2 + tmp3; + tmp2 = Rn_VPR128.8H[32,16]; + tmp3 = Rn_VPR128.8H[48,16]; + TMPQ1[16,16] = tmp2 + tmp3; + tmp2 = Rn_VPR128.8H[64,16]; + tmp3 = Rn_VPR128.8H[80,16]; + TMPQ1[32,16] = tmp2 + tmp3; + tmp2 = Rn_VPR128.8H[96,16]; + tmp3 = Rn_VPR128.8H[112,16]; + TMPQ1[48,16] = tmp2 + tmp3; + tmp2 = Rm_VPR128.8H[0,16]; + tmp3 = Rm_VPR128.8H[16,16]; + TMPQ1[64,16] = tmp2 + tmp3; + tmp2 = Rm_VPR128.8H[32,16]; + tmp3 = Rm_VPR128.8H[48,16]; + TMPQ1[80,16] = tmp2 + tmp3; + tmp2 = Rm_VPR128.8H[64,16]; + tmp3 = Rm_VPR128.8H[80,16]; + TMPQ1[96,16] = tmp2 + tmp3; + tmp2 = Rm_VPR128.8H[96,16]; + tmp3 = Rm_VPR128.8H[112,16]; + TMPQ1[112,16] = tmp2 + tmp3; + Rd_VPR128.8H = TMPQ1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.6 ADDV page C7-2027 line 118452 MATCH x0e31b800/mask=xbf3ffc00 +# CONSTRUCT x4e31b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_addv/1@1 +# AUNIT --inst x4e31b800/mask=xfffffc00 --status nopcodeop + +:addv Rd_FPR8, Rn_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1b & b_1011=2 & Rn_VPR128.16B & Rd_FPR8 & Zd +{ + Rd_FPR8 = NEON_addv(Rn_VPR128.16B, 1:1); +} + +# C7.2.6 ADDV page C7-2027 line 118452 MATCH x0e31b800/mask=xbf3ffc00 +# CONSTRUCT x0e31b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_addv/1@1 +# AUNIT --inst x0e31b800/mask=xfffffc00 --status nopcodeop + +:addv Rd_FPR8, Rn_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1b & b_1011=2 & Rn_VPR64.8B & Rd_FPR8 & Zd +{ + Rd_FPR8 = NEON_addv(Rn_VPR64.8B, 1:1); +} + +# C7.2.6 ADDV page C7-2027 line 118452 MATCH x0e31b800/mask=xbf3ffc00 +# CONSTRUCT x0e71b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_addv/1@2 +# AUNIT --inst x0e71b800/mask=xfffffc00 --status nopcodeop + +:addv Rd_FPR16, Rn_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1b & b_1011=2 & Rn_VPR64.4H & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_addv(Rn_VPR64.4H, 2:1); +} + +# C7.2.6 ADDV page C7-2027 line 118452 MATCH x0e31b800/mask=xbf3ffc00 +# CONSTRUCT x4e71b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_addv/1@2 +# AUNIT --inst x4e71b800/mask=xfffffc00 --status nopcodeop + +:addv Rd_FPR16, Rn_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1b & b_1011=2 & Rn_VPR128.8H & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_addv(Rn_VPR128.8H, 2:1); +} + +# C7.2.6 ADDV page C7-2027 line 118452 MATCH x0e31b800/mask=xbf3ffc00 +# CONSTRUCT x4eb1b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(force-primitive) ARG1 ARG2[0]:4 ARG2[1]:4 + ARG2[2]:4 ARG2[3]:4 + =+ +# SMACRO(pseudo) ARG1 ARG2 =NEON_addv/1@4 +# AUNIT --inst x4eb1b800/mask=xfffffc00 --status pass + +:addv Rd_FPR32, Rn_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x1b & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd +{ + local tmp1:4 = Rn_VPR128.4S[0,32]; + local tmp2:4 = Rn_VPR128.4S[32,32]; + local tmp3:4 = tmp1 + tmp2; + local tmp4:4 = Rn_VPR128.4S[64,32]; + local tmp5:4 = Rn_VPR128.4S[96,32]; + local tmp6:4 = tmp4 + tmp5; + Rd_FPR32 = tmp3 + tmp6; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.7 AESD page C7-2029 line 118544 MATCH x4e285800/mask=xfffffc00 +# CONSTRUCT x4e285800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_aesd/2 +# AUNIT --inst x4e285800/mask=xfffffc00 --status noqemu + +:aesd Rd_VPR128.16B, Rn_VPR128.16B +is b_2431=0b01001110 & b_2223=0b00 & b_1721=0b10100 & b_1216=5 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_aesd(Rd_VPR128.16B, Rn_VPR128.16B); +} + +# C7.2.8 AESE page C7-2030 line 118606 MATCH x4e284800/mask=xfffffc00 +# CONSTRUCT x4e284800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_aese/2 +# AUNIT --inst x4e284800/mask=xfffffc00 --status noqemu + +:aese Rd_VPR128.16B, Rn_VPR128.16B +is b_2431=0b01001110 & b_2223=0b00 & b_1721=0b10100 & b_1216=4 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_aese(Rd_VPR128.16B, Rn_VPR128.16B); +} + +# C7.2.9 AESIMC page C7-2031 line 118669 MATCH x4e287800/mask=xfffffc00 +# CONSTRUCT x4e287800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_aesimc/2 +# AUNIT --inst x4e287800/mask=xfffffc00 --status noqemu + +:aesimc Rd_VPR128.16B, Rn_VPR128.16B +is b_2431=0b01001110 & b_2223=0b00 & b_1721=0b10100 & b_1216=7 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Rd_VPR128 & Zd +{ + Rd_VPR128.16B = NEON_aesimc(Rd_VPR128.16B, Rn_VPR128.16B); +} + +# C7.2.10 AESMC page C7-2032 line 118729 MATCH x4e286800/mask=xfffffc00 +# CONSTRUCT x4e286800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_aesmc/2 +# AUNIT --inst x4e286800/mask=xfffffc00 --status noqemu + +:aesmc Rd_VPR128.16B, Rn_VPR128.16B +is b_2431=0b01001110 & b_2223=0b00 & b_1721=0b10100 & b_1216=6 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Rd_VPR128 & Zd +{ + Rd_VPR128.16B = NEON_aesmc(Rd_VPR128.16B, Rn_VPR128.16B); +} + +# C7.2.11 AND (vector) page C7-2033 line 118789 MATCH x0e201c00/mask=xbfe0fc00 +# CONSTRUCT x4e201c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$&@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_and/2@1 +# AUNIT --inst x4e201c00/mask=xffe0fc00 --status pass + +:and Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + # simd infix Rd_VPR128.16B = Rn_VPR128.16B & Rm_VPR128.16B on lane size 1 + Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] & Rm_VPR128.16B[0,8]; + Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] & Rm_VPR128.16B[8,8]; + Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] & Rm_VPR128.16B[16,8]; + Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] & Rm_VPR128.16B[24,8]; + Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] & Rm_VPR128.16B[32,8]; + Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] & Rm_VPR128.16B[40,8]; + Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] & Rm_VPR128.16B[48,8]; + Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] & Rm_VPR128.16B[56,8]; + Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] & Rm_VPR128.16B[64,8]; + Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] & Rm_VPR128.16B[72,8]; + Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] & Rm_VPR128.16B[80,8]; + Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] & Rm_VPR128.16B[88,8]; + Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] & Rm_VPR128.16B[96,8]; + Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] & Rm_VPR128.16B[104,8]; + Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] & Rm_VPR128.16B[112,8]; + Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] & Rm_VPR128.16B[120,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.11 AND (vector) page C7-2033 line 118789 MATCH x0e201c00/mask=xbfe0fc00 +# CONSTRUCT x0e201c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =& +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_and/2@1 +# AUNIT --inst x0e201c00/mask=xffe0fc00 --status pass + +:and Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = Rn_VPR64.8B & Rm_VPR64.8B; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.12 BCAX page C7-2035 line 118871 MATCH xce200000/mask=xffe08000 +# CONSTRUCT xce200000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 ARG4 $~@1 $&@1 =$|@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG3 =NEON_bcax/3@1 +# AUNIT --inst xce200000/mask=xffe08000 --status noqemu + +:bcax Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, Ra_VPR128.16B +is b_2131=0b11001110001 & b_15=0 & Rd_VPR128.16B & Rn_VPR128.16B & Rm_VPR128.16B & Ra_VPR128.16B & Zd +{ + # simd unary TMPQ1 = ~(Ra_VPR128.16B) on lane size 1 + TMPQ1[0,8] = ~(Ra_VPR128.16B[0,8]); + TMPQ1[8,8] = ~(Ra_VPR128.16B[8,8]); + TMPQ1[16,8] = ~(Ra_VPR128.16B[16,8]); + TMPQ1[24,8] = ~(Ra_VPR128.16B[24,8]); + TMPQ1[32,8] = ~(Ra_VPR128.16B[32,8]); + TMPQ1[40,8] = ~(Ra_VPR128.16B[40,8]); + TMPQ1[48,8] = ~(Ra_VPR128.16B[48,8]); + TMPQ1[56,8] = ~(Ra_VPR128.16B[56,8]); + TMPQ1[64,8] = ~(Ra_VPR128.16B[64,8]); + TMPQ1[72,8] = ~(Ra_VPR128.16B[72,8]); + TMPQ1[80,8] = ~(Ra_VPR128.16B[80,8]); + TMPQ1[88,8] = ~(Ra_VPR128.16B[88,8]); + TMPQ1[96,8] = ~(Ra_VPR128.16B[96,8]); + TMPQ1[104,8] = ~(Ra_VPR128.16B[104,8]); + TMPQ1[112,8] = ~(Ra_VPR128.16B[112,8]); + TMPQ1[120,8] = ~(Ra_VPR128.16B[120,8]); + # simd infix TMPQ2 = Rm_VPR128.16B & TMPQ1 on lane size 1 + TMPQ2[0,8] = Rm_VPR128.16B[0,8] & TMPQ1[0,8]; + TMPQ2[8,8] = Rm_VPR128.16B[8,8] & TMPQ1[8,8]; + TMPQ2[16,8] = Rm_VPR128.16B[16,8] & TMPQ1[16,8]; + TMPQ2[24,8] = Rm_VPR128.16B[24,8] & TMPQ1[24,8]; + TMPQ2[32,8] = Rm_VPR128.16B[32,8] & TMPQ1[32,8]; + TMPQ2[40,8] = Rm_VPR128.16B[40,8] & TMPQ1[40,8]; + TMPQ2[48,8] = Rm_VPR128.16B[48,8] & TMPQ1[48,8]; + TMPQ2[56,8] = Rm_VPR128.16B[56,8] & TMPQ1[56,8]; + TMPQ2[64,8] = Rm_VPR128.16B[64,8] & TMPQ1[64,8]; + TMPQ2[72,8] = Rm_VPR128.16B[72,8] & TMPQ1[72,8]; + TMPQ2[80,8] = Rm_VPR128.16B[80,8] & TMPQ1[80,8]; + TMPQ2[88,8] = Rm_VPR128.16B[88,8] & TMPQ1[88,8]; + TMPQ2[96,8] = Rm_VPR128.16B[96,8] & TMPQ1[96,8]; + TMPQ2[104,8] = Rm_VPR128.16B[104,8] & TMPQ1[104,8]; + TMPQ2[112,8] = Rm_VPR128.16B[112,8] & TMPQ1[112,8]; + TMPQ2[120,8] = Rm_VPR128.16B[120,8] & TMPQ1[120,8]; + # simd infix Rd_VPR128.16B = Rn_VPR128.16B | TMPQ2 on lane size 1 + Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] | TMPQ2[0,8]; + Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] | TMPQ2[8,8]; + Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] | TMPQ2[16,8]; + Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] | TMPQ2[24,8]; + Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] | TMPQ2[32,8]; + Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] | TMPQ2[40,8]; + Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] | TMPQ2[48,8]; + Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] | TMPQ2[56,8]; + Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] | TMPQ2[64,8]; + Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] | TMPQ2[72,8]; + Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] | TMPQ2[80,8]; + Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] | TMPQ2[88,8]; + Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] | TMPQ2[96,8]; + Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] | TMPQ2[104,8]; + Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] | TMPQ2[112,8]; + Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] | TMPQ2[120,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.20 BIC (vector, immediate) page C7-2048 line 119572 MATCH x2f001400/mask=xbff81c00 +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00 +# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00 +# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00 +# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00 +# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00 +# CONSTRUCT x2f001400/mask=xfff89c00 MATCHED 7 DOCUMENTED OPCODES +# SMACRO ARG1 Imm_neon_uimm8Shift:4 ~ &=$& +# SMACRO(pseudo) ARG1 Imm_neon_uimm8Shift:4 &=NEON_bic/2@4 +# AUNIT --inst x2f001400/mask=xfff89c00 --status pass + +:bic Rd_VPR64.2S, abcdefgh +is b_3131=0 & q=0 & b_29=1 & b_2428=0xf & b_1923=0x0 & b_1515=0 & abcdefgh & Imm_neon_uimm8Shift & b_1012=5 & Rd_VPR64.2S & Zd +{ + local tmp1:4 = ~ Imm_neon_uimm8Shift:4; + # simd infix Rd_VPR64.2S = Rd_VPR64.2S & tmp1 on lane size 4 + Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] & tmp1; + Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] & tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.20 BIC (vector, immediate) page C7-2048 line 119572 MATCH x2f001400/mask=xbff81c00 +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00 +# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x2f009400/mask=xbf80fc00 +# CONSTRUCT x2f009400/mask=xfff8dc00 MATCHED 4 DOCUMENTED OPCODES +# SMACRO ARG1 Imm_neon_uimm8Shift:2 ~ &=$& +# SMACRO(pseudo) ARG1 Imm_neon_uimm8Shift:2 &=NEON_bic/2@2 +# AUNIT --inst x2f009400/mask=xfff8dc00 --status pass + +:bic Rd_VPR64.4H, abcdefgh +is b_3131=0 & q=0 & b_29=1 & b_2428=0xf & abcdefgh & b_1923=0x0 & b_1415=2 & Imm_neon_uimm8Shift & b_1012=5 & Rd_VPR64.4H & Zd +{ + local tmp1:2 = ~ Imm_neon_uimm8Shift:2; + # simd infix Rd_VPR64.4H = Rd_VPR64.4H & tmp1 on lane size 2 + Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] & tmp1; + Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] & tmp1; + Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] & tmp1; + Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] & tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.20 BIC (vector, immediate) page C7-2048 line 119572 MATCH x2f001400/mask=xbff81c00 +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00 +# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00 +# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00 +# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00 +# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00 +# CONSTRUCT x6f001400/mask=xfff89c00 MATCHED 7 DOCUMENTED OPCODES +# SMACRO ARG1 Imm_neon_uimm8Shift:4 ~ &=$& +# SMACRO(pseudo) ARG1 Imm_neon_uimm8Shift:4 &=NEON_bic/2@4 +# AUNIT --inst x6f001400/mask=xfff89c00 --status pass + +:bic Rd_VPR128.4S, abcdefgh +is b_3131=0 & q=1 & b_29=1 & b_2428=0xf & b_1923=0x0 & b_1515=0 & abcdefgh & Imm_neon_uimm8Shift & b_1012=5 & Rd_VPR128.4S & Zd +{ + local tmp1:4 = ~ Imm_neon_uimm8Shift:4; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S & tmp1 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] & tmp1; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] & tmp1; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] & tmp1; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] & tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.20 BIC (vector, immediate) page C7-2048 line 119572 MATCH x2f001400/mask=xbff81c00 +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00 +# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x2f009400/mask=xbf80fc00 +# CONSTRUCT x6f009400/mask=xfff8dc00 MATCHED 4 DOCUMENTED OPCODES +# SMACRO ARG1 Imm_neon_uimm8Shift:2 ~ &=$& +# SMACRO(pseudo) ARG1 Imm_neon_uimm8Shift:2 &=NEON_bic/2@2 +# AUNIT --inst x6f009400/mask=xfff8dc00 --status pass + +:bic Rd_VPR128.8H, abcdefgh +is b_3131=0 & q=1 & b_29=1 & b_2428=0xf & b_1923=0x0 & abcdefgh & b_1415=2 & Imm_neon_uimm8Shift & b_1012=5 & Rd_VPR128.8H & Zd +{ + local tmp1:2 = ~ Imm_neon_uimm8Shift:2; + # simd infix Rd_VPR128.8H = Rd_VPR128.8H & tmp1 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] & tmp1; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] & tmp1; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] & tmp1; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] & tmp1; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] & tmp1; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] & tmp1; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] & tmp1; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] & tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.21 BIC (vector, register) page C7-2050 line 119707 MATCH x0e601c00/mask=xbfe0fc00 +# CONSTRUCT x4e601c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $~@1 =$&@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_bic/2@1 +# AUNIT --inst x4e601c00/mask=xffe0fc00 --status pass + +:bic Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + # simd unary TMPQ1 = ~(Rm_VPR128.16B) on lane size 1 + TMPQ1[0,8] = ~(Rm_VPR128.16B[0,8]); + TMPQ1[8,8] = ~(Rm_VPR128.16B[8,8]); + TMPQ1[16,8] = ~(Rm_VPR128.16B[16,8]); + TMPQ1[24,8] = ~(Rm_VPR128.16B[24,8]); + TMPQ1[32,8] = ~(Rm_VPR128.16B[32,8]); + TMPQ1[40,8] = ~(Rm_VPR128.16B[40,8]); + TMPQ1[48,8] = ~(Rm_VPR128.16B[48,8]); + TMPQ1[56,8] = ~(Rm_VPR128.16B[56,8]); + TMPQ1[64,8] = ~(Rm_VPR128.16B[64,8]); + TMPQ1[72,8] = ~(Rm_VPR128.16B[72,8]); + TMPQ1[80,8] = ~(Rm_VPR128.16B[80,8]); + TMPQ1[88,8] = ~(Rm_VPR128.16B[88,8]); + TMPQ1[96,8] = ~(Rm_VPR128.16B[96,8]); + TMPQ1[104,8] = ~(Rm_VPR128.16B[104,8]); + TMPQ1[112,8] = ~(Rm_VPR128.16B[112,8]); + TMPQ1[120,8] = ~(Rm_VPR128.16B[120,8]); + # simd infix Rd_VPR128.16B = Rn_VPR128.16B & TMPQ1 on lane size 1 + Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] & TMPQ1[0,8]; + Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] & TMPQ1[8,8]; + Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] & TMPQ1[16,8]; + Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] & TMPQ1[24,8]; + Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] & TMPQ1[32,8]; + Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] & TMPQ1[40,8]; + Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] & TMPQ1[48,8]; + Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] & TMPQ1[56,8]; + Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] & TMPQ1[64,8]; + Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] & TMPQ1[72,8]; + Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] & TMPQ1[80,8]; + Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] & TMPQ1[88,8]; + Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] & TMPQ1[96,8]; + Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] & TMPQ1[104,8]; + Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] & TMPQ1[112,8]; + Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] & TMPQ1[120,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.21 BIC (vector, register) page C7-2050 line 119707 MATCH x0e601c00/mask=xbfe0fc00 +# CONSTRUCT x0e601c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $~@1 =$&@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_bic/2@1 +# AUNIT --inst x0e601c00/mask=xffe0fc00 --status pass + +:bic Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + # simd unary TMPD1 = ~(Rm_VPR64.8B) on lane size 1 + TMPD1[0,8] = ~(Rm_VPR64.8B[0,8]); + TMPD1[8,8] = ~(Rm_VPR64.8B[8,8]); + TMPD1[16,8] = ~(Rm_VPR64.8B[16,8]); + TMPD1[24,8] = ~(Rm_VPR64.8B[24,8]); + TMPD1[32,8] = ~(Rm_VPR64.8B[32,8]); + TMPD1[40,8] = ~(Rm_VPR64.8B[40,8]); + TMPD1[48,8] = ~(Rm_VPR64.8B[48,8]); + TMPD1[56,8] = ~(Rm_VPR64.8B[56,8]); + # simd infix Rd_VPR64.8B = Rn_VPR64.8B & TMPD1 on lane size 1 + Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] & TMPD1[0,8]; + Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] & TMPD1[8,8]; + Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] & TMPD1[16,8]; + Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] & TMPD1[24,8]; + Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] & TMPD1[32,8]; + Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] & TMPD1[40,8]; + Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] & TMPD1[48,8]; + Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] & TMPD1[56,8]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.22 BIF page C7-2052 line 119791 MATCH x2ee01c00/mask=xbfe0fc00 +# CONSTRUCT x6ee01c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_bif/3@1 +# AUNIT --inst x6ee01c00/mask=xffe0fc00 --status nopcodeop + +:bif Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_bif(Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.22 BIF page C7-2052 line 119791 MATCH x2ee01c00/mask=xbfe0fc00 +# CONSTRUCT x2ee01c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_bif/3@1 +# AUNIT --inst x2ee01c00/mask=xffe0fc00 --status nopcodeop + +:bif Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_bif(Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.23 BIT page C7-2054 line 119875 MATCH x2ea01c00/mask=xbfe0fc00 +# CONSTRUCT x6ea01c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_bit/3@1 +# AUNIT --inst x6ea01c00/mask=xffe0fc00 --status nopcodeop + +:bit Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_bit(Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.23 BIT page C7-2054 line 119875 MATCH x2ea01c00/mask=xbfe0fc00 +# CONSTRUCT x2ea01c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_bit/3@1 +# AUNIT --inst x2ea01c00/mask=xffe0fc00 --status nopcodeop + +:bit Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_bit(Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.24 BSL page C7-2056 line 119959 MATCH x2e601c00/mask=xbfe0fc00 +# CONSTRUCT x6e601c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_bsl/3@1 +# AUNIT --inst x6e601c00/mask=xffe0fc00 --status nopcodeop + +:bsl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_bsl(Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.24 BSL page C7-2056 line 119959 MATCH x2e601c00/mask=xbfe0fc00 +# CONSTRUCT x2e601c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_bsl/3@1 +# AUNIT --inst x2e601c00/mask=xffe0fc00 --status nopcodeop + +:bsl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_bsl(Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.25 CLS (vector) page C7-2058 line 120043 MATCH x0e204800/mask=xbf3ffc00 +# CONSTRUCT x0e204800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_cls/1@1 +# AUNIT --inst x0e204800/mask=xfffffc00 --status nopcodeop +# CLS (vector) SIMD 8B when size = 00 , Q = 0 + +:cls Rd_VPR64.8B, Rn_VPR64.8B +is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000010010 & Rd_VPR64.8B & Rn_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_cls(Rn_VPR64.8B, 1:1); +} + +# C7.2.25 CLS (vector) page C7-2058 line 120043 MATCH x0e204800/mask=xbf3ffc00 +# CONSTRUCT x4e204800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_cls/1@1 +# AUNIT --inst x4e204800/mask=xfffffc00 --status nopcodeop +# CLS (vector) SIMD 16B when size = 00 , Q = 1 + +:cls Rd_VPR128.16B, Rn_VPR128.16B +is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000010010 & Rd_VPR128.16B & Rn_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_cls(Rn_VPR128.16B, 1:1); +} + +# C7.2.25 CLS (vector) page C7-2058 line 120043 MATCH x0e204800/mask=xbf3ffc00 +# CONSTRUCT x0e604800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_cls/1@2 +# AUNIT --inst x0e604800/mask=xfffffc00 --status nopcodeop +# CLS (vector) SIMD 4H when size = 01 , Q = 0 + +:cls Rd_VPR64.4H, Rn_VPR64.4H +is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000010010 & Rd_VPR64.4H & Rn_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_cls(Rn_VPR64.4H, 2:1); +} + +# C7.2.25 CLS (vector) page C7-2058 line 120043 MATCH x0e204800/mask=xbf3ffc00 +# CONSTRUCT x4e604800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_cls/1@2 +# AUNIT --inst x4e604800/mask=xfffffc00 --status nopcodeop +# CLS (vector) SIMD 8H when size = 01 , Q = 1 + +:cls Rd_VPR128.8H, Rn_VPR128.8H +is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000010010 & Rd_VPR128.8H & Rn_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_cls(Rn_VPR128.8H, 2:1); +} + +# C7.2.25 CLS (vector) page C7-2058 line 120043 MATCH x0e204800/mask=xbf3ffc00 +# CONSTRUCT x0ea04800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_cls/1@4 +# AUNIT --inst x0ea04800/mask=xfffffc00 --status nopcodeop +# CLS (vector) SIMD 2S when size = 10 , Q = 0 + +:cls Rd_VPR64.2S, Rn_VPR64.2S +is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000010010 & Rd_VPR64.2S & Rn_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_cls(Rn_VPR64.2S, 4:1); +} + +# C7.2.25 CLS (vector) page C7-2058 line 120043 MATCH x0e204800/mask=xbf3ffc00 +# CONSTRUCT x4ea04800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_cls/1@4 +# AUNIT --inst x4ea04800/mask=xfffffc00 --status nopcodeop +# CLS (vector) SIMD 4S when size = 10 , Q = 1 + +:cls Rd_VPR128.4S, Rn_VPR128.4S +is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000010010 & Rd_VPR128.4S & Rn_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_cls(Rn_VPR128.4S, 4:1); +} + +# C7.2.26 CLZ (vector) page C7-2060 line 120140 MATCH x2e204800/mask=xbf3ffc00 +# CONSTRUCT x2e204800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_clz/1@1 +# AUNIT --inst x2e204800/mask=xfffffc00 --status nopcodeop +# CLZ (vector) SIMD 8B when size = 00 , Q = 0 + +:clz Rd_VPR64.8B, Rn_VPR64.8B +is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000010010 & Rd_VPR64.8B & Rn_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_clz(Rn_VPR64.8B, 1:1); +} + +# C7.2.26 CLZ (vector) page C7-2060 line 120140 MATCH x2e204800/mask=xbf3ffc00 +# CONSTRUCT x6e204800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_clz/1@1 +# AUNIT --inst x6e204800/mask=xfffffc00 --status nopcodeop +# CLZ (vector) SIMD 16B when size = 00 , Q = 1 + +:clz Rd_VPR128.16B, Rn_VPR128.16B +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000010010 & Rd_VPR128.16B & Rn_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_clz(Rn_VPR128.16B, 1:1); +} + +# C7.2.26 CLZ (vector) page C7-2060 line 120140 MATCH x2e204800/mask=xbf3ffc00 +# CONSTRUCT x2e604800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_clz/1@2 +# AUNIT --inst x2e604800/mask=xfffffc00 --status nopcodeop +# CLZ (vector) SIMD 4H when size = 01 , Q = 0 + +:clz Rd_VPR64.4H, Rn_VPR64.4H +is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000010010 & Rd_VPR64.4H & Rn_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_clz(Rn_VPR64.4H, 2:1); +} + +# C7.2.26 CLZ (vector) page C7-2060 line 120140 MATCH x2e204800/mask=xbf3ffc00 +# CONSTRUCT x6e604800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_clz/1@2 +# AUNIT --inst x6e604800/mask=xfffffc00 --status nopcodeop +# CLZ (vector) SIMD 8H when size = 01 , Q = 1 + +:clz Rd_VPR128.8H, Rn_VPR128.8H +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000010010 & Rd_VPR128.8H & Rn_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_clz(Rn_VPR128.8H, 2:1); +} + +# C7.2.26 CLZ (vector) page C7-2060 line 120140 MATCH x2e204800/mask=xbf3ffc00 +# CONSTRUCT x2ea04800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_clz/1@4 +# AUNIT --inst x2ea04800/mask=xfffffc00 --status nopcodeop +# CLZ (vector) SIMD 2S when size = 10 , Q = 0 + +:clz Rd_VPR64.2S, Rn_VPR64.2S +is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000010010 & Rd_VPR64.2S & Rn_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_clz(Rn_VPR64.2S, 4:1); +} + +# C7.2.26 CLZ (vector) page C7-2060 line 120140 MATCH x2e204800/mask=xbf3ffc00 +# CONSTRUCT x6ea04800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_clz/1@4 +# AUNIT --inst x6ea04800/mask=xfffffc00 --status nopcodeop +# CLZ (vector) SIMD 4S when size = 10 , Q = 1 + +:clz Rd_VPR128.4S, Rn_VPR128.4S +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000010010 & Rd_VPR128.4S & Rn_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_clz(Rn_VPR128.4S, 4:1); +} + +# C7.2.27 CMEQ (register) page C7-2062 line 120236 MATCH x7e208c00/mask=xff20fc00 +# CONSTRUCT x7ee08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 dup dup dup ARG2 ARG3 equal:1 zext:8 0:8 ~ =* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2 +# AUNIT --inst x7ee08c00/mask=xffe0fc00 --status pass +# CMEQ (register) Scalar + +:cmeq Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_2431=0b01111110 & b_2223=0b11 & b_21=1 & b_1015=0b100011 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd +{ + local tmp1:1 = Rn_FPR64 == Rm_FPR64; + local tmp2:8 = zext(tmp1); + local tmp3:8 = ~ 0:8; + Rd_FPR64 = tmp2 * tmp3; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.27 CMEQ (register) page C7-2062 line 120236 MATCH x2e208c00/mask=xbf20fc00 +# CONSTRUCT x2e208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@1 +# AUNIT --inst x2e208c00/mask=xffe0fc00 --status nopcodeop +# CMEQ (register) SIMD 8B when size = 00 , Q = 0 + +:cmeq Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b00 & b_21=1 & b_1015=0b100011 & Rd_VPR64.8B & Rn_VPR64.8B & Rm_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_cmeq(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.27 CMEQ (register) page C7-2062 line 120236 MATCH x2e208c00/mask=xbf20fc00 +# CONSTRUCT x6e208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@1 +# AUNIT --inst x6e208c00/mask=xffe0fc00 --status nopcodeop +# CMEQ (register) SIMD 16B when size = 00 , Q = 1 + +:cmeq Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b00 & b_21=1 & b_1015=0b100011 & Rd_VPR128.16B & Rn_VPR128.16B & Rm_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_cmeq(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.27 CMEQ (register) page C7-2062 line 120236 MATCH x2e208c00/mask=xbf20fc00 +# CONSTRUCT x2e608c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@2 +# AUNIT --inst x2e608c00/mask=xffe0fc00 --status nopcodeop +# CMEQ (register) SIMD 4H when size = 01 , Q = 0 + +:cmeq Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_21=1 & b_1015=0b100011 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_cmeq(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.27 CMEQ (register) page C7-2062 line 120236 MATCH x2e208c00/mask=xbf20fc00 +# CONSTRUCT x6e608c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@2 +# AUNIT --inst x6e608c00/mask=xffe0fc00 --status nopcodeop +# CMEQ (register) SIMD 8H when size = 01 , Q = 1 + +:cmeq Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_21=1 & b_1015=0b100011 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_cmeq(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.27 CMEQ (register) page C7-2062 line 120236 MATCH x2e208c00/mask=xbf20fc00 +# CONSTRUCT x2ea08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@4 +# AUNIT --inst x2ea08c00/mask=xffe0fc00 --status nopcodeop +# CMEQ (register) SIMD 2S when size = 10 , Q = 0 + +:cmeq Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_21=1 & b_1015=0b100011 & Rd_VPR64.2S & Rn_VPR64.2S & Rm_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_cmeq(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.27 CMEQ (register) page C7-2062 line 120236 MATCH x2e208c00/mask=xbf20fc00 +# CONSTRUCT x6ea08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@4 +# AUNIT --inst x6ea08c00/mask=xffe0fc00 --status nopcodeop +# CMEQ (register) SIMD 4S when size = 10 , Q = 1 + +:cmeq Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_21=1 & b_1015=0b100011 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_cmeq(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.27 CMEQ (register) page C7-2062 line 120236 MATCH x2e208c00/mask=xbf20fc00 +# CONSTRUCT x6ee08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@8 +# AUNIT --inst x6ee08c00/mask=xffe0fc00 --status nopcodeop +# CMEQ (register) SIMD 2D when size = 11 , Q = 1 + +:cmeq Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b11 & b_21=1 & b_1015=0b100011 & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_cmeq(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.28 CMEQ (zero) page C7-2064 line 120376 MATCH x0e209800/mask=xbf3ffc00 +# CONSTRUCT x4e209800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmeq/2@1 +# AUNIT --inst x4e209800/mask=xfffffc00 --status nopcodeop + +:cmeq Rd_VPR128.16B, Rn_VPR128.16B, "#0" +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_cmeq(Rn_VPR128.16B, 0:1, 1:1); +} + +# C7.2.28 CMEQ (zero) page C7-2064 line 120376 MATCH x0e209800/mask=xbf3ffc00 +# CONSTRUCT x4ee09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmeq/2@8 +# AUNIT --inst x4ee09800/mask=xfffffc00 --status nopcodeop + +:cmeq Rd_VPR128.2D, Rn_VPR128.2D, "#0" +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_cmeq(Rn_VPR128.2D, 0:8, 8:1); +} + +# C7.2.28 CMEQ (zero) page C7-2064 line 120376 MATCH x0e209800/mask=xbf3ffc00 +# CONSTRUCT x0ea09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmeq/2@4 +# AUNIT --inst x0ea09800/mask=xfffffc00 --status nopcodeop + +:cmeq Rd_VPR64.2S, Rn_VPR64.2S, "#0" +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_cmeq(Rn_VPR64.2S, 0:4, 4:1); +} + +# C7.2.28 CMEQ (zero) page C7-2064 line 120376 MATCH x0e209800/mask=xbf3ffc00 +# CONSTRUCT x0e609800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmeq/2@2 +# AUNIT --inst x0e609800/mask=xfffffc00 --status nopcodeop + +:cmeq Rd_VPR64.4H, Rn_VPR64.4H, "#0" +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_cmeq(Rn_VPR64.4H, 0:2, 2:1); +} + +# C7.2.28 CMEQ (zero) page C7-2064 line 120376 MATCH x0e209800/mask=xbf3ffc00 +# CONSTRUCT x4ea09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmeq/2@2 +# AUNIT --inst x4ea09800/mask=xfffffc00 --status nopcodeop + +:cmeq Rd_VPR128.4S, Rn_VPR128.4S, "#0" +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_cmeq(Rn_VPR128.4S, 0:4, 2:1); +} + +# C7.2.28 CMEQ (zero) page C7-2064 line 120376 MATCH x0e209800/mask=xbf3ffc00 +# CONSTRUCT x0e209800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmeq/2@1 +# AUNIT --inst x0e209800/mask=xfffffc00 --status nopcodeop + +:cmeq Rd_VPR64.8B, Rn_VPR64.8B, "#0" +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_cmeq(Rn_VPR64.8B, 0:1, 1:1); +} + +# C7.2.28 CMEQ (zero) page C7-2064 line 120376 MATCH x0e209800/mask=xbf3ffc00 +# CONSTRUCT x4e609800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmeq/2@2 +# AUNIT --inst x4e609800/mask=xfffffc00 --status nopcodeop + +:cmeq Rd_VPR128.8H, Rn_VPR128.8H, "#0" +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_cmeq(Rn_VPR128.8H, 0:2, 2:1); +} + +# C7.2.28 CMEQ (zero) page C7-2064 line 120376 MATCH x5e209800/mask=xff3ffc00 +# CONSTRUCT x5ee09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmeq/2 +# AUNIT --inst x5ee09800/mask=xfffffc00 --status nopcodeop + +:cmeq Rd_FPR64, Rn_FPR64, "#0" +is b_2431=0b01011110 & b_2223=0b11 & b_1021=0b100000100110 & Rd_FPR64 & Rn_FPR64 & Zd +{ + Rd_FPR64 = NEON_cmeq(Rn_FPR64, 0:4); +} + +# C7.2.29 CMGE (register) page C7-2067 line 120534 MATCH x0e203c00/mask=xbf20fc00 +# CONSTRUCT x4e203c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@1 +# AUNIT --inst x4e203c00/mask=xffe0fc00 --status nopcodeop + +:cmge Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x7 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_cmge(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.29 CMGE (register) page C7-2067 line 120534 MATCH x0e203c00/mask=xbf20fc00 +# CONSTRUCT x4ee03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@8 +# AUNIT --inst x4ee03c00/mask=xffe0fc00 --status nopcodeop + +:cmge Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x7 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_cmge(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.29 CMGE (register) page C7-2067 line 120534 MATCH x0e203c00/mask=xbf20fc00 +# CONSTRUCT x0ea03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@4 +# AUNIT --inst x0ea03c00/mask=xffe0fc00 --status nopcodeop + +:cmge Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x7 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_cmge(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.29 CMGE (register) page C7-2067 line 120534 MATCH x0e203c00/mask=xbf20fc00 +# CONSTRUCT x0e603c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@2 +# AUNIT --inst x0e603c00/mask=xffe0fc00 --status nopcodeop + +:cmge Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x7 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_cmge(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.29 CMGE (register) page C7-2067 line 120534 MATCH x0e203c00/mask=xbf20fc00 +# CONSTRUCT x4ea03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@4 +# AUNIT --inst x4ea03c00/mask=xffe0fc00 --status nopcodeop + +:cmge Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x7 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_cmge(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.29 CMGE (register) page C7-2067 line 120534 MATCH x0e203c00/mask=xbf20fc00 +# CONSTRUCT x0e203c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@1 +# AUNIT --inst x0e203c00/mask=xffe0fc00 --status nopcodeop + +:cmge Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x7 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_cmge(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.29 CMGE (register) page C7-2067 line 120534 MATCH x0e203c00/mask=xbf20fc00 +# CONSTRUCT x4e603c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@2 +# AUNIT --inst x4e603c00/mask=xffe0fc00 --status nopcodeop + +:cmge Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x7 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_cmge(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.29 CMGE (register) page C7-2067 line 120534 MATCH x5e203c00/mask=xff20fc00 +# CONSTRUCT x5ee03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2 +# AUNIT --inst x5ee03c00/mask=xffe0fc00 --status nopcodeop + +:cmge Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_2431=0b01011110 & b_2223=0b11 & b_21=1 & b_1015=0b001111 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd +{ + Rd_FPR64 = NEON_cmge(Rn_FPR64, Rm_FPR64); +} + +# C7.2.30 CMGE (zero) page C7-2070 line 120683 MATCH x2e208800/mask=xbf3ffc00 +# CONSTRUCT x6e208800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmge/2@1 +# AUNIT --inst x6e208800/mask=xfffffc00 --status nopcodeop + +:cmge Rd_VPR128.16B, Rn_VPR128.16B, "#0" +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_cmge(Rn_VPR128.16B, 0:1, 1:1); +} + +# C7.2.30 CMGE (zero) page C7-2070 line 120683 MATCH x2e208800/mask=xbf3ffc00 +# CONSTRUCT x6ee08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmge/2@8 +# AUNIT --inst x6ee08800/mask=xfffffc00 --status nopcodeop + +:cmge Rd_VPR128.2D, Rn_VPR128.2D, "#0" +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_cmge(Rn_VPR128.2D, 0:8, 8:1); +} + +# C7.2.30 CMGE (zero) page C7-2070 line 120683 MATCH x2e208800/mask=xbf3ffc00 +# CONSTRUCT x2ea08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmge/2@4 +# AUNIT --inst x2ea08800/mask=xfffffc00 --status nopcodeop + +:cmge Rd_VPR64.2S, Rn_VPR64.2S, "#0" +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_cmge(Rn_VPR64.2S, 0:4, 4:1); +} + +# C7.2.30 CMGE (zero) page C7-2070 line 120683 MATCH x2e208800/mask=xbf3ffc00 +# CONSTRUCT x2e608800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmge/2@2 +# AUNIT --inst x2e608800/mask=xfffffc00 --status nopcodeop + +:cmge Rd_VPR64.4H, Rn_VPR64.4H, "#0" +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_cmge(Rn_VPR64.4H, 0:2, 2:1); +} + +# C7.2.30 CMGE (zero) page C7-2070 line 120683 MATCH x2e208800/mask=xbf3ffc00 +# CONSTRUCT x6ea08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmge/2@4 +# AUNIT --inst x6ea08800/mask=xfffffc00 --status nopcodeop + +:cmge Rd_VPR128.4S, Rn_VPR128.4S, "#0" +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_cmge(Rn_VPR128.4S, 0:4, 4:1); +} + +# C7.2.30 CMGE (zero) page C7-2070 line 120683 MATCH x2e208800/mask=xbf3ffc00 +# CONSTRUCT x2e208800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmge/2@1 +# AUNIT --inst x2e208800/mask=xfffffc00 --status nopcodeop + +:cmge Rd_VPR64.8B, Rn_VPR64.8B, "#0" +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_cmge(Rn_VPR64.8B, 0:1, 1:1); +} + +# C7.2.30 CMGE (zero) page C7-2070 line 120683 MATCH x2e208800/mask=xbf3ffc00 +# CONSTRUCT x6e608800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmge/2@2 +# AUNIT --inst x6e608800/mask=xfffffc00 --status nopcodeop + +:cmge Rd_VPR128.8H, Rn_VPR128.8H, "#0" +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_cmge(Rn_VPR128.8H, 0:2, 2:1); +} + +# C7.2.30 CMGE (zero) page C7-2070 line 120683 MATCH x7e208800/mask=xff3ffc00 +# CONSTRUCT x7ee08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmge/2 +# AUNIT --inst x7ee08800/mask=xfffffc00 --status nopcodeop + +:cmge Rd_FPR64, Rn_FPR64, "#0" +is b_2431=0b01111110 & b_2223=0b11 & b_1021=0b100000100010 & Rd_FPR64 & Rn_FPR64 & Zd +{ + Rd_FPR64 = NEON_cmge(Rn_FPR64, 0:4); +} + +# C7.2.31 CMGT (register) page C7-2073 line 120841 MATCH x0e203400/mask=xbf20fc00 +# CONSTRUCT x4e203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@1 +# AUNIT --inst x4e203400/mask=xffe0fc00 --status nopcodeop + +:cmgt Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x6 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_cmgt(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.31 CMGT (register) page C7-2073 line 120841 MATCH x0e203400/mask=xbf20fc00 +# CONSTRUCT x4ee03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@8 +# AUNIT --inst x4ee03400/mask=xffe0fc00 --status nopcodeop + +:cmgt Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x6 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_cmgt(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.31 CMGT (register) page C7-2073 line 120841 MATCH x0e203400/mask=xbf20fc00 +# CONSTRUCT x0ea03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@4 +# AUNIT --inst x0ea03400/mask=xffe0fc00 --status nopcodeop + +:cmgt Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x6 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_cmgt(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.31 CMGT (register) page C7-2073 line 120841 MATCH x0e203400/mask=xbf20fc00 +# CONSTRUCT x0e603400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@2 +# AUNIT --inst x0e603400/mask=xffe0fc00 --status nopcodeop + +:cmgt Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x6 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_cmgt(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.31 CMGT (register) page C7-2073 line 120841 MATCH x0e203400/mask=xbf20fc00 +# CONSTRUCT x4ea03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@4 +# AUNIT --inst x4ea03400/mask=xffe0fc00 --status nopcodeop + +:cmgt Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x6 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_cmgt(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.31 CMGT (register) page C7-2073 line 120841 MATCH x0e203400/mask=xbf20fc00 +# CONSTRUCT x0e203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@1 +# AUNIT --inst x0e203400/mask=xffe0fc00 --status nopcodeop + +:cmgt Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x6 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_cmgt(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.31 CMGT (register) page C7-2073 line 120841 MATCH x0e203400/mask=xbf20fc00 +# CONSTRUCT x4e603400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@2 +# AUNIT --inst x4e603400/mask=xffe0fc00 --status nopcodeop + +:cmgt Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x6 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_cmgt(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.31 CMGT (register) page C7-2073 line 120841 MATCH x5e203400/mask=xff20fc00 +# CONSTRUCT x5ee03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2 +# AUNIT --inst x5ee03400/mask=xffe0fc00 --status nopcodeop + +:cmgt Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_2431=0b01011110 & b_2223=0b11 & b_21=1 & b_1015=0b001101 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd +{ + Rd_FPR64 = NEON_cmgt(Rn_FPR64, Rm_FPR64); +} + +# C7.2.32 CMGT (zero) page C7-2076 line 120990 MATCH x0e208800/mask=xbf3ffc00 +# CONSTRUCT x4e208800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmgt/2@1 +# AUNIT --inst x4e208800/mask=xfffffc00 --status nopcodeop + +:cmgt Rd_VPR128.16B, Rn_VPR128.16B, "#0" +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_cmgt(Rn_VPR128.16B, 0:1, 1:1); +} + +# C7.2.32 CMGT (zero) page C7-2076 line 120990 MATCH x0e208800/mask=xbf3ffc00 +# CONSTRUCT x4ee08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmgt/2@8 +# AUNIT --inst x4ee08800/mask=xfffffc00 --status nopcodeop + +:cmgt Rd_VPR128.2D, Rn_VPR128.2D, "#0" +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_cmgt(Rn_VPR128.2D, 0:8, 8:1); +} + +# C7.2.32 CMGT (zero) page C7-2076 line 120990 MATCH x0e208800/mask=xbf3ffc00 +# CONSTRUCT x0ea08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmgt/2@4 +# AUNIT --inst x0ea08800/mask=xfffffc00 --status nopcodeop + +:cmgt Rd_VPR64.2S, Rn_VPR64.2S, "#0" +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_cmgt(Rn_VPR64.2S, 0:4, 4:1); +} + +# C7.2.32 CMGT (zero) page C7-2076 line 120990 MATCH x0e208800/mask=xbf3ffc00 +# CONSTRUCT x0e608800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmgt/2@2 +# AUNIT --inst x0e608800/mask=xfffffc00 --status nopcodeop + +:cmgt Rd_VPR64.4H, Rn_VPR64.4H, "#0" +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_cmgt(Rn_VPR64.4H, 0:2, 2:1); +} + +# C7.2.32 CMGT (zero) page C7-2076 line 120990 MATCH x0e208800/mask=xbf3ffc00 +# CONSTRUCT x4ea08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmgt/2@4 +# AUNIT --inst x4ea08800/mask=xfffffc00 --status nopcodeop + +:cmgt Rd_VPR128.4S, Rn_VPR128.4S, "#0" +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_cmgt(Rn_VPR128.4S, 0:4, 4:1); +} + +# C7.2.32 CMGT (zero) page C7-2076 line 120990 MATCH x0e208800/mask=xbf3ffc00 +# CONSTRUCT x0e208800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmgt/2@1 +# AUNIT --inst x0e208800/mask=xfffffc00 --status nopcodeop + +:cmgt Rd_VPR64.8B, Rn_VPR64.8B, "#0" +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_cmgt(Rn_VPR64.8B, 0:1, 1:1); +} + +# C7.2.32 CMGT (zero) page C7-2076 line 120990 MATCH x0e208800/mask=xbf3ffc00 +# CONSTRUCT x4e608800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmgt/2@2 +# AUNIT --inst x4e608800/mask=xfffffc00 --status nopcodeop + +:cmgt Rd_VPR128.8H, Rn_VPR128.8H, "#0" +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_cmgt(Rn_VPR128.8H, 0:2, 2:1); +} + +# C7.2.32 CMGT (zero) page C7-2076 line 120990 MATCH x5e208800/mask=xff3ffc00 +# CONSTRUCT x5ee08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmgt/2 +# AUNIT --inst x5ee08800/mask=xfffffc00 --status nopcodeop + +:cmgt Rd_FPR64, Rn_FPR64, "#0" +is b_2431=0b01011110 & b_2223=0b11 & b_1021=0b100000100010 & Rd_FPR64 & Rn_FPR64 & Zd +{ + Rd_FPR64 = NEON_cmgt(Rn_FPR64, 0:8); +} + +# C7.2.33 CMHI (register) page C7-2079 line 121148 MATCH x2e203400/mask=xbf20fc00 +# CONSTRUCT x6e203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@1 +# AUNIT --inst x6e203400/mask=xffe0fc00 --status nopcodeop + +:cmhi Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x6 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_cmhi(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.33 CMHI (register) page C7-2079 line 121148 MATCH x2e203400/mask=xbf20fc00 +# CONSTRUCT x6ee03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@8 +# AUNIT --inst x6ee03400/mask=xffe0fc00 --status nopcodeop + +:cmhi Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x6 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_cmhi(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.33 CMHI (register) page C7-2079 line 121148 MATCH x2e203400/mask=xbf20fc00 +# CONSTRUCT x2ea03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@4 +# AUNIT --inst x2ea03400/mask=xffe0fc00 --status nopcodeop + +:cmhi Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x6 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_cmhi(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.33 CMHI (register) page C7-2079 line 121148 MATCH x2e203400/mask=xbf20fc00 +# CONSTRUCT x2e603400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@2 +# AUNIT --inst x2e603400/mask=xffe0fc00 --status nopcodeop + +:cmhi Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x6 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_cmhi(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.33 CMHI (register) page C7-2079 line 121148 MATCH x2e203400/mask=xbf20fc00 +# CONSTRUCT x6ea03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@4 +# AUNIT --inst x6ea03400/mask=xffe0fc00 --status nopcodeop + +:cmhi Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x6 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_cmhi(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.33 CMHI (register) page C7-2079 line 121148 MATCH x2e203400/mask=xbf20fc00 +# CONSTRUCT x2e203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@1 +# AUNIT --inst x2e203400/mask=xffe0fc00 --status nopcodeop + +:cmhi Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x6 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_cmhi(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.33 CMHI (register) page C7-2079 line 121148 MATCH x2e203400/mask=xbf20fc00 +# CONSTRUCT x6e603400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@2 +# AUNIT --inst x6e603400/mask=xffe0fc00 --status nopcodeop + +:cmhi Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x6 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_cmhi(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.33 CMHI (register) page C7-2079 line 121148 MATCH x7e203400/mask=xff20fc00 +# CONSTRUCT x7ee03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2 +# AUNIT --inst x7ee03400/mask=xffe0fc00 --status nopcodeop + +:cmhi Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_2431=0b01111110 & b_2223=0b11 & b_21=1 & b_1015=0b001101 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd +{ + Rd_FPR64 = NEON_cmhi(Rn_FPR64, Rm_FPR64); +} + +# C7.2.34 CMHS (register) page C7-2082 line 121297 MATCH x2e203c00/mask=xbf20fc00 +# CONSTRUCT x6e203c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@1 +# AUNIT --inst x6e203c00/mask=xffe0fc00 --status nopcodeop + +:cmhs Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x7 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_cmhs(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.34 CMHS (register) page C7-2082 line 121297 MATCH x2e203c00/mask=xbf20fc00 +# CONSTRUCT x6ee03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@8 +# AUNIT --inst x6ee03c00/mask=xffe0fc00 --status nopcodeop + +:cmhs Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x7 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_cmhs(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.34 CMHS (register) page C7-2082 line 121297 MATCH x2e203c00/mask=xbf20fc00 +# CONSTRUCT x2ea03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@4 +# AUNIT --inst x2ea03c00/mask=xffe0fc00 --status nopcodeop + +:cmhs Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x7 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_cmhs(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.34 CMHS (register) page C7-2082 line 121297 MATCH x2e203c00/mask=xbf20fc00 +# CONSTRUCT x2e603c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@2 +# AUNIT --inst x2e603c00/mask=xffe0fc00 --status nopcodeop + +:cmhs Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x7 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_cmhs(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.34 CMHS (register) page C7-2082 line 121297 MATCH x2e203c00/mask=xbf20fc00 +# CONSTRUCT x6ea03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@4 +# AUNIT --inst x6ea03c00/mask=xffe0fc00 --status nopcodeop + +:cmhs Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x7 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_cmhs(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.34 CMHS (register) page C7-2082 line 121297 MATCH x2e203c00/mask=xbf20fc00 +# CONSTRUCT x2e203c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@1 +# AUNIT --inst x2e203c00/mask=xffe0fc00 --status nopcodeop + +:cmhs Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x7 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_cmhs(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.34 CMHS (register) page C7-2082 line 121297 MATCH x2e203c00/mask=xbf20fc00 +# CONSTRUCT x6e603c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@2 +# AUNIT --inst x6e603c00/mask=xffe0fc00 --status nopcodeop + +:cmhs Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x7 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_cmhs(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.34 CMHS (register) page C7-2082 line 121297 MATCH x7e203c00/mask=xff20fc00 +# CONSTRUCT x7ee03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2 +# AUNIT --inst x7ee03c00/mask=xffe0fc00 --status nopcodeop + +:cmhs Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_2431=0b01111110 & b_2223=0b11 & b_21=1 & b_1015=0b001111 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd +{ + Rd_FPR64 = NEON_cmhs(Rn_FPR64, Rm_FPR64); +} + +# C7.2.35 CMLE (zero) page C7-2085 line 121446 MATCH x2e209800/mask=xbf3ffc00 +# CONSTRUCT x6e209800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmle/2@1 +# AUNIT --inst x6e209800/mask=xfffffc00 --status nopcodeop + +:cmle Rd_VPR128.16B, Rn_VPR128.16B, "#0" +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_cmle(Rn_VPR128.16B, 0:1, 1:1); +} + +# C7.2.35 CMLE (zero) page C7-2085 line 121446 MATCH x2e209800/mask=xbf3ffc00 +# CONSTRUCT x6ee09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmle/2@8 +# AUNIT --inst x6ee09800/mask=xfffffc00 --status nopcodeop + +:cmle Rd_VPR128.2D, Rn_VPR128.2D, "#0" +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_cmle(Rn_VPR128.2D, 0:8, 8:1); +} + +# C7.2.35 CMLE (zero) page C7-2085 line 121446 MATCH x2e209800/mask=xbf3ffc00 +# CONSTRUCT x2ea09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmle/2@4 +# AUNIT --inst x2ea09800/mask=xfffffc00 --status nopcodeop + +:cmle Rd_VPR64.2S, Rn_VPR64.2S, "#0" +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_cmle(Rn_VPR64.2S, 0:4, 4:1); +} + +# C7.2.35 CMLE (zero) page C7-2085 line 121446 MATCH x2e209800/mask=xbf3ffc00 +# CONSTRUCT x2e609800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmle/2@2 +# AUNIT --inst x2e609800/mask=xfffffc00 --status nopcodeop + +:cmle Rd_VPR64.4H, Rn_VPR64.4H, "#0" +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_cmle(Rn_VPR64.4H, 0:2, 2:1); +} + +# C7.2.35 CMLE (zero) page C7-2085 line 121446 MATCH x2e209800/mask=xbf3ffc00 +# CONSTRUCT x6ea09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmle/2@4 +# AUNIT --inst x6ea09800/mask=xfffffc00 --status nopcodeop + +:cmle Rd_VPR128.4S, Rn_VPR128.4S, "#0" +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_cmle(Rn_VPR128.4S, 0:4, 4:1); +} + +# C7.2.35 CMLE (zero) page C7-2085 line 121446 MATCH x2e209800/mask=xbf3ffc00 +# CONSTRUCT x2e209800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmle/2@1 +# AUNIT --inst x2e209800/mask=xfffffc00 --status nopcodeop + +:cmle Rd_VPR64.8B, Rn_VPR64.8B, "#0" +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_cmle(Rn_VPR64.8B, 0:1, 1:1); +} + +# C7.2.35 CMLE (zero) page C7-2085 line 121446 MATCH x2e209800/mask=xbf3ffc00 +# CONSTRUCT x6e609800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmle/2@2 +# AUNIT --inst x6e609800/mask=xfffffc00 --status nopcodeop + +:cmle Rd_VPR128.8H, Rn_VPR128.8H, "#0" +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_cmle(Rn_VPR128.8H, 0:2, 2:1); +} + +# C7.2.35 CMLE (zero) page C7-2085 line 121446 MATCH x7e209800/mask=xff3ffc00 +# CONSTRUCT x7ee09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmle/2 +# AUNIT --inst x7ee09800/mask=xfffffc00 --status nopcodeop + +:cmle Rd_FPR64, Rn_FPR64, "#0" +is b_2431=0b01111110 & b_2223=0b11 & b_1021=0b100000100110 & Rd_FPR64 & Rn_FPR64 & Zd +{ + Rd_FPR64 = NEON_cmle(Rn_FPR64, 0:8); +} + +# C7.2.36 CMLT (zero) page C7-2088 line 121604 MATCH x0e20a800/mask=xbf3ffc00 +# CONSTRUCT x4e20a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmlt/2@1 +# AUNIT --inst x4e20a800/mask=xfffffc00 --status nopcodeop + +:cmlt Rd_VPR128.16B, Rn_VPR128.16B, "#0" +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_cmlt(Rn_VPR128.16B, 0:1, 1:1); +} + +# C7.2.36 CMLT (zero) page C7-2088 line 121604 MATCH x0e20a800/mask=xbf3ffc00 +# CONSTRUCT x4ee0a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmlt/2@8 +# AUNIT --inst x4ee0a800/mask=xfffffc00 --status nopcodeop + +:cmlt Rd_VPR128.2D, Rn_VPR128.2D, "#0" +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_cmlt(Rn_VPR128.2D, 0:8, 8:1); +} + +# C7.2.36 CMLT (zero) page C7-2088 line 121604 MATCH x0e20a800/mask=xbf3ffc00 +# CONSTRUCT x0ea0a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmlt/2@4 +# AUNIT --inst x0ea0a800/mask=xfffffc00 --status nopcodeop + +:cmlt Rd_VPR64.2S, Rn_VPR64.2S, "#0" +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_cmlt(Rn_VPR64.2S, 0:4, 4:1); +} + +# C7.2.36 CMLT (zero) page C7-2088 line 121604 MATCH x0e20a800/mask=xbf3ffc00 +# CONSTRUCT x0e60a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmlt/2@2 +# AUNIT --inst x0e60a800/mask=xfffffc00 --status nopcodeop + +:cmlt Rd_VPR64.4H, Rn_VPR64.4H, "#0" +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_cmlt(Rn_VPR64.4H, 0:2, 2:1); +} + +# C7.2.36 CMLT (zero) page C7-2088 line 121604 MATCH x0e20a800/mask=xbf3ffc00 +# CONSTRUCT x4ea0a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmlt/2@4 +# AUNIT --inst x4ea0a800/mask=xfffffc00 --status nopcodeop + +:cmlt Rd_VPR128.4S, Rn_VPR128.4S, "#0" +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_cmlt(Rn_VPR128.4S, 0:4, 4:1); +} + +# C7.2.36 CMLT (zero) page C7-2088 line 121604 MATCH x0e20a800/mask=xbf3ffc00 +# CONSTRUCT x0e20a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmlt/2@1 +# AUNIT --inst x0e20a800/mask=xfffffc00 --status nopcodeop + +:cmlt Rd_VPR64.8B, Rn_VPR64.8B, "#0" +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_cmlt(Rn_VPR64.8B, 0:1, 1:1); +} + +# C7.2.36 CMLT (zero) page C7-2088 line 121604 MATCH x0e20a800/mask=xbf3ffc00 +# CONSTRUCT x4e60a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmlt/2@2 +# AUNIT --inst x4e60a800/mask=xfffffc00 --status nopcodeop + +:cmlt Rd_VPR128.8H, Rn_VPR128.8H, "#0" +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_cmlt(Rn_VPR128.8H, 0:2, 2:1); +} + +# C7.2.36 CMLT (zero) page C7-2088 line 121604 MATCH x5e20a800/mask=xff3ffc00 +# CONSTRUCT x5ee0a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmlt/2 +# AUNIT --inst x5ee0a800/mask=xfffffc00 --status nopcodeop + +:cmlt Rd_FPR64, Rn_FPR64, "#0" +is b_2431=0b01011110 & b_2223=0b11 & b_1021=0b100000101010 & Rd_FPR64 & Rn_FPR64 & Zd +{ + Rd_FPR64 = NEON_cmlt(Rn_FPR64, 0:8); +} + +# C7.2.37 CMTST page C7-2090 line 121743 MATCH x0e208c00/mask=xbf20fc00 +# CONSTRUCT x4e208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@1 +# AUNIT --inst x4e208c00/mask=xffe0fc00 --status nopcodeop + +:cmtst Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x11 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_cmtst(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.37 CMTST page C7-2090 line 121743 MATCH x0e208c00/mask=xbf20fc00 +# CONSTRUCT x4ee08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@8 +# AUNIT --inst x4ee08c00/mask=xffe0fc00 --status nopcodeop + +:cmtst Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x11 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_cmtst(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.37 CMTST page C7-2090 line 121743 MATCH x0e208c00/mask=xbf20fc00 +# CONSTRUCT x0ea08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@4 +# AUNIT --inst x0ea08c00/mask=xffe0fc00 --status nopcodeop + +:cmtst Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x11 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_cmtst(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.37 CMTST page C7-2090 line 121743 MATCH x0e208c00/mask=xbf20fc00 +# CONSTRUCT x0e608c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@2 +# AUNIT --inst x0e608c00/mask=xffe0fc00 --status nopcodeop + +:cmtst Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x11 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_cmtst(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.37 CMTST page C7-2090 line 121743 MATCH x0e208c00/mask=xbf20fc00 +# CONSTRUCT x4ea08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@4 +# AUNIT --inst x4ea08c00/mask=xffe0fc00 --status nopcodeop + +:cmtst Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x11 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_cmtst(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.37 CMTST page C7-2090 line 121743 MATCH x0e208c00/mask=xbf20fc00 +# CONSTRUCT x0e208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@1 +# AUNIT --inst x0e208c00/mask=xffe0fc00 --status nopcodeop + +:cmtst Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x11 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_cmtst(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.37 CMTST page C7-2090 line 121743 MATCH x0e208c00/mask=xbf20fc00 +# CONSTRUCT x4e608c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@2 +# AUNIT --inst x4e608c00/mask=xffe0fc00 --status nopcodeop + +:cmtst Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x11 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_cmtst(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.37 CMTST page C7-2090 line 121743 MATCH x5e208c00/mask=xff20fc00 +# CONSTRUCT x5ee08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2 +# AUNIT --inst x5ee08c00/mask=xffe0fc00 --status nopcodeop + +:cmtst Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_2431=0b01011110 & b_2223=0b11 & b_21=1 & b_1015=0b100011 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd +{ + Rd_FPR64 = NEON_cmtst(Rn_FPR64, Rm_FPR64); +} + +# C7.2.38 CNT page C7-2092 line 121883 MATCH x0e205800/mask=xbf3ffc00 +# CONSTRUCT x4e205800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_cnt/1@1 +# AUNIT --inst x4e205800/mask=xfffffc00 --status nopcodeop + +:cnt Rd_VPR128.16B, Rn_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x5 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_cnt(Rn_VPR128.16B, 1:1); +} + +# C7.2.38 CNT page C7-2092 line 121883 MATCH x0e205800/mask=xbf3ffc00 +# CONSTRUCT x0e205800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_cnt/1@1 +# AUNIT --inst x0e205800/mask=xfffffc00 --status nopcodeop + +:cnt Rd_VPR64.8B, Rn_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x5 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_cnt(Rn_VPR64.8B, 1:1); +} + +# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x0e000400/mask=xbfe0fc00 +# CONSTRUCT x4e010400/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 &=$dup +# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@1 +# AUNIT --inst x4e010400/mask=xffe1fc00 --status pass + +:dup Rd_VPR128.16B, Rn_VPR128.B.imm_neon_uimm4 +is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR128.16B & Zd +{ + # simd element Rn_VPR128[imm_neon_uimm4] lane size 1 + local tmp1:1 = Rn_VPR128.B.imm_neon_uimm4; + # simd duplicate Rd_VPR128.16B = all elements tmp1 (lane size 1) + Rd_VPR128.16B[0,8] = tmp1; + Rd_VPR128.16B[8,8] = tmp1; + Rd_VPR128.16B[16,8] = tmp1; + Rd_VPR128.16B[24,8] = tmp1; + Rd_VPR128.16B[32,8] = tmp1; + Rd_VPR128.16B[40,8] = tmp1; + Rd_VPR128.16B[48,8] = tmp1; + Rd_VPR128.16B[56,8] = tmp1; + Rd_VPR128.16B[64,8] = tmp1; + Rd_VPR128.16B[72,8] = tmp1; + Rd_VPR128.16B[80,8] = tmp1; + Rd_VPR128.16B[88,8] = tmp1; + Rd_VPR128.16B[96,8] = tmp1; + Rd_VPR128.16B[104,8] = tmp1; + Rd_VPR128.16B[112,8] = tmp1; + Rd_VPR128.16B[120,8] = tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x0e000400/mask=xbfe0fc00 +# CONSTRUCT x4e080400/mask=xffeffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 &=$dup +# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@8 +# AUNIT --inst x4e080400/mask=xffeffc00 --status pass + +:dup Rd_VPR128.2D, Rn_VPR128.D.imm_neon_uimm1 +is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.D.imm_neon_uimm1 & b_1619=0x8 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR128.2D & Zd +{ + # simd element Rn_VPR128[imm_neon_uimm1] lane size 8 + local tmp1:8 = Rn_VPR128.D.imm_neon_uimm1; + # simd duplicate Rd_VPR128.2D = all elements tmp1 (lane size 8) + Rd_VPR128.2D[0,64] = tmp1; + Rd_VPR128.2D[64,64] = tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x0e000400/mask=xbfe0fc00 +# CONSTRUCT x0e040400/mask=xffe7fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 &=$dup +# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@4 +# AUNIT --inst x0e040400/mask=xffe7fc00 --status pass + +:dup Rd_VPR64.2S, Rn_VPR128.S.imm_neon_uimm2 +is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR64.2S & Zd +{ + # simd element Rn_VPR128[imm_neon_uimm2] lane size 4 + local tmp1:4 = Rn_VPR128.S.imm_neon_uimm2; + # simd duplicate Rd_VPR64.2S = all elements tmp1 (lane size 4) + Rd_VPR64.2S[0,32] = tmp1; + Rd_VPR64.2S[32,32] = tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x0e000400/mask=xbfe0fc00 +# CONSTRUCT x0e020400/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 &=$dup +# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@2 +# AUNIT --inst x0e020400/mask=xffe3fc00 --status pass + +:dup Rd_VPR64.4H, Rn_VPR128.H.imm_neon_uimm3 +is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR64.4H & Zd +{ + # simd element Rn_VPR128[imm_neon_uimm3] lane size 2 + local tmp1:2 = Rn_VPR128.H.imm_neon_uimm3; + # simd duplicate Rd_VPR64.4H = all elements tmp1 (lane size 2) + Rd_VPR64.4H[0,16] = tmp1; + Rd_VPR64.4H[16,16] = tmp1; + Rd_VPR64.4H[32,16] = tmp1; + Rd_VPR64.4H[48,16] = tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x0e000400/mask=xbfe0fc00 +# CONSTRUCT x4e040400/mask=xffe7fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 &=$dup +# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@4 +# AUNIT --inst x4e040400/mask=xffe7fc00 --status pass + +:dup Rd_VPR128.4S, Rn_VPR128.S.imm_neon_uimm2 +is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR128.4S & Zd +{ + # simd element Rn_VPR128[imm_neon_uimm2] lane size 4 + local tmp1:4 = Rn_VPR128.S.imm_neon_uimm2; + # simd duplicate Rd_VPR128.4S = all elements tmp1 (lane size 4) + Rd_VPR128.4S[0,32] = tmp1; + Rd_VPR128.4S[32,32] = tmp1; + Rd_VPR128.4S[64,32] = tmp1; + Rd_VPR128.4S[96,32] = tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x0e000400/mask=xbfe0fc00 +# CONSTRUCT x0e010400/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 &=$dup +# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@1 +# AUNIT --inst x0e010400/mask=xffe1fc00 --status pass + +:dup Rd_VPR64.8B, Rn_VPR128.B.imm_neon_uimm4 +is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR64.8B & Zd +{ + # simd element Rn_VPR128[imm_neon_uimm4] lane size 1 + local tmp1:1 = Rn_VPR128.B.imm_neon_uimm4; + # simd duplicate Rd_VPR64.8B = all elements tmp1 (lane size 1) + Rd_VPR64.8B[0,8] = tmp1; + Rd_VPR64.8B[8,8] = tmp1; + Rd_VPR64.8B[16,8] = tmp1; + Rd_VPR64.8B[24,8] = tmp1; + Rd_VPR64.8B[32,8] = tmp1; + Rd_VPR64.8B[40,8] = tmp1; + Rd_VPR64.8B[48,8] = tmp1; + Rd_VPR64.8B[56,8] = tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x0e000400/mask=xbfe0fc00 +# CONSTRUCT x4e020400/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 &=$dup +# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@2 +# AUNIT --inst x4e020400/mask=xffe3fc00 --status pass + +:dup Rd_VPR128.8H, Rn_VPR128.H.imm_neon_uimm3 +is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR128.8H & Zd +{ + # simd element Rn_VPR128[imm_neon_uimm3] lane size 2 + local tmp1:2 = Rn_VPR128.H.imm_neon_uimm3; + # simd duplicate Rd_VPR128.8H = all elements tmp1 (lane size 2) + Rd_VPR128.8H[0,16] = tmp1; + Rd_VPR128.8H[16,16] = tmp1; + Rd_VPR128.8H[32,16] = tmp1; + Rd_VPR128.8H[48,16] = tmp1; + Rd_VPR128.8H[64,16] = tmp1; + Rd_VPR128.8H[80,16] = tmp1; + Rd_VPR128.8H[96,16] = tmp1; + Rd_VPR128.8H[112,16] = tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x5e000400/mask=xffe0fc00 +# C7.2.199 MOV (scalar) page C7-2481 line 145318 MATCH x5e000400/mask=xffe0fc00 +# CONSTRUCT x5e010400/mask=xffe1fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 =ARG2 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@1 +# AUNIT --inst x5e010400/mask=xffe1fc00 --status pass + +:dup Rd_FPR8, Rn_VPR128.B.imm_neon_uimm4 +is b_3131=0 & q=1 & b_29=0 & b_2428=0x1e & b_2123=0 & Rn_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_FPR8 & Zd +{ + # simd element Rn_VPR128[imm_neon_uimm4] lane size 1 + Rd_FPR8 = Rn_VPR128.B.imm_neon_uimm4; + zext_zb(Zd); # zero upper 31 bytes of Zd +} + +# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x5e000400/mask=xffe0fc00 +# C7.2.199 MOV (scalar) page C7-2481 line 145318 MATCH x5e000400/mask=xffe0fc00 +# CONSTRUCT x5e080400/mask=xffeffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 =ARG2 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@8 +# AUNIT --inst x5e080400/mask=xffeffc00 --status pass + +:dup Rd_FPR64, Rn_VPR128.D.imm_neon_uimm1 +is b_3131=0 & q=1 & b_29=0 & b_2428=0x1e & b_2123=0 & Rn_VPR128.D.imm_neon_uimm1 & b_1619=0x8 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_FPR64 & Zd +{ + # simd element Rn_VPR128[imm_neon_uimm1] lane size 8 + Rd_FPR64 = Rn_VPR128.D.imm_neon_uimm1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x5e000400/mask=xffe0fc00 +# C7.2.199 MOV (scalar) page C7-2481 line 145318 MATCH x5e000400/mask=xffe0fc00 +# CONSTRUCT x5e020400/mask=xffe3fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 =ARG2 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@2 +# AUNIT --inst x5e020400/mask=xffe3fc00 --status pass + +:dup Rd_FPR16, Rn_VPR128.H.imm_neon_uimm3 +is b_3131=0 & q=1 & b_29=0 & b_2428=0x1e & b_2123=0 & Rn_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_FPR16 & Zd +{ + # simd element Rn_VPR128[imm_neon_uimm3] lane size 2 + Rd_FPR16 = Rn_VPR128.H.imm_neon_uimm3; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x5e000400/mask=xffe0fc00 +# C7.2.199 MOV (scalar) page C7-2481 line 145318 MATCH x5e000400/mask=xffe0fc00 +# CONSTRUCT x5e040400/mask=xffe7fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 =ARG2 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@4 +# AUNIT --inst x5e040400/mask=xffe7fc00 --status pass + +:dup Rd_FPR32, Rn_VPR128.S.imm_neon_uimm2 +is b_3131=0 & q=1 & b_29=0 & b_2428=0x1e & b_2123=0 & Rn_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_FPR32 & Zd +{ + # simd element Rn_VPR128[imm_neon_uimm2] lane size 4 + Rd_FPR32 = Rn_VPR128.S.imm_neon_uimm2; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.40 DUP (general) page C7-2097 line 122143 MATCH x0e000c00/mask=xbfe0fc00 +# CONSTRUCT x4e010c00/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(force-primitive) ARG1 ARG2[0]:1 &=$dup +# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@1 +# AUNIT --inst x4e010c00/mask=xffe1fc00 --status pass + +:dup Rd_VPR128.16B, Rn_GPR32 +is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & b_16=1 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR32 & Rd_VPR128.16B & Zd +{ + local tmp1:1 = Rn_GPR32[0,8]; + # simd duplicate Rd_VPR128.16B = all elements tmp1 (lane size 1) + Rd_VPR128.16B[0,8] = tmp1; + Rd_VPR128.16B[8,8] = tmp1; + Rd_VPR128.16B[16,8] = tmp1; + Rd_VPR128.16B[24,8] = tmp1; + Rd_VPR128.16B[32,8] = tmp1; + Rd_VPR128.16B[40,8] = tmp1; + Rd_VPR128.16B[48,8] = tmp1; + Rd_VPR128.16B[56,8] = tmp1; + Rd_VPR128.16B[64,8] = tmp1; + Rd_VPR128.16B[72,8] = tmp1; + Rd_VPR128.16B[80,8] = tmp1; + Rd_VPR128.16B[88,8] = tmp1; + Rd_VPR128.16B[96,8] = tmp1; + Rd_VPR128.16B[104,8] = tmp1; + Rd_VPR128.16B[112,8] = tmp1; + Rd_VPR128.16B[120,8] = tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.40 DUP (general) page C7-2097 line 122143 MATCH x0e000c00/mask=xbfe0fc00 +# CONSTRUCT x4e080c00/mask=xffeffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 &=$dup +# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@8 +# AUNIT --inst x4e080c00/mask=xffeffc00 --status pass + +:dup Rd_VPR128.2D, Rn_GPR64 +is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & b_1619=0b1000 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR64 & Rd_VPR128.2D & Zd +{ + # simd duplicate Rd_VPR128.2D = all elements Rn_GPR64 (lane size 8) + Rd_VPR128.2D[0,64] = Rn_GPR64; + Rd_VPR128.2D[64,64] = Rn_GPR64; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.40 DUP (general) page C7-2097 line 122143 MATCH x0e000c00/mask=xbfe0fc00 +# CONSTRUCT x0e040c00/mask=xffe7fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 &=$dup +# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@4 +# AUNIT --inst x0e040c00/mask=xffe7fc00 --status pass + +:dup Rd_VPR64.2S, Rn_GPR32 +is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & b_1618=0b100 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR32 & Rd_VPR64.2S & Zd +{ + # simd duplicate Rd_VPR64.2S = all elements Rn_GPR32 (lane size 4) + Rd_VPR64.2S[0,32] = Rn_GPR32; + Rd_VPR64.2S[32,32] = Rn_GPR32; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.40 DUP (general) page C7-2097 line 122143 MATCH x0e000c00/mask=xbfe0fc00 +# CONSTRUCT x0e020c00/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[0]:2 &=$dup +# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@2 +# AUNIT --inst x0e020c00/mask=xffe3fc00 --status pass + +:dup Rd_VPR64.4H, Rn_GPR32 +is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & b_1617=0b10 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR32 & Rd_VPR64.4H & Zd +{ + local tmp1:2 = Rn_GPR32[0,16]; + # simd duplicate Rd_VPR64.4H = all elements tmp1 (lane size 2) + Rd_VPR64.4H[0,16] = tmp1; + Rd_VPR64.4H[16,16] = tmp1; + Rd_VPR64.4H[32,16] = tmp1; + Rd_VPR64.4H[48,16] = tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.40 DUP (general) page C7-2097 line 122143 MATCH x0e000c00/mask=xbfe0fc00 +# CONSTRUCT x4e040c00/mask=xffe7fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 &=$dup +# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@4 +# AUNIT --inst x4e040c00/mask=xffe7fc00 --status pass + +:dup Rd_VPR128.4S, Rn_GPR32 +is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & b_1618=0b100 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR32 & Rd_VPR128.4S & Zd +{ + # simd duplicate Rd_VPR128.4S = all elements Rn_GPR32 (lane size 4) + Rd_VPR128.4S[0,32] = Rn_GPR32; + Rd_VPR128.4S[32,32] = Rn_GPR32; + Rd_VPR128.4S[64,32] = Rn_GPR32; + Rd_VPR128.4S[96,32] = Rn_GPR32; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.40 DUP (general) page C7-2097 line 122143 MATCH x0e000c00/mask=xbfe0fc00 +# CONSTRUCT x0e010c00/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[0]:1 &=$dup +# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@1 +# AUNIT --inst x0e010c00/mask=xffe1fc00 --status pass + +:dup Rd_VPR64.8B, Rn_GPR32 +is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & b_16=1 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR32 & Rd_VPR64.8B & Zd +{ + local tmp1:1 = Rn_GPR32[0,8]; + # simd duplicate Rd_VPR64.8B = all elements tmp1 (lane size 1) + Rd_VPR64.8B[0,8] = tmp1; + Rd_VPR64.8B[8,8] = tmp1; + Rd_VPR64.8B[16,8] = tmp1; + Rd_VPR64.8B[24,8] = tmp1; + Rd_VPR64.8B[32,8] = tmp1; + Rd_VPR64.8B[40,8] = tmp1; + Rd_VPR64.8B[48,8] = tmp1; + Rd_VPR64.8B[56,8] = tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.40 DUP (general) page C7-2097 line 122143 MATCH x0e000c00/mask=xbfe0fc00 +# CONSTRUCT x4e020c00/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[0]:2 &=$dup +# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@2 +# AUNIT --inst x4e020c00/mask=xffe3fc00 --status pass + +:dup Rd_VPR128.8H, Rn_GPR32 +is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & b_1617=0b10 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR32 & Rd_VPR128.8H & Zd +{ + local tmp1:2 = Rn_GPR32[0,16]; + # simd duplicate Rd_VPR128.8H = all elements tmp1 (lane size 2) + Rd_VPR128.8H[0,16] = tmp1; + Rd_VPR128.8H[16,16] = tmp1; + Rd_VPR128.8H[32,16] = tmp1; + Rd_VPR128.8H[48,16] = tmp1; + Rd_VPR128.8H[64,16] = tmp1; + Rd_VPR128.8H[80,16] = tmp1; + Rd_VPR128.8H[96,16] = tmp1; + Rd_VPR128.8H[112,16] = tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.41 EOR (vector) page C7-2099 line 122248 MATCH x2e201c00/mask=xbfe0fc00 +# CONSTRUCT x6e201c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$^@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_eor/2@1 +# AUNIT --inst x6e201c00/mask=xffe0fc00 --status pass + +:eor Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + # simd infix Rd_VPR128.16B = Rn_VPR128.16B ^ Rm_VPR128.16B on lane size 1 + Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] ^ Rm_VPR128.16B[0,8]; + Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] ^ Rm_VPR128.16B[8,8]; + Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] ^ Rm_VPR128.16B[16,8]; + Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] ^ Rm_VPR128.16B[24,8]; + Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] ^ Rm_VPR128.16B[32,8]; + Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] ^ Rm_VPR128.16B[40,8]; + Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] ^ Rm_VPR128.16B[48,8]; + Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] ^ Rm_VPR128.16B[56,8]; + Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] ^ Rm_VPR128.16B[64,8]; + Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] ^ Rm_VPR128.16B[72,8]; + Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] ^ Rm_VPR128.16B[80,8]; + Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] ^ Rm_VPR128.16B[88,8]; + Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] ^ Rm_VPR128.16B[96,8]; + Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] ^ Rm_VPR128.16B[104,8]; + Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] ^ Rm_VPR128.16B[112,8]; + Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] ^ Rm_VPR128.16B[120,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.41 EOR (vector) page C7-2099 line 122248 MATCH x2e201c00/mask=xbfe0fc00 +# CONSTRUCT x2e201c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$^@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_eor/2@1 +# AUNIT --inst x2e201c00/mask=xffe0fc00 --status pass + +:eor Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + # simd infix Rd_VPR64.8B = Rn_VPR64.8B ^ Rm_VPR64.8B on lane size 1 + Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] ^ Rm_VPR64.8B[0,8]; + Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] ^ Rm_VPR64.8B[8,8]; + Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] ^ Rm_VPR64.8B[16,8]; + Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] ^ Rm_VPR64.8B[24,8]; + Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] ^ Rm_VPR64.8B[32,8]; + Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] ^ Rm_VPR64.8B[40,8]; + Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] ^ Rm_VPR64.8B[48,8]; + Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] ^ Rm_VPR64.8B[56,8]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.42 EOR3 page C7-2101 line 122332 MATCH xce000000/mask=xffe08000 +# CONSTRUCT xce000000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 ARG4 $|@1 =$|@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_eor3/3@1 +# AUNIT --inst xce000000/mask=xffe08000 --status noqemu + +:eor3 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, Ra_VPR128.16B +is b_2131=0b11001110000 & b_15=0 & Rd_VPR128.16B & Rn_VPR128.16B & Rm_VPR128.16B & Ra_VPR128.16B & Zd +{ + # simd infix TMPQ1 = Rm_VPR128.16B | Ra_VPR128.16B on lane size 1 + TMPQ1[0,8] = Rm_VPR128.16B[0,8] | Ra_VPR128.16B[0,8]; + TMPQ1[8,8] = Rm_VPR128.16B[8,8] | Ra_VPR128.16B[8,8]; + TMPQ1[16,8] = Rm_VPR128.16B[16,8] | Ra_VPR128.16B[16,8]; + TMPQ1[24,8] = Rm_VPR128.16B[24,8] | Ra_VPR128.16B[24,8]; + TMPQ1[32,8] = Rm_VPR128.16B[32,8] | Ra_VPR128.16B[32,8]; + TMPQ1[40,8] = Rm_VPR128.16B[40,8] | Ra_VPR128.16B[40,8]; + TMPQ1[48,8] = Rm_VPR128.16B[48,8] | Ra_VPR128.16B[48,8]; + TMPQ1[56,8] = Rm_VPR128.16B[56,8] | Ra_VPR128.16B[56,8]; + TMPQ1[64,8] = Rm_VPR128.16B[64,8] | Ra_VPR128.16B[64,8]; + TMPQ1[72,8] = Rm_VPR128.16B[72,8] | Ra_VPR128.16B[72,8]; + TMPQ1[80,8] = Rm_VPR128.16B[80,8] | Ra_VPR128.16B[80,8]; + TMPQ1[88,8] = Rm_VPR128.16B[88,8] | Ra_VPR128.16B[88,8]; + TMPQ1[96,8] = Rm_VPR128.16B[96,8] | Ra_VPR128.16B[96,8]; + TMPQ1[104,8] = Rm_VPR128.16B[104,8] | Ra_VPR128.16B[104,8]; + TMPQ1[112,8] = Rm_VPR128.16B[112,8] | Ra_VPR128.16B[112,8]; + TMPQ1[120,8] = Rm_VPR128.16B[120,8] | Ra_VPR128.16B[120,8]; + # simd infix Rd_VPR128.16B = Rn_VPR128.16B | TMPQ1 on lane size 1 + Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] | TMPQ1[0,8]; + Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] | TMPQ1[8,8]; + Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] | TMPQ1[16,8]; + Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] | TMPQ1[24,8]; + Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] | TMPQ1[32,8]; + Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] | TMPQ1[40,8]; + Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] | TMPQ1[48,8]; + Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] | TMPQ1[56,8]; + Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] | TMPQ1[64,8]; + Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] | TMPQ1[72,8]; + Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] | TMPQ1[80,8]; + Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] | TMPQ1[88,8]; + Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] | TMPQ1[96,8]; + Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] | TMPQ1[104,8]; + Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] | TMPQ1[112,8]; + Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] | TMPQ1[120,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.43 EXT page C7-2102 line 122403 MATCH x2e000000/mask=xbfe08400 +# CONSTRUCT x6e000000/mask=xffe08400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 imm4:1 =NEON_ext/3@1 +# AUNIT --inst x6e000000/mask=xffe08400 --status nopcodeop + +:ext Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, imm4 +is b_3131=0 & q=1 & b_2429=0x2e & b_2223=0b00 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & imm4 & b_1010=0 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_ext(Rn_VPR128.16B, Rm_VPR128.16B, imm4:1, 1:1); +} + +# C7.2.43 EXT page C7-2102 line 122403 MATCH x2e000000/mask=xbfe08400 +# CONSTRUCT x2e000000/mask=xffe0c400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 imm4:1 =NEON_ext/3@1 +# AUNIT --inst x2e000000/mask=xffe0c400 --status nopcodeop + +:ext Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B, imm4 +is b_3131=0 & q=0 & b_2429=0x2e & b_2223=0b00 & b_2121=0 & Rm_VPR64.8B & b_1415=0 & imm4 & b_1010=0 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_ext(Rn_VPR64.8B, Rm_VPR64.8B, imm4:1, 1:1); +} + +# C7.2.44 FABD page C7-2104 line 122507 MATCH x2ec01400/mask=xbfe0fc00 +# CONSTRUCT x2ec01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $f-@2 =$fabs@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2@2 +# AUNIT --inst x2ec01400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Vector half precision variant when Q=0 sz=1 bb=0 cc=00 F=VPR64.4H + +:fabd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=1 & b_21=0 & b_1015=0b000101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + # simd infix TMPD1 = Rn_VPR64.4H f- Rm_VPR64.4H on lane size 2 + TMPD1[0,16] = Rn_VPR64.4H[0,16] f- Rm_VPR64.4H[0,16]; + TMPD1[16,16] = Rn_VPR64.4H[16,16] f- Rm_VPR64.4H[16,16]; + TMPD1[32,16] = Rn_VPR64.4H[32,16] f- Rm_VPR64.4H[32,16]; + TMPD1[48,16] = Rn_VPR64.4H[48,16] f- Rm_VPR64.4H[48,16]; + # simd unary Rd_VPR64.4H = abs(TMPD1) on lane size 2 + Rd_VPR64.4H[0,16] = abs(TMPD1[0,16]); + Rd_VPR64.4H[16,16] = abs(TMPD1[16,16]); + Rd_VPR64.4H[32,16] = abs(TMPD1[32,16]); + Rd_VPR64.4H[48,16] = abs(TMPD1[48,16]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.44 FABD page C7-2104 line 122507 MATCH x2ec01400/mask=xbfe0fc00 +# CONSTRUCT x6ec01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $f-@2 =$fabs@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2@2 +# AUNIT --inst x6ec01400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Vector half precision variant when Q=1 sz=1 bb=0 cc=00 F=VPR128.8H + +:fabd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=1 & b_21=0 & b_1015=0b000101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.8H f- Rm_VPR128.8H on lane size 2 + TMPQ1[0,16] = Rn_VPR128.8H[0,16] f- Rm_VPR128.8H[0,16]; + TMPQ1[16,16] = Rn_VPR128.8H[16,16] f- Rm_VPR128.8H[16,16]; + TMPQ1[32,16] = Rn_VPR128.8H[32,16] f- Rm_VPR128.8H[32,16]; + TMPQ1[48,16] = Rn_VPR128.8H[48,16] f- Rm_VPR128.8H[48,16]; + TMPQ1[64,16] = Rn_VPR128.8H[64,16] f- Rm_VPR128.8H[64,16]; + TMPQ1[80,16] = Rn_VPR128.8H[80,16] f- Rm_VPR128.8H[80,16]; + TMPQ1[96,16] = Rn_VPR128.8H[96,16] f- Rm_VPR128.8H[96,16]; + TMPQ1[112,16] = Rn_VPR128.8H[112,16] f- Rm_VPR128.8H[112,16]; + # simd unary Rd_VPR128.8H = abs(TMPQ1) on lane size 2 + Rd_VPR128.8H[0,16] = abs(TMPQ1[0,16]); + Rd_VPR128.8H[16,16] = abs(TMPQ1[16,16]); + Rd_VPR128.8H[32,16] = abs(TMPQ1[32,16]); + Rd_VPR128.8H[48,16] = abs(TMPQ1[48,16]); + Rd_VPR128.8H[64,16] = abs(TMPQ1[64,16]); + Rd_VPR128.8H[80,16] = abs(TMPQ1[80,16]); + Rd_VPR128.8H[96,16] = abs(TMPQ1[96,16]); + Rd_VPR128.8H[112,16] = abs(TMPQ1[112,16]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.44 FABD page C7-2104 line 122507 MATCH x2ea0d400/mask=xbfa0fc00 +# CONSTRUCT x2ea0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $f-@4 =$fabs@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2@4 +# AUNIT --inst x2ea0d400/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround" +# Vector half precision variant when Q=0 sz=0 bb=1 cc=11 F=VPR64.2S + +:fabd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=0 & b_21=1 & b_1015=0b110101 & Rd_VPR64.2S & Rn_VPR64.2S & Rm_VPR64.2S & Zd +{ + # simd infix TMPD1 = Rn_VPR64.2S f- Rm_VPR64.2S on lane size 4 + TMPD1[0,32] = Rn_VPR64.2S[0,32] f- Rm_VPR64.2S[0,32]; + TMPD1[32,32] = Rn_VPR64.2S[32,32] f- Rm_VPR64.2S[32,32]; + # simd unary Rd_VPR64.2S = abs(TMPD1) on lane size 4 + Rd_VPR64.2S[0,32] = abs(TMPD1[0,32]); + Rd_VPR64.2S[32,32] = abs(TMPD1[32,32]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.44 FABD page C7-2104 line 122507 MATCH x2ea0d400/mask=xbfa0fc00 +# CONSTRUCT x6ea0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $f-@4 =$fabs@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2@4 +# AUNIT --inst x6ea0d400/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround" +# Vector half precision variant when Q=1 sz=0 bb=1 cc=11 F=VPR128.4S + +:fabd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=0 & b_21=1 & b_1015=0b110101 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.4S f- Rm_VPR128.4S on lane size 4 + TMPQ1[0,32] = Rn_VPR128.4S[0,32] f- Rm_VPR128.4S[0,32]; + TMPQ1[32,32] = Rn_VPR128.4S[32,32] f- Rm_VPR128.4S[32,32]; + TMPQ1[64,32] = Rn_VPR128.4S[64,32] f- Rm_VPR128.4S[64,32]; + TMPQ1[96,32] = Rn_VPR128.4S[96,32] f- Rm_VPR128.4S[96,32]; + # simd unary Rd_VPR128.4S = abs(TMPQ1) on lane size 4 + Rd_VPR128.4S[0,32] = abs(TMPQ1[0,32]); + Rd_VPR128.4S[32,32] = abs(TMPQ1[32,32]); + Rd_VPR128.4S[64,32] = abs(TMPQ1[64,32]); + Rd_VPR128.4S[96,32] = abs(TMPQ1[96,32]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.44 FABD page C7-2104 line 122507 MATCH x2ea0d400/mask=xbfa0fc00 +# CONSTRUCT x6ee0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $f-@8 =$fabs@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2@8 +# AUNIT --inst x6ee0d400/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround" +# Vector half precision variant when Q=1 sz=1 bb=1 cc=11 F=VPR128.2D + +:fabd Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=1 & b_21=1 & b_1015=0b110101 & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.2D f- Rm_VPR128.2D on lane size 8 + TMPQ1[0,64] = Rn_VPR128.2D[0,64] f- Rm_VPR128.2D[0,64]; + TMPQ1[64,64] = Rn_VPR128.2D[64,64] f- Rm_VPR128.2D[64,64]; + # simd unary Rd_VPR128.2D = abs(TMPQ1) on lane size 8 + Rd_VPR128.2D[0,64] = abs(TMPQ1[0,64]); + Rd_VPR128.2D[64,64] = abs(TMPQ1[64,64]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.44 FABD page C7-2104 line 122507 MATCH x7ec01400/mask=xffe0fc00 +# CONSTRUCT x7ec01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 f- =fabs +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2 +# AUNIT --inst x7ec01400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Scalar half precision variant when sz=1 bb=0 cc=00 F=FPR16 + +:fabd Rd_FPR16, Rn_FPR16, Rm_FPR16 +is b_2131=0b01111110110 & b_1015=0b000101 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd +{ + local tmp1:2 = Rn_FPR16 f- Rm_FPR16; + Rd_FPR16 = abs(tmp1); + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.44 FABD page C7-2104 line 122507 MATCH x7ea0d400/mask=xffa0fc00 +# CONSTRUCT x7ea0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 f- =fabs +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2 +# AUNIT --inst x7ea0d400/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround" +# Scalar half precision variant when sz=0 bb=1 cc=11 F=FPR32 + +:fabd Rd_FPR32, Rn_FPR32, Rm_FPR32 +is b_2131=0b01111110101 & b_1015=0b110101 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd +{ + local tmp1:4 = Rn_FPR32 f- Rm_FPR32; + Rd_FPR32 = abs(tmp1); + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.44 FABD page C7-2104 line 122507 MATCH x7ea0d400/mask=xffa0fc00 +# CONSTRUCT x7ee0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 f- =fabs +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2 +# AUNIT --inst x7ee0d400/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround" +# Scalar half precision variant when sz=1 bb=1 cc=11 F=FPR64 + +:fabd Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_2131=0b01111110111 & b_1015=0b110101 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd +{ + local tmp1:8 = Rn_FPR64 f- Rm_FPR64; + Rd_FPR64 = abs(tmp1); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.45 FABS (vector) page C7-2107 line 122704 MATCH x0ea0f800/mask=xbfbffc00 +# CONSTRUCT x4ee0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$fabs@8 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1@8 +# AUNIT --inst x4ee0f800/mask=xfffffc00 --rand dfp --status pass + +:fabs Rd_VPR128.2D, Rn_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0xf & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + # simd unary Rd_VPR128.2D = abs(Rn_VPR128.2D) on lane size 8 + Rd_VPR128.2D[0,64] = abs(Rn_VPR128.2D[0,64]); + Rd_VPR128.2D[64,64] = abs(Rn_VPR128.2D[64,64]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.45 FABS (vector) page C7-2107 line 122704 MATCH x0ea0f800/mask=xbfbffc00 +# CONSTRUCT x0ea0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$fabs@4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1@4 +# AUNIT --inst x0ea0f800/mask=xfffffc00 --rand sfp --status pass + +:fabs Rd_VPR64.2S, Rn_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xf & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + # simd unary Rd_VPR64.2S = abs(Rn_VPR64.2S) on lane size 4 + Rd_VPR64.2S[0,32] = abs(Rn_VPR64.2S[0,32]); + Rd_VPR64.2S[32,32] = abs(Rn_VPR64.2S[32,32]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.45 FABS (vector) page C7-2107 line 122704 MATCH x0ea0f800/mask=xbfbffc00 +# CONSTRUCT x4ea0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$fabs@4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1@4 +# AUNIT --inst x4ea0f800/mask=xfffffc00 --rand sfp --status pass + +:fabs Rd_VPR128.4S, Rn_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xf & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd unary Rd_VPR128.4S = abs(Rn_VPR128.4S) on lane size 4 + Rd_VPR128.4S[0,32] = abs(Rn_VPR128.4S[0,32]); + Rd_VPR128.4S[32,32] = abs(Rn_VPR128.4S[32,32]); + Rd_VPR128.4S[64,32] = abs(Rn_VPR128.4S[64,32]); + Rd_VPR128.4S[96,32] = abs(Rn_VPR128.4S[96,32]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.45 FABS (vector) page C7-2107 line 122704 MATCH x0ef8f800/mask=xbffffc00 +# CONSTRUCT x0ef8f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$fabs@2 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1@2 +# AUNIT --inst x0ef8f800/mask=xfffffc00 --rand hfp --status noqemu +# FABS (vector) SIMD 4H when size=0 Q=0 + +:fabs Rd_VPR64.4H, Rn_VPR64.4H +is b_31=0 & b_30=0 & b_1029=0b00111011111000111110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd +{ + # simd unary Rd_VPR64.4H = abs(Rn_VPR64.4H) on lane size 2 + Rd_VPR64.4H[0,16] = abs(Rn_VPR64.4H[0,16]); + Rd_VPR64.4H[16,16] = abs(Rn_VPR64.4H[16,16]); + Rd_VPR64.4H[32,16] = abs(Rn_VPR64.4H[32,16]); + Rd_VPR64.4H[48,16] = abs(Rn_VPR64.4H[48,16]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.45 FABS (vector) page C7-2107 line 122704 MATCH x0ef8f800/mask=xbffffc00 +# CONSTRUCT x4ef8f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$fabs@2 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1@2 +# AUNIT --inst x4ef8f800/mask=xfffffc00 --rand hfp --status noqemu +# FABS (vector) SIMD 8H when size=0 Q=1 + +:fabs Rd_VPR128.8H, Rn_VPR128.8H +is b_31=0 & b_30=1 & b_1029=0b00111011111000111110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd +{ + # simd unary Rd_VPR128.8H = abs(Rn_VPR128.8H) on lane size 2 + Rd_VPR128.8H[0,16] = abs(Rn_VPR128.8H[0,16]); + Rd_VPR128.8H[16,16] = abs(Rn_VPR128.8H[16,16]); + Rd_VPR128.8H[32,16] = abs(Rn_VPR128.8H[32,16]); + Rd_VPR128.8H[48,16] = abs(Rn_VPR128.8H[48,16]); + Rd_VPR128.8H[64,16] = abs(Rn_VPR128.8H[64,16]); + Rd_VPR128.8H[80,16] = abs(Rn_VPR128.8H[80,16]); + Rd_VPR128.8H[96,16] = abs(Rn_VPR128.8H[96,16]); + Rd_VPR128.8H[112,16] = abs(Rn_VPR128.8H[112,16]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.46 FABS (scalar) page C7-2109 line 122815 MATCH x1e20c000/mask=xff3ffc00 +# CONSTRUCT x1ee0c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =fabs +# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1 +# AUNIT --inst x1ee0c000/mask=xfffffc00 --rand hfp --status noqemu + +:fabs Rd_FPR16, Rn_FPR16 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & fpDpOpcode=0x1 & b_1014=0x10 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = abs(Rn_FPR16); + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.46 FABS (scalar) page C7-2109 line 122815 MATCH x1e20c000/mask=xff3ffc00 +# CONSTRUCT x1e60c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =fabs +# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1 +# AUNIT --inst x1e60c000/mask=xfffffc00 --rand dfp --status pass + +:fabs Rd_FPR64, Rn_FPR64 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & fpDpOpcode=0x1 & b_1014=0x10 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = abs(Rn_FPR64); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.46 FABS (scalar) page C7-2109 line 122815 MATCH x1e20c000/mask=xff3ffc00 +# CONSTRUCT x1e20c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =fabs +# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1 +# AUNIT --inst x1e20c000/mask=xfffffc00 --rand sfp --status pass + +:fabs Rd_FPR32, Rn_FPR32 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & fpDpOpcode=0x1 & b_1014=0x10 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = abs(Rn_FPR32); + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.47 FACGE page C7-2111 line 122911 MATCH x2e20ec00/mask=xbfa0fc00 +# CONSTRUCT x6e60ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2@8 +# AUNIT --inst x6e60ec00/mask=xffe0fc00 --rand dfp --status nopcodeop + +:facge Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1d & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_facge(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.47 FACGE page C7-2111 line 122911 MATCH x2e20ec00/mask=xbfa0fc00 +# CONSTRUCT x2e20ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2@4 +# AUNIT --inst x2e20ec00/mask=xffe0fc00 --rand sfp --status nopcodeop + +:facge Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1d & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_facge(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.47 FACGE page C7-2111 line 122911 MATCH x2e20ec00/mask=xbfa0fc00 +# CONSTRUCT x6e20ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2@4 +# AUNIT --inst x6e20ec00/mask=xffe0fc00 --rand sfp --status nopcodeop + +:facge Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1d & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_facge(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.47 FACGE page C7-2111 line 122911 MATCH x7e402c00/mask=xffe0fc00 +# CONSTRUCT x7e402c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2 +# AUNIT --inst x7e402c00/mask=xffe0fc00 --rand hfp --status noqemu +# Scalar half precision + +:facge Rd_FPR16, Rn_FPR16, Rm_FPR16 +is b_2131=0b01111110010 & b_1015=0b001011 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd +{ + Rd_FPR16 = NEON_facge(Rn_FPR16, Rm_FPR16); +} + +# C7.2.47 FACGE page C7-2111 line 122911 MATCH x7e20ec00/mask=xffa0fc00 +# CONSTRUCT x7e20ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2 +# AUNIT --inst x7e20ec00/mask=xffe0fc00 --rand sfp --status nopcodeop +# Scalar single-precision and double-precision sz=0 + +:facge Rd_FPR32, Rn_FPR32, Rm_FPR32 +is b_2331=0b011111100 & b_22=0 & b_21=1 & b_1015=0b111011 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd +{ + Rd_FPR32 = NEON_facge(Rn_FPR32, Rm_FPR32); +} + +# C7.2.47 FACGE page C7-2111 line 122911 MATCH x7e20ec00/mask=xffa0fc00 +# CONSTRUCT x7e60ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2 +# AUNIT --inst x7e60ec00/mask=xffe0fc00 --rand dfp --status nopcodeop +# Scalar single-precision and double-precision sz=1 + +:facge Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_2331=0b011111100 & b_22=1 & b_21=1 & b_1015=0b111011 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd +{ + Rd_FPR64 = NEON_facge(Rn_FPR64, Rm_FPR64); +} + +# C7.2.47 FACGE page C7-2111 line 122911 MATCH x2e402c00/mask=xbfe0fc00 +# CONSTRUCT x2e402c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2@2 +# AUNIT --inst x2e402c00/mask=xffe0fc00 --rand hfp --status noqemu +# FACGE SIMD 4H when size=0 Q=0 + +:facge Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b001011 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_facge(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.47 FACGE page C7-2111 line 122911 MATCH x2e402c00/mask=xbfe0fc00 +# CONSTRUCT x6e402c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2@2 +# AUNIT --inst x6e402c00/mask=xffe0fc00 --rand hfp --status noqemu +# FACGE SIMD 8H when size=0 Q=1 + +:facge Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b001011 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_facge(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.48 FACGT page C7-2115 line 123160 MATCH x2ea0ec00/mask=xbfa0fc00 +# CONSTRUCT x6ee0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2@8 +# AUNIT --inst x6ee0ec00/mask=xffe0fc00 --rand dfp --status nopcodeop + +:facgt Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x1d & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_facgt(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.48 FACGT page C7-2115 line 123160 MATCH x2ea0ec00/mask=xbfa0fc00 +# CONSTRUCT x2ea0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2@4 +# AUNIT --inst x2ea0ec00/mask=xffe0fc00 --rand sfp --status nopcodeop + +:facgt Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x1d & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_facgt(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.48 FACGT page C7-2115 line 123160 MATCH x2ea0ec00/mask=xbfa0fc00 +# CONSTRUCT x6ea0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2@4 +# AUNIT --inst x6ea0ec00/mask=xffe0fc00 --rand sfp --status nopcodeop + +:facgt Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x1d & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_facgt(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.48 FACGT page C7-2115 line 123160 MATCH x7ec02c00/mask=xffe0fc00 +# CONSTRUCT x7ec02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2 +# AUNIT --inst x7ec02c00/mask=xffe0fc00 --rand hfp --status noqemu +# Scalar half precision + +:facgt Rd_FPR16, Rn_FPR16, Rm_FPR16 +is b_2131=0b01111110110 & b_1015=0b001011 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd +{ + Rd_FPR16 = NEON_facgt(Rn_FPR16, Rm_FPR16); +} + +# C7.2.48 FACGT page C7-2115 line 123160 MATCH x7ea0ec00/mask=xffa0fc00 +# CONSTRUCT x7ea0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2 +# AUNIT --inst x7ea0ec00/mask=xffe0fc00 --rand sfp --status nopcodeop +# Scalar single-precision and double-precision sz=0 + +:facgt Rd_FPR32, Rn_FPR32, Rm_FPR32 +is b_2331=0b011111101 & b_22=0 & b_21=1 & b_1015=0b111011 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd +{ + Rd_FPR32 = NEON_facgt(Rn_FPR32, Rm_FPR32); +} + +# C7.2.48 FACGT page C7-2115 line 123160 MATCH x7ea0ec00/mask=xffa0fc00 +# CONSTRUCT x7ee0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2 +# AUNIT --inst x7ee0ec00/mask=xffe0fc00 --rand dfp --status nopcodeop +# Scalar single-precision and double-precision sz=1 + +:facgt Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_2331=0b011111101 & b_22=1 & b_21=1 & b_1015=0b111011 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd +{ + Rd_FPR64 = NEON_facgt(Rn_FPR64, Rm_FPR64); +} + +# C7.2.48 FACGT page C7-2115 line 123160 MATCH x2ec02c00/mask=xbfe0fc00 +# CONSTRUCT x2ec02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2@2 +# AUNIT --inst x2ec02c00/mask=xffe0fc00 --rand hfp --status noqemu +# Vector half-precision SIMD 4H when Q=0 + +:facgt Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2129=0b101110110 & b_1015=0b001011 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_facgt(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.48 FACGT page C7-2115 line 123160 MATCH x2ec02c00/mask=xbfe0fc00 +# CONSTRUCT x6ec02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2@2 +# AUNIT --inst x6ec02c00/mask=xffe0fc00 --rand hfp --status noqemu +# Vector half-precision SIMD 8H when Q=1 + +:facgt Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2129=0b101110110 & b_1015=0b001011 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_facgt(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.49 FADD (vector) page C7-2119 line 123409 MATCH x0e20d400/mask=xbfa0fc00 +# CONSTRUCT x4e60d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2@8 +# AUNIT --inst x4e60d400/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround" + +:fadd Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1a & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + # simd infix Rd_VPR128.2D = Rn_VPR128.2D f+ Rm_VPR128.2D on lane size 8 + Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] f+ Rm_VPR128.2D[0,64]; + Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] f+ Rm_VPR128.2D[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.49 FADD (vector) page C7-2119 line 123409 MATCH x0e20d400/mask=xbfa0fc00 +# CONSTRUCT x0e20d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2@4 +# AUNIT --inst x0e20d400/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround" + +:fadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1a & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + # simd infix Rd_VPR64.2S = Rn_VPR64.2S f+ Rm_VPR64.2S on lane size 4 + Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] f+ Rm_VPR64.2S[0,32]; + Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] f+ Rm_VPR64.2S[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.49 FADD (vector) page C7-2119 line 123409 MATCH x0e20d400/mask=xbfa0fc00 +# CONSTRUCT x4e20d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2@4 +# AUNIT --inst x4e20d400/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround" + +:fadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1a & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd infix Rd_VPR128.4S = Rn_VPR128.4S f+ Rm_VPR128.4S on lane size 4 + Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] f+ Rm_VPR128.4S[0,32]; + Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] f+ Rm_VPR128.4S[32,32]; + Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] f+ Rm_VPR128.4S[64,32]; + Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] f+ Rm_VPR128.4S[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.49 FADD (vector) page C7-2119 line 123409 MATCH x0e401400/mask=xbfe0fc00 +# CONSTRUCT x0e401400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2@2 +# AUNIT --inst x0e401400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision SIMD 4H when Q=0 + +:fadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b000101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + # simd infix Rd_VPR64.4H = Rn_VPR64.4H f+ Rm_VPR64.4H on lane size 2 + Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f+ Rm_VPR64.4H[0,16]; + Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f+ Rm_VPR64.4H[16,16]; + Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f+ Rm_VPR64.4H[32,16]; + Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f+ Rm_VPR64.4H[48,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.49 FADD (vector) page C7-2119 line 123409 MATCH x0e401400/mask=xbfe0fc00 +# CONSTRUCT x4e401400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2@2 +# AUNIT --inst x4e401400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision SIMD 8H when Q=1 + +:fadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b000101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + # simd infix Rd_VPR128.8H = Rn_VPR128.8H f+ Rm_VPR128.8H on lane size 2 + Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f+ Rm_VPR128.8H[0,16]; + Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f+ Rm_VPR128.8H[16,16]; + Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f+ Rm_VPR128.8H[32,16]; + Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f+ Rm_VPR128.8H[48,16]; + Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f+ Rm_VPR128.8H[64,16]; + Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f+ Rm_VPR128.8H[80,16]; + Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f+ Rm_VPR128.8H[96,16]; + Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f+ Rm_VPR128.8H[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.50 FADD (scalar) page C7-2121 line 123531 MATCH x1e202800/mask=xff20fc00 +# CONSTRUCT x1e602800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =f+ +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2 +# AUNIT --inst x1e602800/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround" + +:fadd Rd_FPR64, Rn_FPR64, Rm_FPR64 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x2 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = Rn_FPR64 f+ Rm_FPR64; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.50 FADD (scalar) page C7-2121 line 123531 MATCH x1e202800/mask=xff20fc00 +# CONSTRUCT x1ee02800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =f+ +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2 +# AUNIT --inst x1ee02800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" + +:fadd Rd_FPR16, Rn_FPR16, Rm_FPR16 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x2 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = Rn_FPR16 f+ Rm_FPR16; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.50 FADD (scalar) page C7-2121 line 123531 MATCH x1e202800/mask=xff20fc00 +# CONSTRUCT x1e202800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =f+ +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2 +# AUNIT --inst x1e202800/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround" + +:fadd Rd_FPR32, Rn_FPR32, Rm_FPR32 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x2 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = Rn_FPR32 f+ Rm_FPR32; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.51 FADDP (scalar) page C7-2123 line 123639 MATCH x7e30d800/mask=xffbffc00 +# CONSTRUCT x7e70d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =#f+ +# SMACRO(pseudo) ARG1 ARG2 =NEON_faddp/1@8 +# AUNIT --inst x7e70d800/mask=xfffffc00 --rand dfp --status pass --comment "nofpround" + +:faddp Rd_FPR64, Rn_VPR128.2D +is b_3031=1 & u=1 & b_2428=0x1e & b_23=0 & b_1722=0x38 & b_1216=0xd & b_1011=2 & Rn_VPR128.2D & Rd_FPR64 & Zd +{ + # sipd infix Rd_FPR64 = f+(Rn_VPR128.2D) on pairs lane size (8 to 8) + local tmp1 = Rn_VPR128.2D[0,64]; + local tmp2 = Rn_VPR128.2D[64,64]; + Rd_FPR64 = tmp1 f+ tmp2; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.51 FADDP (scalar) page C7-2123 line 123639 MATCH x7e30d800/mask=xffbffc00 +# CONSTRUCT x7e30d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =#f+ +# SMACRO(pseudo) ARG1 ARG2 =NEON_faddp/1@4 +# AUNIT --inst x7e30d800/mask=xfffffc00 --rand sfp --status pass --comment "nofpround" + +:faddp Rd_FPR32, Rn_VPR64.2S +is b_3031=1 & u=1 & b_2428=0x1e & b_23=0 & b_1722=0x18 & b_1216=0xd & b_1011=2 & Rn_VPR64.2S & Rd_FPR32 & Zd +{ + # sipd infix Rd_FPR32 = f+(Rn_VPR64.2S) on pairs lane size (4 to 4) + local tmp1 = Rn_VPR64.2S[0,32]; + local tmp2 = Rn_VPR64.2S[32,32]; + Rd_FPR32 = tmp1 f+ tmp2; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.51 FADDP (scalar) page C7-2123 line 123639 MATCH x5e30d800/mask=xffbffc00 +# CONSTRUCT x5e30d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 Rn_FPR32 =#f+@2 +# SMACRO(pseudo) ARG1 Rn_FPR32 =NEON_faddp/1@2 +# AUNIT --inst x5e30d800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant + +:faddp Rd_FPR16, vRn_VPR128^".2H" +is b_1031=0b0101111000110000110110 & Rd_FPR16 & vRn_VPR128 & Rn_FPR32 & Zd +{ + # sipd infix Rd_FPR16 = f+(Rn_FPR32) on pairs lane size (2 to 2) + local tmp1 = Rn_FPR32[0,16]; + local tmp2 = Rn_FPR32[16,16]; + Rd_FPR16 = tmp1 f+ tmp2; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.52 FADDP (vector) page C7-2125 line 123747 MATCH x2e20d400/mask=xbfa0fc00 +# CONSTRUCT x6e60d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 var:16 ARG2 ARG3 =#f+/2 = +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_faddp/2@8 +# AUNIT --inst x6e60d400/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround" + +:faddp Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1a & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + TMPQ1 = 0; + # sipd infix TMPQ1 = f+(Rn_VPR128.2D,Rm_VPR128.2D) on pairs lane size (8 to 8) + local tmp2 = Rn_VPR128.2D[0,64]; + local tmp3 = Rn_VPR128.2D[64,64]; + TMPQ1[0,64] = tmp2 f+ tmp3; + tmp2 = Rm_VPR128.2D[0,64]; + tmp3 = Rm_VPR128.2D[64,64]; + TMPQ1[64,64] = tmp2 f+ tmp3; + Rd_VPR128.2D = TMPQ1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.52 FADDP (vector) page C7-2125 line 123747 MATCH x2e20d400/mask=xbfa0fc00 +# CONSTRUCT x2e20d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 var:8 ARG2 ARG3 =#f+/2 = +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_faddp/2@4 +# AUNIT --inst x2e20d400/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround" + +:faddp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1a & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + TMPD1 = 0; + # sipd infix TMPD1 = f+(Rn_VPR64.2S,Rm_VPR64.2S) on pairs lane size (4 to 4) + local tmp2 = Rn_VPR64.2S[0,32]; + local tmp3 = Rn_VPR64.2S[32,32]; + TMPD1[0,32] = tmp2 f+ tmp3; + tmp2 = Rm_VPR64.2S[0,32]; + tmp3 = Rm_VPR64.2S[32,32]; + TMPD1[32,32] = tmp2 f+ tmp3; + Rd_VPR64.2S = TMPD1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.52 FADDP (vector) page C7-2125 line 123747 MATCH x2e20d400/mask=xbfa0fc00 +# CONSTRUCT x6e20d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 var:16 ARG2 ARG3 =#f+/2 = +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_faddp/2@4 +# AUNIT --inst x6e20d400/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround" + +:faddp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1a & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + TMPQ1 = 0; + # sipd infix TMPQ1 = f+(Rn_VPR128.4S,Rm_VPR128.4S) on pairs lane size (4 to 4) + local tmp2 = Rn_VPR128.4S[0,32]; + local tmp3 = Rn_VPR128.4S[32,32]; + TMPQ1[0,32] = tmp2 f+ tmp3; + tmp2 = Rn_VPR128.4S[64,32]; + tmp3 = Rn_VPR128.4S[96,32]; + TMPQ1[32,32] = tmp2 f+ tmp3; + tmp2 = Rm_VPR128.4S[0,32]; + tmp3 = Rm_VPR128.4S[32,32]; + TMPQ1[64,32] = tmp2 f+ tmp3; + tmp2 = Rm_VPR128.4S[64,32]; + tmp3 = Rm_VPR128.4S[96,32]; + TMPQ1[96,32] = tmp2 f+ tmp3; + Rd_VPR128.4S = TMPQ1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.52 FADDP (vector) page C7-2125 line 123747 MATCH x2e401400/mask=xbfe0fc00 +# CONSTRUCT x2e401400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 var:8 ARG3 ARG2 =#f+/2 = +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_faddp/2@2 +# AUNIT --inst x2e401400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision SIMD 4H when Q = 0 + +:faddp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b000101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + TMPD1 = 0; + # sipd infix TMPD1 = f+(Rm_VPR64.4H,Rn_VPR64.4H) on pairs lane size (2 to 2) + local tmp2 = Rm_VPR64.4H[0,16]; + local tmp3 = Rm_VPR64.4H[16,16]; + TMPD1[0,16] = tmp2 f+ tmp3; + tmp2 = Rm_VPR64.4H[32,16]; + tmp3 = Rm_VPR64.4H[48,16]; + TMPD1[16,16] = tmp2 f+ tmp3; + tmp2 = Rn_VPR64.4H[0,16]; + tmp3 = Rn_VPR64.4H[16,16]; + TMPD1[32,16] = tmp2 f+ tmp3; + tmp2 = Rn_VPR64.4H[32,16]; + tmp3 = Rn_VPR64.4H[48,16]; + TMPD1[48,16] = tmp2 f+ tmp3; + Rd_VPR64.4H = TMPD1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.52 FADDP (vector) page C7-2125 line 123747 MATCH x2e401400/mask=xbfe0fc00 +# CONSTRUCT x6e401400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 var:16 ARG2 ARG3 =#f+/2 = +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_faddp/2@2 +# AUNIT --inst x6e401400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision SIMD 8H when Q = 1 + +:faddp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b000101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + TMPQ1 = 0; + # sipd infix TMPQ1 = f+(Rn_VPR128.8H,Rm_VPR128.8H) on pairs lane size (2 to 2) + local tmp2 = Rn_VPR128.8H[0,16]; + local tmp3 = Rn_VPR128.8H[16,16]; + TMPQ1[0,16] = tmp2 f+ tmp3; + tmp2 = Rn_VPR128.8H[32,16]; + tmp3 = Rn_VPR128.8H[48,16]; + TMPQ1[16,16] = tmp2 f+ tmp3; + tmp2 = Rn_VPR128.8H[64,16]; + tmp3 = Rn_VPR128.8H[80,16]; + TMPQ1[32,16] = tmp2 f+ tmp3; + tmp2 = Rn_VPR128.8H[96,16]; + tmp3 = Rn_VPR128.8H[112,16]; + TMPQ1[48,16] = tmp2 f+ tmp3; + tmp2 = Rm_VPR128.8H[0,16]; + tmp3 = Rm_VPR128.8H[16,16]; + TMPQ1[64,16] = tmp2 f+ tmp3; + tmp2 = Rm_VPR128.8H[32,16]; + tmp3 = Rm_VPR128.8H[48,16]; + TMPQ1[80,16] = tmp2 f+ tmp3; + tmp2 = Rm_VPR128.8H[64,16]; + tmp3 = Rm_VPR128.8H[80,16]; + TMPQ1[96,16] = tmp2 f+ tmp3; + tmp2 = Rm_VPR128.8H[96,16]; + tmp3 = Rm_VPR128.8H[112,16]; + TMPQ1[112,16] = tmp2 f+ tmp3; + Rd_VPR128.8H = TMPQ1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.46 FCADD page C7-1090 line 63037 KEEPWITH + +fcadd_rotate: #90 is b_12=0 { export 90:1; } +fcadd_rotate: #270 is b_12=1 { export 270:1; } + +# C7.2.53 FCADD page C7-2127 line 123874 MATCH x2e00e400/mask=xbf20ec00 +# CONSTRUCT x2e40e400/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcadd/3@2 +# AUNIT --inst x2e40e400/mask=xffe0ec00 --rand hfp --status noqemu --comment "nofpround" +# FCADD SIMD 4H when size = 01 , Q = 0 + +:fcadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H, fcadd_rotate +is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_21=0 & b_1315=0b111 & b_1011=0b01 & fcadd_rotate & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_fcadd(Rn_VPR64.4H, Rm_VPR64.4H, fcadd_rotate, 2:1); +} + +# C7.2.53 FCADD page C7-2127 line 123874 MATCH x2e00e400/mask=xbf20ec00 +# CONSTRUCT x6e40e400/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcadd/3@2 +# AUNIT --inst x6e40e400/mask=xffe0ec00 --rand hfp --status noqemu --comment "nofpround" +# FCADD SIMD 8H when size = 01 , Q = 1 + +:fcadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H, fcadd_rotate +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_21=0 & b_1315=0b111 & b_1011=0b01 & fcadd_rotate & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_fcadd(Rn_VPR128.8H, Rm_VPR128.8H, fcadd_rotate, 2:1); +} + +# C7.2.53 FCADD page C7-2127 line 123874 MATCH x2e00e400/mask=xbf20ec00 +# CONSTRUCT x2e80e400/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcadd/3@4 +# AUNIT --inst x2e80e400/mask=xffe0ec00 --rand sfp --status noqemu --comment "nofpround" +# FCADD SIMD 2S when size = 10 , Q = 0 + +:fcadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S, fcadd_rotate +is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_21=0 & b_1315=0b111 & b_1011=0b01 & fcadd_rotate & Rd_VPR64.2S & Rn_VPR64.2S & Rm_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_fcadd(Rn_VPR64.2S, Rm_VPR64.2S, fcadd_rotate, 4:1); +} + +# C7.2.53 FCADD page C7-2127 line 123874 MATCH x2e00e400/mask=xbf20ec00 +# CONSTRUCT x6e80e400/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcadd/3@4 +# AUNIT --inst x6e80e400/mask=xffe0ec00 --rand sfp --status noqemu --comment "nofpround" +# FCADD SIMD 4S when size = 10 , Q = 1 + +:fcadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, fcadd_rotate +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_21=0 & b_1315=0b111 & b_1011=0b01 & fcadd_rotate & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_fcadd(Rn_VPR128.4S, Rm_VPR128.4S, fcadd_rotate, 4:1); +} + +# C7.2.53 FCADD page C7-2127 line 123874 MATCH x2e00e400/mask=xbf20ec00 +# CONSTRUCT x6ec0e400/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcadd/3@8 +# AUNIT --inst x6ec0e400/mask=xffe0ec00 --rand dfp --status noqemu --comment "nofpround" +# FCADD SIMD 2D when size = 11 , Q = 1 + +:fcadd Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D, fcadd_rotate +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b11 & b_21=0 & b_1315=0b111 & b_1011=0b01 & fcadd_rotate & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_fcadd(Rn_VPR128.2D, Rm_VPR128.2D, fcadd_rotate, 8:1); +} + +# C7.2.54 FCCMP page C7-2129 line 123987 MATCH x1e200400/mask=xff200c10 +# CONSTRUCT x1e600400/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES +# SMACRO null ARG3:1 =setCC_NZCV/1 ARG4:1 ! inst_next goto null ARG1 ARG2 =fcomp/2 +# SMACRO(pseudo) null ARG1 ARG2 ARG3:1 ARG4:1 =NEON_fccmp/4 +# AUNIT --inst x1e600400/mask=xffe00c10 --rand dfp --status nodest --comment "flags" + +:fccmp Rn_FPR64, Rm_FPR64, NZCVImm_uimm4, CondOp +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & CondOp & b_1011=1 & Rn_FPR64 & fpccmp.op=0 & NZCVImm_uimm4 +{ + setCC_NZCV(NZCVImm_uimm4:1); + local tmp1:1 = ! CondOp:1; + if (tmp1) goto inst_next; + fcomp(Rn_FPR64, Rm_FPR64); +} + +# C7.2.54 FCCMP page C7-2129 line 123987 MATCH x1e200400/mask=xff200c10 +# CONSTRUCT x1e200400/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES +# SMACRO null ARG3:1 =setCC_NZCV/1 ARG4:1 ! inst_next goto null ARG1 ARG2 =fcomp/2 +# SMACRO(pseudo) null ARG1 ARG2 ARG3:1 ARG4:1 =NEON_fccmp/4 +# AUNIT --inst x1e200400/mask=xffe00c10 --rand sfp --status nodest --comment "flags" + +:fccmp Rn_FPR32, Rm_FPR32, NZCVImm_uimm4, CondOp +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & CondOp & b_1011=1 & Rn_FPR32 & fpccmp.op=0 & NZCVImm_uimm4 +{ + setCC_NZCV(NZCVImm_uimm4:1); + local tmp1:1 = ! CondOp:1; + if (tmp1) goto inst_next; + fcomp(Rn_FPR32, Rm_FPR32); +} + +# C7.2.54 FCCMP page C7-2129 line 123987 MATCH x1e200400/mask=xff200c10 +# CONSTRUCT x1ee00400/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES +# SMACRO null ARG3:1 =setCC_NZCV/1 ARG4:1 ! inst_next goto null ARG1 ARG2 =fcomp/2 +# SMACRO(pseudo) null ARG1 ARG2 ARG3:1 ARG4:1 =NEON_fccmp/4 +# AUNIT --inst x1ee00400/mask=xffe00c10 --rand hfp --status nodest --comment "flags" + +:fccmp Rn_FPR16, Rm_FPR16, NZCVImm_uimm4, CondOp +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & CondOp & b_1011=1 & Rn_FPR16 & fpccmp.op=0 & NZCVImm_uimm4 +{ + setCC_NZCV(NZCVImm_uimm4:1); + local tmp1:1 = ! CondOp:1; + if (tmp1) goto inst_next; + fcomp(Rn_FPR16, Rm_FPR16); +} + +# C7.2.55 FCCMPE page C7-2131 line 124107 MATCH x1e200410/mask=xff200c10 +# CONSTRUCT x1e600410/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES +# SMACRO null ARG3:1 =setCC_NZCV/1 ARG4:1 ! inst_next goto null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2 +# SMACRO(pseudo) null ARG1 ARG2 ARG3:1 ARG4:1 =NEON_fccmpe/4 +# AUNIT --inst x1e600410/mask=xffe00c10 --rand dfp --status nodest --comment "flags" + +:fccmpe Rn_FPR64, Rm_FPR64, NZCVImm_uimm4, CondOp +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & CondOp & b_1011=1 & Rn_FPR64 & fpccmp.op=1 & NZCVImm_uimm4 +{ + setCC_NZCV(NZCVImm_uimm4:1); + local tmp1:1 = ! CondOp:1; + if (tmp1) goto inst_next; + ftestNAN(Rn_FPR64, Rm_FPR64); + fcomp(Rn_FPR64, Rm_FPR64); +} + +# C7.2.55 FCCMPE page C7-2131 line 124107 MATCH x1e200410/mask=xff200c10 +# CONSTRUCT x1e200410/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES +# SMACRO null ARG3:1 =setCC_NZCV/1 ARG4:1 ! inst_next goto null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2 +# SMACRO(pseudo) null ARG1 ARG2 ARG3:1 ARG4:1 =NEON_fccmpe/4 +# AUNIT --inst x1e200410/mask=xffe00c10 --rand sfp --status nodest --comment "flags" + +:fccmpe Rn_FPR32, Rm_FPR32, NZCVImm_uimm4, CondOp +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & CondOp & b_1011=1 & Rn_FPR32 & fpccmp.op=1 & NZCVImm_uimm4 +{ + setCC_NZCV(NZCVImm_uimm4:1); + local tmp1:1 = ! CondOp:1; + if (tmp1) goto inst_next; + ftestNAN(Rn_FPR32, Rm_FPR32); + fcomp(Rn_FPR32, Rm_FPR32); +} + +# C7.2.55 FCCMPE page C7-2131 line 124107 MATCH x1e200410/mask=xff200c10 +# CONSTRUCT x1ee00410/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES +# SMACRO null ARG3:1 =setCC_NZCV/1 ARG4:1 ! inst_next goto null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2 +# SMACRO(pseudo) null ARG1 ARG2 ARG3:1 ARG4:1 =NEON_fccmpe/4 +# AUNIT --inst x1ee00410/mask=xffe00c10 --rand hfp --status nodest --comment "flags" + +:fccmpe Rn_FPR16, Rm_FPR16, NZCVImm_uimm4, CondOp +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & CondOp & b_1011=1 & Rn_FPR16 & fpccmp.op=1 & NZCVImm_uimm4 +{ + setCC_NZCV(NZCVImm_uimm4:1); + local tmp1:1 = ! CondOp:1; + if (tmp1) goto inst_next; + ftestNAN(Rn_FPR16, Rm_FPR16); + fcomp(Rn_FPR16, Rm_FPR16); +} + +# C7.2.56 FCMEQ (register) page C7-2133 line 124227 MATCH x0e20e400/mask=xbfa0fc00 +# CONSTRUCT x4e60e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2@8 +# AUNIT --inst x4e60e400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "noflags" + +:fcmeq Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1c & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_fcmeq(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.56 FCMEQ (register) page C7-2133 line 124227 MATCH x0e20e400/mask=xbfa0fc00 +# CONSTRUCT x0e20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2@4 +# AUNIT --inst x0e20e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags" + +:fcmeq Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1c & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_fcmeq(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.56 FCMEQ (register) page C7-2133 line 124227 MATCH x0e20e400/mask=xbfa0fc00 +# CONSTRUCT x4e20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2@4 +# AUNIT --inst x4e20e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags" + +:fcmeq Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1c & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_fcmeq(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.56 FCMEQ (register) page C7-2133 line 124227 MATCH x5e402400/mask=xffe0fc00 +# CONSTRUCT x5e402400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2 +# AUNIT --inst x5e402400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags" +# Scalar half precision variant + +:fcmeq Rd_FPR16, Rn_FPR16, Rm_FPR16 +is b_2131=0b01011110010 & b_1015=0b001001 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd +{ + Rd_FPR16 = NEON_fcmeq(Rn_FPR16, Rm_FPR16); +} + +# C7.2.56 FCMEQ (register) page C7-2133 line 124227 MATCH x5e20e400/mask=xffa0fc00 +# CONSTRUCT x5e20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2 +# AUNIT --inst x5e20e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags" +# Scalar single-precision and double-precision variant sz=0 + +:fcmeq Rd_FPR32, Rn_FPR32, Rm_FPR32 +is b_2331=0b010111100 & b_22=0 & b_21=1 & b_1015=0b111001 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd +{ + Rd_FPR32 = NEON_fcmeq(Rn_FPR32, Rm_FPR32); +} + +# C7.2.56 FCMEQ (register) page C7-2133 line 124227 MATCH x5e20e400/mask=xffa0fc00 +# CONSTRUCT x5e60e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2 +# AUNIT --inst x5e60e400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "noflags" +# Scalar single-precision and double-precision variant sz=1 + +:fcmeq Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_2331=0b010111100 & b_22=1 & b_21=1 & b_1015=0b111001 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd +{ + Rd_FPR64 = NEON_fcmeq(Rn_FPR64, Rm_FPR64); +} + +# C7.2.56 FCMEQ (register) page C7-2133 line 124227 MATCH x0e402400/mask=xbfe0fc00 +# CONSTRUCT x0e402400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2@2 +# AUNIT --inst x0e402400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags" +# Vector half precision variant SIMD 4H when Q=0 + +:fcmeq Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b001001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_fcmeq(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.56 FCMEQ (register) page C7-2133 line 124227 MATCH x0e402400/mask=xbfe0fc00 +# CONSTRUCT x4e402400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2@2 +# AUNIT --inst x4e402400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags" +# Vector half precision variant SIMD 8H when Q=1 + +:fcmeq Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b001001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_fcmeq(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.57 FCMEQ (zero) page C7-2137 line 124475 MATCH x0ea0d800/mask=xbfbffc00 +# CONSTRUCT x4ee0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmeq/2@8 +# AUNIT --inst x4ee0d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags" + +:fcmeq Rd_VPR128.2D, Rn_VPR128.2D, "#0" +is b_3131=0 & q=1 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x30 & b_1216=0xd & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_fcmeq(Rn_VPR128.2D, 0:8, 8:1); +} + +# C7.2.57 FCMEQ (zero) page C7-2137 line 124475 MATCH x0ea0d800/mask=xbfbffc00 +# CONSTRUCT x0ea0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmeq/2@4 +# AUNIT --inst x0ea0d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags" + +:fcmeq Rd_VPR64.2S, Rn_VPR64.2S, "#0" +is b_3131=0 & q=0 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xd & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_fcmeq(Rn_VPR64.2S, 0:4, 4:1); +} + +# C7.2.57 FCMEQ (zero) page C7-2137 line 124475 MATCH x0ea0d800/mask=xbfbffc00 +# CONSTRUCT x4ea0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmeq/2@4 +# AUNIT --inst x4ea0d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags" + +:fcmeq Rd_VPR128.4S, Rn_VPR128.4S, "#0" +is b_3131=0 & q=1 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xd & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_fcmeq(Rn_VPR128.4S, 0:4, 4:1); +} + +# C7.2.57 FCMEQ (zero) page C7-2137 line 124475 MATCH x5ef8d800/mask=xfffffc00 +# CONSTRUCT x5ef8d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmeq/2 +# AUNIT --inst x5ef8d800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags" +# Scalar half precision variant + +:fcmeq Rd_FPR16, Rn_FPR16, "#0.0" +is b_1031=0b0101111011111000110110 & Rd_FPR16 & Rn_FPR16 & Zd +{ + Rd_FPR16 = NEON_fcmeq(Rn_FPR16, 0:2); +} + +# C7.2.57 FCMEQ (zero) page C7-2137 line 124475 MATCH x5ea0d800/mask=xffbffc00 +# CONSTRUCT x5ea0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmeq/2 +# AUNIT --inst x5ea0d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags" +# Scalar single-precision and double-precision sz=0 + +:fcmeq Rd_FPR32, Rn_FPR32, "#0.0" +is b_2331=0b010111101 & b_22=0 & b_1021=0b100000110110 & Rd_FPR32 & Rn_FPR32 & Zd +{ + Rd_FPR32 = NEON_fcmeq(Rn_FPR32, 0:4); +} + +# C7.2.57 FCMEQ (zero) page C7-2137 line 124475 MATCH x5ea0d800/mask=xffbffc00 +# CONSTRUCT x5ee0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmeq/2 +# AUNIT --inst x5ee0d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags" +# Scalar single-precision and double-precision sz=1 + +:fcmeq Rd_FPR64, Rn_FPR64, "#0.0" +is b_2331=0b010111101 & b_22=1 & b_1021=0b100000110110 & Rd_FPR64 & Rn_FPR64 & Zd +{ + Rd_FPR64 = NEON_fcmeq(Rn_FPR64, 0:8); +} + +# C7.2.57 FCMEQ (zero) page C7-2137 line 124475 MATCH x0ef8d800/mask=xbffffc00 +# CONSTRUCT x0ef8d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmeq/2@2 +# AUNIT --inst x0ef8d800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags" +# Vector half precision variant SIMD 4H when Q = 0 + +:fcmeq Rd_VPR64.4H, Rn_VPR64.4H, "#0.0" +is b_31=0 & b_30=0 & b_1029=0b00111011111000110110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_fcmeq(Rn_VPR64.4H, 0:2, 2:1); +} + +# C7.2.57 FCMEQ (zero) page C7-2137 line 124475 MATCH x0ef8d800/mask=xbffffc00 +# CONSTRUCT x4ef8d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmeq/2@2 +# AUNIT --inst x4ef8d800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags" +# Vector half precision variant SIMD 8H when Q = 1 + +:fcmeq Rd_VPR128.8H, Rn_VPR128.8H, "#0.0" +is b_31=0 & b_30=1 & b_1029=0b00111011111000110110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_fcmeq(Rn_VPR128.8H, 0:2, 2:1); +} + +# C7.2.58 FCMGE (register) page C7-2140 line 124691 MATCH x2e20e400/mask=xbfa0fc00 +# CONSTRUCT x6e60e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2@8 +# AUNIT --inst x6e60e400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "noflags" + +:fcmge Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1c & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_fcmge(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.58 FCMGE (register) page C7-2140 line 124691 MATCH x2e20e400/mask=xbfa0fc00 +# CONSTRUCT x2e20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2@4 +# AUNIT --inst x2e20e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags" + +:fcmge Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1c & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_fcmge(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.58 FCMGE (register) page C7-2140 line 124691 MATCH x2e20e400/mask=xbfa0fc00 +# CONSTRUCT x6e20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2@4 +# AUNIT --inst x6e20e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags" + +:fcmge Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1c & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_fcmge(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.58 FCMGE (register) page C7-2140 line 124691 MATCH x7e402400/mask=xffe0fc00 +# CONSTRUCT x7e402400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2 +# AUNIT --inst x7e402400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags" +# Scalar half precision variant + +:fcmge Rd_FPR16, Rn_FPR16, Rm_FPR16 +is b_2131=0b01111110010 & b_1015=0b001001 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd +{ + Rd_FPR16 = NEON_fcmge(Rn_FPR16, Rm_FPR16); +} + +# C7.2.58 FCMGE (register) page C7-2140 line 124691 MATCH x7e20e400/mask=xffa0fc00 +# CONSTRUCT x7e20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2 +# AUNIT --inst x7e20e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags" +# Scalar single-precision and double-precision variant sz=0 + +:fcmge Rd_FPR32, Rn_FPR32, Rm_FPR32 +is b_2331=0b011111100 & b_22=0 & b_21=1 & b_1015=0b111001 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd +{ + Rd_FPR32 = NEON_fcmge(Rn_FPR32, Rm_FPR32); +} + +# C7.2.58 FCMGE (register) page C7-2140 line 124691 MATCH x7e20e400/mask=xffa0fc00 +# CONSTRUCT x7e60e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2 +# AUNIT --inst x7e60e400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "noflags" +# Scalar single-precision and double-precision variant sz=1 + +:fcmge Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_2331=0b011111100 & b_22=1 & b_21=1 & b_1015=0b111001 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd +{ + Rd_FPR64 = NEON_fcmge(Rn_FPR64, Rm_FPR64); +} + +# C7.2.58 FCMGE (register) page C7-2140 line 124691 MATCH x2e402400/mask=xbfe0fc00 +# CONSTRUCT x2e402400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2@2 +# AUNIT --inst x2e402400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags" +# Vector half precision variant SIMD 4H when Q = 0 + +:fcmge Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b001001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_fcmge(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.58 FCMGE (register) page C7-2140 line 124691 MATCH x2e402400/mask=xbfe0fc00 +# CONSTRUCT x6e402400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2@2 +# AUNIT --inst x6e402400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags" +# Vector half precision variant SIMD 8H when Q = 1 + +:fcmge Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b001001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_fcmge(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.59 FCMGE (zero) page C7-2144 line 124940 MATCH x2ea0c800/mask=xbfbffc00 +# CONSTRUCT x6ee0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmge/2@8 +# AUNIT --inst x6ee0c800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags" + +:fcmge Rd_VPR128.2D, Rn_VPR128.2D, "#0" +is b_3131=0 & q=1 & u=1 & b_2428=0xe & b_23=1 & b_1722=0x30 & b_1216=0xc & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_fcmge(Rn_VPR128.2D, 0:8, 8:1); +} + +# C7.2.59 FCMGE (zero) page C7-2144 line 124940 MATCH x2ea0c800/mask=xbfbffc00 +# CONSTRUCT x2ea0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmge/2@4 +# AUNIT --inst x2ea0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags" + +:fcmge Rd_VPR64.2S, Rn_VPR64.2S, "#0" +is b_3131=0 & q=0 & u=1 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xc & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_fcmge(Rn_VPR64.2S, 0:4, 4:1); +} + +# C7.2.59 FCMGE (zero) page C7-2144 line 124940 MATCH x2ea0c800/mask=xbfbffc00 +# CONSTRUCT x6ea0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmge/2@4 +# AUNIT --inst x6ea0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags" + +:fcmge Rd_VPR128.4S, Rn_VPR128.4S, "#0" +is b_3131=0 & q=1 & u=1 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xc & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_fcmge(Rn_VPR128.4S, 0:4, 4:1); +} + +# C7.2.59 FCMGE (zero) page C7-2144 line 124940 MATCH x7ef8c800/mask=xfffffc00 +# CONSTRUCT x7ef8c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmge/2 +# AUNIT --inst x7ef8c800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags" +# Scalar half precision variant + +:fcmge Rd_FPR16, Rn_FPR16, "#0.0" +is b_1031=0b0111111011111000110010 & Rd_FPR16 & Rn_FPR16 & Zd +{ + Rd_FPR16 = NEON_fcmge(Rn_FPR16, 0:2); +} + +# C7.2.59 FCMGE (zero) page C7-2144 line 124940 MATCH x7ea0c800/mask=xffbffc00 +# CONSTRUCT x7ea0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmge/2 +# AUNIT --inst x7ea0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags" +# Scalar single-precision and double-precision sz=0 + +:fcmge Rd_FPR32, Rn_FPR32, "#0.0" +is b_2331=0b011111101 & b_22=0 & b_1021=0b100000110010 & Rd_FPR32 & Rn_FPR32 & Zd +{ + Rd_FPR32 = NEON_fcmge(Rn_FPR32, 0:4); +} + +# C7.2.59 FCMGE (zero) page C7-2144 line 124940 MATCH x7ea0c800/mask=xffbffc00 +# CONSTRUCT x7ee0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmge/2 +# AUNIT --inst x7ee0c800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags" +# Scalar single-precision and double-precision sz=1 + +:fcmge Rd_FPR64, Rn_FPR64, "#0.0" +is b_2331=0b011111101 & b_22=1 & b_1021=0b100000110010 & Rd_FPR64 & Rn_FPR64 & Zd +{ + Rd_FPR64 = NEON_fcmge(Rn_FPR64, 0:8); +} + +# C7.2.59 FCMGE (zero) page C7-2144 line 124940 MATCH x2ef8c800/mask=xbffffc00 +# CONSTRUCT x2ef8c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmge/2@2 +# AUNIT --inst x2ef8c800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags" +# Vector half precision variant SIMD 4H when Q = 0 + +:fcmge Rd_VPR64.4H, Rn_VPR64.4H, "#0.0" +is b_31=0 & b_30=0 & b_1029=0b10111011111000110010 & Rd_VPR64.4H & Rn_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_fcmge(Rn_VPR64.4H, 0:2, 2:1); +} + +# C7.2.59 FCMGE (zero) page C7-2144 line 124940 MATCH x2ef8c800/mask=xbffffc00 +# CONSTRUCT x6ef8c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmge/2@2 +# AUNIT --inst x6ef8c800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags" +# Vector half precision variant SIMD 8H when Q = 1 + +:fcmge Rd_VPR128.8H, Rn_VPR128.8H, "#0.0" +is b_31=0 & b_30=1 & b_1029=0b10111011111000110010 & Rd_VPR128.8H & Rn_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_fcmge(Rn_VPR128.8H, 0:2, 2:1); +} + +# C7.2.60 FCMGT (register) page C7-2147 line 125156 MATCH x2ea0e400/mask=xbfa0fc00 +# CONSTRUCT x6ee0e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2@8 +# AUNIT --inst x6ee0e400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "noflags" + +:fcmgt Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x1c & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_fcmgt(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.60 FCMGT (register) page C7-2147 line 125156 MATCH x2ea0e400/mask=xbfa0fc00 +# CONSTRUCT x2ea0e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2@4 +# AUNIT --inst x2ea0e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags" + +:fcmgt Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x1c & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_fcmgt(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.60 FCMGT (register) page C7-2147 line 125156 MATCH x2ea0e400/mask=xbfa0fc00 +# CONSTRUCT x6ea0e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2@4 +# AUNIT --inst x6ea0e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags" + +:fcmgt Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x1c & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_fcmgt(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.60 FCMGT (register) page C7-2147 line 125156 MATCH x7ec02400/mask=xffe0fc00 +# CONSTRUCT x7ec02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2 +# AUNIT --inst x7ec02400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags" +# Scalar half precision variant + +:fcmgt Rd_FPR16, Rn_FPR16, Rm_FPR16 +is b_2131=0b01111110110 & b_1015=0b001001 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd +{ + Rd_FPR16 = NEON_fcmgt(Rn_FPR16, Rm_FPR16); +} + +# C7.2.60 FCMGT (register) page C7-2147 line 125156 MATCH x7ea0e400/mask=xffa0fc00 +# CONSTRUCT x7ea0e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2 +# AUNIT --inst x7ea0e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags" +# Scalar single-precision and double-precision variant sz=0 + +:fcmgt Rd_FPR32, Rn_FPR32, Rm_FPR32 +is b_2331=0b011111101 & b_22=0 & b_21=1 & b_1015=0b111001 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd +{ + Rd_FPR32 = NEON_fcmgt(Rn_FPR32, Rm_FPR32); +} + +# C7.2.60 FCMGT (register) page C7-2147 line 125156 MATCH x7ea0e400/mask=xffa0fc00 +# CONSTRUCT x7ee0e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2 +# AUNIT --inst x7ee0e400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "noflags" +# Scalar single-precision and double-precision variant sz=1 + +:fcmgt Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_2331=0b011111101 & b_22=1 & b_21=1 & b_1015=0b111001 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd +{ + Rd_FPR64 = NEON_fcmgt(Rn_FPR64, Rm_FPR64); +} + +# C7.2.60 FCMGT (register) page C7-2147 line 125156 MATCH x2ec02400/mask=xbfe0fc00 +# CONSTRUCT x2ec02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2@2 +# AUNIT --inst x2ec02400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags" +# Vector half precision variant SIMD 4H when Q = 0 + +:fcmgt Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2129=0b101110110 & b_1015=0b001001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_fcmgt(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.60 FCMGT (register) page C7-2147 line 125156 MATCH x2ec02400/mask=xbfe0fc00 +# CONSTRUCT x6ec02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2@2 +# AUNIT --inst x6ec02400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags" +# Vector half precision variant SIMD 8H when Q = 1 + +:fcmgt Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2129=0b101110110 & b_1015=0b001001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_fcmgt(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.61 FCMGT (zero) page C7-2151 line 125404 MATCH x0ea0c800/mask=xbfbffc00 +# CONSTRUCT x4ee0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmgt/2@8 +# AUNIT --inst x4ee0c800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags" + +:fcmgt Rd_VPR128.2D, Rn_VPR128.2D, "#0" +is b_3131=0 & q=1 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x30 & b_1216=0xc & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_fcmgt(Rn_VPR128.2D, 0:8, 8:1); +} + +# C7.2.61 FCMGT (zero) page C7-2151 line 125404 MATCH x0ea0c800/mask=xbfbffc00 +# CONSTRUCT x0ea0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmgt/2@4 +# AUNIT --inst x0ea0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags" + +:fcmgt Rd_VPR64.2S, Rn_VPR64.2S, "#0" +is b_3131=0 & q=0 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xc & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_fcmgt(Rn_VPR64.2S, 0:4, 4:1); +} + +# C7.2.61 FCMGT (zero) page C7-2151 line 125404 MATCH x0ea0c800/mask=xbfbffc00 +# CONSTRUCT x4ea0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmgt/2@4 +# AUNIT --inst x4ea0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags" + +:fcmgt Rd_VPR128.4S, Rn_VPR128.4S, "#0" +is b_3131=0 & q=1 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xc & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_fcmgt(Rn_VPR128.4S, 0:4, 4:1); +} + +# C7.2.61 FCMGT (zero) page C7-2151 line 125404 MATCH x5ef8c800/mask=xfffffc00 +# CONSTRUCT x5ef8c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmgt/2 +# AUNIT --inst x5ef8c800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags" +# Scalar half precision variant + +:fcmgt Rd_FPR16, Rn_FPR16, "#0.0" +is b_1031=0b0101111011111000110010 & Rd_FPR16 & Rn_FPR16 & Zd +{ + Rd_FPR16 = NEON_fcmgt(Rn_FPR16, 0:2); +} + +# C7.2.61 FCMGT (zero) page C7-2151 line 125404 MATCH x5ea0c800/mask=xffbffc00 +# CONSTRUCT x5ea0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmgt/2 +# AUNIT --inst x5ea0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags" +# Scalar single-precision and double-precision sz=0 + +:fcmgt Rd_FPR32, Rn_FPR32, "#0.0" +is b_2331=0b010111101 & b_22=0 & b_1021=0b100000110010 & Rd_FPR32 & Rn_FPR32 & Zd +{ + Rd_FPR32 = NEON_fcmgt(Rn_FPR32, 0:4); +} + +# C7.2.61 FCMGT (zero) page C7-2151 line 125404 MATCH x5ea0c800/mask=xffbffc00 +# CONSTRUCT x5ee0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmgt/2 +# AUNIT --inst x5ee0c800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags" +# Scalar single-precision and double-precision sz=1 + +:fcmgt Rd_FPR64, Rn_FPR64, "#0.0" +is b_2331=0b010111101 & b_22=1 & b_1021=0b100000110010 & Rd_FPR64 & Rn_FPR64 & Zd +{ + Rd_FPR64 = NEON_fcmgt(Rn_FPR64, 0:8); +} + +# C7.2.61 FCMGT (zero) page C7-2151 line 125404 MATCH x0ef8c800/mask=xbffffc00 +# CONSTRUCT x0ef8c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmgt/2@2 +# AUNIT --inst x0ef8c800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags" +# Vector half precision variant SIMD 4H when Q = 0 + +:fcmgt Rd_VPR64.4H, Rn_VPR64.4H, "#0.0" +is b_31=0 & b_30=0 & b_1029=0b00111011111000110010 & Rd_VPR64.4H & Rn_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_fcmgt(Rn_VPR64.4H, 0:2, 2:1); +} + +# C7.2.61 FCMGT (zero) page C7-2151 line 125404 MATCH x0ef8c800/mask=xbffffc00 +# CONSTRUCT x4ef8c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmgt/2@2 +# AUNIT --inst x4ef8c800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags" +# Vector half precision variant SIMD 8H when Q = 1 + +:fcmgt Rd_VPR128.8H, Rn_VPR128.8H, "#0.0" +is b_31=0 & b_30=1 & b_1029=0b00111011111000110010 & Rd_VPR128.8H & Rn_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_fcmgt(Rn_VPR128.8H, 0:2, 2:1); +} + +# C7.2.55 FCMLA (by element) page C7-1117 line 64749 KEEPWITH + +fcmla_rotate: #0 is b_15=0 & b_1314=0b00 { export 0:1; } +fcmla_rotate: #90 is b_15=0 & b_1314=0b01 { export 90:1; } +fcmla_rotate: #180 is b_15=0 & b_1314=0b10 { export 180:1; } +fcmla_rotate: #270 is b_15=0 & b_1314=0b11 { export 270:1; } +fcmla_rotate: #0 is b_15=1 & b_1112=0b00 { export 0:1; } +fcmla_rotate: #90 is b_15=1 & b_1112=0b01 { export 90:1; } +fcmla_rotate: #180 is b_15=1 & b_1112=0b10 { export 180:1; } +fcmla_rotate: #270 is b_15=1 & b_1112=0b11 { export 270:1; } + +# C7.2.62 FCMLA (by element) page C7-2154 line 125620 MATCH x2f001000/mask=xbf009400 +# CONSTRUCT x2f401000/mask=xffc09c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@2 +# AUNIT --inst x2f401000/mask=xffc09c00 --rand hfp --status noqemu --comment "noflags" +# The representation of Rm in the documentation as a 4 bit field +# extended by M actually makes it a standard 5 bit field. +# 4H variant when size = 01 , Q = 0 T=VPR64.4H imm=Re_VPR128.H.vIndexHL i1=Re_VPR128.H i2=vIndexHL +# NOTE: if size == '01' and H == '1' && Q == '0' then ReservedValue(); + +:fcmla Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128.H.vIndexHL, fcmla_rotate +is b_31=0 & b_30=0 & b_2429=0b101111 & b_2223=0b01 & b_15=0 & b_12=1 & b_11=0 & b_10=0 & fcmla_rotate & Rd_VPR64.4H & Rn_VPR64.4H & Re_VPR128.H.vIndexHL & Re_VPR128.H & vIndexHL & Zd +{ + local tmp1:2 = SIMD_PIECE(Re_VPR128.H, vIndexHL:1); + Rd_VPR64.4H = NEON_fcmla(Rn_VPR64.4H, tmp1, fcmla_rotate, 2:1); +} + +# C7.2.62 FCMLA (by element) page C7-2154 line 125620 MATCH x2f001000/mask=xbf009400 +# CONSTRUCT x6f401000/mask=xffc09400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@2 +# AUNIT --inst x6f401000/mask=xffc09400 --rand hfp --status noqemu --comment "noflags" +# 8H variant when size = 01 , Q = 1 T=VPR128.8H imm=Re_VPR128.H.vIndexHL i1=Re_VPR128.H i2=vIndexHL + +:fcmla Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128.H.vIndexHL, fcmla_rotate +is b_31=0 & b_30=1 & b_2429=0b101111 & b_2223=0b01 & b_15=0 & b_12=1 & b_10=0 & fcmla_rotate & Rd_VPR128.8H & Rn_VPR128.8H & Re_VPR128.H.vIndexHL & Re_VPR128.H & vIndexHL & Zd +{ + local tmp1:2 = SIMD_PIECE(Re_VPR128.H, vIndexHL:1); + Rd_VPR128.8H = NEON_fcmla(Rn_VPR128.8H, tmp1, fcmla_rotate, 2:1); +} + +# C7.2.62 FCMLA (by element) page C7-2154 line 125620 MATCH x2f001000/mask=xbf009400 +# CONSTRUCT x6f801000/mask=xffe09400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@4 +# AUNIT --inst x6f801000/mask=xffe09400 --rand sfp --status noqemu --comment "noflags" +# 4S variant when size = 10 , Q = 1 T=VPR128.4S imm=Re_VPR128.S.vIndex i1=Re_VPR128.S i2=vIndex +# NOTE: if size == '10' and (L == '1' || Q == '0') then ReservedValue(); + +:fcmla Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex, fcmla_rotate +is b_31=0 & b_30=1 & b_2429=0b101111 & b_2223=0b10 & b_21=0 & b_15=0 & b_12=1 & b_10=0 & fcmla_rotate & Rd_VPR128.4S & Rn_VPR128.4S & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Zd +{ + local tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1); + Rd_VPR128.4S = NEON_fcmla(Rn_VPR128.4S, tmp1, fcmla_rotate, 4:1); +} + +# C7.2.63 FCMLA page C7-2157 line 125798 MATCH x2e00c400/mask=xbf20e400 +# CONSTRUCT x2e40c400/mask=xffe0e400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@4 +# AUNIT --inst x2e40c400/mask=xffe0e400 --rand hfp --status noqemu --comment "noflags" +# FCMLA SIMD 4H when size = 01 , Q = 0 + +:fcmla Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H, fcmla_rotate +is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_21=0 & b_1315=0b110 & b_10=1 & fcmla_rotate & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_fcmla(Rn_VPR64.4H, Rm_VPR64.4H, fcmla_rotate, 4:1); +} + +# C7.2.63 FCMLA page C7-2157 line 125798 MATCH x2e00c400/mask=xbf20e400 +# CONSTRUCT x6e40c400/mask=xffe0e400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@4 +# AUNIT --inst x6e40c400/mask=xffe0e400 --rand hfp --status noqemu --comment "noflags" +# FCMLA SIMD 8H when size = 01 , Q = 1 + +:fcmla Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H, fcmla_rotate +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_21=0 & b_1315=0b110 & b_10=1 & fcmla_rotate & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_fcmla(Rn_VPR128.8H, Rm_VPR128.8H, fcmla_rotate, 4:1); +} + +# C7.2.63 FCMLA page C7-2157 line 125798 MATCH x2e00c400/mask=xbf20e400 +# CONSTRUCT x2e80c400/mask=xffe0e400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@4 +# AUNIT --inst x2e80c400/mask=xffe0e400 --rand sfp --status noqemu --comment "noflags" +# FCMLA SIMD 2S when size = 10 , Q = 0 + +:fcmla Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S, fcmla_rotate +is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_21=0 & b_1315=0b110 & b_10=1 & fcmla_rotate & Rd_VPR64.2S & Rn_VPR64.2S & Rm_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_fcmla(Rn_VPR64.2S, Rm_VPR64.2S, fcmla_rotate, 4:1); +} + +# C7.2.63 FCMLA page C7-2157 line 125798 MATCH x2e00c400/mask=xbf20e400 +# CONSTRUCT x6e80c400/mask=xffe0e400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@4 +# AUNIT --inst x6e80c400/mask=xffe0e400 --rand sfp --status noqemu --comment "noflags" +# FCMLA SIMD 4S when size = 10 , Q = 1 + +:fcmla Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, fcmla_rotate +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_21=0 & b_1315=0b110 & b_10=1 & fcmla_rotate & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_fcmla(Rn_VPR128.4S, Rm_VPR128.4S, fcmla_rotate, 4:1); +} + +# C7.2.63 FCMLA page C7-2157 line 125798 MATCH x2e00c400/mask=xbf20e400 +# CONSTRUCT x6ec0c400/mask=xffe0e400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@4 +# AUNIT --inst x6ec0c400/mask=xffe0e400 --rand dfp --status noqemu --comment "noflags" +# FCMLA SIMD 2D when size = 11 , Q = 1 + +:fcmla Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D, fcmla_rotate +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b11 & b_21=0 & b_1315=0b110 & b_10=1 & fcmla_rotate & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_fcmla(Rn_VPR128.2D, Rm_VPR128.2D, fcmla_rotate, 4:1); +} + +# C7.2.64 FCMLE (zero) page C7-2160 line 125952 MATCH x2ea0d800/mask=xbfbffc00 +# CONSTRUCT x6ee0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmle/2@8 +# AUNIT --inst x6ee0d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags" + +:fcmle Rd_VPR128.2D, Rn_VPR128.2D, "#0" +is b_3131=0 & q=1 & u=1 & b_2428=0xe & b_23=1 & b_1722=0x30 & b_1216=0xd & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_fcmle(Rn_VPR128.2D, 0:8, 8:1); +} + +# C7.2.64 FCMLE (zero) page C7-2160 line 125952 MATCH x2ea0d800/mask=xbfbffc00 +# CONSTRUCT x2ea0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmle/2@2 +# AUNIT --inst x2ea0d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags" + +:fcmle Rd_VPR64.2S, Rn_VPR64.2S, "#0" +is b_3131=0 & q=0 & u=1 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xd & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_fcmle(Rn_VPR64.2S, 0:2, 2:1); +} + +# C7.2.64 FCMLE (zero) page C7-2160 line 125952 MATCH x2ea0d800/mask=xbfbffc00 +# CONSTRUCT x6ea0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmle/2@4 +# AUNIT --inst x6ea0d800/mask=xfffffc00 --rand sfp --status nopcodeop + +:fcmle Rd_VPR128.4S, Rn_VPR128.4S, "#0" +is b_3131=0 & q=1 & u=1 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xd & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_fcmle(Rn_VPR128.4S, 0:4, 4:1); +} + +# C7.2.64 FCMLE (zero) page C7-2160 line 125952 MATCH x7ef8d800/mask=xfffffc00 +# CONSTRUCT x7ef8d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmle/2 +# AUNIT --inst x7ef8d800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags" +# Scalar half precision variant + +:fcmle Rd_FPR16, Rn_FPR16, "#0.0" +is b_1031=0b0111111011111000110110 & Rd_FPR16 & Rn_FPR16 & Zd +{ + Rd_FPR16 = NEON_fcmle(Rn_FPR16, 0:2); +} + +# C7.2.64 FCMLE (zero) page C7-2160 line 125952 MATCH x7ea0d800/mask=xffbffc00 +# CONSTRUCT x7ea0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmle/2 +# AUNIT --inst x7ea0d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags" +# Scalar single-precision and double-precision sz=0 + +:fcmle Rd_FPR32, Rn_FPR32, "#0.0" +is b_2331=0b011111101 & b_22=0 & b_1021=0b100000110110 & Rd_FPR32 & Rn_FPR32 & Zd +{ + Rd_FPR32 = NEON_fcmle(Rn_FPR32, 0:4); +} + +# C7.2.64 FCMLE (zero) page C7-2160 line 125952 MATCH x7ea0d800/mask=xffbffc00 +# CONSTRUCT x7ee0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmle/2 +# AUNIT --inst x7ee0d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags" +# Scalar single-precision and double-precision sz=1 + +:fcmle Rd_FPR64, Rn_FPR64, "#0.0" +is b_2331=0b011111101 & b_22=1 & b_1021=0b100000110110 & Rd_FPR64 & Rn_FPR64 & Zd +{ + Rd_FPR64 = NEON_fcmle(Rn_FPR64, 0:8); +} + +# C7.2.64 FCMLE (zero) page C7-2160 line 125952 MATCH x2ef8d800/mask=xbffffc00 +# CONSTRUCT x2ef8d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmle/2@2 +# AUNIT --inst x2ef8d800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags" +# Vector half precision variant SIMD 4H when Q = 0 + +:fcmle Rd_VPR64.4H, Rn_VPR64.4H, "#0.0" +is b_31=0 & b_30=0 & b_1029=0b10111011111000110110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_fcmle(Rn_VPR64.4H, 0:2, 2:1); +} + +# C7.2.64 FCMLE (zero) page C7-2160 line 125952 MATCH x2ef8d800/mask=xbffffc00 +# CONSTRUCT x6ef8d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmle/2@2 +# AUNIT --inst x6ef8d800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags" +# Vector half precision variant SIMD 8H when Q = 1 + +:fcmle Rd_VPR128.8H, Rn_VPR128.8H, "#0.0" +is b_31=0 & b_30=1 & b_1029=0b10111011111000110110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_fcmle(Rn_VPR128.8H, 0:2, 2:1); +} + +# C7.2.65 FCMLT (zero) page C7-2163 line 126168 MATCH x0ea0e800/mask=xbfbffc00 +# CONSTRUCT x4ee0e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmlt/2@8 +# AUNIT --inst x4ee0e800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags" + +:fcmlt Rd_VPR128.2D, Rn_VPR128.2D, "#0" +is b_3131=0 & q=1 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x30 & b_1216=0xe & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_fcmlt(Rn_VPR128.2D, 0:8, 8:1); +} + +# C7.2.65 FCMLT (zero) page C7-2163 line 126168 MATCH x0ea0e800/mask=xbfbffc00 +# CONSTRUCT x0ea0e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmlt/2@4 +# AUNIT --inst x0ea0e800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags" + +:fcmlt Rd_VPR64.2S, Rn_VPR64.2S, "#0" +is b_3131=0 & q=0 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xe & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_fcmlt(Rn_VPR64.2S, 0:4, 4:1); +} + +# C7.2.65 FCMLT (zero) page C7-2163 line 126168 MATCH x0ea0e800/mask=xbfbffc00 +# CONSTRUCT x4ea0e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmlt/2@4 +# AUNIT --inst x4ea0e800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags" + +:fcmlt Rd_VPR128.4S, Rn_VPR128.4S, "#0" +is b_3131=0 & q=1 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xe & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_fcmlt(Rn_VPR128.4S, 0:4, 4:1); +} + +# C7.2.65 FCMLT (zero) page C7-2163 line 126168 MATCH x5ef8e800/mask=xfffffc00 +# CONSTRUCT x5ef8e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmlt/2 +# AUNIT --inst x5ef8e800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags" +# Scalar half precision variant + +:fcmlt Rd_FPR16, Rn_FPR16, "#0.0" +is b_1031=0b0101111011111000111010 & Rd_FPR16 & Rn_FPR16 & Zd +{ + Rd_FPR16 = NEON_fcmlt(Rn_FPR16, 0:2); +} + +# C7.2.65 FCMLT (zero) page C7-2163 line 126168 MATCH x5ea0e800/mask=xffbffc00 +# CONSTRUCT x5ea0e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmlt/2 +# AUNIT --inst x5ea0e800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags" +# Scalar single-precision and double-precision sz=0 + +:fcmlt Rd_FPR32, Rn_FPR32, "#0.0" +is b_2331=0b010111101 & b_22=0 & b_1021=0b100000111010 & Rd_FPR32 & Rn_FPR32 & Zd +{ + Rd_FPR32 = NEON_fcmlt(Rn_FPR32, 0:4); +} + +# C7.2.65 FCMLT (zero) page C7-2163 line 126168 MATCH x5ea0e800/mask=xffbffc00 +# CONSTRUCT x5ee0e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmlt/2 +# AUNIT --inst x5ee0e800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags" +# Scalar single-precision and double-precision sz=1 + +:fcmlt Rd_FPR64, Rn_FPR64, "#0.0" +is b_2331=0b010111101 & b_22=1 & b_1021=0b100000111010 & Rd_FPR64 & Rn_FPR64 & Zd +{ + Rd_FPR64 = NEON_fcmlt(Rn_FPR64, 0:8); +} + +# C7.2.65 FCMLT (zero) page C7-2163 line 126168 MATCH x0ef8e800/mask=xbffffc00 +# CONSTRUCT x0ef8e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmlt/2@2 +# AUNIT --inst x0ef8e800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags" +# Vector half precision variant SIMD 4H when Q = 0 + +:fcmlt Rd_VPR64.4H, Rn_VPR64.4H, "#0.0" +is b_31=0 & b_30=0 & b_1029=0b00111011111000111010 & Rd_VPR64.4H & Rn_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_fcmlt(Rn_VPR64.4H, 0:2, 2:1); +} + +# C7.2.65 FCMLT (zero) page C7-2163 line 126168 MATCH x0ef8e800/mask=xbffffc00 +# CONSTRUCT x4ef8e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmlt/2@2 +# AUNIT --inst x4ef8e800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags" +# Vector half precision variant SIMD 8H when Q = 1 + +:fcmlt Rd_VPR128.8H, Rn_VPR128.8H, "#0.0" +is b_31=0 & b_30=1 & b_1029=0b00111011111000111010 & Rd_VPR128.8H & Rn_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_fcmlt(Rn_VPR128.8H, 0:2, 2:1); +} + +# C7.2.66 FCMP page C7-2166 line 126365 MATCH x1e202000/mask=xff20fc17 +# CONSTRUCT x1e602000/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES +# SMACRO null ARG1 ARG2 =fcomp/2 +# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmp/2 +# AUNIT --inst x1e602000/mask=xffe0fc1f --rand dfp --status nodest --comment "flags" + +:fcmp Rn_FPR64, Rm_FPR64 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR64 & fpcmp.opcode2=0x0 +{ + fcomp(Rn_FPR64, Rm_FPR64); +} + +# C7.2.66 FCMP page C7-2166 line 126365 MATCH x1e202000/mask=xff20fc17 +# CONSTRUCT x1e602008/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES +# SMACRO null ARG1 ARG2 =fcomp/2 +# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmp/2 +# AUNIT --inst x1e602008/mask=xffe0fc1f --rand dfp --status nodest --comment "flags" + +:fcmp Rn_FPR64, Rm_fpz64 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_fpz64 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR64 & fpcmp.opcode2=0x8 +{ + fcomp(Rn_FPR64, Rm_fpz64); +} + +# C7.2.66 FCMP page C7-2166 line 126365 MATCH x1e202000/mask=xff20fc17 +# CONSTRUCT x1e202008/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES +# SMACRO null ARG1 ARG2 =fcomp/2 +# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmp/2 +# AUNIT --inst x1e202008/mask=xffe0fc1f --rand sfp --status nodest --comment "flags" + +:fcmp Rn_FPR32, Rm_fpz32 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_fpz32 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR32 & fpcmp.opcode2=0x8 +{ + fcomp(Rn_FPR32, Rm_fpz32); +} + +# C7.2.66 FCMP page C7-2166 line 126365 MATCH x1e202000/mask=xff20fc17 +# CONSTRUCT x1e202000/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES +# SMACRO null ARG1 ARG2 =fcomp/2 +# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmp/2 +# AUNIT --inst x1e202000/mask=xffe0fc1f --rand sfp --status nodest --comment "flags" + +:fcmp Rn_FPR32, Rm_FPR32 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR32 & fpcmp.opcode2=0x0 +{ + fcomp(Rn_FPR32, Rm_FPR32); +} + +# C7.2.66 FCMP page C7-2166 line 126365 MATCH x1e202000/mask=xff20fc17 +# CONSTRUCT x1ee02008/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES +# SMACRO null ARG1 ARG2 =fcomp/2 +# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmp/2 +# AUNIT --inst x1ee02008/mask=xffe0fc1f --rand hfp --status nodest --comment "flags" + +:fcmp Rn_FPR16, Rm_fpz16 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_fpz16 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR16 & fpcmp.opcode2=0x8 +{ + fcomp(Rn_FPR16, Rm_fpz16); +} + +# C7.2.66 FCMP page C7-2166 line 126365 MATCH x1e202000/mask=xff20fc17 +# CONSTRUCT x1ee02000/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES +# SMACRO null ARG1 ARG2 =fcomp/2 +# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmp/2 +# AUNIT --inst x1ee02000/mask=xffe0fc1f --rand hfp --status nodest --comment "flags" + +:fcmp Rn_FPR16, Rm_FPR16 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR16 & fpcmp.opcode2=0x0 +{ + fcomp(Rn_FPR16, Rm_FPR16); +} + +# C7.2.67 FCMPE page C7-2168 line 126506 MATCH x1e202010/mask=xff20fc17 +# CONSTRUCT x1e602010/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES +# SMACRO null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2 +# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmpe/2 +# AUNIT --inst x1e602010/mask=xffe0fc1f --rand dfp --status nodest --comment "flags" + +:fcmpe Rn_FPR64, Rm_FPR64 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR64 & fpcmp.opcode2=0x10 +{ + ftestNAN(Rn_FPR64, Rm_FPR64); + fcomp(Rn_FPR64, Rm_FPR64); +} + +# C7.2.67 FCMPE page C7-2168 line 126506 MATCH x1e202010/mask=xff20fc17 +# CONSTRUCT x1e602018/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES +# SMACRO null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2 +# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmpe/2 +# AUNIT --inst x1e602018/mask=xffe0fc1f --rand dfp --status nodest --comment "flags" + +:fcmpe Rn_FPR64, Rm_fpz64 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_fpz64 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR64 & fpcmp.opcode2=0x18 +{ + ftestNAN(Rn_FPR64, Rm_fpz64); + fcomp(Rn_FPR64, Rm_fpz64); +} + +# C7.2.67 FCMPE page C7-2168 line 126506 MATCH x1e202010/mask=xff20fc17 +# CONSTRUCT x1e202018/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES +# SMACRO null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2 +# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmpe/2 +# AUNIT --inst x1e202018/mask=xffe0fc1f --rand sfp --status nodest --comment "flags" + +:fcmpe Rn_FPR32, Rm_fpz32 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_fpz32 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR32 & fpcmp.opcode2=0x18 +{ + ftestNAN(Rn_FPR32, Rm_fpz32); + fcomp(Rn_FPR32, Rm_fpz32); +} + +# C7.2.67 FCMPE page C7-2168 line 126506 MATCH x1e202010/mask=xff20fc17 +# CONSTRUCT x1e202010/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES +# SMACRO null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2 +# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmpe/2 +# AUNIT --inst x1e202010/mask=xffe0fc1f --rand sfp --status nodest --comment "flags" + +:fcmpe Rn_FPR32, Rm_FPR32 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR32 & fpcmp.opcode2=0x10 +{ + ftestNAN(Rn_FPR32, Rm_FPR32); + fcomp(Rn_FPR32, Rm_FPR32); +} + +# C7.2.67 FCMPE page C7-2168 line 126506 MATCH x1e202010/mask=xff20fc17 +# CONSTRUCT x1ee02018/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES +# SMACRO null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2 +# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmpe/2 +# AUNIT --inst x1ee02018/mask=xffe0fc1f --rand hfp --status nodest --comment "flags" + +:fcmpe Rn_FPR16, Rm_fpz16 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_fpz16 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR16 & fpcmp.opcode2=0x18 +{ + ftestNAN(Rn_FPR16, Rm_fpz16); + fcomp(Rn_FPR16, Rm_fpz16); +} + +# C7.2.67 FCMPE page C7-2168 line 126506 MATCH x1e202010/mask=xff20fc17 +# CONSTRUCT x1ee02010/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES +# SMACRO null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2 +# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmpe/2 +# AUNIT --inst x1ee02010/mask=xffe0fc1f --rand hfp --status nodest --comment "flags" + +:fcmpe Rn_FPR16, Rm_FPR16 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR16 & fpcmp.opcode2=0x10 +{ + ftestNAN(Rn_FPR16, Rm_FPR16); + fcomp(Rn_FPR16, Rm_FPR16); +} + +# C7.2.68 FCSEL page C7-2170 line 126647 MATCH x1e200c00/mask=xff200c00 +# CONSTRUCT x1e600c00/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 = dup ext swap ARG4:1 inst_next goto = +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4:1 =NEON_fcsel/3 +# AUNIT --inst x1e600c00/mask=xffe00c00 --rand dfp --status pass --comment "flags" +# Rm may be the same register as Rd, so it needs to be saved + +:fcsel Rd_FPR64, Rn_FPR64, Rm_FPR64, CondOp +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & CondOp & b_1011=3 & Rn_FPR64 & Rd_FPR64 & Zd +{ + local tmp1:8 = Rm_FPR64; + Rd_FPR64 = Rn_FPR64; + zext_zd(Zd); # zero upper 24 bytes of Zd + if (CondOp:1) goto inst_next; + Rd_FPR64 = tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.68 FCSEL page C7-2170 line 126647 MATCH x1e200c00/mask=xff200c00 +# CONSTRUCT x1e200c00/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 = dup ext swap ARG4:1 inst_next goto = +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4:1 =NEON_fcsel/3 +# AUNIT --inst x1e200c00/mask=xffe00c00 --rand sfp --status pass --comment "flags" + +:fcsel Rd_FPR32, Rn_FPR32, Rm_FPR32, CondOp +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & CondOp & b_1011=3 & Rn_FPR32 & Rd_FPR32 & Zd +{ + local tmp1:4 = Rm_FPR32; + Rd_FPR32 = Rn_FPR32; + zext_zs(Zd); # zero upper 28 bytes of Zd + if (CondOp:1) goto inst_next; + Rd_FPR32 = tmp1; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.68 FCSEL page C7-2170 line 126647 MATCH x1e200c00/mask=xff200c00 +# CONSTRUCT x1ee00c00/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 = dup ext swap ARG4:1 inst_next goto = +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4:1 =NEON_fcsel/3 +# AUNIT --inst x1ee00c00/mask=xffe00c00 --rand hfp --status noqemu --comment "flags" + +:fcsel Rd_FPR16, Rn_FPR16, Rm_FPR16, CondOp +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & CondOp & b_1011=3 & Rn_FPR16 & Rd_FPR16 & Zd +{ + local tmp1:2 = Rm_FPR16; + Rd_FPR16 = Rn_FPR16; + zext_zh(Zd); # zero upper 30 bytes of Zd + if (CondOp:1) goto inst_next; + Rd_FPR16 = tmp1; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.69 FCVT page C7-2172 line 126762 MATCH x1e224000/mask=xff3e7c00 +# CONSTRUCT x1ee2c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =float2float/1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt/1 +# AUNIT --inst x1ee2c000/mask=xfffffc00 --rand hfp --status pass --comment "nofpround" + +:fcvt Rd_FPR64, Rn_FPR16 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & fpDpOpcode=0x5 & b_1014=0x10 & Rn_FPR16 & Rd_FPR64 & Zd +{ + Rd_FPR64 = float2float(Rn_FPR16); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.69 FCVT page C7-2172 line 126762 MATCH x1e224000/mask=xff3e7c00 +# CONSTRUCT x1e22c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =float2float/1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt/1 +# AUNIT --inst x1e22c000/mask=xfffffc00 --rand sfp --status pass --comment "nofpround" + +:fcvt Rd_FPR64, Rn_FPR32 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & fpDpOpcode=0x5 & b_1014=0x10 & Rn_FPR32 & Rd_FPR64 & Zd +{ + Rd_FPR64 = float2float(Rn_FPR32); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.69 FCVT page C7-2172 line 126762 MATCH x1e224000/mask=xff3e7c00 +# CONSTRUCT x1e63c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =float2float/1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt/1 +# AUNIT --inst x1e63c000/mask=xfffffc00 --rand hfp --status pass --comment "nofpround" + +:fcvt Rd_FPR16, Rn_FPR64 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & fpDpOpcode=0x7 & b_1014=0x10 & Rn_FPR64 & Rd_FPR16 & Zd +{ + Rd_FPR16 = float2float(Rn_FPR64); + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.69 FCVT page C7-2172 line 126762 MATCH x1e224000/mask=xff3e7c00 +# CONSTRUCT x1e23c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =float2float/1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt/1 +# AUNIT --inst x1e23c000/mask=xfffffc00 --rand hfp --status fail --comment "nofpround" + +:fcvt Rd_FPR16, Rn_FPR32 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & fpDpOpcode=0x7 & b_1014=0x10 & Rn_FPR32 & Rd_FPR16 & Zd +{ + Rd_FPR16 = float2float(Rn_FPR32); + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.69 FCVT page C7-2172 line 126762 MATCH x1e224000/mask=xff3e7c00 +# CONSTRUCT x1e624000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =float2float/1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt/1 +# AUNIT --inst x1e624000/mask=xfffffc00 --rand sfp --status fail --comment "nofpround" + +:fcvt Rd_FPR32, Rn_FPR64 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & fpDpOpcode=0x4 & b_1014=0x10 & Rn_FPR64 & Rd_FPR32 & Zd +{ + Rd_FPR32 = float2float(Rn_FPR64); + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.69 FCVT page C7-2172 line 126762 MATCH x1e224000/mask=xff3e7c00 +# CONSTRUCT x1ee24000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =float2float/1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt/1 +# AUNIT --inst x1ee24000/mask=xfffffc00 --rand hfp --status pass --comment "nofpround" + +:fcvt Rd_FPR32, Rn_FPR16 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & fpDpOpcode=0x4 & b_1014=0x10 & Rn_FPR16 & Rd_FPR32 & Zd +{ + Rd_FPR32 = float2float(Rn_FPR16); + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.63 FCVTAS (vector) page C7-1136 line 65961 KEEPWITH + +fcvt_vmnemonic: "fcvtas" is b_29=0 & b_23=0 & b_1314=0b10 & b_12=0 { } +fcvt_vmnemonic: "fcvtau" is b_29=1 & b_23=0 & b_1314=0b10 & b_12=0 { } +fcvt_vmnemonic: "fcvtms" is b_29=0 & b_23=0 & b_1314=0b01 & b_12=1 { } +fcvt_vmnemonic: "fcvtmu" is b_29=1 & b_23=0 & b_1314=0b01 & b_12=1 { } +fcvt_vmnemonic: "fcvtns" is b_29=0 & b_23=0 & b_1314=0b01 & b_12=0 { } +fcvt_vmnemonic: "fcvtnu" is b_29=1 & b_23=0 & b_1314=0b01 & b_12=0 { } +fcvt_vmnemonic: "fcvtps" is b_29=0 & b_23=1 & b_1314=0b01 & b_12=0 { } +fcvt_vmnemonic: "fcvtpu" is b_29=1 & b_23=1 & b_1314=0b01 & b_12=0 { } +fcvt_vmnemonic: "fcvtzs" is b_29=0 & b_23=1 & b_1314=0b01 & b_12=1 { } +fcvt_vmnemonic: "fcvtzu" is b_29=1 & b_23=1 & b_1314=0b01 & b_12=1 { } + +fcvt_smnemonic: "fcvtas" is b_1920=0b00 & b_1618=0b100 { } +fcvt_smnemonic: "fcvtau" is b_1920=0b00 & b_1618=0b101 { } +fcvt_smnemonic: "fcvtms" is b_1920=0b10 & b_1618=0b000 { } +fcvt_smnemonic: "fcvtmu" is b_1920=0b10 & b_1618=0b001 { } +fcvt_smnemonic: "fcvtns" is b_1920=0b00 & b_1618=0b000 { } +fcvt_smnemonic: "fcvtnu" is b_1920=0b00 & b_1618=0b001 { } +fcvt_smnemonic: "fcvtps" is b_1920=0b01 & b_1618=0b000 { } +fcvt_smnemonic: "fcvtpu" is b_1920=0b01 & b_1618=0b001 { } +fcvt_smnemonic: "fcvtzs" is b_1920=0b11 & b_1618=0b000 { } +fcvt_smnemonic: "fcvtzu" is b_1920=0b11 & b_1618=0b001 { } + +# C7.2.70 FCVTAS (vector) page C7-2174 line 126882 MATCH x5e79c800/mask=xfffffc00 +# C7.2.72 FCVTAU (vector) page C7-2179 line 127203 MATCH x7e79c800/mask=xfffffc00 +# CONSTRUCT x5e79c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =trunc +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1 +# AUNIT --inst x5e79c800/mask=xdffffc00 --rand hfp --status noqemu --comment "nofpround" +# Scalar half precision + +:^fcvt_vmnemonic Rd_FPR16, Rn_FPR16 +is b_3031=0b01 & b_1028=0b1111001111001110010 & fcvt_vmnemonic & Rd_FPR16 & Rn_FPR16 & Zd +{ + Rd_FPR16 = trunc(Rn_FPR16); + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.70 FCVTAS (vector) page C7-2174 line 126882 MATCH x5e21c800/mask=xffbffc00 +# C7.2.72 FCVTAU (vector) page C7-2179 line 127203 MATCH x7e21c800/mask=xffbffc00 +# CONSTRUCT x5e21c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =trunc +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1 +# AUNIT --inst x5e21c800/mask=xdffffc00 --rand sfp --status fail --comment "nofpround" +# Scalar single-precision and double-precision variant sz=0 + +:^fcvt_vmnemonic Rd_FPR32, Rn_FPR32 +is b_3031=0b01 & b_2328=0b111100 & b_22=0 & b_1021=0b100001110010 & fcvt_vmnemonic & Rd_FPR32 & Rn_FPR32 & Zd +{ + Rd_FPR32 = trunc(Rn_FPR32); + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.70 FCVTAS (vector) page C7-2174 line 126882 MATCH x5e21c800/mask=xffbffc00 +# C7.2.72 FCVTAU (vector) page C7-2179 line 127203 MATCH x7e21c800/mask=xffbffc00 +# CONSTRUCT x5e61c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =trunc +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1 +# AUNIT --inst x5e61c800/mask=xdffffc00 --rand dfp --status fail --comment "nofpround" +# Scalar single-precision and double-precision variant sz=1 + +:^fcvt_vmnemonic Rd_FPR64, Rn_FPR64 +is b_3031=0b01 & b_2328=0b111100 & b_22=1 & b_1021=0b100001110010 & fcvt_vmnemonic & Rd_FPR64 & Rn_FPR64 & Zd +{ + Rd_FPR64 = trunc(Rn_FPR64); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.70 FCVTAS (vector) page C7-2174 line 126882 MATCH x0e79c800/mask=xbffffc00 +# C7.2.72 FCVTAU (vector) page C7-2179 line 127203 MATCH x2e79c800/mask=xbffffc00 +# CONSTRUCT x0e79c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$trunc@2 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@2 +# AUNIT --inst x0e79c800/mask=xdffffc00 --rand hfp --status noqemu --comment "nofpround" +# Vector half precision variant Q=0 + +:^fcvt_vmnemonic Rd_VPR64.4H, Rn_VPR64.4H +is b_31=0 & b_30=0 & b_2328=0b011100 & b_1022=0b1111001110010 & fcvt_vmnemonic & Rd_VPR64.4H & Rn_VPR64.4H & Zd +{ + # simd unary Rd_VPR64.4H = trunc(Rn_VPR64.4H) on lane size 2 + Rd_VPR64.4H[0,16] = trunc(Rn_VPR64.4H[0,16]); + Rd_VPR64.4H[16,16] = trunc(Rn_VPR64.4H[16,16]); + Rd_VPR64.4H[32,16] = trunc(Rn_VPR64.4H[32,16]); + Rd_VPR64.4H[48,16] = trunc(Rn_VPR64.4H[48,16]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.70 FCVTAS (vector) page C7-2174 line 126882 MATCH x0e79c800/mask=xbffffc00 +# C7.2.72 FCVTAU (vector) page C7-2179 line 127203 MATCH x2e79c800/mask=xbffffc00 +# CONSTRUCT x4e79c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$trunc@2 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@2 +# AUNIT --inst x4e79c800/mask=xdffffc00 --rand hfp --status noqemu --comment "nofpround" +# Vector half precision variant Q=1 + +:^fcvt_vmnemonic Rd_VPR128.8H, Rn_VPR128.8H +is b_31=0 & b_30=1 & b_2328=0b011100 & b_1022=0b1111001110010 & fcvt_vmnemonic & Rd_VPR128.8H & Rn_VPR128.8H & Zd +{ + # simd unary Rd_VPR128.8H = trunc(Rn_VPR128.8H) on lane size 2 + Rd_VPR128.8H[0,16] = trunc(Rn_VPR128.8H[0,16]); + Rd_VPR128.8H[16,16] = trunc(Rn_VPR128.8H[16,16]); + Rd_VPR128.8H[32,16] = trunc(Rn_VPR128.8H[32,16]); + Rd_VPR128.8H[48,16] = trunc(Rn_VPR128.8H[48,16]); + Rd_VPR128.8H[64,16] = trunc(Rn_VPR128.8H[64,16]); + Rd_VPR128.8H[80,16] = trunc(Rn_VPR128.8H[80,16]); + Rd_VPR128.8H[96,16] = trunc(Rn_VPR128.8H[96,16]); + Rd_VPR128.8H[112,16] = trunc(Rn_VPR128.8H[112,16]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.70 FCVTAS (vector) page C7-2174 line 126882 MATCH x0e21c800/mask=xbfbffc00 +# C7.2.72 FCVTAU (vector) page C7-2179 line 127203 MATCH x2e21c800/mask=xbfbffc00 +# CONSTRUCT x0e21c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$trunc@4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@4 +# AUNIT --inst x0e21c800/mask=xdffffc00 --rand sfp --status fail --comment "nofpround" +# Vector single-precision and double-precision variant SIMD 2S when sz = 0 , Q = 0 + +:^fcvt_vmnemonic Rd_VPR64.2S, Rn_VPR64.2S +is b_31=0 & b_30=0 & b_2328=0b011100 & b_22=0 & b_1021=0b100001110010 & fcvt_vmnemonic & Rd_VPR64.2S & Rn_VPR64.2S & Zd +{ + # simd unary Rd_VPR64.2S = trunc(Rn_VPR64.2S) on lane size 4 + Rd_VPR64.2S[0,32] = trunc(Rn_VPR64.2S[0,32]); + Rd_VPR64.2S[32,32] = trunc(Rn_VPR64.2S[32,32]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.70 FCVTAS (vector) page C7-2174 line 126882 MATCH x0e21c800/mask=xbfbffc00 +# C7.2.72 FCVTAU (vector) page C7-2179 line 127203 MATCH x2e21c800/mask=xbfbffc00 +# CONSTRUCT x4e21c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$trunc@4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@4 +# AUNIT --inst x4e21c800/mask=xdffffc00 --rand sfp --status fail --comment "nofpround" +# Vector single-precision and double-precision variant SIMD 4S when sz = 0 , Q = 1 + +:^fcvt_vmnemonic Rd_VPR128.4S, Rn_VPR128.4S +is b_31=0 & b_30=1 & b_2328=0b011100 & b_22=0 & b_1021=0b100001110010 & fcvt_vmnemonic & Rd_VPR128.4S & Rn_VPR128.4S & Zd +{ + # simd unary Rd_VPR128.4S = trunc(Rn_VPR128.4S) on lane size 4 + Rd_VPR128.4S[0,32] = trunc(Rn_VPR128.4S[0,32]); + Rd_VPR128.4S[32,32] = trunc(Rn_VPR128.4S[32,32]); + Rd_VPR128.4S[64,32] = trunc(Rn_VPR128.4S[64,32]); + Rd_VPR128.4S[96,32] = trunc(Rn_VPR128.4S[96,32]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.70 FCVTAS (vector) page C7-2174 line 126882 MATCH x0e21c800/mask=xbfbffc00 +# C7.2.72 FCVTAU (vector) page C7-2179 line 127203 MATCH x2e21c800/mask=xbfbffc00 +# CONSTRUCT x4e61c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$trunc@8 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@8 +# AUNIT --inst x4e61c800/mask=xdffffc00 --rand dfp --status fail --comment "nofpround" +# Vector single-precision and double-precision variant SIMD 2D when sz = 1 , Q = 1 + +:^fcvt_vmnemonic Rd_VPR128.2D, Rn_VPR128.2D +is b_31=0 & b_30=1 & b_2328=0b011100 & b_22=1 & b_1021=0b100001110010 & fcvt_vmnemonic & Rd_VPR128.2D & Rn_VPR128.2D & Zd +{ + # simd unary Rd_VPR128.2D = trunc(Rn_VPR128.2D) on lane size 8 + Rd_VPR128.2D[0,64] = trunc(Rn_VPR128.2D[0,64]); + Rd_VPR128.2D[64,64] = trunc(Rn_VPR128.2D[64,64]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.71 FCVTAS (scalar) page C7-2177 line 127075 MATCH x1e240000/mask=x7f3ffc00 +# C7.2.73 FCVTAU (scalar) page C7-2182 line 127396 MATCH x1e250000/mask=x7f3ffc00 +# CONSTRUCT x1ee40000/mask=xfffefc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =trunc +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1 +# AUNIT --inst x1ee40000/mask=xfffefc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision to 32-bit variant when sf == 0 && type == 11 + +:^fcvt_smnemonic Rd_GPR32, Rn_FPR16 +is b_31=0 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1720=0b0010 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR32 & Rn_FPR16 & Rd_GPR64 +{ + Rd_GPR32 = trunc(Rn_FPR16); + zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64 +} + +# C7.2.71 FCVTAS (scalar) page C7-2177 line 127075 MATCH x1e240000/mask=x7f3ffc00 +# C7.2.73 FCVTAU (scalar) page C7-2182 line 127396 MATCH x1e250000/mask=x7f3ffc00 +# CONSTRUCT x9ee40000/mask=xfffefc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =trunc +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1 +# AUNIT --inst x9ee40000/mask=xfffefc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision to 64-bit variant when sf == 1 && type == 11 + +:^fcvt_smnemonic Rd_GPR64, Rn_FPR16 +is b_31=1 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1720=0b0010 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR64 & Rn_FPR16 +{ + Rd_GPR64 = trunc(Rn_FPR16); +} + +# C7.2.71 FCVTAS (scalar) page C7-2177 line 127075 MATCH x1e240000/mask=x7f3ffc00 +# C7.2.73 FCVTAU (scalar) page C7-2182 line 127396 MATCH x1e250000/mask=x7f3ffc00 +# CONSTRUCT x1e240000/mask=xfffefc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =trunc +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1 +# AUNIT --inst x1e240000/mask=xfffefc00 --rand sfp --status fail --comment "nofpround" +# Single-precision to 32-bit variant when sf == 0 && type == 00 + +:^fcvt_smnemonic Rd_GPR32, Rn_FPR32 +is b_31=0 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1720=0b0010 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR32 & Rn_FPR32 & Rd_GPR64 +{ + Rd_GPR32 = trunc(Rn_FPR32); + zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64 +} + +# C7.2.71 FCVTAS (scalar) page C7-2177 line 127075 MATCH x1e240000/mask=x7f3ffc00 +# C7.2.73 FCVTAU (scalar) page C7-2182 line 127396 MATCH x1e250000/mask=x7f3ffc00 +# CONSTRUCT x9e240000/mask=xfffefc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =trunc +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1 +# AUNIT --inst x9e240000/mask=xfffefc00 --rand sfp --status fail --comment "nofpround" +# Single-precision to 64-bit variant when sf == 1 && type == 00 + +:^fcvt_smnemonic Rd_GPR64, Rn_FPR32 +is b_31=1 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1720=0b0010 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR64 & Rn_FPR32 +{ + Rd_GPR64 = trunc(Rn_FPR32); +} + +# C7.2.71 FCVTAS (scalar) page C7-2177 line 127075 MATCH x1e240000/mask=x7f3ffc00 +# C7.2.73 FCVTAU (scalar) page C7-2182 line 127396 MATCH x1e250000/mask=x7f3ffc00 +# CONSTRUCT x1e640000/mask=xfffefc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =trunc +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1 +# AUNIT --inst x1e640000/mask=xfffefc00 --rand dfp --status fail --comment "nofpround" +# Double-precision to 32-bit variant when sf == 0 && type == 01 + +:^fcvt_smnemonic Rd_GPR32, Rn_FPR64 +is b_31=0 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1720=0b0010 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR32 & Rn_FPR64 & Rd_GPR64 +{ + Rd_GPR32 = trunc(Rn_FPR64); + zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64 +} + +# C7.2.71 FCVTAS (scalar) page C7-2177 line 127075 MATCH x1e240000/mask=x7f3ffc00 +# C7.2.73 FCVTAU (scalar) page C7-2182 line 127396 MATCH x1e250000/mask=x7f3ffc00 +# CONSTRUCT x9e640000/mask=xfffefc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =trunc +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1 +# AUNIT --inst x9e640000/mask=xfffefc00 --rand dfp --status fail --comment "nofpround" +# Double-precision to 64-bit variant sf == 1 && type == 01 + +:^fcvt_smnemonic Rd_GPR64, Rn_FPR64 +is b_31=1 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1720=0b0010 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR64 & Rn_FPR64 +{ + Rd_GPR64 = trunc(Rn_FPR64); +} + +# C7.2.74 FCVTL, FCVTL2 page C7-2184 line 127524 MATCH x0e217800/mask=xbfbffc00 +# CONSTRUCT x0e617800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =var =$float2float@4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvtl/1@4 +# AUNIT --inst x0e617800/mask=xfffffc00 --rand dfp --status fail --comment "ext nofpround" + +:fcvtl Rd_VPR128.2D, Rn_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x17 & b_1011=2 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR64.2S; + # simd resize Rd_VPR128.2D = float2float(TMPD1) (lane size 4 to 8) + Rd_VPR128.2D[0,64] = float2float(TMPD1[0,32]); + Rd_VPR128.2D[64,64] = float2float(TMPD1[32,32]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.74 FCVTL, FCVTL2 page C7-2184 line 127524 MATCH x0e217800/mask=xbfbffc00 +# CONSTRUCT x4e617800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 =$float2float@4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvtl2/1@8 +# AUNIT --inst x4e617800/mask=xfffffc00 --rand dfp --status fail --comment "ext nofpround" + +:fcvtl2 Rd_VPR128.2D, Rn_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x17 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize Rd_VPR128.2D = float2float(TMPD1) (lane size 4 to 8) + Rd_VPR128.2D[0,64] = float2float(TMPD1[0,32]); + Rd_VPR128.2D[64,64] = float2float(TMPD1[32,32]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.74 FCVTL, FCVTL2 page C7-2184 line 127524 MATCH x0e217800/mask=xbfbffc00 +# CONSTRUCT x0e217800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =var =$float2float@2 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvtl/1@4 +# AUNIT --inst x0e217800/mask=xfffffc00 --rand sfp --status fail --comment "ext nofpround" + +:fcvtl Rd_VPR128.4S, Rn_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x17 & b_1011=2 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR64.4H; + # simd resize Rd_VPR128.4S = float2float(TMPD1) (lane size 2 to 4) + Rd_VPR128.4S[0,32] = float2float(TMPD1[0,16]); + Rd_VPR128.4S[32,32] = float2float(TMPD1[16,16]); + Rd_VPR128.4S[64,32] = float2float(TMPD1[32,16]); + Rd_VPR128.4S[96,32] = float2float(TMPD1[48,16]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.74 FCVTL, FCVTL2 page C7-2184 line 127524 MATCH x0e217800/mask=xbfbffc00 +# CONSTRUCT x4e217800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 =$float2float@2 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvtl2/1@2 +# AUNIT --inst x4e217800/mask=xfffffc00 --rand sfp --status fail --comment "ext nofpround" + +:fcvtl2 Rd_VPR128.4S, Rn_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x17 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize Rd_VPR128.4S = float2float(TMPD1) (lane size 2 to 4) + Rd_VPR128.4S[0,32] = float2float(TMPD1[0,16]); + Rd_VPR128.4S[32,32] = float2float(TMPD1[16,16]); + Rd_VPR128.4S[64,32] = float2float(TMPD1[32,16]); + Rd_VPR128.4S[96,32] = float2float(TMPD1[48,16]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.75 FCVTMS (vector) page C7-2186 line 127614 MATCH x5e79b800/mask=xfffffc00 +# C7.2.77 FCVTMU (vector) page C7-2191 line 127938 MATCH x7e79b800/mask=xfffffc00 +# C7.2.80 FCVTNS (vector) page C7-2198 line 128355 MATCH x5e79a800/mask=xfffffc00 +# C7.2.82 FCVTNU (vector) page C7-2203 line 128679 MATCH x7e79a800/mask=xfffffc00 +# C7.2.84 FCVTPS (vector) page C7-2208 line 129003 MATCH x5ef9a800/mask=xfffffc00 +# C7.2.86 FCVTPU (vector) page C7-2213 line 129327 MATCH x7ef9a800/mask=xfffffc00 +# C7.2.90 FCVTZS (vector, integer) page C7-2224 line 129963 MATCH x5ef9b800/mask=xfffffc00 +# C7.2.94 FCVTZU (vector, integer) page C7-2234 line 130576 MATCH x7ef9b800/mask=xfffffc00 +# CONSTRUCT x5e79a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =trunc +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1 +# AUNIT --inst x5e79a800/mask=xdf7fec00 --rand hfp --status noqemu --comment "nofpround" +# Scalar half precision + +:^fcvt_vmnemonic Rd_FPR16, Rn_FPR16 +is b_3031=0b01 & b_2428=0b11110 & b_1322=0b1111001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_FPR16 & Rn_FPR16 & Zd +{ + Rd_FPR16 = trunc(Rn_FPR16); + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.75 FCVTMS (vector) page C7-2186 line 127614 MATCH x5e21b800/mask=xffbffc00 +# C7.2.77 FCVTMU (vector) page C7-2191 line 127938 MATCH x7e21b800/mask=xffbffc00 +# C7.2.80 FCVTNS (vector) page C7-2198 line 128355 MATCH x5e21a800/mask=xffbffc00 +# C7.2.82 FCVTNU (vector) page C7-2203 line 128679 MATCH x7e21a800/mask=xffbffc00 +# C7.2.84 FCVTPS (vector) page C7-2208 line 129003 MATCH x5ea1a800/mask=xffbffc00 +# C7.2.86 FCVTPU (vector) page C7-2213 line 129327 MATCH x7ea1a800/mask=xffbffc00 +# C7.2.90 FCVTZS (vector, integer) page C7-2224 line 129963 MATCH x5ea1b800/mask=xffbffc00 +# C7.2.94 FCVTZU (vector, integer) page C7-2234 line 130576 MATCH x7ea1b800/mask=xffbffc00 +# CONSTRUCT x5e21a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =trunc +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1 +# AUNIT --inst x5e21a800/mask=xdf7fec00 --rand sfp --status fail --comment "nofpround" +# Scalar single-precision and double-precision variant sz=0 + +:^fcvt_vmnemonic Rd_FPR32, Rn_FPR32 +is b_3031=0b01 & b_2428=0b11110 & b_22=0 & b_1321=0b100001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_FPR32 & Rn_FPR32 & Zd +{ + Rd_FPR32 = trunc(Rn_FPR32); + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.75 FCVTMS (vector) page C7-2186 line 127614 MATCH x5e21b800/mask=xffbffc00 +# C7.2.77 FCVTMU (vector) page C7-2191 line 127938 MATCH x7e21b800/mask=xffbffc00 +# C7.2.80 FCVTNS (vector) page C7-2198 line 128355 MATCH x5e21a800/mask=xffbffc00 +# C7.2.82 FCVTNU (vector) page C7-2203 line 128679 MATCH x7e21a800/mask=xffbffc00 +# C7.2.84 FCVTPS (vector) page C7-2208 line 129003 MATCH x5ea1a800/mask=xffbffc00 +# C7.2.86 FCVTPU (vector) page C7-2213 line 129327 MATCH x7ea1a800/mask=xffbffc00 +# C7.2.90 FCVTZS (vector, integer) page C7-2224 line 129963 MATCH x5ea1b800/mask=xffbffc00 +# C7.2.94 FCVTZU (vector, integer) page C7-2234 line 130576 MATCH x7ea1b800/mask=xffbffc00 +# CONSTRUCT x5e61a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =trunc +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1 +# AUNIT --inst x5e61a800/mask=xdf7fec00 --rand dfp --status fail --comment "nofpround" +# Scalar single-precision and double-precision variant sz=1 + +:^fcvt_vmnemonic Rd_FPR64, Rn_FPR64 +is b_3031=0b01 & b_2428=0b11110 & b_22=1 & b_1321=0b100001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_FPR64 & Rn_FPR64 & Zd +{ + Rd_FPR64 = trunc(Rn_FPR64); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.75 FCVTMS (vector) page C7-2186 line 127614 MATCH x0e79b800/mask=xbffffc00 +# C7.2.77 FCVTMU (vector) page C7-2191 line 127938 MATCH x2e79b800/mask=xbffffc00 +# C7.2.80 FCVTNS (vector) page C7-2198 line 128355 MATCH x0e79a800/mask=xbffffc00 +# C7.2.82 FCVTNU (vector) page C7-2203 line 128679 MATCH x2e79a800/mask=xbffffc00 +# C7.2.84 FCVTPS (vector) page C7-2208 line 129003 MATCH x0ef9a800/mask=xbffffc00 +# C7.2.86 FCVTPU (vector) page C7-2213 line 129327 MATCH x2ef9a800/mask=xbffffc00 +# C7.2.90 FCVTZS (vector, integer) page C7-2224 line 129963 MATCH x0ef9b800/mask=xbffffc00 +# C7.2.94 FCVTZU (vector, integer) page C7-2234 line 130576 MATCH x2ef9b800/mask=xbffffc00 +# CONSTRUCT x0e79a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$trunc@2 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@2 +# AUNIT --inst x0e79a800/mask=xdf7fec00 --rand hfp --status noqemu --comment "nofpround" +# Vector half precision variant Q=0 + +:^fcvt_vmnemonic Rd_VPR64.4H, Rn_VPR64.4H +is b_31=0 & b_30=0 & b_2428=0b01110 & b_1322=0b1111001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_VPR64.4H & Rn_VPR64.4H & Zd +{ + # simd unary Rd_VPR64.4H = trunc(Rn_VPR64.4H) on lane size 2 + Rd_VPR64.4H[0,16] = trunc(Rn_VPR64.4H[0,16]); + Rd_VPR64.4H[16,16] = trunc(Rn_VPR64.4H[16,16]); + Rd_VPR64.4H[32,16] = trunc(Rn_VPR64.4H[32,16]); + Rd_VPR64.4H[48,16] = trunc(Rn_VPR64.4H[48,16]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.75 FCVTMS (vector) page C7-2186 line 127614 MATCH x0e79b800/mask=xbffffc00 +# C7.2.77 FCVTMU (vector) page C7-2191 line 127938 MATCH x2e79b800/mask=xbffffc00 +# C7.2.80 FCVTNS (vector) page C7-2198 line 128355 MATCH x0e79a800/mask=xbffffc00 +# C7.2.82 FCVTNU (vector) page C7-2203 line 128679 MATCH x2e79a800/mask=xbffffc00 +# C7.2.84 FCVTPS (vector) page C7-2208 line 129003 MATCH x0ef9a800/mask=xbffffc00 +# C7.2.86 FCVTPU (vector) page C7-2213 line 129327 MATCH x2ef9a800/mask=xbffffc00 +# C7.2.90 FCVTZS (vector, integer) page C7-2224 line 129963 MATCH x0ef9b800/mask=xbffffc00 +# C7.2.94 FCVTZU (vector, integer) page C7-2234 line 130576 MATCH x2ef9b800/mask=xbffffc00 +# CONSTRUCT x4e79a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$trunc@2 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@2 +# AUNIT --inst x4e79a800/mask=xdf7fec00 --rand hfp --status noqemu --comment "nofpround" +# Vector half precision variant Q=1 + +:^fcvt_vmnemonic Rd_VPR128.8H, Rn_VPR128.8H +is b_31=0 & b_30=1 & b_2428=0b01110 & b_1322=0b1111001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_VPR128.8H & Rn_VPR128.8H & Zd +{ + # simd unary Rd_VPR128.8H = trunc(Rn_VPR128.8H) on lane size 2 + Rd_VPR128.8H[0,16] = trunc(Rn_VPR128.8H[0,16]); + Rd_VPR128.8H[16,16] = trunc(Rn_VPR128.8H[16,16]); + Rd_VPR128.8H[32,16] = trunc(Rn_VPR128.8H[32,16]); + Rd_VPR128.8H[48,16] = trunc(Rn_VPR128.8H[48,16]); + Rd_VPR128.8H[64,16] = trunc(Rn_VPR128.8H[64,16]); + Rd_VPR128.8H[80,16] = trunc(Rn_VPR128.8H[80,16]); + Rd_VPR128.8H[96,16] = trunc(Rn_VPR128.8H[96,16]); + Rd_VPR128.8H[112,16] = trunc(Rn_VPR128.8H[112,16]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.75 FCVTMS (vector) page C7-2186 line 127614 MATCH x0e21b800/mask=xbfbffc00 +# C7.2.77 FCVTMU (vector) page C7-2191 line 127938 MATCH x2e21b800/mask=xbfbffc00 +# C7.2.80 FCVTNS (vector) page C7-2198 line 128355 MATCH x0e21a800/mask=xbfbffc00 +# C7.2.82 FCVTNU (vector) page C7-2203 line 128679 MATCH x2e21a800/mask=xbfbffc00 +# C7.2.84 FCVTPS (vector) page C7-2208 line 129003 MATCH x0ea1a800/mask=xbfbffc00 +# C7.2.86 FCVTPU (vector) page C7-2213 line 129327 MATCH x2ea1a800/mask=xbfbffc00 +# C7.2.90 FCVTZS (vector, integer) page C7-2224 line 129963 MATCH x0ea1b800/mask=xbfbffc00 +# C7.2.94 FCVTZU (vector, integer) page C7-2234 line 130576 MATCH x2ea1b800/mask=xbfbffc00 +# CONSTRUCT x0e21a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$trunc@4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@4 +# AUNIT --inst x0e21a800/mask=xdf7fec00 --rand sfp --status fail --comment "nofpround" +# Vector single-precision and double-precision variant SIMD 2S when sz = 0 , Q = 0 + +:^fcvt_vmnemonic Rd_VPR64.2S, Rn_VPR64.2S +is b_31=0 & b_30=0 & b_2428=0b01110 & b_22=0 & b_1321=0b100001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_VPR64.2S & Rn_VPR64.2S & Zd +{ + # simd unary Rd_VPR64.2S = trunc(Rn_VPR64.2S) on lane size 4 + Rd_VPR64.2S[0,32] = trunc(Rn_VPR64.2S[0,32]); + Rd_VPR64.2S[32,32] = trunc(Rn_VPR64.2S[32,32]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.75 FCVTMS (vector) page C7-2186 line 127614 MATCH x0e21b800/mask=xbfbffc00 +# C7.2.77 FCVTMU (vector) page C7-2191 line 127938 MATCH x2e21b800/mask=xbfbffc00 +# C7.2.80 FCVTNS (vector) page C7-2198 line 128355 MATCH x0e21a800/mask=xbfbffc00 +# C7.2.82 FCVTNU (vector) page C7-2203 line 128679 MATCH x2e21a800/mask=xbfbffc00 +# C7.2.84 FCVTPS (vector) page C7-2208 line 129003 MATCH x0ea1a800/mask=xbfbffc00 +# C7.2.86 FCVTPU (vector) page C7-2213 line 129327 MATCH x2ea1a800/mask=xbfbffc00 +# C7.2.90 FCVTZS (vector, integer) page C7-2224 line 129963 MATCH x0ea1b800/mask=xbfbffc00 +# C7.2.94 FCVTZU (vector, integer) page C7-2234 line 130576 MATCH x2ea1b800/mask=xbfbffc00 +# CONSTRUCT x4e21a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$trunc@4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@4 +# AUNIT --inst x4e21a800/mask=xdf7fec00 --rand sfp --status fail --comment "nofpround" +# Vector single-precision and double-precision variant SIMD 4S when sz = 0 , Q = 1 + +:^fcvt_vmnemonic Rd_VPR128.4S, Rn_VPR128.4S +is b_31=0 & b_30=1 & b_2428=0b01110 & b_22=0 & b_1321=0b100001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_VPR128.4S & Rn_VPR128.4S & Zd +{ + # simd unary Rd_VPR128.4S = trunc(Rn_VPR128.4S) on lane size 4 + Rd_VPR128.4S[0,32] = trunc(Rn_VPR128.4S[0,32]); + Rd_VPR128.4S[32,32] = trunc(Rn_VPR128.4S[32,32]); + Rd_VPR128.4S[64,32] = trunc(Rn_VPR128.4S[64,32]); + Rd_VPR128.4S[96,32] = trunc(Rn_VPR128.4S[96,32]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.75 FCVTMS (vector) page C7-2186 line 127614 MATCH x0e21b800/mask=xbfbffc00 +# C7.2.77 FCVTMU (vector) page C7-2191 line 127938 MATCH x2e21b800/mask=xbfbffc00 +# C7.2.80 FCVTNS (vector) page C7-2198 line 128355 MATCH x0e21a800/mask=xbfbffc00 +# C7.2.82 FCVTNU (vector) page C7-2203 line 128679 MATCH x2e21a800/mask=xbfbffc00 +# C7.2.84 FCVTPS (vector) page C7-2208 line 129003 MATCH x0ea1a800/mask=xbfbffc00 +# C7.2.86 FCVTPU (vector) page C7-2213 line 129327 MATCH x2ea1a800/mask=xbfbffc00 +# C7.2.90 FCVTZS (vector, integer) page C7-2224 line 129963 MATCH x0ea1b800/mask=xbfbffc00 +# C7.2.94 FCVTZU (vector, integer) page C7-2234 line 130576 MATCH x2ea1b800/mask=xbfbffc00 +# CONSTRUCT x4e61a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$trunc@8 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@8 +# AUNIT --inst x4e61a800/mask=xdf7fec00 --rand dfp --status fail --comment "nofpround" +# Vector single-precision and double-precision variant SIMD 2D when sz = 1 , Q = 1 + +:^fcvt_vmnemonic Rd_VPR128.2D, Rn_VPR128.2D +is b_31=0 & b_30=1 & b_2428=0b01110 & b_22=1 & b_1321=0b100001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_VPR128.2D & Rn_VPR128.2D & Zd +{ + # simd unary Rd_VPR128.2D = trunc(Rn_VPR128.2D) on lane size 8 + Rd_VPR128.2D[0,64] = trunc(Rn_VPR128.2D[0,64]); + Rd_VPR128.2D[64,64] = trunc(Rn_VPR128.2D[64,64]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.76 FCVTMS (scalar) page C7-2189 line 127807 MATCH x1e300000/mask=x7f3ffc00 +# C7.2.78 FCVTMU (scalar) page C7-2194 line 128131 MATCH x1e310000/mask=x7f3ffc00 +# C7.2.81 FCVTNS (scalar) page C7-2201 line 128548 MATCH x1e200000/mask=x7f3ffc00 +# C7.2.83 FCVTNU (scalar) page C7-2206 line 128872 MATCH x1e210000/mask=x7f3ffc00 +# C7.2.85 FCVTPS (scalar) page C7-2211 line 129196 MATCH x1e280000/mask=x7f3ffc00 +# C7.2.87 FCVTPU (scalar) page C7-2216 line 129520 MATCH x1e290000/mask=x7f3ffc00 +# C7.2.92 FCVTZS (scalar, integer) page C7-2229 line 130291 MATCH x1e380000/mask=x7f3ffc00 +# C7.2.96 FCVTZU (scalar, integer) page C7-2239 line 130904 MATCH x1e390000/mask=x7f3ffc00 +# CONSTRUCT x1ee00000/mask=xffe6fc00 MATCHED 8 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =trunc +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1 +# AUNIT --inst x1ee00000/mask=xffe6fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision to 32-bit variant when sf == 0 && type == 11 + +:^fcvt_smnemonic Rd_GPR32, Rn_FPR16 +is b_31=0 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1718=0b00 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR32 & Rn_FPR16 & Rd_GPR64 +{ + Rd_GPR32 = trunc(Rn_FPR16); + zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64 +} + +# C7.2.76 FCVTMS (scalar) page C7-2189 line 127807 MATCH x1e300000/mask=x7f3ffc00 +# C7.2.78 FCVTMU (scalar) page C7-2194 line 128131 MATCH x1e310000/mask=x7f3ffc00 +# C7.2.81 FCVTNS (scalar) page C7-2201 line 128548 MATCH x1e200000/mask=x7f3ffc00 +# C7.2.83 FCVTNU (scalar) page C7-2206 line 128872 MATCH x1e210000/mask=x7f3ffc00 +# C7.2.85 FCVTPS (scalar) page C7-2211 line 129196 MATCH x1e280000/mask=x7f3ffc00 +# C7.2.87 FCVTPU (scalar) page C7-2216 line 129520 MATCH x1e290000/mask=x7f3ffc00 +# C7.2.92 FCVTZS (scalar, integer) page C7-2229 line 130291 MATCH x1e380000/mask=x7f3ffc00 +# C7.2.96 FCVTZU (scalar, integer) page C7-2239 line 130904 MATCH x1e390000/mask=x7f3ffc00 +# CONSTRUCT x9ee00000/mask=xffe6fc00 MATCHED 8 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =trunc +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1 +# AUNIT --inst x9ee00000/mask=xffe6fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision to 64-bit variant when sf == 1 && type == 11 + +:^fcvt_smnemonic Rd_GPR64, Rn_FPR16 +is b_31=1 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1718=0b00 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR64 & Rn_FPR16 +{ + Rd_GPR64 = trunc(Rn_FPR16); +} + +# C7.2.76 FCVTMS (scalar) page C7-2189 line 127807 MATCH x1e300000/mask=x7f3ffc00 +# C7.2.78 FCVTMU (scalar) page C7-2194 line 128131 MATCH x1e310000/mask=x7f3ffc00 +# C7.2.81 FCVTNS (scalar) page C7-2201 line 128548 MATCH x1e200000/mask=x7f3ffc00 +# C7.2.83 FCVTNU (scalar) page C7-2206 line 128872 MATCH x1e210000/mask=x7f3ffc00 +# C7.2.85 FCVTPS (scalar) page C7-2211 line 129196 MATCH x1e280000/mask=x7f3ffc00 +# C7.2.87 FCVTPU (scalar) page C7-2216 line 129520 MATCH x1e290000/mask=x7f3ffc00 +# C7.2.92 FCVTZS (scalar, integer) page C7-2229 line 130291 MATCH x1e380000/mask=x7f3ffc00 +# C7.2.96 FCVTZU (scalar, integer) page C7-2239 line 130904 MATCH x1e390000/mask=x7f3ffc00 +# CONSTRUCT x1e200000/mask=xffe6fc00 MATCHED 8 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =trunc +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1 +# AUNIT --inst x1e200000/mask=xffe6fc00 --rand sfp --status fail --comment "nofpround" +# Single-precision to 32-bit variant when sf == 0 && type == 00 + +:^fcvt_smnemonic Rd_GPR32, Rn_FPR32 +is b_31=0 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1718=0b00 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR32 & Rn_FPR32 & Rd_GPR64 +{ + Rd_GPR32 = trunc(Rn_FPR32); + zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64 +} + +# C7.2.76 FCVTMS (scalar) page C7-2189 line 127807 MATCH x1e300000/mask=x7f3ffc00 +# C7.2.78 FCVTMU (scalar) page C7-2194 line 128131 MATCH x1e310000/mask=x7f3ffc00 +# C7.2.81 FCVTNS (scalar) page C7-2201 line 128548 MATCH x1e200000/mask=x7f3ffc00 +# C7.2.83 FCVTNU (scalar) page C7-2206 line 128872 MATCH x1e210000/mask=x7f3ffc00 +# C7.2.85 FCVTPS (scalar) page C7-2211 line 129196 MATCH x1e280000/mask=x7f3ffc00 +# C7.2.87 FCVTPU (scalar) page C7-2216 line 129520 MATCH x1e290000/mask=x7f3ffc00 +# C7.2.92 FCVTZS (scalar, integer) page C7-2229 line 130291 MATCH x1e380000/mask=x7f3ffc00 +# C7.2.96 FCVTZU (scalar, integer) page C7-2239 line 130904 MATCH x1e390000/mask=x7f3ffc00 +# CONSTRUCT x9e200000/mask=xffe6fc00 MATCHED 8 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =trunc +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1 +# AUNIT --inst x9e200000/mask=xffe6fc00 --rand sfp --status fail --comment "nofpround" +# Single-precision to 64-bit variant when sf == 1 && type == 00 + +:^fcvt_smnemonic Rd_GPR64, Rn_FPR32 +is b_31=1 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1718=0b00 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR64 & Rn_FPR32 +{ + Rd_GPR64 = trunc(Rn_FPR32); +} + +# C7.2.76 FCVTMS (scalar) page C7-2189 line 127807 MATCH x1e300000/mask=x7f3ffc00 +# C7.2.78 FCVTMU (scalar) page C7-2194 line 128131 MATCH x1e310000/mask=x7f3ffc00 +# C7.2.81 FCVTNS (scalar) page C7-2201 line 128548 MATCH x1e200000/mask=x7f3ffc00 +# C7.2.83 FCVTNU (scalar) page C7-2206 line 128872 MATCH x1e210000/mask=x7f3ffc00 +# C7.2.85 FCVTPS (scalar) page C7-2211 line 129196 MATCH x1e280000/mask=x7f3ffc00 +# C7.2.87 FCVTPU (scalar) page C7-2216 line 129520 MATCH x1e290000/mask=x7f3ffc00 +# C7.2.92 FCVTZS (scalar, integer) page C7-2229 line 130291 MATCH x1e380000/mask=x7f3ffc00 +# C7.2.96 FCVTZU (scalar, integer) page C7-2239 line 130904 MATCH x1e390000/mask=x7f3ffc00 +# CONSTRUCT x1e600000/mask=xffe6fc00 MATCHED 8 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =trunc +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1 +# AUNIT --inst x1e600000/mask=xffe6fc00 --rand dfp --status fail --comment "nofpround" +# Double-precision to 32-bit variant when sf == 0 && type == 01 + +:^fcvt_smnemonic Rd_GPR32, Rn_FPR64 +is b_31=0 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1718=0b00 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR32 & Rn_FPR64 & Rd_GPR64 +{ + Rd_GPR32 = trunc(Rn_FPR64); + zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64 +} + +# C7.2.76 FCVTMS (scalar) page C7-2189 line 127807 MATCH x1e300000/mask=x7f3ffc00 +# C7.2.78 FCVTMU (scalar) page C7-2194 line 128131 MATCH x1e310000/mask=x7f3ffc00 +# C7.2.81 FCVTNS (scalar) page C7-2201 line 128548 MATCH x1e200000/mask=x7f3ffc00 +# C7.2.83 FCVTNU (scalar) page C7-2206 line 128872 MATCH x1e210000/mask=x7f3ffc00 +# C7.2.85 FCVTPS (scalar) page C7-2211 line 129196 MATCH x1e280000/mask=x7f3ffc00 +# C7.2.87 FCVTPU (scalar) page C7-2216 line 129520 MATCH x1e290000/mask=x7f3ffc00 +# C7.2.92 FCVTZS (scalar, integer) page C7-2229 line 130291 MATCH x1e380000/mask=x7f3ffc00 +# C7.2.96 FCVTZU (scalar, integer) page C7-2239 line 130904 MATCH x1e390000/mask=x7f3ffc00 +# CONSTRUCT x9e600000/mask=xffe6fc00 MATCHED 8 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =trunc +# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1 +# AUNIT --inst x9e600000/mask=xffe6fc00 --rand dfp --status fail --comment "nofpround" +# Double-precision to 64-bit variant sf == 1 && type == 01 + +:^fcvt_smnemonic Rd_GPR64, Rn_FPR64 +is b_31=1 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1718=0b00 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR64 & Rn_FPR64 +{ + Rd_GPR64 = trunc(Rn_FPR64); +} + +# C7.2.79 FCVTN, FCVTN2 page C7-2196 line 128262 MATCH x0e216800/mask=xbfbffc00 +# CONSTRUCT x0e616800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =var =$float2float@8:8 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtn/2@8 +# AUNIT --inst x0e616800/mask=xfffffc00 --rand sfp --status fail --comment "ext nofpround" + +:fcvtn Rd_VPR64.2S, Rn_VPR128.2D +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x16 & b_1011=2 & Rn_VPR128.2D & Rd_VPR64.2S & Rd_VPR128 & Zd +{ + TMPQ1 = Rn_VPR128.2D; + # simd resize Rd_VPR64.2S = float2float(TMPQ1) (lane size 8 to 4) + Rd_VPR64.2S[0,32] = float2float(TMPQ1[0,64]); + Rd_VPR64.2S[32,32] = float2float(TMPQ1[64,64]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.79 FCVTN, FCVTN2 page C7-2196 line 128262 MATCH x0e216800/mask=xbfbffc00 +# CONSTRUCT x4e616800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $float2float@8:8 1:1 &=$copy +# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtn2/2@8 +# AUNIT --inst x4e616800/mask=xfffffc00 --rand sfp --status pass --comment "ext nofpround" + +:fcvtn2 Rd_VPR128.4S, Rn_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x16 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.4S & Zd +{ + # simd resize TMPD1 = float2float(Rn_VPR128.2D) (lane size 8 to 4) + TMPD1[0,32] = float2float(Rn_VPR128.2D[0,64]); + TMPD1[32,32] = float2float(Rn_VPR128.2D[64,64]); + # simd copy Rd_VPR128.4S element 1:1 = TMPD1 (lane size 8) + Rd_VPR128.4S[64,64] = TMPD1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.79 FCVTN, FCVTN2 page C7-2196 line 128262 MATCH x0e216800/mask=xbfbffc00 +# CONSTRUCT x0e216800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =var =$float2float@4:8 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtn/2@4 +# AUNIT --inst x0e216800/mask=xfffffc00 --rand hfp --status fail --comment "ext nofpround" + +:fcvtn Rd_VPR64.4H, Rn_VPR128.4S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x16 & b_1011=2 & Rn_VPR128.4S & Rd_VPR64.4H & Rd_VPR128 & Zd +{ + TMPQ1 = Rn_VPR128.4S; + # simd resize Rd_VPR64.4H = float2float(TMPQ1) (lane size 4 to 2) + Rd_VPR64.4H[0,16] = float2float(TMPQ1[0,32]); + Rd_VPR64.4H[16,16] = float2float(TMPQ1[32,32]); + Rd_VPR64.4H[32,16] = float2float(TMPQ1[64,32]); + Rd_VPR64.4H[48,16] = float2float(TMPQ1[96,32]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.79 FCVTN, FCVTN2 page C7-2196 line 128262 MATCH x0e216800/mask=xbfbffc00 +# CONSTRUCT x4e216800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $float2float@4:8 1:1 &=$copy +# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtn2/2@4 +# AUNIT --inst x4e216800/mask=xfffffc00 --rand hfp --status fail --comment "ext nofpround" + +:fcvtn2 Rd_VPR128.8H, Rn_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x16 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.8H & Zd +{ + # simd resize TMPD1 = float2float(Rn_VPR128.4S) (lane size 4 to 2) + TMPD1[0,16] = float2float(Rn_VPR128.4S[0,32]); + TMPD1[16,16] = float2float(Rn_VPR128.4S[32,32]); + TMPD1[32,16] = float2float(Rn_VPR128.4S[64,32]); + TMPD1[48,16] = float2float(Rn_VPR128.4S[96,32]); + # simd copy Rd_VPR128.8H element 1:1 = TMPD1 (lane size 8) + Rd_VPR128.8H[64,64] = TMPD1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.88 FCVTXN, FCVTXN2 page C7-2218 line 129651 MATCH x7e216800/mask=xffbffc00 +# CONSTRUCT x7e616800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =float2float +# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtxn/2 +# AUNIT --inst x7e616800/mask=xfffffc00 --rand sfp --status fail --comment "nofpround" + +:fcvtxn Rd_FPR32, Rn_FPR64 +is b_2331=0b011111100 & b_22=1 & b_1021=0b100001011010 & Rd_FPR32 & Rn_FPR64 & Zd +{ + Rd_FPR32 = float2float(Rn_FPR64); + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.88 FCVTXN, FCVTXN2 page C7-2218 line 129651 MATCH x2e216800/mask=xbfbffc00 +# CONSTRUCT x2e616800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =var =$float2float@8:8 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtxn/2@8 +# AUNIT --inst x2e616800/mask=xfffffc00 --rand sfp --status fail --comment "ext nofpround" +# Vector Variant + +:fcvtxn Rd_VPR64.2S, Rn_VPR128.2D +is b_31=0 & b_30=0 & b_2329=0b1011100 & b_22=1 & b_1021=0b100001011010 & Rd_VPR64.2S & Rd_VPR128 & Rn_VPR128.2D & Zd +{ + TMPQ1 = Rn_VPR128.2D; + # simd resize Rd_VPR64.2S = float2float(TMPQ1) (lane size 8 to 4) + Rd_VPR64.2S[0,32] = float2float(TMPQ1[0,64]); + Rd_VPR64.2S[32,32] = float2float(TMPQ1[64,64]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.88 FCVTXN, FCVTXN2 page C7-2218 line 129651 MATCH x2e216800/mask=xbfbffc00 +# CONSTRUCT x6e616800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $float2float@8:8 1:1 &=$copy +# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtxn2/2@8 +# AUNIT --inst x6e616800/mask=xfffffc00 --rand sfp --status fail --comment "ext nofpround" +# Vector Variant + +:fcvtxn2 Rd_VPR128.4S, Rn_VPR128.2D +is b_31=0 & b_30=1 & b_2329=0b1011100 & b_22=1 & b_1021=0b100001011010 & Rd_VPR128.4S & Rn_VPR128.2D & Rd_VPR128 & Zd +{ + # simd resize TMPD1 = float2float(Rn_VPR128.2D) (lane size 8 to 4) + TMPD1[0,32] = float2float(Rn_VPR128.2D[0,64]); + TMPD1[32,32] = float2float(Rn_VPR128.2D[64,64]); + # simd copy Rd_VPR128.4S element 1:1 = TMPD1 (lane size 8) + Rd_VPR128.4S[64,64] = TMPD1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x5f00fc00/mask=xff80fc00 +# CONSTRUCT x5f40fc00/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 zext:8 =NEON_fcvtzs/2 +# AUNIT --inst x5f40fc00/mask=xffc0fc00 --rand dfp --status nopcodeop --comment "nofpround" +# Scalar variant when immh=1xxx + +:fcvtzs Rd_FPR64, Rn_FPR64, Imm_shr_imm64 +is b_2331=0b010111110 & b_22=1 & b_1015=0b111111 & Imm_shr_imm64 & Rn_FPR64 & Rd_FPR64 & Zd +{ + local tmp1:8 = zext(Imm_shr_imm64); + Rd_FPR64 = NEON_fcvtzs(Rn_FPR64, tmp1); +} + +# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x5f00fc00/mask=xff80fc00 +# CONSTRUCT x5f20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_fcvtzs/2 +# AUNIT --inst x5f20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" +# Scalar variant when immh=01xx + +:fcvtzs Rd_FPR32, Rn_FPR32, Imm_shr_imm32 +is b_2331=0b010111110 & b_2122=0b01 & b_1015=0b111111 & Imm_shr_imm32 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_fcvtzs(Rn_FPR32, Imm_shr_imm32:4); +} + +# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x5f00fc00/mask=xff80fc00 +# CONSTRUCT x5f10fc00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzs/2 +# AUNIT --inst x5f10fc00/mask=xfff0fc00 --rand hfp --status noqemu --comment "nofpround" +# Scalar variant when immh=001x + +:fcvtzs Rd_FPR16, Rn_FPR16, Imm_shr_imm16 +is b_2331=0b010111110 & b_2022=0b001 & b_1015=0b111111 & Imm_shr_imm16 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_fcvtzs(Rn_FPR16, Imm_shr_imm16); +} + +# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x0f00fc00/mask=xbf80fc00 +# CONSTRUCT x4f40fc00/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 zext:8 =NEON_fcvtzs/2@8 +# AUNIT --inst x4f40fc00/mask=xffc0fc00 --rand dfp --status nopcodeop --comment "nofpround" +# Vector 2D variant when immh=1xxx Q=1 bb=b_22 cc=1 V=VPR128.2D imm=Imm_shr_imm64 + +:fcvtzs Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64 +is b_31=0 & b_30=1 & b_2329=0b0011110 & b_22=1 & b_1015=0b111111 & Rd_VPR128.2D & Rn_VPR128.2D & Imm_shr_imm64 & Zd +{ + local tmp1:8 = zext(Imm_shr_imm64); + Rd_VPR128.2D = NEON_fcvtzs(Rn_VPR128.2D, tmp1, 8:1); +} + +# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x0f00fc00/mask=xbf80fc00 +# CONSTRUCT x0f20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_fcvtzs/2@4 +# AUNIT --inst x0f20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" +# Vector 2S variant when immh=01xx Q=0 bb=b_2122 cc=0b01 V=VPR64.2S imm=Imm_shr_imm32 + +:fcvtzs Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32 +is b_31=0 & b_30=0 & b_2329=0b0011110 & b_2122=0b01 & b_1015=0b111111 & Rd_VPR64.2S & Rn_VPR64.2S & Imm_shr_imm32 & Zd +{ + Rd_VPR64.2S = NEON_fcvtzs(Rn_VPR64.2S, Imm_shr_imm32:4, 4:1); +} + +# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x0f00fc00/mask=xbf80fc00 +# CONSTRUCT x4f20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_fcvtzs/2@4 +# AUNIT --inst x4f20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" +# Vector 4S variant when immh=01xx Q=1 bb=b_2122 cc=0b01 V=VPR128.4S imm=Imm_shr_imm32 + +:fcvtzs Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32 +is b_31=0 & b_30=1 & b_2329=0b0011110 & b_2122=0b01 & b_1015=0b111111 & Rd_VPR128.4S & Rn_VPR128.4S & Imm_shr_imm32 & Zd +{ + Rd_VPR128.4S = NEON_fcvtzs(Rn_VPR128.4S, Imm_shr_imm32:4, 4:1); +} + +# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x0f00fc00/mask=xbf80fc00 +# CONSTRUCT x0f10fc00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzs/2@2 +# AUNIT --inst x0f10fc00/mask=xfff0fc00 --rand hfp --status noqemu --comment "nofpround" +# Vector 4H variant when immh=001x Q=0 bb=b_2022 cc=0b001 V=VPR64.4H imm=Imm_shr_imm16 + +:fcvtzs Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16 +is b_31=0 & b_30=0 & b_2329=0b0011110 & b_2022=0b001 & b_1015=0b111111 & Rd_VPR64.4H & Rn_VPR64.4H & Imm_shr_imm16 & Zd +{ + Rd_VPR64.4H = NEON_fcvtzs(Rn_VPR64.4H, Imm_shr_imm16, 2:1); +} + +# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x0f00fc00/mask=xbf80fc00 +# CONSTRUCT x4f10fc00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzs/2@2 +# AUNIT --inst x4f10fc00/mask=xfff0fc00 --rand hfp --status noqemu --comment "nofpround" +# Vector 8H variant when immh=001x Q=1 bb=b_2022 cc=0b001 V=VPR128.8H imm=Imm_shr_imm16 + +:fcvtzs Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16 +is b_31=0 & b_30=1 & b_2329=0b0011110 & b_2022=0b001 & b_1015=0b111111 & Rd_VPR128.8H & Rn_VPR128.8H & Imm_shr_imm16 & Zd +{ + Rd_VPR128.8H = NEON_fcvtzs(Rn_VPR128.8H, Imm_shr_imm16, 2:1); +} + +# C7.2.91 FCVTZS (scalar, fixed-point) page C7-2227 line 130156 MATCH x1e180000/mask=x7f3f0000 +# CONSTRUCT x1ed88000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 FBits16 f* =trunc +# SMACRO(pseudo) ARG1 ARG2 FBits16 =NEON_fcvtzs/2 +# AUNIT --inst x1ed88000/mask=xffff8000 --rand hfp --status noqemu --comment "nofpround" +# if sf == '0' && scale<5> == '0' then UnallocatedEncoding(); +# Half-precision to 32-bit variant when sf == 0 && type == 11 G=GPR32 V=FPR16 size=2 fbits=FBits16 + +:fcvtzs Rd_GPR32, Rn_FPR16, FBitsOp +is b_31=0 & b_2430=0b0011110 & b_2223=0b11 & b_1621=0b011000 & b_15=1 & Rd_GPR32 & Rn_FPR16 & FBitsOp & FBits16 & Rd_GPR64 +{ + local tmp1:2 = Rn_FPR16 f* FBits16; + Rd_GPR32 = trunc(tmp1); + zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64 +} + +# C7.2.91 FCVTZS (scalar, fixed-point) page C7-2227 line 130156 MATCH x1e180000/mask=x7f3f0000 +# CONSTRUCT x9ed80000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 f* =trunc +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzs/2 +# AUNIT --inst x9ed80000/mask=xffff0000 --rand hfp --status noqemu --comment "nofpround" +# Half-precision to 64-bit variant when sf == 1 && type == 11 G=GPR64 V=FPR16 size=2 fbits=FBits16 + +:fcvtzs Rd_GPR64, Rn_FPR16, FBitsOp +is b_31=1 & b_2430=0b0011110 & b_2223=0b11 & b_1621=0b011000 & Rd_GPR64 & Rn_FPR16 & FBitsOp & FBits16 +{ + local tmp1:2 = Rn_FPR16 f* FBitsOp; + Rd_GPR64 = trunc(tmp1); +} + +# C7.2.91 FCVTZS (scalar, fixed-point) page C7-2227 line 130156 MATCH x1e180000/mask=x7f3f0000 +# CONSTRUCT x1e188000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 FBits32 f* =trunc +# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_fcvtzs/2 +# AUNIT --inst x1e188000/mask=xffff8000 --rand sfp --status fail --comment "nofpround" +# Single-precision to 32-bit variant when sf == 0 && type == 00 G=GPR32 V=FPR32 size=4 fbits=FBits32 + +:fcvtzs Rd_GPR32, Rn_FPR32, FBitsOp +is b_31=0 & b_2430=0b0011110 & b_2223=0b00 & b_1621=0b011000 & b_15=1 & Rd_GPR32 & Rn_FPR32 & FBitsOp & FBits32 & Rd_GPR64 +{ + local tmp1:4 = Rn_FPR32 f* FBits32; + Rd_GPR32 = trunc(tmp1); + zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64 +} + +# C7.2.91 FCVTZS (scalar, fixed-point) page C7-2227 line 130156 MATCH x1e180000/mask=x7f3f0000 +# CONSTRUCT x9e180000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 FBits32 f* =trunc +# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_fcvtzs/2 +# AUNIT --inst x9e180000/mask=xffff0000 --rand sfp --status pass --comment "nofpround" +# Single-precision to 64-bit variant when sf == 1 && type == 00 G=GPR64 V=FPR32 size=4 fbits=FBits32 + +:fcvtzs Rd_GPR64, Rn_FPR32, FBitsOp +is b_31=1 & b_2430=0b0011110 & b_2223=0b00 & b_1621=0b011000 & Rd_GPR64 & Rn_FPR32 & FBitsOp & FBits32 +{ + local tmp1:4 = Rn_FPR32 f* FBits32; + Rd_GPR64 = trunc(tmp1); +} + +# C7.2.91 FCVTZS (scalar, fixed-point) page C7-2227 line 130156 MATCH x1e180000/mask=x7f3f0000 +# CONSTRUCT x1e588000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 FBits64 f* =trunc +# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_fcvtzs/2 +# AUNIT --inst x1e588000/mask=xffff8000 --rand dfp --status fail --comment "nofpround" +# Double-precision to 32-bit variant when sf == 0 && type == 01 G=GPR32 V=FPR64 size=8 fbits=FBits64 + +:fcvtzs Rd_GPR32, Rn_FPR64, FBitsOp +is b_31=0 & b_2430=0b0011110 & b_2223=0b01 & b_1621=0b011000 & b_15=1 & Rd_GPR32 & Rn_FPR64 & FBitsOp & FBits64 & Rd_GPR64 +{ + local tmp1:8 = Rn_FPR64 f* FBits64; + Rd_GPR32 = trunc(tmp1); + zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64 +} + +# C7.2.91 FCVTZS (scalar, fixed-point) page C7-2227 line 130156 MATCH x1e180000/mask=x7f3f0000 +# CONSTRUCT x9e580000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 FBits64 f* =trunc +# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_fcvtzs/2 +# AUNIT --inst x9e580000/mask=xffff0000 --rand dfp --status pass --comment "nofpround" +# Double-precision to 64-bit variant when sf == 1 && type == 01 G=GPR64 V=FPR64 size=8 fbits=FBits64 + +:fcvtzs Rd_GPR64, Rn_FPR64, FBitsOp +is b_31=1 & b_2430=0b0011110 & b_2223=0b01 & b_1621=0b011000 & Rd_GPR64 & Rn_FPR64 & FBitsOp & FBits64 +{ + local tmp1:8 = Rn_FPR64 f* FBits64; + Rd_GPR64 = trunc(tmp1); +} + +# C7.2.93 FCVTZU (vector, fixed-point) page C7-2231 line 130422 MATCH x2f00fc00/mask=xbf80fc00 +# CONSTRUCT x6f40fc00/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 zext:8 =NEON_fcvtzu/2@8 +# AUNIT --inst x6f40fc00/mask=xffc0fc00 --rand dfp --status nopcodeop --comment "nofpround" + +:fcvtzu Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x1f & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + local tmp1:8 = zext(Imm_shr_imm64); + Rd_VPR128.2D = NEON_fcvtzu(Rn_VPR128.2D, tmp1, 8:1); +} + +# C7.2.93 FCVTZU (vector, fixed-point) page C7-2231 line 130422 MATCH x2f00fc00/mask=xbf80fc00 +# CONSTRUCT x2f20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_fcvtzu/2@4 +# AUNIT --inst x2f20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fcvtzu Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x1f & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_fcvtzu(Rn_VPR64.2S, Imm_shr_imm32:4, 4:1); +} + +# C7.2.93 FCVTZU (vector, fixed-point) page C7-2231 line 130422 MATCH x2f00fc00/mask=xbf80fc00 +# CONSTRUCT x6f20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_fcvtzu/2@4 +# AUNIT --inst x6f20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fcvtzu Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x1f & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_fcvtzu(Rn_VPR128.4S, Imm_shr_imm32:4, 4:1); +} + +# C7.2.93 FCVTZU (vector, fixed-point) page C7-2231 line 130422 MATCH x2f00fc00/mask=xbf80fc00 +# CONSTRUCT x2f10fc00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2@2 +# AUNIT --inst x2f10fc00/mask=xfff0fc00 --rand hfp --status noqemu --comment "nofpround" + +:fcvtzu Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=1 & Imm_shr_imm16 & b_1115=0x1f & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_fcvtzu(Rn_VPR64.4H, Imm_shr_imm16, 2:1); +} + +# C7.2.93 FCVTZU (vector, fixed-point) page C7-2231 line 130422 MATCH x2f00fc00/mask=xbf80fc00 +# CONSTRUCT x6f10fc00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2@2 +# AUNIT --inst x6f10fc00/mask=xfff0fc00 --rand hfp --status noqemu --comment "nofpround" + +:fcvtzu Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=1 & Imm_shr_imm16 & b_1115=0x1f & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_fcvtzu(Rn_VPR128.8H, Imm_shr_imm16, 2:1); +} + +# C7.2.93 FCVTZU (vector, fixed-point) page C7-2231 line 130422 MATCH x7f00fc00/mask=xff80fc00 +# CONSTRUCT x7f10fc00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 1:2 ARG3 << int2float:2 f* fabs =trunc +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2 +# AUNIT --inst x7f10fc00/mask=xfff0fc00 --rand hfp --status noqemu --comment "nofpround" +# FCVTZU (vector, fixed-point) Scalar immh=001x + +:fcvtzu Rd_FPR16, Rn_FPR16, Imm_shr_imm32 +is b_2331=0b011111110 & b_2022=0b001 & b_1015=0b111111 & Imm_shr_imm32 & Rn_FPR16 & Rd_FPR16 & Zd +{ + local tmp1:2 = 1:2 << Imm_shr_imm32; + local tmp2:2 = int2float(tmp1); + local tmp3:2 = Rn_FPR16 f* tmp2; + local tmp4:2 = abs(tmp3); + Rd_FPR16 = trunc(tmp4); + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.93 FCVTZU (vector, fixed-point) page C7-2231 line 130422 MATCH x7f00fc00/mask=xff80fc00 +# CONSTRUCT x7f20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 1:4 ARG3:4 << int2float:4 f* fabs =trunc +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2 +# AUNIT --inst x7f20fc00/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround" +# FCVTZU (vector, fixed-point) Scalar immh=01xx + +:fcvtzu Rd_FPR32, Rn_FPR32, Imm_shr_imm32 +is b_2331=0b011111110 & b_2122=0b01 & b_1015=0b111111 & Imm_shr_imm32 & Rn_FPR32 & Rd_FPR32 & Zd +{ + local tmp1:4 = 1:4 << Imm_shr_imm32:4; + local tmp2:4 = int2float(tmp1); + local tmp3:4 = Rn_FPR32 f* tmp2; + local tmp4:4 = abs(tmp3); + Rd_FPR32 = trunc(tmp4); + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.93 FCVTZU (vector, fixed-point) page C7-2231 line 130422 MATCH x7f00fc00/mask=xff80fc00 +# CONSTRUCT x7f40fc00/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 1:8 ARG3 zext:8 << int2float:8 f* fabs =trunc +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2 +# AUNIT --inst x7f40fc00/mask=xffc0fc00 --rand dfp --status fail --comment "nofpround" +# FCVTZU (vector, fixed-point) Scalar immh=1xxx + +:fcvtzu Rd_FPR64, Rn_FPR64, Imm_shr_imm32 +is b_2331=0b011111110 & b_22=1 & b_1015=0b111111 & Imm_shr_imm32 & Rn_FPR64 & Rd_FPR64 & Zd +{ + local tmp1:8 = zext(Imm_shr_imm32); + local tmp2:8 = 1:8 << tmp1; + local tmp3:8 = int2float(tmp2); + local tmp4:8 = Rn_FPR64 f* tmp3; + local tmp5:8 = abs(tmp4); + Rd_FPR64 = trunc(tmp5); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.95 FCVTZU (scalar, fixed-point) page C7-2237 line 130769 MATCH x1e190000/mask=x7f3f0000 +# CONSTRUCT x1ed98000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 f* =trunc +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2 +# AUNIT --inst x1ed98000/mask=xffff8000 --rand hfp --status noqemu --comment "nofpround" + +:fcvtzu Rd_GPR32, Rn_FPR16, FBitsOp +is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=0 & mode=3 & fpOpcode=1 & b_15=1 & FBitsOp & FBits16 & Rn_FPR16 & Rd_GPR32 & Rd_GPR64 +{ + local tmp1:2 = Rn_FPR16 f* FBitsOp; + Rd_GPR32 = trunc(tmp1); + zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64 +} + +# C7.2.95 FCVTZU (scalar, fixed-point) page C7-2237 line 130769 MATCH x1e190000/mask=x7f3f0000 +# CONSTRUCT x9ed90000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 f* =trunc +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2 +# AUNIT --inst x9ed90000/mask=xffff0000 --rand hfp --status noqemu --comment "nofpround" + +:fcvtzu Rd_GPR64, Rn_FPR16, FBitsOp +is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=0 & mode=3 & fpOpcode=1 & FBitsOp & FBits16 & Rn_FPR16 & Rd_GPR64 +{ + local tmp1:2 = Rn_FPR16 f* FBitsOp; + Rd_GPR64 = trunc(tmp1); +} + +# C7.2.95 FCVTZU (scalar, fixed-point) page C7-2237 line 130769 MATCH x1e190000/mask=x7f3f0000 +# CONSTRUCT x1e598000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 FBits64 f* =trunc +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2 +# AUNIT --inst x1e598000/mask=xffff8000 --rand dfp --status fail --comment "nofpround" + +:fcvtzu Rd_GPR32, Rn_FPR64, FBitsOp +is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=0 & mode=3 & fpOpcode=1 & b_15=1 & FBitsOp & FBits64 & Rn_FPR64 & Rd_GPR32 & Rd_GPR64 +{ + local tmp1:8 = Rn_FPR64 f* FBits64; + Rd_GPR32 = trunc(tmp1); + zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64 +} + +# C7.2.95 FCVTZU (scalar, fixed-point) page C7-2237 line 130769 MATCH x1e190000/mask=x7f3f0000 +# CONSTRUCT x1e198000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 FBits32 f* =trunc +# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_fcvtzu/2 +# AUNIT --inst x1e198000/mask=xffff8000 --rand sfp --status fail --comment "nofpround" + +:fcvtzu Rd_GPR32, Rn_FPR32, FBitsOp +is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=0 & mode=3 & fpOpcode=1 & b_15=1 & FBitsOp & FBits32 & Rn_FPR32 & Rd_GPR32 & Rd_GPR64 +{ + local tmp1:4 = Rn_FPR32 f* FBits32; + Rd_GPR32 = trunc(tmp1); + zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64 +} + +# C7.2.95 FCVTZU (scalar, fixed-point) page C7-2237 line 130769 MATCH x1e190000/mask=x7f3f0000 +# CONSTRUCT x9e590000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 FBits64 f* =trunc +# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_fcvtzu/2 +# AUNIT --inst x9e590000/mask=xffff0000 --rand dfp --status fail --comment "nofpround" + +:fcvtzu Rd_GPR64, Rn_FPR64, FBitsOp +is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=0 & mode=3 & fpOpcode=1 & FBitsOp & FBits64 & Rn_FPR64 & Rd_GPR64 +{ + local tmp1:8 = Rn_FPR64 f* FBits64; + Rd_GPR64 = trunc(tmp1); +} + +# C7.2.95 FCVTZU (scalar, fixed-point) page C7-2237 line 130769 MATCH x1e190000/mask=x7f3f0000 +# CONSTRUCT x9e190000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 FBits32 f* =trunc +# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_fcvtzu/2 +# AUNIT --inst x9e190000/mask=xffff0000 --rand sfp --status fail --comment "nofpround" + +:fcvtzu Rd_GPR64, Rn_FPR32, FBitsOp +is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=0 & mode=3 & fpOpcode=1 & FBitsOp & FBits32 & Rn_FPR32 & Rd_GPR64 +{ + local tmp1:4 = Rn_FPR32 f* FBits32; + Rd_GPR64 = trunc(tmp1); +} + +# C7.2.97 FDIV (vector) page C7-2241 line 131035 MATCH x2e20fc00/mask=xbfa0fc00 +# CONSTRUCT x6e60fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f/@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2@8 +# AUNIT --inst x6e60fc00/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround" + +:fdiv Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1f & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + # simd infix Rd_VPR128.2D = Rn_VPR128.2D f/ Rm_VPR128.2D on lane size 8 + Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] f/ Rm_VPR128.2D[0,64]; + Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] f/ Rm_VPR128.2D[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.97 FDIV (vector) page C7-2241 line 131035 MATCH x2e20fc00/mask=xbfa0fc00 +# CONSTRUCT x2e20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f/@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2@4 +# AUNIT --inst x2e20fc00/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround" + +:fdiv Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1f & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + # simd infix Rd_VPR64.2S = Rn_VPR64.2S f/ Rm_VPR64.2S on lane size 4 + Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] f/ Rm_VPR64.2S[0,32]; + Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] f/ Rm_VPR64.2S[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.97 FDIV (vector) page C7-2241 line 131035 MATCH x2e20fc00/mask=xbfa0fc00 +# CONSTRUCT x6e20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f/@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2@4 +# AUNIT --inst x6e20fc00/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround" + +:fdiv Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1f & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd infix Rd_VPR128.4S = Rn_VPR128.4S f/ Rm_VPR128.4S on lane size 4 + Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] f/ Rm_VPR128.4S[0,32]; + Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] f/ Rm_VPR128.4S[32,32]; + Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] f/ Rm_VPR128.4S[64,32]; + Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] f/ Rm_VPR128.4S[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.97 FDIV (vector) page C7-2241 line 131035 MATCH x2e403c00/mask=xbfe0fc00 +# CONSTRUCT x2e403c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f/@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2@2 +# AUNIT --inst x2e403c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 4H when Q = 0 + +:fdiv Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b001111 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + # simd infix Rd_VPR64.4H = Rn_VPR64.4H f/ Rm_VPR64.4H on lane size 2 + Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f/ Rm_VPR64.4H[0,16]; + Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f/ Rm_VPR64.4H[16,16]; + Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f/ Rm_VPR64.4H[32,16]; + Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f/ Rm_VPR64.4H[48,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.97 FDIV (vector) page C7-2241 line 131035 MATCH x2e403c00/mask=xbfe0fc00 +# CONSTRUCT x6e403c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f/@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2@2 +# AUNIT --inst x6e403c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 8H when Q = 1 + +:fdiv Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b001111 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + # simd infix Rd_VPR128.8H = Rn_VPR128.8H f/ Rm_VPR128.8H on lane size 2 + Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f/ Rm_VPR128.8H[0,16]; + Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f/ Rm_VPR128.8H[16,16]; + Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f/ Rm_VPR128.8H[32,16]; + Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f/ Rm_VPR128.8H[48,16]; + Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f/ Rm_VPR128.8H[64,16]; + Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f/ Rm_VPR128.8H[80,16]; + Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f/ Rm_VPR128.8H[96,16]; + Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f/ Rm_VPR128.8H[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.98 FDIV (scalar) page C7-2243 line 131150 MATCH x1e201800/mask=xff20fc00 +# CONSTRUCT x1e601800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =f/ +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2 +# AUNIT --inst x1e601800/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround" + +:fdiv Rd_FPR64, Rn_FPR64, Rm_FPR64 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x1 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = Rn_FPR64 f/ Rm_FPR64; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.98 FDIV (scalar) page C7-2243 line 131150 MATCH x1e201800/mask=xff20fc00 +# CONSTRUCT x1e201800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =f/ +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2 +# AUNIT --inst x1e201800/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround" + +:fdiv Rd_FPR32, Rn_FPR32, Rm_FPR32 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x1 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = Rn_FPR32 f/ Rm_FPR32; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.98 FDIV (scalar) page C7-2243 line 131150 MATCH x1e201800/mask=xff20fc00 +# CONSTRUCT x1ee01800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =f/ +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2 +# AUNIT --inst x1ee01800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" + +:fdiv Rd_FPR16, Rn_FPR16, Rm_FPR16 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x1 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = Rn_FPR16 f/ Rm_FPR16; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.99 FJCVTZS page C7-2245 line 131259 MATCH x1e7e0000/mask=xfffffc00 +# CONSTRUCT x1e7e0000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =trunc +# SMACRO(pseudo) ARG1 ARG2 =NEON_fjcvtzs/1 +# AUNIT --inst x1e7e0000/mask=xfffffc00 --rand dfp --status noqemu --comment "nofpround" + +:fjcvtzs Rd_GPR32, Rn_FPR64 +is b_1031=0b0001111001111110000000 & Rd_GPR32 & Rn_FPR64 & Rd_GPR64 +{ + Rd_GPR32 = trunc(Rn_FPR64); + zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64 +} + +# C7.2.100 FMADD page C7-2246 line 131323 MATCH x1f000000/mask=xff208000 +# CONSTRUCT x1f400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fmadd/3 +# AUNIT --inst x1f400000/mask=xffe08000 --rand dfp --status nopcodeop --comment "nofpround" + +:fmadd Rd_FPR64, Rn_FPR64, Rm_FPR64, Ra_FPR64 +is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=1 & b_21=0 & Rm_FPR64 & b_15=0 & Ra_FPR64 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_fmadd(Rn_FPR64, Rm_FPR64, Ra_FPR64); +} + +# C7.2.100 FMADD page C7-2246 line 131323 MATCH x1f000000/mask=xff208000 +# CONSTRUCT x1f000000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fmadd/3 +# AUNIT --inst x1f000000/mask=xffe08000 --rand sfp --status nopcodeop --comment "nofpround" + +:fmadd Rd_FPR32, Rn_FPR32, Rm_FPR32, Ra_FPR32 +is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=0 & b_21=0 & Rm_FPR32 & b_15=0 & Ra_FPR32 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_fmadd(Rn_FPR32, Rm_FPR32, Ra_FPR32); +} + +# C7.2.100 FMADD page C7-2246 line 131323 MATCH x1f000000/mask=xff208000 +# CONSTRUCT x1fc00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fmadd/3 +# AUNIT --inst x1fc00000/mask=xffe08000 --rand hfp --status noqemu --comment "nofpround" + +:fmadd Rd_FPR16, Rn_FPR16, Rm_FPR16, Ra_FPR16 +is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=3 & b_21=0 & Rm_FPR16 & b_15=0 & Ra_FPR16 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_fmadd(Rn_FPR16, Rm_FPR16, Ra_FPR16); +} + +# C7.2.101 FMAX (vector) page C7-2248 line 131451 MATCH x0e20f400/mask=xbfa0fc00 +# CONSTRUCT x4e60f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2@8 +# AUNIT --inst x4e60f400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround" + +:fmax Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1e & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_fmax(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.101 FMAX (vector) page C7-2248 line 131451 MATCH x0e20f400/mask=xbfa0fc00 +# CONSTRUCT x0e20f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2@4 +# AUNIT --inst x0e20f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fmax Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1e & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_fmax(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.101 FMAX (vector) page C7-2248 line 131451 MATCH x0e20f400/mask=xbfa0fc00 +# CONSTRUCT x4e20f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2@4 +# AUNIT --inst x4e20f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fmax Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1e & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_fmax(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.101 FMAX (vector) page C7-2248 line 131451 MATCH x0e403400/mask=xbfe0fc00 +# CONSTRUCT x0e403400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2@2 +# AUNIT --inst x0e403400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 4H when Q = 0 + +:fmax Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b001101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_fmax(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.101 FMAX (vector) page C7-2248 line 131451 MATCH x0e403400/mask=xbfe0fc00 +# CONSTRUCT x4e403400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2@2 +# AUNIT --inst x4e403400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 8H when Q = 1 + +:fmax Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b001101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_fmax(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.102 FMAX (scalar) page C7-2250 line 131581 MATCH x1e204800/mask=xff20fc00 +# CONSTRUCT x1e604800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 = ext ARG2 ARG3 f>:1 inst_next goto ARG1 ARG3 = +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2 +# AUNIT --inst x1e604800/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround" + +:fmax Rd_FPR64, Rn_FPR64, Rm_FPR64 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x4 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = Rn_FPR64; + zext_zd(Zd); # zero upper 24 bytes of Zd + local tmp1:1 = Rn_FPR64 f> Rm_FPR64; + if (tmp1) goto inst_next; + Rd_FPR64 = Rm_FPR64; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.102 FMAX (scalar) page C7-2250 line 131581 MATCH x1e204800/mask=xff20fc00 +# CONSTRUCT x1e204800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 = ext ARG2 ARG3 f>:1 inst_next goto ARG1 ARG3 = +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2 +# AUNIT --inst x1e204800/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fmax Rd_FPR32, Rn_FPR32, Rm_FPR32 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x4 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = Rn_FPR32; + zext_zs(Zd); # zero upper 28 bytes of Zd + local tmp1:1 = Rn_FPR32 f> Rm_FPR32; + if (tmp1) goto inst_next; + Rd_FPR32 = Rm_FPR32; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.102 FMAX (scalar) page C7-2250 line 131581 MATCH x1e204800/mask=xff20fc00 +# CONSTRUCT x1ee04800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2 +# AUNIT --inst x1ee04800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" + +:fmax Rd_FPR16, Rn_FPR16, Rm_FPR16 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x4 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_fmax(Rn_FPR16, Rm_FPR16); +} + +# C7.2.103 FMAXNM (vector) page C7-2252 line 131688 MATCH x0e20c400/mask=xbfa0fc00 +# CONSTRUCT x4e60c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2@8 +# AUNIT --inst x4e60c400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround" + +:fmaxnm Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x18 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_fmaxnm(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.103 FMAXNM (vector) page C7-2252 line 131688 MATCH x0e20c400/mask=xbfa0fc00 +# CONSTRUCT x0e20c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2@4 +# AUNIT --inst x0e20c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fmaxnm Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x18 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_fmaxnm(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.103 FMAXNM (vector) page C7-2252 line 131688 MATCH x0e20c400/mask=xbfa0fc00 +# CONSTRUCT x4e20c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2@4 +# AUNIT --inst x4e20c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fmaxnm Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x18 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_fmaxnm(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.103 FMAXNM (vector) page C7-2252 line 131688 MATCH x0e400400/mask=xbfe0fc00 +# CONSTRUCT x0e400400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2@2 +# AUNIT --inst x0e400400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision SIMD 4H when Q = 0 + +:fmaxnm Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b000001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_fmaxnm(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.103 FMAXNM (vector) page C7-2252 line 131688 MATCH x0e400400/mask=xbfe0fc00 +# CONSTRUCT x4e400400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2@2 +# AUNIT --inst x4e400400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision SIMD 8H when Q = 1 + +:fmaxnm Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b000001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_fmaxnm(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.104 FMAXNM (scalar) page C7-2254 line 131821 MATCH x1e206800/mask=xff20fc00 +# CONSTRUCT x1e606800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 = ext ARG2 ARG3 f>:1 inst_next goto ARG1 ARG3 = +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2 +# AUNIT --inst x1e606800/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround" + +:fmaxnm Rd_FPR64, Rn_FPR64, Rm_FPR64 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x6 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = Rn_FPR64; + zext_zd(Zd); # zero upper 24 bytes of Zd + local tmp1:1 = Rn_FPR64 f> Rm_FPR64; + if (tmp1) goto inst_next; + Rd_FPR64 = Rm_FPR64; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.104 FMAXNM (scalar) page C7-2254 line 131821 MATCH x1e206800/mask=xff20fc00 +# CONSTRUCT x1e206800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 = ext ARG2 ARG3 f>:1 inst_next goto ARG1 ARG3 = +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2 +# AUNIT --inst x1e206800/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fmaxnm Rd_FPR32, Rn_FPR32, Rm_FPR32 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x6 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = Rn_FPR32; + zext_zs(Zd); # zero upper 28 bytes of Zd + local tmp1:1 = Rn_FPR32 f> Rm_FPR32; + if (tmp1) goto inst_next; + Rd_FPR32 = Rm_FPR32; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.104 FMAXNM (scalar) page C7-2254 line 131821 MATCH x1e206800/mask=xff20fc00 +# CONSTRUCT x1ee06800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 = ext ARG2 ARG3 f>:1 inst_next goto ARG1 ARG3 = +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2 +# AUNIT --inst x1ee06800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" + +:fmaxnm Rd_FPR16, Rn_FPR16, Rm_FPR16 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x6 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = Rn_FPR16; + zext_zh(Zd); # zero upper 30 bytes of Zd + local tmp1:1 = Rn_FPR16 f> Rm_FPR16; + if (tmp1) goto inst_next; + Rd_FPR16 = Rm_FPR16; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.105 FMAXNMP (scalar) page C7-2256 line 131930 MATCH x7e30c800/mask=xffbffc00 +# CONSTRUCT x7e70c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxnmp/1@8 +# AUNIT --inst x7e70c800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround" + +:fmaxnmp Rd_FPR64, Rn_VPR128.2D +is b_3031=1 & u=1 & b_2428=0x1e & b_23=0 & b_1722=0x38 & b_1216=0xc & b_1011=2 & Rn_VPR128.2D & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_fmaxnmp(Rn_VPR128.2D, 8:1); +} + +# C7.2.105 FMAXNMP (scalar) page C7-2256 line 131930 MATCH x7e30c800/mask=xffbffc00 +# CONSTRUCT x7e30c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxnmp/1@4 +# AUNIT --inst x7e30c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fmaxnmp Rd_FPR32, Rn_VPR64.2S +is b_3031=1 & u=1 & b_2428=0x1e & b_23=0 & b_1722=0x18 & b_1216=0xc & b_1011=2 & Rn_VPR64.2S & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_fmaxnmp(Rn_VPR64.2S, 4:1); +} + +# C7.2.105 FMAXNMP (scalar) page C7-2256 line 131930 MATCH x5e30c800/mask=xffbffc00 +# CONSTRUCT x5e30c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 Rn_FPR32 =NEON_fmaxnmp/1@2 +# AUNIT --inst x5e30c800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant + +:fmaxnmp Rd_FPR16, vRn_VPR128^".2H" +is b_1031=0b0101111000110000110010 & Rd_FPR16 & vRn_VPR128 & Rn_FPR32 & Zd +{ + Rd_FPR16 = NEON_fmaxnmp(Rn_FPR32, 2:1); +} + +# C7.2.106 FMAXNMP (vector) page C7-2258 line 132036 MATCH x2e20c400/mask=xbfa0fc00 +# CONSTRUCT x6e60c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnmp/2@8 +# AUNIT --inst x6e60c400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround" + +:fmaxnmp Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x18 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_fmaxnmp(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.106 FMAXNMP (vector) page C7-2258 line 132036 MATCH x2e20c400/mask=xbfa0fc00 +# CONSTRUCT x2e20c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnmp/2@4 +# AUNIT --inst x2e20c400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround" + +:fmaxnmp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x18 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_fmaxnmp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.106 FMAXNMP (vector) page C7-2258 line 132036 MATCH x2e20c400/mask=xbfa0fc00 +# CONSTRUCT x6e20c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnmp/2@4 +# AUNIT --inst x6e20c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fmaxnmp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x18 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_fmaxnmp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.106 FMAXNMP (vector) page C7-2258 line 132036 MATCH x2e400400/mask=xbfe0fc00 +# CONSTRUCT x2e400400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnmp/2@2 +# AUNIT --inst x2e400400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 4H when Q = 0 + +:fmaxnmp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b000001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_fmaxnmp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.106 FMAXNMP (vector) page C7-2258 line 132036 MATCH x2e400400/mask=xbfe0fc00 +# CONSTRUCT x6e400400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnmp/2@2 +# AUNIT --inst x6e400400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 8H when Q = 1 + +:fmaxnmp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b000001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_fmaxnmp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.107 FMAXNMV page C7-2260 line 132171 MATCH x2e30c800/mask=xbfbffc00 +# CONSTRUCT x6e30c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxnmv/1@4 +# AUNIT --inst x6e30c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fmaxnmv Rd_FPR32, Rn_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xc & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_fmaxnmv(Rn_VPR128.4S, 4:1); +} + +# C7.2.107 FMAXNMV page C7-2260 line 132171 MATCH x0e30c800/mask=xbffffc00 +# CONSTRUCT x0e30c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxnmv/1@2 +# AUNIT --inst x0e30c800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 4H when Q = 0 + +:fmaxnmv Rd_FPR16, Rn_VPR64.4H +is b_31=0 & b_30=0 & b_1029=0b00111000110000110010 & Rd_FPR16 & Rn_VPR64.4H & Zd +{ + Rd_FPR16 = NEON_fmaxnmv(Rn_VPR64.4H, 2:1); +} + +# C7.2.107 FMAXNMV page C7-2260 line 132171 MATCH x0e30c800/mask=xbffffc00 +# CONSTRUCT x4e30c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxnmv/1@2 +# AUNIT --inst x4e30c800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 8H when Q = 1 + +:fmaxnmv Rd_FPR16, Rn_VPR128.8H +is b_31=0 & b_30=1 & b_1029=0b00111000110000110010 & Rd_FPR16 & Rn_VPR128.8H & Zd +{ + Rd_FPR16 = NEON_fmaxnmv(Rn_VPR128.8H, 2:1); +} + +# C7.2.108 FMAXP (scalar) page C7-2262 line 132280 MATCH x7e30f800/mask=xffbffc00 +# CONSTRUCT x7e70f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxnmv/1@8 +# AUNIT --inst x7e70f800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround" + +:fmaxp Rd_FPR64, Rn_VPR128.2D +is b_3031=1 & u=1 & b_2428=0x1e & b_23=0 & b_1722=0x38 & b_1216=0xf & b_1011=2 & Rn_VPR128.2D & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_fmaxnmv(Rn_VPR128.2D, 8:1); +} + +# C7.2.108 FMAXP (scalar) page C7-2262 line 132280 MATCH x7e30f800/mask=xffbffc00 +# CONSTRUCT x7e30f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxp/1@4 +# AUNIT --inst x7e30f800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fmaxp Rd_FPR32, Rn_VPR64.2S +is b_3031=1 & u=1 & b_2428=0x1e & b_23=0 & b_1722=0x18 & b_1216=0xf & b_1011=2 & Rn_VPR64.2S & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_fmaxp(Rn_VPR64.2S, 4:1); +} + +# C7.2.108 FMAXP (scalar) page C7-2262 line 132280 MATCH x5e30f800/mask=xffbffc00 +# CONSTRUCT x5e30f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 Rn_FPR32 =NEON_fmaxp/1@2 +# AUNIT --inst x5e30f800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant + +:fmaxp Rd_FPR16, vRn_VPR128^".2H" +is b_1031=0b0101111000110000111110 & Rd_FPR16 & vRn_VPR128 & Rn_FPR32 & Zd +{ + Rd_FPR16 = NEON_fmaxp(Rn_FPR32, 2:1); +} + +# C7.2.109 FMAXP (vector) page C7-2264 line 132387 MATCH x2e20f400/mask=xbfa0fc00 +# CONSTRUCT x6e60f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxp/2@8 +# AUNIT --inst x6e60f400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround" + +:fmaxp Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1e & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_fmaxp(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.109 FMAXP (vector) page C7-2264 line 132387 MATCH x2e20f400/mask=xbfa0fc00 +# CONSTRUCT x2e20f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxp/2@4 +# AUNIT --inst x2e20f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fmaxp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1e & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_fmaxp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.109 FMAXP (vector) page C7-2264 line 132387 MATCH x2e20f400/mask=xbfa0fc00 +# CONSTRUCT x6e20f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxp/2@4 +# AUNIT --inst x6e20f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fmaxp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1e & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_fmaxp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.109 FMAXP (vector) page C7-2264 line 132387 MATCH x2e403400/mask=xbfe0fc00 +# CONSTRUCT x2e403400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxp/2@2 +# AUNIT --inst x2e403400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 4H when Q = 0 + +:fmaxp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b001101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_fmaxp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.109 FMAXP (vector) page C7-2264 line 132387 MATCH x2e403400/mask=xbfe0fc00 +# CONSTRUCT x6e403400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxp/2@2 +# AUNIT --inst x6e403400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 8H when Q = 1 + +:fmaxp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b001101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_fmaxp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.110 FMAXV page C7-2266 line 132519 MATCH x2e30f800/mask=xbfbffc00 +# CONSTRUCT x6e30f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxv/1@4 +# AUNIT --inst x6e30f800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fmaxv Rd_FPR32, Rn_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xf & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_fmaxv(Rn_VPR128.4S, 4:1); +} + +# C7.2.110 FMAXV page C7-2266 line 132519 MATCH x0e30f800/mask=xbffffc00 +# CONSTRUCT x0e30f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxv/1@2 +# AUNIT --inst x0e30f800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 4H when Q = 0 + +:fmaxv Rd_FPR16, Rn_VPR64.4H +is b_31=0 & b_30=0 & b_1029=0b00111000110000111110 & Rd_FPR16 & Rn_VPR64.4H & Zd +{ + Rd_FPR16 = NEON_fmaxv(Rn_VPR64.4H, 2:1); +} + +# C7.2.110 FMAXV page C7-2266 line 132519 MATCH x0e30f800/mask=xbffffc00 +# CONSTRUCT x4e30f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxv/1@2 +# AUNIT --inst x4e30f800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 8H when Q = 1 + +:fmaxv Rd_FPR16, Rn_VPR128.8H +is b_31=0 & b_30=1 & b_1029=0b00111000110000111110 & Rd_FPR16 & Rn_VPR128.8H & Zd +{ + Rd_FPR16 = NEON_fmaxv(Rn_VPR128.8H, 2:1); +} + +# C7.2.111 FMIN (vector) page C7-2268 line 132628 MATCH x0ea0f400/mask=xbfa0fc00 +# CONSTRUCT x4ee0f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2@8 +# AUNIT --inst x4ee0f400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround" + +:fmin Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x1e & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_fmin(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.111 FMIN (vector) page C7-2268 line 132628 MATCH x0ea0f400/mask=xbfa0fc00 +# CONSTRUCT x0ea0f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2@4 +# AUNIT --inst x0ea0f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fmin Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x1e & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_fmin(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.111 FMIN (vector) page C7-2268 line 132628 MATCH x0ea0f400/mask=xbfa0fc00 +# CONSTRUCT x4ea0f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2@4 +# AUNIT --inst x4ea0f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fmin Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x1e & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_fmin(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.111 FMIN (vector) page C7-2268 line 132628 MATCH x0ec03400/mask=xbfe0fc00 +# CONSTRUCT x0ec03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2@2 +# AUNIT --inst x0ec03400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 4H when Q = 0 + +:fmin Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2129=0b001110110 & b_1015=0b001101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_fmin(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.111 FMIN (vector) page C7-2268 line 132628 MATCH x0ec03400/mask=xbfe0fc00 +# CONSTRUCT x4ec03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2@2 +# AUNIT --inst x4ec03400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 8H when Q = 1 + +:fmin Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2129=0b001110110 & b_1015=0b001101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_fmin(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.112 FMIN (scalar) page C7-2270 line 132758 MATCH x1e205800/mask=xff20fc00 +# CONSTRUCT x1e605800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2 +# AUNIT --inst x1e605800/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround" + +:fmin Rd_FPR64, Rn_FPR64, Rm_FPR64 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x5 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_fmin(Rn_FPR64, Rm_FPR64); +} + +# C7.2.112 FMIN (scalar) page C7-2270 line 132758 MATCH x1e205800/mask=xff20fc00 +# CONSTRUCT x1e205800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2 +# AUNIT --inst x1e205800/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fmin Rd_FPR32, Rn_FPR32, Rm_FPR32 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x5 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_fmin(Rn_FPR32, Rm_FPR32); +} + +# C7.2.112 FMIN (scalar) page C7-2270 line 132758 MATCH x1e205800/mask=xff20fc00 +# CONSTRUCT x1ee05800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2 +# AUNIT --inst x1ee05800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" + +:fmin Rd_FPR16, Rn_FPR16, Rm_FPR16 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x5 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_fmin(Rn_FPR16, Rm_FPR16); +} + +# C7.2.113 FMINNM (vector) page C7-2272 line 132865 MATCH x0ea0c400/mask=xbfa0fc00 +# CONSTRUCT x4ee0c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2@8 +# AUNIT --inst x4ee0c400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround" + +:fminnm Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x18 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_fminnm(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.113 FMINNM (vector) page C7-2272 line 132865 MATCH x0ea0c400/mask=xbfa0fc00 +# CONSTRUCT x0ea0c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2@4 +# AUNIT --inst x0ea0c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fminnm Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x18 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_fminnm(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.113 FMINNM (vector) page C7-2272 line 132865 MATCH x0ea0c400/mask=xbfa0fc00 +# CONSTRUCT x4ea0c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2@4 +# AUNIT --inst x4ea0c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fminnm Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x18 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_fminnm(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.113 FMINNM (vector) page C7-2272 line 132865 MATCH x0ec00400/mask=xbfe0fc00 +# CONSTRUCT x0ec00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2@2 +# AUNIT --inst x0ec00400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 4H when Q = 0 + +:fminnm Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2129=0b001110110 & b_1015=0b000001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_fminnm(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.113 FMINNM (vector) page C7-2272 line 132865 MATCH x0ec00400/mask=xbfe0fc00 +# CONSTRUCT x4ec00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2@2 +# AUNIT --inst x4ec00400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 8H when Q = 1 + +:fminnm Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2129=0b001110110 & b_1015=0b000001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_fminnm(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.114 FMINNM (scalar) page C7-2274 line 132998 MATCH x1e207800/mask=xff20fc00 +# CONSTRUCT x1e607800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2 +# AUNIT --inst x1e607800/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround" + +:fminnm Rd_FPR64, Rn_FPR64, Rm_FPR64 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x7 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_fminnm(Rn_FPR64, Rm_FPR64); +} + +# C7.2.114 FMINNM (scalar) page C7-2274 line 132998 MATCH x1e207800/mask=xff20fc00 +# CONSTRUCT x1e207800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2 +# AUNIT --inst x1e207800/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fminnm Rd_FPR32, Rn_FPR32, Rm_FPR32 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x7 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_fminnm(Rn_FPR32, Rm_FPR32); +} + +# C7.2.114 FMINNM (scalar) page C7-2274 line 132998 MATCH x1e207800/mask=xff20fc00 +# CONSTRUCT x1ee07800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2 +# AUNIT --inst x1ee07800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" + +:fminnm Rd_FPR16, Rn_FPR16, Rm_FPR16 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x7 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_fminnm(Rn_FPR16, Rm_FPR16); +} + +# C7.2.115 FMINNMP (scalar) page C7-2276 line 133108 MATCH x7eb0c800/mask=xffbffc00 +# CONSTRUCT x7ef0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fminnmp/1@8 +# AUNIT --inst x7ef0c800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround" + +:fminnmp Rd_FPR64, Rn_VPR128.2D +is b_3031=1 & u=1 & b_2428=0x1e & b_23=1 & b_1722=0x38 & b_1216=0xc & b_1011=2 & Rn_VPR128.2D & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_fminnmp(Rn_VPR128.2D, 8:1); +} + +# C7.2.115 FMINNMP (scalar) page C7-2276 line 133108 MATCH x7eb0c800/mask=xffbffc00 +# CONSTRUCT x7eb0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fminnmp/1@4 +# AUNIT --inst x7eb0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fminnmp Rd_FPR32, Rn_VPR64.2S +is b_3031=1 & u=1 & b_2428=0x1e & b_23=1 & b_1722=0x18 & b_1216=0xc & b_1011=2 & Rn_VPR64.2S & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_fminnmp(Rn_VPR64.2S, 4:1); +} + +# C7.2.115 FMINNMP (scalar) page C7-2276 line 133108 MATCH x5eb0c800/mask=xffbffc00 +# CONSTRUCT x5eb0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 Rn_FPR32 =NEON_fminnmp/1@2 +# AUNIT --inst x5eb0c800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant + +:fminnmp Rd_FPR16, vRn_VPR128^".2H" +is b_1031=0b0101111010110000110010 & Rd_FPR16 & vRn_VPR128 & Rn_FPR32 & Zd +{ + Rd_FPR16 = NEON_fminnmp(Rn_FPR32, 2:1); +} + +# C7.2.116 FMINNMP (vector) page C7-2278 line 133214 MATCH x2ea0c400/mask=xbfa0fc00 +# CONSTRUCT x6ee0c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnmp/2@8 +# AUNIT --inst x6ee0c400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround" + +:fminnmp Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x18 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_fminnmp(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.116 FMINNMP (vector) page C7-2278 line 133214 MATCH x2ea0c400/mask=xbfa0fc00 +# CONSTRUCT x2ea0c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnmp/2@4 +# AUNIT --inst x2ea0c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fminnmp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x18 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_fminnmp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.116 FMINNMP (vector) page C7-2278 line 133214 MATCH x2ea0c400/mask=xbfa0fc00 +# CONSTRUCT x6ea0c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnmp/2@4 +# AUNIT --inst x6ea0c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fminnmp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x18 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_fminnmp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.116 FMINNMP (vector) page C7-2278 line 133214 MATCH x2ec00400/mask=xbfe0fc00 +# CONSTRUCT x2ec00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnmp/2@2 +# AUNIT --inst x2ec00400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 4H when Q = 0 + +:fminnmp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2129=0b101110110 & b_1015=0b000001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_fminnmp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.116 FMINNMP (vector) page C7-2278 line 133214 MATCH x2ec00400/mask=xbfe0fc00 +# CONSTRUCT x6ec00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnmp/2@2 +# AUNIT --inst x6ec00400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 8H when Q = 1 + +:fminnmp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2129=0b101110110 & b_1015=0b000001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_fminnmp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.117 FMINNMV page C7-2280 line 133349 MATCH x2eb0c800/mask=xbfbffc00 +# CONSTRUCT x6eb0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fminnmv/1@4 +# AUNIT --inst x6eb0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fminnmv Rd_FPR32, Rn_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0xc & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_fminnmv(Rn_VPR128.4S, 4:1); +} + +# C7.2.117 FMINNMV page C7-2280 line 133349 MATCH x0eb0c800/mask=xbffffc00 +# CONSTRUCT x0eb0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fminnmv/1@2 +# AUNIT --inst x0eb0c800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 4H when Q = 0 + +:fminnmv Rd_FPR16, Rn_VPR64.4H +is b_31=0 & b_30=0 & b_1029=0b00111010110000110010 & Rd_FPR16 & Rn_VPR64.4H & Zd +{ + Rd_FPR16 = NEON_fminnmv(Rn_VPR64.4H, 2:1); +} + +# C7.2.117 FMINNMV page C7-2280 line 133349 MATCH x0eb0c800/mask=xbffffc00 +# CONSTRUCT x4eb0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fminnmv/1@2 +# AUNIT --inst x4eb0c800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 8H when Q = 1 + +:fminnmv Rd_FPR16, Rn_VPR128.8H +is b_31=0 & b_30=1 & b_1029=0b00111010110000110010 & Rd_FPR16 & Rn_VPR128.8H & Zd +{ + Rd_FPR16 = NEON_fminnmv(Rn_VPR128.8H, 2:1); +} + +# C7.2.118 FMINP (scalar) page C7-2282 line 133458 MATCH x7eb0f800/mask=xffbffc00 +# CONSTRUCT x7ef0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fminp/1@8 +# AUNIT --inst x7ef0f800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround" + +:fminp Rd_FPR64, Rn_VPR128.2D +is b_3031=1 & u=1 & b_2428=0x1e & b_23=1 & b_1722=0x38 & b_1216=0xf & b_1011=2 & Rn_VPR128.2D & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_fminp(Rn_VPR128.2D, 8:1); +} + +# C7.2.118 FMINP (scalar) page C7-2282 line 133458 MATCH x7eb0f800/mask=xffbffc00 +# CONSTRUCT x7eb0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fminp/1@4 +# AUNIT --inst x7eb0f800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fminp Rd_FPR32, Rn_VPR64.2S +is b_3031=1 & u=1 & b_2428=0x1e & b_23=1 & b_1722=0x18 & b_1216=0xf & b_1011=2 & Rn_VPR64.2S & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_fminp(Rn_VPR64.2S, 4:1); +} + +# C7.2.118 FMINP (scalar) page C7-2282 line 133458 MATCH x5eb0f800/mask=xffbffc00 +# CONSTRUCT x5eb0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 Rn_FPR32 =NEON_fminp/1@2 +# AUNIT --inst x5eb0f800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant + +:fminp Rd_FPR16, vRn_VPR128^".2H" +is b_1031=0b0101111010110000111110 & Rd_FPR16 & vRn_VPR128 & Rn_FPR32 & Zd +{ + Rd_FPR16 = NEON_fminp(Rn_FPR32, 2:1); +} + +# C7.2.119 FMINP (vector) page C7-2284 line 133565 MATCH x2ea0f400/mask=xbfa0fc00 +# CONSTRUCT x6ee0f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminp/2@8 +# AUNIT --inst x6ee0f400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround" + +:fminp Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x1e & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_fminp(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.119 FMINP (vector) page C7-2284 line 133565 MATCH x2ea0f400/mask=xbfa0fc00 +# CONSTRUCT x2ea0f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminp/2@4 +# AUNIT --inst x2ea0f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fminp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x1e & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_fminp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.119 FMINP (vector) page C7-2284 line 133565 MATCH x2ea0f400/mask=xbfa0fc00 +# CONSTRUCT x6ea0f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminp/2@4 +# AUNIT --inst x6ea0f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fminp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x1e & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_fminp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.119 FMINP (vector) page C7-2284 line 133565 MATCH x2ec03400/mask=xbfe0fc00 +# CONSTRUCT x2ec03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminp/2@2 +# AUNIT --inst x2ec03400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 4H when Q = 0 + +:fminp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2129=0b101110110 & b_1015=0b001101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_fminp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.119 FMINP (vector) page C7-2284 line 133565 MATCH x2ec03400/mask=xbfe0fc00 +# CONSTRUCT x6ec03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminp/2@2 +# AUNIT --inst x6ec03400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 8H when Q = 1 + +:fminp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2129=0b101110110 & b_1015=0b001101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_fminp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.120 FMINV page C7-2286 line 133697 MATCH x2eb0f800/mask=xbfbffc00 +# CONSTRUCT x6eb0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fminv/1@4 +# AUNIT --inst x6eb0f800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fminv Rd_FPR32, Rn_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0xf & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_fminv(Rn_VPR128.4S, 4:1); +} + +# C7.2.120 FMINV page C7-2286 line 133697 MATCH x0eb0f800/mask=xbffffc00 +# CONSTRUCT x0eb0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fminv/1@2 +# AUNIT --inst x0eb0f800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 4H when Q = 0 + +:fminv Rd_FPR16, Rn_VPR64.4H +is b_31=0 & b_30=0 & b_1029=0b00111010110000111110 & Rd_FPR16 & Rn_VPR64.4H & Zd +{ + Rd_FPR16 = NEON_fminv(Rn_VPR64.4H, 2:1); +} + +# C7.2.120 FMINV page C7-2286 line 133697 MATCH x0eb0f800/mask=xbffffc00 +# CONSTRUCT x4eb0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fminv/1@2 +# AUNIT --inst x4eb0f800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 8H when Q = 1 + +:fminv Rd_FPR16, Rn_VPR128.8H +is b_31=0 & b_30=1 & b_1029=0b00111010110000111110 & Rd_FPR16 & Rn_VPR128.8H & Zd +{ + Rd_FPR16 = NEON_fminv(Rn_VPR128.8H, 2:1); +} + +# C7.2.121 FMLA (by element) page C7-2288 line 133806 MATCH x0f801000/mask=xbf80f400 +# CONSTRUCT x4fc01000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $f* &=$f+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@8 +# AUNIT --inst x4fc01000/mask=xffe0f400 --rand dfp --status pass --comment "nofpround" + +:fmla Rd_VPR128.2D, Rn_VPR128.2D, Re_VPR128.D.vIndex +is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=3 & b_2121=0 & Re_VPR128.D.vIndex & vIndex & Re_VPR128.D & b_1215=0x1 & b_1010=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + # simd element Re_VPR128.D[vIndex] lane size 8 + local tmp1:8 = Re_VPR128.D.vIndex; + # simd infix TMPQ1 = Rn_VPR128.2D f* tmp1 on lane size 8 + TMPQ1[0,64] = Rn_VPR128.2D[0,64] f* tmp1; + TMPQ1[64,64] = Rn_VPR128.2D[64,64] f* tmp1; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D f+ TMPQ1 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] f+ TMPQ1[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] f+ TMPQ1[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.121 FMLA (by element) page C7-2288 line 133806 MATCH x0f801000/mask=xbf80f400 +# CONSTRUCT x0f801000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $f* &=$f+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@4 +# AUNIT --inst x0f801000/mask=xffc0f400 --rand sfp --status pass --comment "nofpround" + +:fmla Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex +is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x1 & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp1:4 = Re_VPR128.S.vIndex; + # simd infix TMPD1 = Rn_VPR64.2S f* tmp1 on lane size 4 + TMPD1[0,32] = Rn_VPR64.2S[0,32] f* tmp1; + TMPD1[32,32] = Rn_VPR64.2S[32,32] f* tmp1; + # simd infix Rd_VPR64.2S = Rd_VPR64.2S f+ TMPD1 on lane size 4 + Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] f+ TMPD1[0,32]; + Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] f+ TMPD1[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.121 FMLA (by element) page C7-2288 line 133806 MATCH x0f801000/mask=xbf80f400 +# CONSTRUCT x4f801000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $f* &=$f+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@4 +# AUNIT --inst x4f801000/mask=xffc0f400 --rand sfp --status fail --comment "nofpround" + +:fmla Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex +is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x1 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp1:4 = Re_VPR128.S.vIndex; + # simd infix TMPQ1 = Rn_VPR128.4S f* tmp1 on lane size 4 + TMPQ1[0,32] = Rn_VPR128.4S[0,32] f* tmp1; + TMPQ1[32,32] = Rn_VPR128.4S[32,32] f* tmp1; + TMPQ1[64,32] = Rn_VPR128.4S[64,32] f* tmp1; + TMPQ1[96,32] = Rn_VPR128.4S[96,32] f* tmp1; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S f+ TMPQ1 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] f+ TMPQ1[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] f+ TMPQ1[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] f+ TMPQ1[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] f+ TMPQ1[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.121 FMLA (by element) page C7-2288 line 133806 MATCH x5f001000/mask=xffc0f400 +# CONSTRUCT x5f001000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 f* &=f+ +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@2 +# AUNIT --inst x5f001000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround" +# Scalar half-precision variant + +:fmla Rd_FPR16, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM +is b_2231=0b0101111100 & b_1215=0b0001 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_FPR16 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Zd +{ + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp1:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp2:2 = Rn_FPR16 f* tmp1; + Rd_FPR16 = Rd_FPR16 f+ tmp2; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.121 FMLA (by element) page C7-2288 line 133806 MATCH x5f801000/mask=xff80f400 +# CONSTRUCT x5f801000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 f* &=f+ +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@4 +# AUNIT --inst x5f801000/mask=xffc0f400 --rand sfp --status pass --comment "nofpround" +# Scalar, single-precision and double-precision variant, sz=0 + +:fmla Rd_FPR32, Rn_FPR32, Re_VPR128.S.vIndex +is b_2331=0b010111111 & b_22=0 & b_1215=0b0001 & b_10=0 & Re_VPR128.S & vIndex & Rd_FPR32 & Rn_FPR32 & Re_VPR128.S.vIndex & Zd +{ + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp1:4 = Re_VPR128.S.vIndex; + local tmp2:4 = Rn_FPR32 f* tmp1; + Rd_FPR32 = Rd_FPR32 f+ tmp2; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.121 FMLA (by element) page C7-2288 line 133806 MATCH x5f801000/mask=xff80f400 +# CONSTRUCT x5fc01000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 f* &=f+ +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@8 +# AUNIT --inst x5fc01000/mask=xffe0f400 --rand dfp --status pass --comment "nofpround" +# Scalar, single-precision and double-precision variant, sz=1 + +:fmla Rd_FPR64, Rn_FPR64, Re_VPR128.D.vIndex +is b_2331=0b010111111 & b_22=1 & b_21=0 & b_1215=0b0001 & b_10=0 & Re_VPR128.D & vIndex & Rd_FPR64 & Rn_FPR64 & Re_VPR128.D.vIndex & Zd +{ + # simd element Re_VPR128.D[vIndex] lane size 8 + local tmp1:8 = Re_VPR128.D.vIndex; + local tmp2:8 = Rn_FPR64 f* tmp1; + Rd_FPR64 = Rd_FPR64 f+ tmp2; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.121 FMLA (by element) page C7-2288 line 133806 MATCH x0f001000/mask=xbfc0f400 +# CONSTRUCT x0f001000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $f* &=$f+$@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@2 +# AUNIT --inst x0f001000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround" +# Vector, half-precision variant SIMD 4H when Q = 0 + +:fmla Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM +is b_31=0 & b_30=0 & b_2229=0b00111100 & b_1215=0b0001 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.4H & Rn_VPR64.4H & Re_VPR128Lo.H.vIndexHLM & Zd +{ + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp1:2 = Re_VPR128Lo.H.vIndexHLM; + # simd infix TMPD1 = Rn_VPR64.4H f* tmp1 on lane size 2 + TMPD1[0,16] = Rn_VPR64.4H[0,16] f* tmp1; + TMPD1[16,16] = Rn_VPR64.4H[16,16] f* tmp1; + TMPD1[32,16] = Rn_VPR64.4H[32,16] f* tmp1; + TMPD1[48,16] = Rn_VPR64.4H[48,16] f* tmp1; + # simd infix Rd_VPR64.4H = Rd_VPR64.4H f+ TMPD1 on lane size 2 + Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] f+ TMPD1[0,16]; + Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] f+ TMPD1[16,16]; + Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] f+ TMPD1[32,16]; + Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] f+ TMPD1[48,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.121 FMLA (by element) page C7-2288 line 133806 MATCH x0f001000/mask=xbfc0f400 +# CONSTRUCT x4f001000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $f* &=$f+$@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@2 +# AUNIT --inst x4f001000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround" +# Vector, half-precision variant SIMD 8H when Q = 1 + +:fmla Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM +is b_31=0 & b_30=1 & b_2229=0b00111100 & b_1215=0b0001 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.8H & Rn_VPR128.8H & Re_VPR128Lo.H.vIndexHLM & Zd +{ + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp1:2 = Re_VPR128Lo.H.vIndexHLM; + # simd infix TMPQ1 = Rn_VPR128.8H f* tmp1 on lane size 2 + TMPQ1[0,16] = Rn_VPR128.8H[0,16] f* tmp1; + TMPQ1[16,16] = Rn_VPR128.8H[16,16] f* tmp1; + TMPQ1[32,16] = Rn_VPR128.8H[32,16] f* tmp1; + TMPQ1[48,16] = Rn_VPR128.8H[48,16] f* tmp1; + TMPQ1[64,16] = Rn_VPR128.8H[64,16] f* tmp1; + TMPQ1[80,16] = Rn_VPR128.8H[80,16] f* tmp1; + TMPQ1[96,16] = Rn_VPR128.8H[96,16] f* tmp1; + TMPQ1[112,16] = Rn_VPR128.8H[112,16] f* tmp1; + # simd infix Rd_VPR128.8H = Rd_VPR128.8H f+ TMPQ1 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] f+ TMPQ1[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] f+ TMPQ1[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] f+ TMPQ1[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] f+ TMPQ1[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] f+ TMPQ1[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] f+ TMPQ1[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] f+ TMPQ1[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] f+ TMPQ1[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.122 FMLA (vector) page C7-2292 line 134046 MATCH x0e20cc00/mask=xbfa0fc00 +# CONSTRUCT x4e60cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $f*@8 &=$f+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@8 +# AUNIT --inst x4e60cc00/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround" + +:fmla Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.2D & b_1115=0x19 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.2D f* Rm_VPR128.2D on lane size 8 + TMPQ1[0,64] = Rn_VPR128.2D[0,64] f* Rm_VPR128.2D[0,64]; + TMPQ1[64,64] = Rn_VPR128.2D[64,64] f* Rm_VPR128.2D[64,64]; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D f+ TMPQ1 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] f+ TMPQ1[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] f+ TMPQ1[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.122 FMLA (vector) page C7-2292 line 134046 MATCH x0e20cc00/mask=xbfa0fc00 +# CONSTRUCT x0e20cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@4 +# AUNIT --inst x0e20cc00/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround" + +:fmla Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.2S & b_1115=0x19 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Re_VPR128 & Zd +{ + # simd infix TMPD1 = Rn_VPR64.2S f* Rm_VPR64.2S on lane size 4 + TMPD1[0,32] = Rn_VPR64.2S[0,32] f* Rm_VPR64.2S[0,32]; + TMPD1[32,32] = Rn_VPR64.2S[32,32] f* Rm_VPR64.2S[32,32]; + # simd infix Rd_VPR64.2S = Rd_VPR64.2S f+ TMPD1 on lane size 4 + Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] f+ TMPD1[0,32]; + Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] f+ TMPD1[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.122 FMLA (vector) page C7-2292 line 134046 MATCH x0e20cc00/mask=xbfa0fc00 +# CONSTRUCT x4e20cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@4 +# AUNIT --inst x4e20cc00/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround" + +:fmla Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.4S & b_1115=0x19 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.4S f* Rm_VPR128.4S on lane size 4 + TMPQ1[0,32] = Rn_VPR128.4S[0,32] f* Rm_VPR128.4S[0,32]; + TMPQ1[32,32] = Rn_VPR128.4S[32,32] f* Rm_VPR128.4S[32,32]; + TMPQ1[64,32] = Rn_VPR128.4S[64,32] f* Rm_VPR128.4S[64,32]; + TMPQ1[96,32] = Rn_VPR128.4S[96,32] f* Rm_VPR128.4S[96,32]; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S f+ TMPQ1 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] f+ TMPQ1[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] f+ TMPQ1[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] f+ TMPQ1[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] f+ TMPQ1[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.122 FMLA (vector) page C7-2292 line 134046 MATCH x0e400c00/mask=xbfe0fc00 +# CONSTRUCT x0e400c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@2 +# AUNIT --inst x0e400c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 4H when Q = 0 + +:fmla Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b000011 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + # simd infix TMPD1 = Rn_VPR64.4H f* Rm_VPR64.4H on lane size 4 + TMPD1[0,32] = Rn_VPR64.4H[0,32] f* Rm_VPR64.4H[0,32]; + TMPD1[32,32] = Rn_VPR64.4H[32,32] f* Rm_VPR64.4H[32,32]; + # simd infix Rd_VPR64.4H = Rd_VPR64.4H f+ TMPD1 on lane size 4 + Rd_VPR64.4H[0,32] = Rd_VPR64.4H[0,32] f+ TMPD1[0,32]; + Rd_VPR64.4H[32,32] = Rd_VPR64.4H[32,32] f+ TMPD1[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.122 FMLA (vector) page C7-2292 line 134046 MATCH x0e400c00/mask=xbfe0fc00 +# CONSTRUCT x4e400c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@2 +# AUNIT --inst x4e400c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 8H when Q = 1 + +:fmla Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b000011 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.8H f* Rm_VPR128.8H on lane size 4 + TMPQ1[0,32] = Rn_VPR128.8H[0,32] f* Rm_VPR128.8H[0,32]; + TMPQ1[32,32] = Rn_VPR128.8H[32,32] f* Rm_VPR128.8H[32,32]; + TMPQ1[64,32] = Rn_VPR128.8H[64,32] f* Rm_VPR128.8H[64,32]; + TMPQ1[96,32] = Rn_VPR128.8H[96,32] f* Rm_VPR128.8H[96,32]; + # simd infix Rd_VPR128.8H = Rd_VPR128.8H f+ TMPQ1 on lane size 4 + Rd_VPR128.8H[0,32] = Rd_VPR128.8H[0,32] f+ TMPQ1[0,32]; + Rd_VPR128.8H[32,32] = Rd_VPR128.8H[32,32] f+ TMPQ1[32,32]; + Rd_VPR128.8H[64,32] = Rd_VPR128.8H[64,32] f+ TMPQ1[64,32]; + Rd_VPR128.8H[96,32] = Rd_VPR128.8H[96,32] f+ TMPQ1[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.123 FMLAL, FMLAL2 (by element) page C7-2294 line 134165 MATCH x0f800000/mask=xbfc0f400 +# CONSTRUCT x0f800000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[0]:4 ARG3 $f* $float2float@2:8 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal/3@4 +# AUNIT --inst x0f800000/mask=xffc0f400 --rand sfp --status noqemu --comment "ext nofpround" +# SIMD 2S when Q = 0 + +:fmlal Rd_VPR64.2S, vRn_VPR64^".2H", Re_VPR128Lo.H.vIndexHLM +is b_31=0 & b_30=0 & b_2329=0b0011111 & b_22=0 & b_1215=0b0000 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & Re_VPR128Lo.H.vIndexHLM & Zd +{ + TMPS1 = Rn_VPR64[0,32]; + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp2:2 = Re_VPR128Lo.H.vIndexHLM; + # simd infix TMPS2 = TMPS1 f* tmp2 on lane size 2 + TMPS2[0,16] = TMPS1[0,16] f* tmp2; + TMPS2[16,16] = TMPS1[16,16] f* tmp2; + # simd resize TMPD3 = float2float(TMPS2) (lane size 2 to 4) + TMPD3[0,32] = float2float(TMPS2[0,16]); + TMPD3[32,32] = float2float(TMPS2[16,16]); + # simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD3 on lane size 4 + Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD3[0,32]; + Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD3[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.123 FMLAL, FMLAL2 (by element) page C7-2294 line 134165 MATCH x0f800000/mask=xbfc0f400 +# CONSTRUCT x4f800000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[0]:8 ARG3 $f* $float2float@2:16 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal/3@2 +# AUNIT --inst x4f800000/mask=xffc0f400 --rand sfp --status noqemu --comment "ext nofpround" +# SIMD 4S when Q = 1 + +:fmlal Rd_VPR128.4S, vRn_VPR128^".4H", Re_VPR128Lo.H.vIndexHLM +is b_31=0 & b_30=1 & b_2329=0b0011111 & b_22=0 & b_1215=0b0000 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Re_VPR128Lo.H.vIndexHLM & Zd +{ + TMPD1 = Rn_VPR128[0,64]; + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp2:2 = Re_VPR128Lo.H.vIndexHLM; + # simd infix TMPD2 = TMPD1 f* tmp2 on lane size 2 + TMPD2[0,16] = TMPD1[0,16] f* tmp2; + TMPD2[16,16] = TMPD1[16,16] f* tmp2; + TMPD2[32,16] = TMPD1[32,16] f* tmp2; + TMPD2[48,16] = TMPD1[48,16] f* tmp2; + # simd resize TMPQ3 = float2float(TMPD2) (lane size 2 to 4) + TMPQ3[0,32] = float2float(TMPD2[0,16]); + TMPQ3[32,32] = float2float(TMPD2[16,16]); + TMPQ3[64,32] = float2float(TMPD2[32,16]); + TMPQ3[96,32] = float2float(TMPD2[48,16]); + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.123 FMLAL, FMLAL2 (by element) page C7-2294 line 134165 MATCH x2f808000/mask=xbfc0f400 +# CONSTRUCT x2f808000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:4 ARG3 $f* $float2float@2:8 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal2/3@2 +# AUNIT --inst x2f808000/mask=xffc0f400 --rand sfp --status noqemu --comment "ext nofpround" +# SIMD 2S when Q = 0 + +:fmlal2 Rd_VPR64.2S, vRn_VPR64^".2H", Re_VPR128Lo.H.vIndexHLM +is b_31=0 & b_30=0 & b_2329=0b1011111 & b_22=0 & b_1215=0b1000 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & Re_VPR128Lo.H.vIndexHLM & Zd +{ + TMPS1 = Rn_VPR64[32,32]; + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp2:2 = Re_VPR128Lo.H.vIndexHLM; + # simd infix TMPS2 = TMPS1 f* tmp2 on lane size 2 + TMPS2[0,16] = TMPS1[0,16] f* tmp2; + TMPS2[16,16] = TMPS1[16,16] f* tmp2; + # simd resize TMPD3 = float2float(TMPS2) (lane size 2 to 4) + TMPD3[0,32] = float2float(TMPS2[0,16]); + TMPD3[32,32] = float2float(TMPS2[16,16]); + # simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD3 on lane size 4 + Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD3[0,32]; + Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD3[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.123 FMLAL, FMLAL2 (by element) page C7-2294 line 134165 MATCH x2f808000/mask=xbfc0f400 +# CONSTRUCT x6f808000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 ARG3 $f* $float2float@2:16 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal2/3@2 +# AUNIT --inst x6f808000/mask=xffc0f400 --rand sfp --status noqemu --comment "ext nofpround" +# SIMD 4S when Q = 1 + +:fmlal2 Rd_VPR128.4S, vRn_VPR128^".4H", Re_VPR128Lo.H.vIndexHLM +is b_31=0 & b_30=1 & b_2329=0b1011111 & b_22=0 & b_1215=0b1000 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Re_VPR128Lo.H.vIndexHLM & Zd +{ + TMPD1 = Rn_VPR128[64,64]; + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp2:2 = Re_VPR128Lo.H.vIndexHLM; + # simd infix TMPD2 = TMPD1 f* tmp2 on lane size 2 + TMPD2[0,16] = TMPD1[0,16] f* tmp2; + TMPD2[16,16] = TMPD1[16,16] f* tmp2; + TMPD2[32,16] = TMPD1[32,16] f* tmp2; + TMPD2[48,16] = TMPD1[48,16] f* tmp2; + # simd resize TMPQ3 = float2float(TMPD2) (lane size 2 to 4) + TMPQ3[0,32] = float2float(TMPD2[0,16]); + TMPQ3[32,32] = float2float(TMPD2[16,16]); + TMPQ3[64,32] = float2float(TMPD2[32,16]); + TMPQ3[96,32] = float2float(TMPD2[48,16]); + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.124 FMLAL, FMLAL2 (vector) page C7-2296 line 134298 MATCH x0e20ec00/mask=xbfe0fc00 +# CONSTRUCT x0e20ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[0]:4 ARG3[0]:4 $f*@2 $float2float@2:8 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal/3@2 +# AUNIT --inst x0e20ec00/mask=xffe0fc00 --rand sfp --status noqemu --comment "ext nofpround" +# SIMD 2S when Q = 0 + +:fmlal Rd_VPR64.2S, vRn_VPR64^".2H", vRm_VPR64^".2H" +is b_31=0 & b_30=0 & b_2329=0b0011100 & b_22=0 & b_21=1 & b_1015=0b111011 & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & vRm_VPR64 & Rm_VPR64 & Zd +{ + TMPS1 = Rn_VPR64[0,32]; + TMPS2 = Rm_VPR64[0,32]; + # simd infix TMPS3 = TMPS1 f* TMPS2 on lane size 2 + TMPS3[0,16] = TMPS1[0,16] f* TMPS2[0,16]; + TMPS3[16,16] = TMPS1[16,16] f* TMPS2[16,16]; + # simd resize TMPD4 = float2float(TMPS3) (lane size 2 to 4) + TMPD4[0,32] = float2float(TMPS3[0,16]); + TMPD4[32,32] = float2float(TMPS3[16,16]); + # simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD4 on lane size 4 + Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD4[0,32]; + Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD4[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.124 FMLAL, FMLAL2 (vector) page C7-2296 line 134298 MATCH x0e20ec00/mask=xbfe0fc00 +# CONSTRUCT x4e20ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[0]:8 ARG3[0]:8 $f*@2 $float2float@2:16 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal/3@2 +# AUNIT --inst x4e20ec00/mask=xffe0fc00 --rand sfp --status noqemu --comment "ext nofpround" +# SIMD 4S when Q = 1 + +:fmlal Rd_VPR128.4S, vRn_VPR128^".4H", Rm_VPR64.4H +is b_31=0 & b_30=1 & b_2329=0b0011100 & b_22=0 & b_21=1 & b_1015=0b111011 & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Rm_VPR64.4H & Zd +{ + TMPD1 = Rn_VPR128[0,64]; + TMPD2 = Rm_VPR64.4H[0,64]; + # simd infix TMPD3 = TMPD1 f* TMPD2 on lane size 2 + TMPD3[0,16] = TMPD1[0,16] f* TMPD2[0,16]; + TMPD3[16,16] = TMPD1[16,16] f* TMPD2[16,16]; + TMPD3[32,16] = TMPD1[32,16] f* TMPD2[32,16]; + TMPD3[48,16] = TMPD1[48,16] f* TMPD2[48,16]; + # simd resize TMPQ4 = float2float(TMPD3) (lane size 2 to 4) + TMPQ4[0,32] = float2float(TMPD3[0,16]); + TMPQ4[32,32] = float2float(TMPD3[16,16]); + TMPQ4[64,32] = float2float(TMPD3[32,16]); + TMPQ4[96,32] = float2float(TMPD3[48,16]); + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ4 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ4[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ4[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ4[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ4[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.124 FMLAL, FMLAL2 (vector) page C7-2296 line 134298 MATCH x2e20cc00/mask=xbfe0fc00 +# CONSTRUCT x2e20cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:4 ARG3[1]:4 $f*@2 $float2float@2:8 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal2/3@2 +# AUNIT --inst x2e20cc00/mask=xffe0fc00 --rand sfp --status noqemu --comment "ext nofpround" +# SIMD 2S when Q = 0 + +:fmlal2 Rd_VPR64.2S, vRn_VPR64^".2H", vRm_VPR128^".2H" +is b_31=0 & b_30=0 & b_2329=0b1011100 & b_22=0 & b_21=1 & b_1015=0b110011 & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & vRm_VPR128 & Rm_VPR128 & Zd +{ + TMPS1 = Rn_VPR64[32,32]; + TMPS2 = Rm_VPR128[32,32]; + # simd infix TMPS3 = TMPS1 f* TMPS2 on lane size 2 + TMPS3[0,16] = TMPS1[0,16] f* TMPS2[0,16]; + TMPS3[16,16] = TMPS1[16,16] f* TMPS2[16,16]; + # simd resize TMPD4 = float2float(TMPS3) (lane size 2 to 4) + TMPD4[0,32] = float2float(TMPS3[0,16]); + TMPD4[32,32] = float2float(TMPS3[16,16]); + # simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD4 on lane size 4 + Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD4[0,32]; + Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD4[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.124 FMLAL, FMLAL2 (vector) page C7-2296 line 134298 MATCH x2e20cc00/mask=xbfe0fc00 +# CONSTRUCT x6e20cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 ARG3 $f*@2 $float2float@2:16 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal2/3@2 +# AUNIT --inst x6e20cc00/mask=xffe0fc00 --rand sfp --status noqemu --comment "ext nofpround" +# SIMD 4S when Q = 1 + +:fmlal2 Rd_VPR128.4S, vRn_VPR128^".4H", Rm_VPR64.4H +is b_31=0 & b_30=1 & b_2329=0b1011100 & b_22=0 & b_21=1 & b_1015=0b110011 & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Rm_VPR64.4H & Zd +{ + TMPD1 = Rn_VPR128[64,64]; + # simd infix TMPD2 = TMPD1 f* Rm_VPR64.4H on lane size 2 + TMPD2[0,16] = TMPD1[0,16] f* Rm_VPR64.4H[0,16]; + TMPD2[16,16] = TMPD1[16,16] f* Rm_VPR64.4H[16,16]; + TMPD2[32,16] = TMPD1[32,16] f* Rm_VPR64.4H[32,16]; + TMPD2[48,16] = TMPD1[48,16] f* Rm_VPR64.4H[48,16]; + # simd resize TMPQ3 = float2float(TMPD2) (lane size 2 to 4) + TMPQ3[0,32] = float2float(TMPD2[0,16]); + TMPQ3[32,32] = float2float(TMPD2[16,16]); + TMPQ3[64,32] = float2float(TMPD2[32,16]); + TMPQ3[96,32] = float2float(TMPD2[48,16]); + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.125 FMLS (by element) page C7-2298 line 134425 MATCH x0f805000/mask=xbf80f400 +# CONSTRUCT x4fc05000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $f* &=$f-@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@8 +# AUNIT --inst x4fc05000/mask=xffe0f400 --rand dfp --status pass --comment "nofpround" + +:fmls Rd_VPR128.2D, Rn_VPR128.2D, Re_VPR128.D.vIndex +is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=3 & b_2121=0 & Re_VPR128.D.vIndex & vIndex & Re_VPR128.D & b_1215=0x5 & b_1010=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + # simd element Re_VPR128.D[vIndex] lane size 8 + local tmp1:8 = Re_VPR128.D.vIndex; + # simd infix TMPQ1 = Rn_VPR128.2D f* tmp1 on lane size 8 + TMPQ1[0,64] = Rn_VPR128.2D[0,64] f* tmp1; + TMPQ1[64,64] = Rn_VPR128.2D[64,64] f* tmp1; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D f- TMPQ1 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] f- TMPQ1[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] f- TMPQ1[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.125 FMLS (by element) page C7-2298 line 134425 MATCH x0f805000/mask=xbf80f400 +# CONSTRUCT x0f805000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $f* &=$f-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@4 +# AUNIT --inst x0f805000/mask=xffc0f400 --rand sfp --status pass --comment "nofpround" + +:fmls Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex +is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x5 & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp1:4 = Re_VPR128.S.vIndex; + # simd infix TMPD1 = Rn_VPR64.2S f* tmp1 on lane size 4 + TMPD1[0,32] = Rn_VPR64.2S[0,32] f* tmp1; + TMPD1[32,32] = Rn_VPR64.2S[32,32] f* tmp1; + # simd infix Rd_VPR64.2S = Rd_VPR64.2S f- TMPD1 on lane size 4 + Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] f- TMPD1[0,32]; + Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] f- TMPD1[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.125 FMLS (by element) page C7-2298 line 134425 MATCH x0f805000/mask=xbf80f400 +# CONSTRUCT x4f805000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $f* &=$f-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@4 +# AUNIT --inst x4f805000/mask=xffc0f400 --rand sfp --status fail --comment "nofpround" + +:fmls Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex +is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x5 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp1:4 = Re_VPR128.S.vIndex; + # simd infix TMPQ1 = Rn_VPR128.4S f* tmp1 on lane size 4 + TMPQ1[0,32] = Rn_VPR128.4S[0,32] f* tmp1; + TMPQ1[32,32] = Rn_VPR128.4S[32,32] f* tmp1; + TMPQ1[64,32] = Rn_VPR128.4S[64,32] f* tmp1; + TMPQ1[96,32] = Rn_VPR128.4S[96,32] f* tmp1; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S f- TMPQ1 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] f- TMPQ1[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] f- TMPQ1[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] f- TMPQ1[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] f- TMPQ1[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.125 FMLS (by element) page C7-2298 line 134425 MATCH x5f005000/mask=xffc0f400 +# CONSTRUCT x5f005000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 f* &=f- +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@2 +# AUNIT --inst x5f005000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround" +# Scalar half-precision variant + +:fmls Rd_FPR16, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM +is b_2231=0b0101111100 & b_1215=0b0101 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_FPR16 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Zd +{ + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp1:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp2:2 = Rn_FPR16 f* tmp1; + Rd_FPR16 = Rd_FPR16 f- tmp2; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.125 FMLS (by element) page C7-2298 line 134425 MATCH x5f805000/mask=xff80f400 +# CONSTRUCT x5f805000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 f* &=f- +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@4 +# AUNIT --inst x5f805000/mask=xffc0f400 --rand sfp --status pass --comment "nofpround" +# Scalar, single-precision and double-precision variant, sz=0 + +:fmls Rd_FPR32, Rn_FPR32, Re_VPR128.S.vIndex +is b_2331=0b010111111 & b_22=0 & b_1215=0b0101 & b_10=0 & Re_VPR128.S & vIndex & Rd_FPR32 & Rn_FPR32 & Re_VPR128.S.vIndex & Zd +{ + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp1:4 = Re_VPR128.S.vIndex; + local tmp2:4 = Rn_FPR32 f* tmp1; + Rd_FPR32 = Rd_FPR32 f- tmp2; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.125 FMLS (by element) page C7-2298 line 134425 MATCH x5f805000/mask=xff80f400 +# CONSTRUCT x5fc05000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 f* &=f- +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@8 +# AUNIT --inst x5fc05000/mask=xffe0f400 --rand dfp --status pass --comment "nofpround" +# Scalar, single-precision and double-precision variant, sz=1 + +:fmls Rd_FPR64, Rn_FPR64, Re_VPR128.D.vIndex +is b_2331=0b010111111 & b_22=1 & b_21=0 & b_1215=0b0101 & b_10=0 & Re_VPR128.D & vIndex & Rd_FPR64 & Rn_FPR64 & Re_VPR128.D.vIndex & Zd +{ + # simd element Re_VPR128.D[vIndex] lane size 8 + local tmp1:8 = Re_VPR128.D.vIndex; + local tmp2:8 = Rn_FPR64 f* tmp1; + Rd_FPR64 = Rd_FPR64 f- tmp2; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.125 FMLS (by element) page C7-2298 line 134425 MATCH x0f005000/mask=xbfc0f400 +# CONSTRUCT x0f005000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $f*@2 &=$f-$@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@2 +# AUNIT --inst x0f005000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround" +# Vector, half-precision variant SIMD 4H when Q = 0 + +:fmls Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM +is b_31=0 & b_30=0 & b_2229=0b00111100 & b_1215=0b0101 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.4H & Rn_VPR64.4H & Re_VPR128Lo.H.vIndexHLM & Zd +{ + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp1:2 = Re_VPR128Lo.H.vIndexHLM; + # simd infix TMPD1 = Rn_VPR64.4H f* tmp1 on lane size 2 + TMPD1[0,16] = Rn_VPR64.4H[0,16] f* tmp1; + TMPD1[16,16] = Rn_VPR64.4H[16,16] f* tmp1; + TMPD1[32,16] = Rn_VPR64.4H[32,16] f* tmp1; + TMPD1[48,16] = Rn_VPR64.4H[48,16] f* tmp1; + # simd infix Rd_VPR64.4H = Rd_VPR64.4H f- TMPD1 on lane size 2 + Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] f- TMPD1[0,16]; + Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] f- TMPD1[16,16]; + Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] f- TMPD1[32,16]; + Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] f- TMPD1[48,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.125 FMLS (by element) page C7-2298 line 134425 MATCH x0f005000/mask=xbfc0f400 +# CONSTRUCT x4f005000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $f*@2 &=$f-$@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@2 +# AUNIT --inst x4f005000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround" +# Vector, half-precision variant SIMD 8H when Q = 1 + +:fmls Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM +is b_31=0 & b_30=1 & b_2229=0b00111100 & b_1215=0b0101 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.8H & Rn_VPR128.8H & Re_VPR128Lo.H.vIndexHLM & Zd +{ + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp1:2 = Re_VPR128Lo.H.vIndexHLM; + # simd infix TMPQ1 = Rn_VPR128.8H f* tmp1 on lane size 2 + TMPQ1[0,16] = Rn_VPR128.8H[0,16] f* tmp1; + TMPQ1[16,16] = Rn_VPR128.8H[16,16] f* tmp1; + TMPQ1[32,16] = Rn_VPR128.8H[32,16] f* tmp1; + TMPQ1[48,16] = Rn_VPR128.8H[48,16] f* tmp1; + TMPQ1[64,16] = Rn_VPR128.8H[64,16] f* tmp1; + TMPQ1[80,16] = Rn_VPR128.8H[80,16] f* tmp1; + TMPQ1[96,16] = Rn_VPR128.8H[96,16] f* tmp1; + TMPQ1[112,16] = Rn_VPR128.8H[112,16] f* tmp1; + # simd infix Rd_VPR128.8H = Rd_VPR128.8H f- TMPQ1 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] f- TMPQ1[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] f- TMPQ1[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] f- TMPQ1[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] f- TMPQ1[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] f- TMPQ1[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] f- TMPQ1[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] f- TMPQ1[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] f- TMPQ1[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.126 FMLS (vector) page C7-2302 line 134665 MATCH x0ea0cc00/mask=xbfa0fc00 +# CONSTRUCT x4ee0cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG1 $f*@8 &=$f-@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@8 +# AUNIT --inst x4ee0cc00/mask=xffe0fc00 --rand dfp --status fail --comment "nofpround" + +:fmls Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x19 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.2D f* Rd_VPR128.2D on lane size 8 + TMPQ1[0,64] = Rn_VPR128.2D[0,64] f* Rd_VPR128.2D[0,64]; + TMPQ1[64,64] = Rn_VPR128.2D[64,64] f* Rd_VPR128.2D[64,64]; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D f- TMPQ1 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] f- TMPQ1[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] f- TMPQ1[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.126 FMLS (vector) page C7-2302 line 134665 MATCH x0ea0cc00/mask=xbfa0fc00 +# CONSTRUCT x0ea0cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $f*@4 &=f-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@4 +# AUNIT --inst x0ea0cc00/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround" + +:fmls Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x19 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + # simd infix TMPD1 = Rn_VPR64.2S f* Rm_VPR64.2S on lane size 4 + TMPD1[0,32] = Rn_VPR64.2S[0,32] f* Rm_VPR64.2S[0,32]; + TMPD1[32,32] = Rn_VPR64.2S[32,32] f* Rm_VPR64.2S[32,32]; + Rd_VPR64.2S = Rd_VPR64.2S f- TMPD1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.126 FMLS (vector) page C7-2302 line 134665 MATCH x0ea0cc00/mask=xbfa0fc00 +# CONSTRUCT x4ea0cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@4 +# AUNIT --inst x4ea0cc00/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround" + +:fmls Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x19 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.4S f* Rm_VPR128.4S on lane size 4 + TMPQ1[0,32] = Rn_VPR128.4S[0,32] f* Rm_VPR128.4S[0,32]; + TMPQ1[32,32] = Rn_VPR128.4S[32,32] f* Rm_VPR128.4S[32,32]; + TMPQ1[64,32] = Rn_VPR128.4S[64,32] f* Rm_VPR128.4S[64,32]; + TMPQ1[96,32] = Rn_VPR128.4S[96,32] f* Rm_VPR128.4S[96,32]; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S f- TMPQ1 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] f- TMPQ1[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] f- TMPQ1[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] f- TMPQ1[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] f- TMPQ1[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.126 FMLS (vector) page C7-2302 line 134665 MATCH x0ec00c00/mask=xbfe0fc00 +# CONSTRUCT x0ec00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@2 +# AUNIT --inst x0ec00c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 4H when Q = 0 + +:fmls Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2129=0b001110110 & b_1015=0b000011 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + # simd infix TMPD1 = Rn_VPR64.4H f* Rm_VPR64.4H on lane size 4 + TMPD1[0,32] = Rn_VPR64.4H[0,32] f* Rm_VPR64.4H[0,32]; + TMPD1[32,32] = Rn_VPR64.4H[32,32] f* Rm_VPR64.4H[32,32]; + # simd infix Rd_VPR64.4H = Rd_VPR64.4H f- TMPD1 on lane size 4 + Rd_VPR64.4H[0,32] = Rd_VPR64.4H[0,32] f- TMPD1[0,32]; + Rd_VPR64.4H[32,32] = Rd_VPR64.4H[32,32] f- TMPD1[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.126 FMLS (vector) page C7-2302 line 134665 MATCH x0ec00c00/mask=xbfe0fc00 +# CONSTRUCT x4ec00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@2 +# AUNIT --inst x4ec00c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 8H when Q = 1 + +:fmls Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2129=0b001110110 & b_1015=0b000011 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.8H f* Rm_VPR128.8H on lane size 4 + TMPQ1[0,32] = Rn_VPR128.8H[0,32] f* Rm_VPR128.8H[0,32]; + TMPQ1[32,32] = Rn_VPR128.8H[32,32] f* Rm_VPR128.8H[32,32]; + TMPQ1[64,32] = Rn_VPR128.8H[64,32] f* Rm_VPR128.8H[64,32]; + TMPQ1[96,32] = Rn_VPR128.8H[96,32] f* Rm_VPR128.8H[96,32]; + # simd infix Rd_VPR128.8H = Rd_VPR128.8H f- TMPQ1 on lane size 4 + Rd_VPR128.8H[0,32] = Rd_VPR128.8H[0,32] f- TMPQ1[0,32]; + Rd_VPR128.8H[32,32] = Rd_VPR128.8H[32,32] f- TMPQ1[32,32]; + Rd_VPR128.8H[64,32] = Rd_VPR128.8H[64,32] f- TMPQ1[64,32]; + Rd_VPR128.8H[96,32] = Rd_VPR128.8H[96,32] f- TMPQ1[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.127 FMLSL, FMLSL2 (by element) page C7-2304 line 134788 MATCH x0f804000/mask=xbfc0f400 +# CONSTRUCT x0f804000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[0]:4 ARG3 $f* $float2float@2:8 &=$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl/3@2 +# AUNIT --inst x0f804000/mask=xffc0f400 --rand sfp --status noqemu --comment "ext nofpround" +# SIMD 2S when Q = 0 + +:fmlsl Rd_VPR64.2S, vRn_VPR64^".2H", Re_VPR128Lo.H.vIndexHLM +is b_31=0 & b_30=0 & b_2329=0b0011111 & b_22=0 & b_1215=0b0100 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & Re_VPR128Lo.H.vIndexHLM & Zd +{ + TMPS1 = Rn_VPR64[0,32]; + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp2:2 = Re_VPR128Lo.H.vIndexHLM; + # simd infix TMPS2 = TMPS1 f* tmp2 on lane size 2 + TMPS2[0,16] = TMPS1[0,16] f* tmp2; + TMPS2[16,16] = TMPS1[16,16] f* tmp2; + # simd resize TMPD3 = float2float(TMPS2) (lane size 2 to 4) + TMPD3[0,32] = float2float(TMPS2[0,16]); + TMPD3[32,32] = float2float(TMPS2[16,16]); + # simd infix Rd_VPR64.2S = Rd_VPR64.2S - TMPD3 on lane size 4 + Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] - TMPD3[0,32]; + Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] - TMPD3[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.127 FMLSL, FMLSL2 (by element) page C7-2304 line 134788 MATCH x0f804000/mask=xbfc0f400 +# CONSTRUCT x4f804000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[0]:8 ARG3 $f* $float2float@2:16 &=$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl/3@2 +# AUNIT --inst x4f804000/mask=xffc0f400 --rand sfp --status noqemu --comment "ext nofpround" +# SIMD 4S when Q = 1 + +:fmlsl Rd_VPR128.4S, vRn_VPR128^".4H", Re_VPR128Lo.H.vIndexHLM +is b_31=0 & b_30=1 & b_2329=0b0011111 & b_22=0 & b_1215=0b0100 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Re_VPR128Lo.H.vIndexHLM & Zd +{ + TMPD1 = Rn_VPR128[0,64]; + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp2:2 = Re_VPR128Lo.H.vIndexHLM; + # simd infix TMPD2 = TMPD1 f* tmp2 on lane size 2 + TMPD2[0,16] = TMPD1[0,16] f* tmp2; + TMPD2[16,16] = TMPD1[16,16] f* tmp2; + TMPD2[32,16] = TMPD1[32,16] f* tmp2; + TMPD2[48,16] = TMPD1[48,16] f* tmp2; + # simd resize TMPQ3 = float2float(TMPD2) (lane size 2 to 4) + TMPQ3[0,32] = float2float(TMPD2[0,16]); + TMPQ3[32,32] = float2float(TMPD2[16,16]); + TMPQ3[64,32] = float2float(TMPD2[32,16]); + TMPQ3[96,32] = float2float(TMPD2[48,16]); + # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.127 FMLSL, FMLSL2 (by element) page C7-2304 line 134788 MATCH x2f80c000/mask=xbfc0f400 +# CONSTRUCT x2f80c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:4 ARG3 $f* $float2float@2:8 &=$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl2/3@2 +# AUNIT --inst x2f80c000/mask=xffc0f400 --rand sfp --status noqemu --comment "ext nofpround" +# SIMD 2S when Q = 0 + +:fmlsl2 Rd_VPR64.2S, vRn_VPR64^".2H", Re_VPR128Lo.H.vIndexHLM +is b_31=0 & b_30=0 & b_2329=0b1011111 & b_22=0 & b_1215=0b1100 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & Re_VPR128Lo.H.vIndexHLM & Zd +{ + TMPS1 = Rn_VPR64[32,32]; + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp2:2 = Re_VPR128Lo.H.vIndexHLM; + # simd infix TMPS2 = TMPS1 f* tmp2 on lane size 2 + TMPS2[0,16] = TMPS1[0,16] f* tmp2; + TMPS2[16,16] = TMPS1[16,16] f* tmp2; + # simd resize TMPD3 = float2float(TMPS2) (lane size 2 to 4) + TMPD3[0,32] = float2float(TMPS2[0,16]); + TMPD3[32,32] = float2float(TMPS2[16,16]); + # simd infix Rd_VPR64.2S = Rd_VPR64.2S - TMPD3 on lane size 4 + Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] - TMPD3[0,32]; + Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] - TMPD3[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.127 FMLSL, FMLSL2 (by element) page C7-2304 line 134788 MATCH x2f80c000/mask=xbfc0f400 +# CONSTRUCT x6f80c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 ARG3 $f* $float2float@2:16 &=$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl2/3@2 +# AUNIT --inst x6f80c000/mask=xffc0f400 --rand sfp --status noqemu --comment "ext nofpround" +# SIMD 4S when Q = 1 + +:fmlsl2 Rd_VPR128.4S, vRn_VPR128^".4H", Re_VPR128Lo.H.vIndexHLM +is b_31=0 & b_30=1 & b_2329=0b1011111 & b_22=0 & b_1215=0b1100 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Re_VPR128Lo.H.vIndexHLM & Zd +{ + TMPD1 = Rn_VPR128[64,64]; + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp2:2 = Re_VPR128Lo.H.vIndexHLM; + # simd infix TMPD2 = TMPD1 f* tmp2 on lane size 2 + TMPD2[0,16] = TMPD1[0,16] f* tmp2; + TMPD2[16,16] = TMPD1[16,16] f* tmp2; + TMPD2[32,16] = TMPD1[32,16] f* tmp2; + TMPD2[48,16] = TMPD1[48,16] f* tmp2; + # simd resize TMPQ3 = float2float(TMPD2) (lane size 2 to 4) + TMPQ3[0,32] = float2float(TMPD2[0,16]); + TMPQ3[32,32] = float2float(TMPD2[16,16]); + TMPQ3[64,32] = float2float(TMPD2[32,16]); + TMPQ3[96,32] = float2float(TMPD2[48,16]); + # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.128 FMLSL, FMLSL2 (vector) page C7-2306 line 134921 MATCH x0ea0ec00/mask=xbfe0fc00 +# CONSTRUCT x0ea0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[0]:4 ARG3[0]:4 $f*@2 $float2float@2:8 &=$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl/3@2 +# AUNIT --inst x0ea0ec00/mask=xffe0fc00 --rand sfp --status noqemu --comment "ext nofpround" +# SIMD 2S when Q = 0 + +:fmlsl Rd_VPR64.2S, vRn_VPR64^".2H", vRm_VPR64^".2H" +is b_31=0 & b_30=0 & b_2329=0b0011101 & b_22=0 & b_21=1 & b_1015=0b111011 & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & vRm_VPR64 & Rm_VPR64 & Zd +{ + TMPS1 = Rn_VPR64[0,32]; + TMPS2 = Rm_VPR64[0,32]; + # simd infix TMPS3 = TMPS1 f* TMPS2 on lane size 2 + TMPS3[0,16] = TMPS1[0,16] f* TMPS2[0,16]; + TMPS3[16,16] = TMPS1[16,16] f* TMPS2[16,16]; + # simd resize TMPD4 = float2float(TMPS3) (lane size 2 to 4) + TMPD4[0,32] = float2float(TMPS3[0,16]); + TMPD4[32,32] = float2float(TMPS3[16,16]); + # simd infix Rd_VPR64.2S = Rd_VPR64.2S - TMPD4 on lane size 4 + Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] - TMPD4[0,32]; + Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] - TMPD4[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.128 FMLSL, FMLSL2 (vector) page C7-2306 line 134921 MATCH x0ea0ec00/mask=xbfe0fc00 +# CONSTRUCT x4ea0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[0]:8 ARG3[0]:8 $f*@2 $float2float@2:16 &=$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl/3@2 +# AUNIT --inst x4ea0ec00/mask=xffe0fc00 --rand sfp --status noqemu --comment "ext nofpround" +# SIMD 4S when Q = 1 + +:fmlsl Rd_VPR128.4S, vRn_VPR128^".4H", Rm_VPR64.4H +is b_31=0 & b_30=1 & b_2329=0b0011101 & b_22=0 & b_21=1 & b_1015=0b111011 & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Rm_VPR64.4H & Zd +{ + TMPD1 = Rn_VPR128[0,64]; + TMPD2 = Rm_VPR64.4H[0,64]; + # simd infix TMPD3 = TMPD1 f* TMPD2 on lane size 2 + TMPD3[0,16] = TMPD1[0,16] f* TMPD2[0,16]; + TMPD3[16,16] = TMPD1[16,16] f* TMPD2[16,16]; + TMPD3[32,16] = TMPD1[32,16] f* TMPD2[32,16]; + TMPD3[48,16] = TMPD1[48,16] f* TMPD2[48,16]; + # simd resize TMPQ4 = float2float(TMPD3) (lane size 2 to 4) + TMPQ4[0,32] = float2float(TMPD3[0,16]); + TMPQ4[32,32] = float2float(TMPD3[16,16]); + TMPQ4[64,32] = float2float(TMPD3[32,16]); + TMPQ4[96,32] = float2float(TMPD3[48,16]); + # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ4 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ4[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ4[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ4[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ4[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.128 FMLSL, FMLSL2 (vector) page C7-2306 line 134921 MATCH x2ea0cc00/mask=xbfe0fc00 +# CONSTRUCT x2ea0cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:4 ARG3[1]:4 $f*@2 $float2float@2:8 &=$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl2/3@2 +# AUNIT --inst x2ea0cc00/mask=xffe0fc00 --rand sfp --status noqemu --comment "ext nofpround" +# SIMD 2S when Q = 0 + +:fmlsl2 Rd_VPR64.2S, vRn_VPR64^".2H", vRm_VPR128^".2H" +is b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=0 & b_21=1 & b_1015=0b110011 & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & vRm_VPR128 & Rm_VPR128 & Zd +{ + TMPS1 = Rn_VPR64[32,32]; + TMPS2 = Rm_VPR128[32,32]; + # simd infix TMPS3 = TMPS1 f* TMPS2 on lane size 2 + TMPS3[0,16] = TMPS1[0,16] f* TMPS2[0,16]; + TMPS3[16,16] = TMPS1[16,16] f* TMPS2[16,16]; + # simd resize TMPD4 = float2float(TMPS3) (lane size 2 to 4) + TMPD4[0,32] = float2float(TMPS3[0,16]); + TMPD4[32,32] = float2float(TMPS3[16,16]); + # simd infix Rd_VPR64.2S = Rd_VPR64.2S - TMPD4 on lane size 4 + Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] - TMPD4[0,32]; + Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] - TMPD4[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.128 FMLSL, FMLSL2 (vector) page C7-2306 line 134921 MATCH x2ea0cc00/mask=xbfe0fc00 +# CONSTRUCT x6ea0cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 ARG3 $f*@2 $float2float@2:16 &=$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl2/3@2 +# AUNIT --inst x6ea0cc00/mask=xffe0fc00 --rand sfp --status noqemu --comment "ext nofpround" +# SIMD 4S when Q = 1 + +:fmlsl2 Rd_VPR128.4S, vRn_VPR128^".4H", Rm_VPR64.4H +is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=0 & b_21=1 & b_1015=0b110011 & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Rm_VPR64.4H & Zd +{ + TMPD1 = Rn_VPR128[64,64]; + # simd infix TMPD2 = TMPD1 f* Rm_VPR64.4H on lane size 2 + TMPD2[0,16] = TMPD1[0,16] f* Rm_VPR64.4H[0,16]; + TMPD2[16,16] = TMPD1[16,16] f* Rm_VPR64.4H[16,16]; + TMPD2[32,16] = TMPD1[32,16] f* Rm_VPR64.4H[32,16]; + TMPD2[48,16] = TMPD1[48,16] f* Rm_VPR64.4H[48,16]; + # simd resize TMPQ3 = float2float(TMPD2) (lane size 2 to 4) + TMPQ3[0,32] = float2float(TMPD2[0,16]); + TMPQ3[32,32] = float2float(TMPD2[16,16]); + TMPQ3[64,32] = float2float(TMPD2[32,16]); + TMPQ3[96,32] = float2float(TMPD2[48,16]); + # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.129 FMOV (vector, immediate) page C7-2308 line 135048 MATCH x0f00f400/mask=x9ff8fc00 +# C7.2.20 BIC (vector, immediate) page C7-2048 line 119572 MATCH x2f001400/mask=xbff81c00 +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00 +# CONSTRUCT x6f00f400/mask=xfff8fc00 MATCHED 4 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1@8 +# AUNIT --inst x6f00f400/mask=xfff8fc00 --rand dfp --status nopcodeop + +:fmov Rd_VPR128.2D, Imm_neon_uimm8Shift +is b_3131=0 & q=1 & b_29=1 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & cmode=0xf & b_1011=1 & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_fmov(Imm_neon_uimm8Shift, 8:1); +} + +# C7.2.129 FMOV (vector, immediate) page C7-2308 line 135048 MATCH x0f00f400/mask=x9ff8fc00 +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.212 ORR (vector, immediate) page C7-2507 line 146708 MATCH x0f001400/mask=xbff81c00 +# CONSTRUCT x0f00f400/mask=xfff8fc00 MATCHED 3 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2:4 =NEON_fmov/1@4 +# AUNIT --inst x0f00f400/mask=xfff8fc00 --rand dfp --status nopcodeop + +:fmov Rd_VPR64.2S, Imm_neon_uimm8Shift +is b_3131=0 & q=0 & b_29=0 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & cmode=0xf & b_1011=1 & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_fmov(Imm_neon_uimm8Shift:4, 4:1); +} + +# C7.2.129 FMOV (vector, immediate) page C7-2308 line 135048 MATCH x0f00f400/mask=x9ff8fc00 +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.212 ORR (vector, immediate) page C7-2507 line 146708 MATCH x0f001400/mask=xbff81c00 +# CONSTRUCT x4f00f400/mask=xfff8fc00 MATCHED 3 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2:4 =NEON_fmov/1@4 +# AUNIT --inst x4f00f400/mask=xfff8fc00 --rand sfp --status nopcodeop + +:fmov Rd_VPR128.4S, Imm_neon_uimm8Shift +is b_3131=0 & q=1 & b_29=0 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & cmode=0xf & b_1011=1 & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_fmov(Imm_neon_uimm8Shift:4, 4:1); +} + +# C7.2.129 FMOV (vector, immediate) page C7-2308 line 135048 MATCH x0f00fc00/mask=xbff8fc00 +# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x0f00fc00/mask=xbf80fc00 +# CONSTRUCT x0f00fc00/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 int2float:2 &=$dup +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1@2 +# AUNIT --inst x0f00fc00/mask=xfff8fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 4H when Q = 0 + +:fmov Rd_VPR64.4H, Imm_neon_uimm8Shift +is b_31=0 & b_30=0 & b_1929=0b00111100000 & b_1015=0b111111 & Rd_VPR64.4H & Imm_neon_uimm8Shift & Zd +{ + local tmp1:2 = int2float(Imm_neon_uimm8Shift); + # simd duplicate Rd_VPR64.4H = all elements tmp1 (lane size 2) + Rd_VPR64.4H[0,16] = tmp1; + Rd_VPR64.4H[16,16] = tmp1; + Rd_VPR64.4H[32,16] = tmp1; + Rd_VPR64.4H[48,16] = tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.129 FMOV (vector, immediate) page C7-2308 line 135048 MATCH x0f00fc00/mask=xbff8fc00 +# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x0f00fc00/mask=xbf80fc00 +# CONSTRUCT x4f00fc00/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 int2float:2 &=$dup +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1@2 +# AUNIT --inst x4f00fc00/mask=xfff8fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant SIMD 8H when Q = 1 + +:fmov Rd_VPR128.8H, Imm_neon_uimm8Shift +is b_31=0 & b_30=1 & b_1929=0b00111100000 & b_1015=0b111111 & Rd_VPR128.8H & Imm_neon_uimm8Shift & Zd +{ + local tmp1:2 = int2float(Imm_neon_uimm8Shift); + # simd duplicate Rd_VPR128.8H = all elements tmp1 (lane size 2) + Rd_VPR128.8H[0,16] = tmp1; + Rd_VPR128.8H[16,16] = tmp1; + Rd_VPR128.8H[32,16] = tmp1; + Rd_VPR128.8H[48,16] = tmp1; + Rd_VPR128.8H[64,16] = tmp1; + Rd_VPR128.8H[80,16] = tmp1; + Rd_VPR128.8H[96,16] = tmp1; + Rd_VPR128.8H[112,16] = tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.130 FMOV (register) page C7-2310 line 135162 MATCH x1e204000/mask=xff3ffc00 +# CONSTRUCT x1ee04000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 = +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1 +# AUNIT --inst x1ee04000/mask=xfffffc00 --rand hfp --status noqemu +# Half-precision variant when type == 11 arg1=Rd_FPR16 arg2=Rn_FPR16 + +:fmov Rd_FPR16, Rn_FPR16 +is b_2431=0b00011110 & b_2223=0b11 & b_1021=0b100000010000 & Rd_FPR16 & Rn_FPR16 & Rd_FPR64 & Zd +{ + Rd_FPR16 = Rn_FPR16; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.130 FMOV (register) page C7-2310 line 135162 MATCH x1e204000/mask=xff3ffc00 +# CONSTRUCT x1e204000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 = +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1 +# AUNIT --inst x1e204000/mask=xfffffc00 --rand sfp --status pass +# Single-precision variant when type == 00 arg1=Rd_FPR32 arg2=Rn_FPR32 + +:fmov Rd_FPR32, Rn_FPR32 +is b_2431=0b00011110 & b_2223=0b00 & b_1021=0b100000010000 & Rd_FPR32 & Rn_FPR32 & Zd +{ + Rd_FPR32 = Rn_FPR32; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.130 FMOV (register) page C7-2310 line 135162 MATCH x1e204000/mask=xff3ffc00 +# CONSTRUCT x1e604000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 = +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1 +# AUNIT --inst x1e604000/mask=xfffffc00 --rand dfp --status pass +# Double-precision variant when type == 01 arg1=Rd_FPR64 arg2=Rn_FPR64 + +:fmov Rd_FPR64, Rn_FPR64 +is b_2431=0b00011110 & b_2223=0b01 & b_1021=0b100000010000 & Rd_FPR64 & Rn_FPR64 & Zd +{ + Rd_FPR64 = Rn_FPR64; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00 +# CONSTRUCT x1e660000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =float2float +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1 +# AUNIT --inst x1e660000/mask=xfffffc00 --rand dfp --status noqemu --comment "nofpround" +# UNDOCUMENTED Double-precision to 32-bit variant when sf == 0 && type == 01 && rmode == 00 && opcode = 110 arg1=Rd_GPR32 arg2=Rn_FPR64 + +:fmov Rd_GPR32, Rn_FPR64 +is b_31=0 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1920=0b00 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR32 & Rn_FPR64 & Rd_GPR64 +{ + Rd_GPR32 = float2float(Rn_FPR64); + zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64 +} + +# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00 +# CONSTRUCT x9e260000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =float2float +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1 +# AUNIT --inst x9e260000/mask=xfffffc00 --rand sfp --status noqemu --comment "nofpround" +# UNDOCUMENTED Single-precision to 64-bit variant when sf == 1 && type == 00 && rmode == 00 && opcode = 110 arg1=Rd_GPR64 arg2=Rn_FPR32 + +:fmov Rd_GPR64, Rn_FPR32 +is b_31=1 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1920=0b00 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR64 & Rn_FPR32 +{ + Rd_GPR64 = float2float(Rn_FPR32); +} + +# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00 +# CONSTRUCT x1e670000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =float2float +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1 +# AUNIT --inst x1e670000/mask=xfffffc00 --rand dfp --status noqemu --comment "nofpround" +# UNDOCUMENTED 32-bit to Double-precision variant when sf == 0 && type == 01 && rmode == 00 && opcode = 111 arg1=Rd_FPR64 arg2=Rn_GPR32 + +:fmov Rd_FPR64, Rn_GPR32 +is b_31=0 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1920=0b00 & b_1618=0b111 & b_1015=0b000000 & Rd_FPR64 & Rn_GPR32 & Zd +{ + Rd_FPR64 = float2float(Rn_GPR32); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00 +# CONSTRUCT x9e270000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =float2float +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1 +# AUNIT --inst x9e270000/mask=xfffffc00 --rand sfp --status noqemu --comment "nofpround" +# UNDOCUMENTED 64-bit to single-precision variant when sf == 1 && type == 00 && rmode == 00 && opcode = 111 arg1=Rd_FPR32 arg2=Rn_GPR64 + +:fmov Rd_FPR32, Rn_GPR64 +is b_31=1 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1920=0b00 & b_1618=0b111 & b_1015=0b000000 & Rd_FPR32 & Rn_GPR64 & Zd +{ + Rd_FPR32 = float2float(Rn_GPR64); + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00 +# CONSTRUCT x1ee60000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =float2float +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1 +# AUNIT --inst x1ee60000/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision to 32-bit variant when sf == 0 && type == 11 && rmode == 00 && opcode == 110 arg1=Rd_GPR32 arg2=Rn_FPR16 + +:fmov Rd_GPR32, Rn_FPR16 +is b_31=0 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1920=0b00 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR32 & Rn_FPR16 & Rd_GPR64 +{ + Rd_GPR32 = float2float(Rn_FPR16); + zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64 +} + +# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00 +# CONSTRUCT x9ee60000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =float2float +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1 +# AUNIT --inst x9ee60000/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision to 64-bit variant when sf == 1 && type == 11 && rmode == 00 && opcode == 110 arg1=Rd_GPR64 arg2=Rn_FPR16 + +:fmov Rd_GPR64, Rn_FPR16 +is b_31=1 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1920=0b00 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR64 & Rn_FPR16 +{ + Rd_GPR64 = float2float(Rn_FPR16); +} + +# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00 +# CONSTRUCT x1ee70000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =float2float +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1 +# AUNIT --inst x1ee70000/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# 32-bit to half-precision variant when sf == 0 && type == 11 && rmode == 00 && opcode == 111 arg1=Rd_FPR16 arg2=Rn_GPR32 + +:fmov Rd_FPR16, Rn_GPR32 +is b_31=0 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1920=0b00 & b_1618=0b111 & b_1015=0b000000 & Rd_FPR16 & Rn_GPR32 & Zd +{ + Rd_FPR16 = float2float(Rn_GPR32); + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00 +# CONSTRUCT x1e270000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 = +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1 +# AUNIT --inst x1e270000/mask=xfffffc00 --rand sfp --status pass --comment "nofpround" +# 32-bit to single-precision variant when sf == 0 && type == 00 && rmode == 00 && opcode == 111 arg1=Rd_FPR32 arg2=Rn_GPR32 + +:fmov Rd_FPR32, Rn_GPR32 +is b_31=0 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1920=0b00 & b_1618=0b111 & b_1015=0b000000 & Rd_FPR32 & Rn_GPR32 & Zd +{ + Rd_FPR32 = Rn_GPR32; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00 +# CONSTRUCT x1e260000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 = +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1 +# AUNIT --inst x1e260000/mask=xfffffc00 --rand sfp --status pass --comment "nofpround" +# Single-precision to 32-bit variant when sf == 0 && type == 00 && rmode == 00 && opcode == 110 arg1=Rd_GPR32 arg2=Rn_FPR32 + +:fmov Rd_GPR32, Rn_FPR32 +is b_31=0 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1920=0b00 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR32 & Rn_FPR32 & Rd_GPR64 +{ + Rd_GPR32 = Rn_FPR32; + zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64 +} + +# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00 +# CONSTRUCT x9ee70000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =float2float +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1 +# AUNIT --inst x9ee70000/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# 64-bit to half-precision variant when sf == 1 && type == 11 && rmode == 00 && opcode == 111 arg1=Rd_FPR16 arg2=Rn_GPR64 + +:fmov Rd_FPR16, Rn_GPR64 +is b_31=1 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1920=0b00 & b_1618=0b111 & b_1015=0b000000 & Rd_FPR16 & Rn_GPR64 & Zd +{ + Rd_FPR16 = float2float(Rn_GPR64); + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00 +# CONSTRUCT x9e670000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 = +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1 +# AUNIT --inst x9e670000/mask=xfffffc00 --rand dfp --status pass --comment "nofpround" +# 64-bit to double-precision variant when sf == 1 && type == 01 && rmode == 00 && opcode == 111 arg1=Rd_FPR64 arg2=Rn_GPR64 + +:fmov Rd_FPR64, Rn_GPR64 +is b_31=1 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1920=0b00 & b_1618=0b111 & b_1015=0b000000 & Rd_FPR64 & Rn_GPR64 & Zd +{ + Rd_FPR64 = Rn_GPR64; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00 +# CONSTRUCT x9eaf0000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 1:1 &=$copy@8 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_fmov/2 +# AUNIT --inst x9eaf0000/mask=xfffffc00 --rand dfp --status pass --comment "nofpround" +# 64-bit to top half of 128-bit variant when sf == 1 && type == 10 && rmode == 01 && opcode == 111 arg1=vRd_VPR128^".D[1]" arg2=Rn_GPR64 + +:fmov vRd_VPR128^".D[1]", Rn_GPR64 +is b_31=1 & b_2430=0b0011110 & b_2223=0b10 & b_21=1 & b_1920=0b01 & b_1618=0b111 & b_1015=0b000000 & vRd_VPR128 & Rd_VPR128 & Rn_GPR64 & Zd +{ + # simd copy Rd_VPR128 element 1:1 = Rn_GPR64 (lane size 8) + Rd_VPR128[64,64] = Rn_GPR64; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00 +# CONSTRUCT x9e660000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 = +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1 +# AUNIT --inst x9e660000/mask=xfffffc00 --rand dfp --status pass --comment "nofpround" +# Double-precision to 64-bit variant when sf == 1 && type == 01 && rmode == 00 && opcode == 110 arg1=Rd_GPR64 arg2=Rn_FPR64 + +:fmov Rd_GPR64, Rn_FPR64 +is b_31=1 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1920=0b00 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR64 & Rn_FPR64 +{ + Rd_GPR64 = Rn_FPR64; +} + +# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00 +# CONSTRUCT x9eae0000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 =ARG2[1]:8 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1@8 +# AUNIT --inst x9eae0000/mask=xfffffc00 --rand dfp --status pass --comment "nofpround" +# Top half of 128-bit to 64-bit variant when sf == 1 && type == 10 && rmode == 01 && opcode == 110 arg1=Rd_GPR64 arg2=vRd_VPR128^".D[1]" + +:fmov Rd_GPR64, vRn_VPR128^".D[1]" +is b_31=1 & b_2430=0b0011110 & b_2223=0b10 & b_21=1 & b_1920=0b01 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR64 & vRn_VPR128 & Rn_VPR128 +{ + Rd_GPR64 = Rn_VPR128[64,64]; +} + +# C7.2.132 FMOV (scalar, immediate) page C7-2316 line 135493 MATCH x1e201000/mask=xff201fe0 +# CONSTRUCT x1e601001/mask=xffe01fe1 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 = +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1 +# AUNIT --inst x1e601001/mask=xffe01fe1 --rand dfp --status pass + +:fmov Rd_FPR64, Imm8_fmov64_operand +is ImmS_ImmR_TestSet=1 & m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Imm8_fmov64_operand & b_1012=4 & imm5=0x0 & Rd_FPR64 & Zd +{ + Rd_FPR64 = Imm8_fmov64_operand:8; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.132 FMOV (scalar, immediate) page C7-2316 line 135493 MATCH x1e201000/mask=xff201fe0 +# CONSTRUCT x1e201000/mask=xffe01fe0 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 = +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1 +# AUNIT --inst x1e201000/mask=xffe01fe0 --rand sfp --status pass + +:fmov Rd_FPR32, Imm8_fmov32_operand +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Imm8_fmov32_operand & b_1012=4 & imm5=0x0 & Rd_FPR32 & Zd +{ + Rd_FPR32 = Imm8_fmov32_operand:4; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.132 FMOV (scalar, immediate) page C7-2316 line 135493 MATCH x1e201000/mask=xff201fe0 +# CONSTRUCT x1ee01000/mask=xffe01fe0 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 = +# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1 +# AUNIT --inst x1ee01000/mask=xffe01fe0 --rand hfp --status noqemu + +:fmov Rd_FPR16, Imm8_fmov16_operand +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Imm8_fmov16_operand & b_1012=4 & imm5=0x0 & Rd_FPR16 & Zd +{ + Rd_FPR16 = Imm8_fmov16_operand:2; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.133 FMSUB page C7-2318 line 135582 MATCH x1f008000/mask=xff208000 +# CONSTRUCT x1f408000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fmsub/3 +# AUNIT --inst x1f408000/mask=xffe08000 --rand dfp --status nopcodeop --comment "nofpround" + +:fmsub Rd_FPR64, Rn_FPR64, Rm_FPR64, Ra_FPR64 +is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=1 & b_21=0 & Rm_FPR64 & b_15=1 & Ra_FPR64 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_fmsub(Rn_FPR64, Rm_FPR64, Ra_FPR64); +} + +# C7.2.133 FMSUB page C7-2318 line 135582 MATCH x1f008000/mask=xff208000 +# CONSTRUCT x1f008000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fmsub/3 +# AUNIT --inst x1f008000/mask=xffe08000 --rand sfp --status nopcodeop --comment "nofpround" + +:fmsub Rd_FPR32, Rn_FPR32, Rm_FPR32, Ra_FPR32 +is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=0 & b_21=0 & Rm_FPR32 & b_15=1 & Ra_FPR32 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_fmsub(Rn_FPR32, Rm_FPR32, Ra_FPR32); +} + +# C7.2.133 FMSUB page C7-2318 line 135582 MATCH x1f008000/mask=xff208000 +# CONSTRUCT x1fc08000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fmsub/3 +# AUNIT --inst x1fc08000/mask=xffe08000 --rand hfp --status noqemu --comment "nofpround" + +:fmsub Rd_FPR16, Rn_FPR16, Rm_FPR16, Ra_FPR16 +is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=3 & b_21=0 & Rm_FPR16 & b_15=1 & Ra_FPR16 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_fmsub(Rn_FPR16, Rm_FPR16, Ra_FPR16); +} + +# C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x5f009000/mask=xffc0f400 +# CONSTRUCT x5f009000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =f* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@2 +# AUNIT --inst x5f009000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround" +# FMUL (by element) Scalar, half-precision + +:fmul Rd_FPR16, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM +is b_2231=0b0101111100 & b_1215=0b1001 & b_10=0 & Rd_FPR16 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd +{ + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp1:2 = Re_VPR128Lo.H.vIndexHLM; + Rd_FPR16 = Rn_FPR16 f* tmp1; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x5f809000/mask=xff80f400 +# CONSTRUCT x5f809000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =f* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@4 +# AUNIT --inst x5f809000/mask=xffc0f400 --rand sfp --status pass --comment "nofpround" +# FMUL (by element) Scalar, single-precision and double-precision sz=0 + +:fmul Rd_FPR32, Rn_FPR32, Re_VPR128.S.vIndex +is b_2331=0b010111111 & b_22=0 & b_1215=0b1001 & b_10=0 & Re_VPR128.S & vIndex & Rd_FPR32 & Rn_FPR32 & Re_VPR128.S.vIndex & Zd +{ + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp1:4 = Re_VPR128.S.vIndex; + Rd_FPR32 = Rn_FPR32 f* tmp1; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x5f809000/mask=xff80f400 +# CONSTRUCT x5fc09000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =f* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@8 +# AUNIT --inst x5fc09000/mask=xffe0f400 --rand dfp --status pass --comment "nofpround" +# FMUL (by element) Scalar, single-precision and double-precision sz=1 + +:fmul Rd_FPR64, Rn_FPR64, Re_VPR128.D.vIndex +is b_2331=0b010111111 & b_22=1 & b_21=0 & b_1215=0b1001 & b_10=0 & Re_VPR128.D & vIndex & Rd_FPR64 & Rn_FPR64 & Re_VPR128.D.vIndex & Zd +{ + # simd element Re_VPR128.D[vIndex] lane size 8 + local tmp1:8 = Re_VPR128.D.vIndex; + Rd_FPR64 = Rn_FPR64 f* tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x0f009000/mask=xbfc0f400 +# CONSTRUCT x0f009000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@2 +# AUNIT --inst x0f009000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround" +# FMUL (by element) Vector, half-precision, Q=0 + +:fmul Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM +is b_31=0 &b_30=0 & b_2229=0b00111100 & b_1215=0b1001 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.4H & Rn_VPR64.4H & Re_VPR128Lo.H.vIndexHLM & Zd +{ + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp1:2 = Re_VPR128Lo.H.vIndexHLM; + # simd infix Rd_VPR64.4H = Rn_VPR64.4H f* tmp1 on lane size 2 + Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f* tmp1; + Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f* tmp1; + Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f* tmp1; + Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f* tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x0f009000/mask=xbfc0f400 +# CONSTRUCT x4f009000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@2 +# AUNIT --inst x4f009000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround" +# FMUL (by element) Vector, half-precision, Q=1 + +:fmul Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM +is b_31=0 &b_30=1 & b_2229=0b00111100 & b_1215=0b1001 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.8H & Rn_VPR128.8H & Re_VPR128Lo.H.vIndexHLM & Zd +{ + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp1:2 = Re_VPR128Lo.H.vIndexHLM; + # simd infix Rd_VPR128.8H = Rn_VPR128.8H f* tmp1 on lane size 2 + Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f* tmp1; + Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f* tmp1; + Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f* tmp1; + Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f* tmp1; + Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f* tmp1; + Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f* tmp1; + Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f* tmp1; + Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f* tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x0f809000/mask=xbf80f400 +# CONSTRUCT x4fc09000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@8 +# AUNIT --inst x4fc09000/mask=xffe0f400 --rand dfp --status pass --comment "nofpround" +# Vector, single-precision and double-precision Q=1 and sz:L=10 + +:fmul Rd_VPR128.2D, Rn_VPR128.2D, Re_VPR128.D.vIndex +is b_31=0 & b_30=1 & b_2329=0b0011111 & b_22=1 & b_21=0 & b_1215=0b1001 & b_10=0 & Re_VPR128.D.vIndex & vIndex & Re_VPR128.D & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + # simd element Re_VPR128.D[vIndex] lane size 8 + local tmp1:8 = Re_VPR128.D.vIndex; + # simd infix Rd_VPR128.2D = Rn_VPR128.2D f* tmp1 on lane size 8 + Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] f* tmp1; + Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] f* tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x0f809000/mask=xbf80f400 +# CONSTRUCT x0f809000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@4 +# AUNIT --inst x0f809000/mask=xffc0f400 --rand sfp --status fail --comment "nofpround" +# Vector, single-precision and double-precision Q=0 and sz:L=0x + +:fmul Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex +is b_31=0 & b_30=0 & b_2329=0b0011111 & b_22=0 & b_1215=0b1001 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp1:4 = Re_VPR128.S.vIndex; + # simd infix Rd_VPR64.2S = Rn_VPR64.2S f* tmp1 on lane size 4 + Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] f* tmp1; + Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] f* tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x0f809000/mask=xbf80f400 +# CONSTRUCT x4f809000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@4 +# AUNIT --inst x4f809000/mask=xffc0f400 --rand sfp --status fail --comment "nofpround" +# Vector, single-precision and double-precision Q=1 and sz:L=0x + +:fmul Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex +is b_31=0 & b_30=1 & b_2329=0b0011111 & b_22=0 & b_1215=0b1001 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp1:4 = Re_VPR128.S.vIndex; + # simd infix Rd_VPR128.4S = Rn_VPR128.4S f* tmp1 on lane size 4 + Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] f* tmp1; + Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] f* tmp1; + Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] f* tmp1; + Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] f* tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.135 FMUL (vector) page C7-2324 line 135951 MATCH x2e20dc00/mask=xbfa0fc00 +# CONSTRUCT x6e60dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f*@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@8 +# AUNIT --inst x6e60dc00/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround" + +:fmul Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1b & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + # simd infix Rd_VPR128.2D = Rn_VPR128.2D f* Rm_VPR128.2D on lane size 8 + Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] f* Rm_VPR128.2D[0,64]; + Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] f* Rm_VPR128.2D[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.135 FMUL (vector) page C7-2324 line 135951 MATCH x2e20dc00/mask=xbfa0fc00 +# CONSTRUCT x2e20dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f*@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@4 +# AUNIT --inst x2e20dc00/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround" + +:fmul Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1b & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + # simd infix Rd_VPR64.2S = Rn_VPR64.2S f* Rm_VPR64.2S on lane size 4 + Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] f* Rm_VPR64.2S[0,32]; + Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] f* Rm_VPR64.2S[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.135 FMUL (vector) page C7-2324 line 135951 MATCH x2e20dc00/mask=xbfa0fc00 +# CONSTRUCT x6e20dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f*@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@4 +# AUNIT --inst x6e20dc00/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround" + +:fmul Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1b & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd infix Rd_VPR128.4S = Rn_VPR128.4S f* Rm_VPR128.4S on lane size 4 + Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] f* Rm_VPR128.4S[0,32]; + Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] f* Rm_VPR128.4S[32,32]; + Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] f* Rm_VPR128.4S[64,32]; + Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] f* Rm_VPR128.4S[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.135 FMUL (vector) page C7-2324 line 135951 MATCH x2e401c00/mask=xbfe0fc00 +# CONSTRUCT x2e401c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f*@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@2 +# AUNIT --inst x2e401c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant when Q=0 suf=VPR64.4H + +:fmul Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b000111 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + # simd infix Rd_VPR64.4H = Rn_VPR64.4H f* Rm_VPR64.4H on lane size 2 + Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f* Rm_VPR64.4H[0,16]; + Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f* Rm_VPR64.4H[16,16]; + Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f* Rm_VPR64.4H[32,16]; + Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f* Rm_VPR64.4H[48,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.135 FMUL (vector) page C7-2324 line 135951 MATCH x2e401c00/mask=xbfe0fc00 +# CONSTRUCT x6e401c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f*@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@2 +# AUNIT --inst x6e401c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant when Q=1 suf=VPR128.8H + +:fmul Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b000111 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + # simd infix Rd_VPR128.8H = Rn_VPR128.8H f* Rm_VPR128.8H on lane size 2 + Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f* Rm_VPR128.8H[0,16]; + Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f* Rm_VPR128.8H[16,16]; + Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f* Rm_VPR128.8H[32,16]; + Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f* Rm_VPR128.8H[48,16]; + Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f* Rm_VPR128.8H[64,16]; + Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f* Rm_VPR128.8H[80,16]; + Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f* Rm_VPR128.8H[96,16]; + Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f* Rm_VPR128.8H[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.136 FMUL (scalar) page C7-2326 line 136066 MATCH x1e200800/mask=xff20fc00 +# CONSTRUCT x1e600800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =f* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2 +# AUNIT --inst x1e600800/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround" + +:fmul Rd_FPR64, Rn_FPR64, Rm_FPR64 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x0 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = Rn_FPR64 f* Rm_FPR64; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.136 FMUL (scalar) page C7-2326 line 136066 MATCH x1e200800/mask=xff20fc00 +# CONSTRUCT x1e200800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =f* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2 +# AUNIT --inst x1e200800/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround" + +:fmul Rd_FPR32, Rn_FPR32, Rm_FPR32 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x0 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = Rn_FPR32 f* Rm_FPR32; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.136 FMUL (scalar) page C7-2326 line 136066 MATCH x1e200800/mask=xff20fc00 +# CONSTRUCT x1ee00800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =f* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2 +# AUNIT --inst x1ee00800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" + +:fmul Rd_FPR16, Rn_FPR16, Rm_FPR16 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x0 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = Rn_FPR16 f* Rm_FPR16; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.137 FMULX (by element) page C7-2328 line 136175 MATCH x2f809000/mask=xbf80f400 +# CONSTRUCT x6fc09000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@8 +# AUNIT --inst x6fc09000/mask=xffe0f400 --rand dfp --status nopcodeop --comment "nofpround" + +:fmulx Rd_VPR128.2D, Rn_VPR128.2D, Re_VPR128.D.vIndex +is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=3 & b_2121=0 & Re_VPR128.D.vIndex & vIndex & Re_VPR128.D & b_1215=0x9 & b_1010=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + local tmp1:8 = SIMD_PIECE(Re_VPR128.D, vIndex:1); + Rd_VPR128.2D = NEON_fmulx(Rn_VPR128.2D, tmp1, 8:1); +} + +# C7.2.137 FMULX (by element) page C7-2328 line 136175 MATCH x2f809000/mask=xbf80f400 +# CONSTRUCT x2f809000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@4 +# AUNIT --inst x2f809000/mask=xffc0f400 --rand sfp --status fail --comment "nofpround" + +:fmulx Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex +is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x9 & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp1:4 = Re_VPR128.S.vIndex; + # simd infix Rd_VPR64.2S = Rn_VPR64.2S f* tmp1 on lane size 4 + Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] f* tmp1; + Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] f* tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.137 FMULX (by element) page C7-2328 line 136175 MATCH x2f809000/mask=xbf80f400 +# CONSTRUCT x6f809000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@4 +# AUNIT --inst x6f809000/mask=xffc0f400 --rand sfp --status nopcodeop --comment "nofpround" + +:fmulx Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex +is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x9 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + local tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1); + Rd_VPR128.4S = NEON_fmulx(Rn_VPR128.4S, tmp1, 4:1); +} + +# C7.2.137 FMULX (by element) page C7-2328 line 136175 MATCH x7f009000/mask=xffc0f400 +# CONSTRUCT x7f009000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =f* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@2 +# AUNIT --inst x7f009000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround" +# Scalar, half-precision variant + +:fmulx Rd_FPR16, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM +is b_2231=0b0111111100 & b_1215=0b1001 & b_10=0 & Rd_FPR16 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd +{ + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp1:2 = Re_VPR128Lo.H.vIndexHLM; + Rd_FPR16 = Rn_FPR16 f* tmp1; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.137 FMULX (by element) page C7-2328 line 136175 MATCH x7f809000/mask=xff80f400 +# CONSTRUCT x7f809000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =f* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@4 +# AUNIT --inst x7f809000/mask=xffc0f400 --rand sfp --status pass --comment "nofpround" +# Scalar, single-precision and double-precision variant when sz=0 Ts=S V=32 + +:fmulx Rd_FPR32, Rn_FPR32, Re_VPR128.S.vIndex +is b_2331=0b011111111 & b_22=0 & b_1215=0b1001 & b_10=0 & Rd_FPR32 & Rn_FPR32 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Zd +{ + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp1:4 = Re_VPR128.S.vIndex; + Rd_FPR32 = Rn_FPR32 f* tmp1; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.137 FMULX (by element) page C7-2328 line 136175 MATCH x7f809000/mask=xff80f400 +# CONSTRUCT x7fc09000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =f* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@8 +# AUNIT --inst x7fc09000/mask=xffe0f400 --rand dfp --status pass --comment "nofpround" +# Scalar, single-precision and double-precision variant when sz=1 Ts=D V=64 + +:fmulx Rd_FPR64, Rn_FPR64, Re_VPR128.D.vIndex +is b_2331=0b011111111 & b_22=1 & b_21=0 & b_1215=0b1001 & b_10=0 & Rd_FPR64 & Rn_FPR64 & Re_VPR128.D.vIndex & Re_VPR128.D & vIndex & Zd +{ + # simd element Re_VPR128.D[vIndex] lane size 8 + local tmp1:8 = Re_VPR128.D.vIndex; + Rd_FPR64 = Rn_FPR64 f* tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.137 FMULX (by element) page C7-2328 line 136175 MATCH x2f009000/mask=xbfc0f400 +# CONSTRUCT x2f009000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f*@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@2 +# AUNIT --inst x2f009000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround" +# Vector, half-precision variant when Q = 0 suf=64.4H + +:fmulx Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM +is b_31=0 & b_30=0 & b_2229=0b10111100 & b_1215=0b1001 & b_10=0 & Rd_VPR64.4H & Rn_VPR64.4H & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd +{ + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp1:2 = Re_VPR128Lo.H.vIndexHLM; + # simd infix Rd_VPR64.4H = Rn_VPR64.4H f* tmp1 on lane size 2 + Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f* tmp1; + Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f* tmp1; + Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f* tmp1; + Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f* tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.137 FMULX (by element) page C7-2328 line 136175 MATCH x2f009000/mask=xbfc0f400 +# CONSTRUCT x6f009000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f*@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@2 +# AUNIT --inst x6f009000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround" +# Vector, half-precision variant when Q = 1 suf=128.8H + +:fmulx Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM +is b_31=0 & b_30=1 & b_2229=0b10111100 & b_1215=0b1001 & b_10=0 & Rd_VPR128.8H & Rn_VPR128.8H & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd +{ + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp1:2 = Re_VPR128Lo.H.vIndexHLM; + # simd infix Rd_VPR128.8H = Rn_VPR128.8H f* tmp1 on lane size 2 + Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f* tmp1; + Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f* tmp1; + Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f* tmp1; + Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f* tmp1; + Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f* tmp1; + Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f* tmp1; + Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f* tmp1; + Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f* tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.138 FMULX page C7-2332 line 136418 MATCH x5e20dc00/mask=xffa0fc00 +# CONSTRUCT x5e60dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2 +# AUNIT --inst x5e60dc00/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround" + +:fmulx Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_3031=1 & u=0 & b_2428=0x1e & size_high=0 & b_2122=3 & Rm_FPR64 & b_1115=0x1b & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_fmulx(Rn_FPR64, Rm_FPR64); +} + +# C7.2.138 FMULX page C7-2332 line 136418 MATCH x5e20dc00/mask=xffa0fc00 +# CONSTRUCT x5e20dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2 +# AUNIT --inst x5e20dc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fmulx Rd_FPR32, Rn_FPR32, Rm_FPR32 +is b_3031=1 & u=0 & b_2428=0x1e & size_high=0 & b_2122=1 & Rm_FPR32 & b_1115=0x1b & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_fmulx(Rn_FPR32, Rm_FPR32); +} + +# C7.2.138 FMULX page C7-2332 line 136418 MATCH x0e20dc00/mask=xbfa0fc00 +# CONSTRUCT x4e60dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@8 +# AUNIT --inst x4e60dc00/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround" + +:fmulx Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1b & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_fmulx(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.138 FMULX page C7-2332 line 136418 MATCH x0e20dc00/mask=xbfa0fc00 +# CONSTRUCT x0e20dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@4 +# AUNIT --inst x0e20dc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fmulx Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1b & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_fmulx(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.138 FMULX page C7-2332 line 136418 MATCH x0e20dc00/mask=xbfa0fc00 +# CONSTRUCT x4e20dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@4 +# AUNIT --inst x4e20dc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:fmulx Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1b & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_fmulx(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.138 FMULX page C7-2332 line 136418 MATCH x5e401c00/mask=xffe0fc00 +# CONSTRUCT x5e401c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =f* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2 +# AUNIT --inst x5e401c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Scalar half precision variant + +:fmulx Rd_FPR16, Rn_FPR16, Rm_FPR16 +is b_2131=0b01011110010 & b_1015=0b000111 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd +{ + Rd_FPR16 = Rn_FPR16 f* Rm_FPR16; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.138 FMULX page C7-2332 line 136418 MATCH x0e401c00/mask=xbfe0fc00 +# CONSTRUCT x0e401c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f*@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@2 +# AUNIT --inst x0e401c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Vector half precision variant when Q=0 suf=64.4H + +:fmulx Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b000111 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + # simd infix Rd_VPR64.4H = Rn_VPR64.4H f* Rm_VPR64.4H on lane size 2 + Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f* Rm_VPR64.4H[0,16]; + Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f* Rm_VPR64.4H[16,16]; + Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f* Rm_VPR64.4H[32,16]; + Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f* Rm_VPR64.4H[48,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.138 FMULX page C7-2332 line 136418 MATCH x0e401c00/mask=xbfe0fc00 +# CONSTRUCT x4e401c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f*@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@2 +# AUNIT --inst x4e401c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Vector half precision variant when Q=1 suf=128.8H + +:fmulx Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b000111 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + # simd infix Rd_VPR128.8H = Rn_VPR128.8H f* Rm_VPR128.8H on lane size 2 + Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f* Rm_VPR128.8H[0,16]; + Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f* Rm_VPR128.8H[16,16]; + Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f* Rm_VPR128.8H[32,16]; + Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f* Rm_VPR128.8H[48,16]; + Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f* Rm_VPR128.8H[64,16]; + Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f* Rm_VPR128.8H[80,16]; + Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f* Rm_VPR128.8H[96,16]; + Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f* Rm_VPR128.8H[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.139 FNEG (vector) page C7-2335 line 136615 MATCH x2ea0f800/mask=xbfbffc00 +# CONSTRUCT x6ee0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$fneg@8 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1@8 +# AUNIT --inst x6ee0f800/mask=xfffffc00 --rand dfp --status pass + +:fneg Rd_VPR128.2D, Rn_VPR128.2D +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0xf & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + # simd unary Rd_VPR128.2D = f-(Rn_VPR128.2D) on lane size 8 + Rd_VPR128.2D[0,64] = f-(Rn_VPR128.2D[0,64]); + Rd_VPR128.2D[64,64] = f-(Rn_VPR128.2D[64,64]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.139 FNEG (vector) page C7-2335 line 136615 MATCH x2ea0f800/mask=xbfbffc00 +# CONSTRUCT x2ea0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$fneg@4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1@4 +# AUNIT --inst x2ea0f800/mask=xfffffc00 --rand sfp --status pass + +:fneg Rd_VPR64.2S, Rn_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xf & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + # simd unary Rd_VPR64.2S = f-(Rn_VPR64.2S) on lane size 4 + Rd_VPR64.2S[0,32] = f-(Rn_VPR64.2S[0,32]); + Rd_VPR64.2S[32,32] = f-(Rn_VPR64.2S[32,32]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.139 FNEG (vector) page C7-2335 line 136615 MATCH x2ea0f800/mask=xbfbffc00 +# CONSTRUCT x6ea0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$fneg@4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1@4 +# AUNIT --inst x6ea0f800/mask=xfffffc00 --rand sfp --status pass + +:fneg Rd_VPR128.4S, Rn_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xf & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd unary Rd_VPR128.4S = f-(Rn_VPR128.4S) on lane size 4 + Rd_VPR128.4S[0,32] = f-(Rn_VPR128.4S[0,32]); + Rd_VPR128.4S[32,32] = f-(Rn_VPR128.4S[32,32]); + Rd_VPR128.4S[64,32] = f-(Rn_VPR128.4S[64,32]); + Rd_VPR128.4S[96,32] = f-(Rn_VPR128.4S[96,32]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.139 FNEG (vector) page C7-2335 line 136615 MATCH x2ef8f800/mask=xbffffc00 +# CONSTRUCT x2ef8f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$fneg@2 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1@2 +# AUNIT --inst x2ef8f800/mask=xfffffc00 --rand hfp --status noqemu +# Half-precision variant when Q=0 suf=64.4H + +:fneg Rd_VPR64.4H, Rn_VPR64.4H +is b_31=0 & b_30=0 & b_1029=0b10111011111000111110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd +{ + # simd unary Rd_VPR64.4H = f-(Rn_VPR64.4H) on lane size 2 + Rd_VPR64.4H[0,16] = f-(Rn_VPR64.4H[0,16]); + Rd_VPR64.4H[16,16] = f-(Rn_VPR64.4H[16,16]); + Rd_VPR64.4H[32,16] = f-(Rn_VPR64.4H[32,16]); + Rd_VPR64.4H[48,16] = f-(Rn_VPR64.4H[48,16]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.139 FNEG (vector) page C7-2335 line 136615 MATCH x2ef8f800/mask=xbffffc00 +# CONSTRUCT x6ef8f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$fneg@2 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1@2 +# AUNIT --inst x6ef8f800/mask=xfffffc00 --rand hfp --status noqemu +# Half-precision variant when Q=1 suf=128.8H + +:fneg Rd_VPR128.8H, Rn_VPR128.8H +is b_31=0 & b_30=1 & b_1029=0b10111011111000111110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd +{ + # simd unary Rd_VPR128.8H = f-(Rn_VPR128.8H) on lane size 2 + Rd_VPR128.8H[0,16] = f-(Rn_VPR128.8H[0,16]); + Rd_VPR128.8H[16,16] = f-(Rn_VPR128.8H[16,16]); + Rd_VPR128.8H[32,16] = f-(Rn_VPR128.8H[32,16]); + Rd_VPR128.8H[48,16] = f-(Rn_VPR128.8H[48,16]); + Rd_VPR128.8H[64,16] = f-(Rn_VPR128.8H[64,16]); + Rd_VPR128.8H[80,16] = f-(Rn_VPR128.8H[80,16]); + Rd_VPR128.8H[96,16] = f-(Rn_VPR128.8H[96,16]); + Rd_VPR128.8H[112,16] = f-(Rn_VPR128.8H[112,16]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.140 FNEG (scalar) page C7-2337 line 136726 MATCH x1e214000/mask=xff3ffc00 +# CONSTRUCT x1e614000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =fneg +# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1 +# AUNIT --inst x1e614000/mask=xfffffc00 --rand dfp --status pass + +:fneg Rd_FPR64, Rn_FPR64 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & fpDpOpcode=0x2 & b_1014=0x10 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = f- Rn_FPR64; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.140 FNEG (scalar) page C7-2337 line 136726 MATCH x1e214000/mask=xff3ffc00 +# CONSTRUCT x1e214000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =fneg +# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1 +# AUNIT --inst x1e214000/mask=xfffffc00 --rand sfp --status pass + +:fneg Rd_FPR32, Rn_FPR32 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & fpDpOpcode=0x2 & b_1014=0x10 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = f- Rn_FPR32; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.140 FNEG (scalar) page C7-2337 line 136726 MATCH x1e214000/mask=xff3ffc00 +# CONSTRUCT x1ee14000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =fneg +# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1 +# AUNIT --inst x1ee14000/mask=xfffffc00 --rand hfp --status noqemu + +:fneg Rd_FPR16, Rn_FPR16 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & fpDpOpcode=0x2 & b_1014=0x10 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = f- Rn_FPR16; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.141 FNMADD page C7-2339 line 136822 MATCH x1f200000/mask=xff208000 +# CONSTRUCT x1f600000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 fneg =NEON_fnmadd/3 +# AUNIT --inst x1f600000/mask=xffe08000 --rand dfp --status nopcodeop --comment "nofpround" + +:fnmadd Rd_FPR64, Rn_FPR64, Rm_FPR64, Ra_FPR64 +is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=1 & b_21=1 & Rm_FPR64 & b_15=0 & Ra_FPR64 & Rn_FPR64 & Rd_FPR64 & Zd +{ + local tmp1:8 = f- Ra_FPR64; + Rd_FPR64 = NEON_fnmadd(Rn_FPR64, Rm_FPR64, tmp1); +} + +# C7.2.141 FNMADD page C7-2339 line 136822 MATCH x1f200000/mask=xff208000 +# CONSTRUCT x1f200000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 fneg =NEON_fnmadd/3 +# AUNIT --inst x1f200000/mask=xffe08000 --rand sfp --status nopcodeop --comment "nofpround" + +:fnmadd Rd_FPR32, Rn_FPR32, Rm_FPR32, Ra_FPR32 +is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=0 & b_21=1 & Rm_FPR32 & b_15=0 & Ra_FPR32 & Rn_FPR32 & Rd_FPR32 & Zd +{ + local tmp1:4 = f- Ra_FPR32; + Rd_FPR32 = NEON_fnmadd(Rn_FPR32, Rm_FPR32, tmp1); +} + +# C7.2.141 FNMADD page C7-2339 line 136822 MATCH x1f200000/mask=xff208000 +# CONSTRUCT x1fe00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 fneg =NEON_fnmadd/3 +# AUNIT --inst x1fe00000/mask=xffe08000 --rand hfp --status noqemu --comment "nofpround" + +:fnmadd Rd_FPR16, Rn_FPR16, Rm_FPR16, Ra_FPR16 +is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=3 & b_21=1 & Rm_FPR16 & b_15=0 & Ra_FPR16 & Rn_FPR16 & Rd_FPR16 & Zd +{ + local tmp1:2 = f- Ra_FPR16; + Rd_FPR16 = NEON_fnmadd(Rn_FPR16, Rm_FPR16, tmp1); +} + +# C7.2.142 FNMSUB page C7-2341 line 136952 MATCH x1f208000/mask=xff208000 +# CONSTRUCT x1f608000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fnmsub/3 +# AUNIT --inst x1f608000/mask=xffe08000 --rand dfp --status nopcodeop --comment "nofpround" + +:fnmsub Rd_FPR64, Rn_FPR64, Rm_FPR64, Ra_FPR64 +is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=1 & b_21=1 & Rm_FPR64 & b_15=1 & Ra_FPR64 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_fnmsub(Rn_FPR64, Rm_FPR64, Ra_FPR64); +} + +# C7.2.142 FNMSUB page C7-2341 line 136952 MATCH x1f208000/mask=xff208000 +# CONSTRUCT x1f208000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fnmsub/3 +# AUNIT --inst x1f208000/mask=xffe08000 --rand sfp --status nopcodeop --comment "nofpround" + +:fnmsub Rd_FPR32, Rn_FPR32, Rm_FPR32, Ra_FPR32 +is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=0 & b_21=1 & Rm_FPR32 & b_15=1 & Ra_FPR32 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_fnmsub(Rn_FPR32, Rm_FPR32, Ra_FPR32); +} + +# C7.2.142 FNMSUB page C7-2341 line 136952 MATCH x1f208000/mask=xff208000 +# CONSTRUCT x1fe08000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fnmsub/3 +# AUNIT --inst x1fe08000/mask=xffe08000 --rand hfp --status noqemu --comment "nofpround" + +:fnmsub Rd_FPR16, Rn_FPR16, Rm_FPR16, Ra_FPR16 +is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=3 & b_21=1 & Rm_FPR16 & b_15=1 & Ra_FPR16 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_fnmsub(Rn_FPR16, Rm_FPR16, Ra_FPR16); +} + +# C7.2.143 FNMUL (scalar) page C7-2343 line 137081 MATCH x1e208800/mask=xff20fc00 +# CONSTRUCT x1e608800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 f* =fneg +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fnmul/2 +# AUNIT --inst x1e608800/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround" + +:fnmul Rd_FPR64, Rn_FPR64, Rm_FPR64 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x8 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd +{ + local tmp1:8 = Rn_FPR64 f* Rm_FPR64; + Rd_FPR64 = f- tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.143 FNMUL (scalar) page C7-2343 line 137081 MATCH x1e208800/mask=xff20fc00 +# CONSTRUCT x1e208800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 f* =fneg +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fnmul/2 +# AUNIT --inst x1e208800/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround" + +:fnmul Rd_FPR32, Rn_FPR32, Rm_FPR32 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x8 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd +{ + local tmp1:4 = Rn_FPR32 f* Rm_FPR32; + Rd_FPR32 = f- tmp1; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.143 FNMUL (scalar) page C7-2343 line 137081 MATCH x1e208800/mask=xff20fc00 +# CONSTRUCT x1ee08800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 f* =fneg +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fnmul/2 +# AUNIT --inst x1ee08800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" + +:fnmul Rd_FPR16, Rn_FPR16, Rm_FPR16 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x8 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd +{ + local tmp1:2 = Rn_FPR16 f* Rm_FPR16; + Rd_FPR16 = f- tmp1; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.144 FRECPE page C7-2345 line 137191 MATCH x0ea1d800/mask=xbfbffc00 +# CONSTRUCT x4ee1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1@8 +# AUNIT --inst x4ee1d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround" + +:frecpe Rd_VPR128.2D, Rn_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & size_high=1 & b_1722=0x30 & b_1216=0x1d & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_frecpe(Rn_VPR128.2D, 8:1); +} + +# C7.2.144 FRECPE page C7-2345 line 137191 MATCH x0ea1d800/mask=xbfbffc00 +# CONSTRUCT x0ea1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1@4 +# AUNIT --inst x0ea1d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround" + +:frecpe Rd_VPR64.2S, Rn_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & size_high=1 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_frecpe(Rn_VPR64.2S, 4:1); +} + +# C7.2.144 FRECPE page C7-2345 line 137191 MATCH x0ea1d800/mask=xbfbffc00 +# CONSTRUCT x4ea1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1@4 +# AUNIT --inst x4ea1d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround" + +:frecpe Rd_VPR128.4S, Rn_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & size_high=1 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_frecpe(Rn_VPR128.4S, 4:1); +} + +# C7.2.144 FRECPE page C7-2345 line 137191 MATCH x5ea1d800/mask=xffbffc00 +# CONSTRUCT x5ee1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1 +# AUNIT --inst x5ee1d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround" + +:frecpe Rd_FPR64, Rn_FPR64 +is b_3031=1 & u=0 & b_2428=0x1e & size_high=1 & b_1722=0x30 & b_1216=0x1d & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_frecpe(Rn_FPR64); +} + +# C7.2.144 FRECPE page C7-2345 line 137191 MATCH x5ea1d800/mask=xffbffc00 +# CONSTRUCT x5ea1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1 +# AUNIT --inst x5ea1d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround" + +:frecpe Rd_FPR32, Rn_FPR32 +is b_3031=1 & u=0 & b_2428=0x1e & size_high=1 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_frecpe(Rn_FPR32); +} + +# C7.2.144 FRECPE page C7-2345 line 137191 MATCH x5ef9d800/mask=xfffffc00 +# CONSTRUCT x5ef9d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1 +# AUNIT --inst x5ef9d800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# Scalar half precision variant + +:frecpe Rd_FPR16, Rn_FPR16 +is b_1031=0b0101111011111001110110 & Rd_FPR16 & Rn_FPR16 & Zd +{ + Rd_FPR16 = NEON_frecpe(Rn_FPR16); +} + +# C7.2.144 FRECPE page C7-2345 line 137191 MATCH x0ef9d800/mask=xbffffc00 +# CONSTRUCT x0ef9d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1@2 +# AUNIT --inst x0ef9d800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# Vector half precision variant when Q=0 suf=64.4H + +:frecpe Rd_VPR64.4H, Rn_VPR64.4H +is b_31=0 & b_30=0 & b_1029=0b00111011111001110110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_frecpe(Rn_VPR64.4H, 2:1); +} + +# C7.2.144 FRECPE page C7-2345 line 137191 MATCH x0ef9d800/mask=xbffffc00 +# CONSTRUCT x4ef9d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1@2 +# AUNIT --inst x4ef9d800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# Vector half precision variant when Q=1 suf=128.8H + +:frecpe Rd_VPR128.8H, Rn_VPR128.8H +is b_31=0 & b_30=1 & b_1029=0b00111011111001110110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_frecpe(Rn_VPR128.8H, 2:1); +} + +# C7.2.145 FRECPS page C7-2348 line 137379 MATCH x5e20fc00/mask=xffa0fc00 +# CONSTRUCT x5e60fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2 +# AUNIT --inst x5e60fc00/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround" + +:frecps Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_3031=1 & u=0 & b_2428=0x1e & size_high=0 & b_2122=3 & Rm_FPR64 & b_1115=0x1f & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_frecps(Rn_FPR64, Rm_FPR64); +} + +# C7.2.145 FRECPS page C7-2348 line 137379 MATCH x5e20fc00/mask=xffa0fc00 +# CONSTRUCT x5e20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2 +# AUNIT --inst x5e20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:frecps Rd_FPR32, Rn_FPR32, Rm_FPR32 +is b_3031=1 & u=0 & b_2428=0x1e & size_high=0 & b_2122=1 & Rm_FPR32 & b_1115=0x1f & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_frecps(Rn_FPR32, Rm_FPR32); +} + +# C7.2.145 FRECPS page C7-2348 line 137379 MATCH x0e20fc00/mask=xbfa0fc00 +# CONSTRUCT x4e60fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2@8 +# AUNIT --inst x4e60fc00/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround" + +:frecps Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1f & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_frecps(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.145 FRECPS page C7-2348 line 137379 MATCH x0e20fc00/mask=xbfa0fc00 +# CONSTRUCT x0e20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2@4 +# AUNIT --inst x0e20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:frecps Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1f & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_frecps(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.145 FRECPS page C7-2348 line 137379 MATCH x0e20fc00/mask=xbfa0fc00 +# CONSTRUCT x4e20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2@4 +# AUNIT --inst x4e20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" + +:frecps Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1f & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_frecps(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.145 FRECPS page C7-2348 line 137379 MATCH x5e403c00/mask=xffe0fc00 +# CONSTRUCT x5e403c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2 +# AUNIT --inst x5e403c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Scalar half precision variant + +:frecps Rd_FPR16, Rn_FPR16, Rm_FPR16 +is b_2131=0b01011110010 & b_1015=0b001111 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd +{ + Rd_FPR16 = NEON_frecps(Rn_FPR16, Rm_FPR16); +} + +# C7.2.145 FRECPS page C7-2348 line 137379 MATCH x0e403c00/mask=xbfe0fc00 +# CONSTRUCT x0e403c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2@2 +# AUNIT --inst x0e403c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Vector half precision variant when Q=0 suf=64.4H + +:frecps Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b001111 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_frecps(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.145 FRECPS page C7-2348 line 137379 MATCH x0e403c00/mask=xbfe0fc00 +# CONSTRUCT x4e403c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2@2 +# AUNIT --inst x4e403c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Vector half precision variant when Q=1 suf=128.8H + +:frecps Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b001111 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_frecps(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.146 FRECPX page C7-2351 line 137576 MATCH x5ef9f800/mask=xfffffc00 +# CONSTRUCT x5ef9f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpx/1 +# AUNIT --inst x5ef9f800/mask=xfffffc00 --rand hfp --status noqemu +# Half-precision variant + +:frecpx Rd_FPR16, Rn_FPR16 +is b_1031=0b0101111011111001111110 & Rd_FPR16 & Rn_FPR16 & Zd +{ + Rd_FPR16 = NEON_frecpx(Rn_FPR16); +} + +# C7.2.146 FRECPX page C7-2351 line 137576 MATCH x5ea1f800/mask=xffbffc00 +# CONSTRUCT x5ea1f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpx/1 +# AUNIT --inst x5ea1f800/mask=xfffffc00 --rand sfp --status nopcodeop +# Single-precision and double-precision variant when sz=0 suf=32 + +:frecpx Rd_FPR32, Rn_FPR32 +is b_2331=0b010111101 & b_22=0 & b_1021=0b100001111110 & Rd_FPR32 & Rn_FPR32 & Zd +{ + Rd_FPR32 = NEON_frecpx(Rn_FPR32); +} + +# C7.2.146 FRECPX page C7-2351 line 137576 MATCH x5ea1f800/mask=xffbffc00 +# CONSTRUCT x5ee1f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpx/1 +# AUNIT --inst x5ee1f800/mask=xfffffc00 --rand dfp --status nopcodeop +# Single-precision and double-precision variant when sz=1 suf=64 + +:frecpx Rd_FPR64, Rn_FPR64 +is b_2331=0b010111101 & b_22=1 & b_1021=0b100001111110 & Rd_FPR64 & Rn_FPR64 & Zd +{ + Rd_FPR64 = NEON_frecpx(Rn_FPR64); +} + +# C7.2.140 FRINTA (vector) page C7-1313 line 76386 KEEPWITH + +frint_vmode: "a" is b_29=1 & b_23=0 & b_12=0 { } +frint_vmode: "i" is b_29=1 & b_23=1 & b_12=1 { } +frint_vmode: "m" is b_29=0 & b_23=0 & b_12=1 { } +frint_vmode: "n" is b_29=0 & b_23=0 & b_12=0 { } +frint_vmode: "p" is b_29=0 & b_23=1 & b_12=0 { } +frint_vmode: "x" is b_29=1 & b_23=0 & b_12=1 { } +frint_vmode: "z" is b_29=0 & b_23=1 & b_12=1 { } + +# C7.2.155 FRINTA (vector) page C7-2369 line 138408 MATCH x2e798800/mask=xbffffc00 +# C7.2.157 FRINTI (vector) page C7-2373 line 138642 MATCH x2ef99800/mask=xbffffc00 +# C7.2.159 FRINTM (vector) page C7-2377 line 138880 MATCH x0e799800/mask=xbffffc00 +# C7.2.161 FRINTN (vector) page C7-2381 line 139118 MATCH x0e798800/mask=xbffffc00 +# C7.2.163 FRINTP (vector) page C7-2385 line 139356 MATCH x0ef98800/mask=xbffffc00 +# C7.2.165 FRINTX (vector) page C7-2389 line 139594 MATCH x2e799800/mask=xbffffc00 +# C7.2.167 FRINTZ (vector) page C7-2393 line 139833 MATCH x0ef99800/mask=xbffffc00 +# CONSTRUCT x0e798800/mask=xdf7fec00 MATCHED 7 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$trunc@2 +# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1@2 +# AUNIT --inst x0e798800/mask=xdf7fec00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant when Q=0 suf=64.4H + +:frint^frint_vmode Rd_VPR64.4H, Rn_VPR64.4H +is b_31=0 & b_30=0 & b_29 & b_2428=0b01110 & b_23 & b_1322=0b1111001100 & b_12 & b_1011=0b10 & frint_vmode & Rd_VPR64.4H & Rn_VPR64.4H & Zd +{ + # simd unary Rd_VPR64.4H = trunc(Rn_VPR64.4H) on lane size 2 + Rd_VPR64.4H[0,16] = trunc(Rn_VPR64.4H[0,16]); + Rd_VPR64.4H[16,16] = trunc(Rn_VPR64.4H[16,16]); + Rd_VPR64.4H[32,16] = trunc(Rn_VPR64.4H[32,16]); + Rd_VPR64.4H[48,16] = trunc(Rn_VPR64.4H[48,16]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.155 FRINTA (vector) page C7-2369 line 138408 MATCH x2e798800/mask=xbffffc00 +# C7.2.157 FRINTI (vector) page C7-2373 line 138642 MATCH x2ef99800/mask=xbffffc00 +# C7.2.159 FRINTM (vector) page C7-2377 line 138880 MATCH x0e799800/mask=xbffffc00 +# C7.2.161 FRINTN (vector) page C7-2381 line 139118 MATCH x0e798800/mask=xbffffc00 +# C7.2.163 FRINTP (vector) page C7-2385 line 139356 MATCH x0ef98800/mask=xbffffc00 +# C7.2.165 FRINTX (vector) page C7-2389 line 139594 MATCH x2e799800/mask=xbffffc00 +# C7.2.167 FRINTZ (vector) page C7-2393 line 139833 MATCH x0ef99800/mask=xbffffc00 +# CONSTRUCT x4e798800/mask=xdf7fec00 MATCHED 7 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$trunc@2 +# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1@2 +# AUNIT --inst x4e798800/mask=xdf7fec00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant when Q=1 suf=128.8H + +:frint^frint_vmode Rd_VPR128.8H, Rn_VPR128.8H +is b_31=0 & b_30=1 & b_29 & b_2428=0b01110 & b_23 & b_1322=0b1111001100 & b_12 & b_1011=0b10 & frint_vmode & Rd_VPR128.8H & Rn_VPR128.8H & Zd +{ + # simd unary Rd_VPR128.8H = trunc(Rn_VPR128.8H) on lane size 2 + Rd_VPR128.8H[0,16] = trunc(Rn_VPR128.8H[0,16]); + Rd_VPR128.8H[16,16] = trunc(Rn_VPR128.8H[16,16]); + Rd_VPR128.8H[32,16] = trunc(Rn_VPR128.8H[32,16]); + Rd_VPR128.8H[48,16] = trunc(Rn_VPR128.8H[48,16]); + Rd_VPR128.8H[64,16] = trunc(Rn_VPR128.8H[64,16]); + Rd_VPR128.8H[80,16] = trunc(Rn_VPR128.8H[80,16]); + Rd_VPR128.8H[96,16] = trunc(Rn_VPR128.8H[96,16]); + Rd_VPR128.8H[112,16] = trunc(Rn_VPR128.8H[112,16]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.155 FRINTA (vector) page C7-2369 line 138408 MATCH x2e218800/mask=xbfbffc00 +# C7.2.157 FRINTI (vector) page C7-2373 line 138642 MATCH x2ea19800/mask=xbfbffc00 +# C7.2.159 FRINTM (vector) page C7-2377 line 138880 MATCH x0e219800/mask=xbfbffc00 +# C7.2.161 FRINTN (vector) page C7-2381 line 139118 MATCH x0e218800/mask=xbfbffc00 +# C7.2.163 FRINTP (vector) page C7-2385 line 139356 MATCH x0ea18800/mask=xbfbffc00 +# C7.2.165 FRINTX (vector) page C7-2389 line 139594 MATCH x2e219800/mask=xbfbffc00 +# C7.2.167 FRINTZ (vector) page C7-2393 line 139833 MATCH x0ea19800/mask=xbfbffc00 +# CONSTRUCT x0e218800/mask=xdf7fec00 MATCHED 7 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$trunc@4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1@4 +# AUNIT --inst x0e218800/mask=xdf7fec00 --rand sfp --status fail --comment "nofpround" +# Single-precision and double-precision variant when sz=0 Q=0 suf=64.2S + +:frint^frint_vmode Rd_VPR64.2S, Rn_VPR64.2S +is b_31=0 & b_30=0 & b_29 & b_2428=0b01110 & b_23 & b_22=0b0 & b_1321=0b100001100 & b_12 & b_1011=0b10 & frint_vmode & Rd_VPR64.2S & Rn_VPR64.2S & Zd +{ + # simd unary Rd_VPR64.2S = trunc(Rn_VPR64.2S) on lane size 4 + Rd_VPR64.2S[0,32] = trunc(Rn_VPR64.2S[0,32]); + Rd_VPR64.2S[32,32] = trunc(Rn_VPR64.2S[32,32]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.155 FRINTA (vector) page C7-2369 line 138408 MATCH x2e218800/mask=xbfbffc00 +# C7.2.157 FRINTI (vector) page C7-2373 line 138642 MATCH x2ea19800/mask=xbfbffc00 +# C7.2.159 FRINTM (vector) page C7-2377 line 138880 MATCH x0e219800/mask=xbfbffc00 +# C7.2.161 FRINTN (vector) page C7-2381 line 139118 MATCH x0e218800/mask=xbfbffc00 +# C7.2.163 FRINTP (vector) page C7-2385 line 139356 MATCH x0ea18800/mask=xbfbffc00 +# C7.2.165 FRINTX (vector) page C7-2389 line 139594 MATCH x2e219800/mask=xbfbffc00 +# C7.2.167 FRINTZ (vector) page C7-2393 line 139833 MATCH x0ea19800/mask=xbfbffc00 +# CONSTRUCT x4e218800/mask=xdf7fec00 MATCHED 7 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$trunc@4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1@4 +# AUNIT --inst x4e218800/mask=xdf7fec00 --rand sfp --status fail --comment "nofpround" +# Single-precision and double-precision variant when sz=0 Q=1 suf=128.4S + +:frint^frint_vmode Rd_VPR128.4S, Rn_VPR128.4S +is b_31=0 & b_30=1 & b_29 & b_2428=0b01110 & b_23 & b_22=0b0 & b_1321=0b100001100 & b_12 & b_1011=0b10 & frint_vmode & Rd_VPR128.4S & Rn_VPR128.4S & Zd +{ + # simd unary Rd_VPR128.4S = trunc(Rn_VPR128.4S) on lane size 4 + Rd_VPR128.4S[0,32] = trunc(Rn_VPR128.4S[0,32]); + Rd_VPR128.4S[32,32] = trunc(Rn_VPR128.4S[32,32]); + Rd_VPR128.4S[64,32] = trunc(Rn_VPR128.4S[64,32]); + Rd_VPR128.4S[96,32] = trunc(Rn_VPR128.4S[96,32]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.155 FRINTA (vector) page C7-2369 line 138408 MATCH x2e218800/mask=xbfbffc00 +# C7.2.157 FRINTI (vector) page C7-2373 line 138642 MATCH x2ea19800/mask=xbfbffc00 +# C7.2.159 FRINTM (vector) page C7-2377 line 138880 MATCH x0e219800/mask=xbfbffc00 +# C7.2.161 FRINTN (vector) page C7-2381 line 139118 MATCH x0e218800/mask=xbfbffc00 +# C7.2.163 FRINTP (vector) page C7-2385 line 139356 MATCH x0ea18800/mask=xbfbffc00 +# C7.2.165 FRINTX (vector) page C7-2389 line 139594 MATCH x2e219800/mask=xbfbffc00 +# C7.2.167 FRINTZ (vector) page C7-2393 line 139833 MATCH x0ea19800/mask=xbfbffc00 +# CONSTRUCT x4e618800/mask=xdf7fec00 MATCHED 7 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$trunc@8 +# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1@8 +# AUNIT --inst x4e618800/mask=xdf7fec00 --rand dfp --status fail --comment "nofpround" +# Single-precision and double-precision variant when sz=1 Q=1 suf=128.2D + +:frint^frint_vmode Rd_VPR128.2D, Rn_VPR128.2D +is b_31=0 & b_30=1 & b_29 & b_2428=0b01110 & b_23 & b_22=0b1 & b_1321=0b100001100 & b_12 & b_1011=0b10 & frint_vmode & Rd_VPR128.2D & Rn_VPR128.2D & Zd +{ + # simd unary Rd_VPR128.2D = trunc(Rn_VPR128.2D) on lane size 8 + Rd_VPR128.2D[0,64] = trunc(Rn_VPR128.2D[0,64]); + Rd_VPR128.2D[64,64] = trunc(Rn_VPR128.2D[64,64]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.141 FRINTA (scalar) page C7-1315 line 76515 KEEPWITH +# FP rounding instruction (not implemented) + +frint_smode: "a" is b_1517=0b100 { } +frint_smode: "i" is b_1517=0b111 { } +frint_smode: "m" is b_1517=0b010 { } +frint_smode: "n" is b_1517=0b000 { } +frint_smode: "p" is b_1517=0b001 { } +frint_smode: "x" is b_1517=0b110 { } +frint_smode: "z" is b_1517=0b011 { } + +# C7.2.156 FRINTA (scalar) page C7-2371 line 138539 MATCH x1e264000/mask=xff3ffc00 +# C7.2.158 FRINTI (scalar) page C7-2375 line 138773 MATCH x1e27c000/mask=xff3ffc00 +# C7.2.160 FRINTM (scalar) page C7-2379 line 139011 MATCH x1e254000/mask=xff3ffc00 +# C7.2.162 FRINTN (scalar) page C7-2383 line 139249 MATCH x1e244000/mask=xff3ffc00 +# C7.2.164 FRINTP (scalar) page C7-2387 line 139487 MATCH x1e24c000/mask=xff3ffc00 +# C7.2.166 FRINTX (scalar) page C7-2391 line 139726 MATCH x1e274000/mask=xff3ffc00 +# C7.2.168 FRINTZ (scalar) page C7-2395 line 139964 MATCH x1e25c000/mask=xff3ffc00 +# CONSTRUCT x1ee44000/mask=xfffc7c00 MATCHED 7 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =trunc +# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1 +# AUNIT --inst x1ee44000/mask=xfffc7c00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant when type = 11 suf=16 + +:frint^frint_smode Rd_FPR16, Rn_FPR16 +is b_2431=0b00011110 & b_2223=0b11 & b_1821=0b1001 & b_1517 & b_1014=0b10000 & frint_smode & Rd_FPR16 & Rn_FPR16 & Zd +{ + Rd_FPR16 = trunc(Rn_FPR16); + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.156 FRINTA (scalar) page C7-2371 line 138539 MATCH x1e264000/mask=xff3ffc00 +# C7.2.158 FRINTI (scalar) page C7-2375 line 138773 MATCH x1e27c000/mask=xff3ffc00 +# C7.2.160 FRINTM (scalar) page C7-2379 line 139011 MATCH x1e254000/mask=xff3ffc00 +# C7.2.162 FRINTN (scalar) page C7-2383 line 139249 MATCH x1e244000/mask=xff3ffc00 +# C7.2.164 FRINTP (scalar) page C7-2387 line 139487 MATCH x1e24c000/mask=xff3ffc00 +# C7.2.166 FRINTX (scalar) page C7-2391 line 139726 MATCH x1e274000/mask=xff3ffc00 +# C7.2.168 FRINTZ (scalar) page C7-2395 line 139964 MATCH x1e25c000/mask=xff3ffc00 +# CONSTRUCT x1e244000/mask=xfffc7c00 MATCHED 7 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =trunc +# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1 +# AUNIT --inst x1e244000/mask=xfffc7c00 --rand sfp --status fail --comment "nofpround" +# Single-precision variant when type = 00 suf=32 + +:frint^frint_smode Rd_FPR32, Rn_FPR32 +is b_2431=0b00011110 & b_2223=0b00 & b_1821=0b1001 & b_1517 & b_1014=0b10000 & frint_smode & Rd_FPR32 & Rn_FPR32 & Zd +{ + Rd_FPR32 = trunc(Rn_FPR32); + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.156 FRINTA (scalar) page C7-2371 line 138539 MATCH x1e264000/mask=xff3ffc00 +# C7.2.158 FRINTI (scalar) page C7-2375 line 138773 MATCH x1e27c000/mask=xff3ffc00 +# C7.2.160 FRINTM (scalar) page C7-2379 line 139011 MATCH x1e254000/mask=xff3ffc00 +# C7.2.162 FRINTN (scalar) page C7-2383 line 139249 MATCH x1e244000/mask=xff3ffc00 +# C7.2.164 FRINTP (scalar) page C7-2387 line 139487 MATCH x1e24c000/mask=xff3ffc00 +# C7.2.166 FRINTX (scalar) page C7-2391 line 139726 MATCH x1e274000/mask=xff3ffc00 +# C7.2.168 FRINTZ (scalar) page C7-2395 line 139964 MATCH x1e25c000/mask=xff3ffc00 +# CONSTRUCT x1e644000/mask=xfffc7c00 MATCHED 7 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =trunc +# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1 +# AUNIT --inst x1e644000/mask=xfffc7c00 --rand dfp --status fail --comment "nofpround" +# Double-precision variant when type = 01 suf=64 + +:frint^frint_smode Rd_FPR64, Rn_FPR64 +is b_2431=0b00011110 & b_2223=0b01 & b_1821=0b1001 & b_1517 & b_1014=0b10000 & frint_smode & Rd_FPR64 & Rn_FPR64 & Zd +{ + Rd_FPR64 = trunc(Rn_FPR64); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.169 FRSQRTE page C7-2397 line 140071 MATCH x7ef9d800/mask=xfffffc00 +# CONSTRUCT x7ef9d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1 +# AUNIT --inst x7ef9d800/mask=xfffffc00 --status noqemu --comment "nofpround" +# Scalar half precision variant when Q=1 sz=1 ba=11 bb=111 V=FPR16 esize= + +:frsqrte Rd_FPR16, Rn_FPR16 +is b_31=0 & b_30=1 & b_2329=0b1111101 & b_22=1 & b_1021=0b111001110110 & Rd_FPR16 & Rn_FPR16 & Zd +{ + Rd_FPR16 = NEON_frsqrte(Rn_FPR16); +} + +# C7.2.169 FRSQRTE page C7-2397 line 140071 MATCH x7ea1d800/mask=xffbffc00 +# CONSTRUCT x7ea1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1 +# AUNIT --inst x7ea1d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround" +# Scalar single-precision and double-precision variant when Q=1 sz=0 ba=11 bb=100 V=FPR32 esize= + +:frsqrte Rd_FPR32, Rn_FPR32 +is b_31=0 & b_30=1 & b_2329=0b1111101 & b_22=0 & b_1021=0b100001110110 & Rd_FPR32 & Rn_FPR32 & Zd +{ + Rd_FPR32 = NEON_frsqrte(Rn_FPR32); +} + +# C7.2.169 FRSQRTE page C7-2397 line 140071 MATCH x7ea1d800/mask=xffbffc00 +# CONSTRUCT x7ee1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1 +# AUNIT --inst x7ee1d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround" +# Scalar single-precision and double-precision variant when Q=1 sz=1 ba=11 bb=100 V=FPR64 esize= + +:frsqrte Rd_FPR64, Rn_FPR64 +is b_31=0 & b_30=1 & b_2329=0b1111101 & b_22=1 & b_1021=0b100001110110 & Rd_FPR64 & Rn_FPR64 & Zd +{ + Rd_FPR64 = NEON_frsqrte(Rn_FPR64); +} + +# C7.2.169 FRSQRTE page C7-2397 line 140071 MATCH x2ef9d800/mask=xbffffc00 +# CONSTRUCT x2ef9d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1@2 +# AUNIT --inst x2ef9d800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# Vector half precision variant when Q=0 sz=1 ba=10 bb=111 V=VPR64.4H esize=@2 + +:frsqrte Rd_VPR64.4H, Rn_VPR64.4H +is b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=1 & b_1021=0b111001110110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_frsqrte(Rn_VPR64.4H, 2:1); +} + +# C7.2.169 FRSQRTE page C7-2397 line 140071 MATCH x2ef9d800/mask=xbffffc00 +# CONSTRUCT x6ef9d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1@2 +# AUNIT --inst x6ef9d800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# Vector half precision variant when Q=1 sz=1 ba=10 bb=111 V=VPR128.8H esize=@2 + +:frsqrte Rd_VPR128.8H, Rn_VPR128.8H +is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=1 & b_1021=0b111001110110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_frsqrte(Rn_VPR128.8H, 2:1); +} + +# C7.2.169 FRSQRTE page C7-2397 line 140071 MATCH x2ea1d800/mask=xbfbffc00 +# CONSTRUCT x2ea1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1@4 +# AUNIT --inst x2ea1d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround" +# Vector single-precision and double-precision variant when Q=0 sz=0 ba=10 bb=100 V=VPR64.2S esize=@4 + +:frsqrte Rd_VPR64.2S, Rn_VPR64.2S +is b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=0 & b_1021=0b100001110110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_frsqrte(Rn_VPR64.2S, 4:1); +} + +# C7.2.169 FRSQRTE page C7-2397 line 140071 MATCH x2ea1d800/mask=xbfbffc00 +# CONSTRUCT x6ea1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1@4 +# AUNIT --inst x6ea1d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround" +# Vector single-precision and double-precision variant when Q=1 sz=0 ba=10 bb=100 V=VPR128.4S esize=@4 + +:frsqrte Rd_VPR128.4S, Rn_VPR128.4S +is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=0 & b_1021=0b100001110110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_frsqrte(Rn_VPR128.4S, 4:1); +} + +# C7.2.169 FRSQRTE page C7-2397 line 140071 MATCH x2ea1d800/mask=xbfbffc00 +# CONSTRUCT x6ee1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1@8 +# AUNIT --inst x6ee1d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround" +# Vector single-precision and double-precision variant when Q=1 sz=1 ba=10 bb=100 V=VPR128.2D esize=@8 + +:frsqrte Rd_VPR128.2D, Rn_VPR128.2D +is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=1 & b_1021=0b100001110110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_frsqrte(Rn_VPR128.2D, 8:1); +} + +# C7.2.170 FRSQRTS page C7-2400 line 140259 MATCH x5ec03c00/mask=xffe0fc00 +# CONSTRUCT x5ec03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrts/1 +# AUNIT --inst x5ec03c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Scalar half precision variant when Q=1 sz=1 ba=01 bb=0 bc=00 V=FPR16 esize= + +:frsqrts Rd_FPR16, Rn_FPR16, Rm_FPR16 +is b_31=0 & b_30=1 & b_2329=0b0111101 & b_22=1 & b_21=0 & b_1015=0b001111 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd +{ + Rd_FPR16 = NEON_frsqrts(Rn_FPR16); +} + +# C7.2.170 FRSQRTS page C7-2400 line 140259 MATCH x5ea0fc00/mask=xffa0fc00 +# CONSTRUCT x5ea0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2 +# AUNIT --inst x5ea0fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" +# Scalar single-precision and double-precision variant when Q=1 sz=0 ba=01 bb=1 bc=11 V=FPR32 esize= + +:frsqrts Rd_FPR32, Rn_FPR32, Rm_FPR32 +is b_31=0 & b_30=1 & b_2329=0b0111101 & b_22=0 & b_21=1 & b_1015=0b111111 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd +{ + Rd_FPR32 = NEON_frsqrts(Rn_FPR32, Rm_FPR32); +} + +# C7.2.170 FRSQRTS page C7-2400 line 140259 MATCH x5ea0fc00/mask=xffa0fc00 +# CONSTRUCT x5ee0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2 +# AUNIT --inst x5ee0fc00/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround" +# Scalar single-precision and double-precision variant when Q=1 sz=1 ba=01 bb=1 bc=11 V=FPR64 esize= + +:frsqrts Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_31=0 & b_30=1 & b_2329=0b0111101 & b_22=1 & b_21=1 & b_1015=0b111111 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd +{ + Rd_FPR64 = NEON_frsqrts(Rn_FPR64, Rm_FPR64); +} + +# C7.2.170 FRSQRTS page C7-2400 line 140259 MATCH x0ec03c00/mask=xbfe0fc00 +# CONSTRUCT x0ec03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2@2 +# AUNIT --inst x0ec03c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Vector half precision variant when Q=0 sz=1 ba=00 bb=0 bc=00 V=VPR64.4H esize=@2 + +:frsqrts Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2329=0b0011101 & b_22=1 & b_21=0 & b_1015=0b001111 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_frsqrts(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.170 FRSQRTS page C7-2400 line 140259 MATCH x0ec03c00/mask=xbfe0fc00 +# CONSTRUCT x4ec03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2@2 +# AUNIT --inst x4ec03c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Vector half precision variant when Q=1 sz=1 ba=00 bb=0 bc=00 V=VPR128.8H esize=@2 + +:frsqrts Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2329=0b0011101 & b_22=1 & b_21=0 & b_1015=0b001111 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_frsqrts(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.170 FRSQRTS page C7-2400 line 140259 MATCH x0ea0fc00/mask=xbfa0fc00 +# CONSTRUCT x0ea0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2@4 +# AUNIT --inst x0ea0fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" +# Vector single-precision and double-precision variant when Q=0 sz=0 ba=00 bb=1 bc=11 V=VPR64.2S esize=@4 + +:frsqrts Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_31=0 & b_30=0 & b_2329=0b0011101 & b_22=0 & b_21=1 & b_1015=0b111111 & Rd_VPR64.2S & Rn_VPR64.2S & Rm_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_frsqrts(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.170 FRSQRTS page C7-2400 line 140259 MATCH x0ea0fc00/mask=xbfa0fc00 +# CONSTRUCT x4ea0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2@4 +# AUNIT --inst x4ea0fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround" +# Vector single-precision and double-precision variant when Q=1 sz=0 ba=00 bb=1 bc=11 V=VPR128.4S esize=@4 + +:frsqrts Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_31=0 & b_30=1 & b_2329=0b0011101 & b_22=0 & b_21=1 & b_1015=0b111111 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_frsqrts(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.170 FRSQRTS page C7-2400 line 140259 MATCH x0ea0fc00/mask=xbfa0fc00 +# CONSTRUCT x4ee0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2@8 +# AUNIT --inst x4ee0fc00/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround" +# Vector single-precision and double-precision variant when Q=1 sz=1 ba=00 bb=1 bc=11 V=VPR128.2D esize=@8 + +:frsqrts Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_31=0 & b_30=1 & b_2329=0b0011101 & b_22=1 & b_21=1 & b_1015=0b111111 & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_frsqrts(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.171 FSQRT (vector) page C7-2403 line 140456 MATCH x2ef9f800/mask=xbffffc00 +# CONSTRUCT x2ef9f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1@2 +# AUNIT --inst x2ef9f800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant when Q=0 sz=1 ba=111 esize=2 suf=VPR64.4H + +:fsqrt Rd_VPR64.4H, Rn_VPR64.4H +is b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=1 & b_1021=0b111001111110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_fsqrt(Rn_VPR64.4H, 2:1); +} + +# C7.2.171 FSQRT (vector) page C7-2403 line 140456 MATCH x2ef9f800/mask=xbffffc00 +# CONSTRUCT x6ef9f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1@2 +# AUNIT --inst x6ef9f800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant when Q=1 sz=1 ba=111 esize=2 suf=VPR128.8H + +:fsqrt Rd_VPR128.8H, Rn_VPR128.8H +is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=1 & b_1021=0b111001111110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_fsqrt(Rn_VPR128.8H, 2:1); +} + +# C7.2.171 FSQRT (vector) page C7-2403 line 140456 MATCH x2ea1f800/mask=xbfbffc00 +# CONSTRUCT x2ea1f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1@4 +# AUNIT --inst x2ea1f800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround" +# Single-precision and double-precision variant when Q=0 sz=0 ba=100 esize=4 suf=VPR64.2S + +:fsqrt Rd_VPR64.2S, Rn_VPR64.2S +is b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=0 & b_1021=0b100001111110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_fsqrt(Rn_VPR64.2S, 4:1); +} + +# C7.2.171 FSQRT (vector) page C7-2403 line 140456 MATCH x2ea1f800/mask=xbfbffc00 +# CONSTRUCT x6ea1f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1@4 +# AUNIT --inst x6ea1f800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround" +# Single-precision and double-precision variant when Q=1 sz=0 ba=100 esize=4 suf=VPR128.4S + +:fsqrt Rd_VPR128.4S, Rn_VPR128.4S +is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=0 & b_1021=0b100001111110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_fsqrt(Rn_VPR128.4S, 4:1); +} + +# C7.2.171 FSQRT (vector) page C7-2403 line 140456 MATCH x2ea1f800/mask=xbfbffc00 +# CONSTRUCT x6ee1f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1@8 +# AUNIT --inst x6ee1f800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround" +# Single-precision and double-precision variant when Q=1 sz=1 ba=100 esize=8 suf=VPR128.2D + +:fsqrt Rd_VPR128.2D, Rn_VPR128.2D +is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=1 & b_1021=0b100001111110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_fsqrt(Rn_VPR128.2D, 8:1); +} + +# C7.2.172 FSQRT (scalar) page C7-2405 line 140566 MATCH x1e21c000/mask=xff3ffc00 +# CONSTRUCT x1ee1c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =sqrt/1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1 +# AUNIT --inst x1ee1c000/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant + +:fsqrt Rd_FPR16, Rn_FPR16 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & fpDpOpcode=0x3 & b_1014=0x10 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = sqrt(Rn_FPR16); + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.172 FSQRT (scalar) page C7-2405 line 140566 MATCH x1e21c000/mask=xff3ffc00 +# CONSTRUCT x1e21c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =sqrt/1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1 +# AUNIT --inst x1e21c000/mask=xfffffc00 --rand sfp --status fail --comment "nofpround" +# Single-precision variant + +:fsqrt Rd_FPR32, Rn_FPR32 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & fpDpOpcode=0x3 & b_1014=0x10 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = sqrt(Rn_FPR32); + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.172 FSQRT (scalar) page C7-2405 line 140566 MATCH x1e21c000/mask=xff3ffc00 +# CONSTRUCT x1e61c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =sqrt/1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1 +# AUNIT --inst x1e61c000/mask=xfffffc00 --rand dfp --status fail --comment "nofpround" +# Double-precision variant + +:fsqrt Rd_FPR64, Rn_FPR64 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & fpDpOpcode=0x3 & b_1014=0x10 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = sqrt(Rn_FPR64); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.173 FSUB (vector) page C7-2407 line 140666 MATCH x0ea0d400/mask=xbfa0fc00 +# CONSTRUCT x4ee0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f-@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2@8 +# AUNIT --inst x4ee0d400/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround" + +:fsub Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x1a & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + # simd infix Rd_VPR128.2D = Rn_VPR128.2D f- Rm_VPR128.2D on lane size 8 + Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] f- Rm_VPR128.2D[0,64]; + Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] f- Rm_VPR128.2D[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.173 FSUB (vector) page C7-2407 line 140666 MATCH x0ea0d400/mask=xbfa0fc00 +# CONSTRUCT x0ea0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2@4 +# AUNIT --inst x0ea0d400/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround" + +:fsub Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x1a & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + # simd infix Rd_VPR64.2S = Rn_VPR64.2S f- Rm_VPR64.2S on lane size 4 + Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] f- Rm_VPR64.2S[0,32]; + Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] f- Rm_VPR64.2S[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.173 FSUB (vector) page C7-2407 line 140666 MATCH x0ea0d400/mask=xbfa0fc00 +# CONSTRUCT x4ea0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2@4 +# AUNIT --inst x4ea0d400/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround" + +:fsub Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x1a & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd infix Rd_VPR128.4S = Rn_VPR128.4S f- Rm_VPR128.4S on lane size 4 + Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] f- Rm_VPR128.4S[0,32]; + Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] f- Rm_VPR128.4S[32,32]; + Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] f- Rm_VPR128.4S[64,32]; + Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] f- Rm_VPR128.4S[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.173 FSUB (vector) page C7-2407 line 140666 MATCH x0ec01400/mask=xbfe0fc00 +# CONSTRUCT x0ec01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f-@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2@2 +# AUNIT --inst x0ec01400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant when Q=0 suf=VPR64.4H + +:fsub Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2129=0b001110110 & b_1015=0b000101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd +{ + # simd infix Rd_VPR64.4H = Rn_VPR64.4H f- Rm_VPR64.4H on lane size 2 + Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f- Rm_VPR64.4H[0,16]; + Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f- Rm_VPR64.4H[16,16]; + Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f- Rm_VPR64.4H[32,16]; + Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f- Rm_VPR64.4H[48,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.173 FSUB (vector) page C7-2407 line 140666 MATCH x0ec01400/mask=xbfe0fc00 +# CONSTRUCT x4ec01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$f-@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2@2 +# AUNIT --inst x4ec01400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" +# Half-precision variant when Q=1 suf=VPR128.8H + +:fsub Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2129=0b001110110 & b_1015=0b000101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd +{ + # simd infix Rd_VPR128.8H = Rn_VPR128.8H f- Rm_VPR128.8H on lane size 2 + Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f- Rm_VPR128.8H[0,16]; + Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f- Rm_VPR128.8H[16,16]; + Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f- Rm_VPR128.8H[32,16]; + Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f- Rm_VPR128.8H[48,16]; + Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f- Rm_VPR128.8H[64,16]; + Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f- Rm_VPR128.8H[80,16]; + Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f- Rm_VPR128.8H[96,16]; + Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f- Rm_VPR128.8H[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.174 FSUB (scalar) page C7-2409 line 140785 MATCH x1e203800/mask=xff20fc00 +# CONSTRUCT x1e603800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =f- +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2 +# AUNIT --inst x1e603800/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround" + +:fsub Rd_FPR64, Rn_FPR64, Rm_FPR64 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x3 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = Rn_FPR64 f- Rm_FPR64; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.174 FSUB (scalar) page C7-2409 line 140785 MATCH x1e203800/mask=xff20fc00 +# CONSTRUCT x1e203800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =f- +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2 +# AUNIT --inst x1e203800/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround" + +:fsub Rd_FPR32, Rn_FPR32, Rm_FPR32 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x3 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = Rn_FPR32 f- Rm_FPR32; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.174 FSUB (scalar) page C7-2409 line 140785 MATCH x1e203800/mask=xff20fc00 +# CONSTRUCT x1ee03800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =f- +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2 +# AUNIT --inst x1ee03800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround" + +:fsub Rd_FPR16, Rn_FPR16, Rm_FPR16 +is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x3 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = Rn_FPR16 f- Rm_FPR16; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.189 LDNP (SIMD&FP) page C7-2456 line 143778 MATCH x2c400000/mask=x3fc00000 +# CONSTRUCT x2c400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG3 =load ext ARG2 ARG3 4 +:8 =load ext +# SMACRO(pseudo) ARG1 ARG3 =NEON_ldnp1/1 ARG2 ARG3 =NEON_ldnp2/1 +# AUNIT --inst x2c400000/mask=xffc00000 --status nomem + +:ldnp Rt_FPR32, Rt2_FPR32, addrPairIndexed +is b_3031=0b00 & b_2229=0b10110001 & Rt2_FPR32 & addrPairIndexed & Rt_FPR32 & Zt & Zt2 +{ + Rt_FPR32 = * addrPairIndexed; + zext_zs(Zt); # zero upper 28 bytes of Zt + local tmp1:8 = addrPairIndexed + 4; + Rt2_FPR32 = * tmp1; + zext_zs(Zt2); # zero upper 28 bytes of Zt2 +} + +# C7.2.189 LDNP (SIMD&FP) page C7-2456 line 143778 MATCH x2c400000/mask=x3fc00000 +# CONSTRUCT x6c400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG3 =load ext ARG2 ARG3 8 +:8 =load ext +# SMACRO(pseudo) ARG1 ARG3 =NEON_ldnp1/1 ARG2 ARG3 =NEON_ldnp2/1 +# AUNIT --inst x6c400000/mask=xffc00000 --status nomem + +:ldnp Rt_FPR64, Rt2_FPR64, addrPairIndexed +is b_3031=0b01 & b_2229=0b10110001 & Rt2_FPR64 & addrPairIndexed & Rt_FPR64 & Zt & Zt2 +{ + Rt_FPR64 = * addrPairIndexed; + zext_zd(Zt); # zero upper 24 bytes of Zt + local tmp1:8 = addrPairIndexed + 8; + Rt2_FPR64 = * tmp1; + zext_zd(Zt2); # zero upper 24 bytes of Zt2 +} + +# C7.2.189 LDNP (SIMD&FP) page C7-2456 line 143778 MATCH x2c400000/mask=x3fc00000 +# CONSTRUCT xac400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG3 =load ext ARG2 ARG3 16 +:8 =load ext +# SMACRO(pseudo) ARG1 ARG3 =NEON_ldnp1/1 ARG2 ARG3 =NEON_ldnp2/1 +# AUNIT --inst xac400000/mask=xffc00000 --status nomem + +:ldnp Rt_FPR128, Rt2_FPR128, addrPairIndexed +is b_3031=0b10 & b_2229=0b10110001 & Rt2_FPR128 & addrPairIndexed & Rt_FPR128 & Zt & Zt2 +{ + Rt_FPR128 = * addrPairIndexed; + zext_zq(Zt); # zero upper 16 bytes of Zt + local tmp1:8 = addrPairIndexed + 16; + Rt2_FPR128 = * tmp1; + zext_zq(Zt2); # zero upper 16 bytes of Zt2 +} + +# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2cc00000/mask=x3fc00000 +# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2dc00000/mask=x3fc00000 +# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2d400000/mask=x3fc00000 +# C7.2.189 LDNP (SIMD&FP) page C7-2456 line 143778 MATCH x2c400000/mask=x3fc00000 +# CONSTRUCT xac400000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES +# SMACRO ARG1 ARG3 =load ext ARG2 ARG3 16 +:8 =load ext +# SMACRO(pseudo) ARG1 ARG3 =NEON_ldp1/1 ARG2 ARG3 =NEON_ldp2/1 +# AUNIT --inst xac400000/mask=xfe400000 --status nomem + +:ldp Rt_FPR128, Rt2_FPR128, addrPairIndexed +is b_3031=0b10 & b_2529=0b10110 & b_22=0b1 & Rt2_FPR128 & addrPairIndexed & Rt_FPR128 & Zt & Zt2 +{ + Rt_FPR128 = * addrPairIndexed; + zext_zq(Zt); # zero upper 16 bytes of Zt + local tmp1:8 = addrPairIndexed + 16; + Rt2_FPR128 = * tmp1; + zext_zq(Zt2); # zero upper 16 bytes of Zt2 +} + +# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2cc00000/mask=x3fc00000 +# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2dc00000/mask=x3fc00000 +# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2d400000/mask=x3fc00000 +# C7.2.189 LDNP (SIMD&FP) page C7-2456 line 143778 MATCH x2c400000/mask=x3fc00000 +# CONSTRUCT x2c400000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES +# SMACRO ARG1 ARG3 =load ext ARG2 ARG3 4 +:8 =load ext +# SMACRO(pseudo) ARG1 ARG3 =NEON_ldp1/1 ARG2 ARG3 =NEON_ldp2/1 +# AUNIT --inst x2c400000/mask=xfe400000 --status nomem + +:ldp Rt_FPR32, Rt2_FPR32, addrPairIndexed +is b_3031=0b00 & b_2529=0b10110 & b_22=0b1 & Rt2_FPR32 & addrPairIndexed & Rt_FPR32 & Zt & Zt2 +{ + Rt_FPR32 = * addrPairIndexed; + zext_zs(Zt); # zero upper 28 bytes of Zt + local tmp1:8 = addrPairIndexed + 4; + Rt2_FPR32 = * tmp1; + zext_zs(Zt2); # zero upper 28 bytes of Zt2 +} + +# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2cc00000/mask=x3fc00000 +# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2dc00000/mask=x3fc00000 +# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2d400000/mask=x3fc00000 +# C7.2.189 LDNP (SIMD&FP) page C7-2456 line 143778 MATCH x2c400000/mask=x3fc00000 +# CONSTRUCT x6c400000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES +# SMACRO ARG1 ARG3 =load ext ARG2 ARG3 8 +:8 =load ext +# SMACRO(pseudo) ARG1 ARG3 =NEON_ldp1/1 ARG2 ARG3 =NEON_ldp2/1 +# AUNIT --inst x6c400000/mask=xfe400000 --status nomem + +:ldp Rt_FPR64, Rt2_FPR64, addrPairIndexed +is b_3031=0b01 & b_2529=0b10110 & b_22=0b1 & Rt2_FPR64 & addrPairIndexed & Rt_FPR64 & Zt & Zt2 +{ + Rt_FPR64 = * addrPairIndexed; + zext_zd(Zt); # zero upper 24 bytes of Zt + local tmp1:8 = addrPairIndexed + 8; + Rt2_FPR64 = * tmp1; + zext_zd(Zt2); # zero upper 24 bytes of Zt2 +} + +# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400400/mask=x3f600c00 +# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400c00/mask=x3f600c00 +# CONSTRUCT x3c400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =load +# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1 +# AUNIT --inst x3c400400/mask=xffe00400 --status nomem +# Post- and Pre-index 8-bit variant when size==00 && opc==01 F=FPR8 + +:ldr Rt_FPR8, addrIndexed +is b_3031=0b00 & b_2429=0b111100 & b_2223=0b01 & b_21=0 & b_10=1 & Rt_FPR8 & addrIndexed & Zt +{ + Rt_FPR8 = * addrIndexed; + zext_zb(Zt); # zero upper 31 bytes of Zt +} + +# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400400/mask=x3f600c00 +# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400c00/mask=x3f600c00 +# CONSTRUCT x7c400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =load +# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1 +# AUNIT --inst x7c400400/mask=xffe00400 --status nomem +# Post- and Pre-index 16-bit variant when size==01 && opc==01 F=FPR16 + +:ldr Rt_FPR16, addrIndexed +is b_3031=0b01 & b_2429=0b111100 & b_2223=0b01 & b_21=0 & b_10=1 & Rt_FPR16 & addrIndexed & Zt +{ + Rt_FPR16 = * addrIndexed; + zext_zh(Zt); # zero upper 30 bytes of Zt +} + +# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400400/mask=x3f600c00 +# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400c00/mask=x3f600c00 +# CONSTRUCT xbc400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =load +# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1 +# AUNIT --inst xbc400400/mask=xffe00400 --status nomem +# Post- and Pre-index 32-bit variant when size==10 && opc==01 F=FPR32 + +:ldr Rt_FPR32, addrIndexed +is b_3031=0b10 & b_2429=0b111100 & b_2223=0b01 & b_21=0 & b_10=1 & Rt_FPR32 & addrIndexed & Zt +{ + Rt_FPR32 = * addrIndexed; + zext_zs(Zt); # zero upper 28 bytes of Zt +} + +# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400400/mask=x3f600c00 +# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400c00/mask=x3f600c00 +# CONSTRUCT xfc400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =load +# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1 +# AUNIT --inst xfc400400/mask=xffe00400 --status nomem +# Post- and Pre-index 64-bit variant when size==11 && opc==01 F=FPR64 + +:ldr Rt_FPR64, addrIndexed +is b_3031=0b11 & b_2429=0b111100 & b_2223=0b01 & b_21=0 & b_10=1 & Rt_FPR64 & addrIndexed & Zt +{ + Rt_FPR64 = * addrIndexed; + zext_zd(Zt); # zero upper 24 bytes of Zt +} + +# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400400/mask=x3f600c00 +# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400c00/mask=x3f600c00 +# CONSTRUCT x3cc00400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =load +# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1 +# AUNIT --inst x3cc00400/mask=xffe00400 --status nomem +# Post- and Pre-index 128-bit variant when size==00 && opc==11 F=FPR128 + +:ldr Rt_FPR128, addrIndexed +is b_3031=0b00 & b_2429=0b111100 & b_2223=0b11 & b_21=0 & b_10=1 & Rt_FPR128 & addrIndexed & Zt +{ + Rt_FPR128 = * addrIndexed; + zext_zq(Zt); # zero upper 16 bytes of Zt +} + +# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3d400000/mask=x3f400000 +# CONSTRUCT x3d400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =load +# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1 +# AUNIT --inst x3d400000/mask=xffc00000 --status nomem +# Unsigned offset 8-bit variant when size == 00 && opc == 01 F=FPR8 + +:ldr Rt_FPR8, addrUIMM +is b_3031=0b00 & b_2429=0b111101 & b_2223=0b01 & Rt_FPR8 & addrUIMM & Zt +{ + Rt_FPR8 = * addrUIMM; + zext_zb(Zt); # zero upper 31 bytes of Zt +} + +# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3d400000/mask=x3f400000 +# CONSTRUCT x7d400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =load +# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1 +# AUNIT --inst x7d400000/mask=xffc00000 --status nomem +# Unsigned offset 16-bit variant when size == 01 && opc == 01 F=FPR16 + +:ldr Rt_FPR16, addrUIMM +is b_3031=0b01 & b_2429=0b111101 & b_2223=0b01 & Rt_FPR16 & addrUIMM & Zt +{ + Rt_FPR16 = * addrUIMM; + zext_zh(Zt); # zero upper 30 bytes of Zt +} + +# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3d400000/mask=x3f400000 +# CONSTRUCT xbd400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =load +# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1 +# AUNIT --inst xbd400000/mask=xffc00000 --status nomem +# Unsigned offset 32-bit variant when size == 10 && opc == 01 F=FPR32 + +:ldr Rt_FPR32, addrUIMM +is b_3031=0b10 & b_2429=0b111101 & b_2223=0b01 & Rt_FPR32 & addrUIMM & Zt +{ + Rt_FPR32 = * addrUIMM; + zext_zs(Zt); # zero upper 28 bytes of Zt +} + +# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3d400000/mask=x3f400000 +# CONSTRUCT xfd400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =load +# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1 +# AUNIT --inst xfd400000/mask=xffc00000 --status nomem +# Unsigned offset 64-bit variant when size == 11 && opc == 01 F=FPR64 + +:ldr Rt_FPR64, addrUIMM +is b_3031=0b11 & b_2429=0b111101 & b_2223=0b01 & Rt_FPR64 & addrUIMM & Zt +{ + Rt_FPR64 = * addrUIMM; + zext_zd(Zt); # zero upper 24 bytes of Zt +} + +# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3d400000/mask=x3f400000 +# CONSTRUCT x3dc00000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =load +# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1 +# AUNIT --inst x3dc00000/mask=xffc00000 --status nomem +# Unsigned offset 128-bit variant when size == 00 && opc == 11 F=FPR128 + +:ldr Rt_FPR128, addrUIMM +is b_3031=0b00 & b_2429=0b111101 & b_2223=0b11 & Rt_FPR128 & addrUIMM & Zt +{ + Rt_FPR128 = * addrUIMM; + zext_zq(Zt); # zero upper 16 bytes of Zt +} + +# C7.2.192 LDR (literal, SIMD&FP) page C7-2466 line 144427 MATCH x1c000000/mask=x3f000000 +# CONSTRUCT x5c000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =load:8 +# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1 +# AUNIT --inst x5c000000/mask=xff000000 --status nomem + +:ldr Rt_FPR64, AddrLoc19 +is size.ldstr=1 & b_2729=3 & v=1 & b_2425=0 & AddrLoc19 & Rt_FPR64 & Zt +{ + Rt_FPR64 = *:8 AddrLoc19; + zext_zd(Zt); # zero upper 24 bytes of Zt +} + +# C7.2.192 LDR (literal, SIMD&FP) page C7-2466 line 144427 MATCH x1c000000/mask=x3f000000 +# CONSTRUCT x9c000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =load:16 +# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1 +# AUNIT --inst x9c000000/mask=xff000000 --status nomem + +:ldr Rt_FPR128, AddrLoc19 +is size.ldstr=2 & b_2729=3 & v=1 & b_2425=0 & AddrLoc19 & Rt_FPR128 & Zt +{ + Rt_FPR128 = *:16 AddrLoc19; + zext_zq(Zt); # zero upper 16 bytes of Zt +} + +# C7.2.192 LDR (literal, SIMD&FP) page C7-2466 line 144427 MATCH x1c000000/mask=x3f000000 +# CONSTRUCT x1c000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =load:4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1 +# AUNIT --inst x1c000000/mask=xff000000 --status nomem + +:ldr Rt_FPR32, AddrLoc19 +is size.ldstr=0 & b_2729=3 & v=1 & b_2425=0 & AddrLoc19 & Rt_FPR32 & Zt +{ + Rt_FPR32 = *:4 AddrLoc19; + zext_zs(Zt); # zero upper 28 bytes of Zt +} + +# C7.2.178 LDR (register, SIMD&FP) page C7-1411 line 82199 KEEPWITH + +extend_amount: "" is b_3031=0b00 & b_23=0 & b_12=0 { export 0:1; } +extend_amount: " #0" is b_3031=0b00 & b_23=0 & b_12=1 { export 0:1; } +extend_amount: "" is b_3031=0b01 & b_23=0 & b_12=0 { export 0:1; } +extend_amount: " #1" is b_3031=0b01 & b_23=0 & b_12=1 { export 1:1; } +extend_amount: "" is b_3031=0b10 & b_23=0 & b_12=0 { export 0:1; } +extend_amount: " #2" is b_3031=0b10 & b_23=0 & b_12=1 { export 2:1; } +extend_amount: "" is b_3031=0b11 & b_23=0 & b_12=0 { export 0:1; } +extend_amount: " #3" is b_3031=0b11 & b_23=0 & b_12=1 { export 3:1; } +extend_amount: "" is b_3031=0b00 & b_23=1 & b_12=0 { export 0:1; } +extend_amount: " #4" is b_3031=0b00 & b_23=1 & b_12=1 { export 4:1; } + +extend_spec: ", uxtw" is b_1315=0b010 & Rm_GPR32 { local tmp:8 = zext(Rm_GPR32); export tmp; } +extend_spec: ", sxtw" is b_1315=0b110 & Rm_GPR32 { local tmp:8 = sext(Rm_GPR32); export tmp; } +extend_spec: ", sxtx" is b_1315=0b111 & Rm_GPR64 { export Rm_GPR64; } +extend_spec: ", lsl" is b_1315=0b011 & b_12=1 & Rm_GPR64 { export Rm_GPR64; } # same as uxtx +extend_spec: "" is b_1315=0b011 & b_12=0 & Rm_GPR64 { export Rm_GPR64; } # same as uxtx + +# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00 +# CONSTRUCT x3c600800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load +# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3 +# AUNIT --inst x3c600800/mask=xffe02c00 --status nomem +# 8-fsreg,LDR-8-fsreg variant when size == 00 && opc == 01 && option is not 011 bb=b_13 option=0 F=FPR8 G=GPR32 + +:ldr Rt_FPR8, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount] +is b_3031=0b00 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR8 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zt +{ + local tmp1:8 = extend_spec << extend_amount; + local tmp2:8 = Rn_GPR64xsp + tmp1; + Rt_FPR8 = * tmp2; + zext_zb(Zt); # zero upper 31 bytes of Zt +} + +# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00 +# CONSTRUCT x3c602800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load +# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3 +# AUNIT --inst x3c602800/mask=xffe02c00 --status nomem +# 8-fsreg,LDR-8-fsreg variant when size == 00 && opc == 01 && option is not 011 bb=b_13 option=1 F=FPR8 G=GPR64 + +:ldr Rt_FPR8, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount] +is b_3031=0b00 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR8 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zt +{ + local tmp1:8 = extend_spec << extend_amount; + local tmp2:8 = Rn_GPR64xsp + tmp1; + Rt_FPR8 = * tmp2; + zext_zb(Zt); # zero upper 31 bytes of Zt +} + +# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00 +# CONSTRUCT x3c606800/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load +# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3 +# AUNIT --inst x3c606800/mask=xffe0ec00 --status nomem +# 8-fsreg,LDR-8-fsreg variant when size == 00 && opc == 01 && option is 011 bb=b_1315 option=0b011 F=FPR8 G=GPR64 + +:ldr Rt_FPR8, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount] +is b_3031=0b00 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_1315=0b011 & b_1011=0b10 & Rt_FPR8 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zt +{ + local tmp1:8 = extend_spec << extend_amount; + local tmp2:8 = Rn_GPR64xsp + tmp1; + Rt_FPR8 = * tmp2; + zext_zb(Zt); # zero upper 31 bytes of Zt +} + +# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00 +# CONSTRUCT x7c600800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load +# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3 +# AUNIT --inst x7c600800/mask=xffe02c00 --status nomem +# 16-fsreg,LDR-16-fsreg variant when size == 01 && opc == 01 bb=b_13 option=0 F=FPR16 G=GPR32 + +:ldr Rt_FPR16, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount] +is b_3031=0b01 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR16 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zt +{ + local tmp1:8 = extend_spec << extend_amount; + local tmp2:8 = Rn_GPR64xsp + tmp1; + Rt_FPR16 = * tmp2; + zext_zh(Zt); # zero upper 30 bytes of Zt +} + +# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00 +# CONSTRUCT x7c602800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load +# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3 +# AUNIT --inst x7c602800/mask=xffe02c00 --status nomem +# 16-fsreg,LDR-16-fsreg variant when size == 01 && opc == 01 bb=b_13 option=1 F=FPR16 G=GPR64 + +:ldr Rt_FPR16, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount] +is b_3031=0b01 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR16 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zt +{ + local tmp1:8 = extend_spec << extend_amount; + local tmp2:8 = Rn_GPR64xsp + tmp1; + Rt_FPR16 = * tmp2; + zext_zh(Zt); # zero upper 30 bytes of Zt +} + +# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00 +# CONSTRUCT xbc600800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load +# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3 +# AUNIT --inst xbc600800/mask=xffe02c00 --status nomem +# 32-fsreg,LDR-32-fsreg variant when size == 10 && opc == 01 bb=b_13 option=0 F=FPR32 G=GPR32 + +:ldr Rt_FPR32, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount] +is b_3031=0b10 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR32 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zt +{ + local tmp1:8 = extend_spec << extend_amount; + local tmp2:8 = Rn_GPR64xsp + tmp1; + Rt_FPR32 = * tmp2; + zext_zs(Zt); # zero upper 28 bytes of Zt +} + +# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00 +# CONSTRUCT xbc602800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load +# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3 +# AUNIT --inst xbc602800/mask=xffe02c00 --status nomem +# 32-fsreg,LDR-32-fsreg variant when size == 10 && opc == 01 bb=b_13 option=1 F=FPR32 G=GPR64 + +:ldr Rt_FPR32, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount] +is b_3031=0b10 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR32 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zt +{ + local tmp1:8 = extend_spec << extend_amount; + local tmp2:8 = Rn_GPR64xsp + tmp1; + Rt_FPR32 = * tmp2; + zext_zs(Zt); # zero upper 28 bytes of Zt +} + +# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00 +# CONSTRUCT xfc600800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load +# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3 +# AUNIT --inst xfc600800/mask=xffe02c00 --status nomem +# 64-fsreg,LDR-64-fsreg variant when size == 11 && opc == 01 bb=b_13 option=0 F=FPR64 G=GPR32 + +:ldr Rt_FPR64, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount] +is b_3031=0b11 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR64 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zt +{ + local tmp1:8 = extend_spec << extend_amount; + local tmp2:8 = Rn_GPR64xsp + tmp1; + Rt_FPR64 = * tmp2; + zext_zd(Zt); # zero upper 24 bytes of Zt +} + +# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00 +# CONSTRUCT xfc602800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load +# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3 +# AUNIT --inst xfc602800/mask=xffe02c00 --status nomem +# 64-fsreg,LDR-64-fsreg variant when size == 11 && opc == 01 bb=b_13 option=1 F=FPR64 G=GPR64 + +:ldr Rt_FPR64, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount] +is b_3031=0b11 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR64 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zt +{ + local tmp1:8 = extend_spec << extend_amount; + local tmp2:8 = Rn_GPR64xsp + tmp1; + Rt_FPR64 = * tmp2; + zext_zd(Zt); # zero upper 24 bytes of Zt +} + +# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00 +# CONSTRUCT x3ce00800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load +# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3 +# AUNIT --inst x3ce00800/mask=xffe02c00 --status nomem +# 128-fsreg,LDR-128-fsreg variant when size == 00 && opc == 11 bb=b_13 option=0 F=FPR128 G=GPR32 + +:ldr Rt_FPR128, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount] +is b_3031=0b00 & b_2429=0b111100 & b_2223=0b11 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR128 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zt +{ + local tmp1:8 = extend_spec << extend_amount; + local tmp2:8 = Rn_GPR64xsp + tmp1; + Rt_FPR128 = * tmp2; + zext_zq(Zt); # zero upper 16 bytes of Zt +} + +# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00 +# CONSTRUCT x3ce02800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load +# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3 +# AUNIT --inst x3ce02800/mask=xffe02c00 --status nomem +# 128-fsreg,LDR-128-fsreg variant when size == 00 && opc == 11 bb=b_13 option=1 F=FPR128 G=GPR64 + +:ldr Rt_FPR128, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount] +is b_3031=0b00 & b_2429=0b111100 & b_2223=0b11 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR128 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zt +{ + local tmp1:8 = extend_spec << extend_amount; + local tmp2:8 = Rn_GPR64xsp + tmp1; + Rt_FPR128 = * tmp2; + zext_zq(Zt); # zero upper 16 bytes of Zt +} + +# C7.2.194 LDUR (SIMD&FP) page C7-2471 line 144715 MATCH x3c400000/mask=x3f600c00 +# CONSTRUCT x3cc00000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =load +# SMACRO(pseudo) ARG1 ARG2 =NEON_ldur/1 +# AUNIT --inst x3cc00000/mask=xffe00c00 --status nomem + +:ldur Rt_FPR128, addrIndexed +is size.ldstr=0 & b_2729=7 & v=1 & b_2425=0 & b_23=1 & b_2222=1 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR128 & Zt +{ + Rt_FPR128 = * addrIndexed; + zext_zq(Zt); # zero upper 16 bytes of Zt +} + +# C7.2.194 LDUR (SIMD&FP) page C7-2471 line 144715 MATCH x3c400000/mask=x3f600c00 +# CONSTRUCT x7c400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =load +# SMACRO(pseudo) ARG1 ARG2 =NEON_ldur/1 +# AUNIT --inst x7c400000/mask=xffe00c00 --status nomem + +:ldur Rt_FPR16, addrIndexed +is size.ldstr=1 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR16 & Zt +{ + Rt_FPR16 = * addrIndexed; + zext_zh(Zt); # zero upper 30 bytes of Zt +} + +# C7.2.194 LDUR (SIMD&FP) page C7-2471 line 144715 MATCH x3c400000/mask=x3f600c00 +# CONSTRUCT xbc400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =load +# SMACRO(pseudo) ARG1 ARG2 =NEON_ldur/1 +# AUNIT --inst xbc400000/mask=xffe00c00 --status nomem + +:ldur Rt_FPR32, addrIndexed +is size.ldstr=2 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR32 & Zt +{ + Rt_FPR32 = * addrIndexed; + zext_zs(Zt); # zero upper 28 bytes of Zt +} + +# C7.2.194 LDUR (SIMD&FP) page C7-2471 line 144715 MATCH x3c400000/mask=x3f600c00 +# CONSTRUCT xfc400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =load +# SMACRO(pseudo) ARG1 ARG2 =NEON_ldur/1 +# AUNIT --inst xfc400000/mask=xffe00c00 --status nomem + +:ldur Rt_FPR64, addrIndexed +is size.ldstr=3 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR64 & Zt +{ + Rt_FPR64 = * addrIndexed; + zext_zd(Zt); # zero upper 24 bytes of Zt +} + +# C7.2.194 LDUR (SIMD&FP) page C7-2471 line 144715 MATCH x3c400000/mask=x3f600c00 +# CONSTRUCT x3c400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =load +# SMACRO(pseudo) ARG1 ARG2 =NEON_ldur/1 +# AUNIT --inst x3c400000/mask=xffe00c00 --status nomem + +:ldur Rt_FPR8, addrIndexed +is size.ldstr=0 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR8 & Zt +{ + Rt_FPR8 = * addrIndexed; + zext_zb(Zt); # zero upper 31 bytes of Zt +} + +# C7.2.195 MLA (by element) page C7-2473 line 144842 MATCH x2f000000/mask=xbf00f400 +# CONSTRUCT x2f800000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $* &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@4 +# AUNIT --inst x2f800000/mask=xffc0f400 --status pass + +:mla Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex +is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & vIndex & Re_VPR128.S & b_1215=0x0 & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp1:4 = Re_VPR128.S.vIndex; + # simd infix TMPD1 = Rn_VPR64.2S * tmp1 on lane size 4 + TMPD1[0,32] = Rn_VPR64.2S[0,32] * tmp1; + TMPD1[32,32] = Rn_VPR64.2S[32,32] * tmp1; + # simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4 + Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32]; + Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.195 MLA (by element) page C7-2473 line 144842 MATCH x2f000000/mask=xbf00f400 +# CONSTRUCT x2f400000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $* &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@2 +# AUNIT --inst x2f400000/mask=xffc0f400 --status pass + +:mla Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM +is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x0 & b_1010=0 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp1:2 = Re_VPR128Lo.H.vIndexHLM; + # simd infix TMPD1 = Rn_VPR64.4H * tmp1 on lane size 2 + TMPD1[0,16] = Rn_VPR64.4H[0,16] * tmp1; + TMPD1[16,16] = Rn_VPR64.4H[16,16] * tmp1; + TMPD1[32,16] = Rn_VPR64.4H[32,16] * tmp1; + TMPD1[48,16] = Rn_VPR64.4H[48,16] * tmp1; + # simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2 + Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16]; + Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16]; + Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16]; + Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.195 MLA (by element) page C7-2473 line 144842 MATCH x2f000000/mask=xbf00f400 +# CONSTRUCT x6f800000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $* &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@4 +# AUNIT --inst x6f800000/mask=xffc0f400 --status pass + +:mla Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex +is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x0 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp1:4 = Re_VPR128.S.vIndex; + # simd infix TMPQ1 = Rn_VPR128.4S * tmp1 on lane size 4 + TMPQ1[0,32] = Rn_VPR128.4S[0,32] * tmp1; + TMPQ1[32,32] = Rn_VPR128.4S[32,32] * tmp1; + TMPQ1[64,32] = Rn_VPR128.4S[64,32] * tmp1; + TMPQ1[96,32] = Rn_VPR128.4S[96,32] * tmp1; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.195 MLA (by element) page C7-2473 line 144842 MATCH x2f000000/mask=xbf00f400 +# CONSTRUCT x6f400000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $* &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@2 +# AUNIT --inst x6f400000/mask=xffc0f400 --status pass + +:mla Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM +is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x0 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp1:2 = Re_VPR128Lo.H.vIndexHLM; + # simd infix TMPQ1 = Rn_VPR128.8H * tmp1 on lane size 2 + TMPQ1[0,16] = Rn_VPR128.8H[0,16] * tmp1; + TMPQ1[16,16] = Rn_VPR128.8H[16,16] * tmp1; + TMPQ1[32,16] = Rn_VPR128.8H[32,16] * tmp1; + TMPQ1[48,16] = Rn_VPR128.8H[48,16] * tmp1; + TMPQ1[64,16] = Rn_VPR128.8H[64,16] * tmp1; + TMPQ1[80,16] = Rn_VPR128.8H[80,16] * tmp1; + TMPQ1[96,16] = Rn_VPR128.8H[96,16] * tmp1; + TMPQ1[112,16] = Rn_VPR128.8H[112,16] * tmp1; + # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.196 MLA (vector) page C7-2475 line 144975 MATCH x0e209400/mask=xbf20fc00 +# CONSTRUCT x4e209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $*@1 &=$+@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@1 +# AUNIT --inst x4e209400/mask=xffe0fc00 --status pass + +:mla Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x12 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.16B * Rm_VPR128.16B on lane size 1 + TMPQ1[0,8] = Rn_VPR128.16B[0,8] * Rm_VPR128.16B[0,8]; + TMPQ1[8,8] = Rn_VPR128.16B[8,8] * Rm_VPR128.16B[8,8]; + TMPQ1[16,8] = Rn_VPR128.16B[16,8] * Rm_VPR128.16B[16,8]; + TMPQ1[24,8] = Rn_VPR128.16B[24,8] * Rm_VPR128.16B[24,8]; + TMPQ1[32,8] = Rn_VPR128.16B[32,8] * Rm_VPR128.16B[32,8]; + TMPQ1[40,8] = Rn_VPR128.16B[40,8] * Rm_VPR128.16B[40,8]; + TMPQ1[48,8] = Rn_VPR128.16B[48,8] * Rm_VPR128.16B[48,8]; + TMPQ1[56,8] = Rn_VPR128.16B[56,8] * Rm_VPR128.16B[56,8]; + TMPQ1[64,8] = Rn_VPR128.16B[64,8] * Rm_VPR128.16B[64,8]; + TMPQ1[72,8] = Rn_VPR128.16B[72,8] * Rm_VPR128.16B[72,8]; + TMPQ1[80,8] = Rn_VPR128.16B[80,8] * Rm_VPR128.16B[80,8]; + TMPQ1[88,8] = Rn_VPR128.16B[88,8] * Rm_VPR128.16B[88,8]; + TMPQ1[96,8] = Rn_VPR128.16B[96,8] * Rm_VPR128.16B[96,8]; + TMPQ1[104,8] = Rn_VPR128.16B[104,8] * Rm_VPR128.16B[104,8]; + TMPQ1[112,8] = Rn_VPR128.16B[112,8] * Rm_VPR128.16B[112,8]; + TMPQ1[120,8] = Rn_VPR128.16B[120,8] * Rm_VPR128.16B[120,8]; + # simd infix Rd_VPR128.16B = Rd_VPR128.16B + TMPQ1 on lane size 1 + Rd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] + TMPQ1[0,8]; + Rd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] + TMPQ1[8,8]; + Rd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] + TMPQ1[16,8]; + Rd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] + TMPQ1[24,8]; + Rd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] + TMPQ1[32,8]; + Rd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] + TMPQ1[40,8]; + Rd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] + TMPQ1[48,8]; + Rd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] + TMPQ1[56,8]; + Rd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] + TMPQ1[64,8]; + Rd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] + TMPQ1[72,8]; + Rd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] + TMPQ1[80,8]; + Rd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] + TMPQ1[88,8]; + Rd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] + TMPQ1[96,8]; + Rd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] + TMPQ1[104,8]; + Rd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] + TMPQ1[112,8]; + Rd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] + TMPQ1[120,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.196 MLA (vector) page C7-2475 line 144975 MATCH x0e209400/mask=xbf20fc00 +# CONSTRUCT x0ea09400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $*@4 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@4 +# AUNIT --inst x0ea09400/mask=xffe0fc00 --status pass + +:mla Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x12 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + # simd infix TMPD1 = Rn_VPR64.2S * Rm_VPR64.2S on lane size 4 + TMPD1[0,32] = Rn_VPR64.2S[0,32] * Rm_VPR64.2S[0,32]; + TMPD1[32,32] = Rn_VPR64.2S[32,32] * Rm_VPR64.2S[32,32]; + # simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4 + Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32]; + Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.196 MLA (vector) page C7-2475 line 144975 MATCH x0e209400/mask=xbf20fc00 +# CONSTRUCT x0e609400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $*@2 &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@2 +# AUNIT --inst x0e609400/mask=xffe0fc00 --status pass + +:mla Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x12 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + # simd infix TMPD1 = Rn_VPR64.4H * Rm_VPR64.4H on lane size 2 + TMPD1[0,16] = Rn_VPR64.4H[0,16] * Rm_VPR64.4H[0,16]; + TMPD1[16,16] = Rn_VPR64.4H[16,16] * Rm_VPR64.4H[16,16]; + TMPD1[32,16] = Rn_VPR64.4H[32,16] * Rm_VPR64.4H[32,16]; + TMPD1[48,16] = Rn_VPR64.4H[48,16] * Rm_VPR64.4H[48,16]; + # simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2 + Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16]; + Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16]; + Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16]; + Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.196 MLA (vector) page C7-2475 line 144975 MATCH x0e209400/mask=xbf20fc00 +# CONSTRUCT x4ea09400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $*@4 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@4 +# AUNIT --inst x4ea09400/mask=xffe0fc00 --status pass + +:mla Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x12 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.4S * Rm_VPR128.4S on lane size 4 + TMPQ1[0,32] = Rn_VPR128.4S[0,32] * Rm_VPR128.4S[0,32]; + TMPQ1[32,32] = Rn_VPR128.4S[32,32] * Rm_VPR128.4S[32,32]; + TMPQ1[64,32] = Rn_VPR128.4S[64,32] * Rm_VPR128.4S[64,32]; + TMPQ1[96,32] = Rn_VPR128.4S[96,32] * Rm_VPR128.4S[96,32]; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.196 MLA (vector) page C7-2475 line 144975 MATCH x0e209400/mask=xbf20fc00 +# CONSTRUCT x0e209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $*@1 &=$+@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@1 +# AUNIT --inst x0e209400/mask=xffe0fc00 --status pass + +:mla Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x12 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + # simd infix TMPD1 = Rn_VPR64.8B * Rm_VPR64.8B on lane size 1 + TMPD1[0,8] = Rn_VPR64.8B[0,8] * Rm_VPR64.8B[0,8]; + TMPD1[8,8] = Rn_VPR64.8B[8,8] * Rm_VPR64.8B[8,8]; + TMPD1[16,8] = Rn_VPR64.8B[16,8] * Rm_VPR64.8B[16,8]; + TMPD1[24,8] = Rn_VPR64.8B[24,8] * Rm_VPR64.8B[24,8]; + TMPD1[32,8] = Rn_VPR64.8B[32,8] * Rm_VPR64.8B[32,8]; + TMPD1[40,8] = Rn_VPR64.8B[40,8] * Rm_VPR64.8B[40,8]; + TMPD1[48,8] = Rn_VPR64.8B[48,8] * Rm_VPR64.8B[48,8]; + TMPD1[56,8] = Rn_VPR64.8B[56,8] * Rm_VPR64.8B[56,8]; + # simd infix Rd_VPR64.8B = Rd_VPR64.8B + TMPD1 on lane size 1 + Rd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] + TMPD1[0,8]; + Rd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] + TMPD1[8,8]; + Rd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] + TMPD1[16,8]; + Rd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] + TMPD1[24,8]; + Rd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] + TMPD1[32,8]; + Rd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] + TMPD1[40,8]; + Rd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] + TMPD1[48,8]; + Rd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] + TMPD1[56,8]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.196 MLA (vector) page C7-2475 line 144975 MATCH x0e209400/mask=xbf20fc00 +# CONSTRUCT x4e609400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $*@2 &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@2 +# AUNIT --inst x4e609400/mask=xffe0fc00 --status pass + +:mla Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x12 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.8H * Rm_VPR128.8H on lane size 2 + TMPQ1[0,16] = Rn_VPR128.8H[0,16] * Rm_VPR128.8H[0,16]; + TMPQ1[16,16] = Rn_VPR128.8H[16,16] * Rm_VPR128.8H[16,16]; + TMPQ1[32,16] = Rn_VPR128.8H[32,16] * Rm_VPR128.8H[32,16]; + TMPQ1[48,16] = Rn_VPR128.8H[48,16] * Rm_VPR128.8H[48,16]; + TMPQ1[64,16] = Rn_VPR128.8H[64,16] * Rm_VPR128.8H[64,16]; + TMPQ1[80,16] = Rn_VPR128.8H[80,16] * Rm_VPR128.8H[80,16]; + TMPQ1[96,16] = Rn_VPR128.8H[96,16] * Rm_VPR128.8H[96,16]; + TMPQ1[112,16] = Rn_VPR128.8H[112,16] * Rm_VPR128.8H[112,16]; + # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.197 MLS (by element) page C7-2477 line 145080 MATCH x2f004000/mask=xbf00f400 +# CONSTRUCT x2f804000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $* &=$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@4 +# AUNIT --inst x2f804000/mask=xffc0f400 --status pass + +:mls Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex +is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x4 & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp1:4 = Re_VPR128.S.vIndex; + # simd infix TMPD1 = Rn_VPR64.2S * tmp1 on lane size 4 + TMPD1[0,32] = Rn_VPR64.2S[0,32] * tmp1; + TMPD1[32,32] = Rn_VPR64.2S[32,32] * tmp1; + # simd infix Rd_VPR64.2S = Rd_VPR64.2S - TMPD1 on lane size 4 + Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] - TMPD1[0,32]; + Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] - TMPD1[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.197 MLS (by element) page C7-2477 line 145080 MATCH x2f004000/mask=xbf00f400 +# CONSTRUCT x2f404000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $* &=$-@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@2 +# AUNIT --inst x2f404000/mask=xffc0f400 --status pass + +:mls Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM +is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x4 & b_1010=0 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp1:2 = Re_VPR128Lo.H.vIndexHLM; + # simd infix TMPD1 = Rn_VPR64.4H * tmp1 on lane size 2 + TMPD1[0,16] = Rn_VPR64.4H[0,16] * tmp1; + TMPD1[16,16] = Rn_VPR64.4H[16,16] * tmp1; + TMPD1[32,16] = Rn_VPR64.4H[32,16] * tmp1; + TMPD1[48,16] = Rn_VPR64.4H[48,16] * tmp1; + # simd infix Rd_VPR64.4H = Rd_VPR64.4H - TMPD1 on lane size 2 + Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] - TMPD1[0,16]; + Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] - TMPD1[16,16]; + Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] - TMPD1[32,16]; + Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] - TMPD1[48,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.197 MLS (by element) page C7-2477 line 145080 MATCH x2f004000/mask=xbf00f400 +# CONSTRUCT x6f804000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $* &=$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@4 +# AUNIT --inst x6f804000/mask=xffc0f400 --status pass + +:mls Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex +is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x4 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp1:4 = Re_VPR128.S.vIndex; + # simd infix TMPQ1 = Rn_VPR128.4S * tmp1 on lane size 4 + TMPQ1[0,32] = Rn_VPR128.4S[0,32] * tmp1; + TMPQ1[32,32] = Rn_VPR128.4S[32,32] * tmp1; + TMPQ1[64,32] = Rn_VPR128.4S[64,32] * tmp1; + TMPQ1[96,32] = Rn_VPR128.4S[96,32] * tmp1; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ1 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ1[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ1[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ1[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ1[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.197 MLS (by element) page C7-2477 line 145080 MATCH x2f004000/mask=xbf00f400 +# CONSTRUCT x6f404000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $* &=$-@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@2 +# AUNIT --inst x6f404000/mask=xffc0f400 --status pass + +:mls Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM +is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x4 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp1:2 = Re_VPR128Lo.H.vIndexHLM; + # simd infix TMPQ1 = Rn_VPR128.8H * tmp1 on lane size 2 + TMPQ1[0,16] = Rn_VPR128.8H[0,16] * tmp1; + TMPQ1[16,16] = Rn_VPR128.8H[16,16] * tmp1; + TMPQ1[32,16] = Rn_VPR128.8H[32,16] * tmp1; + TMPQ1[48,16] = Rn_VPR128.8H[48,16] * tmp1; + TMPQ1[64,16] = Rn_VPR128.8H[64,16] * tmp1; + TMPQ1[80,16] = Rn_VPR128.8H[80,16] * tmp1; + TMPQ1[96,16] = Rn_VPR128.8H[96,16] * tmp1; + TMPQ1[112,16] = Rn_VPR128.8H[112,16] * tmp1; + # simd infix Rd_VPR128.8H = Rd_VPR128.8H - TMPQ1 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] - TMPQ1[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] - TMPQ1[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] - TMPQ1[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] - TMPQ1[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] - TMPQ1[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] - TMPQ1[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] - TMPQ1[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] - TMPQ1[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.198 MLS (vector) page C7-2479 line 145213 MATCH x2e209400/mask=xbf20fc00 +# CONSTRUCT x6e209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $*@1 &=$-@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@1 +# AUNIT --inst x6e209400/mask=xffe0fc00 --status pass + +:mls Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x12 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.16B * Rm_VPR128.16B on lane size 1 + TMPQ1[0,8] = Rn_VPR128.16B[0,8] * Rm_VPR128.16B[0,8]; + TMPQ1[8,8] = Rn_VPR128.16B[8,8] * Rm_VPR128.16B[8,8]; + TMPQ1[16,8] = Rn_VPR128.16B[16,8] * Rm_VPR128.16B[16,8]; + TMPQ1[24,8] = Rn_VPR128.16B[24,8] * Rm_VPR128.16B[24,8]; + TMPQ1[32,8] = Rn_VPR128.16B[32,8] * Rm_VPR128.16B[32,8]; + TMPQ1[40,8] = Rn_VPR128.16B[40,8] * Rm_VPR128.16B[40,8]; + TMPQ1[48,8] = Rn_VPR128.16B[48,8] * Rm_VPR128.16B[48,8]; + TMPQ1[56,8] = Rn_VPR128.16B[56,8] * Rm_VPR128.16B[56,8]; + TMPQ1[64,8] = Rn_VPR128.16B[64,8] * Rm_VPR128.16B[64,8]; + TMPQ1[72,8] = Rn_VPR128.16B[72,8] * Rm_VPR128.16B[72,8]; + TMPQ1[80,8] = Rn_VPR128.16B[80,8] * Rm_VPR128.16B[80,8]; + TMPQ1[88,8] = Rn_VPR128.16B[88,8] * Rm_VPR128.16B[88,8]; + TMPQ1[96,8] = Rn_VPR128.16B[96,8] * Rm_VPR128.16B[96,8]; + TMPQ1[104,8] = Rn_VPR128.16B[104,8] * Rm_VPR128.16B[104,8]; + TMPQ1[112,8] = Rn_VPR128.16B[112,8] * Rm_VPR128.16B[112,8]; + TMPQ1[120,8] = Rn_VPR128.16B[120,8] * Rm_VPR128.16B[120,8]; + # simd infix Rd_VPR128.16B = Rd_VPR128.16B - TMPQ1 on lane size 1 + Rd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] - TMPQ1[0,8]; + Rd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] - TMPQ1[8,8]; + Rd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] - TMPQ1[16,8]; + Rd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] - TMPQ1[24,8]; + Rd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] - TMPQ1[32,8]; + Rd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] - TMPQ1[40,8]; + Rd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] - TMPQ1[48,8]; + Rd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] - TMPQ1[56,8]; + Rd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] - TMPQ1[64,8]; + Rd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] - TMPQ1[72,8]; + Rd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] - TMPQ1[80,8]; + Rd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] - TMPQ1[88,8]; + Rd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] - TMPQ1[96,8]; + Rd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] - TMPQ1[104,8]; + Rd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] - TMPQ1[112,8]; + Rd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] - TMPQ1[120,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.198 MLS (vector) page C7-2479 line 145213 MATCH x2e209400/mask=xbf20fc00 +# CONSTRUCT x2ea09400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $*@4 &=$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@4 +# AUNIT --inst x2ea09400/mask=xffe0fc00 --status pass + +:mls Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x12 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + # simd infix TMPD1 = Rn_VPR64.2S * Rm_VPR64.2S on lane size 4 + TMPD1[0,32] = Rn_VPR64.2S[0,32] * Rm_VPR64.2S[0,32]; + TMPD1[32,32] = Rn_VPR64.2S[32,32] * Rm_VPR64.2S[32,32]; + # simd infix Rd_VPR64.2S = Rd_VPR64.2S - TMPD1 on lane size 4 + Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] - TMPD1[0,32]; + Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] - TMPD1[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.198 MLS (vector) page C7-2479 line 145213 MATCH x2e209400/mask=xbf20fc00 +# CONSTRUCT x2e609400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $*@2 &=$-@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@2 +# AUNIT --inst x2e609400/mask=xffe0fc00 --status pass + +:mls Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x12 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + # simd infix TMPD1 = Rn_VPR64.4H * Rm_VPR64.4H on lane size 2 + TMPD1[0,16] = Rn_VPR64.4H[0,16] * Rm_VPR64.4H[0,16]; + TMPD1[16,16] = Rn_VPR64.4H[16,16] * Rm_VPR64.4H[16,16]; + TMPD1[32,16] = Rn_VPR64.4H[32,16] * Rm_VPR64.4H[32,16]; + TMPD1[48,16] = Rn_VPR64.4H[48,16] * Rm_VPR64.4H[48,16]; + # simd infix Rd_VPR64.4H = Rd_VPR64.4H - TMPD1 on lane size 2 + Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] - TMPD1[0,16]; + Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] - TMPD1[16,16]; + Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] - TMPD1[32,16]; + Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] - TMPD1[48,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.198 MLS (vector) page C7-2479 line 145213 MATCH x2e209400/mask=xbf20fc00 +# CONSTRUCT x6ea09400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $*@4 &=$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@4 +# AUNIT --inst x6ea09400/mask=xffe0fc00 --status pass + +:mls Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x12 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.4S * Rm_VPR128.4S on lane size 4 + TMPQ1[0,32] = Rn_VPR128.4S[0,32] * Rm_VPR128.4S[0,32]; + TMPQ1[32,32] = Rn_VPR128.4S[32,32] * Rm_VPR128.4S[32,32]; + TMPQ1[64,32] = Rn_VPR128.4S[64,32] * Rm_VPR128.4S[64,32]; + TMPQ1[96,32] = Rn_VPR128.4S[96,32] * Rm_VPR128.4S[96,32]; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ1 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ1[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ1[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ1[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ1[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.198 MLS (vector) page C7-2479 line 145213 MATCH x2e209400/mask=xbf20fc00 +# CONSTRUCT x2e209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $*@1 &=$-@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@1 +# AUNIT --inst x2e209400/mask=xffe0fc00 --status pass + +:mls Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x12 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + # simd infix TMPD1 = Rn_VPR64.8B * Rm_VPR64.8B on lane size 1 + TMPD1[0,8] = Rn_VPR64.8B[0,8] * Rm_VPR64.8B[0,8]; + TMPD1[8,8] = Rn_VPR64.8B[8,8] * Rm_VPR64.8B[8,8]; + TMPD1[16,8] = Rn_VPR64.8B[16,8] * Rm_VPR64.8B[16,8]; + TMPD1[24,8] = Rn_VPR64.8B[24,8] * Rm_VPR64.8B[24,8]; + TMPD1[32,8] = Rn_VPR64.8B[32,8] * Rm_VPR64.8B[32,8]; + TMPD1[40,8] = Rn_VPR64.8B[40,8] * Rm_VPR64.8B[40,8]; + TMPD1[48,8] = Rn_VPR64.8B[48,8] * Rm_VPR64.8B[48,8]; + TMPD1[56,8] = Rn_VPR64.8B[56,8] * Rm_VPR64.8B[56,8]; + # simd infix Rd_VPR64.8B = Rd_VPR64.8B - TMPD1 on lane size 1 + Rd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] - TMPD1[0,8]; + Rd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] - TMPD1[8,8]; + Rd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] - TMPD1[16,8]; + Rd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] - TMPD1[24,8]; + Rd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] - TMPD1[32,8]; + Rd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] - TMPD1[40,8]; + Rd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] - TMPD1[48,8]; + Rd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] - TMPD1[56,8]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.198 MLS (vector) page C7-2479 line 145213 MATCH x2e209400/mask=xbf20fc00 +# CONSTRUCT x6e609400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $*@2 &=$-@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@2 +# AUNIT --inst x6e609400/mask=xffe0fc00 --status pass + +:mls Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x12 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.8H * Rm_VPR128.8H on lane size 2 + TMPQ1[0,16] = Rn_VPR128.8H[0,16] * Rm_VPR128.8H[0,16]; + TMPQ1[16,16] = Rn_VPR128.8H[16,16] * Rm_VPR128.8H[16,16]; + TMPQ1[32,16] = Rn_VPR128.8H[32,16] * Rm_VPR128.8H[32,16]; + TMPQ1[48,16] = Rn_VPR128.8H[48,16] * Rm_VPR128.8H[48,16]; + TMPQ1[64,16] = Rn_VPR128.8H[64,16] * Rm_VPR128.8H[64,16]; + TMPQ1[80,16] = Rn_VPR128.8H[80,16] * Rm_VPR128.8H[80,16]; + TMPQ1[96,16] = Rn_VPR128.8H[96,16] * Rm_VPR128.8H[96,16]; + TMPQ1[112,16] = Rn_VPR128.8H[112,16] * Rm_VPR128.8H[112,16]; + # simd infix Rd_VPR128.8H = Rd_VPR128.8H - TMPQ1 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] - TMPQ1[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] - TMPQ1[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] - TMPQ1[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] - TMPQ1[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] - TMPQ1[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] - TMPQ1[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] - TMPQ1[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] - TMPQ1[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.200 MOV (element) page C7-2483 line 145410 MATCH x6e000400/mask=xffe08400 +# C7.2.175 INS (element) page C7-2411 line 140892 MATCH x6e000400/mask=xffe08400 +# CONSTRUCT x6e010400/mask=xffe18400 MATCHED 2 DOCUMENTED OPCODES +# SMACRO Rd_VPR128 ARG2 imm_neon_uimm4:1 &=$copy +# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm4:1 &=NEON_mov/3@1 +# AUNIT --inst x6e010400/mask=xffe18400 --status pass + +:mov Rd_VPR128.B.imm_neon_uimm4, Rn_VPR128.B.immN_neon_uimm4 +is b_3131=0 & q=1 & b_29=1 & b_2428=0xe & b_2123=0 & Rd_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & Rn_VPR128.B.immN_neon_uimm4 & immN_neon_uimm4 & b_1010=1 & Rn_VPR128 & Rd_VPR128 & Zd +{ + # simd element Rn_VPR128[immN_neon_uimm4] lane size 1 + local tmp1:1 = Rn_VPR128.B.immN_neon_uimm4; + # simd copy Rd_VPR128 element imm_neon_uimm4:1 = tmp1 (lane size 1) + Rd_VPR128.B.imm_neon_uimm4 = tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.200 MOV (element) page C7-2483 line 145410 MATCH x6e000400/mask=xffe08400 +# C7.2.175 INS (element) page C7-2411 line 140892 MATCH x6e000400/mask=xffe08400 +# CONSTRUCT x6e080400/mask=xffef8400 MATCHED 2 DOCUMENTED OPCODES +# SMACRO Rd_VPR128 ARG2 imm_neon_uimm1:1 &=$copy +# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm1:1 &=NEON_mov/3@8 +# AUNIT --inst x6e080400/mask=xffef8400 --status pass + +:mov Rd_VPR128.D.imm_neon_uimm1, Rn_VPR128.D.immN_neon_uimm1 +is b_3131=0 & q=1 & b_29=1 & b_2428=0xe & b_2123=0 & Rd_VPR128.D.imm_neon_uimm1 & b_1619=0x8 & b_1515=0 & Rn_VPR128.D.immN_neon_uimm1 & immN_neon_uimm1 & Imm4 & b_1010=1 & Rn_VPR128 & Rd_VPR128 & Zd +{ + # simd element Rn_VPR128[immN_neon_uimm1] lane size 8 + local tmp1:8 = Rn_VPR128.D.immN_neon_uimm1; + # simd copy Rd_VPR128 element imm_neon_uimm1:1 = tmp1 (lane size 8) + Rd_VPR128.D.imm_neon_uimm1 = tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.200 MOV (element) page C7-2483 line 145410 MATCH x6e000400/mask=xffe08400 +# C7.2.175 INS (element) page C7-2411 line 140892 MATCH x6e000400/mask=xffe08400 +# CONSTRUCT x6e020400/mask=xffe38400 MATCHED 2 DOCUMENTED OPCODES +# SMACRO Rd_VPR128 ARG2 imm_neon_uimm3:1 &=$copy +# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm3:1 &=NEON_mov/3@2 +# AUNIT --inst x6e020400/mask=xffe38400 --status pass + +:mov Rd_VPR128.H.imm_neon_uimm3, Rn_VPR128.H.immN_neon_uimm3 +is b_3131=0 & q=1 & b_29=1 & b_2428=0xe & b_2123=0 & Rd_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & Rn_VPR128.H.immN_neon_uimm3 & immN_neon_uimm3 & Imm4 & b_1010=1 & Rn_VPR128 & Rd_VPR128 & Zd +{ + # simd element Rn_VPR128[immN_neon_uimm3] lane size 2 + local tmp1:2 = Rn_VPR128.H.immN_neon_uimm3; + # simd copy Rd_VPR128 element imm_neon_uimm3:1 = tmp1 (lane size 2) + Rd_VPR128.H.imm_neon_uimm3 = tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.200 MOV (element) page C7-2483 line 145410 MATCH x6e000400/mask=xffe08400 +# C7.2.175 INS (element) page C7-2411 line 140892 MATCH x6e000400/mask=xffe08400 +# CONSTRUCT x6e040400/mask=xffe78400 MATCHED 2 DOCUMENTED OPCODES +# SMACRO Rd_VPR128 ARG2 imm_neon_uimm2:1 &=$copy +# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm2:1 &=NEON_mov/3@4 +# AUNIT --inst x6e040400/mask=xffe78400 --status pass + +:mov Rd_VPR128.S.imm_neon_uimm2, Rn_VPR128.S.immN_neon_uimm2 +is b_3131=0 & q=1 & b_29=1 & b_2428=0xe & b_2123=0 & Rd_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & Rn_VPR128.S.immN_neon_uimm2 & immN_neon_uimm2 & Imm4 & b_1010=1 & Rn_VPR128 & Rd_VPR128 & Zd +{ + # simd element Rn_VPR128[immN_neon_uimm2] lane size 4 + local tmp1:4 = Rn_VPR128.S.immN_neon_uimm2; + # simd copy Rd_VPR128 element imm_neon_uimm2:1 = tmp1 (lane size 4) + Rd_VPR128.S.imm_neon_uimm2 = tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.201 MOV (from general) page C7-2485 line 145507 MATCH x4e001c00/mask=xffe0fc00 +# C7.2.176 INS (general) page C7-2413 line 141002 MATCH x4e001c00/mask=xffe0fc00 +# CONSTRUCT x4e011c00/mask=xffe1fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO Rd_VPR128 ARG2[0]:1 imm_neon_uimm4:1 &=$copy +# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm4:1 &=NEON_mov/3@1 +# AUNIT --inst x4e011c00/mask=xffe1fc00 --status pass + +:mov Rd_VPR128.B.imm_neon_uimm4, Rn_GPR32 +is b_3131=0 & q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rd_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x3 & b_1010=1 & Rn_GPR32 & Rd_VPR128 & Zd +{ + local tmp1:1 = Rn_GPR32[0,8]; + # simd copy Rd_VPR128 element imm_neon_uimm4:1 = tmp1 (lane size 1) + Rd_VPR128.B.imm_neon_uimm4 = tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.201 MOV (from general) page C7-2485 line 145507 MATCH x4e001c00/mask=xffe0fc00 +# C7.2.176 INS (general) page C7-2413 line 141002 MATCH x4e001c00/mask=xffe0fc00 +# CONSTRUCT x4e081c00/mask=xffeffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO Rd_VPR128 ARG2 imm_neon_uimm1:1 &=$copy +# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm1:1 &=NEON_mov/3@8 +# AUNIT --inst x4e081c00/mask=xffeffc00 --status pass + +:mov Rd_VPR128.D.imm_neon_uimm1, Rn_GPR64 +is b_3131=0 & q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rd_VPR128.D.imm_neon_uimm1 & b_1619=0x8 & b_1515=0 & imm4=0x3 & b_1010=1 & Rn_GPR64 & Rd_VPR128 & Zd +{ + # simd copy Rd_VPR128 element imm_neon_uimm1:1 = Rn_GPR64 (lane size 8) + Rd_VPR128.D.imm_neon_uimm1 = Rn_GPR64; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.201 MOV (from general) page C7-2485 line 145507 MATCH x4e001c00/mask=xffe0fc00 +# C7.2.176 INS (general) page C7-2413 line 141002 MATCH x4e001c00/mask=xffe0fc00 +# CONSTRUCT x4e021c00/mask=xffe3fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO Rd_VPR128 ARG2[0]:2 imm_neon_uimm3:1 &=$copy +# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm3:1 &=NEON_mov/3@2 +# AUNIT --inst x4e021c00/mask=xffe3fc00 --status pass + +:mov Rd_VPR128.H.imm_neon_uimm3, Rn_GPR32 +is b_3131=0 & q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rd_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x3 & b_1010=1 & Rn_GPR32 & Rd_VPR128 & Zd +{ + local tmp1:2 = Rn_GPR32[0,16]; + # simd copy Rd_VPR128 element imm_neon_uimm3:1 = tmp1 (lane size 2) + Rd_VPR128.H.imm_neon_uimm3 = tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.201 MOV (from general) page C7-2485 line 145507 MATCH x4e001c00/mask=xffe0fc00 +# C7.2.176 INS (general) page C7-2413 line 141002 MATCH x4e001c00/mask=xffe0fc00 +# CONSTRUCT x4e041c00/mask=xffe7fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO(force-primitive) Rd_VPR128 ARG2 imm_neon_uimm2:1 &=$copy +# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm2:1 &=NEON_mov/3@2 +# AUNIT --inst x4e041c00/mask=xffe7fc00 --status pass + +:mov Rd_VPR128.S.imm_neon_uimm2, Rn_GPR32 +is b_3131=0 & q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rd_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & imm4=0x3 & b_1010=1 & Rn_GPR32 & Rd_VPR128 & Zd +{ + # simd copy Rd_VPR128 element imm_neon_uimm2:1 = Rn_GPR32 (lane size 4) + Rd_VPR128.S.imm_neon_uimm2 = Rn_GPR32; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.202 MOV (vector) page C7-2487 line 145604 MATCH x0ea01c00/mask=xbfe0fc00 +# C7.2.213 ORR (vector, register) page C7-2509 line 146837 MATCH x0ea01c00/mask=xbfe0fc00 +# CONSTRUCT x4ea01c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 = +# SMACRO(pseudo) ARG1 ARG2 =NEON_mov/1@1 +# AUNIT --inst x4ea01c00/mask=xffe0fc00 --status pass + +:mov Rd_VPR128.16B, Rn_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Rn=Rm & Zd +{ + Rd_VPR128.16B = Rn_VPR128.16B; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.202 MOV (vector) page C7-2487 line 145604 MATCH x0ea01c00/mask=xbfe0fc00 +# C7.2.213 ORR (vector, register) page C7-2509 line 146837 MATCH x0ea01c00/mask=xbfe0fc00 +# CONSTRUCT x0ea01c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 = +# SMACRO(pseudo) ARG1 ARG2 =NEON_mov/1@1 +# AUNIT --inst x0ea01c00/mask=xffe0fc00 --status pass + +:mov Rd_VPR64.8B, Rn_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Rn=Rm & Zd +{ + Rd_VPR64.8B = Rn_VPR64.8B; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.203 MOV (to general) page C7-2488 line 145671 MATCH x0e003c00/mask=xbfe3fc00 +# C7.2.371 UMOV page C7-2868 line 167415 MATCH x0e003c00/mask=xbfe0fc00 +# CONSTRUCT x0e043c00/mask=xffe7fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO(force-primitive) ARG1 ARG2 = +# SMACRO(pseudo) ARG1 ARG2 =NEON_mov/1@4 +# AUNIT --inst x0e043c00/mask=xffe7fc00 --status pass + +:mov Rd_GPR32, Rn_VPR128.S.imm_neon_uimm2 +is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & imm4=0x7 & b_1010=1 & Rn_VPR128 & Rd_GPR32 & Rd_GPR64 & Rd_VPR128 +{ + # simd element Rn_VPR128[imm_neon_uimm2] lane size 4 + local tmp1:4 = Rn_VPR128.S.imm_neon_uimm2; + Rd_GPR32 = tmp1; + zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64 +} + +# C7.2.203 MOV (to general) page C7-2488 line 145671 MATCH x0e003c00/mask=xbfe3fc00 +# C7.2.371 UMOV page C7-2868 line 167415 MATCH x0e003c00/mask=xbfe0fc00 +# CONSTRUCT x4e083c00/mask=xffeffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 = +# SMACRO(pseudo) ARG1 ARG2 =NEON_mov/1@8 +# AUNIT --inst x4e083c00/mask=xffeffc00 --status pass + +:mov Rd_GPR64, Rn_VPR128.D.imm_neon_uimm1 +is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.D.imm_neon_uimm1 & b_1619=0x8 & b_1515=0 & imm4=0x7 & b_1010=1 & Rn_VPR128 & Rd_GPR64 +{ + # simd element Rn_VPR128[imm_neon_uimm1] lane size 8 + local tmp1:8 = Rn_VPR128.D.imm_neon_uimm1; + Rd_GPR64 = tmp1; +} + +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00 +# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x2f00e400/mask=xbf80fc00 +# CONSTRUCT x2f00e400/mask=xfff8fc00 MATCHED 3 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 = +# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1 +# AUNIT --inst x2f00e400/mask=xfff8fc00 --status pass +# MOVI 64-bit scalar variant when datasize=64 q == 0 && op == 1 && cmode == 1110 + +:movi Rd_FPR64, Imm_neon_uimm8Shift +is b_31=0 & b_30=0 & b_29=1 & b_1928=0b0111100000 & b_1215=0b1110 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_FPR64 & Zd +{ + Rd_FPR64 = Imm_neon_uimm8Shift:8; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x0f00e400/mask=xbf80fc00 +# CONSTRUCT x4f00e400/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2:1 &=$dup +# SMACRO(pseudo) ARG1 ARG2:1 =NEON_movi/1@1 +# AUNIT --inst x4f00e400/mask=xfff8fc00 --status pass +# MOVI 8-bit variant when datasize=128 q == 1 && op == 0 && cmode == 0b1110 + +:movi Rd_VPR128.16B, Imm_neon_uimm8Shift +is b_31=0 & b_30=1 & b_29=0 & b_1928=0b0111100000 & b_1215=0b1110 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR128.16B & Zd +{ + # simd duplicate Rd_VPR128.16B = all elements Imm_neon_uimm8Shift:1 (lane size 1) + Rd_VPR128.16B[0,8] = Imm_neon_uimm8Shift:1; + Rd_VPR128.16B[8,8] = Imm_neon_uimm8Shift:1; + Rd_VPR128.16B[16,8] = Imm_neon_uimm8Shift:1; + Rd_VPR128.16B[24,8] = Imm_neon_uimm8Shift:1; + Rd_VPR128.16B[32,8] = Imm_neon_uimm8Shift:1; + Rd_VPR128.16B[40,8] = Imm_neon_uimm8Shift:1; + Rd_VPR128.16B[48,8] = Imm_neon_uimm8Shift:1; + Rd_VPR128.16B[56,8] = Imm_neon_uimm8Shift:1; + Rd_VPR128.16B[64,8] = Imm_neon_uimm8Shift:1; + Rd_VPR128.16B[72,8] = Imm_neon_uimm8Shift:1; + Rd_VPR128.16B[80,8] = Imm_neon_uimm8Shift:1; + Rd_VPR128.16B[88,8] = Imm_neon_uimm8Shift:1; + Rd_VPR128.16B[96,8] = Imm_neon_uimm8Shift:1; + Rd_VPR128.16B[104,8] = Imm_neon_uimm8Shift:1; + Rd_VPR128.16B[112,8] = Imm_neon_uimm8Shift:1; + Rd_VPR128.16B[120,8] = Imm_neon_uimm8Shift:1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00 +# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x2f00e400/mask=xbf80fc00 +# CONSTRUCT x6f00e400/mask=xfff8fc00 MATCHED 3 DOCUMENTED OPCODES +# SMACRO(force-primitive) ARG1 ARG2 =var:8 &=$dup +# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@8 +# AUNIT --inst x6f00e400/mask=xfff8fc00 --status pass +# MOVI 64-bit vector variant when datasize=128 q == 1 && op == 1 && cmode == 1110 + +:movi Rd_VPR128.2D, Imm_neon_uimm8Shift +is b_31=0 & b_30=1 & b_29=1 & b_1928=0b0111100000 & b_1215=0b1110 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR128.2D & Zd +{ + local tmp1:8 = Imm_neon_uimm8Shift; + # simd duplicate Rd_VPR128.2D = all elements tmp1 (lane size 8) + Rd_VPR128.2D[0,64] = tmp1; + Rd_VPR128.2D[64,64] = tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x0f00e400/mask=xbf80fc00 +# CONSTRUCT x0f00e400/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 = +# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@1 +# AUNIT --inst x0f00e400/mask=xfff8fc00 --status pass +# MOVI 8-bit variant when datasize=64 q == 0 && op == 0 && cmode == 1110 + +:movi Rd_VPR64.8B, Imm_neon_uimm8Shift +is b_31=0 & b_30=0 & b_29=0 & b_1928=0b0111100000 & b_1215=0b1110 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = Imm_neon_uimm8Shift:8; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00 +# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00 +# CONSTRUCT x0f000400/mask=xfff89c00 MATCHED 3 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 = +# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@4 +# AUNIT --inst x0f000400/mask=xfff89c00 --status pass +# MOVI 32-bit shifted immediate variant when datasize=64 q == 0 && op == 0 && cmode == 0xx0 + +:movi Rd_VPR64.2S, Imm_neon_uimm8Shift +is b_31=0 & b_30=0 & b_29=0 & b_1928=0b0111100000 & b_15=0 & b_12=0 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = Imm_neon_uimm8Shift:8; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.256 SHRN, SHRN2 page C7-2587 line 151244 MATCH x0f008400/mask=xbf80fc00 +# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00 +# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00 +# CONSTRUCT x0f008400/mask=xfff8dc00 MATCHED 4 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 = +# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@2 +# AUNIT --inst x0f008400/mask=xfff8dc00 --status pass +# MOVI 16-bit shifted immediate variant when datasize=64 q == 0 && op == 0 && cmode == 10x0 + +:movi Rd_VPR64.4H, Imm_neon_uimm8Shift +is b_31=0 & b_30=0 & b_29=0 & b_1928=0b0111100000 & b_1415=0b10 & b_12=0 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = Imm_neon_uimm8Shift:8; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00 +# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00 +# CONSTRUCT x4f000400/mask=xfff89c00 MATCHED 3 DOCUMENTED OPCODES +# SMACRO(force-primitive) ARG1 ARG2:4 &=$dup +# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@4 +# AUNIT --inst x4f000400/mask=xfff89c00 --status pass +# MOVI 32-bit shifted immediate variant when datasize=128 q == 1 && op == 0 && cmode == 0xx0 + +:movi Rd_VPR128.4S, Imm_neon_uimm8Shift +is b_31=0 & b_30=1 & b_29=0 & b_1928=0b0111100000 & b_15=0 & b_12=0 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR128.4S & Zd +{ + # simd duplicate Rd_VPR128.4S = all elements Imm_neon_uimm8Shift:4 (lane size 4) + Rd_VPR128.4S[0,32] = Imm_neon_uimm8Shift:4; + Rd_VPR128.4S[32,32] = Imm_neon_uimm8Shift:4; + Rd_VPR128.4S[64,32] = Imm_neon_uimm8Shift:4; + Rd_VPR128.4S[96,32] = Imm_neon_uimm8Shift:4; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.256 SHRN, SHRN2 page C7-2587 line 151244 MATCH x0f008400/mask=xbf80fc00 +# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00 +# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00 +# CONSTRUCT x4f008400/mask=xfff8dc00 MATCHED 4 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2:2 &=$dup +# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@2 +# AUNIT --inst x4f008400/mask=xfff8dc00 --status pass +# MOVI 16-bit shifted immediate variant when datasize=128 q == 1 && op == 0 && cmode == 10x0 + +:movi Rd_VPR128.8H, Imm_neon_uimm8Shift +is b_31=0 & b_30=1 & b_29=0 & b_1928=0b0111100000 & b_1415=0b10 & b_12=0 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR128.8H & Zd +{ + # simd duplicate Rd_VPR128.8H = all elements Imm_neon_uimm8Shift:2 (lane size 2) + Rd_VPR128.8H[0,16] = Imm_neon_uimm8Shift:2; + Rd_VPR128.8H[16,16] = Imm_neon_uimm8Shift:2; + Rd_VPR128.8H[32,16] = Imm_neon_uimm8Shift:2; + Rd_VPR128.8H[48,16] = Imm_neon_uimm8Shift:2; + Rd_VPR128.8H[64,16] = Imm_neon_uimm8Shift:2; + Rd_VPR128.8H[80,16] = Imm_neon_uimm8Shift:2; + Rd_VPR128.8H[96,16] = Imm_neon_uimm8Shift:2; + Rd_VPR128.8H[112,16] = Imm_neon_uimm8Shift:2; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.212 ORR (vector, immediate) page C7-2507 line 146708 MATCH x0f001400/mask=xbff81c00 +# CONSTRUCT x0f00c400/mask=xfff8ec00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 = +# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@4 +# AUNIT --inst x0f00c400/mask=xfff8ec00 --status pass +# MOVI 32-bit shifting ones variant when datasize=64 q == 0 && op == 0 && cmode == 110x + +:movi Rd_VPR64.2S, Imm_neon_uimm8Shift +is b_31=0 & b_30=0 & b_29=0 & b_1928=0b0111100000 & b_1315=0b110 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = Imm_neon_uimm8Shift:8; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.212 ORR (vector, immediate) page C7-2507 line 146708 MATCH x0f001400/mask=xbff81c00 +# CONSTRUCT x4f00c400/mask=xfff8ec00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2:4 &=$dup +# SMACRO(pseudo) ARG1 ARG2:4 =NEON_movi/1@4 +# AUNIT --inst x4f00c400/mask=xfff8ec00 --status pass +# MOVI 32-bit shifting ones variant when datasize=128 q == 1 && op == 0 && cmode == 110x + +:movi Rd_VPR128.4S, Imm_neon_uimm8Shift +is b_31=0 & b_30=1 & b_29=0 & b_1928=0b0111100000 & b_1315=0b110 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR128.4S & Zd +{ + # simd duplicate Rd_VPR128.4S = all elements Imm_neon_uimm8Shift:4 (lane size 4) + Rd_VPR128.4S[0,32] = Imm_neon_uimm8Shift:4; + Rd_VPR128.4S[32,32] = Imm_neon_uimm8Shift:4; + Rd_VPR128.4S[64,32] = Imm_neon_uimm8Shift:4; + Rd_VPR128.4S[96,32] = Imm_neon_uimm8Shift:4; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.205 MUL (by element) page C7-2493 line 145949 MATCH x0f008000/mask=xbf00f400 +# CONSTRUCT x0f808000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@4 +# AUNIT --inst x0f808000/mask=xffc0f400 --status pass + +:mul Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex +is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x8 & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp1:4 = Re_VPR128.S.vIndex; + # simd infix Rd_VPR64.2S = Rn_VPR64.2S * tmp1 on lane size 4 + Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] * tmp1; + Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] * tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.205 MUL (by element) page C7-2493 line 145949 MATCH x0f008000/mask=xbf00f400 +# CONSTRUCT x0f408000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@2 +# AUNIT --inst x0f408000/mask=xffc0f400 --status pass + +:mul Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM +is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x8 & b_1010=0 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp1:2 = Re_VPR128Lo.H.vIndexHLM; + # simd infix Rd_VPR64.4H = Rn_VPR64.4H * tmp1 on lane size 2 + Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] * tmp1; + Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] * tmp1; + Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] * tmp1; + Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] * tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.205 MUL (by element) page C7-2493 line 145949 MATCH x0f008000/mask=xbf00f400 +# CONSTRUCT x4f808000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(force-primitive) ARG1 ARG2 ARG3 =$* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@4 +# AUNIT --inst x4f808000/mask=xffc0f400 --status pass + +:mul Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex +is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x8 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp1:4 = Re_VPR128.S.vIndex; + # simd infix Rd_VPR128.4S = Rn_VPR128.4S * tmp1 on lane size 4 + Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] * tmp1; + Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] * tmp1; + Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] * tmp1; + Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] * tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.205 MUL (by element) page C7-2493 line 145949 MATCH x0f008000/mask=xbf00f400 +# CONSTRUCT x4f408000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@2 +# AUNIT --inst x4f408000/mask=xffc0f400 --status pass + +:mul Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM +is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x8 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp1:2 = Re_VPR128Lo.H.vIndexHLM; + # simd infix Rd_VPR128.8H = Rn_VPR128.8H * tmp1 on lane size 2 + Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] * tmp1; + Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] * tmp1; + Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] * tmp1; + Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] * tmp1; + Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] * tmp1; + Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] * tmp1; + Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] * tmp1; + Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] * tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.206 MUL (vector) page C7-2495 line 146079 MATCH x0e209c00/mask=xbf20fc00 +# CONSTRUCT x4e209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$*@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@1 +# AUNIT --inst x4e209c00/mask=xffe0fc00 --status pass + +:mul Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x13 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + # simd infix Rd_VPR128.16B = Rn_VPR128.16B * Rm_VPR128.16B on lane size 1 + Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] * Rm_VPR128.16B[0,8]; + Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] * Rm_VPR128.16B[8,8]; + Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] * Rm_VPR128.16B[16,8]; + Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] * Rm_VPR128.16B[24,8]; + Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] * Rm_VPR128.16B[32,8]; + Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] * Rm_VPR128.16B[40,8]; + Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] * Rm_VPR128.16B[48,8]; + Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] * Rm_VPR128.16B[56,8]; + Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] * Rm_VPR128.16B[64,8]; + Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] * Rm_VPR128.16B[72,8]; + Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] * Rm_VPR128.16B[80,8]; + Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] * Rm_VPR128.16B[88,8]; + Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] * Rm_VPR128.16B[96,8]; + Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] * Rm_VPR128.16B[104,8]; + Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] * Rm_VPR128.16B[112,8]; + Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] * Rm_VPR128.16B[120,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.206 MUL (vector) page C7-2495 line 146079 MATCH x0e209c00/mask=xbf20fc00 +# CONSTRUCT x0ea09c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$*@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@4 +# AUNIT --inst x0ea09c00/mask=xffe0fc00 --status pass + +:mul Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x13 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + # simd infix Rd_VPR64.2S = Rn_VPR64.2S * Rm_VPR64.2S on lane size 4 + Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] * Rm_VPR64.2S[0,32]; + Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] * Rm_VPR64.2S[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.206 MUL (vector) page C7-2495 line 146079 MATCH x0e209c00/mask=xbf20fc00 +# CONSTRUCT x0e609c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$*@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@2 +# AUNIT --inst x0e609c00/mask=xffe0fc00 --status pass + +:mul Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x13 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + # simd infix Rd_VPR64.4H = Rn_VPR64.4H * Rm_VPR64.4H on lane size 2 + Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] * Rm_VPR64.4H[0,16]; + Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] * Rm_VPR64.4H[16,16]; + Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] * Rm_VPR64.4H[32,16]; + Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] * Rm_VPR64.4H[48,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.206 MUL (vector) page C7-2495 line 146079 MATCH x0e209c00/mask=xbf20fc00 +# CONSTRUCT x4ea09c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$*@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@4 +# AUNIT --inst x4ea09c00/mask=xffe0fc00 --status pass + +:mul Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x13 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd infix Rd_VPR128.4S = Rn_VPR128.4S * Rm_VPR128.4S on lane size 4 + Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] * Rm_VPR128.4S[0,32]; + Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] * Rm_VPR128.4S[32,32]; + Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] * Rm_VPR128.4S[64,32]; + Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] * Rm_VPR128.4S[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.206 MUL (vector) page C7-2495 line 146079 MATCH x0e209c00/mask=xbf20fc00 +# CONSTRUCT x0e209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$*@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@1 +# AUNIT --inst x0e209c00/mask=xffe0fc00 --status pass + +:mul Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x13 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + # simd infix Rd_VPR64.8B = Rn_VPR64.8B * Rm_VPR64.8B on lane size 1 + Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] * Rm_VPR64.8B[0,8]; + Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] * Rm_VPR64.8B[8,8]; + Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] * Rm_VPR64.8B[16,8]; + Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] * Rm_VPR64.8B[24,8]; + Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] * Rm_VPR64.8B[32,8]; + Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] * Rm_VPR64.8B[40,8]; + Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] * Rm_VPR64.8B[48,8]; + Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] * Rm_VPR64.8B[56,8]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.206 MUL (vector) page C7-2495 line 146079 MATCH x0e209c00/mask=xbf20fc00 +# CONSTRUCT x4e609c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$*@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@2 +# AUNIT --inst x4e609c00/mask=xffe0fc00 --status pass + +:mul Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x13 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + # simd infix Rd_VPR128.8H = Rn_VPR128.8H * Rm_VPR128.8H on lane size 2 + Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] * Rm_VPR128.8H[0,16]; + Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] * Rm_VPR128.8H[16,16]; + Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] * Rm_VPR128.8H[32,16]; + Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] * Rm_VPR128.8H[48,16]; + Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] * Rm_VPR128.8H[64,16]; + Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] * Rm_VPR128.8H[80,16]; + Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] * Rm_VPR128.8H[96,16]; + Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] * Rm_VPR128.8H[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.207 MVN page C7-2497 line 146183 MATCH x2e205800/mask=xbffffc00 +# C7.2.210 NOT page C7-2503 line 146536 MATCH x2e205800/mask=xbffffc00 +# CONSTRUCT x6e205800/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$~@1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_mvn/1@1 +# AUNIT --inst x6e205800/mask=xfffffc00 --status pass + +:mvn Rd_VPR128.16B, Rn_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=16 & b_1216=5 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + # simd unary Rd_VPR128.16B = ~(Rn_VPR128.16B) on lane size 1 + Rd_VPR128.16B[0,8] = ~(Rn_VPR128.16B[0,8]); + Rd_VPR128.16B[8,8] = ~(Rn_VPR128.16B[8,8]); + Rd_VPR128.16B[16,8] = ~(Rn_VPR128.16B[16,8]); + Rd_VPR128.16B[24,8] = ~(Rn_VPR128.16B[24,8]); + Rd_VPR128.16B[32,8] = ~(Rn_VPR128.16B[32,8]); + Rd_VPR128.16B[40,8] = ~(Rn_VPR128.16B[40,8]); + Rd_VPR128.16B[48,8] = ~(Rn_VPR128.16B[48,8]); + Rd_VPR128.16B[56,8] = ~(Rn_VPR128.16B[56,8]); + Rd_VPR128.16B[64,8] = ~(Rn_VPR128.16B[64,8]); + Rd_VPR128.16B[72,8] = ~(Rn_VPR128.16B[72,8]); + Rd_VPR128.16B[80,8] = ~(Rn_VPR128.16B[80,8]); + Rd_VPR128.16B[88,8] = ~(Rn_VPR128.16B[88,8]); + Rd_VPR128.16B[96,8] = ~(Rn_VPR128.16B[96,8]); + Rd_VPR128.16B[104,8] = ~(Rn_VPR128.16B[104,8]); + Rd_VPR128.16B[112,8] = ~(Rn_VPR128.16B[112,8]); + Rd_VPR128.16B[120,8] = ~(Rn_VPR128.16B[120,8]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.207 MVN page C7-2497 line 146183 MATCH x2e205800/mask=xbffffc00 +# C7.2.210 NOT page C7-2503 line 146536 MATCH x2e205800/mask=xbffffc00 +# CONSTRUCT x2e205800/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$~@1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_mvn/1@1 +# AUNIT --inst x2e205800/mask=xfffffc00 --status pass + +:mvn Rd_VPR64.8B, Rn_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=16 & b_1216=5 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + # simd unary Rd_VPR64.8B = ~(Rn_VPR64.8B) on lane size 1 + Rd_VPR64.8B[0,8] = ~(Rn_VPR64.8B[0,8]); + Rd_VPR64.8B[8,8] = ~(Rn_VPR64.8B[8,8]); + Rd_VPR64.8B[16,8] = ~(Rn_VPR64.8B[16,8]); + Rd_VPR64.8B[24,8] = ~(Rn_VPR64.8B[24,8]); + Rd_VPR64.8B[32,8] = ~(Rn_VPR64.8B[32,8]); + Rd_VPR64.8B[40,8] = ~(Rn_VPR64.8B[40,8]); + Rd_VPR64.8B[48,8] = ~(Rn_VPR64.8B[48,8]); + Rd_VPR64.8B[56,8] = ~(Rn_VPR64.8B[56,8]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00 +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00 +# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00 +# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00 +# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00 +# CONSTRUCT x2f000400/mask=xfff89c00 MATCHED 6 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2:4 ~ &=$dup +# SMACRO(pseudo) ARG1 ARG2:4 =NEON_mvni/1@4 +# AUNIT --inst x2f000400/mask=xfff89c00 --status pass + +:mvni Rd_VPR64.2S, Imm_neon_uimm8Shift +is b_3131=0 & q=0 & b_29=1 & b_2428=0xf & b_1923=0x0 & b_1515=0 & Imm_neon_uimm8Shift & b_1012=1 & Rd_VPR64.2S & Zd +{ + local tmp1:4 = ~ Imm_neon_uimm8Shift:4; + # simd duplicate Rd_VPR64.2S = all elements tmp1 (lane size 4) + Rd_VPR64.2S[0,32] = tmp1; + Rd_VPR64.2S[32,32] = tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00 +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x2f008400/mask=xbf80fc00 +# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00 +# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00 +# CONSTRUCT x2f008400/mask=xfff8dc00 MATCHED 5 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2:2 ~ &=$dup +# SMACRO(pseudo) ARG1 ARG2:2 =NEON_mvni/1@2 +# AUNIT --inst x2f008400/mask=xfff8dc00 --status pass + +:mvni Rd_VPR64.4H, Imm_neon_uimm8Shift +is b_3131=0 & q=0 & b_29=1 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1415=2 & b_1012=1 & Rd_VPR64.4H & Zd +{ + local tmp1:2 = ~ Imm_neon_uimm8Shift:2; + # simd duplicate Rd_VPR64.4H = all elements tmp1 (lane size 2) + Rd_VPR64.4H[0,16] = tmp1; + Rd_VPR64.4H[16,16] = tmp1; + Rd_VPR64.4H[32,16] = tmp1; + Rd_VPR64.4H[48,16] = tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00 +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00 +# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00 +# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00 +# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00 +# CONSTRUCT x6f000400/mask=xfff89c00 MATCHED 6 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2:4 ~ &=$dup +# SMACRO(pseudo) ARG1 ARG2:4 =NEON_mvni/1@4 +# AUNIT --inst x6f000400/mask=xfff89c00 --status pass + +:mvni Rd_VPR128.4S, Imm_neon_uimm8Shift +is b_3131=0 & q=1 & b_29=1 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1515=0 & b_1012=1 & Rd_VPR128.4S & Zd +{ + local tmp1:4 = ~ Imm_neon_uimm8Shift:4; + # simd duplicate Rd_VPR128.4S = all elements tmp1 (lane size 4) + Rd_VPR128.4S[0,32] = tmp1; + Rd_VPR128.4S[32,32] = tmp1; + Rd_VPR128.4S[64,32] = tmp1; + Rd_VPR128.4S[96,32] = tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00 +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x2f008400/mask=xbf80fc00 +# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00 +# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00 +# CONSTRUCT x6f008400/mask=xfff8dc00 MATCHED 5 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2:2 ~ &=$dup +# SMACRO(pseudo) ARG1 ARG2:2 =NEON_mvni/1@2 +# AUNIT --inst x6f008400/mask=xfff8dc00 --status pass + +:mvni Rd_VPR128.8H, Imm_neon_uimm8Shift +is b_3131=0 & q=1 & b_29=1 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1415=2 & b_1012=1 & Rd_VPR128.8H & Zd +{ + local tmp1:2 = ~ Imm_neon_uimm8Shift:2; + # simd duplicate Rd_VPR128.8H = all elements tmp1 (lane size 2) + Rd_VPR128.8H[0,16] = tmp1; + Rd_VPR128.8H[16,16] = tmp1; + Rd_VPR128.8H[32,16] = tmp1; + Rd_VPR128.8H[48,16] = tmp1; + Rd_VPR128.8H[64,16] = tmp1; + Rd_VPR128.8H[80,16] = tmp1; + Rd_VPR128.8H[96,16] = tmp1; + Rd_VPR128.8H[112,16] = tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00 +# C7.2.20 BIC (vector, immediate) page C7-2048 line 119572 MATCH x2f001400/mask=xbff81c00 +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# CONSTRUCT x2f00c400/mask=xfff8ec00 MATCHED 3 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2:4 ~ &=$dup +# SMACRO(pseudo) ARG1 ARG2:4 =NEON_mvni/1@4 +# AUNIT --inst x2f00c400/mask=xfff8ec00 --status pass + +:mvni Rd_VPR64.2S, Imm_neon_uimm8Shift +is b_3131=0 & q=0 & b_29=1 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1315=6 & b_1011=1 & Rd_VPR64.2S & Zd +{ + local tmp1:4 = ~ Imm_neon_uimm8Shift:4; + # simd duplicate Rd_VPR64.2S = all elements tmp1 (lane size 4) + Rd_VPR64.2S[0,32] = tmp1; + Rd_VPR64.2S[32,32] = tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00 +# C7.2.20 BIC (vector, immediate) page C7-2048 line 119572 MATCH x2f001400/mask=xbff81c00 +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# CONSTRUCT x6f00c400/mask=xfff8ec00 MATCHED 3 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2:4 ~ &=$dup +# SMACRO(pseudo) ARG1 ARG2:4 =NEON_mvni/1@4 +# AUNIT --inst x6f00c400/mask=xfff8ec00 --status pass + +:mvni Rd_VPR128.4S, Imm_neon_uimm8Shift +is b_3131=0 & q=1 & b_29=1 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1315=6 & b_1011=1 & Rd_VPR128.4S & Zd +{ + local tmp1:4 = ~ Imm_neon_uimm8Shift:4; + # simd duplicate Rd_VPR128.4S = all elements tmp1 (lane size 4) + Rd_VPR128.4S[0,32] = tmp1; + Rd_VPR128.4S[32,32] = tmp1; + Rd_VPR128.4S[64,32] = tmp1; + Rd_VPR128.4S[96,32] = tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.209 NEG (vector) page C7-2501 line 146404 MATCH x7e20b800/mask=xff3ffc00 +# CONSTRUCT x7ee0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =2comp +# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1 +# AUNIT --inst x7ee0b800/mask=xfffffc00 --status pass + +:neg Rd_VPR64, Rn_VPR64 +is b_3131=0 & q=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR64 & Rd_VPR64 & Zd +{ + Rd_VPR64 = - Rn_VPR64; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.209 NEG (vector) page C7-2501 line 146404 MATCH x2e20b800/mask=xbf3ffc00 +# CONSTRUCT x2e20b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@1 +# AUNIT --inst x2e20b800/mask=xfffffc00 --status nopcodeop + +:neg Rd_VPR64.8B, Rn_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_neg(Rn_VPR64.8B, 1:1); +} + +# C7.2.209 NEG (vector) page C7-2501 line 146404 MATCH x2e20b800/mask=xbf3ffc00 +# CONSTRUCT x6e20b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@1 +# AUNIT --inst x6e20b800/mask=xfffffc00 --status nopcodeop + +:neg Rd_VPR128.16B, Rn_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_neg(Rn_VPR128.16B, 1:1); +} + +# C7.2.209 NEG (vector) page C7-2501 line 146404 MATCH x2e20b800/mask=xbf3ffc00 +# CONSTRUCT x2e60b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@2 +# AUNIT --inst x2e60b800/mask=xfffffc00 --status nopcodeop + +:neg Rd_VPR64.4H, Rn_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_neg(Rn_VPR64.4H, 2:1); +} + +# C7.2.209 NEG (vector) page C7-2501 line 146404 MATCH x2e20b800/mask=xbf3ffc00 +# CONSTRUCT x6e60b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@2 +# AUNIT --inst x6e60b800/mask=xfffffc00 --status nopcodeop + +:neg Rd_VPR128.8H, Rn_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_neg(Rn_VPR128.8H, 2:1); +} + +# C7.2.209 NEG (vector) page C7-2501 line 146404 MATCH x2e20b800/mask=xbf3ffc00 +# CONSTRUCT x2ea0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@4 +# AUNIT --inst x2ea0b800/mask=xfffffc00 --status nopcodeop + +:neg Rd_VPR64.2S, Rn_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_neg(Rn_VPR64.2S, 4:1); +} + +# C7.2.209 NEG (vector) page C7-2501 line 146404 MATCH x2e20b800/mask=xbf3ffc00 +# CONSTRUCT x6ea0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@4 +# AUNIT --inst x6ea0b800/mask=xfffffc00 --status nopcodeop + +:neg Rd_VPR128.4S, Rn_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_neg(Rn_VPR128.4S, 4:1); +} + +# C7.2.209 NEG (vector) page C7-2501 line 146404 MATCH x2e20b800/mask=xbf3ffc00 +# CONSTRUCT x6ee0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@8 +# AUNIT --inst x6ee0b800/mask=xfffffc00 --status nopcodeop + +:neg Rd_VPR128.2D, Rn_VPR128.2D +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_neg(Rn_VPR128.2D, 8:1); +} + +# C7.2.211 ORN (vector) page C7-2505 line 146624 MATCH x0ee01c00/mask=xbfe0fc00 +# CONSTRUCT x4ee01c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $~@1 =$|@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_orn/2@1 +# AUNIT --inst x4ee01c00/mask=xffe0fc00 --status pass + +:orn Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + # simd unary TMPQ1 = ~(Rm_VPR128.16B) on lane size 1 + TMPQ1[0,8] = ~(Rm_VPR128.16B[0,8]); + TMPQ1[8,8] = ~(Rm_VPR128.16B[8,8]); + TMPQ1[16,8] = ~(Rm_VPR128.16B[16,8]); + TMPQ1[24,8] = ~(Rm_VPR128.16B[24,8]); + TMPQ1[32,8] = ~(Rm_VPR128.16B[32,8]); + TMPQ1[40,8] = ~(Rm_VPR128.16B[40,8]); + TMPQ1[48,8] = ~(Rm_VPR128.16B[48,8]); + TMPQ1[56,8] = ~(Rm_VPR128.16B[56,8]); + TMPQ1[64,8] = ~(Rm_VPR128.16B[64,8]); + TMPQ1[72,8] = ~(Rm_VPR128.16B[72,8]); + TMPQ1[80,8] = ~(Rm_VPR128.16B[80,8]); + TMPQ1[88,8] = ~(Rm_VPR128.16B[88,8]); + TMPQ1[96,8] = ~(Rm_VPR128.16B[96,8]); + TMPQ1[104,8] = ~(Rm_VPR128.16B[104,8]); + TMPQ1[112,8] = ~(Rm_VPR128.16B[112,8]); + TMPQ1[120,8] = ~(Rm_VPR128.16B[120,8]); + # simd infix Rd_VPR128.16B = Rn_VPR128.16B | TMPQ1 on lane size 1 + Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] | TMPQ1[0,8]; + Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] | TMPQ1[8,8]; + Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] | TMPQ1[16,8]; + Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] | TMPQ1[24,8]; + Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] | TMPQ1[32,8]; + Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] | TMPQ1[40,8]; + Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] | TMPQ1[48,8]; + Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] | TMPQ1[56,8]; + Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] | TMPQ1[64,8]; + Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] | TMPQ1[72,8]; + Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] | TMPQ1[80,8]; + Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] | TMPQ1[88,8]; + Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] | TMPQ1[96,8]; + Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] | TMPQ1[104,8]; + Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] | TMPQ1[112,8]; + Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] | TMPQ1[120,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.211 ORN (vector) page C7-2505 line 146624 MATCH x0ee01c00/mask=xbfe0fc00 +# CONSTRUCT x0ee01c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $~@1 =$|@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_orn/2@1 +# AUNIT --inst x0ee01c00/mask=xffe0fc00 --status pass + +:orn Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + # simd unary TMPD1 = ~(Rm_VPR64.8B) on lane size 1 + TMPD1[0,8] = ~(Rm_VPR64.8B[0,8]); + TMPD1[8,8] = ~(Rm_VPR64.8B[8,8]); + TMPD1[16,8] = ~(Rm_VPR64.8B[16,8]); + TMPD1[24,8] = ~(Rm_VPR64.8B[24,8]); + TMPD1[32,8] = ~(Rm_VPR64.8B[32,8]); + TMPD1[40,8] = ~(Rm_VPR64.8B[40,8]); + TMPD1[48,8] = ~(Rm_VPR64.8B[48,8]); + TMPD1[56,8] = ~(Rm_VPR64.8B[56,8]); + # simd infix Rd_VPR64.8B = Rn_VPR64.8B | TMPD1 on lane size 1 + Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] | TMPD1[0,8]; + Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] | TMPD1[8,8]; + Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] | TMPD1[16,8]; + Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] | TMPD1[24,8]; + Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] | TMPD1[32,8]; + Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] | TMPD1[40,8]; + Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] | TMPD1[48,8]; + Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] | TMPD1[56,8]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.212 ORR (vector, immediate) page C7-2507 line 146708 MATCH x0f001400/mask=xbff81c00 +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00 +# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00 +# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00 +# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00 +# CONSTRUCT x0f001400/mask=xfff89c00 MATCHED 6 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2:4 &=$|@4 +# SMACRO(pseudo) ARG1 ARG2:4 &=NEON_orn/2@4 +# AUNIT --inst x0f001400/mask=xfff89c00 --status pass + +:orr Rd_VPR64.2S, Imm_neon_uimm8Shift +is b_3131=0 & q=0 & b_29=0 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1515=0 & b_1012=5 & Rd_VPR64.2S & Zd +{ + # simd infix Rd_VPR64.2S = Rd_VPR64.2S | Imm_neon_uimm8Shift:4 on lane size 4 + Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] | Imm_neon_uimm8Shift:4; + Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] | Imm_neon_uimm8Shift:4; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.212 ORR (vector, immediate) page C7-2507 line 146708 MATCH x0f001400/mask=xbff81c00 +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x0f009400/mask=xbf80fc00 +# CONSTRUCT x0f009400/mask=xfff8dc00 MATCHED 3 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2:2 &=$|@2 +# SMACRO(pseudo) ARG1 ARG2:2 &=NEON_orn/2@2 +# AUNIT --inst x0f009400/mask=xfff8dc00 --status pass + +:orr Rd_VPR64.4H, Imm_neon_uimm8Shift +is b_3131=0 & q=0 & b_29=0 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1415=2 & b_1012=5 & Rd_VPR64.4H & Zd +{ + # simd infix Rd_VPR64.4H = Rd_VPR64.4H | Imm_neon_uimm8Shift:2 on lane size 2 + Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] | Imm_neon_uimm8Shift:2; + Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] | Imm_neon_uimm8Shift:2; + Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] | Imm_neon_uimm8Shift:2; + Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] | Imm_neon_uimm8Shift:2; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.212 ORR (vector, immediate) page C7-2507 line 146708 MATCH x0f001400/mask=xbff81c00 +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00 +# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00 +# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00 +# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00 +# CONSTRUCT x4f001400/mask=xfff89c00 MATCHED 6 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2:4 &=$| +# SMACRO(pseudo) ARG1 ARG2:4 &=NEON_orn/2@4 +# AUNIT --inst x4f001400/mask=xfff89c00 --status pass + +:orr Rd_VPR128.4S, Imm_neon_uimm8Shift +is b_3131=0 & q=1 & b_29=0 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1515=0 & b_1012=5 & Rd_VPR128.4S & Zd +{ + # simd infix Rd_VPR128.4S = Rd_VPR128.4S | Imm_neon_uimm8Shift:4 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] | Imm_neon_uimm8Shift:4; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] | Imm_neon_uimm8Shift:4; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] | Imm_neon_uimm8Shift:4; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] | Imm_neon_uimm8Shift:4; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.212 ORR (vector, immediate) page C7-2507 line 146708 MATCH x0f001400/mask=xbff81c00 +# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00 +# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x0f009400/mask=xbf80fc00 +# CONSTRUCT x4f009400/mask=xfff8dc00 MATCHED 3 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2:2 &=$| +# SMACRO(pseudo) ARG1 ARG2:2 &=NEON_orr/2@2 +# AUNIT --inst x4f009400/mask=xfff8dc00 --status pass + +:orr Rd_VPR128.8H, Imm_neon_uimm8Shift +is b_3131=0 & q=1 & b_29=0 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1415=2 & b_1012=5 & Rd_VPR128.8H & Zd +{ + # simd infix Rd_VPR128.8H = Rd_VPR128.8H | Imm_neon_uimm8Shift:2 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] | Imm_neon_uimm8Shift:2; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] | Imm_neon_uimm8Shift:2; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] | Imm_neon_uimm8Shift:2; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] | Imm_neon_uimm8Shift:2; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] | Imm_neon_uimm8Shift:2; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] | Imm_neon_uimm8Shift:2; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] | Imm_neon_uimm8Shift:2; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] | Imm_neon_uimm8Shift:2; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.213 ORR (vector, register) page C7-2509 line 146837 MATCH x0ea01c00/mask=xbfe0fc00 +# C7.2.202 MOV (vector) page C7-2487 line 145604 MATCH x0ea01c00/mask=xbfe0fc00 +# CONSTRUCT x4ea01c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$|@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_orr/2@1 +# AUNIT --inst x4ea01c00/mask=xffe0fc00 --status pass + +:orr Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + # simd infix Rd_VPR128.16B = Rn_VPR128.16B | Rm_VPR128.16B on lane size 1 + Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] | Rm_VPR128.16B[0,8]; + Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] | Rm_VPR128.16B[8,8]; + Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] | Rm_VPR128.16B[16,8]; + Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] | Rm_VPR128.16B[24,8]; + Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] | Rm_VPR128.16B[32,8]; + Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] | Rm_VPR128.16B[40,8]; + Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] | Rm_VPR128.16B[48,8]; + Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] | Rm_VPR128.16B[56,8]; + Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] | Rm_VPR128.16B[64,8]; + Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] | Rm_VPR128.16B[72,8]; + Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] | Rm_VPR128.16B[80,8]; + Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] | Rm_VPR128.16B[88,8]; + Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] | Rm_VPR128.16B[96,8]; + Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] | Rm_VPR128.16B[104,8]; + Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] | Rm_VPR128.16B[112,8]; + Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] | Rm_VPR128.16B[120,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.213 ORR (vector, register) page C7-2509 line 146837 MATCH x0ea01c00/mask=xbfe0fc00 +# C7.2.202 MOV (vector) page C7-2487 line 145604 MATCH x0ea01c00/mask=xbfe0fc00 +# CONSTRUCT x0ea01c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$|@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_orr/2@1 +# AUNIT --inst x0ea01c00/mask=xffe0fc00 --status pass + +:orr Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + # simd infix Rd_VPR64.8B = Rn_VPR64.8B | Rm_VPR64.8B on lane size 1 + Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] | Rm_VPR64.8B[0,8]; + Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] | Rm_VPR64.8B[8,8]; + Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] | Rm_VPR64.8B[16,8]; + Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] | Rm_VPR64.8B[24,8]; + Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] | Rm_VPR64.8B[32,8]; + Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] | Rm_VPR64.8B[40,8]; + Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] | Rm_VPR64.8B[48,8]; + Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] | Rm_VPR64.8B[56,8]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.214 PMUL page C7-2511 line 146928 MATCH x2e209c00/mask=xbf20fc00 +# CONSTRUCT x6e209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_pmul/2@1 +# AUNIT --inst x6e209c00/mask=xffe0fc00 --status nopcodeop + +:pmul Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x13 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_pmul(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.214 PMUL page C7-2511 line 146928 MATCH x2e209c00/mask=xbf20fc00 +# CONSTRUCT x2e209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_pmul/2@1 +# AUNIT --inst x2e209c00/mask=xffe0fc00 --status nopcodeop + +:pmul Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x13 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_pmul(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.215 PMULL, PMULL2 page C7-2513 line 147032 MATCH x0e20e000/mask=xbf20fc00 +# CONSTRUCT x0ee0e000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_pmull/2@8 +# AUNIT --inst x0ee0e000/mask=xffe0fc00 --status nopcodeop --comment "ext" + +:pmull Rd_VPR128.1Q, Rn_VPR64.1D, Rm_VPR64.1D +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR64.1D & b_1215=0xe & b_1011=0 & Rn_VPR64.1D & Rd_VPR128.1Q & Zd +{ + Rd_VPR128.1Q = NEON_pmull(Rn_VPR64.1D, Rm_VPR64.1D, 8:1); +} + +# C7.2.215 PMULL, PMULL2 page C7-2513 line 147032 MATCH x0e20e000/mask=xbf20fc00 +# CONSTRUCT x0e20e000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_pmull/2@1 +# AUNIT --inst x0e20e000/mask=xffe0fc00 --status nopcodeop --comment "ext" + +:pmull Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0xe & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_pmull(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.215 PMULL, PMULL2 page C7-2513 line 147032 MATCH x0e20e000/mask=xbf20fc00 +# CONSTRUCT x4ee0e000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_pmull2/2@8 +# AUNIT --inst x4ee0e000/mask=xffe0fc00 --status nopcodeop --comment "ext" + +:pmull2 Rd_VPR128.1Q, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1215=0xe & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.1Q & Zd +{ + Rd_VPR128.1Q = NEON_pmull2(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.215 PMULL, PMULL2 page C7-2513 line 147032 MATCH x0e20e000/mask=xbf20fc00 +# CONSTRUCT x4e20e000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_pmull2/2@1 +# AUNIT --inst x4e20e000/mask=xffe0fc00 --status nopcodeop --comment "ext" + +:pmull2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0xe & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_pmull2(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.216 RADDHN, RADDHN2 page C7-2515 line 147152 MATCH x2e204000/mask=xbf20fc00 +# CONSTRUCT x6e204000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $+@2 0x80:2 &=$+@2 &=$shuffle@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15:1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_raddhn2/3@2 +# AUNIT --inst x6e204000/mask=xffe0fc00 --status pass --comment "intround" + +:raddhn2 Rd_VPR128.16B, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x4 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.16B & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.8H + Rm_VPR128.8H on lane size 2 + TMPQ1[0,16] = Rn_VPR128.8H[0,16] + Rm_VPR128.8H[0,16]; + TMPQ1[16,16] = Rn_VPR128.8H[16,16] + Rm_VPR128.8H[16,16]; + TMPQ1[32,16] = Rn_VPR128.8H[32,16] + Rm_VPR128.8H[32,16]; + TMPQ1[48,16] = Rn_VPR128.8H[48,16] + Rm_VPR128.8H[48,16]; + TMPQ1[64,16] = Rn_VPR128.8H[64,16] + Rm_VPR128.8H[64,16]; + TMPQ1[80,16] = Rn_VPR128.8H[80,16] + Rm_VPR128.8H[80,16]; + TMPQ1[96,16] = Rn_VPR128.8H[96,16] + Rm_VPR128.8H[96,16]; + TMPQ1[112,16] = Rn_VPR128.8H[112,16] + Rm_VPR128.8H[112,16]; + # simd infix TMPQ1 = TMPQ1 + 0x80:2 on lane size 2 + TMPQ1[0,16] = TMPQ1[0,16] + 0x80:2; + TMPQ1[16,16] = TMPQ1[16,16] + 0x80:2; + TMPQ1[32,16] = TMPQ1[32,16] + 0x80:2; + TMPQ1[48,16] = TMPQ1[48,16] + 0x80:2; + TMPQ1[64,16] = TMPQ1[64,16] + 0x80:2; + TMPQ1[80,16] = TMPQ1[80,16] + 0x80:2; + TMPQ1[96,16] = TMPQ1[96,16] + 0x80:2; + TMPQ1[112,16] = TMPQ1[112,16] + 0x80:2; + # simd shuffle Rd_VPR128.16B = TMPQ1 (@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15) lane size 1 + Rd_VPR128.16B[64,8] = TMPQ1[8,8]; + Rd_VPR128.16B[72,8] = TMPQ1[24,8]; + Rd_VPR128.16B[80,8] = TMPQ1[40,8]; + Rd_VPR128.16B[88,8] = TMPQ1[56,8]; + Rd_VPR128.16B[96,8] = TMPQ1[72,8]; + Rd_VPR128.16B[104,8] = TMPQ1[88,8]; + Rd_VPR128.16B[112,8] = TMPQ1[104,8]; + Rd_VPR128.16B[120,8] = TMPQ1[120,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.216 RADDHN, RADDHN2 page C7-2515 line 147152 MATCH x2e204000/mask=xbf20fc00 +# CONSTRUCT x6ea04000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $+@8 0x80000000:8 &=$+@8 &=$shuffle@1-2@3-3:4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_raddhn2/3@8 +# AUNIT --inst x6ea04000/mask=xffe0fc00 --status pass --comment "intround" + +:raddhn2 Rd_VPR128.4S, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x4 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.4S & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.2D + Rm_VPR128.2D on lane size 8 + TMPQ1[0,64] = Rn_VPR128.2D[0,64] + Rm_VPR128.2D[0,64]; + TMPQ1[64,64] = Rn_VPR128.2D[64,64] + Rm_VPR128.2D[64,64]; + # simd infix TMPQ1 = TMPQ1 + 0x80000000:8 on lane size 8 + TMPQ1[0,64] = TMPQ1[0,64] + 0x80000000:8; + TMPQ1[64,64] = TMPQ1[64,64] + 0x80000000:8; + # simd shuffle Rd_VPR128.4S = TMPQ1 (@1-2@3-3) lane size 4 + Rd_VPR128.4S[64,32] = TMPQ1[32,32]; + Rd_VPR128.4S[96,32] = TMPQ1[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.216 RADDHN, RADDHN2 page C7-2515 line 147152 MATCH x2e204000/mask=xbf20fc00 +# CONSTRUCT x6e604000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $+@4 0x8000:4 &=$+@4 &=$shuffle@1-4@3-5@5-6@7-7:2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_raddhn2/3@4 +# AUNIT --inst x6e604000/mask=xffe0fc00 --status pass --comment "intround" + +:raddhn2 Rd_VPR128.8H, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x4 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.8H & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.4S + Rm_VPR128.4S on lane size 4 + TMPQ1[0,32] = Rn_VPR128.4S[0,32] + Rm_VPR128.4S[0,32]; + TMPQ1[32,32] = Rn_VPR128.4S[32,32] + Rm_VPR128.4S[32,32]; + TMPQ1[64,32] = Rn_VPR128.4S[64,32] + Rm_VPR128.4S[64,32]; + TMPQ1[96,32] = Rn_VPR128.4S[96,32] + Rm_VPR128.4S[96,32]; + # simd infix TMPQ1 = TMPQ1 + 0x8000:4 on lane size 4 + TMPQ1[0,32] = TMPQ1[0,32] + 0x8000:4; + TMPQ1[32,32] = TMPQ1[32,32] + 0x8000:4; + TMPQ1[64,32] = TMPQ1[64,32] + 0x8000:4; + TMPQ1[96,32] = TMPQ1[96,32] + 0x8000:4; + # simd shuffle Rd_VPR128.8H = TMPQ1 (@1-4@3-5@5-6@7-7) lane size 2 + Rd_VPR128.8H[64,16] = TMPQ1[16,16]; + Rd_VPR128.8H[80,16] = TMPQ1[48,16]; + Rd_VPR128.8H[96,16] = TMPQ1[80,16]; + Rd_VPR128.8H[112,16] = TMPQ1[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.216 RADDHN, RADDHN2 page C7-2515 line 147152 MATCH x2e204000/mask=xbf20fc00 +# CONSTRUCT x2ea04000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_raddhn/3@8 +# AUNIT --inst x2ea04000/mask=xffe0fc00 --status nopcodeop + +:raddhn Rd_VPR64.2S, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x4 & b_1011=0 & Rn_VPR128.2D & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_raddhn(Rd_VPR64.2S, Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.216 RADDHN, RADDHN2 page C7-2515 line 147152 MATCH x2e204000/mask=xbf20fc00 +# CONSTRUCT x2e604000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_raddhn/3@4 +# AUNIT --inst x2e604000/mask=xffe0fc00 --status nopcodeop + +:raddhn Rd_VPR64.4H, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x4 & b_1011=0 & Rn_VPR128.4S & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_raddhn(Rd_VPR64.4H, Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.216 RADDHN, RADDHN2 page C7-2515 line 147152 MATCH x2e204000/mask=xbf20fc00 +# CONSTRUCT x2e204000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_raddhn/3@2 +# AUNIT --inst x2e204000/mask=xffe0fc00 --status nopcodeop + +:raddhn Rd_VPR64.8B, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x4 & b_1011=0 & Rn_VPR128.8H & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_raddhn(Rd_VPR64.8B, Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.217 RAX1 page C7-2517 line 147279 MATCH xce608c00/mask=xffe0fc00 +# CONSTRUCT xce608c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 1:8 $<<@8 =$|@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_rax1/2@8 +# AUNIT --inst xce608c00/mask=xffe0fc00 --status noqemu + +:rax1 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_2131=0b11001110011 & b_1015=0b100011 & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd +{ + # simd infix TMPQ1 = Rm_VPR128.2D << 1:8 on lane size 8 + TMPQ1[0,64] = Rm_VPR128.2D[0,64] << 1:8; + TMPQ1[64,64] = Rm_VPR128.2D[64,64] << 1:8; + # simd infix Rd_VPR128.2D = Rn_VPR128.2D | TMPQ1 on lane size 8 + Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] | TMPQ1[0,64]; + Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] | TMPQ1[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.218 RBIT (vector) page C7-2518 line 147347 MATCH x2e605800/mask=xbffffc00 +# CONSTRUCT x2e605800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_rbit/1@1 +# AUNIT --inst x2e605800/mask=xfffffc00 --status nopcodeop + +:rbit Rd_VPR64.8B, Rn_VPR64.8B +is b_31=0 & b_30=0 & b_1029=0b10111001100000010110 & Rd_VPR64.8B & Rn_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_rbit(Rn_VPR64.8B, 1:1); +} + +# C7.2.218 RBIT (vector) page C7-2518 line 147347 MATCH x2e605800/mask=xbffffc00 +# CONSTRUCT x6e605800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_rbit/1@1 +# AUNIT --inst x6e605800/mask=xfffffc00 --status nopcodeop + +:rbit Rd_VPR128.16B, Rn_VPR128.16B +is b_31=0 & b_30=1 & b_1029=0b10111001100000010110 & Rd_VPR128.16B & Rn_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_rbit(Rn_VPR128.16B, 1:1); +} + +# C7.2.219 REV16 (vector) page C7-2520 line 147435 MATCH x0e201800/mask=xbf3ffc00 +# CONSTRUCT x4e201800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_rev16/1@1 +# AUNIT --inst x4e201800/mask=xfffffc00 --status nopcodeop + +:rev16 Rd_VPR128.16B, Rn_VPR128.16B +is b_3131=0 & Q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x1 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_rev16(Rn_VPR128.16B, 1:1); +} + +# C7.2.219 REV16 (vector) page C7-2520 line 147435 MATCH x0e201800/mask=xbf3ffc00 +# CONSTRUCT x0e201800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_rev16/1@1 +# AUNIT --inst x0e201800/mask=xfffffc00 --status nopcodeop + +:rev16 Rd_VPR64.8B, Rn_VPR64.8B +is b_3131=0 & Q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x1 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_rev16(Rn_VPR64.8B, 1:1); +} + +# C7.2.220 REV32 (vector) page C7-2522 line 147553 MATCH x2e200800/mask=xbf3ffc00 +# CONSTRUCT x6e200800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_rev32/1@1 +# AUNIT --inst x6e200800/mask=xfffffc00 --status nopcodeop + +:rev32 Rd_VPR128.16B, Rn_VPR128.16B +is b_3131=0 & Q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_rev32(Rn_VPR128.16B, 1:1); +} + +# C7.2.220 REV32 (vector) page C7-2522 line 147553 MATCH x2e200800/mask=xbf3ffc00 +# CONSTRUCT x2e600800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_rev32/1@2 +# AUNIT --inst x2e600800/mask=xfffffc00 --status nopcodeop + +:rev32 Rd_VPR64.4H, Rn_VPR64.4H +is b_3131=0 & Q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_rev32(Rn_VPR64.4H, 2:1); +} + +# C7.2.220 REV32 (vector) page C7-2522 line 147553 MATCH x2e200800/mask=xbf3ffc00 +# CONSTRUCT x2e200800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_rev32/1@1 +# AUNIT --inst x2e200800/mask=xfffffc00 --status nopcodeop + +:rev32 Rd_VPR64.8B, Rn_VPR64.8B +is b_3131=0 & Q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_rev32(Rn_VPR64.8B, 1:1); +} + +# C7.2.220 REV32 (vector) page C7-2522 line 147553 MATCH x2e200800/mask=xbf3ffc00 +# CONSTRUCT x6e600800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_rev32/1@2 +# AUNIT --inst x6e600800/mask=xfffffc00 --status nopcodeop + +:rev32 Rd_VPR128.8H, Rn_VPR128.8H +is b_3131=0 & Q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_rev32(Rn_VPR128.8H, 2:1); +} + +# C7.2.221 REV64 page C7-2524 line 147671 MATCH x0e200800/mask=xbf3ffc00 +# CONSTRUCT x4e200800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_rev64/1@1 +# AUNIT --inst x4e200800/mask=xfffffc00 --status nopcodeop + +:rev64 Rd_VPR128.16B, Rn_VPR128.16B +is b_3131=0 & Q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_rev64(Rn_VPR128.16B, 1:1); +} + +# C7.2.221 REV64 page C7-2524 line 147671 MATCH x0e200800/mask=xbf3ffc00 +# CONSTRUCT x0ea00800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_rev64/1@4 +# AUNIT --inst x0ea00800/mask=xfffffc00 --status nopcodeop + +:rev64 Rd_VPR64.2S, Rn_VPR64.2S +is b_3131=0 & Q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_rev64(Rn_VPR64.2S, 4:1); +} + +# C7.2.221 REV64 page C7-2524 line 147671 MATCH x0e200800/mask=xbf3ffc00 +# CONSTRUCT x0e600800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_rev64/1@2 +# AUNIT --inst x0e600800/mask=xfffffc00 --status nopcodeop + +:rev64 Rd_VPR64.4H, Rn_VPR64.4H +is b_3131=0 & Q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_rev64(Rn_VPR64.4H, 2:1); +} + +# C7.2.221 REV64 page C7-2524 line 147671 MATCH x0e200800/mask=xbf3ffc00 +# CONSTRUCT x4ea00800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_rev64/1@4 +# AUNIT --inst x4ea00800/mask=xfffffc00 --status nopcodeop + +:rev64 Rd_VPR128.4S, Rn_VPR128.4S +is b_3131=0 & Q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_rev64(Rn_VPR128.4S, 4:1); +} + +# C7.2.221 REV64 page C7-2524 line 147671 MATCH x0e200800/mask=xbf3ffc00 +# CONSTRUCT x0e200800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_rev64/1@1 +# AUNIT --inst x0e200800/mask=xfffffc00 --status nopcodeop + +:rev64 Rd_VPR64.8B, Rn_VPR64.8B +is b_3131=0 & Q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_rev64(Rn_VPR64.8B, 1:1); +} + +# C7.2.221 REV64 page C7-2524 line 147671 MATCH x0e200800/mask=xbf3ffc00 +# CONSTRUCT x4e600800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_rev64/1@2 +# AUNIT --inst x4e600800/mask=xfffffc00 --status nopcodeop + +:rev64 Rd_VPR128.8H, Rn_VPR128.8H +is b_3131=0 & Q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_rev64(Rn_VPR128.8H, 2:1); +} + +# C7.2.222 RSHRN, RSHRN2 page C7-2526 line 147791 MATCH x0f008c00/mask=xbf80fc00 +# CONSTRUCT x4f088c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_rshrn2/3@2 +# AUNIT --inst x4f088c00/mask=xfff8fc00 --status nopcodeop --comment "nointround" + +:rshrn2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x11 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_rshrn2(Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1); +} + +# C7.2.222 RSHRN, RSHRN2 page C7-2526 line 147791 MATCH x0f008c00/mask=xbf80fc00 +# CONSTRUCT x0f208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_rshrn/3@8 +# AUNIT --inst x0f208c00/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:rshrn Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x11 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_rshrn(Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1); +} + +# C7.2.222 RSHRN, RSHRN2 page C7-2526 line 147791 MATCH x0f008c00/mask=xbf80fc00 +# CONSTRUCT x0f108c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_rshrn/3@4 +# AUNIT --inst x0f108c00/mask=xfff0fc00 --status nopcodeop --comment "nointround" + +:rshrn Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x11 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_rshrn(Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1); +} + +# C7.2.222 RSHRN, RSHRN2 page C7-2526 line 147791 MATCH x0f008c00/mask=xbf80fc00 +# CONSTRUCT x4f208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_rshrn2/3@8 +# AUNIT --inst x4f208c00/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:rshrn2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x11 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_rshrn2(Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1); +} + +# C7.2.222 RSHRN, RSHRN2 page C7-2526 line 147791 MATCH x0f008c00/mask=xbf80fc00 +# CONSTRUCT x0f088c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_rshrn/3@2 +# AUNIT --inst x0f088c00/mask=xfff8fc00 --status nopcodeop --comment "nointround" + +:rshrn Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x11 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_rshrn(Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1); +} + +# C7.2.222 RSHRN, RSHRN2 page C7-2526 line 147791 MATCH x0f008c00/mask=xbf80fc00 +# CONSTRUCT x4f108c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_rshrn2/3@4 +# AUNIT --inst x4f108c00/mask=xfff0fc00 --status nopcodeop --comment "nointround" + +:rshrn2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x11 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_rshrn2(Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1); +} + +# C7.2.223 RSUBHN, RSUBHN2 page C7-2528 line 147915 MATCH x2e206000/mask=xbf20fc00 +# CONSTRUCT x6e206000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_rsubhn2/3@2 +# AUNIT --inst x6e206000/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:rsubhn2 Rd_VPR128.16B, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x6 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_rsubhn2(Rd_VPR128.16B, Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.223 RSUBHN, RSUBHN2 page C7-2528 line 147915 MATCH x2e206000/mask=xbf20fc00 +# CONSTRUCT x6ea06000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_rsubhn2/3@8 +# AUNIT --inst x6ea06000/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:rsubhn2 Rd_VPR128.4S, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x6 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_rsubhn2(Rd_VPR128.4S, Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.223 RSUBHN, RSUBHN2 page C7-2528 line 147915 MATCH x2e206000/mask=xbf20fc00 +# CONSTRUCT x6e606000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_rsubhn2/3@4 +# AUNIT --inst x6e606000/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:rsubhn2 Rd_VPR128.8H, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x6 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_rsubhn2(Rd_VPR128.8H, Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.223 RSUBHN, RSUBHN2 page C7-2528 line 147915 MATCH x2e206000/mask=xbf20fc00 +# CONSTRUCT x2ea06000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_rsubhn/3@8 +# AUNIT --inst x2ea06000/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:rsubhn Rd_VPR64.2S, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x6 & b_1011=0 & Rn_VPR128.2D & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_rsubhn(Rd_VPR64.2S, Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.223 RSUBHN, RSUBHN2 page C7-2528 line 147915 MATCH x2e206000/mask=xbf20fc00 +# CONSTRUCT x2e606000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_rsubhn/3@4 +# AUNIT --inst x2e606000/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:rsubhn Rd_VPR64.4H, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x6 & b_1011=0 & Rn_VPR128.4S & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_rsubhn(Rd_VPR64.4H, Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.223 RSUBHN, RSUBHN2 page C7-2528 line 147915 MATCH x2e206000/mask=xbf20fc00 +# CONSTRUCT x2e206000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_rsubhn/3@2 +# AUNIT --inst x2e206000/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:rsubhn Rd_VPR64.8B, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x6 & b_1011=0 & Rn_VPR128.8H & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_rsubhn(Rd_VPR64.8B, Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.224 SABA page C7-2530 line 148042 MATCH x0e207c00/mask=xbf20fc00 +# CONSTRUCT x4e207c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saba/3@1 +# AUNIT --inst x4e207c00/mask=xffe0fc00 --status nopcodeop --comment "abd" + +:saba Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xf & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_saba(Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.224 SABA page C7-2530 line 148042 MATCH x0e207c00/mask=xbf20fc00 +# CONSTRUCT x0ea07c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saba/3@4 +# AUNIT --inst x0ea07c00/mask=xffe0fc00 --status nopcodeop --comment "abd" + +:saba Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xf & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_saba(Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.224 SABA page C7-2530 line 148042 MATCH x0e207c00/mask=xbf20fc00 +# CONSTRUCT x0e607c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saba/3@2 +# AUNIT --inst x0e607c00/mask=xffe0fc00 --status nopcodeop --comment "abd" + +:saba Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xf & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_saba(Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.224 SABA page C7-2530 line 148042 MATCH x0e207c00/mask=xbf20fc00 +# CONSTRUCT x4ea07c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saba/3@4 +# AUNIT --inst x4ea07c00/mask=xffe0fc00 --status nopcodeop --comment "abd" + +:saba Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xf & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_saba(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.224 SABA page C7-2530 line 148042 MATCH x0e207c00/mask=xbf20fc00 +# CONSTRUCT x0e207c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saba/3@1 +# AUNIT --inst x0e207c00/mask=xffe0fc00 --status nopcodeop --comment "abd" + +:saba Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xf & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_saba(Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.224 SABA page C7-2530 line 148042 MATCH x0e207c00/mask=xbf20fc00 +# CONSTRUCT x4e607c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saba/3@2 +# AUNIT --inst x4e607c00/mask=xffe0fc00 --status nopcodeop --comment "abd" + +:saba Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xf & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_saba(Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.225 SABAL, SABAL2 page C7-2532 line 148144 MATCH x0e205000/mask=xbf20fc00 +# CONSTRUCT x0ea05000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 $-@8 $abs@8 &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabal/3@4 +# AUNIT --inst x0ea05000/mask=xffe0fc00 --status pass --comment "ext abd" + +:sabal Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x5 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]); + # simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8) + TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]); + TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]); + # simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 8 + TMPQ3[0,64] = TMPQ1[0,64] - TMPQ2[0,64]; + TMPQ3[64,64] = TMPQ1[64,64] - TMPQ2[64,64]; + # simd unary TMPQ4 = MP_INT_ABS(TMPQ3) on lane size 8 + TMPQ4[0,64] = MP_INT_ABS(TMPQ3[0,64]); + TMPQ4[64,64] = MP_INT_ABS(TMPQ3[64,64]); + # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ4 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ4[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ4[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.225 SABAL, SABAL2 page C7-2532 line 148144 MATCH x0e205000/mask=xbf20fc00 +# CONSTRUCT x0e605000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 $-@4 $abs@4 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabal/3@2 +# AUNIT --inst x0e605000/mask=xffe0fc00 --status pass --comment "ext abd" + +:sabal Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x5 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]); + # simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4) + TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]); + TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]); + TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]); + TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]); + # simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 4 + TMPQ3[0,32] = TMPQ1[0,32] - TMPQ2[0,32]; + TMPQ3[32,32] = TMPQ1[32,32] - TMPQ2[32,32]; + TMPQ3[64,32] = TMPQ1[64,32] - TMPQ2[64,32]; + TMPQ3[96,32] = TMPQ1[96,32] - TMPQ2[96,32]; + # simd unary TMPQ4 = MP_INT_ABS(TMPQ3) on lane size 4 + TMPQ4[0,32] = MP_INT_ABS(TMPQ3[0,32]); + TMPQ4[32,32] = MP_INT_ABS(TMPQ3[32,32]); + TMPQ4[64,32] = MP_INT_ABS(TMPQ3[64,32]); + TMPQ4[96,32] = MP_INT_ABS(TMPQ3[96,32]); + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ4 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ4[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ4[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ4[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ4[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.225 SABAL, SABAL2 page C7-2532 line 148144 MATCH x0e205000/mask=xbf20fc00 +# CONSTRUCT x0e205000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 $-@2 $abs@2 &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabal/3@1 +# AUNIT --inst x0e205000/mask=xffe0fc00 --status pass --comment "ext abd" + +:sabal Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x5 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2) + TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]); + TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]); + TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]); + TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]); + TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]); + TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]); + TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]); + TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]); + # simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2) + TMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]); + TMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]); + TMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]); + TMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]); + TMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]); + TMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]); + TMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]); + TMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]); + # simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 2 + TMPQ3[0,16] = TMPQ1[0,16] - TMPQ2[0,16]; + TMPQ3[16,16] = TMPQ1[16,16] - TMPQ2[16,16]; + TMPQ3[32,16] = TMPQ1[32,16] - TMPQ2[32,16]; + TMPQ3[48,16] = TMPQ1[48,16] - TMPQ2[48,16]; + TMPQ3[64,16] = TMPQ1[64,16] - TMPQ2[64,16]; + TMPQ3[80,16] = TMPQ1[80,16] - TMPQ2[80,16]; + TMPQ3[96,16] = TMPQ1[96,16] - TMPQ2[96,16]; + TMPQ3[112,16] = TMPQ1[112,16] - TMPQ2[112,16]; + # simd unary TMPQ4 = MP_INT_ABS(TMPQ3) on lane size 2 + TMPQ4[0,16] = MP_INT_ABS(TMPQ3[0,16]); + TMPQ4[16,16] = MP_INT_ABS(TMPQ3[16,16]); + TMPQ4[32,16] = MP_INT_ABS(TMPQ3[32,16]); + TMPQ4[48,16] = MP_INT_ABS(TMPQ3[48,16]); + TMPQ4[64,16] = MP_INT_ABS(TMPQ3[64,16]); + TMPQ4[80,16] = MP_INT_ABS(TMPQ3[80,16]); + TMPQ4[96,16] = MP_INT_ABS(TMPQ3[96,16]); + TMPQ4[112,16] = MP_INT_ABS(TMPQ3[112,16]); + # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ4 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ4[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ4[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ4[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ4[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ4[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ4[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ4[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ4[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.225 SABAL, SABAL2 page C7-2532 line 148144 MATCH x0e205000/mask=xbf20fc00 +# CONSTRUCT x4ea05000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $-@8 $abs@8 &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabal2/3@4 +# AUNIT --inst x4ea05000/mask=xffe0fc00 --status pass --comment "ext abd" + +:sabal2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x5 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = sext(TMPD1[0,32]); + TMPQ2[64,64] = sext(TMPD1[32,32]); + TMPD3 = Rm_VPR128.4S[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8) + TMPQ4[0,64] = sext(TMPD3[0,32]); + TMPQ4[64,64] = sext(TMPD3[32,32]); + # simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 8 + TMPQ5[0,64] = TMPQ2[0,64] - TMPQ4[0,64]; + TMPQ5[64,64] = TMPQ2[64,64] - TMPQ4[64,64]; + # simd unary TMPQ6 = MP_INT_ABS(TMPQ5) on lane size 8 + TMPQ6[0,64] = MP_INT_ABS(TMPQ5[0,64]); + TMPQ6[64,64] = MP_INT_ABS(TMPQ5[64,64]); + # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ6 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ6[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ6[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.225 SABAL, SABAL2 page C7-2532 line 148144 MATCH x0e205000/mask=xbf20fc00 +# CONSTRUCT x4e605000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $-@4 $abs@4 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabal2/3@2 +# AUNIT --inst x4e605000/mask=xffe0fc00 --status pass --comment "ext abd" + +:sabal2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x5 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = sext(TMPD1[0,16]); + TMPQ2[32,32] = sext(TMPD1[16,16]); + TMPQ2[64,32] = sext(TMPD1[32,16]); + TMPQ2[96,32] = sext(TMPD1[48,16]); + TMPD3 = Rm_VPR128.8H[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4) + TMPQ4[0,32] = sext(TMPD3[0,16]); + TMPQ4[32,32] = sext(TMPD3[16,16]); + TMPQ4[64,32] = sext(TMPD3[32,16]); + TMPQ4[96,32] = sext(TMPD3[48,16]); + # simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 4 + TMPQ5[0,32] = TMPQ2[0,32] - TMPQ4[0,32]; + TMPQ5[32,32] = TMPQ2[32,32] - TMPQ4[32,32]; + TMPQ5[64,32] = TMPQ2[64,32] - TMPQ4[64,32]; + TMPQ5[96,32] = TMPQ2[96,32] - TMPQ4[96,32]; + # simd unary TMPQ6 = MP_INT_ABS(TMPQ5) on lane size 4 + TMPQ6[0,32] = MP_INT_ABS(TMPQ5[0,32]); + TMPQ6[32,32] = MP_INT_ABS(TMPQ5[32,32]); + TMPQ6[64,32] = MP_INT_ABS(TMPQ5[64,32]); + TMPQ6[96,32] = MP_INT_ABS(TMPQ5[96,32]); + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ6 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ6[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ6[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ6[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ6[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.225 SABAL, SABAL2 page C7-2532 line 148144 MATCH x0e205000/mask=xbf20fc00 +# CONSTRUCT x4e205000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 $-@2 $abs@2 &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabal2/3@1 +# AUNIT --inst x4e205000/mask=xffe0fc00 --status pass --comment "ext abd" + +:sabal2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x5 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd +{ + TMPD1 = Rn_VPR128.16B[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2) + TMPQ2[0,16] = sext(TMPD1[0,8]); + TMPQ2[16,16] = sext(TMPD1[8,8]); + TMPQ2[32,16] = sext(TMPD1[16,8]); + TMPQ2[48,16] = sext(TMPD1[24,8]); + TMPQ2[64,16] = sext(TMPD1[32,8]); + TMPQ2[80,16] = sext(TMPD1[40,8]); + TMPQ2[96,16] = sext(TMPD1[48,8]); + TMPQ2[112,16] = sext(TMPD1[56,8]); + TMPD3 = Rm_VPR128.16B[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2) + TMPQ4[0,16] = sext(TMPD3[0,8]); + TMPQ4[16,16] = sext(TMPD3[8,8]); + TMPQ4[32,16] = sext(TMPD3[16,8]); + TMPQ4[48,16] = sext(TMPD3[24,8]); + TMPQ4[64,16] = sext(TMPD3[32,8]); + TMPQ4[80,16] = sext(TMPD3[40,8]); + TMPQ4[96,16] = sext(TMPD3[48,8]); + TMPQ4[112,16] = sext(TMPD3[56,8]); + # simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 2 + TMPQ5[0,16] = TMPQ2[0,16] - TMPQ4[0,16]; + TMPQ5[16,16] = TMPQ2[16,16] - TMPQ4[16,16]; + TMPQ5[32,16] = TMPQ2[32,16] - TMPQ4[32,16]; + TMPQ5[48,16] = TMPQ2[48,16] - TMPQ4[48,16]; + TMPQ5[64,16] = TMPQ2[64,16] - TMPQ4[64,16]; + TMPQ5[80,16] = TMPQ2[80,16] - TMPQ4[80,16]; + TMPQ5[96,16] = TMPQ2[96,16] - TMPQ4[96,16]; + TMPQ5[112,16] = TMPQ2[112,16] - TMPQ4[112,16]; + # simd unary TMPQ6 = MP_INT_ABS(TMPQ5) on lane size 2 + TMPQ6[0,16] = MP_INT_ABS(TMPQ5[0,16]); + TMPQ6[16,16] = MP_INT_ABS(TMPQ5[16,16]); + TMPQ6[32,16] = MP_INT_ABS(TMPQ5[32,16]); + TMPQ6[48,16] = MP_INT_ABS(TMPQ5[48,16]); + TMPQ6[64,16] = MP_INT_ABS(TMPQ5[64,16]); + TMPQ6[80,16] = MP_INT_ABS(TMPQ5[80,16]); + TMPQ6[96,16] = MP_INT_ABS(TMPQ5[96,16]); + TMPQ6[112,16] = MP_INT_ABS(TMPQ5[112,16]); + # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ6 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ6[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ6[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ6[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ6[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ6[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ6[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ6[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ6[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.226 SABD page C7-2534 line 148264 MATCH x0e207400/mask=xbf20fc00 +# CONSTRUCT x4e207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@1 +# AUNIT --inst x4e207400/mask=xffe0fc00 --status nopcodeop --comment "abd" + +:sabd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xe & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_sabd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.226 SABD page C7-2534 line 148264 MATCH x0e207400/mask=xbf20fc00 +# CONSTRUCT x0ea07400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $-@4 ARG3 ARG2 $-@4 2:4 &=$* ARG2 ARG3 $sless@4 &=$*@4 =$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@4 +# AUNIT --inst x0ea07400/mask=xffe0fc00 --status pass --comment "abd" +# This abd instruction is implemented correctly to document a correct +# way to implement the signed absolute difference semantic. + +:sabd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xe & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + # simd infix TMPD1 = Rn_VPR64.2S - Rm_VPR64.2S on lane size 4 + TMPD1[0,32] = Rn_VPR64.2S[0,32] - Rm_VPR64.2S[0,32]; + TMPD1[32,32] = Rn_VPR64.2S[32,32] - Rm_VPR64.2S[32,32]; + # simd infix TMPD2 = Rm_VPR64.2S - Rn_VPR64.2S on lane size 4 + TMPD2[0,32] = Rm_VPR64.2S[0,32] - Rn_VPR64.2S[0,32]; + TMPD2[32,32] = Rm_VPR64.2S[32,32] - Rn_VPR64.2S[32,32]; + # simd infix TMPD2 = TMPD2 * 2:4 on lane size 4 + TMPD2[0,32] = TMPD2[0,32] * 2:4; + TMPD2[32,32] = TMPD2[32,32] * 2:4; + # simd infix TMPD3 = Rn_VPR64.2S s< Rm_VPR64.2S on lane size 4 + TMPD3[0,32] = zext(Rn_VPR64.2S[0,32] s< Rm_VPR64.2S[0,32]); + TMPD3[32,32] = zext(Rn_VPR64.2S[32,32] s< Rm_VPR64.2S[32,32]); + # simd infix TMPD2 = TMPD2 * TMPD3 on lane size 4 + TMPD2[0,32] = TMPD2[0,32] * TMPD3[0,32]; + TMPD2[32,32] = TMPD2[32,32] * TMPD3[32,32]; + # simd infix Rd_VPR64.2S = TMPD1 + TMPD2 on lane size 4 + Rd_VPR64.2S[0,32] = TMPD1[0,32] + TMPD2[0,32]; + Rd_VPR64.2S[32,32] = TMPD1[32,32] + TMPD2[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.226 SABD page C7-2534 line 148264 MATCH x0e207400/mask=xbf20fc00 +# CONSTRUCT x0e607400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@2 +# AUNIT --inst x0e607400/mask=xffe0fc00 --status nopcodeop --comment "abd" + +:sabd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xe & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_sabd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.226 SABD page C7-2534 line 148264 MATCH x0e207400/mask=xbf20fc00 +# CONSTRUCT x4ea07400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@4 +# AUNIT --inst x4ea07400/mask=xffe0fc00 --status nopcodeop --comment "abd" + +:sabd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xe & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sabd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.226 SABD page C7-2534 line 148264 MATCH x0e207400/mask=xbf20fc00 +# CONSTRUCT x0e207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@1 +# AUNIT --inst x0e207400/mask=xffe0fc00 --status nopcodeop --comment "abd" + +:sabd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xe & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_sabd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.226 SABD page C7-2534 line 148264 MATCH x0e207400/mask=xbf20fc00 +# CONSTRUCT x4e607400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@2 +# AUNIT --inst x4e607400/mask=xffe0fc00 --status nopcodeop --comment "abd" + +:sabd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xe & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_sabd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.227 SABDL, SABDL2 page C7-2536 line 148366 MATCH x0e207000/mask=xbf20fc00 +# CONSTRUCT x0ea07000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 $-@8 =$abs@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabdl/3@4 +# AUNIT --inst x0ea07000/mask=xffe0fc00 --status pass --comment "ext abd" + +:sabdl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x7 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]); + # simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8) + TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]); + TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]); + # simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 8 + TMPQ3[0,64] = TMPQ1[0,64] - TMPQ2[0,64]; + TMPQ3[64,64] = TMPQ1[64,64] - TMPQ2[64,64]; + # simd unary Rd_VPR128.2D = MP_INT_ABS(TMPQ3) on lane size 8 + Rd_VPR128.2D[0,64] = MP_INT_ABS(TMPQ3[0,64]); + Rd_VPR128.2D[64,64] = MP_INT_ABS(TMPQ3[64,64]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.227 SABDL, SABDL2 page C7-2536 line 148366 MATCH x0e207000/mask=xbf20fc00 +# CONSTRUCT x0e607000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 $-@4 =$abs@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabdl/3@2 +# AUNIT --inst x0e607000/mask=xffe0fc00 --status pass --comment "ext abd" + +:sabdl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x7 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]); + # simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4) + TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]); + TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]); + TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]); + TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]); + # simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 4 + TMPQ3[0,32] = TMPQ1[0,32] - TMPQ2[0,32]; + TMPQ3[32,32] = TMPQ1[32,32] - TMPQ2[32,32]; + TMPQ3[64,32] = TMPQ1[64,32] - TMPQ2[64,32]; + TMPQ3[96,32] = TMPQ1[96,32] - TMPQ2[96,32]; + # simd unary Rd_VPR128.4S = MP_INT_ABS(TMPQ3) on lane size 4 + Rd_VPR128.4S[0,32] = MP_INT_ABS(TMPQ3[0,32]); + Rd_VPR128.4S[32,32] = MP_INT_ABS(TMPQ3[32,32]); + Rd_VPR128.4S[64,32] = MP_INT_ABS(TMPQ3[64,32]); + Rd_VPR128.4S[96,32] = MP_INT_ABS(TMPQ3[96,32]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.227 SABDL, SABDL2 page C7-2536 line 148366 MATCH x0e207000/mask=xbf20fc00 +# CONSTRUCT x0e207000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 $-@2 =$abs@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabdl/3@1 +# AUNIT --inst x0e207000/mask=xffe0fc00 --status pass --comment "ext abd" + +:sabdl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x7 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2) + TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]); + TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]); + TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]); + TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]); + TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]); + TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]); + TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]); + TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]); + # simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2) + TMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]); + TMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]); + TMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]); + TMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]); + TMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]); + TMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]); + TMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]); + TMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]); + # simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 2 + TMPQ3[0,16] = TMPQ1[0,16] - TMPQ2[0,16]; + TMPQ3[16,16] = TMPQ1[16,16] - TMPQ2[16,16]; + TMPQ3[32,16] = TMPQ1[32,16] - TMPQ2[32,16]; + TMPQ3[48,16] = TMPQ1[48,16] - TMPQ2[48,16]; + TMPQ3[64,16] = TMPQ1[64,16] - TMPQ2[64,16]; + TMPQ3[80,16] = TMPQ1[80,16] - TMPQ2[80,16]; + TMPQ3[96,16] = TMPQ1[96,16] - TMPQ2[96,16]; + TMPQ3[112,16] = TMPQ1[112,16] - TMPQ2[112,16]; + # simd unary Rd_VPR128.8H = MP_INT_ABS(TMPQ3) on lane size 2 + Rd_VPR128.8H[0,16] = MP_INT_ABS(TMPQ3[0,16]); + Rd_VPR128.8H[16,16] = MP_INT_ABS(TMPQ3[16,16]); + Rd_VPR128.8H[32,16] = MP_INT_ABS(TMPQ3[32,16]); + Rd_VPR128.8H[48,16] = MP_INT_ABS(TMPQ3[48,16]); + Rd_VPR128.8H[64,16] = MP_INT_ABS(TMPQ3[64,16]); + Rd_VPR128.8H[80,16] = MP_INT_ABS(TMPQ3[80,16]); + Rd_VPR128.8H[96,16] = MP_INT_ABS(TMPQ3[96,16]); + Rd_VPR128.8H[112,16] = MP_INT_ABS(TMPQ3[112,16]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.227 SABDL, SABDL2 page C7-2536 line 148366 MATCH x0e207000/mask=xbf20fc00 +# CONSTRUCT x4ea07000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $-@8 =$abs@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabdl2/3@4 +# AUNIT --inst x4ea07000/mask=xffe0fc00 --status pass --comment "ext abd" + +:sabdl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x7 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = sext(TMPD1[0,32]); + TMPQ2[64,64] = sext(TMPD1[32,32]); + TMPD3 = Rm_VPR128.4S[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8) + TMPQ4[0,64] = sext(TMPD3[0,32]); + TMPQ4[64,64] = sext(TMPD3[32,32]); + # simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 8 + TMPQ5[0,64] = TMPQ2[0,64] - TMPQ4[0,64]; + TMPQ5[64,64] = TMPQ2[64,64] - TMPQ4[64,64]; + # simd unary Rd_VPR128.2D = MP_INT_ABS(TMPQ5) on lane size 8 + Rd_VPR128.2D[0,64] = MP_INT_ABS(TMPQ5[0,64]); + Rd_VPR128.2D[64,64] = MP_INT_ABS(TMPQ5[64,64]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.227 SABDL, SABDL2 page C7-2536 line 148366 MATCH x0e207000/mask=xbf20fc00 +# CONSTRUCT x4e607000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $-@4 =$abs@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabdl2/3@2 +# AUNIT --inst x4e607000/mask=xffe0fc00 --status pass --comment "ext abd" + +:sabdl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x7 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = sext(TMPD1[0,16]); + TMPQ2[32,32] = sext(TMPD1[16,16]); + TMPQ2[64,32] = sext(TMPD1[32,16]); + TMPQ2[96,32] = sext(TMPD1[48,16]); + TMPD3 = Rm_VPR128.8H[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4) + TMPQ4[0,32] = sext(TMPD3[0,16]); + TMPQ4[32,32] = sext(TMPD3[16,16]); + TMPQ4[64,32] = sext(TMPD3[32,16]); + TMPQ4[96,32] = sext(TMPD3[48,16]); + # simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 4 + TMPQ5[0,32] = TMPQ2[0,32] - TMPQ4[0,32]; + TMPQ5[32,32] = TMPQ2[32,32] - TMPQ4[32,32]; + TMPQ5[64,32] = TMPQ2[64,32] - TMPQ4[64,32]; + TMPQ5[96,32] = TMPQ2[96,32] - TMPQ4[96,32]; + # simd unary Rd_VPR128.4S = MP_INT_ABS(TMPQ5) on lane size 4 + Rd_VPR128.4S[0,32] = MP_INT_ABS(TMPQ5[0,32]); + Rd_VPR128.4S[32,32] = MP_INT_ABS(TMPQ5[32,32]); + Rd_VPR128.4S[64,32] = MP_INT_ABS(TMPQ5[64,32]); + Rd_VPR128.4S[96,32] = MP_INT_ABS(TMPQ5[96,32]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.227 SABDL, SABDL2 page C7-2536 line 148366 MATCH x0e207000/mask=xbf20fc00 +# CONSTRUCT x4e207000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 $-@2 =$abs@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabdl2/3@1 +# AUNIT --inst x4e207000/mask=xffe0fc00 --status pass --comment "ext abd" + +:sabdl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x7 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd +{ + TMPD1 = Rn_VPR128.16B[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2) + TMPQ2[0,16] = sext(TMPD1[0,8]); + TMPQ2[16,16] = sext(TMPD1[8,8]); + TMPQ2[32,16] = sext(TMPD1[16,8]); + TMPQ2[48,16] = sext(TMPD1[24,8]); + TMPQ2[64,16] = sext(TMPD1[32,8]); + TMPQ2[80,16] = sext(TMPD1[40,8]); + TMPQ2[96,16] = sext(TMPD1[48,8]); + TMPQ2[112,16] = sext(TMPD1[56,8]); + TMPD3 = Rm_VPR128.16B[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2) + TMPQ4[0,16] = sext(TMPD3[0,8]); + TMPQ4[16,16] = sext(TMPD3[8,8]); + TMPQ4[32,16] = sext(TMPD3[16,8]); + TMPQ4[48,16] = sext(TMPD3[24,8]); + TMPQ4[64,16] = sext(TMPD3[32,8]); + TMPQ4[80,16] = sext(TMPD3[40,8]); + TMPQ4[96,16] = sext(TMPD3[48,8]); + TMPQ4[112,16] = sext(TMPD3[56,8]); + # simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 2 + TMPQ5[0,16] = TMPQ2[0,16] - TMPQ4[0,16]; + TMPQ5[16,16] = TMPQ2[16,16] - TMPQ4[16,16]; + TMPQ5[32,16] = TMPQ2[32,16] - TMPQ4[32,16]; + TMPQ5[48,16] = TMPQ2[48,16] - TMPQ4[48,16]; + TMPQ5[64,16] = TMPQ2[64,16] - TMPQ4[64,16]; + TMPQ5[80,16] = TMPQ2[80,16] - TMPQ4[80,16]; + TMPQ5[96,16] = TMPQ2[96,16] - TMPQ4[96,16]; + TMPQ5[112,16] = TMPQ2[112,16] - TMPQ4[112,16]; + # simd unary Rd_VPR128.8H = MP_INT_ABS(TMPQ5) on lane size 2 + Rd_VPR128.8H[0,16] = MP_INT_ABS(TMPQ5[0,16]); + Rd_VPR128.8H[16,16] = MP_INT_ABS(TMPQ5[16,16]); + Rd_VPR128.8H[32,16] = MP_INT_ABS(TMPQ5[32,16]); + Rd_VPR128.8H[48,16] = MP_INT_ABS(TMPQ5[48,16]); + Rd_VPR128.8H[64,16] = MP_INT_ABS(TMPQ5[64,16]); + Rd_VPR128.8H[80,16] = MP_INT_ABS(TMPQ5[80,16]); + Rd_VPR128.8H[96,16] = MP_INT_ABS(TMPQ5[96,16]); + Rd_VPR128.8H[112,16] = MP_INT_ABS(TMPQ5[112,16]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.228 SADALP page C7-2538 line 148486 MATCH x0e206800/mask=xbf3ffc00 +# CONSTRUCT x0e206800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 var:8 ARG2 =#+ &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sadalp/2@1 +# AUNIT --inst x0e206800/mask=xfffffc00 --status pass --comment "ext" +# Vector variant when 4H when size = 00 , Q = 0 Ta=VPR64.4H Tb=VPR64.8B e1=1 e2=2 s2=16 + +:sadalp Rd_VPR64.4H, Rn_VPR64.8B +is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000011010 & Rd_VPR64.4H & Rn_VPR64.8B & Zd +{ + TMPD1 = 0; + # sipd infix TMPD1 = +(Rn_VPR64.8B) on pairs lane size (1 to 2) + local tmp2 = Rn_VPR64.8B[0,8]; + local tmp4 = sext(tmp2); + local tmp3 = Rn_VPR64.8B[8,8]; + local tmp5 = sext(tmp3); + TMPD1[0,16] = tmp4 + tmp5; + tmp2 = Rn_VPR64.8B[16,8]; + tmp4 = sext(tmp2); + tmp3 = Rn_VPR64.8B[24,8]; + tmp5 = sext(tmp3); + TMPD1[16,16] = tmp4 + tmp5; + tmp2 = Rn_VPR64.8B[32,8]; + tmp4 = sext(tmp2); + tmp3 = Rn_VPR64.8B[40,8]; + tmp5 = sext(tmp3); + TMPD1[32,16] = tmp4 + tmp5; + tmp2 = Rn_VPR64.8B[48,8]; + tmp4 = sext(tmp2); + tmp3 = Rn_VPR64.8B[56,8]; + tmp5 = sext(tmp3); + TMPD1[48,16] = tmp4 + tmp5; + # simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2 + Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16]; + Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16]; + Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16]; + Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.228 SADALP page C7-2538 line 148486 MATCH x0e206800/mask=xbf3ffc00 +# CONSTRUCT x4e206800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 var:16 ARG2 =#+ &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sadalp/2@1 +# AUNIT --inst x4e206800/mask=xfffffc00 --status pass --comment "ext" +# Vector variant when 8H when size = 00 , Q = 1 Ta=VPR128.8H Tb=VPR128.16B e1=1 e2=2 s2=32 + +:sadalp Rd_VPR128.8H, Rn_VPR128.16B +is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000011010 & Rd_VPR128.8H & Rn_VPR128.16B & Zd +{ + TMPQ1 = 0; + # sipd infix TMPQ1 = +(Rn_VPR128.16B) on pairs lane size (1 to 2) + local tmp2 = Rn_VPR128.16B[0,8]; + local tmp4 = sext(tmp2); + local tmp3 = Rn_VPR128.16B[8,8]; + local tmp5 = sext(tmp3); + TMPQ1[0,16] = tmp4 + tmp5; + tmp2 = Rn_VPR128.16B[16,8]; + tmp4 = sext(tmp2); + tmp3 = Rn_VPR128.16B[24,8]; + tmp5 = sext(tmp3); + TMPQ1[16,16] = tmp4 + tmp5; + tmp2 = Rn_VPR128.16B[32,8]; + tmp4 = sext(tmp2); + tmp3 = Rn_VPR128.16B[40,8]; + tmp5 = sext(tmp3); + TMPQ1[32,16] = tmp4 + tmp5; + tmp2 = Rn_VPR128.16B[48,8]; + tmp4 = sext(tmp2); + tmp3 = Rn_VPR128.16B[56,8]; + tmp5 = sext(tmp3); + TMPQ1[48,16] = tmp4 + tmp5; + tmp2 = Rn_VPR128.16B[64,8]; + tmp4 = sext(tmp2); + tmp3 = Rn_VPR128.16B[72,8]; + tmp5 = sext(tmp3); + TMPQ1[64,16] = tmp4 + tmp5; + tmp2 = Rn_VPR128.16B[80,8]; + tmp4 = sext(tmp2); + tmp3 = Rn_VPR128.16B[88,8]; + tmp5 = sext(tmp3); + TMPQ1[80,16] = tmp4 + tmp5; + tmp2 = Rn_VPR128.16B[96,8]; + tmp4 = sext(tmp2); + tmp3 = Rn_VPR128.16B[104,8]; + tmp5 = sext(tmp3); + TMPQ1[96,16] = tmp4 + tmp5; + tmp2 = Rn_VPR128.16B[112,8]; + tmp4 = sext(tmp2); + tmp3 = Rn_VPR128.16B[120,8]; + tmp5 = sext(tmp3); + TMPQ1[112,16] = tmp4 + tmp5; + # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.228 SADALP page C7-2538 line 148486 MATCH x0e206800/mask=xbf3ffc00 +# CONSTRUCT x0e606800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 var:8 ARG2 =#+ &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sadalp/2@2 +# AUNIT --inst x0e606800/mask=xfffffc00 --status pass --comment "ext" +# Vector variant when 2S when size = 01 , Q = 0 Ta=VPR64.2S Tb=VPR64.4H e1=2 e2=4 s2=16 + +:sadalp Rd_VPR64.2S, Rn_VPR64.4H +is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000011010 & Rd_VPR64.2S & Rn_VPR64.4H & Zd +{ + TMPD1 = 0; + # sipd infix TMPD1 = +(Rn_VPR64.4H) on pairs lane size (2 to 4) + local tmp2 = Rn_VPR64.4H[0,16]; + local tmp4 = sext(tmp2); + local tmp3 = Rn_VPR64.4H[16,16]; + local tmp5 = sext(tmp3); + TMPD1[0,32] = tmp4 + tmp5; + tmp2 = Rn_VPR64.4H[32,16]; + tmp4 = sext(tmp2); + tmp3 = Rn_VPR64.4H[48,16]; + tmp5 = sext(tmp3); + TMPD1[32,32] = tmp4 + tmp5; + # simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4 + Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32]; + Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.228 SADALP page C7-2538 line 148486 MATCH x0e206800/mask=xbf3ffc00 +# CONSTRUCT x4e606800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 var:16 ARG2 =#+ &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sadalp/2@2 +# AUNIT --inst x4e606800/mask=xfffffc00 --status pass --comment "ext" +# Vector variant when 4S when size = 01 , Q = 1 Ta=VPR128.4S Tb=VPR128.8H e1=2 e2=4 s2=32 + +:sadalp Rd_VPR128.4S, Rn_VPR128.8H +is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000011010 & Rd_VPR128.4S & Rn_VPR128.8H & Zd +{ + TMPQ1 = 0; + # sipd infix TMPQ1 = +(Rn_VPR128.8H) on pairs lane size (2 to 4) + local tmp2 = Rn_VPR128.8H[0,16]; + local tmp4 = sext(tmp2); + local tmp3 = Rn_VPR128.8H[16,16]; + local tmp5 = sext(tmp3); + TMPQ1[0,32] = tmp4 + tmp5; + tmp2 = Rn_VPR128.8H[32,16]; + tmp4 = sext(tmp2); + tmp3 = Rn_VPR128.8H[48,16]; + tmp5 = sext(tmp3); + TMPQ1[32,32] = tmp4 + tmp5; + tmp2 = Rn_VPR128.8H[64,16]; + tmp4 = sext(tmp2); + tmp3 = Rn_VPR128.8H[80,16]; + tmp5 = sext(tmp3); + TMPQ1[64,32] = tmp4 + tmp5; + tmp2 = Rn_VPR128.8H[96,16]; + tmp4 = sext(tmp2); + tmp3 = Rn_VPR128.8H[112,16]; + tmp5 = sext(tmp3); + TMPQ1[96,32] = tmp4 + tmp5; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.228 SADALP page C7-2538 line 148486 MATCH x0e206800/mask=xbf3ffc00 +# CONSTRUCT x0ea06800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 var:8 ARG2 =#+ &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sadalp/2@4 +# AUNIT --inst x0ea06800/mask=xfffffc00 --status pass --comment "ext" +# Vector variant when 1D when size = 10 , Q = 0 Ta=VPR64.1D Tb=VPR64.2S e1=4 e2=8 s2=16 + +:sadalp Rd_VPR64.1D, Rn_VPR64.2S +is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000011010 & Rd_VPR64.1D & Rn_VPR64.2S & Zd +{ + TMPD1 = 0; + # sipd infix TMPD1 = +(Rn_VPR64.2S) on pairs lane size (4 to 8) + local tmp2 = Rn_VPR64.2S[0,32]; + local tmp4 = sext(tmp2); + local tmp3 = Rn_VPR64.2S[32,32]; + local tmp5 = sext(tmp3); + TMPD1 = tmp4 + tmp5; + # simd infix Rd_VPR64.1D = Rd_VPR64.1D + TMPD1 on lane size 8 + Rd_VPR64.1D = Rd_VPR64.1D + TMPD1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.228 SADALP page C7-2538 line 148486 MATCH x0e206800/mask=xbf3ffc00 +# CONSTRUCT x4ea06800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 var:16 ARG2 =#+ &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sadalp/2@4 +# AUNIT --inst x4ea06800/mask=xfffffc00 --status pass --comment "ext" +# Vector variant when 2D when size = 10 , Q = 1 Ta=VPR128.2D Tb=VPR128.4S e1=4 e2=8 s2=32 + +:sadalp Rd_VPR128.2D, Rn_VPR128.4S +is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000011010 & Rd_VPR128.2D & Rn_VPR128.4S & Zd +{ + TMPQ1 = 0; + # sipd infix TMPQ1 = +(Rn_VPR128.4S) on pairs lane size (4 to 8) + local tmp2 = Rn_VPR128.4S[0,32]; + local tmp4 = sext(tmp2); + local tmp3 = Rn_VPR128.4S[32,32]; + local tmp5 = sext(tmp3); + TMPQ1[0,64] = tmp4 + tmp5; + tmp2 = Rn_VPR128.4S[64,32]; + tmp4 = sext(tmp2); + tmp3 = Rn_VPR128.4S[96,32]; + tmp5 = sext(tmp3); + TMPQ1[64,64] = tmp4 + tmp5; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ1 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ1[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ1[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.229 SADDL, SADDL2 page C7-2540 line 148596 MATCH x0e200000/mask=xbf20fc00 +# CONSTRUCT x0ea00000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 =$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saddl/2@4 +# AUNIT --inst x0ea00000/mask=xffe0fc00 --status pass --comment "ext" + +:saddl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x0 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]); + # simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8) + TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]); + TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]); + # simd infix Rd_VPR128.2D = TMPQ1 + TMPQ2 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ1[0,64] + TMPQ2[0,64]; + Rd_VPR128.2D[64,64] = TMPQ1[64,64] + TMPQ2[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.229 SADDL, SADDL2 page C7-2540 line 148596 MATCH x0e200000/mask=xbf20fc00 +# CONSTRUCT x0e600000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 =$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddl/2@2 +# AUNIT --inst x0e600000/mask=xffe0fc00 --status pass --comment "ext" + +:saddl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x0 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]); + # simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4) + TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]); + TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]); + TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]); + TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]); + # simd infix Rd_VPR128.4S = TMPQ1 + TMPQ2 on lane size 4 + Rd_VPR128.4S[0,32] = TMPQ1[0,32] + TMPQ2[0,32]; + Rd_VPR128.4S[32,32] = TMPQ1[32,32] + TMPQ2[32,32]; + Rd_VPR128.4S[64,32] = TMPQ1[64,32] + TMPQ2[64,32]; + Rd_VPR128.4S[96,32] = TMPQ1[96,32] + TMPQ2[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.229 SADDL, SADDL2 page C7-2540 line 148596 MATCH x0e200000/mask=xbf20fc00 +# CONSTRUCT x0e200000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 =$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddl/2@1 +# AUNIT --inst x0e200000/mask=xffe0fc00 --status pass --comment "ext" + +:saddl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x0 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2) + TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]); + TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]); + TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]); + TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]); + TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]); + TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]); + TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]); + TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]); + # simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2) + TMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]); + TMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]); + TMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]); + TMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]); + TMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]); + TMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]); + TMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]); + TMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]); + # simd infix Rd_VPR128.8H = TMPQ1 + TMPQ2 on lane size 2 + Rd_VPR128.8H[0,16] = TMPQ1[0,16] + TMPQ2[0,16]; + Rd_VPR128.8H[16,16] = TMPQ1[16,16] + TMPQ2[16,16]; + Rd_VPR128.8H[32,16] = TMPQ1[32,16] + TMPQ2[32,16]; + Rd_VPR128.8H[48,16] = TMPQ1[48,16] + TMPQ2[48,16]; + Rd_VPR128.8H[64,16] = TMPQ1[64,16] + TMPQ2[64,16]; + Rd_VPR128.8H[80,16] = TMPQ1[80,16] + TMPQ2[80,16]; + Rd_VPR128.8H[96,16] = TMPQ1[96,16] + TMPQ2[96,16]; + Rd_VPR128.8H[112,16] = TMPQ1[112,16] + TMPQ2[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.229 SADDL, SADDL2 page C7-2540 line 148596 MATCH x0e200000/mask=xbf20fc00 +# CONSTRUCT x4ea00000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 =$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddl2/2@4 +# AUNIT --inst x4ea00000/mask=xffe0fc00 --status pass --comment "ext" + +:saddl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x0 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = sext(TMPD1[0,32]); + TMPQ2[64,64] = sext(TMPD1[32,32]); + TMPD3 = Rm_VPR128.4S[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8) + TMPQ4[0,64] = sext(TMPD3[0,32]); + TMPQ4[64,64] = sext(TMPD3[32,32]); + # simd infix Rd_VPR128.2D = TMPQ2 + TMPQ4 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ2[0,64] + TMPQ4[0,64]; + Rd_VPR128.2D[64,64] = TMPQ2[64,64] + TMPQ4[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.229 SADDL, SADDL2 page C7-2540 line 148596 MATCH x0e200000/mask=xbf20fc00 +# CONSTRUCT x4e600000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 =$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddl2/2@2 +# AUNIT --inst x4e600000/mask=xffe0fc00 --status pass --comment "ext" + +:saddl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x0 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = sext(TMPD1[0,16]); + TMPQ2[32,32] = sext(TMPD1[16,16]); + TMPQ2[64,32] = sext(TMPD1[32,16]); + TMPQ2[96,32] = sext(TMPD1[48,16]); + TMPD3 = Rm_VPR128.8H[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4) + TMPQ4[0,32] = sext(TMPD3[0,16]); + TMPQ4[32,32] = sext(TMPD3[16,16]); + TMPQ4[64,32] = sext(TMPD3[32,16]); + TMPQ4[96,32] = sext(TMPD3[48,16]); + # simd infix Rd_VPR128.4S = TMPQ2 + TMPQ4 on lane size 4 + Rd_VPR128.4S[0,32] = TMPQ2[0,32] + TMPQ4[0,32]; + Rd_VPR128.4S[32,32] = TMPQ2[32,32] + TMPQ4[32,32]; + Rd_VPR128.4S[64,32] = TMPQ2[64,32] + TMPQ4[64,32]; + Rd_VPR128.4S[96,32] = TMPQ2[96,32] + TMPQ4[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.229 SADDL, SADDL2 page C7-2540 line 148596 MATCH x0e200000/mask=xbf20fc00 +# CONSTRUCT x4e200000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 =$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddl2/2@1 +# AUNIT --inst x4e200000/mask=xffe0fc00 --status pass --comment "ext" + +:saddl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x0 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd +{ + TMPD1 = Rn_VPR128.16B[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2) + TMPQ2[0,16] = sext(TMPD1[0,8]); + TMPQ2[16,16] = sext(TMPD1[8,8]); + TMPQ2[32,16] = sext(TMPD1[16,8]); + TMPQ2[48,16] = sext(TMPD1[24,8]); + TMPQ2[64,16] = sext(TMPD1[32,8]); + TMPQ2[80,16] = sext(TMPD1[40,8]); + TMPQ2[96,16] = sext(TMPD1[48,8]); + TMPQ2[112,16] = sext(TMPD1[56,8]); + TMPD3 = Rm_VPR128.16B[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2) + TMPQ4[0,16] = sext(TMPD3[0,8]); + TMPQ4[16,16] = sext(TMPD3[8,8]); + TMPQ4[32,16] = sext(TMPD3[16,8]); + TMPQ4[48,16] = sext(TMPD3[24,8]); + TMPQ4[64,16] = sext(TMPD3[32,8]); + TMPQ4[80,16] = sext(TMPD3[40,8]); + TMPQ4[96,16] = sext(TMPD3[48,8]); + TMPQ4[112,16] = sext(TMPD3[56,8]); + # simd infix Rd_VPR128.8H = TMPQ2 + TMPQ4 on lane size 2 + Rd_VPR128.8H[0,16] = TMPQ2[0,16] + TMPQ4[0,16]; + Rd_VPR128.8H[16,16] = TMPQ2[16,16] + TMPQ4[16,16]; + Rd_VPR128.8H[32,16] = TMPQ2[32,16] + TMPQ4[32,16]; + Rd_VPR128.8H[48,16] = TMPQ2[48,16] + TMPQ4[48,16]; + Rd_VPR128.8H[64,16] = TMPQ2[64,16] + TMPQ4[64,16]; + Rd_VPR128.8H[80,16] = TMPQ2[80,16] + TMPQ4[80,16]; + Rd_VPR128.8H[96,16] = TMPQ2[96,16] + TMPQ4[96,16]; + Rd_VPR128.8H[112,16] = TMPQ2[112,16] + TMPQ4[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.230 SADDLP page C7-2542 line 148719 MATCH x0e202800/mask=xbf3ffc00 +# CONSTRUCT x0ea02800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =var =#+@4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlp/1@4 +# AUNIT --inst x0ea02800/mask=xfffffc00 --status pass --comment "ext" + +:saddlp Rd_VPR64.1D, Rn_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=2 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.1D & Zd +{ + TMPD1 = Rn_VPR64.2S; + # sipd infix Rd_VPR64.1D = +(TMPD1) on pairs lane size (4 to 8) + local tmp2 = TMPD1[0,32]; + local tmp4 = sext(tmp2); + local tmp3 = TMPD1[32,32]; + local tmp5 = sext(tmp3); + Rd_VPR64.1D = tmp4 + tmp5; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.230 SADDLP page C7-2542 line 148719 MATCH x0e202800/mask=xbf3ffc00 +# CONSTRUCT x0e602800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =var =#+@2 +# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlp/1@2 +# AUNIT --inst x0e602800/mask=xfffffc00 --status pass --comment "ext" + +:saddlp Rd_VPR64.2S, Rn_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=2 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.2S & Zd +{ + TMPD1 = Rn_VPR64.4H; + # sipd infix Rd_VPR64.2S = +(TMPD1) on pairs lane size (2 to 4) + local tmp2 = TMPD1[0,16]; + local tmp4 = sext(tmp2); + local tmp3 = TMPD1[16,16]; + local tmp5 = sext(tmp3); + Rd_VPR64.2S[0,32] = tmp4 + tmp5; + tmp2 = TMPD1[32,16]; + tmp4 = sext(tmp2); + tmp3 = TMPD1[48,16]; + tmp5 = sext(tmp3); + Rd_VPR64.2S[32,32] = tmp4 + tmp5; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.230 SADDLP page C7-2542 line 148719 MATCH x0e202800/mask=xbf3ffc00 +# CONSTRUCT x0e202800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =var =#+@1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlp/1@1 +# AUNIT --inst x0e202800/mask=xfffffc00 --status pass --comment "ext" + +:saddlp Rd_VPR64.4H, Rn_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=2 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.4H & Zd +{ + TMPD1 = Rn_VPR64.8B; + # sipd infix Rd_VPR64.4H = +(TMPD1) on pairs lane size (1 to 2) + local tmp2 = TMPD1[0,8]; + local tmp4 = sext(tmp2); + local tmp3 = TMPD1[8,8]; + local tmp5 = sext(tmp3); + Rd_VPR64.4H[0,16] = tmp4 + tmp5; + tmp2 = TMPD1[16,8]; + tmp4 = sext(tmp2); + tmp3 = TMPD1[24,8]; + tmp5 = sext(tmp3); + Rd_VPR64.4H[16,16] = tmp4 + tmp5; + tmp2 = TMPD1[32,8]; + tmp4 = sext(tmp2); + tmp3 = TMPD1[40,8]; + tmp5 = sext(tmp3); + Rd_VPR64.4H[32,16] = tmp4 + tmp5; + tmp2 = TMPD1[48,8]; + tmp4 = sext(tmp2); + tmp3 = TMPD1[56,8]; + tmp5 = sext(tmp3); + Rd_VPR64.4H[48,16] = tmp4 + tmp5; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.230 SADDLP page C7-2542 line 148719 MATCH x0e202800/mask=xbf3ffc00 +# CONSTRUCT x4ea02800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =var =#+@4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlp/1@4 +# AUNIT --inst x4ea02800/mask=xfffffc00 --status pass --comment "ext" + +:saddlp Rd_VPR128.2D, Rn_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=2 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPQ1 = Rn_VPR128.4S; + # sipd infix Rd_VPR128.2D = +(TMPQ1) on pairs lane size (4 to 8) + local tmp2 = TMPQ1[0,32]; + local tmp4 = sext(tmp2); + local tmp3 = TMPQ1[32,32]; + local tmp5 = sext(tmp3); + Rd_VPR128.2D[0,64] = tmp4 + tmp5; + tmp2 = TMPQ1[64,32]; + tmp4 = sext(tmp2); + tmp3 = TMPQ1[96,32]; + tmp5 = sext(tmp3); + Rd_VPR128.2D[64,64] = tmp4 + tmp5; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.230 SADDLP page C7-2542 line 148719 MATCH x0e202800/mask=xbf3ffc00 +# CONSTRUCT x4e602800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =var =#+@2 +# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlp/1@2 +# AUNIT --inst x4e602800/mask=xfffffc00 --status pass --comment "ext" + +:saddlp Rd_VPR128.4S, Rn_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=2 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPQ1 = Rn_VPR128.8H; + # sipd infix Rd_VPR128.4S = +(TMPQ1) on pairs lane size (2 to 4) + local tmp2 = TMPQ1[0,16]; + local tmp4 = sext(tmp2); + local tmp3 = TMPQ1[16,16]; + local tmp5 = sext(tmp3); + Rd_VPR128.4S[0,32] = tmp4 + tmp5; + tmp2 = TMPQ1[32,16]; + tmp4 = sext(tmp2); + tmp3 = TMPQ1[48,16]; + tmp5 = sext(tmp3); + Rd_VPR128.4S[32,32] = tmp4 + tmp5; + tmp2 = TMPQ1[64,16]; + tmp4 = sext(tmp2); + tmp3 = TMPQ1[80,16]; + tmp5 = sext(tmp3); + Rd_VPR128.4S[64,32] = tmp4 + tmp5; + tmp2 = TMPQ1[96,16]; + tmp4 = sext(tmp2); + tmp3 = TMPQ1[112,16]; + tmp5 = sext(tmp3); + Rd_VPR128.4S[96,32] = tmp4 + tmp5; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.230 SADDLP page C7-2542 line 148719 MATCH x0e202800/mask=xbf3ffc00 +# CONSTRUCT x4e202800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =var =#+@1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlp/1@1 +# AUNIT --inst x4e202800/mask=xfffffc00 --status pass --comment "ext" + +:saddlp Rd_VPR128.8H, Rn_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=2 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.8H & Zd +{ + TMPQ1 = Rn_VPR128.16B; + # sipd infix Rd_VPR128.8H = +(TMPQ1) on pairs lane size (1 to 2) + local tmp2 = TMPQ1[0,8]; + local tmp4 = sext(tmp2); + local tmp3 = TMPQ1[8,8]; + local tmp5 = sext(tmp3); + Rd_VPR128.8H[0,16] = tmp4 + tmp5; + tmp2 = TMPQ1[16,8]; + tmp4 = sext(tmp2); + tmp3 = TMPQ1[24,8]; + tmp5 = sext(tmp3); + Rd_VPR128.8H[16,16] = tmp4 + tmp5; + tmp2 = TMPQ1[32,8]; + tmp4 = sext(tmp2); + tmp3 = TMPQ1[40,8]; + tmp5 = sext(tmp3); + Rd_VPR128.8H[32,16] = tmp4 + tmp5; + tmp2 = TMPQ1[48,8]; + tmp4 = sext(tmp2); + tmp3 = TMPQ1[56,8]; + tmp5 = sext(tmp3); + Rd_VPR128.8H[48,16] = tmp4 + tmp5; + tmp2 = TMPQ1[64,8]; + tmp4 = sext(tmp2); + tmp3 = TMPQ1[72,8]; + tmp5 = sext(tmp3); + Rd_VPR128.8H[64,16] = tmp4 + tmp5; + tmp2 = TMPQ1[80,8]; + tmp4 = sext(tmp2); + tmp3 = TMPQ1[88,8]; + tmp5 = sext(tmp3); + Rd_VPR128.8H[80,16] = tmp4 + tmp5; + tmp2 = TMPQ1[96,8]; + tmp4 = sext(tmp2); + tmp3 = TMPQ1[104,8]; + tmp5 = sext(tmp3); + Rd_VPR128.8H[96,16] = tmp4 + tmp5; + tmp2 = TMPQ1[112,8]; + tmp4 = sext(tmp2); + tmp3 = TMPQ1[120,8]; + tmp5 = sext(tmp3); + Rd_VPR128.8H[112,16] = tmp4 + tmp5; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.231 SADDLV page C7-2544 line 148829 MATCH x0e303800/mask=xbf3ffc00 +# CONSTRUCT x4eb03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlv/1@4 +# AUNIT --inst x4eb03800/mask=xfffffc00 --status nopcodeop --comment "ext" + +:saddlv Rd_FPR64, Rn_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR128.4S & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_saddlv(Rn_VPR128.4S, 4:1); +} + +# C7.2.231 SADDLV page C7-2544 line 148829 MATCH x0e303800/mask=xbf3ffc00 +# CONSTRUCT x4e303800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlv/1@1 +# AUNIT --inst x4e303800/mask=xfffffc00 --status nopcodeop --comment "ext" + +:saddlv Rd_FPR16, Rn_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR128.16B & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_saddlv(Rn_VPR128.16B, 1:1); +} + +# C7.2.231 SADDLV page C7-2544 line 148829 MATCH x0e303800/mask=xbf3ffc00 +# CONSTRUCT x0e303800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlv/1@1 +# AUNIT --inst x0e303800/mask=xfffffc00 --status nopcodeop --comment "ext" + +:saddlv Rd_FPR16, Rn_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR64.8B & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_saddlv(Rn_VPR64.8B, 1:1); +} + +# C7.2.231 SADDLV page C7-2544 line 148829 MATCH x0e303800/mask=xbf3ffc00 +# CONSTRUCT x0e703800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlv/1@2 +# AUNIT --inst x0e703800/mask=xfffffc00 --status nopcodeop --comment "ext" + +:saddlv Rd_FPR32, Rn_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR64.4H & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_saddlv(Rn_VPR64.4H, 2:1); +} + +# C7.2.231 SADDLV page C7-2544 line 148829 MATCH x0e303800/mask=xbf3ffc00 +# CONSTRUCT x4e703800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlv/1@2 +# AUNIT --inst x4e703800/mask=xfffffc00 --status nopcodeop --comment "ext" + +:saddlv Rd_FPR32, Rn_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR128.8H & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_saddlv(Rn_VPR128.8H, 2:1); +} + +# C7.2.232 SADDW, SADDW2 page C7-2546 line 148929 MATCH x0e201000/mask=xbf20fc00 +# CONSTRUCT x0ea01000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $sext@4:16 =$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddw/2@4 +# AUNIT --inst x0ea01000/mask=xffe0fc00 --status pass --comment "ext" + +:saddw Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x1 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = sext(Rm_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = sext(Rm_VPR64.2S[0,32]); + TMPQ1[64,64] = sext(Rm_VPR64.2S[32,32]); + # simd infix Rd_VPR128.2D = Rn_VPR128.2D + TMPQ1 on lane size 8 + Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] + TMPQ1[0,64]; + Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] + TMPQ1[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.232 SADDW, SADDW2 page C7-2546 line 148929 MATCH x0e201000/mask=xbf20fc00 +# CONSTRUCT x0e601000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $sext@2:16 =$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddw/2@2 +# AUNIT --inst x0e601000/mask=xffe0fc00 --status pass --comment "ext" + +:saddw Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x1 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = sext(Rm_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = sext(Rm_VPR64.4H[0,16]); + TMPQ1[32,32] = sext(Rm_VPR64.4H[16,16]); + TMPQ1[64,32] = sext(Rm_VPR64.4H[32,16]); + TMPQ1[96,32] = sext(Rm_VPR64.4H[48,16]); + # simd infix Rd_VPR128.4S = Rn_VPR128.4S + TMPQ1 on lane size 4 + Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] + TMPQ1[0,32]; + Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] + TMPQ1[32,32]; + Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] + TMPQ1[64,32]; + Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] + TMPQ1[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.232 SADDW, SADDW2 page C7-2546 line 148929 MATCH x0e201000/mask=xbf20fc00 +# CONSTRUCT x0e201000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $sext@1:16 =$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddw/2@1 +# AUNIT --inst x0e201000/mask=xffe0fc00 --status pass --comment "ext" + +:saddw Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x1 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + # simd resize TMPQ1 = sext(Rm_VPR64.8B) (lane size 1 to 2) + TMPQ1[0,16] = sext(Rm_VPR64.8B[0,8]); + TMPQ1[16,16] = sext(Rm_VPR64.8B[8,8]); + TMPQ1[32,16] = sext(Rm_VPR64.8B[16,8]); + TMPQ1[48,16] = sext(Rm_VPR64.8B[24,8]); + TMPQ1[64,16] = sext(Rm_VPR64.8B[32,8]); + TMPQ1[80,16] = sext(Rm_VPR64.8B[40,8]); + TMPQ1[96,16] = sext(Rm_VPR64.8B[48,8]); + TMPQ1[112,16] = sext(Rm_VPR64.8B[56,8]); + # simd infix Rd_VPR128.8H = Rn_VPR128.8H + TMPQ1 on lane size 2 + Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] + TMPQ1[0,16]; + Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] + TMPQ1[16,16]; + Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] + TMPQ1[32,16]; + Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] + TMPQ1[48,16]; + Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] + TMPQ1[64,16]; + Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] + TMPQ1[80,16]; + Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] + TMPQ1[96,16]; + Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] + TMPQ1[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.232 SADDW, SADDW2 page C7-2546 line 148929 MATCH x0e201000/mask=xbf20fc00 +# CONSTRUCT x4ea01000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3[1]:8 $sext@4:16 =$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddw2/2@4 +# AUNIT --inst x4ea01000/mask=xffe0fc00 --status pass --comment "ext" + +:saddw2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x1 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + TMPD1 = Rm_VPR128.4S[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = sext(TMPD1[0,32]); + TMPQ2[64,64] = sext(TMPD1[32,32]); + # simd infix Rd_VPR128.2D = Rn_VPR128.2D + TMPQ2 on lane size 8 + Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] + TMPQ2[0,64]; + Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] + TMPQ2[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.232 SADDW, SADDW2 page C7-2546 line 148929 MATCH x0e201000/mask=xbf20fc00 +# CONSTRUCT x4e601000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3[1]:8 $sext@2:16 =$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddw2/2@2 +# AUNIT --inst x4e601000/mask=xffe0fc00 --status pass --comment "ext" + +:saddw2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x1 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + TMPD1 = Rm_VPR128.8H[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = sext(TMPD1[0,16]); + TMPQ2[32,32] = sext(TMPD1[16,16]); + TMPQ2[64,32] = sext(TMPD1[32,16]); + TMPQ2[96,32] = sext(TMPD1[48,16]); + # simd infix Rd_VPR128.4S = Rn_VPR128.4S + TMPQ2 on lane size 4 + Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] + TMPQ2[0,32]; + Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] + TMPQ2[32,32]; + Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] + TMPQ2[64,32]; + Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] + TMPQ2[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.232 SADDW, SADDW2 page C7-2546 line 148929 MATCH x0e201000/mask=xbf20fc00 +# CONSTRUCT x4e201000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3[1]:8 $sext@1:16 =$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddw2/2@1 +# AUNIT --inst x4e201000/mask=xffe0fc00 --status pass --comment "ext" + +:saddw2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x1 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + TMPD1 = Rm_VPR128.16B[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2) + TMPQ2[0,16] = sext(TMPD1[0,8]); + TMPQ2[16,16] = sext(TMPD1[8,8]); + TMPQ2[32,16] = sext(TMPD1[16,8]); + TMPQ2[48,16] = sext(TMPD1[24,8]); + TMPQ2[64,16] = sext(TMPD1[32,8]); + TMPQ2[80,16] = sext(TMPD1[40,8]); + TMPQ2[96,16] = sext(TMPD1[48,8]); + TMPQ2[112,16] = sext(TMPD1[56,8]); + # simd infix Rd_VPR128.8H = Rn_VPR128.8H + TMPQ2 on lane size 2 + Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] + TMPQ2[0,16]; + Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] + TMPQ2[16,16]; + Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] + TMPQ2[32,16]; + Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] + TMPQ2[48,16]; + Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] + TMPQ2[64,16]; + Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] + TMPQ2[80,16]; + Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] + TMPQ2[96,16]; + Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] + TMPQ2[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x5f00e400/mask=xff80fc00 +# CONSTRUCT x5f40e400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2 +# AUNIT --inst x5f40e400/mask=xffc0fc00 --status nopcodeop --comment "nofpround" + +:scvtf Rd_FPR64, Rn_FPR64, Imm_shr_imm64 +is b_3031=1 & u=0 & b_2428=0x1f & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x1c & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_scvtf(Rn_FPR64, Imm_shr_imm64:4); +} + +# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x5f00e400/mask=xff80fc00 +# CONSTRUCT x5f20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2 +# AUNIT --inst x5f20e400/mask=xffe0fc00 --status nopcodeop --comment "nofpround" + +:scvtf Rd_FPR32, Rn_FPR32, Imm_shr_imm32 +is b_3031=1 & u=0 & b_2428=0x1f & b_2123=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_scvtf(Rn_FPR32, Imm_shr_imm32:4); +} + +# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x5f00e400/mask=xff80fc00 +# CONSTRUCT x5f10e400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2 +# AUNIT --inst x5f10e400/mask=xfff0fc00 --status noqemu --comment "nofpround" + +:scvtf Rd_FPR16, Rn_FPR16, Imm_shr_imm16 +is b_3031=1 & u=0 & b_2428=0x1f & b_2023=1 & Imm_shr_imm16 & b_1115=0x1c & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_scvtf(Rn_FPR16, Imm_shr_imm16:4); +} + +# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x0f00e400/mask=xbf80fc00 +# CONSTRUCT x4f40e400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2@8 +# AUNIT --inst x4f40e400/mask=xffc0fc00 --status nopcodeop --comment "nofpround" + +:scvtf Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x1c & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_scvtf(Rn_VPR128.2D, Imm_shr_imm64:4, 8:1); +} + +# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x0f00e400/mask=xbf80fc00 +# CONSTRUCT x0f20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2@4 +# AUNIT --inst x0f20e400/mask=xffe0fc00 --status nopcodeop --comment "nofpround" + +:scvtf Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_scvtf(Rn_VPR64.2S, Imm_shr_imm32:4, 4:1); +} + +# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x0f00e400/mask=xbf80fc00 +# CONSTRUCT x4f20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2@4 +# AUNIT --inst x4f20e400/mask=xffe0fc00 --status nopcodeop --comment "nofpround" + +:scvtf Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_scvtf(Rn_VPR128.4S, Imm_shr_imm32:4, 4:1); +} + +# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x0f00e400/mask=xbf80fc00 +# CONSTRUCT x0f10e400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2@2 +# AUNIT --inst x0f10e400/mask=xfff0fc00 --status noqemu --comment "nofpround" + +:scvtf Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm32 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_scvtf(Rn_VPR64.4H, Imm_shr_imm32:4, 2:1); +} + +# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x0f00e400/mask=xbf80fc00 +# CONSTRUCT x4f10e400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2@2 +# AUNIT --inst x4f10e400/mask=xfff0fc00 --status noqemu --comment "nofpround" + +:scvtf Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm32 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_scvtf(Rn_VPR128.8H, Imm_shr_imm32:4, 2:1); +} + +# C7.2.234 SCVTF (vector, integer) page C7-2551 line 149206 MATCH x5e21d800/mask=xffbffc00 +# CONSTRUCT x5e21d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =int2float +# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1 +# AUNIT --inst x5e21d800/mask=xfffffc00 --status fail --comment "nofpround" + +:scvtf Rd_FPR32, Rn_FPR32 +is b_3031=1 & u=0 & b_2428=0x1e & size_high=0 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = int2float(Rn_FPR32); + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.234 SCVTF (vector, integer) page C7-2551 line 149206 MATCH x5e21d800/mask=xffbffc00 +# CONSTRUCT x5e61d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =int2float +# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1 +# AUNIT --inst x5e61d800/mask=xfffffc00 --status pass --comment "nofpround" + +:scvtf Rd_FPR64, Rn_FPR64 +is b_3031=1 & u=0 & b_2428=0x1e & size_high=0 & b_1722=0x30 & b_1216=0x1d & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = int2float(Rn_FPR64); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.234 SCVTF (vector, integer) page C7-2551 line 149206 MATCH x0e21d800/mask=xbfbffc00 +# CONSTRUCT x4e61d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1@8 +# AUNIT --inst x4e61d800/mask=xfffffc00 --status nopcodeop --comment "nofpround" + +:scvtf Rd_VPR128.2D, Rn_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & size_high=0 & b_1722=0x30 & b_1216=0x1d & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_scvtf(Rn_VPR128.2D, 8:1); +} + +# C7.2.234 SCVTF (vector, integer) page C7-2551 line 149206 MATCH x0e21d800/mask=xbfbffc00 +# CONSTRUCT x0e21d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1@4 +# AUNIT --inst x0e21d800/mask=xfffffc00 --status nopcodeop --comment "nofpround" + +:scvtf Rd_VPR64.2S, Rn_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & size_high=0 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_scvtf(Rn_VPR64.2S, 4:1); +} + +# C7.2.234 SCVTF (vector, integer) page C7-2551 line 149206 MATCH x0e21d800/mask=xbfbffc00 +# CONSTRUCT x4e21d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1@4 +# AUNIT --inst x4e21d800/mask=xfffffc00 --status nopcodeop --comment "nofpround" + +:scvtf Rd_VPR128.4S, Rn_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & size_high=0 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_scvtf(Rn_VPR128.4S, 4:1); +} + +# C7.2.234 SCVTF (vector, integer) page C7-2551 line 149206 MATCH x5e79d800/mask=xfffffc00 +# CONSTRUCT x5e79d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =int2float +# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1 +# AUNIT --inst x5e79d800/mask=xfffffc00 --status noqemu --comment "nofpround" +# Scalar half precision variant + +:scvtf Rd_FPR16, Rn_FPR16 +is b_1031=0b0101111001111001110110 & Rd_FPR16 & Rn_FPR16 & Zd +{ + Rd_FPR16 = int2float(Rn_FPR16); + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.234 SCVTF (vector, integer) page C7-2551 line 149206 MATCH x0e79d800/mask=xbffffc00 +# CONSTRUCT x0e79d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1@2 +# AUNIT --inst x0e79d800/mask=xfffffc00 --status noqemu --comment "nofpround" +# Vector half precision variant when Q=0 suf=VPR64.4H + +:scvtf Rd_VPR64.4H, Rn_VPR64.4H +is b_31=0 & b_30=0 & b_1029=0b00111001111001110110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_scvtf(Rn_VPR64.4H, 2:1); +} + +# C7.2.234 SCVTF (vector, integer) page C7-2551 line 149206 MATCH x0e79d800/mask=xbffffc00 +# CONSTRUCT x4e79d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1@2 +# AUNIT --inst x4e79d800/mask=xfffffc00 --status noqemu --comment "nofpround" +# Vector half precision variant when Q=1 suf=VPR128.8H + +:scvtf Rd_VPR128.8H, Rn_VPR128.8H +is b_31=0 & b_30=1 & b_1029=0b00111001111001110110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_scvtf(Rn_VPR128.8H, 2:1); +} + +# C7.2.235 SCVTF (scalar, fixed-point) page C7-2554 line 149390 MATCH x1e020000/mask=x7f3f0000 +# CONSTRUCT x1ec28000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 int2float:2 FBits16 =f/ +# SMACRO(pseudo) ARG1 ARG2 FBits16 =NEON_scvtf/2 +# AUNIT --inst x1ec28000/mask=xffff8000 --status noqemu --comment "nofpround" +# 32-bit to half-precision variant when sf == 0 && type == 11 + +:scvtf Rd_FPR16, Rn_GPR32, FBitsOp +is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=0 & mode=0 & fpOpcode=2 & b_15=1 & FBitsOp & FBits16 & Rn_GPR32 & Rd_FPR16 & Zd +{ + local tmp1:2 = int2float(Rn_GPR32); + Rd_FPR16 = tmp1 f/ FBits16; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.235 SCVTF (scalar, fixed-point) page C7-2554 line 149390 MATCH x1e020000/mask=x7f3f0000 +# CONSTRUCT x9ec20000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 int2float:2 FBits16 =f/ +# SMACRO(pseudo) ARG1 ARG2 FBits16 =NEON_scvtf/2 +# AUNIT --inst x9ec20000/mask=xffff0000 --status noqemu --comment "nofpround" +# 64-bit to half-precision variant when sf == 1 && type == 11 + +:scvtf Rd_FPR16, Rn_GPR64, FBitsOp +is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=0 & mode=0 & fpOpcode=2 & FBitsOp & FBits16 & Rn_GPR64 & Rd_FPR16 & Zd +{ + local tmp1:2 = int2float(Rn_GPR64); + Rd_FPR16 = tmp1 f/ FBits16; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.235 SCVTF (scalar, fixed-point) page C7-2554 line 149390 MATCH x1e020000/mask=x7f3f0000 +# CONSTRUCT x1e428000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 int2float:8 FBits64 =f/ +# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_scvtf/2 +# AUNIT --inst x1e428000/mask=xffff8000 --status pass --comment "nofpround" + +:scvtf Rd_FPR64, Rn_GPR32, FBitsOp +is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=0 & mode=0 & fpOpcode=2 & b_15=1 & FBitsOp & FBits64 & Rn_GPR32 & Rd_FPR64 & Zd +{ + local tmp1:8 = int2float(Rn_GPR32); + Rd_FPR64 = tmp1 f/ FBits64; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.235 SCVTF (scalar, fixed-point) page C7-2554 line 149390 MATCH x1e020000/mask=x7f3f0000 +# CONSTRUCT x1e028000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 int2float FBits32 =f/ +# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_scvtf/2 +# AUNIT --inst x1e028000/mask=xffff8000 --status fail --comment "nofpround" + +:scvtf Rd_FPR32, Rn_GPR32, FBitsOp +is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=0 & mode=0 & fpOpcode=2 & b_15=1 & FBitsOp & FBits32 & Rn_GPR32 & Rd_FPR32 & Zd +{ + local tmp1:4 = int2float(Rn_GPR32); + Rd_FPR32 = tmp1 f/ FBits32; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.235 SCVTF (scalar, fixed-point) page C7-2554 line 149390 MATCH x1e020000/mask=x7f3f0000 +# CONSTRUCT x9e420000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 int2float FBits64 =f/ +# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_scvtf/2 +# AUNIT --inst x9e420000/mask=xffff0000 --status fail --comment "nofpround" + +:scvtf Rd_FPR64, Rn_GPR64, FBitsOp +is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=0 & mode=0 & fpOpcode=2 & FBitsOp & FBits64 & Rn_GPR64 & Rd_FPR64 & Zd +{ + local tmp1:8 = int2float(Rn_GPR64); + Rd_FPR64 = tmp1 f/ FBits64; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.235 SCVTF (scalar, fixed-point) page C7-2554 line 149390 MATCH x1e020000/mask=x7f3f0000 +# CONSTRUCT x9e020000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 int2float:4 FBits32 =f/ +# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_scvtf/2 +# AUNIT --inst x9e020000/mask=xffff0000 --status fail --comment "nofpround" + +:scvtf Rd_FPR32, Rn_GPR64, FBitsOp +is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=0 & mode=0 & fpOpcode=2 & FBitsOp & FBits32 & Rn_GPR64 & Rd_FPR32 & Rd_FPR64 & Zd +{ + local tmp1:4 = int2float(Rn_GPR64); + Rd_FPR32 = tmp1 f/ FBits32; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.236 SCVTF (scalar, integer) page C7-2556 line 149525 MATCH x1e220000/mask=x7f3ffc00 +# CONSTRUCT x1ee20000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =int2float/1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1 +# AUNIT --inst x1ee20000/mask=xfffffc00 --status noqemu --comment "nofpround" + +:scvtf Rd_FPR16, Rn_GPR32 +is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & rmode=0 & fpOpcode=2 & b_1015=0x0 & Rn_GPR32 & Rd_FPR16 & Zd +{ + Rd_FPR16 = int2float(Rn_GPR32); + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.236 SCVTF (scalar, integer) page C7-2556 line 149525 MATCH x1e220000/mask=x7f3ffc00 +# CONSTRUCT x9ee20000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =int2float/1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1 +# AUNIT --inst x9ee20000/mask=xfffffc00 --status noqemu --comment "nofpround" + +:scvtf Rd_FPR16, Rn_GPR64 +is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & rmode=0 & fpOpcode=2 & b_1015=0x0 & Rn_GPR64 & Rd_FPR16 & Zd +{ + Rd_FPR16 = int2float(Rn_GPR64); + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.236 SCVTF (scalar, integer) page C7-2556 line 149525 MATCH x1e220000/mask=x7f3ffc00 +# CONSTRUCT x1e620000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =int2float/1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1 +# AUNIT --inst x1e620000/mask=xfffffc00 --status pass --comment "nofpround" + +:scvtf Rd_FPR64, Rn_GPR32 +is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & rmode=0 & fpOpcode=2 & b_1015=0x0 & Rn_GPR32 & Rd_FPR64 & Zd +{ + Rd_FPR64 = int2float(Rn_GPR32); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.236 SCVTF (scalar, integer) page C7-2556 line 149525 MATCH x1e220000/mask=x7f3ffc00 +# CONSTRUCT x9e620000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =int2float/1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1 +# AUNIT --inst x9e620000/mask=xfffffc00 --status pass --comment "nofpround" + +:scvtf Rd_FPR64, Rn_GPR64 +is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & rmode=0 & fpOpcode=2 & b_1015=0x0 & Rn_GPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = int2float(Rn_GPR64); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.236 SCVTF (scalar, integer) page C7-2556 line 149525 MATCH x1e220000/mask=x7f3ffc00 +# CONSTRUCT x1e220000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =int2float/1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1 +# AUNIT --inst x1e220000/mask=xfffffc00 --status fail --comment "nofpround" + +:scvtf Rd_FPR32, Rn_GPR32 +is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & rmode=0 & fpOpcode=2 & b_1015=0x0 & Rn_GPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = int2float(Rn_GPR32); + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.236 SCVTF (scalar, integer) page C7-2556 line 149525 MATCH x1e220000/mask=x7f3ffc00 +# CONSTRUCT x9e220000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =int2float/1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1 +# AUNIT --inst x9e220000/mask=xfffffc00 --status fail --comment "nofpround" + +:scvtf Rd_FPR32, Rn_GPR64 +is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & rmode=0 & fpOpcode=2 & b_1015=0x0 & Rn_GPR64 & Rd_FPR32 & Zd +{ + Rd_FPR32 = int2float(Rn_GPR64); + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.237 SDOT (by element) page C7-2558 line 149653 MATCH x0f00e000/mask=xbf00f400 +# CONSTRUCT x0f80e000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 Re_VPR128.S.vIndex =NEON_sdot/2@1 +# AUNIT --inst x0f80e000/mask=xffc0f400 --status noqemu +# Vector variant when Q=0 Ta=64.2S Tb=64.8B + +:sdot Rd_VPR64.2S, Rn_VPR64.8B, Re_VPR128.B.vIndex +is b_31=0 & b_30=0 & b_2429=0b001111 & b_2223=0b10 & b_1215=0b1110 & b_10=0 & Rd_VPR64.2S & Rn_VPR64.8B & Re_VPR128.B.vIndex & Re_VPR128.S & vIndex & Zd +{ + local tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1); + Rd_VPR64.2S = NEON_sdot(Rn_VPR64.8B, tmp1, 1:1); +} + +# C7.2.237 SDOT (by element) page C7-2558 line 149653 MATCH x0f00e000/mask=xbf00f400 +# CONSTRUCT x4f80e000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 Re_VPR128.S.vIndex =NEON_sdot/2@1 +# AUNIT --inst x4f80e000/mask=xffc0f400 --status noqemu +# Vector variant when Q=1 Ta=128.4S Tb=128.16B + +:sdot Rd_VPR128.4S, Rn_VPR128.16B, Re_VPR128.B.vIndex +is b_31=0 & b_30=1 & b_2429=0b001111 & b_2223=0b10 & b_1215=0b1110 & b_10=0 & Rd_VPR128.4S & Rn_VPR128.16B & Re_VPR128.B.vIndex & Re_VPR128.S & vIndex & Zd +{ + local tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1); + Rd_VPR128.4S = NEON_sdot(Rn_VPR128.16B, tmp1, 1:1); +} + +# C7.2.238 SDOT (vector) page C7-2560 line 149755 MATCH x0e009400/mask=xbf20fc00 +# CONSTRUCT x0e809400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sdot/2@1 +# AUNIT --inst x0e809400/mask=xffe0fc00 --status noqemu +# Three registers of the same type variant when Q=0 Ta=64.2S Tb=64.8B + +:sdot Rd_VPR64.2S, Rn_VPR64.8B, Rm_VPR64.8B +is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_21=0 & b_1015=0b100101 & Rd_VPR64.2S & Rn_VPR64.8B & Rm_VPR64.8B & Zd +{ + Rd_VPR64.2S = NEON_sdot(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.238 SDOT (vector) page C7-2560 line 149755 MATCH x0e009400/mask=xbf20fc00 +# CONSTRUCT x4e809400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sdot/2@1 +# AUNIT --inst x4e809400/mask=xffe0fc00 --status noqemu +# Three registers of the same type variant when Q=1 Ta=128.4S Tb=128.16B + +:sdot Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B +is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_21=0 & b_1015=0b100101 & Rd_VPR128.4S & Rn_VPR128.16B & Rm_VPR128.16B & Zd +{ + Rd_VPR128.4S = NEON_sdot(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.239 SHA1C page C7-2562 line 149854 MATCH x5e000000/mask=xffe0fc00 +# CONSTRUCT x5e000000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha1c/3@4 +# AUNIT --inst x5e000000/mask=xffe0fc00 --status noqemu + +:sha1c Rd_VPR128, Rn_FPR32, Rm_VPR128.4S +is b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b000000 & Rn_FPR32 & Rd_VPR128 & Zd +{ + Rd_VPR128 = NEON_sha1c(Rd_VPR128, Rn_FPR32, Rm_VPR128.4S, 4:1); +} + +# C7.2.240 SHA1H page C7-2563 line 149925 MATCH x5e280800/mask=xfffffc00 +# CONSTRUCT x5e280800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 30:1 =<< +# SMACRO(pseudo) ARG1 ARG2 =NEON_sha1h/1 +# AUNIT --inst x5e280800/mask=xfffffc00 --status noqemu + +:sha1h Rd_FPR32, Rn_FPR32 +is b_2431=0b01011110 & b_2223=0b00 & b_1721=0b10100 & b_1216=0b00000 & b_1011=0b10 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = Rn_FPR32 << 30:1; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.241 SHA1M page C7-2564 line 149984 MATCH x5e002000/mask=xffe0fc00 +# CONSTRUCT x5e002000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha1m/3@4 +# AUNIT --inst x5e002000/mask=xffe0fc00 --status noqemu + +:sha1m Rd_VPR128, Rn_FPR32, Rm_VPR128.4S +is b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b001000 & Rn_FPR32 & Rd_VPR128 & Zd +{ + Rd_VPR128 = NEON_sha1m(Rd_VPR128, Rn_FPR32, Rm_VPR128.4S, 4:1); +} + +# C7.2.242 SHA1P page C7-2565 line 150055 MATCH x5e001000/mask=xffe0fc00 +# CONSTRUCT x5e001000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha1p/3@4 +# AUNIT --inst x5e001000/mask=xffe0fc00 --status noqemu + +:sha1p Rd_VPR128, Rn_FPR32, Rm_VPR128.4S +is b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b000100 & Rn_FPR32 & Rd_VPR128 & Zd +{ + Rd_VPR128 = NEON_sha1p(Rd_VPR128, Rn_FPR32, Rm_VPR128.4S, 4:1); +} + +# C7.2.243 SHA1SU0 page C7-2566 line 150126 MATCH x5e003000/mask=xffe0fc00 +# CONSTRUCT x5e003000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha1su0/3@4 +# AUNIT --inst x5e003000/mask=xffe0fc00 --status noqemu + +:sha1su0 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b001100 & Rn_VPR128.4S & Rd_VPR128.4S & Rd_VPR128 & Zd +{ + Rd_VPR128.4S = NEON_sha1su0(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.244 SHA1SU1 page C7-2567 line 150194 MATCH x5e281800/mask=xfffffc00 +# CONSTRUCT x5e281800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sha1su1/2@4 +# AUNIT --inst x5e281800/mask=xfffffc00 --status noqemu + +:sha1su1 Rd_VPR128.4S, Rn_VPR128.4S +is b_2431=0b01011110 & b_2223=0b00 & b_2121=1 & b_1620=0b01000 & b_1015=0b000110 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sha1su1(Rd_VPR128.4S, Rn_VPR128.4S, 4:1); +} + +# C7.2.245 SHA256H2 page C7-2568 line 150260 MATCH x5e005000/mask=xffe0fc00 +# CONSTRUCT x5e005000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha256h2/3@4 +# AUNIT --inst x5e005000/mask=xffe0fc00 --status noqemu + +:sha256h2 Rd_VPR128, Rn_VPR128, Rm_VPR128.4S +is b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b010100 & Rn_VPR128 & Rd_VPR128 & Zd +{ + Rd_VPR128 = NEON_sha256h2(Rd_VPR128, Rn_VPR128, Rm_VPR128.4S, 4:1); +} + +# C7.2.246 SHA256H page C7-2569 line 150322 MATCH x5e004000/mask=xffe0fc00 +# CONSTRUCT x5e004000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha256h/3@4 +# AUNIT --inst x5e004000/mask=xffe0fc00 --status noqemu + +:sha256h Rd_VPR128, Rn_VPR128, Rm_VPR128.4S +is b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b010000 & Rn_VPR128 & Rd_VPR128 & Zd +{ + Rd_VPR128 = NEON_sha256h(Rd_VPR128, Rn_VPR128, Rm_VPR128.4S, 4:1); +} + +# C7.2.247 SHA256SU0 page C7-2570 line 150384 MATCH x5e282800/mask=xfffffc00 +# CONSTRUCT x5e282800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sha256su0/2@4 +# AUNIT --inst x5e282800/mask=xfffffc00 --status noqemu + +:sha256su0 Rd_VPR128.4S, Rn_VPR128.4S +is b_2431=0b01011110 & b_2223=0b00 & b_2121=1 & b_1620=0b01000 & b_1015=0b001010 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sha256su0(Rd_VPR128.4S, Rn_VPR128.4S, 4:1); +} + +# C7.2.248 SHA256SU1 page C7-2571 line 150452 MATCH x5e006000/mask=xffe0fc00 +# CONSTRUCT x5e006000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha256su1/3@4 +# AUNIT --inst x5e006000/mask=xffe0fc00 --status noqemu + +:sha256su1 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b011000 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sha256su1(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.249 SHA512H page C7-2573 line 150543 MATCH xce608000/mask=xffe0fc00 +# CONSTRUCT xce608000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha512h/3@8 +# AUNIT --inst xce608000/mask=xffe0fc00 --status noqemu + +:sha512h Rd_VPR128, Rn_VPR128, Rm_VPR128.2D +is b_2131=0b11001110011 & b_1015=0b100000 & Rd_VPR128 & Rn_VPR128 & Rm_VPR128.2D & Zd +{ + Rd_VPR128 = NEON_sha512h(Rd_VPR128, Rn_VPR128, Rm_VPR128.2D, 8:1); +} + +# C7.2.250 SHA512H2 page C7-2575 line 150631 MATCH xce608400/mask=xffe0fc00 +# CONSTRUCT xce608400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha512h2/3@8 +# AUNIT --inst xce608400/mask=xffe0fc00 --status noqemu + +:sha512h2 Rd_VPR128, Rn_VPR128, Rm_VPR128.2D +is b_2131=0b11001110011 & b_1015=0b100001 & Rd_VPR128 & Rn_VPR128 & Rm_VPR128.2D & Zd +{ + Rd_VPR128 = NEON_sha512h2(Rd_VPR128, Rn_VPR128, Rm_VPR128.2D, 8:1); +} + +# C7.2.251 SHA512SU0 page C7-2577 line 150719 MATCH xcec08000/mask=xfffffc00 +# CONSTRUCT xcec08000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sha512su0/2@8 +# AUNIT --inst xcec08000/mask=xfffffc00 --status noqemu + +:sha512su0 Rd_VPR128.2D, Rn_VPR128.2D +is b_1031=0b1100111011000000100000 & Rd_VPR128.2D & Rn_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_sha512su0(Rd_VPR128.2D, Rn_VPR128.2D, 8:1); +} + +# C7.2.252 SHA512SU1 page C7-2578 line 150789 MATCH xce608800/mask=xffe0fc00 +# CONSTRUCT xce608800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha512su1/3@8 +# AUNIT --inst xce608800/mask=xffe0fc00 --status noqemu + +:sha512su1 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_2131=0b11001110011 & b_1015=0b100010 & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_sha512su1(Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.253 SHADD page C7-2580 line 150875 MATCH x0e200400/mask=xbf20fc00 +# CONSTRUCT x4e200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shadd/2@1 +# AUNIT --inst x4e200400/mask=xffe0fc00 --status nopcodeop + +:shadd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x0 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_shadd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.253 SHADD page C7-2580 line 150875 MATCH x0e200400/mask=xbf20fc00 +# CONSTRUCT x0ea00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shadd/2@4 +# AUNIT --inst x0ea00400/mask=xffe0fc00 --status nopcodeop + +:shadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x0 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_shadd(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.253 SHADD page C7-2580 line 150875 MATCH x0e200400/mask=xbf20fc00 +# CONSTRUCT x0e600400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shadd/2@2 +# AUNIT --inst x0e600400/mask=xffe0fc00 --status nopcodeop + +:shadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x0 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_shadd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.253 SHADD page C7-2580 line 150875 MATCH x0e200400/mask=xbf20fc00 +# CONSTRUCT x4ea00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shadd/2@4 +# AUNIT --inst x4ea00400/mask=xffe0fc00 --status nopcodeop + +:shadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x0 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_shadd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.253 SHADD page C7-2580 line 150875 MATCH x0e200400/mask=xbf20fc00 +# CONSTRUCT x0e200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shadd/2@1 +# AUNIT --inst x0e200400/mask=xffe0fc00 --status nopcodeop + +:shadd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x0 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_shadd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.253 SHADD page C7-2580 line 150875 MATCH x0e200400/mask=xbf20fc00 +# CONSTRUCT x4e600400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shadd/2@2 +# AUNIT --inst x4e600400/mask=xffe0fc00 --status nopcodeop + +:shadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x0 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_shadd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.254 SHL page C7-2582 line 150977 MATCH x5f005400/mask=xff80fc00 +# CONSTRUCT x5f405400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2 +# AUNIT --inst x5f405400/mask=xffc0fc00 --status nopcodeop + +:shl Rd_FPR64, Rn_FPR64, Imm_imm0_63 +is b_3031=1 & u=0 & b_2428=0x1f & b_2223=0b01 & Imm_imm0_63 & b_1115=0xa & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_shl(Rn_FPR64, Imm_imm0_63:1); +} + +# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00 +# CONSTRUCT x4f085400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =var:1 =$<<@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@1 +# AUNIT --inst x4f085400/mask=xfff8fc00 --status pass + +:shl Rd_VPR128.16B, Rn_VPR128.16B, Imm_uimm3 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xa & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + local tmp1:1 = Imm_uimm3; + # simd infix Rd_VPR128.16B = Rn_VPR128.16B << tmp1 on lane size 1 + Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] << tmp1; + Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] << tmp1; + Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] << tmp1; + Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] << tmp1; + Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] << tmp1; + Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] << tmp1; + Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] << tmp1; + Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] << tmp1; + Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] << tmp1; + Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] << tmp1; + Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] << tmp1; + Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] << tmp1; + Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] << tmp1; + Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] << tmp1; + Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] << tmp1; + Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] << tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00 +# CONSTRUCT x4f405400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =var:8 =$<<@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@8 +# AUNIT --inst x4f405400/mask=xffc0fc00 --status pass + +:shl Rd_VPR128.2D, Rn_VPR128.2D, Imm_imm0_63 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_imm0_63 & b_1115=0xa & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + local tmp1:8 = Imm_imm0_63; + # simd infix Rd_VPR128.2D = Rn_VPR128.2D << tmp1 on lane size 8 + Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] << tmp1; + Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] << tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00 +# CONSTRUCT x0f205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =var:4 =$<<@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@4 +# AUNIT --inst x0f205400/mask=xffe0fc00 --status pass + +:shl Rd_VPR64.2S, Rn_VPR64.2S, Imm_uimm5 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xa & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + local tmp1:4 = Imm_uimm5; + # simd infix Rd_VPR64.2S = Rn_VPR64.2S << tmp1 on lane size 4 + Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] << tmp1; + Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] << tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00 +# CONSTRUCT x0f105400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =var:2 =$<<@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@2 +# AUNIT --inst x0f105400/mask=xfff0fc00 --status pass + +:shl Rd_VPR64.4H, Rn_VPR64.4H, Imm_uimm4 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xa & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + local tmp1:2 = Imm_uimm4; + # simd infix Rd_VPR64.4H = Rn_VPR64.4H << tmp1 on lane size 2 + Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] << tmp1; + Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] << tmp1; + Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] << tmp1; + Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] << tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00 +# CONSTRUCT x4f205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =var:4 =$<<@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@4 +# AUNIT --inst x4f205400/mask=xffe0fc00 --status pass + +:shl Rd_VPR128.4S, Rn_VPR128.4S, Imm_uimm5 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xa & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + local tmp1:4 = Imm_uimm5; + # simd infix Rd_VPR128.4S = Rn_VPR128.4S << tmp1 on lane size 4 + Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] << tmp1; + Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] << tmp1; + Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] << tmp1; + Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] << tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00 +# CONSTRUCT x0f085400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =var:1 =$<<@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@1 +# AUNIT --inst x0f085400/mask=xfff8fc00 --status pass + +:shl Rd_VPR64.8B, Rn_VPR64.8B, Imm_uimm3 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xa & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + local tmp1:1 = Imm_uimm3; + # simd infix Rd_VPR64.8B = Rn_VPR64.8B << tmp1 on lane size 1 + Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] << tmp1; + Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] << tmp1; + Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] << tmp1; + Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] << tmp1; + Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] << tmp1; + Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] << tmp1; + Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] << tmp1; + Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] << tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00 +# CONSTRUCT x4f105400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =var:2 =$<<@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@2 +# AUNIT --inst x4f105400/mask=xfff0fc00 --status pass + +:shl Rd_VPR128.8H, Rn_VPR128.8H, Imm_uimm4 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xa & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + local tmp1:2 = Imm_uimm4; + # simd infix Rd_VPR128.8H = Rn_VPR128.8H << tmp1 on lane size 2 + Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] << tmp1; + Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] << tmp1; + Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] << tmp1; + Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] << tmp1; + Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] << tmp1; + Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] << tmp1; + Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] << tmp1; + Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] << tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.255 SHLL, SHLL2 page C7-2585 line 151125 MATCH x2e213800/mask=xbf3ffc00 +# CONSTRUCT x2ea13800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@4:16 ARG3 zext:8 =$<<@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shll/2@4 +# AUNIT --inst x2ea13800/mask=xfffffc00 --status pass --comment "ext" + +:shll Rd_VPR128.2D, Rn_VPR64.2S, Imm_uimm_exact32 +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & Imm_uimm_exact32 & b_1721=0x10 & b_1216=0x13 & b_1011=2 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]); + local tmp2:8 = zext(Imm_uimm_exact32); + # simd infix Rd_VPR128.2D = TMPQ1 << tmp2 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ1[0,64] << tmp2; + Rd_VPR128.2D[64,64] = TMPQ1[64,64] << tmp2; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.255 SHLL, SHLL2 page C7-2585 line 151125 MATCH x2e213800/mask=xbf3ffc00 +# CONSTRUCT x2e613800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@2:16 ARG3:4 =$<<@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shll/2@2 +# AUNIT --inst x2e613800/mask=xfffffc00 --status pass --comment "ext" + +:shll Rd_VPR128.4S, Rn_VPR64.4H, Imm_uimm_exact16 +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & Imm_uimm_exact16 & b_1721=0x10 & b_1216=0x13 & b_1011=2 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]); + # simd infix Rd_VPR128.4S = TMPQ1 << Imm_uimm_exact16:4 on lane size 4 + Rd_VPR128.4S[0,32] = TMPQ1[0,32] << Imm_uimm_exact16:4; + Rd_VPR128.4S[32,32] = TMPQ1[32,32] << Imm_uimm_exact16:4; + Rd_VPR128.4S[64,32] = TMPQ1[64,32] << Imm_uimm_exact16:4; + Rd_VPR128.4S[96,32] = TMPQ1[96,32] << Imm_uimm_exact16:4; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.255 SHLL, SHLL2 page C7-2585 line 151125 MATCH x2e213800/mask=xbf3ffc00 +# CONSTRUCT x2e213800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@1:16 ARG3:2 =$<<@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shll/2@1 +# AUNIT --inst x2e213800/mask=xfffffc00 --status pass --comment "ext" + +:shll Rd_VPR128.8H, Rn_VPR64.8B, Imm_uimm_exact8 +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & Imm_uimm_exact8 & b_1721=0x10 & b_1216=0x13 & b_1011=2 & Rn_VPR64.8B & Rd_VPR128.8H & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2) + TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]); + TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]); + TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]); + TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]); + TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]); + TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]); + TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]); + TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]); + # simd infix Rd_VPR128.8H = TMPQ1 << Imm_uimm_exact8:2 on lane size 2 + Rd_VPR128.8H[0,16] = TMPQ1[0,16] << Imm_uimm_exact8:2; + Rd_VPR128.8H[16,16] = TMPQ1[16,16] << Imm_uimm_exact8:2; + Rd_VPR128.8H[32,16] = TMPQ1[32,16] << Imm_uimm_exact8:2; + Rd_VPR128.8H[48,16] = TMPQ1[48,16] << Imm_uimm_exact8:2; + Rd_VPR128.8H[64,16] = TMPQ1[64,16] << Imm_uimm_exact8:2; + Rd_VPR128.8H[80,16] = TMPQ1[80,16] << Imm_uimm_exact8:2; + Rd_VPR128.8H[96,16] = TMPQ1[96,16] << Imm_uimm_exact8:2; + Rd_VPR128.8H[112,16] = TMPQ1[112,16] << Imm_uimm_exact8:2; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.255 SHLL, SHLL2 page C7-2585 line 151125 MATCH x2e213800/mask=xbf3ffc00 +# CONSTRUCT x6ea13800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 zext:8 =$<<@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shll2/2@4 +# AUNIT --inst x6ea13800/mask=xfffffc00 --status pass --comment "ext" + +:shll2 Rd_VPR128.2D, Rn_VPR128.4S, Imm_uimm_exact32 +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & Imm_uimm_exact32 & b_1721=0x10 & b_1216=0x13 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = sext(TMPD1[0,32]); + TMPQ2[64,64] = sext(TMPD1[32,32]); + local tmp3:8 = zext(Imm_uimm_exact32); + # simd infix Rd_VPR128.2D = TMPQ2 << tmp3 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ2[0,64] << tmp3; + Rd_VPR128.2D[64,64] = TMPQ2[64,64] << tmp3; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.255 SHLL, SHLL2 page C7-2585 line 151125 MATCH x2e213800/mask=xbf3ffc00 +# CONSTRUCT x6e613800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3:4 =$<<@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shll2/2@2 +# AUNIT --inst x6e613800/mask=xfffffc00 --status pass --comment "ext" + +:shll2 Rd_VPR128.4S, Rn_VPR128.8H, Imm_uimm_exact16 +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & Imm_uimm_exact16 & b_1721=0x10 & b_1216=0x13 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = sext(TMPD1[0,16]); + TMPQ2[32,32] = sext(TMPD1[16,16]); + TMPQ2[64,32] = sext(TMPD1[32,16]); + TMPQ2[96,32] = sext(TMPD1[48,16]); + # simd infix Rd_VPR128.4S = TMPQ2 << Imm_uimm_exact16:4 on lane size 4 + Rd_VPR128.4S[0,32] = TMPQ2[0,32] << Imm_uimm_exact16:4; + Rd_VPR128.4S[32,32] = TMPQ2[32,32] << Imm_uimm_exact16:4; + Rd_VPR128.4S[64,32] = TMPQ2[64,32] << Imm_uimm_exact16:4; + Rd_VPR128.4S[96,32] = TMPQ2[96,32] << Imm_uimm_exact16:4; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.255 SHLL, SHLL2 page C7-2585 line 151125 MATCH x2e213800/mask=xbf3ffc00 +# CONSTRUCT x6e213800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3:2 =$<<@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shll2/2@1 +# AUNIT --inst x6e213800/mask=xfffffc00 --status pass --comment "ext" + +:shll2 Rd_VPR128.8H, Rn_VPR128.16B, Imm_uimm_exact8 +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & Imm_uimm_exact8 & b_1721=0x10 & b_1216=0x13 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.8H & Zd +{ + TMPD1 = Rn_VPR128.16B[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2) + TMPQ2[0,16] = sext(TMPD1[0,8]); + TMPQ2[16,16] = sext(TMPD1[8,8]); + TMPQ2[32,16] = sext(TMPD1[16,8]); + TMPQ2[48,16] = sext(TMPD1[24,8]); + TMPQ2[64,16] = sext(TMPD1[32,8]); + TMPQ2[80,16] = sext(TMPD1[40,8]); + TMPQ2[96,16] = sext(TMPD1[48,8]); + TMPQ2[112,16] = sext(TMPD1[56,8]); + # simd infix Rd_VPR128.8H = TMPQ2 << Imm_uimm_exact8:2 on lane size 2 + Rd_VPR128.8H[0,16] = TMPQ2[0,16] << Imm_uimm_exact8:2; + Rd_VPR128.8H[16,16] = TMPQ2[16,16] << Imm_uimm_exact8:2; + Rd_VPR128.8H[32,16] = TMPQ2[32,16] << Imm_uimm_exact8:2; + Rd_VPR128.8H[48,16] = TMPQ2[48,16] << Imm_uimm_exact8:2; + Rd_VPR128.8H[64,16] = TMPQ2[64,16] << Imm_uimm_exact8:2; + Rd_VPR128.8H[80,16] = TMPQ2[80,16] << Imm_uimm_exact8:2; + Rd_VPR128.8H[96,16] = TMPQ2[96,16] << Imm_uimm_exact8:2; + Rd_VPR128.8H[112,16] = TMPQ2[112,16] << Imm_uimm_exact8:2; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.256 SHRN, SHRN2 page C7-2587 line 151244 MATCH x0f008400/mask=xbf80fc00 +# CONSTRUCT x0f208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 zext:8 $>>@8 =$zext@8:8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shrn/2@8 +# AUNIT --inst x0f208400/mask=xffe0fc00 --status pass --comment "ext" + +:shrn Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x10 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd +{ + local tmp1:8 = zext(Imm_shr_imm32); + # simd infix TMPQ1 = Rn_VPR128.2D >> tmp1 on lane size 8 + TMPQ1[0,64] = Rn_VPR128.2D[0,64] >> tmp1; + TMPQ1[64,64] = Rn_VPR128.2D[64,64] >> tmp1; + # simd resize Rd_VPR64.2S = zext(TMPQ1) (lane size 8 to 4) + Rd_VPR64.2S[0,32] = TMPQ1[0,32]; + Rd_VPR64.2S[32,32] = TMPQ1[64,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.256 SHRN, SHRN2 page C7-2587 line 151244 MATCH x0f008400/mask=xbf80fc00 +# CONSTRUCT x0f108400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:4 $>>@4 =$zext@4:16 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shrn/2@4 +# AUNIT --inst x0f108400/mask=xfff0fc00 --status pass --comment "ext" + +:shrn Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x10 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.4S >> Imm_shr_imm16:4 on lane size 4 + TMPQ1[0,32] = Rn_VPR128.4S[0,32] >> Imm_shr_imm16:4; + TMPQ1[32,32] = Rn_VPR128.4S[32,32] >> Imm_shr_imm16:4; + TMPQ1[64,32] = Rn_VPR128.4S[64,32] >> Imm_shr_imm16:4; + TMPQ1[96,32] = Rn_VPR128.4S[96,32] >> Imm_shr_imm16:4; + # simd resize Rd_VPR64.4H = zext(TMPQ1) (lane size 4 to 2) + Rd_VPR64.4H[0,16] = TMPQ1[0,16]; + Rd_VPR64.4H[16,16] = TMPQ1[32,16]; + Rd_VPR64.4H[32,16] = TMPQ1[64,16]; + Rd_VPR64.4H[48,16] = TMPQ1[96,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.256 SHRN, SHRN2 page C7-2587 line 151244 MATCH x0f008400/mask=xbf80fc00 +# CONSTRUCT x0f088400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:2 $>>@2 =$zext@2:8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shrn/2@2 +# AUNIT --inst x0f088400/mask=xfff8fc00 --status pass --comment "ext" + +:shrn Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x10 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.8H >> Imm_shr_imm8:2 on lane size 2 + TMPQ1[0,16] = Rn_VPR128.8H[0,16] >> Imm_shr_imm8:2; + TMPQ1[16,16] = Rn_VPR128.8H[16,16] >> Imm_shr_imm8:2; + TMPQ1[32,16] = Rn_VPR128.8H[32,16] >> Imm_shr_imm8:2; + TMPQ1[48,16] = Rn_VPR128.8H[48,16] >> Imm_shr_imm8:2; + TMPQ1[64,16] = Rn_VPR128.8H[64,16] >> Imm_shr_imm8:2; + TMPQ1[80,16] = Rn_VPR128.8H[80,16] >> Imm_shr_imm8:2; + TMPQ1[96,16] = Rn_VPR128.8H[96,16] >> Imm_shr_imm8:2; + TMPQ1[112,16] = Rn_VPR128.8H[112,16] >> Imm_shr_imm8:2; + # simd resize Rd_VPR64.8B = zext(TMPQ1) (lane size 2 to 1) + Rd_VPR64.8B[0,8] = TMPQ1[0,8]; + Rd_VPR64.8B[8,8] = TMPQ1[16,8]; + Rd_VPR64.8B[16,8] = TMPQ1[32,8]; + Rd_VPR64.8B[24,8] = TMPQ1[48,8]; + Rd_VPR64.8B[32,8] = TMPQ1[64,8]; + Rd_VPR64.8B[40,8] = TMPQ1[80,8]; + Rd_VPR64.8B[48,8] = TMPQ1[96,8]; + Rd_VPR64.8B[56,8] = TMPQ1[112,8]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.256 SHRN, SHRN2 page C7-2587 line 151244 MATCH x0f008400/mask=xbf80fc00 +# CONSTRUCT x4f208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 zext:8 $>>@8 $zext@8:8 1:1 &=$copy +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shrn2/2@8 +# AUNIT --inst x4f208400/mask=xffe0fc00 --status pass --comment "ext" + +:shrn2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x10 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd +{ + local tmp1:8 = zext(Imm_shr_imm32); + # simd infix TMPQ1 = Rn_VPR128.2D >> tmp1 on lane size 8 + TMPQ1[0,64] = Rn_VPR128.2D[0,64] >> tmp1; + TMPQ1[64,64] = Rn_VPR128.2D[64,64] >> tmp1; + # simd resize TMPD2 = zext(TMPQ1) (lane size 8 to 4) + TMPD2[0,32] = TMPQ1[0,32]; + TMPD2[32,32] = TMPQ1[64,32]; + # simd copy Rd_VPR128.4S element 1:1 = TMPD2 (lane size 8) + Rd_VPR128.4S[64,64] = TMPD2; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.256 SHRN, SHRN2 page C7-2587 line 151244 MATCH x0f008400/mask=xbf80fc00 +# CONSTRUCT x4f108400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:4 $>>@4 $zext@4:8 1:1 &=$copy +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shrn2/2@4 +# AUNIT --inst x4f108400/mask=xfff0fc00 --status pass --comment "ext" + +:shrn2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x10 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.4S >> Imm_shr_imm16:4 on lane size 4 + TMPQ1[0,32] = Rn_VPR128.4S[0,32] >> Imm_shr_imm16:4; + TMPQ1[32,32] = Rn_VPR128.4S[32,32] >> Imm_shr_imm16:4; + TMPQ1[64,32] = Rn_VPR128.4S[64,32] >> Imm_shr_imm16:4; + TMPQ1[96,32] = Rn_VPR128.4S[96,32] >> Imm_shr_imm16:4; + # simd resize TMPD2 = zext(TMPQ1) (lane size 4 to 2) + TMPD2[0,16] = TMPQ1[0,16]; + TMPD2[16,16] = TMPQ1[32,16]; + TMPD2[32,16] = TMPQ1[64,16]; + TMPD2[48,16] = TMPQ1[96,16]; + # simd copy Rd_VPR128.8H element 1:1 = TMPD2 (lane size 8) + Rd_VPR128.8H[64,64] = TMPD2; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.256 SHRN, SHRN2 page C7-2587 line 151244 MATCH x0f008400/mask=xbf80fc00 +# CONSTRUCT x4f088400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:2 $>>@2 $zext@2:8 1:1 &=$copy +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shrn2/2@2 +# AUNIT --inst x4f088400/mask=xfff8fc00 --status pass --comment "ext" + +:shrn2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x10 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.8H >> Imm_shr_imm8:2 on lane size 2 + TMPQ1[0,16] = Rn_VPR128.8H[0,16] >> Imm_shr_imm8:2; + TMPQ1[16,16] = Rn_VPR128.8H[16,16] >> Imm_shr_imm8:2; + TMPQ1[32,16] = Rn_VPR128.8H[32,16] >> Imm_shr_imm8:2; + TMPQ1[48,16] = Rn_VPR128.8H[48,16] >> Imm_shr_imm8:2; + TMPQ1[64,16] = Rn_VPR128.8H[64,16] >> Imm_shr_imm8:2; + TMPQ1[80,16] = Rn_VPR128.8H[80,16] >> Imm_shr_imm8:2; + TMPQ1[96,16] = Rn_VPR128.8H[96,16] >> Imm_shr_imm8:2; + TMPQ1[112,16] = Rn_VPR128.8H[112,16] >> Imm_shr_imm8:2; + # simd resize TMPD2 = zext(TMPQ1) (lane size 2 to 1) + TMPD2[0,8] = TMPQ1[0,8]; + TMPD2[8,8] = TMPQ1[16,8]; + TMPD2[16,8] = TMPQ1[32,8]; + TMPD2[24,8] = TMPQ1[48,8]; + TMPD2[32,8] = TMPQ1[64,8]; + TMPD2[40,8] = TMPQ1[80,8]; + TMPD2[48,8] = TMPQ1[96,8]; + TMPD2[56,8] = TMPQ1[112,8]; + # simd copy Rd_VPR128.16B element 1:1 = TMPD2 (lane size 8) + Rd_VPR128.16B[64,64] = TMPD2; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.257 SHSUB page C7-2589 line 151368 MATCH x0e202400/mask=xbf20fc00 +# CONSTRUCT x4e202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shsub/2@1 +# AUNIT --inst x4e202400/mask=xffe0fc00 --status nopcodeop + +:shsub Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x4 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_shsub(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.257 SHSUB page C7-2589 line 151368 MATCH x0e202400/mask=xbf20fc00 +# CONSTRUCT x0ea02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shsub/2@4 +# AUNIT --inst x0ea02400/mask=xffe0fc00 --status nopcodeop + +:shsub Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x4 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_shsub(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.257 SHSUB page C7-2589 line 151368 MATCH x0e202400/mask=xbf20fc00 +# CONSTRUCT x0e602400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shsub/2@2 +# AUNIT --inst x0e602400/mask=xffe0fc00 --status nopcodeop + +:shsub Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x4 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_shsub(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.257 SHSUB page C7-2589 line 151368 MATCH x0e202400/mask=xbf20fc00 +# CONSTRUCT x4ea02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shsub/2@4 +# AUNIT --inst x4ea02400/mask=xffe0fc00 --status nopcodeop + +:shsub Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x4 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_shsub(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.257 SHSUB page C7-2589 line 151368 MATCH x0e202400/mask=xbf20fc00 +# CONSTRUCT x0e202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shsub/2@1 +# AUNIT --inst x0e202400/mask=xffe0fc00 --status nopcodeop + +:shsub Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x4 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_shsub(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.257 SHSUB page C7-2589 line 151368 MATCH x0e202400/mask=xbf20fc00 +# CONSTRUCT x4e602400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shsub/2@2 +# AUNIT --inst x4e602400/mask=xffe0fc00 --status nopcodeop + +:shsub Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x4 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_shsub(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00 +# CONSTRUCT x6f085400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@1 +# AUNIT --inst x6f085400/mask=xfff8fc00 --status nopcodeop + +:sli Rd_VPR128.16B, Rn_VPR128.16B, Imm_uimm3 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xa & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_sli(Rd_VPR128.16B, Rn_VPR128.16B, Imm_uimm3:1, 1:1); +} + +# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00 +# CONSTRUCT x6f405400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@8 +# AUNIT --inst x6f405400/mask=xffc0fc00 --status nopcodeop + +:sli Rd_VPR128.2D, Rn_VPR128.2D, Imm_imm0_63 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_imm0_63 & b_1115=0xa & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_sli(Rd_VPR128.2D, Rn_VPR128.2D, Imm_imm0_63:1, 8:1); +} + +# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00 +# CONSTRUCT x2f205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@4 +# AUNIT --inst x2f205400/mask=xffe0fc00 --status nopcodeop + +:sli Rd_VPR64.2S, Rn_VPR64.2S, Imm_uimm5 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xa & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_sli(Rd_VPR64.2S, Rn_VPR64.2S, Imm_uimm5:1, 4:1); +} + +# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00 +# CONSTRUCT x2f105400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@2 +# AUNIT --inst x2f105400/mask=xfff0fc00 --status nopcodeop + +:sli Rd_VPR64.4H, Rn_VPR64.4H, Imm_uimm4 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xa & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_sli(Rd_VPR64.4H, Rn_VPR64.4H, Imm_uimm4:1, 2:1); +} + +# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00 +# CONSTRUCT x6f205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@4 +# AUNIT --inst x6f205400/mask=xffe0fc00 --status nopcodeop + +:sli Rd_VPR128.4S, Rn_VPR128.4S, Imm_uimm5 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xa & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sli(Rd_VPR128.4S, Rn_VPR128.4S, Imm_uimm5:1, 4:1); +} + +# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00 +# CONSTRUCT x2f085400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@1 +# AUNIT --inst x2f085400/mask=xfff8fc00 --status nopcodeop + +:sli Rd_VPR64.8B, Rn_VPR64.8B, Imm_uimm3 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xa & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_sli(Rd_VPR64.8B, Rn_VPR64.8B, Imm_uimm3:1, 1:1); +} + +# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00 +# CONSTRUCT x6f105400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@2 +# AUNIT --inst x6f105400/mask=xfff0fc00 --status nopcodeop + +:sli Rd_VPR128.8H, Rn_VPR128.8H, Imm_uimm4 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xa & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_sli(Rd_VPR128.8H, Rn_VPR128.8H, Imm_uimm4:1, 2:1); +} + +# C7.2.258 SLI page C7-2591 line 151468 MATCH x7f005400/mask=xff80fc00 +# CONSTRUCT x7f405400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3 +# AUNIT --inst x7f405400/mask=xffc0fc00 --status nopcodeop + +:sli Rd_VPR64, Rn_VPR64, Imm_uimm5 +is b_2331=0b011111110 & b_22=1 & b_1015=0b010101 & Rd_VPR64 & Rn_VPR64 & Imm_uimm5 & Zd +{ + Rd_VPR64 = NEON_sli(Rd_VPR64, Rn_VPR64, Imm_uimm5:1); +} + +# C7.2.259 SM3PARTW1 page C7-2594 line 151635 MATCH xce60c000/mask=xffe0fc00 +# CONSTRUCT xce60c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm3partw1/3@4 +# AUNIT --inst xce60c000/mask=xffe0fc00 --status noqemu + +:sm3partw1 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_2131=0b11001110011 & b_1015=0b110000 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sm3partw1(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.260 SM3PARTW2 page C7-2596 line 151723 MATCH xce60c400/mask=xffe0fc00 +# CONSTRUCT xce60c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm3partw2/3@4 +# AUNIT --inst xce60c400/mask=xffe0fc00 --status noqemu + +:sm3partw2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_2131=0b11001110011 & b_1015=0b110001 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sm3partw2(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.261 SM3SS1 page C7-2598 line 151808 MATCH xce400000/mask=xffe08000 +# CONSTRUCT xce400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_sm3ss1/3@4 +# AUNIT --inst xce400000/mask=xffe08000 --status noqemu + +:sm3ss1 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, Ra_VPR128.4S +is b_2131=0b11001110010 & b_15=0 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Ra_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sm3ss1(Rn_VPR128.4S, Rm_VPR128.4S, Ra_VPR128.4S, 4:1); +} + +# C7.2.247 SM3TT1A page C7-1529 line 88534 KEEPWITH + +sm3imm2: b_1213 is b_1213 { export *[const]:4 b_1213; } +Re_VPR128.S.sm3imm2: Re_VPR128.S^"["^sm3imm2^"]" is Re_VPR128.S & sm3imm2 { export Re_VPR128.S; } + +# C7.2.262 SM3TT1A page C7-2600 line 151893 MATCH xce408000/mask=xffe0cc00 +# CONSTRUCT xce408000/mask=xffe0cc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm3tt1a/3@4 +# AUNIT --inst xce408000/mask=xffe0cc00 --status noqemu + +:sm3tt1a Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.sm3imm2 +is b_2131=0b11001110010 & b_1415=0b10 & b_1011=0b00 & Rd_VPR128.4S & Rn_VPR128.4S & Re_VPR128.S.sm3imm2 & Re_VPR128.S & sm3imm2 & Zd +{ + local tmp1:4 = SIMD_PIECE(Re_VPR128.S, sm3imm2:1); + Rd_VPR128.4S = NEON_sm3tt1a(Rd_VPR128.4S, Rn_VPR128.4S, tmp1, 4:1); +} + +# C7.2.263 SM3TT1B page C7-2602 line 151999 MATCH xce408400/mask=xffe0cc00 +# CONSTRUCT xce408400/mask=xffe0cc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm3tt1b/3@4 +# AUNIT --inst xce408400/mask=xffe0cc00 --status noqemu + +:sm3tt1b Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.sm3imm2 +is b_2131=0b11001110010 & b_1415=0b10 & b_1011=0b01 & Rd_VPR128.4S & Rn_VPR128.4S & Re_VPR128.S.sm3imm2 & Re_VPR128.S & sm3imm2 & Zd +{ + local tmp1:4 = SIMD_PIECE(Re_VPR128.S, sm3imm2:1); + Rd_VPR128.4S = NEON_sm3tt1b(Rd_VPR128.4S, Rn_VPR128.4S, tmp1, 4:1); +} + +# C7.2.264 SM3TT2A page C7-2604 line 152105 MATCH xce408800/mask=xffe0cc00 +# CONSTRUCT xce408800/mask=xffe0cc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm3tt2a/3@4 +# AUNIT --inst xce408800/mask=xffe0cc00 --status noqemu + +:sm3tt2a Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.sm3imm2 +is b_2131=0b11001110010 & b_1415=0b10 & b_1011=0b10 & Rd_VPR128.4S & Rn_VPR128.4S & Re_VPR128.S.sm3imm2 & Re_VPR128.S & sm3imm2 & Zd +{ + local tmp1:4 = SIMD_PIECE(Re_VPR128.S, sm3imm2:1); + Rd_VPR128.4S = NEON_sm3tt2a(Rd_VPR128.4S, Rn_VPR128.4S, tmp1, 4:1); +} + +# C7.2.265 SM3TT2B page C7-2606 line 152210 MATCH xce408c00/mask=xffe0cc00 +# CONSTRUCT xce408c00/mask=xffe0cc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm3tt2b/3@4 +# AUNIT --inst xce408c00/mask=xffe0cc00 --status noqemu + +:sm3tt2b Rd_VPR128.S, Rn_VPR128.S, Re_VPR128.S.sm3imm2 +is b_2131=0b11001110010 & b_1415=0b10 & b_1011=0b11 & Rd_VPR128.S & Rn_VPR128.S & Re_VPR128.S.sm3imm2 & Re_VPR128.S & sm3imm2 & Zd +{ + local tmp1:4 = SIMD_PIECE(Re_VPR128.S, sm3imm2:1); + Rd_VPR128.S = NEON_sm3tt2b(Rd_VPR128.S, Rn_VPR128.S, tmp1, 4:1); +} + +# C7.2.266 SM4E page C7-2608 line 152315 MATCH xcec08400/mask=xfffffc00 +# CONSTRUCT xcec08400/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sm4e/2@4 +# AUNIT --inst xcec08400/mask=xfffffc00 --status noqemu + +:sm4e Rd_VPR128.4S, Rn_VPR128.4S +is b_1031=0b1100111011000000100001 & Rd_VPR128.4S & Rn_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sm4e(Rd_VPR128.4S, Rn_VPR128.4S, 4:1); +} + +# C7.2.267 SM4EKEY page C7-2610 line 152409 MATCH xce60c800/mask=xffe0fc00 +# CONSTRUCT xce60c800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm4ekey/3@4 +# AUNIT --inst xce60c800/mask=xffe0fc00 --status noqemu + +:sm4ekey Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_2131=0b11001110011 & b_1015=0b110010 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sm4ekey(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.268 SMAX page C7-2612 line 152509 MATCH x0e206400/mask=xbf20fc00 +# CONSTRUCT x4e206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@1 +# AUNIT --inst x4e206400/mask=xffe0fc00 --status nopcodeop + +:smax Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xc & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_smax(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.268 SMAX page C7-2612 line 152509 MATCH x0e206400/mask=xbf20fc00 +# CONSTRUCT x0ea06400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@4 +# AUNIT --inst x0ea06400/mask=xffe0fc00 --status nopcodeop + +:smax Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xc & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_smax(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.268 SMAX page C7-2612 line 152509 MATCH x0e206400/mask=xbf20fc00 +# CONSTRUCT x0e606400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@2 +# AUNIT --inst x0e606400/mask=xffe0fc00 --status nopcodeop + +:smax Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xc & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_smax(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.268 SMAX page C7-2612 line 152509 MATCH x0e206400/mask=xbf20fc00 +# CONSTRUCT x4ea06400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@4 +# AUNIT --inst x4ea06400/mask=xffe0fc00 --status nopcodeop + +:smax Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xc & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_smax(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.268 SMAX page C7-2612 line 152509 MATCH x0e206400/mask=xbf20fc00 +# CONSTRUCT x0e206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@1 +# AUNIT --inst x0e206400/mask=xffe0fc00 --status nopcodeop + +:smax Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xc & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_smax(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.268 SMAX page C7-2612 line 152509 MATCH x0e206400/mask=xbf20fc00 +# CONSTRUCT x4e606400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@2 +# AUNIT --inst x4e606400/mask=xffe0fc00 --status nopcodeop + +:smax Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xc & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_smax(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.269 SMAXP page C7-2614 line 152611 MATCH x0e20a400/mask=xbf20fc00 +# CONSTRUCT x4e20a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@1 +# AUNIT --inst x4e20a400/mask=xffe0fc00 --status nopcodeop + +:smaxp Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x14 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_smax(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.269 SMAXP page C7-2614 line 152611 MATCH x0e20a400/mask=xbf20fc00 +# CONSTRUCT x0ea0a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smaxp/2@4 +# AUNIT --inst x0ea0a400/mask=xffe0fc00 --status nopcodeop + +:smaxp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x14 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_smaxp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.269 SMAXP page C7-2614 line 152611 MATCH x0e20a400/mask=xbf20fc00 +# CONSTRUCT x0e60a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smaxp/2@2 +# AUNIT --inst x0e60a400/mask=xffe0fc00 --status nopcodeop + +:smaxp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x14 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_smaxp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.269 SMAXP page C7-2614 line 152611 MATCH x0e20a400/mask=xbf20fc00 +# CONSTRUCT x4ea0a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smaxp/2@4 +# AUNIT --inst x4ea0a400/mask=xffe0fc00 --status nopcodeop + +:smaxp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x14 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_smaxp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.269 SMAXP page C7-2614 line 152611 MATCH x0e20a400/mask=xbf20fc00 +# CONSTRUCT x0e20a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smaxp/2@1 +# AUNIT --inst x0e20a400/mask=xffe0fc00 --status nopcodeop + +:smaxp Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x14 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_smaxp(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.269 SMAXP page C7-2614 line 152611 MATCH x0e20a400/mask=xbf20fc00 +# CONSTRUCT x4e60a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smaxp/2@2 +# AUNIT --inst x4e60a400/mask=xffe0fc00 --status nopcodeop + +:smaxp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x14 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_smaxp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.270 SMAXV page C7-2616 line 152715 MATCH x0e30a800/mask=xbf3ffc00 +# CONSTRUCT x4e30a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_smaxv/1@1 +# AUNIT --inst x4e30a800/mask=xfffffc00 --status nopcodeop + +:smaxv Rd_FPR8, Rn_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.16B & Rd_FPR8 & Zd +{ + Rd_FPR8 = NEON_smaxv(Rn_VPR128.16B, 1:1); +} + +# C7.2.270 SMAXV page C7-2616 line 152715 MATCH x0e30a800/mask=xbf3ffc00 +# CONSTRUCT x0e30a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_smaxv/1@1 +# AUNIT --inst x0e30a800/mask=xfffffc00 --status nopcodeop + +:smaxv Rd_FPR8, Rn_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR64.8B & Rd_FPR8 & Zd +{ + Rd_FPR8 = NEON_smaxv(Rn_VPR64.8B, 1:1); +} + +# C7.2.270 SMAXV page C7-2616 line 152715 MATCH x0e30a800/mask=xbf3ffc00 +# CONSTRUCT x0e70a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_smaxv/1@2 +# AUNIT --inst x0e70a800/mask=xfffffc00 --status nopcodeop + +:smaxv Rd_FPR16, Rn_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR64.4H & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_smaxv(Rn_VPR64.4H, 2:1); +} + +# C7.2.270 SMAXV page C7-2616 line 152715 MATCH x0e30a800/mask=xbf3ffc00 +# CONSTRUCT x4e70a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_smaxv/1@2 +# AUNIT --inst x4e70a800/mask=xfffffc00 --status nopcodeop + +:smaxv Rd_FPR16, Rn_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.8H & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_smaxv(Rn_VPR128.8H, 2:1); +} + +# C7.2.270 SMAXV page C7-2616 line 152715 MATCH x0e30a800/mask=xbf3ffc00 +# CONSTRUCT x4eb0a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_smaxv/1@4 +# AUNIT --inst x4eb0a800/mask=xfffffc00 --status nopcodeop + +:smaxv Rd_FPR32, Rn_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_smaxv(Rn_VPR128.4S, 4:1); +} + +# C7.2.271 SMIN page C7-2618 line 152818 MATCH x0e206c00/mask=xbf20fc00 +# CONSTRUCT x4e206c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smin/2@1 +# AUNIT --inst x4e206c00/mask=xffe0fc00 --status nopcodeop + +:smin Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xd & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_smin(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.271 SMIN page C7-2618 line 152818 MATCH x0e206c00/mask=xbf20fc00 +# CONSTRUCT x0ea06c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smin/2@4 +# AUNIT --inst x0ea06c00/mask=xffe0fc00 --status nopcodeop + +:smin Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xd & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_smin(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.271 SMIN page C7-2618 line 152818 MATCH x0e206c00/mask=xbf20fc00 +# CONSTRUCT x0e606c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smin/2@2 +# AUNIT --inst x0e606c00/mask=xffe0fc00 --status nopcodeop + +:smin Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xd & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_smin(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.271 SMIN page C7-2618 line 152818 MATCH x0e206c00/mask=xbf20fc00 +# CONSTRUCT x4ea06c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smin/2@4 +# AUNIT --inst x4ea06c00/mask=xffe0fc00 --status nopcodeop + +:smin Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xd & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_smin(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.271 SMIN page C7-2618 line 152818 MATCH x0e206c00/mask=xbf20fc00 +# CONSTRUCT x0e206c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smin/2@1 +# AUNIT --inst x0e206c00/mask=xffe0fc00 --status nopcodeop + +:smin Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xd & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_smin(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.271 SMIN page C7-2618 line 152818 MATCH x0e206c00/mask=xbf20fc00 +# CONSTRUCT x4e606c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smin/2@2 +# AUNIT --inst x4e606c00/mask=xffe0fc00 --status nopcodeop + +:smin Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xd & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_smin(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.272 SMINP page C7-2620 line 152920 MATCH x0e20ac00/mask=xbf20fc00 +# CONSTRUCT x4e20ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sminp/2@1 +# AUNIT --inst x4e20ac00/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:sminp Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x15 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_sminp(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.272 SMINP page C7-2620 line 152920 MATCH x0e20ac00/mask=xbf20fc00 +# CONSTRUCT x0ea0ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sminp/2@4 +# AUNIT --inst x0ea0ac00/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:sminp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x15 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_sminp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.272 SMINP page C7-2620 line 152920 MATCH x0e20ac00/mask=xbf20fc00 +# CONSTRUCT x0e60ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sminp/2@2 +# AUNIT --inst x0e60ac00/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:sminp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x15 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_sminp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.272 SMINP page C7-2620 line 152920 MATCH x0e20ac00/mask=xbf20fc00 +# CONSTRUCT x4ea0ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sminp/2@4 +# AUNIT --inst x4ea0ac00/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:sminp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x15 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sminp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.272 SMINP page C7-2620 line 152920 MATCH x0e20ac00/mask=xbf20fc00 +# CONSTRUCT x0e20ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sminp/2@1 +# AUNIT --inst x0e20ac00/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:sminp Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x15 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_sminp(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.272 SMINP page C7-2620 line 152920 MATCH x0e20ac00/mask=xbf20fc00 +# CONSTRUCT x4e60ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sminp/2@2 +# AUNIT --inst x4e60ac00/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:sminp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x15 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_sminp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.273 SMINV page C7-2622 line 153024 MATCH x0e31a800/mask=xbf3ffc00 +# CONSTRUCT x4e31a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_sminv/1@1 +# AUNIT --inst x4e31a800/mask=xfffffc00 --status nopcodeop + +:sminv Rd_FPR8, Rn_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.16B & Rd_FPR8 & Zd +{ + Rd_FPR8 = NEON_sminv(Rn_VPR128.16B, 1:1); +} + +# C7.2.273 SMINV page C7-2622 line 153024 MATCH x0e31a800/mask=xbf3ffc00 +# CONSTRUCT x0e31a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_sminv/1@1 +# AUNIT --inst x0e31a800/mask=xfffffc00 --status nopcodeop + +:sminv Rd_FPR8, Rn_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR64.8B & Rd_FPR8 & Zd +{ + Rd_FPR8 = NEON_sminv(Rn_VPR64.8B, 1:1); +} + +# C7.2.273 SMINV page C7-2622 line 153024 MATCH x0e31a800/mask=xbf3ffc00 +# CONSTRUCT x0e71a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_sminv/1@2 +# AUNIT --inst x0e71a800/mask=xfffffc00 --status nopcodeop + +:sminv Rd_FPR16, Rn_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR64.4H & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_sminv(Rn_VPR64.4H, 2:1); +} + +# C7.2.273 SMINV page C7-2622 line 153024 MATCH x0e31a800/mask=xbf3ffc00 +# CONSTRUCT x4e71a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_sminv/1@2 +# AUNIT --inst x4e71a800/mask=xfffffc00 --status nopcodeop + +:sminv Rd_FPR16, Rn_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.8H & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_sminv(Rn_VPR128.8H, 2:1); +} + +# C7.2.273 SMINV page C7-2622 line 153024 MATCH x0e31a800/mask=xbf3ffc00 +# CONSTRUCT x4eb1a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_sminv/1@4 +# AUNIT --inst x4eb1a800/mask=xfffffc00 --status nopcodeop + +:sminv Rd_FPR32, Rn_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_sminv(Rn_VPR128.4S, 4:1); +} + +# C7.2.274 SMLAL, SMLAL2 (by element) page C7-2624 line 153127 MATCH x0f002000/mask=xbf00f400 +# CONSTRUCT x0f802000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal/3@4 +# AUNIT --inst x0f802000/mask=xffc0f400 --status pass --comment "ext" + +:smlal Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex +is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x2 & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp2:4 = Re_VPR128.S.vIndex; + local tmp3:8 = sext(tmp2); + # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8 + TMPQ2[0,64] = TMPQ1[0,64] * tmp3; + TMPQ2[64,64] = TMPQ1[64,64] * tmp3; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ2 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ2[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ2[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.274 SMLAL, SMLAL2 (by element) page C7-2624 line 153127 MATCH x0f002000/mask=xbf00f400 +# CONSTRUCT x0f402000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal/3@2 +# AUNIT --inst x0f402000/mask=xffc0f400 --status pass --comment "ext" + +:smlal Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM +is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x2 & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]); + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp2:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp3:4 = sext(tmp2); + # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4 + TMPQ2[0,32] = TMPQ1[0,32] * tmp3; + TMPQ2[32,32] = TMPQ1[32,32] * tmp3; + TMPQ2[64,32] = TMPQ1[64,32] * tmp3; + TMPQ2[96,32] = TMPQ1[96,32] * tmp3; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ2 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ2[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ2[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ2[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ2[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.274 SMLAL, SMLAL2 (by element) page C7-2624 line 153127 MATCH x0f002000/mask=xbf00f400 +# CONSTRUCT x4f802000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 sext:8 $* &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal2/3@4 +# AUNIT --inst x4f802000/mask=xffc0f400 --status pass --comment "ext" + +:smlal2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex +is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x2 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Rn_VPR128 & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = sext(TMPD1[0,32]); + TMPQ2[64,64] = sext(TMPD1[32,32]); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp3:4 = Re_VPR128.S.vIndex; + local tmp4:8 = sext(tmp3); + # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8 + TMPQ3[0,64] = TMPQ2[0,64] * tmp4; + TMPQ3[64,64] = TMPQ2[64,64] * tmp4; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ3 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ3[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ3[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.274 SMLAL, SMLAL2 (by element) page C7-2624 line 153127 MATCH x0f002000/mask=xbf00f400 +# CONSTRUCT x4f402000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 sext:4 $* &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal2/3@2 +# AUNIT --inst x4f402000/mask=xffc0f400 --status pass --comment "ext" + +:smlal2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM +is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x2 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Rn_VPR128 & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = sext(TMPD1[0,16]); + TMPQ2[32,32] = sext(TMPD1[16,16]); + TMPQ2[64,32] = sext(TMPD1[32,16]); + TMPQ2[96,32] = sext(TMPD1[48,16]); + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp3:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp4:4 = sext(tmp3); + # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4 + TMPQ3[0,32] = TMPQ2[0,32] * tmp4; + TMPQ3[32,32] = TMPQ2[32,32] * tmp4; + TMPQ3[64,32] = TMPQ2[64,32] * tmp4; + TMPQ3[96,32] = TMPQ2[96,32] * tmp4; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.275 SMLAL, SMLAL2 (vector) page C7-2627 line 153291 MATCH x0e208000/mask=xbf20fc00 +# CONSTRUCT x0ea08000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 $*@8 &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal/3@4 +# AUNIT --inst x0ea08000/mask=xffe0fc00 --status pass --comment "ext" + +:smlal Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x8 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]); + # simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8) + TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]); + TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]); + # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 8 + TMPQ3[0,64] = TMPQ1[0,64] * TMPQ2[0,64]; + TMPQ3[64,64] = TMPQ1[64,64] * TMPQ2[64,64]; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ3 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ3[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ3[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.275 SMLAL, SMLAL2 (vector) page C7-2627 line 153291 MATCH x0e208000/mask=xbf20fc00 +# CONSTRUCT x0e608000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 $*@4 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal/3@2 +# AUNIT --inst x0e608000/mask=xffe0fc00 --status pass --comment "ext" + +:smlal Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x8 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]); + # simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4) + TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]); + TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]); + TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]); + TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]); + # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 4 + TMPQ3[0,32] = TMPQ1[0,32] * TMPQ2[0,32]; + TMPQ3[32,32] = TMPQ1[32,32] * TMPQ2[32,32]; + TMPQ3[64,32] = TMPQ1[64,32] * TMPQ2[64,32]; + TMPQ3[96,32] = TMPQ1[96,32] * TMPQ2[96,32]; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.275 SMLAL, SMLAL2 (vector) page C7-2627 line 153291 MATCH x0e208000/mask=xbf20fc00 +# CONSTRUCT x0e208000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 $*@2 &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal/3@1 +# AUNIT --inst x0e208000/mask=xffe0fc00 --status pass --comment "ext" + +:smlal Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x8 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2) + TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]); + TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]); + TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]); + TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]); + TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]); + TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]); + TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]); + TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]); + # simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2) + TMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]); + TMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]); + TMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]); + TMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]); + TMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]); + TMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]); + TMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]); + TMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]); + # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 2 + TMPQ3[0,16] = TMPQ1[0,16] * TMPQ2[0,16]; + TMPQ3[16,16] = TMPQ1[16,16] * TMPQ2[16,16]; + TMPQ3[32,16] = TMPQ1[32,16] * TMPQ2[32,16]; + TMPQ3[48,16] = TMPQ1[48,16] * TMPQ2[48,16]; + TMPQ3[64,16] = TMPQ1[64,16] * TMPQ2[64,16]; + TMPQ3[80,16] = TMPQ1[80,16] * TMPQ2[80,16]; + TMPQ3[96,16] = TMPQ1[96,16] * TMPQ2[96,16]; + TMPQ3[112,16] = TMPQ1[112,16] * TMPQ2[112,16]; + # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ3 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ3[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ3[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ3[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ3[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ3[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ3[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ3[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ3[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.275 SMLAL, SMLAL2 (vector) page C7-2627 line 153291 MATCH x0e208000/mask=xbf20fc00 +# CONSTRUCT x4ea08000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $*@8 &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal2/3@4 +# AUNIT --inst x4ea08000/mask=xffe0fc00 --status pass --comment "ext" + +:smlal2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x8 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = sext(TMPD1[0,32]); + TMPQ2[64,64] = sext(TMPD1[32,32]); + TMPD3 = Rm_VPR128.4S[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8) + TMPQ4[0,64] = sext(TMPD3[0,32]); + TMPQ4[64,64] = sext(TMPD3[32,32]); + # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8 + TMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64]; + TMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64]; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ5 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ5[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ5[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.275 SMLAL, SMLAL2 (vector) page C7-2627 line 153291 MATCH x0e208000/mask=xbf20fc00 +# CONSTRUCT x4e608000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $*@4 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal2/3@2 +# AUNIT --inst x4e608000/mask=xffe0fc00 --status pass --comment "ext" + +:smlal2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x8 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = sext(TMPD1[0,16]); + TMPQ2[32,32] = sext(TMPD1[16,16]); + TMPQ2[64,32] = sext(TMPD1[32,16]); + TMPQ2[96,32] = sext(TMPD1[48,16]); + TMPD3 = Rm_VPR128.8H[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4) + TMPQ4[0,32] = sext(TMPD3[0,16]); + TMPQ4[32,32] = sext(TMPD3[16,16]); + TMPQ4[64,32] = sext(TMPD3[32,16]); + TMPQ4[96,32] = sext(TMPD3[48,16]); + # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4 + TMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32]; + TMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32]; + TMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32]; + TMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32]; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ5 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ5[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ5[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ5[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ5[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.275 SMLAL, SMLAL2 (vector) page C7-2627 line 153291 MATCH x0e208000/mask=xbf20fc00 +# CONSTRUCT x4e208000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 $*@2 &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal2/3@1 +# AUNIT --inst x4e208000/mask=xffe0fc00 --status pass --comment "ext" + +:smlal2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x8 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd +{ + TMPD1 = Rn_VPR128.16B[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2) + TMPQ2[0,16] = sext(TMPD1[0,8]); + TMPQ2[16,16] = sext(TMPD1[8,8]); + TMPQ2[32,16] = sext(TMPD1[16,8]); + TMPQ2[48,16] = sext(TMPD1[24,8]); + TMPQ2[64,16] = sext(TMPD1[32,8]); + TMPQ2[80,16] = sext(TMPD1[40,8]); + TMPQ2[96,16] = sext(TMPD1[48,8]); + TMPQ2[112,16] = sext(TMPD1[56,8]); + TMPD3 = Rm_VPR128.16B[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2) + TMPQ4[0,16] = sext(TMPD3[0,8]); + TMPQ4[16,16] = sext(TMPD3[8,8]); + TMPQ4[32,16] = sext(TMPD3[16,8]); + TMPQ4[48,16] = sext(TMPD3[24,8]); + TMPQ4[64,16] = sext(TMPD3[32,8]); + TMPQ4[80,16] = sext(TMPD3[40,8]); + TMPQ4[96,16] = sext(TMPD3[48,8]); + TMPQ4[112,16] = sext(TMPD3[56,8]); + # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 2 + TMPQ5[0,16] = TMPQ2[0,16] * TMPQ4[0,16]; + TMPQ5[16,16] = TMPQ2[16,16] * TMPQ4[16,16]; + TMPQ5[32,16] = TMPQ2[32,16] * TMPQ4[32,16]; + TMPQ5[48,16] = TMPQ2[48,16] * TMPQ4[48,16]; + TMPQ5[64,16] = TMPQ2[64,16] * TMPQ4[64,16]; + TMPQ5[80,16] = TMPQ2[80,16] * TMPQ4[80,16]; + TMPQ5[96,16] = TMPQ2[96,16] * TMPQ4[96,16]; + TMPQ5[112,16] = TMPQ2[112,16] * TMPQ4[112,16]; + # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ5 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ5[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ5[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ5[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ5[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ5[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ5[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ5[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ5[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.276 SMLSL, SMLSL2 (by element) page C7-2629 line 153415 MATCH x0f006000/mask=xbf00f400 +# CONSTRUCT x0f806000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* &=$-@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl/3@4 +# AUNIT --inst x0f806000/mask=xffc0f400 --status pass --comment "ext" + +:smlsl Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex +is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x6 & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp2:4 = Re_VPR128.S.vIndex; + local tmp3:8 = sext(tmp2); + # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8 + TMPQ2[0,64] = TMPQ1[0,64] * tmp3; + TMPQ2[64,64] = TMPQ1[64,64] * tmp3; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ2 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ2[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ2[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.276 SMLSL, SMLSL2 (by element) page C7-2629 line 153415 MATCH x0f006000/mask=xbf00f400 +# CONSTRUCT x0f406000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* &=$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl/3@2 +# AUNIT --inst x0f406000/mask=xffc0f400 --status pass --comment "ext" + +:smlsl Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM +is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x6 & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]); + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp2:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp3:4 = sext(tmp2); + # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4 + TMPQ2[0,32] = TMPQ1[0,32] * tmp3; + TMPQ2[32,32] = TMPQ1[32,32] * tmp3; + TMPQ2[64,32] = TMPQ1[64,32] * tmp3; + TMPQ2[96,32] = TMPQ1[96,32] * tmp3; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ2 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ2[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ2[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ2[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ2[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.276 SMLSL, SMLSL2 (by element) page C7-2629 line 153415 MATCH x0f006000/mask=xbf00f400 +# CONSTRUCT x4f806000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 sext:8 $* &=$-@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl2/3@4 +# AUNIT --inst x4f806000/mask=xffc0f400 --status pass --comment "ext" + +:smlsl2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex +is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x6 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = sext(TMPD1[0,32]); + TMPQ2[64,64] = sext(TMPD1[32,32]); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp3:4 = Re_VPR128.S.vIndex; + local tmp4:8 = sext(tmp3); + # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8 + TMPQ3[0,64] = TMPQ2[0,64] * tmp4; + TMPQ3[64,64] = TMPQ2[64,64] * tmp4; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ3 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ3[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ3[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.276 SMLSL, SMLSL2 (by element) page C7-2629 line 153415 MATCH x0f006000/mask=xbf00f400 +# CONSTRUCT x4f406000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 sext:4 $* &=$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl2/3@2 +# AUNIT --inst x4f406000/mask=xffc0f400 --status pass --comment "ext" + +:smlsl2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM +is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x6 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = sext(TMPD1[0,16]); + TMPQ2[32,32] = sext(TMPD1[16,16]); + TMPQ2[64,32] = sext(TMPD1[32,16]); + TMPQ2[96,32] = sext(TMPD1[48,16]); + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp3:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp4:4 = sext(tmp3); + # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4 + TMPQ3[0,32] = TMPQ2[0,32] * tmp4; + TMPQ3[32,32] = TMPQ2[32,32] * tmp4; + TMPQ3[64,32] = TMPQ2[64,32] * tmp4; + TMPQ3[96,32] = TMPQ2[96,32] * tmp4; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.277 SMLSL, SMLSL2 (vector) page C7-2632 line 153579 MATCH x0e20a000/mask=xbf20fc00 +# CONSTRUCT x0ea0a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 $*@8 &=$-@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl/3@4 +# AUNIT --inst x0ea0a000/mask=xffe0fc00 --status pass --comment "ext" + +:smlsl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0xa & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]); + # simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8) + TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]); + TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]); + # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 8 + TMPQ3[0,64] = TMPQ1[0,64] * TMPQ2[0,64]; + TMPQ3[64,64] = TMPQ1[64,64] * TMPQ2[64,64]; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ3 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ3[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ3[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.277 SMLSL, SMLSL2 (vector) page C7-2632 line 153579 MATCH x0e20a000/mask=xbf20fc00 +# CONSTRUCT x0e60a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 $*@4 &=$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl/3@2 +# AUNIT --inst x0e60a000/mask=xffe0fc00 --status pass --comment "ext" + +:smlsl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0xa & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]); + # simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4) + TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]); + TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]); + TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]); + TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]); + # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 4 + TMPQ3[0,32] = TMPQ1[0,32] * TMPQ2[0,32]; + TMPQ3[32,32] = TMPQ1[32,32] * TMPQ2[32,32]; + TMPQ3[64,32] = TMPQ1[64,32] * TMPQ2[64,32]; + TMPQ3[96,32] = TMPQ1[96,32] * TMPQ2[96,32]; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.277 SMLSL, SMLSL2 (vector) page C7-2632 line 153579 MATCH x0e20a000/mask=xbf20fc00 +# CONSTRUCT x0e20a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 $*@2 &=$-@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl/3@1 +# AUNIT --inst x0e20a000/mask=xffe0fc00 --status pass --comment "ext" + +:smlsl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0xa & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2) + TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]); + TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]); + TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]); + TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]); + TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]); + TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]); + TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]); + TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]); + # simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2) + TMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]); + TMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]); + TMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]); + TMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]); + TMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]); + TMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]); + TMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]); + TMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]); + # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 2 + TMPQ3[0,16] = TMPQ1[0,16] * TMPQ2[0,16]; + TMPQ3[16,16] = TMPQ1[16,16] * TMPQ2[16,16]; + TMPQ3[32,16] = TMPQ1[32,16] * TMPQ2[32,16]; + TMPQ3[48,16] = TMPQ1[48,16] * TMPQ2[48,16]; + TMPQ3[64,16] = TMPQ1[64,16] * TMPQ2[64,16]; + TMPQ3[80,16] = TMPQ1[80,16] * TMPQ2[80,16]; + TMPQ3[96,16] = TMPQ1[96,16] * TMPQ2[96,16]; + TMPQ3[112,16] = TMPQ1[112,16] * TMPQ2[112,16]; + # simd infix Rd_VPR128.8H = Rd_VPR128.8H - TMPQ3 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] - TMPQ3[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] - TMPQ3[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] - TMPQ3[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] - TMPQ3[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] - TMPQ3[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] - TMPQ3[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] - TMPQ3[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] - TMPQ3[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.277 SMLSL, SMLSL2 (vector) page C7-2632 line 153579 MATCH x0e20a000/mask=xbf20fc00 +# CONSTRUCT x4ea0a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $*@8 &=$-@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl2/3@4 +# AUNIT --inst x4ea0a000/mask=xffe0fc00 --status pass --comment "ext" + +:smlsl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0xa & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = sext(TMPD1[0,32]); + TMPQ2[64,64] = sext(TMPD1[32,32]); + TMPD3 = Rm_VPR128.4S[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8) + TMPQ4[0,64] = sext(TMPD3[0,32]); + TMPQ4[64,64] = sext(TMPD3[32,32]); + # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8 + TMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64]; + TMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64]; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ5 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ5[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ5[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.277 SMLSL, SMLSL2 (vector) page C7-2632 line 153579 MATCH x0e20a000/mask=xbf20fc00 +# CONSTRUCT x4e60a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $*@4 &=$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl2/3@2 +# AUNIT --inst x4e60a000/mask=xffe0fc00 --status pass --comment "ext" + +:smlsl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0xa & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = sext(TMPD1[0,16]); + TMPQ2[32,32] = sext(TMPD1[16,16]); + TMPQ2[64,32] = sext(TMPD1[32,16]); + TMPQ2[96,32] = sext(TMPD1[48,16]); + TMPD3 = Rm_VPR128.8H[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4) + TMPQ4[0,32] = sext(TMPD3[0,16]); + TMPQ4[32,32] = sext(TMPD3[16,16]); + TMPQ4[64,32] = sext(TMPD3[32,16]); + TMPQ4[96,32] = sext(TMPD3[48,16]); + # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4 + TMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32]; + TMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32]; + TMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32]; + TMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32]; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ5 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ5[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ5[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ5[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ5[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.277 SMLSL, SMLSL2 (vector) page C7-2632 line 153579 MATCH x0e20a000/mask=xbf20fc00 +# CONSTRUCT x4e20a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 $*@2 &=$-@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl2/3@1 +# AUNIT --inst x4e20a000/mask=xffe0fc00 --status pass --comment "ext" + +:smlsl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0xa & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd +{ + TMPD1 = Rn_VPR128.16B[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2) + TMPQ2[0,16] = sext(TMPD1[0,8]); + TMPQ2[16,16] = sext(TMPD1[8,8]); + TMPQ2[32,16] = sext(TMPD1[16,8]); + TMPQ2[48,16] = sext(TMPD1[24,8]); + TMPQ2[64,16] = sext(TMPD1[32,8]); + TMPQ2[80,16] = sext(TMPD1[40,8]); + TMPQ2[96,16] = sext(TMPD1[48,8]); + TMPQ2[112,16] = sext(TMPD1[56,8]); + TMPD3 = Rm_VPR128.16B[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2) + TMPQ4[0,16] = sext(TMPD3[0,8]); + TMPQ4[16,16] = sext(TMPD3[8,8]); + TMPQ4[32,16] = sext(TMPD3[16,8]); + TMPQ4[48,16] = sext(TMPD3[24,8]); + TMPQ4[64,16] = sext(TMPD3[32,8]); + TMPQ4[80,16] = sext(TMPD3[40,8]); + TMPQ4[96,16] = sext(TMPD3[48,8]); + TMPQ4[112,16] = sext(TMPD3[56,8]); + # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 2 + TMPQ5[0,16] = TMPQ2[0,16] * TMPQ4[0,16]; + TMPQ5[16,16] = TMPQ2[16,16] * TMPQ4[16,16]; + TMPQ5[32,16] = TMPQ2[32,16] * TMPQ4[32,16]; + TMPQ5[48,16] = TMPQ2[48,16] * TMPQ4[48,16]; + TMPQ5[64,16] = TMPQ2[64,16] * TMPQ4[64,16]; + TMPQ5[80,16] = TMPQ2[80,16] * TMPQ4[80,16]; + TMPQ5[96,16] = TMPQ2[96,16] * TMPQ4[96,16]; + TMPQ5[112,16] = TMPQ2[112,16] * TMPQ4[112,16]; + # simd infix Rd_VPR128.8H = Rd_VPR128.8H - TMPQ5 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] - TMPQ5[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] - TMPQ5[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] - TMPQ5[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] - TMPQ5[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] - TMPQ5[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] - TMPQ5[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] - TMPQ5[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] - TMPQ5[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.279 SMOV page C7-2635 line 153760 MATCH x0e002c00/mask=xbfe0fc00 +# CONSTRUCT x0e012c00/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =sext +# SMACRO(pseudo) ARG1 ARG2 =NEON_smov/1 +# AUNIT --inst x0e012c00/mask=xffe1fc00 --status pass + +:smov Rd_GPR32, Rn_VPR128.B.imm_neon_uimm4 +is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x5 & b_1010=1 & Rn_VPR128 & Rd_GPR32 & Rd_GPR64 +{ + # simd element Rn_VPR128[imm_neon_uimm4] lane size 1 + local tmp1:1 = Rn_VPR128.B.imm_neon_uimm4; + Rd_GPR32 = sext(tmp1); + zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64 +} + +# C7.2.279 SMOV page C7-2635 line 153760 MATCH x0e002c00/mask=xbfe0fc00 +# CONSTRUCT x0e022c00/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =sext +# SMACRO(pseudo) ARG1 ARG2 =NEON_smov/1 +# AUNIT --inst x0e022c00/mask=xffe3fc00 --status pass + +:smov Rd_GPR32, Rn_VPR128.H.imm_neon_uimm3 +is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x5 & b_1010=1 & Rn_VPR128 & Rd_GPR32 & Rd_GPR64 +{ + # simd element Rn_VPR128[imm_neon_uimm3] lane size 2 + local tmp1:2 = Rn_VPR128.H.imm_neon_uimm3; + Rd_GPR32 = sext(tmp1); + zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64 +} + +# C7.2.279 SMOV page C7-2635 line 153760 MATCH x0e002c00/mask=xbfe0fc00 +# CONSTRUCT x4e012c00/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =sext +# SMACRO(pseudo) ARG1 ARG2 =NEON_smov/1 +# AUNIT --inst x4e012c00/mask=xffe1fc00 --status pass + +:smov Rd_GPR64, Rn_VPR128.B.imm_neon_uimm4 +is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x5 & b_1010=1 & Rn_VPR128 & Rd_GPR64 +{ + # simd element Rn_VPR128[imm_neon_uimm4] lane size 1 + local tmp1:1 = Rn_VPR128.B.imm_neon_uimm4; + Rd_GPR64 = sext(tmp1); +} + +# C7.2.279 SMOV page C7-2635 line 153760 MATCH x0e002c00/mask=xbfe0fc00 +# CONSTRUCT x4e022c00/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =sext +# SMACRO(pseudo) ARG1 ARG2 =NEON_smov/1 +# AUNIT --inst x4e022c00/mask=xffe3fc00 --status pass + +:smov Rd_GPR64, Rn_VPR128.H.imm_neon_uimm3 +is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x5 & b_1010=1 & Rn_VPR128 & Rd_GPR64 +{ + # simd element Rn_VPR128[imm_neon_uimm3] lane size 2 + local tmp1:2 = Rn_VPR128.H.imm_neon_uimm3; + Rd_GPR64 = sext(tmp1); +} + +# C7.2.279 SMOV page C7-2635 line 153760 MATCH x0e002c00/mask=xbfe0fc00 +# CONSTRUCT x4e042c00/mask=xffe7fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =sext +# SMACRO(pseudo) ARG1 ARG2 =NEON_smov/1 +# AUNIT --inst x4e042c00/mask=xffe7fc00 --status pass + +:smov Rd_GPR64, Rn_VPR128.S.imm_neon_uimm2 +is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & imm4=0x5 & b_1010=1 & Rn_VPR128 & Rd_GPR64 +{ + # simd element Rn_VPR128[imm_neon_uimm2] lane size 4 + local tmp1:4 = Rn_VPR128.S.imm_neon_uimm2; + Rd_GPR64 = sext(tmp1); +} + +# C7.2.280 SMULL, SMULL2 (by element) page C7-2637 line 153881 MATCH x0f00a000/mask=xbf00f400 +# CONSTRUCT x0f80a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 =$* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull/2@4 +# AUNIT --inst x0f80a000/mask=xffc0f400 --status pass --comment "ext" + +:smull Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex +is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xa & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp2:4 = Re_VPR128.S.vIndex; + local tmp3:8 = sext(tmp2); + # simd infix Rd_VPR128.2D = TMPQ1 * tmp3 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ1[0,64] * tmp3; + Rd_VPR128.2D[64,64] = TMPQ1[64,64] * tmp3; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.280 SMULL, SMULL2 (by element) page C7-2637 line 153881 MATCH x0f00a000/mask=xbf00f400 +# CONSTRUCT x0f40a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 =$* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull/2@2 +# AUNIT --inst x0f40a000/mask=xffc0f400 --status pass --comment "ext" + +:smull Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM +is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xa & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]); + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp2:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp3:4 = sext(tmp2); + # simd infix Rd_VPR128.4S = TMPQ1 * tmp3 on lane size 4 + Rd_VPR128.4S[0,32] = TMPQ1[0,32] * tmp3; + Rd_VPR128.4S[32,32] = TMPQ1[32,32] * tmp3; + Rd_VPR128.4S[64,32] = TMPQ1[64,32] * tmp3; + Rd_VPR128.4S[96,32] = TMPQ1[96,32] * tmp3; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.280 SMULL, SMULL2 (by element) page C7-2637 line 153881 MATCH x0f00a000/mask=xbf00f400 +# CONSTRUCT x4f80a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 sext:8 =$* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull2/2@4 +# AUNIT --inst x4f80a000/mask=xffc0f400 --status pass --comment "ext" + +:smull2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex +is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xa & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Rn_VPR128 & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = sext(TMPD1[0,32]); + TMPQ2[64,64] = sext(TMPD1[32,32]); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp3:4 = Re_VPR128.S.vIndex; + local tmp4:8 = sext(tmp3); + # simd infix Rd_VPR128.2D = TMPQ2 * tmp4 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ2[0,64] * tmp4; + Rd_VPR128.2D[64,64] = TMPQ2[64,64] * tmp4; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.280 SMULL, SMULL2 (by element) page C7-2637 line 153881 MATCH x0f00a000/mask=xbf00f400 +# CONSTRUCT x4f40a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 sext:4 =$* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull2/2@2 +# AUNIT --inst x4f40a000/mask=xffc0f400 --status pass --comment "ext" + +:smull2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM +is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xa & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Rn_VPR128 & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = sext(TMPD1[0,16]); + TMPQ2[32,32] = sext(TMPD1[16,16]); + TMPQ2[64,32] = sext(TMPD1[32,16]); + TMPQ2[96,32] = sext(TMPD1[48,16]); + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp3:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp4:4 = sext(tmp3); + # simd infix Rd_VPR128.4S = TMPQ2 * tmp4 on lane size 4 + Rd_VPR128.4S[0,32] = TMPQ2[0,32] * tmp4; + Rd_VPR128.4S[32,32] = TMPQ2[32,32] * tmp4; + Rd_VPR128.4S[64,32] = TMPQ2[64,32] * tmp4; + Rd_VPR128.4S[96,32] = TMPQ2[96,32] * tmp4; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.281 SMULL, SMULL2 (vector) page C7-2640 line 154037 MATCH x0e20c000/mask=xbf20fc00 +# CONSTRUCT x0ea0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 =$*@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull/2@4 +# AUNIT --inst x0ea0c000/mask=xffe0fc00 --status pass --comment "ext" + +:smull Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0xc & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]); + # simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8) + TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]); + TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]); + # simd infix Rd_VPR128.2D = TMPQ1 * TMPQ2 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ1[0,64] * TMPQ2[0,64]; + Rd_VPR128.2D[64,64] = TMPQ1[64,64] * TMPQ2[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.281 SMULL, SMULL2 (vector) page C7-2640 line 154037 MATCH x0e20c000/mask=xbf20fc00 +# CONSTRUCT x0e60c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 =$*@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull/2@2 +# AUNIT --inst x0e60c000/mask=xffe0fc00 --status pass --comment "ext" + +:smull Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0xc & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]); + # simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4) + TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]); + TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]); + TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]); + TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]); + # simd infix Rd_VPR128.4S = TMPQ1 * TMPQ2 on lane size 4 + Rd_VPR128.4S[0,32] = TMPQ1[0,32] * TMPQ2[0,32]; + Rd_VPR128.4S[32,32] = TMPQ1[32,32] * TMPQ2[32,32]; + Rd_VPR128.4S[64,32] = TMPQ1[64,32] * TMPQ2[64,32]; + Rd_VPR128.4S[96,32] = TMPQ1[96,32] * TMPQ2[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.281 SMULL, SMULL2 (vector) page C7-2640 line 154037 MATCH x0e20c000/mask=xbf20fc00 +# CONSTRUCT x0e20c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 =$*@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull/2@1 +# AUNIT --inst x0e20c000/mask=xffe0fc00 --status pass --comment "ext" + +:smull Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0xc & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2) + TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]); + TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]); + TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]); + TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]); + TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]); + TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]); + TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]); + TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]); + # simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2) + TMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]); + TMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]); + TMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]); + TMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]); + TMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]); + TMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]); + TMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]); + TMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]); + # simd infix Rd_VPR128.8H = TMPQ1 * TMPQ2 on lane size 2 + Rd_VPR128.8H[0,16] = TMPQ1[0,16] * TMPQ2[0,16]; + Rd_VPR128.8H[16,16] = TMPQ1[16,16] * TMPQ2[16,16]; + Rd_VPR128.8H[32,16] = TMPQ1[32,16] * TMPQ2[32,16]; + Rd_VPR128.8H[48,16] = TMPQ1[48,16] * TMPQ2[48,16]; + Rd_VPR128.8H[64,16] = TMPQ1[64,16] * TMPQ2[64,16]; + Rd_VPR128.8H[80,16] = TMPQ1[80,16] * TMPQ2[80,16]; + Rd_VPR128.8H[96,16] = TMPQ1[96,16] * TMPQ2[96,16]; + Rd_VPR128.8H[112,16] = TMPQ1[112,16] * TMPQ2[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.281 SMULL, SMULL2 (vector) page C7-2640 line 154037 MATCH x0e20c000/mask=xbf20fc00 +# CONSTRUCT x4ea0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 =$*@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull2/2@4 +# AUNIT --inst x4ea0c000/mask=xffe0fc00 --status pass --comment "ext" + +:smull2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0xc & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Rn_VPR128 & Rm_VPR128 & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = sext(TMPD1[0,32]); + TMPQ2[64,64] = sext(TMPD1[32,32]); + TMPD3 = Rm_VPR128.4S[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8) + TMPQ4[0,64] = sext(TMPD3[0,32]); + TMPQ4[64,64] = sext(TMPD3[32,32]); + # simd infix Rd_VPR128.2D = TMPQ2 * TMPQ4 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ2[0,64] * TMPQ4[0,64]; + Rd_VPR128.2D[64,64] = TMPQ2[64,64] * TMPQ4[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.281 SMULL, SMULL2 (vector) page C7-2640 line 154037 MATCH x0e20c000/mask=xbf20fc00 +# CONSTRUCT x4e60c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 =$*@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull2/2@2 +# AUNIT --inst x4e60c000/mask=xffe0fc00 --status pass --comment "ext" + +:smull2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0xc & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Rn_VPR128 & Rm_VPR128 & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = sext(TMPD1[0,16]); + TMPQ2[32,32] = sext(TMPD1[16,16]); + TMPQ2[64,32] = sext(TMPD1[32,16]); + TMPQ2[96,32] = sext(TMPD1[48,16]); + TMPD3 = Rm_VPR128.8H[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4) + TMPQ4[0,32] = sext(TMPD3[0,16]); + TMPQ4[32,32] = sext(TMPD3[16,16]); + TMPQ4[64,32] = sext(TMPD3[32,16]); + TMPQ4[96,32] = sext(TMPD3[48,16]); + # simd infix Rd_VPR128.4S = TMPQ2 * TMPQ4 on lane size 4 + Rd_VPR128.4S[0,32] = TMPQ2[0,32] * TMPQ4[0,32]; + Rd_VPR128.4S[32,32] = TMPQ2[32,32] * TMPQ4[32,32]; + Rd_VPR128.4S[64,32] = TMPQ2[64,32] * TMPQ4[64,32]; + Rd_VPR128.4S[96,32] = TMPQ2[96,32] * TMPQ4[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.281 SMULL, SMULL2 (vector) page C7-2640 line 154037 MATCH x0e20c000/mask=xbf20fc00 +# CONSTRUCT x4e20c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 =$*@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull2/2@1 +# AUNIT --inst x4e20c000/mask=xffe0fc00 --status pass --comment "ext" + +:smull2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0xc & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Rn_VPR128 & Rm_VPR128 & Zd +{ + TMPD1 = Rn_VPR128.16B[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2) + TMPQ2[0,16] = sext(TMPD1[0,8]); + TMPQ2[16,16] = sext(TMPD1[8,8]); + TMPQ2[32,16] = sext(TMPD1[16,8]); + TMPQ2[48,16] = sext(TMPD1[24,8]); + TMPQ2[64,16] = sext(TMPD1[32,8]); + TMPQ2[80,16] = sext(TMPD1[40,8]); + TMPQ2[96,16] = sext(TMPD1[48,8]); + TMPQ2[112,16] = sext(TMPD1[56,8]); + TMPD3 = Rm_VPR128.16B[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2) + TMPQ4[0,16] = sext(TMPD3[0,8]); + TMPQ4[16,16] = sext(TMPD3[8,8]); + TMPQ4[32,16] = sext(TMPD3[16,8]); + TMPQ4[48,16] = sext(TMPD3[24,8]); + TMPQ4[64,16] = sext(TMPD3[32,8]); + TMPQ4[80,16] = sext(TMPD3[40,8]); + TMPQ4[96,16] = sext(TMPD3[48,8]); + TMPQ4[112,16] = sext(TMPD3[56,8]); + # simd infix Rd_VPR128.8H = TMPQ2 * TMPQ4 on lane size 2 + Rd_VPR128.8H[0,16] = TMPQ2[0,16] * TMPQ4[0,16]; + Rd_VPR128.8H[16,16] = TMPQ2[16,16] * TMPQ4[16,16]; + Rd_VPR128.8H[32,16] = TMPQ2[32,16] * TMPQ4[32,16]; + Rd_VPR128.8H[48,16] = TMPQ2[48,16] * TMPQ4[48,16]; + Rd_VPR128.8H[64,16] = TMPQ2[64,16] * TMPQ4[64,16]; + Rd_VPR128.8H[80,16] = TMPQ2[80,16] * TMPQ4[80,16]; + Rd_VPR128.8H[96,16] = TMPQ2[96,16] * TMPQ4[96,16]; + Rd_VPR128.8H[112,16] = TMPQ2[112,16] * TMPQ4[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.282 SQABS page C7-2642 line 154155 MATCH x5e207800/mask=xff3ffc00 +# CONSTRUCT x5e207800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =abs +# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1 +# AUNIT --inst x5e207800/mask=xfffffc00 --status pass --comment "nointsat" +# Scalar variant when size = 00 Q = 1 aa=1 suf=FPR8 +# Note: in some implemented semantics that ignore saturation (where it +# makes a difference), there is an error in about 50% of the lanes. + +:sqabs Rd_FPR8, Rn_FPR8 +is b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b00 & b_1021=0b100000011110 & Rd_FPR8 & Rn_FPR8 & Zd +{ + Rd_FPR8 = MP_INT_ABS(Rn_FPR8); + zext_zb(Zd); # zero upper 31 bytes of Zd +} + +# C7.2.282 SQABS page C7-2642 line 154155 MATCH x5e207800/mask=xff3ffc00 +# CONSTRUCT x5e607800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =abs +# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1 +# AUNIT --inst x5e607800/mask=xfffffc00 --status pass --comment "nointsat" +# Scalar variant when size = 01 Q = 1 aa=1 suf=FPR16 + +:sqabs Rd_FPR16, Rn_FPR16 +is b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b01 & b_1021=0b100000011110 & Rd_FPR16 & Rn_FPR16 & Zd +{ + Rd_FPR16 = MP_INT_ABS(Rn_FPR16); + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.282 SQABS page C7-2642 line 154155 MATCH x5e207800/mask=xff3ffc00 +# CONSTRUCT x5ea07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =abs +# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1 +# AUNIT --inst x5ea07800/mask=xfffffc00 --status pass --comment "nointsat" +# Scalar variant when size = 10 Q = 1 aa=1 suf=FPR32 + +:sqabs Rd_FPR32, Rn_FPR32 +is b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b10 & b_1021=0b100000011110 & Rd_FPR32 & Rn_FPR32 & Zd +{ + Rd_FPR32 = MP_INT_ABS(Rn_FPR32); + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.282 SQABS page C7-2642 line 154155 MATCH x5e207800/mask=xff3ffc00 +# CONSTRUCT x5ee07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =abs +# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1 +# AUNIT --inst x5ee07800/mask=xfffffc00 --status pass --comment "nointsat" +# Scalar variant when size = 11 Q = 1 aa=1 suf=FPR64 + +:sqabs Rd_FPR64, Rn_FPR64 +is b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b11 & b_1021=0b100000011110 & Rd_FPR64 & Rn_FPR64 & Zd +{ + Rd_FPR64 = MP_INT_ABS(Rn_FPR64); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.282 SQABS page C7-2642 line 154155 MATCH x0e207800/mask=xbf3ffc00 +# CONSTRUCT x0e207800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$abs@1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@1 +# AUNIT --inst x0e207800/mask=xfffffc00 --status fail --comment "nointsat" +# Vector variant when size = 00 Q = 0 aa=0 esize=1 suf=VPR64.8B + +:sqabs Rd_VPR64.8B, Rn_VPR64.8B +is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000011110 & Rd_VPR64.8B & Rn_VPR64.8B & Zd +{ + # simd unary Rd_VPR64.8B = MP_INT_ABS(Rn_VPR64.8B) on lane size 1 + Rd_VPR64.8B[0,8] = MP_INT_ABS(Rn_VPR64.8B[0,8]); + Rd_VPR64.8B[8,8] = MP_INT_ABS(Rn_VPR64.8B[8,8]); + Rd_VPR64.8B[16,8] = MP_INT_ABS(Rn_VPR64.8B[16,8]); + Rd_VPR64.8B[24,8] = MP_INT_ABS(Rn_VPR64.8B[24,8]); + Rd_VPR64.8B[32,8] = MP_INT_ABS(Rn_VPR64.8B[32,8]); + Rd_VPR64.8B[40,8] = MP_INT_ABS(Rn_VPR64.8B[40,8]); + Rd_VPR64.8B[48,8] = MP_INT_ABS(Rn_VPR64.8B[48,8]); + Rd_VPR64.8B[56,8] = MP_INT_ABS(Rn_VPR64.8B[56,8]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.282 SQABS page C7-2642 line 154155 MATCH x0e207800/mask=xbf3ffc00 +# CONSTRUCT x4e207800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$abs@1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@1 +# AUNIT --inst x4e207800/mask=xfffffc00 --status fail --comment "nointsat" +# Vector variant when size = 00 Q = 1 aa=0 esize=1 suf=VPR128.16B + +:sqabs Rd_VPR128.16B, Rn_VPR128.16B +is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000011110 & Rd_VPR128.16B & Rn_VPR128.16B & Zd +{ + # simd unary Rd_VPR128.16B = MP_INT_ABS(Rn_VPR128.16B) on lane size 1 + Rd_VPR128.16B[0,8] = MP_INT_ABS(Rn_VPR128.16B[0,8]); + Rd_VPR128.16B[8,8] = MP_INT_ABS(Rn_VPR128.16B[8,8]); + Rd_VPR128.16B[16,8] = MP_INT_ABS(Rn_VPR128.16B[16,8]); + Rd_VPR128.16B[24,8] = MP_INT_ABS(Rn_VPR128.16B[24,8]); + Rd_VPR128.16B[32,8] = MP_INT_ABS(Rn_VPR128.16B[32,8]); + Rd_VPR128.16B[40,8] = MP_INT_ABS(Rn_VPR128.16B[40,8]); + Rd_VPR128.16B[48,8] = MP_INT_ABS(Rn_VPR128.16B[48,8]); + Rd_VPR128.16B[56,8] = MP_INT_ABS(Rn_VPR128.16B[56,8]); + Rd_VPR128.16B[64,8] = MP_INT_ABS(Rn_VPR128.16B[64,8]); + Rd_VPR128.16B[72,8] = MP_INT_ABS(Rn_VPR128.16B[72,8]); + Rd_VPR128.16B[80,8] = MP_INT_ABS(Rn_VPR128.16B[80,8]); + Rd_VPR128.16B[88,8] = MP_INT_ABS(Rn_VPR128.16B[88,8]); + Rd_VPR128.16B[96,8] = MP_INT_ABS(Rn_VPR128.16B[96,8]); + Rd_VPR128.16B[104,8] = MP_INT_ABS(Rn_VPR128.16B[104,8]); + Rd_VPR128.16B[112,8] = MP_INT_ABS(Rn_VPR128.16B[112,8]); + Rd_VPR128.16B[120,8] = MP_INT_ABS(Rn_VPR128.16B[120,8]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.282 SQABS page C7-2642 line 154155 MATCH x0e207800/mask=xbf3ffc00 +# CONSTRUCT x0e607800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$abs@2 +# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@2 +# AUNIT --inst x0e607800/mask=xfffffc00 --status pass --comment "nointsat" +# Vector variant when size = 01 Q = 0 aa=0 esize=2 suf=VPR64.4H + +:sqabs Rd_VPR64.4H, Rn_VPR64.4H +is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000011110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd +{ + # simd unary Rd_VPR64.4H = MP_INT_ABS(Rn_VPR64.4H) on lane size 2 + Rd_VPR64.4H[0,16] = MP_INT_ABS(Rn_VPR64.4H[0,16]); + Rd_VPR64.4H[16,16] = MP_INT_ABS(Rn_VPR64.4H[16,16]); + Rd_VPR64.4H[32,16] = MP_INT_ABS(Rn_VPR64.4H[32,16]); + Rd_VPR64.4H[48,16] = MP_INT_ABS(Rn_VPR64.4H[48,16]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.282 SQABS page C7-2642 line 154155 MATCH x0e207800/mask=xbf3ffc00 +# CONSTRUCT x4e607800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$abs@2 +# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@2 +# AUNIT --inst x4e607800/mask=xfffffc00 --status pass --comment "nointsat" +# Vector variant when size = 01 Q = 1 aa=0 esize=2 suf=VPR128.8H + +:sqabs Rd_VPR128.8H, Rn_VPR128.8H +is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000011110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd +{ + # simd unary Rd_VPR128.8H = MP_INT_ABS(Rn_VPR128.8H) on lane size 2 + Rd_VPR128.8H[0,16] = MP_INT_ABS(Rn_VPR128.8H[0,16]); + Rd_VPR128.8H[16,16] = MP_INT_ABS(Rn_VPR128.8H[16,16]); + Rd_VPR128.8H[32,16] = MP_INT_ABS(Rn_VPR128.8H[32,16]); + Rd_VPR128.8H[48,16] = MP_INT_ABS(Rn_VPR128.8H[48,16]); + Rd_VPR128.8H[64,16] = MP_INT_ABS(Rn_VPR128.8H[64,16]); + Rd_VPR128.8H[80,16] = MP_INT_ABS(Rn_VPR128.8H[80,16]); + Rd_VPR128.8H[96,16] = MP_INT_ABS(Rn_VPR128.8H[96,16]); + Rd_VPR128.8H[112,16] = MP_INT_ABS(Rn_VPR128.8H[112,16]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.282 SQABS page C7-2642 line 154155 MATCH x0e207800/mask=xbf3ffc00 +# CONSTRUCT x0ea07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$abs@4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@4 +# AUNIT --inst x0ea07800/mask=xfffffc00 --status pass --comment "nointsat" +# Vector variant when size = 10 Q = 0 aa=0 esize=4 suf=VPR64.2S + +:sqabs Rd_VPR64.2S, Rn_VPR64.2S +is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000011110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd +{ + # simd unary Rd_VPR64.2S = MP_INT_ABS(Rn_VPR64.2S) on lane size 4 + Rd_VPR64.2S[0,32] = MP_INT_ABS(Rn_VPR64.2S[0,32]); + Rd_VPR64.2S[32,32] = MP_INT_ABS(Rn_VPR64.2S[32,32]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.282 SQABS page C7-2642 line 154155 MATCH x0e207800/mask=xbf3ffc00 +# CONSTRUCT x4ea07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$abs@4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@4 +# AUNIT --inst x4ea07800/mask=xfffffc00 --status pass --comment "nointsat" +# Vector variant when size = 10 Q = 1 aa=0 esize=4 suf=VPR128.4S + +:sqabs Rd_VPR128.4S, Rn_VPR128.4S +is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000011110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd +{ + # simd unary Rd_VPR128.4S = MP_INT_ABS(Rn_VPR128.4S) on lane size 4 + Rd_VPR128.4S[0,32] = MP_INT_ABS(Rn_VPR128.4S[0,32]); + Rd_VPR128.4S[32,32] = MP_INT_ABS(Rn_VPR128.4S[32,32]); + Rd_VPR128.4S[64,32] = MP_INT_ABS(Rn_VPR128.4S[64,32]); + Rd_VPR128.4S[96,32] = MP_INT_ABS(Rn_VPR128.4S[96,32]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.282 SQABS page C7-2642 line 154155 MATCH x0e207800/mask=xbf3ffc00 +# CONSTRUCT x4ee07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$abs@8 +# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@8 +# AUNIT --inst x4ee07800/mask=xfffffc00 --status pass --comment "nointsat" +# Vector variant when size = 11 Q = 1 aa=0 esize=8 suf=VPR128.2D + +:sqabs Rd_VPR128.2D, Rn_VPR128.2D +is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b11 & b_1021=0b100000011110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd +{ + # simd unary Rd_VPR128.2D = MP_INT_ABS(Rn_VPR128.2D) on lane size 8 + Rd_VPR128.2D[0,64] = MP_INT_ABS(Rn_VPR128.2D[0,64]); + Rd_VPR128.2D[64,64] = MP_INT_ABS(Rn_VPR128.2D[64,64]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.283 SQADD page C7-2644 line 154278 MATCH x5e200c00/mask=xff20fc00 +# CONSTRUCT x5e200c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2 +# AUNIT --inst x5e200c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqadd Rd_FPR8, Rn_FPR8, Rm_FPR8 +is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0x1 & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd +{ + Rd_FPR8 = NEON_sqadd(Rn_FPR8, Rm_FPR8); +} + +# C7.2.283 SQADD page C7-2644 line 154278 MATCH x5e200c00/mask=xff20fc00 +# CONSTRUCT x5ee00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2 +# AUNIT --inst x5ee00c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqadd Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x1 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_sqadd(Rn_FPR64, Rm_FPR64); +} + +# C7.2.283 SQADD page C7-2644 line 154278 MATCH x5e200c00/mask=xff20fc00 +# CONSTRUCT x5e600c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2 +# AUNIT --inst x5e600c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqadd Rd_FPR16, Rn_FPR16, Rm_FPR16 +is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x1 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_sqadd(Rn_FPR16, Rm_FPR16); +} + +# C7.2.283 SQADD page C7-2644 line 154278 MATCH x5e200c00/mask=xff20fc00 +# CONSTRUCT x5ea00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2 +# AUNIT --inst x5ea00c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqadd Rd_FPR32, Rn_FPR32, Rm_FPR32 +is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x1 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_sqadd(Rn_FPR32, Rm_FPR32); +} + +# C7.2.283 SQADD page C7-2644 line 154278 MATCH x0e200c00/mask=xbf20fc00 +# CONSTRUCT x4e200c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@1 +# AUNIT --inst x4e200c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqadd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x1 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_sqadd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.283 SQADD page C7-2644 line 154278 MATCH x0e200c00/mask=xbf20fc00 +# CONSTRUCT x4ee00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@8 +# AUNIT --inst x4ee00c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqadd Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x1 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_sqadd(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.283 SQADD page C7-2644 line 154278 MATCH x0e200c00/mask=xbf20fc00 +# CONSTRUCT x0ea00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@4 +# AUNIT --inst x0ea00c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x1 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_sqadd(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.283 SQADD page C7-2644 line 154278 MATCH x0e200c00/mask=xbf20fc00 +# CONSTRUCT x0e600c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@2 +# AUNIT --inst x0e600c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x1 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_sqadd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.283 SQADD page C7-2644 line 154278 MATCH x0e200c00/mask=xbf20fc00 +# CONSTRUCT x4ea00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@4 +# AUNIT --inst x4ea00c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x1 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sqadd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.283 SQADD page C7-2644 line 154278 MATCH x0e200c00/mask=xbf20fc00 +# CONSTRUCT x0e200c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@1 +# AUNIT --inst x0e200c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqadd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x1 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_sqadd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.283 SQADD page C7-2644 line 154278 MATCH x0e200c00/mask=xbf20fc00 +# CONSTRUCT x4e600c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@2 +# AUNIT --inst x4e600c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x1 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_sqadd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.284 SQDMLAL, SQDMLAL2 (by element) page C7-2646 line 154405 MATCH x5f003000/mask=xff00f400 +# CONSTRUCT x5f803000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 * &=+/2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3 +# AUNIT --inst x5f803000/mask=xffc0f400 --status fail --comment "nointsat" +# scalar variant, size == 10 (always part == 0) + +:sqdmlal Rd_FPR64, Rn_FPR32, Re_VPR128.S.vIndex +is b_2431=0b01011111 & b_2223=0b10 & b_1215=0b0011 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rd_FPR64 & Rn_FPR32 & Zd +{ + local tmp1:8 = sext(Rn_FPR32); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp2:4 = Re_VPR128.S.vIndex; + local tmp3:8 = sext(tmp2); + local tmp4:8 = tmp1 * tmp3; + local tmp5:8 = tmp4 * 2:8; + Rd_FPR64 = Rd_FPR64 + tmp5; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.284 SQDMLAL, SQDMLAL2 (by element) page C7-2646 line 154405 MATCH x5f003000/mask=xff00f400 +# CONSTRUCT x5f403000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG3 sext:4 ARG2 sext:4 * 2:4 * &=+ +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3 +# AUNIT --inst x5f403000/mask=xffc0f400 --status fail --comment "nointsat" +# scalar variant, size == 01 (always part == 0) + +:sqdmlal Rd_FPR32, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM +is b_2431=0b01011111 & b_2223=0b01 & b_1215=0b0011 & b_10=0 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Rd_FPR32 & Rn_FPR16 & Zd +{ + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp1:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp2:4 = sext(tmp1); + local tmp3:4 = sext(Rn_FPR16); + local tmp4:4 = tmp2 * tmp3; + local tmp5:4 = tmp4 * 2:4; + Rd_FPR32 = Rd_FPR32 + tmp5; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.284 SQDMLAL, SQDMLAL2 (by element) page C7-2646 line 154405 MATCH x0f003000/mask=xbf00f400 +# CONSTRUCT x0f803000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* 2:8 $* &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3@4 +# AUNIT --inst x0f803000/mask=xffc0f400 --status fail --comment "ext nointsat" +# vector variant, Q == 0, size == 10 + +:sqdmlal Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex +is b_31=0 & b_30=0 & b_2429=0b001111 & b_2223=0b10 & b_1215=0b0011 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp2:4 = Re_VPR128.S.vIndex; + local tmp3:8 = sext(tmp2); + # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8 + TMPQ2[0,64] = TMPQ1[0,64] * tmp3; + TMPQ2[64,64] = TMPQ1[64,64] * tmp3; + # simd infix TMPQ3 = TMPQ2 * 2:8 on lane size 8 + TMPQ3[0,64] = TMPQ2[0,64] * 2:8; + TMPQ3[64,64] = TMPQ2[64,64] * 2:8; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ3 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ3[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ3[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.284 SQDMLAL, SQDMLAL2 (by element) page C7-2646 line 154405 MATCH x0f003000/mask=xbf00f400 +# CONSTRUCT x0f403000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* 2:4 $* &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3@2 +# AUNIT --inst x0f403000/mask=xffc0f400 --status fail --comment "ext nointsat" +# vector variant, Q = 0, size == 01 + +:sqdmlal Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM +is b_31=0 & b_30=0 & b_2429=0b001111 & b_2223=0b01 & b_1215=0b0011 & b_10=0 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]); + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp2:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp3:4 = sext(tmp2); + # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4 + TMPQ2[0,32] = TMPQ1[0,32] * tmp3; + TMPQ2[32,32] = TMPQ1[32,32] * tmp3; + TMPQ2[64,32] = TMPQ1[64,32] * tmp3; + TMPQ2[96,32] = TMPQ1[96,32] * tmp3; + # simd infix TMPQ3 = TMPQ2 * 2:4 on lane size 4 + TMPQ3[0,32] = TMPQ2[0,32] * 2:4; + TMPQ3[32,32] = TMPQ2[32,32] * 2:4; + TMPQ3[64,32] = TMPQ2[64,32] * 2:4; + TMPQ3[96,32] = TMPQ2[96,32] * 2:4; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.284 SQDMLAL, SQDMLAL2 (by element) page C7-2646 line 154405 MATCH x0f003000/mask=xbf00f400 +# CONSTRUCT x4f803000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 sext:8 $* 2:8 $* &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal2/3@4 +# AUNIT --inst x4f803000/mask=xffc0f400 --status fail --comment "ext nointsat" +# vector variant, Q = 1, size == 10 + +:sqdmlal2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex +is b_31=0 & b_30=1 & b_2429=0b001111 & b_2223=0b10 & b_1215=0b0011 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = sext(TMPD1[0,32]); + TMPQ2[64,64] = sext(TMPD1[32,32]); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp3:4 = Re_VPR128.S.vIndex; + local tmp4:8 = sext(tmp3); + # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8 + TMPQ3[0,64] = TMPQ2[0,64] * tmp4; + TMPQ3[64,64] = TMPQ2[64,64] * tmp4; + # simd infix TMPQ4 = TMPQ3 * 2:8 on lane size 8 + TMPQ4[0,64] = TMPQ3[0,64] * 2:8; + TMPQ4[64,64] = TMPQ3[64,64] * 2:8; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ4 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ4[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ4[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.284 SQDMLAL, SQDMLAL2 (by element) page C7-2646 line 154405 MATCH x0f003000/mask=xbf00f400 +# CONSTRUCT x4f403000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 sext:4 $* 2:4 $* &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal2/3@2 +# AUNIT --inst x4f403000/mask=xffc0f400 --status fail --comment "ext nointsat" +# vector variant, Q = 1, size == 01 + +:sqdmlal2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM +is b_31=0 & b_30=1 & b_2429=0b001111 & b_2223=0b01 & b_1215=0b0011 & b_10=0 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = sext(TMPD1[0,16]); + TMPQ2[32,32] = sext(TMPD1[16,16]); + TMPQ2[64,32] = sext(TMPD1[32,16]); + TMPQ2[96,32] = sext(TMPD1[48,16]); + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp3:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp4:4 = sext(tmp3); + # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4 + TMPQ3[0,32] = TMPQ2[0,32] * tmp4; + TMPQ3[32,32] = TMPQ2[32,32] * tmp4; + TMPQ3[64,32] = TMPQ2[64,32] * tmp4; + TMPQ3[96,32] = TMPQ2[96,32] * tmp4; + # simd infix TMPQ4 = TMPQ3 * 2:4 on lane size 4 + TMPQ4[0,32] = TMPQ3[0,32] * 2:4; + TMPQ4[32,32] = TMPQ3[32,32] * 2:4; + TMPQ4[64,32] = TMPQ3[64,32] * 2:4; + TMPQ4[96,32] = TMPQ3[96,32] * 2:4; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ4 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ4[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ4[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ4[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ4[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.285 SQDMLAL, SQDMLAL2 (vector) page C7-2650 line 154623 MATCH x5e209000/mask=xff20fc00 +# CONSTRUCT x5ea09000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 * &=+ +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3 +# AUNIT --inst x5ea09000/mask=xffe0fc00 --status fail --comment "nointsat" +# scalar variant, size == 10 (always part == 0) + +:sqdmlal Rd_FPR64, Rn_FPR32, Rm_FPR32 +is b_2431=0b01011110 & b_2223=0b10 & b_21=1 & b_1015=0b100100 & Rd_FPR64 & Rn_FPR32 & Rm_FPR32 & Zd +{ + local tmp1:8 = sext(Rn_FPR32); + local tmp2:8 = sext(Rm_FPR32); + local tmp3:8 = tmp1 * tmp2; + local tmp4:8 = tmp3 * 2:8; + Rd_FPR64 = Rd_FPR64 + tmp4; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.285 SQDMLAL, SQDMLAL2 (vector) page C7-2650 line 154623 MATCH x5e209000/mask=xff20fc00 +# CONSTRUCT x5e609000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 * &=+ +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3 +# AUNIT --inst x5e609000/mask=xffe0fc00 --status fail --comment "nointsat" +# scalar variant, size == 01 (always part == 0) + +:sqdmlal Rd_FPR32, Rn_FPR16, Rm_FPR16 +is b_2431=0b01011110 & b_2223=0b01 & b_21=1 & b_1015=0b100100 & Rd_FPR32 & Rn_FPR16 & Rm_FPR16 & Zd +{ + local tmp1:4 = sext(Rn_FPR16); + local tmp2:4 = sext(Rm_FPR16); + local tmp3:4 = tmp1 * tmp2; + local tmp4:4 = tmp3 * 2:4; + Rd_FPR32 = Rd_FPR32 + tmp4; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.285 SQDMLAL, SQDMLAL2 (vector) page C7-2650 line 154623 MATCH x0e209000/mask=xbf20fc00 +# CONSTRUCT x0ea09000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 $*@8 2:8 $* &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3@4 +# AUNIT --inst x0ea09000/mask=xffe0fc00 --status fail --comment "ext nointsat" +# vector variant, Q == 0, size == 10 + +:sqdmlal Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S +is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_21=1 & b_1015=0b100100 & Rn_VPR64.2S & Rd_VPR128.2D & Rm_VPR64.2S & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]); + # simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8) + TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]); + TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]); + # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 8 + TMPQ3[0,64] = TMPQ1[0,64] * TMPQ2[0,64]; + TMPQ3[64,64] = TMPQ1[64,64] * TMPQ2[64,64]; + # simd infix TMPQ4 = TMPQ3 * 2:8 on lane size 8 + TMPQ4[0,64] = TMPQ3[0,64] * 2:8; + TMPQ4[64,64] = TMPQ3[64,64] * 2:8; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ4 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ4[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ4[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.285 SQDMLAL, SQDMLAL2 (vector) page C7-2650 line 154623 MATCH x0e209000/mask=xbf20fc00 +# CONSTRUCT x0e609000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 $*@4 2:4 $* &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3@2 +# AUNIT --inst x0e609000/mask=xffe0fc00 --status fail --comment "ext nointsat" +# vector variant, Q = 0, size == 01 + +:sqdmlal Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_21=1 & b_1015=0b100100 & Rn_VPR64.4H & Rd_VPR128.4S & Rm_VPR64.4H & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]); + # simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4) + TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]); + TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]); + TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]); + TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]); + # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 4 + TMPQ3[0,32] = TMPQ1[0,32] * TMPQ2[0,32]; + TMPQ3[32,32] = TMPQ1[32,32] * TMPQ2[32,32]; + TMPQ3[64,32] = TMPQ1[64,32] * TMPQ2[64,32]; + TMPQ3[96,32] = TMPQ1[96,32] * TMPQ2[96,32]; + # simd infix TMPQ4 = TMPQ3 * 2:4 on lane size 4 + TMPQ4[0,32] = TMPQ3[0,32] * 2:4; + TMPQ4[32,32] = TMPQ3[32,32] * 2:4; + TMPQ4[64,32] = TMPQ3[64,32] * 2:4; + TMPQ4[96,32] = TMPQ3[96,32] * 2:4; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ4 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ4[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ4[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ4[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ4[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.285 SQDMLAL, SQDMLAL2 (vector) page C7-2650 line 154623 MATCH x0e209000/mask=xbf20fc00 +# CONSTRUCT x4ea09000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $*@8 2:8 $* &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal2/3@4 +# AUNIT --inst x4ea09000/mask=xffe0fc00 --status fail --comment "ext nointsat" +# vector variant, Q = 1, size == 10 + +:sqdmlal2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S +is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_21=1 & b_1015=0b100100 & Rn_VPR128.4S & Rd_VPR128.2D & Rm_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = sext(TMPD1[0,32]); + TMPQ2[64,64] = sext(TMPD1[32,32]); + TMPD3 = Rm_VPR128.4S[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8) + TMPQ4[0,64] = sext(TMPD3[0,32]); + TMPQ4[64,64] = sext(TMPD3[32,32]); + # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8 + TMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64]; + TMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64]; + # simd infix TMPQ6 = TMPQ5 * 2:8 on lane size 8 + TMPQ6[0,64] = TMPQ5[0,64] * 2:8; + TMPQ6[64,64] = TMPQ5[64,64] * 2:8; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ6 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ6[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ6[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.285 SQDMLAL, SQDMLAL2 (vector) page C7-2650 line 154623 MATCH x0e209000/mask=xbf20fc00 +# CONSTRUCT x4e609000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $*@4 2:4 $* &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal2/3@2 +# AUNIT --inst x4e609000/mask=xffe0fc00 --status fail --comment "ext nointsat" +# vector variant, Q = 1, size == 01 + +:sqdmlal2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_21=1 & b_1015=0b100100 & Rn_VPR128.8H & Rd_VPR128.4S & Rm_VPR128.8H & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = sext(TMPD1[0,16]); + TMPQ2[32,32] = sext(TMPD1[16,16]); + TMPQ2[64,32] = sext(TMPD1[32,16]); + TMPQ2[96,32] = sext(TMPD1[48,16]); + TMPD3 = Rm_VPR128.8H[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4) + TMPQ4[0,32] = sext(TMPD3[0,16]); + TMPQ4[32,32] = sext(TMPD3[16,16]); + TMPQ4[64,32] = sext(TMPD3[32,16]); + TMPQ4[96,32] = sext(TMPD3[48,16]); + # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4 + TMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32]; + TMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32]; + TMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32]; + TMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32]; + # simd infix TMPQ6 = TMPQ5 * 2:4 on lane size 4 + TMPQ6[0,32] = TMPQ5[0,32] * 2:4; + TMPQ6[32,32] = TMPQ5[32,32] * 2:4; + TMPQ6[64,32] = TMPQ5[64,32] * 2:4; + TMPQ6[96,32] = TMPQ5[96,32] * 2:4; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ6 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ6[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ6[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ6[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ6[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.286 SQDMLSL, SQDMLSL2 (by element) page C7-2653 line 154796 MATCH x5f007000/mask=xff00f400 +# CONSTRUCT x5f807000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 * &=- +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3 +# AUNIT --inst x5f807000/mask=xffc0f400 --status fail --comment "nointsat" +# scalar variant, size == 10 (always part == 0) + +:sqdmlsl Rd_FPR64, Rn_FPR32, Re_VPR128.S.vIndex +is b_2431=0b01011111 & b_2223=0b10 & b_1215=0b0111 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rd_FPR64 & Rn_FPR32 & Zd +{ + local tmp1:8 = sext(Rn_FPR32); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp2:4 = Re_VPR128.S.vIndex; + local tmp3:8 = sext(tmp2); + local tmp4:8 = tmp1 * tmp3; + local tmp5:8 = tmp4 * 2:8; + Rd_FPR64 = Rd_FPR64 - tmp5; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.286 SQDMLSL, SQDMLSL2 (by element) page C7-2653 line 154796 MATCH x5f007000/mask=xff00f400 +# CONSTRUCT x5f407000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 * &=- +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3 +# AUNIT --inst x5f407000/mask=xffc0f400 --status fail --comment "nointsat" +# scalar variant, size == 01 (always part == 0) + +:sqdmlsl Rd_FPR32, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM +is b_2431=0b01011111 & b_2223=0b01 & b_1215=0b0111 & b_10=0 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Rd_FPR32 & Rn_FPR16 & Zd +{ + local tmp1:4 = sext(Rn_FPR16); + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp2:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp3:4 = sext(tmp2); + local tmp4:4 = tmp1 * tmp3; + local tmp5:4 = tmp4 * 2:4; + Rd_FPR32 = Rd_FPR32 - tmp5; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.286 SQDMLSL, SQDMLSL2 (by element) page C7-2653 line 154796 MATCH x0f007000/mask=xbf00f400 +# CONSTRUCT x0f807000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* 2:8 $* &=$-@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3@4 +# AUNIT --inst x0f807000/mask=xffc0f400 --status fail --comment "ext nointsat" +# vector variant, Q == 0, size == 10 + +:sqdmlsl Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex +is b_31=0 & b_30=0 & b_2429=0b001111 & b_2223=0b10 & b_1215=0b0111 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp2:4 = Re_VPR128.S.vIndex; + local tmp3:8 = sext(tmp2); + # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8 + TMPQ2[0,64] = TMPQ1[0,64] * tmp3; + TMPQ2[64,64] = TMPQ1[64,64] * tmp3; + # simd infix TMPQ3 = TMPQ2 * 2:8 on lane size 8 + TMPQ3[0,64] = TMPQ2[0,64] * 2:8; + TMPQ3[64,64] = TMPQ2[64,64] * 2:8; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ3 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ3[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ3[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.286 SQDMLSL, SQDMLSL2 (by element) page C7-2653 line 154796 MATCH x0f007000/mask=xbf00f400 +# CONSTRUCT x0f407000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* 2:4 $* &=$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3@2 +# AUNIT --inst x0f407000/mask=xffc0f400 --status fail --comment "ext nointsat" +# vector variant, Q = 0, size == 01 + +:sqdmlsl Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM +is b_31=0 & b_30=0 & b_2429=0b001111 & b_2223=0b01 & b_1215=0b0111 & b_10=0 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]); + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp2:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp3:4 = sext(tmp2); + # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4 + TMPQ2[0,32] = TMPQ1[0,32] * tmp3; + TMPQ2[32,32] = TMPQ1[32,32] * tmp3; + TMPQ2[64,32] = TMPQ1[64,32] * tmp3; + TMPQ2[96,32] = TMPQ1[96,32] * tmp3; + # simd infix TMPQ3 = TMPQ2 * 2:4 on lane size 4 + TMPQ3[0,32] = TMPQ2[0,32] * 2:4; + TMPQ3[32,32] = TMPQ2[32,32] * 2:4; + TMPQ3[64,32] = TMPQ2[64,32] * 2:4; + TMPQ3[96,32] = TMPQ2[96,32] * 2:4; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.286 SQDMLSL, SQDMLSL2 (by element) page C7-2653 line 154796 MATCH x0f007000/mask=xbf00f400 +# CONSTRUCT x4f807000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 sext:8 $* 2:8 $* &=$-@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl2/3@4 +# AUNIT --inst x4f807000/mask=xffc0f400 --status fail --comment "ext nointsat" +# vector variant, Q = 1, size == 10 + +:sqdmlsl2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex +is b_31=0 & b_30=1 & b_2429=0b001111 & b_2223=0b10 & b_1215=0b0111 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = sext(TMPD1[0,32]); + TMPQ2[64,64] = sext(TMPD1[32,32]); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp3:4 = Re_VPR128.S.vIndex; + local tmp4:8 = sext(tmp3); + # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8 + TMPQ3[0,64] = TMPQ2[0,64] * tmp4; + TMPQ3[64,64] = TMPQ2[64,64] * tmp4; + # simd infix TMPQ4 = TMPQ3 * 2:8 on lane size 8 + TMPQ4[0,64] = TMPQ3[0,64] * 2:8; + TMPQ4[64,64] = TMPQ3[64,64] * 2:8; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ4 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ4[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ4[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.286 SQDMLSL, SQDMLSL2 (by element) page C7-2653 line 154796 MATCH x0f007000/mask=xbf00f400 +# CONSTRUCT x4f407000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 sext:4 $* 2:4 $* &=$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl2/3@2 +# AUNIT --inst x4f407000/mask=xffc0f400 --status fail --comment "ext nointsat" +# vector variant, Q = 1, size == 01 + +:sqdmlsl2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM +is b_31=0 & b_30=1 & b_2429=0b001111 & b_2223=0b01 & b_1215=0b0111 & b_10=0 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = sext(TMPD1[0,16]); + TMPQ2[32,32] = sext(TMPD1[16,16]); + TMPQ2[64,32] = sext(TMPD1[32,16]); + TMPQ2[96,32] = sext(TMPD1[48,16]); + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp3:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp4:4 = sext(tmp3); + # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4 + TMPQ3[0,32] = TMPQ2[0,32] * tmp4; + TMPQ3[32,32] = TMPQ2[32,32] * tmp4; + TMPQ3[64,32] = TMPQ2[64,32] * tmp4; + TMPQ3[96,32] = TMPQ2[96,32] * tmp4; + # simd infix TMPQ4 = TMPQ3 * 2:4 on lane size 4 + TMPQ4[0,32] = TMPQ3[0,32] * 2:4; + TMPQ4[32,32] = TMPQ3[32,32] * 2:4; + TMPQ4[64,32] = TMPQ3[64,32] * 2:4; + TMPQ4[96,32] = TMPQ3[96,32] * 2:4; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ4 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ4[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ4[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ4[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ4[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.287 SQDMLSL, SQDMLSL2 (vector) page C7-2657 line 155015 MATCH x5e20b000/mask=xff20fc00 +# CONSTRUCT x5ea0b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 * &=- +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3 +# AUNIT --inst x5ea0b000/mask=xffe0fc00 --status fail --comment "nointsat" +# scalar variant, size == 10 (always part == 0) + +:sqdmlsl Rd_FPR64, Rn_FPR32, Rm_FPR32 +is b_2431=0b01011110 & b_2223=0b10 & b_21=1 & b_1015=0b101100 & Rd_FPR64 & Rn_FPR32 & Rm_FPR32 & Zd +{ + local tmp1:8 = sext(Rn_FPR32); + local tmp2:8 = sext(Rm_FPR32); + local tmp3:8 = tmp1 * tmp2; + local tmp4:8 = tmp3 * 2:8; + Rd_FPR64 = Rd_FPR64 - tmp4; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.287 SQDMLSL, SQDMLSL2 (vector) page C7-2657 line 155015 MATCH x5e20b000/mask=xff20fc00 +# CONSTRUCT x5e60b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 * &=- +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3 +# AUNIT --inst x5e60b000/mask=xffe0fc00 --status fail --comment "nointsat" +# scalar variant, size == 01 (always part == 0) + +:sqdmlsl Rd_FPR32, Rn_FPR16, Rm_FPR16 +is b_2431=0b01011110 & b_2223=0b01 & b_21=1 & b_1015=0b101100 & Rd_FPR32 & Rn_FPR16 & Rm_FPR16 & Zd +{ + local tmp1:4 = sext(Rn_FPR16); + local tmp2:4 = sext(Rm_FPR16); + local tmp3:4 = tmp1 * tmp2; + local tmp4:4 = tmp3 * 2:4; + Rd_FPR32 = Rd_FPR32 - tmp4; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.287 SQDMLSL, SQDMLSL2 (vector) page C7-2657 line 155015 MATCH x0e20b000/mask=xbf20fc00 +# CONSTRUCT x0ea0b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 $*@8 2:8 $* &=$-@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3 +# AUNIT --inst x0ea0b000/mask=xffe0fc00 --status fail --comment "ext nointsat" +# vector variant, Q == 0, size == 10 + +:sqdmlsl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S +is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_21=1 & b_1015=0b101100 & Rn_VPR64.2S & Rd_VPR128.2D & Rm_VPR64.2S & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]); + # simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8) + TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]); + TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]); + # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 8 + TMPQ3[0,64] = TMPQ1[0,64] * TMPQ2[0,64]; + TMPQ3[64,64] = TMPQ1[64,64] * TMPQ2[64,64]; + # simd infix TMPQ4 = TMPQ3 * 2:8 on lane size 8 + TMPQ4[0,64] = TMPQ3[0,64] * 2:8; + TMPQ4[64,64] = TMPQ3[64,64] * 2:8; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ4 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ4[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ4[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.287 SQDMLSL, SQDMLSL2 (vector) page C7-2657 line 155015 MATCH x0e20b000/mask=xbf20fc00 +# CONSTRUCT x0e60b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 $*@4 2:4 $* &=$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3@2 +# AUNIT --inst x0e60b000/mask=xffe0fc00 --status fail --comment "ext nointsat" +# vector variant, Q = 0, size == 01 + +:sqdmlsl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H +is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_21=1 & b_1015=0b101100 & Rn_VPR64.4H & Rd_VPR128.4S & Rm_VPR64.4H & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]); + # simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4) + TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]); + TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]); + TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]); + TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]); + # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 4 + TMPQ3[0,32] = TMPQ1[0,32] * TMPQ2[0,32]; + TMPQ3[32,32] = TMPQ1[32,32] * TMPQ2[32,32]; + TMPQ3[64,32] = TMPQ1[64,32] * TMPQ2[64,32]; + TMPQ3[96,32] = TMPQ1[96,32] * TMPQ2[96,32]; + # simd infix TMPQ4 = TMPQ3 * 2:4 on lane size 4 + TMPQ4[0,32] = TMPQ3[0,32] * 2:4; + TMPQ4[32,32] = TMPQ3[32,32] * 2:4; + TMPQ4[64,32] = TMPQ3[64,32] * 2:4; + TMPQ4[96,32] = TMPQ3[96,32] * 2:4; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ4 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ4[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ4[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ4[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ4[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.287 SQDMLSL, SQDMLSL2 (vector) page C7-2657 line 155015 MATCH x0e20b000/mask=xbf20fc00 +# CONSTRUCT x4ea0b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $*@8 2:8 $* &=$-@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl2/3@4 +# AUNIT --inst x4ea0b000/mask=xffe0fc00 --status fail --comment "ext nointsat" +# vector variant, Q = 1, size == 10 + +:sqdmlsl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S +is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_21=1 & b_1015=0b101100 & Rn_VPR128.4S & Rd_VPR128.2D & Rm_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = sext(TMPD1[0,32]); + TMPQ2[64,64] = sext(TMPD1[32,32]); + TMPD3 = Rm_VPR128.4S[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8) + TMPQ4[0,64] = sext(TMPD3[0,32]); + TMPQ4[64,64] = sext(TMPD3[32,32]); + # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8 + TMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64]; + TMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64]; + # simd infix TMPQ6 = TMPQ5 * 2:8 on lane size 8 + TMPQ6[0,64] = TMPQ5[0,64] * 2:8; + TMPQ6[64,64] = TMPQ5[64,64] * 2:8; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ6 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ6[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ6[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.287 SQDMLSL, SQDMLSL2 (vector) page C7-2657 line 155015 MATCH x0e20b000/mask=xbf20fc00 +# CONSTRUCT x4e60b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $*@4 2:4 $* &=$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl2/3@2 +# AUNIT --inst x4e60b000/mask=xffe0fc00 --status fail --comment "ext nointsat" +# vector variant, Q = 1, size == 01 + +:sqdmlsl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H +is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_21=1 & b_1015=0b101100 & Rn_VPR128.8H & Rd_VPR128.4S & Rm_VPR128.8H & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = sext(TMPD1[0,16]); + TMPQ2[32,32] = sext(TMPD1[16,16]); + TMPQ2[64,32] = sext(TMPD1[32,16]); + TMPQ2[96,32] = sext(TMPD1[48,16]); + TMPD3 = Rm_VPR128.8H[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4) + TMPQ4[0,32] = sext(TMPD3[0,16]); + TMPQ4[32,32] = sext(TMPD3[16,16]); + TMPQ4[64,32] = sext(TMPD3[32,16]); + TMPQ4[96,32] = sext(TMPD3[48,16]); + # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4 + TMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32]; + TMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32]; + TMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32]; + TMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32]; + # simd infix TMPQ6 = TMPQ5 * 2:4 on lane size 4 + TMPQ6[0,32] = TMPQ5[0,32] * 2:4; + TMPQ6[32,32] = TMPQ5[32,32] * 2:4; + TMPQ6[64,32] = TMPQ5[64,32] * 2:4; + TMPQ6[96,32] = TMPQ5[96,32] * 2:4; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ6 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ6[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ6[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ6[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ6[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.288 SQDMULH (by element) page C7-2660 line 155188 MATCH x0f00c000/mask=xbf00f400 +# CONSTRUCT x0f80c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* 2:8 $* &=$shuffle@1-0@3-1:4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3@4 +# AUNIT --inst x0f80c000/mask=xffc0f400 --status pass --comment "ext nointsat" + +:sqdmulh Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex +is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xc & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp2:4 = Re_VPR128.S.vIndex; + local tmp3:8 = sext(tmp2); + # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8 + TMPQ2[0,64] = TMPQ1[0,64] * tmp3; + TMPQ2[64,64] = TMPQ1[64,64] * tmp3; + # simd infix TMPQ3 = TMPQ2 * 2:8 on lane size 8 + TMPQ3[0,64] = TMPQ2[0,64] * 2:8; + TMPQ3[64,64] = TMPQ2[64,64] * 2:8; + # simd shuffle Rd_VPR64.2S = TMPQ3 (@1-0@3-1) lane size 4 + Rd_VPR64.2S[0,32] = TMPQ3[32,32]; + Rd_VPR64.2S[32,32] = TMPQ3[96,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.288 SQDMULH (by element) page C7-2660 line 155188 MATCH x0f00c000/mask=xbf00f400 +# CONSTRUCT x0f40c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* 2:4 $* &=$shuffle@1-0@3-1@5-2@7-3:2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@2 +# AUNIT --inst x0f40c000/mask=xffc0f400 --status pass --comment "ext nointsat" + +:sqdmulh Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM +is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xc & b_1010=0 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]); + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp2:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp3:4 = sext(tmp2); + # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4 + TMPQ2[0,32] = TMPQ1[0,32] * tmp3; + TMPQ2[32,32] = TMPQ1[32,32] * tmp3; + TMPQ2[64,32] = TMPQ1[64,32] * tmp3; + TMPQ2[96,32] = TMPQ1[96,32] * tmp3; + # simd infix TMPQ3 = TMPQ2 * 2:4 on lane size 4 + TMPQ3[0,32] = TMPQ2[0,32] * 2:4; + TMPQ3[32,32] = TMPQ2[32,32] * 2:4; + TMPQ3[64,32] = TMPQ2[64,32] * 2:4; + TMPQ3[96,32] = TMPQ2[96,32] * 2:4; + # simd shuffle Rd_VPR64.4H = TMPQ3 (@1-0@3-1@5-2@7-3) lane size 2 + Rd_VPR64.4H[0,16] = TMPQ3[16,16]; + Rd_VPR64.4H[16,16] = TMPQ3[48,16]; + Rd_VPR64.4H[32,16] = TMPQ3[80,16]; + Rd_VPR64.4H[48,16] = TMPQ3[112,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.288 SQDMULH (by element) page C7-2660 line 155188 MATCH x0f00c000/mask=xbf00f400 +# CONSTRUCT x4f80c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@4:32 ARG3 sext:8 $* 2:8 $* &=$shuffle@1-0@3-1@5-2@7-3:4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@4 +# AUNIT --inst x4f80c000/mask=xffc0f400 --status pass --comment "ext nointsat" + +:sqdmulh Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex +is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xc & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd resize TMPZ1 = sext(Rn_VPR128.4S) (lane size 4 to 8) + TMPZ1[0,64] = sext(Rn_VPR128.4S[0,32]); + TMPZ1[64,64] = sext(Rn_VPR128.4S[32,32]); + TMPZ1[128,64] = sext(Rn_VPR128.4S[64,32]); + TMPZ1[192,64] = sext(Rn_VPR128.4S[96,32]); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp2:4 = Re_VPR128.S.vIndex; + local tmp3:8 = sext(tmp2); + # simd infix TMPZ2 = TMPZ1 * tmp3 on lane size 8 + TMPZ2[0,64] = TMPZ1[0,64] * tmp3; + TMPZ2[64,64] = TMPZ1[64,64] * tmp3; + TMPZ2[128,64] = TMPZ1[128,64] * tmp3; + TMPZ2[192,64] = TMPZ1[192,64] * tmp3; + # simd infix TMPZ3 = TMPZ2 * 2:8 on lane size 8 + TMPZ3[0,64] = TMPZ2[0,64] * 2:8; + TMPZ3[64,64] = TMPZ2[64,64] * 2:8; + TMPZ3[128,64] = TMPZ2[128,64] * 2:8; + TMPZ3[192,64] = TMPZ2[192,64] * 2:8; + # simd shuffle Rd_VPR128.4S = TMPZ3 (@1-0@3-1@5-2@7-3) lane size 4 + Rd_VPR128.4S[0,32] = TMPZ3[32,32]; + Rd_VPR128.4S[32,32] = TMPZ3[96,32]; + Rd_VPR128.4S[64,32] = TMPZ3[160,32]; + Rd_VPR128.4S[96,32] = TMPZ3[224,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.288 SQDMULH (by element) page C7-2660 line 155188 MATCH x0f00c000/mask=xbf00f400 +# CONSTRUCT x4f40c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@2:32 ARG3 sext:4 $* 2:4 $* &=$shuffle@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7:2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@2 +# AUNIT --inst x4f40c000/mask=xffc0f400 --status pass --comment "ext nointsat" + +:sqdmulh Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM +is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xc & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + # simd resize TMPZ1 = sext(Rn_VPR128.8H) (lane size 2 to 4) + TMPZ1[0,32] = sext(Rn_VPR128.8H[0,16]); + TMPZ1[32,32] = sext(Rn_VPR128.8H[16,16]); + TMPZ1[64,32] = sext(Rn_VPR128.8H[32,16]); + TMPZ1[96,32] = sext(Rn_VPR128.8H[48,16]); + TMPZ1[128,32] = sext(Rn_VPR128.8H[64,16]); + TMPZ1[160,32] = sext(Rn_VPR128.8H[80,16]); + TMPZ1[192,32] = sext(Rn_VPR128.8H[96,16]); + TMPZ1[224,32] = sext(Rn_VPR128.8H[112,16]); + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp2:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp3:4 = sext(tmp2); + # simd infix TMPZ2 = TMPZ1 * tmp3 on lane size 4 + TMPZ2[0,32] = TMPZ1[0,32] * tmp3; + TMPZ2[32,32] = TMPZ1[32,32] * tmp3; + TMPZ2[64,32] = TMPZ1[64,32] * tmp3; + TMPZ2[96,32] = TMPZ1[96,32] * tmp3; + TMPZ2[128,32] = TMPZ1[128,32] * tmp3; + TMPZ2[160,32] = TMPZ1[160,32] * tmp3; + TMPZ2[192,32] = TMPZ1[192,32] * tmp3; + TMPZ2[224,32] = TMPZ1[224,32] * tmp3; + # simd infix TMPZ3 = TMPZ2 * 2:4 on lane size 4 + TMPZ3[0,32] = TMPZ2[0,32] * 2:4; + TMPZ3[32,32] = TMPZ2[32,32] * 2:4; + TMPZ3[64,32] = TMPZ2[64,32] * 2:4; + TMPZ3[96,32] = TMPZ2[96,32] * 2:4; + TMPZ3[128,32] = TMPZ2[128,32] * 2:4; + TMPZ3[160,32] = TMPZ2[160,32] * 2:4; + TMPZ3[192,32] = TMPZ2[192,32] * 2:4; + TMPZ3[224,32] = TMPZ2[224,32] * 2:4; + # simd shuffle Rd_VPR128.8H = TMPZ3 (@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7) lane size 2 + Rd_VPR128.8H[0,16] = TMPZ3[16,16]; + Rd_VPR128.8H[16,16] = TMPZ3[48,16]; + Rd_VPR128.8H[32,16] = TMPZ3[80,16]; + Rd_VPR128.8H[48,16] = TMPZ3[112,16]; + Rd_VPR128.8H[64,16] = TMPZ3[144,16]; + Rd_VPR128.8H[80,16] = TMPZ3[176,16]; + Rd_VPR128.8H[96,16] = TMPZ3[208,16]; + Rd_VPR128.8H[112,16] = TMPZ3[240,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.288 SQDMULH (by element) page C7-2660 line 155188 MATCH x5f00c000/mask=xff00f400 +# CONSTRUCT x5f40c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 * 16:1 >>:4 = +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2 +# AUNIT --inst x5f40c000/mask=xffc0f400 --status pass --comment "nointsat" +# Scalar variant when size=01 suf=FPR16 elem=Re_VPR128Lo.H.vIndexHLM p1=Re_VPR128Lo.H p2=vIndexHLM + +:sqdmulh Rd_FPR16, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM +is b_2431=0b01011111 & b_2223=0b01 & b_1215=0b1100 & b_10=0 & Rd_FPR16 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd +{ + local tmp1:4 = sext(Rn_FPR16); + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp2:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp3:4 = sext(tmp2); + local tmp4:4 = tmp1 * tmp3; + local tmp5:4 = tmp4 * 2:4; + local tmp6:4 = tmp5 >> 16:1; + Rd_FPR16 = tmp6:2; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.288 SQDMULH (by element) page C7-2660 line 155188 MATCH x5f00c000/mask=xff00f400 +# CONSTRUCT x5f80c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 * 32:1 >>:8 = +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2 +# AUNIT --inst x5f80c000/mask=xffc0f400 --status pass --comment "nointsat" +# Scalar variant when size=10 suf=FPR32 elem=Re_VPR128.S.vIndex p1=Re_VPR128.S p2=vIndex + +:sqdmulh Rd_FPR32, Rn_FPR32, Re_VPR128.S.vIndex +is b_2431=0b01011111 & b_2223=0b10 & b_1215=0b1100 & b_10=0 & Rd_FPR32 & Rn_FPR32 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Zd +{ + local tmp1:8 = sext(Rn_FPR32); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp2:4 = Re_VPR128.S.vIndex; + local tmp3:8 = sext(tmp2); + local tmp4:8 = tmp1 * tmp3; + local tmp5:8 = tmp4 * 2:8; + local tmp6:8 = tmp5 >> 32:1; + Rd_FPR32 = tmp6:4; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.289 SQDMULH (vector) page C7-2663 line 155365 MATCH x5e20b400/mask=xff20fc00 +# CONSTRUCT x5e60b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2 +# AUNIT --inst x5e60b400/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqdmulh Rd_FPR16, Rn_FPR16, Rm_FPR16 +is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x16 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_sqdmulh(Rn_FPR16, Rm_FPR16); +} + +# C7.2.289 SQDMULH (vector) page C7-2663 line 155365 MATCH x5e20b400/mask=xff20fc00 +# CONSTRUCT x5ea0b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2 +# AUNIT --inst x5ea0b400/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqdmulh Rd_FPR32, Rn_FPR32, Rm_FPR32 +is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x16 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_sqdmulh(Rn_FPR32, Rm_FPR32); +} + +# C7.2.289 SQDMULH (vector) page C7-2663 line 155365 MATCH x0e20b400/mask=xbf20fc00 +# CONSTRUCT x0ea0b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@4 +# AUNIT --inst x0ea0b400/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqdmulh Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x16 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_sqdmulh(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.289 SQDMULH (vector) page C7-2663 line 155365 MATCH x0e20b400/mask=xbf20fc00 +# CONSTRUCT x0e60b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@2 +# AUNIT --inst x0e60b400/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqdmulh Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x16 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_sqdmulh(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.289 SQDMULH (vector) page C7-2663 line 155365 MATCH x0e20b400/mask=xbf20fc00 +# CONSTRUCT x4ea0b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@4 +# AUNIT --inst x4ea0b400/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqdmulh Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x16 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sqdmulh(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.289 SQDMULH (vector) page C7-2663 line 155365 MATCH x0e20b400/mask=xbf20fc00 +# CONSTRUCT x4e60b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@2 +# AUNIT --inst x4e60b400/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqdmulh Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x16 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_sqdmulh(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.290 SQDMULL, SQDMULL2 (by element) page C7-2665 line 155494 MATCH x0f00b000/mask=xbf00f400 +# CONSTRUCT x0f80b000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* 2:8 =$* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2@4 +# AUNIT --inst x0f80b000/mask=xffc0f400 --status pass --comment "ext nointsat" + +:sqdmull Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex +is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xb & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp2:4 = Re_VPR128.S.vIndex; + local tmp3:8 = sext(tmp2); + # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8 + TMPQ2[0,64] = TMPQ1[0,64] * tmp3; + TMPQ2[64,64] = TMPQ1[64,64] * tmp3; + # simd infix Rd_VPR128.2D = TMPQ2 * 2:8 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ2[0,64] * 2:8; + Rd_VPR128.2D[64,64] = TMPQ2[64,64] * 2:8; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.290 SQDMULL, SQDMULL2 (by element) page C7-2665 line 155494 MATCH x0f00b000/mask=xbf00f400 +# CONSTRUCT x4f80b000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 sext:8 $* 2:8 =$* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull2/2@4 +# AUNIT --inst x4f80b000/mask=xffc0f400 --status pass --comment "ext nointsat" + +:sqdmull2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex +is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xb & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = sext(TMPD1[0,32]); + TMPQ2[64,64] = sext(TMPD1[32,32]); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp3:4 = Re_VPR128.S.vIndex; + local tmp4:8 = sext(tmp3); + # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8 + TMPQ3[0,64] = TMPQ2[0,64] * tmp4; + TMPQ3[64,64] = TMPQ2[64,64] * tmp4; + # simd infix Rd_VPR128.2D = TMPQ3 * 2:8 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ3[0,64] * 2:8; + Rd_VPR128.2D[64,64] = TMPQ3[64,64] * 2:8; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.290 SQDMULL, SQDMULL2 (by element) page C7-2665 line 155494 MATCH x0f00b000/mask=xbf00f400 +# CONSTRUCT x0f40b000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* 2:4 =$* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull2/2@2 +# AUNIT --inst x0f40b000/mask=xffc0f400 --status pass --comment "ext nointsat" + +:sqdmull Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM +is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xb & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]); + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp2:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp3:4 = sext(tmp2); + # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4 + TMPQ2[0,32] = TMPQ1[0,32] * tmp3; + TMPQ2[32,32] = TMPQ1[32,32] * tmp3; + TMPQ2[64,32] = TMPQ1[64,32] * tmp3; + TMPQ2[96,32] = TMPQ1[96,32] * tmp3; + # simd infix Rd_VPR128.4S = TMPQ2 * 2:4 on lane size 4 + Rd_VPR128.4S[0,32] = TMPQ2[0,32] * 2:4; + Rd_VPR128.4S[32,32] = TMPQ2[32,32] * 2:4; + Rd_VPR128.4S[64,32] = TMPQ2[64,32] * 2:4; + Rd_VPR128.4S[96,32] = TMPQ2[96,32] * 2:4; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.290 SQDMULL, SQDMULL2 (by element) page C7-2665 line 155494 MATCH x0f00b000/mask=xbf00f400 +# CONSTRUCT x4f40b000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 sext:4 $* 2:4 =$* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull2/2@2 +# AUNIT --inst x4f40b000/mask=xffc0f400 --status pass --comment "ext nointsat" + +:sqdmull2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM +is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xb & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = sext(TMPD1[0,16]); + TMPQ2[32,32] = sext(TMPD1[16,16]); + TMPQ2[64,32] = sext(TMPD1[32,16]); + TMPQ2[96,32] = sext(TMPD1[48,16]); + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp3:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp4:4 = sext(tmp3); + # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4 + TMPQ3[0,32] = TMPQ2[0,32] * tmp4; + TMPQ3[32,32] = TMPQ2[32,32] * tmp4; + TMPQ3[64,32] = TMPQ2[64,32] * tmp4; + TMPQ3[96,32] = TMPQ2[96,32] * tmp4; + # simd infix Rd_VPR128.4S = TMPQ3 * 2:4 on lane size 4 + Rd_VPR128.4S[0,32] = TMPQ3[0,32] * 2:4; + Rd_VPR128.4S[32,32] = TMPQ3[32,32] * 2:4; + Rd_VPR128.4S[64,32] = TMPQ3[64,32] * 2:4; + Rd_VPR128.4S[96,32] = TMPQ3[96,32] * 2:4; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.290 SQDMULL, SQDMULL2 (by element) page C7-2665 line 155494 MATCH x5f00b000/mask=xff00f400 +# CONSTRUCT x5f40b000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 =* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2 +# AUNIT --inst x5f40b000/mask=xffc0f400 --status pass --comment "nointsat" +# Scalar variant when size=01 Va=FPR32 Vb=FPR16 elem=Re_VPR128Lo.H.vIndexHLM p1=Re_VPR128Lo.H p2=vIndexHLM + +:sqdmull Rd_FPR32, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM +is b_2431=0b01011111 & b_2223=0b01 & b_1215=0b1011 & b_10=0 & Rd_FPR32 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd +{ + local tmp1:4 = sext(Rn_FPR16); + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp2:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp3:4 = sext(tmp2); + local tmp4:4 = tmp1 * tmp3; + Rd_FPR32 = tmp4 * 2:4; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.290 SQDMULL, SQDMULL2 (by element) page C7-2665 line 155494 MATCH x5f00b000/mask=xff00f400 +# CONSTRUCT x5f80b000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 =* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2 +# AUNIT --inst x5f80b000/mask=xffc0f400 --status pass --comment "nointsat" +# Scalar variant when size=10 Va=FPR64 Vb=FPR32 elem=Re_VPR128.S.vIndex p1=Re_VPR128.S p2=vIndex + +:sqdmull Rd_FPR64, Rn_FPR32, Re_VPR128.S.vIndex +is b_2431=0b01011111 & b_2223=0b10 & b_1215=0b1011 & b_10=0 & Rd_FPR64 & Rn_FPR32 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Zd +{ + local tmp1:8 = sext(Rn_FPR32); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp2:4 = Re_VPR128.S.vIndex; + local tmp3:8 = sext(tmp2); + local tmp4:8 = tmp1 * tmp3; + Rd_FPR64 = tmp4 * 2:8; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.291 SQDMULL, SQDMULL2 (vector) page C7-2668 line 155694 MATCH x0e20d000/mask=xbf20fc00 +# CONSTRUCT x4ea0d000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $*@8 2:8 =$* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull2/2@4 +# AUNIT --inst x4ea0d000/mask=xffe0fc00 --status pass --comment "ext nointsat" + +:sqdmull2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0xd & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = sext(TMPD1[0,32]); + TMPQ2[64,64] = sext(TMPD1[32,32]); + TMPD3 = Rm_VPR128.4S[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8) + TMPQ4[0,64] = sext(TMPD3[0,32]); + TMPQ4[64,64] = sext(TMPD3[32,32]); + # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8 + TMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64]; + TMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64]; + # simd infix Rd_VPR128.2D = TMPQ5 * 2:8 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ5[0,64] * 2:8; + Rd_VPR128.2D[64,64] = TMPQ5[64,64] * 2:8; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.291 SQDMULL, SQDMULL2 (vector) page C7-2668 line 155694 MATCH x0e20d000/mask=xbf20fc00 +# CONSTRUCT x4e60d000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $*@4 2:4 =$* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull2/2@2 +# AUNIT --inst x4e60d000/mask=xffe0fc00 --status pass --comment "ext nointsat" + +:sqdmull2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0xd & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = sext(TMPD1[0,16]); + TMPQ2[32,32] = sext(TMPD1[16,16]); + TMPQ2[64,32] = sext(TMPD1[32,16]); + TMPQ2[96,32] = sext(TMPD1[48,16]); + TMPD3 = Rm_VPR128.8H[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4) + TMPQ4[0,32] = sext(TMPD3[0,16]); + TMPQ4[32,32] = sext(TMPD3[16,16]); + TMPQ4[64,32] = sext(TMPD3[32,16]); + TMPQ4[96,32] = sext(TMPD3[48,16]); + # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4 + TMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32]; + TMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32]; + TMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32]; + TMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32]; + # simd infix Rd_VPR128.4S = TMPQ5 * 2:4 on lane size 4 + Rd_VPR128.4S[0,32] = TMPQ5[0,32] * 2:4; + Rd_VPR128.4S[32,32] = TMPQ5[32,32] * 2:4; + Rd_VPR128.4S[64,32] = TMPQ5[64,32] * 2:4; + Rd_VPR128.4S[96,32] = TMPQ5[96,32] * 2:4; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.291 SQDMULL, SQDMULL2 (vector) page C7-2668 line 155694 MATCH x0e20d000/mask=xbf20fc00 +# CONSTRUCT x0ea0d000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2@4 +# AUNIT --inst x0ea0d000/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqdmull Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0xd & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_sqdmull(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.291 SQDMULL, SQDMULL2 (vector) page C7-2668 line 155694 MATCH x0e20d000/mask=xbf20fc00 +# CONSTRUCT x0e60d000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2@2 +# AUNIT --inst x0e60d000/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqdmull Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0xd & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sqdmull(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.291 SQDMULL, SQDMULL2 (vector) page C7-2668 line 155694 MATCH x5e20d000/mask=xff20fc00 +# CONSTRUCT x5e60d000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 =* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2 +# AUNIT --inst x5e60d000/mask=xffe0fc00 --status pass --comment "nointsat" +# Scalar variant when size=01 Va=FPR32 Vb=FPR16 + +:sqdmull Rd_FPR32, Rn_FPR16, Rm_FPR16 +is b_2431=0b01011110 & b_2223=0b01 & b_21=1 & b_1015=0b110100 & Rd_FPR32 & Rn_FPR16 & Rm_FPR16 & Zd +{ + local tmp1:4 = sext(Rn_FPR16); + local tmp2:4 = sext(Rm_FPR16); + local tmp3:4 = tmp1 * tmp2; + Rd_FPR32 = tmp3 * 2:4; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.291 SQDMULL, SQDMULL2 (vector) page C7-2668 line 155694 MATCH x5e20d000/mask=xff20fc00 +# CONSTRUCT x5ea0d000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 =* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2 +# AUNIT --inst x5ea0d000/mask=xffe0fc00 --status pass --comment "nointsat" +# Scalar variant when size=10 Va=FPR64 Vb=FPR32 + +:sqdmull Rd_FPR64, Rn_FPR32, Rm_FPR32 +is b_2431=0b01011110 & b_2223=0b10 & b_21=1 & b_1015=0b110100 & Rd_FPR64 & Rn_FPR32 & Rm_FPR32 & Zd +{ + local tmp1:8 = sext(Rn_FPR32); + local tmp2:8 = sext(Rm_FPR32); + local tmp3:8 = tmp1 * tmp2; + Rd_FPR64 = tmp3 * 2:8; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x7e207800/mask=xff3ffc00 +# CONSTRUCT x7e207800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =2comp +# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1 +# AUNIT --inst x7e207800/mask=xfffffc00 --status pass --comment "nointsat" +# Scalar variant when size=00 Q=1 aa=1 suf=FPR8 + +:sqneg Rd_FPR8, Rn_FPR8 +is b_31=0 & Q=1 & b_2429=0b111110 & b_2223=0b00 & b_1021=0b100000011110 & Rd_FPR8 & Rn_FPR8 & Zd +{ + Rd_FPR8 = - Rn_FPR8; + zext_zb(Zd); # zero upper 31 bytes of Zd +} + +# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x7e207800/mask=xff3ffc00 +# CONSTRUCT x7e607800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =2comp +# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1 +# AUNIT --inst x7e607800/mask=xfffffc00 --status pass --comment "nointsat" +# Scalar variant when size=01 Q=1 aa=1 suf=FPR16 + +:sqneg Rd_FPR16, Rn_FPR16 +is b_31=0 & Q=1 & b_2429=0b111110 & b_2223=0b01 & b_1021=0b100000011110 & Rd_FPR16 & Rn_FPR16 & Zd +{ + Rd_FPR16 = - Rn_FPR16; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x7e207800/mask=xff3ffc00 +# CONSTRUCT x7ea07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =2comp +# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1 +# AUNIT --inst x7ea07800/mask=xfffffc00 --status pass --comment "nointsat" +# Scalar variant when size=10 Q=1 aa=1 suf=FPR32 + +:sqneg Rd_FPR32, Rn_FPR32 +is b_31=0 & Q=1 & b_2429=0b111110 & b_2223=0b10 & b_1021=0b100000011110 & Rd_FPR32 & Rn_FPR32 & Zd +{ + Rd_FPR32 = - Rn_FPR32; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x7e207800/mask=xff3ffc00 +# CONSTRUCT x7ee07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =2comp +# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1 +# AUNIT --inst x7ee07800/mask=xfffffc00 --status pass --comment "nointsat" +# Scalar variant when size=11 Q=1 aa=1 suf=FPR64 + +:sqneg Rd_FPR64, Rn_FPR64 +is b_31=0 & Q=1 & b_2429=0b111110 & b_2223=0b11 & b_1021=0b100000011110 & Rd_FPR64 & Rn_FPR64 & Zd +{ + Rd_FPR64 = - Rn_FPR64; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x2e207800/mask=xbf3ffc00 +# CONSTRUCT x2e207800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$2comp@1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@1 +# AUNIT --inst x2e207800/mask=xfffffc00 --status fail --comment "nointsat" +# Vector variant when when size = 00 , Q = 0 aa=0 esize=1 suf=VPR64.8B + +:sqneg Rd_VPR64.8B, Rn_VPR64.8B +is b_31=0 & Q=0 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000011110 & Rd_VPR64.8B & Rn_VPR64.8B & Zd +{ + # simd unary Rd_VPR64.8B = -(Rn_VPR64.8B) on lane size 1 + Rd_VPR64.8B[0,8] = -(Rn_VPR64.8B[0,8]); + Rd_VPR64.8B[8,8] = -(Rn_VPR64.8B[8,8]); + Rd_VPR64.8B[16,8] = -(Rn_VPR64.8B[16,8]); + Rd_VPR64.8B[24,8] = -(Rn_VPR64.8B[24,8]); + Rd_VPR64.8B[32,8] = -(Rn_VPR64.8B[32,8]); + Rd_VPR64.8B[40,8] = -(Rn_VPR64.8B[40,8]); + Rd_VPR64.8B[48,8] = -(Rn_VPR64.8B[48,8]); + Rd_VPR64.8B[56,8] = -(Rn_VPR64.8B[56,8]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x2e207800/mask=xbf3ffc00 +# CONSTRUCT x6e207800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$2comp@1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@1 +# AUNIT --inst x6e207800/mask=xfffffc00 --status fail --comment "nointsat" +# Vector variant when when size = 00 , Q = 1 aa=0 esize=1 suf=VPR128.16B + +:sqneg Rd_VPR128.16B, Rn_VPR128.16B +is b_31=0 & Q=1 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000011110 & Rd_VPR128.16B & Rn_VPR128.16B & Zd +{ + # simd unary Rd_VPR128.16B = -(Rn_VPR128.16B) on lane size 1 + Rd_VPR128.16B[0,8] = -(Rn_VPR128.16B[0,8]); + Rd_VPR128.16B[8,8] = -(Rn_VPR128.16B[8,8]); + Rd_VPR128.16B[16,8] = -(Rn_VPR128.16B[16,8]); + Rd_VPR128.16B[24,8] = -(Rn_VPR128.16B[24,8]); + Rd_VPR128.16B[32,8] = -(Rn_VPR128.16B[32,8]); + Rd_VPR128.16B[40,8] = -(Rn_VPR128.16B[40,8]); + Rd_VPR128.16B[48,8] = -(Rn_VPR128.16B[48,8]); + Rd_VPR128.16B[56,8] = -(Rn_VPR128.16B[56,8]); + Rd_VPR128.16B[64,8] = -(Rn_VPR128.16B[64,8]); + Rd_VPR128.16B[72,8] = -(Rn_VPR128.16B[72,8]); + Rd_VPR128.16B[80,8] = -(Rn_VPR128.16B[80,8]); + Rd_VPR128.16B[88,8] = -(Rn_VPR128.16B[88,8]); + Rd_VPR128.16B[96,8] = -(Rn_VPR128.16B[96,8]); + Rd_VPR128.16B[104,8] = -(Rn_VPR128.16B[104,8]); + Rd_VPR128.16B[112,8] = -(Rn_VPR128.16B[112,8]); + Rd_VPR128.16B[120,8] = -(Rn_VPR128.16B[120,8]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x2e207800/mask=xbf3ffc00 +# CONSTRUCT x2e607800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$2comp@2 +# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@2 +# AUNIT --inst x2e607800/mask=xfffffc00 --status pass --comment "nointsat" +# Vector variant when when size = 01 , Q = 0 aa=0 esize=2 suf=VPR64.4H + +:sqneg Rd_VPR64.4H, Rn_VPR64.4H +is b_31=0 & Q=0 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000011110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd +{ + # simd unary Rd_VPR64.4H = -(Rn_VPR64.4H) on lane size 2 + Rd_VPR64.4H[0,16] = -(Rn_VPR64.4H[0,16]); + Rd_VPR64.4H[16,16] = -(Rn_VPR64.4H[16,16]); + Rd_VPR64.4H[32,16] = -(Rn_VPR64.4H[32,16]); + Rd_VPR64.4H[48,16] = -(Rn_VPR64.4H[48,16]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x2e207800/mask=xbf3ffc00 +# CONSTRUCT x6e607800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$2comp@2 +# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@2 +# AUNIT --inst x6e607800/mask=xfffffc00 --status pass --comment "nointsat" +# Vector variant when when size = 01 , Q = 1 aa=0 esize=2 suf=VPR128.8H + +:sqneg Rd_VPR128.8H, Rn_VPR128.8H +is b_31=0 & Q=1 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000011110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd +{ + # simd unary Rd_VPR128.8H = -(Rn_VPR128.8H) on lane size 2 + Rd_VPR128.8H[0,16] = -(Rn_VPR128.8H[0,16]); + Rd_VPR128.8H[16,16] = -(Rn_VPR128.8H[16,16]); + Rd_VPR128.8H[32,16] = -(Rn_VPR128.8H[32,16]); + Rd_VPR128.8H[48,16] = -(Rn_VPR128.8H[48,16]); + Rd_VPR128.8H[64,16] = -(Rn_VPR128.8H[64,16]); + Rd_VPR128.8H[80,16] = -(Rn_VPR128.8H[80,16]); + Rd_VPR128.8H[96,16] = -(Rn_VPR128.8H[96,16]); + Rd_VPR128.8H[112,16] = -(Rn_VPR128.8H[112,16]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x2e207800/mask=xbf3ffc00 +# CONSTRUCT x2ea07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$2comp@4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@4 +# AUNIT --inst x2ea07800/mask=xfffffc00 --status pass --comment "nointsat" +# Vector variant when when size = 10 , Q = 0 aa=0 esize=4 suf=VPR64.2S + +:sqneg Rd_VPR64.2S, Rn_VPR64.2S +is b_31=0 & Q=0 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000011110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd +{ + # simd unary Rd_VPR64.2S = -(Rn_VPR64.2S) on lane size 4 + Rd_VPR64.2S[0,32] = -(Rn_VPR64.2S[0,32]); + Rd_VPR64.2S[32,32] = -(Rn_VPR64.2S[32,32]); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x2e207800/mask=xbf3ffc00 +# CONSTRUCT x6ea07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$2comp@4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@4 +# AUNIT --inst x6ea07800/mask=xfffffc00 --status pass --comment "nointsat" +# Vector variant when when size = 10 , Q = 1 aa=0 esize=4 suf=VPR128.4S + +:sqneg Rd_VPR128.4S, Rn_VPR128.4S +is b_31=0 & Q=1 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000011110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd +{ + # simd unary Rd_VPR128.4S = -(Rn_VPR128.4S) on lane size 4 + Rd_VPR128.4S[0,32] = -(Rn_VPR128.4S[0,32]); + Rd_VPR128.4S[32,32] = -(Rn_VPR128.4S[32,32]); + Rd_VPR128.4S[64,32] = -(Rn_VPR128.4S[64,32]); + Rd_VPR128.4S[96,32] = -(Rn_VPR128.4S[96,32]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x2e207800/mask=xbf3ffc00 +# CONSTRUCT x6ee07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =$2comp@8 +# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@8 +# AUNIT --inst x6ee07800/mask=xfffffc00 --status pass --comment "nointsat" +# Vector variant when when size = 11 , Q = 1 aa=0 esize=8 suf=VPR128.2D + +:sqneg Rd_VPR128.2D, Rn_VPR128.2D +is b_31=0 & Q=1 & b_2429=0b101110 & b_2223=0b11 & b_1021=0b100000011110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd +{ + # simd unary Rd_VPR128.2D = -(Rn_VPR128.2D) on lane size 8 + Rd_VPR128.2D[0,64] = -(Rn_VPR128.2D[0,64]); + Rd_VPR128.2D[64,64] = -(Rn_VPR128.2D[64,64]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.277 SQRDMLAH (by element) page C7-1598 line 92254 KEEPWITH +# Integer saturating instruction (not implemented) + +sqrdml_subop: "ah" is b_24=0 & b_11=0 { export 0:1; } +sqrdml_subop: "ah" is b_24=1 & b_13=0 { export 0:1; } +sqrdml_subop: "sh" is b_24=0 & b_11=1 { export 1:1; } +sqrdml_subop: "sh" is b_24=1 & b_13=1 { export 1:1; } + +sqrdml_esize: "h" is b_2223=0b01 { export 16:1; } +sqrdml_esize: "s" is b_2223=0b10 { export 32:1; } + +sqrdml_elements: "4h" is b_2223=0b01 & b_30=0 { export 4:1; } +sqrdml_elements: "8h" is b_2223=0b01 & b_30=1 { export 8:1; } +sqrdml_elements: "2s" is b_2223=0b10 & b_30=0 { export 2:1; } +sqrdml_elements: "4s" is b_2223=0b10 & b_30=1 { export 4:1; } + +sqrdml_index: val is b_2223=0b01 & b_21 & b_20 & b_11 [ val = b_11 * 4 + b_21 * 2 + b_20; ] { export * [const]:1 val; } +sqrdml_index: val is b_2223=0b10 & b_21 & b_11 [ val = b_11 * 2 + b_21; ] { export * [const]:1 val; } + +# We could be more specific about the size of the register, which +# depends on the variant and Q (b_30). For now, I've just made them +# all 128 bits. + +sqrdml_vd: Rd_FPR16 is b_28=1 & b_2223=0b01 & Rd_FPR16 & Rd_VPR128 { export Rd_VPR128; } +sqrdml_vd: Rd_FPR32 is b_28=1 & b_2223=0b10 & Rd_FPR32 & Rd_VPR128 { export Rd_VPR128; } +sqrdml_vd: vRd_VPR128^"."^sqrdml_elements is b_28=0 & vRd_VPR128 & Rd_VPR128 & sqrdml_elements { export Rd_VPR128; } + +sqrdml_vn: Rn_FPR16 is b_28=1 & b_2223=0b01 & Rn_FPR16 & Rn_VPR128 { export Rn_VPR128; } +sqrdml_vn: Rn_FPR32 is b_28=1 & b_2223=0b10 & Rn_FPR32 & Rn_VPR128 { export Rn_VPR128; } +sqrdml_vn: vRn_VPR128^"."^sqrdml_elements is b_28=0 & vRn_VPR128 & Rn_VPR128 & sqrdml_elements { export Rn_VPR128; } + +# Decode Vm (in some cases) depending on size + +# cases 34.1, 36.1 +sqrdml_vm: Rm_FPR16 is b_28=1 & b_24=0 & b_2223=0b01 & Rm_FPR16 & Rm_VPR128 { export Rm_VPR128; } +sqrdml_vm: Rm_FPR32 is b_28=1 & b_24=0 & b_2223=0b10 & Rm_FPR32 & Rm_VPR128 { export Rm_VPR128; } + +# cases 34.2, 36.2 +sqrdml_vm: vRm_VPR128^"."^sqrdml_elements is b_28=0 & b_24=0 & vRm_VPR128 & sqrdml_elements & Rm_VPR128 { export Rm_VPR128; } + +sqrdml_vmlo: vRm_VPR128Lo is b_2223=0b01 & vRm_VPR128Lo & Rm_VPR128Lo { export Rm_VPR128Lo; } +sqrdml_vmlo: vRm_VPR128 is b_2223=0b10 & vRm_VPR128 & Rm_VPR128 { export Rm_VPR128; } + +# cases 33, 35 +sqrdml_vm: sqrdml_vmlo^"."^sqrdml_esize[sqrdml_index] is b_24=1 & sqrdml_vmlo & sqrdml_esize & sqrdml_index { export sqrdml_vmlo; } + +# SQRDML(Vd, Vn, Vm, esize, elements, subop[, index]) +# +# performs the SQRDML operation +# +# Vd[e] = SignedSatQ(Vd[e]<>:4 = +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2 +# AUNIT --inst x5f40d000/mask=xffc0f400 --status fail --comment "nointround nointsat" +# Scalar variant when size=01 suf=FPR16 elem elem=Re_VPR128Lo.H.vIndexHLM p1=Re_VPR128Lo.H p2=vIndexHLM + +:sqrdmulh Rd_FPR16, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM +is b_2431=0b01011111 & b_2223=0b01 & b_1215=0b1101 & b_10=0 & Rd_FPR16 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd +{ + local tmp1:4 = sext(Rn_FPR16); + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp2:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp3:4 = sext(tmp2); + local tmp4:4 = tmp1 * tmp3; + local tmp5:4 = tmp4 * 2:4; + local tmp6:4 = tmp5 >> 16:4; + Rd_FPR16 = tmp6:2; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.297 SQRDMULH (by element) page C7-2685 line 156680 MATCH x5f00d000/mask=xff00f400 +# CONSTRUCT x5f80d000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 * 32:8 >>:8 = +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2 +# AUNIT --inst x5f80d000/mask=xffc0f400 --status fail --comment "nointround nointsat" +# Scalar variant when size=10 suf=FPR32 elem=Re_VPR128.S.vIndex p1=Re_VPR128.S p2=vIndex + +:sqrdmulh Rd_FPR32, Rn_FPR32, Re_VPR128.S.vIndex +is b_2431=0b01011111 & b_2223=0b10 & b_1215=0b1101 & b_10=0 & Rd_FPR32 & Rn_FPR32 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Zd +{ + local tmp1:8 = sext(Rn_FPR32); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp2:4 = Re_VPR128.S.vIndex; + local tmp3:8 = sext(tmp2); + local tmp4:8 = tmp1 * tmp3; + local tmp5:8 = tmp4 * 2:8; + local tmp6:8 = tmp5 >> 32:8; + Rd_FPR32 = tmp6:4; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.298 SQRDMULH (vector) page C7-2688 line 156859 MATCH x7e20b400/mask=xff20fc00 +# CONSTRUCT x7e60b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2 +# AUNIT --inst x7e60b400/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrdmulh Rd_FPR16, Rn_FPR16, Rm_FPR16 +is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x16 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_sqrdmulh(Rn_FPR16, Rm_FPR16); +} + +# C7.2.298 SQRDMULH (vector) page C7-2688 line 156859 MATCH x7e20b400/mask=xff20fc00 +# CONSTRUCT x7ea0b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2 +# AUNIT --inst x7ea0b400/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrdmulh Rd_FPR32, Rn_FPR32, Rm_FPR32 +is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x16 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_sqrdmulh(Rn_FPR32, Rm_FPR32); +} + +# C7.2.298 SQRDMULH (vector) page C7-2688 line 156859 MATCH x2e20b400/mask=xbf20fc00 +# CONSTRUCT x2ea0b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2@4 +# AUNIT --inst x2ea0b400/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrdmulh Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x16 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_sqrdmulh(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.298 SQRDMULH (vector) page C7-2688 line 156859 MATCH x2e20b400/mask=xbf20fc00 +# CONSTRUCT x2e60b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2@2 +# AUNIT --inst x2e60b400/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrdmulh Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x16 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_sqrdmulh(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.298 SQRDMULH (vector) page C7-2688 line 156859 MATCH x2e20b400/mask=xbf20fc00 +# CONSTRUCT x6ea0b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2@4 +# AUNIT --inst x6ea0b400/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrdmulh Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x16 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sqrdmulh(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.298 SQRDMULH (vector) page C7-2688 line 156859 MATCH x2e20b400/mask=xbf20fc00 +# CONSTRUCT x6e60b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2@2 +# AUNIT --inst x6e60b400/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrdmulh Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x16 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_sqrdmulh(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x5e205c00/mask=xff20fc00 +# CONSTRUCT x5e205c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2 +# AUNIT --inst x5e205c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrshl Rd_FPR8, Rn_FPR8, Rm_FPR8 +is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0xb & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd +{ + Rd_FPR8 = NEON_sqrshl(Rn_FPR8, Rm_FPR8); +} + +# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x5e205c00/mask=xff20fc00 +# CONSTRUCT x5ee05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2 +# AUNIT --inst x5ee05c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrshl Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0xb & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_sqrshl(Rn_FPR64, Rm_FPR64); +} + +# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x5e205c00/mask=xff20fc00 +# CONSTRUCT x5e605c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2 +# AUNIT --inst x5e605c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrshl Rd_FPR16, Rn_FPR16, Rm_FPR16 +is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0xb & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_sqrshl(Rn_FPR16, Rm_FPR16); +} + +# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x5e205c00/mask=xff20fc00 +# CONSTRUCT x5ea05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2 +# AUNIT --inst x5ea05c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrshl Rd_FPR32, Rn_FPR32, Rm_FPR32 +is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0xb & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_sqrshl(Rn_FPR32, Rm_FPR32); +} + +# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x0e205c00/mask=xbf20fc00 +# CONSTRUCT x4e205c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@1 +# AUNIT --inst x4e205c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xb & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_sqrshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x0e205c00/mask=xbf20fc00 +# CONSTRUCT x4ee05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@8 +# AUNIT --inst x4ee05c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0xb & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_sqrshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x0e205c00/mask=xbf20fc00 +# CONSTRUCT x0ea05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@4 +# AUNIT --inst x0ea05c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xb & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_sqrshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x0e205c00/mask=xbf20fc00 +# CONSTRUCT x0e605c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@2 +# AUNIT --inst x0e605c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xb & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_sqrshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x0e205c00/mask=xbf20fc00 +# CONSTRUCT x4ea05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@4 +# AUNIT --inst x4ea05c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xb & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sqrshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x0e205c00/mask=xbf20fc00 +# CONSTRUCT x0e205c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@1 +# AUNIT --inst x0e205c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xb & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_sqrshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x0e205c00/mask=xbf20fc00 +# CONSTRUCT x4e605c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@2 +# AUNIT --inst x4e605c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xb & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_sqrshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x0f009c00/mask=xbf80fc00 +# CONSTRUCT x4f089c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn2/3@2 +# AUNIT --inst x4f089c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrshrn2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x13 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_sqrshrn2(Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1); +} + +# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x0f009c00/mask=xbf80fc00 +# CONSTRUCT x0f209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn/3@8 +# AUNIT --inst x0f209c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrshrn Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x13 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_sqrshrn(Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1); +} + +# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x0f009c00/mask=xbf80fc00 +# CONSTRUCT x0f109c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn/3@4 +# AUNIT --inst x0f109c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrshrn Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x13 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_sqrshrn(Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1); +} + +# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x0f009c00/mask=xbf80fc00 +# CONSTRUCT x4f209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn2/3@8 +# AUNIT --inst x4f209c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrshrn2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x13 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sqrshrn2(Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1); +} + +# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x0f009c00/mask=xbf80fc00 +# CONSTRUCT x0f089c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn2/3@2 +# AUNIT --inst x0f089c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrshrn Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x13 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_sqrshrn2(Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1); +} + +# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x0f009c00/mask=xbf80fc00 +# CONSTRUCT x4f109c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn2/3@4 +# AUNIT --inst x4f109c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrshrn2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x13 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_sqrshrn2(Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1); +} + +# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x5f009c00/mask=xff80fc00 +# CONSTRUCT x5f089c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn/3 +# AUNIT --inst x5f089c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat" +# Scalar variant when immh=0001 Va=FPR16 Vb=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001 + +:sqrshrn Rd_FPR8, Rn_FPR16, Imm_shr_imm8 +is b_2331=0b010111110 & b_1922=0b0001 & b_1015=0b100111 & Rd_FPR8 & Rn_FPR16 & Imm_shr_imm8 & Zd +{ + Rd_FPR8 = NEON_sqrshrn(Rd_FPR8, Rn_FPR16, Imm_shr_imm8:1); +} + +# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x5f009c00/mask=xff80fc00 +# CONSTRUCT x5f109c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn/3 +# AUNIT --inst x5f109c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat" +# Scalar variant when immh=001x Va=FPR32 Vb=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001 + +:sqrshrn Rd_FPR16, Rn_FPR32, Imm_shr_imm16 +is b_2331=0b010111110 & b_2022=0b001 & b_1015=0b100111 & Rd_FPR16 & Rn_FPR32 & Imm_shr_imm16 & Zd +{ + Rd_FPR16 = NEON_sqrshrn(Rd_FPR16, Rn_FPR32, Imm_shr_imm16:1); +} + +# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x5f009c00/mask=xff80fc00 +# CONSTRUCT x5f209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn/3 +# AUNIT --inst x5f209c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" +# Scalar variant when immh=01xx Va=FPR64 Vb=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01 + +:sqrshrn Rd_FPR32, Rn_FPR64, Imm_shr_imm32 +is b_2331=0b010111110 & b_2122=0b01 & b_1015=0b100111 & Rd_FPR32 & Rn_FPR64 & Imm_shr_imm32 & Zd +{ + Rd_FPR32 = NEON_sqrshrn(Rd_FPR32, Rn_FPR64, Imm_shr_imm32:1); +} + +# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x2f008c00/mask=xbf80fc00 +# CONSTRUCT x6f088c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun2/3@2 +# AUNIT --inst x6f088c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrshrun2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x11 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_sqrshrun2(Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1); +} + +# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x2f008c00/mask=xbf80fc00 +# CONSTRUCT x2f208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun/3@8 +# AUNIT --inst x2f208c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrshrun Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x11 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_sqrshrun(Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1); +} + +# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x2f008c00/mask=xbf80fc00 +# CONSTRUCT x2f108c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun/3@4 +# AUNIT --inst x2f108c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrshrun Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x11 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_sqrshrun(Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1); +} + +# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x2f008c00/mask=xbf80fc00 +# CONSTRUCT x6f208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun2/3@8 +# AUNIT --inst x6f208c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrshrun2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x11 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sqrshrun2(Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1); +} + +# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x2f008c00/mask=xbf80fc00 +# CONSTRUCT x2f088c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun/3@2 +# AUNIT --inst x2f088c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrshrun Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x11 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_sqrshrun(Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1); +} + +# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x2f008c00/mask=xbf80fc00 +# CONSTRUCT x6f108c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun2/3@4 +# AUNIT --inst x6f108c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat" + +:sqrshrun2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x11 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_sqrshrun2(Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1); +} + +# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x7f008c00/mask=xff80fc00 +# CONSTRUCT x7f088c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun/3 +# AUNIT --inst x7f088c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat" +# Scalar variant when immh=0001 Va=FPR16 Vb=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001 + +:sqrshrun Rd_FPR8, Rn_FPR16, Imm_shr_imm8 +is b_2331=0b011111110 & b_1922=0b0001 & b_1015=0b100011 & Rd_FPR8 & Rn_FPR16 & Imm_shr_imm8 & Zd +{ + Rd_FPR8 = NEON_sqrshrun(Rd_FPR8, Rn_FPR16, Imm_shr_imm8:1); +} + +# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x7f008c00/mask=xff80fc00 +# CONSTRUCT x7f108c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun/3 +# AUNIT --inst x7f108c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat" +# Scalar variant when immh=001x Va=FPR32 Vb=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001 + +:sqrshrun Rd_FPR16, Rn_FPR32, Imm_shr_imm16 +is b_2331=0b011111110 & b_2022=0b001 & b_1015=0b100011 & Rd_FPR16 & Rn_FPR32 & Imm_shr_imm16 & Zd +{ + Rd_FPR16 = NEON_sqrshrun(Rd_FPR16, Rn_FPR32, Imm_shr_imm16:1); +} + +# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x7f008c00/mask=xff80fc00 +# CONSTRUCT x7f208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun/3 +# AUNIT --inst x7f208c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" +# Scalar variant when immh=01xx Va=FPR64 Vb=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01 + +:sqrshrun Rd_FPR32, Rn_FPR64, Imm_shr_imm32 +is b_2331=0b011111110 & b_2122=0b01 & b_1015=0b100011 & Rd_FPR32 & Rn_FPR64 & Imm_shr_imm32 & Zd +{ + Rd_FPR32 = NEON_sqrshrun(Rd_FPR32, Rn_FPR64, Imm_shr_imm32:1); +} + +# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00 +# CONSTRUCT x4f087400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@1 +# AUNIT --inst x4f087400/mask=xfff8fc00 --status nopcodeop --comment "nointsat" + +:sqshl Rd_VPR128.16B, Rn_VPR128.16B, Imm_uimm3 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xe & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_sqshl(Rn_VPR128.16B, Imm_uimm3:1, 1:1); +} + +# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00 +# CONSTRUCT x4f407400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@8 +# AUNIT --inst x4f407400/mask=xffc0fc00 --status nopcodeop --comment "nointsat" + +:sqshl Rd_VPR128.2D, Rn_VPR128.2D, Imm_imm0_63 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_imm0_63 & b_1115=0xe & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_sqshl(Rn_VPR128.2D, Imm_imm0_63:1, 8:1); +} + +# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00 +# CONSTRUCT x0f207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@4 +# AUNIT --inst x0f207400/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqshl Rd_VPR64.2S, Rn_VPR64.2S, Imm_uimm5 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xe & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_sqshl(Rn_VPR64.2S, Imm_uimm5:1, 4:1); +} + +# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00 +# CONSTRUCT x0f107400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@2 +# AUNIT --inst x0f107400/mask=xfff0fc00 --status nopcodeop --comment "nointsat" + +:sqshl Rd_VPR64.4H, Rn_VPR64.4H, Imm_uimm4 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xe & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_sqshl(Rn_VPR64.4H, Imm_uimm4:1, 2:1); +} + +# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00 +# CONSTRUCT x4f207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@4 +# AUNIT --inst x4f207400/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqshl Rd_VPR128.4S, Rn_VPR128.4S, Imm_uimm5 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xe & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sqshl(Rn_VPR128.4S, Imm_uimm5:1, 4:1); +} + +# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00 +# CONSTRUCT x0f087400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@1 +# AUNIT --inst x0f087400/mask=xfff8fc00 --status nopcodeop --comment "nointsat" + +:sqshl Rd_VPR64.8B, Rn_VPR64.8B, Imm_uimm3 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xe & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_sqshl(Rn_VPR64.8B, Imm_uimm3:1, 1:1); +} + +# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00 +# CONSTRUCT x4f107400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@2 +# AUNIT --inst x4f107400/mask=xfff0fc00 --status nopcodeop --comment "nointsat" + +:sqshl Rd_VPR128.8H, Rn_VPR128.8H, Imm_uimm4 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xe & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_sqshl(Rn_VPR128.8H, Imm_uimm4:1, 2:1); +} + +# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x5f007400/mask=xff80fc00 +# CONSTRUCT x5f087400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2 +# AUNIT --inst x5f087400/mask=xfff8fc00 --status nopcodeop --comment "nointsat" +# Scalar variant when immh=0001 V=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001 + +:sqshl Rd_FPR8, Rn_FPR8, Imm_shr_imm8 +is b_2331=0b010111110 & b_1922=0b0001 & b_1015=0b011101 & Rd_FPR8 & Rn_FPR8 & Imm_shr_imm8 & Zd +{ + Rd_FPR8 = NEON_sqshl(Rn_FPR8, Imm_shr_imm8:1); +} + +# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x5f007400/mask=xff80fc00 +# CONSTRUCT x5f107400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2 +# AUNIT --inst x5f107400/mask=xfff0fc00 --status nopcodeop --comment "nointsat" +# Scalar variant when immh=001x V=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001 + +:sqshl Rd_FPR16, Rn_FPR16, Imm_shr_imm16 +is b_2331=0b010111110 & b_2022=0b001 & b_1015=0b011101 & Rd_FPR16 & Rn_FPR16 & Imm_shr_imm16 & Zd +{ + Rd_FPR16 = NEON_sqshl(Rn_FPR16, Imm_shr_imm16:1); +} + +# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x5f007400/mask=xff80fc00 +# CONSTRUCT x5f207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2 +# AUNIT --inst x5f207400/mask=xffe0fc00 --status nopcodeop --comment "nointsat" +# Scalar variant when immh=01xx V=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01 + +:sqshl Rd_FPR32, Rn_FPR32, Imm_shr_imm32 +is b_2331=0b010111110 & b_2122=0b01 & b_1015=0b011101 & Rd_FPR32 & Rn_FPR32 & Imm_shr_imm32 & Zd +{ + Rd_FPR32 = NEON_sqshl(Rn_FPR32, Imm_shr_imm32:1); +} + +# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x5f007400/mask=xff80fc00 +# CONSTRUCT x5f407400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2 +# AUNIT --inst x5f407400/mask=xffc0fc00 --status nopcodeop --comment "nointsat" +# Scalar variant when immh=1xxx V=FPR64 imm=Imm_shr_imm64 bb=b_22 aa=1 + +:sqshl Rd_FPR64, Rn_FPR64, Imm_shr_imm64 +is b_2331=0b010111110 & b_22=1 & b_1015=0b011101 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd +{ + Rd_FPR64 = NEON_sqshl(Rn_FPR64, Imm_shr_imm64:1); +} + +# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x5e204c00/mask=xff20fc00 +# CONSTRUCT x5e204c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2 +# AUNIT --inst x5e204c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqshl Rd_FPR8, Rn_FPR8, Rm_FPR8 +is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0x9 & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd +{ + Rd_FPR8 = NEON_sqshl(Rn_FPR8, Rm_FPR8); +} + +# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x5e204c00/mask=xff20fc00 +# CONSTRUCT x5ee04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2 +# AUNIT --inst x5ee04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqshl Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x9 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_sqshl(Rn_FPR64, Rm_FPR64); +} + +# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x5e204c00/mask=xff20fc00 +# CONSTRUCT x5e604c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2 +# AUNIT --inst x5e604c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqshl Rd_FPR16, Rn_FPR16, Rm_FPR16 +is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x9 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_sqshl(Rn_FPR16, Rm_FPR16); +} + +# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x5e204c00/mask=xff20fc00 +# CONSTRUCT x5ea04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2 +# AUNIT --inst x5ea04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqshl Rd_FPR32, Rn_FPR32, Rm_FPR32 +is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x9 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_sqshl(Rn_FPR32, Rm_FPR32); +} + +# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x0e204c00/mask=xbf20fc00 +# CONSTRUCT x4e204c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@1 +# AUNIT --inst x4e204c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x9 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_sqshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x0e204c00/mask=xbf20fc00 +# CONSTRUCT x4ee04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@8 +# AUNIT --inst x4ee04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x9 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_sqshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x0e204c00/mask=xbf20fc00 +# CONSTRUCT x0ea04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@4 +# AUNIT --inst x0ea04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x9 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_sqshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x0e204c00/mask=xbf20fc00 +# CONSTRUCT x0e604c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@2 +# AUNIT --inst x0e604c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x9 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_sqshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x0e204c00/mask=xbf20fc00 +# CONSTRUCT x4ea04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@4 +# AUNIT --inst x4ea04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x9 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sqshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x0e204c00/mask=xbf20fc00 +# CONSTRUCT x0e204c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@1 +# AUNIT --inst x0e204c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x9 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_sqshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x0e204c00/mask=xbf20fc00 +# CONSTRUCT x4e604c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@2 +# AUNIT --inst x4e604c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x9 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_sqshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00 +# CONSTRUCT x6f086400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@1 +# AUNIT --inst x6f086400/mask=xfff8fc00 --status nopcodeop --comment "nointsat" + +:sqshlu Rd_VPR128.16B, Rn_VPR128.16B, Imm_uimm3 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xc & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_sqshlu(Rn_VPR128.16B, Imm_uimm3:1, 1:1); +} + +# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00 +# CONSTRUCT x6f406400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@8 +# AUNIT --inst x6f406400/mask=xffc0fc00 --status nopcodeop --comment "nointsat" + +:sqshlu Rd_VPR128.2D, Rn_VPR128.2D, Imm_imm0_63 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_imm0_63 & b_1115=0xc & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_sqshlu(Rn_VPR128.2D, Imm_imm0_63:1, 8:1); +} + +# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00 +# CONSTRUCT x2f206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@4 +# AUNIT --inst x2f206400/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqshlu Rd_VPR64.2S, Rn_VPR64.2S, Imm_uimm5 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xc & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_sqshlu(Rn_VPR64.2S, Imm_uimm5:1, 4:1); +} + +# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00 +# CONSTRUCT x2f106400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@2 +# AUNIT --inst x2f106400/mask=xfff0fc00 --status nopcodeop --comment "nointsat" + +:sqshlu Rd_VPR64.4H, Rn_VPR64.4H, Imm_uimm4 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xc & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_sqshlu(Rn_VPR64.4H, Imm_uimm4:1, 2:1); +} + +# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00 +# CONSTRUCT x6f206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@4 +# AUNIT --inst x6f206400/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqshlu Rd_VPR128.4S, Rn_VPR128.4S, Imm_uimm5 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xc & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sqshlu(Rn_VPR128.4S, Imm_uimm5:1, 4:1); +} + +# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00 +# CONSTRUCT x2f086400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@1 +# AUNIT --inst x2f086400/mask=xfff8fc00 --status nopcodeop --comment "nointsat" + +:sqshlu Rd_VPR64.8B, Rn_VPR64.8B, Imm_uimm3 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xc & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_sqshlu(Rn_VPR64.8B, Imm_uimm3:1, 1:1); +} + +# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00 +# CONSTRUCT x6f106400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@2 +# AUNIT --inst x6f106400/mask=xfff0fc00 --status nopcodeop --comment "nointsat" + +:sqshlu Rd_VPR128.8H, Rn_VPR128.8H, Imm_uimm4 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xc & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_sqshlu(Rn_VPR128.8H, Imm_uimm4:1, 2:1); +} + +# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x7f006400/mask=xff80fc00 +# CONSTRUCT x7f086400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2 +# AUNIT --inst x7f086400/mask=xfff8fc00 --status nopcodeop --comment "nointsat" +# Scalar variant when immh=0001 V=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001 + +:sqshlu Rd_FPR8, Rn_FPR8, Imm_shr_imm8 +is b_2331=0b011111110 & b_1922=0b0001 & b_1015=0b011001 & Rd_FPR8 & Rn_FPR8 & Imm_shr_imm8 & Zd +{ + Rd_FPR8 = NEON_sqshlu(Rn_FPR8, Imm_shr_imm8:1); +} + +# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x7f006400/mask=xff80fc00 +# CONSTRUCT x7f106400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2 +# AUNIT --inst x7f106400/mask=xfff0fc00 --status nopcodeop --comment "nointsat" +# Scalar variant when immh=001x V=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001 + +:sqshlu Rd_FPR16, Rn_FPR16, Imm_shr_imm16 +is b_2331=0b011111110 & b_2022=0b001 & b_1015=0b011001 & Rd_FPR16 & Rn_FPR16 & Imm_shr_imm16 & Zd +{ + Rd_FPR16 = NEON_sqshlu(Rn_FPR16, Imm_shr_imm16:1); +} + +# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x7f006400/mask=xff80fc00 +# CONSTRUCT x7f206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2 +# AUNIT --inst x7f206400/mask=xffe0fc00 --status nopcodeop --comment "nointsat" +# Scalar variant when immh=01xx V=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01 + +:sqshlu Rd_FPR32, Rn_FPR32, Imm_shr_imm32 +is b_2331=0b011111110 & b_2122=0b01 & b_1015=0b011001 & Rd_FPR32 & Rn_FPR32 & Imm_shr_imm32 & Zd +{ + Rd_FPR32 = NEON_sqshlu(Rn_FPR32, Imm_shr_imm32:1); +} + +# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x7f006400/mask=xff80fc00 +# CONSTRUCT x7f406400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2 +# AUNIT --inst x7f406400/mask=xffc0fc00 --status nopcodeop --comment "nointsat" +# Scalar variant when immh=1xxx V=FPR64 imm=Imm_shr_imm64 bb=b_22 aa=1 + +:sqshlu Rd_FPR64, Rn_FPR64, Imm_shr_imm64 +is b_2331=0b011111110 & b_22=1 & b_1015=0b011001 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd +{ + Rd_FPR64 = NEON_sqshlu(Rn_FPR64, Imm_shr_imm64:1); +} + +# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x0f009400/mask=xbf80fc00 +# CONSTRUCT x4f089400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn2/3@2 +# AUNIT --inst x4f089400/mask=xfff8fc00 --status nopcodeop --comment "nointsat" + +:sqshrn2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x12 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_sqshrn2(Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1); +} + +# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x0f009400/mask=xbf80fc00 +# CONSTRUCT x0f209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn/3@8 +# AUNIT --inst x0f209400/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqshrn Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x12 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_sqshrn(Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1); +} + +# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x0f009400/mask=xbf80fc00 +# CONSTRUCT x0f109400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn/3@4 +# AUNIT --inst x0f109400/mask=xfff0fc00 --status nopcodeop --comment "nointsat" + +:sqshrn Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x12 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_sqshrn(Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1); +} + +# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x0f009400/mask=xbf80fc00 +# CONSTRUCT x4f209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn2/3@8 +# AUNIT --inst x4f209400/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqshrn2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x12 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sqshrn2(Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1); +} + +# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x0f009400/mask=xbf80fc00 +# CONSTRUCT x0f089400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn/3@2 +# AUNIT --inst x0f089400/mask=xfff8fc00 --status nopcodeop --comment "nointsat" + +:sqshrn Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x12 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_sqshrn(Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1); +} + +# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x0f009400/mask=xbf80fc00 +# CONSTRUCT x4f109400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn2/3@4 +# AUNIT --inst x4f109400/mask=xfff0fc00 --status nopcodeop --comment "nointsat" + +:sqshrn2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x12 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_sqshrn2(Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1); +} + +# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x5f009400/mask=xff80fc00 +# CONSTRUCT x5f089400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn/3 +# AUNIT --inst x5f089400/mask=xfff8fc00 --status nopcodeop --comment "nointsat" +# Scalar variant when immh=0001 Va=FPR16 Vb=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001 + +:sqshrn Rd_FPR8, Rd_FPR16, Imm_shr_imm8 +is b_2331=0b010111110 & b_1922=0b0001 & b_1015=0b100101 & Rd_FPR8 & Rd_FPR16 & Imm_shr_imm8 & Zd +{ + Rd_FPR8 = NEON_sqshrn(Rd_FPR8, Rd_FPR16, Imm_shr_imm8:1); +} + +# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x5f009400/mask=xff80fc00 +# CONSTRUCT x5f109400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn/3 +# AUNIT --inst x5f109400/mask=xfff0fc00 --status nopcodeop --comment "nointsat" +# Scalar variant when immh=001x Va=FPR32 Vb=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001 + +:sqshrn Rd_FPR16, Rd_FPR32, Imm_shr_imm16 +is b_2331=0b010111110 & b_2022=0b001 & b_1015=0b100101 & Rd_FPR16 & Rd_FPR32 & Imm_shr_imm16 & Zd +{ + Rd_FPR16 = NEON_sqshrn(Rd_FPR16, Rd_FPR32, Imm_shr_imm16:1); +} + +# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x5f009400/mask=xff80fc00 +# CONSTRUCT x5f209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn/3 +# AUNIT --inst x5f209400/mask=xffe0fc00 --status nopcodeop --comment "nointsat" +# Scalar variant when immh=01xx Va=FPR64 Vb=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01 + +:sqshrn Rd_FPR32, Rd_FPR64, Imm_shr_imm32 +is b_2331=0b010111110 & b_2122=0b01 & b_1015=0b100101 & Rd_FPR32 & Rd_FPR64 & Imm_shr_imm32 & Zd +{ + Rd_FPR32 = NEON_sqshrn(Rd_FPR32, Rd_FPR64, Imm_shr_imm32:1); +} + +# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x2f008400/mask=xbf80fc00 +# CONSTRUCT x6f088400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun2/3@2 +# AUNIT --inst x6f088400/mask=xfff8fc00 --status nopcodeop --comment "nointsat" + +:sqshrun2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x10 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_sqshrun2(Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1); +} + +# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x2f008400/mask=xbf80fc00 +# CONSTRUCT x2f208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun/3@8 +# AUNIT --inst x2f208400/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqshrun Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x10 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_sqshrun(Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1); +} + +# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x2f008400/mask=xbf80fc00 +# CONSTRUCT x2f108400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun/3@4 +# AUNIT --inst x2f108400/mask=xfff0fc00 --status nopcodeop --comment "nointsat" + +:sqshrun Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x10 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_sqshrun(Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1); +} + +# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x2f008400/mask=xbf80fc00 +# CONSTRUCT x6f208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun2/3@8 +# AUNIT --inst x6f208400/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqshrun2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x10 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sqshrun2(Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1); +} + +# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x2f008400/mask=xbf80fc00 +# CONSTRUCT x2f088400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun/3@2 +# AUNIT --inst x2f088400/mask=xfff8fc00 --status nopcodeop --comment "nointsat" + +:sqshrun Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x10 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_sqshrun(Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1); +} + +# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x2f008400/mask=xbf80fc00 +# CONSTRUCT x6f108400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun2/3@4 +# AUNIT --inst x6f108400/mask=xfff0fc00 --status nopcodeop --comment "nointsat" + +:sqshrun2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x10 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_sqshrun2(Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1); +} + +# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x7f008400/mask=xff80fc00 +# CONSTRUCT x7f088400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun/3 +# AUNIT --inst x7f088400/mask=xfff8fc00 --status nopcodeop --comment "nointsat" +# Scalar variant when immh=0001 Va=FPR16 Vb=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001 + +:sqshrun Rd_FPR8, Rd_FPR16, Imm_shr_imm8 +is b_2331=0b011111110 & b_1922=0b0001 & b_1015=0b100001 & Rd_FPR8 & Rd_FPR16 & Imm_shr_imm8 & Zd +{ + Rd_FPR8 = NEON_sqshrun(Rd_FPR8, Rd_FPR16, Imm_shr_imm8:1); +} + +# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x7f008400/mask=xff80fc00 +# CONSTRUCT x7f108400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun/3 +# AUNIT --inst x7f108400/mask=xfff0fc00 --status nopcodeop --comment "nointsat" +# Scalar variant when immh=001x Va=FPR32 Vb=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001 + +:sqshrun Rd_FPR16, Rd_FPR32, Imm_shr_imm16 +is b_2331=0b011111110 & b_2022=0b001 & b_1015=0b100001 & Rd_FPR16 & Rd_FPR32 & Imm_shr_imm16 & Zd +{ + Rd_FPR16 = NEON_sqshrun(Rd_FPR16, Rd_FPR32, Imm_shr_imm16:1); +} + +# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x7f008400/mask=xff80fc00 +# CONSTRUCT x7f208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun/3 +# AUNIT --inst x7f208400/mask=xffe0fc00 --status nopcodeop --comment "nointsat" +# Scalar variant when immh=01xx Va=FPR64 Vb=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01 + +:sqshrun Rd_FPR32, Rd_FPR64, Imm_shr_imm32 +is b_2331=0b011111110 & b_2122=0b01 & b_1015=0b100001 & Rd_FPR32 & Rd_FPR64 & Imm_shr_imm32 & Zd +{ + Rd_FPR32 = NEON_sqshrun(Rd_FPR32, Rd_FPR64, Imm_shr_imm32:1); +} + +# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x5e202c00/mask=xff20fc00 +# CONSTRUCT x5e202c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2 +# AUNIT --inst x5e202c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqsub Rd_FPR8, Rn_FPR8, Rm_FPR8 +is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0x5 & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd +{ + Rd_FPR8 = NEON_sqsub(Rn_FPR8, Rm_FPR8); +} + +# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x5e202c00/mask=xff20fc00 +# CONSTRUCT x5ee02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2 +# AUNIT --inst x5ee02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqsub Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x5 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_sqsub(Rn_FPR64, Rm_FPR64); +} + +# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x5e202c00/mask=xff20fc00 +# CONSTRUCT x5e602c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2 +# AUNIT --inst x5e602c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqsub Rd_FPR16, Rn_FPR16, Rm_FPR16 +is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x5 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_sqsub(Rn_FPR16, Rm_FPR16); +} + +# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x5e202c00/mask=xff20fc00 +# CONSTRUCT x5ea02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2 +# AUNIT --inst x5ea02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqsub Rd_FPR32, Rn_FPR32, Rm_FPR32 +is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x5 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_sqsub(Rn_FPR32, Rm_FPR32); +} + +# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x0e202c00/mask=xbf20fc00 +# CONSTRUCT x4e202c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@1 +# AUNIT --inst x4e202c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqsub Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x5 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_sqsub(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x0e202c00/mask=xbf20fc00 +# CONSTRUCT x4ee02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@8 +# AUNIT --inst x4ee02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqsub Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x5 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_sqsub(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x0e202c00/mask=xbf20fc00 +# CONSTRUCT x0ea02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@4 +# AUNIT --inst x0ea02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqsub Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x5 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_sqsub(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x0e202c00/mask=xbf20fc00 +# CONSTRUCT x0e602c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@2 +# AUNIT --inst x0e602c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqsub Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x5 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_sqsub(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x0e202c00/mask=xbf20fc00 +# CONSTRUCT x4ea02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@4 +# AUNIT --inst x4ea02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqsub Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x5 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sqsub(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x0e202c00/mask=xbf20fc00 +# CONSTRUCT x0e202c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@1 +# AUNIT --inst x0e202c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqsub Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x5 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_sqsub(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x0e202c00/mask=xbf20fc00 +# CONSTRUCT x4e602c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@2 +# AUNIT --inst x4e602c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:sqsub Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x5 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_sqsub(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x5e214800/mask=xff3ffc00 +# CONSTRUCT x5e214800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn/2 +# AUNIT --inst x5e214800/mask=xfffffc00 --status nopcodeop --comment "nointsat" + +:sqxtn Rd_FPR8, Rn_FPR16 +is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_FPR16 & Rd_FPR8 & Zd +{ + Rd_FPR8 = NEON_sqxtn(Rd_FPR8, Rn_FPR16); +} + +# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x5e214800/mask=xff3ffc00 +# CONSTRUCT x5e614800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn/2 +# AUNIT --inst x5e614800/mask=xfffffc00 --status nopcodeop --comment "nointsat" + +:sqxtn Rd_FPR16, Rn_FPR32 +is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_FPR32 & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_sqxtn(Rd_FPR16, Rn_FPR32); +} + +# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x5e214800/mask=xff3ffc00 +# CONSTRUCT x5ea14800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn/2 +# AUNIT --inst x5ea14800/mask=xfffffc00 --status nopcodeop --comment "nointsat" + +:sqxtn Rd_FPR32, Rn_FPR64 +is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_FPR64 & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_sqxtn(Rd_FPR32, Rn_FPR64); +} + +# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x0e214800/mask=xbf3ffc00 +# CONSTRUCT x4e214800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn2/2@2 +# AUNIT --inst x4e214800/mask=xfffffc00 --status nopcodeop --comment "nointsat" + +:sqxtn2 Rd_VPR128.16B, Rn_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_sqxtn2(Rd_VPR128.16B, Rn_VPR128.8H, 2:1); +} + +# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x0e214800/mask=xbf3ffc00 +# CONSTRUCT x4e614800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn2/2@4 +# AUNIT --inst x4e614800/mask=xfffffc00 --status nopcodeop --comment "nointsat" + +:sqxtn2 Rd_VPR128.8H, Rn_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_sqxtn2(Rd_VPR128.8H, Rn_VPR128.4S, 4:1); +} + +# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x0e214800/mask=xbf3ffc00 +# CONSTRUCT x4ea14800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn2/2@8 +# AUNIT --inst x4ea14800/mask=xfffffc00 --status nopcodeop --comment "nointsat" + +:sqxtn2 Rd_VPR128.4S, Rn_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sqxtn2(Rd_VPR128.4S, Rn_VPR128.2D, 8:1); +} + +# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x0e214800/mask=xbf3ffc00 +# CONSTRUCT x0ea14800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn/2@8 +# AUNIT --inst x0ea14800/mask=xfffffc00 --status nopcodeop --comment "nointsat" + +:sqxtn Rd_VPR64.2S, Rn_VPR128.2D +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_VPR128.2D & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_sqxtn(Rd_VPR64.2S, Rn_VPR128.2D, 8:1); +} + +# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x0e214800/mask=xbf3ffc00 +# CONSTRUCT x0e614800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn/2@4 +# AUNIT --inst x0e614800/mask=xfffffc00 --status nopcodeop --comment "nointsat" + +:sqxtn Rd_VPR64.4H, Rn_VPR128.4S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_VPR128.4S & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_sqxtn(Rd_VPR64.4H, Rn_VPR128.4S, 4:1); +} + +# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x0e214800/mask=xbf3ffc00 +# CONSTRUCT x0e214800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn/2@2 +# AUNIT --inst x0e214800/mask=xfffffc00 --status nopcodeop --comment "nointsat" + +:sqxtn Rd_VPR64.8B, Rn_VPR128.8H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_VPR128.8H & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_sqxtn(Rd_VPR64.8B, Rn_VPR128.8H, 2:1); +} + +# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x7e212800/mask=xff3ffc00 +# CONSTRUCT x7e212800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun/2 +# AUNIT --inst x7e212800/mask=xfffffc00 --status noqemu --comment "nointsat" +# Scalar variant when size=00 Q=1 bb=1 Ta=FPR16 Tb=FPR8 + +:sqxtun Rd_FPR8, Rn_FPR16 +is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b00 & b_1021=0b100001001010 & Rd_FPR8 & Rn_FPR16 & Zd +{ + Rd_FPR8 = NEON_sqxtun(Rd_FPR8, Rn_FPR16); +} + +# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x7e212800/mask=xff3ffc00 +# CONSTRUCT x7e612800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun/2 +# AUNIT --inst x7e612800/mask=xfffffc00 --status noqemu --comment "nointsat" +# Scalar variant when size=01 Q=1 bb=1 Ta=FPR32 Tb=FPR16 + +:sqxtun Rd_FPR16, Rn_FPR32 +is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b01 & b_1021=0b100001001010 & Rd_FPR16 & Rn_FPR32 & Zd +{ + Rd_FPR16 = NEON_sqxtun(Rd_FPR16, Rn_FPR32); +} + +# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x7e212800/mask=xff3ffc00 +# CONSTRUCT x7ea12800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun/2 +# AUNIT --inst x7ea12800/mask=xfffffc00 --status noqemu --comment "nointsat" +# Scalar variant when size=10 Q=1 bb=1 Ta=FPR64 Tb=FPR32 + +:sqxtun Rd_FPR32, Rn_FPR64 +is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b10 & b_1021=0b100001001010 & Rd_FPR32 & Rn_FPR64 & Zd +{ + Rd_FPR32 = NEON_sqxtun(Rd_FPR32, Rn_FPR64); +} + +# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x2e212800/mask=xbf3ffc00 +# CONSTRUCT x2e212800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun/2@2 +# AUNIT --inst x2e212800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Vector variant when size=00 Q=0 bb=0 Ta=VPR128.8H Tb=VPR64.8B esize=2 + +:sqxtun Rd_VPR64.8B, Rn_VPR128.8H +is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100001001010 & Rd_VPR64.8B & Rn_VPR128.8H & Zd +{ + Rd_VPR64.8B = NEON_sqxtun(Rd_VPR64.8B, Rn_VPR128.8H, 2:1); +} + +# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x2e212800/mask=xbf3ffc00 +# CONSTRUCT x6e212800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun2/2@2 +# AUNIT --inst x6e212800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Vector variant when size=00 Q=1 bb=0 Ta=VPR128.8H Tb=VPR128.16B esize=2 + +:sqxtun2 Rd_VPR128.16B, Rn_VPR128.8H +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100001001010 & Rd_VPR128.16B & Rn_VPR128.8H & Zd +{ + Rd_VPR128.16B = NEON_sqxtun2(Rd_VPR128.16B, Rn_VPR128.8H, 2:1); +} + +# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x2e212800/mask=xbf3ffc00 +# CONSTRUCT x2e612800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun/2@4 +# AUNIT --inst x2e612800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Vector variant when size=01 Q=0 bb=0 Ta=VPR128.4S Tb=VPR64.4H esize=4 + +:sqxtun Rd_VPR64.4H, Rn_VPR128.4S +is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100001001010 & Rd_VPR64.4H & Rn_VPR128.4S & Zd +{ + Rd_VPR64.4H = NEON_sqxtun(Rd_VPR64.4H, Rn_VPR128.4S, 4:1); +} + +# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x2e212800/mask=xbf3ffc00 +# CONSTRUCT x6e612800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun2/2@4 +# AUNIT --inst x6e612800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Vector variant when size=01 Q=1 bb=0 Ta=VPR128.4S Tb=VPR128.8H esize=4 + +:sqxtun2 Rd_VPR128.8H, Rn_VPR128.4S +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100001001010 & Rd_VPR128.8H & Rn_VPR128.4S & Zd +{ + Rd_VPR128.8H = NEON_sqxtun2(Rd_VPR128.8H, Rn_VPR128.4S, 4:1); +} + +# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x2e212800/mask=xbf3ffc00 +# CONSTRUCT x2ea12800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun/2@8 +# AUNIT --inst x2ea12800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Vector variant when size=10 Q=0 bb=0 Ta=VPR128.2D Tb=VPR64.2S esize=8 + +:sqxtun Rd_VPR64.2S, Rn_VPR128.2D +is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100001001010 & Rd_VPR64.2S & Rn_VPR128.2D & Zd +{ + Rd_VPR64.2S = NEON_sqxtun(Rd_VPR64.2S, Rn_VPR128.2D, 8:1); +} + +# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x2e212800/mask=xbf3ffc00 +# CONSTRUCT x6ea12800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun2/2@8 +# AUNIT --inst x6ea12800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Vector variant when size=10 Q=1 bb=0 Ta=VPR128.2D Tb=VPR128.4S esize=8 + +:sqxtun2 Rd_VPR128.4S, Rn_VPR128.2D +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100001001010 & Rd_VPR128.4S & Rn_VPR128.2D & Zd +{ + Rd_VPR128.4S = NEON_sqxtun2(Rd_VPR128.4S, Rn_VPR128.2D, 8:1); +} + +# C7.2.310 SRHADD page C7-2720 line 158773 MATCH x0e201400/mask=xbf20fc00 +# CONSTRUCT x4e201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_srhadd/2@1 +# AUNIT --inst x4e201400/mask=xffe0fc00 --status nopcodeop + +:srhadd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x2 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rn_VPR128.16B = NEON_srhadd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.310 SRHADD page C7-2720 line 158773 MATCH x0e201400/mask=xbf20fc00 +# CONSTRUCT x0ea01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_srhadd/2@4 +# AUNIT --inst x0ea01400/mask=xffe0fc00 --status nopcodeop + +:srhadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x2 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rn_VPR64.2S = NEON_srhadd(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.310 SRHADD page C7-2720 line 158773 MATCH x0e201400/mask=xbf20fc00 +# CONSTRUCT x0e601400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_srhadd/2@2 +# AUNIT --inst x0e601400/mask=xffe0fc00 --status nopcodeop + +:srhadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x2 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rn_VPR64.4H = NEON_srhadd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.310 SRHADD page C7-2720 line 158773 MATCH x0e201400/mask=xbf20fc00 +# CONSTRUCT x4ea01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_srhadd/2@4 +# AUNIT --inst x4ea01400/mask=xffe0fc00 --status nopcodeop + +:srhadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x2 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rn_VPR128.4S = NEON_srhadd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.310 SRHADD page C7-2720 line 158773 MATCH x0e201400/mask=xbf20fc00 +# CONSTRUCT x0e201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_srhadd/2@1 +# AUNIT --inst x0e201400/mask=xffe0fc00 --status nopcodeop + +:srhadd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x2 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rn_VPR64.8B = NEON_srhadd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.310 SRHADD page C7-2720 line 158773 MATCH x0e201400/mask=xbf20fc00 +# CONSTRUCT x4e601400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_srhadd/2@2 +# AUNIT --inst x4e601400/mask=xffe0fc00 --status nopcodeop + +:srhadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x2 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rn_VPR128.8H = NEON_srhadd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00 +# CONSTRUCT x6f084400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@1 +# AUNIT --inst x6f084400/mask=xfff8fc00 --status nopcodeop + +:sri Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x8 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_sri(Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8:4, 1:1); +} + +# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00 +# CONSTRUCT x6f404400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@8 +# AUNIT --inst x6f404400/mask=xffc0fc00 --status nopcodeop + +:sri Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x8 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_sri(Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64:4, 8:1); +} + +# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00 +# CONSTRUCT x2f204400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@4 +# AUNIT --inst x2f204400/mask=xffe0fc00 --status nopcodeop + +:sri Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x8 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_sri(Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32:4, 4:1); +} + +# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00 +# CONSTRUCT x2f104400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@2 +# AUNIT --inst x2f104400/mask=xfff0fc00 --status nopcodeop + +:sri Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x8 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_sri(Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16:4, 2:1); +} + +# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00 +# CONSTRUCT x6f204400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@4 +# AUNIT --inst x6f204400/mask=xffe0fc00 --status nopcodeop + +:sri Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x8 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sri(Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32:4, 4:1); +} + +# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00 +# CONSTRUCT x2f084400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@1 +# AUNIT --inst x2f084400/mask=xfff8fc00 --status nopcodeop + +:sri Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x8 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_sri(Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8:4, 1:1); +} + +# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00 +# CONSTRUCT x6f104400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@2 +# AUNIT --inst x6f104400/mask=xfff0fc00 --status nopcodeop + +:sri Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x8 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_sri(Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16:4, 2:1); +} + +# C7.2.311 SRI page C7-2722 line 158861 MATCH x7f004400/mask=xff80fc00 +# CONSTRUCT x7f404400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sri/3 +# AUNIT --inst x7f404400/mask=xffc0fc00 --status nopcodeop + +:sri Rd_FPR64, Rn_FPR64, Imm_shr_imm64 +is b_2331=0b011111110 & b_22=1 & b_1015=0b010001 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd +{ + Rd_FPR64 = NEON_sri(Rd_FPR64, Rn_FPR64, Imm_shr_imm64:1); +} + +# C7.2.312 SRSHL page C7-2725 line 159028 MATCH x5e205400/mask=xff20fc00 +# CONSTRUCT x5ee05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2 +# AUNIT --inst x5ee05400/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:srshl Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0xa & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_srshl(Rn_FPR64, Rm_FPR64); +} + +# C7.2.312 SRSHL page C7-2725 line 159028 MATCH x0e205400/mask=xbf20fc00 +# CONSTRUCT x4e205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@1 +# AUNIT --inst x4e205400/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:srshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xa & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_srshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.312 SRSHL page C7-2725 line 159028 MATCH x0e205400/mask=xbf20fc00 +# CONSTRUCT x4ee05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@8 +# AUNIT --inst x4ee05400/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:srshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0xa & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_srshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.312 SRSHL page C7-2725 line 159028 MATCH x0e205400/mask=xbf20fc00 +# CONSTRUCT x0ea05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@4 +# AUNIT --inst x0ea05400/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:srshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xa & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_srshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.312 SRSHL page C7-2725 line 159028 MATCH x0e205400/mask=xbf20fc00 +# CONSTRUCT x0e605400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@2 +# AUNIT --inst x0e605400/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:srshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xa & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_srshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.312 SRSHL page C7-2725 line 159028 MATCH x0e205400/mask=xbf20fc00 +# CONSTRUCT x4ea05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@4 +# AUNIT --inst x4ea05400/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:srshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xa & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_srshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.312 SRSHL page C7-2725 line 159028 MATCH x0e205400/mask=xbf20fc00 +# CONSTRUCT x0e205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@1 +# AUNIT --inst x0e205400/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:srshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xa & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_srshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.312 SRSHL page C7-2725 line 159028 MATCH x0e205400/mask=xbf20fc00 +# CONSTRUCT x4e605400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@2 +# AUNIT --inst x4e605400/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:srshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xa & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_srshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00 +# CONSTRUCT x4f082400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@1 +# AUNIT --inst x4f082400/mask=xfff8fc00 --status nopcodeop --comment "nointround" + +:srshr Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x4 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_srshr(Rn_VPR128.16B, Imm_shr_imm8:1, 1:1); +} + +# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00 +# CONSTRUCT x4f402400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@8 +# AUNIT --inst x4f402400/mask=xffc0fc00 --status nopcodeop --comment "nointround" + +:srshr Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x4 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_srshr(Rn_VPR128.2D, Imm_shr_imm64:1, 8:1); +} + +# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00 +# CONSTRUCT x0f202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@4 +# AUNIT --inst x0f202400/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:srshr Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x4 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_srshr(Rn_VPR64.2S, Imm_shr_imm32:1, 4:1); +} + +# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00 +# CONSTRUCT x0f102400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@2 +# AUNIT --inst x0f102400/mask=xfff0fc00 --status nopcodeop --comment "nointround" + +:srshr Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x4 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_srshr(Rn_VPR64.4H, Imm_shr_imm16:1, 2:1); +} + +# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00 +# CONSTRUCT x4f202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@4 +# AUNIT --inst x4f202400/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:srshr Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x4 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_srshr(Rn_VPR128.4S, Imm_shr_imm32:1, 4:1); +} + +# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00 +# CONSTRUCT x0f082400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@1 +# AUNIT --inst x0f082400/mask=xfff8fc00 --status nopcodeop --comment "nointround" + +:srshr Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x4 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_srshr(Rn_VPR64.8B, Imm_shr_imm8:1, 1:1); +} + +# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00 +# CONSTRUCT x4f102400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@2 +# AUNIT --inst x4f102400/mask=xfff0fc00 --status nopcodeop --comment "nointround" + +:srshr Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x4 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_srshr(Rn_VPR128.8H, Imm_shr_imm16:1, 2:1); +} + +# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x5f002400/mask=xff80fc00 +# CONSTRUCT x5f402400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2 +# AUNIT --inst x5f402400/mask=xffc0fc00 --status nopcodeop --comment "nointround" + +:srshr Rd_FPR64, Rn_FPR64, Imm_shr_imm64 +is b_2331=0b010111110 & b_22=1 & b_1015=0b001001 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd +{ + Rd_FPR64 = NEON_srshr(Rn_FPR64, Imm_shr_imm64:1); +} + +# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00 +# CONSTRUCT x4f083400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:1 $s>>@1 &=$+@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@1 +# AUNIT --inst x4f083400/mask=xfff8fc00 --status fail --comment "nointround" + +:srsra Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x6 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.16B s>> Imm_shr_imm8:1 on lane size 1 + TMPQ1[0,8] = Rn_VPR128.16B[0,8] s>> Imm_shr_imm8:1; + TMPQ1[8,8] = Rn_VPR128.16B[8,8] s>> Imm_shr_imm8:1; + TMPQ1[16,8] = Rn_VPR128.16B[16,8] s>> Imm_shr_imm8:1; + TMPQ1[24,8] = Rn_VPR128.16B[24,8] s>> Imm_shr_imm8:1; + TMPQ1[32,8] = Rn_VPR128.16B[32,8] s>> Imm_shr_imm8:1; + TMPQ1[40,8] = Rn_VPR128.16B[40,8] s>> Imm_shr_imm8:1; + TMPQ1[48,8] = Rn_VPR128.16B[48,8] s>> Imm_shr_imm8:1; + TMPQ1[56,8] = Rn_VPR128.16B[56,8] s>> Imm_shr_imm8:1; + TMPQ1[64,8] = Rn_VPR128.16B[64,8] s>> Imm_shr_imm8:1; + TMPQ1[72,8] = Rn_VPR128.16B[72,8] s>> Imm_shr_imm8:1; + TMPQ1[80,8] = Rn_VPR128.16B[80,8] s>> Imm_shr_imm8:1; + TMPQ1[88,8] = Rn_VPR128.16B[88,8] s>> Imm_shr_imm8:1; + TMPQ1[96,8] = Rn_VPR128.16B[96,8] s>> Imm_shr_imm8:1; + TMPQ1[104,8] = Rn_VPR128.16B[104,8] s>> Imm_shr_imm8:1; + TMPQ1[112,8] = Rn_VPR128.16B[112,8] s>> Imm_shr_imm8:1; + TMPQ1[120,8] = Rn_VPR128.16B[120,8] s>> Imm_shr_imm8:1; + # simd infix Rd_VPR128.16B = Rd_VPR128.16B + TMPQ1 on lane size 1 + Rd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] + TMPQ1[0,8]; + Rd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] + TMPQ1[8,8]; + Rd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] + TMPQ1[16,8]; + Rd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] + TMPQ1[24,8]; + Rd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] + TMPQ1[32,8]; + Rd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] + TMPQ1[40,8]; + Rd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] + TMPQ1[48,8]; + Rd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] + TMPQ1[56,8]; + Rd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] + TMPQ1[64,8]; + Rd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] + TMPQ1[72,8]; + Rd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] + TMPQ1[80,8]; + Rd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] + TMPQ1[88,8]; + Rd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] + TMPQ1[96,8]; + Rd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] + TMPQ1[104,8]; + Rd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] + TMPQ1[112,8]; + Rd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] + TMPQ1[120,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00 +# CONSTRUCT x4f403400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 zext:8 $s>>@8 &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@8 +# AUNIT --inst x4f403400/mask=xffc0fc00 --status fail --comment "nointround" + +:srsra Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x6 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + local tmp1:8 = zext(Imm_shr_imm64); + # simd infix TMPQ1 = Rn_VPR128.2D s>> tmp1 on lane size 8 + TMPQ1[0,64] = Rn_VPR128.2D[0,64] s>> tmp1; + TMPQ1[64,64] = Rn_VPR128.2D[64,64] s>> tmp1; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ1 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ1[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ1[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00 +# CONSTRUCT x0f203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:4 $s>>@4 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@4 +# AUNIT --inst x0f203400/mask=xffe0fc00 --status fail --comment "nointround" + +:srsra Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x6 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + # simd infix TMPD1 = Rn_VPR64.2S s>> Imm_shr_imm32:4 on lane size 4 + TMPD1[0,32] = Rn_VPR64.2S[0,32] s>> Imm_shr_imm32:4; + TMPD1[32,32] = Rn_VPR64.2S[32,32] s>> Imm_shr_imm32:4; + # simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4 + Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32]; + Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00 +# CONSTRUCT x0f103400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:2 $s>>@2 &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@2 +# AUNIT --inst x0f103400/mask=xfff0fc00 --status fail --comment "nointround" + +:srsra Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x6 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + # simd infix TMPD1 = Rn_VPR64.4H s>> Imm_shr_imm16:2 on lane size 2 + TMPD1[0,16] = Rn_VPR64.4H[0,16] s>> Imm_shr_imm16:2; + TMPD1[16,16] = Rn_VPR64.4H[16,16] s>> Imm_shr_imm16:2; + TMPD1[32,16] = Rn_VPR64.4H[32,16] s>> Imm_shr_imm16:2; + TMPD1[48,16] = Rn_VPR64.4H[48,16] s>> Imm_shr_imm16:2; + # simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2 + Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16]; + Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16]; + Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16]; + Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00 +# CONSTRUCT x4f203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:4 $s>>@4 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@4 +# AUNIT --inst x4f203400/mask=xffe0fc00 --status fail --comment "nointround" + +:srsra Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x6 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.4S s>> Imm_shr_imm32:4 on lane size 4 + TMPQ1[0,32] = Rn_VPR128.4S[0,32] s>> Imm_shr_imm32:4; + TMPQ1[32,32] = Rn_VPR128.4S[32,32] s>> Imm_shr_imm32:4; + TMPQ1[64,32] = Rn_VPR128.4S[64,32] s>> Imm_shr_imm32:4; + TMPQ1[96,32] = Rn_VPR128.4S[96,32] s>> Imm_shr_imm32:4; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00 +# CONSTRUCT x0f083400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:1 $s>>@1 &=$+@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@1 +# AUNIT --inst x0f083400/mask=xfff8fc00 --status fail --comment "nointround" + +:srsra Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x6 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + # simd infix TMPD1 = Rn_VPR64.8B s>> Imm_shr_imm8:1 on lane size 1 + TMPD1[0,8] = Rn_VPR64.8B[0,8] s>> Imm_shr_imm8:1; + TMPD1[8,8] = Rn_VPR64.8B[8,8] s>> Imm_shr_imm8:1; + TMPD1[16,8] = Rn_VPR64.8B[16,8] s>> Imm_shr_imm8:1; + TMPD1[24,8] = Rn_VPR64.8B[24,8] s>> Imm_shr_imm8:1; + TMPD1[32,8] = Rn_VPR64.8B[32,8] s>> Imm_shr_imm8:1; + TMPD1[40,8] = Rn_VPR64.8B[40,8] s>> Imm_shr_imm8:1; + TMPD1[48,8] = Rn_VPR64.8B[48,8] s>> Imm_shr_imm8:1; + TMPD1[56,8] = Rn_VPR64.8B[56,8] s>> Imm_shr_imm8:1; + # simd infix Rd_VPR64.8B = Rd_VPR64.8B + TMPD1 on lane size 1 + Rd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] + TMPD1[0,8]; + Rd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] + TMPD1[8,8]; + Rd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] + TMPD1[16,8]; + Rd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] + TMPD1[24,8]; + Rd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] + TMPD1[32,8]; + Rd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] + TMPD1[40,8]; + Rd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] + TMPD1[48,8]; + Rd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] + TMPD1[56,8]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00 +# CONSTRUCT x4f103400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:2 $s>>@2 &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@2 +# AUNIT --inst x4f103400/mask=xfff0fc00 --status fail --comment "nointround" + +:srsra Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x6 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.8H s>> Imm_shr_imm16:2 on lane size 2 + TMPQ1[0,16] = Rn_VPR128.8H[0,16] s>> Imm_shr_imm16:2; + TMPQ1[16,16] = Rn_VPR128.8H[16,16] s>> Imm_shr_imm16:2; + TMPQ1[32,16] = Rn_VPR128.8H[32,16] s>> Imm_shr_imm16:2; + TMPQ1[48,16] = Rn_VPR128.8H[48,16] s>> Imm_shr_imm16:2; + TMPQ1[64,16] = Rn_VPR128.8H[64,16] s>> Imm_shr_imm16:2; + TMPQ1[80,16] = Rn_VPR128.8H[80,16] s>> Imm_shr_imm16:2; + TMPQ1[96,16] = Rn_VPR128.8H[96,16] s>> Imm_shr_imm16:2; + TMPQ1[112,16] = Rn_VPR128.8H[112,16] s>> Imm_shr_imm16:2; + # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x5f003400/mask=xff80fc00 +# CONSTRUCT x5f403400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 zext:8 s>> &=+ +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3 +# AUNIT --inst x5f403400/mask=xffc0fc00 --status fail --comment "nointround" + +:srsra Rd_FPR64, Rn_FPR64, Imm_shr_imm64 +is b_2331=0b010111110 & b_22=1 & b_1015=0b001101 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd +{ + local tmp1:8 = zext(Imm_shr_imm64); + local tmp2:8 = Rn_FPR64 s>> tmp1; + Rd_FPR64 = Rd_FPR64 + tmp2; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.315 SSHL page C7-2733 line 159467 MATCH x5e204400/mask=xff20fc00 +# CONSTRUCT x5ee04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2 +# AUNIT --inst x5ee04400/mask=xffe0fc00 --status nopcodeop + +:sshl Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x8 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_sshl(Rn_FPR64, Rm_FPR64); +} + +# C7.2.315 SSHL page C7-2733 line 159467 MATCH x0e204400/mask=xbf20fc00 +# CONSTRUCT x4e204400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@1 +# AUNIT --inst x4e204400/mask=xffe0fc00 --status nopcodeop + +:sshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x8 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_sshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.315 SSHL page C7-2733 line 159467 MATCH x0e204400/mask=xbf20fc00 +# CONSTRUCT x4ee04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@8 +# AUNIT --inst x4ee04400/mask=xffe0fc00 --status nopcodeop + +:sshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x8 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_sshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.315 SSHL page C7-2733 line 159467 MATCH x0e204400/mask=xbf20fc00 +# CONSTRUCT x0ea04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@4 +# AUNIT --inst x0ea04400/mask=xffe0fc00 --status nopcodeop + +:sshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x8 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_sshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.315 SSHL page C7-2733 line 159467 MATCH x0e204400/mask=xbf20fc00 +# CONSTRUCT x0e604400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@2 +# AUNIT --inst x0e604400/mask=xffe0fc00 --status nopcodeop + +:sshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x8 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_sshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.315 SSHL page C7-2733 line 159467 MATCH x0e204400/mask=xbf20fc00 +# CONSTRUCT x4ea04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@4 +# AUNIT --inst x4ea04400/mask=xffe0fc00 --status nopcodeop + +:sshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x8 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_sshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.315 SSHL page C7-2733 line 159467 MATCH x0e204400/mask=xbf20fc00 +# CONSTRUCT x0e204400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@1 +# AUNIT --inst x0e204400/mask=xffe0fc00 --status nopcodeop + +:sshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x8 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_sshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.315 SSHL page C7-2733 line 159467 MATCH x0e204400/mask=xbf20fc00 +# CONSTRUCT x4e604400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@2 +# AUNIT --inst x4e604400/mask=xffe0fc00 --status nopcodeop + +:sshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x8 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_sshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00 +# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00 +# CONSTRUCT x4f08a400/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3 =var:2 =$<<@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshll2/2@1 +# AUNIT --inst x4f08a400/mask=xfff8fc00 --status pass --comment "ext" + +:sshll2 Rd_VPR128.8H, Rn_VPR128.16B, Imm_uimm3 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0x14 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.8H & Zd +{ + TMPD1 = Rn_VPR128.16B[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2) + TMPQ2[0,16] = sext(TMPD1[0,8]); + TMPQ2[16,16] = sext(TMPD1[8,8]); + TMPQ2[32,16] = sext(TMPD1[16,8]); + TMPQ2[48,16] = sext(TMPD1[24,8]); + TMPQ2[64,16] = sext(TMPD1[32,8]); + TMPQ2[80,16] = sext(TMPD1[40,8]); + TMPQ2[96,16] = sext(TMPD1[48,8]); + TMPQ2[112,16] = sext(TMPD1[56,8]); + local tmp3:2 = Imm_uimm3; + # simd infix Rd_VPR128.8H = TMPQ2 << tmp3 on lane size 2 + Rd_VPR128.8H[0,16] = TMPQ2[0,16] << tmp3; + Rd_VPR128.8H[16,16] = TMPQ2[16,16] << tmp3; + Rd_VPR128.8H[32,16] = TMPQ2[32,16] << tmp3; + Rd_VPR128.8H[48,16] = TMPQ2[48,16] << tmp3; + Rd_VPR128.8H[64,16] = TMPQ2[64,16] << tmp3; + Rd_VPR128.8H[80,16] = TMPQ2[80,16] << tmp3; + Rd_VPR128.8H[96,16] = TMPQ2[96,16] << tmp3; + Rd_VPR128.8H[112,16] = TMPQ2[112,16] << tmp3; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00 +# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00 +# CONSTRUCT x0f20a400/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@4:16 ARG3 =var:8 =$<<@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshll/2@4 +# AUNIT --inst x0f20a400/mask=xffe0fc00 --status pass --comment "ext" + +:sshll Rd_VPR128.2D, Rn_VPR64.2S, Imm_uimm5 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0x14 & b_1010=1 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]); + local tmp2:8 = Imm_uimm5; + # simd infix Rd_VPR128.2D = TMPQ1 << tmp2 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ1[0,64] << tmp2; + Rd_VPR128.2D[64,64] = TMPQ1[64,64] << tmp2; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00 +# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00 +# CONSTRUCT x0f10a400/mask=xfff0fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@2:16 ARG3 =var:4 =$<<@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshll/2@2 +# AUNIT --inst x0f10a400/mask=xfff0fc00 --status pass --comment "ext" + +:sshll Rd_VPR128.4S, Rn_VPR64.4H, Imm_uimm4 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0x14 & b_1010=1 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]); + local tmp2:4 = Imm_uimm4; + # simd infix Rd_VPR128.4S = TMPQ1 << tmp2 on lane size 4 + Rd_VPR128.4S[0,32] = TMPQ1[0,32] << tmp2; + Rd_VPR128.4S[32,32] = TMPQ1[32,32] << tmp2; + Rd_VPR128.4S[64,32] = TMPQ1[64,32] << tmp2; + Rd_VPR128.4S[96,32] = TMPQ1[96,32] << tmp2; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00 +# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00 +# CONSTRUCT x4f20a400/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 =var:8 =$<<@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshll2/2@4 +# AUNIT --inst x4f20a400/mask=xffe0fc00 --status pass --comment "ext" + +:sshll2 Rd_VPR128.2D, Rn_VPR128.4S, Imm_uimm5 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0x14 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = sext(TMPD1[0,32]); + TMPQ2[64,64] = sext(TMPD1[32,32]); + local tmp3:8 = Imm_uimm5; + # simd infix Rd_VPR128.2D = TMPQ2 << tmp3 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ2[0,64] << tmp3; + Rd_VPR128.2D[64,64] = TMPQ2[64,64] << tmp3; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00 +# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00 +# CONSTRUCT x0f08a400/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@1:16 ARG3 =var:2 =$<<@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshll/2@1 +# AUNIT --inst x0f08a400/mask=xfff8fc00 --status pass --comment "ext" + +:sshll Rd_VPR128.8H, Rn_VPR64.8B, Imm_uimm3 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0x14 & b_1010=1 & Rn_VPR64.8B & Rd_VPR128.8H & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2) + TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]); + TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]); + TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]); + TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]); + TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]); + TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]); + TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]); + TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]); + local tmp2:2 = Imm_uimm3; + # simd infix Rd_VPR128.8H = TMPQ1 << tmp2 on lane size 2 + Rd_VPR128.8H[0,16] = TMPQ1[0,16] << tmp2; + Rd_VPR128.8H[16,16] = TMPQ1[16,16] << tmp2; + Rd_VPR128.8H[32,16] = TMPQ1[32,16] << tmp2; + Rd_VPR128.8H[48,16] = TMPQ1[48,16] << tmp2; + Rd_VPR128.8H[64,16] = TMPQ1[64,16] << tmp2; + Rd_VPR128.8H[80,16] = TMPQ1[80,16] << tmp2; + Rd_VPR128.8H[96,16] = TMPQ1[96,16] << tmp2; + Rd_VPR128.8H[112,16] = TMPQ1[112,16] << tmp2; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00 +# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00 +# CONSTRUCT x4f10a400/mask=xfff0fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 =var:4 =$<<@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshll2/2@2 +# AUNIT --inst x4f10a400/mask=xfff0fc00 --status pass --comment "ext" + +:sshll2 Rd_VPR128.4S, Rn_VPR128.8H, Imm_uimm4 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0x14 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = sext(TMPD1[0,16]); + TMPQ2[32,32] = sext(TMPD1[16,16]); + TMPQ2[64,32] = sext(TMPD1[32,16]); + TMPQ2[96,32] = sext(TMPD1[48,16]); + local tmp3:4 = Imm_uimm4; + # simd infix Rd_VPR128.4S = TMPQ2 << tmp3 on lane size 4 + Rd_VPR128.4S[0,32] = TMPQ2[0,32] << tmp3; + Rd_VPR128.4S[32,32] = TMPQ2[32,32] << tmp3; + Rd_VPR128.4S[64,32] = TMPQ2[64,32] << tmp3; + Rd_VPR128.4S[96,32] = TMPQ2[96,32] << tmp3; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.317 SSHR page C7-2738 line 159757 MATCH x5f000400/mask=xff80fc00 +# CONSTRUCT x5f400400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2 +# AUNIT --inst x5f400400/mask=xffc0fc00 --status nopcodeop + +:sshr Rd_FPR64, Rn_FPR64, Imm_shr_imm64 +is b_3031=1 & u=0 & b_2428=0x1f & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x0 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_sshr(Rn_FPR64, Imm_shr_imm64:1); +} + +# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00 +# CONSTRUCT x4f080400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:1 =$s>>@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@1 +# AUNIT --inst x4f080400/mask=xfff8fc00 --status pass + +:sshr Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x0 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + # simd infix Rd_VPR128.16B = Rn_VPR128.16B s>> Imm_shr_imm8:1 on lane size 1 + Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] s>> Imm_shr_imm8:1; + Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] s>> Imm_shr_imm8:1; + Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] s>> Imm_shr_imm8:1; + Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] s>> Imm_shr_imm8:1; + Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] s>> Imm_shr_imm8:1; + Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] s>> Imm_shr_imm8:1; + Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] s>> Imm_shr_imm8:1; + Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] s>> Imm_shr_imm8:1; + Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] s>> Imm_shr_imm8:1; + Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] s>> Imm_shr_imm8:1; + Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] s>> Imm_shr_imm8:1; + Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] s>> Imm_shr_imm8:1; + Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] s>> Imm_shr_imm8:1; + Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] s>> Imm_shr_imm8:1; + Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] s>> Imm_shr_imm8:1; + Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] s>> Imm_shr_imm8:1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00 +# CONSTRUCT x4f400400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 zext:8 =$s>>@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@8 +# AUNIT --inst x4f400400/mask=xffc0fc00 --status pass + +:sshr Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x0 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + local tmp1:8 = zext(Imm_shr_imm64); + # simd infix Rd_VPR128.2D = Rn_VPR128.2D s>> tmp1 on lane size 8 + Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] s>> tmp1; + Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] s>> tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00 +# CONSTRUCT x0f200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =var:4 =$s>>@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@4 +# AUNIT --inst x0f200400/mask=xffe0fc00 --status pass + +:sshr Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x0 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + local tmp1:4 = Imm_shr_imm32; + # simd infix Rd_VPR64.2S = Rn_VPR64.2S s>> tmp1 on lane size 4 + Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] s>> tmp1; + Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] s>> tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00 +# CONSTRUCT x0f100400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:2 =$s>>@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@2 +# AUNIT --inst x0f100400/mask=xfff0fc00 --status pass + +:sshr Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x0 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + # simd infix Rd_VPR64.4H = Rn_VPR64.4H s>> Imm_shr_imm16:2 on lane size 2 + Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] s>> Imm_shr_imm16:2; + Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] s>> Imm_shr_imm16:2; + Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] s>> Imm_shr_imm16:2; + Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] s>> Imm_shr_imm16:2; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00 +# CONSTRUCT x4f200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =var:4 =$s>>@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@4 +# AUNIT --inst x4f200400/mask=xffe0fc00 --status pass + +:sshr Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x0 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + local tmp1:4 = Imm_shr_imm32; + # simd infix Rd_VPR128.4S = Rn_VPR128.4S s>> tmp1 on lane size 4 + Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] s>> tmp1; + Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] s>> tmp1; + Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] s>> tmp1; + Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] s>> tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00 +# CONSTRUCT x0f080400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:1 =$s>>@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@1 +# AUNIT --inst x0f080400/mask=xfff8fc00 --status pass + +:sshr Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x0 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + # simd infix Rd_VPR64.8B = Rn_VPR64.8B s>> Imm_shr_imm8:1 on lane size 1 + Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] s>> Imm_shr_imm8:1; + Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] s>> Imm_shr_imm8:1; + Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] s>> Imm_shr_imm8:1; + Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] s>> Imm_shr_imm8:1; + Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] s>> Imm_shr_imm8:1; + Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] s>> Imm_shr_imm8:1; + Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] s>> Imm_shr_imm8:1; + Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] s>> Imm_shr_imm8:1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00 +# CONSTRUCT x4f100400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:2 =$s>>@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@2 +# AUNIT --inst x4f100400/mask=xfff0fc00 --status pass + +:sshr Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x0 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + # simd infix Rd_VPR128.8H = Rn_VPR128.8H s>> Imm_shr_imm16:2 on lane size 2 + Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] s>> Imm_shr_imm16:2; + Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] s>> Imm_shr_imm16:2; + Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] s>> Imm_shr_imm16:2; + Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] s>> Imm_shr_imm16:2; + Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] s>> Imm_shr_imm16:2; + Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] s>> Imm_shr_imm16:2; + Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] s>> Imm_shr_imm16:2; + Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] s>> Imm_shr_imm16:2; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00 +# CONSTRUCT x4f081400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:1 $s>>@1 &=$+@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@1 +# AUNIT --inst x4f081400/mask=xfff8fc00 --status pass + +:ssra Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x2 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.16B s>> Imm_shr_imm8:1 on lane size 1 + TMPQ1[0,8] = Rn_VPR128.16B[0,8] s>> Imm_shr_imm8:1; + TMPQ1[8,8] = Rn_VPR128.16B[8,8] s>> Imm_shr_imm8:1; + TMPQ1[16,8] = Rn_VPR128.16B[16,8] s>> Imm_shr_imm8:1; + TMPQ1[24,8] = Rn_VPR128.16B[24,8] s>> Imm_shr_imm8:1; + TMPQ1[32,8] = Rn_VPR128.16B[32,8] s>> Imm_shr_imm8:1; + TMPQ1[40,8] = Rn_VPR128.16B[40,8] s>> Imm_shr_imm8:1; + TMPQ1[48,8] = Rn_VPR128.16B[48,8] s>> Imm_shr_imm8:1; + TMPQ1[56,8] = Rn_VPR128.16B[56,8] s>> Imm_shr_imm8:1; + TMPQ1[64,8] = Rn_VPR128.16B[64,8] s>> Imm_shr_imm8:1; + TMPQ1[72,8] = Rn_VPR128.16B[72,8] s>> Imm_shr_imm8:1; + TMPQ1[80,8] = Rn_VPR128.16B[80,8] s>> Imm_shr_imm8:1; + TMPQ1[88,8] = Rn_VPR128.16B[88,8] s>> Imm_shr_imm8:1; + TMPQ1[96,8] = Rn_VPR128.16B[96,8] s>> Imm_shr_imm8:1; + TMPQ1[104,8] = Rn_VPR128.16B[104,8] s>> Imm_shr_imm8:1; + TMPQ1[112,8] = Rn_VPR128.16B[112,8] s>> Imm_shr_imm8:1; + TMPQ1[120,8] = Rn_VPR128.16B[120,8] s>> Imm_shr_imm8:1; + # simd infix Rd_VPR128.16B = Rd_VPR128.16B + TMPQ1 on lane size 1 + Rd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] + TMPQ1[0,8]; + Rd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] + TMPQ1[8,8]; + Rd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] + TMPQ1[16,8]; + Rd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] + TMPQ1[24,8]; + Rd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] + TMPQ1[32,8]; + Rd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] + TMPQ1[40,8]; + Rd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] + TMPQ1[48,8]; + Rd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] + TMPQ1[56,8]; + Rd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] + TMPQ1[64,8]; + Rd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] + TMPQ1[72,8]; + Rd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] + TMPQ1[80,8]; + Rd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] + TMPQ1[88,8]; + Rd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] + TMPQ1[96,8]; + Rd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] + TMPQ1[104,8]; + Rd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] + TMPQ1[112,8]; + Rd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] + TMPQ1[120,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00 +# CONSTRUCT x4f401400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 zext:8 $s>>@8 &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@8 +# AUNIT --inst x4f401400/mask=xffc0fc00 --status pass + +:ssra Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x2 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + local tmp1:8 = zext(Imm_shr_imm64); + # simd infix TMPQ1 = Rn_VPR128.2D s>> tmp1 on lane size 8 + TMPQ1[0,64] = Rn_VPR128.2D[0,64] s>> tmp1; + TMPQ1[64,64] = Rn_VPR128.2D[64,64] s>> tmp1; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ1 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ1[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ1[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00 +# CONSTRUCT x0f201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =var:4 $s>>@4 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@4 +# AUNIT --inst x0f201400/mask=xffe0fc00 --status pass + +:ssra Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x2 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + local tmp1:4 = Imm_shr_imm32; + # simd infix TMPD1 = Rn_VPR64.2S s>> tmp1 on lane size 4 + TMPD1[0,32] = Rn_VPR64.2S[0,32] s>> tmp1; + TMPD1[32,32] = Rn_VPR64.2S[32,32] s>> tmp1; + # simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4 + Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32]; + Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00 +# CONSTRUCT x0f101400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:2 $s>>@2 &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@2 +# AUNIT --inst x0f101400/mask=xfff0fc00 --status pass + +:ssra Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x2 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + # simd infix TMPD1 = Rn_VPR64.4H s>> Imm_shr_imm16:2 on lane size 2 + TMPD1[0,16] = Rn_VPR64.4H[0,16] s>> Imm_shr_imm16:2; + TMPD1[16,16] = Rn_VPR64.4H[16,16] s>> Imm_shr_imm16:2; + TMPD1[32,16] = Rn_VPR64.4H[32,16] s>> Imm_shr_imm16:2; + TMPD1[48,16] = Rn_VPR64.4H[48,16] s>> Imm_shr_imm16:2; + # simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2 + Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16]; + Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16]; + Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16]; + Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00 +# CONSTRUCT x4f201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =var:4 $s>>@4 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@4 +# AUNIT --inst x4f201400/mask=xffe0fc00 --status pass + +:ssra Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x2 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + local tmp1:4 = Imm_shr_imm32; + # simd infix TMPQ1 = Rn_VPR128.4S s>> tmp1 on lane size 4 + TMPQ1[0,32] = Rn_VPR128.4S[0,32] s>> tmp1; + TMPQ1[32,32] = Rn_VPR128.4S[32,32] s>> tmp1; + TMPQ1[64,32] = Rn_VPR128.4S[64,32] s>> tmp1; + TMPQ1[96,32] = Rn_VPR128.4S[96,32] s>> tmp1; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00 +# CONSTRUCT x0f081400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:1 $s>>@1 &=$+@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@1 +# AUNIT --inst x0f081400/mask=xfff8fc00 --status pass + +:ssra Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8 +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x2 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + # simd infix TMPD1 = Rn_VPR64.8B s>> Imm_shr_imm8:1 on lane size 1 + TMPD1[0,8] = Rn_VPR64.8B[0,8] s>> Imm_shr_imm8:1; + TMPD1[8,8] = Rn_VPR64.8B[8,8] s>> Imm_shr_imm8:1; + TMPD1[16,8] = Rn_VPR64.8B[16,8] s>> Imm_shr_imm8:1; + TMPD1[24,8] = Rn_VPR64.8B[24,8] s>> Imm_shr_imm8:1; + TMPD1[32,8] = Rn_VPR64.8B[32,8] s>> Imm_shr_imm8:1; + TMPD1[40,8] = Rn_VPR64.8B[40,8] s>> Imm_shr_imm8:1; + TMPD1[48,8] = Rn_VPR64.8B[48,8] s>> Imm_shr_imm8:1; + TMPD1[56,8] = Rn_VPR64.8B[56,8] s>> Imm_shr_imm8:1; + # simd infix Rd_VPR64.8B = Rd_VPR64.8B + TMPD1 on lane size 1 + Rd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] + TMPD1[0,8]; + Rd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] + TMPD1[8,8]; + Rd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] + TMPD1[16,8]; + Rd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] + TMPD1[24,8]; + Rd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] + TMPD1[32,8]; + Rd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] + TMPD1[40,8]; + Rd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] + TMPD1[48,8]; + Rd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] + TMPD1[56,8]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00 +# CONSTRUCT x4f101400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:2 $s>>@2 &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@2 +# AUNIT --inst x4f101400/mask=xfff0fc00 --status pass + +:ssra Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16 +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x2 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.8H s>> Imm_shr_imm16:2 on lane size 2 + TMPQ1[0,16] = Rn_VPR128.8H[0,16] s>> Imm_shr_imm16:2; + TMPQ1[16,16] = Rn_VPR128.8H[16,16] s>> Imm_shr_imm16:2; + TMPQ1[32,16] = Rn_VPR128.8H[32,16] s>> Imm_shr_imm16:2; + TMPQ1[48,16] = Rn_VPR128.8H[48,16] s>> Imm_shr_imm16:2; + TMPQ1[64,16] = Rn_VPR128.8H[64,16] s>> Imm_shr_imm16:2; + TMPQ1[80,16] = Rn_VPR128.8H[80,16] s>> Imm_shr_imm16:2; + TMPQ1[96,16] = Rn_VPR128.8H[96,16] s>> Imm_shr_imm16:2; + TMPQ1[112,16] = Rn_VPR128.8H[112,16] s>> Imm_shr_imm16:2; + # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.318 SSRA page C7-2741 line 159921 MATCH x5f001400/mask=xff80fc00 +# CONSTRUCT x5f401400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 zext:8 s>> &=+ +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3 +# AUNIT --inst x5f401400/mask=xffc0fc00 --status pass + +:ssra Rd_FPR64, Rn_FPR64, Imm_shr_imm64 +is b_2331=0b010111110 & b_22=1 & b_1015=0b000101 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd +{ + local tmp1:8 = zext(Imm_shr_imm64); + local tmp2:8 = Rn_FPR64 s>> tmp1; + Rd_FPR64 = Rd_FPR64 + tmp2; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.319 SSUBL, SSUBL2 page C7-2744 line 160085 MATCH x0e202000/mask=xbf20fc00 +# CONSTRUCT x4ea02000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 =$-@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubl2/2@4 +# AUNIT --inst x4ea02000/mask=xffe0fc00 --status pass --comment "ext" + +:ssubl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x2 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = sext(TMPD1[0,32]); + TMPQ2[64,64] = sext(TMPD1[32,32]); + TMPD3 = Rm_VPR128.4S[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8) + TMPQ4[0,64] = sext(TMPD3[0,32]); + TMPQ4[64,64] = sext(TMPD3[32,32]); + # simd infix Rd_VPR128.2D = TMPQ2 - TMPQ4 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ2[0,64] - TMPQ4[0,64]; + Rd_VPR128.2D[64,64] = TMPQ2[64,64] - TMPQ4[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.319 SSUBL, SSUBL2 page C7-2744 line 160085 MATCH x0e202000/mask=xbf20fc00 +# CONSTRUCT x4e602000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 =$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubl2/2@2 +# AUNIT --inst x4e602000/mask=xffe0fc00 --status pass --comment "ext" + +:ssubl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x2 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = sext(TMPD1[0,16]); + TMPQ2[32,32] = sext(TMPD1[16,16]); + TMPQ2[64,32] = sext(TMPD1[32,16]); + TMPQ2[96,32] = sext(TMPD1[48,16]); + TMPD3 = Rm_VPR128.8H[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4) + TMPQ4[0,32] = sext(TMPD3[0,16]); + TMPQ4[32,32] = sext(TMPD3[16,16]); + TMPQ4[64,32] = sext(TMPD3[32,16]); + TMPQ4[96,32] = sext(TMPD3[48,16]); + # simd infix Rd_VPR128.4S = TMPQ2 - TMPQ4 on lane size 4 + Rd_VPR128.4S[0,32] = TMPQ2[0,32] - TMPQ4[0,32]; + Rd_VPR128.4S[32,32] = TMPQ2[32,32] - TMPQ4[32,32]; + Rd_VPR128.4S[64,32] = TMPQ2[64,32] - TMPQ4[64,32]; + Rd_VPR128.4S[96,32] = TMPQ2[96,32] - TMPQ4[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.319 SSUBL, SSUBL2 page C7-2744 line 160085 MATCH x0e202000/mask=xbf20fc00 +# CONSTRUCT x4e202000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 =$-@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubl2/2@1 +# AUNIT --inst x4e202000/mask=xffe0fc00 --status pass --comment "ext" + +:ssubl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x2 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd +{ + TMPD1 = Rn_VPR128.16B[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2) + TMPQ2[0,16] = sext(TMPD1[0,8]); + TMPQ2[16,16] = sext(TMPD1[8,8]); + TMPQ2[32,16] = sext(TMPD1[16,8]); + TMPQ2[48,16] = sext(TMPD1[24,8]); + TMPQ2[64,16] = sext(TMPD1[32,8]); + TMPQ2[80,16] = sext(TMPD1[40,8]); + TMPQ2[96,16] = sext(TMPD1[48,8]); + TMPQ2[112,16] = sext(TMPD1[56,8]); + TMPD3 = Rm_VPR128.16B[64,64]; + # simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2) + TMPQ4[0,16] = sext(TMPD3[0,8]); + TMPQ4[16,16] = sext(TMPD3[8,8]); + TMPQ4[32,16] = sext(TMPD3[16,8]); + TMPQ4[48,16] = sext(TMPD3[24,8]); + TMPQ4[64,16] = sext(TMPD3[32,8]); + TMPQ4[80,16] = sext(TMPD3[40,8]); + TMPQ4[96,16] = sext(TMPD3[48,8]); + TMPQ4[112,16] = sext(TMPD3[56,8]); + # simd infix Rd_VPR128.8H = TMPQ2 - TMPQ4 on lane size 2 + Rd_VPR128.8H[0,16] = TMPQ2[0,16] - TMPQ4[0,16]; + Rd_VPR128.8H[16,16] = TMPQ2[16,16] - TMPQ4[16,16]; + Rd_VPR128.8H[32,16] = TMPQ2[32,16] - TMPQ4[32,16]; + Rd_VPR128.8H[48,16] = TMPQ2[48,16] - TMPQ4[48,16]; + Rd_VPR128.8H[64,16] = TMPQ2[64,16] - TMPQ4[64,16]; + Rd_VPR128.8H[80,16] = TMPQ2[80,16] - TMPQ4[80,16]; + Rd_VPR128.8H[96,16] = TMPQ2[96,16] - TMPQ4[96,16]; + Rd_VPR128.8H[112,16] = TMPQ2[112,16] - TMPQ4[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.319 SSUBL, SSUBL2 page C7-2744 line 160085 MATCH x0e202000/mask=xbf20fc00 +# CONSTRUCT x0ea02000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 =$-@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubl/2@4 +# AUNIT --inst x0ea02000/mask=xffe0fc00 --status pass --comment "ext" + +:ssubl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x2 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]); + # simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8) + TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]); + TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]); + # simd infix Rd_VPR128.2D = TMPQ1 - TMPQ2 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ1[0,64] - TMPQ2[0,64]; + Rd_VPR128.2D[64,64] = TMPQ1[64,64] - TMPQ2[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.319 SSUBL, SSUBL2 page C7-2744 line 160085 MATCH x0e202000/mask=xbf20fc00 +# CONSTRUCT x0e602000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 =$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubl/2@2 +# AUNIT --inst x0e602000/mask=xffe0fc00 --status pass --comment "ext" + +:ssubl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x2 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]); + # simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4) + TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]); + TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]); + TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]); + TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]); + # simd infix Rd_VPR128.4S = TMPQ1 - TMPQ2 on lane size 4 + Rd_VPR128.4S[0,32] = TMPQ1[0,32] - TMPQ2[0,32]; + Rd_VPR128.4S[32,32] = TMPQ1[32,32] - TMPQ2[32,32]; + Rd_VPR128.4S[64,32] = TMPQ1[64,32] - TMPQ2[64,32]; + Rd_VPR128.4S[96,32] = TMPQ1[96,32] - TMPQ2[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.319 SSUBL, SSUBL2 page C7-2744 line 160085 MATCH x0e202000/mask=xbf20fc00 +# CONSTRUCT x0e202000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 =$-@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubl/2@1 +# AUNIT --inst x0e202000/mask=xffe0fc00 --status pass --comment "ext" + +:ssubl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x2 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd +{ + # simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2) + TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]); + TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]); + TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]); + TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]); + TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]); + TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]); + TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]); + TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]); + # simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2) + TMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]); + TMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]); + TMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]); + TMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]); + TMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]); + TMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]); + TMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]); + TMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]); + # simd infix Rd_VPR128.8H = TMPQ1 - TMPQ2 on lane size 2 + Rd_VPR128.8H[0,16] = TMPQ1[0,16] - TMPQ2[0,16]; + Rd_VPR128.8H[16,16] = TMPQ1[16,16] - TMPQ2[16,16]; + Rd_VPR128.8H[32,16] = TMPQ1[32,16] - TMPQ2[32,16]; + Rd_VPR128.8H[48,16] = TMPQ1[48,16] - TMPQ2[48,16]; + Rd_VPR128.8H[64,16] = TMPQ1[64,16] - TMPQ2[64,16]; + Rd_VPR128.8H[80,16] = TMPQ1[80,16] - TMPQ2[80,16]; + Rd_VPR128.8H[96,16] = TMPQ1[96,16] - TMPQ2[96,16]; + Rd_VPR128.8H[112,16] = TMPQ1[112,16] - TMPQ2[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.320 SSUBW, SSUBW2 page C7-2746 line 160208 MATCH x0e203000/mask=xbf20fc00 +# CONSTRUCT x4ea03000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3[1]:8 $sext@4:16 =$-@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubw2/2@4 +# AUNIT --inst x4ea03000/mask=xffe0fc00 --status pass --comment "ext" + +:ssubw2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x3 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Rm_VPR128 & Zd +{ + TMPD1 = Rm_VPR128.4S[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = sext(TMPD1[0,32]); + TMPQ2[64,64] = sext(TMPD1[32,32]); + # simd infix Rd_VPR128.2D = Rn_VPR128.2D - TMPQ2 on lane size 8 + Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] - TMPQ2[0,64]; + Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] - TMPQ2[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.320 SSUBW, SSUBW2 page C7-2746 line 160208 MATCH x0e203000/mask=xbf20fc00 +# CONSTRUCT x4e603000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3[1]:8 $sext@2:16 =$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubw2/2@2 +# AUNIT --inst x4e603000/mask=xffe0fc00 --status pass --comment "ext" + +:ssubw2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x3 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + TMPD1 = Rm_VPR128.8H[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = sext(TMPD1[0,16]); + TMPQ2[32,32] = sext(TMPD1[16,16]); + TMPQ2[64,32] = sext(TMPD1[32,16]); + TMPQ2[96,32] = sext(TMPD1[48,16]); + # simd infix Rd_VPR128.4S = Rn_VPR128.4S - TMPQ2 on lane size 4 + Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] - TMPQ2[0,32]; + Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] - TMPQ2[32,32]; + Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] - TMPQ2[64,32]; + Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] - TMPQ2[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.320 SSUBW, SSUBW2 page C7-2746 line 160208 MATCH x0e203000/mask=xbf20fc00 +# CONSTRUCT x4e203000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3[1]:8 $sext@1:16 =$-@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubw2/2@1 +# AUNIT --inst x4e203000/mask=xffe0fc00 --status pass --comment "ext" + +:ssubw2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x3 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + TMPD1 = Rm_VPR128.16B[64,64]; + # simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2) + TMPQ2[0,16] = sext(TMPD1[0,8]); + TMPQ2[16,16] = sext(TMPD1[8,8]); + TMPQ2[32,16] = sext(TMPD1[16,8]); + TMPQ2[48,16] = sext(TMPD1[24,8]); + TMPQ2[64,16] = sext(TMPD1[32,8]); + TMPQ2[80,16] = sext(TMPD1[40,8]); + TMPQ2[96,16] = sext(TMPD1[48,8]); + TMPQ2[112,16] = sext(TMPD1[56,8]); + # simd infix Rd_VPR128.8H = Rn_VPR128.8H - TMPQ2 on lane size 2 + Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] - TMPQ2[0,16]; + Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] - TMPQ2[16,16]; + Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] - TMPQ2[32,16]; + Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] - TMPQ2[48,16]; + Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] - TMPQ2[64,16]; + Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] - TMPQ2[80,16]; + Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] - TMPQ2[96,16]; + Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] - TMPQ2[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.320 SSUBW, SSUBW2 page C7-2746 line 160208 MATCH x0e203000/mask=xbf20fc00 +# CONSTRUCT x0ea03000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $sext@4:16 =$-@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubw/2@4 +# AUNIT --inst x0ea03000/mask=xffe0fc00 --status pass --comment "ext" + +:ssubw Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x3 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = sext(Rm_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = sext(Rm_VPR64.2S[0,32]); + TMPQ1[64,64] = sext(Rm_VPR64.2S[32,32]); + # simd infix Rd_VPR128.2D = Rn_VPR128.2D - TMPQ1 on lane size 8 + Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] - TMPQ1[0,64]; + Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] - TMPQ1[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.320 SSUBW, SSUBW2 page C7-2746 line 160208 MATCH x0e203000/mask=xbf20fc00 +# CONSTRUCT x0e603000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $sext@2:16 =$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubw/2@2 +# AUNIT --inst x0e603000/mask=xffe0fc00 --status pass --comment "ext" + +:ssubw Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x3 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = sext(Rm_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = sext(Rm_VPR64.4H[0,16]); + TMPQ1[32,32] = sext(Rm_VPR64.4H[16,16]); + TMPQ1[64,32] = sext(Rm_VPR64.4H[32,16]); + TMPQ1[96,32] = sext(Rm_VPR64.4H[48,16]); + # simd infix Rd_VPR128.4S = Rn_VPR128.4S - TMPQ1 on lane size 4 + Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] - TMPQ1[0,32]; + Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] - TMPQ1[32,32]; + Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] - TMPQ1[64,32]; + Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] - TMPQ1[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.320 SSUBW, SSUBW2 page C7-2746 line 160208 MATCH x0e203000/mask=xbf20fc00 +# CONSTRUCT x0e203000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $sext@1:16 =$-@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubw/2@1 +# AUNIT --inst x0e203000/mask=xffe0fc00 --status pass --comment "ext" + +:ssubw Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x3 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + # simd resize TMPQ1 = sext(Rm_VPR64.8B) (lane size 1 to 2) + TMPQ1[0,16] = sext(Rm_VPR64.8B[0,8]); + TMPQ1[16,16] = sext(Rm_VPR64.8B[8,8]); + TMPQ1[32,16] = sext(Rm_VPR64.8B[16,8]); + TMPQ1[48,16] = sext(Rm_VPR64.8B[24,8]); + TMPQ1[64,16] = sext(Rm_VPR64.8B[32,8]); + TMPQ1[80,16] = sext(Rm_VPR64.8B[40,8]); + TMPQ1[96,16] = sext(Rm_VPR64.8B[48,8]); + TMPQ1[112,16] = sext(Rm_VPR64.8B[56,8]); + # simd infix Rd_VPR128.8H = Rn_VPR128.8H - TMPQ1 on lane size 2 + Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] - TMPQ1[0,16]; + Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] - TMPQ1[16,16]; + Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] - TMPQ1[32,16]; + Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] - TMPQ1[48,16]; + Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] - TMPQ1[64,16]; + Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] - TMPQ1[80,16]; + Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] - TMPQ1[96,16]; + Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] - TMPQ1[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.329 STNP (SIMD&FP) page C7-2777 line 162166 MATCH x2c000000/mask=x3fc00000 +# CONSTRUCT x2c000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG3 =store pop ARG2 ARG3 4 +:8 =store pop +# SMACRO(pseudo) null ARG1 ARG3 =NEON_stnp1/2 null ARG2 ARG3 =NEON_stnp2/2 +# AUNIT --inst x2c000000/mask=xffc00000 --status nomem + +:stnp Rt_FPR32, Rt2_FPR32, addrPairIndexed +is b_3031=0b00 & b_2229=0b10110000 & Rt2_FPR32 & addrPairIndexed & Rt_FPR32 +{ + * addrPairIndexed = Rt_FPR32; + local tmp1:8 = addrPairIndexed + 4; + * tmp1 = Rt2_FPR32; +} + +# C7.2.329 STNP (SIMD&FP) page C7-2777 line 162166 MATCH x2c000000/mask=x3fc00000 +# CONSTRUCT x6c000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG3 =store pop ARG2 ARG3 8 +:8 =store pop +# SMACRO(pseudo) null ARG1 ARG3 =NEON_stnp1/2 null ARG2 ARG3 =NEON_stnp2/2 +# AUNIT --inst x6c000000/mask=xffc00000 --status nomem + +:stnp Rt_FPR64, Rt2_FPR64, addrPairIndexed +is b_3031=0b01 & b_2229=0b10110000 & Rt2_FPR64 & addrPairIndexed & Rt_FPR64 +{ + * addrPairIndexed = Rt_FPR64; + local tmp1:8 = addrPairIndexed + 8; + * tmp1 = Rt2_FPR64; +} + +# C7.2.329 STNP (SIMD&FP) page C7-2777 line 162166 MATCH x2c000000/mask=x3fc00000 +# CONSTRUCT xac000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG3 =store pop ARG2 ARG3 16 +:8 =store pop +# SMACRO(pseudo) null ARG1 ARG3 =NEON_stnp1/2 null ARG2 ARG3 =NEON_stnp2/2 +# AUNIT --inst xac000000/mask=xffc00000 --status nomem + +:stnp Rt_FPR128, Rt2_FPR128, addrPairIndexed +is b_3031=0b10 & b_2229=0b10110000 & Rt2_FPR64 & Rt2_FPR128 & addrPairIndexed & Rt_FPR128 +{ + * addrPairIndexed = Rt_FPR128; + local tmp1:8 = addrPairIndexed + 16; + * tmp1 = Rt2_FPR128; +} + +# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2c800000/mask=x3fc00000 +# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2d800000/mask=x3fc00000 +# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2d000000/mask=x3fc00000 +# C7.2.329 STNP (SIMD&FP) page C7-2777 line 162166 MATCH x2c000000/mask=x3fc00000 +# CONSTRUCT xac000000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES +# SMACRO ARG1 ARG3 =store pop ARG2 ARG3 16 +:8 =store pop +# SMACRO(pseudo) null ARG1 ARG3 =NEON_stp1/2 null ARG2 ARG3 =NEON_stp2/2 +# AUNIT --inst xac000000/mask=xfe400000 --status nomem +# 128-bit variant (post-index, pre-index, and signed offset) + +:stp Rt_FPR128, Rt2_FPR128, addrPairIndexed +is b_3031=0b10 & b_2529=0b10110 & b_22=0 & Rt2_FPR128 & addrPairIndexed & Rt_FPR128 +{ + * addrPairIndexed = Rt_FPR128; + local tmp1:8 = addrPairIndexed + 16; + * tmp1 = Rt2_FPR128; +} + +# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2c800000/mask=x3fc00000 +# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2d800000/mask=x3fc00000 +# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2d000000/mask=x3fc00000 +# C7.2.329 STNP (SIMD&FP) page C7-2777 line 162166 MATCH x2c000000/mask=x3fc00000 +# CONSTRUCT x2c000000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES +# SMACRO ARG1 ARG3 =store pop ARG2 ARG3 4 +:8 =store pop +# SMACRO(pseudo) null ARG1 ARG3 =NEON_stp1/2 null ARG2 ARG3 =NEON_stp2/2 +# AUNIT --inst x2c000000/mask=xfe400000 --status nomem +# 32-bit variant (post-index, pre-index, and signed offset) + +:stp Rt_FPR32, Rt2_FPR32, addrPairIndexed +is b_3031=0b00 & b_2529=0b10110 & b_22=0 & Rt2_FPR32 & addrPairIndexed & Rt_FPR32 +{ + * addrPairIndexed = Rt_FPR32; + local tmp1:8 = addrPairIndexed + 4; + * tmp1 = Rt2_FPR32; +} + +# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2c800000/mask=x3fc00000 +# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2d800000/mask=x3fc00000 +# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2d000000/mask=x3fc00000 +# C7.2.329 STNP (SIMD&FP) page C7-2777 line 162166 MATCH x2c000000/mask=x3fc00000 +# CONSTRUCT x6c000000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES +# SMACRO ARG1 ARG3 =store pop ARG2 ARG3 8 +:8 =store pop +# SMACRO(pseudo) null ARG1 ARG3 =NEON_stp1/2 null ARG2 ARG3 =NEON_stp2/2 +# AUNIT --inst x6c000000/mask=xfe400000 --status nomem +# 64-bit variant (post-index, pre-index, and signed offset) + +:stp Rt_FPR64, Rt2_FPR64, addrPairIndexed +is b_3031=0b01 & b_2529=0b10110 & b_22=0 & Rt2_FPR64 & addrPairIndexed & Rt_FPR64 +{ + * addrPairIndexed = Rt_FPR64; + local tmp1:8 = addrPairIndexed + 8; + * tmp1 = Rt2_FPR64; +} + +# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000400/mask=x3f600c00 +# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000c00/mask=x3f600c00 +# CONSTRUCT x3c000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =store pop +# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2 +# AUNIT --inst x3c000400/mask=xffe00400 --status nomem +# Post- and Pre-offset 8-bit variant when size == 00 && opc == 00 F=FPR8 + +:str Rt_FPR8, addrIndexed +is b_3031=0b00 & b_2429=0b111100 & b_2223=0b00 & b_21=0 & b_10=1 & Rt_FPR8 & addrIndexed & Zt +{ + * addrIndexed = Rt_FPR8; +} + +# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000400/mask=x3f600c00 +# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000c00/mask=x3f600c00 +# CONSTRUCT x7c000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =store pop +# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2 +# AUNIT --inst x7c000400/mask=xffe00400 --status nomem +# Post- and Pre-offset 16-bit variant when size == 01 && opc == 00 F=FPR16 + +:str Rt_FPR16, addrIndexed +is b_3031=0b01 & b_2429=0b111100 & b_2223=0b00 & b_21=0 & b_10=1 & Rt_FPR16 & addrIndexed & Zt +{ + * addrIndexed = Rt_FPR16; +} + +# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000400/mask=x3f600c00 +# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000c00/mask=x3f600c00 +# CONSTRUCT xbc000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =store pop +# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2 +# AUNIT --inst xbc000400/mask=xffe00400 --status nomem +# Post- and Pre-offset 32-bit variant when size == 10 && opc == 00 F=FPR32 + +:str Rt_FPR32, addrIndexed +is b_3031=0b10 & b_2429=0b111100 & b_2223=0b00 & b_21=0 & b_10=1 & Rt_FPR32 & addrIndexed & Zt +{ + * addrIndexed = Rt_FPR32; +} + +# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000400/mask=x3f600c00 +# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000c00/mask=x3f600c00 +# CONSTRUCT xfc000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =store pop +# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2 +# AUNIT --inst xfc000400/mask=xffe00400 --status nomem +# Post- and Pre-offset 64-bit variant when size == 11 && opc == 00 F=FPR64 + +:str Rt_FPR64, addrIndexed +is b_3031=0b11 & b_2429=0b111100 & b_2223=0b00 & b_21=0 & b_10=1 & Rt_FPR64 & addrIndexed & Zt +{ + * addrIndexed = Rt_FPR64; +} + +# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000400/mask=x3f600c00 +# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000c00/mask=x3f600c00 +# CONSTRUCT x3c800400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =store pop +# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2 +# AUNIT --inst x3c800400/mask=xffe00400 --status nomem +# Post- and Pre-offset 128-bit variant when size == 00 && opc == 10 F=FPR128 + +:str Rt_FPR128, addrIndexed +is b_3031=0b00 & b_2429=0b111100 & b_2223=0b10 & b_21=0 & b_10=1 & Rt_FPR128 & addrIndexed & Zt +{ + * addrIndexed = Rt_FPR128; +} + +# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3d000000/mask=x3f400000 +# CONSTRUCT x3d000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =store pop +# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2 +# AUNIT --inst x3d000000/mask=xffc00000 --status nomem +# Unsigned offset 8-bit variant when size == 00 && opc == 00 F=FPR8 + +:str Rt_FPR8, addrUIMM +is b_3031=0b00 & b_2429=0b111101 & b_2223=0b00 & Rt_FPR8 & addrUIMM & Zt +{ + * addrUIMM = Rt_FPR8; +} + +# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3d000000/mask=x3f400000 +# CONSTRUCT x7d000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =store pop +# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2 +# AUNIT --inst x7d000000/mask=xffc00000 --status nomem +# Unsigned offset 16-bit variant when size == 01 && opc == 00 F=FPR16 + +:str Rt_FPR16, addrUIMM +is b_3031=0b01 & b_2429=0b111101 & b_2223=0b00 & Rt_FPR16 & addrUIMM & Zt +{ + * addrUIMM = Rt_FPR16; +} + +# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3d000000/mask=x3f400000 +# CONSTRUCT xbd000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =store pop +# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2 +# AUNIT --inst xbd000000/mask=xffc00000 --status nomem +# Unsigned offset 32-bit variant when size == 10 && opc == 00 F=FPR32 + +:str Rt_FPR32, addrUIMM +is b_3031=0b10 & b_2429=0b111101 & b_2223=0b00 & Rt_FPR32 & addrUIMM & Zt +{ + * addrUIMM = Rt_FPR32; +} + +# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3d000000/mask=x3f400000 +# CONSTRUCT xfd000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =store pop +# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2 +# AUNIT --inst xfd000000/mask=xffc00000 --status nomem +# Unsigned offset 64-bit variant when size == 11 && opc == 00 F=FPR64 + +:str Rt_FPR64, addrUIMM +is b_3031=0b11 & b_2429=0b111101 & b_2223=0b00 & Rt_FPR64 & addrUIMM & Zt +{ + * addrUIMM = Rt_FPR64; +} + +# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3d000000/mask=x3f400000 +# CONSTRUCT x3d800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =store pop +# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2 +# AUNIT --inst x3d800000/mask=xffc00000 --status nomem +# Unsigned offset 128-bit variant when size == 00 && opc == 10 F=FPR128 + +:str Rt_FPR128, addrUIMM +is b_3031=0b00 & b_2429=0b111101 & b_2223=0b10 & Rt_FPR128 & addrUIMM & Zt +{ + * addrUIMM = Rt_FPR128; +} + +# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00 +# CONSTRUCT x3c200800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop +# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4 +# AUNIT --inst x3c200800/mask=xffe02c00 --status nomem +# 8-fsreg,STR-8-fsreg variant when size == 00 && opc == 00 && option is not 011 bb=b_13 option=0 F=FPR8 G=GPR32 + +:str Rt_FPR8, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount] +is b_3031=0b00 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR8 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zd +{ + local tmp1:8 = extend_spec << extend_amount; + local tmp2:8 = Rn_GPR64xsp + tmp1; + * tmp2 = Rt_FPR8; +} + +# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00 +# CONSTRUCT x3c202800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop +# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4 +# AUNIT --inst x3c202800/mask=xffe02c00 --status nomem +# 8-fsreg,STR-8-fsreg variant when size == 00 && opc == 00 && option is not 011 bb=b_13 option=1 F=FPR8 G=GPR64 + +:str Rt_FPR8, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount] +is b_3031=0b00 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR8 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zd +{ + local tmp1:8 = extend_spec << extend_amount; + local tmp2:8 = Rn_GPR64xsp + tmp1; + * tmp2 = Rt_FPR8; +} + +# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00 +# CONSTRUCT x3c206800/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop +# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4 +# AUNIT --inst x3c206800/mask=xffe0ec00 --status nomem +# 8-fsreg,STR-8-fsreg variant when size == 00 && opc == 00 && option is 011 bb=b_1315 option=0b011 F=FPR8 G=GPR64 + +:str Rt_FPR8, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount] +is b_3031=0b00 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_1315=0b011 & b_1011=0b10 & Rt_FPR8 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zd +{ + local tmp1:8 = extend_spec << extend_amount; + local tmp2:8 = Rn_GPR64xsp + tmp1; + * tmp2 = Rt_FPR8; +} + +# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00 +# CONSTRUCT x7c200800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop +# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4 +# AUNIT --inst x7c200800/mask=xffe02c00 --status nomem +# 16-fsreg,STR-16-fsreg variant when size == 01 && opc == 00 bb=b_13 option=0 F=FPR16 G=GPR32 + +:str Rt_FPR16, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount] +is b_3031=0b01 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR16 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zd +{ + local tmp1:8 = extend_spec << extend_amount; + local tmp2:8 = Rn_GPR64xsp + tmp1; + * tmp2 = Rt_FPR16; +} + +# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00 +# CONSTRUCT x7c202800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop +# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4 +# AUNIT --inst x7c202800/mask=xffe02c00 --status nomem +# 16-fsreg,STR-16-fsreg variant when size == 01 && opc == 00 bb=b_13 option=1 F=FPR16 G=GPR64 + +:str Rt_FPR16, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount] +is b_3031=0b01 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR16 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zd +{ + local tmp1:8 = extend_spec << extend_amount; + local tmp2:8 = Rn_GPR64xsp + tmp1; + * tmp2 = Rt_FPR16; +} + +# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00 +# CONSTRUCT xbc200800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop +# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4 +# AUNIT --inst xbc200800/mask=xffe02c00 --status nomem +# 32-fsreg,STR-32-fsreg variant when size == 10 && opc == 00 bb=b_13 option=0 F=FPR32 G=GPR32 + +:str Rt_FPR32, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount] +is b_3031=0b10 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR32 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zd +{ + local tmp1:8 = extend_spec << extend_amount; + local tmp2:8 = Rn_GPR64xsp + tmp1; + * tmp2 = Rt_FPR32; +} + +# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00 +# CONSTRUCT xbc202800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop +# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4 +# AUNIT --inst xbc202800/mask=xffe02c00 --status nomem +# 32-fsreg,STR-32-fsreg variant when size == 10 && opc == 00 bb=b_13 option=1 F=FPR32 G=GPR64 + +:str Rt_FPR32, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount] +is b_3031=0b10 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR32 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zd +{ + local tmp1:8 = extend_spec << extend_amount; + local tmp2:8 = Rn_GPR64xsp + tmp1; + * tmp2 = Rt_FPR32; +} + +# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00 +# CONSTRUCT xfc200800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop +# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4 +# AUNIT --inst xfc200800/mask=xffe02c00 --status nomem +# 64-fsreg,STR-64-fsreg variant when size == 11 && opc == 00 bb=b_13 option=0 F=FPR64 G=GPR32 + +:str Rt_FPR64, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount] +is b_3031=0b11 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR64 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zd +{ + local tmp1:8 = extend_spec << extend_amount; + local tmp2:8 = Rn_GPR64xsp + tmp1; + * tmp2 = Rt_FPR64; +} + +# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00 +# CONSTRUCT xfc202800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop +# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4 +# AUNIT --inst xfc202800/mask=xffe02c00 --status nomem +# 64-fsreg,STR-64-fsreg variant when size == 11 && opc == 00 bb=b_13 option=1 F=FPR64 G=GPR64 + +:str Rt_FPR64, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount] +is b_3031=0b11 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR64 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zd +{ + local tmp1:8 = extend_spec << extend_amount; + local tmp2:8 = Rn_GPR64xsp + tmp1; + * tmp2 = Rt_FPR64; +} + +# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00 +# CONSTRUCT x3ca00800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop +# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4 +# AUNIT --inst x3ca00800/mask=xffe02c00 --status nomem +# 128-fsreg,STR-128-fsreg variant when size == 00 && opc == 10 bb=b_13 option=0 F=FPR128 G=GPR32 + +:str Rt_FPR128, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount] +is b_3031=0b00 & b_2429=0b111100 & b_2223=0b10 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR128 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zd +{ + local tmp1:8 = extend_spec << extend_amount; + local tmp2:8 = Rn_GPR64xsp + tmp1; + * tmp2 = Rt_FPR128; +} + +# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00 +# CONSTRUCT x3ca02800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop +# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4 +# AUNIT --inst x3ca02800/mask=xffe02c00 --status nomem +# 128-fsreg,STR-128-fsreg variant when size == 00 && opc == 10 bb=b_13 option=1 F=FPR128 G=GPR64 + +:str Rt_FPR128, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount] +is b_3031=0b00 & b_2429=0b111100 & b_2223=0b10 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR128 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zd +{ + local tmp1:8 = extend_spec << extend_amount; + local tmp2:8 = Rn_GPR64xsp + tmp1; + * tmp2 = Rt_FPR128; +} + +# C7.2.333 STUR (SIMD&FP) page C7-2789 line 162949 MATCH x3c000000/mask=x3f600c00 +# CONSTRUCT x3c800000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =store pop +# SMACRO(pseudo) null ARG1 ARG2 =NEON_stur/2 +# AUNIT --inst x3c800000/mask=xffe00c00 --status nomem + +:stur Rt_FPR128, addrIndexed +is size.ldstr=0 & b_2729=7 & v=1 & b_2425=0 & b_23=1 & b_2222=0 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR128 +{ + * addrIndexed = Rt_FPR128; +} + +# C7.2.333 STUR (SIMD&FP) page C7-2789 line 162949 MATCH x3c000000/mask=x3f600c00 +# CONSTRUCT x7c000000/mask=xffc00c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =store pop +# SMACRO(pseudo) null ARG1 ARG2 =NEON_stur/2 +# AUNIT --inst x7c000000/mask=xffc00c00 --status nomem + +:stur Rt_FPR16, addrIndexed +is size.ldstr=1 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=0 & b_1011=0 & addrIndexed & Rt_FPR16 +{ + * addrIndexed = Rt_FPR16; +} + +# C7.2.333 STUR (SIMD&FP) page C7-2789 line 162949 MATCH x3c000000/mask=x3f600c00 +# CONSTRUCT xbc000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =store pop +# SMACRO(pseudo) null ARG1 ARG2 =NEON_stur/2 +# AUNIT --inst xbc000000/mask=xffe00c00 --status nomem + +:stur Rt_FPR32, addrIndexed +is size.ldstr=2 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR32 +{ + * addrIndexed = Rt_FPR32; +} + +# C7.2.333 STUR (SIMD&FP) page C7-2789 line 162949 MATCH x3c000000/mask=x3f600c00 +# CONSTRUCT xfc000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =store pop +# SMACRO(pseudo) null ARG1 ARG2 =NEON_stur/2 +# AUNIT --inst xfc000000/mask=xffe00c00 --status nomem + +:stur Rt_FPR64, addrIndexed +is size.ldstr=3 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR64 +{ + * addrIndexed = Rt_FPR64; +} + +# C7.2.333 STUR (SIMD&FP) page C7-2789 line 162949 MATCH x3c000000/mask=x3f600c00 +# CONSTRUCT x3c000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =store pop +# SMACRO(pseudo) null ARG1 ARG2 =NEON_stur/2 +# AUNIT --inst x3c000000/mask=xffe00c00 --status nomem + +:stur Rt_FPR8, addrIndexed +is size.ldstr=0 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR8 +{ + * addrIndexed = Rt_FPR8; +} + +# C7.2.334 SUB (vector) page C7-2791 line 163076 MATCH x7e208400/mask=xff20fc00 +# CONSTRUCT x7ee08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =- +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2 +# AUNIT --inst x7ee08400/mask=xffe0fc00 --status pass + +:sub Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x10 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = Rn_FPR64 - Rm_FPR64; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.334 SUB (vector) page C7-2791 line 163076 MATCH x2e208400/mask=xbf20fc00 +# CONSTRUCT x6e208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$-@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@1 +# AUNIT --inst x6e208400/mask=xffe0fc00 --status pass + +:sub Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x10 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + # simd infix Rd_VPR128.16B = Rn_VPR128.16B - Rm_VPR128.16B on lane size 1 + Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] - Rm_VPR128.16B[0,8]; + Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] - Rm_VPR128.16B[8,8]; + Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] - Rm_VPR128.16B[16,8]; + Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] - Rm_VPR128.16B[24,8]; + Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] - Rm_VPR128.16B[32,8]; + Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] - Rm_VPR128.16B[40,8]; + Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] - Rm_VPR128.16B[48,8]; + Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] - Rm_VPR128.16B[56,8]; + Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] - Rm_VPR128.16B[64,8]; + Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] - Rm_VPR128.16B[72,8]; + Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] - Rm_VPR128.16B[80,8]; + Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] - Rm_VPR128.16B[88,8]; + Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] - Rm_VPR128.16B[96,8]; + Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] - Rm_VPR128.16B[104,8]; + Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] - Rm_VPR128.16B[112,8]; + Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] - Rm_VPR128.16B[120,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.334 SUB (vector) page C7-2791 line 163076 MATCH x2e208400/mask=xbf20fc00 +# CONSTRUCT x6ee08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$-@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@8 +# AUNIT --inst x6ee08400/mask=xffe0fc00 --status pass + +:sub Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x10 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + # simd infix Rd_VPR128.2D = Rn_VPR128.2D - Rm_VPR128.2D on lane size 8 + Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] - Rm_VPR128.2D[0,64]; + Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] - Rm_VPR128.2D[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.334 SUB (vector) page C7-2791 line 163076 MATCH x2e208400/mask=xbf20fc00 +# CONSTRUCT x2ea08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@4 +# AUNIT --inst x2ea08400/mask=xffe0fc00 --status pass + +:sub Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x10 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + # simd infix Rd_VPR64.2S = Rn_VPR64.2S - Rm_VPR64.2S on lane size 4 + Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] - Rm_VPR64.2S[0,32]; + Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] - Rm_VPR64.2S[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.334 SUB (vector) page C7-2791 line 163076 MATCH x2e208400/mask=xbf20fc00 +# CONSTRUCT x2e608400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$-@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@2 +# AUNIT --inst x2e608400/mask=xffe0fc00 --status pass + +:sub Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x10 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + # simd infix Rd_VPR64.4H = Rn_VPR64.4H - Rm_VPR64.4H on lane size 2 + Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] - Rm_VPR64.4H[0,16]; + Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] - Rm_VPR64.4H[16,16]; + Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] - Rm_VPR64.4H[32,16]; + Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] - Rm_VPR64.4H[48,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.334 SUB (vector) page C7-2791 line 163076 MATCH x2e208400/mask=xbf20fc00 +# CONSTRUCT x6ea08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@4 +# AUNIT --inst x6ea08400/mask=xffe0fc00 --status pass + +:sub Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x10 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd infix Rd_VPR128.4S = Rn_VPR128.4S - Rm_VPR128.4S on lane size 4 + Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] - Rm_VPR128.4S[0,32]; + Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] - Rm_VPR128.4S[32,32]; + Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] - Rm_VPR128.4S[64,32]; + Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] - Rm_VPR128.4S[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.334 SUB (vector) page C7-2791 line 163076 MATCH x2e208400/mask=xbf20fc00 +# CONSTRUCT x2e208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$-@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@1 +# AUNIT --inst x2e208400/mask=xffe0fc00 --status pass + +:sub Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x10 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + # simd infix Rd_VPR64.8B = Rn_VPR64.8B - Rm_VPR64.8B on lane size 1 + Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] - Rm_VPR64.8B[0,8]; + Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] - Rm_VPR64.8B[8,8]; + Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] - Rm_VPR64.8B[16,8]; + Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] - Rm_VPR64.8B[24,8]; + Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] - Rm_VPR64.8B[32,8]; + Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] - Rm_VPR64.8B[40,8]; + Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] - Rm_VPR64.8B[48,8]; + Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] - Rm_VPR64.8B[56,8]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.334 SUB (vector) page C7-2791 line 163076 MATCH x2e208400/mask=xbf20fc00 +# CONSTRUCT x6e608400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =$-@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@2 +# AUNIT --inst x6e608400/mask=xffe0fc00 --status pass + +:sub Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x10 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + # simd infix Rd_VPR128.8H = Rn_VPR128.8H - Rm_VPR128.8H on lane size 2 + Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] - Rm_VPR128.8H[0,16]; + Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] - Rm_VPR128.8H[16,16]; + Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] - Rm_VPR128.8H[32,16]; + Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] - Rm_VPR128.8H[48,16]; + Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] - Rm_VPR128.8H[64,16]; + Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] - Rm_VPR128.8H[80,16]; + Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] - Rm_VPR128.8H[96,16]; + Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] - Rm_VPR128.8H[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.335 SUBHN, SUBHN2 page C7-2793 line 163214 MATCH x0e206000/mask=xbf20fc00 +# CONSTRUCT x4e206000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $-@2 &=$shuffle@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15:1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@2 +# AUNIT --inst x4e206000/mask=xffe0fc00 --status pass + +:subhn2 Rd_VPR128.16B, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x6 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.16B & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.8H - Rm_VPR128.8H on lane size 2 + TMPQ1[0,16] = Rn_VPR128.8H[0,16] - Rm_VPR128.8H[0,16]; + TMPQ1[16,16] = Rn_VPR128.8H[16,16] - Rm_VPR128.8H[16,16]; + TMPQ1[32,16] = Rn_VPR128.8H[32,16] - Rm_VPR128.8H[32,16]; + TMPQ1[48,16] = Rn_VPR128.8H[48,16] - Rm_VPR128.8H[48,16]; + TMPQ1[64,16] = Rn_VPR128.8H[64,16] - Rm_VPR128.8H[64,16]; + TMPQ1[80,16] = Rn_VPR128.8H[80,16] - Rm_VPR128.8H[80,16]; + TMPQ1[96,16] = Rn_VPR128.8H[96,16] - Rm_VPR128.8H[96,16]; + TMPQ1[112,16] = Rn_VPR128.8H[112,16] - Rm_VPR128.8H[112,16]; + # simd shuffle Rd_VPR128.16B = TMPQ1 (@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15) lane size 1 + Rd_VPR128.16B[64,8] = TMPQ1[8,8]; + Rd_VPR128.16B[72,8] = TMPQ1[24,8]; + Rd_VPR128.16B[80,8] = TMPQ1[40,8]; + Rd_VPR128.16B[88,8] = TMPQ1[56,8]; + Rd_VPR128.16B[96,8] = TMPQ1[72,8]; + Rd_VPR128.16B[104,8] = TMPQ1[88,8]; + Rd_VPR128.16B[112,8] = TMPQ1[104,8]; + Rd_VPR128.16B[120,8] = TMPQ1[120,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.335 SUBHN, SUBHN2 page C7-2793 line 163214 MATCH x0e206000/mask=xbf20fc00 +# CONSTRUCT x4ea06000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $-@8 &=$shuffle@1-2@3-3:4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@8 +# AUNIT --inst x4ea06000/mask=xffe0fc00 --status pass + +:subhn2 Rd_VPR128.4S, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x6 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.4S & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.2D - Rm_VPR128.2D on lane size 8 + TMPQ1[0,64] = Rn_VPR128.2D[0,64] - Rm_VPR128.2D[0,64]; + TMPQ1[64,64] = Rn_VPR128.2D[64,64] - Rm_VPR128.2D[64,64]; + # simd shuffle Rd_VPR128.4S = TMPQ1 (@1-2@3-3) lane size 4 + Rd_VPR128.4S[64,32] = TMPQ1[32,32]; + Rd_VPR128.4S[96,32] = TMPQ1[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.335 SUBHN, SUBHN2 page C7-2793 line 163214 MATCH x0e206000/mask=xbf20fc00 +# CONSTRUCT x4e606000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $-@4 &=$shuffle@1-4@3-5@5-6@7-7:2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_subhn2/3@4 +# AUNIT --inst x4e606000/mask=xffe0fc00 --status pass + +:subhn2 Rd_VPR128.8H, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x6 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.8H & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.4S - Rm_VPR128.4S on lane size 4 + TMPQ1[0,32] = Rn_VPR128.4S[0,32] - Rm_VPR128.4S[0,32]; + TMPQ1[32,32] = Rn_VPR128.4S[32,32] - Rm_VPR128.4S[32,32]; + TMPQ1[64,32] = Rn_VPR128.4S[64,32] - Rm_VPR128.4S[64,32]; + TMPQ1[96,32] = Rn_VPR128.4S[96,32] - Rm_VPR128.4S[96,32]; + # simd shuffle Rd_VPR128.8H = TMPQ1 (@1-4@3-5@5-6@7-7) lane size 2 + Rd_VPR128.8H[64,16] = TMPQ1[16,16]; + Rd_VPR128.8H[80,16] = TMPQ1[48,16]; + Rd_VPR128.8H[96,16] = TMPQ1[80,16]; + Rd_VPR128.8H[112,16] = TMPQ1[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.335 SUBHN, SUBHN2 page C7-2793 line 163214 MATCH x0e206000/mask=xbf20fc00 +# CONSTRUCT x0ea06000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $-@8 &=$shuffle@1-0@3-1:4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_subhn/3@8 +# AUNIT --inst x0ea06000/mask=xffe0fc00 --status pass + +:subhn Rd_VPR64.2S, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x6 & b_1011=0 & Rn_VPR128.2D & Rd_VPR64.2S & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.2D - Rm_VPR128.2D on lane size 8 + TMPQ1[0,64] = Rn_VPR128.2D[0,64] - Rm_VPR128.2D[0,64]; + TMPQ1[64,64] = Rn_VPR128.2D[64,64] - Rm_VPR128.2D[64,64]; + # simd shuffle Rd_VPR64.2S = TMPQ1 (@1-0@3-1) lane size 4 + Rd_VPR64.2S[0,32] = TMPQ1[32,32]; + Rd_VPR64.2S[32,32] = TMPQ1[96,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.335 SUBHN, SUBHN2 page C7-2793 line 163214 MATCH x0e206000/mask=xbf20fc00 +# CONSTRUCT x0e606000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $-@4 &=$shuffle@1-0@3-1@5-2@7-3:2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_subhn/3@4 +# AUNIT --inst x0e606000/mask=xffe0fc00 --status pass + +:subhn Rd_VPR64.4H, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x6 & b_1011=0 & Rn_VPR128.4S & Rd_VPR64.4H & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.4S - Rm_VPR128.4S on lane size 4 + TMPQ1[0,32] = Rn_VPR128.4S[0,32] - Rm_VPR128.4S[0,32]; + TMPQ1[32,32] = Rn_VPR128.4S[32,32] - Rm_VPR128.4S[32,32]; + TMPQ1[64,32] = Rn_VPR128.4S[64,32] - Rm_VPR128.4S[64,32]; + TMPQ1[96,32] = Rn_VPR128.4S[96,32] - Rm_VPR128.4S[96,32]; + # simd shuffle Rd_VPR64.4H = TMPQ1 (@1-0@3-1@5-2@7-3) lane size 2 + Rd_VPR64.4H[0,16] = TMPQ1[16,16]; + Rd_VPR64.4H[16,16] = TMPQ1[48,16]; + Rd_VPR64.4H[32,16] = TMPQ1[80,16]; + Rd_VPR64.4H[48,16] = TMPQ1[112,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.335 SUBHN, SUBHN2 page C7-2793 line 163214 MATCH x0e206000/mask=xbf20fc00 +# CONSTRUCT x0e206000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $-@2 &=$shuffle@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7:1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_subhn/3@2 +# AUNIT --inst x0e206000/mask=xffe0fc00 --status pass + +:subhn Rd_VPR64.8B, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x6 & b_1011=0 & Rn_VPR128.8H & Rd_VPR64.8B & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.8H - Rm_VPR128.8H on lane size 2 + TMPQ1[0,16] = Rn_VPR128.8H[0,16] - Rm_VPR128.8H[0,16]; + TMPQ1[16,16] = Rn_VPR128.8H[16,16] - Rm_VPR128.8H[16,16]; + TMPQ1[32,16] = Rn_VPR128.8H[32,16] - Rm_VPR128.8H[32,16]; + TMPQ1[48,16] = Rn_VPR128.8H[48,16] - Rm_VPR128.8H[48,16]; + TMPQ1[64,16] = Rn_VPR128.8H[64,16] - Rm_VPR128.8H[64,16]; + TMPQ1[80,16] = Rn_VPR128.8H[80,16] - Rm_VPR128.8H[80,16]; + TMPQ1[96,16] = Rn_VPR128.8H[96,16] - Rm_VPR128.8H[96,16]; + TMPQ1[112,16] = Rn_VPR128.8H[112,16] - Rm_VPR128.8H[112,16]; + # simd shuffle Rd_VPR64.8B = TMPQ1 (@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7) lane size 1 + Rd_VPR64.8B[0,8] = TMPQ1[8,8]; + Rd_VPR64.8B[8,8] = TMPQ1[24,8]; + Rd_VPR64.8B[16,8] = TMPQ1[40,8]; + Rd_VPR64.8B[24,8] = TMPQ1[56,8]; + Rd_VPR64.8B[32,8] = TMPQ1[72,8]; + Rd_VPR64.8B[40,8] = TMPQ1[88,8]; + Rd_VPR64.8B[48,8] = TMPQ1[104,8]; + Rd_VPR64.8B[56,8] = TMPQ1[120,8]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x5e203800/mask=xff3ffc00 +# CONSTRUCT x5e203800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 &=+ +# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2 +# AUNIT --inst x5e203800/mask=xfffffc00 --status fail --comment "nointsat" +# Scalar variant when size=00 Q=1 bb=1 V=FPR8 s2=2 + +:suqadd Rd_FPR8, Rn_FPR8 +is b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b00 & b_1021=0b100000001110 & Rd_FPR8 & Rn_FPR8 & Zd +{ + Rd_FPR8 = Rd_FPR8 + Rn_FPR8; + zext_zb(Zd); # zero upper 31 bytes of Zd +} + +# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x5e203800/mask=xff3ffc00 +# CONSTRUCT x5e603800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 &=+ +# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2 +# AUNIT --inst x5e603800/mask=xfffffc00 --status fail --comment "nointsat" +# Scalar variant when size=01 Q=1 bb=1 V=FPR16 s2=4 + +:suqadd Rd_FPR16, Rn_FPR16 +is b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b01 & b_1021=0b100000001110 & Rd_FPR16 & Rn_FPR16 & Zd +{ + Rd_FPR16 = Rd_FPR16 + Rn_FPR16; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x5e203800/mask=xff3ffc00 +# CONSTRUCT x5ea03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 &=+ +# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2 +# AUNIT --inst x5ea03800/mask=xfffffc00 --status fail --comment "nointsat" +# Scalar variant when size=10 Q=1 bb=1 V=FPR32 s2=8 + +:suqadd Rd_FPR32, Rn_FPR32 +is b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b10 & b_1021=0b100000001110 & Rd_FPR32 & Rn_FPR32 & Zd +{ + Rd_FPR32 = Rd_FPR32 + Rn_FPR32; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x5e203800/mask=xff3ffc00 +# CONSTRUCT x5ee03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 &=+ +# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2 +# AUNIT --inst x5ee03800/mask=xfffffc00 --status fail --comment "nointsat" +# Scalar variant when size=11 Q=1 bb=1 V=FPR64 s2=16 + +:suqadd Rd_FPR64, Rn_FPR64 +is b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b11 & b_1021=0b100000001110 & Rd_FPR64 & Rn_FPR64 & Zd +{ + Rd_FPR64 = Rd_FPR64 + Rn_FPR64; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x0e203800/mask=xbf3ffc00 +# CONSTRUCT x0e203800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 &=$+@1 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@1 +# AUNIT --inst x0e203800/mask=xfffffc00 --status fail --comment "nointsat" +# Vector variant when size=00 Q=0 bb=0 V=VPR64.8B e1=1 s2=16 + +:suqadd Rd_VPR64.8B, Rn_VPR64.8B +is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000001110 & Rd_VPR64.8B & Rn_VPR64.8B & Zd +{ + # simd infix Rd_VPR64.8B = Rd_VPR64.8B + Rn_VPR64.8B on lane size 1 + Rd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] + Rn_VPR64.8B[0,8]; + Rd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] + Rn_VPR64.8B[8,8]; + Rd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] + Rn_VPR64.8B[16,8]; + Rd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] + Rn_VPR64.8B[24,8]; + Rd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] + Rn_VPR64.8B[32,8]; + Rd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] + Rn_VPR64.8B[40,8]; + Rd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] + Rn_VPR64.8B[48,8]; + Rd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] + Rn_VPR64.8B[56,8]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x0e203800/mask=xbf3ffc00 +# CONSTRUCT x4e203800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 &=$+@1 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@1 +# AUNIT --inst x4e203800/mask=xfffffc00 --status fail --comment "nointsat" +# Vector variant when size=00 Q=1 bb=0 V=VPR128.16B e1=1 s2=32 + +:suqadd Rd_VPR128.16B, Rn_VPR128.16B +is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000001110 & Rd_VPR128.16B & Rn_VPR128.16B & Zd +{ + # simd infix Rd_VPR128.16B = Rd_VPR128.16B + Rn_VPR128.16B on lane size 1 + Rd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] + Rn_VPR128.16B[0,8]; + Rd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] + Rn_VPR128.16B[8,8]; + Rd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] + Rn_VPR128.16B[16,8]; + Rd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] + Rn_VPR128.16B[24,8]; + Rd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] + Rn_VPR128.16B[32,8]; + Rd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] + Rn_VPR128.16B[40,8]; + Rd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] + Rn_VPR128.16B[48,8]; + Rd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] + Rn_VPR128.16B[56,8]; + Rd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] + Rn_VPR128.16B[64,8]; + Rd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] + Rn_VPR128.16B[72,8]; + Rd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] + Rn_VPR128.16B[80,8]; + Rd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] + Rn_VPR128.16B[88,8]; + Rd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] + Rn_VPR128.16B[96,8]; + Rd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] + Rn_VPR128.16B[104,8]; + Rd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] + Rn_VPR128.16B[112,8]; + Rd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] + Rn_VPR128.16B[120,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x0e203800/mask=xbf3ffc00 +# CONSTRUCT x0e603800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@2 +# AUNIT --inst x0e603800/mask=xfffffc00 --status fail --comment "nointsat" +# Vector variant when size=01 Q=0 bb=0 V=VPR64.4H e1=2 s2=16 + +:suqadd Rd_VPR64.4H, Rn_VPR64.4H +is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000001110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd +{ + # simd infix Rd_VPR64.4H = Rd_VPR64.4H + Rn_VPR64.4H on lane size 2 + Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + Rn_VPR64.4H[0,16]; + Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + Rn_VPR64.4H[16,16]; + Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + Rn_VPR64.4H[32,16]; + Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + Rn_VPR64.4H[48,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x0e203800/mask=xbf3ffc00 +# CONSTRUCT x4e603800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@2 +# AUNIT --inst x4e603800/mask=xfffffc00 --status fail --comment "nointsat" +# Vector variant when size=01 Q=1 bb=0 V=VPR128.8H e1=2 s2=32 + +:suqadd Rd_VPR128.8H, Rn_VPR128.8H +is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000001110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd +{ + # simd infix Rd_VPR128.8H = Rd_VPR128.8H + Rn_VPR128.8H on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + Rn_VPR128.8H[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + Rn_VPR128.8H[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + Rn_VPR128.8H[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + Rn_VPR128.8H[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + Rn_VPR128.8H[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + Rn_VPR128.8H[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + Rn_VPR128.8H[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + Rn_VPR128.8H[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x0e203800/mask=xbf3ffc00 +# CONSTRUCT x0ea03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@4 +# AUNIT --inst x0ea03800/mask=xfffffc00 --status fail --comment "nointsat" +# Vector variant when size=10 Q=0 bb=0 V=VPR64.2S e1=4 s2=16 + +:suqadd Rd_VPR64.2S, Rn_VPR64.2S +is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000001110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd +{ + # simd infix Rd_VPR64.2S = Rd_VPR64.2S + Rn_VPR64.2S on lane size 4 + Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + Rn_VPR64.2S[0,32]; + Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + Rn_VPR64.2S[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x0e203800/mask=xbf3ffc00 +# CONSTRUCT x4ea03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@4 +# AUNIT --inst x4ea03800/mask=xfffffc00 --status fail --comment "nointsat" +# Vector variant when size=10 Q=1 bb=0 V=VPR128.4S e1=4 s2=32 + +:suqadd Rd_VPR128.4S, Rn_VPR128.4S +is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000001110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd +{ + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + Rn_VPR128.4S on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + Rn_VPR128.4S[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + Rn_VPR128.4S[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + Rn_VPR128.4S[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + Rn_VPR128.4S[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x0e203800/mask=xbf3ffc00 +# CONSTRUCT x4ee03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@8 +# AUNIT --inst x4ee03800/mask=xfffffc00 --status fail --comment "nointsat" +# Vector variant when size=11 Q=1 bb=0 V=VPR128.2D e1=8 s2=32 + +:suqadd Rd_VPR128.2D, Rn_VPR128.2D +is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b11 & b_1021=0b100000001110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd +{ + # simd infix Rd_VPR128.2D = Rd_VPR128.2D + Rn_VPR128.2D on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + Rn_VPR128.2D[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + Rn_VPR128.2D[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00 +# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00 +# CONSTRUCT x4f08a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 =$sext@1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_sxtl2/1@1 +# AUNIT --inst x4f08a400/mask=xfffffc00 --status pass --comment "ext" + +:sxtl2 Rd_VPR128.8H, Rn_VPR128.16B +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3=0 & b_1115=0x14 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.8H & Zd +{ + TMPD1 = Rn_VPR128.16B[64,64]; + # simd resize Rd_VPR128.8H = sext(TMPD1) (lane size 1 to 2) + Rd_VPR128.8H[0,16] = sext(TMPD1[0,8]); + Rd_VPR128.8H[16,16] = sext(TMPD1[8,8]); + Rd_VPR128.8H[32,16] = sext(TMPD1[16,8]); + Rd_VPR128.8H[48,16] = sext(TMPD1[24,8]); + Rd_VPR128.8H[64,16] = sext(TMPD1[32,8]); + Rd_VPR128.8H[80,16] = sext(TMPD1[40,8]); + Rd_VPR128.8H[96,16] = sext(TMPD1[48,8]); + Rd_VPR128.8H[112,16] = sext(TMPD1[56,8]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00 +# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00 +# CONSTRUCT x0f20a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =var =$sext@4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_sxtl/1@4 +# AUNIT --inst x0f20a400/mask=xfffffc00 --status pass --comment "ext" + +:sxtl Rd_VPR128.2D, Rn_VPR64.2S +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5=0 & b_1115=0x14 & b_1010=1 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR64.2S; + # simd resize Rd_VPR128.2D = sext(TMPD1) (lane size 4 to 8) + Rd_VPR128.2D[0,64] = sext(TMPD1[0,32]); + Rd_VPR128.2D[64,64] = sext(TMPD1[32,32]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00 +# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00 +# CONSTRUCT x0f10a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =var =$sext@2 +# SMACRO(pseudo) ARG1 ARG2 =NEON_sxtl/1@2 +# AUNIT --inst x0f10a400/mask=xfffffc00 --status pass --comment "ext" + +:sxtl Rd_VPR128.4S, Rn_VPR64.4H +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4=0 & b_1115=0x14 & b_1010=1 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR64.4H; + # simd resize Rd_VPR128.4S = sext(TMPD1) (lane size 2 to 4) + Rd_VPR128.4S[0,32] = sext(TMPD1[0,16]); + Rd_VPR128.4S[32,32] = sext(TMPD1[16,16]); + Rd_VPR128.4S[64,32] = sext(TMPD1[32,16]); + Rd_VPR128.4S[96,32] = sext(TMPD1[48,16]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00 +# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00 +# CONSTRUCT x4f20a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 =$sext@4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_sxtl2/1@4 +# AUNIT --inst x4f20a400/mask=xfffffc00 --status pass --comment "ext" + +:sxtl2 Rd_VPR128.2D, Rn_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5=0 & b_1115=0x14 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize Rd_VPR128.2D = sext(TMPD1) (lane size 4 to 8) + Rd_VPR128.2D[0,64] = sext(TMPD1[0,32]); + Rd_VPR128.2D[64,64] = sext(TMPD1[32,32]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00 +# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00 +# CONSTRUCT x0f08a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =var =$sext@1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_sxtl/1@1 +# AUNIT --inst x0f08a400/mask=xfffffc00 --status pass --comment "ext" + +:sxtl Rd_VPR128.8H, Rn_VPR64.8B +is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3=0 & b_1115=0x14 & b_1010=1 & Rn_VPR64.8B & Rd_VPR128.8H & Rn_VPR128 & Zd +{ + TMPD1 = Rn_VPR64.8B; + # simd resize Rd_VPR128.8H = sext(TMPD1) (lane size 1 to 2) + Rd_VPR128.8H[0,16] = sext(TMPD1[0,8]); + Rd_VPR128.8H[16,16] = sext(TMPD1[8,8]); + Rd_VPR128.8H[32,16] = sext(TMPD1[16,8]); + Rd_VPR128.8H[48,16] = sext(TMPD1[24,8]); + Rd_VPR128.8H[64,16] = sext(TMPD1[32,8]); + Rd_VPR128.8H[80,16] = sext(TMPD1[40,8]); + Rd_VPR128.8H[96,16] = sext(TMPD1[48,8]); + Rd_VPR128.8H[112,16] = sext(TMPD1[56,8]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00 +# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00 +# CONSTRUCT x4f10a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 =$sext@2 +# SMACRO(pseudo) ARG1 ARG2 =NEON_sxtl2/1@2 +# AUNIT --inst x4f10a400/mask=xfffffc00 --status pass --comment "ext" + +:sxtl2 Rd_VPR128.4S, Rn_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4=0 & b_1115=0x14 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize Rd_VPR128.4S = sext(TMPD1) (lane size 2 to 4) + Rd_VPR128.4S[0,32] = sext(TMPD1[0,16]); + Rd_VPR128.4S[32,32] = sext(TMPD1[16,16]); + Rd_VPR128.4S[64,32] = sext(TMPD1[32,16]); + Rd_VPR128.4S[96,32] = sext(TMPD1[48,16]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.322 TBL page C7-1717 line 99409 KEEPWITH + +tblx: "tbl" is b_12=0 { local tmp:16 = zext(0:8); export tmp; } +tblx: "tbx" is b_12=1 & Rd_VPR128 { export Rd_VPR128; } + +# C7.2.339 TBL page C7-2801 line 163652 MATCH x0e000000/mask=xbfe09c00 +# C7.2.340 TBX page C7-2803 line 163781 MATCH x0e001000/mask=xbfe09c00 +# CONSTRUCT x0e000000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 tblx Rn_VPR128.16B ARG3 =a64_TBL/3 +# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B ARG3 =NEON_tblx/3@1 +# AUNIT --inst x0e000000/mask=xffe0ec00 --status pass +# Q == 0 && len == 00 8B, Single register table variant + +:^tblx Rd_VPR64.8B, "{"^Rn_VPR128.16B^"}", Rm_VPR64.8B +is b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=0 & b_1314=0b00 & Rm_VPR64.8B & Rn_VPR128.16B & Rd_VPR64.8B & tblx & Zd +{ + Rd_VPR64.8B = a64_TBL(tblx, Rn_VPR128.16B, Rm_VPR64.8B); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.339 TBL page C7-2801 line 163652 MATCH x0e000000/mask=xbfe09c00 +# C7.2.340 TBX page C7-2803 line 163781 MATCH x0e001000/mask=xbfe09c00 +# CONSTRUCT x4e000000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 tblx Rn_VPR128.16B ARG3 =a64_TBL/3 +# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B ARG3 =NEON_tblx/3@1 +# AUNIT --inst x4e000000/mask=xffe0ec00 --status pass +# Q == 1 && len == 00 16B, Single register table variant + +:^tblx Rd_VPR128.16B, "{"^Rn_VPR128.16B^"}", Rm_VPR128.16B +is b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=1 & b_1314=0b00 & Rm_VPR128.16B & Rn_VPR128.16B & Rd_VPR128.16B & tblx & Zd +{ + Rd_VPR128.16B = a64_TBL(tblx, Rn_VPR128.16B, Rm_VPR128.16B); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.339 TBL page C7-2801 line 163652 MATCH x0e000000/mask=xbfe09c00 +# C7.2.340 TBX page C7-2803 line 163781 MATCH x0e001000/mask=xbfe09c00 +# CONSTRUCT x0e002000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B ARG4 =a64_TBL/4 +# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B ARG4 =NEON_tblx/4 +# AUNIT --inst x0e002000/mask=xffe0ec00 --status pass +# Q == 0 && len == 01 8B, Two register table variant + +:^tblx Rd_VPR64.8B, "{"^Rn_VPR128.16B^", "^Rnn_VPR128.16B^"}", Rm_VPR64.8B +is b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=0 & b_1314=0b01 & Rm_VPR64.8B & Rn_VPR128.16B & Rnn_VPR128.16B & Rd_VPR64.8B & tblx & Zd +{ + Rd_VPR64.8B = a64_TBL(tblx, Rn_VPR128.16B, Rnn_VPR128.16B, Rm_VPR64.8B); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.339 TBL page C7-2801 line 163652 MATCH x0e000000/mask=xbfe09c00 +# C7.2.340 TBX page C7-2803 line 163781 MATCH x0e001000/mask=xbfe09c00 +# CONSTRUCT x4e002000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B ARG4 =a64_TBL/4 +# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B ARG4 =NEON_tblx/4 +# AUNIT --inst x4e002000/mask=xffe0ec00 --status pass +# Q == 1 && len == 01 16B, Two register table variant + +:^tblx Rd_VPR128.16B, "{"^Rn_VPR128.16B^", "^Rnn_VPR128.16B^"}", Rm_VPR128.16B +is b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=1 & b_1314=0b01 & Rm_VPR128.16B & Rn_VPR128.16B & Rnn_VPR128.16B & Rd_VPR128.16B & tblx & Zd +{ + Rd_VPR128.16B = a64_TBL(tblx, Rn_VPR128.16B, Rnn_VPR128.16B, Rm_VPR128.16B); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.339 TBL page C7-2801 line 163652 MATCH x0e000000/mask=xbfe09c00 +# C7.2.340 TBX page C7-2803 line 163781 MATCH x0e001000/mask=xbfe09c00 +# CONSTRUCT x0e004000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B ARG5 =a64_TBL/5 +# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B ARG5 =NEON_tblx/5 +# AUNIT --inst x0e004000/mask=xffe0ec00 --status pass +# Q == 0 && len == 10 8B, Three register table variant + +:^tblx Rd_VPR64.8B, "{"^Rn_VPR128.16B^", "^Rnn_VPR128.16B^", "^Rnnn_VPR128.16B^"}", Rm_VPR64.8B +is b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=0 & b_1314=0b10 & Rm_VPR64.8B & Rn_VPR128.16B & Rnn_VPR128.16B & Rnnn_VPR128.16B & Rd_VPR64.8B & tblx & Zd +{ + Rd_VPR64.8B = a64_TBL(tblx, Rn_VPR128.16B, Rnn_VPR128.16B, Rnnn_VPR128.16B, Rm_VPR64.8B); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.339 TBL page C7-2801 line 163652 MATCH x0e000000/mask=xbfe09c00 +# C7.2.340 TBX page C7-2803 line 163781 MATCH x0e001000/mask=xbfe09c00 +# CONSTRUCT x4e004000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B ARG5 =a64_TBL/5 +# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B ARG5 =NEON_tblx/5 +# AUNIT --inst x4e004000/mask=xffe0ec00 --status pass +# Q == 1 && len == 10 16B, Three register table variant + +:^tblx Rd_VPR128.16B, "{"^Rn_VPR128.16B^", "^Rnn_VPR128.16B^", "^Rnnn_VPR128.16B^"}", Rm_VPR128.16B +is b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=1 & b_1314=0b10 & Rm_VPR128.16B & Rn_VPR128.16B & Rnn_VPR128.16B & Rnnn_VPR128.16B & Rd_VPR128.16B & tblx & Zd +{ + Rd_VPR128.16B = a64_TBL(tblx, Rn_VPR128.16B, Rnn_VPR128.16B, Rnnn_VPR128.16B, Rm_VPR128.16B); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.339 TBL page C7-2801 line 163652 MATCH x0e000000/mask=xbfe09c00 +# C7.2.340 TBX page C7-2803 line 163781 MATCH x0e001000/mask=xbfe09c00 +# CONSTRUCT x0e006000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B Rnnnn_VPR128.16B ARG6 =a64_TBL/6 +# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B Rnnnn_VPR128.16B ARG6 =NEON_tblx/6 +# AUNIT --inst x0e006000/mask=xffe0ec00 --status pass +# Q == 0 && len == 11 8B, Four register table variant + +:^tblx Rd_VPR64.8B, "{"^Rn_VPR128.16B^", "^Rnn_VPR128.16B^", "^Rnnn_VPR128.16B^", "^Rnnnn_VPR128.16B^"}", Rm_VPR64.8B +is b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=0 & b_1314=0b11 & Rm_VPR64.8B & Rn_VPR128.16B & Rnn_VPR128.16B & Rnnn_VPR128.16B & Rnnnn_VPR128.16B & Rd_VPR64.8B & tblx & Zd +{ + Rd_VPR64.8B = a64_TBL(tblx, Rn_VPR128.16B, Rnn_VPR128.16B, Rnnn_VPR128.16B, Rnnnn_VPR128.16B, Rm_VPR64.8B); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.339 TBL page C7-2801 line 163652 MATCH x0e000000/mask=xbfe09c00 +# C7.2.340 TBX page C7-2803 line 163781 MATCH x0e001000/mask=xbfe09c00 +# CONSTRUCT x4e006000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B Rnnnn_VPR128.16B ARG6 =a64_TBL/6 +# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B Rnnnn_VPR128.16B ARG6 =NEON_tblx/6 +# AUNIT --inst x4e006000/mask=xffe0ec00 --status pass +# Q == 1 && len == 11 16B, Four register table variant + +:^tblx Rd_VPR128.16B, "{"^Rn_VPR128.16B^", "^Rnn_VPR128.16B^", "^Rnnn_VPR128.16B^", "^Rnnnn_VPR128.16B^"}", Rm_VPR128.16B +is b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=1 & b_1314=0b11 & Rm_VPR128.16B & Rn_VPR128.16B & Rnn_VPR128.16B & Rnnn_VPR128.16B & Rnnnn_VPR128.16B & Rd_VPR128.16B & tblx & Zd +{ + Rd_VPR128.16B = a64_TBL(tblx, Rn_VPR128.16B, Rnn_VPR128.16B, Rnnn_VPR128.16B, Rnnnn_VPR128.16B, Rm_VPR128.16B); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.341 TRN1 page C7-2805 line 163910 MATCH x0e002800/mask=xbf20fc00 +# CONSTRUCT x4e002800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-2@4-4@6-6@8-8@10-10@12-12@14-14:1 swap &=$shuffle@0-1@2-3@4-5@6-7@8-9@10-11@12-13@14-15:1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@1 +# AUNIT --inst x4e002800/mask=xffe0fc00 --status pass + +:trn1 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + TMPQ2 = Rm_VPR128.16B; + TMPQ1 = Rn_VPR128.16B; + # simd shuffle Rd_VPR128.16B = TMPQ1 (@0-0@2-2@4-4@6-6@8-8@10-10@12-12@14-14) lane size 1 + Rd_VPR128.16B[0,8] = TMPQ1[0,8]; + Rd_VPR128.16B[16,8] = TMPQ1[16,8]; + Rd_VPR128.16B[32,8] = TMPQ1[32,8]; + Rd_VPR128.16B[48,8] = TMPQ1[48,8]; + Rd_VPR128.16B[64,8] = TMPQ1[64,8]; + Rd_VPR128.16B[80,8] = TMPQ1[80,8]; + Rd_VPR128.16B[96,8] = TMPQ1[96,8]; + Rd_VPR128.16B[112,8] = TMPQ1[112,8]; + # simd shuffle Rd_VPR128.16B = TMPQ2 (@0-1@2-3@4-5@6-7@8-9@10-11@12-13@14-15) lane size 1 + Rd_VPR128.16B[8,8] = TMPQ2[0,8]; + Rd_VPR128.16B[24,8] = TMPQ2[16,8]; + Rd_VPR128.16B[40,8] = TMPQ2[32,8]; + Rd_VPR128.16B[56,8] = TMPQ2[48,8]; + Rd_VPR128.16B[72,8] = TMPQ2[64,8]; + Rd_VPR128.16B[88,8] = TMPQ2[80,8]; + Rd_VPR128.16B[104,8] = TMPQ2[96,8]; + Rd_VPR128.16B[120,8] = TMPQ2[112,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.341 TRN1 page C7-2805 line 163910 MATCH x0e002800/mask=xbf20fc00 +# CONSTRUCT x4ec02800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0:8 swap &=$shuffle@0-1:8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@8 +# AUNIT --inst x4ec02800/mask=xffe0fc00 --status pass + +:trn1 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=3 & b_2121=0 & Rm_VPR128.2D & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + TMPQ2 = Rm_VPR128.2D; + TMPQ1 = Rn_VPR128.2D; + # simd shuffle Rd_VPR128.2D = TMPQ1 (@0-0) lane size 8 + Rd_VPR128.2D[0,64] = TMPQ1[0,64]; + # simd shuffle Rd_VPR128.2D = TMPQ2 (@0-1) lane size 8 + Rd_VPR128.2D[64,64] = TMPQ2[0,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.341 TRN1 page C7-2805 line 163910 MATCH x0e002800/mask=xbf20fc00 +# CONSTRUCT x0e802800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0:4 swap &=$shuffle@0-1:4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@4 +# AUNIT --inst x0e802800/mask=xffe0fc00 --status pass + +:trn1 Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR64.2S & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + TMPD2 = Rm_VPR64.2S; + TMPD1 = Rn_VPR64.2S; + # simd shuffle Rd_VPR64.2S = TMPD1 (@0-0) lane size 4 + Rd_VPR64.2S[0,32] = TMPD1[0,32]; + # simd shuffle Rd_VPR64.2S = TMPD2 (@0-1) lane size 4 + Rd_VPR64.2S[32,32] = TMPD2[0,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.341 TRN1 page C7-2805 line 163910 MATCH x0e002800/mask=xbf20fc00 +# CONSTRUCT x0e402800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-2:2 swap &=$shuffle@0-1@2-3:2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@2 +# AUNIT --inst x0e402800/mask=xffe0fc00 --status pass + +:trn1 Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR64.4H & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + TMPD2 = Rm_VPR64.4H; + TMPD1 = Rn_VPR64.4H; + # simd shuffle Rd_VPR64.4H = TMPD1 (@0-0@2-2) lane size 2 + Rd_VPR64.4H[0,16] = TMPD1[0,16]; + Rd_VPR64.4H[32,16] = TMPD1[32,16]; + # simd shuffle Rd_VPR64.4H = TMPD2 (@0-1@2-3) lane size 2 + Rd_VPR64.4H[16,16] = TMPD2[0,16]; + Rd_VPR64.4H[48,16] = TMPD2[32,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.341 TRN1 page C7-2805 line 163910 MATCH x0e002800/mask=xbf20fc00 +# CONSTRUCT x4e802800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-2:4 swap &=$shuffle@0-1@2-3:4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@4 +# AUNIT --inst x4e802800/mask=xffe0fc00 --status pass + +:trn1 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR128.4S & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + TMPQ2 = Rm_VPR128.4S; + TMPQ1 = Rn_VPR128.4S; + # simd shuffle Rd_VPR128.4S = TMPQ1 (@0-0@2-2) lane size 4 + Rd_VPR128.4S[0,32] = TMPQ1[0,32]; + Rd_VPR128.4S[64,32] = TMPQ1[64,32]; + # simd shuffle Rd_VPR128.4S = TMPQ2 (@0-1@2-3) lane size 4 + Rd_VPR128.4S[32,32] = TMPQ2[0,32]; + Rd_VPR128.4S[96,32] = TMPQ2[64,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.341 TRN1 page C7-2805 line 163910 MATCH x0e002800/mask=xbf20fc00 +# CONSTRUCT x0e002800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-2@4-4@6-6:1 swap &=$shuffle@0-1@2-3@4-5@6-7:1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@1 +# AUNIT --inst x0e002800/mask=xffe0fc00 --status pass + +:trn1 Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR64.8B & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + TMPD2 = Rm_VPR64.8B; + TMPD1 = Rn_VPR64.8B; + # simd shuffle Rd_VPR64.8B = TMPD1 (@0-0@2-2@4-4@6-6) lane size 1 + Rd_VPR64.8B[0,8] = TMPD1[0,8]; + Rd_VPR64.8B[16,8] = TMPD1[16,8]; + Rd_VPR64.8B[32,8] = TMPD1[32,8]; + Rd_VPR64.8B[48,8] = TMPD1[48,8]; + # simd shuffle Rd_VPR64.8B = TMPD2 (@0-1@2-3@4-5@6-7) lane size 1 + Rd_VPR64.8B[8,8] = TMPD2[0,8]; + Rd_VPR64.8B[24,8] = TMPD2[16,8]; + Rd_VPR64.8B[40,8] = TMPD2[32,8]; + Rd_VPR64.8B[56,8] = TMPD2[48,8]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.341 TRN1 page C7-2805 line 163910 MATCH x0e002800/mask=xbf20fc00 +# CONSTRUCT x4e402800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-2@4-4@6-6:2 swap &=$shuffle@0-1@2-3@4-5@6-7:2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@2 +# AUNIT --inst x4e402800/mask=xffe0fc00 --status pass + +:trn1 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR128.8H & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + TMPQ2 = Rm_VPR128.8H; + TMPQ1 = Rn_VPR128.8H; + # simd shuffle Rd_VPR128.8H = TMPQ1 (@0-0@2-2@4-4@6-6) lane size 2 + Rd_VPR128.8H[0,16] = TMPQ1[0,16]; + Rd_VPR128.8H[32,16] = TMPQ1[32,16]; + Rd_VPR128.8H[64,16] = TMPQ1[64,16]; + Rd_VPR128.8H[96,16] = TMPQ1[96,16]; + # simd shuffle Rd_VPR128.8H = TMPQ2 (@0-1@2-3@4-5@6-7) lane size 2 + Rd_VPR128.8H[16,16] = TMPQ2[0,16]; + Rd_VPR128.8H[48,16] = TMPQ2[32,16]; + Rd_VPR128.8H[80,16] = TMPQ2[64,16]; + Rd_VPR128.8H[112,16] = TMPQ2[96,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.342 TRN2 page C7-2807 line 164028 MATCH x0e006800/mask=xbf20fc00 +# CONSTRUCT x4e006800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-2@5-4@7-6@9-8@11-10@13-12@15-14:1 swap &=$shuffle@1-1@3-3@5-5@7-7@9-9@11-11@13-13@15-15:1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@1 +# AUNIT --inst x4e006800/mask=xffe0fc00 --status pass + +:trn2 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + TMPQ2 = Rm_VPR128.16B; + TMPQ1 = Rn_VPR128.16B; + # simd shuffle Rd_VPR128.16B = TMPQ1 (@1-0@3-2@5-4@7-6@9-8@11-10@13-12@15-14) lane size 1 + Rd_VPR128.16B[0,8] = TMPQ1[8,8]; + Rd_VPR128.16B[16,8] = TMPQ1[24,8]; + Rd_VPR128.16B[32,8] = TMPQ1[40,8]; + Rd_VPR128.16B[48,8] = TMPQ1[56,8]; + Rd_VPR128.16B[64,8] = TMPQ1[72,8]; + Rd_VPR128.16B[80,8] = TMPQ1[88,8]; + Rd_VPR128.16B[96,8] = TMPQ1[104,8]; + Rd_VPR128.16B[112,8] = TMPQ1[120,8]; + # simd shuffle Rd_VPR128.16B = TMPQ2 (@1-1@3-3@5-5@7-7@9-9@11-11@13-13@15-15) lane size 1 + Rd_VPR128.16B[8,8] = TMPQ2[8,8]; + Rd_VPR128.16B[24,8] = TMPQ2[24,8]; + Rd_VPR128.16B[40,8] = TMPQ2[40,8]; + Rd_VPR128.16B[56,8] = TMPQ2[56,8]; + Rd_VPR128.16B[72,8] = TMPQ2[72,8]; + Rd_VPR128.16B[88,8] = TMPQ2[88,8]; + Rd_VPR128.16B[104,8] = TMPQ2[104,8]; + Rd_VPR128.16B[120,8] = TMPQ2[120,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.342 TRN2 page C7-2807 line 164028 MATCH x0e006800/mask=xbf20fc00 +# CONSTRUCT x4ec06800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0:8 swap &=$shuffle@1-1:8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@8 +# AUNIT --inst x4ec06800/mask=xffe0fc00 --status pass + +:trn2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=3 & b_2121=0 & Rm_VPR128.2D & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + TMPQ2 = Rm_VPR128.2D; + TMPQ1 = Rn_VPR128.2D; + # simd shuffle Rd_VPR128.2D = TMPQ1 (@1-0) lane size 8 + Rd_VPR128.2D[0,64] = TMPQ1[64,64]; + # simd shuffle Rd_VPR128.2D = TMPQ2 (@1-1) lane size 8 + Rd_VPR128.2D[64,64] = TMPQ2[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.342 TRN2 page C7-2807 line 164028 MATCH x0e006800/mask=xbf20fc00 +# CONSTRUCT x0e806800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0:4 swap &=$shuffle@1-1:4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@4 +# AUNIT --inst x0e806800/mask=xffe0fc00 --status pass + +:trn2 Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR64.2S & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + TMPD2 = Rm_VPR64.2S; + TMPD1 = Rn_VPR64.2S; + # simd shuffle Rd_VPR64.2S = TMPD1 (@1-0) lane size 4 + Rd_VPR64.2S[0,32] = TMPD1[32,32]; + # simd shuffle Rd_VPR64.2S = TMPD2 (@1-1) lane size 4 + Rd_VPR64.2S[32,32] = TMPD2[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.342 TRN2 page C7-2807 line 164028 MATCH x0e006800/mask=xbf20fc00 +# CONSTRUCT x0e406800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-2:2 swap &=$shuffle@1-1@3-3:2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@2 +# AUNIT --inst x0e406800/mask=xffe0fc00 --status pass + +:trn2 Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR64.4H & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + TMPD2 = Rm_VPR64.4H; + TMPD1 = Rn_VPR64.4H; + # simd shuffle Rd_VPR64.4H = TMPD1 (@1-0@3-2) lane size 2 + Rd_VPR64.4H[0,16] = TMPD1[16,16]; + Rd_VPR64.4H[32,16] = TMPD1[48,16]; + # simd shuffle Rd_VPR64.4H = TMPD2 (@1-1@3-3) lane size 2 + Rd_VPR64.4H[16,16] = TMPD2[16,16]; + Rd_VPR64.4H[48,16] = TMPD2[48,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.342 TRN2 page C7-2807 line 164028 MATCH x0e006800/mask=xbf20fc00 +# CONSTRUCT x4e806800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-2:4 swap &=$shuffle@1-1@3-3:4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@4 +# AUNIT --inst x4e806800/mask=xffe0fc00 --status pass + +:trn2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR128.4S & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + TMPQ2 = Rm_VPR128.4S; + TMPQ1 = Rn_VPR128.4S; + # simd shuffle Rd_VPR128.4S = TMPQ1 (@1-0@3-2) lane size 4 + Rd_VPR128.4S[0,32] = TMPQ1[32,32]; + Rd_VPR128.4S[64,32] = TMPQ1[96,32]; + # simd shuffle Rd_VPR128.4S = TMPQ2 (@1-1@3-3) lane size 4 + Rd_VPR128.4S[32,32] = TMPQ2[32,32]; + Rd_VPR128.4S[96,32] = TMPQ2[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.342 TRN2 page C7-2807 line 164028 MATCH x0e006800/mask=xbf20fc00 +# CONSTRUCT x0e006800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-2@5-4@7-6:1 swap &=$shuffle@1-1@3-3@5-5@7-7:1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@1 +# AUNIT --inst x0e006800/mask=xffe0fc00 --status pass + +:trn2 Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR64.8B & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + TMPD2 = Rm_VPR64.8B; + TMPD1 = Rn_VPR64.8B; + # simd shuffle Rd_VPR64.8B = TMPD1 (@1-0@3-2@5-4@7-6) lane size 1 + Rd_VPR64.8B[0,8] = TMPD1[8,8]; + Rd_VPR64.8B[16,8] = TMPD1[24,8]; + Rd_VPR64.8B[32,8] = TMPD1[40,8]; + Rd_VPR64.8B[48,8] = TMPD1[56,8]; + # simd shuffle Rd_VPR64.8B = TMPD2 (@1-1@3-3@5-5@7-7) lane size 1 + Rd_VPR64.8B[8,8] = TMPD2[8,8]; + Rd_VPR64.8B[24,8] = TMPD2[24,8]; + Rd_VPR64.8B[40,8] = TMPD2[40,8]; + Rd_VPR64.8B[56,8] = TMPD2[56,8]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.342 TRN2 page C7-2807 line 164028 MATCH x0e006800/mask=xbf20fc00 +# CONSTRUCT x4e406800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-2@5-4@7-6:2 swap &=$shuffle@1-1@3-3@5-5@7-7:2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@2 +# AUNIT --inst x4e406800/mask=xffe0fc00 --status pass + +:trn2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR128.8H & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + TMPQ2 = Rm_VPR128.8H; + TMPQ1 = Rn_VPR128.8H; + # simd shuffle Rd_VPR128.8H = TMPQ1 (@1-0@3-2@5-4@7-6) lane size 2 + Rd_VPR128.8H[0,16] = TMPQ1[16,16]; + Rd_VPR128.8H[32,16] = TMPQ1[48,16]; + Rd_VPR128.8H[64,16] = TMPQ1[80,16]; + Rd_VPR128.8H[96,16] = TMPQ1[112,16]; + # simd shuffle Rd_VPR128.8H = TMPQ2 (@1-1@3-3@5-5@7-7) lane size 2 + Rd_VPR128.8H[16,16] = TMPQ2[16,16]; + Rd_VPR128.8H[48,16] = TMPQ2[48,16]; + Rd_VPR128.8H[80,16] = TMPQ2[80,16]; + Rd_VPR128.8H[112,16] = TMPQ2[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.343 UABA page C7-2809 line 164146 MATCH x2e207c00/mask=xbf20fc00 +# CONSTRUCT x6e207c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uaba/3@1 +# AUNIT --inst x6e207c00/mask=xffe0fc00 --status nopcodeop --comment "abd" + +:uaba Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xf & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_uaba(Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.343 UABA page C7-2809 line 164146 MATCH x2e207c00/mask=xbf20fc00 +# CONSTRUCT x2ea07c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uaba/3@4 +# AUNIT --inst x2ea07c00/mask=xffe0fc00 --status nopcodeop --comment "abd" + +:uaba Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xf & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_uaba(Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.343 UABA page C7-2809 line 164146 MATCH x2e207c00/mask=xbf20fc00 +# CONSTRUCT x2e607c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uaba/3@2 +# AUNIT --inst x2e607c00/mask=xffe0fc00 --status nopcodeop --comment "abd" + +:uaba Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xf & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_uaba(Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.343 UABA page C7-2809 line 164146 MATCH x2e207c00/mask=xbf20fc00 +# CONSTRUCT x6ea07c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uaba/3@4 +# AUNIT --inst x6ea07c00/mask=xffe0fc00 --status nopcodeop --comment "abd" + +:uaba Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xf & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_uaba(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.343 UABA page C7-2809 line 164146 MATCH x2e207c00/mask=xbf20fc00 +# CONSTRUCT x2e207c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uaba/3@1 +# AUNIT --inst x2e207c00/mask=xffe0fc00 --status nopcodeop --comment "abd" + +:uaba Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xf & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_uaba(Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.343 UABA page C7-2809 line 164146 MATCH x2e207c00/mask=xbf20fc00 +# CONSTRUCT x6e607c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uaba/3@2 +# AUNIT --inst x6e607c00/mask=xffe0fc00 --status nopcodeop --comment "abd" + +:uaba Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xf & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_uaba(Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.344 UABAL, UABAL2 page C7-2811 line 164248 MATCH x2e205000/mask=xbf20fc00 +# CONSTRUCT x6ea05000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 $-@8 $abs@8 &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uabal2/3@4 +# AUNIT --inst x6ea05000/mask=xffe0fc00 --status pass --comment "ext abd" + +:uabal2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x5 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = zext(TMPD1[0,32]); + TMPQ2[64,64] = zext(TMPD1[32,32]); + TMPD3 = Rm_VPR128.4S[64,64]; + # simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8) + TMPQ4[0,64] = zext(TMPD3[0,32]); + TMPQ4[64,64] = zext(TMPD3[32,32]); + # simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 8 + TMPQ5[0,64] = TMPQ2[0,64] - TMPQ4[0,64]; + TMPQ5[64,64] = TMPQ2[64,64] - TMPQ4[64,64]; + # simd unary TMPQ6 = MP_INT_ABS(TMPQ5) on lane size 8 + TMPQ6[0,64] = MP_INT_ABS(TMPQ5[0,64]); + TMPQ6[64,64] = MP_INT_ABS(TMPQ5[64,64]); + # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ6 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ6[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ6[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.344 UABAL, UABAL2 page C7-2811 line 164248 MATCH x2e205000/mask=xbf20fc00 +# CONSTRUCT x6e605000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 $-@4 $abs@4 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uabal2/3@2 +# AUNIT --inst x6e605000/mask=xffe0fc00 --status pass --comment "ext abd" + +:uabal2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x5 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = zext(TMPD1[0,16]); + TMPQ2[32,32] = zext(TMPD1[16,16]); + TMPQ2[64,32] = zext(TMPD1[32,16]); + TMPQ2[96,32] = zext(TMPD1[48,16]); + TMPD3 = Rm_VPR128.8H[64,64]; + # simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4) + TMPQ4[0,32] = zext(TMPD3[0,16]); + TMPQ4[32,32] = zext(TMPD3[16,16]); + TMPQ4[64,32] = zext(TMPD3[32,16]); + TMPQ4[96,32] = zext(TMPD3[48,16]); + # simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 4 + TMPQ5[0,32] = TMPQ2[0,32] - TMPQ4[0,32]; + TMPQ5[32,32] = TMPQ2[32,32] - TMPQ4[32,32]; + TMPQ5[64,32] = TMPQ2[64,32] - TMPQ4[64,32]; + TMPQ5[96,32] = TMPQ2[96,32] - TMPQ4[96,32]; + # simd unary TMPQ6 = MP_INT_ABS(TMPQ5) on lane size 4 + TMPQ6[0,32] = MP_INT_ABS(TMPQ5[0,32]); + TMPQ6[32,32] = MP_INT_ABS(TMPQ5[32,32]); + TMPQ6[64,32] = MP_INT_ABS(TMPQ5[64,32]); + TMPQ6[96,32] = MP_INT_ABS(TMPQ5[96,32]); + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ6 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ6[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ6[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ6[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ6[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.344 UABAL, UABAL2 page C7-2811 line 164248 MATCH x2e205000/mask=xbf20fc00 +# CONSTRUCT x6e205000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 $-@2 $abs@2 &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uabal2/3@1 +# AUNIT --inst x6e205000/mask=xffe0fc00 --status pass --comment "ext abd" + +:uabal2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x5 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd +{ + TMPD1 = Rn_VPR128.16B[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2) + TMPQ2[0,16] = zext(TMPD1[0,8]); + TMPQ2[16,16] = zext(TMPD1[8,8]); + TMPQ2[32,16] = zext(TMPD1[16,8]); + TMPQ2[48,16] = zext(TMPD1[24,8]); + TMPQ2[64,16] = zext(TMPD1[32,8]); + TMPQ2[80,16] = zext(TMPD1[40,8]); + TMPQ2[96,16] = zext(TMPD1[48,8]); + TMPQ2[112,16] = zext(TMPD1[56,8]); + TMPD3 = Rm_VPR128.16B[64,64]; + # simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2) + TMPQ4[0,16] = zext(TMPD3[0,8]); + TMPQ4[16,16] = zext(TMPD3[8,8]); + TMPQ4[32,16] = zext(TMPD3[16,8]); + TMPQ4[48,16] = zext(TMPD3[24,8]); + TMPQ4[64,16] = zext(TMPD3[32,8]); + TMPQ4[80,16] = zext(TMPD3[40,8]); + TMPQ4[96,16] = zext(TMPD3[48,8]); + TMPQ4[112,16] = zext(TMPD3[56,8]); + # simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 2 + TMPQ5[0,16] = TMPQ2[0,16] - TMPQ4[0,16]; + TMPQ5[16,16] = TMPQ2[16,16] - TMPQ4[16,16]; + TMPQ5[32,16] = TMPQ2[32,16] - TMPQ4[32,16]; + TMPQ5[48,16] = TMPQ2[48,16] - TMPQ4[48,16]; + TMPQ5[64,16] = TMPQ2[64,16] - TMPQ4[64,16]; + TMPQ5[80,16] = TMPQ2[80,16] - TMPQ4[80,16]; + TMPQ5[96,16] = TMPQ2[96,16] - TMPQ4[96,16]; + TMPQ5[112,16] = TMPQ2[112,16] - TMPQ4[112,16]; + # simd unary TMPQ6 = MP_INT_ABS(TMPQ5) on lane size 2 + TMPQ6[0,16] = MP_INT_ABS(TMPQ5[0,16]); + TMPQ6[16,16] = MP_INT_ABS(TMPQ5[16,16]); + TMPQ6[32,16] = MP_INT_ABS(TMPQ5[32,16]); + TMPQ6[48,16] = MP_INT_ABS(TMPQ5[48,16]); + TMPQ6[64,16] = MP_INT_ABS(TMPQ5[64,16]); + TMPQ6[80,16] = MP_INT_ABS(TMPQ5[80,16]); + TMPQ6[96,16] = MP_INT_ABS(TMPQ5[96,16]); + TMPQ6[112,16] = MP_INT_ABS(TMPQ5[112,16]); + # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ6 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ6[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ6[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ6[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ6[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ6[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ6[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ6[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ6[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.344 UABAL, UABAL2 page C7-2811 line 164248 MATCH x2e205000/mask=xbf20fc00 +# CONSTRUCT x2ea05000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@4:16 ARG3 $zext@4:16 $-@8 $abs@8 &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uabal/3@4 +# AUNIT --inst x2ea05000/mask=xffe0fc00 --status pass --comment "ext abd" + +:uabal Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x5 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]); + # simd resize TMPQ2 = zext(Rm_VPR64.2S) (lane size 4 to 8) + TMPQ2[0,64] = zext(Rm_VPR64.2S[0,32]); + TMPQ2[64,64] = zext(Rm_VPR64.2S[32,32]); + # simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 8 + TMPQ3[0,64] = TMPQ1[0,64] - TMPQ2[0,64]; + TMPQ3[64,64] = TMPQ1[64,64] - TMPQ2[64,64]; + # simd unary TMPQ4 = MP_INT_ABS(TMPQ3) on lane size 8 + TMPQ4[0,64] = MP_INT_ABS(TMPQ3[0,64]); + TMPQ4[64,64] = MP_INT_ABS(TMPQ3[64,64]); + # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ4 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ4[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ4[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.344 UABAL, UABAL2 page C7-2811 line 164248 MATCH x2e205000/mask=xbf20fc00 +# CONSTRUCT x2e605000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@2:16 ARG3 $zext@2:16 $-@4 $abs@4 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uabal/3@2 +# AUNIT --inst x2e605000/mask=xffe0fc00 --status pass --comment "ext abd" + +:uabal Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x5 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]); + # simd resize TMPQ2 = zext(Rm_VPR64.4H) (lane size 2 to 4) + TMPQ2[0,32] = zext(Rm_VPR64.4H[0,16]); + TMPQ2[32,32] = zext(Rm_VPR64.4H[16,16]); + TMPQ2[64,32] = zext(Rm_VPR64.4H[32,16]); + TMPQ2[96,32] = zext(Rm_VPR64.4H[48,16]); + # simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 4 + TMPQ3[0,32] = TMPQ1[0,32] - TMPQ2[0,32]; + TMPQ3[32,32] = TMPQ1[32,32] - TMPQ2[32,32]; + TMPQ3[64,32] = TMPQ1[64,32] - TMPQ2[64,32]; + TMPQ3[96,32] = TMPQ1[96,32] - TMPQ2[96,32]; + # simd unary TMPQ4 = MP_INT_ABS(TMPQ3) on lane size 4 + TMPQ4[0,32] = MP_INT_ABS(TMPQ3[0,32]); + TMPQ4[32,32] = MP_INT_ABS(TMPQ3[32,32]); + TMPQ4[64,32] = MP_INT_ABS(TMPQ3[64,32]); + TMPQ4[96,32] = MP_INT_ABS(TMPQ3[96,32]); + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ4 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ4[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ4[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ4[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ4[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.344 UABAL, UABAL2 page C7-2811 line 164248 MATCH x2e205000/mask=xbf20fc00 +# CONSTRUCT x2e205000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@1:16 ARG3 $zext@1:16 $-@2 $abs@2 &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uabal/3@1 +# AUNIT --inst x2e205000/mask=xffe0fc00 --status pass --comment "ext abd" + +:uabal Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x5 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2) + TMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]); + TMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]); + TMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]); + TMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]); + TMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]); + TMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]); + TMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]); + TMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]); + # simd resize TMPQ2 = zext(Rm_VPR64.8B) (lane size 1 to 2) + TMPQ2[0,16] = zext(Rm_VPR64.8B[0,8]); + TMPQ2[16,16] = zext(Rm_VPR64.8B[8,8]); + TMPQ2[32,16] = zext(Rm_VPR64.8B[16,8]); + TMPQ2[48,16] = zext(Rm_VPR64.8B[24,8]); + TMPQ2[64,16] = zext(Rm_VPR64.8B[32,8]); + TMPQ2[80,16] = zext(Rm_VPR64.8B[40,8]); + TMPQ2[96,16] = zext(Rm_VPR64.8B[48,8]); + TMPQ2[112,16] = zext(Rm_VPR64.8B[56,8]); + # simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 2 + TMPQ3[0,16] = TMPQ1[0,16] - TMPQ2[0,16]; + TMPQ3[16,16] = TMPQ1[16,16] - TMPQ2[16,16]; + TMPQ3[32,16] = TMPQ1[32,16] - TMPQ2[32,16]; + TMPQ3[48,16] = TMPQ1[48,16] - TMPQ2[48,16]; + TMPQ3[64,16] = TMPQ1[64,16] - TMPQ2[64,16]; + TMPQ3[80,16] = TMPQ1[80,16] - TMPQ2[80,16]; + TMPQ3[96,16] = TMPQ1[96,16] - TMPQ2[96,16]; + TMPQ3[112,16] = TMPQ1[112,16] - TMPQ2[112,16]; + # simd unary TMPQ4 = MP_INT_ABS(TMPQ3) on lane size 2 + TMPQ4[0,16] = MP_INT_ABS(TMPQ3[0,16]); + TMPQ4[16,16] = MP_INT_ABS(TMPQ3[16,16]); + TMPQ4[32,16] = MP_INT_ABS(TMPQ3[32,16]); + TMPQ4[48,16] = MP_INT_ABS(TMPQ3[48,16]); + TMPQ4[64,16] = MP_INT_ABS(TMPQ3[64,16]); + TMPQ4[80,16] = MP_INT_ABS(TMPQ3[80,16]); + TMPQ4[96,16] = MP_INT_ABS(TMPQ3[96,16]); + TMPQ4[112,16] = MP_INT_ABS(TMPQ3[112,16]); + # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ4 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ4[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ4[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ4[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ4[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ4[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ4[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ4[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ4[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.345 UABD page C7-2813 line 164369 MATCH x2e207400/mask=xbf20fc00 +# CONSTRUCT x6e207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabd/2@1 +# AUNIT --inst x6e207400/mask=xffe0fc00 --status nopcodeop --comment "abd" + +:uabd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xe & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_uabd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.345 UABD page C7-2813 line 164369 MATCH x2e207400/mask=xbf20fc00 +# CONSTRUCT x2ea07400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $-@4 ARG3 ARG2 $-@4 2:4 &=$* ARG2 ARG3 $less@4 &=$*@4 =$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabd/2@4 +# AUNIT --inst x2ea07400/mask=xffe0fc00 --status pass --comment "abd" +# This abd instruction is implemented correctly to document a correct +# way to implement the unsigned absolute difference semantic. + +:uabd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xe & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + # simd infix TMPD1 = Rn_VPR64.2S - Rm_VPR64.2S on lane size 4 + TMPD1[0,32] = Rn_VPR64.2S[0,32] - Rm_VPR64.2S[0,32]; + TMPD1[32,32] = Rn_VPR64.2S[32,32] - Rm_VPR64.2S[32,32]; + # simd infix TMPD2 = Rm_VPR64.2S - Rn_VPR64.2S on lane size 4 + TMPD2[0,32] = Rm_VPR64.2S[0,32] - Rn_VPR64.2S[0,32]; + TMPD2[32,32] = Rm_VPR64.2S[32,32] - Rn_VPR64.2S[32,32]; + # simd infix TMPD2 = TMPD2 * 2:4 on lane size 4 + TMPD2[0,32] = TMPD2[0,32] * 2:4; + TMPD2[32,32] = TMPD2[32,32] * 2:4; + # simd infix TMPD3 = Rn_VPR64.2S < Rm_VPR64.2S on lane size 4 + TMPD3[0,32] = zext(Rn_VPR64.2S[0,32] < Rm_VPR64.2S[0,32]); + TMPD3[32,32] = zext(Rn_VPR64.2S[32,32] < Rm_VPR64.2S[32,32]); + # simd infix TMPD2 = TMPD2 * TMPD3 on lane size 4 + TMPD2[0,32] = TMPD2[0,32] * TMPD3[0,32]; + TMPD2[32,32] = TMPD2[32,32] * TMPD3[32,32]; + # simd infix Rd_VPR64.2S = TMPD1 + TMPD2 on lane size 4 + Rd_VPR64.2S[0,32] = TMPD1[0,32] + TMPD2[0,32]; + Rd_VPR64.2S[32,32] = TMPD1[32,32] + TMPD2[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.345 UABD page C7-2813 line 164369 MATCH x2e207400/mask=xbf20fc00 +# CONSTRUCT x2e607400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabd/2@2 +# AUNIT --inst x2e607400/mask=xffe0fc00 --status nopcodeop --comment "abd" + +:uabd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xe & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_uabd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.345 UABD page C7-2813 line 164369 MATCH x2e207400/mask=xbf20fc00 +# CONSTRUCT x6ea07400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabd/2@4 +# AUNIT --inst x6ea07400/mask=xffe0fc00 --status nopcodeop --comment "abd" + +:uabd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xe & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_uabd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.345 UABD page C7-2813 line 164369 MATCH x2e207400/mask=xbf20fc00 +# CONSTRUCT x2e207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabd/2@1 +# AUNIT --inst x2e207400/mask=xffe0fc00 --status nopcodeop --comment "abd" + +:uabd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xe & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_uabd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.345 UABD page C7-2813 line 164369 MATCH x2e207400/mask=xbf20fc00 +# CONSTRUCT x6e607400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabd/2@2 +# AUNIT --inst x6e607400/mask=xffe0fc00 --status nopcodeop --comment "abd" + +:uabd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xe & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_uabd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.346 UABDL, UABDL2 page C7-2815 line 164471 MATCH x2e207000/mask=xbf20fc00 +# CONSTRUCT x6ea07000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 $-@8 =$abs@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabdl2/2@4 +# AUNIT --inst x6ea07000/mask=xffe0fc00 --status pass --comment "ext abd" + +:uabdl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x7 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = zext(TMPD1[0,32]); + TMPQ2[64,64] = zext(TMPD1[32,32]); + TMPD3 = Rm_VPR128.4S[64,64]; + # simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8) + TMPQ4[0,64] = zext(TMPD3[0,32]); + TMPQ4[64,64] = zext(TMPD3[32,32]); + # simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 8 + TMPQ5[0,64] = TMPQ2[0,64] - TMPQ4[0,64]; + TMPQ5[64,64] = TMPQ2[64,64] - TMPQ4[64,64]; + # simd unary Rd_VPR128.2D = MP_INT_ABS(TMPQ5) on lane size 8 + Rd_VPR128.2D[0,64] = MP_INT_ABS(TMPQ5[0,64]); + Rd_VPR128.2D[64,64] = MP_INT_ABS(TMPQ5[64,64]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.346 UABDL, UABDL2 page C7-2815 line 164471 MATCH x2e207000/mask=xbf20fc00 +# CONSTRUCT x6e607000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 $-@4 =$abs@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabdl2/2@2 +# AUNIT --inst x6e607000/mask=xffe0fc00 --status pass --comment "ext abd" + +:uabdl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x7 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = zext(TMPD1[0,16]); + TMPQ2[32,32] = zext(TMPD1[16,16]); + TMPQ2[64,32] = zext(TMPD1[32,16]); + TMPQ2[96,32] = zext(TMPD1[48,16]); + TMPD3 = Rm_VPR128.8H[64,64]; + # simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4) + TMPQ4[0,32] = zext(TMPD3[0,16]); + TMPQ4[32,32] = zext(TMPD3[16,16]); + TMPQ4[64,32] = zext(TMPD3[32,16]); + TMPQ4[96,32] = zext(TMPD3[48,16]); + # simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 4 + TMPQ5[0,32] = TMPQ2[0,32] - TMPQ4[0,32]; + TMPQ5[32,32] = TMPQ2[32,32] - TMPQ4[32,32]; + TMPQ5[64,32] = TMPQ2[64,32] - TMPQ4[64,32]; + TMPQ5[96,32] = TMPQ2[96,32] - TMPQ4[96,32]; + # simd unary Rd_VPR128.4S = MP_INT_ABS(TMPQ5) on lane size 4 + Rd_VPR128.4S[0,32] = MP_INT_ABS(TMPQ5[0,32]); + Rd_VPR128.4S[32,32] = MP_INT_ABS(TMPQ5[32,32]); + Rd_VPR128.4S[64,32] = MP_INT_ABS(TMPQ5[64,32]); + Rd_VPR128.4S[96,32] = MP_INT_ABS(TMPQ5[96,32]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.346 UABDL, UABDL2 page C7-2815 line 164471 MATCH x2e207000/mask=xbf20fc00 +# CONSTRUCT x6e207000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 $-@2 =$abs@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabdl2/2@1 +# AUNIT --inst x6e207000/mask=xffe0fc00 --status pass --comment "ext abd" + +:uabdl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x7 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd +{ + TMPD1 = Rn_VPR128.16B[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2) + TMPQ2[0,16] = zext(TMPD1[0,8]); + TMPQ2[16,16] = zext(TMPD1[8,8]); + TMPQ2[32,16] = zext(TMPD1[16,8]); + TMPQ2[48,16] = zext(TMPD1[24,8]); + TMPQ2[64,16] = zext(TMPD1[32,8]); + TMPQ2[80,16] = zext(TMPD1[40,8]); + TMPQ2[96,16] = zext(TMPD1[48,8]); + TMPQ2[112,16] = zext(TMPD1[56,8]); + TMPD3 = Rm_VPR128.16B[64,64]; + # simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2) + TMPQ4[0,16] = zext(TMPD3[0,8]); + TMPQ4[16,16] = zext(TMPD3[8,8]); + TMPQ4[32,16] = zext(TMPD3[16,8]); + TMPQ4[48,16] = zext(TMPD3[24,8]); + TMPQ4[64,16] = zext(TMPD3[32,8]); + TMPQ4[80,16] = zext(TMPD3[40,8]); + TMPQ4[96,16] = zext(TMPD3[48,8]); + TMPQ4[112,16] = zext(TMPD3[56,8]); + # simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 2 + TMPQ5[0,16] = TMPQ2[0,16] - TMPQ4[0,16]; + TMPQ5[16,16] = TMPQ2[16,16] - TMPQ4[16,16]; + TMPQ5[32,16] = TMPQ2[32,16] - TMPQ4[32,16]; + TMPQ5[48,16] = TMPQ2[48,16] - TMPQ4[48,16]; + TMPQ5[64,16] = TMPQ2[64,16] - TMPQ4[64,16]; + TMPQ5[80,16] = TMPQ2[80,16] - TMPQ4[80,16]; + TMPQ5[96,16] = TMPQ2[96,16] - TMPQ4[96,16]; + TMPQ5[112,16] = TMPQ2[112,16] - TMPQ4[112,16]; + # simd unary Rd_VPR128.8H = MP_INT_ABS(TMPQ5) on lane size 2 + Rd_VPR128.8H[0,16] = MP_INT_ABS(TMPQ5[0,16]); + Rd_VPR128.8H[16,16] = MP_INT_ABS(TMPQ5[16,16]); + Rd_VPR128.8H[32,16] = MP_INT_ABS(TMPQ5[32,16]); + Rd_VPR128.8H[48,16] = MP_INT_ABS(TMPQ5[48,16]); + Rd_VPR128.8H[64,16] = MP_INT_ABS(TMPQ5[64,16]); + Rd_VPR128.8H[80,16] = MP_INT_ABS(TMPQ5[80,16]); + Rd_VPR128.8H[96,16] = MP_INT_ABS(TMPQ5[96,16]); + Rd_VPR128.8H[112,16] = MP_INT_ABS(TMPQ5[112,16]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.346 UABDL, UABDL2 page C7-2815 line 164471 MATCH x2e207000/mask=xbf20fc00 +# CONSTRUCT x2ea07000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@4:16 ARG3 $zext@4:16 $-@8 =$abs@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabdl/2@4 +# AUNIT --inst x2ea07000/mask=xffe0fc00 --status pass --comment "ext abd" + +:uabdl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x7 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]); + # simd resize TMPQ2 = zext(Rm_VPR64.2S) (lane size 4 to 8) + TMPQ2[0,64] = zext(Rm_VPR64.2S[0,32]); + TMPQ2[64,64] = zext(Rm_VPR64.2S[32,32]); + # simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 8 + TMPQ3[0,64] = TMPQ1[0,64] - TMPQ2[0,64]; + TMPQ3[64,64] = TMPQ1[64,64] - TMPQ2[64,64]; + # simd unary Rd_VPR128.2D = MP_INT_ABS(TMPQ3) on lane size 8 + Rd_VPR128.2D[0,64] = MP_INT_ABS(TMPQ3[0,64]); + Rd_VPR128.2D[64,64] = MP_INT_ABS(TMPQ3[64,64]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.346 UABDL, UABDL2 page C7-2815 line 164471 MATCH x2e207000/mask=xbf20fc00 +# CONSTRUCT x2e607000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@2:16 ARG3 $zext@2:16 $-@4 =$abs@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabdl/2@2 +# AUNIT --inst x2e607000/mask=xffe0fc00 --status pass --comment "ext abd" + +:uabdl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x7 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Rn_VPR128 & Rm_VPR128 & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]); + # simd resize TMPQ2 = zext(Rm_VPR64.4H) (lane size 2 to 4) + TMPQ2[0,32] = zext(Rm_VPR64.4H[0,16]); + TMPQ2[32,32] = zext(Rm_VPR64.4H[16,16]); + TMPQ2[64,32] = zext(Rm_VPR64.4H[32,16]); + TMPQ2[96,32] = zext(Rm_VPR64.4H[48,16]); + # simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 4 + TMPQ3[0,32] = TMPQ1[0,32] - TMPQ2[0,32]; + TMPQ3[32,32] = TMPQ1[32,32] - TMPQ2[32,32]; + TMPQ3[64,32] = TMPQ1[64,32] - TMPQ2[64,32]; + TMPQ3[96,32] = TMPQ1[96,32] - TMPQ2[96,32]; + # simd unary Rd_VPR128.4S = MP_INT_ABS(TMPQ3) on lane size 4 + Rd_VPR128.4S[0,32] = MP_INT_ABS(TMPQ3[0,32]); + Rd_VPR128.4S[32,32] = MP_INT_ABS(TMPQ3[32,32]); + Rd_VPR128.4S[64,32] = MP_INT_ABS(TMPQ3[64,32]); + Rd_VPR128.4S[96,32] = MP_INT_ABS(TMPQ3[96,32]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.346 UABDL, UABDL2 page C7-2815 line 164471 MATCH x2e207000/mask=xbf20fc00 +# CONSTRUCT x2e207000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@1:16 ARG3 $zext@1:16 $-@2 =$abs@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabdl/2@1 +# AUNIT --inst x2e207000/mask=xffe0fc00 --status pass --comment "ext abd" + +:uabdl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x7 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Rn_VPR128 & Rm_VPR128 & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2) + TMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]); + TMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]); + TMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]); + TMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]); + TMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]); + TMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]); + TMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]); + TMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]); + # simd resize TMPQ2 = zext(Rm_VPR64.8B) (lane size 1 to 2) + TMPQ2[0,16] = zext(Rm_VPR64.8B[0,8]); + TMPQ2[16,16] = zext(Rm_VPR64.8B[8,8]); + TMPQ2[32,16] = zext(Rm_VPR64.8B[16,8]); + TMPQ2[48,16] = zext(Rm_VPR64.8B[24,8]); + TMPQ2[64,16] = zext(Rm_VPR64.8B[32,8]); + TMPQ2[80,16] = zext(Rm_VPR64.8B[40,8]); + TMPQ2[96,16] = zext(Rm_VPR64.8B[48,8]); + TMPQ2[112,16] = zext(Rm_VPR64.8B[56,8]); + # simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 2 + TMPQ3[0,16] = TMPQ1[0,16] - TMPQ2[0,16]; + TMPQ3[16,16] = TMPQ1[16,16] - TMPQ2[16,16]; + TMPQ3[32,16] = TMPQ1[32,16] - TMPQ2[32,16]; + TMPQ3[48,16] = TMPQ1[48,16] - TMPQ2[48,16]; + TMPQ3[64,16] = TMPQ1[64,16] - TMPQ2[64,16]; + TMPQ3[80,16] = TMPQ1[80,16] - TMPQ2[80,16]; + TMPQ3[96,16] = TMPQ1[96,16] - TMPQ2[96,16]; + TMPQ3[112,16] = TMPQ1[112,16] - TMPQ2[112,16]; + # simd unary Rd_VPR128.8H = MP_INT_ABS(TMPQ3) on lane size 2 + Rd_VPR128.8H[0,16] = MP_INT_ABS(TMPQ3[0,16]); + Rd_VPR128.8H[16,16] = MP_INT_ABS(TMPQ3[16,16]); + Rd_VPR128.8H[32,16] = MP_INT_ABS(TMPQ3[32,16]); + Rd_VPR128.8H[48,16] = MP_INT_ABS(TMPQ3[48,16]); + Rd_VPR128.8H[64,16] = MP_INT_ABS(TMPQ3[64,16]); + Rd_VPR128.8H[80,16] = MP_INT_ABS(TMPQ3[80,16]); + Rd_VPR128.8H[96,16] = MP_INT_ABS(TMPQ3[96,16]); + Rd_VPR128.8H[112,16] = MP_INT_ABS(TMPQ3[112,16]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.347 UADALP page C7-2817 line 164592 MATCH x2e206800/mask=xbf3ffc00 +# CONSTRUCT x6e206800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 var:16 ARG2 =#u+ &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_uadalp/2@1 +# AUNIT --inst x6e206800/mask=xfffffc00 --status pass --comment "ext" + +:uadalp Rd_VPR128.8H, Rn_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x6 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.8H & Zd +{ + TMPQ1 = 0; + # sipd infix TMPQ1 = +(Rn_VPR128.16B) on pairs lane size (1 to 2) + local tmp2 = Rn_VPR128.16B[0,8]; + local tmp4 = zext(tmp2); + local tmp3 = Rn_VPR128.16B[8,8]; + local tmp5 = zext(tmp3); + TMPQ1[0,16] = tmp4 + tmp5; + tmp2 = Rn_VPR128.16B[16,8]; + tmp4 = zext(tmp2); + tmp3 = Rn_VPR128.16B[24,8]; + tmp5 = zext(tmp3); + TMPQ1[16,16] = tmp4 + tmp5; + tmp2 = Rn_VPR128.16B[32,8]; + tmp4 = zext(tmp2); + tmp3 = Rn_VPR128.16B[40,8]; + tmp5 = zext(tmp3); + TMPQ1[32,16] = tmp4 + tmp5; + tmp2 = Rn_VPR128.16B[48,8]; + tmp4 = zext(tmp2); + tmp3 = Rn_VPR128.16B[56,8]; + tmp5 = zext(tmp3); + TMPQ1[48,16] = tmp4 + tmp5; + tmp2 = Rn_VPR128.16B[64,8]; + tmp4 = zext(tmp2); + tmp3 = Rn_VPR128.16B[72,8]; + tmp5 = zext(tmp3); + TMPQ1[64,16] = tmp4 + tmp5; + tmp2 = Rn_VPR128.16B[80,8]; + tmp4 = zext(tmp2); + tmp3 = Rn_VPR128.16B[88,8]; + tmp5 = zext(tmp3); + TMPQ1[80,16] = tmp4 + tmp5; + tmp2 = Rn_VPR128.16B[96,8]; + tmp4 = zext(tmp2); + tmp3 = Rn_VPR128.16B[104,8]; + tmp5 = zext(tmp3); + TMPQ1[96,16] = tmp4 + tmp5; + tmp2 = Rn_VPR128.16B[112,8]; + tmp4 = zext(tmp2); + tmp3 = Rn_VPR128.16B[120,8]; + tmp5 = zext(tmp3); + TMPQ1[112,16] = tmp4 + tmp5; + # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.347 UADALP page C7-2817 line 164592 MATCH x2e206800/mask=xbf3ffc00 +# CONSTRUCT x2ea06800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 var:8 ARG2 =#u+ &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_uadalp/2@4 +# AUNIT --inst x2ea06800/mask=xfffffc00 --status pass --comment "ext" + +:uadalp Rd_VPR64.1D, Rn_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x6 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.1D & Zd +{ + TMPD1 = 0; + # sipd infix TMPD1 = +(Rn_VPR64.2S) on pairs lane size (4 to 8) + local tmp2 = Rn_VPR64.2S[0,32]; + local tmp4 = zext(tmp2); + local tmp3 = Rn_VPR64.2S[32,32]; + local tmp5 = zext(tmp3); + TMPD1 = tmp4 + tmp5; + # simd infix Rd_VPR64.1D = Rd_VPR64.1D + TMPD1 on lane size 8 + Rd_VPR64.1D = Rd_VPR64.1D + TMPD1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.347 UADALP page C7-2817 line 164592 MATCH x2e206800/mask=xbf3ffc00 +# CONSTRUCT x2e606800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 var:8 ARG2 =#u+ &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_uadalp/2@2 +# AUNIT --inst x2e606800/mask=xfffffc00 --status pass --comment "ext" + +:uadalp Rd_VPR64.2S, Rn_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x6 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.2S & Zd +{ + TMPD1 = 0; + # sipd infix TMPD1 = +(Rn_VPR64.4H) on pairs lane size (2 to 4) + local tmp2 = Rn_VPR64.4H[0,16]; + local tmp4 = zext(tmp2); + local tmp3 = Rn_VPR64.4H[16,16]; + local tmp5 = zext(tmp3); + TMPD1[0,32] = tmp4 + tmp5; + tmp2 = Rn_VPR64.4H[32,16]; + tmp4 = zext(tmp2); + tmp3 = Rn_VPR64.4H[48,16]; + tmp5 = zext(tmp3); + TMPD1[32,32] = tmp4 + tmp5; + # simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4 + Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32]; + Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.347 UADALP page C7-2817 line 164592 MATCH x2e206800/mask=xbf3ffc00 +# CONSTRUCT x6ea06800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 var:16 ARG2 =#u+ &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_uadalp/2@4 +# AUNIT --inst x6ea06800/mask=xfffffc00 --status pass --comment "ext" + +:uadalp Rd_VPR128.2D, Rn_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x6 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPQ1 = 0; + # sipd infix TMPQ1 = +(Rn_VPR128.4S) on pairs lane size (4 to 8) + local tmp2 = Rn_VPR128.4S[0,32]; + local tmp4 = zext(tmp2); + local tmp3 = Rn_VPR128.4S[32,32]; + local tmp5 = zext(tmp3); + TMPQ1[0,64] = tmp4 + tmp5; + tmp2 = Rn_VPR128.4S[64,32]; + tmp4 = zext(tmp2); + tmp3 = Rn_VPR128.4S[96,32]; + tmp5 = zext(tmp3); + TMPQ1[64,64] = tmp4 + tmp5; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ1 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ1[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ1[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.347 UADALP page C7-2817 line 164592 MATCH x2e206800/mask=xbf3ffc00 +# CONSTRUCT x2e206800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 var:8 ARG2 =#u+ &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_uadalp/2@1 +# AUNIT --inst x2e206800/mask=xfffffc00 --status pass --comment "ext" + +:uadalp Rd_VPR64.4H, Rn_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x6 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.4H & Zd +{ + TMPD1 = 0; + # sipd infix TMPD1 = +(Rn_VPR64.8B) on pairs lane size (1 to 2) + local tmp2 = Rn_VPR64.8B[0,8]; + local tmp4 = zext(tmp2); + local tmp3 = Rn_VPR64.8B[8,8]; + local tmp5 = zext(tmp3); + TMPD1[0,16] = tmp4 + tmp5; + tmp2 = Rn_VPR64.8B[16,8]; + tmp4 = zext(tmp2); + tmp3 = Rn_VPR64.8B[24,8]; + tmp5 = zext(tmp3); + TMPD1[16,16] = tmp4 + tmp5; + tmp2 = Rn_VPR64.8B[32,8]; + tmp4 = zext(tmp2); + tmp3 = Rn_VPR64.8B[40,8]; + tmp5 = zext(tmp3); + TMPD1[32,16] = tmp4 + tmp5; + tmp2 = Rn_VPR64.8B[48,8]; + tmp4 = zext(tmp2); + tmp3 = Rn_VPR64.8B[56,8]; + tmp5 = zext(tmp3); + TMPD1[48,16] = tmp4 + tmp5; + # simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2 + Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16]; + Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16]; + Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16]; + Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.347 UADALP page C7-2817 line 164592 MATCH x2e206800/mask=xbf3ffc00 +# CONSTRUCT x6e606800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 var:16 ARG2 =#u+ &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_uadalp/2@2 +# AUNIT --inst x6e606800/mask=xfffffc00 --status pass --comment "ext" + +:uadalp Rd_VPR128.4S, Rn_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x6 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPQ1 = 0; + # sipd infix TMPQ1 = +(Rn_VPR128.8H) on pairs lane size (2 to 4) + local tmp2 = Rn_VPR128.8H[0,16]; + local tmp4 = zext(tmp2); + local tmp3 = Rn_VPR128.8H[16,16]; + local tmp5 = zext(tmp3); + TMPQ1[0,32] = tmp4 + tmp5; + tmp2 = Rn_VPR128.8H[32,16]; + tmp4 = zext(tmp2); + tmp3 = Rn_VPR128.8H[48,16]; + tmp5 = zext(tmp3); + TMPQ1[32,32] = tmp4 + tmp5; + tmp2 = Rn_VPR128.8H[64,16]; + tmp4 = zext(tmp2); + tmp3 = Rn_VPR128.8H[80,16]; + tmp5 = zext(tmp3); + TMPQ1[64,32] = tmp4 + tmp5; + tmp2 = Rn_VPR128.8H[96,16]; + tmp4 = zext(tmp2); + tmp3 = Rn_VPR128.8H[112,16]; + tmp5 = zext(tmp3); + TMPQ1[96,32] = tmp4 + tmp5; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.348 UADDL, UADDL2 page C7-2819 line 164702 MATCH x2e200000/mask=xbf20fc00 +# CONSTRUCT x6ea00000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 =$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddl2/2@4 +# AUNIT --inst x6ea00000/mask=xffe0fc00 --status pass --comment "ext" + +:uaddl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x0 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = zext(TMPD1[0,32]); + TMPQ2[64,64] = zext(TMPD1[32,32]); + TMPD3 = Rm_VPR128.4S[64,64]; + # simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8) + TMPQ4[0,64] = zext(TMPD3[0,32]); + TMPQ4[64,64] = zext(TMPD3[32,32]); + # simd infix Rd_VPR128.2D = TMPQ2 + TMPQ4 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ2[0,64] + TMPQ4[0,64]; + Rd_VPR128.2D[64,64] = TMPQ2[64,64] + TMPQ4[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.348 UADDL, UADDL2 page C7-2819 line 164702 MATCH x2e200000/mask=xbf20fc00 +# CONSTRUCT x6e600000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 =$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddl2/2@2 +# AUNIT --inst x6e600000/mask=xffe0fc00 --status pass --comment "ext" + +:uaddl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x0 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = zext(TMPD1[0,16]); + TMPQ2[32,32] = zext(TMPD1[16,16]); + TMPQ2[64,32] = zext(TMPD1[32,16]); + TMPQ2[96,32] = zext(TMPD1[48,16]); + TMPD3 = Rm_VPR128.8H[64,64]; + # simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4) + TMPQ4[0,32] = zext(TMPD3[0,16]); + TMPQ4[32,32] = zext(TMPD3[16,16]); + TMPQ4[64,32] = zext(TMPD3[32,16]); + TMPQ4[96,32] = zext(TMPD3[48,16]); + # simd infix Rd_VPR128.4S = TMPQ2 + TMPQ4 on lane size 4 + Rd_VPR128.4S[0,32] = TMPQ2[0,32] + TMPQ4[0,32]; + Rd_VPR128.4S[32,32] = TMPQ2[32,32] + TMPQ4[32,32]; + Rd_VPR128.4S[64,32] = TMPQ2[64,32] + TMPQ4[64,32]; + Rd_VPR128.4S[96,32] = TMPQ2[96,32] + TMPQ4[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.348 UADDL, UADDL2 page C7-2819 line 164702 MATCH x2e200000/mask=xbf20fc00 +# CONSTRUCT x6e200000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 =$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddl2/2@1 +# AUNIT --inst x6e200000/mask=xffe0fc00 --status pass --comment "ext" + +:uaddl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x0 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd +{ + TMPD1 = Rn_VPR128.16B[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2) + TMPQ2[0,16] = zext(TMPD1[0,8]); + TMPQ2[16,16] = zext(TMPD1[8,8]); + TMPQ2[32,16] = zext(TMPD1[16,8]); + TMPQ2[48,16] = zext(TMPD1[24,8]); + TMPQ2[64,16] = zext(TMPD1[32,8]); + TMPQ2[80,16] = zext(TMPD1[40,8]); + TMPQ2[96,16] = zext(TMPD1[48,8]); + TMPQ2[112,16] = zext(TMPD1[56,8]); + TMPD3 = Rm_VPR128.16B[64,64]; + # simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2) + TMPQ4[0,16] = zext(TMPD3[0,8]); + TMPQ4[16,16] = zext(TMPD3[8,8]); + TMPQ4[32,16] = zext(TMPD3[16,8]); + TMPQ4[48,16] = zext(TMPD3[24,8]); + TMPQ4[64,16] = zext(TMPD3[32,8]); + TMPQ4[80,16] = zext(TMPD3[40,8]); + TMPQ4[96,16] = zext(TMPD3[48,8]); + TMPQ4[112,16] = zext(TMPD3[56,8]); + # simd infix Rd_VPR128.8H = TMPQ2 + TMPQ4 on lane size 2 + Rd_VPR128.8H[0,16] = TMPQ2[0,16] + TMPQ4[0,16]; + Rd_VPR128.8H[16,16] = TMPQ2[16,16] + TMPQ4[16,16]; + Rd_VPR128.8H[32,16] = TMPQ2[32,16] + TMPQ4[32,16]; + Rd_VPR128.8H[48,16] = TMPQ2[48,16] + TMPQ4[48,16]; + Rd_VPR128.8H[64,16] = TMPQ2[64,16] + TMPQ4[64,16]; + Rd_VPR128.8H[80,16] = TMPQ2[80,16] + TMPQ4[80,16]; + Rd_VPR128.8H[96,16] = TMPQ2[96,16] + TMPQ4[96,16]; + Rd_VPR128.8H[112,16] = TMPQ2[112,16] + TMPQ4[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.348 UADDL, UADDL2 page C7-2819 line 164702 MATCH x2e200000/mask=xbf20fc00 +# CONSTRUCT x2ea00000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@4:16 ARG3 $zext@4:16 =$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddl/2@4 +# AUNIT --inst x2ea00000/mask=xffe0fc00 --status pass --comment "ext" + +:uaddl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x0 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]); + # simd resize TMPQ2 = zext(Rm_VPR64.2S) (lane size 4 to 8) + TMPQ2[0,64] = zext(Rm_VPR64.2S[0,32]); + TMPQ2[64,64] = zext(Rm_VPR64.2S[32,32]); + # simd infix Rd_VPR128.2D = TMPQ1 + TMPQ2 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ1[0,64] + TMPQ2[0,64]; + Rd_VPR128.2D[64,64] = TMPQ1[64,64] + TMPQ2[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.348 UADDL, UADDL2 page C7-2819 line 164702 MATCH x2e200000/mask=xbf20fc00 +# CONSTRUCT x2e600000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@2:16 ARG3 $zext@2:16 =$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddl/2@2 +# AUNIT --inst x2e600000/mask=xffe0fc00 --status pass --comment "ext" + +:uaddl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x0 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]); + # simd resize TMPQ2 = zext(Rm_VPR64.4H) (lane size 2 to 4) + TMPQ2[0,32] = zext(Rm_VPR64.4H[0,16]); + TMPQ2[32,32] = zext(Rm_VPR64.4H[16,16]); + TMPQ2[64,32] = zext(Rm_VPR64.4H[32,16]); + TMPQ2[96,32] = zext(Rm_VPR64.4H[48,16]); + # simd infix Rd_VPR128.4S = TMPQ1 + TMPQ2 on lane size 4 + Rd_VPR128.4S[0,32] = TMPQ1[0,32] + TMPQ2[0,32]; + Rd_VPR128.4S[32,32] = TMPQ1[32,32] + TMPQ2[32,32]; + Rd_VPR128.4S[64,32] = TMPQ1[64,32] + TMPQ2[64,32]; + Rd_VPR128.4S[96,32] = TMPQ1[96,32] + TMPQ2[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.348 UADDL, UADDL2 page C7-2819 line 164702 MATCH x2e200000/mask=xbf20fc00 +# CONSTRUCT x2e200000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@1:16 ARG3 $zext@1:16 =$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddl/2@1 +# AUNIT --inst x2e200000/mask=xffe0fc00 --status pass --comment "ext" + +:uaddl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x0 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2) + TMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]); + TMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]); + TMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]); + TMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]); + TMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]); + TMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]); + TMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]); + TMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]); + # simd resize TMPQ2 = zext(Rm_VPR64.8B) (lane size 1 to 2) + TMPQ2[0,16] = zext(Rm_VPR64.8B[0,8]); + TMPQ2[16,16] = zext(Rm_VPR64.8B[8,8]); + TMPQ2[32,16] = zext(Rm_VPR64.8B[16,8]); + TMPQ2[48,16] = zext(Rm_VPR64.8B[24,8]); + TMPQ2[64,16] = zext(Rm_VPR64.8B[32,8]); + TMPQ2[80,16] = zext(Rm_VPR64.8B[40,8]); + TMPQ2[96,16] = zext(Rm_VPR64.8B[48,8]); + TMPQ2[112,16] = zext(Rm_VPR64.8B[56,8]); + # simd infix Rd_VPR128.8H = TMPQ1 + TMPQ2 on lane size 2 + Rd_VPR128.8H[0,16] = TMPQ1[0,16] + TMPQ2[0,16]; + Rd_VPR128.8H[16,16] = TMPQ1[16,16] + TMPQ2[16,16]; + Rd_VPR128.8H[32,16] = TMPQ1[32,16] + TMPQ2[32,16]; + Rd_VPR128.8H[48,16] = TMPQ1[48,16] + TMPQ2[48,16]; + Rd_VPR128.8H[64,16] = TMPQ1[64,16] + TMPQ2[64,16]; + Rd_VPR128.8H[80,16] = TMPQ1[80,16] + TMPQ2[80,16]; + Rd_VPR128.8H[96,16] = TMPQ1[96,16] + TMPQ2[96,16]; + Rd_VPR128.8H[112,16] = TMPQ1[112,16] + TMPQ2[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.349 UADDLP page C7-2821 line 164825 MATCH x2e202800/mask=xbf3ffc00 +# CONSTRUCT x2e202800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =var =#u+@1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlp/1@1 +# AUNIT --inst x2e202800/mask=xfffffc00 --status pass --comment "ext" +# Vector variant when size = 00 , Q = 0 s=16 e1=1 e2=2 Ta=VPR64.4H Tb=VPR64.8B + +:uaddlp Rd_VPR64.4H, Rn_VPR64.8B +is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000001010 & Rd_VPR64.4H & Rn_VPR64.8B & Zd +{ + TMPD1 = Rn_VPR64.8B; + # sipd infix Rd_VPR64.4H = +(TMPD1) on pairs lane size (1 to 2) + local tmp2 = TMPD1[0,8]; + local tmp4 = zext(tmp2); + local tmp3 = TMPD1[8,8]; + local tmp5 = zext(tmp3); + Rd_VPR64.4H[0,16] = tmp4 + tmp5; + tmp2 = TMPD1[16,8]; + tmp4 = zext(tmp2); + tmp3 = TMPD1[24,8]; + tmp5 = zext(tmp3); + Rd_VPR64.4H[16,16] = tmp4 + tmp5; + tmp2 = TMPD1[32,8]; + tmp4 = zext(tmp2); + tmp3 = TMPD1[40,8]; + tmp5 = zext(tmp3); + Rd_VPR64.4H[32,16] = tmp4 + tmp5; + tmp2 = TMPD1[48,8]; + tmp4 = zext(tmp2); + tmp3 = TMPD1[56,8]; + tmp5 = zext(tmp3); + Rd_VPR64.4H[48,16] = tmp4 + tmp5; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.349 UADDLP page C7-2821 line 164825 MATCH x2e202800/mask=xbf3ffc00 +# CONSTRUCT x6e202800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =var =#u+@1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlp/1@1 +# AUNIT --inst x6e202800/mask=xfffffc00 --status pass --comment "ext" +# Vector variant when size = 00 , Q = 1 s=32 e1=1 e2=2 Ta=VPR128.8H Tb=VPR128.16B + +:uaddlp Rd_VPR128.8H, Rn_VPR128.16B +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000001010 & Rd_VPR128.8H & Rn_VPR128.16B & Zd +{ + TMPQ1 = Rn_VPR128.16B; + # sipd infix Rd_VPR128.8H = +(TMPQ1) on pairs lane size (1 to 2) + local tmp2 = TMPQ1[0,8]; + local tmp4 = zext(tmp2); + local tmp3 = TMPQ1[8,8]; + local tmp5 = zext(tmp3); + Rd_VPR128.8H[0,16] = tmp4 + tmp5; + tmp2 = TMPQ1[16,8]; + tmp4 = zext(tmp2); + tmp3 = TMPQ1[24,8]; + tmp5 = zext(tmp3); + Rd_VPR128.8H[16,16] = tmp4 + tmp5; + tmp2 = TMPQ1[32,8]; + tmp4 = zext(tmp2); + tmp3 = TMPQ1[40,8]; + tmp5 = zext(tmp3); + Rd_VPR128.8H[32,16] = tmp4 + tmp5; + tmp2 = TMPQ1[48,8]; + tmp4 = zext(tmp2); + tmp3 = TMPQ1[56,8]; + tmp5 = zext(tmp3); + Rd_VPR128.8H[48,16] = tmp4 + tmp5; + tmp2 = TMPQ1[64,8]; + tmp4 = zext(tmp2); + tmp3 = TMPQ1[72,8]; + tmp5 = zext(tmp3); + Rd_VPR128.8H[64,16] = tmp4 + tmp5; + tmp2 = TMPQ1[80,8]; + tmp4 = zext(tmp2); + tmp3 = TMPQ1[88,8]; + tmp5 = zext(tmp3); + Rd_VPR128.8H[80,16] = tmp4 + tmp5; + tmp2 = TMPQ1[96,8]; + tmp4 = zext(tmp2); + tmp3 = TMPQ1[104,8]; + tmp5 = zext(tmp3); + Rd_VPR128.8H[96,16] = tmp4 + tmp5; + tmp2 = TMPQ1[112,8]; + tmp4 = zext(tmp2); + tmp3 = TMPQ1[120,8]; + tmp5 = zext(tmp3); + Rd_VPR128.8H[112,16] = tmp4 + tmp5; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.349 UADDLP page C7-2821 line 164825 MATCH x2e202800/mask=xbf3ffc00 +# CONSTRUCT x2e602800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =var =#u+@2 +# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlp/1@2 +# AUNIT --inst x2e602800/mask=xfffffc00 --status pass --comment "ext" +# Vector variant when size = 01 , Q = 0 s=16 e1=2 e2=4 Ta=VPR64.2S Tb=VPR64.4H + +:uaddlp Rd_VPR64.2S, Rn_VPR64.4H +is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000001010 & Rd_VPR64.2S & Rn_VPR64.4H & Zd +{ + TMPD1 = Rn_VPR64.4H; + # sipd infix Rd_VPR64.2S = +(TMPD1) on pairs lane size (2 to 4) + local tmp2 = TMPD1[0,16]; + local tmp4 = zext(tmp2); + local tmp3 = TMPD1[16,16]; + local tmp5 = zext(tmp3); + Rd_VPR64.2S[0,32] = tmp4 + tmp5; + tmp2 = TMPD1[32,16]; + tmp4 = zext(tmp2); + tmp3 = TMPD1[48,16]; + tmp5 = zext(tmp3); + Rd_VPR64.2S[32,32] = tmp4 + tmp5; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.349 UADDLP page C7-2821 line 164825 MATCH x2e202800/mask=xbf3ffc00 +# CONSTRUCT x6e602800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =var =#u+@2 +# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlp/1@2 +# AUNIT --inst x6e602800/mask=xfffffc00 --status pass --comment "ext" +# Vector variant when size = 01 , Q = 1 s=32 e1=2 e2=4 Ta=VPR128.4S Tb=VPR128.8H + +:uaddlp Rd_VPR128.4S, Rn_VPR128.8H +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000001010 & Rd_VPR128.4S & Rn_VPR128.8H & Zd +{ + TMPQ1 = Rn_VPR128.8H; + # sipd infix Rd_VPR128.4S = +(TMPQ1) on pairs lane size (2 to 4) + local tmp2 = TMPQ1[0,16]; + local tmp4 = zext(tmp2); + local tmp3 = TMPQ1[16,16]; + local tmp5 = zext(tmp3); + Rd_VPR128.4S[0,32] = tmp4 + tmp5; + tmp2 = TMPQ1[32,16]; + tmp4 = zext(tmp2); + tmp3 = TMPQ1[48,16]; + tmp5 = zext(tmp3); + Rd_VPR128.4S[32,32] = tmp4 + tmp5; + tmp2 = TMPQ1[64,16]; + tmp4 = zext(tmp2); + tmp3 = TMPQ1[80,16]; + tmp5 = zext(tmp3); + Rd_VPR128.4S[64,32] = tmp4 + tmp5; + tmp2 = TMPQ1[96,16]; + tmp4 = zext(tmp2); + tmp3 = TMPQ1[112,16]; + tmp5 = zext(tmp3); + Rd_VPR128.4S[96,32] = tmp4 + tmp5; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.349 UADDLP page C7-2821 line 164825 MATCH x2e202800/mask=xbf3ffc00 +# CONSTRUCT x2ea02800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =var =#u+@4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlp/1@4 +# AUNIT --inst x2ea02800/mask=xfffffc00 --status pass --comment "ext" +# Vector variant when size = 10 , Q = 0 s=16 e1=4 e2=8 Ta=VPR64.1D Tb=VPR64.2S + +:uaddlp Rd_VPR64.1D, Rn_VPR64.2S +is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000001010 & Rd_VPR64.1D & Rn_VPR64.2S & Zd +{ + TMPD1 = Rn_VPR64.2S; + # sipd infix Rd_VPR64.1D = +(TMPD1) on pairs lane size (4 to 8) + local tmp2 = TMPD1[0,32]; + local tmp4 = zext(tmp2); + local tmp3 = TMPD1[32,32]; + local tmp5 = zext(tmp3); + Rd_VPR64.1D = tmp4 + tmp5; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.349 UADDLP page C7-2821 line 164825 MATCH x2e202800/mask=xbf3ffc00 +# CONSTRUCT x6ea02800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =var =#u+@4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlp/1@4 +# AUNIT --inst x6ea02800/mask=xfffffc00 --status pass --comment "ext" +# Vector variant when size = 10 , Q = 1 s=32 e1=4 e2=8 Ta=VPR128.2D Tb=VPR128.4S + +:uaddlp Rd_VPR128.2D, Rn_VPR128.4S +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000001010 & Rd_VPR128.2D & Rn_VPR128.4S & Zd +{ + TMPQ1 = Rn_VPR128.4S; + # sipd infix Rd_VPR128.2D = +(TMPQ1) on pairs lane size (4 to 8) + local tmp2 = TMPQ1[0,32]; + local tmp4 = zext(tmp2); + local tmp3 = TMPQ1[32,32]; + local tmp5 = zext(tmp3); + Rd_VPR128.2D[0,64] = tmp4 + tmp5; + tmp2 = TMPQ1[64,32]; + tmp4 = zext(tmp2); + tmp3 = TMPQ1[96,32]; + tmp5 = zext(tmp3); + Rd_VPR128.2D[64,64] = tmp4 + tmp5; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.350 UADDLV page C7-2823 line 164935 MATCH x2e303800/mask=xbf3ffc00 +# CONSTRUCT x6eb03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlv/1@4 +# AUNIT --inst x6eb03800/mask=xfffffc00 --status nopcodeop --comment "ext" + +:uaddlv Rd_FPR64, Rn_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR128.4S & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_uaddlv(Rn_VPR128.4S, 4:1); +} + +# C7.2.350 UADDLV page C7-2823 line 164935 MATCH x2e303800/mask=xbf3ffc00 +# CONSTRUCT x6e303800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlv/1@1 +# AUNIT --inst x6e303800/mask=xfffffc00 --status nopcodeop --comment "ext" + +:uaddlv Rd_FPR16, Rn_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR128.16B & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_uaddlv(Rn_VPR128.16B, 1:1); +} + +# C7.2.350 UADDLV page C7-2823 line 164935 MATCH x2e303800/mask=xbf3ffc00 +# CONSTRUCT x2e303800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlv/1@1 +# AUNIT --inst x2e303800/mask=xfffffc00 --status nopcodeop --comment "ext" + +:uaddlv Rd_FPR16, Rn_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR64.8B & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_uaddlv(Rn_VPR64.8B, 1:1); +} + +# C7.2.350 UADDLV page C7-2823 line 164935 MATCH x2e303800/mask=xbf3ffc00 +# CONSTRUCT x2e703800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlv/1@2 +# AUNIT --inst x2e703800/mask=xfffffc00 --status nopcodeop --comment "ext" + +:uaddlv Rd_FPR32, Rn_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR64.4H & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_uaddlv(Rn_VPR64.4H, 2:1); +} + +# C7.2.350 UADDLV page C7-2823 line 164935 MATCH x2e303800/mask=xbf3ffc00 +# CONSTRUCT x6e703800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlv/1@2 +# AUNIT --inst x6e703800/mask=xfffffc00 --status nopcodeop --comment "ext" + +:uaddlv Rd_FPR32, Rn_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR128.8H & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_uaddlv(Rn_VPR128.8H, 2:1); +} + +# C7.2.351 UADDW, UADDW2 page C7-2825 line 165035 MATCH x2e201000/mask=xbf20fc00 +# CONSTRUCT x6ea01000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3[1]:8 $zext@4:16 =$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddw2/2@4 +# AUNIT --inst x6ea01000/mask=xffe0fc00 --status pass --comment "ext" + +:uaddw2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x1 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + TMPD1 = Rm_VPR128.4S[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = zext(TMPD1[0,32]); + TMPQ2[64,64] = zext(TMPD1[32,32]); + # simd infix Rd_VPR128.2D = Rn_VPR128.2D + TMPQ2 on lane size 8 + Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] + TMPQ2[0,64]; + Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] + TMPQ2[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.351 UADDW, UADDW2 page C7-2825 line 165035 MATCH x2e201000/mask=xbf20fc00 +# CONSTRUCT x6e601000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3[1]:8 $zext@2:16 =$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddw2/2@2 +# AUNIT --inst x6e601000/mask=xffe0fc00 --status pass --comment "ext" + +:uaddw2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x1 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + TMPD1 = Rm_VPR128.8H[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = zext(TMPD1[0,16]); + TMPQ2[32,32] = zext(TMPD1[16,16]); + TMPQ2[64,32] = zext(TMPD1[32,16]); + TMPQ2[96,32] = zext(TMPD1[48,16]); + # simd infix Rd_VPR128.4S = Rn_VPR128.4S + TMPQ2 on lane size 4 + Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] + TMPQ2[0,32]; + Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] + TMPQ2[32,32]; + Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] + TMPQ2[64,32]; + Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] + TMPQ2[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.351 UADDW, UADDW2 page C7-2825 line 165035 MATCH x2e201000/mask=xbf20fc00 +# CONSTRUCT x6e201000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3[1]:8 $zext@1:16 =$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddw2/2@1 +# AUNIT --inst x6e201000/mask=xffe0fc00 --status pass --comment "ext" + +:uaddw2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x1 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + TMPD1 = Rm_VPR128.16B[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2) + TMPQ2[0,16] = zext(TMPD1[0,8]); + TMPQ2[16,16] = zext(TMPD1[8,8]); + TMPQ2[32,16] = zext(TMPD1[16,8]); + TMPQ2[48,16] = zext(TMPD1[24,8]); + TMPQ2[64,16] = zext(TMPD1[32,8]); + TMPQ2[80,16] = zext(TMPD1[40,8]); + TMPQ2[96,16] = zext(TMPD1[48,8]); + TMPQ2[112,16] = zext(TMPD1[56,8]); + # simd infix Rd_VPR128.8H = Rn_VPR128.8H + TMPQ2 on lane size 2 + Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] + TMPQ2[0,16]; + Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] + TMPQ2[16,16]; + Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] + TMPQ2[32,16]; + Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] + TMPQ2[48,16]; + Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] + TMPQ2[64,16]; + Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] + TMPQ2[80,16]; + Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] + TMPQ2[96,16]; + Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] + TMPQ2[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.351 UADDW, UADDW2 page C7-2825 line 165035 MATCH x2e201000/mask=xbf20fc00 +# CONSTRUCT x2ea01000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $zext@4:16 =$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddw/2@4 +# AUNIT --inst x2ea01000/mask=xffe0fc00 --status pass --comment "ext" + +:uaddw Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x1 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = zext(Rm_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = zext(Rm_VPR64.2S[0,32]); + TMPQ1[64,64] = zext(Rm_VPR64.2S[32,32]); + # simd infix Rd_VPR128.2D = Rn_VPR128.2D + TMPQ1 on lane size 8 + Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] + TMPQ1[0,64]; + Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] + TMPQ1[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.351 UADDW, UADDW2 page C7-2825 line 165035 MATCH x2e201000/mask=xbf20fc00 +# CONSTRUCT x2e601000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $zext@2:16 =$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddw/2@2 +# AUNIT --inst x2e601000/mask=xffe0fc00 --status pass --comment "ext" + +:uaddw Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x1 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = zext(Rm_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = zext(Rm_VPR64.4H[0,16]); + TMPQ1[32,32] = zext(Rm_VPR64.4H[16,16]); + TMPQ1[64,32] = zext(Rm_VPR64.4H[32,16]); + TMPQ1[96,32] = zext(Rm_VPR64.4H[48,16]); + # simd infix Rd_VPR128.4S = Rn_VPR128.4S + TMPQ1 on lane size 4 + Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] + TMPQ1[0,32]; + Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] + TMPQ1[32,32]; + Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] + TMPQ1[64,32]; + Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] + TMPQ1[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.351 UADDW, UADDW2 page C7-2825 line 165035 MATCH x2e201000/mask=xbf20fc00 +# CONSTRUCT x2e201000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $zext@1:16 =$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddw/2@1 +# AUNIT --inst x2e201000/mask=xffe0fc00 --status pass --comment "ext" + +:uaddw Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x1 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + # simd resize TMPQ1 = zext(Rm_VPR64.8B) (lane size 1 to 2) + TMPQ1[0,16] = zext(Rm_VPR64.8B[0,8]); + TMPQ1[16,16] = zext(Rm_VPR64.8B[8,8]); + TMPQ1[32,16] = zext(Rm_VPR64.8B[16,8]); + TMPQ1[48,16] = zext(Rm_VPR64.8B[24,8]); + TMPQ1[64,16] = zext(Rm_VPR64.8B[32,8]); + TMPQ1[80,16] = zext(Rm_VPR64.8B[40,8]); + TMPQ1[96,16] = zext(Rm_VPR64.8B[48,8]); + TMPQ1[112,16] = zext(Rm_VPR64.8B[56,8]); + # simd infix Rd_VPR128.8H = Rn_VPR128.8H + TMPQ1 on lane size 2 + Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] + TMPQ1[0,16]; + Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] + TMPQ1[16,16]; + Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] + TMPQ1[32,16]; + Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] + TMPQ1[48,16]; + Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] + TMPQ1[64,16]; + Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] + TMPQ1[80,16]; + Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] + TMPQ1[96,16]; + Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] + TMPQ1[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x7f00e400/mask=xff80fc00 +# CONSTRUCT x7f40e400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2 +# AUNIT --inst x7f40e400/mask=xffc0fc00 --status nopcodeop --comment "nofpround" + +:ucvtf Rd_FPR64, Rn_FPR64, Imm_shr_imm64 +is b_3031=1 & u=1 & b_2428=0x1f & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x1c & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_ucvtf(Rn_FPR64, Imm_shr_imm64:1); +} + +# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x7f00e400/mask=xff80fc00 +# CONSTRUCT x7f20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2 +# AUNIT --inst x7f20e400/mask=xffe0fc00 --status nopcodeop --comment "nofpround" + +:ucvtf Rd_FPR32, Rn_FPR32, Imm_shr_imm32 +is b_3031=1 & u=1 & b_2428=0x1f & b_2123=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_ucvtf(Rn_FPR32, Imm_shr_imm32:1); +} + +# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x7f00e400/mask=xff80fc00 +# CONSTRUCT x7f10e400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2 +# AUNIT --inst x7f10e400/mask=xfff0fc00 --status noqemu --comment "nofpround" + +:ucvtf Rd_FPR16, Rn_FPR16, Imm_shr_imm16 +is b_3031=1 & u=1 & b_2428=0x1f & b_2023=1 & Imm_shr_imm16 & b_1115=0x1c & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_ucvtf(Rn_FPR16, Imm_shr_imm16:1); +} + +# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x2f00e400/mask=xbf80fc00 +# CONSTRUCT x6f40e400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2@8 +# AUNIT --inst x6f40e400/mask=xffc0fc00 --status nopcodeop --comment "nofpround" + +:ucvtf Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x1c & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_ucvtf(Rn_VPR128.2D, Imm_shr_imm64:1, 8:1); +} + +# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x2f00e400/mask=xbf80fc00 +# CONSTRUCT x2f20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2@4 +# AUNIT --inst x2f20e400/mask=xffe0fc00 --status nopcodeop --comment "nofpround" + +:ucvtf Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_ucvtf(Rn_VPR64.2S, Imm_shr_imm32:1, 4:1); +} + +# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x2f00e400/mask=xbf80fc00 +# CONSTRUCT x6f20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2@4 +# AUNIT --inst x6f20e400/mask=xffe0fc00 --status nopcodeop --comment "nofpround" + +:ucvtf Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_ucvtf(Rn_VPR128.4S, Imm_shr_imm32:1, 4:1); +} + +# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x2f00e400/mask=xbf80fc00 +# CONSTRUCT x2f10e400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2@2 +# AUNIT --inst x2f10e400/mask=xfff0fc00 --status noqemu --comment "nofpround" + +:ucvtf Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm32 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_ucvtf(Rn_VPR64.4H, Imm_shr_imm32:1, 2:1); +} + +# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x2f00e400/mask=xbf80fc00 +# CONSTRUCT x6f10e400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2@2 +# AUNIT --inst x6f10e400/mask=xfff0fc00 --status noqemu --comment "nofpround" + +:ucvtf Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm32 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_ucvtf(Rn_VPR128.8H, Imm_shr_imm32:1, 2:1); +} + +# C7.2.353 UCVTF (vector, integer) page C7-2830 line 165313 MATCH x7e21d800/mask=xffbffc00 +# CONSTRUCT x7e21d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1 +# AUNIT --inst x7e21d800/mask=xfffffc00 --status nopcodeop --comment "nofpround" + +:ucvtf Rd_FPR32, Rn_FPR32 +is b_3031=1 & u=1 & b_2428=0x1e & size_high=0 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_ucvtf(Rn_FPR32); +} + +# C7.2.353 UCVTF (vector, integer) page C7-2830 line 165313 MATCH x7e21d800/mask=xffbffc00 +# CONSTRUCT x7e61d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1 +# AUNIT --inst x7e61d800/mask=xfffffc00 --status nopcodeop --comment "nofpround" + +:ucvtf Rd_FPR64, Rn_FPR64 +is b_3031=1 & u=1 & b_2428=0x1e & size_high=0 & b_1722=0x30 & b_1216=0x1d & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_ucvtf(Rn_FPR64); +} + +# C7.2.353 UCVTF (vector, integer) page C7-2830 line 165313 MATCH x2e21d800/mask=xbfbffc00 +# CONSTRUCT x2e21d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1@4 +# AUNIT --inst x2e21d800/mask=xfffffc00 --status nopcodeop --comment "nofpround" + +:ucvtf Rd_VPR64.2S, Rn_VPR64.2S +is sf=0 & q=0 & b_2929=1 & b_2428=0x0e & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x1d & b_1011=2 & Rd_VPR64.2S & Rn_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_ucvtf(Rn_VPR64.2S, 4:1); +} + +# C7.2.353 UCVTF (vector, integer) page C7-2830 line 165313 MATCH x2e21d800/mask=xbfbffc00 +# CONSTRUCT x6e21d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1@4 +# AUNIT --inst x6e21d800/mask=xfffffc00 --status nopcodeop --comment "nofpround" + +:ucvtf Rd_VPR128.4S, Rn_VPR128.4S +is sf=0 & q=1 & b_2929=1 & b_2428=0x0e & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x1d & b_1011=2 & Rd_VPR128.4S & Rn_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_ucvtf(Rn_VPR128.4S, 4:1); +} + +# C7.2.353 UCVTF (vector, integer) page C7-2830 line 165313 MATCH x2e21d800/mask=xbfbffc00 +# CONSTRUCT x6e61d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1@8 +# AUNIT --inst x6e61d800/mask=xfffffc00 --status nopcodeop --comment "nofpround" + +:ucvtf Rd_VPR128.2D, Rn_VPR128.2D +is sf=0 & q=1 & b_2929=1 & b_2428=0x0e & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x1d & b_1011=2 & Rd_VPR128.2D & Rn_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_ucvtf(Rn_VPR128.2D, 8:1); +} + +# C7.2.353 UCVTF (vector, integer) page C7-2830 line 165313 MATCH x7e79d800/mask=xfffffc00 +# CONSTRUCT x7e79d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1 +# AUNIT --inst x7e79d800/mask=xfffffc00 --status noqemu --comment "nofpround" +# Scalar half precision variant + +:ucvtf Rd_FPR16, Rn_FPR16 +is b_1031=0b0111111001111001110110 & Rd_FPR16 & Rn_FPR16 & Zd +{ + Rd_FPR16 = NEON_ucvtf(Rn_FPR16); +} + +# C7.2.353 UCVTF (vector, integer) page C7-2830 line 165313 MATCH x2e79d800/mask=xbffffc00 +# CONSTRUCT x2e79d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1@2 +# AUNIT --inst x2e79d800/mask=xfffffc00 --status noqemu --comment "nofpround" +# Vector half precision variant when Q=0 T=VPR64.4H + +:ucvtf Rd_VPR64.4H, Rn_VPR64.4H +is b_31=0 & b_30=0 & b_1029=0b10111001111001110110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_ucvtf(Rn_VPR64.4H, 2:1); +} + +# C7.2.353 UCVTF (vector, integer) page C7-2830 line 165313 MATCH x2e79d800/mask=xbffffc00 +# CONSTRUCT x6e79d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1@2 +# AUNIT --inst x6e79d800/mask=xfffffc00 --status noqemu --comment "nofpround" +# Vector half precision variant when Q=1 T=VPR128.8H + +:ucvtf Rd_VPR128.8H, Rn_VPR128.8H +is b_31=0 & b_30=1 & b_1029=0b10111001111001110110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_ucvtf(Rn_VPR128.8H, 2:1); +} + +# C7.2.354 UCVTF (scalar, fixed-point) page C7-2833 line 165497 MATCH x1e030000/mask=x7f3f0000 +# CONSTRUCT x1ec38000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 zext:8 int2float:2 FBits16 =f/ +# SMACRO(pseudo) ARG1 ARG2 FBits16 =NEON_ucvtf/2 +# AUNIT --inst x1ec38000/mask=xffff8000 --status noqemu --comment "nofpround" +# if sf == '0' && scale<5> == '0' then UnallocatedEncoding(); + +:ucvtf Rd_FPR16, Rn_GPR32, FBitsOp +is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=0 & mode=0 & fpOpcode=3 & b_15=1 & FBitsOp & FBits16 & Rn_GPR32 & Rd_FPR16 & Zd +{ + local tmp1:8 = zext(Rn_GPR32); + local tmp2:2 = int2float(tmp1); + Rd_FPR16 = tmp2 f/ FBits16; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.354 UCVTF (scalar, fixed-point) page C7-2833 line 165497 MATCH x1e030000/mask=x7f3f0000 +# CONSTRUCT x9ec30000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 zext:9 int2float:2 FBits16 =f/ +# SMACRO(pseudo) ARG1 ARG2 FBits16 =NEON_ucvtf/2 +# AUNIT --inst x9ec30000/mask=xffff0000 --status noqemu --comment "nofpround" + +:ucvtf Rd_FPR16, Rn_GPR64, FBitsOp +is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=0 & mode=0 & fpOpcode=3 & FBitsOp & FBits16 & Rn_GPR64 & Rd_FPR16 & Zd +{ + local tmp1:9 = zext(Rn_GPR64); + local tmp2:2 = int2float(tmp1); + Rd_FPR16 = tmp2 f/ FBits16; + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.354 UCVTF (scalar, fixed-point) page C7-2833 line 165497 MATCH x1e030000/mask=x7f3f0000 +# CONSTRUCT x1e438000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 zext:8 int2float:8 FBits64 =f/ +# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_ucvtf/2 +# AUNIT --inst x1e438000/mask=xffff8000 --status pass --comment "nofpround" +# if sf == '0' && scale<5> == '0' then UnallocatedEncoding(); + +:ucvtf Rd_FPR64, Rn_GPR32, FBitsOp +is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=0 & mode=0 & fpOpcode=3 & b_15=1 & FBitsOp & FBits64 & Rn_GPR32 & Rd_FPR64 & Zd +{ + local tmp1:8 = zext(Rn_GPR32); + local tmp2:8 = int2float(tmp1); + Rd_FPR64 = tmp2 f/ FBits64; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.354 UCVTF (scalar, fixed-point) page C7-2833 line 165497 MATCH x1e030000/mask=x7f3f0000 +# CONSTRUCT x9e430000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 zext:9 int2float:8 FBits64 =f/ +# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_ucvtf/2 +# AUNIT --inst x9e430000/mask=xffff0000 --status fail --comment "nofpround" +# The zext:9 naively force unsigned int before conversion + +:ucvtf Rd_FPR64, Rn_GPR64, FBitsOp +is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=0 & mode=0 & fpOpcode=3 & FBitsOp & FBits64 & Rn_GPR64 & Rd_FPR64 & Zd +{ + local tmp1:9 = zext(Rn_GPR64); + local tmp2:8 = int2float(tmp1); + Rd_FPR64 = tmp2 f/ FBits64; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.354 UCVTF (scalar, fixed-point) page C7-2833 line 165497 MATCH x1e030000/mask=x7f3f0000 +# CONSTRUCT x1e038000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 zext:8 int2float:4 FBits32 =f/ +# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_ucvtf/2 +# AUNIT --inst x1e038000/mask=xffff8000 --status fail --comment "nofpround" +# if sf == '0' && scale<5> == '0' then UnallocatedEncoding(); + +:ucvtf Rd_FPR32, Rn_GPR32, FBitsOp +is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=0 & mode=0 & fpOpcode=3 & b_15=1 & FBitsOp & FBits32 & Rn_GPR32 & Rd_FPR32 & Zd +{ + local tmp1:8 = zext(Rn_GPR32); + local tmp2:4 = int2float(tmp1); + Rd_FPR32 = tmp2 f/ FBits32; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.354 UCVTF (scalar, fixed-point) page C7-2833 line 165497 MATCH x1e030000/mask=x7f3f0000 +# CONSTRUCT x9e030000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 zext:9 int2float:4 FBits32 =f/ +# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_ucvtf/2 +# AUNIT --inst x9e030000/mask=xffff0000 --status fail --comment "nofpround" + +:ucvtf Rd_FPR32, Rn_GPR64, FBitsOp +is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=0 & mode=0 & fpOpcode=3 & FBitsOp & FBits32 & Rn_GPR64 & Rd_FPR32 & Zd +{ + local tmp1:9 = zext(Rn_GPR64); + local tmp2:4 = int2float(tmp1); + Rd_FPR32 = tmp2 f/ FBits32; + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.355 UCVTF (scalar, integer) page C7-2835 line 165632 MATCH x1e230000/mask=x7f3ffc00 +# CONSTRUCT x1ee30000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 zext:8 =int2float +# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1 +# AUNIT --inst x1ee30000/mask=xfffffc00 --status noqemu --comment "nofpround" + +:ucvtf Rd_FPR16, Rn_GPR32 +is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & rmode=0 & fpOpcode=3 & b_1015=0x0 & Rn_GPR32 & Rd_FPR16 & Zd +{ + local tmp1:8 = zext(Rn_GPR32); + Rd_FPR16 = int2float(tmp1); + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.355 UCVTF (scalar, integer) page C7-2835 line 165632 MATCH x1e230000/mask=x7f3ffc00 +# CONSTRUCT x9ee30000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 zext:9 =int2float +# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1 +# AUNIT --inst x9ee30000/mask=xfffffc00 --status noqemu --comment "nofpround" + +:ucvtf Rd_FPR16, Rn_GPR64 +is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & rmode=0 & fpOpcode=3 & b_1015=0x0 & Rn_GPR64 & Rd_FPR16 & Zd +{ + local tmp1:9 = zext(Rn_GPR64); + Rd_FPR16 = int2float(tmp1); + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.355 UCVTF (scalar, integer) page C7-2835 line 165632 MATCH x1e230000/mask=x7f3ffc00 +# CONSTRUCT x1e630000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 zext:8 =int2float +# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1 +# AUNIT --inst x1e630000/mask=xfffffc00 --status pass --comment "nofpround" + +:ucvtf Rd_FPR64, Rn_GPR32 +is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & rmode=0 & fpOpcode=3 & b_1015=0x0 & Rn_GPR32 & Rd_FPR64 & Zd +{ + local tmp1:8 = zext(Rn_GPR32); + Rd_FPR64 = int2float(tmp1); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.355 UCVTF (scalar, integer) page C7-2835 line 165632 MATCH x1e230000/mask=x7f3ffc00 +# CONSTRUCT x9e630000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 zext:9 =int2float +# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1 +# AUNIT --inst x9e630000/mask=xfffffc00 --status fail --comment "nofpround" + +:ucvtf Rd_FPR64, Rn_GPR64 +is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & rmode=0 & fpOpcode=3 & b_1015=0x0 & Rn_GPR64 & Rd_FPR64 & Zd +{ + local tmp1:9 = zext(Rn_GPR64); + Rd_FPR64 = int2float(tmp1); + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.355 UCVTF (scalar, integer) page C7-2835 line 165632 MATCH x1e230000/mask=x7f3ffc00 +# CONSTRUCT x1e230000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 zext:8 =int2float +# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1 +# AUNIT --inst x1e230000/mask=xfffffc00 --status fail --comment "nofpround" + +:ucvtf Rd_FPR32, Rn_GPR32 +is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & rmode=0 & fpOpcode=3 & b_1015=0x0 & Rn_GPR32 & Rd_FPR32 & Zd +{ + local tmp1:8 = zext(Rn_GPR32); + Rd_FPR32 = int2float(tmp1); + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.355 UCVTF (scalar, integer) page C7-2835 line 165632 MATCH x1e230000/mask=x7f3ffc00 +# CONSTRUCT x9e230000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 zext:9 =int2float +# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1 +# AUNIT --inst x9e230000/mask=xfffffc00 --status fail --comment "nofpround" + +:ucvtf Rd_FPR32, Rn_GPR64 +is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & rmode=0 & fpOpcode=3 & b_1015=0x0 & Rn_GPR64 & Rd_FPR32 & Zd +{ + local tmp1:9 = zext(Rn_GPR64); + Rd_FPR32 = int2float(tmp1); + zext_zs(Zd); # zero upper 28 bytes of Zd +} + +# C7.2.356 UDOT (by element) page C7-2837 line 165760 MATCH x2f00e000/mask=xbf00f400 +# CONSTRUCT x2f80e000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 Re_VPR128.S.vIndex =NEON_udot/2@1 +# AUNIT --inst x2f80e000/mask=xffc0f400 --status noqemu +# Vector variant when Q=0 Ta=VPR64.2S Tb=VPR64.8B + +:udot Rd_VPR64.2S, Rn_VPR64.8B, Re_VPR128.B.vIndex +is b_31=0 & b_30=0 & b_2429=0b101111 & b_2223=0b10 & b_1215=0b1110 & b_10=0 & Rd_VPR64.2S & Rn_VPR64.8B & Re_VPR128.B.vIndex & Re_VPR128.S & vIndex & Zd +{ + local tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1); + Rd_VPR64.2S = NEON_udot(Rn_VPR64.8B, tmp1, 1:1); +} + +# C7.2.356 UDOT (by element) page C7-2837 line 165760 MATCH x2f00e000/mask=xbf00f400 +# CONSTRUCT x6f80e000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 Re_VPR128.S.vIndex =NEON_udot/2@1 +# AUNIT --inst x6f80e000/mask=xffc0f400 --status noqemu +# Vector variant when Q=1 Ta=VPR128.4S Tb=VPR128.16B + +:udot Rd_VPR128.4S, Rn_VPR128.16B, Re_VPR128.B.vIndex +is b_31=0 & b_30=1 & b_2429=0b101111 & b_2223=0b10 & b_1215=0b1110 & b_10=0 & Rd_VPR128.4S & Rn_VPR128.16B & Re_VPR128.B.vIndex & Re_VPR128.S & vIndex & Zd +{ + local tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1); + Rd_VPR128.4S = NEON_udot(Rn_VPR128.16B, tmp1, 1:1); +} + +# C7.2.357 UDOT (vector) page C7-2839 line 165862 MATCH x2e009400/mask=xbf20fc00 +# CONSTRUCT x2e809400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_udot/2@1 +# AUNIT --inst x2e809400/mask=xffe0fc00 --status noqemu +# Three registers of the same type variant when Q=0 Ta=VPR64.2S Tb=VPR64.8B + +:udot Rd_VPR64.2S, Rn_VPR64.8B, Rm_VPR64.8B +is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_21=0 & b_1015=0b100101 & Rd_VPR64.2S & Rn_VPR64.8B & Rm_VPR64.8B & Zd +{ + Rd_VPR64.2S = NEON_udot(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.357 UDOT (vector) page C7-2839 line 165862 MATCH x2e009400/mask=xbf20fc00 +# CONSTRUCT x6e809400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_udot/2@1 +# AUNIT --inst x6e809400/mask=xffe0fc00 --status noqemu +# Three registers of the same type variant when Q=1 Ta=VPR128.4S Tb=VPR128.16B + +:udot Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_21=0 & b_1015=0b100101 & Rd_VPR128.4S & Rn_VPR128.16B & Rm_VPR128.16B & Zd +{ + Rd_VPR128.4S = NEON_udot(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.358 UHADD page C7-2841 line 165961 MATCH x2e200400/mask=xbf20fc00 +# CONSTRUCT x6e200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhadd/2@1 +# AUNIT --inst x6e200400/mask=xffe0fc00 --status nopcodeop + +:uhadd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x0 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_uhadd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.358 UHADD page C7-2841 line 165961 MATCH x2e200400/mask=xbf20fc00 +# CONSTRUCT x2ea00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhadd/2@4 +# AUNIT --inst x2ea00400/mask=xffe0fc00 --status nopcodeop + +:uhadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x0 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_uhadd(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.358 UHADD page C7-2841 line 165961 MATCH x2e200400/mask=xbf20fc00 +# CONSTRUCT x2e600400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhadd/2@2 +# AUNIT --inst x2e600400/mask=xffe0fc00 --status nopcodeop + +:uhadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x0 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_uhadd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.358 UHADD page C7-2841 line 165961 MATCH x2e200400/mask=xbf20fc00 +# CONSTRUCT x6ea00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhadd/2@4 +# AUNIT --inst x6ea00400/mask=xffe0fc00 --status nopcodeop + +:uhadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x0 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_uhadd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.358 UHADD page C7-2841 line 165961 MATCH x2e200400/mask=xbf20fc00 +# CONSTRUCT x2e200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhadd/2@1 +# AUNIT --inst x2e200400/mask=xffe0fc00 --status nopcodeop + +:uhadd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x0 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_uhadd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.358 UHADD page C7-2841 line 165961 MATCH x2e200400/mask=xbf20fc00 +# CONSTRUCT x6e600400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhadd/2@2 +# AUNIT --inst x6e600400/mask=xffe0fc00 --status nopcodeop + +:uhadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x0 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_uhadd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.359 UHSUB page C7-2843 line 166063 MATCH x2e202400/mask=xbf20fc00 +# CONSTRUCT x6e202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhsub/2@1 +# AUNIT --inst x6e202400/mask=xffe0fc00 --status nopcodeop + +:uhsub Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x4 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_uhsub(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.359 UHSUB page C7-2843 line 166063 MATCH x2e202400/mask=xbf20fc00 +# CONSTRUCT x2ea02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhsub/2@4 +# AUNIT --inst x2ea02400/mask=xffe0fc00 --status nopcodeop + +:uhsub Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x4 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_uhsub(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.359 UHSUB page C7-2843 line 166063 MATCH x2e202400/mask=xbf20fc00 +# CONSTRUCT x2e602400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhsub/2@2 +# AUNIT --inst x2e602400/mask=xffe0fc00 --status nopcodeop + +:uhsub Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x4 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_uhsub(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.359 UHSUB page C7-2843 line 166063 MATCH x2e202400/mask=xbf20fc00 +# CONSTRUCT x6ea02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhsub/2@4 +# AUNIT --inst x6ea02400/mask=xffe0fc00 --status nopcodeop + +:uhsub Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x4 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_uhsub(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.359 UHSUB page C7-2843 line 166063 MATCH x2e202400/mask=xbf20fc00 +# CONSTRUCT x2e202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhsub/2@1 +# AUNIT --inst x2e202400/mask=xffe0fc00 --status nopcodeop + +:uhsub Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x4 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_uhsub(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.359 UHSUB page C7-2843 line 166063 MATCH x2e202400/mask=xbf20fc00 +# CONSTRUCT x6e602400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhsub/2@2 +# AUNIT --inst x6e602400/mask=xffe0fc00 --status nopcodeop + +:uhsub Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x4 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_uhsub(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.360 UMAX page C7-2845 line 166163 MATCH x2e206400/mask=xbf20fc00 +# CONSTRUCT x6e206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umax/2@1 +# AUNIT --inst x6e206400/mask=xffe0fc00 --status nopcodeop + +:umax Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xc & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_umax(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.360 UMAX page C7-2845 line 166163 MATCH x2e206400/mask=xbf20fc00 +# CONSTRUCT x2ea06400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umax/2@4 +# AUNIT --inst x2ea06400/mask=xffe0fc00 --status nopcodeop + +:umax Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xc & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_umax(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.360 UMAX page C7-2845 line 166163 MATCH x2e206400/mask=xbf20fc00 +# CONSTRUCT x2e606400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umax/2@2 +# AUNIT --inst x2e606400/mask=xffe0fc00 --status nopcodeop + +:umax Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xc & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_umax(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.360 UMAX page C7-2845 line 166163 MATCH x2e206400/mask=xbf20fc00 +# CONSTRUCT x6ea06400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umax/2@4 +# AUNIT --inst x6ea06400/mask=xffe0fc00 --status nopcodeop + +:umax Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xc & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_umax(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.360 UMAX page C7-2845 line 166163 MATCH x2e206400/mask=xbf20fc00 +# CONSTRUCT x2e206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umax/2@1 +# AUNIT --inst x2e206400/mask=xffe0fc00 --status nopcodeop + +:umax Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xc & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_umax(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.360 UMAX page C7-2845 line 166163 MATCH x2e206400/mask=xbf20fc00 +# CONSTRUCT x6e606400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umax/2@2 +# AUNIT --inst x6e606400/mask=xffe0fc00 --status nopcodeop + +:umax Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xc & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_umax(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.361 UMAXP page C7-2847 line 166265 MATCH x2e20a400/mask=xbf20fc00 +# CONSTRUCT x6e20a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umaxp/2@1 +# AUNIT --inst x6e20a400/mask=xffe0fc00 --status nopcodeop + +:umaxp Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x14 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_umaxp(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.361 UMAXP page C7-2847 line 166265 MATCH x2e20a400/mask=xbf20fc00 +# CONSTRUCT x2ea0a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umaxp/2@4 +# AUNIT --inst x2ea0a400/mask=xffe0fc00 --status nopcodeop + +:umaxp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x14 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_umaxp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.361 UMAXP page C7-2847 line 166265 MATCH x2e20a400/mask=xbf20fc00 +# CONSTRUCT x2e60a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umaxp/2@2 +# AUNIT --inst x2e60a400/mask=xffe0fc00 --status nopcodeop + +:umaxp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x14 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_umaxp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.361 UMAXP page C7-2847 line 166265 MATCH x2e20a400/mask=xbf20fc00 +# CONSTRUCT x6ea0a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umaxp/2@4 +# AUNIT --inst x6ea0a400/mask=xffe0fc00 --status nopcodeop + +:umaxp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x14 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_umaxp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.361 UMAXP page C7-2847 line 166265 MATCH x2e20a400/mask=xbf20fc00 +# CONSTRUCT x2e20a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umaxp/2@1 +# AUNIT --inst x2e20a400/mask=xffe0fc00 --status nopcodeop + +:umaxp Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x14 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_umaxp(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.361 UMAXP page C7-2847 line 166265 MATCH x2e20a400/mask=xbf20fc00 +# CONSTRUCT x6e60a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umaxp/2@2 +# AUNIT --inst x6e60a400/mask=xffe0fc00 --status nopcodeop + +:umaxp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x14 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_umaxp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.362 UMAXV page C7-2849 line 166369 MATCH x2e30a800/mask=xbf3ffc00 +# CONSTRUCT x6e30a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_umaxv/1@1 +# AUNIT --inst x6e30a800/mask=xfffffc00 --status nopcodeop + +:umaxv Rd_FPR8, Rn_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.16B & Rd_FPR8 & Zd +{ + Rd_FPR8 = NEON_umaxv(Rn_VPR128.16B, 1:1); +} + +# C7.2.362 UMAXV page C7-2849 line 166369 MATCH x2e30a800/mask=xbf3ffc00 +# CONSTRUCT x2e30a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_umaxv/1@1 +# AUNIT --inst x2e30a800/mask=xfffffc00 --status nopcodeop + +:umaxv Rd_FPR8, Rn_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR64.8B & Rd_FPR8 & Zd +{ + Rd_FPR8 = NEON_umaxv(Rn_VPR64.8B, 1:1); +} + +# C7.2.362 UMAXV page C7-2849 line 166369 MATCH x2e30a800/mask=xbf3ffc00 +# CONSTRUCT x2e70a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_umaxv/1@2 +# AUNIT --inst x2e70a800/mask=xfffffc00 --status nopcodeop + +:umaxv Rd_FPR16, Rn_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR64.4H & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_umaxv(Rn_VPR64.4H, 2:1); +} + +# C7.2.362 UMAXV page C7-2849 line 166369 MATCH x2e30a800/mask=xbf3ffc00 +# CONSTRUCT x6e70a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_umaxv/1@2 +# AUNIT --inst x6e70a800/mask=xfffffc00 --status nopcodeop + +:umaxv Rd_FPR16, Rn_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.8H & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_umaxv(Rn_VPR128.8H, 2:1); +} + +# C7.2.362 UMAXV page C7-2849 line 166369 MATCH x2e30a800/mask=xbf3ffc00 +# CONSTRUCT x6eb0a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_umaxv/1@4 +# AUNIT --inst x6eb0a800/mask=xfffffc00 --status nopcodeop + +:umaxv Rd_FPR32, Rn_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_umaxv(Rn_VPR128.4S, 4:1); +} + +# C7.2.363 UMIN page C7-2851 line 166472 MATCH x2e206c00/mask=xbf20fc00 +# CONSTRUCT x6e206c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umin/2@1 +# AUNIT --inst x6e206c00/mask=xffe0fc00 --status nopcodeop + +:umin Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xd & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_umin(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.363 UMIN page C7-2851 line 166472 MATCH x2e206c00/mask=xbf20fc00 +# CONSTRUCT x2ea06c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umin/2@4 +# AUNIT --inst x2ea06c00/mask=xffe0fc00 --status nopcodeop + +:umin Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xd & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_umin(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.363 UMIN page C7-2851 line 166472 MATCH x2e206c00/mask=xbf20fc00 +# CONSTRUCT x2e606c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umin/2@2 +# AUNIT --inst x2e606c00/mask=xffe0fc00 --status nopcodeop + +:umin Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xd & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_umin(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.363 UMIN page C7-2851 line 166472 MATCH x2e206c00/mask=xbf20fc00 +# CONSTRUCT x6ea06c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umin/2@4 +# AUNIT --inst x6ea06c00/mask=xffe0fc00 --status nopcodeop + +:umin Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xd & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_umin(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.363 UMIN page C7-2851 line 166472 MATCH x2e206c00/mask=xbf20fc00 +# CONSTRUCT x2e206c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umin/2@1 +# AUNIT --inst x2e206c00/mask=xffe0fc00 --status nopcodeop + +:umin Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xd & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_umin(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.363 UMIN page C7-2851 line 166472 MATCH x2e206c00/mask=xbf20fc00 +# CONSTRUCT x6e606c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umin/2@2 +# AUNIT --inst x6e606c00/mask=xffe0fc00 --status nopcodeop + +:umin Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xd & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_umin(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.364 UMINP page C7-2853 line 166574 MATCH x2e20ac00/mask=xbf20fc00 +# CONSTRUCT x6e20ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uminp/2@1 +# AUNIT --inst x6e20ac00/mask=xffe0fc00 --status nopcodeop + +:uminp Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x15 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_uminp(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.364 UMINP page C7-2853 line 166574 MATCH x2e20ac00/mask=xbf20fc00 +# CONSTRUCT x2ea0ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uminp/2@4 +# AUNIT --inst x2ea0ac00/mask=xffe0fc00 --status nopcodeop + +:uminp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x15 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_uminp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.364 UMINP page C7-2853 line 166574 MATCH x2e20ac00/mask=xbf20fc00 +# CONSTRUCT x2e60ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uminp/2@2 +# AUNIT --inst x2e60ac00/mask=xffe0fc00 --status nopcodeop + +:uminp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x15 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_uminp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.364 UMINP page C7-2853 line 166574 MATCH x2e20ac00/mask=xbf20fc00 +# CONSTRUCT x6ea0ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uminp/2@4 +# AUNIT --inst x6ea0ac00/mask=xffe0fc00 --status nopcodeop + +:uminp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x15 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_uminp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.364 UMINP page C7-2853 line 166574 MATCH x2e20ac00/mask=xbf20fc00 +# CONSTRUCT x2e20ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uminp/2@1 +# AUNIT --inst x2e20ac00/mask=xffe0fc00 --status nopcodeop + +:uminp Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x15 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_uminp(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.364 UMINP page C7-2853 line 166574 MATCH x2e20ac00/mask=xbf20fc00 +# CONSTRUCT x6e60ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uminp/2@2 +# AUNIT --inst x6e60ac00/mask=xffe0fc00 --status nopcodeop + +:uminp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x15 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_uminp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.365 UMINV page C7-2855 line 166678 MATCH x2e31a800/mask=xbf3ffc00 +# CONSTRUCT x6e31a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_uminv/1@1 +# AUNIT --inst x6e31a800/mask=xfffffc00 --status nopcodeop + +:uminv Rd_FPR8, Rn_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.16B & Rd_FPR8 & Zd +{ + Rd_FPR8 = NEON_uminv(Rn_VPR128.16B, 1:1); +} + +# C7.2.365 UMINV page C7-2855 line 166678 MATCH x2e31a800/mask=xbf3ffc00 +# CONSTRUCT x2e31a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_uminv/1@1 +# AUNIT --inst x2e31a800/mask=xfffffc00 --status nopcodeop + +:uminv Rd_FPR8, Rn_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR64.8B & Rd_FPR8 & Zd +{ + Rd_FPR8 = NEON_uminv(Rn_VPR64.8B, 1:1); +} + +# C7.2.365 UMINV page C7-2855 line 166678 MATCH x2e31a800/mask=xbf3ffc00 +# CONSTRUCT x2e71a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_uminv/1@2 +# AUNIT --inst x2e71a800/mask=xfffffc00 --status nopcodeop + +:uminv Rd_FPR16, Rn_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR64.4H & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_uminv(Rn_VPR64.4H, 2:1); +} + +# C7.2.365 UMINV page C7-2855 line 166678 MATCH x2e31a800/mask=xbf3ffc00 +# CONSTRUCT x6e71a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_uminv/1@2 +# AUNIT --inst x6e71a800/mask=xfffffc00 --status nopcodeop + +:uminv Rd_FPR16, Rn_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.8H & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_uminv(Rn_VPR128.8H, 2:1); +} + +# C7.2.365 UMINV page C7-2855 line 166678 MATCH x2e31a800/mask=xbf3ffc00 +# CONSTRUCT x6eb1a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_uminv/1@4 +# AUNIT --inst x6eb1a800/mask=xfffffc00 --status nopcodeop + +:uminv Rd_FPR32, Rn_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_uminv(Rn_VPR128.4S, 4:1); +} + +# C7.2.366 UMLAL, UMLAL2 (by element) page C7-2857 line 166781 MATCH x2f002000/mask=xbf00f400 +# CONSTRUCT x2f802000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@4:16 ARG3 zext:8 $* &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal/3@4 +# AUNIT --inst x2f802000/mask=xffc0f400 --status pass --comment "ext" + +:umlal Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex +is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x2 & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp2:4 = Re_VPR128.S.vIndex; + local tmp3:8 = zext(tmp2); + # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8 + TMPQ2[0,64] = TMPQ1[0,64] * tmp3; + TMPQ2[64,64] = TMPQ1[64,64] * tmp3; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ2 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ2[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ2[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.366 UMLAL, UMLAL2 (by element) page C7-2857 line 166781 MATCH x2f002000/mask=xbf00f400 +# CONSTRUCT x6f802000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3 zext:8 $* &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal/3@4 +# AUNIT --inst x6f802000/mask=xffc0f400 --status pass --comment "ext" + +:umlal2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex +is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x2 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = zext(TMPD1[0,32]); + TMPQ2[64,64] = zext(TMPD1[32,32]); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp3:4 = Re_VPR128.S.vIndex; + local tmp4:8 = zext(tmp3); + # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8 + TMPQ3[0,64] = TMPQ2[0,64] * tmp4; + TMPQ3[64,64] = TMPQ2[64,64] * tmp4; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ3 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ3[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ3[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.366 UMLAL, UMLAL2 (by element) page C7-2857 line 166781 MATCH x2f002000/mask=xbf00f400 +# CONSTRUCT x2f402000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@2:16 ARG3 zext:4 $* &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal/3@2 +# AUNIT --inst x2f402000/mask=xffc0f400 --status pass --comment "ext" + +:umlal Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM +is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x2 & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]); + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp2:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp3:4 = zext(tmp2); + # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4 + TMPQ2[0,32] = TMPQ1[0,32] * tmp3; + TMPQ2[32,32] = TMPQ1[32,32] * tmp3; + TMPQ2[64,32] = TMPQ1[64,32] * tmp3; + TMPQ2[96,32] = TMPQ1[96,32] * tmp3; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ2 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ2[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ2[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ2[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ2[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.366 UMLAL, UMLAL2 (by element) page C7-2857 line 166781 MATCH x2f002000/mask=xbf00f400 +# CONSTRUCT x6f402000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3 zext:4 $* &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal2/3@2 +# AUNIT --inst x6f402000/mask=xffc0f400 --status pass --comment "ext" + +:umlal2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM +is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x2 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = zext(TMPD1[0,16]); + TMPQ2[32,32] = zext(TMPD1[16,16]); + TMPQ2[64,32] = zext(TMPD1[32,16]); + TMPQ2[96,32] = zext(TMPD1[48,16]); + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp3:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp4:4 = zext(tmp3); + # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4 + TMPQ3[0,32] = TMPQ2[0,32] * tmp4; + TMPQ3[32,32] = TMPQ2[32,32] * tmp4; + TMPQ3[64,32] = TMPQ2[64,32] * tmp4; + TMPQ3[96,32] = TMPQ2[96,32] * tmp4; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.367 UMLAL, UMLAL2 (vector) page C7-2860 line 166945 MATCH x2e208000/mask=xbf20fc00 +# CONSTRUCT x6ea08000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 $*@8 &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal2/3@4 +# AUNIT --inst x6ea08000/mask=xffe0fc00 --status pass --comment "ext" + +:umlal2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x8 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = zext(TMPD1[0,32]); + TMPQ2[64,64] = zext(TMPD1[32,32]); + TMPD3 = Rm_VPR128.4S[64,64]; + # simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8) + TMPQ4[0,64] = zext(TMPD3[0,32]); + TMPQ4[64,64] = zext(TMPD3[32,32]); + # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8 + TMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64]; + TMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64]; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ5 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ5[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ5[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.367 UMLAL, UMLAL2 (vector) page C7-2860 line 166945 MATCH x2e208000/mask=xbf20fc00 +# CONSTRUCT x6e608000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 $*@4 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal2/3@2 +# AUNIT --inst x6e608000/mask=xffe0fc00 --status pass --comment "ext" + +:umlal2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x8 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = zext(TMPD1[0,16]); + TMPQ2[32,32] = zext(TMPD1[16,16]); + TMPQ2[64,32] = zext(TMPD1[32,16]); + TMPQ2[96,32] = zext(TMPD1[48,16]); + TMPD3 = Rm_VPR128.8H[64,64]; + # simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4) + TMPQ4[0,32] = zext(TMPD3[0,16]); + TMPQ4[32,32] = zext(TMPD3[16,16]); + TMPQ4[64,32] = zext(TMPD3[32,16]); + TMPQ4[96,32] = zext(TMPD3[48,16]); + # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4 + TMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32]; + TMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32]; + TMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32]; + TMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32]; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ5 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ5[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ5[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ5[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ5[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.367 UMLAL, UMLAL2 (vector) page C7-2860 line 166945 MATCH x2e208000/mask=xbf20fc00 +# CONSTRUCT x6e208000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 $*@2 &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal2/3@1 +# AUNIT --inst x6e208000/mask=xffe0fc00 --status pass --comment "ext" + +:umlal2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x8 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd +{ + TMPD1 = Rn_VPR128.16B[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2) + TMPQ2[0,16] = zext(TMPD1[0,8]); + TMPQ2[16,16] = zext(TMPD1[8,8]); + TMPQ2[32,16] = zext(TMPD1[16,8]); + TMPQ2[48,16] = zext(TMPD1[24,8]); + TMPQ2[64,16] = zext(TMPD1[32,8]); + TMPQ2[80,16] = zext(TMPD1[40,8]); + TMPQ2[96,16] = zext(TMPD1[48,8]); + TMPQ2[112,16] = zext(TMPD1[56,8]); + TMPD3 = Rm_VPR128.16B[64,64]; + # simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2) + TMPQ4[0,16] = zext(TMPD3[0,8]); + TMPQ4[16,16] = zext(TMPD3[8,8]); + TMPQ4[32,16] = zext(TMPD3[16,8]); + TMPQ4[48,16] = zext(TMPD3[24,8]); + TMPQ4[64,16] = zext(TMPD3[32,8]); + TMPQ4[80,16] = zext(TMPD3[40,8]); + TMPQ4[96,16] = zext(TMPD3[48,8]); + TMPQ4[112,16] = zext(TMPD3[56,8]); + # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 2 + TMPQ5[0,16] = TMPQ2[0,16] * TMPQ4[0,16]; + TMPQ5[16,16] = TMPQ2[16,16] * TMPQ4[16,16]; + TMPQ5[32,16] = TMPQ2[32,16] * TMPQ4[32,16]; + TMPQ5[48,16] = TMPQ2[48,16] * TMPQ4[48,16]; + TMPQ5[64,16] = TMPQ2[64,16] * TMPQ4[64,16]; + TMPQ5[80,16] = TMPQ2[80,16] * TMPQ4[80,16]; + TMPQ5[96,16] = TMPQ2[96,16] * TMPQ4[96,16]; + TMPQ5[112,16] = TMPQ2[112,16] * TMPQ4[112,16]; + # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ5 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ5[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ5[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ5[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ5[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ5[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ5[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ5[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ5[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.367 UMLAL, UMLAL2 (vector) page C7-2860 line 166945 MATCH x2e208000/mask=xbf20fc00 +# CONSTRUCT x2ea08000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@4:16 ARG3 $zext@4:16 $*@8 &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal/3@4 +# AUNIT --inst x2ea08000/mask=xffe0fc00 --status pass --comment "ext" + +:umlal Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x8 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]); + # simd resize TMPQ2 = zext(Rm_VPR64.2S) (lane size 4 to 8) + TMPQ2[0,64] = zext(Rm_VPR64.2S[0,32]); + TMPQ2[64,64] = zext(Rm_VPR64.2S[32,32]); + # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 8 + TMPQ3[0,64] = TMPQ1[0,64] * TMPQ2[0,64]; + TMPQ3[64,64] = TMPQ1[64,64] * TMPQ2[64,64]; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ3 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ3[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ3[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.367 UMLAL, UMLAL2 (vector) page C7-2860 line 166945 MATCH x2e208000/mask=xbf20fc00 +# CONSTRUCT x2e608000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@2:16 ARG3 $zext@2:16 $*@4 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal/3@2 +# AUNIT --inst x2e608000/mask=xffe0fc00 --status pass --comment "ext" + +:umlal Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x8 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]); + # simd resize TMPQ2 = zext(Rm_VPR64.4H) (lane size 2 to 4) + TMPQ2[0,32] = zext(Rm_VPR64.4H[0,16]); + TMPQ2[32,32] = zext(Rm_VPR64.4H[16,16]); + TMPQ2[64,32] = zext(Rm_VPR64.4H[32,16]); + TMPQ2[96,32] = zext(Rm_VPR64.4H[48,16]); + # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 4 + TMPQ3[0,32] = TMPQ1[0,32] * TMPQ2[0,32]; + TMPQ3[32,32] = TMPQ1[32,32] * TMPQ2[32,32]; + TMPQ3[64,32] = TMPQ1[64,32] * TMPQ2[64,32]; + TMPQ3[96,32] = TMPQ1[96,32] * TMPQ2[96,32]; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.367 UMLAL, UMLAL2 (vector) page C7-2860 line 166945 MATCH x2e208000/mask=xbf20fc00 +# CONSTRUCT x2e208000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@1:16 ARG3 $zext@1:16 $*@2 &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal/3@1 +# AUNIT --inst x2e208000/mask=xffe0fc00 --status pass --comment "ext" + +:umlal Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x8 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2) + TMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]); + TMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]); + TMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]); + TMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]); + TMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]); + TMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]); + TMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]); + TMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]); + # simd resize TMPQ2 = zext(Rm_VPR64.8B) (lane size 1 to 2) + TMPQ2[0,16] = zext(Rm_VPR64.8B[0,8]); + TMPQ2[16,16] = zext(Rm_VPR64.8B[8,8]); + TMPQ2[32,16] = zext(Rm_VPR64.8B[16,8]); + TMPQ2[48,16] = zext(Rm_VPR64.8B[24,8]); + TMPQ2[64,16] = zext(Rm_VPR64.8B[32,8]); + TMPQ2[80,16] = zext(Rm_VPR64.8B[40,8]); + TMPQ2[96,16] = zext(Rm_VPR64.8B[48,8]); + TMPQ2[112,16] = zext(Rm_VPR64.8B[56,8]); + # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 2 + TMPQ3[0,16] = TMPQ1[0,16] * TMPQ2[0,16]; + TMPQ3[16,16] = TMPQ1[16,16] * TMPQ2[16,16]; + TMPQ3[32,16] = TMPQ1[32,16] * TMPQ2[32,16]; + TMPQ3[48,16] = TMPQ1[48,16] * TMPQ2[48,16]; + TMPQ3[64,16] = TMPQ1[64,16] * TMPQ2[64,16]; + TMPQ3[80,16] = TMPQ1[80,16] * TMPQ2[80,16]; + TMPQ3[96,16] = TMPQ1[96,16] * TMPQ2[96,16]; + TMPQ3[112,16] = TMPQ1[112,16] * TMPQ2[112,16]; + # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ3 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ3[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ3[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ3[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ3[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ3[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ3[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ3[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ3[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.368 UMLSL, UMLSL2 (by element) page C7-2862 line 167069 MATCH x2f006000/mask=xbf00f400 +# CONSTRUCT x2f806000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@4:16 ARG3 zext:8 $*@8 &=$-@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl/3@4 +# AUNIT --inst x2f806000/mask=xffc0f400 --status pass --comment "ext" + +:umlsl Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex +is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x6 & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp2:4 = Re_VPR128.S.vIndex; + local tmp3:8 = zext(tmp2); + # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8 + TMPQ2[0,64] = TMPQ1[0,64] * tmp3; + TMPQ2[64,64] = TMPQ1[64,64] * tmp3; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ2 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ2[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ2[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.368 UMLSL, UMLSL2 (by element) page C7-2862 line 167069 MATCH x2f006000/mask=xbf00f400 +# CONSTRUCT x6f806000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3 zext:8 $*@8 &=$-@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl2/3@4 +# AUNIT --inst x6f806000/mask=xffc0f400 --status pass --comment "ext" + +:umlsl2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex +is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x6 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = zext(TMPD1[0,32]); + TMPQ2[64,64] = zext(TMPD1[32,32]); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp3:4 = Re_VPR128.S.vIndex; + local tmp4:8 = zext(tmp3); + # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8 + TMPQ3[0,64] = TMPQ2[0,64] * tmp4; + TMPQ3[64,64] = TMPQ2[64,64] * tmp4; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ3 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ3[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ3[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.368 UMLSL, UMLSL2 (by element) page C7-2862 line 167069 MATCH x2f006000/mask=xbf00f400 +# CONSTRUCT x2f406000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@2:16 ARG3 zext:4 $*@4 &=$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl/3@2 +# AUNIT --inst x2f406000/mask=xffc0f400 --status pass --comment "ext" + +:umlsl Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM +is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x6 & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]); + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp2:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp3:4 = zext(tmp2); + # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4 + TMPQ2[0,32] = TMPQ1[0,32] * tmp3; + TMPQ2[32,32] = TMPQ1[32,32] * tmp3; + TMPQ2[64,32] = TMPQ1[64,32] * tmp3; + TMPQ2[96,32] = TMPQ1[96,32] * tmp3; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ2 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ2[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ2[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ2[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ2[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.368 UMLSL, UMLSL2 (by element) page C7-2862 line 167069 MATCH x2f006000/mask=xbf00f400 +# CONSTRUCT x6f406000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3 zext:4 $*@4 &=$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl2/3@2 +# AUNIT --inst x6f406000/mask=xffc0f400 --status pass --comment "ext" + +:umlsl2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM +is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x6 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = zext(TMPD1[0,16]); + TMPQ2[32,32] = zext(TMPD1[16,16]); + TMPQ2[64,32] = zext(TMPD1[32,16]); + TMPQ2[96,32] = zext(TMPD1[48,16]); + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp3:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp4:4 = zext(tmp3); + # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4 + TMPQ3[0,32] = TMPQ2[0,32] * tmp4; + TMPQ3[32,32] = TMPQ2[32,32] * tmp4; + TMPQ3[64,32] = TMPQ2[64,32] * tmp4; + TMPQ3[96,32] = TMPQ2[96,32] * tmp4; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.369 UMLSL, UMLSL2 (vector) page C7-2865 line 167233 MATCH x2e20a000/mask=xbf20fc00 +# CONSTRUCT x6ea0a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 $*@8 &=$-@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl2/3@4 +# AUNIT --inst x6ea0a000/mask=xffe0fc00 --status pass --comment "ext" + +:umlsl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0xa & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = zext(TMPD1[0,32]); + TMPQ2[64,64] = zext(TMPD1[32,32]); + TMPD3 = Rm_VPR128.4S[64,64]; + # simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8) + TMPQ4[0,64] = zext(TMPD3[0,32]); + TMPQ4[64,64] = zext(TMPD3[32,32]); + # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8 + TMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64]; + TMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64]; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ5 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ5[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ5[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.369 UMLSL, UMLSL2 (vector) page C7-2865 line 167233 MATCH x2e20a000/mask=xbf20fc00 +# CONSTRUCT x6e60a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 $*@4 &=$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl2/3@2 +# AUNIT --inst x6e60a000/mask=xffe0fc00 --status pass --comment "ext" + +:umlsl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0xa & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = zext(TMPD1[0,16]); + TMPQ2[32,32] = zext(TMPD1[16,16]); + TMPQ2[64,32] = zext(TMPD1[32,16]); + TMPQ2[96,32] = zext(TMPD1[48,16]); + TMPD3 = Rm_VPR128.8H[64,64]; + # simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4) + TMPQ4[0,32] = zext(TMPD3[0,16]); + TMPQ4[32,32] = zext(TMPD3[16,16]); + TMPQ4[64,32] = zext(TMPD3[32,16]); + TMPQ4[96,32] = zext(TMPD3[48,16]); + # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4 + TMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32]; + TMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32]; + TMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32]; + TMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32]; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ5 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ5[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ5[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ5[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ5[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.369 UMLSL, UMLSL2 (vector) page C7-2865 line 167233 MATCH x2e20a000/mask=xbf20fc00 +# CONSTRUCT x6e20a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 $*@2 &=$-@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl2/3@1 +# AUNIT --inst x6e20a000/mask=xffe0fc00 --status pass --comment "ext" + +:umlsl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0xa & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd +{ + TMPD1 = Rn_VPR128.16B[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2) + TMPQ2[0,16] = zext(TMPD1[0,8]); + TMPQ2[16,16] = zext(TMPD1[8,8]); + TMPQ2[32,16] = zext(TMPD1[16,8]); + TMPQ2[48,16] = zext(TMPD1[24,8]); + TMPQ2[64,16] = zext(TMPD1[32,8]); + TMPQ2[80,16] = zext(TMPD1[40,8]); + TMPQ2[96,16] = zext(TMPD1[48,8]); + TMPQ2[112,16] = zext(TMPD1[56,8]); + TMPD3 = Rm_VPR128.16B[64,64]; + # simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2) + TMPQ4[0,16] = zext(TMPD3[0,8]); + TMPQ4[16,16] = zext(TMPD3[8,8]); + TMPQ4[32,16] = zext(TMPD3[16,8]); + TMPQ4[48,16] = zext(TMPD3[24,8]); + TMPQ4[64,16] = zext(TMPD3[32,8]); + TMPQ4[80,16] = zext(TMPD3[40,8]); + TMPQ4[96,16] = zext(TMPD3[48,8]); + TMPQ4[112,16] = zext(TMPD3[56,8]); + # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 2 + TMPQ5[0,16] = TMPQ2[0,16] * TMPQ4[0,16]; + TMPQ5[16,16] = TMPQ2[16,16] * TMPQ4[16,16]; + TMPQ5[32,16] = TMPQ2[32,16] * TMPQ4[32,16]; + TMPQ5[48,16] = TMPQ2[48,16] * TMPQ4[48,16]; + TMPQ5[64,16] = TMPQ2[64,16] * TMPQ4[64,16]; + TMPQ5[80,16] = TMPQ2[80,16] * TMPQ4[80,16]; + TMPQ5[96,16] = TMPQ2[96,16] * TMPQ4[96,16]; + TMPQ5[112,16] = TMPQ2[112,16] * TMPQ4[112,16]; + # simd infix Rd_VPR128.8H = Rd_VPR128.8H - TMPQ5 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] - TMPQ5[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] - TMPQ5[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] - TMPQ5[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] - TMPQ5[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] - TMPQ5[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] - TMPQ5[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] - TMPQ5[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] - TMPQ5[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.369 UMLSL, UMLSL2 (vector) page C7-2865 line 167233 MATCH x2e20a000/mask=xbf20fc00 +# CONSTRUCT x2ea0a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@4:16 ARG3 $zext@4:16 $*@8 &=$-@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl/3@4 +# AUNIT --inst x2ea0a000/mask=xffe0fc00 --status pass --comment "ext" + +:umlsl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0xa & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]); + # simd resize TMPQ2 = zext(Rm_VPR64.2S) (lane size 4 to 8) + TMPQ2[0,64] = zext(Rm_VPR64.2S[0,32]); + TMPQ2[64,64] = zext(Rm_VPR64.2S[32,32]); + # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 8 + TMPQ3[0,64] = TMPQ1[0,64] * TMPQ2[0,64]; + TMPQ3[64,64] = TMPQ1[64,64] * TMPQ2[64,64]; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ3 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ3[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ3[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.369 UMLSL, UMLSL2 (vector) page C7-2865 line 167233 MATCH x2e20a000/mask=xbf20fc00 +# CONSTRUCT x2e60a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@2:16 ARG3 $zext@2:16 $*@4 &=$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl/3@2 +# AUNIT --inst x2e60a000/mask=xffe0fc00 --status pass --comment "ext" + +:umlsl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0xa & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Rd_VPR128 & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]); + # simd resize TMPQ2 = zext(Rm_VPR64.4H) (lane size 2 to 4) + TMPQ2[0,32] = zext(Rm_VPR64.4H[0,16]); + TMPQ2[32,32] = zext(Rm_VPR64.4H[16,16]); + TMPQ2[64,32] = zext(Rm_VPR64.4H[32,16]); + TMPQ2[96,32] = zext(Rm_VPR64.4H[48,16]); + # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 4 + TMPQ3[0,32] = TMPQ1[0,32] * TMPQ2[0,32]; + TMPQ3[32,32] = TMPQ1[32,32] * TMPQ2[32,32]; + TMPQ3[64,32] = TMPQ1[64,32] * TMPQ2[64,32]; + TMPQ3[96,32] = TMPQ1[96,32] * TMPQ2[96,32]; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.369 UMLSL, UMLSL2 (vector) page C7-2865 line 167233 MATCH x2e20a000/mask=xbf20fc00 +# CONSTRUCT x2e20a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@1:16 ARG3 $zext@1:16 $*@2 &=$-@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl/3@1 +# AUNIT --inst x2e20a000/mask=xffe0fc00 --status pass --comment "ext" + +:umlsl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0xa & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Rd_VPR128 & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2) + TMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]); + TMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]); + TMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]); + TMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]); + TMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]); + TMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]); + TMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]); + TMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]); + # simd resize TMPQ2 = zext(Rm_VPR64.8B) (lane size 1 to 2) + TMPQ2[0,16] = zext(Rm_VPR64.8B[0,8]); + TMPQ2[16,16] = zext(Rm_VPR64.8B[8,8]); + TMPQ2[32,16] = zext(Rm_VPR64.8B[16,8]); + TMPQ2[48,16] = zext(Rm_VPR64.8B[24,8]); + TMPQ2[64,16] = zext(Rm_VPR64.8B[32,8]); + TMPQ2[80,16] = zext(Rm_VPR64.8B[40,8]); + TMPQ2[96,16] = zext(Rm_VPR64.8B[48,8]); + TMPQ2[112,16] = zext(Rm_VPR64.8B[56,8]); + # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 2 + TMPQ3[0,16] = TMPQ1[0,16] * TMPQ2[0,16]; + TMPQ3[16,16] = TMPQ1[16,16] * TMPQ2[16,16]; + TMPQ3[32,16] = TMPQ1[32,16] * TMPQ2[32,16]; + TMPQ3[48,16] = TMPQ1[48,16] * TMPQ2[48,16]; + TMPQ3[64,16] = TMPQ1[64,16] * TMPQ2[64,16]; + TMPQ3[80,16] = TMPQ1[80,16] * TMPQ2[80,16]; + TMPQ3[96,16] = TMPQ1[96,16] * TMPQ2[96,16]; + TMPQ3[112,16] = TMPQ1[112,16] * TMPQ2[112,16]; + # simd infix Rd_VPR128.8H = Rd_VPR128.8H - TMPQ3 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] - TMPQ3[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] - TMPQ3[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] - TMPQ3[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] - TMPQ3[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] - TMPQ3[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] - TMPQ3[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] - TMPQ3[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] - TMPQ3[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.371 UMOV page C7-2868 line 167415 MATCH x0e003c00/mask=xbfe0fc00 +# CONSTRUCT x0e013c00/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =zext:4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_umov/1 +# AUNIT --inst x0e013c00/mask=xffe1fc00 --status pass + +:umov Rd_GPR32, Rn_VPR128.B.imm_neon_uimm4 +is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x7 & b_1010=1 & Rn_VPR128 & Rd_GPR32 & Rd_GPR64 +{ + # simd element Rn_VPR128[imm_neon_uimm4] lane size 1 + local tmp1:1 = Rn_VPR128.B.imm_neon_uimm4; + Rd_GPR32 = zext(tmp1); + zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64 +} + +# C7.2.371 UMOV page C7-2868 line 167415 MATCH x0e003c00/mask=xbfe0fc00 +# CONSTRUCT x0e023c00/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =zext:4 +# SMACRO(pseudo) ARG1 ARG2 =NEON_umov/1 +# AUNIT --inst x0e023c00/mask=xffe3fc00 --status pass + +:umov Rd_GPR32, Rn_VPR128.H.imm_neon_uimm3 +is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x7 & b_1010=1 & Rn_VPR128 & Rd_GPR32 & Rd_GPR64 & Rd_VPR128 +{ + # simd element Rn_VPR128[imm_neon_uimm3] lane size 2 + local tmp1:2 = Rn_VPR128.H.imm_neon_uimm3; + Rd_GPR32 = zext(tmp1); + zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64 +} + +# C7.2.372 UMULL, UMULL2 (by element) page C7-2870 line 167549 MATCH x2f00a000/mask=xbf00f400 +# CONSTRUCT x6f80a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3 zext:8 =$* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull2/2@4 +# AUNIT --inst x6f80a000/mask=xffc0f400 --status pass --comment "ext" + +:umull2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex +is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xa & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = zext(TMPD1[0,32]); + TMPQ2[64,64] = zext(TMPD1[32,32]); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp3:4 = Re_VPR128.S.vIndex; + local tmp4:8 = zext(tmp3); + # simd infix Rd_VPR128.2D = TMPQ2 * tmp4 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ2[0,64] * tmp4; + Rd_VPR128.2D[64,64] = TMPQ2[64,64] * tmp4; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.372 UMULL, UMULL2 (by element) page C7-2870 line 167549 MATCH x2f00a000/mask=xbf00f400 +# CONSTRUCT x6f40a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3 zext:4 =$* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull2/2@2 +# AUNIT --inst x6f40a000/mask=xffc0f400 --status pass --comment "ext" + +:umull2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM +is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xa & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = zext(TMPD1[0,16]); + TMPQ2[32,32] = zext(TMPD1[16,16]); + TMPQ2[64,32] = zext(TMPD1[32,16]); + TMPQ2[96,32] = zext(TMPD1[48,16]); + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp3:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp4:4 = zext(tmp3); + # simd infix Rd_VPR128.4S = TMPQ2 * tmp4 on lane size 4 + Rd_VPR128.4S[0,32] = TMPQ2[0,32] * tmp4; + Rd_VPR128.4S[32,32] = TMPQ2[32,32] * tmp4; + Rd_VPR128.4S[64,32] = TMPQ2[64,32] * tmp4; + Rd_VPR128.4S[96,32] = TMPQ2[96,32] * tmp4; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.372 UMULL, UMULL2 (by element) page C7-2870 line 167549 MATCH x2f00a000/mask=xbf00f400 +# CONSTRUCT x2f80a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@4:16 ARG3 zext:8 =$* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull/2@4 +# AUNIT --inst x2f80a000/mask=xffc0f400 --status pass --comment "ext" + +:umull Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex +is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xa & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]); + # simd element Re_VPR128.S[vIndex] lane size 4 + local tmp2:4 = Re_VPR128.S.vIndex; + local tmp3:8 = zext(tmp2); + # simd infix Rd_VPR128.2D = TMPQ1 * tmp3 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ1[0,64] * tmp3; + Rd_VPR128.2D[64,64] = TMPQ1[64,64] * tmp3; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.372 UMULL, UMULL2 (by element) page C7-2870 line 167549 MATCH x2f00a000/mask=xbf00f400 +# CONSTRUCT x2f40a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@2:16 ARG3 zext:4 =$* +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull/2@2 +# AUNIT --inst x2f40a000/mask=xffc0f400 --status pass --comment "ext" + +:umull Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM +is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xa & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]); + # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2 + local tmp2:2 = Re_VPR128Lo.H.vIndexHLM; + local tmp3:4 = zext(tmp2); + # simd infix Rd_VPR128.4S = TMPQ1 * tmp3 on lane size 4 + Rd_VPR128.4S[0,32] = TMPQ1[0,32] * tmp3; + Rd_VPR128.4S[32,32] = TMPQ1[32,32] * tmp3; + Rd_VPR128.4S[64,32] = TMPQ1[64,32] * tmp3; + Rd_VPR128.4S[96,32] = TMPQ1[96,32] * tmp3; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.373 UMULL, UMULL2 (vector) page C7-2873 line 167705 MATCH x2e20c000/mask=xbf20fc00 +# CONSTRUCT x6ea0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 =$*@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull2/2@4 +# AUNIT --inst x6ea0c000/mask=xffe0fc00 --status pass --comment "ext" + +:umull2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0xc & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = zext(TMPD1[0,32]); + TMPQ2[64,64] = zext(TMPD1[32,32]); + TMPD3 = Rm_VPR128.4S[64,64]; + # simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8) + TMPQ4[0,64] = zext(TMPD3[0,32]); + TMPQ4[64,64] = zext(TMPD3[32,32]); + # simd infix Rd_VPR128.2D = TMPQ2 * TMPQ4 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ2[0,64] * TMPQ4[0,64]; + Rd_VPR128.2D[64,64] = TMPQ2[64,64] * TMPQ4[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.373 UMULL, UMULL2 (vector) page C7-2873 line 167705 MATCH x2e20c000/mask=xbf20fc00 +# CONSTRUCT x6e60c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 =$*@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull2/2@2 +# AUNIT --inst x6e60c000/mask=xffe0fc00 --status pass --comment "ext" + +:umull2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0xc & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = zext(TMPD1[0,16]); + TMPQ2[32,32] = zext(TMPD1[16,16]); + TMPQ2[64,32] = zext(TMPD1[32,16]); + TMPQ2[96,32] = zext(TMPD1[48,16]); + TMPD3 = Rm_VPR128.8H[64,64]; + # simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4) + TMPQ4[0,32] = zext(TMPD3[0,16]); + TMPQ4[32,32] = zext(TMPD3[16,16]); + TMPQ4[64,32] = zext(TMPD3[32,16]); + TMPQ4[96,32] = zext(TMPD3[48,16]); + # simd infix Rd_VPR128.4S = TMPQ2 * TMPQ4 on lane size 4 + Rd_VPR128.4S[0,32] = TMPQ2[0,32] * TMPQ4[0,32]; + Rd_VPR128.4S[32,32] = TMPQ2[32,32] * TMPQ4[32,32]; + Rd_VPR128.4S[64,32] = TMPQ2[64,32] * TMPQ4[64,32]; + Rd_VPR128.4S[96,32] = TMPQ2[96,32] * TMPQ4[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.373 UMULL, UMULL2 (vector) page C7-2873 line 167705 MATCH x2e20c000/mask=xbf20fc00 +# CONSTRUCT x6e20c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 =$*@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull2/2@1 +# AUNIT --inst x6e20c000/mask=xffe0fc00 --status pass --comment "ext" + +:umull2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0xc & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd +{ + TMPD1 = Rn_VPR128.16B[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2) + TMPQ2[0,16] = zext(TMPD1[0,8]); + TMPQ2[16,16] = zext(TMPD1[8,8]); + TMPQ2[32,16] = zext(TMPD1[16,8]); + TMPQ2[48,16] = zext(TMPD1[24,8]); + TMPQ2[64,16] = zext(TMPD1[32,8]); + TMPQ2[80,16] = zext(TMPD1[40,8]); + TMPQ2[96,16] = zext(TMPD1[48,8]); + TMPQ2[112,16] = zext(TMPD1[56,8]); + TMPD3 = Rm_VPR128.16B[64,64]; + # simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2) + TMPQ4[0,16] = zext(TMPD3[0,8]); + TMPQ4[16,16] = zext(TMPD3[8,8]); + TMPQ4[32,16] = zext(TMPD3[16,8]); + TMPQ4[48,16] = zext(TMPD3[24,8]); + TMPQ4[64,16] = zext(TMPD3[32,8]); + TMPQ4[80,16] = zext(TMPD3[40,8]); + TMPQ4[96,16] = zext(TMPD3[48,8]); + TMPQ4[112,16] = zext(TMPD3[56,8]); + # simd infix Rd_VPR128.8H = TMPQ2 * TMPQ4 on lane size 2 + Rd_VPR128.8H[0,16] = TMPQ2[0,16] * TMPQ4[0,16]; + Rd_VPR128.8H[16,16] = TMPQ2[16,16] * TMPQ4[16,16]; + Rd_VPR128.8H[32,16] = TMPQ2[32,16] * TMPQ4[32,16]; + Rd_VPR128.8H[48,16] = TMPQ2[48,16] * TMPQ4[48,16]; + Rd_VPR128.8H[64,16] = TMPQ2[64,16] * TMPQ4[64,16]; + Rd_VPR128.8H[80,16] = TMPQ2[80,16] * TMPQ4[80,16]; + Rd_VPR128.8H[96,16] = TMPQ2[96,16] * TMPQ4[96,16]; + Rd_VPR128.8H[112,16] = TMPQ2[112,16] * TMPQ4[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.373 UMULL, UMULL2 (vector) page C7-2873 line 167705 MATCH x2e20c000/mask=xbf20fc00 +# CONSTRUCT x2ea0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull/2@4 +# AUNIT --inst x2ea0c000/mask=xffe0fc00 --status nopcodeop --comment "ext" + +:umull Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0xc & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_umull(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.373 UMULL, UMULL2 (vector) page C7-2873 line 167705 MATCH x2e20c000/mask=xbf20fc00 +# CONSTRUCT x2e60c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull/2@2 +# AUNIT --inst x2e60c000/mask=xffe0fc00 --status nopcodeop --comment "ext" + +:umull Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0xc & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_umull(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.373 UMULL, UMULL2 (vector) page C7-2873 line 167705 MATCH x2e20c000/mask=xbf20fc00 +# CONSTRUCT x2e20c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull/2@1 +# AUNIT --inst x2e20c000/mask=xffe0fc00 --status nopcodeop --comment "ext" + +:umull Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0xc & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_umull(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.374 UQADD page C7-2875 line 167821 MATCH x7e200c00/mask=xff20fc00 +# CONSTRUCT x7e200c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2 +# AUNIT --inst x7e200c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:uqadd Rd_FPR8, Rn_FPR8, Rm_FPR8 +is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0x1 & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd +{ + Rd_FPR8 = NEON_uqadd(Rn_FPR8, Rm_FPR8); +} + +# C7.2.374 UQADD page C7-2875 line 167821 MATCH x7e200c00/mask=xff20fc00 +# CONSTRUCT x7ee00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2 +# AUNIT --inst x7ee00c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:uqadd Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x1 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_uqadd(Rn_FPR64, Rm_FPR64); +} + +# C7.2.374 UQADD page C7-2875 line 167821 MATCH x7e200c00/mask=xff20fc00 +# CONSTRUCT x7e600c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2 +# AUNIT --inst x7e600c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:uqadd Rd_FPR16, Rn_FPR16, Rm_FPR16 +is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x1 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_uqadd(Rn_FPR16, Rm_FPR16); +} + +# C7.2.374 UQADD page C7-2875 line 167821 MATCH x7e200c00/mask=xff20fc00 +# CONSTRUCT x7ea00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2 +# AUNIT --inst x7ea00c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:uqadd Rd_FPR32, Rn_FPR32, Rm_FPR32 +is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x1 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_uqadd(Rn_FPR32, Rm_FPR32); +} + +# C7.2.374 UQADD page C7-2875 line 167821 MATCH x2e200c00/mask=xbf20fc00 +# CONSTRUCT x6e200c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@1 +# AUNIT --inst x6e200c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:uqadd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x1 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_uqadd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.374 UQADD page C7-2875 line 167821 MATCH x2e200c00/mask=xbf20fc00 +# CONSTRUCT x6ee00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@8 +# AUNIT --inst x6ee00c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:uqadd Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x1 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_uqadd(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.374 UQADD page C7-2875 line 167821 MATCH x2e200c00/mask=xbf20fc00 +# CONSTRUCT x2ea00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@4 +# AUNIT --inst x2ea00c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:uqadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x1 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_uqadd(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.374 UQADD page C7-2875 line 167821 MATCH x2e200c00/mask=xbf20fc00 +# CONSTRUCT x2e600c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@2 +# AUNIT --inst x2e600c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:uqadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x1 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_uqadd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.374 UQADD page C7-2875 line 167821 MATCH x2e200c00/mask=xbf20fc00 +# CONSTRUCT x6ea00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@4 +# AUNIT --inst x6ea00c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:uqadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x1 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_uqadd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.374 UQADD page C7-2875 line 167821 MATCH x2e200c00/mask=xbf20fc00 +# CONSTRUCT x2e200c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@1 +# AUNIT --inst x2e200c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:uqadd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x1 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_uqadd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.374 UQADD page C7-2875 line 167821 MATCH x2e200c00/mask=xbf20fc00 +# CONSTRUCT x6e600c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@2 +# AUNIT --inst x6e600c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:uqadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x1 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_uqadd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x7e205c00/mask=xff20fc00 +# CONSTRUCT x7e205c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2 +# AUNIT --inst x7e205c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqrshl Rd_FPR8, Rn_FPR8, Rm_FPR8 +is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0xb & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd +{ + Rd_FPR8 = NEON_uqrshl(Rn_FPR8, Rm_FPR8); +} + +# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x7e205c00/mask=xff20fc00 +# CONSTRUCT x7ee05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2 +# AUNIT --inst x7ee05c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqrshl Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0xb & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_uqrshl(Rn_FPR64, Rm_FPR64); +} + +# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x7e205c00/mask=xff20fc00 +# CONSTRUCT x7e605c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2 +# AUNIT --inst x7e605c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqrshl Rd_FPR16, Rn_FPR16, Rm_FPR16 +is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0xb & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_uqrshl(Rn_FPR16, Rm_FPR16); +} + +# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x7e205c00/mask=xff20fc00 +# CONSTRUCT x7ea05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2 +# AUNIT --inst x7ea05c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqrshl Rd_FPR32, Rn_FPR32, Rm_FPR32 +is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0xb & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_uqrshl(Rn_FPR32, Rm_FPR32); +} + +# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x2e205c00/mask=xbf20fc00 +# CONSTRUCT x6e205c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@1 +# AUNIT --inst x6e205c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqrshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xb & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_uqrshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x2e205c00/mask=xbf20fc00 +# CONSTRUCT x6ee05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@8 +# AUNIT --inst x6ee05c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqrshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0xb & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_uqrshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x2e205c00/mask=xbf20fc00 +# CONSTRUCT x2ea05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@4 +# AUNIT --inst x2ea05c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqrshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xb & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_uqrshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x2e205c00/mask=xbf20fc00 +# CONSTRUCT x2e605c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@2 +# AUNIT --inst x2e605c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqrshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xb & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_uqrshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x2e205c00/mask=xbf20fc00 +# CONSTRUCT x6ea05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@4 +# AUNIT --inst x6ea05c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqrshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xb & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_uqrshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x2e205c00/mask=xbf20fc00 +# CONSTRUCT x2e205c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@1 +# AUNIT --inst x2e205c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqrshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xb & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_uqrshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x2e205c00/mask=xbf20fc00 +# CONSTRUCT x6e605c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@2 +# AUNIT --inst x6e605c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqrshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xb & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_uqrshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x2f009c00/mask=xbf80fc00 +# CONSTRUCT x6f089c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn2/2@2 +# AUNIT --inst x6f089c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat" + +:uqrshrn2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x13 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_uqrshrn2(Rn_VPR128.8H, Imm_shr_imm8:1, 2:1); +} + +# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x2f009c00/mask=xbf80fc00 +# CONSTRUCT x2f209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2@8 +# AUNIT --inst x2f209c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:uqrshrn Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x13 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_uqrshrn(Rn_VPR128.2D, Imm_shr_imm32:1, 8:1); +} + +# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x2f009c00/mask=xbf80fc00 +# CONSTRUCT x2f109c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2@4 +# AUNIT --inst x2f109c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat" + +:uqrshrn Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x13 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_uqrshrn(Rn_VPR128.4S, Imm_shr_imm16:1, 4:1); +} + +# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x2f009c00/mask=xbf80fc00 +# CONSTRUCT x6f209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2@8 +# AUNIT --inst x6f209c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" + +:uqrshrn2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x13 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_uqrshrn(Rn_VPR128.2D, Imm_shr_imm32:1, 8:1); +} + +# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x2f009c00/mask=xbf80fc00 +# CONSTRUCT x2f089c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2@2 +# AUNIT --inst x2f089c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat" + +:uqrshrn Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x13 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_uqrshrn(Rn_VPR128.8H, Imm_shr_imm8:1, 2:1); +} + +# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x2f009c00/mask=xbf80fc00 +# CONSTRUCT x6f109c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn2/2@4 +# AUNIT --inst x6f109c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat" + +:uqrshrn2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x13 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_uqrshrn2(Rn_VPR128.4S, Imm_shr_imm16:1, 4:1); +} + +# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x7f009c00/mask=xff80fc00 +# CONSTRUCT x7f089c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2 +# AUNIT --inst x7f089c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat" +# Scalar variant when immh=0001 Va=FPR16 Vb=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001 + +:uqrshrn Rd_FPR8, Rn_FPR16, Imm_shr_imm8 +is b_2331=0b011111110 & b_1922=0b0001 & b_1015=0b100111 & Rd_FPR8 & Rn_FPR16 & Imm_shr_imm8 & Zd +{ + Rd_FPR8 = NEON_uqrshrn(Rn_FPR16, Imm_shr_imm8:1); +} + +# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x7f009c00/mask=xff80fc00 +# CONSTRUCT x7f109c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2 +# AUNIT --inst x7f109c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat" +# Scalar variant when immh=001x Va=FPR32 Vb=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001 + +:uqrshrn Rd_FPR16, Rn_FPR32, Imm_shr_imm16 +is b_2331=0b011111110 & b_2022=0b001 & b_1015=0b100111 & Rd_FPR16 & Rn_FPR32 & Imm_shr_imm16 & Zd +{ + Rd_FPR16 = NEON_uqrshrn(Rn_FPR32, Imm_shr_imm16:1); +} + +# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x7f009c00/mask=xff80fc00 +# CONSTRUCT x7f209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2 +# AUNIT --inst x7f209c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat" +# Scalar variant when immh=01xx Va=FPR64 Vb=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01 + +:uqrshrn Rd_FPR32, Rn_FPR64, Imm_shr_imm32 +is b_2331=0b011111110 & b_2122=0b01 & b_1015=0b100111 & Rd_FPR32 & Rn_FPR64 & Imm_shr_imm32 & Zd +{ + Rd_FPR32 = NEON_uqrshrn(Rn_FPR64, Imm_shr_imm32:1); +} + +# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00 +# CONSTRUCT x6f087400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@1 +# AUNIT --inst x6f087400/mask=xfff8fc00 --status nopcodeop --comment "nointsat" + +:uqshl Rd_VPR128.16B, Rn_VPR128.16B, Imm_uimm3 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xe & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_uqshl(Rn_VPR128.16B, Imm_uimm3:1, 1:1); +} + +# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00 +# CONSTRUCT x6f407400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@8 +# AUNIT --inst x6f407400/mask=xffc0fc00 --status nopcodeop --comment "nointsat" + +:uqshl Rd_VPR128.2D, Rn_VPR128.2D, Imm_imm0_63 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_imm0_63 & b_1115=0xe & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_uqshl(Rn_VPR128.2D, Imm_imm0_63:1, 8:1); +} + +# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00 +# CONSTRUCT x2f207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@4 +# AUNIT --inst x2f207400/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqshl Rd_VPR64.2S, Rn_VPR64.2S, Imm_uimm5 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xe & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_uqshl(Rn_VPR64.2S, Imm_uimm5:1, 4:1); +} + +# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00 +# CONSTRUCT x2f107400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@2 +# AUNIT --inst x2f107400/mask=xfff0fc00 --status nopcodeop --comment "nointsat" + +:uqshl Rd_VPR64.4H, Rn_VPR64.4H, Imm_uimm4 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xe & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_uqshl(Rn_VPR64.4H, Imm_uimm4:1, 2:1); +} + +# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00 +# CONSTRUCT x6f207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@4 +# AUNIT --inst x6f207400/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqshl Rd_VPR128.4S, Rn_VPR128.4S, Imm_uimm5 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xe & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_uqshl(Rn_VPR128.4S, Imm_uimm5:1, 4:1); +} + +# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00 +# CONSTRUCT x2f087400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@1 +# AUNIT --inst x2f087400/mask=xfff8fc00 --status nopcodeop --comment "nointsat" + +:uqshl Rd_VPR64.8B, Rn_VPR64.8B, Imm_uimm3 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xe & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_uqshl(Rn_VPR64.8B, Imm_uimm3:1, 1:1); +} + +# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00 +# CONSTRUCT x6f107400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@2 +# AUNIT --inst x6f107400/mask=xfff0fc00 --status nopcodeop --comment "nointsat" + +:uqshl Rd_VPR128.8H, Rn_VPR128.8H, Imm_uimm4 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xe & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_uqshl(Rn_VPR128.8H, Imm_uimm4:1, 2:1); +} + +# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x7f007400/mask=xff80fc00 +# CONSTRUCT x7f087400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2 +# AUNIT --inst x7f087400/mask=xfff8fc00 --status nopcodeop --comment "nointsat" +# Scalar variant when immh=0001 V=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001 + +:uqshl Rd_FPR8, Rn_FPR8, Imm_shr_imm8 +is b_2331=0b011111110 & b_1922=0b0001 & b_1015=0b011101 & Rd_FPR8 & Rn_FPR8 & Imm_shr_imm8 & Zd +{ + Rd_FPR8 = NEON_uqshl(Rn_FPR8, Imm_shr_imm8:1); +} + +# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x7f007400/mask=xff80fc00 +# CONSTRUCT x7f107400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2 +# AUNIT --inst x7f107400/mask=xfff0fc00 --status nopcodeop --comment "nointsat" +# Scalar variant when immh=001x V=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001 + +:uqshl Rd_FPR16, Rn_FPR16, Imm_shr_imm16 +is b_2331=0b011111110 & b_2022=0b001 & b_1015=0b011101 & Rd_FPR16 & Rn_FPR16 & Imm_shr_imm16 & Zd +{ + Rd_FPR16 = NEON_uqshl(Rn_FPR16, Imm_shr_imm16:1); +} + +# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x7f007400/mask=xff80fc00 +# CONSTRUCT x7f207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2 +# AUNIT --inst x7f207400/mask=xffe0fc00 --status nopcodeop --comment "nointsat" +# Scalar variant when immh=01xx V=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01 + +:uqshl Rd_FPR32, Rn_FPR32, Imm_shr_imm32 +is b_2331=0b011111110 & b_2122=0b01 & b_1015=0b011101 & Rd_FPR32 & Rn_FPR32 & Imm_shr_imm32 & Zd +{ + Rd_FPR32 = NEON_uqshl(Rn_FPR32, Imm_shr_imm32:1); +} + +# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x7f007400/mask=xff80fc00 +# CONSTRUCT x7f407400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2 +# AUNIT --inst x7f407400/mask=xffc0fc00 --status nopcodeop --comment "nointsat" +# Scalar variant when immh=1xxx V=FPR64 imm=Imm_shr_imm64 bb=b_22 aa=1 + +:uqshl Rd_FPR64, Rn_FPR64, Imm_shr_imm64 +is b_2331=0b011111110 & b_22=1 & b_1015=0b011101 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd +{ + Rd_FPR64 = NEON_uqshl(Rn_FPR64, Imm_shr_imm64:1); +} + +# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x7e204c00/mask=xff20fc00 +# CONSTRUCT x7e204c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2 +# AUNIT --inst x7e204c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqshl Rd_FPR8, Rn_FPR8, Rm_FPR8 +is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0x9 & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd +{ + Rd_FPR8 = NEON_uqshl(Rn_FPR8, Rm_FPR8); +} + +# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x7e204c00/mask=xff20fc00 +# CONSTRUCT x7ee04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2 +# AUNIT --inst x7ee04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqshl Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x9 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_uqshl(Rn_FPR64, Rm_FPR64); +} + +# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x7e204c00/mask=xff20fc00 +# CONSTRUCT x7e604c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2 +# AUNIT --inst x7e604c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqshl Rd_FPR16, Rn_FPR16, Rm_FPR16 +is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x9 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_uqshl(Rn_FPR16, Rm_FPR16); +} + +# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x7e204c00/mask=xff20fc00 +# CONSTRUCT x7ea04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2 +# AUNIT --inst x7ea04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqshl Rd_FPR32, Rn_FPR32, Rm_FPR32 +is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x9 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_uqshl(Rn_FPR32, Rm_FPR32); +} + +# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x2e204c00/mask=xbf20fc00 +# CONSTRUCT x6e204c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@1 +# AUNIT --inst x6e204c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x9 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_uqshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x2e204c00/mask=xbf20fc00 +# CONSTRUCT x6ee04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@8 +# AUNIT --inst x6ee04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x9 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_uqshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x2e204c00/mask=xbf20fc00 +# CONSTRUCT x2ea04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@4 +# AUNIT --inst x2ea04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x9 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_uqshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x2e204c00/mask=xbf20fc00 +# CONSTRUCT x2e604c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@2 +# AUNIT --inst x2e604c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x9 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_uqshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x2e204c00/mask=xbf20fc00 +# CONSTRUCT x6ea04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@4 +# AUNIT --inst x6ea04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x9 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_uqshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x2e204c00/mask=xbf20fc00 +# CONSTRUCT x2e204c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@1 +# AUNIT --inst x2e204c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x9 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_uqshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x2e204c00/mask=xbf20fc00 +# CONSTRUCT x6e604c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@2 +# AUNIT --inst x6e604c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x9 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_uqshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x2f009400/mask=xbf80fc00 +# CONSTRUCT x6f089400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn2/3@2 +# AUNIT --inst x6f089400/mask=xfff8fc00 --status nopcodeop --comment "nointsat" + +:uqshrn2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x12 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_uqshrn2(Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1); +} + +# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x2f009400/mask=xbf80fc00 +# CONSTRUCT x2f209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn/3@8 +# AUNIT --inst x2f209400/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqshrn Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x12 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_uqshrn(Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1); +} + +# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x2f009400/mask=xbf80fc00 +# CONSTRUCT x2f109400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn/3@4 +# AUNIT --inst x2f109400/mask=xfff0fc00 --status nopcodeop --comment "nointsat" + +:uqshrn Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x12 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_uqshrn(Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1); +} + +# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x2f009400/mask=xbf80fc00 +# CONSTRUCT x6f209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn2/3@8 +# AUNIT --inst x6f209400/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqshrn2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x12 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_uqshrn2(Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1); +} + +# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x2f009400/mask=xbf80fc00 +# CONSTRUCT x2f089400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn/3@2 +# AUNIT --inst x2f089400/mask=xfff8fc00 --status nopcodeop --comment "nointsat" + +:uqshrn Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x12 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_uqshrn(Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1); +} + +# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x2f009400/mask=xbf80fc00 +# CONSTRUCT x6f109400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn2/3@4 +# AUNIT --inst x6f109400/mask=xfff0fc00 --status nopcodeop --comment "nointsat" + +:uqshrn2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x12 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_uqshrn2(Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1); +} + +# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x7f009400/mask=xff80fc00 +# CONSTRUCT x7f089400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn/3 +# AUNIT --inst x7f089400/mask=xfff8fc00 --status nopcodeop --comment "nointsat" +# Scalar variant when immh=0001 Va=FPR16 Vb=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001 + +:uqshrn Rd_FPR8, Rn_FPR16, Imm_shr_imm8 +is b_2331=0b011111110 & b_1922=0b0001 & b_1015=0b100101 & Rd_FPR8 & Rn_FPR16 & Imm_shr_imm8 & Zd +{ + Rd_FPR8 = NEON_uqshrn(Rd_FPR8, Rn_FPR16, Imm_shr_imm8:1); +} + +# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x7f009400/mask=xff80fc00 +# CONSTRUCT x7f109400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn/3 +# AUNIT --inst x7f109400/mask=xfff0fc00 --status nopcodeop --comment "nointsat" +# Scalar variant when immh=001x Va=FPR32 Vb=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001 + +:uqshrn Rd_FPR16, Rn_FPR32, Imm_shr_imm16 +is b_2331=0b011111110 & b_2022=0b001 & b_1015=0b100101 & Rd_FPR16 & Rn_FPR32 & Imm_shr_imm16 & Zd +{ + Rd_FPR16 = NEON_uqshrn(Rd_FPR16, Rn_FPR32, Imm_shr_imm16:1); +} + +# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x7f009400/mask=xff80fc00 +# CONSTRUCT x7f209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn/3 +# AUNIT --inst x7f209400/mask=xffe0fc00 --status nopcodeop --comment "nointsat" +# Scalar variant when immh=01xx Va=FPR64 Vb=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01 + +:uqshrn Rd_FPR32, Rn_FPR64, Imm_shr_imm32 +is b_2331=0b011111110 & b_2122=0b01 & b_1015=0b100101 & Rd_FPR32 & Rn_FPR64 & Imm_shr_imm32 & Zd +{ + Rd_FPR32 = NEON_uqshrn(Rd_FPR32, Rn_FPR64, Imm_shr_imm32:1); +} + +# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x7e202c00/mask=xff20fc00 +# CONSTRUCT x7e202c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2 +# AUNIT --inst x7e202c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqsub Rd_FPR8, Rn_FPR8, Rm_FPR8 +is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0x5 & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd +{ + Rd_FPR8 = NEON_uqsub(Rn_FPR8, Rm_FPR8); +} + +# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x7e202c00/mask=xff20fc00 +# CONSTRUCT x7ee02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2 +# AUNIT --inst x7ee02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqsub Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x5 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_uqsub(Rn_FPR64, Rm_FPR64); +} + +# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x7e202c00/mask=xff20fc00 +# CONSTRUCT x7e602c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2 +# AUNIT --inst x7e602c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqsub Rd_FPR16, Rn_FPR16, Rm_FPR16 +is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x5 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd +{ + Rd_FPR16 = NEON_uqsub(Rn_FPR16, Rm_FPR16); +} + +# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x7e202c00/mask=xff20fc00 +# CONSTRUCT x7ea02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2 +# AUNIT --inst x7ea02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqsub Rd_FPR32, Rn_FPR32, Rm_FPR32 +is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x5 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd +{ + Rd_FPR32 = NEON_uqsub(Rn_FPR32, Rm_FPR32); +} + +# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x2e202c00/mask=xbf20fc00 +# CONSTRUCT x6e202c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@1 +# AUNIT --inst x6e202c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqsub Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x5 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_uqsub(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x2e202c00/mask=xbf20fc00 +# CONSTRUCT x6ee02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@8 +# AUNIT --inst x6ee02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqsub Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x5 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_uqsub(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x2e202c00/mask=xbf20fc00 +# CONSTRUCT x2ea02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@4 +# AUNIT --inst x2ea02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqsub Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x5 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_uqsub(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x2e202c00/mask=xbf20fc00 +# CONSTRUCT x2e602c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@2 +# AUNIT --inst x2e602c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqsub Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x5 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_uqsub(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x2e202c00/mask=xbf20fc00 +# CONSTRUCT x6ea02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@4 +# AUNIT --inst x6ea02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqsub Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x5 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_uqsub(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x2e202c00/mask=xbf20fc00 +# CONSTRUCT x2e202c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@1 +# AUNIT --inst x2e202c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqsub Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x5 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_uqsub(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x2e202c00/mask=xbf20fc00 +# CONSTRUCT x6e602c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@2 +# AUNIT --inst x6e602c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat" + +:uqsub Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x5 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_uqsub(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x7e214800/mask=xff3ffc00 +# CONSTRUCT x7e214800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn/2 +# AUNIT --inst x7e214800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Scalar variant when size=00 Q=1 bb=1 mnemonic=uqxtn Ta=FPR16 Tb=FPR8 + +:uqxtn Rd_FPR8, Rn_FPR16 +is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b00 & b_1021=0b100001010010 & Rd_FPR8 & Rn_FPR16 & Zd +{ + Rd_FPR8 = NEON_uqxtn(Rd_FPR8, Rn_FPR16); +} + +# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x7e214800/mask=xff3ffc00 +# CONSTRUCT x7e614800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn/2 +# AUNIT --inst x7e614800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Scalar variant when size=01 Q=1 bb=1 mnemonic=uqxtn Ta=FPR32 Tb=FPR16 + +:uqxtn Rd_FPR16, Rn_FPR32 +is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b01 & b_1021=0b100001010010 & Rd_FPR16 & Rn_FPR32 & Zd +{ + Rd_FPR16 = NEON_uqxtn(Rd_FPR16, Rn_FPR32); +} + +# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x7e214800/mask=xff3ffc00 +# CONSTRUCT x7ea14800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn/2 +# AUNIT --inst x7ea14800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Scalar variant when size=10 Q=1 bb=1 mnemonic=uqxtn Ta=FPR64 Tb=FPR32 + +:uqxtn Rd_FPR32, Rn_FPR64 +is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b10 & b_1021=0b100001010010 & Rd_FPR32 & Rn_FPR64 & Zd +{ + Rd_FPR32 = NEON_uqxtn(Rd_FPR32, Rn_FPR64); +} + +# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x2e214800/mask=xbf3ffc00 +# CONSTRUCT x2e214800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn/2@2 +# AUNIT --inst x2e214800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Vector variant when size=00 Q=0 bb=0 mnemonic=uqxtn e=2 Ta=VPR128.8H Tb=VPR64.8B + +:uqxtn Rd_VPR64.8B, Rn_VPR128.8H +is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100001010010 & Rd_VPR64.8B & Rn_VPR128.8H & Zd +{ + Rd_VPR64.8B = NEON_uqxtn(Rd_VPR64.8B, Rn_VPR128.8H, 2:1); +} + +# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x2e214800/mask=xbf3ffc00 +# CONSTRUCT x6e214800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn2/2@2 +# AUNIT --inst x6e214800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Vector variant when size=00 Q=1 bb=0 mnemonic=uqxtn2 e=2 Ta=VPR128.8H Tb=VPR128.16B + +:uqxtn2 Rd_VPR128.16B, Rn_VPR128.8H +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100001010010 & Rd_VPR128.16B & Rn_VPR128.8H & Zd +{ + Rd_VPR128.16B = NEON_uqxtn2(Rd_VPR128.16B, Rn_VPR128.8H, 2:1); +} + +# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x2e214800/mask=xbf3ffc00 +# CONSTRUCT x2e614800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn/2@4 +# AUNIT --inst x2e614800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Vector variant when size=01 Q=0 bb=0 mnemonic=uqxtn e=4 Ta=VPR128.4S Tb=VPR64.4H + +:uqxtn Rd_VPR64.4H, Rn_VPR128.4S +is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100001010010 & Rd_VPR64.4H & Rn_VPR128.4S & Zd +{ + Rd_VPR64.4H = NEON_uqxtn(Rd_VPR64.4H, Rn_VPR128.4S, 4:1); +} + +# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x2e214800/mask=xbf3ffc00 +# CONSTRUCT x6e614800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn2/2@4 +# AUNIT --inst x6e614800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Vector variant when size=01 Q=1 bb=0 mnemonic=uqxtn2 e=4 Ta=VPR128.4S Tb=VPR128.8H + +:uqxtn2 Rd_VPR128.8H, Rn_VPR128.4S +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100001010010 & Rd_VPR128.8H & Rn_VPR128.4S & Zd +{ + Rd_VPR128.8H = NEON_uqxtn2(Rd_VPR128.8H, Rn_VPR128.4S, 4:1); +} + +# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x2e214800/mask=xbf3ffc00 +# CONSTRUCT x2ea14800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn/2@8 +# AUNIT --inst x2ea14800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Vector variant when size=10 Q=0 bb=0 mnemonic=uqxtn e=8 Ta=VPR128.2D Tb=VPR64.2S + +:uqxtn Rd_VPR64.2S, Rn_VPR128.2D +is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100001010010 & Rd_VPR64.2S & Rn_VPR128.2D & Zd +{ + Rd_VPR64.2S = NEON_uqxtn(Rd_VPR64.2S, Rn_VPR128.2D, 8:1); +} + +# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x2e214800/mask=xbf3ffc00 +# CONSTRUCT x6ea14800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn2/2@8 +# AUNIT --inst x6ea14800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Vector variant when size=10 Q=1 bb=0 mnemonic=uqxtn2 e=8 Ta=VPR128.2D Tb=VPR128.4S + +:uqxtn2 Rd_VPR128.4S, Rn_VPR128.2D +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100001010010 & Rd_VPR128.4S & Rn_VPR128.2D & Zd +{ + Rd_VPR128.4S = NEON_uqxtn2(Rd_VPR128.4S, Rn_VPR128.2D, 8:1); +} + +# C7.2.382 URECPE page C7-2895 line 169051 MATCH x0ea1c800/mask=xbfbffc00 +# CONSTRUCT x0ea1c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_urecpe/1@4 +# AUNIT --inst x0ea1c800/mask=xfffffc00 --status nopcodeop +# Vector variant when Q=0 T=VPR64.2S + +:urecpe Rd_VPR64.2S, Rn_VPR64.2S +is b_31=0 & b_30=0 & b_2329=0b0011101 & b_22=0 & b_1021=0b100001110010 & Rd_VPR64.2S & Rn_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_urecpe(Rn_VPR64.2S, 4:1); +} + +# C7.2.382 URECPE page C7-2895 line 169051 MATCH x0ea1c800/mask=xbfbffc00 +# CONSTRUCT x4ea1c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_urecpe/1@4 +# AUNIT --inst x4ea1c800/mask=xfffffc00 --status nopcodeop +# Vector variant when Q=1 T=VPR128.4S + +:urecpe Rd_VPR128.4S, Rn_VPR128.4S +is b_31=0 & b_30=1 & b_2329=0b0011101 & b_22=0 & b_1021=0b100001110010 & Rd_VPR128.4S & Rn_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_urecpe(Rn_VPR128.4S, 4:1); +} + +# C7.2.383 URHADD page C7-2896 line 169117 MATCH x2e201400/mask=xbf20fc00 +# CONSTRUCT x6e201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urhadd/2@1 +# AUNIT --inst x6e201400/mask=xffe0fc00 --status nopcodeop + +:urhadd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x2 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_urhadd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.383 URHADD page C7-2896 line 169117 MATCH x2e201400/mask=xbf20fc00 +# CONSTRUCT x2ea01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urhadd/2@2 +# AUNIT --inst x2ea01400/mask=xffe0fc00 --status nopcodeop + +:urhadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x2 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_urhadd(Rn_VPR64.2S, Rm_VPR64.2S, 2:1); +} + +# C7.2.383 URHADD page C7-2896 line 169117 MATCH x2e201400/mask=xbf20fc00 +# CONSTRUCT x2e601400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urhadd/2@2 +# AUNIT --inst x2e601400/mask=xffe0fc00 --status nopcodeop + +:urhadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x2 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_urhadd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.383 URHADD page C7-2896 line 169117 MATCH x2e201400/mask=xbf20fc00 +# CONSTRUCT x6ea01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urhadd/2@4 +# AUNIT --inst x6ea01400/mask=xffe0fc00 --status nopcodeop + +:urhadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x2 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_urhadd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.383 URHADD page C7-2896 line 169117 MATCH x2e201400/mask=xbf20fc00 +# CONSTRUCT x2e201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urhadd/2@1 +# AUNIT --inst x2e201400/mask=xffe0fc00 --status nopcodeop + +:urhadd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x2 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_urhadd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.383 URHADD page C7-2896 line 169117 MATCH x2e201400/mask=xbf20fc00 +# CONSTRUCT x6e601400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urhadd/2@2 +# AUNIT --inst x6e601400/mask=xffe0fc00 --status nopcodeop + +:urhadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x2 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_urhadd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.384 URSHL page C7-2898 line 169205 MATCH x7e205400/mask=xff20fc00 +# CONSTRUCT x7ee05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2 +# AUNIT --inst x7ee05400/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:urshl Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0xa & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_urshl(Rn_FPR64, Rm_FPR64); +} + +# C7.2.384 URSHL page C7-2898 line 169205 MATCH x2e205400/mask=xbf20fc00 +# CONSTRUCT x6e205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@1 +# AUNIT --inst x6e205400/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:urshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xa & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_urshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.384 URSHL page C7-2898 line 169205 MATCH x2e205400/mask=xbf20fc00 +# CONSTRUCT x6ee05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@8 +# AUNIT --inst x6ee05400/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:urshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0xa & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_urshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.384 URSHL page C7-2898 line 169205 MATCH x2e205400/mask=xbf20fc00 +# CONSTRUCT x2ea05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@4 +# AUNIT --inst x2ea05400/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:urshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xa & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_urshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.384 URSHL page C7-2898 line 169205 MATCH x2e205400/mask=xbf20fc00 +# CONSTRUCT x2e605400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@2 +# AUNIT --inst x2e605400/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:urshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xa & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_urshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.384 URSHL page C7-2898 line 169205 MATCH x2e205400/mask=xbf20fc00 +# CONSTRUCT x6ea05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@4 +# AUNIT --inst x6ea05400/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:urshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xa & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_urshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.384 URSHL page C7-2898 line 169205 MATCH x2e205400/mask=xbf20fc00 +# CONSTRUCT x2e205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@1 +# AUNIT --inst x2e205400/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:urshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xa & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_urshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.384 URSHL page C7-2898 line 169205 MATCH x2e205400/mask=xbf20fc00 +# CONSTRUCT x6e605400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@2 +# AUNIT --inst x6e605400/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:urshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xa & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_urshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00 +# CONSTRUCT x6f082400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@1 +# AUNIT --inst x6f082400/mask=xfff8fc00 --status nopcodeop --comment "nointround" + +:urshr Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x4 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_urshr(Rn_VPR128.16B, Imm_shr_imm8:1, 1:1); +} + +# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00 +# CONSTRUCT x6f402400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@8 +# AUNIT --inst x6f402400/mask=xffc0fc00 --status nopcodeop --comment "nointround" + +:urshr Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x4 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_urshr(Rn_VPR128.2D, Imm_shr_imm64:1, 8:1); +} + +# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00 +# CONSTRUCT x2f202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@4 +# AUNIT --inst x2f202400/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:urshr Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x4 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_urshr(Rn_VPR64.2S, Imm_shr_imm32:1, 4:1); +} + +# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00 +# CONSTRUCT x2f102400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@2 +# AUNIT --inst x2f102400/mask=xfff0fc00 --status nopcodeop --comment "nointround" + +:urshr Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x4 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_urshr(Rn_VPR64.4H, Imm_shr_imm16:1, 2:1); +} + +# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00 +# CONSTRUCT x6f202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@4 +# AUNIT --inst x6f202400/mask=xffe0fc00 --status nopcodeop --comment "nointround" + +:urshr Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x4 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_urshr(Rn_VPR128.4S, Imm_shr_imm32:1, 4:1); +} + +# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00 +# CONSTRUCT x2f082400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@1 +# AUNIT --inst x2f082400/mask=xfff8fc00 --status nopcodeop --comment "nointround" + +:urshr Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x4 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_urshr(Rn_VPR64.8B, Imm_shr_imm8:1, 1:1); +} + +# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00 +# CONSTRUCT x6f102400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@2 +# AUNIT --inst x6f102400/mask=xfff0fc00 --status nopcodeop --comment "nointround" + +:urshr Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x4 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_urshr(Rn_VPR128.8H, Imm_shr_imm16:1, 2:1); +} + +# C7.2.385 URSHR page C7-2900 line 169341 MATCH x7f002400/mask=xff80fc00 +# CONSTRUCT x7f402400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2 +# AUNIT --inst x7f402400/mask=xffc0fc00 --status nopcodeop --comment "nointround" +# Scalar variant + +:urshr Rd_FPR64, Rn_FPR64, Imm_shr_imm32 +is b_2331=0b011111110 & b_22=1 & b_1015=0b001001 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm32 & Zd +{ + Rd_FPR64 = NEON_urshr(Rn_FPR64, Imm_shr_imm32:1); +} + +# C7.2.386 URSQRTE page C7-2903 line 169492 MATCH x2ea1c800/mask=xbfbffc00 +# CONSTRUCT x2ea1c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_ursqrte/1@4 +# AUNIT --inst x2ea1c800/mask=xfffffc00 --status nopcodeop +# Vector variant when Q=0 T=VPR64.2S + +:ursqrte Rd_VPR64.2S, Rn_VPR64.2S +is b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=0 & b_1021=0b100001110010 & Rd_VPR64.2S & Rn_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_ursqrte(Rn_VPR64.2S, 4:1); +} + +# C7.2.386 URSQRTE page C7-2903 line 169492 MATCH x2ea1c800/mask=xbfbffc00 +# CONSTRUCT x6ea1c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 =NEON_ursqrte/1@4 +# AUNIT --inst x6ea1c800/mask=xfffffc00 --status nopcodeop +# Vector variant when Q=0 T=VPR128.4S + +:ursqrte Rd_VPR128.4S, Rn_VPR128.4S +is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=0 & b_1021=0b100001110010 & Rd_VPR128.4S & Rn_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_ursqrte(Rn_VPR128.4S, 4:1); +} + +# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00 +# CONSTRUCT x6f083400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:1 $>>@1 &=$+@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@1 +# AUNIT --inst x6f083400/mask=xfff8fc00 --status fail --comment "nointround" + +:ursra Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x6 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.16B >> Imm_shr_imm8:1 on lane size 1 + TMPQ1[0,8] = Rn_VPR128.16B[0,8] >> Imm_shr_imm8:1; + TMPQ1[8,8] = Rn_VPR128.16B[8,8] >> Imm_shr_imm8:1; + TMPQ1[16,8] = Rn_VPR128.16B[16,8] >> Imm_shr_imm8:1; + TMPQ1[24,8] = Rn_VPR128.16B[24,8] >> Imm_shr_imm8:1; + TMPQ1[32,8] = Rn_VPR128.16B[32,8] >> Imm_shr_imm8:1; + TMPQ1[40,8] = Rn_VPR128.16B[40,8] >> Imm_shr_imm8:1; + TMPQ1[48,8] = Rn_VPR128.16B[48,8] >> Imm_shr_imm8:1; + TMPQ1[56,8] = Rn_VPR128.16B[56,8] >> Imm_shr_imm8:1; + TMPQ1[64,8] = Rn_VPR128.16B[64,8] >> Imm_shr_imm8:1; + TMPQ1[72,8] = Rn_VPR128.16B[72,8] >> Imm_shr_imm8:1; + TMPQ1[80,8] = Rn_VPR128.16B[80,8] >> Imm_shr_imm8:1; + TMPQ1[88,8] = Rn_VPR128.16B[88,8] >> Imm_shr_imm8:1; + TMPQ1[96,8] = Rn_VPR128.16B[96,8] >> Imm_shr_imm8:1; + TMPQ1[104,8] = Rn_VPR128.16B[104,8] >> Imm_shr_imm8:1; + TMPQ1[112,8] = Rn_VPR128.16B[112,8] >> Imm_shr_imm8:1; + TMPQ1[120,8] = Rn_VPR128.16B[120,8] >> Imm_shr_imm8:1; + # simd infix Rd_VPR128.16B = Rd_VPR128.16B + TMPQ1 on lane size 1 + Rd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] + TMPQ1[0,8]; + Rd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] + TMPQ1[8,8]; + Rd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] + TMPQ1[16,8]; + Rd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] + TMPQ1[24,8]; + Rd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] + TMPQ1[32,8]; + Rd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] + TMPQ1[40,8]; + Rd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] + TMPQ1[48,8]; + Rd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] + TMPQ1[56,8]; + Rd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] + TMPQ1[64,8]; + Rd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] + TMPQ1[72,8]; + Rd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] + TMPQ1[80,8]; + Rd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] + TMPQ1[88,8]; + Rd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] + TMPQ1[96,8]; + Rd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] + TMPQ1[104,8]; + Rd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] + TMPQ1[112,8]; + Rd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] + TMPQ1[120,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00 +# CONSTRUCT x6f403400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 zext:8 $>>@8 &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@8 +# AUNIT --inst x6f403400/mask=xffc0fc00 --status fail --comment "nointround" + +:ursra Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x6 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + local tmp1:8 = zext(Imm_shr_imm64); + # simd infix TMPQ1 = Rn_VPR128.2D >> tmp1 on lane size 8 + TMPQ1[0,64] = Rn_VPR128.2D[0,64] >> tmp1; + TMPQ1[64,64] = Rn_VPR128.2D[64,64] >> tmp1; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ1 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ1[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ1[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00 +# CONSTRUCT x2f203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =var:4 $>>@4 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@4 +# AUNIT --inst x2f203400/mask=xffe0fc00 --status fail --comment "nointround" + +:ursra Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x6 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + local tmp1:4 = Imm_shr_imm32; + # simd infix TMPD1 = Rn_VPR64.2S >> tmp1 on lane size 4 + TMPD1[0,32] = Rn_VPR64.2S[0,32] >> tmp1; + TMPD1[32,32] = Rn_VPR64.2S[32,32] >> tmp1; + # simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4 + Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32]; + Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00 +# CONSTRUCT x2f103400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:2 $>>@2 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@2 +# AUNIT --inst x2f103400/mask=xfff0fc00 --status fail --comment "nointround" + +:ursra Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x6 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + # simd infix TMPD1 = Rn_VPR64.4H >> Imm_shr_imm16:2 on lane size 2 + TMPD1[0,16] = Rn_VPR64.4H[0,16] >> Imm_shr_imm16:2; + TMPD1[16,16] = Rn_VPR64.4H[16,16] >> Imm_shr_imm16:2; + TMPD1[32,16] = Rn_VPR64.4H[32,16] >> Imm_shr_imm16:2; + TMPD1[48,16] = Rn_VPR64.4H[48,16] >> Imm_shr_imm16:2; + # simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 4 + Rd_VPR64.4H[0,32] = Rd_VPR64.4H[0,32] + TMPD1[0,32]; + Rd_VPR64.4H[32,32] = Rd_VPR64.4H[32,32] + TMPD1[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00 +# CONSTRUCT x6f203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =var:4 $>>@4 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@4 +# AUNIT --inst x6f203400/mask=xffe0fc00 --status fail --comment "nointround" + +:ursra Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x6 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + local tmp1:4 = Imm_shr_imm32; + # simd infix TMPQ1 = Rn_VPR128.4S >> tmp1 on lane size 4 + TMPQ1[0,32] = Rn_VPR128.4S[0,32] >> tmp1; + TMPQ1[32,32] = Rn_VPR128.4S[32,32] >> tmp1; + TMPQ1[64,32] = Rn_VPR128.4S[64,32] >> tmp1; + TMPQ1[96,32] = Rn_VPR128.4S[96,32] >> tmp1; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00 +# CONSTRUCT x2f083400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:1 $>>@1 &=$+@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@1 +# AUNIT --inst x2f083400/mask=xfff8fc00 --status fail --comment "nointround" + +:ursra Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x6 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + # simd infix TMPD1 = Rn_VPR64.8B >> Imm_shr_imm8:1 on lane size 1 + TMPD1[0,8] = Rn_VPR64.8B[0,8] >> Imm_shr_imm8:1; + TMPD1[8,8] = Rn_VPR64.8B[8,8] >> Imm_shr_imm8:1; + TMPD1[16,8] = Rn_VPR64.8B[16,8] >> Imm_shr_imm8:1; + TMPD1[24,8] = Rn_VPR64.8B[24,8] >> Imm_shr_imm8:1; + TMPD1[32,8] = Rn_VPR64.8B[32,8] >> Imm_shr_imm8:1; + TMPD1[40,8] = Rn_VPR64.8B[40,8] >> Imm_shr_imm8:1; + TMPD1[48,8] = Rn_VPR64.8B[48,8] >> Imm_shr_imm8:1; + TMPD1[56,8] = Rn_VPR64.8B[56,8] >> Imm_shr_imm8:1; + # simd infix Rd_VPR64.8B = Rd_VPR64.8B + TMPD1 on lane size 1 + Rd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] + TMPD1[0,8]; + Rd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] + TMPD1[8,8]; + Rd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] + TMPD1[16,8]; + Rd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] + TMPD1[24,8]; + Rd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] + TMPD1[32,8]; + Rd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] + TMPD1[40,8]; + Rd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] + TMPD1[48,8]; + Rd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] + TMPD1[56,8]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00 +# CONSTRUCT x6f103400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:2 $>>@2 &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@2 +# AUNIT --inst x6f103400/mask=xfff0fc00 --status fail --comment "nointround" + +:ursra Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x6 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.8H >> Imm_shr_imm16:2 on lane size 2 + TMPQ1[0,16] = Rn_VPR128.8H[0,16] >> Imm_shr_imm16:2; + TMPQ1[16,16] = Rn_VPR128.8H[16,16] >> Imm_shr_imm16:2; + TMPQ1[32,16] = Rn_VPR128.8H[32,16] >> Imm_shr_imm16:2; + TMPQ1[48,16] = Rn_VPR128.8H[48,16] >> Imm_shr_imm16:2; + TMPQ1[64,16] = Rn_VPR128.8H[64,16] >> Imm_shr_imm16:2; + TMPQ1[80,16] = Rn_VPR128.8H[80,16] >> Imm_shr_imm16:2; + TMPQ1[96,16] = Rn_VPR128.8H[96,16] >> Imm_shr_imm16:2; + TMPQ1[112,16] = Rn_VPR128.8H[112,16] >> Imm_shr_imm16:2; + # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.387 URSRA page C7-2904 line 169558 MATCH x7f003400/mask=xff80fc00 +# CONSTRUCT x7f403400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 zext:8 >> &=+ +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3 +# AUNIT --inst x7f403400/mask=xffc0fc00 --status fail --comment "nointround" +# Scalar variant when immh=1xxx + +:ursra Rd_FPR64, Rn_FPR64, Imm_shr_imm64 +is b_2331=0b011111110 & b_22=1 & b_1015=0b001101 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd +{ + local tmp1:8 = zext(Imm_shr_imm64); + local tmp2:8 = Rn_FPR64 >> tmp1; + Rd_FPR64 = Rd_FPR64 + tmp2; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.390 USHL page C7-2911 line 169885 MATCH x7e204400/mask=xff20fc00 +# CONSTRUCT x7ee04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2 +# AUNIT --inst x7ee04400/mask=xffe0fc00 --status nopcodeop + +:ushl Rd_FPR64, Rn_FPR64, Rm_FPR64 +is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x8 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd +{ + Rd_FPR64 = NEON_ushl(Rn_FPR64, Rm_FPR64); +} + +# C7.2.390 USHL page C7-2911 line 169885 MATCH x2e204400/mask=xbf20fc00 +# CONSTRUCT x6e204400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@1 +# AUNIT --inst x6e204400/mask=xffe0fc00 --status nopcodeop + +:ushl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x8 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_ushl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.390 USHL page C7-2911 line 169885 MATCH x2e204400/mask=xbf20fc00 +# CONSTRUCT x6ee04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@8 +# AUNIT --inst x6ee04400/mask=xffe0fc00 --status nopcodeop + +:ushl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x8 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_ushl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1); +} + +# C7.2.390 USHL page C7-2911 line 169885 MATCH x2e204400/mask=xbf20fc00 +# CONSTRUCT x2ea04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@4 +# AUNIT --inst x2ea04400/mask=xffe0fc00 --status nopcodeop + +:ushl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x8 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_ushl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); +} + +# C7.2.390 USHL page C7-2911 line 169885 MATCH x2e204400/mask=xbf20fc00 +# CONSTRUCT x2e604400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@2 +# AUNIT --inst x2e604400/mask=xffe0fc00 --status nopcodeop + +:ushl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x8 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_ushl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1); +} + +# C7.2.390 USHL page C7-2911 line 169885 MATCH x2e204400/mask=xbf20fc00 +# CONSTRUCT x6ea04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@4 +# AUNIT --inst x6ea04400/mask=xffe0fc00 --status nopcodeop + +:ushl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x8 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_ushl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); +} + +# C7.2.390 USHL page C7-2911 line 169885 MATCH x2e204400/mask=xbf20fc00 +# CONSTRUCT x2e204400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@1 +# AUNIT --inst x2e204400/mask=xffe0fc00 --status nopcodeop + +:ushl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x8 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_ushl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1); +} + +# C7.2.390 USHL page C7-2911 line 169885 MATCH x2e204400/mask=xbf20fc00 +# CONSTRUCT x6e604400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@2 +# AUNIT --inst x6e604400/mask=xffe0fc00 --status nopcodeop + +:ushl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x8 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_ushl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1); +} + +# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00 +# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00 +# CONSTRUCT x6f08a400/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3 =var:2 =$<<@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushll2/2@1 +# AUNIT --inst x6f08a400/mask=xfff8fc00 --status pass --comment "ext" + +:ushll2 Rd_VPR128.8H, Rn_VPR128.16B, Imm_uimm3 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0x14 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.8H & Zd +{ + TMPD1 = Rn_VPR128.16B[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2) + TMPQ2[0,16] = zext(TMPD1[0,8]); + TMPQ2[16,16] = zext(TMPD1[8,8]); + TMPQ2[32,16] = zext(TMPD1[16,8]); + TMPQ2[48,16] = zext(TMPD1[24,8]); + TMPQ2[64,16] = zext(TMPD1[32,8]); + TMPQ2[80,16] = zext(TMPD1[40,8]); + TMPQ2[96,16] = zext(TMPD1[48,8]); + TMPQ2[112,16] = zext(TMPD1[56,8]); + local tmp3:2 = Imm_uimm3; + # simd infix Rd_VPR128.8H = TMPQ2 << tmp3 on lane size 2 + Rd_VPR128.8H[0,16] = TMPQ2[0,16] << tmp3; + Rd_VPR128.8H[16,16] = TMPQ2[16,16] << tmp3; + Rd_VPR128.8H[32,16] = TMPQ2[32,16] << tmp3; + Rd_VPR128.8H[48,16] = TMPQ2[48,16] << tmp3; + Rd_VPR128.8H[64,16] = TMPQ2[64,16] << tmp3; + Rd_VPR128.8H[80,16] = TMPQ2[80,16] << tmp3; + Rd_VPR128.8H[96,16] = TMPQ2[96,16] << tmp3; + Rd_VPR128.8H[112,16] = TMPQ2[112,16] << tmp3; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00 +# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00 +# CONSTRUCT x2f20a400/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@4:16 ARG3 =var:8 =$<<@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushll/2@4 +# AUNIT --inst x2f20a400/mask=xffe0fc00 --status pass --comment "ext" + +:ushll Rd_VPR128.2D, Rn_VPR64.2S, Imm_uimm5 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0x14 & b_1010=1 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]); + local tmp2:8 = Imm_uimm5; + # simd infix Rd_VPR128.2D = TMPQ1 << tmp2 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ1[0,64] << tmp2; + Rd_VPR128.2D[64,64] = TMPQ1[64,64] << tmp2; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00 +# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00 +# CONSTRUCT x2f10a400/mask=xfff0fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@2:16 ARG3 =var:4 =$<<@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushll/2@2 +# AUNIT --inst x2f10a400/mask=xfff0fc00 --status pass --comment "ext" + +:ushll Rd_VPR128.4S, Rn_VPR64.4H, Imm_uimm4 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0x14 & b_1010=1 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]); + local tmp2:4 = Imm_uimm4; + # simd infix Rd_VPR128.4S = TMPQ1 << tmp2 on lane size 4 + Rd_VPR128.4S[0,32] = TMPQ1[0,32] << tmp2; + Rd_VPR128.4S[32,32] = TMPQ1[32,32] << tmp2; + Rd_VPR128.4S[64,32] = TMPQ1[64,32] << tmp2; + Rd_VPR128.4S[96,32] = TMPQ1[96,32] << tmp2; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00 +# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00 +# CONSTRUCT x6f20a400/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3 =var:8 =$<<@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushll2/2@4 +# AUNIT --inst x6f20a400/mask=xffe0fc00 --status pass --comment "ext" + +:ushll2 Rd_VPR128.2D, Rn_VPR128.4S, Imm_uimm5 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0x14 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = zext(TMPD1[0,32]); + TMPQ2[64,64] = zext(TMPD1[32,32]); + local tmp3:8 = Imm_uimm5; + # simd infix Rd_VPR128.2D = TMPQ2 << tmp3 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ2[0,64] << tmp3; + Rd_VPR128.2D[64,64] = TMPQ2[64,64] << tmp3; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00 +# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00 +# CONSTRUCT x2f08a400/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@1:16 ARG3 =var:2 =$<<@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushll/2@1 +# AUNIT --inst x2f08a400/mask=xfff8fc00 --status pass --comment "ext" + +:ushll Rd_VPR128.8H, Rn_VPR64.8B, Imm_uimm3 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0x14 & b_1010=1 & Rn_VPR64.8B & Rd_VPR128.8H & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2) + TMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]); + TMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]); + TMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]); + TMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]); + TMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]); + TMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]); + TMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]); + TMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]); + local tmp2:2 = Imm_uimm3; + # simd infix Rd_VPR128.8H = TMPQ1 << tmp2 on lane size 2 + Rd_VPR128.8H[0,16] = TMPQ1[0,16] << tmp2; + Rd_VPR128.8H[16,16] = TMPQ1[16,16] << tmp2; + Rd_VPR128.8H[32,16] = TMPQ1[32,16] << tmp2; + Rd_VPR128.8H[48,16] = TMPQ1[48,16] << tmp2; + Rd_VPR128.8H[64,16] = TMPQ1[64,16] << tmp2; + Rd_VPR128.8H[80,16] = TMPQ1[80,16] << tmp2; + Rd_VPR128.8H[96,16] = TMPQ1[96,16] << tmp2; + Rd_VPR128.8H[112,16] = TMPQ1[112,16] << tmp2; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00 +# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00 +# CONSTRUCT x6f10a400/mask=xfff0fc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3 =var:4 =$<<@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushll2/2@2 +# AUNIT --inst x6f10a400/mask=xfff0fc00 --status pass --comment "ext" + +:ushll2 Rd_VPR128.4S, Rn_VPR128.8H, Imm_uimm4 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0x14 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = zext(TMPD1[0,16]); + TMPQ2[32,32] = zext(TMPD1[16,16]); + TMPQ2[64,32] = zext(TMPD1[32,16]); + TMPQ2[96,32] = zext(TMPD1[48,16]); + local tmp3:4 = Imm_uimm4; + # simd infix Rd_VPR128.4S = TMPQ2 << tmp3 on lane size 4 + Rd_VPR128.4S[0,32] = TMPQ2[0,32] << tmp3; + Rd_VPR128.4S[32,32] = TMPQ2[32,32] << tmp3; + Rd_VPR128.4S[64,32] = TMPQ2[64,32] << tmp3; + Rd_VPR128.4S[96,32] = TMPQ2[96,32] << tmp3; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00 +# CONSTRUCT x6f080400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:1 =$>>@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@1 +# AUNIT --inst x6f080400/mask=xfff8fc00 --status pass + +:ushr Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x0 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + # simd infix Rd_VPR128.16B = Rn_VPR128.16B >> Imm_shr_imm8:1 on lane size 1 + Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] >> Imm_shr_imm8:1; + Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] >> Imm_shr_imm8:1; + Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] >> Imm_shr_imm8:1; + Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] >> Imm_shr_imm8:1; + Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] >> Imm_shr_imm8:1; + Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] >> Imm_shr_imm8:1; + Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] >> Imm_shr_imm8:1; + Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] >> Imm_shr_imm8:1; + Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] >> Imm_shr_imm8:1; + Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] >> Imm_shr_imm8:1; + Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] >> Imm_shr_imm8:1; + Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] >> Imm_shr_imm8:1; + Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] >> Imm_shr_imm8:1; + Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] >> Imm_shr_imm8:1; + Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] >> Imm_shr_imm8:1; + Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] >> Imm_shr_imm8:1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00 +# CONSTRUCT x6f400400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 zext:8 =$>>@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@8 +# AUNIT --inst x6f400400/mask=xffc0fc00 --status pass + +:ushr Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x0 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + local tmp1:8 = zext(Imm_shr_imm64); + # simd infix Rd_VPR128.2D = Rn_VPR128.2D >> tmp1 on lane size 8 + Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] >> tmp1; + Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] >> tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00 +# CONSTRUCT x2f200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =var:4 =$>>@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@4 +# AUNIT --inst x2f200400/mask=xffe0fc00 --status pass + +:ushr Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x0 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + local tmp1:4 = Imm_shr_imm32; + # simd infix Rd_VPR64.2S = Rn_VPR64.2S >> tmp1 on lane size 4 + Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] >> tmp1; + Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] >> tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00 +# CONSTRUCT x2f100400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:2 =$>>@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@2 +# AUNIT --inst x2f100400/mask=xfff0fc00 --status pass + +:ushr Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x0 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + # simd infix Rd_VPR64.4H = Rn_VPR64.4H >> Imm_shr_imm16:2 on lane size 2 + Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] >> Imm_shr_imm16:2; + Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] >> Imm_shr_imm16:2; + Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] >> Imm_shr_imm16:2; + Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] >> Imm_shr_imm16:2; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00 +# CONSTRUCT x6f200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =var:4 =$>>@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@4 +# AUNIT --inst x6f200400/mask=xffe0fc00 --status pass + +:ushr Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x0 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + local tmp1:4 = Imm_shr_imm32; + # simd infix Rd_VPR128.4S = Rn_VPR128.4S >> tmp1 on lane size 4 + Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] >> tmp1; + Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] >> tmp1; + Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] >> tmp1; + Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] >> tmp1; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00 +# CONSTRUCT x2f080400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:1 =$>>@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@1 +# AUNIT --inst x2f080400/mask=xfff8fc00 --status pass + +:ushr Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x0 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + # simd infix Rd_VPR64.8B = Rn_VPR64.8B >> Imm_shr_imm8:1 on lane size 1 + Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] >> Imm_shr_imm8:1; + Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] >> Imm_shr_imm8:1; + Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] >> Imm_shr_imm8:1; + Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] >> Imm_shr_imm8:1; + Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] >> Imm_shr_imm8:1; + Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] >> Imm_shr_imm8:1; + Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] >> Imm_shr_imm8:1; + Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] >> Imm_shr_imm8:1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00 +# CONSTRUCT x6f100400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:2 =$>>@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@2 +# AUNIT --inst x6f100400/mask=xfff0fc00 --status pass + +:ushr Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x0 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + # simd infix Rd_VPR128.8H = Rn_VPR128.8H >> Imm_shr_imm16:2 on lane size 2 + Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] >> Imm_shr_imm16:2; + Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] >> Imm_shr_imm16:2; + Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] >> Imm_shr_imm16:2; + Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] >> Imm_shr_imm16:2; + Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] >> Imm_shr_imm16:2; + Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] >> Imm_shr_imm16:2; + Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] >> Imm_shr_imm16:2; + Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] >> Imm_shr_imm16:2; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.392 USHR page C7-2916 line 170174 MATCH x7f000400/mask=xff80fc00 +# CONSTRUCT x7f400400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 zext:8 =>> +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2 +# AUNIT --inst x7f400400/mask=xffc0fc00 --status pass +# Scalar variant when immh=1xxx + +:ushr Rd_FPR64, Rn_FPR64, Imm_shr_imm64 +is b_2331=0b011111110 & b_22=1 & b_1015=0b000001 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd +{ + local tmp1:8 = zext(Imm_shr_imm64); + Rd_FPR64 = Rn_FPR64 >> tmp1; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.394 USQADD page C7-2920 line 170396 MATCH x7e203800/mask=xff3ffc00 +# CONSTRUCT x7e203800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2 +# AUNIT --inst x7e203800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Scalar variant when size=00 Q=1 bb=1 T=FPR8 + +:usqadd Rd_FPR8, Rn_FPR8 +is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b00 & b_1021=0b100000001110 & Rd_FPR8 & Rn_FPR8 & Zd +{ + Rd_FPR8 = NEON_usqadd(Rd_FPR8, Rn_FPR8); +} + +# C7.2.394 USQADD page C7-2920 line 170396 MATCH x7e203800/mask=xff3ffc00 +# CONSTRUCT x7e603800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2 +# AUNIT --inst x7e603800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Scalar variant when size=01 Q=1 bb=1 T=FPR16 + +:usqadd Rd_FPR16, Rn_FPR16 +is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b01 & b_1021=0b100000001110 & Rd_FPR16 & Rn_FPR16 & Zd +{ + Rd_FPR16 = NEON_usqadd(Rd_FPR16, Rn_FPR16); +} + +# C7.2.394 USQADD page C7-2920 line 170396 MATCH x7e203800/mask=xff3ffc00 +# CONSTRUCT x7ea03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2 +# AUNIT --inst x7ea03800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Scalar variant when size=10 Q=1 bb=1 T=FPR32 + +:usqadd Rd_FPR32, Rn_FPR32 +is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b10 & b_1021=0b100000001110 & Rd_FPR32 & Rn_FPR32 & Zd +{ + Rd_FPR32 = NEON_usqadd(Rd_FPR32, Rn_FPR32); +} + +# C7.2.394 USQADD page C7-2920 line 170396 MATCH x7e203800/mask=xff3ffc00 +# CONSTRUCT x7ee03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2 +# AUNIT --inst x7ee03800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Scalar variant when size=11 Q=1 bb=1 T=FPR64 + +:usqadd Rd_FPR64, Rn_FPR64 +is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b11 & b_1021=0b100000001110 & Rd_FPR64 & Rn_FPR64 & Zd +{ + Rd_FPR64 = NEON_usqadd(Rd_FPR64, Rn_FPR64); +} + +# C7.2.394 USQADD page C7-2920 line 170396 MATCH x2e203800/mask=xbf3ffc00 +# CONSTRUCT x2e203800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@1 +# AUNIT --inst x2e203800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Vector variant when size=00 Q=0 bb=0 e=1 T=VPR64.8B + +:usqadd Rd_VPR64.8B, Rn_VPR64.8B +is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000001110 & Rd_VPR64.8B & Rn_VPR64.8B & Zd +{ + Rd_VPR64.8B = NEON_usqadd(Rd_VPR64.8B, Rn_VPR64.8B, 1:1); +} + +# C7.2.394 USQADD page C7-2920 line 170396 MATCH x2e203800/mask=xbf3ffc00 +# CONSTRUCT x6e203800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@1 +# AUNIT --inst x6e203800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Vector variant when size=00 Q=1 bb=0 e=1 T=VPR128.16B + +:usqadd Rd_VPR128.16B, Rn_VPR128.16B +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000001110 & Rd_VPR128.16B & Rn_VPR128.16B & Zd +{ + Rd_VPR128.16B = NEON_usqadd(Rd_VPR128.16B, Rn_VPR128.16B, 1:1); +} + +# C7.2.394 USQADD page C7-2920 line 170396 MATCH x2e203800/mask=xbf3ffc00 +# CONSTRUCT x2e603800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@2 +# AUNIT --inst x2e603800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Vector variant when size=01 Q=0 bb=0 e=2 T=VPR64.4H + +:usqadd Rd_VPR64.4H, Rn_VPR64.4H +is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000001110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd +{ + Rd_VPR64.4H = NEON_usqadd(Rd_VPR64.4H, Rn_VPR64.4H, 2:1); +} + +# C7.2.394 USQADD page C7-2920 line 170396 MATCH x2e203800/mask=xbf3ffc00 +# CONSTRUCT x6e603800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@2 +# AUNIT --inst x6e603800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Vector variant when size=01 Q=1 bb=0 e=2 T=VPR128.8H + +:usqadd Rd_VPR128.8H, Rn_VPR128.8H +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000001110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd +{ + Rd_VPR128.8H = NEON_usqadd(Rd_VPR128.8H, Rn_VPR128.8H, 2:1); +} + +# C7.2.394 USQADD page C7-2920 line 170396 MATCH x2e203800/mask=xbf3ffc00 +# CONSTRUCT x2ea03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@4 +# AUNIT --inst x2ea03800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Vector variant when size=10 Q=0 bb=0 e=4 T=VPR64.2S + +:usqadd Rd_VPR64.2S, Rn_VPR64.2S +is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000001110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd +{ + Rd_VPR64.2S = NEON_usqadd(Rd_VPR64.2S, Rn_VPR64.2S, 4:1); +} + +# C7.2.394 USQADD page C7-2920 line 170396 MATCH x2e203800/mask=xbf3ffc00 +# CONSTRUCT x6ea03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@4 +# AUNIT --inst x6ea03800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Vector variant when size=10 Q=1 bb=0 e=4 T=VPR128.4S + +:usqadd Rd_VPR128.4S, Rn_VPR128.4S +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000001110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd +{ + Rd_VPR128.4S = NEON_usqadd(Rd_VPR128.4S, Rn_VPR128.4S, 4:1); +} + +# C7.2.394 USQADD page C7-2920 line 170396 MATCH x2e203800/mask=xbf3ffc00 +# CONSTRUCT x6ee03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@8 +# AUNIT --inst x6ee03800/mask=xfffffc00 --status nopcodeop --comment "nointsat" +# Vector variant when size=11 Q=1 bb=0 e=8 T=VPR128.2D + +:usqadd Rd_VPR128.2D, Rn_VPR128.2D +is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b11 & b_1021=0b100000001110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd +{ + Rd_VPR128.2D = NEON_usqadd(Rd_VPR128.2D, Rn_VPR128.2D, 8:1); +} + +# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00 +# CONSTRUCT x6f081400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:1 $>>@1 &=$+@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@1 +# AUNIT --inst x6f081400/mask=xfff8fc00 --status pass + +:usra Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x2 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.16B >> Imm_shr_imm8:1 on lane size 1 + TMPQ1[0,8] = Rn_VPR128.16B[0,8] >> Imm_shr_imm8:1; + TMPQ1[8,8] = Rn_VPR128.16B[8,8] >> Imm_shr_imm8:1; + TMPQ1[16,8] = Rn_VPR128.16B[16,8] >> Imm_shr_imm8:1; + TMPQ1[24,8] = Rn_VPR128.16B[24,8] >> Imm_shr_imm8:1; + TMPQ1[32,8] = Rn_VPR128.16B[32,8] >> Imm_shr_imm8:1; + TMPQ1[40,8] = Rn_VPR128.16B[40,8] >> Imm_shr_imm8:1; + TMPQ1[48,8] = Rn_VPR128.16B[48,8] >> Imm_shr_imm8:1; + TMPQ1[56,8] = Rn_VPR128.16B[56,8] >> Imm_shr_imm8:1; + TMPQ1[64,8] = Rn_VPR128.16B[64,8] >> Imm_shr_imm8:1; + TMPQ1[72,8] = Rn_VPR128.16B[72,8] >> Imm_shr_imm8:1; + TMPQ1[80,8] = Rn_VPR128.16B[80,8] >> Imm_shr_imm8:1; + TMPQ1[88,8] = Rn_VPR128.16B[88,8] >> Imm_shr_imm8:1; + TMPQ1[96,8] = Rn_VPR128.16B[96,8] >> Imm_shr_imm8:1; + TMPQ1[104,8] = Rn_VPR128.16B[104,8] >> Imm_shr_imm8:1; + TMPQ1[112,8] = Rn_VPR128.16B[112,8] >> Imm_shr_imm8:1; + TMPQ1[120,8] = Rn_VPR128.16B[120,8] >> Imm_shr_imm8:1; + # simd infix Rd_VPR128.16B = Rd_VPR128.16B + TMPQ1 on lane size 1 + Rd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] + TMPQ1[0,8]; + Rd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] + TMPQ1[8,8]; + Rd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] + TMPQ1[16,8]; + Rd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] + TMPQ1[24,8]; + Rd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] + TMPQ1[32,8]; + Rd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] + TMPQ1[40,8]; + Rd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] + TMPQ1[48,8]; + Rd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] + TMPQ1[56,8]; + Rd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] + TMPQ1[64,8]; + Rd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] + TMPQ1[72,8]; + Rd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] + TMPQ1[80,8]; + Rd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] + TMPQ1[88,8]; + Rd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] + TMPQ1[96,8]; + Rd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] + TMPQ1[104,8]; + Rd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] + TMPQ1[112,8]; + Rd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] + TMPQ1[120,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00 +# CONSTRUCT x6f401400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 zext:8 $>>@8 &=$+@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@8 +# AUNIT --inst x6f401400/mask=xffc0fc00 --status pass + +:usra Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x2 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + local tmp1:8 = zext(Imm_shr_imm64); + # simd infix TMPQ1 = Rn_VPR128.2D >> tmp1 on lane size 8 + TMPQ1[0,64] = Rn_VPR128.2D[0,64] >> tmp1; + TMPQ1[64,64] = Rn_VPR128.2D[64,64] >> tmp1; + # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ1 on lane size 8 + Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ1[0,64]; + Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ1[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00 +# CONSTRUCT x2f201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =var:4 $>>@4 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@4 +# AUNIT --inst x2f201400/mask=xffe0fc00 --status pass + +:usra Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x2 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + local tmp1:4 = Imm_shr_imm32; + # simd infix TMPD1 = Rn_VPR64.2S >> tmp1 on lane size 4 + TMPD1[0,32] = Rn_VPR64.2S[0,32] >> tmp1; + TMPD1[32,32] = Rn_VPR64.2S[32,32] >> tmp1; + # simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4 + Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32]; + Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00 +# CONSTRUCT x2f101400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:2 $>>@2 &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@2 +# AUNIT --inst x2f101400/mask=xfff0fc00 --status pass + +:usra Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x2 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + # simd infix TMPD1 = Rn_VPR64.4H >> Imm_shr_imm16:2 on lane size 2 + TMPD1[0,16] = Rn_VPR64.4H[0,16] >> Imm_shr_imm16:2; + TMPD1[16,16] = Rn_VPR64.4H[16,16] >> Imm_shr_imm16:2; + TMPD1[32,16] = Rn_VPR64.4H[32,16] >> Imm_shr_imm16:2; + TMPD1[48,16] = Rn_VPR64.4H[48,16] >> Imm_shr_imm16:2; + # simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2 + Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16]; + Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16]; + Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16]; + Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00 +# CONSTRUCT x6f201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 =var:4 $>>@4 &=$+@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@4 +# AUNIT --inst x6f201400/mask=xffe0fc00 --status pass + +:usra Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x2 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + local tmp1:4 = Imm_shr_imm32; + # simd infix TMPQ1 = Rn_VPR128.4S >> tmp1 on lane size 4 + TMPQ1[0,32] = Rn_VPR128.4S[0,32] >> tmp1; + TMPQ1[32,32] = Rn_VPR128.4S[32,32] >> tmp1; + TMPQ1[64,32] = Rn_VPR128.4S[64,32] >> tmp1; + TMPQ1[96,32] = Rn_VPR128.4S[96,32] >> tmp1; + # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4 + Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32]; + Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32]; + Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32]; + Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00 +# CONSTRUCT x2f081400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:1 $>>@1 &=$+@1 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@1 +# AUNIT --inst x2f081400/mask=xfff8fc00 --status pass + +:usra Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8 +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x2 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + # simd infix TMPD1 = Rn_VPR64.8B >> Imm_shr_imm8:1 on lane size 1 + TMPD1[0,8] = Rn_VPR64.8B[0,8] >> Imm_shr_imm8:1; + TMPD1[8,8] = Rn_VPR64.8B[8,8] >> Imm_shr_imm8:1; + TMPD1[16,8] = Rn_VPR64.8B[16,8] >> Imm_shr_imm8:1; + TMPD1[24,8] = Rn_VPR64.8B[24,8] >> Imm_shr_imm8:1; + TMPD1[32,8] = Rn_VPR64.8B[32,8] >> Imm_shr_imm8:1; + TMPD1[40,8] = Rn_VPR64.8B[40,8] >> Imm_shr_imm8:1; + TMPD1[48,8] = Rn_VPR64.8B[48,8] >> Imm_shr_imm8:1; + TMPD1[56,8] = Rn_VPR64.8B[56,8] >> Imm_shr_imm8:1; + # simd infix Rd_VPR64.8B = Rd_VPR64.8B + TMPD1 on lane size 1 + Rd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] + TMPD1[0,8]; + Rd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] + TMPD1[8,8]; + Rd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] + TMPD1[16,8]; + Rd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] + TMPD1[24,8]; + Rd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] + TMPD1[32,8]; + Rd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] + TMPD1[40,8]; + Rd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] + TMPD1[48,8]; + Rd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] + TMPD1[56,8]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00 +# CONSTRUCT x6f101400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3:2 $>>@2 &=$+@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@2 +# AUNIT --inst x6f101400/mask=xfff0fc00 --status pass + +:usra Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16 +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x2 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.8H >> Imm_shr_imm16:2 on lane size 2 + TMPQ1[0,16] = Rn_VPR128.8H[0,16] >> Imm_shr_imm16:2; + TMPQ1[16,16] = Rn_VPR128.8H[16,16] >> Imm_shr_imm16:2; + TMPQ1[32,16] = Rn_VPR128.8H[32,16] >> Imm_shr_imm16:2; + TMPQ1[48,16] = Rn_VPR128.8H[48,16] >> Imm_shr_imm16:2; + TMPQ1[64,16] = Rn_VPR128.8H[64,16] >> Imm_shr_imm16:2; + TMPQ1[80,16] = Rn_VPR128.8H[80,16] >> Imm_shr_imm16:2; + TMPQ1[96,16] = Rn_VPR128.8H[96,16] >> Imm_shr_imm16:2; + TMPQ1[112,16] = Rn_VPR128.8H[112,16] >> Imm_shr_imm16:2; + # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2 + Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16]; + Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16]; + Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16]; + Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16]; + Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16]; + Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16]; + Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16]; + Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.395 USRA page C7-2922 line 170519 MATCH x7f001400/mask=xff80fc00 +# CONSTRUCT x7f401400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 zext:8 >> &=+ +# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3 +# AUNIT --inst x7f401400/mask=xffc0fc00 --status pass +# Scalar variant when immh=1xxx + +:usra Rd_FPR64, Rn_FPR64, Imm_shr_imm64 +is b_2331=0b011111110 & b_22=1 & b_1015=0b000101 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd +{ + local tmp1:8 = zext(Imm_shr_imm64); + local tmp2:8 = Rn_FPR64 >> tmp1; + Rd_FPR64 = Rd_FPR64 + tmp2; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.396 USUBL, USUBL2 page C7-2925 line 170683 MATCH x2e202000/mask=xbf20fc00 +# CONSTRUCT x6ea02000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 =$-@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubl2/2@4 +# AUNIT --inst x6ea02000/mask=xffe0fc00 --status pass --comment "ext" + +:usubl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x2 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = zext(TMPD1[0,32]); + TMPQ2[64,64] = zext(TMPD1[32,32]); + TMPD3 = Rm_VPR128.4S[64,64]; + # simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8) + TMPQ4[0,64] = zext(TMPD3[0,32]); + TMPQ4[64,64] = zext(TMPD3[32,32]); + # simd infix Rd_VPR128.2D = TMPQ2 - TMPQ4 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ2[0,64] - TMPQ4[0,64]; + Rd_VPR128.2D[64,64] = TMPQ2[64,64] - TMPQ4[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.396 USUBL, USUBL2 page C7-2925 line 170683 MATCH x2e202000/mask=xbf20fc00 +# CONSTRUCT x6e602000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 =$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubl2/2@2 +# AUNIT --inst x6e602000/mask=xffe0fc00 --status pass --comment "ext" + +:usubl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x2 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = zext(TMPD1[0,16]); + TMPQ2[32,32] = zext(TMPD1[16,16]); + TMPQ2[64,32] = zext(TMPD1[32,16]); + TMPQ2[96,32] = zext(TMPD1[48,16]); + TMPD3 = Rm_VPR128.8H[64,64]; + # simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4) + TMPQ4[0,32] = zext(TMPD3[0,16]); + TMPQ4[32,32] = zext(TMPD3[16,16]); + TMPQ4[64,32] = zext(TMPD3[32,16]); + TMPQ4[96,32] = zext(TMPD3[48,16]); + # simd infix Rd_VPR128.4S = TMPQ2 - TMPQ4 on lane size 4 + Rd_VPR128.4S[0,32] = TMPQ2[0,32] - TMPQ4[0,32]; + Rd_VPR128.4S[32,32] = TMPQ2[32,32] - TMPQ4[32,32]; + Rd_VPR128.4S[64,32] = TMPQ2[64,32] - TMPQ4[64,32]; + Rd_VPR128.4S[96,32] = TMPQ2[96,32] - TMPQ4[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.396 USUBL, USUBL2 page C7-2925 line 170683 MATCH x2e202000/mask=xbf20fc00 +# CONSTRUCT x6e202000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 =$-@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubl2/2@1 +# AUNIT --inst x6e202000/mask=xffe0fc00 --status pass --comment "ext" + +:usubl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x2 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd +{ + TMPD1 = Rn_VPR128.16B[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2) + TMPQ2[0,16] = zext(TMPD1[0,8]); + TMPQ2[16,16] = zext(TMPD1[8,8]); + TMPQ2[32,16] = zext(TMPD1[16,8]); + TMPQ2[48,16] = zext(TMPD1[24,8]); + TMPQ2[64,16] = zext(TMPD1[32,8]); + TMPQ2[80,16] = zext(TMPD1[40,8]); + TMPQ2[96,16] = zext(TMPD1[48,8]); + TMPQ2[112,16] = zext(TMPD1[56,8]); + TMPD3 = Rm_VPR128.16B[64,64]; + # simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2) + TMPQ4[0,16] = zext(TMPD3[0,8]); + TMPQ4[16,16] = zext(TMPD3[8,8]); + TMPQ4[32,16] = zext(TMPD3[16,8]); + TMPQ4[48,16] = zext(TMPD3[24,8]); + TMPQ4[64,16] = zext(TMPD3[32,8]); + TMPQ4[80,16] = zext(TMPD3[40,8]); + TMPQ4[96,16] = zext(TMPD3[48,8]); + TMPQ4[112,16] = zext(TMPD3[56,8]); + # simd infix Rd_VPR128.8H = TMPQ2 - TMPQ4 on lane size 2 + Rd_VPR128.8H[0,16] = TMPQ2[0,16] - TMPQ4[0,16]; + Rd_VPR128.8H[16,16] = TMPQ2[16,16] - TMPQ4[16,16]; + Rd_VPR128.8H[32,16] = TMPQ2[32,16] - TMPQ4[32,16]; + Rd_VPR128.8H[48,16] = TMPQ2[48,16] - TMPQ4[48,16]; + Rd_VPR128.8H[64,16] = TMPQ2[64,16] - TMPQ4[64,16]; + Rd_VPR128.8H[80,16] = TMPQ2[80,16] - TMPQ4[80,16]; + Rd_VPR128.8H[96,16] = TMPQ2[96,16] - TMPQ4[96,16]; + Rd_VPR128.8H[112,16] = TMPQ2[112,16] - TMPQ4[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.396 USUBL, USUBL2 page C7-2925 line 170683 MATCH x2e202000/mask=xbf20fc00 +# CONSTRUCT x2ea02000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@4:16 ARG3 $zext@4:16 =$-@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubl/2@4 +# AUNIT --inst x2ea02000/mask=xffe0fc00 --status pass --comment "ext" + +:usubl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x2 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]); + TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]); + # simd resize TMPQ2 = zext(Rm_VPR64.2S) (lane size 4 to 8) + TMPQ2[0,64] = zext(Rm_VPR64.2S[0,32]); + TMPQ2[64,64] = zext(Rm_VPR64.2S[32,32]); + # simd infix Rd_VPR128.2D = TMPQ1 - TMPQ2 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ1[0,64] - TMPQ2[0,64]; + Rd_VPR128.2D[64,64] = TMPQ1[64,64] - TMPQ2[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.396 USUBL, USUBL2 page C7-2925 line 170683 MATCH x2e202000/mask=xbf20fc00 +# CONSTRUCT x2e602000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@2:16 ARG3 $zext@2:16 =$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubl/2@2 +# AUNIT --inst x2e602000/mask=xffe0fc00 --status pass --comment "ext" + +:usubl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x2 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]); + TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]); + TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]); + TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]); + # simd resize TMPQ2 = zext(Rm_VPR64.4H) (lane size 2 to 4) + TMPQ2[0,32] = zext(Rm_VPR64.4H[0,16]); + TMPQ2[32,32] = zext(Rm_VPR64.4H[16,16]); + TMPQ2[64,32] = zext(Rm_VPR64.4H[32,16]); + TMPQ2[96,32] = zext(Rm_VPR64.4H[48,16]); + # simd infix Rd_VPR128.4S = TMPQ1 - TMPQ2 on lane size 4 + Rd_VPR128.4S[0,32] = TMPQ1[0,32] - TMPQ2[0,32]; + Rd_VPR128.4S[32,32] = TMPQ1[32,32] - TMPQ2[32,32]; + Rd_VPR128.4S[64,32] = TMPQ1[64,32] - TMPQ2[64,32]; + Rd_VPR128.4S[96,32] = TMPQ1[96,32] - TMPQ2[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.396 USUBL, USUBL2 page C7-2925 line 170683 MATCH x2e202000/mask=xbf20fc00 +# CONSTRUCT x2e202000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@1:16 ARG3 $zext@1:16 =$-@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubl/2@1 +# AUNIT --inst x2e202000/mask=xffe0fc00 --status pass --comment "ext" + +:usubl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x2 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd +{ + # simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2) + TMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]); + TMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]); + TMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]); + TMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]); + TMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]); + TMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]); + TMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]); + TMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]); + # simd resize TMPQ2 = zext(Rm_VPR64.8B) (lane size 1 to 2) + TMPQ2[0,16] = zext(Rm_VPR64.8B[0,8]); + TMPQ2[16,16] = zext(Rm_VPR64.8B[8,8]); + TMPQ2[32,16] = zext(Rm_VPR64.8B[16,8]); + TMPQ2[48,16] = zext(Rm_VPR64.8B[24,8]); + TMPQ2[64,16] = zext(Rm_VPR64.8B[32,8]); + TMPQ2[80,16] = zext(Rm_VPR64.8B[40,8]); + TMPQ2[96,16] = zext(Rm_VPR64.8B[48,8]); + TMPQ2[112,16] = zext(Rm_VPR64.8B[56,8]); + # simd infix Rd_VPR128.8H = TMPQ1 - TMPQ2 on lane size 2 + Rd_VPR128.8H[0,16] = TMPQ1[0,16] - TMPQ2[0,16]; + Rd_VPR128.8H[16,16] = TMPQ1[16,16] - TMPQ2[16,16]; + Rd_VPR128.8H[32,16] = TMPQ1[32,16] - TMPQ2[32,16]; + Rd_VPR128.8H[48,16] = TMPQ1[48,16] - TMPQ2[48,16]; + Rd_VPR128.8H[64,16] = TMPQ1[64,16] - TMPQ2[64,16]; + Rd_VPR128.8H[80,16] = TMPQ1[80,16] - TMPQ2[80,16]; + Rd_VPR128.8H[96,16] = TMPQ1[96,16] - TMPQ2[96,16]; + Rd_VPR128.8H[112,16] = TMPQ1[112,16] - TMPQ2[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.397 USUBW, USUBW2 page C7-2927 line 170806 MATCH x2e203000/mask=xbf20fc00 +# CONSTRUCT x6ea03000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3[1]:8 $zext@4:16 =$-@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubw2/2@4 +# AUNIT --inst x6ea03000/mask=xffe0fc00 --status pass --comment "ext" + +:usubw2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x3 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + TMPD1 = Rm_VPR128.4S[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8) + TMPQ2[0,64] = zext(TMPD1[0,32]); + TMPQ2[64,64] = zext(TMPD1[32,32]); + # simd infix Rd_VPR128.2D = Rn_VPR128.2D - TMPQ2 on lane size 8 + Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] - TMPQ2[0,64]; + Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] - TMPQ2[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.397 USUBW, USUBW2 page C7-2927 line 170806 MATCH x2e203000/mask=xbf20fc00 +# CONSTRUCT x6e603000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3[1]:8 $zext@2:16 =$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubw2/2@2 +# AUNIT --inst x6e603000/mask=xffe0fc00 --status pass --comment "ext" + +:usubw2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x3 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + TMPD1 = Rm_VPR128.8H[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4) + TMPQ2[0,32] = zext(TMPD1[0,16]); + TMPQ2[32,32] = zext(TMPD1[16,16]); + TMPQ2[64,32] = zext(TMPD1[32,16]); + TMPQ2[96,32] = zext(TMPD1[48,16]); + # simd infix Rd_VPR128.4S = Rn_VPR128.4S - TMPQ2 on lane size 4 + Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] - TMPQ2[0,32]; + Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] - TMPQ2[32,32]; + Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] - TMPQ2[64,32]; + Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] - TMPQ2[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.397 USUBW, USUBW2 page C7-2927 line 170806 MATCH x2e203000/mask=xbf20fc00 +# CONSTRUCT x6e203000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3[1]:8 $zext@1:16 =$-@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubw2/2@1 +# AUNIT --inst x6e203000/mask=xffe0fc00 --status pass --comment "ext" + +:usubw2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x3 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + TMPD1 = Rm_VPR128.16B[64,64]; + # simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2) + TMPQ2[0,16] = zext(TMPD1[0,8]); + TMPQ2[16,16] = zext(TMPD1[8,8]); + TMPQ2[32,16] = zext(TMPD1[16,8]); + TMPQ2[48,16] = zext(TMPD1[24,8]); + TMPQ2[64,16] = zext(TMPD1[32,8]); + TMPQ2[80,16] = zext(TMPD1[40,8]); + TMPQ2[96,16] = zext(TMPD1[48,8]); + TMPQ2[112,16] = zext(TMPD1[56,8]); + # simd infix Rd_VPR128.8H = Rn_VPR128.8H - TMPQ2 on lane size 2 + Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] - TMPQ2[0,16]; + Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] - TMPQ2[16,16]; + Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] - TMPQ2[32,16]; + Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] - TMPQ2[48,16]; + Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] - TMPQ2[64,16]; + Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] - TMPQ2[80,16]; + Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] - TMPQ2[96,16]; + Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] - TMPQ2[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.397 USUBW, USUBW2 page C7-2927 line 170806 MATCH x2e203000/mask=xbf20fc00 +# CONSTRUCT x2ea03000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $zext@4:16 =$-@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubw/2@4 +# AUNIT --inst x2ea03000/mask=xffe0fc00 --status pass --comment "ext" + +:usubw Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x3 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + # simd resize TMPQ1 = zext(Rm_VPR64.2S) (lane size 4 to 8) + TMPQ1[0,64] = zext(Rm_VPR64.2S[0,32]); + TMPQ1[64,64] = zext(Rm_VPR64.2S[32,32]); + # simd infix Rd_VPR128.2D = Rn_VPR128.2D - TMPQ1 on lane size 8 + Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] - TMPQ1[0,64]; + Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] - TMPQ1[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.397 USUBW, USUBW2 page C7-2927 line 170806 MATCH x2e203000/mask=xbf20fc00 +# CONSTRUCT x2e603000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $zext@2:16 =$-@4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubw/2@2 +# AUNIT --inst x2e603000/mask=xffe0fc00 --status pass --comment "ext" + +:usubw Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x3 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + # simd resize TMPQ1 = zext(Rm_VPR64.4H) (lane size 2 to 4) + TMPQ1[0,32] = zext(Rm_VPR64.4H[0,16]); + TMPQ1[32,32] = zext(Rm_VPR64.4H[16,16]); + TMPQ1[64,32] = zext(Rm_VPR64.4H[32,16]); + TMPQ1[96,32] = zext(Rm_VPR64.4H[48,16]); + # simd infix Rd_VPR128.4S = Rn_VPR128.4S - TMPQ1 on lane size 4 + Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] - TMPQ1[0,32]; + Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] - TMPQ1[32,32]; + Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] - TMPQ1[64,32]; + Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] - TMPQ1[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.397 USUBW, USUBW2 page C7-2927 line 170806 MATCH x2e203000/mask=xbf20fc00 +# CONSTRUCT x2e203000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $zext@1:16 =$-@2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubw/2@1 +# AUNIT --inst x2e203000/mask=xffe0fc00 --status pass --comment "ext" + +:usubw Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x3 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + # simd resize TMPQ1 = zext(Rm_VPR64.8B) (lane size 1 to 2) + TMPQ1[0,16] = zext(Rm_VPR64.8B[0,8]); + TMPQ1[16,16] = zext(Rm_VPR64.8B[8,8]); + TMPQ1[32,16] = zext(Rm_VPR64.8B[16,8]); + TMPQ1[48,16] = zext(Rm_VPR64.8B[24,8]); + TMPQ1[64,16] = zext(Rm_VPR64.8B[32,8]); + TMPQ1[80,16] = zext(Rm_VPR64.8B[40,8]); + TMPQ1[96,16] = zext(Rm_VPR64.8B[48,8]); + TMPQ1[112,16] = zext(Rm_VPR64.8B[56,8]); + # simd infix Rd_VPR128.8H = Rn_VPR128.8H - TMPQ1 on lane size 2 + Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] - TMPQ1[0,16]; + Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] - TMPQ1[16,16]; + Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] - TMPQ1[32,16]; + Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] - TMPQ1[48,16]; + Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] - TMPQ1[64,16]; + Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] - TMPQ1[80,16]; + Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] - TMPQ1[96,16]; + Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] - TMPQ1[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00 +# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00 +# CONSTRUCT x6f08a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 =$zext@1:16 +# SMACRO(pseudo) ARG1 ARG2 =NEON_uxtl2/1@1 +# AUNIT --inst x6f08a400/mask=xfffffc00 --status pass --comment "ext" + +:uxtl2 Rd_VPR128.8H, Rn_VPR128.16B +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3=0 & b_1115=0x14 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.8H & Zd +{ + TMPD1 = Rn_VPR128.16B[64,64]; + # simd resize Rd_VPR128.8H = zext(TMPD1) (lane size 1 to 2) + Rd_VPR128.8H[0,16] = zext(TMPD1[0,8]); + Rd_VPR128.8H[16,16] = zext(TMPD1[8,8]); + Rd_VPR128.8H[32,16] = zext(TMPD1[16,8]); + Rd_VPR128.8H[48,16] = zext(TMPD1[24,8]); + Rd_VPR128.8H[64,16] = zext(TMPD1[32,8]); + Rd_VPR128.8H[80,16] = zext(TMPD1[40,8]); + Rd_VPR128.8H[96,16] = zext(TMPD1[48,8]); + Rd_VPR128.8H[112,16] = zext(TMPD1[56,8]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00 +# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00 +# CONSTRUCT x2f20a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =var =$zext@4:16 +# SMACRO(pseudo) ARG1 ARG2 =NEON_uxtl/1@4 +# AUNIT --inst x2f20a400/mask=xfffffc00 --status pass --comment "ext" + +:uxtl Rd_VPR128.2D, Rn_VPR64.2S +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5=0 & b_1115=0x14 & b_1010=1 & Rn_VPR64.2S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR64.2S; + # simd resize Rd_VPR128.2D = zext(TMPD1) (lane size 4 to 8) + Rd_VPR128.2D[0,64] = zext(TMPD1[0,32]); + Rd_VPR128.2D[64,64] = zext(TMPD1[32,32]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00 +# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00 +# CONSTRUCT x2f10a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =var =$zext@2:16 +# SMACRO(pseudo) ARG1 ARG2 =NEON_uxtl/1@2 +# AUNIT --inst x2f10a400/mask=xfffffc00 --status pass --comment "ext" + +:uxtl Rd_VPR128.4S, Rn_VPR64.4H +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4=0 & b_1115=0x14 & b_1010=1 & Rn_VPR64.4H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR64.4H; + # simd resize Rd_VPR128.4S = zext(TMPD1) (lane size 2 to 4) + Rd_VPR128.4S[0,32] = zext(TMPD1[0,16]); + Rd_VPR128.4S[32,32] = zext(TMPD1[16,16]); + Rd_VPR128.4S[64,32] = zext(TMPD1[32,16]); + Rd_VPR128.4S[96,32] = zext(TMPD1[48,16]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00 +# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00 +# CONSTRUCT x6f20a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 =$zext@4:16 +# SMACRO(pseudo) ARG1 ARG2 =NEON_uxtl2/1@4 +# AUNIT --inst x6f20a400/mask=xfffffc00 --status pass --comment "ext" + +:uxtl2 Rd_VPR128.2D, Rn_VPR128.4S +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5=0 & b_1115=0x14 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.2D & Zd +{ + TMPD1 = Rn_VPR128.4S[64,64]; + # simd resize Rd_VPR128.2D = zext(TMPD1) (lane size 4 to 8) + Rd_VPR128.2D[0,64] = zext(TMPD1[0,32]); + Rd_VPR128.2D[64,64] = zext(TMPD1[32,32]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00 +# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00 +# CONSTRUCT x2f08a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 =var =$zext@1:16 +# SMACRO(pseudo) ARG1 ARG2 =NEON_uxtl/1@1 +# AUNIT --inst x2f08a400/mask=xfffffc00 --status pass --comment "ext" + +:uxtl Rd_VPR128.8H, Rn_VPR64.8B +is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3=0 & b_1115=0x14 & b_1010=1 & Rn_VPR64.8B & Rd_VPR128.8H & Zd +{ + TMPD1 = Rn_VPR64.8B; + # simd resize Rd_VPR128.8H = zext(TMPD1) (lane size 1 to 2) + Rd_VPR128.8H[0,16] = zext(TMPD1[0,8]); + Rd_VPR128.8H[16,16] = zext(TMPD1[8,8]); + Rd_VPR128.8H[32,16] = zext(TMPD1[16,8]); + Rd_VPR128.8H[48,16] = zext(TMPD1[24,8]); + Rd_VPR128.8H[64,16] = zext(TMPD1[32,8]); + Rd_VPR128.8H[80,16] = zext(TMPD1[40,8]); + Rd_VPR128.8H[96,16] = zext(TMPD1[48,8]); + Rd_VPR128.8H[112,16] = zext(TMPD1[56,8]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00 +# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00 +# CONSTRUCT x6f10a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2[1]:8 =$zext@2:16 +# SMACRO(pseudo) ARG1 ARG2 =NEON_uxtl2/1@2 +# AUNIT --inst x6f10a400/mask=xfffffc00 --status pass --comment "ext" + +:uxtl2 Rd_VPR128.4S, Rn_VPR128.8H +is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4=0 & b_1115=0x14 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPD1 = Rn_VPR128.8H[64,64]; + # simd resize Rd_VPR128.4S = zext(TMPD1) (lane size 2 to 4) + Rd_VPR128.4S[0,32] = zext(TMPD1[0,16]); + Rd_VPR128.4S[32,32] = zext(TMPD1[16,16]); + Rd_VPR128.4S[64,32] = zext(TMPD1[32,16]); + Rd_VPR128.4S[96,32] = zext(TMPD1[48,16]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.399 UZP1 page C7-2931 line 171030 MATCH x0e001800/mask=xbf20fc00 +# CONSTRUCT x4e001800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-1@4-2@6-3@8-4@10-5@12-6@14-7:1 swap &=$shuffle@0-8@2-9@4-10@6-11@8-12@10-13@12-14@14-15:1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@1 +# AUNIT --inst x4e001800/mask=xffe0fc00 --status pass + +:uzp1 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + TMPQ2 = Rm_VPR128.16B; + TMPQ1 = Rn_VPR128.16B; + # simd shuffle Rd_VPR128.16B = TMPQ1 (@0-0@2-1@4-2@6-3@8-4@10-5@12-6@14-7) lane size 1 + Rd_VPR128.16B[0,8] = TMPQ1[0,8]; + Rd_VPR128.16B[8,8] = TMPQ1[16,8]; + Rd_VPR128.16B[16,8] = TMPQ1[32,8]; + Rd_VPR128.16B[24,8] = TMPQ1[48,8]; + Rd_VPR128.16B[32,8] = TMPQ1[64,8]; + Rd_VPR128.16B[40,8] = TMPQ1[80,8]; + Rd_VPR128.16B[48,8] = TMPQ1[96,8]; + Rd_VPR128.16B[56,8] = TMPQ1[112,8]; + # simd shuffle Rd_VPR128.16B = TMPQ2 (@0-8@2-9@4-10@6-11@8-12@10-13@12-14@14-15) lane size 1 + Rd_VPR128.16B[64,8] = TMPQ2[0,8]; + Rd_VPR128.16B[72,8] = TMPQ2[16,8]; + Rd_VPR128.16B[80,8] = TMPQ2[32,8]; + Rd_VPR128.16B[88,8] = TMPQ2[48,8]; + Rd_VPR128.16B[96,8] = TMPQ2[64,8]; + Rd_VPR128.16B[104,8] = TMPQ2[80,8]; + Rd_VPR128.16B[112,8] = TMPQ2[96,8]; + Rd_VPR128.16B[120,8] = TMPQ2[112,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.399 UZP1 page C7-2931 line 171030 MATCH x0e001800/mask=xbf20fc00 +# CONSTRUCT x4ec01800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0:8 swap &=$shuffle@0-1:8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@8 +# AUNIT --inst x4ec01800/mask=xffe0fc00 --status pass + +:uzp1 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=3 & b_2121=0 & Rm_VPR128.2D & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + TMPQ2 = Rm_VPR128.2D; + TMPQ1 = Rn_VPR128.2D; + # simd shuffle Rd_VPR128.2D = TMPQ1 (@0-0) lane size 8 + Rd_VPR128.2D[0,64] = TMPQ1[0,64]; + # simd shuffle Rd_VPR128.2D = TMPQ2 (@0-1) lane size 8 + Rd_VPR128.2D[64,64] = TMPQ2[0,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.399 UZP1 page C7-2931 line 171030 MATCH x0e001800/mask=xbf20fc00 +# CONSTRUCT x0e801800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0:4 swap &=$shuffle@0-1:4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@4 +# AUNIT --inst x0e801800/mask=xffe0fc00 --status pass + +:uzp1 Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR64.2S & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + TMPD2 = Rm_VPR64.2S; + TMPD1 = Rn_VPR64.2S; + # simd shuffle Rd_VPR64.2S = TMPD1 (@0-0) lane size 4 + Rd_VPR64.2S[0,32] = TMPD1[0,32]; + # simd shuffle Rd_VPR64.2S = TMPD2 (@0-1) lane size 4 + Rd_VPR64.2S[32,32] = TMPD2[0,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.399 UZP1 page C7-2931 line 171030 MATCH x0e001800/mask=xbf20fc00 +# CONSTRUCT x0e401800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-1:2 swap &=$shuffle@0-2@2-3:2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@2 +# AUNIT --inst x0e401800/mask=xffe0fc00 --status pass + +:uzp1 Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR64.4H & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + TMPD2 = Rm_VPR64.4H; + TMPD1 = Rn_VPR64.4H; + # simd shuffle Rd_VPR64.4H = TMPD1 (@0-0@2-1) lane size 2 + Rd_VPR64.4H[0,16] = TMPD1[0,16]; + Rd_VPR64.4H[16,16] = TMPD1[32,16]; + # simd shuffle Rd_VPR64.4H = TMPD2 (@0-2@2-3) lane size 2 + Rd_VPR64.4H[32,16] = TMPD2[0,16]; + Rd_VPR64.4H[48,16] = TMPD2[32,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.399 UZP1 page C7-2931 line 171030 MATCH x0e001800/mask=xbf20fc00 +# CONSTRUCT x4e801800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-1:4 swap &=$shuffle@0-2@2-3:4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@4 +# AUNIT --inst x4e801800/mask=xffe0fc00 --status pass + +:uzp1 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR128.4S & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + TMPQ2 = Rm_VPR128.4S; + TMPQ1 = Rn_VPR128.4S; + # simd shuffle Rd_VPR128.4S = TMPQ1 (@0-0@2-1) lane size 4 + Rd_VPR128.4S[0,32] = TMPQ1[0,32]; + Rd_VPR128.4S[32,32] = TMPQ1[64,32]; + # simd shuffle Rd_VPR128.4S = TMPQ2 (@0-2@2-3) lane size 4 + Rd_VPR128.4S[64,32] = TMPQ2[0,32]; + Rd_VPR128.4S[96,32] = TMPQ2[64,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.399 UZP1 page C7-2931 line 171030 MATCH x0e001800/mask=xbf20fc00 +# CONSTRUCT x0e001800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-1@4-2@6-3:1 swap &=$shuffle@0-4@2-5@4-6@6-7:1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@1 +# AUNIT --inst x0e001800/mask=xffe0fc00 --status pass + +:uzp1 Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR64.8B & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + TMPD2 = Rm_VPR64.8B; + TMPD1 = Rn_VPR64.8B; + # simd shuffle Rd_VPR64.8B = TMPD1 (@0-0@2-1@4-2@6-3) lane size 1 + Rd_VPR64.8B[0,8] = TMPD1[0,8]; + Rd_VPR64.8B[8,8] = TMPD1[16,8]; + Rd_VPR64.8B[16,8] = TMPD1[32,8]; + Rd_VPR64.8B[24,8] = TMPD1[48,8]; + # simd shuffle Rd_VPR64.8B = TMPD2 (@0-4@2-5@4-6@6-7) lane size 1 + Rd_VPR64.8B[32,8] = TMPD2[0,8]; + Rd_VPR64.8B[40,8] = TMPD2[16,8]; + Rd_VPR64.8B[48,8] = TMPD2[32,8]; + Rd_VPR64.8B[56,8] = TMPD2[48,8]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.399 UZP1 page C7-2931 line 171030 MATCH x0e001800/mask=xbf20fc00 +# CONSTRUCT x4e401800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-1@4-2@6-3:2 swap &=$shuffle@0-4@2-5@4-6@6-7:2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@2 +# AUNIT --inst x4e401800/mask=xffe0fc00 --status pass + +:uzp1 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR128.8H & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + TMPQ2 = Rm_VPR128.8H; + TMPQ1 = Rn_VPR128.8H; + # simd shuffle Rd_VPR128.8H = TMPQ1 (@0-0@2-1@4-2@6-3) lane size 2 + Rd_VPR128.8H[0,16] = TMPQ1[0,16]; + Rd_VPR128.8H[16,16] = TMPQ1[32,16]; + Rd_VPR128.8H[32,16] = TMPQ1[64,16]; + Rd_VPR128.8H[48,16] = TMPQ1[96,16]; + # simd shuffle Rd_VPR128.8H = TMPQ2 (@0-4@2-5@4-6@6-7) lane size 2 + Rd_VPR128.8H[64,16] = TMPQ2[0,16]; + Rd_VPR128.8H[80,16] = TMPQ2[32,16]; + Rd_VPR128.8H[96,16] = TMPQ2[64,16]; + Rd_VPR128.8H[112,16] = TMPQ2[96,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.400 UZP2 page C7-2933 line 171142 MATCH x0e005800/mask=xbf20fc00 +# CONSTRUCT x4e005800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7:1 swap &=$shuffle@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15:1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@1 +# AUNIT --inst x4e005800/mask=xffe0fc00 --status pass + +:uzp2 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + TMPQ2 = Rm_VPR128.16B; + TMPQ1 = Rn_VPR128.16B; + # simd shuffle Rd_VPR128.16B = TMPQ1 (@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7) lane size 1 + Rd_VPR128.16B[0,8] = TMPQ1[8,8]; + Rd_VPR128.16B[8,8] = TMPQ1[24,8]; + Rd_VPR128.16B[16,8] = TMPQ1[40,8]; + Rd_VPR128.16B[24,8] = TMPQ1[56,8]; + Rd_VPR128.16B[32,8] = TMPQ1[72,8]; + Rd_VPR128.16B[40,8] = TMPQ1[88,8]; + Rd_VPR128.16B[48,8] = TMPQ1[104,8]; + Rd_VPR128.16B[56,8] = TMPQ1[120,8]; + # simd shuffle Rd_VPR128.16B = TMPQ2 (@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15) lane size 1 + Rd_VPR128.16B[64,8] = TMPQ2[8,8]; + Rd_VPR128.16B[72,8] = TMPQ2[24,8]; + Rd_VPR128.16B[80,8] = TMPQ2[40,8]; + Rd_VPR128.16B[88,8] = TMPQ2[56,8]; + Rd_VPR128.16B[96,8] = TMPQ2[72,8]; + Rd_VPR128.16B[104,8] = TMPQ2[88,8]; + Rd_VPR128.16B[112,8] = TMPQ2[104,8]; + Rd_VPR128.16B[120,8] = TMPQ2[120,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.400 UZP2 page C7-2933 line 171142 MATCH x0e005800/mask=xbf20fc00 +# CONSTRUCT x4ec05800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0:8 swap &=$shuffle@1-1:8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@8 +# AUNIT --inst x4ec05800/mask=xffe0fc00 --status pass + +:uzp2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=3 & b_2121=0 & Rm_VPR128.2D & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + TMPQ2 = Rm_VPR128.2D; + TMPQ1 = Rn_VPR128.2D; + # simd shuffle Rd_VPR128.2D = TMPQ1 (@1-0) lane size 8 + Rd_VPR128.2D[0,64] = TMPQ1[64,64]; + # simd shuffle Rd_VPR128.2D = TMPQ2 (@1-1) lane size 8 + Rd_VPR128.2D[64,64] = TMPQ2[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.400 UZP2 page C7-2933 line 171142 MATCH x0e005800/mask=xbf20fc00 +# CONSTRUCT x0e805800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0:4 swap &=$shuffle@1-1:4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@4 +# AUNIT --inst x0e805800/mask=xffe0fc00 --status pass + +:uzp2 Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR64.2S & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + TMPD2 = Rm_VPR64.2S; + TMPD1 = Rn_VPR64.2S; + # simd shuffle Rd_VPR64.2S = TMPD1 (@1-0) lane size 4 + Rd_VPR64.2S[0,32] = TMPD1[32,32]; + # simd shuffle Rd_VPR64.2S = TMPD2 (@1-1) lane size 4 + Rd_VPR64.2S[32,32] = TMPD2[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.400 UZP2 page C7-2933 line 171142 MATCH x0e005800/mask=xbf20fc00 +# CONSTRUCT x0e405800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-1:2 swap &=$shuffle@1-2@3-3:2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@2 +# AUNIT --inst x0e405800/mask=xffe0fc00 --status pass + +:uzp2 Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR64.4H & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + TMPD2 = Rm_VPR64.4H; + TMPD1 = Rn_VPR64.4H; + # simd shuffle Rd_VPR64.4H = TMPD1 (@1-0@3-1) lane size 2 + Rd_VPR64.4H[0,16] = TMPD1[16,16]; + Rd_VPR64.4H[16,16] = TMPD1[48,16]; + # simd shuffle Rd_VPR64.4H = TMPD2 (@1-2@3-3) lane size 2 + Rd_VPR64.4H[32,16] = TMPD2[16,16]; + Rd_VPR64.4H[48,16] = TMPD2[48,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.400 UZP2 page C7-2933 line 171142 MATCH x0e005800/mask=xbf20fc00 +# CONSTRUCT x4e805800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-1:4 swap &=$shuffle@1-2@3-3:4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@4 +# AUNIT --inst x4e805800/mask=xffe0fc00 --status pass + +:uzp2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR128.4S & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + TMPQ2 = Rm_VPR128.4S; + TMPQ1 = Rn_VPR128.4S; + # simd shuffle Rd_VPR128.4S = TMPQ1 (@1-0@3-1) lane size 4 + Rd_VPR128.4S[0,32] = TMPQ1[32,32]; + Rd_VPR128.4S[32,32] = TMPQ1[96,32]; + # simd shuffle Rd_VPR128.4S = TMPQ2 (@1-2@3-3) lane size 4 + Rd_VPR128.4S[64,32] = TMPQ2[32,32]; + Rd_VPR128.4S[96,32] = TMPQ2[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.400 UZP2 page C7-2933 line 171142 MATCH x0e005800/mask=xbf20fc00 +# CONSTRUCT x0e005800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-1@5-2@7-3:1 swap &=$shuffle@1-4@3-5@5-6@7-7:1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@1 +# AUNIT --inst x0e005800/mask=xffe0fc00 --status pass + +:uzp2 Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR64.8B & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + TMPD2 = Rm_VPR64.8B; + TMPD1 = Rn_VPR64.8B; + # simd shuffle Rd_VPR64.8B = TMPD1 (@1-0@3-1@5-2@7-3) lane size 1 + Rd_VPR64.8B[0,8] = TMPD1[8,8]; + Rd_VPR64.8B[8,8] = TMPD1[24,8]; + Rd_VPR64.8B[16,8] = TMPD1[40,8]; + Rd_VPR64.8B[24,8] = TMPD1[56,8]; + # simd shuffle Rd_VPR64.8B = TMPD2 (@1-4@3-5@5-6@7-7) lane size 1 + Rd_VPR64.8B[32,8] = TMPD2[8,8]; + Rd_VPR64.8B[40,8] = TMPD2[24,8]; + Rd_VPR64.8B[48,8] = TMPD2[40,8]; + Rd_VPR64.8B[56,8] = TMPD2[56,8]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.400 UZP2 page C7-2933 line 171142 MATCH x0e005800/mask=xbf20fc00 +# CONSTRUCT x4e405800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-1@5-2@7-3:2 swap &=$shuffle@1-4@3-5@5-6@7-7:2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@2 +# AUNIT --inst x4e405800/mask=xffe0fc00 --status pass + +:uzp2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR128.8H & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + TMPQ2 = Rm_VPR128.8H; + TMPQ1 = Rn_VPR128.8H; + # simd shuffle Rd_VPR128.8H = TMPQ1 (@1-0@3-1@5-2@7-3) lane size 2 + Rd_VPR128.8H[0,16] = TMPQ1[16,16]; + Rd_VPR128.8H[16,16] = TMPQ1[48,16]; + Rd_VPR128.8H[32,16] = TMPQ1[80,16]; + Rd_VPR128.8H[48,16] = TMPQ1[112,16]; + # simd shuffle Rd_VPR128.8H = TMPQ2 (@1-4@3-5@5-6@7-7) lane size 2 + Rd_VPR128.8H[64,16] = TMPQ2[16,16]; + Rd_VPR128.8H[80,16] = TMPQ2[48,16]; + Rd_VPR128.8H[96,16] = TMPQ2[80,16]; + Rd_VPR128.8H[112,16] = TMPQ2[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.401 XAR page C7-2935 line 171254 MATCH xce800000/mask=xffe00000 +# CONSTRUCT xce800000/mask=xffe00000 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 ARG3 $|@8 ARG4 =var:8 =$>>@8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_xar/3@8 +# AUNIT --inst xce800000/mask=xffe00000 --status noqemu +# Advanced SIMD variant + +:xar Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D, LSB_bitfield64_imm +is b_2131=0b11001110100 & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & LSB_bitfield64_imm & Zd +{ + # simd infix TMPQ1 = Rn_VPR128.2D | Rm_VPR128.2D on lane size 8 + TMPQ1[0,64] = Rn_VPR128.2D[0,64] | Rm_VPR128.2D[0,64]; + TMPQ1[64,64] = Rn_VPR128.2D[64,64] | Rm_VPR128.2D[64,64]; + local tmp2:8 = LSB_bitfield64_imm; + # simd infix Rd_VPR128.2D = TMPQ1 >> tmp2 on lane size 8 + Rd_VPR128.2D[0,64] = TMPQ1[0,64] >> tmp2; + Rd_VPR128.2D[64,64] = TMPQ1[64,64] >> tmp2; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.402 XTN, XTN2 page C7-2936 line 171324 MATCH x0e212800/mask=xbf3ffc00 +# CONSTRUCT x0ea12800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@8:8 &=$shuffle@0-0@1-1:4 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_xtn/2@8 +# AUNIT --inst x0ea12800/mask=xfffffc00 --status pass --comment "ext" + +:xtn Rd_VPR64.2S, Rn_VPR128.2D +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x12 & b_1011=2 & Rn_VPR128.2D & Rd_VPR64.2S & Zd +{ + # simd resize TMPD1 = zext(Rn_VPR128.2D) (lane size 8 to 4) + TMPD1[0,32] = Rn_VPR128.2D[0,32]; + TMPD1[32,32] = Rn_VPR128.2D[64,32]; + # simd shuffle Rd_VPR64.2S = TMPD1 (@0-0@1-1) lane size 4 + Rd_VPR64.2S[0,32] = TMPD1[0,32]; + Rd_VPR64.2S[32,32] = TMPD1[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.402 XTN, XTN2 page C7-2936 line 171324 MATCH x0e212800/mask=xbf3ffc00 +# CONSTRUCT x4ea12800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@8:8 &=$shuffle@0-2@1-3:4 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_xtn2/2@8 +# AUNIT --inst x4ea12800/mask=xfffffc00 --status pass --comment "ext" + +:xtn2 Rd_VPR128.4S, Rn_VPR128.2D +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x12 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.4S & Zd +{ + # simd resize TMPD1 = zext(Rn_VPR128.2D) (lane size 8 to 4) + TMPD1[0,32] = Rn_VPR128.2D[0,32]; + TMPD1[32,32] = Rn_VPR128.2D[64,32]; + # simd shuffle Rd_VPR128.4S = TMPD1 (@0-2@1-3) lane size 4 + Rd_VPR128.4S[64,32] = TMPD1[0,32]; + Rd_VPR128.4S[96,32] = TMPD1[32,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.402 XTN, XTN2 page C7-2936 line 171324 MATCH x0e212800/mask=xbf3ffc00 +# CONSTRUCT x0e612800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@4:8 &=$shuffle@0-0@1-1@2-2@3-3:2 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_xtn/2@4 +# AUNIT --inst x0e612800/mask=xfffffc00 --status pass --comment "ext" + +:xtn Rd_VPR64.4H, Rn_VPR128.4S +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x12 & b_1011=2 & Rn_VPR128.4S & Rd_VPR64.4H & Zd +{ + # simd resize TMPD1 = zext(Rn_VPR128.4S) (lane size 4 to 2) + TMPD1[0,16] = Rn_VPR128.4S[0,16]; + TMPD1[16,16] = Rn_VPR128.4S[32,16]; + TMPD1[32,16] = Rn_VPR128.4S[64,16]; + TMPD1[48,16] = Rn_VPR128.4S[96,16]; + # simd shuffle Rd_VPR64.4H = TMPD1 (@0-0@1-1@2-2@3-3) lane size 2 + Rd_VPR64.4H[0,16] = TMPD1[0,16]; + Rd_VPR64.4H[16,16] = TMPD1[16,16]; + Rd_VPR64.4H[32,16] = TMPD1[32,16]; + Rd_VPR64.4H[48,16] = TMPD1[48,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.402 XTN, XTN2 page C7-2936 line 171324 MATCH x0e212800/mask=xbf3ffc00 +# CONSTRUCT x4e612800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@4:8 &=$shuffle@0-4@1-5@2-6@3-7:2 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_xtn2/2@4 +# AUNIT --inst x4e612800/mask=xfffffc00 --status pass --comment "ext" + +:xtn2 Rd_VPR128.8H, Rn_VPR128.4S +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x12 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.8H & Zd +{ + # simd resize TMPD1 = zext(Rn_VPR128.4S) (lane size 4 to 2) + TMPD1[0,16] = Rn_VPR128.4S[0,16]; + TMPD1[16,16] = Rn_VPR128.4S[32,16]; + TMPD1[32,16] = Rn_VPR128.4S[64,16]; + TMPD1[48,16] = Rn_VPR128.4S[96,16]; + # simd shuffle Rd_VPR128.8H = TMPD1 (@0-4@1-5@2-6@3-7) lane size 2 + Rd_VPR128.8H[64,16] = TMPD1[0,16]; + Rd_VPR128.8H[80,16] = TMPD1[16,16]; + Rd_VPR128.8H[96,16] = TMPD1[32,16]; + Rd_VPR128.8H[112,16] = TMPD1[48,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.402 XTN, XTN2 page C7-2936 line 171324 MATCH x0e212800/mask=xbf3ffc00 +# CONSTRUCT x0e212800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@2:8 &=$shuffle@0-0@1-1@2-2@3-3@4-4@5-5@6-6@7-7:1 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_xtn/2@2 +# AUNIT --inst x0e212800/mask=xfffffc00 --status pass --comment "ext" + +:xtn Rd_VPR64.8B, Rn_VPR128.8H +is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x12 & b_1011=2 & Rn_VPR128.8H & Rd_VPR64.8B & Zd +{ + # simd resize TMPD1 = zext(Rn_VPR128.8H) (lane size 2 to 1) + TMPD1[0,8] = Rn_VPR128.8H[0,8]; + TMPD1[8,8] = Rn_VPR128.8H[16,8]; + TMPD1[16,8] = Rn_VPR128.8H[32,8]; + TMPD1[24,8] = Rn_VPR128.8H[48,8]; + TMPD1[32,8] = Rn_VPR128.8H[64,8]; + TMPD1[40,8] = Rn_VPR128.8H[80,8]; + TMPD1[48,8] = Rn_VPR128.8H[96,8]; + TMPD1[56,8] = Rn_VPR128.8H[112,8]; + # simd shuffle Rd_VPR64.8B = TMPD1 (@0-0@1-1@2-2@3-3@4-4@5-5@6-6@7-7) lane size 1 + Rd_VPR64.8B[0,8] = TMPD1[0,8]; + Rd_VPR64.8B[8,8] = TMPD1[8,8]; + Rd_VPR64.8B[16,8] = TMPD1[16,8]; + Rd_VPR64.8B[24,8] = TMPD1[24,8]; + Rd_VPR64.8B[32,8] = TMPD1[32,8]; + Rd_VPR64.8B[40,8] = TMPD1[40,8]; + Rd_VPR64.8B[48,8] = TMPD1[48,8]; + Rd_VPR64.8B[56,8] = TMPD1[56,8]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.402 XTN, XTN2 page C7-2936 line 171324 MATCH x0e212800/mask=xbf3ffc00 +# CONSTRUCT x4e212800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG1 ARG2 $zext@2:8 &=$shuffle@0-8@1-9@2-10@3-11@4-12@5-13@6-14@7-15:1 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_xtn2/2@2 +# AUNIT --inst x4e212800/mask=xfffffc00 --status pass --comment "ext" + +:xtn2 Rd_VPR128.16B, Rn_VPR128.8H +is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x12 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.16B & Zd +{ + # simd resize TMPD1 = zext(Rn_VPR128.8H) (lane size 2 to 1) + TMPD1[0,8] = Rn_VPR128.8H[0,8]; + TMPD1[8,8] = Rn_VPR128.8H[16,8]; + TMPD1[16,8] = Rn_VPR128.8H[32,8]; + TMPD1[24,8] = Rn_VPR128.8H[48,8]; + TMPD1[32,8] = Rn_VPR128.8H[64,8]; + TMPD1[40,8] = Rn_VPR128.8H[80,8]; + TMPD1[48,8] = Rn_VPR128.8H[96,8]; + TMPD1[56,8] = Rn_VPR128.8H[112,8]; + # simd shuffle Rd_VPR128.16B = TMPD1 (@0-8@1-9@2-10@3-11@4-12@5-13@6-14@7-15) lane size 1 + Rd_VPR128.16B[64,8] = TMPD1[0,8]; + Rd_VPR128.16B[72,8] = TMPD1[8,8]; + Rd_VPR128.16B[80,8] = TMPD1[16,8]; + Rd_VPR128.16B[88,8] = TMPD1[24,8]; + Rd_VPR128.16B[96,8] = TMPD1[32,8]; + Rd_VPR128.16B[104,8] = TMPD1[40,8]; + Rd_VPR128.16B[112,8] = TMPD1[48,8]; + Rd_VPR128.16B[120,8] = TMPD1[56,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.403 ZIP1 page C7-2938 line 171432 MATCH x0e003800/mask=xbf20fc00 +# CONSTRUCT x4e003800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@1-2@2-4@3-6@4-8@5-10@6-12@7-14:1 swap &=$shuffle@0-1@1-3@2-5@3-7@4-9@5-11@6-13@7-15:1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@1 +# AUNIT --inst x4e003800/mask=xffe0fc00 --status pass + +:zip1 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + TMPQ2 = Rm_VPR128.16B; + TMPQ1 = Rn_VPR128.16B; + # simd shuffle Rd_VPR128.16B = TMPQ1 (@0-0@1-2@2-4@3-6@4-8@5-10@6-12@7-14) lane size 1 + Rd_VPR128.16B[0,8] = TMPQ1[0,8]; + Rd_VPR128.16B[16,8] = TMPQ1[8,8]; + Rd_VPR128.16B[32,8] = TMPQ1[16,8]; + Rd_VPR128.16B[48,8] = TMPQ1[24,8]; + Rd_VPR128.16B[64,8] = TMPQ1[32,8]; + Rd_VPR128.16B[80,8] = TMPQ1[40,8]; + Rd_VPR128.16B[96,8] = TMPQ1[48,8]; + Rd_VPR128.16B[112,8] = TMPQ1[56,8]; + # simd shuffle Rd_VPR128.16B = TMPQ2 (@0-1@1-3@2-5@3-7@4-9@5-11@6-13@7-15) lane size 1 + Rd_VPR128.16B[8,8] = TMPQ2[0,8]; + Rd_VPR128.16B[24,8] = TMPQ2[8,8]; + Rd_VPR128.16B[40,8] = TMPQ2[16,8]; + Rd_VPR128.16B[56,8] = TMPQ2[24,8]; + Rd_VPR128.16B[72,8] = TMPQ2[32,8]; + Rd_VPR128.16B[88,8] = TMPQ2[40,8]; + Rd_VPR128.16B[104,8] = TMPQ2[48,8]; + Rd_VPR128.16B[120,8] = TMPQ2[56,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.403 ZIP1 page C7-2938 line 171432 MATCH x0e003800/mask=xbf20fc00 +# CONSTRUCT x4ec03800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0:8 swap &=$shuffle@0-1:8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@8 +# AUNIT --inst x4ec03800/mask=xffe0fc00 --status pass + +:zip1 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=3 & b_2121=0 & Rm_VPR128.2D & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + TMPQ2 = Rm_VPR128.2D; + TMPQ1 = Rn_VPR128.2D; + # simd shuffle Rd_VPR128.2D = TMPQ1 (@0-0) lane size 8 + Rd_VPR128.2D[0,64] = TMPQ1[0,64]; + # simd shuffle Rd_VPR128.2D = TMPQ2 (@0-1) lane size 8 + Rd_VPR128.2D[64,64] = TMPQ2[0,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.403 ZIP1 page C7-2938 line 171432 MATCH x0e003800/mask=xbf20fc00 +# CONSTRUCT x0e803800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0:4 swap &=$shuffle@0-1:4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@4 +# AUNIT --inst x0e803800/mask=xffe0fc00 --status pass + +:zip1 Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR64.2S & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + TMPD2 = Rm_VPR64.2S; + TMPD1 = Rn_VPR64.2S; + # simd shuffle Rd_VPR64.2S = TMPD1 (@0-0) lane size 4 + Rd_VPR64.2S[0,32] = TMPD1[0,32]; + # simd shuffle Rd_VPR64.2S = TMPD2 (@0-1) lane size 4 + Rd_VPR64.2S[32,32] = TMPD2[0,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.403 ZIP1 page C7-2938 line 171432 MATCH x0e003800/mask=xbf20fc00 +# CONSTRUCT x0e403800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@1-2:2 swap &=$shuffle@0-1@1-3:2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@2 +# AUNIT --inst x0e403800/mask=xffe0fc00 --status pass + +:zip1 Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR64.4H & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + TMPD2 = Rm_VPR64.4H; + TMPD1 = Rn_VPR64.4H; + # simd shuffle Rd_VPR64.4H = TMPD1 (@0-0@1-2) lane size 2 + Rd_VPR64.4H[0,16] = TMPD1[0,16]; + Rd_VPR64.4H[32,16] = TMPD1[16,16]; + # simd shuffle Rd_VPR64.4H = TMPD2 (@0-1@1-3) lane size 2 + Rd_VPR64.4H[16,16] = TMPD2[0,16]; + Rd_VPR64.4H[48,16] = TMPD2[16,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.403 ZIP1 page C7-2938 line 171432 MATCH x0e003800/mask=xbf20fc00 +# CONSTRUCT x4e803800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@1-2:4 swap &=$shuffle@0-1@1-3:4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@4 +# AUNIT --inst x4e803800/mask=xffe0fc00 --status pass + +:zip1 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR128.4S & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + TMPQ2 = Rm_VPR128.4S; + TMPQ1 = Rn_VPR128.4S; + # simd shuffle Rd_VPR128.4S = TMPQ1 (@0-0@1-2) lane size 4 + Rd_VPR128.4S[0,32] = TMPQ1[0,32]; + Rd_VPR128.4S[64,32] = TMPQ1[32,32]; + # simd shuffle Rd_VPR128.4S = TMPQ2 (@0-1@1-3) lane size 4 + Rd_VPR128.4S[32,32] = TMPQ2[0,32]; + Rd_VPR128.4S[96,32] = TMPQ2[32,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.403 ZIP1 page C7-2938 line 171432 MATCH x0e003800/mask=xbf20fc00 +# CONSTRUCT x0e003800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@1-2@2-4@3-6:1 swap &=$shuffle@0-1@1-3@2-5@3-7:1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@1 +# AUNIT --inst x0e003800/mask=xffe0fc00 --status pass + +:zip1 Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR64.8B & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + TMPD2 = Rm_VPR64.8B; + TMPD1 = Rn_VPR64.8B; + # simd shuffle Rd_VPR64.8B = TMPD1 (@0-0@1-2@2-4@3-6) lane size 1 + Rd_VPR64.8B[0,8] = TMPD1[0,8]; + Rd_VPR64.8B[16,8] = TMPD1[8,8]; + Rd_VPR64.8B[32,8] = TMPD1[16,8]; + Rd_VPR64.8B[48,8] = TMPD1[24,8]; + # simd shuffle Rd_VPR64.8B = TMPD2 (@0-1@1-3@2-5@3-7) lane size 1 + Rd_VPR64.8B[8,8] = TMPD2[0,8]; + Rd_VPR64.8B[24,8] = TMPD2[8,8]; + Rd_VPR64.8B[40,8] = TMPD2[16,8]; + Rd_VPR64.8B[56,8] = TMPD2[24,8]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.403 ZIP1 page C7-2938 line 171432 MATCH x0e003800/mask=xbf20fc00 +# CONSTRUCT x4e403800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@1-2@2-4@3-6:2 swap &=$shuffle@0-1@1-3@2-5@3-7:2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@2 +# AUNIT --inst x4e403800/mask=xffe0fc00 --status pass + +:zip1 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR128.8H & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + TMPQ2 = Rm_VPR128.8H; + TMPQ1 = Rn_VPR128.8H; + # simd shuffle Rd_VPR128.8H = TMPQ1 (@0-0@1-2@2-4@3-6) lane size 2 + Rd_VPR128.8H[0,16] = TMPQ1[0,16]; + Rd_VPR128.8H[32,16] = TMPQ1[16,16]; + Rd_VPR128.8H[64,16] = TMPQ1[32,16]; + Rd_VPR128.8H[96,16] = TMPQ1[48,16]; + # simd shuffle Rd_VPR128.8H = TMPQ2 (@0-1@1-3@2-5@3-7) lane size 2 + Rd_VPR128.8H[16,16] = TMPQ2[0,16]; + Rd_VPR128.8H[48,16] = TMPQ2[16,16]; + Rd_VPR128.8H[80,16] = TMPQ2[32,16]; + Rd_VPR128.8H[112,16] = TMPQ2[48,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.404 ZIP2 page C7-2940 line 171547 MATCH x0e007800/mask=xbf20fc00 +# CONSTRUCT x4e007800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@8-0@9-2@10-4@11-6@12-8@13-10@14-12@15-14:1 swap &=$shuffle@8-1@9-3@10-5@11-7@12-9@13-11@14-13@15-15:1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@1 +# AUNIT --inst x4e007800/mask=xffe0fc00 --status pass + +:zip2 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd +{ + TMPQ2 = Rm_VPR128.16B; + TMPQ1 = Rn_VPR128.16B; + # simd shuffle Rd_VPR128.16B = TMPQ1 (@8-0@9-2@10-4@11-6@12-8@13-10@14-12@15-14) lane size 1 + Rd_VPR128.16B[0,8] = TMPQ1[64,8]; + Rd_VPR128.16B[16,8] = TMPQ1[72,8]; + Rd_VPR128.16B[32,8] = TMPQ1[80,8]; + Rd_VPR128.16B[48,8] = TMPQ1[88,8]; + Rd_VPR128.16B[64,8] = TMPQ1[96,8]; + Rd_VPR128.16B[80,8] = TMPQ1[104,8]; + Rd_VPR128.16B[96,8] = TMPQ1[112,8]; + Rd_VPR128.16B[112,8] = TMPQ1[120,8]; + # simd shuffle Rd_VPR128.16B = TMPQ2 (@8-1@9-3@10-5@11-7@12-9@13-11@14-13@15-15) lane size 1 + Rd_VPR128.16B[8,8] = TMPQ2[64,8]; + Rd_VPR128.16B[24,8] = TMPQ2[72,8]; + Rd_VPR128.16B[40,8] = TMPQ2[80,8]; + Rd_VPR128.16B[56,8] = TMPQ2[88,8]; + Rd_VPR128.16B[72,8] = TMPQ2[96,8]; + Rd_VPR128.16B[88,8] = TMPQ2[104,8]; + Rd_VPR128.16B[104,8] = TMPQ2[112,8]; + Rd_VPR128.16B[120,8] = TMPQ2[120,8]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.404 ZIP2 page C7-2940 line 171547 MATCH x0e007800/mask=xbf20fc00 +# CONSTRUCT x4ec07800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0:8 swap &=$shuffle@1-1:8 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@8 +# AUNIT --inst x4ec07800/mask=xffe0fc00 --status pass + +:zip2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D +is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=3 & b_2121=0 & Rm_VPR128.2D & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd +{ + TMPQ2 = Rm_VPR128.2D; + TMPQ1 = Rn_VPR128.2D; + # simd shuffle Rd_VPR128.2D = TMPQ1 (@1-0) lane size 8 + Rd_VPR128.2D[0,64] = TMPQ1[64,64]; + # simd shuffle Rd_VPR128.2D = TMPQ2 (@1-1) lane size 8 + Rd_VPR128.2D[64,64] = TMPQ2[64,64]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.404 ZIP2 page C7-2940 line 171547 MATCH x0e007800/mask=xbf20fc00 +# CONSTRUCT x0e807800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0:4 swap &=$shuffle@1-1:4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@4 +# AUNIT --inst x0e807800/mask=xffe0fc00 --status pass + +:zip2 Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S +is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR64.2S & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd +{ + TMPD2 = Rm_VPR64.2S; + TMPD1 = Rn_VPR64.2S; + # simd shuffle Rd_VPR64.2S = TMPD1 (@1-0) lane size 4 + Rd_VPR64.2S[0,32] = TMPD1[32,32]; + # simd shuffle Rd_VPR64.2S = TMPD2 (@1-1) lane size 4 + Rd_VPR64.2S[32,32] = TMPD2[32,32]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.404 ZIP2 page C7-2940 line 171547 MATCH x0e007800/mask=xbf20fc00 +# CONSTRUCT x0e407800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@2-0@3-2:2 swap &=$shuffle@2-1@3-3:2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@2 +# AUNIT --inst x0e407800/mask=xffe0fc00 --status pass + +:zip2 Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H +is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR64.4H & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd +{ + TMPD2 = Rm_VPR64.4H; + TMPD1 = Rn_VPR64.4H; + # simd shuffle Rd_VPR64.4H = TMPD1 (@2-0@3-2) lane size 2 + Rd_VPR64.4H[0,16] = TMPD1[32,16]; + Rd_VPR64.4H[32,16] = TMPD1[48,16]; + # simd shuffle Rd_VPR64.4H = TMPD2 (@2-1@3-3) lane size 2 + Rd_VPR64.4H[16,16] = TMPD2[32,16]; + Rd_VPR64.4H[48,16] = TMPD2[48,16]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.404 ZIP2 page C7-2940 line 171547 MATCH x0e007800/mask=xbf20fc00 +# CONSTRUCT x4e807800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@2-0@3-2:4 swap &=$shuffle@2-1@3-3:4 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@4 +# AUNIT --inst x4e807800/mask=xffe0fc00 --status pass + +:zip2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S +is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR128.4S & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd +{ + TMPQ2 = Rm_VPR128.4S; + TMPQ1 = Rn_VPR128.4S; + # simd shuffle Rd_VPR128.4S = TMPQ1 (@2-0@3-2) lane size 4 + Rd_VPR128.4S[0,32] = TMPQ1[64,32]; + Rd_VPR128.4S[64,32] = TMPQ1[96,32]; + # simd shuffle Rd_VPR128.4S = TMPQ2 (@2-1@3-3) lane size 4 + Rd_VPR128.4S[32,32] = TMPQ2[64,32]; + Rd_VPR128.4S[96,32] = TMPQ2[96,32]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.404 ZIP2 page C7-2940 line 171547 MATCH x0e007800/mask=xbf20fc00 +# CONSTRUCT x0e007800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@4-0@5-2@6-4@7-6:1 swap &=$shuffle@4-1@5-3@6-5@7-7:1 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@1 +# AUNIT --inst x0e007800/mask=xffe0fc00 --status pass + +:zip2 Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B +is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR64.8B & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd +{ + TMPD2 = Rm_VPR64.8B; + TMPD1 = Rn_VPR64.8B; + # simd shuffle Rd_VPR64.8B = TMPD1 (@4-0@5-2@6-4@7-6) lane size 1 + Rd_VPR64.8B[0,8] = TMPD1[32,8]; + Rd_VPR64.8B[16,8] = TMPD1[40,8]; + Rd_VPR64.8B[32,8] = TMPD1[48,8]; + Rd_VPR64.8B[48,8] = TMPD1[56,8]; + # simd shuffle Rd_VPR64.8B = TMPD2 (@4-1@5-3@6-5@7-7) lane size 1 + Rd_VPR64.8B[8,8] = TMPD2[32,8]; + Rd_VPR64.8B[24,8] = TMPD2[40,8]; + Rd_VPR64.8B[40,8] = TMPD2[48,8]; + Rd_VPR64.8B[56,8] = TMPD2[56,8]; + zext_zd(Zd); # zero upper 24 bytes of Zd +} + +# C7.2.404 ZIP2 page C7-2940 line 171547 MATCH x0e007800/mask=xbf20fc00 +# CONSTRUCT x4e407800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@4-0@5-2@6-4@7-6:2 swap &=$shuffle@4-1@5-3@6-5@7-7:2 +# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@2 +# AUNIT --inst x4e407800/mask=xffe0fc00 --status pass + +:zip2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR128.8H & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd +{ + TMPQ2 = Rm_VPR128.8H; + TMPQ1 = Rn_VPR128.8H; + # simd shuffle Rd_VPR128.8H = TMPQ1 (@4-0@5-2@6-4@7-6) lane size 2 + Rd_VPR128.8H[0,16] = TMPQ1[64,16]; + Rd_VPR128.8H[32,16] = TMPQ1[80,16]; + Rd_VPR128.8H[64,16] = TMPQ1[96,16]; + Rd_VPR128.8H[96,16] = TMPQ1[112,16]; + # simd shuffle Rd_VPR128.8H = TMPQ2 (@4-1@5-3@6-5@7-7) lane size 2 + Rd_VPR128.8H[16,16] = TMPQ2[64,16]; + Rd_VPR128.8H[48,16] = TMPQ2[80,16]; + Rd_VPR128.8H[80,16] = TMPQ2[96,16]; + Rd_VPR128.8H[112,16] = TMPQ2[112,16]; + zext_zq(Zd); # zero upper 16 bytes of Zd +} + + +# C7.2.13 BFCVT page C7-2037 line 118954 MATCH x1e634000/mask=xfffffc00 +# C7.2.69 FCVT page C7-2172 line 126762 MATCH x1e224000/mask=xff3e7c00 +# CONSTRUCT x1e634000/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES +# x1e634000/mask=xfffffc00 NOT MATCHED BY ANY CONSTRUCTOR +# SMACRO ARG1 ARG2 =float2float/1 +# SMACRO(pseudo) ARG1 ARG2 =NEON_bfcvt/1 +# b_0031=0001111001100011010000.......... +:bfcvt Rd_FPR16, Rn_FPR32 +is b_1031=0b0001111001100011010000 & Rd_FPR16 & Rn_FPR32 & Zd +{ + Rd_FPR16 = float2float(Rn_FPR32); + zext_zh(Zd); # zero upper 30 bytes of Zd +} + +# C7.2.14 BFCVTN, BFCVTN2 page C7-2038 line 119011 MATCH x0ea16800/mask=xbffffc00 +# CONSTRUCT x0ea16800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# x0ea16800/mask=xbffffc00 NOT MATCHED BY ANY CONSTRUCTOR +# SMACRO ARG1 ARG2 =var =$float2float@4:8 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtn/2@4 +# b_0031=0.00111010100001011010.......... + +:bfcvtn Rd_VPR128.4S, Rn_VPR128.4H +is b_3131=0b0 & Q=0 & b_1029=0b00111010100001011010 & Rn_VPR128.4H & Rd_VPR128.4S & Zd +{ + TMPQ1 = Rn_VPR128.4H; + # simd resize Rd_VPR128.4S = float2float(TMPQ1) (lane size 4 to 4) + Rd_VPR128.4S[0,32] = float2float(TMPQ1[0,32]); + Rd_VPR128.4S[32,32] = float2float(TMPQ1[32,32]); + Rd_VPR128.4S[64,32] = float2float(TMPQ1[64,32]); + Rd_VPR128.4S[96,32] = float2float(TMPQ1[96,32]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.14 BFCVTN, BFCVTN2 page C7-2038 line 119011 MATCH x0ea16800/mask=xbffffc00 +# CONSTRUCT x4ea16800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES +# x0ea16800/mask=xbffffc00 NOT MATCHED BY ANY CONSTRUCTOR +# SMACRO ARG1 ARG2 =var =$float2float@4:8 +# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtn/2@4 + +:bfcvtn2 Rd_VPR128.4S, Rn_VPR128.8H +is b_3131=0b0 & Q=1 & b_1029=0b00111010100001011010 & Rn_VPR128.8H & Rd_VPR128.4S & Zd +{ + TMPQ1 = Rn_VPR128.8H; + # simd resize Rd_VPR128.4S = float2float(TMPQ1) (lane size 4 to 4) + Rd_VPR128.4S[0,32] = float2float(TMPQ1[0,32]); + Rd_VPR128.4S[32,32] = float2float(TMPQ1[32,32]); + Rd_VPR128.4S[64,32] = float2float(TMPQ1[64,32]); + Rd_VPR128.4S[96,32] = float2float(TMPQ1[96,32]); + zext_zq(Zd); # zero upper 16 bytes of Zd +} + +# C7.2.15 BFDOT (by element) page C7-2039 line 119080 MATCH x0f40f000/mask=xbfc0f400 +# CONSTRUCT x0f40f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# x0f40f000/mask=xbfc0f400 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=0.00111101......1111.0.......... + +:bfdot Rd_VPR128.2S, Rn_VPR128.4H, , Re_VPR128.H.vIndexHL +is b_3131=0b0 & Q=0 & b_2229=0b00111101 & Re_VPR128.H.vIndexHL & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.4H & Rd_VPR128.2S +{ + Rd_VPR128.2S = NEON_bfdot(Rn_VPR128.4H, Re_VPR128.H.vIndexHL); +} + +# C7.2.15 BFDOT (by element) page C7-2039 line 119080 MATCH x0f40f000/mask=xbfc0f400 +# CONSTRUCT x4f40f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES + +:bfdot Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128.H.vIndexHL +is b_3131=0b0 & Q=1 & b_2229=0b00111101 & Re_VPR128.H.vIndexHL & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.8H & Rd_VPR128.4S +{ + Rd_VPR128.4S = NEON_bfdot(Rn_VPR128.8H, Re_VPR128.H.vIndexHL); +} + +# C7.2.16 BFDOT (vector) page C7-2041 line 119201 MATCH x2e40fc00/mask=xbfe0fc00 +# CONSTRUCT x2e40fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# x2e40fc00/mask=xbfe0fc00 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=0.101110010.....111111.......... + +:bfdot Rd_VPR128.2S, Rn_VPR128.4H, Rm_VPR128.4H +is b_3131=0b0 & Q=0 & b_2129=0b101110010 & Rm_VPR128.4H & b_1015=0b111111 & Rn_VPR128.4H & Rd_VPR128.2S +{ + Rd_VPR128.2S = NEON_bfdot(Rn_VPR128.4H, Rm_VPR128.4H); +} + +# C7.2.16 BFDOT (vector) page C7-2041 line 119201 MATCH x2e40fc00/mask=xbfe0fc00 +# CONSTRUCT x6e40fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES + +:bfdot Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0b0 & Q=1 & b_2129=0b101110010 & Rm_VPR128.8H & b_1015=0b111111 & Rn_VPR128.8H & Rd_VPR128.4S +{ + Rd_VPR128.4S = NEON_bfdot(Rn_VPR128.8H, Rm_VPR128.8H); +} + +# C7.2.17 BFMLALB, BFMLALT (by element) page C7-2043 line 119316 MATCH x0fc0f000/mask=xbfc0f400 +# CONSTRUCT x0fc0f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# x0fc0f000/mask=xbfc0f400 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=0.00111111......1111.0.......... + +:bfmlalb Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM +is b_3131=0b0 & Q=0 & b_2229=0b00111111 & Re_VPR128Lo.H.vIndexHLM & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.8H & Rd_VPR128.4S +{ + Rd_VPR128.4S = NEON_bfmlalb(Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM); +} + +# C7.2.17 BFMLALB, BFMLALT (by element) page C7-2043 line 119316 MATCH x0fc0f000/mask=xbfc0f400 +# CONSTRUCT x4fc0f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES + +:bfmlalt Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM +is b_3131=0b0 & Q=1 & b_2229=0b00111111 & Re_VPR128Lo.H.vIndexHLM & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.8H & Rd_VPR128.4S +{ + Rd_VPR128.4S = NEON_bfmlalt(Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM); +} + +# C7.2.18 BFMLALB, BFMLALT (vector) page C7-2045 line 119401 MATCH x2ec0fc00/mask=xbfe0fc00 +# CONSTRUCT x2ec0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# x2ec0fc00/mask=xbfe0fc00 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=0.101110110.....111111.......... + +:bfmlalb Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0b0 & Q=0 & b_2129=0b101110110 & Rm_VPR128.8H & b_1015=0b111111 & Rn_VPR128.8H & Rd_VPR128.4S +{ + Rd_VPR128.4S = NEON_bfmlalb(Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H); +} + +# C7.2.18 BFMLALB, BFMLALT (vector) page C7-2045 line 119401 MATCH x2ec0fc00/mask=xbfe0fc00 +# CONSTRUCT x6ec0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES + +:bfmlalt Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H +is b_3131=0b0 & Q=1 & b_2129=0b101110110 & Rm_VPR128.8H & b_1015=0b111111 & Rn_VPR128.8H & Rd_VPR128.4S +{ + Rd_VPR128.4S = NEON_bfmlalt(Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H); +} + +# C7.2.19 BFMMLA page C7-2046 line 119472 MATCH x6e40ec00/mask=xffe0fc00 +# CONSTRUCT x6e40ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# x6e40ec00/mask=xffe0fc00 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=01101110010.....111011.......... + +:bfmmla Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H +is b_2131=0b01101110010 & Rm_VPR128.8H & b_1015=0b111011 & Rn_VPR128.8H & Rd_VPR128.4S +{ + Rd_VPR128.4S = NEON_bfmmla(Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H); +} + +# C7.2.147 FRINT32X (vector) page C7-2353 line 137678 MATCH x2e21e800/mask=xbfbffc00 +# CONSTRUCT x2e21e800/mask=xbfbffc00 MATCHED 1 DOCUMENTED OPCODES +# x2e21e800/mask=xbfbffc00 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=0.1011100.100001111010.......... + +:frint32x +is b_3131=0b0 & Q & b_2329=0b1011100 & b_22 & b_1021=0b100001111010 & Rn & Rd +unimpl + +# C7.2.148 FRINT32X (scalar) page C7-2355 line 137767 MATCH x1e28c000/mask=xffbffc00 +# CONSTRUCT x1e28c000/mask=xffbffc00 MATCHED 1 DOCUMENTED OPCODES +# x1e28c000/mask=xffbffc00 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=000111100.101000110000.......... + +:frint32x +is b_2331=0b000111100 & b_22 & b_1021=0b101000110000 & Rn & Rd +unimpl + +# C7.2.149 FRINT32Z (vector) page C7-2357 line 137862 MATCH x0e21e800/mask=xbfbffc00 +# CONSTRUCT x0e21e800/mask=xbfbffc00 MATCHED 1 DOCUMENTED OPCODES +# x0e21e800/mask=xbfbffc00 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=0.0011100.100001111010.......... + +:frint32z +is b_3131=0b0 & Q & b_2329=0b0011100 & b_22 & b_1021=0b100001111010 & Rn & Rd +unimpl + +# C7.2.150 FRINT32Z (scalar) page C7-2359 line 137950 MATCH x1e284000/mask=xffbffc00 +# CONSTRUCT x1e284000/mask=xffbffc00 MATCHED 1 DOCUMENTED OPCODES +# x1e284000/mask=xffbffc00 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=000111100.101000010000.......... + +:frint32z +is b_2331=0b000111100 & b_22 & b_1021=0b101000010000 & Rn & Rd +unimpl + +# C7.2.151 FRINT64X (vector) page C7-2361 line 138043 MATCH x2e21f800/mask=xbfbffc00 +# CONSTRUCT x2e21f800/mask=xbfbffc00 MATCHED 1 DOCUMENTED OPCODES +# x2e21f800/mask=xbfbffc00 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=0.1011100.100001111110.......... + +:frint64x +is b_3131=0b0 & Q & b_2329=0b1011100 & b_22 & b_1021=0b100001111110 & Rn & Rd +unimpl + +# C7.2.152 FRINT64X (scalar) page C7-2363 line 138132 MATCH x1e29c000/mask=xffbffc00 +# CONSTRUCT x1e29c000/mask=xffbffc00 MATCHED 1 DOCUMENTED OPCODES +# x1e29c000/mask=xffbffc00 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=000111100.101001110000.......... + +:frint64x +is b_2331=0b000111100 & b_22 & b_1021=0b101001110000 & Rn & Rd +unimpl + +# C7.2.153 FRINT64Z (vector) page C7-2365 line 138227 MATCH x0e21f800/mask=xbfbffc00 +# CONSTRUCT x0e21f800/mask=xbfbffc00 MATCHED 1 DOCUMENTED OPCODES +# x0e21f800/mask=xbfbffc00 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=0.0011100.100001111110.......... + +:frint64z +is b_3131=0b0 & Q & b_2329=0b0011100 & b_22 & b_1021=0b100001111110 & Rn & Rd +unimpl + +# C7.2.154 FRINT64Z (scalar) page C7-2367 line 138315 MATCH x1e294000/mask=xffbffc00 +# CONSTRUCT x1e294000/mask=xffbffc00 MATCHED 1 DOCUMENTED OPCODES +# x1e294000/mask=xffbffc00 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=000111100.101001010000.......... + +:frint64z +is b_2331=0b000111100 & b_22 & b_1021=0b101001010000 & Rn & Rd +unimpl + +# C7.2.278 SMMLA (vector) page C7-2634 line 153703 MATCH x4e80a400/mask=xffe0fc00 +# CONSTRUCT x4e80a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# x4e80a400/mask=xffe0fc00 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=01001110100.....101001.......... + +:smmla Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B +is b_2131=0b01001110100 & Rm_VPR128.16B & b_1015=0b101001 & Rn_VPR128.16B & Rd_VPR128.4S +{ + Rd_VPR128.4S = NEON_smmla(Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B); +} + +# C7.2.336 SUDOT (by element) page C7-2795 line 163341 MATCH x0f00f000/mask=xbfc0f400 +# CONSTRUCT x0f00f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# x0f00f000/mask=xbfc0f400 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=0.00111100......1111.0.......... + +:sudot Rd_VPR128.2S, Rn_VPR128.8B, Re_VPR128.H.vIndexHL +is b_3131=0b0 & Q=0 & b_2229=0b00111100 & Re_VPR128.H.vIndexHL & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.8B & Rd_VPR128.2S +{ + Rd_VPR128.2S = NEON_sudot(Rd_VPR128.2S, Rn_VPR128.8B, Re_VPR128.H.vIndexHL); +} + +# C7.2.336 SUDOT (by element) page C7-2795 line 163341 MATCH x0f00f000/mask=xbfc0f400 +# CONSTRUCT x4f00f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES + +:sudot Rd_VPR128.4S, Rn_VPR128.16B, Re_VPR128.H.vIndexHL +is b_3131=0b0 & Q=1 & b_2229=0b00111100 & Re_VPR128.H.vIndexHL & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.16B & Rd_VPR128.4S +{ + Rd_VPR128.4S = NEON_sudot(Rd_VPR128.4S, Rn_VPR128.16B, Re_VPR128.H.vIndexHL); +} + +# C7.2.370 UMMLA (vector) page C7-2867 line 167357 MATCH x6e80a400/mask=xffe0fc00 +# CONSTRUCT x6e80a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# x6e80a400/mask=xffe0fc00 NOT MATCHED BY ANY CONSTRUCTOR +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_ummla/3@1 +# b_0031=01101110100.....101001.......... +:ummla Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B +is b_2131=0b01101110100 & Rm_VPR128.16B & b_1015=0b101001 & Rn_VPR128.16B & Rd_VPR128.4S +{ + Rd_VPR128.4S = NEON_ummla(Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} + +# C7.2.388 USDOT (vector) page C7-2907 line 169709 MATCH x0e809c00/mask=xbfe0fc00 +# CONSTRUCT x0e809c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# x0e809c00/mask=xbfe0fc00 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=0.001110100.....100111.......... + +:usdot Rd_VPR128.2S, Rn_VPR128.8B, Rm_VPR128.8B +is b_3131=0b0 & Q=0 & b_2129=0b001110100 & Rm_VPR128.8B & b_1015=0b100111 & Rn_VPR128.8B & Rd_VPR128.2S +{ + Rd_VPR128.2S = NEON_usdot(Rd_VPR128.2S, Rn_VPR128.8B, Rm_VPR128.8B); +} + +# C7.2.388 USDOT (vector) page C7-2907 line 169709 MATCH x0e809c00/mask=xbfe0fc00 +# CONSTRUCT x4e809c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES + +:usdot Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B +is b_3131=0b0 & Q=1 & b_2129=0b001110100 & Rn_VPR128.16B & b_1015=0b100111 & Rm_VPR128.16B & Rd_VPR128.4S +{ + Rd_VPR128.4S = NEON_usdot(Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B); +} + +# C7.2.389 USDOT (by element) page C7-2909 line 169795 MATCH x0f80f000/mask=xbfc0f400 +# CONSTRUCT x0f80f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES +# x0f80f000/mask=xbfc0f400 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=0.00111110......1111.0.......... + +:usdot Rd_VPR128.2S, Rn_VPR128.8B, Re_VPR128.H.vIndexHL +is b_3131=0b0 & Q=0 & b_2229=0b00111110 & Re_VPR128.H.vIndexHL & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.8B & Rd_VPR128.2S +{ + Rd_VPR128.2S = NEON_usdot(Rd_VPR128.2S, Rn_VPR128.8B, Re_VPR128.H.vIndexHL); +} + +# C7.2.389 USDOT (by element) page C7-2909 line 169795 MATCH x0f80f000/mask=xbfc0f400 +# CONSTRUCT x4f80f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES + +:usdot Rd_VPR128.4S, Rn_VPR128.16B, Re_VPR128.H.vIndexHL +is b_3131=0b0 & Q=1 & b_2229=0b00111110 & Re_VPR128.H.vIndexHL & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.16B & Rd_VPR128.4S +{ + Rd_VPR128.4S = NEON_usdot(Rd_VPR128.4S, Rn_VPR128.16B, Re_VPR128.H.vIndexHL); +} + +# C7.2.393 USMMLA (vector) page C7-2919 line 170338 MATCH x4e80ac00/mask=xffe0fc00 +# CONSTRUCT x4e80ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES +# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_usmmla/3@1 +# x4e80ac00/mask=xffe0fc00 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=01001110100.....101011.......... +:usmmla Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B +is b_2131=0b01001110100 & Rm_VPR128.16B & b_1015=0b101011 & Rn_VPR128.16B & Rd_VPR128.4S +{ + Rd_VPR128.4S = NEON_usmmla(Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B, 1:1); +} diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64sve.sinc b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64sve.sinc new file mode 100644 index 0000000..958b466 --- /dev/null +++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64sve.sinc @@ -0,0 +1,7405 @@ +# INFO This file automatically generated by andre on Mon Apr 30 14:51:39 2018 +# INFO Direct edits to this file may be lost in future updates +# INFO Command line arguments: ['../../../ProcessorTest/test/andre/scrape/sveit.py', '--sinc'] + +# abs_z_p_z.xml: ABS variant SVE +# PATTERN x0416a000/mask=xff3fe000 + +:abs Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_abs(Zd.T, Pg3_m, Zn.T); +} + +# add_z_p_zz.xml: ADD (vectors, predicated) variant SVE +# PATTERN x04000000/mask=xff3fe000 + +:add Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_add(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# add_z_zi.xml: ADD (immediate) variant SVE +# PATTERN x2520c000/mask=xff3fc000 + +:add Zd.T, Zd.T_2, sve_shf8_1_0to255 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b100 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1415=0b11 & sve_sh_13 & sve_imm8_0512 & sve_zdn_0004 & sve_shift_13 & Zd.T & Zd.T_2 & sve_imm8_1_0to255 & sve_shf8_1_0to255 +{ + Zd.T = SVE_add(Zd.T, Zd.T_2, sve_shf8_1_0to255, sve_shift_13:1); +} + +# add_z_zz.xml: ADD (vectors, unpredicated) variant SVE +# PATTERN x04200000/mask=xff20fc00 + +:add Zd.T, Zn.T, Zm.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b00 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T +{ + Zd.T = SVE_add(Zd.T, Zn.T, Zm.T); +} + +# addpl_r_ri.xml: ADDPL variant SVE +# PATTERN x04605000/mask=xffe0f800 + +:addpl Rd_GPR64xsp, Rm_GPR64xsp, "#"^sve_imm6_1_m32to31 +is sve_b_2331=0b000001000 & sve_b_22=1 & sve_b_21=1 & sve_rn_1620 & sve_b_1115=0b01010 & sve_imm6_0510 & sve_rd_0004 & Rd_GPR64xsp & Rm_GPR64xsp & sve_imm6_1_m32to31 +{ + Rd_GPR64xsp = SVE_addpl(Rd_GPR64xsp, Rm_GPR64xsp, sve_imm6_1_m32to31:1); +} + +# addvl_r_ri.xml: ADDVL variant SVE +# PATTERN x04205000/mask=xffe0f800 + +:addvl Rd_GPR64xsp, Rm_GPR64xsp, "#"^sve_imm6_1_m32to31 +is sve_b_2331=0b000001000 & sve_b_22=0 & sve_b_21=1 & sve_rn_1620 & sve_b_1115=0b01010 & sve_imm6_0510 & sve_rd_0004 & Rd_GPR64xsp & Rm_GPR64xsp & sve_imm6_1_m32to31 +{ + Rd_GPR64xsp = SVE_addvl(Rd_GPR64xsp, Rm_GPR64xsp, sve_imm6_1_m32to31:1); +} + +# adr_z_az.xml: ADR variant Packed offsets +# PATTERN x04a0a000/mask=xffa0f000 + +:adr Zd.T_sz, [Zn.T_sz, Zm.T_sz^sve_mod_amount] +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_sz_22 & sve_b_21=1 & sve_zm_1620 & sve_b_1215=0b1010 & sve_msz_1011 & sve_zn_0509 & sve_zd_0004 & sve_mod_amount & Zm.T_sz & Zd.T_sz & Zn.T_sz +{ + Zd.T_sz = SVE_adr(Zd.T_sz, Zn.T_sz, Zm.T_sz, sve_mod_amount:1); +} + +# adr_z_az.xml: ADR variant Unpacked 32-bit signed offsets +# PATTERN x0420a000/mask=xffe0f000 + +:adr Zd.D, [Zn.D, Zm.D, "sxtw"^sve_msz_1011] +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_21=1 & sve_zm_1620 & sve_b_1215=0b1010 & sve_msz_1011 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Zm.D +{ + Zd.D = SVE_adr(Zd.D, Zn.D, Zm.D, sve_msz_1011:1); +} + +# adr_z_az.xml: ADR variant Unpacked 32-bit unsigned offsets +# PATTERN x0460a000/mask=xffe0f000 + +:adr Zd.D, [Zn.D, Zm.D, "uxtw"^sve_msz_1011] +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_21=1 & sve_zm_1620 & sve_b_1215=0b1010 & sve_msz_1011 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Zm.D +{ + Zd.D = SVE_adr(Zd.D, Zn.D, Zm.D, sve_msz_1011:1); +} + +# and_p_p_pp.xml: AND, ANDS (predicates) variant Flag setting +# PATTERN x25404000/mask=xfff0c210 + +:ands Pd.B, Pg_z, Pn.B, Pm.B +is sve_b_2431=0b00100101 & sve_b_23=0 & sve_s_22=1 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B +{ + Pd.B = SVE_ands(Pd.B, Pg_z, Pn.B, Pm.B); +} + +# and_p_p_pp.xml: AND, ANDS (predicates) variant Not flag setting +# PATTERN x25004000/mask=xfff0c210 + +:and Pd.B, Pg_z, Pn.B, Pm.B +is sve_b_2431=0b00100101 & sve_b_23=0 & sve_s_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B +{ + Pd.B = SVE_and(Pd.B, Pg_z, Pn.B, Pm.B); +} + +# and_z_p_zz.xml: AND (vectors, predicated) variant SVE +# PATTERN x041a0000/mask=xff3fe000 + +:and Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_and(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# and_z_zi.xml: AND (immediate) variant SVE +# PATTERN x05800000/mask=xfffc0000 + +:and Zd.T_imm13, Zd.T_imm13_2, "#"^sve_decode_bit_mask +is sve_b_2431=0b00000101 & sve_b_23=1 & sve_b_22=0 & sve_b_1821=0b0000 & sve_imm13_0517 & sve_zdn_0004 & sve_decode_bit_mask & Zd.T_imm13 & Zd.T_imm13_2 +{ + Zd.T_imm13 = SVE_and(Zd.T_imm13, Zd.T_imm13_2, sve_decode_bit_mask:1); +} + +# and_z_zz.xml: AND (vectors, unpredicated) variant SVE +# PATTERN x04203000/mask=xffe0fc00 + +:and Zd.D, Zn.D, Zm.D +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_21=1 & sve_zm_1620 & sve_b_1015=0b001100 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Zm.D +{ + Zd.D = SVE_and(Zd.D, Zn.D, Zm.D); +} + +# andv_r_p_z.xml: ANDV variant SVE +# PATTERN x041a2000/mask=xff3fe000 + +:andv Rd_FPR8, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b00 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3 +{ + Rd_FPR8 = SVE_andv(Rd_FPR8, Pg3, Zn.T); +} + +# andv_r_p_z.xml: ANDV variant SVE +# PATTERN x041a2000/mask=xff3fe000 + +:andv Rd_FPR32, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b10 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3 +{ + Rd_FPR32 = SVE_andv(Rd_FPR32, Pg3, Zn.T); +} + +# andv_r_p_z.xml: ANDV variant SVE +# PATTERN x041a2000/mask=xff3fe000 + +:andv Rd_FPR16, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b01 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3 +{ + Rd_FPR16 = SVE_andv(Rd_FPR16, Pg3, Zn.T); +} + +# andv_r_p_z.xml: ANDV variant SVE +# PATTERN x041a2000/mask=xff3fe000 + +:andv Rd_FPR64, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b11 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3 +{ + Rd_FPR64 = SVE_andv(Rd_FPR64, Pg3, Zn.T); +} + +# asr_z_p_zi.xml: ASR (immediate, predicated) variant SVE +# PATTERN x04008000/mask=xff3fe000 + +:asr Zd.T_tszh, Pg3_m, Zd.T_tszh_2, "#"^sve_imm_shift +is sve_b_2431=0b00000100 & sve_tszh_2223 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_tszl_0809 & sve_imm3_0507 & sve_zdn_0004 & sve_imm_shift & Zd.T_tszh & Zd.T_tszh_2 & Pg3_m +{ + Zd.T_tszh = SVE_asr(Zd.T_tszh, Pg3_m, Zd.T_tszh_2, sve_imm_shift:1); +} + +# asr_z_p_zw.xml: ASR (wide elements, predicated) variant SVE +# PATTERN x04188000/mask=xff3fe000 + +:asr Zd.T, Pg3_m, Zd.T_2, Zn.D +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Pg3_m & Zn.D +{ + Zd.T = SVE_asr(Zd.T, Pg3_m, Zd.T_2, Zn.D); +} + +# asr_z_p_zz.xml: ASR (vectors) variant SVE +# PATTERN x04108000/mask=xff3fe000 + +:asr Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_asr(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# asr_z_zi.xml: ASR (immediate, unpredicated) variant SVE +# PATTERN x04209000/mask=xff20fc00 + +:asr Zd.T_tszh, Zn.T_tszh, "#"^sve_imm_shift +is sve_b_2431=0b00000100 & sve_tszh_2223 & sve_b_21=1 & sve_tszl_1920 & sve_imm3_1618 & sve_b_1215=0b1001 & sve_b_11=0 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & sve_imm_shift & Zd.T_tszh & Zn.T_tszh +{ + Zd.T_tszh = SVE_asr(Zd.T_tszh, Zn.T_tszh, sve_imm_shift:1); +} + +# asr_z_zw.xml: ASR (wide elements, unpredicated) variant SVE +# PATTERN x04208000/mask=xff20fc00 + +:asr Zd.T, Zn.T, Zm.D +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1215=0b1000 & sve_b_11=0 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Zm.D +{ + Zd.T = SVE_asr(Zd.T, Zn.T, Zm.D); +} + +# asrd_z_p_zi.xml: ASRD variant SVE +# PATTERN x04048000/mask=xff3fe000 + +:asrd Zd.T_tszh, Pg3_m, Zd.T_tszh_2, "#"^sve_imm_shift +is sve_b_2431=0b00000100 & sve_tszh_2223 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_tszl_0809 & sve_imm3_0507 & sve_zdn_0004 & sve_imm_shift & Zd.T_tszh & Zd.T_tszh_2 & Pg3_m +{ + Zd.T_tszh = SVE_asrd(Zd.T_tszh, Pg3_m, Zd.T_tszh_2, sve_imm_shift:1); +} + +# asrr_z_p_zz.xml: ASRR variant SVE +# PATTERN x04148000/mask=xff3fe000 + +:asrr Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_asrr(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# bic_and_z_zi.xml: BIC (immediate) variant SVE +# ALIASEDBY AND ., ., #(- - 1) if Never +# PATTERN x05800000/mask=xfffc0000 + +# SKIPPING bic_and_z_zi.xml because x05800000/mask=xfffc0000 has already been defined + +# bic_p_p_pp.xml: BIC, BICS (predicates) variant Flag setting +# PATTERN x25404010/mask=xfff0c210 + +:bics Pd.B, Pg_z, Pn.B, Pm.B +is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=1 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B +{ + Pd.B = SVE_bics(Pd.B, Pg_z, Pn.B, Pm.B); +} + +# bic_p_p_pp.xml: BIC, BICS (predicates) variant Not flag setting +# PATTERN x25004010/mask=xfff0c210 + +:bic Pd.B, Pg_z, Pn.B, Pm.B +is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=1 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B +{ + Pd.B = SVE_bic(Pd.B, Pg_z, Pn.B, Pm.B); +} + +# bic_z_p_zz.xml: BIC (vectors, predicated) variant SVE +# PATTERN x041b0000/mask=xff3fe000 + +:bic Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=1 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_bic(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# bic_z_zz.xml: BIC (vectors, unpredicated) variant SVE +# PATTERN x04e03000/mask=xffe0fc00 + +:bic Zd.D, Zn.D, Zm.D +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_zm_1620 & sve_b_1015=0b001100 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Zm.D +{ + Zd.D = SVE_bic(Zd.D, Zn.D, Zm.D); +} + +# brka_p_p_p.xml: BRKA, BRKAS variant Flag setting +# PATTERN x25504000/mask=xffffc210 + +:brkas Pd.B, Pg_z, Pn.B +is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1421=0b01000001 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B +{ + Pd.B = SVE_brkas(Pd.B, Pg_z, Pn.B); +} + +# brka_p_p_p.xml: BRKA, BRKAS variant Not flag setting +# PATTERN x25104000/mask=xffffc200 + +:brka Pd.B, Pg_zm, Pn.B +is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=0 & sve_b_1421=0b01000001 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_m_04 & sve_pd_0003 & Pg_zm & Pd.B & Pn.B +{ + Pd.B = SVE_brka(Pd.B, Pg_zm, Pn.B); +} + +# brkb_p_p_p.xml: BRKB, BRKBS variant Flag setting +# PATTERN x25d04000/mask=xffffc210 + +:brkbs Pd.B, Pg_z, Pn.B +is sve_b_2431=0b00100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1421=0b01000001 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B +{ + Pd.B = SVE_brkbs(Pd.B, Pg_z, Pn.B); +} + +# brkb_p_p_p.xml: BRKB, BRKBS variant Not flag setting +# PATTERN x25904000/mask=xffffc200 + +:brkb Pd.B, Pg_zm, Pn.B +is sve_b_2431=0b00100101 & sve_b_23=1 & sve_b_22=0 & sve_b_1421=0b01000001 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_m_04 & sve_pd_0003 & Pg_zm & Pd.B & Pn.B +{ + Pd.B = SVE_brkb(Pd.B, Pg_zm, Pn.B); +} + +# brkn_p_p_pp.xml: BRKN, BRKNS variant Flag setting +# PATTERN x25584000/mask=xffffc210 + +:brkns Pd.B, Pg_z, Pn.B, Pd.B_2 +is sve_b_2331=0b001001010 & sve_b_22=1 & sve_b_1421=0b01100001 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pdm_0003 & Pd.B & Pd.B_2 & Pg_z & Pn.B +{ + Pd.B = SVE_brkns(Pd.B, Pg_z, Pn.B, Pd.B_2); +} + +# brkn_p_p_pp.xml: BRKN, BRKNS variant Not flag setting +# PATTERN x25184000/mask=xffffc210 + +:brkn Pd.B, Pg_z, Pn.B, Pd.B_2 +is sve_b_2331=0b001001010 & sve_b_22=0 & sve_b_1421=0b01100001 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pdm_0003 & Pd.B & Pd.B_2 & Pg_z & Pn.B +{ + Pd.B = SVE_brkn(Pd.B, Pg_z, Pn.B, Pd.B_2); +} + +# brkpa_p_p_pp.xml: BRKPA, BRKPAS variant Flag setting +# PATTERN x2540c000/mask=xfff0c210 + +:brkpas Pd.B, Pg_z, Pn.B, Pm.B +is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b11 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B +{ + Pd.B = SVE_brkpas(Pd.B, Pg_z, Pn.B, Pm.B); +} + +# brkpa_p_p_pp.xml: BRKPA, BRKPAS variant Not flag setting +# PATTERN x2500c000/mask=xfff0c210 + +:brkpa Pd.B, Pg_z, Pn.B, Pm.B +is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b11 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B +{ + Pd.B = SVE_brkpa(Pd.B, Pg_z, Pn.B, Pm.B); +} + +# brkpb_p_p_pp.xml: BRKPB, BRKPBS variant Flag setting +# PATTERN x2540c010/mask=xfff0c210 + +:brkpbs Pd.B, Pg_z, Pn.B, Pm.B +is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b11 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=1 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B +{ + Pd.B = SVE_brkpbs(Pd.B, Pg_z, Pn.B, Pm.B); +} + +# brkpb_p_p_pp.xml: BRKPB, BRKPBS variant Not flag setting +# PATTERN x2500c010/mask=xfff0c210 + +:brkpb Pd.B, Pg_z, Pn.B, Pm.B +is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b11 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=1 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B +{ + Pd.B = SVE_brkpb(Pd.B, Pg_z, Pn.B, Pm.B); +} + +# clasta_r_p_z.xml: CLASTA (scalar) variant SVE +# PATTERN x0530a000/mask=xff3fe000 + +:clasta Rd_GPR64, Pg3, Rd_GPR64_2, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1721=0b11000 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zm_0509 & sve_rdn_0004 & Zn.T & Rd_GPR64 & Rd_GPR64_2 & Pg3 +{ + Rd_GPR64 = SVE_clasta(Rd_GPR64, Pg3, Rd_GPR64_2, Zn.T); +} + +# clasta_r_p_z.xml: CLASTA (scalar) variant SVE +# PATTERN x0530a000/mask=xff3fe000 + +:clasta Rd_GPR32, Pg3, Rd_GPR32_2, Zn.T +is sve_b_2431=0b00000101 & (b_23=0 | b_22=0) & sve_b_1721=0b11000 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zm_0509 & sve_rdn_0004 & Zn.T & Rd_GPR32 & Rd_GPR32_2 & Pg3 +{ + Rd_GPR32 = SVE_clasta(Rd_GPR32, Pg3, Rd_GPR32_2, Zn.T); +} + +# clasta_v_p_z.xml: CLASTA (SIMD&FP scalar) variant SVE +# PATTERN x052a8000/mask=xff3fe000 + +:clasta Rd_FPR8, Pg3, Rd_FPR8_2, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223=0b00 & sve_b_1721=0b10101 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR8 & Rd_FPR8_2 & Pg3 +{ + Rd_FPR8 = SVE_clasta(Rd_FPR8, Pg3, Rd_FPR8_2, Zn.T); +} + +# clasta_v_p_z.xml: CLASTA (SIMD&FP scalar) variant SVE +# PATTERN x052a8000/mask=xff3fe000 + +:clasta Rd_FPR32, Pg3, Rd_FPR32_2, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223=0b10 & sve_b_1721=0b10101 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR32 & Rd_FPR32_2 & Pg3 +{ + Rd_FPR32 = SVE_clasta(Rd_FPR32, Pg3, Rd_FPR32_2, Zn.T); +} + +# clasta_v_p_z.xml: CLASTA (SIMD&FP scalar) variant SVE +# PATTERN x052a8000/mask=xff3fe000 + +:clasta Rd_FPR16, Pg3, Rd_FPR16_2, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223=0b01 & sve_b_1721=0b10101 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR16 & Rd_FPR16_2 & Pg3 +{ + Rd_FPR16 = SVE_clasta(Rd_FPR16, Pg3, Rd_FPR16_2, Zn.T); +} + +# clasta_v_p_z.xml: CLASTA (SIMD&FP scalar) variant SVE +# PATTERN x052a8000/mask=xff3fe000 + +:clasta Rd_FPR64, Pg3, Rd_FPR64_2, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1721=0b10101 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR64 & Rd_FPR64_2 & Pg3 +{ + Rd_FPR64 = SVE_clasta(Rd_FPR64, Pg3, Rd_FPR64_2, Zn.T); +} + +# clasta_z_p_zz.xml: CLASTA (vectors) variant SVE +# PATTERN x05288000/mask=xff3fe000 + +:clasta Zd.T, Pg3, Zd.T_2, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1721=0b10100 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3 +{ + Zd.T = SVE_clasta(Zd.T, Pg3, Zd.T_2, Zn.T); +} + +# clastb_r_p_z.xml: CLASTB (scalar) variant SVE +# PATTERN x0531a000/mask=xff3fe000 + +:clastb Rd_GPR64, Pg3, Rd_GPR64_2, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1721=0b11000 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zm_0509 & sve_rdn_0004 & Zn.T & Rd_GPR64 & Rd_GPR64_2 & Pg3 +{ + Rd_GPR64 = SVE_clastb(Rd_GPR64, Pg3, Rd_GPR64_2, Zn.T); +} + +# clastb_r_p_z.xml: CLASTB (scalar) variant SVE +# PATTERN x0531a000/mask=xff3fe000 + +:clastb Rd_GPR32, Pg3, Rd_GPR32_2, Zn.T +is sve_b_2431=0b00000101 & (b_23=0 | b_22=0) & sve_b_1721=0b11000 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zm_0509 & sve_rdn_0004 & Zn.T & Rd_GPR32 & Rd_GPR32_2 & Pg3 +{ + Rd_GPR32 = SVE_clastb(Rd_GPR32, Pg3, Rd_GPR32_2, Zn.T); +} + +# clastb_v_p_z.xml: CLASTB (SIMD&FP scalar) variant SVE +# PATTERN x052b8000/mask=xff3fe000 + +:clastb Rd_FPR8, Pg3, Rd_FPR8_2, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223=0b00 & sve_b_1721=0b10101 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR8 & Rd_FPR8_2 & Pg3 +{ + Rd_FPR8 = SVE_clastb(Rd_FPR8, Pg3, Rd_FPR8_2, Zn.T); +} + +# clastb_v_p_z.xml: CLASTB (SIMD&FP scalar) variant SVE +# PATTERN x052b8000/mask=xff3fe000 + +:clastb Rd_FPR32, Pg3, Rd_FPR32_2, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223=0b10 & sve_b_1721=0b10101 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR32 & Rd_FPR32_2 & Pg3 +{ + Rd_FPR32 = SVE_clastb(Rd_FPR32, Pg3, Rd_FPR32_2, Zn.T); +} + +# clastb_v_p_z.xml: CLASTB (SIMD&FP scalar) variant SVE +# PATTERN x052b8000/mask=xff3fe000 + +:clastb Rd_FPR16, Pg3, Rd_FPR16_2, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223=0b01 & sve_b_1721=0b10101 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR16 & Rd_FPR16_2 & Pg3 +{ + Rd_FPR16 = SVE_clastb(Rd_FPR16, Pg3, Rd_FPR16_2, Zn.T); +} + +# clastb_v_p_z.xml: CLASTB (SIMD&FP scalar) variant SVE +# PATTERN x052b8000/mask=xff3fe000 + +:clastb Rd_FPR64, Pg3, Rd_FPR64_2, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1721=0b10101 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR64 & Rd_FPR64_2 & Pg3 +{ + Rd_FPR64 = SVE_clastb(Rd_FPR64, Pg3, Rd_FPR64_2, Zn.T); +} + +# clastb_z_p_zz.xml: CLASTB (vectors) variant SVE +# PATTERN x05298000/mask=xff3fe000 + +:clastb Zd.T, Pg3, Zd.T_2, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1721=0b10100 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3 +{ + Zd.T = SVE_clastb(Zd.T, Pg3, Zd.T_2, Zn.T); +} + +# cls_z_p_z.xml: CLS variant SVE +# PATTERN x0418a000/mask=xff3fe000 + +:cls Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_cls(Zd.T, Pg3_m, Zn.T); +} + +# clz_z_p_z.xml: CLZ variant SVE +# PATTERN x0419a000/mask=xff3fe000 + +:clz Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_clz(Zd.T, Pg3_m, Zn.T); +} + +# cmpeq_p_p_zi.xml: CMP (immediate) variant Equal +# PATTERN x25008000/mask=xff20e010 + +:cmpeq Pd.T, Pg3_z, Zn.T, "#"^sve_imm5s_1620 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=0 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & sve_imm5s_1620 +{ + Pd.T = SVE_cmpeq(Pd.T, Pg3_z, Zn.T, sve_imm5s_1620:1); +} + +# cmpeq_p_p_zi.xml: CMP (immediate) variant Greater than +# PATTERN x25000010/mask=xff20e010 + +:cmpgt Pd.T, Pg3_z, Zn.T, "#"^sve_imm5s_1620 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=0 & sve_imm5_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & sve_imm5s_1620 +{ + Pd.T = SVE_cmpgt(Pd.T, Pg3_z, Zn.T, sve_imm5s_1620:1); +} + +# cmpeq_p_p_zi.xml: CMP (immediate) variant Greater than or equal +# PATTERN x25000000/mask=xff20e010 + +:cmpge Pd.T, Pg3_z, Zn.T, "#"^sve_imm5s_1620 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=0 & sve_imm5_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & sve_imm5s_1620 +{ + Pd.T = SVE_cmpge(Pd.T, Pg3_z, Zn.T, sve_imm5s_1620:1); +} + +# cmpeq_p_p_zi.xml: CMP (immediate) variant Higher +# PATTERN x24200010/mask=xff202010 + +:cmphi Pd.T, Pg3_z, Zn.T, "#"^sve_imm7_1420 +is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=1 & sve_imm7_1420 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z +{ + Pd.T = SVE_cmphi(Pd.T, Pg3_z, Zn.T, sve_imm7_1420:1); +} + +# cmpeq_p_p_zi.xml: CMP (immediate) variant Higher or same +# PATTERN x24200000/mask=xff202010 + +:cmphs Pd.T, Pg3_z, Zn.T, "#"^sve_imm7_1420 +is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=1 & sve_imm7_1420 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z +{ + Pd.T = SVE_cmphs(Pd.T, Pg3_z, Zn.T, sve_imm7_1420:1); +} + +# cmpeq_p_p_zi.xml: CMP (immediate) variant Less than +# PATTERN x25002000/mask=xff20e010 + +:cmplt Pd.T, Pg3_z, Zn.T, "#"^sve_imm5s_1620 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=0 & sve_imm5_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & sve_imm5s_1620 +{ + Pd.T = SVE_cmplt(Pd.T, Pg3_z, Zn.T, sve_imm5s_1620:1); +} + +# cmpeq_p_p_zi.xml: CMP (immediate) variant Less than or equal +# PATTERN x25002010/mask=xff20e010 + +:cmple Pd.T, Pg3_z, Zn.T, "#"^sve_imm5s_1620 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=0 & sve_imm5_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & sve_imm5s_1620 +{ + Pd.T = SVE_cmple(Pd.T, Pg3_z, Zn.T, sve_imm5s_1620:1); +} + +# cmpeq_p_p_zi.xml: CMP (immediate) variant Lower +# PATTERN x24202000/mask=xff202010 + +:cmplo Pd.T, Pg3_z, Zn.T, "#"^sve_imm7_1420 +is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=1 & sve_imm7_1420 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z +{ + Pd.T = SVE_cmplo(Pd.T, Pg3_z, Zn.T, sve_imm7_1420:1); +} + +# cmpeq_p_p_zi.xml: CMP (immediate) variant Lower or same +# PATTERN x24202010/mask=xff202010 + +:cmpls Pd.T, Pg3_z, Zn.T, "#"^sve_imm7_1420 +is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=1 & sve_imm7_1420 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z +{ + Pd.T = SVE_cmpls(Pd.T, Pg3_z, Zn.T, sve_imm7_1420:1); +} + +# cmpeq_p_p_zi.xml: CMP (immediate) variant Not equal +# PATTERN x25008010/mask=xff20e010 + +:cmpne Pd.T, Pg3_z, Zn.T, "#"^sve_imm5s_1620 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=0 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & sve_imm5s_1620 +{ + Pd.T = SVE_cmpne(Pd.T, Pg3_z, Zn.T, sve_imm5s_1620:1); +} + +# cmpeq_p_p_zw.xml: CMP (wide elements) variant Equal +# PATTERN x24002000/mask=xff20e010 + +:cmpeq Pd.T, Pg3_z, Zn.T, Zm.D +is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D +{ + Pd.T = SVE_cmpeq(Pd.T, Pg3_z, Zn.T, Zm.D); +} + +# cmpeq_p_p_zw.xml: CMP (wide elements) variant Greater than +# PATTERN x24004010/mask=xff20e010 + +:cmpgt Pd.T, Pg3_z, Zn.T, Zm.D +is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D +{ + Pd.T = SVE_cmpgt(Pd.T, Pg3_z, Zn.T, Zm.D); +} + +# cmpeq_p_p_zw.xml: CMP (wide elements) variant Greater than or equal +# PATTERN x24004000/mask=xff20e010 + +:cmpge Pd.T, Pg3_z, Zn.T, Zm.D +is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D +{ + Pd.T = SVE_cmpge(Pd.T, Pg3_z, Zn.T, Zm.D); +} + +# cmpeq_p_p_zw.xml: CMP (wide elements) variant Higher +# PATTERN x2400c010/mask=xff20e010 + +:cmphi Pd.T, Pg3_z, Zn.T, Zm.D +is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D +{ + Pd.T = SVE_cmphi(Pd.T, Pg3_z, Zn.T, Zm.D); +} + +# cmpeq_p_p_zw.xml: CMP (wide elements) variant Higher or same +# PATTERN x2400c000/mask=xff20e010 + +:cmphs Pd.T, Pg3_z, Zn.T, Zm.D +is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D +{ + Pd.T = SVE_cmphs(Pd.T, Pg3_z, Zn.T, Zm.D); +} + +# cmpeq_p_p_zw.xml: CMP (wide elements) variant Less than +# PATTERN x24006000/mask=xff20e010 + +:cmplt Pd.T, Pg3_z, Zn.T, Zm.D +is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D +{ + Pd.T = SVE_cmplt(Pd.T, Pg3_z, Zn.T, Zm.D); +} + +# cmpeq_p_p_zw.xml: CMP (wide elements) variant Less than or equal +# PATTERN x24006010/mask=xff20e010 + +:cmple Pd.T, Pg3_z, Zn.T, Zm.D +is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D +{ + Pd.T = SVE_cmple(Pd.T, Pg3_z, Zn.T, Zm.D); +} + +# cmpeq_p_p_zw.xml: CMP (wide elements) variant Lower +# PATTERN x2400e000/mask=xff20e010 + +:cmplo Pd.T, Pg3_z, Zn.T, Zm.D +is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D +{ + Pd.T = SVE_cmplo(Pd.T, Pg3_z, Zn.T, Zm.D); +} + +# cmpeq_p_p_zw.xml: CMP (wide elements) variant Lower or same +# PATTERN x2400e010/mask=xff20e010 + +:cmpls Pd.T, Pg3_z, Zn.T, Zm.D +is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D +{ + Pd.T = SVE_cmpls(Pd.T, Pg3_z, Zn.T, Zm.D); +} + +# cmpeq_p_p_zw.xml: CMP (wide elements) variant Not equal +# PATTERN x24002010/mask=xff20e010 + +:cmpne Pd.T, Pg3_z, Zn.T, Zm.D +is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D +{ + Pd.T = SVE_cmpne(Pd.T, Pg3_z, Zn.T, Zm.D); +} + +# cmpeq_p_p_zz.xml: CMP (vectors) variant Equal +# PATTERN x2400a000/mask=xff20e010 + +:cmpeq Pd.T, Pg3_z, Zn.T, Zm.T +is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z +{ + Pd.T = SVE_cmpeq(Pd.T, Pg3_z, Zn.T, Zm.T); +} + +# cmpeq_p_p_zz.xml: CMP (vectors) variant Greater than +# PATTERN x24008010/mask=xff20e010 + +:cmpgt Pd.T, Pg3_z, Zn.T, Zm.T +is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z +{ + Pd.T = SVE_cmpgt(Pd.T, Pg3_z, Zn.T, Zm.T); +} + +# cmpeq_p_p_zz.xml: CMP (vectors) variant Greater than or equal +# PATTERN x24008000/mask=xff20e010 + +:cmpge Pd.T, Pg3_z, Zn.T, Zm.T +is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z +{ + Pd.T = SVE_cmpge(Pd.T, Pg3_z, Zn.T, Zm.T); +} + +# cmpeq_p_p_zz.xml: CMP (vectors) variant Higher +# PATTERN x24000010/mask=xff20e010 + +:cmphi Pd.T, Pg3_z, Zn.T, Zm.T +is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z +{ + Pd.T = SVE_cmphi(Pd.T, Pg3_z, Zn.T, Zm.T); +} + +# cmpeq_p_p_zz.xml: CMP (vectors) variant Higher or same +# PATTERN x24000000/mask=xff20e010 + +:cmphs Pd.T, Pg3_z, Zn.T, Zm.T +is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z +{ + Pd.T = SVE_cmphs(Pd.T, Pg3_z, Zn.T, Zm.T); +} + +# cmpeq_p_p_zz.xml: CMP (vectors) variant Not equal +# PATTERN x2400a010/mask=xff20e010 + +:cmpne Pd.T, Pg3_z, Zn.T, Zm.T +is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z +{ + Pd.T = SVE_cmpne(Pd.T, Pg3_z, Zn.T, Zm.T); +} + +# cmple_cmpeq_p_p_zz.xml: CMPLE (vectors) variant Greater than or equal +# ALIASEDBY CMPGE ., /Z, ., . if Never +# PATTERN x24008000/mask=xff20e010 + +# SKIPPING cmple_cmpeq_p_p_zz.xml because x24008000/mask=xff20e010 has already been defined + +# cmplo_cmpeq_p_p_zz.xml: CMPLO (vectors) variant Higher +# ALIASEDBY CMPHI ., /Z, ., . if Never +# PATTERN x24000010/mask=xff20e010 + +# SKIPPING cmplo_cmpeq_p_p_zz.xml because x24000010/mask=xff20e010 has already been defined + +# cmpls_cmpeq_p_p_zz.xml: CMPLS (vectors) variant Higher or same +# ALIASEDBY CMPHS ., /Z, ., . if Never +# PATTERN x24000000/mask=xff20e010 + +# SKIPPING cmpls_cmpeq_p_p_zz.xml because x24000000/mask=xff20e010 has already been defined + +# cmplt_cmpeq_p_p_zz.xml: CMPLT (vectors) variant Greater than +# ALIASEDBY CMPGT ., /Z, ., . if Never +# PATTERN x24008010/mask=xff20e010 + +# SKIPPING cmplt_cmpeq_p_p_zz.xml because x24008010/mask=xff20e010 has already been defined + +# cnot_z_p_z.xml: CNOT variant SVE +# PATTERN x041ba000/mask=xff3fe000 + +:cnot Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_cnot(Zd.T, Pg3_m, Zn.T); +} + +# cnt_z_p_z.xml: CNT variant SVE +# PATTERN x041aa000/mask=xff3fe000 + +:cnt Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_cnt(Zd.T, Pg3_m, Zn.T); +} + +# cntb_r_s.xml: CNTB, CNTD, CNTH, CNTW variant Byte +# PATTERN x0420e000/mask=xfff0fc00 + +:cntb Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=0 & sve_pattern_0509 & sve_rd_0004 & sve_pattern & sve_imm4_1_1to16 & Rd_GPR64 & sve_mul_pattern +{ + Rd_GPR64 = SVE_cntb(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# cntb_r_s.xml: CNTB, CNTD, CNTH, CNTW variant Doubleword +# PATTERN x04e0e000/mask=xfff0fc00 + +:cntd Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=0 & sve_pattern_0509 & sve_rd_0004 & sve_pattern & sve_imm4_1_1to16 & Rd_GPR64 & sve_mul_pattern +{ + Rd_GPR64 = SVE_cntd(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# cntb_r_s.xml: CNTB, CNTD, CNTH, CNTW variant Halfword +# PATTERN x0460e000/mask=xfff0fc00 + +:cnth Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=0 & sve_pattern_0509 & sve_rd_0004 & sve_pattern & sve_imm4_1_1to16 & Rd_GPR64 & sve_mul_pattern +{ + Rd_GPR64 = SVE_cnth(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# cntb_r_s.xml: CNTB, CNTD, CNTH, CNTW variant Word +# PATTERN x04a0e000/mask=xfff0fc00 + +:cntw Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=0 & sve_pattern_0509 & sve_rd_0004 & sve_pattern & sve_imm4_1_1to16 & Rd_GPR64 & sve_mul_pattern +{ + Rd_GPR64 = SVE_cntw(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# cntp_r_p_p.xml: CNTP variant SVE +# PATTERN x25208000/mask=xff3fc200 + +:cntp Rd_GPR64, Pg, Pn.T +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b100 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1415=0b10 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_rd_0004 & Pn.T & Rd_GPR64 & Pg +{ + Rd_GPR64 = SVE_cntp(Rd_GPR64, Pn.T, Pg); +} + +# compact_z_p_z.xml: COMPACT variant SVE +# PATTERN x05a18000/mask=xffbfe000 + +:compact Zd.T_sz, Pg3, Zn.T_sz +is sve_b_2331=0b000001011 & sve_sz_22 & sve_b_1321=0b100001100 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T_sz & Zn.T_sz & Pg3 +{ + Zd.T_sz = SVE_compact(Zd.T_sz, Pg3, Zn.T_sz); +} + +# cpy_z_p_i.xml: CPY (immediate) variant SVE +# PATTERN x05100000/mask=xff308000 + +:cpy Zd.T, Pm_zm, sve_shf8_1_m128to127 +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_2021=0b01 & sve_pg_1619 & sve_b_15=0 & sve_m_14 & sve_sh_13 & sve_imm8_0512 & sve_zd_0004 & sve_shift_13 & Pm_zm & Zd.T & sve_imm8_1_m128to127 & sve_shf8_1_m128to127 +{ + Zd.T = SVE_cpy(Zd.T, Pm_zm, sve_shf8_1_m128to127, sve_shift_13:1); +} + +# cpy_z_p_r.xml: CPY (scalar) variant SVE +# PATTERN x0528a000/mask=xff3fe000 + +:cpy Zd.T, Pg3_m, Rn_GPR64xsp +is sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1321=0b101000101 & sve_pg_1012 & sve_rn_0509 & sve_zd_0004 & Rn_GPR64xsp & Zd.T & Pg3_m +{ + Zd.T = SVE_cpy(Zd.T, Pg3_m, Rn_GPR64xsp); +} + +# cpy_z_p_r.xml: CPY (scalar) variant SVE +# PATTERN x0528a000/mask=xff3fe000 + +:cpy Zd.T, Pg3_m, Rn_GPR32xsp +is sve_b_2431=0b00000101 & (b_23=0 | b_22=0) & sve_b_1321=0b101000101 & sve_pg_1012 & sve_rn_0509 & sve_zd_0004 & Rn_GPR32xsp & Zd.T & Pg3_m +{ + Zd.T = SVE_cpy(Zd.T, Pg3_m, Rn_GPR32xsp); +} + +# cpy_z_p_v.xml: CPY (SIMD&FP scalar) variant SVE +# PATTERN x05208000/mask=xff3fe000 + +:cpy Zd.T, Pg3_m, Rn_FPR8 +is sve_b_2431=0b00000101 & sve_size_2223=0b00 & sve_b_1321=0b100000100 & sve_pg_1012 & sve_vn_0509 & sve_zd_0004 & Zd.T & Rn_FPR8 & Pg3_m +{ + Zd.T = SVE_cpy(Zd.T, Pg3_m, Rn_FPR8); +} + +# cpy_z_p_v.xml: CPY (SIMD&FP scalar) variant SVE +# PATTERN x05208000/mask=xff3fe000 + +:cpy Zd.T, Pg3_m, Rn_FPR32 +is sve_b_2431=0b00000101 & sve_size_2223=0b10 & sve_b_1321=0b100000100 & sve_pg_1012 & sve_vn_0509 & sve_zd_0004 & Zd.T & Rn_FPR32 & Pg3_m +{ + Zd.T = SVE_cpy(Zd.T, Pg3_m, Rn_FPR32); +} + +# cpy_z_p_v.xml: CPY (SIMD&FP scalar) variant SVE +# PATTERN x05208000/mask=xff3fe000 + +:cpy Zd.T, Pg3_m, Rn_FPR16 +is sve_b_2431=0b00000101 & sve_size_2223=0b01 & sve_b_1321=0b100000100 & sve_pg_1012 & sve_vn_0509 & sve_zd_0004 & Zd.T & Rn_FPR16 & Pg3_m +{ + Zd.T = SVE_cpy(Zd.T, Pg3_m, Rn_FPR16); +} + +# cpy_z_p_v.xml: CPY (SIMD&FP scalar) variant SVE +# PATTERN x05208000/mask=xff3fe000 + +:cpy Zd.T, Pg3_m, Rn_FPR64 +is sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1321=0b100000100 & sve_pg_1012 & sve_vn_0509 & sve_zd_0004 & Zd.T & Rn_FPR64 & Pg3_m +{ + Zd.T = SVE_cpy(Zd.T, Pg3_m, Rn_FPR64); +} + +# ctermeq_rr.xml: CTERMEQ, CTERMNE variant Equal +# PATTERN x25a02000/mask=xffa0fc1f + +:ctermeq Rn_GPR64, Rm_GPR64 +is sve_b_3031=0b00 & sve_b_2429=0b100101 & sve_b_23=1 & sve_sz_22=1 & sve_b_21=1 & sve_rm_1620 & sve_b_1015=0b001000 & sve_rn_0509 & sve_b_04=0 & sve_b_03=0 & sve_b_02=0 & sve_b_0001=0b00 & Rn_GPR64 & Rm_GPR64 +{ + SVE_ctermeq(Rn_GPR64, Rm_GPR64); +} + +# ctermeq_rr.xml: CTERMEQ, CTERMNE variant Equal +# PATTERN x25a02000/mask=xffa0fc1f + +:ctermeq Rn_GPR32, Rm_GPR32 +is sve_b_3031=0b00 & sve_b_2429=0b100101 & sve_b_23=1 & sve_sz_22=0 & sve_b_21=1 & sve_rm_1620 & sve_b_1015=0b001000 & sve_rn_0509 & sve_b_04=0 & sve_b_03=0 & sve_b_02=0 & sve_b_0001=0b00 & Rn_GPR32 & Rm_GPR32 +{ + SVE_ctermeq(Rn_GPR32, Rm_GPR32); +} + +# ctermeq_rr.xml: CTERMEQ, CTERMNE variant Not equal +# PATTERN x25a02010/mask=xffa0fc1f + +:ctermne Rn_GPR64, Rm_GPR64 +is sve_b_3031=0b00 & sve_b_2429=0b100101 & sve_b_23=1 & sve_sz_22=1 & sve_b_21=1 & sve_rm_1620 & sve_b_1015=0b001000 & sve_rn_0509 & sve_b_04=1 & sve_b_03=0 & sve_b_02=0 & sve_b_0001=0b00 & Rn_GPR64 & Rm_GPR64 +{ + SVE_ctermne(Rn_GPR64, Rm_GPR64); +} + +# ctermeq_rr.xml: CTERMEQ, CTERMNE variant Not equal +# PATTERN x25a02010/mask=xffa0fc1f + +:ctermne Rn_GPR32, Rm_GPR32 +is sve_b_3031=0b00 & sve_b_2429=0b100101 & sve_b_23=1 & sve_sz_22=0 & sve_b_21=1 & sve_rm_1620 & sve_b_1015=0b001000 & sve_rn_0509 & sve_b_04=1 & sve_b_03=0 & sve_b_02=0 & sve_b_0001=0b00 & Rn_GPR32 & Rm_GPR32 +{ + SVE_ctermne(Rn_GPR32, Rm_GPR32); +} + +# decb_r_rs.xml: DECB, DECD, DECH, DECW (scalar) variant Byte +# PATTERN x0430e400/mask=xfff0fc00 + +:decb Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_decb(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# decb_r_rs.xml: DECB, DECD, DECH, DECW (scalar) variant Doubleword +# PATTERN x04f0e400/mask=xfff0fc00 + +:decd Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_decd(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# decb_r_rs.xml: DECB, DECD, DECH, DECW (scalar) variant Halfword +# PATTERN x0470e400/mask=xfff0fc00 + +:dech Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_dech(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# decb_r_rs.xml: DECB, DECD, DECH, DECW (scalar) variant Word +# PATTERN x04b0e400/mask=xfff0fc00 + +:decw Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_decw(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# decd_z_zs.xml: DECD, DECH, DECW (vector) variant Doubleword +# PATTERN x04f0c400/mask=xfff0fc00 + +:decd Zd.D^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11000 & sve_b_10=1 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.D & sve_imm4_1_1to16 & sve_mul_pattern +{ + Zd.D = SVE_decd(Zd.D, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# decd_z_zs.xml: DECD, DECH, DECW (vector) variant Halfword +# PATTERN x0470c400/mask=xfff0fc00 + +:dech Zd.H^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11000 & sve_b_10=1 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.H & sve_imm4_1_1to16 & sve_mul_pattern +{ + Zd.H = SVE_dech(Zd.H, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# decd_z_zs.xml: DECD, DECH, DECW (vector) variant Word +# PATTERN x04b0c400/mask=xfff0fc00 + +:decw Zd.S^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11000 & sve_b_10=1 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.S & sve_imm4_1_1to16 & sve_mul_pattern +{ + Zd.S = SVE_decw(Zd.S, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# decp_r_p_r.xml: DECP (scalar) variant SVE +# PATTERN x252d8800/mask=xff3ffe00 + +:decp Rd_GPR64, Pn.T +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1011 & sve_b_17=0 & sve_b_16=1 & sve_b_1115=0b10001 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_rdn_0004 & Pn.T & Rd_GPR64 +{ + Rd_GPR64 = SVE_decp(Rd_GPR64, Pn.T); +} + +# decp_z_p_z.xml: DECP (vector) variant SVE +# PATTERN x252d8000/mask=xff3ffe00 + +:decp Zd.T, Pn +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1011 & sve_b_17=0 & sve_b_16=1 & sve_b_1115=0b10000 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_zdn_0004 & Zd.T & Pn +{ + Zd.T = SVE_decp(Zd.T, Pn); +} + +# dup_z_i.xml: DUP (immediate) variant SVE +# PATTERN x2538c000/mask=xff3fc000 + +:dup Zd.T, sve_shf8_1_m128to127 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b111 & sve_b_18=0 & sve_b_17=0 & sve_b_1416=0b011 & sve_sh_13 & sve_imm8_0512 & sve_zd_0004 & sve_shift_13 & Zd.T & sve_imm8_1_m128to127 & sve_shf8_1_m128to127 +{ + Zd.T = SVE_dup(Zd.T, sve_shf8_1_m128to127, sve_shift_13:1); +} + +# dup_z_r.xml: DUP (scalar) variant SVE +# PATTERN x05203800/mask=xff3ffc00 + +:dup Zd.T, Rn_GPR64xsp +is sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1021=0b100000001110 & sve_rn_0509 & sve_zd_0004 & Rn_GPR64xsp & Zd.T +{ + Zd.T = SVE_dup(Zd.T, Rn_GPR64xsp); +} + +# dup_z_r.xml: DUP (scalar) variant SVE +# PATTERN x05203800/mask=xff3ffc00 + +:dup Zd.T, Rn_GPR32xsp +is sve_b_2431=0b00000101 & (b_23=0 | b_22=0) & sve_b_1021=0b100000001110 & sve_rn_0509 & sve_zd_0004 & Rn_GPR32xsp & Zd.T +{ + Zd.T = SVE_dup(Zd.T, Rn_GPR32xsp); +} + +# dup_z_zi.xml: DUP (indexed) variant SVE +# PATTERN x05202000/mask=xff20fc00 + +:dup Zd.T_tsz, Zn.T_tsz[sve_imm2_tsz] +is sve_b_2431=0b00000101 & sve_imm2_2223 & sve_b_21=1 & sve_tsz_1620 & sve_b_1015=0b001000 & sve_zn_0509 & sve_zd_0004 & Zd.T_tsz & Zn.T_tsz & sve_imm2_tsz +{ + Zd.T_tsz = SVE_dup(Zd.T_tsz, Zn.T_tsz, sve_imm2_tsz:1); +} + +# dupm_z_i.xml: DUPM variant SVE +# PATTERN x05c00000/mask=xfffc0000 + +:dupm Zd.T_imm13, "#"^sve_decode_bit_mask +is sve_b_1831=0b00000101110000 & sve_imm13_0517 & sve_zd_0004 & sve_decode_bit_mask & Zd.T_imm13 +{ + Zd.T_imm13 = SVE_dupm(Zd.T_imm13, sve_decode_bit_mask:1); +} + +# eon_eor_z_zi.xml: EON variant SVE +# ALIASEDBY EOR ., ., #(- - 1) if Never +# PATTERN x05400000/mask=xfffc0000 + +:eon Zd.T_imm13, Zd.T_imm13_2, "#"^sve_decode_bit_mask +is sve_b_2431=0b00000101 & sve_b_23=0 & sve_b_22=1 & sve_b_1821=0b0000 & sve_imm13_0517 & sve_zdn_0004 & sve_decode_bit_mask & Zd.T_imm13 & Zd.T_imm13_2 +{ + Zd.T_imm13 = SVE_eon(Zd.T_imm13, Zd.T_imm13_2, sve_decode_bit_mask:1); +} + +# eor_p_p_pp.xml: EOR, EORS (predicates) variant Flag setting +# PATTERN x25404200/mask=xfff0c210 + +:eors Pd.B, Pg_z, Pn.B, Pm.B +is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=1 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B +{ + Pd.B = SVE_eors(Pd.B, Pg_z, Pn.B, Pm.B); +} + +# eor_p_p_pp.xml: EOR, EORS (predicates) variant Not flag setting +# PATTERN x25004200/mask=xfff0c210 + +:eor Pd.B, Pg_z, Pn.B, Pm.B +is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=1 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B +{ + Pd.B = SVE_eor(Pd.B, Pg_z, Pn.B, Pm.B); +} + +# eor_z_p_zz.xml: EOR (vectors, predicated) variant SVE +# PATTERN x04190000/mask=xff3fe000 + +:eor Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_eor(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# eor_z_zi.xml: EOR (immediate) variant SVE +# PATTERN x05400000/mask=xfffc0000 + +# SKIPPING eor_z_zi.xml because x05400000/mask=xfffc0000 has already been defined + +# eor_z_zz.xml: EOR (vectors, unpredicated) variant SVE +# PATTERN x04a03000/mask=xffe0fc00 + +:eor Zd.D, Zn.D, Zm.D +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_zm_1620 & sve_b_1015=0b001100 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Zm.D +{ + Zd.D = SVE_eor(Zd.D, Zn.D, Zm.D); +} + +# eorv_r_p_z.xml: EORV variant SVE +# PATTERN x04192000/mask=xff3fe000 + +:eorv Rd_FPR8, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b00 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3 +{ + Rd_FPR8 = SVE_eorv(Rd_FPR8, Pg3, Zn.T); +} + +# eorv_r_p_z.xml: EORV variant SVE +# PATTERN x04192000/mask=xff3fe000 + +:eorv Rd_FPR32, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b10 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3 +{ + Rd_FPR32 = SVE_eorv(Rd_FPR32, Pg3, Zn.T); +} + +# eorv_r_p_z.xml: EORV variant SVE +# PATTERN x04192000/mask=xff3fe000 + +:eorv Rd_FPR16, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b01 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3 +{ + Rd_FPR16 = SVE_eorv(Rd_FPR16, Pg3, Zn.T); +} + +# eorv_r_p_z.xml: EORV variant SVE +# PATTERN x04192000/mask=xff3fe000 + +:eorv Rd_FPR64, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b11 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3 +{ + Rd_FPR64 = SVE_eorv(Rd_FPR64, Pg3, Zn.T); +} + +# ext_z_zi.xml: EXT variant SVE +# PATTERN x05200000/mask=xffe0e000 + +:ext Zd.B, Zd.B_2, Zn.B, "#"^sve_imm8_2_0to255 +is sve_b_2131=0b00000101001 & sve_imm8h_1620 & sve_b_1315=0b000 & sve_imm8l_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.B & Zd.B_2 & Zn.B & sve_imm8_2_0to255 +{ + Zd.B = SVE_ext(Zd.B, Zd.B_2, Zn.B, sve_imm8_2_0to255:1); +} + +# fabd_z_p_zz.xml: FABD variant SVE +# PATTERN x65088000/mask=xff3fe000 + +:fabd Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b100 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_fabd(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# fabs_z_p_z.xml: FABS variant SVE +# PATTERN x041ca000/mask=xff3fe000 + +:fabs Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_fabs(Zd.T, Pg3_m, Zn.T); +} + +# facge_p_p_zz.xml: FAC variant Greater than +# PATTERN x6500e010/mask=xff20e010 + +:facgt Pd.T, Pg3_z, Zn.T, Zm.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z +{ + Pd.T = SVE_facgt(Pd.T, Pg3_z, Zn.T, Zm.T); +} + +# facge_p_p_zz.xml: FAC variant Greater than or equal +# PATTERN x6500c010/mask=xff20e010 + +:facge Pd.T, Pg3_z, Zn.T, Zm.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z +{ + Pd.T = SVE_facge(Pd.T, Pg3_z, Zn.T, Zm.T); +} + +# facle_facge_p_p_zz.xml: FACLE variant Greater than or equal +# ALIASEDBY FACGE ., /Z, ., . if Never +# PATTERN x6500c010/mask=xff20e010 + +# SKIPPING facle_facge_p_p_zz.xml because x6500c010/mask=xff20e010 has already been defined + +# faclt_facge_p_p_zz.xml: FACLT variant Greater than +# ALIASEDBY FACGT ., /Z, ., . if Never +# PATTERN x6500e010/mask=xff20e010 + +# SKIPPING faclt_facge_p_p_zz.xml because x6500e010/mask=xff20e010 has already been defined + +# fadd_z_p_zs.xml: FADD (immediate) variant SVE +# PATTERN x65188000/mask=xff3fe3c0 + +:fadd Zd.T, Pg3_m, Zd.T_2, sve_float_0510 +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_b_0609=0b0000 & sve_i1_05 & sve_zdn_0004 & sve_float_0510 & Zd.T & Zd.T_2 & Pg3_m +{ + Zd.T = SVE_fadd(Zd.T, Pg3_m, Zd.T_2, sve_float_0510:1); +} + +# fadd_z_p_zz.xml: FADD (vectors, predicated) variant SVE +# PATTERN x65008000/mask=xff3fe000 + +:fadd Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b000 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_fadd(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# fadd_z_zz.xml: FADD (vectors, unpredicated) variant SVE +# PATTERN x65000000/mask=xff20fc00 + +:fadd Zd.T, Zn.T, Zm.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b00 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T +{ + Zd.T = SVE_fadd(Zd.T, Zn.T, Zm.T); +} + +# fadda_v_p_z.xml: FADDA variant SVE +# PATTERN x65182000/mask=xff3fe000 + +:fadda Rd_FPR8, Pg3, Rd_FPR8_2, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223=0b00 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR8 & Rd_FPR8_2 & Pg3 +{ + Rd_FPR8 = SVE_fadda(Rd_FPR8, Pg3, Rd_FPR8_2, Zn.T); +} + +# fadda_v_p_z.xml: FADDA variant SVE +# PATTERN x65182000/mask=xff3fe000 + +:fadda Rd_FPR32, Pg3, Rd_FPR32_2, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223=0b10 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR32 & Rd_FPR32_2 & Pg3 +{ + Rd_FPR32 = SVE_fadda(Rd_FPR32, Pg3, Rd_FPR32_2, Zn.T); +} + +# fadda_v_p_z.xml: FADDA variant SVE +# PATTERN x65182000/mask=xff3fe000 + +:fadda Rd_FPR16, Pg3, Rd_FPR16_2, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223=0b01 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR16 & Rd_FPR16_2 & Pg3 +{ + Rd_FPR16 = SVE_fadda(Rd_FPR16, Pg3, Rd_FPR16_2, Zn.T); +} + +# fadda_v_p_z.xml: FADDA variant SVE +# PATTERN x65182000/mask=xff3fe000 + +:fadda Rd_FPR64, Pg3, Rd_FPR64_2, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223=0b11 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR64 & Rd_FPR64_2 & Pg3 +{ + Rd_FPR64 = SVE_fadda(Rd_FPR64, Pg3, Rd_FPR64_2, Zn.T); +} + +# faddv_v_p_z.xml: FADDV variant SVE +# PATTERN x65002000/mask=xff3fe000 + +:faddv Rd_FPR8, Pg3, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223=0b00 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3 +{ + Rd_FPR8 = SVE_faddv(Rd_FPR8, Pg3, Zn.T); +} + +# faddv_v_p_z.xml: FADDV variant SVE +# PATTERN x65002000/mask=xff3fe000 + +:faddv Rd_FPR32, Pg3, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223=0b10 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3 +{ + Rd_FPR32 = SVE_faddv(Rd_FPR32, Pg3, Zn.T); +} + +# faddv_v_p_z.xml: FADDV variant SVE +# PATTERN x65002000/mask=xff3fe000 + +:faddv Rd_FPR16, Pg3, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223=0b01 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3 +{ + Rd_FPR16 = SVE_faddv(Rd_FPR16, Pg3, Zn.T); +} + +# faddv_v_p_z.xml: FADDV variant SVE +# PATTERN x65002000/mask=xff3fe000 + +:faddv Rd_FPR64, Pg3, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223=0b11 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3 +{ + Rd_FPR64 = SVE_faddv(Rd_FPR64, Pg3, Zn.T); +} + +# fcadd_z_p_zz.xml: FCADD variant SVE +# PATTERN x64008000/mask=xff3ee000 + +:fcadd Zd.T, Pg3_m, Zd.T_2, Zn.T, sve_rot_16 +is sve_b_2431=0b01100100 & sve_size_2223 & sve_b_1721=0b00000 & sve_rot_16 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_fcadd(Zd.T, Pg3_m, Zd.T_2, Zn.T, sve_rot_16:1); +} + +# fcmeq_p_p_z0.xml: FCM (zero) variant Equal +# PATTERN x65122000/mask=xff3fe010 + +:fcmeq Pd.T, Pg3_z, Zn.T, "#0.0" +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1821=0b0100 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z +{ + Pd.T = SVE_fcmeq(Pd.T, Pg3_z, Zn.T); +} + +# fcmeq_p_p_z0.xml: FCM (zero) variant Greater than +# PATTERN x65102010/mask=xff3fe010 + +:fcmgt Pd.T, Pg3_z, Zn.T, "#0.0" +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1821=0b0100 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z +{ + Pd.T = SVE_fcmgt(Pd.T, Pg3_z, Zn.T); +} + +# fcmeq_p_p_z0.xml: FCM (zero) variant Greater than or equal +# PATTERN x65102000/mask=xff3fe010 + +:fcmge Pd.T, Pg3_z, Zn.T, "#0.0" +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1821=0b0100 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z +{ + Pd.T = SVE_fcmge(Pd.T, Pg3_z, Zn.T); +} + +# fcmeq_p_p_z0.xml: FCM (zero) variant Less than +# PATTERN x65112000/mask=xff3fe010 + +:fcmlt Pd.T, Pg3_z, Zn.T, "#0.0" +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1821=0b0100 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z +{ + Pd.T = SVE_fcmlt(Pd.T, Pg3_z, Zn.T); +} + +# fcmeq_p_p_z0.xml: FCM (zero) variant Less than or equal +# PATTERN x65112010/mask=xff3fe010 + +:fcmle Pd.T, Pg3_z, Zn.T, "#0.0" +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1821=0b0100 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z +{ + Pd.T = SVE_fcmle(Pd.T, Pg3_z, Zn.T); +} + +# fcmeq_p_p_z0.xml: FCM (zero) variant Not equal +# PATTERN x65132000/mask=xff3fe010 + +:fcmne Pd.T, Pg3_z, Zn.T, "#0.0" +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1821=0b0100 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z +{ + Pd.T = SVE_fcmne(Pd.T, Pg3_z, Zn.T); +} + +# fcmeq_p_p_zz.xml: FCM (vectors) variant Equal +# PATTERN x65006000/mask=xff20e010 + +:fcmeq Pd.T, Pg3_z, Zn.T, Zm.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z +{ + Pd.T = SVE_fcmeq(Pd.T, Pg3_z, Zn.T, Zm.T); +} + +# fcmeq_p_p_zz.xml: FCM (vectors) variant Greater than +# PATTERN x65004010/mask=xff20e010 + +:fcmgt Pd.T, Pg3_z, Zn.T, Zm.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z +{ + Pd.T = SVE_fcmgt(Pd.T, Pg3_z, Zn.T, Zm.T); +} + +# fcmeq_p_p_zz.xml: FCM (vectors) variant Greater than or equal +# PATTERN x65004000/mask=xff20e010 + +:fcmge Pd.T, Pg3_z, Zn.T, Zm.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z +{ + Pd.T = SVE_fcmge(Pd.T, Pg3_z, Zn.T, Zm.T); +} + +# fcmeq_p_p_zz.xml: FCM (vectors) variant Not equal +# PATTERN x65006010/mask=xff20e010 + +:fcmne Pd.T, Pg3_z, Zn.T, Zm.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z +{ + Pd.T = SVE_fcmne(Pd.T, Pg3_z, Zn.T, Zm.T); +} + +# fcmeq_p_p_zz.xml: FCM (vectors) variant Unordered +# PATTERN x6500c000/mask=xff20e010 + +:fcmuo Pd.T, Pg3_z, Zn.T, Zm.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z +{ + Pd.T = SVE_fcmuo(Pd.T, Pg3_z, Zn.T, Zm.T); +} + +# fcmla_z_p_zzz.xml: FCMLA (vectors) variant SVE +# PATTERN x64000000/mask=xff208000 + +:fcmla Zd.T, Pg3_m, Zn.T, Zm.T, sve_rot_1314 +is sve_b_2431=0b01100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_rot_1314 & sve_pg_1012 & sve_zn_0509 & sve_zda_0004 & Zd.T & Zm.T & Zn.T & Pg3_m +{ + Zd.T = SVE_fcmla(Zd.T, Pg3_m, Zn.T, Zm.T, sve_rot_1314:1); +} + +# fcmla_z_zzzi.xml: FCMLA (indexed) variant Half-precision +# PATTERN x64a01000/mask=xffe0f000 + +:fcmla Zd.H, Zn.H, Zm3.H[sve_i2_1920], sve_rot_1011 +is sve_b_2431=0b01100100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_i2_1920 & sve_zm_1618 & sve_b_1215=0b0001 & sve_rot_1011 & sve_zn_0509 & sve_zda_0004 & Zd.H & Zn.H & Zm3.H +{ + Zd.H = SVE_fcmla(Zd.H, Zn.H, Zm3.H, sve_i2_1920:1, sve_rot_1011:1); +} + +# fcmla_z_zzzi.xml: FCMLA (indexed) variant Single-precision +# PATTERN x64e01000/mask=xffe0f000 + +:fcmla Zd.S, Zn.S, Zm4.S[sve_i1_20], sve_rot_1011 +is sve_b_2431=0b01100100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_i1_20 & sve_zm_1619 & sve_b_1215=0b0001 & sve_rot_1011 & sve_zn_0509 & sve_zda_0004 & Zd.S & Zn.S & Zm4.S +{ + Zd.S = SVE_fcmla(Zd.S, Zn.S, Zm4.S, sve_i1_20:1, sve_rot_1011:1); +} + +# fcmle_fcmeq_p_p_zz.xml: FCMLE (vectors) variant Greater than or equal +# ALIASEDBY FCMGE ., /Z, ., . if Never +# PATTERN x65004000/mask=xff20e010 + +# SKIPPING fcmle_fcmeq_p_p_zz.xml because x65004000/mask=xff20e010 has already been defined + +# fcmlt_fcmeq_p_p_zz.xml: FCMLT (vectors) variant Greater than +# ALIASEDBY FCMGT ., /Z, ., . if Never +# PATTERN x65004010/mask=xff20e010 + +# SKIPPING fcmlt_fcmeq_p_p_zz.xml because x65004010/mask=xff20e010 has already been defined + +# fcpy_z_p_i.xml: FCPY variant SVE +# PATTERN x0510c000/mask=xff30e000 + +:fcpy Zd.T, Pm_m, "#"^sve_float_imm8 +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_2021=0b01 & sve_pg_1619 & sve_b_1315=0b110 & sve_imm8_0512 & sve_zd_0004 & sve_float_imm8 & Zd.T & Pm_m +{ + Zd.T = SVE_fcpy(Zd.T, Pm_m, sve_float_imm8:1); +} + +# fcvt_z_p_z.xml: FCVT variant Half-precision to single-precision +# PATTERN x6589a000/mask=xffffe000 + +:fcvt Zd.S, Pg3_m, Zn.H +is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=0 & sve_b_1821=0b0010 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.S & Pg3_m +{ + Zd.S = SVE_fcvt(Zd.S, Pg3_m, Zn.H); +} + +# fcvt_z_p_z.xml: FCVT variant Half-precision to double-precision +# PATTERN x65c9a000/mask=xffffe000 + +:fcvt Zd.D, Pg3_m, Zn.H +is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1821=0b0010 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.D & Pg3_m +{ + Zd.D = SVE_fcvt(Zd.D, Pg3_m, Zn.H); +} + +# fcvt_z_p_z.xml: FCVT variant Single-precision to half-precision +# PATTERN x6588a000/mask=xffffe000 + +:fcvt Zd.H, Pg3_m, Zn.S +is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=0 & sve_b_1821=0b0010 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.H & Pg3_m +{ + Zd.H = SVE_fcvt(Zd.H, Pg3_m, Zn.S); +} + +# fcvt_z_p_z.xml: FCVT variant Single-precision to double-precision +# PATTERN x65cba000/mask=xffffe000 + +:fcvt Zd.D, Pg3_m, Zn.S +is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1821=0b0010 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.D & Pg3_m +{ + Zd.D = SVE_fcvt(Zd.D, Pg3_m, Zn.S); +} + +# fcvt_z_p_z.xml: FCVT variant Double-precision to half-precision +# PATTERN x65c8a000/mask=xffffe000 + +:fcvt Zd.H, Pg3_m, Zn.D +is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1821=0b0010 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.H & Pg3_m +{ + Zd.H = SVE_fcvt(Zd.H, Pg3_m, Zn.D); +} + +# fcvt_z_p_z.xml: FCVT variant Double-precision to single-precision +# PATTERN x65caa000/mask=xffffe000 + +:fcvt Zd.S, Pg3_m, Zn.D +is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1821=0b0010 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.S & Pg3_m +{ + Zd.S = SVE_fcvt(Zd.S, Pg3_m, Zn.D); +} + +# fcvtzs_z_p_z.xml: FCVTZS variant Half-precision to 16-bit +# PATTERN x655aa000/mask=xffffe000 + +:fcvtzs Zd.H, Pg3_m, Zn.H +is sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=0 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.H & Pg3_m +{ + Zd.H = SVE_fcvtzs(Zd.H, Pg3_m, Zn.H); +} + +# fcvtzs_z_p_z.xml: FCVTZS variant Half-precision to 32-bit +# PATTERN x655ca000/mask=xffffe000 + +:fcvtzs Zd.S, Pg3_m, Zn.H +is sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.S & Pg3_m +{ + Zd.S = SVE_fcvtzs(Zd.S, Pg3_m, Zn.H); +} + +# fcvtzs_z_p_z.xml: FCVTZS variant Half-precision to 64-bit +# PATTERN x655ea000/mask=xffffe000 + +:fcvtzs Zd.D, Pg3_m, Zn.H +is sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.D & Pg3_m +{ + Zd.D = SVE_fcvtzs(Zd.D, Pg3_m, Zn.H); +} + +# fcvtzs_z_p_z.xml: FCVTZS variant Single-precision to 32-bit +# PATTERN x659ca000/mask=xffffe000 + +:fcvtzs Zd.S, Pg3_m, Zn.S +is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=0 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.S & Pg3_m +{ + Zd.S = SVE_fcvtzs(Zd.S, Pg3_m, Zn.S); +} + +# fcvtzs_z_p_z.xml: FCVTZS variant Single-precision to 64-bit +# PATTERN x65dca000/mask=xffffe000 + +:fcvtzs Zd.D, Pg3_m, Zn.S +is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.D & Pg3_m +{ + Zd.D = SVE_fcvtzs(Zd.D, Pg3_m, Zn.S); +} + +# fcvtzs_z_p_z.xml: FCVTZS variant Double-precision to 32-bit +# PATTERN x65d8a000/mask=xffffe000 + +:fcvtzs Zd.S, Pg3_m, Zn.D +is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=0 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.S & Pg3_m +{ + Zd.S = SVE_fcvtzs(Zd.S, Pg3_m, Zn.D); +} + +# fcvtzs_z_p_z.xml: FCVTZS variant Double-precision to 64-bit +# PATTERN x65dea000/mask=xffffe000 + +:fcvtzs Zd.D, Pg3_m, Zn.D +is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Pg3_m +{ + Zd.D = SVE_fcvtzs(Zd.D, Pg3_m, Zn.D); +} + +# fcvtzu_z_p_z.xml: FCVTZU variant Half-precision to 16-bit +# PATTERN x655ba000/mask=xffffe000 + +:fcvtzu Zd.H, Pg3_m, Zn.H +is sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=0 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.H & Pg3_m +{ + Zd.H = SVE_fcvtzu(Zd.H, Pg3_m, Zn.H); +} + +# fcvtzu_z_p_z.xml: FCVTZU variant Half-precision to 32-bit +# PATTERN x655da000/mask=xffffe000 + +:fcvtzu Zd.S, Pg3_m, Zn.H +is sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.S & Pg3_m +{ + Zd.S = SVE_fcvtzu(Zd.S, Pg3_m, Zn.H); +} + +# fcvtzu_z_p_z.xml: FCVTZU variant Half-precision to 64-bit +# PATTERN x655fa000/mask=xffffe000 + +:fcvtzu Zd.D, Pg3_m, Zn.H +is sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.D & Pg3_m +{ + Zd.D = SVE_fcvtzu(Zd.D, Pg3_m, Zn.H); +} + +# fcvtzu_z_p_z.xml: FCVTZU variant Single-precision to 32-bit +# PATTERN x659da000/mask=xffffe000 + +:fcvtzu Zd.S, Pg3_m, Zn.S +is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=0 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.S & Pg3_m +{ + Zd.S = SVE_fcvtzu(Zd.S, Pg3_m, Zn.S); +} + +# fcvtzu_z_p_z.xml: FCVTZU variant Single-precision to 64-bit +# PATTERN x65dda000/mask=xffffe000 + +:fcvtzu Zd.D, Pg3_m, Zn.S +is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.D & Pg3_m +{ + Zd.D = SVE_fcvtzu(Zd.D, Pg3_m, Zn.S); +} + +# fcvtzu_z_p_z.xml: FCVTZU variant Double-precision to 32-bit +# PATTERN x65d9a000/mask=xffffe000 + +:fcvtzu Zd.S, Pg3_m, Zn.D +is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=0 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.S & Pg3_m +{ + Zd.S = SVE_fcvtzu(Zd.S, Pg3_m, Zn.D); +} + +# fcvtzu_z_p_z.xml: FCVTZU variant Double-precision to 64-bit +# PATTERN x65dfa000/mask=xffffe000 + +:fcvtzu Zd.D, Pg3_m, Zn.D +is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Pg3_m +{ + Zd.D = SVE_fcvtzu(Zd.D, Pg3_m, Zn.D); +} + +# fdiv_z_p_zz.xml: FDIV variant SVE +# PATTERN x650d8000/mask=xff3fe000 + +:fdiv Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b110 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_fdiv(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# fdivr_z_p_zz.xml: FDIVR variant SVE +# PATTERN x650c8000/mask=xff3fe000 + +:fdivr Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b110 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_fdivr(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# fdup_z_i.xml: FDUP variant SVE +# PATTERN x2539c000/mask=xff3fe000 + +:fdup Zd.T, "#"^sve_float_imm8 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b111 & sve_b_18=0 & sve_b_17=0 & sve_b_1416=0b111 & sve_b_13=0 & sve_imm8_0512 & sve_zd_0004 & sve_float_imm8 & Zd.T +{ + Zd.T = SVE_fdup(Zd.T, sve_float_imm8:1); +} + +# fexpa_z_z.xml: FEXPA variant SVE +# PATTERN x0420b800/mask=xff3ffc00 + +:fexpa Zd.T, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_b_1720=0b0000 & sve_b_16=0 & sve_b_1015=0b101110 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T +{ + Zd.T = SVE_fexpa(Zd.T, Zn.T); +} + +# fmad_z_p_zzz.xml: FMAD variant SVE +# PATTERN x65208000/mask=xff20e000 + +:fmad Zd.T, Pg3_m, Zn.T, Zm.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=1 & sve_za_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zn.T & Zm.T & Pg3_m +{ + Zd.T = SVE_fmad(Zd.T, Pg3_m, Zn.T, Zm.T); +} + +# fmax_z_p_zs.xml: FMAX (immediate) variant SVE +# PATTERN x651e8000/mask=xff3fe3c0 + +:fmax Zd.T, Pg3_m, Zd.T_2, sve_float_0010 +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_b_0609=0b0000 & sve_i1_05 & sve_zdn_0004 & sve_float_0010 & Zd.T & Zd.T_2 & Pg3_m +{ + Zd.T = SVE_fmax(Zd.T, Pg3_m, Zd.T_2, sve_float_0010:1); +} + +# fmax_z_p_zz.xml: FMAX (vectors) variant SVE +# PATTERN x65068000/mask=xff3fe000 + +:fmax Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b011 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_fmax(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# fmaxnm_z_p_zs.xml: FMAXNM (immediate) variant SVE +# PATTERN x651c8000/mask=xff3fe3c0 + +:fmaxnm Zd.T, Pg3_m, Zd.T_2, sve_float_0010 +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_b_0609=0b0000 & sve_i1_05 & sve_zdn_0004 & sve_float_0010 & Zd.T & Zd.T_2 & Pg3_m +{ + Zd.T = SVE_fmaxnm(Zd.T, Pg3_m, Zd.T_2, sve_float_0010:1); +} + +# fmaxnm_z_p_zz.xml: FMAXNM (vectors) variant SVE +# PATTERN x65048000/mask=xff3fe000 + +:fmaxnm Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b010 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_fmaxnm(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# fmaxnmv_v_p_z.xml: FMAXNMV variant SVE +# PATTERN x65042000/mask=xff3fe000 + +:fmaxnmv Rd_FPR8, Pg3, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223=0b00 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3 +{ + Rd_FPR8 = SVE_fmaxnmv(Rd_FPR8, Pg3, Zn.T); +} + +# fmaxnmv_v_p_z.xml: FMAXNMV variant SVE +# PATTERN x65042000/mask=xff3fe000 + +:fmaxnmv Rd_FPR32, Pg3, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223=0b10 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3 +{ + Rd_FPR32 = SVE_fmaxnmv(Rd_FPR32, Pg3, Zn.T); +} + +# fmaxnmv_v_p_z.xml: FMAXNMV variant SVE +# PATTERN x65042000/mask=xff3fe000 + +:fmaxnmv Rd_FPR16, Pg3, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223=0b01 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3 +{ + Rd_FPR16 = SVE_fmaxnmv(Rd_FPR16, Pg3, Zn.T); +} + +# fmaxnmv_v_p_z.xml: FMAXNMV variant SVE +# PATTERN x65042000/mask=xff3fe000 + +:fmaxnmv Rd_FPR64, Pg3, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223=0b11 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3 +{ + Rd_FPR64 = SVE_fmaxnmv(Rd_FPR64, Pg3, Zn.T); +} + +# fmaxv_v_p_z.xml: FMAXV variant SVE +# PATTERN x65062000/mask=xff3fe000 + +:fmaxv Rd_FPR8, Pg3, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223=0b00 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3 +{ + Rd_FPR8 = SVE_fmaxv(Rd_FPR8, Pg3, Zn.T); +} + +# fmaxv_v_p_z.xml: FMAXV variant SVE +# PATTERN x65062000/mask=xff3fe000 + +:fmaxv Rd_FPR32, Pg3, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223=0b10 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3 +{ + Rd_FPR32 = SVE_fmaxv(Rd_FPR32, Pg3, Zn.T); +} + +# fmaxv_v_p_z.xml: FMAXV variant SVE +# PATTERN x65062000/mask=xff3fe000 + +:fmaxv Rd_FPR16, Pg3, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223=0b01 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3 +{ + Rd_FPR16 = SVE_fmaxv(Rd_FPR16, Pg3, Zn.T); +} + +# fmaxv_v_p_z.xml: FMAXV variant SVE +# PATTERN x65062000/mask=xff3fe000 + +:fmaxv Rd_FPR64, Pg3, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223=0b11 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3 +{ + Rd_FPR64 = SVE_fmaxv(Rd_FPR64, Pg3, Zn.T); +} + +# fmin_z_p_zs.xml: FMIN (immediate) variant SVE +# PATTERN x651f8000/mask=xff3fe3c0 + +:fmin Zd.T, Pg3_m, Zd.T_2, sve_float_0010 +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_b_0609=0b0000 & sve_i1_05 & sve_zdn_0004 & sve_float_0010 & Zd.T & Zd.T_2 & Pg3_m +{ + Zd.T = SVE_fmin(Zd.T, Pg3_m, Zd.T_2, sve_float_0010:1); +} + +# fmin_z_p_zz.xml: FMIN (vectors) variant SVE +# PATTERN x65078000/mask=xff3fe000 + +:fmin Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b011 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_fmin(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# fminnm_z_p_zs.xml: FMINNM (immediate) variant SVE +# PATTERN x651d8000/mask=xff3fe3c0 + +:fminnm Zd.T, Pg3_m, Zd.T_2, sve_float_0010 +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b10 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_b_0609=0b0000 & sve_i1_05 & sve_zdn_0004 & sve_float_0010 & Zd.T & Zd.T_2 & Pg3_m +{ + Zd.T = SVE_fminnm(Zd.T, Pg3_m, Zd.T_2, sve_float_0010:1); +} + +# fminnm_z_p_zz.xml: FMINNM (vectors) variant SVE +# PATTERN x65058000/mask=xff3fe000 + +:fminnm Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b010 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_fminnm(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# fminnmv_v_p_z.xml: FMINNMV variant SVE +# PATTERN x65052000/mask=xff3fe000 + +:fminnmv Rd_FPR8, Pg3, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223=0b00 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3 +{ + Rd_FPR8 = SVE_fminnmv(Rd_FPR8, Pg3, Zn.T); +} + +# fminnmv_v_p_z.xml: FMINNMV variant SVE +# PATTERN x65052000/mask=xff3fe000 + +:fminnmv Rd_FPR32, Pg3, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223=0b10 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3 +{ + Rd_FPR32 = SVE_fminnmv(Rd_FPR32, Pg3, Zn.T); +} + +# fminnmv_v_p_z.xml: FMINNMV variant SVE +# PATTERN x65052000/mask=xff3fe000 + +:fminnmv Rd_FPR16, Pg3, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223=0b01 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3 +{ + Rd_FPR16 = SVE_fminnmv(Rd_FPR16, Pg3, Zn.T); +} + +# fminnmv_v_p_z.xml: FMINNMV variant SVE +# PATTERN x65052000/mask=xff3fe000 + +:fminnmv Rd_FPR64, Pg3, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223=0b11 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3 +{ + Rd_FPR64 = SVE_fminnmv(Rd_FPR64, Pg3, Zn.T); +} + +# fminv_v_p_z.xml: FMINV variant SVE +# PATTERN x65072000/mask=xff3fe000 + +:fminv Rd_FPR8, Pg3, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223=0b00 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3 +{ + Rd_FPR8 = SVE_fminv(Rd_FPR8, Pg3, Zn.T); +} + +# fminv_v_p_z.xml: FMINV variant SVE +# PATTERN x65072000/mask=xff3fe000 + +:fminv Rd_FPR32, Pg3, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223=0b10 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3 +{ + Rd_FPR32 = SVE_fminv(Rd_FPR32, Pg3, Zn.T); +} + +# fminv_v_p_z.xml: FMINV variant SVE +# PATTERN x65072000/mask=xff3fe000 + +:fminv Rd_FPR16, Pg3, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223=0b01 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3 +{ + Rd_FPR16 = SVE_fminv(Rd_FPR16, Pg3, Zn.T); +} + +# fminv_v_p_z.xml: FMINV variant SVE +# PATTERN x65072000/mask=xff3fe000 + +:fminv Rd_FPR64, Pg3, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223=0b11 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3 +{ + Rd_FPR64 = SVE_fminv(Rd_FPR64, Pg3, Zn.T); +} + +# fmla_z_p_zzz.xml: FMLA (vectors) variant SVE +# PATTERN x65200000/mask=xff20e000 + +:fmla Zd.T, Pg3_m, Zn.T, Zm.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zda_0004 & Zd.T & Zm.T & Zn.T & Pg3_m +{ + Zd.T = SVE_fmla(Zd.T, Pg3_m, Zn.T, Zm.T); +} + +# fmla_z_zzzi.xml: FMLA (indexed) variant Half-precision +# PATTERN x64200000/mask=xffa0fc00 + +:fmla Zd.H, Zn.H, Zm3.H[sve_i3h_i3l] +is sve_b_2431=0b01100100 & sve_b_23=0 & sve_i3h_22 & sve_b_21=1 & sve_i3l_1920 & sve_zm_1618 & sve_b_1115=0b00000 & sve_b_10=0 & sve_zn_0509 & sve_zda_0004 & Zd.H & Zn.H & Zm3.H & sve_i3h_i3l +{ + Zd.H = SVE_fmla(Zd.H, Zn.H, Zm3.H, sve_i3h_i3l:1); +} + +# fmla_z_zzzi.xml: FMLA (indexed) variant Single-precision +# PATTERN x64a00000/mask=xffe0fc00 + +:fmla Zd.S, Zn.S, Zm3.S[sve_i2_1920] +is sve_b_2431=0b01100100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_i2_1920 & sve_zm_1618 & sve_b_1115=0b00000 & sve_b_10=0 & sve_zn_0509 & sve_zda_0004 & Zd.S & Zn.S & Zm3.S +{ + Zd.S = SVE_fmla(Zd.S, Zn.S, Zm3.S, sve_i2_1920:1); +} + +# fmla_z_zzzi.xml: FMLA (indexed) variant Double-precision +# PATTERN x64e00000/mask=xffe0fc00 + +:fmla Zd.D, Zn.D, Zm4.D[sve_i1_20] +is sve_b_2431=0b01100100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_i1_20 & sve_zm_1619 & sve_b_1115=0b00000 & sve_b_10=0 & sve_zn_0509 & sve_zda_0004 & Zd.D & Zn.D & Zm4.D +{ + Zd.D = SVE_fmla(Zd.D, Zn.D, Zm4.D, sve_i1_20:1); +} + +# fmls_z_p_zzz.xml: FMLS (vectors) variant SVE +# PATTERN x65202000/mask=xff20e000 + +:fmls Zd.T, Pg3_m, Zn.T, Zm.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zda_0004 & Zd.T & Zm.T & Zn.T & Pg3_m +{ + Zd.T = SVE_fmls(Zd.T, Pg3_m, Zn.T, Zm.T); +} + +# fmls_z_zzzi.xml: FMLS (indexed) variant Half-precision +# PATTERN x64200400/mask=xffa0fc00 + +:fmls Zd.H, Zn.H, Zm3.H[sve_i3h_i3l] +is sve_b_2431=0b01100100 & sve_b_23=0 & sve_i3h_22 & sve_b_21=1 & sve_i3l_1920 & sve_zm_1618 & sve_b_1115=0b00000 & sve_b_10=1 & sve_zn_0509 & sve_zda_0004 & Zd.H & Zn.H & Zm3.H & sve_i3h_i3l +{ + Zd.H = SVE_fmls(Zd.H, Zn.H, Zm3.H, sve_i3h_i3l:1); +} + +# fmls_z_zzzi.xml: FMLS (indexed) variant Single-precision +# PATTERN x64a00400/mask=xffe0fc00 + +:fmls Zd.S, Zn.S, Zm3.S[sve_i2_1920] +is sve_b_2431=0b01100100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_i2_1920 & sve_zm_1618 & sve_b_1115=0b00000 & sve_b_10=1 & sve_zn_0509 & sve_zda_0004 & Zd.S & Zn.S & Zm3.S +{ + Zd.S = SVE_fmls(Zd.S, Zn.S, Zm3.S, sve_i2_1920:1); +} + +# fmls_z_zzzi.xml: FMLS (indexed) variant Double-precision +# PATTERN x64e00400/mask=xffe0fc00 + +:fmls Zd.D, Zn.D, Zm4.D[sve_i1_20] +is sve_b_2431=0b01100100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_i1_20 & sve_zm_1619 & sve_b_1115=0b00000 & sve_b_10=1 & sve_zn_0509 & sve_zda_0004 & Zd.D & Zn.D & Zm4.D +{ + Zd.D = SVE_fmls(Zd.D, Zn.D, Zm4.D, sve_i1_20:1); +} + +# fmov_cpy_z_p_i.xml: FMOV (zero, predicated) variant SVE +# ALIASEDBY CPY ., /M, #0 if Never +# PATTERN x05104000/mask=xff30ffe0 + +:fmov Zd.T, Pm_m, "#0.0" +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_2021=0b01 & sve_pg_1619 & sve_b_15=0 & sve_m_14=1 & sve_sh_13=0 & sve_imm8_0512=0b00000000 & sve_zd_0004 & Zd.T & Pm_m +{ + Zd.T = SVE_fmov(Zd.T, Pm_m); +} + +# fmov_dup_z_i.xml: FMOV (zero, unpredicated) variant SVE +# ALIASEDBY DUP ., #0 if Never +# PATTERN x2538c000/mask=xff3fffe0 + +:fmov Zd.T, "#0.0" +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b111 & sve_b_18=0 & sve_b_17=0 & sve_b_1416=0b011 & sve_sh_13=0 & sve_imm8_0512=0b00000000 & sve_zd_0004 & Zd.T +{ + Zd.T = SVE_fmov(Zd.T); +} + +# fmov_fcpy_z_p_i.xml: FMOV (immediate, predicated) variant SVE +# ALIASEDBY FCPY ., /M, # if Unconditionally +# PATTERN x0510c000/mask=xff30e000 + +# SKIPPING fmov_fcpy_z_p_i.xml because x0510c000/mask=xff30e000 has already been defined + +# fmov_fdup_z_i.xml: FMOV (immediate, unpredicated) variant SVE +# ALIASEDBY FDUP ., # if Unconditionally +# PATTERN x2539c000/mask=xff3fe000 + +# SKIPPING fmov_fdup_z_i.xml because x2539c000/mask=xff3fe000 has already been defined + +# fmsb_z_p_zzz.xml: FMSB variant SVE +# PATTERN x6520a000/mask=xff20e000 + +:fmsb Zd.T, Pg3_m, Zn.T, Zm.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=1 & sve_za_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zn.T & Zm.T & Pg3_m +{ + Zd.T = SVE_fmsb(Zd.T, Pg3_m, Zn.T, Zm.T); +} + +# fmul_z_p_zs.xml: FMUL (immediate) variant SVE +# PATTERN x651a8000/mask=xff3fe3c0 + +:fmul Zd.T, Pg3_m, Zd.T_2, sve_float_0520 +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_b_0609=0b0000 & sve_i1_05 & sve_zdn_0004 & sve_float_0520 & Zd.T & Zd.T_2 & Pg3_m +{ + Zd.T = SVE_fmul(Zd.T, Pg3_m, Zd.T_2, sve_float_0520:1); +} + +# fmul_z_p_zz.xml: FMUL (vectors, predicated) variant SVE +# PATTERN x65028000/mask=xff3fe000 + +:fmul Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b001 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_fmul(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# fmul_z_zz.xml: FMUL (vectors, unpredicated) variant SVE +# PATTERN x65000800/mask=xff20fc00 + +:fmul Zd.T, Zn.T, Zm.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b01 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T +{ + Zd.T = SVE_fmul(Zd.T, Zn.T, Zm.T); +} + +# fmul_z_zzi.xml: FMUL (indexed) variant Half-precision +# PATTERN x64202000/mask=xffa0fc00 + +:fmul Zd.H, Zn.H, Zm3.H[sve_i3h_i3l] +is sve_b_2431=0b01100100 & sve_b_23=0 & sve_i3h_22 & sve_b_21=1 & sve_i3l_1920 & sve_zm_1618 & sve_b_1015=0b001000 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.H & Zm3.H & sve_i3h_i3l +{ + Zd.H = SVE_fmul(Zd.H, Zn.H, Zm3.H, sve_i3h_i3l:1); +} + +# fmul_z_zzi.xml: FMUL (indexed) variant Single-precision +# PATTERN x64a02000/mask=xffe0fc00 + +:fmul Zd.S, Zn.S, Zm3.S[sve_i2_1920] +is sve_b_2431=0b01100100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_i2_1920 & sve_zm_1618 & sve_b_1015=0b001000 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.S & Zm3.S +{ + Zd.S = SVE_fmul(Zd.S, Zn.S, Zm3.S, sve_i2_1920:1); +} + +# fmul_z_zzi.xml: FMUL (indexed) variant Double-precision +# PATTERN x64e02000/mask=xffe0fc00 + +:fmul Zd.D, Zn.D, Zm4.D[sve_i1_20] +is sve_b_2431=0b01100100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_i1_20 & sve_zm_1619 & sve_b_1015=0b001000 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Zm4.D +{ + Zd.D = SVE_fmul(Zd.D, Zn.D, Zm4.D, sve_i1_20:1); +} + +# fmulx_z_p_zz.xml: FMULX variant SVE +# PATTERN x650a8000/mask=xff3fe000 + +:fmulx Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b101 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_fmulx(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# fneg_z_p_z.xml: FNEG variant SVE +# PATTERN x041da000/mask=xff3fe000 + +:fneg Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b10 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_fneg(Zd.T, Pg3_m, Zn.T); +} + +# fnmad_z_p_zzz.xml: FNMAD variant SVE +# PATTERN x6520c000/mask=xff20e000 + +:fnmad Zd.T, Pg3_m, Zn.T, Zm.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=1 & sve_za_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zn.T & Zm.T & Pg3_m +{ + Zd.T = SVE_fnmad(Zd.T, Pg3_m, Zn.T, Zm.T); +} + +# fnmla_z_p_zzz.xml: FNMLA variant SVE +# PATTERN x65204000/mask=xff20e000 + +:fnmla Zd.T, Pg3_m, Zn.T, Zm.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zda_0004 & Zd.T & Zm.T & Zn.T & Pg3_m +{ + Zd.T = SVE_fnmla(Zd.T, Pg3_m, Zn.T, Zm.T); +} + +# fnmls_z_p_zzz.xml: FNMLS variant SVE +# PATTERN x65206000/mask=xff20e000 + +:fnmls Zd.T, Pg3_m, Zn.T, Zm.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zda_0004 & Zd.T & Zm.T & Zn.T & Pg3_m +{ + Zd.T = SVE_fnmls(Zd.T, Pg3_m, Zn.T, Zm.T); +} + +# fnmsb_z_p_zzz.xml: FNMSB variant SVE +# PATTERN x6520e000/mask=xff20e000 + +:fnmsb Zd.T, Pg3_m, Zn.T, Zm.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=1 & sve_za_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zn.T & Zm.T & Pg3_m +{ + Zd.T = SVE_fnmsb(Zd.T, Pg3_m, Zn.T, Zm.T); +} + +# frecpe_z_z.xml: FRECPE variant SVE +# PATTERN x650e3000/mask=xff3ffc00 + +:frecpe Zd.T, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b001 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1015=0b001100 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T +{ + Zd.T = SVE_frecpe(Zd.T, Zn.T); +} + +# frecps_z_zz.xml: FRECPS variant SVE +# PATTERN x65001800/mask=xff20fc00 + +:frecps Zd.T, Zn.T, Zm.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b11 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T +{ + Zd.T = SVE_frecps(Zd.T, Zn.T, Zm.T); +} + +# frecpx_z_p_z.xml: FRECPX variant SVE +# PATTERN x650ca000/mask=xff3fe000 + +:frecpx Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1821=0b0011 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_frecpx(Zd.T, Pg3_m, Zn.T); +} + +# frinta_z_p_z.xml: FRINT variant Current mode +# PATTERN x6507a000/mask=xff3fe000 + +:frinti Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_frinti(Zd.T, Pg3_m, Zn.T); +} + +# frinta_z_p_z.xml: FRINT variant Current mode signalling inexact +# PATTERN x6506a000/mask=xff3fe000 + +:frintx Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_frintx(Zd.T, Pg3_m, Zn.T); +} + +# frinta_z_p_z.xml: FRINT variant Nearest with ties to away +# PATTERN x6504a000/mask=xff3fe000 + +:frinta Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_frinta(Zd.T, Pg3_m, Zn.T); +} + +# frinta_z_p_z.xml: FRINT variant Nearest with ties to even +# PATTERN x6500a000/mask=xff3fe000 + +:frintn Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_frintn(Zd.T, Pg3_m, Zn.T); +} + +# frinta_z_p_z.xml: FRINT variant Toward zero +# PATTERN x6503a000/mask=xff3fe000 + +:frintz Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b000 & sve_b_1718=0b01 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_frintz(Zd.T, Pg3_m, Zn.T); +} + +# frinta_z_p_z.xml: FRINT variant Toward minus infinity +# PATTERN x6502a000/mask=xff3fe000 + +:frintm Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b000 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_frintm(Zd.T, Pg3_m, Zn.T); +} + +# frinta_z_p_z.xml: FRINT variant Toward plus infinity +# PATTERN x6501a000/mask=xff3fe000 + +:frintp Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_frintp(Zd.T, Pg3_m, Zn.T); +} + +# frsqrte_z_z.xml: FRSQRTE variant SVE +# PATTERN x650f3000/mask=xff3ffc00 + +:frsqrte Zd.T, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b001 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1015=0b001100 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T +{ + Zd.T = SVE_frsqrte(Zd.T, Zn.T); +} + +# frsqrts_z_zz.xml: FRSQRTS variant SVE +# PATTERN x65001c00/mask=xff20fc00 + +:frsqrts Zd.T, Zn.T, Zm.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b11 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T +{ + Zd.T = SVE_frsqrts(Zd.T, Zn.T, Zm.T); +} + +# fscale_z_p_zz.xml: FSCALE variant SVE +# PATTERN x65098000/mask=xff3fe000 + +:fscale Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b100 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_fscale(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# fsqrt_z_p_z.xml: FSQRT variant SVE +# PATTERN x650da000/mask=xff3fe000 + +:fsqrt Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1821=0b0011 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_fsqrt(Zd.T, Pg3_m, Zn.T); +} + +# fsub_z_p_zs.xml: FSUB (immediate) variant SVE +# PATTERN x65198000/mask=xff3fe3c0 + +:fsub Zd.T, Pg3_m, Zd.T_2, sve_float_0510 +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_b_0609=0b0000 & sve_i1_05 & sve_zdn_0004 & sve_float_0510 & Zd.T & Zd.T_2 & Pg3_m +{ + Zd.T = SVE_fsub(Zd.T, Pg3_m, Zd.T_2, sve_float_0510:1); +} + +# fsub_z_p_zz.xml: FSUB (vectors, predicated) variant SVE +# PATTERN x65018000/mask=xff3fe000 + +:fsub Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b000 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_fsub(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# fsub_z_zz.xml: FSUB (vectors, unpredicated) variant SVE +# PATTERN x65000400/mask=xff20fc00 + +:fsub Zd.T, Zn.T, Zm.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b00 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T +{ + Zd.T = SVE_fsub(Zd.T, Zn.T, Zm.T); +} + +# fsubr_z_p_zs.xml: FSUBR (immediate) variant SVE +# PATTERN x651b8000/mask=xff3fe3c0 + +:fsubr Zd.T, Pg3_m, Zd.T_2, sve_float_0510 +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_b_0609=0b0000 & sve_i1_05 & sve_zdn_0004 & sve_float_0510 & Zd.T & Zd.T_2 & Pg3_m +{ + Zd.T = SVE_fsubr(Zd.T, Pg3_m, Zd.T_2, sve_float_0510:1); +} + +# fsubr_z_p_zz.xml: FSUBR (vectors) variant SVE +# PATTERN x65038000/mask=xff3fe000 + +:fsubr Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b001 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_fsubr(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# ftmad_z_zzi.xml: FTMAD variant SVE +# PATTERN x65108000/mask=xff38fc00 + +:ftmad Zd.T, Zd.T_2, Zn.T, "#"^sve_imm3_1_0to7 +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b010 & sve_imm3_1618 & sve_b_1015=0b100000 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & sve_imm3_1_0to7 +{ + Zd.T = SVE_ftmad(Zd.T, Zd.T_2, Zn.T, sve_imm3_1_0to7:1); +} + +# ftsmul_z_zz.xml: FTSMUL variant SVE +# PATTERN x65000c00/mask=xff20fc00 + +:ftsmul Zd.T, Zn.T, Zm.T +is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b01 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T +{ + Zd.T = SVE_ftsmul(Zd.T, Zn.T, Zm.T); +} + +# ftssel_z_zz.xml: FTSSEL variant SVE +# PATTERN x0420b000/mask=xff20fc00 + +:ftssel Zd.T, Zn.T, Zm.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1115=0b10110 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T +{ + Zd.T = SVE_ftssel(Zd.T, Zn.T, Zm.T); +} + +# incb_r_rs.xml: INCB, INCD, INCH, INCW (scalar) variant Byte +# PATTERN x0430e000/mask=xfff0fc00 + +:incb Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_incb(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# incb_r_rs.xml: INCB, INCD, INCH, INCW (scalar) variant Doubleword +# PATTERN x04f0e000/mask=xfff0fc00 + +:incd Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_incd(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# incb_r_rs.xml: INCB, INCD, INCH, INCW (scalar) variant Halfword +# PATTERN x0470e000/mask=xfff0fc00 + +:inch Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_inch(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# incb_r_rs.xml: INCB, INCD, INCH, INCW (scalar) variant Word +# PATTERN x04b0e000/mask=xfff0fc00 + +:incw Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_incw(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# incd_z_zs.xml: INCD, INCH, INCW (vector) variant Doubleword +# PATTERN x04f0c000/mask=xfff0fc00 + +:incd Zd.D^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11000 & sve_b_10=0 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.D & sve_imm4_1_1to16 & sve_mul_pattern +{ + Zd.D = SVE_incd(Zd.D, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# incd_z_zs.xml: INCD, INCH, INCW (vector) variant Halfword +# PATTERN x0470c000/mask=xfff0fc00 + +:inch Zd.H^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11000 & sve_b_10=0 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.H & sve_imm4_1_1to16 & sve_mul_pattern +{ + Zd.H = SVE_inch(Zd.H, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# incd_z_zs.xml: INCD, INCH, INCW (vector) variant Word +# PATTERN x04b0c000/mask=xfff0fc00 + +:incw Zd.S^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11000 & sve_b_10=0 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.S & sve_imm4_1_1to16 & sve_mul_pattern +{ + Zd.S = SVE_incw(Zd.S, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# incp_r_p_r.xml: INCP (scalar) variant SVE +# PATTERN x252c8800/mask=xff3ffe00 + +:incp Rd_GPR64, Pn.T +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1011 & sve_b_17=0 & sve_b_16=0 & sve_b_1115=0b10001 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_rdn_0004 & Pn.T & Rd_GPR64 +{ + Rd_GPR64 = SVE_incp(Rd_GPR64, Pn.T); +} + +# incp_z_p_z.xml: INCP (vector) variant SVE +# PATTERN x252c8000/mask=xff3ffe00 + +:incp Zd.T, Pn +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1011 & sve_b_17=0 & sve_b_16=0 & sve_b_1115=0b10000 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_zdn_0004 & Zd.T & Pn +{ + Zd.T = SVE_incp(Zd.T, Pn); +} + +# index_z_ii.xml: INDEX (immediates) variant SVE +# PATTERN x04204000/mask=xff20fc00 + +:index Zd.T, "#"^sve_imm5s_0509, "#"^sve_imm5b_1620 +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_imm5b_1620 & sve_b_1015=0b010000 & sve_imm5_0509 & sve_zd_0004 & Zd.T & sve_imm5s_0509 +{ + Zd.T = SVE_index(Zd.T, sve_imm5s_0509:1, sve_imm5b_1620:1); +} + +# index_z_ir.xml: INDEX (immediate, scalar) variant SVE +# PATTERN x04204800/mask=xff20fc00 + +:index Zd.T, "#"^sve_imm5_1_m16to15, Rm_GPR64 +is sve_b_2431=0b00000100 & sve_size_2223=0b11 & sve_b_21=1 & sve_rm_1620 & sve_b_1015=0b010010 & sve_imm5_0509 & sve_zd_0004 & Zd.T & Rm_GPR64 & sve_imm5_1_m16to15 +{ + Zd.T = SVE_index(Zd.T, sve_imm5_1_m16to15:1, Rm_GPR64); +} + +# index_z_ir.xml: INDEX (immediate, scalar) variant SVE +# PATTERN x04204800/mask=xff20fc00 + +:index Zd.T, "#"^sve_imm5_1_m16to15, Rm_GPR32 +is sve_b_2431=0b00000100 & (b_23=0 | b_22=0) & sve_b_21=1 & sve_rm_1620 & sve_b_1015=0b010010 & sve_imm5_0509 & sve_zd_0004 & Zd.T & Rm_GPR32 & sve_imm5_1_m16to15 +{ + Zd.T = SVE_index(Zd.T, sve_imm5_1_m16to15:1, Rm_GPR32); +} + +# index_z_ri.xml: INDEX (scalar, immediate) variant SVE +# PATTERN x04204400/mask=xff20fc00 + +:index Zd.T, Rn_GPR64, "#"^sve_imm5_1_m16to15 +is sve_b_2431=0b00000100 & sve_size_2223=0b11 & sve_b_21=1 & sve_imm5_1620 & sve_b_1015=0b010001 & sve_rn_0509 & sve_zd_0004 & Zd.T & Rn_GPR64 & sve_imm5_1_m16to15 +{ + Zd.T = SVE_index(Zd.T, Rn_GPR64, sve_imm5_1_m16to15:1); +} + +# index_z_ri.xml: INDEX (scalar, immediate) variant SVE +# PATTERN x04204400/mask=xff20fc00 + +:index Zd.T, Rn_GPR32, "#"^sve_imm5_1_m16to15 +is sve_b_2431=0b00000100 & (b_23=0 | b_22=0) & sve_b_21=1 & sve_imm5_1620 & sve_b_1015=0b010001 & sve_rn_0509 & sve_zd_0004 & Zd.T & Rn_GPR32 & sve_imm5_1_m16to15 +{ + Zd.T = SVE_index(Zd.T, Rn_GPR32, sve_imm5_1_m16to15:1); +} + +# index_z_rr.xml: INDEX (scalars) variant SVE +# PATTERN x04204c00/mask=xff20fc00 + +:index Zd.T, Rn_GPR64, Rm_GPR64 +is sve_b_2431=0b00000100 & sve_size_2223=0b11 & sve_b_21=1 & sve_rm_1620 & sve_b_1015=0b010011 & sve_rn_0509 & sve_zd_0004 & Zd.T & Rn_GPR64 & Rm_GPR64 +{ + Zd.T = SVE_index(Zd.T, Rn_GPR64, Rm_GPR64); +} + +# index_z_rr.xml: INDEX (scalars) variant SVE +# PATTERN x04204c00/mask=xff20fc00 + +:index Zd.T, Rn_GPR32, Rm_GPR32 +is sve_b_2431=0b00000100 & (b_23=0 | b_22=0) & sve_b_21=1 & sve_rm_1620 & sve_b_1015=0b010011 & sve_rn_0509 & sve_zd_0004 & Zd.T & Rn_GPR32 & Rm_GPR32 +{ + Zd.T = SVE_index(Zd.T, Rn_GPR32, Rm_GPR32); +} + +# insr_z_r.xml: INSR (scalar) variant SVE +# PATTERN x05243800/mask=xff3ffc00 + +:insr Zd.T, Rn_GPR64 +is sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1021=0b100100001110 & sve_rm_0509 & sve_zdn_0004 & Zd.T & Rn_GPR64 +{ + Zd.T = SVE_insr(Zd.T, Rn_GPR64); +} + +# insr_z_r.xml: INSR (scalar) variant SVE +# PATTERN x05243800/mask=xff3ffc00 + +:insr Zd.T, Rn_GPR32 +is sve_b_2431=0b00000101 & (b_23=0 | b_22=0) & sve_b_1021=0b100100001110 & sve_rm_0509 & sve_zdn_0004 & Zd.T & Rn_GPR32 +{ + Zd.T = SVE_insr(Zd.T, Rn_GPR32); +} + +# insr_z_v.xml: INSR (SIMD&FP scalar) variant SVE +# PATTERN x05343800/mask=xff3ffc00 + +:insr Zd.T, Rn_FPR8 +is sve_b_2431=0b00000101 & sve_size_2223=0b00 & sve_b_1021=0b110100001110 & sve_vm_0509 & sve_zdn_0004 & Zd.T & Rn_FPR8 +{ + Zd.T = SVE_insr(Zd.T, Rn_FPR8); +} + +# insr_z_v.xml: INSR (SIMD&FP scalar) variant SVE +# PATTERN x05343800/mask=xff3ffc00 + +:insr Zd.T, Rn_FPR32 +is sve_b_2431=0b00000101 & sve_size_2223=0b10 & sve_b_1021=0b110100001110 & sve_vm_0509 & sve_zdn_0004 & Zd.T & Rn_FPR32 +{ + Zd.T = SVE_insr(Zd.T, Rn_FPR32); +} + +# insr_z_v.xml: INSR (SIMD&FP scalar) variant SVE +# PATTERN x05343800/mask=xff3ffc00 + +:insr Zd.T, Rn_FPR16 +is sve_b_2431=0b00000101 & sve_size_2223=0b01 & sve_b_1021=0b110100001110 & sve_vm_0509 & sve_zdn_0004 & Zd.T & Rn_FPR16 +{ + Zd.T = SVE_insr(Zd.T, Rn_FPR16); +} + +# insr_z_v.xml: INSR (SIMD&FP scalar) variant SVE +# PATTERN x05343800/mask=xff3ffc00 + +:insr Zd.T, Rn_FPR64 +is sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1021=0b110100001110 & sve_vm_0509 & sve_zdn_0004 & Zd.T & Rn_FPR64 +{ + Zd.T = SVE_insr(Zd.T, Rn_FPR64); +} + +# lasta_r_p_z.xml: LASTA (scalar) variant SVE +# PATTERN x0520a000/mask=xff3fe000 + +:lasta Rd_GPR64, Pg3, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1721=0b10000 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_rd_0004 & Zn.T & Rd_GPR64 & Pg3 +{ + Rd_GPR64 = SVE_lasta(Rd_GPR64, Pg3, Zn.T); +} + +# lasta_r_p_z.xml: LASTA (scalar) variant SVE +# PATTERN x0520a000/mask=xff3fe000 + +:lasta Rd_GPR32, Pg3, Zn.T +is sve_b_2431=0b00000101 & (b_23=0 | b_22=0) & sve_b_1721=0b10000 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_rd_0004 & Zn.T & Rd_GPR32 & Pg3 +{ + Rd_GPR32 = SVE_lasta(Rd_GPR32, Pg3, Zn.T); +} + +# lasta_v_p_z.xml: LASTA (SIMD&FP scalar) variant SVE +# PATTERN x05228000/mask=xff3fe000 + +:lasta Rd_FPR8, Pg3, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223=0b00 & sve_b_1721=0b10001 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3 +{ + Rd_FPR8 = SVE_lasta(Rd_FPR8, Pg3, Zn.T); +} + +# lasta_v_p_z.xml: LASTA (SIMD&FP scalar) variant SVE +# PATTERN x05228000/mask=xff3fe000 + +:lasta Rd_FPR32, Pg3, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223=0b10 & sve_b_1721=0b10001 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3 +{ + Rd_FPR32 = SVE_lasta(Rd_FPR32, Pg3, Zn.T); +} + +# lasta_v_p_z.xml: LASTA (SIMD&FP scalar) variant SVE +# PATTERN x05228000/mask=xff3fe000 + +:lasta Rd_FPR16, Pg3, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223=0b01 & sve_b_1721=0b10001 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3 +{ + Rd_FPR16 = SVE_lasta(Rd_FPR16, Pg3, Zn.T); +} + +# lasta_v_p_z.xml: LASTA (SIMD&FP scalar) variant SVE +# PATTERN x05228000/mask=xff3fe000 + +:lasta Rd_FPR64, Pg3, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1721=0b10001 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3 +{ + Rd_FPR64 = SVE_lasta(Rd_FPR64, Pg3, Zn.T); +} + +# lastb_r_p_z.xml: LASTB (scalar) variant SVE +# PATTERN x0521a000/mask=xff3fe000 + +:lastb Rd_GPR64, Pg3, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1721=0b10000 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_rd_0004 & Zn.T & Rd_GPR64 & Pg3 +{ + Rd_GPR64 = SVE_lastb(Rd_GPR64, Pg3, Zn.T); +} + +# lastb_r_p_z.xml: LASTB (scalar) variant SVE +# PATTERN x0521a000/mask=xff3fe000 + +:lastb Rd_GPR32, Pg3, Zn.T +is sve_b_2431=0b00000101 & (b_23=0 | b_22=0) & sve_b_1721=0b10000 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_rd_0004 & Zn.T & Rd_GPR32 & Pg3 +{ + Rd_GPR32 = SVE_lastb(Rd_GPR32, Pg3, Zn.T); +} + +# lastb_v_p_z.xml: LASTB (SIMD&FP scalar) variant SVE +# PATTERN x05238000/mask=xff3fe000 + +:lastb Rd_FPR8, Pg3, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223=0b00 & sve_b_1721=0b10001 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3 +{ + Rd_FPR8 = SVE_lastb(Rd_FPR8, Pg3, Zn.T); +} + +# lastb_v_p_z.xml: LASTB (SIMD&FP scalar) variant SVE +# PATTERN x05238000/mask=xff3fe000 + +:lastb Rd_FPR32, Pg3, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223=0b10 & sve_b_1721=0b10001 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3 +{ + Rd_FPR32 = SVE_lastb(Rd_FPR32, Pg3, Zn.T); +} + +# lastb_v_p_z.xml: LASTB (SIMD&FP scalar) variant SVE +# PATTERN x05238000/mask=xff3fe000 + +:lastb Rd_FPR16, Pg3, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223=0b01 & sve_b_1721=0b10001 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3 +{ + Rd_FPR16 = SVE_lastb(Rd_FPR16, Pg3, Zn.T); +} + +# lastb_v_p_z.xml: LASTB (SIMD&FP scalar) variant SVE +# PATTERN x05238000/mask=xff3fe000 + +:lastb Rd_FPR64, Pg3, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1721=0b10001 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3 +{ + Rd_FPR64 = SVE_lastb(Rd_FPR64, Pg3, Zn.T); +} + +# ld1b_z_p_ai.xml: LD1B (vector plus immediate) variant 32-bit element +# PATTERN x8420c000/mask=xffe0e000 + +:ld1b "{"^Zd.S^"}", Pg3_z, [Zn.S^sve_opt5_1_0to31] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Pg3_z & Zd.S & sve_opt5_1_0to31 +{ + Zd.S = SVE_ld1b(Zd.S, Pg3_z, Zn.S, sve_opt5_1_0to31); +} + +# ld1b_z_p_ai.xml: LD1B (vector plus immediate) variant 64-bit element +# PATTERN xc420c000/mask=xffe0e000 + +:ld1b "{"^Zd.D^"}", Pg3_z, [Zn.D^sve_opt5_1_0to31] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to31 +{ + Zd.D = SVE_ld1b(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to31); +} + +# ld1b_z_p_bi.xml: LD1B (scalar plus immediate) variant 8-bit element +# PATTERN xa400a000/mask=xfff0e000 + +:ld1b "{"^Zd.B^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b000 & sve_b_21=0 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.B & sve_mul4_1_m8to7 +{ + Zd.B = SVE_ld1b(Zd.B, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ld1b_z_p_bi.xml: LD1B (scalar plus immediate) variant 16-bit element +# PATTERN xa420a000/mask=xfff0e000 + +:ld1b "{"^Zd.H^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b000 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & sve_mul4_1_m8to7 +{ + Zd.H = SVE_ld1b(Zd.H, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ld1b_z_p_bi.xml: LD1B (scalar plus immediate) variant 32-bit element +# PATTERN xa440a000/mask=xfff0e000 + +:ld1b "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b001 & sve_b_21=0 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_mul4_1_m8to7 +{ + Zd.S = SVE_ld1b(Zd.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ld1b_z_p_bi.xml: LD1B (scalar plus immediate) variant 64-bit element +# PATTERN xa460a000/mask=xfff0e000 + +:ld1b "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b001 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7 +{ + Zd.D = SVE_ld1b(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ld1b_z_p_br.xml: LD1B (scalar plus scalar) variant 8-bit element +# PATTERN xa4004000/mask=xffe0e000 + +:ld1b "{"^Zd.B^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1010010 & sve_b_2224=0b000 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.B & Rm_GPR64 +{ + Zd.B = SVE_ld1b(Zd.B, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld1b_z_p_br.xml: LD1B (scalar plus scalar) variant 16-bit element +# PATTERN xa4204000/mask=xffe0e000 + +:ld1b "{"^Zd.H^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1010010 & sve_b_2224=0b000 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & Rm_GPR64 +{ + Zd.H = SVE_ld1b(Zd.H, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld1b_z_p_br.xml: LD1B (scalar plus scalar) variant 32-bit element +# PATTERN xa4404000/mask=xffe0e000 + +:ld1b "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1010010 & sve_b_2224=0b001 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & Rm_GPR64 +{ + Zd.S = SVE_ld1b(Zd.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld1b_z_p_br.xml: LD1B (scalar plus scalar) variant 64-bit element +# PATTERN xa4604000/mask=xffe0e000 + +:ld1b "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1010010 & sve_b_2224=0b001 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64 +{ + Zd.D = SVE_ld1b(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld1b_z_p_bz.xml: LD1B (scalar plus vector) variant 32-bit unpacked unscaled offset +# PATTERN xc4004000/mask=xffa0e000 + +:ld1b "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod +{ + Zd.D = SVE_ld1b(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# ld1b_z_p_bz.xml: LD1B (scalar plus vector) variant 32-bit unscaled offset +# PATTERN x84004000/mask=xffa0e000 + +:ld1b "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod +{ + Zd.S = SVE_ld1b(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# ld1b_z_p_bz.xml: LD1B (scalar plus vector) variant 64-bit unscaled offset +# PATTERN xc440c000/mask=xffe0e000 + +:ld1b "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D +{ + Zd.D = SVE_ld1b(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D); +} + +# ld1d_z_p_ai.xml: LD1D (vector plus immediate) variant SVE +# PATTERN xc5a0c000/mask=xffe0e000 + +:ld1d "{"^Zd.D^"}", Pg3_z, [Zn.D^sve_opt5_1_0to248] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to248 +{ + Zd.D = SVE_ld1d(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to248); +} + +# ld1d_z_p_bi.xml: LD1D (scalar plus immediate) variant SVE +# PATTERN xa5e0a000/mask=xfff0e000 + +:ld1d "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b111 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7 +{ + Zd.D = SVE_ld1d(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ld1d_z_p_br.xml: LD1D (scalar plus scalar) variant SVE +# PATTERN xa5e04000/mask=xffe0e000 + +:ld1d "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #3"] +is sve_b_2531=0b1010010 & sve_b_2224=0b111 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64 +{ + Zd.D = SVE_ld1d(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld1d_z_p_bz.xml: LD1D (scalar plus vector) variant 32-bit unpacked scaled offset +# PATTERN xc5a04000/mask=xffa0e000 + +:ld1d "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod^" #3"] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=1 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod +{ + Zd.D = SVE_ld1d(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# ld1d_z_p_bz.xml: LD1D (scalar plus vector) variant 32-bit unpacked unscaled offset +# PATTERN xc5804000/mask=xffa0e000 + +:ld1d "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=1 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod +{ + Zd.D = SVE_ld1d(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# ld1d_z_p_bz.xml: LD1D (scalar plus vector) variant 64-bit scaled offset +# PATTERN xc5e0c000/mask=xffe0e000 + +:ld1d "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, "lsl #3"] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b11 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D +{ + Zd.D = SVE_ld1d(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D); +} + +# ld1d_z_p_bz.xml: LD1D (scalar plus vector) variant 64-bit unscaled offset +# PATTERN xc5c0c000/mask=xffe0e000 + +:ld1d "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D +{ + Zd.D = SVE_ld1d(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D); +} + +# ld1h_z_p_ai.xml: LD1H (vector plus immediate) variant 32-bit element +# PATTERN x84a0c000/mask=xffe0e000 + +:ld1h "{"^Zd.S^"}", Pg3_z, [Zn.S^sve_opt5_1_0to62] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Pg3_z & Zd.S & sve_opt5_1_0to62 +{ + Zd.S = SVE_ld1h(Zd.S, Pg3_z, Zn.S, sve_opt5_1_0to62); +} + +# ld1h_z_p_ai.xml: LD1H (vector plus immediate) variant 64-bit element +# PATTERN xc4a0c000/mask=xffe0e000 + +:ld1h "{"^Zd.D^"}", Pg3_z, [Zn.D^sve_opt5_1_0to62] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to62 +{ + Zd.D = SVE_ld1h(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to62); +} + +# ld1h_z_p_bi.xml: LD1H (scalar plus immediate) variant 16-bit element +# PATTERN xa4a0a000/mask=xfff0e000 + +:ld1h "{"^Zd.H^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b010 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & sve_mul4_1_m8to7 +{ + Zd.H = SVE_ld1h(Zd.H, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ld1h_z_p_bi.xml: LD1H (scalar plus immediate) variant 32-bit element +# PATTERN xa4c0a000/mask=xfff0e000 + +:ld1h "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b011 & sve_b_21=0 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_mul4_1_m8to7 +{ + Zd.S = SVE_ld1h(Zd.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ld1h_z_p_bi.xml: LD1H (scalar plus immediate) variant 64-bit element +# PATTERN xa4e0a000/mask=xfff0e000 + +:ld1h "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b011 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7 +{ + Zd.D = SVE_ld1h(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ld1h_z_p_br.xml: LD1H (scalar plus scalar) variant 16-bit element +# PATTERN xa4a04000/mask=xffe0e000 + +:ld1h "{"^Zd.H^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #1"] +is sve_b_2531=0b1010010 & sve_b_2224=0b010 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & Rm_GPR64 +{ + Zd.H = SVE_ld1h(Zd.H, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld1h_z_p_br.xml: LD1H (scalar plus scalar) variant 32-bit element +# PATTERN xa4c04000/mask=xffe0e000 + +:ld1h "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #1"] +is sve_b_2531=0b1010010 & sve_b_2224=0b011 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & Rm_GPR64 +{ + Zd.S = SVE_ld1h(Zd.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld1h_z_p_br.xml: LD1H (scalar plus scalar) variant 64-bit element +# PATTERN xa4e04000/mask=xffe0e000 + +:ld1h "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #1"] +is sve_b_2531=0b1010010 & sve_b_2224=0b011 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64 +{ + Zd.D = SVE_ld1h(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld1h_z_p_bz.xml: LD1H (scalar plus vector) variant 32-bit scaled offset +# PATTERN x84a04000/mask=xffa0e000 + +:ld1h "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod^" #1"] +is sve_b_2331=0b100001001 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod +{ + Zd.S = SVE_ld1h(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# ld1h_z_p_bz.xml: LD1H (scalar plus vector) variant 32-bit unpacked scaled offset +# PATTERN xc4a04000/mask=xffa0e000 + +:ld1h "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod^" #1"] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod +{ + Zd.D = SVE_ld1h(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# ld1h_z_p_bz.xml: LD1H (scalar plus vector) variant 32-bit unpacked unscaled offset +# PATTERN xc4804000/mask=xffa0e000 + +:ld1h "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod +{ + Zd.D = SVE_ld1h(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# ld1h_z_p_bz.xml: LD1H (scalar plus vector) variant 32-bit unscaled offset +# PATTERN x84804000/mask=xffa0e000 + +:ld1h "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod +{ + Zd.S = SVE_ld1h(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# ld1h_z_p_bz.xml: LD1H (scalar plus vector) variant 64-bit scaled offset +# PATTERN xc4e0c000/mask=xffe0e000 + +:ld1h "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, "lsl #1"] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b11 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D +{ + Zd.D = SVE_ld1h(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D); +} + +# ld1h_z_p_bz.xml: LD1H (scalar plus vector) variant 64-bit unscaled offset +# PATTERN xc4c0c000/mask=xffe0e000 + +:ld1h "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D +{ + Zd.D = SVE_ld1h(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D); +} + +# ld1rb_z_p_bi.xml: LD1RB variant 8-bit element +# PATTERN x84408000/mask=xffc0e000 + +:ld1rb "{"^Zd.B^"}", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to63] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.B & sve_opt6_1_0to63 +{ + Zd.B = SVE_ld1rb(Zd.B, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to63); +} + +# ld1rb_z_p_bi.xml: LD1RB variant 16-bit element +# PATTERN x8440a000/mask=xffc0e000 + +:ld1rb "{"^Zd.H^"}", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to63] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & sve_opt6_1_0to63 +{ + Zd.H = SVE_ld1rb(Zd.H, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to63); +} + +# ld1rb_z_p_bi.xml: LD1RB variant 32-bit element +# PATTERN x8440c000/mask=xffc0e000 + +:ld1rb "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to63] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_opt6_1_0to63 +{ + Zd.S = SVE_ld1rb(Zd.S, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to63); +} + +# ld1rb_z_p_bi.xml: LD1RB variant 64-bit element +# PATTERN x8440e000/mask=xffc0e000 + +:ld1rb "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to63] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_opt6_1_0to63 +{ + Zd.D = SVE_ld1rb(Zd.D, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to63); +} + +# ld1rd_z_p_bi.xml: LD1RD variant SVE +# PATTERN x85c0e000/mask=xffc0e000 + +:ld1rd "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to504] +is sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=1 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_opt6_1_0to504 +{ + Zd.D = SVE_ld1rd(Zd.D, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to504); +} + +# ld1rh_z_p_bi.xml: LD1RH variant 16-bit element +# PATTERN x84c0a000/mask=xffc0e000 + +:ld1rh "{"^Zd.H^"}", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to126] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & sve_opt6_1_0to126 +{ + Zd.H = SVE_ld1rh(Zd.H, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to126); +} + +# ld1rh_z_p_bi.xml: LD1RH variant 32-bit element +# PATTERN x84c0c000/mask=xffc0e000 + +:ld1rh "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to126] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_opt6_1_0to126 +{ + Zd.S = SVE_ld1rh(Zd.S, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to126); +} + +# ld1rh_z_p_bi.xml: LD1RH variant 64-bit element +# PATTERN x84c0e000/mask=xffc0e000 + +:ld1rh "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to126] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_opt6_1_0to126 +{ + Zd.D = SVE_ld1rh(Zd.D, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to126); +} + +# ld1rqb_z_p_bi.xml: LD1RQB (scalar plus immediate) variant SVE +# PATTERN xa4002000/mask=xfff0e000 + +:ld1rqb "{"^Zd.B^"}", Pg3_z, [Rn_GPR64xsp^sve_opt4_1_m128to112] +is sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b00 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b001 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.B & sve_opt4_1_m128to112 +{ + Zd.B = SVE_ld1rqb(Zd.B, Pg3_z, Rn_GPR64xsp, sve_opt4_1_m128to112); +} + +# ld1rqb_z_p_br.xml: LD1RQB (scalar plus scalar) variant SVE +# PATTERN xa4000000/mask=xffe0e000 + +:ld1rqb "{"^Zd.B^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b000 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.B & Rm_GPR64 +{ + Zd.B = SVE_ld1rqb(Zd.B, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld1rqd_z_p_bi.xml: LD1RQD (scalar plus immediate) variant SVE +# PATTERN xa5802000/mask=xfff0e000 + +:ld1rqd "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp^sve_opt4_1_m128to112] +is sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b00 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b001 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_opt4_1_m128to112 +{ + Zd.D = SVE_ld1rqd(Zd.D, Pg3_z, Rn_GPR64xsp, sve_opt4_1_m128to112); +} + +# ld1rqd_z_p_br.xml: LD1RQD (scalar plus scalar) variant SVE +# PATTERN xa5800000/mask=xffe0e000 + +:ld1rqd "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #3"] +is sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b000 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64 +{ + Zd.D = SVE_ld1rqd(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld1rqh_z_p_bi.xml: LD1RQH (scalar plus immediate) variant SVE +# PATTERN xa4802000/mask=xfff0e000 + +:ld1rqh "{"^Zd.H^"}", Pg3_z, [Rn_GPR64xsp^sve_opt4_1_m128to112] +is sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b00 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b001 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & sve_opt4_1_m128to112 +{ + Zd.H = SVE_ld1rqh(Zd.H, Pg3_z, Rn_GPR64xsp, sve_opt4_1_m128to112); +} + +# ld1rqh_z_p_br.xml: LD1RQH (scalar plus scalar) variant SVE +# PATTERN xa4800000/mask=xffe0e000 + +:ld1rqh "{"^Zd.H^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #1"] +is sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b000 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & Rm_GPR64 +{ + Zd.H = SVE_ld1rqh(Zd.H, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld1rqw_z_p_bi.xml: LD1RQW (scalar plus immediate) variant SVE +# PATTERN xa5002000/mask=xfff0e000 + +:ld1rqw "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp^sve_opt4_1_m128to112] +is sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b00 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b001 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_opt4_1_m128to112 +{ + Zd.S = SVE_ld1rqw(Zd.S, Pg3_z, Rn_GPR64xsp, sve_opt4_1_m128to112); +} + +# ld1rqw_z_p_br.xml: LD1RQW (scalar plus scalar) variant SVE +# PATTERN xa5000000/mask=xffe0e000 + +:ld1rqw "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #2"] +is sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b000 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & Rm_GPR64 +{ + Zd.S = SVE_ld1rqw(Zd.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld1rsb_z_p_bi.xml: LD1RSB variant 16-bit element +# PATTERN x85c0c000/mask=xffc0e000 + +:ld1rsb "{"^Zd.H^"}", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to63] +is sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=1 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & sve_opt6_1_0to63 +{ + Zd.H = SVE_ld1rsb(Zd.H, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to63); +} + +# ld1rsb_z_p_bi.xml: LD1RSB variant 32-bit element +# PATTERN x85c0a000/mask=xffc0e000 + +:ld1rsb "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to63] +is sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=1 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_opt6_1_0to63 +{ + Zd.S = SVE_ld1rsb(Zd.S, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to63); +} + +# ld1rsb_z_p_bi.xml: LD1RSB variant 64-bit element +# PATTERN x85c08000/mask=xffc0e000 + +:ld1rsb "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to63] +is sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=1 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_opt6_1_0to63 +{ + Zd.D = SVE_ld1rsb(Zd.D, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to63); +} + +# ld1rsh_z_p_bi.xml: LD1RSH variant 32-bit element +# PATTERN x8540a000/mask=xffc0e000 + +:ld1rsh "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to126] +is sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=0 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_opt6_1_0to126 +{ + Zd.S = SVE_ld1rsh(Zd.S, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to126); +} + +# ld1rsh_z_p_bi.xml: LD1RSH variant 64-bit element +# PATTERN x85408000/mask=xffc0e000 + +:ld1rsh "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to126] +is sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=0 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_opt6_1_0to126 +{ + Zd.D = SVE_ld1rsh(Zd.D, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to126); +} + +# ld1rsw_z_p_bi.xml: LD1RSW variant SVE +# PATTERN x84c08000/mask=xffc0e000 + +:ld1rsw "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to252] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_opt6_1_0to252 +{ + Zd.D = SVE_ld1rsw(Zd.D, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to252); +} + +# ld1rw_z_p_bi.xml: LD1RW variant 32-bit element +# PATTERN x8540c000/mask=xffc0e000 + +:ld1rw "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to252] +is sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=0 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_opt6_1_0to252 +{ + Zd.S = SVE_ld1rw(Zd.S, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to252); +} + +# ld1rw_z_p_bi.xml: LD1RW variant 64-bit element +# PATTERN x8540e000/mask=xffc0e000 + +:ld1rw "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp^sve_opt6_1_0to252] +is sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=0 & sve_b_22=1 & sve_imm6_1621 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_opt6_1_0to252 +{ + Zd.D = SVE_ld1rw(Zd.D, Pg3_z, Rn_GPR64xsp, sve_opt6_1_0to252); +} + +# ld1sb_z_p_ai.xml: LD1SB (vector plus immediate) variant 32-bit element +# PATTERN x84208000/mask=xffe0e000 + +:ld1sb "{"^Zd.S^"}", Pg3_z, [Zn.S^sve_opt5_1_0to31] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Pg3_z & Zd.S & sve_opt5_1_0to31 +{ + Zd.S = SVE_ld1sb(Zd.S, Pg3_z, Zn.S, sve_opt5_1_0to31); +} + +# ld1sb_z_p_ai.xml: LD1SB (vector plus immediate) variant 64-bit element +# PATTERN xc4208000/mask=xffe0e000 + +:ld1sb "{"^Zd.D^"}", Pg3_z, [Zn.D^sve_opt5_1_0to31] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to31 +{ + Zd.D = SVE_ld1sb(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to31); +} + +# ld1sb_z_p_bi.xml: LD1SB (scalar plus immediate) variant 16-bit element +# PATTERN xa5c0a000/mask=xfff0e000 + +:ld1sb "{"^Zd.H^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b111 & sve_b_21=0 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & sve_mul4_1_m8to7 +{ + Zd.H = SVE_ld1sb(Zd.H, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ld1sb_z_p_bi.xml: LD1SB (scalar plus immediate) variant 32-bit element +# PATTERN xa5a0a000/mask=xfff0e000 + +:ld1sb "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b110 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_mul4_1_m8to7 +{ + Zd.S = SVE_ld1sb(Zd.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ld1sb_z_p_bi.xml: LD1SB (scalar plus immediate) variant 64-bit element +# PATTERN xa580a000/mask=xfff0e000 + +:ld1sb "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b110 & sve_b_21=0 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7 +{ + Zd.D = SVE_ld1sb(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ld1sb_z_p_br.xml: LD1SB (scalar plus scalar) variant 16-bit element +# PATTERN xa5c04000/mask=xffe0e000 + +:ld1sb "{"^Zd.H^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1010010 & sve_b_2224=0b111 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & Rm_GPR64 +{ + Zd.H = SVE_ld1sb(Zd.H, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld1sb_z_p_br.xml: LD1SB (scalar plus scalar) variant 32-bit element +# PATTERN xa5a04000/mask=xffe0e000 + +:ld1sb "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1010010 & sve_b_2224=0b110 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & Rm_GPR64 +{ + Zd.S = SVE_ld1sb(Zd.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld1sb_z_p_br.xml: LD1SB (scalar plus scalar) variant 64-bit element +# PATTERN xa5804000/mask=xffe0e000 + +:ld1sb "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1010010 & sve_b_2224=0b110 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64 +{ + Zd.D = SVE_ld1sb(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld1sb_z_p_bz.xml: LD1SB (scalar plus vector) variant 32-bit unpacked unscaled offset +# PATTERN xc4000000/mask=xffa0e000 + +:ld1sb "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod +{ + Zd.D = SVE_ld1sb(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# ld1sb_z_p_bz.xml: LD1SB (scalar plus vector) variant 32-bit unscaled offset +# PATTERN x84000000/mask=xffa0e000 + +:ld1sb "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod +{ + Zd.S = SVE_ld1sb(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# ld1sb_z_p_bz.xml: LD1SB (scalar plus vector) variant 64-bit unscaled offset +# PATTERN xc4408000/mask=xffe0e000 + +:ld1sb "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D +{ + Zd.D = SVE_ld1sb(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D); +} + +# ld1sh_z_p_ai.xml: LD1SH (vector plus immediate) variant 32-bit element +# PATTERN x84a08000/mask=xffe0e000 + +:ld1sh "{"^Zd.S^"}", Pg3_z, [Zn.S^sve_opt5_1_0to62] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Pg3_z & Zd.S & sve_opt5_1_0to62 +{ + Zd.S = SVE_ld1sh(Zd.S, Pg3_z, Zn.S, sve_opt5_1_0to62); +} + +# ld1sh_z_p_ai.xml: LD1SH (vector plus immediate) variant 64-bit element +# PATTERN xc4a08000/mask=xffe0e000 + +:ld1sh "{"^Zd.D^"}", Pg3_z, [Zn.D^sve_opt5_1_0to62] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to62 +{ + Zd.D = SVE_ld1sh(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to62); +} + +# ld1sh_z_p_bi.xml: LD1SH (scalar plus immediate) variant 32-bit element +# PATTERN xa520a000/mask=xfff0e000 + +:ld1sh "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b100 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_mul4_1_m8to7 +{ + Zd.S = SVE_ld1sh(Zd.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ld1sh_z_p_bi.xml: LD1SH (scalar plus immediate) variant 64-bit element +# PATTERN xa500a000/mask=xfff0e000 + +:ld1sh "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b100 & sve_b_21=0 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7 +{ + Zd.D = SVE_ld1sh(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ld1sh_z_p_br.xml: LD1SH (scalar plus scalar) variant 32-bit element +# PATTERN xa5204000/mask=xffe0e000 + +:ld1sh "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #1"] +is sve_b_2531=0b1010010 & sve_b_2224=0b100 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & Rm_GPR64 +{ + Zd.S = SVE_ld1sh(Zd.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld1sh_z_p_br.xml: LD1SH (scalar plus scalar) variant 64-bit element +# PATTERN xa5004000/mask=xffe0e000 + +:ld1sh "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #1"] +is sve_b_2531=0b1010010 & sve_b_2224=0b100 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64 +{ + Zd.D = SVE_ld1sh(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld1sh_z_p_bz.xml: LD1SH (scalar plus vector) variant 32-bit scaled offset +# PATTERN x84a00000/mask=xffa0e000 + +:ld1sh "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod^" #1"] +is sve_b_2331=0b100001001 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod +{ + Zd.S = SVE_ld1sh(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# ld1sh_z_p_bz.xml: LD1SH (scalar plus vector) variant 32-bit unpacked scaled offset +# PATTERN xc4a00000/mask=xffa0e000 + +:ld1sh "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod^" #1"] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod +{ + Zd.D = SVE_ld1sh(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# ld1sh_z_p_bz.xml: LD1SH (scalar plus vector) variant 32-bit unpacked unscaled offset +# PATTERN xc4800000/mask=xffa0e000 + +:ld1sh "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod +{ + Zd.D = SVE_ld1sh(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# ld1sh_z_p_bz.xml: LD1SH (scalar plus vector) variant 32-bit unscaled offset +# PATTERN x84800000/mask=xffa0e000 + +:ld1sh "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod +{ + Zd.S = SVE_ld1sh(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# ld1sh_z_p_bz.xml: LD1SH (scalar plus vector) variant 64-bit scaled offset +# PATTERN xc4e08000/mask=xffe0e000 + +:ld1sh "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, "lsl #1"] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b11 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D +{ + Zd.D = SVE_ld1sh(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D); +} + +# ld1sh_z_p_bz.xml: LD1SH (scalar plus vector) variant 64-bit unscaled offset +# PATTERN xc4c08000/mask=xffe0e000 + +:ld1sh "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D +{ + Zd.D = SVE_ld1sh(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D); +} + +# ld1sw_z_p_ai.xml: LD1SW (vector plus immediate) variant SVE +# PATTERN xc5208000/mask=xffe0e000 + +:ld1sw "{"^Zd.D^"}", Pg3_z, [Zn.D^sve_opt5_1_0to124] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to124 +{ + Zd.D = SVE_ld1sw(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to124); +} + +# ld1sw_z_p_bi.xml: LD1SW (scalar plus immediate) variant SVE +# PATTERN xa480a000/mask=xfff0e000 + +:ld1sw "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b010 & sve_b_21=0 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7 +{ + Zd.D = SVE_ld1sw(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ld1sw_z_p_br.xml: LD1SW (scalar plus scalar) variant SVE +# PATTERN xa4804000/mask=xffe0e000 + +:ld1sw "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #2"] +is sve_b_2531=0b1010010 & sve_b_2224=0b010 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64 +{ + Zd.D = SVE_ld1sw(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld1sw_z_p_bz.xml: LD1SW (scalar plus vector) variant 32-bit unpacked scaled offset +# PATTERN xc5200000/mask=xffa0e000 + +:ld1sw "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod^" #2"] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod +{ + Zd.D = SVE_ld1sw(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# ld1sw_z_p_bz.xml: LD1SW (scalar plus vector) variant 32-bit unpacked unscaled offset +# PATTERN xc5000000/mask=xffa0e000 + +:ld1sw "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod +{ + Zd.D = SVE_ld1sw(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# ld1sw_z_p_bz.xml: LD1SW (scalar plus vector) variant 64-bit scaled offset +# PATTERN xc5608000/mask=xffe0e000 + +:ld1sw "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, "lsl #2"] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b11 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D +{ + Zd.D = SVE_ld1sw(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D); +} + +# ld1sw_z_p_bz.xml: LD1SW (scalar plus vector) variant 64-bit unscaled offset +# PATTERN xc5408000/mask=xffe0e000 + +:ld1sw "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D +{ + Zd.D = SVE_ld1sw(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D); +} + +# ld1w_z_p_ai.xml: LD1W (vector plus immediate) variant 32-bit element +# PATTERN x8520c000/mask=xffe0e000 + +:ld1w "{"^Zd.S^"}", Pg3_z, [Zn.S^sve_opt5_1_0to124] +is sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Pg3_z & Zd.S & sve_opt5_1_0to124 +{ + Zd.S = SVE_ld1w(Zd.S, Pg3_z, Zn.S, sve_opt5_1_0to124); +} + +# ld1w_z_p_ai.xml: LD1W (vector plus immediate) variant 64-bit element +# PATTERN xc520c000/mask=xffe0e000 + +:ld1w "{"^Zd.D^"}", Pg3_z, [Zn.D^sve_opt5_1_0to124] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to124 +{ + Zd.D = SVE_ld1w(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to124); +} + +# ld1w_z_p_bi.xml: LD1W (scalar plus immediate) variant 32-bit element +# PATTERN xa540a000/mask=xfff0e000 + +:ld1w "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b101 & sve_b_21=0 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_mul4_1_m8to7 +{ + Zd.S = SVE_ld1w(Zd.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ld1w_z_p_bi.xml: LD1W (scalar plus immediate) variant 64-bit element +# PATTERN xa560a000/mask=xfff0e000 + +:ld1w "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b101 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7 +{ + Zd.D = SVE_ld1w(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ld1w_z_p_br.xml: LD1W (scalar plus scalar) variant 32-bit element +# PATTERN xa5404000/mask=xffe0e000 + +:ld1w "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #2"] +is sve_b_2531=0b1010010 & sve_b_2224=0b101 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & Rm_GPR64 +{ + Zd.S = SVE_ld1w(Zd.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld1w_z_p_br.xml: LD1W (scalar plus scalar) variant 64-bit element +# PATTERN xa5604000/mask=xffe0e000 + +:ld1w "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #2"] +is sve_b_2531=0b1010010 & sve_b_2224=0b101 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64 +{ + Zd.D = SVE_ld1w(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld1w_z_p_bz.xml: LD1W (scalar plus vector) variant 32-bit scaled offset +# PATTERN x85204000/mask=xffa0e000 + +:ld1w "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod^" #2"] +is sve_b_2331=0b100001010 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod +{ + Zd.S = SVE_ld1w(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# ld1w_z_p_bz.xml: LD1W (scalar plus vector) variant 32-bit unpacked scaled offset +# PATTERN xc5204000/mask=xffa0e000 + +:ld1w "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod^" #2"] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod +{ + Zd.D = SVE_ld1w(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# ld1w_z_p_bz.xml: LD1W (scalar plus vector) variant 32-bit unpacked unscaled offset +# PATTERN xc5004000/mask=xffa0e000 + +:ld1w "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod +{ + Zd.D = SVE_ld1w(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# ld1w_z_p_bz.xml: LD1W (scalar plus vector) variant 32-bit unscaled offset +# PATTERN x85004000/mask=xffa0e000 + +:ld1w "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod] +is sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod +{ + Zd.S = SVE_ld1w(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# ld1w_z_p_bz.xml: LD1W (scalar plus vector) variant 64-bit scaled offset +# PATTERN xc560c000/mask=xffe0e000 + +:ld1w "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, "lsl #2"] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b11 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D +{ + Zd.D = SVE_ld1w(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D); +} + +# ld1w_z_p_bz.xml: LD1W (scalar plus vector) variant 64-bit unscaled offset +# PATTERN xc540c000/mask=xffe0e000 + +:ld1w "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D +{ + Zd.D = SVE_ld1w(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D); +} + +# ld2b_z_p_bi.xml: LD2B (scalar plus immediate) variant SVE +# PATTERN xa420e000/mask=xfff0e000 + +:ld2b "{"^Zt.B, Ztt.B^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m16to14] +is sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b01 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.B & Zt.B & Rn_GPR64xsp & Pg3_z & sve_mul4_1_m16to14 +{ + Zt.B = SVE_ld2b(Zt.B, Ztt.B, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m16to14); +} + +# ld2b_z_p_br.xml: LD2B (scalar plus scalar) variant SVE +# PATTERN xa420c000/mask=xffe0e000 + +:ld2b "{"^Zt.B, Ztt.B^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b01 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.B & Zt.B & Rn_GPR64xsp & Pg3_z & Rm_GPR64 +{ + Zt.B = SVE_ld2b(Zt.B, Ztt.B, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld2d_z_p_bi.xml: LD2D (scalar plus immediate) variant SVE +# PATTERN xa5a0e000/mask=xfff0e000 + +:ld2d "{"^Zt.D, Ztt.D^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m16to14] +is sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b01 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.D & Zt.D & Rn_GPR64xsp & Pg3_z & sve_mul4_1_m16to14 +{ + Zt.D = SVE_ld2d(Zt.D, Ztt.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m16to14); +} + +# ld2d_z_p_br.xml: LD2D (scalar plus scalar) variant SVE +# PATTERN xa5a0c000/mask=xffe0e000 + +:ld2d "{"^Zt.D, Ztt.D^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #3"] +is sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b01 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.D & Zt.D & Rn_GPR64xsp & Pg3_z & Rm_GPR64 +{ + Zt.D = SVE_ld2d(Zt.D, Ztt.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld2h_z_p_bi.xml: LD2H (scalar plus immediate) variant SVE +# PATTERN xa4a0e000/mask=xfff0e000 + +:ld2h "{"^Zt.H, Ztt.H^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m16to14] +is sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.H & Zt.H & Rn_GPR64xsp & Pg3_z & sve_mul4_1_m16to14 +{ + Zt.H = SVE_ld2h(Zt.H, Ztt.H, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m16to14); +} + +# ld2h_z_p_br.xml: LD2H (scalar plus scalar) variant SVE +# PATTERN xa4a0c000/mask=xffe0e000 + +:ld2h "{"^Zt.H, Ztt.H^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #1"] +is sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.H & Zt.H & Rn_GPR64xsp & Pg3_z & Rm_GPR64 +{ + Zt.H = SVE_ld2h(Zt.H, Ztt.H, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld2w_z_p_bi.xml: LD2W (scalar plus immediate) variant SVE +# PATTERN xa520e000/mask=xfff0e000 + +:ld2w "{"^Zt.S, Ztt.S^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m16to14] +is sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b01 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.S & Zt.S & Rn_GPR64xsp & Pg3_z & sve_mul4_1_m16to14 +{ + Zt.S = SVE_ld2w(Zt.S, Ztt.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m16to14); +} + +# ld2w_z_p_br.xml: LD2W (scalar plus scalar) variant SVE +# PATTERN xa520c000/mask=xffe0e000 + +:ld2w "{"^Zt.S, Ztt.S^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #2"] +is sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b01 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.S & Zt.S & Rn_GPR64xsp & Pg3_z & Rm_GPR64 +{ + Zt.S = SVE_ld2w(Zt.S, Ztt.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld3b_z_p_bi.xml: LD3B (scalar plus immediate) variant SVE +# PATTERN xa440e000/mask=xfff0e000 + +:ld3b "{"^Zt.B, Ztt.B, Zttt.B^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m24to21] +is sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b10 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.B & Zttt.B & Zt.B & Rn_GPR64xsp & Pg3_z & sve_mul4_1_m24to21 +{ + Zt.B = SVE_ld3b(Zt.B, Ztt.B, Zttt.B, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m24to21); +} + +# ld3b_z_p_br.xml: LD3B (scalar plus scalar) variant SVE +# PATTERN xa440c000/mask=xffe0e000 + +:ld3b "{"^Zt.B, Ztt.B, Zttt.B^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b10 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.B & Zttt.B & Zt.B & Rn_GPR64xsp & Pg3_z & Rm_GPR64 +{ + Zt.B = SVE_ld3b(Zt.B, Ztt.B, Zttt.B, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld3d_z_p_bi.xml: LD3D (scalar plus immediate) variant SVE +# PATTERN xa5c0e000/mask=xfff0e000 + +:ld3d "{"^Zt.D, Ztt.D, Zttt.D^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m24to21] +is sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b10 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.D & Zttt.D & Zt.D & Rn_GPR64xsp & Pg3_z & sve_mul4_1_m24to21 +{ + Zt.D = SVE_ld3d(Zt.D, Ztt.D, Zttt.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m24to21); +} + +# ld3d_z_p_br.xml: LD3D (scalar plus scalar) variant SVE +# PATTERN xa5c0c000/mask=xffe0e000 + +:ld3d "{"^Zt.D, Ztt.D, Zttt.D^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #3"] +is sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b10 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.D & Zttt.D & Zt.D & Rn_GPR64xsp & Pg3_z & Rm_GPR64 +{ + Zt.D = SVE_ld3d(Zt.D, Ztt.D, Zttt.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld3h_z_p_bi.xml: LD3H (scalar plus immediate) variant SVE +# PATTERN xa4c0e000/mask=xfff0e000 + +:ld3h "{"^Zt.H, Ztt.H, Zttt.H^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m24to21] +is sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b10 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.H & Zttt.H & Zt.H & Rn_GPR64xsp & Pg3_z & sve_mul4_1_m24to21 +{ + Zt.H = SVE_ld3h(Zt.H, Ztt.H, Zttt.H, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m24to21); +} + +# ld3h_z_p_br.xml: LD3H (scalar plus scalar) variant SVE +# PATTERN xa4c0c000/mask=xffe0e000 + +:ld3h "{"^Zt.H, Ztt.H, Zttt.H^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #1"] +is sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b10 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.H & Zttt.H & Zt.H & Rn_GPR64xsp & Pg3_z & Rm_GPR64 +{ + Zt.H = SVE_ld3h(Zt.H, Ztt.H, Zttt.H, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld3w_z_p_bi.xml: LD3W (scalar plus immediate) variant SVE +# PATTERN xa540e000/mask=xfff0e000 + +:ld3w "{"^Zt.S, Ztt.S, Zttt.S^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m24to21] +is sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b10 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.S & Zt.S & Zttt.S & Rn_GPR64xsp & Pg3_z & sve_mul4_1_m24to21 +{ + Zt.S = SVE_ld3w(Zt.S, Ztt.S, Zttt.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m24to21); +} + +# ld3w_z_p_br.xml: LD3W (scalar plus scalar) variant SVE +# PATTERN xa540c000/mask=xffe0e000 + +:ld3w "{"^Zt.S, Ztt.S, Zttt.S^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #2"] +is sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b10 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.S & Zt.S & Zttt.S & Rn_GPR64xsp & Pg3_z & Rm_GPR64 +{ + Zt.S = SVE_ld3w(Zt.S, Ztt.S, Zttt.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld4b_z_p_bi.xml: LD4B (scalar plus immediate) variant SVE +# PATTERN xa460e000/mask=xfff0e000 + +:ld4b "{"^Zt.B, Ztt.B, Zttt.B, Ztttt.B^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m32to28] +is sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b11 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.B & Zttt.B & Zt.B & Ztttt.B & Rn_GPR64xsp & Pg3_z & sve_mul4_1_m32to28 +{ + Zt.B = SVE_ld4b(Zt.B, Ztt.B, Zttt.B, Ztttt.B, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m32to28); +} + +# ld4b_z_p_br.xml: LD4B (scalar plus scalar) variant SVE +# PATTERN xa460c000/mask=xffe0e000 + +:ld4b "{"^Zt.B, Ztt.B, Zttt.B, Ztttt.B^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b11 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.B & Zttt.B & Zt.B & Ztttt.B & Rn_GPR64xsp & Pg3_z & Rm_GPR64 +{ + Zt.B = SVE_ld4b(Zt.B, Ztt.B, Zttt.B, Ztttt.B, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld4d_z_p_bi.xml: LD4D (scalar plus immediate) variant SVE +# PATTERN xa5e0e000/mask=xfff0e000 + +:ld4d "{"^Zt.D, Ztt.D, Zttt.D, Ztttt.D^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m32to28] +is sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b11 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.D & Zttt.D & Zt.D & Ztttt.D & Rn_GPR64xsp & Pg3_z & sve_mul4_1_m32to28 +{ + Zt.D = SVE_ld4d(Zt.D, Ztt.D, Zttt.D, Ztttt.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m32to28); +} + +# ld4d_z_p_br.xml: LD4D (scalar plus scalar) variant SVE +# PATTERN xa5e0c000/mask=xffe0e000 + +:ld4d "{"^Zt.D, Ztt.D, Zttt.D, Ztttt.D^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #3"] +is sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b11 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.D & Zttt.D & Zt.D & Ztttt.D & Rn_GPR64xsp & Pg3_z & Rm_GPR64 +{ + Zt.D = SVE_ld4d(Zt.D, Ztt.D, Zttt.D, Ztttt.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld4h_z_p_bi.xml: LD4H (scalar plus immediate) variant SVE +# PATTERN xa4e0e000/mask=xfff0e000 + +:ld4h "{"^Zt.H, Ztt.H, Zttt.H, Ztttt.H^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m32to28] +is sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b11 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.H & Zttt.H & Zt.H & Ztttt.H & Rn_GPR64xsp & Pg3_z & sve_mul4_1_m32to28 +{ + Zt.H = SVE_ld4h(Zt.H, Ztt.H, Zttt.H, Ztttt.H, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m32to28); +} + +# ld4h_z_p_br.xml: LD4H (scalar plus scalar) variant SVE +# PATTERN xa4e0c000/mask=xffe0e000 + +:ld4h "{"^Zt.H, Ztt.H, Zttt.H, Ztttt.H^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #1"] +is sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b11 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.H & Zttt.H & Zt.H & Ztttt.H & Rn_GPR64xsp & Pg3_z & Rm_GPR64 +{ + Zt.H = SVE_ld4h(Zt.H, Ztt.H, Zttt.H, Ztttt.H, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ld4w_z_p_bi.xml: LD4W (scalar plus immediate) variant SVE +# PATTERN xa560e000/mask=xfff0e000 + +:ld4w "{"^Zt.S, Ztt.S, Zttt.S, Ztttt.S^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m32to28] +is sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b11 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.S & Zt.S & Zttt.S & Ztttt.S & Rn_GPR64xsp & Pg3_z & sve_mul4_1_m32to28 +{ + Zt.S = SVE_ld4w(Zt.S, Ztt.S, Zttt.S, Ztttt.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m32to28); +} + +# ld4w_z_p_br.xml: LD4W (scalar plus scalar) variant SVE +# PATTERN xa560c000/mask=xffe0e000 + +:ld4w "{"^Zt.S, Ztt.S, Zttt.S, Ztttt.S^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #2"] +is sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b11 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.S & Zt.S & Zttt.S & Ztttt.S & Rn_GPR64xsp & Pg3_z & Rm_GPR64 +{ + Zt.S = SVE_ld4w(Zt.S, Ztt.S, Zttt.S, Ztttt.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ldff1b_z_p_ai.xml: LDFF1B (vector plus immediate) variant 32-bit element +# PATTERN x8420e000/mask=xffe0e000 + +:ldff1b "{"^Zd.S^"}", Pg3_z, [Zn.S^sve_opt5_1_0to31] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Pg3_z & Zd.S & sve_opt5_1_0to31 +{ + Zd.S = SVE_ldff1b(Zd.S, Pg3_z, Zn.S, sve_opt5_1_0to31); +} + +# ldff1b_z_p_ai.xml: LDFF1B (vector plus immediate) variant 64-bit element +# PATTERN xc420e000/mask=xffe0e000 + +:ldff1b "{"^Zd.D^"}", Pg3_z, [Zn.D^sve_opt5_1_0to31] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to31 +{ + Zd.D = SVE_ldff1b(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to31); +} + +# ldff1b_z_p_br.xml: LDFF1B (scalar plus scalar) variant 8-bit element +# PATTERN xa4006000/mask=xffe0e000 + +:ldff1b "{"^Zd.B^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1010010 & sve_b_2224=0b000 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.B & Rm_GPR64 +{ + Zd.B = SVE_ldff1b(Zd.B, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ldff1b_z_p_br.xml: LDFF1B (scalar plus scalar) variant 16-bit element +# PATTERN xa4206000/mask=xffe0e000 + +:ldff1b "{"^Zd.H^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1010010 & sve_b_2224=0b000 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & Rm_GPR64 +{ + Zd.H = SVE_ldff1b(Zd.H, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ldff1b_z_p_br.xml: LDFF1B (scalar plus scalar) variant 32-bit element +# PATTERN xa4406000/mask=xffe0e000 + +:ldff1b "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1010010 & sve_b_2224=0b001 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & Rm_GPR64 +{ + Zd.S = SVE_ldff1b(Zd.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ldff1b_z_p_br.xml: LDFF1B (scalar plus scalar) variant 64-bit element +# PATTERN xa4606000/mask=xffe0e000 + +:ldff1b "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1010010 & sve_b_2224=0b001 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64 +{ + Zd.D = SVE_ldff1b(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ldff1b_z_p_bz.xml: LDFF1B (scalar plus vector) variant 32-bit unpacked unscaled offset +# PATTERN xc4006000/mask=xffa0e000 + +:ldff1b "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod +{ + Zd.D = SVE_ldff1b(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# ldff1b_z_p_bz.xml: LDFF1B (scalar plus vector) variant 32-bit unscaled offset +# PATTERN x84006000/mask=xffa0e000 + +:ldff1b "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod +{ + Zd.S = SVE_ldff1b(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# ldff1b_z_p_bz.xml: LDFF1B (scalar plus vector) variant 64-bit unscaled offset +# PATTERN xc440e000/mask=xffe0e000 + +:ldff1b "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D +{ + Zd.D = SVE_ldff1b(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D); +} + +# ldff1d_z_p_ai.xml: LDFF1D (vector plus immediate) variant SVE +# PATTERN xc5a0e000/mask=xffe0e000 + +:ldff1d "{"^Zd.D^"}", Pg3_z, [Zn.D^sve_opt5_1_0to248] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to248 +{ + Zd.D = SVE_ldff1d(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to248); +} + +# ldff1d_z_p_br.xml: LDFF1D (scalar plus scalar) variant SVE +# PATTERN xa5e06000/mask=xffe0e000 + +:ldff1d "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #3"] +is sve_b_2531=0b1010010 & sve_b_2224=0b111 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64 +{ + Zd.D = SVE_ldff1d(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ldff1d_z_p_bz.xml: LDFF1D (scalar plus vector) variant 32-bit unpacked scaled offset +# PATTERN xc5a06000/mask=xffa0e000 + +:ldff1d "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod^" #3"] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=1 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod +{ + Zd.D = SVE_ldff1d(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# ldff1d_z_p_bz.xml: LDFF1D (scalar plus vector) variant 32-bit unpacked unscaled offset +# PATTERN xc5806000/mask=xffa0e000 + +:ldff1d "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=1 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod +{ + Zd.D = SVE_ldff1d(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# ldff1d_z_p_bz.xml: LDFF1D (scalar plus vector) variant 64-bit scaled offset +# PATTERN xc5e0e000/mask=xffe0e000 + +:ldff1d "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, "lsl #3"] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b11 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D +{ + Zd.D = SVE_ldff1d(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D); +} + +# ldff1d_z_p_bz.xml: LDFF1D (scalar plus vector) variant 64-bit unscaled offset +# PATTERN xc5c0e000/mask=xffe0e000 + +:ldff1d "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D +{ + Zd.D = SVE_ldff1d(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D); +} + +# ldff1h_z_p_ai.xml: LDFF1H (vector plus immediate) variant 32-bit element +# PATTERN x84a0e000/mask=xffe0e000 + +:ldff1h "{"^Zd.S^"}", Pg3_z, [Zn.S^sve_opt5_1_0to62] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Pg3_z & Zd.S & sve_opt5_1_0to62 +{ + Zd.S = SVE_ldff1h(Zd.S, Pg3_z, Zn.S, sve_opt5_1_0to62); +} + +# ldff1h_z_p_ai.xml: LDFF1H (vector plus immediate) variant 64-bit element +# PATTERN xc4a0e000/mask=xffe0e000 + +:ldff1h "{"^Zd.D^"}", Pg3_z, [Zn.D^sve_opt5_1_0to62] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to62 +{ + Zd.D = SVE_ldff1h(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to62); +} + +# ldff1h_z_p_br.xml: LDFF1H (scalar plus scalar) variant 16-bit element +# PATTERN xa4a06000/mask=xffe0e000 + +:ldff1h "{"^Zd.H^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #1"] +is sve_b_2531=0b1010010 & sve_b_2224=0b010 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & Rm_GPR64 +{ + Zd.H = SVE_ldff1h(Zd.H, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ldff1h_z_p_br.xml: LDFF1H (scalar plus scalar) variant 32-bit element +# PATTERN xa4c06000/mask=xffe0e000 + +:ldff1h "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #1"] +is sve_b_2531=0b1010010 & sve_b_2224=0b011 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & Rm_GPR64 +{ + Zd.S = SVE_ldff1h(Zd.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ldff1h_z_p_br.xml: LDFF1H (scalar plus scalar) variant 64-bit element +# PATTERN xa4e06000/mask=xffe0e000 + +:ldff1h "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #1"] +is sve_b_2531=0b1010010 & sve_b_2224=0b011 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64 +{ + Zd.D = SVE_ldff1h(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ldff1h_z_p_bz.xml: LDFF1H (scalar plus vector) variant 32-bit scaled offset +# PATTERN x84a06000/mask=xffa0e000 + +:ldff1h "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod^" #1"] +is sve_b_2331=0b100001001 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod +{ + Zd.S = SVE_ldff1h(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# ldff1h_z_p_bz.xml: LDFF1H (scalar plus vector) variant 32-bit unpacked scaled offset +# PATTERN xc4a06000/mask=xffa0e000 + +:ldff1h "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod^" #1"] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod +{ + Zd.D = SVE_ldff1h(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# ldff1h_z_p_bz.xml: LDFF1H (scalar plus vector) variant 32-bit unpacked unscaled offset +# PATTERN xc4806000/mask=xffa0e000 + +:ldff1h "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod +{ + Zd.D = SVE_ldff1h(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# ldff1h_z_p_bz.xml: LDFF1H (scalar plus vector) variant 32-bit unscaled offset +# PATTERN x84806000/mask=xffa0e000 + +:ldff1h "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod +{ + Zd.S = SVE_ldff1h(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# ldff1h_z_p_bz.xml: LDFF1H (scalar plus vector) variant 64-bit scaled offset +# PATTERN xc4e0e000/mask=xffe0e000 + +:ldff1h "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, "lsl #1"] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b11 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D +{ + Zd.D = SVE_ldff1h(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D); +} + +# ldff1h_z_p_bz.xml: LDFF1H (scalar plus vector) variant 64-bit unscaled offset +# PATTERN xc4c0e000/mask=xffe0e000 + +:ldff1h "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D +{ + Zd.D = SVE_ldff1h(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D); +} + +# ldff1sb_z_p_ai.xml: LDFF1SB (vector plus immediate) variant 32-bit element +# PATTERN x8420a000/mask=xffe0e000 + +:ldff1sb "{"^Zd.S^"}", Pg3_z, [Zn.S^sve_opt5_1_0to31] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Pg3_z & Zd.S & sve_opt5_1_0to31 +{ + Zd.S = SVE_ldff1sb(Zd.S, Pg3_z, Zn.S, sve_opt5_1_0to31); +} + +# ldff1sb_z_p_ai.xml: LDFF1SB (vector plus immediate) variant 64-bit element +# PATTERN xc420a000/mask=xffe0e000 + +:ldff1sb "{"^Zd.D^"}", Pg3_z, [Zn.D^sve_opt5_1_0to31] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to31 +{ + Zd.D = SVE_ldff1sb(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to31); +} + +# ldff1sb_z_p_br.xml: LDFF1SB (scalar plus scalar) variant 16-bit element +# PATTERN xa5c06000/mask=xffe0e000 + +:ldff1sb "{"^Zd.H^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1010010 & sve_b_2224=0b111 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & Rm_GPR64 +{ + Zd.H = SVE_ldff1sb(Zd.H, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ldff1sb_z_p_br.xml: LDFF1SB (scalar plus scalar) variant 32-bit element +# PATTERN xa5a06000/mask=xffe0e000 + +:ldff1sb "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1010010 & sve_b_2224=0b110 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & Rm_GPR64 +{ + Zd.S = SVE_ldff1sb(Zd.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ldff1sb_z_p_br.xml: LDFF1SB (scalar plus scalar) variant 64-bit element +# PATTERN xa5806000/mask=xffe0e000 + +:ldff1sb "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1010010 & sve_b_2224=0b110 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64 +{ + Zd.D = SVE_ldff1sb(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ldff1sb_z_p_bz.xml: LDFF1SB (scalar plus vector) variant 32-bit unpacked unscaled offset +# PATTERN xc4002000/mask=xffa0e000 + +:ldff1sb "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod +{ + Zd.D = SVE_ldff1sb(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# ldff1sb_z_p_bz.xml: LDFF1SB (scalar plus vector) variant 32-bit unscaled offset +# PATTERN x84002000/mask=xffa0e000 + +:ldff1sb "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod +{ + Zd.S = SVE_ldff1sb(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# ldff1sb_z_p_bz.xml: LDFF1SB (scalar plus vector) variant 64-bit unscaled offset +# PATTERN xc440a000/mask=xffe0e000 + +:ldff1sb "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D +{ + Zd.D = SVE_ldff1sb(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D); +} + +# ldff1sh_z_p_ai.xml: LDFF1SH (vector plus immediate) variant 32-bit element +# PATTERN x84a0a000/mask=xffe0e000 + +:ldff1sh "{"^Zd.S^"}", Pg3_z, [Zn.S^sve_opt5_1_0to62] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Pg3_z & Zd.S & sve_opt5_1_0to62 +{ + Zd.S = SVE_ldff1sh(Zd.S, Pg3_z, Zn.S, sve_opt5_1_0to62); +} + +# ldff1sh_z_p_ai.xml: LDFF1SH (vector plus immediate) variant 64-bit element +# PATTERN xc4a0a000/mask=xffe0e000 + +:ldff1sh "{"^Zd.D^"}", Pg3_z, [Zn.D^sve_opt5_1_0to62] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to62 +{ + Zd.D = SVE_ldff1sh(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to62); +} + +# ldff1sh_z_p_br.xml: LDFF1SH (scalar plus scalar) variant 32-bit element +# PATTERN xa5206000/mask=xffe0e000 + +:ldff1sh "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #1"] +is sve_b_2531=0b1010010 & sve_b_2224=0b100 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & Rm_GPR64 +{ + Zd.S = SVE_ldff1sh(Zd.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ldff1sh_z_p_br.xml: LDFF1SH (scalar plus scalar) variant 64-bit element +# PATTERN xa5006000/mask=xffe0e000 + +:ldff1sh "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #1"] +is sve_b_2531=0b1010010 & sve_b_2224=0b100 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64 +{ + Zd.D = SVE_ldff1sh(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ldff1sh_z_p_bz.xml: LDFF1SH (scalar plus vector) variant 32-bit scaled offset +# PATTERN x84a02000/mask=xffa0e000 + +:ldff1sh "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod^" #1"] +is sve_b_2331=0b100001001 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod +{ + Zd.S = SVE_ldff1sh(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# ldff1sh_z_p_bz.xml: LDFF1SH (scalar plus vector) variant 32-bit unpacked scaled offset +# PATTERN xc4a02000/mask=xffa0e000 + +:ldff1sh "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod^" #1"] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod +{ + Zd.D = SVE_ldff1sh(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# ldff1sh_z_p_bz.xml: LDFF1SH (scalar plus vector) variant 32-bit unpacked unscaled offset +# PATTERN xc4802000/mask=xffa0e000 + +:ldff1sh "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod +{ + Zd.D = SVE_ldff1sh(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# ldff1sh_z_p_bz.xml: LDFF1SH (scalar plus vector) variant 32-bit unscaled offset +# PATTERN x84802000/mask=xffa0e000 + +:ldff1sh "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod +{ + Zd.S = SVE_ldff1sh(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# ldff1sh_z_p_bz.xml: LDFF1SH (scalar plus vector) variant 64-bit scaled offset +# PATTERN xc4e0a000/mask=xffe0e000 + +:ldff1sh "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, "lsl #1"] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b11 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D +{ + Zd.D = SVE_ldff1sh(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D); +} + +# ldff1sh_z_p_bz.xml: LDFF1SH (scalar plus vector) variant 64-bit unscaled offset +# PATTERN xc4c0a000/mask=xffe0e000 + +:ldff1sh "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D +{ + Zd.D = SVE_ldff1sh(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D); +} + +# ldff1sw_z_p_ai.xml: LDFF1SW (vector plus immediate) variant SVE +# PATTERN xc520a000/mask=xffe0e000 + +:ldff1sw "{"^Zd.D^"}", Pg3_z, [Zn.D^sve_opt5_1_0to124] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to124 +{ + Zd.D = SVE_ldff1sw(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to124); +} + +# ldff1sw_z_p_br.xml: LDFF1SW (scalar plus scalar) variant SVE +# PATTERN xa4806000/mask=xffe0e000 + +:ldff1sw "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #2"] +is sve_b_2531=0b1010010 & sve_b_2224=0b010 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64 +{ + Zd.D = SVE_ldff1sw(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ldff1sw_z_p_bz.xml: LDFF1SW (scalar plus vector) variant 32-bit unpacked scaled offset +# PATTERN xc5202000/mask=xffa0e000 + +:ldff1sw "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod^" #2"] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod +{ + Zd.D = SVE_ldff1sw(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# ldff1sw_z_p_bz.xml: LDFF1SW (scalar plus vector) variant 32-bit unpacked unscaled offset +# PATTERN xc5002000/mask=xffa0e000 + +:ldff1sw "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod +{ + Zd.D = SVE_ldff1sw(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# ldff1sw_z_p_bz.xml: LDFF1SW (scalar plus vector) variant 64-bit scaled offset +# PATTERN xc560a000/mask=xffe0e000 + +:ldff1sw "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, "lsl #2"] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b11 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D +{ + Zd.D = SVE_ldff1sw(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D); +} + +# ldff1sw_z_p_bz.xml: LDFF1SW (scalar plus vector) variant 64-bit unscaled offset +# PATTERN xc540a000/mask=xffe0e000 + +:ldff1sw "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D +{ + Zd.D = SVE_ldff1sw(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D); +} + +# ldff1w_z_p_ai.xml: LDFF1W (vector plus immediate) variant 32-bit element +# PATTERN x8520e000/mask=xffe0e000 + +:ldff1w "{"^Zd.S^"}", Pg3_z, [Zn.S^sve_opt5_1_0to124] +is sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Pg3_z & Zd.S & sve_opt5_1_0to124 +{ + Zd.S = SVE_ldff1w(Zd.S, Pg3_z, Zn.S, sve_opt5_1_0to124); +} + +# ldff1w_z_p_ai.xml: LDFF1W (vector plus immediate) variant 64-bit element +# PATTERN xc520e000/mask=xffe0e000 + +:ldff1w "{"^Zd.D^"}", Pg3_z, [Zn.D^sve_opt5_1_0to124] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b01 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Pg3_z & Zd.D & sve_opt5_1_0to124 +{ + Zd.D = SVE_ldff1w(Zd.D, Pg3_z, Zn.D, sve_opt5_1_0to124); +} + +# ldff1w_z_p_br.xml: LDFF1W (scalar plus scalar) variant 32-bit element +# PATTERN xa5406000/mask=xffe0e000 + +:ldff1w "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #2"] +is sve_b_2531=0b1010010 & sve_b_2224=0b101 & sve_b_21=0 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & Rm_GPR64 +{ + Zd.S = SVE_ldff1w(Zd.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ldff1w_z_p_br.xml: LDFF1W (scalar plus scalar) variant 64-bit element +# PATTERN xa5606000/mask=xffe0e000 + +:ldff1w "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #2"] +is sve_b_2531=0b1010010 & sve_b_2224=0b101 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64 +{ + Zd.D = SVE_ldff1w(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ldff1w_z_p_bz.xml: LDFF1W (scalar plus vector) variant 32-bit scaled offset +# PATTERN x85206000/mask=xffa0e000 + +:ldff1w "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod^" #2"] +is sve_b_2331=0b100001010 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod +{ + Zd.S = SVE_ldff1w(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# ldff1w_z_p_bz.xml: LDFF1W (scalar plus vector) variant 32-bit unpacked scaled offset +# PATTERN xc5206000/mask=xffa0e000 + +:ldff1w "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod^" #2"] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod +{ + Zd.D = SVE_ldff1w(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# ldff1w_z_p_bz.xml: LDFF1W (scalar plus vector) variant 32-bit unpacked unscaled offset +# PATTERN xc5006000/mask=xffa0e000 + +:ldff1w "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, sve_mod] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D & sve_mod +{ + Zd.D = SVE_ldff1w(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# ldff1w_z_p_bz.xml: LDFF1W (scalar plus vector) variant 32-bit unscaled offset +# PATTERN x85006000/mask=xffa0e000 + +:ldff1w "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Zm.S, sve_mod] +is sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=0 & sve_xs_22 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.S & Zd.S & sve_mod +{ + Zd.S = SVE_ldff1w(Zd.S, Pg3_z, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# ldff1w_z_p_bz.xml: LDFF1W (scalar plus vector) variant 64-bit scaled offset +# PATTERN xc560e000/mask=xffe0e000 + +:ldff1w "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D, "lsl #2"] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b11 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D +{ + Zd.D = SVE_ldff1w(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D); +} + +# ldff1w_z_p_bz.xml: LDFF1W (scalar plus vector) variant 64-bit unscaled offset +# PATTERN xc540e000/mask=xffe0e000 + +:ldff1w "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Zm.D] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zm.D & Zd.D +{ + Zd.D = SVE_ldff1w(Zd.D, Pg3_z, Rn_GPR64xsp, Zm.D); +} + +# ldnf1b_z_p_bi.xml: LDNF1B variant 8-bit element +# PATTERN xa410a000/mask=xfff0e000 + +:ldnf1b "{"^Zd.B^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b000 & sve_b_21=0 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.B & sve_mul4_1_m8to7 +{ + Zd.B = SVE_ldnf1b(Zd.B, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ldnf1b_z_p_bi.xml: LDNF1B variant 16-bit element +# PATTERN xa430a000/mask=xfff0e000 + +:ldnf1b "{"^Zd.H^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b000 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & sve_mul4_1_m8to7 +{ + Zd.H = SVE_ldnf1b(Zd.H, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ldnf1b_z_p_bi.xml: LDNF1B variant 32-bit element +# PATTERN xa450a000/mask=xfff0e000 + +:ldnf1b "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b001 & sve_b_21=0 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_mul4_1_m8to7 +{ + Zd.S = SVE_ldnf1b(Zd.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ldnf1b_z_p_bi.xml: LDNF1B variant 64-bit element +# PATTERN xa470a000/mask=xfff0e000 + +:ldnf1b "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b001 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7 +{ + Zd.D = SVE_ldnf1b(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ldnf1d_z_p_bi.xml: LDNF1D variant SVE +# PATTERN xa5f0a000/mask=xfff0e000 + +:ldnf1d "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b111 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7 +{ + Zd.D = SVE_ldnf1d(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ldnf1h_z_p_bi.xml: LDNF1H variant 16-bit element +# PATTERN xa4b0a000/mask=xfff0e000 + +:ldnf1h "{"^Zd.H^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b010 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & sve_mul4_1_m8to7 +{ + Zd.H = SVE_ldnf1h(Zd.H, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ldnf1h_z_p_bi.xml: LDNF1H variant 32-bit element +# PATTERN xa4d0a000/mask=xfff0e000 + +:ldnf1h "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b011 & sve_b_21=0 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_mul4_1_m8to7 +{ + Zd.S = SVE_ldnf1h(Zd.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ldnf1h_z_p_bi.xml: LDNF1H variant 64-bit element +# PATTERN xa4f0a000/mask=xfff0e000 + +:ldnf1h "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b011 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7 +{ + Zd.D = SVE_ldnf1h(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ldnf1sb_z_p_bi.xml: LDNF1SB variant 16-bit element +# PATTERN xa5d0a000/mask=xfff0e000 + +:ldnf1sb "{"^Zd.H^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b111 & sve_b_21=0 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & sve_mul4_1_m8to7 +{ + Zd.H = SVE_ldnf1sb(Zd.H, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ldnf1sb_z_p_bi.xml: LDNF1SB variant 32-bit element +# PATTERN xa5b0a000/mask=xfff0e000 + +:ldnf1sb "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b110 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_mul4_1_m8to7 +{ + Zd.S = SVE_ldnf1sb(Zd.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ldnf1sb_z_p_bi.xml: LDNF1SB variant 64-bit element +# PATTERN xa590a000/mask=xfff0e000 + +:ldnf1sb "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b110 & sve_b_21=0 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7 +{ + Zd.D = SVE_ldnf1sb(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ldnf1sh_z_p_bi.xml: LDNF1SH variant 32-bit element +# PATTERN xa530a000/mask=xfff0e000 + +:ldnf1sh "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b100 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_mul4_1_m8to7 +{ + Zd.S = SVE_ldnf1sh(Zd.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ldnf1sh_z_p_bi.xml: LDNF1SH variant 64-bit element +# PATTERN xa510a000/mask=xfff0e000 + +:ldnf1sh "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b100 & sve_b_21=0 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7 +{ + Zd.D = SVE_ldnf1sh(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ldnf1sw_z_p_bi.xml: LDNF1SW variant SVE +# PATTERN xa490a000/mask=xfff0e000 + +:ldnf1sw "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b010 & sve_b_21=0 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7 +{ + Zd.D = SVE_ldnf1sw(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ldnf1w_z_p_bi.xml: LDNF1W variant 32-bit element +# PATTERN xa550a000/mask=xfff0e000 + +:ldnf1w "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b101 & sve_b_21=0 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_mul4_1_m8to7 +{ + Zd.S = SVE_ldnf1w(Zd.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ldnf1w_z_p_bi.xml: LDNF1W variant 64-bit element +# PATTERN xa570a000/mask=xfff0e000 + +:ldnf1w "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_2224=0b101 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7 +{ + Zd.D = SVE_ldnf1w(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ldnt1b_z_p_bi.xml: LDNT1B (scalar plus immediate) variant SVE +# PATTERN xa400e000/mask=xfff0e000 + +:ldnt1b "{"^Zd.B^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=0 & sve_b_2022=0b000 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.B & sve_mul4_1_m8to7 +{ + Zd.B = SVE_ldnt1b(Zd.B, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ldnt1b_z_p_br.xml: LDNT1B (scalar plus scalar) variant SVE +# PATTERN xa400c000/mask=xffe0e000 + +:ldnt1b "{"^Zd.B^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.B & Rm_GPR64 +{ + Zd.B = SVE_ldnt1b(Zd.B, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ldnt1d_z_p_bi.xml: LDNT1D (scalar plus immediate) variant SVE +# PATTERN xa580e000/mask=xfff0e000 + +:ldnt1d "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=1 & sve_b_2022=0b000 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & sve_mul4_1_m8to7 +{ + Zd.D = SVE_ldnt1d(Zd.D, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ldnt1d_z_p_br.xml: LDNT1D (scalar plus scalar) variant SVE +# PATTERN xa580c000/mask=xffe0e000 + +:ldnt1d "{"^Zd.D^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #3"] +is sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.D & Rm_GPR64 +{ + Zd.D = SVE_ldnt1d(Zd.D, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ldnt1h_z_p_bi.xml: LDNT1H (scalar plus immediate) variant SVE +# PATTERN xa480e000/mask=xfff0e000 + +:ldnt1h "{"^Zd.H^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=1 & sve_b_2022=0b000 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & sve_mul4_1_m8to7 +{ + Zd.H = SVE_ldnt1h(Zd.H, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ldnt1h_z_p_br.xml: LDNT1H (scalar plus scalar) variant SVE +# PATTERN xa480c000/mask=xffe0e000 + +:ldnt1h "{"^Zd.H^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #1"] +is sve_b_2531=0b1010010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.H & Rm_GPR64 +{ + Zd.H = SVE_ldnt1h(Zd.H, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ldnt1w_z_p_bi.xml: LDNT1W (scalar plus immediate) variant SVE +# PATTERN xa500e000/mask=xfff0e000 + +:ldnt1w "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=0 & sve_b_2022=0b000 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & sve_mul4_1_m8to7 +{ + Zd.S = SVE_ldnt1w(Zd.S, Pg3_z, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# ldnt1w_z_p_br.xml: LDNT1W (scalar plus scalar) variant SVE +# PATTERN xa500c000/mask=xffe0e000 + +:ldnt1w "{"^Zd.S^"}", Pg3_z, [Rn_GPR64xsp, Rm_GPR64, "lsl #2"] +is sve_b_2531=0b1010010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Pg3_z & Zd.S & Rm_GPR64 +{ + Zd.S = SVE_ldnt1w(Zd.S, Pg3_z, Rn_GPR64xsp, Rm_GPR64); +} + +# ldr_p_bi.xml: LDR (predicate) variant SVE +# PATTERN x85800000/mask=xffc0e010 + +:ldr Pd, [Rn_GPR64xsp^sve_mul9_2_m256to255] +is sve_b_2231=0b1000010110 & sve_imm9h_1621 & sve_b_1315=0b000 & sve_imm9l_1012 & sve_rn_0509 & sve_b_04=0 & sve_pt_0003 & Rn_GPR64xsp & sve_mul9_2_m256to255 & Pd +{ + Pd = SVE_ldr(Pd, Rn_GPR64xsp, sve_mul9_2_m256to255); +} + +# ldr_z_bi.xml: LDR (vector) variant SVE +# PATTERN x85804000/mask=xffc0e000 + +:ldr Zd, [Rn_GPR64xsp^sve_mul9_2_m256to255] +is sve_b_2231=0b1000010110 & sve_imm9h_1621 & sve_b_1315=0b010 & sve_imm9l_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & sve_mul9_2_m256to255 & Zd +{ + Zd = SVE_ldr(Zd, Rn_GPR64xsp, sve_mul9_2_m256to255); +} + +# lsl_z_p_zi.xml: LSL (immediate, predicated) variant SVE +# PATTERN x04038000/mask=xff3fe000 + +:lsl Zd.T_tszh, Pg3_m, Zd.T_tszh_2, "#"^sve_imm_shift +is sve_b_2431=0b00000100 & sve_tszh_2223 & sve_b_1921=0b000 & sve_b_1718=0b01 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_tszl_0809 & sve_imm3_0507 & sve_zdn_0004 & sve_imm_shift & Zd.T_tszh & Zd.T_tszh_2 & Pg3_m +{ + Zd.T_tszh = SVE_lsl(Zd.T_tszh, Pg3_m, Zd.T_tszh_2, sve_imm_shift:1); +} + +# lsl_z_p_zw.xml: LSL (wide elements, predicated) variant SVE +# PATTERN x041b8000/mask=xff3fe000 + +:lsl Zd.T, Pg3_m, Zd.T_2, Zn.D +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Pg3_m & Zn.D +{ + Zd.T = SVE_lsl(Zd.T, Pg3_m, Zd.T_2, Zn.D); +} + +# lsl_z_p_zz.xml: LSL (vectors) variant SVE +# PATTERN x04138000/mask=xff3fe000 + +:lsl Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b01 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_lsl(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# lsl_z_zi.xml: LSL (immediate, unpredicated) variant SVE +# PATTERN x04209c00/mask=xff20fc00 + +:lsl Zd.T_tszh, Zn.T_tszh, "#"^sve_imm_shift +is sve_b_2431=0b00000100 & sve_tszh_2223 & sve_b_21=1 & sve_tszl_1920 & sve_imm3_1618 & sve_b_1215=0b1001 & sve_b_11=1 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & sve_imm_shift & Zd.T_tszh & Zn.T_tszh +{ + Zd.T_tszh = SVE_lsl(Zd.T_tszh, Zn.T_tszh, sve_imm_shift:1); +} + +# lsl_z_zw.xml: LSL (wide elements, unpredicated) variant SVE +# PATTERN x04208c00/mask=xff20fc00 + +:lsl Zd.T, Zn.T, Zm.D +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1215=0b1000 & sve_b_11=1 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Zm.D +{ + Zd.T = SVE_lsl(Zd.T, Zn.T, Zm.D); +} + +# lslr_z_p_zz.xml: LSLR variant SVE +# PATTERN x04178000/mask=xff3fe000 + +:lslr Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_lslr(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# lsr_z_p_zi.xml: LSR (immediate, predicated) variant SVE +# PATTERN x04018000/mask=xff3fe000 + +:lsr Zd.T_tszh, Pg3_m, Zd.T_tszh_2, "#"^sve_imm_shift +is sve_b_2431=0b00000100 & sve_tszh_2223 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_tszl_0809 & sve_imm3_0507 & sve_zdn_0004 & sve_imm_shift & Zd.T_tszh & Zd.T_tszh_2 & Pg3_m +{ + Zd.T_tszh = SVE_lsr(Zd.T_tszh, Pg3_m, Zd.T_tszh_2, sve_imm_shift:1); +} + +# lsr_z_p_zw.xml: LSR (wide elements, predicated) variant SVE +# PATTERN x04198000/mask=xff3fe000 + +:lsr Zd.T, Pg3_m, Zd.T_2, Zn.D +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Pg3_m & Zn.D +{ + Zd.T = SVE_lsr(Zd.T, Pg3_m, Zd.T_2, Zn.D); +} + +# lsr_z_p_zz.xml: LSR (vectors) variant SVE +# PATTERN x04118000/mask=xff3fe000 + +:lsr Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_lsr(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# lsr_z_zi.xml: LSR (immediate, unpredicated) variant SVE +# PATTERN x04209400/mask=xff20fc00 + +:lsr Zd.T_tszh, Zn.T_tszh, "#"^sve_imm_shift +is sve_b_2431=0b00000100 & sve_tszh_2223 & sve_b_21=1 & sve_tszl_1920 & sve_imm3_1618 & sve_b_1215=0b1001 & sve_b_11=0 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & sve_imm_shift & Zd.T_tszh & Zn.T_tszh +{ + Zd.T_tszh = SVE_lsr(Zd.T_tszh, Zn.T_tszh, sve_imm_shift:1); +} + +# lsr_z_zw.xml: LSR (wide elements, unpredicated) variant SVE +# PATTERN x04208400/mask=xff20fc00 + +:lsr Zd.T, Zn.T, Zm.D +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1215=0b1000 & sve_b_11=0 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Zm.D +{ + Zd.T = SVE_lsr(Zd.T, Zn.T, Zm.D); +} + +# lsrr_z_p_zz.xml: LSRR variant SVE +# PATTERN x04158000/mask=xff3fe000 + +:lsrr Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b10 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_lsrr(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# mad_z_p_zzz.xml: MAD variant SVE +# PATTERN x0400c000/mask=xff20e000 + +:mad Zd.T, Pg3_m, Zm.T, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_1415=0b11 & sve_b_13=0 & sve_pg_1012 & sve_za_0509 & sve_zdn_0004 & Zd.T & Zm.T & Zn.T & Pg3_m +{ + Zd.T = SVE_mad(Zd.T, Pg3_m, Zm.T, Zn.T); +} + +# mla_z_p_zzz.xml: MLA variant SVE +# PATTERN x04004000/mask=xff20e000 + +:mla Zd.T, Pg3_m, Zn.T, Zm.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_1415=0b01 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zda_0004 & Zd.T & Zm.T & Zn.T & Pg3_m +{ + Zd.T = SVE_mla(Zd.T, Pg3_m, Zn.T, Zm.T); +} + +# mls_z_p_zzz.xml: MLS variant SVE +# PATTERN x04006000/mask=xff20e000 + +:mls Zd.T, Pg3_m, Zn.T, Zm.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_1415=0b01 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zda_0004 & Zd.T & Zm.T & Zn.T & Pg3_m +{ + Zd.T = SVE_mls(Zd.T, Pg3_m, Zn.T, Zm.T); +} + +# mov_and_p_p_pp.xml: MOV (predicate, predicated, zeroing) variant Not flag setting +# ALIASEDBY AND .B, /Z, .B, .B if S == '0' && Pn == Pm +# PATTERN x25004000/mask=xfff0c210 + +# SKIPPING mov_and_p_p_pp.xml because x25004000/mask=xfff0c210 has already been defined + +# mov_cpy_z_p_i.xml: MOV (immediate, predicated) variant SVE +# ALIASEDBY CPY ., /, #{, } if Unconditionally +# PATTERN x05100000/mask=xff308000 + +# SKIPPING mov_cpy_z_p_i.xml because x05100000/mask=xff308000 has already been defined + +# mov_cpy_z_p_r.xml: MOV (scalar, predicated) variant SVE +# ALIASEDBY CPY ., /M, if Unconditionally +# PATTERN x0528a000/mask=xff3fe000 + +# SKIPPING mov_cpy_z_p_r.xml because x0528a000/mask=xff3fe000 has already been defined + +# mov_cpy_z_p_v.xml: MOV (SIMD&FP scalar, predicated) variant SVE +# ALIASEDBY CPY ., /M, if Unconditionally +# PATTERN x05208000/mask=xff3fe000 + +# SKIPPING mov_cpy_z_p_v.xml because x05208000/mask=xff3fe000 has already been defined + +# mov_dup_z_i.xml: MOV (immediate, unpredicated) variant SVE +# ALIASEDBY DUP ., #{, } if Unconditionally +# PATTERN x2538c000/mask=xff3fc000 + +# SKIPPING mov_dup_z_i.xml because x2538c000/mask=xff3fc000 has already been defined + +# mov_dup_z_r.xml: MOV (scalar, unpredicated) variant SVE +# ALIASEDBY DUP ., if Unconditionally +# PATTERN x05203800/mask=xff3ffc00 + +# SKIPPING mov_dup_z_r.xml because x05203800/mask=xff3ffc00 has already been defined + +# mov_dup_z_zi.xml: MOV (SIMD&FP scalar, unpredicated) variant SVE +# ALIASEDBY DUP ., .[0] if BitCount(imm2:tsz) == 1 +# ALIASEDBY DUP ., .[] if BitCount(imm2:tsz) > 1 +# PATTERN + +# SKIPPING mov_dup_z_zi.xml because there is a mismatch between the XML asmtemplate(4) and regdiagram(1) + +# mov_dupm_z_i.xml: MOV (bitmask immediate) variant SVE +# ALIASEDBY DUPM ., # if SVEMoveMaskPreferred(imm13) +# PATTERN x05c00000/mask=xfffc0000 + +# SKIPPING mov_dupm_z_i.xml because x05c00000/mask=xfffc0000 has already been defined + +# mov_orr_p_p_pp.xml: MOV (predicate, unpredicated) variant Not flag setting +# ALIASEDBY ORR .B, /Z, .B, .B if S == '0' && Pn == Pm && Pm == Pg +# PATTERN x25804000/mask=xfff0c210 + +# SKIPPING mov_orr_p_p_pp.xml because it is an alias: + +# mov_orr_z_zz.xml: MOV (vector, unpredicated) variant SVE +# ALIASEDBY ORR .D, .D, .D if Zn == Zm +# PATTERN x04603000/mask=xffe0fc00 + +# SKIPPING mov_orr_z_zz.xml because it is an alias: + +# mov_sel_p_p_pp.xml: MOV (predicate, predicated, merging) variant SVE +# ALIASEDBY SEL .B, , .B, .B if Pd == Pm +# PATTERN x25004210/mask=xfff0c210 + +# SKIPPING mov_sel_p_p_pp.xml because it is an alias: + +# mov_sel_z_p_zz.xml: MOV (vector, predicated) variant SVE +# ALIASEDBY SEL ., , ., . if Zd == Zm +# PATTERN x0520c000/mask=xff20c000 + +# SKIPPING mov_sel_z_p_zz.xml because it is an alias: + +# movprfx_z_p_z.xml: MOVPRFX (predicated) variant SVE +# PATTERN x04102000/mask=xff3ee000 + +:movprfx Zd.T, Pg3_zm, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_18=0 & sve_b_17=0 & sve_m_16 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Pg3_zm & Zd.T & Zn.T +{ + Zd.T = SVE_movprfx(Zd.T, Pg3_zm, Zn.T); +} + +# movprfx_z_z.xml: MOVPRFX (unpredicated) variant SVE +# PATTERN x0420bc00/mask=xfffffc00 + +:movprfx Zd, Zn +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_21=1 & sve_b_1720=0b0000 & sve_b_16=0 & sve_b_1015=0b101111 & sve_zn_0509 & sve_zd_0004 & Zn & Zd +{ + Zd = SVE_movprfx(Zd, Zn); +} + +# movs_and_p_p_pp.xml: MOVS (predicated) variant Flag setting +# ALIASEDBY ANDS .B, /Z, .B, .B if S == '1' && Pn == Pm +# PATTERN x25404000/mask=xfff0c210 + +# SKIPPING movs_and_p_p_pp.xml because x25404000/mask=xfff0c210 has already been defined + +# movs_orr_p_p_pp.xml: MOVS (unpredicated) variant Flag setting +# ALIASEDBY ORRS .B, /Z, .B, .B if S == '1' && Pn == Pm && Pm == Pg +# PATTERN x25c04000/mask=xfff0c210 + +# SKIPPING movs_orr_p_p_pp.xml because it is an alias: + +# msb_z_p_zzz.xml: MSB variant SVE +# PATTERN x0400e000/mask=xff20e000 + +:msb Zd.T, Pg3_m, Zm.T, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_1415=0b11 & sve_b_13=1 & sve_pg_1012 & sve_za_0509 & sve_zdn_0004 & Zd.T & Zm.T & Zn.T & Pg3_m +{ + Zd.T = SVE_msb(Zd.T, Pg3_m, Zm.T, Zn.T); +} + +# mul_z_p_zz.xml: MUL (vectors) variant SVE +# PATTERN x04100000/mask=xff3fe000 + +:mul Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_18=0 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_mul(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# mul_z_zi.xml: MUL (immediate) variant SVE +# PATTERN x2530c000/mask=xff3fe000 + +:mul Zd.T, Zd.T_2, "#"^sve_imm8_1_m128to127 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b110 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1415=0b11 & sve_b_13=0 & sve_imm8_0512 & sve_zdn_0004 & Zd.T & Zd.T_2 & sve_imm8_1_m128to127 +{ + Zd.T = SVE_mul(Zd.T, Zd.T_2, sve_imm8_1_m128to127:1); +} + +# nand_p_p_pp.xml: NAND, NANDS variant Flag setting +# PATTERN x25c04210/mask=xfff0c210 + +:nands Pd.B, Pg_z, Pn.B, Pm.B +is sve_b_2431=0b00100101 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=1 & sve_pn_0508 & sve_b_04=1 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B +{ + Pd.B = SVE_nands(Pd.B, Pg_z, Pn.B, Pm.B); +} + +# nand_p_p_pp.xml: NAND, NANDS variant Not flag setting +# PATTERN x25804210/mask=xfff0c210 + +:nand Pd.B, Pg_z, Pn.B, Pm.B +is sve_b_2431=0b00100101 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=1 & sve_pn_0508 & sve_b_04=1 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B +{ + Pd.B = SVE_nand(Pd.B, Pg_z, Pn.B, Pm.B); +} + +# neg_z_p_z.xml: NEG variant SVE +# PATTERN x0417a000/mask=xff3fe000 + +:neg Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_neg(Zd.T, Pg3_m, Zn.T); +} + +# nor_p_p_pp.xml: NOR, NORS variant Flag setting +# PATTERN x25c04200/mask=xfff0c210 + +:nors Pd.B, Pg_z, Pn.B, Pm.B +is sve_b_2431=0b00100101 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=1 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B +{ + Pd.B = SVE_nors(Pd.B, Pg_z, Pn.B, Pm.B); +} + +# nor_p_p_pp.xml: NOR, NORS variant Not flag setting +# PATTERN x25804200/mask=xfff0c210 + +:nor Pd.B, Pg_z, Pn.B, Pm.B +is sve_b_2431=0b00100101 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=1 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B +{ + Pd.B = SVE_nor(Pd.B, Pg_z, Pn.B, Pm.B); +} + +# not_eor_p_p_pp.xml: NOT (predicate) variant Not flag setting +# ALIASEDBY EOR .B, /Z, .B, .B if Pm == Pg +# PATTERN x25004200/mask=xfff0c210 + +# SKIPPING not_eor_p_p_pp.xml because x25004200/mask=xfff0c210 has already been defined + +# not_z_p_z.xml: NOT (vector) variant SVE +# PATTERN x041ea000/mask=xff3fe000 + +:not Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_not(Zd.T, Pg3_m, Zn.T); +} + +# nots_eor_p_p_pp.xml: NOTS variant Flag setting +# ALIASEDBY EORS .B, /Z, .B, .B if Pm == Pg +# PATTERN x25404200/mask=xfff0c210 + +# SKIPPING nots_eor_p_p_pp.xml because x25404200/mask=xfff0c210 has already been defined + +# orn_orr_z_zi.xml: ORN (immediate) variant SVE +# ALIASEDBY ORR ., ., #(- - 1) if Never +# PATTERN x05000000/mask=xfffc0000 + +:orn Zd.T_imm13, Zd.T_imm13_2, "#"^sve_decode_bit_mask +is sve_b_2431=0b00000101 & sve_b_23=0 & sve_b_22=0 & sve_b_1821=0b0000 & sve_imm13_0517 & sve_zdn_0004 & sve_decode_bit_mask & Zd.T_imm13 & Zd.T_imm13_2 +{ + Zd.T_imm13 = SVE_orn(Zd.T_imm13, Zd.T_imm13_2, sve_decode_bit_mask:1); +} + +# orn_p_p_pp.xml: ORN, ORNS (predicates) variant Flag setting +# PATTERN x25c04010/mask=xfff0c210 + +:orns Pd.B, Pg_z, Pn.B, Pm.B +is sve_b_2431=0b00100101 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=1 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B +{ + Pd.B = SVE_orns(Pd.B, Pg_z, Pn.B, Pm.B); +} + +# orn_p_p_pp.xml: ORN, ORNS (predicates) variant Not flag setting +# PATTERN x25804010/mask=xfff0c210 + +:orn Pd.B, Pg_z, Pn.B, Pm.B +is sve_b_2431=0b00100101 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=1 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B +{ + Pd.B = SVE_orn(Pd.B, Pg_z, Pn.B, Pm.B); +} + +# orr_p_p_pp.xml: ORR, ORRS (predicates) variant Flag setting +# PATTERN x25c04000/mask=xfff0c210 + +:orrs Pd.B, Pg_z, Pn.B, Pm.B +is sve_b_2431=0b00100101 & sve_b_23=1 & sve_s_22=1 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B +{ + Pd.B = SVE_orrs(Pd.B, Pg_z, Pn.B, Pm.B); +} + +# orr_p_p_pp.xml: ORR, ORRS (predicates) variant Not flag setting +# PATTERN x25804000/mask=xfff0c210 + +:orr Pd.B, Pg_z, Pn.B, Pm.B +is sve_b_2431=0b00100101 & sve_b_23=1 & sve_s_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B +{ + Pd.B = SVE_orr(Pd.B, Pg_z, Pn.B, Pm.B); +} + +# orr_z_p_zz.xml: ORR (vectors, predicated) variant SVE +# PATTERN x04180000/mask=xff3fe000 + +:orr Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_orr(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# orr_z_zi.xml: ORR (immediate) variant SVE +# PATTERN x05000000/mask=xfffc0000 + +# SKIPPING orr_z_zi.xml because x05000000/mask=xfffc0000 has already been defined + +# orr_z_zz.xml: ORR (vectors, unpredicated) variant SVE +# PATTERN x04603000/mask=xffe0fc00 + +:orr Zd.D, Zn.D, Zm.D +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_21=1 & sve_zm_1620 & sve_b_1015=0b001100 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Zm.D +{ + Zd.D = SVE_orr(Zd.D, Zn.D, Zm.D); +} + +# orv_r_p_z.xml: ORV variant SVE +# PATTERN x04182000/mask=xff3fe000 + +:orv Rd_FPR8, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b00 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3 +{ + Rd_FPR8 = SVE_orv(Rd_FPR8, Pg3, Zn.T); +} + +# orv_r_p_z.xml: ORV variant SVE +# PATTERN x04182000/mask=xff3fe000 + +:orv Rd_FPR32, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b10 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3 +{ + Rd_FPR32 = SVE_orv(Rd_FPR32, Pg3, Zn.T); +} + +# orv_r_p_z.xml: ORV variant SVE +# PATTERN x04182000/mask=xff3fe000 + +:orv Rd_FPR16, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b01 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3 +{ + Rd_FPR16 = SVE_orv(Rd_FPR16, Pg3, Zn.T); +} + +# orv_r_p_z.xml: ORV variant SVE +# PATTERN x04182000/mask=xff3fe000 + +:orv Rd_FPR64, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b11 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3 +{ + Rd_FPR64 = SVE_orv(Rd_FPR64, Pg3, Zn.T); +} + +# pfalse_p.xml: PFALSE variant SVE +# PATTERN x2518e400/mask=xfffffff0 + +:pfalse Pd.B +is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=0 & sve_b_1021=0b011000111001 & sve_b_0409=0b000000 & sve_pd_0003 & Pd.B +{ + Pd.B = SVE_pfalse(Pd.B); +} + +# pfirst_p_p_p.xml: PFIRST variant SVE +# PATTERN x2558c000/mask=xfffffe10 + +:pfirst Pd.B, Pn, Pd.B_2 +is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1021=0b011000110000 & sve_b_09=0 & sve_pg_0508 & sve_b_04=0 & sve_pdn_0003 & Pd.B & Pd.B_2 & Pn +{ + Pd.B = SVE_pfirst(Pd.B, Pn, Pd.B_2); +} + +# pnext_p_p_p.xml: PNEXT variant SVE +# PATTERN x2519c400/mask=xff3ffe10 + +:pnext Pd.T, Pn, Pd.T_2 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1021=0b011001110001 & sve_b_09=0 & sve_pg_0508 & sve_b_04=0 & sve_pdn_0003 & Pd.T & Pd.T_2 & Pn +{ + Pd.T = SVE_pnext(Pd.T, Pn, Pd.T_2); +} + +# prfb_i_p_ai.xml: PRFB (vector plus immediate) variant 32-bit element +# PATTERN x8400e000/mask=xffe0e010 + +:prfb sve_prfop, Pg3, [Zn.S^sve_opt5_1_0to31] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b00 & sve_imm5_1620 & sve_b_1315=0b111 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Zn.S & sve_opt5_1_0to31 & Pg3 +{ + SVE_prfb(sve_prfop:1, Pg3, Zn.S, sve_opt5_1_0to31); +} + +# prfb_i_p_ai.xml: PRFB (vector plus immediate) variant 64-bit element +# PATTERN xc400e000/mask=xffe0e010 + +:prfb sve_prfop, Pg3, [Zn.D^sve_opt5_1_0to31] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b00 & sve_imm5_1620 & sve_b_1315=0b111 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Zn.D & sve_opt5_1_0to31 & Pg3 +{ + SVE_prfb(sve_prfop:1, Pg3, Zn.D, sve_opt5_1_0to31); +} + +# prfb_i_p_bi.xml: PRFB (scalar plus immediate) variant SVE +# PATTERN x85c00000/mask=xffc0e010 + +:prfb sve_prfop, Pg3, [Rn_GPR64xsp^sve_mul6_1_m32to31] +is sve_b_2231=0b1000010111 & sve_imm6_1621 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & sve_mul6_1_m32to31 & Pg3 +{ + SVE_prfb(sve_prfop:1, Pg3, Rn_GPR64xsp, sve_mul6_1_m32to31); +} + +# prfb_i_p_br.xml: PRFB (scalar plus scalar) variant SVE +# PATTERN x8400c000/mask=xffe0e010 + +:prfb sve_prfop, Pg3, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Rm_GPR64 & Pg3 +{ + SVE_prfb(sve_prfop:1, Pg3, Rn_GPR64xsp, Rm_GPR64); +} + +# prfb_i_p_bz.xml: PRFB (scalar plus vector) variant 32-bit scaled offset +# PATTERN x84200000/mask=xffa0e010 + +:prfb sve_prfop, Pg3, [Rn_GPR64xsp, Zm.S, sve_mod] +is sve_b_2331=0b100001000 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Zm.S & sve_mod & Pg3 +{ + SVE_prfb(sve_prfop:1, Pg3, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# prfb_i_p_bz.xml: PRFB (scalar plus vector) variant 32-bit unpacked scaled offset +# PATTERN xc4200000/mask=xffa0e010 + +:prfb sve_prfop, Pg3, [Rn_GPR64xsp, Zm.D, sve_mod] +is sve_b_2331=0b110001000 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Zm.D & sve_mod & Pg3 +{ + SVE_prfb(sve_prfop:1, Pg3, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# prfb_i_p_bz.xml: PRFB (scalar plus vector) variant 64-bit scaled offset +# PATTERN xc4608000/mask=xffe0e010 + +:prfb sve_prfop, Pg3, [Rn_GPR64xsp, Zm.D] +is sve_b_2131=0b11000100011 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Zm.D & Pg3 +{ + SVE_prfb(sve_prfop:1, Pg3, Rn_GPR64xsp, Zm.D); +} + +# prfd_i_p_ai.xml: PRFD (vector plus immediate) variant 32-bit element +# PATTERN x8580e000/mask=xffe0e010 + +:prfd sve_prfop, Pg3, [Zn.S^sve_opt5_1_0to248] +is sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b00 & sve_imm5_1620 & sve_b_1315=0b111 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Zn.S & sve_opt5_1_0to248 & Pg3 +{ + SVE_prfd(sve_prfop:1, Pg3, Zn.S, sve_opt5_1_0to248); +} + +# prfd_i_p_ai.xml: PRFD (vector plus immediate) variant 64-bit element +# PATTERN xc580e000/mask=xffe0e010 + +:prfd sve_prfop, Pg3, [Zn.D^sve_opt5_1_0to248] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b00 & sve_imm5_1620 & sve_b_1315=0b111 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Zn.D & sve_opt5_1_0to248 & Pg3 +{ + SVE_prfd(sve_prfop:1, Pg3, Zn.D, sve_opt5_1_0to248); +} + +# prfd_i_p_bi.xml: PRFD (scalar plus immediate) variant SVE +# PATTERN x85c06000/mask=xffc0e010 + +:prfd sve_prfop, Pg3, [Rn_GPR64xsp^sve_mul6_1_m32to31] +is sve_b_2231=0b1000010111 & sve_imm6_1621 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & sve_mul6_1_m32to31 & Pg3 +{ + SVE_prfd(sve_prfop:1, Pg3, Rn_GPR64xsp, sve_mul6_1_m32to31); +} + +# prfd_i_p_br.xml: PRFD (scalar plus scalar) variant SVE +# PATTERN x8580c000/mask=xffe0e010 + +:prfd sve_prfop, Pg3, [Rn_GPR64xsp, Rm_GPR64, "lsl #3"] +is sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Rm_GPR64 & Pg3 +{ + SVE_prfd(sve_prfop:1, Pg3, Rn_GPR64xsp, Rm_GPR64); +} + +# prfd_i_p_bz.xml: PRFD (scalar plus vector) variant 32-bit scaled offset +# PATTERN x84206000/mask=xffa0e010 + +:prfd sve_prfop, Pg3, [Rn_GPR64xsp, Zm.S, sve_mod^" #3"] +is sve_b_2331=0b100001000 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Zm.S & sve_mod & Pg3 +{ + SVE_prfd(sve_prfop:1, Pg3, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# prfd_i_p_bz.xml: PRFD (scalar plus vector) variant 32-bit unpacked scaled offset +# PATTERN xc4206000/mask=xffa0e010 + +:prfd sve_prfop, Pg3, [Rn_GPR64xsp, Zm.D, sve_mod^" #3"] +is sve_b_2331=0b110001000 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Zm.D & sve_mod & Pg3 +{ + SVE_prfd(sve_prfop:1, Pg3, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# prfd_i_p_bz.xml: PRFD (scalar plus vector) variant 64-bit scaled offset +# PATTERN xc460e000/mask=xffe0e010 + +:prfd sve_prfop, Pg3, [Rn_GPR64xsp, Zm.D, "lsl #3"] +is sve_b_2131=0b11000100011 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Zm.D & Pg3 +{ + SVE_prfd(sve_prfop:1, Pg3, Rn_GPR64xsp, Zm.D); +} + +# prfh_i_p_ai.xml: PRFH (vector plus immediate) variant 32-bit element +# PATTERN x8480e000/mask=xffe0e010 + +:prfh sve_prfop, Pg3, [Zn.S^sve_opt5_1_0to62] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b00 & sve_imm5_1620 & sve_b_1315=0b111 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Zn.S & sve_opt5_1_0to62 & Pg3 +{ + SVE_prfh(sve_prfop:1, Pg3, Zn.S, sve_opt5_1_0to62); +} + +# prfh_i_p_ai.xml: PRFH (vector plus immediate) variant 64-bit element +# PATTERN xc480e000/mask=xffe0e010 + +:prfh sve_prfop, Pg3, [Zn.D^sve_opt5_1_0to62] +is sve_b_2531=0b1100010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b00 & sve_imm5_1620 & sve_b_1315=0b111 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Zn.D & sve_opt5_1_0to62 & Pg3 +{ + SVE_prfh(sve_prfop:1, Pg3, Zn.D, sve_opt5_1_0to62); +} + +# prfh_i_p_bi.xml: PRFH (scalar plus immediate) variant SVE +# PATTERN x85c02000/mask=xffc0e010 + +:prfh sve_prfop, Pg3, [Rn_GPR64xsp^sve_mul6_1_m32to31] +is sve_b_2231=0b1000010111 & sve_imm6_1621 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & sve_mul6_1_m32to31 & Pg3 +{ + SVE_prfh(sve_prfop:1, Pg3, Rn_GPR64xsp, sve_mul6_1_m32to31); +} + +# prfh_i_p_br.xml: PRFH (scalar plus scalar) variant SVE +# PATTERN x8480c000/mask=xffe0e010 + +:prfh sve_prfop, Pg3, [Rn_GPR64xsp, Rm_GPR64, "lsl #1"] +is sve_b_2531=0b1000010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Rm_GPR64 & Pg3 +{ + SVE_prfh(sve_prfop:1, Pg3, Rn_GPR64xsp, Rm_GPR64); +} + +# prfh_i_p_bz.xml: PRFH (scalar plus vector) variant 32-bit scaled offset +# PATTERN x84202000/mask=xffa0e010 + +:prfh sve_prfop, Pg3, [Rn_GPR64xsp, Zm.S, sve_mod^" #1"] +is sve_b_2331=0b100001000 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Zm.S & sve_mod & Pg3 +{ + SVE_prfh(sve_prfop:1, Pg3, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# prfh_i_p_bz.xml: PRFH (scalar plus vector) variant 32-bit unpacked scaled offset +# PATTERN xc4202000/mask=xffa0e010 + +:prfh sve_prfop, Pg3, [Rn_GPR64xsp, Zm.D, sve_mod^" #1"] +is sve_b_2331=0b110001000 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Zm.D & sve_mod & Pg3 +{ + SVE_prfh(sve_prfop:1, Pg3, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# prfh_i_p_bz.xml: PRFH (scalar plus vector) variant 64-bit scaled offset +# PATTERN xc460a000/mask=xffe0e010 + +:prfh sve_prfop, Pg3, [Rn_GPR64xsp, Zm.D, "lsl #1"] +is sve_b_2131=0b11000100011 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Zm.D & Pg3 +{ + SVE_prfh(sve_prfop:1, Pg3, Rn_GPR64xsp, Zm.D); +} + +# prfw_i_p_ai.xml: PRFW (vector plus immediate) variant 32-bit element +# PATTERN x8500e000/mask=xffe0e010 + +:prfw sve_prfop, Pg3, [Zn.S^sve_opt5_1_0to124] +is sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b00 & sve_imm5_1620 & sve_b_1315=0b111 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Zn.S & sve_opt5_1_0to124 & Pg3 +{ + SVE_prfw(sve_prfop:1, Pg3, Zn.S, sve_opt5_1_0to124); +} + +# prfw_i_p_ai.xml: PRFW (vector plus immediate) variant 64-bit element +# PATTERN xc500e000/mask=xffe0e010 + +:prfw sve_prfop, Pg3, [Zn.D^sve_opt5_1_0to124] +is sve_b_2531=0b1100010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b00 & sve_imm5_1620 & sve_b_1315=0b111 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Zn.D & sve_opt5_1_0to124 & Pg3 +{ + SVE_prfw(sve_prfop:1, Pg3, Zn.D, sve_opt5_1_0to124); +} + +# prfw_i_p_bi.xml: PRFW (scalar plus immediate) variant SVE +# PATTERN x85c04000/mask=xffc0e010 + +:prfw sve_prfop, Pg3, [Rn_GPR64xsp^sve_mul6_1_m32to31] +is sve_b_2231=0b1000010111 & sve_imm6_1621 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & sve_mul6_1_m32to31 & Pg3 +{ + SVE_prfw(sve_prfop:1, Pg3, Rn_GPR64xsp, sve_mul6_1_m32to31); +} + +# prfw_i_p_br.xml: PRFW (scalar plus scalar) variant SVE +# PATTERN x8500c000/mask=xffe0e010 + +:prfw sve_prfop, Pg3, [Rn_GPR64xsp, Rm_GPR64, "lsl #2"] +is sve_b_2531=0b1000010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b110 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Rm_GPR64 & Pg3 +{ + SVE_prfw(sve_prfop:1, Pg3, Rn_GPR64xsp, Rm_GPR64); +} + +# prfw_i_p_bz.xml: PRFW (scalar plus vector) variant 32-bit scaled offset +# PATTERN x84204000/mask=xffa0e010 + +:prfw sve_prfop, Pg3, [Rn_GPR64xsp, Zm.S, sve_mod^" #2"] +is sve_b_2331=0b100001000 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Zm.S & sve_mod & Pg3 +{ + SVE_prfw(sve_prfop:1, Pg3, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# prfw_i_p_bz.xml: PRFW (scalar plus vector) variant 32-bit unpacked scaled offset +# PATTERN xc4204000/mask=xffa0e010 + +:prfw sve_prfop, Pg3, [Rn_GPR64xsp, Zm.D, sve_mod^" #2"] +is sve_b_2331=0b110001000 & sve_xs_22 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Zm.D & sve_mod & Pg3 +{ + SVE_prfw(sve_prfop:1, Pg3, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# prfw_i_p_bz.xml: PRFW (scalar plus vector) variant 64-bit scaled offset +# PATTERN xc460c000/mask=xffe0e010 + +:prfw sve_prfop, Pg3, [Rn_GPR64xsp, Zm.D, "lsl #2"] +is sve_b_2131=0b11000100011 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_b_04=0 & sve_prfop_0003 & sve_prfop & Rn_GPR64xsp & Zm.D & Pg3 +{ + SVE_prfw(sve_prfop:1, Pg3, Rn_GPR64xsp, Zm.D); +} + +# ptest_p_p.xml: PTEST variant SVE +# PATTERN x2550c000/mask=xffffc21f + +:ptest Pg, Pn.B +is sve_b_3031=0b00 & sve_b_2429=0b100101 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b01 & sve_b_1419=0b000011 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_b_03=0 & sve_b_02=0 & sve_b_01=0 & sve_b_00=0 & Pn.B & Pg +{ + SVE_ptest(Pg, Pn.B); +} + +# ptrue_p_s.xml: PTRUE, PTRUES variant Flag setting +# PATTERN x2519e000/mask=xff3ffc10 + +:ptrues Pd.T^sve_opt_pattern +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1721=0b01100 & sve_b_16=1 & sve_b_1015=0b111000 & sve_pattern_0509 & sve_b_04=0 & sve_pd_0003 & sve_pattern & Pd.T & sve_opt_pattern +{ + Pd.T = SVE_ptrues(Pd.T, sve_opt_pattern); +} + +# ptrue_p_s.xml: PTRUE, PTRUES variant Not flag setting +# PATTERN x2518e000/mask=xff3ffc10 + +:ptrue Pd.T^sve_opt_pattern +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1721=0b01100 & sve_b_16=0 & sve_b_1015=0b111000 & sve_pattern_0509 & sve_b_04=0 & sve_pd_0003 & sve_pattern & Pd.T & sve_opt_pattern +{ + Pd.T = SVE_ptrue(Pd.T, sve_opt_pattern); +} + +# punpkhi_p_p.xml: PUNPKHI, PUNPKLO variant High half +# PATTERN x05314000/mask=xfffffe10 + +:punpkhi Pd.H, Pn.B +is sve_b_1731=0b000001010011000 & sve_b_16=1 & sve_b_1015=0b010000 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.H & Pn.B +{ + Pd.H = SVE_punpkhi(Pd.H, Pn.B); +} + +# punpkhi_p_p.xml: PUNPKHI, PUNPKLO variant Low half +# PATTERN x05304000/mask=xfffffe10 + +:punpklo Pd.H, Pn.B +is sve_b_1731=0b000001010011000 & sve_b_16=0 & sve_b_1015=0b010000 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.H & Pn.B +{ + Pd.H = SVE_punpklo(Pd.H, Pn.B); +} + +# rbit_z_p_z.xml: RBIT variant SVE +# PATTERN x05278000/mask=xff3fe000 + +:rbit Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1821=0b1001 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_rbit(Zd.T, Pg3_m, Zn.T); +} + +# rdffr_p_f.xml: RDFFR (unpredicated) variant SVE +# PATTERN x2519f000/mask=xfffffff0 + +:rdffr Pd.B +is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=0 & sve_b_1021=0b011001111100 & sve_b_0409=0b000000 & sve_pd_0003 & Pd.B +{ + Pd.B = SVE_rdffr(Pd.B); +} + +# rdffr_p_p_f.xml: RDFFR, RDFFRS (predicated) variant Flag setting +# PATTERN x2558f000/mask=xfffffe10 + +:rdffrs Pd.B, Pn_z +is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1021=0b011000111100 & sve_b_09=0 & sve_pg_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pn_z +{ + Pd.B = SVE_rdffrs(Pd.B, Pn_z); +} + +# rdffr_p_p_f.xml: RDFFR, RDFFRS (predicated) variant Not flag setting +# PATTERN x2518f000/mask=xfffffe10 + +:rdffr Pd.B, Pn_z +is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=0 & sve_b_1021=0b011000111100 & sve_b_09=0 & sve_pg_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pn_z +{ + Pd.B = SVE_rdffr(Pd.B, Pn_z); +} + +# rdvl_r_i.xml: RDVL variant SVE +# PATTERN x04bf5000/mask=xfffff800 + +:rdvl Rd_GPR64, "#"^sve_imm6_1_m32to31 +is sve_b_2331=0b000001001 & sve_b_22=0 & sve_b_21=1 & sve_b_1720=0b1111 & sve_b_16=1 & sve_b_1115=0b01010 & sve_imm6_0510 & sve_rd_0004 & sve_imm6_1_m32to31 & Rd_GPR64 +{ + Rd_GPR64 = SVE_rdvl(Rd_GPR64, sve_imm6_1_m32to31:1); +} + +# rev_p_p.xml: REV (predicate) variant SVE +# PATTERN x05344000/mask=xff3ffe10 + +:rev Pd.T, Pn.T +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1021=0b110100010000 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pn.T & Pd.T +{ + Pd.T = SVE_rev(Pd.T, Pn.T); +} + +# rev_z_z.xml: REV (vector) variant SVE +# PATTERN x05383800/mask=xff3ffc00 + +:rev Zd.T, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1021=0b111000001110 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T +{ + Zd.T = SVE_rev(Zd.T, Zn.T); +} + +# revb_z_z.xml: REVB, REVH, REVW variant Byte +# PATTERN x05248000/mask=xff3fe000 + +:revb Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1821=0b1001 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_revb(Zd.T, Pg3_m, Zn.T); +} + +# revb_z_z.xml: REVB, REVH, REVW variant Halfword +# PATTERN x05258000/mask=xff3fe000 + +:revh Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1821=0b1001 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_revh(Zd.T, Pg3_m, Zn.T); +} + +# revb_z_z.xml: REVB, REVH, REVW variant Word +# PATTERN x05268000/mask=xff3fe000 + +:revw Zd.D, Pg3_m, Zn.D +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1821=0b1001 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Pg3_m +{ + Zd.D = SVE_revw(Zd.D, Pg3_m, Zn.D); +} + +# sabd_z_p_zz.xml: SABD variant SVE +# PATTERN x040c0000/mask=xff3fe000 + +:sabd Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b001 & sve_b_18=1 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_sabd(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# saddv_r_p_z.xml: SADDV variant SVE +# PATTERN x04002000/mask=xff3fe000 + +:saddv Rd_FPR64, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b000 & sve_b_18=0 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3 +{ + Rd_FPR64 = SVE_saddv(Rd_FPR64, Zn.T, Pg3); +} + +# scvtf_z_p_z.xml: SCVTF variant 16-bit to half-precision +# PATTERN x6552a000/mask=xffffe000 + +:scvtf Zd.H, Pg3_m, Zn.H +is sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b010 & sve_b_18=0 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.H & Pg3_m +{ + Zd.H = SVE_scvtf(Zd.H, Pg3_m, Zn.H); +} + +# scvtf_z_p_z.xml: SCVTF variant 32-bit to half-precision +# PATTERN x6554a000/mask=xffffe000 + +:scvtf Zd.H, Pg3_m, Zn.S +is sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.H & Pg3_m +{ + Zd.H = SVE_scvtf(Zd.H, Pg3_m, Zn.S); +} + +# scvtf_z_p_z.xml: SCVTF variant 32-bit to single-precision +# PATTERN x6594a000/mask=xffffe000 + +:scvtf Zd.S, Pg3_m, Zn.S +is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=0 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.S & Pg3_m +{ + Zd.S = SVE_scvtf(Zd.S, Pg3_m, Zn.S); +} + +# scvtf_z_p_z.xml: SCVTF variant 32-bit to double-precision +# PATTERN x65d0a000/mask=xffffe000 + +:scvtf Zd.D, Pg3_m, Zn.S +is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b010 & sve_b_18=0 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.D & Pg3_m +{ + Zd.D = SVE_scvtf(Zd.D, Pg3_m, Zn.S); +} + +# scvtf_z_p_z.xml: SCVTF variant 64-bit to half-precision +# PATTERN x6556a000/mask=xffffe000 + +:scvtf Zd.H, Pg3_m, Zn.D +is sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.H & Pg3_m +{ + Zd.H = SVE_scvtf(Zd.H, Pg3_m, Zn.D); +} + +# scvtf_z_p_z.xml: SCVTF variant 64-bit to single-precision +# PATTERN x65d4a000/mask=xffffe000 + +:scvtf Zd.S, Pg3_m, Zn.D +is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.S & Pg3_m +{ + Zd.S = SVE_scvtf(Zd.S, Pg3_m, Zn.D); +} + +# scvtf_z_p_z.xml: SCVTF variant 64-bit to double-precision +# PATTERN x65d6a000/mask=xffffe000 + +:scvtf Zd.D, Pg3_m, Zn.D +is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Pg3_m +{ + Zd.D = SVE_scvtf(Zd.D, Pg3_m, Zn.D); +} + +# sdiv_z_p_zz.xml: SDIV variant SVE +# PATTERN x04940000/mask=xffbfe000 + +:sdiv Zd.T_sz, Pg3_m, Zd.T_sz_2, Zn.T_sz +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_sz_22 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T_sz & Zd.T_sz_2 & Zn.T_sz & Pg3_m +{ + Zd.T_sz = SVE_sdiv(Zd.T_sz, Pg3_m, Zd.T_sz_2, Zn.T_sz); +} + +# sdivr_z_p_zz.xml: SDIVR variant SVE +# PATTERN x04960000/mask=xffbfe000 + +:sdivr Zd.T_sz, Pg3_m, Zd.T_sz_2, Zn.T_sz +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_sz_22 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T_sz & Zd.T_sz_2 & Zn.T_sz & Pg3_m +{ + Zd.T_sz = SVE_sdivr(Zd.T_sz, Pg3_m, Zd.T_sz_2, Zn.T_sz); +} + +# sdot_z_zzz.xml: SDOT (vectors) variant SVE +# PATTERN x44800000/mask=xffa0fc00 + +:sdot Zd.T_sz, Zn.Tb_sz, Zm.Tb_sz +is sve_b_2431=0b01000100 & sve_b_23=1 & sve_sz_22 & sve_b_21=0 & sve_zm_1620 & sve_b_1115=0b00000 & sve_b_10=0 & sve_zn_0509 & sve_zda_0004 & Zm.Tb_sz & Zd.T_sz & Zn.Tb_sz +{ + Zd.T_sz = SVE_sdot(Zd.T_sz, Zn.Tb_sz, Zm.Tb_sz); +} + +# sdot_z_zzzi.xml: SDOT (indexed) variant 32-bit +# PATTERN x44a00000/mask=xffe0fc00 + +:sdot Zd.S, Zn.B, Zm3.B[sve_i2_1920] +is sve_b_2431=0b01000100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_i2_1920 & sve_zm_1618 & sve_b_1115=0b00000 & sve_b_10=0 & sve_zn_0509 & sve_zda_0004 & Zd.S & Zn.B & Zm3.B +{ + Zd.S = SVE_sdot(Zd.S, Zn.B, Zm3.B, sve_i2_1920:1); +} + +# sdot_z_zzzi.xml: SDOT (indexed) variant 64-bit +# PATTERN x44e00000/mask=xffe0fc00 + +:sdot Zd.D, Zn.H, Zm4.H[sve_i1_20] +is sve_b_2431=0b01000100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_i1_20 & sve_zm_1619 & sve_b_1115=0b00000 & sve_b_10=0 & sve_zn_0509 & sve_zda_0004 & Zd.D & Zn.H & Zm4.H +{ + Zd.D = SVE_sdot(Zd.D, Zn.H, Zm4.H, sve_i1_20:1); +} + +# sel_p_p_pp.xml: SEL (predicates) variant SVE +# PATTERN x25004210/mask=xfff0c210 + +:sel Pd.B, Pg, Pn.B, Pm.B +is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=1 & sve_pn_0508 & sve_b_04=1 & sve_pd_0003 & Pd.B & Pn.B & Pm.B & Pg +{ + Pd.B = SVE_sel(Pd.B, Pg, Pn.B, Pm.B); +} + +# sel_z_p_zz.xml: SEL (vectors) variant SVE +# PATTERN x0520c000/mask=xff20c000 + +:sel Zd.T, Pg, Zn.T, Zm.T +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1415=0b11 & sve_pg_1013 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T & Pg +{ + Zd.T = SVE_sel(Zd.T, Pg, Zn.T, Zm.T); +} + +# setffr_f.xml: SETFFR variant SVE +# PATTERN x252c9000/mask=xffffffff + +:setffr "" +is sve_b_3031=0b00 & sve_b_2429=0b100101 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b10 & sve_b_1019=0b1100100100 & sve_b_0409=0b000000 & sve_b_03=0 & sve_b_02=0 & sve_b_0001=0b00 +unimpl + +# smax_z_p_zz.xml: SMAX (vectors) variant SVE +# PATTERN x04080000/mask=xff3fe000 + +:smax Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_smax(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# smax_z_zi.xml: SMAX (immediate) variant SVE +# PATTERN x2528c000/mask=xff3fe000 + +:smax Zd.T, Zd.T_2, "#"^sve_imm8_1_m128to127 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b101 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1415=0b11 & sve_b_13=0 & sve_imm8_0512 & sve_zdn_0004 & Zd.T & Zd.T_2 & sve_imm8_1_m128to127 +{ + Zd.T = SVE_smax(Zd.T, Zd.T_2, sve_imm8_1_m128to127:1); +} + +# smaxv_r_p_z.xml: SMAXV variant SVE +# PATTERN x04082000/mask=xff3fe000 + +:smaxv Rd_FPR8, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b00 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3 +{ + Rd_FPR8 = SVE_smaxv(Rd_FPR8, Pg3, Zn.T); +} + +# smaxv_r_p_z.xml: SMAXV variant SVE +# PATTERN x04082000/mask=xff3fe000 + +:smaxv Rd_FPR32, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b10 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3 +{ + Rd_FPR32 = SVE_smaxv(Rd_FPR32, Pg3, Zn.T); +} + +# smaxv_r_p_z.xml: SMAXV variant SVE +# PATTERN x04082000/mask=xff3fe000 + +:smaxv Rd_FPR16, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b01 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3 +{ + Rd_FPR16 = SVE_smaxv(Rd_FPR16, Pg3, Zn.T); +} + +# smaxv_r_p_z.xml: SMAXV variant SVE +# PATTERN x04082000/mask=xff3fe000 + +:smaxv Rd_FPR64, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b11 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3 +{ + Rd_FPR64 = SVE_smaxv(Rd_FPR64, Pg3, Zn.T); +} + +# smin_z_p_zz.xml: SMIN (vectors) variant SVE +# PATTERN x040a0000/mask=xff3fe000 + +:smin Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_smin(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# smin_z_zi.xml: SMIN (immediate) variant SVE +# PATTERN x252ac000/mask=xff3fe000 + +:smin Zd.T, Zd.T_2, "#"^sve_imm8_1_m128to127 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b101 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1415=0b11 & sve_b_13=0 & sve_imm8_0512 & sve_zdn_0004 & Zd.T & Zd.T_2 & sve_imm8_1_m128to127 +{ + Zd.T = SVE_smin(Zd.T, Zd.T_2, sve_imm8_1_m128to127:1); +} + +# sminv_r_p_z.xml: SMINV variant SVE +# PATTERN x040a2000/mask=xff3fe000 + +:sminv Rd_FPR8, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b00 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3 +{ + Rd_FPR8 = SVE_sminv(Rd_FPR8, Pg3, Zn.T); +} + +# sminv_r_p_z.xml: SMINV variant SVE +# PATTERN x040a2000/mask=xff3fe000 + +:sminv Rd_FPR32, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b10 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3 +{ + Rd_FPR32 = SVE_sminv(Rd_FPR32, Pg3, Zn.T); +} + +# sminv_r_p_z.xml: SMINV variant SVE +# PATTERN x040a2000/mask=xff3fe000 + +:sminv Rd_FPR16, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b01 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3 +{ + Rd_FPR16 = SVE_sminv(Rd_FPR16, Pg3, Zn.T); +} + +# sminv_r_p_z.xml: SMINV variant SVE +# PATTERN x040a2000/mask=xff3fe000 + +:sminv Rd_FPR64, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b11 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3 +{ + Rd_FPR64 = SVE_sminv(Rd_FPR64, Pg3, Zn.T); +} + +# smulh_z_p_zz.xml: SMULH variant SVE +# PATTERN x04120000/mask=xff3fe000 + +:smulh Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_18=0 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_smulh(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# splice_z_p_zz.xml: SPLICE variant SVE +# PATTERN x052c8000/mask=xff3fe000 + +:splice Zd.T, Pg3, Zd.T_2, Zn.T +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1321=0b101100100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3 +{ + Zd.T = SVE_splice(Zd.T, Pg3, Zd.T_2, Zn.T); +} + +# sqadd_z_zi.xml: SQADD (immediate) variant SVE +# PATTERN x2524c000/mask=xff3fc000 + +:sqadd Zd.T, Zd.T_2, sve_shf8_1_0to255 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b100 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1415=0b11 & sve_sh_13 & sve_imm8_0512 & sve_zdn_0004 & sve_shift_13 & Zd.T & Zd.T_2 & sve_imm8_1_0to255 & sve_shf8_1_0to255 +{ + Zd.T = SVE_sqadd(Zd.T, Zd.T_2, sve_shf8_1_0to255, sve_shift_13:1); +} + +# sqadd_z_zz.xml: SQADD (vectors) variant SVE +# PATTERN x04201000/mask=xff20fc00 + +:sqadd Zd.T, Zn.T, Zm.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b10 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T +{ + Zd.T = SVE_sqadd(Zd.T, Zn.T, Zm.T); +} + +# sqdecb_r_rs.xml: SQDECB variant 32-bit +# PATTERN x0420f800/mask=xfff0fc00 + +:sqdecb Rd_GPR64, Rd_GPR32^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_sqdecb(Rd_GPR64, Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# sqdecb_r_rs.xml: SQDECB variant 64-bit +# PATTERN x0430f800/mask=xfff0fc00 + +:sqdecb Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_sqdecb(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# sqdecd_r_rs.xml: SQDECD (scalar) variant 32-bit +# PATTERN x04e0f800/mask=xfff0fc00 + +:sqdecd Rd_GPR64, Rd_GPR32^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_sqdecd(Rd_GPR64, Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# sqdecd_r_rs.xml: SQDECD (scalar) variant 64-bit +# PATTERN x04f0f800/mask=xfff0fc00 + +:sqdecd Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_sqdecd(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# sqdecd_z_zs.xml: SQDECD (vector) variant SVE +# PATTERN x04e0c800/mask=xfff0fc00 + +:sqdecd Zd.D^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1215=0b1100 & sve_b_11=1 & sve_b_10=0 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.D & sve_imm4_1_1to16 & sve_mul_pattern +{ + Zd.D = SVE_sqdecd(Zd.D, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# sqdech_r_rs.xml: SQDECH (scalar) variant 32-bit +# PATTERN x0460f800/mask=xfff0fc00 + +:sqdech Rd_GPR64, Rd_GPR32^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_sqdech(Rd_GPR64, Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# sqdech_r_rs.xml: SQDECH (scalar) variant 64-bit +# PATTERN x0470f800/mask=xfff0fc00 + +:sqdech Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_sqdech(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# sqdech_z_zs.xml: SQDECH (vector) variant SVE +# PATTERN x0460c800/mask=xfff0fc00 + +:sqdech Zd.H^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1215=0b1100 & sve_b_11=1 & sve_b_10=0 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.H & sve_imm4_1_1to16 & sve_mul_pattern +{ + Zd.H = SVE_sqdech(Zd.H, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# sqdecp_r_p_r.xml: SQDECP (scalar) variant 32-bit +# PATTERN x252a8800/mask=xff3ffe00 + +:sqdecp Rd_GPR64, Pn.T, Rd_GPR32 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1010 & sve_b_17=1 & sve_b_16=0 & sve_b_1115=0b10001 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_rdn_0004 & Pn.T & Rd_GPR32 & Rd_GPR64 +{ + Rd_GPR64 = SVE_sqdecp(Rd_GPR64, Pn.T, Rd_GPR32); +} + +# sqdecp_r_p_r.xml: SQDECP (scalar) variant 64-bit +# PATTERN x252a8c00/mask=xff3ffe00 + +:sqdecp Rd_GPR64, Pn.T +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1010 & sve_b_17=1 & sve_b_16=0 & sve_b_1115=0b10001 & sve_b_10=1 & sve_b_09=0 & sve_pg_0508 & sve_rdn_0004 & Pn.T & Rd_GPR64 +{ + Rd_GPR64 = SVE_sqdecp(Rd_GPR64, Pn.T); +} + +# sqdecp_z_p_z.xml: SQDECP (vector) variant SVE +# PATTERN x252a8000/mask=xff3ffe00 + +:sqdecp Zd.T, Pn +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1010 & sve_b_17=1 & sve_b_16=0 & sve_b_1115=0b10000 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_zdn_0004 & Zd.T & Pn +{ + Zd.T = SVE_sqdecp(Zd.T, Pn); +} + +# sqdecw_r_rs.xml: SQDECW (scalar) variant 32-bit +# PATTERN x04a0f800/mask=xfff0fc00 + +:sqdecw Rd_GPR64, Rd_GPR32^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_sqdecw(Rd_GPR64, Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# sqdecw_r_rs.xml: SQDECW (scalar) variant 64-bit +# PATTERN x04b0f800/mask=xfff0fc00 + +:sqdecw Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_sqdecw(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# sqdecw_z_zs.xml: SQDECW (vector) variant SVE +# PATTERN x04a0c800/mask=xfff0fc00 + +:sqdecw Zd.S^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1215=0b1100 & sve_b_11=1 & sve_b_10=0 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.S & sve_imm4_1_1to16 & sve_mul_pattern +{ + Zd.S = SVE_sqdecw(Zd.S, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# sqincb_r_rs.xml: SQINCB variant 32-bit +# PATTERN x0420f000/mask=xfff0fc00 + +:sqincb Rd_GPR64, Rd_GPR32^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_sqincb(Rd_GPR64, Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# sqincb_r_rs.xml: SQINCB variant 64-bit +# PATTERN x0430f000/mask=xfff0fc00 + +:sqincb Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_sqincb(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# sqincd_r_rs.xml: SQINCD (scalar) variant 32-bit +# PATTERN x04e0f000/mask=xfff0fc00 + +:sqincd Rd_GPR64, Rd_GPR32^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_sqincd(Rd_GPR64, Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# sqincd_r_rs.xml: SQINCD (scalar) variant 64-bit +# PATTERN x04f0f000/mask=xfff0fc00 + +:sqincd Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_sqincd(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# sqincd_z_zs.xml: SQINCD (vector) variant SVE +# PATTERN x04e0c000/mask=xfff0fc00 + +:sqincd Zd.D^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1215=0b1100 & sve_b_11=0 & sve_b_10=0 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.D & sve_imm4_1_1to16 & sve_mul_pattern +{ + Zd.D = SVE_sqincd(Zd.D, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# sqinch_r_rs.xml: SQINCH (scalar) variant 32-bit +# PATTERN x0460f000/mask=xfff0fc00 + +:sqinch Rd_GPR64, Rd_GPR32^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_sqinch(Rd_GPR64, Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# sqinch_r_rs.xml: SQINCH (scalar) variant 64-bit +# PATTERN x0470f000/mask=xfff0fc00 + +:sqinch Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_sqinch(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# sqinch_z_zs.xml: SQINCH (vector) variant SVE +# PATTERN x0460c000/mask=xfff0fc00 + +:sqinch Zd.H^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1215=0b1100 & sve_b_11=0 & sve_b_10=0 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.H & sve_imm4_1_1to16 & sve_mul_pattern +{ + Zd.H = SVE_sqinch(Zd.H, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# sqincp_r_p_r.xml: SQINCP (scalar) variant 32-bit +# PATTERN x25288800/mask=xff3ffe00 + +:sqincp Rd_GPR64, Pn.T, Rd_GPR32 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1010 & sve_b_17=0 & sve_b_16=0 & sve_b_1115=0b10001 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_rdn_0004 & Pn.T & Rd_GPR32 & Rd_GPR64 +{ + Rd_GPR64 = SVE_sqincp(Rd_GPR64, Pn.T, Rd_GPR32); +} + +# sqincp_r_p_r.xml: SQINCP (scalar) variant 64-bit +# PATTERN x25288c00/mask=xff3ffe00 + +:sqincp Rd_GPR64, Pn.T +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1010 & sve_b_17=0 & sve_b_16=0 & sve_b_1115=0b10001 & sve_b_10=1 & sve_b_09=0 & sve_pg_0508 & sve_rdn_0004 & Pn.T & Rd_GPR64 +{ + Rd_GPR64 = SVE_sqincp(Rd_GPR64, Pn.T); +} + +# sqincp_z_p_z.xml: SQINCP (vector) variant SVE +# PATTERN x25288000/mask=xff3ffe00 + +:sqincp Zd.T, Pn +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1010 & sve_b_17=0 & sve_b_16=0 & sve_b_1115=0b10000 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_zdn_0004 & Zd.T & Pn +{ + Zd.T = SVE_sqincp(Zd.T, Pn); +} + +# sqincw_r_rs.xml: SQINCW (scalar) variant 32-bit +# PATTERN x04a0f000/mask=xfff0fc00 + +:sqincw Rd_GPR64, Rd_GPR32^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_sqincw(Rd_GPR64, Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# sqincw_r_rs.xml: SQINCW (scalar) variant 64-bit +# PATTERN x04b0f000/mask=xfff0fc00 + +:sqincw Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=0 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_sqincw(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# sqincw_z_zs.xml: SQINCW (vector) variant SVE +# PATTERN x04a0c000/mask=xfff0fc00 + +:sqincw Zd.S^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1215=0b1100 & sve_b_11=0 & sve_b_10=0 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.S & sve_imm4_1_1to16 & sve_mul_pattern +{ + Zd.S = SVE_sqincw(Zd.S, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# sqsub_z_zi.xml: SQSUB (immediate) variant SVE +# PATTERN x2526c000/mask=xff3fc000 + +:sqsub Zd.T, Zd.T_2, sve_shf8_1_0to255 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b100 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1415=0b11 & sve_sh_13 & sve_imm8_0512 & sve_zdn_0004 & sve_shift_13 & Zd.T & Zd.T_2 & sve_imm8_1_0to255 & sve_shf8_1_0to255 +{ + Zd.T = SVE_sqsub(Zd.T, Zd.T_2, sve_shf8_1_0to255, sve_shift_13:1); +} + +# sqsub_z_zz.xml: SQSUB (vectors) variant SVE +# PATTERN x04201800/mask=xff20fc00 + +:sqsub Zd.T, Zn.T, Zm.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b11 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T +{ + Zd.T = SVE_sqsub(Zd.T, Zn.T, Zm.T); +} + +# st1b_z_p_ai.xml: ST1B (vector plus immediate) variant 32-bit element +# PATTERN xe460a000/mask=xffe0e000 + +:st1b "{"^Zd.S^"}", Pg3, [Zn.S^sve_opt5_1_0to31] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b11 & sve_imm5_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Zd.S & sve_opt5_1_0to31 & Pg3 +{ + SVE_st1b(Zd.S, Pg3, Zn.S, sve_opt5_1_0to31); +} + +# st1b_z_p_ai.xml: ST1B (vector plus immediate) variant 64-bit element +# PATTERN xe440a000/mask=xffe0e000 + +:st1b "{"^Zd.D^"}", Pg3, [Zn.D^sve_opt5_1_0to31] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b10 & sve_imm5_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Zd.D & sve_opt5_1_0to31 & Pg3 +{ + SVE_st1b(Zd.D, Pg3, Zn.D, sve_opt5_1_0to31); +} + +# st1b_z_p_bi.xml: ST1B (scalar plus immediate) variant SVE +# PATTERN xe400e000/mask=xff90e000 + +:st1b "{"^Zd.T_size_2122^"}", Pg3, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_size_2122 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Zd.T_size_2122 & Rn_GPR64xsp & sve_mul4_1_m8to7 & Pg3 +{ + SVE_st1b(Zd.T_size_2122, Pg3, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# st1b_z_p_br.xml: ST1B (scalar plus scalar) variant SVE +# PATTERN xe4004000/mask=xff80e000 + +:st1b "{"^Zd.T_size_2122^"}", Pg3, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_size_2122 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Zd.T_size_2122 & Rn_GPR64xsp & Rm_GPR64 & Pg3 +{ + SVE_st1b(Zd.T_size_2122, Pg3, Rn_GPR64xsp, Rm_GPR64); +} + +# st1b_z_p_bz.xml: ST1B (scalar plus vector) variant 32-bit unpacked unscaled offset +# PATTERN xe4008000/mask=xffe0a000 + +:st1b "{"^Zd.D^"}", Pg3, [Rn_GPR64xsp, Zm.D, sve_mod] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b00 & sve_zm_1620 & sve_b_15=1 & sve_xs_14 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & sve_mod & Pg3 +{ + SVE_st1b(Zd.D, Pg3, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# st1b_z_p_bz.xml: ST1B (scalar plus vector) variant 32-bit unscaled offset +# PATTERN xe4408000/mask=xffe0a000 + +:st1b "{"^Zd.S^"}", Pg3, [Rn_GPR64xsp, Zm.S, sve_mod] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_xs_14 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.S & Zd.S & sve_mod & Pg3 +{ + SVE_st1b(Zd.S, Pg3, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# st1b_z_p_bz.xml: ST1B (scalar plus vector) variant 64-bit unscaled offset +# PATTERN xe400a000/mask=xffe0e000 + +:st1b "{"^Zd.D^"}", Pg3, [Rn_GPR64xsp, Zm.D] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b00 & sve_zm_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & Pg3 +{ + SVE_st1b(Zd.D, Pg3, Rn_GPR64xsp, Zm.D); +} + +# st1d_z_p_ai.xml: ST1D (vector plus immediate) variant SVE +# PATTERN xe5c0a000/mask=xffe0e000 + +:st1d "{"^Zd.D^"}", Pg3, [Zn.D^sve_opt5_1_0to248] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b10 & sve_imm5_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Zd.D & sve_opt5_1_0to248 & Pg3 +{ + SVE_st1d(Zd.D, Pg3, Zn.D, sve_opt5_1_0to248); +} + +# st1d_z_p_bi.xml: ST1D (scalar plus immediate) variant SVE +# PATTERN xe580e000/mask=xff90e000 + +:st1d "{"^Zd.D^"}", Pg3, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_size_2122 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zd.D & sve_mul4_1_m8to7 & Pg3 +{ + SVE_st1d(Zd.D, Pg3, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# st1d_z_p_br.xml: ST1D (scalar plus scalar) variant SVE +# PATTERN xe5804000/mask=xff80e000 + +:st1d "{"^Zd.D^"}", Pg3, [Rn_GPR64xsp, Rm_GPR64, "lsl #3"] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_size_2122 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zd.D & Rm_GPR64 & Pg3 +{ + SVE_st1d(Zd.D, Pg3, Rn_GPR64xsp, Rm_GPR64); +} + +# st1d_z_p_bz.xml: ST1D (scalar plus vector) variant 32-bit unpacked scaled offset +# PATTERN xe5a08000/mask=xffe0a000 + +:st1d "{"^Zd.D^"}", Pg3, [Rn_GPR64xsp, Zm.D, sve_mod^" #3"] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b01 & sve_zm_1620 & sve_b_15=1 & sve_xs_14 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & sve_mod & Pg3 +{ + SVE_st1d(Zd.D, Pg3, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# st1d_z_p_bz.xml: ST1D (scalar plus vector) variant 32-bit unpacked unscaled offset +# PATTERN xe5808000/mask=xffe0a000 + +:st1d "{"^Zd.D^"}", Pg3, [Rn_GPR64xsp, Zm.D, sve_mod] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b00 & sve_zm_1620 & sve_b_15=1 & sve_xs_14 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & sve_mod & Pg3 +{ + SVE_st1d(Zd.D, Pg3, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# st1d_z_p_bz.xml: ST1D (scalar plus vector) variant 64-bit scaled offset +# PATTERN xe5a0a000/mask=xffe0e000 + +:st1d "{"^Zd.D^"}", Pg3, [Rn_GPR64xsp, Zm.D, "lsl #3"] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b01 & sve_zm_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & Pg3 +{ + SVE_st1d(Zd.D, Pg3, Rn_GPR64xsp, Zm.D); +} + +# st1d_z_p_bz.xml: ST1D (scalar plus vector) variant 64-bit unscaled offset +# PATTERN xe580a000/mask=xffe0e000 + +:st1d "{"^Zd.D^"}", Pg3, [Rn_GPR64xsp, Zm.D] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b00 & sve_zm_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & Pg3 +{ + SVE_st1d(Zd.D, Pg3, Rn_GPR64xsp, Zm.D); +} + +# st1h_z_p_ai.xml: ST1H (vector plus immediate) variant 32-bit element +# PATTERN xe4e0a000/mask=xffe0e000 + +:st1h "{"^Zd.S^"}", Pg3, [Zn.S^sve_opt5_1_0to62] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b11 & sve_imm5_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Zd.S & sve_opt5_1_0to62 & Pg3 +{ + SVE_st1h(Zd.S, Pg3, Zn.S, sve_opt5_1_0to62); +} + +# st1h_z_p_ai.xml: ST1H (vector plus immediate) variant 64-bit element +# PATTERN xe4c0a000/mask=xffe0e000 + +:st1h "{"^Zd.D^"}", Pg3, [Zn.D^sve_opt5_1_0to62] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b10 & sve_imm5_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Zd.D & sve_opt5_1_0to62 & Pg3 +{ + SVE_st1h(Zd.D, Pg3, Zn.D, sve_opt5_1_0to62); +} + +# st1h_z_p_bi.xml: ST1H (scalar plus immediate) variant SVE +# PATTERN xe480e000/mask=xff90e000 + +:st1h "{"^Zd.T_size_2122^"}", Pg3, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_size_2122 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Zd.T_size_2122 & Rn_GPR64xsp & sve_mul4_1_m8to7 & Pg3 +{ + SVE_st1h(Zd.T_size_2122, Pg3, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# st1h_z_p_br.xml: ST1H (scalar plus scalar) variant SVE +# PATTERN xe4804000/mask=xff80e000 + +:st1h "{"^Zd.T_size_2122^"}", Pg3, [Rn_GPR64xsp, Rm_GPR64, "lsl #1"] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_size_2122 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Zd.T_size_2122 & Rn_GPR64xsp & Rm_GPR64 & Pg3 +{ + SVE_st1h(Zd.T_size_2122, Pg3, Rn_GPR64xsp, Rm_GPR64); +} + +# st1h_z_p_bz.xml: ST1H (scalar plus vector) variant 32-bit scaled offset +# PATTERN xe4e08000/mask=xffe0a000 + +:st1h "{"^Zd.S^"}", Pg3, [Rn_GPR64xsp, Zm.S, sve_mod^" #1"] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b11 & sve_zm_1620 & sve_b_15=1 & sve_xs_14 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.S & Zd.S & sve_mod & Pg3 +{ + SVE_st1h(Zd.S, Pg3, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# st1h_z_p_bz.xml: ST1H (scalar plus vector) variant 32-bit unpacked scaled offset +# PATTERN xe4a08000/mask=xffe0a000 + +:st1h "{"^Zd.D^"}", Pg3, [Rn_GPR64xsp, Zm.D, sve_mod^" #1"] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_zm_1620 & sve_b_15=1 & sve_xs_14 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & sve_mod & Pg3 +{ + SVE_st1h(Zd.D, Pg3, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# st1h_z_p_bz.xml: ST1H (scalar plus vector) variant 32-bit unpacked unscaled offset +# PATTERN xe4808000/mask=xffe0a000 + +:st1h "{"^Zd.D^"}", Pg3, [Rn_GPR64xsp, Zm.D, sve_mod] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b00 & sve_zm_1620 & sve_b_15=1 & sve_xs_14 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & sve_mod & Pg3 +{ + SVE_st1h(Zd.D, Pg3, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# st1h_z_p_bz.xml: ST1H (scalar plus vector) variant 32-bit unscaled offset +# PATTERN xe4c08000/mask=xffe0a000 + +:st1h "{"^Zd.S^"}", Pg3, [Rn_GPR64xsp, Zm.S, sve_mod] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_xs_14 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.S & Zd.S & sve_mod & Pg3 +{ + SVE_st1h(Zd.S, Pg3, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# st1h_z_p_bz.xml: ST1H (scalar plus vector) variant 64-bit scaled offset +# PATTERN xe4a0a000/mask=xffe0e000 + +:st1h "{"^Zd.D^"}", Pg3, [Rn_GPR64xsp, Zm.D, "lsl #1"] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_zm_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & Pg3 +{ + SVE_st1h(Zd.D, Pg3, Rn_GPR64xsp, Zm.D); +} + +# st1h_z_p_bz.xml: ST1H (scalar plus vector) variant 64-bit unscaled offset +# PATTERN xe480a000/mask=xffe0e000 + +:st1h "{"^Zd.D^"}", Pg3, [Rn_GPR64xsp, Zm.D] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b00 & sve_zm_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & Pg3 +{ + SVE_st1h(Zd.D, Pg3, Rn_GPR64xsp, Zm.D); +} + +# st1w_z_p_ai.xml: ST1W (vector plus immediate) variant 32-bit element +# PATTERN xe560a000/mask=xffe0e000 + +:st1w "{"^Zd.S^"}", Pg3, [Zn.S^sve_opt5_1_0to124] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b11 & sve_imm5_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.S & Zd.S & sve_opt5_1_0to124 & Pg3 +{ + SVE_st1w(Zd.S, Pg3, Zn.S, sve_opt5_1_0to124); +} + +# st1w_z_p_ai.xml: ST1W (vector plus immediate) variant 64-bit element +# PATTERN xe540a000/mask=xffe0e000 + +:st1w "{"^Zd.D^"}", Pg3, [Zn.D^sve_opt5_1_0to124] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b10 & sve_imm5_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zt_0004 & Zn.D & Zd.D & sve_opt5_1_0to124 & Pg3 +{ + SVE_st1w(Zd.D, Pg3, Zn.D, sve_opt5_1_0to124); +} + +# st1w_z_p_bi.xml: ST1W (scalar plus immediate) variant SVE +# PATTERN xe500e000/mask=xff90e000 + +:st1w "{"^Zd.T_size_2122^"}", Pg3, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_size_2122 & sve_b_20=0 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Zd.T_size_2122 & Rn_GPR64xsp & sve_mul4_1_m8to7 & Pg3 +{ + SVE_st1w(Zd.T_size_2122, Pg3, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# st1w_z_p_br.xml: ST1W (scalar plus scalar) variant SVE +# PATTERN xe5004000/mask=xff80e000 + +:st1w "{"^Zd.T_size_2122^"}", Pg3, [Rn_GPR64xsp, Rm_GPR64, "lsl #2"] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_size_2122 & sve_rm_1620 & sve_b_1315=0b010 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Zd.T_size_2122 & Rn_GPR64xsp & Rm_GPR64 & Pg3 +{ + SVE_st1w(Zd.T_size_2122, Pg3, Rn_GPR64xsp, Rm_GPR64); +} + +# st1w_z_p_bz.xml: ST1W (scalar plus vector) variant 32-bit scaled offset +# PATTERN xe5608000/mask=xffe0a000 + +:st1w "{"^Zd.S^"}", Pg3, [Rn_GPR64xsp, Zm.S, sve_mod^" #2"] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b11 & sve_zm_1620 & sve_b_15=1 & sve_xs_14 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.S & Zd.S & sve_mod & Pg3 +{ + SVE_st1w(Zd.S, Pg3, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# st1w_z_p_bz.xml: ST1W (scalar plus vector) variant 32-bit unpacked scaled offset +# PATTERN xe5208000/mask=xffe0a000 + +:st1w "{"^Zd.D^"}", Pg3, [Rn_GPR64xsp, Zm.D, sve_mod^" #2"] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b01 & sve_zm_1620 & sve_b_15=1 & sve_xs_14 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & sve_mod & Pg3 +{ + SVE_st1w(Zd.D, Pg3, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# st1w_z_p_bz.xml: ST1W (scalar plus vector) variant 32-bit unpacked unscaled offset +# PATTERN xe5008000/mask=xffe0a000 + +:st1w "{"^Zd.D^"}", Pg3, [Rn_GPR64xsp, Zm.D, sve_mod] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b00 & sve_zm_1620 & sve_b_15=1 & sve_xs_14 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & sve_mod & Pg3 +{ + SVE_st1w(Zd.D, Pg3, Rn_GPR64xsp, Zm.D, sve_mod:1); +} + +# st1w_z_p_bz.xml: ST1W (scalar plus vector) variant 32-bit unscaled offset +# PATTERN xe5408000/mask=xffe0a000 + +:st1w "{"^Zd.S^"}", Pg3, [Rn_GPR64xsp, Zm.S, sve_mod] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b10 & sve_zm_1620 & sve_b_15=1 & sve_xs_14 & sve_b_13=0 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.S & Zd.S & sve_mod & Pg3 +{ + SVE_st1w(Zd.S, Pg3, Rn_GPR64xsp, Zm.S, sve_mod:1); +} + +# st1w_z_p_bz.xml: ST1W (scalar plus vector) variant 64-bit scaled offset +# PATTERN xe520a000/mask=xffe0e000 + +:st1w "{"^Zd.D^"}", Pg3, [Rn_GPR64xsp, Zm.D, "lsl #2"] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b01 & sve_zm_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & Pg3 +{ + SVE_st1w(Zd.D, Pg3, Rn_GPR64xsp, Zm.D); +} + +# st1w_z_p_bz.xml: ST1W (scalar plus vector) variant 64-bit unscaled offset +# PATTERN xe500a000/mask=xffe0e000 + +:st1w "{"^Zd.D^"}", Pg3, [Rn_GPR64xsp, Zm.D] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b00 & sve_zm_1620 & sve_b_1315=0b101 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zm.D & Zd.D & Pg3 +{ + SVE_st1w(Zd.D, Pg3, Rn_GPR64xsp, Zm.D); +} + +# st2b_z_p_bi.xml: ST2B (scalar plus immediate) variant SVE +# PATTERN xe430e000/mask=xfff0e000 + +:st2b "{"^Zt.B, Ztt.B^"}", Pg3, [Rn_GPR64xsp^sve_mul4_1_m16to14] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b01 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.B & Zt.B & Rn_GPR64xsp & sve_mul4_1_m16to14 & Pg3 +{ + SVE_st2b(Zt.B, Ztt.B, Pg3, Rn_GPR64xsp, sve_mul4_1_m16to14); +} + +# st2b_z_p_br.xml: ST2B (scalar plus scalar) variant SVE +# PATTERN xe4206000/mask=xffe0e000 + +:st2b "{"^Zt.B, Ztt.B^"}", Pg3, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b01 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.B & Zt.B & Rn_GPR64xsp & Rm_GPR64 & Pg3 +{ + SVE_st2b(Zt.B, Ztt.B, Pg3, Rn_GPR64xsp, Rm_GPR64); +} + +# st2d_z_p_bi.xml: ST2D (scalar plus immediate) variant SVE +# PATTERN xe5b0e000/mask=xfff0e000 + +:st2d "{"^Zt.D, Ztt.D^"}", Pg3, [Rn_GPR64xsp^sve_mul4_1_m16to14] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b01 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.D & Zt.D & Rn_GPR64xsp & sve_mul4_1_m16to14 & Pg3 +{ + SVE_st2d(Zt.D, Ztt.D, Pg3, Rn_GPR64xsp, sve_mul4_1_m16to14); +} + +# st2d_z_p_br.xml: ST2D (scalar plus scalar) variant SVE +# PATTERN xe5a06000/mask=xffe0e000 + +:st2d "{"^Zt.D, Ztt.D^"}", Pg3, [Rn_GPR64xsp, Rm_GPR64, "lsl #3"] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b01 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.D & Zt.D & Rn_GPR64xsp & Rm_GPR64 & Pg3 +{ + SVE_st2d(Zt.D, Ztt.D, Pg3, Rn_GPR64xsp, Rm_GPR64); +} + +# st2h_z_p_bi.xml: ST2H (scalar plus immediate) variant SVE +# PATTERN xe4b0e000/mask=xfff0e000 + +:st2h "{"^Zt.H, Ztt.H^"}", Pg3, [Rn_GPR64xsp^sve_mul4_1_m16to14] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.H & Zt.H & Rn_GPR64xsp & sve_mul4_1_m16to14 & Pg3 +{ + SVE_st2h(Zt.H, Ztt.H, Pg3, Rn_GPR64xsp, sve_mul4_1_m16to14); +} + +# st2h_z_p_br.xml: ST2H (scalar plus scalar) variant SVE +# PATTERN xe4a06000/mask=xffe0e000 + +:st2h "{"^Zt.H, Ztt.H^"}", Pg3, [Rn_GPR64xsp, Rm_GPR64, "lsl #1"] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b01 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.H & Zt.H & Rn_GPR64xsp & Rm_GPR64 & Pg3 +{ + SVE_st2h(Zt.H, Ztt.H, Pg3, Rn_GPR64xsp, Rm_GPR64); +} + +# st2w_z_p_bi.xml: ST2W (scalar plus immediate) variant SVE +# PATTERN xe530e000/mask=xfff0e000 + +:st2w "{"^Zt.S, Ztt.S^"}", Pg3, [Rn_GPR64xsp^sve_mul4_1_m16to14] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b01 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.S & Zt.S & Rn_GPR64xsp & sve_mul4_1_m16to14 & Pg3 +{ + SVE_st2w(Zt.S, Ztt.S, Pg3, Rn_GPR64xsp, sve_mul4_1_m16to14); +} + +# st2w_z_p_br.xml: ST2W (scalar plus scalar) variant SVE +# PATTERN xe5206000/mask=xffe0e000 + +:st2w "{"^Zt.S, Ztt.S^"}", Pg3, [Rn_GPR64xsp, Rm_GPR64, "lsl #2"] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b01 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.S & Zt.S & Rn_GPR64xsp & Rm_GPR64 & Pg3 +{ + SVE_st2w(Zt.S, Ztt.S, Pg3, Rn_GPR64xsp, Rm_GPR64); +} + +# st3b_z_p_bi.xml: ST3B (scalar plus immediate) variant SVE +# PATTERN xe450e000/mask=xfff0e000 + +:st3b "{"^Zt.B, Ztt.B, Zttt.B^"}", Pg3, [Rn_GPR64xsp^sve_mul4_1_m24to21] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b10 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.B & Zttt.B & Zt.B & Rn_GPR64xsp & sve_mul4_1_m24to21 & Pg3 +{ + SVE_st3b(Zt.B, Ztt.B, Zttt.B, Pg3, Rn_GPR64xsp, sve_mul4_1_m24to21); +} + +# st3b_z_p_br.xml: ST3B (scalar plus scalar) variant SVE +# PATTERN xe4406000/mask=xffe0e000 + +:st3b "{"^Zt.B, Ztt.B, Zttt.B^"}", Pg3, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b10 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.B & Zttt.B & Zt.B & Rn_GPR64xsp & Rm_GPR64 & Pg3 +{ + SVE_st3b(Zt.B, Ztt.B, Zttt.B, Pg3, Rn_GPR64xsp, Rm_GPR64); +} + +# st3d_z_p_bi.xml: ST3D (scalar plus immediate) variant SVE +# PATTERN xe5d0e000/mask=xfff0e000 + +:st3d "{"^Zt.D, Ztt.D, Zttt.D^"}", Pg3, [Rn_GPR64xsp^sve_mul4_1_m24to21] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b10 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.D & Zttt.D & Zt.D & Rn_GPR64xsp & sve_mul4_1_m24to21 & Pg3 +{ + SVE_st3d(Zt.D, Ztt.D, Zttt.D, Pg3, Rn_GPR64xsp, sve_mul4_1_m24to21); +} + +# st3d_z_p_br.xml: ST3D (scalar plus scalar) variant SVE +# PATTERN xe5c06000/mask=xffe0e000 + +:st3d "{"^Zt.D, Ztt.D, Zttt.D^"}", Pg3, [Rn_GPR64xsp, Rm_GPR64, "lsl #3"] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b10 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.D & Zttt.D & Zt.D & Rn_GPR64xsp & Rm_GPR64 & Pg3 +{ + SVE_st3d(Zt.D, Ztt.D, Zttt.D, Pg3, Rn_GPR64xsp, Rm_GPR64); +} + +# st3h_z_p_bi.xml: ST3H (scalar plus immediate) variant SVE +# PATTERN xe4d0e000/mask=xfff0e000 + +:st3h "{"^Zt.H, Ztt.H, Zttt.H^"}", Pg3, [Rn_GPR64xsp^sve_mul4_1_m24to21] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b10 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.H & Zttt.H & Zt.H & Rn_GPR64xsp & sve_mul4_1_m24to21 & Pg3 +{ + SVE_st3h(Zt.H, Ztt.H, Zttt.H, Pg3, Rn_GPR64xsp, sve_mul4_1_m24to21); +} + +# st3h_z_p_br.xml: ST3H (scalar plus scalar) variant SVE +# PATTERN xe4c06000/mask=xffe0e000 + +:st3h "{"^Zt.H, Ztt.H, Zttt.H^"}", Pg3, [Rn_GPR64xsp, Rm_GPR64, "lsl #1"] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b10 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.H & Zttt.H & Zt.H & Rn_GPR64xsp & Rm_GPR64 & Pg3 +{ + SVE_st3h(Zt.H, Ztt.H, Zttt.H, Pg3, Rn_GPR64xsp, Rm_GPR64); +} + +# st3w_z_p_bi.xml: ST3W (scalar plus immediate) variant SVE +# PATTERN xe550e000/mask=xfff0e000 + +:st3w "{"^Zt.S, Ztt.S, Zttt.S^"}", Pg3, [Rn_GPR64xsp^sve_mul4_1_m24to21] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b10 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.S & Zt.S & Zttt.S & Rn_GPR64xsp & sve_mul4_1_m24to21 & Pg3 +{ + SVE_st3w(Zt.S, Ztt.S, Zttt.S, Pg3, Rn_GPR64xsp, sve_mul4_1_m24to21); +} + +# st3w_z_p_br.xml: ST3W (scalar plus scalar) variant SVE +# PATTERN xe5406000/mask=xffe0e000 + +:st3w "{"^Zt.S, Ztt.S, Zttt.S^"}", Pg3, [Rn_GPR64xsp, Rm_GPR64, "lsl #2"] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b10 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.S & Zt.S & Zttt.S & Rn_GPR64xsp & Rm_GPR64 & Pg3 +{ + SVE_st3w(Zt.S, Ztt.S, Zttt.S, Pg3, Rn_GPR64xsp, Rm_GPR64); +} + +# st4b_z_p_bi.xml: ST4B (scalar plus immediate) variant SVE +# PATTERN xe470e000/mask=xfff0e000 + +:st4b "{"^Zt.B, Ztt.B, Zttt.B, Ztttt.B^"}", Pg3, [Rn_GPR64xsp^sve_mul4_1_m32to28] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b11 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.B & Zttt.B & Zt.B & Ztttt.B & Rn_GPR64xsp & sve_mul4_1_m32to28 & Pg3 +{ + SVE_st4b(Zt.B, Ztt.B, Zttt.B, Ztttt.B, Pg3, Rn_GPR64xsp, sve_mul4_1_m32to28); +} + +# st4b_z_p_br.xml: ST4B (scalar plus scalar) variant SVE +# PATTERN xe4606000/mask=xffe0e000 + +:st4b "{"^Zt.B, Ztt.B, Zttt.B, Ztttt.B^"}", Pg3, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b11 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.B & Zttt.B & Zt.B & Ztttt.B & Rn_GPR64xsp & Rm_GPR64 & Pg3 +{ + SVE_st4b(Zt.B, Ztt.B, Zttt.B, Ztttt.B, Pg3, Rn_GPR64xsp, Rm_GPR64); +} + +# st4d_z_p_bi.xml: ST4D (scalar plus immediate) variant SVE +# PATTERN xe5f0e000/mask=xfff0e000 + +:st4d "{"^Zt.D, Ztt.D, Zttt.D, Ztttt.D^"}", Pg3, [Rn_GPR64xsp^sve_mul4_1_m32to28] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b11 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.D & Zttt.D & Zt.D & Ztttt.D & Rn_GPR64xsp & sve_mul4_1_m32to28 & Pg3 +{ + SVE_st4d(Zt.D, Ztt.D, Zttt.D, Ztttt.D, Pg3, Rn_GPR64xsp, sve_mul4_1_m32to28); +} + +# st4d_z_p_br.xml: ST4D (scalar plus scalar) variant SVE +# PATTERN xe5e06000/mask=xffe0e000 + +:st4d "{"^Zt.D, Ztt.D, Zttt.D, Ztttt.D^"}", Pg3, [Rn_GPR64xsp, Rm_GPR64, "lsl #3"] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b11 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.D & Zttt.D & Zt.D & Ztttt.D & Rn_GPR64xsp & Rm_GPR64 & Pg3 +{ + SVE_st4d(Zt.D, Ztt.D, Zttt.D, Ztttt.D, Pg3, Rn_GPR64xsp, Rm_GPR64); +} + +# st4h_z_p_bi.xml: ST4H (scalar plus immediate) variant SVE +# PATTERN xe4f0e000/mask=xfff0e000 + +:st4h "{"^Zt.H, Ztt.H, Zttt.H, Ztttt.H^"}", Pg3, [Rn_GPR64xsp^sve_mul4_1_m32to28] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b11 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.H & Zttt.H & Zt.H & Ztttt.H & Rn_GPR64xsp & sve_mul4_1_m32to28 & Pg3 +{ + SVE_st4h(Zt.H, Ztt.H, Zttt.H, Ztttt.H, Pg3, Rn_GPR64xsp, sve_mul4_1_m32to28); +} + +# st4h_z_p_br.xml: ST4H (scalar plus scalar) variant SVE +# PATTERN xe4e06000/mask=xffe0e000 + +:st4h "{"^Zt.H, Ztt.H, Zttt.H, Ztttt.H^"}", Pg3, [Rn_GPR64xsp, Rm_GPR64, "lsl #1"] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b11 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.H & Zttt.H & Zt.H & Ztttt.H & Rn_GPR64xsp & Rm_GPR64 & Pg3 +{ + SVE_st4h(Zt.H, Ztt.H, Zttt.H, Ztttt.H, Pg3, Rn_GPR64xsp, Rm_GPR64); +} + +# st4w_z_p_bi.xml: ST4W (scalar plus immediate) variant SVE +# PATTERN xe570e000/mask=xfff0e000 + +:st4w "{"^Zt.S, Ztt.S, Zttt.S, Ztttt.S^"}", Pg3, [Rn_GPR64xsp^sve_mul4_1_m32to28] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b11 & sve_b_20=1 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.S & Zt.S & Zttt.S & Ztttt.S & Rn_GPR64xsp & sve_mul4_1_m32to28 & Pg3 +{ + SVE_st4w(Zt.S, Ztt.S, Zttt.S, Ztttt.S, Pg3, Rn_GPR64xsp, sve_mul4_1_m32to28); +} + +# st4w_z_p_br.xml: ST4W (scalar plus scalar) variant SVE +# PATTERN xe5606000/mask=xffe0e000 + +:st4w "{"^Zt.S, Ztt.S, Zttt.S, Ztttt.S^"}", Pg3, [Rn_GPR64xsp, Rm_GPR64, "lsl #2"] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b11 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Ztt.S & Zt.S & Zttt.S & Ztttt.S & Rn_GPR64xsp & Rm_GPR64 & Pg3 +{ + SVE_st4w(Zt.S, Ztt.S, Zttt.S, Ztttt.S, Pg3, Rn_GPR64xsp, Rm_GPR64); +} + +# stnt1b_z_p_bi.xml: STNT1B (scalar plus immediate) variant SVE +# PATTERN xe410e000/mask=xfff0e000 + +:stnt1b "{"^Zd.B^"}", Pg3, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2022=0b001 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zd.B & sve_mul4_1_m8to7 & Pg3 +{ + SVE_stnt1b(Zd.B, Pg3, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# stnt1b_z_p_br.xml: STNT1B (scalar plus scalar) variant SVE +# PATTERN xe4006000/mask=xffe0e000 + +:stnt1b "{"^Zd.B^"}", Pg3, [Rn_GPR64xsp, Rm_GPR64] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=0 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zd.B & Rm_GPR64 & Pg3 +{ + SVE_stnt1b(Zd.B, Pg3, Rn_GPR64xsp, Rm_GPR64); +} + +# stnt1d_z_p_bi.xml: STNT1D (scalar plus immediate) variant SVE +# PATTERN xe590e000/mask=xfff0e000 + +:stnt1d "{"^Zd.D^"}", Pg3, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2022=0b001 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zd.D & sve_mul4_1_m8to7 & Pg3 +{ + SVE_stnt1d(Zd.D, Pg3, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# stnt1d_z_p_br.xml: STNT1D (scalar plus scalar) variant SVE +# PATTERN xe5806000/mask=xffe0e000 + +:stnt1d "{"^Zd.D^"}", Pg3, [Rn_GPR64xsp, Rm_GPR64, "lsl #3"] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=1 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zd.D & Rm_GPR64 & Pg3 +{ + SVE_stnt1d(Zd.D, Pg3, Rn_GPR64xsp, Rm_GPR64); +} + +# stnt1h_z_p_bi.xml: STNT1H (scalar plus immediate) variant SVE +# PATTERN xe490e000/mask=xfff0e000 + +:stnt1h "{"^Zd.H^"}", Pg3, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2022=0b001 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zd.H & sve_mul4_1_m8to7 & Pg3 +{ + SVE_stnt1h(Zd.H, Pg3, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# stnt1h_z_p_br.xml: STNT1H (scalar plus scalar) variant SVE +# PATTERN xe4806000/mask=xffe0e000 + +:stnt1h "{"^Zd.H^"}", Pg3, [Rn_GPR64xsp, Rm_GPR64, "lsl #1"] +is sve_b_2531=0b1110010 & sve_b_24=0 & sve_b_23=1 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zd.H & Rm_GPR64 & Pg3 +{ + SVE_stnt1h(Zd.H, Pg3, Rn_GPR64xsp, Rm_GPR64); +} + +# stnt1w_z_p_bi.xml: STNT1W (scalar plus immediate) variant SVE +# PATTERN xe510e000/mask=xfff0e000 + +:stnt1w "{"^Zd.S^"}", Pg3, [Rn_GPR64xsp^sve_mul4_1_m8to7] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2022=0b001 & sve_imm4_1619 & sve_b_1315=0b111 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zd.S & sve_mul4_1_m8to7 & Pg3 +{ + SVE_stnt1w(Zd.S, Pg3, Rn_GPR64xsp, sve_mul4_1_m8to7); +} + +# stnt1w_z_p_br.xml: STNT1W (scalar plus scalar) variant SVE +# PATTERN xe5006000/mask=xffe0e000 + +:stnt1w "{"^Zd.S^"}", Pg3, [Rn_GPR64xsp, Rm_GPR64, "lsl #2"] +is sve_b_2531=0b1110010 & sve_b_24=1 & sve_b_23=0 & sve_b_2122=0b00 & sve_rm_1620 & sve_b_1315=0b011 & sve_pg_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & Zd.S & Rm_GPR64 & Pg3 +{ + SVE_stnt1w(Zd.S, Pg3, Rn_GPR64xsp, Rm_GPR64); +} + +# str_p_bi.xml: STR (predicate) variant SVE +# PATTERN xe5800000/mask=xffc0e010 + +:str Pd, [Rn_GPR64xsp^sve_mul9_2_m256to255] +is sve_b_2231=0b1110010110 & sve_imm9h_1621 & sve_b_1315=0b000 & sve_imm9l_1012 & sve_rn_0509 & sve_b_04=0 & sve_pt_0003 & Rn_GPR64xsp & sve_mul9_2_m256to255 & Pd +{ + SVE_str(Pd, Rn_GPR64xsp, sve_mul9_2_m256to255); +} + +# str_z_bi.xml: STR (vector) variant SVE +# PATTERN xe5804000/mask=xffc0e000 + +:str Zd, [Rn_GPR64xsp^sve_mul9_2_m256to255] +is sve_b_2231=0b1110010110 & sve_imm9h_1621 & sve_b_1315=0b010 & sve_imm9l_1012 & sve_rn_0509 & sve_zt_0004 & Rn_GPR64xsp & sve_mul9_2_m256to255 & Zd +{ + SVE_str(Zd, Rn_GPR64xsp, sve_mul9_2_m256to255); +} + +# sub_z_p_zz.xml: SUB (vectors, predicated) variant SVE +# PATTERN x04010000/mask=xff3fe000 + +:sub Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_sub(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# sub_z_zi.xml: SUB (immediate) variant SVE +# PATTERN x2521c000/mask=xff3fc000 + +:sub Zd.T, Zd.T_2, sve_shf8_1_0to255 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b100 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1415=0b11 & sve_sh_13 & sve_imm8_0512 & sve_zdn_0004 & sve_shift_13 & Zd.T & Zd.T_2 & sve_imm8_1_0to255 & sve_shf8_1_0to255 +{ + Zd.T = SVE_sub(Zd.T, Zd.T_2, sve_shf8_1_0to255, sve_shift_13:1); +} + +# sub_z_zz.xml: SUB (vectors, unpredicated) variant SVE +# PATTERN x04200400/mask=xff20fc00 + +:sub Zd.T, Zn.T, Zm.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b00 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T +{ + Zd.T = SVE_sub(Zd.T, Zn.T, Zm.T); +} + +# subr_z_p_zz.xml: SUBR (vectors) variant SVE +# PATTERN x04030000/mask=xff3fe000 + +:subr Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b000 & sve_b_1718=0b01 & sve_b_16=1 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_subr(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# subr_z_zi.xml: SUBR (immediate) variant SVE +# PATTERN x2523c000/mask=xff3fc000 + +:subr Zd.T, Zd.T_2, sve_shf8_1_0to255 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b100 & sve_b_1718=0b01 & sve_b_16=1 & sve_b_1415=0b11 & sve_sh_13 & sve_imm8_0512 & sve_zdn_0004 & sve_shift_13 & Zd.T & Zd.T_2 & sve_imm8_1_0to255 & sve_shf8_1_0to255 +{ + Zd.T = SVE_subr(Zd.T, Zd.T_2, sve_shf8_1_0to255, sve_shift_13:1); +} + +# sunpkhi_z_z.xml: SUNPKHI, SUNPKLO variant High half +# PATTERN x05313800/mask=xff3ffc00 + +:sunpkhi Zd.T, Zn.Tb +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1821=0b1100 & sve_b_17=0 & sve_b_16=1 & sve_b_1015=0b001110 & sve_zn_0509 & sve_zd_0004 & Zn.Tb & Zd.T +{ + Zd.T = SVE_sunpkhi(Zd.T, Zn.Tb); +} + +# sunpkhi_z_z.xml: SUNPKHI, SUNPKLO variant Low half +# PATTERN x05303800/mask=xff3ffc00 + +:sunpklo Zd.T, Zn.Tb +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1821=0b1100 & sve_b_17=0 & sve_b_16=0 & sve_b_1015=0b001110 & sve_zn_0509 & sve_zd_0004 & Zn.Tb & Zd.T +{ + Zd.T = SVE_sunpklo(Zd.T, Zn.Tb); +} + +# sxtb_z_p_z.xml: SXTB, SXTH, SXTW variant Byte +# PATTERN x0410a000/mask=xff3fe000 + +:sxtb Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_sxtb(Zd.T, Pg3_m, Zn.T); +} + +# sxtb_z_p_z.xml: SXTB, SXTH, SXTW variant Halfword +# PATTERN x0412a000/mask=xff3fe000 + +:sxth Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_sxth(Zd.T, Pg3_m, Zn.T); +} + +# sxtb_z_p_z.xml: SXTB, SXTH, SXTW variant Word +# PATTERN x0414a000/mask=xff3fe000 + +:sxtw Zd.D, Pg3_m, Zn.D +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Pg3_m +{ + Zd.D = SVE_sxtw(Zd.D, Pg3_m, Zn.D); +} + +# tbl_z_zz.xml: TBL variant SVE +# PATTERN x05203000/mask=xff20fc00 + +:tbl Zd.T, "{"^Zn.T^"}", Zm.T +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1015=0b001100 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T +{ + Zd.T = SVE_tbl(Zd.T, Zn.T, Zm.T); +} + +# trn1_p_pp.xml: TRN1, TRN2 (predicates) variant Even +# PATTERN x05205000/mask=xff30fe10 + +:trn1 Pd.T, Pn.T, Pm.T +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_2021=0b10 & sve_pm_1619 & sve_b_1315=0b010 & sve_b_12=1 & sve_b_11=0 & sve_b_10=0 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pn.T & Pd.T & Pm.T +{ + Pd.T = SVE_trn1(Pd.T, Pn.T, Pm.T); +} + +# trn1_p_pp.xml: TRN1, TRN2 (predicates) variant Odd +# PATTERN x05205400/mask=xff30fe10 + +:trn2 Pd.T, Pn.T, Pm.T +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_2021=0b10 & sve_pm_1619 & sve_b_1315=0b010 & sve_b_12=1 & sve_b_11=0 & sve_b_10=1 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pn.T & Pd.T & Pm.T +{ + Pd.T = SVE_trn2(Pd.T, Pn.T, Pm.T); +} + +# trn1_z_zz.xml: TRN1, TRN2 (vectors) variant Even +# PATTERN x05207000/mask=xff20fc00 + +:trn1 Zd.T, Zn.T, Zm.T +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b011 & sve_b_1112=0b10 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T +{ + Zd.T = SVE_trn1(Zd.T, Zn.T, Zm.T); +} + +# trn1_z_zz.xml: TRN1, TRN2 (vectors) variant Odd +# PATTERN x05207400/mask=xff20fc00 + +:trn2 Zd.T, Zn.T, Zm.T +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b011 & sve_b_1112=0b10 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T +{ + Zd.T = SVE_trn2(Zd.T, Zn.T, Zm.T); +} + +# uabd_z_p_zz.xml: UABD variant SVE +# PATTERN x040d0000/mask=xff3fe000 + +:uabd Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b001 & sve_b_18=1 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_uabd(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# uaddv_r_p_z.xml: UADDV variant SVE +# PATTERN x04012000/mask=xff3fe000 + +:uaddv Rd_FPR64, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b000 & sve_b_18=0 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3 +{ + Rd_FPR64 = SVE_uaddv(Rd_FPR64, Zn.T, Pg3); +} + +# ucvtf_z_p_z.xml: UCVTF variant 16-bit to half-precision +# PATTERN x6553a000/mask=xffffe000 + +:ucvtf Zd.H, Pg3_m, Zn.H +is sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b010 & sve_b_18=0 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.H & Pg3_m +{ + Zd.H = SVE_ucvtf(Zd.H, Pg3_m, Zn.H); +} + +# ucvtf_z_p_z.xml: UCVTF variant 32-bit to half-precision +# PATTERN x6555a000/mask=xffffe000 + +:ucvtf Zd.H, Pg3_m, Zn.S +is sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.H & Pg3_m +{ + Zd.H = SVE_ucvtf(Zd.H, Pg3_m, Zn.S); +} + +# ucvtf_z_p_z.xml: UCVTF variant 32-bit to single-precision +# PATTERN x6595a000/mask=xffffe000 + +:ucvtf Zd.S, Pg3_m, Zn.S +is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=0 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.S & Pg3_m +{ + Zd.S = SVE_ucvtf(Zd.S, Pg3_m, Zn.S); +} + +# ucvtf_z_p_z.xml: UCVTF variant 32-bit to double-precision +# PATTERN x65d1a000/mask=xffffe000 + +:ucvtf Zd.D, Pg3_m, Zn.S +is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b010 & sve_b_18=0 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.D & Pg3_m +{ + Zd.D = SVE_ucvtf(Zd.D, Pg3_m, Zn.S); +} + +# ucvtf_z_p_z.xml: UCVTF variant 64-bit to half-precision +# PATTERN x6557a000/mask=xffffe000 + +:ucvtf Zd.H, Pg3_m, Zn.D +is sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.H & Pg3_m +{ + Zd.H = SVE_ucvtf(Zd.H, Pg3_m, Zn.D); +} + +# ucvtf_z_p_z.xml: UCVTF variant 64-bit to single-precision +# PATTERN x65d5a000/mask=xffffe000 + +:ucvtf Zd.S, Pg3_m, Zn.D +is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.S & Pg3_m +{ + Zd.S = SVE_ucvtf(Zd.S, Pg3_m, Zn.D); +} + +# ucvtf_z_p_z.xml: UCVTF variant 64-bit to double-precision +# PATTERN x65d7a000/mask=xffffe000 + +:ucvtf Zd.D, Pg3_m, Zn.D +is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Pg3_m +{ + Zd.D = SVE_ucvtf(Zd.D, Pg3_m, Zn.D); +} + +# udiv_z_p_zz.xml: UDIV variant SVE +# PATTERN x04950000/mask=xffbfe000 + +:udiv Zd.T_sz, Pg3_m, Zd.T_sz_2, Zn.T_sz +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_sz_22 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T_sz & Zd.T_sz_2 & Zn.T_sz & Pg3_m +{ + Zd.T_sz = SVE_udiv(Zd.T_sz, Pg3_m, Zd.T_sz_2, Zn.T_sz); +} + +# udivr_z_p_zz.xml: UDIVR variant SVE +# PATTERN x04970000/mask=xffbfe000 + +:udivr Zd.T_sz, Pg3_m, Zd.T_sz_2, Zn.T_sz +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_sz_22 & sve_b_1921=0b010 & sve_b_18=1 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T_sz & Zd.T_sz_2 & Zn.T_sz & Pg3_m +{ + Zd.T_sz = SVE_udivr(Zd.T_sz, Pg3_m, Zd.T_sz_2, Zn.T_sz); +} + +# udot_z_zzz.xml: UDOT (vectors) variant SVE +# PATTERN x44800400/mask=xffa0fc00 + +:udot Zd.T_sz, Zn.Tb_sz, Zm.Tb_sz +is sve_b_2431=0b01000100 & sve_b_23=1 & sve_sz_22 & sve_b_21=0 & sve_zm_1620 & sve_b_1115=0b00000 & sve_b_10=1 & sve_zn_0509 & sve_zda_0004 & Zm.Tb_sz & Zd.T_sz & Zn.Tb_sz +{ + Zd.T_sz = SVE_udot(Zd.T_sz, Zn.Tb_sz, Zm.Tb_sz); +} + +# udot_z_zzzi.xml: UDOT (indexed) variant 32-bit +# PATTERN x44a00400/mask=xffe0fc00 + +:udot Zd.S, Zn.B, Zm3.B[sve_i2_1920] +is sve_b_2431=0b01000100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_i2_1920 & sve_zm_1618 & sve_b_1115=0b00000 & sve_b_10=1 & sve_zn_0509 & sve_zda_0004 & Zd.S & Zn.B & Zm3.B +{ + Zd.S = SVE_udot(Zd.S, Zn.B, Zm3.B, sve_i2_1920:1); +} + +# udot_z_zzzi.xml: UDOT (indexed) variant 64-bit +# PATTERN x44e00400/mask=xffe0fc00 + +:udot Zd.D, Zn.H, Zm4.H[sve_i1_20] +is sve_b_2431=0b01000100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_i1_20 & sve_zm_1619 & sve_b_1115=0b00000 & sve_b_10=1 & sve_zn_0509 & sve_zda_0004 & Zd.D & Zn.H & Zm4.H +{ + Zd.D = SVE_udot(Zd.D, Zn.H, Zm4.H, sve_i1_20:1); +} + +# umax_z_p_zz.xml: UMAX (vectors) variant SVE +# PATTERN x04090000/mask=xff3fe000 + +:umax Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_umax(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# umax_z_zi.xml: UMAX (immediate) variant SVE +# PATTERN x2529c000/mask=xff3fe000 + +:umax Zd.T, Zd.T_2, "#"^sve_imm8_1_0to255 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b101 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1415=0b11 & sve_b_13=0 & sve_imm8_0512 & sve_zdn_0004 & Zd.T & Zd.T_2 & sve_imm8_1_0to255 +{ + Zd.T = SVE_umax(Zd.T, Zd.T_2, sve_imm8_1_0to255:1); +} + +# umaxv_r_p_z.xml: UMAXV variant SVE +# PATTERN x04092000/mask=xff3fe000 + +:umaxv Rd_FPR8, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b00 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3 +{ + Rd_FPR8 = SVE_umaxv(Rd_FPR8, Pg3, Zn.T); +} + +# umaxv_r_p_z.xml: UMAXV variant SVE +# PATTERN x04092000/mask=xff3fe000 + +:umaxv Rd_FPR32, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b10 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3 +{ + Rd_FPR32 = SVE_umaxv(Rd_FPR32, Pg3, Zn.T); +} + +# umaxv_r_p_z.xml: UMAXV variant SVE +# PATTERN x04092000/mask=xff3fe000 + +:umaxv Rd_FPR16, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b01 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3 +{ + Rd_FPR16 = SVE_umaxv(Rd_FPR16, Pg3, Zn.T); +} + +# umaxv_r_p_z.xml: UMAXV variant SVE +# PATTERN x04092000/mask=xff3fe000 + +:umaxv Rd_FPR64, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b11 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3 +{ + Rd_FPR64 = SVE_umaxv(Rd_FPR64, Pg3, Zn.T); +} + +# umin_z_p_zz.xml: UMIN (vectors) variant SVE +# PATTERN x040b0000/mask=xff3fe000 + +:umin Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_umin(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# umin_z_zi.xml: UMIN (immediate) variant SVE +# PATTERN x252bc000/mask=xff3fe000 + +:umin Zd.T, Zd.T_2, "#"^sve_imm8_1_0to255 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b101 & sve_b_1718=0b01 & sve_b_16=1 & sve_b_1415=0b11 & sve_b_13=0 & sve_imm8_0512 & sve_zdn_0004 & Zd.T & Zd.T_2 & sve_imm8_1_0to255 +{ + Zd.T = SVE_umin(Zd.T, Zd.T_2, sve_imm8_1_0to255:1); +} + +# uminv_r_p_z.xml: UMINV variant SVE +# PATTERN x040b2000/mask=xff3fe000 + +:uminv Rd_FPR8, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b00 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3 +{ + Rd_FPR8 = SVE_uminv(Rd_FPR8, Pg3, Zn.T); +} + +# uminv_r_p_z.xml: UMINV variant SVE +# PATTERN x040b2000/mask=xff3fe000 + +:uminv Rd_FPR32, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b10 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3 +{ + Rd_FPR32 = SVE_uminv(Rd_FPR32, Pg3, Zn.T); +} + +# uminv_r_p_z.xml: UMINV variant SVE +# PATTERN x040b2000/mask=xff3fe000 + +:uminv Rd_FPR16, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b01 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3 +{ + Rd_FPR16 = SVE_uminv(Rd_FPR16, Pg3, Zn.T); +} + +# uminv_r_p_z.xml: UMINV variant SVE +# PATTERN x040b2000/mask=xff3fe000 + +:uminv Rd_FPR64, Pg3, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223=0b11 & sve_b_1921=0b001 & sve_b_18=0 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3 +{ + Rd_FPR64 = SVE_uminv(Rd_FPR64, Pg3, Zn.T); +} + +# umulh_z_p_zz.xml: UMULH variant SVE +# PATTERN x04130000/mask=xff3fe000 + +:umulh Zd.T, Pg3_m, Zd.T_2, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_18=0 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m +{ + Zd.T = SVE_umulh(Zd.T, Pg3_m, Zd.T_2, Zn.T); +} + +# uqadd_z_zi.xml: UQADD (immediate) variant SVE +# PATTERN x2525c000/mask=xff3fc000 + +:uqadd Zd.T, Zd.T_2, sve_shf8_1_0to255 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b100 & sve_b_1718=0b10 & sve_b_16=1 & sve_b_1415=0b11 & sve_sh_13 & sve_imm8_0512 & sve_zdn_0004 & sve_shift_13 & Zd.T & Zd.T_2 & sve_imm8_1_0to255 & sve_shf8_1_0to255 +{ + Zd.T = SVE_uqadd(Zd.T, Zd.T_2, sve_shf8_1_0to255, sve_shift_13:1); +} + +# uqadd_z_zz.xml: UQADD (vectors) variant SVE +# PATTERN x04201400/mask=xff20fc00 + +:uqadd Zd.T, Zn.T, Zm.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b10 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T +{ + Zd.T = SVE_uqadd(Zd.T, Zn.T, Zm.T); +} + +# uqdecb_r_rs.xml: UQDECB variant 32-bit +# PATTERN x0420fc00/mask=xfff0fc00 + +:uqdecb Rd_GPR32^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR32 = SVE_uqdecb(Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# uqdecb_r_rs.xml: UQDECB variant 64-bit +# PATTERN x0430fc00/mask=xfff0fc00 + +:uqdecb Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_uqdecb(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# uqdecd_r_rs.xml: UQDECD (scalar) variant 32-bit +# PATTERN x04e0fc00/mask=xfff0fc00 + +:uqdecd Rd_GPR32^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR32 = SVE_uqdecd(Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# uqdecd_r_rs.xml: UQDECD (scalar) variant 64-bit +# PATTERN x04f0fc00/mask=xfff0fc00 + +:uqdecd Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_uqdecd(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# uqdecd_z_zs.xml: UQDECD (vector) variant SVE +# PATTERN x04e0cc00/mask=xfff0fc00 + +:uqdecd Zd.D^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1215=0b1100 & sve_b_11=1 & sve_b_10=1 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.D & sve_imm4_1_1to16 & sve_mul_pattern +{ + Zd.D = SVE_uqdecd(Zd.D, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# uqdech_r_rs.xml: UQDECH (scalar) variant 32-bit +# PATTERN x0460fc00/mask=xfff0fc00 + +:uqdech Rd_GPR32^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR32 = SVE_uqdech(Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# uqdech_r_rs.xml: UQDECH (scalar) variant 64-bit +# PATTERN x0470fc00/mask=xfff0fc00 + +:uqdech Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_uqdech(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# uqdech_z_zs.xml: UQDECH (vector) variant SVE +# PATTERN x0460cc00/mask=xfff0fc00 + +:uqdech Zd.H^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1215=0b1100 & sve_b_11=1 & sve_b_10=1 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.H & sve_imm4_1_1to16 & sve_mul_pattern +{ + Zd.H = SVE_uqdech(Zd.H, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# uqdecp_r_p_r.xml: UQDECP (scalar) variant 32-bit +# PATTERN x252b8800/mask=xff3ffe00 + +:uqdecp Rd_GPR32, Pn.T +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1010 & sve_b_17=1 & sve_b_16=1 & sve_b_1115=0b10001 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_rdn_0004 & Pn.T & Rd_GPR32 +{ + Rd_GPR32 = SVE_uqdecp(Rd_GPR32, Pn.T); +} + +# uqdecp_r_p_r.xml: UQDECP (scalar) variant 64-bit +# PATTERN x252b8c00/mask=xff3ffe00 + +:uqdecp Rd_GPR64, Pn.T +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1010 & sve_b_17=1 & sve_b_16=1 & sve_b_1115=0b10001 & sve_b_10=1 & sve_b_09=0 & sve_pg_0508 & sve_rdn_0004 & Pn.T & Rd_GPR64 +{ + Rd_GPR64 = SVE_uqdecp(Rd_GPR64, Pn.T); +} + +# uqdecp_z_p_z.xml: UQDECP (vector) variant SVE +# PATTERN x252b8000/mask=xff3ffe00 + +:uqdecp Zd.T, Pn +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1010 & sve_b_17=1 & sve_b_16=1 & sve_b_1115=0b10000 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_zdn_0004 & Zd.T & Pn +{ + Zd.T = SVE_uqdecp(Zd.T, Pn); +} + +# uqdecw_r_rs.xml: UQDECW (scalar) variant 32-bit +# PATTERN x04a0fc00/mask=xfff0fc00 + +:uqdecw Rd_GPR32^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR32 = SVE_uqdecw(Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# uqdecw_r_rs.xml: UQDECW (scalar) variant 64-bit +# PATTERN x04b0fc00/mask=xfff0fc00 + +:uqdecw Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=1 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_uqdecw(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# uqdecw_z_zs.xml: UQDECW (vector) variant SVE +# PATTERN x04a0cc00/mask=xfff0fc00 + +:uqdecw Zd.S^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1215=0b1100 & sve_b_11=1 & sve_b_10=1 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.S & sve_imm4_1_1to16 & sve_mul_pattern +{ + Zd.S = SVE_uqdecw(Zd.S, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# uqincb_r_rs.xml: UQINCB variant 32-bit +# PATTERN x0420f400/mask=xfff0fc00 + +:uqincb Rd_GPR32^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR32 = SVE_uqincb(Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# uqincb_r_rs.xml: UQINCB variant 64-bit +# PATTERN x0430f400/mask=xfff0fc00 + +:uqincb Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_uqincb(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# uqincd_r_rs.xml: UQINCD (scalar) variant 32-bit +# PATTERN x04e0f400/mask=xfff0fc00 + +:uqincd Rd_GPR32^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR32 = SVE_uqincd(Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# uqincd_r_rs.xml: UQINCD (scalar) variant 64-bit +# PATTERN x04f0f400/mask=xfff0fc00 + +:uqincd Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_uqincd(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# uqincd_z_zs.xml: UQINCD (vector) variant SVE +# PATTERN x04e0c400/mask=xfff0fc00 + +:uqincd Zd.D^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1215=0b1100 & sve_b_11=0 & sve_b_10=1 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.D & sve_imm4_1_1to16 & sve_mul_pattern +{ + Zd.D = SVE_uqincd(Zd.D, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# uqinch_r_rs.xml: UQINCH (scalar) variant 32-bit +# PATTERN x0460f400/mask=xfff0fc00 + +:uqinch Rd_GPR32^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR32 = SVE_uqinch(Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# uqinch_r_rs.xml: UQINCH (scalar) variant 64-bit +# PATTERN x0470f400/mask=xfff0fc00 + +:uqinch Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_uqinch(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# uqinch_z_zs.xml: UQINCH (vector) variant SVE +# PATTERN x0460c400/mask=xfff0fc00 + +:uqinch Zd.H^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1215=0b1100 & sve_b_11=0 & sve_b_10=1 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.H & sve_imm4_1_1to16 & sve_mul_pattern +{ + Zd.H = SVE_uqinch(Zd.H, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# uqincp_r_p_r.xml: UQINCP (scalar) variant 32-bit +# PATTERN x25298800/mask=xff3ffe00 + +:uqincp Rd_GPR32, Pn.T +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1010 & sve_b_17=0 & sve_b_16=1 & sve_b_1115=0b10001 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_rdn_0004 & Pn.T & Rd_GPR32 +{ + Rd_GPR32 = SVE_uqincp(Rd_GPR32, Pn.T); +} + +# uqincp_r_p_r.xml: UQINCP (scalar) variant 64-bit +# PATTERN x25298c00/mask=xff3ffe00 + +:uqincp Rd_GPR64, Pn.T +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1010 & sve_b_17=0 & sve_b_16=1 & sve_b_1115=0b10001 & sve_b_10=1 & sve_b_09=0 & sve_pg_0508 & sve_rdn_0004 & Pn.T & Rd_GPR64 +{ + Rd_GPR64 = SVE_uqincp(Rd_GPR64, Pn.T); +} + +# uqincp_z_p_z.xml: UQINCP (vector) variant SVE +# PATTERN x25298000/mask=xff3ffe00 + +:uqincp Zd.T, Pn +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1010 & sve_b_17=0 & sve_b_16=1 & sve_b_1115=0b10000 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_zdn_0004 & Zd.T & Pn +{ + Zd.T = SVE_uqincp(Zd.T, Pn); +} + +# uqincw_r_rs.xml: UQINCW (scalar) variant 32-bit +# PATTERN x04a0f400/mask=xfff0fc00 + +:uqincw Rd_GPR32^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_b_20=0 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR32 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR32 = SVE_uqincw(Rd_GPR32, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# uqincw_r_rs.xml: UQINCW (scalar) variant 64-bit +# PATTERN x04b0f400/mask=xfff0fc00 + +:uqincw Rd_GPR64^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_b_20=1 & sve_imm4_1619 & sve_b_1215=0b1111 & sve_b_11=0 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern +{ + Rd_GPR64 = SVE_uqincw(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# uqincw_z_zs.xml: UQINCW (vector) variant SVE +# PATTERN x04a0c400/mask=xfff0fc00 + +:uqincw Zd.S^sve_mul_pattern +is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1215=0b1100 & sve_b_11=0 & sve_b_10=1 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.S & sve_imm4_1_1to16 & sve_mul_pattern +{ + Zd.S = SVE_uqincw(Zd.S, sve_mul_pattern, sve_imm4_1_1to16:1); +} + +# uqsub_z_zi.xml: UQSUB (immediate) variant SVE +# PATTERN x2527c000/mask=xff3fc000 + +:uqsub Zd.T, Zd.T_2, sve_shf8_1_0to255 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b100 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1415=0b11 & sve_sh_13 & sve_imm8_0512 & sve_zdn_0004 & sve_shift_13 & Zd.T & Zd.T_2 & sve_imm8_1_0to255 & sve_shf8_1_0to255 +{ + Zd.T = SVE_uqsub(Zd.T, Zd.T_2, sve_shf8_1_0to255, sve_shift_13:1); +} + +# uqsub_z_zz.xml: UQSUB (vectors) variant SVE +# PATTERN x04201c00/mask=xff20fc00 + +:uqsub Zd.T, Zn.T, Zm.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b11 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T +{ + Zd.T = SVE_uqsub(Zd.T, Zn.T, Zm.T); +} + +# uunpkhi_z_z.xml: UUNPKHI, UUNPKLO variant High half +# PATTERN x05333800/mask=xff3ffc00 + +:uunpkhi Zd.T, Zn.Tb +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1821=0b1100 & sve_b_17=1 & sve_b_16=1 & sve_b_1015=0b001110 & sve_zn_0509 & sve_zd_0004 & Zn.Tb & Zd.T +{ + Zd.T = SVE_uunpkhi(Zd.T, Zn.Tb); +} + +# uunpkhi_z_z.xml: UUNPKHI, UUNPKLO variant Low half +# PATTERN x05323800/mask=xff3ffc00 + +:uunpklo Zd.T, Zn.Tb +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1821=0b1100 & sve_b_17=1 & sve_b_16=0 & sve_b_1015=0b001110 & sve_zn_0509 & sve_zd_0004 & Zn.Tb & Zd.T +{ + Zd.T = SVE_uunpklo(Zd.T, Zn.Tb); +} + +# uxtb_z_p_z.xml: UXTB, UXTH, UXTW variant Byte +# PATTERN x0411a000/mask=xff3fe000 + +:uxtb Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_uxtb(Zd.T, Pg3_m, Zn.T); +} + +# uxtb_z_p_z.xml: UXTB, UXTH, UXTW variant Halfword +# PATTERN x0413a000/mask=xff3fe000 + +:uxth Zd.T, Pg3_m, Zn.T +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b01 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m +{ + Zd.T = SVE_uxth(Zd.T, Pg3_m, Zn.T); +} + +# uxtb_z_p_z.xml: UXTB, UXTH, UXTW variant Word +# PATTERN x0415a000/mask=xff3fe000 + +:uxtw Zd.D, Pg3_m, Zn.D +is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b10 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Pg3_m +{ + Zd.D = SVE_uxtw(Zd.D, Pg3_m, Zn.D); +} + +# uzp1_p_pp.xml: UZP1, UZP2 (predicates) variant Even +# PATTERN x05204800/mask=xff30fe10 + +:uzp1 Pd.T, Pn.T, Pm.T +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_2021=0b10 & sve_pm_1619 & sve_b_1315=0b010 & sve_b_12=0 & sve_b_11=1 & sve_b_10=0 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pn.T & Pd.T & Pm.T +{ + Pd.T = SVE_uzp1(Pd.T, Pn.T, Pm.T); +} + +# uzp1_p_pp.xml: UZP1, UZP2 (predicates) variant Odd +# PATTERN x05204c00/mask=xff30fe10 + +:uzp2 Pd.T, Pn.T, Pm.T +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_2021=0b10 & sve_pm_1619 & sve_b_1315=0b010 & sve_b_12=0 & sve_b_11=1 & sve_b_10=1 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pn.T & Pd.T & Pm.T +{ + Pd.T = SVE_uzp2(Pd.T, Pn.T, Pm.T); +} + +# uzp1_z_zz.xml: UZP1, UZP2 (vectors) variant Even +# PATTERN x05206800/mask=xff20fc00 + +:uzp1 Zd.T, Zn.T, Zm.T +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b011 & sve_b_1112=0b01 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T +{ + Zd.T = SVE_uzp1(Zd.T, Zn.T, Zm.T); +} + +# uzp1_z_zz.xml: UZP1, UZP2 (vectors) variant Odd +# PATTERN x05206c00/mask=xff20fc00 + +:uzp2 Zd.T, Zn.T, Zm.T +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b011 & sve_b_1112=0b01 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T +{ + Zd.T = SVE_uzp2(Zd.T, Zn.T, Zm.T); +} + +# whilele_p_p_rr.xml: WHILELE variant SVE +# PATTERN x25200410/mask=xff20ec10 + +:whilele Pd.T, Rn_GPR64, Rm_GPR64 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b000 & sve_sf_12=1 & sve_b_11=0 & sve_b_10=1 & sve_rn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Rn_GPR64 & Rm_GPR64 +{ + Pd.T = SVE_whilele(Pd.T, Rn_GPR64, Rm_GPR64); +} + +# whilele_p_p_rr.xml: WHILELE variant SVE +# PATTERN x25200410/mask=xff20ec10 + +:whilele Pd.T, Rn_GPR32, Rm_GPR32 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b000 & sve_sf_12=0 & sve_b_11=0 & sve_b_10=1 & sve_rn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Rn_GPR32 & Rm_GPR32 +{ + Pd.T = SVE_whilele(Pd.T, Rn_GPR32, Rm_GPR32); +} + +# whilelo_p_p_rr.xml: WHILELO variant SVE +# PATTERN x25200c00/mask=xff20ec10 + +:whilelo Pd.T, Rn_GPR64, Rm_GPR64 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b000 & sve_sf_12=1 & sve_b_11=1 & sve_b_10=1 & sve_rn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Rn_GPR64 & Rm_GPR64 +{ + Pd.T = SVE_whilelo(Pd.T, Rn_GPR64, Rm_GPR64); +} + +# whilelo_p_p_rr.xml: WHILELO variant SVE +# PATTERN x25200c00/mask=xff20ec10 + +:whilelo Pd.T, Rn_GPR32, Rm_GPR32 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b000 & sve_sf_12=0 & sve_b_11=1 & sve_b_10=1 & sve_rn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Rn_GPR32 & Rm_GPR32 +{ + Pd.T = SVE_whilelo(Pd.T, Rn_GPR32, Rm_GPR32); +} + +# whilels_p_p_rr.xml: WHILELS variant SVE +# PATTERN x25200c10/mask=xff20ec10 + +:whilels Pd.T, Rn_GPR64, Rm_GPR64 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b000 & sve_sf_12=1 & sve_b_11=1 & sve_b_10=1 & sve_rn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Rn_GPR64 & Rm_GPR64 +{ + Pd.T = SVE_whilels(Pd.T, Rn_GPR64, Rm_GPR64); +} + +# whilels_p_p_rr.xml: WHILELS variant SVE +# PATTERN x25200c10/mask=xff20ec10 + +:whilels Pd.T, Rn_GPR32, Rm_GPR32 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b000 & sve_sf_12=0 & sve_b_11=1 & sve_b_10=1 & sve_rn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Rn_GPR32 & Rm_GPR32 +{ + Pd.T = SVE_whilels(Pd.T, Rn_GPR32, Rm_GPR32); +} + +# whilelt_p_p_rr.xml: WHILELT variant SVE +# PATTERN x25200400/mask=xff20ec10 + +:whilelt Pd.T, Rn_GPR64, Rm_GPR64 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b000 & sve_sf_12=1 & sve_b_11=0 & sve_b_10=1 & sve_rn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Rn_GPR64 & Rm_GPR64 +{ + Pd.T = SVE_whilelt(Pd.T, Rn_GPR64, Rm_GPR64); +} + +# whilelt_p_p_rr.xml: WHILELT variant SVE +# PATTERN x25200400/mask=xff20ec10 + +:whilelt Pd.T, Rn_GPR32, Rm_GPR32 +is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=1 & sve_rm_1620 & sve_b_1315=0b000 & sve_sf_12=0 & sve_b_11=0 & sve_b_10=1 & sve_rn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Rn_GPR32 & Rm_GPR32 +{ + Pd.T = SVE_whilelt(Pd.T, Rn_GPR32, Rm_GPR32); +} + +# wrffr_f_p.xml: WRFFR variant SVE +# PATTERN x25289000/mask=xfffffe1f + +:wrffr Pn.B +is sve_b_3031=0b00 & sve_b_2429=0b100101 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b10 & sve_b_1019=0b1000100100 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_b_03=0 & sve_b_02=0 & sve_b_0001=0b00 & Pn.B +{ + SVE_wrffr(Pn.B); +} + +# zip1_p_pp.xml: ZIP1, ZIP2 (predicates) variant High halves +# PATTERN x05204400/mask=xff30fe10 + +:zip2 Pd.T, Pn.T, Pm.T +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_2021=0b10 & sve_pm_1619 & sve_b_1315=0b010 & sve_b_12=0 & sve_b_11=0 & sve_b_10=1 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pn.T & Pd.T & Pm.T +{ + Pd.T = SVE_zip2(Pd.T, Pn.T, Pm.T); +} + +# zip1_p_pp.xml: ZIP1, ZIP2 (predicates) variant Low halves +# PATTERN x05204000/mask=xff30fe10 + +:zip1 Pd.T, Pn.T, Pm.T +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_2021=0b10 & sve_pm_1619 & sve_b_1315=0b010 & sve_b_12=0 & sve_b_11=0 & sve_b_10=0 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pn.T & Pd.T & Pm.T +{ + Pd.T = SVE_zip1(Pd.T, Pn.T, Pm.T); +} + +# zip1_z_zz.xml: ZIP1, ZIP2 (vectors) variant High halves +# PATTERN x05206400/mask=xff20fc00 + +:zip2 Zd.T, Zn.T, Zm.T +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b011 & sve_b_1112=0b00 & sve_b_10=1 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T +{ + Zd.T = SVE_zip2(Zd.T, Zn.T, Zm.T); +} + +# zip1_z_zz.xml: ZIP1, ZIP2 (vectors) variant Low halves +# PATTERN x05206000/mask=xff20fc00 + +:zip1 Zd.T, Zn.T, Zm.T +is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b011 & sve_b_1112=0b00 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T +{ + Zd.T = SVE_zip1(Zd.T, Zn.T, Zm.T); +} diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AppleSilicon.ldefs b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AppleSilicon.ldefs new file mode 100644 index 0000000..f8c0e54 --- /dev/null +++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AppleSilicon.ldefs @@ -0,0 +1,18 @@ + + + + AppleSilicon ARM v8.5-A LE instructions, LE data, AMX extensions + + + + + + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARM.cspec b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM.cspec new file mode 100644 index 0000000..2a8c24b --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM.cspec @@ -0,0 +1,266 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ; + offset = *:1 (lr + r3); + r3 = zext(offset); + + + if (inbounds) goto ; + offset = *:1 (lr + r12); + r3 = zext(offset); + + + r3 = r3 * 2; + + r12 = lr + r3; + + ISAModeSwitch = (r12 & 1) != 1; + TB = ISAModeSwitch; + pc = r12 & 0xfffffffe; + goto [pc]; + ]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARM.dwarf b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM.dwarf new file mode 100644 index 0000000..0444463 --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM.dwarf @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARM.gdis b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM.gdis new file mode 100644 index 0000000..33429f8 --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM.gdis @@ -0,0 +1,41 @@ + + + + TMode + + + + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARM.ldefs b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM.ldefs new file mode 100644 index 0000000..3705510 --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM.ldefs @@ -0,0 +1,377 @@ + + + + + Generic ARM/Thumb v8 little endian + + + + + + + + + + + + + + + + Generic ARM/Thumb v8 little endian (Thumb is default) + + + + + + + + + + + Generic ARM/Thumb v8 little endian instructions and big endian data + + + + + + + Generic ARM/Thumb v8 big endian + + + + + + + + + + + + + + + Generic ARM/Thumb v8 big endian (Thumb is default) + + + + + + + + + Generic ARM/Thumb v7 little endian + + + + + + + + + + + Generic ARM/Thumb v7 little endian instructions and big endian data + + + + + + + Generic ARM/Thumb v7 big endian + + + + + + + + + + ARM Cortex / Thumb little endian + + + + + + + + + + + + ARM Cortex / Thumb big endian + + + + + + + + + + + Generic ARM/Thumb v6 little endian + + + + + + + + + + + + Generic ARM/Thumb v6 big endian + + + + + + + + + + + + Generic ARM/Thumb v5 little endian (T-variant) + + + + + + + + + + Generic ARM/Thumb v5 big endian (T-variant) + + + + + + + + + + Generic ARM v5 little endian + + + + + + + + Generic ARM v5 big endian + + + + + + + + Generic ARM/Thumb v4 little endian (T-variant) + + + + + + + + + Generic ARM/Thumb v4 big endian (T-variant) + + + + + + + + + Generic ARM v4 little endian + + + + + + + + + + + + Generic ARM v4 big endian + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARM.opinion b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM.opinion new file mode 100644 index 0000000..81cdb8a --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM.opinion @@ -0,0 +1,68 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARM.sinc b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM.sinc new file mode 100644 index 0000000..09f3181 --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM.sinc @@ -0,0 +1,302 @@ +# Specification for the ARM Version 4, 4T, 5, 5T, 5E +# The following boolean defines control specific support: T_VARIANT, VERSION_5, VERSION_5E + +define endian=$(ENDIAN); +define alignment=2; + +define space ram type=ram_space size=4 default; +define space register type=register_space size=4; + +define register offset=0x0020 size=4 [ r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 sp lr pc ]; +define register offset=0x0060 size=1 [ NG ZR CY OV tmpNG tmpZR tmpCY tmpOV shift_carry TB Q GE1 GE2 GE3 GE4 ]; +define register offset=0x0070 size=4 [ cpsr spsr ]; +define register offset=0x0080 size=4 [ mult_addr ]; # Special internal register for dealing with multiple stores/loads +define register offset=0x0084 size=4 [ r14_svc r13_svc spsr_svc ]; +define register offset=0x0090 size=8 [ mult_dat8 ]; # Special internal register for dealing with multiple stores/loads +define register offset=0x0090 size=16 [ mult_dat16 ]; # Special internal register for dealing with multiple stores/loads +define register offset=0x00A0 size=4 [ fpsr ]; # floating point state register (for FPA10 floating-point accelerator) +define register offset=0x00B0 size=1 [ ISAModeSwitch ]; # generic name for TB ThumbBit - set same as TB + +@define FPSCR_N "fpscr[31,1]" +@define FPSCR_Z "fpscr[30,1]" +@define FPSCR_C "fpscr[29,1]" +@define FPSCR_V "fpscr[28,1]" + +@if defined(VFPv2) || defined(VFPv3) || defined(SIMD) + define register offset=0x00B0 size=4 [ fpsid fpscr fpexc mvfr0 mvfr1 ]; +@endif +define register offset=0x0100 size=10 [ fp0 fp1 fp2 fp3 fp4 fp5 fp6 fp7 ]; # eight 80-bit floating registers + +# pseudo-registers for coprocessor calculations +define register offset=0x0200 size=4 [ cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 cr8 cr9 cr10 cr11 cr12 cr13 cr14 cr15 ]; + +# Advanced SIMD and VFP extension registers +@if defined(VFPv2) || defined(VFPv3) + +@if ENDIAN == "little" + define register offset=0x0300 size=4 [ s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 + s16 s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31 ]; +@else # ENDIAN == "big" + define register offset=0x0300 size=4 [ s31 s30 s29 s28 s27 s26 s25 s24 s23 s22 s21 s20 s19 s18 s17 s16 + s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 ]; +@endif # ENDIAN = "big" + +@endif # VFPv2 || VFPv3 + +@if defined(VFPv2) + +@if ENDIAN == "little" + define register offset=0x0300 size=8 [ d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ]; +@else # ENDIAN == "big" + define register offset=0x0300 size=8 [ d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ]; +@endif # ENDIAN = "big" + +@endif # VFPv2 + +@if defined(SIMD) || defined(VFPv3) + +@if ENDIAN == "little" + define register offset=0x0300 size=8 [ d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 + d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 ]; +@else # ENDIAN == "big" + define register offset=0x0300 size=8 [ d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 + d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ]; +@endif # ENDIAN = "big" + +@endif # SIMD || VFPv3 + +@if defined(SIMD) + +@if ENDIAN == "little" + define register offset=0x0300 size=16 [ q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 ]; +@else # ENDIAN == "big" + define register offset=0x0300 size=16 [ q15 q14 q13 q12 q11 q10 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 ]; +@endif # ENDIAN = "big" + +@endif # SIMD + +# Define context bits +# WARNING: when adjusting context keep compiler packing in mind +# and make sure fields do not span a 32-bit boundary before or +# after context packing +define register offset=0x00 size=8 contextreg; +define context contextreg +@ifdef T_VARIANT + TMode = (0,0) # 1 if in Thumb instruction decode mode + T = (0,0) # exact copy (alias!) of TMode + LowBitCodeMode = (0,0) # 1 if low bit of instruction address is set on a branch + ISA_MODE = (0,0) # 1 for Thumb instruction decode mode +@endif + LRset = (1,1) noflow # 1 if the instruction right before was a mov lr,pc + REToverride = (2,2) noflow # 1 if the instruction should be a branch not a return + CALLoverride = (3,3) noflow # 1 if the call should actually be a jump +@if defined(VERSION_6T2) || defined(VERSION_7) + TEEMode = (4,4) # 1 if in ThumbEE mode, changes some instruction behavior, and makes some instructions invalid + condit = (5,13) noflow # both base and shift + cond_mask = (10,13) # base condition + cond_full = (6,9) # full condition + cond_true = (9,9) # true if this condition should be tested for true + cond_base = (6,8) # shift mask for controlling shift + cond_shft = (9,13) # mask and lower bit of it condition field + itmode = (5,5) # true if in ITBlock mode + +@endif + + # Transient context bits + counter = (14,18) # 0 to 7 counter (for building variable length register lists) +# dreg = (17,21) # D register (attached, for building register lists) +# sreg = (17,21) # S register (attached, for building register lists) + regNum = (19,23) # D register number (see dreg) + counter2 = (24,26) # 0 to 7 counter (for building variable length register lists) +# dreg2 = (25,29) # 2nd D register (attached, for building register lists) +# sreg2 = (25,29) # 2nd S register (attached, for building register lists) + reg2Num = (27,31) # 2nd D register number (see dreg2) +# --- do not allow any field to span 32-bit boundary --- + regInc = (32,33) # Pair register increment + ARMcond = (34,34) # ARM conditional instruction + ARMcondCk = (35,35) # Finished ARM condition check phase +; + +define pcodeop coprocessor_function; +define pcodeop coprocessor_function2; +define pcodeop coprocessor_load; +define pcodeop coprocessor_load2; +define pcodeop coprocessor_loadlong; +define pcodeop coprocessor_loadlong2; +define pcodeop coprocessor_moveto; +define pcodeop coprocessor_moveto2; +define pcodeop coprocessor_movefromRt; +define pcodeop coprocessor_movefromRt2; +define pcodeop coprocessor_movefrom2; +define pcodeop coprocessor_store; +define pcodeop coprocessor_store2; +define pcodeop coprocessor_storelong; +define pcodeop coprocessor_storelong2; +define pcodeop software_interrupt; +define pcodeop software_bkpt; +define pcodeop software_udf; +define pcodeop software_hlt; +define pcodeop software_hvc; +define pcodeop software_smc; + +# CPS methods (Version 6) +define pcodeop setUserMode; +define pcodeop setFIQMode; +define pcodeop setIRQMode; +define pcodeop setSupervisorMode; +define pcodeop setMonitorMode; +define pcodeop setAbortMode; +define pcodeop setUndefinedMode; +define pcodeop setSystemMode; +define pcodeop enableIRQinterrupts; +define pcodeop enableFIQinterrupts; +define pcodeop enableDataAbortInterrupts; +define pcodeop disableIRQinterrupts; +define pcodeop disableFIQinterrupts; +define pcodeop isFIQinterruptsEnabled; +define pcodeop isIRQinterruptsEnabled; +define pcodeop disableDataAbortInterrupts; +define pcodeop hasExclusiveAccess; +define pcodeop isCurrentModePrivileged; +define pcodeop setThreadModePrivileged; +define pcodeop isThreadMode; + +define pcodeop jazelle_branch; +define pcodeop ClearExclusiveLocal; +define pcodeop HintDebug; + +define pcodeop DataMemoryBarrier; +define pcodeop DataSynchronizationBarrier; + +define pcodeop secureMonitorCall; + +define pcodeop WaitForEvent; +define pcodeop WaitForInterrupt; + +define pcodeop HintYield; +define pcodeop InstructionSynchronizationBarrier; + +define pcodeop HintPreloadData; +define pcodeop HintPreloadDataForWrite; +define pcodeop HintPreloadInstruction; + +define pcodeop SignedSaturate; +define pcodeop SignedDoesSaturate; +define pcodeop UnsignedSaturate; +define pcodeop UnsignedDoesSaturate; +define pcodeop Absolute; +define pcodeop ReverseBitOrder; +define pcodeop SendEvent; +define pcodeop setEndianState; + +macro affectflags() { + CY = tmpCY; ZR = tmpZR; NG = tmpNG; OV = tmpOV; +} + +macro affect_resflags() { + ZR = tmpZR; NG = tmpNG; +} + +macro SetThumbMode(value) { + ISAModeSwitch = value; + TB = ISAModeSwitch; +} + +# +# simple branch, not inter-working +macro BranchWritePC(addr) { + pc = addr; +} + +# +# Interworking branch, ARM<->Thumb +macro BXWritePC(addr) { + SetThumbMode((addr & 0x1) != 0); + local tmp = addr & 0xfffffffe; + pc = tmp; +} + +# +# Branch depends on version +macro LoadWritePC(addr) { +@if defined(VERSION_5) + BXWritePC(addr); +@else + BranchWritePC(addr); +@endif +} + +# Branch depends on version +macro ALUWritePC(addr) { +@if defined(VERSION_7) + BXWritePC(addr); +@else + BranchWritePC(addr); +@endif +} + +@if defined(T_VARIANT) + +ItCond: is TMode=1 { } +CheckInIT_CZNO: is TMode=1 { CY = tmpCY; ZR = tmpZR; NG = tmpNG; OV = tmpOV; } # in older, arms always affect flags +CheckInIT_CZN: is TMode=1 { CY = tmpCY; ZR = tmpZR; NG = tmpNG; } # in older, arms always affect flags +CheckInIT_ZN: is TMode=1 { ZR = tmpZR; NG = tmpNG; } # in older, arms always affect flags + +@endif + +@if defined(VERSION_6T2) || defined(VERSION_7) + +# conditionals for instruction following IT Block +thfcc: "eq" is cond_full=0 { local tmp:1 = (ZR!=0); export tmp; } +thfcc: "ne" is cond_full=1 { local tmp:1 = (ZR==0); export tmp; } +thfcc: "cs" is cond_full=2 { local tmp:1 = (CY!=0); export tmp; } +thfcc: "cc" is cond_full=3 { local tmp:1 = (CY==0); export tmp; } +thfcc: "mi" is cond_full=4 { local tmp:1 = (NG!=0); export tmp; } +thfcc: "pl" is cond_full=5 { local tmp:1 = (NG==0); export tmp; } +thfcc: "vs" is cond_full=6 { local tmp:1 = (OV!=0); export tmp; } +thfcc: "vc" is cond_full=7 { local tmp:1 = (OV==0); export tmp; } +thfcc: "hi" is cond_full=8 { local tmp:1 = CY && !ZR; export tmp; } +thfcc: "ls" is cond_full=9 { local tmp:1 = !CY || ZR; export tmp; } +thfcc: "ge" is cond_full=10 { local tmp:1 = (NG == OV); export tmp; } +thfcc: "lt" is cond_full=11 { local tmp:1 = (NG != OV); export tmp; } +thfcc: "gt" is cond_full=12 { local tmp:1 = !ZR && (NG == OV); export tmp; } +thfcc: "le" is cond_full=13 { local tmp:1 = ZR || (NG != OV); export tmp; } +thfcc: "al" is cond_full=14 { local tmp:1 = 1; export tmp; } #can happen +#thfcc: "nv" is cond_full=15 { local tmp:1 = 0; export tmp; } #unpredictable, shouldn't happen + + +# no ITcondition +ItCond: is TMode=1 & itmode=0 & cond_mask=0 {} +# ITBlock then/else case - the condition being tested is modified by the shift below +ItCond: "."thfcc is TMode=1 & itmode=0 & cond_mask & thfcc [ itmode=1; globalset(inst_next,condit);] + { if (!thfcc) goto inst_next; } + +# last ITBlock then/else case - the condition being tested is modified by the shift below +ItCond: "."thfcc is TMode=1 & itmode=0 & cond_mask=8 & thfcc + { if (!thfcc) goto inst_next; } + +# certain Thumb instructions don't affect all flags in the IT block +CheckInIT_CZNO: is TMode=1 & itmode=1 & cond_mask { } # Do nothing to the flag bits +CheckInIT_CZNO: is TMode=1 & itmode=0 & cond_mask { } # Do nothing to the flag bits +CheckInIT_CZNO: "s" is TMode=1 & itmode=0 & cond_mask=0 { CY = tmpCY; ZR = tmpZR; NG = tmpNG; OV = tmpOV; } + +CheckInIT_CZN: is TMode=1 & itmode=1 & cond_mask { } # Do nothing to the flag bits +CheckInIT_CZN: is TMode=1 & itmode=0 & cond_mask { } # Do nothing to the flag bits +CheckInIT_CZN: "s" is TMode=1 & itmode=0 & cond_mask=0 { CY = tmpCY; ZR = tmpZR; NG = tmpNG; } + +CheckInIT_ZN: is TMode=1 & itmode=1 & cond_mask { } # Do nothing to the flag bits +CheckInIT_ZN: is TMode=1 & itmode=0 & cond_mask { } # Do nothing to the flag bits +CheckInIT_ZN: "s" is TMode=1 & itmode=0 & cond_mask=0 { ZR = tmpZR; NG = tmpNG; } + + +:^instruction is itmode=1 & cond_mask=8 & instruction [ condit=0; ] {} +:^instruction is itmode=1 & cond_mask & instruction [ cond_shft=cond_shft << 1; itmode=0; ]{} + +@endif # defined(VERSION_6T2) || defined(VERSION_7) + +@include "ARMinstructions.sinc" + +# THUMB instructions +@ifdef T_VARIANT +@include "ARMTHUMBinstructions.sinc" +@endif diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARM4_be.slaspec b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM4_be.slaspec new file mode 100644 index 0000000..ef190b1 --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM4_be.slaspec @@ -0,0 +1,5 @@ + +@define ENDIAN "big" + +@include "ARM.sinc" + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARM4_le.slaspec b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM4_le.slaspec new file mode 100644 index 0000000..ee66cfc --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM4_le.slaspec @@ -0,0 +1,5 @@ + +@define ENDIAN "little" + +@include "ARM.sinc" + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARM4t_be.slaspec b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM4t_be.slaspec new file mode 100644 index 0000000..1e56f79 --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM4t_be.slaspec @@ -0,0 +1,6 @@ + +@define ENDIAN "big" +@define T_VARIANT "" + +@include "ARM.sinc" + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARM4t_le.slaspec b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM4t_le.slaspec new file mode 100644 index 0000000..712b636 --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM4t_le.slaspec @@ -0,0 +1,6 @@ + +@define ENDIAN "little" +@define T_VARIANT "" + +@include "ARM.sinc" + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARM5_be.slaspec b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM5_be.slaspec new file mode 100644 index 0000000..c490b01 --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM5_be.slaspec @@ -0,0 +1,7 @@ + +@define ENDIAN "big" +@define VERSION_5 "" +@define VERSION_5E "" + +@include "ARM.sinc" + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARM5_le.slaspec b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM5_le.slaspec new file mode 100644 index 0000000..48f9cf7 --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM5_le.slaspec @@ -0,0 +1,7 @@ + +@define ENDIAN "little" +@define VERSION_5 "" +@define VERSION_5E "" + +@include "ARM.sinc" + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARM5t_be.slaspec b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM5t_be.slaspec new file mode 100644 index 0000000..dbd9cc1 --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM5t_be.slaspec @@ -0,0 +1,9 @@ + +@define ENDIAN "big" +@define T_VARIANT "" +@define VERSION_5 "" +@define VERSION_5E "" + +@include "ARM.sinc" + + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARM5t_le.slaspec b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM5t_le.slaspec new file mode 100644 index 0000000..ae5bc1d --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM5t_le.slaspec @@ -0,0 +1,8 @@ + +@define ENDIAN "little" +@define T_VARIANT "" +@define VERSION_5 "" +@define VERSION_5E "" + +@include "ARM.sinc" + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARM6_be.slaspec b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM6_be.slaspec new file mode 100644 index 0000000..02983a4 --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM6_be.slaspec @@ -0,0 +1,12 @@ + +@define ENDIAN "big" +@define T_VARIANT "" +@define VERSION_5 "" +@define VERSION_5E "" +@define VERSION_6 "" +@define VERSION_6K "" +@define VERSION_6T2 "" +@define VFPv2 "" + +@include "ARM.sinc" + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARM6_le.slaspec b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM6_le.slaspec new file mode 100644 index 0000000..f45a510 --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM6_le.slaspec @@ -0,0 +1,12 @@ + +@define ENDIAN "little" +@define T_VARIANT "" +@define VERSION_5 "" +@define VERSION_5E "" +@define VERSION_6 "" +@define VERSION_6K "" +@define VERSION_6T2 "" +@define VFPv2 "" + +@include "ARM.sinc" + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARM7_be.slaspec b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM7_be.slaspec new file mode 100644 index 0000000..768216a --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM7_be.slaspec @@ -0,0 +1,16 @@ + +@define ENDIAN "big" +@define T_VARIANT "" +@define VERSION_5 "" +@define VERSION_5E "" +@define VERSION_6 "" +@define VERSION_6K "" +@define VERSION_6T2 "" +@define VERSION_7 "" +@define VERSION_7M "" +@define SIMD "" +@define VFPv3 "" +@define VFPv4 "" + +@include "ARM.sinc" + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARM7_le.slaspec b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM7_le.slaspec new file mode 100644 index 0000000..965278c --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM7_le.slaspec @@ -0,0 +1,16 @@ + +@define ENDIAN "little" +@define T_VARIANT "" +@define VERSION_5 "" +@define VERSION_5E "" +@define VERSION_6 "" +@define VERSION_6K "" +@define VERSION_6T2 "" +@define VERSION_7 "" +@define VERSION_7M "" +@define SIMD "" +@define VFPv3 "" +@define VFPv4 "" + +@include "ARM.sinc" + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARM8_be.slaspec b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM8_be.slaspec new file mode 100644 index 0000000..62d990b --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM8_be.slaspec @@ -0,0 +1,17 @@ + +@define ENDIAN "big" +@define T_VARIANT "" +@define VERSION_5 "" +@define VERSION_5E "" +@define VERSION_6 "" +@define VERSION_6K "" +@define VERSION_6T2 "" +@define VERSION_7 "" +@define VERSION_7M "" +@define VERSION_8 "" +@define SIMD "" +@define VFPv3 "" +@define VFPv4 "" + +@include "ARM.sinc" + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARM8_le.slaspec b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM8_le.slaspec new file mode 100644 index 0000000..8765268 --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM8_le.slaspec @@ -0,0 +1,17 @@ + +@define ENDIAN "little" +@define T_VARIANT "" +@define VERSION_5 "" +@define VERSION_5E "" +@define VERSION_6 "" +@define VERSION_6K "" +@define VERSION_6T2 "" +@define VERSION_7 "" +@define VERSION_7M "" +@define VERSION_8 "" +@define SIMD "" +@define VFPv3 "" +@define VFPv4 "" + +@include "ARM.sinc" + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARMCortex.pspec b/python/icicle/Ghidra/Processors/ARM/data/languages/ARMCortex.pspec new file mode 100644 index 0000000..e6bf29b --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARMCortex.pspec @@ -0,0 +1,42 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc b/python/icicle/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc new file mode 100644 index 0000000..5925d13 --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc @@ -0,0 +1,5331 @@ +# Specification for the THUMB Version 2 +# This closely follows +# "Architecture Reference Manual" Second Edition Edited by David Seal + +# +# WARNING NOTE: Be very careful taking a subpiece or truncating a register with :# or (#) +# The LEBE hybrid language causes endian issues if you do not assign the register to a temp +# variable and then take a subpiece or truncate. +# + +define token instr2 (16) + part2op=(11,15) # this second instruction token is needed for the + part2J1=(13,13) + part2J2=(11,11) + part2cond=(6,9) + part2imm6=(0,5) + part2S=(10,10) + part2imm11=(0,10) + part2imm10=(0,9) + part2off=(0,10) # bl and blx instructions which use 2 16-bit instructions + part2off_10=(1,10) # blx instruction which switches to ARM mode + part2c1415=(14,15) + part2c1212=(12,12) + part2c0615=(6,15) + part2Rt=(12,15) + part2c0011=(0,11) + part2c0909=(9,9) + part2c0808=(8,8) + part2c0707=(7,7) + part2c0505=(5,5) + part2c0404=(4,4) + part2Rd0003=(0,3) +; + +define token instrThumb (16) + op4=(4,15) + op6=(6,15) + op7=(7,15) + op8=(8,15) + op9=(9,15) + op11=(11,15) + op12=(12,15) + op0=(0,15) + sop0407=(4,7) + sop0507=(5,7) + sop0508=(5,8) + sop0003=(0,3) + sop0608=(6,8) + sop0610=(6,10) + + sopit=(0,7) + + Ra1215=(12,15) + Rd0002=(0,2) + Rd0003=(0,3) + Rd0810=(8,10) + Rd0811=(8,11) + Rn0002=(0,2) + Rn0003=(0,3) + Rn0305=(3,5) + Rn0810=(8,10) + Rm0305=(3,5) + Rm0306=(3,6) + Rm0608=(6,8) + Rm0003=(0,3) + Rs0305=(3,5) + Rt1215=(12,15) + Rt0811=(8,11) + + thI9=(9,9) + thP8=(8,8) + thH8=(8,8) + thL8=(8,8) + thU7=(7,7) + thB6=(6,6) + thN6=(6,6) + thS6=(6,6) + thW5=(5,5) + thL4=(4,4) + + thCRd=(12,15) + thCRn=(0,3) + thCRm=(0,3) + + hrn0002=(0,2) + hrm0305=(3,5) + rm0306=(3,6) + hrd0002=(0,2) + + immed3=(6,8) + immed5=(6,10) + immed6=(0,5) + immed7=(0,6) + immed8=(0,7) + + immed12_i=(10,10) + immed12_imm3=(12,14) + immed12_imm8=(0,7) + + soffset8=(0,7) signed + offset10=(0,9) + offset10S=(10,10) + offset11=(0,10) + soffset11=(0,10) signed + offset12=(0,11) + + thcond=(8,11) + thcpn=(8,11) + thopcode1=(4,7) + thopcode2=(5,7) + l07=(7,7) + l11=(11,11) + h1=(7,7) + h2=(6,6) + R=(8,8) + sbz=(0,2) + thwbit=(5,5) + + th_psrmask=(8,11) + + addr_pbit=(10,10) + addr_ubit=(9,9) + addr_wbit=(8,8) + addr_puw =(8,10) + addr_puw1 =(5,8) + + thsrsMode=(0,4) + + fcond=(4,7) + + throt=(4,6) + + imm3_12=(12,14) + + imm3_shft=(12,14) + imm2_shft=(6,7) + + imm5=(3,7) + + sysm=(0,7) + sysm37=(3,7) + sysm02=(0,2) + + + thc0001=(0,1) + thc0002=(0,2) + thc0003=(0,3) + thc0004=(0,4) + thc0005=(0,5) + thc0006=(0,6) + thc0007=(0,7) + thc0011=(0,11) + thc0107=(1,7) + thc0207=(2,7) + thc0307=(3,7) + thc0407=(4,7) + thc0405=(4,5) + thc0409=(4,9) + thc0506=(5,6) + thc0507=(5,7) + thc0607=(6,7) + thc0810=(8,10) + thc0811=(8,11) + thc0910=(9,10) + thc1414=(14,14) + thc1313=(13,13) + thc1212=(12,12) + thc1214=(12,14) + thc1111=(11,11) + thc1010=(10,10) + thc0909=(9,9) + thc0808=(8,8) + thc0707=(7,7) + thc0606=(6,6) + thc0505=(5,5) + thc0404=(4,4) + thc0303=(3,3) + thc0202=(2,2) + thc0101=(1,1) + thc0000=(0,0) + thc0115=(1,15) + thc0215=(2,15) + thc0315=(3,15) + thc0415=(4,15) + thc0515=(5,15) + thc0615=(6,15) + thc0715=(7,15) + thc0815=(8,15) + thc0915=(9,15) + thc1015=(10,15) + thc1112=(11,12) + thc1115=(11,15) + thc1215=(12,15) + thc1315=(13,15) + thc1415=(14,15) + thc1515=(15,15) +; + +attach variables [ Rd0002 Rd0810 Rn0002 Rn0305 Rn0810 Rm0305 Rm0608 Rs0305 ] + [ r0 r1 r2 r3 r4 r5 r6 r7 ]; + +attach variables [ Rm0003 Rm0306 Rd0811 Rn0003 Rt1215 Rt0811 Ra1215 Rd0003 part2Rt part2Rd0003 ] [ r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 sp lr pc ]; + +attach variables [ thCRn thCRd thCRm ] [ cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 cr8 cr9 cr10 cr11 cr12 cr13 cr14 cr15 ]; + +attach names [ thcpn ] [ p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 ]; + +attach variables [ hrn0002 hrm0305 hrd0002 ] + [ r8 r9 r10 r11 r12 sp lr pc ]; + +macro th_addflags(op1,op2) { + tmpCY = carry(op1,op2); + tmpOV = scarry(op1,op2); +} + +#See ARM Architecture reference section "Pseudocode details of addition and subtraction" +macro th_add_with_carry_flags(op1,op2){ + local CYz = zext(CY); + local result = op1 + op2; + tmpCY = carry( op1, op2 ) || carry( result, CYz ); + tmpOV = scarry( op1, op2) ^^ scarry( result, CYz ); +} + +#Note: used for subtraction op1 - (op2 + !CY) +#sets tmpCY if there is NO borrow +macro th_sub_with_carry_flags(op1, op2){ + local result = op1 - op2; + tmpCY = (op1 > op2) || (result < zext(CY)); + tmpOV = sborrow(op1,op2) ^^ sborrow(result,zext(!CY)); +} + + +macro th_test_flags(result){ + ZR = (result == 0); + NG = (result s< 0); + CY = shift_carry; +} + +# Note (unlike x86) carry flag is SET if there is NO borrow +macro th_subflags(op1,op2) { + tmpCY = op2 <= op1; + tmpOV = sborrow(op1,op2); +} +macro th_subflags0(op2) { + tmpCY = op2 == 0; + tmpOV = sborrow(0,op2); +} + + + +macro resflags(result) { + tmpNG = result s< 0; + tmpZR = result == 0; +} + +macro th_logicflags() { + tmpCY = shift_carry; + tmpOV = OV; +} + +macro th_affectflags() { + CY = tmpCY; ZR = tmpZR; NG = tmpNG; OV = tmpOV; +} + +############################################################################### + +# conditionals for the branch instruction + +thcc: "eq" is thcond=0 { tmp:1 = (ZR!=0); export tmp; } +thcc: "ne" is thcond=1 { tmp:1 = (ZR==0); export tmp; } +thcc: "cs" is thcond=2 { tmp:1 = (CY!=0); export tmp; } +thcc: "cc" is thcond=3 { tmp:1 = (CY==0); export tmp; } +thcc: "mi" is thcond=4 { tmp:1 = (NG!=0); export tmp; } +thcc: "pl" is thcond=5 { tmp:1 = (NG==0); export tmp; } +thcc: "vs" is thcond=6 { tmp:1 = (OV!=0); export tmp; } +thcc: "vc" is thcond=7 { tmp:1 = (OV==0); export tmp; } +thcc: "hi" is thcond=8 { tmp:1 = CY && !ZR; export tmp; } +thcc: "ls" is thcond=9 { tmp:1 = !CY || ZR; export tmp; } +thcc: "ge" is thcond=10 { tmp:1 = (NG == OV); export tmp; } +thcc: "lt" is thcond=11 { tmp:1 = (NG != OV); export tmp; } +thcc: "gt" is thcond=12 { tmp:1 = !ZR && (NG == OV); export tmp; } +thcc: "le" is thcond=13 { tmp:1 = ZR || (NG != OV); export tmp; } +# thcc: "AL" is thcond=14 { tmp = 1; export tmp; } +# thcc: "NV" is thcond=15 { tmp = 0; export tmp; } + +@define THCC "thcc & (thc1515=0 | thc1414=0 | thc1313=0)" + + +@if defined(VERSION_6T2) || defined(VERSION_7) + +part2thcc: "eq" is part2cond=0 { tmp:1 = (ZR!=0); export tmp; } +part2thcc: "ne" is part2cond=1 { tmp:1 = (ZR==0); export tmp; } +part2thcc: "cs" is part2cond=2 { tmp:1 = (CY!=0); export tmp; } +part2thcc: "cc" is part2cond=3 { tmp:1 = (CY==0); export tmp; } +part2thcc: "mi" is part2cond=4 { tmp:1 = (NG!=0); export tmp; } +part2thcc: "pl" is part2cond=5 { tmp:1 = (NG==0); export tmp; } +part2thcc: "vs" is part2cond=6 { tmp:1 = (OV!=0); export tmp; } +part2thcc: "vc" is part2cond=7 { tmp:1 = (OV==0); export tmp; } +part2thcc: "hi" is part2cond=8 { tmp:1 = CY && !ZR; export tmp; } +part2thcc: "ls" is part2cond=9 { tmp:1 = !CY || ZR; export tmp; } +part2thcc: "ge" is part2cond=10 { tmp:1 = (NG == OV); export tmp; } +part2thcc: "lt" is part2cond=11 { tmp:1 = (NG != OV); export tmp; } +part2thcc: "gt" is part2cond=12 { tmp:1 = !ZR && (NG == OV); export tmp; } +part2thcc: "le" is part2cond=13 { tmp:1 = ZR || (NG != OV); export tmp; } +# part2thcc: "AL" is part2cond=14 { tmp = 1; export tmp; } +# part2thcc: "NV" is part2cond=15 { tmp = 0; export tmp; } + +@define PART2THCC "part2thcc & (part2c0909=0 | part2c0808=0 | part2c0707=0)" + +@endif # defined(VERSION_6T2) || defined(VERSION_7) + + +@if defined(VERSION_6T2) || defined(VERSION_7) + +# conditionals for IT Block +# Marvel at the UGLINESS: the p-code for pairs (eq,ne) (cs,cc) (mi,pl), etc. are the same +# The IT block decoding fills in the complement (if necessary) based on the IT mask bit for the instruction +it_thfcc: "eq" is fcond=0 { tmp:1 = (ZR!=0); export tmp; } +it_thfcc: "ne" is fcond=1 { tmp:1 = (ZR!=0); export tmp; } +it_thfcc: "cs" is fcond=2 { tmp:1 = (CY!=0); export tmp; } +it_thfcc: "cc" is fcond=3 { tmp:1 = (CY!=0); export tmp; } +it_thfcc: "mi" is fcond=4 { tmp:1 = (NG!=0); export tmp; } +it_thfcc: "pl" is fcond=5 { tmp:1 = (NG!=0); export tmp; } +it_thfcc: "vs" is fcond=6 { tmp:1 = (OV!=0); export tmp; } +it_thfcc: "vc" is fcond=7 { tmp:1 = (OV!=0); export tmp; } +it_thfcc: "hi" is fcond=8 { tmp:1 = CY && !ZR; export tmp; } +it_thfcc: "ls" is fcond=9 { tmp:1 = CY && !ZR; export tmp; } +it_thfcc: "ge" is fcond=10 { tmp:1 = (NG == OV); export tmp; } +it_thfcc: "lt" is fcond=11 { tmp:1 = (NG == OV); export tmp; } +it_thfcc: "gt" is fcond=12 { tmp:1 = !ZR && (NG == OV); export tmp; } +it_thfcc: "le" is fcond=13 { tmp:1 = !ZR && (NG == OV); export tmp; } +it_thfcc: "al" is fcond=14 { tmp:1 = 1; export tmp; } + +@define IT_THFCC "it_thfcc & (thc0707=0 | thc0606=0 | thc0505=0 | thc0404=0)" + +ByteRotate: "#"^rot is throt [rot = throt << 3; ] { export *[const]:1 rot; } + +thSBIT_CZNO: is thc0404=0 { } # Do nothing to the flag bits +thSBIT_CZNO: "s" is thc0404=1 { CY = tmpCY; ZR = tmpZR; NG = tmpNG; OV = tmpOV; } +thSBIT_CZN: is thc0404=0 { } # Do nothing to the flags bits +thSBIT_CZN: "s" is thc0404=1 {CY = tmpCY; ZR = tmpZR; NG = tmpNG;} +thSBIT_ZN: is thc0404=0 { } # Do nothing to the flag bits +thSBIT_ZN: "s" is thc0404=1 { ZR = tmpZR; NG = tmpNG; } + +@endif # defined(VERSION_6T2) || defined(VERSION_7) + + +# Addressing modes +# The capitalized fields are raw register addressing modes + +Hrd0002: Rd0002 is Rd0002 & h1=0 { export Rd0002; } +Hrd0002: hrd0002 is hrd0002 & h1=1 { export hrd0002; } +Hrd0002: pc is pc & hrd0002=7 & h1=1 { tmp:4 = inst_start + 4; export tmp; } + +Hrn0002: Rn0002 is Rn0002 & h1=0 { export Rn0002; } +Hrn0002: hrn0002 is hrn0002 & h1=1 { export hrn0002; } +Hrn0002: pc is pc & hrn0002=7 & h1=1 { tmp:4 = inst_start + 4; export tmp; } + +Hrm0305: Rm0305 is Rm0305 & h2=0 { export Rm0305; } +Hrm0305: hrm0305 is hrm0305 & h2=1 { export hrm0305; } +Hrm0305: pc is pc & hrm0305=7 & h2=1 { tmp:4 = inst_start + 4; export tmp; } + +@if defined(VERSION_6T2) || defined(VERSION_7) +Immed8_4: "#"^immval is immed8 [ immval = immed8 * 4; ] { export *[const]:4 immval; } +Immed4: "#"^thc0003 is thc0003 { export *[const]:4 thc0003; } +@endif + +Immed8: "#"^immed8 is immed8 { export *[const]:4 immed8; } +Immed3: "#"^immed3 is immed3 { export *[const]:4 immed3; } + +Pcrel8: [reloc] is immed8 + [ reloc = ((inst_start+4) $and 0xfffffffc) + 4*immed8; ] +{ + # don't export as an address, may be PIC code, and would add spurious symbols. + export *[const]:4 reloc; +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +Pcrel8_s8: [reloc] is immed8 + [ reloc = ((inst_start+4) $and 0xfffffffc) + 4*immed8; ] +{ + export *:8 reloc; +} +@endif # defined(VERSION_6T2) || defined(VERSION_7) + + +Sprel8: sp,"#"^immval is sp & immed8 [ immval = immed8 * 4; ] { local tmp = sp + immval; export tmp; } +Immed7_4: "#"^immval is immed7 [ immval = immed7 * 4; ] { tmp:4 = immval; export tmp; } +Immed5: "#"^immed5 is immed5 { export *[const]:4 immed5; } + + +@if defined(VERSION_6T2) || defined(VERSION_7) + +Immed12: "#"^immed12 is immed12_i; immed12_imm3 & immed12_imm8 + [ immed12=(immed12_i<<11) | (immed12_imm3<<8) | (immed12_imm8); ] +{ + export *[const]:4 immed12; +} + +Immed16: "#"^immed16 is immed12_i & sop0003; immed12_imm3 & immed12_imm8 + [ immed16 = (sop0003 << 12) | (immed12_i<<11) | (immed12_imm3<<8) | (immed12_imm8); ] +{ + export *[const]:2 immed16; +} + +PcrelImmed12Addr: reloc is immed12_i; immed12_imm3 & immed12_imm8 + [ reloc = ((inst_start+4) $and 0xfffffffc) + ((immed12_i<<11) | (immed12_imm3<<8) | (immed12_imm8)); ] +{ + # don't export as an address, may be PIC code, and would add spurious symbols. + export *[const]:4 reloc; +} + +NegPcrelImmed12Addr: reloc is immed12_i; immed12_imm3 & immed12_imm8 + [ reloc = ((inst_start+4) $and 0xfffffffc) - ((immed12_i<<11) | (immed12_imm3<<8) | (immed12_imm8)); ] +{ + # don't export as an address, may be PIC code, and would add spurious symbols. + export *[const]:4 reloc; +} + +PcrelOffset12: [reloc] is thc0707=1; offset12 + [ reloc = ((inst_start+4) $and 0xfffffffc) + offset12; ] +{ + export *:4 reloc; +} +PcrelOffset12: [reloc] is thc0707=0; offset12 + [ reloc = ((inst_start+4) $and 0xfffffffc) - offset12; ] +{ + export *:4 reloc; +} + +@endif # defined(VERSION_6T2) || defined(VERSION_7) + + +# decode thumb immediate12 encoded value + +@if defined(VERSION_6T2) || defined(VERSION_7) + +ThumbExpandImm12: "#"^imm32 is immed12_i=0 ; thc1414=0 & immed12_imm3=0 & immed12_imm8 + [ imm32=immed12_imm8 $and 0xff; ] +{ + tmp:4 = imm32; shift_carry = CY; export tmp; +} +ThumbExpandImm12: "#"^imm32 is immed12_i=0 ; thc1414=0 & immed12_imm3=1 & immed12_imm8 + [ imm32=(immed12_imm8<<16) | (immed12_imm8); ] +{ + tmp:4 = imm32; shift_carry = CY; export tmp; +} +ThumbExpandImm12: "#"^imm32 is immed12_i=0 ; thc1414=0 & immed12_imm3=2 & immed12_imm8 + [ imm32=(immed12_imm8<<24) | (immed12_imm8<<8); ] +{ + tmp:4 = imm32; shift_carry = CY; export tmp; +} +ThumbExpandImm12: "#"^imm32 is immed12_i=0 ; thc1414=0 & immed12_imm3=3 & immed12_imm8 + [ imm32=(immed12_imm8<<24) | (immed12_imm8<<16) | (immed12_imm8<<8) | (immed12_imm8); ] +{ + tmp:4 = imm32; shift_carry = CY; export tmp; +} +ThumbExpandImm12: "#"^imm32 is immed12_i=0 ; immed12_imm3 & thc0707 & immed7 + [ imm32=(((0x80+immed7)<<(32-((immed12_imm3<<1)|thc0707)))|((0x80+immed7)>>(((immed12_imm3<<1)|thc0707)))) $and 0xffffffff; ] +{ + tmp:4 = imm32; local tmp1 = (tmp >> 31); shift_carry = tmp1(0); export tmp; +} +ThumbExpandImm12: "#"^imm32 is immed12_i=1 ; immed12_imm3 & thc0707 & immed7 + [ imm32=(((0x80+immed7)<<(32-(16+((immed12_imm3<<1)|thc0707))))|((0x80+immed7)>>((16+((immed12_imm3<<1)|thc0707))))) $and 0xffffffff; ] +{ + tmp:4 = imm32; local tmp1 = (tmp >> 31); shift_carry = tmp1(0); export tmp; +} + +@endif # defined(VERSION_6T2) || defined(VERSION_7) + +@if defined(VERSION_6T2) || defined(VERSION_7) + +thLsbImm: "#"^lsb is imm3_shft & imm2_shft [ lsb= (imm3_shft<<2) | imm2_shft; ] { tmp:4 = lsb; export tmp; } +thMsbImm: "#"^thc0004 is thc0004 { tmp:4 = thc0004; export tmp; } +thWidthMinus1: "#"^width is thc0004 [ width = thc0004 + 1; ] { tmp:4 = thc0004; export tmp; } +thBitWidth: "#"^w is imm3_shft & imm2_shft & thc0004 [ w = thc0004 - ((imm3_shft<<2) | imm2_shft) + 1; ] { tmp:4 = w; export tmp; } + +@endif # VERSION_6T2 || VERSION_7 + + +##################### +###### thshift2 ###### +##################### + +@if defined(VERSION_6T2) || defined(VERSION_7) + +thshift2: Rm0003 is imm3_shft=0 & imm2_shft=0 & thc0405=0 & Rm0003 +{ + shift_carry = CY; export Rm0003; +} + +thshift2: Rm0003, "lsl #"^shftval is imm3_shft & imm2_shft & thc0405=0 & Rm0003 + [ shftval=(imm3_shft<<2) | (imm2_shft); ] +{ + local tmp1=(Rm0003>>(32-shftval))&1; shift_carry=tmp1(0); local tmp2=Rm0003<>31); shift_carry=tmp1(0); tmp2:4=0; export tmp2; +} + +thshift2: Rm0003, "lsr #"^shftval is imm3_shft & imm2_shft & thc0405=1 & Rm0003 + [ shftval=(imm3_shft<<2) | (imm2_shft); ] +{ + local tmp1=(Rm0003>>(shftval-1))&1; shift_carry=tmp1(0); local tmp2=Rm0003>>shftval; export tmp2; +} + +thshift2: Rm0003, "asr #32" is imm3_shft=0 & imm2_shft=0 & thc0405=2 & Rm0003 +{ + local tmp1=(Rm0003>>31); shift_carry=tmp1(0); local tmp2 = Rm0003 s>> 32; export tmp2; +} + +thshift2: Rm0003, "asr #"^shftval is imm3_shft & imm2_shft & thc0405=2 & Rm0003 + [ shftval=(imm3_shft<<2) | (imm2_shft); ] +{ + local tmp1=(Rm0003>>(shftval-1))&1; shift_carry=tmp1(0); local tmp2=Rm0003 s>> shftval; export tmp2; +} + +thshift2: Rm0003, "rrx" is imm3_shft=0 & imm2_shft=0 & thc0405=3 & Rm0003 +{ + local tmp1=Rm0003&1; shift_carry=tmp1(0); local tmp2 = (zext(CY)<<31)|(Rm0003>>1); export tmp2; +} + +thshift2: Rm0003, "ror #"^shftval is imm3_shft & imm2_shft & thc0405=3 & Rm0003 + [ shftval=(imm3_shft<<2) | (imm2_shft); ] +{ + local tmp1=(Rm0003>>shftval)|(Rm0003<<(32-shftval)); local tmp2=tmp1 >> 31; shift_carry=tmp2(0); export tmp1; +} + +@endif # VERSION_6T2 || VERSION_7 + +Addr5: reloc is imm5 & thc0909 + [ reloc = inst_start + 4 + ((thc0909 << 6) | (imm5 << 1)); ] +{ + export *:4 reloc; +} + +Addr8: reloc is soffset8 + [ reloc = (inst_start+4) + 2*soffset8; ] +{ + export *:4 reloc; +} + +Addr11: reloc is soffset11 + [ reloc = (inst_start+4) + 2*soffset11; ] +{ + export *:4 reloc; +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +ThAddr20: reloc is part2S=1 & part2imm6; part2J1 & part2J2 & part2imm11 + [ reloc = inst_start + 4 + ((-1 << 20) $or (part2J2 << 19) $or (part2J1 << 18) $or (part2imm6 << 12) $or (part2imm11 << 1)); ] +{ + export *:4 reloc; +} + +ThAddr20: reloc is part2S=0 & part2imm6; part2J1 & part2J2 & part2imm11 + [ reloc = inst_start + 4 + ((part2J2 << 19) $or (part2J1 << 18) $or (part2imm6 << 12) $or (part2imm11 << 1)); ] +{ + export *:4 reloc; +} + +@endif # defined(VERSION_6T2) || defined(VERSION_7) + +ThAddr24: reloc is offset10S=0 & offset10; part2J1 & part2J2 & part2off + [ reloc = inst_start + 4 + (((part2J1 $xor 1) << 23) $or ((part2J2 $xor 1) << 22) $or (offset10 << 12) $or (part2off << 1)); ] +{ + export *:4 reloc; +} + +ThAddr24: reloc is offset10S=1 & offset10; part2J1 & part2J2 & part2off + [ reloc = inst_start + 4 + ((-1 << 24) $or (part2J1 << 23) $or (part2J2 << 22) $or (offset10 << 12) $or (part2off << 1)); ] +{ + export *:4 reloc; +} + +@if defined(VERSION_5) + +ThArmAddr23: reloc is offset10S=0 & offset10; part2J1 & part2J2 & part2off_10 + [ reloc = ((inst_start + 4) $and 0xfffffffc) + (((part2J1 $xor 1) << 23) $or ((part2J2 $xor 1) << 22) $or (offset10 << 12) $or (part2off_10 << 2)); ] +{ + export *:4 reloc; +} + +ThArmAddr23: reloc is offset10S=1 & offset10; part2J1 & part2J2 & part2off_10 + [ reloc = ((inst_start + 4) $and 0xfffffffc) + ((-1 << 24) $or (part2J1 << 23) $or (part2J2 << 22) $or (offset10 << 12) $or (part2off_10 << 2)); ] +{ + export *:4 reloc; +} + +@endif # VERSION_5 + + +Rn_exclaim: Rn0810 is Rn0810 & thc0810=0 & thc0000=1 { mult_addr = Rn0810; export Rn0810; } +Rn_exclaim: Rn0810 is Rn0810 & thc0810=1 & thc0101=1 { mult_addr = Rn0810; export Rn0810; } +Rn_exclaim: Rn0810 is Rn0810 & thc0810=2 & thc0202=1 { mult_addr = Rn0810; export Rn0810; } +Rn_exclaim: Rn0810 is Rn0810 & thc0810=3 & thc0303=1 { mult_addr = Rn0810; export Rn0810; } +Rn_exclaim: Rn0810 is Rn0810 & thc0810=4 & thc0404=1 { mult_addr = Rn0810; export Rn0810; } +Rn_exclaim: Rn0810 is Rn0810 & thc0810=5 & thc0505=1 { mult_addr = Rn0810; export Rn0810; } +Rn_exclaim: Rn0810 is Rn0810 & thc0810=6 & thc0606=1 { mult_addr = Rn0810; export Rn0810; } +Rn_exclaim: Rn0810 is Rn0810 & thc0810=7 & thc0707=1 { mult_addr = Rn0810; export Rn0810; } +Rn_exclaim: Rn0810! is Rn0810 & thc0810 { mult_addr = Rn0810; export Rn0810; } + +Rn_exclaim_WB: is Rn0810 & thc0810=0 & thc0000=1 { } +Rn_exclaim_WB: is Rn0810 & thc0810=1 & thc0101=1 { } +Rn_exclaim_WB: is Rn0810 & thc0810=2 & thc0202=1 { } +Rn_exclaim_WB: is Rn0810 & thc0810=3 & thc0303=1 { } +Rn_exclaim_WB: is Rn0810 & thc0810=4 & thc0404=1 { } +Rn_exclaim_WB: is Rn0810 & thc0810=5 & thc0505=1 { } +Rn_exclaim_WB: is Rn0810 & thc0810=6 & thc0606=1 { } +Rn_exclaim_WB: is Rn0810 & thc0810=7 & thc0707=1 { } +Rn_exclaim_WB: is Rn0810 & thc0810 { Rn0810 = mult_addr; } + +# ldlist is the list of registers to be loaded or popped +LdRtype0: r0 is thc0000=1 & r0 & thc0107=0 { r0 = *mult_addr; mult_addr = mult_addr + 4; } +LdRtype0: r0, is thc0000=1 & r0 { r0 = *mult_addr; mult_addr = mult_addr + 4; } +LdRtype0: is thc0000=0 { } +LdRtype1: LdRtype0^r1 is LdRtype0 & thc0101=1 & r1 & thc0207=0 { r1 = *mult_addr; mult_addr = mult_addr + 4; } +LdRtype1: LdRtype0^r1, is LdRtype0 & thc0101=1 & r1 { r1 = *mult_addr; mult_addr = mult_addr + 4; } +LdRtype1: LdRtype0 is LdRtype0 & thc0101=0 { } +LdRtype2: LdRtype1^r2 is LdRtype1 & thc0202=1 & r2 & thc0307=0 { r2 = *mult_addr; mult_addr = mult_addr + 4; } +LdRtype2: LdRtype1^r2, is LdRtype1 & thc0202=1 & r2 { r2 = *mult_addr; mult_addr = mult_addr + 4; } +LdRtype2: LdRtype1 is LdRtype1 & thc0202=0 { } +LdRtype3: LdRtype2^r3 is LdRtype2 & thc0303=1 & r3 & thc0407=0 { r3 = *mult_addr; mult_addr = mult_addr + 4; } +LdRtype3: LdRtype2^r3, is LdRtype2 & thc0303=1 & r3 { r3 = *mult_addr; mult_addr = mult_addr + 4; } +LdRtype3: LdRtype2 is LdRtype2 & thc0303=0 { } +LdRtype4: LdRtype3^r4 is LdRtype3 & thc0404=1 & r4 & thc0507=0 { r4 = *mult_addr; mult_addr = mult_addr + 4; } +LdRtype4: LdRtype3^r4, is LdRtype3 & thc0404=1 & r4 { r4 = *mult_addr; mult_addr = mult_addr + 4; } +LdRtype4: LdRtype3 is LdRtype3 & thc0404=0 { } +LdRtype5: LdRtype4^r5 is LdRtype4 & thc0505=1 & r5 & thc0607=0 { r5 = *mult_addr; mult_addr = mult_addr + 4; } +LdRtype5: LdRtype4^r5, is LdRtype4 & thc0505=1 & r5 { r5 = *mult_addr; mult_addr = mult_addr + 4; } +LdRtype5: LdRtype4 is LdRtype4 & thc0505=0 { } +LdRtype6: LdRtype5^r6 is LdRtype5 & thc0606=1 & r6 & thc0707=0 { r6 = *mult_addr; mult_addr = mult_addr + 4; } +LdRtype6: LdRtype5^r6, is LdRtype5 & thc0606=1 & r6 { r6 = *mult_addr; mult_addr = mult_addr + 4; } +LdRtype6: LdRtype5 is LdRtype5 & thc0606=0 { } +ldlist: LdRtype6^r7 is LdRtype6 & thc0707=1 & r7 { r7 = *mult_addr; mult_addr = mult_addr + 4; } +ldlist: LdRtype6 is LdRtype6 & thc0707=0 { } + +#strlist is the list of registers to be stored +StrType0: r0 is thc0000=1 & r0 & thc0107=0 { *mult_addr = r0; mult_addr = mult_addr + 4; } +StrType0: r0, is thc0000=1 & r0 { *mult_addr = r0; mult_addr = mult_addr + 4; } +StrType0: is thc0000=0 { } +StrType1: StrType0^r1 is StrType0 & thc0101=1 & r1 & thc0207=0 { *mult_addr = r1; mult_addr = mult_addr + 4; } +StrType1: StrType0^r1, is StrType0 & thc0101=1 & r1 { *mult_addr = r1; mult_addr = mult_addr + 4; } +StrType1: StrType0 is StrType0 & thc0101=0 { } +StrType2: StrType1^r2 is StrType1 & thc0202=1 & r2 & thc0307=0 { *mult_addr = r2; mult_addr = mult_addr + 4; } +StrType2: StrType1^r2, is StrType1 & thc0202=1 & r2 { *mult_addr = r2; mult_addr = mult_addr + 4; } +StrType2: StrType1 is StrType1 & thc0202=0 { } +StrType3: StrType2^r3 is StrType2 & thc0303=1 & r3 & thc0407=0 { *mult_addr = r3; mult_addr = mult_addr + 4; } +StrType3: StrType2^r3, is StrType2 & thc0303=1 & r3 { *mult_addr = r3; mult_addr = mult_addr + 4; } +StrType3: StrType2 is StrType2 & thc0303=0 { } +StrType4: StrType3^r4 is StrType3 & thc0404=1 & r4 & thc0507=0 { *mult_addr = r4; mult_addr = mult_addr + 4; } +StrType4: StrType3^r4, is StrType3 & thc0404=1 & r4 { *mult_addr = r4; mult_addr = mult_addr + 4; } +StrType4: StrType3 is StrType3 & thc0404=0 { } +StrType5: StrType4^r5 is StrType4 & thc0505=1 & r5 & thc0607=0 { *mult_addr = r5; mult_addr = mult_addr + 4; } +StrType5: StrType4^r5, is StrType4 & thc0505=1 & r5 { *mult_addr = r5; mult_addr = mult_addr + 4; } +StrType5: StrType4 is StrType4 & thc0505=0 { } +StrType6: StrType5^r6 is StrType5 & thc0606=1 & r6 & thc0707=0 { *mult_addr = r6; mult_addr = mult_addr + 4; } +StrType6: StrType5^r6, is StrType5 & thc0606=1 & r6 { *mult_addr = r6; mult_addr = mult_addr + 4; } +StrType6: StrType5 is StrType5 & thc0606=0 { } +StrType7: StrType6^r7 is StrType6 & thc0707=1 & r7 { *mult_addr = r7; mult_addr = mult_addr + 4; } +StrType7: StrType6 is StrType6 & thc0707=0 { } +strlist: StrType7 is StrType7 { } + +# pshlist is the list registers to be pushed to memory +# SCR 10921, fix the order in which the regs appear in the disassembled insn, to be in line with objdump +# Also add commas between regs +# +PshType7: "" is thc0707=0 { } +PshType7: r7 is thc0707=1 & r7 { mult_addr = mult_addr - 4; *mult_addr = r7; } +PshType6: PshType7 is PshType7 & thc0606=0 { } +PshType6: r6 is thc0606=1 & r6 & thc0707=0 { mult_addr = mult_addr - 4; *mult_addr = r6; } +PshType6: r6,PshType7 is PshType7 & thc0606=1 & r6 { mult_addr = mult_addr - 4; *mult_addr = r6; } +PshType5: PshType6 is PshType6 & thc0505=0 { } +PshType5: r5 is thc0505=1 & r5 & thc0607=0 { mult_addr = mult_addr - 4; *mult_addr = r5; } +PshType5: r5,PshType6 is PshType6 & thc0505=1 & r5 { mult_addr = mult_addr - 4; *mult_addr = r5; } +PshType4: PshType5 is PshType5 & thc0404=0 { } +PshType4: r4 is thc0404=1 & r4 & thc0507=0 { mult_addr = mult_addr - 4; *mult_addr = r4; } +PshType4: r4,PshType5 is PshType5 & thc0404=1 & r4 { mult_addr = mult_addr - 4; *mult_addr = r4; } +PshType3: PshType4 is PshType4 & thc0303=0 { } +PshType3: r3 is thc0303=1 & r3 & thc0407=0 { mult_addr = mult_addr - 4; *mult_addr = r3; } +PshType3: r3,PshType4 is PshType4 & thc0303=1 & r3 { mult_addr = mult_addr - 4; *mult_addr = r3; } +PshType2: PshType3 is PshType3 & thc0202=0 { } +PshType2: r2 is thc0202=1 & r2 & thc0307=0 { mult_addr = mult_addr - 4; *mult_addr = r2; } +PshType2: r2,PshType3 is PshType3 & thc0202=1 & r2 { mult_addr = mult_addr - 4; *mult_addr = r2; } +PshType1: PshType2 is PshType2 & thc0101=0 { } +PshType1: r1 is thc0101=1 & r1 & thc0207=0 { mult_addr = mult_addr - 4; *mult_addr = r1; } +PshType1: r1,PshType2 is PshType2 & thc0101=1 & r1 { mult_addr = mult_addr - 4; *mult_addr = r1; } +pshlist: PshType1 is PshType1 & thc0000=0 { } +pshlist: r0 is thc0000=1 & r0 & thc0107=0 { mult_addr = mult_addr - 4; *mult_addr = r0; } +pshlist: r0,PshType1 is PshType1 & thc0000=1 & r0 { mult_addr = mult_addr - 4; *mult_addr = r0; } + +# ldlist_inc is the list of registers to be loaded for pop instructions +thrlist15: r0 is thc0000=1 & r0 & thc0115=0 { r0 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist15: r0, is thc0000=1 & r0 { r0 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist15: is thc0000=0 { } +thrlist14: thrlist15^r1 is thc0101=1 & thrlist15 & r1 & thc0215=0 { r1 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist14: thrlist15^r1, is thc0101=1 & thrlist15 & r1 { r1 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist14: thrlist15 is thc0101=0 & thrlist15 { } +thrlist13: thrlist14^r2 is thc0202=1 & thrlist14 & r2 & thc0315=0 { r2 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist13: thrlist14^r2, is thc0202=1 & thrlist14 & r2 { r2 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist13: thrlist14 is thc0202=0 & thrlist14 { } +thrlist12: thrlist13^r3 is thc0303=1 & thrlist13 & r3 & thc0415=0 { r3 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist12: thrlist13^r3, is thc0303=1 & thrlist13 & r3 { r3 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist12: thrlist13 is thc0303=0 & thrlist13 { } +thrlist11: thrlist12^r4 is thc0404=1 & thrlist12 & r4 & thc0515=0 { r4 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist11: thrlist12^r4, is thc0404=1 & thrlist12 & r4 { r4 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist11: thrlist12 is thc0404=0 & thrlist12 { } +thrlist10: thrlist11^r5 is thc0505=1 & thrlist11 & r5 & thc0615=0 { r5 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist10: thrlist11^r5, is thc0505=1 & thrlist11 & r5 { r5 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist10: thrlist11 is thc0505=0 & thrlist11 { } +thrlist9: thrlist10^r6 is thc0606=1 & thrlist10 & r6 & thc0715=0 { r6 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist9: thrlist10^r6, is thc0606=1 & thrlist10 & r6 { r6 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist9: thrlist10 is thc0606=0 & thrlist10 { } +thrlist8: thrlist9^r7 is thc0707=1 & thrlist9 & r7 & thc0815=0 { r7 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist8: thrlist9^r7, is thc0707=1 & thrlist9 & r7 { r7 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist8: thrlist9 is thc0707=0 & thrlist9 { } +thrlist7: thrlist8^r8 is thc0808=1 & thrlist8 & r8 & thc0915=0 { r8 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist7: thrlist8^r8, is thc0808=1 & thrlist8 & r8 { r8 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist7: thrlist8 is thc0808=0 & thrlist8 { } +thrlist6: thrlist7^r9 is thc0909=1 & thrlist7 & r9 & thc1015=0 { r9 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist6: thrlist7^r9, is thc0909=1 & thrlist7 & r9 { r9 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist6: thrlist7 is thc0909=0 & thrlist7 { } +thrlist5: thrlist6^r10 is thc1010=1 & thrlist6 & r10 & thc1115=0 { r10 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist5: thrlist6^r10, is thc1010=1 & thrlist6 & r10 { r10 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist5: thrlist6 is thc1010=0 & thrlist6 { } +thrlist4: thrlist5^r11 is thc1111=1 & thrlist5 & r11 & thc1215=0 { r11 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist4: thrlist5^r11, is thc1111=1 & thrlist5 & r11 { r11 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist4: thrlist5 is thc1111=0 & thrlist5 { } +thrlist3: thrlist4^r12 is thc1212=1 & thrlist4 & r12 & thc1315=0 { r12 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist3: thrlist4^r12, is thc1212=1 & thrlist4 & r12 { r12 = * mult_addr; mult_addr = mult_addr + 4; } +thrlist3: thrlist4 is thc1212=0 & thrlist4 { } +thrlist2: thrlist3^sp is thc1313=1 & thrlist3 & sp & thc1415=0 { sp = * mult_addr; mult_addr = mult_addr + 4; } +thrlist2: thrlist3^sp, is thc1313=1 & thrlist3 & sp { sp = * mult_addr; mult_addr = mult_addr + 4; } +thrlist2: thrlist3 is thc1313=0 & thrlist3 { } +thrlist1: thrlist2^lr is thc1414=1 & thrlist2 & lr & thc1515=0 { lr = * mult_addr; mult_addr = mult_addr + 4; } +thrlist1: thrlist2^lr, is thc1414=1 & thrlist2 & lr { lr = * mult_addr; mult_addr = mult_addr + 4; } +thrlist1: thrlist2 is thc1414=0 & thrlist2 { } +thldrlist_inc: {thrlist1^pc} is thc1515=1 & thrlist1 & pc { pc = * mult_addr; mult_addr = mult_addr + 4; } +thldrlist_inc: {thrlist1} is thc1515=0 & thrlist1 { } + +@if defined(VERSION_6T2) || defined(VERSION_7) + +# thstrlist_inc is the list of registers to be stored using IA or IB in Addressing Mode 4 +thsinc15: r0 is thc0000=1 & r0 & thc0115=0 { * mult_addr = r0; mult_addr = mult_addr + 4; } +thsinc15: r0, is thc0000=1 & r0 { * mult_addr = r0; mult_addr = mult_addr + 4; } +thsinc15: is thc0000=0 { } +thsinc14: thsinc15^r1 is thc0101=1 & thsinc15 & r1 & thc0215=0 { * mult_addr = r1; mult_addr = mult_addr + 4; } +thsinc14: thsinc15^r1, is thc0101=1 & thsinc15 & r1 { * mult_addr = r1; mult_addr = mult_addr + 4; } +thsinc14: thsinc15 is thc0101=0 & thsinc15 { } +thsinc13: thsinc14^r2 is thc0202=1 & thsinc14 & r2 & thc0315=0 { * mult_addr = r2; mult_addr = mult_addr + 4; } +thsinc13: thsinc14^r2, is thc0202=1 & thsinc14 & r2 { * mult_addr = r2; mult_addr = mult_addr + 4; } +thsinc13: thsinc14 is thc0202=0 & thsinc14 { } +thsinc12: thsinc13^r3 is thc0303=1 & thsinc13 & r3 & thc0415=0 { * mult_addr = r3; mult_addr = mult_addr + 4; } +thsinc12: thsinc13^r3, is thc0303=1 & thsinc13 & r3 { * mult_addr = r3; mult_addr = mult_addr + 4; } +thsinc12: thsinc13 is thc0303=0 & thsinc13 { } +thsinc11: thsinc12^r4 is thc0404=1 & thsinc12 & r4 & thc0515=0 { * mult_addr = r4; mult_addr = mult_addr + 4; } +thsinc11: thsinc12^r4, is thc0404=1 & thsinc12 & r4 { * mult_addr = r4; mult_addr = mult_addr + 4; } +thsinc11: thsinc12 is thc0404=0 & thsinc12 { } +thsinc10: thsinc11^r5 is thc0505=1 & thsinc11 & r5 & thc0615=0 { * mult_addr = r5; mult_addr = mult_addr + 4; } +thsinc10: thsinc11^r5, is thc0505=1 & thsinc11 & r5 { * mult_addr = r5; mult_addr = mult_addr + 4; } +thsinc10: thsinc11 is thc0505=0 & thsinc11 { } +thsinc9: thsinc10^r6 is thc0606=1 & thsinc10 & r6 & thc0715=0 { * mult_addr = r6; mult_addr = mult_addr + 4; } +thsinc9: thsinc10^r6, is thc0606=1 & thsinc10 & r6 { * mult_addr = r6; mult_addr = mult_addr + 4; } +thsinc9: thsinc10 is thc0606=0 & thsinc10 { } +thsinc8: thsinc9^r7 is thc0707=1 & thsinc9 & r7 & thc0815=0 { * mult_addr = r7; mult_addr = mult_addr + 4; } +thsinc8: thsinc9^r7, is thc0707=1 & thsinc9 & r7 { * mult_addr = r7; mult_addr = mult_addr + 4; } +thsinc8: thsinc9 is thc0707=0 & thsinc9 { } +thsinc7: thsinc8^r8 is thc0808=1 & thsinc8 & r8 & thc0915=0 { * mult_addr = r8; mult_addr = mult_addr + 4; } +thsinc7: thsinc8^r8, is thc0808=1 & thsinc8 & r8 { * mult_addr = r8; mult_addr = mult_addr + 4; } +thsinc7: thsinc8 is thc0808=0 & thsinc8 { } +thsinc6: thsinc7^r9 is thc0909=1 & thsinc7 & r9 & thc1015=0 { * mult_addr = r9; mult_addr = mult_addr + 4; } +thsinc6: thsinc7^r9, is thc0909=1 & thsinc7 & r9 { * mult_addr = r9; mult_addr = mult_addr + 4; } +thsinc6: thsinc7 is thc0909=0 & thsinc7 { } +thsinc5: thsinc6^r10 is thc1010=1 & thsinc6 & r10 & thc1115=0 { * mult_addr = r10; mult_addr = mult_addr + 4; } +thsinc5: thsinc6^r10, is thc1010=1 & thsinc6 & r10 { * mult_addr = r10; mult_addr = mult_addr + 4; } +thsinc5: thsinc6 is thc1010=0 & thsinc6 { } +thsinc4: thsinc5^r11 is thc1111=1 & thsinc5 & r11 & thc1215=0 { * mult_addr = r11; mult_addr = mult_addr + 4; } +thsinc4: thsinc5^r11, is thc1111=1 & thsinc5 & r11 { * mult_addr = r11; mult_addr = mult_addr + 4; } +thsinc4: thsinc5 is thc1111=0 & thsinc5 { } +thsinc3: thsinc4^r12 is thc1212=1 & thsinc4 & r12 & thc1315=0 { * mult_addr = r12; mult_addr = mult_addr + 4; } +thsinc3: thsinc4^r12, is thc1212=1 & thsinc4 & r12 { * mult_addr = r12; mult_addr = mult_addr + 4; } +thsinc3: thsinc4 is thc1212=0 & thsinc4 { } +thsinc2: thsinc3^sp is thc1313=1 & thsinc3 & sp & thc1415=0 { * mult_addr = sp; mult_addr = mult_addr + 4; } +thsinc2: thsinc3^sp, is thc1313=1 & thsinc3 & sp { * mult_addr = sp; mult_addr = mult_addr + 4; } +thsinc2: thsinc3 is thc1313=0 & thsinc3 { } +thsinc1: thsinc2^lr is thc1414=1 & thsinc2 & lr & thc1515=0 { * mult_addr = lr; mult_addr = mult_addr + 4; } +thsinc1: thsinc2^lr, is thc1414=1 & thsinc2 & lr { * mult_addr = lr; mult_addr = mult_addr + 4; } +thsinc1: thsinc2 is thc1414=0 & thsinc2 { } +thstrlist_inc: {thsinc1^pc} is thc1515=1 & thsinc1 & pc { *:4 mult_addr = inst_start+4; mult_addr = mult_addr + 4; } +thstrlist_inc: {thsinc1} is thc1515=0 & thsinc1 { } + +# thldrlist_dec is the list of registers to be loaded using DA or DB in Addressing Mode 4 +thrldec15: pc is thc1515=1 & pc { pc = * mult_addr; mult_addr = mult_addr - 4; } +thrldec15: is thc1515=0 { } +thrldec14: lr^thrldec15 is thc1414=1 & thrldec15 & lr & thc1515=0 { lr = * mult_addr; mult_addr = mult_addr - 4; } +thrldec14: lr,thrldec15 is thc1414=1 & thrldec15 & lr { lr = * mult_addr; mult_addr = mult_addr - 4; } +thrldec14: thrldec15 is thc1414=0 & thrldec15 { } +thrldec13: sp^thrldec14 is thc1313=1 & thrldec14 & sp & thc1415=0 { sp = * mult_addr; mult_addr = mult_addr - 4; } +thrldec13: sp,thrldec14 is thc1313=1 & thrldec14 & sp { sp = * mult_addr; mult_addr = mult_addr - 4; } +thrldec13: thrldec14 is thc1313=0 & thrldec14 { } +thrldec12: r12^thrldec13 is thc1212=1 & thrldec13 & r12 & thc1315=0 { r12 = * mult_addr; mult_addr = mult_addr - 4; } +thrldec12: r12,thrldec13 is thc1212=1 & thrldec13 & r12 { r12 = * mult_addr; mult_addr = mult_addr - 4; } +thrldec12: thrldec13 is thc1212=0 & thrldec13 { } +thrldec11: r11^thrldec12 is thc1111=1 & thrldec12 & r11 & thc1215=0 { r11 = * mult_addr; mult_addr = mult_addr - 4; } +thrldec11: r11,thrldec12 is thc1111=1 & thrldec12 & r11 { r11 = * mult_addr; mult_addr = mult_addr - 4; } +thrldec11: thrldec12 is thc1111=0 & thrldec12 { } +thrldec10: r10^thrldec11 is thc1010=1 & thrldec11 & r10 & thc1115=0 { r10 = * mult_addr; mult_addr = mult_addr - 4; } +thrldec10: r10,thrldec11 is thc1010=1 & thrldec11 & r10 { r10 = * mult_addr; mult_addr = mult_addr - 4; } +thrldec10: thrldec11 is thc1010=0 & thrldec11 { } +thrldec9: r9^thrldec10 is thc0909=1 & thrldec10 & r9 & thc1015=0 { r9 = * mult_addr; mult_addr = mult_addr - 4; } +thrldec9: r9,thrldec10 is thc0909=1 & thrldec10 & r9 { r9 = * mult_addr; mult_addr = mult_addr - 4; } +thrldec9: thrldec10 is thc0909=0 & thrldec10 { } +thrldec8: r8^thrldec9 is thc0808=1 & thrldec9 & r8 & thc0915=0 { r8 = * mult_addr; mult_addr = mult_addr - 4; } +thrldec8: r8,thrldec9 is thc0808=1 & thrldec9 & r8 { r8 = * mult_addr; mult_addr = mult_addr - 4; } +thrldec8: thrldec9 is thc0808=0 & thrldec9 { } +thrldec7: r7^thrldec8 is thc0707=1 & thrldec8 & r7 & thc0815=0 { r7 = * mult_addr; mult_addr = mult_addr - 4; } +thrldec7: r7,thrldec8 is thc0707=1 & thrldec8 & r7 { r7 = * mult_addr; mult_addr = mult_addr - 4; } +thrldec7: thrldec8 is thc0707=0 & thrldec8 { } +thrldec6: r6^thrldec7 is thc0606=1 & thrldec7 & r6 & thc0715=0 { r6 = * mult_addr; mult_addr = mult_addr - 4; } +thrldec6: r6,thrldec7 is thc0606=1 & thrldec7 & r6 { r6 = * mult_addr; mult_addr = mult_addr - 4; } +thrldec6: thrldec7 is thc0606=0 & thrldec7 { } +thrldec5: r5^thrldec6 is thc0505=1 & thrldec6 & r5 & thc0615=0 { r5 = * mult_addr; mult_addr = mult_addr - 4; } +thrldec5: r5,thrldec6 is thc0505=1 & thrldec6 & r5 { r5 = * mult_addr; mult_addr = mult_addr - 4; } +thrldec5: thrldec6 is thc0505=0 & thrldec6 { } +thrldec4: r4^thrldec5 is thc0404=1 & thrldec5 & r4 & thc0515=0 { r4 = * mult_addr; mult_addr = mult_addr - 4; } +thrldec4: r4,thrldec5 is thc0404=1 & thrldec5 & r4 { r4 = * mult_addr; mult_addr = mult_addr - 4; } +thrldec4: thrldec5 is thc0404=0 & thrldec5 { } +thrldec3: r3^thrldec4 is thc0303=1 & thrldec4 & r3 & thc0415=0 { r3 = * mult_addr; mult_addr = mult_addr - 4; } +thrldec3: r3,thrldec4 is thc0303=1 & thrldec4 & r3 { r3 = * mult_addr; mult_addr = mult_addr - 4; } +thrldec3: thrldec4 is thc0303=0 & thrldec4 { } +thrldec2: r2^thrldec3 is thc0202=1 & thrldec3 & r2 & thc0315=0 { r2 = * mult_addr; mult_addr = mult_addr - 4; } +thrldec2: r2,thrldec3 is thc0202=1 & thrldec3 & r2 { r2 = * mult_addr; mult_addr = mult_addr - 4; } +thrldec2: thrldec3 is thc0202=0 & thrldec3 { } +thrldec1: r1^thrldec2 is thc0101=1 & thrldec2 & r1 & thc0215=0 { r1 = * mult_addr; mult_addr = mult_addr - 4; } +thrldec1: r1,thrldec2 is thc0101=1 & thrldec2 & r1 { r1 = * mult_addr; mult_addr = mult_addr - 4; } +thrldec1: thrldec2 is thc0101=0 & thrldec2 { } +thldrlist_dec: {r0^thrldec1} is thc0000=1 & thrldec1 & r0 & thc0115=0 { r0 = * mult_addr; mult_addr = mult_addr - 4; } +thldrlist_dec: {r0,thrldec1} is thc0000=1 & thrldec1 & r0 { r0 = * mult_addr; mult_addr = mult_addr - 4; } +thldrlist_dec: {thrldec1} is thc0000=0 & thrldec1 { } + +@endif # defined(VERSION_6T2) || defined(VERSION_7) + +# thstrlist_dec is the list of registers to be pushed +thsdec15: pc is thc1515=1 & pc { *:4 mult_addr = inst_start+4; mult_addr = mult_addr - 4; } +thsdec15: is thc1515=0 { } +thsdec14: lr is thc1414=1 & thsdec15 & lr & thc1515=0 { * mult_addr=lr; mult_addr = mult_addr - 4; } +thsdec14: lr,thsdec15 is thc1414=1 & thsdec15 & lr { * mult_addr=lr; mult_addr = mult_addr - 4; } +thsdec14: thsdec15 is thc1414=0 & thsdec15 { } +thsdec13: sp is thc1313=1 & sp & thc1415=0 { * mult_addr=sp; mult_addr = mult_addr - 4; } +thsdec13: sp,thsdec14 is thc1313=1 & thsdec14 & sp { * mult_addr=sp; mult_addr = mult_addr - 4; } +thsdec13: thsdec14 is thc1313=0 & thsdec14 { } +thsdec12: r12 is thc1212=1 & r12 & thc1315=0 { * mult_addr=r12; mult_addr = mult_addr - 4; } +thsdec12: r12,thsdec13 is thc1212=1 & thsdec13 & r12 { * mult_addr=r12; mult_addr = mult_addr - 4; } +thsdec12: thsdec13 is thc1212=0 & thsdec13 { } +thsdec11: r11 is thc1111=1 & r11 & thc1215=0 { * mult_addr=r11; mult_addr = mult_addr - 4; } +thsdec11: r11,thsdec12 is thc1111=1 & thsdec12 & r11 { * mult_addr=r11; mult_addr = mult_addr - 4; } +thsdec11: thsdec12 is thc1111=0 & thsdec12 { } +thsdec10: r10 is thc1010=1 & r10 & thc1115=0 { * mult_addr=r10; mult_addr = mult_addr - 4; } +thsdec10: r10,thsdec11 is thc1010=1 & thsdec11 & r10 { * mult_addr=r10; mult_addr = mult_addr - 4; } +thsdec10: thsdec11 is thc1010=0 & thsdec11 { } +thsdec9: r9 is thc0909=1 & r9 & thc1015=0 { * mult_addr=r9; mult_addr = mult_addr - 4; } +thsdec9: r9,thsdec10 is thc0909=1 & thsdec10 & r9 { * mult_addr=r9; mult_addr = mult_addr - 4; } +thsdec9: thsdec10 is thc0909=0 & thsdec10 { } +thsdec8: r8 is thc0808=1 & r8 & thc0915=0 { * mult_addr=r8; mult_addr = mult_addr - 4; } +thsdec8: r8,thsdec9 is thc0808=1 & thsdec9 & r8 { * mult_addr=r8; mult_addr = mult_addr - 4; } +thsdec8: thsdec9 is thc0808=0 & thsdec9 { } +thsdec7: r7 is thc0707=1 & r7 & thc0815=0 { * mult_addr=r7; mult_addr = mult_addr - 4; } +thsdec7: r7,thsdec8 is thc0707=1 & thsdec8 & r7 { * mult_addr=r7; mult_addr = mult_addr - 4; } +thsdec7: thsdec8 is thc0707=0 & thsdec8 { } +thsdec6: r6 is thc0606=1 & r6 & thc0715=0 { * mult_addr=r6; mult_addr = mult_addr - 4; } +thsdec6: r6,thsdec7 is thc0606=1 & thsdec7 & r6 { * mult_addr=r6; mult_addr = mult_addr - 4; } +thsdec6: thsdec7 is thc0606=0 & thsdec7 { } +thsdec5: r5 is thc0505=1 & r5 & thc0615=0 { * mult_addr=r5; mult_addr = mult_addr - 4; } +thsdec5: r5,thsdec6 is thc0505=1 & thsdec6 & r5 { * mult_addr=r5; mult_addr = mult_addr - 4; } +thsdec5: thsdec6 is thc0505=0 & thsdec6 { } +thsdec4: r4 is thc0404=1 & r4 & thc0515=0 { * mult_addr=r4; mult_addr = mult_addr - 4; } +thsdec4: r4,thsdec5 is thc0404=1 & thsdec5 & r4 { * mult_addr=r4; mult_addr = mult_addr - 4; } +thsdec4: thsdec5 is thc0404=0 & thsdec5 { } +thsdec3: r3 is thc0303=1 & r3 & thc0415=0 { * mult_addr=r3; mult_addr = mult_addr - 4; } +thsdec3: r3,thsdec4 is thc0303=1 & thsdec4 & r3 { * mult_addr=r3; mult_addr = mult_addr - 4; } +thsdec3: thsdec4 is thc0303=0 & thsdec4 { } +thsdec2: r2 is thc0202=1 & r2 & thc0315=0 { * mult_addr=r2; mult_addr = mult_addr - 4; } +thsdec2: r2,thsdec3 is thc0202=1 & thsdec3 & r2 { * mult_addr=r2; mult_addr = mult_addr - 4; } +thsdec2: thsdec3 is thc0202=0 & thsdec3 { } +thsdec1: r1 is thc0101=1 & r1 & thc0215=0 { * mult_addr=r1; mult_addr = mult_addr - 4; } +thsdec1: r1,thsdec2 is thc0101=1 & thsdec2 & r1 { * mult_addr=r1; mult_addr = mult_addr - 4; } +thsdec1: thsdec2 is thc0101=0 & thsdec2 { } +thstrlist_dec: {r0} is thc0000=1 & r0 & thc0115=0 { * mult_addr=r0; mult_addr = mult_addr - 4; } +thstrlist_dec: {r0,thsdec1} is thc0000=1 & thsdec1 & r0 { * mult_addr=r0; mult_addr = mult_addr - 4; } +thstrlist_dec: {thsdec1^} is thc0000=0 & thsdec1 { } + +ldbrace: {ldlist} is ldlist { } +stbrace: {strlist} is strlist { } +psbrace: {pshlist} is pshlist { } + +# Some extra subconstructors for the push and pop instructions +pclbrace:{ldlist,pc} is ldlist & pc { build ldlist; pc = *mult_addr; mult_addr = mult_addr + 4; } +pclbrace:{pc} is thc0007=0 & pc { pc = *mult_addr; mult_addr = mult_addr + 4; } +pcpbrace:{pshlist,lr} is pshlist & lr { mult_addr = mult_addr - 4; *mult_addr = lr; build pshlist; } +pcpbrace:{lr} is thc0007=0 & lr { mult_addr = mult_addr - 4; *mult_addr = lr; } + +@if defined(VERSION_6T2) || defined(VERSION_7) +RnIndirect12: [Rn0003,"#"^offset12] is Rn0003; offset12 { local tmp = Rn0003 + offset12; export tmp; } + +RnIndirectPUW: [Rn0003],"#"^-immed8 is Rn0003; addr_puw=1 & immed8 { local tmp = Rn0003; Rn0003=Rn0003-immed8; export tmp; } +RnIndirectPUW: [Rn0003],"#"^immed8 is Rn0003; addr_puw=3 & immed8 { local tmp = Rn0003; Rn0003=Rn0003+immed8; export tmp; } +RnIndirectPUW: [Rn0003,"#"^-immed8] is Rn0003; addr_puw=4 & immed8 { local tmp = Rn0003 - immed8; export tmp; } +RnIndirectPUW: [Rn0003,"#"^-immed8]! is Rn0003; addr_puw=5 & immed8 { local tmp = Rn0003 - immed8; Rn0003=tmp; export tmp; } +RnIndirectPUW: [Rn0003,"#"^immed8]! is Rn0003; addr_puw=7 & immed8 { local tmp = Rn0003 + immed8; Rn0003=tmp; export tmp; } + +@define RN_INDIRECT_PUW "(op0; (addr_puw=4 | thc0808=1)) & RnIndirectPUW" # constraint for RnIndirectPUW + +RnIndirectPUW1: [Rn0003],"#"^-immval is Rn0003 & addr_puw1=0x3; immed8 [ immval = immed8 * 4; ] { local tmp = Rn0003; Rn0003=Rn0003-immval; export tmp; } +RnIndirectPUW1: [Rn0003],"#"^immval is Rn0003 & addr_puw1=0x7; immed8 [ immval = immed8 * 4; ] { local tmp = Rn0003; Rn0003=Rn0003+immval; export tmp; } +RnIndirectPUW1: [Rn0003,"#"^-immval] is Rn0003 & addr_puw1=0xa; immed8 [ immval = immed8 * 4; ] { local tmp = Rn0003 - immval; export tmp; } +RnIndirectPUW1: [Rn0003,"#"^-immval]! is Rn0003 & addr_puw1=0xb; immed8 [ immval = immed8 * 4; ] { local tmp = Rn0003 - immval; Rn0003=tmp; export tmp; } +RnIndirectPUW1: [Rn0003,"#"^immval] is Rn0003 & addr_puw1=0xe; immed8 [ immval = immed8 * 4; ] { local tmp = Rn0003 + immval; export tmp; } +RnIndirectPUW1: [Rn0003,"#"^immval]! is Rn0003 & addr_puw1=0xf; immed8 [ immval = immed8 * 4; ] { local tmp = Rn0003 + immval; Rn0003=tmp; export tmp; } + +@endif # VERSION_6T2 || VERSION_7 + +@define RN_INDIRECT_PUW1 "((thc0808=1 | thc0505=1); op0) & RnIndirectPUW1" # constraint for RnIndirectPUW1 + +RnIndirect4: [Rn0305,"#"^immval] is Rn0305 & immed5 [ immval = immed5 * 4; ] { local tmp = Rn0305 + immval; export tmp; } +RnIndirect2: [Rn0305,"#"^immval] is Rn0305 & immed5 [ immval = immed5 * 2; ] { local tmp = Rn0305 + immval; export tmp; } +RnIndirect1: [Rn0305,"#"^immed5] is Rn0305 & immed5 { local tmp = Rn0305 + immed5; export tmp; } + +RnRmIndirect: [Rn0305,Rm0608] is Rn0305 & Rm0608 { local tmp = Rn0305 + Rm0608; export tmp; } + +Pcrel8Indirect: [reloc] is immed8 + [ reloc = ((inst_start+4) $and 0xfffffffc) + 4*immed8; ] +{ + export *:4 reloc; +} + +Sprel8Indirect: [sp,"#"^immval] is sp & immed8 [ immval = immed8 * 4; ] { local tmp = sp + immval; export tmp; } + +@if defined(VERSION_6T2) || defined(VERSION_7) + +taddrmode5: [Rn0003,"#"^off8] is thP8=1 & thU7=1 & thW5=0 & Rn0003; immed8 [ off8=immed8*4; ] { local tmp = Rn0003 + off8; export tmp; } +taddrmode5: [Rn0003,"#"^noff8] is thP8=1 & thU7=0 & thW5=0 & Rn0003; immed8 [ noff8=-(immed8*4); ] { local tmp = Rn0003 + noff8; export tmp; } +taddrmode5: [Rn0003,"#"^off8]! is thP8=1 & thU7=1 & thW5=1 & Rn0003; immed8 [ off8=immed8*4; ] { Rn0003 = Rn0003 + off8; export Rn0003; } +taddrmode5: [Rn0003,"#"^noff8]! is thP8=1 & thU7=0 & thW5=1 & Rn0003; immed8 [ noff8=-(immed8*4); ] { Rn0003 = Rn0003 + noff8; export Rn0003; } +taddrmode5: [Rn0003],"#"^off8 is thP8=0 & thU7=1 & thW5=1 & Rn0003; immed8 [ off8=immed8*4; ] { local tmp = Rn0003; Rn0003 = Rn0003+off8; export tmp; } +taddrmode5: [Rn0003],"#"^noff8 is thP8=0 & thU7=0 & thW5=1 & Rn0003; immed8 [ noff8=-(immed8*4); ] { local tmp = Rn0003; Rn0003 = Rn0003 + noff8; export tmp; } +taddrmode5: [Rn0003],{immed8} is thP8=0 & thU7=1 & thW5=0 & Rn0003; immed8 { export Rn0003; } + +@endif # VERSION_6T2 || VERSION_7 + +# +# Modes for SRS instructions +# +thSRSMode: "usr" is thsrsMode=8 & thc0004 { export *[const]:1 thc0004; } +thSRSMode: "fiq" is thsrsMode=9 & thc0004 { export *[const]:1 thc0004; } +thSRSMode: "irq" is thsrsMode=10 & thc0004 { export *[const]:1 thc0004; } +thSRSMode: "svc" is thsrsMode=11 & thc0004 { export *[const]:1 thc0004; } +thSRSMode: "mon" is thsrsMode=14 & thc0004 { export *[const]:1 thc0004; } +thSRSMode: "abt" is thsrsMode=15 & thc0004 { export *[const]:1 thc0004; } +thSRSMode: "und" is thsrsMode=19 & thc0004 { export *[const]:1 thc0004; } +thSRSMode: "sys" is thsrsMode=23 & thc0004 { export *[const]:1 thc0004; } +thSRSMode: "#"^thsrsMode is thsrsMode { export *[const]:1 thsrsMode; } + +# +# Detect if the PC is loaded and do a GOTO +# +# TODO: this is how all detections of writes into the PC should be done. +# Instead of enumerating and splitting the case into PC loaded and non loaded, IE (add PC,#0x...) +# Should only have one base constructor and have a sub constructor and build to test if the PC was loaded and do the right thing. +# + +@if defined(VERSION_6T2) || defined(VERSION_7) + +RtGotoCheck: is Rt1215=15 { + LoadWritePC(pc); + goto [pc]; +} +RtGotoCheck: is Rt1215 {} + +@endif # VERSION_6T2 || VERSION_7 + +############################################################ + +# Base constructors + +# We have the following operand types: +# Type Corresponding syntax in ARM/THUMB manual +# +# Rd0002 with Rd occupying bits 0-2 +# Rd0810 with Rd occupying bits 8-10 +# Rm0305 with Rm occupying bits 3-5 +# Rm0608 with Rm occupying bits 6-8 +# Rn0002 with Rn occupying bits 0-2 +# Rn0305 with Rn occupying bits 3-5 +# Rn0810 with Rn occupying bits 8-10 +# Hrd0002 with H1 bit in diagram +# Hrn0002 with H1 bit in diagram +# Hrm0305 with H2 bit in diagram +# Rs0305 with Rs occupying bits 3-5 +# Immed3 # +# Immed5 # +# Immed8 # +# Pcrel8 PC,#*4 +# Sprel8 SP,#*4 +# Immed7_4 #*4 +# thcc +# Addr8 (for B) +# Addr11 (for B no condition) +# ThAddr22 (for double BL, BLX) +# immed8 (no "#" as in BKPT and SWI) +# Rn_exclaim ! +# ldbrace (load instructions) +# strbrace (store instructions) +# RnIndirect4 [,#*4] +# RnIndirect2 [,#*2] +# RnIndirect1 [,#] +# RnRmIndirect [,] +# Pcrel8Indirect [PC,#*4] +# Sprel8Indirect [SP,#*4] + +# + + +# Ensure that the condition check phase has been completed +with : ARMcondCk=1 { + +:adc^CheckInIT_CZNO^ItCond Rd0002,Rm0305 is TMode=1 & ItCond & op6=0x105 & Rm0305 & Rd0002 & CheckInIT_CZNO +{ + build ItCond; + th_add_with_carry_flags(Rd0002,Rm0305); + Rd0002 = Rd0002 + Rm0305 + zext(CY); + resflags(Rd0002); + build CheckInIT_CZNO; +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:adc^thSBIT_CZNO^ItCond Rd0811,Rn0003,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=0xa & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811) & ThumbExpandImm12 +{ + build ItCond; + build ThumbExpandImm12; + th_add_with_carry_flags(Rn0003,ThumbExpandImm12); + Rd0811 = Rn0003 + ThumbExpandImm12 + zext(CY); + resflags(Rd0811); + build thSBIT_CZNO; +} + +:adc^thSBIT_CZNO^ItCond^".w" Rd0811,Rn0003,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=0xa & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811 & thshift2 +{ + build ItCond; + build thshift2; + th_add_with_carry_flags(Rn0003,thshift2); + local tmp = thshift2+zext(CY); + Rd0811 = Rn0003+tmp; + resflags(Rd0811); + build thSBIT_CZNO; +} +@endif # VERSION_6T2 || VERSION_7 + +:add^CheckInIT_CZNO^ItCond Rd0002,Rn0305,Immed3 is TMode=1 & ItCond & op9=0x0e & Immed3 & Rn0305 & Rd0002 & CheckInIT_CZNO +{ + build ItCond; + th_addflags(Rn0305,Immed3); + Rd0002 = Rn0305 + Immed3; + resflags(Rd0002); + build CheckInIT_CZNO; +} + +:add^CheckInIT_CZNO^ItCond Rd0810,Immed8 is TMode=1 & ItCond & op11=0x06 & Rd0810 & Immed8 & CheckInIT_CZNO +{ + build ItCond; + th_addflags(Rd0810,Immed8); + Rd0810 = Rd0810 + Immed8; + resflags(Rd0810); + build CheckInIT_CZNO; +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:add^thSBIT_CZNO^ItCond^".w" Rd0811,Rn0003,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=8 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811) & ThumbExpandImm12 +{ + build ItCond; + build ThumbExpandImm12; + th_addflags(Rn0003,ThumbExpandImm12); + Rd0811 = Rn0003+ThumbExpandImm12; + resflags(Rd0811); + build thSBIT_CZNO; +} + +:addw^ItCond Rd0811,Rn0003,Immed12 is TMode=1 & ItCond & (op11=0x1e & thc0909=1 & sop0508=0 & thc0404=0 & Rn0003; thc1515=0 & Rd0811) & Immed12 +{ + build ItCond; + th_addflags(Rn0003,Immed12); + Rd0811 = Rn0003+Immed12; + resflags(Rd0811); +} + +:add^thSBIT_CZNO^ItCond^".w" Rd0811,Rn0003,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=8 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811 & thshift2 +{ + build ItCond; + build thshift2; + local tmp = thshift2; + th_addflags(Rn0003,tmp); + Rd0811 = Rn0003+tmp; + resflags(Rd0811); + build thSBIT_CZNO; +} + +:add^thSBIT_CZNO^ItCond^".w" Rd0811,sp,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=8 & thSBIT_CZNO & sp & sop0003=0xd; thc1515=0 & Rd0811) & ThumbExpandImm12 +{ + build ItCond; + build ThumbExpandImm12; + th_addflags(sp,ThumbExpandImm12); + Rd0811 = sp+ThumbExpandImm12; + resflags(Rd0811); + build thSBIT_CZNO; +} + +:addw^ItCond Rd0811,sp,Immed12 is TMode=1 & ItCond & (op11=0x1e & thc0909=1 & sop0508=0 & thc0404=0 & sop0003=0xd & sp; thc1515=0 & Rd0811) & Immed12 +{ + build ItCond; + th_addflags(sp,Immed12); + Rd0811 = sp+Immed12; + resflags(Rd0811); +} + +:add^thSBIT_CZNO^ItCond^".w" Rd0811,sp,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=8 & thSBIT_CZNO & sop0003=0xd & sp; thc1515=0 & Rd0811 & thshift2 +{ + build ItCond; + build thshift2; + local tmp = thshift2; + th_addflags(sp,tmp); + Rd0811 = sp+tmp; + resflags(Rd0811); + build thSBIT_CZNO; +} + +@endif # VERSION_6T2 || VERSION_7 + +:add^CheckInIT_CZNO^ItCond Rd0002,Rn0305,Rm0608 is TMode=1 & ItCond & op9=0x0c & Rm0608 & Rn0305 & Rd0002 & CheckInIT_CZNO +{ + build ItCond; + th_addflags(Rn0305,Rm0608); + Rd0002 = Rn0305 + Rm0608; + resflags(Rd0002); + build CheckInIT_CZNO; +} + +:add^ItCond Hrd0002,Hrm0305 is TMode=1 & ItCond & op8=0x44 & Hrd0002 & Hrm0305 +{ + build ItCond; + Hrd0002 = Hrd0002 + Hrm0305; +} + +:add^ItCond Hrd0002,Hrm0305 is TMode=1 & ItCond & op8=0x44 & Hrd0002 & Hrm0305 & hrd0002=7 & h1=1 +{ + build ItCond; + dest:4 = Hrd0002 + Hrm0305; + BranchWritePC(dest); + goto [pc]; +} + +:add^ItCond Rd0810,Sprel8 is TMode=1 & ItCond & op11=0x15 & Rd0810 & Sprel8 +{ + build ItCond; + Rd0810 = Sprel8; +} + +:add^ItCond sp,Immed7_4 is TMode=1 & ItCond & op7=0x160 & sp & Immed7_4 +{ + build ItCond; + sp = sp + Immed7_4; +} + +:adr^ItCond Rd0810,Pcrel8 is TMode=1 & ItCond & op11=0x14 & Rd0810 & Pcrel8 +{ + build ItCond; + Rd0810 = &Pcrel8; +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:adr^ItCond^".w" Rd0811,NegPcrelImmed12Addr is TMode=1 & ItCond & (op11=0x1e & thc0909=1 & sop0508=5 & thc0404=0 & sop0003=0xf; thc1515=0 & Rd0811) & NegPcrelImmed12Addr +{ + build ItCond; + Rd0811 = &NegPcrelImmed12Addr; +} + +:adr^ItCond^".w" Rd0811,PcrelImmed12Addr is TMode=1 & ItCond & (op11=0x1e & thc0909=1 & sop0508=0 & thc0404=0 & sop0003=0xf; thc1515=0 & Rd0811) & PcrelImmed12Addr +{ + build ItCond; + Rd0811 = &PcrelImmed12Addr; +} + +:adr^ItCond^".w" Rd0811,NegPcrelImmed12Addr is TMode=1 & ItCond & (op11=0x1e & thc0909=1 & sop0508=5 & thc0404=0 & sop0003=0xf; thc1515=0 & Rd0811 & thc0811=15) & NegPcrelImmed12Addr +{ + build ItCond; + pc = &NegPcrelImmed12Addr; + goto NegPcrelImmed12Addr; +} + +:adr^ItCond^".w" Rd0811,PcrelImmed12Addr is TMode=1 & ItCond & (op11=0x1e & thc0909=1 & sop0508=0 & thc0404=0 & sop0003=0xf; thc1515=0 & Rd0811 & thc0811=15) & PcrelImmed12Addr +{ + build ItCond; + pc = &PcrelImmed12Addr; + goto PcrelImmed12Addr; +} + +@endif # VERSION_6T2 || VERSION_7 + +:and^CheckInIT_ZN^ItCond Rd0002,Rm0305 is TMode=1 & ItCond & op6=0x100 & Rd0002 & Rm0305 & CheckInIT_ZN +{ + build ItCond; + Rd0002 = Rd0002 & Rm0305; + resflags(Rd0002); + build CheckInIT_ZN; +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:and^thSBIT_ZN^ItCond Rd0811,Rn0003,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=0 & thSBIT_ZN & Rn0003; thc1515=0 & Rd0811) & ThumbExpandImm12 +{ + build ItCond; + build ThumbExpandImm12; + Rd0811 = Rn0003 & ThumbExpandImm12; + resflags(Rd0811); + build thSBIT_ZN; +} + +:and^thSBIT_ZN^ItCond^".w" Rd0811,Rn0003,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=0 & thSBIT_ZN & Rn0003; thc1515=0 & Rd0811 & thshift2 +{ + build ItCond; + build thshift2; + Rd0811 = Rn0003 & thshift2; + resflags(Rd0811); + build thSBIT_ZN; +} +@endif # VERSION_6T2 || VERSION_7 + +macro th_set_carry_for_asr(op1,shift_count) { + local bit = (op1 s>> (shift_count-1)) & 1; + tmpCY = ((shift_count == 0) && CY) || ((shift_count != 0) && (bit != 0)); +} + +#note that this is a special case where immed5 = 0, which corresponds to a shift amount of 32 +:asr^CheckInIT_CZN^ItCond Rd0002,Rm0305,"#0x20" is TMode=1 & ItCond & op11=0x02 & Immed5 & Rm0305 & Rd0002 & immed5=0 & CheckInIT_CZN +{ + build ItCond; + th_set_carry_for_asr(Rm0305,32:1); + Rd0002 = Rm0305 s>> 32; + resflags(Rd0002); + build CheckInIT_CZN; +} + +:asr^CheckInIT_CZN^ItCond Rd0002,Rm0305,Immed5 is TMode=1 & ItCond & op11=0x02 & Immed5 & Rm0305 & Rd0002 & CheckInIT_CZN +{ + build ItCond; + th_set_carry_for_asr(Rm0305,Immed5); + Rd0002 = Rm0305 s>> Immed5; + resflags(Rd0002); + build CheckInIT_CZN; +} + +:asr^CheckInIT_CZN^ItCond Rd0002,Rs0305 is TMode=1 & ItCond & op6=0x104 & Rd0002 & Rs0305 & CheckInIT_CZN +{ + build ItCond; + local shift_amount = Rs0305 & 0xff; + th_set_carry_for_asr(Rd0002,shift_amount); + Rd0002 = Rd0002 s>> (shift_amount); + resflags(Rd0002); + build CheckInIT_CZN; +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:asr^thSBIT_CZN^ItCond^".w" Rd0811,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=2 & thSBIT_CZN & sop0003=0xf; thc1515=0 & Rd0811 & thc0405=2 & thshift2 +{ + build ItCond; + build thshift2; + Rd0811 = thshift2; + tmpCY = shift_carry; + resflags(Rd0811); + build thSBIT_CZN; +} + +:asr^thSBIT_CZN^ItCond^".w" Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op11=0x1f & thc0910=1 & sop0508=2 & thSBIT_CZN & Rn0003; op12=0xf & Rd0811 & sop0407=0 & Rm0003 +{ + build ItCond; + local shift_amount = Rm0003 & 0xff; + th_set_carry_for_asr(Rn0003,shift_amount); + Rd0811 = Rn0003 s>> (shift_amount); + resflags(Rd0811); + build thSBIT_CZN; +} +@endif # VERSION_6T2 || VERSION_7 + +# this constructor is identical to 16-bit udf instruction. it looks +# like it implented an unconditional branch instruction (giving it a +# made up name), but the thumb 16-bit instruction does not support +# unconditional branching. + +@ifdef NOT_AN_INSTRUCTION +:bal Addr8 is TMode=1 & op12=0xd & thcond=14 & Addr8 +{ + goto Addr8; +} +@endif + +:b^thcc Addr8 is TMode=1 & ItCond & op12=0b1101 & $(THCC) & Addr8 +{ + if (thcc) goto Addr8; +} + +:b^ItCond Addr11 is TMode=1 & ItCond & op11=0b11100 & Addr11 +{ + goto Addr11; +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:b^part2thcc^".w" ThAddr20 is TMode=1 & (part2op=0x1e & $(PART2THCC); part2c1415=2 & part2c1212=0) & ThAddr20 +{ + if (part2thcc) goto ThAddr20; +} + +:b^ItCond^".w" ThAddr24 is TMode=1 & ItCond & (op11=0x1e; part2c1415=2 & part2c1212=1) & ThAddr24 +{ + build ItCond; + goto ThAddr24; +} +@endif # VERSION_6T2 || VERSION_7 + + +@if defined(VERSION_6T2) || defined(VERSION_7) +:bfc^ItCond Rd0811,thLsbImm,thBitWidth is TMode=1 & ItCond & op0=0xf36f; thc1515=0 & Rd0811 & thc0505=0 & thLsbImm & thMsbImm & thBitWidth +{ + build ItCond; + clearMask:4 = (-1 << (thMsbImm + 1)) | (-1 >> (32 - thLsbImm)); + Rd0811 = Rd0811 & clearMask; +} + +:bfi^ItCond Rd0811,Rn0003,thLsbImm,thBitWidth is TMode=1 & ItCond & op4=0xf36 & Rn0003; thc1515=0 & Rd0811 & thc0505=0 & thLsbImm & thBitWidth +{ + build ItCond; + vmask:4 = (1 << thBitWidth) - 1; + clear:4 = ~(vmask << thLsbImm); + bits:4 = (Rn0003 & vmask) << thLsbImm; + Rd0811 = (Rd0811 & clear) | bits; +} + +@endif # VERSION_6T2 || VERSION_7 + + +:bic^CheckInIT_ZN^ItCond Rd0002,Rm0305 is TMode=1 & ItCond & op6=0x10e & Rd0002 & Rm0305 & CheckInIT_ZN +{ + build ItCond; + Rd0002 = Rd0002 & (~Rm0305); + resflags(Rd0002); + build CheckInIT_ZN; +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:bic^thSBIT_ZN^ItCond Rd0811,Rn0003,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=1 & thSBIT_ZN & Rn0003; thc1515=0 & Rd0811) & ThumbExpandImm12 +{ + build ItCond; + build ThumbExpandImm12; + Rd0811 = Rn0003&(~ThumbExpandImm12); + resflags(Rd0811); + build thSBIT_ZN; +} + +:bic^thSBIT_CZNO^ItCond^".w" Rd0811,Rn0003,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=1 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811 & thshift2 +{ + build ItCond; + build thshift2; + Rd0811 = Rn0003&(~thshift2); + th_logicflags(); + resflags(Rd0811); + build thSBIT_CZNO; +} +@endif # VERSION_6T2 || VERSION_7 + + +@if defined(VERSION_5) + +# Exception Generation and UDF + +:hlt immed6 is TMode=1 & op6=0b1011101010 & immed6 +{ + software_hlt(immed6:4); +} + +:bkpt immed8 is TMode=1 & ItCond & op8=0xbe & immed8 +{ + software_bkpt(immed8:4); + # Not a mistake, breakpoint always unconditional even in IT Block + build ItCond; +} + +:hvc "#"^tmp is TMode=1 & op4=0xf7e & thc0003; op12=0x8 & thc0011 [tmp = thc0003 << 12 | thc0011;] +{ + software_hvc(tmp:4); +} + +# Requires Security Extensions +:smc^ItCond "#"^thc0003 is TMode=1 & ItCond & op4=0xf7f & thc0003; op12=0x8 +{ + build ItCond; + software_smc(thc0003:1); +} + +@ifndef NOT_AN_INSTRUCTION +:udf^ItCond "#"thc0007 is TMode=1 & ItCond & op8 = 0xde & thc0007 +{ + build ItCond; + local excaddr:4 = inst_start; + local target:4 = software_udf(thc0007:4, excaddr); + goto [target]; +} +@endif + +:udf^ItCond "#"tmp is TMode=1 & ItCond & op4=0xf7f & thc0003; op12=0xa & thc0011 [tmp = thc0003 << 12 | thc0011;] +{ + build ItCond; + local excaddr:4 = inst_start; + local target:4 = software_udf(tmp:4, excaddr); + goto [target]; +} + +@endif # VERSION_5 + +:bl^ItCond ThAddr24 is TMode=1 & ItCond & (op11=0x1e; part2c1415=3 & part2c1212=1) & ThAddr24 +{ + build ItCond; + lr = inst_next|1; + SetThumbMode(1); + call ThAddr24; +} + +@ifndef VERSION_6T2 + +:bl^ItCond "#"^off is TMode=1 & ItCond & op11=0x1e & soffset11 [ off = inst_start + 4 + (soffset11 << 12); ] +{ + build ItCond; + lr = off:4; +} + +:bl^ItCond "#"^off is TMode=1 & ItCond & op11=0x1f & offset11 [ off = offset11 << 1; ] +{ + build ItCond; + local dest = lr + off:4; + lr = inst_next|1; + SetThumbMode(1); + call [dest]; +} + +:bl^ItCond lr is TMode=1 & ItCond & op11=0x1f & offset11=0 & lr +{ + build ItCond; + local dest = lr; + lr = inst_next|1; + SetThumbMode(1); + call [dest]; +} + +:blx^ItCond "#"^off is TMode=1 & ItCond & op11=0x1d & offset11 & thc0000=0 [ off = offset11 << 1; ] +{ + build ItCond; + local dest = (lr & (~0x3)) + off:4; + lr = inst_next|1; + SetThumbMode(0); + call [dest]; +} + +:blx^ItCond lr is TMode=1 & ItCond & op11=0x1d & offset11=0 & thc0000=0 & lr +{ + build ItCond; + local dest = (lr & (~0x3)); + lr = inst_next|1; + SetThumbMode(0); + call [dest]; +} + +@endif + +:bl^ItCond ThAddr24 is TMode=1 & CALLoverride=1 & ItCond & (op11=0x1e; part2c1415=3 & part2c1212=1) & ThAddr24 +{ + build ItCond; + lr = inst_next|1; + SetThumbMode(1); + goto ThAddr24; +} + +bxns: "" is thc0003 { } +bxns: "ns" is thc0002=0b100 { } + +@if defined(VERSION_5) + +:blx^ItCond ThArmAddr23 is TMode=1 & ItCond & (op11=0x1e;part2op=0x1d) & ThArmAddr23 [ TMode=0; globalset(ThArmAddr23,TMode); TMode=1; ] +{ + build ItCond; + lr = inst_next|1; + SetThumbMode(0); + call ThArmAddr23; + # Don't set this, assume return will set for emulation. Was screwing up decompiler. TB = 1; +} + +:blx^ItCond ThArmAddr23 is TMode=1 & ItCond & CALLoverride=1 & (op11=0x1e;part2op=0x1d) & ThArmAddr23 [ TMode=0; globalset(ThArmAddr23,TMode); TMode=1; ] +{ + build ItCond; + lr = inst_next|1; + SetThumbMode(0); + goto ThArmAddr23; +} + +:blx^ItCond ThArmAddr23 is TMode=1 & ItCond & (op11=0x1e; part2c1415=3 & part2c1212=0) & ThArmAddr23 [ TMode=0; globalset(ThArmAddr23,TMode); TMode=1; ] +{ + build ItCond; + lr = inst_next|1; + SetThumbMode(0); + call ThArmAddr23; +} + +:blx^bxns^ItCond Hrm0305 is TMode=1 & ItCond & op7=0x08f & Hrm0305 & bxns +{ + build ItCond; + BXWritePC(Hrm0305); + lr = inst_next|1; + call [pc]; + # Don't set this, assume return will set for emulation. Was screwing up decompiler. TB = 1; +} + +@endif # VERSION_5 + +:bx^bxns^ItCond Hrm0305 is TMode=1 & ItCond & op7=0x08e & Hrm0305 & hrm0305=6 & h2=1 & bxns +{ + build ItCond; + BXWritePC(Hrm0305); + return [pc]; +} + +:bx^bxns^ItCond Hrm0305 is TMode=1 & ItCond & op7=0x08e & Hrm0305 & bxns +{ + build ItCond; + BXWritePC(Hrm0305); + goto [pc]; +} + +:bx^bxns^ItCond Hrm0305 is TMode=1 & ItCond & LRset=1 & op7=0x08e & Hrm0305 & bxns [ LRset=0; TMode=1; globalset(inst_next,LRset); globalset(inst_next,TMode); ] +{ + build ItCond; + BXWritePC(Hrm0305); + call [pc]; + # Don't set this, assume return will set for emulation. Was screwing up decompiler. TB = 1; +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:bxj^ItCond Rn0003 is TMode=1 & ItCond & op4=0xf3c & Rn0003; op0=0x8f00 +{ + build ItCond; + success:1 = jazelle_branch(); + if (success) goto ; + SetThumbMode( (Rn0003&0x00000001)!=0 ); + local tmp=Rn0003&0xfffffffe; + goto [tmp]; + +} # Optional change to THUMB + +@endif # VERSION_6T2 || VERSION_7 + +:cbnz^ItCond Rn0002,Addr5 is TMode=1 & ItCond & op12=0xb & thc1111=1 & thc1010=0 & thc0808=1 & Rn0002 & Addr5 +{ + build ItCond; + local tmp = Rn0002 != 0; + if (tmp) goto Addr5; +} + +:cbz^ItCond Rn0002,Addr5 is TMode=1 & ItCond & op12=0xb & thc1111=0 & thc1010=0 & thc0808=1 & Rn0002 & Addr5 +{ + build ItCond; + local tmp = Rn0002 == 0; + if (tmp) goto Addr5; +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:cdp^ItCond thcpn,thopcode1,thCRd,thCRn,thCRm,thopcode2 is TMode=1 & ItCond & op8=0xee & thopcode1 & thCRn; thCRd & thcpn & thopcode2 & thc0404=0 & thCRm +{ + build ItCond; + t_cpn:4 = thcpn; + t_op1:4 = thopcode1; + t_op2:4 = thopcode2; + coprocessor_function(t_cpn,t_op1,t_op2,thCRd,thCRn,thCRm); +} + +:cdp2^ItCond thcpn,thopcode1,thCRd,thCRn,thCRm,thopcode2 is TMode=1 & ItCond & op8=0xfe & thopcode1 & thCRn; thCRd & thcpn & thopcode2 & thc0404=0 & thCRm +{ + build ItCond; + t_cpn:4 = thcpn; + t_op1:4 = thopcode1; + t_op2:4 = thopcode2; + coprocessor_function2(t_cpn,t_op1,t_op2,thCRd,thCRn,thCRm); +} + +define pcodeop IndexCheck; + +:chka^ItCond Hrn0002,Rm0306 is TMode=1 & ItCond & TEEMode=1 & op8=0xca & Rm0306 & Hrn0002 +{ + build ItCond; + local tmp = Hrn0002 <= Rm0306; + if (!tmp) goto inst_next; + lr = inst_next|1; + IndexCheck(); +} + +:clrex^ItCond is TMode=1 & ItCond & op0=0xf3bf; op0=0x8f2f +{ + build ItCond; + ClearExclusiveLocal(); +} + +:clz^ItCond Rd0811,Rm0003 is TMode=1 & ItCond & op4=0xfab & Rm0003; op12=15 & Rd0811 +{ + build ItCond; + Rd0811 = lzcount(Rm0003); +} + +:cmn^ItCond Rn0003,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=8 & thc0404=1 & Rn0003; thc1515=0 & thc0811=15) & ThumbExpandImm12 +{ + build ItCond; + th_addflags(Rn0003,ThumbExpandImm12); + local tmp = Rn0003 + ThumbExpandImm12; + resflags(tmp); + th_affectflags(); +} + +:cmn^ItCond^".w" Rn0003,thshift2 is TMode=1 & ItCond & op4=0xeb1 & Rn0003; thc1515=0 & thc0811=15 & thshift2 +{ + build ItCond; + build thshift2; + th_addflags(Rn0003,thshift2); + local tmp = Rn0003+thshift2; + resflags(tmp); + th_affectflags(); +} + +@endif # VERSION_6T2 || VERSION_7 + +:cmn^ItCond Rn0002,Rm0305 is TMode=1 & ItCond & op6=0x10b & Rm0305 & Rn0002 +{ + build ItCond; + th_addflags(Rn0002,Rm0305); + local tmp = Rn0002 + Rm0305; + resflags(tmp); + th_affectflags(); +} + +:cmp^ItCond Rn0810,Immed8 is TMode=1 & ItCond & op11=5 & Rn0810 & Immed8 +{ + build ItCond; + th_subflags(Rn0810,Immed8); + local tmp = Rn0810 - Immed8; + resflags(tmp); + th_affectflags(); +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:cmp^ItCond^".w" Rn0003,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & thc0404=1 & sop0508=13 & Rn0003; thc1515=0 & thc0811=15) & ThumbExpandImm12 +{ + build ItCond; + th_subflags(Rn0003,ThumbExpandImm12); + local tmp = Rn0003 - ThumbExpandImm12; + resflags(tmp); + th_affectflags(); +} + +:cmp^ItCond^".w" Rn0003,thshift2 is TMode=1 & ItCond & op4=0xebb & Rn0003; thc1515=0 & thc0811=15 & thshift2 +{ + build ItCond; + th_subflags(Rn0003,thshift2); + local tmp = Rn0003 - thshift2; + resflags(tmp); + th_affectflags(); +} + +@endif # VERSION_6T2 || VERSION_7 + +:cmp^ItCond Rn0002,Rm0305 is TMode=1 & ItCond & op6=0x10a & Rm0305 & Rn0002 +{ + build ItCond; + th_subflags(Rn0002,Rm0305); + local tmp = Rn0002 - Rm0305; + resflags(tmp); + th_affectflags(); +} + +:cmp^ItCond Hrn0002,Hrm0305 is TMode=1 & ItCond & op8=0x45 & Hrm0305 & Hrn0002 +{ + build ItCond; + th_subflags(Hrn0002,Hrm0305); + local tmp = Hrn0002 - Hrm0305; + resflags(tmp); + th_affectflags(); +} + +@if defined(VERSION_6) + +aflag: "a" is thc0202=1 & thc0404=0 { enableDataAbortInterrupts(); } +aflag: "a" is thc0202=1 { disableDataAbortInterrupts(); } +aflag: is thc0202=0 { } + +iflag: "i" is thc0101=1 & thc0404=0 { enableIRQinterrupts(); } # 7M: set primask +iflag: "i" is thc0101=1 { disableIRQinterrupts(); } # 7M: clear primask +iflag: is thc0101=0 { } + +fflag: "f" is thc0000=1 & thc0404=0 { enableFIQinterrupts(); } # 7M: set faultmask +fflag: "f" is thc0000=1 { disableFIQinterrupts(); } # 7M: clear faultmask +fflag: is thc0000=0 { } + +iflags: aflag^iflag^fflag is aflag & iflag & fflag { } + +:cpsie^ItCond iflags is TMode=1 & ItCond & op8=0xb6 & sop0507=3 & thc0303=0 & iflags & thc0404=0 +{ + build ItCond; + build iflags; + # see iflags for semantics +} + +:cpsid^ItCond iflags is TMode=1 & ItCond & op8=0xb6 & sop0507=3 & thc0303=0 & iflags & thc0404=1 +{ + build ItCond; + build iflags; + # see iflags for semantics +} + +@endif # VERSION_6 + +@if defined(VERSION_6T2) || defined(VERSION_7) + +# For SCR 11074, implement the "Encoding T2" 32-bit Thumb-2 cps change processor state instruction +# Note the manual says there are no conditions on this insn +# +th2_aflag: "a" is thc0707=1 & thc0910=0x2 { enableDataAbortInterrupts(); } +th2_aflag: "a" is thc0707=1 { disableDataAbortInterrupts(); } +th2_aflag: is thc0707=0 { } + +th2_iflag: "i" is thc0606=1 & thc0910=0x2 { enableIRQinterrupts(); } # 7M: set primask +th2_iflag: "i" is thc0606=1 { disableIRQinterrupts(); } # 7M: clear primask +th2_iflag: is thc0606=0 { } + +th2_fflag: "f" is thc0505=1 & thc0910=0 { enableFIQinterrupts(); } # 7M: set faultmask +th2_fflag: "f" is thc0505=1 { disableFIQinterrupts(); } # 7M: clear faultmask +th2_fflag: is thc0505=0 { } + +th2_iflags: th2_aflag^th2_iflag^th2_fflag is th2_aflag & th2_iflag & th2_fflag { } + +th2_SetMode: "#"^16 is thc0004=0x10 { setUserMode(); } +th2_SetMode: "#"^17 is thc0004=0x11 { setFIQMode(); } +th2_SetMode: "#"^18 is thc0004=0x12 { setIRQMode(); } +th2_SetMode: "#"^19 is thc0004=0x13 { setSupervisorMode(); } +th2_SetMode: "#"^22 is thc0004=0x16 { setMonitorMode(); } +th2_SetMode: "#"^23 is thc0004=0x17 { setAbortMode(); } +th2_SetMode: "#"^27 is thc0004=0x1b { setUndefinedMode(); } +th2_SetMode: "#"^31 is thc0004=0x1f { setSystemMode(); } + +# 11110 0 1110 1 0 1111 10 0 0 0 +:cpsie th2_iflags, th2_SetMode is + TMode=1 & part2op=0x1e & part2S=0x0 & part2cond=0xe & part2imm6=0x2f ; + thc0910=0x2 & th2_SetMode & op11=0x10 & th2_iflags +{ + build th2_iflags; +} + +:cpsid th2_iflags, th2_SetMode is + TMode=1 & part2op=0x1e & part2S=0x0 & part2cond=0xe & part2imm6=0x2f ; + thc0910=0x3 & th2_SetMode & op11=0x10 & th2_iflags +{ + build th2_iflags; +} + +:cps th2_SetMode is + TMode=1 & part2op=0x1e & part2S=0x0 & part2cond=0xe & part2imm6=0x2f ; + thc0808=0x1 & th2_SetMode & op11=0x10 +{ +} + +@endif # (VERSION_6T2) || defined(VERSION_7) + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:dbg^ItCond "#"^thc0004 is TMode=1 & ItCond & op0=0xf3af; op4=0x80f & thc0004 +{ +@if defined(VERSION_7) + HintDebug(thc0004:1); +@endif # VERSION_7 +} + +@if defined(VERSION_7) +:dmb^ItCond "#"^thc0004 is TMode=1 & ItCond & op0=0xf3bf; op4=0x8f5 & thc0004 +{ + DataMemoryBarrier(thc0004:1); +} + +:dsb^ItCond "#"^thc0004 is TMode=1 & ItCond & op0=0xf3bf; op4=0x8f4 & thc0004 +{ + DataSynchronizationBarrier(thc0004:1); +} +@endif + +:eor^thSBIT_CZNO^ItCond Rd0811,Rn0003,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=4 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811) & ThumbExpandImm12 +{ + build ItCond; + Rd0811 = Rn0003 ^ ThumbExpandImm12; + th_logicflags(); + resflags(Rd0811); + build thSBIT_CZNO; +} + +:eor^thSBIT_CZNO^ItCond^".w" Rd0811,Rn0003,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=4 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811 & thshift2 +{ + build ItCond; + Rd0811 = Rn0003 ^ thshift2; + th_logicflags(); + resflags(Rd0811); + build thSBIT_CZNO; +} + + +:enterx^ItCond is TMode=1 & ItCond & op0=0xf3bf; op0=0x8f1f [ TEEMode=1; globalset(inst_next,TEEMode); ] +{ + build ItCond; +} + +:leavex^ItCond is TMode=1 & ItCond & op0=0xf3bf; op0=0x8f0f [ TEEMode=0; globalset(inst_next,TEEMode); ] +{ + build ItCond; +} + +@endif # VERSION_6T2 || VERSION_7 + + +:eor^CheckInIT_ZN^ItCond Rd0002,Rm0305 is TMode=1 & ItCond & op6=0x101 & Rm0305 & Rd0002 & CheckInIT_ZN +{ + build ItCond; + Rd0002 = Rd0002 ^ Rm0305; + resflags(Rd0002); + build CheckInIT_ZN; +} + +@if defined(VERSION_7) + +:hb^ItCond "#"^immed8 is TMode=1 & ItCond & TEEMode=1 & op9=0x61 & immed8 +{ + build ItCond; +} + + +:isb^ItCond "#"^thc0004 is TMode=1 & ItCond & op0=0xf3bf; op4=0x8f6 & thc0004 +{ + InstructionSynchronizationBarrier(thc0004:1); +} + +@endif # VERSION_7 + +@if defined(VERSION_8) + +# F5.1.178 p2969 SEVL T1 variant +:sevl + is TMode=1 & op0=0b1011111101010000 + & ItCond + { + build ItCond; + SendEvent(); + } + +@endif # VERSION_8 + +@if defined(VERSION_6T2) || defined(VERSION_7) +X: "t" is TMode=1 & ((thc0404=1 & thc0303=1) | (thc0404=0 & thc0303=0)) & (thc0202=1 | thc0101=1 | thc0000=1) { } +X: "e" is TMode=1 & ((thc0404=1 & thc0303=0) | (thc0404=0 & thc0303=1)) & (thc0202=1 | thc0101=1 | thc0000=1) { } +X: "" is TMode=1 & thc0404 & thc0303 & (thc0202=0 & thc0101=0 & thc0000=0) { } +Y: "t" is TMode=1 & ((thc0404=1 & thc0202=1) | (thc0404=0 & thc0202=0)) & (thc0101=1 | thc0000=1) { } +Y: "e" is TMode=1 & ((thc0404=1 & thc0202=0) | (thc0404=0 & thc0202=1)) & (thc0101=1 | thc0000=1) { } +Y: "" is TMode=1 & thc0404 & thc0202 & (thc0101=0 & thc0000=0) { } +Z: "t" is TMode=1 & ((thc0404=1 & thc0101=1) | (thc0404=0 & thc0101=0)) & (thc0000=1) { } +Z: "e" is TMode=1 & ((thc0404=1 & thc0101=0) | (thc0404=0 & thc0101=1)) & (thc0000=1) { } +Z: "" is TMode=1 & thc0404 & thc0101 & (thc0000=0) { } + +XYZ: is TMode=1 & sop0003=8 { } +XYZ: X^Y^Z is TMode=1 & X & Y & Z { } + + +:it^XYZ it_thfcc is TMode=1 & op8=0xbf & XYZ & $(IT_THFCC) & thc0507 & thc0004 + [ itmode=0; cond_base = thc0507; cond_shft=thc0004; globalset(inst_next,condit); ] +{ + # just sets up the condition and If Then/Else mask +} + +:ldc^ItCond thcpn,thCRd,taddrmode5 is (TMode=1 & ItCond & op9=0x76 & thN6=0 & thL4=1; thCRd & thcpn) & taddrmode5 +{ + build ItCond; + build taddrmode5; + t_cpn:4 = thcpn; + coprocessor_load(t_cpn,thCRd,taddrmode5); +} + +:ldcl^ItCond thcpn,thCRd,taddrmode5 is (TMode=1 & ItCond & op9=0x76 & thN6=1 & thL4=1; thCRd & thcpn) & taddrmode5 +{ + build ItCond; + build taddrmode5; + t_cpn:4 = thcpn; + coprocessor_loadlong(t_cpn,thCRd,taddrmode5); +} + +:ldc2^ItCond thcpn,thCRd,taddrmode5 is (TMode=1 & ItCond & op9=0x7e & thN6=0 & thL4=1; thCRd & thcpn) & taddrmode5 +{ + build ItCond; + build taddrmode5; + t_cpn:4 = thcpn; + coprocessor_load(t_cpn,thCRd,taddrmode5); +} + +:ldc2l^ItCond thcpn,thCRd,taddrmode5 is (TMode=1 & ItCond & op9=0x7e & thN6=1 & thL4=1; thCRd & thcpn) & taddrmode5 +{ + build ItCond; + build taddrmode5; + t_cpn:4 = thcpn; + coprocessor_loadlong(t_cpn,thCRd,taddrmode5); +} + +@endif # VERSION_6T2 || VERSION_7 + +:ldmia^ItCond Rn_exclaim,ldbrace is TMode=1 & ItCond & op11=0x19 & Rn_exclaim & ldbrace & Rn_exclaim_WB +{ + build ItCond; + build Rn_exclaim; + build ldbrace; + build Rn_exclaim_WB; +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:ldm^ItCond^".w" Rn0003,thldrlist_inc is TMode=1 & ItCond & op11=0x1d & thc0910=0 & sop0608=2 & thwbit=0 & thc0404=1 & Rn0003; thc1313=0 & thldrlist_inc +{ + build ItCond; + mult_addr = Rn0003; + build thldrlist_inc; +} + +:ldm^ItCond^".w" Rn0003!,thldrlist_inc is TMode=1 & ItCond & op11=0x1d & thc0910=0 & sop0608=2 & thwbit=1 & thc0404=1 & Rn0003; thc1313=0 & thldrlist_inc +{ + build ItCond; + mult_addr = Rn0003; + build thldrlist_inc; + Rn0003 = mult_addr; +} + +:ldm^ItCond Rn0003,thldrlist_inc is TMode=1 & ItCond & op11=0x1d & thc0910=0 & sop0608=2 & thwbit=0 & thc0404=1 & Rn0003; thc1515=1 & thc1313=0 & thldrlist_inc +{ + build ItCond; + mult_addr = Rn0003; + build thldrlist_inc; + LoadWritePC(pc); + goto [pc]; +} + +:ldm^ItCond^".w" Rn0003,thldrlist_inc is TMode=1 & ItCond & op11=0x1d & thc0910=0 & sop0608=2 & thwbit=1 & thc0404=1 & Rn0003; thc1515=1 & thc1313=0 & thldrlist_inc +{ + build ItCond; + mult_addr = Rn0003; + build thldrlist_inc; + Rn0003 = mult_addr; + LoadWritePC(pc); + goto [pc]; +} + + +:ldmdb^ItCond Rn0003,thldrlist_dec is TMode=1 & ItCond & op4=0xe91 & Rn0003; thc1313=0 & thldrlist_dec +{ + build ItCond; + mult_addr = Rn0003-4; + build thldrlist_dec; +} + +:ldmdb^ItCond Rn0003!,thldrlist_dec is TMode=1 & ItCond & op4=0xe93 & Rn0003; thc1313=0 & thldrlist_dec +{ + build ItCond; + mult_addr = Rn0003-4; + build thldrlist_dec; + Rn0003 = mult_addr + 4; +} + +:ldmdb^ItCond Rn0003,thldrlist_dec is TMode=1 & ItCond & op4=0xe91 & Rn0003; thc1515=1 & thc1313=0 & thldrlist_dec +{ + build ItCond; + mult_addr = Rn0003-4; + build thldrlist_dec; + LoadWritePC(pc); + goto [pc]; +} + +:ldmdb^ItCond Rn0003,thldrlist_dec is TMode=1 & ItCond & op4=0xe93 & Rn0003; thc1515=1 & thc1313=0 & thldrlist_dec +{ + build ItCond; + mult_addr = Rn0003-4; + build thldrlist_dec; + Rn0003 = mult_addr + 4; + LoadWritePC(pc); + goto [pc]; +} + +@endif # VERSION_6T2 || VERSION_7 + +:ldr^ItCond Rd0002,RnIndirect4 is TMode=1 & ItCond & op11=0xd & RnIndirect4 & Rd0002 +{ + build ItCond; + build RnIndirect4; + Rd0002 = *RnIndirect4; +} + +:ldr^ItCond Rd0002,RnRmIndirect is TMode=1 & ItCond & op9=0x2c & RnRmIndirect & Rd0002 +{ + build ItCond; + build RnRmIndirect; + Rd0002 = *RnRmIndirect; +} + +:ldr^ItCond Rd0810,Pcrel8Indirect is TMode=1 & ItCond & op11=9 & Pcrel8Indirect & Rd0810 +{ + build ItCond; + build Pcrel8Indirect; + Rd0810 = Pcrel8Indirect; +} + + # Note: NO '*' IS INTENTIONAL +:ldr^ItCond Rd0810,Sprel8Indirect is TMode=1 & ItCond & op11=0x13 & Sprel8Indirect & Rd0810 +{ + build ItCond; + build Sprel8Indirect; + Rd0810 = *Sprel8Indirect; +} + +:ldrb^ItCond Rd0002,RnIndirect1 is TMode=1 & ItCond & op11=0xf & RnIndirect1 & Rd0002 +{ + build ItCond; + build RnIndirect1; + Rd0002 = zext( *:1 RnIndirect1 ); +} + +:ldrb^ItCond Rd0002,RnRmIndirect is TMode=1 & ItCond & op9=0x2e & RnRmIndirect & Rd0002 +{ + build ItCond; + build RnRmIndirect; + Rd0002 = zext( *:1 RnRmIndirect); +} + +:ldrh^ItCond Rd0002,RnIndirect2 is TMode=1 & ItCond & op11=0x11 & RnIndirect2 & Rd0002 +{ + build ItCond; + build RnIndirect2; + Rd0002 = zext( *:2 RnIndirect2); +} + +:ldrh^ItCond Rd0002,RnRmIndirect is TMode=1 & ItCond & op9=0x2d & RnRmIndirect & Rd0002 +{ + build ItCond; + build RnRmIndirect; + Rd0002 = zext( *:2 RnRmIndirect); +} + +:ldrsb^ItCond Rd0002,RnRmIndirect is TMode=1 & ItCond & op9=0x2b & RnRmIndirect & Rd0002 +{ + build ItCond; + build RnRmIndirect; + Rd0002 = sext( *:1 RnRmIndirect); +} + +:ldrsh^ItCond Rd0002,RnRmIndirect is TMode=1 & ItCond & op9=0x2f & RnRmIndirect & Rd0002 +{ + build ItCond; + build RnRmIndirect; + Rd0002 = sext( *:2 RnRmIndirect); +} + +define pcodeop ExclusiveAccess; + +@if defined(VERSION_7) + +:ldrexb^ItCond Rt1215,[Rn0003] is TMode=1 & ItCond & op4=0xe8d & Rn0003; Rt1215 & thc0811=15 & thc0407=4 & thc0003=15 +{ + build ItCond; + local tmp = Rn0003; + ExclusiveAccess(tmp); + val:1 = *tmp; + Rt1215 = zext(val); +} + +:ldrexh^ItCond Rt1215,[Rn0003] is TMode=1 & ItCond & op4=0xe8d & Rn0003; Rt1215 & thc0811=15 & thc0407=5 & thc0003=15 +{ + build ItCond; + local tmp = Rn0003; + ExclusiveAccess(tmp); + val:2 = *tmp; + Rt1215 = zext(val); +} + +:ldrexd^ItCond Rt1215,Rt0811,[Rn0003] is TMode=1 & ItCond & op4=0xe8d & Rn0003; Rt1215 & Rt0811 & thc0407=7 & thc0003=15 +{ + build ItCond; + local tmp = Rn0003; + ExclusiveAccess(tmp); + val1:4 = *tmp; + val2:4 = *(tmp + 4); + Rt1215 = val1; + Rt0811 = val2; +} + +@endif # VERSION_7 + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:ldrex^ItCond Rt1215,[Rn0003,Immed8_4] is TMode=1 & ItCond & op4=0xe85 & Rn0003; Rt1215 & thc0811=15 & Immed8_4 +{ + build ItCond; + local tmp = Rn0003 + Immed8_4; + ExclusiveAccess(tmp); + Rt1215 = *tmp; +} + +# overlaps patterns with the other ldr intructions when Rn==1111, therefore it must occur first +:ldr^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf85 & sop0003=15; Rt1215 & RtGotoCheck) & PcrelOffset12 +{ + build ItCond; + build PcrelOffset12; + Rt1215 = PcrelOffset12:4; + build RtGotoCheck; +} + +:ldr^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf8d & sop0003=15; Rt1215 & RtGotoCheck) & PcrelOffset12 +{ + build ItCond; + build PcrelOffset12; + Rt1215 = PcrelOffset12:4; + build RtGotoCheck; +} + +:ldr^ItCond^".w" Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf8d; Rt1215 & RtGotoCheck) & RnIndirect12 +{ + build ItCond; + build RnIndirect12; + Rt1215 = *RnIndirect12; + build RtGotoCheck; +} + +:ldr^ItCond^".w" Rt1215,RnIndirectPUW is TMode=1 & ItCond & (op4=0xf85; Rt1215 & thc1111=1 & RtGotoCheck) & $(RN_INDIRECT_PUW) +{ + build ItCond; + build RnIndirectPUW; + Rt1215 = *RnIndirectPUW; + build RtGotoCheck; +} + +:ldr^ItCond^".w" Rt1215,[Rn0003,Rm0003] is TMode=1 & ItCond & op4=0xf85 & Rn0003; Rt1215 & RtGotoCheck & thc1111=0 & sop0610=0 & thc0405=0 & Rm0003 +{ + build ItCond; + local tmp = Rn0003 + Rm0003; + Rt1215 = *tmp; + build RtGotoCheck; +} + +:ldr^ItCond^".w" Rt1215,[Rn0003,Rm0003,"lsl #"^thc0405] is TMode=1 & ItCond & op4=0xf85 & Rn0003; Rt1215 & RtGotoCheck & thc1111=0 & sop0610=0 & thc0405 & Rm0003 +{ + build ItCond; + local tmp = Rn0003 + (Rm0003 << thc0405); + Rt1215 = *tmp; + build RtGotoCheck; +} + +:ldrb^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf81 & sop0003=15; Rt1215) & PcrelOffset12 +{ + build ItCond; + build PcrelOffset12; + tmp:1 = PcrelOffset12:1; + Rt1215 = zext(tmp); +} + +# overlaps patterns with the other ldrb intructions when Rn==1111, therefore it must occur first +:ldrb^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf89 & sop0003=15; Rt1215) & PcrelOffset12 +{ + build ItCond; + build PcrelOffset12; + tmp:1 = PcrelOffset12:1; + Rt1215 = zext(tmp); +} + +:ldrb^ItCond^".w" Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf89; Rt1215) & RnIndirect12 +{ + build ItCond; + build RnIndirect12; + tmp:1 = *RnIndirect12; + Rt1215 = zext(tmp); +} + +:ldrb^ItCond^".w" Rt1215,RnIndirectPUW is TMode=1 & ItCond & (op4=0xf81; Rt1215 & thc1111=1) & $(RN_INDIRECT_PUW) +{ + build ItCond; + build RnIndirectPUW; + tmp:1 = *RnIndirectPUW; + Rt1215 = zext(tmp); +} + +:ldrb^ItCond^".w" Rt1215,[Rn0003,Rm0003,"lsl #"^thc0405] is TMode=1 & ItCond & op4=0xf81 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003 +{ + build ItCond; + local tmp = Rn0003 + (Rm0003 << thc0405); + val:1 = *tmp; + Rt1215 = zext(val); +} + + +:ldrbt^ItCond^".w" Rt1215,[Rn0003,"#"^Immed8] is TMode=1 & ItCond & op4=0xf81 & Rn0003; Rt1215 & thc0811=14 & Immed8 +{ + build ItCond; + local tmp = Rn0003 + Immed8; + val:1 = *tmp; + Rt1215 = zext(val); +} + + +# overlaps patterns with the other ldrd intructions when Rn==1111, therefore it must occur first +:ldrd^ItCond Rt1215,Rt0811,Pcrel8_s8 is TMode=1 & ItCond & op9=0x74 & thc0606=1 & thc0404=1 & sop0003=15; Rt1215 & Rt0811 & Pcrel8_s8 +{ + build ItCond; + build Pcrel8_s8; + local val = Pcrel8_s8; + Rt1215 = val(4); + Rt0811 = val(0); +} + +:ldrd^ItCond Rt1215,Rt0811,RnIndirectPUW1 is TMode=1 & ItCond & (op9=0x74 & thc0606=1 & thc0404=1 & Rn0003; Rt1215 & Rt0811) & $(RN_INDIRECT_PUW1) +{ + build ItCond; + build RnIndirectPUW1; + Rt1215 = *RnIndirectPUW1; + Rt0811 = *(RnIndirectPUW1+4); +} + + +# pldw must come before ldrh.w because of overlap of Rt != 1111 in ldrh.w +:pldw^ItCond Rn0003,"#"^offset12 is TMode=1 & ItCond & op6=0x3e2 & thwbit=1 & thc0404=1 & Rn0003; op12=0xf & offset12 +{ + build ItCond; + addr:4 = Rn0003 + offset12; + HintPreloadDataForWrite(addr); +} + +:pldw^ItCond Rn0003,"#-"^immed8 is TMode=1 & ItCond & op6=0x3e0 & thwbit=1 & thc0404=1 & Rn0003; op8=0xfc & immed8 +{ + build ItCond; + addr:4 = Rn0003 - immed8; + HintPreloadDataForWrite(addr); +} + +:pldw^ItCond Rn0003,Rm0003,"lsl #"^thc0405 is TMode=1 & ItCond & op6=0x3e0 & thwbit=1 & thc0404=1 & Rn0003; op8=0xf0 & thc0607=0 & thc0405 & Rm0003 +{ + build ItCond; + addr:4 = Rn0003 + (Rm0003 << thc0405); + HintPreloadDataForWrite(addr); +} + + +# overlaps patterns with the other ldrh intructions when Rn==1111, therefore it must occur first +:ldrh^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf83 & sop0003=15; Rt1215) & PcrelOffset12 +{ + build ItCond; + local tmp = PcrelOffset12:2; + Rt1215 = zext(tmp); +} +:ldrh^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf8b & sop0003=15; Rt1215) & PcrelOffset12 +{ + build ItCond; + tmp:2 = PcrelOffset12:2; + Rt1215 = zext(tmp); +} + +:ldrh.w^ItCond Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf8B; Rt1215) & RnIndirect12 +{ + build ItCond; + build RnIndirect12; + tmp:2 = *RnIndirect12; + Rt1215 = zext(tmp); +} + +:ldrh^ItCond^".w" Rt1215,RnIndirectPUW is TMode=1 & ItCond & (op4=0xf83; Rt1215 & thc1111=1) & $(RN_INDIRECT_PUW) +{ + build ItCond; + build RnIndirectPUW; + tmp:2 = *RnIndirectPUW; + Rt1215 = zext(tmp); +} + +:ldrh^ItCond^".w" Rt1215,[Rn0003,Rm0003,"lsl #"^thc0405] is TMode=1 & ItCond & op4=0xf83 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003 +{ + build ItCond; + local tmp = Rn0003 + (Rm0003 << thc0405); + val:2 = *tmp; + Rt1215 = zext(val); +} + +:ldrht^ItCond^".w" Rt1215,[Rn0003,"#"^Immed8] is TMode=1 & ItCond & op4=0xf83 & Rn0003; Rt1215 & thc0811=14 & Immed8 +{ + build ItCond; + local tmp = Rn0003 + Immed8; + val:2 = *tmp; + Rt1215 = zext(val); +} + + +# pli moevd above ldrsb to avoid conflict for ldrsb when Rt == 1111 +:pli^ItCond Rn0003,"#"^offset12 is TMode=1 & ItCond & op4=0xf99 & Rn0003; op12=0xf & offset12 +{ + build ItCond; + addr:4 = Rn0003 + offset12; + HintPreloadInstruction(addr); +} + +:pli^ItCond Rn0003,"#-"^immed8 is TMode=1 & ItCond & op4=0xf91 & Rn0003; op8=0xfc & immed8 +{ + build ItCond; + addr:4 = Rn0003 - immed8; + HintPreloadInstruction(addr); +} + +:pli^ItCond PcrelOffset12 is TMode=1 & ItCond & (op8=0xf9 & thc0506=0 & thc0004=0x1f; thc1215=0xf) & PcrelOffset12 +{ + build ItCond; + HintPreloadInstruction(PcrelOffset12); +} + +:pli^ItCond Rn0003,Rm0003"lsl #"^thc0405 is TMode=1 & ItCond & op4=0xf91 & Rn0003; op6=0x3c0 & thc0405 & Rm0003 +{ + build ItCond; + addr:4 = Rn0003 + (Rm0003 << thc0405); + HintPreloadInstruction(addr); +} + + +# overlaps patterns with the other ldrsb intructions when Rn==1111, therefore it must occur first +:ldrsb^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op8=0xf9 & thc0506=0 & thc0404=1 & sop0003=15; Rt1215) & PcrelOffset12 +{ + build ItCond; + tmp:1 = *PcrelOffset12; + Rt1215 = sext(tmp); +} + +:ldrsb^ItCond^".w" Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf99; Rt1215) & RnIndirect12 +{ + build ItCond; + tmp:1 = *RnIndirect12; + Rt1215 = sext(tmp); +} + +:ldrsb^ItCond^".w" Rt1215,RnIndirectPUW is TMode=1 & ItCond & (op4=0xf91; Rt1215 & thc1111=1) & $(RN_INDIRECT_PUW) +{ + build ItCond; + build RnIndirectPUW; + tmp:1 = *RnIndirectPUW; + Rt1215 = sext(tmp); +} + +:ldrsb^ItCond^".w" Rt1215,[Rn0003,Rm0003,"lsl #"^thc0405] is TMode=1 & ItCond & op4=0xf91 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003 +{ + build ItCond; + local tmp = Rn0003 + (Rm0003 << thc0405); + val:1 = *tmp; + Rt1215 = sext(val); +} + +:ldrsbt^ItCond^".w" Rt1215,[Rn0003,"#"^Immed8] is TMode=1 & ItCond & op4=0xf91 & Rn0003; Rt1215 & thc0811=14 & Immed8 +{ + build ItCond; + local tmp = Rn0003 + Immed8; + val:1 = *tmp; + Rt1215 = sext(val); +} + + +# overlaps patterns with the other ldr intructions when Rn==1111, therefore it must occur first +:ldrsh^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op8=0xf9 & thc0506=1 & thc0404=1 & sop0003=15; Rt1215) & PcrelOffset12 +{ + build ItCond; + build PcrelOffset12; + tmp:2 = *PcrelOffset12; + Rt1215 = sext(tmp); +} + +:ldrsh^ItCond^".w" Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf9B; Rt1215) & RnIndirect12 +{ + build ItCond; + tmp:2 = *RnIndirect12; + Rt1215 = sext(tmp); +} + +:ldrsh^ItCond^".w" Rt1215,RnIndirectPUW is TMode=1 & ItCond & (op4=0xf93; Rt1215 & thc1111=1) & $(RN_INDIRECT_PUW) +{ + build ItCond; + build RnIndirectPUW; + tmp:2 = *RnIndirectPUW; + Rt1215 = sext(tmp); +} + +:ldrsh^ItCond^".w" Rt1215,[Rn0003,Rm0003,"lsl #"^thc0405] is TMode=1 & ItCond & op4=0xf93 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003 +{ + build ItCond; + local tmp = Rn0003 + (Rm0003 << thc0405); + val:2 = *tmp; + Rt1215 = sext(val); +} + +:ldrsht^ItCond^".w" Rt1215,[Rn0003,"#"^Immed8] is TMode=1 & ItCond & op4=0xf93 & Rn0003; Rt1215 & thc0811=14 & Immed8 +{ + build ItCond; + local tmp = Rn0003 + Immed8; + val:2 = *tmp; + Rt1215 = sext(val); +} + +:ldrt^ItCond^".w" Rt1215,[Rn0003,"#"^Immed8] is TMode=1 & ItCond & op4=0xf85 & Rn0003; Rt1215 & thc0811=14 & Immed8 +{ + build ItCond; + local tmp = Rn0003 + Immed8; + Rt1215 = *tmp; +} + +@endif # VERSION_6T2 || VERSION_7 + +macro th_set_carry_for_lsl(op1,shift_count) { + local bit = (op1 << (shift_count-1)) & 0x80000000; + tmpCY = ((shift_count == 0) && CY) || ((shift_count != 0) && (bit != 0)); +} + +:lsl^CheckInIT_CZN^ItCond Rd0002,Rm0305,Immed5 is TMode=1 & ItCond & op11=0x0 & Immed5 & Rm0305 & Rd0002 & CheckInIT_CZN +{ + build ItCond; + th_set_carry_for_lsl(Rm0305,Immed5); + Rd0002 = Rm0305 << Immed5; + resflags(Rd0002); + build CheckInIT_CZN; +} + +:lsl^CheckInIT_CZN^ItCond Rd0002,Rs0305 is TMode=1 & ItCond & op6=0x102 & Rs0305 & Rd0002 & CheckInIT_CZN +{ + build ItCond; + local shift_count = Rs0305 & 0xff; + th_set_carry_for_lsl(Rd0002,shift_count); + Rd0002 = Rd0002 << shift_count; + resflags(Rd0002); + build CheckInIT_CZN; +} + +macro th_set_carry_for_lsr(op1,shift_count) { + local bit = (op1 >> (shift_count-1)) & 1; + tmpCY = ((shift_count == 0) && CY) || ((shift_count != 0) && (bit != 0)); +} + +#note that this is a special case where immed5 = 0, which corresponds to a shift amount of 32 +:lsr^CheckInIT_CZN^ItCond Rd0002,Rm0305,"#0x20" is TMode=1 & ItCond & op11=1 & Immed5 & Rm0305 & Rd0002 & immed5=0 & CheckInIT_CZN +{ + build ItCond; + th_set_carry_for_lsr(Rm0305,32:1); + Rd0002 = Rm0305 >> 32; + resflags(Rd0002); + build CheckInIT_CZN; +} + +:lsr^CheckInIT_CZN^ItCond Rd0002,Rm0305,Immed5 is TMode=1 & ItCond & op11=1 & Immed5 & Rm0305 & Rd0002 & CheckInIT_CZN +{ + build ItCond; + local shift_amount = Immed5; + th_set_carry_for_lsr(Rm0305,shift_amount); + Rd0002 = Rm0305 >> Immed5; + resflags(Rd0002); + build CheckInIT_CZN; +} + +:lsr^CheckInIT_CZN^ItCond Rd0002,Rs0305 is TMode=1 & ItCond & op6=0x103 & Rd0002 & Rs0305 & CheckInIT_CZN +{ + build ItCond; + local shift_amount = (Rs0305 & 0xff); + th_set_carry_for_lsr(Rd0002,shift_amount); + Rd0002 = Rd0002 >> (Rs0305 & 0xff); + resflags(Rd0002); + build CheckInIT_CZN; +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:lsl^thSBIT_CZN^ItCond^".w" Rd0811,Rm0003,thLsbImm is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=2 & thSBIT_CZN & sop0003=15; thc1515=0 & Rd0811 & thc0405=0 & Rm0003 & thLsbImm +{ + build ItCond; + th_set_carry_for_lsl(Rm0003,thLsbImm); + Rd0811 = Rm0003 << thLsbImm; + resflags(Rd0811); + build thSBIT_CZN; +} + +:lsl^thSBIT_CZN^ItCond^".w" Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op11=0x1f & thc0910=1 & sop0508=0 & thSBIT_CZN & Rn0003; op12=15 & Rd0811 & sop0407=0 & Rm0003 +{ + build ItCond; + local shift_amount = (Rm0003 & 0xff); + th_set_carry_for_lsl(Rn0003,shift_amount); + Rd0811 = Rn0003 << (shift_amount); + resflags(Rd0811); + build thSBIT_CZN; +} + +:lsr^thSBIT_CZN^ItCond^".w" Rd0811,Rm0003,thLsbImm is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=2 & thSBIT_CZN & sop0003=15; thc1515=0 & Rd0811 & thc0405=1 & Rm0003 & thLsbImm +{ + build ItCond; + th_set_carry_for_lsr(Rm0003,thLsbImm); + Rd0811 = Rm0003 >> thLsbImm; + resflags(Rd0811); + build thSBIT_CZN; +} + +:lsr^thSBIT_CZN^ItCond^".w" Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op11=0x1f & thc0910=1 & sop0508=1 & thSBIT_CZN & Rn0003; op12=15 & Rd0811 & sop0407=0 & Rm0003 +{ + build ItCond; + local shift_amount = Rm0003 & 0xff; + th_set_carry_for_lsr(Rn0003,shift_amount); + Rd0811 = Rn0003 >> shift_amount; + resflags(Rd0811); + build thSBIT_CZN; +} + + +@endif # VERSION_6T2 || VERSION_7 + +:mcr^ItCond thcpn,thc0507,Rt1215,thCRn,thCRm,thopcode2 is TMode=1 & ItCond & op8=0xee & thc0507 & thc0404=0 & thCRn; Rt1215 & thcpn & thopcode2 & thc0404=1 & thCRm +{ + build ItCond; + t_cpn:4 = thcpn; + t_op1:4 = thc0507; + t_op2:4 = thopcode2; + coprocessor_moveto(t_cpn,t_op1,t_op2,Rt1215,thCRn,thCRm); +} + +:mcr2^ItCond thcpn,thc0507,Rt1215,thCRn,thCRm,thopcode2 is TMode=1 & ItCond & op8=0xfe & thc0507 & thc0404=0 & thCRn; Rt1215 & thcpn & thopcode2 & thc0404=1 & thCRm +{ + build ItCond; + t_cpn:4 = thcpn; + t_op1:4 = thc0507; + t_op2:4 = thopcode2; + coprocessor_moveto(t_cpn,t_op1,t_op2,Rt1215,thCRn,thCRm); +} + +:mcrr^ItCond thcpn,thopcode1,Rt1215,Rn0003,thCRm is TMode=1 & ItCond & op4=0xec4 & Rn0003; Rt1215 & thcpn & thopcode1 & thCRm +{ + build ItCond; + t_cpn:4 = thcpn; + t_op:4 = thopcode1; + coprocessor_moveto2(t_cpn,t_op,Rt1215,Rn0003,thCRm); +} + +:mcrr^ItCond thcpn,thopcode1,Rt1215,Rn0003,thCRm is TMode=1 & ItCond & op4=0xfc4 & Rn0003; Rt1215 & thcpn & thopcode1 & thCRm +{ + build ItCond; + t_cpn:4 = thcpn; + t_op:4 = thopcode1; + coprocessor_moveto2(t_cpn,t_op,Rt1215,Rn0003,thCRm); +} + + +:mov^CheckInIT_ZN^ItCond Rd0810,Immed8 is TMode=1 & ItCond & op11=4 & Rd0810 & Immed8 & CheckInIT_ZN +{ + build ItCond; + Rd0810 = Immed8; + resflags(Rd0810); + build CheckInIT_ZN; +} + +:mov^CheckInIT_ZN^ItCond Rd0002,Rn0305 is TMode=1 & ItCond & op6=0x000 & Rn0305 & Rd0002 & CheckInIT_ZN +{ + build ItCond; + Rd0002 = Rn0305; + resflags(Rd0002); + build CheckInIT_ZN; +} + +:mov^ItCond Hrd0002,Hrm0305 is TMode=1 & ItCond & op8=0x46 & Hrm0305 & Hrd0002 +{ + build ItCond; + Hrd0002 = Hrm0305; +} + +:mov^ItCond Hrd0002,Hrm0305 is TMode=1 & ItCond & op8=0x46 & Hrm0305 & Hrd0002 & hrd0002=7 & h1=1 +{ + build ItCond; + dest:4 = Hrm0305; + BranchWritePC(dest); + goto [pc]; +} + +:mov^ItCond Hrd0002,Hrm0305 is TMode=1 & ItCond & op8=0x46 & Hrm0305 & rm0306=14 & Hrd0002 & hrd0002=7 & h1=1 +{ + build ItCond; + dest:4 = Hrm0305; + BranchWritePC(dest); + return [pc]; +} + +:mov^ItCond Hrd0002,Hrm0305 is TMode=1 & ItCond & op8=0x46 & Hrm0305 & hrm0305=7 & Hrd0002 & hrd0002=6 & h1=1 [ LRset=1; TMode=1; globalset(inst_next,LRset); globalset(inst_next,TMode); ] +{ + build ItCond; + Hrd0002 = Hrm0305; +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:mov^thSBIT_ZN^ItCond^".w" Rd0811,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=2 & thSBIT_ZN & sop0003=15; thc1515=0 & Rd0811) & ThumbExpandImm12 +{ + build ItCond; + Rd0811 = ThumbExpandImm12; + resflags(Rd0811); + build thSBIT_ZN; +} + +:movw^ItCond Rd0811,Immed16 is TMode=1 & ItCond & (op11=0x1e & thc0909=1 & sop0508=2 & thc0404=0; thc1515=0 & Rd0811) & Immed16 +{ + build ItCond; + Rd0811 = zext(Immed16); + resflags(Rd0811); +} + +:mov^thSBIT_ZN^ItCond^".w" Rd0811,Rm0003 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=2 & thSBIT_ZN & sop0003=15; op12=0 & Rd0811 & thc0407=0 & Rm0003 +{ + build ItCond; + Rd0811 = Rm0003; + resflags(Rd0811); + build thSBIT_ZN; +} + +:movt^ItCond Rd0811,Immed16 is TMode=1 & ItCond & (op11=0x1e & thc0909=1 & sop0508=6 & thc0404=0; thc1515=0 & Rd0811) & Immed16 +{ + build ItCond; + Rd0811 = (zext(Immed16) << 16) | (Rd0811 & 0xffff); +} + + +:mrc^ItCond thcpn,thc0507,Rt1215,thCRn,thCRm,thopcode2 is TMode=1 & ItCond & op8=0xee & thc0507 & thc0404=1 & thCRn; Rt1215 & thcpn & thopcode2 & thc0404=1 & thCRm +{ + build ItCond; + t_cpn:4 = thcpn; + t_op1:4 = thc0507; + t_op2:4 = thopcode2; + Rt1215 = coprocessor_movefromRt(t_cpn,t_op1,t_op2,thCRn,thCRm); +} + +:mrc2^ItCond thcpn,thc0507,Rt1215,thCRn,thCRm,thopcode2 is TMode=1 & ItCond & op8=0xfe & thc0507 & thc0404=1 & thCRn; Rt1215 & thcpn & thopcode2 & thc0404=1 & thCRm +{ + build ItCond; + t_cpn:4 = thcpn; + t_op1:4 = thc0507; + t_op2:4 = thopcode2; + Rt1215 = coprocessor_movefromRt(t_cpn,t_op1,t_op2,thCRn,thCRm); +} + +:mrrc^ItCond thcpn,thopcode1,Rt1215,Rn0003,thCRm is TMode=1 & ItCond & op4=0xec5 & Rn0003; Rt1215 & thcpn & thopcode1 & thCRm +{ + build ItCond; + t_cpn:4 = thcpn; + t_op:4 = thopcode1; + Rt1215 = coprocessor_movefromRt(t_cpn,t_op,thCRm); + Rn0003 = coprocessor_movefromRt2(t_cpn,t_op,thCRm); +} + +:mrrc2^ItCond thcpn,thopcode1,Rt1215,Rn0003,thCRm is TMode=1 & ItCond & op4=0xfc5 & Rn0003; Rt1215 & thcpn & thopcode1 & thCRm +{ + build ItCond; + t_cpn:4 = thcpn; + t_op:4 = thopcode1; + Rt1215 = coprocessor_movefromRt(t_cpn,t_op,thCRm); + Rn0003 = coprocessor_movefromRt2(t_cpn,t_op,thCRm); +} + +macro readAPSR(r) { +# TODO: GE bits have not been included + r = r | zext( (NG<<4) | (ZR<<3) | (CY<<2) | (OV<<1) | (Q) ) << 27; +} + +macro writeAPSR(r) { +# TODO: GE bits have not been included + local tmp = r >> 27 & 0x1f; + Q = ((tmp ) & 0x1) != 0; + OV = ((tmp >> 1) & 0x1) != 0; + CY = ((tmp >> 2) & 0x1) != 0; + ZR = ((tmp >> 3) & 0x1) != 0; + NG = ((tmp >> 4) & 0x1) != 0; +} + +@if defined(VERSION_7M) + +define pcodeop getMainStackPointer; +define pcodeop getProcessStackPointer; +define pcodeop getBasePriority; +define pcodeop getCurrentExceptionNumber; + +mrsipsr: "i" is thc0000=1 & Rd0811 { + b:1 = isCurrentModePrivileged(); + if (!b) goto ; + ipsr:4 = getCurrentExceptionNumber(); + Rd0811 = Rd0811 | (ipsr & 0x1ff); + +} +mrsipsr: is thc0000=0 { } +mrsepsr: "e" is thc0101=1 { } +mrsepsr: is thc0101=0 { } +mrsapsr: is thc0202=1 { } +mrsapsr: "a" is thc0202=0 & Rd0811 { readAPSR(Rd0811); } + +mrspsr: mrsipsr^mrsepsr^mrsapsr^"psr" is mrsipsr & mrsepsr & mrsapsr & Rd0811 { + Rd0811 = 0; + build mrsapsr; + build mrsipsr; +} +mrspsr: "xpsr" is sysm02=3 & mrsipsr & mrsepsr & mrsapsr & Rd0811 { + Rd0811 = 0; + build mrsapsr; + build mrsipsr; +} + +:mrs^ItCond Rd0811,mrspsr is TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm37=0 & mrspsr +{ + build ItCond; + build mrspsr; +} + +msp: "msp" is epsilon {} + +:mrs^ItCond Rd0811,msp is TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm=8 & msp +{ + build ItCond; + Rd0811 = getMainStackPointer(); +} + +psp: "psp" is epsilon {} + +:mrs^ItCond Rd0811,psp is TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm=9 & psp +{ + build ItCond; + Rd0811 = getProcessStackPointer(); +} + +primask: "primask" is epsilon {} + +:mrs^ItCond Rd0811,primask is TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm=16 & primask +{ + build ItCond; + Rd0811 = 0; + b:1 = isCurrentModePrivileged(); + if (!b) goto inst_next; + Rd0811 = isIRQinterruptsEnabled(); # should reflect primask register/bit +} + +basepri: "basepri" is epsilon {} + +:mrs^ItCond Rd0811,basepri is TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm=17 & basepri +{ + build ItCond; + Rd0811 = 0; + b:1 = isCurrentModePrivileged(); + if (!b) goto inst_next; + Rd0811 = getBasePriority(); +} + +basepri_max: "basepri_max" is epsilon {} + +:mrs^ItCond Rd0811,basepri_max is TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm=18 & basepri_max +{ + build ItCond; + Rd0811 = 0; + b:1 = isCurrentModePrivileged(); + if (!b) goto inst_next; + Rd0811 = getBasePriority(); +} + +faultmask: "faultmask" is epsilon {} + +:mrs^ItCond Rd0811,faultmask is TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm=19 & faultmask +{ + build ItCond; + Rd0811 = 0; + b:1 = isCurrentModePrivileged(); + if (!b) goto inst_next; + Rd0811 = isFIQinterruptsEnabled(); # should reflect faultmask register/bit +} + +define pcodeop isThreadModePrivileged; +define pcodeop isUsingMainStack; + +control: "control" is epsilon {} + +:mrs^ItCond Rd0811,control is TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm=20 & control +{ + build ItCond; + notPrivileged:1 = isThreadModePrivileged() != 1:1; + altStackMode:1 = isUsingMainStack() != 1:1; + Rd0811 = zext((altStackMode << 1) | notPrivileged); +} + +@endif + +:mrs^ItCond Rd0811,cpsr is TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm=0 & cpsr +{ + build ItCond; + tmp:4 = 0; + readAPSR(tmp); + Rd0811 = tmp; +} + +:mrs^ItCond Rd0811,spsr is TMode=1 & ItCond & op0=0xf3ff; op12=0x8 & Rd0811 & sysm=0 & spsr +{ + build ItCond; + Rd0811 = spsr; +} + + +@if defined(VERSION_7M) + +msripsr: "i" is thc0000=1 { } +msripsr: is thc0000=0 { } +msrepsr: "e" is thc0101=1 { } +msrepsr: is thc0101=0 { } +msrapsr: is thc0202=1 { } +msrapsr: "a" is thc0202=0 & Rn0003 { + cpsr = cpsr | (Rn0003 & 0xf8000000); + writeAPSR(cpsr); +} + +msrpsr: msripsr^msrepsr^msrapsr^"psr" is msripsr & msrepsr & msrapsr { + build msrapsr; +} +msrpsr: "xpsr" is sysm02=3 & msrapsr { + build msrapsr; +} + +:msr^ItCond msrpsr,Rn0003 is TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm37=0 & msrpsr +{ + build ItCond; + build msrpsr; +} + +define pcodeop setMainStackPointer; +define pcodeop setProcessStackPointer; +define pcodeop setBasePriority; + +:msr^ItCond msp,Rn0003 is TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm=8 & msp +{ + build ItCond; + b:1 = isCurrentModePrivileged(); + if (!b) goto inst_next; + setMainStackPointer(Rn0003); +} + +:msr^ItCond psp,Rn0003 is TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm=9 & psp +{ + build ItCond; + b:1 = isCurrentModePrivileged(); + if (!b) goto inst_next; + setProcessStackPointer(Rn0003); +} + +:msr^ItCond primask,Rn0003 is TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm=16 & primask +{ + build ItCond; + b:1 = isCurrentModePrivileged(); + if (!b) goto inst_next; + + IRQsDisabled:1 = (Rn0003 & 1) == 1; + if (IRQsDisabled) goto ; + enableIRQinterrupts(); + goto inst_next; + + disableIRQinterrupts(); +} + +:msr^ItCond basepri,Rn0003 is TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm=17 & basepri +{ + build ItCond; + b:1 = isCurrentModePrivileged(); + if (!b) goto inst_next; + setBasePriority(Rn0003); +} + +:msr^ItCond basepri_max,Rn0003 is TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm=18 & basepri_max +{ + build ItCond; + b:1 = isCurrentModePrivileged(); + if (!b) goto inst_next; + if (Rn0003 == 0) goto inst_next; +# TODO: does the following compare need to be signed?? + cur:4 = getBasePriority(); + if (cur != 0 && Rn0003 >= cur) goto inst_next; + setBasePriority(Rn0003); +} + +:msr^ItCond faultmask,Rn0003 is TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm=19 & faultmask +{ + build ItCond; + b:1 = isCurrentModePrivileged(); + if (!b) goto inst_next; + + FIQsDisabled:1 = (Rn0003 & 1) == 1; + if (FIQsDisabled) goto ; + enableFIQinterrupts(); + goto inst_next; + + disableFIQinterrupts(); +} + +define pcodeop setStackMode; + +:msr^ItCond control,Rn0003 is TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm=20 & control +{ + build ItCond; + b:1 = isCurrentModePrivileged(); + if (!b) goto inst_next; + privileged:1 = (Rn0003 & 1) == 0; + setThreadModePrivileged(privileged); + + b = isThreadMode(); + if (!b) goto inst_next; + stackMode:1 = (Rn0003 & 2) == 0; + setStackMode(stackMode); +} + +@endif + +thpsrmask: is th_psrmask=0 { export 0:4; } +thpsrmask: "_c" is th_psrmask=1 { export 0xff:4; } +thpsrmask: "_x" is th_psrmask=2 { export 0xff00:4; } +thpsrmask: "_cx" is th_psrmask=3 { export 0xffff:4; } +thpsrmask: "_s" is th_psrmask=4 { export 0xff0000:4; } +thpsrmask: "_cs" is th_psrmask=5 { export 0xff00ff:4; } +thpsrmask: "_xs" is th_psrmask=6 { export 0xffff00:4; } +thpsrmask: "_cxs" is th_psrmask=7 { export 0xffffff:4; } +thpsrmask: "_f" is th_psrmask=8 { export 0xff000000:4; } +thpsrmask: "_cf" is th_psrmask=9 { export 0xff0000ff:4; } +thpsrmask: "_xf" is th_psrmask=10 { export 0xff00ff00:4; } +thpsrmask: "_cxf" is th_psrmask=11 { export 0xff00ffff:4; } +thpsrmask: "_sf" is th_psrmask=12 { export 0xffff0000:4; } +thpsrmask: "_csf" is th_psrmask=13 { export 0xffff00ff:4; } +thpsrmask: "_xsf" is th_psrmask=14 { export 0xffffff00:4; } +thpsrmask: "_cxsf" is th_psrmask=15 { export 0xffffffff:4; } + +thcpsrmask: cpsr^thpsrmask is thpsrmask & cpsr { export thpsrmask; } + +:msr^ItCond thcpsrmask,Rn0003 is TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & thcpsrmask & thc0007=0 +{ + build ItCond; + build thcpsrmask; + cpsr = (cpsr& ~thcpsrmask) | (Rn0003 & thcpsrmask); + writeAPSR(cpsr); +} + +thspsrmask: spsr^thpsrmask is thpsrmask & spsr { export thpsrmask; } + +:msr^ItCond thspsrmask,Rn0003 is TMode=1 & ItCond & op4=0xf39 & Rn0003; op12=0x8 & thspsrmask & thc0007=0 +{ + build ItCond; + build thspsrmask; + spsr = (spsr& ~thspsrmask) | (Rn0003 & thspsrmask); +} + +:mvn^thSBIT_ZN^ItCond Rd0811,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=3 & thSBIT_ZN & thc0003=15; thc1515=0 & Rd0811) & ThumbExpandImm12 +{ + build ItCond; + Rd0811 = ~ThumbExpandImm12; + resflags(Rd0811); + build thSBIT_ZN; +} + +:mvn^thSBIT_ZN^ItCond^".w" Rd0811,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=3 & thSBIT_ZN & thc0003=15; thc1515=0 & Rd0811 & thshift2 +{ + build ItCond; + Rd0811 = ~thshift2; + resflags(Rd0811); + build thSBIT_ZN; +} + +@endif # VERSION_6T2 || VERSION_7 + +:mul^CheckInIT_ZN^ItCond Rd0002,Rm0305 is TMode=1 & ItCond & op6=0x10d & Rm0305 & Rd0002 & CheckInIT_ZN +{ + build ItCond; + Rd0002 = Rm0305 * Rd0002; + resflags(Rd0002); + build CheckInIT_ZN; +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:mla^ItCond Rd0811,Rn0003,Rm0003,Ra1215 is TMode=1 & ItCond & op4=0xfb0 & Rn0003; Ra1215 & Rd0811 & sop0407=0 & Rm0003 +{ + build ItCond; + Rd0811 = Rn0003 * Rm0003 + Ra1215; +} + +:mls^ItCond Rd0811,Rn0003,Rm0003,Ra1215 is TMode=1 & ItCond & op4=0xfb0 & Rn0003; Ra1215 & Rd0811 & sop0407=1 & Rm0003 +{ + build ItCond; + Rd0811 = Ra1215- Rn0003 * Rm0003; +} + +:mul^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfb0 & Rn0003; op12=15 & Rd0811 & sop0407=0 & Rm0003 +{ + build ItCond; + Rd0811 = Rn0003 * Rm0003; +} + +@endif # VERSION_6T2 || VERSION_7 + +:mvn^CheckInIT_ZN^ItCond Rd0002,Rm0305 is TMode=1 & ItCond & op6=0x10f & Rm0305 & Rd0002 & CheckInIT_ZN +{ + build ItCond; + Rd0002 = ~Rm0305; + resflags(Rd0002); + build CheckInIT_ZN; +} + +:nop^ItCond is TMode=1 & ItCond & op0=0xbf00 +{ +} + +:nop^ItCond^".w" is TMode=1 & ItCond & op0=0xf3af; op0=0x8000 +{ +} + +:nop is op0=0x46c0 # This is just like a mov r0 r0 +{ +} + +:orr^CheckInIT_ZN^ItCond Rd0002,Rm0305 is TMode=1 & ItCond & op6=0x10c & Rm0305 & Rd0002 & CheckInIT_ZN +{ + build ItCond; + Rd0002 = Rd0002 | Rm0305; + resflags(Rd0002); + build CheckInIT_ZN; +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:orn^thSBIT_CZNO^ItCond Rd0811,Rn0003,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=3 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811) & ThumbExpandImm12 +{ + build ItCond; + Rd0811 = Rn0003 | ~(ThumbExpandImm12); + th_logicflags(); + resflags(Rd0811); + build thSBIT_CZNO; +} + +:orn^thSBIT_CZNO^ItCond^".w" Rd0811,Rn0003,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=3 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811 & thshift2 +{ + build ItCond; + Rd0811 = Rn0003 | ~(thshift2); + th_logicflags(); + resflags(Rd0811); + build thSBIT_CZNO; +} + +:orr^thSBIT_CZNO^ItCond Rd0811,Rn0003,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=2 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811) & ThumbExpandImm12 +{ + build ItCond; + Rd0811 = Rn0003 | ThumbExpandImm12; + th_logicflags(); + resflags(Rd0811); + build thSBIT_CZNO; +} + +:orr^thSBIT_CZNO^ItCond^".w" Rd0811,Rn0003,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=2 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811 & thshift2 +{ + build ItCond; + Rd0811 = Rn0003 | thshift2; + th_logicflags(); + resflags(Rd0811); + build thSBIT_CZNO; +} + +:pkhbt^ItCond^".w" Rd0811,Rn0003,thshift2 is TMode=1 & ItCond & op4=0xeac & Rn0003; thc1515=0 & Rd0811 & thc0505=0 & thc0404=0 & thshift2 +{ + build ItCond; + Rd0811 = (Rn0003 & 0x0000ffff) | (thshift2 & 0xffff0000); + th_logicflags(); + resflags(Rd0811); +} + +:pkhtb^ItCond^".w" Rd0811,Rn0003,thshift2 is TMode=1 & ItCond & op4=0xeac & Rn0003; thc1515=0 & Rd0811 & thc0505=1 & thc0404=0 & thshift2 +{ + build ItCond; + Rd0811 = (Rn0003 & 0xffff0000) | (thshift2 & 0x0000ffff); + th_logicflags(); + resflags(Rd0811); +} + +:pld^ItCond Rn0003,"#"^offset12 is TMode=1 & ItCond & op6=0x3e2 & thwbit=0 & thc0404=1 & Rn0003; op12=0xf & offset12 +{ + build ItCond; + addr:4 = Rn0003 + offset12; + HintPreloadData(addr); +} + + +:pld^ItCond Rn0003,"#-"^immed8 is TMode=1 & ItCond & op6=0x3e0 & thwbit=0 & thc0404=1 & Rn0003; op8=0xfc & immed8 +{ + build ItCond; + addr:4 = Rn0003 - immed8; + HintPreloadData(addr); +} + +:pld^ItCond PcrelOffset12 is TMode=1 & ItCond & (op8=0xf8 & thc0506=0 & thc0004=0x1f; thc1215=0xf) & PcrelOffset12 +{ + build ItCond; + HintPreloadData(PcrelOffset12); +} + +:pld^ItCond Rn0003,Rm0003"lsl #"^thc0405 is TMode=1 & ItCond & op6=0x3e0 & thwbit=0 & thc0404=1 & Rn0003; op8=0xf0 & thc0607=0 & thc0405 & Rm0003 +{ + build ItCond; + addr:4 = Rn0003 + (Rm0003 << thc0405); + HintPreloadData(addr); +} + +# pld.w moved above ldrh to avoid conflicts + +#pli moved above ldrsb + + +@endif # VERSION_6T2 || VERSION_7 + +# +# Removed the masking of the stack pointer on push and pop to ignore the lower 2 bits. +# This isn't really needed for modeling. +# NOTE: It may need to be put back in to model correctly for nasty stack shenanigans. +# +:pop^ItCond ldbrace is TMode=1 & ItCond & op9=0x5e & R=0 & ldbrace +{ + build ItCond; +# mult_addr = sp & 0xfffffffc; + mult_addr = sp; + build ldbrace; + sp = mult_addr; +} + +:pop^ItCond pclbrace is TMode=1 & ItCond & op9=0x5e & R=1 & pclbrace +{ + build ItCond; +# mult_addr = sp & 0xfffffffc; + mult_addr = sp; + build pclbrace; + sp = mult_addr; + LoadWritePC(pc); + return [pc]; +} + +:pop^ItCond thldrlist_inc is TMode=1 & ItCond & op0=0xe8bd; thldrlist_inc +{ + build ItCond; +# mult_addr = sp & 0xfffffffc; + mult_addr = sp; + build thldrlist_inc; + sp = mult_addr; +} + +:pop^ItCond thldrlist_inc is TMode=1 & ItCond & op0=0xe8bd; thldrlist_inc & thc1515=1 +{ + build ItCond; +# mult_addr = sp & 0xfffffffc; + mult_addr = sp; + build thldrlist_inc; + sp = mult_addr; + LoadWritePC(pc); + return [pc]; +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:pop^ItCond^".w" thldrlist_inc is TMode=1 & ItCond & op0=0xe8bd; thc1515=0 & thc1313=0 & thldrlist_inc +{ + build ItCond; + mult_addr = sp; + build thldrlist_inc; + sp = mult_addr; +} + +:pop^ItCond^".w" Rt1215 is TMode=1 & ItCond & op0=0xf85d; Rt1215 & offset12=0xb04 +{ + build ItCond; + Rt1215 = *sp; + sp=sp+4; +} + +:pop^ItCond^".w" thldrlist_inc is TMode=1 & ItCond & op0=0xe8bd; thc1515=1 & thc1313=0 & thldrlist_inc +{ + build ItCond; + mult_addr = sp; + build thldrlist_inc; + sp = mult_addr; + LoadWritePC(pc); + return [pc]; +} + +:pop^ItCond^".w" Rt1215 is TMode=1 & ItCond & op0=0xf85d; Rt1215 & op12=15 & offset12=0xb04 +{ + build ItCond; + dest:4 = *sp; + sp=sp+4; + LoadWritePC(dest); + return [pc]; +} + +:push^ItCond^".w" thstrlist_dec is TMode=1 & ItCond & op0=0xe8ad; thc1515=0 & thc1313=0 & thstrlist_dec +{ + build ItCond; + mult_addr = sp-4; + build thstrlist_dec; + sp = mult_addr + 4; +} + +:push^ItCond^".w" Rt1215 is TMode=1 & ItCond & op0=0xf84d; Rt1215 & offset12=0xd04 +{ + build ItCond; + sp=sp-4; + *sp = Rt1215; +} + +@endif # VERSION_6T2 || VERSION_7 + +:push^ItCond psbrace is TMode=1 & ItCond & op9=0x5a & R=0 & psbrace +{ + build ItCond; +# mult_addr = sp & 0xfffffffc; + mult_addr = sp; + build psbrace; + sp = mult_addr; +} + +:push^ItCond pcpbrace is TMode=1 & ItCond & op9=0x5a & R=1 & pcpbrace +{ + build ItCond; +# mult_addr = sp & 0xfffffffc; + mult_addr = sp; + build pcpbrace; + sp = mult_addr; +} + +:push^ItCond thstrlist_dec is TMode=1 & ItCond & op0=0xe92d; thstrlist_dec +{ + build ItCond; +# mult_addr = sp & 0xfffffffc; + mult_addr = sp-4; + build thstrlist_dec; + sp = mult_addr+4; +} + +@if defined(VERSION_5E) + +:qadd^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa8 & Rn0003; op12=0xf & Rd0811 & thc0407=0x8 & Rm0003 +{ + build ItCond; + local sum1 = Rm0003 + Rn0003; + sum1 = SignedSaturate(sum1,32:2); + Q = SignedDoesSaturate(sum1,32:2); + Rd0811 = sum1; +} + +@endif # VERSION_5E + +@if defined(VERSION_6) + +:qadd16^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa9 & Rn0003; op12=0xf & Rd0811 & thc0407=0x1 & Rm0003 +{ + build ItCond; + local lRn = Rn0003 & 0xffff; + local lRm = Rm0003 & 0xffff; + local uRn = (Rn0003) & 0xffff; + local uRm = (Rm0003 >> 16) & 0xffff; + sum1:2 = lRn:2 + lRm:2; + sum1 = SignedSaturate(sum1,16:2); + sum2:2 = uRn:2 + uRm:2; + sum2 = SignedSaturate(sum2,16:2); + Rd0811 = (zext(sum2) << 16) | zext(sum1); +} + +:qadd8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa8 & Rn0003; op12=0xf & Rd0811 & thc0407=0x1 & Rm0003 +{ + build ItCond; + local rn1 = Rn0003 & 0xff; + local rm1 = Rm0003 & 0xff; + local rn2 = (Rn0003 >> 8) & 0xff; + local rm2 = (Rm0003 >> 8) & 0xff; + local rn3 = (Rn0003 >> 16) & 0xff; + local rm3 = (Rm0003 >> 16) & 0xff; + local rn4 = (Rn0003 >> 24) & 0xff; + local rm4 = (Rm0003 >> 24) & 0xff; + sum1:1 = rn1:1 + rm1:1; + sum1 = SignedSaturate(sum1,8:2); + sum2:1 = rn2:1 + rm2:1; + sum2 = SignedSaturate(sum2,8:2); + sum3:1 = rn3:1 + rm3:1; + sum3 = SignedSaturate(sum3,8:2); + sum4:1 = rn4:1 + rm4:1; + sum4 = SignedSaturate(sum4,8:2); + Rd0811 = (zext(sum4) << 24) | (zext(sum3) << 16) | (zext(sum2) << 8) | zext(sum1); +} + +# qaddsubx +:qasx^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfaa & Rn0003; op12=0xf & Rd0811 & thc0407=0x1 & Rm0003 +{ + build ItCond; + local lRn = Rn0003 & 0xffff; + local lRm = Rm0003 & 0xffff; + local uRn = (Rn0003 >> 16) & 0xffff; + local uRm = (Rm0003 >> 16) & 0xffff; + sum1:2 = lRn:2 - lRm:2; + sum1 = SignedSaturate(sum1,16:2); + sum2:2 = uRn:2 + uRm:2; + sum2 = SignedSaturate(sum2,16:2); + Rd0811 = (zext(sum2) << 16) | zext(sum1); +} + +@endif # VERSION_6 + +@if defined(VERSION_5E) + +:qdadd^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa8 & Rn0003; op12=0xf & Rd0811 & thc0407=0x9 & Rm0003 +{ + build ItCond; + tmp:4 = Rn0003 * 2; + tmp = SignedSaturate(tmp,32:2); + Q = SignedDoesSaturate(tmp,32:2); + tmp = tmp + Rm0003; + tmp = SignedSaturate(tmp,32:2); + Q = Q | SignedDoesSaturate(tmp,32:2); + Rd0811 = tmp; +} + +:qdsub^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa8 & Rn0003; op12=0xf & Rd0811 & thc0407=0xb & Rm0003 +{ + build ItCond; + tmp:4 = Rn0003 * 2; + tmp = SignedSaturate(tmp); + Q = SignedDoesSaturate(tmp,32:2); + tmp = Rm0003 - tmp; + tmp = SignedSaturate(tmp,32:2); + Q = Q | SignedDoesSaturate(tmp,32:2); + Rd0811 = tmp; +} + +@endif # VERSION_5E + +@if defined(VERSION_6) + +# qsubaddx +:qsax^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfae & Rn0003; op12=0xf & Rd0811 & thc0407=0x1 & Rm0003 +{ + build ItCond; + local lRn = Rn0003 & 0xffff; + local lRm = Rm0003 & 0xffff; + local uRn = (Rn0003 >> 16) & 0xffff; + local uRm = (Rm0003 >> 16) & 0xffff; + sum1:2 = lRn:2 + lRm:2; + sum1 = SignedSaturate(sum1,16:2); + sum2:2 = uRn:2 - uRm:2; + sum2 = SignedSaturate(sum2,16:2); + Rd0811 = (zext(sum2) << 16) | zext(sum1); +} + +@endif # VERSION_6 + +@if defined(VERSION_5E) + +:qsub^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa8 & Rn0003; op12=0xf & Rd0811 & thc0407=0xa & Rm0003 +{ + build ItCond; + tmp:4 = Rm0003 - Rn0003; + tmp = SignedSaturate(tmp,32:2); + Q = SignedDoesSaturate(tmp,32:2); + Rd0811 = tmp; +} + +@endif # VERSION_5E + +@if defined(VERSION_6) + +:qsub16^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfad & Rn0003; op12=0xf & Rd0811 & thc0407=0x1 & Rm0003 +{ + build ItCond; + local lRn = Rn0003 & 0xffff; + local lRm = Rm0003 & 0xffff; + local uRn = (Rn0003 >> 16) & 0xffff; + local uRm = (Rm0003 >> 16) & 0xffff; + sum1:2 = lRn:2 - lRm:2; + sum1 = SignedSaturate(sum1,16:2); + sum2:2 = uRn:2 - uRm:2; + sum2 = SignedSaturate(sum2,16:2); + Rd0811 = (zext(sum2) << 16) | zext(sum1); +} + +:qsub8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfac & Rn0003; op12=0xf & Rd0811 & thc0407=0x1 & Rm0003 +{ + build ItCond; + local rn1 = Rn0003 & 0xff; + local rm1 = Rm0003 & 0xff; + local rn2 = (Rn0003 >> 8) & 0xff; + local rm2 = (Rm0003 >> 8) & 0xff; + local rn3 = (Rn0003 >> 16) & 0xff; + local rm3 = (Rm0003 >> 16) & 0xff; + local rn4 = (Rn0003 >> 24) & 0xff; + local rm4 = (Rm0003 >> 24) & 0xff; + sum1:1 = rn1:1 - rm1:1; + sum1 = SignedSaturate(sum1,8:2); + sum2:1 = rn2:1 - rm2:1; + sum2 = SignedSaturate(sum2,8:2); + sum3:1 = rn3:1 - rm3:1; + sum3 = SignedSaturate(sum3,8:2); + sum4:1 = rn4:1 - rm4:1; + sum4 = SignedSaturate(sum4,8:2); + Rd0811 = (zext(sum4) << 24) | (zext(sum3) << 16) | (zext(sum2) << 8) | zext(sum1); +} + +@endif # VERSION_6 + +@if defined(THUMB_2) + +# WARNING Rm0003 on the first 2 bytes must be the same value as Rm0003 on the last bytes! +# but there is no easy way to check this now... +:rev^ItCond Rd0811,Rm0003 is TMode=1 & ItCond & op4=0xfa9; op6=0x2e8 & Rd0811 & Rm0003 +{ + build ItCond; + local tmp1 = Rm0003 & 0xff; + local tmp2 = (Rm0003 >> 8) & 0xff; + local tmp3 = (Rm0003 >> 16) & 0xff; + local tmp4 = (Rm0003 >> 24) & 0xff; + Rd0811 = (tmp1 << 24) | (tmp2 << 16) | (tmp3 << 8) | tmp4; +} + +@endif # THUMB_2 + +:rsb^CheckInIT_CZNO^ItCond Rd0002,Rm0305 is TMode=1 & ItCond & op6=0x109 & Rm0305 & Rd0002 & CheckInIT_CZNO +{ + build ItCond; + th_subflags0(Rm0305); + Rd0002 = 0-Rm0305; + resflags(Rd0002); + build CheckInIT_CZNO; +} + +@if defined(VERSION_6) + +:rev^ItCond Rd0002,Rm0305 is TMode=1 & ItCond & op6=0x2e8 & Rd0002 & Rm0305 +{ + build ItCond; + local tmp1 = Rm0305 & 0xff; + local tmp2 = (Rm0305 >> 8) & 0xff; + local tmp3 = (Rm0305 >> 16) & 0xff; + local tmp4 = (Rm0305 >> 24) & 0xff; + Rd0002 = (tmp1 << 24) | (tmp2 << 16) | (tmp3 << 8) | tmp4; +} + +:rev16^ItCond Rd0002,Rm0305 is TMode=1 & ItCond & op6=0x2e9 & Rd0002 & Rm0305 +{ + build ItCond; + local tmp1 = Rm0305 & 0xff; + local tmp2 = (Rm0305 >> 8) & 0xff; + local tmp3 = (Rm0305 >> 16) & 0xff; + local tmp4 = (Rm0305 >> 24) & 0xff; + Rd0002 = (tmp3 << 24) | (tmp4 << 16) | (tmp1 << 8) | tmp2; +} + +:revsh^ItCond Rd0002,Rm0305 is TMode=1 & ItCond & op6=0x2eb & Rd0002 & Rm0305 +{ + build ItCond; + local tmp1 = Rm0305 & 0xff; + local tmp2 = (Rm0305 >> 8) & 0xff; + local result = (tmp1 << 8) | tmp2; + Rd0002 = sext(result:2); +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +macro BitReverse(val) { + tval:1 = val; + result:1 = 0; + result = (result << 1) | (tval & 1); + tval = tval >> 1; + result = (result << 1) | (tval & 1); + tval = tval >> 1; + result = (result << 1) | (tval & 1); + tval = tval >> 1; + result = (result << 1) | (tval & 1); + tval = tval >> 1; + result = (result << 1) | (tval & 1); + tval = tval >> 1; + result = (result << 1) | (tval & 1); + tval = tval >> 1; + result = (result << 1) | (tval & 1); + tval = tval >> 1; + result = (result << 1) | (tval & 1); + tval = tval >> 1; + val = result; +} + +:rbit^ItCond Rd0811, Rm0003 is TMode=1 & ItCond & op4=0xfa9 & Rm0003; op12=0xf & Rd0811 & thc0407=0xa & Rn0003 +{ + build ItCond; + t:4 = Rm0003 & 0xff; + b1:1 = t:1; + t = (Rm0003 >> 8) & 0xff; + b2:1 = t:1; + t = (Rm0003 >> 16) & 0xff; + b3:1 = t:1; + t = (Rm0003 >> 24) & 0xff; + b4:1 = t:1; + BitReverse(b1); + BitReverse(b2); + BitReverse(b3); + BitReverse(b4); + Rd0811 = (zext(b1) << 24) | (zext(b2) << 16) | (zext(b3) << 8) | zext(b4); +} + +:rev^ItCond^".w" Rd0811, Rm0003 is TMode=1 & ItCond & op4=0xfa9 & Rm0003; op12=0xf & Rd0811 & thc0407=8 & Rn0003 +{ + build ItCond; + local tmp1 = Rm0003 & 0xff; + local tmp2 = (Rm0003 >> 8) & 0xff; + local tmp3 = (Rm0003 >> 16) & 0xff; + local tmp4 = (Rm0003 >> 24) & 0xff; + Rd0811 = (tmp1 << 24) | (tmp2 << 16) | (tmp3 << 8) | tmp4; +} + +:rev16^ItCond^".w" Rd0811, Rm0003 is TMode=1 & ItCond & op4=0xfa9 & Rm0003; op12=0xf & Rd0811 & thc0407=9 & Rn0003 +{ + build ItCond; + local tmp1 = Rm0003 & 0xff; + local tmp2 = (Rm0003 >> 8) & 0xff; + local tmp3 = (Rm0003 >> 16) & 0xff; + local tmp4 = (Rm0003 >> 24) & 0xff; + Rd0811 = (tmp3 << 24) | (tmp4 << 16) | (tmp1 << 8) | tmp2; +} + +:revsh^ItCond^".w" Rd0811, Rm0003 is TMode=1 & ItCond & op4=0xfa9 & Rm0003; op12=0xf & Rd0811 & thc0407=0xb & Rn0003 +{ + build ItCond; + local tmp1 = Rm0003 & 0xff; + local tmp2 = (Rm0003 >> 8) & 0xff; + local result = (tmp1 << 8) | tmp2; + Rd0811 = sext(result:2); +} + +# RFE instructions for Thumb-2 "Encoding T1" and "Encoding T2" on page 1574 +# +:rfedb part2Rd0003 is TMode=1 & part2c0615=0x3a0 & part2c0505=0x0 & part2c0404=0x1 & part2Rd0003 ; op0=0xc000 +{ + # register list is always: pc, cpsr + ptr:4 = part2Rd0003 - 4; + cpsr = *ptr; + ptr = ptr - 4; + dest:4 = *ptr; + BranchWritePC(dest); + return [pc]; +} + +:rfedb part2Rd0003^"!" is TMode=1 & part2c0615=0x3a0 & part2c0505=0x1 & part2c0404=0x1 & part2Rd0003 ; op0=0xc000 +{ + # register list is always: pc, cpsr + ptr:4 = part2Rd0003 - 4; + cpsr = *ptr; + ptr = ptr - 4; + dest:4 = *ptr; + part2Rd0003 = ptr; + BranchWritePC(dest); + return [pc]; +} + +:rfeia part2Rd0003 is TMode=1 & part2c0615=0x3a6 & part2c0505=0x0 & part2c0404=0x1 & part2Rd0003 ; op0=0xc000 +{ + # register list is always: pc, cpsr + ptr:4 = part2Rd0003; + cpsr = *ptr; + ptr = ptr + 4; + dest:4 = *ptr; + BranchWritePC(dest); + return [pc]; +} + +:rfeia part2Rd0003^"!" is TMode=1 & part2c0615=0x3a6 & part2c0505=0x1 & part2c0404=0x1 & part2Rd0003 ; op0=0xc000 +{ + # register list is always: pc, cpsr + ptr:4 = part2Rd0003; + cpsr = *ptr; + ptr = ptr + 4; + dest:4 = *ptr; + part2Rd0003 = ptr + 4; + BranchWritePC(dest); + return [pc]; +} + +@endif # defined(VERSION_6T2) || defined(VERSION_7) + + +:rsb^thSBIT_CZNO^ItCond^".w" Rd0811,Rn0003,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=14 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811) & ThumbExpandImm12 +{ + build ItCond; + th_subflags(ThumbExpandImm12,Rn0003); + Rd0811 = ThumbExpandImm12 - Rn0003; + resflags(Rd0811); + build thSBIT_CZNO; +} + +:rsb^thSBIT_CZNO^ItCond Rd0811,Rn0003,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=14 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811 & thshift2 +{ + build ItCond; + th_subflags(thshift2,Rn0003); + Rd0811 = thshift2 - Rn0003; + resflags(Rd0811); + build thSBIT_CZNO; +} + +@endif # VERSION_6 + +macro th_set_carry_for_ror(result, count) { + local bit = result & 0x80000000; + tmpCY = ((count == 0) && CY) || ((count != 0) && (bit != 0)); +} + +:ror^CheckInIT_CZN^ItCond Rd0002,Rs0305 is TMode=1 & ItCond & op6=0x107 & Rs0305 & Rd0002 & CheckInIT_CZN +{ + build ItCond; + local shift_amount = Rs0305 & 0x1f; + local tmp = (Rd0002 >> shift_amount)|(Rd0002 << (32-shift_amount)); + th_set_carry_for_ror(tmp,Rs0305 & 0xff); + Rd0002 = tmp; + resflags(Rd0002); + build CheckInIT_CZN; +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:ror^thSBIT_CZN^ItCond Rd0811,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=2 & thSBIT_CZN & thc0003=0xf; thc1515=0 & Rd0811 & thc0405=3 & thshift2 +{ + build ItCond; + Rd0811 = thshift2; + tmpCY = shift_carry; + resflags(Rd0811); + build thSBIT_CZN; +} + +:ror^thSBIT_CZN^ItCond^".w" Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op8=0xfa & thc0707=0 & thc0506=3 & thSBIT_CZN & Rn0003; op12=15 & Rd0811 & sop0407=0 & Rm0003 +{ + build ItCond; + local shift_amount = Rm0003 & 0x1f; + local tmp = (Rn0003>>shift_amount)|(Rn0003<<(32-shift_amount)); + th_set_carry_for_ror(tmp,Rm0003 & 0xff); + Rd0811 = tmp; + resflags(Rd0811); + build thSBIT_CZN; +} + +:rrx^thSBIT_CZN^ItCond Rd0811,Rm0003 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=2 & thSBIT_CZN & thc0003=0xf; thc1515=0 & thc1214=0 & Rd0811 & thc0607=0 & thc0405=3 & Rm0003 +{ + build ItCond; + local tmp1=Rm0003&1; + shift_carry=tmp1(0); + local tmp2 = (zext(CY)<<31)|(Rm0003>>1); + Rd0811 = tmp2; + th_logicflags(); + resflags(Rd0811); + build thSBIT_CZN; +} + +@endif # defined(VERSION_6T2) || defined(VERSION_7) + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:sadd16^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa9 & Rn0003; op12=0xf & Rd0811 & thc0407=0x0 & Rm0003 +{ + build ItCond; + local tmpRm0003 = Rm0003; + local tmpRn0003 = Rn0003; + sum1:4 = sext(tmpRn0003[ 0,16]) + sext(tmpRm0003[ 0,16]); + sum2:4 = sext(tmpRn0003[16,16]) + sext(tmpRm0003[16,16]); + Rd0811[ 0,16] = sum1:2; + Rd0811[16,16] = sum2:2; + GE1 = sum1 s>= 0; + GE2 = sum1 s>= 0; + GE3 = sum2 s>= 0; + GE4 = sum2 s>= 0; +} + +:sadd8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa8 & Rn0003; op12=0xf & Rd0811 & thc0407=0x0 & Rm0003 +{ + build ItCond; + local tmpRm0003 = Rm0003; + local tmpRn0003 = Rn0003; + sum1:4 = sext(tmpRn0003[ 0,8]) + sext(tmpRm0003[ 0,8]); + sum2:4 = sext(tmpRn0003[ 8,8]) + sext(tmpRm0003[ 8,8]); + sum3:4 = sext(tmpRn0003[16,8]) + sext(tmpRm0003[16,8]); + sum4:4 = sext(tmpRn0003[24,8]) + sext(tmpRm0003[24,8]); + Rd0811[ 0,8] = sum1:1; + Rd0811[ 8,8] = sum2:1; + Rd0811[16,8] = sum3:1; + Rd0811[24,8] = sum4:1; + GE1 = sum1 s>= 0; + GE2 = sum2 s>= 0; + GE3 = sum3 s>= 0; + GE4 = sum4 s>= 0; +} + +:sasx^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfaa & Rn0003; op12=0xf & Rd0811 & thc0407=0x0 & Rm0003 +{ + build ItCond; + local tmpRm0003 = Rm0003; + local tmpRn0003 = Rn0003; + diff:4 = sext(tmpRn0003[ 0,16]) - sext(tmpRm0003[16,16]); + sum:4 = sext(tmpRn0003[16,16]) + sext(tmpRm0003[ 0,16]); + Rd0811[ 0,16] = diff[ 0,16]; + Rd0811[16,16] = sum[ 0,16]; + GE1 = diff s>= 0; + GE2 = diff s>= 0; + GE3 = sum s>= 0; + GE4 = sum s>= 0; +} + +@endif # defined(VERSION_6T2) || defined(VERSION_7) + +:sbc^CheckInIT_CZNO^ItCond Rd0002,Rm0305 is TMode=1 & ItCond & op6=0x106 & Rm0305 & Rd0002 & CheckInIT_CZNO +{ + build ItCond; + th_sub_with_carry_flags(Rd0002,Rm0305); + Rd0002 = Rd0002 - Rm0305 - zext(!CY); + resflags(Rd0002); + build CheckInIT_CZNO; +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:sbc^thSBIT_CZNO^ItCond Rd0811,Rn0003,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=11 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811) & ThumbExpandImm12 +{ + build ItCond; + build ThumbExpandImm12; + th_sub_with_carry_flags(Rn0003,ThumbExpandImm12); + Rd0811 = Rn0003 - ThumbExpandImm12 - zext(!CY); + resflags(Rd0811); + build thSBIT_CZNO; +} + +:sbc^thSBIT_CZNO^ItCond^".w" Rd0811,Rn0003,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=11 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811 & thshift2 +{ + build ItCond; + build thshift2; + th_sub_with_carry_flags(Rn0003,thshift2); + Rd0811 = Rn0003 - thshift2 - zext(!CY); + resflags(Rd0811); + build thSBIT_CZNO; +} + +:sbfx^ItCond Rd0811,Rn0003,thLsbImm,thWidthMinus1 is TMode=1 & ItCond & op4=0xf34 & Rn0003; thc1515=0 & Rd0811 & thLsbImm & thWidthMinus1 +{ + build ItCond; + build thLsbImm; + build thWidthMinus1; + shift:4 = 31 - (thLsbImm + thWidthMinus1); # thMsbImm represents widthMinus1 + Rd0811 = Rn0003 << shift; + shift = 31 - thWidthMinus1; # msbImm represents widthMinus1 + Rd0811 = Rd0811 s>> shift; +} + +:sdiv^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfb9 & Rn0003; op12=0xf & Rd0811 & thc0407=0xf & Rm0003 +{ + build ItCond; + sdiv(Rd0811, Rn0003, Rm0003); +} + +:sel^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfaa & Rn0003; op12=0xf & Rd0811 & thc0407=0x8 & Rm0003 +{ + build ItCond; + Rd0811[ 0,8] = ((GE1 == 1) * Rn0003[ 0,8]) + ((GE1 == 0) * Rm0003[ 0,8]); + Rd0811[ 8,8] = ((GE2 == 1) * Rn0003[ 8,8]) + ((GE2 == 0) * Rm0003[ 8,8]); + Rd0811[16,8] = ((GE3 == 1) * Rn0003[16,8]) + ((GE3 == 0) * Rm0003[16,8]); + Rd0811[24,8] = ((GE4 == 1) * Rn0003[24,8]) + ((GE4 == 0) * Rm0003[24,8]); +} + +:shadd16^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa9 & Rn0003; op12=0xf & Rd0811 & thc0407=0x2 & Rm0003 +{ + build ItCond; + sum1:4 = sext(Rn0003[ 0,16]) + sext(Rm0003[ 0,16]); + sum2:4 = sext(Rn0003[16,16]) + sext(Rm0003[16,16]); + Rd0811[ 0,16] = sum1[1,16]; + Rd0811[16,16] = sum2[1,16]; +} + +:shadd8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa8 & Rn0003; op12=0xf & Rd0811 & thc0407=0x2 & Rm0003 +{ + build ItCond; + sum1:4 = sext(Rn0003[ 0,8]) + sext(Rm0003[ 0,8]); + sum2:4 = sext(Rn0003[ 8,8]) + sext(Rm0003[ 8,8]); + sum3:4 = sext(Rn0003[16,8]) + sext(Rm0003[16,8]); + sum4:4 = sext(Rn0003[24,8]) + sext(Rm0003[24,8]); + Rd0811[ 0,8] = sum1[1,8]; + Rd0811[ 8,8] = sum2[1,8]; + Rd0811[16,8] = sum3[1,8]; + Rd0811[24,8] = sum4[1,8]; +} + +:shasx^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfaa & Rn0003; op12=0xf & Rd0811 & thc0407=0x2 & Rm0003 +{ + build ItCond; + diff:4 = sext(Rn0003[ 0,16]) - sext(Rm0003[16,16]); + sum:4 = sext(Rn0003[16,16]) + sext(Rm0003[ 0,16]); + Rd0811[ 0,16] = diff[1,16]; + Rd0811[16,16] = sum[1,16]; +} + +:shsax^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfae & Rn0003; op12=0xf & Rd0811 & thc0407=0x2 & Rm0003 +{ + build ItCond; + sum:4 = sext(Rn0003[ 0,16]) + sext(Rm0003[16,16]); + diff:4 = sext(Rn0003[16,16]) - sext(Rm0003[ 0,16]); + Rd0811[ 0,16] = sum[1,16]; + Rd0811[16,16] = diff[1,16]; +} + +:shsub16^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfad & Rn0003; op12=0xf & Rd0811 & thc0407=0x2 & Rm0003 +{ + build ItCond; + diff1:4 = sext(Rn0003[ 0,16]) - sext(Rm0003[ 0,16]); + diff2:4 = sext(Rn0003[16,16]) - sext(Rm0003[16,16]); + Rd0811[ 0,16] = diff1[1,16]; + Rd0811[16,16] = diff2[1,16]; +} + +:shsub8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfac & Rn0003; op12=0xf & Rd0811 & thc0407=0x2 & Rm0003 +{ + build ItCond; + diff1:4 = sext(Rn0003[ 0,8]) - sext(Rm0003[ 0,8]); + diff2:4 = sext(Rn0003[ 8,8]) - sext(Rm0003[ 8,8]); + diff3:4 = sext(Rn0003[16,8]) - sext(Rm0003[16,8]); + diff4:4 = sext(Rn0003[24,8]) - sext(Rm0003[24,8]); + Rd0811[ 0,8] = diff1[1,8]; + Rd0811[ 8,8] = diff2[1,8]; + Rd0811[16,8] = diff3[1,8]; + Rd0811[24,8] = diff4[1,8]; +} + +@endif # defined(VERSION_6T2) || defined(VERSION_7) + +thXBIT: "b" is Rn0003 ; thc0505=0 { local tmpRn0003 = Rn0003; tmp_x:2 = tmpRn0003:2; export tmp_x; } +thXBIT: "t" is Rn0003 ; thc0505=1 { local tmpRn0003 = Rn0003; tmp_x:2 = tmpRn0003(2); export tmp_x; } + +thYBIT: "b" is thc0404=0 & Rm0003 { local tmpRm0003 = Rm0003; tmp_y:2 = tmpRm0003:2; export tmp_y; } +thYBIT: "t" is thc0404=1 & Rm0003 { local tmpRm0003 = Rm0003; tmp_y:2 = tmpRm0003(2); export tmp_y; } + +:smla^thXBIT^thYBIT^ItCond Rd0811,Rn0003,Rm0003,Rt1215 is TMode=1 & ItCond & (op4=0xfb1 & Rn0003; Rt1215 & Rd0811 & thc0607=0 & thYBIT & Rm0003) & thXBIT +{ + build ItCond; + tmp:4 = sext(thXBIT) * sext(thYBIT); + Q = scarry(tmp,Rt1215) || Q; #Q flag is never cleared by this instruction + Rd0811 = tmp + Rt1215; +} + +thdXbot: "" is thc0404=0 & Rm0003 { local tmpRm0003 = Rm0003; tmp:2 = tmpRm0003:2; export tmp; } +thdXbot: "X" is thc0404=1 & Rm0003 { local tmpRm0003 = Rm0003; tmp:2 = tmpRm0003(2); export tmp; } + +thdXtop: "" is thc0404=0 & Rm0003 { local tmpRm0003 = Rm0003; tmp:2 = tmpRm0003(2); export tmp; } +thdXtop: "X" is thc0404=1 & Rm0003 { local tmpRm0003 = Rm0003; tmp:2 = tmpRm0003:2; export tmp; } + +:smlad^thdXbot^ItCond Rd0811,Rn0003,Rm0003,Ra1215 is TMode=1 & ItCond & op4=0xfb2 & Rn0003; Ra1215 & Rd0811 & thc0507=0 & thdXbot & thdXtop & Rm0003 +{ + build ItCond; + local tmpRn0003 = Rn0003; + rnbot:2 = tmpRn0003:2; + rntop:2 = tmpRn0003(2); + tmpbot:4 = sext(rnbot) * sext(thdXbot); + tmptop:4 = sext(rntop) * sext(thdXtop); + tmp:4 = sext(tmpbot) + sext(tmptop); + Q = scarry(tmp,Ra1215) || Q; #Q flag is never cleared by this instruction + Rd0811 = tmp + Ra1215; +} + +:smlald^thdXbot^ItCond Rt1215,Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfbc & Rn0003; Rt1215 & Rd0811 & thc0507=6 & thdXbot & thdXtop & Rm0003 +{ + build ItCond; + local tmpRn0003 = Rn0003; + rnbot:2 = tmpRn0003:2; + rntop:2 = tmpRn0003(2); + tmpbot:4 = sext(rnbot) * sext(thdXbot); + tmptop:4 = sext(rntop) * sext(thdXtop); + accum:8 = (sext(Rd0811) << 32) | zext(Rt1215); + tmp:8 = sext(tmpbot) + sext(tmptop); + accum = tmp + accum; + Rt1215 = accum:4; + Rd0811 = accum(4); +} + +:smlal^ItCond Rt1215,Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfbc & Rn0003; Rt1215 & Rd0811 & sop0407=0 & Rm0003 +{ + build ItCond; + accum:8 = (sext(Rd0811) << 32) | zext(Rt1215); + val:8 = sext(Rn0003) * sext(Rm0003) + accum; + Rt1215 = val(0); + Rd0811 = val(4); +} + +:smlal^thXBIT^thYBIT^ItCond Rt1215,Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & (op4=0xfbc & Rn0003; Rt1215 & Rd0811 & thc0607=2 & thYBIT & Rm0003) & thXBIT +{ + build ItCond; + tmp:4 = sext(thXBIT) * sext(thYBIT); + accum:8 = (zext(Rd0811) << 32) | zext(Rt1215); + val:8 = sext(tmp) + accum; + Rt1215 = val(0); + Rd0811 = val(4); +} + +:smlaw^thYBIT^ItCond Rd0811,Rn0003,Rm0003,Ra1215 is TMode=1 & ItCond & op4=0xfb3 & Rn0003; Ra1215 & Rd0811 & thc0507=0 & thYBIT & Rm0003 +{ + build ItCond; + local tmp:6 = (sext(Rn0003) * sext(thYBIT)); + local addend:6 = sext(Ra1215) << 16; + Q = scarry(tmp,addend) || Q; #this instruction never clears the Q flag + tmp = tmp + addend; + Rd0811 = tmp(2); +} + +:smlsd^thdXbot^ItCond Rd0811,Rn0003,Rm0003,Ra1215 is TMode=1 & ItCond & op4=0xfb4 & Rn0003; Ra1215 & Rd0811 & thc0507=0 & thdXbot & thdXtop & Rm0003 +{ + build ItCond; + local tmpRn0003 = Rn0003; + local rnbot:2 = tmpRn0003:2; + local rntop:2 = tmpRn0003(2); + local prod1:4 = sext(rnbot) * sext(thdXbot); + local prod2:4 = sext(rntop) * sext(thdXtop); + local diff = prod1 - prod2; + Q = scarry(diff,Ra1215) || Q; #instruction never clears Q flag + Rd0811 = diff + Ra1215; +} + +:smlsld^thdXbot^ItCond Rt1215,Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfbd & Rn0003; Rt1215 & Rd0811 & thc0507=6 & thdXbot & thdXtop & Rm0003 +{ + build ItCond; + local tmpRn0003 = Rn0003; + local rnbot:2 = tmpRn0003:2; + local rntop:2 = tmpRn0003(2); + local tmpbot:4 = sext(rnbot) * sext(thdXbot); + local tmptop:4 = sext(rntop) * sext(thdXtop); + local accum:8 = (sext(Rd0811) << 32) | zext(Rt1215); + local tmp:8 = sext(tmpbot) - sext(tmptop); + accum = tmp + accum; + Rt1215 = accum:4; + Rd0811 = accum(4); +} + +:smmla^ItCond Rd0811,Rn0003,Rm0003,Ra1215 is TMode=1 & ItCond & op4=0xfb5 & Rn0003; Ra1215 & Rd0811 & thc0407=0 & Rm0003 +{ + build ItCond; + local val:8 = sext(Rn0003) * sext(Rm0003); + local accum:8 = (zext(Ra1215)) << 32; + val = val + accum; + Rd0811 = val(4); +} + +:smmlar^ItCond Rd0811,Rn0003,Rm0003,Ra1215 is TMode=1 & ItCond & op4=0xfb5 & Rn0003; Ra1215 & Rd0811 & thc0407=1 & Rm0003 +{ + build ItCond; + local val:8 = sext(Rn0003) * sext(Rm0003); + local accum:8 = (zext(Ra1215)) << 32; + val = val + accum + 0x80000000; + Rd0811 = val(4); +} + +:smmls^ItCond Rd0811,Rn0003,Rm0003,Ra1215 is TMode=1 & ItCond & op4=0xfb6 & Rn0003; Ra1215 & Rd0811 & thc0407=0 & Rm0003 +{ + build ItCond; + local val:8 = sext(Rn0003) * sext(Rm0003); + val = (zext(Ra1215) << 32) - val; + Rd0811 = val(4); +} + +:smmlsr^ItCond Rd0811,Rn0003,Rm0003,Ra1215 is TMode=1 & ItCond & op4=0xfb6 & Rn0003; Ra1215 & Rd0811 & thc0407=1 & Rm0003 +{ + build ItCond; + local val:8 = sext(Rn0003) * sext(Rm0003); + val = (zext(Ra1215) << 32) - val; + val = val + 0x80000000; + Rd0811 = val(4); +} + +:smmul^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfb5 & Rn0003; thc1215=0xf & Rd0811 & thc0407=0 & Rm0003 +{ + build ItCond; + val:8 = sext(Rn0003) * sext(Rm0003); + Rd0811 = val(4); +} + +:smmulr^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfb5 & Rn0003; thc1215=0xf & Rd0811 & thc0407=1 & Rm0003 +{ + build ItCond; + val:8 = sext(Rn0003) * sext(Rm0003); + val = val + 0x80000000; + Rd0811 = val(4); +} + +:smuad^thdXbot^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfb2 & Rn0003; thc1215=0xf & Rd0811 & thc0507=0 & thdXbot & thdXtop & Rm0003 +{ + build ItCond; + local tmpRn0003 = Rn0003; + local rnbot:2 = tmpRn0003:2; + local rntop:2 = tmpRn0003(2); + local prod1:4 = sext(rnbot) * sext(thdXbot); + local prod2:4 = sext(rntop) * sext(thdXtop); + Q = scarry(prod1,prod2) || Q; #instruction does not clear the Q flag + Rd0811 = prod1 + prod2; +} + +:smulbb^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfb1 & Rn0003; op12=15 & Rd0811 & sop0407=0 & Rm0003 +{ + build ItCond; + local tmpRn0003 = Rn0003; + local tmpRm0003 = Rm0003; + op1:2 = tmpRn0003:2; + op2:2 = tmpRm0003:2; + Rd0811 = sext(op1) * sext(op2); +} + +:smulbt^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfb1 & Rn0003; op12=15 & Rd0811 & sop0407=1 & Rm0003 +{ + build ItCond; + local tmpRn0003 = Rn0003; + local tmpRm0003 = Rm0003; + op1:2 = tmpRn0003:2; + op2:2 = tmpRm0003(2); + Rd0811 = sext(op1) * sext(op2); +} + +:smultb^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfb1 & Rn0003; op12=15 & Rd0811 & sop0407=2 & Rm0003 +{ + build ItCond; + local tmpRn0003 = Rn0003; + local tmpRm0003 = Rm0003; + op1:2 = tmpRn0003(2); + op2:2 = tmpRm0003:2; + Rd0811 = sext(op1) * sext(op2); +} + +:smultt^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfb1 & Rn0003; op12=15 & Rd0811 & sop0407=3 & Rm0003 +{ + build ItCond; + local tmpRn0003 = Rn0003; + local tmpRm0003 = Rm0003; + op1:2 = tmpRn0003(2); + op2:2 = tmpRm0003(2); + Rd0811 = sext(op1) * sext(op2); +} + +:smull^ItCond Ra1215,Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfb8 & Rn0003; Ra1215 & Rd0811 & sop0407=0 & Rm0003 +{ + build ItCond; + val:8 = sext(Rn0003) * sext(Rm0003); + Ra1215 = val(0); + Rd0811 = val(4); +} + +:smusd^thdXbot^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfb4 & Rn0003; thc1215=0xf & Rd0811 & thc0507=0 & thdXbot & thdXtop & Rm0003 +{ + build ItCond; + local tmpRn0003 = Rn0003; + rnbot:2 = tmpRn0003:2; + rntop:2 = tmpRn0003(2); + tmpbot:4 = sext(rnbot) * sext(thdXbot); + tmptop:4 = sext(rntop) * sext(thdXtop); + tmp:8 = sext(tmpbot) - sext(tmptop); + Rd0811 = tmp:4; +} + +:smulw^thYBIT^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfb3 & Rn0003; thc1215=0xf & Rd0811 & thc0507=0 & thYBIT & Rm0003 +{ + build ItCond; + tmp:8 = (sext(Rn0003) * sext(thYBIT)) s>> 16; + Rd0811 = tmp:4; +} + +:srsdb^ItCond sp^"!",thSRSMode is TMode=1 & ItCond & op6=0x3a0 & sp & thc0505=1 & thc0004=0xd; op8=0xc0 & sop0507=0 & thSRSMode +{ + build ItCond; + # register list is always: r14, spsr + ptr:4 = sp - 4; + *ptr = lr; + ptr = ptr - 4; + *ptr = spsr; + sp = ptr; +} + +:srsdb^ItCond sp,thSRSMode is TMode=1 & ItCond & op6=0x3a0 & sp & thc0505=0 & thc0004=0xd; op8=0xc0 & sop0507=0 & thSRSMode +{ + build ItCond; + # register list is always: r14, spsr + ptr:4 = sp - 4; + *ptr = lr; + ptr = ptr - 4; + *ptr = spsr; +} + +:srsib^ItCond sp^"!",thSRSMode is TMode=1 & ItCond & op6=0x3a6 & sp & thc0505=1 & thc0004=0xd; op8=0xc0 & sop0507=0 & thSRSMode +{ + build ItCond; + # register list is always: r14, spsr + ptr:4 = sp + 4; + *ptr = lr; + ptr = ptr + 4; + *ptr = spsr; + sp = ptr; +} + +:srsia^ItCond sp,thSRSMode is TMode=1 & ItCond & op6=0x3a6 & sp & thc0505=0 & thc0004=0xd; op8=0xc0 & sop0507=0 & thSRSMode +{ + build ItCond; + # register list is always: r14, spsr + ptr:4 = sp + 4; + *ptr = lr; + ptr = ptr + 4; + *ptr = spsr; +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +# ssat and ssat16 were defined elsewhere and moved here to preserve sort order + +# shift operands for ssat and usat: + +th2_shift0: is imm3_shft=0x0 & imm2_shft=0x0 { } +th2_shift0: ",lsl "^thLsbImm is imm3_shft & imm2_shft & thLsbImm { } +th2_shift1: ",asr "^thLsbImm is imm3_shft & imm2_shft & thLsbImm { } +th2_shift1: ",asr #32" is imm3_shft=0x0 & imm2_shft=0x0 { } + +:ssat Rt0811, thMsbImm, part2Rd0003^th2_shift0 is + TMode=1 & part2op=0x1e & part2S=0x0 & part2cond=0xc & part2c0505=0x0 & part2c0404=0x0 & part2Rd0003 ; + thc1515=0x0 & Rt0811 & thc0505=0x0 & th2_shift0 & thMsbImm & thLsbImm +{ + # Shift bit is 0 + tmpRn:4 = part2Rd0003 << thLsbImm; + tmp:4 = SignedSaturate(tmpRn, thMsbImm); + Q = SignedDoesSaturate(tmpRn, thMsbImm); + Rt0811 = tmp; +} + +:ssat Rt0811, thMsbImm, part2Rd0003^th2_shift1 is + TMode=1 & part2op=0x1e & part2S=0x0 & part2cond=0xc & part2c0505=0x1 & part2c0404=0x0 & part2Rd0003; + thc1515=0x0 & Rt0811 & thc0505=0x0 & th2_shift1 & thMsbImm & thLsbImm +{ + # Shift bit is 1 + tmpRn:4 = part2Rd0003 s>> thLsbImm; + tmp:4 = SignedSaturate(tmpRn, thMsbImm); + Q = SignedDoesSaturate(tmpRn, thMsbImm); + Rt0811 = tmp; +} + +:ssat16 Rt0811, "#"^Immed4, part2Rd0003 is + TMode=1 & part2op=0x1e & part2S=0x0 & part2cond=0xc & part2c0505=0x1 & part2c0404=0x0 & part2Rd0003; + op12=0x0 & Rt0811 & thc0407=0x0 & Immed4 +{ + tmp:4 = SignedSaturate(part2Rd0003, Immed4); + Q = SignedDoesSaturate(part2Rd0003, Immed4); + Rt0811 = tmp; +} + +:ssax^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfae & Rn0003; op12=0xf & Rd0811 & thc0407=0x0 & Rm0003 +{ + build ItCond; + sum:4 = sext(Rn0003[ 0,16]) + sext(Rm0003[16,16]); + diff:4 = sext(Rn0003[16,16]) - sext(Rm0003[ 0,16]); + Rd0811[ 0,16] = sum[0,16]; + Rd0811[16,16] = diff[0,16]; + GE1 = sum s>= 0; + GE2 = sum s>= 0; + GE3 = diff s>= 0; + GE4 = diff s>= 0; +} + +:ssub16^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfad & Rn0003; op12=0xf & Rd0811 & thc0407=0x0 & Rm0003 +{ + build ItCond; + diff1:4 = sext(Rn0003[ 0,16]) - sext(Rm0003[ 0,16]); + diff2:4 = sext(Rn0003[16,16]) - sext(Rm0003[16,16]); + Rd0811[ 0,16] = diff1[0,16]; + Rd0811[16,16] = diff2[0,16]; + GE1 = diff1 s>= 0; + GE2 = diff1 s>= 0; + GE3 = diff2 s>= 0; + GE4 = diff2 s>= 0; +} + +:ssub8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfac & Rn0003; op12=0xf & Rd0811 & thc0407=0x0 & Rm0003 +{ + build ItCond; + diff1:4 = sext(Rn0003[ 0,8]) - sext(Rm0003[ 0,8]); + diff2:4 = sext(Rn0003[ 8,8]) - sext(Rm0003[ 8,8]); + diff3:4 = sext(Rn0003[16,8]) - sext(Rm0003[16,8]); + diff4:4 = sext(Rn0003[24,8]) - sext(Rm0003[24,8]); + Rd0811[ 0,8] = diff1[0,8]; + Rd0811[ 8,8] = diff2[0,8]; + Rd0811[16,8] = diff3[0,8]; + Rd0811[24,8] = diff4[0,8]; + GE1 = diff1 s>= 0; + GE2 = diff2 s>= 0; + GE3 = diff3 s>= 0; + GE4 = diff4 s>= 0; +} + +:umull^ItCond Ra1215,Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfba & Rn0003; Ra1215 & Rd0811 & sop0407=0 & Rm0003 +{ + build ItCond; + val:8 = zext(Rn0003) * zext(Rm0003); + Ra1215 = val(0); + Rd0811 = val(4); +} + +:umaal^ItCond Ra1215,Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfbe & Rn0003; Ra1215 & Rd0811 & sop0407=6 & Rm0003 +{ + build ItCond; + val:8 = zext(Rn0003) * zext(Rm0003) + zext(Ra1215) + zext(Rd0811); + Ra1215 = val(0); + Rd0811 = val(4); +} + +:umlal^ItCond Ra1215,Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfbe & Rn0003; Ra1215 & Rd0811 & sop0407=0 & Rm0003 +{ + build ItCond; + accum:8 = (zext(Rd0811) << 32) | zext(Ra1215); + val:8 = zext(Rn0003) * zext(Rm0003) + accum; + Ra1215 = val(0); + Rd0811 = val(4); +} + +@endif # defined(VERSION_6T2) || defined(VERSION_7) + +@if defined(VERSION_6) + +thumbEndianNess: "LE" is op0=0xb650 { export 0:1; } +thumbEndianNess: "BE" is op0=0xb658 { export 1:1; } + +:setend^ItCond thumbEndianNess is TMode=1 & ItCond & (op0=0xb650 | op0=0xb658) & thumbEndianNess { setEndianState(thumbEndianNess); } + + +:sev^ItCond is TMode=1 & ItCond & op0=0xbf40 +{ + build ItCond; +} + +:sev^ItCond^".w" is TMode=1 & ItCond & op0=0xf3af; op0=8004 +{ + build ItCond; +} + +@endif # VERSION_6 + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:stc^ItCond thcpn,thCRd,taddrmode5 is (TMode=1 & ItCond & op9=0x76 & thN6=0 & thL4=0; thCRd & thcpn) & taddrmode5 +{ + build ItCond; + build taddrmode5; + t_cpn:4 = thcpn; + coprocessor_store(t_cpn,thCRd,taddrmode5); +} + +:stcl^ItCond thcpn,thCRd,taddrmode5 is (TMode=1 & ItCond & op9=0x76 & thN6=1 & thL4=0; thCRd & thcpn) & taddrmode5 +{ + build ItCond; + build taddrmode5; + t_cpn:4 = thcpn; + coprocessor_storelong(t_cpn,thCRd,taddrmode5); +} + +:stc2^ItCond thcpn,thCRd,taddrmode5 is (TMode=1 & ItCond & op9=0x7e & thN6=0 & thL4=0; thCRd & thcpn) & taddrmode5 +{ + build ItCond; + build taddrmode5; + t_cpn:4 = thcpn; + coprocessor_store(t_cpn,thCRd,taddrmode5); +} + +:stc2l^ItCond thcpn,thCRd,taddrmode5 is (TMode=1 & ItCond & op9=0x7e & thN6=1 & thL4=0; thCRd & thcpn) & taddrmode5 +{ + build ItCond; + build taddrmode5; + t_cpn:4 = thcpn; + coprocessor_storelong(t_cpn,thCRd,taddrmode5); +} + +:stm^ItCond Rn0003,thstrlist_inc is TMode=1 & ItCond & op11=0x1d & thc0910=0 & sop0608=2 & thwbit=0 & thc0404=0 & Rn0003; thc1515=0 & thc1313=0 & thstrlist_inc +{ + build ItCond; + mult_addr = Rn0003; + build thstrlist_inc; +} + +:stm^ItCond^".w" Rn0003!,thstrlist_inc is TMode=1 & ItCond & op11=0x1d & thc0910=0 & sop0608=2 & thwbit=1 & thc0404=0 & Rn0003; thc1515=0 & thc1313=0 & thstrlist_inc +{ + build ItCond; + mult_addr = Rn0003; + build thstrlist_inc; + Rn0003 = mult_addr; +} + +:stmdb^ItCond Rn0003!,thstrlist_dec is TMode=1 & ItCond & op4=0xe92 & Rn0003; thc1515=0 & thc1313=0 & thstrlist_dec +{ + build ItCond; + mult_addr = Rn0003-4; + build thstrlist_dec; + Rn0003 = mult_addr + 4; +} + +:stmdb^ItCond Rn0003,thstrlist_dec is TMode=1 & ItCond & op4=0xe90 & Rn0003; thc1515=0 & thc1313=0 & thstrlist_dec +{ + build ItCond; + mult_addr = Rn0003-4; + build thstrlist_dec; +} + +@endif # defined(VERSION_6T2) || defined(VERSION_7) + +:stmia^ItCond Rn_exclaim,stbrace is TMode=1 & ItCond & op11=0x18 & Rn_exclaim & stbrace & Rn_exclaim_WB +{ + build ItCond; + build Rn_exclaim; + build stbrace; + build Rn_exclaim_WB; +} + +:str^ItCond Rd0002,RnIndirect4 is TMode=1 & ItCond & op11=0xc & RnIndirect4 & Rd0002 +{ + build ItCond; + *RnIndirect4 = Rd0002; +} + +:str^ItCond Rd0002,RnRmIndirect is TMode=1 & ItCond & op9=0x28 & RnRmIndirect & Rd0002 +{ + build ItCond; + *RnRmIndirect = Rd0002; +} + +:str^ItCond Rd0810,Sprel8Indirect is TMode=1 & ItCond & op11=0x12 & Sprel8Indirect & Rd0810 +{ + build ItCond; + *Sprel8Indirect = Rd0810; +} + + +:strb^ItCond Rd0002,RnIndirect1 is TMode=1 & ItCond & op11=0xe & RnIndirect1 & Rd0002 +{ + build ItCond; + local tmpRd0002 = Rd0002; + *RnIndirect1 = tmpRd0002:1; +} + +:strb^ItCond Rd0002,RnRmIndirect is TMode=1 & ItCond & op9=0x2a & RnRmIndirect & Rd0002 +{ + build ItCond; + local tmpRd0002 = Rd0002; + *RnRmIndirect = tmpRd0002:1; +} + +:strh^ItCond Rd0002,RnIndirect2 is TMode=1 & ItCond & op11=0x10 & RnIndirect2 & Rd0002 +{ + build ItCond; + local tmpRd0002 = Rd0002; + *RnIndirect2 = tmpRd0002:2; +} + +:strh^ItCond Rd0002,RnRmIndirect is TMode=1 & ItCond & op9=0x29 & RnRmIndirect & Rd0002 +{ + build ItCond; + local tmpRd0002 = Rd0002; + *RnRmIndirect = tmpRd0002:2; +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:str.w^ItCond Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf8c; Rt1215) & RnIndirect12 +{ + build ItCond; + *RnIndirect12 = Rt1215; +} + +:str.w^ItCond Rt1215,RnIndirectPUW is TMode=1 & ItCond & (op4=0xf84; Rt1215 & thc1111=1) & $(RN_INDIRECT_PUW) +{ + build ItCond; + build RnIndirectPUW; + *RnIndirectPUW = Rt1215; +} + +:str^ItCond^".w" Rt1215,[Rn0003,Rm0003] is TMode=1 & ItCond & op4=0xf84 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405=0 & Rm0003 +{ + build ItCond; + local tmp = Rn0003 + Rm0003; + *tmp = Rt1215; +} + +:str^ItCond^".w" Rt1215,[Rn0003,Rm0003,"lsl #"^thc0405] is TMode=1 & ItCond & op4=0xf84 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003 +{ + build ItCond; + local tmp = Rn0003 + (Rm0003 << thc0405); + *tmp = Rt1215; +} + +:strb^ItCond^".w" Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf88; Rt1215) & RnIndirect12 +{ + build ItCond; + build RnIndirect12; + local tmpRt1215 = Rt1215; + *RnIndirect12 = tmpRt1215:1; +} + +:strb^ItCond^".w" Rt1215,RnIndirectPUW is TMode=1 & ItCond & (op4=0xf80; Rt1215 & thc1111=1) & $(RN_INDIRECT_PUW) +{ + build ItCond; + build RnIndirectPUW; + local tmpRt1215 = Rt1215; + *RnIndirectPUW = tmpRt1215:1; +} + +:strb^ItCond^".w" Rt1215,[Rn0003,Rm0003,"lsl #"^thc0405] is TMode=1 & ItCond & op4=0xf80 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003 +{ + build ItCond; + local tmp = Rn0003 + (Rm0003 << thc0405); + local tmpRt1215 = Rt1215; + *tmp = tmpRt1215:1; +} + +:strbt^ItCond Rt1215,[Rn0003,"#"^Immed8] is TMode=1 & ItCond & op4=0xf80 & Rn0003; Rt1215 & thc0811=14 & Immed8 +{ + build ItCond; + local tmp = Rn0003 + Immed8; + local tmpRt1215 = Rt1215; + *tmp = tmpRt1215:1; +} + +:strd^ItCond Rt1215,Rt0811,RnIndirectPUW1 is TMode=1 & ItCond & (op9=0x74 & thc0910=0 & thc0606=1 & thc0404=0 & Rn0003; Rt1215 & Rt0811) & $(RN_INDIRECT_PUW1) +{ + build ItCond; + build RnIndirectPUW1; + local tmp = RnIndirectPUW1; + *tmp = Rt1215; + tmp = tmp + 4; + *tmp = Rt0811; +} + +:strh^ItCond^".w" Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf8A; Rt1215) & RnIndirect12 +{ + build ItCond; + local tmpRt1215 = Rt1215; + *RnIndirect12 = tmpRt1215:2; +} + +:strh^ItCond Rt1215,RnIndirectPUW is TMode=1 & ItCond & (op4=0xf82; Rt1215 & thc1111=1) & $(RN_INDIRECT_PUW) +{ + build ItCond; + build RnIndirectPUW; + local tmpRt1215 = Rt1215; + *RnIndirectPUW = tmpRt1215:2; +} + +:strh^ItCond^".w" Rt1215,[Rn0003,Rm0003,"lsl #"^thc0405] is TMode=1 & ItCond & op4=0xf82 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003 +{ + build ItCond; + local tmp = Rn0003 + (Rm0003 << thc0405); + local tmpRt1215 = Rt1215; + *tmp = tmpRt1215:2; +} + +:strht^ItCond Rt1215,[Rn0003,"#"^Immed8] is TMode=1 & ItCond & op4=0xf82 & Rn0003; Rt1215 & thc0811=14 & Immed8 +{ + build ItCond; + local tmp = Rn0003 + Immed8; + local tmpRt1215 = Rt1215; + *tmp = tmpRt1215:2; +} + +macro strex(addr, value, failed) { + local access = hasExclusiveAccess(addr); + failed = 1; + if (!access) goto inst_next; + failed = 0; + *addr = value; +} + +:strex^ItCond Rd0811,Rt1215,[Rn0003,Immed8_4] is TMode=1 & ItCond & op4=0xe84 & Rn0003; Rt1215 & Rd0811 & Immed8_4 +{ + build ItCond; + local addr = Rn0003 + Immed8_4; + local value = Rt1215; + strex(addr, value, Rd0811); +} + +@endif # VERSION_6T2 || VERSION_7 + +@if defined(VERSION_7) + +:strexb^ItCond Rd0003,Rt1215,[Rn0003] is TMode=1 & ItCond & op4=0xe8c & Rn0003; Rt1215 & thc0811=15 & thc0407=4 & Rd0003 +{ + build ItCond; + local addr = Rn0003; + local value = Rt1215:1; + strex(addr, value, Rd0003); +} + +:strexh^ItCond Rd0003,Rt1215,[Rn0003] is TMode=1 & ItCond & op4=0xe8c & Rn0003; Rt1215 & thc0811=15 & thc0407=5 & Rd0003 +{ + build ItCond; + local addr = Rn0003; + local value = Rt1215:2; + strex(addr, value, Rd0003); +} + +:strexd^ItCond Rd0003,Rt1215,Rt0811,[Rn0003] is TMode=1 & ItCond & op4=0xe8c & Rn0003; Rt1215 & Rt0811 & thc0407=7 & Rd0003 +{ + build ItCond; + local addr = Rn0003; + local value:8 = (zxt(Rt0811) << 4) | zxt(Rt1215); + strex(addr, value, Rd0003); +} + +@endif # VERSION_7 + +:sub^CheckInIT_CZNO^ItCond Rd0002,Rn0305,Immed3 is TMode=1 & ItCond & op9=0xf & Immed3 & Rn0305 & Rd0002 & CheckInIT_CZNO +{ + build ItCond; + th_subflags(Rn0305,Immed3); + Rd0002 = Rn0305 - Immed3; + resflags(Rd0002); + build CheckInIT_CZNO; +} + +:sub^CheckInIT_CZNO^ItCond Rd0810,Immed8 is TMode=1 & ItCond & op11=7 & Rd0810 & Immed8 & CheckInIT_CZNO +{ + build ItCond; + th_subflags(Rd0810,Immed8); + Rd0810 = Rd0810 - Immed8; + resflags(Rd0810); + build CheckInIT_CZNO; +} + +:sub^CheckInIT_CZNO^ItCond Rd0002,Rn0305,Rm0608 is TMode=1 & ItCond & op9=0xd & Rm0608 & Rn0305 & Rd0002 & CheckInIT_CZNO +{ + build ItCond; + th_subflags(Rn0305,Rm0608); + Rd0002 = Rn0305 - Rm0608; + resflags(Rd0002); + build CheckInIT_CZNO; +} + +:sub^ItCond sp,Immed7_4 is TMode=1 & ItCond & op7=0x161 & sp & Immed7_4 +{ + build ItCond; + sp = sp - Immed7_4; +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:sub^thSBIT_CZNO^ItCond^".w" Rd0811,Rn0003,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=13 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811) & ThumbExpandImm12 +{ + build ItCond; + build ThumbExpandImm12; + th_subflags(Rn0003,ThumbExpandImm12); + Rd0811 = Rn0003-ThumbExpandImm12; + resflags(Rd0811); + build thSBIT_CZNO; +} + +:subw^ItCond Rd0811,Rn0003,Immed12 is TMode=1 & ItCond & (op11=0x1e & thc0909=1 & sop0508=5 & thc0404=0 & Rn0003; thc1515=0 & Rd0811) & Immed12 +{ + build ItCond; + th_subflags(Rn0003,Immed12); + Rd0811 = Rn0003-Immed12; + resflags(Rd0811); +} + +:sub^thSBIT_CZNO^ItCond^".w" Rd0811,Rn0003,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=13 & thSBIT_CZNO & Rn0003; thc1515=0 & Rd0811 & thshift2 +{ + build ItCond; + build thshift2; + local tmp = thshift2; + th_subflags(Rn0003,tmp); + Rd0811 = Rn0003-tmp; + resflags(Rd0811); + build thSBIT_CZNO; +} + +:sub^thSBIT_CZNO^ItCond^".w" Rd0811,sp,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=13 & thSBIT_CZNO & sp & sop0003=0xd; thc1515=0 & Rd0811) & ThumbExpandImm12 +{ + build ItCond; + build ThumbExpandImm12; + th_subflags(sp,ThumbExpandImm12); + Rd0811 = sp-ThumbExpandImm12; + resflags(Rd0811); + build thSBIT_CZNO; +} + +:sub^ItCond pc,lr,Immed8 is TMode=1 & ItCond & op4=0xf3d & pc & sop0003=0xe; op8=0x8f & lr & Immed8 +{ + build ItCond; + build Immed8; + th_subflags(lr,Immed8); + dest:4 = lr-Immed8; + resflags(dest); + cpsr=spsr; + SetThumbMode( ((cpsr >> 5) & 1) != 0 ); + pc = dest; + goto [pc]; +} + +:subw^ItCond Rd0811,sp,Immed12 is TMode=1 & ItCond & (op11=0x1e & thc0909=1 & sop0508=5 & thc0404=0 & sop0003=0xd & sp; thc1515=0 & Rd0811) & Immed12 +{ + build ItCond; + th_subflags(sp,Immed12); + Rd0811 = sp-Immed12; + resflags(Rd0811); +} + +:sub^thSBIT_CZNO^ItCond^".w" Rd0811,sp,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=13 & thSBIT_CZNO & sop0003=0xd & sp; thc1515=0 & Rd0811 & thshift2 +{ + build ItCond; + build thshift2; + local tmp = thshift2; + th_subflags(sp,tmp); + Rd0811 = sp-tmp; + resflags(Rd0811); + build thSBIT_CZNO; +} + +@endif # VERSION_6T2 || VERSION_7 + +:svc^ItCond immed8 is TMode=1 & ItCond & op8=0xdf & immed8 +{ + build ItCond; + tmp:4 = immed8; + software_interrupt(tmp); +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:sxtab^ItCond Rd0811, Rn0003, Rm0003, ByteRotate is TMode=1 & ItCond & op4=0xfa4 & Rn0003; op12=0xf & Rd0811 & thc0707=1 & thc0606=0 & ByteRotate & Rm0003 +{ + build ItCond; + tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate); + Rd0811 = sext(tmp:1) + Rn0003; +} + +:sxtab^ItCond Rd0811, Rn0003, Rm0003 is TMode=1 & ItCond & op4=0xfa4 & Rn0003; op12=0xf & Rd0811 & thc0707=1 & throt=0 & Rm0003 +{ + build ItCond; + local tmpRm0003 = Rm0003; + Rd0811 = sext(tmpRm0003:1) + Rn0003; +} + +:sxtab16^ItCond Rd0811, Rn0003, Rm0003, ByteRotate is TMode=1 & ItCond & op4=0xfa2 & Rn0003; op12=0xf & Rd0811 & thc0707=1 & thc0606=0 & ByteRotate & Rm0003 +{ + build ItCond; + tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate); + local tmpRn0003 = Rn0003; + tmpL:2 = sext(tmp:1) + tmpRn0003:2; + tmp = tmp >> 16; + tmpH:2 = sext(tmp:1) + tmpRn0003(2); + Rd0811 = zext(tmpL) + (zext(tmpH) << 16); +} + +:sxtab16^ItCond Rd0811, Rn0003, Rm0003 is TMode=1 & ItCond & op4=0xfa2 & Rn0003; op12=0xf & Rd0811 & thc0707=1 & throt=0 & Rm0003 +{ + build ItCond; + local tmpRn0003 = Rn0003; + local tmpRm0003 = Rm0003; + tmpL:2 = sext(tmpRm0003:1) + tmpRn0003:2; + local tmp = tmpRm0003 >> 16; + tmpH:2 = sext(tmp:1) + tmpRn0003(2); + Rd0811 = zext(tmpL) + (zext(tmpH) << 16); +} + +:sxtah^ItCond Rd0811, Rn0003, Rm0003, ByteRotate is TMode=1 & ItCond & op4=0xfa0 & Rn0003; op12=0xf & Rd0811 & thc0707=1 & thc0606=0 & ByteRotate & Rm0003 +{ + build ItCond; + tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate); + Rd0811 = sext(tmp:2) + Rn0003; +} + +:sxtah^ItCond Rd0811, Rn0003, Rm0003 is TMode=1 & ItCond & op4=0xfa0 & Rn0003; op12=0xf & Rd0811 & thc0707=1 & throt=0 & Rm0003 +{ + build ItCond; + local tmpRm0003 = Rm0003; + Rd0811 = sext(tmpRm0003:2) + Rn0003; +} + +@endif # VERSION_6T2 || VERSION_7 + +@if defined(VERSION_6) + +:sxtb^ItCond Rd0002, Rm0305 is TMode=1 & ItCond & op8=0xb2 & thc0707=0 & thc0606=1 & Rm0305 & Rd0002 +{ + build ItCond; + local tmpRm0305 = Rm0305; + Rd0002 = sext(tmpRm0305:1); +} + +:sxtb^ItCond^".w" Rd0811, Rm0003, ByteRotate is TMode=1 & ItCond & op0=0xfa4f; op12=0xf & Rd0811 & thc0707=1 & thc0606=0 & ByteRotate & Rm0003 +{ + build ItCond; + tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate); + Rd0811 = sext(tmp:1); +} + +:sxtb^ItCond^".w" Rd0811, Rm0003 is TMode=1 & ItCond & op0=0xfa4f; op12=0xf & Rd0811 & thc0707=1 & throt=0 & Rm0003 +{ + build ItCond; + local tmpRm0003 = Rm0003; + Rd0811 = sext(tmpRm0003:1); +} + +@endif # VERSION_6 + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:sxtb16^ItCond Rd0811, Rm0003, ByteRotate is TMode=1 & ItCond & op0=0xfa2f; op12=0xf & Rd0811 & thc0707=1 & thc0606=0 & ByteRotate & Rm0003 + +{ + build ItCond; + tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate); + tmpL:2 = sext(tmp:1); + tmp = tmp >> 16; + tmpH:2 = sext(tmp:1); + Rd0811 = zext(tmpL) + (zext(tmpH) << 16); +} + +:sxtb16^ItCond Rd0811, Rm0003 is TMode=1 & ItCond & op0=0xfa2f; op12=0xf & Rd0811 & thc0707=1 & throt=0 & Rm0003 +{ + build ItCond; + local tmpRm0003 = Rm0003; + tmpL:2 = sext(tmpRm0003:1); + tmp:4 = tmpRm0003 >> 16; + tmpH:2 = sext(tmp:1); + Rd0811 = zext(tmpL) + (zext(tmpH) << 16); +} + +@endif # VERSION_6T2 || VERSION_7 + +@if defined(VERSION_6) + +:sxth^ItCond Rd0002, Rm0305 is TMode=1 & ItCond & op8=0xb2 & thc0707=0 & thc0606=0 & Rm0305 & Rd0002 +{ + build ItCond; + local tmpRm0305 = Rm0305; + Rd0002 = sext(tmpRm0305:2); +} + +:sxth^ItCond^".w" Rd0811, Rm0003, ByteRotate is TMode=1 & ItCond & op0=0xfa0f; op12=0xf & Rd0811 & thc0707=1 & thc0606=0 & ByteRotate & Rm0003 +{ + build ItCond; + tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate); + Rd0811 = sext(tmp:2); +} + +:sxth^ItCond^".w" Rd0811, Rm0003 is TMode=1 & ItCond & op0=0xfa0f; op12=0xf & Rd0811 & thc0707=1 & throt=0 & Rm0003 +{ + build ItCond; + local tmpRm0003 = Rm0003; + Rd0811 = sext(tmpRm0003:2); +} + +@endif # VERSION_6 + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:tbb^ItCond [Rn0003,Rm0003] is TMode=1 & ItCond & op4=0xe8d & Rn0003; op8=0xf0 & thc0507=0 & thc0404=0 & Rm0003 +{ + build ItCond; + local tmp = Rn0003 + Rm0003; + offs:1 = *tmp; + SetThumbMode(1); + pc = inst_next + (zext(offs) * 2); + goto [pc]; +} + +:tbh^ItCond [Rn0003,Rm0003] is TMode=1 & ItCond & op4=0xe8d & Rn0003; op8=0xf0 & thc0507=0 & thc0404=1 & Rm0003 +{ + build ItCond; + local tmp = Rn0003 + (Rm0003 * 2); + offs:2 = *tmp; + SetThumbMode(1); + pc = inst_next + (zext(offs) * 2); + goto [pc]; +} + +Pcrel: [pc,Rm0003] is Rm0003 & thc0404=0 & pc +{ + local tmp = Rm0003; tmp = inst_next + tmp; val:1 = *tmp; tmp = zext(val); export tmp; +} +Pcrel: [pc,Rm0003] is Rm0003 & thc0404=1 & pc +{ + local tmp = Rm0003; tmp = inst_next + (tmp * 2); val:2 = *tmp; tmp = zext(val); export tmp; +} + +:tbb^ItCond Pcrel is TMode=1 & ItCond & op4=0xe8d & thc0003=15; op8=0xf0 & thc0507=0 & thc0404=0 & Pcrel +{ + build ItCond; + SetThumbMode(1); + pc = inst_next + (Pcrel * 2); + goto [pc]; +} + +:tbh^ItCond Pcrel is TMode=1 & ItCond & op4=0xe8d & thc0003=15; op8=0xf0 & thc0507=0 & thc0404=1 & Pcrel +{ + build ItCond; + SetThumbMode(1); + pc = inst_next + (Pcrel * 2); + goto [pc]; +} + +@endif # VERSION_6T2 || VERSION_7 + +:tst^ItCond Rn0002,Rm0305 is TMode=1 & ItCond & op6=0x108 & Rm0305 & Rn0002 +{ + build ItCond; + local tmp = Rn0002 & Rm0305; + ZR = (tmp == 0); + NG = (tmp s< 0); +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:teq^ItCond Rn0003,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=4 & thc0404=1 & Rn0003; thc1515=0 & thc0811=0xf) & ThumbExpandImm12 +{ + build ItCond; + build ThumbExpandImm12; + local tmp = Rn0003 ^ ThumbExpandImm12; + th_test_flags(tmp); +} + +:teq^ItCond^".w" Rn0003,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=4 & thc0404=1 & Rn0003; thc1515=0 & thc0811=0xf & thshift2 +{ + build ItCond; + build thshift2; + local tmp = Rn0003 ^ thshift2; + th_test_flags(tmp); +} + +:tst^ItCond Rn0003,ThumbExpandImm12 is TMode=1 & ItCond & (op11=0x1e & thc0909=0 & sop0508=0 & thc0404=1 & Rn0003; thc1515=0 & thc0811=0xf) & ThumbExpandImm12 +{ + build ItCond; + build ThumbExpandImm12; + local tmp = Rn0003 & ThumbExpandImm12; + th_test_flags(tmp); +} + +:tst^ItCond^".w" Rn0003,thshift2 is TMode=1 & ItCond & op11=0x1d & thc0910=1 & sop0508=0 & thc0404=1 & Rn0003; thc1515=0 & thc0811=0xf & thshift2 +{ + build ItCond; + build thshift2; + local tmp = Rn0003 & thshift2; + th_test_flags(tmp); +} + +:uadd16^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa9 & Rn0003; op12=0xf & Rd0811 & thc0407=0x4 & Rm0003 +{ + build ItCond; + sum1:4 = zext(Rn0003[ 0,16]) + zext(Rm0003[ 0,16]); + sum2:4 = zext(Rn0003[16,16]) + zext(Rm0003[16,16]); + GE1 = carry(Rn0003[0,16],Rm0003[0,16]); + GE2 = GE1; + GE3 = carry(Rn0003[16,16],Rm0003[16,16]); + GE4 = GE3; + Rd0811[ 0,16] = sum1[0,16]; + Rd0811[16,16] = sum2[0,16]; +} + +:uadd8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa8 & Rn0003; op12=0xf & Rd0811 & thc0407=0x4 & Rm0003 +{ + build ItCond; + sum1:4 = zext(Rn0003[ 0,8]) + zext(Rm0003[ 0,8]); + sum2:4 = zext(Rn0003[ 8,8]) + zext(Rm0003[ 8,8]); + sum3:4 = zext(Rn0003[16,8]) + zext(Rm0003[16,8]); + sum4:4 = zext(Rn0003[24,8]) + zext(Rm0003[24,8]); + GE1 = carry(Rn0003[0,8],Rm0003[0,8]); + GE2 = carry(Rn0003[8,8],Rm0003[8,8]); + GE3 = carry(Rn0003[16,8],Rm0003[16,8]); + GE4 = carry(Rn0003[24,8],Rm0003[24,8]); + Rd0811[ 0,8] = sum1[0,8]; + Rd0811[ 8,8] = sum2[0,8]; + Rd0811[16,8] = sum3[0,8]; + Rd0811[24,8] = sum4[0,8]; +} + +:uasx^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfaa & Rn0003; op12=0xf & Rd0811 & thc0407=0x4 & Rm0003 +{ + build ItCond; + diff:4 = zext(Rn0003[ 0,16]) - zext(Rm0003[16,16]); + sum:4 = zext(Rn0003[16,16]) + zext(Rm0003[ 0,16]); + GE1 = diff s>= 0; + GE2 = GE1; + GE3 = carry(Rn0003[16,16],Rm0003[0,16]); + GE4 = GE3; + Rd0811[ 0,16] = diff[0,16]; + Rd0811[16,16] = sum[0,16]; + } + +:uhadd16^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa9 & Rn0003; op12=0xf & Rd0811 & thc0407=0x6 & Rm0003 +{ + build ItCond; + sum1:4 = zext(Rn0003[ 0,16]) + zext(Rm0003[ 0,16]); + sum2:4 = zext(Rn0003[16,16]) + zext(Rm0003[16,16]); + Rd0811[ 0,16] = sum1[1,16]; + Rd0811[16,16] = sum2[1,16]; +} + +:uhadd8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa8 & Rn0003; op12=0xf & Rd0811 & thc0407=0x6 & Rm0003 +{ + build ItCond; + sum1:4 = zext(Rn0003[ 0,8]) + zext(Rm0003[ 0,8]); + sum2:4 = zext(Rn0003[ 8,8]) + zext(Rm0003[ 8,8]); + sum3:4 = zext(Rn0003[16,8]) + zext(Rm0003[16,8]); + sum4:4 = zext(Rn0003[24,8]) + zext(Rm0003[24,8]); + Rd0811[ 0,8] = sum1[1,8]; + Rd0811[ 8,8] = sum2[1,8]; + Rd0811[16,8] = sum3[1,8]; + Rd0811[24,8] = sum4[1,8]; +} + +:uhasx^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfaa & Rn0003; op12=0xf & Rd0811 & thc0407=0x6 & Rm0003 +{ + build ItCond; + diff:4 = zext(Rn0003[ 0,16]) - zext(Rm0003[16,16]); + sum:4 = zext(Rn0003[16,16]) + zext(Rm0003[ 0,16]); + Rd0811[ 0,16] = diff[1,16]; + Rd0811[16,16] = sum[1,16]; +} + +:uhsax^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfae & Rn0003; op12=0xf & Rd0811 & thc0407=0x6 & Rm0003 +{ + build ItCond; + sum:4 = zext(Rn0003[ 0,16]) + zext(Rm0003[16,16]); + diff:4 = zext(Rn0003[16,16]) - zext(Rm0003[ 0,16]); + Rd0811[ 0,16] = sum[1,16]; + Rd0811[16,16] = diff[1,16]; +} + +:uhsub16^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfad & Rn0003; op12=0xf & Rd0811 & thc0407=0x6 & Rm0003 +{ + build ItCond; + diff1:4 = zext(Rn0003[ 0,16]) - zext(Rm0003[ 0,16]); + diff2:4 = zext(Rn0003[16,16]) - zext(Rm0003[16,16]); + Rd0811[ 0,16] = diff1[1,16]; + Rd0811[16,16] = diff2[1,16]; +} + +:uhsub8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfac & Rn0003; op12=0xf & Rd0811 & thc0407=0x6 & Rm0003 +{ + build ItCond; + diff1:4 = zext(Rn0003[ 0,8]) - zext(Rm0003[ 0,8]); + diff2:4 = zext(Rn0003[ 8,8]) - zext(Rm0003[ 8,8]); + diff3:4 = zext(Rn0003[16,8]) - zext(Rm0003[16,8]); + diff4:4 = zext(Rn0003[24,8]) - zext(Rm0003[24,8]); + Rd0811[ 0,8] = diff1[1,8]; + Rd0811[ 8,8] = diff2[1,8]; + Rd0811[16,8] = diff3[1,8]; + Rd0811[24,8] = diff4[1,8]; +} + +:uqadd16^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa9 & Rn0003; op12=0xf & Rd0811 & thc0407=0x5 & Rm0003 +{ + build ItCond; + sum1:4 = zext(Rn0003[ 0,16]) + zext(Rm0003[ 0,16]); + sum2:4 = zext(Rn0003[16,16]) + zext(Rm0003[16,16]); + tmp1:4 = UnsignedSaturate(sum1, 16:2); + tmp2:4 = UnsignedSaturate(sum2, 16:2); + Rd0811[ 0,16] = tmp1[0,16]; + Rd0811[16,16] = tmp2[0,16]; +} + +:uqadd8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa8 & Rn0003; op12=0xf & Rd0811 & thc0407=0x5 & Rm0003 +{ + build ItCond; + sum1:4 = zext(Rn0003[ 0,8]) + zext(Rm0003[ 0,8]); + sum2:4 = zext(Rn0003[ 8,8]) + zext(Rm0003[ 8,8]); + sum3:4 = zext(Rn0003[16,8]) + zext(Rm0003[16,8]); + sum4:4 = zext(Rn0003[24,8]) + zext(Rm0003[24,8]); + tmp1:4 = UnsignedSaturate(sum1, 8:2); + tmp2:4 = UnsignedSaturate(sum2, 8:2); + tmp3:4 = UnsignedSaturate(sum3, 8:2); + tmp4:4 = UnsignedSaturate(sum4, 8:2); + Rd0811[ 0,8] = tmp1[0,8]; + Rd0811[ 8,8] = tmp2[0,8]; + Rd0811[16,8] = tmp3[0,8]; + Rd0811[24,8] = tmp4[0,8]; +} + +:uqasx^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfaa & Rn0003; op12=0xf & Rd0811 & thc0407=0x5 & Rm0003 +{ + build ItCond; + diff:4 = zext(Rn0003[ 0,16]) - zext(Rm0003[16,16]); + sum:4 = zext(Rn0003[16,16]) + zext(Rm0003[ 0,16]); + tmpdiff:4 = UnsignedSaturate(diff, 16:2); + tmpsum:4 = UnsignedSaturate(sum, 16:2); + Rd0811[ 0,16] = tmpdiff[0,16]; + Rd0811[16,16] = tmpsum[0,16]; +} + +:uqsax^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfae & Rn0003; op12=0xf & Rd0811 & thc0407=0x5 & Rm0003 +{ + build ItCond; + sum:4 = zext(Rn0003[ 0,16]) + zext(Rm0003[16,16]); + diff:4 = zext(Rn0003[16,16]) - zext(Rm0003[ 0,16]); + tmpsum:4 = UnsignedSaturate(sum, 16:2); + tmpdiff:4 = UnsignedSaturate(diff, 16:2); + Rd0811[ 0,16] = tmpsum[0,16]; + Rd0811[16,16] = tmpdiff[0,16]; +} + +:uqsub16^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfad & Rn0003; op12=0xf & Rd0811 & thc0407=0x5 & Rm0003 +{ + build ItCond; + diff1:4 = zext(Rn0003[ 0,16]) - zext(Rm0003[ 0,16]); + diff2:4 = zext(Rn0003[16,16]) - zext(Rm0003[16,16]); + tmp1:4 = UnsignedSaturate(diff1, 16:2); + tmp2:4 = UnsignedSaturate(diff2, 16:2); + Rd0811[ 0,16] = tmp1[0,16]; + Rd0811[16,16] = tmp2[0,16]; +} + +:uqsub8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfac & Rn0003; op12=0xf & Rd0811 & thc0407=0x5 & Rm0003 +{ + build ItCond; + diff1:4 = zext(Rn0003[ 0,8]) - zext(Rm0003[ 0,8]); + diff2:4 = zext(Rn0003[ 8,8]) - zext(Rm0003[ 8,8]); + diff3:4 = zext(Rn0003[16,8]) - zext(Rm0003[16,8]); + diff4:4 = zext(Rn0003[24,8]) - zext(Rm0003[24,8]); + tmp1:4 = UnsignedSaturate(diff1, 8:2); + tmp2:4 = UnsignedSaturate(diff2, 8:2); + tmp3:4 = UnsignedSaturate(diff3, 8:2); + tmp4:4 = UnsignedSaturate(diff4, 8:2); + Rd0811[ 0,8] = tmp1[0,8]; + Rd0811[ 8,8] = tmp2[0,8]; + Rd0811[16,8] = tmp3[0,8]; + Rd0811[24,8] = tmp4[0,8]; +} + +:usad8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfb7 & Rn0003; op12=0xf & Rd0811 & thc0407=0x0 & Rm0003 +{ + build ItCond; + diff1:4 = zext(Rn0003[ 0,8]) - zext(Rm0003[ 0,8]); + diff2:4 = zext(Rn0003[ 8,8]) - zext(Rm0003[ 8,8]); + diff3:4 = zext(Rn0003[16,8]) - zext(Rm0003[16,8]); + diff4:4 = zext(Rn0003[24,8]) - zext(Rm0003[24,8]); + absdiff1:4 = Absolute(diff1); + absdiff2:4 = Absolute(diff2); + absdiff3:4 = Absolute(diff3); + absdiff4:4 = Absolute(diff4); + Rd0811 = absdiff1 + absdiff2 + absdiff3 + absdiff4; +} + +:usada8^ItCond Rd0811,Rn0003,Rm0003,Ra1215 is TMode=1 & ItCond & op4=0xfb7 & Rn0003; Ra1215 & Rd0811 & thc0407=0x0 & Rm0003 +{ + build ItCond; + diff1:4 = zext(Rn0003[ 0,8]) - zext(Rm0003[ 0,8]); + diff2:4 = zext(Rn0003[ 8,8]) - zext(Rm0003[ 8,8]); + diff3:4 = zext(Rn0003[16,8]) - zext(Rm0003[16,8]); + diff4:4 = zext(Rn0003[24,8]) - zext(Rm0003[24,8]); + absdiff1:4 = Absolute(diff1); + absdiff2:4 = Absolute(diff2); + absdiff3:4 = Absolute(diff3); + absdiff4:4 = Absolute(diff4); + # The manual specifies a zero extension of Ra to an unspecified + # intermediate precision, followed by truncation to 4 bytes. In this + # model, zext is retained, but it has no effect because the + # intermediate precision is 4 bytes. + Rd0811 = zext(Ra1215) + absdiff1 + absdiff2 + absdiff3 + absdiff4; +} + +# usat and ussat16 were defined elsewhere and moved here to preserve sort order + +:usat Rt0811, thMsbImm, part2Rd0003^th2_shift0 is + TMode=1 & part2op=0x1e & part2S=0x0 & part2cond=0xe & part2c0505=0x0 & part2c0404=0x0 & part2Rd0003 ; + thc1515=0x0 & Rt0811 & thc0505=0x0 & th2_shift0 & thMsbImm & thLsbImm +{ + # Shift bit is 0 + tmpRn:4 = part2Rd0003 << thLsbImm; + tmp:4 = UnsignedSaturate(tmpRn, thMsbImm); + Q = UnsignedDoesSaturate(tmpRn, thMsbImm); + Rt0811 = tmp; +} + +:usat Rt0811, thMsbImm, part2Rd0003^th2_shift1 is + TMode=1 & part2op=0x1e & part2S=0x0 & part2cond=0xe & part2c0505=0x1 & part2c0404=0x0 & part2Rd0003 ; + thc1515=0x0 & Rt0811 & thc0505=0x0 & th2_shift1 & thMsbImm & thLsbImm +{ + # Shift bit is 1 + tmpRn:4 = part2Rd0003 s>> thLsbImm; + tmp:4 = UnsignedSaturate(tmpRn, thMsbImm); + Q = UnsignedDoesSaturate(tmpRn, thMsbImm); + Rt0811 = tmp; +} + +:usat16 Rt0811, "#"^Immed4, part2Rd0003 is + TMode=1 & part2op=0x1e & part2S=0x0 & part2cond=0xe & part2c0505=0x1 & part2c0404=0x0 & part2Rd0003 ; + op12=0x0 & Rt0811 & thc0407=0x0 & Immed4 +{ + tmp:4 = UnsignedSaturate(part2Rd0003, Immed4); + Q = UnsignedDoesSaturate(part2Rd0003, Immed4); + Rt0811 = tmp; +} + +:usax^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfae & Rn0003; op12=0xf & Rd0811 & thc0407=0x4 & Rm0003 +{ + build ItCond; + sum:4 = zext(Rn0003[ 0,16]) + zext(Rm0003[16,16]); + diff:4 = zext(Rn0003[16,16]) - zext(Rm0003[ 0,16]); + Rd0811[ 0,16] = sum[0,16]; + Rd0811[16,16] = diff[0,16]; + # this odd looking condition tests that the 16 bit sum overflowed, + # which would have made it a negative number. That's how it's + # documented, but to be consistent they might have used s< 0. + GE1 = sum s>= 0x10000; + GE2 = sum s>= 0x10000; + GE3 = diff s>= 0; + GE4 = diff s>= 0; +} + +:usub16^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfad & Rn0003; op12=0xf & Rd0811 & thc0407=0x4 & Rm0003 +{ + build ItCond; + diff1:4 = zext(Rn0003[ 0,16]) - zext(Rm0003[ 0,16]); + diff2:4 = zext(Rn0003[16,16]) - zext(Rm0003[16,16]); + Rd0811[ 0,16] = diff1[0,16]; + Rd0811[16,16] = diff2[0,16]; + GE1 = diff1 s>= 0; + GE2 = diff1 s>= 0; + GE3 = diff2 s>= 0; + GE4 = diff2 s>= 0; +} + +:usub8^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfac & Rn0003; op12=0xf & Rd0811 & thc0407=0x4 & Rm0003 +{ + build ItCond; + diff1:4 = zext(Rn0003[ 0,8]) - zext(Rm0003[ 0,8]); + diff2:4 = zext(Rn0003[ 8,8]) - zext(Rm0003[ 8,8]); + diff3:4 = zext(Rn0003[16,8]) - zext(Rm0003[16,8]); + diff4:4 = zext(Rn0003[24,8]) - zext(Rm0003[24,8]); + Rd0811[ 0,8] = diff1[0,8]; + Rd0811[ 8,8] = diff2[0,8]; + Rd0811[16,8] = diff3[0,8]; + Rd0811[24,8] = diff4[0,8]; + GE1 = diff1 s>= 0; + GE2 = diff2 s>= 0; + GE3 = diff3 s>= 0; + GE4 = diff4 s>= 0; +} + +:ubfx^ItCond Rd0811,Rn0003,thLsbImm,thWidthMinus1 is TMode=1 & ItCond & op4=0xf3c & Rn0003; thc1515=0 & Rd0811 & thLsbImm & thc0505=0 & thWidthMinus1 +{ + build ItCond; + build thLsbImm; + build thWidthMinus1; + shift:4 = 31 - (thLsbImm + thWidthMinus1); # thMsbImm represents widthMinus1 + Rd0811 = Rn0003 << shift; + shift = 31 - thWidthMinus1; # msbImm represents widthMinus1 + Rd0811 = Rd0811 >> shift; +} + +:udiv^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfbb & Rn0003; op12=0xf & Rd0811 & thc0407=0xf & Rm0003 +{ + build ItCond; + udiv(Rd0811, Rn0003, Rm0003); +} + +:uxtab^ItCond Rd0811,Rn0003,Rm0003,ByteRotate is TMode=1 & ItCond & op4=0xfa5 & Rn0003; op12=15 & Rd0811 & thc0707=1 & ByteRotate & Rm0003 +{ + build ItCond; + tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate); + Rd0811 = Rn0003 + zext(tmp:1); +} + +:uxtab16^ItCond Rd0811,Rn0003,Rm0003,ByteRotate is TMode=1 & ItCond & op4=0xfa3 & Rn0003; op12=15 & Rd0811 & thc0707=1 & ByteRotate & Rm0003 +{ + build ItCond; + rotated:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate); + local tmp_b = rotated:1; + local tmpRn0003 = Rn0003; + tmpl:2 = tmpRn0003:2 + zext(tmp_b); + local tmph = (rotated >> 16); + tmp_b = tmph:1; + tmph = (tmpRn0003 >> 16) + zext(tmp_b); + Rd0811 = (tmph << 16) | zext(tmpl); +} + +:uxtah^ItCond Rd0811,Rn0003,Rm0003 is TMode=1 & ItCond & op4=0xfa1 & Rn0003; op12=15 & Rd0811 & thc0707=1 & throt=0 & Rm0003 +{ + build ItCond; + local tmpRm0003 = Rm0003; + Rd0811 = Rn0003 + zext(tmpRm0003:2); +} + +:uxtah^ItCond Rd0811,Rn0003,Rm0003,ByteRotate is TMode=1 & ItCond & op4=0xfa1 & Rn0003; op12=15 & Rd0811 & thc0707=1 & ByteRotate & Rm0003 +{ + build ItCond; + tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate); + Rd0811 = Rn0003 + zext(tmp:2); +} + +@endif # VERSION_6T2 || VERSION_7 + +@if defined(VERSION_6) + +:uxtb^ItCond Rd0002, Rm0305 is TMode=1 & ItCond & op8=0xb2 & thc0707=1 & thc0606=1 & Rm0305 & Rd0002 +{ + build ItCond; + local tmpRm0305 = Rm0305; + Rd0002 = zext(tmpRm0305:1); +} + +@endif # VERSION_6 + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:uxtb^ItCond^".w" Rd0811, Rm0003, ByteRotate is TMode=1 & ItCond & op0=0xfa5f; op12=0xf & Rd0811 & thc0707=1 & ByteRotate & Rm0003 +{ + build ItCond; + tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate); + Rd0811 = zext(tmp:1); +} + +:uxtb^ItCond^".w" Rd0811, Rm0003 is TMode=1 & ItCond & op0=0xfa5f; op12=0xf & Rd0811 & thc0707=1 & throt=0 & Rm0003 +{ + build ItCond; + local tmpRm0003 = Rm0003; + Rd0811 = zext(tmpRm0003:1); +} + +:uxtb16^ItCond Rd0811, Rm0003, ByteRotate is TMode=1 & ItCond & op0=0xfa3f; op12=0xf & Rd0811 & thc0707=1 & ByteRotate & Rm0003 +{ + build ItCond; + tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate); + Rd0811 = tmp & 0x00ff00ff; +} + +:uxtb16^ItCond Rd0811, Rm0003 is TMode=1 & ItCond & op0=0xfa3f; op12=0xf & Rd0811 & thc0707=1 & throt=0 & Rm0003 +{ + build ItCond; + Rd0811 = Rm0003 & 0x00ff00ff; +} + +@endif # VERSION_6T2 || VERSION_7 + +@if defined(VERSION_6) + +:uxth^ItCond Rd0002, Rm0305 is TMode=1 & ItCond & op8=0xb2 & thc0707=1 & thc0606=0 & Rm0305 & Rd0002 +{ + build ItCond; + local tmpRm0305 = Rm0305; + Rd0002 = zext(tmpRm0305:2); +} + +@endif # VERSION_6 + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:uxth^ItCond^".w" Rd0811, Rm0003, ByteRotate is TMode=1 & ItCond & op0=0xfa1f; op12=0xf & Rd0811 & thc0707=1 & ByteRotate & Rm0003 +{ build ItCond; + tmp:4 = (Rm0003 >> ByteRotate) | Rm0003 << ( 32 - ByteRotate); + Rd0811 = zext(tmp:2); +} + +:uxth^ItCond^".w" Rd0811, Rm0003 is TMode=1 & ItCond & op0=0xfa1f; op12=0xf & Rd0811 & thc0707=1 & throt=0 & Rm0003 +{ + build ItCond; + local tmpRm0003 = Rm0003; + Rd0811 = zext(tmpRm0003:2); +} + +@endif # VERSION_6T2 || VERSION_7 + +# V* see ARMneon.sinc + +@if defined(VERSION_6) + +:wfe^ItCond is TMode=1 & ItCond & op0=0xbf20 +{ + WaitForEvent(); +} + +:wfi^ItCond is TMode=1 & ItCond & op0=0xbf30 +{ + WaitForInterrupt(); +} + +:yield^ItCond is TMode=1 & ItCond & op0=0xbf10 +{ + HintYield(); +} + +@endif # VERSION_6 + +@if defined(VERSION_6T2) || defined(VERSION_7) + +:wfe^ItCond^".w" is TMode=1 & ItCond & op0=0xf3af; op0=0x8002 +{ + WaitForEvent(); +} + +:wfi^ItCond^".w" is TMode=1 & ItCond & op0=0xf3af; op0=0x8003 +{ + WaitForInterrupt(); +} + +:yield^ItCond^".w" is TMode=1 & ItCond & op0=0xf3af; op0=0x8001 +{ + HintYield(); +} +@endif #VERSION_6T2 || VERSION_7 + +} # End with : ARMcondCk=1 \ No newline at end of file diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARM_v45.cspec b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM_v45.cspec new file mode 100644 index 0000000..5b6a05a --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM_v45.cspec @@ -0,0 +1,209 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ; + offset = *:1 (lr + r3); + r3 = zext(offset); + + + if (inbounds) goto ; + offset = *:1 (lr + r12); + r3 = zext(offset); + + + r3 = r3 * 2; + + r12 = lr + r3; + + ISAModeSwitch = (r12 & 1) != 1; + TB = ISAModeSwitch; + pc = r12 & 0xfffffffe; + goto [pc]; + ]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARM_v45.pspec b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM_v45.pspec new file mode 100644 index 0000000..b7cd952 --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM_v45.pspec @@ -0,0 +1,40 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARM_win.cspec b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM_win.cspec new file mode 100644 index 0000000..f4e1dc2 --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARM_win.cspec @@ -0,0 +1,131 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc b/python/icicle/Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc new file mode 100644 index 0000000..ed3ce57 --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc @@ -0,0 +1,6488 @@ +# Specification for the ARM Version 4, 4T, 5, 5T, 5E +# The following boolean defines control specific support: T_VARIANT, VERSION_5, VERSION_5E + +# +# WARNING NOTE: Be very careful taking a subpiece or truncating a register with :# or (#) +# The LEBE hybrid language causes endian issues if you do not assign the register to a temp +# variable and then take a subpiece or truncate. +# + +@if defined(SIMD) || defined(VFPv2) || defined(VFPv3) +@define INCLUDE_NEON "" # Neon instructions included with SIMD, VFPv2 or VFPv3 +@endif + +@if defined(T_VARIANT) +@define AMODE "TMode=0" # T_VARIANT must restrict ARM instruction decoding and require TMode=0 +@else +@define AMODE "epsilon" # THUMB instructions not supported - ARM only +@endif + +@if defined(T_VARIANT) +@define VERSION_5_or_T "" +@endif +@if defined(VERSION_5) +@define VERSION_5_or_T "" +@endif + +define token prefix (32) + pref=(0,31) +; + +define token instrArm (32) + cond=(28,31) + I25=(25,25) + P24=(24,24) + H24=(24,24) + L24=(24,24) + U23=(23,23) + B22=(22,22) + N22=(22,22) + S22=(22,22) + op=(21,24) + W21=(21,21) + S20=(20,20) + L20=(20,20) + Rn=(16,19) + RnLo=(0,3) + msb=(16,20) + satimm5=(16,20) + satimm4=(16,19) + mask=(16,19) + Rd=(12,15) + Rd2=(12,15) + CRd=(12,15) + CRn=(16,19) + CRm=(0,3) + RdHi=(16,19) + RdLo=(12,15) + smRd=(16,19) + smRa=(12,15) + smRm=(8,11) + smRn=(0,3) + immed12=(8,19) + Rs=(8,11) + rotate=(8,11) + immedH=(8,11) + cpn=(8,11) + opc1=(21,23) + opcode1=(20,23) + opc2=(5,7) + opcode2=(5,7) + opcode3=(4,7) + lsb=(7,11) + sftimm=(7,11) + sh=(6,6) + shft=(5,6) + immed24=(0,23) + addr24=(0,23) signed + offset_12=(0,11) + immed=(0,7) + srsMode=(0,4) + immedL=(0,3) + immed4=(0,3) + dbOption=(0,3) + ibOption=(0,3) + Rm=(0,3) + RmHi=(8,11) + Rm2=(0,3) + x=(5,5) + r=(5,5) + y=(6,6) + + # Advanced SIMD and VFP instruction fields + D22=(22,22) + N7=(7,7) + L7=(7,7) + Q6=(6,6) + M5=(5,5) + Qn0=(16,19) + Qd0=(12,15) + Qm0=(0,3) + Qn1=(16,19) + Qd1=(12,15) + Qm1=(0,3) + Dn0=(16,19) + Dd0=(12,15) + Dd_1=(12,15) + Dd_2=(12,15) + Dd_3=(12,15) + Dd_4=(12,15) + Dd_5=(12,15) + Dd_6=(12,15) + Dd_7=(12,15) + Dd_8=(12,15) + Dd_9=(12,15) + Dd_10=(12,15) + Dd_11=(12,15) + Dd_12=(12,15) + Dd_13=(12,15) + Dd_14=(12,15) + Dd_15=(12,15) + Dd_16=(12,15) + Dm0=(0,3) + Dn1=(16,19) + Dd1=(12,15) + Dm1=(0,3) + Dm_3=(0,2) + Dm_4=(0,3) + Sn0=(16,19) + Sd0=(12,15) + Sm0=(0,3) + Sm0next=(0,3) + Sn1=(16,19) + Sd1=(12,15) + Sm1=(0,3) + Sm1next=(0,3) + Sm0_3=(0,2) + Sm1_3=(0,2) + cmode=(8,11) + + + + # Arbitrary bit fields + bit31=(31,31) + bit30=(30,30) + bit29=(29,29) + bit28=(28,28) + c2831=(28,31) + c2627=(26,27) + c2531=(25,31) + c2527=(25,27) + c2525=(25,25) + c2427=(24,27) + c2424=(24,24) + c2331=(23,31) + c2327=(23,27) + c2324=(23,24) + c2323=(23,23) + c2222=(22,22) + c2131=(21,31) + c2127=(21,27) + c2124=(21,24) + c2123=(21,23) + c2122=(21,22) + c2121=(21,21) + c2027=(20,27) + c2024=(20,24) + c2022=(20,22) + c2021=(20,21) + c2020=(20,20) + c1921=(19,21) + c1919=(19,19) + c1821=(18,21) + c1819=(18,19) + c1818=(18,18) + c1721=(17,21) + c1719=(17,19) + c1718=(17,18) + c1717=(17,17) + c1631=(16,31) + c1627=(16,27) + c1621=(16,21) + c1620=(16,20) + c1619=(16,19) + c1618=(16,18) + c1617=(16,17) + c1616=(16,16) + c1515=(15,15) + c1415=(14,15) + c1414=(14,14) + c1315=(13,15) + c1313=(13,13) + c1215=(12,15) + c1212=(12,12) + c1115=(11,15) + c1111=(11,11) + c1015=(10,15) + c1011=(10,11) + c1010=(10,10) + c0916=(9,16) + c0915=(9,15) + c0911=(9,11) + c0909=(9,9) + c0815=(8,15) + c0811=(8,11) + c0809=(8,9) + c0808=(8,8) + c0715=(7,15) + c0711=(7,11) + c0709=(7,9) + c0708=(7,8) + c0707=(7,7) + c0615=(6,15) + c0611=(6,11) + c0607=(6,7) + c0606=(6,6) + c0515=(5,15) + c0508=(5,8) + c0507=(5,7) + c0506=(5,6) + c0505=(5,5) + c0431=(4,31) + c0427=(4,27) + c0415=(4,15) + c0411=(4,11) + c0409=(4,9) + c0408=(4,8) + c0407=(4,7) + c0406=(4,6) + c0405=(4,5) + c0404=(4,4) + c0315=(3,15) + c0303=(3,3) + c0215=(2,15) + c0202=(2,2) + c0115=(1,15) + c0101=(1,1) + c0031=(0,31) + c0027=(0,27) + c0014=(0,14) + c0013=(0,13) + c0012=(0,12) + c0011=(0,11) + c0010=(0,10) + c0009=(0,9) + c0008=(0,8) + c0007=(0,7) + c0006=(0,6) + c0005=(0,5) + c0004=(0,4) + c0003=(0,3) + c0002=(0,2) + c0001=(0,1) + c0000=(0,0) + +# +# 32-bit Thumb fields which correspond closely with ARM fields for +# certain coprocessor instructions +# + +@if ENDIAN == "little" + + # Advanced SIMD and VFP instruction fields for 32-bit Little Endian Thumb + thv_D22=(6,6) + thv_N7=(23,23) + thv_L7=(23,23) + thv_Q6=(22,22) + thv_M5=(21,21) + thv_Qn0=(0,3) + thv_Qd0=(28,31) + thv_Qm0=(16,19) + thv_Qn1=(0,3) + thv_Qd1=(28,31) + thv_Qm1=(16,19) + thv_Dn0=(0,3) + thv_Dd0=(28,31) + thv_Dd_1=(28,31) + thv_Dd_2=(28,31) + thv_Dd_3=(28,31) + thv_Dd_4=(28,31) + thv_Dd_5=(28,31) + thv_Dd_6=(28,31) + thv_Dd_7=(28,31) + thv_Dd_8=(28,31) + thv_Dd_9=(28,31) + thv_Dd_10=(28,31) + thv_Dd_11=(28,31) + thv_Dd_12=(28,31) + thv_Dd_13=(28,31) + thv_Dd_14=(28,31) + thv_Dd_15=(28,31) + thv_Dd_16=(28,31) + thv_Dm0=(16,19) + thv_Dn1=(0,3) + thv_Dd1=(28,31) + thv_Dm1=(16,19) + thv_Dm_3=(16,18) + thv_Dm_4=(16,19) + thv_Sn0=(0,3) + thv_Sd0=(28,31) + thv_Sm0=(16,19) + thv_Sm0next=(16,19) + thv_Sn1=(0,3) + thv_Sd1=(28,31) + thv_Sm1=(16,19) + thv_Sm1next=(16,19) + thv_cmode=(24,27) + thv_Sm0_3=(16,18) + thv_Sm1_3=(16,18) + + thv_Rd=(28,31) + thv_Rt=(28,31) + thv_Rn=(0,3) + thv_Rm=(16,19) + thv_Rt2=(24,27) + thv_immed=(16,23) + + # Arbitrary bit fields for 32-bit Little Endian Thumb + + thv_bit31=(15,15) + thv_bit30=(14,14) + thv_bit29=(13,13) + thv_bit28=(12,12) + thv_bit23=(7,7) + thv_bit21=(5,5) + thv_bit20=(4,4) + thv_bit07=(23,23) + thv_bit06=(22,22) + thv_bit00=(16,16) + thv_c2931=(13,15) + thv_c2831=(12,15) + thv_c2828=(12,12) + thv_c2627=(10,11) + thv_c2531=(9,15) + thv_c2527=(9,11) + thv_c2525=(9,9) + thv_c2427=(8,11) + thv_c2424=(8,8) + thv_c2331=(7,15) + thv_c2327=(7,11) + thv_c2324=(7,8) + thv_c2323=(7,7) + thv_c2222=(6,6) + thv_c2131=(5,15) + thv_c2127=(5,11) + thv_c2124=(5,8) + thv_c2123=(5,7) + thv_c2122=(5,6) + thv_c2121=(5,5) + thv_c2031=(4,15) + thv_c2027=(4,11) + thv_c2024=(4,8) + thv_c2022=(4,6) + thv_c2021=(4,5) + thv_c2020=(4,4) + thv_c1921=(3,5) + thv_c1919=(3,3) + thv_c1821=(2,5) + thv_c1819=(2,3) + thv_c1818=(2,2) + thv_c1721=(1,5) + thv_c1719=(1,3) + thv_c1718=(1,2) + thv_c1717=(1,1) + thv_c1631=(0,15) + thv_c1627=(0,11) + thv_c1621=(0,5) + thv_c1620=(0,4) + thv_c1619=(0,3) + thv_c1618=(0,2) + thv_c1617=(0,1) + thv_c1616=(0,0) + thv_c1515=(31,31) + thv_c1415=(30,31) + thv_c1414=(30,30) + thv_c1313=(29,29) + thv_c1215=(28,31) + thv_c1212=(28,28) + thv_c1111=(27,27) + thv_c1011=(26,27) + thv_c1010=(26,26) + thv_c0911=(25,27) + thv_c0909=(25,25) + thv_c0811=(24,27) + thv_c0809=(24,25) + thv_c0808=(24,24) + thv_c0711=(23,27) + thv_c0709=(23,25) + thv_c0708=(23,24) + thv_c0707=(23,23) + thv_c0611=(22,27) + thv_c0607=(22,23) + thv_c0606=(22,22) + thv_c0508=(21,24) + thv_c0507=(21,23) + thv_c0506=(21,22) + thv_c0505=(21,21) + thv_c0431=(4,31) + thv_c0427=(4,27) + thv_c0411=(20,27) + thv_c0409=(20,25) + thv_c0407=(20,23) + thv_c0406=(20,22) + thv_c0405=(20,21) + thv_c0404=(20,20) + thv_c0303=(19,19) + thv_c0215=(18,31) + thv_c0202=(18,18) + thv_c0101=(17,17) + thv_c0104=(17,20) + thv_c0031=(0,31) + thv_c0027=(0,27) + thv_c0015=(16,31) + thv_c0011=(16,27) + thv_c0010=(16,26) + thv_c0008=(16,24) + thv_c0007=(16,23) + thv_c0006=(16,22) + thv_c0004=(16,20) + thv_c0003=(16,19) + thv_c0001=(16,17) + thv_c0000=(16,16) + thv_option=(16,19) + +@else # ENDIAN == "big" + + # Advanced SIMD and VFP instruction fields for 32-bit Big Endian Thumb + thv_D22=(22,22) + thv_N7=(7,7) + thv_L7=(7,7) + thv_Q6=(6,6) + thv_M5=(5,5) + thv_Qn0=(16,19) + thv_Qd0=(12,15) + thv_Qm0=(0,3) + thv_Qn1=(16,19) + thv_Qd1=(12,15) + thv_Qm1=(0,3) + thv_Dn0=(16,19) + thv_Dd0=(12,15) + thv_Dd_1=(12,15) + thv_Dd_2=(12,15) + thv_Dd_3=(12,15) + thv_Dd_4=(12,15) + thv_Dd_5=(12,15) + thv_Dd_6=(12,15) + thv_Dd_7=(12,15) + thv_Dd_8=(12,15) + thv_Dd_9=(12,15) + thv_Dd_10=(12,15) + thv_Dd_11=(12,15) + thv_Dd_12=(12,15) + thv_Dd_13=(12,15) + thv_Dd_14=(12,15) + thv_Dd_15=(12,15) + thv_Dd_16=(12,15) + thv_Dm0=(0,3) + thv_Dn1=(16,19) + thv_Dd1=(12,15) + thv_Dm1=(0,3) + thv_Dm_3=(0,2) + thv_Dm_4=(0,3) + thv_Sn0=(16,19) + thv_Sd0=(12,15) + thv_Sm0=(0,3) + thv_Sm0next=(0,3) + thv_Sn1=(16,19) + thv_Sd1=(12,15) + thv_Sm1=(0,3) + thv_Sm1next=(0,3) + thv_Sm0_3=(0,2) + thv_Sm1_3=(0,2) + thv_cmode=(8,11) + + thv_Rd=(12,15) + thv_Rt=(12,15) + thv_Rn=(16,19) + thv_Rm=(0,3) + thv_Rt2=(8,11) + thv_immed=(0,7) + + # Arbitrary bit fields for 32-bit Big Endian Thumb + thv_bit31=(31,31) + thv_bit30=(30,30) + thv_bit29=(29,29) + thv_bit28=(28,28) + thv_bit23=(23,23) + thv_bit21=(21,21) + thv_bit20=(20,20) + thv_bit07=(7,7) + thv_bit06=(6,6) + thv_bit00=(0,0) + thv_c2931=(29,31) + thv_c2831=(28,31) + thv_c2828=(28,28) + thv_c2627=(26,27) + thv_c2531=(25,31) + thv_c2527=(25,27) + thv_c2525=(25,25) + thv_c2427=(24,27) + thv_c2424=(24,24) + thv_c2331=(23,31) + thv_c2327=(23,27) + thv_c2324=(23,24) + thv_c2323=(23,23) + thv_c2222=(22,22) + thv_c2131=(21,31) + thv_c2127=(21,27) + thv_c2124=(21,24) + thv_c2123=(21,23) + thv_c2122=(21,22) + thv_c2121=(21,21) + thv_c2031=(20,31) + thv_c2027=(20,27) + thv_c2024=(20,24) + thv_c2022=(20,22) + thv_c2021=(20,21) + thv_c2020=(20,20) + thv_c1921=(19,21) + thv_c1919=(19,19) + thv_c1821=(18,21) + thv_c1819=(18,19) + thv_c1818=(18,18) + thv_c1721=(17,21) + thv_c1719=(17,19) + thv_c1718=(17,18) + thv_c1717=(17,17) + thv_c1631=(16,31) + thv_c1627=(16,27) + thv_c1621=(16,21) + thv_c1620=(16,20) + thv_c1619=(16,19) + thv_c1618=(16,18) + thv_c1617=(16,17) + thv_c1616=(16,16) + thv_c1515=(15,15) + thv_c1415=(14,15) + thv_c1414=(14,14) + thv_c1313=(13,13) + thv_c1215=(12,15) + thv_c1212=(12,12) + thv_c1111=(11,11) + thv_c1011=(10,11) + thv_c1010=(10,10) + thv_c0911=(9,11) + thv_c0909=(9,9) + thv_c0811=(8,11) + thv_c0809=(8,9) + thv_c0808=(8,8) + thv_c0711=(7,11) + thv_c0709=(7,9) + thv_c0708=(7,8) + thv_c0707=(7,7) + thv_c0611=(6,11) + thv_c0607=(6,7) + thv_c0606=(6,6) + thv_c0508=(5,8) + thv_c0507=(5,7) + thv_c0506=(5,6) + thv_c0505=(5,5) + thv_c0431=(4,31) + thv_c0427=(4,27) + thv_c0411=(4,11) + thv_c0409=(4,9) + thv_c0407=(4,7) + thv_c0406=(4,6) + thv_c0405=(4,5) + thv_c0404=(4,4) + thv_c0303=(3,3) + thv_c0215=(2,15) + thv_c0202=(2,2) + thv_c0101=(1,1) + thv_c0104=(1,4) + thv_c0031=(0,31) + thv_c0027=(0,27) + thv_c0015=(0,15) + thv_c0011=(0,11) + thv_c0010=(0,10) + thv_c0008=(0,8) + thv_c0007=(0,7) + thv_c0006=(0,6) + thv_c0004=(0,4) + thv_c0003=(0,3) + thv_c0001=(0,1) + thv_c0000=(0,0) + thv_option=(0,3) + +@endif # ENDIAN = "big" + +; + +attach variables [ Rn Rd Rs Rm RdHi RdLo smRd smRn smRm smRa RmHi RnLo ] [ r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 sp lr pc ]; +attach variables [ Rd2 Rm2 ] [ r1 _ r3 _ r5 _ r7 _ r9 _ r11 _ sp _ _ _ ]; # see LDREXD +attach variables [ CRd CRn CRm ] [ cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 cr8 cr9 cr10 cr11 cr12 cr13 cr14 cr15 ]; +attach variables [ thv_Rd thv_Rn thv_Rt thv_Rt2 ] [ r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 sp lr pc ]; + +attach names [ cpn ] [ p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 ]; +attach names [ ibOption ] [ opt0 opt1 opt2 opt3 opt4 opt5 opt6 opt7 opt8 opt9 opt10 opt11 opt12 opt13 opt14 SY ]; +attach names [ dbOption ] [ opt0 opt1 OSHST OSH opt4 opt5 NSHST NSH opt8 opt9 ISHST ISH opt12 opt13 ST SY ]; + +macro addflags(op1,op2) { + tmpCY = carry(op1,op2); + tmpOV = scarry(op1,op2); +} + +# NOTE: unlike x86, carry flag is SET if there is NO borrow +macro subflags(op1,op2) { + tmpCY = op2 <= op1; + tmpOV = sborrow(op1,op2); +} + +macro logicflags() { + tmpCY = shift_carry; + tmpOV = OV; +} + +macro CVunaffected() { + tmpCY = CY; + tmpOV = OV; +} + +macro resultflags(result) { + tmpNG = result s< 0; + tmpZR = result == 0; +} + +rn: pc is pc & c1619=15 { tmp:4 = inst_start+8; export tmp; } +rn: Rn is Rn { export Rn; } + +rm: pc is pc & Rm=15 { tmp:4 = inst_start+8; export tmp; } +rm: Rm is Rm { export Rm; } + +rs: pc is pc & Rs=15 { tmp:4 = inst_start+8; export tmp; } +rs: Rs is Rs { export Rs; } + +cc: "eq" is cond=0 { export ZR; } +cc: "ne" is cond=1 { tmp:1 = !ZR; export tmp; } +cc: "cs" is cond=2 { export CY; } +cc: "cc" is cond=3 { tmp:1 = !CY; export tmp; } +cc: "mi" is cond=4 { export NG; } +cc: "pl" is cond=5 { tmp:1 = !NG; export tmp; } +cc: "vs" is cond=6 { export OV; } +cc: "vc" is cond=7 { tmp:1 = !OV; export tmp; } +cc: "hi" is cond=8 { tmp:1 = CY && (!ZR); export tmp; } +cc: "ls" is cond=9 { tmp:1 = (!CY) || ZR; export tmp; } +cc: "ge" is cond=10 { tmp:1 = (NG==OV); export tmp; } +cc: "lt" is cond=11 { tmp:1 = (NG!=OV); export tmp; } +cc: "gt" is cond=12 { tmp:1 = (!ZR) && (NG==OV); export tmp; } +cc: "le" is cond=13 { tmp:1 = ZR || (NG!=OV); export tmp; } + +COND: cc is $(AMODE) & cc { if (!cc) goto inst_next; } # Execute conditionally +COND: is $(AMODE) & cond=14 { } # Always execute +#COND: is $(AMODE) & cond=15 { } # Always execute - deprecated, should not be used. + +@if defined(INCLUDE_NEON) # Unconditional Neon Thumb instructions share many Conditional Neon ARM constructors +COND: ItCond is TMode=1 & thv_c2831=14 & cond & ItCond { } # ItCond execute +#COND: ItCond is TMode=1 & thv_c2831=15 & cond & ItCond { } # ItCond execute +@endif + +SBIT_CZNO: is S20=0 { } # Do nothing to the flag bits +SBIT_CZNO: "s" is S20=1 { CY = tmpCY; ZR = tmpZR; NG = tmpNG; OV = tmpOV; } +SBIT_ZN: is S20=0 { } # Do nothing to the flag bits +SBIT_ZN: "s" is S20=1 { ZR = tmpZR; NG = tmpNG; } + +Addr24: reloc is addr24 [ reloc = (inst_next+4) + (4*addr24); ] { export *[ram]:4 reloc; } + +# see blx(1) instruction +@if defined(T_VARIANT) && defined(VERSION_5) + +HAddr24: reloc is addr24 & H24 + [ reloc = ((inst_next+4) + (4*addr24) + (2*H24)) & 0xFFFFFFFF; TMode=1; globalset(reloc,TMode); ] + { export *[ram]:4 reloc; } +@endif # T_VARIANT && VERSION_5 + +@if defined(VERSION_5E) + +XBIT: "b" is x=0 & smRn { local tmpRn = smRn; tmp:2 = tmpRn:2; export tmp; } +XBIT: "t" is x=1 & smRn { local tmpRn = smRn; tmp:2 = tmpRn(2); export tmp; } + +YBIT: "b" is y=0 & smRm { local tmpRm = smRm; tmp:2 = tmpRm:2; export tmp; } +YBIT: "t" is y=1 & smRm { local tmpRm = smRm; tmp:2 = tmpRm(2); export tmp; } + +@endif # VERSION_5E + + + +##################### +###### shift1 ###### +##################### + +shift1_old: "#"^value is I25=1 & immed & rotate + [ value=((immed<<(32-rotate*2))|(immed>>(rotate*2))) $and 0xffffffff; ] +{ + local tmp:4 = (value >> 31); shift_carry = ((rotate == 0:1) && CY) || ((rotate != 0:1) && tmp(0)); export *[const]:4 value; +} + +#################### +define pcodeop coproc_moveto_Main_ID; +define pcodeop coproc_moveto_Cache_Type; +define pcodeop coproc_moveto_TCM_Status; +define pcodeop coproc_moveto_TLB_Type; +define pcodeop coproc_moveto_Control; +define pcodeop coproc_moveto_Auxiliary_Control; +define pcodeop coproc_moveto_Coprocessor_Access_Control; +define pcodeop coproc_moveto_Secure_Configuration; +define pcodeop coproc_moveto_Secure_Debug_Enable; +define pcodeop coproc_moveto_NonSecure_Access_Control; +define pcodeop coproc_moveto_Translation_table_base_0; +define pcodeop coproc_moveto_Translation_table_base_1; +define pcodeop coproc_moveto_Translation_table_control; +define pcodeop coproc_moveto_Domain_Access_Control; +define pcodeop coproc_moveto_Data_Fault_Status; +define pcodeop coproc_moveto_Instruction_Fault_Status; +define pcodeop coproc_moveto_Instruction_Fault_Address; +define pcodeop coproc_moveto_Fault_Address; +define pcodeop coproc_moveto_Instruction_Fault; +define pcodeop coproc_moveto_Wait_for_interrupt; +define pcodeop coproc_moveto_Invalidate_Entire_Instruction; +define pcodeop coproc_moveto_Invalidate_Instruction_Cache_by_MVA; +define pcodeop coproc_moveto_Flush_Prefetch_Buffer; +define pcodeop coproc_moveto_Invalidate_Entire_Data_cache; +define pcodeop coproc_moveto_Invalidate_Entire_Data_by_MVA; +define pcodeop coproc_moveto_Invalidate_Entire_Data_by_Index; +define pcodeop coproc_moveto_Clean_Entire_Data_Cache; +define pcodeop coproc_moveto_Clean_Data_Cache_by_MVA; +define pcodeop coproc_moveto_Clean_Data_Cache_by_Index; +define pcodeop coproc_moveto_Data_Synchronization; +define pcodeop coproc_moveto_Data_Memory_Barrier; +define pcodeop coproc_moveto_Invalidate_Entire_Data_Cache; +define pcodeop coproc_moveto_Invalidate_Data_Cache_by_MVA; +define pcodeop coproc_moveto_Invalidate_unified_TLB_unlocked; +define pcodeop coproc_moveto_Invalidate_unified_TLB_by_MVA; +define pcodeop coproc_moveto_Invalidate_unified_TLB_by_ASID_match; +define pcodeop coproc_moveto_FCSE_PID; +define pcodeop coproc_moveto_Context_ID; +define pcodeop coproc_moveto_User_RW_Thread_and_Process_ID; +define pcodeop coproc_moveto_User_R_Thread_and_Process_ID; +define pcodeop coproc_moveto_Privileged_only_Thread_and_Process_ID; +define pcodeop coproc_moveto_Peripherial_Port_Memory_Remap; +define pcodeop coproc_moveto_Feature_Identification; +define pcodeop coproc_moveto_ISA_Feature_Identification; +define pcodeop coproc_moveto_Peripheral_Port_Memory_Remap; +define pcodeop coproc_moveto_Control_registers; +define pcodeop coproc_moveto_Security_world_control; +define pcodeop coproc_moveto_Translation_table; +define pcodeop coproc_moveto_Instruction_cache; +define pcodeop coproc_moveto_Data_cache_operations; +define pcodeop coproc_moveto_Identification_registers; +define pcodeop coproc_moveto_Peripheral_System; + +define pcodeop coproc_movefrom_Main_ID; +define pcodeop coproc_movefrom_Cache_Type; +define pcodeop coproc_movefrom_TCM_Status; +define pcodeop coproc_movefrom_TLB_Type; +define pcodeop coproc_movefrom_Control; +define pcodeop coproc_movefrom_Auxiliary_Control; +define pcodeop coproc_movefrom_Coprocessor_Access_Control; +define pcodeop coproc_movefrom_Secure_Configuration; +define pcodeop coproc_movefrom_Secure_Debug_Enable; +define pcodeop coproc_movefrom_NonSecure_Access_Control; +define pcodeop coproc_movefrom_Translation_table_base_0; +define pcodeop coproc_movefrom_Translation_table_base_1; +define pcodeop coproc_movefrom_Translation_table_control; +define pcodeop coproc_movefrom_Domain_Access_Control; +define pcodeop coproc_movefrom_Data_Fault_Status; +define pcodeop coproc_movefrom_Instruction_Fault; +define pcodeop coproc_movefrom_Fault_Address; +define pcodeop coproc_movefrom_Instruction_Fault_Status; +define pcodeop coproc_movefrom_Instruction_Fault_Address; +define pcodeop coproc_movefrom_Wait_for_interrupt; +define pcodeop coproc_movefrom_Invalidate_Entire_Instruction; +define pcodeop coproc_movefrom_Invalidate_Instruction_Cache_by_MVA; +define pcodeop coproc_movefrom_Flush_Prefetch_Buffer; +define pcodeop coproc_movefrom_Invalidate_Entire_Data_cache; +define pcodeop coproc_movefrom_Invalidate_Entire_Data_by_MVA; +define pcodeop coproc_movefrom_Invalidate_Entire_Data_by_Index; +define pcodeop coproc_movefrom_Clean_Entire_Data_Cache; +define pcodeop coproc_movefrom_Clean_Data_Cache_by_MVA; +define pcodeop coproc_movefrom_Clean_Data_Cache_by_Index; +define pcodeop coproc_movefrom_Data_Synchronization; +define pcodeop coproc_movefrom_Data_Memory_Barrier; +define pcodeop coproc_movefrom_Invalidate_Entire_Data_Cache; +define pcodeop coproc_movefrom_Invalidate_Data_Cache_by_MVA; +define pcodeop coproc_movefrom_Invalidate_unified_TLB_unlocked; +define pcodeop coproc_movefrom_Invalidate_unified_TLB_by_MVA; +define pcodeop coproc_movefrom_Invalidate_unified_TLB_by_ASID_match; +define pcodeop coproc_movefrom_FCSE_PID; +define pcodeop coproc_movefrom_Context_ID; +define pcodeop coproc_movefrom_User_RW_Thread_and_Process_ID; +define pcodeop coproc_movefrom_User_R_Thread_and_Process_ID; +define pcodeop coproc_movefrom_Privileged_only_Thread_and_Process_ID; +define pcodeop coproc_movefrom_Peripherial_Port_Memory_Remap; +define pcodeop coproc_movefrom_Feature_Identification; +define pcodeop coproc_movefrom_ISA_Feature_Identification; +define pcodeop coproc_movefrom_Peripheral_Port_Memory_Remap; +define pcodeop coproc_movefrom_Control_registers; +define pcodeop coproc_movefrom_Security_world_control; +define pcodeop coproc_movefrom_Translation_table; +define pcodeop coproc_movefrom_Instruction_cache; +define pcodeop coproc_movefrom_Data_cache_operations; +define pcodeop coproc_movefrom_Identification_registers; +define pcodeop coproc_movefrom_Peripheral_System; + +mcrOperands: cpn,opc1,Rd,CRn,CRm,opc2 is CRm & opc2 & cpn & CRn & opc1 & Rd { } + +##################### +###### shift2 ###### +##################### + +shift2: rm is I25=0 & sftimm=0 & c0406=0 & rm +{ + shift_carry = CY; export rm; +} + +shift2: rm, "lsl #"^sftimm is I25=0 & sftimm & c0406=0 & rm +{ + local tmp1=(rm>>(32-sftimm))&1; shift_carry=tmp1(0); local tmp2=rm<>31); shift_carry=tmp1(0); tmp2:4=0; export tmp2; +} + +shift2: rm, "lsr #"^sftimm is I25=0 & sftimm & c0406=2 & rm +{ + local tmp1=(rm>>(sftimm-1))&1; shift_carry=tmp1(0); local tmp2=rm>>sftimm; export tmp2; +} + +shift2: rm, "asr #32" is I25=0 & sftimm=0 & c0406=4 & rm +{ + local tmp1=(rm>>31); shift_carry=tmp1(0); local tmp2 = rm s>> 32; export tmp2; +} + +shift2: rm, "asr #"^sftimm is I25=0 & sftimm & c0406=4 & rm +{ + local tmp1=(rm>>(sftimm-1))&1; shift_carry=tmp1(0); local tmp2=rm s>> sftimm; export tmp2; +} + +shift2: rm, "rrx" is I25=0 & c0411=6 & rm +{ + local tmp1=rm&1; shift_carry=tmp1(0); local tmp2 = (zext(CY)<<31)|(rm>>1); export tmp2; +} + +shift2: rm, "ror #"^sftimm is I25=0 & sftimm & c0406=6 & rm +{ + local tmp1=(rm>>sftimm)|(rm<<(32-sftimm)); local tmp2=(tmp1>>31)&1; shift_carry=tmp2(0); export tmp1; +} + +##################### +###### shift3 ###### +##################### + +shift3: rm, "lsl "^rs is I25=0 & rs & c0407=1 & rm +{ + local sa=rs&0xff; local tmp1=(rm>>(32-sa))&1; shift_carry=((sa==0:4)&&CY) || ((sa!=0:4)&&tmp1(0)); local tmp2=rm<>(sa-1))&1; shift_carry=((sa==0:4)&&CY) || ((sa!=0:4)&&tmp1(0)); local tmp2=rm>>sa; export tmp2; +} + +shift3: rm, "asr "^rs is I25=0 & rs & c0407=5 & rm +{ + local sa=rs&0xff; local tmp1=(rm s>>(sa-1))&1; shift_carry=((sa==0:4)&&CY) || ((sa!=0:4)&&tmp1(0)); local tmp2=rm s>> sa; export tmp2; +} + +shift3: rm, "ror "^rs is I25=0 & rs & c0407=7 & rm +{ + local sa=rs&0x1f; local tmp1=(rm>>sa)|(rm<<(32-sa)); local tmp2=tmp1>>31; shift_carry=(((rs&0xff)==0:4)&&CY) || (((rs&0xff)!=0:4)&&tmp2(0)); export tmp1; +} + +shift1: shift1_old is I25=1 & shift1_old { export shift1_old; } +shift1: shift2 is I25=0 & (c0406=0 | c0406=2 | c0406=4 | c0406=6 | c0411=6) & shift2 { export shift2; } +shift1: shift3 is I25=0 & (c0407=1 | c0407=3 | c0407=5 | c0407=7) & shift3 { export shift3; } + +##################### +###### shift4 ###### +##################### +@if defined(VERSION_6) + +shift4: rm is sftimm=0 & sh=0 & rm +{ + shift_carry = CY; export rm; +} + +shift4: rm, "lsl #"^sftimm is sftimm & sh=0 & rm +{ + local tmp1=(rm>>(32-sftimm))&1; shift_carry=tmp1(0); local tmp2=rm<>31); shift_carry=tmp1(0); local tmp2 = rm s>> 32; export tmp2; +} + +shift4: rm, "asr #"^sftimm is sftimm & sh=1 & rm +{ + local tmp1=(rm>>(sftimm-1))&1; shift_carry=tmp1(0); local tmp2=rm s>> sftimm; export tmp2; +} + +@endif # VERSION_6 + +##################### +###### ror1 ###### +##################### +@if defined(VERSION_6) + +ror1: rm is c1011=0 & rm +{ + local tmp = rm; + export tmp; +} + +ror1: rm, "ror #8" is c1011=1 & rm +{ + local tmp = (rm <<24)| (rm >> 8); + export tmp; +} + +ror1: rm, "ror #16" is c1011=2 & rm +{ + local tmp = (rm << 16) | (rm >> 16); + export tmp; +} + +ror1: rm, "ror #24" is c1011=3 & rm +{ + local tmp = (rm << 8) | (rm >> 24); + export tmp; +} + +@endif # VERSION_6 + +##################### +# addrmode2 is the resulting address for Addressing Mode 2 +# it takes care of bits 27-0, except for the B and L flags and the Rd register +# the Rn register is taken care of including any possible write-back +# it returns a varnode containing the address +##################### + +# addr2shift is the register rm shifting portion of Addressing Mode 2 +addr2shift: rm is c0411=0 & rm { export rm; } +addr2shift: rm,"lsl #"^sftimm is sftimm & shft=0 & c0404=0 & rm { local tmp = rm << sftimm; export tmp; } +addr2shift: rm,"lsr #"^sftimm is sftimm & shft=1 & c0404=0 & rm { local tmp = rm >> sftimm; export tmp; } +addr2shift: rm,"lsr #32" is sftimm=0 & shft=1 & c0404=0 & rm { tmp:4 = 0; export tmp; } +addr2shift: rm,"asr #"^sftimm is sftimm & shft=2 & c0404=0 & rm { local tmp = rm s>> sftimm; export tmp; } +addr2shift: rm,"asr #32" is sftimm=0 & shft=2 & c0404=0 & rm { local tmp = rm s>> 32; export tmp; } +addr2shift: rm,"ror #"^sftimm is sftimm & shft=3 & c0404=0 & rm { local tmp = (rm>>sftimm) | (rm<<(32-sftimm)); export tmp; } +addr2shift: rm,"rrx" is sftimm=0 & shft=3 & c0404=0 & rm { tmp:4 = zext(CY); tmp = (tmp<<31) | (rm>>1); export tmp; } + + # no writeback + +addrmode2: [reloff] is I25=0 & P24=1 & U23=1 & W21=0 & c1619=15 & offset_12 + [ reloff = inst_start + 8 + offset_12; ] +{ + export *[const]:4 reloff; +} + +addrmode2: [reloff] is I25=0 & P24=1 & U23=0 & W21=0 & c1619=15 & offset_12 + [ reloff = inst_start + 8 - offset_12; ] +{ + export *[const]:4 reloff; +} + +addrmode2: [rn,"#"^offset_12] is I25=0 & P24=1 & U23=1 & W21=0 & rn & offset_12 { local tmp = rn + offset_12; export tmp; } +addrmode2: [rn,"#"^noff] is I25=0 & P24=1 & U23=0 & W21=0 & rn & offset_12 [ noff = -offset_12; ] { local tmp = rn + noff; export tmp; } +addrmode2: [rn,addr2shift] is I25=1 & P24=1 & U23=1 & W21=0 & rn & addr2shift { local tmp = rn + addr2shift; export tmp; } +addrmode2: [rn,-addr2shift] is I25=1 & P24=1 & U23=0 & W21=0 & rn & addr2shift { local tmp = rn - addr2shift; export tmp; } + # pre-indexed writeback +addrmode2: [rn,"#"^offset_12]! is I25=0 & P24=1 & U23=1 & W21=1 & rn & offset_12 { rn = rn + offset_12; export rn; } +addrmode2: [rn,"#"^noff]! is I25=0 & P24=1 & U23=0 & W21=1 & rn & offset_12 [ noff = -offset_12; ] { rn = rn + noff; export rn; } +addrmode2: [rn,addr2shift]! is I25=1 & P24=1 & U23=1 & W21=1 & rn & addr2shift { rn = rn + addr2shift; export rn; } +addrmode2: [rn,-addr2shift]! is I25=1 & P24=1 & U23=0 & W21=1 & rn & addr2shift { rn = rn - addr2shift; export rn; } + # post-indexed writeback +addrmode2: [rn],"#"^offset_12 is I25=0 & P24=0 & U23=1 & W21=0 & rn & offset_12 { local tmp = rn; rn = rn + offset_12; export tmp; } +addrmode2: [rn],"#"^noff is I25=0 & P24=0 & U23=0 & W21=0 & rn & offset_12 [ noff = -offset_12; ] { local tmp = rn; rn = rn + noff; export tmp; } +addrmode2: [rn],addr2shift is I25=1 & P24=0 & U23=1 & W21=0 & rn & addr2shift { local tmp = rn; rn = rn + addr2shift; export tmp; } +addrmode2: [rn],-addr2shift is I25=1 & P24=0 & U23=0 & W21=0 & rn & addr2shift { local tmp = rn; rn = rn - addr2shift; export tmp; } + # special-form post-indexed writeback for ldrbt, ldrt, strbt, etc. +addrmode2: [rn],"#"^offset_12 is I25=0 & P24=0 & U23=1 & W21=1 & rn & offset_12 { local tmp = rn; rn = rn + offset_12; export tmp; } +addrmode2: [rn],"#"^noff is I25=0 & P24=0 & U23=0 & W21=1 & rn & offset_12 [ noff = -offset_12; ] { local tmp = rn; rn = rn + noff; export tmp; } +addrmode2: [rn],addr2shift is I25=1 & P24=0 & U23=1 & W21=1 & rn & addr2shift { local tmp = rn; rn = rn + addr2shift; export tmp; } +addrmode2: [rn],-addr2shift is I25=1 & P24=0 & U23=0 & W21=1 & rn & addr2shift { local tmp = rn; rn = rn - addr2shift; export tmp; } + +########################### +# addrmode3 is the resulting address for Addressing Mode 3 +# it takes care of bits 27-0, except for the L, S, and H flags and the Rd register +# the Rn register is taken care of including any possible write-back +# it returns a varnode containing the address +########################### + +addrmode3: [reloff] is P24=1 & U23=1 & c2122=2 & c1619=15 & immedH & immedL + [ reloff=inst_start+8+((immedH<<4) | immedL);] +{ + export *:4 reloff; +} + +addrmode3: [reloff] is P24=1 & U23=0 & c2122=2 & c1619=15 & immedH & immedL + [ reloff=inst_start+8-((immedH<<4) | immedL);] +{ + export *:4 reloff; +} + +addrmode3: [rn,"#"^off8] is P24=1 & U23=1 & c2122=2 & rn & immedH & immedL + [ off8=(immedH<<4)|immedL;] +{ + local tmp = rn + off8; export tmp; +} + +addrmode3: [rn,"#"^noff8] is P24=1 & U23=0 & c2122=2 & rn & immedH & immedL + [ noff8=-((immedH<<4)|immedL);] +{ + local tmp = rn + noff8; export tmp; +} + +addrmode3: [rn,rm] is P24=1 & U23=1 & c2122=0 & rn & c0811=0 & rm +{ + local tmp = rn + rm; export tmp; +} + +addrmode3: [rn,-rm] is P24=1 & U23=0 & c2122=0 & rn & c0811=0 & rm +{ + local tmp = rn - rm; export tmp; +} + +addrmode3: [rn,"#"^off8]! is P24=1 & U23=1 & c2122=3 & rn & immedH & immedL + [ off8=(immedH<<4)|immedL;] +{ + rn=rn + off8; export rn; +} + +addrmode3: [rn,"#"^noff8]! is P24=1 & U23=0 & c2122=3 & rn & immedH & immedL + [ noff8=-((immedH<<4)|immedL);] +{ + rn=rn + noff8; export rn; +} + +addrmode3: [rn,rm]! is P24=1 & U23=1 & c2122=1 & rn & c0811=0 & rm +{ + rn = rn+rm; export rn; +} + +addrmode3: [rn,-rm]! is P24=1 & U23=0 & c2122=1 & rn & c0811=0 & rm +{ + rn = rn - rm; export rn; +} + +addrmode3: [rn],"#"^off8 is P24=0 & U23=1 & c2222=1 & rn & immedH & immedL + [ off8=(immedH<<4)|immedL;] +{ + local tmp=rn; rn=rn + off8; export tmp; +} + +addrmode3: [rn],"#"^noff8 is P24=0 & U23=0 & c2222=1 & rn & immedH & immedL + [ noff8=-((immedH<<4)|immedL);] +{ + local tmp=rn; rn=rn + noff8; export tmp; +} + +addrmode3: [rn],rm is P24=0 & U23=1 & c2222=0 & rn & c0811=0 & rm +{ + local tmp=rn; rn=rn+rm; export tmp; +} + +addrmode3: [rn],-rm is P24=0 & U23=0 & c2222=0 & rn & c0811=0 & rm +{ + local tmp=rn; rn=rn-rm; export tmp; +} + +############################ +# Addressing Mode 4. These 4 types take care of the register_list argument in Addressing Mode 4. +############################ + + +# ldlist_inc is the list of registers to be loaded using IA or IB in Addressing Mode 4 +linc15: r0 is c0000=1 & r0 { r0 = * mult_addr; mult_addr = mult_addr + 4; } +linc15: is c0000=0 { } +linc14: linc15,r1 is c0101=1 & linc15 & r1 { r1 = * mult_addr; mult_addr = mult_addr + 4; } +linc14: r1 is c0101=1 & c0000=0 & r1 { r1 = * mult_addr; mult_addr = mult_addr + 4; } +linc14: linc15 is c0101=0 & linc15 { } +linc13: linc14,r2 is c0202=1 & linc14 & r2 { r2 = * mult_addr; mult_addr = mult_addr + 4; } +linc13: r2 is c0202=1 & c0001=0 & r2 { r2 = * mult_addr; mult_addr = mult_addr + 4; } +linc13: linc14 is c0202=0 & linc14 { } +linc12: linc13,r3 is c0303=1 & linc13 & r3 { r3 = * mult_addr; mult_addr = mult_addr + 4; } +linc12: r3 is c0303=1 & c0002=0 & r3 { r3 = * mult_addr; mult_addr = mult_addr + 4; } +linc12: linc13 is c0303=0 & linc13 { } +linc11: linc12,r4 is c0404=1 & linc12 & r4 { r4 = * mult_addr; mult_addr = mult_addr + 4; } +linc11: r4 is c0404=1 & c0003=0 & r4 { r4 = * mult_addr; mult_addr = mult_addr + 4; } +linc11: linc12 is c0404=0 & linc12 { } +linc10: linc11,r5 is c0505=1 & linc11 & r5 { r5 = * mult_addr; mult_addr = mult_addr + 4; } +linc10: r5 is c0505=1 & c0004=0 & r5 { r5 = * mult_addr; mult_addr = mult_addr + 4; } +linc10: linc11 is c0505=0 & linc11 { } +linc9: linc10,r6 is c0606=1 & linc10 & r6 { r6 = * mult_addr; mult_addr = mult_addr + 4; } +linc9: r6 is c0606=1 & c0005=0 & r6 { r6 = * mult_addr; mult_addr = mult_addr + 4; } +linc9: linc10 is c0606=0 & linc10 { } +linc8: linc9,r7 is c0707=1 & linc9 & r7 { r7 = * mult_addr; mult_addr = mult_addr + 4; } +linc8: r7 is c0707=1 & c0006=0 & r7 { r7 = * mult_addr; mult_addr = mult_addr + 4; } +linc8: linc9 is c0707=0 & linc9 { } +linc7: linc8,r8 is c0808=1 & linc8 & r8 { r8 = * mult_addr; mult_addr = mult_addr + 4; } +linc7: r8 is c0808=1 & c0007=0 & r8 { r8 = * mult_addr; mult_addr = mult_addr + 4; } +linc7: linc8 is c0808=0 & linc8 { } +linc6: linc7,r9 is c0909=1 & linc7 & r9 { r9 = * mult_addr; mult_addr = mult_addr + 4; } +linc6: r9 is c0909=1 & c0008=0 & r9 { r9 = * mult_addr; mult_addr = mult_addr + 4; } +linc6: linc7 is c0909=0 & linc7 { } +linc5: linc6,r10 is c1010=1 & linc6 & r10 { r10 = * mult_addr; mult_addr = mult_addr + 4; } +linc5: r10 is c1010=1 & c0009=0 & r10 { r10 = * mult_addr; mult_addr = mult_addr + 4; } +linc5: linc6 is c1010=0 & linc6 { } +linc4: linc5,r11 is c1111=1 & linc5 & r11 { r11 = * mult_addr; mult_addr = mult_addr + 4; } +linc4: r11 is c1111=1 & c0010=0 & r11 { r11 = * mult_addr; mult_addr = mult_addr + 4; } +linc4: linc5 is c1111=0 & linc5 { } +linc3: linc4,r12 is c1212=1 & linc4 & r12 { r12 = * mult_addr; mult_addr = mult_addr + 4; } +linc3: r12 is c1212=1 & c0011=0 & r12 { r12 = * mult_addr; mult_addr = mult_addr + 4; } +linc3: linc4 is c1212=0 & linc4 { } +linc2: linc3,sp is c1313=1 & linc3 & sp { sp = * mult_addr; mult_addr = mult_addr + 4; } +linc2: sp is c1313=1 & c0012=0 & sp { sp = * mult_addr; mult_addr = mult_addr + 4; } +linc2: linc3 is c1313=0 & linc3 { } +linc1: linc2,lr is c1414=1 & linc2 & lr { lr = * mult_addr; mult_addr = mult_addr + 4; } +linc1: lr is c1414=1 & c0013=0 & lr { lr = * mult_addr; mult_addr = mult_addr + 4; } +linc1: linc2 is c1414=0 & linc2 { } +linc0: linc1,pc is c1515=1 & linc1 & pc { pc = * mult_addr; mult_addr = mult_addr + 4; } +linc0: pc is c1515=1 & c0014=0 & pc { pc = * mult_addr; mult_addr = mult_addr + 4; } +linc0: linc1 is c1515=0 & linc1 { } +ldlist_inc: {linc0} is linc0 { } + +# stlist_inc is the list of registers to be stored using IA or IB in Addressing Mode 4 +sinc15: r0 is c0000=1 & r0 { * mult_addr = r0; mult_addr = mult_addr + 4; } +sinc15: is c0000=0 { } +sinc14: sinc15,r1 is c0101=1 & sinc15 & r1 { * mult_addr = r1; mult_addr = mult_addr + 4; } +sinc14: r1 is c0101=1 & c0000=0 & r1 { * mult_addr = r1; mult_addr = mult_addr + 4; } +sinc14: sinc15 is c0101=0 & sinc15 { } +sinc13: sinc14,r2 is c0202=1 & sinc14 & r2 { * mult_addr = r2; mult_addr = mult_addr + 4; } +sinc13: r2 is c0202=1 & c0001=0 & r2 { * mult_addr = r2; mult_addr = mult_addr + 4; } +sinc13: sinc14 is c0202=0 & sinc14 { } +sinc12: sinc13,r3 is c0303=1 & sinc13 & r3 { * mult_addr = r3; mult_addr = mult_addr + 4; } +sinc12: r3 is c0303=1 & c0002=0 & r3 { * mult_addr = r3; mult_addr = mult_addr + 4; } +sinc12: sinc13 is c0303=0 & sinc13 { } +sinc11: sinc12,r4 is c0404=1 & sinc12 & r4 { * mult_addr = r4; mult_addr = mult_addr + 4; } +sinc11: r4 is c0404=1 & c0003=0 & r4 { * mult_addr = r4; mult_addr = mult_addr + 4; } +sinc11: sinc12 is c0404=0 & sinc12 { } +sinc10: sinc11,r5 is c0505=1 & sinc11 & r5 { * mult_addr = r5; mult_addr = mult_addr + 4; } +sinc10: r5 is c0505=1 & c0004=0 & r5 { * mult_addr = r5; mult_addr = mult_addr + 4; } +sinc10: sinc11 is c0505=0 & sinc11 { } +sinc9: sinc10,r6 is c0606=1 & sinc10 & r6 { * mult_addr = r6; mult_addr = mult_addr + 4; } +sinc9: r6 is c0606=1 & c0005=0 & r6 { * mult_addr = r6; mult_addr = mult_addr + 4; } +sinc9: sinc10 is c0606=0 & sinc10 { } +sinc8: sinc9,r7 is c0707=1 & sinc9 & r7 { * mult_addr = r7; mult_addr = mult_addr + 4; } +sinc8: r7 is c0707=1 & c0006=0 & r7 { * mult_addr = r7; mult_addr = mult_addr + 4; } +sinc8: sinc9 is c0707=0 & sinc9 { } +sinc7: sinc8,r8 is c0808=1 & sinc8 & r8 { * mult_addr = r8; mult_addr = mult_addr + 4; } +sinc7: r8 is c0808=1 & c0007=0 & r8 { * mult_addr = r8; mult_addr = mult_addr + 4; } +sinc7: sinc8 is c0808=0 & sinc8 { } +sinc6: sinc7,r9 is c0909=1 & sinc7 & r9 { * mult_addr = r9; mult_addr = mult_addr + 4; } +sinc6: r9 is c0909=1 & c0008=0 & r9 { * mult_addr = r9; mult_addr = mult_addr + 4; } +sinc6: sinc7 is c0909=0 & sinc7 { } +sinc5: sinc6,r10 is c1010=1 & sinc6 & r10 { * mult_addr = r10; mult_addr = mult_addr + 4; } +sinc5: r10 is c1010=1 & c0009=0 & r10 { * mult_addr = r10; mult_addr = mult_addr + 4; } +sinc5: sinc6 is c1010=0 & sinc6 { } +sinc4: sinc5,r11 is c1111=1 & sinc5 & r11 { * mult_addr = r11; mult_addr = mult_addr + 4; } +sinc4: r11 is c1111=1 & c0010=0 & r11 { * mult_addr = r11; mult_addr = mult_addr + 4; } +sinc4: sinc5 is c1111=0 & sinc5 { } +sinc3: sinc4,r12 is c1212=1 & sinc4 & r12 { * mult_addr = r12; mult_addr = mult_addr + 4; } +sinc3: r12 is c1212=1 & c0011=0 & r12 { * mult_addr = r12; mult_addr = mult_addr + 4; } +sinc3: sinc4 is c1212=0 & sinc4 { } +sinc2: sinc3,sp is c1313=1 & sinc3 & sp { * mult_addr = sp; mult_addr = mult_addr + 4; } +sinc2: sp is c1313=1 & c0012=0 & sp { * mult_addr = sp; mult_addr = mult_addr + 4; } +sinc2: sinc3 is c1313=0 & sinc3 { } +sinc1: sinc2,lr is c1414=1 & sinc2 & lr { * mult_addr = lr; mult_addr = mult_addr + 4; } +sinc1: lr is c1414=1 & c0013=0 & lr { * mult_addr = lr; mult_addr = mult_addr + 4; } +sinc1: sinc2 is c1414=0 & sinc2 { } +sinc0: sinc1,pc is c1515=1 & sinc1 & pc { *:4 mult_addr = (inst_start + 8); mult_addr = mult_addr + 4; } +sinc0: pc is c1515=1 & c0014=0 & pc { *:4 mult_addr = (inst_start + 8); mult_addr = mult_addr + 4; } +sinc0: sinc1 is c1515=0 & sinc1 { } +stlist_inc: {sinc0} is sinc0 { } + + +# ldlist_dec is the list of registers to be loaded using DA or DB in Addressing Mode 4 +ldec15: pc is c1515=1 & pc { pc = * mult_addr; mult_addr = mult_addr - 4; } +ldec15: is c1515=0 { } +ldec14: lr,ldec15 is c1414=1 & ldec15 & lr { lr = * mult_addr; mult_addr = mult_addr - 4; } +ldec14: lr is c1414=1 & c1515=0 & lr { lr = * mult_addr; mult_addr = mult_addr - 4; } +ldec14: ldec15 is c1414=0 & ldec15 { } +ldec13: sp,ldec14 is c1313=1 & ldec14 & sp { sp = * mult_addr; mult_addr = mult_addr - 4; } +ldec13: sp is c1313=1 & c1415=0 & sp { sp = * mult_addr; mult_addr = mult_addr - 4; } +ldec13: ldec14 is c1313=0 & ldec14 { } +ldec12: r12,ldec13 is c1212=1 & ldec13 & r12 { r12 = * mult_addr; mult_addr = mult_addr - 4; } +ldec12: r12 is c1212=1 & c1315=0 & r12 { r12 = * mult_addr; mult_addr = mult_addr - 4; } +ldec12: ldec13 is c1212=0 & ldec13 { } +ldec11: r11,ldec12 is c1111=1 & ldec12 & r11 { r11 = * mult_addr; mult_addr = mult_addr - 4; } +ldec11: r11 is c1111=1 & c1215=0 & r11 { r11 = * mult_addr; mult_addr = mult_addr - 4; } +ldec11: ldec12 is c1111=0 & ldec12 { } +ldec10: r10,ldec11 is c1010=1 & ldec11 & r10 { r10 = * mult_addr; mult_addr = mult_addr - 4; } +ldec10: r10 is c1010=1 & c1115=0 & r10 { r10 = * mult_addr; mult_addr = mult_addr - 4; } +ldec10: ldec11 is c1010=0 & ldec11 { } +ldec9: r9,ldec10 is c0909=1 & ldec10 & r9 { r9 = * mult_addr; mult_addr = mult_addr - 4; } +ldec9: r9 is c0909=1 & c1015=0 & r9 { r9 = * mult_addr; mult_addr = mult_addr - 4; } +ldec9: ldec10 is c0909=0 & ldec10 { } +ldec8: r8,ldec9 is c0808=1 & ldec9 & r8 { r8 = * mult_addr; mult_addr = mult_addr - 4; } +ldec8: r8 is c0808=1 & c0915=0 & r8 { r8 = * mult_addr; mult_addr = mult_addr - 4; } +ldec8: ldec9 is c0808=0 & ldec9 { } +ldec7: r7,ldec8 is c0707=1 & ldec8 & r7 { r7 = * mult_addr; mult_addr = mult_addr - 4; } +ldec7: r7 is c0707=1 & c0815=0 & r7 { r7 = * mult_addr; mult_addr = mult_addr - 4; } +ldec7: ldec8 is c0707=0 & ldec8 { } +ldec6: r6,ldec7 is c0606=1 & ldec7 & r6 { r6 = * mult_addr; mult_addr = mult_addr - 4; } +ldec6: r6 is c0606=1 & c0715=0 & r6 { r6 = * mult_addr; mult_addr = mult_addr - 4; } +ldec6: ldec7 is c0606=0 & ldec7 { } +ldec5: r5,ldec6 is c0505=1 & ldec6 & r5 { r5 = * mult_addr; mult_addr = mult_addr - 4; } +ldec5: r5 is c0505=1 & c0615=0 & r5 { r5 = * mult_addr; mult_addr = mult_addr - 4; } +ldec5: ldec6 is c0505=0 & ldec6 { } +ldec4: r4,ldec5 is c0404=1 & ldec5 & r4 { r4 = * mult_addr; mult_addr = mult_addr - 4; } +ldec4: r4 is c0404=1 & c0515=0 & r4 { r4 = * mult_addr; mult_addr = mult_addr - 4; } +ldec4: ldec5 is c0404=0 & ldec5 { } +ldec3: r3,ldec4 is c0303=1 & ldec4 & r3 { r3 = * mult_addr; mult_addr = mult_addr - 4; } +ldec3: r3 is c0303=1 & c0415=0 & r3 { r3 = * mult_addr; mult_addr = mult_addr - 4; } +ldec3: ldec4 is c0303=0 & ldec4 { } +ldec2: r2,ldec3 is c0202=1 & ldec3 & r2 { r2 = * mult_addr; mult_addr = mult_addr - 4; } +ldec2: r2 is c0202=1 & c0315=0 & r2 { r2 = * mult_addr; mult_addr = mult_addr - 4; } +ldec2: ldec3 is c0202=0 & ldec3 { } +ldec1: r1,ldec2 is c0101=1 & ldec2 & r1 { r1 = * mult_addr; mult_addr = mult_addr - 4; } +ldec1: r1 is c0101=1 & c0215=0 & r1 { r1 = * mult_addr; mult_addr = mult_addr - 4; } +ldec1: ldec2 is c0101=0 & ldec2 { } +ldec0: r0,ldec1 is c0000=1 & ldec1 & r0 { r0 = * mult_addr; mult_addr = mult_addr - 4; } +ldec0: r0 is c0000=1 & c0115=0 & r0 { r0 = * mult_addr; mult_addr = mult_addr - 4; } +ldec0: ldec1 is c0000=0 & ldec1 { } +ldlist_dec: {ldec0} is ldec0 { } + +# stlist_dec is the list of registers to be stored using DA or DB in Addressing Mode 4 +sdec15: pc is c1515=1 & pc { *:4 mult_addr = (inst_start + 8); mult_addr = mult_addr - 4; } +sdec15: is c1515=0 { } +sdec14: lr,sdec15 is c1414=1 & sdec15 & lr { * mult_addr=lr; mult_addr = mult_addr - 4; } +sdec14: lr is c1414=1 & c1515=0 & lr { * mult_addr=lr; mult_addr = mult_addr - 4; } +sdec14: sdec15 is c1414=0 & sdec15 { } +sdec13: sp,sdec14 is c1313=1 & sdec14 & sp { * mult_addr=sp; mult_addr = mult_addr - 4; } +sdec13: sp is c1313=1 & c1415=0 & sp { * mult_addr=sp; mult_addr = mult_addr - 4; } +sdec13: sdec14 is c1313=0 & sdec14 { } +sdec12: r12,sdec13 is c1212=1 & sdec13 & r12 { * mult_addr=r12; mult_addr = mult_addr - 4; } +sdec12: r12 is c1212=1 & c1315=0 & r12 { * mult_addr=r12; mult_addr = mult_addr - 4; } +sdec12: sdec13 is c1212=0 & sdec13 { } +sdec11: r11,sdec12 is c1111=1 & sdec12 & r11 { * mult_addr=r11; mult_addr = mult_addr - 4; } +sdec11: r11 is c1111=1 & c1215=0 & r11 { * mult_addr=r11; mult_addr = mult_addr - 4; } +sdec11: sdec12 is c1111=0 & sdec12 { } +sdec10: r10,sdec11 is c1010=1 & sdec11 & r10 { * mult_addr=r10; mult_addr = mult_addr - 4; } +sdec10: r10 is c1010=1 & c1115=0 & r10 { * mult_addr=r10; mult_addr = mult_addr - 4; } +sdec10: sdec11 is c1010=0 & sdec11 { } +sdec9: r9,sdec10 is c0909=1 & sdec10 & r9 { * mult_addr=r9; mult_addr = mult_addr - 4; } +sdec9: r9 is c0909=1 & c1015=0 & r9 { * mult_addr=r9; mult_addr = mult_addr - 4; } +sdec9: sdec10 is c0909=0 & sdec10 { } +sdec8: r8,sdec9 is c0808=1 & sdec9 & r8 { * mult_addr=r8; mult_addr = mult_addr - 4; } +sdec8: r8 is c0808=1 & c0915=0 & r8 { * mult_addr=r8; mult_addr = mult_addr - 4; } +sdec8: sdec9 is c0808=0 & sdec9 { } +sdec7: r7,sdec8 is c0707=1 & sdec8 & r7 { * mult_addr=r7; mult_addr = mult_addr - 4; } +sdec7: r7 is c0707=1 & c0815=0 & r7 { * mult_addr=r7; mult_addr = mult_addr - 4; } +sdec7: sdec8 is c0707=0 & sdec8 { } +sdec6: r6,sdec7 is c0606=1 & sdec7 & r6 { * mult_addr=r6; mult_addr = mult_addr - 4; } +sdec6: r6 is c0606=1 & c0715=0 & r6 { * mult_addr=r6; mult_addr = mult_addr - 4; } +sdec6: sdec7 is c0606=0 & sdec7 { } +sdec5: r5,sdec6 is c0505=1 & sdec6 & r5 { * mult_addr=r5; mult_addr = mult_addr - 4; } +sdec5: r5 is c0505=1 & c0615=0 & r5 { * mult_addr=r5; mult_addr = mult_addr - 4; } +sdec5: sdec6 is c0505=0 & sdec6 { } +sdec4: r4,sdec5 is c0404=1 & sdec5 & r4 { * mult_addr=r4; mult_addr = mult_addr - 4; } +sdec4: r4 is c0404=1 & c0515=0 & r4 { * mult_addr=r4; mult_addr = mult_addr - 4; } +sdec4: sdec5 is c0404=0 & sdec5 { } +sdec3: r3,sdec4 is c0303=1 & sdec4 & r3 { * mult_addr=r3; mult_addr = mult_addr - 4; } +sdec3: r3 is c0303=1 & c0415=0 & r3 { * mult_addr=r3; mult_addr = mult_addr - 4; } +sdec3: sdec4 is c0303=0 & sdec4 { } +sdec2: r2,sdec3 is c0202=1 & sdec3 & r2 { * mult_addr=r2; mult_addr = mult_addr - 4; } +sdec2: r2 is c0202=1 & c0315=0 & r2 { * mult_addr=r2; mult_addr = mult_addr - 4; } +sdec2: sdec3 is c0202=0 & sdec3 { } +sdec1: r1,sdec2 is c0101=1 & sdec2 & r1 { * mult_addr=r1; mult_addr = mult_addr - 4; } +sdec1: r1 is c0101=1 & c0215=0 & r1 { * mult_addr=r1; mult_addr = mult_addr - 4; } +sdec1: sdec2 is c0101=0 & sdec2 { } +sdec0: r0,sdec1 is c0000=1 & sdec1 & r0 { * mult_addr=r0; mult_addr = mult_addr - 4; } +sdec0: r0 is c0000=1 & c0115=0 & r0 { * mult_addr=r0; mult_addr = mult_addr - 4; } +sdec0: sdec1 is c0000=0 & sdec1 { } + +stlist_dec: {sdec0} is sdec0 { } + +# reglist deals with Addressing Mode 4 +# it takes care of bits 0-27 +# we assume that alignment checking is turned on +reglist: rn,ldlist_inc is P24=0 & U23=1 & S22=0 & W21=0 & L20=1 & rn & ldlist_inc +{ + mult_addr=rn; build ldlist_inc; +} + +reglist: rn,ldlist_inc"^" is P24=0 & U23=1 & S22=1 & W21=0 & L20=1 & rn & ldlist_inc +{ + mult_addr=rn; build ldlist_inc; +} + +reglist: rn!,ldlist_inc is P24=0 & U23=1 & S22=0 & W21=1 & L20=1 & rn & ldlist_inc +{ + mult_addr=rn; build ldlist_inc; rn=mult_addr; +} + +reglist: rn!,ldlist_inc"^" is P24=0 & U23=1 & S22=1 & W21=1 & L20=1 & rn & ldlist_inc +{ + mult_addr=rn; build ldlist_inc; rn=mult_addr; +} + +reglist: rn,ldlist_inc is P24=1 & U23=1 & S22=0 & W21=0 & L20=1 & rn & ldlist_inc +{ + mult_addr=(rn+4); build ldlist_inc; +} + +reglist: rn,ldlist_inc"^" is P24=1 & U23=1 & S22=1 & W21=0 & L20=1 & rn & ldlist_inc +{ + mult_addr=(rn+4); build ldlist_inc; +} + +reglist: rn!,ldlist_inc is P24=1 & U23=1 & S22=0 & W21=1 & L20=1 & rn & ldlist_inc +{ + mult_addr=(rn+4); build ldlist_inc; rn=mult_addr-4; +} + +reglist: rn!,ldlist_inc"^" is P24=1 & U23=1 & S22=1 & W21=1 & L20=1 & rn & ldlist_inc +{ + mult_addr=(rn+4); build ldlist_inc; rn=mult_addr-4; +} + +reglist: rn,ldlist_dec is P24=0 & U23=0 & S22=0 & W21=0 & L20=1 & rn & ldlist_dec +{ + mult_addr=rn; build ldlist_dec; +} + +reglist: rn,ldlist_dec"^" is P24=0 & U23=0 & S22=1 & W21=0 & L20=1 & rn & ldlist_dec +{ + mult_addr=rn; build ldlist_dec; +} + +reglist: rn!,ldlist_dec is P24=0 & U23=0 & S22=0 & W21=1 & L20=1 & rn & ldlist_dec +{ + mult_addr=rn; build ldlist_dec; rn=mult_addr; +} + +reglist: rn!,ldlist_dec"^" is P24=0 & U23=0 & S22=1 & W21=1 & L20=1 & rn & ldlist_dec +{ + mult_addr=rn; build ldlist_dec; rn=mult_addr; +} + +reglist: rn,ldlist_dec is P24=1 & U23=0 & S22=0 & W21=0 & L20=1 & rn & ldlist_dec +{ + mult_addr=(rn-4); build ldlist_dec; +} + +reglist: rn,ldlist_dec"^" is P24=1 & U23=0 & S22=1 & W21=0 & L20=1 & rn & ldlist_dec +{ + mult_addr=(rn-4); build ldlist_dec; +} + +reglist: rn!,ldlist_dec is P24=1 & U23=0 & S22=0 & W21=1 & L20=1 & rn & ldlist_dec +{ + mult_addr=(rn-4); build ldlist_dec; rn=mult_addr+4; +} + +reglist: rn!,ldlist_dec"^" is P24=1 & U23=0 & S22=1 & W21=1 & L20=1 & rn & ldlist_dec +{ + mult_addr=(rn-4); build ldlist_dec; rn=mult_addr+4; +} + +reglist: rn,stlist_inc is P24=0 & U23=1 & S22=0 & W21=0 & L20=0 & rn & stlist_inc +{ + mult_addr=rn; build stlist_inc; +} + +reglist: rn,stlist_inc"^" is P24=0 & U23=1 & S22=1 & W21=0 & L20=0 & rn & stlist_inc +{ + mult_addr=rn; build stlist_inc; +} + +## This is here to allow old versions of this instruction to decode. +## The W-Bit21 is specified as (0) in the manual meaning should be 0 but is unpredictable if 1 +## Some older processors did not specify that Writeback was not available if the P24=0 and S22=0, +## which is a system interrupt instruction. +## I AM ASSUMING, that the W-bit is honored on these processors and does update the register!!!! +## This is probably an arbitrary decision, but keeps with what old processor did. +reglist: rn,stlist_inc"^" is P24=0 & U23=1 & S22=1 & W21=1 & L20=0 & rn & stlist_inc +{ + mult_addr=rn; build stlist_inc; rn=mult_addr; +} + + +reglist: rn!,stlist_inc is P24=0 & U23=1 & S22=0 & W21=1 & L20=0 & rn & stlist_inc +{ + mult_addr=rn; build stlist_inc; rn=mult_addr; +} + +reglist: rn,stlist_inc is P24=1 & U23=1 & S22=0 & W21=0 & L20=0 & rn & stlist_inc +{ + mult_addr=(rn+4); build stlist_inc; +} + +reglist: rn,stlist_inc"^" is P24=1 & U23=1 & S22=1 & W21=0 & L20=0 & rn & stlist_inc +{ + mult_addr=(rn+4); build stlist_inc; +} + +reglist: rn!,stlist_inc is P24=1 & U23=1 & S22=0 & W21=1 & L20=0 & rn & stlist_inc +{ + mult_addr=(rn+4); build stlist_inc; rn=mult_addr-4; +} + +reglist: rn,stlist_dec is P24=0 & U23=0 & S22=0 & W21=0 & L20=0 & rn & stlist_dec +{ + mult_addr=rn; build stlist_dec; +} + +reglist: rn,stlist_dec"^" is P24=0 & U23=0 & S22=1 & W21=0 & L20=0 & rn & stlist_dec +{ + mult_addr=rn; build stlist_dec; +} + +reglist: rn!,stlist_dec is P24=0 & U23=0 & S22=0 & W21=1 & L20=0 & rn & stlist_dec +{ + mult_addr=rn; build stlist_dec; rn=mult_addr; +} + +reglist: rn,stlist_dec is P24=1 & U23=0 & S22=0 & W21=0 & L20=0 & rn & stlist_dec +{ + mult_addr=(rn-4); build stlist_dec; +} + +reglist: rn,stlist_dec"^" is P24=1 & U23=0 & S22=1 & W21=0 & L20=0 & rn & stlist_dec +{ + mult_addr=(rn-4); build stlist_dec; +} + +reglist: rn!,stlist_dec is P24=1 & U23=0 & S22=0 & W21=1 & L20=0 & rn & stlist_dec +{ + mult_addr=(rn-4); build stlist_dec; rn=mult_addr+4; +} + +# mdir is for attaching the load/store multiple addressing mode mnemonic to the mnemonic +mdir: "ia" is P24=0 & U23=1 { } +mdir: "ib" is P24=1 & U23=1 { } +mdir: "da" is P24=0 & U23=0 { } +mdir: "db" is P24=1 & U23=0 { } + +# addrmode5 is the parameter in Addressing Mode5 +# it takes care of bits 27-0 except for the N and L flags and CRd and cp# +# it takes care of possible writebacks to Rn +addrmode5: [rn,"#"^off8] is P24=1 & U23=1 & W21=0 & rn & immed [ off8=immed*4; ] { local tmp = rn + off8; export tmp; } +addrmode5: [rn,"#"^noff8] is P24=1 & U23=0 & W21=0 & rn & immed [ noff8=-(immed*4); ] { local tmp = rn + noff8; export tmp; } +addrmode5: [rn,"#"^off8]! is P24=1 & U23=1 & W21=1 & rn & immed [ off8=immed*4; ] { rn = rn + off8; export rn; } +addrmode5: [rn,"#"^noff8]! is P24=1 & U23=0 & W21=1 & rn & immed [ noff8=-(immed*4); ] { rn = rn + noff8; export rn; } +addrmode5: [rn],"#"^off8 is P24=0 & U23=1 & W21=1 & rn & immed [ off8=immed*4; ] { local tmp = rn; rn = rn+off8; export tmp; } +addrmode5: [rn],"#"^noff8 is P24=0 & U23=0 & W21=1 & rn & immed [ noff8=-(immed*4); ] { local tmp = rn; rn = rn + noff8; export tmp; } +addrmode5: [rn],{immed} is P24=0 & U23=1 & W21=0 & rn & immed { export rn; } + +# cpsrmask is the resulting cpsr mask for the msr instruction + +cpsrmask: is mask=0 { export 0:4; } +cpsrmask: "cpsr_c" is mask=1 { export 0xff:4; } +cpsrmask: "cpsr_x" is mask=2 { export 0xff00:4; } +cpsrmask: "cpsr_cx" is mask=3 { export 0xffff:4; } +cpsrmask: "cpsr_s" is mask=4 { export 0xff0000:4; } +cpsrmask: "cpsr_cs" is mask=5 { export 0xff00ff:4; } +cpsrmask: "cpsr_xs" is mask=6 { export 0xffff00:4; } +cpsrmask: "cpsr_cxs" is mask=7 { export 0xffffff:4; } +cpsrmask: "cpsr_f" is mask=8 { export 0xff000000:4; } +cpsrmask: "cpsr_cf" is mask=9 { export 0xff0000ff:4; } +cpsrmask: "cpsr_xf" is mask=10 { export 0xff00ff00:4; } +cpsrmask: "cpsr_cxf" is mask=11 { export 0xff00ffff:4; } +cpsrmask: "cpsr_sf" is mask=12 { export 0xffff0000:4; } +cpsrmask: "cpsr_csf" is mask=13 { export 0xffff00ff:4; } +cpsrmask: "cpsr_xsf" is mask=14 { export 0xffffff00:4; } +cpsrmask: "cpsr_cxsf" is mask=15 { export 0xffffffff:4; } + +# spsrmask is the mask for spsr in the msr instruction + +spsrmask: is mask=0 { export 0:4; } +spsrmask: "spsr_c" is mask=1 { export 0xff:4; } +spsrmask: "spsr_x" is mask=2 { export 0xff00:4; } +spsrmask: "spsr_cx" is mask=3 { export 0xffff:4; } +spsrmask: "spsr_s" is mask=4 { export 0xff0000:4; } +spsrmask: "spsr_cs" is mask=5 { export 0xff00ff:4; } +spsrmask: "spsr_xs" is mask=6 { export 0xffff00:4; } +spsrmask: "spsr_cxs" is mask=7 { export 0xffffff:4; } +spsrmask: "spsr_f" is mask=8 { export 0xff000000:4; } +spsrmask: "spsr_cf" is mask=9 { export 0xff0000ff:4; } +spsrmask: "spsr_xf" is mask=10 { export 0xff00ff00:4; } +spsrmask: "spsr_cxf" is mask=11 { export 0xff00ffff:4; } +spsrmask: "spsr_sf" is mask=12 { export 0xffff0000:4; } +spsrmask: "spsr_csf" is mask=13 { export 0xffff00ff:4; } +spsrmask: "spsr_xsf" is mask=14 { export 0xffffff00:4; } +spsrmask: "spsr_cxsf" is mask=15 { export 0xffffffff:4; } + +##################### +###### immediate bit-number data for unsigned/signed saturated instructions +##################### +@if defined(VERSION_6) + +sSatImm5: "#"^satimm is satimm5 [ satimm = satimm5 + 1; ] { export *[const]:2 satimm; } +sSatImm4: "#"^satimm is satimm4 [ satimm = satimm4 + 1; ] { export *[const]:2 satimm; } +uSatImm5: "#"^satimm5 is satimm5 { export *[const]:2 satimm5; } +uSatImm4: "#"^satimm4 is satimm4 { export *[const]:2 satimm4; } + +@endif # VERSION_6 + +@if defined(VERSION_6K) || defined(VERSION_6T2) +optionImm: "#"^immed4 is immed4 { export *[const]:4 immed4; } +@endif + +@if defined(VERSION_6T2) || defined(VERSION_7) + +lsbImm: "#"^lsb is lsb { export *[const]:4 lsb; } +msbImm: "#"^msb is msb { export *[const]:4 msb; } +widthMinus1: "#"^width is msb [ width = msb + 1; ] { export *[const]:4 msb; } +bitWidth: "#"^w is lsb & msb [ w = msb - lsb + 1; ] { export *[const]:4 w; } + +@endif # VERSION_6T2 || VERSION_7 + +# +# Modes for SRS instructions +# +@if defined(VERSION_6) +SRSMode: "usr" is srsMode=8 & c0004 { export *[const]:1 c0004; } +SRSMode: "fiq" is srsMode=9 & c0004 { export *[const]:1 c0004; } +SRSMode: "irq" is srsMode=10 & c0004 { export *[const]:1 c0004; } +SRSMode: "svc" is srsMode=11 & c0004 { export *[const]:1 c0004; } +SRSMode: "mon" is srsMode=14 & c0004 { export *[const]:1 c0004; } +SRSMode: "abt" is srsMode=15 & c0004 { export *[const]:1 c0004; } +SRSMode: "und" is srsMode=19 & c0004 { export *[const]:1 c0004; } +SRSMode: "sys" is srsMode=23 & c0004 { export *[const]:1 c0004; } +SRSMode: "#"^srsMode is srsMode { export *[const]:1 srsMode; } +@endif # VERSION_6 + +# Perform ARMcond check phase and set ARMcond context variable +:^instruction is $(AMODE) & ARMcondCk=0 & (bit31=0|bit30=0|bit29=0|bit28=0) & instruction [ ARMcondCk=1; ARMcond=1; ] {} +:^instruction is ARMcondCk=0 & instruction [ ARMcondCk=1; ARMcond=0; ] {} + +# Ensure that the condition check phase has been completed +with : ARMcondCk=1 { + +################################################# +# +# Include the SIMD/VFP instructions before the +# other ARM instructions to avoid incorrect +# constructor matching for those that use the +# COND subconstructor. This also ensures +# that the various VFP instructions supersede the +# CDP/MCR/MRC general coprocessor instructions +# +################################################# +@if defined(INCLUDE_NEON) +@include "ARMneon.sinc" +@endif + +################################################# +# +# Do the same now for ARMv8, which also has neon +# +################################################# +@if defined(VERSION_8) +@include "ARMv8.sinc" +@endif # VERSION_8 + +################################################ +# +# These instructions must come first because the cond pattern match +# is more specific than the subconstructor COND. If a base intruction +# matches and then COND fails (cond=14 or cond=15) then the disassembly +# will fail +# +################################################ + +@if defined(VERSION_5) + +# Exception Generation and UDF + +# immed12_4 used in Exception Generation and Media instructions class + +immed12_4: "#"^tmp is $(AMODE) & immed12 & immed4 [tmp = (immed12 << 4) | immed4; ] { export *[const]:4 tmp; } + +:hlt immed12_4 is $(AMODE) & cond=0xe & c2027=0x10 & c0407=0x7 & immed12_4 +{ + software_hlt(immed12_4); +} + +:bkpt immed12_4 is $(AMODE) & cond=0xe & c2027=0x12 & c0407=0x7 & immed12_4 +{ + software_bkpt(immed12_4); +} + +:hvc immed12_4 is $(AMODE) & cond=0xe & c2027=0x14 & c0407=0x7 & immed12_4 +{ + software_hvc(immed12_4); +} + +@if defined(VERSION_6T2) || defined(VERSION_7) + +define pcodeop SG; + +:sg is TMode=1 & thv_c0031=0xe97fe97f +{ + SG(); +} +@endif + +# Requires Security Extensions +:smc^COND immed4 is $(AMODE) & COND & c2027=0x16 & c0407=0x7 & immed4 +{ + build COND; + software_smc(immed4:4); +} + +@if defined(VERSION_6T2) || defined(VERSION_7) +define pcodeop TT; + +:tt^ItCond thv_Rt2, thv_Rn is TMode=1 & ItCond & thv_c2031=0b111010000100 & thv_c1215=0b1111 & thv_bit07=0 & thv_bit06=0 & thv_Rt2 & thv_Rn +{ + thv_Rt2 = TT(thv_Rn); +} + +define pcodeop TTA; + +:tta^ItCond thv_Rt2, thv_Rn is TMode=1 & ItCond & thv_c2031=0b111010000100 & thv_c1215=0b1111 & thv_bit07=1 & thv_bit06=0 & thv_Rt2 & thv_Rn +{ + thv_Rt2 = TTA(thv_Rn); +} + +define pcodeop TTAT; + +:ttat^ItCond thv_Rt2, thv_Rn is TMode=1 & ItCond & thv_c2031=0b111010000100 & thv_c1215=0b1111 & thv_bit07=1 & thv_bit06=1 & thv_Rt2 & thv_Rn +{ + thv_Rt2 = TTAT(thv_Rn); +} + +define pcodeop TTT; + +:ttt^ItCond thv_Rt2, thv_Rn is TMode=1 & ItCond & thv_c2031=0b111010000100 & thv_c1215=0b1111 & thv_bit07=0 & thv_bit06=1 & thv_Rt2 & thv_Rn +{ + thv_Rt2 = TTT(thv_Rn); +} + +@endif + +:udf immed12_4 is $(AMODE) & cond=0xe & c2027=0x7f & c0407=0xf & immed12_4 +{ + local excaddr:4 = inst_start; + local target:4 = software_udf(immed12_4:4, excaddr); + goto [target]; +} + +@endif # VERSION_5 + +@if defined(VERSION_6) + +AFLAG: "a" is c0808=1 & c1819=2 { enableDataAbortInterrupts(); } +AFLAG: "a" is c0808=1 { disableDataAbortInterrupts(); } +AFLAG: is c0808=0 { } +IFLAG: "i" is c0707=1 & c1819=2 { enableIRQinterrupts(); } +IFLAG: "i" is c0707=1 { disableIRQinterrupts(); } +IFLAG: is c0707=0 { } +FFLAG: "f" is c0606=1 & c1819=2 { enableFIQinterrupts(); } +FFLAG: "f" is c0606=1 { disableFIQinterrupts(); } +FFLAG: is c0606=0 { } +IFLAGS: AFLAG^IFLAG^FFLAG is AFLAG & IFLAG & FFLAG { } + +SetMode: "#"^16 is c0004=0x10 { setUserMode(); } +SetMode: "#"^17 is c0004=0x11 { setFIQMode(); } +SetMode: "#"^18 is c0004=0x12 { setIRQMode(); } +SetMode: "#"^19 is c0004=0x13 { setSupervisorMode(); } +SetMode: "#"^22 is c0004=0x16 { setMonitorMode(); } +SetMode: "#"^23 is c0004=0x17 { setAbortMode(); } +SetMode: "#"^27 is c0004=0x1b { setUndefinedMode(); } +SetMode: "#"^31 is c0004=0x1f { setSystemMode(); } + +:cps SetMode is $(AMODE) & ARMcond=0 & cond=15 & c2027=16 & c1819=0 & c1717=1 & c0916=0 & c0508=0 & SetMode { } +:cpsie IFLAGS is $(AMODE) & ARMcond=0 & cond=15 & c2027=16 & c1819=2 & c1717=0 & c0916=0 & c0505=0 & c0004=0 & IFLAGS { } +:cpsid IFLAGS is $(AMODE) & ARMcond=0 & cond=15 & c2027=16 & c1819=3 & c1717=0 & c0916=0 & c0505=0 & c0004=0 & IFLAGS { } +:cpsie IFLAGS, SetMode is $(AMODE) & ARMcond=0 & cond=15 & c2027=16 & c1819=2 & c1717=1 & c0916=0 & c0505=0 & IFLAGS & SetMode { } +:cpsid IFLAGS, SetMode is $(AMODE) & ARMcond=0 & cond=15 & c2027=16 & c1819=3 & c1717=1 & c0916=0 & c0505=0 & IFLAGS & SetMode { } + +@endif # VERSION_6 + +@if defined(VERSION_5E) + +:pld addrmode2 is $(AMODE) & cond=0xf & c2627=1 & c2424=1 & c2022=5 & c1215=0xf & (I25=0 | (I25=1 & c0404=0)) & addrmode2 +{ + HintPreloadData(addrmode2); +} + +# prevent literal form getting matched by pldw +:pld addrmode2 is $(AMODE) & cond=0xf & c2627=1 & c2424=1 & c2022=5 & c1619=0xf & c1215=0xf & (I25=0 | (I25=1 & c0404=0)) & addrmode2 +{ + HintPreloadData(addrmode2); +} + +@endif # VERSION_5E + +@if defined(VERSION_7) + +:pldw addrmode2 is $(AMODE) & cond=0xf & c2627=1 & c2424=1 & c2022=1 & c1215=0xf & (I25=0 | (I25=1 & c0404=0)) & addrmode2 +{ + HintPreloadDataForWrite(addrmode2); +} + +:pli addrmode2 is $(AMODE) & cond=0xf & c2627=1 & c2424=0 & c2022=5 & c1215=0xf & (I25=0 | (I25=1 & c0404=0)) & addrmode2 +{ + HintPreloadInstruction(addrmode2); +} + +@endif # VERSION_7 + + +@if defined(VERSION_6) + +:rfeia rn is $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=0 & U23=1 & S22=0 & W21=0 & L20=1 & rn & c1215=0 & c0811=10 & c0007=0 +{ + # register list is always: pc, cpsr + ptr:4 = rn; + cpsr = *ptr; + ptr = ptr + 4; + pc = *ptr; + return [pc]; +} + +:rfeib rn is $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=1 & U23=1 & S22=0 & W21=0 & L20=1 & rn & c1215=0 & c0811=10 & c0007=0 +{ + # register list is always: pc, cpsr + ptr:4 = rn + 4; + cpsr = *ptr; + ptr = ptr + 4; + pc = *ptr; + return [pc]; +} + +:rfeda rn is $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=0 & U23=0 & S22=0 & W21=0 & L20=1 & rn & c1215=0 & c0811=10 & c0007=0 +{ + # register list is always: pc, cpsr + ptr:4 = rn; + cpsr = *ptr; + ptr = ptr - 4; + pc = *ptr; + return [pc]; +} + +:rfedb rn is $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=1 & U23=0 & S22=0 & W21=0 & L20=1 & rn & c1215=0 & c0811=10 & c0007=0 +{ + # register list is always: pc, cpsr + ptr:4 = rn - 4; + cpsr = *ptr; + ptr = ptr - 4; + pc = *ptr; + return [pc]; +} + +:rfeia Rn! is $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=0 & U23=1 & S22=0 & W21=1 & L20=1 & Rn & c1215=0 & c0811=10 & c0007=0 +{ + # register list is always: pc, cpsr + ptr:4 = Rn; + cpsr = *ptr; + ptr = ptr + 4; + pc = *ptr; + Rn = ptr + 4; + return [pc]; +} + +:rfeib Rn! is $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=1 & U23=1 & S22=0 & W21=1 & L20=1 & Rn & c1215=0 & c0811=10 & c0007=0 +{ + # register list is always: pc, cpsr + ptr:4 = Rn + 4; + cpsr = *ptr; + ptr = ptr + 4; + pc = *ptr; + Rn = ptr; + return [pc]; +} + +:rfeda Rn! is $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=0 & U23=0 & S22=0 & W21=1 & L20=1 & Rn & c1215=0 & c0811=10 & c0007=0 +{ + # register list is always: pc, cpsr + ptr:4 = Rn; + cpsr = *ptr; + ptr = ptr - 4; + pc = *ptr; + Rn = ptr - 4; + return [pc]; +} + +:rfedb Rn! is $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=1 & U23=0 & S22=0 & W21=1 & L20=1 & Rn & c1215=0 & c0811=10 & c0007=0 +{ + # register list is always: pc, cpsr + ptr:4 = Rn - 4; + cpsr = *ptr; + ptr = ptr - 4; + pc = *ptr; + Rn = ptr; + return [pc]; +} + +:srsia SRSMode is $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=0 & U23=1 & S22=1 & W21=0 & L20=0 & c1215=0 & c0811=5 & c0507=0 & SRSMode +{ + # register list is always: r14, spsr + ptr:4 = sp; + *ptr = lr; + ptr = ptr + 4; + *ptr = spsr; + ptr = ptr + 4; +} + +:srsib SRSMode is $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=1 & U23=1 & W21=0 & S22=1 & L20=0 & c1215=0 & c0811=5 & c0507=0 & SRSMode +{ + # register list is always: r14, spsr + ptr:4 = sp + 4; + *ptr = lr; + ptr = ptr + 4; + *ptr = spsr; +} + +:srsda SRSMode is $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=0 & U23=0 & W21=0 & S22=1 & L20=0 & c1215=0 & c0811=5 & c0507=0 & SRSMode +{ + # register list is always: r14, spsr + ptr:4 = sp; + *ptr = lr; + ptr = ptr - 4; + *ptr = spsr; + ptr = ptr - 4; +} + +:srsdb SRSMode is $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=1 & U23=0 & W21=0 & S22=1 & L20=0 & c1215=0 & c0811=5 & c0507=0 & SRSMode +{ + # register list is always: r14, spsr + ptr:4 = sp - 4; + *ptr = lr; + ptr = ptr - 4; + *ptr = spsr; +} + +:srsia SRSMode! is $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=0 & U23=1 & S22=1 & W21=1 & L20=0 & c1215=0 & c0811=5 & c0507=0 & SRSMode +{ + # register list is always: r14, spsr + ptr:4 = sp; + *ptr = lr; + ptr = ptr + 4; + *ptr = spsr; + ptr = ptr + 4; + sp = ptr; +} + +:srsib SRSMode! is $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=1 & U23=1 & W21=1 & S22=1 & L20=0 & c1215=0 & c0811=5 & c0507=0 & SRSMode +{ + # register list is always: r14, spsr + ptr:4 = sp + 4; + *ptr = lr; + ptr = ptr + 4; + *ptr = spsr; + sp = ptr; +} + +:srsda SRSMode! is $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=0 & U23=0 & W21=1 & S22=1 & L20=0 & c1215=0 & c0811=5 & c0507=0 & SRSMode +{ + # register list is always: r14, spsr + ptr:4 = sp; + *ptr = lr; + ptr = ptr - 4; + *ptr = spsr; + ptr = ptr - 4; + sp = ptr; +} + +:srsdb SRSMode! is $(AMODE) & ARMcond=0 & cond=15 & c2527=4 & P24=1 & U23=0 & W21=1 & S22=1 & L20=0 & c1215=0 & c0811=5 & c0507=0 & SRSMode +{ + # register list is always: r14, spsr + ptr:4 = sp; + ptr = ptr - 4; + *ptr = lr; + ptr = ptr - 4; + *ptr = spsr; + sp = ptr; +} + +@endif # VERSION_6 + +@if defined(VERSION_5) + +:stc2 cpn,CRd,addrmode5 is $(AMODE) & ARMcond=0 & cond=15 & c2527=6 & addrmode5 & cpn & CRd & N22=0 & L20=0 +{ + t_cpn:4 = cpn; + coprocessor_store2(t_cpn,CRd,addrmode5); +} + +:stc2l cpn,CRd,addrmode5 is $(AMODE) & ARMcond=0 & cond=15 & c2527=6 & addrmode5 & cpn & CRd & N22=1 & L20=0 +{ + t_cpn:4 = cpn; + coprocessor_storelong2(t_cpn,CRd,addrmode5); +} + +@endif # VERSION_5 + +################################################# +# +# Here are the rest of instructions in alphabetical order +# +################################################# + +#See ARM Architecture reference section "Pseudocode details of addition and subtraction" +macro add_with_carry_flags(op1,op2){ + local CYz = zext(CY); + local result = op1 + op2; + tmpCY = carry( op1, op2) || carry( result, CYz ); + tmpOV = scarry( op1, op2 ) ^^ scarry( result, CYz ); +} + +#Note: used for subtraction op1 - (op2 + !CY) +#sets tmpCY if there is NO borrow +macro sub_with_carry_flags(op1, op2){ + local result = op1 - op2; + tmpCY = (op1 > op2) || (result < zext(CY)); + tmpOV = sborrow(op1,op2) ^^ sborrow(result,zext(!CY)); +} + + +:adc^COND^SBIT_CZNO Rd,rn,shift1 is $(AMODE) & ARMcond=1 & COND & c2124=5 & SBIT_CZNO & rn & Rd & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + add_with_carry_flags(rn,shift1); + Rd = rn+shift1+zext(CY); + resultflags(Rd); + build SBIT_CZNO; +} + +:adc^COND^SBIT_CZNO Rd,rn,shift2 is $(AMODE) & ARMcond=1 & COND & c2124=5 & SBIT_CZNO & rn & Rd & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + add_with_carry_flags(rn,shift2); + Rd = rn+shift2+zext(CY); + resultflags(Rd); + build SBIT_CZNO; +} + +:adc^COND^SBIT_CZNO Rd,rn,shift3 is $(AMODE) & ARMcond=1 & COND & c2124=5 & SBIT_CZNO & rn & Rd & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + add_with_carry_flags(rn,shift3); + Rd = rn+shift3+zext(CY); + resultflags(Rd); + build SBIT_CZNO; +} + +:adc^COND^SBIT_CZNO pc,rn,shift1 is $(AMODE) & pc & ARMcond=1 & COND & c2124=5 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + add_with_carry_flags(rn,shift1); + dest:4 = rn + shift1 + zext(CY); + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +:adc^COND^SBIT_CZNO pc,rn,shift2 is $(AMODE) & pc & ARMcond=1 & COND & c2124=5 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + add_with_carry_flags(rn,shift2); + dest:4 = rn + shift2 + zext(CY); + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +:adc^COND^SBIT_CZNO pc,rn,shift3 is $(AMODE) & pc & ARMcond=1 & COND & c2124=5 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + add_with_carry_flags(rn,shift3); + dest:4 = rn + shift3 + zext(CY); + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +ArmPCRelImmed12: reloff is U23=1 & immed & rotate + [ reloff = inst_start + 8 + ( ((immed<<(32-rotate*2))|(immed>>(rotate*2))) $and 0xffffffff); ] +{ + export *[const]:4 reloff; +} + +ArmPCRelImmed12: reloff is U23=0 & immed & rotate + [ reloff = inst_start + 8 - ( ((immed<<(32-rotate*2))|(immed>>(rotate*2))) $and 0xffffffff); ] +{ + export *[const]:4 reloff; +} + +# +# ADR constructors must appear before ADD constructors to give ADR parsing precedence +# + +:adr^COND Rd,ArmPCRelImmed12 is $(AMODE) & ARMcond=1 & COND & c2527=1 & (c2024=8 | c2024=4) & Rn=15 & Rd & ArmPCRelImmed12 +{ + build COND; + Rd = ArmPCRelImmed12; +} + +:adr^COND pc,ArmPCRelImmed12 is $(AMODE) & ARMcond=1 & COND & c2527=1 & (c2024=8 | c2024=4) & Rn=15 & Rd=15 & pc & ArmPCRelImmed12 +{ + build COND; + dest:4 = ArmPCRelImmed12; + ALUWritePC(dest); + goto [pc]; +} + + +:add^COND^SBIT_CZNO Rd,rn,shift1 is $(AMODE) & ARMcond=1 & COND & c2124=4 & SBIT_CZNO & rn & Rd & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + addflags(rn,shift1); + Rd = rn + shift1; + resultflags(Rd); + build SBIT_CZNO; +} + +:add^COND^SBIT_CZNO Rd,rn,shift2 is $(AMODE) & ARMcond=1 & COND & c2124=4 & SBIT_CZNO & rn & Rd & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + addflags(rn,shift2); + Rd = rn + shift2; + resultflags(Rd); + build SBIT_CZNO; +} + +:add^COND^SBIT_CZNO Rd,rn,shift3 is $(AMODE) & ARMcond=1 & COND & c2124=4 & SBIT_CZNO & rn & Rd & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + addflags(rn,shift3); + Rd = rn + shift3; + resultflags(Rd); + build SBIT_CZNO; +} + +:add^COND^SBIT_CZNO pc,rn,shift1 is $(AMODE) & pc & ARMcond=1 & COND & c2124=4 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + addflags(rn,shift1); + dest:4 = rn + shift1; + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +:add^COND^SBIT_CZNO pc,rn,shift2 is $(AMODE) & pc & ARMcond=1 & COND & c2124=4 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + addflags(rn,shift2); + dest:4 = rn + shift2; + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +:add^COND^SBIT_CZNO pc,rn,shift3 is $(AMODE) & pc & ARMcond=1 & COND & c2124=4 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + addflags(rn,shift3); + dest:4 = rn + shift3; + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +:and^COND^SBIT_CZNO Rd,rn,shift1 is $(AMODE) & ARMcond=1 & COND & c2124=0 & SBIT_CZNO & rn & Rd & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + Rd = rn & shift1; + logicflags(); + resultflags(Rd); + build SBIT_CZNO; +} + +:and^COND^SBIT_CZNO Rd,rn,shift2 is $(AMODE) & ARMcond=1 & COND & c2124=0 & SBIT_CZNO & rn & Rd & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + Rd = rn & shift2; + logicflags(); + resultflags(Rd); + build SBIT_CZNO; +} + +:and^COND^SBIT_CZNO Rd,rn,shift3 is $(AMODE) & ARMcond=1 & COND & c2124=0 & SBIT_CZNO & rn & Rd & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + Rd = rn & shift3; + logicflags(); + resultflags(Rd); + build SBIT_CZNO; +} + +:and^COND^SBIT_CZNO pc,rn,shift1 is $(AMODE) & pc & ARMcond=1 & COND & c2124=0 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + dest:4 = rn & shift1; + logicflags(); + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +:and^COND^SBIT_CZNO pc,rn,shift2 is $(AMODE) & pc & ARMcond=1 & COND & c2124=0 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + dest:4 = rn & shift2; + logicflags(); + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +:and^COND^SBIT_CZNO pc,rn,shift3 is $(AMODE) & pc & ARMcond=1 & COND & c2124=0 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + dest:4 = rn & shift3; + logicflags(); + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +# must match first! before conditional goto + +:b Addr24 is $(AMODE) & cond=14 & c2527=5 & L24=0 & Addr24 +{ + goto Addr24; +} + +:b^cc Addr24 is $(AMODE) & cc & c2527=5 & L24=0 & Addr24 +{ + if (cc) goto Addr24; +} + + + +@if defined(VERSION_6T2) + +:bfc^COND Rd,lsbImm,bitWidth is $(AMODE) & ARMcond=1 & COND & c2127=0x3e & msbImm & Rd & lsbImm & bitWidth & c0006=0x1f { + build COND; + build lsbImm; + build msbImm; + build bitWidth; + clearMask:4 = (-1 << (msbImm + 1)) | (-1 >> (32 - lsbImm)); + Rd = Rd & clearMask; +} + +:bfi^COND Rd,Rm,lsbImm,bitWidth is $(AMODE) & ARMcond=1 & COND & c2127=0x3e & Rd & Rm & lsbImm & bitWidth & c0406=1 { + build COND; + build lsbImm; + build bitWidth; + vmask:4 = (1 << bitWidth) - 1; + clear:4 = ~(vmask << lsbImm); + bits:4 = (Rm & vmask) << lsbImm; + Rd = (Rd & clear) | bits; +} + +@endif # VERSION_6T2 + +:bic^COND^SBIT_CZNO Rd,rn,shift1 is $(AMODE) & ARMcond=1 & COND & c2124=14 & SBIT_CZNO & rn & Rd & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + Rd = rn&(~shift1); + logicflags(); + resultflags(Rd); + build SBIT_CZNO; +} + +:bic^COND^SBIT_CZNO Rd,rn,shift2 is $(AMODE) & ARMcond=1 & COND & c2124=14 & SBIT_CZNO & rn & Rd & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + Rd = rn&(~shift2); + logicflags(); + resultflags(Rd); + build SBIT_CZNO; +} + +:bic^COND^SBIT_CZNO Rd,rn,shift3 is $(AMODE) & ARMcond=1 & COND & c2124=14 & SBIT_CZNO & rn & Rd & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + Rd = rn&(~shift3); + logicflags(); + resultflags(Rd); + build SBIT_CZNO; +} + +:bic^COND^SBIT_CZNO pc,rn,shift1 is $(AMODE) & pc & ARMcond=1 & COND & c2124=14 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + dest:4 = rn&(~shift1); + logicflags(); + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +:bic^COND^SBIT_CZNO pc,rn,shift2 is $(AMODE) & pc & ARMcond=1 & COND & c2124=14 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + dest:4 = rn&(~shift2); + logicflags(); + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +:bic^COND^SBIT_CZNO pc,rn,shift3 is $(AMODE) & pc & ARMcond=1 & COND & c2124=14 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + dest:4 = rn&(~shift3); + logicflags(); + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +# bl used as a PIC instruction to get at current PC in lr +:bl Addr24 is $(AMODE) & cond=14 & c2527=5 & L24=1 & immed24=0xffffff & Addr24 +{ + lr = inst_next; + goto Addr24; +} + +# bl used as a PIC instruction to get at current PC in lr +:bl^COND Addr24 is $(AMODE) & ARMcond=1 & COND & c2527=5 & L24=1 & immed24=0xffffff & Addr24 +{ + build COND; + build Addr24; + lr = inst_next; + goto Addr24; +} + +:bl Addr24 is $(AMODE) & cond=14 & c2527=5 & L24=1 & Addr24 +{ + lr = inst_next; + call Addr24; +} + +:bl^COND Addr24 is $(AMODE) & CALLoverride=0 & COND & c2527=5 & L24=1 & Addr24 +{ + build COND; + build Addr24; + lr = inst_next; + call Addr24; +} + +:bl^COND Addr24 is $(AMODE) & CALLoverride=1 & COND & c2527=5 & L24=1 & Addr24 +{ + build COND; + build Addr24; + lr = inst_next; + goto Addr24; +} + +# blx(1) instruction +@if defined(T_VARIANT) && defined(VERSION_5) + +# Two forms of blx needed to distinguish from b +:blx HAddr24 is $(AMODE) & CALLoverride=0 & ARMcond=0 & cond=15 & c2527=5 & H24=0 & HAddr24 +{ + lr = inst_next; + SetThumbMode(1); + call HAddr24; + # don't do causes decompiler trouble TB = 0; +} # Always changes to THUMB mode + +:blx HAddr24 is $(AMODE) & CALLoverride=1 & ARMcond=0 & cond=15 & c2527=5 & H24=0 & HAddr24 +{ + lr = inst_next; + SetThumbMode(1); + goto HAddr24; +} # Always changes to THUMB mode + + +:blx HAddr24 is $(AMODE) & ARMcond=0 & CALLoverride=0 & cond=15 & c2527=5 & H24=1 & HAddr24 +{ + lr = inst_next; + SetThumbMode(1); + call HAddr24; + # don't do causes decompiler trouble TB = 0; +} # Always changes to THUMB mode + +:blx HAddr24 is $(AMODE) & ARMcond=0 & CALLoverride=1 & cond=15 & c2527=5 & H24=1 & HAddr24 +{ + lr = inst_next; + SetThumbMode(1); + goto HAddr24; +} # Always changes to THUMB mode + +@endif # T_VARIANT && VERSION_5 + +@if defined(VERSION_5) + +:blx^COND rm is $(AMODE) & ARMcond=1 & COND & c2027=18 & c1619=15 & c1215=15 & c0811=15 & c0407=3 & rm +{ + build COND; + build rm; + BXWritePC(rm); + lr=inst_next; + call [pc]; +# don't do causes decompiler trouble TB = 0; +} # Optional THUMB + +:blx^COND rm is $(AMODE) & CALLoverride=1 & ARMcond=1 & COND & c2027=18 & c1619=15 & c1215=15 & c0811=15 & c0407=3 & rm +{ + build COND; + build rm; + BXWritePC(rm); + lr=inst_next; + goto [pc]; +} # Optional THUMB + +@endif # VERSION_5 + +@if defined(VERSION_5_or_T) + +# if branching using lr, assume return +:bx^COND rm is $(AMODE) & REToverride=0 & LRset=0 & ARMcond=1 & COND & c2027=18 & c1619=15 & c1215=15 & c0811=15 & c0407=1 & rm & Rm=14 +{ + build COND; + build rm; + BXWritePC(rm); + return [pc]; +} # Optional change to THUMB + +:bx^COND rm is $(AMODE) & REToverride=0 & LRset=0 & ARMcond=1 & COND & c2027=18 & c1619=15 & c1215=15 & c0811=15 & c0407=1 & rm & Rm +{ + build COND; + build rm; + BXWritePC(rm); + goto [pc]; +} # Optional change to THUMB + +# if lr has just been set, assume call +:bx^COND rm is $(AMODE) & REToverride=0 & LRset=1 & ARMcond=1 & COND & c2027=18 & c1619=15 & c1215=15 & c0811=15 & c0407=1 & rm & Rm +{ + build COND; + build rm; + BXWritePC(rm); + call [pc]; +} # Optional change to THUMB + +:bx^COND rm is $(AMODE) & REToverride=1 & ARMcond=1 & COND & c2027=18 & c1619=15 & c1215=15 & c0811=15 & c0407=1 & rm +{ + build COND; + build rm; + BXWritePC(rm); + goto [pc]; +} # Optional change to THUMB + +#:bx^COND lr is $(AMODE) & ARMcond=1 & COND & c2027=18 & c1619=15 & c1215=15 & c0811=15 & c0407=1 & Rm=14 & lr +#{ +# build COND; +# TB=(lr&0x00000001)!=0; +# tmp = lr & 0xfffffffe; +# return [tmp]; +#} # Optional change to THUMB + +@endif # VERSION_5_or_T + +@if defined(VERSION_6) + +# bxj behaves like bx except that Jazelle state is enabled if available (added with Version-5 J-variant) + +:bxj^COND rm is $(AMODE) & REToverride=0 & ARMcond=1 & COND & c2027=18 & c1619=15 & c1215=15 & c0811=15 & c0407=2 & rm +{ + build COND; + build rm; + success:1 = jazelle_branch(); + if (success) goto ; + BXWritePC(rm); + return [pc]; + +} # Optional change to THUMB + +# if branching using "ip" then is a goto +:bxj^COND rm is $(AMODE) & REToverride=0 & ARMcond=1 & COND & c2027=18 & c1619=15 & c1215=15 & c0811=15 & c0407=2 & rm & Rm=12 +{ + build COND; + build rm; + success:1 = jazelle_branch(); + if (success) goto ; + BXWritePC(rm); + goto [pc]; + +} # Optional change to THUMB + +:bxj^COND rm is $(AMODE) & REToverride=1 & ARMcond=1 & COND & c2027=18 & c1619=15 & c1215=15 & c0811=15 & c0407=2 & rm +{ + build COND; + build rm; + success:1 = jazelle_branch(); + if (success) goto ; + BXWritePC(rm); + goto [pc]; + +} # Optional change to THUMB + +@endif # VERSION_6 + +@if defined(VERSION_5) + +:cdp2 cpn,opcode1,CRd,CRn,CRm,opcode2 is $(AMODE) & ARMcond=0 & cond=15 & c2427=14 & opcode1 & CRn & CRd & cpn & opcode2 & c0404=0 & CRm +{ + t_cpn:4 = cpn; + t_op1:4 = opcode1; + t_op2:4 = opcode2; + coprocessor_function2(t_cpn,t_op1,t_op2,CRd,CRn,CRm); +} + +@endif # VERSION_5 + +:cdp^COND cpn,opcode1,CRd,CRn,CRm,opcode2 is $(AMODE) & ARMcond=1 & COND & c2427=14 & opcode1 & CRn & CRd & cpn & opcode2 & c0404=0 & CRm +{ + build COND; + t_cpn:4 = cpn; + t_op1:4 = opcode1; + t_op2:4 = opcode2; + coprocessor_function(t_cpn,t_op1,t_op2,CRd,CRn,CRm); +} + +@if defined(VERSION_6K) || defined(VERSION_7) + +:clrex is $(AMODE) & c0031=0xf57ff01f { + ClearExclusiveLocal(); +} + +@endif # VERSION_6K + +@if defined(VERSION_5) + +:clz^COND Rd,rm is $(AMODE) & ARMcond=1 & COND & c2027=22 & c1619=15 & Rd & c0811=15 & c0407=1 & rm +{ + build COND; + build rm; + Rd = lzcount(rm); +} + +@endif # VERSION_5 + +:cmn^COND rn,shift1 is $(AMODE) & ARMcond=1 & COND & c2024=23 & rn & c1215=0 & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + addflags(rn,shift1); + local tmp = rn + shift1; + resultflags(tmp); + affectflags(); +} + +:cmn^COND rn,shift2 is $(AMODE) & ARMcond=1 & COND & c2024=23 & rn & c1215=0 & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + addflags(rn,shift2); + local tmp = rn + shift2; + resultflags(tmp); + affectflags(); +} + +:cmn^COND rn,shift3 is $(AMODE) & ARMcond=1 & COND & c2024=23 & rn & c1215=0 & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + addflags(rn,shift3); + local tmp = rn + shift3; + resultflags(tmp); + affectflags(); +} + +:cmp^COND rn,shift1 is $(AMODE) & ARMcond=1 & COND & c2024=21 & rn & c1215=0 & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + subflags(rn,shift1); + local tmp = rn - shift1; + resultflags(tmp); + affectflags(); +} + +:cmp^COND rn,shift2 is $(AMODE) & ARMcond=1 & COND & c2024=21 & rn & c1215=0 & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + subflags(rn,shift2); + local tmp = rn - shift2; + resultflags(tmp); + affectflags(); +} + +:cmp^COND rn,shift3 is $(AMODE) & ARMcond=1 & COND & c2024=21 & rn & c1215=0 & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + subflags(rn,shift3); + local tmp = rn - shift3; + resultflags(tmp); + affectflags(); +} + +@if defined(VERSION_6) + +# cpy is a pre-UAL synonym for mov +:cpy^COND pc,rm is $(AMODE) & ARMcond=1 & COND & pc & c2027=0x1a & c1619=0 & c0411=0 & Rd=15 & rm +{ + build COND; + build rm; + BXWritePC(rm); + goto [pc]; +} + +:cpy^COND lr,rm is $(AMODE) & ARMcond=1 & COND & c2027=0x1a & c1619=0 & c0411=0 & Rd=14 & lr & rm & Rm2=15 + [ LRset=1; globalset(inst_next,LRset); ] +{ + build COND; + lr = rm; +} + +:cpy^COND Rd,rm is $(AMODE) & ARMcond=1 & COND & c2027=0x1a & c1619=0 & c0411=0 & Rd & rm +{ + build COND; + build rm; + Rd = rm; +} + +@endif # VERSION_6 + +@if defined(VERSION_6K) || defined(VERSION_6T2) + +:dbg^COND optionImm is $(AMODE) & ARMcond=1 & COND & c0427=0x320f0f & optionImm { +@if defined(VERSION_7) + build COND; + build optionImm; + HintDebug(optionImm); +@endif # VERSION_7 +} + +@endif # VERSION_6K || VERSION_6T2 + +@if defined(VERSION_7) + + + +:dmb dbOption is $(AMODE) & c0431=0xf57ff05 & dbOption { + DataMemoryBarrier(dbOption:1); +} + +:dsb dbOption is $(AMODE) & c0431=0xf57ff04 & dbOption { + DataSynchronizationBarrier(dbOption:1); +} + +@endif # VERSION_7 + +:eor^COND^SBIT_CZNO Rd,rn,shift1 is $(AMODE) & ARMcond=1 & COND & c2124=1 & SBIT_CZNO & rn & Rd & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + Rd = rn^shift1; + logicflags(); + resultflags(Rd); + build SBIT_CZNO; +} + +:eor^COND^SBIT_CZNO Rd,rn,shift2 is $(AMODE) & ARMcond=1 & COND & c2124=1 & SBIT_CZNO & rn & Rd & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + Rd = rn^shift2; + logicflags(); + resultflags(Rd); + build SBIT_CZNO; +} + +:eor^COND^SBIT_CZNO Rd,rn,shift3 is $(AMODE) & ARMcond=1 & COND & c2124=1 & SBIT_CZNO & rn & Rd & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + Rd = rn^shift3; + logicflags(); + resultflags(Rd); + build SBIT_CZNO; +} + +:eor^COND^SBIT_CZNO pc,rn,shift1 is $(AMODE) & pc & ARMcond=1 & COND & c2124=1 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + dest:4 = rn^shift1; + logicflags(); + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +:eor^COND^SBIT_CZNO pc,rn,shift2 is $(AMODE) & pc & ARMcond=1 & COND & c2124=1 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + dest:4 = rn^shift2; + logicflags(); + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +:eor^COND^SBIT_CZNO pc,rn,shift3 is $(AMODE) & pc & ARMcond=1 & COND & c2124=1 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + dest:4 = rn^shift3; + logicflags(); + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +@if defined(VERSION_7) + + +:isb ibOption is $(AMODE) & c0431=0xf57ff06 & ibOption { + InstructionSynchronizationBarrier(ibOption:1); +} + +@endif # VERSION_7 + +### These must come first, because of cond=15 match +@if defined(VERSION_5) + +:ldc2 cpn,CRd,addrmode5 is $(AMODE) & ARMcond=0 & cond=15 & c2527=6 & addrmode5 & cpn & CRd & N22=0 & L20=1 +{ + t_cpn:4 = cpn; + coprocessor_load2(t_cpn,CRd,addrmode5); +} + +:ldc2l cpn,CRd,addrmode5 is $(AMODE) & ARMcond=0 & cond=15 & c2527=6 & addrmode5 & cpn & CRd & N22=1 & L20=1 +{ + t_cpn:4 = cpn; + coprocessor_loadlong2(t_cpn,CRd,addrmode5); +} + +@endif # VERSION_5 +######## cond=15 match + +:ldc^COND cpn,CRd,addrmode5 is $(AMODE) & ARMcond=1 & COND & c2527=6 & addrmode5 & cpn & CRd & N22=0 & L20=1 +{ + build COND; + build addrmode5; + t_cpn:4 = cpn; + coprocessor_load(t_cpn,CRd,addrmode5); +} + +:ldcl^COND cpn,CRd,addrmode5 is $(AMODE) & ARMcond=1 & COND & c2527=6 & addrmode5 & cpn & CRd & N22=1 & L20=1 +{ + build COND; + build addrmode5; + t_cpn:4 = cpn; + coprocessor_loadlong(t_cpn,CRd,addrmode5); +} + +:ldm^mdir^COND reglist is $(AMODE) & ARMcond=1 & COND & c2527=4 & mdir & L20=1 & c1515=0 & reglist +{ + build COND; + build reglist; +} + +:ldm^mdir^COND reglist is $(AMODE) & ARMcond=1 & COND & c2527=4 & mdir & L20=1 & c1515=1 & reglist +{ + build COND; + build reglist; + LoadWritePC(pc); + return [pc]; +} + +#:ldr^COND Rd,addrmode2 is $(AMODE) & ARMcond=1 & COND & B22=0 & L20=1 & Rd & (I25=0 | (I25=1 & c0404=0)) & addrmode2 +#{ +# build COND; +# build addrmode2; +# tmp:4=addrmode2&0xfffffffc; +# tmp2:4=(addrmode2&3)<<3; +# Rd=*tmp; +# Rd = (Rd >> tmp2) | (Rd << (32-tmp2)); +#} + +# The following form of ldr assumes alignment checking is on +:ldr^COND Rd,addrmode2 is $(AMODE) & ARMcond=1 & COND & c2627=1 & B22=0 & L20=1 & Rd & (I25=0 | (I25=1 & c0404=0)) & addrmode2 +{ + build COND; + build addrmode2; + Rd = *addrmode2; +} + +# Two forms of ldr with destination=pc needed to distinguish from ldrt +:ldr^COND pc,addrmode2 is $(AMODE) & pc & ARMcond=1 & COND & LRset=1 & c2627=1 & B22=0 & L20=1 & Rd=15 & P24=1 & (I25=0 | (I25=1 & c0404=0)) & addrmode2 + [ LRset=0; globalset(inst_next,LRset); ] +{ + build COND; + build addrmode2; + dest:4=*addrmode2; + SetThumbMode((dest&0x00000001)!=0); + pc=dest&0xfffffffe; + call [pc]; + SetThumbMode(0); +} # No unaligned address + +:ldr^COND pc,addrmode2 is $(AMODE) & pc & ARMcond=1 & COND & LRset=1 & c2627=1 & B22=0 & L20=1 & Rd=15 & P24=0 & W21=0 & (I25=0 | (I25=1 & c0404=0)) & addrmode2 + [ LRset=0; globalset(inst_next,LRset); ] +{ + build COND; + build addrmode2; + dest:4=*addrmode2; + SetThumbMode((dest&0x00000001)!=0); + pc=dest&0xfffffffe; + call [pc]; + SetThumbMode(0); +} # No unaligned address + +# Two forms of ldr with destination=pc needed to distinguish from ldrt +:ldr^COND pc,addrmode2 is $(AMODE) & pc & ARMcond=1 & COND & c2627=1 & B22=0 & L20=1 & Rd=15 & P24=1 & (I25=0 | (I25=1 & c0404=0)) & addrmode2 +{ + build COND; + build addrmode2; + dest:4=*addrmode2; + BXWritePC(dest); + goto [pc]; +} # No unaligned address + +:ldr^COND pc,addrmode2 is $(AMODE) & pc & ARMcond=1 & COND & c2627=1 & B22=0 & L20=1 & Rd=15 & P24=0 & W21=0 & (I25=0 | (I25=1 & c0404=0)) & addrmode2 +{ + build COND; + build addrmode2; + dest:4=*addrmode2; + BXWritePC(dest); + goto [pc]; +} # No unaligned address + +:ldrb^COND Rd,addrmode2 is $(AMODE) & ARMcond=1 & COND & c2627=1 & B22=1 & L20=1 & Rd & (I25=0 | (I25=1 & c0404=0)) & addrmode2 +{ + build COND; + build addrmode2; + Rd = zext( *:1 addrmode2); +} + +:ldrbt^COND Rd,addrmode2 is $(AMODE) & ARMcond=1 & COND & c2627=1 & B22=1 & L20=1 & P24=0 & W21=1 & Rd & (I25=0 | (I25=1 & c0404=0)) & addrmode2 +{ + build COND; + build addrmode2; + Rd = zext( *:1 addrmode2); +} + +@if defined(VERSION_5E) + +:ldrd^COND Rd,Rd2,addrmode3 is $(AMODE) & ARMcond=1 & COND & c2527=0 & c0407=13 & c1212=0 & L20=0 & Rd & Rd2 & addrmode3 +{ + build COND; + build addrmode3; + Rd = *(addrmode3); + Rd2 = *(addrmode3+4); +} + +@endif # VERSION_5E + +@if defined(VERSION_6) + +:ldrex^COND Rd,[Rn] is $(AMODE) & ARMcond=1 & COND & c2027=0x19 & Rn & Rd & c0011=0xf9f +{ + build COND; + Rd = *Rn; +} + +@endif # VERSION_6 + +@if defined(VERSION_6K) + +:ldrexb^COND Rd,[Rn] is $(AMODE) & ARMcond=1 & COND & c2027=0x1d & Rn & Rd & c0011=0xf9f +{ + build COND; + Rd = zext(*:1 Rn); +} + +:ldrexd^COND Rd,Rd2,[Rn] is $(AMODE) & ARMcond=1 & COND & c2027=0x1b & Rn & Rd & Rd2 & c0011=0xf9f +{ + build COND; + Rd = *(Rn); + Rd2 = *(Rn + 4); +} + +:ldrexh^COND Rd,[Rn] is $(AMODE) & ARMcond=1 & COND & c2027=0x1f & Rn & Rd & c0011=0xf9f +{ + build COND; + Rd = zext(*:2 Rn); +} + +@endif # VERSION_6K + +:ldrh^COND Rd,addrmode3 is $(AMODE) & ARMcond=1 & COND & c2527=0 & L20=1 & c0407=11 & Rd & addrmode3 +{ + build COND; + build addrmode3; + Rd = zext( *:2 addrmode3); +} + +@if defined(VERSION_6T2) + +:ldrht^COND Rd,addrmode3 is $(AMODE) & ARMcond=1 & COND & c2527=0 & P24=0 & W21=1 & L20=1 & c0407=11 & Rd & addrmode3 { + build COND; + build addrmode3; + Rd = zext( *:2 addrmode3); +} + +@endif # VERSION_6T2 + +:ldrsb^COND Rd,addrmode3 is $(AMODE) & ARMcond=1 & COND & c2527=0 & L20=1 & c0407=13 & Rd & addrmode3 +{ + build COND; + build addrmode3; + Rd = sext( *:1 addrmode3); +} + +@if defined(VERSION_6T2) + +:ldrsbt^COND Rd,addrmode3 is $(AMODE) & ARMcond=1 & COND & c2527=0 & P24=0 & W21=1 & L20=1 & c0407=13 & Rd & addrmode3 { + build COND; + build addrmode3; + Rd = sext( *:1 addrmode3); +} + +@endif # VERSION_6T2 + +:ldrsh^COND Rd,addrmode3 is $(AMODE) & ARMcond=1 & COND & c2527=0 & L20=1 & c0407=15 & Rd & addrmode3 +{ + build COND; + build addrmode3; + Rd = sext( *:2 addrmode3); +} + +@if defined(VERSION_6T2) + +:ldrsht^COND Rd,addrmode3 is $(AMODE) & ARMcond=1 & COND & c2527=0 & P24=0 & W21=1 & L20=1 & c0407=15 & Rd & addrmode3 { + build COND; + build addrmode3; + Rd = sext( *:2 addrmode3); +} + +@endif # VERSION_6T2 + +# The following form of ldr assumes alignment checking is on +:ldrt^COND Rd,addrmode2 is $(AMODE) & ARMcond=1 & COND & c2627=1 & B22=0 & L20=1 & P24=0 & W21=1 & Rd & (I25=0 | (I25=1 & c0404=0)) & addrmode2 +{ + build COND; + build addrmode2; + Rd = *addrmode2; +} + + +###### must come first cond=15 +@if defined(VERSION_5) +:mcr2 cpn,opc1,Rd,CRn,CRm,opc2 is $(AMODE) & ARMcond=0 & cond=15 & c2427=14 & opc1 & c2020=0 & CRn & Rd & cpn & opc2 & c0404=1 & CRm +{ + t_cpn:4 = cpn; + t_op1:4 = opc1; + t_op2:4 = opc2; + coprocessor_moveto(t_cpn,t_op1,t_op2,Rd,CRn,CRm); +} +@endif # VERSION_5 +###### must come first cond=15 + + +# ===== START mcr + +:mcr^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=0 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Main_ID(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=0 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Cache_Type(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=0 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_TCM_Status(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=3 & cpn=15 & Rd & CRn=0 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_TLB_Type(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=1 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Control(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=1 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Auxiliary_Control(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=1 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Coprocessor_Access_Control(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=1 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=1 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Secure_Configuration(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=1 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=1 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Secure_Debug_Enable(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=1 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=1 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_NonSecure_Access_Control(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=2 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Translation_table_base_0(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=2 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Translation_table_base_1(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=2 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Translation_table_control(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=3 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Domain_Access_Control(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=5 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Data_Fault_Status(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=5 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Instruction_Fault(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=6 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Fault_Address(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=6 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Instruction_Fault(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=4 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Wait_for_interrupt(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=5 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Invalidate_Entire_Instruction(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=5 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Invalidate_Instruction_Cache_by_MVA(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=5 & c0404=1 & opc2=4 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Flush_Prefetch_Buffer(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=6 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Invalidate_Entire_Data_cache(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=6 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Invalidate_Entire_Data_by_MVA(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=6 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Invalidate_Entire_Data_by_Index(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=10 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Clean_Entire_Data_Cache(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=10 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Clean_Data_Cache_by_MVA(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=10 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Clean_Data_Cache_by_Index(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=10 & c0404=1 & opc2=4 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Data_Synchronization(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=10 & c0404=1 & opc2=5 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Data_Memory_Barrier(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=14 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Invalidate_Entire_Data_Cache(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=14 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Invalidate_Data_Cache_by_MVA(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=7 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=8 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Invalidate_unified_TLB_unlocked(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=7 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=8 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Invalidate_unified_TLB_by_MVA(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=7 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=8 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Invalidate_unified_TLB_by_ASID_match(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=13 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_FCSE_PID(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=13 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Context_ID(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=13 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_User_RW_Thread_and_Process_ID(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=3 & cpn=15 & Rd & CRn=13 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_User_R_Thread_and_Process_ID(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=4 & cpn=15 & Rd & CRn=13 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Privileged_only_Thread_and_Process_ID(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=2 & c0404=1 & opc2=4 & cpn=15 & Rd & CRn=15 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + coproc_moveto_Peripherial_Port_Memory_Remap(Rd); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=1 & c0404=1 & opc2 & cpn=15 & Rd & CRn=0 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + t_opt2:4=opc2; + coproc_moveto_Feature_Identification(Rd,t_opt2); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=2 & c0404=1 & opc2 & cpn=15 & Rd & CRn=0 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + t_opt2:4=opc2; + coproc_moveto_ISA_Feature_Identification(Rd,t_opt2); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=4 & c0404=1 & opc2 & cpn=15 & Rd & CRn=0 & c2020=0 & opc1=2 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + t_opc2:4 = opc2; + coproc_moveto_Peripheral_Port_Memory_Remap(Rd,t_opc2); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2 & cpn=15 & Rd & CRn=1 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + t_opc2:4 = opc2; + coproc_moveto_Control_registers(Rd, t_opc2); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=1 & c0404=1 & opc2 & cpn=15 & Rd & CRn=1 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + t_opc2:4 = opc2; + coproc_moveto_Security_world_control(Rd, t_opc2); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2 & cpn=15 & Rd & CRn=2 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + t_opc2:4 = opc2; + coproc_moveto_Translation_table(Rd,t_opc2); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=5 & c0404=1 & opc2 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + t_opc2:4 = opc2; + coproc_moveto_Instruction_cache(Rd,t_opc2); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm=10 & c0404=1 & opc2 & cpn=15 & Rd & CRn=7 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + t_opc2:4 = opc2; + coproc_moveto_Data_cache_operations(Rd,t_opc2); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm & c0404=1 & opc2 & cpn=15 & Rd & CRn=0 & c2020=0 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + t_opc2:4 = opc2; t_crm:4 = CRm; + coproc_moveto_Identification_registers(Rd,t_opc2,t_crm); +} + + +:mcr^COND mcrOperands is + $(AMODE) & CRm & c0404=1 & opc2 & cpn=15 & Rd & CRn=15 & c2020=0 & opc1 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + t_opc2:4 = opc2; t_crm:4 = CRm; t_op1:4 = opc1; + coproc_moveto_Peripheral_System(Rd,t_opc2,t_crm,t_op1); +} + + +# ===== END mcr + +:mcr^COND cpn,opc1,Rd,CRn,CRm,opc2 is $(AMODE) & ARMcond=1 & COND & c2427=14 & opc1 & c2020=0 & CRn & Rd & cpn & opc2 & c0404=1 & CRm +{ + build COND; + t_cpn:4 = cpn; + t_op1:4 = opc1; + t_op2:4 = opc2; + coprocessor_moveto(t_cpn,t_op1,t_op2,Rd,CRn,CRm); +} + +##### must come first cond=15 +@if defined(VERSION_6) +:mcrr2 cpn,opcode3,Rd,Rn,CRm is $(AMODE) & ARMcond=0 & cond=15 & c2027=0xc4 & cpn & opcode3 & Rd & Rn & CRm +{ + t_cpn:4 = cpn; + t_op:4 = opcode3; + coprocessor_moveto2(t_cpn,t_op,Rd,Rn,CRm); +} + +:mrrc2 cpn,opcode3,Rd,Rn,CRm is $(AMODE) & ARMcond=0 & cond=15 & c2027=0xc5 & cpn & opcode3 & Rd & Rn & CRm +{ + t_cpn:4 = cpn; + t_op:4 = opcode3; + Rd = coprocessor_movefromRt(t_cpn,t_op,CRm); + Rn = coprocessor_movefromRt2(t_cpn,t_op,CRm); +} +@endif # VERSION_6 +##### must come first cond=15 + + +@if defined(VERSION_5E) + +:mcrr^COND cpn,opcode3,Rd,Rn,CRm is $(AMODE) & c2027=0xc4 & COND & ARMcond=1 & cpn & opcode3 & Rd & Rn & CRm +{ + build COND; + t_cpn:4 = cpn; + t_op:4 = opcode3; + coprocessor_moveto2(t_cpn,t_op,Rd,Rn,CRm); +} + +:mrrc^COND cpn,opcode3,Rd,Rn,CRm is $(AMODE) & c2027=0xc5 & COND & ARMcond=1 & cpn & opcode3 & Rd & Rn & CRm +{ + build COND; + t_cpn:4 = cpn; + t_op:4 = opcode3; + Rd = coprocessor_movefromRt(t_cpn,t_op,CRm); + Rn = coprocessor_movefromRt2(t_cpn,t_op,CRm); +} + +@endif # VERSION_5E + +:mla^COND^SBIT_ZN Rn,Rm,Rs,Rd is $(AMODE) & ARMcond=1 & COND & c2527=0 & c2124=1 & SBIT_ZN & Rn & Rd & Rs & c0407=9 & Rm +{ + build COND; + Rn = Rm*Rs + Rd; + resultflags(Rn); + build SBIT_ZN; +} + +@if defined(VERSION_6T2) + +:mls^COND Rn,Rm,Rs,Rd is $(AMODE) & ARMcond=1 & COND & c2027=0x06 & Rn & Rd & Rs & c0407=9 & Rm { + build COND; + Rn = Rd - Rm*Rs; +} + +@endif # VERSION_6T2 + +:mov^COND^SBIT_CZNO Rd,shift1 is $(AMODE) & ARMcond=1 & COND & c2124=13 & SBIT_CZNO & c1619=0 & Rd & c2627=0 & shift1 +{ + build COND; + build shift1; + Rd = shift1; + resultflags(Rd); + logicflags(); + build SBIT_CZNO; +} + +:mov^COND^SBIT_CZNO Rd,shift2 is $(AMODE) & ARMcond=1 & COND & c2124=13 & SBIT_CZNO & c1619=0 & Rd & c2627=0 & shift2 +{ + build COND; + build shift2; + Rd = shift2; + resultflags(Rd); + logicflags(); + build SBIT_CZNO; +} + +:mov lr,pc is $(AMODE) & ARMcond=1 & c0031=0xe1a0e00f & lr & pc + [ LRset=1; globalset(inst_next,LRset); ] +{ + lr = inst_next + 4; + resultflags(lr); + logicflags(); +} + +:mov^COND^SBIT_CZNO Rd,shift3 is $(AMODE) & ARMcond=1 & COND & c2124=13 & SBIT_CZNO & c1619=0 & Rd & c2627=0 & shift3 +{ + build COND; + build shift3; + Rd = shift3; + resultflags(Rd); + logicflags(); + build SBIT_CZNO; +} + +:mov^COND^SBIT_CZNO pc,shift1 is $(AMODE) & pc & ARMcond=1 & COND & c2124=13 & SBIT_CZNO & c1619=0 & Rd=15 & c2627=0 & shift1 +{ + build COND; + build shift1; + SetThumbMode((shift1&0x00000001)!=0); + local tmp=shift1&0xfffffffe; + resultflags(tmp); + logicflags(); + build SBIT_CZNO; + ALUWritePC(tmp); + goto [pc]; +} + +:mov^COND^SBIT_CZNO pc,shift2 is $(AMODE) & pc & ARMcond=1 & COND & c2124=13 & SBIT_CZNO & c1619=0 & Rd=15 & c2627=0 & shift2 +{ + build COND; + build shift2; + SetThumbMode((shift2&0x00000001)!=0); + local tmp=shift2&0xfffffffe; + resultflags(tmp); + logicflags(); + build SBIT_CZNO; + ALUWritePC(tmp); + goto [pc]; +} +:mov^COND^SBIT_CZNO pc,shift2 is $(AMODE) & LRset=1 & pc & COND & ARMcond=1 & c2124=13 & SBIT_CZNO & c1619=0 & Rd=15 & c2627=0 & shift2 +{ + build COND; + build shift2; + SetThumbMode((shift2&0x00000001)!=0); + local tmp=shift2&0xfffffffe; + resultflags(tmp); + logicflags(); + build SBIT_CZNO; + ALUWritePC(tmp); + call [pc]; +} + +:mov^COND^SBIT_CZNO pc,shift3 is $(AMODE) & pc & ARMcond=1 & COND & c2124=13 & SBIT_CZNO & c1619=0 & Rd=15 & c2627=0 & shift3 +{ + build COND; + build shift3; + SetThumbMode((shift3&0x00000001)!=0); + local tmp=shift3&0xfffffffe; + resultflags(tmp); + logicflags(); + build SBIT_CZNO; + ALUWritePC(tmp); + goto [pc]; +} + +:mov lr,rm is $(AMODE) & ARMcond=0 & cond=15 & c2527=0 & S20=0 & c2124=13 & c1619=0 & rm & Rm2=15 & sftimm=0 & c0406=0 & Rd=14 & lr + [ LRset=1; globalset(inst_next,LRset); ] +{ + lr = rm; +} + +:mov^COND pc,lr is $(AMODE) & pc & ARMcond=1 & COND & c2527=0 & S20=0 & c2124=13 & c1619=0 & Rd=15 & sftimm=0 & c0406=0 & Rm=14 & lr +{ + build COND; + dest:4 = lr; + ALUWritePC(dest); + return [pc]; +} + +@if defined(VERSION_6T2) + +:movw^COND Rd,"#"^val is $(AMODE) & ARMcond=1 & COND & c2027=0x30 & c1619 & Rd & c0011 [ val = (c1619 << 12) | c0011; ] { + build COND; + Rd = val; +} + +:movt^COND Rd,"#"^val is $(AMODE) & ARMcond=1 & COND & c2027=0x34 & c1619 & Rd & c0011 [ val = (c1619 << 12) | c0011; ] { + build COND; + Rd = (val << 16) | (Rd & 0xffff); +} + +@endif # VERSION_6T2 + +###### must come before next instruction because cond=15 +@if defined(VERSION_5) + + +:mrc2 cpn,opc1,Rd,CRn,CRm,opc2 is $(AMODE) & ARMcond=0 & cond=15 & c2427=14 & opc1 & c2020=1 & CRn & Rd & cpn & opc2 & c0404=1 & CRm +{ + t_cpn:4 = cpn; + t_op1:4 = opc1; + t_op2:4 = opc2; + Rd = coprocessor_movefromRt(t_cpn,t_op1,t_op2,CRn,CRm); +} +@endif # VERSION_5 + +# ===== Start mrc + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=0 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Main_ID(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=0 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Cache_Type(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=0 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_TCM_Status(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=3 & cpn=15 & Rd & CRn=0 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_TLB_Type(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=1 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Control(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=1 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Auxiliary_Control(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=1 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Coprocessor_Access_Control(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=1 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=1 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Secure_Configuration(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=1 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=1 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Secure_Debug_Enable(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=1 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=1 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_NonSecure_Access_Control(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=2 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Translation_table_base_0(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=2 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Translation_table_base_1(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=2 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Translation_table_control(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=3 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Domain_Access_Control(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=5 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Instruction_Fault_Status(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=5 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Data_Fault_Status(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=6 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Fault_Address(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=6 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Instruction_Fault_Address(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=4 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Wait_for_interrupt(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=5 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Invalidate_Entire_Instruction(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=5 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Invalidate_Instruction_Cache_by_MVA(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=5 & c0404=1 & opc2=4 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Flush_Prefetch_Buffer(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=6 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Invalidate_Entire_Data_cache(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=6 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Invalidate_Entire_Data_by_MVA(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=6 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Invalidate_Entire_Data_by_Index(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=10 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Clean_Entire_Data_Cache(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=10 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Clean_Data_Cache_by_MVA(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=10 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Clean_Data_Cache_by_Index(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=10 & c0404=1 & opc2=4 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Data_Synchronization(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=10 & c0404=1 & opc2=5 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Data_Memory_Barrier(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=14 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Invalidate_Entire_Data_Cache(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=14 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Invalidate_Data_Cache_by_MVA(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=7 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=8 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Invalidate_unified_TLB_unlocked(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=7 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=8 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Invalidate_unified_TLB_by_MVA(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=7 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=8 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Invalidate_unified_TLB_by_ASID_match(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=0 & cpn=15 & Rd & CRn=13 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_FCSE_PID(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=1 & cpn=15 & Rd & CRn=13 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Context_ID(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=2 & cpn=15 & Rd & CRn=13 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_User_RW_Thread_and_Process_ID(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=3 & cpn=15 & Rd & CRn=13 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_User_R_Thread_and_Process_ID(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2=4 & cpn=15 & Rd & CRn=13 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Privileged_only_Thread_and_Process_ID(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=2 & c0404=1 & opc2=4 & cpn=15 & Rd & CRn=15 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + Rd = coproc_movefrom_Peripherial_Port_Memory_Remap(); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=1 & c0404=1 & opc2 & cpn=15 & Rd & CRn=0 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + t_opt2:4=opc2; + Rd = coproc_movefrom_Feature_Identification(t_opt2); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=2 & c0404=1 & opc2 & cpn=15 & Rd & CRn=0 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + t_opc2:4 = opc2; + Rd = coproc_movefrom_ISA_Feature_Identification(t_opc2); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=4 & c0404=1 & opc2 & cpn=15 & Rd & CRn=0 & c2020=1 & opc1=2 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + t_opc2:4 = opc2; + Rd = coproc_movefrom_Peripheral_Port_Memory_Remap(t_opc2); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2 & cpn=15 & Rd & CRn=1 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + t_opc2:4 = opc2; + Rd = coproc_movefrom_Control_registers(t_opc2); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=1 & c0404=1 & opc2 & cpn=15 & Rd & CRn=1 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + t_opc2:4 = opc2; + Rd = coproc_movefrom_Security_world_control(t_opc2); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=0 & c0404=1 & opc2 & cpn=15 & Rd & CRn=2 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + t_opc2:4 = opc2; + Rd = coproc_movefrom_Translation_table(t_opc2); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=5 & c0404=1 & opc2 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + t_opc2:4 = opc2; + Rd = coproc_movefrom_Instruction_cache(t_opc2); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm=10 & c0404=1 & opc2 & cpn=15 & Rd & CRn=7 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + t_opc2:4 = opc2; + Rd = coproc_movefrom_Data_cache_operations(t_opc2); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm & c0404=1 & opc2 & cpn=15 & Rd & CRn=0 & c2020=1 & opc1=0 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + t_opc2:4 = opc2; t_crm:4 = CRm; + Rd = coproc_movefrom_Identification_registers(t_opc2,t_crm); +} + + + +:mrc^COND mcrOperands is + $(AMODE) & CRm & c0404=1 & opc2 & cpn=15 & Rd & CRn=15 & c2020=1 & opc1 & c2427=14 & COND & ARMcond=1 & + mcrOperands +{ + build COND; + t_opc2:4 = opc2; t_crm:4 = CRm; t_op1:4 = opc1; + Rd = coproc_movefrom_Peripheral_System(t_opc2,t_crm,t_op1); +} + + + +# ===== End mrc + +:mrc^COND cpn,opc1,Rd,CRn,CRm,opc2 is $(AMODE) & ARMcond=1 & COND & c2427=14 & opc1 & c2020=1 & CRn & Rd & cpn & opc2 & c0404=1 & CRm +{ + build COND; + t_cpn:4 = cpn; + t_op1:4 = opc1; + t_opc2:4 = opc2; + Rd = coprocessor_movefromRt(t_cpn,t_op1,t_opc2,CRn,CRm); +} + + +:mrs^COND Rd,cpsr is $(AMODE) & ARMcond=1 & COND & c2027=16 & c1619=15 & Rd & offset_12=0 & cpsr +{ +# TODO: GE bits have not been included + build COND; + Rd = zext( (NG<<4) | (ZR<<3) | (CY<<2) | (OV<<1) | (Q) ) << 27; +} + +:mrs^COND Rd,spsr is $(AMODE) & ARMcond=1 & COND & c2027=20 & c1619=15 & Rd & offset_12=0 & spsr +{ + build COND; + Rd = spsr; +} + +:msr^COND cpsrmask,shift1 is $(AMODE) & ARMcond=1 & COND & c2027=50 & cpsrmask & c1215=15 & c2627=0 & shift1 +{ + build COND; + build cpsrmask; + build shift1; + cpsr = (cpsr& ~cpsrmask) | (shift1 & cpsrmask); +} + +:msr^COND cpsrmask,rm is $(AMODE) & ARMcond=1 & COND & c2027=18 & cpsrmask & c1215=15 & c0811=0 & c0407=0 & rm +{ +# TODO: GE bits have not been included + build COND; + build cpsrmask; + cpsr = (cpsr& ~cpsrmask) | (rm & cpsrmask); + local tmp = cpsr >> 27 & 0x1f; + Q = ((tmp ) & 0x1) != 0; + OV = ((tmp >> 1) & 0x1) != 0; + CY = ((tmp >> 2) & 0x1) != 0; + ZR = ((tmp >> 3) & 0x1) != 0; + NG = ((tmp >> 4) & 0x1) != 0; +} + +:msr^COND spsrmask,shift1 is $(AMODE) & ARMcond=1 & COND & c2027=54 & spsrmask & c1215=15 & c2627=0 & shift1 +{ + build COND; + build spsrmask; + build shift1; + spsr = (spsr& ~spsrmask) | (shift1 & spsrmask); +} + +:msr^COND spsrmask,rm is $(AMODE) & ARMcond=1 & COND & c2027=22 & spsrmask & c1215=15 & c0811=0 & c0407=0 & rm +{ + build COND; + build spsrmask; + spsr = (spsr& ~spsrmask) | (rm & spsrmask); +} + +:mul^COND^SBIT_ZN rn,rm,rs is $(AMODE) & ARMcond=1 & COND & c2527=0 & c2124=0 & SBIT_ZN & rn & c1215=0 & rs & c0407=9 & rm +{ + build COND; + build rm; + build rs; + rn = rm*rs; + resultflags(rn); + build SBIT_ZN; +} + +:mvn^COND^SBIT_CZNO Rd,shift1 is $(AMODE) & ARMcond=1 & COND & c2124=15 & SBIT_CZNO & c1619=0 & Rd & c2627=0 & shift1 +{ + build COND; + build shift1; + Rd=~shift1; + resultflags(Rd); + logicflags(); + build SBIT_CZNO; +} + +:mvn^COND^SBIT_CZNO Rd,shift2 is $(AMODE) & ARMcond=1 & COND & c2124=15 & SBIT_CZNO & c1619=0 & Rd & c2627=0 & shift2 +{ + build COND; + build shift2; + Rd=~shift2; + resultflags(Rd); + logicflags(); + build SBIT_CZNO; +} + +:mvn^COND^SBIT_CZNO Rd,shift3 is $(AMODE) & ARMcond=1 & COND & c2124=15 & SBIT_CZNO & c1619=0 & Rd & c2627=0 & shift3 +{ + build COND; + build shift3; + Rd=~shift3; + resultflags(Rd); + logicflags(); + build SBIT_CZNO; +} + +:mvn^COND^SBIT_ZN pc,shift1 is $(AMODE) & pc & ARMcond=1 & COND & c2124=15 & SBIT_ZN & c1619=0 & Rd=15 & c2627=0 & shift1 +{ + build COND; + build shift1; + dest:4 = ~shift1; + resultflags(dest); + build SBIT_ZN; + ALUWritePC(dest); + goto [pc]; +} + +:mvn^COND^SBIT_ZN pc,shift2 is $(AMODE) & pc & ARMcond=1 & COND & c2124=15 & SBIT_ZN & c1619=0 & Rd=15 & c2627=0 & shift2 +{ + build COND; + build shift2; + dest:4 = ~shift2; + resultflags(dest); + build SBIT_ZN; + ALUWritePC(dest); + goto [pc]; +} + +:mvn^COND^SBIT_ZN pc,shift3 is $(AMODE) & pc & ARMcond=1 & COND & c2124=15 & SBIT_ZN & c1619=0 & Rd=15 & c2627=0 & shift3 +{ + build COND; + build shift3; + dest:4 = ~shift3; + resultflags(dest); + build SBIT_ZN; + ALUWritePC(dest); + goto [pc]; +} + +@if defined(VERSION_6K) || defined(VERSION_6T2) || defined(VERSION_7) + +:nop^COND is $(AMODE) & ARMcond=1 & COND & c0027=0x320f000 { +} + +@endif # VERSION_6K + +:orr^COND^SBIT_CZNO Rd,rn,shift1 is $(AMODE) & ARMcond=1 & COND & c2124=12 & SBIT_CZNO & rn & Rd & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + Rd = rn|shift1; + logicflags(); + resultflags(Rd); + build SBIT_CZNO; +} + +:orr^COND^SBIT_CZNO Rd,rn,shift2 is $(AMODE) & ARMcond=1 & COND & c2124=12 & SBIT_CZNO & rn & Rd & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + Rd = rn|shift2; + logicflags(); + resultflags(Rd); + build SBIT_CZNO; +} + +:orr^COND^SBIT_CZNO Rd,rn,shift3 is $(AMODE) & ARMcond=1 & COND & c2124=12 & SBIT_CZNO & rn & Rd & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + Rd = rn|shift3; + logicflags(); + resultflags(Rd); + build SBIT_CZNO; +} + +:orr^COND^SBIT_CZNO pc,rn,shift1 is $(AMODE) & pc & ARMcond=1 & COND & c2124=12 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + dest:4 = rn|shift1; + logicflags(); + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +:orr^COND^SBIT_CZNO pc,rn,shift2 is $(AMODE) & pc & ARMcond=1 & COND & c2124=12 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + dest:4 = rn|shift2; + logicflags(); + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +:orr^COND^SBIT_CZNO pc,rn,shift3 is $(AMODE) & pc & ARMcond=1 & COND & c2124=12 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + dest:4 = rn|shift3; + logicflags(); + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +@if defined(VERSION_6) + +:pkhbt^COND Rd,rn,shift4 is $(AMODE) & ARMcond=1 & COND & c2027=0x68 & c0406=1 & Rd & rn & shift4 +{ + build COND; + build rn; + build shift4; + Rd = (rn & 0xffff) + (shift4 & 0xffff0000); +} + +:pkhtb^COND Rd,rn,shift4 is $(AMODE) & ARMcond=1 & COND & c2027=0x68 & c0406=5 & Rd & rn & shift4 +{ + build COND; + build rn; + build shift4; + Rd = (shift4 & 0xffff) + (rn & 0xffff0000); +} + +@endif # VERSION_6 + +@if defined(VERSION_5E) + +:qadd^COND Rd,Rm,Rn is $(AMODE) & ARMcond=1 & COND & c2027=0x10 & Rn & Rd & c0811=0 & c0407=5 & Rm +{ + build COND; + local sum1 = Rm + Rn; + sum1 = SignedSaturate(sum1,32:2); + Q = SignedDoesSaturate(sum1,32:2); + Rd = sum1; +} + +@endif # VERSION_5E + +@if defined(VERSION_6) + +:qadd16^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x62 & c0811=15 & c0407=1 & Rn & Rd & Rm +{ + build COND; + local lRn = Rn & 0xffff; + local lRm = Rm & 0xffff; + local uRn = (Rn >> 16) & 0xffff; + local uRm = (Rm >> 16) & 0xffff; + sum1:2 = lRn:2 + lRm:2; + sum1 = SignedSaturate(sum1,16:2); + sum2:2 = uRn:2 + uRm:2; + sum2 = SignedSaturate(sum2,16:2); + Rd = (zext(sum2) << 16) | zext(sum1); +} + +:qadd8^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x62 & c0811=15 & c0407=9 & Rn & Rd & Rm +{ + build COND; + local rn1 = Rn & 0xff; + local rm1 = Rm & 0xff; + local rn2 = (Rn >> 8) & 0xff; + local rm2 = (Rm >> 8) & 0xff; + local rn3 = (Rn >> 16) & 0xff; + local rm3 = (Rm >> 16) & 0xff; + local rn4 = (Rn >> 24) & 0xff; + local rm4 = (Rm >> 24) & 0xff; + sum1:1 = rn1:1 + rm1:1; + sum1 = SignedSaturate(sum1,8:2); + sum2:1 = rn2:1 + rm2:1; + sum2 = SignedSaturate(sum2,8:2); + sum3:1 = rn3:1 + rm3:1; + sum3 = SignedSaturate(sum3,8:2); + sum4:1 = rn4:1 + rm4:1; + sum4 = SignedSaturate(sum4,8:2); + Rd = (zext(sum4) << 24) | (zext(sum3) << 16) | (zext(sum2) << 8) | zext(sum1); +} + +# qaddsubx +:qasx^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x62 & c0811=15 & c0407=3 & Rn & Rd & Rm +{ + build COND; + local lRn = Rn & 0xffff; + local lRm = Rm & 0xffff; + local uRn = (Rn >> 16) & 0xffff; + local uRm = (Rm >> 16) & 0xffff; + sum1:2 = lRn:2 - lRm:2; + sum1 = SignedSaturate(sum1,16:2); + sum2:2 = uRn:2 + uRm:2; + sum2 = SignedSaturate(sum2,16:2); + Rd = (zext(sum2) << 16) | zext(sum1); +} + +@endif # VERSION_6 + +@if defined(VERSION_5E) + +:qdadd^COND Rd,Rm,Rn is $(AMODE) & ARMcond=1 & COND & c2027=0x14 & Rn & Rd & c0811=0 & c0407=5 & Rm +{ + build COND; + tmp:4 = Rn * 2; + tmp = SignedSaturate(tmp,32:2); + Q = SignedDoesSaturate(tmp,32:2); + tmp = tmp + Rm; + tmp = SignedSaturate(tmp,32:2); + Q = Q | SignedDoesSaturate(tmp,32:2); + Rd = tmp; +} + +:qdsub^COND Rd,Rm,Rn is $(AMODE) & ARMcond=1 & COND & c2027=0x16 & Rn & Rd & c0811=0 & c0407=5 & Rm +{ + build COND; + tmp:4 = Rn * 2; + tmp = SignedSaturate(tmp); + Q = SignedDoesSaturate(tmp,32:2); + tmp = Rm - tmp; + tmp = SignedSaturate(tmp,32:2); + Q = Q | SignedDoesSaturate(tmp,32:2); + Rd = tmp; +} + +@endif # VERSION_5E + +@if defined(VERSION_6) + +# qsubaddx +:qsax^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x62 & c0811=15 & c0407=5 & Rn & Rd & Rm +{ + build COND; + local lRn = Rn & 0xffff; + local lRm = Rm & 0xffff; + local uRn = (Rn >> 16) & 0xffff; + local uRm = (Rm >> 16) & 0xffff; + sum1:2 = lRn:2 + lRm:2; + sum1 = SignedSaturate(sum1,16:2); + sum2:2 = uRn:2 - uRm:2; + sum2 = SignedSaturate(sum2,16:2); + Rd = (zext(sum2) << 16) | zext(sum1); +} + +@endif # VERSION_6 + +@if defined(VERSION_5E) + +:qsub^COND Rd,Rm,Rn is $(AMODE) & ARMcond=1 & COND & c2027=0x12 & Rn & Rd & c0811=0 & c0407=5 & Rm +{ + build COND; + tmp:4 = Rm - Rn; + tmp = SignedSaturate(tmp,32:2); + Q = SignedDoesSaturate(tmp,32:2); + Rd = tmp; +} + +@endif # VERSION_5E + +@if defined(VERSION_6) + +:qsub16^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x62 & c0811=15 & c0407=7 & Rn & Rd & Rm +{ + build COND; + local lRn = Rn & 0xffff; + local lRm = Rm & 0xffff; + local uRn = (Rn >> 16) & 0xffff; + local uRm = (Rm >> 16) & 0xffff; + sum1:2 = lRn:2 - lRm:2; + sum1 = SignedSaturate(sum1,16:2); + sum2:2 = uRn:2 - uRm:2; + sum2 = SignedSaturate(sum2,16:2); + Rd = (zext(sum2) << 16) | zext(sum1); +} + +:qsub8^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x62 & c0811=15 & c0407=15 & Rn & Rd & Rm +{ + build COND; + local rn1 = Rn & 0xff; + local rm1 = Rm & 0xff; + local rn2 = (Rn >> 8) & 0xff; + local rm2 = (Rm >> 8) & 0xff; + local rn3 = (Rn >> 16) & 0xff; + local rm3 = (Rm >> 16) & 0xff; + local rn4 = (Rn >> 24) & 0xff; + local rm4 = (Rm >> 24) & 0xff; + sum1:1 = rn1:1 - rm1:1; + sum1 = SignedSaturate(sum1,8:2); + sum2:1 = rn2:1 - rm2:1; + sum2 = SignedSaturate(sum2,8:2); + sum3:1 = rn3:1 - rm3:1; + sum3 = SignedSaturate(sum3,8:2); + sum4:1 = rn4:1 - rm4:1; + sum4 = SignedSaturate(sum4,8:2); + Rd = (zext(sum4) << 24) | (zext(sum3) << 16) | (zext(sum2) << 8) | zext(sum1); +} + +@endif # VERSION_6 + +@if defined(VERSION_6T2) + +macro BitReverse_arm(val) { + tval:1 = val; + result:1 = 0; + result = (result << 1) | (tval & 1); + tval = tval >> 1; + result = (result << 1) | (tval & 1); + tval = tval >> 1; + result = (result << 1) | (tval & 1); + tval = tval >> 1; + result = (result << 1) | (tval & 1); + tval = tval >> 1; + result = (result << 1) | (tval & 1); + tval = tval >> 1; + result = (result << 1) | (tval & 1); + tval = tval >> 1; + result = (result << 1) | (tval & 1); + tval = tval >> 1; + result = (result << 1) | (tval & 1); + tval = tval >> 1; + val = result; +} + + +:rbit^COND Rd, rm is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=7 & c0407=3 & c1619=15 & c0811=15 & Rd & rm +{ + build COND; + build rm; + local t:4 = rm & 0xff; + local b1:1 = t:1; + t = (rm >> 8) & 0xff; + local b2:1 = t:1; + t = (rm >> 16) & 0xff; + local b3:1 = t:1; + t = (rm >> 24) & 0xff; + local b4:1 = t:1; + BitReverse_arm(b1); + BitReverse_arm(b2); + BitReverse_arm(b3); + BitReverse_arm(b4); + Rd = (zext(b1) << 24) | (zext(b2) << 16) | (zext(b3) << 8) | zext(b4); +} + +@endif # VERSION_6T2 + +@if defined(VERSION_6) + +:rev^COND Rd, rm is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=3 & c0407=3 & c1619=15 & c0811=15 & Rd & rm +{ + build COND; + build rm; + local tmp1 = rm & 0xff; + local tmp2 = (rm >> 8) & 0xff; + local tmp3 = (rm >> 16) & 0xff; + local tmp4 = (rm >> 24) & 0xff; + Rd = (tmp1 << 24) | (tmp2 << 16) | (tmp3 << 8) | tmp4; +} + +:rev16^COND Rd, rm is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=3 & c0407=11 & Rd & rm +{ + build COND; + build rm; + local tmp1 = rm & 0xff; + local tmp2 = (rm >> 8) & 0xff; + local tmp3 = (rm >> 16) & 0xff; + local tmp4 = (rm >> 24) & 0xff; + Rd = (tmp3 << 24) | (tmp4 << 16) | (tmp1 << 8) | tmp2; +} + +:revsh^COND Rd, rm is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=7 & c0407=11 & Rd & rm +{ + build COND; + build rm; + local tmp1 = rm & 0xff; + local tmp2 = (rm >> 8) & 0xff; + tmp3:2 = zext(tmp1:1) << 8 | zext(tmp2:1); + Rd = sext(tmp3); +} + +@endif # VERSION_6 + +:rsb^COND^SBIT_CZNO Rd,rn,shift1 is $(AMODE) & ARMcond=1 & COND & c2124=3 & SBIT_CZNO & rn & Rd & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + subflags(shift1,rn); + Rd = shift1-rn; + resultflags(Rd); + build SBIT_CZNO; +} + +:rsb^COND^SBIT_CZNO Rd,rn,shift2 is $(AMODE) & ARMcond=1 & COND & c2124=3 & SBIT_CZNO & rn & Rd & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + subflags(shift2,rn); + Rd = shift2-rn; + resultflags(Rd); + build SBIT_CZNO; +} + +:rsb^COND^SBIT_CZNO Rd,rn,shift3 is $(AMODE) & ARMcond=1 & COND & c2124=3 & SBIT_CZNO & rn & Rd & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + subflags(shift3,rn); + Rd = shift3-rn; + resultflags(Rd); + build SBIT_CZNO; +} + +:rsb^COND^SBIT_CZNO pc,rn,shift1 is $(AMODE) & pc & ARMcond=1 & COND & c2124=3 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + subflags(shift1,rn); + dest:4 = shift1-rn; + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +:rsb^COND^SBIT_CZNO pc,rn,shift2 is $(AMODE) & pc & ARMcond=1 & COND & c2124=3 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + subflags(shift2,rn); + dest:4 = shift2-rn; + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +:rsb^COND^SBIT_CZNO pc,rn,shift3 is $(AMODE) & pc & ARMcond=1 & COND & c2124=3 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + subflags(shift3,rn); + dest:4 = shift3-rn; + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +:rsc^COND^SBIT_CZNO Rd,rn,shift1 is $(AMODE) & ARMcond=1 & COND & c2124=7 & SBIT_CZNO & rn & Rd & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + sub_with_carry_flags(shift1,rn); + Rd=shift1-(rn+zext(!CY)); + resultflags(Rd); + build SBIT_CZNO; +} + +:rsc^COND^SBIT_CZNO Rd,rn,shift2 is $(AMODE) & ARMcond=1 & COND & c2124=7 & SBIT_CZNO & rn & Rd & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + sub_with_carry_flags(shift2,rn); + Rd=shift2-(rn+zext(!CY)); + resultflags(Rd); + build SBIT_CZNO; +} + +:rsc^COND^SBIT_CZNO Rd,rn,shift3 is $(AMODE) & ARMcond=1 & COND & c2124=7 & SBIT_CZNO & rn & Rd & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + sub_with_carry_flags(shift3,rn); + Rd=shift3-(rn+zext(!CY)); + resultflags(Rd); + build SBIT_CZNO; +} + +:rsc^COND^SBIT_CZNO pc,rn,shift1 is $(AMODE) & pc & ARMcond=1 & COND & c2124=7 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + sub_with_carry_flags(shift1,rn); + local dest:4=shift1-(rn+zext(!CY)); + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +:rsc^COND^SBIT_CZNO pc,rn,shift2 is $(AMODE) & pc & ARMcond=1 & COND & c2124=7 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + sub_with_carry_flags(shift2,rn); + local dest:4=shift2-(rn + zext(!CY)); + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +:rsc^COND^SBIT_CZNO pc,rn,shift3 is $(AMODE) & pc & ARMcond=1 & COND & c2124=7 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + sub_with_carry_flags(shift3,rn); + local dest:4=shift3-(rn + zext(!CY)); + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +@if defined(VERSION_6) + +:sadd16^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x61 & c0811=15 & c0407=1 & Rn & Rd & Rm +{ + build COND; + local tmpRn = Rn & 0xffff; + local tmpRm = Rm & 0xffff; + local sum1 = sext(tmpRn:2) + sext(tmpRm:2); + GE1 = sum1 s>= 0; + GE2 = sum1 s>= 0; + tmpRn = (Rn >> 16) & 0xffff; + tmpRm = (Rm >> 16) & 0xffff; + local sum2 = sext(tmpRn:2) + sext(tmpRm:2); + GE3 = sum2 s>= 0; + GE4 = sum2 s>= 0; + Rd = ((sum2 & 0xffff) << 16) | (sum1 & 0xffff); +} + +:sadd8^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x61 & c0811=15 & c0407=9 & Rn & Rd & Rm +{ + build COND; + local tmpRn = Rn & 0xff; + local tmpRm = Rm & 0xff; + local sum1 = sext(tmpRn:1) + sext(tmpRm:1); + GE1 = sum1 s>= 0; + tmpRn = (Rn >> 8) & 0xff; + tmpRm = (Rm >> 8) & 0xff; + local sum2 = sext(tmpRn:1) + sext(tmpRm:1); + GE2 = sum2 s>= 0; + tmpRn = (Rn >> 16) & 0xff; + tmpRm = (Rm >> 16) & 0xff; + local sum3 = sext(tmpRn:1) + sext(tmpRm:1); + GE3 = sum3 s>= 0; + tmpRn = (Rn >> 24) & 0xff; + tmpRm = (Rm >> 24) & 0xff; + local sum4 = sext(tmpRn:1) + sext(tmpRm:1); + GE4 = sum4 s>= 0; + Rd = ((sum4 & 0xff) << 24) | ((sum3 & 0xff) << 16) | ((sum2 & 0xff) << 8) | (sum1 & 0xff); +} + +# saddsubx +:sasx^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x61 & c0811=15 & c0407=3 & Rn & Rd & Rm +{ + build COND; + local lRn = Rn & 0xffff; + local lRm = Rm & 0xffff; + local uRn = (Rn >> 16) & 0xffff; + local uRm = (Rm >> 16) & 0xffff; + local sum1 = sext(uRn:2) + sext(lRm:2); + GE3 = sum1 s>= 0; + GE4 = sum1 s>= 0; + local diff = sext(lRn:2) - sext(uRm:2); + GE1 = diff s>= 0; + GE2 = diff s>= 0; + + Rd = ((sum1 & 0xffff) << 16) | (diff & 0xffff); +} + +@endif # VERSION_6 + +:sbc^SBIT_CZNO^COND Rd,rn,shift1 is $(AMODE) & ARMcond=1 & COND & c2124=6 & SBIT_CZNO & rn & Rd & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + sub_with_carry_flags(rn,shift1); + Rd = rn-(shift1+zext(!CY)); + resultflags(Rd); + build SBIT_CZNO; +} + +:sbc^SBIT_CZNO^COND Rd,rn,shift2 is $(AMODE) & ARMcond=1 & COND & c2124=6 & SBIT_CZNO & rn & Rd & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + sub_with_carry_flags(rn,shift2); + Rd = rn-(shift2 + zext(!CY)); + resultflags(Rd); + build SBIT_CZNO; +} + +:sbc^SBIT_CZNO^COND Rd,rn,shift3 is $(AMODE) & ARMcond=1 & COND & c2124=6 & SBIT_CZNO & rn & Rd & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + sub_with_carry_flags(rn,shift3); + Rd = rn-(shift3+zext(!CY)); + resultflags(Rd); + build SBIT_CZNO; +} + +:sbc^SBIT_CZNO^COND pc,rn,shift1 is $(AMODE) & pc & ARMcond=1 & COND & c2124=6 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + sub_with_carry_flags(rn,shift1); + local dest:4 = rn-(shift1 + zext(!CY)); + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +:sbc^SBIT_CZNO^COND pc,rn,shift2 is $(AMODE) & pc & ARMcond=1 & COND & c2124=6 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + sub_with_carry_flags(rn,shift2); + local dest:4 = rn-(shift2+zext(!CY)); + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +:sbc^SBIT_CZNO^COND pc,rn,shift3 is $(AMODE) & pc & ARMcond=1 & COND & c2124=6 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + sub_with_carry_flags(rn,shift3); + local dest:4 = rn-(shift3 + zext(!CY)); + resultflags(dest); + build SBIT_CZNO; + ALUWritePC(dest); + goto [pc]; +} + +@if defined(VERSION_6) + +@if defined(VERSION_6T2) + +:sbfx^COND Rd,Rm,lsbImm,widthMinus1 is $(AMODE) & COND & ARMcond=1 & c2127=0x3d & widthMinus1 & Rd & lsbImm & c0406=5 & Rm +{ + build COND; + build lsbImm; + build widthMinus1; + shift:4 = 31 - (lsbImm + widthMinus1); + Rd = Rm << shift; + shift = 31 - widthMinus1; + Rd = Rd s>> shift; +} + +@endif # VERSION_6T2 + +@if defined(VERSION_7) + +macro sdiv(result, a, b) { + if (b != 0) goto ; + result = 0; + goto ; + + + result = a s/ b; + + +} + +# Warning: note the non-standard use of Rd, Rm, Rn +:sdiv^COND RdHi,RnLo,RmHi is $(AMODE) & ARMcond=1 & COND & c2027=0x71 & RdHi & c1215=0xf & RmHi & c0407=0x1 & RnLo +{ + build COND; + sdiv(RdHi, RnLo, RmHi); +} + +@endif # VERSION_7 + +:sel^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x68 & Rn & Rd & c0811=15 & c0407=11 & Rm +{ + build COND; + local rD1 = ((zext(GE1) * Rn) + (zext(!GE1) * Rm)) & 0x0ff; + local rD2 = ((zext(GE2) * Rn) + (zext(!GE2) * Rm)) & 0x0ff00; + local rD3 = ((zext(GE3) * Rn) + (zext(!GE3) * Rm)) & 0x0ff0000; + local rD4 = ((zext(GE4) * Rn) + (zext(!GE4) * Rm)) & 0x0ff000000; + Rd = rD1 | rD2 | rD3 | rD4; +} + +@if defined(VERSION_6K) + +:sev^COND is $(AMODE) & ARMcond=1 & COND & c0027=0x320f004 +{ + build COND; + SendEvent(); +} + +@endif # VERSION_6K + +# Hopefully we never encounter this instruction since we can not change the effective endianess of the language +armEndianNess: "LE" is c0031=0xf1010000 { export 0:1; } +armEndianNess: "BE" is c0031=0xf1010200 { export 1:1; } + +:setend armEndianNess is $(AMODE) & (c0031=0xf1010000 | c0031=0xf1010200) & armEndianNess { setEndianState(armEndianNess); } + + +:shadd16^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x63 & Rn & Rd & c0811=15 & c0407=1 & Rm +{ + build COND; + local tmpRn = Rn; + local tmpRm = Rm; + sum1:4 = (sext(tmpRn:2) + sext(tmpRm:2)) >> 1; + sum2:4 = ((tmpRn s>> 16) + (tmpRm s>> 16)) >> 1; + Rd = (sum2 << 16) + (sum1 & 0xffff); +} + +:shadd8^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x63 & Rn & Rd & c0811=15 & c0407=9 & Rm +{ + build COND; + local tmpRn = Rn; + local tmpRm = Rm; + sum1:4 = (sext(tmpRn:1) + sext(tmpRm:1)) >> 1; + local tmpn = tmpRn >> 8; + local tmpm = tmpRm >> 8; + sum2:4 = (sext(tmpn:1) + sext(tmpm:1)) >> 1; + tmpn = tmpRn >> 16; + tmpm = tmpRm >> 16; + sum3:4 = (sext(tmpn:1) + sext(tmpm:1)) >> 1; + tmpn = tmpRn >> 24; + tmpm = tmpRm >> 24; + sum4:4 = (sext(tmpn:1) + sext(tmpm:1)) >> 1; + Rd = (sum4 << 24) + ((sum3 & 0xff) << 16) + ((sum2 & 0xff) << 8) + (sum1 & 0xff); +} + +# shaddsubx +:shasx^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x63 & Rn & Rd & c0811=15 & c0407=3 & Rm +{ + build COND; + local tmpRn = Rn; + local tmpRm = Rm; + local diff:4 = sext(tmpRn[ 0,16]) - sext(tmpRm[16,16]); + local sum:4 = sext(tmpRn[16,16]) + sext(tmpRm[ 0,16]); + Rd[0,16] = diff[1,16]; + Rd[16,16] = sum[1,16]; +} + +# shsubbaddx +:shsax^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x63 & Rn & Rd & c0811=15 & c0407=5 & Rm +{ + build COND; + local tmpRn = Rn; + local tmpRm = Rm; + local sum:4 = sext(tmpRn[ 0,16]) + sext(tmpRm[16,16]); + local diff:4 = sext(tmpRn[16,16]) - sext(tmpRm[ 0,16]); + Rd[ 0,16] = sum[1,16]; + Rd[16,16] = diff[1,16]; +} + +:shsub16^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x63 & Rn & Rd & c0811=15 & c0407=7 & Rm +{ + build COND; + local tmpRn = Rn; + local tmpRm = Rm; + sum1:4 = (sext(tmpRn:2) - sext(tmpRm:2)) >> 1; + sum2:4 = ((tmpRn s>> 16) - (tmpRm s>> 16)) >> 1; + Rd = (sum2 << 16) + (sum1 & 0xffff); +} + +:shsub8^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x63 & Rn & Rd & c0811=15 & c0407=15 & Rm +{ + build COND; + local tmpRn = Rn; + local tmpRm = Rm; + sum1:4 = (sext(tmpRn:1) - sext(tmpRm:1)) >> 1; + local tmpn = tmpRn >> 8; + local tmpm = tmpRm >> 8; + sum2:4 = (sext(tmpn:1) - sext(tmpm:1)) >> 1; + tmpn = tmpRn >> 16; + tmpm = tmpRm >> 16; + sum3:4 = (sext(tmpn:1) - sext(tmpm:1)) >> 1; + tmpn = tmpRn >> 24; + tmpm = tmpRm >> 24; + sum4:4 = (sext(tmpn:1) - sext(tmpm:1)) >> 1; + Rd = (sum4 << 24) + ((sum3 & 0xff) << 16) + ((sum2 & 0xff) << 8) + (sum1 & 0xff); +} + +@endif # VERSION_6 + +@if defined(VERSION_5E) + +:smla^XBIT^YBIT^COND smRd,smRn,smRm,smRa is $(AMODE) & ARMcond=1 & COND & c2027=0x10 & smRd & smRn & smRm & c0707=1 & XBIT & YBIT & c0404=0 & smRa +{ + build COND; + local tmp:4 = sext(XBIT) * sext(YBIT); + Q = scarry(tmp,smRa) || Q; #Q flag is sticky + smRd = tmp+smRa; +} + +@endif + +@if defined(VERSION_6) + +:smlad^COND smRd,smRn,smRm,smRa is $(AMODE) & ARMcond=1 & COND & c2027=0x70 & c0407=1 & smRd & smRa & smRm & smRn +{ + build COND; + local tmpRn = smRn; + local tmpRm = smRm; + local tmpLRn = tmpRn:2; + local tmpURn = tmpRn >> 16; + local tmpLRm = tmpRm:2; + local tmpURm = tmpRm >> 16; + local product1 = sext(tmpLRn) * sext(tmpLRm); + local product2 = sext(tmpURn:2) * sext(tmpURm:2); + local tmpprod = product1 + product2; + Q = scarry(smRa, tmpprod) || Q; #Q is sticky + smRd = smRa + tmpprod; +} + +:smladx^COND smRd, smRn, smRm, smRa is $(AMODE) & ARMcond=1 & COND & c2027=0x70 & c0407=3 & smRd & smRn & smRm & smRa +{ + build COND; + local tmpRn = smRn; + local tmpRm = smRm; + local tmpLRn = tmpRn:2; + local tmpURn = tmpRn >> 16; + local tmpLRm = tmpRm:2; + local tmpURm = tmpRm >> 16; + local product1 = sext(tmpLRn) * sext(tmpURm:2); + local product2 = sext(tmpURn:2) * sext(tmpLRm); + local tmpprod = product1 + product2; + Q = scarry(smRa, tmpprod) || Q; #Q is sticky + smRd = smRa + tmpprod; +} + +@endif # VERSION_6 + +:smlal^COND^SBIT_ZN RdLo,RdHi,smRn,smRm is $(AMODE) & ARMcond=1 & COND & c2527=0 & c2124=7 & SBIT_ZN & RdLo & RdHi & smRn & c0407=9 & smRm +{ + build COND; + tmp:8 = (zext(RdHi) << 32) | zext(RdLo); + rs64:8 = sext(smRm); + rm64:8 = sext(smRn); + tmp = rs64 * rm64 + tmp; + resultflags(tmp); + RdLo = tmp(0); + RdHi = tmp(4); + build SBIT_ZN; +} + +@if defined(VERSION_5E) + +:smlal^XBIT^YBIT^COND RdLo,RdHi,smRn,smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x14 & RdLo & RdHi & smRm & c0707=1 & XBIT & YBIT & c0404=0 & smRn +{ + build COND; + local prod:8 = sext(XBIT) * sext(YBIT); + local result:8 = (zext(RdHi) << 32) | zext(RdLo); + result = result + prod; + RdLo = result(0); + RdHi = result(4); +} + +@endif # VERSION_5E + +@if defined(VERSION_6) + +:smlald^COND RdLo,RdHi,smRn,smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x74 & RdLo & RdHi & c0607=0 & c0405=1 & smRn & smRm +{ + build COND; + local tmpRn = smRn; + local tmpRm = smRm; + prod1:8 = sext(tmpRn:2) * sext(tmpRm:2); + rmHi:2 = tmpRm(2); + rnHi:2 = tmpRn(2); + prod2:8 = sext(rmHi) * sext(rnHi); + result:8 = zext(RdLo) + (zext(RdHi) << 32) + prod1 + prod2; + RdLo = result:4; + RdHi = result(4); +} + +:smlaldx^COND RdLo,RdHi,smRn,smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x74 & RdLo & RdHi & c0607=0 & c0405=3 & smRn & smRm +{ + build COND; + local tmpRn = smRn; + local tmpRm = smRm; + rmHi:2 = tmpRm(2); + rnHi:2 = tmpRn(2); + prod1:8 = sext(tmpRn:2) * sext(rmHi); + prod2:8 = sext(rnHi) * sext(tmpRm:2); + result:8 = zext(RdLo) + (zext(RdHi) << 32) + prod1 + prod2; + RdLo = result:4; + RdHi = result(4); +} + +@endif # VERSION_6 + +@if defined(VERSION_5E) + +:smlaw^YBIT^COND smRd,smRn,smRm,smRa is $(AMODE) & ARMcond=1 & COND & c2027=0x12 & smRd & smRn & smRm & c0707=1 & YBIT & x=0 & c0404=0 & smRa +{ + build COND; + local tmp64:6 = sext(smRn) * sext(YBIT); + local tmp32:4 = tmp64(2); + Q = scarry(tmp32, smRa) || Q; #Q flag is sticky + smRd = tmp32 + smRa; +} + +@endif # VERSION_5E + +@if defined(VERSION_6) + +:smlsd^COND smRd,smRn,smRm,smRa is $(AMODE) & ARMcond=1 & COND & c2027=0x70 & smRd & smRn & c0607=1 & x=0 & c0404=1 & smRm & smRa +{ + build COND; + local tmpRn = smRn; + local tmpRm = smRm; + prod1:4 = sext(tmpRn:2) * sext(tmpRm:2); + rnHi:2 = tmpRn(2); + rmHi:2 = tmpRm(2); + prod2:4 = sext(rnHi) * sext(rmHi); + diff:4 = prod1 - prod2; + Q = scarry(diff, smRa) || Q; #Q is sticky + smRd = smRa + diff; +} + +:smlsdx^COND smRd,smRn,smRm,smRa is $(AMODE) & ARMcond=1 & COND & c2027=0x70 & smRd & smRn & c0607=1 & x=1 & c0404=1 & smRm & smRa +{ + build COND; + local tmpRn = smRn; + local tmpRm = smRm; + rnHi:2 = tmpRn(2); + rmHi:2 = tmpRm(2); + prod1:4 = sext(tmpRn:2) * sext(rmHi); + prod2:4 = sext(rnHi) * sext(tmpRm:2); + diff:4 = prod1 - prod2; + Q = scarry(diff, smRa) || Q; #Q is sticky + smRd = smRa + diff; +} + +:smlsld^COND RdLo,RdHi,smRn,smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x74 & RdHi & RdLo & smRm & c0607=1 & x=0 & c0404=1 & smRn +{ + build COND; + local tmpRn = smRn; + local tmpRm = smRm; + prod1:8 = sext(tmpRn:2) * sext(tmpRm:2); + rnHi:2 = tmpRn(2); + rmHi:2 = tmpRm(2); + prod2:8 = sext(rnHi) * sext(rmHi); + result:8 = zext(RdLo) + (zext(RdHi) << 32) + (prod1 - prod2); + RdLo = result:4; + RdHi = result(4); +} + +:smlsldx^COND RdLo,RdHi,smRn,smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x74 & RdHi & RdLo & smRm & c0607=1 & x=1 & c0404=1 & smRn +{ + build COND; + local tmpRn = smRn; + local tmpRm = smRm; + rnHi:2 = tmpRn(2); + rmHi:2 = tmpRm(2); + prod1:8 = sext(tmpRn:2) * sext(rmHi); + prod2:8 = sext(rnHi) * sext(tmpRm:2); + result:8 = zext(RdLo) + (zext(RdHi) << 32) + (prod1 - prod2); + RdLo = result:4; + RdHi = result(4); +} + +:smmla^COND smRd,smRn,smRm,smRa is $(AMODE) & ARMcond=1 & COND & c2027=0x75 & smRd & smRn & smRm & c0607=0 & r=0 & c0404=1 & smRa +{ + build COND; + val:8 = sext(smRn) * sext(smRm); + val = (zext(smRa) << 32) + val; + smRd = val(4); +} + +:smmlar^COND smRd,smRn,smRm,smRa is $(AMODE) & ARMcond=1 & COND & c2027=0x75 & smRd & smRn & smRm & c0607=0 & r=1 & c0404=1 & smRa +{ + build COND; + val:8 = sext(smRn) * sext(smRm); + val = (zext(smRa) << 32) + val + 0x80000000; + smRd = val(4); +} + +:smmls^COND smRd,smRn,smRm,smRa is $(AMODE) & ARMcond=1 & COND & c2027=0x75 & smRd & smRn & smRm & c0607=3 & r=0 & c0404=1 & smRa +{ + build COND; + val:8 = sext(smRn) * sext(smRm); + val = (zext(smRa) << 32) - val; + smRd = val(4); +} + +:smmlsr^COND smRd,smRn,smRm,smRa is $(AMODE) & ARMcond=1 & COND & c2027=0x75 & smRd & smRn & smRm & c0607=3 & r=1 & c0404=1 & smRa +{ + build COND; + val:8 = sext(smRn) * sext(smRm); + val = (zext(smRa) << 32) - val + 0x80000000; + smRd = val(4); +} + +:smmul^COND smRd,smRn,smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x75 & smRd & c1215=15 & smRn & c0607=0 & r=0 & c0404=1 & smRm +{ + build COND; + val:8 = sext(smRn) * sext(smRm); + smRd = val(4); +} + +:smmulr^COND smRd,smRn,smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x75 & smRd & c1215=15 & smRn & c0607=0 & r=1 & c0404=1 & smRm +{ + build COND; + val:8 = (sext(smRn) * sext(smRm)) + 0x080000000; + smRd = val(4); +} + +:smuad^COND smRd, smRn, smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x70 & c0407=1 & smRd & c1619=15 & smRn & smRm +{ + build COND; + local tmpRm = smRm; + local tmpRn = smRn; + local tmpLRm = tmpRm:2; + local tmpURm = tmpRm >> 16; + local tmpLRn = tmpRn:2; + local tmpURn = tmpRn >> 16; + local product1 = sext(tmpLRm) * sext(tmpLRn); + local product2 = sext(tmpURm:2) * sext(tmpURn:2); + local tmpprod = product1 + product2; + Q = scarry(product1, product2); + smRd = tmpprod; +} + +:smuadx^COND smRd, smRn, smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x70 & c0407=3 & smRd & c1619=15 & smRn & smRm +{ + build COND; + local tmpRm = smRm; + local tmpRn = smRn; + local tmpLRm = tmpRm:2; + local tmpURm = tmpRm >> 16; + local tmpLRn = tmpRn:2; + local tmpURn = tmpRn >> 16; + local product1 = sext(tmpLRm) * sext(tmpURn:2); + local product2 = sext(tmpURm:2) * sext(tmpLRn); + local tmpprod = product1 + product2; + Q = scarry(product1, product2); + smRd = tmpprod; +} + +@endif # VERSION_6 + +@if defined(VERSION_5E) + +:smul^XBIT^YBIT^COND smRd,smRn,smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x16 & smRd & c1215=0 & smRm & c0707=1 & XBIT & YBIT & c0404=0 & smRn +{ + build COND; + tmp:8 = sext(XBIT) * sext(YBIT); + smRd = tmp:4; +} + +@endif # VERSION_5E + +:smull^COND^SBIT_ZN RdLo,RdHi,smRn,smRm is $(AMODE) & ARMcond=1 & COND & c2527=0 & c2124=6 & SBIT_ZN & RdHi & RdLo & smRn & c0407=9 & smRm +{ + build COND; + rn64:8 = sext(smRn); + rm64:8 = sext(smRm); + local tmp = rn64 * rm64; + resultflags(tmp); + RdLo = tmp(0); + RdHi = tmp(4); + build SBIT_ZN; +} + +@if defined(VERSION_5E) + +:smulw^YBIT^COND smRd,smRn,smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x12 & smRd & c1215=0 & smRn & c0707=1 & YBIT & x=1 & c0404=0 & smRm +{ + build COND; + tmp:6 = sext(smRn) * sext(YBIT); + tmp = tmp >> 16; + smRd = tmp:4; +} + +@endif # VERSION_5E + +@if defined(VERSION_6) + +:smusd^COND smRd,smRn,smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x70 & smRd & c1215=15 & smRm & c0607=1 & x=0 & c0404=1 & smRn +{ + build COND; + local tmpRn = smRn; + local tmpRm = smRm; + rmHi:2 = tmpRm(2); + prod1:4 = sext(tmpRn:2) * sext(tmpRm:2); + rnHi:2 = tmpRn(2); + prod2:4 = sext(rnHi) * sext(rmHi); + smRd = prod1 - prod2; +} + +:smusdx^COND smRd,smRn,smRm is $(AMODE) & ARMcond=1 & COND & c2027=0x70 & smRd & c1215=15 & smRm & c0607=1 & x=1 & c0404=1 & smRn +{ + build COND; + local tmpRn = smRn; + local tmpRm = smRm; + rmHi:2 = tmpRm(2); + rnHi:2 = tmpRn(2); + prod1:4 = sext(tmpRn:2) * sext(rmHi); + prod2:4 = sext(rnHi) * sext(tmpRm:2); + smRd = prod1 - prod2; +} + + +:ssat^COND Rd, sSatImm5, shift4 is $(AMODE) & ARMcond=1 & COND & c2127=0x35 & c0405=1 & sSatImm5 & Rd & shift4 +{ + build COND; + build shift4; + tmp:4 = SignedSaturate(shift4, sSatImm5); + Q = SignedDoesSaturate(shift4, sSatImm5); + Rd = tmp; +} + +:ssat16^COND Rd, sSatImm4, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x6a & c0811=15 & c0407=0x3 & sSatImm4 & Rd & Rm +{ + build COND; + build sSatImm4; + local tmpl = Rm & 0xffff; + tmpl = SignedSaturate(tmpl, sSatImm4); + local tmpu = Rm >> 16; + tmpu = SignedSaturate(tmpu, sSatImm4); + Q = SignedDoesSaturate(tmpl,sSatImm4) | SignedDoesSaturate(tmpu,sSatImm4); + Rd = ((tmpu & 0xffff) << 16) | (tmpl & 0xffff); +} + +# ssubaddx +:ssax^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x61 & c0811=15 & c0407=5 & Rn & Rd & Rm +{ + build COND; + local lRn = Rn & 0xffff; + local lRm = Rm & 0xffff; + local uRn = (Rn >> 16) & 0xffff; + local uRm = (Rm >> 16) & 0xffff; + local diff = sext(uRn:2) - sext(lRm:2); + GE3 = diff s>= 0; + GE4 = diff s>= 0; + local sum = sext(lRn:2) + sext(uRm:2); + GE1 = sum s>= 0; + GE2 = sum s>= 0; + Rd = ((diff & 0xffff) << 16) | (sum & 0xffff); +} + +:ssub16^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x61 & c0811=15 & c0407=7 & Rn & Rd & Rm +{ + build COND; + local lRn = Rn & 0xffff; + local lRm = Rm & 0xffff; + local uRn = (Rn >> 16) & 0xffff; + local uRm = (Rm >> 16) & 0xffff; + local diffl = sext(lRn:2) - sext(lRm:2); + GE1 = diffl s>= 0; + GE2 = diffl s>= 0; + local diffu = sext(uRn:2) - sext(uRm:2); + GE3 = diffu s>= 0; + GE4 = diffu s>= 0; + Rd = ((diffu & 0xffff) << 16) | (diffl & 0xffff); +} + +:ssub8^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x61 & c0811=15 & c0407=15 & Rn & Rd & Rm +{ + build COND; + local tmpRn = Rn & 0xff; + local tmpRm = Rm & 0xff; + local diff1 = sext(tmpRn:1) - sext(tmpRm:1); + GE1 = diff1 s>= 0; + tmpRn = (Rn >> 8) & 0xff; + tmpRm = (Rm >> 8) & 0xff; + local diff2 = sext(tmpRn:1) - sext(tmpRm:1); + GE2 = diff2 s>= 0; + tmpRn = (Rn >> 16) & 0xff; + tmpRm = (Rm >> 16) & 0xff; + local diff3 = sext(tmpRn:1) - sext(tmpRm:1); + GE3 = diff3 s>= 0; + tmpRn = (Rn >> 24) & 0xff; + tmpRm = (Rm >> 24) & 0xff; + local diff4 = sext(tmpRn:1) - sext(tmpRm:1); + GE4 = diff4 s>= 0; + Rd = ((diff4 & 0xff) << 24) | ((diff3 & 0xff) << 16) | ((diff2 & 0xff) << 8) | (diff1 & 0xff); +} + +@endif # VERSION_6 + +:stc^COND cpn,CRd,addrmode5 is $(AMODE) & ARMcond=1 & COND & c2527=6 & addrmode5 & cpn & CRd & N22=0 & L20=0 +{ + build COND; + build addrmode5; + t_cpn:4 = cpn; + coprocessor_store(t_cpn,CRd,addrmode5); +} + +:stcl^COND cpn,CRd,addrmode5 is $(AMODE) & ARMcond=1 & COND & c2527=6 & addrmode5 & cpn & CRd & N22=1 & L20=0 +{ + build COND; + build addrmode5; + t_cpn:4 = cpn; + coprocessor_storelong(t_cpn,CRd,addrmode5); +} + +:stm^mdir^COND reglist is $(AMODE) & ARMcond=1 & COND & c2527=4 & mdir & L20=0 & reglist +{ + build COND; + build reglist; +} + +#:str^COND Rd,addrmode2 is $(AMODE) & ARMcond=1 & COND & c2627=1 & B22=0 & L20=0 & Rd & (I25=0 | (I25=1 & c0404=0)) & addrmode2 +#{ +# build COND; +# build addrmode2; +# tmp=addrmode2&0xfffffffc; +# *tmp = Rd; +#} + +# The following form of str assumes alignment checking is on +:str^COND Rd,addrmode2 is $(AMODE) & ARMcond=1 & COND & c2627=1 & B22=0 & L20=0 & Rd & (I25=0 | (I25=1 & c0404=0)) & addrmode2 +{ + build COND; + build addrmode2; + *addrmode2 = Rd; +} + +:strb^COND Rd,addrmode2 is $(AMODE) & ARMcond=1 & COND & c2627=1 & B22=1 & L20=0 & Rd & (I25=0 | (I25=1 & c0404=0)) & addrmode2 +{ + build COND; + build addrmode2; + local tmpRd = Rd; + *addrmode2 = tmpRd:1; +} + +:strbt^COND Rd,addrmode2 is $(AMODE) & ARMcond=1 & COND & c2627=1 & P24=0 & B22=1 & W21=1 & L20=0 & Rd & (I25=0 | (I25=1 & c0404=0)) & addrmode2 +{ + build COND; + build addrmode2; + local tmpRd = Rd; + *addrmode2 = tmpRd:1; +} + +:strh^COND Rd,addrmode3 is $(AMODE) & ARMcond=1 & COND & c2527=0 & L20=0 & c0407=11 & Rd & addrmode3 +{ + build COND; + build addrmode3; + local tmpRd = Rd; + *addrmode3 = tmpRd:2; +} + +@if defined(VERSION_5E) + +:strd^COND Rd,Rd2,addrmode3 is $(AMODE) & ARMcond=1 & COND & c2527=0 & c0407=0xf & L20=0 & Rd & Rd2 & addrmode3 +{ + build COND; + build addrmode3; + local addr = addrmode3; + *(addr) = Rd; + addr = addr + 4; + *(addr) = Rd2; +} + +@endif # VERSION_5E + +@if defined(VERSION_6) + +:strex^COND Rd,Rm,[Rn] is $(AMODE) & ARMcond=1 & COND & c2027=0x18 & c0411=0xf9 & Rn & Rd & Rm +{ + build COND; + local tmp = Rn; + access:1 = hasExclusiveAccess(tmp); + Rd = 1; + if (!access) goto inst_next; + Rd = 0; + *tmp = Rm; +} + +@endif # VERSION_6 + +@if defined(VERSION_6K) + +:strexb^COND Rd,Rm,[Rn] is $(AMODE) & ARMcond=1 & COND & c2027=0x1c & c0411=0xf9 & Rn & Rd & Rm +{ + build COND; + local tmp = Rn; + access:1 = hasExclusiveAccess(tmp); + Rd = 1; + if (!access) goto inst_next; + Rd = 0; + local tmpRm = Rm; + *tmp = tmpRm:1; +} + +:strexd^COND Rd,Rm,Rm2,[Rn] is $(AMODE) & ARMcond=1 & COND & c2027=0x1a & Rn & Rd & c0411=0xf9 & c0003 & Rm & Rm2 +{ + build COND; + local addr = Rn; + access:1 = hasExclusiveAccess(addr); + Rd = 1; + if (!access) goto inst_next; + Rd = 0; + *(addr) = Rm; + addr = addr + 4; + *(addr) = Rm2; +} + +:strexh^COND Rd,Rm,[Rn] is $(AMODE) & ARMcond=1 & COND & c2027=0x1e & c0411=0xf9 & Rn & Rd & Rm +{ + build COND; + local tmp = Rn; + access:1 = hasExclusiveAccess(tmp); + Rd = 1; + if (!access) goto inst_next; + Rd = 0; + local tmpRm = Rm; + *tmp = tmpRm:2; +} + +:strht^COND Rd,addrmode3 is $(AMODE) & ARMcond=1 & COND & c2527=0 & P24=0 & W21=1 & L20=0 & c0407=11 & Rd & addrmode3 { + build COND; + *:2 addrmode3 = Rd; +} + +@endif # VERSION_6K + +#:strt^COND Rd,addrmode2 is $(AMODE) & ARMcond=1 & COND & c2627=1 & B22=0 & L20=0 & P24=0 & W21=1 & Rd & addrmode2 +#{ +# build COND; +# build addrmode2; +# tmp=addrmode2&0xfffffffc; +# *tmp = Rd; +#} + +# The following form of str assumes alignment checking is on +:strt^COND Rd,addrmode2 is $(AMODE) & ARMcond=1 & COND & c2627=1 & B22=0 & L20=0 & P24=0 & W21=1 & Rd & (I25=0 | (I25=1 & c0404=0)) & addrmode2 +{ + build COND; + build addrmode2; + *addrmode2 = Rd; +} + +:sub^COND^SBIT_CZNO Rd,rn,shift1 is $(AMODE) & ARMcond=1 & COND & c2124=2 & SBIT_CZNO & rn & Rd & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + subflags(rn,shift1); + Rd = rn-shift1; + resultflags(Rd); + build SBIT_CZNO; +} + +:sub^COND^SBIT_CZNO Rd,rn,shift2 is $(AMODE) & ARMcond=1 & COND & c2124=2 & SBIT_CZNO & rn & Rd & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + subflags(rn,shift2); + Rd = rn-shift2; + resultflags(Rd); + build SBIT_CZNO; +} + +:sub^COND^SBIT_CZNO Rd,rn,shift3 is $(AMODE) & ARMcond=1 & COND & c2124=2 & SBIT_CZNO & rn & Rd & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + subflags(rn,shift3); + Rd = rn-shift3; + resultflags(Rd); + build SBIT_CZNO; +} + +:sub^COND^SBIT_CZNO pc,rn,shift1 is $(AMODE) & pc & ARMcond=1 & COND & c2124=2 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + subflags(rn,shift1); + dest:4 = rn-shift1; + resultflags(dest); + build SBIT_CZNO; + cpsr = spsr; + SetThumbMode( ((cpsr >> 5) & 1) != 0 ); + pc = dest; + goto [pc]; +} + +:sub^COND^SBIT_CZNO pc,rn,shift1 is $(AMODE) & pc & ARMcond=1 & COND & c2124=2 & SBIT_CZNO & rn & Rd=15 & Rn=14 & I25=1 & immed=0 & rotate=0 & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + subflags(rn,shift1); + dest:4 = rn-shift1; + resultflags(dest); + build SBIT_CZNO; + cpsr = spsr; + ALUWritePC(dest); + return [pc]; +} + +:sub^COND^SBIT_CZNO pc,rn,shift2 is $(AMODE) & pc & ARMcond=1 & COND & c2124=2 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + subflags(rn,shift2); + dest:4 = rn-shift2; + resultflags(dest); + build SBIT_CZNO; + cpsr = spsr; + SetThumbMode( ((cpsr >> 5) & 1) != 0 ); + pc = dest; + goto [pc]; +} + +:sub^COND^SBIT_CZNO pc,rn,shift3 is $(AMODE) & pc & ARMcond=1 & COND & c2124=2 & SBIT_CZNO & rn & Rd=15 & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + subflags(rn,shift3); + dest:4 = rn-shift3; + resultflags(dest); + build SBIT_CZNO; + cpsr = spsr; + SetThumbMode( ((cpsr >> 5) & 1) != 0 ); + pc = dest; + goto [pc]; +} + +:swi^COND immed24 is $(AMODE) & ARMcond=1 & COND & c2427=15 & immed24 +{ + build COND; + tmp:4 = immed24; + software_interrupt(tmp); +} + +#:swp^COND Rd,Rm,Rn is $(AMODE) & ARMcond=1 & COND & c2027=16 & Rn & Rd & c0811=0 & c0407=9 & Rm +#{ +# build COND; +# tmp = Rn & 0xfffffffc; +# tmp2 = (Rn&3)<<3; +# val:4 = *tmp; +# val=(val>>tmp2) | (val << (32-tmp2)); +# *tmp = Rm; +# Rd = val; +#} + +# Assuming alignment checking is enabled +:swp^COND Rd,Rm,Rn is $(AMODE) & ARMcond=1 & COND & c2027=16 & Rn & Rd & c0811=0 & c0407=9 & Rm +{ + build COND; + val:4 = *Rn; + *Rn = Rm; + Rd = val; +} + +:swpb^COND Rd,Rm,Rn is $(AMODE) & ARMcond=1 & COND & c2027=20 & Rn & Rd & c0811=0 & c0407=9 & Rm +{ + build COND; + local tmp = *:1 Rn; + local tmpRm = Rm; + *Rn = tmpRm:1; + Rd = zext(tmp); +} + +@if defined(VERSION_6) + +:sxtab^COND Rd,Rn,ror1 is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=2 & c0407=7 & Rd & Rn & ror1 +{ + build COND; + build ror1; + Rd = Rn + sext(ror1:1); +} + +:sxtab16^COND Rd,Rn,ror1 is $(AMODE) & ARMcond=1 & COND & c2027=0x68 & c0407=7 & Rn & Rd & ror1 +{ + build COND; + build ror1; + b:1 = ror1:1; + lo:2 = Rn:2 + sext(b); + b = ror1(2); + hi:2 = Rn(2) + sext(b); + Rd = (zext(hi) << 16) + zext(lo); +} + +:sxtah^COND Rd,Rn,ror1 is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=3 & c0407=7 & Rd & Rn & ror1 +{ + build COND; + build ror1; + Rd = Rn + sext(ror1:2); +} + +:sxtb^COND Rd,ror1 is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=2 & c0407=7 & Rd & c1619=15 & ror1 +{ + build COND; + build ror1; + Rd = sext(ror1:1); +} + +:sxtb16^COND Rd,ror1 is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=0 & c0407=7 & Rd & c1619=15 & ror1 +{ + build COND; + build ror1; + local tmp1:1 = ror1:1; + local low:2 = sext(tmp1); + local tmp2:1 = ror1(2); + local high:2 = sext(tmp2); + Rd = (zext(high) << 16) | zext(low); +} + +:sxth^COND Rd,ror1 is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=3 & c0407=7 & Rd & c1619=15 & ror1 +{ + build COND; + build ror1; + Rd = sext(ror1:2); +} + +@endif # VERSION_6 + +:teq^COND rn,shift1 is $(AMODE) & ARMcond=1 & COND & c2024=19 & rn & c1215=0 & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + local tmp = rn^shift1; + logicflags(); + resultflags(tmp); + affectflags(); +} + +:teq^COND rn,shift2 is $(AMODE) & ARMcond=1 & COND & c2024=19 & rn & c1215=0 & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + local tmp = rn^shift2; + logicflags(); + resultflags(tmp); + affectflags(); +} + +:teq^COND rn,shift3 is $(AMODE) & ARMcond=1 & COND & c2024=19 & rn & c1215=0 & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + local tmp = rn^shift3; + logicflags(); + resultflags(tmp); + affectflags(); +} + +:teq^COND^"p" rn,shift1 is $(AMODE) & ARMcond=1 & COND & c2024=19 & rn & c1215=15 & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + local tmp = rn^shift1; + logicflags(); + resultflags(tmp); + affectflags(); +} + +:teq^COND^"p" rn,shift2 is $(AMODE) & ARMcond=1 & COND & c2024=19 & rn & c1215=15 & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + local tmp = rn^shift2; + logicflags(); + resultflags(tmp); + affectflags(); +} + +:teq^COND^"p" rn,shift3 is $(AMODE) & ARMcond=1 & COND & c2024=19 & rn & c1215=15 & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + local tmp = rn^shift3; + logicflags(); + resultflags(tmp); + affectflags(); +} + + +:tst^COND rn,shift1 is $(AMODE) & ARMcond=1 & COND & c2024=17 & rn & c1215=0 & c2627=0 & shift1 +{ + build COND; + build rn; + build shift1; + local tmp = rn & shift1; + logicflags(); + resultflags(tmp); + affectflags(); +} + +:tst^COND rn,shift2 is $(AMODE) & ARMcond=1 & COND & c2024=17 & rn & c1215=0 & c2627=0 & shift2 +{ + build COND; + build rn; + build shift2; + local tmp = rn & shift2; + logicflags(); + resultflags(tmp); + affectflags(); +} + +:tst^COND rn,shift3 is $(AMODE) & ARMcond=1 & COND & c2024=17 & rn & c1215=0 & c2627=0 & shift3 +{ + build COND; + build rn; + build shift3; + local tmp = rn & shift3; + logicflags(); + resultflags(tmp); + affectflags(); +} + +@if defined(VERSION_6) + +:uadd16^COND Rd,rn,rm is $(AMODE) & ARMcond=1 & COND & c2327=12 & c2022=5 & c0811=15 & c0407=1 & Rd & rn & rm +{ + build COND; + build rn; + build rm; + local tmpRn = rn; + local tmpRm = rm; + tmp1:2 = tmpRn:2; + tmp2:2 = tmpRm:2; + local tcarry = carry(tmp1,tmp2); + GE1 = tcarry; + GE2 = tcarry; + local tmpLow = tmp1 + tmp2; + tmp1 = rn(2); + tmp2 = rm(2); + tcarry = carry(tmp1,tmp2); + GE3 = tcarry; + GE4 = tcarry; + local tmpHigh = tmp1 + tmp2; + Rd = zext(tmpHigh) << 16 | zext(tmpLow); +} + +:uadd8^COND Rd,rn,rm is $(AMODE) & ARMcond=1 & COND & c2327=12 & c2022=5 & c0811=15 & c0407=9 & Rd & rn & rm +{ + build COND; + build rn; + build rm; + local tmpRn = rn; + local tmpRm = rm; + tmp1:1 = tmpRn:1; + tmp2:1 = tmpRm:1; + GE1 = carry(tmp1,tmp2); + b1:1 = tmp1 + tmp2; + tmp1 = rn(1); + tmp2 = rm(1); + GE2 = carry(tmp1,tmp2); + b2:1 = tmp1 + tmp2; + tmp1 = rn(2); + tmp2 = rm(2); + GE3 = carry(tmp1,tmp2); + b3:1 = tmp1 + tmp2; + tmp1 = rn(3); + tmp2 = rm(3); + GE4 = carry(tmp1,tmp2); + b4:1 = tmp1 + tmp2; + Rd = (zext(b4) << 24) | (zext(b3) << 16) | (zext(b2) << 8) | zext(b1); +} + +# uaddsubx +:uasx^COND Rd,rn,rm is $(AMODE) & ARMcond=1 & COND & c2327=12 & c2022=5 & c0811=15 & c0407=3 & Rd & rn & rm +{ + build COND; + build rn; + build rm; + local tmpRn = rn; + local tmpRm = rm; + tmp1:2 = tmpRn:2; + tmp2:2 = tmpRm(2); + local tmpLow:4 = zext(tmp1) - zext(tmp2); + GE1 = tmpLow s>= 0; + GE2 = tmpLow s>= 0; + tmp1 = tmpRn(2); + tmp2 = tmpRm:2; + tcarry:1 = carry(tmp1,tmp2); + GE3 = tcarry; + GE4 = tcarry; + local tmpHigh = tmp1 + tmp2; + Rd[0,16] = tmpLow[0,16]; + Rd[16,16] = tmpHigh; + } + +@endif # VERSION_6 + +@if defined(VERSION_6T2) + +:ubfx^COND Rd,Rm,lsbImm,widthMinus1 is $(AMODE) & ARMcond=1 & COND & c2127=0x3f & widthMinus1 & Rd & lsbImm & c0406=5 & Rm +{ + build COND; + build lsbImm; + build widthMinus1; + shift:4 = 31 - (lsbImm + widthMinus1); + Rd = Rm << shift; + shift = 31 - widthMinus1; + Rd = Rd >> shift; +} + +@endif # VERSION_6T2 + +@if defined(VERSION_7) + +macro udiv(result, a, b) { + if (b != 0) goto ; + result = 0; + goto ; + + + local tmp:8 = zext(a) / zext(b); + result = tmp(0); + + +} + +:udiv^COND RdHi,RnLo,RmHi is $(AMODE) & ARMcond=1 & COND & c2027=0x73 & RdHi & c1215=0xf & RmHi & c0407=0x1 & RnLo +{ + build COND; + udiv(RdHi, RnLo, RmHi); +} + +@endif # VERSION_7 + +@if defined(VERSION_6) + +:uhadd16^COND Rd,rn,rm is $(AMODE) & ARMcond=1 & COND & c2327=12 & c2022=7 & c0811=15 & c0407=1 & Rd & rn & rm +{ + build COND; + build rn; + build rm; + local tmpRn = rn; + local tmpRm = rm; + tmp1:4 = tmpRn & 0xffff; + tmp2:4 = tmpRm & 0xffff; + local tmpLow = tmp1 + tmp2; + local tmpHigh = (tmpRn >> 16) + (tmpRm >> 16); + Rd[0,16] = tmpLow[1,16]; + Rd[16,16] = tmpHigh[1,16]; +} + +:uhadd8^COND Rd,rn,rm is $(AMODE) & ARMcond=1 & COND & c2327=12 & c2022=7 & c0811=15 & c0407=9 & Rd & rn & rm +{ + build COND; + build rn; + build rm; + local tmpRn = rn; + local tmpRm = rm; + tmp1:1 = tmpRn:1; + tmp2:1 = tmpRm:1; + b1:2 = (zext(tmp1) + zext(tmp2)) >> 1; + tmp1 = tmpRn(1); + tmp2 = tmpRm(1); + b2:2 = (zext(tmp1) + zext(tmp2)) >> 1; + tmp1 = tmpRn(2); + tmp2 = tmpRm(2); + b3:2 = (zext(tmp1) + zext(tmp2)) >> 1; + tmp1 = tmpRn(3); + tmp2 = tmpRm(3); + b4:2 = (zext(tmp1) + zext(tmp2)) >> 1; + Rd = (zext(b4) << 24) | (zext(b3) << 16) | (zext(b2) << 8) | zext(b1); +} + +# uhaddsubx +:uhasx^COND Rd,rn,rm is $(AMODE) & ARMcond=1 & COND & c2327=12 & c2022=7 & c0811=15 & c0407=3 & Rd & rn & rm +{ + build COND; + build rn; + build rm; + local tmpRn = rn; + local tmpRm = rm; + tmp1:2 = tmpRn:2; + tmp2:2 = tmpRm(2); + tmpLow:4 = ((zext(tmp1) - zext(tmp2)) >> 1) & 0x0ffff; + tmp1 = tmpRn(2); + tmp2 = tmpRm:2; + tmpHigh:4 = (zext(tmp1) + zext(tmp2)) >> 1; + Rd = (tmpHigh << 16) | tmpLow; +} + +# uhsubaddx +:uhsax^COND Rd,rn,rm is $(AMODE) & ARMcond=1 & COND & c2327=12 & c2022=7 & c0811=15 & c0407=5 & Rd & rn & rm +{ + build COND; + build rn; + build rm; + local tmpRn = rn; + local tmpRm = rm; + tmp1:2 = tmpRn:2; + tmp2:2 = tmpRm(2); + tmpLow:4 = (zext(tmp1) + zext(tmp2)) >> 1; + tmp1 = tmpRn(2); + tmp2 = tmpRm:2; + tmpHigh:4 = ((zext(tmp1) - zext(tmp2)) >> 1) & 0x0ffff; + Rd = (tmpHigh << 16) | tmpLow; +} + +:uhsub16^COND Rd,rn,rm is $(AMODE) & ARMcond=1 & COND & c2327=12 & c2022=7 & c0811=15 & c0407=7 & Rd & rn & rm +{ + build COND; + build rn; + build rm; + local tmpRn = rn; + local tmpRm = rm; + tmp1:2 = tmpRn:2; + tmp2:2 = tmpRm:2; + tmpLow:4 = ((zext(tmp1) - zext(tmp2)) >> 1) & 0x0ffff; + tmp1 = rn(2); + tmp2 = rm(2); + tmpHigh:4 = ((zext(tmp1) - zext(tmp2)) >> 1) & 0x0ffff; + Rd = (tmpHigh << 16) | tmpLow; +} + +:uhsub8^COND Rd,rn,rm is $(AMODE) & ARMcond=1 & COND & c2327=12 & c2022=7 & c0811=15 & c0407=15 & Rd & rn & rm +{ + build COND; + build rn; + build rm; + local tmpRn = rn; + local tmpRm = rm; + tmp1:1 = tmpRn:1; + tmp2:1 = tmpRm:1; + b1:4 = ((zext(tmp1) - zext(tmp2)) >> 1) & 0x0ff; + tmp1 = tmpRn(1); + tmp2 = tmpRm(1); + b2:4 = ((zext(tmp1) - zext(tmp2)) >> 1) & 0x0ff; + tmp1 = tmpRn(2); + tmp2 = tmpRm(2); + b3:4 = ((zext(tmp1) - zext(tmp2)) >> 1) & 0x0ff; + tmp1 = tmpRn(3); + tmp2 = tmpRm(3); + b4:4 = ((zext(tmp1) - zext(tmp2)) >> 1) & 0x0ff; + Rd = (b4 << 24) | (b3 << 16) | (b2 << 8) | b1; +} + +:umaal^COND RdLo,RdHi,Rm,Rs is $(AMODE) & ARMcond=1 & COND & c2027=0x04 & RdHi & RdLo & Rs & c0407=9 & Rm +{ + build COND; + result:8 = (zext(Rm) * zext(Rs)) + zext(RdLo) + zext(RdHi); + RdLo = result:4; + RdHi = result(4); +} + +@endif # VERSION_6 + +:umlal^COND^SBIT_ZN Rd,Rn,rm,rs is $(AMODE) & ARMcond=1 & COND & c2527=0 & c2124=5 & SBIT_ZN & Rn & Rd & rs & c0407=9 & rm +{ + build COND; + build rm; + build rs; + tmp:8 = (zext(Rn) << 32) | zext(Rd); + rs64:8 = zext(rs); + rm64:8 = zext(rm); + tmp = rs64 * rm64 + tmp; + resultflags(tmp); + Rd = tmp(0); + Rn = tmp(4); + build SBIT_ZN; +} + +:umull^COND^SBIT_ZN Rd,Rn,rm,rs is $(AMODE) & ARMcond=1 & COND & c2527=0 & c2124=4 & SBIT_ZN & Rn & Rd & rs & c0407=9 & rm +{ + build COND; + build rm; + build rs; + rs64:8 = zext(rs); + rm64:8 = zext(rm); + local tmp = rs64 * rm64; + resultflags(tmp); + Rd = tmp(0); + Rn = tmp(4); + build SBIT_ZN; +} + +@if defined(VERSION_6) + +:uqadd16^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x66 & c0811=15 & c0407=1 & Rn & Rd & Rm +{ + build COND; + local tmpRn = Rn; + local tmpRm = Rm; + tmp2Rn:2 = tmpRn:2; + tmp2Rm:2 = tmpRm:2; + sum1:2 = UnsignedSaturate(tmp2Rn + tmp2Rm, 16:2); + tmp2Rn = tmpRn(2); + tmp2Rm = tmpRm(2); + sum2:2 = UnsignedSaturate(tmp2Rn + tmp2Rm, 16:2); + Rd = (zext(sum2) << 16) | zext(sum1); +} + +:uqadd8^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x66 & c0811=15 & c0407=9 & Rn & Rd & Rm +{ + build COND; + local tmpRn = Rn; + local tmpRm = Rm; + tmp1Rn:1 = tmpRn:1; + tmp1Rm:1 = tmpRm:1; + sum1:1 = UnsignedSaturate(tmp1Rn + tmp1Rm, 16:2); + tmp1Rn = tmpRn(1); + tmp1Rm = tmpRm(1); + sum2:2 = UnsignedSaturate(tmp1Rn + tmp1Rm, 16:2); + tmp1Rn = tmpRn(2); + tmp1Rm = tmpRm(2); + sum3:2 = UnsignedSaturate(tmp1Rn + tmp1Rm, 16:2); + tmp1Rn = tmpRn(3); + tmp1Rm = tmpRm(3); + sum4:2 = UnsignedSaturate(tmp1Rn + tmp1Rm, 16:2); + Rd = (zext(sum4) << 24) | (zext(sum3) << 16) | (zext(sum2) << 8) | zext(sum1); +} + +# uqaddsubx +:uqasx^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x66 & c0811=15 & c0407=3 & Rn & Rd & Rm +{ + build COND; + local tmpRn = Rn; + local tmpRm = Rm; + tmp2Rn:2 = tmpRn:2; + tmp2Rm:2 = tmpRm(2); + sum1:2 = UnsignedSaturate(tmp2Rn - tmp2Rm, 16:2); + tmp2Rn = tmpRn(2); + tmp2Rm = tmpRm:2; + sum2:2 = UnsignedSaturate(tmp2Rn + tmp2Rm, 16:2); + Rd = (zext(sum2) << 16) | zext(sum1); +} + +# uqsubaddx +:uqsax^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x66 & c0811=15 & c0407=5 & Rn & Rd & Rm +{ + build COND; + local tmpRn = Rn; + local tmpRm = Rm; + tmp2Rn:2 = tmpRn:2; + tmp2Rm:2 = tmpRm(2); + sum1:2 = UnsignedSaturate(tmp2Rn + tmp2Rm, 16:2); + tmp2Rn = tmpRn(2); + tmp2Rm = tmpRm:2; + sum2:2 = UnsignedSaturate(tmp2Rn - tmp2Rm, 16:2); + Rd = (zext(sum2) << 16) | zext(sum1); +} + +:uqsub16^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x66 & c0811=15 & c0407=7 & Rn & Rd & Rm +{ + build COND; + local tmpRn = Rn; + local tmpRm = Rm; + tmp2Rn:2 = tmpRn:2; + tmp2Rm:2 = tmpRm:2; + sum1:2 = UnsignedSaturate(tmp2Rn - tmp2Rm, 16:2); + tmp2Rn = tmpRn(2); + tmp2Rm = tmpRm(2); + sum2:2 = UnsignedSaturate(tmp2Rn - tmp2Rm, 16:2); + Rd = (zext(sum2) << 16) | zext(sum1); +} + +:uqsub8^COND Rd, Rn, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x66 & c0811=15 & c0407=15 & Rn & Rd & Rm +{ + build COND; + local tmpRn = Rn; + local tmpRm = Rm; + tmp1Rn:1 = tmpRn:1; + tmp1Rm:1 = tmpRm:1; + sum1:1 = UnsignedSaturate(tmp1Rn - tmp1Rm, 16:2); + tmp1Rn = tmpRn(1); + tmp1Rm = tmpRm(1); + sum2:2 = UnsignedSaturate(tmp1Rn - tmp1Rm, 16:2); + tmp1Rn = tmpRn(2); + tmp1Rm = tmpRm(2); + sum3:2 = UnsignedSaturate(tmp1Rn - tmp1Rm, 16:2); + tmp1Rn = tmpRn(3); + tmp1Rm = tmpRm(3); + sum4:2 = UnsignedSaturate(tmp1Rn - tmp1Rm, 16:2); + Rd = (zext(sum4) << 24) | (zext(sum3) << 16) | (zext(sum2) << 8) | zext(sum1); +} + +:usad8^COND Rd, Rm, Rs is $(AMODE) & ARMcond=1 & COND & c2027=0x78 & c1215=15 & c0407=1 & Rd & Rm & Rs +{ + build COND; + local tmpRs = Rs; + local tmpRm = Rm; + tmp1Rs:1 = tmpRs:1; + tmp1Rm:1 = tmpRm:1; + sum1:1 = Absolute(tmp1Rs - tmp1Rm); + tmp1Rs = tmpRs(1); + tmp1Rm = tmpRm(1); + sum2:1 = Absolute(tmp1Rs - tmp1Rm); + tmp1Rs = tmpRs(2); + tmp1Rm = tmpRm(2); + sum3:1 = Absolute(tmp1Rs - tmp1Rm); + tmp1Rs = tmpRs(3); + tmp1Rm = tmpRm(3); + sum4:1 = Absolute(tmp1Rs - tmp1Rm); + Rd = (zext(sum4) << 24) | (zext(sum3) << 16) | (zext(sum2) << 8) | zext(sum1); +} + +:usada8^COND Rd, Rm, Rs, Rn is $(AMODE) & ARMcond=1 & COND & c2027=0x78 & c0407=1 & Rd & Rn& Rm & Rs +{ + build COND; + local tmpRs = Rs; + local tmpRm = Rm; + tmp1Rs:1 = tmpRs:1; + tmp1Rm:1 = tmpRm:1; + sum1:1 = Absolute(tmp1Rs - tmp1Rm); + tmp1Rs = tmpRs(1); + tmp1Rm = tmpRm(1); + sum2:1 = Absolute(tmp1Rs - tmp1Rm); + tmp1Rs = tmpRs(2); + tmp1Rm = tmpRm(2); + sum3:1 = Absolute(tmp1Rs - tmp1Rm); + tmp1Rs = tmpRs(3); + tmp1Rm = tmpRm(3); + sum4:1 = Absolute(tmp1Rs - tmp1Rm); + Rd = Rn + ((zext(sum4) << 24) | (zext(sum3) << 16) | (zext(sum2) << 8) | zext(sum1)); +} + +:usat^COND Rd, uSatImm5, shift4 is $(AMODE) & ARMcond=1 & COND & c2127=0x37 & c0405=0x1 & uSatImm5 & Rd & shift4 +{ + build COND; + build uSatImm5; + build shift4; + tmp:4 = UnsignedSaturate(shift4, uSatImm5); + Q = UnsignedDoesSaturate(shift4, uSatImm5); + Rd = tmp; +} + +:usat16^COND Rd, uSatImm4, Rm is $(AMODE) & ARMcond=1 & COND & c2027=0x6e & c0811=15 & c0407=0x3 & uSatImm4 & Rd & Rm +{ + build COND; + build uSatImm4; + local tmpl = Rm & 0xffff; + tmpl = UnsignedSaturate(tmpl, uSatImm4); + local tmpu = Rm >> 16; + tmpu = UnsignedSaturate(tmpu, uSatImm4); + Q = UnsignedDoesSaturate(tmpl,uSatImm4) | UnsignedDoesSaturate(tmpu,uSatImm4); + Rd = ((tmpu & 0xffff) << 16) | (tmpl & 0xffff); +} + +# usubaddx +:usax^COND Rd,rn,rm is $(AMODE) & ARMcond=1 & COND & c2327=12 & c2022=5 & c0811=15 & c0407=5 & Rd & rn & rm +{ + build COND; + build rn; + build rm; + local tmpRn = rn; + local tmpRm = rm; + tmp1:2 = tmpRn:2; + tmp2:2 = tmpRm(2); + local tcarry = carry(tmp2,tmp1); + GE1 = tcarry; + GE2 = tcarry; + local tmpLow = tmp1 + tmp2; + tmp1 = tmpRn(2); + tmp2 = tmpRm:2; + tcarry = tmp2 <= tmp1; + GE3 = tcarry; + GE4 = tcarry; + local tmpHigh = tmp1 - tmp2; + Rd = zext(tmpHigh) << 16 | zext(tmpLow); +} + +:usub16^COND Rd,rn,rm is $(AMODE) & ARMcond=1 & COND & c2327=12 & c2022=5 & c0811=15 & c0407=7 & Rd & rn & rm +{ + build COND; + build rn; + build rm; + local tmpRn = rn; + local tmpRm = rm; + tmp1:2 = tmpRn:2; + tmp2:2 = tmpRm:2; + local tcarry = tmp2 <= tmp1; + GE1 = tcarry; + GE2 = tcarry; + local tmpLow = tmp1 - tmp2; + tmp1 = tmpRn(2); + tmp2 = tmpRm(2); + tcarry = tmp2 <= tmp1; + GE3 = tcarry; + GE4 = tcarry; + local tmpHigh = tmp1 - tmp2; + Rd = zext(tmpHigh) << 16 | zext(tmpLow); +} + +:usub8^COND Rd,rn,rm is $(AMODE) & ARMcond=1 & COND & c2327=12 & c2022=5 & c0811=15 & c0407=15 & Rd & rn & rm +{ + build COND; + build rn; + build rm; + local tmpRn = rn; + local tmpRm = rm; + tmp1:1 = tmpRn:1; + tmp2:1 = tmpRm:1; + GE1 = tmp2 <= tmp1; + b1:1 = tmp1 - tmp2; + tmp1 = tmpRn(1); + tmp2 = tmpRm(1); + GE2 = tmp2 <= tmp1; + b2:1 = tmp1 - tmp2; + tmp1 = tmpRn(2); + tmp2 = tmpRm(2); + GE3 = tmp2 <= tmp1; + b3:1 = tmp1 - tmp2; + tmp1 = tmpRn(3); + tmp2 = tmpRm(3); + GE4 = tmp2 <= tmp1; + b4:1 = tmp1 - tmp2; + Rd = (zext(b4) << 24) | (zext(b3) << 16) | (zext(b2) << 8) | zext(b1); +} + +:uxtab^COND Rd,Rn,ror1 is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=6 & c0407=7 & Rd & Rn & ror1 +{ + build COND; + build ror1; + Rd = Rn + zext(ror1:1); +} + +:uxtab16^COND Rd,Rn,ror1 is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=4 & c0407=7 & Rd & Rn & ror1 +{ + build COND; + build ror1; + local tmp1 = ror1 & 0xff; + local tmp2 = (ror1 >> 16) & 0xff; + local tmp1n = (Rn + tmp1) & 0xffff; + local tmp2n = (Rn >> 16) + tmp2; + Rd = (tmp2n << 16) | tmp1n; +} + +:uxtah^COND Rd,Rn,ror1 is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=7 & c0407=7 & Rd & Rn & ror1 +{ + build COND; + build ror1; + Rd = Rn + zext(ror1:2); +} + +:uxtb^COND Rd,ror1 is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=6 & c0407=7 & Rd & c1619=15 & ror1 +{ + build COND; + build ror1; + Rd = ror1 & 0x0ff; +} + +:uxtb16^COND Rd,ror1 is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=4 & c0407=7 & Rd & c1619=15 & ror1 +{ + build COND; + build ror1; + Rd = ror1 & 0x0ff00ff; +} + +:uxth^COND Rd,ror1 is $(AMODE) & ARMcond=1 & COND & c2327=13 & c2022=7 & c0407=7 & Rd & c1619=15 & ror1 +{ + build COND; + build ror1; + Rd = ror1 & 0x0ffff; +} + +@endif # VERSION_6 + +# :v* Advanced SIMD and VFP instructions - see ARMneon.sinc + +@if defined(VERSION_6K) + +:wfe^COND is $(AMODE) & ARMcond=1 & COND & c0027=0x320f002 +{ + build COND; + WaitForEvent(); +} + +:wfi^COND is $(AMODE) & ARMcond=1 & COND & c0027=0x320f003 +{ + build COND; + WaitForInterrupt(); +} + +:yield^COND is $(AMODE) & ARMcond=1 & COND & c0027=0x320f001 +{ + build COND; + HintYield(); +} + +@endif # VERSION_6K + +## Some special pseudo ops for better distinguishing +## indirect calls, and returns + +#:callx rm is $(AMODE) & pref=0xe1a0e00f; cond=14 & c2027=18 & c1619=15 & c1215=15 & c0811=15 & c0407=1 & rm +#{ +# lr = inst_next + 8; +# TB=(rm&0x00000001)!=0; +# tmp=rm&0xfffffffe; +# call [tmp]; +# TB=0; +#} # Optional change to THUMB + +#:call^COND^SBIT_CZNO shift1 is $(AMODE) & pref=0xe1a0e00f; COND & c2124=13 & SBIT_CZNO & c1619=0 & Rd=15 & c2627=0 & shift1 +#{ +# lr = inst_next + 8; +# build COND; +# build shift1; +# pc = shift1; +# resultflags(pc); +# logicflags(); +# build SBIT_CZNO; +# call [pc]; +#} + +#:call^COND^SBIT_CZNO shift2 is $(AMODE) & pref=0xe1a0e00f; COND & c2124=13 & SBIT_CZNO & c1619=0 & Rd=15 & c2627=0 & shift2 +#{ +# lr = inst_next + 8; +# build COND; +# build shift2; +# pc = shift2; +# resultflags(pc); +# logicflags(); +# build SBIT_CZNO; +# call [pc]; +#} + +#:call^COND^SBIT_CZNO shift3 is $(AMODE) & pref=0xe1a0e00f; COND & c2124=13 & SBIT_CZNO & c1619=0 & Rd=15 & c2627=0 & shift3 +#{ +# lr = inst_next + 8; +# build COND; +# build shift3; +# pc = shift3; +# resultflags(pc); +# logicflags(); +# build SBIT_CZNO; +# call [pc]; +#} + + +} # End with : ARMcondCk=1 + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARMneon.dwarf b/python/icicle/Ghidra/Processors/ARM/data/languages/ARMneon.dwarf new file mode 100644 index 0000000..fa2ff76 --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARMneon.dwarf @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARMneon.sinc b/python/icicle/Ghidra/Processors/ARM/data/languages/ARMneon.sinc new file mode 100644 index 0000000..ff8a9da --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARMneon.sinc @@ -0,0 +1,6141 @@ +# Advanced SIMD support / NEON + +# WARNING NOTE: Be very careful taking a subpiece or truncating a register with :# or (#) +# The LEBE hybrid language causes endian issues if you do not assign the register to a temp +# variable and then take a subpiece or truncate. +# + +@define FPSCR_RMODE "fpscr[22,2]" + +@define TMODE_E "TMode=1 & thv_c2831=14" # check for neon instructions in thumb mode +@define TMODE_F "TMode=1 & thv_c2831=15" +@define TMODE_EorF "TMode=1 & thv_c2931=7" + +# The RM field is bits 22 and 23 of FPSCR +@define FPSCR_RMODE "fpscr[21,2]" + +zero: "#0" is c0000 { export 0:8; } + +@if defined(SIMD) + +attach variables [ thv_Rm ] [ r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 sp lr pc ]; + +attach variables [ Qn0 Qd0 Qm0 thv_Qn0 thv_Qd0 thv_Qm0 ] [ q0 _ q1 _ q2 _ q3 _ q4 _ q5 _ q6 _ q7 _ ]; +attach variables [ Qn1 Qd1 Qm1 thv_Qn1 thv_Qd1 thv_Qm1 ] [ q8 _ q9 _ q10 _ q11 _ q12 _ q13 _ q14 _ q15 _ ]; + +Qd: Qd0 is TMode=0 & Qd0 & D22=0 { export Qd0; } +Qd: Qd1 is TMode=0 & Qd1 & D22=1 { export Qd1; } +Qd: thv_Qd0 is TMode=1 & thv_Qd0 & thv_D22=0 { export thv_Qd0; } +Qd: thv_Qd1 is TMode=1 & thv_Qd1 & thv_D22=1 { export thv_Qd1; } + +Qn: Qn0 is TMode=0 & Qn0 & N7=0 { export Qn0; } +Qn: Qn1 is TMode=0 & Qn1 & N7=1 { export Qn1; } +Qn: thv_Qn0 is TMode=1 & thv_Qn0 & thv_N7=0 { export thv_Qn0; } +Qn: thv_Qn1 is TMode=1 & thv_Qn1 & thv_N7=1 { export thv_Qn1; } + +Qm: Qm0 is TMode=0 & Qm0 & M5=0 { export Qm0; } +Qm: Qm1 is TMode=0 & Qm1 & M5=1 { export Qm1; } +Qm: thv_Qm0 is TMode=1 & thv_Qm0 & thv_M5=0 { export thv_Qm0; } +Qm: thv_Qm1 is TMode=1 & thv_Qm1 & thv_M5=1 { export thv_Qm1; } + +@endif # SIMD + +@if defined(SIMD) || defined(VFPv3) || defined(VFPv2) + +attach variables [ Dm_3 thv_Dm_3 ] [ d0 d1 d2 d3 d4 d5 d6 d7 ]; + +attach variables [ Dn0 Dd0 Dm0 Dm_4 thv_Dn0 thv_Dd0 thv_Dm0 thv_Dm_4 ] [ d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ]; +attach variables [ thv_Dd_1 Dd_1 ] [ d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ]; +attach variables [ thv_Dd_2 Dd_2 ] [ d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 _ ]; +attach variables [ thv_Dd_3 Dd_3 ] [ d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 _ _ ]; +attach variables [ thv_Dd_4 Dd_4 ] [ d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 _ _ _ ]; +attach variables [ thv_Dd_5 Dd_5 ] [ d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 _ _ _ _ ]; +attach variables [ thv_Dd_6 Dd_6 ] [ d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 _ _ _ _ _ ]; +attach variables [ thv_Dd_7 Dd_7 ] [ d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 _ _ _ _ _ _ ]; +attach variables [ thv_Dd_8 Dd_8 ] [ d7 d8 d9 d10 d11 d12 d13 d14 d15 _ _ _ _ _ _ _ ]; +attach variables [ thv_Dd_9 Dd_9 ] [ d8 d9 d10 d11 d12 d13 d14 d15 _ _ _ _ _ _ _ _ ]; +attach variables [ thv_Dd_10 Dd_10 ] [ d9 d10 d11 d12 d13 d14 d15 _ _ _ _ _ _ _ _ _ ]; +attach variables [ thv_Dd_11 Dd_11 ] [ d10 d11 d12 d13 d14 d15 _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ thv_Dd_12 Dd_12 ] [ d11 d12 d13 d14 d15 _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ thv_Dd_13 Dd_13 ] [ d12 d13 d14 d15 _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ thv_Dd_14 Dd_14 ] [ d13 d14 d15 _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ thv_Dd_15 Dd_15 ] [ d14 d15 _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; +attach variables [ thv_Dd_16 Dd_16 ] [ d15 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ]; + +Dd: Dd0 is TMode=0 & Dd0 & D22=0 { export Dd0; } +Dn: Dn0 is TMode=0 & Dn0 & N7=0 { export Dn0; } +Dm: Dm0 is TMode=0 & Dm0 & M5=0 { export Dm0; } +Dd: thv_Dd0 is TMode=1 & thv_Dd0 & thv_D22=0 { export thv_Dd0; } +Dn: thv_Dn0 is TMode=1 & thv_Dn0 & thv_N7=0 { export thv_Dn0; } +Dm: thv_Dm0 is TMode=1 & thv_Dm0 & thv_M5=0 { export thv_Dm0; } + +Dd2: Dd is Dd { export Dd; } + +@endif # SIMD || VFPv3 || VFPv2 + +@if defined(SIMD) || defined(VFPv3) + +attach variables [ Dn1 Dd1 Dm1 thv_Dn1 thv_Dd1 thv_Dm1 ] [ d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 ]; + +Dd: Dd1 is TMode=0 & Dd1 & D22=1 { export Dd1; } +Dn: Dn1 is TMode=0 & Dn1 & N7=1 { export Dn1; } +Dm: Dm1 is TMode=0 & Dm1 & M5=1 { export Dm1; } +Dd: thv_Dd1 is TMode=1 & thv_Dd1 & thv_D22=1 { export thv_Dd1; } +Dn: thv_Dn1 is TMode=1 & thv_Dn1 & thv_N7=1 { export thv_Dn1; } +Dm: thv_Dm1 is TMode=1 & thv_Dm1 & thv_M5=1 { export thv_Dm1; } + +attach variables [ Sm0_3 thv_Sm0_3 ][s0 s2 s4 s6 s8 s10 s12 s14]; +attach variables [ Sm1_3 thv_Sm1_3][s1 s3 s5 s7 s9 s11 s13 s15]; + +Sm_3: Sm0_3 is TMode=0 & Sm0_3 & M5=0 { export Sm0_3; } +Sm_3: Sm1_3 is TMode=0 & Sm1_3 & M5=1 { export Sm1_3; } +Sm_3: thv_Sm0_3 is TMode=1 & thv_Sm0_3 & M5=0 { export thv_Sm0_3; } +Sm_3: thv_Sm1_3 is TMode=1 & thv_Sm1_3 & M5=1 { export thv_Sm1_3; } + +@endif # SIMD || VFPv3 + +@if defined(VFPv2) || defined(VFPv3) + +attach variables [ Sn0 Sd0 Sm0 thv_Sn0 thv_Sd0 thv_Sm0 ] [ s0 s2 s4 s6 s8 s10 s12 s14 s16 s18 s20 s22 s24 s26 s28 s30 ]; +attach variables [ Sn1 Sd1 Sm1 thv_Sn1 thv_Sd1 thv_Sm1 ] [ s1 s3 s5 s7 s9 s11 s13 s15 s17 s19 s21 s23 s25 s27 s29 s31 ]; + +attach variables [ Sm0next thv_Sm0next ] [ s1 s3 s5 s7 s9 s11 s13 s15 s17 s19 s21 s23 s25 s27 s29 s31 ]; +attach variables [ Sm1next thv_Sm1next ] [ s2 s4 s6 s8 s10 s12 s14 s16 s18 s20 s22 s24 s26 s28 s30 _ ]; + +# We need to create separate constructors for each register rather than attaching +# directly to a context variable +@if defined (VFPv2) || defined(SIMD) +Sreg: s0 is s0 & regNum=0 { export s0; } +Sreg: s1 is s1 & regNum=1 { export s1; } +Sreg: s2 is s2 & regNum=2 { export s2; } +Sreg: s3 is s3 & regNum=3 { export s3; } +Sreg: s4 is s4 & regNum=4 { export s4; } +Sreg: s5 is s5 & regNum=5 { export s5; } +Sreg: s6 is s6 & regNum=6 { export s6; } +Sreg: s7 is s7 & regNum=7 { export s7; } +Sreg: s8 is s8 & regNum=8 { export s8; } +Sreg: s9 is s9 & regNum=9 { export s9; } +Sreg: s10 is s10 & regNum=10 { export s10; } +Sreg: s11 is s11 & regNum=11 { export s11; } +Sreg: s12 is s12 & regNum=12 { export s12; } +Sreg: s13 is s13 & regNum=13 { export s13; } +Sreg: s14 is s14 & regNum=14 { export s14; } +Sreg: s15 is s15 & regNum=15 { export s15; } +Sreg: s16 is s16 & regNum=16 { export s16; } +Sreg: s17 is s17 & regNum=17 { export s17; } +Sreg: s18 is s18 & regNum=18 { export s18; } +Sreg: s19 is s19 & regNum=19 { export s19; } +Sreg: s20 is s20 & regNum=20 { export s20; } +Sreg: s21 is s21 & regNum=21 { export s21; } +Sreg: s22 is s22 & regNum=22 { export s22; } +Sreg: s23 is s23 & regNum=23 { export s23; } +Sreg: s24 is s24 & regNum=24 { export s24; } +Sreg: s25 is s25 & regNum=25 { export s25; } +Sreg: s26 is s26 & regNum=26 { export s26; } +Sreg: s27 is s27 & regNum=27 { export s27; } +Sreg: s28 is s28 & regNum=28 { export s28; } +Sreg: s29 is s29 & regNum=29 { export s29; } +Sreg: s30 is s30 & regNum=30 { export s30; } +Sreg: s31 is s31 & regNum=31 { export s31; } + +Sreg2: s0 is s0 & reg2Num=0 { export s0; } +Sreg2: s1 is s1 & reg2Num=1 { export s1; } +Sreg2: s2 is s2 & reg2Num=2 { export s2; } +Sreg2: s3 is s3 & reg2Num=3 { export s3; } +Sreg2: s4 is s4 & reg2Num=4 { export s4; } +Sreg2: s5 is s5 & reg2Num=5 { export s5; } +Sreg2: s6 is s6 & reg2Num=6 { export s6; } +Sreg2: s7 is s7 & reg2Num=7 { export s7; } +Sreg2: s8 is s8 & reg2Num=8 { export s8; } +Sreg2: s9 is s9 & reg2Num=9 { export s9; } +Sreg2: s10 is s10 & reg2Num=10 { export s10; } +Sreg2: s11 is s11 & reg2Num=11 { export s11; } +Sreg2: s12 is s12 & reg2Num=12 { export s12; } +Sreg2: s13 is s13 & reg2Num=13 { export s13; } +Sreg2: s14 is s14 & reg2Num=14 { export s14; } +Sreg2: s15 is s15 & reg2Num=15 { export s15; } +Sreg2: s16 is s16 & reg2Num=16 { export s16; } +Sreg2: s17 is s17 & reg2Num=17 { export s17; } +Sreg2: s18 is s18 & reg2Num=18 { export s18; } +Sreg2: s19 is s19 & reg2Num=19 { export s19; } +Sreg2: s20 is s20 & reg2Num=20 { export s20; } +Sreg2: s21 is s21 & reg2Num=21 { export s21; } +Sreg2: s22 is s22 & reg2Num=22 { export s22; } +Sreg2: s23 is s23 & reg2Num=23 { export s23; } +Sreg2: s24 is s24 & reg2Num=24 { export s24; } +Sreg2: s25 is s25 & reg2Num=25 { export s25; } +Sreg2: s26 is s26 & reg2Num=26 { export s26; } +Sreg2: s27 is s27 & reg2Num=27 { export s27; } +Sreg2: s28 is s28 & reg2Num=28 { export s28; } +Sreg2: s29 is s29 & reg2Num=29 { export s29; } +Sreg2: s30 is s30 & reg2Num=30 { export s30; } +Sreg2: s31 is s31 & reg2Num=31 { export s31; } + +Dreg: d0 is d0 & regNum=0 { export d0; } +Dreg: d1 is d1 & regNum=1 { export d1; } +Dreg: d2 is d2 & regNum=2 { export d2; } +Dreg: d3 is d3 & regNum=3 { export d3; } +Dreg: d4 is d4 & regNum=4 { export d4; } +Dreg: d5 is d5 & regNum=5 { export d5; } +Dreg: d6 is d6 & regNum=6 { export d6; } +Dreg: d7 is d7 & regNum=7 { export d7; } +Dreg: d8 is d8 & regNum=8 { export d8; } +Dreg: d9 is d9 & regNum=9 { export d9; } +Dreg: d10 is d10 & regNum=10 { export d10; } +Dreg: d11 is d11 & regNum=11 { export d11; } +Dreg: d12 is d12 & regNum=12 { export d12; } +Dreg: d13 is d13 & regNum=13 { export d13; } +Dreg: d14 is d14 & regNum=14 { export d14; } +Dreg: d15 is d15 & regNum=15 { export d15; } +Dreg2: d0 is d0 & reg2Num=0 { export d0; } +Dreg2: d1 is d1 & reg2Num=1 { export d1; } +Dreg2: d2 is d2 & reg2Num=2 { export d2; } +Dreg2: d3 is d3 & reg2Num=3 { export d3; } +Dreg2: d4 is d4 & reg2Num=4 { export d4; } +Dreg2: d5 is d5 & reg2Num=5 { export d5; } +Dreg2: d6 is d6 & reg2Num=6 { export d6; } +Dreg2: d7 is d7 & reg2Num=7 { export d7; } +Dreg2: d8 is d8 & reg2Num=8 { export d8; } +Dreg2: d9 is d9 & reg2Num=9 { export d9; } +Dreg2: d10 is d10 & reg2Num=10 { export d10; } +Dreg2: d11 is d11 & reg2Num=11 { export d11; } +Dreg2: d12 is d12 & reg2Num=12 { export d12; } +Dreg2: d13 is d13 & reg2Num=13 { export d13; } +Dreg2: d14 is d14 & reg2Num=14 { export d14; } +Dreg2: d15 is d15 & reg2Num=15 { export d15; } +@if defined(SIMD) || defined(VFPv3) +Dreg: d16 is d16 & regNum=16 { export d16; } +Dreg: d17 is d17 & regNum=17 { export d17; } +Dreg: d18 is d18 & regNum=18 { export d18; } +Dreg: d19 is d19 & regNum=19 { export d19; } +Dreg: d20 is d20 & regNum=20 { export d20; } +Dreg: d21 is d21 & regNum=21 { export d21; } +Dreg: d22 is d22 & regNum=22 { export d22; } +Dreg: d23 is d23 & regNum=23 { export d23; } +Dreg: d24 is d24 & regNum=24 { export d24; } +Dreg: d25 is d25 & regNum=25 { export d25; } +Dreg: d26 is d26 & regNum=26 { export d26; } +Dreg: d27 is d27 & regNum=27 { export d27; } +Dreg: d28 is d28 & regNum=28 { export d28; } +Dreg: d29 is d29 & regNum=29 { export d29; } +Dreg: d30 is d30 & regNum=30 { export d30; } +Dreg: d31 is d31 & regNum=31 { export d31; } +Dreg2: d16 is d16 & reg2Num=16 { export d16; } +Dreg2: d17 is d17 & reg2Num=17 { export d17; } +Dreg2: d18 is d18 & reg2Num=18 { export d18; } +Dreg2: d19 is d19 & reg2Num=19 { export d19; } +Dreg2: d20 is d20 & reg2Num=20 { export d20; } +Dreg2: d21 is d21 & reg2Num=21 { export d21; } +Dreg2: d22 is d22 & reg2Num=22 { export d22; } +Dreg2: d23 is d23 & reg2Num=23 { export d23; } +Dreg2: d24 is d24 & reg2Num=24 { export d24; } +Dreg2: d25 is d25 & reg2Num=25 { export d25; } +Dreg2: d26 is d26 & reg2Num=26 { export d26; } +Dreg2: d27 is d27 & reg2Num=27 { export d27; } +Dreg2: d28 is d28 & reg2Num=28 { export d28; } +Dreg2: d29 is d29 & reg2Num=29 { export d29; } +Dreg2: d30 is d30 & reg2Num=30 { export d30; } +Dreg2: d31 is d31 & reg2Num=31 { export d31; } +@else +# this is just a placeholder so the parse patterns will match correctly. +# regNum is 31 when the base pattern matches, and incremented when +# this constructor actually matches +Dreg: d0 is d0 & regNum=31 { export d0; } +Dreg2: d0 is d0 & reg2Num=31 { export d0; } +@endif +@endif + +VRm: Rm is TMode=0 & Rm { export Rm; } +VRm: thv_Rm is TMode=1 & thv_Rm { export thv_Rm; } + +VRn: Rn is TMode=0 & Rn { export Rn; } +VRn: thv_Rn is TMode=1 & thv_Rn { export thv_Rn; } + +VRd: Rd is TMode=0 & Rd { export Rd; } +VRd: thv_Rd is TMode=1 & thv_Rd { export thv_Rd; } + +Sd: Sd0 is TMode=0 & Sd0 & D22=0 { export Sd0; } +Sd: Sd1 is TMode=0 & Sd1 & D22=1 { export Sd1; } +Sd: thv_Sd0 is TMode=1 & thv_Sd0 & thv_D22=0 { export thv_Sd0; } +Sd: thv_Sd1 is TMode=1 & thv_Sd1 & thv_D22=1 { export thv_Sd1; } + +Sn: Sn0 is TMode=0 & Sn0 & N7=0 { export Sn0; } +Sn: Sn1 is TMode=0 & Sn1 & N7=1 { export Sn1; } +Sn: thv_Sn0 is TMode=1 & thv_Sn0 & thv_N7=0 { export thv_Sn0; } +Sn: thv_Sn1 is TMode=1 & thv_Sn1 & thv_N7=1 { export thv_Sn1; } + +Sm: Sm0 is TMode=0 & Sm0 & M5=0 { export Sm0; } +Sm: Sm1 is TMode=0 & Sm1 & M5=1 { export Sm1; } +Sm: thv_Sm0 is TMode=1 & thv_Sm0 & thv_M5=0 { export thv_Sm0; } +Sm: thv_Sm1 is TMode=1 & thv_Sm1 & thv_M5=1 { export thv_Sm1; } + +SmNext: Sm0next is TMode=0 & Sm0next & M5=0 { export Sm0next; } +SmNext: Sm1next is TMode=0 & Sm1next & M5=1 { export Sm1next; } +SmNext: thv_Sm0next is TMode=1 & thv_Sm0next & thv_M5=0 { export thv_Sm0next; } +SmNext: thv_Sm1next is TMode=1 & thv_Sm1next & thv_M5=1 { export thv_Sm1next; } + +Sd2: Sd is Sd { export Sd; } + +@endif # VFPv2 || VFPv3 + +udt: "s" is TMode=0 & c2424=0 { export 0:1; } +udt: "u" is TMode=0 & c2424=1 { export 1:1; } +udt: "s" is TMode=1 & thv_c2828=0 { export 0:1; } +udt: "u" is TMode=1 & thv_c2828=1 { export 1:1; } + +udt7: "s" is TMode=0 & c0707=0 { export 0:1; } +udt7: "u" is TMode=0 & c0707=1 { export 1:1; } +udt7: "s" is TMode=1 & thv_c0707=0 { export 0:1; } +udt7: "u" is TMode=1 & thv_c0707=1 { export 1:1; } + +fdt: "u" is TMode=0 & c0808=0 { export 0:1; } +fdt: "f" is TMode=0 & c0808=1 { export 1:1; } +fdt: "u" is TMode=1 & thv_c0808=0 { export 0:1; } +fdt: "f" is TMode=1 & thv_c0808=1 { export 1:1; } + +esize2021: "8" is TMode=0 & c2021=0 { export 1:4; } +esize2021: "16" is TMode=0 & c2021=1 { export 2:4; } +esize2021: "32" is TMode=0 & c2021=2 { export 4:4; } +esize2021: "64" is TMode=0 & c2021=3 { export 8:4; } +esize2021: "8" is TMode=1 & thv_c2021=0 { export 1:4; } +esize2021: "16" is TMode=1 & thv_c2021=1 { export 2:4; } +esize2021: "32" is TMode=1 & thv_c2021=2 { export 4:4; } +esize2021: "64" is TMode=1 & thv_c2021=3 { export 8:4; } + +esize2021x2: "16" is TMode=0 & c2021=0 { export 2:4; } +esize2021x2: "32" is TMode=0 & c2021=1 { export 4:4; } +esize2021x2: "64" is TMode=0 & c2021=2 { export 8:4; } +esize2021x2: "16" is TMode=1 & thv_c2021=0 { export 2:4; } +esize2021x2: "32" is TMode=1 & thv_c2021=1 { export 4:4; } +esize2021x2: "64" is TMode=1 & thv_c2021=2 { export 8:4; } + +esize1819: "8" is TMode=0 & c1819=0 { export 1:4; } +esize1819: "16" is TMode=0 & c1819=1 { export 2:4; } +esize1819: "32" is TMode=0 & c1819=2 { export 4:4; } +esize1819: "64" is TMode=0 & c1819=3 { export 8:4; } +esize1819: "8" is TMode=1 & thv_c1819=0 { export 1:4; } +esize1819: "16" is TMode=1 & thv_c1819=1 { export 2:4; } +esize1819: "32" is TMode=1 & thv_c1819=2 { export 4:4; } +esize1819: "64" is TMode=1 & thv_c1819=3 { export 8:4; } + +esize1819x2: "16" is TMode=0 & c1819=0 { export 2:4; } +esize1819x2: "32" is TMode=0 & c1819=1 { export 4:4; } +esize1819x2: "64" is TMode=0 & c1819=2 { export 8:4; } +esize1819x2: "16" is TMode=1 & thv_c1819=0 { export 2:4; } +esize1819x2: "32" is TMode=1 & thv_c1819=1 { export 4:4; } +esize1819x2: "64" is TMode=1 & thv_c1819=2 { export 8:4; } + +esize1819x3: "8" is TMode=0 & c1819=0 { export 1:4; } +esize1819x3: "16" is TMode=0 & c1819=1 { export 2:4; } +esize1819x3: "32" is TMode=0 & c1819=2 { export 4:4; } +esize1819x3: "8" is TMode=1 & thv_c1819=0 { export 1:4; } +esize1819x3: "16" is TMode=1 & thv_c1819=1 { export 2:4; } +esize1819x3: "32" is TMode=1 & thv_c1819=2 { export 4:4; } + +esize1011: "8" is TMode=0 & c1011=0 { export 1:4; } +esize1011: "16" is TMode=0 & c1011=1 { export 2:4; } +esize1011: "32" is TMode=0 & c1011=2 { export 4:4; } +esize1011: "64" is TMode=0 & c1011=3 { export 8:4; } +esize1011: "8" is TMode=1 & thv_c1011=0 { export 1:4; } +esize1011: "16" is TMode=1 & thv_c1011=1 { export 2:4; } +esize1011: "32" is TMode=1 & thv_c1011=2 { export 4:4; } +esize1011: "64" is TMode=1 & thv_c1011=3 { export 8:4; } + +esize0607: "8" is TMode=0 & c0607=0 { export 1:4; } +esize0607: "16" is TMode=0 & c0607=1 { export 2:4; } +esize0607: "32" is TMode=0 & c0607=2 { export 4:4; } +esize0607: "64" is TMode=0 & c0607=3 { export 8:4; } # see VLD4 (single 4-element structure to all lanes) +esize0607: "8" is TMode=1 & thv_c0607=0 { export 1:4; } +esize0607: "16" is TMode=1 & thv_c0607=1 { export 2:4; } +esize0607: "32" is TMode=1 & thv_c0607=2 { export 4:4; } +esize0607: "64" is TMode=1 & thv_c0607=3 { export 8:4; } # see VLD4 (single 4-element structure to all lanes) + + +fesize2323: "16" is TMode=0 & c2323=1 { export 4:4; } +fesize2323: "32" is TMode=0 & c2323=0 { export 2:4; } +fesize2323: "16" is TMode=1 & thv_c2323=1 { export 4:4; } +fesize2323: "32" is TMode=1 & thv_c2323=0 { export 2:4; } + +fesize2020: "16" is TMode=0 & c2020=1 { export 4:4; } +fesize2020: "32" is TMode=0 & c2020=0 { export 2:4; } +fesize2020: "16" is TMode=1 & thv_c2020=1 { export 4:4; } +fesize2020: "32" is TMode=1 & thv_c2020=0 { export 2:4; } + +fesize1819: "16" is TMode=0 & c1819=1 { export 4:4; } +fesize1819: "32" is TMode=0 & c1819=2 { export 2:4; } +fesize1819: "16" is TMode=1 & thv_c1819=1 { export 4:4; } +fesize1819: "32" is TMode=1 & thv_c1819=2 { export 2:4; } + +roundType: "a" is TMode=0 & c0809=0 { export 0:1; } +roundType: "a" is TMode=1 & thv_c0809=0 { export 0:1; } +roundType: "n" is TMode=0 & c0809=1 { export 1:1; } +roundType: "n" is TMode=1 & thv_c0809=1 { export 1:1; } +roundType: "p" is TMode=0 & c0809=2 { export 2:1; } +roundType: "p" is TMode=1 & thv_c0809=2 { export 2:1; } +roundType: "m" is TMode=0 & c0809=3 { export 3:1; } +roundType: "m" is TMode=1 & thv_c0809=3 { export 3:1; } + +define pcodeop VFPExpandImmediate; + + + +# float +vfpExpImm_4: imm is TMode=0 & c1919 & c1818 & c1617 & c0003 [ imm = (c1919 << 31) | ((c1818 $xor 1) << 30) | ((c1818 * 0x1f) << 25) | (c1617 << 23) | (c0003 << 19); ] { + export *[const]:4 imm; +} + +# float +vfpExpImm_4: imm is TMode=1 & thv_c1919 & thv_c1818 & thv_c1617 & thv_c0003 [ imm = (thv_c1919 << 31) | ((thv_c1818 $xor 1) << 30) | ((thv_c1818 * 0x1f) << 25) | (thv_c1617 << 23) | (thv_c0003 << 19); ] { + export *[const]:4 imm; +} + + +# double +vfpExpImm_8: imm is TMode=0 & c1919 & c1818 & c1617 & c0003 [ imm = (c1919 << 63) | ((c1818 $xor 1) << 62) | ((c1818 * 0xff) << 54) | (c1617 << 52) | (c0003 << 48); ] { + export *[const]:8 imm; +} + +# double +vfpExpImm_8: imm is TMode=1 & thv_c1919 & thv_c1818 & thv_c1617 & thv_c0003 [ imm = (thv_c1919 << 63) | ((thv_c1818 $xor 1) << 62) | ((thv_c1818 * 0xff) << 54) | (thv_c1617 << 52) | (thv_c0003 << 48); ] { + export *[const]:8 imm; +} + +define pcodeop SIMDExpandImmediate; + +simdExpImm_8: "#0" is TMode=0 & c2424=0 & c1618=0 & c0003=0 { + export 0:8; +} +simdExpImm_8: "simdExpand("^c0505^","^cmode^","^val^")" is TMode=0 & c2424 & c1618 & c0505 & c0003 & cmode [ val = (c2424 << 7) | (c1618 << 4) | c0003; ] { + imm64:8 = SIMDExpandImmediate(c0505:1, cmode:1, val:1); + export imm64; +} +simdExpImm_8: "#0" is TMode=1 & thv_c2828=0 & thv_c1618=0 & thv_c0003=0 { + export 0:8; +} +simdExpImm_8: "simdExpand("^thv_c0505^","^thv_cmode^","^val^")" is TMode=1 & thv_c2828 & thv_c1618 & thv_c0505 & thv_c0003 & thv_cmode [ val = (thv_c2828 << 7) | (thv_c1618 << 4) | thv_c0003; ] { + imm64:8 = SIMDExpandImmediate(thv_c0505:1, thv_cmode:1, val:1); + export imm64; +} + +simdExpImm_16: "#0" is TMode=0 & c2424=0 & c1618=0 & c0003=0 { + tmp:8 = 0; + tmp1:16 = zext(tmp); + export tmp1; +} +simdExpImm_16: "simdExpand("^c0505^","^cmode^","^val^")" is TMode=0 & c2424 & c1618 & c0505 & c0003 & cmode [ val = (c2424 << 7) | (c1618 << 4) | c0003; ] { + imm128:16 = SIMDExpandImmediate(c0505:1, cmode:1, val:1); + export imm128; +} +simdExpImm_16: "#0" is TMode=1 & thv_c2828=0 & thv_c1618=0 & thv_c0003=0 { + tmp:8 = 0; + tmp1:16 = zext(tmp); + export tmp1; +} +simdExpImm_16: "simdExpand("^thv_c0505^","^thv_cmode^","^val^")" is TMode=1 & thv_c2828 & thv_c1618 & thv_c0505 & thv_c0003 & thv_cmode [ val = (thv_c2828 << 7) | (thv_c1618 << 4) | thv_c0003; ] { + imm128:16 = SIMDExpandImmediate(thv_c0505:1, thv_cmode:1, val:1); + export imm128; +} + +simdExpImmDT: "i32" is TMode=0 & c0911=0 { } +simdExpImmDT: "i32" is TMode=0 & c0911=1 { } +simdExpImmDT: "i32" is TMode=0 & c0911=2 { } +simdExpImmDT: "i32" is TMode=0 & c0911=3 { } +simdExpImmDT: "i16" is TMode=0 & c0911=4 { } +simdExpImmDT: "i16" is TMode=0 & c0911=5 { } +simdExpImmDT: "i32" is TMode=0 & c0811=12 { } +simdExpImmDT: "i32" is TMode=0 & c0811=13 { } +simdExpImmDT: "i8" is TMode=0 & c0811=14 & c0505=0 { } +simdExpImmDT: "i64" is TMode=0 & c0811=14 & c0505=1 { } +simdExpImmDT: "f32" is TMode=0 & c0811=15 & c0505=0 { } + +simdExpImmDT: "i32" is TMode=1 & thv_c0911=0 { } +simdExpImmDT: "i32" is TMode=1 & thv_c0911=1 { } +simdExpImmDT: "i32" is TMode=1 & thv_c0911=2 { } +simdExpImmDT: "i32" is TMode=1 & thv_c0911=3 { } +simdExpImmDT: "i16" is TMode=1 & thv_c0911=4 { } +simdExpImmDT: "i16" is TMode=1 & thv_c0911=5 { } +simdExpImmDT: "i32" is TMode=1 & thv_c0811=12 { } +simdExpImmDT: "i32" is TMode=1 & thv_c0811=13 { } +simdExpImmDT: "i8" is TMode=1 & thv_c0811=14 & thv_c0505=0 { } +simdExpImmDT: "i64" is TMode=1 & thv_c0811=14 & thv_c0505=1 { } +simdExpImmDT: "f32" is TMode=1 & thv_c0811=15 & thv_c0505=0 { } + +macro replicate1to8(bytes, dest) { + local val:8 = zext(bytes); + val = val | (val << 8); + val = val | (val << 16); + dest = val | (val << 32); +} + +macro replicate2to8(bytes, dest) { + local val:8 = zext(bytes); + val = val | (val << 16); + dest = val | (val << 32); +} + +macro replicate4to8(bytes, dest) { + local val:8 = zext(bytes); + dest = val | (val << 32); +} + +define pcodeop VectorAbsoluteDifferenceAndAccumulate; +define pcodeop VectorAbsoluteDifference; +define pcodeop FloatVectorAbsoluteDifference; +define pcodeop VectorAbsolute; +define pcodeop FloatVectorAbsolute; + +@if defined(SIMD) +# CryptOp(val) +# Various crypto algorithms, too numerous for explication at +# this time + +define pcodeop CryptOp; +####### +# AESD single round decryption + +define pcodeop AESInvShiftRows; +define pcodeop AESInvSubBytes; +# F6.1.1 p3235 A1/T1 +:aesd.8 Qd,Qm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b00 & c1617=0b00 & c0611=0b001101 & c0404=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b00 & thv_c1617=0b00 & thv_c0611=0b001101 & thv_c0404=0)) + & Qd & Qm +{ + local shiftRows:16 = AESInvShiftRows(Qd ^ Qm); + Qd = AESInvSubBytes(shiftRows); +} + +####### +# AESE single round encryption + +define pcodeop AESShiftRows; +define pcodeop AESSubBytes; +# F6.1.2 p3237 A1/T1 +:aese.8 Qd,Qm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b00 & c1617=0b00 & c0611=0b001100 & c0404=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b00 & thv_c1617=0b00 & thv_c0611=0b001100 & thv_c0404=0)) + & Qd & Qm +{ + local shiftRows:16 = AESInvShiftRows(Qd ^ Qm); + Qd = AESSubBytes(shiftRows); +} + +####### +# AESIMC inverse mix columns + +define pcodeop AESInvMixColumns; +# F6.1.3 p3239 A1/T1 +:aesimc.8 Qd,Qm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b00 & c1617=0b00 & c0611=0b001111 & c0404=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b00 & thv_c1617=0b00 & thv_c0611=0b001111 & thv_c0404=0)) + & Qd & Qm +{ + Qd = AESInvMixColumns(Qm); +} + +####### +# AESMC mix columns + +define pcodeop AESMixColumns; +# F6.1.4 p3240 A1/T1 +:aesmc.8 Qd,Qm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b00 & c1617=0b00 & c0611=0b001110 & c0404=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b00 & thv_c1617=0b00 & thv_c0611=0b001110 & thv_c0404=0)) + & Qd & Qm +{ + Qd = AESMixColumns(Qm); +} + +####### +# SHA1C SHA1 hash update (choose) + +define pcodeop SHA1HashUpdateChoose; +# F6.1.7 p3248 A1/T1 +:sha1c.32 Qd,Qn,Qm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00100 & c2021=0b00 & c0811=0b1100 & c0606=1 & c0404=0) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0)) + & Qn & Qd & Qm +{ + local X = Qd; + local Y = Qn:4; + local W = Qm; + Qd = SHA1HashUpdateChoose(X, Y, W); +} + +####### +# SHA1H SHA1 fixed rotate + +# F6.1.8 p3250 A1/T1 +:sha1h.32 Qd,Qm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b01 & c0611=0b001011 & c0404=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b01 & thv_c0611=0b001011 & thv_c0404=0)) + & Qd & Qm +{ + local W:4 = Qm(0); + Qd = zext(W << 30 | W >> 2); +} + +####### +# SHA1M SHA1 hash update (majority) + +define pcodeop SHA1HashUpdateMajority; +# F6.1.9 p3251 A1/T1 +:sha1m.32 Qd,Qn,Qm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00100 & c2021=0b10 & c0811=0b1100 & c0606=1 & c0404=0) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0)) + & Qn & Qd & Qm +{ + local X = Qd; + local Y = Qn:4; + local W = Qm; + Qd = SHA1HashUpdateMajority(X, Y, W); +} + +####### +# SHA1P SHA1 hash update (parity) + +define pcodeop SHA1HashUpdateParity; +# F6.1.10 p3253 A1/T1 +:sha1p.32 Qd,Qn,Qm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00100 & c2021=0b01 & c0811=0b1100 & c0606=1 & c0404=0) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0)) + & Qn & Qd & Qm +{ + local X = Qd; + local Y = Qn:4; + local W = Qm; + Qd = SHA1HashUpdateParity(X, Y, W); +} + +####### +# SHA1SU0 SHA1 schedule update 0 + +# F6.1.11 p3255 A1/T1 +:sha1su0.32 Qd,Qn,Qm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00100 & c2021=0b11 & c0811=0b1100 & c0606=1 & c0404=0) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11110 & thv_c2021=0b11 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0)) + & Qn & Qd & Qm +{ + local op1 = Qd; + local op2 = Qn; + local op3 = Qm; + local op2lo:8 = op2(0); + local op1hi:8 = op1(8); + op2 = zext(op2lo << 64) | zext(op1hi); + Qd = op1 ^ op2 ^ op3; +} + +####### +# SHA1SU1 SHA1 schedule update 1 + +# F6.1.12 p3257 A1/T1 +:sha1su1.32 Qd,Qm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b10 & c0611=0b001110 & c0404=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b10 & thv_c0611=0b001110 & thv_c0404=0)) + & Qd & Qm +{ + local X = Qd; + local Y = Qm; + local Tm = X ^ (Y >> 32); + local t0:4 = Tm(0); + local t1:4 = Tm(4); + local t2:4 = Tm(8); + local t3:4 = Tm(12); + local W0:4 = (t0 << 1 | t0 >> 31); + local W1:4 = (t1 << 1 | t1 >> 31); + local W2:4 = (t2 << 1 | t2 >> 31); + local W3:4 = (t3 << 1 | t3 >> 31) ^ (t0 << 2 | t0 >> 30); + Qd = zext(W3 << 96) | zext(W2 << 64) | zext(W1 << 32) | zext(W0); +} + +####### +# SHA256H SHA256 hash update part 1 + +define pcodeop SHA256hash; +# F6.1.13 p3259 A1/T1 +:sha256h.32 Qd,Qn,Qm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1100 & c0606=1 & c0404=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0)) + & Qn & Qd & Qm +{ + local part1:1 = 1; + Qd = SHA256hash(Qd,Qn,Qm, part1); +} + +####### +# SHA256H2 SHA256 hash update part 2 + +# F6.1.14 p3260 A1/T1 +:sha256h2.32 Qd,Qn,Qm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1100 & c0606=1 & c0404=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0)) + & Qn & Qd & Qm +{ + local part1:1 = 0; + Qd = SHA256hash(Qd,Qn,Qm, part1); +} + +####### +# SHA256SU0 SHA256 schedule update 0 + +define pcodeop SHA256ScheduleUpdate0; +# F6.1.15 p3261 A1/T1 +:sha256su0.32 Qd,Qm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b10 & c0611=0b001111 & c0404=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b10 & thv_c0611=0b001111 & thv_c0404=0)) + & Qd & Qm +{ + Qd = SHA256ScheduleUpdate0(Qd,Qm); +} + +####### +# SHA256SU1 SHA256 schedule update 1 + +define pcodeop SHA256ScheduleUpdate1; +# F6.1.16 p3263 A1/T1 +:sha256su1.32 Qd,Qn,Qm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1100 & c0606=1 & c0404=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1100 & thv_c0606=1 & thv_c0404=0)) + & Qn & Qd & Qm +{ + Qd = SHA256ScheduleUpdate1(Qd,Qn,Qm); +} + +# TODO: watch out for c2021=3 + +:vaba.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=7 & Q6=0 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=7 & thv_c0606=0 & thv_c0404=1 ) ) & Dm & Dn & Dd & udt & esize2021 +{ + Dd = VectorAbsoluteDifferenceAndAccumulate(Dn,Dm,esize2021,udt); +} + +:vaba.^udt^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=7 & Q6=1 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=7 & thv_c0606=1 & thv_c0404=1 ) ) & Qd & Qn & Qm & udt & esize2021 +{ + Qd = VectorAbsoluteDifferenceAndAccumulate(Qn,Qm,esize2021,udt); +} + +:vabal.^udt^esize2021 Qd,Dn,Dm is (($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=5 & Q6=0 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=5 & thv_c0606=0 & thv_c0404=0 ) ) & Qd & Dm & Dn & udt & esize2021 +{ + Qd = VectorAbsoluteDifferenceAndAccumulate(Dn,Dm,esize2021,udt); +} + +:vabd.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=7 & Q6=0 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=7 & thv_c0606=0 & thv_c0404=0 ) ) & Dm & Dn & Dd & udt & esize2021 +{ + Dd = VectorAbsoluteDifference(Dn,Dm,esize2021,udt); +} + +:vabd.^udt^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=7 & Q6=1 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=7 & thv_Q6=1 & thv_c0404=0 ) ) & Qd & Qn & Qm & udt & esize2021 +{ + Qd = VectorAbsoluteDifference(Qn,Qm,esize2021,udt); +} + +:vabdl.^udt^esize2021 Qd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=7 & Q6=0 & c0404=0 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=7 & thv_c0606=0 & thv_c0404=0 ) ) & Dm & Dn & Qd & udt & esize2021 +{ + Qd = VectorAbsoluteDifference(Dn,Dm,esize2021,udt); +} + +:vabd.f^fesize2020 Dd,Dn,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c0811=13 & Q6=0 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c0811=13 & thv_c0606=0 & thv_c0404=0 ) ) & fesize2020 & Dd & Dm & Dn +{ + Dd = FloatVectorAbsoluteDifference(Dn,Dm,fesize2020); +} + +:vabd.f^fesize2020 Qd,Qn,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c0811=13 & Q6=1 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c0811=13 & thv_c0606=1 & thv_c0404=0 ) ) & fesize2020 & Qd & Qm & Qn +{ + Qd = FloatVectorAbsoluteDifference(Qn,Qm,fesize2020); +} + +:vabs.s^esize1819 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=6 & Q6=0 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=6 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm & esize1819 +{ + Dd = VectorAbsolute(Dm,esize1819); +} + +:vabs.s^esize1819 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=6 & Q6=1 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=6 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm & esize1819 +{ + Qd = VectorAbsolute(Qm,esize1819); +} + +:vabs.f^esize1819 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=0xe & Q6=0 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=0xe & thv_c0606=0 & thv_c0404=0 ) ) & esize1819 & Dm & Dd +{ + Dd = FloatVectorAbsolute(Dm,esize1819); +} + +:vabs.f^esize1819 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=0xe & Q6=1 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=0xe & thv_c0606=1 & thv_c0404=0 ) ) & esize1819 & Qd & Qm +{ + Qd = FloatVectorAbsolute(Qm,esize1819); +} + +@endif # SIMD + +@if defined(VFPv2) || defined(VFPv3) + +:vabs^COND^".f32" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x30 & c0611=0x2b & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x30 & thv_c0611=0x2b & thv_c0404=0 ) ) & COND & Sm & Sd +{ + build COND; + build Sd; + build Sm; + Sd = abs(Sm); +} + +:vabs^COND^".f64" Dd,Dm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x30 & c0611=0x2f & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x30 & thv_c0611=0x2f & thv_c0404=0 ) ) & COND & Dd & Dm +{ + build COND; + build Dd; + build Dm; + Dd = abs(Dm); +} + +@endif # VFPv2 || VFPv3 + +define pcodeop FloatCompareGE; +define pcodeop FloatCompareGT; +define pcodeop VectorAbs; +define pcodeop VectorAdd; +define pcodeop VectorSub; +define pcodeop FloatVectorAdd; +define pcodeop VectorPairwiseAdd; +define pcodeop VectorPairwiseMin; +define pcodeop VectorPairwiseMax; +define pcodeop FloatVectorPairwiseAdd; +define pcodeop FloatVectorPairwiseMin; +define pcodeop FloatVectorPairwiseMax; +define pcodeop VectorPairwiseAddLong; +define pcodeop VectorPairwiseAddAccumulateLong; +define pcodeop VectorGetElement; + +@if defined(SIMD) + +:vacge.f^fesize2020 Dd,Dn,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2121=0 & c0811=14 & Q6=0 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=0 & thv_c0811=14 & thv_c0606=0 & thv_c0404=1 ) ) & fesize2020 & Dn & Dd & Dm +{ + Dd = FloatCompareGE(Dn,Dm,fesize2020); +} + +:vacge.f^fesize2020 Qd,Qn,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2121=0 & c0811=14 & Q6=1 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=0 & thv_c0811=14 & thv_c0606=1 & thv_c0404=1 ) ) & fesize2020 & Qn & Qd & Qm +{ + Qd = FloatCompareGE(Qn,Qm,fesize2020); +} + +:vacgt.f^fesize2020 Dd,Dn,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2121=1 & c0811=14 & Q6=0 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=1 & thv_c0811=14 & thv_c0606=0 & thv_c0404=1 ) ) & fesize2020 & Dn & Dd & Dm +{ + Dd = FloatCompareGT(Dn,Dm,fesize2020); +} + +:vacgt.f^fesize2020 Qd,Qn,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2121=1 & c0811=14 & Q6=1 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=1 & thv_c0811=14 & thv_c0606=1 & thv_c0404=1 ) ) & fesize2020 & Qn & Qd & Qm +{ + Qd = FloatCompareGT(Qn,Qm,fesize2020); +} + +:vadd.i^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c0811=8 & Q6=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=8 & thv_Q6=0 & thv_c0404=0)) & esize2021 & Dn & Dd & Dm +{ + Dd = VectorAdd(Dn,Dm,esize2021); +} + +:vadd.i^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c0811=8 & Q6=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=8 & thv_Q6=1 & thv_c0404=0)) & esize2021 & Qm & Qn & Qd +{ + Qd = VectorAdd(Qn,Qm,esize2021); +} + +:vadd.f^fesize2020 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2121=0 & c0811=13 & Q6=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2121=0 & thv_c0811=13 & thv_Q6=0 & thv_c0404=0) ) & fesize2020 & Dm & Dn & Dd +{ + Dd = FloatVectorAdd(Dn,Dm,fesize2020); +} + +:vadd.f^fesize2020 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2121=0 & c0811=13 & Q6=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2121=0 & thv_c0811=13 & thv_Q6=1 & thv_c0404=0) ) & fesize2020 & Qn & Qd & Qm +{ + Qd = FloatVectorAdd(Qn,Qm,fesize2020); +} + +:vpadd.i^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c0811=11 & Q6=0 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=11 & thv_Q6=0 & thv_c0404=1)) & esize2021 & Dn & Dd & Dm +{ + Dd = VectorPairwiseAdd(Dn,Dm,esize2021); +} + +:vpadd.i^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021<3 & c0811=11 & Q6=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=11 & thv_Q6=1 & thv_c0404=1) ) & esize2021 & Qm & Qn & Qd +{ + Qd = VectorPairwiseAdd(Qn,Qm,esize2021); +} + +:vpadd.f^fesize2020 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2121=0 & c0811=13 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=0 & thv_c0811=13 & thv_Q6=0 & thv_c0404=0) ) & fesize2020 & Dm& Dn & Dd +{ + Dd = FloatVectorPairwiseAdd(Dn,Dm,fesize2020:1); +} + + +:vpmax.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=10 & Q6=0 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=10 & thv_Q6=0 & thv_c0404=0)) & udt & esize2021 & Dn & Dd & Dm +{ + Dd = VectorPairwiseMax(Dn,Dm,esize2021,udt); +} + + +:vpmax.f^fesize2020 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2121=0 & c0811=15 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=0 & thv_c0811=15 & thv_Q6=0 & thv_c0404=0) ) & fesize2020 & Dm & Dn & Dd +{ + Dd = FloatVectorPairwiseMax(Dn,Dm,fesize2020:1); +} + +:vpmin.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=10 & Q6=0 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=10 & thv_Q6=0 & thv_c0404=1)) & udt & esize2021 & Dn & Dd & Dm +{ + Dd = VectorPairwiseMin(Dn,Dm,esize2021,udt); +} + +:vpmin.f^fesize2020 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2121=1 & c0811=15 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=1 & thv_c0811=15 & thv_Q6=0 & thv_c0404=0) ) & fesize2020 & Dm & Dn & Dd +{ + Dd = FloatVectorPairwiseMin(Dn,Dm,fesize2020); +} + +:vpadal.^udt7^esize1819 Dd,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0811=6 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0811=6 & thv_Q6=0 & thv_c0404=0)) & udt7 & esize1819 & Dd & Dm +{ + Dd = VectorPairwiseAddAccumulateLong(Dm,esize1819); +} + +:vpadal.^udt7^esize1819 Qd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0811=6 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0811=6 & thv_Q6=1 & thv_c0404=0)) & udt7 & esize1819 & Qd & Qm +{ + Qd = VectorPairwiseAddAccumulateLong(Qm,esize1819); +} + +:vpaddl.^udt7^esize1819 Dd,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0811=2 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0811=2 & thv_Q6=0 & thv_c0404=0)) & udt7 & esize1819 & Dd & Dm +{ + Dd = VectorPairwiseAddLong(Dm,esize1819); +} + +:vpaddl.^udt7^esize1819 Qd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0811=2 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0811=2 & thv_Q6=1 & thv_c0404=0)) & udt7 & esize1819 & Qd & Qm +{ + Qd = VectorPairwiseAddLong(Qm,esize1819); +} + +@endif # SIMD + +@if defined(VFPv2) || defined(VFPv3) + +:vadd^COND^".f16" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=3 & c0811=9 & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=3 & thv_c0811=9 & thv_c0606=0 & thv_c0404=0) ) & COND & Sm & Sd & Sn +{ + build COND; + build Sd; + build Sm; + build Sn; + local result:2 = Sn(0) f+ Sm(0); + Sd = zext(result); +} + +:vadd^COND^".f32" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=3 & c0811=10 & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=3 & thv_c0811=10 & thv_c0606=0 & thv_c0404=0) ) & COND & Sm & Sd & Sn +{ + build COND; + build Sd; + build Sm; + build Sn; + Sd = Sn f+ Sm; +} + +:vadd^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1c & c2021=3 & c0811=11 & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=3 & thv_c0811=11 & thv_c0606=0 & thv_c0404=0) ) & COND & Dm & Dd & Dn +{ + build COND; + build Dd; + build Dm; + build Dn; + Dd = Dn f+ Dm; +} + +@endif # VFPv2 || VFPv3 + +define pcodeop VectorAddReturnHigh; +define pcodeop VectorBitwiseInsertIfFalse; +define pcodeop VectorBitwiseInsertIfTrue; +define pcodeop VectorBitwiseSelect; +define pcodeop VectorCompareEqual; +define pcodeop FloatVectorCompareEqual; +define pcodeop VectorCompareGreaterThanOrEqual; +define pcodeop FloatVectorCompareGreaterThanOrEqual; +define pcodeop VectorCompareGreaterThan; +define pcodeop FloatVectorCompareGreaterThan; +define pcodeop VectorCountLeadingSignBits; +define pcodeop VectorCountLeadingZeros; +define pcodeop VectorComplexAdd; +define pcodeop VectorComplexMultiplyAccumulate; +define pcodeop VectorComplexMultiplyAccumulateByElement; + +@if defined(SIMD) + +:vaddhn.i^esize2021x2 Dd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=5 & c2021<3 & c0811=4 & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=4 & thv_c0606=0 & thv_c0404=0) ) & esize2021x2 & Qn & Dd & Qm +{ + Dd = VectorAddReturnHigh(Qn,Qm,esize2021x2); +} + +:vaddl.^udt^esize2021 Qd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=0 & c0606=0 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=0 & thv_c0606=0 & thv_c0404=0) ) & esize2021 & udt & Dn & Qd & Dm +{ + Qd = VectorAdd(Dn,Dm,esize2021,udt); +} + +:vaddw.^udt^esize2021 Qd,Qn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=1 & c0606=0 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=1 & thv_c0606=0 & thv_c0404=0) ) & esize2021 & udt & Qn & Qd & Dm +{ + Qd = VectorAdd(Qn,Dm,esize2021,udt); +} + + +:vand Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=0 & c0811=1 & Q6=0 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=1 & thv_Q6=0 & thv_c0404=1)) & Dn & Dd & Dm +{ + Dd = Dn & Dm; +} + +:vand Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=0 & c0811=1 & Q6=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=1 & thv_Q6=1 & thv_c0404=1)) & Qn & Qd & Qm +{ + Qd = Qn & Qm; +} + +:vbic.i32 Dd,simdExpImm_8 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1111=0 & c0808=1 & c0407=3 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1111=0 & thv_c0808=1 & thv_c0407=3) ) & Dd & simdExpImm_8 +{ + Dd = Dd & ~simdExpImm_8; +} + +:vbic.i32 Qd,simdExpImm_16 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1111=0 & c0808=1 & c0407=7 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1111=0 & thv_c0808=1 & thv_c0407=7) ) & Qd & simdExpImm_16 +{ + Qd = Qd & ~simdExpImm_16; +} + +:vbic.i16 Dd,simdExpImm_8 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011=2 & c0808=1 & c0407=3 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011=2 & thv_c0808=1 & thv_c0407=3) ) & Dd & simdExpImm_8 +{ + Dd = Dd & ~simdExpImm_8; +} + +:vbic.i16 Qd,simdExpImm_16 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011=2 & c0808=1 & c0407=7 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011=2 & thv_c0808=1 & thv_c0407=7) ) & Qd & simdExpImm_16 +{ + Qd = Qd & ~simdExpImm_16; +} + +:vbic Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=1 & c0811=1 & Q6=0 & c0404=1 ) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=1 & thv_c0811=1 & thv_Q6=0 & thv_c0404=1) ) & Dm & Dn & Dd +{ + Dd = Dn & ~Dm; +} + +:vbic Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=1 & c0811=1 & Q6=1 & c0404=1 ) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=1 & thv_c0811=1 & thv_Q6=1 & thv_c0404=1) ) & Qm & Qn & Qd +{ + Qd = Qn & ~Qm; +} + +:vbif Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2021=3 & c0811=1 & Q6=0 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=3 & thv_c0811=1 & thv_Q6=0 & thv_c0404=1) ) & Dm & Dn & Dd +{ + Dd = VectorBitwiseInsertIfFalse(Dd,Dn,Dm); +} + +:vbif Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2021=3 & c0811=1 & Q6=1 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=3 & thv_c0811=1 & thv_Q6=1 & thv_c0404=1)) & Qm & Qn & Qd +{ + Qd = VectorBitwiseInsertIfFalse(Qd,Qn,Qm); +} + +:vbit Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2021=2 & c0811=1 & Q6=0 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=2 & thv_c0811=1 & thv_Q6=0 & thv_c0404=1)) & Dm & Dn & Dd +{ + Dd = VectorBitwiseInsertIfTrue(Dd,Dn,Dm); +} + +:vbit Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2021=2 & c0811=1 & Q6=1 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=2 & thv_c0811=1 & thv_Q6=1 & thv_c0404=1)) & Qm & Qn & Qd +{ + Qd = VectorBitwiseInsertIfTrue(Qd,Qn,Qm); +} + +:vbsl Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2021=1 & c0811=1 & Q6=0 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=1 & thv_c0811=1 & thv_Q6=0 & thv_c0404=1)) & Dm & Dn & Dd +{ + Dd = VectorBitwiseSelect(Dd,Dn,Dm); +} + +:vbsl Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2021=1 & c0811=1 & Q6=1 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=1 & thv_c0811=1 & thv_Q6=1 & thv_c0404=1)) & Qm & Qn & Qd +{ + Qd = VectorBitwiseSelect(Qd,Qn,Qm); +} + +crot2424: "#"^90 is ($(AMODE) & c2424=0 ) | (TMode=1 & thv_c2424=0) { local tmp:4 = 90; export tmp; } +crot2424: "#"^270 is ($(AMODE) & c2424=1 ) | (TMode=1 & thv_c2424=1) { local tmp:4 = 270; export tmp; } + + +:vcadd.f^fesize2020 Dd,Dn,Dm,crot2424 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=6 & c2323=1 & c2121=0 & c0811=8 & Q6=0 & c0404=1 ) | + ($(TMODE_F) & thv_c2527=6 & thv_c2323=1 & thv_c2121=0 & thv_c0811=8 & thv_Q6=0 & thv_c0404=1)) & crot2424 & fesize2020 & Dm & Dn & Dd +{ + Dd = VectorComplexAdd(Dd,Dn,Dm,crot2424,fesize2020); +} + +:vcadd.f^fesize2020 Qd,Qn,Qm,crot2424 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=6 & c2323=1 & c2121=0 & c0811=8 & Q6=1 & c0404=1 )| + ($(TMODE_F) & thv_c2527=6 & thv_c2323=1 & thv_c2021=0 & thv_c0811=8 & thv_Q6=1 & thv_c0404=1)) & crot2424 & fesize2020 & Qm & Qn & Qd +{ + Qd = VectorComplexAdd(Qd,Qn,Qm,crot2424,fesize2020); +} + + +:vceq.i^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2021<3 & c0811=8 & Q6=0 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=8 & thv_Q6=0 & thv_c0404=1) ) & esize2021 & Dm & Dn & Dd +{ + Dd = VectorCompareEqual(Dn,Dm,esize2021); +} + +:vceq.i^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2021<3 & c0811=8 & Q6=1 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=8 & thv_Q6=1 & thv_c0404=1) ) & esize2021 & Qm & Qn & Qd +{ + Qd = VectorCompareEqual(Qn,Qm,esize2021); +} + +:vceq.f^fesize2020 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c0811=14 & Q6=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=14 & thv_Q6=0 & thv_c0404=0) ) & fesize2020 & Dm & Dn & Dd +{ + Dd = FloatVectorCompareEqual(Dn,Dm,fesize2020); +} + +:vceq.f^fesize2020 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c0811=14 & Q6=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=14 & thv_Q6=1 & thv_c0404=0) ) & fesize2020 & Qm & Qn & Qd +{ + Qd = FloatVectorCompareEqual(Qn,Qm,fesize2020); +} + +:vceq.i^esize1819 Dd,Dm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=2 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=2 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dm & Dd & zero +{ + Dd = VectorCompareEqual(Dm,zero,esize1819); +} + +:vceq.i^esize1819 Qd,Qm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=2 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=2 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qm & Qd & zero +{ + Qd = VectorCompareEqual(Qm,zero,esize1819); +} + +:vceq.f^fesize1819 Dd,Dm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=10 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=10 & thv_Q6=0 & thv_c0404=0) ) & fesize1819 & Dm & Dd & zero +{ + Dd = FloatVectorCompareEqual(Dm,zero,fesize1819); +} + +:vceq.f^fesize1819 Qd,Qm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=1 & c0711=10 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=1 & thv_c0711=10 & thv_Q6=1 & thv_c0404=0) ) & fesize1819 & Qm & Qd & zero +{ + Qd = FloatVectorCompareEqual(Qm,zero,fesize1819); +} + +:vcge.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=3 & Q6=0 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=3 & thv_Q6=0 & thv_c0404=1) ) & udt & esize2021 & Dm & Dn & Dd +{ + Dd = VectorCompareGreaterThanOrEqual(Dn,Dm,esize2021,udt); +} + +:vcge.^udt^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=3 & Q6=1 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=3 & thv_Q6=1 & thv_c0404=1) ) & udt & esize2021 & Qm & Qn & Qd +{ + Qd = VectorCompareGreaterThanOrEqual(Qn,Qm,esize2021,udt); +} + +:vcge.f^fesize2020 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2121=0 & c0811=14 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=14 & thv_Q6=0 & thv_c0404=0) ) & fesize2020 & Dm & Dn & Dd +{ + Dd = FloatVectorCompareGreaterThanOrEqual(Dn,Dm,2:1,32:1); +} + +:vcge.f^fesize2020 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2121=0 & c0811=14 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=14 & thv_Q6=1 & thv_c0404=0) ) & fesize2020 & Qm & Qn & Qd +{ + Qd = FloatVectorCompareGreaterThanOrEqual(Qn,Qm,2:1,32:1); +} + +:vcge.s^esize1819 Dd,Dm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=1 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=1 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dm & Dd & zero +{ + Dd = VectorCompareGreaterThanOrEqual(Dm,zero,esize1819); +} + +:vcge.s^esize1819 Qd,Qm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=1 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=1 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qm & Qd & zero +{ + Qd = VectorCompareGreaterThanOrEqual(Qm,zero,esize1819); +} + +:vcge.f^fesize1819 Dd,Dm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=9 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=9 & thv_Q6=0 & thv_c0404=0) ) & fesize1819 & Dm & Dd & zero +{ + Dd = FloatVectorCompareGreaterThanOrEqual(Dm,zero,fesize1819); +} + +:vcge.f^fesize1819 Qd,Qm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=9 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=9 & thv_Q6=1 & thv_c0404=0) ) & fesize1819 & Qm & Qd & zero +{ + Qd = FloatVectorCompareGreaterThanOrEqual(Qm,zero,fesize1819); +} + +:vcgt.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=3 & Q6=0 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=3 & thv_Q6=0 & thv_c0404=0) ) & udt & esize2021 & Dm & Dn & Dd +{ + Dd = VectorCompareGreaterThan(Dn,Dm,esize2021); +} + +:vcgt.^udt^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=3 & Q6=1 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=3 & thv_Q6=1 & thv_c0404=0) ) & udt & esize2021 & Qm & Qn & Qd +{ + Qd = VectorCompareGreaterThan(Qn,Qm,esize2021); +} + +:vcgt.f^fesize2020 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2121=1 & c0811=14 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=1 & thv_c0811=14 & thv_Q6=0 & thv_c0404=0) ) & fesize2020 & Dm & Dn & Dd +{ + Dd = FloatVectorCompareGreaterThan(Dn,Dm,fesize2020); +} + +:vcgt.f^fesize2020 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2121=1 & c0811=14 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=1 & thv_c0811=14 & thv_Q6=1 & thv_c0404=0) ) & fesize2020 & Qm & Qn & Qd +{ + Qd = FloatVectorCompareGreaterThan(Qn,Qm,fesize2020); +} + +:vcgt.i^esize1819 Dd,Dm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=0 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=0 & thv_Q6=0 & thv_c0404=0 ) ) & esize1819 & Dd & Dm & zero +{ + Dd = VectorCompareGreaterThan(Dm,zero,esize1819); +} + +:vcgt.i^esize1819 Qd,Qm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=0 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=0 & thv_Q6=1 & thv_c0404=0 ) ) & esize1819 & Qd & Qm & zero +{ + Qd = VectorCompareGreaterThan(Qm,zero,esize1819); +} + +:vcgt.f^fesize1819 Dd,Dm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=8 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=8 & thv_Q6=0 & thv_c0404=0 ) ) & fesize1819 & Dd & Dm & zero +{ + Dd = FloatVectorCompareGreaterThan(Dm,zero,fesize1819); +} + +:vcgt.f^fesize1819 Qd,Qm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=8 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=8 & thv_Q6=1 & thv_c0404=0 ) ) & fesize1819 & Qd & Qm & zero +{ + Qd = FloatVectorCompareGreaterThan(Qm,zero,fesize1819); +} + +:vcle.s^esize1819 Dd,Dm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=3 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=3 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dd & Dm & zero +{ + Dd = VectorCompareGreaterThanOrEqual(zero,Dm,esize1819); +} + +:vcle.s^esize1819 Qd,Qm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=3 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=3 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qd & Qm & zero +{ + Qd = VectorCompareGreaterThanOrEqual(zero,Qm,esize1819); +} + +:vcle.f^fesize1819 Dd,Dm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=0xb & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=0xb & thv_Q6=0 & thv_c0404=0) ) & fesize1819 & Dd & Dm & zero +{ + Dd = FloatVectorCompareGreaterThanOrEqual(zero,Dm,fesize1819); +} + +:vcle.f^fesize1819 Qd,Qm,zero is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=0xb & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=0xb & thv_Q6=1 & thv_c0404=0) ) & fesize1819 & Qd & Qm & zero +{ + Qd = FloatVectorCompareGreaterThanOrEqual(zero,Qm,fesize1819); +} + +:vcls.s^esize1819 Dd,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=0 & c0711=8 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=0 & thv_c0711=8 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dd & Dm +{ + Dd = VectorCountLeadingSignBits(Dm,esize1819); +} + +:vcls.s^esize1819 Qd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=0 & c0711=8 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=0 & thv_c0711=8 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qd & Qm +{ + Qd = VectorCountLeadingSignBits(Qm,esize1819); +} + +:vclt.s^esize1819 Dd,Dm,zero is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=4 & Q6=0 & c0404=0) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=4 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dm & Dd & zero +{ + Dd = VectorCompareGreaterThan(zero,Dm,esize1819); +} + +:vclt.s^esize1819 Qd,Qm,zero is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=4 & Q6=1 & c0404=0) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=4 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qm & Qd & zero +{ + Qd = VectorCompareGreaterThan(zero,Qm,esize1819); +} + +:vclt.f^fesize1819 Dd,Dm,zero is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=12 & Q6=0 & c0404=0) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=12 & thv_Q6=0 & thv_c0404=0) ) & fesize1819 & Dm & Dd & zero +{ + Dd = FloatVectorCompareGreaterThan(zero,Dm,fesize1819); +} + +:vclt.f^fesize1819 Qd,Qm,zero is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & (c1819=1 | c1819=2) & c1617=1 & c0711=12 & Q6=1 & c0404=0) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & (thv_c1819=1 | thv_c1819=2) & thv_c1617=1 & thv_c0711=12 & thv_Q6=1 & thv_c0404=0) ) & fesize1819 & Qm & Qd & zero +{ + Qd = FloatVectorCompareGreaterThan(zero,Qm,fesize1819); +} + +:vclz.i^esize1819 Dd,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=0 & c0711=9 & Q6=0 & c0404=0) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=0 & thv_c0711=9 & thv_Q6=0 & thv_c0404=0) ) & esize1819 & Dd & Dm +{ + Dd = VectorCountLeadingZeros(Dm,esize1819); +} + +:vclz.i^esize1819 Qd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=0 & c0711=9 & Q6=1 & c0404=0) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=0 & thv_c0711=9 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qd & Qm +{ + Qd = VectorCountLeadingZeros(Qm,esize1819); +} + +crot2324: "#"^0 is ($(AMODE) & c2324=0 ) | (TMode=1 & thv_c2324=0) { local tmp:4 = 0; export tmp; } +crot2324: "#"^90 is ($(AMODE) & c2324=1 ) | (TMode=1 & thv_c2324=1) { local tmp:4 = 90; export tmp; } +crot2324: "#"^180 is ($(AMODE) & c2324=2 ) | (TMode=1 & thv_c2324=2) { local tmp:4 = 180; export tmp; } +crot2324: "#"^270 is ($(AMODE) & c2324=3 ) | (TMode=1 & thv_c2324=3) { local tmp:4 = 270; export tmp; } +crot2021: "#"^0 is ($(AMODE) & c2021=0 ) | (TMode=1 & thv_c2021=0) { local tmp:4 = 0; export tmp; } +crot2021: "#"^90 is ($(AMODE) & c2021=1 ) | (TMode=1 & thv_c2021=1) { local tmp:4 = 90; export tmp; } +crot2021: "#"^180 is ($(AMODE) & c2021=2 ) | (TMode=1 & thv_c2021=2) { local tmp:4 = 180; export tmp; } +crot2021: "#"^270 is ($(AMODE) & c2021=3 ) | (TMode=1 & thv_c2021=3) { local tmp:4 = 270; export tmp; } + +:vcmla.f^fesize2020 Dd,Dn,Dm,crot2324 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=6 & c2121=1 & c0811=8 & Q6=0 & c0404=0 ) | + ($(TMODE_F) & thv_c2527=6 & thv_c2121=1 & thv_c0811=8 & thv_Q6=0 & thv_c0404=0)) & crot2324 & fesize2020 & Dm & Dn & Dd +{ + Dd = VectorComplexMultiplyAccumulate(Dd,Dn,Dm,crot2324,fesize2020); +} + +:vcmla.f^fesize2020 Qd,Qn,Qm,crot2324 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=6 & c2121=1 & c0811=8 & Q6=1 & c0404=0 )| + ($(TMODE_F) & thv_c2527=6 & thv_c2021=1 & thv_c0811=8 & thv_Q6=1 & thv_c0404=0)) & crot2324 & fesize2020 & Qm & Qn & Qd +{ + Qd = VectorComplexMultiplyAccumulate(Qd,Qn,Qm,crot2324,fesize2020); +} + +:vcmla.f^fesize2323 Dd,Dn,Dm,crot2021 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=7 & c2424=0 & c0811=8 & Q6=0 & c0404=0 ) | + ($(TMODE_F) & thv_c2527=7 & thv_c2424=0 & thv_c0811=8 & thv_Q6=0 & thv_c0404=0)) & crot2021 & fesize2323 & Dm & Dn & Dd +{ + Dd = VectorComplexMultiplyAccumulateByElement(Dd,Dn,Dm,crot2021,fesize2323); +} + +:vcmla.f^fesize2323 Qd,Qn,Qm,crot2021 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=7 & c2424=0 & c0811=8 & Q6=1 & c0404=0 )| + ($(TMODE_F) & thv_c2527=7 & thv_c2424=0 & thv_c0811=8 & thv_Q6=1 & thv_c0404=0)) & crot2021 & fesize2323 & Qm & Qn & Qd +{ + Qd = VectorComplexMultiplyAccumulateByElement(Qd,Qn,Qm,crot2021,fesize2323); +} + +@endif # SIMD + +# set float register flags correctly for comparison +macro FloatVectorCompare(op1,op2,nanx) { + local tNG = op1 f< op2; + local tZR = op1 f== op2; + local tCY = op2 f<= op1; + tOV:1 = nan(op1) | nan(op2); # this is really a comparison with NAN and may also raise an exception when NAN + + fpscr = (fpscr & 0x0fffffff) | (zext(tNG) << 31) | (zext(tZR) << 30) | (zext(tCY) << 29) | (zext(tOV) << 28); +} + +@if defined(VFPv2) || defined(VFPv3) + +nanx: "e" is c0707=1 { export 1:1; } +nanx: is c0707=0 { export 0:1; } + +:vcmp^nanx^COND^".f16" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=4 & c0811=0b1001 & c0606=1 & c0404=0) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=4 & thv_c0811=0b1001 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & nanx & Sm +{ + build COND; + build Sd; + build Sm; + local sm16:2 = Sm(0); + local sd16:2 = Sd(0); + + FloatVectorCompare(sd16,sm16,nanx); +} + +:vcmp^nanx^COND^".f32" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=4 & c0811=0b1010 & c0606=1 & c0404=0) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=4 & thv_c0811=0b1010 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & nanx & Sm +{ + build COND; + build Sd; + build Sm; + + FloatVectorCompare(Sd,Sm,nanx); +} + +:vcmp^nanx^COND^".f64" Dd,Dm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=4 & c0811=0b1011 & c0606=1 & c0404=0) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=4 & thv_c0811=0b1011 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & nanx & Dm +{ + build COND; + build Dd; + build Dm; + FloatVectorCompare(Dd,Dm,nanx); +} + +:vcmp^nanx^COND^".f16" Sd,zero is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=5 & c0811=0b1001 & c0006=0b1000000 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=5 & thv_c0811=0b1001 & thv_c0006=0b1000000 ) ) & COND & Sd & nanx & zero +{ + build COND; + build Sd; + local Zero:2 = 0; + local sd16:2 = Sd(0); + + FloatVectorCompare(sd16,Zero,nanx); +} + +:vcmp^nanx^COND^".f32" Sd,zero is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=5 & c0811=0b1010 & c0006=0b1000000 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=5 & thv_c0811=0b1010 & thv_c0006=0b1000000 ) ) & COND & Sd & nanx & zero +{ + build COND; + build Sd; + local Zero:4 = 0; + FloatVectorCompare(Sd,Zero,nanx); +} + +:vcmp^nanx^COND^".f64" Dd,zero is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=5 & c0811=0b1011 & c0006=0b1000000 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=5 & thv_c0811=0b1011 & thv_c0006=0b1000000 ) ) & COND & Dd & nanx & zero +{ + build COND; + build Dd; + local Zero:8 = 0; + FloatVectorCompare(Dd,Zero,nanx); +} + +@endif # VFPv2 || VFPv3 + +define pcodeop VectorCountOneBits; + + +@ifndef VERSION_8 +#second arg to conversion function indicates rounding mode (see RMODE bits of FPSCR) +define pcodeop VectorFloatToSigned; +define pcodeop VectorFloatToUnsigned; +define pcodeop VectorSignedToFloat; +define pcodeop VectorUnsignedToFloat; +@endif # VERSION_8 + +@if defined(SIMD) +####### +# VCVT (between floating-point and integer, Advanced SIMD) +# + +:vcnt.8 Dd,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1619=0 & c0711=10 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1619=0 & thv_c0711=10 & thv_c0606=0 & thv_c0404=0) ) & Dd & Dm +{ + Dd = VectorCountOneBits(Dm,8:1,8:1); +} + +:vcnt.8 Qd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819=0 & c1617=0 & c0711=10 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1619=0 & thv_c0711=10 & thv_c0606=1 & thv_c0404=0) ) & Qd & Qm +{ + Qd = VectorCountOneBits(Qm,8:1,8:1); +} + +@ifndef VERSION_8 +:vcvt.s16.f16 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x37 & c0911=3 & c0708=2 & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x37 & thv_c0911=3 & thv_c0708=2 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm + +{ + Dd = VectorFloatToSigned(Dm,3:1); +} + +:vcvt.u16.f16 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x37 & c0911=3 & c0708=3 & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x37 & thv_c0911=3 & thv_c0708=3 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm + +{ + Dd = VectorFloatToUnsigned(Dm,0:1); +} + +:vcvt.f16.s16 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x37 & c0911=3 & c0708=0 & Q6=0 & c0404=0) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x37 & thv_c0911=3 & thv_c0708=0 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm +{ + Dd = VectorSignedToFloat(Dm,0:1); +} + +:vcvt.f16.u16 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x37 & c0911=3 & c0708=1 & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x37 & thv_c0911=3 & thv_c0708=1 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm + +{ + Dd = VectorUnsignedToFloat(Dm,0:1); +} + +:vcvt.s32.f32 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=2 & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=2 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm + +{ + Dd = VectorFloatToSigned(Dm,3:1); +} + +:vcvt.u32.f32 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=3 & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=3 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm + +{ + Dd = VectorFloatToUnsigned(Dm,3:1); +} + +:vcvt.f32.s32 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=0 & Q6=0 & c0404=0) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=0 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm +{ + Dd = VectorSignedToFloat(Dm,0:1); +} + +:vcvt.f32.u32 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=1 & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=1 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm + +{ + Dd = VectorUnsignedToFloat(Dm,0:1); +} + + + + + +:vcvt.s16.f16 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x37 & c0911=3 & c0708=2 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x37 & thv_c0911=3 & thv_c0708=2 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm + +{ + Qd = VectorFloatToSigned(Qm,6:1); +} + +:vcvt.u16.f16 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x37 & c0911=3 & c0708=3 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x37 & thv_c0911=3 & thv_c0708=3 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm + +{ + Qd = VectorFloatToUnsigned(Qm,7:1); +} + +:vcvt.f16.s16 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x37 & c0911=3 & c0708=0 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x37 & thv_c0911=3 & thv_c0708=0 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm + +{ + Qd = VectorSignedToFloat(Qm,4:1); +} + +:vcvt.f16.u16 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x37 & c0911=3 & c0708=1 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x37 & thv_c0911=3 & thv_c0708=1 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm + +{ + Qd = VectorUnsignedToFloat(Qm,5:1); +} + +:vcvt.s32.f32 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=2 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=2 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm + +{ + Qd = VectorFloatToSigned(Qm,10:1); +} + +:vcvt.u32.f32 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=3 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=3 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm + +{ + Qd = VectorFloatToUnsigned(Qm,11:1); +} + +:vcvt.f32.s32 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=0 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=0 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm + +{ + Qd = VectorSignedToFloat(Qm,8:1); +} + +:vcvt.f32.u32 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x3b & c0911=3 & c0708=1 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x3b & thv_c0911=3 & thv_c0708=1 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm + +{ + Qd = VectorUnsignedToFloat(Qm,9:1); +} + +@endif # ! VERSION_8 +@endif # SIMD + +@if defined(VFPv2) || defined(VFPv3) + +@ifndef VERSION_8 +####### +# VCVT (between floating-point and integer, VFP) +# + +roundMode: "r" is TMode=0 & c0707=0 { tmp:1 = $(FPSCR_RMODE); export tmp; } +roundMode: is TMode=0 & c0707=1 { export 3:1; } # Round towards zero +roundMode: "r" is TMode=1 & thv_c0707=0 { tmp:1 = $(FPSCR_RMODE); export tmp; } +roundMode: is TMode=1 & thv_c0707=1 { export 3:1; } # Round towards zero + +:vcvt^roundMode^COND^".s32.f16" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=5 & c0911=4 & c0808=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=5 & thv_c0911=4 & thv_c0808=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sm & roundMode +{ + build COND; + build Sd; + build Sm; + build roundMode; + local Sm16:2 = Sm(0); + Sd = trunc(Sm16);#VectorFloatToSigned(Sm16,roundMode); +} + +:vcvt^roundMode^COND^".s32.f32" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=5 & c0911=5 & c0808=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=5 & thv_c0911=5 & thv_c0808=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sm & roundMode +{ + build COND; + build Sd; + build Sm; + build roundMode; + Sd = trunc(Sm);#VectorFloatToSigned(Sm16,roundMode); +} + +:vcvt^roundMode^COND^".s32.f64" Sd,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=5 & c0911=5 & c0808=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=5 & thv_c0911=5 & thv_c0808=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & roundMode & Dm +{ + build COND; + build Sd; + build Dm; + build roundMode; + Sd = VectorFloatToSigned(Dm,roundMode); +} + +:vcvt^roundMode^COND^".u32.f16" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=4 & c0911=4 & c0808=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=4 & thv_c0911=4 & thv_c0808=1 & thv_c0606=1 & thv_c0404=0) ) & COND & roundMode & Sd & Sm +{ + build COND; + build Sd; + build Sm; + build roundMode; + local Sm16:2 = Sm(0); + Sd = VectorFloatToUnsigned(Sm16,roundMode); +} + +:vcvt^roundMode^COND^".u32.f32" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=4 & c0911=5 & c0808=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=4 & thv_c0911=5 & thv_c0808=0 & thv_c0606=1 & thv_c0404=0) ) & COND & roundMode & Sd & Sm +{ + build COND; + build Sd; + build Sm; + build roundMode; + Sd = VectorFloatToUnsigned(Sm,roundMode); +} + +:vcvt^roundMode^COND^".u32.f64" Sd,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=4 & c0911=5 & c0808=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=4 & thv_c0911=5 & thv_c0808=1 & thv_c0606=1 & thv_c0404=0)) & COND & roundMode & Sd & Dm +{ + build COND; + build Sd; + build Dm; + build roundMode; + Sd = VectorFloatToUnsigned(Dm,roundMode); +} + +:vcvt^COND^".f16.s32" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=0 & c0911=4 & c0808=1 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=0 & thv_c0911=4 & thv_c0808=1 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sm +{ + build COND; + build Sd; + build Sm; + local mode:1 = $(FPSCR_RMODE); + local Sm16:2 = Sm(0); + Sd = VectorSignedToFloat(Sm16,mode); +} + +:vcvt^COND^".f16.u32" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=0 & c0911=4 & c0808=1 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=0 & thv_c0911=4 & thv_c0808=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sm +{ + build COND; + build Sd; + build Sm; + local mode:1 = $(FPSCR_RMODE); + local Sm16:2 = Sm(0); + Sd = VectorUnsignedToFloat(Sm16,mode); +} + +:vcvt^COND^".f64.s32" Dd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=0 & c0911=5 & c0808=1 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=0 & thv_c0911=5 & thv_c0808=1 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Sm +{ + build COND; + build Dd; + build Sm; + mode:1 = $(FPSCR_RMODE); + Dd = VectorSignedToFloat(Sm,mode); +} + +:vcvt^COND^".f32.s32" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=0 & c0911=5 & c0808=0 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=0 & thv_c0911=5 & thv_c0808=0 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sm +{ + build COND; + build Sd; + build Sm; + mode:1 = $(FPSCR_RMODE); + Sd = VectorSignedToFloat(Sm,mode); +} + +:vcvt^COND^".f32.u32" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=0 & c0911=5 & c0808=0 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=0 & thv_c0911=5 & thv_c0808=0 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sm +{ + build COND; + build Sd; + build Sm; + mode:1 = $(FPSCR_RMODE); + Sd = VectorUnsignedToFloat(Sm,mode); +} + +:vcvt^COND^".f64.u32" Dd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1618=0 & c0911=5 & c0808=1 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1618=0 & thv_c0911=5 & thv_c0808=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Sm +{ + build COND; + build Dd; + build Sm; + mode:1 = $(FPSCR_RMODE); + Dd = VectorUnsignedToFloat(Sm,mode); +} + +@endif # ! VERSION_8 +@endif # VFPv2 || VFPv3 + +@if defined(SIMD) +@ifndef VERSION_8 +define pcodeop VectorFloatToSignedFixed; +define pcodeop VectorFloatToUnsignedFixed; +define pcodeop VectorSignedFixedToFloat; +define pcodeop VectorUnsignedFixedToFloat; + +####### +# VCVT (between floating-point and fixed-point, Advanced SIMD) +# + +fbits: "#"val is TMode=0 & c1621 [ val = 64 - c1621; ] { tmp:1 = val; export tmp; } +fbits: "#"val is TMode=1 & thv_c1621 [ val = 64 - thv_c1621; ] { tmp:1 = val; export tmp; } + +:vcvt.s16.f16 Dd,Dm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & c0911=6 & c0808=1 & c0707=0 & Q6=0 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=6 & thv_c0808=1 & thv_c0707=0 & thv_c0606=0 & thv_c0404=1) ) & fbits & Dd & Dm +{ + Dd = VectorFloatToSignedFixed(Dm,fbits); +} + +:vcvt.u16.f16 Dd,Dm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & c0911=6 & c0808=1 & c0707=0 & Q6=0 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=6 & thv_c0808=1 & thv_c0707=0 & thv_c0606=0 & thv_c0404=1) ) & fbits & Dd & Dm + +{ + Dd = VectorFloatToUnsignedFixed(Dm,fbits); +} + +:vcvt.f16.s16 Dd,Dm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & c0911=6 & c0808=0 & c0707=0 & Q6=0 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=6 & thv_c0808=0 & thv_c0707=0 & thv_c0606=0 & thv_c0404=1) ) & fbits & Dd & Dm +{ + Dd = VectorSignedFixedToFloat(Dm,fbits); +} + +:vcvt.f16.u16 Dd,Dm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & c0911=6 & c0808=0 & c0707=0 & Q6=0 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=6 & thv_c0808=0 & thv_c0707=0 & thv_c0606=0 & thv_c0404=1) ) & fbits & Dd & Dm +{ + Dd = VectorUnsignedFixedToFloat(Dm,fbits); +} + +:vcvt.s16.f16 Qd,Qm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & c0911=6 & c0808=1 & c0707=0 & Q6=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=6 & thv_c0808=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & fbits & Qd & Qm +{ + Qd = VectorFloatToSignedFixed(Qm,fbits); +} + +:vcvt.u16.f16 Qd,Qm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & c0911=6 & c0808=1 & c0707=0 & Q6=1 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=6 & thv_c0808=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & fbits & Qd & Qm +{ + Qd = VectorFloatToUnsignedFixed(Qm,fbits); +} + +:vcvt.f16.s16 Qd,Qm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & c0911=0 & c0808=0 & c0707=0 & Q6=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=0 & thv_c0808=0 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & fbits & Qd & Qm +{ + Qd = VectorSignedFixedToFloat(Qm,fbits); +} + +:vcvt.f16.u16 Qd,Qm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & c0911=0 & c0808=0 & c0707=0 & Q6=1 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=0 & thv_c0808=0 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & fbits & Qd & Qm +{ + Qd = VectorUnsignedFixedToFloat(Qm,fbits); +} + +:vcvt.f32.s32 Dd,Dm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & c0911=7 & c0808=0 & c0707=0 & Q6=0 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=7 & thv_c0808=0 & thv_c0707=0 & thv_c0606=0 & thv_c0404=1) ) & fbits & Dd & Dm +{ + Dd = VectorSignedFixedToFloat(Dm,fbits); +} + +:vcvt.f32.u32 Dd,Dm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & c0911=7 & c0808=0 & c0707=0 & Q6=0 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=7 & thv_c0808=0 & thv_c0707=0 & thv_c0606=0 & thv_c0404=1) ) & fbits & Dd & Dm +{ + Dd = VectorUnsignedFixedToFloat(Dm,fbits); +} + +:vcvt.s32.f32 Qd,Qm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & c0911=7 & c0808=1 & c0707=0 & Q6=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=7 & thv_c0808=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & fbits & Qd & Qm +{ + Qd = VectorFloatToSignedFixed(Qm,fbits); +} + +:vcvt.u32.f32 Qd,Qm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & c0911=7 & c0808=1 & c0707=0 & Q6=1 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=7 & thv_c0808=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & fbits & Qd & Qm +{ + Qd = VectorFloatToUnsignedFixed(Qm,fbits); +} + +:vcvt.f32.s32 Qd,Qm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2121=1 & c0911=7 & c0808=0 & c0707=0 & Q6=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=7 & thv_c0808=0 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & fbits & Qd & Qm +{ + Qd = VectorSignedFixedToFloat(Qm,fbits); +} + +:vcvt.f32.u32 Qd,Qm,fbits is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2121=1 & c0911=7 & c0808=0 & c0707=0 & Q6=1 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2121=1 & thv_c0911=7 & thv_c0808=0 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & fbits & Qd & Qm +{ + Qd = VectorUnsignedFixedToFloat(Qm,fbits); +} + +@endif # ! VERSION_8 + +@endif # SIMD + +@if defined(VFPv3) + +@ifndef VERSION_8 + +####### +# VCVT (between floating-point and fixed-point, VFP) +# + +fbits16: "#"^val is TMode=0 & c0505 & c0003 [ val = 16 - ((c0003 << 1) + c0505); ] { tmp:1 = val; export tmp; } +fbits32: "#"^val is TMode=0 & c0505 & c0003 [ val = 32 - ((c0003 << 1) + c0505); ] { tmp:1 = val; export tmp; } +fbits16: "#"^val is TMode=1 & thv_c0505 & thv_c0003 [ val = 16 - ((thv_c0003 << 1) + thv_c0505); ] { tmp:1 = val; export tmp; } +fbits32: "#"^val is TMode=1 & thv_c0505 & thv_c0003 [ val = 32 - ((thv_c0003 << 1) + thv_c0505); ] { tmp:1 = val; export tmp; } + +:vcvt^COND^".s16.f16" Sd,Sd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=0 & c1011=2 & c0809=1 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0)) & COND & Sd & Sd2 & fbits16 +{ + build COND; + build Sd; + build Sd2; + build fbits16; + Sd = VectorFloatToSignedFixed(Sd2,16:1,fbits16); +} + +:vcvt^COND^".u16.f16" Sd,Sd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=1 & c1011=2 & c0809=1 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits16 +{ + build COND; + build Sd; + build Sd2; + build fbits16; + Sd = VectorFloatToUnsignedFixed(Sd2,16:1,fbits16); +} + +:vcvt^COND^".s32.f16" Sd,Sd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=0 & c1011=2 & c0809=1 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=1 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits32 +{ + build COND; + build Sd; + build Sd2; + build fbits32; + Sd = VectorFloatToSignedFixed(Sd2,32:1,fbits32); +} + +:vcvt^COND^".u32.f16" Sd,Sd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=1 & c1011=2 & c0809=1 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=1 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits32 +{ + build COND; + build Sd; + build Sd2; + build fbits32; + Sd = VectorFloatToUnsignedFixed(Sd2,32:1,fbits32); +} + +:vcvt^COND^".s16.f32" Sd,Sd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=0 & c1011=2 & c0809=2 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=2 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0)) & COND & Sd & Sd2 & fbits16 +{ + build COND; + build Sd; + build Sd2; + build fbits16; + Sd = VectorFloatToSignedFixed(Sd2,16:1,fbits16); +} + +:vcvt^COND^".u16.f32" Sd,Sd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=1 & c1011=2 & c0809=2 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=2 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits16 +{ + build COND; + build Sd; + build Sd2; + build fbits16; + Sd = VectorFloatToUnsignedFixed(Sd2,16:1,fbits16); +} + +:vcvt^COND^".s32.f32" Sd,Sd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=0 & c1011=2 & c0809=2 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=2 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits32 +{ + build COND; + build Sd; + build Sd2; + build fbits32; + Sd = VectorFloatToSignedFixed(Sd2,32:1,fbits32); +} + +:vcvt^COND^".u32.f32" Sd,Sd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=1 & c1011=2 & c0809=2 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=2 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits32 +{ + build COND; + build Sd; + build Sd2; + build fbits32; + Sd = VectorFloatToUnsignedFixed(Sd2,32:1,fbits32); +} + +:vcvt^COND^".s16.f64" Dd,Dd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=0 & c1011=2 & c0809=3 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=3 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Dd2 & fbits16 +{ + build COND; + build Dd; + build Dd2; + build fbits16; + Dd = VectorFloatToSignedFixed(Dd2,16:1,fbits16); +} + +:vcvt^COND^".u16.f64" Dd,Dd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=1 & c1011=2 & c0809=3 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=3 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Dd2 & fbits16 +{ + build COND; + build Dd; + build Dd2; + build fbits16; + Dd = VectorFloatToUnsignedFixed(Dd2,16:1,fbits16); +} + +:vcvt^COND^".s32.f64" Dd,Dd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=0 & c1011=2 & c0809=3 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=3 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Dd2 & fbits32 +{ + build COND; + build Dd; + build Dd2; + build fbits32; + Dd = VectorFloatToSignedFixed(Dd2,32:1,fbits32); +} + +:vcvt^COND^".u32.f64" Dd,Dd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=1 & c1717=1 & c1616=1 & c1011=2 & c0809=3 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=1 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=3 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Dd2 & fbits32 +{ + build COND; + build Dd; + build Dd2; + build fbits32; + Dd = VectorFloatToUnsignedFixed(Dd2,32:1,fbits32); +} + +:vcvt^COND^".f16.s16" Sd,Sd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=0 & c1011=2 & c0809=1 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0)) & COND & Sd & Sd2 & fbits16 +{ + build COND; + build Sd; + build Sd2; + build fbits16; + Sd = VectorSignedFixedToFloat(Sd2,16:1,fbits16); +} + +:vcvt^COND^".f16.u16" Sd,Sd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=1 & c1011=2 & c0809=1 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=1 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits16 +{ + build COND; + build Sd; + build Sd2; + build fbits16; + Sd = VectorFloatToUnsignedFixed(Sd2,16:1,fbits16); +} + +:vcvt^COND^".f16.s32" Sd,Sd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=0 & c1011=2 & c0809=1 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=1 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits32 +{ + build COND; + build Sd; + build Sd2; + build fbits32; + Sd = VectorSignedFixedToFloat(Sd2,32:1,fbits32); +} + +:vcvt^COND^".f16.u32" Sd,Sd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=1 & c1011=2 & c0809=1 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=1 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits32 +{ + build COND; + build Sd; + build Sd2; + build fbits32; + Sd = VectorFloatToUnsignedFixed(Sd2,32:1,fbits32); +} + +:vcvt^COND^".f32.s16" Sd,Sd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=0 & c1011=2 & c0809=2 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=2 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0)) & COND & Sd & Sd2 & fbits16 +{ + build COND; + build Sd; + build Sd2; + build fbits16; + Sd = VectorSignedFixedToFloat(Sd2,16:1,fbits16); +} + +:vcvt^COND^".f32.u16" Sd,Sd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=1 & c1011=2 & c0809=2 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=2 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits16 +{ + build COND; + build Sd; + build Sd2; + build fbits16; + Sd = VectorFloatToUnsignedFixed(Sd2,16:1,fbits16); +} + +:vcvt^COND^".f32.s32" Sd,Sd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=0 & c1011=2 & c0809=2 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=2 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits32 +{ + build COND; + build Sd; + build Sd2; + build fbits32; + Sd = VectorSignedFixedToFloat(Sd2,32:1,fbits32); +} + +:vcvt^COND^".f32.u32" Sd,Sd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=1 & c1011=2 & c0809=2 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=2 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Sd & Sd2 & fbits32 +{ + build COND; + build Sd; + build Sd2; + build fbits32; + Sd = VectorFloatToUnsignedFixed(Sd2,32:1,fbits32); +} + +:vcvt^COND^".f64.s16" Dd,Dd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=0 & c1011=2 & c0809=3 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=3 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Dd2 & fbits16 +{ + build COND; + build Dd; + build Dd2; + build fbits16; + Dd = VectorSignedFixedToFloat(Dd2,16:1,fbits16); +} + +:vcvt^COND^".f64.u16" Dd,Dd2,fbits16 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=1 & c1011=2 & c0809=3 & c0707=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=3 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Dd2 & fbits16 +{ + build COND; + build Dd; + build Dd2; + build fbits16; + Dd = VectorFloatToUnsignedFixed(Dd2,16:1,fbits16); +} + +:vcvt^COND^".f64.s32" Dd,Dd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=0 & c1011=2 & c0809=3 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=0 & thv_c1011=2 & thv_c0809=3 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Dd2 & fbits32 +{ + build COND; + build Dd; + build Dd2; + build fbits32; + Dd = VectorSignedFixedToFloat(Dd2,32:1,fbits32); +} + +:vcvt^COND^".f64.u32" Dd,Dd2,fbits32 is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1921=7 & c1818=0 & c1717=1 & c1616=1 & c1011=2 & c0809=3 & c0707=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1921=7 & thv_c1818=0 & thv_c1717=1 & thv_c1616=1 & thv_c1011=2 & thv_c0809=3 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0) ) & COND & Dd & Dd2 & fbits32 +{ + build COND; + build Dd; + build Dd2; + build fbits32; + Dd = VectorFloatToUnsignedFixed(Dd2,32:1,fbits32); +} + +@endif # ! VERSION_8 + +@endif # VFPv3 + +define pcodeop VectorFloatDoubleToSingle; +define pcodeop VectorFloatSingleToDouble; + +@if defined(VFPv2) || defined(VFPv3) + +@ifndef VERSION_8 +####### +# VCVT (between double-precision and single-precision) +# + +:vcvt^COND^".f32.f64" Sd,Dm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x37 & c0911=5 & c0808=1 & c0607=3 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x36 & thv_c0911=5 & thv_c0808=1 & thv_c0607=3 & thv_c0404=0 ) ) & COND & Sd & Dm +{ + build COND; + build Sd; + build Dm; + Sd = float2float(Dm); +} + +:vcvt^COND^".f64.f32" Dd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x37 & c0911=5 & c0808=0 & c0607=3 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x36 & thv_c0911=5 & thv_c0808=0 & thv_c0607=3 & thv_c0404=0 ) ) & COND & Dd & Sm +{ + build COND; + build Dd; + build Sm; + Dd = float2float(Sm); +} + +@endif # ! VERSION_8 +@endif # VFPv2 || VFPv3 + +@if defined(SIMD) + +@ifndef VERSION_8 + +define pcodeop VectorFloatSingleToBFloat16; +define pcodeop FloatSingleToBFloat16; + +####### +# VCVT (between single-precision and BFloat16) +# + +:vcvt.bf16.f32 Dd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x36 & c0911=3 & c0808=0 & c0607=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x36 & thv_c0911=3 & thv_c0808=0 & thv_c0607=1 & thv_c0404=0 ) ) & Dd & Qm + +{ + Dd = VectorFloatSingleToBFloat16(Qm, 4:1, 16:1); +} + +# VCVTB Convert Single-precision to BFloat16 in Bottom +:vcvtb^COND^".bf16.f32" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x33 & c0611=0x25 & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x33 & thv_c0611=0x25 & thv_c0404=0 ) ) & COND & Sd & Sm +{ + build COND; + build Sd; + build Sm; + local w:2 = FloatSingleToBFloat16(Sm); + Sd[0,16] = w; +} + + +# VCVTT Convert Single-precision to BFloat16 in Top +:vcvtt^COND^".bf16.f32" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x33 & c0611=0x27 & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x33 & thv_c0611=0x27 & thv_c0404=0 ) ) & COND & Sd & Sm +{ + build COND; + build Sd; + build Sm; + w:2 = FloatSingleToBFloat16(Sm); + Sd[16,16] = w; +} + +define pcodeop VectorFloatSingleToHalf; +define pcodeop VectorFloatHalfToSingle; + +####### +# VCVT (between half-precision and single-precision) +# +:vcvt.f16.f32 Dd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x36 & c0911=3 & c0808=0 & c0607=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x36 & thv_c0911=3 & thv_c0808=0 & thv_c0607=0 & thv_c0404=0 ) ) & Dd & Qm + +{ + Dd = VectorFloatSingleToHalf(Qm, 4:1, 16:1); +} + +:vcvt.f16.f32 Qd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1621=0x36 & c0911=3 & c0808=1 & c0607=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1621=0x36 & thv_c0911=3 & thv_c0808=1 & thv_c0607=0 & thv_c0404=0 ) ) & Qd & Dm + +{ + Qd = VectorFloatHalfToSingle(Dm, 4:1, 16:1); +} + + +define pcodeop VectorFloatToSignedRound; +define pcodeop VectorFloatToUnsignedRound; + +# VCVTA/M/N/P Vector convert floating-point to integer with Rounding +:vcvt^roundType^".s16.f16" Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1821=0xb & c1011=0 & c0707=0 & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1821=0xb & thv_c1011=0 & thv_c0707=0 & thv_c0606=0 & thv_c0404=0 ) ) & roundType & Dd & Dm +{ + Dd = VectorFloatToSignedRound(Dm, 0:1, roundType); +} + +:vcvt^roundType^".u16.f16" Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1821=0xb & c1011=0 & c0707=1 & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1821=0xb & thv_c1011=0 & thv_c0707=1 & thv_c0606=0 & thv_c0404=0 ) ) & roundType & Dd & Dm +{ + Dd = VectorFloatToUnsignedRound(Dm, 0:1, roundType); +} + +:vcvt^roundType^".s32.f32" Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1821=0xc & c1011=0 & c0707=0 & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1821=0xc & thv_c1011=0 & thv_c0707=0 & thv_c0606=0 & thv_c0404=0 ) ) & roundType & Dd & Dm +{ + Dd = VectorFloatToSignedRound(Dm, 1:1, roundType); +} + +:vcvt^roundType^".u32.f32" Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1821=0xc & c1011=0 & c0707=1 & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1821=0xc & thv_c1011=0 & thv_c0707=1 & thv_c0606=0 & thv_c0404=0 ) ) & roundType & Dd & Dm +{ + Dd = VectorFloatToUnsignedRound(Dm, 1:1, roundType); +} + +:vcvt^roundType^".s16.f16" Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1821=0xb & c1011=0 & c0707=0 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1821=0xb & thv_c1011=0 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0 ) ) & roundType & Qd & Qm +{ + Qd = VectorFloatToSignedRound(Qm, 0:1, roundType); +} + +:vcvt^roundType^".u16.f16" Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1821=0xb & c1011=0 & c0707=1 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1821=0xb & thv_c1011=0 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0 ) ) & roundType & Qd & Qm +{ + Qd = VectorFloatToUnsignedRound(Qm, 0:1, roundType); +} + +:vcvt^roundType^".s32.f32" Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1821=0xc & c1011=0 & c0707=0 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1821=0xc & thv_c1011=0 & thv_c0707=0 & thv_c0606=1 & thv_c0404=0 ) ) & roundType & Qd & Qm +{ + Qd = VectorFloatToSignedRound(Qm, 1:1, roundType); +} + +:vcvt^roundType^".u32.f32" Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c1821=0xc & c1011=0 & c0707=1 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c1821=0xc & thv_c1011=0 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0 ) ) & roundType & Qd & Qm +{ + Qd = VectorFloatToUnsignedRound(Qm, 1:1, roundType); +} +@endif # ! VERSION_8 +@endif # SIMD + +@if defined(VFPv3) + +@ifndef VERSION_8 + +define pcodeop FloatToSignedRound; +define pcodeop FloatToUnsignedRound; + +# VCVTA/M/N/P Float convert floating-point to integer with Rounding + +:vcvt^roundType^".s32.f16" Sd,Sm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=0x1d & c1821=0xf & c0911=4 & c0808=1 & c0607=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1d & thv_c1821=0xf & thv_c0911=4 & thv_c0808=1 & thv_c0607=0 & thv_c0404=0 ) ) & roundType & Sd & Sm +{ + local sm16:2 = Sm(0); + Sd = FloatToSignedRound(sm16, roundType); +} + +:vcvt^roundType^".u32.f16" Sd,Sm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=0x1d & c1821=0xf & c0911=4 & c0808=1 & c0607=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1d & thv_c1821=0xf & thv_c0911=4 & thv_c0808=1 & thv_c0607=1 & thv_c0404=0 ) ) & roundType & Sd & Sm +{ + local sm16:2 = Sm(0); + Sd = FloatToUnsignedRound(sm16, roundType); +} + +:vcvt^roundType^".s32.f32" Sd,Sm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=0x1d & c1821=0xf & c0911=4 & c0808=0 & c0607=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1d & thv_c1821=0xf & thv_c0911=4 & thv_c0808=0 & thv_c0607=0 & thv_c0404=0 ) ) & roundType & Sd & Sm +{ + Sd = FloatToSignedRound(Sm, roundType); +} +:vcvt^roundType^".u32.f32" Sd,Sm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=0x1d & c1821=0xf & c0911=4 & c0808=0 & c0607=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1d & thv_c1821=0xf & thv_c0911=4 & thv_c0808=0 & thv_c0607=1 & thv_c0404=0 ) ) & roundType & Sd & Sm +{ + Sd = FloatToUnsignedRound(Sm, roundType); +} + +:vcvt^roundType^".s32.f64" Sd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=0x1d & c1821=0xf & c0911=5 & c0808=1 & c0607=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1d & thv_c1821=0xf & thv_c0911=5 & thv_c0808=1 & thv_c0607=0 & thv_c0404=0 ) ) & roundType & Sd & Dm +{ + Sd = FloatToSignedRound(Dm, roundType); +} +:vcvt^roundType^".u32.f64" Sd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=0x1d & c1821=0xf & c0911=5 & c0808=1 & c0607=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1d & thv_c1821=0xf & thv_c0911=5 & thv_c0808=1 & thv_c0607=1 & thv_c0404=0 ) ) & roundType & Sd & Dm +{ + Sd = FloatToUnsignedRound(Dm, roundType); +} + +# VCVTB Convert Half-precision in Bottom to Single-precision + +:vcvtb^COND^".f32.f16" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x32 & c0611=0x29 & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x32 & thv_c0611=0x29 & thv_c0404=0 ) ) & COND & Sd & Sm +{ + build COND; + build Sd; + build Sm; + Sd = float2float(Sm:2); +} + +:vcvtb^COND^".f16.f32" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x33 & c0611=0x29 & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x33 & thv_c0611=0x29 & thv_c0404=0 ) ) & COND & Sd & Sm +{ + build COND; + build Sd; + build Sm; + local w:2 = float2float(Sm); + Sd[0,16] = w; +} + +:vcvtb^COND^".f64.f16" Dd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x32 & c0611=0x2d & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x32 & thv_c0611=0x2d & thv_c0404=0 ) ) & COND & Dd & Sm +{ + build COND; + build Dd; + build Sm; + Dd = float2float(Sm:2); +} + +:vcvtb^COND^".f16.f64" Sd,Dm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x33 & c0611=0x2d & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x33 & thv_c0611=0x2d & thv_c0404=0 ) ) & COND & Sd & Dm +{ + build COND; + build Sd; + build Dm; + local w:2 = float2float(Dm); + Sd[0,16] = w; +} + +# VCVTT Convert Half-precision in Top to Single-precision + +:vcvtt^COND^".f32.f16" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x32 & c0611=0x2b & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x32 & thv_c0611=0x2b & thv_c0404=0 ) ) & COND & Sd & Sm +{ + build COND; + build Sd; + build Sm; + w:2 = Sm(2); + Sd = float2float(w); +} + +:vcvtt^COND^".f16.f32" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x33 & c0611=0x2b & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x33 & thv_c0611=0x2b & thv_c0404=0 ) ) & COND & Sd & Sm +{ + build COND; + build Sd; + build Sm; + w:2 = float2float(Sm); + Sd[16,16] = w; +} + +:vcvtt^COND^".f64.f16" Dd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x32 & c0611=0x2f & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x32 & thv_c0611=0x2f & thv_c0404=0 ) ) & COND & Dd & Sm +{ + build COND; + build Dd; + build Sm; + w:2 = Sm(2); + Dd = float2float(w); +} + +:vcvtt^COND^".f16.f64" Sd,Dm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x33 & c0611=0x2f & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x33 & thv_c0611=0x2f & thv_c0404=0 ) ) & COND & Sd & Dm +{ + build COND; + build Sd; + build Dm; + w:2 = float2float(Dm); + Sd[16,16] = w; +} + +@endif # ! VERSION_8 + +@endif # VFPv3 + +@if defined(VFPv2) || defined(VFPv3) + +:vdiv^COND^".f16" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2021=0 & c0811=9 & c0606=0 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=9 & thv_c0606=0 & thv_c0404=0 ) ) & COND & Sn & Sd & Sm +{ + build COND; + build Sd; + build Sm; + build Sn; + local sm16:2 = Sm(0); + local sn16:2 = Sn(0); + Sd = zext(sn16 f/ sm16); +} + +:vdiv^COND^".f32" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2021=0 & c0811=10 & c0606=0 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=10 & thv_c0606=0 & thv_c0404=0 ) ) & COND & Sn & Sd & Sm +{ + build COND; + build Sd; + build Sm; + build Sn; + Sd = Sn f/ Sm; +} + +:vdiv^COND^".f64" Dd,Dn,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2021=0 & c0811=11 & c0606=0 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=11 & thv_c0606=0 & thv_c0404=0 ) ) & COND & Dn & Dd & Dm +{ + build COND; + build Dd; + build Dm; + build Dn; + Dd = Dn f/ Dm; +} + +@endif # VFPv2 || VFPv3 + +define pcodeop VectorHalvingAdd; +define pcodeop VectorHalvingSubtract; +define pcodeop VectorRoundHalvingAdd; +define pcodeop VectorRoundAddAndNarrow; +define pcodeop VectorDotProduct; +define pcodeop vectorFusedMultiplyAccumulate; +define pcodeop BfloatMultiplyAccumulate; +define pcodeop VectorMultiplyAddLongVector; +define pcodeop VectorMultiplyAddLongScalar; + + +@if defined(SIMD) + +# F6.1.79 VDOT (vector) page F6-8052 line 467006 +# xfc000d00/mask=xffb00f10 NOT MATCHED BY ANY CONSTRUCTOR +# b_0031=111111000.00........1101...0.... + +:vdot.bf16 Dd, Dn, Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=0 & c0811=0xd & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x18 & thv_c2021=0 & thv_c0811=0xd & thv_Q6=0 & thv_c0404=0 ) ) & Dm & Dn & Dd +{ + Dd = VectorDotProduct(Dn,Dm); +} + +:vdot.bf16 Qd, Qn, Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=0 & c0811=0xd & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x18 & thv_c2021=0 & thv_c0811=0xd & thv_Q6=1 & thv_c0404=0 ) ) & Qm & Qn & Qd +{ + Qd = VectorDotProduct(Qn,Qm); +} + +Mindex: "["^M5^"]" is TMode=0 & M5 { local idx:1 = M5:1; export idx; } +Mindex: "["^thv_M5^"]" is TMode=1 & thv_M5 { local idx:1 = thv_M5:1; export idx; } + +:vdot.bf16 Dd, Dn, Dm0^Mindex is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=0x1c & c2021=0 & c0811=0xd & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1c & thv_c2021=0 & thv_c0811=0xd & thv_Q6=0 & thv_c0404=0 ) ) & Dm0 & Mindex & Dn & Dd +{ + Dd = VectorDotProduct(Dn,Dm0,Mindex); +} + +:vdot.bf16 Qd, Qn, Qm0^Mindex is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=0x1c & c2021=0 & c0811=0xd & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1c & thv_c2021=0 & thv_c0811=0xd & thv_Q6=1 & thv_c0404=0 ) ) & Qm0 & Mindex & Qn & Qd +{ + Qd = VectorDotProduct(Qn,Qm0,Mindex); +} + +####### +# VDUP (scalar) +# + +vdupIndex: c1719 is TMode=0 & c1616=1 & c1719 { tmp:4 = c1719; export tmp; } +vdupIndex: c1819 is TMode=0 & c1617=2 & c1819 { tmp:4 = c1819; export tmp; } +vdupIndex: c1919 is TMode=0 & c1618=4 & c1919 { tmp:4 = c1919; export tmp; } + +vdupIndex: thv_c1719 is TMode=1 & thv_c1616=1 & thv_c1719 { tmp:4 = thv_c1719; export tmp; } +vdupIndex: thv_c1819 is TMode=1 & thv_c1617=2 & thv_c1819 { tmp:4 = thv_c1819; export tmp; } +vdupIndex: thv_c1919 is TMode=1 & thv_c1618=4 & thv_c1919 { tmp:4 = thv_c1919; export tmp; } + +vdupSize: 8 is TMode=0 & c1616=1 { } +vdupSize: 16 is TMode=0 & c1617=2 { } +vdupSize: 32 is TMode=0 & c1618=4 { } +vdupSize: 8 is TMode=1 & thv_c1616=1 { } +vdupSize: 16 is TMode=1 & thv_c1617=2 { } +vdupSize: 32 is TMode=1 & thv_c1618=4 { } + +vdupDm: Dm^"["^vdupIndex^"]" is Dm & vdupIndex & ((TMode=0 & c1616=1) | (TMode=1 & thv_c1616=1)) +{ + ptr:4 = &Dm + vdupIndex; + val:8 = 0; + replicate1to8(*[register]:1 ptr, val); + export val; +} +vdupDm: Dm^"["^vdupIndex^"]" is Dm & vdupIndex & ((TMode=0 & c1617=2) | (TMode=1 & thv_c1617=2)) +{ + ptr:4 = &Dm + (2 * vdupIndex); + val:8 = 0; + replicate2to8(*[register]:2 ptr, val); + export val; +} +vdupDm: Dm^"["^vdupIndex^"]" is Dm & vdupIndex & ((TMode=0 & c1618=4) | (TMode=1 & thv_c1618=4)) +{ + ptr:4 = &Dm + (4 * vdupIndex); + val:8 = 0; + replicate4to8(*[register]:4 ptr, val); + export val; +} + +vdupDm16: vdupDm is vdupDm +{ + val:16 = zext(vdupDm); + val = val & (val << 64); + export val; +} + +:vdup.^vdupSize Dd,vdupDm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & vdupSize & c0711=0x18 & Q6=0 & c0404=0 ) | + ($(TMODE_F) &thv_c2327=0x1f & thv_c2021=3 & thv_c0711=0x18 & thv_Q6=0 & thv_c0404=0 ) ) & Dd & vdupDm +{ + Dd = vdupDm; +} + +:vdup.^vdupSize Qd,vdupDm16 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & vdupSize & c0711=0x18 & Q6=1 & c0404=0 ) | + ($(TMODE_F) &thv_c2327=0x1f & thv_c2021=3 & thv_c0711=0x18 & thv_Q6=1 & thv_c0404=0) ) & Qd & vdupDm16 +{ + Qd = vdupDm16; +} + +####### +# VDUP (ARM core register) +# + +vdupSize2: 8 is c2222=1 & c0505=0 { } +vdupSize2: 16 is c2222=0 & c0505=1 { } +vdupSize2: 32 is c2222=0 & c0505=0 { } + +vdupRd8: Rd is Rd & c2222=1 & c0505=0 +{ + val:8 = 0; + local tmpRd = Rd; + replicate1to8(tmpRd:1, val); + export val; +} +vdupRd8: Rd is Rd & c2222=0 & c0505=1 +{ + val:8 = 0; + local tmpRd = Rd; + replicate2to8(tmpRd:2, val); + export val; +} +vdupRd8: Rd is Rd & c2222=0 & c0505=0 +{ + val:8 = 0; + local tmpRd = Rd; + replicate4to8(tmpRd:4, val); + export val; +} + +vdupRd16: vdupRd8 is vdupRd8 +{ + val:16 = zext(vdupRd8); + val = val & (val << 64); + export val; +} + +:vdup^COND^"."^vdupSize2 Dn,vdupRd8 is (( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=0 & c0811=11 & c0606=0 & c0004=0x10) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=11 & thv_c0606=0 & thv_c0004=0x10 ) ) & COND & Dn & vdupSize2 & vdupRd8 +{ + build COND; + build vdupRd8; + build Dn; + Dn = vdupRd8; +} + +:vdup^COND^"."^vdupSize2 Qn,vdupRd16 is (( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=2 & c0811=11 & c0606=0 & c0004=0x10) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c0811=11 & thv_c0606=0 & thv_c0004=0x10 ) ) & COND & Qn & vdupSize2 & vdupRd16 +{ + build COND; + build vdupRd16; + build Qn; + Qn = vdupRd16; +} + +:veor Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x6 & c2021=0 & c0811=1 & Q6=0 & c0404=1) | + ($(TMODE_F) &thv_c2327=0x1e & thv_c2021=0 & thv_c0811=1 & thv_Q6=0 & thv_c0404=1)) & Dn & Dd & Dm + +{ + Dd = Dn ^ Dm; +} + +:veor Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x6 & c2021=0 & c0811=1 & Q6=1 & c0404=1) | + ($(TMODE_F) &thv_c2327=0x1e & thv_c2021=0 & thv_c0811=1 & thv_Q6=1 & thv_c0404=1)) & Qd & Qn & Qm +{ + Qd = Qn ^ Qm; +} + +extImm: "#"^c0811 is TMode=0 & c0811 { tmp:1 = c0811; export tmp; } +extImm: "#"^thv_c0811 is TMode=1 & thv_c0811 { tmp:1 = thv_c0811; export tmp; } + +:vext.8 Dd,Dn,Dm,extImm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=5 & c2021=3 & c0606=0 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c2021=3 & thv_c0606=0 & thv_c0404=0) ) & Dd & Dn & Dm & extImm +{ + val:16 = (zext(Dm) << 64) | zext(Dn); + local shift = extImm * 8; + val = val >> shift; + Dd = val:8; +} + +:vext.8 Qd,Qn,Qm,extImm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=5 & c2021=3 & c0606=1 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c2021=3 & thv_c0606=1 & thv_c0404=0) ) & Qd & Qn & Qm & extImm +{ + val:32 = (zext(Qm) << 128) | zext(Qn); + local shift = extImm * 8; + val = val >> shift; + Qd = val:16; +} + +:vfma.f^fesize2020 Dd,Dn,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2121=0 & c0811=0xc & c0606=0 & c0404=1 ) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2121=0 & thv_c0811=0xc & thv_c0606=0 & thv_c0404=1) ) & fesize2020 & Dd & Dn & Dm +{ + Dd = vectorFusedMultiplyAccumulate(Dn, Dm, fesize2020); +} + +:vfma.f^fesize2020 Qd,Qn,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2121=0 & c0811=0xc & c0606=1 & c0404=1 ) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2121=0 & thv_c0811=0xc & thv_c0606=1 & thv_c0404=1) ) & fesize2020 & Qd & Qn & Qm +{ + Qd = vectorFusedMultiplyAccumulate(Qn, Qm, fesize2020); +} + + +# Floating-point Multiply-Accumulate BFloat (vector) +:vfmab.BF16 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=0x3 & c0811=8 & c0606=0 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=0x3 & thv_c0811=8 & thv_c0606=0 & thv_c0404=1) ) & Qd & Qn & Qm +{ + Qd = BfloatMultiplyAccumulate(Qn, Qm, 0:1); +} + +:vfmat.BF16 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=0x3 & c0811=8 & c0606=1 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=0x3 & thv_c0811=8 & thv_c0606=1 & thv_c0404=1) ) & Qd & Qn & Qm +{ + Qd = BfloatMultiplyAccumulate(Qn, Qm, 1:1); +} + +vmfDm: Dm_3^"["^index^"]" is TMode=0 & Dm_3 & M5 & c0303 [ index = (M5 << 1) + c0303; ] { el:4 = VectorGetElement(Dm_3, index:1, 2:1, 0:1); export el; } +vmfDm: thv_Dm_3^"["^index^"]" is TMode=1 & thv_Dm_3 & thv_M5 & thv_c0303 [ index = (thv_M5 << 1) + thv_c0303; ] { el:4 = VectorGetElement(thv_Dm_3, index:1, 2:1, 0:1); export el; } +vmfSm: Sm_3^"["^c0303^"]" is TMode=0 & c0404=1 & Sm_3 & M5 & c0303 { el:4 = VectorGetElement(Sm_3, M5:1, 4:1, 0:1); export el; } +vmfSm: Sm_3^"["^c0303^"]" is TMode=1 & thv_c0404=1 & Sm_3 & thv_M5 & c0303 { el:4 = VectorGetElement(Sm_3, thv_M5:1, 4:1, 0:1); export el; } + +:vfmab.BF16 Qd,Qn,vmfDm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1c & c2021=0x3 & c0811=8 & c0606=0 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x1c & thv_c2021=0x3 & thv_c0811=8 & thv_c0606=0 & thv_c0404=1) ) & Qd & Qn & vmfDm +{ + Qd = BfloatMultiplyAccumulate(Qn, vmfDm, 0:1); +} + +:vfmat.BF16 Qd,Qn,vmfDm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1c & c2021=0x3 & c0811=8 & c0606=1 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x1c & thv_c2021=0x3 & thv_c0811=8 & thv_c0606=1 & thv_c0404=1) ) & Qd & Qn & vmfDm +{ + Qd = BfloatMultiplyAccumulate(Qn, vmfDm, 1:1); +} + +:vfmal.F16 Dd,Sn,Sm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=0x2 & c0811=0x8 & c0606=0 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=0x2 & thv_c0811=0x8 & thv_c0606=0 & thv_c0404=1) ) & Dd & Sn & Sm +{ + Dd = VectorMultiplyAddLongVector(Sn, Sm, 0:1); +} + +:vfmal.F16 Qd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=0x2 & c0811=0x8 & c0606=1 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=0x2 & thv_c0811=0x8 & thv_c0606=1 & thv_c0404=1) ) & Qd & Dn & Dm +{ + Qd = VectorMultiplyAddLongVector(Dn, Dm, 1:1); +} + +:vfmal.F16 Dd,Sn,vmfSm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1c & c2021=0x2 & c0811=8 & c0606=0 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x1c & thv_c2021=0x2 & thv_c0811=8 & thv_c0606=0 & thv_c0404=1) ) & Dd & Sn & vmfSm +{ + Dd = VectorMultiplyAddLongScalar(Sn, vmfSm, 0:1); +} + +:vfmal.F16 Qd,Dn,vmfDm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1c & c2021=0x2 & c0811=8 & c0606=1 & c0404=1 ) | + ($(TMODE_F) & thv_c2327=0x1c & thv_c2021=0x2 & thv_c0811=8 & thv_c0606=1 & thv_c0404=1) ) & Qd & Dn & vmfDm +{ + Qd = VectorMultiplyAddLongScalar(Dn, vmfDm, 1:1); +} + + + + +:vhadd.^udt^esize2021 Dd,Dn,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=0 & Q6=0 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=0 & thv_Q6=0 & thv_c0404=0) ) & udt & Dm & esize2021 & Dn & Dd +{ + Dd = VectorHalvingAdd(Dn,Dm,esize2021,udt); +} + +:vhadd.^udt^esize2021 Qd,Qn,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=0 & Q6=1 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=0 & thv_Q6=1 & thv_c0404=0) ) & udt & Qm & esize2021 & Qn & Qd +{ + Qd = VectorHalvingAdd(Qn,Qm,esize2021,udt); +} + + +:vraddhn.i^esize2021x2 Dd,Qn,Qm is (($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=4 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=4 & thv_Q6=0 & thv_c0404=0) ) & Qm & esize2021x2 & Qn & Dd +{ + Dd = VectorRoundAddAndNarrow(Qn,Qm,esize2021x2); +} + +:vrhadd.^udt^esize2021 Dd,Dn,Dm is (($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=1 & Q6=0 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=1 & thv_Q6=0 & thv_c0404=0) ) & udt & Dm & esize2021 & Dn & Dd +{ + Dd = VectorRoundHalvingAdd(Dn,Dm,esize2021,udt); +} + +:vrhadd.^udt^esize2021 Qd,Qn,Qm is (($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=1 & Q6=1 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=1 & thv_Q6=1 & thv_c0404=0) ) & udt & Qm & esize2021 & Qn & Qd +{ + Qd = VectorRoundHalvingAdd(Qn,Qm,esize2021,udt); +} + +:vhsub.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=2 & Q6=0 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=2 & thv_Q6=0 & thv_c0404=0) ) & udt & esize2021 & Dn & Dd & Dm +{ + Dd = VectorHalvingSubtract(Dn,Dm,esize2021,udt); +} + +:vhsub.^udt^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=2 & Q6=1 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=2 & thv_Q6=1 & thv_c0404=0) ) & udt & Qm & esize2021 & Qn & Qd +{ + Qd = VectorHalvingSubtract(Qn,Qm,esize2021,udt); +} + +####### +# VFMA VFMS VFNMA and VFNMS +# + +@if defined(VFPv4) + +:vfma^COND^".f16" Sd,Sn,Sm is ( ( $(AMODE) & ARMcond=1 & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=1 & c0606=0 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=1 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd +{ + Sd = zext(Sd:2 f+ (Sn:2 f* Sm:2)); +} + +:vfma^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & ARMcond=1 & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=2 & c0606=0 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=2 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd +{ + Sd = Sd f+ (Sn f* Sm); +} + +:vfma^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & ARMcond=1 & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=3 & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=3 & thv_c0606=0 & thv_c0404=0)) & Dm & Dn & Dd +{ + Dd = Dd f+ (Dn f* Dm); +} + +:vfms^COND^".f16" Sd,Sn,Sm is ( ( $(AMODE) & ARMcond=1 & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=1 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd +{ + Sd = zext(Sd:2 f+ ((f- Sn:2) f* Sm:2)); +} + +:vfms^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & ARMcond=1 & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=2 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=2 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd +{ + Sd = Sd f+ ((f- Sn) f* Sm); +} + +:vfms^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & ARMcond=1 & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=3 & c0606=1 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=3 & thv_c0606=1 & thv_c0404=0)) & Dm & Dn & Dd +{ + Dd = Dd f+ ((f- Dn) f* Dm); +} + +:vfnma^COND^".f16" Sd,Sn,Sm is ( ( $(AMODE) & ARMcond=1 & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=1 & c0606=1 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=1 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd +{ + Sd = zext((f- Sd:2) f+ ((f- Sn:2) f* Sm:2)); +} + +:vfnma^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & ARMcond=1 & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=2 & c0606=1 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=2 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd +{ + Sd = (f- Sd) f+ ((f- Sn) f* Sm); +} + +:vfnma^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & ARMcond=1 & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=3 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=3 & thv_c0606=1 & thv_c0404=0)) & Dm & Dn & Dd +{ + Dd = (f- Dd) f+ ((f- Dn) f* Dm); +} + +:vfnms^COND^".f16" Sd,Sn,Sm is ( ( $(AMODE) & ARMcond=1 & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=1 & c0606=0 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=1 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd +{ + Sd = zext((f- Sd:2) f+ (Sn:2 f* Sm:2)); +} + +:vfnms^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & ARMcond=1 & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=2 & c0606=0 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=2 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd +{ + Sd = (f- Sd) f+ (Sn f* Sm); +} + +:vfnms^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & ARMcond=1 & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=3 & c0606=0 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=3 & thv_c0606=0 & thv_c0404=0)) & Dm & Dn & Dd +{ + Dd = (f- Dd) f+ (Dn f* Dm); +} + +@endif # VFPv4 + +####### +# VLD1 (multiple single elements) +# + +buildVld1DdList: Dreg is Dreg & counter=1 [ counter=0; regNum=regNum+1; ] +{ + Dreg = * mult_addr; +} +buildVld1DdList: Dreg,buildVld1DdList is Dreg & buildVld1DdList [ counter=counter-1; regNum=regNum+1; ] +{ + Dreg = * mult_addr; + mult_addr = mult_addr + 8; + build buildVld1DdList; +} + +vld1DdList: "{"^buildVld1DdList^"}" is TMode=0 & c0811=7 & D22 & c1215 & buildVld1DdList [ regNum=(D22<<4)+c1215-1; counter=1; ] { export 1:4; } +vld1DdList: "{"^buildVld1DdList^"}" is TMode=0 & c0811=10 & D22 & c1215 & buildVld1DdList [ regNum=(D22<<4)+c1215-1; counter=2; ] { export 2:4; } +vld1DdList: "{"^buildVld1DdList^"}" is TMode=0 & c0811=6 & D22 & c1215 & buildVld1DdList [ regNum=(D22<<4)+c1215-1; counter=3; ] { export 3:4; } +vld1DdList: "{"^buildVld1DdList^"}" is TMode=0 & c0811=2 & D22 & c1215 & buildVld1DdList [ regNum=(D22<<4)+c1215-1; counter=4; ] { export 4:4; } +vld1DdList: "{"^buildVld1DdList^"}" is TMode=1 & thv_c0811=7 & thv_D22 & thv_c1215 & buildVld1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=1; ] { export 1:4; } +vld1DdList: "{"^buildVld1DdList^"}" is TMode=1 & thv_c0811=10 & thv_D22 & thv_c1215 & buildVld1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=2; ] { export 2:4; } +vld1DdList: "{"^buildVld1DdList^"}" is TMode=1 & thv_c0811=6 & thv_D22 & thv_c1215 & buildVld1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=3; ] { export 3:4; } +vld1DdList: "{"^buildVld1DdList^"}" is TMode=1 & thv_c0811=2 & thv_D22 & thv_c1215 & buildVld1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=4; ] { export 4:4; } + +@define Vld1DdList "(c0811=2 | c0811=6 | c0811=7 | c0811=10)" +@define thv_Vld1DdList "(thv_c0811=2 | thv_c0811=6 | thv_c0811=7 | thv_c0811=10)" + +vldAlign45: is TMode=0 & c0405=0 { } +vldAlign45: "@64" is TMode=0 & c0405=1 { } +vldAlign45: "@128" is TMode=0 & c0405=2 { } +vldAlign45: "@256" is TMode=0 & c0405=3 { } +vldAlign45: is TMode=1 & thv_c0405=0 { } +vldAlign45: "@64" is TMode=1 & thv_c0405=1 { } +vldAlign45: "@128" is TMode=1 & thv_c0405=2 { } +vldAlign45: "@256" is TMode=1 & thv_c0405=3 { } + +RnAligned45: "["^VRn^vldAlign45^"]" is TMode=0 & VRn & vldAlign45 { export VRn; } +RnAligned45: "["^VRn^vldAlign45^"]" is TMode=1 & VRn & vldAlign45 { export VRn; } + + +:vld1.^esize0607 vld1DdList,RnAligned45 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & c0003=15 & $(Vld1DdList)) | + ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & thv_c0003=15 & $(thv_Vld1DdList)) ) & esize0607 & RnAligned45 & vld1DdList +{ + mult_addr = RnAligned45; + build vld1DdList; +} + +:vld1.^esize0607 vld1DdList,RnAligned45^"!" is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & c0003=13 & $(Vld1DdList)) | + ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & thv_c0003=13 & $(thv_Vld1DdList)) ) & esize0607 & RnAligned45 & vld1DdList +{ + mult_addr = RnAligned45; + build vld1DdList; + RnAligned45 = RnAligned45 + (8 * vld1DdList); +} + +:vld1.^esize0607 vld1DdList,RnAligned45,VRm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & $(Vld1DdList)) | + ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & $(thv_Vld1DdList)) ) & VRm & esize0607 & RnAligned45 & vld1DdList +{ + mult_addr = RnAligned45; + build vld1DdList; + RnAligned45 = RnAligned45 + VRm; +} + + +####### +# VLD1 (single element to one lane) +# + +vld1Index: val is TMode=0 & c0507 & c1011 [ val = c0507 >> c1011; ] { tmp:4 = val; export tmp; } +vld1Index: val is TMode=1 & thv_c0507 & thv_c1011 [ val = thv_c0507 >> thv_c1011; ] { tmp:4 = val; export tmp; } + +vld1DdElement2: Dd^"["^vld1Index^"]" is Dd & vld1Index & ((TMode=0 & c1011=0) | (TMode=1 & thv_c1011=0)) +{ + ptr:4 = &Dd + vld1Index; + *[register]:1 ptr = *:1 mult_addr; +} +vld1DdElement2: Dd^"["^vld1Index^"]" is Dd & vld1Index & ((TMode=0 & c1011=1) | (TMode=1 & thv_c1011=1)) +{ + ptr:4 = &Dd + (2 * vld1Index); + *[register]:2 ptr = *:2 mult_addr; +} +vld1DdElement2: Dd^"["^vld1Index^"]" is Dd & vld1Index & ((TMode=0 & c1011=2) | (TMode=1 & thv_c1011=2)) +{ + ptr:4 = &Dd + (4 * vld1Index); + *[register]:4 ptr = *:4 mult_addr; +} + +@define Vld1DdElement2 "((c1011=0 & c0404=0) | (c1011=1 & c0505=0) | (c1011=2 & (c0406=0 | c0406=3)))" +@define T_Vld1DdElement2 "((thv_c1011=0 & thv_c0404=0) | (thv_c1011=1 & thv_c0505=0) | (thv_c1011=2 & (thv_c0406=0 | thv_c0406=3)))" + + +vld1Align2: is TMode=0 & c0404=0 { } +vld1Align2: "@16" is TMode=0 & c1011=1 & c0404=1 { } +vld1Align2: "@32" is TMode=0 & c1011=2 & c0404=1 { } +vld1Align2: is TMode=1 & thv_c0404=0 { } +vld1Align2: "@16" is TMode=1 & thv_c1011=1 & thv_c0404=1 { } +vld1Align2: "@32" is TMode=1 & thv_c1011=2 & thv_c0404=1 { } + +RnAligned2: "["^VRn^vld1Align2^"]" is VRn & vld1Align2 { export VRn; } + +:vld1.^esize1011 vld1DdElement2,RnAligned2 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0809=0 & c0003=15 & $(Vld1DdElement2) ) | + ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0809=0 & thv_c0003=15 & $(T_Vld1DdElement2) ) ) & RnAligned2 & esize1011 & vld1DdElement2 +{ + mult_addr = RnAligned2; + build vld1DdElement2; +} + +:vld1.^esize1011 vld1DdElement2,RnAligned2^"!" is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0809=0 & c0003=13 & $(Vld1DdElement2) ) | + ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0809=0 & thv_c0003=13 & $(T_Vld1DdElement2) ) ) & RnAligned2 & esize1011 & vld1DdElement2 +{ + mult_addr = RnAligned2; + build vld1DdElement2; + RnAligned2 = RnAligned2 + esize1011; +} + +:vld1.^esize1011 vld1DdElement2,RnAligned2,VRm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0809=0 & $(Vld1DdElement2) ) | + ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0809=0 & $(T_Vld1DdElement2) ) ) & VRm & RnAligned2 & esize1011 & vld1DdElement2 +{ + mult_addr = RnAligned2; + build vld1DdElement2; + RnAligned2 = RnAligned2 + VRm; +} + + +####### +# VLD1 (single element to all lanes) +# + +vld1RnReplicate: is Rn & c0607=0 +{ + val:8 = 0; + replicate1to8(*:1 Rn, val); + export val; +} +vld1RnReplicate: is Rn & c0607=1 +{ + val:8 = 0; + replicate2to8(*:2 Rn, val); + export val; +} +vld1RnReplicate: is Rn & c0607=2 +{ + val:8 = 0; + replicate4to8(*:4 Rn, val); + export val; +} + +vld1Dd3: Dreg^"[]" is Dreg { export Dreg; } + +buildVld1DdList3: is counter=0 { } +buildVld1DdList3: vld1Dd3 is counter=1 & vld1Dd3 [ counter=0; regNum=regNum+1; ] +{ + vld1Dd3 = mult_dat8; +} +buildVld1DdList3: vld1Dd3,buildVld1DdList3 is vld1Dd3 & buildVld1DdList3 [ counter=counter-1; regNum=regNum+1; ] +{ + vld1Dd3 = mult_dat8; + build buildVld1DdList3; +} + +vld1DdList3: "{"^buildVld1DdList3^"}" is c0505=0 & D22 & c1215 & buildVld1DdList3 [ regNum=(D22<<4)+c1215-1; counter=1; ] { export 1:4; } +vld1DdList3: "{"^buildVld1DdList3^"}" is c0505=1 & D22 & c1215 & buildVld1DdList3 [ regNum=(D22<<4)+c1215-1; counter=2; ] { export 2:4; } + +vld1Align3: is c0404=0 { } +vld1Align3: "@16" is c0404=1 & c0607=1 { } +vld1Align3: "@32" is c0404=1 & c0607=2 { } + +RnAligned3: "["^Rn^vld1Align3^"]" is Rn & vld1Align3 { export Rn; } + +@define vld1Constrain "((c0607=0 & c0404=0) | c0607=1 | c0607=2)" + +:vld1.^esize0607 vld1DdList3,RnAligned3 is $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & RnAligned3 & vld1RnReplicate & vld1DdList3 & c0811=12 & esize0607 & c0003=15 & $(vld1Constrain) +{ + mult_dat8 = vld1RnReplicate; + build vld1DdList3; +} + +:vld1.^esize0607 vld1DdList3,RnAligned3^"!" is $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & RnAligned3 & vld1RnReplicate & vld1DdList3 & c0811=12 & esize0607 & c0003=13 & $(vld1Constrain) +{ + mult_dat8 = vld1RnReplicate; + build vld1DdList3; + RnAligned3 = RnAligned3 + vld1DdList3; +} + +:vld1.^esize0607 vld1DdList3,RnAligned3,VRm is $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & RnAligned3 & vld1RnReplicate & vld1DdList3 & c0811=12 & esize0607 & VRm & $(vld1Constrain) +{ + mult_dat8 = vld1RnReplicate; + build vld1DdList3; + RnAligned3 = RnAligned3 + VRm; +} + +thv_vld1RnReplicate: is VRn & thv_c0607=0 +{ + val:8 = 0; + replicate1to8(*:1 VRn, val); + export val; +} +thv_vld1RnReplicate: is VRn & thv_c0607=1 +{ + val:8 = 0; + replicate2to8(*:2 VRn, val); + export val; +} +thv_vld1RnReplicate: is VRn & thv_c0607=2 +{ + val:8 = 0; + replicate4to8(*:4 VRn, val); + export val; +} + +thv_vld1DdList3: "{"^buildVld1DdList3^"}" is thv_c0505=0 & thv_D22 & thv_c1215 & buildVld1DdList3 [ regNum=(thv_D22<<4)+thv_c1215-1; counter=1; ] { export 1:4; } +thv_vld1DdList3: "{"^buildVld1DdList3^"}" is thv_c0505=1 & thv_D22 & thv_c1215 & buildVld1DdList3 [ regNum=(thv_D22<<4)+thv_c1215-1; counter=2; ] { export 2:4; } + +thv_vld1Align3: is thv_c0404=0 { } +thv_vld1Align3: "@16" is thv_c0404=1 & thv_c0607=1 { } +thv_vld1Align3: "@32" is thv_c0404=1 & thv_c0607=2 { } + +VRnAligned3: "["^VRn^thv_vld1Align3^"]" is VRn & thv_vld1Align3 { export VRn; } + +@define T_vld1Constrain "((thv_c0607=0 & thv_c0404=0) | thv_c0607=1 | thv_c0607=2)" + +:vld1.^esize0607 thv_vld1DdList3,VRnAligned3 is $(TMODE_F) &thv_c2327=19 & thv_c2021=2 & VRnAligned3 & thv_vld1RnReplicate & thv_vld1DdList3 & thv_c0811=12 & esize0607 & thv_c0003=15 & $(T_vld1Constrain) +{ + mult_dat8 = thv_vld1RnReplicate; + build thv_vld1DdList3; +} + +:vld1.^esize0607 thv_vld1DdList3,VRnAligned3^"!" is $(TMODE_F) &thv_c2327=19 & thv_c2021=2 & VRnAligned3 & thv_vld1RnReplicate & thv_vld1DdList3 & thv_c0811=12 & esize0607 & thv_c0003=13 & $(T_vld1Constrain) +{ + mult_dat8 = thv_vld1RnReplicate; + build thv_vld1DdList3; + VRnAligned3 = VRnAligned3 + thv_vld1DdList3; +} + +:vld1.^esize0607 thv_vld1DdList3,VRnAligned3,VRm is $(TMODE_F) &thv_c2327=19 & thv_c2021=2 & VRnAligned3 & thv_vld1RnReplicate & thv_vld1DdList3 & thv_c0811=12 & esize0607 & VRm & $(T_vld1Constrain) +{ + mult_dat8 = thv_vld1RnReplicate; + build thv_vld1DdList3; + VRnAligned3 = VRnAligned3 + VRm; +} + +####### +# VLD2 (multiple 2-element structures) +# + +vld2Dd: Dreg is (($(AMODE) & c0607=0) | ($(TMODE_F) & thv_c0607=0)) & Dreg & regInc +{ + ptr1:4 = &Dreg; +@if ENDIAN == "little" + ptr2:4 = &Dreg + (regInc * 8); +@else # ENDIAN == "big" + ptr2:4 = &Dreg - (regInc * 8); +@endif # ENDIAN = "big" + mult_dat8 = 8; + + *[register]:1 ptr1 = *:1 mult_addr; + mult_addr = mult_addr + 1; + *[register]:1 ptr2 = *:1 mult_addr; + mult_addr = mult_addr + 1; + mult_dat8 = mult_dat8 - 1; + if(mult_dat8 == 0) goto ; + ptr1 = ptr1 + 1; + ptr2 = ptr2 + 1; + goto ; + +} +vld2Dd: Dreg is (($(AMODE) & c0607=1) | ($(TMODE_F) & thv_c0607=1)) & Dreg & regInc +{ + ptr1:4 = &Dreg; +@if ENDIAN == "little" + ptr2:4 = &Dreg + (regInc * 8); +@else # ENDIAN == "big" + ptr2:4 = &Dreg - (regInc * 8); +@endif # ENDIAN = "big" + mult_dat8 = 4; + + *[register]:2 ptr1 = *:2 mult_addr; + mult_addr = mult_addr + 2; + *[register]:2 ptr2 = *:2 mult_addr; + mult_addr = mult_addr + 2; + mult_dat8 = mult_dat8 - 1; + if(mult_dat8 == 0) goto ; + ptr1 = ptr1 + 2; + ptr2 = ptr2 + 2; + goto ; + +} +vld2Dd: Dreg is (($(AMODE) & c0607=2) | ($(TMODE_F) & thv_c0607=2)) & Dreg & regInc +{ + ptr1:4 = &Dreg; +@if ENDIAN == "little" + ptr2:4 = &Dreg + (regInc * 8); +@else # ENDIAN == "big" + ptr2:4 = &Dreg - (regInc * 8); +@endif # ENDIAN = "big" + mult_dat8 = 2; + + *[register]:4 ptr1 = *:4 mult_addr; + mult_addr = mult_addr + 4; + *[register]:4 ptr2 = *:4 mult_addr; + mult_addr = mult_addr + 4; + mult_dat8 = mult_dat8 - 1; + if(mult_dat8 == 0) goto ; + ptr1 = ptr1 + 4; + ptr2 = ptr2 + 4; + goto ; + +} + +buildVld2DdListA: is counter=0 { } +buildVld2DdListA: vld2Dd,buildVld2DdListA is vld2Dd & buildVld2DdListA & esize0607 [ counter=counter-1; regNum=regNum+1; ] +{ + build vld2Dd; + build buildVld2DdListA; +} + +buildVld2DdListB: is counter2=0 { } +buildVld2DdListB: Dreg2 is Dreg2 & counter2=1 & esize0607 [ counter2=0; reg2Num=reg2Num+1; ] { } +buildVld2DdListB: Dreg2,buildVld2DdListB is Dreg2 & buildVld2DdListB & esize0607 [ counter2=counter2-1; reg2Num=reg2Num+1; ] { } + +vld2DdList: "{"^buildVld2DdListA^buildVld2DdListB^"}" is TMode=0 & c0811=8 & D22 & c1215 & buildVld2DdListA & buildVld2DdListB [ regNum=(D22<<4)+c1215-1; regInc=1; reg2Num=regNum+1; counter=1; counter2=1; ] { build buildVld2DdListA; build buildVld2DdListB; export 2:4; } +vld2DdList: "{"^buildVld2DdListA^buildVld2DdListB^"}" is TMode=0 & c0811=9 & D22 & c1215 & buildVld2DdListA & buildVld2DdListB [ regNum=(D22<<4)+c1215-1; regInc=2; reg2Num=regNum+2; counter=1; counter2=1; ] { build buildVld2DdListA; build buildVld2DdListB; export 2:4; } +vld2DdList: "{"^buildVld2DdListA^buildVld2DdListB^"}" is TMode=0 & c0811=3 & D22 & c1215 & buildVld2DdListA & buildVld2DdListB [ regNum=(D22<<4)+c1215-1; regInc=2; reg2Num=regNum+2; counter=2; counter2=2; ] { build buildVld2DdListA; build buildVld2DdListB; export 4:4; } +vld2DdList: "{"^buildVld2DdListA^buildVld2DdListB^"}" is TMode=1 & thv_c0811=8 & thv_D22 & thv_c1215 & buildVld2DdListA & buildVld2DdListB [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; reg2Num=regNum+1; counter=1; counter2=1; ] { build buildVld2DdListA; build buildVld2DdListB; export 2:4; } +vld2DdList: "{"^buildVld2DdListA^buildVld2DdListB^"}" is TMode=1 & thv_c0811=9 & thv_D22 & thv_c1215 & buildVld2DdListA & buildVld2DdListB [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=2; reg2Num=regNum+2; counter=1; counter2=1; ] { build buildVld2DdListA; build buildVld2DdListB; export 2:4; } +vld2DdList: "{"^buildVld2DdListA^buildVld2DdListB^"}" is TMode=1 & thv_c0811=3 & thv_D22 & thv_c1215 & buildVld2DdListA & buildVld2DdListB [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=2; reg2Num=regNum+2; counter=2; counter2=2; ] { build buildVld2DdListA; build buildVld2DdListB; export 4:4; } + +@define Vld2DdList "(c0811=3 | c0811=8 | c0811=9)" +@define thv_Vld2DdList "(thv_c0811=3 | thv_c0811=8 | thv_c0811=9)" + +:vld2.^esize0607 vld2DdList,RnAligned45 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & c0607<3 & c0003=15 & $(Vld2DdList) ) | + ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & thv_c0607<3 & thv_c0003=15 & $(thv_Vld2DdList) ) ) & RnAligned45 & esize0607 & vld2DdList +{ + mult_addr = RnAligned45; + build vld2DdList; +} + +:vld2.^esize0607 vld2DdList,RnAligned45^"!" is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & c0607<3 & c0003=13 & $(Vld2DdList) ) | + ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & thv_c0607<3 & thv_c0003=13 & $(thv_Vld2DdList) ) ) & RnAligned45 & esize0607 & vld2DdList +{ + mult_addr = RnAligned45; + build vld2DdList; + RnAligned45 = RnAligned45 + (8 * vld2DdList); +} + +:vld2.^esize0607 vld2DdList,RnAligned45,VRm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & c0607<3 & c0003 & $(Vld2DdList) ) | + ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & thv_c0607<3 & thv_c0003 & $(thv_Vld2DdList) ) ) & VRm & RnAligned45 & esize0607 & vld2DdList +{ + mult_addr = RnAligned45; + build vld2DdList; + RnAligned45 = RnAligned45 + VRm; +} + +####### +# VLD2 (single 2-element structure to one lane) +# + +vld2Index: val is TMode=0 & c0507 & c1011 [ val = c0507 >> c1011; ] { tmp:4 = val; export tmp; } +vld2Index: val is TMode=1 & thv_c0507 & thv_c1011 [ val = thv_c0507 >> thv_c1011; ] { tmp:4 = val; export tmp; } + +vld2DdElement2: Dreg^"["^vld2Index^"]" is Dreg & vld2Index +{ +} + +vld2Align2: is TMode=0 & c0404=0 & (c1111=0 | c0505=0) { } +vld2Align2: "@16" is TMode=0 & c1011=0 & c0404=1 { } +vld2Align2: "@32" is TMode=0 & c1011=1 & c0404=1 { } +vld2Align2: "@64" is TMode=0 & c1011=2 & c0405=1 { } +vld2Align2: is TMode=1 & thv_c0404=0 & (thv_c1111=0 | thv_c0505=0) { } +vld2Align2: "@16" is TMode=1 & thv_c1011=0 & thv_c0404=1 { } +vld2Align2: "@32" is TMode=1 & thv_c1011=1 & thv_c0404=1 { } +vld2Align2: "@64" is TMode=1 & thv_c1011=2 & thv_c0405=1 { } + +vld2RnAligned2: "["^VRn^vld2Align2^"]" is VRn & vld2Align2 { export VRn; } + +buildVld2DdList2: is counter=0 { } +buildVld2DdList2: vld2DdElement2 is counter=1 & vld2DdElement2 [ counter=0; regNum=regNum+regInc; ] { } +buildVld2DdList2: vld2DdElement2,buildVld2DdList2 is vld2DdElement2 & buildVld2DdList2 [ counter=counter-1; regNum=regNum+regInc; ] { } + +vld2DdList2: "{"^buildVld2DdList2^"}" is TMode=0 & D22 & c1215 & buildVld2DdList2 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=2; ] { } # Single +vld2DdList2: "{"^buildVld2DdList2^"}" is TMode=0 & ((c1011=1 & c0505=1) | (c1011=2 & c0606=1)) & D22 & c1215 & buildVld2DdList2 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=2; ] { } # Double +vld2DdList2: "{"^buildVld2DdList2^"}" is TMode=1 & thv_D22 & thv_c1215 & buildVld2DdList2 [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=2; ] { } # Single +vld2DdList2: "{"^buildVld2DdList2^"}" is TMode=1 & ((thv_c1011=1 & thv_c0505=1) | (thv_c1011=2 & thv_c0606=1)) & thv_D22 & thv_c1215 & buildVld2DdList2 [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=2; ] { } # Double + + +:vld2.^esize1011 vld2DdList2,vld2RnAligned2 is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c1011<3 & c0809=1 & c0003=15 ) | + ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=1 & thv_c0003=15 ) ) & esize1011 & VRm & vld2RnAligned2 & vld2DdList2 + unimpl + +:vld2.^esize1011 vld2DdList2,vld2RnAligned2^"!" is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c1011<3 & c0809=1 & c0003=13 ) | + ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=1 & thv_c0003=13 ) ) & esize1011 & VRm & vld2RnAligned2 & vld2DdList2 + unimpl + +:vld2.^esize1011 vld2DdList2,vld2RnAligned2,VRm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c1011<3 & c0809=1 & c0003 ) | + ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=1 & thv_c0003 ) ) & esize1011 & VRm & vld2RnAligned2 & vld2DdList2 + unimpl + +####### +# VLD2 (single 2-element structure to all lanes) +# + +vld2Align3: is TMode=0 & c0404=0 { } +vld2Align3: "@16" is TMode=0 & c0404=1 & c0607=0 { } +vld2Align3: "@32" is TMode=0 & c0404=1 & c0607=1 { } +vld2Align3: "@64" is TMode=0 & c0404=1 & c0607=2 { } +vld2Align3: is TMode=1 & thv_c0404=0 { } +vld2Align3: "@16" is TMode=1 & thv_c0404=1 & thv_c0607=0 { } +vld2Align3: "@32" is TMode=1 & thv_c0404=1 & thv_c0607=1 { } +vld2Align3: "@64" is TMode=1 & thv_c0404=1 & thv_c0607=2 { } + +vld2RnAligned3: "["^VRn^vld2Align3^"]" is VRn & vld2Align3 { export VRn; } + +buildVld2DdList3: is counter=0 { } +buildVld2DdList3: Dreg^"[]" is counter=1 & Dreg [ counter=0; regNum=regNum+regInc; ] { } +buildVld2DdList3: Dreg^"[]",buildVld2DdList3 is Dreg & buildVld2DdList3 [ counter=counter-1; regNum=regNum+regInc; ] { } + +vld2DdList3: "{"^buildVld2DdList3^"}" is TMode=0 & c0505=0 & D22 & c1215 & buildVld2DdList3 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=2; ] { } # Single +vld2DdList3: "{"^buildVld2DdList3^"}" is TMode=0 & c0505=1 & D22 & c1215 & buildVld2DdList3 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=2; ] { } # Double +vld2DdList3: "{"^buildVld2DdList3^"}" is TMode=1 & thv_c0505=0 & thv_D22 & thv_c1215 & buildVld2DdList3 [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=2; ] { } # Single +vld2DdList3: "{"^buildVld2DdList3^"}" is TMode=1 & thv_c0505=1 & thv_D22 & thv_c1215 & buildVld2DdList3 [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=2; ] { } # Double + +:vld2.^esize0607 vld2DdList3,vld2RnAligned3 is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=13 & c0607<3 & c0003=15 ) | + ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=13 & thv_c0607<3 & thv_c0003=15 ) ) & esize0607 & VRm & vld2RnAligned3 & vld2DdList3 + unimpl + +:vld2.^esize0607 vld2DdList3,vld2RnAligned3^"!" is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=13 & c0607<3 & c0003=13 ) | + ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=13 & thv_c0607<3 & thv_c0003=13 ) ) & esize0607 & VRm & vld2RnAligned3 & vld2DdList3 + unimpl + +:vld2.^esize0607 vld2DdList3,vld2RnAligned3,VRm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=13 & c0607<3 & c0003) | + ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=13 & thv_c0607<3 & thv_c0003 ) ) & esize0607 & VRm & vld2RnAligned3 & vld2DdList3 + unimpl + +####### +# VLD3 (multiple 3-element structures) +# + +vld3Align: is TMode=0 & c0404=0 { } +vld3Align: "@64" is TMode=0 & c0404=1 { } +vld3Align: is TMode=1 & thv_c0404=0 { } +vld3Align: "@64" is TMode=1 & thv_c0404=1 { } + + +vld3RnAligned: "["^VRn^vld3Align^"]" is VRn & vld3Align { export VRn; } + +buildVld3DdList: is counter=0 { } +buildVld3DdList: Dreg is counter=1 & Dreg [ counter=0; regNum=regNum+regInc; ] { } +buildVld3DdList: Dreg,buildVld3DdList is Dreg & buildVld3DdList [ counter=counter-1; regNum=regNum+regInc; ] { } + +vld3DdList: "{"^buildVld3DdList^"}" is TMode=0 & c0811=4 & D22 & c1215 & buildVld3DdList [ regNum=(D22<<4)+c1215-1; regInc=1; counter=3; ] { } # Single +vld3DdList: "{"^buildVld3DdList^"}" is TMode=0 & c0811=5 & D22 & c1215 & buildVld3DdList [ regNum=(D22<<4)+c1215-2; regInc=2; counter=3; ] { } # Double +vld3DdList: "{"^buildVld3DdList^"}" is TMode=1 & thv_c0811=4 & thv_D22 & thv_c1215 & buildVld3DdList [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=3; ] { } # Single +vld3DdList: "{"^buildVld3DdList^"}" is TMode=1 & thv_c0811=5 & thv_D22 & thv_c1215 & buildVld3DdList [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=3; ] { } # Double + +:vld3.^esize0607 vld3DdList,vld3RnAligned is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & (c0811=4 | c0811=5) & c0607<3 & c0505=0 & c0003=15 ) | + ( $(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & (thv_c0811=4 | thv_c0811=5) & thv_c0607<3 & thv_c0505=0 & thv_c0003=15) ) & vld3RnAligned & esize0607 & vld3DdList unimpl + +:vld3.^esize0607 vld3DdList,vld3RnAligned^"!" is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & (c0811=4 | c0811=5) & c0607<3 & c0505=0 & c0003=13 ) | + ( $(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & (thv_c0811=4 | thv_c0811=5) & thv_c0607<3 & thv_c0505=0 & thv_c0003=13) ) & vld3RnAligned & esize0607 & vld3DdList unimpl + +:vld3.^esize0607 vld3DdList,vld3RnAligned,VRm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & (c0811=4 | c0811=5) & c0607<3 & c0505=0 ) | + ( $(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & (thv_c0811=4 | thv_c0811=5) & thv_c0607<3 & thv_c0505=0 ) ) & VRm & vld3RnAligned & esize0607 & vld3DdList unimpl + +####### +# VLD3 (single 3-element structure to one lane) +# + +vld3Index: val is TMode=0 & c0507 & c1011 [ val = c0507 >> c1011; ] { tmp:4 = val; export tmp; } +vld3Index: val is TMode=1 & thv_c0507 & thv_c1011 [ val = thv_c0507 >> thv_c1011; ] { tmp:4 = val; export tmp; } + +vld3DdElement2: Dreg^"["^vld3Index^"]" is Dreg & vld3Index +{ +} + +vld3Rn: "["^VRn^"]" is VRn { export VRn; } + +buildVld3DdList2: is counter=0 { } +buildVld3DdList2: vld3DdElement2 is counter=1 & vld3DdElement2 [ counter=0; regNum=regNum+regInc; ] { } +buildVld3DdList2: vld3DdElement2,buildVld3DdList2 is vld3DdElement2 & buildVld3DdList2 [ counter=counter-1; regNum=regNum+regInc; ] { } + +vld3DdList2: "{"^buildVld3DdList2^"}" is TMode=0 & D22 & c1215 & buildVld3DdList2 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=3; ] { } # Single +vld3DdList2: "{"^buildVld3DdList2^"}" is TMode=0 & ((c1011=1 & c0405=2) | (c1011=2 & c0406=4)) & D22 & c1215 & buildVld3DdList2 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=3; ] { } # Double +vld3DdList2: "{"^buildVld3DdList2^"}" is TMode=1 & thv_D22 & thv_c1215 & buildVld3DdList2 [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=3; ] { } # Single +vld3DdList2: "{"^buildVld3DdList2^"}" is TMode=1 & ((thv_c1011=1 & thv_c0405=2) | (thv_c1011=2 & thv_c0406=4)) & thv_D22 & thv_c1215 & buildVld3DdList2 [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=3; ] { } # Double + + +:vld3.^esize1011 vld3DdList2,vld3Rn is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c1011<3 & c0809=2 & c0003=15) | + ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=2 & thv_c0003=15) ) & vld3Rn & esize1011 & vld3DdList2 unimpl + +:vld3.^esize1011 vld3DdList2,vld3Rn^"!" is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c1011<3 & c0809=2 & c0003=13) | + ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=2 & thv_c0003=13) ) & vld3Rn & esize1011 & vld3DdList2 unimpl + +:vld3.^esize1011 vld3DdList2,vld3Rn,VRm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c1011<3 & c0809=2) | + ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=2) ) & VRm & vld3Rn & esize1011 & vld3DdList2 unimpl + +####### +# VLD3 (single 3-element structure to all lanes) +# + +buildVld3DdList3: is counter=0 { } +buildVld3DdList3: Dreg^"[]" is counter=1 & Dreg [ counter=0; regNum=regNum+regInc; ] { } +buildVld3DdList3: Dreg^"[]",buildVld3DdList3 is Dreg & buildVld3DdList3 [ counter=counter-1; regNum=regNum+regInc; ] { } + +vld3DdList3: "{"^buildVld3DdList3^"}" is TMode=0 & c0505=0 & D22 & c1215 & buildVld3DdList3 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=3; ] { } # Single +vld3DdList3: "{"^buildVld3DdList3^"}" is TMode=0 & c0505=1 & D22 & c1215 & buildVld3DdList3 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=3; ] { } # Double +vld3DdList3: "{"^buildVld3DdList3^"}" is TMode=1 & thv_c0505=0 & thv_D22 & thv_c1215 & buildVld3DdList3 [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=3; ] { } # Single +vld3DdList3: "{"^buildVld3DdList3^"}" is TMode=1 & thv_c0505=1 & thv_D22 & thv_c1215 & buildVld3DdList3 [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=3; ] { } # Double + +:vld3.^esize0607 vld3DdList3,vld3Rn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=14 & c0607<3 & c0404=0 & c0003=15) | + ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=14 & thv_c0404=0 & thv_c0003=15) ) & vld3Rn & esize0607 & vld3DdList3 unimpl + +:vld3.^esize0607 vld3DdList3,vld3Rn^"!" is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=14 & c0607<3 & c0404=0 & c0003=13) | + ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=14 & thv_c0404=0 & thv_c0003=13) ) & vld3Rn & esize0607 & vld3DdList3 unimpl + +:vld3.^esize0607 vld3DdList3,vld3Rn,VRm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=14 & c0607<3 & c0404=0) | + ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=14 & thv_c0404=0) ) & VRm & vld3Rn & esize0607 & vld3DdList3 unimpl + + +####### +# VLD4 (single 4-element structure to one lane) +# + +vld4Index: val is TMode=0 & c0507 & c1011 [ val = c0507 >> c1011; ] { tmp:4 = val; export tmp; } +vld4Index: val is TMode=1 & thv_c0507 & thv_c1011 [ val = thv_c0507 >> thv_c1011; ] { tmp:4 = val; export tmp; } + +vld4DdElement2: Dreg^"["^vld4Index^"]" is Dreg & vld4Index +{ +} + +vld4Align2: is TMode=0 & c0404=0 & (c1111=0 | c0505=0) { } +vld4Align2: "@32" is TMode=0 & c1011=0 & c0404=1 { } +vld4Align2: "@64" is TMode=0 & ((c1011=1 & c0404=1) | (c1011=2 & c0405=1)) { } +vld4Align2: "@128" is TMode=0 & c1011=2 & c0405=2 { } +vld4Align2: is TMode=1 & thv_c0404=0 & (thv_c1111=0 | thv_c0505=0) { } +vld4Align2: "@32" is TMode=1 & thv_c1011=0 & thv_c0404=1 { } +vld4Align2: "@64" is TMode=1 & ((thv_c1011=1 & thv_c0404=1) | (thv_c1011=2 & thv_c0405=1)) { } +vld4Align2: "@128" is TMode=1 & thv_c1011=2 & thv_c0405=2 { } + +vld4RnAligned2: "["^Rn^vld4Align2^"]" is Rn & vld4Align2 { export Rn; } + +buildVld4DdList2: is counter=0 { } +buildVld4DdList2: vld4DdElement2 is counter=1 & vld4DdElement2 [ counter=0; regNum=regNum+regInc; ] { } +buildVld4DdList2: vld4DdElement2,buildVld4DdList2 is vld4DdElement2 & buildVld4DdList2 [ counter=counter-1; regNum=regNum+regInc; ] { } + +vld4DdList2: "{"^buildVld4DdList2^"}" is TMode=0 & D22 & c1215 & buildVld4DdList2 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=4; ] { } # Single +vld4DdList2: "{"^buildVld4DdList2^"}" is TMode=0 & ((c1011=1 & c0505=1) | (c1011=2 & c0606=1)) & D22 & c1215 & buildVld4DdList2 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=4; ] { } # Double +vld4DdList2: "{"^buildVld4DdList2^"}" is TMode=1 & thv_D22 & thv_c1215 & buildVld4DdList2 [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=4; ] { } # Single +vld4DdList2: "{"^buildVld4DdList2^"}" is TMode=1 & ((thv_c1011=1 & thv_c0505=1) | (thv_c1011=2 & thv_c0606=1)) & thv_D22 & thv_c1215 & buildVld4DdList2 [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=4; ] { } # Double + + +:vld4.^esize1011 vld4DdList2,vld4RnAligned2 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c1011<3 & c0809=3 & c0003=15) | + ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=3 & thv_c0003=15 ) ) & esize1011 & vld4RnAligned2 & vld4DdList2 +unimpl + +:vld4.^esize1011 vld4DdList2,vld4RnAligned2^"!" is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c1011<3 & c0809=3 & c0003=13) | + ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=3 & thv_c0003=13 ) ) & esize1011 & vld4RnAligned2 & vld4DdList2 +unimpl + +:vld4.^esize1011 vld4DdList2,vld4RnAligned2,VRm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c1011<3 & c0809=3 & c0003) | + ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=3 & thv_c0003 ) ) & esize1011 & VRm & vld4RnAligned2 & vld4DdList2 + unimpl + +####### +# VLD4 (single 4-element structure to all lanes) +# + +vld4Align3: is c0404=0 { } +vld4Align3: "@32" is c0404=1 & c0607=0 { } +vld4Align3: "@64" is c0404=1 & (c0607=1 | c0607=2) { } +vld4Align3: "@128" is c0404=1 & c0607=3 { } + +vld4RnAligned3: "["^Rn^vld4Align3^"]" is Rn & vld4Align3 { export Rn; } + +buildVld4DdList3: is counter=0 { } +buildVld4DdList3: Dreg^"[]" is counter=1 & Dreg [ counter=0; regNum=regNum+regInc; ] { } +buildVld4DdList3: Dreg^"[]",buildVld4DdList3 is Dreg & buildVld4DdList3 [ counter=counter-1; regNum=regNum+regInc; ] { } + +vld4DdList3: "{"^buildVld4DdList3^"}" is c0505=0 & D22 & c1215 & buildVld4DdList3 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=4; ] { } # Single +vld4DdList3: "{"^buildVld4DdList3^"}" is c0505=1 & D22 & c1215 & buildVld4DdList3 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=4; ] { } # Double + +:vld4.^esize0607 vld4DdList3,vld4RnAligned3 is $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & vld4RnAligned3 & c0811=15 & esize0607 & c0003=15 & vld4DdList3 unimpl +#thv_2327=0x12 + +:vld4.^esize0607 vld4DdList3,vld4RnAligned3^"!" is $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & vld4RnAligned3 & c0811=15 & esize0607 & c0003=13 & vld4DdList3 unimpl + +:vld4.^esize0607 vld4DdList3,vld4RnAligned3,VRm is $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & vld4RnAligned3 & c0811=15 & esize0607 & VRm & vld4DdList3 unimpl + +####### +# VLD4 (multiple 4-element structures) +# + +vld4Align: is TMode=0 & c0405=0 { } +vld4Align: "@64" is TMode=0 & c0405=1 { } +vld4Align: "@128" is TMode=0 & c0405=2 { } +vld4Align: "@256" is TMode=0 & c0405=3 { } +vld4Align: is TMode=1 & thv_c0405=0 { } +vld4Align: "@64" is TMode=1 & thv_c0405=1 { } +vld4Align: "@128" is TMode=1 & thv_c0405=2 { } +vld4Align: "@256" is TMode=1 & thv_c0405=3 { } + +vld4RnAligned: "["^VRn^vld4Align^"]" is VRn & vld4Align { export VRn; } + +buildVld4DdList: is counter=0 { } +buildVld4DdList: Dreg is counter=1 & Dreg [ counter=0; regNum=regNum+regInc; ] { } +buildVld4DdList: Dreg,buildVld4DdList is Dreg & buildVld4DdList [ counter=counter-1; regNum=regNum+regInc; ] { } + +vld4DdList: "{"^buildVld4DdList^"}" is TMode=0 & c0808=0 & D22 & c1215 & buildVld4DdList [ regNum=(D22<<4)+c1215-1; regInc=1; counter=4; ] { } # Single +vld4DdList: "{"^buildVld4DdList^"}" is TMode=0 & c0808=1 & D22 & c1215 & buildVld4DdList [ regNum=(D22<<4)+c1215-2; regInc=2; counter=4; ] { } # Double +vld4DdList: "{"^buildVld4DdList^"}" is TMode=1 & thv_c0808=0 & thv_D22 & thv_c1215 & buildVld4DdList [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=4; ] { } # Single +vld4DdList: "{"^buildVld4DdList^"}" is TMode=1 & thv_c0808=1 & thv_D22 & thv_c1215 & buildVld4DdList [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=4; ] { } # Double + +:vld4.^esize0607 vld4DdList,vld4RnAligned is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & c0911=0 & c0607<3 & c0003=15 ) | + ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & thv_c0911=0 & thv_c0607<3 & thv_c0003=15 ) ) & esize0607 & VRm & vld4RnAligned & vld4DdList + unimpl + +:vld4.^esize0607 vld4DdList,vld4RnAligned^"!" is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & c0911=0 & c0607<3 & c0003=13 ) | + ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & thv_c0911=0 & thv_c0607<3 & thv_c0003=13 ) ) & esize0607 & VRm & vld4RnAligned & vld4DdList + unimpl + +:vld4.^esize0607 vld4DdList,vld4RnAligned,VRm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & c0911=0 & c0607<3) | + ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & thv_c0911=0 & thv_c0607<3 ) ) & esize0607 & VRm & vld4RnAligned & vld4DdList + unimpl + + +@endif # SIMD + +@if defined(VFPv2) || defined(VFPv3) || defined(SIMD) + +####### +# VLDM (A1) +# + +vldmRn: Rn is TMode=0 & Rn & c2121=0 { export Rn; } +vldmRn: Rn^"!" is TMode=0 & Rn & c2121=1 { export Rn; } +vldmRn: thv_Rn is TMode=1 & thv_Rn & thv_c2121=0 { export thv_Rn; } +vldmRn: thv_Rn^"!" is TMode=1 & thv_Rn & thv_c2121=1 { export thv_Rn; } +vldmOffset: value is $(AMODE) & immed [ value= immed << 2; ] { export *[const]:4 value; } +vldmOffset: value is TMode=1 & thv_immed [ value= thv_immed << 2; ] { export *[const]:4 value; } +vldmUpdate: immed is TMode=0 & vldmRn & c2121=0 & immed { } +vldmUpdate: immed is TMode=0 & vldmRn & c2121=1 & immed { vldmRn = vldmRn + (immed << 2); } +vldmUpdate: thv_immed is TMode=1 & vldmRn & thv_c2121=0 & thv_immed { } +vldmUpdate: thv_immed is TMode=1 & vldmRn & thv_c2121=1 & thv_immed { vldmRn = vldmRn + (thv_immed << 2); } + +buildVldmDdList: is counter=0 { } +buildVldmDdList: Dreg is counter=1 & Dreg [ counter=0; regNum=regNum+1; ] +{ + Dreg = *mult_addr; + mult_addr = mult_addr + 8; +} + +buildVldmDdList: Dreg,buildVldmDdList is Dreg & buildVldmDdList [ counter=counter-1; regNum=regNum+1; ] +{ + Dreg = *mult_addr; + mult_addr = mult_addr + 8; + build buildVldmDdList; +} + +vldmDdList: "{"^buildVldmDdList^"}" is TMode=0 & D22 & c1215 & c0007 & buildVldmDdList [ regNum=(D22<<4)+c1215 - 1; counter=c0007>>1; ] { } +vldmDdList: "{"^buildVldmDdList^"}" is TMode=1 & thv_D22 & thv_c1215 & thv_c0007 & buildVldmDdList [ regNum=(thv_D22<<4)+thv_c1215 - 1; counter=thv_c0007>>1; ] { } + +:vldmia^COND vldmRn,vldmDdList is ( ($(AMODE) & c2327=0x19 & c2121 & c2020=1 & c0811=11 & c0000=0) | + ($(TMODE_E) & thv_c2327=0x19 & thv_c2121 & thv_c2020=1 & thv_c0811=11 & thv_c0000=0) ) & COND & vldmRn & vldmDdList & vldmOffset & vldmUpdate +{ + mult_addr = vldmRn; + build vldmDdList; + build vldmUpdate; +} + +:vldmdb^COND vldmRn,vldmDdList is ( ($(AMODE) & c2327=0x1a & c2121=1 & c2020=1 & c0811=11 & c0000=0) | + ($(TMODE_E) & thv_c2327=0x1a & thv_c2121=1 & thv_c2020=1 & thv_c0811=11 & thv_c0000=0 ) ) & COND & vldmRn & vldmDdList & vldmOffset +{ + local start_addr = vldmRn - vldmOffset; + mult_addr = start_addr; + build vldmDdList; + vldmRn = start_addr; +} + +@endif # VFPv2 | VFPv3 | SIMD + +@if defined(VERSION_8) + +with : TMode=0 { +fldmSet1: Dd_1 is Rn & Dd_1 { Dd_1 = * Rn; } +fldmSet2: Dd_2 is Rn & Dd_2 & fldmSet1 { build fldmSet1; Dd_2 = *:8 (Rn + 8:4); } +fldmSet3: Dd_3 is Rn & Dd_3 & fldmSet2 { build fldmSet2; Dd_3 = *:8 (Rn + 16:4); } +fldmSet4: Dd_4 is Rn & Dd_4 & fldmSet3 { build fldmSet3; Dd_4 = *:8 (Rn + 24:4); } +fldmSet5: Dd_5 is Rn & Dd_5 & fldmSet4 { build fldmSet4; Dd_5 = *:8 (Rn + 32:4); } +fldmSet6: Dd_6 is Rn & Dd_6 & fldmSet5 { build fldmSet5; Dd_6 = *:8 (Rn + 40:4); } +fldmSet7: Dd_7 is Rn & Dd_7 & fldmSet6 { build fldmSet6; Dd_7 = *:8 (Rn + 48:4); } +fldmSet8: Dd_8 is Rn & Dd_8 & fldmSet7 { build fldmSet7; Dd_8 = *:8 (Rn + 56:4); } +fldmSet9: Dd_9 is Rn & Dd_9 & fldmSet8 { build fldmSet8; Dd_9 = *:8 (Rn + 64:4); } +fldmSet10: Dd_10 is Rn & Dd_10 & fldmSet9 { build fldmSet9; Dd_10 = *:8 (Rn + 72:4); } +fldmSet11: Dd_11 is Rn & Dd_11 & fldmSet10 { build fldmSet10; Dd_11 = *:8 (Rn + 80:4); } +fldmSet12: Dd_12 is Rn & Dd_12 & fldmSet11 { build fldmSet11; Dd_12 = *:8 (Rn + 88:4); } +fldmSet13: Dd_13 is Rn & Dd_13 & fldmSet12 { build fldmSet12; Dd_13 = *:8 (Rn + 96:4); } +fldmSet14: Dd_14 is Rn & Dd_14 & fldmSet13 { build fldmSet13; Dd_14 = *:8 (Rn + 104:4); } +fldmSet15: Dd_15 is Rn & Dd_15 & fldmSet14 { build fldmSet14; Dd_15 = *:8 (Rn + 112:4); } +fldmSet16: Dd_16 is Rn & Dd_16 & fldmSet15 { build fldmSet15; Dd_16 = *:8 (Rn + 120:4); } + +fldmSet: "{"^Dd_1^"}" is Dd_1 & c0007=3 & fldmSet1 { build fldmSet1; } +fldmSet: "{"^Dd_1^"-"^fldmSet2^"}" is Dd_1 & c0007=5 & fldmSet2 { build fldmSet2; } +fldmSet: "{"^Dd_1^"-"^fldmSet3^"}" is Dd_1 & c0007=7 & fldmSet3 { build fldmSet3; } +fldmSet: "{"^Dd_1^"-"^fldmSet4^"}" is Dd_1 & c0007=9 & fldmSet4 { build fldmSet4; } +fldmSet: "{"^Dd_1^"-"^fldmSet5^"}" is Dd_1 & c0007=11 & fldmSet5 { build fldmSet5; } +fldmSet: "{"^Dd_1^"-"^fldmSet6^"}" is Dd_1 & c0007=13 & fldmSet6 { build fldmSet6; } +fldmSet: "{"^Dd_1^"-"^fldmSet7^"}" is Dd_1 & c0007=15 & fldmSet7 { build fldmSet7; } +fldmSet: "{"^Dd_1^"-"^fldmSet8^"}" is Dd_1 & c0007=17 & fldmSet8 { build fldmSet8; } +fldmSet: "{"^Dd_1^"-"^fldmSet9^"}" is Dd_1 & c0007=19 & fldmSet9 { build fldmSet9; } +fldmSet: "{"^Dd_1^"-"^fldmSet10^"}" is Dd_1 & c0007=21 & fldmSet10 { build fldmSet10; } +fldmSet: "{"^Dd_1^"-"^fldmSet11^"}" is Dd_1 & c0007=23 & fldmSet11 { build fldmSet11; } +fldmSet: "{"^Dd_1^"-"^fldmSet12^"}" is Dd_1 & c0007=25 & fldmSet12 { build fldmSet12; } +fldmSet: "{"^Dd_1^"-"^fldmSet13^"}" is Dd_1 & c0007=27 & fldmSet13 { build fldmSet13; } +fldmSet: "{"^Dd_1^"-"^fldmSet14^"}" is Dd_1 & c0007=29 & fldmSet14 { build fldmSet14; } +fldmSet: "{"^Dd_1^"-"^fldmSet15^"}" is Dd_1 & c0007=31 & fldmSet15 { build fldmSet15; } +fldmSet: "{"^Dd_1^"-"^fldmSet16^"}" is Dd_1 & c0007=33 & fldmSet16 { build fldmSet16; } + + +fldmWback: Rn^"!" is c2121=1 & c2323=1 & c0007 & Rn { Rn = Rn + (4 * c0007:4); } +fldmWback: Rn^"!" is c2121=1 & c2323=0 & c0007 & Rn { Rn = Rn - (4 * c0007:4); } +fldmWback: Rn is c2121=0 & Rn { } +} + +with : TMode=1 { +fldmSet1: thv_Dd_1 is thv_Rn & thv_Dd_1 { thv_Dd_1 = * thv_Rn; } +fldmSet2: thv_Dd_2 is thv_Rn & thv_Dd_2 & fldmSet1 { build fldmSet1; thv_Dd_2 = *:8 (thv_Rn + 8:4); } +fldmSet3: thv_Dd_3 is thv_Rn & thv_Dd_3 & fldmSet2 { build fldmSet2; thv_Dd_3 = *:8 (thv_Rn + 16:4); } +fldmSet4: thv_Dd_4 is thv_Rn & thv_Dd_4 & fldmSet3 { build fldmSet3; thv_Dd_4 = *:8 (thv_Rn + 24:4); } +fldmSet5: thv_Dd_5 is thv_Rn & thv_Dd_5 & fldmSet4 { build fldmSet4; thv_Dd_5 = *:8 (thv_Rn + 32:4); } +fldmSet6: thv_Dd_6 is thv_Rn & thv_Dd_6 & fldmSet5 { build fldmSet5; thv_Dd_6 = *:8 (thv_Rn + 40:4); } +fldmSet7: thv_Dd_7 is thv_Rn & thv_Dd_7 & fldmSet6 { build fldmSet6; thv_Dd_7 = *:8 (thv_Rn + 48:4); } +fldmSet8: thv_Dd_8 is thv_Rn & thv_Dd_8 & fldmSet7 { build fldmSet7; thv_Dd_8 = *:8 (thv_Rn + 56:4); } +fldmSet9: thv_Dd_9 is thv_Rn & thv_Dd_9 & fldmSet8 { build fldmSet8; thv_Dd_9 = *:8 (thv_Rn + 64:4); } +fldmSet10: thv_Dd_10 is thv_Rn & thv_Dd_10 & fldmSet9 { build fldmSet9; thv_Dd_10 = *:8 (thv_Rn + 72:4); } +fldmSet11: thv_Dd_11 is thv_Rn & thv_Dd_11 & fldmSet10 { build fldmSet10; thv_Dd_11 = *:8 (thv_Rn + 80:4); } +fldmSet12: thv_Dd_12 is thv_Rn & thv_Dd_12 & fldmSet11 { build fldmSet11; thv_Dd_12 = *:8 (thv_Rn + 88:4); } +fldmSet13: thv_Dd_13 is thv_Rn & thv_Dd_13 & fldmSet12 { build fldmSet12; thv_Dd_13 = *:8 (thv_Rn + 96:4); } +fldmSet14: thv_Dd_14 is thv_Rn & thv_Dd_14 & fldmSet13 { build fldmSet13; thv_Dd_14 = *:8 (thv_Rn + 104:4); } +fldmSet15: thv_Dd_15 is thv_Rn & thv_Dd_15 & fldmSet14 { build fldmSet14; thv_Dd_15 = *:8 (thv_Rn + 112:4); } +fldmSet16: thv_Dd_16 is thv_Rn & thv_Dd_16 & fldmSet15 { build fldmSet15; thv_Dd_16 = *:8 (thv_Rn + 120:4); } + +fldmSet: "{"^thv_Dd_1^"}" is thv_Dd_1 & thv_c0007=3 & fldmSet1 { build fldmSet1; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet2^"}" is thv_Dd_1 & thv_c0007=5 & fldmSet2 { build fldmSet2; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet3^"}" is thv_Dd_1 & thv_c0007=7 & fldmSet3 { build fldmSet3; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet4^"}" is thv_Dd_1 & thv_c0007=9 & fldmSet4 { build fldmSet4; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet5^"}" is thv_Dd_1 & thv_c0007=11 & fldmSet5 { build fldmSet5; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet6^"}" is thv_Dd_1 & thv_c0007=13 & fldmSet6 { build fldmSet6; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet7^"}" is thv_Dd_1 & thv_c0007=15 & fldmSet7 { build fldmSet7; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet8^"}" is thv_Dd_1 & thv_c0007=17 & fldmSet8 { build fldmSet8; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet9^"}" is thv_Dd_1 & thv_c0007=19 & fldmSet9 { build fldmSet9; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet10^"}" is thv_Dd_1 & thv_c0007=21 & fldmSet10 { build fldmSet10; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet11^"}" is thv_Dd_1 & thv_c0007=23 & fldmSet11 { build fldmSet11; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet12^"}" is thv_Dd_1 & thv_c0007=25 & fldmSet12 { build fldmSet12; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet13^"}" is thv_Dd_1 & thv_c0007=27 & fldmSet13 { build fldmSet13; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet14^"}" is thv_Dd_1 & thv_c0007=29 & fldmSet14 { build fldmSet14; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet15^"}" is thv_Dd_1 & thv_c0007=31 & fldmSet15 { build fldmSet15; } +fldmSet: "{"^thv_Dd_1^"-"^fldmSet16^"}" is thv_Dd_1 & thv_c0007=33 & fldmSet16 { build fldmSet16; } + + +fldmWback: thv_Rn^"!" is thv_bit21=1 & thv_bit23=1 & thv_c0007 & thv_Rn { thv_Rn = thv_Rn + (4 * thv_c0007:4); } +fldmWback: thv_Rn^"!" is thv_bit21=1 & thv_bit23=0 & thv_c0007 & thv_Rn { thv_Rn = thv_Rn - (4 * thv_c0007:4); } +fldmWback: thv_Rn is thv_bit21=0 & thv_Rn { } +} + +:fldmdbx^COND fldmWback, fldmSet is $(AMODE) & COND & ARMcond=1 & c2327=0x1a & c2021=3 & c0811=0xb & c0000=1 & fldmWback & fldmSet +{ + build fldmWback; + build fldmSet; +} + +:fldmiax^COND fldmWback, fldmSet is $(AMODE) & COND & ARMcond=1 & c2327=0x19 & c2020=1 & c0811=0xb & c0000=1 & fldmWback & fldmSet +{ + build fldmSet; + build fldmWback; +} + +:fldmdbx^ItCond fldmWback, fldmSet is TMode=1 & ItCond & thv_c2331=0x1da & thv_c2021=3 & thv_c0811=0xb & fldmWback & fldmSet +{ + build fldmWback; + build fldmSet; +} + +:fldmiax^ItCond fldmWback, fldmSet is TMode=1 & ItCond & thv_c2331=0x1d9 & thv_bit20=1 & thv_c0811=0xb & fldmWback & fldmSet +{ + build fldmSet; + build fldmWback; +} + +with : TMode=0 { +fstmSet1: Dd_1 is Rn & Dd_1 { * Rn = Dd_1; } +fstmSet2: Dd_2 is Rn & Dd_2 & fstmSet1 { build fstmSet1; *:8 (Rn + 8:4) = Dd_2; } +fstmSet3: Dd_3 is Rn & Dd_3 & fstmSet2 { build fstmSet2; *:8 (Rn + 16:4) = Dd_3; } +fstmSet4: Dd_4 is Rn & Dd_4 & fstmSet3 { build fstmSet3; *:8 (Rn + 24:4) = Dd_4; } +fstmSet5: Dd_5 is Rn & Dd_5 & fstmSet4 { build fstmSet4; *:8 (Rn + 32:4) = Dd_5; } +fstmSet6: Dd_6 is Rn & Dd_6 & fstmSet5 { build fstmSet5; *:8 (Rn + 40:4) = Dd_6; } +fstmSet7: Dd_7 is Rn & Dd_7 & fstmSet6 { build fstmSet6; *:8 (Rn + 48:4) = Dd_7; } +fstmSet8: Dd_8 is Rn & Dd_8 & fstmSet7 { build fstmSet7; *:8 (Rn + 56:4) = Dd_8; } +fstmSet9: Dd_9 is Rn & Dd_9 & fstmSet8 { build fstmSet8; *:8 (Rn + 64:4) = Dd_9; } +fstmSet10: Dd_10 is Rn & Dd_10 & fstmSet9 { build fstmSet9; *:8 (Rn + 72:4) = Dd_10; } +fstmSet11: Dd_11 is Rn & Dd_11 & fstmSet10 { build fstmSet10; *:8 (Rn + 80:4) = Dd_11; } +fstmSet12: Dd_12 is Rn & Dd_12 & fstmSet11 { build fstmSet11; *:8 (Rn + 88:4) = Dd_12; } +fstmSet13: Dd_13 is Rn & Dd_13 & fstmSet12 { build fstmSet12; *:8 (Rn + 96:4) = Dd_13; } +fstmSet14: Dd_14 is Rn & Dd_14 & fstmSet13 { build fstmSet13; *:8 (Rn + 104:4) = Dd_14; } +fstmSet15: Dd_15 is Rn & Dd_15 & fstmSet14 { build fstmSet14; *:8 (Rn + 112:4) = Dd_15; } +fstmSet16: Dd_16 is Rn & Dd_16 & fstmSet15 { build fstmSet15; *:8 (Rn + 120:4) = Dd_16; } + +fstmSet: "{"^Dd_1^"}" is Dd_1 & c0007=3 & fstmSet1 { build fstmSet1; } +fstmSet: "{"^Dd_1^"-"^fstmSet2^"}" is Dd_1 & c0007=5 & fstmSet2 { build fstmSet2; } +fstmSet: "{"^Dd_1^"-"^fstmSet3^"}" is Dd_1 & c0007=7 & fstmSet3 { build fstmSet3; } +fstmSet: "{"^Dd_1^"-"^fstmSet4^"}" is Dd_1 & c0007=9 & fstmSet4 { build fstmSet4; } +fstmSet: "{"^Dd_1^"-"^fstmSet5^"}" is Dd_1 & c0007=11 & fstmSet5 { build fstmSet5; } +fstmSet: "{"^Dd_1^"-"^fstmSet6^"}" is Dd_1 & c0007=13 & fstmSet6 { build fstmSet6; } +fstmSet: "{"^Dd_1^"-"^fstmSet7^"}" is Dd_1 & c0007=15 & fstmSet7 { build fstmSet7; } +fstmSet: "{"^Dd_1^"-"^fstmSet8^"}" is Dd_1 & c0007=17 & fstmSet8 { build fstmSet8; } +fstmSet: "{"^Dd_1^"-"^fstmSet9^"}" is Dd_1 & c0007=19 & fstmSet9 { build fstmSet9; } +fstmSet: "{"^Dd_1^"-"^fstmSet10^"}" is Dd_1 & c0007=21 & fstmSet10 { build fstmSet10; } +fstmSet: "{"^Dd_1^"-"^fstmSet11^"}" is Dd_1 & c0007=23 & fstmSet11 { build fstmSet11; } +fstmSet: "{"^Dd_1^"-"^fstmSet12^"}" is Dd_1 & c0007=25 & fstmSet12 { build fstmSet12; } +fstmSet: "{"^Dd_1^"-"^fstmSet13^"}" is Dd_1 & c0007=27 & fstmSet13 { build fstmSet13; } +fstmSet: "{"^Dd_1^"-"^fstmSet14^"}" is Dd_1 & c0007=29 & fstmSet14 { build fstmSet14; } +fstmSet: "{"^Dd_1^"-"^fstmSet15^"}" is Dd_1 & c0007=31 & fstmSet15 { build fstmSet15; } +fstmSet: "{"^Dd_1^"-"^fstmSet16^"}" is Dd_1 & c0007=33 & fstmSet16 { build fstmSet16; } + + +fstmWback: Rn^"!" is c2121=1 & c2323=1 & c0007 & Rn { Rn = Rn + (4 * c0007:4); } +fstmWback: Rn^"!" is c2121=1 & c2323=0 & c0007 & Rn { Rn = Rn - (4 * c0007:4); } +fstmWback: Rn is c2121=0 & Rn { } +} + +with : TMode=1 { +fstmSet1: thv_Dd_1 is thv_Rn & thv_Dd_1 { * thv_Rn = thv_Dd_1; } +fstmSet2: thv_Dd_2 is thv_Rn & thv_Dd_2 & fstmSet1 { build fstmSet1; *:8 (thv_Rn + 8:4) = thv_Dd_2; } +fstmSet3: thv_Dd_3 is thv_Rn & thv_Dd_3 & fstmSet2 { build fstmSet2; *:8 (thv_Rn + 16:4) = thv_Dd_3; } +fstmSet4: thv_Dd_4 is thv_Rn & thv_Dd_4 & fstmSet3 { build fstmSet3; *:8 (thv_Rn + 24:4) = thv_Dd_4; } +fstmSet5: thv_Dd_5 is thv_Rn & thv_Dd_5 & fstmSet4 { build fstmSet4; *:8 (thv_Rn + 32:4) = thv_Dd_5; } +fstmSet6: thv_Dd_6 is thv_Rn & thv_Dd_6 & fstmSet5 { build fstmSet5; *:8 (thv_Rn + 40:4) = thv_Dd_6; } +fstmSet7: thv_Dd_7 is thv_Rn & thv_Dd_7 & fstmSet6 { build fstmSet6; *:8 (thv_Rn + 48:4) = thv_Dd_7; } +fstmSet8: thv_Dd_8 is thv_Rn & thv_Dd_8 & fstmSet7 { build fstmSet7; *:8 (thv_Rn + 56:4) = thv_Dd_8; } +fstmSet9: thv_Dd_9 is thv_Rn & thv_Dd_9 & fstmSet8 { build fstmSet8; *:8 (thv_Rn + 64:4) = thv_Dd_9; } +fstmSet10: thv_Dd_10 is thv_Rn & thv_Dd_10 & fstmSet9 { build fstmSet9; *:8 (thv_Rn + 72:4) = thv_Dd_10; } +fstmSet11: thv_Dd_11 is thv_Rn & thv_Dd_11 & fstmSet10 { build fstmSet10; *:8 (thv_Rn + 80:4) = thv_Dd_11; } +fstmSet12: thv_Dd_12 is thv_Rn & thv_Dd_12 & fstmSet11 { build fstmSet11; *:8 (thv_Rn + 88:4) = thv_Dd_12; } +fstmSet13: thv_Dd_13 is thv_Rn & thv_Dd_13 & fstmSet12 { build fstmSet12; *:8 (thv_Rn + 96:4) = thv_Dd_13; } +fstmSet14: thv_Dd_14 is thv_Rn & thv_Dd_14 & fstmSet13 { build fstmSet13; *:8 (thv_Rn + 104:4) = thv_Dd_14; } +fstmSet15: thv_Dd_15 is thv_Rn & thv_Dd_15 & fstmSet14 { build fstmSet14; *:8 (thv_Rn + 112:4) = thv_Dd_15; } +fstmSet16: thv_Dd_16 is thv_Rn & thv_Dd_16 & fstmSet15 { build fstmSet15; *:8 (thv_Rn + 120:4) = thv_Dd_16; } + +fstmSet: "{"^thv_Dd_1^"}" is thv_Dd_1 & thv_c0007=3 & fstmSet1 { build fstmSet1; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet2^"}" is thv_Dd_1 & thv_c0007=5 & fstmSet2 { build fstmSet2; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet3^"}" is thv_Dd_1 & thv_c0007=7 & fstmSet3 { build fstmSet3; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet4^"}" is thv_Dd_1 & thv_c0007=9 & fstmSet4 { build fstmSet4; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet5^"}" is thv_Dd_1 & thv_c0007=11 & fstmSet5 { build fstmSet5; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet6^"}" is thv_Dd_1 & thv_c0007=13 & fstmSet6 { build fstmSet6; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet7^"}" is thv_Dd_1 & thv_c0007=15 & fstmSet7 { build fstmSet7; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet8^"}" is thv_Dd_1 & thv_c0007=17 & fstmSet8 { build fstmSet8; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet9^"}" is thv_Dd_1 & thv_c0007=19 & fstmSet9 { build fstmSet9; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet10^"}" is thv_Dd_1 & thv_c0007=21 & fstmSet10 { build fstmSet10; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet11^"}" is thv_Dd_1 & thv_c0007=23 & fstmSet11 { build fstmSet11; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet12^"}" is thv_Dd_1 & thv_c0007=25 & fstmSet12 { build fstmSet12; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet13^"}" is thv_Dd_1 & thv_c0007=27 & fstmSet13 { build fstmSet13; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet14^"}" is thv_Dd_1 & thv_c0007=29 & fstmSet14 { build fstmSet14; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet15^"}" is thv_Dd_1 & thv_c0007=31 & fstmSet15 { build fstmSet15; } +fstmSet: "{"^thv_Dd_1^"-"^fstmSet16^"}" is thv_Dd_1 & thv_c0007=33 & fstmSet16 { build fstmSet16; } + + +fstmWback: thv_Rn^"!" is thv_bit21=1 & thv_bit23=1 & thv_c0007 & thv_Rn { thv_Rn = thv_Rn + (4 * thv_c0007:4); } +fstmWback: thv_Rn^"!" is thv_bit21=1 & thv_bit23=0 & thv_c0007 & thv_Rn { thv_Rn = thv_Rn - (4 * thv_c0007:4); } +fstmWback: thv_Rn is thv_bit21=0 & thv_Rn { } +} + +:fstmdbx^COND fstmSet, fstmWback is $(AMODE) & COND & ARMcond=1 & c2327=0x1a & c2021=2 & c0811=0xb & c0000=1 & fstmWback & fstmSet +{ + build fstmWback; + build fstmSet; +} + +:fstmiax^COND fstmSet, fstmWback is $(AMODE) & COND & ARMcond=1 & c2327=0x19 & c2020=0 & c0811=0xb & c0000=1 & fstmWback & fstmSet +{ + build fstmSet; + build fstmWback; +} + +:fstmdbx^ItCond fstmSet, fstmWback is TMode=1 & ItCond & thv_c2331=0x1da & thv_c2021=2 & thv_c0811=0xb & fstmWback & fstmSet +{ + build fstmWback; + build fstmSet; +} + +:fstmiax^ItCond fstmSet, fstmWback is TMode=1 & ItCond & thv_c2331=0x1d9 & thv_bit20=0 & thv_c0811=0xb & fstmWback & fstmSet +{ + build fstmSet; + build fstmWback; +} + +@endif + +@if defined(VFPv2) || defined(VFPv3) + +####### +# VLDM (A2) +# + +buildVldmSdList: is counter=0 { } +buildVldmSdList: Sreg is counter=1 & Sreg [ counter=0; regNum=regNum+1; ] +{ + Sreg = *mult_addr; + mult_addr = mult_addr + 4; +} +buildVldmSdList: Sreg,buildVldmSdList is Sreg & buildVldmSdList [ counter=counter-1; regNum=regNum+1; ] +{ + Sreg = *mult_addr; + mult_addr = mult_addr + 4; + build buildVldmSdList; +} + +vldmSdList: "{"^buildVldmSdList^"}" is TMode=0 & D22 & c1215 & c0007 & buildVldmSdList [ regNum=(c1215<<1) + D22 - 1; counter=c0007; ] { } +vldmSdList: "{"^buildVldmSdList^"}" is TMode=1 & thv_D22 & thv_c1215 & thv_c0007 & buildVldmSdList [ regNum=(thv_c1215<<1) + thv_D22 - 1; counter=thv_c0007; ] { } + +:vldmia^COND vldmRn,vldmSdList is ( ($(AMODE) & ARMcond=1 & c2327=0x19 & c2020=1 & c0811=10 ) | + ($(TMODE_E) & thv_c2327=0x19 & thv_c2020=1 & thv_c0811=10 ) ) & COND & vldmRn & vldmSdList & vldmOffset & vldmUpdate +{ + mult_addr = vldmRn; + build vldmSdList; + build vldmUpdate; +} + +:vldmdb^COND vldmRn,vldmSdList is ( ($(AMODE) & ARMcond=1 & c2327=0x1a & c2121=1 & c2020=1 & c0811=10 ) | + ($(TMODE_E) & thv_c2327=0x1a & thv_c2121=1 & thv_c2020=1 & thv_c0811=10 ) ) & COND & vldmRn & vldmSdList & vldmOffset +{ + local start_addr = vldmRn - vldmOffset; + mult_addr = start_addr; + build vldmSdList; + vldmRn = start_addr; +} + +####### +# VLDR +# + +vldrRn: "["^Rn^"]" is TMode=0 & Rn & immed=0 & c2323=0 { ptr:4 = Rn; export ptr; } +vldrRn: "["^Rn^"]" is TMode=0 & Rn & immed=0 & c2323=1 { ptr:4 = Rn; export ptr; } +vldrRn: "["^Rn^",#-"^vldrImm^"]" is TMode=0 & Rn & immed & c2323=0 [ vldrImm = immed * 4; ] { ptr:4 = Rn - vldrImm; export ptr; } +vldrRn: "["^Rn^",#"^vldrImm^"]" is TMode=0 & Rn & immed & c2323=1 [ vldrImm = immed * 4; ] { ptr:4 = Rn + vldrImm; export ptr; } +vldrRn: "["^pc^"]" is TMode=0 & Rn=15 & pc & immed=0 & c2323=0 { ptr:4 = ((inst_start + 8) & 0xfffffffc); export ptr; } +vldrRn: "["^pc^"]" is TMode=0 & Rn=15 & pc & immed=0 & c2323=1 { ptr:4 = ((inst_start + 8) & 0xfffffffc); export ptr; } +vldrRn: "["^pc^",#-"^vldrImm^"]" is TMode=0 & Rn=15 & pc & immed & c2323=0 [ vldrImm = immed * 4; ] { ptr:4 = ((inst_start + 8) & 0xfffffffc) - vldrImm; export ptr; } +vldrRn: "["^pc^",#"^vldrImm^"]" is TMode=0 & Rn=15 & pc & immed & c2323=1 [ vldrImm = immed * 4; ] { ptr:4 = ((inst_start + 8) & 0xfffffffc) + vldrImm; export ptr; } +vldrRn: "["^VRn^"]" is TMode=1 & VRn & thv_immed=0 & thv_c2323=0 { ptr:4 = VRn; export ptr; } +vldrRn: "["^VRn^"]" is TMode=1 & VRn & thv_immed=0 & thv_c2323=1 { ptr:4 = VRn; export ptr; } +vldrRn: "["^VRn^",#-"^vldrImm^"]" is TMode=1 & VRn & thv_immed & thv_c2323=0 [ vldrImm = thv_immed * 4; ] { ptr:4 = VRn - vldrImm; export ptr; } +vldrRn: "["^VRn^",#"^vldrImm^"]" is TMode=1 & VRn & thv_immed & thv_c2323=1 [ vldrImm = thv_immed * 4; ] { ptr:4 = VRn + vldrImm; export ptr; } +vldrRn: "["^pc^"]" is TMode=1 & thv_Rn=15 & pc & thv_immed=0 & thv_c2323=0 { ptr:4 = ((inst_start + 4) & 0xfffffffc); export ptr; } +vldrRn: "["^pc^"]" is TMode=1 & thv_Rn=15 & pc & thv_immed=0 & thv_c2323=1 { ptr:4 = ((inst_start + 4) & 0xfffffffc); export ptr; } +vldrRn: "["^pc^",#-"^vldrImm^"]" is TMode=1 & thv_Rn=15 & pc & thv_immed & thv_c2323=0 [ vldrImm = thv_immed * 4; ] { ptr:4 = ((inst_start + 4) & 0xfffffffc) - vldrImm; export ptr; } +vldrRn: "["^pc^",#"^vldrImm^"]" is TMode=1 & thv_Rn=15 & pc & thv_immed & thv_c2323=1 [ vldrImm = thv_immed * 4; ] { ptr:4 = ((inst_start + 4) & 0xfffffffc) + vldrImm; export ptr; } + +:vldr^COND^".64" Dd,vldrRn is COND & ( ($(AMODE) & ARMcond=1 & c2427=13 & c2021=1 & c0811=11) | ($(TMODE_E) & thv_c2427=13 & thv_c2021=1 & thv_c0811=11)) & Dd & vldrRn +{ + Dd = *:8 vldrRn; +} + +:vldr^COND^".32" Sd,vldrRn is COND & ( ($(AMODE) & ARMcond=1 & c2427=13 & c2021=1 & c0811=10) | ($(TMODE_E) & thv_c2427=13 & thv_c2021=1 & thv_c0811=10)) & Sd & vldrRn +{ + Sd = *:4 vldrRn; +} + +@endif # VFPv2 | VFPv3 + +define pcodeop VectorMin; +define pcodeop VectorMax; +define pcodeop FloatVectorMin; +define pcodeop FloatVectorMax; +define pcodeop VectorMultiplyAccumulate; +define pcodeop VectorMultiplySubtract; +define pcodeop VectorMultiplySubtractLong; +define pcodeop VectorDoubleMultiplyHighHalf; +define pcodeop VectorRoundDoubleMultiplyHighHalf; +define pcodeop VectorDoubleMultiplyLong; +define pcodeop VectorDoubleMultiplyAccumulateLong; +define pcodeop VectorDoubleMultiplySubtractLong; +define pcodeop FloatVectorMultiplyAccumulate; +define pcodeop FloatVectorMultiplySubtract; + +@if defined(SIMD) + +:vmax.^udt^esize2021 Dd, Dn, Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=6 & Q6=0 & c0404=0 ) | + ( $(TMODE_EorF) & thv_c2327=0x1e & thv_c2323=0 & thv_c2021<3 & thv_c0811=6 & thv_Q6=0 & thv_c0404=0 ) ) & esize2021 & udt & Dm & Dn & Dd +{ + Dd = VectorMax(Dn,Dm,esize2021,udt); +} + +:vmax.^udt^esize2021 Qd, Qn, Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=6 & Q6=1 & c0404=0 ) | + ( $(TMODE_EorF) & thv_c2327=0x1e & thv_c2323=0 & thv_c2021<3 & thv_c0811=6 & thv_Q6=1 & thv_c0404=0 ) ) & esize2021 & udt & Qm & Qn & Qd +{ + Qd = VectorMax(Qn,Qm,esize2021,udt); +} + +:vmax.f32 Dd,Dn,Dm is (($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=0 & c0811=15 & Q6=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=15 & thv_Q6=0 & thv_c0404=0)) & Dm & Dn & Dd +{ + Dd = FloatVectorMax(Dn,Dm,2:4,32:1); +} + +:vmax.f32 Qd,Qn,Qm is (($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=0 & c0811=15 & Q6=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=15 & thv_Q6=1 & thv_c0404=0)) & Qm & Qn & Qd +{ + Qd = FloatVectorMax(Qn,Qm,2:4,32:1); +} + +:vmin.^udt^esize2021 Dd, Dn, Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=6 & Q6=0 & c0404=1 ) | + ( $(TMODE_EorF) & thv_c2327=0x1e & thv_c2323=0 & thv_c2021<3 & thv_c0811=6 & thv_Q6=0 & thv_c0404=1 ) ) & esize2021 & udt & Dm & Dn & Dd + +{ + Dd = VectorMin(Dn,Dm,esize2021,udt); +} + +:vmin.^udt^esize2021 Qd, Qn, Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=6 & Q6=1 & c0404=1 ) | + ( $(TMODE_EorF) & thv_c2327=0x1e & thv_c2323=0 & thv_c2021<3 & thv_c0811=6 & thv_Q6=1 & thv_c0404=1 ) ) & esize2021 & udt & Qm & Qn & Qd + +{ + Qd = VectorMin(Qn,Qm,esize2021,udt); +} + +:vmin.f32 Dd,Dn,Dm is (($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=2 & c0811=15 & Q6=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=2 & thv_c0811=15 & thv_Q6=0 & thv_c0404=0)) & Dm & Dn & Dd +{ + Dd = FloatVectorMin(Dn,Dm,2:4,32:1); +} + +:vmin.f32 Qd,Qn,Qm is (($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=2 & c0811=15 & Q6=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=2 & thv_c0811=15 & thv_Q6=1 & thv_c0404=0)) & Qm & Qn & Qd +{ + Qd = FloatVectorMin(Qn,Qm,2:4,32:1); +} + +:vmla.i^esize2021 Dd,Dn,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021<3 & c0811=9 & Q6=0 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=9 & thv_Q6=0 & thv_c0404=0)) & esize2021 & Dm & Dn & Dd +{ + Dd = VectorMultiplyAccumulate(Dn,Dm,esize2021,0:1); +} + +:vmla.i^esize2021 Qd,Qn,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021<3 & c0811=9 & Q6=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=9 & thv_Q6=1 & thv_c0404=0)) & esize2021 & Qm & Qn & Qd +{ + Qd = VectorMultiplyAccumulate(Qn,Qm,esize2021,0:1); +} + +:vmls.i^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2424=1 & c2021<3 & c0811=9 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=9 & thv_Q6=0 & thv_c0404=0)) & esize2021 & Dm & Dn & Dd +{ + Dd = VectorMultiplySubtract(Dn,Dm,esize2021,0:1); +} + +:vmls.i^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2424=1 & c2021<3 & c0811=9 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2021<3 & thv_c0811=9 & thv_Q6=1 & thv_c0404=0)) & esize2021 & Qm & Qn & Qd +{ + Qd = VectorMultiplySubtract(Qn,Qm,esize2021,0:1); +} + +:vmlal.^udt^esize2021 Qd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=8 & Q6=0 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=8 & thv_Q6=0 & thv_c0404=0 ) ) & Dm & Dn & Qd & udt & esize2021 +{ + Qd = VectorMultiplyAccumulate(Dn,Dm,esize2021,udt); +} + +:vmlsl.^udt^esize2021 Qd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=10 & Q6=0 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=10 & thv_Q6=0 & thv_c0404=0 ) ) & Dm & Dn & Qd & udt & esize2021 +{ + Qd = VectorMultiplySubtractLong(Dn,Dm,esize2021,udt); +} + +:vmla.f^fesize2020 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2121=0 & c0811=13 & Q6=0 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2121=0 & thv_c0811=13 & thv_c0606=0 & thv_c0404=1)) & fesize2020 & Dn & Dd & Dm +{ + Dd = FloatVectorMultiplyAccumulate(Dn,Dm,fesize2020,8:1); +} + +:vmla.f^fesize2020 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2121=0 & c0811=13 & Q6=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2121=0 & thv_c0811=13 & thv_c0606=1 & thv_c0404=1)) & fesize2020 & Qn & Qd & Qm +{ + Qd = FloatVectorMultiplyAccumulate(Qn,Qm,fesize2020,16:1); +} + +:vmls.f^fesize2020 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2121=1 & c0811=13 & Q6=0 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2121=1 & thv_c0811=13 & thv_c0606=0 & thv_c0404=1)) & fesize2020 & Dn & Dd & Dm +{ + Dd = FloatVectorMultiplySubtract(Dn,Dm,fesize2020,8:1); +} + +:vmls.f^fesize2020 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2121=1 & c0811=13 & Q6=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2121=1 & thv_c0811=13 & thv_c0606=1 & thv_c0404=1)) & fesize2020 & Qn & Qd & Qm +{ + Qd = FloatVectorMultiplySubtract(Qn,Qm,fesize2020,16:1); +} + +@endif # SIMD + +@if defined(VFPv2) || defined(VFPv3) + +:vmla^COND^".f32" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=0 & c0811=10 & c0606=0 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=0 & thv_c0811=10 & thv_c0606=0 & thv_c0404=0)) & COND & Sm & Sn & Sd +{ + Sd = Sd f+ (Sn f* Sm); +} + +:vmla^COND^".f64" Dd,Dn,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=0 & c0811=11 & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=0 & thv_c0811=11 & thv_c0606=0 & thv_c0404=0)) & COND & Dm & Dn & Dd +{ + Dd = Dd f+ (Dn f* Dm); +} + +:vmls^COND^".f32" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=0 & c0811=10 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=0 & thv_c0811=10 & thv_c0606=1 & thv_c0404=0)) & COND & Sm & Sn & Sd +{ + Sd = Sd f- (Sn f* Sm); +} + +:vmls^COND^".f64" Dd,Dn,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=0 & c0811=11 & c0606=1 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=0 & thv_c0811=11 & thv_c0606=1 & thv_c0404=0)) & COND & Dm & Dn & Dd +{ + Dd = Dd f- (Dn f* Dm); +} + +@endif # VFPv2 || VFPv3 + +@if defined(SIMD) + +##### +# VML* (by scalar) (A1) +# + +vmlDm: Dm_3^"["^index^"]" is TMode=0 & c2021=1 & Dm_3 & M5 & c0303 [ index = (M5 << 1) + c0303; ] { el:4 = VectorGetElement(Dm_3, index:1, 2:1, 0:1); export el; } +vmlDm: Dm_4^"["^M5^"]" is TMode=0 & c2021=2 & Dm_4 & M5 { el:4 = VectorGetElement(Dm_4, M5:1, 4:1, 0:1); export el; } +vmlDm: thv_Dm_3^"["^index^"]" is TMode=1 & thv_c2021=1 & thv_Dm_3 & thv_M5 & thv_c0303 [ index = (thv_M5 << 1) + thv_c0303; ] { el:4 = VectorGetElement(thv_Dm_3, index:1, 2:1, 0:1); export el; } +vmlDm: thv_Dm_4^"["^thv_M5^"]" is TMode=1 & thv_c2021=2 & thv_Dm_4 & thv_M5 { el:4 = VectorGetElement(thv_Dm_4, thv_M5:1, 4:1, 0:1); export el; } + + +:vmla.i^esize2021 Dd,Dn,vmlDm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & (c2021=1 | c2021=2) & c0811=0 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0 & thv_c0606=1 & thv_c0404=0)) & esize2021 & Dn & Dd & vmlDm +{ + Dd = VectorMultiplyAccumulate(Dn,vmlDm,esize2021); +} + +:vmla.i^esize2021 Qd,Qn,vmlDm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & (c2021=1 | c2021=2) & c0811=0 & c0606=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0 & thv_c0606=1 & thv_c0404=0)) & esize2021 & Qn & Qd & vmlDm +{ + Qd = VectorMultiplyAccumulate(Qn,vmlDm,esize2021); +} + +:vmla.f32 Dd,Dn,vmlDm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2021=2 & c0811=1 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c2021=2 & thv_c0811=1 & thv_c0606=1 & thv_c0404=0)) & Dn & Dd & vmlDm +{ + Dd = FloatVectorMultiplyAccumulate(Dn,vmlDm,2:4,32:1); +} + +:vmla.f32 Qd,Qn,vmlDm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2021=2 & c0811=1 & c0606=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=2 & thv_c0811=1 & thv_c0606=1 & thv_c0404=0)) & Qn & Qd & vmlDm +{ + Qd = FloatVectorMultiplyAccumulate(Qn,vmlDm,2:4,32:1); +} + +:vmls.i^esize2021 Dd,Dn,vmlDm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & (c2021=1 | c2021=2) & c0811=4 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=4 & thv_c0606=1 & thv_c0404=0)) & esize2021 & Dn & Dd & vmlDm +{ + Dd = VectorMultiplySubtract(Dn,vmlDm,esize2021); +} + +:vmls.i^esize2021 Qd,Qn,vmlDm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & (c2021=1 | c2021=2)& c0811=4 & c0606=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=4 & thv_c0606=1 & thv_c0404=0)) & esize2021 & Qn & Qd & vmlDm +{ + Qd = VectorMultiplySubtract(Qn,vmlDm,esize2021); +} + +:vmls.f32 Dd,Dn,vmlDm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & c2021=2 & c0811=5 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c2021=2 & thv_c0811=5 & thv_c0606=1 & thv_c0404=0)) & Dn & Dd & vmlDm +{ + Dd = FloatVectorMultiplySubtract(Dn,vmlDm,2:4,32:1); +} + +:vmls.f32 Qd,Qn,vmlDm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & c2021=2 & c0811=5 & c0606=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=2 & thv_c0811=5 & thv_c0606=1 & thv_c0404=0)) & Qn & Qd & vmlDm +{ + Qd = FloatVectorMultiplySubtract(Qn,vmlDm,2:4,32:1); +} + +##### +# VML* (by scalar) (A2) +# + + + +:vmlal.^udt^esize2021 Qd,Dn,vmlDm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & (c2021=1 | c2021=2) & c0811=2 & Q6=1 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=2 & thv_Q6=1 & thv_c0404=0 ) ) & udt & esize2021 & Dn & Qd & vmlDm +{ + Qd = VectorMultiplyAccumulate(Dn,vmlDm,esize2021,udt); +} + +:vmlsl.^udt^esize2021 Qd,Dn,vmlDm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & (c2021=1 | c2021=2) & c0811=6 & Q6=1 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=6 & thv_Q6=1 & thv_c0404=0 ) ) & udt & esize2021 & Dn & Qd & vmlDm +{ + Qd = VectorMultiplySubtract(Dn,vmlDm,esize2021,udt); +} + +# Addresses all versions of F6.1.134 except A2/T2 with Q=0 +:vmov.^simdExpImmDT Dd,simdExpImm_8 is (( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0707=0 & Q6=0 & c0404=1 ) | + ( $(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0707=0 & thv_Q6=0 & thv_c0404=1 )) & Dd & simdExpImmDT & simdExpImm_8 +{ + Dd = simdExpImm_8; +} + +# Addresses all versions of F6.1.134 except At/T2 with Q=1 +:vmov.^simdExpImmDT Qd,simdExpImm_16 is (( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0707=0 & Q6=1 & c0404=1 ) | + ( $(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0707=0 & thv_Q6=1 & thv_c0404=1 )) & Qd & simdExpImmDT & simdExpImm_16 +{ + Qd = simdExpImm_16; +} + +@endif # SIMD + +@if defined(VFPv3) + +# F6.1.134 vmov A2/T2 + +:vmov^COND^".f16" Sd,vfpExpImm_4 is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c0411=0x90 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c0411=0x90 ) ) & COND & Sd & vfpExpImm_4 +{ + build COND; + Sd = vfpExpImm_4; +} + +:vmov^COND^".f32" Sd,vfpExpImm_4 is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c0411=0xa0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c0411=0xa0 ) ) & COND & Sd & vfpExpImm_4 +{ + build COND; + Sd = vfpExpImm_4; +} + +# F6.1.134 vmov A2/T2 +:vmov^COND^".f64" Dd,vfpExpImm_8 is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c0411=0xb0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c0411=0xb0 ) ) & COND & Dd & vfpExpImm_8 +{ + build COND; + Dd = vfpExpImm_8; +} + +@endif # VFPv3 + +@if defined(SIMD) + +:vmov Dd,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=2 & c1619=c0003 & c0811=1 & c0707=c0505 & Q6=0 & c0404=1 ) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=2 & thv_c1619=thv_c0003 & thv_c0811=1 & thv_c0707=thv_c0505 & thv_c0606=0 & thv_c0404=1) ) & Dd & Dm +{ + Dd = Dm; +} + +:vmov Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=2 & c1619=c0003 & c0811=1 & c0707=c0505 & Q6=1 & c0404=1 ) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=2 & thv_c1619=thv_c0003 & thv_c0811=1 & thv_c0707=thv_c0505 & thv_c0606=1 & thv_c0404=1) ) & Qd & Qm +{ + Qd = Qm; +} + +@endif # SIMD + +@if defined(VFPv2) || defined(VFPv3) + +:vmov^COND^".f32" Sd,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x30 & c0611=0x29 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x30 & thv_c0611=0x29 & thv_c0404=0) ) & COND & Sd & Sm +{ + Sd = Sm; +} + +:vmov^COND^".f64" Dd,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x30 & c0611=0x2d & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x30 & thv_c0611=0x2d & thv_c0404=0) ) & COND & Dd & Dm +{ + Dd = Dm; +} + +@endif # VFPv2 || VFPv3 + +define pcodeop VectorSetElement; + +@if defined(SIMD) + +vmovIndex: val is TMode=0 & c2222=1 & c2121 & c0506 [ val = (c2121 << 2) + c0506; ] { tmp:1 = val; export tmp; } +vmovIndex: val is TMode=0 & c2222=0 & c2121 & c0606 & c0505=1 [ val = (c2121 << 1) + c0606; ] { tmp:1 = val; export tmp; } + +vmovIndex: val is TMode=1 & thv_c2222=1 & thv_c2121 & thv_c0506 [ val = (thv_c2121 << 2) + thv_c0506; ] { tmp:1 = val; export tmp; } +vmovIndex: val is TMode=1 & thv_c2222=0 & thv_c2121 & thv_c0606 & thv_c0505=1 [ val = (thv_c2121 << 1) + thv_c0606; ] { tmp:1 = val; export tmp; } + +@if defined(VFPv2) || defined(VFPv3) || defined(SIMD) + +vmovIndex: c2121 is TMode=0 & c2222=0 & c2121 & c0506=0 { tmp:1 = c2121; export tmp; } +vmovIndex: thv_c2121 is TMode=1 & thv_c2222=0 & thv_c2121 & thv_c0506=0 { tmp:1 = thv_c2121; export tmp; } + +@endif # VFPv2 || VFPv3 || SIMD + + +dNvmovIndex: Dn^"["^vmovIndex^"]" is Dn & vmovIndex { } + + +:vmov^COND^".8" dNvmovIndex,VRd is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2222=1 & c2020=0 & c0811=11 & c0404=1 & c0003=0 ) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2222=1 & thv_c2020=0 & thv_c0811=11 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex +{ + el:1 = VRd(0); + vmask:8 = 0xf << (vmovIndex*8); + Dn = (Dn & ~vmask) | (zext(el) & vmask); + #VectorSetElement(VRd,Dn,vmovIndex); +} + +:vmov^COND^".16" dNvmovIndex,VRd is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2222=0 & c2020=0 & c0811=11 & c0505=1 & c0404=1 & c0003=0 ) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2222=0 & thv_c2020=0 & thv_c0811=11 & thv_c0505=1 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex +{ + el:2 = VRd(0); + vmask:8 = 0xff << (vmovIndex*16); + Dn = (Dn & ~vmask) | (zext(el) & vmask); + #VectorSetElement(VRd,Dn,vmovIndex,vmovSize); +} + + +:vmov^COND^".32" dNvmovIndex,VRd is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2222=0 & c2020=0 & c0811=11 & c0506=0 & c0404=1 & c0003=0 ) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2222=0 & thv_c2020=0 & thv_c0811=11 & thv_c0506=0 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex +{ + el:4 = VRd; + vmask:8 = 0xffff << (vmovIndex*32); + Dn = (Dn & ~vmask) | (zext(el) & vmask); + #VectorSetElement(VRd,Dn,vmovIndex,vmovSize); +} + + +:vmov^COND^".u8" VRd,dNvmovIndex is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2222=1 & c2020=1 & c0811=11 & c0404=1 & c0003=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2222=1 & thv_c2020=1 & thv_c0811=11 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex +{ + val:8 = Dn >> (vmovIndex*8); + result:1 = val(0); + VRd = zext(result); + #VRd = VectorGetElement(Dn,vmovIndex,vmovSize,0:1); +} + +:vmov^COND^".u16" VRd,dNvmovIndex is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2222=0 & c2020=1 & c0811=11 & c0505=1 & c0404=1 & c0003=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2222=0 & thv_c2020=1 & thv_c0811=11 & thv_c0505=1 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex +{ + val:8 = Dn >> (vmovIndex*16); + result:2 = val(0); + VRd = zext(result); + #VRd = VectorGetElement(Dn,vmovIndex,vmovSize,0:1); +} + +:vmov^COND^".u32" VRd,dNvmovIndex is ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2222=0 & c2020=1 & c0811=11 & c0506=0 & c0404=1 & c0003=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2222=0 & thv_c2020=1 & thv_c0811=11 & thv_c0506=0 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex +{ + val:8 = Dn >> (vmovIndex*32); + result:4 = val(0); + VRd = zext(result); + #VRd = VectorGetElement(Dn,vmovIndex,vmovSize,0:1); +} + +:vmov^COND^".s8" VRd,dNvmovIndex is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2222=1 & c2020=1 & c0811=11 & c0404=1 & c0003=0 ) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2222=1 & thv_c2020=1 & thv_c0811=11 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex +{ + val:8 = Dn >> (vmovIndex*8); + result:1 = val(0); + VRd = sext(result); + #VRd = VectorGetElement(Dn,vmovIndex,vmovSize,0:1); +} + +:vmov^COND^".s16" VRd,dNvmovIndex is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2222=0 & c2020=1 & c0811=11 & c0505=1 & c0404=1 & c0003=0 ) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2222=0 & thv_c2020=1 & thv_c0811=11 & thv_c0505=1 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex +{ + val:8 = Dn >> (vmovIndex*16); + result:2 = val(0); + VRd = sext(result); + #VRd = VectorGetElement(Dn,vmovIndex,vmovSize,0:1); +} + +:vmov^COND^".s32" VRd,dNvmovIndex is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2222=0 & c2020=1 & c0811=11 & c0506=0 & c0404=1 & c0003=0 ) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2222=0 & thv_c2020=1 & thv_c0811=11 & thv_c0506=0 & thv_c0404=1 & thv_c0003=0 ) ) & COND & Dn & VRd & vmovIndex & dNvmovIndex +{ + val:8 = Dn >> (vmovIndex*32); + result:4 = val(0); + VRd = sext(result); + #VRd = VectorGetElement(Dn,vmovIndex,vmovSize,0:1); +} + +@endif # SIMD + + +@if defined(VFPv2) || defined(VFPv3) + +:vmov^COND Sn,VRd is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2122=0 & c2020=0 & c0811=10 & c0006=0x10) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2122=0 & thv_c2020=0 & thv_c0811=10 & thv_c0006=0x10) ) & COND & Sn & VRd +{ + Sn = VRd; +} + +:vmov^COND VRd,Sn is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2122=0 & c2020=1 & c0811=10 & c0006=0x10) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2122=0 & thv_c2020=1 & thv_c0811=10 & thv_c0006=0x10) ) & COND & Sn & VRd +{ + VRd = Sn; +} + +:vmov^COND Sm,SmNext,VRd,VRn is ( ($(AMODE) & ARMcond=1 & c2027=0xc4 & c0611=0x28 & c0404=1) | + ($(TMODE_E) & thv_c2027=0xc4 & thv_c0611=0x28 & thv_c0404=1) ) & COND & VRn & VRd & Sm & SmNext +{ + Sm = VRd; + SmNext = VRn; +} + +:vmov^COND VRd,VRn,Sm,SmNext is ( ($(AMODE) & ARMcond=1 & c2027=0xc5 & c0611=0x28 & c0404=1) | + ($(TMODE_E) & thv_c2027=0xc5 & thv_c0611=0x28 & thv_c0404=1) ) & COND & VRn & VRd & Sm & SmNext +{ + VRd = Sm; + VRn = SmNext; +} + +@endif # VFPv2 || VFPv3 + +@if defined(VFPv2) || defined(VFPv3) || defined(SIMD) + +:vmov^COND Dm,VRd,VRn is COND & ( ($(AMODE) & ARMcond=1 & c2027=0xc4 & c0611=0x2c & c0404=1) | ($(TMODE_E) & thv_c2027=0xc4 & thv_c0611=0x2c & thv_c0404=1) ) & Dm & VRn & VRd +{ + Dm = (zext(VRn) << 32) + zext(VRd); +} + +:vmov^COND VRd,VRn,Dm is COND & ( ($(AMODE) & ARMcond=1 & c2027=0xc5 & c0611=0x2c & c0404=1) | ($(TMODE_E) & thv_c2027=0xc5 & thv_c0611=0x2c & thv_c0404=1) ) & Dm & VRn & VRd +{ + VRn = Dm(4); + VRd = Dm:4; +} + +@endif # VFPv2 || VFPv3 || SIMD + +define pcodeop VectorCopyLong; +define pcodeop VectorCopyNarrow; + +@if defined(SIMD) + +:vmovl.^udt^esize2021 Qd,Dm is (($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & (c1921=1 | c1921=2 | c1921=4) & c1618=0 & c0611=0x28 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1f & (thv_c1921=1 | thv_c1921=2 | thv_c1921=4) & thv_c1618=0 & thv_c0611=0x28 & thv_c0404=1) ) & esize2021 & udt & Qd & Dm +{ + Qd = VectorCopyLong(Dm,esize2021,udt); +} + +:vmovn.i^esize1819x2 Dd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0611=8 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0611=8 & thv_c0404=0) ) & esize1819x2 & Dd & Qm +{ + Dd = VectorCopyNarrow(Qm,esize1819x2); +} + +:vmovx.F16 Sd,Sm is (($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1d & c1921=0x6 & c1618=0 & c0611=0x29 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1d & thv_c1921=0x6 & thv_c1618=0 & thv_c0611=0x29 & thv_c0404=0) ) & Sd & Sm +{ + local SmUpper:2 = Sm(2); + Sd = zext(SmUpper); +} + +@endif # SIMD + +@if defined(VFPv2) || defined(VFPv3) || defined(SIMD) + +:vmrs^COND VRd,fpscr is COND & ( ($(AMODE) & ARMcond=1 & c1627=0xef1 & c0011=0xa10) | + ($(TMODE_E) & thv_c1627=0xef1 & thv_c0011=0xa10)) & fpscr & VRd +{ + VRd = fpscr; +} + +apsr: "apsr" is epsilon {} + +:vmrs^COND apsr,fpscr is ( ($(AMODE) & ARMcond=1 & c1627=0xef1 & c1215=15 & c0011=0xa10) | + ($(TMODE_E) & thv_c1627=0xef1 & thv_c1215=15 & thv_c0011=0xa10) +) & COND & apsr & fpscr +{ + NG = $(FPSCR_N); + ZR = $(FPSCR_Z); + CY = $(FPSCR_C); + OV = $(FPSCR_V); +} + +:vmsr^COND fpscr,VRd is ( ($(AMODE) & ARMcond=1 & c1627=0xee1 & c0011=0xa10) | + ($(TMODE_E) & thv_c1627=0xee1 & thv_c0011=0xa10) +) & COND & VRd & fpscr +{ + fpscr = VRd; +} + +@endif # VFPv2 || VFPv3 || SIMD + +@if defined(SIMD) + +### +# VMUL (floating Point) +# + +define pcodeop FloatVectorMult; +define pcodeop VectorMultiply; +define pcodeop PolynomialMultiply; + +:vmul.f32 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x06 & c2121=0 & c2020=0 & c0811=0xd & Q6=0 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=0 & thv_c2020=0 & thv_c0811=0xd & thv_Q6=0 & thv_c0404=1)) & Dn & Dd & Dm +{ + Dd = FloatVectorMult(Dn,Dm,2:1,32:1); +} + +:vmul.f32 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x06 & c2121=0 & c2020=0 & c0811=0xd & Q6=1 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=0 & thv_c2020=0 & thv_c0811=0xd & thv_Q6=1 & thv_c0404=1) ) & Qm & Qn & Qd +{ + Qd = FloatVectorMult(Qn,Qm,2:1,32:1); +} + +:vmul.f16 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x06 & c2121=0 & c2020=1 & c0811=13 & Q6=0 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=0 & thv_c2020=1 & thv_c0811=13 & thv_Q6=0 & thv_c0404=1)) & Dn & Dd & Dm +{ + Dd = FloatVectorMult(Dn,Dm,4:1,16:1); +} + +:vmul.f16 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x06 & c2121=0 & c2020=1 & c0811=13 & Q6=1 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2121=0 & thv_c2020=1 & thv_c0811=13 & thv_Q6=1 & thv_c0404=1) ) & Qm & Qn & Qd +{ + Qd = FloatVectorMult(Qn,Qm,4:1,16:1); +} + +:vmul^COND^".f64" Dd,Dn,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=2 & c0811=11 & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=11 & thv_c0606=0 & thv_c0404=0) ) & COND & Dm & Dn & Dd +{ + Dd = Dn f* Dm; +} + +:vmul^COND^".f32" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=2 & c0811=10 & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=10 & thv_c0606=0 & thv_c0404=0) ) & COND & Sm & Sn & Sd +{ + Sd = Sn f* Sm; +} + +:vmul^COND^".f16" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=2 & c0811=9 & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=9 & thv_c0606=0 & thv_c0404=0) ) & COND & Sm & Sn & Sd +{ + product:2 = Sn:2 f* Sm:2; + Sd = zext(product); +} + +### +# VMUL (Integer and polynomial) +# + +:vmul.i^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c0811=9 & Q6=0 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=9 & thv_Q6=0 & thv_c0404=1)) & esize2021 & Dn & Dd & Dm +{ + Dd = VectorMultiply(Dn,Dm,esize2021); +} + +:vmul.i^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c0811=9 & Q6=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=9 & thv_Q6=1 & thv_c0404=1)) & esize2021 & Qm & Qn & Qd +{ + Qd = VectorMultiply(Qn,Qm,esize2021); +} + +:vmul.p8 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2021=0 & c0811=9 & Q6=0 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=9 & thv_Q6=0 & thv_c0404=1) ) & Dn & Dd & Dm +{ + Dd = PolynomialMultiply(Dn,Dm,1:1); +} + +:vmul.p8 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c2021=0 & c0811=9 & Q6=1 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=9 & thv_Q6=1 & thv_c0404=1) ) & Qm & Qn & Qd +{ + Qd = PolynomialMultiply(Qn,Qm,1:1); +} + +:vmull.^udt^esize2021 Qd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=0xc & Q6=0 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=0xc & thv_Q6=0 & thv_c0404=0) ) & esize2021 & Dm & Dn & Qd & udt +{ + Qd = VectorMultiply(Dn,Dm,esize2021,udt); +} + +:vmull.p8 Qd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x5 & c2021=0 & c0811=0xe & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=0 & thv_c0811=0xe & thv_Q6=0 & thv_c0404=0) ) & Dm & Dn & Qd +{ + Qd = PolynomialMultiply(Dn,Dm,1:1); +} + +:vmull.p64 Qd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x5 & c2021=2 & c0811=0xe & Q6=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c2021=2 & thv_c0811=0xe & thv_Q6=0 & thv_c0404=0) ) & Dm & Dn & Qd +{ + Qd = PolynomialMultiply(Dn,Dm,8:1); +} + +# The below is confusing but these sub-constructors are used in a combination of F6.1.148 VMUL (by scalar) and F6.1.150 VMULL (by Scalar) + +etype: "I" is TMode=0 & c0909=0 & c0808=0 {} +etype: "F" is TMode=0 & c0909=0 & c0808=1 {} +etype: "S" is TMode=0 & c0909=1 & c2424=0 {} +etype: "U" is TMode=0 & c0909=1 & c2424=1 {} +etype: "I" is TMode=1 & thv_c0909=0 & thv_c0808=0 {} +etype: "F" is TMode=1 & thv_c0909=0 & thv_c0808=1 {} +etype: "S" is TMode=1 & thv_c0909=1 & thv_c2828=0 {} +etype: "U" is TMode=1 & thv_c0909=1 & thv_c2828=1 {} + +vmlDmA: Dm_3^"["^index^"]" is TMode=0 & c2021=1 & Dm_3 & M5 & c0303 [ index = (M5 << 1) + c0303; ] { el:4 = VectorGetElement(Dm_3, index:1, 2:1, 0:1); export el; } +vmlDmA: Dm_4^"["^M5^"]" is TMode=0 & c2021=2 & Dm_4 & M5 { el:4 = VectorGetElement(Dm_4, M5:1, 4:1, 0:1); export el; } +vmlDmA: Dm_3^"["^index^"]" is TMode=1 & thv_c2021=1 & Dm_3 & thv_M5 & c0303 [ index = (thv_M5 << 1) + c0303; ] { el:4 = VectorGetElement(Dm_3, index:1, 2:1, 0:1); export el; } +vmlDmA: Dm_4^"["^thv_M5^"]" is TMode=1 & thv_c2021=2 & Dm_4 & thv_M5 { el:4 = VectorGetElement(Dm_4, thv_M5:1, 4:1, 0:1); export el; } + +:vmul.^etype^esize2021 Qd,Qn,vmlDmA is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x07 & (c2021=1 | c2021=2) & c0911=4 & c0606=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0911=4 & thv_c0606=1 & thv_c0404=0 ) ) & etype & esize2021 & Qn & Qd & vmlDmA +{ + Qd = VectorMultiply(Qn,vmlDmA,esize2021); +} + +:vmul.^etype^esize2021 Dd,Dn,vmlDmA is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x5 & (c2021=1 | c2021=2) & c0911=4 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0911=4 & thv_c0606=1 & thv_c0404=0 ) ) & etype & esize2021 & Dn & Dd & vmlDmA +{ + Dd = VectorMultiply(Dn,vmlDmA,esize2021); +} + +:vmull.^etype^esize2021 Qd,Dn,vmlDmA is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & (c2021=1 | c2021=2) & c0811=10 & c0606=1 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=10 & thv_c0606=1 & thv_c0404=0 ) ) & Dd & Dm & esize1819 & etype & esize2021 & Dn & Qd & vmlDmA +{ + Qd = VectorMultiply(Dn,vmlDmA,esize2021); +} + +### +# VMVN (immediate) +# + +:vmvn.i32 Dd,simdExpImm_8 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011=0 & c0808=0 & c0407=3 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011=0 & thv_c0808=0 & thv_c0407=3) ) & Dd & simdExpImm_8 +{ + Dd = ~simdExpImm_8; +} + +:vmvn.i32 Qd,simdExpImm_16 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011=0 & c0808=0 & c0407=7 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011=0 & thv_c0808=0 & thv_c0407=7) ) & Qd & simdExpImm_16 +{ + Qd = ~simdExpImm_16; +} + +:vmvn.i16 Dd,simdExpImm_8 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011=2 & c0808=0 & c0407=3 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011=2 & thv_c0808=0 & thv_c0407=3) ) & Dd & simdExpImm_8 +{ + Dd = ~simdExpImm_8; +} + +:vmvn.i16 Qd,simdExpImm_16 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011=2 & c0808=0 & c0407=7 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011=2 & thv_c0808=0 & thv_c0407=7) ) & Qd & simdExpImm_16 +{ + Qd = ~simdExpImm_16; +} + +:vmvn.i32 Dd,simdExpImm_8 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0911=6 & c0808=0 & c0407=3 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0911=6 & thv_c0808=0 & thv_c0407=3) ) & Dd & simdExpImm_8 +{ + Dd = ~simdExpImm_8; +} + +:vmvn.i32 Qd,simdExpImm_16 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0911=6 & c0808=0 & c0407=7 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0911=6 & thv_c0808=0 & thv_c0407=7) ) & Qd & simdExpImm_16 +{ + Qd = ~simdExpImm_16; +} + +### +# VMVN (register) +# + +:vmvn Dd,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1619=0 & c0811=5 & c0707=1 & Q6=0 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1619=0 & thv_c0811=5 & thv_c0707=1 & thv_Q6=0 & thv_c0404=0) ) & Dd & Dm +{ + Dd = ~Dm; +} + +:vmvn Qd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1619=0 & c0811=5 & c0707=1 & Q6=1 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1619=0 & thv_c0811=5 & thv_c0707=1 & thv_Q6=1 & thv_c0404=0) ) & Qd & Qm +{ + tmp1:8 = Qm:8; + tmp2:8 = Qm(8); + tmp1 = ~ tmp1; + tmp2 = ~ tmp2; + Qd = (zext(tmp1) << 8) | zext(tmp2); +} + +define pcodeop FloatVectorNeg; + + +:vneg.s^esize1819 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=7 & Q6=0 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=7 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm & esize1819 +{ + Dd = FloatVectorNeg(Dm,1:1,esize1819); +} + +:vneg.s^esize1819 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=1 & c0711=7 & Q6=1 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=1 & thv_c0711=7 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm & esize1819 +{ + Qd = FloatVectorNeg(Qm,1:1,esize1819); +} + +:vneg.f^fesize1819 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=1 & c0711=0xf & Q6=0 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=1 & thv_c0711=0xf & thv_c0606=0 & thv_c0404=0 ) ) & fesize1819 & Dm & Dd +{ + Dd = FloatVectorNeg(Dm,2:1,fesize1819); +} + +:vneg.f^fesize1819 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819=2 & c1617=1 & c0711=0xf & Q6=1 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819=2 & thv_c1617=1 & thv_c0711=0xf & thv_c0606=1 & thv_c0404=0 ) ) & fesize1819 & Qd & Qm +{ + Qd = FloatVectorNeg(Qm,2:1,fesize1819); +} + +@endif # SIMD + +@if defined(VFPv2) || defined(VFPv3) + + +:vnmla^COND^".f64" Dd,Dn,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=1 & c0811=11 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=1 & thv_c0811=11 & thv_c0606=1 & thv_c0404=0) ) & COND & Dm & Dn & Dd +{ + build COND; + product:8 = Dn f* Dm; + Dd = (f- Dd) f+ (f- product); +} + +:vnmla^COND^".f32" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=1 & c0811=10 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=1 & thv_c0811=10 & thv_c0606=1 & thv_c0404=0) ) & COND & Sm & Sn & Sd +{ + build COND; + product:4 = Sn f* Sm; + Sd = (f- Sd) f+ (f- product); +} + +:vnmla^COND^".f16" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=1 & c0811=9 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=1 & thv_c0811=9 & thv_c0606=1 & thv_c0404=0) ) & COND & Sm & Sn & Sd +{ + build COND; + product:2 = Sn:2 f* Sm:2; + product = (f- Sd:2) f+ (f- product); + Sd = zext(product); +} + +:vnmls^COND^".f64" Dd,Dn,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=1 & c0811=11 & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=1 & thv_c0811=11 & thv_c0606=0 & thv_c0404=0) ) & COND & Dm & Dn & Dd +{ + build COND; + product:8 = Dn f* Dm; + Dd = product f- Dd; +} + +:vnmls^COND^".f32" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=1 & c0811=10 & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=1 & thv_c0811=10 & thv_c0606=0 & thv_c0404=0) ) & COND & Sm & Sn & Sd +{ + build COND; + product:4 = Sn f* Sm; + Sd = product f- Sd; +} + +:vnmls^COND^".f16" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=1 & c0811=9 & c0606=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=1 & thv_c0811=9 & thv_c0606=0 & thv_c0404=0) ) & COND & Sm & Sn & Sd +{ + build COND; + product:2 = Sn:2 f* Sm:2; + product = product f- Sd:2; + Sd = zext(product); +} + +:vnmul^COND^".f64" Dd,Dn,Dm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=2 & c0811=11 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=11 & thv_c0606=1 & thv_c0404=0) ) & COND & Dm & Dn & Dd +{ + build COND; + product:8 = Dn f* Dm; + Dd = f- product; +} + +:vnmul^COND^".f32" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=2 & c0811=10 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=10 & thv_c0606=1 & thv_c0404=0) ) & COND & Sm & Sn & Sd +{ + product:4 = Sn f* Sm; + Sd = f- product; +} + +:vnmul^COND^".f16" Sd,Sn,Sm is ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=2 & c0811=9 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=9 & thv_c0606=1 & thv_c0404=0) ) & COND & Sm & Sn & Sd +{ + build COND; + product:2 = Sn:2 f* Sm:2; + product = f- product; + Sd = zext(product); +} + +:vneg^COND^".f16" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x31 & c0611=0x25 & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x31 & thv_c0611=0x25 & thv_c0404=0 ) ) & COND & Sm & Sd +{ + build COND; + build Sd; + build Sm; + local tmp:2 = Sm(0); + Sd = zext(f- tmp); +} + +:vneg^COND^".f32" Sd,Sm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x31 & c0611=0x29 & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x31 & thv_c0611=0x29 & thv_c0404=0 ) ) & COND & Sm & Sd +{ + build COND; + build Sd; + build Sm; + Sd = f- Sm; +} + +:vneg^COND^".f64" Dd,Dm is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c1621=0x31 & c0611=0x2d & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1d & thv_c1621=0x31 & thv_c0611=0x2d & thv_c0404=0 ) ) & COND & Dd & Dm +{ + build COND; + build Dd; + build Dm; + Dd = f- Dm; +} + +@endif # VFPv2 || VFPv3 + +@if defined(SIMD) + +#F6.1.141 VORR (register) 64-bit SIMD vector variant (A1 and T1) +:vorr Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=2 & c0811=1 & Q6=0 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=2 & thv_c0811=1 & thv_Q6=0 & thv_c0404=1)) & Dn & Dd & Dm + +{ + Dd = Dn | Dm; +} + +#F6.1.141 VORR (register) 128-bit SIMD vector variant (A1 and T1) +:vorr Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=2 & c0811=1 & Q6=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=2 & thv_c0811=1 & thv_Q6=1 & thv_c0404=1)) & Qd & Qn & Qm +{ + Qd = Qn | Qm; +} + +#F6.1.140 VORR and F6.1.138 VORN (immediate) 64-bit SIMD vector variant +:vorr Dd,simdExpImm_8 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011<3 & c0808=1 & c0407=1 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011<3 & thv_c0808=1 & thv_c0407=1) ) & Dd & simdExpImm_8 +{ + Dd = Dd | simdExpImm_8; +} + +#F6.1.140 VORR and F6.1.138 VORN (immediate) 128-bit SIMD vector variant +:vorr Qd,simdExpImm_16 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c1011<3 & c0808=1 & c0407=5 ) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c1011<3 & thv_c0808=1 & thv_c0407=5) ) & Qd & simdExpImm_16 +{ + Qd = Qd | simdExpImm_16; +} + +#F6.1.139 VORN (register) 64-bit SIMD vector variant (A1 and T1) +:vorn Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=3 & c0811=1 & Q6=0 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=3 & thv_c0811=1 & thv_Q6=0 & thv_c0404=1)) & Dn & Dd & Dm + +{ + Dd = Dn | ~Dm; +} + +#F6.1.139 VORN (register) 128-bit SIMD vector variant (A1 and T1) +:vorn Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2021=3 & c0811=1 & Q6=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=3 & thv_c0811=1 & thv_Q6=1 & thv_c0404=1)) & Qd & Qn & Qm +{ + Qd = Qn | ~Qm; +} + +@endif # SIMD + + +####### +# VPUSH (A2) +# + +@if defined(VFPv2) || defined(VFPv3) || defined(SIMD) + +buildVpushSdList: Sreg is counter=0 & Sreg [ regNum=regNum+1; ] { * mult_addr = Sreg; mult_addr = mult_addr + 4; } +buildVpushSdList: Sreg,buildVpushSdList is Sreg & buildVpushSdList [ counter=counter-1; regNum=regNum+1; ] { * mult_addr = Sreg; mult_addr = mult_addr + 4; } + +vpushSdList: "{"^buildVpushSdList^"}" is TMode=0 & D22 & c1215 & c0007 & buildVpushSdList [ regNum=(c1215<<1)+D22-1; counter=c0007-1; ] { sp = sp - c0007 * 4; mult_addr = sp; build buildVpushSdList; } +vpushSdList: "{"^buildVpushSdList^"}" is TMode=1 & thv_D22 & thv_c1215 & thv_c0007 & buildVpushSdList [ regNum=(thv_c1215<<1)+thv_D22-1; counter=thv_c0007-1; ] { sp = sp - thv_c0007 * 4; mult_addr = sp; build buildVpushSdList; } + +buildVpushSd64List: Dreg is counter=0 & Dreg [ regNum=regNum+1; ] { * mult_addr = Dreg:8; mult_addr = mult_addr + 8; } +buildVpushSd64List: Dreg,buildVpushSd64List is Dreg & buildVpushSd64List [ counter=counter-1; regNum=regNum+1; ] { * mult_addr = Dreg:8; mult_addr = mult_addr + 8; build buildVpushSd64List; } + +vpushSd64List: "{"^buildVpushSd64List^"}" is TMode=0 & D22 & c1215 & c0007 & buildVpushSd64List [ regNum=(D22<<4)+c1215-1; counter=c0007 / 2 - 1; ] { sp = sp - c0007 * 4; mult_addr = sp; build buildVpushSd64List; } +vpushSd64List: "{"^buildVpushSd64List^"}" is TMode=1 & thv_D22 & thv_c1215 & thv_c0007 & buildVpushSd64List [ regNum=(thv_D22<<4)+thv_c1215-1; counter=thv_c0007 / 2 - 1; ] { sp = sp - thv_c0007 * 4; mult_addr = sp; build buildVpushSd64List; } + + +:vpush^COND vpushSd64List is ( ($(AMODE) & ARMcond=1 & c2327=0x1a & c1619=13 & c2021=2 & c0811=11 & c0000=0) | + ($(TMODE_E) & thv_c2327=0x1a & thv_c1619=13 & thv_c2021=2 & thv_c0811=11 & thv_c0000=0) ) & COND & vpushSd64List +{ + build vpushSd64List; +} + +:vpush^COND vpushSdList is ( ($(AMODE) & ARMcond=1 & c2327=0x1a & c1619=13 & c2021=2 & c0811=10) | + ($(TMODE_E) & thv_c2327=0x1a & thv_c1619=13 & thv_c2021=2 & thv_c0811=10) ) & COND & vpushSdList +{ + build vpushSdList; +} + +buildVpopSdList: Sreg is counter=0 & Sreg [ regNum=regNum+1; ] + { tmp:4 = *mult_addr; Sreg = zext(tmp); mult_addr = mult_addr + 4; } +buildVpopSdList: Sreg,buildVpopSdList is Sreg & buildVpopSdList [ counter=counter-1; regNum=regNum+1; ] + { tmp:4 = *mult_addr; Sreg = zext(tmp); mult_addr = mult_addr + 4; } + +vpopSdList: "{"^buildVpopSdList^"}" is TMode=0 & D22 & c1215 & c0007 & buildVpopSdList [ regNum=(c1215<<1)+D22-1; counter=c0007-1; ] + { mult_addr = sp; sp = sp + c0007 * 4; build buildVpopSdList; } +vpopSdList: "{"^buildVpopSdList^"}" is TMode=1 & thv_D22 & thv_c1215 & thv_c0007 & buildVpopSdList [ regNum=(thv_c1215<<1)+thv_D22-1; counter=thv_c0007-1; ] + { mult_addr = sp; sp = sp + thv_c0007 * 4; build buildVpopSdList; } + +buildVpopSd64List: Dreg is counter=0 & Dreg [ regNum=regNum+1; ] + { Dreg = *mult_addr; mult_addr = mult_addr + 8; } +buildVpopSd64List: Dreg,buildVpopSd64List is Dreg & buildVpopSd64List [ counter=counter-1; regNum=regNum+1; ] + { Dreg = *mult_addr; mult_addr = mult_addr + 8; build buildVpopSd64List; } + +vpopSd64List: "{"^buildVpopSd64List^"}" is TMode=0 & D22 & c1215 & c0007 & buildVpopSd64List [ regNum=(D22<<4)+c1215-1; counter=c0007 / 2 - 1; ] + { mult_addr = sp; sp = sp + c0007 * 4; build buildVpopSd64List; } +vpopSd64List: "{"^buildVpopSd64List^"}" is TMode=1 & thv_D22 & thv_c1215 & thv_c0007 & buildVpopSd64List [ regNum=(thv_D22<<4)+thv_c1215-1; counter=thv_c0007 / 2 - 1; ] + { mult_addr = sp; sp = sp + thv_c0007 * 4; build buildVpopSd64List; } + +:vpop^COND vpopSd64List is ( ($(AMODE) & ARMcond=1 & c2327=0x19 & c1619=13 & c2021=3 & c0811=11 & c0000=0) | + ($(TMODE_E) & thv_c2327=0x19 & thv_c1619=13 & thv_c2021=3 & thv_c0811=11 & thv_c0000=0) ) & COND & vpopSd64List +{ + build vpopSd64List; +} + +:vpop^COND vpopSdList is ( ($(AMODE) & ARMcond=1 & c2327=0x19 & c1619=13 & c2021=3 & c0811=10) | + ($(TMODE_E) & thv_c2327=0x19 & thv_c1619=13 & thv_c2021=3 & thv_c0811=10) ) & COND & vpopSdList +{ + build vpopSdList; +} + +@endif # VFPv2 || VFPv3 || SIMD + +@if defined(SIMD) + +define pcodeop SatQ; +define pcodeop SignedSatQ; + +:vqabs^".s"^esize1819 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0811=7 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0811=7 & thv_Q6=0 & thv_c0404=0)) & esize1819 & Dn & Dd & Dm +{ + Dd = VectorAbs(Dn,Dm,esize1819); + Dd = SatQ(Dd, esize1819, 0:1); +} + +:vqabs^".s"^esize1819 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0811=7 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0811=7 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qm & Qn & Qd +{ + Qd = VectorAbs(Qn,Qm,esize1819); + Qd = SatQ(Qd, esize1819, 0:1); +} + +:vqadd.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c0811=0 & Q6=0 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c0811=0 & thv_Q6=0 & thv_c0404=1)) & udt & esize2021 & Dn & Dd & Dm +{ + Dd = VectorAdd(Dn,Dm,esize2021,udt); + Dd = SatQ(Dd, esize2021, udt); +} + +:vqadd.^udt^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c0811=0 & Q6=1 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c0811=0 & thv_Q6=1 & thv_c0404=1) ) & udt & esize2021 & Qm & Qn & Qd +{ + Qd = VectorAdd(Qn,Qm,esize2021,udt); + Qd = SatQ(Qd, esize2021, udt); +} + +:vqmovn.i^esize1819x2 Dd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0711=5 & c0606 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0711=5 & thv_c0404=0) ) & esize1819x2 & Dd & Qm +{ + Dd = VectorCopyNarrow(Qm,esize1819x2,c0606:1); + Dd = SatQ(Dd, esize1819x2,0:1); +} + +:vqmovun.i^esize1819x2 Dd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0611=9 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0611=9 & thv_c0404=0) ) & esize1819x2 & Dd & Qm +{ + Dd = VectorCopyNarrow(Qm,esize1819x2,0:1); + Dd = SatQ(Dd, esize1819x2,0:1); +} + +:vqdmlal.S^esize2021 Qd,Dn,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=5 & (c2021=1 | c2021=2) & c0811=0x9 & c0606=0 & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0x9 & thv_c0606=0 & thv_c0404=0 ) ) & esize2021 & Dm & Dn & Qd + +{ + Qd = VectorDoubleMultiplyAccumulateLong(Dn,Dm,esize2021,0:1); + Qd = SatQ(Qd, esize2021,0:1); +} + +:vqdmlal.S^esize2021 Qd,Dn,vmlDmA is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=5 & (c2021=1 | c2021=2) & c0811=0x3 & c0606=1 & c0404=0) | + ( $(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0x3 & thv_c0606=1 & thv_c0404=0 ) ) & esize2021 & vmlDmA & Dn & Qd + +{ + Qd = VectorDoubleMultiplyAccumulateLong(Dn,vmlDmA,esize2021,0:1); + Qd = SatQ(Qd, esize2021,0:1); +} + +:vqdmlsl.S^esize2021 Qd, Dn, Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=5 & (c2021=1 | c2021=2) & c0811=0xb & c0606=0 & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0xb & thv_c0606=0 & thv_c0404=0 ) ) & esize2021 & Dm & Dn & Qd + +{ + Qd = VectorDoubleMultiplySubtractLong(Dn,Dm,esize2021,0:1); + Qd = SatQ(Qd, esize2021,0:1); +} + +:vqdmlsl.S^esize2021 Qd, Dn, vmlDmA is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=5 & (c2021=1 | c2021=2)& c0811=0x7 & c0606=1 & c0404=0) | + ( $(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0x7 & thv_c0606=1 & thv_c0404=0 ) ) & esize2021 & vmlDmA & Dn & Qd + +{ + Qd = VectorDoubleMultiplySubtractLong(Dn,vmlDmA,esize2021,0:1); + Qd = SatQ(Qd, esize2021,0:1); +} + +:vqdmulh.S^esize2021 Dd, Dn, Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2324=0 & (c2021=1 | c2021=2) & c0811=0xb & Q6=0 & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1e & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0xb & thv_c0606=0 & thv_c0404=0 ) ) & esize2021 & Dm & Dn & Dd + +{ + Dd = VectorDoubleMultiplyHighHalf(Dn,Dm,esize2021,0:1); + Dd = SatQ(Dd, esize2021,0:1); +} + +:vqdmulh.S^esize2021 Qd, Qn, Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2324=0 & (c2021=1 | c2021=2) & c0811=0xb & Q6=1 & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1e & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0xb & thv_c0606=1 & thv_c0404=0 ) ) & esize2021 & Qm & Qn & Qd + +{ + Qd = VectorDoubleMultiplyHighHalf(Qn,Qm,esize2021,0:1); + Qd = SatQ(Qd, esize2021,0:1); +} + +:vqdmulh.S^esize2021 Dd, Dn, vmlDmA is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & (c2021=1 | c2021=2)& c0811=0xc & c0606=1 & c0404=0) | + ( $(TMODE_E) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0xc & thv_c0606=1 & thv_c0404=0 ) ) & esize2021 & vmlDmA & Dn & Dd + +{ + Dd = VectorDoubleMultiplyLong(Dn,vmlDmA,esize2021,0:1); + Dd = SatQ(Dd, esize2021,0:1); +} + +:vqdmulh.S^esize2021 Qd, Qn, vmlDmA is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & (c2021=1 | c2021=2) & c0811=0xc & c0606=1 & c0404=0) | + ( $(TMODE_F) & thv_c2327=0x1f & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0xc & thv_c0606=1 & thv_c0404=0 ) ) & esize2021 & vmlDmA & Qn & Qd + +{ + Qd = VectorDoubleMultiplyLong(Qn,vmlDmA,esize2021,0:1); + Qd = SatQ(Qd, esize2021,0:1); +} + +:vqdmull.S^esize2021 Qd, Dn, Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=5 & c2021<3 & c0811=0xD & Q6=0 & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=0xD & thv_Q6=0 & thv_c0404=0 ) ) & esize2021 & Dm & Dn & Qd + +{ + Qd = VectorDoubleMultiplyLong(Dn,Dm,esize2021,0:1); + Qd = SatQ(Qd, esize2021,0:1); +} + +:vqdmull.S^esize2021 Qd, Dn, vmlDmA is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=5 & c2021<3 & c0811=0xb & Q6=1 & c0404=0 ) | + ( $(TMODE_E) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=0xb & thv_Q6=1 & thv_c0404=0 ) ) & esize2021 & vmlDmA & Dn & Qd + +{ + Qd = VectorDoubleMultiplyLong(Dn,vmlDmA,esize2021,0:1); + Qd = SatQ(Qd, esize2021,0:1); +} + +:vqrdmulh.S^esize2021 Dd, Dn, Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2324=2 & (c2021=1 | c2021=2) & c0811=0xb & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1e & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0xb & thv_Q6=0 & thv_c0404=0 ) ) & esize2021 & Dm & Dn & Dd + +{ + Dd = VectorRoundDoubleMultiplyHighHalf(Dn,Dm,esize2021,0:1); + Dd = SatQ(Dd, esize2021,0:1); +} + +:vqrdmulh.S^esize2021 Qd, Qn, Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2324=2 & (c2021=1 | c2021=2) & c0811=0xb & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1e & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0xb & thv_Q6=1 & thv_c0404=0 ) ) & esize2021 & Qm & Qn & Qd + +{ + Qd = VectorRoundDoubleMultiplyHighHalf(Qn,Qm,esize2021,0:1); + Qd = SatQ(Qd, esize2021,0:1); +} + +:vqrdmulh.S^esize2021 Dd, Dn, vmlDmA is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=0 & c2323=1 & (c2021=1 | c2021=2)& c0811=0xd & Q6=1 & c0404=0) | + ( $(TMODE_E) & thv_c2327=0x1f & thv_c2323=1 & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0xd & thv_Q6=1 & thv_c0404=0 ) ) & esize2021 & vmlDmA & Dn & Dd + +{ + Dd = VectorRoundDoubleMultiplyHighHalf(Dn,vmlDmA,esize2021,0:1); + Dd = SatQ(Dd, esize2021,0:1); +} + +:vqrdmulh.S^esize2021 Qd, Qn, vmlDmA is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & (c2021=1 | c2021=2) & c0811=0xd & Q6=1 & c0404=0) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c2323=1 & (thv_c2021=1 | thv_c2021=2) & thv_c0811=0xd & thv_Q6=1 & thv_c0404=0 ) ) & esize2021 & vmlDmA & Qn & Qd + +{ + Qd = VectorRoundDoubleMultiplyHighHalf(Qn,vmlDmA,esize2021,0:1); + Qd = SatQ(Qd, esize2021,0:1); +} + + +:vqsub.^udt^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c0811=2 & Q6=0 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2323=0 & thv_c0811=2 & thv_Q6=0 & thv_c0404=1)) & udt & esize2021 & Dn & Dd & Dm +{ + Dd = VectorSub(Dn,Dm,esize2021,udt); + Dd = SatQ(Dd, esize2021, udt); +} + +:vqsub.^udt^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c0811=2 & Q6=1 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c2323=0 & thv_c0811=2 & thv_Q6=1 & thv_c0404=1) ) & udt & esize2021 & Qm & Qn & Qd +{ + Qd = VectorSub(Qn,Qm,esize2021,udt); + Qd = SatQ(Qd, esize2021, udt); +} + +####### +# VRECPE +define pcodeop VectorReciprocalEstimate; + +:vrecpe.^fdt^32 Qd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x7 & c2021=3 & c1619=0xb & c0911=2 & c0707=0 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1619=0xb & thv_c0911=2 & thv_c0707=0 & thv_Q6=1 & thv_c0404=0) ) & fdt & Qm & Qd +{ + Qd = VectorReciprocalEstimate(Qm,fdt); +} + +:vrecpe.^fdt^32 Dd,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x7 & c2021=3 & c1619=0xb & c0911=2 & c0707=0 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1619=0xb & thv_c0911=2 & thv_c0707=0 & thv_Q6=0 & thv_c0404=0) ) & fdt & Dm & Dd +{ + Dd = VectorReciprocalEstimate(Dm,fdt); +} + +####### +# VRECPS +define pcodeop VectorReciprocalStep; + +:vrecps.f32 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x4 & c2021=0 & c0811=0xf & Q6=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=0xf & thv_Q6=1 & thv_c0404=1) ) & Qn & Qm & Qd +{ + Qd = VectorReciprocalStep(Qn,Qm); +} + +:vrecps.f32 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x4 & c2021=0 & c0811=0xf & Q6=0 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=0 & thv_c0811=0xf & thv_Q6=0 & thv_c0404=1) ) & Dn & Dm & Dd +{ + Dd = VectorReciprocalStep(Dn,Dm); +} + +####### +# VREV +# + +define pcodeop vrev; + +:vrev16.^esize1819x3 Qd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0911=0 & c0708=2 & c0606=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0911=0 & thv_c0708=2 & thv_c0606=1 & thv_c0404=0) ) & Qd & Qm & esize1819x3 +{ + Qd = vrev(Qm,esize1819x3); +} + +:vrev32.^esize1819x3 Qd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0911=0 & c0708=1 & c0606=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0911=0 & thv_c0708=1 & thv_c0606=1 & thv_c0404=0) ) & Qd & Qm & esize1819x3 +{ + Qd = vrev(Qm,esize1819x3); +} + +:vrev64.^esize1819x3 Qd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0911=0 & c0708=0 & c0606=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0911=0 & thv_c0708=0 & thv_c0606=1 & thv_c0404=0) ) & Qd & Qm & esize1819x3 +{ + Qd = vrev(Qm,esize1819x3); +} + +:vrev16.^esize1819x3 Dd,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0911=0 & c0708=2 & c0606=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0911=0 & thv_c0708=2 & thv_c0606=0 & thv_c0404=0) ) & Dd & Dm & esize1819x3 +{ + Dd = vrev(Dm,esize1819x3); +} + +:vrev32.^esize1819x3 Dd,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0911=0 & c0708=1 & c0606=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0911=0 & thv_c0708=1 & thv_c0606=0 & thv_c0404=0) ) & Dd & Dm & esize1819x3 +{ + Dd = vrev(Dm,esize1819x3); +} + +:vrev64.^esize1819x3 Dd,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=0 & c0911=0 & c0708=0 & c0606=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=0 & thv_c0911=0 & thv_c0708=0 & thv_c0606=0 & thv_c0404=0) ) & Dd & Dm & esize1819x3 +{ + Dd = vrev(Dm,esize1819x3); +} + +####### +# VSH +# + +define pcodeop VectorShiftLeft; +define pcodeop VectorRoundShiftLeft; +define pcodeop VectorShiftRight; +define pcodeop VectorShiftLeftInsert; +define pcodeop VectorShiftRightInsert; +define pcodeop VectorShiftRightNarrow; +define pcodeop VectorShiftRightAccumulate; +define pcodeop VectorRoundShiftRight; +define pcodeop VectorRoundShiftRightNarrow; +define pcodeop VectorRoundShiftRightAccumulate; + +ShiftSize: "8" is TMode=0 & c1921=1 & L7=0 { export 8:8; } +ShiftSize: "16" is TMode=0 & c2021=1 & L7=0 { export 16:8; } +ShiftSize: "32" is TMode=0 & c2121=1 & L7=0 { export 32:8; } +ShiftSize: "64" is TMode=0 & L7=1 { export 64:8; } +ShiftSize: "8" is TMode=1 & thv_c1921=1 & thv_L7=0 { export 8:8; } +ShiftSize: "16" is TMode=1 & thv_c2021=1 & thv_L7=0 { export 16:8; } +ShiftSize: "32" is TMode=1 & thv_c2121=1 & thv_L7=0 { export 32:8; } +ShiftSize: "64" is TMode=1 & thv_L7=1 { export 64:8; } + + +ShiftImmRLI: "#"^shift_amt is TMode=0 & c1921=1 & L7=0 & c1621 [ shift_amt = 16 - c1621; ] { export *[const]:8 shift_amt; } +ShiftImmRLI: "#"^shift_amt is TMode=0 & c2021=1 & L7=0 & c1621 [ shift_amt = 32 - c1621; ] { export *[const]:8 shift_amt; } +ShiftImmRLI: "#"^shift_amt is TMode=0 & c2121=1 & L7=0 & c1621 [ shift_amt = 64 - c1621; ] { export *[const]:8 shift_amt; } +ShiftImmRLI: "#"^shift_amt is TMode=0 & L7=1 & c1621 [ shift_amt = 64 - c1621; ] { export *[const]:8 shift_amt; } +ShiftImmRLI: "#"^shift_amt is TMode=1 & thv_c1921=1 & thv_L7=0 & thv_c1621 [ shift_amt = 16 - thv_c1621; ] { export *[const]:8 shift_amt; } +ShiftImmRLI: "#"^shift_amt is TMode=1 & thv_c2021=1 & thv_L7=0 & thv_c1621 [ shift_amt = 32 - thv_c1621; ] { export *[const]:8 shift_amt; } +ShiftImmRLI: "#"^shift_amt is TMode=1 & thv_c2121=1 & thv_L7=0 & thv_c1621 [ shift_amt = 64 - thv_c1621; ] { export *[const]:8 shift_amt; } +ShiftImmRLI: "#"^shift_amt is TMode=1 & thv_L7=1 & thv_c1621 [ shift_amt = 64 - thv_c1621; ] { export *[const]:8 shift_amt; } + +ShiftImmLLI: "#"^shift_amt is TMode=0 & c1921=1 & L7=0 & c1621 [ shift_amt = c1621 - 8; ] { export *[const]:8 shift_amt; } +ShiftImmLLI: "#"^shift_amt is TMode=0 & c2021=1 & L7=0 & c1621 [ shift_amt = c1621 - 16; ] { export *[const]:8 shift_amt; } +ShiftImmLLI: "#"^shift_amt is TMode=0 & c2121=1 & L7=0 & c1621 [ shift_amt = c1621 - 32; ] { export *[const]:8 shift_amt; } +ShiftImmLLI: "#"^shift_amt is TMode=0 & L7=1 & c1621 [ shift_amt = c1621 - 0; ] { export *[const]:8 shift_amt; } +ShiftImmLLI: "#"^shift_amt is TMode=1 & thv_c1921=1 & thv_L7=0 & thv_c1621 [ shift_amt = thv_c1621 - 8; ] { export *[const]:8 shift_amt; } +ShiftImmLLI: "#"^shift_amt is TMode=1 & thv_c2021=1 & thv_L7=0 & thv_c1621 [ shift_amt = thv_c1621 - 16; ] { export *[const]:8 shift_amt; } +ShiftImmLLI: "#"^shift_amt is TMode=1 & thv_c2121=1 & thv_L7=0 & thv_c1621 [ shift_amt = thv_c1621 - 32; ] { export *[const]:8 shift_amt; } +ShiftImmLLI: "#"^shift_amt is TMode=1 & thv_L7=1 & thv_c1621 [ shift_amt = thv_c1621 - 0; ] { export *[const]:8 shift_amt; } + +:vqrshl.^udt^ShiftSize Qd, Qm, ShiftImmLLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c0811=5 & c0606=1 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c0811=5 & thv_c0606=1 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmLLI & Qd & Qm +{ + Qd = VectorRoundShiftLeft(Qm,ShiftImmLLI,ShiftSize,udt); +} + +:vqrshl.^udt^ShiftSize Dd, Dm, ShiftImmLLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c0811=5 & c0606=0 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c0811=5 & thv_c0606=0 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmLLI & Dd & Dm +{ + Dd = VectorRoundShiftLeft(Dm,ShiftImmLLI,ShiftSize,udt); +} + + +:vqshrn.^udt^esize2021 Dd,Qm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & (c1919=1 | c2020=1 | c2121=1) & c0611=0x24 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1f & (thv_c1919=1 | thv_c2020=1 | thv_c2121=1) & thv_c0611=0x24 & thv_c0404=1) ) & udt & esize2021 & ShiftSize & ShiftImmRLI & Dd & Qm +{ + Dd = VectorShiftRightNarrow(Qm,ShiftImmRLI,esize2021,udt); + Dd = SatQ(Dd,esize2021,udt); +} + +:vqshrun.^udt^esize2021 Dd,Qm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & (c1919=1 | c2020=1 | c2121=1) & c0611=0x20 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1f & (thv_c1919=1 | thv_c2020=1 | thv_c2121=1) & thv_c0611=0x20 & thv_c0404=1) ) & udt & esize2021 & ShiftSize & ShiftImmRLI & Dd & Qm +{ + Dd = VectorShiftRightNarrow(Qm,ShiftImmRLI,esize2021,udt); + Dd = SatQ(Dd,esize2021,udt); +} + +:vqrshrn.^udt^esize2021 Dd,Qm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & (c1919=1 | c2020=1 | c2121=1) & c0611=0x25 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1f & (thv_c1919=1 | thv_c2020=1 | thv_c2121=1) & thv_c0611=0x25 & thv_c0404=1) ) & udt & esize2021 & ShiftSize & ShiftImmRLI & Dd & Qm +{ + Dd = VectorRoundShiftRightNarrow(Qm,ShiftImmRLI,esize2021,udt); + Dd = SatQ(Dd,esize2021,udt); +} + +:vqrshrun.^udt^esize2021 Dd,Qm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & (c1919=1 | c2020=1 | c2121=1) & c0611=0x21 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1f & (thv_c1919=1 | thv_c2020=1 | thv_c2121=1) & thv_c0611=0x21 & thv_c0404=1) ) & udt & esize2021 & ShiftImmRLI & Dd & Qm +{ + Dd = VectorRoundShiftRightNarrow(Qm,ShiftImmRLI,esize2021,udt); + Dd = SatQ(Dd,esize2021,udt); +} + + +:vqshl.^udt^ShiftSize Qd, Qm, ShiftImmLLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1621 & c0811=7 & c0606=1 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1621 & thv_c0811=7 & thv_c0606=1 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmLLI & Qd & Qm +{ + Qd = VectorShiftLeft(Qm,ShiftImmLLI,ShiftSize,udt); +} + +:vqshl.^udt^ShiftSize Dd, Dm, ShiftImmLLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1621 & c0811=7 & c0606=0 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c1621 & thv_c0811=7 & thv_c0606=0 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmLLI & Dd & Dm +{ + Dd = VectorShiftLeft(Dm,ShiftImmLLI,ShiftSize,udt); +} + +:vqshlu.^udt^ShiftSize Qd, Qm, ShiftImmLLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1621 & c0811=6 & c0606=1 & c0404=1) | + ($(TMODE_EorF) & thv_c2828=1 & thv_c2327=0x1f & thv_c1621 & thv_c0811=6 & thv_c0606=1 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmLLI & Qd & Qm +{ + Qd = VectorShiftLeft(Qm,ShiftImmLLI,ShiftSize,udt); +} + +:vqshlu.^udt^ShiftSize Dd, Dm, ShiftImmLLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1621 & c0811=6 & c0606=0 & c0404=1) | + ($(TMODE_EorF) & thv_c2828=1 & thv_c2327=0x1f & thv_c1621 & thv_c0811=6 & thv_c0606=0 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmLLI & Dd & Dm +{ + Dd = VectorShiftLeft(Dm,ShiftImmLLI,ShiftSize,udt); +} + + +:vqshl.^udt^esize2021 Qd, Qm, Qn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c0811=4 & c0606=1 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c0811=4 & thv_c0606=1 & thv_c0404=1) ) & udt & esize2021 & Qd & Qm & Qn +{ + Qd = VectorShiftLeft(Qm,Qn,esize2021,udt); +} + +:vqshl.^udt^esize2021 Dd, Dm, Dn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c0811=4 & c0606=0 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c0811=4 & thv_c0606=0 & thv_c0404=1) ) & udt & esize2021 & Dd & Dm & Dn +{ + Dd = VectorShiftLeft(Dm,Dn,esize2021,udt); +} + + +:vshl.I^ShiftSize Qd, Qm, ShiftImmLLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=5 & c0811=5 & c0606=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c0811=5 & thv_c0606=1 & thv_c0404=1) ) & ShiftSize & ShiftImmLLI & Qd & Qm +{ + Qd = VectorShiftLeft(Qm,ShiftImmLLI,ShiftSize,0:1); +} + +:vshl.I^ShiftSize Dd, Dm, ShiftImmLLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=5 & c0811=5 & c0606=0 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c0811=5 & thv_c0606=0 & thv_c0404=1) ) & ShiftSize & ShiftImmLLI & Dd & Dm +{ + Dd = VectorShiftLeft(Dm,ShiftImmLLI,ShiftSize,0:1); +} + + +:vshl.^udt^esize2021 Qd, Qm, Qn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c0811=4 & c0606=1 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c0811=4 & thv_c0606=1 & thv_c0404=0) ) & udt & esize2021 & Qd & Qm & Qn +{ + Qd = VectorShiftLeft(Qm,Qn,esize2021,udt); +} + +:vshl.^udt^esize2021 Dd, Dm, Dn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c0811=4 & c0606=0 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c0811=4 & thv_c0606=0 & thv_c0404=0) ) & udt & esize2021 & Dd & Dm & Dn +{ + Dd = VectorShiftLeft(Dm,Dn,esize2021,udt); +} + +define pcodeop VectorShiftLongLeft; + +:vshll.^udt^ShiftSize Qd, Dm, ShiftImmLLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c0811=10 & c0607=0 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c0811=10 & thv_c0607=0 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmLLI & Qd & Dm +{ + Qd = VectorShiftLongLeft(Dm,ShiftImmLLI); +} + +:vshll.^udt^esize1819 Qd, Dm, "#"^esize1819x3 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=2 & c0811=3 & c0607=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=2 & thv_c0811=3 & thv_c0607=0 & thv_c0404=0) ) & udt & esize1819 & esize1819x3 & Qd & Dm +{ + Qd = VectorShiftLongLeft(Dm,esize1819x3); +} + +:vrshl.^udt^esize2021 Qd, Qm, Qn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c0811=5 & c0606=1 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c0811=5 & thv_c0606=1 & thv_c0404=0) ) & udt & esize2021 & Qd & Qm & Qn +{ + Qd = VectorRoundShiftLeft(Qm,esize2021,Qn); +} + +:vrshl.^udt^esize2021 Dd, Dm, Dn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=0 & c0811=5 & c0606=0 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1e & thv_c0811=5 & thv_c0606=0 & thv_c0404=0) ) & udt & esize2021 & Dd & Dm & Dn +{ + Dd = VectorRoundShiftLeft(Dm,esize2021,Dn); +} + +:vrshr.^udt^ShiftSize Qd, Qm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c0811=2 & c0606=1 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c0811=2 & thv_c0606=1 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmRLI & Qd & Qm +{ + Qd = VectorRoundShiftRight(Qm,ShiftImmRLI); +} + +:vrshr.^udt^ShiftSize Dd, Dm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c0811=2 & c0606=0 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c0811=2 & thv_c0606=0 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmRLI & Dd & Dm +{ + Dd = VectorRoundShiftRight(Dm,ShiftImmRLI); +} + +:vrshrn.^ShiftSize Dd, Qm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=5 & c0811=8 & c0707=0 & c0606=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c0811=8 & thv_c0707=0 & thv_c0606=1 & thv_c0404=1) ) & ShiftSize & ShiftImmRLI & Dd & Qm +{ + Dd = VectorRoundShiftRightNarrow(Qm,ShiftImmRLI); +} + +:vrsra.^udt^ShiftSize Qd, Qm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c0811=3 & c0606=1 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c0811=3 & thv_c0606=1 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmRLI & Qd & Qm +{ + Qd = VectorRoundShiftRightAccumulate(Qd, Qm,ShiftImmRLI); +} + +:vrsra.^udt^ShiftSize Dd, Dm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c0811=3 & c0606=0 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c0811=3 & thv_c0606=0 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmRLI & Dd & Dm +{ + Dd = VectorRoundShiftRightAccumulate(Dd, Dm,ShiftImmRLI); +} + +:vsli.^ShiftSize Dd, Dm, ShiftImmLLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c0811=5 & c0606=0 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c0811=5 & thv_c0606=0 & thv_c0404=1) ) & ShiftSize & ShiftImmLLI & Dd & Dm +{ + Dd = VectorShiftLeftInsert(Dd, Dm,ShiftImmLLI); +} + +:vsli.^ShiftSize Qd, Qm, ShiftImmLLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c0811=5 & c0606=1 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c0811=5 & thv_c0606=1 & thv_c0404=1) ) & ShiftSize & ShiftImmLLI & Qd & Qm +{ + Qd = VectorShiftLeftInsert(Qd, Qm,ShiftImmLLI); +} + +define pcodeop VectorWidenMultipyAccumulate; +:vsmmla.s8 Dd, Dm, Dn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=2 & c0811=0xc & c0606=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=2 & thv_c0811=0xc & thv_c0606=0 & thv_c0404=0) ) & Dd & Dm & Dn +{ + Dd = VectorWidenMultipyAccumulate(Dm,Dn,0:1); +} + +:vsmmla.s8 Qd, Qm, Qn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=2 & c0811=0xc & c0606=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=2 & thv_c0811=0xc & thv_c0606=1 & thv_c0404=0) ) & Qd & Qm & Qn +{ + Qd = VectorWidenMultipyAccumulate(Qm,Qn,0:1); +} + +:vummla.u8 Dd, Dm, Dn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=2 & c0811=0xc & c0606=0 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=2 & thv_c0811=0xc & thv_c0606=0 & thv_c0404=1) ) & Dd & Dm & Dn +{ + Dd = VectorWidenMultipyAccumulate(Dm,Dn,1:1); +} + +:vummla.u8 Qd, Qm, Qn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=2 & c0811=0xc & c0606=1 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=2 & thv_c0811=0xc & thv_c0606=1 & thv_c0404=1) ) & Qd & Qm & Qn +{ + Qd = VectorWidenMultipyAccumulate(Qm,Qn,1:1); +} + +:vusmmla.s8 Dd, Dm, Dn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x19 & c2021=2 & c0811=0xc & c0606=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x19 & thv_c2021=2 & thv_c0811=0xc & thv_c0606=0 & thv_c0404=0) ) & Dd & Dm & Dn +{ + Dd = VectorWidenMultipyAccumulate(Dm,Dn,2:1); +} + +:vusmmla.s8 Qd, Qm, Qn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x19 & c2021=2 & c0811=0xc & c0606=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x19 & thv_c2021=2 & thv_c0811=0xc & thv_c0606=1 & thv_c0404=0) ) & Qd & Qm & Qn +{ + Qd = VectorWidenMultipyAccumulate(Qm,Qn,2:1); +} + +:vsqrt^COND^".f32" Sd,Sm is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=1 & c0811=10 & c0607=3 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=1 & thv_c0811=10 & thv_c0606=1 & thv_c0404=0) ) & Sm & Sd +{ + build COND; + build Sd; + build Sm; + Sd = sqrt(Sm); +} + +:vsqrt^COND^".f64" Dd,Dm is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c1619=1 & c0811=11 & c0606=1 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c1619=1 & thv_c0811=11 & thv_c0606=1 & thv_c0404=0) ) & Dm & Dd +{ + build COND; + build Dd; + build Dm; + Dd = sqrt(Dm); +} + +:vsra.^udt^ShiftSize Qd, Qm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c0811=1 & c0606=1 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c0811=1 & thv_c0606=1 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmRLI & Qd & Qm +{ + Qd = VectorShiftRightAccumulate(Qd, Qm,ShiftImmRLI); +} + +:vsra.^udt^ShiftSize Dd, Dm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c0811=1 & c0606=0 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c0811=1 & thv_c0606=0 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmRLI & Dd & Dm +{ + Dd = VectorShiftRightAccumulate(Dd, Dm,ShiftImmRLI); +} + +:vsri.^ShiftSize Qd, Qm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & c0811=4 & c0606=1 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c0811=4 & thv_c0606=1 & thv_c0404=1) ) & ShiftSize & ShiftImmRLI & Qd & Qm +{ + Qd = VectorShiftRightInsert(Qd, Qm,ShiftImmRLI); +} + +:vsri.^ShiftSize Dd, Dm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2424=1 & c2323=1 & c0811=4 & c0606=0 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c0811=4 & thv_c0606=0 & thv_c0404=1) ) & ShiftSize & ShiftImmRLI & Dd & Dm +{ + Dd = VectorShiftRightInsert(Dd, Dm,ShiftImmRLI); +} + +####### +# VSHR +# + +:vshr.^udt^ShiftSize Qd, Qm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c0811=0 & c0606=1 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c0811=0 & thv_c0606=1 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmRLI & Qd & Qm +{ + Qd = VectorShiftRight(Qm,ShiftImmRLI); +} + +:vshr.^udt^ShiftSize Dd, Dm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c0811=0 & c0606=0 & c0404=1) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c0811=0 & thv_c0606=0 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmRLI & Dd & Dm +{ + Dd = VectorShiftRight(Dm,ShiftImmRLI); +} + +define pcodeop VectorShiftNarrowRight; + +:vshrn.^ShiftSize Dd, Qm, ShiftImmRLI is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=5 & c0811=8 & c0607=0 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c0811=8 & thv_c0607=0 & thv_c0404=1) ) & udt & ShiftSize & ShiftImmRLI & Dd & Qm +{ + Dd = VectorShiftNarrowRight(Qm,ShiftImmRLI); +} + +####### +# VRSQRTE +define pcodeop VectorReciprocalSquareRootEstimate; + +:vrsqrte.^fdt^32 Qd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x7 & c2021=3 & c1619=0xb & c0911=2 & c0707=1 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1619=0xb & thv_c0911=2 & thv_c0707=1 & thv_Q6=1 & thv_c0404=0) ) & fdt & Qm & Qd +{ + Qd = VectorReciprocalSquareRootEstimate(Qm,fdt); +} + +:vrsqrte.^fdt^32 Dd,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x7 & c2021=3 & c1619=0xb & c0911=2 & c0707=1 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1619=0xb & thv_c0911=2 & thv_c0707=1 & thv_Q6=0 & thv_c0404=0) ) & fdt & Dm & Dd +{ + Dd = VectorReciprocalSquareRootEstimate(Dm,fdt); +} + +####### +# VRSQRTS +define pcodeop VectorReciprocalSquareRootStep; + +:vrsqrts.f32 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x4 & c2021=2 & c0811=0xf & Q6=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=2 & thv_c0811=0xf & thv_Q6=1 & thv_c0404=1) ) & Qn & Qm & Qd +{ + Qd = VectorReciprocalSquareRootStep(Qn,Qm); +} + +:vrsqrts.f32 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x4 & c2021=2 & c0811=0xf & Q6=0 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2021=2 & thv_c0811=0xf & thv_Q6=0 & thv_c0404=1) ) & Dn & Dm & Dd +{ + Dd = VectorReciprocalSquareRootStep(Dn,Dm); +} + + +####### +# VST1 (multiple single elements) +# + +buildVst1DdList: Dreg is Dreg & counter=1 [ counter=0; regNum=regNum+1; ] +{ + * mult_addr = Dreg; +} +buildVst1DdList: Dreg,buildVst1DdList is Dreg & buildVst1DdList [ counter=counter-1; regNum=regNum+1; ] +{ + * mult_addr = Dreg; + mult_addr = mult_addr + 8; + build buildVst1DdList; +} + +vst1DdList: "{"^buildVst1DdList^"}" is TMode = 0 & c0811=7 & D22 & c1215 & buildVst1DdList [ regNum=(D22<<4)+c1215-1; counter=1; ] { export 1:4; } +vst1DdList: "{"^buildVst1DdList^"}" is TMode = 0 & c0811=10 & D22 & c1215 & buildVst1DdList [ regNum=(D22<<4)+c1215-1; counter=2; ] { export 2:4; } +vst1DdList: "{"^buildVst1DdList^"}" is TMode = 0 & c0811=6 & D22 & c1215 & buildVst1DdList [ regNum=(D22<<4)+c1215-1; counter=3; ] { export 3:4; } +vst1DdList: "{"^buildVst1DdList^"}" is TMode = 0 & c0811=2 & D22 & c1215 & buildVst1DdList [ regNum=(D22<<4)+c1215-1; counter=4; ] { export 4:4; } +vst1DdList: "{"^buildVst1DdList^"}" is TMode = 1 & thv_c0811=7 & thv_D22 & thv_c1215 & buildVst1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=1; ] { export 1:4; } +vst1DdList: "{"^buildVst1DdList^"}" is TMode = 1 & thv_c0811=10 & thv_D22 & thv_c1215 & buildVst1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=2; ] { export 2:4; } +vst1DdList: "{"^buildVst1DdList^"}" is TMode = 1 & thv_c0811=6 & thv_D22 & thv_c1215 & buildVst1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=3; ] { export 3:4; } +vst1DdList: "{"^buildVst1DdList^"}" is TMode = 1 & thv_c0811=2 & thv_D22 & thv_c1215 & buildVst1DdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=4; ] { export 4:4; } + +@define Vst1DdList "(c0811=2 | c0811=6 | c0811=7 | c0811=10)" +@define T_Vst1DdList "(thv_c0811=2 | thv_c0811=6 | thv_c0811=7 | thv_c0811=10)" + +:vst1.^esize0607 vst1DdList,RnAligned45 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0003=15 & $(Vst1DdList)) | + ($(TMODE_F) &thv_c2327=18 & thv_c2021=0 & thv_c0003=15 & $(T_Vst1DdList)) ) & RnAligned45 & esize0607 & vst1DdList +{ + mult_addr = RnAligned45; + build vst1DdList; +} + +:vst1.^esize0607 vst1DdList,RnAligned45^"!" is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0003=13 & $(Vst1DdList)) | + ($(TMODE_F) &thv_c2327=18 & thv_c2021=0 & thv_c0003=13 & $(T_Vst1DdList)) ) & RnAligned45 & esize0607 & vst1DdList +{ + mult_addr = RnAligned45; + build vst1DdList; + RnAligned45 = RnAligned45 + (8 * vst1DdList); +} + +:vst1.^esize0607 vst1DdList,RnAligned45,VRm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & $(Vst1DdList)) | + ($(TMODE_F) &thv_c2327=18 & thv_c2021=0 & $(T_Vst1DdList)) ) & RnAligned45 & esize0607 & VRm & vst1DdList +{ + mult_addr = RnAligned45; + build vst1DdList; + RnAligned45 = RnAligned45 + VRm; +} + +####### +# VST1 (single element to one lane) +# + +vst1Index: val is c0507 & c1011 [ val = c0507 >> c1011; ] { tmp:4 = val; export tmp; } + +vst1DdElement2: Dd^"["^vst1Index^"]" is Dd & vst1Index & c1011=0 +{ + ptr:4 = &Dd + vst1Index; + *:1 mult_addr = *[register]:1 ptr; +} +vst1DdElement2: Dd^"["^vst1Index^"]" is Dd & vst1Index & c1011=1 +{ + ptr:4 = &Dd + (2 * vst1Index); + *:2 mult_addr = *[register]:2 ptr; +} +vst1DdElement2: Dd^"["^vst1Index^"]" is Dd & vst1Index & c1011=2 +{ + ptr:4 = &Dd + (4 * vst1Index); + *:4 mult_addr = *[register]:4 ptr; +} + +@define Vst1DdElement2 "((c1011=0 & c0404=0) | (c1011=1 & c0505=0) | (c1011=2 & (c0406=0 | c0406=3))) & vst1DdElement2" + +:vst1.^esize1011 vst1DdElement2,RnAligned2 is $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & RnAligned2 & esize1011 & c0809=0 & c0003=15 & $(Vst1DdElement2) +{ + mult_addr = RnAligned2; + build vst1DdElement2; +} + +:vst1.^esize1011 vst1DdElement2,RnAligned2^"!" is $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & RnAligned2 & esize1011 & c0809=0 & c0003=13 & $(Vst1DdElement2) +{ + mult_addr = RnAligned2; + build vst1DdElement2; + RnAligned2 = RnAligned2 + esize1011; +} + +:vst1.^esize1011 vst1DdElement2,RnAligned2,VRm is $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & RnAligned2 & esize1011 & c0809=0 & VRm & $(Vst1DdElement2) +{ + mult_addr = RnAligned2; + build vst1DdElement2; + RnAligned2 = RnAligned2 + VRm; +} + +thv_vst1Index: val is thv_c0507 & thv_c1011 [ val = thv_c0507 >> thv_c1011; ] { tmp:4 = val; export tmp; } + +thv_vst1DdElement2: Dd^"["^thv_vst1Index^"]" is Dd & thv_vst1Index & thv_c1011=0 +{ + ptr:4 = &Dd + thv_vst1Index; + *:1 mult_addr = *[register]:1 ptr; +} +thv_vst1DdElement2: Dd^"["^thv_vst1Index^"]" is Dd & thv_vst1Index & thv_c1011=1 +{ + ptr:4 = &Dd + (2 * thv_vst1Index); + *:2 mult_addr = *[register]:2 ptr; +} +thv_vst1DdElement2: Dd^"["^thv_vst1Index^"]" is Dd & thv_vst1Index & thv_c1011=2 +{ + ptr:4 = &Dd + (4 * thv_vst1Index); + *:4 mult_addr = *[register]:4 ptr; +} + +@define T_Vst1DdElement2 "((thv_c1011=0 & thv_c0404=0) | (thv_c1011=1 & thv_c0505=0) | (thv_c1011=2 & (thv_c0406=0 | thv_c0406=3))) & thv_vst1DdElement2" + +:vst1.^esize1011 thv_vst1DdElement2,RnAligned2 is $(TMODE_F) &thv_c2327=19 & thv_c2021=0 & RnAligned2 & esize1011 & thv_c0809=0 & thv_c0003=15 & $(T_Vst1DdElement2) +{ + mult_addr = RnAligned2; + build thv_vst1DdElement2; +} + +:vst1.^esize1011 thv_vst1DdElement2,RnAligned2^"!" is $(TMODE_F) &thv_c2327=19 & thv_c2021=0 & RnAligned2 & esize1011 & thv_c0809=0 & thv_c0003=13 & $(T_Vst1DdElement2) +{ + mult_addr = RnAligned2; + build thv_vst1DdElement2; + RnAligned2 = RnAligned2 + esize1011; +} + +:vst1.^esize1011 thv_vst1DdElement2,RnAligned2,VRm is $(TMODE_F) &thv_c2327=19 & thv_c2021=0 & RnAligned2 & esize1011 & thv_c0809=0 & VRm & $(T_Vst1DdElement2) +{ + mult_addr = RnAligned2; + build thv_vst1DdElement2; + RnAligned2 = RnAligned2 + VRm; +} + + +####### +# VST2 +# + +####### +# VST2 (multiple 2-element structures) +# + +vst2Dd: Dreg is Dreg & ((TMode=0 & c0607=0) | (TMode=1 & thv_c0607=0)) & regInc +{ + ptr1:4 = &Dreg; +@if ENDIAN == "little" + ptr2:4 = &Dreg + (regInc * 8); +@else # ENDIAN == "big" + ptr2:4 = &Dreg - (regInc * 8); +@endif # ENDIAN = "big" + mult_dat8 = 8; + + *:1 mult_addr = *[register]:1 ptr1; + mult_addr = mult_addr + 1; + *:1 mult_addr = *[register]:1 ptr2; + mult_addr = mult_addr + 1; + mult_dat8 = mult_dat8 - 1; + if(mult_dat8 == 0) goto ; + ptr1 = ptr1 + 1; + ptr2 = ptr2 + 1; + goto ; + +} +vst2Dd: Dreg is Dreg & ((TMode=0 & c0607=1) | (TMode=1 & thv_c0607=1)) & regInc +{ + ptr1:4 = &Dreg; +@if ENDIAN == "little" + ptr2:4 = &Dreg + (regInc * 8); +@else # ENDIAN == "big" + ptr2:4 = &Dreg - (regInc * 8); +@endif # ENDIAN = "big" + mult_dat8 = 4; + + *:2 mult_addr = *[register]:2 ptr1; + mult_addr = mult_addr + 2; + *:2 mult_addr = *[register]:2 ptr2; + mult_addr = mult_addr + 2; + mult_dat8 = mult_dat8 - 1; + if(mult_dat8 == 0) goto ; + ptr1 = ptr1 + 2; + ptr2 = ptr2 + 2; + goto ; + +} +vst2Dd: Dreg is Dreg & ((TMode=0 & c0607=2) | (TMode=1 & thv_c0607=2)) & regInc +{ + ptr1:4 = &Dreg; +@if ENDIAN == "little" + ptr2:4 = &Dreg + (regInc * 8); +@else # ENDIAN == "big" + ptr2:4 = &Dreg - (regInc * 8); +@endif # ENDIAN = "big" + mult_dat8 = 2; + + *:4 mult_addr = *[register]:4 ptr1; + mult_addr = mult_addr + 4; + *:4 mult_addr = *[register]:4 ptr2; + mult_addr = mult_addr + 4; + mult_dat8 = mult_dat8 - 1; + if(mult_dat8 == 0) goto ; + ptr1 = ptr1 + 4; + ptr2 = ptr2 + 4; + goto ; + +} + +buildVst2DdListA: is counter=0 { } +buildVst2DdListA: vst2Dd,buildVst2DdListA is vst2Dd & buildVst2DdListA & esize0607 [ counter=counter-1; regNum=regNum+1; ] +{ + build vst2Dd; + build buildVst2DdListA; +} + +buildVst2DdListB: is counter2=0 { } +buildVst2DdListB: Dreg2 is Dreg2 & counter2=1 & esize0607 [ counter2=0; reg2Num=reg2Num+1; ] { } +buildVst2DdListB: Dreg2,buildVst2DdListB is Dreg2 & buildVst2DdListB & esize0607 [ counter2=counter2-1; reg2Num=reg2Num+1; ] { } + +vst2DdList: "{"^buildVst2DdListA^buildVst2DdListB^"}" is TMode=0 & c0811=8 & D22 & c1215 & buildVst2DdListA & buildVst2DdListB [ regNum=(D22<<4)+c1215-1; regInc=1; reg2Num=regNum+1; counter=1; counter2=1; ] { build buildVst2DdListA; build buildVst2DdListB; export 2:4; } +vst2DdList: "{"^buildVst2DdListA^buildVst2DdListB^"}" is TMode=0 & c0811=9 & D22 & c1215 & buildVst2DdListA & buildVst2DdListB [ regNum=(D22<<4)+c1215-1; regInc=2; reg2Num=regNum+2; counter=1; counter2=1; ] { build buildVst2DdListA; build buildVst2DdListB; export 2:4; } +vst2DdList: "{"^buildVst2DdListA^buildVst2DdListB^"}" is TMode=0 & c0811=3 & D22 & c1215 & buildVst2DdListA & buildVst2DdListB [ regNum=(D22<<4)+c1215-1; regInc=2; reg2Num=regNum+2; counter=2; counter2=2; ] { build buildVst2DdListA; build buildVst2DdListB; export 4:4; } +vst2DdList: "{"^buildVst2DdListA^buildVst2DdListB^"}" is TMode=1 & thv_c0811=8 & thv_D22 & thv_c1215 & buildVst2DdListA & buildVst2DdListB [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; reg2Num=regNum+1; counter=1; counter2=1; ] { build buildVst2DdListA; build buildVst2DdListB; export 2:4; } +vst2DdList: "{"^buildVst2DdListA^buildVst2DdListB^"}" is TMode=1 & thv_c0811=9 & thv_D22 & thv_c1215 & buildVst2DdListA & buildVst2DdListB [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=2; reg2Num=regNum+2; counter=1; counter2=1; ] { build buildVst2DdListA; build buildVst2DdListB; export 2:4; } +vst2DdList: "{"^buildVst2DdListA^buildVst2DdListB^"}" is TMode=1 & thv_c0811=3 & thv_D22 & thv_c1215 & buildVst2DdListA & buildVst2DdListB [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=2; reg2Num=regNum+2; counter=2; counter2=2; ] { build buildVst2DdListA; build buildVst2DdListB; export 4:4; } + + +@define Vst2DdList "(c0811=3 | c0811=8 | c0811=9)" +@define T_Vst2DdList "(thv_c0811=3 | thv_c0811=8 | thv_c0811=9)" + +:vst2.^esize0607 vst2DdList,RnAligned45 is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0607<3 & c0003=15 & $(Vst2DdList) ) | + ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 & thv_c0607<3 & thv_c0003=15 & $(T_Vst2DdList) ) ) & RnAligned45 & esize0607 & vst2DdList +{ + mult_addr = RnAligned45; + build vst2DdList; +} + +:vst2.^esize0607 vst2DdList,RnAligned45^"!" is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0607<3 & c0003=13 & $(Vst2DdList) ) | + ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 & thv_c0607<3 & thv_c0003=13 & $(T_Vst2DdList) ) ) & RnAligned45 & esize0607 & vst2DdList +{ + mult_addr = RnAligned45; + build vst2DdList; + RnAligned45 = RnAligned45 + (8 * vst2DdList); +} + +:vst2.^esize0607 vst2DdList,RnAligned45,VRm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0607<3 & $(Vst2DdList) ) | + ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 & thv_c0607<3 & $(T_Vst2DdList) ) ) & RnAligned45 & VRm & esize0607 & vst2DdList +{ + mult_addr = RnAligned45; + build vst2DdList; + RnAligned45 = RnAligned45 + VRm; +} + +####### +# VST2 (single 2-element structure to one lane) +# + +vst2DdElement2: Dreg^"["^vld2Index^"]" is Dreg & vld2Index +{ +} + +vst2Align2: is TMode=0 & c0404=0 & (c1111=0 | c0505=0) { } +vst2Align2: "@16" is TMode=0 & c1011=0 & c0404=1 { } +vst2Align2: "@32" is TMode=0 & c1011=1 & c0404=1 { } +vst2Align2: "@64" is TMode=0 & c1011=2 & c0405=1 { } +vst2Align2: is TMode=1 & thv_c0404=0 & (thv_c1111=0 | thv_c0505=0) { } +vst2Align2: "@16" is TMode=1 & thv_c1011=0 & thv_c0404=1 { } +vst2Align2: "@32" is TMode=1 & thv_c1011=1 & thv_c0404=1 { } +vst2Align2: "@64" is TMode=1 & thv_c1011=2 & thv_c0405=1 { } + +vst2RnAligned2: "["^VRn^vst2Align2^"]" is VRn & vst2Align2 { export VRn; } + +buildVst2DdList2: is counter=0 { } +buildVst2DdList2: vst2DdElement2 is counter=1 & vst2DdElement2 [ counter=0; regNum=regNum+regInc; ] { } +buildVst2DdList2: vst2DdElement2,buildVst2DdList2 is vst2DdElement2 & buildVst2DdList2 [ counter=counter-1; regNum=regNum+regInc; ] { } + +vst2DdList2: "{"^buildVst2DdList2^"}" is TMode=0 & D22 & c1215 & buildVst2DdList2 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=2; ] { } # Single +vst2DdList2: "{"^buildVst2DdList2^"}" is TMode=0 & ((c1011=1 & c0505=1) | (c1011=2 & c0606=1)) & D22 & c1215 & buildVst2DdList2 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=2; ] { } # Double +vst2DdList2: "{"^buildVst2DdList2^"}" is TMode=1 & thv_D22 & thv_c1215 & buildVst2DdList2 [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=2; ] { } # Single +vst2DdList2: "{"^buildVst2DdList2^"}" is TMode=1 & ((thv_c1011=1 & thv_c0505=1) | (thv_c1011=2 & thv_c0606=1)) & thv_D22 & thv_c1215 & buildVst2DdList2 [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=2; ] { } # Double + +:vst2.^esize1011 vst2DdList2,vst2RnAligned2 is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c1011<3 & c0809=1 & c0003=15 ) | + ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=0 & thv_c1011<3 & thv_c0809=1 & thv_c0003=15 ) ) & vst2RnAligned2 & esize1011 & vst2DdList2 + unimpl + +:vst2.^esize1011 vst2DdList2,vst2RnAligned2^"!" is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c1011<3 & c0809=1 & c0003=13 ) | + ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=0 & thv_c1011<3 & thv_c0809=1 & thv_c0003=13 ) ) & vst2RnAligned2 & esize1011 & vst2DdList2 + unimpl + +:vst2.^esize1011 vst2DdList2,vst2RnAligned2,VRm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c1011<3 & c0809=1 ) | + ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=0 & thv_c1011<3 & thv_c0809=1 ) ) & vst2RnAligned2 & esize1011 & vst2DdList2 & VRm + unimpl + + +####### +# VST3 +# + +####### +# VST3 (multiple 3-element structures) +# + + +vst3Align: is TMode=0 & c0404=0 { } +vst3Align: "@64" is TMode=0 & c0404=1 { } +vst3Align: is TMode=1 & thv_c0404=0 { } +vst3Align: "@64" is TMode=1 & thv_c0404=1 { } + + +vst3RnAligned: "["^VRn^vst3Align^"]" is VRn & vst3Align { export VRn; } + +buildvst3DdList: is counter=0 { } +buildvst3DdList: Dreg is counter=1 & Dreg [ counter=0; regNum=regNum+regInc; ] { } +buildvst3DdList: Dreg,buildvst3DdList is Dreg & buildvst3DdList [ counter=counter-1; regNum=regNum+regInc; ] { } + +vst3DdList: "{"^buildvst3DdList^"}" is TMode=0 & c0811=4 & D22 & c1215 & buildvst3DdList [ regNum=(D22<<4)+c1215-1; regInc=1; counter=3; ] { } # Single +vst3DdList: "{"^buildvst3DdList^"}" is TMode=0 & c0811=5 & D22 & c1215 & buildvst3DdList [ regNum=(D22<<4)+c1215-2; regInc=2; counter=3; ] { } # Double +vst3DdList: "{"^buildvst3DdList^"}" is TMode=1 & thv_c0811=4 & thv_D22 & thv_c1215 & buildvst3DdList [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=3; ] { } # Single +vst3DdList: "{"^buildvst3DdList^"}" is TMode=1 & thv_c0811=5 & thv_D22 & thv_c1215 & buildvst3DdList [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=3; ] { } # Double + + +:vst3.^esize0607 vst3DdList,vst3RnAligned is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0003=15 ) | + ( $(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 & thv_c0003=15 ) ) & vst3RnAligned & esize0607 & vst3DdList + unimpl + +:vst3.^esize0607 vst3DdList,vst3RnAligned^"!" is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0003=13 ) | + ( $(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 & thv_c0003=13 ) ) & vst3RnAligned & esize0607 & vst3DdList + unimpl + +:vst3.^esize0607 vst3DdList,vst3RnAligned,VRm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0) | + ( $(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 ) ) & vst3RnAligned & esize0607 & vst3DdList & VRm + unimpl + + +####### +# VST3 (single 3-element structure to one lane) +# + +vst3Rn: "["^VRn^"]" is VRn { export VRn; } + +vst3DdList2: "{"^buildvst3DdList^"}" is TMode=0 & D22 & c1215 & buildvst3DdList [ regNum=(D22<<4)+c1215-1; regInc=1; counter=2; ] { } # Single +vst3DdList2: "{"^buildvst3DdList^"}" is TMode=0 & ((c1011=1 & c0505=1) | (c1011=2 & c0606=1)) & D22 & c1215 & buildvst3DdList [ regNum=(D22<<4)+c1215-2; regInc=2; counter=2; ] { } # Double +vst3DdList2: "{"^buildvst3DdList^"}" is TMode=1 & thv_D22 & thv_c1215 & buildvst3DdList [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=2; ] { } # Single +vst3DdList2: "{"^buildvst3DdList^"}" is TMode=1 & ((thv_c1011=1 & thv_c0505=1) | (thv_c1011=2 & thv_c0606=1)) & thv_D22 & thv_c1215 & buildvst3DdList [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=2; ] { } # Double + +:vst3.^esize1011 vst3DdList2,vst3Rn is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c1011<3 & c0809=2 & c0003=15 ) | + ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=0 & thv_c1011<3 & thv_c0809=2 & thv_c0003=15 ) ) & vst3Rn & esize1011 & vst3DdList2 + unimpl + +:vst3.^esize1011 vst3DdList2,vst3Rn^"!" is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c1011<3 & c0809=2 & c0003=13 ) | + ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=0 & thv_c1011<3 & thv_c0809=2 & thv_c0003=13 ) ) & vst3Rn & esize1011 & vst3DdList2 + unimpl + +:vst3.^esize1011 vst3DdList2,vst3Rn,VRm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c1011<3 & c0809=2 ) | + ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=0 & thv_c1011<3 & thv_c0809=2 ) ) & vst3Rn & esize1011 & vst3DdList2 & VRm + unimpl + +####### +# VST4 (multiple 4-element structures) +# + +vst4Align: is TMode=0 & c0405=0 { } +vst4Align: "@64" is TMode=0 & c0405=1 { } +vst4Align: "@128" is TMode=0 & c0405=2 { } +vst4Align: "@256" is TMode=0 & c0405=3 { } +vst4Align: is TMode=1 & thv_c0405=0 { } +vst4Align: "@64" is TMode=1 & thv_c0405=1 { } +vst4Align: "@128" is TMode=1 & thv_c0405=2 { } +vst4Align: "@256" is TMode=1 & thv_c0405=3 { } + +vst4RnAligned: "["^VRn^vst4Align^"]" is VRn & vst4Align { export VRn; } + +buildVst4DdList: is counter=0 { } +buildVst4DdList: Dreg is counter=1 & Dreg [ counter=0; regNum=regNum+regInc; ] { } +buildVst4DdList: Dreg,buildVst4DdList is Dreg & buildVst4DdList [ counter=counter-1; regNum=regNum+regInc; ] { } + +vst4DdList: "{"^buildVst4DdList^"}" is TMode=0 & c0808=0 & D22 & c1215 & buildVst4DdList [ regNum=(D22<<4)+c1215-1; regInc=1; counter=4; ] { } # Single +vst4DdList: "{"^buildVst4DdList^"}" is TMode=0 & c0808=1 & D22 & c1215 & buildVst4DdList [ regNum=(D22<<4)+c1215-2; regInc=2; counter=4; ] { } # Double +vst4DdList: "{"^buildVst4DdList^"}" is TMode=1 & thv_c0808=0 & thv_D22 & thv_c1215 & buildVst4DdList [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=4; ] { } # Single +vst4DdList: "{"^buildVst4DdList^"}" is TMode=1 & thv_c0808=1 & thv_D22 & thv_c1215 & buildVst4DdList [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=4; ] { } # Double + +:vst4.^esize0607 vst4DdList,vst4RnAligned is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0911=0 & c0607<3 & c0003=15) | + ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 & thv_c0911=0 & thv_c0607<3 & thv_c0003=15) ) & vst4RnAligned & esize0607 & vst4DdList unimpl + +:vst4.^esize0607 vst4DdList,vst4RnAligned^"!" is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0911=0 & c0607<3 & c0003=13) | + ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 & thv_c0911=0 & thv_c0607<3 & thv_c0003=13) ) & vst4RnAligned & esize0607 & vst4DdList unimpl + +:vst4.^esize0607 vst4DdList,vst4RnAligned,VRm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0911=0 & c0607<3) | + ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 & thv_c0911=0 & thv_c0607<3) ) & VRm & vst4RnAligned & esize0607 & vst4DdList unimpl + +####### +# VST4 (single 4-element structure from one lane) +# + +vst4Index: val is TMode=0 & c0507 & c1011 [ val = c0507 >> c1011; ] { tmp:4 = val; export tmp; } +vst4Index: val is TMode=1 & thv_c0507 & thv_c1011 [ val = thv_c0507 >> thv_c1011; ] { tmp:4 = val; export tmp; } + + +vst4DdElement2: Dreg^"["^vst4Index^"]" is Dreg & vst4Index +{ +} + +vst4Align2: is TMode=0 & c0404=0 & (c1111=0 | c0505=0) { } +vst4Align2: "@32" is TMode=0 & c1011=0 & c0404=1 { } +vst4Align2: "@64" is TMode=0 & ((c1011=1 & c0404=1) | (c1011=2 & c0405=1)) { } +vst4Align2: "@128" is TMode=0 & c1011=2 & c0405=2 { } +vst4Align2: is TMode=1 & thv_c0404=0 & (thv_c1111=0 | thv_c0505=0) { } +vst4Align2: "@32" is TMode=1 & thv_c1011=0 & thv_c0404=1 { } +vst4Align2: "@64" is TMode=1 & ((thv_c1011=1 & thv_c0404=1) | (thv_c1011=2 & thv_c0405=1)) { } +vst4Align2: "@128" is TMode=1 & thv_c1011=2 & thv_c0405=2 { } + +vst4RnAligned2: "["^VRn^vst4Align2^"]" is VRn & vst4Align2 { export VRn; } + +buildVst4DdList2: is counter=0 { } +buildVst4DdList2: vst4DdElement2 is counter=1 & vst4DdElement2 [ counter=0; regNum=regNum+regInc; ] { } +buildVst4DdList2: vst4DdElement2,buildVst4DdList2 is vst4DdElement2 & buildVst4DdList2 [ counter=counter-1; regNum=regNum+regInc; ] { } + +vst4DdList2: "{"^buildVst4DdList2^"}" is TMode=0 & D22 & c1215 & buildVst4DdList2 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=4; ] { } # Single +vst4DdList2: "{"^buildVst4DdList2^"}" is TMode=0 & ((c1011=1 & c0505=1) | (c1011=2 & c0606=1)) & D22 & c1215 & buildVst4DdList2 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=4; ] { } # Double +vst4DdList2: "{"^buildVst4DdList2^"}" is TMode=1 & thv_D22 & thv_c1215 & buildVst4DdList2 [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=4; ] { } # Single +vst4DdList2: "{"^buildVst4DdList2^"}" is TMode=1 & ((thv_c1011=1 & thv_c0505=1) | (thv_c1011=2 & thv_c0606=1)) & thv_D22 & thv_c1215 & buildVst4DdList2 [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=4; ] { } # Double + +:vst4.^esize1011 vst4DdList2,vst4RnAligned2 is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c1011<3 & c0809=3 & c0003=15) | + ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=0 & thv_c1011<3 & thv_c0809=3 & thv_c0003=15) ) & vst4RnAligned2 & esize1011 & vst4DdList2 unimpl + +:vst4.^esize1011 vst4DdList2,vst4RnAligned2^"!" is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c1011<3 & c0809=3 & c0003=13) | + ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=0 & thv_c1011<3 & thv_c0809=3 & thv_c0003=13) ) & vst4RnAligned2 & esize1011 & vst4DdList2 unimpl + +:vst4.^esize1011 vst4DdList2,vst4RnAligned2,VRm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c1011<3 & c0809=3) | + ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=0 & thv_c1011<3 & thv_c0809=3) ) & VRm & vst4RnAligned2 & esize1011 & vst4DdList2 unimpl + +@endif # SIMD + +@if defined(VFPv2) || defined(VFPv3) || defined(SIMD) + +####### +# VSTM (A1) +# + +buildVstmDdList: is counter=0 { } +buildVstmDdList: Dreg is counter=1 & Dreg [ counter=0; regNum=regNum+1; ] +{ + *mult_addr = Dreg; + mult_addr = mult_addr + 8; +} +buildVstmDdList: Dreg,buildVstmDdList is Dreg & buildVstmDdList [ counter=counter-1; regNum=regNum+1; ] +{ + *mult_addr = Dreg; + mult_addr = mult_addr + 8; + build buildVstmDdList; +} + +vstmDdList: "{"^buildVstmDdList^"}" is TMode=0 & D22 & c1215 & c0007 & buildVstmDdList [ regNum=(D22<<4)+c1215-1; counter=c0007>>1; ] { } +vstmDdList: "{"^buildVstmDdList^"}" is TMode=1 & thv_D22 & thv_c1215 & thv_c0007 & buildVstmDdList [ regNum=(thv_D22<<4)+thv_c1215-1; counter=thv_c0007>>1; ] { } + +:vstmia^COND vldmRn,vstmDdList is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x19 & c2121 & c2020=0 & c0811=11 & c0000=0) | + ($(TMODE_E) & thv_c2327=0x19 & thv_c2121 & thv_c2020=0 & thv_c0811=11 & thv_c0000=0) ) & vldmRn & vstmDdList & vldmOffset & vldmUpdate +{ + mult_addr = vldmRn; + build vstmDdList; + build vldmUpdate; +} + +:vstmdb^COND vldmRn,vstmDdList is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1a & c2121=1 & c2020=0 & c0811=11 & c0000=0) | + ($(TMODE_E) & thv_c2327=0x1a & thv_c2121=1 & thv_c2020=0 & thv_c0811=11 & thv_c0000=0) ) & vldmRn & vstmDdList & vldmOffset +{ + local start_addr = vldmRn - vldmOffset; + mult_addr = start_addr; + build vstmDdList; + vldmRn = start_addr; +} + +@endif # VFPv2 | VFPv3 | SIMD + +@if defined(VFPv2) || defined(VFPv3) + +####### +# VSTM (A2) +# + +buildVstmSdList: is counter=0 { } +buildVstmSdList: Sreg is counter=1 & Sreg [ counter=0; regNum=regNum+1; ] +{ + *mult_addr = Sreg; + mult_addr = mult_addr + 4; +} +buildVstmSdList: Sreg,buildVstmSdList is Sreg & buildVstmSdList [ counter=counter-1; regNum=regNum+1; ] +{ + *mult_addr = Sreg; + mult_addr = mult_addr + 4; + build buildVstmSdList; +} + +vstmSdList: "{"^buildVstmSdList^"}" is TMode=0 & D22 & c1215 & c0007 & buildVstmSdList [ regNum=(c1215<<1) + D22 -1; counter=c0007; ] { } +vstmSdList: "{"^buildVstmSdList^"}" is TMode=1 & thv_D22 & thv_c1215 & thv_c0007 & buildVstmSdList [ regNum=(thv_c1215<<1) + thv_D22 -1; counter=thv_c0007; ] { } + +:vstmia^COND vldmRn,vstmSdList is COND & ( ( $(AMODE) & ARMcond=1 & c2327=0x19 & c2121 & c2020=0 & c0811=10 ) | + ($(TMODE_E) & thv_c2327=0x19 & thv_c2121 & thv_c2020=0 & thv_c0811=10 ) ) & vldmRn & vstmSdList & vldmOffset & vldmUpdate +{ + mult_addr = vldmRn; + build vstmSdList; + build vldmUpdate; +} + +:vstmdb^COND vldmRn,vstmSdList is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1a & c2121=1 & c2020=0 & c0811=10 ) | + ($(TMODE_E) & thv_c2327=0x1a & thv_c2121=1 & thv_c2020=0 & thv_c0811=10) ) & vldmRn & vstmSdList & vldmOffset +{ + local start_addr = vldmRn - vldmOffset; + mult_addr = start_addr; + build vstmSdList; + vldmRn = start_addr; +} + + +####### +# VSTR +# + +:vstr^COND^".64" Dd,vldrRn is COND & ( ($(AMODE) & ARMcond=1 & c2427=13 & c2021=0 & c0811=11) | ($(TMODE_E) & thv_c2427=13 & thv_c2021=0 & thv_c0811=11)) & Dd & vldrRn +{ + *vldrRn = Dd; +} + +:vstr^COND^".32" Sd,vldrRn is COND & ( ($(AMODE) & ARMcond=1 & c2427=13 & c2021=0 & c0811=10) | ($(TMODE_E) & thv_c2427=13 & thv_c2021=0 & thv_c0811=10)) & Sd & vldrRn +{ + *vldrRn = Sd; +} + +@endif # VFPv2 || VFPv3 || SIMD + + +####### +# VSUB +# + +@if defined(SIMD) + +define pcodeop FloatVectorSub; +define pcodeop VectorSubAndNarrow; + +:vsub.i^esize2021 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c0811=8 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1e & thv_c0811=8 & thv_Q6=0 & thv_c0404=0)) & esize2021 & Dn & Dd & Dm +{ + Dd = VectorSub(Dn,Dm,esize2021); +} + +:vsub.i^esize2021 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=6 & c0811=8 & Q6=1 & c0404=0) | + ($(TMODE_F) &thv_c2327=0x1e & thv_c0811=8 & thv_Q6=1 & thv_c0404=0) ) & esize2021 & Qm & Qn & Qd +{ + Qd = VectorSub(Qn,Qm,esize2021); +} + +:vsub.f32 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2121=1 & c0811=13 & Q6=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2121=1 & thv_c0811=13 & thv_Q6=0 & thv_c0404=0) ) & Dm & Dn & Dd +{ + Dd = FloatVectorSub(Dn,Dm,2:1,32:1); +} + +:vsub.f32 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c2121=1 & c0811=13 & Q6=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c2121=1 & thv_c0811=13 & thv_Q6=1 & thv_c0404=0) ) & Qn & Qd & Qm +{ + Qd = FloatVectorSub(Qn,Qm,2:1,32:1); +} + +:vsubhn.i^esize2021x2 Dd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=5 & c0811=6 & Q6=0 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1f & thv_c0811=6 & thv_Q6=0 & thv_c0404=0)) & esize2021x2 & Dd & Qn & Qm +{ + Dd = VectorSubAndNarrow(Qn,Qm,esize2021x2); +} + +:vsubl.^udt^esize2021 Qd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=2 & c0606=0 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=2 & thv_c0606=0 & thv_c0404=0) ) & esize2021 & udt & Dn & Qd & Dm +{ + Qd = VectorSub(Dn,Dm,esize2021,udt); +} + +:vsubw.^udt^esize2021 Qd,Qn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=3 & c0606=0 & c0404=0) | + ($(TMODE_EorF) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=3 & thv_c0606=0 & thv_c0404=0) ) & esize2021 & udt & Qn & Qd & Dm +{ + Qd = VectorSub(Qn,Dm,esize2021,udt); +} + +@endif # SIMD + +@if defined(VFPv2) || defined(VFPv3) + +:vsub^COND^".f32" Sd,Sn,Sm is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=3 & c0811=10 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=3 & thv_c0811=10 & thv_c0606=1 & thv_c0404=0) ) & Sm & Sn & Sd +{ + build COND; + build Sd; + build Sm; + build Sn; + Sd = Sn f- Sm; +} + +:vsub^COND^".f64" Dd,Dn,Dm is COND & ( ($(AMODE) & ARMcond=1 & c2327=0x1c & c2021=3 & c0811=11 & c0606=1 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=3 & thv_c0811=11 & thv_c0606=1 & thv_c0404=0) ) & Dm & Dn & Dd +{ + build COND; + build Dd; + build Dm; + build Dn; + Dd = Dn f- Dm; +} + +@endif # VFPv2 || VFPv3 + +@if defined(SIMD) + + +####### +# VSWP +# + +:vswp Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0711=0 & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0711=0 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm +{ + tmp:8 = Dm; + Dm = Dd; + Dd = tmp; +} + +:vswp Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0711=0 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0711=0 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm +{ + tmp:16 = Qm; + Qm = Qd; + Qd = tmp; +} + + +########### +# VTBL/VTBX +# + +define pcodeop VectorTableLookup; + +buildVtblDdList: is counter=0 { } +buildVtblDdList: Dreg is Dreg & counter=1 [ counter=0; regNum=regNum+1; ] { } +buildVtblDdList: Dreg,buildVtblDdList is Dreg & buildVtblDdList [ counter=counter-1; regNum=regNum+1; ] +{ + build buildVtblDdList; +} + +vtblDdList: "{"^buildVtblDdList^"}" is TMode=0 & c0809=0 & N7 & c1619 & buildVtblDdList [ regNum=(N7<<4)+c1619-1; counter=1; ] { export 1:4; } +vtblDdList: "{"^buildVtblDdList^"}" is TMode=0 & c0809=1 & N7 & c1619 & buildVtblDdList [ regNum=(N7<<4)+c1619-1; counter=2; ] { export 2:4; } +vtblDdList: "{"^buildVtblDdList^"}" is TMode=0 & c0809=2 & N7 & c1619 & buildVtblDdList [ regNum=(N7<<4)+c1619-1; counter=3; ] { export 3:4; } +vtblDdList: "{"^buildVtblDdList^"}" is TMode=0 & c0809=3 & N7 & c1619 & buildVtblDdList [ regNum=(N7<<4)+c1619-1; counter=4; ] { export 4:4; } +vtblDdList: "{"^buildVtblDdList^"}" is TMode=1 & thv_c0809=0 & thv_N7 & thv_c1619 & buildVtblDdList [ regNum=(thv_N7<<4)+thv_c1619-1; counter=1; ] { export 1:4; } +vtblDdList: "{"^buildVtblDdList^"}" is TMode=1 & thv_c0809=1 & thv_N7 & thv_c1619 & buildVtblDdList [ regNum=(thv_N7<<4)+thv_c1619-1; counter=2; ] { export 2:4; } +vtblDdList: "{"^buildVtblDdList^"}" is TMode=1 & thv_c0809=2 & thv_N7 & thv_c1619 & buildVtblDdList [ regNum=(thv_N7<<4)+thv_c1619-1; counter=3; ] { export 3:4; } +vtblDdList: "{"^buildVtblDdList^"}" is TMode=1 & thv_c0809=3 & thv_N7 & thv_c1619 & buildVtblDdList [ regNum=(thv_N7<<4)+thv_c1619-1; counter=4; ] { export 4:4; } + + +:vtbl.8 VRd,vtblDdList,VRm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1011=2 & c0606=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1011=2 & thv_c0606=0 & thv_c0404=0 ) ) & VRm & VRd & VRn & vtblDdList +{ + VRd = VectorTableLookup(VRm,VRn,vtblDdList); +} + +:vtbx.8 VRd,vtblDdList,VRm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1011=2 & c0606=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1011=2 & thv_c0606=1 & thv_c0404=0 ) ) & VRm & VRd & VRn & vtblDdList +{ + VRd = VectorTableLookup(VRm,VRn,vtblDdList); +} + + +###### +# VTST +# + +define pcodeop VectorTest; + +:vtst.^esize2021 Qd, Qn, Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c0811=8 & c0606=1 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=8 & thv_c0606=1 & thv_c0404=1) ) & esize2021 & Qm & Qn & Qd +{ + Qd = VectorTest(Qn, Qm); +} + +:vtst.^esize2021 Dd, Dn, Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=4 & c0811=8 & c0606=0 & c0404=1) | + ($(TMODE_E) & thv_c2327=0x1e & thv_c0811=8 & thv_c0606=0 & thv_c0404=1) ) & esize2021 & Dm & Dn & Dd +{ + Dd = VectorTest(Dn, Dm); +} + +define pcodeop VectorTranspose; + +:vtrn^"."^esize1819 Dd,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=2 & c0811=0 & c0707=1 & Q6=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=2 & thv_c0811=0 & thv_c0707=1 & thv_Q6=0 & thv_c0404=0)) & esize1819 & Dd & Dm +{ + Dd = VectorTranspose(Dm,esize1819); +} + +:vtrn^"."^esize1819 Qd,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1617=2 & c0811=0 & c0707=1 & Q6=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1617=2 & thv_c0811=0 & thv_c0707=1 & thv_Q6=1 & thv_c0404=0) ) & esize1819 & Qm & Qd +{ + Qd = VectorTranspose(Qm,esize1819); +} + +##### +# V[SU]DOT +define pcodeop VectorSignedDotProduct; +define pcodeop VectorUnsignedDotProduct; +define pcodeop VectorSignedUnsignedDotProduct; +define pcodeop VectorUnsignedSignedDotProduct; + +:vsdot.s8 Dd,Dn,Dm0^Mindex is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1c & c2021=2 & c0811=0xd & c0606=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=0xd & thv_c0606=0 & thv_c0404=0) ) & Dm0 & Mindex & Dn & Dd +{ + Dd = VectorSignedDotProduct(Dn,Dm0,Mindex); +} + +:vsdot.s8 Qd,Qn,Dm0^Mindex is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1c & c2021=2 & c0811=0xd & c0606=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=0xd & thv_c0606=1 & thv_c0404=0) ) & Dm0 & Mindex & Qn & Qd +{ + Qd = VectorSignedDotProduct(Qn,Dm0,Mindex); +} + +:vsdot.s8 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=2 & c0811=0xd & c0606=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=2 & thv_c0811=0xd & thv_c0606=0 & thv_c0404=0) ) & Dm & Dn & Dd +{ + Dd = VectorSignedDotProduct(Dn,Dm); +} + +:vsdot.s8 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=2 & c0811=0xd & c0606=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=2 & thv_c0811=0xd & thv_c0606=1 & thv_c0404=0) ) & Qm & Qn & Qd +{ + Qd = VectorSignedDotProduct(Qn,Qm); +} + +:vudot.u8 Dd,Dn,Dm0^Mindex is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1c & c2021=2 & c0811=0xd & c0606=0 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=0xd & thv_c0606=0 & thv_c0404=1) ) & Dm0 & Mindex & Dn & Dd +{ + Dd = VectorUnsignedDotProduct(Dn,Dm0,Mindex); +} + +:vudot.u8 Qd,Qn,Dm0^Mindex is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1c & c2021=2 & c0811=0xd & c0606=1 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=0xd & thv_c0606=1 & thv_c0404=1) ) & Dm0 & Mindex & Qn & Qd +{ + Qd = VectorUnsignedDotProduct(Qn,Dm0,Mindex); +} + +:vudot.u8 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=2 & c0811=0xd & c0606=0 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=2 & thv_c0811=0xd & thv_c0606=0 & thv_c0404=1) ) & Dm & Dn & Dd +{ + Dd = VectorUnsignedDotProduct(Dn,Dm); +} + +:vudot.u8 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x18 & c2021=2 & c0811=0xd & c0606=1 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x18 & thv_c2021=2 & thv_c0811=0xd & thv_c0606=1 & thv_c0404=1) ) & Qm & Qn & Qd +{ + Qd = VectorUnsignedDotProduct(Qn,Qm); +} + +:vsudot.u8 Dd,Dn,Dm0^Mindex is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1d & c2021=0 & c0811=0xd & c0606=0 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=0xd & thv_c0606=0 & thv_c0404=1) ) & Dm0 & Mindex & Dn & Dd +{ + Dd = VectorSignedUnsignedDotProduct(Dn,Dm0,Mindex); +} + +:vsudot.u8 Qd,Qn,Dm0^Mindex is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1d & c2021=0 & c0811=0xd & c0606=1 & c0404=1) | + ($(TMODE_F) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=0xd & thv_c0606=1 & thv_c0404=1) ) & Dm0 & Mindex & Qn & Qd +{ + Qd = VectorSignedUnsignedDotProduct(Qn,Dm0,Mindex); +} + +:vusdot.u8 Dd,Dn,Dm0^Mindex is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1d & c2021=0 & c0811=0xd & c0606=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=0xd & thv_c0606=0 & thv_c0404=0) ) & Dm0 & Mindex & Dn & Dd +{ + Dd = VectorUnsignedSignedDotProduct(Dn,Dm0,Mindex); +} + +:vusdot.u8 Qd,Qn,Dm0^Mindex is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x1d & c2021=0 & c0811=0xd & c0606=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=0xd & thv_c0606=1 & thv_c0404=0) ) & Dm0 & Mindex & Qn & Qd +{ + Qd = VectorUnsignedSignedDotProduct(Qn,Dm0,Mindex); +} + +:vusdot.u8 Dd,Dn,Dm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x19 & c2021=2 & c0811=0xd & c0606=0 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x19 & thv_c2021=2 & thv_c0811=0xd & thv_c0606=0 & thv_c0404=0) ) & Dm & Dn & Dd +{ + Dd = VectorUnsignedSignedDotProduct(Dn,Dm); +} + +:vusdot.u8 Qd,Qn,Qm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=0x19 & c2021=2 & c0811=0xd & c0606=1 & c0404=0) | + ($(TMODE_F) & thv_c2327=0x19 & thv_c2021=2 & thv_c0811=0xd & thv_c0606=1 & thv_c0404=0) ) & Qm & Qn & Qd +{ + Qd = VectorUnsignedSignedDotProduct(Qn,Qm); +} + +####### +# VUZP +# + +define pcodeop VectorUnzip; + +:vuzp^esize1819 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0711=2 & Q6=0 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0711=2 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm & esize1819 +{ + Dd = VectorUnzip(Dm,esize1819); +} + +:vuzp^esize1819 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0711=2 & Q6=1 & c0404=0 ) | + ( $(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0711=2 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm & esize1819 +{ + Qd = VectorUnzip(Qm,esize1819); +} + + +####### +# VZIP +# + +define pcodeop VectorZip; + +:vzip^esize1819 Dd,Dm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0711=3 & Q6=0 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0711=3 & thv_c0606=0 & thv_c0404=0 ) ) & Dd & Dm & esize1819 +{ + Dd = VectorZip(Dm,esize1819); +} + +:vzip^esize1819 Qd,Qm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=7 & c2021=3 & c1819<3 & c1617=2 & c0711=3 & Q6=1 & c0404=0 ) | + ($(TMODE_F) & thv_c2327=0x1f & thv_c2021=3 & thv_c1819<3 & thv_c1617=2 & thv_c0711=3 & thv_c0606=1 & thv_c0404=0 ) ) & Qd & Qm & esize1819 +{ + Qd = VectorZip(Qm,esize1819); +} + + +@endif # SIMD + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARMt.pspec b/python/icicle/Ghidra/Processors/ARM/data/languages/ARMt.pspec new file mode 100644 index 0000000..ff62a39 --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARMt.pspec @@ -0,0 +1,64 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARMtTHUMB.pspec b/python/icicle/Ghidra/Processors/ARM/data/languages/ARMtTHUMB.pspec new file mode 100644 index 0000000..58b125c --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARMtTHUMB.pspec @@ -0,0 +1,65 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARMt_v45.pspec b/python/icicle/Ghidra/Processors/ARM/data/languages/ARMt_v45.pspec new file mode 100644 index 0000000..a8fe2ee --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARMt_v45.pspec @@ -0,0 +1,43 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARMt_v6.pspec b/python/icicle/Ghidra/Processors/ARM/data/languages/ARMt_v6.pspec new file mode 100644 index 0000000..a10848d --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARMt_v6.pspec @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/ARMv8.sinc b/python/icicle/Ghidra/Processors/ARM/data/languages/ARMv8.sinc new file mode 100644 index 0000000..3520d6a --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/ARMv8.sinc @@ -0,0 +1,1348 @@ + +# This macro is always defined in this file, but the ifdef may be +# useful if it is moved to ARMinstructions.sinc. + +crc32_type: "b" is TMode=0 & c2122=0b00 & c0909=0 { } +crc32_type: "h" is TMode=0 & c2122=0b01 & c0909=0 { } +crc32_type: "w" is TMode=0 & c2122=0b10 & c0909=0 { } +crc32_type: "cb" is TMode=0 & c2122=0b00 & c0909=1 { } +crc32_type: "ch" is TMode=0 & c2122=0b01 & c0909=1 { } +crc32_type: "cw" is TMode=0 & c2122=0b10 & c0909=1 { } +crc32_type: "b" is TMode=1 & thv_c0405=0b00 { } +crc32_type: "h" is TMode=1 & thv_c0405=0b01 { } +crc32_type: "w" is TMode=1 & thv_c0405=0b10 { } + +define pcodeop Crc32Calc; + +# F5.1.39,40 p7226,7229 CRC32,CRC32C A1 +:crc32^crc32_type Rd,Rn,Rm + is TMode=0 & c2831=0b1110 & c2327=0b00010 & c2020=0 & c0407=0b0100 & c1011=0b00 & c0808=0 + & crc32_type & Rn & Rd & Rm + { Rd = Crc32Calc(Rn,Rm); } + +# F5.1.39 p7226 CRC32 T1 +:crc32^crc32_type thv_Rt2,thv_Rn,thv_Rm + is TMode=1 & thv_c2031=0b111110101100 & thv_c1215=0b1111 & thv_c0607=0b10 + & crc32_type & thv_Rn & thv_Rt2 & thv_Rm + { thv_Rt2 = Crc32Calc(thv_Rn,thv_Rm); } + +# F5.1.40 p7229 CRC32C T1 +:crc32c^crc32_type thv_Rt2,thv_Rn,thv_Rm + is TMode=1 & thv_c2031=0b111110101101 & thv_c1215=0b1111 & thv_c0607=0b10 + & crc32_type & thv_Rn & thv_Rt2 & thv_Rm + { thv_Rt2 = Crc32Calc(thv_Rn,thv_Rm); } + +define pcodeop DCPSInstruction; + +dcps_lev:1 is TMode=1 & thv_c0001=0b01 { export 1:1; } +dcps_lev:2 is TMode=1 & thv_c0001=0b10 { export 2:1; } +dcps_lev:3 is TMode=1 & thv_c0001=0b11 { export 3:1; } + +# F5.1.43 p7235 DCPS1,DCPS2,DCPS3 DSPS1 variant +:dcps^dcps_lev + is TMode=1 & thv_c1631=0b1111011110001111 & thv_c0215=0b10000000000000 & (thv_c0101=1 | thv_c0000=1) & dcps_lev + { DCPSInstruction(dcps_lev:1); } + +# F5.1.57 p7268 LDA +:lda^COND Rd,[Rn] + is TMode=0 & ARMcond=1 & COND & c2027=0x19 & Rn & Rd & c0011=0xc9f + { + build COND; + Rd = *Rn; + } + +# F5.1.57 p7268 LDA +:lda thv_Rt,[thv_Rn] + is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1010 + & ItCond & thv_Rn & thv_Rt + { + build ItCond; + thv_Rt = *thv_Rn; + } + +# F5.1.58 p7270 LDAB +:ldab^COND Rd,[Rn] + is TMode=0 & ARMcond=1 & COND & c2027=0x1d & Rn & Rd & c0011=0xc9f + { + build COND; + val:1 = *Rn; + Rd = zext(val); + } + +# F5.1.58 p7270 LDAB +:ldab thv_Rt,[thv_Rn] + is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1000 + & ItCond & thv_Rt & thv_Rn + { + build ItCond; + val:1 = *thv_Rn; + thv_Rt = zext(val); + } + +# F5.1.59 p7272 LDAEX +:ldaex^COND Rd,[Rn] + is TMode=0 & ARMcond=1 & COND & c2027=0x19 & Rn & Rd & c0011=0xe9f + { + build COND; + Rd = *Rn; + } + +# F5.1.59 p7272 LDAEX +:ldaex thv_Rt,[thv_Rn] + is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1110 + & ItCond & thv_Rt & thv_Rn + { + build ItCond; + thv_Rt = *thv_Rn; + } + +# F5.1.60 p7274 LDAEXB +:ldaexb^COND Rd,[Rn] + is TMode=0 & ARMcond=1 & COND & c2027=0x1d & Rn & Rd & c0011=0xe9f + { + build COND; + val:1 = *Rn; + Rd = zext(val); + } + +# F5.1.60 p7274 LDAEXB +:ldaexb thv_Rt,thv_Rn + is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1100 + & ItCond & thv_Rt & thv_Rn + { + build ItCond; + val:1 = *thv_Rn; + thv_Rt = zext(val); + } + +# F5.1.61 p7274 LDAEXD +:ldaexd^COND Rd,Rd2,[Rn] + is TMode=0 & ARMcond=1 & COND & c2027=0x1b & Rn & Rd & Rd2 & c0011=0xe9f + { + build COND; +@if ENDIAN == "big" + Rd = *(Rn + 4); + Rd2 = *(Rn); +@else # ENDIAN == "little" + Rd = *(Rn); + Rd2 = *(Rn + 4); +@endif # ENDIAN == "little" + } + +# F5.1.61 p7274 LDAEXD +:ldaexd thv_Rt,thv_Rt2,[thv_Rn] + is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1111 + & ItCond & thv_Rt & thv_Rt2 & thv_Rn + { + build ItCond; +@if ENDIAN == "big" + thv_Rt = *(thv_Rn + 4); + thv_Rt2 = *(thv_Rn); +@else # ENDIAN == "little" + thv_Rt = *(thv_Rn); + thv_Rt2 = *(thv_Rn + 4); +@endif # ENDIAN == "little" + } + +# F5.1.62 p7278 LDAEXH +:ldaexh^COND Rd,[Rn] + is TMode=0 & ARMcond=1 & COND & c2027=0x1f & Rn & Rd & c0011=0xe9f + { + build COND; + val:2 = *Rn; + Rd = zext(val); + } + +# F5.1.62 p7278 LDAEXH +:ldaexh thv_Rt,[thv_Rn] + is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1101 + & ItCond & thv_Rt & thv_Rn + { + build ItCond; + val:2 = *thv_Rn; + thv_Rt = zext(val); + } + +# F5.1.63 p7280 LDAH +:ldah^COND Rd,[Rn] + is TMode=0 & ARMcond=1 & COND & c2027=0x1f & Rn & Rd & c0011=0xc9f + { + build COND; + val:2 = *Rn; + Rd = zext(val); + } + +# F5.1.63 p7280 LDAH +:ldah thv_Rt,[thv_Rn] + is TMode=1 & thv_c2031=0b111010001101 & thv_c0407=0b1001 + & ItCond & thv_Rt & thv_Rn + { + build ItCond; + val:2 = *thv_Rn; + thv_Rt = zext(val); + } + +# F5.1.185 p7573 SEVL A1 variant +:sevl^COND + is TMode=0 & ARMcond=1 & COND & c1627=0b001100100000 & c0007=0b00000101 + { + build COND; + SendEvent(); + } + +# F5.1.185 p7573 SEVL T2 variant +:sevl.w + is TMode=1 & thv_c2031=0b111100111010 & thv_c1415=0b10 & thv_c1212=0 & thv_c0010=0b00000000101 + & ItCond + { + build ItCond; + SendEvent(); + } + +# F5.1.217 p7642 STL +:stl^COND Rm,[Rn] + is TMode=0 & ARMcond=1 & COND & c2027=0x18 & Rn & c0415=0xfc9 & Rm + { + build COND; + *Rn = Rm; + } + +# F5.1.217 p7642 STL +:stl thv_Rt,[thv_Rn] + is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1010 + & ItCond & thv_Rt & thv_Rn + { + build ItCond; + *thv_Rn = thv_Rt; + } + +# F5.1.218 p7644 STLB +:stlb^COND Rm,[Rn] + is TMode=0 & ARMcond=1 & COND & c2027=0x1c & Rn & c0415=0xfc9 & Rm + { + build COND; + *:1 Rn = Rm[0,8]; + } + +# F5.1.218 p7644 STLB +:stlb thv_Rt,[thv_Rn] + is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1000 + & ItCond & thv_Rt & thv_Rn + { + build ItCond; + *:1 thv_Rn = thv_Rt[0,8]; + } + +# F5.1.219 p7646 STLEX +:stlex^COND Rd,Rm,[Rn] + is TMode=0 & ARMcond=1 & COND & c2027=0x18 & Rn & Rd & c0411=0xe9 & Rm + { + build COND; + *Rn = Rm; + Rd = 0; + } + +# F5.1.219 p7646 STLEX +:stlex thv_Rm,thv_Rt,[thv_Rn] + is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1110 + & ItCond & thv_Rm & thv_Rt & thv_Rn + { + build ItCond; + *thv_Rn = thv_Rt; + thv_Rm = 0; + } + +# F5.1.220 p7649 STLEXB +:stlexb^COND Rd,Rm,[Rn] + is TMode=0 & ARMcond=1 & COND & c2027=0x1c & Rn & Rd & c0411=0xe9 & Rm + { + build COND; + *:1 Rn = Rm[0,8]; + Rd = 0; + } + +# F5.1.220 p7649 STLEXB +:stlexb thv_Rm,thv_Rt,[thv_Rn] + is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1100 + & ItCond & thv_Rm & thv_Rt & thv_Rn + { + build ItCond; + *:1 thv_Rn = thv_Rt[0,8]; + thv_Rm = 0; + } + +# F5.1.221 p7651 STLEXD +:stlexd^COND Rd,Rm,Rm2,[Rn] + is TMode=0 & ARMcond=1 & COND & c2027=0x1a & Rn & Rd & c0411=0xe9 & Rm & Rm2 + { + build COND; +@if ENDIAN == "big" + *Rn = Rm; + *(Rn + 4) = Rm2; +@else # ENDIAN == "little" + *Rn = Rm2; + *(Rn + 4) = Rm; +@endif # ENDIAN == "little" + Rd = 0; + } + +# F5.1.221 p7651 STLEXD +:stlexd thv_Rm,thv_Rt,thv_Rt2,[thv_Rn] + is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1111 + & ItCond & thv_Rm & thv_Rt & thv_Rt2 & thv_Rn + { + build ItCond; +@if ENDIAN == "big" + *thv_Rn = thv_Rt; + *(thv_Rn + 4) = thv_Rt2; +@else # ENDIAN == "little" + *thv_Rn = thv_Rt2; + *(thv_Rn + 4) = thv_Rt; +@endif # ENDIAN == "little" + thv_Rm = 0; + } + +# F5.1.222 p7654 STLEXH +:stlexh^COND Rd,Rm,[Rn] + is TMode=0 & ARMcond=1 & COND & c2027=0x1e & Rn & Rd & c0411=0xe9 & Rm + { + build COND; + *:2 Rn = Rm[0,16]; + Rd = 0; + } + +# F5.1.222 p7654 STLEXH +:stlexh thv_Rm,thv_Rt,[thv_Rn] + is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1101 + & ItCond & thv_Rm & thv_Rt & thv_Rn + { + build ItCond; + *:2 thv_Rn = thv_Rt[0,16]; + thv_Rm = 0; + } + +# F5.1.223 p7657 STLH +:stlh^COND Rm,[Rn] + is TMode=0 & ARMcond=1 & COND & c2027=0x1e & Rn & c0415=0xfc9 & Rm + { + build COND; + *:2 Rn = Rm[0,16]; + } + +# F5.1.223 p7657 STLH +:stlh thv_Rt,[thv_Rn] + is TMode=1 & thv_c2031=0b111010001100 & thv_c0407=0b1001 + & ItCond & thv_Rt & thv_Rn + { + build ItCond; + *:2 thv_Rn = thv_Rt[0,16]; + } + +@ifdef INCLUDE_NEON + +# Advanced SIMD support / NEON in ARMv8 + +####### +# macro declarations + +# The Inexact flag is bit 4 of FPEXC +@define FPEXC_IXF "fpexc[3,1]" + +# Rounding modes, as used in pseudocode, defined as an enumeration +# '01' N +@define FPRounding_TIEEVEN "0:1" +# '10' P +@define FPRounding_POSINF "1:1" +# '11' M +@define FPRounding_NEGINF "2:1" +@define FPRounding_ZERO "3:1" +# '00' A +@define FPRounding_TIEAWAY "4:1" +@define FPRounding_ODD "5:1" + +####### +# pcodeop declarations + + + +# FixedToFP(fp, M, N, fbits, unsigned, rounding) +# Convert M-bit fixed point with fbits fractional bits to N-bit +# floating point, controlled by unsigned flag and rounding. Can +# also be used with packed "SIMD" floats. + +define pcodeop FixedToFP; + +# FPConvert(fp, M, N [, rounding]) +# Convert floating point between from M-bit to N-bit precision. +# Can also be used with packed "SIMD" floats. Sometimes +# equivalent to float2float. M, N are the input and output sizes +# (16, 32, 64), implied by pseudocode, but given explicitly +# here. Rounding is only required when converting to integral +# type. + +define pcodeop FPConvert; + +# FPConvertInexact() +# At the end of any rounding or conversion operation, the +# pseudocode tests whether the converted value is identical to +# the original value. If it is not identical, and if the "exact" +# argument is true, then it sets the floating point exception +# FPEXC.Inexact bit. This function is understood to return 0/1 +# depending on whether converstion was exact (0) or inexact (1). +# + +define pcodeop FPConvertInexact; + +# FPToFixed(fp, M, N, fbits, unsigned, rounding) +# Convert M-bit floating point to N-bit fixed point with fbits +# fractional bits, controlled by unsigned flag and rounding. +# between different precisions. Can also be used with packed +# "SIMD" floats. + +define pcodeop FPToFixed; + +# FPRoundInt(fp, N, rounding, exact) +# Round fp to nearest integral floating point, controlled by +# rounding. If exact is true, set FPSR.IXC flag. Can also be +# used with packed "SIMD" floats. + +define pcodeop FPRoundInt; + +# PolynomialMult(op1, op2) + +define pcodeop PolynomialMult; + + + +####### +# The VCVT instructions are a large family for converting between +# floating point numbers and integers, of all sizes and combinations + +# F6.1.58 p7998 A1 cases size = 10 (c0809) +:vcvt^COND^".f64.f32" Dd,Sm + is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11011 & c1616=1 & c1011=0b10 & c0707=1 & c0606=1 & c0404=0 & c0809=0b10) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11011 & thv_c1616=1 & thv_c1011=0b10 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10)) + & COND & Dd & Sm + { build COND; Dd = float2float(Sm); } + +# F6.1.58 p7998 A1 cases size = 11 (c0809) +:vcvt^COND^".f32.f64" Sd,Dm + is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11011 & c1616=1 & c1011=0b10 & c0707=1 & c0606=1 & c0404=0 & c0809=0b11) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11011 & thv_c1616=1 & thv_c1011=0b10 & thv_c0707=1 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11)) + & COND & Sd & Dm + { build COND; Sd = float2float(Dm); } + +# F6.1.59 p8000 A1 op == 1 (c0808) +:vcvt.f32.f16 Qd,Dm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b01 & c1617=0b10 & c0911=0b011 & c0607=0b00 & c0404=0 & c0808=1) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b01 & thv_c1617=0b10 & thv_c0911=0b011 & thv_c0607=0b00 & thv_c0404=0 & thv_c0808=1)) + & Qd & Dm + { + Qd = float2float(Dm:2); + } + +# F6.1.59 p8000 A1 op == 0 (c0808) +:vcvt.f16.f32 Dd,Qm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b01 & c1617=0b10 & c0911=0b011 & c0607=0b00 & c0404=0 & c0808=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b01 & thv_c1617=0b10 & thv_c0911=0b011 & thv_c0607=0b00 & thv_c0404=0 & thv_c0808=0)) + & Dd & Qm + { Dd = float2float(Qm); } + +vcvt_56_64_dt: ".f32.s32" + is ((TMode=0 & c0708=0b00) + | (TMode=1 & thv_c0708=0b00)) + & Dd & Dm + { Dd = FixedToFP(Dm, 32:1, 32:1, 0:1, 0:1, $(FPRounding_TIEEVEN)); } +vcvt_56_64_dt: ".f32.u32" + is ((TMode=0 & c0708=0b01) + | (TMode=1 & thv_c0708=0b01)) + & Dd & Dm + { Dd = FixedToFP(Dm, 32:1, 32:1, 0:1, 1:1, $(FPRounding_TIEEVEN)); } +vcvt_56_64_dt: ".s32.f32" + is ((TMode=0 & c0708=0b10) + | (TMode=1 & thv_c0708=0b10)) + & Dd & Dm + { Dd = FPToFixed(Dm, 32:1, 32:1, 0:1, 0:1, $(FPRounding_ZERO)); } +vcvt_56_64_dt: ".u32.f32" + is ((TMode=0 & c0708=0b11) + | (TMode=1 & thv_c0708=0b11)) + & Dd & Dm + { Dd = FPToFixed(Dm, 32:1, 32:1, 0:1, 1:1, $(FPRounding_ZERO)); } + +vcvt_56_128_dt: ".f32.s32" + is ((TMode=0 & c0708=0b00) + | (TMode=1 & thv_c0708=0b00)) + & Qd & Qm + { Qd = FixedToFP(Qm, 32:1, 32:1, 0:1, 0:1, $(FPRounding_TIEEVEN)); } +vcvt_56_128_dt: ".f32.u32" + is ((TMode=0 & c0708=0b01) + | (TMode=1 & thv_c0708=0b01)) + & Qd & Qm + { Qd = FixedToFP(Qm, 32:1, 32:1, 0:1, 1:1, $(FPRounding_TIEEVEN)); } +vcvt_56_128_dt: ".s32.f32" + is ((TMode=0 & c0708=0b10) + | (TMode=1 & thv_c0708=0b10)) + & Qd & Qm + { Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 0:1, $(FPRounding_ZERO)); } +vcvt_56_128_dt: ".u32.f32" + is ((TMode=0 & c0708=0b11) + | (TMode=1 & thv_c0708=0b11)) + & Qd & Qm + { Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 1:1, $(FPRounding_ZERO)); } + +# F6.1.60 p8002 A1 Q == 0 (c0606) +:vcvt^vcvt_56_64_dt Dd,Dm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c0911=0b011 & c0404=0 & c0606=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c0911=0b011 & thv_c0404=0 & thv_c0606=0)) + & vcvt_56_64_dt & Dd & Dm + unimpl + +# F6.1.60 p8002 A1 Q == 1 (c0606) +:vcvt^vcvt_56_128_dt Qd,Qm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c0911=0b011 & c0404=0 & c0606=1) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c0911=0b011 & thv_c0404=0 & thv_c0606=1)) + & vcvt_56_128_dt & Qd & Qm + unimpl + +# F6.1.61 p8005 A1 opc2==100 && size==10 (c1618, c0809) +:vcvt^COND^".u32.f32" Sd,Sm + is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b100 & c0809=0b10) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b11 & thv_c0404=0 & thv_c1618=0b100 & thv_c0809=0b10)) + & COND & Sd & Sm + { build COND; Sd = zext(Sm f> 0) * (trunc(Sm)); } + +# F6.1.61 p8005 A1 opc2==101 && size==10 (c1618, c0809) +:vcvt^COND^".s32.f32" Sd,Sm + is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b101 & c0809=0b10) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b11 & thv_c0404=0 & thv_c1618=0b101 & thv_c0809=0b10)) + & COND & Sd & Sm + { build COND; Sd = zext(Sm f> 0) * (trunc(Sm)); } + +# F6.1.61 p8005 A1 opc2==100 && size==11 (c1618, c0809) +:vcvt^COND^".u32.f64" Sd,Dm + is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b100 & c0809=0b11) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b11 & thv_c0404=0 & thv_c1618=0b100 & thv_c0809=0b11)) + & COND & Sd & Dm + { build COND; local tmp:8 = zext(Dm f> 0) * (trunc(Dm)); Sd = tmp:4; } + +# F6.1.61 p8005 A1 opc2==101 && size==11 (c1618, c0809) +:vcvt^COND^".s32.f64" Sd,Dm + is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b101 & c0809=0b11) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b11 & thv_c0404=0 & thv_c1618=0b101 & thv_c0809=0b11)) + & COND & Sd & Dm + { build COND; local tmp:8 = zext(Dm f> 0:8) * (trunc(Dm)); Sd = tmp:4; } + +# The rounding mode depends on c0707=0 => FPSCR else ZERO + +vcvt_58_3232_dt: ".f32.u32" + is ((TMode=0 & c0708=0b00) + | (TMode=1 & thv_c0708=0b00)) + & Sd & Sm + { local tmp:8 = zext(Sm); Sd = int2float(tmp); } +vcvt_58_3232_dt: ".f32.s32" + is ((TMode=0 & c0708=0b01) + | (TMode=1 & thv_c0708=0b01)) + & Sd & Sm + { local tmp:8 = sext(Sm); Sd = int2float(tmp); } + +vcvt_58_6432_dt: ".f64.u32" + is ((TMode=0 & c0708=0b10) + | (TMode=1 & thv_c0708=0b10)) + & Dd & Sm + { local tmp:8 = zext(Sm); Dd = int2float(tmp); } +vcvt_58_6432_dt: ".f64.s32" + is ((TMode=0 & c0708=0b11) + | (TMode=1 & thv_c0708=0b11)) + & Dd & Sm + { local tmp:8 = sext(Sm); Dd = int2float(tmp); } + +# F6.1.62 p8009 A1 size == 10 (c0809) +:vcvt^COND^vcvt_58_3232_dt Sd,Sm + is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11100 & c1616=0 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11100 & thv_c1616=0 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10)) + & COND & vcvt_58_3232_dt & Sd & Sm + { build COND; build vcvt_58_3232_dt; } + +# F6.1.62 p8009 A1 size == 11 (c0809) +:vcvt^COND^vcvt_58_6432_dt Dd,Sm + is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11100 & c1616=0 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11100 & thv_c1616=0 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11)) + & COND & vcvt_58_6432_dt & Dd & Sm + { build COND; build vcvt_58_6432_dt; } + +vcvt_59_fbits_built: fbits is TMode=0 & c1621 [ fbits = 64 - c1621; ] { export * [const]:1 fbits; } +vcvt_59_fbits_built: fbits is TMode=1 & thv_c1621 [ fbits = 64 - thv_c1621; ] { export * [const]:1 fbits; } +vcvt_59_fbits: "#"^fbits is TMode=0 & c1621 [ fbits = 64 - c1621; ] { } +vcvt_59_fbits: "#"^fbits is TMode=1 & thv_c1621 [ fbits = 64 - thv_c1621; ] { } + +vcvt_59_32_dt: ".f32.s32" + is ((TMode=0 & c0809=2 & c2424=0) + | (TMode=1 & thv_c0809=2 & thv_c2828=0)) + & Dd & Dm & vcvt_59_fbits_built + { Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } +vcvt_59_32_dt: ".f32.u32" + is ((TMode=0 & c0809=2 & c2424=1) + | (TMode=1 & thv_c0809=2 & thv_c2828=1)) + & Dd & Dm & vcvt_59_fbits_built + { Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } +vcvt_59_32_dt: ".s32.f32" + is ((TMode=0 & c0809=3 & c2424=0) + | (TMode=1 & thv_c0809=3 & thv_c2828=0)) + & Dd & Dm & vcvt_59_fbits_built + { Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); } +vcvt_59_32_dt: ".u32.f32" + is ((TMode=0 & c0809=3 & c2424=1) + | (TMode=1 & thv_c0809=3 & thv_c2828=1)) + & Dd & Dm & vcvt_59_fbits_built + { Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); } +vcvt_59_32_dt: ".f16.s16" + is ((TMode=0 & c0809=0 & c2424=0) + | (TMode=1 & thv_c0809=0 & thv_c2828=0)) + & Dd & Dm & vcvt_59_fbits_built + { Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } +vcvt_59_32_dt: ".f16.u16" + is ((TMode=0 & c0809=0 & c2424=1) + | (TMode=1 & thv_c0809=0 & thv_c2828=1)) + & Dd & Dm & vcvt_59_fbits_built + { Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } +vcvt_59_32_dt: ".s16.f16" + is ((TMode=0 & c0809=1 & c2424=0) + | (TMode=1 & thv_c0809=1 & thv_c2828=0)) + & Dd & Dm & vcvt_59_fbits_built + { Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); } +vcvt_59_32_dt: ".u16.f16" + is ((TMode=0 & c0809=1 & c2424=1) + | (TMode=1 & thv_c0809=1 & thv_c2828=1)) + & Dd & Dm & vcvt_59_fbits_built + { Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); } + +vcvt_59_64_dt: ".f32.s32" + is ((TMode=0 & c0809=2 & c2424=0) + | (TMode=1 & thv_c0809=2 & thv_c2828=0)) + & Qd & Qm & vcvt_59_fbits_built + { Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } +vcvt_59_64_dt: ".f32.u32" + is ((TMode=0 & c0809=2 & c2424=1) + | (TMode=1 & thv_c0809=2 & thv_c2828=1)) + & Qd & Qm & vcvt_59_fbits_built + { Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } +vcvt_59_64_dt: ".s32.f32" + is ((TMode=0 & c0809=3 & c2424=0) + | (TMode=1 & thv_c0809=3 & thv_c2828=0)) + & Qd & Qm & vcvt_59_fbits_built + { Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); } +vcvt_59_64_dt: ".u32.f32" + is ((TMode=0 & c0809=3 & c2424=1) + | (TMode=1 & thv_c0809=3 & thv_c2828=1)) + & Qd & Qm & vcvt_59_fbits_built + { Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); } +vcvt_59_64_dt: ".f16.s16" + is ((TMode=0 & c0809=0 & c2424=0) + | (TMode=1 & thv_c0809=0 & thv_c2828=0)) + & Qd & Qm & vcvt_59_fbits_built + { Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } +vcvt_59_64_dt: ".f16.u16" + is ((TMode=0 & c0809=0 & c2424=1) + | (TMode=1 & thv_c0809=0 & thv_c2828=1)) + & Qd & Qm & vcvt_59_fbits_built + { Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } +vcvt_59_64_dt: ".s16.f16" + is ((TMode=0 & c0809=1 & c2424=0) + | (TMode=1 & thv_c0809=1 & thv_c2828=0)) + & Qd & Qm & vcvt_59_fbits_built + { Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); } +vcvt_59_64_dt: ".u16.f16" + is ((TMode=0 & c0809=1 & c2424=1) + | (TMode=1 & thv_c0809=1 & thv_c2828=1)) + & Qd & Qm & vcvt_59_fbits_built + { Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); } + +# Should add rounding here, if dt2 is s32 or u32 then rounding is +# FPRounding_ZERO otherwise FPROunding_TIEEVEN + +# F6.1.63 p8012 A1 Q = 0 (c0606) +:vcvt^vcvt_59_32_dt Dd,Dm,vcvt_59_fbits + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2527=0b001 & c2323=1 & c2121=1 & c1011=0b11 & c0707=0 & c0404=1 & c0606=0) + | (TMode=1 & thv_c2931=0b111 & thv_c2327=0b11111 & thv_c2121=1 & thv_c1011=0b11 & thv_c0707=0 & thv_c0404=1 & thv_c0606=0)) + & vcvt_59_32_dt & vcvt_59_fbits & Dd & Dm + unimpl + +# F6.1.63 p8012 A1 Q = 1 (c0606) +:vcvt^vcvt_59_64_dt Qd,Qm,vcvt_59_fbits + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2527=0b001 & c2323=1 & c2121=1 & c1011=0b11 & c0707=0 & c0404=1 & c0606=1) + | (TMode=1 & thv_c2931=0b111 & thv_c2327=0b11111 & thv_c2121=1 & thv_c1011=0b11 & thv_c0707=0 & thv_c0404=1 & thv_c0606=1)) + & vcvt_59_64_dt & vcvt_59_fbits & Qd & Qm + unimpl + +vcvt_60_fbits_built: fbits is TMode=0 & c0707=0 & c0505 & c0003 [fbits = 16 - ( c0003 * 2 + c0505); ] { export * [const]:1 fbits; } +vcvt_60_fbits_built: fbits is TMode=1 & thv_c0707=0 & thv_c0505 & thv_c0003 [fbits = 16 - (thv_c0003 * 2 + thv_c0505); ] { export * [const]:1 fbits; } +vcvt_60_fbits_built: fbits is TMode=0 & c0707=1 & c0505 & c0003 [fbits = 32 - ( c0003 * 2 + c0505); ] { export * [const]:1 fbits; } +vcvt_60_fbits_built: fbits is TMode=1 & thv_c0707=1 & thv_c0505 & thv_c0003 [fbits = 32 - (thv_c0003 * 2 + thv_c0505); ] { export * [const]:1 fbits; } +vcvt_60_fbits: "#"^fbits is TMode=0 & c0707=0 & c0505 & c0003 [fbits = 16 - ( c0003 * 2 + c0505); ] { } +vcvt_60_fbits: "#"^fbits is TMode=1 & thv_c0707=0 & thv_c0505 & thv_c0003 [fbits = 16 - (thv_c0003 * 2 + thv_c0505); ] { } +vcvt_60_fbits: "#"^fbits is TMode=0 & c0707=1 & c0505 & c0003 [fbits = 32 - ( c0003 * 2 + c0505); ] { } +vcvt_60_fbits: "#"^fbits is TMode=1 & thv_c0707=1 & thv_c0505 & thv_c0003 [fbits = 32 - (thv_c0003 * 2 + thv_c0505); ] { } + +vcvt_60_32_dt: ".f32.s16" + is ((TMode=0 & c1818=0 & c1616=0 & c0809=0b10 & c0707=0) + | (TMode=1 & thv_c1818=0 & thv_c1616=0 & thv_c0809=0b10 & thv_c0707=0)) + & Sd & Sd2 & vcvt_60_fbits_built + { Sd = FixedToFP(Sd2, 16:1, 32:1, vcvt_60_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } +vcvt_60_32_dt: ".f32.s32" + is ((TMode=0 & c1818=0 & c1616=0 & c0809=0b10 & c0707=1) + | (TMode=1 & thv_c1818=0 & thv_c1616=0 & thv_c0809=0b10 & thv_c0707=1)) + & Sd & Sd2 & vcvt_60_fbits_built + { Sd = FixedToFP(Sd2, 32:1, 32:1, vcvt_60_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } +vcvt_60_32_dt: ".f32.u16" + is ((TMode=0 & c1818=0 & c1616=1 & c0809=0b10 & c0707=0) + | (TMode=1 & thv_c1818=0 & thv_c1616=1 & thv_c0809=0b10 & thv_c0707=0)) + & Sd & Sd2 & vcvt_60_fbits_built + { Sd = FixedToFP(Sd2, 16:1, 32:1, vcvt_60_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } +vcvt_60_32_dt: ".f32.u32" + is ((TMode=0 & c1818=0 & c1616=1 & c0809=0b10 & c0707=1) + | (TMode=1 & thv_c1818=0 & thv_c1616=1 & thv_c0809=0b10 & thv_c0707=1)) + & Sd & Sd2 & vcvt_60_fbits_built + { Sd = FixedToFP(Sd2, 32:1, 32:1, vcvt_60_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } +vcvt_60_32_dt: ".s16.f32" + is ((TMode=0 & c1818=1 & c1616=0 & c0809=0b10 & c0707=0) + | (TMode=1 & thv_c1818=1 & thv_c1616=0 & thv_c0809=0b10 & thv_c0707=0)) + & Sd & Sd2 & vcvt_60_fbits_built + { Sd = FPToFixed(Sd2, 32:1, 16:1, vcvt_60_fbits_built, 0:1, $(FPRounding_ZERO)); } +vcvt_60_32_dt: ".s32.f32" + is ((TMode=0 & c1818=1 & c1616=0 & c0809=0b10 & c0707=1) + | (TMode=1 & thv_c1818=1 & thv_c1616=0 & thv_c0809=0b10 & thv_c0707=1)) + & Sd & Sd2 & vcvt_60_fbits_built + { Sd = FPToFixed(Sd2, 32:1, 32:1, vcvt_60_fbits_built, 0:1, $(FPRounding_ZERO)); } +vcvt_60_32_dt: ".u16.f32" + is ((TMode=0 & c1818=1 & c1616=1 & c0809=0b10 & c0707=0) + | (TMode=1 & thv_c1818=1 & thv_c1616=1 & thv_c0809=0b10 & thv_c0707=0)) + & Sd & Sd2 & vcvt_60_fbits_built + { Sd = FPToFixed(Sd2, 32:1, 16:1, vcvt_60_fbits_built, 1:1, $(FPRounding_ZERO)); } +vcvt_60_32_dt: ".u32.f32" + is ((TMode=0 & c1818=1 & c1616=1 & c0809=0b10 & c0707=1) + | (TMode=1 & thv_c1818=1 & thv_c1616=1 & thv_c0809=0b10 & thv_c0707=1)) + & Sd & Sd2 & vcvt_60_fbits_built + { Sd = FPToFixed(Sd2, 32:1, 32:1, vcvt_60_fbits_built, 1:1, $(FPRounding_ZERO)); } + +vcvt_60_64_dt: ".f64.s16" + is ((TMode=0 & c1818=0 & c1616=0 & c0809=0b11 & c0707=0) + | (TMode=1 & thv_c1818=0 & thv_c1616=0 & thv_c0809=0b11 & thv_c0707=0)) + & Dd & Dd2 & vcvt_60_fbits_built + { Dd = FixedToFP(Dd2, 16:1, 64:1, vcvt_60_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } +vcvt_60_64_dt: ".f64.s32" + is ((TMode=0 & c1818=0 & c1616=0 & c0809=0b11 & c0707=1) + | (TMode=1 & thv_c1818=0 & thv_c1616=0 & thv_c0809=0b11 & thv_c0707=1)) + & Dd & Dd2 & vcvt_60_fbits_built + { Dd = FixedToFP(Dd2, 32:1, 64:1, vcvt_60_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } +vcvt_60_64_dt: ".f64.u16" + is ((TMode=0 & c1818=0 & c1616=1 & c0809=0b11 & c0707=0) + | (TMode=1 & thv_c1818=0 & thv_c1616=1 & thv_c0809=0b11 & thv_c0707=0)) + & Dd & Dd2 & vcvt_60_fbits_built + { Dd = FixedToFP(Dd2, 16:1, 64:1, vcvt_60_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } +vcvt_60_64_dt: ".f64.u32" + is ((TMode=0 & c1818=0 & c1616=1 & c0809=0b11 & c0707=1) + | (TMode=1 & thv_c1818=0 & thv_c1616=1 & thv_c0809=0b11 & thv_c0707=1)) + & Dd & Dd2 & vcvt_60_fbits_built + { Dd = FixedToFP(Dd2, 32:1, 64:1, vcvt_60_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } +vcvt_60_64_dt: ".s16.f64" + is ((TMode=0 & c1818=1 & c1616=0 & c0809=0b11 & c0707=0) + | (TMode=1 & thv_c1818=1 & thv_c1616=0 & thv_c0809=0b11 & thv_c0707=0)) + & Dd & Dd2 & vcvt_60_fbits_built + { Dd = FPToFixed(Dd2, 64:1, 16:1, vcvt_60_fbits_built, 0:1, $(FPRounding_ZERO)); } +vcvt_60_64_dt: ".s32.f64" + is ((TMode=0 & c1818=1 & c1616=0 & c0809=0b11 & c0707=1) + | (TMode=1 & thv_c1818=1 & thv_c1616=0 & thv_c0809=0b11 & thv_c0707=1)) + & Dd & Dd2 & vcvt_60_fbits_built + { Dd = FPToFixed(Dd2, 64:1, 32:1, vcvt_60_fbits_built, 0:1, $(FPRounding_ZERO)); } +vcvt_60_64_dt: ".u16.f64" + is ((TMode=0 & c1818=1 & c1616=1 & c0809=0b11 & c0707=0) + | (TMode=1 & thv_c1818=1 & thv_c1616=1 & thv_c0809=0b11 & thv_c0707=0)) + & Dd & Dd2 & vcvt_60_fbits_built + { Dd = FPToFixed(Dd2, 64:1, 16:1, vcvt_60_fbits_built, 1:1, $(FPRounding_ZERO)); } +vcvt_60_64_dt: ".u32.f64" + is ((TMode=0 & c1818=1 & c1616=1 & c0809=0b11 & c0707=1) + | (TMode=1 & thv_c1818=1 & thv_c1616=1 & thv_c0809=0b11 & thv_c0707=1)) + & Dd & Dd2 & vcvt_60_fbits_built + { Dd = FPToFixed(Dd2, 64:1, 32:1, vcvt_60_fbits_built, 1:1, $(FPRounding_ZERO)); } + +# F6.1.63 p8012 A1 op=0/1 sf=10 (c1818, c0809) +:vcvt^COND^vcvt_60_32_dt Sd,Sd2,vcvt_60_fbits + is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1717=1 & c1011=0b10 & c0606=1 & c0404=0 & c1818 & c0809=0b10) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1717=1 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c1818 & thv_c0809=0b10)) + & COND & vcvt_60_fbits & vcvt_60_32_dt & Sd & Sd2 + { build COND; build vcvt_60_32_dt; } + +# F6.1.63 p8012 A1 op=0/1 sf=11 (c1818, c0809) +:vcvt^COND^vcvt_60_64_dt Dd,Dd2,vcvt_60_fbits + is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1717=1 & c1011=0b10 & c0606=1 & c0404=0 & c1818 & c0809=0b11) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1717=1 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c1818 & thv_c0809=0b11)) + & COND & vcvt_60_fbits & vcvt_60_64_dt & Dd & Dd2 + { build COND; build vcvt_60_64_dt; } + +# vcvta, vcvtm, vcvtn, and vcvtp + +vcvt_amnp_simd_RM: "a" + is ((TMode=0 & c0809=0b00) + | (TMode=1 & thv_c0809=0b00)) + { export $(FPRounding_TIEAWAY); } +vcvt_amnp_simd_RM: "n" + is ((TMode=0 & c0809=0b01) + | (TMode=1 & thv_c0809=0b01)) + { export $(FPRounding_TIEEVEN); } +vcvt_amnp_simd_RM: "p" + is ((TMode=0 & c0809=0b10) + | (TMode=1 & thv_c0809=0b10)) + { export $(FPRounding_POSINF); } +vcvt_amnp_simd_RM: "m" + is ((TMode=0 & c0809=0b11) + | (TMode=1 & thv_c0809=0b11)) + { export $(FPRounding_NEGINF); } + +# These RM values need to be converted properly +vcvt_amnp_simd_64_dt: ".s32" is TMode=0 & c0707=0 & c0809 & vcvt_amnp_simd_RM & Dd & Dm { Dd = FPToFixed(Dm, 32:1, 32:1, 0:1, 0:1, vcvt_amnp_simd_RM); } +vcvt_amnp_simd_64_dt: ".s32" is TMode=1 & thv_c0707=0 & thv_c0809 & vcvt_amnp_simd_RM & Dd & Dm { Dd = FPToFixed(Dm, 32:1, 32:1, 0:1, 0:1, vcvt_amnp_simd_RM); } +vcvt_amnp_simd_64_dt: ".u32" is TMode=0 & c0707=1 & c0809 & vcvt_amnp_simd_RM & Dd & Dm { Dd = FPToFixed(Dm, 32:1, 32:1, 0:1, 1:1, vcvt_amnp_simd_RM); } +vcvt_amnp_simd_64_dt: ".u32" is TMode=1 & thv_c0707=1 & thv_c0809 & vcvt_amnp_simd_RM & Dd & Dm { Dd = FPToFixed(Dm, 32:1, 32:1, 0:1, 1:1, vcvt_amnp_simd_RM); } + +vcvt_amnp_simd_128_dt: ".s32" is TMode=0 & c0707=0 & c0809 & vcvt_amnp_simd_RM & Qd & Qm { Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 0:1, vcvt_amnp_simd_RM); } +vcvt_amnp_simd_128_dt: ".s32" is TMode=1 & thv_c0707=0 & thv_c0809 & vcvt_amnp_simd_RM & Qd & Qm { Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 0:1, vcvt_amnp_simd_RM); } +vcvt_amnp_simd_128_dt: ".u32" is TMode=0 & c0707=1 & c0809 & vcvt_amnp_simd_RM & Qd & Qm { Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 1:1, vcvt_amnp_simd_RM); } +vcvt_amnp_simd_128_dt: ".u32" is TMode=1 & thv_c0707=1 & thv_c0809 & vcvt_amnp_simd_RM & Qd & Qm { Qd = FPToFixed(Qm, 32:1, 32:1, 0:1, 1:1, vcvt_amnp_simd_RM); } + +# F6.1.65,69,71,73 p8019,8028,8032,8036 A1 64-bit SIMD vector variant Q = 0 (c0606) +:vcvt^vcvt_amnp_simd_RM^vcvt_amnp_simd_64_dt^".f32" Dd,Dm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c1011=0b00 & c0404=0 & c0606=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c1011=0b00 & thv_c0404=0 & thv_c0606=0)) + & vcvt_amnp_simd_RM & vcvt_amnp_simd_64_dt & Dd & Dm + unimpl + +# F6.1.65,69,71,73 p8019,8028,8032,8036 A1 128-bit SIMD vector variant Q = 1(c0606) +:vcvt^vcvt_amnp_simd_RM^vcvt_amnp_simd_128_dt^".f32" Qd,Qm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c1011=0b00 & c0404=0 & c0606=1) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c1011=0b00 & thv_c0404=0 & thv_c0606=1)) + & vcvt_amnp_simd_RM & vcvt_amnp_simd_128_dt & Qd & Qm + unimpl + +vcvt_amnp_fp_RM: "a" + is ((TMode=0 & c1617=0b00) + | (TMode=1 & thv_c1617=0b00)) + { export $(FPRounding_TIEAWAY); } +vcvt_amnp_fp_RM: "n" + is ((TMode=0 & c1617=0b01) + | (TMode=1 & thv_c1617=0b01)) + { export $(FPRounding_TIEEVEN); } +vcvt_amnp_fp_RM: "p" + is ((TMode=0 & c1617=0b10) + | (TMode=1 & thv_c1617=0b10)) + { export $(FPRounding_POSINF); } +vcvt_amnp_fp_RM: "m" + is ((TMode=0 & c1617=0b11) + | (TMode=1 & thv_c1617=0b11)) + { export $(FPRounding_NEGINF); } + +vcvt_amnp_fp_s_dt: ".u32" is TMode=0 & c0707=0 & c1617 & vcvt_amnp_fp_RM & Sd & Sm { Sd = FPToFixed(Sm, 32:1, 32:1, 0:1, 1:1, vcvt_amnp_fp_RM); } +vcvt_amnp_fp_s_dt: ".u32" is TMode=1 & thv_c0707=0 & thv_c1617 & vcvt_amnp_fp_RM & Sd & Sm { Sd = FPToFixed(Sm, 32:1, 32:1, 0:1, 1:1, vcvt_amnp_fp_RM); } +vcvt_amnp_fp_s_dt: ".s32" is TMode=0 & c0707=1 & c1617 & vcvt_amnp_fp_RM & Sd & Sm { Sd = FPToFixed(Sm, 32:1, 32:1, 0:1, 0:1, vcvt_amnp_fp_RM); } +vcvt_amnp_fp_s_dt: ".s32" is TMode=1 & thv_c0707=1 & thv_c1617 & vcvt_amnp_fp_RM & Sd & Sm { Sd = FPToFixed(Sm, 32:1, 32:1, 0:1, 0:1, vcvt_amnp_fp_RM); } + +vcvt_amnp_fp_d_dt: ".u32" is TMode=0 & c0707=0 & c1617 & vcvt_amnp_fp_RM & Sd & Dm { Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 1:1, vcvt_amnp_fp_RM); } +vcvt_amnp_fp_d_dt: ".u32" is TMode=1 & thv_c0707=0 & thv_c1617 & vcvt_amnp_fp_RM & Sd & Dm { Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 1:1, vcvt_amnp_fp_RM); } +vcvt_amnp_fp_d_dt: ".s32" is TMode=0 & c0707=1 & c1617 & vcvt_amnp_fp_RM & Sd & Dm { Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 0:1, vcvt_amnp_fp_RM); } +vcvt_amnp_fp_d_dt: ".s32" is TMode=1 & thv_c0707=1 & thv_c1617 & vcvt_amnp_fp_RM & Sd & Dm { Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 0:1, vcvt_amnp_fp_RM); } + +# F6.1.66,70,72,74 p8021,8030,8034,8038 Single-precision scalar variant size = 01 (c0809) +:vcvt^vcvt_amnp_fp_RM^vcvt_amnp_fp_s_dt^".f16" Sd,Sm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b11 & c1819=0b11 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b01) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b11 & thv_c1819=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b01)) + & vcvt_amnp_fp_RM & vcvt_amnp_fp_s_dt & Sd & Sm + unimpl + +# F6.1.66,70,72,74 p8021,8030,8034,8038 Single-precision scalar variant size = 11 (c0809) +:vcvt^vcvt_amnp_fp_RM^vcvt_amnp_fp_s_dt^".f32" Sd,Sm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b11 & c1819=0b11 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b11 & thv_c1819=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10)) + & vcvt_amnp_fp_RM & vcvt_amnp_fp_s_dt & Sd & Sm + unimpl + +# F6.1.66,70,72,74 p8021,8030,8034,8038 Double-precision scalar variant size = 11 (c0809) +:vcvt^vcvt_amnp_fp_RM^vcvt_amnp_fp_d_dt^".f64" Sd,Dm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b11 & c1819=0b11 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b11 & thv_c1819=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11)) + & vcvt_amnp_fp_RM & vcvt_amnp_fp_d_dt & Sd & Dm + unimpl + +# vcvtb and vcvtt + +vcvt_bt3216_op: "b" + is ((TMode=0 & c0707=0) + | (TMode=1 & thv_c0707=0)) + & Sd & Sm + { Sd = float2float(Sm:2); } +vcvt_bt3216_op: "t" + is ((TMode=0 & c0707=1) + | (TMode=1 & thv_c0707=1)) + & Sd & Sm + { w:2 = Sm(2); Sd = float2float(w); } + +vcvt_bt6416_op: "b" + is ((TMode=0 & c0707=0) + | (TMode=1 & thv_c0707=0)) + & Dd & Sm + { Dd = float2float(Sm:2); } +vcvt_bt6416_op: "t" + is ((TMode=0 & c0707=1) + | (TMode=1 & thv_c0707=1)) + & Dd & Sm + { w:2 = Sm(2); Dd = float2float(w); } + +vcvt_bt1632_op: "b" + is ((TMode=0 & c0707=0) + | (TMode=1 & thv_c0707=0)) + & Sd & Sm + { Sd[0,16] = float2float(Sm); } +vcvt_bt1632_op: "t" + is ((TMode=0 & c0707=1) + | (TMode=1 & thv_c0707=1)) + & Sd & Sm + { tmp:2 = float2float(Sm); Sd = (zext(tmp)<<16) | zext(Sd[0,16]); } + +vcvt_bt1664_op: "b" + is ((TMode=0 & c0707=0) + | (TMode=1 & thv_c0707=0)) + & Sd & Dm + { Sd[0,16] = float2float(Dm); } +vcvt_bt1664_op: "t" + is ((TMode=0 & c0707=1) + | (TMode=1 & thv_c0707=1)) + & Sd & Dm + { tmp:2 = float2float(Dm); Sd = (zext(tmp)<<16) | zext(Sd[0,16]); } + +# F6.1.67 p8023 A1 cases op:sz = 00 (c1616, c0808) +# F6.1.76 p8044 A1 cases op:sz = 00 (c1616, c0808) +:vcvt^vcvt_bt3216_op^COND^".f32.f16" Sd,Sm + is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11001 & c0911=0b101 & c0606=1 & c0404=0 & c1616=0 & c0808=0) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11001 & thv_c0911=0b101 & thv_c0606=1 & thv_c0404=0 & thv_c1616=0 & thv_c0808=0)) + & COND & vcvt_bt3216_op & Sd & Sm + { build COND; build vcvt_bt3216_op; } + +# F6.1.67 p8023 A1 cases op:sz = 01 (c1616, c0808) +# F6.1.76 p8044 A1 cases op:sz = 01 (c1616, c0808) +:vcvt^vcvt_bt6416_op^COND^".f64.f16" Dd,Sm + is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11001 & c0911=0b101 & c0606=1 & c0404=0 & c1616=0 & c0808=1) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11001 & thv_c0911=0b101 & thv_c0606=1 & thv_c0404=0 & thv_c1616=0 & thv_c0808=1)) + & COND & vcvt_bt6416_op & Dd & Sm + { build COND; build vcvt_bt6416_op; } + +# F6.1.67 p8023 A1 cases op:sz = 10 (c1616, c0808) +# F6.1.76 p8044 A1 cases op:sz = 10 (c1616, c0808) +:vcvt^vcvt_bt1632_op^COND^".f16.f32" Sd,Sm + is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11001 & c0911=0b101 & c0606=1 & c0404=0 & c1616=1 & c0808=0) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11001 & thv_c0911=0b101 & thv_c0606=1 & thv_c0404=0 & thv_c1616=1 & thv_c0808=0)) + & COND & vcvt_bt1632_op & Sd & Sm + { build COND; build vcvt_bt1632_op; } + +# F6.1.67 p8023 A1 cases op:sz = 11 (c1616, c0808) +# F6.1.76 p8044 A1 cases op:sz = 11 (c1616, c0808) +:vcvt^vcvt_bt1664_op^COND^".f16.f64" Sd,Dm + is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1721=0b11001 & c0911=0b101 & c0606=1 & c0404=0 & c1616=1 & c0808=1) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1721=0b11001 & thv_c0911=0b101 & thv_c0606=1 & thv_c0404=0 & thv_c1616=1 & thv_c0808=1)) + & COND & vcvt_bt1664_op & Sd & Dm + { build COND; build vcvt_bt1664_op; } + +# vcvtr + +# F6.1.75 p8040 A1 case opc2=100 size=10 (c1618, c0809) +:vcvtr^COND^".u32.f32" Sd,Sm + is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b01 & c0404=0 & c1618=0b100 & c0809=0b10) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c1618=0b100 & thv_c0809=0b10)) + & COND & Sd & Sm + { build COND; Sd = FPToFixed(Sm, 32:1, 32:1, 0:1, 1:1, $(FPSCR_RMODE)); } + +# F6.1.75 p8040 A1 case opc2=101 size=10 +:vcvtr^COND^".s32.f32" Sd,Sm + is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b01 & c0404=0 & c1618=0b101 & c0809=0b10) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c1618=0b101 & thv_c0809=0b10)) + & COND & Sd & Sm + { build COND; Sd = FPToFixed(Sm, 32:1, 32:1, 0:1, 0:1, $(FPSCR_RMODE)); } + +# F6.1.75 p8040 A1 case opc2=100 size=11 +:vcvtr^COND^".u32.f64" Sd,Dm + is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b01 & c0404=0 & c1618=0b100 & c0809=0b11) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c1618=0b100 & thv_c0809=0b11)) + & COND & Sd & Dm + { build COND; Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 1:1, $(FPSCR_RMODE)); } + +# F6.1.75 p8040 A1 case opc2=101 size=11 +:vcvtr^COND^".s32.f64" Sd,Dm + is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b01 & c0404=0 & c1618=0b101 & c0809=0b11) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c1618=0b101 & thv_c0809=0b11)) + & COND & Sd & Dm + { build COND; Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 0:1, $(FPSCR_RMODE)); } + +####### +# VMAXNM/VMINNM + + +# FPMaxNum(Vn, Vm) +# Return the maximum of two floating point numbers. +# Includes FP and SIMD variants of all lane sizes. + +define pcodeop FPMaxNum; + +# FPMinNum(Vn, Vm) +# Return the minimum of two floating point numbers. +# Includes FP and SIMD variants of all lane sizes. + +define pcodeop FPMinNum; + +# F6.1.117 p8178 A1/T1 Q = 0 (c0606) +:vmaxnm^".f32" Dd,Dn,Dm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1111 & c0404=1 & c0606=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0)) + & Dd & Dn & Dm + { Dd = FPMaxNum(Dn, Dm); } + +# F6.1.117 p8178 A1/T1 Q = 1 (c0606) +:vmaxnm^".f32" Qd,Qn,Qm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1111 & c0404=1 & c0606=1) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1)) + & Qd & Qn & Qm + { Qd = FPMaxNum(Qn, Qm); } + +# F6.1.117 p8178 A1/T1 Q = 0 (c0606) +:vmaxnm^".f16" Dd,Dn,Dm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1111 & c0404=1 & c0606=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0)) + & Dd & Dn & Dm + { Dd = FPMaxNum(Dn, Dm); } + +# F6.1.117 p8178 A1/T1 Q = 1 (c0606) +:vmaxnm^".f16" Qd,Qn,Qm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1111 & c0404=1 & c0606=1) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1)) + & Qd & Qn & Qm + { Qd = FPMaxNum(Qn, Qm); } + +# F6.1.117 p8178 A2/T2 size = 01 (c0809) +:vmaxnm^".f16" Sd,Sn,Sm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b01) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b01)) + & Sd & Sn & Sm + { Sd = FPMaxNum(Sn, Sm); } + +# F6.1.117 p8178 A2/T2 size = 10 (c0809) +:vmaxnm^".f32" Sd,Sn,Sm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b10) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b10)) + & Sd & Sn & Sm + { Sd = FPMaxNum(Sn, Sm); } + +# F6.1.117 p8178 A2/T2 size = 11 (c0809) +:vmaxnm^".f64" Dd,Dn,Dm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b11) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b11)) + & Dd & Dn & Dm + { Dd = FPMaxNum(Dn, Dm); } + +# F6.1.120 p8178 A1/T1 Q = 0 (c0606) +:vminnm^".f32" Dd,Dn,Dm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1111 & c0404=1 & c0606=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0)) + & Dd & Dn & Dm + { Dd = FPMinNum(Dn, Dm); } + +# F6.1.120 p8178 A1/T1 Q = 1 (c0606) +:vminnm^".f32" Qd,Qn,Qm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1111 & c0404=1 & c0606=1) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1)) + & Qd & Qn & Qm + { Qd = FPMinNum(Qn, Qm); } + +# F6.1.120 p8178 A1/T1 Q = 0 (c0606) +:vminnm^".f16" Dd,Dn,Dm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b11 & c0811=0b1111 & c0404=1 & c0606=0) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b11 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0)) + & Dd & Dn & Dm + { Dd = FPMinNum(Dn, Dm); } + +# F6.1.120 p8178 A1/T1 Q = 1 (c0606) +:vminnm^".f16" Qd,Qn,Qm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b11 & c0811=0b1111 & c0404=1 & c0606=1) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b11 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1)) + & Qd & Qn & Qm + { Qd = FPMinNum(Qn, Qm); } + +# F6.1.120 p8178 A2/T2 size = 01 (c0809) +:vminnm^".f16" Sd,Sn,Sm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b01) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b01)) + & Sd & Sn & Sm + { Sd = FPMinNum(Sn, Sm); } + +# F6.1.120 p8178 A2/T2 size = 10 (c0809) +:vminnm^".f32" Sd,Sn,Sm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10)) + & Sd & Sn & Sm + { Sd = FPMinNum(Sn, Sm); } + +# F6.1.120 p8178 A2/T2 size = 11 (c0809) +:vminnm^".f64" Dd,Dn,Dm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11)) + & Dd & Dn & Dm + { Dd = FPMinNum(Dn, Dm); } + +####### +# VMULL instructions vector/polynomial multiplication + +vmull_dt: ".s8" + is ((TMode=0 & c0909=0 & c2424=0 & c2021=0b00) + | (TMode=1 & thv_c0909=0 & thv_c2828=0 & thv_c2021=0b00)) + { } + +vmull_dt: ".s16" + is ((TMode=0 & c0909=0 & c2424=0 & c2021=0b01) + | (TMode=1 & thv_c0909=0 & thv_c2828=0 & thv_c2021=0b01)) + { } + +vmull_dt: ".s32" + is ((TMode=0 & c0909=0 & c2424=0 & c2021=0b10) + | (TMode=1 & thv_c0909=0 & thv_c2828=0 & thv_c2021=0b10)) + { } + +vmull_dt: ".u8" + is ((TMode=0 & c0909=0 & c2424=1 & c2021=0b00) + | (TMode=1 & thv_c0909=0 & thv_c2828=1 & thv_c2021=0b00)) + { } + +vmull_dt: ".u16" + is ((TMode=0 & c0909=0 & c2424=1 & c2021=0b01) + | (TMode=1 & thv_c0909=0 & thv_c2828=1 & thv_c2021=0b01)) + { } + +vmull_dt: ".u32" + is ((TMode=0 & c0909=0 & c2424=1 & c2021=0b10) + | (TMode=1 & thv_c0909=0 & thv_c2828=1 & thv_c2021=0b10)) + { } + +vmull_dt: ".p8" + is ((TMode=0 & c0909=1 & c2424=0 & c2021=0b00) + | (TMode=1 & thv_c0909=1 & thv_c2828=0 & thv_c2021=0b00)) + { } + +vmull_dt: ".p64" + is ((TMode=0 & c0909=1 & c2424=0 & c2021=0b10) + | (TMode=1 & thv_c0909=1 & thv_c2828=0 & thv_c2021=0b10)) + { } + +# F6.1.149 p8266 VMULL (-integer and +polynomial) op=1 (c0909) (with condition U!=1 and size!=0b11 and size!=01) +:vmull^vmull_dt Qd,Dn,Dm + is ((TMode=0 & ARMcond=0 & c2531=0b1111001 & c2424=0 & c2323=1 & ( c2121 & c2020=0) & c1011=0b11 & c0808=0 & c0606=0 & c0404=0 & c0909=1) + | (TMode=1 & thv_c2931=0b111 & thv_c2828=0 & thv_c2327=0b11111 & (thv_c2121 & thv_c2020=0) & thv_c1011=0b11 & thv_c0808=0 & thv_c0606=0 & thv_c0404=0 & thv_c0909=1)) + & vmull_dt & Qd & Dn & Dm + { Qd = PolynomialMult(Dn, Dm); } + +# F6.1.149 p8266 VMULL (+integer and -polynomial) op=0 (c0909) (with condition size!=0b11) +:vmull^vmull_dt Qd,Dn,Dm + is ((TMode=0 & ARMcond=0 & c2531=0b1111001 & c2323=1 & ( c2121=0 | c2020=0) & c1011=0b11 & c0808=0 & c0606=0 & c0404=0 & c0909=0) + | (TMode=1 & thv_c2931=0b111 & thv_c2327=0b11111 & (thv_c2121=0 | thv_c2020=0) & thv_c1011=0b11 & thv_c0808=0 & thv_c0606=0 & thv_c0404=0 & thv_c0909=0)) + & vmull_dt & Qd & Dn & Dm + { Qd = VectorMultiply(Dn, Dm); } + +####### +# The VRINT instructions round a "floating-point to an integral +# floating point value of the same size", i.e. trunc. +# The arguments are +# 1: floating point value (can be 2 packed in a Q register) +# 2: rounding mode +# 3: boolean exact, if true then raise the Inexact exception if the +# result differs from the original + +vrint_simd_RM: "a" + is ((TMode=0 & c0709=0b010) + | (TMode=1 & thv_c0709=0b010)) + { export $(FPRounding_TIEAWAY); } + +vrint_simd_RM: "m" + is ((TMode=0 & c0709=0b101) + | (TMode=1 & thv_c0709=0b101)) + { export $(FPRounding_NEGINF); } + +vrint_simd_RM: "n" + is ((TMode=0 & c0709=0b000) + | (TMode=1 & thv_c0709=0b000)) + { export $(FPRounding_TIEEVEN); } + +vrint_simd_RM: "p" + is ((TMode=0 & c0709=0b111) + | (TMode=1 & thv_c0709=0b111)) + { export $(FPRounding_POSINF); } + +vrint_simd_RM: "x" + is ((TMode=0 & c0709=0b001) + | (TMode=1 & thv_c0709=0b001)) + { export $(FPRounding_TIEEVEN); } + +vrint_simd_RM: "z" + is ((TMode=0 & c0709=0b011) + | (TMode=1 & thv_c0709=0b011)) + { export $(FPRounding_ZERO); } + +# For vrintx, the exact flag is 1, and the IXF flag is set (inexact) + +vrint_simd_exact: "x" + is ((TMode=0 & c0709=0b001) + | (TMode=1 & thv_c0709=0b001)) + { export 1:1; } + +vrint_simd_exact: + is ((TMode=0 & ( c0707=1 | c0808=1 | c0909=0)) + | (TMode=1 & ( thv_c0707=1 | thv_c0808=1 | thv_c0909=0))) + { export 0:1; } + +vrint_simd_ixf: + is ((TMode=0 & c0709=0b001) + | (TMode=1 & thv_c0709=0b001)) + { $(FPEXC_IXF) = FPConvertInexact(); } + +vrint_simd_ixf: + is ((TMode=0 & ( c0707=1 | c0808=1 | c0909=0)) + | (TMode=1 & ( thv_c0707=1 | thv_c0808=1 | thv_c0909=0))) + { } + + +# F6.1.199,201,203,205,208,210 p8396,8400,8404,8408,8414,8420 Q = 0 (c0606) +:vrint^vrint_simd_RM^".f32" Dd,Dm + is ((TMode=0 & c2331=0b111100111 & c2021=0b11 & c1819=0b10 & c1617=0b10 & c1011=0b01 & (( c0707=0 & c0909=0) | ( c0707=1 & c0909=1) | ( c0707=1 & c0909=0)) & c0404=0 & c0606=0) + | (TMode=1 & thv_c2331=0b111111111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b10 & thv_c1011=0b01 & ((thv_c0707=0 & thv_c0909=0) | (thv_c0707=1 & thv_c0909=1) | (thv_c0707=1 & thv_c0909=0)) & thv_c0404=0 & thv_c0606=0)) + & vrint_simd_RM & vrint_simd_exact & vrint_simd_ixf & Dd & Dm + { Dd = FPRoundInt(Dm, 32:1, vrint_simd_RM, 0:1); build vrint_simd_ixf; } + +# F6.1.199,201,203,205,208,210 p8396,8400,8404,8408,8414,8420 Q = 1 (c0606) +:vrint^vrint_simd_RM^".f32" Qd,Qm + is ((TMode=0 & c2331=0b111100111 & c2021=0b11 & c1819=0b10 & c1617=0b10 & c1011=0b01 & c0404=0 & c0606=1) + | (TMode=1 & thv_c2331=0b111111111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b10 & thv_c1011=0b01 & thv_c0404=0 & thv_c0606=1)) + & vrint_simd_RM & vrint_simd_exact & vrint_simd_ixf & Qd & Qm + { Qd = FPRoundInt(Qm, 32:1, vrint_simd_RM, 0:1); build vrint_simd_ixf; } + +vrint_fp_RM: "a" + is ((TMode=0 & c1617=0b00) + | (TMode=1 & thv_c1617=0b00)) + { export $(FPRounding_TIEAWAY); } + +vrint_fp_RM: "m" + is ((TMode=0 & c1617=0b11) + | (TMode=1 & thv_c1617=0b11)) + { export $(FPRounding_NEGINF); } + +vrint_fp_RM: "n" + is ((TMode=0 & c1617=0b01) + | (TMode=1 & thv_c1617=0b01)) + { export $(FPRounding_TIEEVEN); } + +vrint_fp_RM: "p" + is ((TMode=0 & c1617=0b10) + | (TMode=1 & thv_c1617=0b10)) + { export $(FPRounding_POSINF); } + +# F6.1.200,202,204,206 p8398,8402,8406,8410 size = 10 (c0809) +:vrint^vrint_fp_RM^".f32" Sd,Sm + is ((TMode=0 & ARMcond=0 & c2331=0b111111101 & c1821=0b1110 & c1011=0b10 & c0607=0b01 & c0404=0 & c0809=0b10) + | (TMode=1 & thv_c2331=0b111111101 & thv_c1821=0b1110 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c0809=0b10)) + & vrint_fp_RM & Sd & Sm + { Sd = FPRoundInt(Sm, 32:1, vrint_fp_RM, 0:1); } + +# F6.1.200,202,204,206 p8398,8402,8406,8410 size = 11 (c0809) +:vrint^vrint_fp_RM^".f64" Dd,Dm + is ((TMode=0 & ARMcond=0 & c2331=0b111111101 & c1821=0b1110 & c1011=0b10 & c0607=0b01 & c0404=0 & c0809=0b11) + | (TMode=1 & thv_c2331=0b111111101 & thv_c1821=0b1110 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c0809=0b11)) + & vrint_fp_RM & Dd & Dm + { Dd = FPRoundInt(Dm, 32:1, vrint_fp_RM, 0:1); } + +vrint_rxz_RM: "r" + is ((TMode=0 & c1616=0 & c0707=0) + | (TMode=1 & thv_c1616=0 & thv_c0707=0)) + { tmp:1 = $(FPSCR_RMODE); export tmp; } + +vrint_rxz_RM: "x" + is ((TMode=0 & c1616=1 & c0707=0) + | (TMode=1 & thv_c1616=1 & thv_c0707=0)) + { tmp:1 = $(FPSCR_RMODE); export tmp; } + +vrint_rxz_RM: "z" + is ((TMode=0 & c1616=0 & c0707=1) + | (TMode=1 & thv_c1616=0 & thv_c0707=1)) + { export $(FPRounding_ZERO); } + +# For vrintx, the exact flag is 1, and the IXF flag is set (inexact) + +vrint_rxz_exact: "x" + is ((TMode=0 & c1616=1 & c0707=0) + | (TMode=1 & thv_c1616=1 & thv_c0707=0)) + { export 1:1; } + +vrint_rxz_exact: + is ((TMode=0 & ( c1616=0 | c0707=1)) + | (TMode=1 & (thv_c1616=0 | thv_c0707=1))) + { export 0:1; } + +vrint_rxz_ixf: + is ((TMode=0 & c1616=1 & c0707=0) + | (TMode=1 & thv_c1616=1 & thv_c0707=0)) + { $(FPEXC_IXF) = FPConvertInexact(); } + +vrint_rxz_ixf: + is ((TMode=0 & ( c1616=0 | c0707=1)) + | (TMode=1 & (thv_c1616=0 | thv_c0707=1))) + { } + +# F6.1.207,209,211 p8412,8416,8420 A1 size = 10 (c0809) +:vrint^vrint_rxz_RM^COND^".f32" Sd,Sm + is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b110 & c1718=0b11 & c1011=0b10 & c0606=1 & c0404=0 & (( c1616=0) | ( c1616=1 & c0707=0)) & c0809=0b10) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b110 & thv_c1718=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & ((thv_c1616=0) | (thv_c1616=1 & thv_c0707=0)) & thv_c0809=0b10)) + & vrint_rxz_RM & vrint_rxz_exact & vrint_rxz_ixf & COND & Sd & Sm + { build COND; Sd = FPRoundInt(Sm, 32:1, vrint_rxz_RM, vrint_rxz_exact); build vrint_rxz_ixf; } + +# F6.1.207,209,211 p8412,8416,8420 A1 size = 11 (c0809) +:vrint^vrint_rxz_RM^COND^".f64" Dd,Dm + is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b110 & c1718=0b11 & c1011=0b10 & c0606=1 & c0404=0 & (( c1616=0) | ( c1616=1 & c0707=0)) & c0809=0b11) + | (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b110 & thv_c1718=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & ((thv_c1616=0) | (thv_c1616=1 & thv_c0707=0)) & thv_c0809=0b11)) + & vrint_rxz_RM & vrint_rxz_exact & vrint_rxz_ixf & COND & Dd & Dm + { build COND; Dd = FPRoundInt(Dm, 32:1, vrint_rxz_RM, vrint_rxz_exact); build vrint_rxz_ixf; } + +####### +# VSEL + +vselcond: "eq" + is ((TMode=0 & c2021=0b00) + | (TMode=1 & thv_c2021=0b00)) + { tmp:1 = ZR; export tmp; } +vselcond: "ge" + is ((TMode=0 & c2021=0b10) + | (TMode=1 & thv_c2021=0b10)) + { tmp:1 = (NG==OV); export tmp; } +vselcond: "gt" + is ((TMode=0 & c2021=0b11) + | (TMode=1 & thv_c2021=0b11)) + { tmp:1 = (!ZR); export tmp; } +vselcond: "vs" + is ((TMode=0 & c2021=0b01) + | (TMode=1 & thv_c2021=0b01)) + { tmp:1 = OV; export tmp; } + +# F6.1.223 p8447 A1/T1 size = 11 doubleprec (c0809) +:vsel^vselcond^".f64" Dd,Dn,Dm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11100 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b11) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11100 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b11)) + & vselcond & Dn & Dd & Dm + { Dd = zext(vselcond != 0) * Dn + zext(vselcond == 0) * Dm; } + +# F6.1.223 p8447 A1/T1 size = 10 singleprec (c0809) +:vsel^vselcond".f32" Sd,Sn,Sm + is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11100 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b10) + | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11100 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b10)) + & vselcond & Sn & Sd & Sm + { Sd = zext(vselcond != 0) * Sn + zext(vselcond == 0) * Sm; } + +@endif # INCLUDE_NEON diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/old/ARMv5.lang b/python/icicle/Ghidra/Processors/ARM/data/languages/old/ARMv5.lang new file mode 100644 index 0000000..03ce014 --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/old/ARMv5.lang @@ -0,0 +1,62 @@ + + + + ARM:LE:32:DEPRECATED ARM V5 + ARM + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/old/ARMv5.trans b/python/icicle/Ghidra/Processors/ARM/data/languages/old/ARMv5.trans new file mode 100644 index 0000000..9c8858d --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/old/ARMv5.trans @@ -0,0 +1,6 @@ + + + Sleigh-ARMv5 + ARM:LE:32:v5 + + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/old/THUMBv2.lang b/python/icicle/Ghidra/Processors/ARM/data/languages/old/THUMBv2.lang new file mode 100644 index 0000000..773cc61 --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/old/THUMBv2.lang @@ -0,0 +1,55 @@ + + + + ARM:LE:32:DEPRECATED THUMB V2 + ARM + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/ARM/data/languages/old/THUMBv2.trans b/python/icicle/Ghidra/Processors/ARM/data/languages/old/THUMBv2.trans new file mode 100644 index 0000000..781a37a --- /dev/null +++ b/python/icicle/Ghidra/Processors/ARM/data/languages/old/THUMBv2.trans @@ -0,0 +1,11 @@ + + + Sleigh-THUMBv2 + ARM:LE:32:v5t + + + + + diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/atmega256.pspec b/python/icicle/Ghidra/Processors/Atmel/data/languages/atmega256.pspec new file mode 100644 index 0000000..b7d0b8f --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/atmega256.pspec @@ -0,0 +1,422 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32.opinion b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32.opinion new file mode 100644 index 0000000..f87fb3b --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32.opinion @@ -0,0 +1,6 @@ + + + + + + diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a.cspec b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a.cspec new file mode 100644 index 0000000..5f87ebf --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a.cspec @@ -0,0 +1,53 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a.ldefs b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a.ldefs new file mode 100644 index 0000000..cb7f471 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a.ldefs @@ -0,0 +1,17 @@ + + + + + Generic AVR32-A big-endian + + + + diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a.pspec b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a.pspec new file mode 100644 index 0000000..52ebcca --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a.pspec @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a.slaspec b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a.slaspec new file mode 100644 index 0000000..7830fae --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a.slaspec @@ -0,0 +1,713 @@ +define endian=big; +define alignment=2; + +define space RAM type=ram_space size=4 default; + +define space register type=register_space size=2; + +# for the AVR32A +define register offset=0x0000 size=4 [ + + SR EVBA ACBA CPUCR ECR RSR_SUP RSR_INT0 RSR_INT1 + RSR_INT2 RSR_INT3 RSR_EX RSR_NMI RSR_DBG RAR_SUP RAR_INT0 RAR_INT1 + RAR_INT2 RAR_INT3 RAR_EX RAR_NMI RAR_DBG JECR JOSP JAVA_LV0 + JAVA_LV1 JAVA_LV2 JAVA_LV3 JAVA_LV4 JAVA_LV5 JAVA_LV6 JAVA_LV7 JTBA + JBCR +]; + +define register offset=0x0100 size=4 [ + CONFIG0 CONFIG1 COUNT COMPARE TLBEHI TLBELO PTBR TLBEAR + MMUCR TLBARLO TLBARHI PCCNT PCNT0 PCNT1 PCCR BEAR + MPUAR0 MPUAR1 MPUAR2 MPUAR3 MPUAR4 MPUAR5 MPUAR6 MPUAR7 + MPUPSR0 MPUPSR1 MPUPSR2 MPUPSR3 MPUPSR4 MPUPSR5 MPUPSR6 MPUPSR7 + MPUCRA MPUCRB MPUBRA MPUBRB MPUAPRA MPUAPRB MPUCR SS_STATUS + SS_ADRF SS_ADRR SS_ADR0 SS_ADR1 SS_SP_SYS SS_SP_APP SS_RAR SS_RSR +]; + +# 103-191 reserved for future use +# 192-255 implementation defined + +define register offset=0x1000 size=4 [ + R0 R1 R2 R3 R4 R5 R6 R7 + R8 R9 R10 R11 R12 SP LR PC +]; + +define register offset=0x1100 size=1 [ + C Z N V Q L _ _ _ _ _ _ _ _ T R + GM I0M I1M I2M I3M EM M0 M1 M2 _ D DM J H _ _ + ALWAYS_TRUE +]; + +macro SRTOLOWFLAGS() { + C = (SR & 0x1) != 0; + Z = (SR & 0x2) != 0; + N = (SR & 0x4) != 0; + V = (SR & 0x8) != 0; +} + +macro SRTOFLAGS() { + C = (SR & 0x1) != 0; + Z = (SR & 0x2) != 0; + N = (SR & 0x4) != 0; + V = (SR & 0x8) != 0; + Q = (SR & 0x10) != 0; + L = (SR & 0x20) != 0; + T = (SR & 0x4000) != 0; + R = (SR & 0x8000) != 0; + GM = (SR & 0x10000) != 0; + I0M = (SR & 0x20000) != 0; + I1M = (SR & 0x40000) != 0; + I2M = (SR & 0x80000) != 0; + I3M = (SR & 0x100000) != 0; + EM = (SR & 0x200000) != 0; + M0 = (SR & 0x400000) != 0; + M1 = (SR & 0x800000) != 0; + M2 = (SR & 0x1000000) != 0; + D = (SR & 0x4000000) != 0; + DM = (SR & 0x8000000) != 0; + J = (SR & 0x10000000) != 0; + H = (SR & 0x20000000) != 0; +} + +macro CZNVTOSR() { + tmp:4 = zext(C&1) | (zext(Z&1) << 1) | (zext(N&1) << 2) | (zext(V&1) << 3); + SR = (SR & 0xFFFFFFF0) | tmp; +} + +macro CZNVQTOSR() { + tmp:4 = zext(C&1) | (zext(Z&1) << 1) | (zext(N&1) << 2) | (zext(V&1) << 3) | (zext(Q&1) << 4); + SR = (SR & 0xFFFFFFE0) | tmp; +} + +macro QTOSR() { + SR = (SR & 0xFFFFFFEF) | (zext(Q&1) << 4); +} + +macro CZTOSR() { + tmp:4 = zext(C&1) | (zext(Z&1) << 1); + SR = (SR & 0xFFFFFFFC) | tmp; +} + +macro JRGMTOSR() { + tmp:4 = (zext(R&1) << 15) | (zext(GM&1) << 16) | (zext(J&1) << 28); + SR = (SR & 0xEFFFFE7F) | tmp; +} + +macro LTOSR() { + tmp:4 = zext(L&1) << 5; + SR = (SR & 0xFFFFFFDF) | tmp; +} + +define register offset=0x1200 size=4 [ + stadd ldadd +]; + +define register offset=0x1300 size=4 contextreg; +define context contextreg + ctx_rel10=(0,9) signed noflow + ctx_rel8_2=(0,1) noflow + ctx_rel0_8=(2,9) noflow + ctx_rel21=(0,20) signed noflow + ctx_rel0_16=(5,20) noflow + ctx_rel16_1=(4,4) noflow + ctx_rel17_4=(0,3) noflow + ctx_rel3=(0,2) signed noflow + ctx_savex=(0,3) noflow + ctx_usex=(0,3) noflow + ctx_savey=(4,7) noflow + ctx_usey=(4,7) noflow + ctx_useu=(4,7) noflow + ctx_shift=(0,4) noflow + ctx_shigh=(0,3) noflow + ctx_slow=(4,4) noflow + ctx_coop=(0,6) noflow + ctx_cohi=(0,1) noflow + ctx_comid=(2,5) noflow + ctx_colow=(6,6) noflow + ctx_rdplus=(8,11) noflow + ctx_rdsave=(8,11) noflow +; + +define token instr1(16) + op13_3 = (13,15) + op11_5 = (11, 15) + op0_3 = (0, 2) + rs9 = (9,12) + rp9 = (9,12) + rb9 = (9,12) + rx9 = (9,12) + op9_4 = (9,12) + op9_7 = (9,15) + op9_2 = (9,10) + op7_9 = (7,15) + op7_2 = (7,8) + op4_5 = (4,8) + op4_12 = (4,15) + op9_1 = (9,9) + op8_1 = (8,8) + op8_8 = (8,15) + op0_9 = (0,8) + b9 = (9,9) + op10_6 = (10,15) + disp4_3 = (4,6) + disp4_5 = (4,8) + disp4_7 = (4,10) + disp4_4 = (4,7) + rs0 = (0,3) + rs0_hi = (1,3) + rs0_low = (1,3) + rd0_hi = (1,3) + rd0_low = (1,3) + rp0 = (0,3) + rd0 = (0,3) + rd9 = (9,12) + ri0 = (0,3) + rb0 = (0,3) + ry0 = (0,3) + b0 = (0,0) + b02 = (2,2) + b03 = (3,3) + b04 = (4,4) + b05 = (5,5) + b06 = (6,6) + b07 = (7,7) + b08 = (8,8) + b09 = (9,9) + b10 = (10,10) + b11 = (11,11) + bp9_4 = (9,12) + bp4_1 = (4,4) + bp4_2 = (4,5) + bp4_3 = (4,6) + bp4_4 = (4,7) + bp4_5 = (4,8) + bp4_6 = (4,9) + bp4_7 = (4,10) + cond4_4 = (4,7) + cond0_4 = (0,3) + cond0_3 = (0,2) + imm4_8 = (4,11) signed + imm4_6 = (4,9) signed + imm4_5 = (4,8) + op12_1 = (12,12) + op5_4 = (5,8) + imm9_4 = (9,12) signed + imm4_1 = (4,4) + imm0_4 = (0,3) + b003 = (0,3) + disp4_8 = (4,11) + sdisp4_8 = (4,11) signed + op3_1 = (3,3) + op3_6 = (3,8) + disp21part2_4_1 = (4,4) + disp21part3_9_4 = (9,12) signed + shift9_4 = (9,12) + shift4_1 = (4,4) + op12_4 = (12,15) + op0_4 = (0,3) + disp0_2 = (0,1) + sdisp0_2 = (0,1) signed + op2_2 = (2,3) + op0_16 = (0,15) + sa0_3 = (0,2) + sa0_4 = (0,3) + coh = (9,9) +; + +define token instr2(16) + ecop13_3 = (13,15) + disp_16 = (0,15) signed + ddisp_16 = (0,15) signed + disp_9 = (0,8) + disp_8 = (0,7) + disp12_4 = (12,15) + disp0_11 = (0,10) signed + disp0_12 = (0,11) signed + edisp4_8 = (4,11) + eop14_2 = (14,15) + eop11_5 = (11,15) + eop12_4 = (12,15) + eop6_10 = (6,15) + eop8_4 = (8,11) + eop6_2 = (6,7) + eop5_3 = (5,7) + eop9_3 = (9,11) + eop8_8 = (8,15) + eop0_9 = (0,8) + eop0_4 = (0,3) + eop9_7 = (9,15) + eop12_1 = (12,12) + eop5_11 = (5,15) + eop0_8 = (0,7) + eop0_16 = (0,15) + eop4_12 = (4,15) + eop4_8 = (4,11) + eop4_4 = (4,7) + eop10_6 = (10,15) + eoff5_5 = (5,9) + eoff0_5 = (0,4) + elen0_5 = (0,4) + eop10_2 = (10,11) + esa0_5 = (0,4) + ebp5_5 = (5,9) + crd8_4 = (8,11) + crd9_3 = (9,11) + crx4_4 = (4,7) + cry0_4 = (0,3) + altcrd8_4 = (8,11) + altcrx4_4 = (4,7) + altcry0_4 = (0,3) + altcrd9_3 = (9,11) + crd8_1 = (8,8) + cp13_3 = (13,15) + altcp13_3 = (13,15) + shift4_2 = (4,5) + shift4_5 = (4,8) + shift0_5 = (0,4) + selectorxy4_2 = (4,5) + ers0 = (0,3) + erb0 = (0,3) + erd0 = (0,3) + erd0a = (0,3) + erp0 = (0,3) + ers0_hi = (1,3) + ers0_low = (1,3) + erd0_hi = (1,3) + erd0_low = (1,3) + econd12_4 = (12, 15) + econd8_4 = (8, 11) + econd4_4 = (4, 7) + eri8 = (8,11) + eri0 = (0,3) + eb0 = (0,0) + eb1 = (1,1) + eb2 = (2,2) + eb3 = (3,3) + eb4 = (4,4) + eb5 = (5,5) + eb6 = (6,6) + eb7 = (7,7) + eb8 = (8,8) + eb9 = (9,9) + eb10 = (10,10) + eb11 = (11,11) + eb12 = (12,12) + eb13 = (13,13) + eb14 = (14,14) + eb15 = (15,15) + ypart = (4,4) + upart = (4,4) + xpart = (5,5) + imm16 = (0,15) + simm16 = (0,15) signed + simm0_8 = (0,7) signed + imm0_8 = (0,7) + simm0_15 = (0,14) signed + imm12_2 = (12,13) + sysreg = (0,7) + dbgreg = (0,7) + disp21part1_0_16 = (0,15) + deb0 = (0,0) + deb1 = (1,1) + deb2 = (2,2) + deb3 = (3,3) + deb4 = (4,4) + deb5 = (5,5) + deb6 = (6,6) + deb7 = (7,7) + deb8 = (8,8) + deb9 = (9,9) + deb10 = (10,10) + deb11 = (11,11) + deb12 = (12,12) + deb13 = (13,13) + deb14 = (14,14) + deb15 = (15,15) +; + +attach variables [ rs9 rp9 rd9 rb9 rs0 rb0 rp0 rx9 ry0 rd0 ri0 ers0 erd0 erb0 eri0 erp0 eri8 ctx_rdplus ctx_usex ctx_usey] [ + R0 R1 R2 R3 R4 R5 R6 R7 + R8 R9 R10 R11 R12 SP LR PC +]; + +attach variables [ rs0_hi rd0_hi erd0_hi ers0_hi ] [ + R1 R3 R5 R7 R9 R11 SP PC +]; + +attach variables [ rs0_low rd0_low erd0_low ers0_low ] [ + R0 R2 R4 R6 R8 R10 R12 LR +]; + +attach variables [ deb0 ] [ R0 R0 ]; +attach variables [ deb1 ] [ R1 R1 ]; +attach variables [ deb2 ] [ R2 R2 ]; +attach variables [ deb3 ] [ R3 R3 ]; +attach variables [ deb4 ] [ R4 R4 ]; +attach variables [ deb5 ] [ R5 R5 ]; +attach variables [ deb6 ] [ R6 R6 ]; +attach variables [ deb7 ] [ R7 R7 ]; +attach variables [ deb8 ] [ R8 R8 ]; +attach variables [ deb9 ] [ R9 R9 ]; +attach variables [ deb10 ] [ R10 R10 ]; +attach variables [ deb11 ] [ R11 R11 ]; +attach variables [ deb12 ] [ R12 R12 ]; +attach variables [ deb13 ] [ SP SP ]; +attach variables [ deb14 ] [ LR LR ]; +attach variables [ deb15 ] [ PC PC ]; + +attach variables [ sysreg] +[ + SR EVBA ACBA CPUCR ECR RSR_SUP RSR_INT0 RSR_INT1 + RSR_INT2 RSR_INT3 RSR_EX RSR_NMI RSR_DBG RAR_SUP RAR_INT0 RAR_INT1 + RAR_INT2 RAR_INT3 RAR_EX RAR_NMI RAR_DBG JECR JOSP JAVA_LV0 + JAVA_LV1 JAVA_LV2 JAVA_LV3 JAVA_LV4 JAVA_LV5 JAVA_LV6 JAVA_LV7 JTBA + JBCR _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + CONFIG0 CONFIG1 COUNT COMPARE TLBEHI TLBELO PTBR TLBEAR + MMUCR TLBARLO TLBARHI PCCNT PCNT0 PCNT1 PCCR BEAR + MPUAR0 MPUAR1 MPUAR2 MPUAR3 MPUAR4 MPUAR5 MPUAR6 MPUAR7 + MPUPSR0 MPUPSR1 MPUPSR2 MPUPSR3 MPUPSR4 MPUPSR5 MPUPSR6 MPUPSR7 + MPUCRA MPUCRB MPUBRA MPUBRB MPUAPRA MPUAPRB MPUCR SS_STATUS + SS_ADRF SS_ADRR SS_ADR0 SS_ADR1 SS_SP_SYS SS_SP_APP SS_RAR SS_RSR + _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ +]; + +# loadCoprocessorWord(CP:1, CRd:1, address:4) +define pcodeop loadCoprocessorWord; + +# loadCoprocessorDWord(CP:1, CRd:1, address:4) +define pcodeop loadCoprocessorDWord; + +define pcodeop CoProcessorDWordToReg; +define pcodeop CoProcessorWordToReg; +define pcodeop RegToCoProcessorDWord; +define pcodeop RegToCoProcessorWord; +define pcodeop storeCoprocessorDword; +define pcodeop storeCoprocessorWord; +define pcodeop CoprocessorOp; +define pcodeop LoadCoProcessorWord; +define pcodeop LoadCoProcessorDword; + +define pcodeop trap; +define pcodeop cacheOp; +define pcodeop CacheFetch; + +define pcodeop doSleep; + +define pcodeop CheckAndRestoreInterupt; +define pcodeop CheckAndRestoreSupervisor; + +define pcodeop ReadTLBEntry; +define pcodeop WriteTLBEntry; +define pcodeop SearchTLBEntry; + +define pcodeop SynchMemory; + +define pcodeop JavaTrap; +define pcodeop JavaPopContext; +define pcodeop JavaPushContext; +define pcodeop JavaCheckStack; + +define pcodeop SupervisorCallSetup; + +define pcodeop MoveToDebugReg; +define pcodeop MoveFromDebugReg; + +# conditions + +# STATUS REGISTER MAP: (LOW) +# C - CARRY +# Z - ZERO +# N - NEGATIVE +# V - OVERFLOW +# Q - SATURATION +# L - LOCK +# T - SCRATCH +# R - REMAP + +# STATUS REGISTER MAP: (HIGH) +# GM - Global Interrupt Mask +# I0M - Interrupt Level 0 Mask +# I1M - Interrupt Level 1 Mask +# I2M - Interrupt Level 2 Mask +# I3M - Interrupt Level 3 Mask +# EM - Exception Mask +# M0 - Execution Mode 0 +# M1 - Execution Mode 1 +# M2 - Execution Mode 2 +# D - Debug State +# DM - Debug State Mask +# J - Java State +# H - Java Handle + + +#Cond4 Registers Extended (12,15) +cc4_e12: "EQ" is econd12_4=0x0 { export Z; } +cc4_e12: "NE" is econd12_4=0x1 { tmp:1 = !Z; export tmp; } +cc4_e12: "HS" is econd12_4=0x2 { tmp:1 = !C; export tmp; } +cc4_e12: "LO" is econd12_4=0x3 { export C; } +cc4_e12: "GE" is econd12_4=0x4 { tmp:1 = N == V; export tmp;} +cc4_e12: "LT" is econd12_4=0x5 { tmp:1 = N!=V; export tmp; } +cc4_e12: "MI" is econd12_4=0x6 { export N; } +cc4_e12: "PL" is econd12_4=0x7 { tmp:1 = !N; export tmp; } +cc4_e12: "LS" is econd12_4=0x8 { tmp:1 = C || Z; export tmp; } +cc4_e12: "GT" is econd12_4=0x9 { tmp:1 = !Z && (N == V); export tmp; } +cc4_e12: "LE" is econd12_4=0xa { tmp:1 = Z || (N!=V); export tmp; } +cc4_e12: "HI" is econd12_4=0xb { tmp:1 = !C && !Z; export tmp; } +cc4_e12: "VS" is econd12_4=0xc { export V; } +cc4_e12: "VC" is econd12_4=0xd { tmp:1 = !V; export tmp; } +cc4_e12: "QS" is econd12_4=0xe { export Q; } +cc4_e12: "AL" is econd12_4=0xf { export ALWAYS_TRUE; } + +COND_e12: cc4_e12 is cc4_e12 { if (!cc4_e12) goto inst_next; } +COND_e12: cc4_e12 is cc4_e12 & econd12_4=0xf { } + +#Cond4 Registers Extended (4,7) +cc4_4: "EQ" is cond4_4=0x0 { export Z; } +cc4_4: "NE" is cond4_4=0x1 { tmp:1 = !Z; export tmp; } +cc4_4: "HS" is cond4_4=0x2 { tmp:1 = !C; export tmp; } +cc4_4: "LO" is cond4_4=0x3 { export C; } +cc4_4: "GE" is cond4_4=0x4 { tmp:1 = N == V; export tmp;} +cc4_4: "LT" is cond4_4=0x5 { tmp:1 = N!=V; export tmp; } +cc4_4: "MI" is cond4_4=0x6 { export N; } +cc4_4: "PL" is cond4_4=0x7 { tmp:1 = !N; export tmp; } +cc4_4: "LS" is cond4_4=0x8 { tmp:1 = C || Z; export tmp; } +cc4_4: "GT" is cond4_4=0x9 { tmp:1 = !Z && (N == V); export tmp; } +cc4_4: "LE" is cond4_4=0xa { tmp:1 = Z || (N!=V); export tmp; } +cc4_4: "HI" is cond4_4=0xb { tmp:1 = !C && !Z; export tmp; } +cc4_4: "VS" is cond4_4=0xc { export V; } +cc4_4: "VC" is cond4_4=0xd { tmp:1 = !V; export tmp; } +cc4_4: "QS" is cond4_4=0xe { export Q; } +cc4_4: "AL" is cond4_4=0xf { export ALWAYS_TRUE; } + +COND_4_4: cc4_4 is cc4_4 { if (!cc4_4) goto inst_next; } +COND_4_4: cc4_4 is cc4_4 & cond4_4=0xf { } + +#Cond4 Registers Extended (4,7) +ecc4_4: "EQ" is econd4_4=0x0 { export Z; } +ecc4_4: "NE" is econd4_4=0x1 { tmp:1 = !Z; export tmp; } +ecc4_4: "HS" is econd4_4=0x2 { tmp:1 = !C; export tmp; } +ecc4_4: "LO" is econd4_4=0x3 { export C; } +ecc4_4: "GE" is econd4_4=0x4 { tmp:1 = N == V; export tmp;} +ecc4_4: "LT" is econd4_4=0x5 { tmp:1 = N!=V; export tmp; } +ecc4_4: "MI" is econd4_4=0x6 { export N; } +ecc4_4: "PL" is econd4_4=0x7 { tmp:1 = !N; export tmp; } +ecc4_4: "LS" is econd4_4=0x8 { tmp:1 = C || Z; export tmp; } +ecc4_4: "GT" is econd4_4=0x9 { tmp:1 = !Z && (N == V); export tmp; } +ecc4_4: "LE" is econd4_4=0xa { tmp:1 = Z || (N!=V); export tmp; } +ecc4_4: "HI" is econd4_4=0xb { tmp:1 = !C && !Z; export tmp; } +ecc4_4: "VS" is econd4_4=0xc { export V; } +ecc4_4: "VC" is econd4_4=0xd { tmp:1 = !V; export tmp; } +ecc4_4: "QS" is econd4_4=0xe { export Q; } +ecc4_4: "AL" is econd4_4=0xf { export ALWAYS_TRUE; } + +ECOND_4_4: ecc4_4 is ecc4_4 { if (!ecc4_4) goto inst_next; } +ECOND_4_4: ecc4_4 is ecc4_4 & econd4_4=0xf { } + +#Cond4 Registers Extended (4,7) +ecc8_4: "EQ" is econd8_4=0x0 { export Z; } +ecc8_4: "NE" is econd8_4=0x1 { tmp:1 = !Z; export tmp; } +ecc8_4: "HS" is econd8_4=0x2 { tmp:1 = !C; export tmp; } +ecc8_4: "LO" is econd8_4=0x3 { export C; } +ecc8_4: "GE" is econd8_4=0x4 { tmp:1 = N == V; export tmp;} +ecc8_4: "LT" is econd8_4=0x5 { tmp:1 = N!=V; export tmp; } +ecc8_4: "MI" is econd8_4=0x6 { export N; } +ecc8_4: "PL" is econd8_4=0x7 { tmp:1 = !N; export tmp; } +ecc8_4: "LS" is econd8_4=0x8 { tmp:1 = C || Z; export tmp; } +ecc8_4: "GT" is econd8_4=0x9 { tmp:1 = !Z && (N == V); export tmp; } +ecc8_4: "LE" is econd8_4=0xa { tmp:1 = Z || (N!=V); export tmp; } +ecc8_4: "HI" is econd8_4=0xb { tmp:1 = !C && !Z; export tmp; } +ecc8_4: "VS" is econd8_4=0xc { export V; } +ecc8_4: "VC" is econd8_4=0xd { tmp:1 = !V; export tmp; } +ecc8_4: "QS" is econd8_4=0xe { export Q; } +ecc8_4: "AL" is econd8_4=0xf { export ALWAYS_TRUE; } + +ECOND_8_4: ecc8_4 is ecc8_4 { if (!ecc8_4) goto inst_next; } +ECOND_8_4: ecc8_4 is ecc8_4 & econd8_4=0xf { } + +#Cond3 Registers(0 - 2) +cc3_0: "eq" is cond0_3=0x0 { export Z; } +cc3_0: "ne" is cond0_3=0x1 { tmp:1 = !Z; export tmp; } +cc3_0: "cc/hs" is cond0_3=0x2 { tmp:1 = !C; export tmp; } +cc3_0: "cc/lo" is cond0_3=0x3 { export C; } +cc3_0: "ge" is cond0_3=0x4 { tmp:1 = N == V; export tmp;} +cc3_0: "lt" is cond0_3=0x5 { tmp:1 = N!=V; export tmp; } +cc3_0: "mi" is cond0_3=0x6 { export N; } +cc3_0: "pl" is cond0_3=0x7 { tmp:1 = !N; export tmp; } + +COND_3: cc3_0 is cc3_0 { export cc3_0; } + +#Cond4 Registers(0 - 3) +cc4_0: "eq" is cond0_4=0x0 { export Z; } +cc4_0: "ne" is cond0_4=0x1 { tmp:1 = !Z; export tmp; } +cc4_0: "cc/hs" is cond0_4=0x2 { tmp:1 = !C; export tmp; } +cc4_0: "cc/lo" is cond0_4=0x3 { export C; } +cc4_0: "ge" is cond0_4=0x4 { tmp:1 = N == V; export tmp;} +cc4_0: "lt" is cond0_4=0x5 { tmp:1 = N!=V; export tmp; } +cc4_0: "mi" is cond0_4=0x6 { export N; } +cc4_0: "pl" is cond0_4=0x7 { tmp:1 = !N; export tmp; } +cc4_0: "ls" is cond0_4=0x8 { tmp:1 = C || Z; export tmp; } +cc4_0: "gt" is cond0_4=0x9 { tmp:1 = !Z && (N == V); export tmp; } +cc4_0: "le" is cond0_4=0xa { tmp:1 = Z || (N!=V); export tmp; } +cc4_0: "hi" is cond0_4=0xb { tmp:1 = !C && !Z; export tmp; } +cc4_0: "vs" is cond0_4=0xc { export V; } +cc4_0: "vc" is cond0_4=0xd { tmp:1 = !V; export tmp; } +cc4_0: "qs" is cond0_4=0xe { export Q; } +cc4_0: "al" is cond0_4=0xf { export ALWAYS_TRUE; } + +COND_4_0: cc4_0 is cc4_0 { if (!cc4_0) goto inst_next; } +COND_4_0: cc4_0 is cc4_0 & cond0_4=0xf { } + +RP9bInc: rp9++ is rp9 { ptr:4 = rp9; rp9 = rp9 + 1; export ptr; } +RPhInc: rp9++ is rp9 { ptr:4 = rp9; rp9 = rp9 + 2; export ptr; } +RPwInc: rp9++ is rp9 { ptr:4 = rp9; rp9 = rp9 + 4; export ptr; } +RPdInc: rp9++ is rp9 { ptr:4 = rp9; rp9 = rp9 + 8; export ptr; } + +RP9bDec: --rp9 is rp9 { rp9 = rp9 - 1; ptr:4 = rp9; export ptr; } +RPhDec: --rp9 is rp9 { rp9 = rp9 - 2; ptr:4 = rp9; export ptr; } +RPwDec: --rp9 is rp9 { rp9 = rp9 - 4; ptr:4 = rp9; export ptr; } +RPdDec: --rp9 is rp9 { rp9 = rp9 - 8; ptr:4 = rp9; export ptr; } + +RPwDec0: --rp0 is rp0 { rp0 = rp0 - 4; ptr:4 = rp0; export ptr; } +RPdDec0: --rp0 is rp0 { rp0 = rp0 - 8; ptr:4 = rp0; export ptr; } + +RPbDisp3: rp9[disp4_3] is rp9 & disp4_3 { ptr:4 = rp9 + disp4_3; export ptr; } + +RPhDisp3: rp9[disp] is rp9 & disp4_3 +[ disp = disp4_3 << 1; ] +{ ptr:4 = rp9 + disp; export ptr; } + +RPwDisp4: rp9[disp] is rp9 & disp4_4 +[ disp = disp4_4 << 2; ] +{ ptr:4 = rp9 + disp; export ptr; } + +RPwDisp5: rp9[disp] is rp9 & disp4_5 +[ disp = disp4_5 << 2; ] +{ ptr:4 = rp9 + disp; export ptr; } + +RPwDisp8: rp0[disp] is rp0; disp_8 +[ disp = disp_8 << 2; ] +{ ptr:4 = rp0 + disp; export ptr; } + +RPbDisp9: rp9[disp_9] is rp9; disp_9 { ptr:4 = rp9 + disp_9; export ptr; } + +RPhDisp9: rp9[disp] is rp9; disp_9 +[ disp = disp_9 << 1; ] +{ ptr:4 = rp9 + disp; export ptr; } + +RPwDisp9: rp9[disp] is rp9; disp_9 +[ disp = disp_9 << 2; ] +{ ptr:4 = rp9 + disp; export ptr; } + +RPwDisp12: rp0[disp] is rp0; disp12_4 & disp_8 +[ disp = ((disp12_4 << 8) | disp_8) << 2; ] +{ ptr:4 = rp0 + disp; export ptr; } + +PCDisp16: loc is disp_16 [ loc = inst_start + disp_16; ] { export *[const]:4 loc; } + +RPDisp16: rp9[disp_16] is rp9; disp_16 { ptr:4 = rp9 + disp_16; export ptr; } +RPDisp16: PC[disp_16] is rp9=15 & PC; disp_16 & PCDisp16 { export PCDisp16; } + +RB9Shift: rb9[ri0 "<<" shift4_2] is rb9 & ri0; shift4_2 { ptr:4 = rb9 + (ri0 << shift4_2); export ptr; } + +RBShift0: rb0[eri0 "<<" shift4_2] is rb0; eri0 & shift4_2 { ptr:4 = rb0 + (eri0 << shift4_2); export ptr; } + +RBSelector: rb9[ri0" << 2]" is rb9 & ri0; selectorxy4_2=0x0 { ptr:4 = rb9 + ((ri0 & 0xff) << 0x02); export ptr; } +RBSelector: rb9[ri0" << 2]" is rb9 & ri0; selectorxy4_2=0x1 { ptr:4 = rb9 + (((ri0 >> 8) & 0xff) << 0x02); export ptr; } +RBSelector: rb9[ri0" << 2]" is rb9 & ri0; selectorxy4_2=0x2 { ptr:4 = rb9 + (((ri0 >> 16) & 0xff) << 0x02); export ptr; } +RBSelector: rb9[ri0" << 2]" is rb9 & ri0; selectorxy4_2=0x3 { ptr:4 = rb9 + (((ri0 >> 24) & 0xff) << 0x02); export ptr; } + +RS0A: rs0 is rs0 { export rs0; } +RS0A: rs0 is rs0 & rs0=0xf { export *[const]:4 inst_start; } + +RS9A: rs9 is rs9 { export rs9; } +RS9A: rs9 is rs9 & rs9=0xf { export *[const]:4 inst_start; } + +RX9A: rx9 is rx9 { export rx9; } +RX9A: rx9 is rx9 & rx9=0xf { export *[const]:4 inst_start; } + +RY0A: ry0 is ry0 { export ry0; } +RY0A: ry0 is ry0 & ry0=0xf { export *[const]:4 inst_start; } + +RD0A: rd0 is rd0 { export rd0; } +RD0A: rd0 is rd0 & rd0=0xf { export *[const]:4 inst_start; } + +macro ZSTATUS(RES) { + Z = RES == 0; + CZNVTOSR(); +} + +macro NZSTATUS(RES) { + N = RES s< 0; + ZSTATUS(RES); + CZNVTOSR(); +} + +macro addflags(OP1, OP2, RES) { + + ## The REAL way to do it (in the processor spec) + #V = (OP1[31,1] && OP2[31,1] && !(RES[31,1])) || + # (!(OP1[31,1]) && !(OP2[31,1]) && RES[31,1]); + + V = scarry(OP1, OP2); + + NZSTATUS(RES); + + ## The REAL way to do it (in the processor spec) + #C = (OP1[31,1] && OP2[31,1]) || + # (OP1[31,1] && !(RES[31,1])) || + # (OP2[31,1] && !(RES[31,1])); + + C = carry(OP1, OP2); + CZNVTOSR(); +} + +macro subflags(OP1, OP2, RES) { + + ## The REAL way to do it (in the processor spec) + #V = (OP1[31,1] && !(OP2[31,1]) && !(RES[31,1])) || + # (!(OP1[31,1]) && OP2[31,1] && RES[31,1]); + + V = sborrow(OP1, OP2); + + NZSTATUS(RES); + + ## The REAL way to do it (in the processor spec) + #C = (!(OP1[31,1]) && (OP2[31,1])) || + # (OP2[31,1] && RES[31,1]) || + # (!(OP1[31,1]) && RES[31,1]); + + C = OP1 < OP2; + CZNVTOSR(); +} + +@include "avr32a_arithmetic_operations.sinc" +@include "avr32a_multiplication_operations.sinc" +@include "avr32a_logic_operations.sinc" +@include "avr32a_bit_operations.sinc" +@include "avr32a_shift_operations.sinc" +@include "avr32a_data_transfer.sinc" +@include "avr32a_system_control.sinc" +@include "avr32a_coprocessor_interface.sinc" +@include "avr32a_instruction_flow.sinc" +@include "avr32a_simd_operations.sinc" +@include "avr32a_dsp_operations2.sinc" diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_arithmetic_operations.sinc b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_arithmetic_operations.sinc new file mode 100644 index 0000000..2d120eb --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_arithmetic_operations.sinc @@ -0,0 +1,733 @@ +#--------------------------------------------------------------------- +# 8.3.2 Arithmetic Operations +#--------------------------------------------------------------------- +macro cpcflags(OP1, OP2, RES) { + + ## The REAL way to do it (in the processor spec) + #V = (OP1[31,1] && !(OP2[31,1]) && !(RES[31,1])) || + # (!(OP1[31,1]) && OP2[31,1] && RES[31,1]); + + V = sborrow(OP1, OP2); + + N = RES s< 0; + Z = RES == 0 & Z; + + ## The REAL way to do it (in the processor spec) + C = (!(OP1[31,1]) && (OP2[31,1])) || + (OP2[31,1] && RES[31,1]) || + (!(OP1[31,1]) && RES[31,1]); + + #C = OP1 < OP2; + CZNVTOSR(); +} + +# DUPLICATE CPCFLAGS TO ACCOUNT FOR OP2 == 0 +macro cpcflags0(OP1, RES) { + + ## The REAL way to do it (in the processor spec) + #V = (OP1[31,1] && !(OP2[31,1]) && !(RES[31,1])) || + # (!(OP1[31,1]) && OP2[31,1] && RES[31,1]); + + V = sborrow(OP1, 0); + + N = RES s< 0; + Z = RES == 0 & Z; + + ## The REAL way to do it (in the processor spec) + #C = (!(OP1[31,1]) && (OP2[31,1])) || + # (OP2[31,1] && RES[31,1]) || + # (!(OP1[31,1]) && RES[31,1]); + + C = 0; + CZNVTOSR(); +} + +macro acrflags(OP1, tmpC, RES) { + ## The REAL way to do it (in the processor spec) + # V = RES[31,1] && !Rd[31,1]; + V = scarry(OP1, tmpC); + N = RES s< 0; + Z = ((RES == 0) && Z); + ## The REAL way to do it (in the processor spec) + # C = RES[31,1] && Rd[31,1]; + C = carry(OP1, tmpC); + CZNVTOSR(); +} +#--------------------------------------------------------------------- +# ABS - Absolute Value +# I. {d, s} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- +#ABS Format I +# Operation: Rd <- abs(Rd); +# Syntax: abs Rd +# 010 1110 00100 dddd (Opcode Form) +# 0101 1100 0100 dddd (Byte half Form) +:ABS rd0 is rd0 & op13_3=0x2 & op9_4=0xe & op4_5=0x4 { + local ztst:1 = rd0 s< 0; + rd0 = (zext(!ztst)*rd0) + (zext(ztst)*(-rd0)); + ZSTATUS(rd0); +} + + +#--------------------------------------------------------------------- +# ACR - Add carry to register +# I. {d, s} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- +#ACR Format I +# Operation: Rd <- Rd + C; +# Syntax: acr Rd +# 010 1110 00000 dddd (Opcode Form) +# 0101 1100 0000 dddd (Byte half Form) +:ACR rd0 is rd0 & op13_3=0x2 & op9_4=0xe & op4_5=0x0 { + tmpRd0:4 = rd0; + tmpC:4 = zext(C); + rd0 = tmpRd0 + tmpC; + acrflags(tmpRd0, tmpC, rd0); +} + +:ACR rd0 is rd0 & op13_3=0x2 & op9_4=0xe & op4_5=0x0 & rd0=0xf { + tmpRd0:4 = inst_start; + tmpC:4 = zext(C); + PC = tmpRd0 + tmpC; + acrflags(tmpRd0, tmpC, PC); + goto [PC]; +} + +#--------------------------------------------------------------------- +# ADC - Add with Carry +# I. {d, x, y} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- +#ADC Format I +# Operation: Rd <- Rx + Ry + C; +# Syntax: adc Rd, Rx, Ry +# 111 xxxx 00000 yyyy 0000 00000100 dddd (Opcode Form) +# 111x xxx0 0000 yyyy 0000 0000 0100 dddd (Byte half Form) +:ADC erd0, RX9A, RY0A is op13_3=0x7 & RX9A & op4_5=0x0 & RY0A; eop12_4=0x0 & eop4_8=0x4 & erd0 { + erd0 = RX9A + RY0A + zext(C); +} + +:ADC erd0, RX9A, RY0A is op13_3=0x7 & RX9A & op4_5=0x0 & RY0A; eop12_4=0x0 & eop4_8=0x4 & erd0 & erd0=0xf{ + PC = RX9A + RY0A + zext(C); + goto [PC]; +} + + +#--------------------------------------------------------------------- +# ADD - Add without Carry +# I. {d, s} -> {0, 1, ..., 15} +# II. {d, x, y} -> {0, 1, ..., 15} +# sa -> {0, 1, 2, 3} +#--------------------------------------------------------------------- +# ADD Format I +# Operation: Rd <- Rd + Rs +# Syntax: add Rd, Rs +# 000s sss0 0000 dddd +:ADD rd0, RS9A is op13_3=0x0 & op4_5=0x0 & rd0 & RS9A { + tmpRd0:4 = rd0; + rd0 = RS9A + tmpRd0; + addflags(tmpRd0, RS9A, rd0); +} + +:ADD PC, RS9A is op13_3=0x0 & op4_5=0x0 & rd0 & RS9A & rs0=0xf & PC { + tmpRd0:4 = inst_start; + PC = RS9A + tmpRd0; + addflags(tmpRd0, RS9A, PC); + goto [PC]; +} + +# ADD Format II +# Operation: Rd <- Rx + Ry << sa2 +# Syntax: add Rd, Rx, Ry << sa +# 111x xxx0 0000 yyyy 0000 0000 00tt dddd +:ADD erd0, RX9A, RY0A^" << " shift4_2 is op13_3=7 & op4_5=0 & RX9A & RY0A; + eop6_10=0 & erd0 & shift4_2 { + tmp:4 = RY0A << shift4_2; + erd0 = RX9A + tmp; + addflags(RX9A, tmp, erd0); +} + +:ADD erd0, RX9A, RY0A^" << " shift4_2 is op13_3=7 & op4_5=0 & RX9A & RY0A; + eop6_10=0 & erd0 & shift4_2 & ers0=0xf { + tmp:4 = RY0A << shift4_2; + PC = RX9A + tmp; + addflags(RX9A, tmp, PC); + goto [PC]; +} + + +#--------------------------------------------------------------------- +# ADD{cond4} - Conditional Add +# I. cond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al} +# {d,x,y} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# ADD{cond4} Format I +# Operation: if(cond4) then +# Rd <- Rx + Ry +# Syntax: add{cond4} Rd, Rx, Ry +# 111x xxx1 1101 yyyy 1110 cccc 0000 dddd + +:ADD^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A; + eop12_4=0xe & eop4_4=0 & ECOND_8_4 & erd0) +{ + build ECOND_8_4; + erd0 = RX9A + RY0A; +} + +:ADD^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A; + eop12_4=0xe & eop4_4=0 & ECOND_8_4 & erd0 & erd0=0xf) +{ + build ECOND_8_4; + PC = RX9A + RY0A; + goto [PC]; +} + +#--------------------------------------------------------------------- +# ADDABS - Add Absolute Value +# I. {d,x,y} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# ADDABS Format I +# Operation: Rd <- Rx + |Ry| +# Syntax: addabs Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 1110 0100 dddd + +:ADDABS erd0, RX9A, RY0A is (op13_3=7 & op4_5=0 & RX9A & RY0A; eop4_12=0xe4 & erd0) +{ + local ztst:1 = RY0A s< 0; + local ary0:4 = (zext(!ztst)*RY0A) + (zext(ztst)*(-RY0A)); + erd0 = RX9A + ary0; + ZSTATUS(erd0); +} + +:ADDABS erd0, RX9A, RY0A is (op13_3=7 & op4_5=0 & RX9A & RY0A; eop4_12=0xe4 & erd0 & erd0=0xf) +{ + local ztst:1 = RY0A s< 0; + local ary0:4 = (zext(!ztst)*RY0A) + (zext(ztst)*(-RY0A)); + PC = RX9A + ary0; + ZSTATUS(PC); + goto [PC]; +} + +#--------------------------------------------------------------------- +# CP.B - Compare Byte +# I. {d, s} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- +# CP.B Format I +# Operation: Rd[7:0] - Rs[7:0] +# Syntax: cp.b Rd, Rs +# 111s sss0 0000 dddd 0001 1000 0000 0000 + +:CP.B RD0A, RS9A is op13_3=7 & op4_5=0 & RD0A & RS9A; eop0_16=0x1800 { + + tmp:1 = RD0A:1 - RS9A:1; + + subflags(RD0A:1, RS9A:1, tmp); +} + +#--------------------------------------------------------------------- +# CP.H - Compare Halfword +# I. {d, s} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- +# CP.H Format I +# Operation: Rd[15:0] - Rs[15:0] +# Syntax: cp.h Rd, Rs +# 111s sss0 0000 dddd 0001 1001 0000 0000 + +:CP.H RD0A, RS9A is op13_3=7 & op4_5=0 & RD0A & RS9A; eop0_16=0x1900 { + tmp:2 = RD0A:2 - RS9A:2; + subflags(RD0A:2, RS9A:2, tmp); +} + +#--------------------------------------------------------------------- +# CP.W - Compare Word +# I. {d, s} -> {0, 1, ..., 15} +# II. d -> {0, 1, ..., 15} +# imm -> {-32, -31, ..., 31} +# III. d -> {0, 1, ..., 15} +# imm -> {-1048576, -1048575, ..., 1048575} +#--------------------------------------------------------------------- +# CP.W Format I +# Operation: Rd - Rs +# Syntax: cp.w Rd, Rs +# 000s sss0 0011 dddd + +:CP.W RD0A, RS9A is op13_3=0x0 & op4_5=0x3 & RD0A & RS9A { + tmp:4 = RD0A - RS9A; + subflags(RD0A, RS9A, tmp); +} + +# CP.W Format II +# Operation: Rd - SE(imm6) +# Syntax: cp.w Rd, imm +# 0101 10ii iiii dddd + +:CP.W RD0A, imm4_6 is op10_6=0x16 & imm4_6 & RD0A { + tmp:4 = RD0A - imm4_6; + subflags(RD0A, imm4_6, tmp); +} + +# CP.W Format III +# Operation: Rd - SE(imm21) +# Syntax: cp.w Rd, imm +# 111i iii0 010i dddd iiii iiii iiii iiii + +:CP.W RD0A, imm is op13_3=0x7 & op5_4=0x2 & imm9_4 & imm4_1 & RD0A; imm16 + [ imm = (imm9_4 << 17) | (imm4_1 << 16) | imm16; ] +{ + tmp:4 = RD0A - imm; + subflags(RD0A, imm, tmp); +} + +#--------------------------------------------------------------------- +# CPC - Compare with Carry +# I. {d, s} -> {0, 1, ..., 15} +# II. d -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# CPC Format I +# Operation: Rd - Rs - C +# Syntax: cpc Rd, Rs +# 111s sss0 0000 dddd 0001 0011 0000 0000 + +:CPC RD0A, RS9A is op13_3=0x7 & op4_5=0x0 & RD0A & RS9A ; eop0_16=0x1300 +{ + temp:4 = RD0A - RS9A - zext(C); + cpcflags(RD0A, RS9A, temp); +} + +# CPC Format II +# Operation: Rd - C +# Syntax: cpc Rd +# 0101 1100 0010 dddd + +:CPC RD0A is op4_12=0x5c2 & RD0A +{ + temp:4 = RD0A - zext(C); + cpcflags0(RD0A, temp); +} + +#--------------------------------------------------------------------- +# MAX - Return Maximum Value +# I. {d,x,y} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# MAX Format I +# Operation: if Rx > Ry +# Rd <- Rx; +# else +# Rd <- Ry; +# Syntax: max Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 1100 0100 dddd + +:MAX erd0, RX9A, RY0A is op13_3=0x7 & op4_5=0x0 & RX9A & RY0A ; eop4_12=0xc4 & erd0 +{ + rxgt:4 = zext(RX9A s> RY0A); + rxle:4 = zext(RX9A s<= RY0A); + erd0 = RX9A * rxgt + RY0A * rxle; +} + +:MAX erd0, RX9A, RY0A is op13_3=0x7 & op4_5=0x0 & RX9A & RY0A ; eop4_12=0xc4 & erd0 & erd0=0xf +{ + rxgt:4 = zext(RX9A s> RY0A); + rxle:4 = zext(RX9A s<= RY0A); + PC = RX9A * rxgt + RY0A * rxle; + goto [PC]; +} + +#--------------------------------------------------------------------- +# MIN - Return Minimum Value +# I. {d,x,y} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# MIN Format I +# Operation: if Rx < Ry +# Rd <- Rx; +# else +# Rd <- Ry; +# Syntax: min Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 1101 0100 dddd + +:MIN erd0, RX9A, RY0A is op13_3=0x7 & op4_5=0x0 & RX9A & RY0A ; eop4_12=0xd4 & erd0 +{ + rxlt:4 = zext(RX9A s< RY0A); + rxge:4 = zext(RX9A s>= RY0A); + erd0 = RX9A * rxlt + RY0A * rxge; +} + +:MIN erd0, RX9A, RY0A is op13_3=0x7 & op4_5=0x0 & RX9A & RY0A ; eop4_12=0xd4 & erd0 & erd0=0xf +{ + rxlt:4 = zext(RX9A s< RY0A); + rxge:4 = zext(RX9A s>= RY0A); + PC = RX9A * rxlt + RY0A * rxge; + goto [PC]; +} + +#--------------------------------------------------------------------- +# NEG - Compare Word +# I. {d, s} -> {0, 1, ..., 15} +# II. d -> {0, 1, ..., 15} +# imm -> {-32, -31, ..., 31} +# III. d -> {0, 1, ..., 15} +# imm -> {-1048576, -1048575, ..., 1048575} +#--------------------------------------------------------------------- + +# NEG Format I +# Operation: Rd <- 0 - Rd +# Syntax: neg Rd +# 0101 1100 0011 dddd + +:NEG rd0 is op4_12=0x5c3 & rd0 { + save:4 = rd0; + rd0 = -rd0; + subflags(0, save, rd0); +} + +:NEG rd0 is op4_12=0x5c3 & rd0 & rd0=0xf { + tmp:4 = inst_start; + PC = -tmp; + subflags(0, tmp, PC); + goto [PC]; +} + +#--------------------------------------------------------------------- +# RSUB - Reverse Subtract +# I. {d, s} -> {0, 1, ..., 15} +# II. {d, s} -> {0, 1, ..., 15} +# imm -> {-128, -127, ..., 127} +#--------------------------------------------------------------------- + +# RSUB Format I +# Operation: Rd <- Rs - Rd +# Syntax: rsub Rd, Rs +# 000s sss0 0010 dddd + +:RSUB rd0, RS9A is op13_3=0x0 & op4_5=2 & rd0 & RS9A { + save:4 = rd0; + rd0 = RS9A - rd0; + subflags(RS9A, save, rd0); +} + +:RSUB rd0, RS9A is op13_3=0x0 & op4_5=2 & rd0 & RS9A & rd0=0xf { + PC = RS9A - inst_start; + subflags(RS9A, inst_start, PC); + goto [PC]; +} + +# RSUB Format II +# Operation: Rd <- SE(imm8) - Rs +# Syntax: rsub Rd, Rs, imm +# 111s sss0 0000 dddd 0001 0001 iiii iiii + +:RSUB rd0, RS9A, simm0_8 is op13_3=7 & op4_5=0 & rd0 & RS9A; + eop12_4=1 & eop8_4=1 & simm0_8 +{ + save:4 = simm0_8; + tmp:4 = RS9A; + rd0 = save - RS9A; + subflags(save, tmp, rd0); +} + +:RSUB rd0, RS9A, simm0_8 is op13_3=7 & op4_5=0 & rd0 & RS9A & rd0=0xf; + eop12_4=1 & eop8_4=1 & simm0_8 +{ + save:4 = simm0_8; + tmp:4 = RS9A; + PC = save - RS9A; + subflags(save, tmp, PC); + goto [PC]; +} + +# RSUB Format II +# Operation: Rd <- SE(imm8) - Rs +# Syntax: rsub Rd, Rs, imm +# 111s sss0 0000 dddd 0001 0001 iiii iiii +#Handles Special Case where Immediate = -0x1 and treat it as a ~ (negate) +:RSUB rd0, RS9A, simm0_8 is op13_3=7 & op4_5=0 & rd0 & RS9A; + eop12_4=1 & eop8_4=1 & simm0_8 & imm0_8=0xff +{ + rd0 = ~RS9A; + subflags(-1:4, RS9A, rd0); +} + +:RSUB rd0, RS9A, simm0_8 is op13_3=7 & op4_5=0 & rd0 & RS9A & rd0=0xf; + eop12_4=1 & eop8_4=1 & simm0_8 & imm0_8=0xff +{ + PC = ~RS9A; + subflags(-1:4, RS9A, PC); + goto [PC]; +} + +#--------------------------------------------------------------------- +# RSUB{cond4} - Conditional Move Register +# I. d -> {0, 1, ..., 15} +# cond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al} +# imm -> {-128, -127, ..., 127} +#--------------------------------------------------------------------- + +# RSUB{cond4} Format I +# Operation: if (cond4) +# Rd <- SE(imm8) - Rd +# Syntax: rsub{cond4} Rd, imm +# 1111 1011 1011 dddd 0000 cccc iiii iiii + +:RSUB^{ECOND_8_4} rd0, simm0_8 is op4_12=0xfbb & rd0 ; eop12_4=0 & simm0_8 & ECOND_8_4 +{ + build ECOND_8_4; + rd0 = simm0_8 - rd0; +} + +:RSUB^{ECOND_8_4} rd0, simm0_8 is op4_12=0xfbb & rd0 & rd0=0xf; eop12_4=0 & simm0_8 & ECOND_8_4 +{ + build ECOND_8_4; + PC = simm0_8 - inst_start; + goto [PC]; +} + +#--------------------------------------------------------------------- +# SBC - Subtract with Carry +# I. {d,x,y} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# SBC Format I +# Operation: Rd <- Rx - Ry - C +# Syntax: sbc Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 0001 0100 dddd + +:SBC erd0, RX9A, RY0A is op13_3=0x7 & op4_5=0x0 & RX9A & RY0A ; eop4_12=0x14 & erd0 +{ + tmpx:4 = RX9A; + tmpy:4 = RY0A; + erd0 = RX9A - RY0A - zext(C); + cpcflags(tmpx, tmpy, erd0); +} + +:SBC erd0, RX9A, RY0A is op13_3=0x7 & op4_5=0x0 & RX9A & RY0A ; eop4_12=0x14 & erd0 & erd0=0xf +{ + tmpx:4 = RX9A; + tmpy:4 = RY0A; + PC = RX9A - RY0A - zext(C); + cpcflags(tmpx, tmpy, PC); + goto [PC]; +} + +#--------------------------------------------------------------------- +# SCR - Subtract Carry from Register +# I. d -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# SCR Format I +# Operation: Rd <- Rd - C +# Syntax: scr Rd +# 0101 1100 0001 dddd + +:SCR rd0 is op4_12=0x5c1 & rd0 +{ + save:4 = rd0; + rd0 = rd0 - zext(C); + + V = (save s< 0) && (rd0 s>= 0); + N = rd0 s< 0; + Z = (rd0 == 0) && Z; + C = (save s>= 0) && (rd0 s< 0); + CZNVTOSR(); +} + +:SCR rd0 is op4_12=0x5c1 & rd0 & rd0=0xf +{ + tmp:4 = inst_start; + PC = tmp - zext(C); + + V = (tmp s< 0) && (PC s>= 0); + N = PC s< 0; + Z = (PC == 0) && Z; + C = (tmp s>= 0) && (PC s< 0); + CZNVTOSR(); + goto [PC]; +} + +#--------------------------------------------------------------------- +# SUB - Subtract (without Carry) +#--------------------------------------------------------------------- +# SUB Format I +# 000s sss0 0001 dddd + +:SUB rd0, RS9A is op13_3=0 & op4_5=1 & rd0 & RS9A { + save:4 = rd0; + tmp:4 = RS9A; + rd0 = rd0 - RS9A; + subflags(save, tmp, rd0); +} + +:SUB rd0, RS9A is op13_3=0 & op4_5=1 & rd0 & RS9A & rd0=0xf { + tmp:4 = RS9A; + PC = inst_start - RS9A; + subflags(inst_start, tmp, rd0); + goto [PC]; +} + +# SUB Format II +# 111x xxx0 0000 yyyy 0000 0001 00tt dddd + +:SUB erd0, RX9A, RY0A^" << " shift4_2 is op13_3=7 & op4_5=0 & RY0A & RX9A; + eop6_10=4 & shift4_2 & erd0 { + save:4 = RX9A; + val:4 = RY0A << shift4_2; + erd0 = RX9A - val; + subflags(save, val, erd0); +} + +:SUB erd0, RX9A, RY0A^" << " shift4_2 is op13_3=7 & op4_5=0 & RY0A & RX9A; + eop6_10=4 & shift4_2 & erd0 & erd0=0xf { + save:4 = RX9A; + val:4 = RY0A << shift4_2; + PC = RX9A - val; + subflags(save, val, PC); + goto [PC]; +} + +# SUB Format III +# 0010 iiii iiii dddd + +:SUB rd0, imm is op13_3=0x1 & op12_1=0 & imm4_8 & rd0 & b003=0xd + [ imm = imm4_8 << 2; ] +{ + save:4 = rd0; + rd0 = rd0 - imm; + subflags(save, imm, rd0); +} + +:SUB rd0, imm4_8 is op13_3=0x1 & op12_1=0 & imm4_8 & rd0 { + save:4 = rd0; + rd0 = rd0 - imm4_8; + subflags(save, imm4_8, rd0); +} + +:SUB rd0, imm4_8 is op13_3=0x1 & op12_1=0 & imm4_8 & rd0 & rd0=0xf { + tmp:4 = inst_start; + PC = tmp - imm4_8; + subflags(tmp, imm4_8, PC); + goto [PC]; +} + +# SUB Format IV +# 111i iii0 001i dddd iiii iiii iiii iiii + +:SUB rd0, imm is op13_3=0x7 & op5_4=0x1 & imm9_4 & imm4_1 & rd0; imm16 + [ imm = (imm9_4 << 17) | (imm4_1 << 16) | imm16; ] +{ + save:4 = rd0; + rd0 = rd0 - imm; + subflags(save, imm, rd0); +} + +:SUB rd0, imm is op13_3=0x7 & op5_4=0x1 & imm9_4 & imm4_1 & rd0 & rd0=0xf; imm16 + [ imm = (imm9_4 << 17) | (imm4_1 << 16) | imm16; ] +{ + tmp:4 = inst_start; + PC = tmp - imm; + subflags(tmp, imm, PC); + goto [PC]; +} + +# SUB Format V +# 111s sss0 1100 dddd iiii iiii iiii iiii + +:SUB rd0, RS9A, simm16 is op13_3=0x7 & op4_5=0xc & RS9A & rd0; simm16 +{ + save:4 = RS9A; + rd0 = RS9A - simm16; + subflags(save, simm16, rd0); +} + +:SUB rd0, RS9A, simm16 is op13_3=0x7 & op4_5=0xc & RS9A & rd0 & rd0=0xf; simm16 +{ + save:4 = RS9A; + PC = RS9A - simm16; + subflags(save, simm16, PC); + goto [PC]; +} + +#--------------------------------------------------------------------- +# SUB{cond4} - Conditional Subtract +# I. cond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al} +# d -> {0, 1, ..., 15} +# imm -> {-128, -127, ..., 127} +# II. cond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al} +# {d,x,y} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# SUB{cond4} Format I +# Operation: if(cond4) then +# Rd <- Rd - imm8 +# Update flags if opcode[f] field is set +# Syntax: sub{f}{cond4} Rd, imm +# 1111 01f1 1011 dddd 0000 cccc iiii iiii + +F: "{F}" is b09=1 & rd0; simm0_8 { + pre:4 = rd0 + simm0_8; + subflags(pre, simm0_8, rd0); +} +F: is b09=0 & rd0; simm0_8 { } + +:SUB^F^{ECOND_8_4} rd0, simm0_8 is (op10_6=0x3d & op4_5=0x1b & rd0 ; + eop12_4=0 & simm0_8 & ECOND_8_4) & F +{ + build ECOND_8_4; + rd0 = rd0 - simm0_8; + build F; +} + +:SUB^F^{ECOND_8_4} rd0, simm0_8 is (op10_6=0x3d & op4_5=0x1b & rd0 & rd0=0xf; + eop12_4=0 & simm0_8 & ECOND_8_4) & F +{ + build ECOND_8_4; + PC = inst_start - simm0_8; + build F; + goto [PC]; +} + +# SUB{cond4} Format II +# Operation: if(cond4) then +# Rd <- Rx - Ry +# Syntax: sub{cond4} Rd, Rx, Ry +# 111x xxx1 1101 yyyy 1110 cccc 0001 dddd + +:SUB^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A; + eop12_4=0xe & eop4_4=1 & ECOND_8_4 & erd0) +{ + build ECOND_8_4; + erd0 = RX9A - RY0A; +} + +:SUB^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A; + eop12_4=0xe & eop4_4=1 & ECOND_8_4 & erd0 & erd0=0xf) +{ + build ECOND_8_4; + PC = RX9A - RY0A; + goto [PC]; +} + +#--------------------------------------------------------------------- +# TNBZ - Test if No Byte is Equal to Zero +# I. d -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# TNBZ Format I +# Operation: if (Rd[31:24] == 0 | +# Rd[23:16] == 0 | +# Rd[23:16] == 0 | +# Rd[23:16] == 0) +# Z <- 1; +# else +# Z <- 0; +# Syntax: tnbz Rd +# 0101 1100 1110 dddd + +:TNBZ RD0A is op4_12=0x5ce & RD0A +{ + Z = ((RD0A & 0xff000000) == 0 || + (RD0A & 0x00ff0000) == 0 || + (RD0A & 0x0000ff00) == 0 || + (RD0A & 0x000000ff) == 0); +} diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_autogen.sinc b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_autogen.sinc new file mode 100644 index 0000000..aa22ea8 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_autogen.sinc @@ -0,0 +1,464 @@ +define token gen_instr1(16) + g_op13_3 = (13,15) + g_op12_4 = (12,15) + g_regsel11_1 = (11,11) + g_op11_5 = (11,15) + g_op10_6 = (10,15) + g_regsel10_1 = (10,10) + g_op9_7 = (9,15) + g_rx9_4 = (9,12) + g_opcode9_2 = (9,10) + g_rs9_4 = (9,12) + g_regsel9_1 = (9,9) + g_offset9_4 = (9,12) + g_disp9_4 = (9,12) + g_rp9_4 = (9,12) + g_update9_1 = (9,9) + g_rb9_4 = (9,12) + g_imm9_4 = (9,12) + g_rd9_4 = (9,12) + g_shift9_4 = (9,12) + g_op8_1 = (8,8) + g_op8_8 = (8,15) + g_regsel8_1 = (8,8) + g_op7_9 = (7,15) + g_op7_2 = (7,8) + g_regsel7_1 = (7,7) + g_regsel6_1 = (6,6) + g_regsel5_1 = (5,5) + g_op5_4 = (5,8) + g_imm4_1 = (4,4) + g_disp4_5 = (4,8) + g_imm4_6 = (4,9) + g_shift4_1 = (4,4) + g_imm4_8 = (4,11) + g_disp4_1 = (4,4) + g_offset4_1 = (4,4) + g_disp4_4 = (4,7) + g_op4_12 = (4,15) + g_disp4_8 = (4,11) + g_disp4_3 = (4,6) + g_regsel4_1 = (4,4) + g_imm4_3 = (4,6) + g_op4_5 = (4,8) + g_offset4_5 = (4,8) + g_cond4_4 = (4,7) + g_disp4_7 = (4,10) + g_op3_1 = (3,3) + g_op3_6 = (3,8) + g_returnflag3_1 = (3,3) + g_op2_2 = (2,3) + g_rd1_3 = (1,3) + g_rs1_3 = (1,3) + g_ri0_4 = (0,3) + g_cond0_4 = (0,3) + g_shift0_4 = (0,3) + g_op0_16 = (0,15) + g_op0_9 = (0,8) + g_op0_1 = (0,0) + g_offset0_4 = (0,3) + g_rs0_4 = (0,3) + g_cond0_3 = (0,2) + g_op0_3 = (0,2) + g_opcode0_4 = (0,3) + g_rd0_4 = (0,3) + g_shift0_3 = (0,2) + g_rp0_4 = (0,3) + g_ry0_4 = (0,3) + g_disp0_2 = (0,1) + g_op0_4 = (0,3) +; +define token gen_instr2(16) + eg_regsel15_1 = (15,15) + eg_offset15_1 = (15,15) + eg_regsel14_1 = (14,14) + eg_op14_2 = (14,15) + eg_op13_3 = (13,15) + eg_xpart13_1 = (13,13) + eg_cop13_3 = (13,15) + eg_regsel13_1 = (13,13) + eg_disp12_4 = (12,15) + eg_op12_4 = (12,15) + eg_regsel12_1 = (12,12) + eg_op12_1 = (12,12) + eg_update12_1 = (12,12) + eg_ypart12_1 = (12,12) + eg_cond12_4 = (12,15) + eg_opcode12_1 = (12,12) + eg_opcode11_5 = (11,15) + eg_regsel11_1 = (11,11) + eg_regsel10_1 = (10,10) + eg_op10_6 = (10,15) + eg_regsel9_1 = (9,9) + eg_op9_7 = (9,15) + eg_rd9_3 = (9,11) + eg_rs9_3 = (9,11) + eg_op9_3 = (9,11) + eg_op8_1 = (8,8) + eg_op8_4 = (8,11) + eg_rd8_4 = (8,11) + eg_op8_8 = (8,15) + eg_cond8_4 = (8,11) + eg_ri8_4 = (8,11) + eg_regsel8_1 = (8,8) + eg_rs8_4 = (8,11) + eg_regsel7_1 = (7,7) + eg_op6_3 = (6,8) + eg_regsel6_1 = (6,6) + eg_op6_2 = (6,7) + eg_op6_10 = (6,15) + eg_op5_11 = (5,15) + eg_regsel5_1 = (5,5) + eg_offset5_5 = (5,9) + eg_xpart5_1 = (5,5) + eg_regsel4_1 = (4,4) + eg_rx4_4 = (4,7) + eg_disp4_8 = (4,11) + eg_ypart4_1 = (4,4) + eg_shift4_5 = (4,8) + eg_cond4_4 = (4,7) + eg_returnflag4_1 = (4,4) + eg_op4_12 = (4,15) + eg_op4_4 = (4,7) + eg_shift4_2 = (4,5) + eg_regsel3_1 = (3,3) + eg_regsel2_1 = (2,2) + eg_regsel1_1 = (1,1) + eg_ri0_4 = (0,3) + eg_opcode0_8 = (0,7) + eg_rd0_4 = (0,3) + eg_imm0_8 = (0,7) + eg_shift0_5 = (0,4) + eg_regsel0_1 = (0,0) + eg_disp0_16 = (0,15) + eg_disp0_12 = (0,11) + eg_disp0_8 = (0,7) + eg_bits0_5 = (0,4) + eg_disp0_9 = (0,8) + eg_imm0_15 = (0,14) + eg_rs0_4 = (0,3) + eg_rb0_4 = (0,3) + eg_offset0_5 = (0,4) + eg_op0_8 = (0,7) + eg_imm0_16 = (0,15) + eg_op0_9 = (0,8) + eg_ry0_4 = (0,3) + eg_op0_16 = (0,15) + eg_dbgregaddr0_8 = (0,7) + eg_disp0_11 = (0,10) + eg_rp0_4 = (0,3) + eg_op0_4 = (0,3) +; +#:ABS g_rd0_4 is g_op4_12=0x5c4 & g_rd0_4 unimpl +#:ACALL g_disp4_8 is g_op12_4=0xd & g_disp4_8 & g_op0_4=0x0 unimpl +#:ACR g_rd0_4 is g_op4_12=0x5c0 & g_rd0_4 unimpl +#:ADC g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x4 & eg_rd0_4 unimpl +#:ADD g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 unimpl +#:ADD g_rx9_4, g_ry0_4, eg_shift4_2, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x0 & eg_shift4_2 & eg_rd0_4 unimpl +#:ADD_COND g_rx9_4, g_ry0_4, eg_cond8_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1d & g_ry0_4 ; eg_op12_4=0xe & eg_cond8_4 & eg_op4_4=0x0 & eg_rd0_4 unimpl +#:ADDABS g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0xe4 & eg_rd0_4 unimpl +#:ADDHH.W g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x38 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl +#:AND g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x6 & g_rd0_4 unimpl +#:AND g_rx9_4, g_ry0_4, eg_shift4_5, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1e & g_ry0_4 ; eg_op9_7=0x0 & eg_shift4_5 & eg_rd0_4 unimpl +#:AND g_rx9_4, g_ry0_4, eg_shift4_5, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1e & g_ry0_4 ; eg_op9_7=0x1 & eg_shift4_5 & eg_rd0_4 unimpl +#:AND_COND g_rx9_4, g_ry0_4, eg_cond8_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1d & g_ry0_4 ; eg_op12_4=0xe & eg_cond8_4 & eg_op4_4=0x2 & eg_rd0_4 unimpl +#:ANDH g_update9_1, g_rd0_4, eg_imm0_16 is g_op10_6=0x39 & g_update9_1 & g_op4_5=0x1 & g_rd0_4 ; eg_imm0_16 unimpl +#:ANDL g_update9_1, g_rd0_4, eg_imm0_16 is g_op10_6=0x38 & g_update9_1 & g_op4_5=0x1 & g_rd0_4 ; eg_imm0_16 unimpl +#:ANDN g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x8 & g_rd0_4 unimpl +#:ASR g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x84 & eg_rd0_4 unimpl +#:ASR g_shift9_4, g_shift4_1, g_rd0_4 is g_op13_3=0x5 & g_shift9_4 & g_op5_4=0xa & g_shift4_1 & g_rd0_4 unimpl +#:ASR g_rs9_4, g_rd0_4, eg_shift0_5 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op5_11=0xa0 & eg_shift0_5 unimpl +#:BFEXTS g_rd9_4, g_rs0_4, eg_offset5_5, eg_bits0_5 is g_op13_3=0x7 & g_rd9_4 & g_op4_5=0x1d & g_rs0_4 ; eg_op10_6=0x2c & eg_offset5_5 & eg_bits0_5 unimpl +#:BFEXTU g_rd9_4, g_rs0_4, eg_offset5_5, eg_bits0_5 is g_op13_3=0x7 & g_rd9_4 & g_op4_5=0x1d & g_rs0_4 ; eg_op10_6=0x30 & eg_offset5_5 & eg_bits0_5 unimpl +#:BFINS g_rd9_4, g_rs0_4, eg_offset5_5, eg_bits0_5 is g_op13_3=0x7 & g_rd9_4 & g_op4_5=0x1d & g_rs0_4 ; eg_op10_6=0x34 & eg_offset5_5 & eg_bits0_5 unimpl +#:BLD g_rd0_4, eg_offset0_5 is g_op4_12=0xedb & g_rd0_4 ; eg_op5_11=0x0 & eg_offset0_5 unimpl +#:BR_COND g_disp4_8, g_cond0_3 is g_op12_4=0xc & g_disp4_8 & g_op3_1=0x0 & g_cond0_3 unimpl +#:BR_COND g_disp9_4, g_disp4_1, g_cond0_4, eg_disp0_16 is g_op13_3=0x7 & g_disp9_4 & g_op5_4=0x4 & g_disp4_1 & g_cond0_4 ; eg_disp0_16 unimpl +#:BREAKPOINT is g_op0_16=0xd673 unimpl +#:BREV g_rd0_4 is g_op4_12=0x5c9 & g_rd0_4 unimpl +#:BST g_rd0_4, eg_offset0_5 is g_op4_12=0xefb & g_rd0_4 ; eg_op5_11=0x0 & eg_offset0_5 unimpl +#:CACHE g_rp0_4, eg_opcode11_5, eg_disp0_11 is g_op4_12=0xf41 & g_rp0_4 ; eg_opcode11_5 & eg_disp0_11 unimpl +#:CASTS.H g_rd0_4 is g_op4_12=0x5c8 & g_rd0_4 unimpl +#:CASTS.B g_rd0_4 is g_op4_12=0x5c6 & g_rd0_4 unimpl +#:CASTU.H g_rd0_4 is g_op4_12=0x5c7 & g_rd0_4 unimpl +#:CASTU.B g_rd0_4 is g_op4_12=0x5c5 & g_rd0_4 unimpl +#:CBR g_offset9_4, g_offset4_1, g_rd0_4 is g_op13_3=0x5 & g_offset9_4 & g_op5_4=0xe & g_offset4_1 & g_rd0_4 unimpl +#:CLZ g_rs9_4, g_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op0_16=0x1200 unimpl +#:COM g_rd0_4 is g_op4_12=0x5cd & g_rd0_4 unimpl +#:COP g_opcode9_2, g_opcode0_4, eg_cop13_3, eg_opcode12_1, eg_rd8_4, eg_rx4_4, eg_ry0_4 is g_op11_5=0x1c & g_opcode9_2 & g_op4_5=0x1a & g_opcode0_4 ; eg_cop13_3 & eg_opcode12_1 & eg_rd8_4 & eg_rx4_4 & eg_ry0_4 unimpl +#:CP.B g_rs9_4, g_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op0_16=0x1800 unimpl +#:CP.H g_rs9_4, g_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op0_16=0x1900 unimpl +#:CP.W g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x3 & g_rd0_4 unimpl +#:CP.W g_imm4_6, g_rd0_4 is g_op10_6=0x16 & g_imm4_6 & g_rd0_4 unimpl +#:CP.W g_imm9_4, g_imm4_1, g_rd0_4, eg_imm0_16 is g_op13_3=0x7 & g_imm9_4 & g_op5_4=0x2 & g_imm4_1 & g_rd0_4 ; eg_imm0_16 unimpl +#:CPC g_rs9_4, g_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op0_16=0x1300 unimpl +#:CPC g_rd0_4 is g_op4_12=0x5c2 & g_rd0_4 unimpl +#:CSRF g_offset4_5 is g_op9_7=0x6a & g_offset4_5 & g_op0_4=0x3 unimpl +#:CSRFCZ g_offset4_5 is g_op9_7=0x68 & g_offset4_5 & g_op0_4=0x3 unimpl +#:DIVS g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0xc0 & eg_rd0_4 unimpl +#:DIVU g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0xd0 & eg_rd0_4 unimpl +#:EOR g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x5 & g_rd0_4 unimpl +#:EOR g_rx9_4, g_ry0_4, eg_shift4_5, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1e & g_ry0_4 ; eg_op9_7=0x10 & eg_shift4_5 & eg_rd0_4 unimpl +#:EOR g_rx9_4, g_ry0_4, eg_shift4_5, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1e & g_ry0_4 ; eg_op9_7=0x11 & eg_shift4_5 & eg_rd0_4 unimpl +#:EOR_COND g_rx9_4, g_ry0_4, eg_cond8_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1d & g_ry0_4 ; eg_op12_4=0xe & eg_cond8_4 & eg_op4_4=0x4 & eg_rd0_4 unimpl +#:EORH g_rd0_4, eg_imm0_16 is g_op4_12=0xee1 & g_rd0_4 ; eg_imm0_16 unimpl +#:EORL g_rd0_4, eg_imm0_16 is g_op4_12=0xec1 & g_rd0_4 ; eg_imm0_16 unimpl +#:FRS is g_op0_16=0xd743 unimpl +#:ICALL g_rd0_4 is g_op4_12=0x5d1 & g_rd0_4 unimpl +#:INCJOSP g_imm4_3 is g_op7_9=0x1ad & g_imm4_3 & g_op0_4=0x3 unimpl +#:LD.D g_rp9_4, g_rd1_3 is g_op13_3=0x5 & g_rp9_4 & g_op4_5=0x10 & g_rd1_3 & g_op0_1=0x1 unimpl +#:LD.D g_rp9_4, g_rd1_3 is g_op13_3=0x5 & g_rp9_4 & g_op4_5=0x11 & g_rd1_3 & g_op0_1=0x0 unimpl +#:LD.D g_rp9_4, g_rd1_3 is g_op13_3=0x5 & g_rp9_4 & g_op4_5=0x10 & g_rd1_3 & g_op0_1=0x0 unimpl +#:LD.D g_rp9_4, g_rd1_3, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0xe & g_rd1_3 & g_op0_1=0x0 ; eg_disp0_16 unimpl +#:LD.D g_rb9_4, g_ri0_4, eg_shift4_2, eg_rd0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x8 & eg_shift4_2 & eg_rd0_4 unimpl +#:LD.SB g_rp9_4, g_rd0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x12 & g_rd0_4 ; eg_disp0_16 unimpl +#:LD.SB g_rb9_4, g_ri0_4, eg_shift4_2, eg_rd0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x18 & eg_shift4_2 & eg_rd0_4 unimpl +#:LD.SB_COND g_rp9_4, g_rd0_4, eg_cond12_4, eg_disp0_9 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1f & g_rd0_4 ; eg_cond12_4 & eg_op9_3=0x3 & eg_disp0_9 unimpl +#:LD.UB g_rp9_4, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0x13 & g_rd0_4 unimpl +#:LD.UB g_rp9_4, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0x17 & g_rd0_4 unimpl +#:LD.UB g_rp9_4, g_disp4_3, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op7_2=0x3 & g_disp4_3 & g_rd0_4 unimpl +#:LD.UB g_rp9_4, g_rd0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x13 & g_rd0_4 ; eg_disp0_16 unimpl +#:LD.UB g_rb9_4, g_ri0_4, eg_shift4_2, eg_rd0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x1c & eg_shift4_2 & eg_rd0_4 unimpl +#:LD.UB_COND g_rp9_4, g_rd0_4, eg_cond12_4, eg_disp0_9 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1f & g_rd0_4 ; eg_cond12_4 & eg_op9_3=0x4 & eg_disp0_9 unimpl +#:LD.SH g_rp9_4, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0x11 & g_rd0_4 unimpl +#:LD.SH g_rp9_4, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0x15 & g_rd0_4 unimpl +#:LD.SH g_rp9_4, g_disp4_3, g_rd0_4 is g_op13_3=0x4 & g_rp9_4 & g_op7_2=0x0 & g_disp4_3 & g_rd0_4 unimpl +#:LD.SH g_rp9_4, g_rd0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x10 & g_rd0_4 ; eg_disp0_16 unimpl +#:LD.SH g_rb9_4, g_ri0_4, eg_shift4_2, eg_rd0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x10 & eg_shift4_2 & eg_rd0_4 unimpl +#:LD.SH_COND g_rp9_4, g_rd0_4, eg_cond12_4, eg_disp0_9 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1f & g_rd0_4 ; eg_cond12_4 & eg_op9_3=0x1 & eg_disp0_9 unimpl +#:LD.UH g_rp9_4, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0x12 & g_rd0_4 unimpl +#:LD.UH g_rp9_4, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0x16 & g_rd0_4 unimpl +#:LD.UH g_rp9_4, g_disp4_3, g_rd0_4 is g_op13_3=0x4 & g_rp9_4 & g_op7_2=0x1 & g_disp4_3 & g_rd0_4 unimpl +#:LD.UH g_rp9_4, g_rd0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x11 & g_rd0_4 ; eg_disp0_16 unimpl +#:LD.UH g_rb9_4, g_ri0_4, eg_shift4_2, eg_rd0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x14 & eg_shift4_2 & eg_rd0_4 unimpl +#:LD.UH_COND g_rp9_4, g_rd0_4, eg_cond12_4, eg_disp0_9 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1f & g_rd0_4 ; eg_cond12_4 & eg_op9_3=0x2 & eg_disp0_9 unimpl +#:LD.W g_rp9_4, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0x10 & g_rd0_4 unimpl +#:LD.W g_rp9_4, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0x14 & g_rd0_4 unimpl +#:LD.W g_rp9_4, g_disp4_5, g_rd0_4 is g_op13_3=0x3 & g_rp9_4 & g_disp4_5 & g_rd0_4 unimpl +#:LD.W g_rp9_4, g_rd0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0xf & g_rd0_4 ; eg_disp0_16 unimpl +#:LD.W g_rb9_4, g_ri0_4, eg_shift4_2, eg_rd0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0xc & eg_shift4_2 & eg_rd0_4 unimpl +#:LD.W g_rb9_4, g_ri0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x3e & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl +#:LD.W_COND g_rp9_4, g_rd0_4, eg_cond12_4, eg_disp0_9 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1f & g_rd0_4 ; eg_cond12_4 & eg_op9_3=0x0 & eg_disp0_9 unimpl +#:LDC.D g_rp0_4, eg_cop13_3, eg_rd9_3, eg_disp0_8 is g_op4_12=0xe9a & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x1 & eg_rd9_3 & eg_op8_1=0x0 & eg_disp0_8 unimpl +#:LDC.D g_rp0_4, eg_cop13_3, eg_rd9_3 is g_op4_12=0xefa & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rd9_3 & eg_op0_9=0x50 unimpl +#:LDC.D g_rp0_4, eg_cop13_3, eg_rd9_3, eg_shift4_2, eg_ri0_4 is g_op4_12=0xefa & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x1 & eg_rd9_3 & eg_op6_3=0x1 & eg_shift4_2 & eg_ri0_4 unimpl +#:LDC.W g_rp0_4, eg_cop13_3, eg_rd8_4, eg_disp0_8 is g_op4_12=0xe9a & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rd8_4 & eg_disp0_8 unimpl +#:LDC.W g_rp0_4, eg_cop13_3, eg_rd8_4 is g_op4_12=0xefa & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rd8_4 & eg_op0_8=0x40 unimpl +#:LDC.W g_rp0_4, eg_cop13_3, eg_rd8_4, eg_shift4_2, eg_ri0_4 is g_op4_12=0xefa & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x1 & eg_rd8_4 & eg_op6_2=0x0 & eg_shift4_2 & eg_ri0_4 unimpl +#:LDC0.D g_rp0_4, eg_disp12_4, eg_rd9_3, eg_disp0_8 is g_op4_12=0xf3a & g_rp0_4 ; eg_disp12_4 & eg_rd9_3 & eg_op8_1=0x0 & eg_disp0_8 unimpl +#:LDC0.W g_rp0_4, eg_disp12_4, eg_rd8_4, eg_disp0_8 is g_op4_12=0xf1a & g_rp0_4 ; eg_disp12_4 & eg_rd8_4 & eg_disp0_8 unimpl +#:LDCM.D g_rp0_4, eg_cop13_3, eg_update12_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op4_12=0xeda & g_rp0_4 ; eg_cop13_3 & eg_update12_1 & eg_op8_4=0x4 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl +#:LDCM.W g_rp0_4, eg_cop13_3, eg_update12_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op4_12=0xeda & g_rp0_4 ; eg_cop13_3 & eg_update12_1 & eg_op8_4=0x1 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl +#:LDCM.W g_rp0_4, eg_cop13_3, eg_update12_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op4_12=0xeda & g_rp0_4 ; eg_cop13_3 & eg_update12_1 & eg_op8_4=0x0 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl +#:LDDPC g_disp4_7, g_rd0_4 is g_op11_5=0x9 & g_disp4_7 & g_rd0_4 unimpl +#:LDDSP g_disp4_7, g_rd0_4 is g_op11_5=0x8 & g_disp4_7 & g_rd0_4 unimpl +#:LDINS.B g_rp9_4, g_rd0_4, eg_xpart13_1, eg_ypart12_1, eg_disp0_12 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1d & g_rd0_4 ; eg_op14_2=0x1 & eg_xpart13_1 & eg_ypart12_1 & eg_disp0_12 unimpl +#:LDINS.H g_rp9_4, g_rd0_4, eg_ypart12_1, eg_disp0_12 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1d & g_rd0_4 ; eg_op13_3=0x0 & eg_ypart12_1 & eg_disp0_12 unimpl +#:LDM g_update9_1, g_rp0_4, eg_regsel15_1, eg_regsel14_1, eg_regsel13_1, eg_regsel12_1, eg_regsel11_1, eg_regsel10_1, eg_regsel9_1, eg_regsel8_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op10_6=0x38 & g_update9_1 & g_op4_5=0x1c & g_rp0_4 ; eg_regsel15_1 & eg_regsel14_1 & eg_regsel13_1 & eg_regsel12_1 & eg_regsel11_1 & eg_regsel10_1 & eg_regsel9_1 & eg_regsel8_1 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl +#:LDMTS g_update9_1, g_rp0_4, eg_regsel15_1, eg_regsel14_1, eg_regsel13_1, eg_regsel12_1, eg_regsel11_1, eg_regsel10_1, eg_regsel9_1, eg_regsel8_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op10_6=0x39 & g_update9_1 & g_op4_5=0x1c & g_rp0_4 ; eg_regsel15_1 & eg_regsel14_1 & eg_regsel13_1 & eg_regsel12_1 & eg_regsel11_1 & eg_regsel10_1 & eg_regsel9_1 & eg_regsel8_1 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl +#:LDSWP.SH g_rp9_4, g_rd0_4, eg_disp0_12 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1d & g_rd0_4 ; eg_op12_4=0x2 & eg_disp0_12 unimpl +#:LDSWP.UH g_rp9_4, g_rd0_4, eg_disp0_12 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1d & g_rd0_4 ; eg_op12_4=0x3 & eg_disp0_12 unimpl +#:LDSWP.W g_rp9_4, g_rd0_4, eg_disp0_12 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1d & g_rd0_4 ; eg_op12_4=0x8 & eg_disp0_12 unimpl +#:LSL g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x94 & eg_rd0_4 unimpl +#:LSL g_shift9_4, g_shift4_1, g_rd0_4 is g_op13_3=0x5 & g_shift9_4 & g_op5_4=0xb & g_shift4_1 & g_rd0_4 unimpl +#:LSL g_rs9_4, g_rd0_4, eg_shift0_5 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op5_11=0xa8 & eg_shift0_5 unimpl +#:LSR g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0xa4 & eg_rd0_4 unimpl +#:LSR g_shift9_4, g_shift4_1, g_rd0_4 is g_op13_3=0x5 & g_shift9_4 & g_op5_4=0xc & g_shift4_1 & g_rd0_4 unimpl +#:LSR g_rs9_4, g_rd0_4, eg_shift0_5 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op5_11=0xb0 & eg_shift0_5 unimpl +#:MAC g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x34 & eg_rd0_4 unimpl +#:MACHH.D g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x16 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl +#:MACHH.W g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x12 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl +#:MACS.D g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x54 & eg_rd0_4 unimpl +#:MACSATHH.W g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x1a & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl +#:MACU.D g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x74 & eg_rd0_4 unimpl +#:MACWH.D g_rx9_4, g_ry0_4, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op5_11=0x64 & eg_ypart4_1 & eg_rd0_4 unimpl +#:MAX g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0xc4 & eg_rd0_4 unimpl +#:MCALL g_rp0_4, eg_disp0_16 is g_op4_12=0xf01 & g_rp0_4 ; eg_disp0_16 unimpl +#:MEMC g_offset0_4, eg_offset15_1, eg_imm0_15 is g_op4_12=0xf61 & g_offset0_4 ; eg_offset15_1 & eg_imm0_15 unimpl +#:MEMS g_offset0_4, eg_offset15_1, eg_imm0_15 is g_op4_12=0xf81 & g_offset0_4 ; eg_offset15_1 & eg_imm0_15 unimpl +#:MEMT g_offset0_4, eg_offset15_1, eg_imm0_15 is g_op4_12=0xfa1 & g_offset0_4 ; eg_offset15_1 & eg_imm0_15 unimpl +#:MFDR g_rd0_4, eg_dbgregaddr0_8 is g_op4_12=0xe5b & g_rd0_4 ; eg_op8_8=0x0 & eg_dbgregaddr0_8 unimpl +#:MFSR g_rd0_4, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op4_12=0xe1b & g_rd0_4 ; eg_op8_8=0x0 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl +#:MIN g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0xd4 & eg_rd0_4 unimpl +#:MOV g_imm4_8, g_rd0_4 is g_op12_4=0x3 & g_imm4_8 & g_rd0_4 unimpl +#:MOV g_imm9_4, g_imm4_1, g_rd0_4, eg_imm0_16 is g_op13_3=0x7 & g_imm9_4 & g_op5_4=0x3 & g_imm4_1 & g_rd0_4 ; eg_imm0_16 unimpl +#:MOV g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x9 & g_rd0_4 unimpl +#:MOV_COND g_rs9_4, g_rd0_4, eg_cond4_4 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op8_8=0x17 & eg_cond4_4 & eg_op0_4=0x0 unimpl +#:MOV_COND g_rd0_4, eg_cond8_4, eg_imm0_8 is g_op4_12=0xf9b & g_rd0_4 ; eg_op12_4=0x0 & eg_cond8_4 & eg_imm0_8 unimpl +#:MOVHI g_rd0_4, eg_imm0_16 is g_op4_12=0xfc1 & g_rd0_4 ; eg_imm0_16 unimpl +#:MTDR g_rs0_4, eg_dbgregaddr0_8 is g_op4_12=0xe7b & g_rs0_4 ; eg_op8_8=0x0 & eg_dbgregaddr0_8 unimpl +#:MTSR g_rs0_4, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op4_12=0xe3b & g_rs0_4 ; eg_op8_8=0x0 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl +#:MUL g_rs9_4, g_rd0_4 is g_op13_3=0x5 & g_rs9_4 & g_op4_5=0x13 & g_rd0_4 unimpl +#:MUL g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x24 & eg_rd0_4 unimpl +#:MUL g_rs9_4, g_rd0_4, eg_imm0_8 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op8_8=0x10 & eg_imm0_8 unimpl +#:MULHH.W g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x1e & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl +#:MULNHH.W g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x6 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl +#:MULNWH.D g_rx9_4, g_ry0_4, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op5_11=0x14 & eg_ypart4_1 & eg_rd0_4 unimpl +#:MULS.D g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x44 & eg_rd0_4 unimpl +#:MULSATHH.H g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x22 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl +#:MULSATHH.W g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x26 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl +#:MULSATRNDHH.H g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x2a & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl +#:MULSATRNDWH.W g_rx9_4, g_ry0_4, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op5_11=0x5c & eg_ypart4_1 & eg_rd0_4 unimpl +#:MULSATWH.W g_rx9_4, g_ry0_4, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op5_11=0x74 & eg_ypart4_1 & eg_rd0_4 unimpl +#:MULU.D g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x64 & eg_rd0_4 unimpl +#:MULWH.D g_rx9_4, g_ry0_4, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op5_11=0x6c & eg_ypart4_1 & eg_rd0_4 unimpl +#:MUSFR g_rs0_4 is g_op4_12=0x5d3 & g_rs0_4 unimpl +#:MUSTR g_rd0_4 is g_op4_12=0x5d2 & g_rd0_4 unimpl +#:MVCR.D g_rd1_3, eg_cop13_3, eg_rs9_3 is g_op4_12=0xefa & g_rd1_3 & g_op0_1=0x0 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rs9_3 & eg_op0_9=0x10 unimpl +#:MVCR.W g_rd0_4, eg_cop13_3, eg_rs8_4 is g_op4_12=0xefa & g_rd0_4 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rs8_4 & eg_op0_8=0x0 unimpl +#:MVRC.D g_rs1_3, eg_cop13_3, eg_rd9_3 is g_op4_12=0xefa & g_rs1_3 & g_op0_1=0x0 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rd9_3 & eg_op0_9=0x30 unimpl +#:MVRC.W g_rs0_4, eg_cop13_3, eg_rd8_4 is g_op4_12=0xefa & g_rs0_4 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rd8_4 & eg_op0_8=0x20 unimpl +#:NEG g_rd0_4 is g_op4_12=0x5c3 & g_rd0_4 unimpl +#:NOP is g_op0_16=0xd703 unimpl +#:OR g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x4 & g_rd0_4 unimpl +#:OR g_rx9_4, g_ry0_4, eg_shift4_5, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1e & g_ry0_4 ; eg_op9_7=0x8 & eg_shift4_5 & eg_rd0_4 unimpl +#:OR g_rx9_4, g_ry0_4, eg_shift4_5, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1e & g_ry0_4 ; eg_op9_7=0x9 & eg_shift4_5 & eg_rd0_4 unimpl +#:OR_COND g_rx9_4, g_ry0_4, eg_cond8_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1d & g_ry0_4 ; eg_op12_4=0xe & eg_cond8_4 & eg_op4_4=0x3 & eg_rd0_4 unimpl +#:ORH g_rd0_4, eg_imm0_16 is g_op4_12=0xea1 & g_rd0_4 ; eg_imm0_16 unimpl +#:ORL g_rd0_4, eg_imm0_16 is g_op4_12=0xe81 & g_rd0_4 ; eg_imm0_16 unimpl +#:PABS.SB g_rs0_4, eg_rd0_4 is g_op4_12=0xe00 & g_rs0_4 ; eg_op4_12=0x23e & eg_rd0_4 unimpl +#:PABS.SH g_rs0_4, eg_rd0_4 is g_op4_12=0xe00 & g_rs0_4 ; eg_op4_12=0x23f & eg_rd0_4 unimpl +#:PACKSH.UB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x24c & eg_rd0_4 unimpl +#:PACKSH.SB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x24d & eg_rd0_4 unimpl +#:PACKW.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x247 & eg_rd0_4 unimpl +#:PADD.B g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x230 & eg_rd0_4 unimpl +#:PADD.H g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x200 & eg_rd0_4 unimpl +#:PADDH.UB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x236 & eg_rd0_4 unimpl +#:PADDH.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x20c & eg_rd0_4 unimpl +#:PADDS.UB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x234 & eg_rd0_4 unimpl +#:PADDS.SB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x232 & eg_rd0_4 unimpl +#:PADDS.UH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x208 & eg_rd0_4 unimpl +#:PADDS.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x204 & eg_rd0_4 unimpl +#:PADDSUB.H g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x84 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl +#:PADDSUBH.SH g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x8a & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl +#:PADDSUBS.UH g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x88 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl +#:PADDSUBS.SH g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x86 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl +#:PADDX.H g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x202 & eg_rd0_4 unimpl +#:PADDXH.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x20e & eg_rd0_4 unimpl +#:PADDXS.UH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x20a & eg_rd0_4 unimpl +#:PADDXS.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x206 & eg_rd0_4 unimpl +#:PASR.B g_rs9_4, g_shift0_3, eg_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op3_6=0x0 & g_shift0_3 ; eg_op4_12=0x241 & eg_rd0_4 unimpl +#:PASR.H g_rs9_4, g_shift0_4, eg_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_shift0_4 ; eg_op4_12=0x244 & eg_rd0_4 unimpl +#:PAVG.UB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x23c & eg_rd0_4 unimpl +#:PAVG.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x23d & eg_rd0_4 unimpl +#:PLSL.B g_rs9_4, g_shift0_3, eg_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op3_6=0x0 & g_shift0_3 ; eg_op4_12=0x242 & eg_rd0_4 unimpl +#:PLSL.H g_rs9_4, g_shift0_4, eg_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_shift0_4 ; eg_op4_12=0x245 & eg_rd0_4 unimpl +#:PLSR.B g_rs9_4, g_shift0_3, eg_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op3_6=0x0 & g_shift0_3 ; eg_op4_12=0x243 & eg_rd0_4 unimpl +#:PLSR.H g_rs9_4, g_shift0_4, eg_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_shift0_4 ; eg_op4_12=0x246 & eg_rd0_4 unimpl +#:PMAX.UB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x238 & eg_rd0_4 unimpl +#:PMAX.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x239 & eg_rd0_4 unimpl +#:PMIN.UB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x23a & eg_rd0_4 unimpl +#:PMIN.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x23b & eg_rd0_4 unimpl +#:POPJC is g_op0_16=0xd713 unimpl +#:POPM g_regsel11_1, g_regsel10_1, g_regsel9_1, g_regsel8_1, g_regsel7_1, g_regsel6_1, g_regsel5_1, g_regsel4_1, g_returnflag3_1 is g_op12_4=0xd & g_regsel11_1 & g_regsel10_1 & g_regsel9_1 & g_regsel8_1 & g_regsel7_1 & g_regsel6_1 & g_regsel5_1 & g_regsel4_1 & g_returnflag3_1 & g_op0_3=0x2 unimpl +#:PREF g_rp0_4, eg_disp0_16 is g_op4_12=0xf21 & g_rp0_4 ; eg_disp0_16 unimpl +#:PSAD g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x240 & eg_rd0_4 unimpl +#:PSUB.B g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x231 & eg_rd0_4 unimpl +#:PSUB.H g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x201 & eg_rd0_4 unimpl +#:PSUBADD.H g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x85 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl +#:PSUBADDH.SH g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x8b & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl +#:PSUBADDS.UH g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x89 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl +#:PSUBADDS.SH g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x87 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl +#:PSUBH.UB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x237 & eg_rd0_4 unimpl +#:PSUBH.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x20d & eg_rd0_4 unimpl +#:PSUBS.UB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x235 & eg_rd0_4 unimpl +#:PSUBS.SB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x233 & eg_rd0_4 unimpl +#:PSUBS.UH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x209 & eg_rd0_4 unimpl +#:PSUBS.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x205 & eg_rd0_4 unimpl +#:PSUBX.H g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x203 & eg_rd0_4 unimpl +#:PSUBXH.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x20f & eg_rd0_4 unimpl +#:PSUBXS.UH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x20b & eg_rd0_4 unimpl +#:PSUBXS.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x207 & eg_rd0_4 unimpl +#:PUNPCKUB.H g_rs9_4, eg_returnflag4_1, eg_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op0_9=0x0 ; eg_op5_11=0x124 & eg_returnflag4_1 & eg_rd0_4 unimpl +#:PUNPCKSB.H g_rs9_4, eg_returnflag4_1, eg_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op0_9=0x0 ; eg_op5_11=0x125 & eg_returnflag4_1 & eg_rd0_4 unimpl +#:PUSHJC is g_op0_16=0xd723 unimpl +#:PUSHM g_regsel11_1, g_regsel10_1, g_regsel9_1, g_regsel8_1, g_regsel7_1, g_regsel6_1, g_regsel5_1, g_regsel4_1 is g_op12_4=0xd & g_regsel11_1 & g_regsel10_1 & g_regsel9_1 & g_regsel8_1 & g_regsel7_1 & g_regsel6_1 & g_regsel5_1 & g_regsel4_1 & g_op0_4=0x1 unimpl +#:RCALL g_disp4_8, g_disp0_2 is g_op12_4=0xc & g_disp4_8 & g_op2_2=0x3 & g_disp0_2 unimpl +#:RCALL g_disp9_4, g_disp4_1, eg_disp0_16 is g_op13_3=0x7 & g_disp9_4 & g_op5_4=0x5 & g_disp4_1 & g_op0_4=0x0 ; eg_disp0_16 unimpl +#:RET_COND g_cond4_4, g_rs0_4 is g_op8_8=0x5e & g_cond4_4 & g_rs0_4 unimpl +#:RETD is g_op0_16=0xd623 unimpl +#:RETE is g_op0_16=0xd603 unimpl +#:RETJ is g_op0_16=0xd633 unimpl +#:RETS is g_op0_16=0xd613 unimpl +#:RJMP g_disp4_8, g_disp0_2 is g_op12_4=0xc & g_disp4_8 & g_op2_2=0x2 & g_disp0_2 unimpl +#:ROL g_rd0_4 is g_op4_12=0x5cf & g_rd0_4 unimpl +#:ROR g_rd0_4 is g_op4_12=0x5d0 & g_rd0_4 unimpl +#:RSUB g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x2 & g_rd0_4 unimpl +#:RSUB g_rs9_4, g_rd0_4, eg_imm0_8 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op8_8=0x11 & eg_imm0_8 unimpl +#:RSUB_COND g_rd0_4, eg_cond8_4, eg_imm0_8 is g_op4_12=0xfbb & g_rd0_4 ; eg_op12_4=0x0 & eg_cond8_4 & eg_imm0_8 unimpl +#:SATADD.H g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x2c & eg_rd0_4 unimpl +#:SATADD.W g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0xc & eg_rd0_4 unimpl +#:SATRNDS g_rd0_4, eg_offset5_5, eg_shift0_5 is g_op4_12=0xf3b & g_rd0_4 ; eg_op10_6=0x0 & eg_offset5_5 & eg_shift0_5 unimpl +#:SATRNDU g_rd0_4, eg_offset5_5, eg_shift0_5 is g_op4_12=0xf3b & g_rd0_4 ; eg_op10_6=0x1 & eg_offset5_5 & eg_shift0_5 unimpl +#:SATS g_rd0_4, eg_offset5_5, eg_shift0_5 is g_op4_12=0xf1b & g_rd0_4 ; eg_op10_6=0x0 & eg_offset5_5 & eg_shift0_5 unimpl +#:SATSUB.H g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x3c & eg_rd0_4 unimpl +#:SATSUB.W g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x1c & eg_rd0_4 unimpl +#:SATSUB.W g_rs9_4, g_rd0_4, eg_imm0_16 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0xd & g_rd0_4 ; eg_imm0_16 unimpl +#:SATU g_rd0_4, eg_offset5_5, eg_shift0_5 is g_op4_12=0xf1b & g_rd0_4 ; eg_op10_6=0x1 & eg_offset5_5 & eg_shift0_5 unimpl +#:SBC g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x14 & eg_rd0_4 unimpl +#:SBR g_offset9_4, g_offset4_1, g_rd0_4 is g_op13_3=0x5 & g_offset9_4 & g_op5_4=0xd & g_offset4_1 & g_rd0_4 unimpl +#:SCALL is g_op0_16=0xd733 unimpl +#:SCR g_rd0_4 is g_op4_12=0x5c1 & g_rd0_4 unimpl +#:SLEEP eg_opcode0_8 is g_op0_16=0xe9b0 ; eg_op8_8=0x0 & eg_opcode0_8 unimpl +#:SR_COND g_cond4_4, g_rd0_4 is g_op8_8=0x5f & g_cond4_4 & g_rd0_4 unimpl +#:SSRF g_offset4_5 is g_op9_7=0x69 & g_offset4_5 & g_op0_4=0x3 unimpl +#:ST.B g_rp9_4, g_rs0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0xc & g_rs0_4 unimpl +#:ST.B g_rp9_4, g_rs0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0xf & g_rs0_4 unimpl +#:ST.B g_rp9_4, g_disp4_3, g_rs0_4 is g_op13_3=0x5 & g_rp9_4 & g_op7_2=0x1 & g_disp4_3 & g_rs0_4 unimpl +#:ST.B g_rp9_4, g_rs0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x16 & g_rs0_4 ; eg_disp0_16 unimpl +#:ST.B g_rb9_4, g_ri0_4, eg_shift4_2, eg_rs0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x2c & eg_shift4_2 & eg_rs0_4 unimpl +#:ST.B_COND g_rp9_4, g_rd0_4, eg_cond12_4, eg_disp0_9 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1f & g_rd0_4 ; eg_cond12_4 & eg_op9_3=0x7 & eg_disp0_9 unimpl +#:ST.D g_rp9_4, g_rs1_3 is g_op13_3=0x5 & g_rp9_4 & g_op4_5=0x12 & g_rs1_3 & g_op0_1=0x0 unimpl +#:ST.D g_rp9_4, g_rs1_3 is g_op13_3=0x5 & g_rp9_4 & g_op4_5=0x12 & g_rs1_3 & g_op0_1=0x1 unimpl +#:ST.D g_rp9_4, g_rs1_3 is g_op13_3=0x5 & g_rp9_4 & g_op4_5=0x11 & g_rs1_3 & g_op0_1=0x1 unimpl +#:ST.D g_rp9_4, g_rs1_3, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0xe & g_rs1_3 & g_op0_1=0x1 ; eg_disp0_16 unimpl +#:ST.D g_rb9_4, g_ri0_4, eg_shift4_2, eg_rs0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x20 & eg_shift4_2 & eg_rs0_4 unimpl +#:ST.H g_rp9_4, g_rs0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0xb & g_rs0_4 unimpl +#:ST.H g_rp9_4, g_rs0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0xe & g_rs0_4 unimpl +#:ST.H g_rp9_4, g_disp4_3, g_rs0_4 is g_op13_3=0x5 & g_rp9_4 & g_op7_2=0x0 & g_disp4_3 & g_rs0_4 unimpl +#:ST.H g_rp9_4, g_rs0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x15 & g_rs0_4 ; eg_disp0_16 unimpl +#:ST.H g_rb9_4, g_ri0_4, eg_shift4_2, eg_rs0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x28 & eg_shift4_2 & eg_rs0_4 unimpl +#:ST.H_COND g_rp9_4, g_rd0_4, eg_cond12_4, eg_disp0_9 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1f & g_rd0_4 ; eg_cond12_4 & eg_op9_3=0x6 & eg_disp0_9 unimpl +#:ST.W g_rp9_4, g_rs0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0xa & g_rs0_4 unimpl +#:ST.W g_rp9_4, g_rs0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0xd & g_rs0_4 unimpl +#:ST.W g_rp9_4, g_disp4_4, g_rs0_4 is g_op13_3=0x4 & g_rp9_4 & g_op8_1=0x1 & g_disp4_4 & g_rs0_4 unimpl +#:ST.W g_rp9_4, g_rs0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x14 & g_rs0_4 ; eg_disp0_16 unimpl +#:ST.W g_rb9_4, g_ri0_4, eg_shift4_2, eg_rs0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x24 & eg_shift4_2 & eg_rs0_4 unimpl +#:ST.W_COND g_rp9_4, g_rd0_4, eg_cond12_4, eg_disp0_9 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1f & g_rd0_4 ; eg_cond12_4 & eg_op9_3=0x5 & eg_disp0_9 unimpl +#:STC.D g_rp0_4, eg_cop13_3, eg_rs9_3, eg_disp0_8 is g_op4_12=0xeba & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x1 & eg_rs9_3 & eg_op8_1=0x0 & eg_disp0_8 unimpl +#:STC.D g_rp0_4, eg_cop13_3, eg_rs9_3 is g_op4_12=0xefa & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rs9_3 & eg_op0_9=0x70 unimpl +#:STC.D g_rp0_4, eg_cop13_3, eg_rs9_3, eg_shift4_2, eg_ri0_4 is g_op4_12=0xefa & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x1 & eg_rs9_3 & eg_op6_3=0x3 & eg_shift4_2 & eg_ri0_4 unimpl +#:STC.W g_rp0_4, eg_cop13_3, eg_rs8_4, eg_disp0_8 is g_op4_12=0xeba & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rs8_4 & eg_disp0_8 unimpl +#:STC.W g_rp0_4, eg_cop13_3, eg_rs8_4 is g_op4_12=0xefa & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rs8_4 & eg_op0_8=0x60 unimpl +#:STC.W g_rp0_4, eg_cop13_3, eg_rs8_4, eg_shift4_2, eg_ri0_4 is g_op4_12=0xefa & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x1 & eg_rs8_4 & eg_op6_2=0x2 & eg_shift4_2 & eg_ri0_4 unimpl +#:STC0.D g_rp0_4, eg_disp12_4, eg_rs9_3, eg_disp0_8 is g_op4_12=0xf7a & g_rp0_4 ; eg_disp12_4 & eg_rs9_3 & eg_op8_1=0x0 & eg_disp0_8 unimpl +#:STC0.W g_rp0_4, eg_disp12_4, eg_rs8_4, eg_disp0_8 is g_op4_12=0xf5a & g_rp0_4 ; eg_disp12_4 & eg_rs8_4 & eg_disp0_8 unimpl +#:STCM.D g_rp0_4, eg_cop13_3, eg_update12_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op4_12=0xeda & g_rp0_4 ; eg_cop13_3 & eg_update12_1 & eg_op8_4=0x5 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl +#:STCM.W g_rp0_4, eg_cop13_3, eg_update12_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op4_12=0xeda & g_rp0_4 ; eg_cop13_3 & eg_update12_1 & eg_op8_4=0x3 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl +#:STCM.W g_rp0_4, eg_cop13_3, eg_update12_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op4_12=0xeda & g_rp0_4 ; eg_cop13_3 & eg_update12_1 & eg_op8_4=0x2 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl +#:STCOND g_rp9_4, g_rs0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x17 & g_rs0_4 ; eg_disp0_16 unimpl +#:STDSP g_disp4_7, g_rs0_4 is g_op11_5=0xa & g_disp4_7 & g_rs0_4 unimpl +#:STHH.W g_rx9_4, g_ry0_4, eg_xpart13_1, eg_ypart12_1, eg_disp4_8, eg_rp0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1e & g_ry0_4 ; eg_op14_2=0x3 & eg_xpart13_1 & eg_ypart12_1 & eg_disp4_8 & eg_rp0_4 unimpl +#:STHH.W g_rx9_4, g_ry0_4, eg_xpart13_1, eg_ypart12_1, eg_ri8_4, eg_shift4_2, eg_rb0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1e & g_ry0_4 ; eg_op14_2=0x2 & eg_xpart13_1 & eg_ypart12_1 & eg_ri8_4 & eg_op6_2=0x0 & eg_shift4_2 & eg_rb0_4 unimpl +#:STM g_update9_1, g_rp0_4, eg_regsel15_1, eg_regsel14_1, eg_regsel13_1, eg_regsel12_1, eg_regsel11_1, eg_regsel10_1, eg_regsel9_1, eg_regsel8_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op10_6=0x3a & g_update9_1 & g_op4_5=0x1c & g_rp0_4 ; eg_regsel15_1 & eg_regsel14_1 & eg_regsel13_1 & eg_regsel12_1 & eg_regsel11_1 & eg_regsel10_1 & eg_regsel9_1 & eg_regsel8_1 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl +#:STMTS g_update9_1, g_rp0_4, eg_regsel15_1, eg_regsel14_1, eg_regsel13_1, eg_regsel12_1, eg_regsel11_1, eg_regsel10_1, eg_regsel9_1, eg_regsel8_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op10_6=0x3b & g_update9_1 & g_op4_5=0x1c & g_rp0_4 ; eg_regsel15_1 & eg_regsel14_1 & eg_regsel13_1 & eg_regsel12_1 & eg_regsel11_1 & eg_regsel10_1 & eg_regsel9_1 & eg_regsel8_1 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl +#:STSWP.H g_rp9_4, g_rs0_4, eg_disp0_12 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1d & g_rs0_4 ; eg_op12_4=0x9 & eg_disp0_12 unimpl +#:STSWP.W g_rp9_4, g_rs0_4, eg_disp0_12 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1d & g_rs0_4 ; eg_op12_4=0xa & eg_disp0_12 unimpl +#:SUB g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x1 & g_rd0_4 unimpl +#:SUB g_rx9_4, g_ry0_4, eg_shift4_2, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x4 & eg_shift4_2 & eg_rd0_4 unimpl +#:SUB g_imm4_8, g_rd0_4 is g_op12_4=0x2 & g_imm4_8 & g_rd0_4 unimpl +#:SUB g_imm9_4, g_imm4_1, g_rd0_4, eg_imm0_16 is g_op13_3=0x7 & g_imm9_4 & g_op5_4=0x1 & g_imm4_1 & g_rd0_4 ; eg_imm0_16 unimpl +#:SUB g_rs9_4, g_rd0_4, eg_imm0_16 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0xc & g_rd0_4 ; eg_imm0_16 unimpl +#:SUB_F_COND g_update9_1, g_rd0_4, eg_cond8_4, eg_imm0_8 is g_op10_6=0x3d & g_update9_1 & g_op4_5=0x1b & g_rd0_4 ; eg_op12_4=0x0 & eg_cond8_4 & eg_imm0_8 unimpl +#:SUB_COND g_rx9_4, g_ry0_4, eg_cond8_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1d & g_ry0_4 ; eg_op12_4=0xe & eg_cond8_4 & eg_op4_4=0x1 & eg_rd0_4 unimpl +#:SUBHH.W g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x3c & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl +#:SWAP.B g_rd0_4 is g_op4_12=0x5cb & g_rd0_4 unimpl +#:SWAP.BH g_rd0_4 is g_op4_12=0x5cc & g_rd0_4 unimpl +#:SWAP.H g_rd0_4 is g_op4_12=0x5ca & g_rd0_4 unimpl +#:SYNC eg_opcode0_8 is g_op0_16=0xebb0 ; eg_op8_8=0x0 & eg_opcode0_8 unimpl +#:TLBR is g_op0_16=0xd643 unimpl +#:TLBS is g_op0_16=0xd653 unimpl +#:TLBW is g_op0_16=0xd663 unimpl +#:TNBZ g_rd0_4 is g_op4_12=0x5ce & g_rd0_4 unimpl +#:TST g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x7 & g_rd0_4 unimpl +#:XCHG g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0xb4 & eg_rd0_4 unimpl diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_bit_operations.sinc b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_bit_operations.sinc new file mode 100644 index 0000000..df6b05c --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_bit_operations.sinc @@ -0,0 +1,505 @@ +#--------------------------------------------------------------------- +# 8.3.6 Bit Operations +#--------------------------------------------------------------------- + +#--------------------------------------------------------------------- +# BFEXTS - Bitfield extract and sign-extend +# I. {d,s} -> {0, 1, ..., 15} +# {bp5, w5} -> {0, 1, ..., 31} +#--------------------------------------------------------------------- + +# BFEXTS Format I +# Operation: Rd <- SE(Rs[bp5+w5-1:bp5]) +# Syntax: bfexts Rd, Rs, bp5, w5 +# 111d ddd1 1101 ssss 1011 00ff fffw wwww + +:BFEXTS rd9, RS0A, eoff5_5, elen0_5 is op13_3=0x7 & rd9 & op4_5=0x1d & RS0A ; + eop10_6=0x2c & eoff5_5 & elen0_5 +{ + shifted:4 = (RS0A >> eoff5_5); + mask:4 = (0xffffffff >> (32 - elen0_5)); + isolated:4 = shifted & mask; + + # Technically, elen0_5 can be 0, but result is undefined + # if that's the case so we're ok here. + signmask:4 = (0xffffffff << (elen0_5 - 1)); + test:4 = zext((signmask & isolated) != 0); + rd9 = (test * signmask) | isolated; + NZSTATUS(rd9); + C = rd9 s< 0; + CZNVTOSR(); +} + +#--------------------------------------------------------------------- +# BFEXTU - Bitfield extract and zero-extend +# I. {d,s} -> {0, 1, ..., 15} +# {bp5, w5} -> {0, 1, ..., 31} +#--------------------------------------------------------------------- + +# BFEXTU Format I +# Operation: Rd <- SE(Rs[bp5+w5-1:bp5]) +# Syntax: bfextu Rd, Rs, bp5, w5 +# 111d ddd1 1101 ssss 1011 00ff fffw wwww + +:BFEXTU rd9, RS0A, eoff5_5, elen0_5 is op13_3=0x7 & rd9 & op4_5=0x1d & RS0A ; + eop10_6=0x30 & eoff5_5 & elen0_5 +{ + shifted:4 = (RS0A >> eoff5_5); + mask:4 = (0xffffffff >> (32 - elen0_5)); + rd9 = shifted & mask; + NZSTATUS(rd9); + C = rd9 s< 0; + CZNVTOSR(); +} + +#--------------------------------------------------------------------- +# BFINS - Bitfield insert +# I. {d,s} -> {0, 1, ..., 15} +# {bp5, w5} -> {0, 1, ..., 31} +#--------------------------------------------------------------------- + +# BFINS Format I +# Operation: Rd[bp5+w5-1:bp5] <- Rs[w5-1:0] +# Syntax: bfins Rd, Rs, bp5, w5 +# 111d ddd1 1101 ssss 1101 00ff fffw wwww + +:BFINS rd9, RS0A, eoff5_5, elen0_5 is op13_3=0x7 & rd9 & op4_5=0x1d & RS0A ; + eop10_6=0x34 & eoff5_5 & elen0_5 +{ + lowmask:4 = (0xffffffff >> (32 - elen0_5)); + destmask:4 = ~(lowmask << eoff5_5); + rd9 = (rd9 & destmask) | ((RS0A & lowmask) << elen0_5); + NZSTATUS(rd9); + C = rd9 s< 0; + CZNVTOSR(); +} + +#--------------------------------------------------------------------- +# BLD - Bit load from register to C and Z +# I. d -> {0, 1, ..., 15} +# bp5 -> {0, 1, ..., 31} +#--------------------------------------------------------------------- + +# BLD Format I +# Operation: C <- Rd[bp5] +# Z <- Rd[bp5] +# Syntax: bld Rd, bp5 +# 1110 1101 1011 dddd 0000 0000 000f ffff + +:BLD rd0, eoff0_5 is op4_12=0xedb & rd0 ; + eop5_11=0x0 & eoff0_5 +{ + tmp:4 = (rd0 & (1 << eoff0_5)); + test:1 = (tmp != 0); + C = test; + Z = test; + CZNVTOSR(); +} + +#--------------------------------------------------------------------- +# BREV - Bit Reverse +# I. d -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# BREV Format I +# Operation: Rd[31:0] <- Rd[0:31] +# Syntax: brev Rd +# 0101 1100 1001 dddd + +# taken from http://graphics.stanford.edu/~seander/bithacks.html#ReverseParallel +# under the 32 bit word reverse + +:BREV rd0 is op4_12=0x5c9 & rd0 +{ + v:4 = rd0; + v = ((v >> 1) & 0x55555555) | ((v & 0x55555555) << 1); + v = ((v >> 2) & 0x33333333) | ((v & 0x33333333) << 2); + v = ((v >> 4) & 0x0F0F0F0F) | ((v & 0x0F0F0F0F) << 4); + v = ((v >> 8) & 0x00FF00FF) | ((v & 0x00FF00FF) << 8); + v = (v >> 16) | (v << 16); + rd0 = v; + ZSTATUS(rd0); +} + +#--------------------------------------------------------------------- +# BST - Copy C to register bit +# I. d -> {0, 1, ..., 15} +# bp5 -> {0, 1, ..., 31} +#--------------------------------------------------------------------- + +# BST Format I +# Operation: Rd[bp5] <- C +# Syntax: bst Rd, bp5 +# 1110 1111 1011 dddd 0000 0000 000f ffff + +:BST rd0, eoff0_5 is op4_12=0xefb & rd0 ; eop5_11=0x0 & eoff0_5 +{ + destbit:4 = (1 << eoff0_5); + cbool:4 = zext(C != 0); + rd0 = (rd0 & ~destbit) | (cbool * destbit); +} + +#--------------------------------------------------------------------- +# CASTS.{H,B} - Typecast to Signed Word +# I, II. d -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# CASTS.H Format I +# Operation: Rd[31:16] <- Rd[15] +# Syntax: casts.h Rd +# 0101 1100 1000 dddd + +:CASTS.H rd0 is op4_12=0x5c8 & rd0 +{ + rd0 = sext(rd0:2); +} + +# CASTS.B Format II +# Operation: Rd[31:8] <- Rd[7] +# Syntax: casts.b Rd +# 0101 1100 0110 dddd + +:CASTS.B rd0 is op4_12=0x5c6 & rd0 +{ + rd0 = sext(rd0:1); +} + +#--------------------------------------------------------------------- +# CASTU.{H,B} - Typecast to Unsigned Word +# I, II. d -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# CASTU.H Format I +# Operation: Rd[31:16] <- 0 +# Syntax: castu.h Rd +# 0101 1100 1000 dddd + +:CASTU.H rd0 is op4_12=0x5c7 & rd0 +{ + rd0 = zext(rd0:2); +} + +# CASTU.B Format II +# Operation: Rd[31:8] <- 0 +# Syntax: castu.b Rd +# 0101 1100 0110 dddd + +:CASTU.B rd0 is op4_12=0x5c5 & rd0 +{ + rd0 = zext(rd0:1); +} + +#--------------------------------------------------------------------- +# CBR - Clear Bit in Register +# I. d -> {0, 1, ..., 15} +# bp5 -> {0, 1, ..., 31} +#--------------------------------------------------------------------- + +# CBR Format I +# Operation: Rd[bp5] <- 0 +# Syntax: cbr Rd, bp5 +# 101f fff1 110f dddd + +CSBRH: off is bp9_4 & bp4_1 +[ off = (bp9_4 << 1) | bp4_1; ] +{ + tmp:4 = off; + export tmp; +} + +:CBR rd0, CSBRH is op13_3=0x5 & op5_4=0xe & CSBRH & rd0 +{ + destbit:4 = (1 << CSBRH); + rd0 = (rd0 & ~destbit); + ZSTATUS(rd0); +} + +#--------------------------------------------------------------------- +# CLZ - Count Leading Zeros +# I. {d,s} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# CLZ Format I +# Operation: temp <- 32 +# for (i = 31; i >= 0; i--) +# if (Rs[i] == 1) then +# temp <- 31 - i; +# break; +# Rd <- temp; +# Syntax: clz Rd, Rs +# 111s sss0 0000 dddd 0001 0010 0000 0000 + +:CLZ rd0, RS9A is op13_3=0x7 & op4_5=0x0 & rd0 & RS9A ; eop0_16=0x1200 +{ + continueloop:4 = 1; + count:4 = 0; + mask:4 = 0x80000000; + + test:4 = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + count = count + test * continueloop; + continueloop = continueloop * test; + mask = mask >> 1; + + test = zext((mask & RS9A) == 0); + rd0 = count + test * continueloop; + + Z = (rd0 == 0); + C = (rd0 == 32); + CZNVTOSR(); +} + +MEMSH: val is simm0_15 [ val = simm0_15 << 2; ] {export *[const]:4 val; } +:MEMC MEMSH, ctx_shift is op4_12=0xf61 & imm0_4 & ctx_shift; eb15 & MEMSH [ctx_shigh = imm0_4; ctx_slow = eb15;] { + tmp:4 = 0x00000001 << ctx_shift; + tmp = ~tmp; + tmpa:4 = *[RAM]:4 MEMSH; + *[RAM]:4 MEMSH = tmpa & tmp; +} + +:MEMS MEMSH, ctx_shift is op4_12=0xf81 & imm0_4 & ctx_shift; eb15 & MEMSH [ctx_shigh = imm0_4; ctx_slow = eb15;] { + tmp:4 = 0x00000001 << ctx_shift; + tmpa:4 = *[RAM]:4 MEMSH; + *[RAM]:4 MEMSH = tmpa & tmp; +} + +:MEMT MEMSH, ctx_shift is op4_12=0xfa1 & imm0_4 & ctx_shift; eb15 & MEMSH [ctx_shigh = imm0_4; ctx_slow = eb15;] { + tmp:4 = 0x00000001 << ctx_shift; + tmpa:4 = *[RAM]:4 MEMSH; + *[RAM]:4 MEMSH = tmpa ^ tmp; +} + +#--------------------------------------------------------------------- +# SBR - Clear Bit in Register +# I. d -> {0, 1, ..., 15} +# bp5 -> {0, 1, ..., 31} +#--------------------------------------------------------------------- + +# SBR Format I +# Operation: Rd[bp5] <- 1 +# Syntax: sbr Rd, bp5 +# 101f fff1 101f dddd + +:SBR rd0, CSBRH is op13_3=0x5 & op5_4=0xd & CSBRH & rd0 +{ + destbit:4 = (1 << CSBRH); + rd0 = (rd0 | destbit); + Z = 0; + CZNVTOSR(); +} + +#--------------------------------------------------------------------- +# SWAP.B - Swap Bytes +# I. d -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# SWAP.B Format I +# Operation: temp <- Rd +# Rd[31:24] <- temp[7:0] +# Rd[23:16] <- temp[15:8] +# Rd[15:8] <- temp[23:16] +# Rd[7:0] <- temp[31:24] +# Syntax: swap.b Rd +# 0101 1100 1011 dddd + +:SWAP.B rd0 is op4_12=0x5cb & rd0 +{ + temp:4 = rd0; + rd0[24,8] = temp[0,8]; + rd0[16,8] = temp[8,8]; + rd0[8,8] = temp[16,8]; + rd0[0,8] = temp[24,8]; +} + +#--------------------------------------------------------------------- +# SWAP.BH - Swap Bytes in Halfword +# I. d -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# SWAP.BH Format I +# Operation: temp <- Rd +# Rd[31:24] <- temp[23:16] +# Rd[23:16] <- temp[31:24] +# Rd[15:8] <- temp[7:0] +# Rd[7:0] <- temp[15:8] +# Syntax: swap.bh Rd +# 0101 1100 1100 dddd + +:SWAP.BH rd0 is op4_12=0x5cc & rd0 +{ + temp:4 = rd0; + rd0[24,8] = temp[16,8]; + rd0[16,8] = temp[24,8]; + rd0[8,8] = temp[0,8]; + rd0[0,8] = temp[8,8]; +} + +#--------------------------------------------------------------------- +# SWAP.H - Swap Halfwords +# I. d -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# SWAP.H Format I +# Operation: temp <- Rd +# Rd[31:24] <- temp[23:16] +# Rd[23:16] <- temp[31:24] +# Rd[15:8] <- temp[7:0] +# Rd[7:0] <- temp[15:8] +# Syntax: swap.h Rd +# 0101 1100 1010 dddd + +:SWAP.H rd0 is op4_12=0x5ca & rd0 +{ + temp:4 = rd0; + rd0[16,16] = temp[0,16]; + rd0[0,16] = temp[16,16]; +} diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_coprocessor_interface.sinc b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_coprocessor_interface.sinc new file mode 100644 index 0000000..254e3f2 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_coprocessor_interface.sinc @@ -0,0 +1,448 @@ +#--------------------------------------------------------------------- +# Coprocessor Interface +#--------------------------------------------------------------------- + +# COP decodes the coprocessor number for display purposes +# because the sleigh "dec" field attribute doesn't exist + +COPD: "CP0" is cp13_3=0x0 & altcp13_3 { tmp:1 = altcp13_3:1; export tmp; } +COPD: "CP1" is cp13_3=0x1 & altcp13_3 { tmp:1 = altcp13_3:1; export tmp; } +COPD: "CP2" is cp13_3=0x2 & altcp13_3 { tmp:1 = altcp13_3:1; export tmp; } +COPD: "CP3" is cp13_3=0x3 & altcp13_3 { tmp:1 = altcp13_3:1; export tmp; } +COPD: "CP4" is cp13_3=0x4 & altcp13_3 { tmp:1 = altcp13_3:1; export tmp; } +COPD: "CP5" is cp13_3=0x5 & altcp13_3 { tmp:1 = altcp13_3:1; export tmp; } +COPD: "CP6" is cp13_3=0x6 & altcp13_3 { tmp:1 = altcp13_3:1; export tmp; } +COPD: "CP7" is cp13_3=0x7 & altcp13_3 { tmp:1 = altcp13_3:1; export tmp; } + +# CRD decodes the coprocessor number for display purposes +# because the sleigh "dec" field attribute doesn't exist + +CRD: "CR0" is crd8_4=0x0 & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; } +CRD: "CR1" is crd8_4=0x1 & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; } +CRD: "CR2" is crd8_4=0x2 & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; } +CRD: "CR3" is crd8_4=0x3 & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; } +CRD: "CR4" is crd8_4=0x4 & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; } +CRD: "CR5" is crd8_4=0x5 & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; } +CRD: "CR6" is crd8_4=0x6 & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; } +CRD: "CR7" is crd8_4=0x7 & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; } +CRD: "CR8" is crd8_4=0x8 & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; } +CRD: "CR9" is crd8_4=0x9 & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; } +CRD: "CR10" is crd8_4=0xa & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; } +CRD: "CR11" is crd8_4=0xb & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; } +CRD: "CR12" is crd8_4=0xc & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; } +CRD: "CR13" is crd8_4=0xd & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; } +CRD: "CR14" is crd8_4=0xe & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; } +CRD: "CR15" is crd8_4=0xf & altcrd8_4 { tmp:1 = altcrd8_4:1; export tmp; } + +CRX: "CR0" is crx4_4=0x0 & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; } +CRX: "CR1" is crx4_4=0x1 & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; } +CRX: "CR2" is crx4_4=0x2 & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; } +CRX: "CR3" is crx4_4=0x3 & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; } +CRX: "CR4" is crx4_4=0x4 & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; } +CRX: "CR5" is crx4_4=0x5 & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; } +CRX: "CR6" is crx4_4=0x6 & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; } +CRX: "CR7" is crx4_4=0x7 & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; } +CRX: "CR8" is crx4_4=0x8 & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; } +CRX: "CR9" is crx4_4=0x9 & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; } +CRX: "CR10" is crx4_4=0xa & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; } +CRX: "CR11" is crx4_4=0xb & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; } +CRX: "CR12" is crx4_4=0xc & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; } +CRX: "CR13" is crx4_4=0xd & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; } +CRX: "CR14" is crx4_4=0xe & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; } +CRX: "CR15" is crx4_4=0xf & altcrx4_4 { tmp:1 = altcrx4_4:1; export tmp; } + +CRY: "CR0" is cry0_4=0x0 & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; } +CRY: "CR1" is cry0_4=0x1 & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; } +CRY: "CR2" is cry0_4=0x2 & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; } +CRY: "CR3" is cry0_4=0x3 & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; } +CRY: "CR4" is cry0_4=0x4 & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; } +CRY: "CR5" is cry0_4=0x5 & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; } +CRY: "CR6" is cry0_4=0x6 & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; } +CRY: "CR7" is cry0_4=0x7 & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; } +CRY: "CR8" is cry0_4=0x8 & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; } +CRY: "CR9" is cry0_4=0x9 & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; } +CRY: "CR10" is cry0_4=0xa & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; } +CRY: "CR11" is cry0_4=0xb & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; } +CRY: "CR12" is cry0_4=0xc & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; } +CRY: "CR13" is cry0_4=0xd & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; } +CRY: "CR14" is cry0_4=0xe & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; } +CRY: "CR15" is cry0_4=0xf & altcry0_4 { tmp:1 = altcry0_4:1; export tmp; } + +CPLoadAddress: is rp0=0xf ; eb15 { ldadd = inst_start; } # Rp=PC +CPLoadAddress: is rp0 ; eb15 { ldadd = rp0; } # Rp!=PC + +LDCMDinc7: ",CR14-CR15" is eb7=1 { tmp:1 = 14; tmpa:1 = 15; LoadCoProcessorDword(tmp,tmpa,ldadd); ldadd = ldadd + 8; } +LDCMDinc6: ",CR12-CR13" is eb6=1 { tmp:1 = 12; tmpa:1 = 13; LoadCoProcessorDword(tmp,tmpa,ldadd); ldadd = ldadd + 8; } +LDCMDinc5: ",CR10-CR11" is eb5=1 { tmp:1 = 10; tmpa:1 = 11; LoadCoProcessorDword(tmp,tmpa,ldadd); ldadd = ldadd + 8; } +LDCMDinc4: ",CR8-CR9" is eb4=1 { tmp:1 = 8; tmpa:1 = 9; LoadCoProcessorDword(tmp,tmpa,ldadd); ldadd = ldadd + 8; } +LDCMDinc3: ",CR6-CR7" is eb3=1 { tmp:1 = 6; tmpa:1 = 7; LoadCoProcessorDword(tmp,tmpa,ldadd); ldadd = ldadd + 8; } +LDCMDinc2: ",CR4-CR5" is eb2=1 { tmp:1 = 4; tmpa:1 = 5; LoadCoProcessorDword(tmp,tmpa,ldadd); ldadd = ldadd + 8; } +LDCMDinc1: ",CR2-CR3" is eb1=1 { tmp:1 = 2; tmpa:1 = 3; LoadCoProcessorDword(tmp,tmpa,ldadd); ldadd = ldadd + 8; } +LDCMDinc0: ",CR0-CR1" is eb0=1 { tmp:1 = 0; tmpa:1 = 1; LoadCoProcessorDword(tmp,tmpa,ldadd); ldadd = ldadd + 8; } + + +LDCMWinc15: ",CR15" is eb7=1 { tmp:1 = 15; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; } +LDCMWinc14: ",CR14" is eb6=1 { tmp:1 = 14; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; } +LDCMWinc13: ",CR13" is eb5=1 { tmp:1 = 13; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; } +LDCMWinc12: ",CR12" is eb4=1 { tmp:1 = 12; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; } +LDCMWinc11: ",CR11" is eb3=1 { tmp:1 = 11; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; } +LDCMWinc10: ",CR10" is eb2=1 { tmp:1 = 10; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; } +LDCMWinc9: ",CR9" is eb1=1 { tmp:1 = 9; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; } +LDCMWinc8: ",CR8" is eb0=1 { tmp:1 = 8; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; } + +LDCMWinc7: ",CR7" is eb7=1 { tmp:1 = 7; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; } +LDCMWinc6: ",CR6" is eb6=1 { tmp:1 = 6; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; } +LDCMWinc5: ",CR5" is eb5=1 { tmp:1 = 5; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; } +LDCMWinc4: ",CR4" is eb4=1 { tmp:1 = 4; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; } +LDCMWinc3: ",CR3" is eb3=1 { tmp:1 = 3; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; } +LDCMWinc2: ",CR2" is eb2=1 { tmp:1 = 2; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; } +LDCMWinc1: ",CR1" is eb1=1 { tmp:1 = 1; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; } +LDCMWinc0: ",CR0" is eb0=1 { tmp:1 = 0; LoadCoProcessorWord(tmp,ldadd); ldadd = ldadd + 4; } + +LDCMWinc15: is eb7=0 { } +LDCMWinc14: is eb6=0 { } +LDCMWinc13: is eb5=0 { } +LDCMWinc12: is eb4=0 { } +LDCMWinc11: is eb3=0 { } +LDCMWinc10: is eb2=0 { } +LDCMWinc9: is eb1=0 { } +LDCMWinc8: is eb0=0 { } + +LDCMWinc7: is eb7=0 { } +LDCMWinc6: is eb6=0 { } +LDCMWinc5: is eb5=0 { } +LDCMWinc4: is eb4=0 { } +LDCMWinc3: is eb3=0 { } +LDCMWinc2: is eb2=0 { } +LDCMWinc1: is eb1=0 { } +LDCMWinc0: is eb0=0 { } + +LDCMDinc7: is eb7=0 { } +LDCMDinc6: is eb6=0 { } +LDCMDinc5: is eb5=0 { } +LDCMDinc4: is eb4=0 { } +LDCMDinc3: is eb3=0 { } +LDCMDinc2: is eb2=0 { } +LDCMDinc1: is eb1=0 { } +LDCMDinc0: is eb0=0 { } + +LDCMpp: is rd0 ; eb12=0 { } +LDCMpp: "++" is rd0 ; eb12=1 { rd0 = ldadd; } + +LDCMDcommon: LDCMDinc0^LDCMDinc1^LDCMDinc2^LDCMDinc3^LDCMDinc4^LDCMDinc5^LDCMDinc6^LDCMDinc7 is + LDCMDinc0 & LDCMDinc1 & LDCMDinc2 & LDCMDinc3 & LDCMDinc4 & LDCMDinc5 & LDCMDinc6 & LDCMDinc7 +{ + build LDCMDinc7; + build LDCMDinc6; + build LDCMDinc5; + build LDCMDinc4; + build LDCMDinc3; + build LDCMDinc2; + build LDCMDinc1; + build LDCMDinc0; +} + +LDCMWLcommon: LDCMWinc0^LDCMWinc1^LDCMWinc2^LDCMWinc3^LDCMWinc4^LDCMWinc5^LDCMWinc6^LDCMWinc7 is + LDCMWinc0 & LDCMWinc1 & LDCMWinc2 & LDCMWinc3 & LDCMWinc4 & LDCMWinc5 & LDCMWinc6 & LDCMWinc7 +{ + build LDCMWinc7; + build LDCMWinc6; + build LDCMWinc5; + build LDCMWinc4; + build LDCMWinc3; + build LDCMWinc2; + build LDCMWinc1; + build LDCMWinc0; +} + +LDCMWHcommon: LDCMWinc8^LDCMWinc9^LDCMWinc10^LDCMWinc11^LDCMWinc12^LDCMWinc13^LDCMWinc14^LDCMWinc15 is + LDCMWinc8 & LDCMWinc9 & LDCMWinc10 & LDCMWinc11 & LDCMWinc12 & LDCMWinc13 & LDCMWinc14 & LDCMWinc15 +{ + build LDCMWinc15; + build LDCMWinc14; + build LDCMWinc13; + build LDCMWinc12; + build LDCMWinc11; + build LDCMWinc10; + build LDCMWinc9; + build LDCMWinc8; +} + + +STCMDdec7: ",CR14-CR15" is eb7=1 { ldadd = ldadd - 8; tmp:1 = 14; tmpa:1 = 15; storeCoprocessorDword(tmp,tmpa,ldadd); } +STCMDdec6: ",CR12-CR13" is eb6=1 { ldadd = ldadd - 8; tmp:1 = 12; tmpa:1 = 13; storeCoprocessorDword(tmp,tmpa,ldadd); } +STCMDdec5: ",CR10-CR11" is eb5=1 { ldadd = ldadd - 8; tmp:1 = 10; tmpa:1 = 11; storeCoprocessorDword(tmp,tmpa,ldadd); } +STCMDdec4: ",CR8-CR9" is eb4=1 { ldadd = ldadd - 8; tmp:1 = 8; tmpa:1 = 9; storeCoprocessorDword(tmp,tmpa,ldadd); } +STCMDdec3: ",CR6-CR7" is eb3=1 { ldadd = ldadd - 8; tmp:1 = 6; tmpa:1 = 7; storeCoprocessorDword(tmp,tmpa,ldadd); } +STCMDdec2: ",CR4-CR5" is eb2=1 { ldadd = ldadd - 8; tmp:1 = 4; tmpa:1 = 5; storeCoprocessorDword(tmp,tmpa,ldadd); } +STCMDdec1: ",CR2-CR3" is eb1=1 { ldadd = ldadd - 8; tmp:1 = 2; tmpa:1 = 3; storeCoprocessorDword(tmp,tmpa,ldadd); } +STCMDdec0: ",CR0-CR1" is eb0=1 { ldadd = ldadd - 8; tmp:1 = 0; tmpa:1 = 1; storeCoprocessorDword(tmp,tmpa,ldadd); } + + +STCMWdec15: ",CR15" is eb7=1 { ldadd = ldadd - 4; tmp:1 = 15; storeCoprocessorWord(tmp,ldadd); } +STCMWdec14: ",CR14" is eb6=1 { ldadd = ldadd - 4; tmp:1 = 14; storeCoprocessorWord(tmp,ldadd); } +STCMWdec13: ",CR13" is eb5=1 { ldadd = ldadd - 4; tmp:1 = 13; storeCoprocessorWord(tmp,ldadd); } +STCMWdec12: ",CR12" is eb4=1 { ldadd = ldadd - 4; tmp:1 = 12; storeCoprocessorWord(tmp,ldadd); } +STCMWdec11: ",CR11" is eb3=1 { ldadd = ldadd - 4; tmp:1 = 11; storeCoprocessorWord(tmp,ldadd); } +STCMWdec10: ",CR10" is eb2=1 { ldadd = ldadd - 4; tmp:1 = 10; storeCoprocessorWord(tmp,ldadd); } +STCMWdec9: ",CR9" is eb1=1 { ldadd = ldadd - 4; tmp:1 = 9; storeCoprocessorWord(tmp,ldadd); } +STCMWdec8: ",CR8" is eb0=1 { ldadd = ldadd - 4; tmp:1 = 8; storeCoprocessorWord(tmp,ldadd); } + +STCMWdec7: ",CR7" is eb7=1 { ldadd = ldadd - 4; tmp:1 = 7; storeCoprocessorWord(tmp,ldadd); } +STCMWdec6: ",CR6" is eb6=1 { ldadd = ldadd - 4; tmp:1 = 6; storeCoprocessorWord(tmp,ldadd); } +STCMWdec5: ",CR5" is eb5=1 { ldadd = ldadd - 4; tmp:1 = 5; storeCoprocessorWord(tmp,ldadd); } +STCMWdec4: ",CR4" is eb4=1 { ldadd = ldadd - 4; tmp:1 = 4; storeCoprocessorWord(tmp,ldadd); } +STCMWdec3: ",CR3" is eb3=1 { ldadd = ldadd - 4; tmp:1 = 3; storeCoprocessorWord(tmp,ldadd); } +STCMWdec2: ",CR2" is eb2=1 { ldadd = ldadd - 4; tmp:1 = 2; storeCoprocessorWord(tmp,ldadd); } +STCMWdec1: ",CR1" is eb1=1 { ldadd = ldadd - 4; tmp:1 = 1; storeCoprocessorWord(tmp,ldadd); } +STCMWdec0: ",CR0" is eb0=1 { ldadd = ldadd - 4; tmp:1 = 0; storeCoprocessorWord(tmp,ldadd); } + +STCMWdec15: is eb7=0 { } +STCMWdec14: is eb6=0 { } +STCMWdec13: is eb5=0 { } +STCMWdec12: is eb4=0 { } +STCMWdec11: is eb3=0 { } +STCMWdec10: is eb2=0 { } +STCMWdec9: is eb1=0 { } +STCMWdec8: is eb0=0 { } + +STCMWdec7: is eb7=0 { } +STCMWdec6: is eb6=0 { } +STCMWdec5: is eb5=0 { } +STCMWdec4: is eb4=0 { } +STCMWdec3: is eb3=0 { } +STCMWdec2: is eb2=0 { } +STCMWdec1: is eb1=0 { } +STCMWdec0: is eb0=0 { } + +STCMDdec7: is eb7=0 { } +STCMDdec6: is eb6=0 { } +STCMDdec5: is eb5=0 { } +STCMDdec4: is eb4=0 { } +STCMDdec3: is eb3=0 { } +STCMDdec2: is eb2=0 { } +STCMDdec1: is eb1=0 { } +STCMDdec0: is eb0=0 { } + +STCMDcommon: STCMDdec0^STCMDdec1^STCMDdec2^STCMDdec3^STCMDdec4^STCMDdec5^STCMDdec6^STCMDdec7 is + STCMDdec0 & STCMDdec1 & STCMDdec2 & STCMDdec3 & STCMDdec4 & STCMDdec5 & STCMDdec6 & STCMDdec7 +{ + build STCMDdec0; + build STCMDdec1; + build STCMDdec2; + build STCMDdec3; + build STCMDdec4; + build STCMDdec5; + build STCMDdec6; + build STCMDdec7; +} + +STCMWLcommon: STCMWdec0^STCMWdec1^STCMWdec2^STCMWdec3^STCMWdec4^STCMWdec5^STCMWdec6^STCMWdec7 is + STCMWdec0 & STCMWdec1 & STCMWdec2 & STCMWdec3 & STCMWdec4 & STCMWdec5 & STCMWdec6 & STCMWdec7 +{ + build STCMWdec0; + build STCMWdec1; + build STCMWdec2; + build STCMWdec3; + build STCMWdec4; + build STCMWdec5; + build STCMWdec6; + build STCMWdec7; +} + +STCMWHcommon: STCMWdec8^STCMWdec9^STCMWdec10^STCMWdec11^STCMWdec12^STCMWdec13^STCMWdec14^STCMWdec15 is + STCMWdec8 & STCMWdec9 & STCMWdec10 & STCMWdec11 & STCMWdec12 & STCMWdec13 & STCMWdec14 & STCMWdec15 +{ + build STCMWdec8; + build STCMWdec9; + build STCMWdec10; + build STCMWdec11; + build STCMWdec12; + build STCMWdec13; + build STCMWdec14; + build STCMWdec15; +} + + +STCMmm: is rd0 ; eb12=0 { } +STCMmm: "--" is rd0 ; eb12=1 { rd0 = ldadd; } + +:COP COPD,CRD,CRX,CRY,ctx_coop is op11_5=0x1c & op4_5=0x1a & op9_2 & op0_4 & ctx_coop; + eop12_1 & COPD & CRD & CRX & CRY [ctx_cohi = op9_2; ctx_comid = op0_4; ctx_colow = eop12_1;] { + tmp:1 = ctx_coop; + CoprocessorOp(COPD,CRD,CRX,CRY,tmp); +} + +#--------------------------------------------------------------------- +# LDC.{D,W} - Load Coprocessor +#--------------------------------------------------------------------- + +# LDC.{D,W} Format I +# 1110 1001 1010 pppp CCC1 DDD0 nnnn nnnn + +:LDC.D COPD,CRD,RPwDisp8 is (op4_12=0xe9a; + eop12_1=0x1 & crd8_1=0x0 & COPD & CRD) + & RPwDisp8 { + loadCoprocessorDWord(COPD, CRD, RPwDisp8); +} + +# LDC.{D,W} Format II +# 1110 1111 1010 pppp CCC0 DDD0 0101 0000 + +:LDC.D COPD,CRD,RPdDec0 is op4_12=0xefa & RPdDec0; + eop12_1=0x0 & crd8_1=0x0 & eop0_8=0x50 + & COPD & CRD { + loadCoprocessorDWord(COPD, CRD, RPdDec0); +} + +# LDC.{D,W} Format III +# NOTE: documentation says bits 16-19 are pppp, but we assume they meant bbbb +# 1110 1111 1010 bbbb CCC1 DDD0 01tt iiii + +:LDC.D COPD,CRD,RBShift0 is (op4_12=0xefa; + eop12_1=0x1 & crd8_1=0x0 & eop6_2=0x1 + & COPD & CRD) & RBShift0 { + loadCoprocessorDWord(COPD, CRD, RBShift0); +} + +# LDC.{D,W} Format IV +# 1110 1001 1010 pppp CCC0 DDDD nnnn nnnn + +:LDC.W COPD,CRD,RPwDisp8 is (op4_12=0xe9a; + eop12_1=0x0 & COPD & CRD) & RPwDisp8 { + loadCoprocessorWord(COPD, CRD, RPwDisp8); +} + +# LDC.{D,W} Format V +# 1110 1111 1010 pppp CCC1 DDDD 0100 0000 + +:LDC.W COPD,CRD,RPwDec0 is op4_12=0xefa & RPwDec0; + eop12_1=0x1 & eop0_8=0x40 & COPD & CRD { + loadCoprocessorWord(COPD, CRD, RPwDec0); +} + +# LDC.{D,W} Format VI +# NOTE: documentation says bits 16-19 are pppp, but we assume they meant bbbb +# 1110 1111 1010 bbbb CCC1 DDDD 00tt iiii + +:LDC.W COPD,CRD,RBShift0 is (op4_12=0xefa; + eop12_1=0x1 & eop6_2=0x0 & COPD & CRD) + & RBShift0 { + loadCoprocessorWord(COPD, CRD, RBShift0); +} + +#--------------------------------------------------------------------- +# LDC0.{D,W} - Load Coprocessor 0 +#--------------------------------------------------------------------- + +# LDC0.{D,W} Format I +# 1111 0011 1010 pppp nnnn DDD0 nnnn nnnn + +:LDC0.D "CP0," CRD,RPwDisp12 is (op4_12=0xf3a; crd8_1=0x0 & CRD) & RPwDisp12 { + cp:1 = 0; + loadCoprocessorDWord(cp, CRD, RPwDisp12); +} + +# LDC0.{D,W} Format II +# 1111 0001 1010 pppp nnnn DDDD nnnn nnnn + +:LDC0.W "CP0," CRD,RPwDisp12 is (op4_12=0xf1a; CRD) & RPwDisp12 { + cp:1 = 0; + loadCoprocessorDWord(cp, CRD, RPwDisp12); +} + + +:LDCM.D ecop13_3,rp0^LDCMpp^LDCMDcommon is (op4_12=0xeda & rp0 ; ecop13_3 & eop8_4=0x4 & LDCMDcommon) & LDCMpp & CPLoadAddress { + build CPLoadAddress; + build LDCMDcommon; + build LDCMpp; +} + +:LDCM.W ecop13_3,rp0^LDCMpp^LDCMWHcommon is (op4_12=0xeda & rp0 ; ecop13_3 & eop8_4=0x1 & LDCMWHcommon) & LDCMpp & CPLoadAddress { + build CPLoadAddress; + build LDCMWHcommon; + build LDCMpp; +} + +:LDCM.W ecop13_3,rp0^LDCMpp^LDCMWLcommon is (op4_12=0xeda & rp0 ; ecop13_3 & eop8_4=0x0 & LDCMWLcommon) & LDCMpp & CPLoadAddress { + build CPLoadAddress; + build LDCMWLcommon; + build LDCMpp; +} + +:MVCR.D COPD,rd0,CRD is op4_12=0xefa & b0=0x0 & rd0; COPD & eb12=0x0 & CRD & eop0_9=0x10 { + CoProcessorDWordToReg(COPD, CRD, rd0); +} +:MVCR.W COPD,rd0,CRD is op4_12=0xefa & b0=0x0 & rd0; COPD & eb12=0x0 & CRD & eop0_8=0x0 { + CoProcessorWordToReg(COPD, CRD, rd0); +} + +:MVRC.D COPD,CRD,rs0 is op4_12=0xefa & b0=0x0 & rs0; COPD & eb12=0x0 & CRD & eop0_9=0x30 { + RegToCoProcessorDWord(COPD, CRD, rs0); +} +:MVRC.W COPD,CRD,rs0 is op4_12=0xefa & b0=0x0 & rs0; COPD & eb12=0x0 & CRD & eop0_9=0x20 { + RegToCoProcessorWord(COPD, CRD, rs0); +} + +:STC.D COPD,RPwDisp8,CRD is (op4_12=0xeba; + eop12_1=0x1 & crd8_1=0x0 & COPD & CRD) + & RPwDisp8 { + storeCoprocessorDword(COPD, CRD, RPwDisp8); +} + +:STC.D COPD,RPdDec0,CRD is op4_12=0xefa & RPdDec0; + eop12_1=0x0 & crd8_1=0x0 & eop0_8=0x70 + & COPD & CRD { + storeCoprocessorDword(COPD, CRD, RPdDec0); +} + +:STC.D COPD,RBShift0,CRD is (op4_12=0xefa; + eop12_1=0x1 & crd8_1=0x0 & eop6_2=0x3 + & COPD & CRD) & RBShift0 { + storeCoprocessorDword(COPD, CRD, RBShift0); +} + +:STC.W COPD,RPwDisp8,CRD is (op4_12=0xeba; + eop12_1=0x0 & COPD & CRD) & RPwDisp8 { + storeCoprocessorWord(COPD, CRD, RPwDisp8); +} + +:STC.W COPD,RPwDec0,CRD is op4_12=0xefa & RPwDec0; + eop12_1=0x1 & eop0_8=0x60 & COPD & CRD { + storeCoprocessorWord(COPD, CRD, RPwDec0); +} + +:STC.W COPD,RBShift0,CRD is (op4_12=0xefa; + eop12_1=0x1 & eop6_2=0x2 & COPD & CRD) + & RBShift0 { + storeCoprocessorWord(COPD, CRD, RBShift0); +} + +:STC0.D "CP0," CRD,RPwDisp12 is (op4_12=0xf7a; crd8_1=0x0 & CRD) & RPwDisp12 { + cp:1 = 0; + storeCoprocessorDword(cp, CRD, RPwDisp12); +} + +:STC0.W "CP0," CRD,RPwDisp12 is (op4_12=0xf5a; CRD) & RPwDisp12 { + cp:1 = 0; + storeCoprocessorWord(cp, CRD, RPwDisp12); +} + +:STCM.D ecop13_3,STCMmm^rp0^STCMDcommon is (op4_12=0xeda & rp0 ; ecop13_3 & eop8_4=0x5 & STCMDcommon) & STCMmm & CPLoadAddress { + build CPLoadAddress; + build STCMDcommon; + build STCMmm; +} + +:STCM.W ecop13_3,STCMmm^rp0^STCMWHcommon is (op4_12=0xeda & rp0 ; ecop13_3 & eop8_4=0x3 & STCMWHcommon) & STCMmm & CPLoadAddress { + build CPLoadAddress; + build STCMWHcommon; + build STCMmm; +} + +:STCM.W ecop13_3,STCMmm^rp0^STCMWLcommon is (op4_12=0xeda & rp0 ; ecop13_3 & eop8_4=0x2 & STCMWLcommon) & STCMmm & CPLoadAddress { + build CPLoadAddress; + build STCMWLcommon; + build STCMmm; +} + diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_data_transfer.sinc b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_data_transfer.sinc new file mode 100644 index 0000000..e5253aa --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_data_transfer.sinc @@ -0,0 +1,1325 @@ +#--------------------------------------------------------------------- +# 8.3.9 Data Transfer +#--------------------------------------------------------------------- + +#--------------------------------------------------------------------- +# 8.3.9.1 Move/Load Immediate Operations +#--------------------------------------------------------------------- + +#--------------------------------------------------------------------- +# MOV - Move Data Into Register +#--------------------------------------------------------------------- + +# MOV Format I +# 0011 iiii iiii dddd + +:MOV rd0, imm4_8 is op13_3=0x1 & op12_1=1 & rd0 & imm4_8 { + rd0 = imm4_8; +} + +# MOV Format II +# 111i iii0 011i dddd iiii iiii iiii iiii + +:MOV rd0, imm is op13_3=0x7 & op5_4=0x3 & imm9_4 & imm4_1 & rd0; imm16 + [ imm = (imm9_4 << 17) | (imm4_1 << 16) | imm16; ] +{ + rd0 = imm; +} + +# MOV Format III +# 000s sss0 1001 dddd + +:MOV rd0, rs9 is op13_3=0x0 & op4_5=0x09 & rd0 & rs9 { + rd0 = rs9; +} + +#--------------------------------------------------------------------- +# MOV{cond4} - Conditional Move Register +# I. {d, s} -> {0, 1, ..., 15} +# cond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al} +# II. d -> {0, 1, ..., 15} +# cond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al} +# imm -> {-128, -127, ..., 127} +#--------------------------------------------------------------------- + +# MOV{cond4} Format I +# Operation: if (cond4) +# Rd <- Rs +# Syntax: mov{cond4} Rd, Rs +# 111s sss0 0000 dddd 0001 0111 cccc 0000 + +:MOV^{ECOND_4_4} rd0, rs9 is op13_3=0x7 & op4_5=0 & rd0 & rs9; + eop8_8=0x17 & eop0_4=0 & ECOND_4_4 +{ + build ECOND_4_4; + rd0 = rs9; +} + +# MOV{cond4} Format II +# Operation: if (cond4) +# Rd <- SE(imm8) +# Syntax: mov{cond4} Rd, imm +# 1111 1001 1011 dddd 0000 cccc iiii iiii + +:MOV^{ECOND_8_4} rd0, simm0_8 is op4_12=0xf9b & rd0 ; + eop12_4=0 & simm0_8 & ECOND_8_4 +{ + build ECOND_8_4; + rd0 = simm0_8; +} + +:MOVH rd0, imm16 is op4_12=0xfc1 & rd0 ; imm16 { + rd0 = imm16 << 16; +} + +#--------------------------------------------------------------------- +# 8.3.9.2 Load/Store Operations +#--------------------------------------------------------------------- + +#--------------------------------------------------------------------- +# LD.D - Load Doubleword +# I-V. d -> {0, 2, ..., 14} +# IV. disp -> {-32768, -32767, ..., 32767} +# V. sa -=> {0, 1, 2, 3} +#--------------------------------------------------------------------- + +# LD.D Format I +# Operation: Rd+1:Rd <- *(Rp) +# Rp <- Rp + 8; +# Syntax: ld.d Rd, Rp++ +# 101p ppp1 0000 ddd1 + +:LD.D rd0_low, RPdInc is op13_3=0x5 & op4_5=0x10 & b0=1 & RPdInc & rd0 & rd0_hi & rd0_low +{ + rd0_hi = *:4 RPdInc; + rd0_low = *:4 (RPdInc + 4); +} + +# LD.D Format II +# Operation: Rp <- Rp - 8; +# Rd+1:Rd <- *(Rp) +# Syntax: ld.d Rd, --Rp +# 101p ppp1 0001 ddd0 + +:LD.D rd0_low, RPdDec is op13_3=0x5 & op4_5=0x11 & b0=0 & RPdDec & rd0 & rd0_hi & rd0_low +{ + rd0_hi = *:4 RPdDec; + rd0_low = *:4 (RPdDec + 4); +} + +# LD.D Format III +# Operation: Rd+1:Rd <- *(Rp) +# Syntax: ld.d Rd, Rp +# 101p ppp1 0000 ddd0 + +:LD.D rd0_low, rp9 is op13_3=0x5 & op4_5=0x10 & b0=0 & rp9 & rd0 & rd0_hi & rd0_low +{ + rd0_hi = *:4 rp9; + rd0_low = *:4 (rp9 + 4); +} + +# LD.D Format IV +# Operation: Rd+1:Rd <- *(Rp + SE(disp16)) +# Syntax: ld.d Rd, Rp[disp16] +# 111p ppp0 1110 ddd0 nnnn nnnn nnnn nnnn + +:LD.D rd0_low, RPDisp16 is (op13_3=0x7 & op4_5=0xe + & b0=0 & rd0 & rd0_hi & rd0_low) ... & RPDisp16 +{ + rd0_hi = *:4 RPDisp16; + rd0_low = *:4 (RPDisp16 + 4); +} + +# LD.D Format V +# Operation: Rd+1:Rd <- *(Rb + (Ri << sa2)) +# Syntax: ld.d Rd, Rb[Ri< {0, 1, ..., 15} +# disp -> {0, 4, ..., 508} +#--------------------------------------------------------------------- + +# LDDPC Format I +# Operation: Rd <- *((PC && 0xfffffffc) + (ZE(disp7) << 2)) +# Syntax: lddpc Rd, PC[disp] +# 0100 1nnn nnnn dddd + +LDDPCdisp: disp is disp4_7 +[ disp = (inst_start & 0xfffffffc) + (disp4_7 << 2); ] +{ + export *:4 disp; +} + +:LDDPC rd0, LDDPCdisp is op11_5=0x9 & LDDPCdisp & rd0 +{ + rd0 = LDDPCdisp; +} + +:LDDPC rd0, LDDPCdisp is op11_5=0x9 & LDDPCdisp & rd0 & rd0=0xf +{ + PC = LDDPCdisp; + goto [PC]; +} + +#--------------------------------------------------------------------- +# LDDSP - Load SP-relative with Displacement +# I. d -> {0, 1, ..., 15} +# disp -> {0, 4, ..., 508} +#--------------------------------------------------------------------- + +# LDDSP Format I +# Operation: Rd <- *((SP && 0xfffffffc) + (ZE(disp7) << 2)) +# Syntax: lddsp Rd, SP[disp] +# 0100 0nnn nnnn dddd + +:LDDSP rd0^", SP["^disp^"]" is op11_5=0x8 & disp4_7 & rd0 +[ disp = (disp4_7 << 2); ] +{ + ptr:4 = (SP & 0xfffffffc) + disp; + # assuming SP was pointing into RAM... + rd0 = * ptr; +} + +:LDDSP rd0^", SP["^disp^"]" is op11_5=0x8 & disp4_7 & rd0 & rd0=0xf +[ disp = (disp4_7 << 2); ] +{ + ptr:4 = (SP & 0xfffffffc) + disp; + # assuming SP was pointing into RAM... + goto [ ptr ]; +} + +LDBP: "B" is imm12_2=0 {} +LDBP: "L" is imm12_2=1 {} +LDBP: "U" is imm12_2=2 {} +LDBP: "T" is imm12_2=3 {} +:LDINS.B rd0:LDBP, rp9"["disp0_11"]" is op13_3=0x7 & op4_5=0x1d & rd0 & rp9 ; eop14_2=0x1 & LDBP & disp0_11 & imm12_2 { + tmp:4 = disp0_11; + tmpa:4 = rp9 + tmp; + tmpb:1 = *[RAM]:1 tmpa; + tmpc:4 = zext(tmpb); + tmpd:4 = tmpc << (8 * imm12_2); + tmpe:4 = 0xff; + tmpe = tmpe << (8 * imm12_2); + tmpf:4 = rp9 & ~tmpe; + rp9 = tmpf | tmpd; +} + +LDSHIFT12: val is disp0_11 [ val = disp0_11 << 1; ] { export *[const]:2 val; } +LDHP: "B" is eb12=0 {} +LDHP: "T" is eb12=1 {} +:LDINS.H rd0:LDHP, rp9[LDSHIFT12] is op13_3=0x7 & op4_5=0x1d & rd0 & rp9 ; cp13_3=0x0 & eb12 & LDHP & LDSHIFT12 { + tmp:4 = sext(LDSHIFT12); + tmpa:4 = rp9 + tmp; + tmpb:2 = *[RAM]:2 tmpa; + tmpc:4 = zext(tmpb); + tmpd:4 = tmpc << (16 * eb12); + tmpe:4 = 0xffff; + tmpe = tmpe << (16 * eb12); + tmpf:4 = rp9 & ~tmpe; + rp9 = tmpf | tmpd; +} + + +LDSTSWPH: val is disp0_12 [ val = disp0_12 << 1; ] { export *[const]:2 val; } +LDSTSWPW: val is disp0_12 [ val = disp0_12 << 2; ] { export *[const]:2 val; } + +:LDSWP.SH rd0, rp9[LDSTSWPH] is op13_3=0x7 & op4_5=0x1d & rp9 & rd0 ; eop12_4=0x2 & LDSTSWPH { + tmp:4 = sext(LDSTSWPH); + tmpa:4 = rp9 + tmp; + tmpb:2 = *[RAM]:2 tmpa; + tmpc:2 = (tmpb << 8) | (tmpb >> 8); + rd0 = sext(tmpc); +} + +:LDSWP.UH rd0, rp9[LDSTSWPH] is op13_3=0x7 & op4_5=0x1d & rp9 & rd0 ; eop12_4=0x3 & LDSTSWPH { + tmp:4 = sext(LDSTSWPH); + tmpa:4 = rp9 + tmp; + tmpb:2 = *[RAM]:2 tmpa; + tmpc:2 = (tmpb << 8) | (tmpb >> 8); + rd0 = zext(tmpc); +} + +:LDSWP.W rd0, rp9[LDSTSWPW] is op13_3=0x7 & op4_5=0x1d & rp9 & rd0 ; eop12_4=0x8 & LDSTSWPW { + tmp:4 = sext(LDSTSWPW); + tmpa:4 = rp9 + tmp; + tmpb:4 = *[RAM]:4 tmpa; + rd0 = (tmpb << 24) | (tmpb >> 24) | ((tmpb & 0x0000FF00) << 8) | ((tmpb & 0x00FF0000) >> 8); +} + +:STSWP.H rp9[LDSTSWPH], rs0 is op13_3=0x7 & op4_5=0x1d & rp9 & rs0 ; eop12_4=0x9 & LDSTSWPH { + tmp:4 = sext(LDSTSWPH); + tmpa:4 = rp9 + tmp; + tmpb:2 = rs0:2; + *[RAM]:2 tmpa = (tmpb >> 8) | (tmpb << 8); +} + +:STSWP.W rp9[LDSTSWPW], rs0 is op13_3=0x7 & op4_5=0x1d & rp9 & rs0 ; eop12_4=0xa & LDSTSWPW { + tmp:4 = sext(LDSTSWPW); + tmpa:4 = rp9 + tmp; + *[RAM]:4 tmpa = (rs0 << 24) | (rs0 >> 24) | ((rs0 & 0x0000FF00) << 8) | ((rs0 & 0x00FF0000) >> 8); +} + +#--------------------------------------------------------------------- +# ST.B - Store Byte +#--------------------------------------------------------------------- + +# ST.B Format I +# 000p ppp0 1100 ssss + +:ST.B RP9bInc, rs0 is op13_3=0x0 & op4_5=0x0c & RP9bInc & rs0 { + *:1 RP9bInc = rs0:1; +} + +# ST.B Format II +# 000p ppp0 1111 ssss + +:ST.B RP9bDec, rs0 is op13_3=0x0 & op4_5=0x0f & RP9bDec & rs0 { + *:1 RP9bDec = rs0:1; +} + +# ST.B Format III +# 101p ppp0 1nnn ssss + +:ST.B RPbDisp3, rs0 is op13_3=0x5 & op7_2=0x1 & rs0 & RPbDisp3 { + *:1 RPbDisp3 = rs0:1; +} + +# ST.B Format IV +# 111p ppp1 0110 ssss nnnn nnnn nnnn nnnn + +:ST.B RPDisp16, rs0 is (op13_3=0x7 & op4_5=0x16 & rs0) ... & RPDisp16 { + *:1 RPDisp16 = rs0:1; +} + +# ST.B Format V +# 111b bbb0 0000 iiii 0000 1011 00tt ssss + +:ST.B RB9Shift, ers0 is (op13_3=0x7 & op4_5=0 & ri0; + eop12_4=0 & eop8_4=0xb & eop6_2=0 & ers0) & RB9Shift { + *:1 RB9Shift = ers0:1; +} + +#--------------------------------------------------------------------- +# ST.B{cond4} - Conditionally Store Byte +#--------------------------------------------------------------------- + +# ST.B{cond4} Format I +# 111p ppp1 1111 ssss cccc 111n nnnn nnnn + +:ST.B^{COND_e12} RPwDisp9, rs0 is (op13_3=0x7 & op4_5=0x1f & rs0; + eop9_3=0x7 & COND_e12) & RPwDisp9 { + build COND_e12; + *:4 RPwDisp9 = rs0:1; +} + +#--------------------------------------------------------------------- +# ST.D - Store Doubleword +#--------------------------------------------------------------------- + +# ST.D Format I +# 101p ppp1 0010 sss0 + +:ST.D RPdInc, rs0_low is op13_3=0x5 & op4_5=0x12 & b0=0 + & RPdInc & rs0 & rs0_hi & rs0_low { + low:8 = zext(rs0_low); + hi:8 = zext(rs0_hi) << 32; + *:8 RPdInc = hi | low; +} + +# ST.D Format II +# 101p ppp1 0010 sss1 + +:ST.D RPdDec, rs0_low is op13_3=0x5 & op4_5=0x12 & b0=1 + & RPdDec & rs0 & rs0_hi & rs0_low { + low:8 = zext(rs0_low); + hi:8 = zext(rs0_hi) << 32; + *:8 RPdDec = hi | low; +} + +# ST.D Format III +# 101p ppp1 0001 sss1 + +:ST.D rp9, rs0_low is op13_3=0x5 & op4_5=0x11 & b0=1 + & rp9 & rs0 & rs0_hi & rs0_low { + low:8 = zext(rs0_low); + hi:8 = zext(rs0_hi) << 32; + *:8 rp9 = hi | low; +} + +# ST.D Format IV +# 111p ppp0 1110 sss1 nnnn nnnn nnnn nnnn + +:ST.D RPDisp16, rs0_low is (op13_3=0x7 & op4_5=0xe + & b0=1 & rs0 & rs0_hi & rs0_low) ... & RPDisp16 +{ + low:8 = zext(rs0_low); + hi:8 = zext(rs0_hi) << 32; + *:8 RPDisp16 = hi | low; +} + +# ST.D Format V +# 111b bbb0 0000 iiii 0000 1000 00tt ssss + +:ST.D RB9Shift, ers0_low is (op13_3=0x7 & op4_5=0 & ri0; + eop12_4=0 & eop8_4=0x8 & eop6_2=0 + & ers0 & ers0_hi & ers0_low) & RB9Shift +{ + low:8 = zext(ers0_low); + hi:8 = zext(ers0_hi) << 32; + *:8 RB9Shift = hi | low; +} + +#--------------------------------------------------------------------- +# ST.H - Store Halfword +#--------------------------------------------------------------------- + +# ST.H Format I +# 000p ppp0 1011 ssss + +:ST.H RPhInc, rs0 is op13_3=0x0 & op4_5=0x0b & RPhInc & rs0 { + *:2 RPhInc = rs0:2; +} + +# ST.H Format II +# 000p ppp0 1110 ssss + +:ST.H RPhDec, rs0 is op13_3=0x0 & op4_5=0x0e & RPhDec & rs0 { + *:2 RPhDec = rs0:2; +} + +# ST.H Format III +# 101p ppp0 0nnn ssss + +:ST.H RPhDisp3, rs0 is op13_3=0x5 & op7_2=0x0 & rs0 & RPhDisp3 { + *:2 RPhDisp3 = rs0:2; +} + +# ST.H Format IV +# 111p ppp1 0101 ssss nnnn nnnn nnnn nnnn + +:ST.H RPDisp16, rs0 is (op13_3=0x7 & op4_5=0x15 & rs0) ... & RPDisp16 { + *:2 RPDisp16 = rs0:2; +} + +# ST.H Format V +# 111b bbb0 0000 iiii 0000 1010 00tt ssss + +:ST.H RB9Shift, ers0 is (op13_3=0x7 & op4_5=0 & ri0; + eop12_4=0 & eop8_4=0xa & eop6_2=0 & ers0) & RB9Shift { + *:2 RB9Shift = ers0:2; +} + +#--------------------------------------------------------------------- +# ST.H{cond4} - Conditionally Store Halfword +#--------------------------------------------------------------------- + +# ST.H{cond4} Format I +# 111p ppp1 1111 ssss cccc 110n nnnn nnnn + +:ST.H^{COND_e12} RPhDisp9, rs0 is (op13_3=0x7 & op4_5=0x1f & rs0; + eop9_3=0x6 & COND_e12) & RPhDisp9 { + build COND_e12; + *:4 RPhDisp9 = rs0:2; +} + +STXP: "T" is eb13=1 & ctx_savex { + tmp:4 = ctx_savex; + tmp = tmp >> 16; + export *[const]:4 tmp; +} +STXP: "B" is eb13=0 & ctx_savex { + tmp:4 = ctx_savex; + tmp = tmp & 0xFFFF; + export *[const]:4 tmp; +} +STYP: "T" is eb12=1 & ctx_savey { + tmp:4 = ctx_savey; + tmp = tmp >> 16; + export *[const]:4 tmp; +} +STYP: "B" is eb12=0 & ctx_savey { + tmp:4 = ctx_savey; + tmp = tmp & 0xFFFF; + export *[const]:4 tmp; +} +STHHD: val is edisp4_8 [ val = edisp4_8 << 2; ] { export *[const]:2 val; } +:STHH.W erp0[STHHD],rx9:STXP,ry0:STYP is op13_3=0x7 & op4_5=0x1e & rx9 & ry0 ; eop14_2=0x3 & STXP & STYP & STHHD & erp0 [ctx_savex=rx9; ctx_savey=ry0;] { + tmp:4 = zext(STHHD); + tmp = erp0 + tmp; + *[RAM]:4 tmp = (STXP << 16) | STYP; +} + +:STHH.W erb0[eri8" << "shift4_2],rx9:STXP,ry0:STYP is op13_3=0x7 & op4_5=0x1e & rx9 & ry0 ; eop14_2=0x2 & STXP & STYP & eri8 & eop6_2=0x0 & shift4_2 & erb0 [ctx_savex=rx9; ctx_savey=ry0;] { + tmp:4 = eri8 << shift4_2; + *[RAM]:4 tmp = (STXP << 16) | STYP; +} + +#--------------------------------------------------------------------- +# ST.W - Store Word +#--------------------------------------------------------------------- + +# ST.W Format I +# 000p ppp0 1010 ssss + +:ST.W RPwInc,rs0 is op13_3=0x0 & op4_5=0x0a & RPwInc & rs0 { + *:4 RPwInc = rs0; +} + +# ST.W Format II +# 000p ppp0 1101 ssss + +:ST.W RPwDec,rs0 is op13_3=0x0 & op4_5=0x0d & RPwDec & rs0 { + *:4 RPwDec = rs0; +} + +# ST.W Format III +# 100p ppp1 nnnn ssss + +:ST.W RPwDisp4,rs0 is op13_3=0x4 & op8_1=1 & RPwDisp4 & rs0 { + *:4 RPwDisp4 = rs0; +} + +# ST.W Format IV +# 111p ppp1 0100 ssss nnnn nnnn nnnn nnnn + +:ST.W RPDisp16,rs0 is (op13_3=7 & op4_5=0x14 & rs0) ... & RPDisp16 { + *:4 RPDisp16 = rs0; +} + +# ST.W Format V +# 111b bbb0 0000 iiii 0000 1001 00tt ssss + +:ST.W RB9Shift,ers0 is (op13_3=0x7 & op4_5=0 & ri0; + eop12_4=0 & eop8_4=0x9 & eop6_2=0 & ers0) + & RB9Shift { + *:4 RB9Shift = ers0; +} + +#--------------------------------------------------------------------- +# ST.W - Conditionally Store Word +#--------------------------------------------------------------------- + +# ST.W{cond4} Format I +# 111p ppp1 1111 ssss cccc 101n nnnn nnnn + +:ST.W^{COND_e12} RPwDisp9, rs0 is (op13_3=0x7 & op4_5=0x1f & rs0; + eop9_3=0x5 & COND_e12) & RPwDisp9 { + build COND_e12; + *:4 RPwDisp9 = rs0; +} + +:STCOND rp9[disp_16],rs0 is op13_3=0x7 & rp9 & op4_5=0x17 & rs0 ; disp_16 { + Z = L; + CZTOSR(); + + if (!L) goto inst_next; + + tmp:2 = disp_16; + tmpa:4 = sext(tmp); + tmpa = tmpa + rp9; + *[RAM]:4 tmpa = rs0; +} + +#--------------------------------------------------------------------- +# STDSP - Store Stack-Pointer Relative +# I. disp -> {0, 4, ..., 508} +# s -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# STDSP Format I +# Operation: *((SP & 0xfffffffc) + (ZE(disp7) << 2)) <- Rs +# Syntax: stdsp SP[disp], Rs +# 0101 0nnn nnnn ssss + +:STDSP "SP["^disp4_7^"], "^rs0 is op11_5=0xa & disp4_7 & rs0 +{ + ptr:4 = (SP & 0xfffffffc) + (disp4_7 << 2); + #ptr:4 = (((SP >> 2) + disp4_7) << 2); + # assuming SP was pointing into RAM... + *:4 ptr = rs0; +} + +#--------------------------------------------------------------------- +# 8.3.9.3 Multiple Data +#--------------------------------------------------------------------- + +#--------------------------------------------------------------------- +# LDM - Load Multiple Registers +#--------------------------------------------------------------------- + +# LDM Format I +# 1110 00M1 1100 pppp LLLL LLLL LLLL LLLL + +macro status_r12() { + V = 0; + N = R12 s< 0; + Z = R12 == 0; + C = 0; + CZNVTOSR(); +} + +LoadAddress: is rp0=0xf ; eb15=1 { ldadd = SP; } # Rp=PC and Reglist16[PC]=1 +LoadAddress: is rp0=0xf ; eb15 { ldadd = inst_start; } # Rp=PC and Reglist16[PC]=0 +LoadAddress: is rp0 ; eb15 { ldadd = rp0; } # Rp!=PC +LoadAddressTS: is rp0 ; eb15 { ldadd = rp0; } + +LDMinc15: ", PC" is eb15=1 { PC = *:4 ldadd; ldadd = ldadd + 4; } +LDMinc14ab: ", LR" is eb14=1 { LR = *:4 ldadd; ldadd = ldadd + 4; } +LDMinc13ab: ", SP" is eb13=1 { SP = *:4 ldadd; ldadd = ldadd + 4; } +LDMinc12c: ", R12=0" is eb14=0 & eb12=0 { R12 = 0; } +LDMinc12c: ", R12=1" is eb14=0 & eb12=1 { R12 = 1; } +LDMinc12c: ", R12=-1" is eb14=1 { R12 = -1; } +LDMinc12ab: ", R12" is eb12=1 { R12 = *:4 ldadd; ldadd = ldadd + 4; } +LDMinc12s: is eb15=1 { status_r12(); } +LDMinc11: ", R11" is eb11=1 { R11 = *:4 ldadd; ldadd = ldadd + 4; } +LDMinc10: ", R10" is eb10=1 { R10 = *:4 ldadd; ldadd = ldadd + 4; } +LDMinc9: ", R9" is eb9=1 { R9 = *:4 ldadd; ldadd = ldadd + 4; } +LDMinc8: ", R8" is eb8=1 { R8 = *:4 ldadd; ldadd = ldadd + 4; } +LDMinc7: ", R7" is eb7=1 { R7 = *:4 ldadd; ldadd = ldadd + 4; } +LDMinc6: ", R6" is eb6=1 { R6 = *:4 ldadd; ldadd = ldadd + 4; } +LDMinc5: ", R5" is eb5=1 { R5 = *:4 ldadd; ldadd = ldadd + 4; } +LDMinc4: ", R4" is eb4=1 { R4 = *:4 ldadd; ldadd = ldadd + 4; } +LDMinc3: ", R3" is eb3=1 { R3 = *:4 ldadd; ldadd = ldadd + 4; } +LDMinc2: ", R2" is eb2=1 { R2 = *:4 ldadd; ldadd = ldadd + 4; } +LDMinc1: ", R1" is eb1=1 { R1 = *:4 ldadd; ldadd = ldadd + 4; } +LDMinc0: ", R0" is eb0=1 { R0 = *:4 ldadd; ldadd = ldadd + 4; } + +LDMinc15: is eb15=0 { } +LDMinc14ab: is eb14=0 { } +LDMinc13ab: is eb13=0 { } +LDMinc12ab: is eb12=0 { } +LDMinc12s: is eb15=0 { } +LDMinc11: is eb11=0 { } +LDMinc10: is eb10=0 { } +LDMinc9: is eb9=0 { } +LDMinc8: is eb8=0 { } +LDMinc7: is eb7=0 { } +LDMinc6: is eb6=0 { } +LDMinc5: is eb5=0 { } +LDMinc4: is eb4=0 { } +LDMinc3: is eb3=0 { } +LDMinc2: is eb2=0 { } +LDMinc1: is eb1=0 { } +LDMinc0: is eb0=0 { } + +LDMpp: is op9_1=0 { } +LDMpp: "++" is op9_1=1 & rp0=0xf { SP = ldadd; } +LDMpp: "++" is op9_1=1 & rp0 { rp0 = ldadd; } + +LDMTSpp: is op9_1=0 { } +LDMTSpp: "++" is op9_1=1 & rp0 { rp0 = ldadd; } + +LDMret: is eb15=1 { return [ PC ]; } +LDMret: is eb15=0 { } + +LDMcommon: LDMinc0^LDMinc1^LDMinc2^LDMinc3^LDMinc4^LDMinc5^LDMinc6^LDMinc7^LDMinc8^LDMinc9^LDMinc10^LDMinc11 is LDMinc0 & LDMinc1 & LDMinc2 & LDMinc3 & LDMinc4 & LDMinc5 + & LDMinc6 & LDMinc7 & LDMinc8 & LDMinc9 & LDMinc10 & LDMinc11 +{ + build LDMinc11; + build LDMinc10; + build LDMinc9; + build LDMinc8; + build LDMinc7; + build LDMinc6; + build LDMinc5; + build LDMinc4; + build LDMinc3; + build LDMinc2; + build LDMinc1; + build LDMinc0; +} + +LDMlistd: LDMpp^LDMcommon^LDMinc12ab^LDMinc13ab^LDMinc14ab^LDMinc15 is (LDMpp ; LDMcommon & LDMinc12ab & LDMinc13ab & LDMinc14ab + & LDMinc12s & LDMinc15 & LDMret) & LoadAddressTS +{ + build LoadAddressTS; + build LDMinc15; + build LDMinc14ab; + build LDMinc13ab; + build LDMinc12ab; + build LDMcommon; + build LDMpp; + build LDMret; +} + +LDMlistc: LDMpp^LDMcommon^LDMinc12c^LDMinc15 is (LDMpp ; LDMcommon & LDMinc12c & LDMinc12s & LDMinc15 & LDMret) & LoadAddress +{ + build LoadAddress; + build LDMinc15; + build LDMinc12c; + build LDMinc12s; + build LDMcommon; + build LDMpp; + build LDMret; +} + +LDMlistb: LDMpp^LDMcommon^LDMinc12ab^LDMinc13ab^LDMinc14ab^LDMinc15 is (LDMpp ; LDMcommon & LDMinc12ab & LDMinc13ab & LDMinc14ab + & LDMinc12s & LDMinc15 & LDMret) & LoadAddress +{ + build LoadAddress; + build LDMinc15; + build LDMinc14ab; + build LDMinc13ab; + build LDMinc12ab; + build LDMinc12s; + build LDMcommon; + build LDMpp; + build LDMret; +} + +LDMlista: LDMpp^LDMcommon^LDMinc12ab^LDMinc13ab^LDMinc14ab is (LDMpp ; LDMcommon & LDMinc12ab & LDMinc13ab & LDMinc14ab) & LoadAddress +{ + build LoadAddress; + build LDMinc14ab; + build LDMinc13ab; + build LDMinc12ab; + build LDMcommon; + build LDMpp; +} + +:LDM rp0^LDMlistc is (rp0 & rp0=0xf & op10_6=0x38 & op4_5=0x1c ; eb15=1) & LDMlistc +{ + build LDMlistc; +} + +:LDM rp0^LDMlistb is (rp0 & op10_6=0x38 & op4_5=0x1c ; eb15=1) & LDMlistb +{ + build LDMlistb; +} + +:LDM rp0^LDMlista is (rp0 & op10_6=0x38 & op4_5=0x1c) ... & LDMlista +{ + build LDMlista; +} + +:LDMTS rp0^LDMlistd is (rp0 & op10_6=0x39 & op4_5=0x1c) ... & LDMlistd { + build LDMlistd; +} + +#--------------------------------------------------------------------- +# POPM - Load Multiple Registers +#--------------------------------------------------------------------- + +# POPM Format I +# 1101 RRRR RRRR k010 +COM5: is bp4_1=0 {} +COM5: "," is bp4_1 {} +COM6: is bp4_2=0 {} +COM6: "," is bp4_2 {} +COM7: is bp4_3=0 {} +COM7: "," is bp4_3 {} +COM8: is bp4_4=0 {} +COM8: "," is bp4_4 {} +COM9: is bp4_5=0 {} +COM9: "," is bp4_5 {} +COM10: is bp4_6=0 {} +COM10: "," is bp4_6 {} +COM11: is bp4_7=0 {} +COM11: is bp4_7=0x20 & b03=1 {} +COM11: "," is bp4_7 {} + +POPMinc11: COM11^"PC" is b11=1 & COM11 { build COM11; PC = *:4 SP; SP = SP + 4; } +POPMinc10b: is b10 { } +POPMinc10a: COM10^"LR" is b10=1 & COM10 { build COM10; LR = *:4 SP; SP = SP + 4; } +POPMinc9b: ",R12=0" is b11=1 & b10=0 & b09=0 { R12 = 0; } +POPMinc9b: ",R12=1" is b11=1 & b10=0 & b09=1 { R12 = 1; } +POPMinc9b: ",R12=-1" is b11=1 & b10=1 { R12 = -1; } +POPMinc9a: COM9^"R12" is b09=1 & COM9 { build COM9; R12 = *:4 SP; SP = SP + 4; } +POPMinc9s: is b11=1 { status_r12(); } +POPMinc8: COM8^"R11" is b08=1 & COM8 { build COM8; + R11 = *:4 SP; SP = SP + 4; } +POPMinc7: COM7^"R10" is b07=1 & COM7 { build COM7; + R10 = *:4 SP; SP = SP + 4; } +POPMinc6: COM6^"R8-R9" is b06=1 & COM6 { build COM6; + R9 = *:4 SP; SP = SP + 4; + R8 = *:4 SP; SP = SP + 4; } +POPMinc5: COM5^"R4-R7" is b05=1 & COM5 { build COM5; + R7 = *:4 SP; SP = SP + 4; + R6 = *:4 SP; SP = SP + 4; + R5 = *:4 SP; SP = SP + 4; + R4 = *:4 SP; SP = SP + 4; } +POPMinc4: "R0-R3" is b04=1 { R3 = *:4 SP; SP = SP + 4; + R2 = *:4 SP; SP = SP + 4; + R1 = *:4 SP; SP = SP + 4; + R0 = *:4 SP; SP = SP + 4; } +POPMinc11: is b11=0 { } +POPMinc10a: is b10=0 { } +POPMinc9a: is b09=0 { } +POPMinc9b: is b11=0 { } +POPMinc9s: is b11=0 { } +POPMinc8: is b08=0 { } +POPMinc7: is b07=0 { } +POPMinc6: is b06=0 { } +POPMinc5: is b05=0 { } +POPMinc4: is b04=0 { } + +POPMjump: is b11=1 { return [ PC ]; } +POPMjump: is b11=0 { } + +POPMchunk: POPMinc4^POPMinc5^POPMinc6^POPMinc7^POPMinc8 is POPMinc4 & POPMinc5 & POPMinc6 & POPMinc7 & POPMinc8 & POPMinc9s & POPMjump +{ + build POPMinc9s; + build POPMinc8; + build POPMinc7; + build POPMinc6; + build POPMinc5; + build POPMinc4; + build POPMjump; +} + +POPMdispa: POPMchunk^POPMinc9a^POPMinc10a^POPMinc11 is POPMchunk & POPMinc9a & POPMinc10a & POPMinc11 +{ + build POPMinc11; + build POPMinc10a; + build POPMinc9a; + build POPMchunk; +} + +POPMdispb: POPMchunk^POPMinc10b^POPMinc11^POPMinc9b is POPMchunk & POPMinc9b & POPMinc10b & POPMinc11 +{ + build POPMinc11; + build POPMinc10b; + build POPMinc9b; + build POPMchunk; +} + +:POPM POPMdispa is op12_4=0xd & op0_4=0x2 & POPMdispa +{ + build POPMdispa; +} + +:POPM POPMdispb is op12_4=0xd & op0_4=0xa & POPMdispb +{ + build POPMdispb; +} + +#--------------------------------------------------------------------- +# PUSHM - Push Multiple Registers to Stack +# I. Reglist8 -> {R0-R3, R4-R7, R8-R9, R10, R11, R12, LR, PC} +#--------------------------------------------------------------------- + +# PUSHM Format I: +# Operation: if Reglist8[0] == 1 then +# *(--SP) <- R0; +# *(--SP) <- R1; +# *(--SP) <- R2; +# *(--SP) <- R3; +# if Reglist8[1] == 1 then +# *(--SP) <- R4; +# *(--SP) <- R5; +# *(--SP) <- R6; +# *(--SP) <- R7; +# if Reglist8[2] == 1 then +# *(--SP) <- R8; +# *(--SP) <- R9; +# if Reglist8[3] == 1 then +# *(--SP) <- R10; +# if Reglist8[4] == 1 then +# *(--SP) <- R11; +# if Reglist8[5] == 1 then +# *(--SP) <- R12; +# if Reglist8[6] == 1 then +# *(--SP) <- LR; +# if Reglist8[7] == 1 then +# *(--SP) <- PC; +# Syntax: pushm Reglist8 +# 1101 RRRR RRRR 0001 + +PUSHMdec4: "R0-R3" is b04=1 { SP = SP - 4; *:4 SP = R0; + SP = SP - 4; *:4 SP = R1; + SP = SP - 4; *:4 SP = R2; + SP = SP - 4; *:4 SP = R3; } +PUSHMdec5: COM5^"R4-R7" is b05=1 & COM5 { build COM5; + SP = SP - 4; *:4 SP = R4; + SP = SP - 4; *:4 SP = R5; + SP = SP - 4; *:4 SP = R6; + SP = SP - 4; *:4 SP = R7; } +PUSHMdec6: COM6^"R8-R9" is b06=1 & COM6{ build COM6; + SP = SP - 4; *:4 SP = R8; + SP = SP - 4; *:4 SP = R9; } +PUSHMdec7: COM7^"R10" is b07=1 & COM7 { build COM7; SP = SP - 4; *:4 SP = R10; } +PUSHMdec8: COM8^"R11" is b08=1 & COM8 { build COM8; SP = SP - 4; *:4 SP = R11; } +PUSHMdec9: COM9^"R12" is b09=1 & COM9 { build COM9; SP = SP - 4; *:4 SP = R12; } +PUSHMdec10: COM10^"LR" is b10=1 & COM10 { build COM10; SP = SP - 4; *:4 SP = LR; } +PUSHMdec11: COM11^"PC" is b11=1 & COM11 { build COM11; SP = SP - 4; *:4 SP = inst_start; } +PUSHMdec4: is b04=0 { } +PUSHMdec5: is b05=0 { } +PUSHMdec6: is b06=0 { } +PUSHMdec7: is b07=0 { } +PUSHMdec8: is b08=0 { } +PUSHMdec9: is b09=0 { } +PUSHMdec10: is b10=0 { } +PUSHMdec11: is b11=0 { } + +PUSHMdisp: PUSHMdec4^PUSHMdec5^PUSHMdec6^PUSHMdec7^PUSHMdec8^PUSHMdec9^PUSHMdec10^PUSHMdec11 is PUSHMdec4 & PUSHMdec5 & PUSHMdec6 & PUSHMdec7 + & PUSHMdec8 & PUSHMdec9 & PUSHMdec10 & PUSHMdec11 +{ + build PUSHMdec4; + build PUSHMdec5; + build PUSHMdec6; + build PUSHMdec7; + build PUSHMdec8; + build PUSHMdec9; + build PUSHMdec10; + build PUSHMdec11; +} + +:PUSHM PUSHMdisp is + op12_4=0xd & op0_4=0x1 & PUSHMdisp +{ + build PUSHMdisp; +} + +#--------------------------------------------------------------------- +# STM - Store Multiple Registers +#--------------------------------------------------------------------- + +# STM Format I +# 1110 10M1 1100 pppp LLLL LLLL LLLL LLLL + +StoreAddress: is rp0 ; eb15 { stadd = rp0; } # Rp!=PC + +STMinc0: ,deb0 is rp0 ; deb0 & eb0=1 { *:4 stadd = R0; stadd = stadd + 4; } +STMinc1: ,deb1 is rp0 ; deb1 & eb1=1 { *:4 stadd = R1; stadd = stadd + 4; } +STMinc2: ,deb2 is rp0 ; deb2 & eb2=1 { *:4 stadd = R2; stadd = stadd + 4; } +STMinc3: ,deb3 is rp0 ; deb3 & eb3=1 { *:4 stadd = R3; stadd = stadd + 4; } +STMinc4: ,deb4 is rp0 ; deb4 & eb4=1 { *:4 stadd = R4; stadd = stadd + 4; } +STMinc5: ,deb5 is rp0 ; deb5 & eb5=1 { *:4 stadd = R5; stadd = stadd + 4; } +STMinc6: ,deb6 is rp0 ; deb6 & eb6=1 { *:4 stadd = R6; stadd = stadd + 4; } +STMinc7: ,deb7 is rp0 ; deb7 & eb7=1 { *:4 stadd = R7; stadd = stadd + 4; } +STMinc8: ,deb8 is rp0 ; deb8 & eb8=1 { *:4 stadd = R8; stadd = stadd + 4; } +STMinc9: ,deb9 is rp0 ; deb9 & eb9=1 { *:4 stadd = R9; stadd = stadd + 4; } +STMinc10: ,deb10 is rp0 ; deb10 & eb10=1 { *:4 stadd = R10; stadd = stadd + 4; } +STMinc11: ,deb11 is rp0 ; deb11 & eb11=1 { *:4 stadd = R11; stadd = stadd + 4; } +STMinc12: ,deb12 is rp0 ; deb12 & eb12=1 { *:4 stadd = R12; stadd = stadd + 4; } +STMinc13: ,deb13 is rp0 ; deb13 & eb13=1 { *:4 stadd = SP; stadd = stadd + 4; } +STMinc14: ,deb14 is rp0 ; deb14 & eb14=1 { *:4 stadd = LR; stadd = stadd + 4; } +STMinc15: ,deb15 is rp0 ; deb15 & eb15=1 { *:4 stadd = inst_start; stadd = stadd + 4; } +STMinc0: is rp0 ; eb0=0 { } +STMinc1: is rp0 ; eb1=0 { } +STMinc2: is rp0 ; eb2=0 { } +STMinc3: is rp0 ; eb3=0 { } +STMinc4: is rp0 ; eb4=0 { } +STMinc5: is rp0 ; eb5=0 { } +STMinc6: is rp0 ; eb6=0 { } +STMinc7: is rp0 ; eb7=0 { } +STMinc8: is rp0 ; eb8=0 { } +STMinc9: is rp0 ; eb9=0 { } +STMinc10: is rp0 ; eb10=0 { } +STMinc11: is rp0 ; eb11=0 { } +STMinc12: is rp0 ; eb12=0 { } +STMinc13: is rp0 ; eb13=0 { } +STMinc14: is rp0 ; eb14=0 { } +STMinc15: is rp0 ; eb15=0 { } + +STMdec0: ,deb0 is rp0 ; deb0 & eb0=1 { rp0 = rp0 - 4; *:4 rp0 = R0; } +STMdec1: ,deb1 is rp0 ; deb1 & eb1=1 { rp0 = rp0 - 4; *:4 rp0 = R1; } +STMdec2: ,deb2 is rp0 ; deb2 & eb2=1 { rp0 = rp0 - 4; *:4 rp0 = R2; } +STMdec3: ,deb3 is rp0 ; deb3 & eb3=1 { rp0 = rp0 - 4; *:4 rp0 = R3; } +STMdec4: ,deb4 is rp0 ; deb4 & eb4=1 { rp0 = rp0 - 4; *:4 rp0 = R4; } +STMdec5: ,deb5 is rp0 ; deb5 & eb5=1 { rp0 = rp0 - 4; *:4 rp0 = R5; } +STMdec6: ,deb6 is rp0 ; deb6 & eb6=1 { rp0 = rp0 - 4; *:4 rp0 = R6; } +STMdec7: ,deb7 is rp0 ; deb7 & eb7=1 { rp0 = rp0 - 4; *:4 rp0 = R7; } +STMdec8: ,deb8 is rp0 ; deb8 & eb8=1 { rp0 = rp0 - 4; *:4 rp0 = R8; } +STMdec9: ,deb9 is rp0 ; deb9 & eb9=1 { rp0 = rp0 - 4; *:4 rp0 = R9; } +STMdec10: ,deb10 is rp0 ; deb10 & eb10=1 { rp0 = rp0 - 4; *:4 rp0 = R10; } +STMdec11: ,deb11 is rp0 ; deb11 & eb11=1 { rp0 = rp0 - 4; *:4 rp0 = R11; } +STMdec12: ,deb12 is rp0 ; deb12 & eb12=1 { rp0 = rp0 - 4; *:4 rp0 = R12; } +STMdec13: ,deb13 is rp0 ; deb13 & eb13=1 { rp0 = rp0 - 4; *:4 rp0 = SP; } +STMdec14: ,deb14 is rp0 ; deb14 & eb14=1 { rp0 = rp0 - 4; *:4 rp0 = LR; } +STMdec15: ,deb15 is rp0 ; deb15 & eb15=1 { rp0 = rp0 - 4; *:4 rp0 = inst_start; } +STMdec0: is rp0 ; eb0=0 { } +STMdec1: is rp0 ; eb1=0 { } +STMdec2: is rp0 ; eb2=0 { } +STMdec3: is rp0 ; eb3=0 { } +STMdec4: is rp0 ; eb4=0 { } +STMdec5: is rp0 ; eb5=0 { } +STMdec6: is rp0 ; eb6=0 { } +STMdec7: is rp0 ; eb7=0 { } +STMdec8: is rp0 ; eb8=0 { } +STMdec9: is rp0 ; eb9=0 { } +STMdec10: is rp0 ; eb10=0 { } +STMdec11: is rp0 ; eb11=0 { } +STMdec12: is rp0 ; eb12=0 { } +STMdec13: is rp0 ; eb13=0 { } +STMdec14: is rp0 ; eb14=0 { } +STMdec15: is rp0 ; eb15=0 { } + +STMdecdisp: STMdec0^STMdec1^STMdec2^STMdec3^STMdec4^STMdec5^STMdec6^STMdec7^STMdec8^STMdec9^STMdec10^STMdec11^STMdec12^STMdec13^STMdec14^STMdec15 is STMdec0 & STMdec1 & STMdec2 & STMdec3 & + STMdec4 & STMdec5 & STMdec6 & STMdec7 & + STMdec8 & STMdec9 & STMdec10 & STMdec11 & + STMdec12 & STMdec13 & STMdec14 & STMdec15 +{ + build STMdec0; + build STMdec1; + build STMdec2; + build STMdec3; + build STMdec4; + build STMdec5; + build STMdec6; + build STMdec7; + build STMdec8; + build STMdec9; + build STMdec10; + build STMdec11; + build STMdec12; + build STMdec13; + build STMdec14; + build STMdec15; +} + +STMincdisp: STMinc0^STMinc1^STMinc2^STMinc3^STMinc4^STMinc5^STMinc6^STMinc7^STMinc8^STMinc9^STMinc10^STMinc11^STMinc12^STMinc13^STMinc14^STMinc15 is STMinc0 & STMinc1 & STMinc2 & STMinc3 & + STMinc4 & STMinc5 & STMinc6 & STMinc7 & + STMinc8 & STMinc9 & STMinc10 & STMinc11 & + STMinc12 & STMinc13 & STMinc14 & STMinc15 & StoreAddress +{ + build StoreAddress; + build STMinc15; + build STMinc14; + build STMinc13; + build STMinc12; + build STMinc11; + build STMinc10; + build STMinc9; + build STMinc8; + build STMinc7; + build STMinc6; + build STMinc5; + build STMinc4; + build STMinc3; + build STMinc2; + build STMinc1; + build STMinc0; +} + +:STM "--"^rp0^STMdecdisp +is + (op10_6=0x3a & op4_5=0x1c & op9_1=1 & rp0) ... & STMdecdisp +{ +} + +:STM rp0^STMincdisp +is + (op10_6=0x3a & op4_5=0x1c & op9_1=0 & rp0) ... & STMincdisp +{ +} + +:STMTS "--"^rp0^STMdecdisp +is + (op10_6=0x3b & op4_5=0x1c & op9_1=1 & rp0) ... & STMdecdisp +{ +} + +:STMTS rp0^STMincdisp +is + (op10_6=0x3b & op4_5=0x1c & op9_1=0 & rp0) ... & STMincdisp +{ +} + +:XCHG rx9, ry0, erd0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0xb4 & erd0 { + erd0 = *[RAM]:4 rx9; + *[RAM]:4 rx9 = ry0; +} diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_dsp_operations.sinc b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_dsp_operations.sinc new file mode 100644 index 0000000..888a62b --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_dsp_operations.sinc @@ -0,0 +1,884 @@ +#--------------------------------------------------------------------- +# 8.3.4 DSP Operations +#--------------------------------------------------------------------- +operand1: ":b" is rx9 ; selectorxy4_2=0x0 {b:4 = sext(rx9[0,16]); export b;} +operand1: ":b" is rx9 ; selectorxy4_2=0x1 {b:4 = sext(rx9[0,16]); export b;} +operand1: ":t" is rx9 ; selectorxy4_2=0x2 {t:4 = sext(rx9[16,16]); export t;} +operand1: ":t" is rx9 ; selectorxy4_2=0x3 {t:4 = sext(rx9[16,16]); export t;} + +operand2: ":b" is ry0 ; selectorxy4_2=0x0 {b:4 = sext(ry0[0,16]); export b;} +operand2: ":t" is ry0 ; selectorxy4_2=0x1 {t:4 = sext(ry0[16,16]); export t;} +operand2: ":b" is ry0 ; selectorxy4_2=0x2 {b:4 = sext(ry0[0,16]); export b;} +operand2: ":t" is ry0 ; selectorxy4_2=0x3 {t:4 = sext(ry0[16,16]); export t;} + +rdPlus1: is erd0=0x0 {export R1;} +rdPlus1: is erd0=0x2 {export R3;} +rdPlus1: is erd0=0x4 {export R5;} +rdPlus1: is erd0=0x6 {export R7;} +rdPlus1: is erd0=0x8 {export R9;} +rdPlus1: is erd0=0xa {export R11;} +rdPlus1: is erd0=0xc {export SP;} +rdPlus1: is erd0=0xe {export *[const]:4 inst_start;}#PC register + +#--------------------------------------------------------------------- +# ADDHH.W - Add Halfwords into Word +# I. {d, x, y} -> {0, 1, ..., 15} +# part -> {t,b} +#--------------------------------------------------------------------- +# ADDHH.W Format I +# Operation: If(Rx-part==t) then operand1=SE(Rx[31:16]) else operand1=SE(Rx[15:0]); +# If(Ry-part==t) then operand2=SE(Ry[31:16]) else operand2=SE(Ry[15:0]); +# Rd <- operand1 + operand2; +# Syntax: addhh.w Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 1110 00XY dddd +# Assumption: t = 1, b = 0 using XY +:ADDHH.W erd0, rx9^operand1, ry0^operand2 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop8_4=0xe & eop6_2=0x0 & selectorxy4_2 & erd0)) & operand1 & operand2 { + erd0 = operand1 + operand2; + addflags(operand1, operand2, erd0); + } + +#--------------------------------------------------------------------- +# MACHH.D - Multiply Halfwords and Accumulate in Doubleword +# I. d -> {0, 2, 4, ..., 14} +# {x, y} -> {0, 1, ..., 15} +# part -> {t,b} +#--------------------------------------------------------------------- +# MACHH.D Format I +# Operation: If(Rx-part==t) then operand1=SE(Rx[31:16]) else operand1=SE(Rx[15:0]); +# If(Ry-part==t) then operand2=SE(Ry[31:16]) else operand2=SE(Ry[15:0]); +# (Rd+1:Rd)[63:16] <- (operand1*operand2)[31:0] + (Rd+1:Rd)[63:16]; +# Rd[15:0] <- 0; +# Syntax: machh.d Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 0101 10XY dddd +# Assumption: t = 1, b = 0 using XY +:MACHH.D erd0, rx9^operand1, ry0^operand2 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop8_4=0x5 & eop6_2=0x2 & selectorxy4_2 & erd0 & rdPlus1)) & operand1 & operand2 { + multAccumulate:8 = (zext(operand1 * operand2) + ((zext(rdPlus1) << 32) | (zext(erd0[16,16]) << 16))); + rdPlus1 = multAccumulate[32,32]; + erd0 = ((zext(multAccumulate[16,16]) << 16) & 0xffff0000); +} + +#--------------------------------------------------------------------- +# MACHH.W - Multiply Halfwords and Accumulate in Word +# I. {d, x, y} -> {0, 1, ..., 15} +# part -> {t,b} +#--------------------------------------------------------------------- +# MACHH.W Format I +# Operation: If(Rx-part==t) then operand1=SE(Rx[31:16]) else operand1=SE(Rx[15:0]); +# If(Ry-part==t) then operand2=SE(Ry[31:16]) else operand2=SE(Ry[15:0]); +# Rd <- (operand1*operand2) + Rd; +# Syntax: machh.w Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 0100 10XY dddd +# Assumption: t = 1, b = 0 using XY +:MACHH.W erd0, rx9^operand1, ry0^operand2 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop8_4=0x4 & eop6_2=0x2 & selectorxy4_2 & erd0)) & operand1 & operand2 { + multAccumulate:4 = ((operand1 * operand2) + erd0); + erd0 = multAccumulate; +} + +#--------------------------------------------------------------------- +# MACWH.D - Multiply Word with Halfword and Accumulate in Doubleword +# I. d -> {0, 2, 4, ..., 14} +# {x, y} -> {0, 1, ..., 15} +# part -> {t,b} +#--------------------------------------------------------------------- +# MACWH.D Format I +# Operation: Operand1 = Rx; +# If(Ry-part==t) then operand2=SE(Ry[31:16]) else operand2=SE(Ry[15:0]); +# (Rd+1:Rd)[63:16] <- (operand1*operand2)[47:0] + (Rd+1:Rd)[63:16]; +# Rd[15:0] <- 0; +# Syntax: macwh.d Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 1100 100Y dddd +# Assumption: t = 1, b = 0 using Y +:MACWH.D erd0, rx9, ry0^operand2 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop8_4=0xc & eop5_3=0x4 & selectorxy4_2 & erd0 & rdPlus1)) & operand2 { + mult:6 = sext(rx9 * operand2); + multAccumulate:8 = (zext(mult) + ((zext(rdPlus1) << 32) | (zext(erd0[16,16]) << 16))); + rdPlus1 = multAccumulate[32,32]; + erd0 = ((zext(multAccumulate[16,16]) << 16) & 0xffff0000); +} + +#--------------------------------------------------------------------- +# MULHH.W - Multiply Halfwords with Halfword +# I. {d, x, y} -> {0, 1, ..., 15} +# part -> {t,b} +#--------------------------------------------------------------------- +# MULHH.W Format I +# Operation: If(Rx-part==t) then operand1=SE(Rx[31:16]) else operand1=SE(Rx[15:0]); +# If(Ry-part==t) then operand2=SE(Ry[31:16]) else operand2=SE(Ry[15:0]); +# Rd <- operand1 * operand2; +# Syntax: mulhh.w Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 0111 10XY dddd +# Assumption: t = 1, b = 0 using XY +:MULHH.W erd0, rx9^operand1, ry0^operand2 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop8_4=0x7 & eop6_2=0x2 & selectorxy4_2 & erd0)) & operand1 & operand2 { + erd0 = operand1 * operand2; + } + +#--------------------------------------------------------------------- +# MULWH.D - Multiply Word with Halfword +# I. d -> {0, 2, 4, ..., 14} +# {x, y} -> {0, 1, ..., 15} +# part -> {t,b} +#--------------------------------------------------------------------- +# MULWH.D Format I +# Operation: Operand1 = Rx; +# If(Ry-part==t) then operand2=SE(Ry[31:16]) else operand2=SE(Ry[15:0]); +# (Rd+1:Rd)[63:16] <- (operand1*operand2); +# Rd[15:0] <- 0; +# Syntax: mulwh.d Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 1101 100Y dddd +# Assumption: t = 1, b = 0 using Y +:MULWH.D erd0, rx9, ry0^operand2 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop8_4=0xd & eop5_3=0x4 & selectorxy4_2 & erd0 & rdPlus1)) & operand2 { + multiply:8 = (sext(rx9 * operand2)); + rdPlus1 = multiply[32,32]; + erd0 = ((zext(multiply[16,16]) << 16) & 0xffff0000); +} + +#--------------------------------------------------------------------- +# MULNHH.W - Multiply Halfwords with Negated Halfword +# I. {d, x, y} -> {0, 1, ..., 15} +# part -> {t,b} +#--------------------------------------------------------------------- +# MULNHH.W Format I +# Operation: If(Rx-part==t) then operand1=SE(Rx[31:16]) else operand1=SE(Rx[15:0]); +# If(Ry-part==t) then operand2=SE(Ry[31:16]) else operand2=SE(Ry[15:0]); +# Rd <- -(operand1 * operand2); +# Syntax: mulnhh.w Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 0001 10XY dddd +# Assumption: t = 1, b = 0 using XY +:MULNHH.W erd0, rx9^operand1, ry0^operand2 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop8_4=0x1 & eop6_2=0x2 & selectorxy4_2 & erd0)) & operand1 & operand2 { + neg1:4 = 0xffffffff; + erd0 = (neg1 * (operand1 * operand2)); + } + +#--------------------------------------------------------------------- +# MULNWH.D - Multiply Word with Negated Halfword +# I. d -> {0, 2, 4, ..., 14} +# {x, y} -> {0, 1, ..., 15} +# part -> {t,b} +#--------------------------------------------------------------------- +# MULNWH.D Format I +# Operation: Operand1 = Rx; +# If(Ry-part==t) then operand2=SE(Ry[31:16]) else operand2=SE(Ry[15:0]); +# (Rd+1:Rd)[63:16] <- -(operand1*operand2); +# Rd[15:0] <- 0; +# Syntax: mulnwh.d Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 0010 100Y dddd +# Assumption: t = 1, b = 0 using Y +:MULNWH.D erd0, rx9, ry0^operand2 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop8_4=0x2 & eop5_3=0x4 & selectorxy4_2 & erd0 & rdPlus1)) & operand2 { + neg1:8 = 0xffffffffffffffff; + multiply:8 = (neg1 * (sext(rx9 * operand2))); + rdPlus1 = multiply[32,32]; + erd0 = ((zext(multiply[16,16]) << 16) & 0xffff0000); +} + + +#--------------------------------------------------------------------- +# SATADD.W - Saturated Add of Words +# I. {d, x, y} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- +macro addSatWflags(RX, RY, TEMP, RD){ + #Q = (RX[31,1] && RY[31,1] && !TEMP[31,1]) || + # (!RX[31,1] && !RY[31,1] && TEMP[31,1]) || Q + Q = sborrow(RX, RY); + + #V = (RX[31,1] && RY[31,1] && !TEMP[31,1]) || + # (!RX[31,1] && !RY[31,1] && TEMP[31,1]) + V = sborrow(RX, RY); + + NZSTATUS(RD); + + C = 0x0; +} + +# SATADD.W Format I +# Operation: temp <- Rx + Ry; +# If(Rx[31] && Ry[31] && ~temp[31]) || (~Rx[31] && ~Ry[31] && temp[31]) then +# If Rx[31] == 0 then +# Rd <- 0x7fffffff; +# else +# Rd <- 0x80000000; +# else +# Rd <- temp; +# Syntax: satadd.w Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 0000 1100 dddd +:SATADD.W erd0, rx9, ry0 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop4_8=0xc & erd0)) { + temp:4 = rx9 + ry0; + local if_state_1 = ((rx9[31,1] && ry0[31,1] && ~temp[31,1]) || (~rx9[31,1] && ~ry0[31,1] && temp[31,1])); + local if_state_2 = (rx9[31,1] == 0x0); + local else_state_1 = !if_state_1; + local else_state_2 = !if_state_2; + erd0 = ((zext(if_state_1 * if_state_2) * (0x7fffffff)) + (zext(if_state_1 * else_state_2) * (0x80000000)) + (zext(else_state_1) * temp)); + addSatWflags(rx9, ry0, temp, erd0); +} + + +#--------------------------------------------------------------------- +# SATADD.H - Saturated Add of HalfWords +# I. {d, x, y} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- +macro addSatHflags(RX, RY, TEMP, RD){ + #Q = (RX[15,1] && RY[15,1] && !TEMP[15,1]) || + # (!RX[15,1] && !RY[15,1] && TEMP[15,1]) || Q + Q = sborrow(RX[0,15], RY[0,15]); + + #V = (RX[15,1] && RY[15,1] && !TEMP[15,1]) || + # (!RX[15,1] && !RY[15,1] && TEMP[15,1]) + V = sborrow(RX[0,15], RY[0,15]); + + NZSTATUS(RD[0,15]); + + C = 0x0; +} + +# SATADD.H Format I +# Operation: temp <- Rx + Ry; +# If(Rx[31] && Ry[31] && ~temp[31]) || (~Rx[31] && ~Ry[31] && temp[31]) then +# If Rx[31] == 0 then +# Rd <- 0x00007fff; +# else +# Rd <- 0xffff8000; +# else +# Rd <- temp; +# Syntax: satadd.h Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 0010 1100 dddd +:SATADD.H erd0, rx9, ry0 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop4_8=0x2c & erd0)) { + temp:4 = zext(rx9[0,15]) + zext(ry0[0,15]); + local if_state_1 = ((rx9[15,1] && ry0[15,1] && ~temp[15,1]) || (~rx9[15,1] && ~ry0[15,1] && temp[15,1])); + local if_state_2 = (rx9[15,1] == 0x0); + local else_state_1 = !if_state_1; + local else_state_2 = !if_state_2; + erd0 = ((zext(if_state_1 * if_state_2) * (0x00007fff)) + (zext(if_state_1 * else_state_2) * (0xffff8000)) + (zext(else_state_1) * zext(temp[0,15]))); + addSatHflags(rx9, ry0, temp, erd0); +} + + +#--------------------------------------------------------------------- +# SATSUB.W - Saturated Subtract of Words +# I. {d, x, y} -> {0, 1, ..., 15} +# II. {d, s} -> {0, 1, ..., 15} +# imm -> {-32768, -32767, ..., 32767} +#--------------------------------------------------------------------- +macro subSatWflags(OP1, OP2, TEMP, RD){ + #Q = (OP1[31,1] && !OP2[31,1] && !TEMP[31,1]) || + # (!OP1[31,1] && OP2[31,1] && TEMP[31,1]) || Q + Q = sborrow(OP1, OP2); + + #V = (OP1[31,1] && !OP2[31,1] && !TEMP[31,1]) || + # (!OP1[31,1] && OP2[31,1] && TEMP[31,1]) + V = sborrow(OP1, OP2); + + NZSTATUS(RD); + + C = 0x0; +} +# SATSUB.W Format I +# Operation: OP1 = Rx, OP2 = Ry +# temp <- Rx - Ry; +# If(OP1[31] && ~OP2[31] && ~temp[31]) || (~OP1[31] && OP2[31] && temp[31]) then +# If OP1[31] == 0 then +# Rd <- 0x7fffffff; +# else +# Rd <- 0x80000000; +# else +# Rd <- temp; +# Syntax: satsub.w Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 0001 1100 dddd +:SATSUB.W erd0, rx9, ry0 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop4_8=0x1c & erd0)) { + temp:4 = rx9 - ry0; + local if_state_1 = ((rx9[31,1] && ~ry0[31,1] && ~temp[31,1]) || (~rx9[31,1] && ry0[31,1] && temp[31,1])); + local if_state_2 = (rx9[31,1] == 0x0); + local else_state_1 = !if_state_1; + local else_state_2 = !if_state_2; + erd0 = ((zext(if_state_1 * if_state_2) * (0x7fffffff)) + (zext(if_state_1 * else_state_2) * (0x80000000)) + (zext(else_state_1) * temp)); + subSatWflags(rx9, ry0, temp, erd0); +} +# SATSUB.W Format II +# Operation: OP1 = Rx, OP2 = sext(imm16) +# temp <- Rx - Ry; +# If(OP1[31] && ~OP2[31] && ~temp[31]) || (~OP1[31] && OP2[31] && temp[31]) then +# If OP1[31] == 0 then +# Rd <- 0x7fffffff; +# else +# Rd <- 0x80000000; +# else +# Rd <- temp; +# Syntax: satsub.w Rd, Rx, Ry +# 111x xxx0 1101 dddd iiii iiii iiii iiii +:SATSUB.W rd0, rx9, simm16 is ((op13_3=0x7 & rx9 & op4_5=0xd & rd0) ; (simm16)) +{ + temp:4 = rx9 - simm16; + simm16Masked:4 = (simm16 & 0x80000000); + local if_state_1 = ((rx9[31,1] && ~simm16Masked[31,1] && ~temp[31,1]) || (~rx9[31,1] && simm16Masked[31,1] && temp[31,1])); + local if_state_2 = (rx9[31,1] == 0x0); + local else_state_1 = !if_state_1; + local else_state_2 = !if_state_2; + rd0 = ((zext(if_state_1 * if_state_2) * (0x7fffffff)) + (zext(if_state_1 * else_state_2) * (0x80000000)) + (zext(else_state_1) * temp)); + subSatWflags(rx9, simm16, temp, rd0); +} + +#--------------------------------------------------------------------- +# SATSUB.H - Saturated Subtract of Halfwords +# I. {d, s} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- +macro subSatHflags(RX, RY, TEMP, RD){ + #Q = (RX[15,1] && !RY[15,1] && !TEMP[15,1]) || + # (!RX[15,1] && RY[15,1] && TEMP[15,1]) || Q + Q = sborrow(RX[0,15], RY[0,15]); + + #V = (RX[15,1] && !RY[15,1] && !TEMP[15,1]) || + # (!RX[15,1] && RY[15,1] && TEMP[15,1]) + V = sborrow(RX[0,15], RY[0,15]); + + NZSTATUS(RD[0,15]); + + C = 0x0; +} +# SATSUB.H Format I +# Operation: temp <- Rx - Ry; +# If(Rx[15] && ~Ry[15] && ~temp[15]) || (~Rx[15] && Ry[15] && temp[15]) then +# If Rx[15] == 0 then +# Rd <- 0x00007fff; +# else +# Rd <- 0xffff8000; +# else +# Rd <- temp; +# Syntax: satsub.h Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 0011 1100 dddd +:SATSUB.H erd0, rx9, ry0 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop4_8=0x3c & erd0)) { + temp:4 = zext(rx9[0,15]) - zext(ry0[0,15]); + local if_state_1 = ((rx9[15,1] && ~ry0[15,1] && ~temp[15,1]) || (~rx9[15,1] && ry0[15,1] && temp[15,1])); + local if_state_2 = (rx9[15,1] == 0x0); + local else_state_1 = !if_state_1; + local else_state_2 = !if_state_2; + erd0 = ((zext(if_state_1 * if_state_2) * (0x00007fff)) + (zext(if_state_1 * else_state_2) * (0xffff8000)) + (zext(else_state_1) * sext(temp[0,15]))); + subSatHflags(rx9, ry0, temp, erd0); +} + +#--------------------------------------------------------------------- +# SATRNDS - Saturate with Rounding Signed +# I. {d} -> {0, 1, ..., 15} +# {sa, bp} -> {0, 1, ..., 31} +#--------------------------------------------------------------------- +SAMINUS1_CALC: is (rd0 ; esa0_5=0x0) {RDMask:4 = (rd0 & 0x00000000); export RDMask;}#0 //sa should never be 0 for this if case! +SAMINUS1_CALC: is (rd0 ; esa0_5=0x1) {RDMask:4 = (rd0 & 0x00000001); export RDMask;}#1 +SAMINUS1_CALC: is (rd0 ; esa0_5=0x2) {RDMask:4 = (rd0 & 0x00000002); export RDMask;}#2 +SAMINUS1_CALC: is (rd0 ; esa0_5=0x3) {RDMask:4 = (rd0 & 0x00000004); export RDMask;}#3 +SAMINUS1_CALC: is (rd0 ; esa0_5=0x4) {RDMask:4 = (rd0 & 0x00000008); export RDMask;}#4 +SAMINUS1_CALC: is (rd0 ; esa0_5=0x5) {RDMask:4 = (rd0 & 0x00000010); export RDMask;}#5 +SAMINUS1_CALC: is (rd0 ; esa0_5=0x6) {RDMask:4 = (rd0 & 0x00000020); export RDMask;}#6 +SAMINUS1_CALC: is (rd0 ; esa0_5=0x7) {RDMask:4 = (rd0 & 0x00000040); export RDMask;}#7 +SAMINUS1_CALC: is (rd0 ; esa0_5=0x8) {RDMask:4 = (rd0 & 0x00000080); export RDMask;}#8 +SAMINUS1_CALC: is (rd0 ; esa0_5=0x9) {RDMask:4 = (rd0 & 0x00000100); export RDMask;}#9 +SAMINUS1_CALC: is (rd0 ; esa0_5=0xa) {RDMask:4 = (rd0 & 0x00000200); export RDMask;}#10 +SAMINUS1_CALC: is (rd0 ; esa0_5=0xb) {RDMask:4 = (rd0 & 0x00000400); export RDMask;}#11 +SAMINUS1_CALC: is (rd0 ; esa0_5=0xc) {RDMask:4 = (rd0 & 0x00000800); export RDMask;}#12 +SAMINUS1_CALC: is (rd0 ; esa0_5=0xd) {RDMask:4 = (rd0 & 0x00001000); export RDMask;}#13 +SAMINUS1_CALC: is (rd0 ; esa0_5=0xe) {RDMask:4 = (rd0 & 0x00002000); export RDMask;}#14 +SAMINUS1_CALC: is (rd0 ; esa0_5=0xf) {RDMask:4 = (rd0 & 0x00004000); export RDMask;}#15 +SAMINUS1_CALC: is (rd0 ; esa0_5=0x10) {RDMask:4 = (rd0 & 0x00008000); export RDMask;}#16 +SAMINUS1_CALC: is (rd0 ; esa0_5=0x11) {RDMask:4 = (rd0 & 0x00010000); export RDMask;}#17 +SAMINUS1_CALC: is (rd0 ; esa0_5=0x12) {RDMask:4 = (rd0 & 0x00020000); export RDMask;}#18 +SAMINUS1_CALC: is (rd0 ; esa0_5=0x13) {RDMask:4 = (rd0 & 0x00040000); export RDMask;}#19 +SAMINUS1_CALC: is (rd0 ; esa0_5=0x14) {RDMask:4 = (rd0 & 0x00080000); export RDMask;}#20 +SAMINUS1_CALC: is (rd0 ; esa0_5=0x15) {RDMask:4 = (rd0 & 0x00100000); export RDMask;}#21 +SAMINUS1_CALC: is (rd0 ; esa0_5=0x16) {RDMask:4 = (rd0 & 0x00200000); export RDMask;}#22 +SAMINUS1_CALC: is (rd0 ; esa0_5=0x17) {RDMask:4 = (rd0 & 0x00400000); export RDMask;}#23 +SAMINUS1_CALC: is (rd0 ; esa0_5=0x18) {RDMask:4 = (rd0 & 0x00800000); export RDMask;}#24 +SAMINUS1_CALC: is (rd0 ; esa0_5=0x19) {RDMask:4 = (rd0 & 0x01000000); export RDMask;}#25 +SAMINUS1_CALC: is (rd0 ; esa0_5=0x1a) {RDMask:4 = (rd0 & 0x02000000); export RDMask;}#26 +SAMINUS1_CALC: is (rd0 ; esa0_5=0x1b) {RDMask:4 = (rd0 & 0x04000000); export RDMask;}#27 +SAMINUS1_CALC: is (rd0 ; esa0_5=0x1c) {RDMask:4 = (rd0 & 0x08000000); export RDMask;}#28 +SAMINUS1_CALC: is (rd0 ; esa0_5=0x1d) {RDMask:4 = (rd0 & 0x10000000); export RDMask;}#29 +SAMINUS1_CALC: is (rd0 ; esa0_5=0x1e) {RDMask:4 = (rd0 & 0x20000000); export RDMask;}#30 +SAMINUS1_CALC: is (rd0 ; esa0_5=0x1f) {RDMask:4 = (rd0 & 0x40000000); export RDMask;}#31 + +GET_TEMP_FINAL_VAL: is (rd0 ; esa0_5) & SAMINUS1_CALC +{ + sa:4 = (esa0_5 & 0xffffffff); + local if_state_1 = (sa != 0x0); + tempRDShiftTempVal:4 = rd0 >> esa0_5; + Rnd:4 = SAMINUS1_CALC; + tempRDShiftFinalVal:4 = (tempRDShiftTempVal + (zext(if_state_1) * Rnd)); + export tempRDShiftFinalVal; +} + +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x0 & esa0_5)){ if_state_2_calc:1 = 0x1; export if_state_2_calc;} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x1 & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,1]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x2 & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,2]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x3 & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,3]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x4 & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,4]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x5 & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,5]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x6 & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,6]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x7 & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,7]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x8 & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,8]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x9 & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,9]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0xa & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,10]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0xb & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,11]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0xc & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,12]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0xd & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,13]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0xe & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,14]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0xf & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,15]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x10 & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,16]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x11 & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,17]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x12 & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,18]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x13 & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,19]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x14 & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,20]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x15 & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 =sext(tempRDShiftFinal[0,21]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x16 & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,22]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x17 & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,23]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x18 & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,24]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x19 & esa0_5)) & GET_TEMP_FINAL_VAL #?NOT SURE WHY I"M GETTING "Unnecessary SEXT warning from here on? +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = tempRDShiftFinal[0,25];#sext(tempRDShiftFinal[0,25]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x1a & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = tempRDShiftFinal[0,26];#sext(tempRDShiftFinal[0,26]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x1b & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = tempRDShiftFinal[0,27];#sext(tempRDShiftFinal[0,27]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x1c & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = tempRDShiftFinal[0,28];#sext(tempRDShiftFinal[0,28]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x1d & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = tempRDShiftFinal[0,29];#sext(tempRDShiftFinal[0,29]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x1e & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = tempRDShiftFinal[0,30];#sext(tempRDShiftFinal[0,30]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC: is (rd0 ; (ebp5_5=0x1f & esa0_5)) & GET_TEMP_FINAL_VAL +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL; + tempRDShiftFinalMask:4 = tempRDShiftFinal[0,31]; + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} + + +# SATRNDS Format I +# Operation: temp <- Rd >> sa; +# if(sa != 0) +# Rnd = Rd[sa - 1]; +# temp = temp + Rnd; +# if((temp == sext(temp[bp - 1:0])) || (bp == 0)) +# Rd <- temp; +# else +# if(temp[31] == 1) +# Rd <- -2^(bp - 1); +# else +# Rd <- 2^(bp - 1); +# Syntax: satrnds Rd >> sa, bp +# 1111 0011 1011 dddd 0000 00bb bbbs ssss (where b = bp, s = sa) +:SATRNDS rd0^"<<"^esa0_5, ebp5_5 is ((op13_3=0x7 & op9_4=0x9 & op4_5=0x1B & rd0) ; (eop12_4=0x0 & eop10_2=0x0 & ebp5_5 & esa0_5)) & GET_IF_STATE2_CALC & GET_TEMP_FINAL_VAL { + bp:4 = (ebp5_5 & 0xffffffff); + bpMinus1:4 = ((ebp5_5 - 1) & 0xffffffff); + local if_state_2 = GET_IF_STATE2_CALC; + temp:4 = GET_TEMP_FINAL_VAL; + local if_state_3 = (temp[31,1] == 1); + bpM1SecondPowerNeg:4 = ((-2)**bpMinus1); + bpM1SecondPowerPos:4 = (2**bpMinus1); + local else_state_2 = !if_state_2; + local else_state_3 = !if_state_3; + rd0 = ((zext(if_state_2) * temp) + (zext(else_state_2 * if_state_3) * bpM1SecondPowerNeg) + (zext(else_state_2 * else_state_3) * bpM1SecondPowerPos)); +} + +#--------------------------------------------------------------------- +# SATRNDU - Saturate with Rounding Unsigned +# I. {d} -> {0, 1, ..., 15} +# {sa, bp} -> {0, 1, ..., 31} +#--------------------------------------------------------------------- +# SATRNDU Format I +# Operation: temp <- Rd >> sa; +# if(sa != 0) +# Rnd = Rd[sa - 1]; +# temp = temp + Rnd; +# if((temp == zext(temp[bp - 1:0])) || (bp == 0)) +# Rd <- temp; +# else +# if(temp[31] == 1) +# Rd <- 0x00000000; +# else +# Rd <- 2^(bp - 1); +# Syntax: satrndu Rd >> sa, bp +# 1111 0011 1011 dddd 0000 01bb bbbs ssss (where b = bp, s = sa) +:SATRNDU rd0^"<<"^esa0_5, ebp5_5 is ((op13_3=0x7 & op9_4=0x9 & op4_5=0x1B & rd0) ; (eop12_4=0x0 & eop10_2=0x1 & ebp5_5 & esa0_5)) & GET_IF_STATE2_CALC & GET_TEMP_FINAL_VAL { + bp:4 = (ebp5_5 & 0xffffffff); + bpMinus1:4 = ((ebp5_5 - 1) & 0xffffffff); + local if_state_2 = GET_IF_STATE2_CALC; + temp:4 = GET_TEMP_FINAL_VAL; + local if_state_3 = (temp[31,1] == 1); + zero32BitVal:4 = 0x00000000; + bpM1SecondPowerPos:4 = (2**bpMinus1); + local else_state_2 = !if_state_2; + local else_state_3 = !if_state_3; + rd0 = ((zext(if_state_2) * temp) + (zext(else_state_2 * if_state_3) * zero32BitVal) + (zext(else_state_2 * else_state_3) * bpM1SecondPowerPos)); +} + +#--------------------------------------------------------------------- +# SATS - Saturate Signed +# I. {d} -> {0, 1, ..., 15} +# {sa, bp} -> {0, 1, ..., 31} +#--------------------------------------------------------------------- +GET_TEMP_FINAL_VAL_NR: is (rd0 ; esa0_5) & SAMINUS1_CALC +{ + tempRDShiftFinalVal:4 = rd0 >> esa0_5; + export tempRDShiftFinalVal; +} + +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x0 & esa0_5)){ if_state_2_calc:1 = 0x1; export if_state_2_calc;} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x1 & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,1]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x2 & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,2]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x3 & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,3]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x4 & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,4]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x5 & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,5]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x6 & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,6]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x7 & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,7]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x8 & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,8]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x9 & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,9]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0xa & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,10]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0xb & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,11]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0xc & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,12]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0xd & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,13]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0xe & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,14]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0xf & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,15]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x10 & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,16]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x11 & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,17]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x12 & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,18]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x13 & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,19]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x14 & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,20]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x15 & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 =sext(tempRDShiftFinal[0,21]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x16 & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,22]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x17 & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,23]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x18 & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = sext(tempRDShiftFinal[0,24]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x19 & esa0_5)) & GET_TEMP_FINAL_VAL_NR #?NOT SURE WHY I"M GETTING "Unnecessary SEXT warning from here on? +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = tempRDShiftFinal[0,25];#sext(tempRDShiftFinal[0,25]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x1a & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = tempRDShiftFinal[0,26];#sext(tempRDShiftFinal[0,26]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x1b & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = tempRDShiftFinal[0,27];#sext(tempRDShiftFinal[0,27]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x1c & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = tempRDShiftFinal[0,28];#sext(tempRDShiftFinal[0,28]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x1d & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = tempRDShiftFinal[0,29];#sext(tempRDShiftFinal[0,29]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x1e & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = tempRDShiftFinal[0,30];#sext(tempRDShiftFinal[0,30]); + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +GET_IF_STATE2_CALC_NR: is (rd0 ; (ebp5_5=0x1f & esa0_5)) & GET_TEMP_FINAL_VAL_NR +{ tempRDShiftFinal:4 = GET_TEMP_FINAL_VAL_NR; + tempRDShiftFinalMask:4 = tempRDShiftFinal[0,31]; + local if_state_2_calc = (tempRDShiftFinal == tempRDShiftFinalMask); export if_state_2_calc; +} +#SATS Format I +#Operation: temp <- Rd >> sa; +# if((temp == sext(temp[bp - 1:0])) || (bp == 0)) +# Rd <- temp; +# else +# if(temp[31] == 1) +# Rd <- -2^(bp - 1); +# else +# Rd <- 2^(bp - 1); +# Syntax: sats Rd >> sa, bp +# 1111 0001 1011 dddd 0000 00bb bbbs ssss (where b = bp, s = sa) +:SATS rd0^"<<"^esa0_5, ebp5_5 is ((op13_3=0x7 & op9_4=0x8 & op4_5=0x1B & rd0) ; (eop12_4=0x0 & eop10_2=0x0 & ebp5_5 & esa0_5)) & GET_IF_STATE2_CALC_NR & GET_TEMP_FINAL_VAL_NR { +bp:4 = (ebp5_5 & 0xffffffff); + bpMinus1:4 = ((ebp5_5 - 1) & 0xffffffff); + local if_state_2 = GET_IF_STATE2_CALC_NR; + temp:4 = GET_TEMP_FINAL_VAL_NR; + local if_state_3 = (temp[31,1] == 1); + bpM1SecondPowerNeg:4 = ((-2)**bpMinus1); + bpM1SecondPowerPos:4 = (2**bpMinus1); + local else_state_2 = !if_state_2; + local else_state_3 = !if_state_3; + rd0 = ((zext(if_state_2) * temp) + (zext(else_state_2 * if_state_3) * bpM1SecondPowerNeg) + (zext(else_state_2 * else_state_3) * bpM1SecondPowerPos)); +} + +#--------------------------------------------------------------------- +# SATU - Saturate Unsigned +# I. {d} -> {0, 1, ..., 15} +# {sa, bp} -> {0, 1, ..., 31} +#--------------------------------------------------------------------- +# SATU Format I +# Operation: temp <- Rd >> sa; +# if((temp == zext(temp[bp - 1:0])) || (bp == 0)) +# Rd <- temp; +# else +# if(temp[31] == 1) +# Rd <- 0x00000000; +# else +# Rd <- 2^(bp - 1); +# Syntax: satrndu Rd >> sa, bp +# 1111 0011 1011 dddd 0000 01bb bbbs ssss (where b = bp, s = sa) +:SATU rd0^"<<"^esa0_5, ebp5_5 is ((op13_3=0x7 & op9_4=0x8 & op4_5=0x1B & rd0) ; (eop12_4=0x0 & eop10_2=0x1 & ebp5_5 & esa0_5)) & GET_IF_STATE2_CALC_NR & GET_TEMP_FINAL_VAL_NR { + bp:4 = (ebp5_5 & 0xffffffff); + bpMinus1:4 = ((ebp5_5 - 1) & 0xffffffff); + local if_state_2 = GET_IF_STATE2_CALC_NR; + temp:4 = GET_TEMP_FINAL_VAL_NR; + local if_state_3 = (temp[31,1] == 1); + zero32BitVal:4 = 0x00000000; + bpM1SecondPowerPos:4 = (2**bpMinus1); + local else_state_2 = !if_state_2; + local else_state_3 = !if_state_3; + rd0 = ((zext(if_state_2) * temp) + (zext(else_state_2 * if_state_3) * zero32BitVal) + (zext(else_state_2 * else_state_3) * bpM1SecondPowerPos)); +} + +#--------------------------------------------------------------------- +# SUBHH.W - Subtract Halfwords into Word +# I. {d, x, y} -> {0, 1, ..., 15} +# part -> {t, b} +#--------------------------------------------------------------------- +# SUBHH.W Format I +# Operation: If(Rx-part==t) then operand1=SE(Rx[31:16]) else operand1=SE(Rx[15:0]); +# If(Ry-part==t) then operand2=SE(Ry[31:16]) else operand2=SE(Ry[15:0]); +# Rd <- operand1 - operand2; +# Syntax: subhh.w Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 1111 00XY dddd +# Assumption: t = 1, b = 0 using XY +:SUBHH.W erd0, rx9^operand1, ry0^operand2 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop8_4=0xf & eop6_2=0x0 & selectorxy4_2 & erd0)) & operand1 & operand2 { + erd0 = operand1 - operand2; + subflags(operand1, operand2, erd0); + } + + +#--------------------------------------------------------------------- +# MULSATHH.W - Multiply Halfwords with Saturation into Halfword +# I. {d, x, y} -> {0, 1, ..., 15} +# part -> {t, b} +#--------------------------------------------------------------------- +# MULSATHH.W Format I +# Operation: If(Rx-part==t) then operand1=SE(Rx[31:16]) else operand1=SE(Rx[15:0]); +# If(Ry-part==t) then operand2=SE(Ry[31:16]) else operand2=SE(Ry[15:0]); +# If(operand1 == operand2 == 0x8000) +# Rd <- 0x7FFF; +# else +# Rd <- sext((operand1 * operand2) >> 15); +# Syntax: mulsahh.w Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 1000 10XY dddd +# Assumption: t = 1, b = 0 using XY +:MULSATHH.W erd0, rx9^operand1, ry0^operand2 is ((op13_3=0x7 & rx9 & op4_5=0x0 & ry0) ; (eop12_4=0x0 & eop8_4=0x8 & eop6_2=0x2 & selectorxy4_2 & erd0)) & operand1 & operand2 { + compareValx8000:4 = 0x8000; + local if_state_3_a = (operand1 == compareValx8000); + local if_state_3_b = (operand2 == compareValx8000); + local if_state_3 = (if_state_3_a == if_state_3_b); + local else_state_3 = !if_state_3; + sat_clamp_val:4 = 0x7FFF; + nonSatMultVal:4 = ((operand1 * operand2) >> 15); + erd0 = ((zext(if_state_3) * sat_clamp_val) + (zext(else_state_3) * nonSatMultVal)); + + } + diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_dsp_operations2.sinc b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_dsp_operations2.sinc new file mode 100644 index 0000000..d9c39b5 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_dsp_operations2.sinc @@ -0,0 +1,392 @@ +#--------------------------------------------------------------------- +# 8.3.4 DSP Operations +# +# Note: all DSP operations are stubbed out with custom pcode ops, +# because their literal implementations are generally too difficult. +#--------------------------------------------------------------------- + +macro satdspmulh(OP1, OP2, RES, RND, TMP1) { + TMP1 = (OP1 == 0x8000) & (OP2 == 0x8000); + Q = Q | TMP1; + RES = (zext(TMP1) * 0x3FFF8000) + (zext(TMP1 == 0) * ((sext(OP1) * sext(OP2)) + zext(RND))); +} + +macro satdspsh(RES) { + V = (RES s> 0x00007FFF) | (RES s< 0xFFFF8000); + Q = V | Q; + RES = (0x00007FFF * zext(RES s> 0x00007FFF)) + (RES * zext(RES s< 0x00008000) * zext(RES s>= 0xFFFF8000)) + (0x00008000 * zext(RES s< 0xFFFF8000)); +} + +macro satdspsw(RES) { + V = (RES s> 0x000000007FFFFFFF) | (RES s< 0xFFFFFFFF80000000); + Q = V | Q; + RES = (0x000000007FFFFFFF * zext(RES s> 0x000000007FFFFFFF)) + (RES * zext(RES s< 0x0000000080000000) * zext(RES s>= 0xFFFFFFFF80000000)) + (0x0000000080000000 * zext(RES s< 0xFFFFFFFF80000000)); +} + + +XPART: ":T" is ctx_usex & xpart=0x1 { + tmp:4 = ctx_usex; + tmp = tmp >> 16; + tmpa:2 = tmp:2; + tmpb:4 = sext(tmpa); + export *:4 tmpb; +} + +XPART: ":B" is ctx_usex & xpart=0x0 { + tmp:4 = ctx_usex; + tmp = tmp & 0xFFFF; + tmpa:2 = tmp:2; + tmpb:4 = sext(tmpa); + export *:4 tmpb; +} + +YPART: ":T" is ctx_usey & ypart=0x1 { + tmp:4 = ctx_usey; + tmp = tmp >> 16; + tmpa:2 = tmp:2; + tmpb:4 = sext(tmpa); + export *:4 tmpb; +} + +YPART: ":B" is ctx_usey & ypart=0x0 { + tmp:4 = ctx_usey; + tmp = tmp & 0xFFFF; + tmpa:2 = tmp:2; + tmpb:4 = sext(tmpa); + export *:4 tmpb; +} + +:ADDHH.W erd0, rx9^XPART, ry0^YPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ; + eop6_10=0x38 & XPART & YPART & erd0 [ctx_savex=rx9; ctx_savey=ry0; ] +{ + erd0 = XPART + YPART; + addflags(XPART, YPART, erd0); +} + + +:MACHH.D erd0, rx9^XPART, ry0^YPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ; + eop6_10=0x16 & XPART & YPART & erd0 & erd0a & ctx_rdplus [ctx_savex=rx9; ctx_savey=ry0; ctx_rdsave=erd0a+1; ] +{ + tmp:4 = XPART * YPART; + tmp64a:8 = zext(tmp); + tmp64b:8 = zext(erd0); + tmp64c:8 = zext(ctx_rdplus); + tmp64b = (tmp64c << 32) | tmp64b; + tmp64a = (tmp64a << 16) + tmp64b; + tmp64b = tmp64a >> 32; + erd0 = tmp64a:4 & 0xFFFF0000; + ctx_rdplus= tmp64b:4; +} + + +:MACHH.W erd0, rx9^XPART, ry0^YPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ; + eop6_10=0x12 & XPART & YPART & erd0 [ctx_savex=rx9; ctx_savey=ry0; ] +{ + erd0 = erd0 + (XPART * YPART); +} + +:MACSATHH.W erd0, rx9^PXPART, ry0^PYPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ; + eop6_10=0x1a & PXPART & PYPART & erd0 +{ + TMPX:2 = PXPART; + TMPY:2 = PYPART; + RES:4 = 0; + RND:2 = 0; + TMP:1 = 0; + satdspmulh(TMPX,TMPY,RES,RND,TMP); + RES = RES << 1; + BIG:8 = sext(RES) + sext(erd0); + satdspsw(BIG); + QTOSR(); +} + + +:MACWH.D erd0, rx9, ry0^YPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ; + eop5_11=0x64 & YPART & erd0 & erd0a & ctx_rdplus [ctx_savey=ry0; ctx_rdsave=erd0a+1; ] +{ + tmp64a:8 = sext(rx9); + tmp64b:8 = sext(YPART); + tmp64a = tmp64a * tmp64b; + tmp64b = zext(ctx_rdplus); + tmp64c:8 = zext(erd0); + tmp64b = (tmp64b << 32) | tmp64c; + tmp64b = tmp64b + (tmp64a << 16); + tmp64a = tmp64b >> 32; + erd0 = tmp64b:4 & 0xFFFF0000; + ctx_rdplus = tmp64a:4; +} + + +:MULHH.W erd0, rx9^XPART, ry0^YPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ; + eop6_10=0x1e & XPART & YPART & erd0 [ctx_savex=rx9; ctx_savey=ry0; ] +{ + erd0 = XPART * YPART; +} + +:MULNHH.W erd0, rx9^XPART, ry0^YPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ; + eop6_10=0x6 & XPART & YPART & erd0 [ctx_savex=rx9; ctx_savey=ry0; ] +{ + erd0 = XPART * YPART; + if (erd0 == 0) goto inst_next; + erd0 = (~erd0) + 1; +} + +:MULNWH.D erd0, rx9, ry0^YPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ; + eop5_11=0x14 & YPART & erd0 & erd0a & ctx_rdplus [ctx_savey=ry0; ctx_rdsave=erd0a+1; ] +{ + tmp64a:8 = sext(rx9); + tmp64b:8 = sext(YPART); + tmp64a = tmp64a * tmp64b; + erd0 = 0; + ctx_rdplus = 0; + if (tmp64a == 0) goto inst_next; + tmp64a = (~tmp64a) + 1; + erd0 = tmp64a:4; + erd0 = erd0 << 16; + tmp64a = tmp64a s>> 16; + ctx_rdplus = tmp64a:4; +} + +:MULSATHH.H erd0, rx9^PXPART, ry0^PYPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ; + eop6_10=0x22 & PXPART & PYPART & erd0 +{ + TMPX:2 = PXPART; + TMPY:2 = PYPART; + RES:4 = 0; + RND:2 = 0; + TMP:1 = 0; + satdspmulh(TMPX,TMPY,RES,RND,TMP); + RES = RES >> 15; + erd0 = sext(RES:2); + QTOSR(); +} + + +:MULSATHH.W erd0, rx9^PXPART, ry0^PYPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ; + eop6_10=0x26 & PXPART & PYPART & erd0 +{ + TMPX:2 = PXPART; + TMPY:2 = PYPART; + RES:4 = 0; + RND:2 = 0; + TMP:1 = 0; + satdspmulh(TMPX,TMPY,RES,RND,TMP); + erd0 = RES << 1; + QTOSR(); +} + + +:MULSATRNDHH.H erd0, rx9^PXPART, ry0^PYPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ; + eop6_10=0x2a & PXPART & PYPART & erd0 +{ + TMPX:2 = PXPART; + TMPY:2 = PYPART; + RES:4 = 0; + RND:2 = 0x4000; + TMP:1 = 0; + satdspmulh(TMPX,TMPY,RES,RND,TMP); + RES = RES >> 15; + erd0 = sext(RES:2); + QTOSR(); +} + +:MULSATRNDWH.W erd0, rx9, ry0^YPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ; + eop5_11=0x5c & YPART & erd0 +{ + SAT:1 = (rx9 == 0x80000000) && (YPART == 0xFFFF8000); + TMP:8 = ((sext(rx9) * sext(YPART)) + 0x4000) s>> 15; + erd0 = (zext(SAT) * 0x7FFFFFFF) + zext(SAT == 0) * TMP:4; +} + + +:MULSATWH.W erd0, rx9, ry0^YPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ; + eop5_11=0x74 & YPART & erd0 +{ + SAT:1 = (rx9 == 0x80000000) && (YPART == 0xFFFF8000); + TMP:8 = (sext(rx9) * sext(YPART)) s>> 15; + erd0 = (zext(SAT) * 0x7FFFFFFF) + zext(SAT == 0) * TMP:4; +} + + +:MULWH.D erd0, rx9, ry0^YPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ; + eop5_11=0x6c & YPART & erd0 & erd0a & ctx_rdplus [ctx_savey=ry0; ctx_rdsave=erd0a+1; ] +{ + tmp64a:8 = sext(rx9); + tmp64b:8 = sext(YPART); + tmp64a = tmp64a * tmp64b; + erd0 = tmp64a:4; + erd0 = erd0 << 16; + tmp64a = tmp64a s>> 16; + ctx_rdplus = tmp64a:4; +} + +:SATADD.H erd0, rx9, ry0 is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ; + eop4_12=0x2c & erd0 +{ + TMP:4 = zext(rx9:2) + zext(ry0:2); + satdspsh(TMP); + erd0 = sext(TMP:2); + N = (erd0 & 0x8000) != 0; + Z = (erd0 == 0); + C = 0; + CZNVQTOSR(); +} + + +:SATADD.W erd0, rx9, ry0 is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ; + eop4_12=0xc & erd0 +{ + TMP:8 = zext(rx9) + zext(ry0); + satdspsw(TMP); + erd0 = TMP:4; + N = (erd0 & 0x80000000) != 0; + Z = (erd0 == 0); + C = 0; + CZNVQTOSR(); +} + + + + +SATM: is ebp5_5=0 { tmp:4 = 0x00000000; export tmp; } +SATM: is ebp5_5=1 { tmp:4 = 0xFFFFFFFF; export tmp; } +SATM: is ebp5_5=2 { tmp:4 = 0xFFFFFFFE; export tmp; } +SATM: is ebp5_5=3 { tmp:4 = 0xFFFFFFFC; export tmp; } +SATM: is ebp5_5=4 { tmp:4 = 0xFFFFFFF8; export tmp; } +SATM: is ebp5_5=5 { tmp:4 = 0xFFFFFFF0; export tmp; } +SATM: is ebp5_5=6 { tmp:4 = 0xFFFFFFE0; export tmp; } +SATM: is ebp5_5=7 { tmp:4 = 0xFFFFFFC0; export tmp; } +SATM: is ebp5_5=8 { tmp:4 = 0xFFFFFF80; export tmp; } +SATM: is ebp5_5=9 { tmp:4 = 0xFFFFFF00; export tmp; } +SATM: is ebp5_5=10 { tmp:4 = 0xFFFFFE00; export tmp; } +SATM: is ebp5_5=11 { tmp:4 = 0xFFFFFC00; export tmp; } +SATM: is ebp5_5=12 { tmp:4 = 0xFFFFF800; export tmp; } +SATM: is ebp5_5=13 { tmp:4 = 0xFFFFF000; export tmp; } +SATM: is ebp5_5=14 { tmp:4 = 0xFFFFE000; export tmp; } +SATM: is ebp5_5=15 { tmp:4 = 0xFFFFC000; export tmp; } +SATM: is ebp5_5=16 { tmp:4 = 0xFFFF8000; export tmp; } +SATM: is ebp5_5=17 { tmp:4 = 0xFFFF0000; export tmp; } +SATM: is ebp5_5=18 { tmp:4 = 0xFFFE0000; export tmp; } +SATM: is ebp5_5=19 { tmp:4 = 0xFFFC0000; export tmp; } +SATM: is ebp5_5=20 { tmp:4 = 0xFFF80000; export tmp; } +SATM: is ebp5_5=21 { tmp:4 = 0xFFF00000; export tmp; } +SATM: is ebp5_5=22 { tmp:4 = 0xFFE00000; export tmp; } +SATM: is ebp5_5=23 { tmp:4 = 0xFFC00000; export tmp; } +SATM: is ebp5_5=24 { tmp:4 = 0xFF800000; export tmp; } +SATM: is ebp5_5=25 { tmp:4 = 0xFF000000; export tmp; } +SATM: is ebp5_5=26 { tmp:4 = 0xFE000000; export tmp; } +SATM: is ebp5_5=27 { tmp:4 = 0xFC000000; export tmp; } +SATM: is ebp5_5=28 { tmp:4 = 0xF8000000; export tmp; } +SATM: is ebp5_5=29 { tmp:4 = 0xF0000000; export tmp; } +SATM: is ebp5_5=30 { tmp:4 = 0xE0000000; export tmp; } +SATM: is ebp5_5=31 { tmp:4 = 0xC0000000; export tmp; } + +:SATRNDS rd0^" >> "^esa0_5, ebp5_5^SATM is op4_12=0xf3b & rd0 ; + eop10_6=0x0 & esa0_5 & ebp5_5 & SATM +{ + build SATM; + BIT:1 = ebp5_5; + BITA:1 = esa0_5; + TMP:4 = rd0 s>> esa0_5; + TMP = TMP + (zext(BITA != 0) * (rd0 & (1 << (esa0_5 - 1)))); + TMPA:4 = TMP << (32-ebp5_5); + TMPB:4 = TMPA s>> (32-ebp5_5); + NSAT:1 = (TMP == TMPB) || (BIT == 0x0); + TMPC:1 = (TMP & 0x80000000) != 0; + rd0 = (TMP * zext(NSAT)) + (zext(NSAT == 0) * ((zext(TMPC) * SATM) + ((1 << (ebp5_5-1) - 1) * zext(TMPC == 0)))); + Q = Q || (NSAT != 0); + QTOSR(); +} + + +:SATRNDU rd0^" >> "^esa0_5, ebp5_5 is op4_12=0xf3b & rd0 ; + eop10_6=0x1 & esa0_5 & ebp5_5 +{ + BIT:1 = ebp5_5; + BITA:1 = esa0_5; + TMP:4 = rd0 >> esa0_5; + TMP = TMP + (zext(BITA != 0) * (rd0 & (1 << (esa0_5 - 1)))); + TMPA:4 = TMP << (32-ebp5_5); + TMPB:4 = TMPA >> (32-ebp5_5); + NSAT:1 = (TMP == TMPB) || (BIT == 0x0); + TMPC:1 = (TMP & 0x80000000) == 0; + rd0 = (TMP * zext(NSAT)) + (zext(NSAT == 0) * zext(TMPC) * ((1 << ebp5_5) - 1)); + Q = Q || (NSAT != 0); + QTOSR(); +} + +:SATS rd0^" >> "^esa0_5, ebp5_5^SATM is op4_12=0xf1b & rd0 ; + eop10_6=0x0 & esa0_5 & ebp5_5 & SATM +{ + build SATM; + BIT:1 = ebp5_5; + TMP:4 = rd0 s>> esa0_5; + TMPA:4 = TMP << (32-ebp5_5); + TMPB:4 = TMPA s>> (32-ebp5_5); + NSAT:1 = (TMP == TMPB) || (BIT == 0x0); + TMPC:1 = (TMP & 0x80000000) != 0; + rd0 = (TMP * zext(NSAT)) + (zext(NSAT == 0) * ((zext(TMPC) * SATM) + ((1 << (ebp5_5-1) - 1) * zext(TMPC == 0)))); + Q = Q || (NSAT != 0); + QTOSR(); +} + + +:SATSUB.H erd0, rx9, ry0 is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ; + eop4_12=0x3c & erd0 +{ + TMP:4 = zext(rx9:2) - zext(ry0:2); + satdspsh(TMP); + erd0 = sext(TMP:2); + N = (erd0 & 0x8000) != 0; + Z = (erd0 == 0); + C = 0; + CZNVQTOSR(); +} + +:SATSUB.W erd0, rx9, ry0 is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ; + eop4_12=0x1c & erd0 +{ + TMP:8 = zext(rx9) - zext(ry0); + satdspsw(TMP); + erd0 = TMP:4; + N = (erd0 & 0x80000000) != 0; + Z = (erd0 == 0); + C = 0; + CZNVQTOSR(); +} + +:SATSUB.W rd0, rs9, simm16 is op13_3=0x7 & op4_5=0xd & rd0 & rs9 ; + simm16 +{ + TMPY:2 = simm16; + TMP:8 = zext(rs9) - sext(TMPY); + satdspsw(TMP); + rd0 = TMP:4; + N = (rd0 & 0x80000000) != 0; + Z = (rd0 == 0); + C = 0; + CZNVQTOSR(); +} + + +:SATU rd0^" >> "^esa0_5, ebp5_5 is op4_12=0xf1b & rd0 ; + eop10_6=0x1 & esa0_5 & ebp5_5 +{ + BIT:1 = ebp5_5; + TMP:4 = rd0 >> esa0_5; + TMPA:4 = TMP << (32-ebp5_5); + TMPB:4 = TMPA >> (32-ebp5_5); + NSAT:1 = (TMP == TMPB) || (BIT == 0x0); + TMPC:1 = (TMP & 0x80000000) == 0; + rd0 = (TMP * zext(NSAT)) + (zext(NSAT == 0) * zext(TMPC) * ((1 << ebp5_5) - 1)); + Q = Q || (NSAT != 0); + QTOSR(); +} + + +:SUBHH.W erd0, rx9^XPART, ry0^YPART is op13_3=0x7 & op4_5=0x0 & rx9 & ry0 ; + eop6_10=0x3c & XPART & YPART & erd0 [ctx_savex=rx9; ctx_savey=ry0; ] +{ + erd0 = XPART - YPART; + subflags(XPART, YPART, erd0); +} diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_instruction_flow.sinc b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_instruction_flow.sinc new file mode 100644 index 0000000..2397036 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_instruction_flow.sinc @@ -0,0 +1,272 @@ +#--------------------------------------------------------------------- +# 8.3.8 INSTRUCTION FLOW +#--------------------------------------------------------------------- + +#--------------------------------------------------------------------- +# ACALL - Application Call +# I. disp -> {0, 4, ..., 1020} +#--------------------------------------------------------------------- + +# ACALL Format I: +# Operation: LR <- PC + 2 +# Syntax: acall disp +# 1101 nnnn nnnn 0000 + +ACALLdisp: disp is disp4_8 [ disp = ACBA + (disp4_8 << 2); ] { export *:4 disp; } + +:ACALL ACALLdisp is op12_4=0xd & op0_4=0 & ACALLdisp +{ + LR = inst_next; + call ACALLdisp; +} + +#--------------------------------------------------------------------- +# RET{cond4} - Conditional Return from Subroutine +# I. cond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al} +# s -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +retCond4Sub: rs0 is rs0 & rs0=0xf { R12 = 0x1;} #PC (0xf) +retCond4Sub: rs0 is rs0 & rs0=0xe { R12 = -0x1;} #LR (0xe) +retCond4Sub: rs0 is rs0 & rs0=0xd { R12 = 0x0;} #SP (0xd) +retCond4Sub: rs0 is rs0 & rs0=0xc {} #Else R12 is R12 +retCond4Sub: rs0 is rs0 {R12 = rs0;} #Else + + +#RET{Cond4} Format I: +#Operation: +# Conditional return from subroutine with move and test of return value: +# if (Rs != {LR, SP, PC}) +# R12 <- Rs +# PC <- LR +# Conditional return from subroutine with return of false value: +# else if (Rs == LR) +# R12 <- -1 +# PC <- LR +# Conditional return from subroutine with return of false value: +# else if (Rs == SP) +# R12 <- 0 +# PC <- LR +# Conditional return from subroutine with return of true value: +# else if (Rs == PC) +# R12 <- 1 +# PC <- LR +#Syntax: ret{cond4} Rs +#010 1111 0 CCCC ssss +#0101 1110 CCCC ssss +:RET^{COND_4_4} retCond4Sub is op13_3=0x2 & op9_4=0xf & op8_1 = 0x0 & COND_4_4 & retCond4Sub { + # Test Condition + build COND_4_4; + build retCond4Sub; + # Flags Set: + V = 0x0; + C = 0x0; + NZSTATUS(R12); + # End Operation: + #PC = LR; + return [ LR ]; +} + +#--------------------------------------------------------------------- +# BR{cond} - Branch if Condition Satisfied +# I. cond3 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl} +# disp -> {-256, -254, ..., 254} +# II. cond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al} +# disp -> {-2097152, -2097150, ..., 2097150} +#--------------------------------------------------------------------- + +sDisp8: sdisp is sdisp4_8 +[ sdisp = inst_start + (sdisp4_8 << 1); ] +{ + export *:4 sdisp; +} + +sDisp21: sdisp21 is disp21part2_4_1 & disp21part3_9_4; disp21part1_0_16 +[ sdisp21 = inst_start + (((disp21part3_9_4 << 17) | (disp21part2_4_1 << 16) | disp21part1_0_16) << 1); ] +{ + export *:4 sdisp21; +} + +#BR{cond3} Format I: +#Operation: +# Branch if condition satisfied: +# if(cond3) +# PC <- PC + (SE(disp8)<<1) +# else +# PC <- PC + 2; +#Syntax: br{cond3}disp +#110 0 nnnnnnnn 0 CCC +#1100 nnnn nnnn 0CCC + + +:BR^{COND_3} sDisp8 is op13_3=0x6 & op12_1=0x0 & op3_1 = 0x0 & COND_3 & sDisp8 +{ + tst:1 = COND_3; + if (tst) goto sDisp8; +} + +#BR{cond4} Format II: +#Operation: +# Branch if condition satisfied: +# if(cond4) +# PC <- PC + (SE(disp21)<<1) +# else +# PC <- PC + 4; +#Syntax: br{cond3}disp +#111 nnnn 0100 n CCCC nnnnnnnnnnnnnnnn +#111n nnn0 100n CCCC nnnn nnnn nnnn nnnn +:BR^{COND_4_0} sDisp21 is (op13_3=0x7 & op5_4=0x4 & COND_4_0) ... & sDisp21 +{ + build COND_4_0; + goto sDisp21; +} + +#--------------------------------------------------------------------- +# RJMP - Relative Jump +# I. disp -> {-1024, -1022, ..., 1022} +#--------------------------------------------------------------------- + +# RJMP Format I: +# Operation: PC <- PC + (SE(disp10)<<1); +# Syntax: rjmp PC[disp] +# 1100 nnnn nnnn 10nn + +RJMPdisp: disp is disp4_8 & sdisp0_2 +[ disp = inst_start + (((sdisp0_2 << 8) | disp4_8) << 1); ] +{ + export *:4 disp; +} + +:RJMP RJMPdisp is op12_4=0xc & op2_2=0x2 & RJMPdisp +{ + goto RJMPdisp; +} + +#--------------------------------------------------------------------- +# ICALL - Subroutine Call +# I. d -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# ICALL Format I: +# Operation: LR <- PC + 2 +# PC <- Rd +# Syntax: icall Rd +# 0101 1101 0001 dddd + +:ICALL rd0 is op4_12=0x5d1 & rd0 { + LR = inst_next; + call [rd0]; +} + +#--------------------------------------------------------------------- +# MCALL - Subroutine Call +# I. p -> {0, 1, ..., 15} +# disp -> {-131072, -131068, ..., 131068} +#--------------------------------------------------------------------- + +RP0Disp16: rp0^"["^disp^"]" is rp0; disp_16 +[ disp = (disp_16 << 2); ] +{ + val:4 = (rp0 & 0xfffffffc) + disp; + export *:4 val; +} + +RP0Disp16_2: PC[disp] is disp_16 & PC +[ disp = (inst_start & 0xfffffffc) + (disp_16 << 2); ] +{ + export *:4 disp; +} + +# MCALL Format I: +# Operation: LR <- PC + 4 +# PC <- *((Rp & 0xfffffffc) + (SE(disp16) << 2)) +# Syntax: mcall Rp[disp] +# 1111 0000 0001 pppp nnnn nnnn nnnn nnnn + +IndirectPlaceHolder: " " is epsilon{} + +:MCALL RP0Disp16 is op4_12=0xf01 ... & RP0Disp16 { + LR = inst_next; + PC = RP0Disp16; + call [PC]; +} + +:MCALL RP0Disp16_2^IndirectPlaceHolder is op4_12=0xf01 & rp0=0xf ; RP0Disp16_2 & IndirectPlaceHolder { + LR = inst_next; + PC = RP0Disp16_2; + call [PC]; +} + +RelDisp10: val is disp4_8 & disp0_2 [ctx_rel0_8=disp4_8; ctx_rel8_2=disp0_2; val= inst_start + (ctx_rel10 << 1); ] { + export *:4 val; +} + +RelDisp21: val is imm16 [ctx_rel0_16=imm16; val=inst_start + (ctx_rel21 << 1); ] { + export *:4 val; +} + +:RCALL PC[RelDisp10] is op13_3=6 & op12_1=0 & b02=1 & b03=1 & PC & RelDisp10 { + LR = inst_next; + call RelDisp10; +} + +:RCALL PC[RelDisp21] is op13_3=7 & op5_4=5 & op0_4=0 & PC & b04 & bp9_4; RelDisp21 [ctx_rel16_1=b04; ctx_rel17_4=bp9_4;] { + LR = inst_next; + call RelDisp21; +} + +# The RETx instructions are somewhat complicated. The architecutre version (A/B) +# determines hardware actions as well as the status of the mode bits M2:M0. For now, +# we follow the "B" model as it's simpler and have a custom pcode. For RETE I also +# picked a given interrupt level that would actually be determined by the mode bits. +:RETD is op0_16=0xd623 { + SR = RSR_DBG; + SRTOFLAGS(); + return [ RAR_DBG ]; +} + +:RETE is op0_16=0xd603 { + CheckAndRestoreInterupt(); + SR = RSR_INT0; + SRTOFLAGS(); + L = 0; + LTOSR(); + return [ RAR_INT0 ]; +} + +:RETS is op0_16=0xd613 { + CheckAndRestoreSupervisor(); + SR = RSR_SUP; + SRTOFLAGS(); + return [ RAR_SUP ]; +} + +:RETJ is op0_16=0xd633 { + JavaTrap(); + J = 1; + R = 0; + JRGMTOSR(); + return [ LR ]; +} + +:SCALL is op0_16=0xd733 { + SupervisorCallSetup(); + LR = inst_next; + tmp:4 = EVBA + 0x100; + call [ tmp ]; +} + +JV3: val is b06=1 & ctx_rel3 [ val = ctx_rel3 << 0; ] { export *[const]:1 val; } +JV3: val is b06=0 & disp4_3 [ val = disp4_3+1; ] { export *[const]:1 val; } +:INCJOSP JV3 is op7_9=0x1ad & op0_4=0x3 & disp4_3 & JV3 [ctx_rel3 = disp4_3;] { + JavaCheckStack(JOSP,JV3); + JOSP = JOSP + sext(JV3); +} + +:POPJC is op0_16=0xd713 { + JavaPopContext(); +} + +:PUSHJC is op0_16=0xd723 { + JavaPushContext(); +} diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_logic_operations.sinc b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_logic_operations.sinc new file mode 100644 index 0000000..c842908 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_logic_operations.sinc @@ -0,0 +1,496 @@ +#--------------------------------------------------------------------- +# 8.3.5 Logic Operations +#--------------------------------------------------------------------- + +#--------------------------------------------------------------------- +# AND - Logical AND with optional logical shift +# I. {d, s} -> {0, 1, ..., 15} +# II, III. {d, x, y} -> {0, 1, ..., 15} +# sa -> {0, 1, ..., 31} +#--------------------------------------------------------------------- + +# AND Format I +# Operation: Rd <- Rd & Rs +# Syntax: and Rd, Rs +# 000s sss0 0110 dddd + +:AND rd0, RS9A is op13_3=0x0 & op4_5=0x6 & rd0 & RS9A { + rd0 = rd0 & RS9A; + NZSTATUS(rd0); +} + +:AND rd0, RS9A is op13_3=0x0 & op4_5=0x6 & rd0 & RS9A & rd0=0xf { + PC = inst_start & RS9A; + NZSTATUS(PC); + goto [PC]; +} + +# AND Format II +# Operation: Rd <- Rx & Ry << sa5 +# Syntax: and Rd, Rx, Ry << sa +# 111x xxx1 1110 yyyy 0000 000t tttt dddd + +:AND erd0, RX9A, RY0A^" << " shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A; + eop9_7=0 & erd0 & shift4_5 { + erd0 = RX9A & (RY0A << shift4_5); + NZSTATUS(erd0); +} + +:AND erd0, RX9A, RY0A^" << " shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A; + eop9_7=0 & erd0 & shift4_5 & erd0=0xf { + PC = RX9A & (RY0A << shift4_5); + NZSTATUS(PC); + goto [PC]; +} + +# AND Format III +# Operation: Rd <- Rx & Ry >> sa5 +# Syntax: and Rd, Rx, Ry >> sa +# 111x xxx1 1110 yyyy 0000 001t tttt dddd + +:AND erd0, RX9A, RY0A^" >> " shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A; + eop9_7=1 & erd0 & shift4_5 { + erd0 = RX9A & (RY0A >> shift4_5); + NZSTATUS(erd0); +} + +:AND erd0, RX9A, RY0A^" >> " shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A; + eop9_7=1 & erd0 & shift4_5 & erd0=0xf { + PC = RX9A & (RY0A >> shift4_5); + NZSTATUS(PC); + goto [PC]; +} + +#--------------------------------------------------------------------- +# AND{cond4} - Conditional And +# I. cond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al} +# {d,x,y} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# AND{cond4} Format I +# Operation: if(cond4) then +# Rd <- Rx & Ry +# Syntax: and{cond4} Rd, Rx, Ry +# 111x xxx1 1101 yyyy 1110 cccc 0010 dddd + +:AND^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A; + eop12_4=0xe & eop4_4=2 & ECOND_8_4 & erd0) +{ + build ECOND_8_4; + erd0 = RX9A & RY0A; +} + +:AND^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A; + eop12_4=0xe & eop4_4=2 & ECOND_8_4 & erd0 & erd0=0xf) +{ + build ECOND_8_4; + PC = RX9A & RY0A; + goto [PC]; +} + +#--------------------------------------------------------------------- +# ANDH, ANDL - Logical AND into high or low half of register +# I, II, III, IV. d -> {0, 1, ..., 15} +# imm -> {0, 1, ..., 65535} +#--------------------------------------------------------------------- + +# ANDH Format I +# Operation: Rd[31:16] <- Rd[31:16] & imm16 +# Syntax: andh Rd, imm +# 1110 01H0 0001 dddd iiii iiii iiii iiii +# H == 0 + +:ANDH rd0, imm16 is op10_6=0x39 & coh=0 & op4_5=1 & rd0 ; imm16 +{ + value:4 = (imm16 << 16) | 0xffff; + rd0 = rd0 & value; + NZSTATUS(rd0); +} + +:ANDH rd0, imm16 is op10_6=0x39 & coh=0 & op4_5=1 & rd0 & rd0=0xf; imm16 +{ + value:4 = (imm16 << 16) | 0xffff; + PC = inst_start & value; + NZSTATUS(PC); + goto [PC]; +} + +# ANDH Format II +# Operation: Rd[31:16] <- Rd[31:16] & imm16 +# Rd[15:0] <- 0 +# Syntax: andh Rd, imm, COH +# 1110 01H0 0001 dddd iiii iiii iiii iiii +# H == 1 + +:ANDH rd0, imm16^", COH" is op10_6=0x39 & coh=1 & op4_5=1 & rd0 ; imm16 +{ + value:4 = imm16 << 16; + rd0 = rd0 & value; + NZSTATUS(rd0); +} + +:ANDH rd0, imm16^", COH" is op10_6=0x39 & coh=1 & op4_5=1 & rd0 & rd0=0xf; imm16 +{ + value:4 = imm16 << 16; + PC = inst_start & value; + NZSTATUS(PC); + goto [PC]; +} + +# ANDL Format III +# Operation: Rd[15:0] <- Rd[15:0] & imm16 +# Syntax: andl Rd, imm +# 1110 00H0 0001 dddd iiii iiii iiii iiii +# H == 0 + +:ANDL rd0, imm16 is op10_6=0x38 & coh=0 & op4_5=1 & rd0 ; imm16 +{ + value:4 = imm16 | 0xffff0000; + rd0 = rd0 & value; + NZSTATUS(rd0); +} + +:ANDL rd0, imm16 is op10_6=0x38 & coh=0 & op4_5=1 & rd0 & rd0=0xf ; imm16 +{ + value:4 = imm16 | 0xffff0000; + PC = inst_start & value; + NZSTATUS(PC); + goto [PC]; +} + +# ANDL Format IV +# Operation: Rd[15:0] <- Rd[15:0] & imm16 +# Rd[31:16] <- 0 +# Syntax: andl Rd, imm, COH +# 1110 00H0 0001 dddd iiii iiii iiii iiii +# H == 1 + +:ANDL rd0, imm16^", COH" is op10_6=0x38 & coh=1 & op4_5=1 & rd0 ; imm16 +{ + value:4 = imm16; + rd0 = rd0 & value; + NZSTATUS(rd0); +} + +:ANDL rd0, imm16^", COH" is op10_6=0x38 & coh=1 & op4_5=1 & rd0 & rd0=0xf; imm16 +{ + value:4 = imm16; + PC = inst_start & value; + NZSTATUS(PC); +} + +#--------------------------------------------------------------------- +# ANDN - Logical AND NOT +# I. {d, s} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# ANDN Format I +# Operation: Rd <- Rd & Rs +# Syntax: andn Rd, Rs +# 000s sss0 1000 dddd + +:ANDN rd0, RS9A is op13_3=0 & op4_5=8 & rd0 & RS9A { + rd0 = rd0 & ~RS9A; + NZSTATUS(rd0); +} + +:ANDN rd0, RS9A is op13_3=0 & op4_5=8 & rd0 & RS9A & rd0=0xf { + PC = inst_start & ~RS9A; + NZSTATUS(PC); + goto [PC]; +} + +#--------------------------------------------------------------------- +# COM - One's Compliment +# I. d -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# COM Format I +# Operation: Rd <- ~Rd +# Syntax: com Rd +# 0101 1100 1101 dddd + +:COM rd0 is op4_12=0x5cd & rd0 +{ + rd0 = ~rd0; + ZSTATUS(rd0); +} + +#--------------------------------------------------------------------- +# EOR - Logical Exclusive OR with optional logical shift +# I. {d, s} -> {0, 1, ..., 15} +# II, III. {d, x, y} -> {0, 1, ..., 15} +# sa -> {0, 1, ..., 31} +#--------------------------------------------------------------------- + +# EOR Format I +# Operation: Rd <- Rd & Rs +# Syntax: eor Rd, Rs +# 000s sss0 0101 dddd + +:EOR rd0, RS9A is op13_3=0x0 & op4_5=0x5 & rd0 & RS9A { + rd0 = rd0 ^ RS9A; + NZSTATUS(rd0); +} + +:EOR rd0, RS9A is op13_3=0x0 & op4_5=0x5 & rd0 & RS9A & rd0=0xf { + PC = inst_start ^ RS9A; + NZSTATUS(PC); + goto [PC]; +} + +# EOR Format II +# Operation: Rd <- Rx & Ry << sa5 +# Syntax: eor Rd, Rx, Ry << sa +# 111x xxx1 1110 yyyy 0010 000t tttt dddd + +:EOR erd0, RX9A, RY0A^" << " shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A; + eop9_7=0x10 & erd0 & shift4_5 { + erd0 = RX9A ^ (RY0A << shift4_5); + NZSTATUS(erd0); +} + +:EOR erd0, RX9A, RY0A^" << " shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A; + eop9_7=0x10 & erd0 & shift4_5 & erd0=0xf { + PC = RX9A ^ (RY0A << shift4_5); + NZSTATUS(PC); + goto [PC]; +} + +# EOR Format III +# Operation: Rd <- Rx & Ry >> sa5 +# Syntax: eor Rd, Rx, Ry >> sa +# 111x xxx1 1110 yyyy 0010 001t tttt dddd + +:EOR erd0, RX9A, RY0A^" >> " shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A; + eop9_7=0x11 & erd0 & shift4_5 { + erd0 = RX9A ^ (RY0A >> shift4_5); + NZSTATUS(erd0); +} + +:EOR erd0, RX9A, RY0A^" >> " shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A; + eop9_7=0x11 & erd0 & shift4_5 & erd0=0xf { + PC = RX9A ^ (RY0A >> shift4_5); + NZSTATUS(PC); + goto [PC]; +} + +#--------------------------------------------------------------------- +# EOR{cond4} - Conditional Logical EOR +# I. cond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al} +# {d,x,y} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# EOR{cond4} Format I +# Operation: if(cond4) then +# Rd <- Rx ^ Ry +# Syntax: eor{cond4} Rd, Rx, Ry +# 111x xxx1 1101 yyyy 1110 cccc 0100 dddd + +:EOR^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A; + eop12_4=0xe & eop4_4=4 & ECOND_8_4 & erd0) +{ + build ECOND_8_4; + erd0 = RX9A ^ RY0A; +} + +:EOR^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A; + eop12_4=0xe & eop4_4=4 & ECOND_8_4 & erd0 & erd0=0xf) +{ + build ECOND_8_4; + PC = RX9A ^ RY0A; + goto [PC]; +} + +#--------------------------------------------------------------------- +# EORH, EORL - Logical EOR into high or low half of register +# I, II. d -> {0, 1, ..., 15} +# imm -> {0, 1, ..., 65535} +#--------------------------------------------------------------------- + +# EORH Format I +# Operation: Rd[31:16] <- Rd[31:16] & imm16 +# Syntax: eorh Rd, imm +# 1110 1110 0001 dddd iiii iiii iiii iiii + +:EORH rd0, imm16 is op4_12=0xee1 & rd0 ; imm16 +{ + value:4 = imm16 << 16; + rd0 = rd0 ^ value; + NZSTATUS(rd0); +} + +:EORH rd0, imm16 is op4_12=0xee1 & rd0 & rd0=0xf ; imm16 +{ + value:4 = imm16 << 16; + PC = inst_start ^ value; + NZSTATUS(PC); + goto [PC]; +} + +# EORL Format II +# Operation: Rd[15:0] <- Rd[15:0] & imm16 +# Syntax: eorl Rd, imm +# 1110 1100 0001 dddd iiii iiii iiii iiii + +:EORL rd0, imm16 is op4_12=0xec1 & rd0 ; imm16 +{ + value:4 = imm16; + rd0 = rd0 ^ value; + NZSTATUS(rd0); +} + +:EORL rd0, imm16 is op4_12=0xec1 & rd0 & rd0=0xf ; imm16 +{ + value:4 = imm16; + PC = inst_start ^ value; + NZSTATUS(PC); + goto [PC]; +} + +#--------------------------------------------------------------------- +# OR - Logical OR with optional logical shift +# I. {d, s} -> {0, 1, ..., 15} +# II, III. {d, x, y} -> {0, 1, ..., 15} +# sa -> {0, 1, ..., 31} +#--------------------------------------------------------------------- + +# OR Format I +# Operation: Rd <- Rd & Rs +# Syntax: or Rd, Rs +# 000s sss0 0100 dddd + +:OR rd0, RS9A is op13_3=0x0 & op4_5=0x4 & rd0 & RS9A { + rd0 = rd0 | RS9A; + NZSTATUS(rd0); +} + +:OR rd0, RS9A is op13_3=0x0 & op4_5=0x4 & rd0 & RS9A & rd0=0xf { + PC = inst_start | RS9A; + NZSTATUS(PC); + goto [PC]; +} + +# OR Format II +# Operation: Rd <- Rx & Ry << sa5 +# Syntax: or Rd, Rx, Ry << sa +# 111x xxx1 1110 yyyy 0001 000t tttt dddd + +:OR erd0, RX9A, RY0A^" << " shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A; + eop9_7=8 & erd0 & shift4_5 { + erd0 = RX9A | (RY0A << shift4_5); + NZSTATUS(erd0); +} + +:OR erd0, RX9A, RY0A^" << " shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A; + eop9_7=8 & erd0 & shift4_5 & erd0=0xf { + PC = RX9A | (RY0A << shift4_5); + NZSTATUS(PC); + goto [PC]; +} + +# OR Format III +# Operation: Rd <- Rx & Ry >> sa5 +# Syntax: or Rd, Rx, Ry >> sa +# 111x xxx1 1110 yyyy 0001 001t tttt dddd + +:OR erd0, RX9A, RY0A^" >> " shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A; + eop9_7=9 & erd0 & shift4_5 { + erd0 = RX9A | (RY0A >> shift4_5); + NZSTATUS(erd0); +} + +:OR erd0, RX9A, RY0A^" >> " shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A; + eop9_7=9 & erd0 & shift4_5 & erd0=0xf { + PC = RX9A | (RY0A >> shift4_5); + NZSTATUS(PC); + goto [PC]; +} + +#--------------------------------------------------------------------- +# OR{cond4} - Conditional Logical OR +# I. cond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al} +# {d,x,y} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# OR{cond4} Format I +# Operation: if(cond4) then +# Rd <- Rx | Ry +# Syntax: or{cond4} Rd, Rx, Ry +# 111x xxx1 1101 yyyy 1110 cccc 0011 dddd + +:OR^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A; + eop12_4=0xe & eop4_4=3 & ECOND_8_4 & erd0) +{ + build ECOND_8_4; + erd0 = RX9A | RY0A; +} + +:OR^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A; + eop12_4=0xe & eop4_4=3 & ECOND_8_4 & erd0 & erd0=0xf) +{ + build ECOND_8_4; + PC = RX9A | RY0A; + goto [PC]; +} + +#--------------------------------------------------------------------- +# ORH, ORL - Logical OR into high or low half of register +# I, II. d -> {0, 1, ..., 15} +# imm -> {0, 1, ..., 65535} +#--------------------------------------------------------------------- + +# ORH Format I +# Operation: Rd[31:16] <- Rd[31:16] | imm16 +# Syntax: orh Rd, imm +# 1110 1010 0001 dddd iiii iiii iiii iiii + +:ORH rd0, imm16 is op4_12=0xea1 & rd0 ; imm16 +{ + val:4 = (imm16 << 16); + rd0 = rd0 | val; + NZSTATUS(rd0); +} + +:ORH rd0, imm16 is op4_12=0xea1 & rd0 & rd0=0xf ; imm16 +{ + val:4 = (imm16 << 16); + PC = inst_start | val; + NZSTATUS(PC); + goto [PC]; +} + +# ORL Format II +# Operation: Rd[15:0] <- Rd[15:0] | imm16 +# Syntax: orl Rd, imm +# 1110 1000 0001 dddd iiii iiii iiii iiii + +:ORL rd0, imm16 is op4_12=0xe81 & rd0 ; imm16 +{ + val:4 = imm16; + rd0 = rd0 | val; + NZSTATUS(rd0); +} + +:ORL rd0, imm16 is op4_12=0xe81 & rd0 & rd0=0xf; imm16 +{ + val:4 = imm16; + PC = inst_start | val; + NZSTATUS(PC); + goto [PC]; +} + +#--------------------------------------------------------------------- +# TST - Test Register +# I. {d, s} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# TST Format I +# Operation: Rd & Rs +# Syntax: tst Rd, Rs +# 000s sss0 0111 dddd + +:TST RD0A, RS9A is op13_3=0x0 & op4_5=0x7 & RD0A & RS9A { + test:4 = RD0A & RS9A; + NZSTATUS(test); +} diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_multiplication_operations.sinc b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_multiplication_operations.sinc new file mode 100644 index 0000000..3547bc3 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_multiplication_operations.sinc @@ -0,0 +1,189 @@ +#--------------------------------------------------------------------- +# 8.3.3 Multiplication Operations +#--------------------------------------------------------------------- + +#--------------------------------------------------------------------- +# DIVS - Signed Divide +# I. d -> {0, 2, ..., 14) +# {x, y} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# DIVS Format I +# Operation: Rd <- Rx / Ry +# Rd+1 <- Rx % Ry +# Syntax: divs Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 1100 0000 dddd + +:DIVS erd0_low, RX9A, RY0A is op13_3=7 & op4_5=0 & RY0A & RX9A ; + eop4_12=0xc0 & eb0=0 & erd0 & erd0_low & erd0_hi +{ + tmpx:4 = RX9A; + tmpy:4 = RY0A; + erd0_low = tmpx s/ tmpy; + erd0_hi = tmpx s% tmpy; +} + +#--------------------------------------------------------------------- +# DIVU - Unsigned Divide +# I. d -> {0, 2, ..., 14) +# {x, y} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# DIVU Format I +# Operation: Rd <- Rx / Ry +# Rd+1 <- Rx % Ry +# Syntax: divu Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 1101 0000 dddd + +:DIVU erd0_low, RX9A, RY0A is op13_3=7 & op4_5=0 & RY0A & RX9A ; + eop4_12=0xd0 & eb0=0 & erd0 & erd0_low & erd0_hi +{ + tmpx:4 = RX9A; + tmpy:4 = RY0A; + erd0_low = tmpx / tmpy; + erd0_hi = tmpx % tmpy; +} + +#--------------------------------------------------------------------- +# MAC - Multiply Accumulate +# I. {d, x, y} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# MAC Format I +# Operation: Rd <- Rx * Ry + Rd +# Syntax: mac Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 0011 0100 dddd + +:MAC erd0, RX9A, RY0A is op13_3=7 & op4_5=0 & RY0A & RX9A ; + eop4_12=0x34 & erd0 +{ + erd0 = RX9A * RY0A + erd0; +} + +#--------------------------------------------------------------------- +# MACS.D - Multiply Accumulate Signed +# I. d -> {0, 2, ..., 14) +# {x, y} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# MACS.D Format I +# Operation: acc <- (Rd+1:Rd) +# prod <- Rx * Ry +# res <- prod + acc +# (Rd+1:Rd) <- res +# Syntax: macs.d Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 0101 0100 dddd + +:MACS.D erd0_low, RX9A, RY0A is op13_3=7 & op4_5=0 & RY0A & RX9A ; + eop4_12=0x54 & eb0=0 & erd0 & erd0_low & erd0_hi +{ + acc:8 = zext(erd0_low) | zext(erd0_hi << 32); + prod:8 = sext(RX9A) * sext(RY0A); + res:8 = prod + acc; + erd0_low = res:4; + tmp:8 = (res s>> 32); + erd0_hi = tmp:4; +} + +#--------------------------------------------------------------------- +# MACU.D - Multiply Accumulate Unsigned +# I. d -> {0, 2, ..., 14) +# {x, y} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# MACU.D Format I +# Operation: acc <- (Rd+1:Rd) +# prod <- Rx * Ry +# res <- prod + acc +# (Rd+1:Rd) <- res +# Syntax: macu.d Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 0111 0100 dddd + +:MACU.D erd0_low, RX9A, RY0A is op13_3=7 & op4_5=0 & RY0A & RX9A ; + eop4_12=0x74 & eb0=0 & erd0 & erd0_low & erd0_hi +{ + acc:8 = zext(erd0_low) | zext(erd0_hi << 32); + prod:8 = zext(RX9A) * zext(RY0A); + res:8 = prod + acc; + erd0_low = res:4; + tmp:8 = (res >> 32); + erd0_hi = tmp:4; +} + +#--------------------------------------------------------------------- +# MUL - Multiply +# I. {d, s} -> {0, 1, ..., 15} +# II. {d, x, y} -> {0, 1, ..., 15} +# III. {d, s} -> {0, 1, ..., 15} +# imm -> {-128, -127, ..., 127} +#--------------------------------------------------------------------- + +# MUL Format I +# Operation: Rd <- Rd * Rs +# Syntax: mul Rd, Rs +# 101s sss1 0011 dddd + +:MUL rd0, RS9A is op13_3=5 & op4_5=0x13 & rd0 & RS9A +{ + rd0 = rd0 * RS9A; +} + +# MUL Format II +# Operation: Rd <- Rx * Ry +# Syntax: mul Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 0010 0100 dddd + +:MUL erd0, RX9A, RY0A is op13_3=7 & op4_5=0 & RY0A & RX9A ; eop4_12=0x24 & erd0 +{ + erd0 = RX9A * RY0A; +} + +# MUL Format III +# Operation: Rd <- Rs * SE(imm8) +# Syntax: mul Rd, Rs, imm +# 111s sss0 0000 dddd 0001 0000 iiii iiii + +:MUL rd0, RS9A, simm0_8 is op13_3=7 & op4_5=0 & rd0 & RS9A ; eop8_8=0x10 & simm0_8 +{ + rd0 = RS9A * simm0_8; +} + +#--------------------------------------------------------------------- +# MULS.D - Multiply Signed +# I. d -> {0, 2, ..., 14) +# {x, y} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# MULS.D Format I +# Operation: (Rd+1:Rd) <- Rx * Ry +# Syntax: muls.d Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 0100 0100 dddd + +:MULS.D erd0_low, RX9A, RY0A is op13_3=7 & op4_5=0 & RY0A & RX9A ; + eop4_12=0x44 & eb0=0 & erd0 & erd0_low & erd0_hi +{ + prod:8 = sext(RX9A) * sext(RY0A); + erd0_low = prod:4; + tmp:8 = (prod s>> 32); + erd0_hi = tmp:4; +} + +#--------------------------------------------------------------------- +# MULU.D - Multiply Unsigned +# I. d -> {0, 2, ..., 14) +# {x, y} -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# MULU.D Format I +# Operation: (Rd+1:Rd) <- Rx * Ry +# Syntax: mulu.d Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 0110 0100 dddd + +:MULU.D erd0_low, RX9A, RY0A is op13_3=7 & op4_5=0 & RY0A & RX9A ; + eop4_12=0x64 & eb0=0 & erd0 & erd0_low & erd0_hi +{ + prod:8 = zext(RX9A) * zext(RY0A); + erd0_low = prod:4; + tmp:8 = (prod >> 32); + erd0_hi = tmp:4; +} diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_shift_operations.sinc b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_shift_operations.sinc new file mode 100644 index 0000000..68349d2 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_shift_operations.sinc @@ -0,0 +1,176 @@ +#--------------------------------------------------------------------- +# 8.3.7 Shift Operations +#--------------------------------------------------------------------- + +macro do_asr(VAL, SA, DEST) { + tmp:8 = zext(VAL) << 32; + tmp = tmp s>> SA; + DEST = VAL s>> SA; + C = (tmp & 0x0000000080000000) != 0; + NZSTATUS(DEST); + +} + +#--------------------------------------------------------------------- +# ASR - Arithmetic Shift Right +# I. {d, x, y} -> {0, 1, ..., 15} +# II. d -> {0, 1, ..., 15} +# sa -> {0, 1, ..., 31} +# III. {d, s} -> {0, 1, ..., 15} +# sa -> {0, 1, ..., 31} +#--------------------------------------------------------------------- + +# ASR Format I +# Operation: Rd <- ASR(Rx, Ry[4:0]) +# Syntax: asr Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 1000 0100 dddd + +:ASR erd0, RX9A, RY0A is op13_3=7 & op4_5=0 & RY0A & RX9A; + eop4_12=0x084 & erd0 +{ + do_asr(RX9A, RY0A, erd0); +} + +# ASR Format II +# Operation: Rd <- ASR(Rd, sa5) +# Syntax: asr Rd, sa +# 101t ttt1 010t dddd + +:ASR rd0, shift is op13_3=5 & op5_4=0xa & shift9_4 & shift4_1 & rd0 + [ shift = (shift9_4 << 1) | shift4_1; ] +{ + do_asr(rd0, shift, rd0); +} + +# ASR Format III +# Operation: Rd <- ASR(Rs, sa5) +# Syntax: asr Rd, Rs, sa +# 111s sss0 0000 dddd 0001 0100 000t tttt + +:ASR rd0, RS9A, shift0_5 is op13_3=7 & op5_4=0 & RS9A & rd0; + eop5_11=0xa0 & shift0_5 +{ + do_asr(RS9A, shift0_5, rd0); +} + +macro do_lsl(VAL, SA, DEST) { + tmp:8 = zext(VAL); + tmp = tmp << SA; + DEST = tmp:4; + C = (tmp & 0x0000000100000000) != 0; + NZSTATUS(DEST); +} + +#--------------------------------------------------------------------- +# LSL - Logical Shift Left +# I. {d, x, y} -> {0, 1, ..., 15} +# II. d -> {0, 1, ..., 15} +# sa -> {0, 1, ..., 31} +# III. {d, s} -> {0, 1, ..., 15} +# sa -> {0, 1, ..., 31} +#--------------------------------------------------------------------- + +# LSL Format I +# Operation: Rd <- LSL(Rx, Ry[4:0]) +# Syntax: lsl Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 1001 0100 dddd + +:LSL erd0, RX9A, RY0A is op13_3=7 & op4_5=0 & RY0A & RX9A; + eop4_12=0x094 & erd0 +{ + tmp:4 = RY0A & 0x0000001F; + do_lsl(RX9A, tmp, erd0); +} + +# LSL Format II +# Operation: Rd <- LSL(Rd, sa5) +# Syntax: lsl Rd, sa +# 101t ttt1 011t dddd + +:LSL rd0, shift is op13_3=5 & op5_4=0xb & shift9_4 & shift4_1 & rd0 + [ shift = (shift9_4 << 1) | shift4_1; ] +{ + do_lsl(rd0, shift, rd0); +} + +# LSL Format III +# Operation: Rd <- LSL(Rs, sa5) +# Syntax: lsl Rd, Rs, sa +# 111s sss0 0000 dddd 0001 0101 000t tttt + +:LSL rd0, RS9A, shift0_5 is op13_3=7 & op5_4=0 & RS9A & rd0; + eop5_11=0xa8 & shift0_5 +{ + do_lsl(RS9A, shift0_5, rd0); +} + +macro do_lsr(VAL, SA, DEST) { + tmp:8 = zext(VAL) << 32; + tmp = tmp >> SA; + DEST = VAL >> SA; + C = (tmp & 0x0000000080000000) != 0; + NZSTATUS(DEST); +} + +#--------------------------------------------------------------------- +# LSR - Logical Shift Right +# I. {d, x, y} -> {0, 1, ..., 15} +# II. d -> {0, 1, ..., 15} +# sa -> {0, 1, ..., 31} +# III. {d, s} -> {0, 1, ..., 15} +# sa -> {0, 1, ..., 31} +#--------------------------------------------------------------------- + +# LSR Format I +# Operation: Rd <- LSR(Rx, Ry[4:0]) +# Syntax: lsr Rd, Rx, Ry +# 111x xxx0 0000 yyyy 0000 1010 0100 dddd + +:LSR erd0, RX9A, RY0A is op13_3=7 & op4_5=0 & RY0A & RX9A; + eop4_12=0x0a4 & erd0 +{ + tmp:4 = RY0A & 0x0000001F; + do_lsr(RX9A, tmp, erd0); +} + +# LSR Format II +# Operation: Rd <- LSR(Rd, sa5) +# Syntax: lsr Rd, sa +# 101t ttt1 100t dddd + +:LSR rd0, shift is op13_3=5 & op5_4=0xc & shift9_4 & shift4_1 & rd0 + [ shift = (shift9_4 << 1) | shift4_1; ] +{ + do_lsr(rd0, shift, rd0); +} + +# LSR Format III +# Operation: Rd <- LSR(Rs, sa5) +# Syntax: lsr Rd, Rs, sa +# 111s sss0 0000 dddd 0001 0110 000t tttt + +:LSR rd0, RS9A, shift0_5 is op13_3=7 & op5_4=0 & RS9A & rd0; + eop5_11=0xb0 & shift0_5 +{ + do_lsr(RS9A, shift0_5, rd0); +} + +:ROL rd0 is op4_12=0x5cf & rd0 { + tmp:4 = rd0 >> 31; + tmpa:4 = zext(C); + rd0 = rd0 << 1; + rd0 = rd0 | tmpa; + C = tmp:1; + CZNVTOSR(); +} + +:ROR rd0 is op4_12=0x5d0 & rd0 { + tmp:4 = rd0 & 0x1; + tmpa:4 = zext(C); + tmpa = tmpa << 31; + rd0 = rd0 >> 1; + rd0 = rd0 | tmpa; + C = tmp:1; + CZNVTOSR(); +} + diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_simd_operations.sinc b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_simd_operations.sinc new file mode 100644 index 0000000..7faa19a --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_simd_operations.sinc @@ -0,0 +1,833 @@ + +macro satub(RES) { + RES = (zext(RES > 0x00FF) * 0x00FF) + (zext(RES < 0x0100) * RES); +} + +macro satsb(RES) { + RES = (0x007F * zext(RES s> 0x007F)) + (RES * zext(RES s< 0x0080) * zext(RES s>= 0xFF80)) + (0x0080 * zext(RES s< 0xFF80)); +} + +macro satsh(RES) { + RES = (0x00007FFF * zext(RES s> 0x00007FFF)) + (RES * zext(RES s< 0x00008000) * zext(RES s>= 0xFFFF8000)) + (0x00008000 * zext(RES s< 0xFFFF8000)); +} + +macro satuh(RES) { + RES = (0x0000FFFF * zext(RES > 0x0000FFFF)) + (RES * zext(RES < 0x00010000)); +} + +macro sataddub(OP1, OP2, RES) { + RES = zext(OP1) + zext(OP2); + satub(RES); +} + +macro sataddsb(OP1, OP2, RES) { + RES = sext(OP1) + sext(OP2); + satsb(RES); +} + +macro satsubub(OP1, OP2, RES) { + RES = zext(OP1) - zext(OP2); + satub(RES); +} + +macro satsubsb(OP1, OP2, RES) { + RES = sext(OP1) - sext(OP2); + satsb(RES); +} + +macro satadduh(OP1, OP2, RES) { + RES = zext(OP1) + zext(OP2); + satuh(RES); +} + +macro satsubuh(OP1, OP2, RES) { + RES = zext(OP1) - zext(OP2); + satuh(RES); +} + +macro sataddsh(OP1, OP2, RES) { + RES = sext(OP1) + sext(OP2); + satsh(RES); +} + +macro satsubsh(OP1, OP2, RES) { + RES = sext(OP1) - sext(OP2); + satsh(RES); +} + +PXPART: ":T" is ctx_usex & xpart=0x1 { + tmp:4 = ctx_usex; + tmp = tmp >> 16; + export *[const]:2 tmp; +} + +PXPART: ":B" is ctx_usex & xpart=0x0 { + tmp:4 = ctx_usex; + tmp = tmp & 0x0000FFFF; + export *[const]:2 tmp; +} + +PYPART: ":T" is ctx_usey & ypart=0x1 { + tmp:4 = ctx_usey; + tmp = tmp >> 16; + export *[const]:2 tmp; +} + +PYPART: ":B" is ctx_usey & ypart=0x0 { + tmp:4 = ctx_usey; + tmp = tmp & 0x0000FFFF; + export *[const]:2 tmp; +} + +PUPART: ":T" is ctx_useu & upart=0x1 { + tmp:4 = ctx_useu; + tmp = tmp >> 16; + export *[const]:2 tmp; +} + +PUPART: ":B" is ctx_useu & upart=0x0 { + tmp:4 = ctx_useu; + tmp = tmp & 0x0000FFFF; + export *[const]:2 tmp; +} + + +:PABS.SB erd0, rs0 is op4_12=0xe00 & rs0 ; eop4_12=0x23e & erd0 { + tmps:1 = rs0[24,8]; + erd0[24,8] = abs(tmps); + + tmps = rs0[16,8]; + erd0[16,8] = abs(tmps); + + tmps = rs0[8,8]; + erd0[8,8] = abs(tmps); + + tmps = rs0[0,8]; + erd0[0,8] = abs(tmps); +} + +:PABS.SH erd0, rs0 is op4_12=0xe00 & rs0 ; eop4_12=0x23f & erd0 { + tmps:2 = rs0[16,16]; + erd0[16,16] = abs(tmps); + + tmps = rs0[0,16]; + erd0[0,16] = abs(tmps); +} + +:PACKSH.UB erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x24c & erd0 { + tmp:2 = rx9[16,16]; + satub(tmp); + erd0[24,8] = tmp:1; + tmp = rx9[0,16]; + satub(tmp); + erd0[16,8] = tmp:1; + tmp = ry0[16,16]; + satub(tmp); + erd0[8,8] = tmp:1; + tmp = ry0[0,16]; + satub(tmp); + erd0[0,8] = tmp:1; +} + +:PACKSH.SB erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x24d & erd0 { + tmp:2 = rx9[16,16]; + satsb(tmp); + erd0[24,8] = tmp:1; + tmp = rx9[0,16]; + satsb(tmp); + erd0[16,8] = tmp:1; + tmp = ry0[16,16]; + satsb(tmp); + erd0[8,8] = tmp:1; + tmp = ry0[0,16]; + satsb(tmp); + erd0[0,8] = tmp:1; +} + +:PACKW.SH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x247 & erd0 { + tmp:4 = rx9; + satsh(tmp); + erd0[16,16] = tmp:2; + tmp = ry0; + satsh(tmp); + erd0[0,16] = tmp:2; +} + +:PADD.B erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x230 & erd0 { + tmpx:1 = rx9[24,8]; + tmpy:1 = ry0[24,8]; + tmpd:1 = tmpx + tmpy; + erd0[24,8] = tmpd; + + tmpx = rx9[16,8]; + tmpy = ry0[16,8]; + tmpd = tmpx + tmpy; + erd0[16,8] = tmpd; + + tmpx = rx9[8,8]; + tmpy = ry0[8,8]; + tmpd = tmpx + tmpy; + erd0[8,8] = tmpd; + + tmpx = rx9[0,8]; + tmpy = ry0[0,8]; + tmpd = tmpx + tmpy; + erd0[0,8] = tmpd; + +} + +:PADD.H erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x200 & erd0 { + tmpx:2 = rx9[16,16]; + tmpy:2 = ry0[16,16]; + tmpd:2 = tmpx + tmpy; + erd0[16,16] = tmpd; + + tmpx = rx9[0,16]; + tmpy = ry0[0,16]; + tmpd = tmpx + tmpy; + erd0[0,16] = tmpd; +} + +:PADDH.UB erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x236 & erd0 { + tmpx:2 = zext(rx9[24,8]); + tmpy:2 = zext(ry0[24,8]); + tmpd:2 = tmpx + tmpy; + tmpd = tmpd >> 1; + erd0[24,8] = tmpd:1; + + tmpx = zext(rx9[16,8]); + tmpy = zext(ry0[16,8]); + tmpd = tmpx + tmpy; + tmpd = tmpd >> 1; + erd0[16,8] = tmpd:1; + + tmpx = zext(rx9[8,8]); + tmpy = zext(ry0[8,8]); + tmpd = tmpx + tmpy; + tmpd = tmpd >> 1; + erd0[8,8] = tmpd:1; + + tmpx = zext(rx9[0,8]); + tmpy = zext(ry0[0,8]); + tmpd = tmpx + tmpy; + tmpd = tmpd >> 1; + erd0[0,8] = tmpd:1; +} + +:PADDH.SH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x20c & erd0 { + tmpx:4 = sext(rx9[16,16]); + tmpy:4 = sext(ry0[16,16]); + tmpd:4 = tmpx + tmpy; + tmpd = tmpd s>> 1; + erd0[16,16] = tmpd:2; + + tmpx = sext(rx9[0,16]); + tmpy = sext(ry0[0,16]); + tmpd = tmpx + tmpy; + tmpd = tmpd s>> 1; + erd0[0,16] = tmpd:2; +} + +:PADDS.UB erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x234 & erd0 { + tmpx:1 = rx9[24,8]; + tmpy:1 = ry0[24,8]; + tmpd:2 = 0; + sataddub(tmpx,tmpy,tmpd); + erd0[24,8] = tmpd:1; + + tmpx = rx9[16,8]; + tmpy = ry0[16,8]; + sataddub(tmpx,tmpy,tmpd); + erd0[16,8] = tmpd:1; + + tmpx = rx9[8,8]; + tmpy = ry0[8,8]; + sataddub(tmpx,tmpy,tmpd); + erd0[8,8] = tmpd:1; + + tmpx = rx9[0,8]; + tmpy = ry0[0,8]; + sataddub(tmpx,tmpy,tmpd); + erd0[0,8] = tmpd:1; + +} + +:PADDS.SB erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x232 & erd0 { + tmpx:1 = rx9[24,8]; + tmpy:1 = ry0[24,8]; + tmpd:2 = 0; + sataddsb(tmpx,tmpy,tmpd); + erd0[24,8] = tmpd:1; + + tmpx = rx9[16,8]; + tmpy = ry0[16,8]; + sataddsb(tmpx,tmpy,tmpd); + erd0[16,8] = tmpd:1; + + tmpx = rx9[8,8]; + tmpy = ry0[8,8]; + sataddsb(tmpx,tmpy,tmpd); + erd0[8,8] = tmpd:1; + + tmpx = rx9[0,8]; + tmpy = ry0[0,8]; + sataddsb(tmpx,tmpy,tmpd); + erd0[0,8] = tmpd:1; + +} + +:PADDS.UH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x208 & erd0 { + tmpx:2 = rx9[16,16]; + tmpy:2 = ry0[16,16]; + tmpd:4 = 0; + satadduh(tmpx,tmpy,tmpd); + erd0[16,16] = tmpd:2; + + tmpx = rx9[0,16]; + tmpy = ry0[0,16]; + satadduh(tmpx,tmpy,tmpd); + erd0[0,16] = tmpd:2; +} + +:PADDS.SH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x204 & erd0 { + tmpx:2 = rx9[16,16]; + tmpy:2 = ry0[16,16]; + tmpd:4 = 0; + sataddsh(tmpx,tmpy,tmpd); + erd0[16,16] = tmpd:2; + + tmpx = rx9[0,16]; + tmpy = ry0[0,16]; + sataddsh(tmpx,tmpy,tmpd); + erd0[0,16] = tmpd:2; +} + +:PADDSUB.H erd0, rx9^PXPART, ry0^PYPART is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop6_10=0x84 & PXPART & PYPART & erd0 [ctx_savex=rx9; ctx_savey=ry0; ] { + tmp:2 = PXPART + PYPART; + erd0[16,16] = tmp; + tmp = PXPART - PYPART; + erd0[0,16] = tmp; +} + +:PADDSUBH.SH erd0, rx9^PXPART, ry0^PYPART is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop6_10=0x8a & PXPART & PYPART & erd0 [ctx_savex=rx9; ctx_savey=ry0; ] { + tmp:4 = sext(PXPART) + sext(PYPART); + tmp = tmp s>> 1; + erd0[16,16] = tmp:2; + tmp = sext(PXPART) - sext(PYPART); + tmp = tmp s>> 1; + erd0[0,16] = tmp:2; +} + +:PADDX.H erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x202 & erd0 { + tmpx:2 = rx9[16,16]; + tmpy:2 = ry0[0,16]; + tmpd:2 = tmpx + tmpy; + erd0[16,16] = tmpd; + + tmpx = rx9[0,16]; + tmpy = ry0[16,16]; + tmpd = tmpx + tmpy; + erd0[0,16] = tmpd; +} + +:PADDXH.SH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x20e & erd0 { + tmpx:4 = sext(rx9[16,16]); + tmpy:4 = sext(ry0[0,16]); + tmpd:4 = tmpx + tmpy; + tmpd = tmpd s>> 1; + erd0[16,16] = tmpd:2; + + tmpx = sext(rx9[0,16]); + tmpy = sext(ry0[16,16]); + tmpd = tmpx + tmpy; + tmpd = tmpd s>> 1; + erd0[0,16] = tmpd:2; +} + +:PASR.B erd0, rs9, sa0_3 is op13_3=0x7 & rs9 & op3_6=0x0 & sa0_3 ; eop4_12=0x241 & erd0 { + tmp:1 = rs9[24,8]; + tmp = tmp s>> sa0_3; + erd0[24,8] = tmp; + tmp = rs9[16,8]; + tmp = tmp s>> sa0_3; + erd0[16,8] = tmp; + tmp = rs9[8,8]; + tmp = tmp s>> sa0_3; + erd0[8,8] = tmp; + tmp = rs9[0,8]; + tmp = tmp s>> sa0_3; + erd0[0,8] = tmp; +} + +:PASR.H erd0, rs9, sa0_4 is op13_3=0x7 & rs9 & op4_5=0x0 & sa0_4 ; eop4_12=0x244 & erd0 { + tmp:2 = rs9[16,16]; + tmp = tmp s>> sa0_4; + erd0[16,16] = tmp; + tmp = rs9[0,16]; + tmp = tmp s>> sa0_4; + erd0[0,16] = tmp; +} + +:PAVG.UB erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x23c & erd0 { + tmpx:1 = rx9[24,8]; + tmpy:1 = ry0[24,8]; + tmpd:2 = (zext(tmpx) + zext(tmpy) + 1) >> 1; + erd0[24,8] = tmpd:1; + + tmpx = rx9[16,8]; + tmpy = ry0[16,8]; + tmpd = (zext(tmpx) + zext(tmpy) + 1) >> 1; + erd0[16,8] = tmpd:1; + + tmpx = rx9[8,8]; + tmpy = ry0[8,8]; + tmpd = (zext(tmpx) + zext(tmpy) + 1) >> 1; + erd0[8,8] = tmpd:1; + + tmpx = rx9[0,8]; + tmpy = ry0[0,8]; + tmpd = (zext(tmpx) + zext(tmpy) + 1) >> 1; + erd0[0,8] = tmpd:1; +} + +:PAVG.SH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x23d & erd0 { + tmpx:2 = rx9[16,16]; + tmpy:2 = ry0[16,16]; + tmpd:4 = (sext(tmpx) + sext(tmpy) + 1) s>> 1; + erd0[16,16] = tmpd:2; + + tmpx = rx9[0,16]; + tmpy = ry0[0,16]; + tmpd = (sext(tmpx) + sext(tmpy) + 1) s>> 1; + erd0[0,16] = tmpd:2; +} + +:PLSL.B erd0, rs9, sa0_3 is op13_3=0x7 & rs9 & op3_6=0x0 & sa0_3 ; eop4_12=0x242 & erd0 { + tmp:1 = rs9[24,8]; + tmp = tmp << sa0_3; + erd0[24,8] = tmp; + tmp = rs9[16,8]; + tmp = tmp << sa0_3; + erd0[16,8] = tmp; + tmp = rs9[8,8]; + tmp = tmp << sa0_3; + erd0[8,8] = tmp; + tmp = rs9[0,8]; + tmp = tmp << sa0_3; + erd0[0,8] = tmp; +} + +:PLSL.H erd0, rs9, sa0_4 is op13_3=0x7 & rs9 & op4_5=0x0 & sa0_4 ; eop4_12=0x245 & erd0 { + tmp:2 = rs9[16,16]; + tmp = tmp << sa0_4; + erd0[16,16] = tmp; + tmp = rs9[0,16]; + tmp = tmp << sa0_4; + erd0[0,16] = tmp; +} + +:PLSR.B erd0, rs9, sa0_3 is op13_3=0x7 & rs9 & op3_6=0x0 & sa0_3 ; eop4_12=0x243 & erd0 { + tmp:1 = rs9[24,8]; + tmp = tmp >> sa0_3; + erd0[24,8] = tmp; + tmp = rs9[16,8]; + tmp = tmp >> sa0_3; + erd0[16,8] = tmp; + tmp = rs9[8,8]; + tmp = tmp >> sa0_3; + erd0[8,8] = tmp; + tmp = rs9[0,8]; + tmp = tmp >> sa0_3; + erd0[0,8] = tmp; +} + +:PLSR.H erd0, rs9, sa0_4 is op13_3=0x7 & rs9 & op4_5=0x0 & sa0_4 ; eop4_12=0x246 & erd0 { + tmp:2 = rs9[16,16]; + tmp = tmp >> sa0_4; + erd0[16,16] = tmp; + tmp = rs9[0,16]; + tmp = tmp >> sa0_4; + erd0[0,16] = tmp; +} + +:PMAX.UB erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x238 & erd0 { + tmpx:1 = rx9[24,8]; + tmpy:1 = ry0[24,8]; + tmpd:1 = (tmpx * zext(tmpx > tmpy)) + (tmpy * zext(tmpy <= tmpx)); + erd0[24,8] = tmpd; + tmpx = rx9[16,8]; + tmpy = ry0[16,8]; + tmpd = (tmpx * zext(tmpx > tmpy)) + (tmpy * zext(tmpy <= tmpx)); + erd0[16,8] = tmpd; + tmpx = rx9[8,8]; + tmpy = ry0[8,8]; + tmpd = (tmpx * zext(tmpx > tmpy)) + (tmpy * zext(tmpy <= tmpx)); + erd0[8,8] = tmpd; + tmpx = rx9[0,8]; + tmpy = ry0[0,8]; + tmpd = (tmpx * zext(tmpx > tmpy)) + (tmpy * zext(tmpy <= tmpx)); + erd0[0,8] = tmpd; +} + +:PMAX.SH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x239 & erd0 { + tmpx:2 = rx9[16,16]; + tmpy:2 = ry0[16,16]; + tmpd:2 = (tmpx * zext(tmpx > tmpy)) + (tmpy * zext(tmpy <= tmpx)); + erd0[16,16] = tmpd; + tmpx = rx9[0,16]; + tmpy = ry0[0,16]; + tmpd = (tmpx * zext(tmpx > tmpy)) + (tmpy * zext(tmpy <= tmpx)); + erd0[0,16] = tmpd; +} + +:PMIN.UB erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x23a & erd0 { + tmpx:1 = rx9[24,8]; + tmpy:1 = ry0[24,8]; + tmpd:1 = (tmpx * zext(tmpx < tmpy)) + (tmpy * zext(tmpy >= tmpx)); + erd0[24,8] = tmpd; + tmpx = rx9[16,8]; + tmpy = ry0[16,8]; + tmpd = (tmpx * zext(tmpx < tmpy)) + (tmpy * zext(tmpy >= tmpx)); + erd0[16,8] = tmpd; + tmpx = rx9[8,8]; + tmpy = ry0[8,8]; + tmpd = (tmpx * zext(tmpx < tmpy)) + (tmpy * zext(tmpy >= tmpx)); + erd0[8,8] = tmpd; + tmpx = rx9[0,8]; + tmpy = ry0[0,8]; + tmpd = (tmpx * zext(tmpx < tmpy)) + (tmpy * zext(tmpy >= tmpx)); + erd0[0,8] = tmpd; +} + +:PMIN.SH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x23b & erd0 { + tmpx:2 = rx9[16,16]; + tmpy:2 = ry0[16,16]; + tmpd:2 = (tmpx * zext(tmpx < tmpy)) + (tmpy * zext(tmpy >= tmpx)); + erd0[16,16] = tmpd; + tmpx = rx9[0,16]; + tmpy = ry0[0,16]; + tmpd = (tmpx * zext(tmpx < tmpy)) + (tmpy * zext(tmpy >= tmpx)); + erd0[0,16] = tmpd; +} + +:PADDSUBS.UH erd0, rx9^PXPART, ry0^PYPART is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop6_10=0x88 & PXPART & PYPART & erd0 { + tmpx:2 = PXPART; + tmpy:2 = PYPART; + tmpd:4 = 0; + satadduh(tmpx,tmpy,tmpd); + erd0[16,16] = tmpd:2; + satsubuh(tmpx,tmpy,tmpd); + erd0[0,16] = tmpd:2; +} + +:PADDSUBS.SH erd0, rx9^PXPART, ry0^PYPART is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop6_10=0x86 & PXPART & PYPART & erd0 { + tmpx:2 = PXPART; + tmpy:2 = PYPART; + tmpd:4 = 0; + sataddsh(tmpx,tmpy,tmpd); + erd0[16,16] = tmpd:2; + satsubsh(tmpx,tmpy,tmpd); + erd0[0,16] = tmpd:2; +} + +:PADDXS.UH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x20a & erd0 { + tmpx:2 = rx9[16,16]; + tmpy:2 = ry0[0,16]; + tmpd:4 = 0; + satadduh(tmpx,tmpy,tmpd); + erd0[16,16] = tmpd:2; + + tmpx = rx9[0,16]; + tmpy = ry0[16,16]; + satadduh(tmpx,tmpy,tmpd); + erd0[0,16] = tmpd:2; +} + +:PADDXS.SH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x206 & erd0 { + tmpx:2 = rx9[16,16]; + tmpy:2 = ry0[0,16]; + tmpd:4 = 0; + sataddsh(tmpx,tmpy,tmpd); + erd0[16,16] = tmpd:2; + + tmpx = rx9[0,16]; + tmpy = ry0[16,16]; + sataddsh(tmpx,tmpy,tmpd); + erd0[0,16] = tmpd:2; +} + +:PSAD erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x240 & erd0 { + tmpx:1 = rx9[24,8]; + tmpy:1 = ry0[24,8]; + tmpd:1 = abs(tmpx - tmpy); + erd0 = zext(tmpd); + + tmpx = rx9[16,8]; + tmpy = ry0[16,8]; + tmpd = abs(tmpx - tmpy); + erd0 = erd0 + zext(tmpd); + + tmpx = rx9[8,8]; + tmpy = ry0[8,8]; + tmpd = abs(tmpx - tmpy); + erd0 = erd0 + zext(tmpd); + + tmpx = rx9[0,8]; + tmpy = ry0[0,8]; + tmpd = abs(tmpx - tmpy); + erd0 = erd0 + zext(tmpd); +} + +:PSUB.B erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x231 & erd0 { + tmpx:1 = rx9[24,8]; + tmpy:1 = ry0[24,8]; + tmpd:1 = tmpx - tmpy; + erd0[24,8] = tmpd; + + tmpx = rx9[16,8]; + tmpy = ry0[16,8]; + tmpd = tmpx - tmpy; + erd0[16,8] = tmpd; + + tmpx = rx9[8,8]; + tmpy = ry0[8,8]; + tmpd = tmpx - tmpy; + erd0[8,8] = tmpd; + + tmpx = rx9[0,8]; + tmpy = ry0[0,8]; + tmpd = tmpx - tmpy; + erd0[0,8] = tmpd; +} + +:PSUB.H erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x201 & erd0 { + tmpx:2 = rx9[16,16]; + tmpy:2 = ry0[16,16]; + tmpd:2 = tmpx - tmpy; + erd0[16,16] = tmpd; + + tmpx = rx9[0,16]; + tmpy = ry0[0,16]; + tmpd = tmpx - tmpy; + erd0[0,16] = tmpd; +} + +:PSUBADD.H erd0, rx9^PXPART, ry0^PYPART is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop6_10=0x85 & PXPART & PYPART & erd0 [ctx_savex=rx9; ctx_savey=ry0; ] { + tmp:2 = PXPART - PYPART; + erd0[16,16] = tmp; + tmp = PXPART + PYPART; + erd0[0,16] = tmp; +} + +:PSUBADDH.SH erd0, rx9^PXPART, ry0^PYPART is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop6_10=0x8b & PXPART & PYPART & erd0 [ctx_savex=rx9; ctx_savey=ry0; ] { + tmp:4 = sext(PXPART) - sext(PYPART); + tmp = tmp s>> 1; + erd0[16,16] = tmp:2; + tmp = sext(PXPART) + sext(PYPART); + tmp = tmp s>> 1; + erd0[0,16] = tmp:2; +} + +:PSUBADDS.UH erd0, rx9^PXPART, ry0^PYPART is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop6_10=0x89 & PXPART & PYPART & erd0 { + tmpx:2 = PXPART; + tmpy:2 = PYPART; + tmpd:4 = 0; + satsubuh(tmpx,tmpy,tmpd); + erd0[16,16] = tmpd:2; + satadduh(tmpx,tmpy,tmpd); + erd0[0,16] = tmpd:2; +} + +:PSUBADDS.SH erd0, rx9^PXPART, ry0^PYPART is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop6_10=0x87 & PXPART & PYPART & erd0 { + tmpx:2 = PXPART; + tmpy:2 = PYPART; + tmpd:4 = 0; + satsubsh(tmpx,tmpy,tmpd); + erd0[16,16] = tmpd:2; + sataddsh(tmpx,tmpy,tmpd); + erd0[0,16] = tmpd:2; +} + +:PSUBH.UB erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x237 & erd0 { + tmpx:2 = zext(rx9[24,8]); + tmpy:2 = zext(ry0[24,8]); + tmpd:2 = tmpx - tmpy; + tmpd = tmpd >> 1; + erd0[24,8] = tmpd:1; + + tmpx = zext(rx9[16,8]); + tmpy = zext(ry0[16,8]); + tmpd = tmpx - tmpy; + tmpd = tmpd >> 1; + erd0[16,8] = tmpd:1; + + tmpx = zext(rx9[8,8]); + tmpy = zext(ry0[8,8]); + tmpd = tmpx - tmpy; + tmpd = tmpd >> 1; + erd0[8,8] = tmpd:1; + + tmpx = zext(rx9[0,8]); + tmpy = zext(ry0[0,8]); + tmpd = tmpx - tmpy; + tmpd = tmpd >> 1; + erd0[0,8] = tmpd:1; +} + +:PSUBH.SH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x20d & erd0 { + tmpx:4 = sext(rx9[16,16]); + tmpy:4 = sext(ry0[16,16]); + tmpd:4 = tmpx - tmpy; + tmpd = tmpd s>> 1; + erd0[16,16] = tmpd:2; + + tmpx = sext(rx9[0,16]); + tmpy = sext(ry0[0,16]); + tmpd = tmpx - tmpy; + tmpd = tmpd s>> 1; + erd0[0,16] = tmpd:2; +} + +:PSUBS.UB erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x235 & erd0 { + tmpx:1 = rx9[24,8]; + tmpy:1 = ry0[24,8]; + tmpd:2 = 0; + satsubub(tmpx,tmpy,tmpd); + erd0[24,8] = tmpd:1; + + tmpx = rx9[16,8]; + tmpy = ry0[16,8]; + satsubub(tmpx,tmpy,tmpd); + erd0[16,8] = tmpd:1; + + tmpx = rx9[8,8]; + tmpy = ry0[8,8]; + satsubub(tmpx,tmpy,tmpd); + erd0[8,8] = tmpd:1; + + tmpx = rx9[0,8]; + tmpy = ry0[0,8]; + satsubub(tmpx,tmpy,tmpd); + erd0[0,8] = tmpd:1; +} + +:PSUBS.SB erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x233 & erd0 { + tmpx:1 = rx9[24,8]; + tmpy:1 = ry0[24,8]; + tmpd:2 = 0; + satsubsb(tmpx,tmpy,tmpd); + erd0[24,8] = tmpd:1; + + tmpx = rx9[16,8]; + tmpy = ry0[16,8]; + satsubsb(tmpx,tmpy,tmpd); + erd0[16,8] = tmpd:1; + + tmpx = rx9[8,8]; + tmpy = ry0[8,8]; + satsubsb(tmpx,tmpy,tmpd); + erd0[8,8] = tmpd:1; + + tmpx = rx9[0,8]; + tmpy = ry0[0,8]; + satsubsb(tmpx,tmpy,tmpd); + erd0[0,8] = tmpd:1; +} + +:PSUBS.UH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x209 & erd0 { + tmpx:2 = rx9[16,16]; + tmpy:2 = ry0[16,16]; + tmpd:4 = 0; + satsubuh(tmpx,tmpy,tmpd); + erd0[16,16] = tmpd:2; + + tmpx = rx9[0,16]; + tmpy = ry0[0,16]; + satsubuh(tmpx,tmpy,tmpd); + erd0[0,16] = tmpd:2; +} + +:PSUBS.SH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x205 & erd0 { + tmpx:2 = rx9[16,16]; + tmpy:2 = ry0[16,16]; + tmpd:4 = 0; + satsubsh(tmpx,tmpy,tmpd); + erd0[16,16] = tmpd:2; + + tmpx = rx9[0,16]; + tmpy = ry0[0,16]; + satsubsh(tmpx,tmpy,tmpd); + erd0[0,16] = tmpd:2; +} + +:PSUBX.H erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x203 & erd0 { + tmpx:2 = rx9[16,16]; + tmpy:2 = ry0[0,16]; + tmpd:2 = tmpx - tmpy; + erd0[16,16] = tmpd; + + tmpx = rx9[0,16]; + tmpy = ry0[16,16]; + tmpd = tmpx - tmpy; + erd0[0,16] = tmpd; +} + +:PSUBXH.SH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x20f & erd0 { + tmpx:4 = sext(rx9[16,16]); + tmpy:4 = sext(ry0[0,16]); + tmpd:4 = tmpx - tmpy; + tmpd = tmpd s>> 1; + erd0[16,16] = tmpd:2; + + tmpx = sext(rx9[0,16]); + tmpy = sext(ry0[16,16]); + tmpd = tmpx - tmpy; + tmpd = tmpd s>> 1; + erd0[0,16] = tmpd:2; +} + +:PSUBXS.UH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x20b & erd0 { + tmpx:2 = rx9[16,16]; + tmpy:2 = ry0[0,16]; + tmpd:4 = 0; + satsubuh(tmpx,tmpy,tmpd); + erd0[16,16] = tmpd:2; + + tmpx = rx9[0,16]; + tmpy = ry0[16,16]; + satsubuh(tmpx,tmpy,tmpd); + erd0[0,16] = tmpd:2; +} + +:PSUBXS.SH erd0, rx9, ry0 is op13_3=0x7 & rx9 & op4_5=0x0 & ry0 ; eop4_12=0x207 & erd0 { + tmpx:2 = rx9[16,16]; + tmpy:2 = ry0[0,16]; + tmpd:4 = 0; + satsubsh(tmpx,tmpy,tmpd); + erd0[16,16] = tmpd:2; + + tmpx = rx9[0,16]; + tmpy = ry0[16,16]; + satsubsh(tmpx,tmpy,tmpd); + erd0[0,16] = tmpd:2; +} + +:PUNPCKUB.H erd0, rs9^PUPART is op13_3=0x7 & rs9 & op0_9=0x0 ; eop5_11=0x124 & PUPART & erd0 { + tmp:2 = PUPART; + tmph:1 = tmp[8,8]; + tmpl:1 = tmp[0,8]; + tmp = zext(tmph); + erd0[16,16] = tmp; + tmp = zext(tmpl); + erd0[0,16] = tmp; +} + +:PUNPCKSB.H erd0, rs9^PUPART is op13_3=0x7 & rs9 & op0_9=0x0 ; eop5_11=0x125 & PUPART & erd0 { + tmp:2 = PUPART; + tmph:1 = tmp[8,8]; + tmpl:1 = tmp[0,8]; + tmp = sext(tmph); + erd0[16,16] = tmp; + tmp = sext(tmpl); + erd0[0,16] = tmp; +} diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_system_control.sinc b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_system_control.sinc new file mode 100644 index 0000000..ce343d9 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a_system_control.sinc @@ -0,0 +1,111 @@ +#--------------------------------------------------------------------- +# 8.3.10 System/Control +#--------------------------------------------------------------------- + +#--------------------------------------------------------------------- +# SR{cond} - Set Register Conditionally +# I. cond4 -> {eq,ne,hs,lo,ge,lt,mi,pl,ls,gt,le,hi,vs,vc,qs,al} +# d -> {0, 1, ..., 15} +#--------------------------------------------------------------------- + +# SR{cond} Format I +# Operation: if (cond4) Rd <- 1; else Rd <- 0; +# Syntax: SR{cond4} Rd +# 0101 1111 cccc dddd + +:SR^{COND_4_4} rd0 is op8_8=0x5f & rd0 & COND_4_4 { + rd0 = 0; + build COND_4_4; + rd0 = 1; +} + +:BREAKPOINT is op0_16=0xd673 { + trap(); +} + +:CACHE rd0[disp0_11],eop11_5 is op4_12=0xF41 & rd0 ; disp0_11 & eop11_5 { + tmpa:4 = disp0_11; + tmpb:4 = eop11_5; + cacheOp(rd0,tmpa,tmpb); +} + +:CSRF imm4_5 is op9_7=0x6a & op0_4=0x3 & imm4_5 { + tmp:4 = 1 << imm4_5; + SR = SR & ~tmp; + SRTOFLAGS(); +} + +:CSRFCZ imm4_5 is op9_7=0x68 & imm4_5 & op0_4=0x3 { + tmp:1 = ((SR >> imm4_5) & 0x1) != 0; + C = tmp; + Z = tmp; + CZTOSR(); +} + +:FRS is op0_16=0xd743 { } + +:MFSR rd0,sysreg is op4_12=0xE1B & rd0 ; eop8_8=0 & sysreg { + rd0 = sysreg; +} + +:MTSR sysreg,rs0 is op4_12=0xE3B & rs0 ; eop8_8=0 & sysreg { + sysreg = rs0; +} + +:MFDR rd0, dbgreg is op4_12=0xe5b & rd0 ; eop8_8=0x0 & dbgreg { + tmp:1 = dbgreg; + MoveFromDebugReg(rd0,tmp); +} + +:MTDR dbgreg, rs0 is op4_12=0xe7b & rs0 ; eop8_8=0x0 & dbgreg { + tmp:1 = dbgreg; + MoveToDebugReg(rs0,tmp); +} + +:MUSFR rs0 is op4_12=0x5d3 & rs0 { + SR = (SR & 0xFFFFFFF0) | (rs0 & 0xF); + SRTOLOWFLAGS(); +} + +:MUSTR rd0 is op4_12=0x5d2 & rd0 { + rd0 = SR & 0xF; +} + +:NOP is op0_16=0xD703 {} +# I found gcc assembler will also use an add r0,r0 for a nop which is an all 0 opcode +:NOP is op0_16=0 {} + +:PREF rp0[disp_16] is op4_12=0xf21 & rp0 ; disp_16 { + tmpa:2 = disp_16; + tmp:4 = rp0 + sext(tmpa); + CacheFetch(tmp); +} + +SLGM: val is disp_8 [ val = disp_8 << 0; ] { export *[const]:1 val; } +SLGM: val is eb7=1 & disp_8 [ val = disp_8 << 0; ] { GM = 0; export *[const]:1 val; } +:SLEEP SLGM is op0_16=0xe9b0 ; eop8_8=0x0 & SLGM { + doSleep(SLGM); +} + +:SSRF imm4_5 is op9_7=0x69 & op0_4=0x3 & imm4_5 { + tmp:4 = 1 << imm4_5; + SR = SR | tmp; + SRTOFLAGS(); +} + +:SYNC eop0_8 is op0_16=0xebb0 ; eop8_8=0x0 & eop0_8 { + tmp:1 = eop0_8; + SynchMemory(tmp); +} + +:TLBR is op0_16=0xd643 { + ReadTLBEntry(); +} + +:TLBS is op0_16=0xd653 { + SearchTLBEntry(); +} + +:TLBW is op0_16=0xd663 { + WriteTLBEntry(); +} diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8.ldefs b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8.ldefs new file mode 100644 index 0000000..35a6be1 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8.ldefs @@ -0,0 +1,67 @@ + + + + + + AVR8 with 16-bit word addressable code space + + + + + + + + + AVR8 with 22-bit word addressable with EIND code space + + + + + + AVR8 for an Atmega 256 + + + + + + + + AVR8 for an Xmega + + + + + + diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8.opinion b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8.opinion new file mode 100644 index 0000000..0541e25 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8.opinion @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8.pspec b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8.pspec new file mode 100644 index 0000000..2903e03 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8.pspec @@ -0,0 +1,175 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8.sinc b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8.sinc new file mode 100644 index 0000000..581edc4 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8.sinc @@ -0,0 +1,1193 @@ +# sleigh specification for the avr8 +# +# Currently designed for ATMega64 in non-ATmel103 configuration +# - 0x20-0xff as IO memory, rather than 0x20-0x5f +# +# This is a ATMega64 with a 64k sized memory +# Other parts available have a 4M sized memory so that stack +# pointer would be three bytes instead + +define endian=little; + +# Declaring space to be word-sized... alternative is to do byte sized +define alignment=2; + +# Force fusion of two byte operations in a row by decoding as words +#@define FUSION "" +#define where the IO space is mapped if not specified +@ifndef IO_START +@define IO_START "0x20" +@define EIND "0x5c" +@endif + +#define where the registers are located if not specified +@ifndef REGISTER_SPACE +@define REGISTER_SPACE "mem" +@endif + +# mem space should really be the default, but the loading scripts will +# prefer the code space as the default. By being explicit for every +# instruction, we can eliminate the ambiguity for at least the +# decompiler. None-the-less, other than when loading the binary into +# Ghidra, it's still preferable to see the name of IO locations used, +# rather than code addresses, so leave mem space as the default. + +define space code type=ram_space size=$(PCBYTESIZE) wordsize=2 default; +define space register type=register_space size=2; +define space mem type=ram_space size=2 wordsize=1; + +# this is a byte address space that should be overlayed on top of the code space +define space codebyte type=ram_space size=$(PCBYTESIZE) wordsize=1; + +# Using decimal rather than hex to match specs +# General registers start at 0 in the iospace for earlier avr8 processors +# In the Xmega line, they are not accessible in mem, and are in a register space +# +define $(REGISTER_SPACE) offset=0 size=1 [ + R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 + R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 + R20 R21 R22 R23 R24 R25 Xlo Xhi Ylo Yhi + Zlo Zhi +]; + +define $(REGISTER_SPACE) offset=0 size=2 [ + R1R0 R3R2 R5R4 R7R6 R9R8 + R11R10 R13R12 R15R14 R17R16 R19R18 + R21R20 R23R22 R25R24 + X Y Z +]; + +define $(REGISTER_SPACE) offset=18 size=8 [ + R25R24R23R22R21R20R19R18 +]; + +define $(REGISTER_SPACE) offset=0 size=8 [ + R7R6R5R4R3R2R1R0 + R15R14R13R12R11R10R9R8 +]; + +# Technically, the stack pointer is in the i/o space so should be addressable with the +# rest of the i/o registers. However, Ghidra does not react well to the stack pointer +# being indirectly addressable so we're making an exception. +define register offset=0x3D size=1 [ SPL SPH ]; +define register offset=0x3D size=2 [ SP ]; + +define register offset=0x42 size=$(PCBYTESIZE) [ PC ]; + +define register offset=0x80 size=1 [ + Cflg Zflg Nflg Vflg Sflg Hflg Tflg Iflg SKIP +]; + +##################################### +# Some AVR processors may have different io layouts not just different io. +# +# AVR processors with more than 64 KiB of RAM make use of the RAMP- registers +# to act as the high bits where the X, Y, or Z registers are used, or in direct +# addressing instructions. +# +# TODO: incorporate the use of RAMPX, RAMPY, RAMPZ in the LD, ST instructions +# ELPM, and LDS instructions use RAMPZ and RAMPD +# +# These IO registers need to be accessible to sleigh instruction PCODE +# so they are defined here. The bulk of the IO registers are defined +# as labels in the appropriate .pspec file. + + + +define mem offset=$(IO_START) size = 1 [ +# IO_START + 0x00 + _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ +# IO_START + 0x10 + _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + +# IO_START + 0x20 + _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ +# IO_START + 0x30 + _ _ _ _ _ _ _ _ + RAMPD RAMPX RAMPY RAMPZ _ _ _ SREG +]; + + +# If the AVR processor has more than 128 KiB of ROM, the processor will support the EIND +# register along with the EIJMP and EICALL extended instructions. +@if HASEIND == "1" +define mem offset=$(EIND) size=1 [ EIND ]; + +@endif + +############################## + +# Define context bits +define register offset=0x90 size=4 contextreg; + +define context contextreg + useSkipCond = (0,0) noflow # =1 skip instruction if SKIP register is true + # transient context + phase = (1,1) # =0 check for useSkipCond, =1 parse instruction +; + +## Following 8051 example rather than define bitrange +# Works better as distinct variables +@define Cflag "Cflg" +@define Zflag "Zflg" +@define Nflag "Nflg" +@define Vflag "Vflg" +@define Sflag "Sflg" +@define Hflag "Hflg" +@define Tflag "Tflg" +@define Iflag "Iflg" + + +define token opword (16) + ophi16 = ( 0,15) + ophi9 = ( 7,15) + ophi8 = ( 8,15) + ophi7 = ( 9,15) + ophi6 = (10,15) + ophi5 = (11,15) + ophi4 = (12,15) + ophi2 = (14,15) + opbit13 = (13,13) + opbit12 = (12,12) + opbit10 = (10,10) + opbit9 = ( 9, 9) + opbit8 = ( 8, 8) + opbit7 = ( 7, 7) + opbit3 = ( 3, 3) + opbit2 = ( 2, 2) + opbit0 = ( 0, 0) + oplow12 = ( 0,11) + oplow12signed = ( 0,11) signed + oplow4 = ( 0, 3) + oplow3_flag = ( 0, 2) + oplow3 = ( 0, 2) + oplow2 = ( 0, 1) + op1to3 = ( 1, 3) + op2to3 = ( 2, 3) + op3to7 = ( 3, 7) + op4to8 = ( 4, 8) + op4to6 = ( 4, 6) + op4to6_flag = ( 4, 6) + op6to7 = ( 6, 7) + op8to10 = ( 8,10) + op9to10 = ( 9,10) + op10to11 = (10,11) + RdHi = ( 4, 7) + RdHi3 = ( 4, 6) + RdFull = ( 4, 8) + RrHi = ( 0, 3) + RrHi3 = ( 0, 2) + RrLow = ( 0, 3) + RrHiLowSel = ( 9, 9) + Rdw2 = ( 4, 5) + Rdw4 = ( 4, 7) + Rrw4 = ( 0, 3) + Rstq = ( 3, 3) + RstPtr = ( 2, 3) + op0to3 = ( 0, 3) + op3to9signed = ( 3, 9) signed + op4to7 = ( 4, 7) + op8to11 = ( 8,11) +; +define token immtok(16) + next16 = (0,15) +; + +define token opfusion16(32) + op1hi4 = (12,15) + op2hi4 = (28,31) + op1hi6 = (10,15) + op2hi6 = (26,31) + op1low4 = ( 0, 3) + op2low4 = (16,19) + op1bits0to3 = ( 0, 3) + op2bits0to3 = (16,19) + op1bits1to3 = ( 1, 3) + op2bits1to3 = (17,19) + op1bits4to8 = ( 4, 8) + op2bits4to8 = (20,24) + op1bits5to7 = ( 5, 7) + op2bits5to7 = (21,23) + op1bits5to8 = ( 5, 8) + op2bits5to8 = (21,24) + op1bits8to11 = ( 8,11) + op2bits8to11 = (24,27) + op1bit0 = ( 0, 0) + op2bit0 = (16,16) + op1bit4 = ( 4, 4) + op2bit4 = (20,20) + op1bit9 = ( 9, 9) + op2bit9 = (25,25) + op1RdPair = ( 5, 8) + op1RdPairHi = ( 5, 7) + op1RrPairLow = ( 1, 3) + op1RrPairHi = ( 1, 3) + op1RrPairSel = ( 9, 9) +; + +define token opfusion24(48) + f3op1hi4 = (12,15) + f3op2hi4 = (28,31) + f3op3hi4 = (34,47) + f3op1hi6 = (10,15) + f3op2hi6 = (26,31) + f3op3hi6 = (42,47) + f3op1bits0to3 = ( 0, 3) + f3op2bits0to3 = (16,19) + f3op3bits0to3 = (32,35) + f3op2bits4to7 = (20,23) + f3op1bits5to7 = ( 5, 7) + f3op3bits5to7 = (37,39) + f3op1bits8to11 = ( 8,11) + f3op2bits8to11 = (24,27) + f3op1bit4 = ( 4, 4) + f3op3bit4 = (36,36) + f3op3bit8 = (40,40) + f3op3bit9 = (41,41) + f3op1RdPairHi = ( 5, 7) + f3op2RdHi = (20,23) +; + +define token opfusionLdsw(64) # lds lds + ldswop1hi7 = ( 9,15) + ldswop2hi7 = (41,47) + ldswop1low4 = ( 0, 3) + ldswop2low4 = (32,35) + ldswop1bits5to8 = ( 5, 8) + ldswop2bits5to8 = (37,40) + ldswop1bit4 = ( 4, 4) + ldswop2bit4 = (36,36) + ldswop1bit16 = (16,16) + ldswop2bit16 = (48,48) + ldswop1imm15 = (17,31) + ldswop2imm15 = (49,63) + ldswop1imm6 = (17,22) + ldswop2imm6 = (49,54) + ldswop1imm16 = (16,31) + ldswop2imm16 = (48,63) + ldswop1RdPair = ( 5, 8) + stswop2RdPair = (37,40) +; + +attach variables [ oplow3_flag op4to6_flag ] [ + Cflg Zflg Nflg Vflg Sflg Hflg Tflg Iflg +]; + +attach variables [ RdHi RrHi f3op2RdHi ] [ + R16 R17 R18 R19 + R20 R21 R22 R23 R24 R25 Xlo Xhi Ylo Yhi + Zlo Zhi ] +; +attach variables [ RdHi3 RrHi3 ] [ + R16 R17 R18 R19 + R20 R21 R22 R23 +]; +attach variables [ RrLow ] [ + R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 + R10 R11 R12 R13 R14 R15 +]; +attach variables [ RdFull ] [ + R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 + R10 R11 R12 R13 R14 R15 + R16 R17 R18 R19 + R20 R21 R22 R23 R24 R25 Xlo Xhi Ylo Yhi + Zlo Zhi +]; +attach variables [ Rdw2 ] [ + R25R24 X Y Z +]; +attach variables [ Rstq ] [ + Z Y +]; +attach variables [ RstPtr ] [ + Z _ Y X +]; +attach variables [ Rdw4 Rrw4 op1RdPair ldswop1RdPair stswop2RdPair ] [ + R1R0 R3R2 R5R4 R7R6 R9R8 + R11R10 R13R12 R15R14 R17R16 R19R18 + R21R20 R23R22 R25R24 + X Y Z +]; +attach variables [ op1RrPairLow ] [ + R1R0 R3R2 R5R4 R7R6 R9R8 + R11R10 R13R12 R15R14 +]; +attach variables [ op1RrPairHi op1RdPairHi f3op1RdPairHi ] [ + R17R16 R19R18 + R21R20 R23R22 R25R24 + X Y Z +]; + +RrFull: RrHi is RrHiLowSel=1 & RrHi { tmp:1 = RrHi; export tmp; } +RrFull: RrLow is RrHiLowSel=0 & RrLow { tmp:1 = RrLow; export tmp; } + +# Alternative: try using some subcontructors +op1RrPair: op1RrPairHi is op1RrPairSel=1 & op1RrPairHi { tmp:2 = op1RrPairHi; export tmp; } +op1RrPair: op1RrPairLow is op1RrPairSel=0 & op1RrPairLow { tmp:2 = op1RrPairLow; export tmp; } + +# I'm uneasy at these... as they require the top of the stack +# to know what size element to reserve before the push. +# The docs should probably say that the top of the stack byte is unused... +# +# The processor is post-decremented, and because of the way the compiler +# manipulates the stack pointer it's important to get this correct. +@if PCBYTESIZE == "2" +macro pushPC(val) { + SP = SP - 1; + *[mem]:2 SP = val; + SP = SP - 1; +} + +macro popPC(val) { + SP = SP + 1; + val = *[mem]:2 SP; + SP = SP + 1; +} + +@else # PCBYTESIZE == 3 +macro pushPC(val) { + SP = SP - 2; + *[mem]:3 SP = val; + SP = SP - 1; +} + +macro popPC(val) { + SP = SP + 1; + val = *[mem]:3 SP; + SP = SP + 2; +} + +@endif + +macro push8(val) { + *[mem]:1 SP = val; + SP = SP -1; +} + +macro pop8(val) { + SP = SP + 1; + val = *[mem]:1 SP; +} + + + +# .slaspec shortcoming: Hflag isn't computed for most results +macro setSflag() { + $(Sflag) = $(Nflag) ^ $(Vflag); +} + +macro setResultFlags(result) { + $(Nflag) = (result s< 0); + $(Zflag) = (result == 0x0); + setSflag(); +} + +macro doSubtract(pre,sub,res) { + local x = pre - sub; + $(Vflag) = sborrow(pre,sub); + $(Cflag) = (pre < sub); + setResultFlags(x); + $(Sflag) = pre s< sub; + res = x; +} + +macro doSubtractWithCarry(pre,sub,res) { + local partial = pre - sub; + local subCarry = sub + $(Cflag); + local x = pre - subCarry; + local oldZflag = $(Zflag); + $(Vflag) = sborrow(pre,sub) ^^ sborrow(partial, $(Cflag)); + $(Cflag) = (pre < sub) || (partial < $(Cflag)); + setResultFlags(x); + $(Sflag) = $(Nflag)^$(Vflag); + $(Zflag) = oldZflag & $(Zflag); + res = x; +} + +macro setMulFlags(res) { + $(Cflag) = ((res & 0x8000) != 0); + $(Zflag) = (res == 0); +} + +macro loadSREG(reg) { + reg = (zext(Cflg==1) << 0) | (zext(Zflg==1) << 1) | (zext(Nflg==1) << 2) | (zext(Vflg==1) << 3) | (zext(Sflg==1) << 4) | (zext(Hflg==1) << 5) | (zext(Tflg==1)<<6) | (zext(Iflg==1) << 7); + SREG = reg; +} + +macro storeSREG(val) { + Cflg = ((val>> 0) & 1); + Zflg = ((val>> 1) & 1); + Nflg = ((val>> 2) & 1); + Vflg = ((val>> 3) & 1); + Sflg = ((val>> 4) & 1); + Hflg = ((val>> 5) & 1); + Tflg = ((val>> 6) & 1); + Iflg = ((val>> 7) & 1); + SREG = val; +} + +# Handle possible skip instruction +# This next line is a NOP except for the phase, which is never really checked. +# A better fix may be to use -l, and ensure phase=1 is checked on the base constructors. +:^instruction is phase=0 & useSkipCond=0 & instruction [ phase=1; ] { build instruction; } +:^instruction is phase=0 & useSkipCond=1 & instruction [ phase=1; ] { + if (SKIP) goto inst_next; + build instruction; +} + +# K8 is immediate for Rd,K8 forms +K8: val is op0to3 & op8to11 [ val = (op8to11 << 4) | op0to3; ] { tmp:1 = val; export tmp; } + +@ifdef FUSION + +K16fuse: val is op1bits0to3 & op1bits8to11 & op2bits0to3 & op2bits8to11 [ val = (((op2bits8to11 << 4) | op2bits0to3) << 8) | ((op1bits8to11 << 4) | op1bits0to3); ] { tmp:2 = val; export tmp; } + +f3cmpK16: val is f3op1bits0to3 & f3op1bits8to11 & f3op2bits0to3 & f3op2bits8to11 [ val = (((f3op2bits8to11 << 4) | f3op2bits0to3) << 8) | ((f3op1bits8to11 << 4) | f3op1bits0to3); ] { tmp:2 = val; export tmp; } +f3cmpK8: val is f3op2bits0to3 & f3op2bits8to11 [ val = (f3op2bits8to11 << 4) | f3op2bits0to3; ] { tmp:1 = val; export tmp; } + +@endif + +rel7addr: rel is op3to9signed [ rel = (op3to9signed + inst_next);] { + export *[code]:2 rel; +} + +rel7dst: byteOffset is op3to9signed & rel7addr [ byteOffset = (op3to9signed + inst_next) << 1;] { + export rel7addr; +} + +rel12addr: rel is oplow12signed [ rel = oplow12signed + inst_start + 1; ] { + export *[code]:2 rel; +} + +rel12dst: byteOffset is oplow12signed & rel12addr [ byteOffset = (oplow12signed + inst_start + 1) << 1; ] { + export rel12addr; +} + +abs22addr: loc is op4to8 & opbit0; next16 [ loc = (op4to8 << 17) | (opbit0 << 16) | next16; ] { + export *[code]:2 loc; +} + +abs22dst: byteOffset is (op4to8 & opbit0; next16) & abs22addr [ byteOffset = ((op4to8 << 17) | (opbit0 << 16) | next16) << 1; ] { + export abs22addr; +} + +next16memPtrVal1: next16 is next16 { export *[mem]:1 next16; } + +@if PCBYTESIZE == "3" +next24memPtrVal1: next24 is next16 [next24 = (RAMPD << 16) | next16;] { export *[mem]:1 next24; } +@endif + +@ifdef FUSION + +ldswMemPtrVal2: ldswop1imm16 is ldswop1imm16 { export *[mem]:2 ldswop1imm16; } + +stswMemPtrVal2: ldswop2imm16 is ldswop2imm16 { export *[mem]:2 ldswop2imm16; } + +@endif + +# K6 is used in dword operation +K6: val is oplow4 & op6to7 [ val = (op6to7 << 4) | oplow4; ] { tmp:1 = val; export tmp; } + +# K7 is used by lds +K7addr: val is oplow4 & op9to10 & opbit8 [ val = ((1 ^ opbit8) << 7) | (opbit8 << 6) | (op9to10 << 4) | oplow4; ] { + export *[mem]:1 val; +} + +# Join against various spaces for dataspace... +# ##################################################################################### +# COMMENTING OUT BECAUSE "subtable symbol K7addr is not allowed in context block" +#K7Ioaddr: val is K7addr [ val = K7addr - 0x20; ] { tmp:1 = val; export tmp; } +# ##################################################################################### +# COMMENTING OUT BECAUSE "Subtable symbol K7Ioaddr is not allowed in context block" +#A7Ioaddr: val is K7Ioaddr [ val = (K7Ioaddr | 0x00) + 0x20 ; ] { export *[mem]:1 val; } +Aio6: val is oplow4 & op9to10 [ val = ((op9to10 << 4) | oplow4) + $(IO_START); ] { export *[mem]:1 val; } +Aio5: val is op3to7 [ val = (op3to7 | 0x00) + $(IO_START); ] { export *[mem]:1 val; } + +q6: val is oplow3 & op10to11 & opbit13 [ val = (opbit13 << 5) | (op10to11 << 3) | oplow3; ] { tmp:1 = val; export tmp; } + +@ifdef FUSION + +# Predicates to verify that fusion will be valid here. +# We just want to construct these. The rules are not null to avoid a NOP bug with sleigh +fusion16rrrrPred: val is op1bit0=0 & op2bit0=1 & op1bit4=0 & op2bit4=1 & op1bit9=op2bit9 & op1bits5to8=op2bits5to8 & op1bits1to3=op2bits1to3 [ val = 0; ] { tmp:2=val; export tmp; } + +fusion16rkrkPred: val is op1bits5to7=op2bits5to7 & op1bit4=0 & op2bit4=1 [ val=0; ] { tmp:2 = val; export tmp; } + +f3cmpPairPred: val is f3op1bits5to7=f3op3bits5to7 & f3op1bit4=0 & f3op3bit4=1 & f3op3bit8=1 [ val=0; ] { tmp:2 = val; export tmp; } + +f3cmpLdiPred: val is f3op3bit9=1 & f3op3bits0to3=f3op2bits4to7 [ val=0; ] { tmp:2 = val; export tmp; } + +ldswPairPred: val is ldswop1bit4=0 & ldswop2bit4=1 & ldswop1bits5to8=ldswop2bits5to8 [ val=0; ] { tmp:2 = val; export tmp; } + +stswPairPred: val is ldswop1bit4=1 & ldswop2bit4=0 & ldswop1bits5to8=ldswop2bits5to8 [ val=0; ] { tmp:2 = val; export tmp; } + +# would like to check this for const pair, but hangs sleigh compiler: ldswop1imm15=ldswop2imm15 +# So check as a few in a row +# Not any better & ldswop1imm5b=ldswop2imm5b & ldswop1imm5c=ldswop2imm5c +ldswConstPairPred: val is ldswop1bit16=0 & ldswop2bit16=1 & ldswop1imm6=ldswop2imm6 [ val=0; ] { tmp:2 = val; export tmp; } + +stswConstPairPred: val is ldswop1bit16=1 & ldswop2bit16=0 & ldswop1imm6=ldswop2imm6 [ val=0; ] { tmp:2 = val; export tmp; } + +@endif + +define pcodeop todo; +define pcodeop todoflow; +define pcodeop todoflags; +define pcodeop todotst; + +define pcodeop break; + +@ifdef FUSION +# add followed by adc +:addw op1RdPair,op1RrPair is phase=1 & op1hi6=0x3 & op2hi6=0x7 & op1RdPair & op1RrPair & fusion16rrrrPred { + local pre = op1RdPair; + local post = op1RdPair + op1RrPair; + $(Cflag) = carry(op1RdPair,op1RrPair); + $(Vflag) = scarry(pre,op1RrPair); + op1RdPair = post; + setResultFlags(post); +} + +@endif +# Rd,Rr +:adc RdFull,RrFull is phase=1 & ophi6=0x7 & RdFull & RrFull { + local res = RdFull + RrFull + $(Cflag); + $(Cflag) = carry(RdFull, RrFull) || carry(RdFull + RrFull, $(Cflag)); + $(Vflag) = scarry(RdFull, RrFull) ^^ scarry(RdFull + RrFull, $(Cflag)); + setResultFlags(res); + RdFull = res; +} +# Rd,Rr +:add RdFull,RrFull is phase=1 & ophi6=0x3 & RdFull & RrFull { + local res = RdFull + RrFull; + $(Cflag) = carry(RdFull,RrFull); + $(Vflag) = scarry(RdFull,RrFull); + setResultFlags(res); + RdFull = res; +} +# adiw Rd+1:Rd,K6 +:adiw Rdw2,K6 is phase=1 & ophi8=0x96 & Rdw2 & K6 { + local pre = Rdw2; + Rdw2 = Rdw2 + zext(K6); + $(Cflag) = carry(pre,zext(K6)); + $(Vflag) = scarry(Rdw2,zext(K6)); + setResultFlags(Rdw2); +} +# and Rd,Rr +:and RdFull,RrFull is phase=1 & ophi6=8 & RdFull & RrFull { + RdFull = RdFull & RrFull; + $(Vflag) = 0; + setResultFlags(RdFull); +} +# andi Rd,K +:andi RdHi,K8 is phase=1 & ophi4=7 & RdHi & K8 { + RdHi = RdHi & K8; + $(Vflag) = 0; + setResultFlags(RdHi); +} +# asr Rd +:asr RdFull is phase=1 & ophi7=0x4a & oplow4=0x5 & RdFull { #done + $(Cflag) = RdFull & 0x01; + RdFull = RdFull s>> 1; + $(Nflag) = (RdFull & 0x80) == 0x80; + $(Vflag) = $(Nflag) ^ $(Cflag); + setResultFlags(RdFull); +} + +# bclr s +:bclr op4to6_flag is phase=1 & ophi9=0x129 & oplow4=0x4 & op4to6_flag { #done + op4to6_flag = 0; +} + +# bld Rd,b +:bld RdFull,oplow3 is phase=1 & ophi7=0x7c & opbit3=0 & RdFull & oplow3 { + local b = $(Tflag) << oplow3; + local mask = 0xff ^ (1 << oplow3); + RdFull = (RdFull & mask) | b; +} +# brbc s,k +:brbc rel7dst,oplow3_flag is phase=1 & ophi6=0x3d & rel7dst & oplow3_flag { + if (!oplow3_flag) + goto rel7dst; +} +# brbs s,k (see prev instruction) +:brbs rel7dst,oplow3_flag is phase=1 & ophi6=0x3c & rel7dst & oplow3_flag { + if (oplow3_flag) + goto rel7dst; +} +# brcs and brcc seem to be special cases of brbs +:break is phase=1 & ophi16=0x9598 { + break(); +} +# Probably want to check for various decode logic for conditional branches... +# ... specifically BRBS 1,k +# breq k - really is BRBS 1,k +# bset s +:bset op4to6_flag is phase=1 & ophi9=(0x94<<1) & oplow4=0x8 & op4to6_flag { + op4to6_flag = 1; +} +# bst Rd,b +:bst RdFull,oplow3 is phase=1 & ophi7=0x7d & opbit3=0 & RdFull & oplow3 { + $(Tflag) = (RdFull >> oplow3) & 0x01; +} +# call k - todo - handle upper bits for 24 bit architecture +:call abs22dst is phase=1 & (ophi7=0x4a & op1to3=0x7) ... & abs22dst { + tmp:$(PCBYTESIZE) = inst_next >> 1; + pushPC(tmp); + PC = &abs22dst; + call abs22dst; +} +# cbi A,b +:cbi Aio5,oplow3 is phase=1 & ophi8=0x98 & Aio5 & oplow3 { + local x = Aio5; + x = x & (0xff ^ (1 << oplow3)); + Aio5 = x; +} +# cbr - not actual instruction + +# clc, clh, cli, cln ... variants on register clearing +# sub bits give which bits in SREG to clear +:clc is phase=1 & ophi16=0x9488 { + $(Cflag) = 0; +} +:clh is phase=1 & ophi16=0x94d8 { + $(Hflag) = 0; +} +:cli is phase=1 & ophi16=0x94f8 { + $(Iflag) = 0; +} +:cln is phase=1 & ophi16=0x94a8 { + $(Nflag) = 0; +} +:cls is phase=1 & ophi16=0x94c8 { + $(Sflag) = 0; +} +:clt is phase=1 & ophi16=0x94e8 { + $(Tflag) = 0; +} +:clv is phase=1 & ophi16=0x94b8 { + $(Vflag) = 0; +} +:clz is phase=1 & ophi16=0x9498 { + $(Zflag) = 0; +} +# clr Rd - really is EOR Rd, Rd +:com RdFull is phase=1 & ophi7=0x4a & RdFull { + RdFull = ~RdFull; + $(Vflag) = 0; + $(Cflag) = 1; + setResultFlags(RdFull); +} +:cp RdFull,RrFull is phase=1 & ophi6=0x05 & RdFull & RrFull { + local x = RdFull - RrFull; + $(Cflag) = (RdFull < RrFull); + $(Vflag) = sborrow(RdFull,RrFull); + setResultFlags(x); +# but doesn't set result into a register +} +:cpc RdFull,RrFull is phase=1 & ophi6=0x1 & RdFull & RrFull { + local res = 0; + doSubtractWithCarry(RdFull,RrFull,res); + res = res; # avoid warning +} +:cpi RdHi,K8 is phase=1 & ophi4=0x3 & RdHi & K8 { + local res = 0; + doSubtract(RdHi,K8,res); + res = res; # avoid warning +} + +@ifdef FUSION +# cpi; ldi; cpc sequence +:cpiw f3op1RdPairHi,f3cmpK16" ;ldi "f3op2RdHi,f3cmpK8 is phase=1 & f3op1hi4=0x3 & f3op2hi4=0xe & f3op3hi6=0x1 & f3cmpPairPred & f3cmpLdiPred & f3op1RdPairHi & f3op2RdHi & f3cmpK16 & f3cmpK8 { + local res = 3; + doSubtract(f3op1RdPairHi,f3cmpK16,res); + f3op2RdHi = f3cmpK8; +} +# cp; cpc sequence +:cpw op1RdPair,op1RrPair phase=1 & is op1hi6=0x5 & op2hi6=0x1 & fusion16rrrrPred & op1RdPair & op1RrPair { + local res = op1RdPair - op1RrPair; + $(Vflag) = sborrow(op1RdPair,op1RrPair); + $(Cflag) = (op1RdPair < op1RrPair); + setResultFlags(res); + $(Sflag) = op1RdPair s< op1RrPair; +} + +@endif + +:cpse RdFull,RrFull is phase=1 & ophi6=0x4 & RdFull & RrFull [ useSkipCond=1; globalset(inst_next,useSkipCond); ] { + SKIP = (RdFull == RrFull); +} + +:dec RdFull is phase=1 & ophi7=0x4a & oplow4=0xa & RdFull { + # doesn't set the C flag + $(Vflag) = (RdFull == 0x80); + RdFull = RdFull - 1; + setResultFlags(RdFull); +} + +define pcodeop encrypt; +define pcodeop decrypt; + +:des op4to7 is phase=1 & ophi8=0x94 & oplow4=0xb & op4to7 { + val:1 = op4to7; + if (Hflg) goto ; + R15R14R13R12R11R10R9R8 = decrypt(R7R6R5R4R3R2R1R0, val); + goto inst_next; + + R15R14R13R12R11R10R9R8 = encrypt(R7R6R5R4R3R2R1R0, val); +} + +@if HASEIND == "1" +:eicall is phase=1 & ophi16=0x9519 { + ptr:$(PCBYTESIZE) = inst_next >> 1; + pushPC(ptr); + PC = zext(Z) | (zext(EIND) << 16); + call [PC]; +} + +:eijmp is phase=1 & ophi16=0x9419 { + PC = zext(Z) | (zext(EIND) << 16); + goto [PC]; +} + +@endif + +@if PCBYTESIZE == "3" +:elpm is phase=1 & ophi16=0x95d8 { + ptr:3 = zext(Z) | (zext(RAMPZ) << 16); + local falseRead:1 = *[code]:2 (ptr >> 1); + R0 = *[codebyte]:1 ptr; +} + +:elpm RdFull, Z is phase=1 & ophi7=0x48 & oplow4=0x6 & RdFull & Z { + ptr:3 = zext(Z) | (zext(RAMPZ) << 16); + local falseRead:1 = *[code]:1 (ptr >> 1); + RdFull = *[codebyte]:1 ptr; +} + +ElpmPlus: Z^"+" is Z {} +:elpm RdFull, ElpmPlus is phase=1 & ophi7=0x48 & oplow4=0x7 & RdFull & ElpmPlus { + ptr:3 = zext(Z) | (zext(RAMPZ) << 16); + local falseRead:1 = *[code]:1 (ptr >> 1); + RdFull = *[codebyte]:1 ptr; + ptr = ptr + 1; + Z = ptr:2; + RAMPZ = ptr[16,8]; +} + +@endif + +:eor RdFull,RrFull is phase=1 & ophi6=0x9 & RdFull & RrFull { + RdFull = RdFull ^ RrFull; + $(Vflag) = 0; + setResultFlags(RdFull); +} + +# Manual uses fmul. I prefer fracmul to distinguish from floating point +:fracmul RdHi,RrHi is phase=1 & ophi9=0x6 & opbit3=1 & RdHi & RrHi { todo(); } +:fracmuls RdHi,RrHi is phase=1 & ophi9=0x7 & opbit3=0 & RdHi & RrHi { todo(); } +:fracmulsu RdHi,RrHi is phase=1 & ophi9=0x7 & opbit3=1 & RdHi & RrHi { todo(); } + +:icall is phase=1 & ophi16=0x9509 { + ptr:$(PCBYTESIZE) = inst_next >> 1; + pushPC(ptr); + PC = zext(Z); + call [PC]; +} +:ijmp is phase=1 & ophi16=0x9409 { + PC = zext(Z); + goto [PC]; +} +# in Rd,A +:in RdFull,Aio6 is phase=1 & ophi5=0x16 & RdFull & Aio6 { + RdFull = Aio6; +} +:in RdFull,SPL is phase=1 & ophi5=0x16 & RdFull & op9to10=3 & oplow4=0xd & SPL { + RdFull = SPL; +} +:in RdFull,SPH is phase=1 & ophi5=0x16 & RdFull & op9to10=3 & oplow4=0xe & SPH { + RdFull = SPH; +} +:in RdFull,SREG is phase=1 & ophi5=0x16 & RdFull & op9to10=3 & oplow4=0xf & SREG { + loadSREG(RdFull); +} + +:inc RdFull is phase=1 & ophi7=0x4a & oplow4=0x3 & RdFull { + # inc doesn't set the C flag. + $(Vflag) = RdFull == 0x7f; + RdFull = RdFull + 1; + setResultFlags(RdFull); +} +:jmp abs22dst is phase=1 & (ophi7=0x4a & op1to3=0x6) ... & abs22dst { + PC = &abs22dst; + goto abs22dst; +} + +:lac Z,RdFull is phase=1 & ophi7=0x49 & oplow4=0x6 & Z & RdFull { + tmp:1 = *[mem]:1 Z; + tmp = tmp & (0xff - RdFull); + *[mem]:1 Z = tmp; + RdFull = tmp; +} + +:las Z,RdFull is phase=1 & ophi7=0x49 & oplow4=0x5 & Z & RdFull { + tmp:1 = *[mem]:1 Z; + tmp = tmp | RdFull; + *[mem]:1 Z = tmp; + RdFull = tmp; +} + +:lat Z,RdFull is phase=1 & ophi7=0x49 & oplow4=0x7 & Z & RdFull { + tmp:1 = *[mem]:1 Z; + tmp = tmp ^ RdFull; + *[mem]:1 Z = tmp; + RdFull = tmp; +} + +# three forms, really just specifying the increment mode +# ld Rd,X +:ld RdFull,X is phase=1 & ophi7=0x48 & oplow4=0xc & X & RdFull { + tmp:2 = X; + RdFull = *[mem]:1 tmp; +} +# ld Rd,Y; ld Rd,Z +# Special case of ldd +q below - will conflict with -i sleigh compile +:ld RdFull,RstPtr is phase=1 & ophi7=0x40 & oplow3=0x0 & RdFull & RstPtr { + tmp:2 = RstPtr; + RdFull = *[mem]:1 tmp; +} + +# ld Rd,Y+ ; ld Rd, X+; ld Rd, Z+ +LdPlus: RstPtr^"+" is RstPtr { tmp:2 = RstPtr; RstPtr = RstPtr + 0x01; export tmp; } +:ld RdFull,LdPlus is phase=1 & ophi7=0x48 & oplow2=0x01 & RdFull & LdPlus { + RdFull = *[mem]:1 LdPlus; +} + +# ld Rd,-Y ; ld Rd, -X; ld Rd, -Z +LdPredec: "-"^RstPtr is RstPtr { RstPtr = RstPtr - 0x01; export RstPtr; } + +:ld RdFull,LdPredec is phase=1 & ophi7=0x48 & oplow2=0x02 & RdFull & LdPredec { + tmp:2 = LdPredec; + RdFull = *[mem]:1 tmp; +} + +# ldd Rd,Y+q +# ldd Rd,Z+q +LddYZq: Rstq^"+"^q6 is phase=1 & Rstq & q6 { local ptr = Rstq + zext(q6); export ptr; } +:ldd RdFull,LddYZq is phase=1 & ophi2=0x2 & opbit12=0 & opbit9=0 & opbit3 & LddYZq & RdFull { + RdFull = *[mem]:1 LddYZq; +} + +# Rd,K +:ldi RdHi,K8 is phase=1 & ophi4=0xe & RdHi & K8 { + RdHi = K8; +} + +@if PCBYTESIZE == "2" +# lds Rd,k +:lds RdFull,next16memPtrVal1 is phase=1 & ophi7=0x48 & oplow4=0 & RdFull; next16memPtrVal1 { + RdFull = next16memPtrVal1; +} +@else +:lds RdFull,next24memPtrVal1 is phase=1 & ophi7=0x48 & oplow4=0 & RdFull; next24memPtrVal1 { + RdFull = next24memPtrVal1; +} +@endif + +@ifdef FUSION +# Fuse together consecuitive lds ; lds +# +:ldsw ldswop1RdPair,ldswMemPtrVal2 is phase=1 & ldswop1hi7=0x48 & ldswop2hi7=0x48 & ldswop1low4=0 & ldswop2low4=0 & ldswMemPtrVal2 & ldswop1RdPair & ldswPairPred & ldswConstPairPred { + ldswop1RdPair = ldswMemPtrVal2; +} + +@endif +# lds Rd,k Seem to get some problems here... but 16-bit instruction isn't available on all atmega64. +# Furthermore, it will sometimes conflict with ldd Z+q for q=0x2_ +:lds RdHi,K7addr is phase=1 & ophi5=0x14 & RdHi & K7addr { + RdHi = K7addr; +} + +# lpm R0 +:lpm R0 is phase=1 & ophi16=0x95c8 & R0 { + ptr:$(PCBYTESIZE) = zext(Z); + local falseRead:1 = *[code]:1 (ptr >> 1); + R0 = *[codebyte]:$(PCBYTESIZE) ptr; +} +# lpm Rd,Z +:lpm RdFull,Z is phase=1 & ophi7=0x48 & op1to3=0x2 & RdFull & Z & opbit0=0 { + ptr:$(PCBYTESIZE) = zext(Z); + local falseRead:1 = *[code]:1 (ptr >> 1); + RdFull = *[codebyte]:$(PCBYTESIZE) ptr; +} +# lpm Rd,Z+ +LpmPlus: Z^"+" is Z {} +:lpm RdFull,LpmPlus is phase=1 & ophi7=0x48 & op1to3=0x2 & RdFull & LpmPlus & opbit0=1 { + ptr:$(PCBYTESIZE) = zext(Z); + local falseRead:1 = *[code]:1 (ptr >> 1); + RdFull = *[codebyte]:$(PCBYTESIZE) ptr; + Z = Z + 1; +} +# lsl - just an assembly mnemonic for add +:lsr RdFull is phase=1 & ophi7=0x4a & oplow4=0x6 & RdFull { + $(Cflag) = RdFull & 0x01; + RdFull = (RdFull >> 1); + $(Vflag) = $(Cflag); + setResultFlags(RdFull); +} +# mov Rd,Rr +:mov RdFull,RrFull is phase=1 & ophi6=0xb & RdFull & RrFull { + RdFull = RrFull; +} +# movw Rd+1:Rd,Rr+1Rr +:movw Rdw4,Rrw4 is phase=1 & ophi8=0x1 & Rdw4 & Rrw4 { + Rdw4 = Rrw4; +} +:mul RdFull,RrFull is phase=1 & ophi6=0x27 & RdFull & RrFull { + a:2 = zext(RdFull); + b:2 = zext(RrFull); + R1R0 = a * b; + setMulFlags(R1R0); +} +:muls RdHi,RrHi is phase=1 & ophi8=0x2 & RdHi & RrHi { + a:2 = sext(RdHi); + b:2 = sext(RrHi); + R1R0 = a * b; + setMulFlags(R1R0); +} +:mulsu RdHi3,RrHi3 is phase=1 & ophi8=0x3 & opbit7=0 & opbit3=0 & RdHi3 & RrHi3 { + a:2 = sext(RdHi3); + b:2 = zext(RrHi3); + R1R0 = a * b; + setMulFlags(R1R0); +} +:neg RdFull is phase=1 & ophi7=0x4a & oplow4=1 & RdFull { + RdFull = -RdFull; + $(Vflag) = (RdFull == 0x80); + $(Cflag) = (RdFull != 0); + setResultFlags(RdFull); +} +:nop is phase=1 & ophi16=0x0 { +} +:or RdFull,RrFull is phase=1 & ophi6=0xa & RdFull & RrFull { + RdFull = RdFull | RrFull; + $(Vflag) = 0; + setResultFlags(RdFull); +} +:ori RdHi,K8 is phase=1 & ophi4=0x6 & RdHi & K8 { + RdHi = RdHi | K8; + $(Vflag) = 0; + setResultFlags(RdHi); +} +# out A,Rr # Note: Rr occupies the normal Rd position +:out Aio6,RdFull is phase=1 & ophi5=0x17 & Aio6 & RdFull { + Aio6 = RdFull; +} +:out SPL,RdFull is phase=1 & ophi5=0x17 & RdFull & op9to10=3 & oplow4=0xd & SPL { + SPL = RdFull; +} +:out SPH,RdFull is phase=1 & ophi5=0x17 & RdFull & op9to10=3 & oplow4=0xe & SPH { + SPH = RdFull; +} +:out SREG,RdFull is phase=1 & ophi5=0x17 & RdFull & op9to10=3 & oplow4=0xf & SREG { + storeSREG(RdFull); +} + +:pop RdFull is phase=1 & ophi7=0x48 & oplow4=0xf & RdFull { + pop8(RdFull); +} +# push Rf # Note: Rr occupies the normal Rd position +:push RdFull is phase=1 & ophi7=0x49 & oplow4=0xf & RdFull { + push8(RdFull); +} + +# rcall . is used by the compiler to create space on the stack +:rcall "." is phase=1 & ophi4=0xd & oplow12=0 { + ptr:$(PCBYTESIZE) = inst_next >> 1; + pushPC(ptr); +} + +:rcall rel12dst is phase=1 & ophi4=0xd & rel12dst { + ptr:$(PCBYTESIZE) = inst_next >> 1; + pushPC(ptr); + PC = &rel12dst; + call rel12dst; +} + +:ret is phase=1 & ophi16=0x9508 { + # Could also handle word size options here + popPC(PC); + return [PC]; +} +:reti is phase=1 & ophi16=0x9518 { + $(Iflag) = 1; + popPC(PC); + return [PC]; +} +# rjmp k +:rjmp rel12dst is phase=1 & ophi4=0xc & rel12dst { + goto rel12dst; +} +# ROL is ADC Rd,Rd +:ror RdFull is phase=1 & ophi7=0x4a & oplow4=0x7 & RdFull { + local c = $(Cflag); + local cnew = RdFull & 0x01; + RdFull = (c << 7) | (RdFull >> 1); + $(Cflag) = cnew; + $(Nflag) = (RdFull & 0x80) == 0x80; + $(Vflag) = $(Cflag) ^ $(Nflag); + setResultFlags(RdFull); +} + +:sbc RdFull,RrFull is phase=1 & ophi6=0x2 & RdFull & RrFull { + doSubtractWithCarry(RdFull,RrFull,RdFull); +} + +:sbci RdHi,K8 is phase=1 & ophi4=4 & RdHi & K8 { + doSubtractWithCarry(RdHi,K8,RdHi); +} + +@ifdef FUSION +# subi sbci +:subiw op1RdPairHi,K16fuse is phase=1 & op1hi4=0x5 & op2hi4=0x4 & K16fuse & fusion16rkrkPred & op1RdPairHi { + # doSubtract(op1RdPairHi,K16fuse,op1RdPairHi); + local res = op1RdPairHi - K16fuse; + local pre = op1RdPairHi; + $(Vflag) = sborrow(pre,K16fuse); + $(Cflag) = (op1RdPairHi < K16fuse); + op1RdPairHi = res; + setResultFlags(res); + $(Sflag) = pre s< K16fuse; +} + +@endif +:sbi Aio5,oplow3 is phase=1 & ophi8=0x9a & Aio5 & oplow3 { + Aio5 = Aio5 | (1 << oplow3); +} + +:sbic Aio5,oplow3 is phase=1 & ophi8=0x99 & Aio5 & oplow3 [ useSkipCond=1; globalset(inst_next,useSkipCond); ] { + SKIP = ((Aio5 & (1 << oplow3)) == 0); +} +:sbis Aio5,oplow3 is phase=1 & ophi8=0x9b & Aio5 & oplow3 [ useSkipCond=1; globalset(inst_next,useSkipCond); ] { + SKIP = ((Aio5 & (1 << oplow3)) != 0); +} + +:sbiw Rdw2,K6 is phase=1 & ophi8=0x97 & Rdw2 & K6 { + local pre = Rdw2; + Rdw2 = Rdw2 - zext(K6); + $(Cflag) = (pre < zext(K6)); + $(Vflag) = sborrow(pre,zext(K6)); + setResultFlags(Rdw2); +} +# sbr is an alias for ori + +:sbrc RdFull,oplow3 is phase=1 & ophi7=0x7e & opbit3=0 & RdFull & oplow3 [ useSkipCond=1; globalset(inst_next,useSkipCond); ] { + SKIP = ((RdFull & (1 << oplow3)) == 0); +} +:sbrs RdFull,oplow3 is phase=1 & ophi7=0x7f & opbit3=0 & RdFull & oplow3 [ useSkipCond=1; globalset(inst_next,useSkipCond); ] { + SKIP = ((RdFull & (1 << oplow3)) != 0); +} + +# More flag setting sec, seh, sei, sen, ses, set, sev, sez +# Implemented as bset +:ser RdHi is phase=1 & ophi8=0xef & oplow4=0xf & RdHi { + RdHi = 0xff; +} + +define pcodeop sleep; + +:sleep is phase=1 & ophi16=0x9588 { + sleep(); +} + +define pcodeop store_program_mem; # make this stand out. + +:spm Z is phase=1 & ophi16=0x95e8 & Z { + ptr:$(PCBYTESIZE) = zext(Z) << 1; + local falseWrite:1 = *[code]:1 (ptr >> 1); + *[codebyte]:$(PCBYTESIZE) ptr = R1R0; + store_program_mem(); +} + +SpmPlus: Z^"+" is Z {} +:spm SpmPlus is phase=1 & ophi16=0x95f8 & SpmPlus { + ptr:$(PCBYTESIZE) = zext(Z) << 1; + local falseWrite:1 = *[code]:1 (ptr >> 1); + *[codebyte]:$(PCBYTESIZE) ptr = R1R0; + Z = Z + 1; + store_program_mem(); +} +# For stores, see the ld code (just flip bit 9) +:st X, RdFull is phase=1 & ophi7=0x49 & oplow4=0xc & X & RdFull { + tmp:2 = X; + *[mem]:1 tmp = RdFull; +} +# st Rd,Y; st Rd,Z +:st RstPtr, RdFull is phase=1 & ophi7=0x41 & oplow3=0x0 & RdFull & RstPtr { + tmp:2 = RstPtr; + *[mem]:1 tmp = RdFull; +} + +# st Rd,Y+ ; st Rd, X+; st Rd, Z+ +StPlus: RstPtr^"+" is RstPtr { tmp:2 = RstPtr; RstPtr = RstPtr + 0x01; export tmp; } +:st StPlus, RdFull is phase=1 & ophi7=0x49 & oplow2=0x01 & RdFull & StPlus { + *[mem]:1 StPlus = RdFull; +} + +# st Rd,-Y ; st Rd, -X; st Rd, -Z +StPredec: "-"^RstPtr is RstPtr { RstPtr = RstPtr - 0x01; export RstPtr; } + +:st StPredec, RdFull is phase=1 & ophi7=0x49 & oplow2=0x02 & RdFull & StPredec { + tmp:2 = StPredec; + *[mem]:1 tmp = RdFull; +} + +# std Rd,Y+q +# std Rd,Z+q +StdYZq: Rstq^"+"^q6 is Rstq & q6 { local ptr = Rstq + zext(q6); export ptr; } +:std StdYZq, RdFull is phase=1 & ophi2=0x2 & opbit12=0 & opbit9=1 & RdFull & opbit3 & StdYZq { + *[mem]:1 StdYZq = RdFull; +} + +:sts next16memPtrVal1,RdFull is phase=1 & ophi7=0x49 & oplow4=0 & RdFull; next16memPtrVal1 { + next16memPtrVal1 = RdFull; +} + +@ifdef FUSION +# sts ; sts emits backwards with respect to lds; lds +:stsw stswMemPtrVal2,stswop2RdPair is phase=1 & ldswop1hi7=0x49 & ldswop2hi7=0x49 & ldswop1low4=0 & ldswop2low4=0 & stswMemPtrVal2 & stswop2RdPair & stswPairPred & stswConstPairPred { + stswMemPtrVal2 = stswop2RdPair; +} + +@endif +# see manual for computation of address for 16-bit STS +:sts K7addr, RdHi is phase=1 & ophi5=0x15 & RdHi & K7addr { + K7addr = RdHi; +} +:sub RdFull,RrFull is phase=1 & ophi6=0x6 & RdFull & RrFull { + doSubtract(RdFull,RrFull,RdFull); +} +# Rd,K +:subi RdHi,K8 is phase=1 & ophi4=5 & RdHi & K8 { + doSubtract(RdHi,K8,RdHi); +} +:swap RdFull is phase=1 & ophi7=0x4a & oplow4=2 & RdFull { + RdFull = (RdFull >> 4) | (RdFull << 4); +} + +# tst is AND Rd,Rd +define pcodeop watchdog_reset; + +:wdr is phase=1 & ophi16=0x95a8 { + watchdog_reset(); +} +:xch RdFull is phase=1 & ophi7=0x49 & oplow4=0x4 & RdFull { + ptr:2 = Z; + local tmp = *[mem]:1 ptr; + *[mem]:1 ptr = RdFull; + RdFull = tmp; +} + diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8.slaspec b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8.slaspec new file mode 100644 index 0000000..7ecbc8d --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8.slaspec @@ -0,0 +1,7 @@ +# AVR8 with 16-bit addressable code space + +@define PCBYTESIZE "2" +@define HASEIND "0" + +@include "avr8.sinc" + diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8e.slaspec b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8e.slaspec new file mode 100644 index 0000000..7895d5a --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8e.slaspec @@ -0,0 +1,7 @@ +# AVR8 with 16-bit addressable code space and support for + +@define PCBYTESIZE "2" +@define HASEIND "1" + +@include "avr8.sinc" + diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8egcc.cspec b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8egcc.cspec new file mode 100644 index 0000000..7dca7dc --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8egcc.cspec @@ -0,0 +1,166 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8eind.slaspec b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8eind.slaspec new file mode 100644 index 0000000..6677949 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8eind.slaspec @@ -0,0 +1,7 @@ +# AVR8 with 22-bit addressable code space + +@define PCBYTESIZE "3" +@define HASEIND "1" + +@include "avr8.sinc" + diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8gcc.cspec b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8gcc.cspec new file mode 100644 index 0000000..5e35b79 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8gcc.cspec @@ -0,0 +1,160 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8iarV1.cspec b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8iarV1.cspec new file mode 100644 index 0000000..3f14042 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8iarV1.cspec @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8imgCraftV8.cspec b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8imgCraftV8.cspec new file mode 100644 index 0000000..fd81d22 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8imgCraftV8.cspec @@ -0,0 +1,40 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8xmega.pspec b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8xmega.pspec new file mode 100644 index 0000000..38cdd9f --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8xmega.pspec @@ -0,0 +1,1490 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8xmega.slaspec b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8xmega.slaspec new file mode 100644 index 0000000..6fdb38b --- /dev/null +++ b/python/icicle/Ghidra/Processors/Atmel/data/languages/avr8xmega.slaspec @@ -0,0 +1,11 @@ +# AVR8 with 22-bit addressable code space + +@define PCBYTESIZE "3" +@define HASEIND "1" + +@define IO_START "0" +@define REGISTER_SPACE "register" +@define EIND "0x3c" + +@include "avr8.sinc" + diff --git a/python/icicle/Ghidra/Processors/CP1600/data/languages/CP1600.cspec b/python/icicle/Ghidra/Processors/CP1600/data/languages/CP1600.cspec new file mode 100644 index 0000000..611eedd --- /dev/null +++ b/python/icicle/Ghidra/Processors/CP1600/data/languages/CP1600.cspec @@ -0,0 +1,43 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/CP1600/data/languages/CP1600.ldefs b/python/icicle/Ghidra/Processors/CP1600/data/languages/CP1600.ldefs new file mode 100644 index 0000000..45a7688 --- /dev/null +++ b/python/icicle/Ghidra/Processors/CP1600/data/languages/CP1600.ldefs @@ -0,0 +1,15 @@ + + + + + General Instruments CP1600 + + + diff --git a/python/icicle/Ghidra/Processors/CP1600/data/languages/CP1600.opinion b/python/icicle/Ghidra/Processors/CP1600/data/languages/CP1600.opinion new file mode 100644 index 0000000..c974dcf --- /dev/null +++ b/python/icicle/Ghidra/Processors/CP1600/data/languages/CP1600.opinion @@ -0,0 +1,2 @@ + + diff --git a/python/icicle/Ghidra/Processors/CP1600/data/languages/CP1600.pspec b/python/icicle/Ghidra/Processors/CP1600/data/languages/CP1600.pspec new file mode 100644 index 0000000..6be5008 --- /dev/null +++ b/python/icicle/Ghidra/Processors/CP1600/data/languages/CP1600.pspec @@ -0,0 +1,5 @@ + + + + + diff --git a/python/icicle/Ghidra/Processors/CP1600/data/languages/CP1600.slaspec b/python/icicle/Ghidra/Processors/CP1600/data/languages/CP1600.slaspec new file mode 100644 index 0000000..5003b32 --- /dev/null +++ b/python/icicle/Ghidra/Processors/CP1600/data/languages/CP1600.slaspec @@ -0,0 +1,657 @@ +define endian=big; +define alignment=2; +define space ram type=ram_space wordsize=2 size=2 default; +define space register type=register_space size=2; + +define register offset=0x00 size=2 [ R0 R1 R2 R3 R4 R5 R6 R7 ]; +define register offset=0x10 size=1 [ I C O Z S ]; +define register offset=0x20 size=4 [ contextreg ]; + +define token opcode_word (16) + target3_5 = (3, 5) + reg3_5 = (3, 5) + target0_2 = (0, 2) + reg0_2 = (0, 2) + reg0_1 = (0, 1) + operation_size = (2, 2) + + branch_sign = (5, 5) + branch_external = (4, 4) + branch_condition = (0, 3) + external_condition = (0, 3) + + opcode6_9 = (6, 9) + opcode3_9 = (3, 9) + opcode2_9 = (2, 9) + opcode1_9 = (1, 9) + opcode0_9 = (0, 9) +; + +define token jump_token (32) + target24_25 = (24, 25) + reg24_25 = (24, 25) + address_hi = (18, 23) + jump_type = (16, 17) + address_lo = (0, 9) +; + +define token double16 (32) + value_lo = (16, 23) + value_hi = (0, 7) +; + +define token immediate16 (16) + imm16 = (0, 15) + addr16 = (0, 15) +; + +define context contextreg + doublebyte = (0, 0) noflow +; + +attach variables [ reg0_1 ] [ R0 R1 R2 R3 ]; +attach variables [ reg0_2 reg3_5 ] [ R0 R1 R2 R3 R4 R5 R6 R7 ]; +attach variables [ reg24_25 ] [ R4 R5 R6 R7 ]; + +################################################################ + +jmpdest16: reloc is address_hi & address_lo [ reloc = (address_hi << 10) + address_lo; ] { export *:2 reloc; } +branchdest16: reloc is branch_sign=0 ; imm16 [ reloc = inst_start + 2 + imm16; ] { export *:2 reloc; } +branchdest16: reloc is branch_sign=1 ; imm16 [ reloc = inst_start + 2 + (imm16 ^ 0xFFFF); ] { export *:2 reloc; } +splitimm16: split is value_hi & value_lo [ split = (value_hi << 8) + value_lo; ] { local tmp:2 = split & 0xFFFF; export tmp; } + +impliedval16: reg3_5 is reg3_5 & (target3_5=0 | target3_5=1 | target3_5=2 | target3_5=3 | target3_5=7) & doublebyte=0 { + local tmp:2 = *:2 reg3_5; + export tmp; +} + +impliedval16: reg3_5 is reg3_5 & (target3_5=4 | target3_5=5) & doublebyte=0 { + local tmp:2 = *:2 reg3_5; + reg3_5 = reg3_5 + 1; + export tmp; +} + +impliedval16: reg3_5 is reg3_5 & target3_5=6 & doublebyte=0 { + reg3_5 = reg3_5 - 1; + local tmp:2 = *:2 reg3_5; + export tmp; +} + +impliedval16: reg3_5 is reg3_5 & (target3_5=4 | target3_5=5) & doublebyte=1 { + local val:4 = *:4 reg3_5; + local low:1 = val(2); + local high:1 = val(0); + local tmp:2 = (zext(high) << 8) | zext(low); + reg3_5 = reg3_5 + 2; + export tmp; +} + +impliedval16: reg3_5 is reg3_5 & target3_5=6 & doublebyte=1 { + reg3_5 = reg3_5 - 2; + local val:4 = *:4 reg3_5; + local low:1 = val(2); + local high:1 = val(0); + local tmp:2 = (zext(high) << 8) | zext(low); + export tmp; +} + +impliedval16: reg3_5 is reg3_5 & (target3_5=0 | target3_5=1 | target3_5=2 | target3_5=3 | target3_5=7) & doublebyte=1 { + local val:2 = *:1 reg3_5; + val = (zext(val) << 8) | zext(val); + export val; +} + +checkbranch: is reg0_2=7 { goto [R7]; } +checkbranch: is reg0_2 {} +regval0_2: is reg0_2=7 { + local tmp:2 = inst_next / 2; + export tmp; +} +regval0_2: is reg0_2 { export reg0_2; } + +cc: "" is branch_external=0 & branch_condition=0 { local tmp:1 = 1; export tmp; } +cc: "C" is branch_external=0 & branch_condition=1 { export C; } +cc: "OV" is branch_external=0 & branch_condition=2 { export O; } +cc: "PL" is branch_external=0 & branch_condition=3 { local tmp = !S; export tmp; } +cc: "EQ" is branch_external=0 & branch_condition=4 { export Z; } +cc: "LT" is branch_external=0 & branch_condition=5 { local tmp = S != O; export tmp; } +cc: "LE" is branch_external=0 & branch_condition=6 { local tmp = (Z == 1) || (S != O); export tmp; } +cc: "USC" is branch_external=0 & branch_condition=7 { local tmp = S != C; export tmp; } +cc: "NC" is branch_external=0 & branch_condition=9 { local tmp = !C; export tmp; } +cc: "NOV" is branch_external=0 & branch_condition=10 { local tmp = !O; export tmp; } +cc: "MI" is branch_external=0 & branch_condition=11 { export S; } +cc: "NEQ" is branch_external=0 & branch_condition=12 { local tmp = !Z; export tmp; } +cc: "GE" is branch_external=0 & branch_condition=13 { local tmp = S == O; export tmp; } +cc: "GT" is branch_external=0 & branch_condition=14 { local tmp = (Z == 0) || (S == O); export tmp; } +cc: "ESC" is branch_external=0 & branch_condition=15 { local tmp = S == C; export tmp; } + +################################################################ + +macro resultFlags(value) { + Z = value == 0; + S = value s< 0; +} + +macro addition(first_w, first_r, second) { + local tmpC = carry(first_r, second); + local tmpO = scarry(first_r, second); + first_w = first_r + second; + C = tmpC; + O = tmpO; + resultFlags(first_w); +} + +macro comparison(first, second) { + local __val__ = first - second; + O = sborrow(first, second); + C = first < second; + resultFlags(__val__); +} + +macro subtraction(first_w, first_r, second) { + local __val__ = first_r - second; + O = sborrow(first_r, second); + C = first_r < second; + resultFlags(__val__); + first_w = __val__; +} + +################################################################ + +define pcodeop TerminateCurrentInterrupt; +define pcodeop SoftwareInterrupt; + +################################################################ + +:ADD addr16, reg0_2 is opcode3_9=0x0058 & reg0_2 & regval0_2 & checkbranch ; addr16 { + local ptr:2 = addr16; + addition(reg0_2, regval0_2, *:2 ptr); + build checkbranch; +} + +:ADD@ impliedval16, reg0_2 is opcode6_9=0x000B & reg0_2 & regval0_2 & checkbranch & impliedval16 { + addition(reg0_2, regval0_2, impliedval16); + build checkbranch; +} + +:ADCR reg0_2 is opcode3_9=0x0005 & reg0_2 & regval0_2 & checkbranch { + local oldC = zext(C); + addition(reg0_2, regval0_2, oldC); + build checkbranch; +} + +:ADDR reg3_5, reg0_2 is opcode6_9=0x0003 & reg3_5 & reg0_2 & regval0_2 & checkbranch { + addition(reg0_2, regval0_2, reg3_5); + build checkbranch; +} + +:AND addr16, reg0_2 is opcode3_9=0x0070 & reg0_2 & regval0_2 & checkbranch ; addr16 { + local ptr:2 = addr16; + reg0_2 = regval0_2 & *:2 ptr; + resultFlags(reg0_2); + build checkbranch; +} + +:AND@ impliedval16, reg0_2 is opcode6_9=0x000E & reg0_2 & regval0_2 & checkbranch & impliedval16 { + reg0_2 = regval0_2 & impliedval16; + resultFlags(reg0_2); + build checkbranch; +} + +:ANDR reg3_5, reg0_2 is opcode6_9=0x0006 & reg3_5 & reg0_2 & regval0_2 & checkbranch { + reg0_2 = regval0_2 & reg3_5; + resultFlags(reg0_2); + build checkbranch; +} + +:B^cc branchdest16 is (opcode6_9=0x0008 & cc) ... & branchdest16 { + if (cc) goto branchdest16; +} + +:BEXT branchdest16, external_condition is (opcode6_9=0x0008 & branch_external=1 & external_condition) ... & branchdest16 { + goto branchdest16; +} + +:CLRC is opcode0_9=0x0006 { + C = 0; +} + +:CLRR reg0_2 is opcode6_9=0x0007 & reg0_2 & (target0_2=target3_5) & checkbranch { + reg0_2 = 0; + resultFlags(reg0_2); + build checkbranch; +} + +:CMP addr16, reg0_2 is opcode3_9=0x0068 & reg0_2 ; addr16 { + local ptr:2 = addr16; + comparison(reg0_2, *:2 ptr); +} + +:CMP@ impliedval16, reg0_2 is opcode6_9=0x000D & reg0_2 & impliedval16 { + comparison(reg0_2, impliedval16); +} + +:CMPR reg3_5, reg0_2 is opcode6_9=0x0005 & reg3_5 & reg0_2 { + comparison(reg0_2, reg3_5); +} + +:COMR reg0_2 is opcode3_9=0x0003 & reg0_2 & regval0_2 & checkbranch { + reg0_2 = ~regval0_2; + resultFlags(reg0_2); + build checkbranch; +} + +:DECR reg0_2 is opcode3_9=0x0002 & reg0_2 & regval0_2 & checkbranch { + reg0_2 = regval0_2 - 1; + resultFlags(reg0_2); + build checkbranch; +} + +:DIS is opcode0_9=0x0003 { + I = 0; +} + +:EIS is opcode0_9=0x0002 { + I = 1; +} + +:GSWD reg0_1 is opcode2_9=0x000C & reg0_1 { + local mask:2 = (zext(S) << 7) + (zext(Z) << 6) + (zext(O) << 5) + (zext(C) << 4); + reg0_1 = (mask << 8) + mask; +} + +:HLT is opcode0_9=0x0000 { + goto inst_start; +} + +:INCR reg0_2 is opcode3_9=0x0001 & reg0_2 & regval0_2 & checkbranch { + reg0_2 = regval0_2 + 1; + resultFlags(reg0_2); + build checkbranch; +} + +:J jmpdest16 is opcode0_9=0x0004 ; jump_type=0 & target24_25=3 & jmpdest16 { + goto jmpdest16; +} + +:JD jmpdest16 is opcode0_9=0x0004 ; jump_type=2 & target24_25=3 & jmpdest16 { + I = 0; + goto jmpdest16; +} + +:JE jmpdest16 is opcode0_9=0x0004 ; jump_type=1 & target24_25=3 & jmpdest16 { + I = 1; + goto jmpdest16; +} + +:JR reg3_5 is opcode6_9=0x0002 & reg3_5 & reg0_2 & reg0_2=7 { + reg0_2 = reg3_5; + resultFlags(reg0_2); + return [reg0_2]; +} + +:JSR reg24_25, jmpdest16 is opcode0_9=0x0004 ; jump_type=0 & reg24_25 & jmpdest16 { + reg24_25 = inst_next; + call jmpdest16; +} + +:JSRD reg24_25, jmpdest16 is opcode0_9=0x0004 ; jump_type=2 & reg24_25 & jmpdest16 { + I = 0; + reg24_25 = inst_next; + call jmpdest16; +} + +:JSRE reg24_25, jmpdest16 is opcode0_9=0x0004 ; jump_type=1 & reg24_25 & jmpdest16 { + I = 1; + reg24_25 = inst_next; + call jmpdest16; +} + +:MOVR reg3_5, reg0_2 is opcode6_9=0x0002 & reg0_2 & reg3_5 & checkbranch { + reg0_2 = reg3_5; + resultFlags(reg0_2); + build checkbranch; +} + +:MVI addr16, reg0_2 is opcode3_9=0x0050 & reg0_2 & checkbranch ; addr16 { + local ptr:2 = addr16; + reg0_2 = *(*:2 ptr); + build checkbranch; +} + +:MVI@ impliedval16, reg0_2 is opcode6_9=0x000A & reg0_2 & impliedval16 & checkbranch { + reg0_2 = impliedval16; + build checkbranch; +} + +:MVO reg0_2, addr16 is opcode3_9=0x0048 & reg0_2 ; addr16 { + local ptr:2 = addr16; + *ptr = reg0_2; +} + +:MVO@ reg0_2, reg3_5 is opcode6_9=0x0009 & reg0_2 & reg3_5 & (reg3_5=4 | reg3_5=5) & checkbranch { + local ptr:2 = reg3_5; + *ptr = reg0_2; + reg3_5 = reg3_5 + 1; + build checkbranch; +} + +:MVO@ reg0_2, reg3_5 is opcode6_9=0x0009 & reg0_2 & reg3_5 & checkbranch { + local ptr:2 = reg3_5; + *ptr = reg0_2; + build checkbranch; +} + +:MVOI reg0_2 is opcode3_9=0x004F & reg0_2 ; imm16 { + local tmp:2 = inst_start + 2; + *tmp = reg0_2; +} + +:NEGR reg0_2 is opcode3_9=0x0004 & reg0_2 & regval0_2 & checkbranch { + local tmp = regval0_2 ^ 0xFFFF; + local tmpC = carry(tmp, 1); + local tmpO = scarry(tmp, 1); + reg0_2 = -regval0_2; + C = tmpC; + O = tmpO; + resultFlags(reg0_2); + build checkbranch; +} + +:NOP is opcode1_9=0x001A { +} + +:NOPP is opcode6_9=0x0008 & branch_external=0 & branch_condition=8 ; imm16 { +} + +:PSHR reg0_2 is opcode6_9=0x0009 & reg0_2 & reg3_5 & reg3_5=6 { + local ptr:2 = reg3_5; + *ptr = reg0_2; + reg3_5 = reg3_5 + 1; +} + +:PULR reg0_2 is opcode6_9=0x000A & impliedval16 & reg0_2 & reg3_5=6 { + reg0_2 = impliedval16; +} + +:RSWD reg0_2 is opcode3_9=0x0007 & reg0_2 { + C = (reg0_2 & 0b00001000) != 0; + O = (reg0_2 & 0b00010000) != 0; + Z = (reg0_2 & 0b00100000) != 0; + S = (reg0_2 & 0b01000000) != 0; +} + +:SDBD is opcode0_9=0x0001 [ doublebyte=1; globalset(inst_next, doublebyte); ] { +} + +:SETC is opcode0_9=0x0007 { + C = 1; +} + +:SIN is opcode1_9=0x001B { + SoftwareInterrupt(); +} + +:SUB addr16, reg0_2 is opcode3_9=0x0060 & reg0_2 & regval0_2 & checkbranch ; addr16 { + local ptr:2 = addr16; + subtraction(reg0_2, regval0_2, *:2 ptr); + build checkbranch; +} + +:SUB@ impliedval16, reg0_2 is opcode6_9=0x000C & reg0_2 & regval0_2 & checkbranch & impliedval16 { + subtraction(reg0_2, regval0_2, impliedval16); + build checkbranch; +} + +:SUBR reg3_5, reg0_2 is opcode6_9=0x0004 & reg3_5 & reg0_2 & regval0_2 & checkbranch { + subtraction(reg0_2, regval0_2, reg3_5); + build checkbranch; +} + +:TCI is opcode0_9=0x0005 { + TerminateCurrentInterrupt(); +} + +:TSTR reg0_2 is opcode6_9=0x0002 & reg0_2 & (target0_2=target3_5) { + resultFlags(reg0_2); +} + +:XOR addr16, reg0_2 is opcode3_9=0x0078 & reg0_2 & regval0_2 & checkbranch ; addr16 { + local ptr:2 = addr16; + reg0_2 = regval0_2 ^ *:2 ptr; + resultFlags(reg0_2); + build checkbranch; +} + +:XOR@ impliedval16, reg0_2 is opcode6_9=0x000F & reg0_2 & regval0_2 & checkbranch & impliedval16 { + reg0_2 = regval0_2 ^ impliedval16; + resultFlags(reg0_2); + build checkbranch; +} + +:XORR reg3_5, reg0_2 is opcode6_9=0x0007 & reg3_5 & reg0_2 & regval0_2 & checkbranch { + reg0_2 = regval0_2 ^ reg3_5; + resultFlags(reg0_2); + build checkbranch; +} + +:RLC reg0_2, 1 is opcode3_9=0x000A & reg0_2 & regval0_2 & checkbranch { + local tmpC = (regval0_2 & 0x8000) != 0; + local tmpS = (regval0_2 & 0x4000) != 0; + reg0_2 = (regval0_2 << 1) + zext(C); + C = tmpC; + S = tmpS; + Z = reg0_2 == 0; + build checkbranch; +} + +:RRC reg0_2, 1 is opcode3_9=0x000E & reg0_2 & regval0_2 & checkbranch { + local tmpC = (regval0_2 & 0x0001) != 0; + local tmpS = (regval0_2 & 0x0100) != 0; + reg0_2 = (regval0_2 >> 1) | (zext(C) << 15); + C = tmpC; + S = tmpS; + Z = reg0_2 == 0; + build checkbranch; +} + +:SAR reg0_2, 1 is opcode3_9=0x000D & reg0_2 & regval0_2 & checkbranch { + local tmpS = (regval0_2 & 0x0100) != 0; + reg0_2 = regval0_2 s>> 1; + S = tmpS; + Z = reg0_2 == 0; + build checkbranch; +} + +:SARC reg0_2, 1 is opcode3_9=0x000F & reg0_2 & regval0_2 & checkbranch { + local tmpC = (regval0_2 & 0x0001) != 0; + local tmpS = (regval0_2 & 0x0100) != 0; + reg0_2 = regval0_2 s>> 1; + C = tmpC; + S = tmpS; + Z = reg0_2 == 0; + build checkbranch; +} + +:SLL reg0_2, 1 is opcode3_9=0x0009 & reg0_2 & regval0_2 & checkbranch { + local tmpS = (regval0_2 & 0x4000) != 0; + reg0_2 = regval0_2 << 1; + S = tmpS; + Z = reg0_2 == 0; + build checkbranch; +} + +:SLLC reg0_2, 1 is opcode3_9=0x000B & reg0_2 & regval0_2 & checkbranch { + local tmpC = (regval0_2 & 0x8000) != 0; + local tmpS = (regval0_2 & 0x4000) != 0; + reg0_2 = regval0_2 << 1; + C = tmpC; + S = tmpS; + Z = reg0_2 == 0; + build checkbranch; +} + +:SLR reg0_2, 1 is opcode3_9=0x000C & reg0_2 & regval0_2 & checkbranch { + local tmpS = (regval0_2 & 0x0100) != 0; + reg0_2 = regval0_2 >> 1; + S = tmpS; + Z = reg0_2 == 0; + build checkbranch; +} + +:SWAP reg0_2, 1 is opcode3_9=0x0008 & reg0_2 & regval0_2 & checkbranch { + local tmpS = (regval0_2 & 0x8000) != 0; + local tmp = (regval0_2 << 8) & 0xFF00; + reg0_2 = tmp | ((regval0_2 >> 8) & 0x00FF); + S = tmpS; + build checkbranch; +} + +with : operation_size=1 { + +:RLC reg0_2, 2 is opcode3_9=0x000A & reg0_2 & regval0_2 & checkbranch { + local tmpC = (regval0_2 & 0x8000) != 0; + local tmpO = (regval0_2 & 0x4000) != 0; + local tmpS = (regval0_2 & 0x2000) != 0; + reg0_2 = (regval0_2 << 2) + (zext(C) << 1) + zext(O); + C = tmpC; + O = tmpO; + S = tmpS; + Z = reg0_2 == 0; + build checkbranch; +} + +:RRC reg0_2, 2 is opcode3_9=0x000E & reg0_2 & regval0_2 & checkbranch { + local tmpC = (regval0_2 & 0x0001) != 0; + local tmpO = (regval0_2 & 0x0002) != 0; + local tmpS = (regval0_2 & 0x0200) != 0; + reg0_2 = (regval0_2 >> 2) | (zext(C) << 14) | (zext(O) << 15); + C = tmpC; + O = tmpO; + S = tmpS; + Z = reg0_2 == 0; + build checkbranch; +} + +:SAR reg0_2, 2 is opcode3_9=0x000D & reg0_2 & regval0_2 & checkbranch { + local tmpS = (regval0_2 & 0x0200) != 0; + reg0_2 = regval0_2 s>> 2; + S = tmpS; + Z = reg0_2 == 0; + build checkbranch; +} + +:SARC reg0_2, 2 is opcode3_9=0x000F & reg0_2 & regval0_2 & checkbranch { + local tmpC = (regval0_2 & 0x0001) != 0; + local tmpO = (regval0_2 & 0x0002) != 0; + local tmpS = (regval0_2 & 0x0200) != 0; + reg0_2 = regval0_2 s>> 2; + C = tmpC; + O = tmpO; + S = tmpS; + Z = reg0_2 == 0; + build checkbranch; +} + +:SLL reg0_2, 2 is opcode3_9=0x0009 & reg0_2 & regval0_2 & checkbranch { + local tmpS = (regval0_2 & 0x2000) != 0; + reg0_2 = regval0_2 << 2; + S = tmpS; + Z = reg0_2 == 0; + build checkbranch; +} + +:SLLC reg0_2, 2 is opcode3_9=0x000B & reg0_2 & regval0_2 & checkbranch { + local tmpC = (regval0_2 & 0x8000) != 0; + local tmpO = (regval0_2 & 0x4000) != 0; + local tmpS = (regval0_2 & 0x2000) != 0; + reg0_2 = regval0_2 << 2; + C = tmpC; + O = tmpO; + S = tmpS; + Z = reg0_2 == 0; + build checkbranch; +} + +:SLR reg0_2, 2 is opcode3_9=0x000C & reg0_2 & regval0_2 & checkbranch { + local tmpS = (regval0_2 & 0x0200) != 0; + reg0_2 = regval0_2 >> 2; + S = tmpS; + Z = reg0_2 == 0; + build checkbranch; +} + +:SWAP reg0_2, 2 is opcode3_9=0x0008 & reg0_2 & regval0_2 & checkbranch { + local tmpS = (regval0_2 & 0x0080) != 0; + reg0_2 = (regval0_2 << 8) | (regval0_2 & 0x00FF); + S = tmpS; + build checkbranch; +} + +} + +:ADDI "#"imm16, reg0_2 is opcode3_9=0x005F & reg0_2 & regval0_2 & checkbranch ; imm16 { + addition(reg0_2, regval0_2, imm16); + build checkbranch; +} + +:ANDI "#"imm16, reg0_2 is opcode3_9=0x0077 & reg0_2 & regval0_2 & checkbranch ; imm16 { + reg0_2 = reg0_2 & imm16; + resultFlags(reg0_2); + build checkbranch; +} + +:CMPI "#"imm16, reg0_2 is opcode3_9=0x006F & reg0_2 ; imm16 { + comparison(reg0_2, imm16); +} + +:MVII "#"imm16, reg0_2 is opcode3_9=0x0057 & reg0_2 & checkbranch ; imm16 { + reg0_2 = imm16; + build checkbranch; +} + +:SUBI "#"imm16, reg0_2 is opcode3_9=0x0067 & reg0_2 & regval0_2 & checkbranch ; imm16 { + subtraction(reg0_2, regval0_2, imm16); + build checkbranch; +} + +:XORI "#"imm16, reg0_2 is opcode3_9=0x007F & reg0_2 & regval0_2 & checkbranch ; imm16 { + reg0_2 = regval0_2 ^ imm16; + resultFlags(reg0_2); + build checkbranch; +} + +with : doublebyte=1 { + +:ADDI "#"splitimm16, reg0_2 is opcode3_9=0x005F & reg0_2 & regval0_2 & checkbranch ; splitimm16 { + addition(reg0_2, regval0_2, splitimm16); + build checkbranch; +} + +:ANDI "#"splitimm16, reg0_2 is opcode3_9=0x0077 & reg0_2 & regval0_2 & checkbranch ; splitimm16 { + reg0_2 = regval0_2 & splitimm16; + resultFlags(reg0_2); + build checkbranch; +} + +:CMPI "#"splitimm16, reg0_2 is opcode3_9=0x006F & reg0_2 ; splitimm16 { + comparison(reg0_2, splitimm16); +} + +:MVII "#"splitimm16, reg0_2 is opcode3_9=0x0057 & reg0_2 & checkbranch ; splitimm16 { + reg0_2 = splitimm16; + build checkbranch; +} + +:SUBI "#"splitimm16, reg0_2 is opcode3_9=0x0067 & reg0_2 & regval0_2 & checkbranch ; splitimm16 { + subtraction(reg0_2, regval0_2, splitimm16); + build checkbranch; +} + +:XORI "#"splitimm16, reg0_2 is opcode3_9=0x007F & reg0_2 & regval0_2 & checkbranch ; splitimm16 { + reg0_2 = regval0_2 ^ splitimm16; + resultFlags(reg0_2); + build checkbranch; +} + +} diff --git a/python/icicle/Ghidra/Processors/CR16/data/languages/CR16.cspec b/python/icicle/Ghidra/Processors/CR16/data/languages/CR16.cspec new file mode 100644 index 0000000..3def084 --- /dev/null +++ b/python/icicle/Ghidra/Processors/CR16/data/languages/CR16.cspec @@ -0,0 +1,146 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/CR16/data/languages/CR16.ldefs b/python/icicle/Ghidra/Processors/CR16/data/languages/CR16.ldefs new file mode 100644 index 0000000..bbaafd2 --- /dev/null +++ b/python/icicle/Ghidra/Processors/CR16/data/languages/CR16.ldefs @@ -0,0 +1,30 @@ + + + + + + National Semiconductor's CompactRISC CR16C little endian + + + diff --git a/python/icicle/Ghidra/Processors/CR16/data/languages/CR16.opinion b/python/icicle/Ghidra/Processors/CR16/data/languages/CR16.opinion new file mode 100644 index 0000000..546f96d --- /dev/null +++ b/python/icicle/Ghidra/Processors/CR16/data/languages/CR16.opinion @@ -0,0 +1,5 @@ + + + + + diff --git a/python/icicle/Ghidra/Processors/CR16/data/languages/CR16.pspec b/python/icicle/Ghidra/Processors/CR16/data/languages/CR16.pspec new file mode 100644 index 0000000..97c7b83 --- /dev/null +++ b/python/icicle/Ghidra/Processors/CR16/data/languages/CR16.pspec @@ -0,0 +1,5 @@ + + + + + diff --git a/python/icicle/Ghidra/Processors/CR16/data/languages/CR16B.sinc b/python/icicle/Ghidra/Processors/CR16/data/languages/CR16B.sinc new file mode 100644 index 0000000..ce6664c --- /dev/null +++ b/python/icicle/Ghidra/Processors/CR16/data/languages/CR16B.sinc @@ -0,0 +1,400 @@ +# CR16B + + +# TODO: instructions not implemented + + +# Basic ================================================================================ + +# define endian=big; # Defined in file that includes this file +define alignment=2; + +define space ram type=ram_space size=3 default; +define space register type=register_space size=2; + +# Registers ============================================================================ + + + +define register offset=0 size=2 [ + R0 R1 R2 R3 R4 R5 R6 R7 + R8 R9 R10 R11 R12_L R12_H R13_L R13_H + RA_L RA_H SP_L _ +]; + + + + +# Fields ================================================================================= + + +define token instr(16) + b0=(0,0) # bit0 + op1=(1,4) # operand1 + op2=(5,8) # operand2 + opcode1=(9,12) # opcode1 + i=(13,13) # integer operation length bit: i=0=8bit, i=1=16bit + opcode2=(14,15) # opcode2 + + op1_b02=(1,3) # bits 0,1,2 of op1 + op1_b12=(2,3) # bits 1,2 of op1 + + op2_b23=(7,8) # bits 2,3 of op2 + op2_b12=(6,7) # bits 1,2 of op2 + + opcode1_b23=(11,12) # bits 2,3 of opcode1 + opcode1_b13=(10,12) # bits 1,2,3 of opcode1 + + ; + + +# Context variables ==================================================== + + +# Attach variables ===================================================== + +# attach normal registers +#attach variables [ N_0 M_0 ] [ +# r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 +#]; + + + + + +# Constructors ======================================================================= + +# MOVES + +:MOV is opcode2=1 & i & opcode1=0xc & op2 & op1 & b0=1 { + +} +:MOV is opcode2=0 & i & opcode1=0xc & op2 & op1 & b0 { + +} + +:MOVXB is opcode2=1 & i=1 & opcode1=0x4 & op2 & op1 & b0=0 { + +} +:MOVZB is opcode2=1 & i=1 & opcode1=0x5 & op2 & op1 & b0=0 { + +} +:MOVD is opcode2=1 & i=1 & opcode1_b13=1 & op2 & op1 & b0=0 { + +} + + +# ARITHMETIC + +:ADD is opcode2=1 & i & opcode1=0 & op2 & op1 & b0=1 { + +} +:ADD is opcode2=0 & i & opcode1=0 & op2 & op1 & b0 { + +} + +:ADDU is opcode2=1 & i & opcode1=1 & op2 & op1 & b0=1 { + +} +:ADDU is opcode2=0 & i & opcode1=1 & op2 & op1 & b0 { + +} + +:ADDC is opcode2=1 & i & opcode1=9 & op2 & op1 & b0=1 { + +} +:ADDC is opcode2=0 & i & opcode1=9 & op2 & op1 & b0 { + +} + + +:MUL is opcode2=1 & i & opcode1=3 & op2 & op1 & b0=1 { + +} +:MUL is opcode2=0 & i & opcode1=3 & op2 & op1 & b0 { + +} + +:MULSB is opcode2=1 & i=1 & opcode1=0 & op2 & op1 & b0=0 { + +} +:MULSW is opcode2=1 & i=1 & opcode1=1 & op2 & op1 & b0=0 { + +} +:MULUW is opcode2=1 & i=1 & opcode1=0xf & op2 & op1_b12=0 & b0=0 { + +} + +:SUB is opcode2=1 & i & opcode1=0xf & op2 & op1 & b0=1 { + +} +:SUB is opcode2=0 & i & opcode1=0xf & op2 & op1 & b0 { + +} + +:SUBC is opcode2=1 & i & opcode1=0xd & op2 & op1 & b0=1 { + +} +:SUBC is opcode2=0 & i & opcode1=0xd & op2 & op1 & b0 { + +} + + +# INTEGER COMPARISON + +:CMP is opcode2=1 & i & opcode1=0x7 & op2 & op1 & b0=1 { + +} +:CMP is opcode2=0 & i & opcode1=0x7 & op2 & op1 & b0 { + +} + +:BEQ0 is opcode2=0 & i & opcode1=0xa & op2_b12=0 & op1 & b0=1 { + +} + +:BEQ1 is opcode2=0 & i & opcode1=0xa & op2_b12=1 & op1 & b0=1 { + +} + +:BNE0 is opcode2=0 & i & opcode1=0xa & op2_b12=2 & op1 & b0=1 { + +} + +:BNE1 is opcode2=0 & i & opcode1=0xa & op2_b12=3 & op1 & b0=1 { + +} + + + +# LOGICAL / BOOLEAN +:AND is opcode2=1 & i & opcode1=0x8 & op2 & op1 & b0=1 { + +} +:AND is opcode2=0 & i & opcode1=0x8 & op2 & op1 & b0 { + +} + +:OR is opcode2=1 & i & opcode1=0xe & op2 & op1 & b0=1 { + +} +:OR is opcode2=0 & i & opcode1=0xe & op2 & op1 & b0 { + +} + +:S is opcode2=1 & i & opcode1=0x7 & op2 & op1 & b0=0 { + +} + +:XOR is opcode2=1 & i & opcode1=0x6 & op2 & op1 & b0=1 { + +} +:XOR is opcode2=0 & i & opcode1=0x6 & op2 & op1 & b0 { + +} + +# SHIFTS +:ASHU is opcode2=1 & i & opcode1=0x4 & op2 & op1 & b0=1 { + +} +:ASHU is opcode2=0 & i & opcode1=0x4 & op2 & op1 & b0 { + +} + +:LSH is opcode2=1 & i & opcode1=0x5 & op2 & op1 & b0=1 { + +} +:LSH is opcode2=0 & i & opcode1=0x5 & op2 & op1 & b0 { + +} + +# BITS +:TBIT is opcode2=1 & i=1 & opcode1=0xb & op2 & op1 & b0=1 { + +} +:TBIT is opcode2=0 & i=1 & opcode1=0xb & op2 & op1 & b0 { + +} + +:TBIT is opcode2=1 & i & opcode1=2 & op2_b12=2 & op1 & b0=1 { + +} +:TBIT is opcode2=0 & i & opcode1=2 & op2_b12=2 & op1 & b0=1 { + +} +:TBIT is opcode2=0 & i & opcode1=2 & op2_b12=2 & op1 & b0=0 { + +} + +:CBIT is opcode2=1 & i & opcode1=2 & op2_b12=0 & op1 & b0=1 { + +} +:CBIT is opcode2=0 & i & opcode1=2 & op2_b12=0 & op1 & b0=1 { + +} +:CBIT is opcode2=0 & i & opcode1=2 & op2_b12=0 & op1 & b0=0 { + +} + +:SBIT is opcode2=1 & i & opcode1=2 & op2_b12=1 & op1 & b0=1 { + +} +:SBIT is opcode2=0 & i & opcode1=2 & op2_b12=1 & op1 & b0=1 { + +} +:SBIT is opcode2=0 & i & opcode1=2 & op2_b12=1 & op1 & b0=0 { + +} + +# PROCESSOR REGISTER MANIPULATION +:LPR is opcode2=1 & i=1 & opcode1=8 & op2 & op1 & b0=0 { + +} +:SPR is opcode2=1 & i=1 & opcode1=9 & op2 & op1 & b0=0 { + +} + +# JUMPS / LINKS +:Bcond is opcode2=1 & i=0 & opcode1 & op2 & op1 & b0=0 { + +} +:Bcond is opcode2=0 & i=0 & opcode1=0xa & op2 & op1_b02=7 & b0=0 { + +} +:Bcond is opcode2=1 & i=1 & opcode1=0xa & op2 & op1 & b0=0 { + +} + +:BAL is opcode2=0 & i=1 & opcode1=0xa & op2 & op1_b02=7 & b0=0 { + +} +:BAL is opcode2=1 & i=1 & opcode1=0xb & op2 & op1 & b0=0 { + +} + +:BR is opcode2=1 & i=0 & opcode1 & op2=0xe & op1 & b0=0 { + +} +:BR is opcode2=0 & i=0 & opcode1=0xa & op2=0xe & op1_b02=7 & b0=0 { + +} +:BR is opcode2=1 & i=1 & opcode1=0xa & op2=0xe & op1 & b0=0 { + +} + +:EXCP is opcode2=1 & i=1 & opcode1=0xd & op2=0xf & op1 & b0=0 { + +} + +:Jcond is opcode2=1 & i=0 & opcode1=0xa & op2 & op1 & b0=1 { + +} +:Jcond is opcode2=0 & i=0 & opcode1=0xb & op2 & op1 & b0=1 { + +} + +:JAL is opcode2=1 & i=1 & opcode1=0xa & op2 & op1 & b0=1 { + +} +:JAL is opcode2=0 & i=0 & opcode1=0xb & op2 & op1 & b0=0 { + +} + +:JUMP is opcode2=1 & i=0 & opcode1=0xa & op2=0xe & op1 & b0=1 { + +} +:JUMP is opcode2=0 & i=0 & opcode1=0xb & op2=0xe & op1 & b0=1 { + +} + +:RETX is opcode2=1 & i=1 & opcode1=0xc & op2=0xf & op1=0xf & b0=0 { + +} + +:PUSH is opcode2=1 & i=1 & opcode1=0x6 & op2_b23=0 & op1 & b0=0 { + +} + +:POP is opcode2=1 & i=1 & opcode1=0x6 & op2_b23=1 & op1 & b0=0 { + +} + +:POPRET is opcode2=1 & i=1 & opcode1=0x6 & op2_b23=2 & op1 & b0=0 { + +} + +:POPRET is opcode2=1 & i=1 & opcode1=0x6 & op2_b23=3 & op1 & b0=0 { + +} + + +# LOAD / STORE + +:LOAD is opcode2=2 & i & opcode1 & op2 & op1 & b0 { + +} +:LOAD is opcode2=2 & i & opcode1_b23=2 & op2 & op1 & b0=1 { + +} +:LOAD is opcode2=2 & i & opcode1_b23=3 & op2 & op1 & b0=1 { + +} +:LOAD is opcode2=2 & i & opcode1_b23=3 & op2 & op1=0xf & b0=1 { + +} + +:LOADM is opcode2=1 & i=1 & opcode1=0xf & op2_b23=0 & op1=2 & b0=0 { + +} + +:STORE is opcode2=3 & i & opcode1 & op2 & op1 & b0 { + +} +:STORE is opcode2=3 & i & opcode1_b23=2 & op2 & op1 & b0=1 { + +} +:STORE is opcode2=3 & i & opcode1_b23=3 & op2 & op1 & b0=1 { + +} +:STORE is opcode2=3 & i & opcode1_b23=3 & op2 & op1=0xf & b0=1 { + +} +:STORE is opcode2=1 & i & opcode1=2 & op2_b12=3 & op1 & b0=1 { + +} +:STORE is opcode2=0 & i & opcode1=2 & op2_b12=3 & op1 & b0=1 { + +} +:STORE is opcode2=0 & i & opcode1=2 & op2_b12=3 & op1 & b0=0 { + +} + +:STORM is opcode2=1 & i=1 & opcode1=0xf & op2_b23=1 & op1=2 & b0=0 { + +} + + +# MISC + +:DI is opcode2=1 & i=1 & opcode1=0xe & op2=0xe & op1=0xf & b0=0 { + +} +:EI is opcode2=1 & i=1 & opcode1=0xe & op2=0xf & op1=0xf & b0=0 { + +} +:NOP is opcode2=0 & i=0 & opcode1=0x1 & op2=0 & op1=0 & b0=0 { + +} +:WAIT is opcode2=1 & i=1 & opcode1=0xf & op2=0xf & op1=0xf & b0=0 { + +} +:EIWAIT is opcode2=1 & i=1 & opcode1=0xf & op2=0xf & op1=0x3 & b0=0 { + +} + + + + + + + diff --git a/python/icicle/Ghidra/Processors/CR16/data/languages/CR16B.slaspec b/python/icicle/Ghidra/Processors/CR16/data/languages/CR16B.slaspec new file mode 100644 index 0000000..7b01a4a --- /dev/null +++ b/python/icicle/Ghidra/Processors/CR16/data/languages/CR16B.slaspec @@ -0,0 +1,4 @@ + +define endian=little; + +@include "CR16B.sinc" diff --git a/python/icicle/Ghidra/Processors/CR16/data/languages/CR16C.sinc b/python/icicle/Ghidra/Processors/CR16/data/languages/CR16C.sinc new file mode 100644 index 0000000..f70a457 --- /dev/null +++ b/python/icicle/Ghidra/Processors/CR16/data/languages/CR16C.sinc @@ -0,0 +1,2315 @@ +# This module defines CR16C + + +# NOTE: Have assumed for now CFG.SR = 0 + +# sizes: +# B = byte = 1 byte +# W = word = 2 bytes +# D = doubleword = 4 bytes + + +# Basic ===================================================================== + +define alignment=2; + +define space ram type=ram_space size=4 default; +define space register type=register_space size=2; + +# Registers ================================================================== + +# - When CFG.SR is not set, register pairs are defined as follows: +# (R1,R0), (R2,R1) ... (R11,R10), (R12_L, R11) +# R12, R13, RA and SP are double-word registers for direct storage of +# addresses greater than 16 bits. +# +# - The most significant 8 bits of ISP and the least significant bit of ISP +# are forced to 0 + +# General purpose registers +# NOTE: RA_L==RA and SP_L==SP +# NOTE: R12_H, R13_H, RA_H don't actually exist as named registers +# (name needed for push/pop instructions implementation only) +define register offset=0 size=2 [ + R0 R1 R2 R3 R4 R5 R6 R7 + R8 R9 R10 R11 R12_L R12_H R13_L R13_H + RA_L RA_H SP_L SP_H +]; + +define register offset=0 size=4 [ + R1R0 R3R2 R5R4 R7R6 R9R8 R11R10 R12 R13 RA SP +]; + +define register offset=2 size=4 [ + R2R1 R4R3 R6R5 R8R7 R10R9 R12LR11 +]; + +# Dedicated address registers +define register offset=50 size=4 [ PC ]; +define register offset=60 size=2 [ ISPH ISPL USPH USPL INTBASEH INTBASEL ]; +define register offset=60 size=4 [ ISP USP INTBASE ]; + +# Processor Status register +define register offset=80 size=2 [ PSR ]; +#define register offset=90 size=1 [ C T L U F Z N E P I ]; # cond flags +@define C "PSR[0,1]" +@define T "PSR[1,1]" +@define L "PSR[2,1]" +@define U "PSR[3,1]" +@define F "PSR[5,1]" +@define Z "PSR[6,1]" +@define N "PSR[7,1]" +@define E "PSR[9,1]" +@define P "PSR[10,1]" +@define I "PSR[11,1]" + +# Configuration register +define register offset=100 size=2 [ CFG ]; + +# Debug registers +define register offset=110 size=2 [ DBS DSR DCRH DCRL CAR0H CAR0L CAR1H CAR1L ]; +define register offset=114 size=4 [ DCR CAR0 CAR1 ]; + +# these don't actually exist - they are for prd definition (size=4) +define register offset=130 size=4 [ DBS_1 DSR_1 CFG_1 PSR_1 ]; + + +# Fields ====================================================================== + +define token word1(16) + hi = (8,15) # opcode8 + lo = (0,7) # + op = (0,15) # opcode16 + op12 = (4,15) # opcode12 + op9 = (7,15) # opcode9 + op7 = (9,15) # opcode7 + op7p3 = (8,8) # p3 for opcode7 +# op10 = (6,15) # opcode10 + op4 = (12,15) # opcode4 + lo1 = (0,3) + op13 = (3,15) # opcode13 + op11 = (5,15) + + dst = (0,3) # register + src = (4,7) + src1 = (0,3) + reg0 = (0,3) + reg1 = (0,3) + reg2 = (0,3) + reg3 = (0,3) + reg4 = (0,3) + reg5 = (0,3) + reg6 = (0,3) + reg7 = (0,3) + dst1 = (4,7) + + rp_dst = (0,3) # register pair + rp_src = (4,7) + rp_dst2 = (4,7) + rp_src2 = (0,3) + + prp_src1 = (0,3) + prp_dst1 = (0,3) + + cond = (4,7) + + x4 = (12,15) # generic, nibble 4 + x3 = (8,11) + x2 = (4,7) + x1 = (0,3) + + x2s = (4,6) + x3s = (8,11) signed + b4_8 = (4,8) + b4_7 = (4,7) + b4_6 = (4,6) + b_ra = (7,7) # RA bit for push/pop, fmt 14 + b_prp = (3,3) # prp bit, fmt 18 + b0_2 = (0,2) # fmt 6 +; + +define token word2(16) + w2 = (0,15) + n4 = (12,15) # nibble 4, sometimes an opcode extension + n3 = (8,11) + n2 = (4,7) + n1 = (0,3) + w2_b0 = (0,0) + w2_b1_15 = (1,15) signed + w2_hi = (8,15) + + prd = (4,7) # processor registers + pr = (4,7) + + rp_src3 = (0,3) # register pairs + rp_dst3 = (0,3) + rp_src6 = (4,7) + rp_dst6 = (4,7) + rp_dst7 = (8,11) + + src2 = (0,3) # registers + dst2 = (0,3) + src5 = (4,7) +; + +define token word3(16) + w3 = (0,15) + w3_b0 = (0,0) + w3_b1_15 = (1,15) +; + +# used this token when operands spanned across 2 words +# | byte1 byte0 byte3 byte2 | +define token doubleword(32) + dw = (0,31) + dw_w1 = (0,15) signed + dw_w2 = (16,31) + n8 = (12,15) # nibble 4, sometimes an opcode extension + n7 = (8,11) + n6 = (4,7) # (cond) + n5 = (0,3) + n5s = (0,3) signed + b1_15 = (17,31) + b0_15 = (16,31) + dw_lo = (0,7) signed # for fmt 5 + dw_hi = (8,15) # (op8) + dw_op7 = (9,15) # (op7) + dw_op9 = (7,15) # (op9) + op10 = (6,15) # (opcode 10) + b_rs = (8,8) # for fmt 13 + dw_b4_6 = (4,6) + dw_b_prp = (3,3) # for fmt 17 + f17a = (16,19) # for fmt 17 p3 + f17b = (4,5) + f17c = (30,31) + f17d = (24,29) + dw_n2 = (20,23) # fmt 17, p2, 4-bits + dw_n2b = (20,22) # fmt 17, p2, 3-bit version + + rp_dst4 = (4,7) + rp_src4 = (4,7) + rp_dst5 = (0,3) + rp_src5 = (0,3) + dst3 = (4,7) + src3 = (4,7) + dst4 = (0,3) + src4 = (0,3) + prp_dst = (0,3) + prp_src = (0,3) +; + + +# Attach variables ===================================================== + +# normal registers +attach variables [ src dst src1 dst1 src2 dst2 src3 dst3 src4 dst4 src5 ] [ + R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12_L R13_L RA_L SP_L +]; + +# register pairs +attach variables [ rp_src rp_dst rp_src2 rp_dst2 rp_src3 rp_dst3 + rp_src4 rp_dst4 rp_src5 rp_dst5 rp_src6 rp_dst6 rp_dst7 ] [ + R1R0 R2R1 R3R2 R4R3 R5R4 R6R5 R7R6 R8R7 + R9R8 R10R9 R11R10 R12LR11 R12 R13 RA SP +]; + +attach variables [ prp_src prp_dst prp_src1 prp_dst1 ] [ # rrp + R1R0 R3R2 R5R4 R7R6 R9R8 R11R10 R4R3 R6R5 + R1R0 R3R2 R5R4 R7R6 R9R8 R11R10 R4R3 R6R5 +]; + +# processor registers +attach variables [ pr ] [ + DBS DSR DCRL DCRH CAR0L CAR0H CAR1L CAR1H CFG PSR INTBASEL INTBASEH ISPL ISPH USPL USPH +]; + +attach variables [ prd ] [ + DBS_1 DSR_1 DCR _ CAR0 _ CAR1 _ CFG_1 PSR_1 INTBASE _ ISP _ USP _ +]; + +# Pseudo instructions ================================================= + +define pcodeop trap; +define pcodeop suspend; + +# Macros ============================================================== + +# Flags set by add instructions +macro addflags(op1, op2) { + $(C) = (carry(op1, op2)); # Check for carry + $(F) = (scarry(op1, op2)); # Check for overflow +} +# Flags set by add instructions (3 operands) +macro addflags2(op1, op2, op3) { + local tmp = (carry(op1,op2)); # Check for carry + $(C) = (carry(zext(tmp), op3)); + tmp = (scarry(op1,op2)); # Check for overflow + $(F) = (scarry(zext(tmp), op3)); +} +# Flags set by sub instructions +macro subflags(op1, op2) { + $(C) = (op1 < op2); # Check for borrow + $(F) = sborrow(op1, op2); # Check for overflow +} +# Flags set by sub instructions (3 operands) +macro subflags2(op1, op2, op3) { + $(C) = (op1 < (op2 + op3)); # Check for borrow + local tmp = sborrow(op1, op2); # Check for overflow + $(F) = sborrow(zext(tmp), op3); +} + +# Flags set by the compare instructions +macro compflags(op1, op2) { + $(Z) = (op1 == op2); # Equal comparison + $(N) = (op2 s< op1); # Signed comparison + $(L) = (op2 < op1); # Unsigned comparison +} + +# Operand Display ==================================================== + +imm20: "$"tmp is n5 & dw_w2 [ tmp = (n5 << 16) + dw_w2; ] { export *[const]:3 tmp; } +imm32: "$"tmp is dw_w1 & dw_w2 [ tmp = (dw_w1 << 16) + dw_w2; ] { export *[const]:4 tmp; } +imm4: "$"x2 is x2 { export *[const]:1 x2; } # imm src +imm4: "$"tmp is x2=9 [ tmp = -1; ] { export *[const]:1 tmp; } +imm4a: "$"x2 is x2 { export *[const]:1 x2; } # imm pos +imm4b: "$"n6 is n6 { export *[const]:1 n6; } +imm4c: "$"dw_n2 is dw_n2 { export *[const]:1 dw_n2; } +imm4d: "$"b4_7 is b4_7 { export *[const]:1 b4_7; } # for ash and lsh (signed count) +imm16: "$"w2 is w2 { export *[const]:2 w2; } +imm5: "$"b4_8 is b4_8 { export *[const]:1 b4_8; } # for ash and lsh (signed count) +imm3: "$"b4_6 is b4_6 { export *[const]:1 b4_6; } +imm3b: "$"dw_b4_6 is dw_b4_6 { export *[const]:1 dw_b4_6; } +imm3c: "$"dw_n2b is dw_n2b { export *[const]:1 dw_n2b; } +imm3d: "$"x2s is x2s { export *[const]:1 x2s; } # for ash and lsh (signed count) + +cnt3: "$"tmp is b4_6 [ tmp = b4_6 + 1; ] { export *[const]:1 tmp; } +cnt3b: "$"tmp is b0_2 [ tmp = b0_2 + 1; ] { export *[const]:1 tmp; } + +# If (abs20 > 0xEFFFF) the resulting address is logically ORed with 0xF00000 +# i.e. addresses from 1M-64k to 1M are re-mapped by the core to 16M-64k to 16M. +abs20: tmp is n5=0xf & dw_w2 [ tmp = 0xff0000 | dw_w2; ] { + export *[const]:3 tmp; +} + +abs20: tmp is n5 & dw_w2 [ tmp = (n5 << 16) + dw_w2; ] { + export *[const]:3 tmp; +} + +abs24: "*"tmp is n5 & n7 & b0_15 + [ tmp = (n5 << 20) + (n7 << 16) + (b0_15); ] { export *[const]:4 tmp; } + +# NOTE: disp24 is sign extended to 25 bits - hopefully that doesn't matter here +# TODO: display *+/*- relative to PC? +disp8: "*"tmp is x1 & x3s + [ tmp = (x3s << 5) + (x1 << 1) + inst_start; ] { export *[ram]:4 tmp; } # fmt 21 +disp16: "*"tmp is w2_b1_15 + [ tmp = (w2_b1_15 << 1) + inst_start; ] { export *[ram]:4 tmp; } # fmt 5, 22 +disp24: "*"tmp is n5s & n7 & b1_15 + [ tmp = (n5s << 20) + (n7 << 16) + (b1_15 << 1) + inst_start; ] { export *[ram]:4 tmp; } +disp24b:"*"tmp is dw_lo & b1_15 + [ tmp = (dw_lo << 16) + (b1_15 << 1) + inst_start; ] { export *[ram]:4 tmp; } +disp4c: "*"tmp is x2 + [ tmp = ((x2 + 1) << 1) + inst_start; ] { export *[ram]:4 tmp; } + +# disps not relative to PC +disp4: "*"tmp is x3 [ tmp = (x3 << 1); ] { export *[const]:3 tmp; } +disp4b: "*"x3 is x3 { export *[const]:3 x3; } +disp16b:"*"w2 is w2 { export *[const]:2 w2; } +disp20: "*"tmp is n7 & dw_w2 + [ tmp = (n7 << 16) + dw_w2; ] { export *[const]:3 tmp; } +disp14: "*"tmp is f17a & f17b & f17c & f17d + [ tmp = (f17d << 8) + (f17c << 6) + (f17b << 4) + f17a; ] { export *[const]:3 tmp; } + + +cc: "eq" is cond=0 { local tmp = $(Z); export tmp; } +cc: "ne" is cond=1 { local tmp = !$(Z); export tmp; } +cc: "cs" is cond=2 { local tmp = $(C); export tmp; } +cc: "cc" is cond=3 { local tmp = !$(C); export tmp; } +cc: "hi" is cond=4 { local tmp = $(L); export tmp; } +cc: "ls" is cond=5 { local tmp = !$(L); export tmp; } +cc: "gt" is cond=6 { local tmp = $(N); export tmp; } +cc: "le" is cond=7 { local tmp = !$(N); export tmp; } +cc: "fs" is cond=8 { local tmp = $(F); export tmp; } +cc: "fc" is cond=9 { local tmp = !$(F); export tmp; } +cc: "lo" is cond=10 { local tmp = !$(Z) && !$(L); export tmp; } +cc: "hs" is cond=11 { local tmp = $(Z) || $(L); export tmp; } +cc: "lt" is cond=12 { local tmp = !$(Z) && !$(N); export tmp; } +cc: "ge" is cond=13 { local tmp = $(Z) || $(N); export tmp; } +COND: cc is cc { if (!cc) goto inst_next; } + +cc2: "eq" is n6=0 { local tmp = $(Z); export tmp; } +cc2: "ne" is n6=1 { local tmp = !$(Z); export tmp; } +cc2: "cs" is n6=2 { local tmp = $(C); export tmp; } +cc2: "cc" is n6=3 { local tmp = !$(C); export tmp; } +cc2: "hi" is n6=4 { local tmp = $(L); export tmp; } +cc2: "ls" is n6=5 { local tmp = !$(L); export tmp; } +cc2: "gt" is n6=6 { local tmp = $(N); export tmp; } +cc2: "le" is n6=7 { local tmp = !$(N); export tmp; } +cc2: "fs" is n6=8 { local tmp = $(F); export tmp; } +cc2: "fc" is n6=9 { local tmp = !$(F); export tmp; } +cc2: "lo" is n6=10 { local tmp = !($(Z) && $(L)); export tmp; } +cc2: "hs" is n6=11 { local tmp = $(Z) || $(L); export tmp; } +cc2: "lt" is n6=12 { local tmp = !($(Z) && $(N)); export tmp; } +cc2: "ge" is n6=13 { local tmp = $(Z) || $(N); export tmp; } +COND2: cc2 is cc2 { if (!cc2) goto inst_next; } + + +ra: "RA" is epsilon { } +const1: "0x0" is epsilon { } + +rs: "[R12]" is b_rs=0 { export R12; } +rs: "[R13]" is b_rs=1 { export R13; } + +prp2: "[R12]" is dw_b_prp=0 { export R12; } +prp2: "[R13]" is dw_b_prp=1 { export R13; } + +prp: "[R12]" is b_prp=0 { export R12; } +prp: "[R13]" is b_prp=1 { export R13; } + +cinv1: "[i]" is epsilon { } +cinv2: "[i,u]" is epsilon { } +cinv3: "[d]" is epsilon { } +cinv4: "[d,u]" is epsilon { } +cinv5: "[d,i]" is epsilon { } +cinv6: "[d,i,u]" is epsilon { } + + + +# Constructors =============================================================== + +# MOVES + +# MOVB - move low-order byte only +:MOVB imm4, dst is hi=0x58 & dst & imm4 { + dst = (dst & 0xff00) | (zext(imm4) & 0x00ff); +} +:MOVB imm16, dst is hi=0x58 & x2=11 & dst ; imm16 { + dst = (dst & 0xff00) | (imm16 & 0x00ff); +} +:MOVB src, dst is hi=0x59 & src & dst { + dst = (dst & 0xff00) | (zext(src:1) & 0x00ff); +} + +# MOVD - move doubleword +:MOVD imm20, rp_dst4 is dw_hi=0x05 & rp_dst4 & imm20 { + rp_dst4 = zext(imm20); +} +:MOVD imm32, rp_dst is op12=0x007 & rp_dst ; imm32 { + rp_dst = imm32; +} +:MOVD imm4, rp_dst is hi=0x54 & rp_dst & imm4 { + rp_dst = sext(imm4); +} +:MOVD imm16, rp_dst is hi=0x54 & x2=11 & rp_dst ; imm16 { + rp_dst = sext(imm16); +} +:MOVD rp_src, rp_dst is hi=0x55 & rp_dst & rp_src { + rp_dst = rp_src; +} + +# MOVW - move word +:MOVW imm4, dst is hi=0x5a & dst & imm4 { + dst = sext(imm4); +} +:MOVW imm16, dst is hi=0x5a & x2=11 & dst ; imm16 { + dst = imm16; +} +:MOVW src, dst is hi=0x5b & src & dst { + dst = src; +} + +# MOVXB - move low-order byte of src to word dst with sign extension +:MOVXB src, dst is hi=0x5c & src & dst { + dst = sext(src:1); +} +# MOVXW - move word src to doubleword dst with sign extension +:MOVXW src, rp_dst is hi=0x5e & src & rp_dst { + rp_dst = sext(src); +} + +# MOVZB - move low-order byte of src to word dst with zero extension +:MOVZB src, dst is hi=0x5d & src & dst { + dst = zext(src:1); +} +# MOVZW - move word src to doubleword dst with zero extension +:MOVZW src, rp_dst is hi=0x5f & src & rp_dst { + rp_dst = zext(src); +} + + +# ARITHMETIC + +# ADDB - add low-order byte only +:ADDB imm4, dst is hi=0x30 & dst & imm4 { + addflags(dst:1, imm4); + tmp:1 = dst:1 + imm4; + dst = (dst & 0xff00) + zext(tmp); +} +:ADDB imm16, dst is hi=0x30 & x2=11 & dst ; imm16 { + addflags(dst:1, imm16:1); + tmp:1 = dst:1 + imm16:1; + dst = (dst & 0xff00) + zext(tmp); +} +:ADDB src, dst is hi=0x31 & src & dst { + addflags(dst:1, src:1); + tmp:1 = dst:1 + src:1; + dst = (dst & 0xff00) + zext(tmp); +} + +# ADDCB - add with carry low-order byte only +:ADDCB imm4, dst is hi=0x34 & dst & imm4 { + addflags2(dst:1, imm4, $(C)); + tmp:1 = dst:1 + imm4 + $(C); + dst = (dst & 0xff00) + zext(tmp); +} +:ADDCB imm16, dst is hi=0x34 & x2=11 & dst ; imm16 { + addflags2(dst:1, imm16:1, $(C)); + tmp:1 = dst:1 + imm16:1 + $(C); + dst = (dst & 0xff00) + zext(tmp); +} +:ADDCB src, dst is hi=0x35 & src & dst { + addflags2(dst:1, src:1, $(C)); + tmp:1 = dst:1 + src:1 + $(C); + dst = (dst & 0xff00) + zext(tmp); +} + +# ADDCW - add word with carry +:ADDCW imm4, dst is hi=0x36 & dst & imm4 { + tmp2:2 = sext(imm4); + tmp3:2 = zext($(C)); + addflags2(dst, tmp2, tmp3); + dst = dst + tmp2 + tmp3; +} +:ADDCW imm16, dst is hi=0x36 & x2=11 & dst ; imm16 { + tmp3:2 = zext($(C)); + addflags2(dst, imm16, tmp3); + dst = dst + imm16 + tmp3; +} +:ADDCW src, dst is hi=0x37 & src & dst { + tmp3:2 = zext($(C)); + addflags2(dst, src, tmp3); + dst = dst + src + tmp3; +} + +# ADDD - add doubleword +:ADDD imm20, rp_dst4 is dw_hi=0x04 & rp_dst4 & imm20 { + tmp:4 = zext(imm20); + addflags(tmp, rp_dst4); + rp_dst4 = rp_dst4 + tmp; +} +:ADDD imm32, rp_dst is op12=0x002 & rp_dst ; imm32 { + addflags(imm32, rp_dst); + rp_dst = rp_dst + imm32; +} +:ADDD imm4, rp_dst is hi=0x60 & rp_dst & imm4 { + tmp:4 = sext(imm4); + addflags(tmp, rp_dst); + rp_dst = rp_dst + tmp; +} +:ADDD imm16, rp_dst is hi=0x60 & x2=11 & rp_dst ; imm16 { + tmp:4 = sext(imm16); + addflags(tmp, rp_dst); + rp_dst = rp_dst + tmp; +} +:ADDD rp_src, rp_dst is hi=0x61 & rp_dst & rp_src { + addflags(rp_src, rp_dst); + rp_dst = rp_dst + rp_src; +} + +# ADDUB - add low-order byte only, PSR flags unaffected +:ADDUB imm4, dst is hi=0x2c & dst & imm4 { + tmp:1 = dst:1 + imm4; + dst = (dst & 0xff00) + zext(tmp); +} +:NOP is hi=0x2c & dst=0 & x2=0 { + +} +:ADDUB imm16, dst is hi=0x2c & x2=11 & dst ; imm16 { + tmp:1 = dst:1 + imm16:1; + dst = (dst & 0xff00) + zext(tmp); +} +:ADDUB src, dst is hi=0x2d & src & dst { + tmp:1 = dst:1 + src:1; + dst = (dst & 0xff00) + zext(tmp); +} + +# ADDUW - add word, PSR flags unaffected +:ADDUW imm4, dst is hi=0x2e & dst & imm4 { + tmp:2 = sext(imm4); + dst = dst + tmp; +} +:ADDUW imm16, dst is hi=0x2e & x2=11 & dst ; imm16 { + dst = dst + imm16; +} +:ADDUW src, dst is hi=0x2f & src & dst { + dst = dst + src; +} + +# ADDW - add word +:ADDW imm4, dst is hi=0x32 & dst & imm4 { + tmp:2 = sext(imm4); + addflags(tmp, dst); + dst = dst + tmp; +} +:ADDW imm16, dst is hi=0x32 & x2=11 & dst ; imm16 { + addflags(imm16, dst); + dst = dst + imm16; +} +:ADDW src, dst is hi=0x33 & src & dst { + addflags(src, dst); + dst = dst + src; +} + +# Multiply Signed Q15 Word and Accumulate Long Result +:MACQW src2, src5, rp_dst7 is op=0x0014 ; n4=13 & src2 & src5 & rp_dst7 { + tmp:4 = sext(src2) * sext(src5); # TODO based on what Q15 is, this sext may not be right + rp_dst7 = rp_dst7 + tmp; + +# if (!scarry(rp_dst7, tmp)) goto ; +# rp_dst7 = 0x7fffffff; # overflowed, set to max +# goto ; +# +# if (!sborrow(rp_dst7, tmp)) goto ; +# rp_dst7 = 0x80000000; # underflowed, set to min +# + + # TODO: if scarry(rp_dst7, tmp) then rp_dst7 = 0x? TODO what is Q15 signed fractional format + # if sborrow(rp_dst7, tmp) then rp_dst7 = 0x? +} + +# Unsigned Multiply Word and Accumulate Long Result +:MACUW src2, src5, rp_dst7 is op=0x0014 ; n4=14 & src2 & src5 & rp_dst7 { + tmp:4 = zext(src2) * zext(src5); + rp_dst7 = rp_dst7 + tmp; + + # if scarry(rp_dst7, tmp) then rp_dst7 = 0xffffffff + if (!scarry(rp_dst7, tmp)) goto ; + rp_dst7 = 0xffffffff; # overflowed, set to max + +} + +# Signed Multiply Word and Add Long Result +:MACSW src2, src5, rp_dst7 is op=0x0014 ; n4=15 & src2 & src5 & rp_dst7 { + tmp:4 = sext(src2) * sext(src5); + rp_dst7 = rp_dst7 + tmp; + + # if scarry(rp_dst7, tmp) then rp_dst7 = 0x7fffffff + if (!scarry(rp_dst7, tmp)) goto ; + rp_dst7 = 0x7fffffff; # overflowed, set to max + goto ; + + # if sborrow(rp_dst7, tmp) then rp_dst7 = 0x80000000 + if (!sborrow(rp_dst7, tmp)) goto ; + rp_dst7 = 0x80000000; # underflowed, set to min + +} + +# MULB - multiply byte +:MULB imm4, dst is hi=0x64 & dst & imm4 { + tmp:1 = dst:1 * imm4; + dst = (dst & 0xff00) + zext(tmp); +} +:MULB imm16, dst is hi=0x64 & x2=11 & dst ; imm16 { + tmp:1 = dst:1 * imm16:1; + dst = (dst & 0xff00) + zext(tmp);} +:MULB src, dst is hi=0x65 & src & dst{ + tmp:1 = dst:1 * src:1; + dst = (dst & 0xff00) + zext(tmp); +} + +# Signed Multiply Byte, Word Result +:MULSB src, dst is hi=0x0b & src & dst { + dst = sext(src:1) * sext(dst:1); +} + +# Signed Multiply Word, Long Result +:MULSW src, rp_dst is hi=0x62 & src & rp_dst { + rp_dst = sext(src) * sext(rp_dst:2); +} + +# Unsigned Multiply Word, Long Result +:MULUW src, rp_dst is hi=0x63 & src & rp_dst { + rp_dst = zext(src) * zext(rp_dst:2); +} + +# MULW - multiply word +:MULW imm4, dst is hi=0x66 & dst & imm4 { + tmp:2 = sext(imm4); + dst = dst * tmp; +} +:MULW imm16, dst is hi=0x66 & x2=11 & dst ; imm16 { + dst = dst * imm16; +} +:MULW src, dst is hi=0x67 & src & dst { + dst = dst * src; +} + +# SUBB - subtract low-order byte only +:SUBB imm4, dst is hi=0x38 & dst & imm4 { + subflags(dst:1, imm4); + tmp:1 = dst:1 - imm4; + dst = (dst & 0xff00) + zext(tmp); +} +:SUBB imm16, dst is hi=0x38 & x2=11 & dst ; imm16 { + subflags(dst:1, imm16:1); + tmp:1 = dst:1 - imm16:1; + dst = (dst & 0xff00) + zext(tmp); +} +:SUBB src, dst is hi=0x39 & src & dst { + subflags(dst:1, src:1); + tmp:1 = dst:1 - src:1; + dst = (dst & 0xff00) + zext(tmp); +} + +# SUBCB - subtract with carry low-order byte only +:SUBCB imm4, dst is hi=0x3c & dst & imm4 { + subflags2(dst:1, imm4, $(C)); + tmp:1 = dst:1 - imm4 - $(C); + dst = (dst & 0xff00) + zext(tmp); +} +:SUBCB imm16, dst is hi=0x3c & x2=11 & dst ; imm16 { + subflags2(dst:1, imm16:1, $(C)); + tmp:1 = dst:1 - imm16:1 - $(C); + dst = (dst & 0xff00) + zext(tmp); +} +:SUBCB src, dst is hi=0x3d & src & dst { + subflags2(dst:1, src:1, $(C)); + tmp:1 = dst:1 - src:1 - $(C); + dst = (dst & 0xff00) + zext(tmp); +} + +# SUBCW - subtract word with carry +:SUBCW imm4, dst is hi=0x3e & dst & imm4 { + tmp2:2 = sext(imm4); + tmp3:2 = zext($(C)); + subflags2(dst, tmp2, tmp3); + dst = dst - tmp2 - tmp3; +} +:SUBCW imm16, dst is hi=0x3e & x2=11 & dst ; imm16 { + tmp3:2 = zext($(C)); + subflags2(dst, imm16, tmp3); + dst = dst - imm16 - tmp3; +} +:SUBCW src, dst is hi=0x3f & src & dst { + tmp3:2 = zext($(C)); + subflags2(dst, src, tmp3); + dst = dst - src - tmp3; +} + +# SUBD - subtract doubleword +:SUBD rp_src6, rp_dst3 is op=0x0014 ; n4=12 & n3=0 & rp_src6 & rp_dst3 { # fmt 1 + subflags(rp_dst3, rp_src6); + rp_dst3 = rp_dst3 - rp_src6; +} +:SUBD imm32, rp_dst is op12=0x003 & rp_dst ; imm32 { + subflags(imm32, rp_dst); + rp_dst = rp_dst - imm32; +} + +# SUBW - subtract word +:SUBW imm4, dst is hi=0x3a & dst & imm4 { + tmp:2 = sext(imm4); + subflags(tmp, dst); + dst = dst - tmp; +} +:SUBW imm16, dst is hi=0x3a & x2=11 & dst ; imm16 { + subflags(imm16, dst); + dst = dst - imm16; +} +:SUBW src, dst is hi=0x3b & src & dst { + subflags(src, dst); + dst = dst - src; +} + + +# INTEGER COMPARISON + +# CMPB - compare low-order byte only +:CMPB imm4, src1 is hi=0x50 & src1 & imm4 { + compflags(imm4, src1:1); +} +:CMPB imm16, src1 is hi=0x50 & x2=11 & src1 ; imm16 { + compflags(imm16:1, src1:1); +} +:CMPB src, src1 is hi=0x51 & src & src1 { + compflags(src:1, src1:1); +} + +# CMPD - compare doubleword +:CMPD imm32, rp_src2 is op12=0x009 & rp_src2 ; imm32 { + compflags(imm32, rp_src2); +} +:CMPD imm4, rp_src2 is hi=0x56 & rp_src2 & imm4 { + tmp:4 = sext(imm4); + compflags(tmp, rp_src2); +} +:CMPD imm16, rp_src2 is hi=0x56 & x2=11 & rp_src2 ; imm16 { + tmp:4 = sext(imm16); + compflags(tmp, rp_src2); +} +:CMPD rp_src, rp_src2 is hi=0x57 & rp_src & rp_src2 { + compflags(rp_src, rp_src2); +} + +# CMPW - compare word +:CMPW imm4, src1 is hi=0x52 & src1 & imm4 { + tmp:2 = sext(imm4); + compflags(tmp, src1); +} +:CMPW imm16, src1 is hi=0x52 & x2=11 & src1 ; imm16 { + compflags(imm16, src1); +} +:CMPW src, src1 is hi=0x53 & src & src1 { + compflags(src, src1); +} + + +# LOGICAL / BOOLEAN + +# ANDB - and low-order byte only +:ANDB imm4, dst is hi=0x20 & dst & imm4 { + tmp:1 = dst:1 & imm4; + dst = (dst & 0xff00) + zext(tmp); +} +:ANDB imm16, dst is hi=0x20 & x2=11 & dst ; imm16 { + tmp:1 = dst:1 & imm16:1; + dst = (dst & 0xff00) + zext(tmp); +} +:ANDB src, dst is hi=0x21 & src & dst { + tmp:1 = dst:1 & src:1; + dst = (dst & 0xff00) + zext(tmp); +} + +# ANDW - and word +:ANDW imm4, dst is hi=0x22 & dst & imm4 { + tmp:2 = sext(imm4); + dst = dst & tmp; +} +:ANDW imm16, dst is hi=0x22 & x2=11 & dst ; imm16 { + dst = dst & imm16; +} +:ANDW src, dst is hi=0x23 & src & dst { + dst = dst & src; +} + +# ANDD - and doubleword +:ANDD imm32, rp_dst is op12=0x004 & rp_dst ; imm32 { + rp_dst = rp_dst & imm32; +} +:ANDD rp_src6, rp_dst3 is op=0x0014 ; n4=11 & rp_src6 & rp_dst3 { # fmt 1 + rp_dst3 = rp_dst3 & rp_src6; +} + +# ORB - or low-order byte only +:ORB imm4, dst is hi=0x24 & dst & imm4 { + tmp:1 = dst:1 | imm4; + dst = (dst & 0xff00) + zext(tmp); +} +:ORB imm16, dst is hi=0x24 & x2=11 & dst ; imm16 { + tmp:1 = dst:1 | imm16:1; + dst = (dst & 0xff00) + zext(tmp); +} +:ORB src, dst is hi=0x25 & src & dst { + tmp:1 = dst:1 | src:1; + dst = (dst & 0xff00) + zext(tmp); +} + +# ORW - or word +:ORW imm4, dst is hi=0x26 & dst & imm4 { + tmp:2 = sext(imm4); + dst = dst | tmp; +} +:ORW imm16, dst is hi=0x26 & x2=11 & dst ; imm16 { + dst = dst | imm16; +} +:ORW src, dst is hi=0x27 & src & dst { + dst = dst | src; +} + +# ORD - or doubleword +:ORD imm32, rp_dst is op12=0x005 & rp_dst ; imm32 { + rp_dst = rp_dst | imm32; +} +:ORD rp_src6, rp_dst3 is op=0x0014 ; n4=9 & rp_src6 & rp_dst3 { # fmt 1 + rp_dst3 = rp_dst3 | rp_src6; +} + +# S - save condition as boolean +:S^COND dst is hi=0x08 & COND & dst { + dst = 0; + build COND; + dst = 1; +} +:S dst is hi=0x08 & cond=14 & dst { + dst = 1; +} +:S dst is hi=0x08 & cond=15 & dst { + dst = 1; +} + +# XORB - xor low-order byte only +:XORB imm4, dst is hi=0x28 & dst & imm4 { + tmp:1 = dst:1 ^ imm4; + dst = (dst & 0xff00) + zext(tmp); +} +:XORB imm16, dst is hi=0x28 & x2=11 & dst ; imm16 { + tmp:1 = dst:1 ^ imm16:1; + dst = (dst & 0xff00) + zext(tmp); +} +:XORB src, dst is hi=0x29 & src & dst { + tmp:1 = dst:1 ^ src:1; + dst = (dst & 0xff00) + zext(tmp); +} + +# XORW - xor word +:XORW imm4, dst is hi=0x2a & dst & imm4 { + tmp:2 = sext(imm4); + dst = dst ^ tmp; +} +:XORW imm16, dst is hi=0x2a & x2=11 & dst ; imm16 { + dst = dst ^ imm16; +} +:XORW src, dst is hi=0x2b & src & dst { + dst = dst ^ src; +} + +# XORD - xor doubleword +:XORD imm32, rp_dst is op12=0x006 & rp_dst ; imm32 { + rp_dst = rp_dst ^ imm32; +} +:XORD rp_src6, rp_dst3 is op=0x0014 ; n4=10 & rp_src6 & rp_dst3 { # fmt 1 + rp_dst3 = rp_dst3 ^ rp_src6; +} + + +# SHIFTS + +# TODO: left shift displays "+", right shift displays "-" + +macro do_ash(count, dest) { + local shift = count:1; + local lf = ( shift) * zext(shift s> 0); + local rt = (-shift) * zext(shift s< 0); + dest = dest << lf; + dest = dest s>> rt; +} + +macro do_ashb(count, dest) { + local tmp = dest & 0xff; + do_ash(count, tmp); + dest = (dest & 0xff00) | (tmp & 0x00ff); +} + +macro do_lsh(count, dest) { + local shift = count:1; + local lf = ( shift) * zext(shift s> 0); + local rt = (-shift) * zext(shift s< 0); + dest = dest << lf; + dest = dest >> rt; +} + +macro do_lshb(count, dest) { + local tmp = dest & 0xff; + do_lsh(count, tmp); + dest = (dest & 0xff00) | (tmp & 0x00ff); +} + +# ASHUB - Arithmetic shift low-order byte only +:ASHUB imm3d, dst is op9=0b010000000 & imm3d & dst { do_ashb(imm3d, dst); } +:ASHUB imm3d, dst is op9=0b010000001 & imm3d & dst { do_ashb(imm3d-8, dst); } +:ASHUB src, dst is hi=0x41 & src & dst { do_ashb(src, dst); } + +# ASHUD - Arithmetic shift doubleword +:ASHUD imm5, rp_dst is op7=0b0100110 & imm5 & rp_dst { do_ash(imm5, rp_dst); } +:ASHUD imm5, rp_dst is op7=0b0100111 & imm5 & rp_dst { do_ash(imm5-32, rp_dst); } +:ASHUD src, rp_dst is hi=0x48 & src & rp_dst { do_ash(src, rp_dst); } + +# ASHUW - Arithmetic shift word +:ASHUW imm4d, dst is hi=0x42 & imm4d & dst { do_ash(imm4d, dst); } +:ASHUW imm4d, dst is hi=0x43 & imm4d & dst { do_ash(imm4d-16, dst); } +:ASHUW src, dst is hi=0x45 & src & dst { do_ash(src, dst); } + +# LSHB - Logical shift low-order byte only +:LSHB imm3d, dst is op9=0b000010011 & imm3d & dst { do_lshb(imm3d-8, dst); } +:LSHB src, dst is hi=0x44 & src & dst { do_lshb(src, dst); } + +# LSHD - Logical shift doubleword +:LSHD imm5, rp_dst is op7=0b0100101 & imm5 & rp_dst { do_lsh(imm5-32, rp_dst); } +:LSHD src, rp_dst is hi=0x47 & src & rp_dst { do_lsh(src, rp_dst); } + +# LSHW - Logical shift word +:LSHW imm4d, dst is hi=0x49 & imm4d & dst { do_lsh(imm4d-16, dst); } +:LSHW src, dst is hi=0x46 & src & dst { do_lsh(src, dst); } + +# BITS +# - for bit ops, dsp(n) is always unsigned + +# CBITB - clear bit in low-order byte +:CBITB imm3c, prp2 disp14(prp_dst) is op10=0x1aa & imm3c & prp2 & disp14 & prp_dst { # fmt 17 + tmp:4 = prp_dst:4 + prp2:4 + zext(disp14); + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3c; + $(F) = (val & mask) >> imm3c; # save bit + mask = ~mask; + *:1 tmp = val & mask; # clear bit, store +} +:CBITB imm3b, disp20(dst4) is op=0x0010 ; n8=4 & imm3b & disp20 & dst4 { # fmt 2 + tmp:4 = zext(dst4) + zext(disp20); + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3b; + $(F) = (val & mask) >> imm3b; # save bit + mask = ~mask; + *:1 tmp = val & mask; # clear bit, store +} +:CBITB imm3, const1(rp_dst) is op9=0x0d4 & imm3 & rp_dst & const1 { # fmt 9 + tmp:4 = rp_dst:4; + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3; + $(F) = (val & mask) >> imm3; # save bit + mask = ~mask; + *:1 tmp = val & mask; # clear bit, store +} +:CBITB imm3, disp16b(rp_dst) is op9=0x0d6 & imm3 & rp_dst ; disp16b { # fmt 10 + tmp:4 = rp_dst:4 + zext(disp16b); + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3; + $(F) = (val & mask) >> imm3; # save bit + mask = ~mask; + *:1 tmp = val & mask; # clear bit, store +} +:CBITB imm3b, disp20(rp_dst5) is op=0x0010 ; n8=5 & imm3b & disp20 & rp_dst5 { # fmt 2 + tmp:4 = rp_dst5:4 + zext(disp20); + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3b; + $(F) = (val & mask) >> imm3b; # save bit + mask = ~mask; + *:1 tmp = val & mask; # clear bit, store +} +:CBITB imm3b, disp20(prp_dst) is op=0x0010 ; n8=6 & imm3b & disp20 & prp_dst { # fmt 2 + tmp:4 = prp_dst:4 + zext(disp20); + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3b; + $(F) = (val & mask) >> imm3b; # save bit + mask = ~mask; + *:1 tmp = val & mask; # clear bit, store +} +:CBITB imm3b, abs20 is dw_op9=0x0d7 & imm3b & abs20 { # fmt 7 + tmp:4 = zext(abs20); + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3b; + $(F) = (val & mask) >> imm3b; # save bit + mask = ~mask; + *:1 tmp = val & mask; # clear bit, store +} +:CBITB imm3b, rs abs20 is dw_hi=0x68 & imm3b & rs & abs20 { # fmt 8 + tmp:4 = zext(abs20) + rs:4; + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3b; + $(F) = (val & mask) >> imm3b; # save bit + mask = ~mask; + *:1 tmp = val & mask; # clear bit, store +} +:CBITB imm3b, abs24 is op=0x0010 ; n8=7 & imm3b & abs24 { # fmt 3 + tmp:4 = abs24; + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3b; + $(F) = (val & mask) >> imm3b; # save bit + mask = ~mask; + *:1 tmp = val & mask; # clear bit, store +} + +# CBITW - clear bit in word +:CBITW imm4c, prp2 disp14(prp_dst) is op10=0x1ab & imm4c & prp2 & disp14 & prp_dst { # fmt 17 + tmp:4 = prp_dst:4 + prp2:4 + zext(disp14); + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4c; + bit:2 = (val & mask) >> imm4c; + $(F) = bit:1; # save bit + mask = ~mask; + *:2 tmp = val & mask; # clear bit, store +} +:CBITW imm4b, disp20(dst4) is op=0x0011 ; n8=4 & imm4b & disp20 & dst4 { # fmt 2 + tmp:4 = zext(dst4) + zext(disp20); + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4b; + bit:2 = (val & mask) >> imm4b; + $(F) = bit:1; # save bit + mask = ~mask; + *:2 tmp = val & mask; # clear bit, store +} +:CBITW imm4a, const1(rp_dst) is hi=0x6e & imm4a & rp_dst & const1 { + tmp:4 = rp_dst:4; + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4a; + bit:2 = (val & mask) >> imm4a; + $(F) = bit:1; # save bit + mask = ~mask; + *:2 tmp = val & mask; # clear bit, store +} +:CBITW imm4a, disp16b(rp_dst) is hi=0x69 & imm4a & rp_dst ; disp16b { + tmp:4 = rp_dst:4 + zext(disp16b); + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4a; + bit:2 = (val & mask) >> imm4a; + $(F) = bit:1; # save bit + mask = ~mask; + *:2 tmp = val & mask; # clear bit, store +} +:CBITW imm4b, disp20(rp_dst5) is op=0x0011 ; n8=5 & rp_dst5 & imm4b & disp20 { + tmp:4 = rp_dst5:4 + zext(disp20); + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4b; + bit:2 = (val & mask) >> imm4b; + $(F) = bit:1; # save bit + mask = ~mask; + *:2 tmp = val & mask; # clear bit, store +} +:CBITW imm4b, disp20(prp_dst) is op=0x0011 ; n8=6 & imm4b & disp20 & prp_dst { # fmt 2 + tmp:4 = prp_dst:4 + zext(disp20); + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4b; + bit:2 = (val & mask) >> imm4b; + $(F) = bit:1; # save bit + mask = ~mask; + *:2 tmp = val & mask; # clear bit, store +} +:CBITW imm4b, abs20 is dw_hi=0x6f & imm4b & abs20 { # fmt 12 + tmp:4 = zext(abs20); + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4b; + bit:2 = (val & mask) >> imm4b; + $(F) = bit:1; # save bit + mask = ~mask; + *:2 tmp = val & mask; # clear bit, store +} +:CBITW imm4b, rs abs20 is dw_op7=0x36 & imm4b & rs & abs20 { # fmt 13 + tmp:4 = zext(abs20) + rs:4; + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4b; + bit:2 = (val & mask) >> imm4b; + $(F) = bit:1; # save bit + mask = ~mask; + *:2 tmp = val & mask; # clear bit, store +} +:CBITW imm4b, abs24 is op=0x0011 ; n8=7 & imm4b & abs24 { # fmt 3 + tmp:4 = abs24; + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4b; + bit:2 = (val & mask) >> imm4b; + $(F) = bit:1; # save bit + mask = ~mask; + *:2 tmp = val & mask; # clear bit, store +} + +# SBITB - set bit in low-order byte +:SBITB imm3c, prp2 disp14(prp_dst) is op10=0x1ca & imm3c & prp2 & disp14 & prp_dst { # fmt 17 + tmp:4 = prp_dst:4 + prp2:4 + zext(disp14); + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3c; + $(F) = (val & mask) >> imm3c; # save bit + *:1 tmp = val | mask; # set bit, store +} +:SBITB imm3b, disp20(dst4) is op=0x0010 ; n8=8 & imm3b & disp20 & dst4 { # fmt 2 + tmp:4 = zext(dst4) + zext(disp20); + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3b; + $(F) = (val & mask) >> imm3b; # save bit + *:1 tmp = val | mask; # set bit, store +} +:SBITB imm3, const1(rp_dst) is op9=0x0e4 & imm3 & rp_dst & const1 { # fmt 9 + tmp:4 = rp_dst:4; + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3; + $(F) = (val & mask) >> imm3; # save bit + *:1 tmp = val | mask; # set bit, store +} +:SBITB imm3, disp16b(rp_dst) is op9=0x0e6 & imm3 & rp_dst ; disp16b { # fmt 10 + tmp:4 = rp_dst:4 + zext(disp16b); + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3; + $(F) = (val & mask) >> imm3; # save bit + *:1 tmp = val | mask; # set bit, store +} +:SBITB imm3b, disp20(rp_dst5) is op=0x0010 ; n8=9 & imm3b & disp20 & rp_dst5 { # fmt 2 + tmp:4 = rp_dst5:4 + zext(disp20); + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3b; + $(F) = (val & mask) >> imm3b; # save bit + *:1 tmp = val | mask; # set bit, store +} +:SBITB imm3b, disp20(prp_dst) is op=0x0010 ; n8=10 & imm3b & disp20 & prp_dst { # fmt 2 + tmp:4 = prp_dst:4 + zext(disp20); + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3b; + $(F) = (val & mask) >> imm3b; # save bit + *:1 tmp = val | mask; # set bit, store +} +:SBITB imm3b, abs20 is dw_op9=0x0e7 & imm3b & abs20 { # fmt 7 + tmp:4 = zext(abs20); + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3b; + $(F) = (val & mask) >> imm3b; # save bit + *:1 tmp = val | mask; # set bit, store +} +:SBITB imm3b, rs abs20 is dw_hi=0x70 & imm3b & rs & abs20 { # fmt 8 + tmp:4 = zext(abs20) + rs:4; + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3b; + $(F) = (val & mask) >> imm3b; # save bit + *:1 tmp = val | mask; # set bit, store +} +:SBITB imm3b, abs24 is op=0x0010 ; n8=11 & imm3b & abs24 { # fmt 3 + tmp:4 = abs24; + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3b; + $(F) = (val & mask) >> imm3b; # save bit + *:1 tmp = val | mask; # set bit, store +} + +# SBITW - set bit in word +:SBITW imm4c, prp2 disp14(prp_dst) is op10=0x1cb & imm4c & prp2 & disp14 & prp_dst { # fmt 17 + tmp:4 = prp_dst:4 + prp2:4 + zext(disp14); + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4c; + bit:2 = (val & mask) >> imm4c; + $(F) = bit:1; # save bit + *:2 tmp = val | mask; # clear bit, store +} +:SBITW imm4b, disp20(dst4) is op=0x0011 ; n8=8 & imm4b & disp20 & dst4 { # fmt 2 + tmp:4 = zext(dst4) + zext(disp20); + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4b; + bit:2 = (val & mask) >> imm4b; + $(F) = bit:1; # save bit + *:2 tmp = val | mask; # clear bit, store +} +:SBITW imm4a, const1(rp_dst) is hi=0x76 & imm4a & const1 & rp_dst { # fmt 15 + tmp:4 = rp_dst:4; + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4a; + bit:2 = (val & mask) >> imm4a; + $(F) = bit:1; # save bit + *:2 tmp = val | mask; # clear bit, store +} +:SBITW imm4a, disp16b(rp_dst) is hi=0x71 & imm4a & rp_dst ; disp16b { # fmt 16 + tmp:4 = rp_dst:4 + zext(disp16b); + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4a; + bit:2 = (val & mask) >> imm4a; + $(F) = bit:1; # save bit + *:2 tmp = val | mask; # clear bit, store +} +:SBITW imm4b, disp20(rp_dst5) is op=0x0011 ; n8=9 & rp_dst5 & imm4b & disp20 { + tmp:4 = rp_dst5:4 + zext(disp20); + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4b; + bit:2 = (val & mask) >> imm4b; + $(F) = bit:1; # save bit + *:2 tmp = val | mask; # clear bit, store +} +:SBITW imm4b, disp20(prp_dst) is op=0x0011 ; n8=10 & imm4b & disp20 & prp_dst { + tmp:4 = prp_dst:4 + zext(disp20); + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4b; + bit:2 = (val & mask) >> imm4b; + $(F) = bit:1; # save bit + *:2 tmp = val | mask; # clear bit, store +} +:SBITW imm4b, abs20 is dw_hi=0x77 & imm4b & abs20 { # fmt 12 + tmp:4 = zext(abs20); + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4b; + bit:2 = (val & mask) >> imm4b; + $(F) = bit:1; # save bit + *:2 tmp = val | mask; # clear bit, store +} +:SBITW imm4b, rs abs20 is dw_op7=0x3a & imm4b & rs & abs20 { + tmp:4 = zext(abs20) + rs:4; + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4b; + bit:2 = (val & mask) >> imm4b; + $(F) = bit:1; # save bit + *:2 tmp = val | mask; # clear bit, store +} +:SBITW imm4b, abs24 is op=0x0011 ; n8=11 & imm4b & abs24 { # fmt 3 + tmp:4 = abs24; + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4b; + bit:2 = (val & mask) >> imm4b; + $(F) = bit:1; # save bit + *:2 tmp = val | mask; # clear bit, store +} + +# TBIT - test bit +:TBIT imm4a, src1 is hi=0x06 & imm4a & src1 { + tmp:4 = zext(src1); + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4a; + bit:2 = (val & mask) >> imm4a; + $(F) = bit:1; # save bit +} +:TBIT src, src1 is hi=0x07 & src & src1 { + tmp:4 = zext(src1); + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << src; + bit:2 = (val & mask) >> src; + $(F) = bit:1; # save bit +} + +# TBITB - test bit in low-order byte +:TBITB imm3c, prp2 disp14(prp_dst) is op10=0x1ea & imm3c & prp2 & disp14 & prp_dst { # fmt 17 (affected by CFG.SR) + tmp:4 = prp_dst:4 + prp2:4 + zext(disp14); + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3c; + $(F) = (val & mask) >> imm3c; # save bit +} +:TBITB imm3b, disp20(dst4) is op=0x0010 ; n8=12 & imm3b & disp20 & dst4 { # fmt 2 + tmp:4 = zext(dst4) + zext(disp20); + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3b; + $(F) = (val & mask) >> imm3b; # save bit +} +:TBITB imm3, const1(rp_dst) is op9=0x0f4 & imm3 & rp_dst & const1 { # fmt 9 + tmp:4 = rp_dst:4; + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3; + $(F) = (val & mask) >> imm3; # save bit +} +:TBITB imm3, disp16b(rp_dst) is op9=0x0f6 & imm3 & rp_dst ; disp16b { # fmt 10 + tmp:4 = rp_dst:4 + zext(disp16b); + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3; + $(F) = (val & mask) >> imm3; # save bit +} +:TBITB imm3b, disp20(rp_dst5) is op=0x0010 ; n8=13 & imm3b & disp20 & rp_dst5 { + tmp:4 = rp_dst5:4 + zext(disp20); + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3b; + $(F) = (val & mask) >> imm3b; # save bit +} +:TBITB imm3b, disp20(prp_dst) is op=0x0010 ; n8=14 & imm3b & disp20 & prp_dst { + tmp:4 = prp_dst:4 + zext(disp20); + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3b; + $(F) = (val & mask) >> imm3b; # save bit +} +:TBITB imm3b, abs20 is dw_op9=0x0f7 & imm3b & abs20 { # fmt 7 + tmp:4 = zext(abs20); + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3b; + $(F) = (val & mask) >> imm3b; # save bit +} +:TBITB imm3b, rs abs20 is dw_hi=0x78 & imm3b & rs & abs20 { # fmt 8 + tmp:4 = zext(abs20) + rs:4; + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3b; + $(F) = (val & mask) >> imm3b; # save bit +} +:TBITB imm3b, abs24 is op=0x0010 ; n8=15 & imm3b & abs24 { # fmt 3 + tmp:4 = abs24; + val:1 = *:1 tmp; # load dst operand + local mask = 1 << imm3b; + $(F) = (val & mask) >> imm3b; # save bit +} + +# TBITW - test bit in word +:TBITW imm4c, prp2 disp14(prp_dst) is op10=0x1eb & imm4c & prp2 & disp14 & prp_dst { # fmt 17 + tmp:4 = prp_dst:4 + prp2:4 + zext(disp14); + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4c; + bit:2 = (val & mask) >> imm4c; + $(F) = bit:1; # save bit +} +:TBITW imm4b, disp20(dst4) is op=0x0011 ; n8=12 & imm4b & disp20 & dst4 { + tmp:4 = zext(dst4) + zext(disp20); + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4b; + bit:2 = (val & mask) >> imm4b; + $(F) = bit:1; # save bit +} +:TBITW imm4a, const1(rp_dst) is hi=0x7e & imm4a & const1 & rp_dst { # fmt 15 + tmp:4 = rp_dst:4; + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4a; + bit:2 = (val & mask) >> imm4a; + $(F) = bit:1; # save bit +} +:TBITW imm4a, disp16b(rp_dst) is hi=0x79 & imm4a & rp_dst ; disp16b { # fmt 16 + tmp:4 = rp_dst:4 + zext(disp16b); + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4a; + bit:2 = (val & mask) >> imm4a; + $(F) = bit:1; # save bit +} +:TBITW imm4b, disp20(rp_dst5) is op=0x0011 ; n8=13 & rp_dst5 & imm4b & disp20 { + tmp:4 = rp_dst5:4 + zext(disp20); + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4b; + bit:2 = (val & mask) >> imm4b; + $(F) = bit:1; # save bit +} +:TBITW imm4b, disp20(prp_dst) is op=0x0011 ; n8=14 & imm4b & disp20 & prp_dst { + tmp:4 = prp_dst:4 + zext(disp20); + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4b; + bit:2 = (val & mask) >> imm4b; + $(F) = bit:1; # save bit +} +:TBITW imm4b, abs20 is dw_hi=0x7f & imm4b & abs20 { + tmp:4 = zext(abs20); + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4b; + bit:2 = (val & mask) >> imm4b; + $(F) = bit:1; # save bit +} +:TBITW imm4b, rs abs20 is dw_op7=0x3e & imm4b & rs & abs20 { # fmt 13 + tmp:4 = zext(abs20) + rs:4; + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4b; + bit:2 = (val & mask) >> imm4b; + $(F) = bit:1; # save bit +} +:TBITW imm4b, abs24 is op=0x0011 ; n8=15 & imm4b & abs24 { + tmp:4 = abs24; + val:2 = *:2 tmp; # load dst operand + mask:2 = 1 << imm4b; + bit:2 = (val & mask) >> imm4b; + $(F) = bit:1; # save bit +} + + +# PROCESSOR REGISTER MANIPULATION + +# TODO: +# For the LPR instruction, if dest is ISPL or INTBASEL the least significant +# bit (bit 0) of the address is 0. If dest is INTBASEH, ISPH, USPH, CAR0H, +# or CAR1H bits 8 through 15 are always written as 0. +# For the LPRD instruction, if dest is ISP or INTBASE the least significant +# bit (bit 0) of the address is 0. If dest is INTBASE, ISP, USP, CAR0, or +# CAR1 bits 24 through 31 are always written as 0. + +# Load Processor Register (word) +:LPR src2, pr is op=0x0014 ; n4=0 & n3=0 & pr & src2 { + pr = src2; +} + +# Load Processor Register (doubleword) +:LPRD rp_src3, prd is op=0x0014 ; n4=1 & n3=0 & prd & rp_src3 { + prd = rp_src3; +} + +# Store Processor Register (word) +:SPR pr, dst2 is op=0x0014 ; n4=2 & n3=0 & pr & dst2 { + dst2 = pr; +} + +# Store Processor Register (doubleword) +:SPRD prd, rp_dst3 is op=0x0014 ; n4=3 & n3=0 & prd & rp_dst3 { + rp_dst3 = prd; +} + + +# JUMPS AND LINKS + +# BAL - Branch and Link +:BAL (RA), disp24b is dw_hi=0xc0 & disp24b & RA { + RA = inst_next >> 1; # save bits 1 to 23 in link reg RA + PC = &disp24b; # PC = PC + sext25(disp) TODO: 25 bits? + call disp24b; +} +:BAL rp_dst4, disp24 is op=0x0010 ; n8=2 & disp24 & rp_dst4 { + # rp link is at word2 (4,7) + rp_dst4 = inst_next >> 1; # save bits 1 to 23 in link reg + PC = &disp24; # PC = PC + sext25(disp) TODO: 25 bits? + call disp24; +} + +# BEQ0B - branch if low byte equals 0 +:BEQ0B src1, disp4c is hi=0x0c & src1 & disp4c { + if (src1:1 != 0) goto inst_next; # don't branch if not equal + PC = &disp4c; # branch + goto disp4c; +} +# BEQ0W - branch if word equals 0 +:BEQ0W src1, disp4c is hi=0x0e & src1 & disp4c { + if (src1 != 0) goto inst_next; # don't branch if not equal + PC = &disp4c; # branch + goto disp4c; +} +# BNE0B - branch if low byte does not equal 0 +:BNE0B src1, disp4c is hi=0x0d & src1 & disp4c { + if (src1:1 == 0) goto inst_next; # don't branch if equal + PC = &disp4c; # branch + goto disp4c; +} +:BNE0W src1, disp4c is hi=0x0f & src1 & disp4c { + if (src1 == 0) goto inst_next; # don't branch if equal + PC = &disp4c; # branch + goto disp4c; +} + +# BR - branch (conditional and unconditional) +:BR^COND disp8 is op4=1 & COND & disp8 { # BR (conditional) + build COND; + PC = &disp8; + goto disp8; +} +:BR disp8 is op4=1 & cond=14 & disp8 { # BR cond=14 (always) + PC = &disp8; + goto disp8; +} +:BR disp8 is op4=1 & cond=15 & disp8 { # BR cond=15 (unconditional) + PC = &disp8; + goto disp8; +} + +:BR^COND disp16 is hi=0x18 & lo1=0 & COND ; disp16 { # BR (conditional) + build COND; + PC = &disp16; + goto disp16; +} +:BR disp16 is hi=0x18 & lo1=0 & cond=14 ; disp16 { # BR cond=14 (always) + PC = &disp16; + goto disp16; +} +:BR disp16 is hi=0x18 & lo1=0 & cond=15 ; disp16 { # BR cond=15 (unconditional) + PC = &disp16; + goto disp16; +} + +:BR^COND2 disp24 is op=0x0010 ; n8=0 & COND2 & disp24 { # BR (conditional) + build COND2; + PC = &disp24; + goto disp24; +} +:BR disp24 is op=0x0010 ; n8=0 & n6=14 & disp24 { # BR cond=14 (always) + PC = &disp24; + goto disp24; +} +:BR disp24 is op=0x0010 ; n8=0 & n6=15 & disp24 { # BR cond=15 (unconditional) + PC = &disp24; + goto disp24; +} + +# EXCP - Exception +:EXCP x1 is op12=0x00c & x1 { +# *:4(ISP:3) = zext(inst_start); + *:2(ISP:4) = PSR; # push PSR onto interrupt stack + ISP = ISP - 2; + *:4(ISP:4) = inst_start; # push ret addr (current instruction) onto interrupt stack + ISP = ISP - 4; + trap(); +} + +# JAL - Jump and Link +:JAL rp_dst is op12=0x00d & rp_dst { + RA = inst_next >> 1; + local tmp = rp_dst << 1; + PC = tmp:4; + call [PC]; +} +:JAL rp_dst6 is op=0x0014 ; n4=8 & n3=0 & rp_dst6 & rp_dst3 { + # rp link is at word2 (0,3) + rp_dst3 = inst_next >> 1; + local tmp = rp_dst6 << 1; + PC = tmp:4; + call [PC]; +} + +# J - Jump - special case jumping through link register +:J^COND RA is hi=0x0a & COND & rp_dst=14 & RA { # conditional + build COND; + local tmp = RA << 1; + PC = tmp:4; + return [PC]; +} +:JUMP RA is hi=0xa & cond=14 & rp_dst=14 & RA { # always + local tmp = RA << 1; + PC = tmp:4; + return [PC]; +} +:JUSR RA is hi=0xa & cond=15 & rp_dst=14 & RA { # unconditional + $(U) = 1; + local tmp = RA << 1; + PC = tmp:4; + return [PC]; +} + +# J - Jump (conditional and unconditional) +:J^COND rp_dst is hi=0x0a & COND & rp_dst { # conditional + build COND; + local tmp = rp_dst << 1; + PC = tmp:4; + goto [PC]; +} +:JUMP rp_dst is hi=0xa & cond=14 & rp_dst { # always + local tmp = rp_dst << 1; + PC = tmp:4; + goto [PC]; +} +:JUSR rp_dst is hi=0xa & cond=15 & rp_dst { # unconditional + $(U) = 1; + local tmp = rp_dst << 1; + PC = tmp:4; + goto [PC]; +} + +attach variables [ reg0 ] [ R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12_L R13_L RA_L SP_L ]; +attach variables [ reg1 ] [ R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12_L R12_H R13_H RA_H SP_H ]; +attach variables [ reg2 ] [ R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12_L R12_H R13_L RA_L SP_L R0 ]; +attach variables [ reg3 ] [ R3 R4 R5 R6 R7 R8 R9 R10 R11 R12_L R12_H R13_L R13_H RA_H SP_H R1 ]; +attach variables [ reg4 ] [ R4 R5 R6 R7 R8 R9 R10 R11 R12_L R12_H R13_L R13_H RA_L SP_L R0 R3 ]; +attach variables [ reg5 ] [ R5 R6 R7 R8 R9 R10 R11 R12_L R12_H R13_L R13_H RA_L RA_H SP_H R1 R4 ]; +attach variables [ reg6 ] [ R6 R7 R8 R9 R10 R11 R12_L R12_H R13_L R13_H RA_L RA_H SP_L R0 R2 R5 ]; +attach variables [ reg7 ] [ R7 R8 R9 R10 R11 R12_L R12_H R13_L R13_H RA_L RA_H SP_L SP_H R1 R3 R6 ]; + +macro push_one(reg) { + SP = SP - 2; + *SP = reg; +} + +macro pop_one(reg) { + reg = *SP; + SP = SP + 2; +} + +macro push_ra() { + SP = SP - 4; + *SP = RA; +} + +macro pop_ra() { + RA = *SP; + SP = SP + 4; +} +macro do_pop_ret() { + tmp:4 = RA << 1; + PC = tmp; + return [PC]; +} + +push_args: "$"tmp, reg0 is b_ra=0 & b4_6 & reg0 [ tmp = b4_6 + 1; ] { } +push_args: "$"tmp, reg0, "ra" is b_ra=1 & b4_6 & reg0 [ tmp = b4_6 + 1; ] { push_ra(); } + +pop_args: "$"tmp, reg0 is b_ra=0 & b4_6 & reg0 [ tmp = b4_6 + 1; ] { } +pop_args: "$"tmp, reg0, "ra" is b_ra=1 & b4_6 & reg0 [ tmp = b4_6 + 1; ] { pop_ra(); } + +:push push_args +is hi=1 & b4_6=0 & reg0 & push_args +{ + build push_args; + push_one(reg0); +} + +:push push_args +is hi=1 & b4_6=1 & reg0 & reg1 & push_args +{ + build push_args; + push_one(reg1); + push_one(reg0); +} + +:push push_args +is hi=1 & b4_6=2 & reg0 & reg1 & reg2 & push_args +{ + build push_args; + push_one(reg2); + push_one(reg1); + push_one(reg0); +} + +:push push_args +is hi=1 & b4_6=3 & reg0 & reg1 & reg2 & reg3 & push_args +{ + build push_args; + push_one(reg3); + push_one(reg2); + push_one(reg1); + push_one(reg0); +} + +:push push_args +is hi=1 & b4_6=4 & reg0 & reg1 & reg2 & reg3 & reg4 & push_args +{ + build push_args; + push_one(reg4); + push_one(reg3); + push_one(reg2); + push_one(reg1); + push_one(reg0); +} + +:push push_args +is hi=1 & b4_6=5 & reg0 & reg1 & reg2 & reg3 & reg4 & reg5 & push_args +{ + build push_args; + push_one(reg5); + push_one(reg4); + push_one(reg3); + push_one(reg2); + push_one(reg1); + push_one(reg0); +} + +:push push_args +is hi=1 & b4_6=6 & reg0 & reg1 & reg2 & reg3 & reg4 & reg5 & reg6 & push_args +{ + build push_args; + push_one(reg6); + push_one(reg5); + push_one(reg4); + push_one(reg3); + push_one(reg2); + push_one(reg1); + push_one(reg0); + +} + +:push push_args +is hi=1 & b4_6=7 & reg0 & reg1 & reg2 & reg3 & reg4 & reg5 & reg6 & reg7 & push_args +{ + build push_args; + push_one(reg7); + push_one(reg6); + push_one(reg5); + push_one(reg4); + push_one(reg3); + push_one(reg2); + push_one(reg1); + push_one(reg0); +} + +pop_ret: "ret" is hi=3 { do_pop_ret(); } +pop_ret: "" is hi=2 { } + +:pop^pop_ret pop_args +is pop_ret & pop_args & op7=1 & b4_6=0 & reg0 +{ + pop_one(reg0); + build pop_args; + build pop_ret; +} + +:pop^pop_ret pop_args +is pop_ret & pop_args & op7=1 & b4_6=1 & reg0 & reg1 +{ + pop_one(reg0); + pop_one(reg1); + build pop_args; + build pop_ret; +} + +:pop^pop_ret pop_args +is pop_ret & pop_args & op7=1 & b4_6=2 & reg0 & reg1 & reg2 +{ + pop_one(reg0); + pop_one(reg1); + pop_one(reg2); + build pop_args; + build pop_ret; +} + +:pop^pop_ret pop_args +is pop_ret & pop_args & op7=1 & b4_6=3 & reg0 & reg1 & reg2 & reg3 +{ + pop_one(reg0); + pop_one(reg1); + pop_one(reg2); + pop_one(reg3); + build pop_args; + build pop_ret; +} + +:pop^pop_ret pop_args +is pop_ret & pop_args & op7=1 & b4_6=4 & reg0 & reg1 & reg2 & reg3 & reg4 +{ + pop_one(reg0); + pop_one(reg1); + pop_one(reg2); + pop_one(reg3); + pop_one(reg4); + build pop_args; + build pop_ret; +} + +:pop^pop_ret pop_args +is pop_ret & pop_args & op7=1 & b4_6=5 & reg0 & reg1 & reg2 & reg3 & reg4 & reg5 +{ + pop_one(reg0); + pop_one(reg1); + pop_one(reg2); + pop_one(reg3); + pop_one(reg4); + pop_one(reg5); + build pop_args; + build pop_ret; +} + +:pop^pop_ret pop_args +is pop_ret & pop_args & op7=1 & b4_6=6 & reg0 & reg1 & reg2 & reg3 & reg4 & reg5 & reg6 +{ + pop_one(reg0); + pop_one(reg1); + pop_one(reg2); + pop_one(reg3); + pop_one(reg4); + pop_one(reg5); + pop_one(reg6); + build pop_args; + build pop_ret; +} + +:pop^pop_ret pop_args +is pop_ret & pop_args & op7=1 & b4_6=7 & reg0 & reg1 & reg2 & reg3 & reg4 & reg5 & reg6 & reg7 +{ + pop_one(reg0); + pop_one(reg1); + pop_one(reg2); + pop_one(reg3); + pop_one(reg4); + pop_one(reg5); + pop_one(reg6); + pop_one(reg7); + build pop_args; + build pop_ret; +} + +# RETX - Return from Exception +:RETX is op=0x0003 { + PC = *(ISP:4) << 1; # PC equals bits 0 to 22 popped from stack shifted left 1 + ISP = ISP + 4; + PSR = *(ISP:4); # PSR popped/restored from interrupt stack + ISP = ISP + 2; + return [PC]; +} + + +# LOAD / STORE +# - for loads and stores, dsp(n) is always unsigned + +# LOADB - Load low-order byte only +:LOADB prp const1(prp_src1), dst1 is hi=0xbe & prp & const1 & prp_src1 & dst1 { # fmt 18 + tmp:4 = prp_src1:4 + prp:4; + dst1 = (dst1 & 0xff00) + zext( *:1 tmp ); +} +:LOADB prp2 disp14(prp_src), dst3 is op10=0x219 & prp2 & disp14 & prp_src & dst3 { # fmt 17 + tmp:4 = prp_src:4 + prp2:4 + zext(disp14); + dst3 = (dst3 & 0xff00) + zext( *:1 tmp ); +} +:LOADB disp20(src4), dst3 is op=0x0012 ; n8=4 & disp20 & src4 & dst3 { # fmt 2 + tmp:4 = zext(src4) + zext(disp20); + dst3 = (dst3 & 0xff00) + zext( *:1 tmp ); +} +:LOADB -disp20(src4), dst3 is op=0x0018 ; n8=4 & disp20 & src4 & dst3 { + tmp:4 = zext(src4) - zext(disp20); + dst3 = (dst3 & 0xff00) + zext( *:1 tmp ); +} +:LOADB disp16b(rp_src2), dst1 is hi=0xbf & rp_src2 & dst1 ; disp16b { # fmt 19 + tmp:4 = rp_src2:4 + zext(disp16b); + dst1 = (dst1 & 0xff00) + zext( *:1 tmp ); +} +:LOADB disp20(rp_src5), dst3 is op=0x0012 ; n8=5 & disp20 & rp_src5 & dst3 { # fmt 2 + tmp:4 = rp_src5:4 + zext(disp20); + dst3 = (dst3 & 0xff00) + zext( *:1 tmp ); +} +:LOADB -disp20(rp_src5), dst3 is op=0x0018 ; n8=5 & disp20 & rp_src5 & dst3 { + tmp:4 = rp_src5:4 - zext(disp20); + dst3 = (dst3 & 0xff00) + zext( *:1 tmp ); +} +:LOADB disp4b(rp_src2), dst1 is op4=0xb & dst1 & disp4b & rp_src2 { # fmt 18 + tmp:4 = rp_src2:4 + zext(disp4b); + dst1 = (dst1 & 0xff00) + zext( *:1 tmp ); +} +:LOADB disp20(prp_src), dst3 is op=0x0012 ; n8=6 & disp20 & prp_src & dst3 { # fmt 2 + tmp:4 = prp_src:4 + zext(disp20); + dst3 = (dst3 & 0xff00) + zext( *:1 tmp ); +} +:LOADB abs20, dst3 is dw_hi=0x88 & abs20 & dst3 { # fmt 12 + tmp:4 = zext(abs20); + dst3 = (dst3 & 0xff00) + zext( *:1 tmp ); +} +:LOADB rs abs20, dst3 is dw_op7=0x45 & dst3 & rs & abs20 { # fmt 13 + tmp:4 = zext(abs20) + rs:4; + dst3 = (dst3 & 0xff00) + zext( *:1 tmp ); +} +:LOADB abs24, dst3 is op=0x0012 ; n8=7 & dst3 & abs24 { # fmt 3 + dst3 = (dst3 & 0xff00) + zext( *:1 abs24 ); +} + +# LOADD - load doubleword +:LOADD prp const1(prp_src1), rp_dst2 is hi=0xae & prp & const1 & prp_src1 & rp_dst2 { # fmt 18 + tmp:4 = prp_src1:4 + prp:4; + rp_dst2 = *tmp; +} +:LOADD prp2 disp14(prp_src), rp_dst4 is op10=0x21a & prp2 & disp14 & prp_src & rp_dst4 { # fmt 17 + tmp:4 = prp_src:4 + prp2:4 + zext(disp14); + rp_dst4 = *tmp; +} +:LOADD disp20(src4), rp_dst4 is op=0x0012 ; n8=8 & disp20 & src4 & rp_dst4 { # fmt 2 + tmp:4 = zext(src4) + zext(disp20); + rp_dst4 = *tmp; +} +:LOADD -disp20(src4), rp_dst4 is op=0x0018 ; n8=8 & disp20 & src4 & rp_dst4 { + tmp:4 = zext(src4) - zext(disp20); + rp_dst4 = *tmp; +} +:LOADD disp16b(rp_src2), rp_dst2 is hi=0xaf & rp_dst2 & rp_src2 ; disp16b { # fmt 19 + tmp:4 = rp_src2:4 + zext(disp16b); + rp_dst2 = *tmp; +} +:LOADD disp20(rp_src5), rp_dst4 is op=0x0012 ; n8=9 & disp20 & rp_src5 & rp_dst4 { # fmt 2 + tmp:4 = rp_src5:4 + zext(disp20); + rp_dst4 = *tmp; +} +:LOADD -disp20(rp_src5), rp_dst4 is op=0x0018 ; n8=9 & disp20 & rp_src5 & rp_dst4 { + tmp:4 = rp_src5:4 - zext(disp20); + rp_dst4 = *tmp; +} +:LOADD disp4(rp_src2), rp_dst2 is op4=0xa & disp4 & rp_src2 & rp_dst2 { + tmp:4 = rp_src2:4 + zext(disp4); + rp_dst2 = *tmp; +} +:LOADD disp20(prp_src), rp_dst4 is op=0x0012 ; n8=10 & disp20 & prp_src & rp_dst4 { # fmt 2 + tmp:4 = prp_src:4 + zext(disp20); + rp_dst4 = *tmp; +} +:LOADD abs20, rp_dst4 is dw_hi=0x87 & abs20 & rp_dst4 { + tmp:4 = zext(abs20); + rp_dst4 = *tmp; +} +:LOADD rs abs20, rp_dst4 is dw_op7=0x46 & rs & abs20 & rp_dst4 { + tmp:4 = zext(abs20) + rs:4; + rp_dst4 = *tmp; +} +:LOADD abs24, rp_dst4 is op=0x0012 ; n8=11 & rp_dst4 & abs24 { # fmt 3 + rp_dst4 = *abs24; +} + +macro load_one_1(rd) { + addr:4 = zext(R0); + rd = *addr; + R0 = R0 + 2; +} + +macro load_one_2(rd) { + addr:4 = R1R0:4; + rd = *addr; + R1R0 = R1R0 + 2; +} + +# LOADM/LOADMP - Load Multiple Registers from Memory +:LOADM cnt3b is op13=0x0014 & b0_2=0 & cnt3b { load_one_1(R2); } +:LOADM cnt3b is op13=0x0014 & b0_2=1 & cnt3b { load_one_1(R2); load_one_1(R3); } +:LOADM cnt3b is op13=0x0014 & b0_2=2 & cnt3b { load_one_1(R2); load_one_1(R3); load_one_1(R4); } +:LOADM cnt3b is op13=0x0014 & b0_2=3 & cnt3b { load_one_1(R2); load_one_1(R3); load_one_1(R4); load_one_1(R5); } +:LOADM cnt3b is op13=0x0014 & b0_2=4 & cnt3b { load_one_1(R2); load_one_1(R3); load_one_1(R4); load_one_1(R5); load_one_1(R8); } +:LOADM cnt3b is op13=0x0014 & b0_2=5 & cnt3b { load_one_1(R2); load_one_1(R3); load_one_1(R4); load_one_1(R5); load_one_1(R8); load_one_1(R9); } +:LOADM cnt3b is op13=0x0014 & b0_2=6 & cnt3b { load_one_1(R2); load_one_1(R3); load_one_1(R4); load_one_1(R5); load_one_1(R8); load_one_1(R9); load_one_1(R10); } +:LOADM cnt3b is op13=0x0014 & b0_2=7 & cnt3b { load_one_1(R2); load_one_1(R3); load_one_1(R4); load_one_1(R5); load_one_1(R8); load_one_1(R9); load_one_1(R10); load_one_1(R11); } + +:LOADMP cnt3b is op13=0x0015 & b0_2=0 & cnt3b { load_one_2(R2); load_one_2(R3); } +:LOADMP cnt3b is op13=0x0015 & b0_2=1 & cnt3b { load_one_2(R2); load_one_2(R3); load_one_2(R4); } +:LOADMP cnt3b is op13=0x0015 & b0_2=2 & cnt3b { load_one_2(R2); load_one_2(R3); load_one_2(R4); } +:LOADMP cnt3b is op13=0x0015 & b0_2=3 & cnt3b { load_one_2(R2); load_one_2(R3); load_one_2(R4); load_one_2(R5); } +:LOADMP cnt3b is op13=0x0015 & b0_2=4 & cnt3b { load_one_2(R2); load_one_2(R3); load_one_2(R4); load_one_2(R5); load_one_2(R8); } +:LOADMP cnt3b is op13=0x0015 & b0_2=5 & cnt3b { load_one_2(R2); load_one_2(R3); load_one_2(R4); load_one_2(R5); load_one_2(R8); load_one_2(R9); } +:LOADMP cnt3b is op13=0x0015 & b0_2=6 & cnt3b { load_one_2(R2); load_one_2(R3); load_one_2(R4); load_one_2(R5); load_one_2(R8); load_one_2(R9); load_one_2(R10); } +:LOADMP cnt3b is op13=0x0015 & b0_2=7 & cnt3b { load_one_2(R2); load_one_2(R3); load_one_2(R4); load_one_2(R5); load_one_2(R8); load_one_2(R9); load_one_2(R10); load_one_2(R11); } + +# LOADW - load word +:LOADW prp const1(prp_src1), dst1 is hi=0x9e & prp & const1 & prp_src1 & dst1 { # fmt 18 + tmp:4 = prp_src1:4 + prp:4; + dst1 = *tmp; +} +:LOADW prp2 disp14(prp_src), dst3 is op10=0x21b & prp2 & disp14 & prp_src & dst3 { # fmt 17 + tmp:4 = prp_src:4 + prp2:4 + zext(disp14); + dst3 = *tmp; +} +:LOADW disp20(src4), dst3 is op=0x0012 ; n8=12 & disp20 & src4 & dst3 { # fmt 2 + tmp:4 = zext(src4) + zext(disp20); + dst3 = *tmp; +} +:LOADW -disp20(src4), dst3 is op=0x0018 ; n8=12 & disp20 & src4 & dst3 { + tmp:4 = zext(src4) - zext(disp20); + dst3 = *tmp; +} +:LOADW disp16b(rp_src2), dst1 is hi=0x9f & rp_src2 & dst1 ; disp16b { # fmt 19 + tmp:4 = rp_src2:4 + zext(disp16b); + dst1 = *tmp; +} +:LOADW disp20(rp_src5), dst3 is op=0x0012 ; n8=13 & disp20 & rp_src5 & dst3 { # fmt 2 + tmp:4 = rp_src5:4 + zext(disp20); + dst3 = *tmp; +} +:LOADW -disp20(rp_src5), dst3 is op=0x0018 ; n8=13 & disp20 & rp_src5 & dst3 { + tmp:4 = rp_src5:4 - zext(disp20); + dst3 = *tmp; +} +:LOADW disp4(rp_src2), dst1 is op4=0x9 & disp4 & rp_src2 & dst1 { # fmt 18 + tmp:4 = rp_src2:4 + zext(disp4); + dst1 = *tmp; +} +:LOADW disp20(prp_src), dst3 is op=0x0012 ; n8=14 & disp20 & prp_src & dst3 { # fmt 2 + tmp:4 = prp_src:4 + zext(disp20); + dst3 = *tmp; +} +:LOADW abs20, dst3 is dw_hi=0x89 & abs20 & dst3 { + tmp:4 = zext(abs20); + dst3 = *tmp; +} +:LOADW rs abs20, dst3 is dw_op7=0x47 & dst3 & rs & abs20 { # fmt 13 + tmp:4 = zext(abs20) + rs:4; + dst3 = *tmp; +} +:LOADW abs24, dst3 is op=0x0012 ; n8=15 & dst3 & abs24 { # fmt 3 + dst3 = *abs24; +} + +# STORB - store low-order byte only +:STORB src, prp const1(prp_dst1) is hi=0xfe & src & prp & const1 & prp_dst1 { # fmt 18 + tmp:4 = prp_dst1:4 + prp:4; + *tmp = src:1; +} +:STORB src3, prp2 disp14(prp_dst) is op10=0x319 & src3 & prp2 & disp14 & prp_dst { # fmt 17 + tmp:4 = prp_dst:4 + prp2:4 + zext(disp14); + *tmp = src3:1; +} +:STORB src3, disp20(dst4) is op=0x0013 ; n8=4 & src3 & disp20 & dst4 { # fmt 2 + tmp:4 = zext(dst4) + zext(disp20); + *tmp = src3:1; +} +:STORB src3, -disp20(dst4) is op=0x0019 ; n8=4 & src3 & disp20 & dst4 { + tmp:4 = zext(dst4) - zext(disp20); + *tmp = src3:1; +} +:STORB src, disp16b(rp_dst) is hi=0xff & src & rp_dst ; disp16b { # fmt 19 + tmp:4 = rp_dst:4 + zext(disp16b); + *tmp = src:1; +} +:STORB src3, disp20(rp_dst5) is op=0x0013 ; n8=5 & src3 & disp20 & rp_dst5 { # fmt 2 + tmp:4 = rp_dst5:4 + zext(disp20); + *tmp = src3:1; +} +:STORB src3, -disp20(rp_dst5) is op=0x0019 ; n8=5 & src3 & disp20 & rp_dst5 { + tmp:4 = rp_dst5:4 - zext(disp20); + *tmp = src3:1; +} +:STORB src, disp4b(rp_dst) is op4=0xf & src & disp4b & rp_dst { # fmt 18 <--- + tmp:4 = rp_dst:4 + zext(disp4b); + *tmp = src:1; +} +:STORB src3, disp20(prp_dst) is op=0x0013 ; n8=6 & src3 & disp20 & prp_dst { # fmt 2 + tmp:4 = prp_dst:4 + zext(disp20); + *tmp = src3:1; +} +:STORB src3, abs20 is dw_hi=0xc8 & abs20 & src3 { + tmp:4 = zext(abs20); + *tmp = src3:1; +} +:STORB src3, rs abs20 is dw_op7=0x65 & src3 & rs & abs20 { # fmt 13 + tmp:4 = zext(abs20) + rs:4; + *tmp = src3:1; +} +:STORB src3, abs24 is op=0x0013 ; n8=7 & src3 & abs24 { # fmt 3 + *abs24 = src3:1; +} + +:STORB imm4c, prp2 disp14(prp_dst) is op10=0x218 & imm4c & prp2 & disp14 & prp_dst { # fmt 17 + tmp:4 = prp_dst:4 + prp2:4 + zext(disp14); + *tmp = imm4c; +} +:STORB imm4c, disp20(dst4) is op=0x0012 ; n8=0 & imm4c & disp20 & dst4 { # fmt 2 + tmp:4 = zext(dst4) + zext(disp20); + *tmp = imm4c; +} +:STORB imm4a, const1(rp_dst) is hi=0x82 & imm4a & const1 & rp_dst { # fmt 15 + *rp_dst:4 = imm4a; +} +:STORB imm4a, disp16b(rp_dst) is hi=0x83 & imm4a & rp_dst ; disp16b { # fmt 16 + tmp:4 = rp_dst:4 + zext(disp16b); + *tmp = imm4a; +} +:STORB imm4c, disp20(rp_dst5) is op=0x0012 ; n8=1 & imm4c & disp20 & rp_dst5 { # fmt 2 + tmp:4 = rp_dst5:4 + zext(disp20); + *tmp = imm4c; +} +:STORB imm4c, disp20(prp_dst) is op=0x0012 ; n8=2 & imm4c & disp20 & prp_dst { + tmp:4 = prp_dst:4 + zext(disp20); + *tmp = imm4c; +} +:STORB imm4b, abs20 is dw_hi=0x81 & imm4b & abs20 { # fmt 12 + tmp:4 = zext(abs20); + *tmp = imm4b; +} +:STORB imm4b, rs abs20 is dw_op7=0x42 & imm4b & rs & abs20 { # fmt 13 + tmp:4 = zext(abs20) + rs:4; + *tmp = imm4b; +} +:STORB imm4b, abs24 is op=0x0012 ; n8=3 & imm4b & abs24 { # fmt 3 + *abs24 = imm4b; +} + +# STORD - store doubleword +:STORD rp_src, prp const1(prp_dst1) is hi=0xee & rp_src & prp & const1 & prp_dst1 { # fmt 18 + tmp:4 = prp_dst1:4 + prp:4; + *tmp = rp_src; +} +:STORD rp_src4, prp2 disp14(prp_dst) is op10=0x31a & rp_src4 & prp2 & disp14 & prp_dst { # fmt 17 + tmp:4 = prp_dst:4 + prp2:4 + zext(disp14); + *tmp = rp_src4; +} +:STORD rp_src4, disp20(dst4) is op=0x0013 ; n8=8 & rp_src4 & dst4 & disp20 { # fmt 2 + tmp:4 = zext(dst4) + zext(disp20); + *tmp = rp_src4; +} +:STORD rp_src4, -disp20(dst4) is op=0x0019 ; n8=8 & rp_src4 & dst4 & disp20 { + tmp:4 = zext(dst4) - zext(disp20); + *tmp = rp_src4; +} +:STORD rp_src, disp16b(rp_dst) is hi=0xef & rp_src & rp_dst ; disp16b { # fmt 19 + tmp:4 = rp_dst:4 + zext(disp16b); + *tmp = rp_src; +} +:STORD rp_src4, disp20(rp_dst5) is op=0x0013 ; n8=9 & rp_src4 & disp20 & rp_dst5 { # fmt 2 + tmp:4 = rp_dst5:4 + zext(disp20); + *tmp = rp_src4; +} +:STORD rp_src4, -disp20(rp_dst5) is op=0x0019 ; n8=9 & rp_src4 & disp20 & rp_dst5 { + tmp:4 = rp_dst5:4 - zext(disp20); + *tmp = rp_src4; +} +:STORD rp_src, disp4(rp_dst) is op4=0xe & disp4 & rp_src & rp_dst { # fmt 18 + tmp:4 = rp_dst:4 + zext(disp4); + *tmp = rp_src; +} +:STORD rp_src4, disp20(prp_dst) is op=0x0013 ; n8=10 & rp_src4 & disp20 & prp_dst { # fmt 2 + tmp:4 = prp_dst:4 + zext(disp20); + *tmp = rp_src4; +} +:STORD rp_src4, abs20 is dw_hi=0xc7 & abs20 & rp_src4 { + tmp:4 = zext(abs20); + *tmp = rp_src4; +} +:STORD rp_src4, rs abs20 is dw_op7=0x66 & rp_src4 & rs & abs20 { + tmp:4 = zext(abs20) + rs:4; + *tmp = rp_src4; +} +:STORD rp_src4, abs24 is op=0x0013 ; n8=11 & rp_src4 & abs24 { # fmt 3 + *abs24 = rp_src4; +} + +macro store_one_1(rd) { + addr:4 = zext(R1); + *addr = rd; + R1 = R1 + 2; +} + +macro store_one_2(rd) { + addr:4 = R7R6:4; + *addr = rd; + R7R6 = R7R6 + 2; +} + +# STORM/STORMP - Store Multiple Registers to Memory +:STORM cnt3b is op13=0x0016 & b0_2=0 & cnt3b { store_one_1(R2); } +:STORM cnt3b is op13=0x0016 & b0_2=1 & cnt3b { store_one_1(R2); store_one_1(R3); } +:STORM cnt3b is op13=0x0016 & b0_2=2 & cnt3b { store_one_1(R2); store_one_1(R3); store_one_1(R4); } +:STORM cnt3b is op13=0x0016 & b0_2=3 & cnt3b { store_one_1(R2); store_one_1(R3); store_one_1(R4); store_one_1(R5); } +:STORM cnt3b is op13=0x0016 & b0_2=4 & cnt3b { store_one_1(R2); store_one_1(R3); store_one_1(R4); store_one_1(R5); store_one_1(R8); } +:STORM cnt3b is op13=0x0016 & b0_2=5 & cnt3b { store_one_1(R2); store_one_1(R3); store_one_1(R4); store_one_1(R5); store_one_1(R8); store_one_1(R9); } +:STORM cnt3b is op13=0x0016 & b0_2=6 & cnt3b { store_one_1(R2); store_one_1(R3); store_one_1(R4); store_one_1(R5); store_one_1(R8); store_one_1(R9); store_one_1(R10); } +:STORM cnt3b is op13=0x0016 & b0_2=7 & cnt3b { store_one_1(R2); store_one_1(R3); store_one_1(R4); store_one_1(R5); store_one_1(R8); store_one_1(R9); store_one_1(R10); store_one_1(R11); } + +:STORMP cnt3b is op13=0x0017 & b0_2=0 & cnt3b { store_one_2(R2); } +:STORMP cnt3b is op13=0x0017 & b0_2=1 & cnt3b { store_one_2(R2); store_one_2(R3); } +:STORMP cnt3b is op13=0x0017 & b0_2=2 & cnt3b { store_one_2(R2); store_one_2(R3); store_one_2(R4); } +:STORMP cnt3b is op13=0x0017 & b0_2=3 & cnt3b { store_one_2(R2); store_one_2(R3); store_one_2(R4); store_one_2(R5); } +:STORMP cnt3b is op13=0x0017 & b0_2=4 & cnt3b { store_one_2(R2); store_one_2(R3); store_one_2(R4); store_one_2(R5); store_one_2(R8); } +:STORMP cnt3b is op13=0x0017 & b0_2=5 & cnt3b { store_one_2(R2); store_one_2(R3); store_one_2(R4); store_one_2(R5); store_one_2(R8); store_one_2(R9); } +:STORMP cnt3b is op13=0x0017 & b0_2=6 & cnt3b { store_one_2(R2); store_one_2(R3); store_one_2(R4); store_one_2(R5); store_one_2(R8); store_one_2(R9); store_one_2(R10); } +:STORMP cnt3b is op13=0x0017 & b0_2=7 & cnt3b { store_one_2(R2); store_one_2(R3); store_one_2(R4); store_one_2(R5); store_one_2(R8); store_one_2(R9); store_one_2(R10); store_one_2(R11); } + +# STORW - store word +:STORW src, prp const1(prp_dst1) is hi=0xde & src & prp & const1 & prp_dst1 { # fmt 18 + tmp:4 = prp_dst1:4 + prp:4; + *tmp = src; +} +:STORW src3, prp2 disp14(prp_dst) is op10=0x31b & prp2 & disp14 & src3 & prp_dst { # fmt 17 + tmp:4 = prp_dst:4 + prp2:4 + zext(disp14); + *tmp = src3; +} +:STORW src3, disp20(dst4) is op=0x0013 ; n8=12 & src3 & disp20 & dst4 { # fmt 2 + tmp:4 = zext(dst4) + zext(disp20); + *tmp = src3; +} +:STORW src3, -disp20(dst4) is op=0x0019 ; n8=12 & src3 & disp20 & dst4 { + tmp:4 = zext(dst4) - zext(disp20); + *tmp = src3; +} +:STORW src, disp16b(rp_dst) is hi=0xdf & src & rp_dst ; disp16b { + tmp:4 = rp_dst:4 + zext(disp16b); + *tmp = src; +} +:STORW src3, disp20(rp_dst5) is op=0x0013 ; n8=13 & src3 & disp20 & rp_dst5 { # fmt 2 + tmp:4 = rp_dst5:4 + zext(disp20); + *tmp = src3; +} +:STORW src3, -disp20(rp_dst5) is op=0x0019 ; n8=13 & src3 & disp20 & rp_dst5 { + tmp:4 = rp_dst5:4 - zext(disp20); + *tmp = src3; +} +:STORW src, disp4(rp_dst) is op4=0xd & disp4 & src & rp_dst { # fmt 18 + tmp:4 = rp_dst:4 + zext(disp4); + *tmp = src; +} +:STORW src3, disp20(prp_dst) is op=0x0013 ; n8=14 & src3 & disp20 & prp_dst { # fmt 2 + tmp:4 = prp_dst:4 + zext(disp20); + *tmp = src3; +} +:STORW src3, abs20 is dw_hi=0xc9 & abs20 & src3 { + tmp:4 = zext(abs20); + *tmp = src3; +} +:STORW src3, rs abs20 is dw_op7=0x67 & src3 & rs & abs20 { # fmt 13 + tmp:4 = zext(abs20) + rs:4; + *tmp = src3; +} +:STORW src3, abs24 is op=0x0013 ; n8=15 & src3 & abs24 { # fmt 3 + *abs24 = src3; +} + +:STORW imm4c, prp2 disp14(prp_dst) is op10=0x318 & imm4c & prp2 & disp14 & prp_dst { # fmt 17 + tmp:4 = prp_dst:4 + prp2:4 + zext(disp14); + *:2 tmp = sext(imm4c); +} +:STORW imm4c, disp20(dst4) is op=0x0013 ; n8=0 & imm4c & disp20 & dst4 { # fmt 2 + tmp:4 = zext(dst4) + zext(disp20); + *:2 tmp = sext(imm4c); +} +:STORW imm4a, const1(rp_dst) is hi=0xc2 & imm4a & const1 & rp_dst { # fmt 15 + *:2 rp_dst:4 = sext(imm4a); +} +:STORW imm4a, disp16b(rp_dst) is hi=0xc3 & imm4a & rp_dst ; disp16b { # fmt 16 + tmp:4 = rp_dst:4 + zext(disp16b); + *:2 tmp = sext(imm4a); +} +:STORW imm4c, disp20(rp_dst5) is op=0x0013 ; n8=1 & imm4c & disp20 & rp_dst5 { # fmt 2 + tmp:4 = rp_dst5:4 + zext(disp20); + *:2 tmp = sext(imm4c); +} +:STORW imm4c, disp20(prp_dst) is op=0x0013 ; n8=2 & imm4c & disp20 & prp_dst { + tmp:4 = prp_dst:4 + zext(disp20); + *:2 tmp = sext(imm4c); +} +:STORW imm4b, abs20 is dw_hi=0xc1 & imm4b & abs20 { + tmp:4 = zext(abs20); + *:2 tmp = sext(imm4b); +} +:STORW imm4b, rs abs20 is dw_op7=0x62 & imm4b & rs & abs20 { # fmt 13 + tmp:4 = zext(abs20) + rs:4; + *:2 tmp = sext(imm4b); +} +:STORW imm4b, abs24 is op=0x0013 ; n8=3 & imm4b & abs24 { # fmt 3 + *:2 abs24 = sext(imm4b); +} + + +# MISC + +# CINV - Cache Invalidate +:CINV cinv1 is op=0x000a & cinv1 { +} +:CINV cinv2 is op=0x000b & cinv2 { +} +:CINV cinv3 is op=0x000c & cinv3 { +} +:CINV cinv4 is op=0x000d & cinv4 { +} +:CINV cinv5 is op=0x000e & cinv5 { +} +:CINV cinv6 is op=0x000f & cinv6 { +} + +# Disable Maskable Interrupts +:DI is op=0x0004 { + $(E) = 0; +} +# Enable Maskable Interrupts +:EI is op=0x0005 { + $(E) = 1; +} +# Wait for Interrupt +:WAIT is op=0x0006 { + suspend(); +} +# Enable Interrupt and Wait for Interrupt +:EIWAIT is op=0x0007 { + $(E) = 1; + suspend(); +} + + +# Reserved + +:undef is op=0x0000 { +} +:undef is op=0x0001 { +} + +:undef is op=0x0002 { +} + +:undef is op=0x0008 { +} +:undef is op=0x0009 { +} + +:undef is op=0x0010 ; w2 ; w3 { +} +:undef is op=0x0011 ; w2 ; w3 { +} +:undef is op=0x0014 ; w2 { +} +:undef is op=0x0015 ; w2 { +} +:undef is op=0x0016 ; w2 { +} +:undef is op=0x0017 ; w2 { +} + +:undef is op=0x0018 ; w2 ; w3 { +} +:undef is op=0x0019 ; w2 ; w3 { +} + +:undef is op=0x001a ; w2 ; w3 { +} +:undef is op=0x001b ; w2 ; w3 { +} +:undef is op=0x001c ; w2 ; w3 { +} +:undef is op=0x001d ; w2 ; w3 { +} +:undef is op=0x001e ; w2 ; w3 { +} +:undef is op=0x001f ; w2 ; w3 { +} + +:undef is op12=0x008 ; w2 ; w3 { +} + +:undef is op11=0x007 { +} + +:undef is op9=0x012 ; w2 { +} + +:undef is hi=0x80 { +} + +#:undef is hi=0xc0 { +#} + +:undef is op=0xffff { +} + diff --git a/python/icicle/Ghidra/Processors/CR16/data/languages/CR16C.slaspec b/python/icicle/Ghidra/Processors/CR16/data/languages/CR16C.slaspec new file mode 100644 index 0000000..1479a6c --- /dev/null +++ b/python/icicle/Ghidra/Processors/CR16/data/languages/CR16C.slaspec @@ -0,0 +1,4 @@ + +define endian=little; + +@include "CR16C.sinc" diff --git a/python/icicle/Ghidra/Processors/DATA/data/languages/data-be-64.slaspec b/python/icicle/Ghidra/Processors/DATA/data/languages/data-be-64.slaspec new file mode 100644 index 0000000..ffeb7e9 --- /dev/null +++ b/python/icicle/Ghidra/Processors/DATA/data/languages/data-be-64.slaspec @@ -0,0 +1,5 @@ +@define ENDIAN "big" + +@define RAMSIZE "8" + +@include "data.sinc" diff --git a/python/icicle/Ghidra/Processors/DATA/data/languages/data-le-64.slaspec b/python/icicle/Ghidra/Processors/DATA/data/languages/data-le-64.slaspec new file mode 100644 index 0000000..e3079e9 --- /dev/null +++ b/python/icicle/Ghidra/Processors/DATA/data/languages/data-le-64.slaspec @@ -0,0 +1,5 @@ +@define ENDIAN "little" + +@define RAMSIZE "8" + +@include "data.sinc" diff --git a/python/icicle/Ghidra/Processors/DATA/data/languages/data-ptr16.cspec b/python/icicle/Ghidra/Processors/DATA/data/languages/data-ptr16.cspec new file mode 100644 index 0000000..f7ea4e0 --- /dev/null +++ b/python/icicle/Ghidra/Processors/DATA/data/languages/data-ptr16.cspec @@ -0,0 +1,31 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/DATA/data/languages/data-ptr32.cspec b/python/icicle/Ghidra/Processors/DATA/data/languages/data-ptr32.cspec new file mode 100644 index 0000000..9704f7d --- /dev/null +++ b/python/icicle/Ghidra/Processors/DATA/data/languages/data-ptr32.cspec @@ -0,0 +1,31 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/DATA/data/languages/data-ptr64.cspec b/python/icicle/Ghidra/Processors/DATA/data/languages/data-ptr64.cspec new file mode 100644 index 0000000..28863f9 --- /dev/null +++ b/python/icicle/Ghidra/Processors/DATA/data/languages/data-ptr64.cspec @@ -0,0 +1,31 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/DATA/data/languages/data.ldefs b/python/icicle/Ghidra/Processors/DATA/data/languages/data.ldefs new file mode 100644 index 0000000..2f885a1 --- /dev/null +++ b/python/icicle/Ghidra/Processors/DATA/data/languages/data.ldefs @@ -0,0 +1,33 @@ + + + + + + Raw Data File (Little Endian) + + + + + + + Raw Data File (Big Endian) + + + + + + diff --git a/python/icicle/Ghidra/Processors/DATA/data/languages/data.pspec b/python/icicle/Ghidra/Processors/DATA/data/languages/data.pspec new file mode 100644 index 0000000..be3ce4f --- /dev/null +++ b/python/icicle/Ghidra/Processors/DATA/data/languages/data.pspec @@ -0,0 +1,5 @@ + + + + + diff --git a/python/icicle/Ghidra/Processors/DATA/data/languages/data.sinc b/python/icicle/Ghidra/Processors/DATA/data/languages/data.sinc new file mode 100644 index 0000000..41a0fdc --- /dev/null +++ b/python/icicle/Ghidra/Processors/DATA/data/languages/data.sinc @@ -0,0 +1,28 @@ +define endian = $(ENDIAN); + +define alignment = 1; + +define space ram type=ram_space size=8 default; + +define space register type=register_space size=4; + +# # # # # # # # # # # # # # # # # # # # # # # # # # # # +# AT LEAST ONE REGISTER, AND STACK POINTER ARE REQUIRED +# # # # # # # # # # # # # # # # # # # # # # # # # # # # + +define register offset=0x0 size=8 [ sp r0 ]; + +# Define context bits +define register offset=0x100 size=4 contextreg; + +define context contextreg + test=(0,0) +; + +# # # # # # # # # # # # # # # # # # # # # # # # # # # # +# AT LEAST ONE INSTRUCTION IS REQUIRED +# # # # # # # # # # # # # # # # # # # # # # # # # # # # + +:nop is test=1 unimpl + +# # # # # # # # # # # # # # # # # # # # # # # # # # # # diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik.ldefs b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik.ldefs new file mode 100644 index 0000000..21bcd33 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik.ldefs @@ -0,0 +1,164 @@ + + + + + + + Dalvik Base + + + + + Dalvik Base + + + + + Dalvik DEX KitKat + + + + + Dalvik ODEX KitKat + + + + + Dalvik DEX Lollipop + + + + + Dalvik DEX Marshmallow + + + + + Dalvik DEX Nougat + + + + + Dalvik DEX Oreo + + + + + Dalvik DEX Pie + + + + + Dalvik DEX Android10 + + + + + Dalvik DEX Android11 + + + + + Dalvik DEX Android12 + + + + + + Dalvik DEX Android13 + + + + diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik.opinion b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik.opinion new file mode 100644 index 0000000..e19ce57 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik.opinion @@ -0,0 +1,54 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_Base.cspec b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_Base.cspec new file mode 100644 index 0000000..ba8bb33 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_Base.cspec @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_Base.pspec b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_Base.pspec new file mode 100644 index 0000000..92e9649 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_Base.pspec @@ -0,0 +1,56 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_Base.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_Base.sinc new file mode 100644 index 0000000..63a7e01 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_Base.sinc @@ -0,0 +1,2025 @@ +#------------------------------------------------------------------------------------ +# Sleigh specification file for DALVIK VM +#------------------------------------------------------------------------------------ + +# Source: +# https://android.googlesource.com/platform/art/+/[...]/runtime/dex_instruction_list.h +# where [...] is the actual Android version name (ie "oreo-release") + +define endian=little; + +define alignment=1; + +@define CPOOL_METHOD "0:4" +@define CPOOL_FIELD "1:4" +@define CPOOL_STATIC_FIELD "2:4" +@define CPOOL_STATIC_METHOD "3:4" +@define CPOOL_STRING "4:4" +@define CPOOL_CLASSREF "5:4" +@define CPOOL_ARRAYLENGTH "6:4" +@define CPOOL_SUPER "7:4" +@define CPOOL_INSTANCEOF "8:4" + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +define space ram type=ram_space size=4 default; + +#define space object type=ram_space size=4; # object instances + +#define space method type=ram_space size=4; # method references + +#define space field type=ram_space size=4; # field references + +define space register type=register_space size=4; + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +define register offset=0x0 size=4 [ sp fp resultreg ]; +define register offset=0x8 size=8 [ resultregw ]; + +define register offset=0x100 size=4 # Special input registers +[ + iv0 iv1 iv2 iv3 iv4 iv5 iv6 iv7 + iv8 iv9 iv10 iv11 iv12 iv13 iv14 iv15 +]; + +define register offset=0x104 size=8 # Wide input registers ODD +[ + ivw1 ivw3 ivw5 ivw7 ivw9 ivw11 ivw13 +]; + +define register offset=0x100 size=8 # Wide input registers EVEN +[ + ivw0 ivw2 ivw4 ivw6 ivw8 ivw10 ivw12 ivw14 +]; + +define register offset=0x1000 size=4 +[ + v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 + v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 + v32 v33 v34 v35 v36 v37 v38 v39 v40 v41 v42 v43 v44 v45 v46 v47 + v48 v49 v50 v51 v52 v53 v54 v55 v56 v57 v58 v59 v60 v61 v62 v63 + v64 v65 v66 v67 v68 v69 v70 v71 v72 v73 v74 v75 v76 v77 v78 v79 + v80 v81 v82 v83 v84 v85 v86 v87 v88 v89 v90 v91 v92 v93 v94 v95 + v96 v97 v98 v99 v100 v101 v102 v103 v104 v105 v106 v107 v108 v109 v110 v111 + v112 v113 v114 v115 v116 v117 v118 v119 v120 v121 v122 v123 v124 v125 v126 v127 + v128 v129 v130 v131 v132 v133 v134 v135 v136 v137 v138 v139 v140 v141 v142 v143 + v144 v145 v146 v147 v148 v149 v150 v151 v152 v153 v154 v155 v156 v157 v158 v159 + v160 v161 v162 v163 v164 v165 v166 v167 v168 v169 v170 v171 v172 v173 v174 v175 + v176 v177 v178 v179 v180 v181 v182 v183 v184 v185 v186 v187 v188 v189 v190 v191 + v192 v193 v194 v195 v196 v197 v198 v199 v200 v201 v202 v203 v204 v205 v206 v207 + v208 v209 v210 v211 v212 v213 v214 v215 v216 v217 v218 v219 v220 v221 v222 v223 + v224 v225 v226 v227 v228 v229 v230 v231 v232 v233 v234 v235 v236 v237 v238 v239 + v240 v241 v242 v243 v244 v245 v246 v247 v248 v249 v250 v251 v252 v253 v254 v255 +]; + +define register offset=0x1004 size=8 # ODD NUMBER WIDE REGISTERS +[ + vw1 vw3 vw5 vw7 vw9 vw11 vw13 vw15 + vw17 vw19 vw21 vw23 vw25 vw27 vw29 vw31 + vw33 vw35 vw37 vw39 vw41 vw43 vw45 vw47 + vw49 vw51 vw53 vw55 vw57 vw59 vw61 vw63 + vw65 vw67 vw69 vw71 vw73 vw75 vw77 vw79 + vw81 vw83 vw85 vw87 vw89 vw91 vw93 vw95 + vw97 vw99 vw101 vw103 vw105 vw107 vw109 vw111 + vw113 vw115 vw117 vw119 vw121 vw123 vw125 vw127 + vw129 vw131 vw133 vw135 vw137 vw139 vw141 vw143 + vw145 vw147 vw149 vw151 vw153 vw155 vw157 vw159 + vw161 vw163 vw165 vw167 vw169 vw171 vw173 vw175 + vw177 vw179 vw181 vw183 vw185 vw187 vw189 vw191 + vw193 vw195 vw197 vw199 vw201 vw203 vw205 vw207 + vw209 vw211 vw213 vw215 vw217 vw219 vw221 vw223 + vw225 vw227 vw229 vw231 vw233 vw235 vw237 vw239 + vw241 vw243 vw245 vw247 vw249 vw251 vw253 +]; + +define register offset=0x1000 size=8 # EVEN NUMBER WIDE REGISTERS +[ + vw0 vw2 vw4 vw6 vw8 vw10 vw12 vw14 + vw16 vw18 vw20 vw22 vw24 vw26 vw28 vw30 + vw32 vw34 vw36 vw38 vw40 vw42 vw44 vw46 + vw48 vw50 vw52 vw54 vw56 vw58 vw60 vw62 + vw64 vw66 vw68 vw70 vw72 vw74 vw76 vw78 + vw80 vw82 vw84 vw86 vw88 vw90 vw92 vw94 + vw96 vw98 vw100 vw102 vw104 vw106 vw108 vw110 + vw112 vw114 vw116 vw118 vw120 vw122 vw124 vw126 + vw128 vw130 vw132 vw134 vw136 vw138 vw140 vw142 + vw144 vw146 vw148 vw150 vw152 vw154 vw156 vw158 + vw160 vw162 vw164 vw166 vw168 vw170 vw172 vw174 + vw176 vw178 vw180 vw182 vw184 vw186 vw188 vw190 + vw192 vw194 vw196 vw198 vw200 vw202 vw204 vw206 + vw208 vw210 vw212 vw214 vw216 vw218 vw220 vw222 + vw224 vw226 vw228 vw230 vw232 vw234 vw236 vw238 + vw240 vw242 vw244 vw246 vw248 vw250 vw252 vw254 +]; + +# TODO: +# 1) test accessing register space past v255. e.g. v12345. + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +define token instruction_byte ( 8 ) + inst0 = ( 0, 7 ) +; + +define token instruction_byte_w_padding ( 16 ) + inst1 = ( 0, 7 ) + inst1_padding = ( 0, 15 ) +; + +define token instruction_operands_4_4 ( 8 ) + A_BITS_0_3 = (0,3) + B_BITS_0_3 = (0,3) + A_BITS_4_7 = (4,7) + B_BITS_4_7 = (4,7) + B_BITS_4_7_S = (4,7) signed +; + +define token instruction_operands_8 ( 8 ) + A_BITS_0_7 = (0,7) + A_BITS_0_7_S = (0,7) signed + B_BITS_0_7 = (0,7) + B_BITS_0_7_S = (0,7) signed + C_BITS_0_7 = (0,7) + C_BITS_0_7_S = (0,7) signed +; + +define token instruction_operands_16 ( 16 ) + A_BITS_0_15 = (0,15) + A_BITS_0_15_S = (0,15) signed + B_BITS_0_15 = (0,15) + B_BITS_0_15_S = (0,15) signed + C_BITS_0_15 = (0,15) + C_BITS_0_15_S = (0,15) signed +; + +define token instruction_operands_32 ( 32 ) + A_BITS_0_31 = (0,31) + A_BITS_0_31_S = (0,31) signed + B_BITS_0_31 = (0,31) + B_BITS_0_31_S = (0,31) signed + C_BITS_0_31 = (0,31) + C_BITS_0_31_S = (0,31) signed +; + +define token invoke_operands ( 40 ) + N_PARAMS = ( 4, 7) + PARAM_G = ( 0, 3) + METHOD_INDEX = ( 8,23) + VTABLE_OFFSET = ( 8,23) + INLINE = ( 8,23) + PARAM_D = (28,31) + PARAM_C = (24,27) + PARAM_F = (36,39) + PARAM_E = (32,35) +; + +define token array_operands ( 40 ) + N_ELEMENTS = ( 4, 7) + ELEMENT_G = ( 0, 3) + TYPE_INDEX = ( 8,23) + ELEMENT_D = (28,31) + ELEMENT_C = (24,27) + ELEMENT_F = (36,39) + ELEMENT_E = (32,35) +; + +define token CONST16 ( 16 ) # one 16 constant + constant16 = ( 0,15 ) + constant16s = ( 0,15 ) signed +; + +define token CONST32 ( 32 ) # one 32 constant + constant32 = ( 0,31 ) + constant32s = ( 0,31 ) signed +; + +define token CONST64 ( 64 ) # one 64 constant + constant64 = ( 0,63 ) +; + +# add "8" to skip over "fp" and "sp" !! + +registerA4: reg is A_BITS_0_3 [ reg = (A_BITS_0_3 * 4) + 0x1000; ] { export *[register]:4 reg; } +registerA8: reg is A_BITS_0_7 [ reg = (A_BITS_0_7 * 4) + 0x1000; ] { export *[register]:4 reg; } +registerA16: reg is A_BITS_0_15 [ reg = (A_BITS_0_15 * 4) + 0x1000; ] { export *[register]:4 reg; } + +registerA4w: reg is A_BITS_0_3 [ reg = (A_BITS_0_3 * 4) + 0x1000; ] { export *[register]:8 reg; } +registerA8w: reg is A_BITS_0_7 [ reg = (A_BITS_0_7 * 4) + 0x1000; ] { export *[register]:8 reg; } +registerA16w: reg is A_BITS_0_15 [ reg = (A_BITS_0_15 * 4) + 0x1000; ] { export *[register]:8 reg; } + +registerB4: reg is B_BITS_4_7 [ reg = (B_BITS_4_7 * 4) + 0x1000; ] { export *[register]:4 reg; } +registerB8: reg is B_BITS_0_7 [ reg = (B_BITS_0_7 * 4) + 0x1000; ] { export *[register]:4 reg; } +registerB16: reg is B_BITS_0_15 [ reg = (B_BITS_0_15 * 4) + 0x1000; ] { export *[register]:4 reg; } + +registerB4w: reg is B_BITS_4_7 [ reg = (B_BITS_4_7 * 4) + 0x1000; ] { export *[register]:8 reg; } +registerB8w: reg is B_BITS_0_7 [ reg = (B_BITS_0_7 * 4) + 0x1000; ] { export *[register]:8 reg; } +registerB16w: reg is B_BITS_0_15 [ reg = (B_BITS_0_15 * 4) + 0x1000; ] { export *[register]:8 reg; } + +registerC8: reg is C_BITS_0_7 [ reg = (C_BITS_0_7 * 4) + 0x1000; ] { export *[register]:4 reg; } +registerC16: reg is C_BITS_0_15 [ reg = (C_BITS_0_15 * 4) + 0x1000; ] { export *[register]:4 reg; } +registerC32: reg is C_BITS_0_31 [ reg = (C_BITS_0_31 * 4) + 0x1000; ] { export *[register]:4 reg; } + + +registerC8w: reg is C_BITS_0_7 [ reg = (C_BITS_0_7 * 4) + 0x1000; ] { export *[register]:8 reg; } +registerC16w: reg is C_BITS_0_15 [ reg = (C_BITS_0_15 * 4) + 0x1000; ] { export *[register]:8 reg; } +registerC32w: reg is C_BITS_0_31 [ reg = (C_BITS_0_31 * 4) + 0x1000; ] { export *[register]:8 reg; } + +regParamC: reg is PARAM_C [ reg = (PARAM_C * 4) + 0x1000; ] { export *[register]:4 reg; } +regParamD: reg is PARAM_D [ reg = (PARAM_D * 4) + 0x1000; ] { export *[register]:4 reg; } +regParamE: reg is PARAM_E [ reg = (PARAM_E * 4) + 0x1000; ] { export *[register]:4 reg; } +regParamF: reg is PARAM_F [ reg = (PARAM_F * 4) + 0x1000; ] { export *[register]:4 reg; } +regParamG: reg is PARAM_G [ reg = (PARAM_G * 4) + 0x1000; ] { export *[register]:4 reg; } + +regElemC: reg is ELEMENT_C [ reg = (ELEMENT_C * 4) + 0x1000; ] { export *[register]:4 reg; } +regElemD: reg is ELEMENT_D [ reg = (ELEMENT_D * 4) + 0x1000; ] { export *[register]:4 reg; } +regElemE: reg is ELEMENT_E [ reg = (ELEMENT_E * 4) + 0x1000; ] { export *[register]:4 reg; } +regElemF: reg is ELEMENT_F [ reg = (ELEMENT_F * 4) + 0x1000; ] { export *[register]:4 reg; } +regElemG: reg is ELEMENT_G [ reg = (ELEMENT_G * 4) + 0x1000; ] { export *[register]:4 reg; } + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +rel16: reloc is A_BITS_0_15_S [ reloc = inst_start + ( A_BITS_0_15_S * 2 ); ] { export *[ram]:32 reloc; } + +goto8: reloc is A_BITS_0_7_S [ reloc = inst_start + ( A_BITS_0_7_S * 2 ); ] { export *[ram]:8 reloc; } +goto16: reloc is A_BITS_0_15_S [ reloc = inst_start + ( A_BITS_0_15_S * 2 ); ] { export *[ram]:16 reloc; } +goto32: reloc is A_BITS_0_31_S [ reloc = inst_start + ( A_BITS_0_31_S ); ] { export *[ram]:32 reloc; } + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Special op which injects correct p-code for invoke*_range instructions +# It takes two arguments: 1) is the number of parameters for the method 2) is the starting register +define pcodeop moveRangeToIV; + +define pcodeop monitorEnter; +define pcodeop monitorExit; + +define pcodeop checkCast; + +define pcodeop throwException; + +define pcodeop getStaticFieldVolatile; +define pcodeop setStaticFieldVolatile; + +define pcodeop getInstanceFieldQuick; +define pcodeop getInstanceFieldVolatile; +define pcodeop setInstanceFieldQuick; +define pcodeop setInstanceFieldVolatile; + +define pcodeop filledNewArray; +define pcodeop filledNewArrayRange; + +define pcodeop invokeSuperQuick; +define pcodeop invokeSuperQuickRange; +define pcodeop invokeVirtualQuick; +define pcodeop invokeVirtualQuickRange; + +define pcodeop switchAssist; + +define pcodeop breakpoint; + +#SOURCE: https://android.googlesource.com/platform/art/+/kitkat-dev/runtime/dex_instruction_list.h + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Waste cycles. + +:nop is inst0=0x00 +{ + #no pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Move the contents of one non-object register to another. +# +# A: destination register (4 bits) +# B: source register (4 bits) + +:move registerA4,registerB4 is inst0=0x01 ; registerA4 & registerB4 +{ + registerA4 = registerB4; +} + +# Move the contents of one non-object register to another. +# +# A: destination register (8 bits) +# B: source register (16 bits) + +:move_from_16 registerA8,registerB16 is inst0=0x02 ; registerA8 ; registerB16 +{ + registerA8 = registerB16; +} + +# Move the contents of one non-object register to another. +# +# A: destination register (16 bits) +# B: source register (16 bits) + +:move_16 registerA16,registerB16 is inst1=0x03 & inst1_padding ; registerA16 ; registerB16 +{ + registerA16 = registerB16; +} + +# Move the contents of one register-pair to another. +# +# A: destination register pair (4 bits) +# B: source register pair (4 bits) + +:move_wide registerA4w,registerB4w is inst0=0x04 ; registerA4w & registerB4w +{ + registerA4w = registerB4w; +} + +# Move the contents of one register-pair to another. +# +# A: destination register pair (8 bits) +# B: source register pair (16 bits) + +:move_wide_from_16 registerA8w,registerB16w is inst0=0x05 ; registerA8w ; registerB16w +{ + registerA8w = registerB16w; +} + +# Move the contents of one register-pair to another. +# +# A: destination register pair (16 bits) +# B: source register pair (16 bits) + +:move_wide_16 registerA16w,registerB16w is inst0=0x06 ; registerA16w ; registerB16w +{ + registerA16w = registerB16w; +} + +# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # +# +# Move the contents of one object-bearing register to another. +# +# A: destination register (4 bits) +# B: source register (4 bits) + +:move_object registerA4,registerB4 is inst0=0x07 ; registerA4 & registerB4 +{ + registerA4 = registerB4; +} + +# Move the contents of one object-bearing register to another. +# +# A: destination register (8 bits) +# B: source register (16 bits) + +:move_object_from_16 registerA8,registerB16 is inst0=0x08 ; registerA8 ; registerB16 +{ + registerA8 = registerB16; +} + +# Move the contents of one object-bearing register to another. +# +# A: destination register (16 bits) +# B: source register (16 bits) + +:move_object_16 registerA16,registerB16 is inst1=0x09 & inst1_padding ; registerA16 ; registerB16 +{ + registerA16 = registerB16; +} + +# Move the single-word non-object result of the most recent invoke-kind +# into the indicated register. This must be done as the instruction +# immediately after an invoke-kind whose (single-word, non-object) +# result is not to be ignored; anywhere else is invalid. +# +# A: destination register (8 bits) + +:move_result registerA8 is inst0=0x0a ; registerA8 +{ + registerA8 = resultreg; +} + +# Move the double-word result of the most recent invoke-kind into +# the indicated register pair. This must be done as the instruction +# immediately after an invoke-kind whose (double-word) result is +# not to be ignored; anywhere else is invalid. +# +# A: destination register pair (8 bits) + +:move_result_wide registerA8w is inst0=0x0b ; registerA8w +{ + registerA8w = resultregw; +} + +# Move the object result of the most recent invoke-kind into +# the indicated register. This must be done as the instruction +# immediately after an invoke-kind or filled-new-array whose +# (object) result is not to be ignored; anywhere else is invalid. +# +# A: destination register (8 bits) + +:move_result_object registerA8 is inst0=0x0c ; registerA8 +{ + registerA8 = resultreg; +} + +# Save a just-caught exception into the given register. This must +# be the first instruction of any exception handler whose caught +# exception is not to be ignored, and this instruction must only +# ever occur as the first instruction of an exception handler; +# anywhere else is invalid. +# +# A: destination register (8 bits) + +:move_exception registerA8 is inst0=0x0d ; registerA8 +{ + #TODO pCode + # this requires state!? +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Return from a void method. + +:return_void is inst1=0x0e & inst1_padding +{ + return [sp]; +} + +# Return from a single-width (32-bit) non-object value-returning method. +# +# A: return value register (8 bits) + +:return registerA8 is inst0=0x0f ; registerA8 +{ + resultreg = registerA8; + return [sp]; +} + +# Return from a double-width (64-bit) value-returning method. +# +# A: return value register-pair (8 bits) + +:return_wide registerA8w is inst0=0x10 ; registerA8w +{ + resultregw = registerA8w; + return [sp]; +} + +# Return from an object-returning method. +# +# A: return value register (8 bits) + +:return_object registerA8 is inst0=0x11 ; registerA8 +{ + resultreg = registerA8; + return [sp]; +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Move the given literal value (sign-extended to 32 bits) into the specified register. +# +# A: destination register (4 bits) +# B: signed int (4 bits) + +:const_4 registerA4,B_BITS_4_7_S is inst0=0x12 ; registerA4 & B_BITS_4_7_S +{ + registerA4 = sext( B_BITS_4_7_S:4) ; +} + +# Move the given literal value (sign-extended to 32 bits) into the specified register. +# +# A: destination register (8 bits) +# B: signed int (16 bits) + +:const_16 registerA8,B_BITS_0_15_S is inst0=0x13 ; registerA8 ; B_BITS_0_15_S +{ + registerA8 = sext( B_BITS_0_15_S:4 ); +} + +# Move the given literal value into the specified register. +# +# A: destination register (8 bits) +# B: arbitrary 32-bit constant + +:"const" registerA8,constant32 is inst0=0x14 ; registerA8 ; constant32 +{ + registerA8 = constant32; +} + +# Move the given literal value (right-zero-extended to 32 bits) into the specified register. +# +# A: destination register (8 bits) +# B: signed int (16 bits) + +:const_high_16 registerA8,B_BITS_0_15 is inst0=0x15 ; registerA8 ; B_BITS_0_15 +{ + registerA8 = B_BITS_0_15:4 << 16; +} + +# Move the given literal value (sign-extended to 64 bits) into the specified register-pair. +# +# A: destination register (8 bits) +# B: signed int (16 bits) + +:const_wide_16 registerA8w,constant16s is inst0=0x16 ; registerA8w ; constant16s +{ + registerA8w = sext( constant16s:2 ); +} + +# Move the given literal value (sign-extended to 64 bits) into the specified register-pair. +# +# A: destination register (8 bits) +# B: signed int (32 bits) + +:const_wide_32 registerA8w,constant32s is inst0=0x17 ; registerA8w ; constant32s +{ + registerA8w = sext( constant32s:4 ); +} + +# Move the given literal value into the specified register-pair. +# +# A: destination register (8 bits) +# B: arbitrary double-width (64-bit) constant + +:const_wide registerA8w,constant64 is inst0=0x18 ; registerA8w ; constant64 +{ + registerA8w = constant64; +} + +# Move the given literal value (right-zero-extended to 64 bits) into the specified register-pair. +# +# A: destination register (8 bits) +# B: signed int (16 bits) + +:const_wide_high_16 registerA8w,B_BITS_0_15_S is inst0=0x19 ; registerA8w ; B_BITS_0_15_S +{ + registerA8w = B_BITS_0_15_S << 48; +} + +# Move a reference to the string specified by the given index into the specified register. +# +# A: destination register (8 bits) +# B: string index + +:const_string registerA8,B_BITS_0_15 is inst0=0x1a ; registerA8 ; B_BITS_0_15 +{ + registerA8 = cpool(0:4, B_BITS_0_15:4, $(CPOOL_STRING)); +} + +# Move a reference to the string specified by the given index into the specified register. +# +# A: destination register (8 bits) +# B: string index + +:const_string_jumbo registerA8,B_BITS_0_31 is inst0=0x1b ; registerA8 ; B_BITS_0_31 +{ + registerA8 = cpool(0:4, B_BITS_0_31:4, $(CPOOL_STRING)); +} + +# Move a reference to the class specified by the given index into the +# specified register. In the case where the indicated type is primitive, +# this will store a reference to the primitive type's degenerate class. +# +# A: destination register (8 bits) +# B: type index + +:const_class registerA8,B_BITS_0_15 is inst0=0x1c ; registerA8 ; B_BITS_0_15 +{ + registerA8 = cpool( 0:4, B_BITS_0_15:4, $(CPOOL_CLASSREF)); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Acquire the monitor for the indicated object. +# +# A: reference-bearing register (8 bits) + +:monitor_enter registerA8 is inst0=0x1d ; registerA8 +{ + monitorEnter( registerA8 ); +} + +# Release the monitor for the indicated object. +# +# A: reference-bearing register (8 bits) + +:monitor_exit registerA8 is inst0=0x1e ; registerA8 +{ + monitorExit( registerA8 ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Throw a ClassCastException if the reference in the given register +# cannot be cast to the indicated type. +# +# A: reference-bearing register (8 bits) +# B: type index (16 bits) + +:check_cast registerA8,B_BITS_0_15 is inst0=0x1f ; registerA8 ; B_BITS_0_15 +{ + checkCast( registerA8, cpool( 0:4, B_BITS_0_15:4, $(CPOOL_CLASSREF)) ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Store in the given destination register 1 if the indicated reference +# is an instance of the given type, or 0 if not. +# +# A: destination register (4 bits) +# B: reference-bearing register (4 bits) +# C: type index (16 bits) + +:instance_of registerA4,registerB4,C_BITS_0_15 is inst0=0x20 ; registerA4 & registerB4 ; C_BITS_0_15 +{ + res:1 = cpool( registerB4, C_BITS_0_15:4, $(CPOOL_INSTANCEOF) ); + registerA4 = zext( res ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Store in the given destination register the length of the indicated array, in entries +# +# A: destination register (4 bits) +# B: array reference-bearing register (4 bits) + +:array_length registerA4,registerB4 is inst0=0x21 ; registerA4 & registerB4 +{ + registerA4 = cpool( registerB4, 0:4, $(CPOOL_ARRAYLENGTH) ); +} + +# Construct a new instance of the indicated type, storing a reference +# to it in the destination. The type must refer to a non-array class. +# +# A: destination register (8 bits) +# B: type index + +:new_instance registerA8,B_BITS_0_15 is inst0=0x22 ; registerA8 ; B_BITS_0_15 +{ + registerA8 = newobject( cpool( 0:4, B_BITS_0_15:4, $(CPOOL_CLASSREF)) ); +} + +# Construct a new array of the indicated type and size. The type must be an array type. +# +# A: destination register (8 bits) +# B: size register +# C: type index + +:new_array registerA4,registerB4,C_BITS_0_15 is inst0=0x23 ; registerA4 & registerB4 ; C_BITS_0_15 +{ + registerA4 = newobject( cpool( 0:4, C_BITS_0_15:4, $(CPOOL_CLASSREF)), registerB4 ); +} + +# Construct an array of the given type and size, filling it with the supplied +# contents. The type must be an array type. The array's contents must be +# single-word (that is, no arrays of long or double, but reference types are +# acceptable). The constructed instance is stored as a "result" in the same +# way that the method invocation instructions store their results, so the +# constructed instance must be moved to a register with an immediately +# subsequent move-result-object instruction (if it is to be used). +# +# A: array size and argument word count (4 bits) +# B: type index (16 bits) +# C..G: argument registers (4 bits each) + +:filled_new_array TYPE_INDEX is inst0=0x24 ; N_ELEMENTS = 0 & TYPE_INDEX & regElemC & regElemD & regElemE & regElemF & regElemG +{ + #TODO pCode + filledNewArray( TYPE_INDEX:4 ); +} +:filled_new_array TYPE_INDEX,regElemC is inst0=0x24 ; N_ELEMENTS = 1 & TYPE_INDEX & regElemC & regElemD & regElemE & regElemF & regElemG +{ + #TODO pCode + filledNewArray( TYPE_INDEX:4, regElemC ); +} +:filled_new_array TYPE_INDEX,regElemC,regElemD is inst0=0x24 ; N_ELEMENTS = 2 & TYPE_INDEX & regElemC & regElemD & regElemE & regElemF & regElemG +{ + #TODO pCode + filledNewArray( TYPE_INDEX:4, regElemC, regElemD ); +} +:filled_new_array TYPE_INDEX,regElemC,regElemD,regElemE is inst0=0x24 ; N_ELEMENTS = 3 & TYPE_INDEX & regElemC & regElemD & regElemE & regElemF & regElemG +{ + #TODO pCode + filledNewArray( TYPE_INDEX:4, regElemC, regElemD, regElemE ); +} +:filled_new_array TYPE_INDEX,regElemC,regElemD,regElemE,regElemF is inst0=0x24 ; N_ELEMENTS = 4 & TYPE_INDEX & regElemC & regElemD & regElemE & regElemF & regElemG +{ + #TODO pCode + filledNewArray( TYPE_INDEX:4, regElemC, regElemD, regElemE, regElemF ); +} +:filled_new_array TYPE_INDEX,regElemC,regElemD,regElemE,regElemF,regElemG is inst0=0x24 ; N_ELEMENTS = 5 & TYPE_INDEX & regElemC & regElemD & regElemE & regElemF & regElemG +{ + #TODO pCode + filledNewArray( TYPE_INDEX:4, regElemC, regElemD, regElemE, regElemF, regElemG ); +} + +# Construct an array of the given type and size, filling it with +# the supplied contents. Clarifications and restrictions are the +# same as filled-new-array, described above. +# +# A: array size and argument word count (8 bits) +# B: type index (16 bits) +# C: first argument register (16 bits) +# N = A + C - 1 + +:filled_new_array_range A_BITS_0_7,B_BITS_0_15,registerC16 is inst0=0x25 ; A_BITS_0_7 ; B_BITS_0_15 ; registerC16 +{ + #TODO pCode + filledNewArrayRange( A_BITS_0_7:4, B_BITS_0_15:4, registerC16 ); +} + +# Fill the given array with the indicated data. The reference must +# be to an array of primitives, and the data table must match it in type +# and must contain no more elements than will fit in the array. That is, +# the array may be larger than the table, and if so, only the initial +# elements of the array are set, leaving the remainder alone. +# +# A: array reference (8 bits) +# B: signed "branch" offset to table data pseudo-instruction (32 bits) + +:fill_array_data registerA8,B_BITS_0_31_S is inst0=0x26 ; registerA8 ; B_BITS_0_31_S +{ + #TODO pCode +# fillArrayData +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Throw the indicated exception. +# +# A: exception-bearing register (8 bits) + +:throw registerA8 is inst0=0x27 ; registerA8 +{ + throwException( registerA8 ); + return [registerA8];#TODO is the best way to return?? +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Unconditionally jump to the indicated instruction. +# +# A: signed branch offset (8 bits) + +:goto goto8 is inst0=0x28 ; goto8 +{ + goto goto8; +} + +# Unconditionally jump to the indicated instruction. +# +# A: signed branch offset (16 bits) + +:goto_16 goto16 is inst1=0x29 & inst1_padding ; goto16 +{ + goto goto16; +} + +# Unconditionally jump to the indicated instruction. +# +# A: signed branch offset (32 bits) + +:goto_32 goto32 is inst1=0x2a & inst1_padding ; goto32 +{ + goto goto32; +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Jump to a new instruction based on the value in the given register, +# using a table of offsets corresponding to each value in a particular +# integral range, or fall through to the next instruction if there is no match. +# +# A: register to test +# B: signed "branch" offset to table data pseudo-instruction (32 bits) +# +# NOTE: Offset (B) and destinations must be multiplied by 2. + +# TODO use disassembly action?? + +:packed_switch registerA8,B_BITS_0_31_S is inst0=0x2b ; registerA8 ; B_BITS_0_31_S +{ + distance:4 = B_BITS_0_31_S * 2; + ident:4 = *[ram] ( inst_start + distance ); + size2:2 = *[ram] ( inst_start + distance + 2 ); + sze:4 = zext( size2 ); + first_key:4 = *[ram] ( inst_start + distance + 2 + 2 ); + + if ( registerA8 < first_key ) goto inst_next; + if ( registerA8 >= ( first_key + sze ) ) goto inst_next; + + targets:4 = ( inst_start + distance + 2 + 2 + 4 ); + delta:4 = ( registerA8 ) - ( first_key ); # which index into target + value:4 = *[ram] ( targets + ( delta * 4 ) ); + address:4 = ( inst_start + ( value * 2 ) ); + + goto [ address ]; +} + +# Jump to a new instruction based on the value in the given register, +# using an ordered table of value-offset pairs, or fall through to the +# next instruction if there is no match. +# +# A: register to test +# B: signed "branch" offset to table data pseudo-instruction (32 bits) +# +# NOTE: Offset (B) and destinations must be multiplied by 2. + +:sparse_switch registerA8,B_BITS_0_31_S is inst0=0x2c ; registerA8 ; B_BITS_0_31_S +{ + distance:4 = B_BITS_0_31_S * 2; + temp:4 = inst_start; + size2:2 = *[ram] ( temp + 2 + distance); + sze:4 = zext( size2 ); + defaultPos:4 = inst_next; + + + address:4 = switchAssist( registerA8, sze, defaultPos, temp, distance ); + goto [ address ]; +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Perform the indicated floating point or long comparison, +# setting a to 0 if b == c, 1 if b > c, or -1 if b < c. +# The "bias" listed for the floating point operations indicates +# how NaN comparisons are treated: "gt bias" instructions return 1 for +# NaN comparisons, and "lt bias" instructions return -1. +# +# For example, to check to see if floating point x < y it is advisable +# to use cmpg-float; a result of -1 indicates that the test was true, +# and the other values indicate it was false either due to a valid +# comparison or because one of the values was NaN. +# +# A: destination register (8 bits) +# B: first source register or pair +# C: second source register or pair + +:cmpl_float registerA8,registerB8,registerC8 is inst0=0x2d ; registerA8 ; registerB8 ; registerC8 +{ + registerA8 = zext( registerC8 f<= registerB8) + zext( registerC8 f< registerB8) - 1; +} + +:cmpg_float registerA8,registerB8,registerC8 is inst0=0x2e ; registerA8 ; registerB8 ; registerC8 +{ + registerA8 = zext( registerC8 f<= registerB8) + zext( registerC8 f< registerB8) - 1; +} + +:cmpl_double registerA8,registerB8w,registerC8w is inst0=0x2f ; registerA8 ; registerB8w ; registerC8w +{ + registerA8 = zext( registerC8w f<= registerB8w) + zext( registerC8w f< registerB8w) - 1; +} + +:cmpg_double registerA8,registerB8w,registerC8w is inst0=0x30 ; registerA8 ; registerB8w ; registerC8w +{ + registerA8 = zext( registerC8w f<= registerB8w) + zext( registerC8w f< registerB8w) - 1; +} + +:cmp_long registerA8,registerB8w,registerC8w is inst0=0x31 ; registerA8 ; registerB8w ; registerC8w +{ + registerA8 = zext( registerC8w s<= registerB8w ) + zext( registerC8w s< registerB8w ) - 1; +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Branch to the given destination if the given two registers' values compare as specified. +# +# A: first register to test (4 bits) +# B: second register to test (4 bits) +# C: signed branch offset (16 bits) + +:if_eq registerA4,registerB4,rel16 is inst0=0x32 ; registerA4 & registerB4 ; rel16 +{ + if ( registerA4 == registerB4 ) goto rel16; +} + +:if_ne registerA4,registerB4,rel16 is inst0=0x33 ; registerA4 & registerB4 ; rel16 +{ + if ( registerA4 != registerB4 ) goto rel16; +} + +:if_lt registerA4,registerB4,rel16 is inst0=0x34 ; registerA4 & registerB4 ; rel16 +{ + if ( registerA4 s< registerB4 ) goto rel16; +} + +:if_ge registerA4,registerB4,rel16 is inst0=0x35 ; registerA4 & registerB4 ; rel16 +{ + if ( registerA4 s>= registerB4 ) goto rel16; +} + +:if_gt registerA4,registerB4,rel16 is inst0=0x36 ; registerA4 & registerB4 ; rel16 +{ + if ( registerA4 s> registerB4 ) goto rel16; +} + +:if_le registerA4,registerB4,rel16 is inst0=0x37 ; registerA4 & registerB4 ; rel16 +{ + if ( registerA4 s<= registerB4 ) goto rel16; +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Branch to the given destination if the given register's value compares with 0 as specified. +# +# A: register to test (8 bits) +# B: signed branch offset (16 bits) + +:if_eqz registerA8,rel16 is inst0=0x38 ; registerA8 ; rel16 +{ + if ( registerA8 == 0 ) goto rel16; +} + +:if_nez registerA8,rel16 is inst0=0x39 ; registerA8 ; rel16 +{ + if ( registerA8 != 0 ) goto rel16; +} + +:if_ltz registerA8,rel16 is inst0=0x3a ; registerA8 ; rel16 +{ + if ( registerA8 s< 0 ) goto rel16; +} + +:if_gez registerA8,rel16 is inst0=0x3b ; registerA8 ; rel16 +{ + if ( registerA8 s>= 0 ) goto rel16; +} + +:if_gtz registerA8,rel16 is inst0=0x3c ; registerA8 ; rel16 +{ + if ( registerA8 s> 0 ) goto rel16; +} + +:if_lez registerA8,rel16 is inst0=0x3d ; registerA8 ; rel16 +{ + if ( registerA8 s<= 0 ) goto rel16; +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Perform the identified array operation at the identified index +# of the given array, loading or storing into the value register. +# +# A: value register or pair; may be source or dest (8 bits) +# B: array register (8 bits) +# C: index register (8 bits) + +:aget registerA8,registerB8,registerC8 is inst0=0x44 ; registerA8 ; registerB8 ; registerC8 +{ + registerA8 = *( registerB8 + registerC8*4 ); +} + +:aget_wide registerA8w,registerB8,registerC8 is inst0=0x45 ; registerA8w ; registerB8 ; registerC8 +{ + registerA8w = *( registerB8 + registerC8*8 ); +} + +:aget_object registerA8,registerB8,registerC8 is inst0=0x46 ; registerA8 ; registerB8 ; registerC8 +{ + registerA8 = *( registerB8 + registerC8*4 ); +} + +:aget_boolean registerA8,registerB8,registerC8 is inst0=0x47 ; registerA8 ; registerB8 ; registerC8 +{ + registerA8 = zext( *:1 ( registerB8 + registerC8 )); +} + +:aget_byte registerA8,registerB8,registerC8 is inst0=0x48 ; registerA8 ; registerB8 ; registerC8 +{ + registerA8 = sext( *:1 (registerB8 + registerC8) ); +} + +:aget_char registerA8,registerB8,registerC8 is inst0=0x49 ; registerA8 ; registerB8 ; registerC8 +{ + registerA8 = zext( *:2 (registerB8 + registerC8*2 ) ); +} + +:aget_short registerA8,registerB8,registerC8 is inst0=0x4a ; registerA8 ; registerB8 ; registerC8 +{ + registerA8 = sext( *:2 (registerB8 + registerC8 * 2 ) ); +} + +:aput registerA8,registerB8,registerC8 is inst0=0x4b ; registerA8 ; registerB8 ; registerC8 +{ + *( registerB8 + registerC8 * 4 ) = registerA8; +} + +:aput_wide registerA8w,registerB8,registerC8 is inst0=0x4c ; registerA8w ; registerB8 ; registerC8 +{ + *( registerB8 + registerC8 * 8 ) = registerA8w; +} + +:aput_object registerA8,registerB8,registerC8 is inst0=0x4d ; registerA8 ; registerB8 ; registerC8 +{ + *( registerB8 + registerC8 * 4 ) = registerA8; +} + +:aput_boolean registerA8,registerB8,registerC8 is inst0=0x4e ; registerA8 ; registerB8 ; registerC8 +{ + *( registerB8 + registerC8 ) = registerA8:1; +} + +:aput_byte registerA8,registerB8,registerC8 is inst0=0x4f ; registerA8 ; registerB8 ; registerC8 +{ + *( registerB8 + registerC8 ) = registerA8:1; +} + +:aput_char registerA8,registerB8,registerC8 is inst0=0x50 ; registerA8 ; registerB8 ; registerC8 +{ + *( registerB8 + registerC8*2 ) = registerA8:2; +} + +:aput_short registerA8,registerB8,registerC8 is inst0=0x51 ; registerA8 ; registerB8 ; registerC8 +{ + *( registerB8 + registerC8*2 ) = registerA8:2; +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Perform the identified object instance field operation with the +# identified field, loading or storing into the value register. +# +# A: value register or pair; may be source or dest (4 bits) +# B: object register (4 bits) +# C: instance field reference index (16 bits) + +:iget registerA4,[registerB4:C_BITS_0_15] is inst0=0x52 ; registerA4 & registerB4 ; C_BITS_0_15 +{ + ptr:4 = cpool( registerB4, C_BITS_0_15:4, $(CPOOL_FIELD)); + registerA4 = *ptr; +} + +:iget_wide registerA4w,[registerB4:C_BITS_0_15] is inst0=0x53 ; registerA4w & registerB4 ; C_BITS_0_15 +{ + ptr:4 = cpool( registerB4, C_BITS_0_15:4, $(CPOOL_FIELD)); + registerA4w = *ptr; +} + +:iget_object registerA4,[registerB4:C_BITS_0_15] is inst0=0x54 ; registerA4 & registerB4 ; C_BITS_0_15 +{ + ptr:4 = cpool( registerB4, C_BITS_0_15:4, $(CPOOL_FIELD)); + registerA4 = *ptr; +} + +:iget_boolean registerA4,[registerB4:C_BITS_0_15] is inst0=0x55 ; registerA4 & registerB4 ; C_BITS_0_15 +{ + ptr:4 = cpool( registerB4, C_BITS_0_15:4, $(CPOOL_FIELD)); + registerA4 = zext( *:1 ptr ); +} + +:iget_byte registerA4,[registerB4:C_BITS_0_15] is inst0=0x56 ; registerA4 & registerB4 ; C_BITS_0_15 +{ + ptr:4 = cpool( registerB4, C_BITS_0_15:4, $(CPOOL_FIELD)); + registerA4 = sext( *:1 ptr ); +} + +:iget_char registerA4,[registerB4:C_BITS_0_15] is inst0=0x57 ; registerA4 & registerB4 ; C_BITS_0_15 +{ + ptr:4 = cpool( registerB4, C_BITS_0_15:4, $(CPOOL_FIELD)); + registerA4 = zext( *:2 ptr ); +} + +:iget_short registerA4,[registerB4:C_BITS_0_15] is inst0=0x58 ; registerA4 & registerB4 ; C_BITS_0_15 +{ + ptr:4 = cpool( registerB4, C_BITS_0_15:4, $(CPOOL_FIELD)); + registerA4 = sext( *:2 ptr ); +} + +:iput registerA4,[registerB4:C_BITS_0_15] is inst0=0x59 ; registerA4 & registerB4 ; C_BITS_0_15 +{ + ptr:4 = cpool(registerB4, C_BITS_0_15:4, $(CPOOL_FIELD)); + *ptr = registerA4; +} + +:iput_wide registerA4w,[registerB4:C_BITS_0_15] is inst0=0x5a ; registerA4w & registerB4 ; C_BITS_0_15 +{ + ptr:4 = cpool(registerB4, C_BITS_0_15:4, $(CPOOL_FIELD)); + *ptr = registerA4w; +} + +:iput_object registerA4,[registerB4:C_BITS_0_15] is inst0=0x5b ; registerA4 & registerB4 ; C_BITS_0_15 +{ + ptr:4 = cpool(registerB4, C_BITS_0_15:4, $(CPOOL_FIELD)); + *ptr = registerA4; +} + +:iput_boolean registerA4,[registerB4:C_BITS_0_15] is inst0=0x5c ; registerA4 & registerB4 ; C_BITS_0_15 +{ + ptr:4 = cpool(registerB4, C_BITS_0_15:4, $(CPOOL_FIELD)); + *ptr = registerA4 : 1; +} + +:iput_byte registerA4,[registerB4:C_BITS_0_15] is inst0=0x5d ; registerA4 & registerB4 ; C_BITS_0_15 +{ + ptr:4 = cpool(registerB4, C_BITS_0_15:4, $(CPOOL_FIELD)); + *ptr = registerA4 : 1; +} + +:iput_char registerA4,[registerB4:C_BITS_0_15] is inst0=0x5e ; registerA4 & registerB4 ; C_BITS_0_15 +{ + ptr:4 = cpool(registerB4, C_BITS_0_15:4, $(CPOOL_FIELD)); + *ptr = registerA4 : 2; +} + +:iput_short registerA4,[registerB4:C_BITS_0_15] is inst0=0x5f ; registerA4 & registerB4 ; C_BITS_0_15 +{ + ptr:4 = cpool(registerB4, C_BITS_0_15:4, $(CPOOL_FIELD)); + *ptr = registerA4 : 2; +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Perform the identified object static field operation with the identified +# static field, loading or storing into the value register. +# +# A: value register or pair; may be source or dest (8 bits) +# B: static field reference index (16 bits) + +:sget registerA8,B_BITS_0_15 is inst0=0x60 ; registerA8 ; B_BITS_0_15 +{ + ptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD)); + registerA8 = *ptr; +} +:sget_wide registerA8w,B_BITS_0_15 is inst0=0x61 ; registerA8w ; B_BITS_0_15 +{ + ptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD)); + registerA8w = *ptr; +} +:sget_object registerA8,B_BITS_0_15 is inst0=0x62 ; registerA8 ; B_BITS_0_15 +{ + ptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD)); + registerA8 = *ptr; +} +:sget_boolean registerA8,B_BITS_0_15 is inst0=0x63 ; registerA8 ; B_BITS_0_15 +{ + ptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD)); + registerA8 = zext(*:1 ptr); +} +:sget_byte registerA8,B_BITS_0_15 is inst0=0x64 ; registerA8 ; B_BITS_0_15 +{ + ptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD)); + registerA8 = sext(*:1 ptr); +} +:sget_char registerA8,B_BITS_0_15 is inst0=0x65 ; registerA8 ; B_BITS_0_15 +{ + ptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD)); + registerA8 = zext(*:2 ptr); +} +:sget_short registerA8,B_BITS_0_15 is inst0=0x66 ; registerA8 ; B_BITS_0_15 +{ + ptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD)); + registerA8 = sext(*:2 ptr); +} + +:sput registerA8,B_BITS_0_15 is inst0=0x67 ; registerA8 ; B_BITS_0_15 +{ + ptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD)); + *ptr = registerA8; +} +:sput_wide registerA8w,B_BITS_0_15 is inst0=0x68 ; registerA8w ; B_BITS_0_15 +{ + ptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD)); + *ptr = registerA8w; +} +:sput_object registerA8,B_BITS_0_15 is inst0=0x69 ; registerA8 ; B_BITS_0_15 +{ + ptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD)); + *ptr = registerA8; +} +:sput_boolean registerA8,B_BITS_0_15 is inst0=0x6a ; registerA8 ; B_BITS_0_15 +{ + ptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD)); + *ptr = registerA8:1; +} +:sput_byte registerA8,B_BITS_0_15 is inst0=0x6b ; registerA8 ; B_BITS_0_15 +{ + ptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD)); + *ptr = registerA8:1; +} +:sput_char registerA8,B_BITS_0_15 is inst0=0x6c ; registerA8 ; B_BITS_0_15 +{ + ptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD)); + *ptr = registerA8:2; +} +:sput_short registerA8,B_BITS_0_15 is inst0=0x6d ; registerA8 ; B_BITS_0_15 +{ + ptr:4 = cpool(0:4,B_BITS_0_15:4,$(CPOOL_STATIC_FIELD)); + *ptr = registerA8:2; +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Call the indicated method. The result (if any) may be stored with +# an appropriate move-result* variant as the immediately subsequent +# instruction. +# +# A: argument word count (4 bits) +# B: method reference index (16 bits) +# C..G: argument registers (4 bits each) + +# invoke-virtual is used to invoke a normal virtual method +# (a method that is not private, static, or final, and is also not a constructor). + +:invoke_virtual METHOD_INDEX is inst0=0x6e ; N_PARAMS=0 & METHOD_INDEX +{ + destination:4 = cpool( 0:4, METHOD_INDEX:4, $(CPOOL_METHOD)); + call [ destination ]; +} +:invoke_virtual METHOD_INDEX,regParamC is inst0=0x6e ; N_PARAMS=1 & METHOD_INDEX & regParamC +{ + iv0 = regParamC; + destination:4 = cpool( regParamC, METHOD_INDEX:4, $(CPOOL_METHOD)); + call [ destination ]; +} +:invoke_virtual METHOD_INDEX,regParamC,regParamD is inst0=0x6e ; N_PARAMS=2 & METHOD_INDEX & regParamC & regParamD +{ + iv0 = regParamC; + iv1 = regParamD; + destination:4 = cpool( regParamC, METHOD_INDEX:4, $(CPOOL_METHOD)); + call [ destination ]; +} +:invoke_virtual METHOD_INDEX,regParamC,regParamD,regParamE is inst0=0x6e ; N_PARAMS=3 & METHOD_INDEX & regParamC & regParamD & regParamE +{ + iv0 = regParamC; + iv1 = regParamD; + iv2 = regParamE; + destination:4 = cpool( regParamC, METHOD_INDEX:4, $(CPOOL_METHOD)); + call [ destination ]; +} +:invoke_virtual METHOD_INDEX,regParamC,regParamD,regParamE,regParamF is inst0=0x6e ; N_PARAMS=4 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF +{ + iv0 = regParamC; + iv1 = regParamD; + iv2 = regParamE; + iv3 = regParamF; + destination:4 = cpool( regParamC, METHOD_INDEX:4, $(CPOOL_METHOD)); + call [ destination ]; +} +:invoke_virtual METHOD_INDEX,regParamC,regParamD,regParamE,regParamF,regParamG is inst0=0x6e ; N_PARAMS=5 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF & regParamG +{ + iv0 = regParamC; + iv1 = regParamD; + iv2 = regParamE; + iv3 = regParamF; + iv4 = regParamG; + destination:4 = cpool( regParamC, METHOD_INDEX:4, $(CPOOL_METHOD)); + call [ destination ]; +} + +# invoke-super is used to invoke the closest superclass's virtual +# method (as opposed to the one with the same method_id in the +# calling class). The same method restrictions hold as for invoke-virtual. + +:invoke_super METHOD_INDEX is inst0=0x6f ; N_PARAMS=0 & METHOD_INDEX +{ + destination:4 = cpool( cpool( 0:4, 0:4, $(CPOOL_SUPER)), METHOD_INDEX:4, $(CPOOL_METHOD)); + call [ destination ]; +} +:invoke_super METHOD_INDEX,regParamC is inst0=0x6f ; N_PARAMS=1 & METHOD_INDEX & regParamC +{ + iv0 = regParamC; + destination:4 = cpool( cpool( 0:4, 0:4, $(CPOOL_SUPER)), METHOD_INDEX:4, $(CPOOL_METHOD)); + call [ destination ]; +} +:invoke_super METHOD_INDEX,regParamC,regParamD is inst0=0x6f ; N_PARAMS=2 & METHOD_INDEX & regParamC & regParamD +{ + iv0 = regParamC; + iv1 = regParamD; + destination:4 = cpool( cpool( 0:4, 0:4, $(CPOOL_SUPER)), METHOD_INDEX:4, $(CPOOL_METHOD)); + call [ destination ]; +} +:invoke_super METHOD_INDEX,regParamC,regParamD,regParamE is inst0=0x6f ; N_PARAMS=3 & METHOD_INDEX & regParamC & regParamD & regParamE +{ + iv0 = regParamC; + iv1 = regParamD; + iv2 = regParamE; + destination:4 = cpool( cpool( 0:4, 0:4, $(CPOOL_SUPER)), METHOD_INDEX:4, $(CPOOL_METHOD)); + call [ destination ]; +} +:invoke_super METHOD_INDEX,regParamC,regParamD,regParamE,regParamF is inst0=0x6f ; N_PARAMS=4 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF +{ + iv0 = regParamC; + iv1 = regParamD; + iv2 = regParamE; + iv3 = regParamF; + destination:4 = cpool( cpool( 0:4, 0:4, $(CPOOL_SUPER)), METHOD_INDEX:4, $(CPOOL_METHOD)); + call [ destination ]; +} +:invoke_super METHOD_INDEX,regParamC,regParamD,regParamE,regParamF,regParamG is inst0=0x6f ; N_PARAMS=5 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF & regParamG +{ + iv0 = regParamC; + iv1 = regParamD; + iv2 = regParamE; + iv3 = regParamF; + iv4 = regParamG; + destination:4 = cpool( cpool( 0:4, 0:4, $(CPOOL_SUPER)), METHOD_INDEX:4, $(CPOOL_METHOD)); + call [ destination ]; +} + +# invoke-direct is used to invoke a non-static direct +# method (that is, an instance method that is by its +# nature non-overridable, namely either a private instance +# method or a constructor). + +:invoke_direct METHOD_INDEX is inst0=0x70 ; N_PARAMS=0 & METHOD_INDEX +{ + destination:4 = cpool( 0:4, METHOD_INDEX, $(CPOOL_METHOD)); + call [destination]; +} +:invoke_direct METHOD_INDEX,regParamC is inst0=0x70 ; N_PARAMS=1 & METHOD_INDEX & regParamC +{ + iv0 = regParamC; + destination:4 = cpool( regParamC, METHOD_INDEX, $(CPOOL_METHOD)); + call [ destination ]; +} +:invoke_direct METHOD_INDEX,regParamC,regParamD, is inst0=0x70 ; N_PARAMS=2 & METHOD_INDEX & regParamC & regParamD +{ + iv0 = regParamC; + iv1 = regParamD; + destination:4 = cpool( regParamC, METHOD_INDEX, $(CPOOL_METHOD)); + call [ destination ]; +} +:invoke_direct METHOD_INDEX,regParamC,regParamD,regParamE is inst0=0x70 ; N_PARAMS=3 & METHOD_INDEX & regParamC & regParamD & regParamE +{ + iv0 = regParamC; + iv1 = regParamD; + iv2 = regParamE; + destination:4 = cpool( regParamC, METHOD_INDEX, $(CPOOL_METHOD)); + call [ destination ]; +} +:invoke_direct METHOD_INDEX,regParamC,regParamD,regParamE,regParamF is inst0=0x70 ; N_PARAMS=4 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF +{ + iv0 = regParamC; + iv1 = regParamD; + iv2 = regParamE; + iv3 = regParamF; + destination:4 = cpool( regParamC, METHOD_INDEX, $(CPOOL_METHOD)); + call [ destination ]; +} +:invoke_direct METHOD_INDEX,regParamC,regParamD,regParamE,regParamF,regParamG is inst0=0x70 ; N_PARAMS=5 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF & regParamG +{ + iv0 = regParamC; + iv1 = regParamD; + iv2 = regParamE; + iv3 = regParamF; + iv4 = regParamG; + destination:4 = cpool( regParamC, METHOD_INDEX, $(CPOOL_METHOD)); + call [ destination ]; +} + +# invoke-static is used to invoke a static method +# (which is always considered a direct method). + +:invoke_static METHOD_INDEX is inst0=0x71 ; N_PARAMS=0 & METHOD_INDEX +{ + destination:4 = cpool( 0:4, METHOD_INDEX, $(CPOOL_STATIC_METHOD)); + call [ destination ]; +} +:invoke_static METHOD_INDEX,regParamC is inst0=0x71 ; N_PARAMS=1 & METHOD_INDEX & regParamC +{ + iv0 = regParamC; + destination:4 = cpool( 0:4, METHOD_INDEX, $(CPOOL_STATIC_METHOD)); + call [ destination ]; +} +:invoke_static METHOD_INDEX,regParamC,regParamD is inst0=0x71 ; N_PARAMS=2 & METHOD_INDEX & regParamC & regParamD +{ + iv0 = regParamC; + iv1 = regParamD; + destination:4 = cpool( 0:4, METHOD_INDEX, $(CPOOL_STATIC_METHOD)); + call [ destination ]; +} +:invoke_static METHOD_INDEX,regParamC,regParamD,regParamE is inst0=0x71 ; N_PARAMS=3 & METHOD_INDEX & regParamC & regParamD & regParamE +{ + iv0 = regParamC; + iv1 = regParamD; + iv2 = regParamE; + destination:4 = cpool( 0:4, METHOD_INDEX, $(CPOOL_STATIC_METHOD)); + call [ destination ]; +} +:invoke_static METHOD_INDEX,regParamC,regParamD,regParamE,regParamF is inst0=0x71 ; N_PARAMS=4 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF +{ + iv0 = regParamC; + iv1 = regParamD; + iv2 = regParamE; + iv3 = regParamF; + destination:4 = cpool( 0:4, METHOD_INDEX, $(CPOOL_STATIC_METHOD)); + call [ destination ]; +} +:invoke_static METHOD_INDEX,regParamC,regParamD,regParamE,regParamF,regParamG is inst0=0x71 ; N_PARAMS=5 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF & regParamG +{ + iv0 = regParamC; + iv1 = regParamD; + iv2 = regParamE; + iv3 = regParamF; + iv4 = regParamG; + destination:4 = cpool( 0:4, METHOD_INDEX, $(CPOOL_STATIC_METHOD)); + call [ destination ]; +} + +# invoke-interface is used to invoke an interface +# method, that is, on an object whose concrete +# class isn't known, using a method_id that refers +# to an interface. + +:invoke_interface METHOD_INDEX is inst0=0x72 ; N_PARAMS=0 & METHOD_INDEX +{ + destination:4 = cpool( 0:4, METHOD_INDEX,$(CPOOL_METHOD)); + call [ destination ]; +} +:invoke_interface METHOD_INDEX,regParamC is inst0=0x72 ; N_PARAMS=1 & METHOD_INDEX & regParamC +{ + iv0 = regParamC; + destination:4 = cpool(regParamC,METHOD_INDEX,$(CPOOL_METHOD)); + call [ destination ]; +} +:invoke_interface METHOD_INDEX,regParamC,regParamD is inst0=0x72 ; N_PARAMS=2 & METHOD_INDEX & regParamC & regParamD +{ + iv0 = regParamC; + iv1 = regParamD; + destination:4 = cpool(regParamC,METHOD_INDEX,$(CPOOL_METHOD)); + call [ destination ]; +} +:invoke_interface METHOD_INDEX,regParamC,regParamD,regParamE is inst0=0x72 ; N_PARAMS=3 & METHOD_INDEX & regParamC & regParamD & regParamE +{ + iv0 = regParamC; + iv1 = regParamD; + iv2 = regParamE; + destination:4 = cpool(regParamC,METHOD_INDEX,$(CPOOL_METHOD)); + call [ destination ]; +} +:invoke_interface METHOD_INDEX,regParamC,regParamD,regParamE,regParamF is inst0=0x72 ; N_PARAMS=4 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF +{ + iv0 = regParamC; + iv1 = regParamD; + iv2 = regParamE; + iv3 = regParamF; + destination:4 = cpool(regParamC,METHOD_INDEX,$(CPOOL_METHOD)); + call [ destination ]; +} +:invoke_interface METHOD_INDEX,regParamC,regParamD,regParamE,regParamF,regParamG is inst0=0x72 ; N_PARAMS=5 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF & regParamG +{ + iv0 = regParamC; + iv1 = regParamD; + iv2 = regParamE; + iv3 = regParamF; + iv4 = regParamG; + destination:4 = cpool(regParamC,METHOD_INDEX,$(CPOOL_METHOD)); + call [ destination ]; +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Call the indicated method. +# See first invoke-kind description above for details, caveats, and suggestions. +# +# A: argument word count (8 bits) +# B: method reference index (16 bits) +# C: first argument register (16 bits) +# N = A + C - 1 + +:invoke_virtual_range B_BITS_0_15,A_BITS_0_7,registerC16 is inst0=0x74 ; A_BITS_0_7 ; B_BITS_0_15 ; registerC16 +{ + moveRangeToIV( A_BITS_0_7:4, registerC16 ); + destination:4 = cpool(registerC16, B_BITS_0_15:4, $(CPOOL_METHOD)); + call [ destination ]; +} +:invoke_super_range B_BITS_0_15,A_BITS_0_7,registerC16 is inst0=0x75 ; A_BITS_0_7 ; B_BITS_0_15 ; registerC16 +{ + moveRangeToIV( A_BITS_0_7:4, registerC16 ); + destination:4 = cpool( cpool( 0:4, 0:4, $(CPOOL_SUPER)), B_BITS_0_15:4, $(CPOOL_METHOD)); + call [ destination ]; +} +:invoke_direct_range B_BITS_0_15,A_BITS_0_7,registerC16 is inst0=0x76 ; A_BITS_0_7 ; B_BITS_0_15 ; registerC16 +{ + moveRangeToIV( A_BITS_0_7:4, registerC16 ); + destination:4 = cpool(registerC16, B_BITS_0_15:4, $(CPOOL_METHOD)); + call [ destination ]; +} +:invoke_static_range B_BITS_0_15,A_BITS_0_7,registerC16 is inst0=0x77 ; A_BITS_0_7 ; B_BITS_0_15 ; registerC16 +{ + moveRangeToIV( A_BITS_0_7:4, registerC16 ); + destination:4 = cpool(0:4, B_BITS_0_15:4, $(CPOOL_STATIC_METHOD)); + call [ destination ]; +} +:invoke_interface_range B_BITS_0_15,A_BITS_0_7,registerC16 is inst0=0x78 ; A_BITS_0_7 ; B_BITS_0_15 ; registerC16 +{ + moveRangeToIV( A_BITS_0_7:4, registerC16 ); + destination:4 = cpool(registerC16, B_BITS_0_15:4, $(CPOOL_METHOD)); + call [ destination ]; +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Perform the identified unary operation on the source register, +# storing the result in the destination register. +# +# A: destination register or pair (4 bits) +# B: source register or pair (4 bits) + +:neg_int registerA4,registerB4 is inst0=0x7b ; registerA4 & registerB4 +{ + registerA4 = -registerB4; +} + +:not_int registerA4,registerB4 is inst0=0x7c ; registerA4 & registerB4 +{ + registerA4 = ~registerB4; +} + +:neg_long registerA4w,registerB4w is inst0=0x7d ; registerA4w & registerB4w +{ + registerA4w = -registerB4w; +} + +:not_long registerA4w,registerB4w is inst0=0x7e ; registerA4w & registerB4w +{ + registerA4w = ~registerB4w; +} + +:neg_float registerA4,registerB4 is inst0=0x7f ; registerA4 & registerB4 +{ + registerA4 = f-registerB4; +} + +:neg_double registerA4,registerB4 is inst0=0x80 ; registerA4 & registerB4 +{ + registerA4 = f-registerB4; +} + +:int_to_long registerA4w,registerB4 is inst0=0x81 ; registerA4w & registerB4 +{ + registerA4w = sext(registerB4); +} + +:int_to_float registerA4,registerB4 is inst0=0x82 ; registerA4 & registerB4 +{ + registerA4 = int2float(registerB4); +} + +:int_to_double registerA4w,registerB4 is inst0=0x83 ; registerA4w & registerB4 +{ + registerA4w = int2float(registerB4); +} + +:long_to_int registerA4,registerB4w is inst0=0x84 ; registerA4 & registerB4w +{ + registerA4 = registerB4w:4; +} +:long_to_float registerA4,registerB4w is inst0=0x85 ; registerA4 & registerB4w +{ + registerA4 = int2float(registerB4w); +} + +:long_to_double registerA4w,registerB4w is inst0=0x86 ; registerA4w & registerB4w +{ + registerA4w = int2float(registerB4w); +} + +:float_to_int registerA4,registerB4 is inst0=0x87 ; registerA4 & registerB4 +{ + registerA4 = trunc(registerB4); +} + +:float_to_long registerA4w,registerB4 is inst0=0x88 ; registerA4w & registerB4 +{ + registerA4w = trunc(registerB4); +} + +:float_to_double registerA4w,registerB4 is inst0=0x89 ; registerA4w & registerB4 +{ + registerA4w = float2float(registerB4); +} + +:double_to_int registerA4,registerB4w is inst0=0x8a ; registerA4 & registerB4w +{ + registerA4 = trunc(registerB4w); +} + +:double_to_long registerA4w,registerB4w is inst0=0x8b ; registerA4w & registerB4w +{ + registerA4w = trunc(registerB4w); +} + +:double_to_float registerA4,registerB4w is inst0=0x8c ; registerA4 & registerB4w +{ + registerA4 = float2float(registerB4w); +} + +:int_to_byte registerA4,registerB4 is inst0=0x8d ; registerA4 & registerB4 +{ + registerA4 = sext(registerB4:1); +} + +:int_to_char registerA4,registerB4 is inst0=0x8e ; registerA4 & registerB4 +{ + registerA4 = zext(registerB4:2); +} + +:int_to_short registerA4,registerB4 is inst0=0x8f ; registerA4 & registerB4 +{ + registerA4 = sext(registerB4:2); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Perform the identified binary operation on the two source registers, +# storing the result in the destination register. +# +# A: destination register or pair (8 bits) +# B: first source register or pair (8 bits) +# C: second source register or pair (8 bits) + +:add_int registerA8,registerB8,registerC8 is inst0=0x90 ; registerA8 ; registerB8 ; registerC8 +{ + registerA8 = registerB8 + registerC8; +} +:sub_int registerA8,registerB8,registerC8 is inst0=0x91 ; registerA8 ; registerB8 ; registerC8 +{ + registerA8 = registerB8 - registerC8; +} +:mul_int registerA8,registerB8,registerC8 is inst0=0x92 ; registerA8 ; registerB8 ; registerC8 +{ + registerA8 = registerB8 * registerC8; +} +:div_int registerA8,registerB8,registerC8 is inst0=0x93 ; registerA8 ; registerB8 ; registerC8 +{ + registerA8 = registerB8 s/ registerC8; +} +:rem_int registerA8,registerB8,registerC8 is inst0=0x94 ; registerA8 ; registerB8 ; registerC8 +{ + registerA8 = registerB8 s% registerC8; +} +:and_int registerA8,registerB8,registerC8 is inst0=0x95 ; registerA8 ; registerB8 ; registerC8 +{ + registerA8 = registerB8 & registerC8; +} +:or_int registerA8,registerB8,registerC8 is inst0=0x96 ; registerA8 ; registerB8 ; registerC8 +{ + registerA8 = registerB8 | registerC8; +} +:xor_int registerA8,registerB8,registerC8 is inst0=0x97 ; registerA8 ; registerB8 ; registerC8 +{ + registerA8 = registerB8 ^ registerC8; +} +:shl_int registerA8,registerB8,registerC8 is inst0=0x98 ; registerA8 ; registerB8 ; registerC8 +{ + registerA8 = registerB8 << registerC8; +} +:shr_int registerA8,registerB8,registerC8 is inst0=0x99 ; registerA8 ; registerB8 ; registerC8 +{ + registerA8 = registerB8 s>> registerC8; +} +:ushr_int registerA8,registerB8,registerC8 is inst0=0x9a ; registerA8 ; registerB8 ; registerC8 +{ + registerA8 = registerB8 >> registerC8; +} +:add_long registerA8w,registerB8w,registerC8w is inst0=0x9b ; registerA8w ; registerB8w ; registerC8w +{ + registerA8w = registerB8w + registerC8w; +} +:sub_long registerA8w,registerB8w,registerC8w is inst0=0x9c ; registerA8w ; registerB8w ; registerC8w +{ + registerA8w = registerB8w - registerC8w; +} +:mul_long registerA8w,registerB8w,registerC8w is inst0=0x9d ; registerA8w ; registerB8w ; registerC8w +{ + registerA8w = registerB8w * registerC8w; +} +:div_long registerA8w,registerB8w,registerC8w is inst0=0x9e ; registerA8w ; registerB8w ; registerC8w +{ + registerA8w = registerB8w s/ registerC8w; +} +:rem_long registerA8w,registerB8w,registerC8w is inst0=0x9f ; registerA8w ; registerB8w ; registerC8w +{ + registerA8w = registerB8w s% registerC8w; +} +:and_long registerA8w,registerB8w,registerC8w is inst0=0xa0 ; registerA8w ; registerB8w ; registerC8w +{ + registerA8w = registerB8w & registerC8w; +} +:or_long registerA8w,registerB8w,registerC8w is inst0=0xa1 ; registerA8w ; registerB8w ; registerC8w +{ + registerA8w = registerB8w | registerC8w; +} +:xor_long registerA8w,registerB8w,registerC8w is inst0=0xa2 ; registerA8w ; registerB8w ; registerC8w +{ + registerA8w = registerB8w ^ registerC8w; +} +:shl_long registerA8w,registerB8w,registerC8 is inst0=0xa3 ; registerA8w ; registerB8w ; registerC8 +{ + registerA8w = registerB8w << registerC8; +} +:shr_long registerA8w,registerB8w,registerC8 is inst0=0xa4 ; registerA8w ; registerB8w ; registerC8 +{ + registerA8w = registerB8w s>> registerC8; +} +:ushr_long registerA8w,registerB8w,registerC8 is inst0=0xa5 ; registerA8w ; registerB8w ; registerC8 +{ + registerA8w = registerB8w >> registerC8; +} +:add_float registerA8,registerB8,registerC8 is inst0=0xa6 ; registerA8 ; registerB8 ; registerC8 +{ + registerA8 = registerB8 f+ registerC8; +} +:sub_float registerA8,registerB8,registerC8 is inst0=0xa7 ; registerA8 ; registerB8 ; registerC8 +{ + registerA8 = registerB8 f- registerC8; +} +:mul_float registerA8,registerB8,registerC8 is inst0=0xa8 ; registerA8 ; registerB8 ; registerC8 +{ + registerA8 = registerB8 f* registerC8; +} +:div_float registerA8,registerB8,registerC8 is inst0=0xa9 ; registerA8 ; registerB8 ; registerC8 +{ + registerA8 = registerB8 f/ registerC8; +} +:rem_float registerA8,registerB8,registerC8 is inst0=0xaa ; registerA8 ; registerB8 ; registerC8 +{ + registerA8 = registerB8 s% registerC8;#TODO how to tell floating point?? +} +:add_double registerA8w,registerB8w,registerC8w is inst0=0xab ; registerA8w ; registerB8w ; registerC8w +{ + registerA8w = registerB8w f+ registerC8w; +} +:sub_double registerA8w,registerB8w,registerC8w is inst0=0xac ; registerA8w ; registerB8w ; registerC8w +{ + registerA8w = registerB8w f- registerC8w; +} +:mul_double registerA8w,registerB8w,registerC8w is inst0=0xad ; registerA8w ; registerB8w ; registerC8w +{ + registerA8w = registerB8w f* registerC8w; +} +:div_double registerA8w,registerB8w,registerC8w is inst0=0xae ; registerA8w ; registerB8w ; registerC8w +{ + registerA8w = registerB8w f/ registerC8w; +} +:rem_double registerA8w,registerB8w,registerC8w is inst0=0xaf ; registerA8w ; registerB8w ; registerC8w +{ + registerA8w = registerB8w s% registerC8w;#TODO how to tell floating point?? +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Perform the identified binary operation on the two source registers, +# storing the result in the first source register. +# +# A: destination and first source register or pair (4 bits) +# B: second source register or pair (4 bits) + +:add_int_2addr registerA4,registerB4 is inst0=0xb0 ; registerA4 & registerB4 +{ + registerA4 = registerA4 + registerB4; +} +:sub_int_2addr registerA4,registerB4 is inst0=0xb1 ; registerA4 & registerB4 +{ + registerA4 = registerA4 - registerB4; +} +:mul_int_2addr registerA4,registerB4 is inst0=0xb2 ; registerA4 & registerB4 +{ + registerA4 = registerA4 * registerB4; +} +:div_int_2addr registerA4,registerB4 is inst0=0xb3 ; registerA4 & registerB4 +{ + registerA4 = registerA4 s/ registerB4; +} +:rem_int_2addr registerA4,registerB4 is inst0=0xb4 ; registerA4 & registerB4 +{ + registerA4 = registerA4 s% registerB4; +} +:and_int_2addr registerA4,registerB4 is inst0=0xb5 ; registerA4 & registerB4 +{ + registerA4 = registerA4 & registerB4; +} +:or_int_2addr registerA4,registerB4 is inst0=0xb6 ; registerA4 & registerB4 +{ + registerA4 = registerA4 | registerB4; +} +:xor_int_2addr registerA4,registerB4 is inst0=0xb7 ; registerA4 & registerB4 +{ + registerA4 = registerA4 ^ registerB4; +} +:shl_int_2addr registerA4,registerB4 is inst0=0xb8 ; registerA4 & registerB4 +{ + registerA4 = registerA4 << registerB4; +} +:shr_int_2addr registerA4,registerB4 is inst0=0xb9 ; registerA4 & registerB4 +{ + registerA4 = registerA4 s>> registerB4; +} +:ushr_int_2addr registerA4,registerB4 is inst0=0xba ; registerA4 & registerB4 +{ + registerA4 = registerA4 >> registerB4; +} +:add_long_2addr registerA4w,registerB4w is inst0=0xbb ; registerA4w & registerB4w +{ + registerA4w = registerA4w + registerB4w; +} +:sub_long_2addr registerA4w,registerB4w is inst0=0xbc ; registerA4w & registerB4w +{ + registerA4w= registerA4w - registerB4w; +} +:mul_long_2addr registerA4w,registerB4w is inst0=0xbd ; registerA4w & registerB4w +{ + registerA4w = registerA4w * registerB4w; +} +:div_long_2addr registerA4w,registerB4w is inst0=0xbe ; registerA4w & registerB4w +{ + registerA4w = registerA4w s/ registerB4w; +} +:rem_long_2addr registerA4w,registerB4w is inst0=0xbf ; registerA4w & registerB4w +{ + registerA4w = registerA4w s% registerB4w; +} +:and_long_2addr registerA4w,registerB4w is inst0=0xc0 ; registerA4w & registerB4w +{ + registerA4w = registerA4w & registerB4w; +} +:or_long_2addr registerA4w,registerB4w is inst0=0xc1 ; registerA4w & registerB4w +{ + registerA4w = registerA4w | registerB4w; +} +:xor_long_2addr registerA4w,registerB4w is inst0=0xc2 ; registerA4w & registerB4w +{ + registerA4w = registerA4w ^ registerB4w; +} +:shl_long_2addr registerA4w,registerB4 is inst0=0xc3 ; registerA4w & registerB4 +{ + registerA4w = registerA4w << registerB4; +} +:shr_long_2addr registerA4w,registerB4 is inst0=0xc4 ; registerA4w & registerB4 +{ + registerA4w = registerA4w s>> registerB4; +} +:ushr_long_2addr registerA4w,registerB4 is inst0=0xc5 ; registerA4w & registerB4 +{ + registerA4w = registerA4w >> registerB4; +} +:add_float_2addr registerA4,registerB4 is inst0=0xc6 ; registerA4 & registerB4 +{ + registerA4 = registerA4 f+ registerB4; +} +:sub_float_2addr registerA4,registerB4 is inst0=0xc7 ; registerA4 & registerB4 +{ + registerA4 = registerA4 f- registerB4; +} +:mul_float_2addr registerA4,registerB4 is inst0=0xc8 ; registerA4 & registerB4 +{ + registerA4 = registerA4 f* registerB4; +} +:div_float_2addr registerA4,registerB4 is inst0=0xc9 ; registerA4 & registerB4 +{ + registerA4 = registerA4 f/ registerB4; +} +:rem_float_2addr registerA4,registerB4 is inst0=0xca ; registerA4 & registerB4 +{ + registerA4 = registerA4 s% registerB4; +} +:add_double_2addr registerA4w,registerB4w is inst0=0xcb ; registerA4w & registerB4w +{ + registerA4w = registerA4w f+ registerB4w; +} +:sub_double_2addr registerA4w,registerB4w is inst0=0xcc ; registerA4w & registerB4w +{ + registerA4w = registerA4w f- registerB4w; +} +:mul_double_2addr registerA4w,registerB4w is inst0=0xcd ; registerA4w & registerB4w +{ + registerA4w = registerA4w f* registerB4w; +} +:div_double_2addr registerA4w,registerB4w is inst0=0xce ; registerA4w & registerB4w +{ + registerA4w = registerA4w f/ registerB4w; +} +:rem_double_2addr registerA4w,registerB4w is inst0=0xcf ; registerA4w & registerB4w +{ + registerA4w = registerA4w s% registerB4w; +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Perform the indicated binary op on the indicated register (first argument) +# and literal value (second argument), storing the result in the destination +# register. +# +# A: destination register (4 bits) +# B: source register (4 bits) +# C: signed int constant (16 bits) + +:add_int_lit16 registerA4,registerB4,C_BITS_0_15_S is inst0=0xd0 ; registerA4 & registerB4 ; C_BITS_0_15_S +{ + registerA4 = registerB4 + C_BITS_0_15_S; +} +:rsub_int registerA4,registerB4,C_BITS_0_15_S is inst0=0xd1 ; registerA4 & registerB4 ; C_BITS_0_15_S +{ + registerA4 = C_BITS_0_15_S - registerB4; # Twos-complement reverse subtraction. +} +:mul_int_lit16 registerA4,registerB4,C_BITS_0_15_S is inst0=0xd2 ; registerA4 & registerB4 ; C_BITS_0_15_S +{ + registerA4 = registerB4 * C_BITS_0_15_S; +} +:div_int_lit16 registerA4,registerB4,C_BITS_0_15_S is inst0=0xd3 ; registerA4 & registerB4 ; C_BITS_0_15_S +{ + registerA4 = registerB4 s/ C_BITS_0_15_S; +} +:rem_int_lit16 registerA4,registerB4,C_BITS_0_15_S is inst0=0xd4 ; registerA4 & registerB4 ; C_BITS_0_15_S +{ + registerA4 = registerB4 s% C_BITS_0_15_S; +} +:and_int_lit16 registerA4,registerB4,C_BITS_0_15_S is inst0=0xd5 ; registerA4 & registerB4 ; C_BITS_0_15_S +{ + registerA4 = registerB4 & C_BITS_0_15_S; +} +:or_int_lit16 registerA4,registerB4,C_BITS_0_15_S is inst0=0xd6 ; registerA4 & registerB4 ; C_BITS_0_15_S +{ + registerA4 = registerB4 | C_BITS_0_15_S; +} +:xor_int_lit16 registerA4,registerB4,C_BITS_0_15_S is inst0=0xd7 ; registerA4 & registerB4 ; C_BITS_0_15_S +{ + registerA4 = registerB4 ^ C_BITS_0_15_S; +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# Perform the indicated binary op on the indicated register (first argument) +# and literal value (second argument), storing the result in the destination +# register. +# +# A: destination register (8 bits) +# B: source register (8 bits) +# C: signed int constant (8 bits) + +:add_int_lit8 registerA8,registerB8,C_BITS_0_7_S is inst0=0xd8 ; registerA8 ; registerB8 ; C_BITS_0_7_S +{ + registerA8 = registerB8 + C_BITS_0_7_S; +} +:rsub_int_lit8 registerA8,registerB8,C_BITS_0_7_S is inst0=0xd9 ; registerA8 ; registerB8 ; C_BITS_0_7_S +{ + registerA8 = C_BITS_0_7_S - registerB8; # Twos-complement reverse subtraction. +} +:mul_int_lit8 registerA8,registerB8,C_BITS_0_7_S is inst0=0xda ; registerA8 ; registerB8 ; C_BITS_0_7_S +{ + registerA8 = registerB8 * C_BITS_0_7_S; +} +:div_int_lit8 registerA8,registerB8,C_BITS_0_7_S is inst0=0xdb ; registerA8 ; registerB8 ; C_BITS_0_7_S +{ + registerA8 = registerB8 s/ C_BITS_0_7_S; +} +:rem_int_lit8 registerA8,registerB8,C_BITS_0_7_S is inst0=0xdc ; registerA8 ; registerB8 ; C_BITS_0_7_S +{ + registerA8 = registerB8 s% C_BITS_0_7_S; +} +:and_int_lit8 registerA8,registerB8,C_BITS_0_7_S is inst0=0xdd ; registerA8 ; registerB8 ; C_BITS_0_7_S +{ + registerA8 = registerB8 & C_BITS_0_7_S; +} +:or_int_lit8 registerA8,registerB8,C_BITS_0_7_S is inst0=0xde ; registerA8 ; registerB8 ; C_BITS_0_7_S +{ + registerA8 = registerB8 | C_BITS_0_7_S; +} +:xor_int_lit8 registerA8,registerB8,C_BITS_0_7_S is inst0=0xdf ; registerA8 ; registerB8 ; C_BITS_0_7_S +{ + registerA8 = registerB8 ^ C_BITS_0_7_S; +} +:shl_int_lit8 registerA8,registerB8,C_BITS_0_7_S is inst0=0xe0 ; registerA8 ; registerB8 ; C_BITS_0_7_S +{ + registerA8 = registerB8 << C_BITS_0_7_S; +} +:shr_int_lit8 registerA8,registerB8,C_BITS_0_7_S is inst0=0xe1 ; registerA8 ; registerB8 ; C_BITS_0_7_S +{ + registerA8 = registerB8 s>> C_BITS_0_7_S; +} +:ushr_int_lit8 registerA8,registerB8,C_BITS_0_7_S is inst0=0xe2 ; registerA8 ; registerB8 ; C_BITS_0_7_S +{ + registerA8 = registerB8 >> C_BITS_0_7_S; #TODO should this value be signed??? +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_Base.slaspec b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_Base.slaspec new file mode 100644 index 0000000..d2a9654 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_Base.slaspec @@ -0,0 +1,5 @@ +#------------------------------------------------------------------------------------ +# Sleigh specification file for DALVIK VM (base set of instructions) +#------------------------------------------------------------------------------------ + +@include "Dalvik_Base.sinc" \ No newline at end of file diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_Android10.slaspec b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_Android10.slaspec new file mode 100644 index 0000000..c303f12 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_Android10.slaspec @@ -0,0 +1,30 @@ +#------------------------------------------------------------------------------------ +# Sleigh specification file for DALVIK VM +#------------------------------------------------------------------------------------ + +# Source: +# https://android.googlesource.com/platform/art/+/refs/heads/android10-release/libdexfile/dex/dex_instruction_list.h + +@include "Dalvik_Base.sinc" + +@include "Dalvik_OpCode_3E_43_unused.sinc" + +@include "Dalvik_OpCode_73_return_void_no_barrier.sinc" + +@include "Dalvik_OpCode_79_unused.sinc" +@include "Dalvik_OpCode_7A_unused.sinc" + +@include "Dalvik_OpCode_E3_EA_dex.sinc" + +@include "Dalvik_OpCode_EB_F2_iput_iget.sinc" + +@include "Dalvik_OpCode_F3_unused.sinc" +@include "Dalvik_OpCode_F4_unused.sinc" +@include "Dalvik_OpCode_F5_unused.sinc" +@include "Dalvik_OpCode_F6_unused.sinc" +@include "Dalvik_OpCode_F7_unused.sinc" +@include "Dalvik_OpCode_F8_unused.sinc" +@include "Dalvik_OpCode_F9_unused.sinc" + +@include "Dalvik_OpCode_FA_FD_dex.sinc" +@include "Dalvik_OpCode_FE_FF_dex.sinc" diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_Android11.slaspec b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_Android11.slaspec new file mode 100644 index 0000000..9829695 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_Android11.slaspec @@ -0,0 +1,30 @@ +#------------------------------------------------------------------------------------ +# Sleigh specification file for DALVIK VM +#------------------------------------------------------------------------------------ + +# Source: +# https://android.googlesource.com/platform/art/+/refs/heads/android11-release/libdexfile/dex/dex_instruction_list.h + +@include "Dalvik_Base.sinc" + +@include "Dalvik_OpCode_3E_43_unused.sinc" + +@include "Dalvik_OpCode_73_return_void_no_barrier.sinc" + +@include "Dalvik_OpCode_79_unused.sinc" +@include "Dalvik_OpCode_7A_unused.sinc" + +@include "Dalvik_OpCode_E3_EA_dex.sinc" + +@include "Dalvik_OpCode_EB_F2_iput_iget.sinc" + +@include "Dalvik_OpCode_F3_unused.sinc" +@include "Dalvik_OpCode_F4_unused.sinc" +@include "Dalvik_OpCode_F5_unused.sinc" +@include "Dalvik_OpCode_F6_unused.sinc" +@include "Dalvik_OpCode_F7_unused.sinc" +@include "Dalvik_OpCode_F8_unused.sinc" +@include "Dalvik_OpCode_F9_unused.sinc" + +@include "Dalvik_OpCode_FA_FD_dex.sinc" +@include "Dalvik_OpCode_FE_FF_dex.sinc" \ No newline at end of file diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_Android12.slaspec b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_Android12.slaspec new file mode 100644 index 0000000..9cd7bad --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_Android12.slaspec @@ -0,0 +1,31 @@ +#------------------------------------------------------------------------------------ +# Sleigh specification file for DALVIK VM +#------------------------------------------------------------------------------------ + +# Source: +# https://android.googlesource.com/platform/art/+/refs/heads/android12-release/libdexfile/dex/dex_instruction_list.h +# https://android.googlesource.com/platform/art/+/refs/heads/android13-release/libdexfile/dex/dex_instruction_list.h + +@include "Dalvik_Base.sinc" + +@include "Dalvik_OpCode_3E_43_unused.sinc" + +@include "Dalvik_OpCode_73_unused.sinc" + +@include "Dalvik_OpCode_79_unused.sinc" +@include "Dalvik_OpCode_7A_unused.sinc" + +@include "Dalvik_OpCode_E3_EA_unused.sinc" + +@include "Dalvik_OpCode_EB_F2_unused.sinc" + +@include "Dalvik_OpCode_F3_unused.sinc" +@include "Dalvik_OpCode_F4_unused.sinc" +@include "Dalvik_OpCode_F5_unused.sinc" +@include "Dalvik_OpCode_F6_unused.sinc" +@include "Dalvik_OpCode_F7_unused.sinc" +@include "Dalvik_OpCode_F8_unused.sinc" +@include "Dalvik_OpCode_F9_unused.sinc" + +@include "Dalvik_OpCode_FA_FD_dex.sinc" +@include "Dalvik_OpCode_FE_FF_dex.sinc" \ No newline at end of file diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_KitKat.slaspec b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_KitKat.slaspec new file mode 100644 index 0000000..d04373f --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_KitKat.slaspec @@ -0,0 +1,33 @@ +#------------------------------------------------------------------------------------ +# Sleigh specification file for DALVIK VM +#------------------------------------------------------------------------------------ + +# Source: +# https://android.googlesource.com/platform/art/+/refs/heads/kitkat-release/runtime/dex_instruction_list.h + +@include "Dalvik_Base.sinc" + +@include "Dalvik_OpCode_3E_43_unused.sinc" + +@include "Dalvik_OpCode_73_return_void_barrier.sinc" + +@include "Dalvik_OpCode_79_unused.sinc" +@include "Dalvik_OpCode_7A_unused.sinc" + +@include "Dalvik_OpCode_E3_EA_dex.sinc" + +@include "Dalvik_OpCode_EB_F2_unused.sinc" + +@include "Dalvik_OpCode_F3_unused.sinc" +@include "Dalvik_OpCode_F4_unused.sinc" +@include "Dalvik_OpCode_F5_unused.sinc" +@include "Dalvik_OpCode_F6_unused.sinc" +@include "Dalvik_OpCode_F7_unused.sinc" +@include "Dalvik_OpCode_F8_unused.sinc" +@include "Dalvik_OpCode_F9_unused.sinc" +@include "Dalvik_OpCode_FA_unused.sinc" +@include "Dalvik_OpCode_FB_unused.sinc" +@include "Dalvik_OpCode_FC_unused.sinc" +@include "Dalvik_OpCode_FD_unused.sinc" +@include "Dalvik_OpCode_FE_unused.sinc" +@include "Dalvik_OpCode_FF_unused.sinc" diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_Lollipop.slaspec b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_Lollipop.slaspec new file mode 100644 index 0000000..18bdd19 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_Lollipop.slaspec @@ -0,0 +1,33 @@ +#------------------------------------------------------------------------------------ +# Sleigh specification file for DALVIK VM +#------------------------------------------------------------------------------------ + +# Source: +# https://android.googlesource.com/platform/art/+/refs/heads/lollipop-release/runtime/dex_instruction_list.h + +@include "Dalvik_Base.sinc" + +@include "Dalvik_OpCode_3E_43_unused.sinc" + +@include "Dalvik_OpCode_73_return_void_barrier.sinc" + +@include "Dalvik_OpCode_79_unused.sinc" +@include "Dalvik_OpCode_7A_unused.sinc" + +@include "Dalvik_OpCode_E3_EA_dex.sinc" + +@include "Dalvik_OpCode_EB_F2_unused.sinc" + +@include "Dalvik_OpCode_F3_unused.sinc" +@include "Dalvik_OpCode_F4_unused.sinc" +@include "Dalvik_OpCode_F5_unused.sinc" +@include "Dalvik_OpCode_F6_unused.sinc" +@include "Dalvik_OpCode_F7_unused.sinc" +@include "Dalvik_OpCode_F8_unused.sinc" +@include "Dalvik_OpCode_F9_unused.sinc" +@include "Dalvik_OpCode_FA_unused.sinc" +@include "Dalvik_OpCode_FB_unused.sinc" +@include "Dalvik_OpCode_FC_unused.sinc" +@include "Dalvik_OpCode_FD_unused.sinc" +@include "Dalvik_OpCode_FE_unused.sinc" +@include "Dalvik_OpCode_FF_unused.sinc" diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_Marshmallow.slaspec b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_Marshmallow.slaspec new file mode 100644 index 0000000..88a620b --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_Marshmallow.slaspec @@ -0,0 +1,33 @@ +#------------------------------------------------------------------------------------ +# Sleigh specification file for DALVIK VM +#------------------------------------------------------------------------------------ + +# Source: +# https://android.googlesource.com/platform/art/+/refs/heads/marshmallow-release/runtime/dex_instruction_list.h + +@include "Dalvik_Base.sinc" + +@include "Dalvik_OpCode_3E_43_unused.sinc" + +@include "Dalvik_OpCode_73_return_void_no_barrier.sinc" + +@include "Dalvik_OpCode_79_unused.sinc" +@include "Dalvik_OpCode_7A_unused.sinc" + +@include "Dalvik_OpCode_E3_EA_dex.sinc" + +@include "Dalvik_OpCode_EB_F2_iput_iget.sinc" + +@include "Dalvik_OpCode_F3_unused.sinc" +@include "Dalvik_OpCode_F4_unused.sinc" +@include "Dalvik_OpCode_F5_unused.sinc" +@include "Dalvik_OpCode_F6_unused.sinc" +@include "Dalvik_OpCode_F7_unused.sinc" +@include "Dalvik_OpCode_F8_unused.sinc" +@include "Dalvik_OpCode_F9_unused.sinc" +@include "Dalvik_OpCode_FA_unused.sinc" +@include "Dalvik_OpCode_FB_unused.sinc" +@include "Dalvik_OpCode_FC_unused.sinc" +@include "Dalvik_OpCode_FD_unused.sinc" +@include "Dalvik_OpCode_FE_unused.sinc" +@include "Dalvik_OpCode_FF_unused.sinc" diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_Nougat.slaspec b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_Nougat.slaspec new file mode 100644 index 0000000..9ef27d1 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_Nougat.slaspec @@ -0,0 +1,129 @@ +#------------------------------------------------------------------------------------ +# Sleigh specification file for DALVIK VM +#------------------------------------------------------------------------------------ + +# Source: +# https://android.googlesource.com/platform/art/+/refs/heads/nougat-release/runtime/dex_instruction_list.h + +@include "Dalvik_Base.sinc" + +@include "Dalvik_OpCode_3E_43_unused.sinc" + +@include "Dalvik_OpCode_73_return_void_no_barrier.sinc" + +@include "Dalvik_OpCode_79_unused.sinc" +@include "Dalvik_OpCode_7A_unused.sinc" + +@include "Dalvik_OpCode_E3_EA_dex.sinc" + +@include "Dalvik_OpCode_EB_F2_iput_iget.sinc" + +@include "Dalvik_OpCode_F4_unused.sinc" + +@include "Dalvik_OpCode_FA_unused.sinc" +@include "Dalvik_OpCode_FB_unused.sinc" +@include "Dalvik_OpCode_FC_unused.sinc" +@include "Dalvik_OpCode_FD_unused.sinc" +@include "Dalvik_OpCode_FE_unused.sinc" +@include "Dalvik_OpCode_FF_unused.sinc" + +define pcodeop invokeLamda; + +define token invokeLamda_operands ( 24 ) + LAMBDA_vB = ( 4 , 7 ) + LAMBDA_vG = ( 0 , 3 ) + LAMBDA_vD = ( 12 , 15 ) + LAMBDA_vC = ( 8 , 11 ) + LAMBDA_vF = ( 20 , 23 ) + LAMBDA_vE = ( 16 , 19 ) +; + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xF3, INVOKE_LAMBDA, "invoke-lambda", k25x, false, kIndexNone, kContinue | kThrow | kInvoke | kExperimental, kVerifyRegC /*TODO: | kVerifyVarArg*/) \ +# k25x, // op vC, {vD, vE, vF, vG} (B: count) +# +# See https://android.googlesource.com/platform/art/+/nougat-release/runtime/dex_instruction-inl.h +# +# * uint16 ||| uint16 +# * 7-0 15-8 7-0 15-8 +# * |------|-----|||-----|-----| +# * |opcode|vB|vG|||vD|vC|vF|vE| +# * |------|-----|||-----|-----| +# +# e.g. invoke-lambda vClosure, {vD, vE, vF, vG} -- up to 4 parameters + the closure. + +:invoke_lambda LAMBDA_vC,{} is inst0=0xf3 ; LAMBDA_vB=0 ;LAMBDA_vG ; LAMBDA_vD ; LAMBDA_vC ; LAMBDA_vF; LAMBDA_vE +{ + #TODO pCode +} +:invoke_lambda LAMBDA_vC,{LAMBDA_vD} is inst0=0xf3 ; LAMBDA_vB=1 ;LAMBDA_vG ; LAMBDA_vD ; LAMBDA_vC ; LAMBDA_vF; LAMBDA_vE +{ + #TODO pCode +} +:invoke_lambda LAMBDA_vC,{LAMBDA_vD,LAMBDA_vE} is inst0=0xf3 ; LAMBDA_vB=2 ;LAMBDA_vG ; LAMBDA_vD ; LAMBDA_vC ; LAMBDA_vF; LAMBDA_vE +{ + #TODO pCode +} +:invoke_lambda LAMBDA_vC,{LAMBDA_vD,LAMBDA_vE,LAMBDA_vF} is inst0=0xf3 ; LAMBDA_vB=3 ;LAMBDA_vG ; LAMBDA_vD ; LAMBDA_vC ; LAMBDA_vF; LAMBDA_vE +{ + #TODO pCode +} +:invoke_lambda LAMBDA_vC,{LAMBDA_vD,LAMBDA_vE,LAMBDA_vF,LAMBDA_vG} is inst0=0xf3 ; LAMBDA_vB=4 ;LAMBDA_vG ; LAMBDA_vD ; LAMBDA_vC ; LAMBDA_vF; LAMBDA_vE +{ + #TODO pCode +} + + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xF5, CAPTURE_VARIABLE, "capture-variable", k21c, false, kIndexStringRef, kExperimental, kVerifyRegA | kVerifyRegBString) \ +# +# e.g. capture-variable v1, "foobar" + +:capture_variable registerA8,B_BITS_0_15 is inst0=0xf5 ; registerA8 ; B_BITS_0_15 +{ + #TODO pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xF6, CREATE_LAMBDA, "create-lambda", k21c, false_UNUSED, kIndexMethodRef, kContinue | kThrow | kExperimental, kVerifyRegA | kVerifyRegBMethod) \ +# +# e.g. create-lambda v1, "java/io/PrintStream/print(Ljava/lang/Stream;)V" + +:create_lambda registerA8,B_BITS_0_15 is inst0=0xf6 ; registerA8 ; B_BITS_0_15 +{ + #TODO pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xF7, LIBERATE_VARIABLE, "liberate-variable", k22c, false, kIndexStringRef, kExperimental, kVerifyRegA | kVerifyRegB | kVerifyRegCString) \ +# +# e.g. liberate-variable v0, v1, "baz" + +:liberate_variable registerA4,registerB4,C_BITS_0_15 is inst0=0xf7 ; registerA4 & registerB4 ; C_BITS_0_15 +{ + #TODO pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xF8, BOX_LAMBDA, "box-lambda", k22x, true, kIndexNone, kContinue | kExperimental, kVerifyRegA | kVerifyRegB) \ + +:box_lambda registerA8,registerB16 is inst0=0xf8 ; registerA8 ; registerB16 +{ + #TODO pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xF9, UNBOX_LAMBDA, "unbox-lambda", k22c, true, kIndexTypeRef, kContinue | kThrow | kExperimental, kVerifyRegA | kVerifyRegB | kVerifyRegCType) \ + +:unbox_lambda registerA4,registerB4,C_BITS_0_15 is inst0=0xf9 ; registerA4 & registerB4 ; C_BITS_0_15 +{ + #TODO pCode +} + + diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_Oreo.slaspec b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_Oreo.slaspec new file mode 100644 index 0000000..b82f6d5 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_Oreo.slaspec @@ -0,0 +1,35 @@ +#------------------------------------------------------------------------------------ +# Sleigh specification file for DALVIK VM +#------------------------------------------------------------------------------------ + +# Source: +# https://android.googlesource.com/platform/art/+/oreo-release/runtime/dex_instruction_list.h + +@include "Dalvik_Base.sinc" + +@include "Dalvik_OpCode_3E_43_unused.sinc" + +@include "Dalvik_OpCode_73_return_void_no_barrier.sinc" + +@include "Dalvik_OpCode_79_unused.sinc" +@include "Dalvik_OpCode_7A_unused.sinc" + +@include "Dalvik_OpCode_E3_EA_dex.sinc" + +@include "Dalvik_OpCode_EB_F2_iput_iget.sinc" + +@include "Dalvik_OpCode_F3_unused.sinc" +@include "Dalvik_OpCode_F4_unused.sinc" +@include "Dalvik_OpCode_F5_unused.sinc" +@include "Dalvik_OpCode_F6_unused.sinc" +@include "Dalvik_OpCode_F7_unused.sinc" +@include "Dalvik_OpCode_F8_unused.sinc" +@include "Dalvik_OpCode_F9_unused.sinc" + +@include "Dalvik_OpCode_FA_FD_dex.sinc" + +@include "Dalvik_OpCode_FE_unused.sinc" +@include "Dalvik_OpCode_FF_unused.sinc" + + + diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_Pie.slaspec b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_Pie.slaspec new file mode 100644 index 0000000..c04c6cc --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_DEX_Pie.slaspec @@ -0,0 +1,30 @@ +#------------------------------------------------------------------------------------ +# Sleigh specification file for DALVIK VM +#------------------------------------------------------------------------------------ + +# Source: +# https://android.googlesource.com/platform/art/+/refs/heads/pie-release/libdexfile/dex/dex_instruction_list.h + +@include "Dalvik_Base.sinc" + +@include "Dalvik_OpCode_3E_43_unused.sinc" + +@include "Dalvik_OpCode_73_return_void_no_barrier.sinc" + +@include "Dalvik_OpCode_79_unused.sinc" +@include "Dalvik_OpCode_7A_unused.sinc" + +@include "Dalvik_OpCode_E3_EA_dex.sinc" + +@include "Dalvik_OpCode_EB_F2_iput_iget.sinc" + +@include "Dalvik_OpCode_F3_unused.sinc" +@include "Dalvik_OpCode_F4_unused.sinc" +@include "Dalvik_OpCode_F5_unused.sinc" +@include "Dalvik_OpCode_F6_unused.sinc" +@include "Dalvik_OpCode_F7_unused.sinc" +@include "Dalvik_OpCode_F8_unused.sinc" +@include "Dalvik_OpCode_F9_unused.sinc" + +@include "Dalvik_OpCode_FA_FD_dex.sinc" +@include "Dalvik_OpCode_FE_FF_dex.sinc" diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_ODEX_KitKat.slaspec b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_ODEX_KitKat.slaspec new file mode 100644 index 0000000..4b29e97 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_ODEX_KitKat.slaspec @@ -0,0 +1,359 @@ +#------------------------------------------------------------------------------------ +# Sleigh specification file for DALVIK VM +#------------------------------------------------------------------------------------ +# +# Source: +# https://android.googlesource.com/platform/dalvik/+/refs/heads/kitkat-release/libdex/DexFile.h +# https://android.googlesource.com/platform/dalvik/+/refs/heads/kitkat-release/libdex/DexOpcodes.h +# + +@include "Dalvik_Base.sinc" + +@include "Dalvik_OpCode_3E_43_unused.sinc" + +@include "Dalvik_OpCode_73_unused.sinc" +@include "Dalvik_OpCode_79_unused.sinc" +@include "Dalvik_OpCode_7A_unused.sinc" + +@include "Dalvik_OpCode_FF_unused.sinc" + + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:iget_volatile registerA4,[registerB4:C_BITS_0_15] is inst0=0xe3 ; registerA4 & registerB4 ; C_BITS_0_15 +{ + registerA4 = getInstanceFieldVolatile( registerB4, C_BITS_0_15:16 ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:iput_volatile registerA4,[registerB4:C_BITS_0_15] is inst0=0xe4 ; registerA4 & registerB4 ; C_BITS_0_15 +{ + setInstanceFieldVolatile( registerB4, C_BITS_0_15:16, registerA4 ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:sget_volatile registerA8,B_BITS_0_15 is inst0=0xe5 ; registerA8 ; B_BITS_0_15 +{ + registerA8 = getStaticFieldVolatile( B_BITS_0_15:16 ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:sput_volatile registerA8,B_BITS_0_15 is inst0=0xe6 ; registerA8 ; B_BITS_0_15 +{ + setStaticFieldVolatile( B_BITS_0_15:16, registerA8 ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:iget_object_volatile registerA4,[registerB4:C_BITS_0_15] is inst0=0xe7 ; registerA4 & registerB4 ; C_BITS_0_15 +{ + registerA4 = getInstanceFieldVolatile( registerB4, C_BITS_0_15:16 ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:iget_wide_volatile registerA4w,[registerB4:C_BITS_0_15] is inst0=0xe8 ; registerA4w & registerB4 ; C_BITS_0_15 +{ + registerA4w = getInstanceFieldVolatile( registerB4, C_BITS_0_15:16 ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:iput_wide_volatile registerA4w,[registerB4:C_BITS_0_15] is inst0=0xe9 ; registerA4w & registerB4 ; C_BITS_0_15 +{ + setInstanceFieldVolatile( registerB4, C_BITS_0_15:16, registerA4w ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:sget_wide_volatile registerA8w,B_BITS_0_15 is inst0=0xea ; registerA8w ; B_BITS_0_15 +{ + registerA8w = getStaticFieldVolatile( B_BITS_0_15:16 ); +} + + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:sput_wide_volatile registerA8w,B_BITS_0_15 is inst0=0xeb ; registerA8w ; B_BITS_0_15 +{ + setStaticFieldVolatile( B_BITS_0_15:16, registerA8w ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +#:iput_byte_quick registerA4,[registerB4:C_BITS_0_15] is inst0=0xec ; registerA4 & registerB4 ; C_BITS_0_15 +#{ +# setInstanceFieldQuick( registerB4, C_BITS_0_15:16, registerA4 ); +#} + +:breakpoint is inst0=0xec +{ + #TODO + breakpoint( ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:throw_verification_error registerA8,registerB16 is inst0=0xed ; registerA8 ; registerB16 +{ + registerA8 = registerB16; +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:execute_inline INLINE,{} is inst0=0xee ; N_PARAMS=0 & INLINE +{ + destination:4 = *[ram] ( ( 4 * INLINE:4 ) + 0xe0000000 ); + call [ destination ]; +} +:execute_inline INLINE,{regParamC} is inst0=0xee ; N_PARAMS=1 & INLINE & regParamC +{ + destination:4 = *[ram] ( ( 4 * INLINE:4 ) + 0xe0000000 ); + call [ destination ]; +} +:execute_inline INLINE,{regParamC,regParamD} is inst0=0xee ; N_PARAMS=2 & INLINE & regParamC & regParamD +{ + destination:4 = *[ram] ( ( 4 * INLINE:4 ) + 0xe0000000 ); + call [ destination ]; +} +:execute_inline INLINE,{regParamC,regParamD,regParamE} is inst0=0xee ; N_PARAMS=3 & INLINE & regParamC & regParamD & regParamE +{ + destination:4 = *[ram] ( ( 4 * INLINE:4 ) + 0xe0000000 ); + call [ destination ]; +} +:execute_inline INLINE,{regParamC,regParamD,regParamE,regParamF} is inst0=0xee ; N_PARAMS=4 & INLINE & regParamC & regParamD & regParamE & regParamF +{ + destination:4 = *[ram] ( ( 4 * INLINE:4 ) + 0xe0000000 ); + call [ destination ]; +} +:execute_inline INLINE,{regParamC,regParamD,regParamE,regParamF,regParamG} is inst0=0xee ; N_PARAMS=5 & INLINE & regParamC & regParamD & regParamE & regParamF & regParamG +{ + destination:4 = *[ram] ( ( 4 * INLINE:4 ) + 0xe0000000 ); + call [ destination ]; +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:execute_inline_range "inline@"^B_BITS_0_15,A_BITS_0_7,registerC16 is inst0=0xef ; A_BITS_0_7 ; B_BITS_0_15 ; registerC16 +{ + destination:4 = *[ram] ( ( 4 * B_BITS_0_15:4 ) + 0xe0000000 ); + call [ destination ]; +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# THIS ODEX INSTRUCTION WAS VALID UNTIL API version 13 (OS Version 3.2.x) + +# :invoke_direct_empty METHOD_INDEX is inst0=0xf0 ; N_PARAMS=0 & METHOD_INDEX +# { +# destination:4 = *[ram] ( ( 4 * METHOD_INDEX:4 ) + 0xe0000000 ); +# call [ destination ]; +# } +# :invoke_direct_empty METHOD_INDEX,regParamC is inst0=0xf0 ; N_PARAMS=1 & METHOD_INDEX & regParamC +# { +# destination:4 = *[ram] ( ( 4 * METHOD_INDEX:4 ) + 0xe0000000 ); +# call [ destination ]; +# } +# :invoke_direct_empty METHOD_INDEX,regParamC,regParamD is inst0=0xf0 ; N_PARAMS=2 & METHOD_INDEX & regParamC & regParamD +# { +# destination:4 = *[ram] ( ( 4 * METHOD_INDEX:4 ) + 0xe0000000 ); +# call [ destination ]; +# } +# :invoke_direct_empty METHOD_INDEX,regParamC,regParamD,regParamE is inst0=0xf0 ; N_PARAMS=3 & METHOD_INDEX & regParamC & regParamD & regParamE +# { +# destination:4 = *[ram] ( ( 4 * METHOD_INDEX:4 ) + 0xe0000000 ); +# call [ destination ]; +# } +# :invoke_direct_empty METHOD_INDEX,regParamC,regParamD,regParamE,regParamF is inst0=0xf0 ; N_PARAMS=4 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF +# { +# destination:4 = *[ram] ( ( 4 * METHOD_INDEX:4 ) + 0xe0000000 ); +# call [ destination ]; +# } +# :invoke_direct_empty METHOD_INDEX,regParamC,regParamD,regParamE,regParamF,regParamG is inst0=0xf0 ; N_PARAMS=5 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF & regParamG +# { +# destination:4 = *[ram] ( ( 4 * METHOD_INDEX:4 ) + 0xe0000000 ); +# call [ destination ]; +# } + +:invoke_object_init_range B_BITS_0_15,A_BITS_0_7,registerC16 is inst0=0xf0 ; A_BITS_0_7 ; B_BITS_0_15 ; registerC16 +{ + destination:4 = *[ram] ( ( 4 * B_BITS_0_15:4 ) + 0xe0000000 ); + call [ destination ]; +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:return_void_barrier is inst1=0xf1 & inst1_padding +{ + return [sp];#TODO +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:iget_quick "field@"^C_BITS_0_15,registerA4,registerB4 is inst0=0xf2 ; registerA4 & registerB4 ; C_BITS_0_15 +{ + registerA4 = getInstanceFieldQuick( registerB4, C_BITS_0_15:16 ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:iget_wide_quick "field@"^C_BITS_0_15,registerA4w,registerB4 is inst0=0xf3 ; registerA4w & registerB4 ; C_BITS_0_15 +{ + registerA4w = getInstanceFieldQuick( registerB4, C_BITS_0_15:16 ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:iget_object_quick "field@"^C_BITS_0_15,registerA4,registerB4 is inst0=0xf4 ; registerA4 & registerB4 ; C_BITS_0_15 +{ + registerA4 = getInstanceFieldQuick( registerB4, C_BITS_0_15:16 ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:iput_quick "field@"^C_BITS_0_15,registerA4,registerB4 is inst0=0xf5 ; registerA4 & registerB4 ; C_BITS_0_15 +{ + setInstanceFieldQuick( registerB4, C_BITS_0_15:16, registerA4 ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:iput_wide_quick "field@"^C_BITS_0_15,registerA4w,registerB4 is inst0=0xf6 ; registerA4w & registerB4 ; C_BITS_0_15 +{ + setInstanceFieldQuick( registerB4, C_BITS_0_15:16, registerA4w ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:iput_object_quick "field@"^C_BITS_0_15,registerA4,registerB4 is inst0=0xf7 ; registerA4 & registerB4 ; C_BITS_0_15 +{ + setInstanceFieldQuick( registerB4, C_BITS_0_15:16, registerA4 ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:invoke_virtual_quick "vtable@"^VTABLE_OFFSET is inst0=0xf8 ; N_PARAMS=0 & VTABLE_OFFSET +{ + invokeVirtualQuick( VTABLE_OFFSET:4 ); +} +:invoke_virtual_quick "vtable@"^VTABLE_OFFSET,regParamC is inst0=0xf8 ; N_PARAMS=1 & VTABLE_OFFSET & regParamC +{ + invokeVirtualQuick( VTABLE_OFFSET:4, regParamC ); +} +:invoke_virtual_quick "vtable@"^VTABLE_OFFSET,regParamC,regParamD is inst0=0xf8 ; N_PARAMS=2 & VTABLE_OFFSET & regParamC & regParamD +{ + invokeVirtualQuick( VTABLE_OFFSET:4, regParamC, regParamD ); +} +:invoke_virtual_quick "vtable@"^VTABLE_OFFSET,regParamC,regParamD,regParamE is inst0=0xf8 ; N_PARAMS=3 & VTABLE_OFFSET & regParamC & regParamD & regParamE +{ + invokeVirtualQuick( VTABLE_OFFSET:4, regParamC, regParamD, regParamE ); +} +:invoke_virtual_quick "vtable@"^VTABLE_OFFSET,regParamC,regParamD,regParamE,regParamF is inst0=0xf8 ; N_PARAMS=4 & VTABLE_OFFSET & regParamC & regParamD & regParamE & regParamF +{ + invokeVirtualQuick( VTABLE_OFFSET:4, regParamC, regParamD, regParamE, regParamF ); +} +:invoke_virtual_quick "vtable@"^VTABLE_OFFSET,regParamC,regParamD,regParamE,regParamF,regParamG is inst0=0xf8 ; N_PARAMS=5 & VTABLE_OFFSET & regParamC & regParamD & regParamE & regParamF & regParamG +{ + invokeVirtualQuick( VTABLE_OFFSET:4, regParamC, regParamD, regParamE, regParamF, regParamG ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:invoke_virtual_quick_range "vtable@"^B_BITS_0_15,A_BITS_0_7,registerC16 is inst0=0xf9 ; A_BITS_0_7 ; B_BITS_0_15 ; registerC16 +{ + invokeVirtualQuickRange( B_BITS_0_15:4, A_BITS_0_7:4, registerC16 ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:invoke_super_quick "vtable@"^VTABLE_OFFSET is inst0=0xfa ; N_PARAMS=0 & VTABLE_OFFSET +{ + invokeSuperQuick( VTABLE_OFFSET:4 ); +} +:invoke_super_quick "vtable@"^VTABLE_OFFSET,regParamC is inst0=0xfa ; N_PARAMS=1 & VTABLE_OFFSET & regParamC +{ + invokeSuperQuick( VTABLE_OFFSET:4, regParamC ); +} +:invoke_super_quick "vtable@"^VTABLE_OFFSET,regParamC,regParamD is inst0=0xfa ; N_PARAMS=2 & VTABLE_OFFSET & regParamC & regParamD +{ + invokeSuperQuick( VTABLE_OFFSET:4, regParamC, regParamD ); +} +:invoke_super_quick "vtable@"^VTABLE_OFFSET,regParamC,regParamD,regParamE is inst0=0xfa ; N_PARAMS=3 & VTABLE_OFFSET & regParamC & regParamD & regParamE +{ + invokeSuperQuick( VTABLE_OFFSET:4, regParamC, regParamD, regParamE ); +} +:invoke_super_quick "vtable@"^VTABLE_OFFSET,regParamC,regParamD,regParamE,regParamF is inst0=0xfa ; N_PARAMS=4 & VTABLE_OFFSET & regParamC & regParamD & regParamE & regParamF +{ + invokeSuperQuick( VTABLE_OFFSET:4, regParamC, regParamD, regParamE, regParamF ); +} +:invoke_super_quick "vtable@"^VTABLE_OFFSET,regParamC,regParamD,regParamE,regParamF,regParamG is inst0=0xfa ; N_PARAMS=5 & VTABLE_OFFSET & regParamC & regParamD & regParamE & regParamF & regParamG +{ + invokeSuperQuick( VTABLE_OFFSET:4, regParamC, regParamD, regParamE, regParamF, regParamG ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:invoke_super_quick_range "vtable@"^B_BITS_0_15,A_BITS_0_7,registerC16 is inst0=0xfb ; A_BITS_0_7 ; B_BITS_0_15 ; registerC16 +{ + invokeSuperQuickRange( B_BITS_0_15:4, A_BITS_0_7:4, registerC16 ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:iput_object_volatile registerA4,registerB4,C_BITS_0_15 is inst0=0xfc ; registerA4 & registerB4 ; C_BITS_0_15 +{ + setInstanceFieldVolatile( registerB4, C_BITS_0_15:16, registerA4 ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:sget_object_volatile registerA8,B_BITS_0_15 is inst0=0xfd ; registerA8 ; B_BITS_0_15 +{ + registerA8 = getStaticFieldVolatile( B_BITS_0_15:16 ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:sput_object_volatile registerA8,B_BITS_0_15 is inst0=0xfe ; registerA8 ; B_BITS_0_15 +{ + setStaticFieldVolatile( B_BITS_0_15:16, registerA8 ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +# 0xff ? + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_3E_43_unused.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_3E_43_unused.sinc new file mode 100644 index 0000000..aecfcfe --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_3E_43_unused.sinc @@ -0,0 +1,54 @@ +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0x3E, UNUSED_3E, "unused-3e", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_3e is inst0=0x3e +{ + #no pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0x3F, UNUSED_3F, "unused-3f", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_3f is inst0=0x3f +{ + #no pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0x40, UNUSED_40, "unused-40", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_40 is inst0=0x40 +{ + #no pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0x41, UNUSED_41, "unused-41", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_41 is inst0=0x41 +{ + #no pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0x42, UNUSED_42, "unused-42", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_42 is inst0=0x42 +{ + #no pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0x43, UNUSED_43, "unused-43", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_43 is inst0=0x43 +{ + #no pCode +} + diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_73_return_void_barrier.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_73_return_void_barrier.sinc new file mode 100644 index 0000000..3278894 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_73_return_void_barrier.sinc @@ -0,0 +1,7 @@ +#------------------------------------------------------------------------------------ +# V(0x73, RETURN_VOID_BARRIER, "return-void-barrier", k10x, false, kNone, kReturn, kVerifyNone) \ + +:return_void_barrier is inst1=0x73 & inst1_padding +{ + return [sp]; +} diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_73_return_void_no_barrier.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_73_return_void_no_barrier.sinc new file mode 100644 index 0000000..f3786d5 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_73_return_void_no_barrier.sinc @@ -0,0 +1,7 @@ +#------------------------------------------------------------------------------------ +# V(0x73, RETURN_VOID_NO_BARRIER, "return-void-no-barrier", k10x, false, kNone, kReturn, kVerifyNone) \ + +:return_void_no_barrier is inst1=0x73 & inst1_padding +{ + return [sp]; +} diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_73_unused.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_73_unused.sinc new file mode 100644 index 0000000..eb2aacc --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_73_unused.sinc @@ -0,0 +1,7 @@ +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ + +:unused_73 is inst0=0x73 +{ + #no pCode +} diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_79_unused.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_79_unused.sinc new file mode 100644 index 0000000..3cf6230 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_79_unused.sinc @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0x79, UNUSED_79, "unused-79", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_79 is inst0=0x79 +{ + #no pCode +} diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_7A_unused.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_7A_unused.sinc new file mode 100644 index 0000000..7409b47 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_7A_unused.sinc @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0x7A, UNUSED_7A, "unused-7a", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_7a is inst0=0x7a +{ + #no pCode +} diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_E3_EA_dex.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_E3_EA_dex.sinc new file mode 100644 index 0000000..e7c5f91 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_E3_EA_dex.sinc @@ -0,0 +1,94 @@ +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xE3, IGET_QUICK, "iget-quick", k22c, true, kFieldRef, kContinue | kThrow, kVerifyRegA | kVerifyRegB) \ + +:iget_quick "field@"^C_BITS_0_15,registerA4,registerB4 is inst0=0xe3 ; registerA4 & registerB4 ; C_BITS_0_15 +{ + registerA4 = getInstanceFieldQuick( registerB4, C_BITS_0_15:16 ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xE4, IGET_WIDE_QUICK, "iget-wide-quick", k22c, true, kFieldRef, kContinue | kThrow, kVerifyRegAWide | kVerifyRegB) \ + +:iget_wide_quick "field@"^C_BITS_0_15,registerA4w,registerB4 is inst0=0xe4 ; registerA4w & registerB4 ; C_BITS_0_15 +{ + registerA4w = getInstanceFieldQuick( registerB4, C_BITS_0_15:16 ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xE5, IGET_OBJECT_QUICK, "iget-object-quick", k22c, true, kFieldRef, kContinue | kThrow, kVerifyRegA | kVerifyRegB) \ + +:iget_object_quick "field@"^C_BITS_0_15,registerA4,registerB4 is inst0=0xe5 ; registerA4 & registerB4 ; C_BITS_0_15 +{ + registerA4 = getInstanceFieldQuick( registerB4, C_BITS_0_15:16 ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xE6, IPUT_QUICK, "iput-quick", k22c, false, kFieldRef, kContinue | kThrow, kVerifyRegA | kVerifyRegB) \ + +:iput_quick "field@"^C_BITS_0_15,registerA4,registerB4 is inst0=0xe6 ; registerA4 & registerB4 ; C_BITS_0_15 +{ + setInstanceFieldQuick( registerB4, C_BITS_0_15:16, registerA4 ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xE7, IPUT_WIDE_QUICK, "iput-wide-quick", k22c, false, kFieldRef, kContinue | kThrow, kVerifyRegAWide | kVerifyRegB) \ + +:iput_wide_quick "field@"^C_BITS_0_15,registerA4w,registerB4 is inst0=0xe7 ; registerA4w & registerB4 ; C_BITS_0_15 +{ + setInstanceFieldQuick( registerB4, C_BITS_0_15:16, registerA4w ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xE8, IPUT_OBJECT_QUICK, "iput-object-quick", k22c, false, kFieldRef, kContinue | kThrow, kVerifyRegA | kVerifyRegB) \ + +:iput_object_quick "field@"^C_BITS_0_15,registerA4,registerB4 is inst0=0xe8 ; registerA4 & registerB4 ; C_BITS_0_15 +{ + setInstanceFieldQuick( registerB4, C_BITS_0_15:16, registerA4 ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xE9, INVOKE_VIRTUAL_QUICK, "invoke-virtual-quick", k35c, false, kMethodRef, kContinue | kThrow | kInvoke, kVerifyVarArg) \ + +:invoke_virtual_quick "vtable@"^VTABLE_OFFSET is inst0=0xe9 ; N_PARAMS=0 & VTABLE_OFFSET +{ + invokeVirtualQuick( VTABLE_OFFSET:4 ); +} +:invoke_virtual_quick "vtable@"^VTABLE_OFFSET,regParamC is inst0=0xe9 ; N_PARAMS=1 & VTABLE_OFFSET & regParamC +{ + invokeVirtualQuick( VTABLE_OFFSET:4, regParamC ); +} +:invoke_virtual_quick "vtable@"^VTABLE_OFFSET,regParamC,regParamD is inst0=0xe9 ; N_PARAMS=2 & VTABLE_OFFSET & regParamC & regParamD +{ + invokeVirtualQuick( VTABLE_OFFSET:4, regParamC, regParamD ); +} +:invoke_virtual_quick "vtable@"^VTABLE_OFFSET,regParamC,regParamD,regParamE is inst0=0xe9 ; N_PARAMS=3 & VTABLE_OFFSET & regParamC & regParamD & regParamE +{ + invokeVirtualQuick( VTABLE_OFFSET:4, regParamC, regParamD, regParamE ); +} +:invoke_virtual_quick "vtable@"^VTABLE_OFFSET,regParamC,regParamD,regParamE,regParamF is inst0=0xe9 ; N_PARAMS=4 & VTABLE_OFFSET & regParamC & regParamD & regParamE & regParamF +{ + invokeVirtualQuick( VTABLE_OFFSET:4, regParamC, regParamD, regParamE, regParamF ); +} +:invoke_virtual_quick "vtable@"^VTABLE_OFFSET,regParamC,regParamD,regParamE,regParamF,regParamG is inst0=0xe9 ; N_PARAMS=5 & VTABLE_OFFSET & regParamC & regParamD & regParamE & regParamF & regParamG +{ + invokeVirtualQuick( VTABLE_OFFSET:4, regParamC, regParamD, regParamE, regParamF, regParamG ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xEA, INVOKE_VIRTUAL_RANGE_QUICK, "invoke-virtual/range-quick", k3rc, false, kMethodRef, kContinue | kThrow | kInvoke, kVerifyVarArgRange) \ + +:invoke_virtual_quick_range "vtable@"^B_BITS_0_15,A_BITS_0_7,registerC16 is inst0=0xea ; A_BITS_0_7 ; B_BITS_0_15 ; registerC16 +{ + invokeVirtualQuickRange( B_BITS_0_15:4, A_BITS_0_7:4, registerC16 ); +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_E3_EA_unused.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_E3_EA_unused.sinc new file mode 100644 index 0000000..121b476 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_E3_EA_unused.sinc @@ -0,0 +1,71 @@ +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xE3, UNUSED_E3, "unused-e3", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_e3 is inst0=0xe3 +{ + #no pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xE4, UNUSED_E4, "unused-e4", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_e4 is inst0=0xe4 +{ + #no pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xE5, UNUSED_E5, "unused-e5", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_e5 is inst0=0xe5 +{ + #no pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xE6, UNUSED_E6, "unused-e6", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_e6 is inst0=0xe6 +{ + #no pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xE7, UNUSED_E7, "unused-e7", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_e7 is inst0=0xe7 +{ + #no pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xE8, UNUSED_E8, "unused-e8", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_e8 is inst0=0xe8 +{ + #no pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xE9, UNUSED_E9, "unused-e9", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_e9 is inst0=0xe9 +{ + #no pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xEA, UNUSED_EA, "unused-ea", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_ea is inst0=0xea +{ + #no pCode +} diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_EB_F2_iput_iget.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_EB_F2_iput_iget.sinc new file mode 100644 index 0000000..2a9b4b1 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_EB_F2_iput_iget.sinc @@ -0,0 +1,71 @@ +#------------------------------------------------------------------------------------ +# V(0xEB, IPUT_BOOLEAN_QUICK, "iput-boolean-quick", k22c, false, kFieldRef, kContinue | kThrow | kStore | kRegCFieldOrConstant, kVerifyRegA | kVerifyRegB | kVerifyRuntimeOnly) \ + +:iput_boolean_quick registerA4,[registerB4:C_BITS_0_15] is inst0=0xeb ; registerA4 & registerB4 ; C_BITS_0_15 +{ + ptr:4 = cpool(registerB4, C_BITS_0_15:4, $(CPOOL_FIELD)); + *ptr = registerA4 : 1; +} + +#------------------------------------------------------------------------------------ +# V(0xEC, IPUT_BYTE_QUICK, "iput-byte-quick", k22c, false, kFieldRef, kContinue | kThrow | kStore | kRegCFieldOrConstant, kVerifyRegA | kVerifyRegB | kVerifyRuntimeOnly) \ + +:iput_byte_quick registerA4,[registerB4:C_BITS_0_15] is inst0=0xec ; registerA4 & registerB4 ; C_BITS_0_15 + { + ptr:4 = cpool(registerB4, C_BITS_0_15:4, $(CPOOL_FIELD)); + *ptr = registerA4 : 1; +} + +#------------------------------------------------------------------------------------ +# V(0xED, IPUT_CHAR_QUICK, "iput-char-quick", k22c, false, kFieldRef, kContinue | kThrow | kStore | kRegCFieldOrConstant, kVerifyRegA | kVerifyRegB | kVerifyRuntimeOnly) \ + +:iput_char_quick registerA4,[registerB4:C_BITS_0_15] is inst0=0xed ; registerA4 & registerB4 ; C_BITS_0_15 +{ + ptr:4 = cpool(registerB4, C_BITS_0_15:4, $(CPOOL_FIELD)); + *ptr = registerA4 : 2; +} + +#------------------------------------------------------------------------------------ +# V(0xEE, IPUT_SHORT_QUICK, "iput-short-quick", k22c, false, kFieldRef, kContinue | kThrow | kStore | kRegCFieldOrConstant, kVerifyRegA | kVerifyRegB | kVerifyRuntimeOnly) \ + +:iput_short_quick registerA4,[registerB4:C_BITS_0_15] is inst0=0xee ; registerA4 & registerB4 ; C_BITS_0_15 +{ + ptr:4 = cpool(registerB4, C_BITS_0_15:4, $(CPOOL_FIELD)); + *ptr = registerA4 : 2; +} + +#------------------------------------------------------------------------------------ +# V(0xEF, IGET_BOOLEAN_QUICK, "iget-boolean-quick", k22c, true, kFieldRef, kContinue | kThrow | kLoad | kRegCFieldOrConstant, kVerifyRegA | kVerifyRegB | kVerifyRuntimeOnly) \ + +:iget_boolean_quick registerA4,[registerB4:C_BITS_0_15] is inst0=0xef ; registerA4 & registerB4 ; C_BITS_0_15 +{ + ptr:4 = cpool( registerB4, C_BITS_0_15:4, $(CPOOL_FIELD)); + registerA4 = zext( *:1 ptr ); +} + +#------------------------------------------------------------------------------------ +# V(0xF0, IGET_BYTE_QUICK, "iget-byte-quick", k22c, true, kFieldRef, kContinue | kThrow | kLoad | kRegCFieldOrConstant, kVerifyRegA | kVerifyRegB | kVerifyRuntimeOnly) \ + +:iget_byte_quick registerA4,[registerB4:C_BITS_0_15] is inst0=0xf0 ; registerA4 & registerB4 ; C_BITS_0_15 +{ + ptr:4 = cpool( registerB4, C_BITS_0_15:4, $(CPOOL_FIELD)); + registerA4 = sext( *:1 ptr ); +} + +#------------------------------------------------------------------------------------ +# V(0xF1, IGET_CHAR_QUICK, "iget-char-quick", k22c, true, kFieldRef, kContinue | kThrow | kLoad | kRegCFieldOrConstant, kVerifyRegA | kVerifyRegB | kVerifyRuntimeOnly) \ + +:iget_char_quick registerA4,[registerB4:C_BITS_0_15] is inst0=0xf1 ; registerA4 & registerB4 ; C_BITS_0_15 + { + ptr:4 = cpool( registerB4, C_BITS_0_15:4, $(CPOOL_FIELD)); + registerA4 = zext( *:2 ptr ); +} + +#------------------------------------------------------------------------------------ +# V(0xF2, IGET_SHORT_QUICK, "iget-short-quick", k22c, true, kFieldRef, kContinue | kThrow | kLoad | kRegCFieldOrConstant, kVerifyRegA | kVerifyRegB | kVerifyRuntimeOnly) \ + +:iget_short_quick registerA4,[registerB4:C_BITS_0_15] is inst0=0xf2 ; registerA4 & registerB4 ; C_BITS_0_15 +{ + ptr:4 = cpool( registerB4, C_BITS_0_15:4, $(CPOOL_FIELD)); + registerA4 = sext( *:2 ptr ); +} diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_EB_F2_unused.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_EB_F2_unused.sinc new file mode 100644 index 0000000..09a3aa8 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_EB_F2_unused.sinc @@ -0,0 +1,71 @@ +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xEB, UNUSED_EB, "unused-eb", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_eb is inst0=0xeb +{ + #no pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xEC, UNUSED_EC, "unused-ec", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_ec is inst0=0xec +{ + #no pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xED, UNUSED_ED, "unused-ed", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_ed is inst0=0xed +{ + #no pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xEE, UNUSED_EE, "unused-ee", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_ee is inst0=0xee +{ + #no pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xEF, UNUSED_EF, "unused-ef", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_ef is inst0=0xef +{ + #no pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xF0, UNUSED_F0, "unused-f0", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_f0 is inst0=0xf0 +{ + #no pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xF1, UNUSED_F1, "unused-f1", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_f1 is inst0=0xf1 +{ + #no pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xF2, UNUSED_F2, "unused-f2", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_f2 is inst0=0xf2 +{ + #no pCode +} diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_F3_unused.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_F3_unused.sinc new file mode 100644 index 0000000..0e2cc34 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_F3_unused.sinc @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xF3, UNUSED_F3, "unused-f3", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_f3 is inst0=0xf3 +{ + #no pCode +} diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_F4_unused.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_F4_unused.sinc new file mode 100644 index 0000000..1e76ac5 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_F4_unused.sinc @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xF4, UNUSED_F4, "unused-f4", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_f4 is inst0=0xf4 +{ + #no pCode +} diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_F5_unused.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_F5_unused.sinc new file mode 100644 index 0000000..9e06181 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_F5_unused.sinc @@ -0,0 +1,9 @@ +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xF5, UNUSED_F5, "unused-f5", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_f5 is inst0=0xf5 +{ + #no pCode +} + diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_F6_unused.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_F6_unused.sinc new file mode 100644 index 0000000..0283f74 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_F6_unused.sinc @@ -0,0 +1,9 @@ +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xF6, UNUSED_F6, "unused-f6", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_f6 is inst0=0xf6 +{ + #no pCode +} + diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_F7_unused.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_F7_unused.sinc new file mode 100644 index 0000000..ec08259 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_F7_unused.sinc @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xF7, UNUSED_F7, "unused-f7", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_f7 is inst0=0xf7 +{ + #no pCode +} diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_F8_unused.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_F8_unused.sinc new file mode 100644 index 0000000..2ea3d0d --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_F8_unused.sinc @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xF8, UNUSED_F8, "unused-f8", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_f8 is inst0=0xf8 +{ + #no pCode +} diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_F9_unused.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_F9_unused.sinc new file mode 100644 index 0000000..d36d1a9 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_F9_unused.sinc @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xF9, UNUSED_F9, "unused-f9", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_f9 is inst0=0xf9 +{ + #no pCode +} diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_FA_FD_dex.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_FA_FD_dex.sinc new file mode 100644 index 0000000..5709a7b --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_FA_FD_dex.sinc @@ -0,0 +1,178 @@ +define token invoke_poly_operands_2 ( 8 ) + POLY_ARG_COUNT = ( 4 , 7 ) + POLY_PARAM_G = ( 0 , 3 ) +; + +define token invoke_poly_operands_1 ( 48 ) + POLY_METHOD_INDEX = ( 0 , 15 ) + POLY_PARAM_D = ( 16 , 19 ) + POLY_PARAM_C = ( 20 , 23 ) + POLY_PARAM_F = ( 24 , 27 ) + POLY_PARAM_E = ( 28 , 31 ) + POLY_PROTO_INDEX = ( 32 , 47 ) +; + +#define token invoke_poly_operands_1 ( 64 ) +# POLY_METHOD_INDEX = ( 0 , 15 ) +# POLY_METHOD_HANDLE = ( 16 , 31 ) +# POLY_PARAM_D = ( 32 , 35 ) +# POLY_PARAM_C = ( 36 , 39 ) +# POLY_PARAM_F = ( 40 , 43 ) +# POLY_PARAM_E = ( 44 , 47 ) +# POLY_PROTO_INDEX = ( 48 , 63 ) +#; + +regPolyC: reg is POLY_PARAM_C [ reg = (POLY_PARAM_C * 4) + 0x1000; ] { export *[register]:4 reg; } +regPolyD: reg is POLY_PARAM_D [ reg = (POLY_PARAM_D * 4) + 0x1000; ] { export *[register]:4 reg; } +regPolyE: reg is POLY_PARAM_E [ reg = (POLY_PARAM_E * 4) + 0x1000; ] { export *[register]:4 reg; } +regPolyF: reg is POLY_PARAM_F [ reg = (POLY_PARAM_F * 4) + 0x1000; ] { export *[register]:4 reg; } +regPolyG: reg is POLY_PARAM_G [ reg = (POLY_PARAM_G * 4) + 0x1000; ] { export *[register]:4 reg; } + +define token invoke_poly_range_operands ( 40 ) + POLY_RANGE_ARG_COUNT = ( 0 , 7 ) + POLY_RANGE_METHOD_INDEX = ( 8 , 23 ) + POLY_RANGE_PROTO_INDEX = ( 24 , 39 ) +; + +#------------------------------------------------------------------------------------ +# V(0xFA, INVOKE_POLYMORPHIC, "invoke-polymorphic", k45cc, kIndexMethodAndProtoRef, kContinue | kThrow | kInvoke, kVerifyRegBMethod | kVerifyVarArgNonZero | kVerifyRegHPrototype) \ +# +# invoke-polymorphic {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH +# +# A: argument word count (4 bits) +# B: method reference index (16 bits) +# C: method handle reference to invoke (16 bits) +# D..G: argument registers (4 bits each) +# H: prototype reference index (16 bits) +# +# case Instruction::k45cc: { // op {vC, vD, vE, vF, vG}, method@BBBB, proto@HHHH +# +# Invoke the indicated method handle. +# The result (if any) may be stored with an appropriate move-result* variant as the immediately subsequent instruction. +# The method reference must be to java.lang.invoke.MethodHandle.invoke or java.lang.invoke.MethodHandle.invokeExact. +# The prototype reference describes the argument types provided and the expected return type. +# +# Present in Dex files from version 038 onwards. + +:invoke_polymorphic "meth@"^POLY_METHOD_INDEX,"proto@"^POLY_PROTO_INDEX,{} is inst0=0xfa ; POLY_ARG_COUNT=0 ; POLY_METHOD_INDEX & POLY_PROTO_INDEX +{ + #TODO pCode +} +:invoke_polymorphic "meth@"^POLY_METHOD_INDEX,"proto@"^POLY_PROTO_INDEX,{regPolyC} is inst0=0xfa ; POLY_ARG_COUNT=1 ; POLY_METHOD_INDEX & POLY_PROTO_INDEX & regPolyC +{ + #TODO pCode +} +:invoke_polymorphic "meth@"^POLY_METHOD_INDEX,"proto@"^POLY_PROTO_INDEX,{regPolyC,regPolyD} is inst0=0xfa ; POLY_ARG_COUNT=2 ; POLY_METHOD_INDEX & POLY_PROTO_INDEX & regPolyC & regPolyD +{ + #TODO pCode +} +:invoke_polymorphic "meth@"^POLY_METHOD_INDEX,"proto@"^POLY_PROTO_INDEX,{regPolyC,regPolyD,regPolyE} is inst0=0xfa ; POLY_ARG_COUNT=3 ; POLY_METHOD_INDEX & POLY_PROTO_INDEX & regPolyC & regPolyD & regPolyE +{ + #TODO pCode +} +:invoke_polymorphic "meth@"^POLY_METHOD_INDEX,"proto@"^POLY_PROTO_INDEX,{regPolyC,regPolyD,regPolyE,regPolyF} is inst0=0xfa ; POLY_ARG_COUNT=4 ; POLY_METHOD_INDEX & POLY_PROTO_INDEX & regPolyC & regPolyD & regPolyE & regPolyF +{ + #TODO pCode +} +:invoke_polymorphic "meth@"^POLY_METHOD_INDEX,"proto@"^POLY_PROTO_INDEX,{regPolyC,regPolyD,regPolyE,regPolyF,regPolyG} is inst0=0xfa ; POLY_ARG_COUNT=5 ; POLY_METHOD_INDEX & POLY_PROTO_INDEX & regPolyC & regPolyD & regPolyE & regPolyF ; regPolyG +{ + #TODO pCode +} + +#------------------------------------------------------------------------------------ +# V(0xFB, INVOKE_POLYMORPHIC_RANGE, "invoke-polymorphic/range", k4rcc, kIndexMethodAndProtoRef, kContinue | kThrow | kInvoke, kVerifyRegBMethod | kVerifyVarArgRangeNonZero | kVerifyRegHPrototype) \ +# +# invoke-polymorphic/range {vCCCC .. vNNNN}, meth@BBBB, proto@HHHH +# +# A: argument word count (8 bits) +# B: method reference index (16 bits) +# C: method handle reference to invoke (16 bits) +# H: prototype reference index (16 bits) +# N = A + C - 1 +# +# case Instruction::k4rcc: { // op {vCCCC .. v(CCCC+AA-1)}, method@BBBB, proto@HHHH +# +# Invoke the indicated method handle. See the invoke-polymorphic description above for details. +# +# Present in Dex files from version 038 onwards. + +:invoke_polymorphic_range "meth@"^POLY_RANGE_METHOD_INDEX,"cnt@"^POLY_RANGE_ARG_COUNT,"proto@"^POLY_RANGE_PROTO_INDEX is inst0=0xfb ; POLY_RANGE_ARG_COUNT & POLY_RANGE_METHOD_INDEX & POLY_RANGE_PROTO_INDEX +{ + #TODO pCode +} + +#------------------------------------------------------------------------------------ +# V(0xFC, INVOKE_CUSTOM, "invoke-custom", k35c, kIndexCallSiteRef, kContinue | kThrow, kVerifyRegBCallSite | kVerifyVarArg) \ +# +# invoke-custom {vC, vD, vE, vF, vG}, call_site@BBBB +# +# A: argument word count (4 bits) +# B: call site reference index (16 bits) +# C..G: argument registers (4 bits each) +# +# Resolves and invokes the indicated call site. +# The result from the invocation (if any) may be stored with an +# appropriate move-result* variant as the immediately subsequent instruction. +# +# This instruction executes in two phases: call site resolution and call site invocation. +# +# Call site resolution checks whether the indicated call site has an associated +# java.lang.invoke.CallSite instance. If not, the bootstrap linker method for the +# indicated call site is invoked using arguments present in the DEX file (see call_site_item). +# The bootstrap linker method returns a java.lang.invoke.CallSite instance that will then +# be associated with the indicated call site if no association exists. Another thread may +# have already made the association first, and if so execution of the instruction continues +# with the first associated java.lang.invoke.CallSite instance. +# +# Call site invocation is made on the java.lang.invoke.MethodHandle target of the resolved +# java.lang.invoke.CallSite instance. The target is invoked as if executing invoke-polymorphic +# (described above) using the method handle and arguments to the invoke-custom instruction as +# the arguments to an exact method handle invocation. +# +# Present in Dex files from version 038 onwards. + +:invoke_custom METHOD_INDEX,{} is inst0=0xfc ; N_PARAMS=0 & METHOD_INDEX +{ + #TODO pCode -- see invoke_direct +} +:invoke_custom METHOD_INDEX,{regParamC} is inst0=0xfc ; N_PARAMS=1 & METHOD_INDEX & regParamC +{ + #TODO pCode +} +:invoke_custom ^METHOD_INDEX,{regParamC,regParamD} is inst0=0xfc ; N_PARAMS=2 & METHOD_INDEX & regParamC & regParamD +{ + #TODO pCode +} +:invoke_custom METHOD_INDEX,{regParamC,regParamD,regParamE} is inst0=0xfc ; N_PARAMS=3 & METHOD_INDEX & regParamC & regParamD & regParamE +{ + #TODO pCode +} +:invoke_custom METHOD_INDEX,{regParamC,regParamD,regParamE,regParamF} is inst0=0xfc ; N_PARAMS=4 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF +{ + #TODO pCode +} +:invoke_custom METHOD_INDEX,{regParamC,regParamD,regParamE,regParamF,regParamG} is inst0=0xfc ; N_PARAMS=5 & METHOD_INDEX & regParamC & regParamD & regParamE & regParamF & regParamG +{ + #TODO pCode +} + +#------------------------------------------------------------------------------------ +# V(0xFD, INVOKE_CUSTOM_RANGE, "invoke-custom/range", k3rc, kIndexCallSiteRef, kContinue | kThrow, kVerifyRegBCallSite | kVerifyVarArgRange) \ +# +# invoke-custom/range {vCCCC .. vNNNN}, call_site@BBBB +# +# A: argument word count (8 bits) +# B: call site reference index (16 bits) +# C: first argument register (16-bits) +# N = A + C - 1 +# +# Resolve and invoke a call site. See the invoke-custom description above for details. +# +# Present in Dex files from version 038 onwards. + +:invoke_custom_range B_BITS_0_15,A_BITS_0_7,registerC16 is inst0=0xfd ; A_BITS_0_7 ; B_BITS_0_15 ; registerC16 +{ + #TODO pCode -- see invoke_direct_range +} + +#------------------------------------------------------------------------------------ diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_FA_unused.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_FA_unused.sinc new file mode 100644 index 0000000..0896131 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_FA_unused.sinc @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xFA, UNUSED_FA, "unused-fa", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_fa is inst0=0xfa +{ + #no pCode +} diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_FB_unused.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_FB_unused.sinc new file mode 100644 index 0000000..a51cfd8 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_FB_unused.sinc @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xFB, UNUSED_FB, "unused-fb", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_fb is inst0=0xfb +{ + #no pCode +} diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_FC_unused.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_FC_unused.sinc new file mode 100644 index 0000000..9ad6eba --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_FC_unused.sinc @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xFC, UNUSED_FC, "unused-fc", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_fc is inst0=0xfc +{ + #no pCode +} diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_FD_unused.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_FD_unused.sinc new file mode 100644 index 0000000..864b3d3 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_FD_unused.sinc @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xFD, UNUSED_FD, "unused-fd", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_fd is inst0=0xfd +{ + #no pCode +} diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_FE_FF_dex.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_FE_FF_dex.sinc new file mode 100644 index 0000000..859e65d --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_FE_FF_dex.sinc @@ -0,0 +1,20 @@ + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xFE, CONST_METHOD_HANDLE, "const-method-handle", k21c, kIndexMethodHandleRef, kContinue | kThrow, 0, kVerifyRegA | kVerifyRegBMethodHandle) \ + +:const_method_handle registerA8,B_BITS_0_15 is inst0=0xfe ; registerA8 ; B_BITS_0_15 +{ + #TODO pCode +} + +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xFF, CONST_METHOD_TYPE, "const-method-type", k21c, kIndexProtoRef, kContinue | kThrow, 0, kVerifyRegA | kVerifyRegBPrototype) + +:const_method_type registerA8,B_BITS_0_15 is inst0=0xff ; registerA8 ; B_BITS_0_15 +{ + #TODO pCode +} + +#------------------------------------------------------------------------------------ diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_FE_unused.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_FE_unused.sinc new file mode 100644 index 0000000..4f30f21 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_FE_unused.sinc @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xFE, UNUSED_FE, "unused-fe", k10x, false, kUnknown, 0, kVerifyError) \ + +:unused_fe is inst0=0xfe +{ + #no pCode +} diff --git a/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_FF_unused.sinc b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_FF_unused.sinc new file mode 100644 index 0000000..f937e75 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Dalvik/data/languages/Dalvik_OpCode_FF_unused.sinc @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------------ +#------------------------------------------------------------------------------------ +# V(0xFF, UNUSED_FF, "unused-ff", k10x, false, kUnknown, 0, kVerifyError) + +:unused_ff is inst0=0xff +{ + #no pCode +} diff --git a/python/icicle/Ghidra/Processors/HCS08/data/languages/HC05-M68HC05TB.pspec b/python/icicle/Ghidra/Processors/HCS08/data/languages/HC05-M68HC05TB.pspec new file mode 100644 index 0000000..ba3c607 --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS08/data/languages/HC05-M68HC05TB.pspec @@ -0,0 +1,60 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/HCS08/data/languages/HC05.ldefs b/python/icicle/Ghidra/Processors/HCS08/data/languages/HC05.ldefs new file mode 100644 index 0000000..4caea38 --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS08/data/languages/HC05.ldefs @@ -0,0 +1,28 @@ + + + + + HC05 (6805) Microcontroller Family + + + + HC05 (6805) Microcontroller Family - M68HC05TB + + + diff --git a/python/icicle/Ghidra/Processors/HCS08/data/languages/HC05.pspec b/python/icicle/Ghidra/Processors/HCS08/data/languages/HC05.pspec new file mode 100644 index 0000000..1b96212 --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS08/data/languages/HC05.pspec @@ -0,0 +1,33 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/HCS08/data/languages/HC05.slaspec b/python/icicle/Ghidra/Processors/HCS08/data/languages/HC05.slaspec new file mode 100644 index 0000000..4e8a0d2 --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS08/data/languages/HC05.slaspec @@ -0,0 +1,5 @@ +# sleigh specification file for Freescale HC05 (6805, 68HC05) + +@define HC05 "1" + +@include "HCS_HC.sinc" diff --git a/python/icicle/Ghidra/Processors/HCS08/data/languages/HC08-MC68HC908QY4.pspec b/python/icicle/Ghidra/Processors/HCS08/data/languages/HC08-MC68HC908QY4.pspec new file mode 100644 index 0000000..c7febf3 --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS08/data/languages/HC08-MC68HC908QY4.pspec @@ -0,0 +1,127 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/HCS08/data/languages/HC08.ldefs b/python/icicle/Ghidra/Processors/HCS08/data/languages/HC08.ldefs new file mode 100644 index 0000000..1213b4c --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS08/data/languages/HC08.ldefs @@ -0,0 +1,28 @@ + + + + + HC08 Microcontroller Family + + + + HC08 Microcontroller Family - MC68HC908QY4 + + + diff --git a/python/icicle/Ghidra/Processors/HCS08/data/languages/HC08.pspec b/python/icicle/Ghidra/Processors/HCS08/data/languages/HC08.pspec new file mode 100644 index 0000000..77be20c --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS08/data/languages/HC08.pspec @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/HCS08/data/languages/HC08.slaspec b/python/icicle/Ghidra/Processors/HCS08/data/languages/HC08.slaspec new file mode 100644 index 0000000..81bac03 --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS08/data/languages/HC08.slaspec @@ -0,0 +1,5 @@ +# sleigh specification file for Freescale HC08 (68HC08) + +@define HC08 "1" + +@include "HCS_HC.sinc" diff --git a/python/icicle/Ghidra/Processors/HCS08/data/languages/HCS08-MC9S08GB60.pspec b/python/icicle/Ghidra/Processors/HCS08/data/languages/HCS08-MC9S08GB60.pspec new file mode 100644 index 0000000..0cd50bd --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS08/data/languages/HCS08-MC9S08GB60.pspec @@ -0,0 +1,244 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/HCS08/data/languages/HCS08.cspec b/python/icicle/Ghidra/Processors/HCS08/data/languages/HCS08.cspec new file mode 100644 index 0000000..f0c0752 --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS08/data/languages/HCS08.cspec @@ -0,0 +1,50 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/HCS08/data/languages/HCS08.ldefs b/python/icicle/Ghidra/Processors/HCS08/data/languages/HCS08.ldefs new file mode 100644 index 0000000..778ab66 --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS08/data/languages/HCS08.ldefs @@ -0,0 +1,28 @@ + + + + + HCS08 Microcontroller Family + + + + HCS08 Microcontroller Family - MC9S08GB60 + + + diff --git a/python/icicle/Ghidra/Processors/HCS08/data/languages/HCS08.opinion b/python/icicle/Ghidra/Processors/HCS08/data/languages/HCS08.opinion new file mode 100644 index 0000000..8922b12 --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS08/data/languages/HCS08.opinion @@ -0,0 +1,6 @@ + + + + + + diff --git a/python/icicle/Ghidra/Processors/HCS08/data/languages/HCS08.pspec b/python/icicle/Ghidra/Processors/HCS08/data/languages/HCS08.pspec new file mode 100644 index 0000000..4f0dc75 --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS08/data/languages/HCS08.pspec @@ -0,0 +1,28 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/HCS08/data/languages/HCS08.slaspec b/python/icicle/Ghidra/Processors/HCS08/data/languages/HCS08.slaspec new file mode 100644 index 0000000..15030c0 --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS08/data/languages/HCS08.slaspec @@ -0,0 +1,5 @@ +# sleigh specification file for Freescale HCS08 (68HCS08) + +@define HCS08 "1" + +@include "HCS_HC.sinc" diff --git a/python/icicle/Ghidra/Processors/HCS08/data/languages/HCS_HC.sinc b/python/icicle/Ghidra/Processors/HCS08/data/languages/HCS_HC.sinc new file mode 100644 index 0000000..567207d --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS08/data/languages/HCS_HC.sinc @@ -0,0 +1,2083 @@ +# common include file for HCS08, HC08 and HC05(6805) constructors + +define endian=big; +define alignment=1; + +define space RAM type=ram_space size=2 default; +define space register type=register_space size=1; + +@define VECTOR_SWI "0xFFFC" + +################################################################ +# Registers +################################################################ + +define register offset=0x00 size=1 [ A ]; + +@if defined(HC05) +define register offset=0x10 size=1 [ X ]; +@elif defined(HCS08) || defined(HC08) +define register offset=0x10 size=2 [ HIX ]; # H:X in the manual +define register offset=0x10 size=1 [ HI X ]; +@endif + +define register offset=0x20 size=2 [ PC SP ]; +define register offset=0x20 size=1 [ PCH PCL SPH SPL ]; + +define register offset=0x30 size=1 [ CCR ]; + +@if defined(HCS08) || defined(HC08) +@define V "CCR[7,1]" # Two's complement overflow Flag +@endif + +# "CCR[6,1]" # unused +# "CCR[5,1]" # unused +@define H "CCR[4,1]" # Half Carry Flag +@define I "CCR[3,1]" # Maskable interrupt control bit +@define N "CCR[2,1]" # Negative Flag +@define Z "CCR[1,1]" # Zero Flag +@define C "CCR[0,1]" # Carry/Borrow Flag + + + +################################################################ +# Tokens +################################################################ + +define token opbyte8 (8) + op = (0,7) + op4_7 = (4,7) + op4_6 = (4,6) + nIndex = (1,3) + op0_0 = (0,0) +; + +define token opbyte16 (16) + op16 = (0,15) +; + +define token data8 (8) + imm8 = (0,7) + simm8 = (0,7) signed + rel = (0,7) signed +; + +define token data16 (16) + imm16 = (0,15) +; + + +################################################################ +# Pseudo Instructions +################################################################ + +@if defined(HCS08) || defined(HC08) || defined(HC05) +define pcodeop readIRQ; +define pcodeop stop; +define pcodeop wait; +@endif + +@if defined(HCS08) || defined(HC08) +define pcodeop decimalAdjustAccumulator; +define pcodeop decimalAdjustCarry; +@endif + +@if defined(HCS08) +define pcodeop backgroundDebugMode; +@endif + + +################################################################ +# Addressing tables +################################################################ + +@if defined(HCS08) || defined(HC08) || defined(HC05) +opr8a_8: imm8 is imm8 { export *:1 imm8; } +opr16a_8: imm16 is imm16 { export *:1 imm16; } +iopr8i: "#"imm8 is imm8 { export *[const]:1 imm8; } +@endif + +@if defined(HCS08) || defined(HC08) +opr8a_16: imm8 is imm8 { export *:2 imm8; } +iopr8is: "#"simm8 is simm8 { export *[const]:1 simm8; } +iopr16i: "#"imm16 is imm16 { export *[const]:2 imm16; } +oprx8: imm8 is imm8 { export *[const]:1 imm8; } +oprx8_8_SP: imm8,SP is imm8 & SP { address:2 = SP + zext(imm8:1); export *:1 address; } +oprx16_8_SP: imm16,SP is imm16 & SP { address:2 = SP + imm16:2; export *:1 address; } +@endif + +@if defined(HCS08) +opr16a_16: imm16 is imm16 { export *:2 imm16; } +oprx8_16_SP: imm8,SP is imm8 & SP { address:2 = SP + zext(imm8:1); export *:2 address; } +@endif + +# X or HIX addressing + +@if defined(HC05) +oprx8_8_X: imm8,X is imm8 & X { address:1 = X + imm8:1; export *:1 address; } +comma_X: ","X is X { address:1 = X; export *:1 address; } +@endif + +@if defined(HCS08) || defined(HC08) +oprx8_8_X: imm8,X is imm8 & X { address:2 = HIX + zext(imm8:1); export *:1 address; } +oprx16_8_X: imm16,X is imm16 & X { address:2 = HIX + imm16:2; export *:1 address; } +comma_X: ","X is X { address:2 = HIX; export *:1 address; } +@endif + +@if defined(HCS08) +oprx8_16_X: imm8,X is imm8 & X { address:2 = HIX + zext(imm8:1); export *:2 address; } +oprx16_16_X: imm16,X is imm16 & X { address:2 = HIX + imm16:2; export *:2 address; } +@endif + + +# address decoding + +OP1: iopr8i is op4_6=2; iopr8i { export iopr8i; } +OP1: opr8a_8 is op4_6=3; opr8a_8 { export opr8a_8; } +OP1: opr16a_8 is op4_6=4; opr16a_8 { export opr16a_8; } + +@if defined(HCS08) || defined(HC08) +OP1: oprx16_8_X is op4_6=5; oprx16_8_X { export oprx16_8_X; } +@endif + +OP1: oprx8_8_X is op4_6=6; oprx8_8_X { export oprx8_8_X; } +OP1: comma_X is op4_6=7 & comma_X { export comma_X; } + +@if defined(HCS08) || defined(HC08) +op2_opr8a: imm8 is imm8 { export *:1 imm8; } +@endif + + +ADDR: opr8a_8 is op4_6=3; opr8a_8 { export opr8a_8; } +ADDR: opr16a_8 is op4_6=4; opr16a_8 { export opr16a_8; } + +@if defined(HCS08) || defined(HC08) +ADDRI: oprx16_8_X is op4_6=5; oprx16_8_X { export oprx16_8_X; } +@endif + +ADDRI: oprx8_8_X is op4_6=6; oprx8_8_X { export oprx8_8_X; } +ADDRI: comma_X is op4_6=7 & comma_X { export comma_X; } + +REL: reloc is rel [ reloc = inst_next + rel; ] { export *:1 reloc; } + +NthBit: nthbit is nIndex [ nthbit = (1 << nIndex); ] { export *[const]:1 nthbit; } + + +################################################################ +# Macros +################################################################ + + +@if defined(HCS08) || defined(HC08) + +macro additionFlags(operand1, operand2, result) { + local AFmask = -1 >> 4; + $(H) = (((operand1 & AFmask) + (operand2 & AFmask)) & (AFmask + 1)) != 0; + $(V) = scarry(operand1, operand2); + $(N) = result s< 0; + $(C) = carry(operand1, operand2); + $(Z) = (result == 0); +} + +macro additionWithCarry(operand1, operand2, result) { + local Ccopy = zext($(C)); + local AFmask = -1 >> 4; + $(H) = (((operand1 & AFmask) + (operand2 & AFmask) + Ccopy) & (AFmask + 1)) != 0; + $(V) = scarry(operand1, operand2); + $(C) = carry(operand1, operand2); + local tempResult = operand1 + operand2; + $(C) = $(C) || carry(tempResult, Ccopy); + $(V) = $(V) ^^ scarry(tempResult, Ccopy); + result = tempResult + Ccopy; + $(N) =result s< 0; + $(Z) = (result == 0); +} + +@elif defined(HC05) + +# V is not implemented in HC05 + +macro additionFlags(operand1, operand2, result) { + local AFmask = -1 >> 4; + $(H) = (((operand1 & AFmask) + (operand2 & AFmask)) & (AFmask + 1)) != 0; + $(N) =result s< 0; + $(Z) = (result == 0); + $(C) = carry(operand1, operand2); +} + +macro additionWithCarry(operand1, operand2, result) { + local Ccopy = zext($(C)); + local AFmask = -1 >> 4; + $(H) = (((operand1 & AFmask) + (operand2 & AFmask) + Ccopy) & (AFmask + 1)) != 0; + $(C) = carry(operand1, operand2); + local tempResult = operand1 + operand2; + $(C) = $(C) || carry(tempResult, Ccopy); + result = tempResult + Ccopy; + $(N) =result s< 0; + $(Z) = (result == 0); +} + +@endif + + +@if defined(HCS08) || defined(HC08) + +macro subtractionFlags(operand1, operand2, result) { + $(V) = sborrow(operand1, operand2); + $(N) = (result s< 0); + $(Z) = (result == 0); + $(C) = operand1 < operand2; +} + +macro subtractWithCarry(operand1, operand2, result) { + local Ccopy = zext($(C)); + $(V) = sborrow(operand1, operand2); + + $(C) = operand1 < operand2; + local tempResult = operand1 - operand2; + $(C) = $(C) || (tempResult < Ccopy); + $(V) = $(V) ^^ sborrow(tempResult, Ccopy); + result = tempResult - Ccopy; + $(N) = result s< 0; +} + +@elif defined(HC05) +macro subtractionFlags(operand1, operand2, result) { + # V is not implemented in HC05 + + $(N) = (result s< 0); + $(Z) = (result == 0); + $(C) = operand1 < operand2; +} + +macro subtractWithCarry(operand1, operand2, result) { + local Ccopy = zext($(C)); + # V is not implemented in HC05 + + $(C) = operand1 < operand2; + local tempResult = operand1 - operand2; + $(C) = $(C) || (tempResult < Ccopy); + result = tempResult - Ccopy; + $(N) = result s< 0; +} + +@endif + +@if defined(HCS08) || defined(HC08) +macro V_equals_0() { + $(V) = 0; +} +@elif defined(HC05) +macro V_equals_0() {} # empty macro because V is not implemented in HC05 +@endif + +@if defined(HCS08) || defined(HC08) +macro V_equals_C() { + $(V) = $(C); +} +@elif defined(HC05) +macro V_equals_C() {} # empty macro because V is not implemented in HC05 +@endif + +@if defined(HCS08) || defined(HC08) +macro V_equals_N_xor_C() { + $(V) = $(N) ^ $(C); +} +@elif defined(HC05) +macro V_equals_N_xor_C() {} # empty macro because V is not implemented in HC05 +@endif + +@if defined(HCS08) || defined(HC08) +macro V_CMP_flag(operand, result) { + $(V) = ( ((A & ~operand & ~result) | (~A & operand & result)) & 0b10000000 ) != 0; +} +@elif defined(HC05) +macro V_CMP_flag(operand, result) {} # empty macro because V is not implemented in HC05 +@endif + +@if defined(HCS08) || defined(HC08) +macro V_CPHX_flag(operand, result) { + $(V) = ( ((HIX & ~operand & ~result) | (~HIX & operand & result)) & 0x8000 ) != 0; +} +@elif defined(HC05) +macro V_CPHX_flag(operand, result) {} # empty macro because V is not implemented in HC05 +@endif + +@if defined(HCS08) || defined(HC08) +macro V_CPX_flag(operand, result) { + $(V) = ( ((X & ~operand & ~result) | (~X & operand & result)) & 0b10000000 ) != 0; +} +@elif defined(HC05) +macro V_CPX_flag(operand, result) {} # empty macro because V is not implemented in HC05 +@endif + +@if defined(HCS08) || defined(HC08) +macro V_DEC_flag(operand, result) { + $(V) = ( (~result & operand) & 0b10000000 ) != 0; +} +@elif defined(HC05) +macro V_DEC_flag(operand, result) {} # empty macro because V is not implemented in HC05 +@endif + +@if defined(HCS08) || defined(HC08) +macro V_INC_flag(operand, result) { + $(V) = ( (~operand & result) & 0b10000000 ) != 0; +} +@elif defined(HC05) +macro V_INC_flag(operand, result) {} # empty macro because V is not implemented in HC05 +@endif + +@if defined(HCS08) || defined(HC08) +macro V_NEG_flag(operand, result) { + $(V) = ( (operand & result) & 0b10000000 ) != 0; +} +@elif defined(HC05) +macro V_NEG_flag(operand, result) {} # empty macro because V is not implemented in HC05 +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +macro Pull1(operand) { + SP = SP + 1; + operand = *:1 SP; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +macro Pull2(operand) { + SP = SP + 1; + operand = *:2 SP; + SP = SP + 1; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +macro Push1(operand) { + *:1 SP = operand; + SP = SP - 1; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +macro Push2(operand) { + SP = SP - 1; + *:2 SP = operand; + SP = SP - 1; +} +@endif + +################################################################ +# Constructors +################################################################ + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:ADC OP1 is (op=0xA9 | op=0xB9 | op=0xC9 | op=0xD9 | op=0xE9 | op=0xF9) ... & OP1 +{ + op1:1 = OP1; + + additionWithCarry(A, op1, A); +} +@endif + +@if defined(HCS08) || defined(HC08) +:ADC oprx16_8_SP is (op16=0x9ED9); oprx16_8_SP +{ + op1:1 = oprx16_8_SP; + + additionWithCarry(A, op1, A); +} +@endif + +@if defined(HCS08) || defined(HC08) +:ADC oprx8_8_SP is (op16=0x9EE9); oprx8_8_SP +{ + op1:1 = oprx8_8_SP; + + additionWithCarry(A, op1, A); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:ADD OP1 is (op=0xAB | op=0xBB | op=0xCB | op=0xDB | op=0xEB | op=0xFB) ... & OP1 +{ + op1:1 = OP1; + + result:1 = A + op1; + additionFlags(A, op1,result); + A = result; +} +@endif + +@if defined(HCS08) || defined(HC08) +:ADD oprx16_8_SP is (op16=0x9EDB); oprx16_8_SP +{ + op1:1 = oprx16_8_SP; + + result:1 = A + op1; + additionFlags(A, op1,result); + A = result; +} +@endif + +@if defined(HCS08) || defined(HC08) +:ADD oprx8_8_SP is (op16=0x9EEB); oprx8_8_SP +{ + op1:1 = oprx8_8_SP; + + result:1 = A + op1; + additionFlags(A, op1,result); + A = result; +} +@endif + +@if defined(HCS08) || defined(HC08) +:AIS iopr8is is op=0xA7; iopr8is +{ + SP = SP + sext(iopr8is); +} +@endif + +@if defined(HCS08) || defined(HC08) +:AIX iopr8is is op=0xAF; iopr8is +{ + HIX = HIX + sext(iopr8is); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:AND OP1 is (op=0xA4 | op=0xB4 | op=0xC4 | op=0xD4 | op=0xE4 | op=0xF4) ... & OP1 +{ + A = A & OP1; + V_equals_0(); + $(Z) = (A == 0); + $(N) = (A s< 0); +} +@endif + +@if defined(HCS08) || defined(HC08) +:AND oprx16_8_SP is (op16=0x9ED4); oprx16_8_SP +{ + A = A & oprx16_8_SP; + V_equals_0(); + $(Z) = (A == 0); + $(N) = (A s< 0); +} +@endif + +@if defined(HCS08) || defined(HC08) +:AND oprx8_8_SP is (op16=0x9EE4); oprx8_8_SP +{ + A = A & oprx8_8_SP; + V_equals_0(); + $(Z) = (A == 0); + $(N) = (A s< 0); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:ASLA is op=0x48 +{ + $(C) = A >> 7; + A = A << 1; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:ASLX is op=0x58 +{ + $(C) = X >> 7; + X = X << 1; + $(Z) = (X == 0); + $(N) = (X s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:ASL OP1 is (op=0x38 | op=0x68 | op=0x78) ... & OP1 +{ + tmp:1 = OP1; + $(C) = tmp >> 7; + tmp = tmp << 1; + OP1 = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:ASL oprx8_8_SP is (op16=0x9E68); oprx8_8_SP +{ + tmp:1 = oprx8_8_SP; + $(C) = tmp >> 7; + tmp = tmp << 1; + oprx8_8_SP = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:ASRA is op=0x47 +{ + $(C) = A & 1; + A = A s>> 1; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:ASRX is op=0x57 +{ + $(C) = X & 1; + X = X s>> 1; + $(Z) = (X == 0); + $(N) = (X s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:ASR OP1 is (op=0x37 | op=0x67 | op=0x77) ... & OP1 +{ + tmp:1 = OP1; + $(C) = tmp & 1; + tmp = tmp s>> 1; + OP1 = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:ASR oprx8_8_SP is (op16=0x9E67); oprx8_8_SP +{ + tmp:1 = oprx8_8_SP; + $(C) = tmp & 1; + tmp = tmp s>> 1; + oprx8_8_SP = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:BCC REL is op=0x24; REL +{ + if ($(C) == 0) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:BCLR nIndex, opr8a_8 is op4_7=1 & nIndex & NthBit & op0_0=1; opr8a_8 +{ + opr8a_8 = opr8a_8 & ~NthBit; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:BCS REL is op=0x25; REL +{ + if ($(C) == 1) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:BEQ REL is op=0x27; REL +{ + if ($(Z) == 1) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) +:BGE REL is op=0x90; REL +{ + if (($(N) ^ $(V)) == 1) goto REL; +} +@endif + +@if defined(HCS08) +:BGND is op=0x82 +{ + backgroundDebugMode(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:BGT REL is op=0x92; REL +{ + if (($(Z) | ($(N) ^ $(V))) == 0) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:BHCC REL is op=0x28; REL +{ + if ($(H) == 0) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:BHCS REL is op=0x29; REL +{ + if ($(H) == 1) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:BHI REL is op=0x22; REL +{ + if (($(C) | $(Z)) == 0) goto REL; +} +@endif + +#:BHS REL is op=0x24; REL See BCC + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:BIH REL is op=0x2F; REL +{ + tmp:1 = readIRQ(); + if (tmp == 1) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:BIL REL is op=0x2E; REL +{ + tmp:1 = readIRQ(); + if (tmp == 0) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:BIT OP1 is (op=0xA5 | op=0xB5 | op=0xC5 | op=0xD5 | op=0xE5 | op=0xF5) ... & OP1 +{ + result:1 = A & OP1; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:BIT oprx16_8_SP is (op16=0x9ED5); oprx16_8_SP +{ + result:1 = A & oprx16_8_SP; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:BIT oprx8_8_SP is (op16=0x9EE5); oprx8_8_SP +{ + result:1 = A & oprx8_8_SP; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:BLE REL is op=0x93; REL +{ + if ($(Z) | ($(N) ^ $(V))) goto REL; +} +@endif + +#:BLO REL is op=0x25; REL see BCS + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:BLS REL is op=0x23; REL +{ + if (($(C) | $(Z)) == 1) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) +:BLT REL is op=0x91; REL +{ + if (($(N) ^ $(V)) == 1) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:BMC REL is op=0x2C; REL +{ + if ($(I) == 0) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:BMI REL is op=0x2B; REL +{ + if ($(N) == 1) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:BMS REL is op=0x2D; REL +{ + if ($(I) == 1) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:BNE REL is op=0x26; REL +{ + if ($(Z) == 0) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:BPL REL is op=0x2A; REL +{ + if ($(N) == 0) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:BRA REL is op=0x20; REL +{ + goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:BRCLR nIndex, opr8a_8, REL is op4_7=0 & nIndex & NthBit & op0_0=1; opr8a_8; REL +{ + result:1 = opr8a_8 & NthBit; + $(C) = (result != 0); + if (result == 0) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +# branch never is a two-byte nop +:BRN REL is op=0x21; REL +{ +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:BRSET nIndex, opr8a_8, REL is op4_7=0 & nIndex & NthBit & op0_0=0; opr8a_8; REL +{ + result:1 = opr8a_8 & NthBit; + $(C) = (result != 0); + if (result != 0) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:BSET nIndex, opr8a_8 is op4_7=1 & nIndex & NthBit & op0_0=0; opr8a_8 +{ + opr8a_8 = opr8a_8 | NthBit; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:BSR REL is op=0xAD; REL +{ + tmp:2 = inst_next; + Push2( tmp ); + + call REL; +} +@endif + +@if defined(HCS08) || defined(HC08) +:CBEQ opr8a_8, REL is (op=0x31); opr8a_8; REL +{ + if (A == opr8a_8) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) +:CBEQA iopr8i, REL is op=0x41; iopr8i; REL +{ + if (A == iopr8i) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) +:CBEQX iopr8i, REL is op=0x51; iopr8i; REL +{ + if (X == iopr8i) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) +:CBEQ oprx8, X"+,", REL is (op=0x61) & X; oprx8; REL +{ + tmp:1 = *:1 (HIX + zext(oprx8)); + HIX = HIX + 1; + + if (A == tmp) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) +:CBEQ ","X"+,", REL is (op=0x71) & X; REL +{ + tmp:1 = *:1 (HIX); + HIX = HIX + 1; + + if (A == tmp) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) +:CBEQ oprx8_8_SP, REL is (op16=0x9E61); oprx8_8_SP; REL +{ + if (A == oprx8_8_SP) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:CLC is op=0x98 +{ + $(C) = 0; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:CLI is op=0x9A +{ + $(I) = 0; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:CLRA is op=0x4F +{ + A = 0; + $(Z) = 1; + $(N) = 0; + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:CLRX is op=0x5F +{ + X = 0; + $(Z) = 1; + $(N) = 0; + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:CLRH is op=0x8C +{ + HI = 0; + $(Z) = 1; + $(N) = 0; + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:CLR OP1 is (op=0x3F | op=0x6F | op=0x7F) ... & OP1 +{ + OP1 = 0; + $(Z) = 1; + $(N) = 0; + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:CLR oprx8_8_SP is (op16=0x9E6F); oprx8_8_SP +{ + oprx8_8_SP = 0; + $(Z) = 1; + $(N) = 0; + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:CMP OP1 is (op=0xA1 | op=0xB1 | op=0xC1 | op=0xD1 | op=0xE1 | op=0xF1) ... & OP1 +{ + op1:1 = OP1; + tmp:1 = A - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > A); + V_CMP_flag(op1, tmp); +} +@endif + +@if defined(HCS08) || defined(HC08) +:CMP oprx16_8_SP is (op16=0x9ED1); oprx16_8_SP +{ + op1:1 = oprx16_8_SP; + tmp:1 = A - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > A); + V_CMP_flag(op1, tmp); +} +@endif + +@if defined(HCS08) || defined(HC08) +:CMP oprx8_8_SP is (op16=0x9EE1); oprx8_8_SP +{ + op1:1 = oprx8_8_SP; + tmp:1 = A - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > A); + V_CMP_flag(op1, tmp); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:COMA is op=0x43 +{ + A = ~A; + $(Z) = (A == 0); + $(N) = (A s< 0); + $(C) = 1; + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:COMX is op=0x53 +{ + X = ~X; + $(Z) = (X == 0); + $(N) = (X s< 0); + $(C) = 1; + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:COM OP1 is (op=0x33 | op=0x63 | op=0x73) ... & OP1 +{ + tmp:1 = ~OP1; + OP1 = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = 1; + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:COM oprx8_8_SP is (op16=0x9E63); oprx8_8_SP +{ + tmp:1 = ~oprx8_8_SP; + oprx8_8_SP = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = 1; + V_equals_0(); +} +@endif + +@if defined(HCS08) +:CPHX opr16a_16 is (op=0x3E); opr16a_16 +{ + op1:2 = opr16a_16; + tmp:2 = HIX - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > HIX); + V_CPHX_flag(op1, tmp); +} +@endif + +@if defined(HCS08) || defined(HC08) +:CPHX iopr16i is (op=0x65); iopr16i +{ + op1:2 = iopr16i; + tmp:2 = HIX - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > HIX); + V_CPHX_flag(op1, tmp); +} +@endif + +@if defined(HCS08) || defined(HC08) +:CPHX opr8a_16 is (op=0x75); opr8a_16 +{ + op1:2 = *:2 opr8a_16; + tmp:2 = HIX - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > HIX); + V_CPHX_flag(op1, tmp); +} +@endif + +@if defined(HCS08) +:CPHX oprx8_16_SP is (op16=0x9EF3); oprx8_16_SP +{ + op1:2 = oprx8_16_SP; + tmp:2 = HIX - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > HIX); + V_CPHX_flag(op1, tmp); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:CPX OP1 is (op=0xA3 | op=0xB3 | op=0xC3 | op=0xD3 | op=0xE3 | op=0xF3) ... & OP1 +{ + op1:1 = OP1; + tmp:1 = X - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > X); + V_CPX_flag(op1, tmp); +} +@endif + +@if defined(HCS08) || defined(HC08) +:CPX oprx16_8_SP is (op16=0x9ED3); oprx16_8_SP +{ + op1:1 = oprx16_8_SP; + tmp:1 = X - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > X); + V_CPX_flag(op1, tmp); +} +@endif + +@if defined(HCS08) || defined(HC08) +:CPX oprx8_8_SP is (op16=0x9EE3); oprx8_8_SP +{ + op1:1 = oprx8_8_SP; + tmp:1 = X - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > X); + V_CPX_flag(op1, tmp); +} +@endif + +@if defined(HCS08) || defined(HC08) +:DAA is op=0x72 +{ + A = decimalAdjustAccumulator(A, $(C), $(H)); + $(C) = decimalAdjustCarry(A, $(C), $(H)); + $(Z) = (A == 0); + $(N) = (A s< 0); + # V is undefined +} +@endif + +@if defined(HCS08) || defined(HC08) +:DBNZA REL is op=0x4B; REL +{ + A = A - 1; + if (A != 0) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) +:DBNZX REL is op=0x5B; REL +{ + X = X - 1; + if (X != 0) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) +:DBNZ OP1, REL is (op=0x3B | op=0x6B | op=0x7B) ... & OP1; REL +{ + OP1 = OP1 - 1; + if (OP1 != 0) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) +:DBNZ oprx8_8_SP, REL is (op16=0x9E6B); oprx8_8_SP; REL +{ + tmp:1 = oprx8_8_SP - 1; + oprx8_8_SP = tmp; + if (tmp != 0) goto REL; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:DECA is op=0x4A +{ + tmp:1 = A; + A = tmp - 1; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_DEC_flag(tmp, A); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:DECX is op=0x5A +{ + tmp:1 = X; + X = tmp - 1; + $(Z) = (X == 0); + $(N) = (X s< 0); + V_DEC_flag(tmp, X); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:DEC OP1 is (op=0x3A | op=0x6A | op=0x7A) ... & OP1 +{ + tmp:1 = OP1; + result:1 = tmp - 1; + OP1 = result; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_DEC_flag(tmp, result); +} +@endif + +@if defined(HCS08) || defined(HC08) +:DEC oprx8_8_SP is (op16=0x9E6A); oprx8_8_SP +{ + tmp:1 = oprx8_8_SP; + result:1 = tmp - 1; + oprx8_8_SP = result; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_DEC_flag(tmp, result); +} +@endif + +@if defined(HCS08) || defined(HC08) +:DIV is op=0x52 +{ + tmp:2 = (zext(HI) << 8) | (zext(A)); + resultQ:2 = tmp / zext(X); + A = resultQ:1; + resultR:2 = tmp % zext(X); + HI = resultR:1; + $(Z) = (A == 0); + $(C) = (X == 0) | (resultQ > 0x00FF); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:EOR OP1 is (op=0xA8 | op=0xB8 | op=0xC8 | op=0xD8 | op=0xE8 | op=0xF8) ... & OP1 +{ + op1:1 = OP1; + A = A ^ op1; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:EOR oprx16_8_SP is (op16=0x9ED8); oprx16_8_SP +{ + op1:1 = oprx16_8_SP; + A = A ^ op1; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:EOR oprx8_8_SP is (op16=0x9EE8); oprx8_8_SP +{ + op1:1 = oprx8_8_SP; + A = A ^ op1; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:INCA is op=0x4C +{ + tmp:1 = A; + A = tmp + 1; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_INC_flag(tmp, A); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:INCX is op=0x5C +{ + tmp:1 = X; + X = tmp + 1; + $(Z) = (X == 0); + $(N) = (X s< 0); + V_INC_flag(tmp, X); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:INC OP1 is (op=0x3C | op=0x6C | op=0x7C) ... & OP1 +{ + tmp:1 = OP1; + result:1 = tmp + 1; + OP1 = result; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_INC_flag(tmp, result); +} +@endif + +@if defined(HCS08) || defined(HC08) +:INC oprx8_8_SP is (op16=0x9E6C); oprx8_8_SP +{ + tmp:1 = oprx8_8_SP; + result:1 = tmp + 1; + oprx8_8_SP = result; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_INC_flag(tmp, result); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:JMP ADDR is (op=0xBC | op=0xCC) ... & ADDR +{ + goto ADDR; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:JMP ADDRI is (op=0xDC | op=0xEC | op=0xFC) ... & ADDRI +{ + goto [ADDRI]; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:JSR ADDR is (op=0xBD | op=0xCD) ... & ADDR +{ + tmp:2 = inst_next; + Push2( tmp ); + + call ADDR; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:JSR ADDRI is (op=0xDD | op=0xED | op=0xFD) ... & ADDRI +{ + tmp:2 = inst_next; + Push2( tmp ); + + call [ADDRI]; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:LDA OP1 is (op=0xA6 | op=0xB6 | op=0xC6 | op=0xD6 | op=0xE6 | op=0xF6) ... & OP1 +{ + A = OP1; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:LDA oprx16_8_SP is (op16=0x9ED6); oprx16_8_SP +{ + A = oprx16_8_SP; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:LDA oprx8_8_SP is (op16=0x9EE6); oprx8_8_SP +{ + A = oprx8_8_SP; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:LDHX iopr16i is (op=0x45); iopr16i +{ + HIX = iopr16i; + $(Z) = (HIX == 0); + $(N) = (HI s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:LDHX opr8a_16 is (op=0x55); opr8a_16 +{ + HIX = opr8a_16; + $(Z) = (HIX == 0); + $(N) = (HI s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) +:LDHX opr16a_16 is (op=0x32); opr16a_16 +{ + HIX = opr16a_16; + $(Z) = (HIX == 0); + $(N) = (HI s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) +:LDHX ","X is (op16=0x9EAE) & X +{ + HIX = *:2 (HIX); + $(Z) = (HIX == 0); + $(N) = (HI s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) +:LDHX oprx16_16_X is (op16=0x9EBE); oprx16_16_X +{ + HIX = oprx16_16_X; + $(Z) = (HIX == 0); + $(N) = (HI s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) +:LDHX oprx8_16_X is (op16=0x9ECE); oprx8_16_X +{ + HIX = oprx8_16_X; + $(Z) = (HIX == 0); + $(N) = (HI s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) +:LDHX oprx8_16_SP is (op16=0x9EFE); oprx8_16_SP +{ + HIX = oprx8_16_SP; + $(Z) = (HIX == 0); + $(N) = (HI s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:LDX OP1 is (op=0xAE | op=0xBE | op=0xCE | op=0xDE | op=0xEE | op=0xFE) ... & OP1 +{ + X = OP1; + $(Z) = (X == 0); + $(N) = (X s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:LDX oprx16_8_SP is (op16=0x9EDE); oprx16_8_SP +{ + X = oprx16_8_SP; + $(Z) = (X == 0); + $(N) = (X s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:LDX oprx8_8_SP is (op16=0x9EEE); oprx8_8_SP +{ + X = oprx8_8_SP; + $(Z) = (X == 0); + $(N) = (X s< 0); + V_equals_0(); +} +@endif + +## Logical Shift left is same as arithmetic shift left +#:LSLA is op=0x48 +#:LSLX is op=0x58 +#:LSL OP1 is (op=0x38 | op=0x68 | op=0x78) ... & OP1 + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:LSRA is op=0x44 +{ + $(C) = (A & 1); + A = (A >> 1); + $(Z) = (A == 0); + $(N) = 0; + V_equals_C(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:LSRX is op=0x54 +{ + $(C) = (X & 1); + X = (X >> 1); + $(Z) = (X == 0); + $(N) = 0; + V_equals_C(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:LSR OP1 is (op=0x34 | op=0x64 | op=0x74) ... & OP1 +{ + tmp:1 = OP1; + $(C) = tmp & 1; + tmp = tmp >> 1; + OP1 = tmp; + $(Z) = (tmp == 0); + $(N) = 0; + V_equals_C(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:LSR oprx8_8_SP is (op16=0x9E64); oprx8_8_SP +{ + tmp:1 = oprx8_8_SP; + $(C) = tmp & 1; + tmp = tmp >> 1; + oprx8_8_SP = tmp; + $(Z) = (tmp == 0); + $(N) = 0; + V_equals_C(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:MOV opr8a_8, op2_opr8a is (op=0x4E); opr8a_8; op2_opr8a +{ + result:1 = opr8a_8; + op2_opr8a = result; + V_equals_0(); + $(N) = (result s< 0); + $(Z) = (result == 0); +} +@endif + +@if defined(HCS08) || defined(HC08) +:MOV opr8a_8, X"+" is (op=0x5E); opr8a_8 & X +{ + result:1 = opr8a_8; + *:1 HIX = result; + HIX = HIX + 1; + V_equals_0(); + $(N) = (result s< 0); + $(Z) = (result == 0); +} +@endif + +@if defined(HCS08) || defined(HC08) +:MOV iopr8i, op2_opr8a is (op=0x6E); iopr8i; op2_opr8a +{ + result:1 = iopr8i; + op2_opr8a = result; + V_equals_0(); + $(N) = (result s< 0); + $(Z) = (result == 0); +} +@endif + +@if defined(HCS08) || defined(HC08) +:MOV ","X"+," op2_opr8a is (op=0x7E) & X; op2_opr8a +{ + result:1 = *:1 HIX; + op2_opr8a = result; + HIX = HIX + 1; + V_equals_0(); + $(N) = (result s< 0); + $(Z) = (result == 0); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:MUL is op=0x42 +{ + op1:2 = zext(A); + op2:2 = zext(X); + result:2 = op1 * op2; + A = result:1; + X = result(1); + $(H) = 0; + $(C) = 0; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:NEGA is op=0x40 +{ + tmp:1 = A; + A = -tmp; + $(C) = (A != 0); + $(Z) = (A == 0); + $(N) = (A s< 0); + V_NEG_flag(tmp, A); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:NEGX is op=0x50 +{ + tmp:1 = X; + X = -tmp; + $(C) = (X != 0); + $(Z) = (X == 0); + $(N) = (X s< 0); + V_NEG_flag(tmp, X); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:NEG OP1 is (op=0x30 | op=0x60 | op=0x70) ... & OP1 +{ + tmp:1 = OP1; + result:1 = -tmp; + OP1 = result; + $(C) = (result != 0); + $(Z) = (result == 0); + $(N) = (result s< 0); + V_NEG_flag(tmp, result); +} +@endif + +@if defined(HCS08) || defined(HC08) +:NEG oprx8_8_SP is (op16=0x9E60); oprx8_8_SP +{ + tmp:1 = oprx8_8_SP; + result:1 = -tmp; + oprx8_8_SP = result; + $(C) = (result != 0); + $(Z) = (result == 0); + $(N) = (result s< 0); + V_NEG_flag(tmp, result); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:NOP is op = 0x9D +{ +} +@endif + +@if defined(HCS08) || defined(HC08) +:NSA is op = 0x62 +{ + A = (A >> 4) | (A << 4); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:ORA OP1 is (op=0xAA | op=0xBA | op=0xCA | op=0xDA | op=0xEA | op=0xFA) ... & OP1 +{ + A = A | OP1; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:ORA oprx16_8_SP is (op16=0x9EDA); oprx16_8_SP +{ + A = A | oprx16_8_SP; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:ORA oprx8_8_SP is (op16=0x9EEA); oprx8_8_SP +{ + A = A | oprx8_8_SP; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:PSHA is op = 0x87 +{ + Push1( A ); +} +@endif + +@if defined(HCS08) || defined(HC08) +:PSHH is op = 0x8B +{ + Push1( HI ); +} +@endif + +@if defined(HCS08) || defined(HC08) +:PSHX is op = 0x89 +{ + Push1( X ); +} +@endif + +@if defined(HCS08) || defined(HC08) +:PULA is op = 0x86 +{ + Pull1( A ); +} +@endif + +@if defined(HCS08) || defined(HC08) +:PULH is op = 0x8A +{ + Pull1( HI ); +} +@endif + +@if defined(HCS08) || defined(HC08) +:PULX is op = 0x88 +{ + Pull1( X ); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:ROLA is op=0x49 +{ + tmpC:1 = $(C) ; + $(C) = A >> 7; + A = (A << 1) | tmpC; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:ROLX is op=0x59 +{ + tmpC:1 = $(C); + $(C) = X >> 7; + X = (X << 1) | tmpC; + $(Z) = (X == 0); + $(N) = (X s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:ROL OP1 is (op=0x39 | op=0x69 | op=0x79) ... & OP1 +{ + tmpC:1 = $(C); + op1:1 = OP1; + $(C) = op1 >> 7; + result:1 = (op1 << 1) | tmpC; + OP1 = result; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:ROL oprx8_8_SP is (op16=0x9E69); oprx8_8_SP +{ + tmpC:1 = $(C); + op1:1 = oprx8_8_SP; + $(C) = op1 >> 7; + result:1 = (op1 << 1) | tmpC; + oprx8_8_SP = result; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:RORA is op=0x46 +{ + tmpC:1 = $(C) << 7; + $(C) = A & 1; + A = (A >> 1) | tmpC; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:RORX is op=0x56 +{ + tmpC:1 = $(C) << 7; + $(C) = X & 1; + X = (X >> 1) | tmpC; + $(Z) = (X == 0); + $(N) = (X s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:ROR OP1 is (op=0x36 | op=0x66 | op=0x76) ... & OP1 +{ + tmpC:1 = $(C) << 7; + tmp:1 = OP1; + $(C) = tmp & 1; + tmp = (tmp >> 1) | tmpC; + OP1 = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:ROR oprx8_8_SP is (op16=0x9E66); oprx8_8_SP +{ + tmpC:1 = $(C) << 7; + tmp:1 = oprx8_8_SP; + $(C) = tmp & 1; + tmp = (tmp >> 1) | tmpC; + oprx8_8_SP = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:RSP is op = 0x9C +{ + SPL = 0xff; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:RTI is op = 0x80 +{ + Pull1( CCR ); + + Pull1( A ); + + Pull1( X ); + + tmp:2 = 0; + Pull2( tmp ); + + return [tmp]; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:RTS is op = 0x81 +{ + tmp:2 = 0; + Pull2( tmp ); + + return [tmp]; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:SBC OP1 is (op=0xA2 | op=0xB2 | op=0xC2 | op=0xD2 | op=0xE2 | op=0xF2) ... & OP1 +{ + op1:1 = OP1; + + subtractWithCarry(A, op1, A); +} +@endif + +@if defined(HCS08) || defined(HC08) +:SBC oprx16_8_SP is (op16=0x9ED2); oprx16_8_SP +{ + op1:1 = oprx16_8_SP; + + subtractWithCarry(A, op1, A); +} +@endif + +@if defined(HCS08) || defined(HC08) +:SBC oprx8_8_SP is (op16=0x9EE2); oprx8_8_SP +{ + op1:1 = oprx8_8_SP; + + subtractWithCarry(A, op1, A); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:SEC is op = 0x99 +{ + $(C) = 1; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:SEI is op = 0x9B +{ + $(I) = 1; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:STA OP1 is (op=0xB7 | op=0xC7 | op=0xD7 | op=0xE7 | op=0xF7) ... & OP1 +{ + OP1 = A; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:STA oprx16_8_SP is (op16=0x9ED7); oprx16_8_SP +{ + oprx16_8_SP = A; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:STA oprx8_8_SP is (op16=0x9EE7); oprx8_8_SP +{ + oprx8_8_SP = A; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:STHX opr8a_16 is (op=0x35); opr8a_16 +{ + opr8a_16 = HIX; + $(Z) = (HIX == 0); + $(N) = (HI s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) +:STHX opr16a_16 is (op=0x96); opr16a_16 +{ + opr16a_16 = HIX; + $(Z) = (HIX == 0); + $(N) = (HI s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) +:STHX oprx8_16_SP is (op16=0x9EFF); oprx8_16_SP +{ + oprx8_16_SP = HIX; + $(Z) = (HIX == 0); + $(N) = (HI s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:STOP is op=0x8E +{ + $(I) = 0; + stop(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:STX OP1 is (op=0xBF | op=0xCF | op=0xDF | op=0xEF | op=0xFF) ... & OP1 +{ + OP1 = X; + $(Z) = (X == 0); + $(N) = (X s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:STX oprx16_8_SP is (op16=0x9EDF); oprx16_8_SP +{ + oprx16_8_SP = X; + $(Z) = (X == 0); + $(N) = (X s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:STX oprx8_8_SP is (op16=0x9EEF); oprx8_8_SP +{ + oprx8_8_SP = X; + $(Z) = (X == 0); + $(N) = (X s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:SUB OP1 is (op=0xA0 | op=0xB0 | op=0xC0 | op=0xD0 | op=0xE0 | op=0xF0) ... & OP1 +{ + op1:1 = OP1; + + result:1 = A - op1; + subtractionFlags(A, op1,result); + A = result; +} +@endif + +@if defined(HCS08) || defined(HC08) +:SUB oprx16_8_SP is (op16=0x9ED0); oprx16_8_SP +{ + op1:1 = oprx16_8_SP; + + result:1 = A - op1; + subtractionFlags(A, op1,result); + A = result; +} +@endif + +@if defined(HCS08) || defined(HC08) +:SUB oprx8_8_SP is (op16=0x9EE0); oprx8_8_SP +{ + op1:1 = oprx8_8_SP; + + result:1 = A - op1; + subtractionFlags(A, op1,result); + A = result; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:SWI is op=0x83 +{ + tmp:2 = inst_next; + Push2( tmp ); + + Push1( X ); + + Push1( A ); + + Push1( CCR ); + + $(I) = 1; + + addr:2 = $(VECTOR_SWI); + call [addr]; +} +@endif + +@if defined(HCS08) || defined(HC08) +:TAP is op=0x84 +{ + CCR = A; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:TAX is op=0x97 +{ + X = A; +} +@endif + +@if defined(HCS08) || defined(HC08) +:TPA is op=0x85 +{ + A = CCR; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:TSTA is op=0x4D +{ + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:TSTX is op=0x5D +{ + $(Z) = (X == 0); + $(N) = (X s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:TST OP1 is (op=0x3D | op=0x6D | op=0x7D) ... & OP1 +{ + op1:1 = OP1; + $(Z) = (op1 == 0); + $(N) = (op1 s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:TST oprx8_8_SP is (op16=0x9E6D); oprx8_8_SP +{ + op1:1 = oprx8_8_SP; + $(Z) = (op1 == 0); + $(N) = (op1 s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS08) || defined(HC08) +:TSX is op=0x95 +{ + HIX = SP + 1; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:TXA is op=0x9F +{ + A = X; +} +@endif + +@if defined(HCS08) || defined(HC08) +:TXS is op=0x94 +{ + SP = HIX - 1; +} +@endif + +@if defined(HCS08) || defined(HC08) || defined(HC05) +:WAIT is op=0x8f +{ + $(I) = 0; + wait(); +} +@endif + diff --git a/python/icicle/Ghidra/Processors/HCS12/data/languages/HC12.cspec b/python/icicle/Ghidra/Processors/HCS12/data/languages/HC12.cspec new file mode 100644 index 0000000..36e470b --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS12/data/languages/HC12.cspec @@ -0,0 +1,58 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/HCS12/data/languages/HC12.pspec b/python/icicle/Ghidra/Processors/HCS12/data/languages/HC12.pspec new file mode 100644 index 0000000..8d1b4e5 --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS12/data/languages/HC12.pspec @@ -0,0 +1,75 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/HCS12/data/languages/HC12.slaspec b/python/icicle/Ghidra/Processors/HCS12/data/languages/HC12.slaspec new file mode 100644 index 0000000..74c45c7 --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS12/data/languages/HC12.slaspec @@ -0,0 +1,9 @@ +# sleigh specification file for Freescale HC12 (68HC12) + +@define HC12 "1" + +@define SIZE "2" + +@define MAXFLASHPage "0xFF" + +@include "HCS_HC12.sinc" \ No newline at end of file diff --git a/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS12.cspec b/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS12.cspec new file mode 100644 index 0000000..4bea806 --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS12.cspec @@ -0,0 +1,102 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS12.ldefs b/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS12.ldefs new file mode 100644 index 0000000..7101719 --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS12.ldefs @@ -0,0 +1,59 @@ + + + + + HC12 Microcontroller Family + + + + + HCS12 Microcontroller Family + + + + + HCS12X Microcontroller Family + + + + + + + HCS12X Microcontroller Family + + + + diff --git a/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS12.opinion b/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS12.opinion new file mode 100644 index 0000000..a35d7be --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS12.opinion @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS12.pspec b/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS12.pspec new file mode 100644 index 0000000..54a7d8e --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS12.pspec @@ -0,0 +1,94 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS12.slaspec b/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS12.slaspec new file mode 100644 index 0000000..049dc69 --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS12.slaspec @@ -0,0 +1,9 @@ +# sleigh specification file for Freescale HCS12 (68HCS12) + +@define HCS12 "1" + +@define SIZE "3" + +@define MAXFLASHPage "0xFF" + +@include "HCS_HC12.sinc" \ No newline at end of file diff --git a/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS12X.cspec b/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS12X.cspec new file mode 100644 index 0000000..60c0d0f --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS12X.cspec @@ -0,0 +1,156 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + R7 = SP; + + + + diff --git a/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS12X.pspec b/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS12X.pspec new file mode 100644 index 0000000..830e243 --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS12X.pspec @@ -0,0 +1,96 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS12X.slaspec b/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS12X.slaspec new file mode 100644 index 0000000..2a97979 --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS12X.slaspec @@ -0,0 +1,10 @@ +# sleigh specification file for Freescale HCS12 (68HCS12) + +@define HCS12 "1" +@define HCS12X "1" +@define SIZE "3" + +@define MAXFLASHPage "0xFF" + +@include "HCS_HC12.sinc" +@include "XGATE.sinc" \ No newline at end of file diff --git a/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS_HC12.sinc b/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS_HC12.sinc new file mode 100644 index 0000000..df02f01 --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS12/data/languages/HCS_HC12.sinc @@ -0,0 +1,5969 @@ +# common include file for HCS12, and HC12 constructors + +define endian=big; +define alignment=1; + +define space RAM type=ram_space size=$(SIZE) default; +define space register type=register_space size=2; + +@define VECTOR_SWI "0xFFF6" +@define VECTOR_TRAP "0xFFF8" + +################################################################ +# Registers +################################################################ + +define register offset=0x00 size=1 [ A B ]; +define register offset=0x00 size=2 [ D ]; + +# IX also referred to as X or x; but must be distinct from X bit in CCR +# IY also referred to as Y or y; made IY to be consistent with IX +define register offset=0x10 size=2 [ IX IY TMP2 TMP3 TMP1 ]; +define register offset=0x10 size=1 [ IXH IXL IYH IYL TMP2H TMP2L TMP3H TMP3L TMP1H TMP1L ]; + +#define register offset=0x20 size=3 [ _ PCE _ SPE ]; +define register offset=0x20 size=3 [ _ PCE ]; +define register offset=0x20 size=2 [ _ _ PC _ _ SP ]; +define register offset=0x20 size=1 [ _ _ _ _ PCH PCL _ _ _ _ SPH SPL ]; + +define register offset=0x30 size=2 [ CCRW ]; +define register offset=0x30 size=1 [ CCRH ]; + +define register offset=0x31 size=1 [ CCR ]; + +define register offset = 0x32 size=3 [physPage]; + +define RAM offset=0x11 size=1 [DIRECT]; + +@ifdef HCS12 +define RAM offset=0x30 size=1 [PPAGE]; +@endif +@ifdef HCS12X +define RAM offset=0x10 size=1 [GPAGE]; +define RAM offset=0x16 size=1 [RPAGE]; +define RAM offset=0x17 size=1 [EPAGE]; +@endif + + +# Define context bits +# WARNING: when adjusting context keep compiler packing in mind +# and make sure fields do not span a 32-bit boundary before or +# after context packing +define register offset=0x40 size=4 contextreg; +define context contextreg + Prefix18 = (0,0) # 1 if 0x18 is the first byte + PrefixHCS12X = (0,0) # 1 if first byte is 0x18 so that HCS12X to use GPAGE for memory access + UseGPAGE = (1,1) # 1 if should use GPAGE concatenated to lower 16-bit EA + XGATE = (2,2) # 1 if in xgate instruction decode mode +; + + +# individual status bits within CCRH + +@define IPL_2 "CCRH[2,1]" +@define IPL_1 "CCRH[1,1]" +@define IPL_0 "CCRH[0,1]" + +@define IPL "CCRH[0,3]" # entire IPL + +# individual status bits within CCR + +@define S "CCR[7,1]" # STOP Enable +@define X "CCR[6,1]" # Non-maskable interrupt control bit +@define H "CCR[5,1]" # Half Carry Flag +@define I "CCR[4,1]" # Maskable interrupt control bit +@define N "CCR[3,1]" # Negative Flag +@define Z "CCR[2,1]" # Zero Flag +@define V "CCR[1,1]" # Two's complement overflow Flag +@define C "CCR[0,1]" # Carry/Borrow Flag + +################################################################ +# Tokens +################################################################ + +define token opbyte8 (8) + op8 = (0,7) + op7_4 = (4,7) + op6_4 = (4,6) + nIndex = (1,3) + op0_0 = (0,0) + trapnum = (0,7) +; + +define token xb8 (8) + rr7_6 = (6,7) + rr7_6a = (6,7) + xb5_5 = (5,5) + nn4_0 = (0,4) signed + + xb7_5 = (5,7) + rr4_3 = (3,4) + xb2_2 = (2,2) + xb2_1 = (1,2) # actually needed this instead of xb2_2 + z1_1 = (1,1) + s0_0 = (0,0) + ss0_0 = (0,0) signed + + xb2_0 = (0,2) + + p4_4 = (4,4) + decrement3_3 = (3,3) + nn3_0 = (0,3) + + aa1_0 = (0,1) + aa0_0 = (0,0) # actually needed this instead of aa1_0 +; + +define token eb8 (8) + notUsed7_7 = (7,7) + abcdxys6_4 = (4,6) + abc5_4 = (4,5) + dxys2_0 = (0,2) + abcdxys2_0 = (0,2) + columns7_4 = (4,7) + rows2_0 = (0,2) + rows3_0 = (0,3) + bytes_ABCl_6_4 = (4,6) + bytes_ABClT3lBXlYlSl_6_4 = (4,6) + bytes_ABChT3hBXhYhSh_6_4 = (4,6) + words_CT3DXYS_6_4 = (4,6) + words_T3DXYS_6_4 = (4,6) + bytes_ABCl_2_0 = (0,2) + bytes_T3lDlXlYlSl_6_4 = (4,6) + words_T2DXYS_2_0 = (0,2) + bytes_T2h_XhYhSh_2_0 = (0,2) + bytes_T2l_XlYlSl_2_0 = (0,2) + bytes_T3l_XlYlSl_6_4 = (4,6) + bytes_T3h_XhYhSh_6_4 = (4,6) + words_T3_XYS_6_4 = (4,6) + bytes_T2hDhXhYhSh_2_0 = (0,2) + bytes_T2lDlXlYlSl_2_0 = (0,2) +; + +define token opbyte16 (16) + op16 = (0,15) + op15_13 = (13,15) + sign12_12 = (12,12) signed + not_used11 = (11,11) + size10_10 = (10,10) + byte9_8 = (8,9) + word9_8 = (8,9) + rr7_0 = (0,7) +; + +define token data8 (8) + imm8 = (0,7) + simm8 = (0,7) signed + rel = (0,7) signed +; + +define token data16 (16) + imm16 = (0,15) + imm16p = (12,15) + imm16e = (8,15) + imm16ev = (0,9) + imm16rv = (0,11) + imm16pv = (0,13) + simm16 = (0,15) signed +; + +attach variables [ rr7_6 rr4_3 ] [ IX IY SP PC ]; +attach variables [ rr7_6a ] [ IX IY SP _ ]; # PC not valid choice in this case + +# TODO would be great if this worked +# attach names [ rr7_6 rr4_3 ] [ "X" "Y" "SP" "PC" ]; + + +# TODO do the negative values work? +attach values [ nn3_0 ] [ 1 2 3 4 5 6 7 8 -8 -7 -6 -5 -4 -3 -2 -1 ]; + +attach variables [ aa0_0 ] [ A B ]; + +attach variables [ byte9_8 ] [ A B _ _ ]; + +attach variables [ word9_8 ] [ D IX IY SP ]; + +attach variables [ abc5_4 ] [ A B CCR _ ]; + +attach variables [ dxys2_0 ] [ _ _ _ TMP2 D IX IY SP ]; + +attach variables [ bytes_ABCl_2_0 ] [ A B CCR _ _ _ _ _ ]; + +attach variables [ bytes_ABClT3lBXlYlSl_6_4 ] [ A B CCR TMP3L B IXL IYL SPL ]; + +attach variables [ bytes_ABChT3hBXhYhSh_6_4 ] [ A B CCRH TMP3H B IXH IYH SPH ]; + +attach variables [ words_T2DXYS_2_0 ] [ _ _ _ TMP2 D IX IY SP ]; + +attach variables [ bytes_T3lDlXlYlSl_6_4 ] [ _ _ _ TMP3L B IXL IYL SPL ]; + +attach variables [ words_T3DXYS_6_4 ] [ _ _ _ TMP3 D IX IY SP ]; + +attach variables [ words_CT3DXYS_6_4 ] [ _ _ CCRW TMP3 D IX IY SP ]; + +attach variables [ bytes_T2l_XlYlSl_2_0 ] [ _ _ _ TMP2L _ IXL IYL SPL ]; + +attach variables [ bytes_T2h_XhYhSh_2_0 ] [ _ _ _ TMP2H _ IXH IYH SPH ]; + +attach variables [ bytes_T3l_XlYlSl_6_4 ] [ _ _ _ TMP3L _ IXL IYL SPL ]; + +attach variables [ bytes_T3h_XhYhSh_6_4 ] [ _ _ _ TMP3H _ IXH IYH SPH ]; + +attach variables [ words_T3_XYS_6_4 ] [ _ _ _ TMP3 _ IX IY SP ]; + +attach variables [ bytes_ABCl_6_4 ] [ A B CCR _ _ _ _ _ ]; + +attach variables [ bytes_T2hDhXhYhSh_2_0 ] [ _ _ _ TMP2H A IXH IYH SPH ]; + +attach variables [ bytes_T2lDlXlYlSl_2_0 ] [ _ _ _ TMP2L B IXL IYL SPL ]; + +################################################################ +# Pseudo Instructions +################################################################ +define pcodeop segment; # Define special pcodeop that calculates the RAM address + +# given the segment selector and offset as input + +define pcodeop readIRQ; +define pcodeop stop; +define pcodeop WaitForInterrupt; + +define pcodeop decimalAdjustAccumulator; +define pcodeop decimalAdjustCarry; +define pcodeop EMACS; +define pcodeop ETBL; +define pcodeop ETBL_Cflag; +define pcodeop GradeOfMembership; +define pcodeop TableLookupAndInterpolate; +define pcodeop TableLookupAndInterpolateRoundable; +define pcodeop WeightedAverageSOPHigh; +define pcodeop WeightedAverageSOPLow; +define pcodeop WeightedAverageSOW; +define pcodeop WeightedAverageResume; +define pcodeop MinMaxRuleEvaluation; +define pcodeop MinMaxRuleEvaluationCorrect; +define pcodeop MinMaxRuleEvaluationWeighted; +define pcodeop MinMaxRuleEvaluationWeightedCorrect; + +define pcodeop backgroundDebugMode; + +@if defined(HCS12X) +macro setHCSphysPage(addr) { + local a3:3 = zext(addr); + + local isReg:1 = (a3 & 0xfC00) == 0x0; + local isEpage:1 = (a3 & 0xfc00) ==0x800; + local isEpage_FF:1 = (a3 & 0xfc00) ==0xC00; + local isRpage:1 = (a3 & 0xf000) ==0x1000; + local isRpage_FE:1 = (a3 & 0xf000) ==0x2000; + local isRpage_FF:1 = (a3 & 0xf000) ==0x3000; + local isPpage_FD:1 = (a3 & 0xc000) ==0x4000; + local isPpage:1 = (a3 & 0xc000) ==0x8000; + local isPpage_FF:1 = (a3 & 0xc000) ==0xC000; + + physPage = (zext(isReg) * 0x0) + + (zext(isEpage) * (0x100000 | ((zext(EPAGE) << 10) ^ 0x800))) + + (zext(isEpage_FF) * ((0x4FF << 10) ^ 0xC00)) + + (zext(isRpage) * (((zext(RPAGE) << 12) ^ 0x1000))) + + (zext(isRpage_FE) * (((0xFE << 12) ^ 0x2000))) + + (zext(isRpage_FF) * (((0xFF << 12) ^ 0x3000))) + + (zext(isPpage_FD) * (0x400000 | ((0x3F4000) ^ 0x4000))) + + (zext(isPpage) * (0x400000 | ((zext(PPAGE) << 14 ) ^ 0x8000))) + + (zext(isPpage_FF) * (0x400000 | ((0x3FC000) ^ 0xC000))) ; +} +@elif defined(HCS12) && SIZE=="3" +macro setHCSphysPage(addr) { + local a3:3 = zext(addr); + + local isPpage_3D:1 = (a3 & 0xc000) ==0x0000; + local isPpage_3E:1 = (a3 & 0xc000) ==0x4000; + local isPpage:1 = (a3 & 0xc000) ==0x8000; + local isPpage_3F:1 = (a3 & 0xc000) ==0xC000; + +# physPage = (zext(isPpage) * (0x000000 | ((zext(PPAGE) << 14 ) ^ 0x8000))); + + physPage = (zext(isPpage_3D) * (0x000000 | ((0xF4000) ^ 0x0000))) + + (zext(isPpage_3E) * (0x000000 | ((0xF8000) ^ 0x4000))) + + (zext(isPpage) * (0x000000 | ((zext(PPAGE) << 14 ) ^ 0x8000))) + + (zext(isPpage_3F) * (0x000000 | ((0xFC000) ^ 0xC000))) ; +} +@endif + +macro GetPagedAddr(addr,paddr) { +@if SIZE=="3" + setHCSphysPage(addr); + paddr = segment(physPage, addr); +@else + paddr = addr; +@endif +} + +macro Load1(value, addr) { + local paddr:$(SIZE); + + GetPagedAddr(addr,paddr); + + value = *:1 paddr; +} +macro Load2(value, addr) { + local paddr:$(SIZE); + + GetPagedAddr(addr,paddr); + + value = *:2 paddr; +} + +macro Store(addr, value) { + local paddr:$(SIZE); + + GetPagedAddr(addr,paddr); + + *paddr = value; +} + +################################################################ +# Addressing tables +################################################################ + +# +# TODO: Paging could be added here as these are constant addresses +# could factor the overlapping addresses here, unless the +# page register is always added in then will have to export as a constant +# since don't know the real address +# + +macro pageCAddr(addr, shift, page, offset) { + addr = (page << shift) | offset; +} +macro pagePAddr(addr, shift, page, offset) { + addr = (zext(page) << shift) | offset; +} + +@if defined(HCS12X) + +# known EPAGE offsets +opr16a: imm16 is imm16e=0x8 & imm16 & imm16ev { local addr:3 = 0x100000; pagePAddr(addr,10,EPAGE,imm16ev); export addr; } +opr16a: imm16 is imm16e=0x9 & imm16 & imm16ev { local addr:3 = 0x100000; pagePAddr(addr,10,EPAGE,imm16ev); export addr; } +opr16a: imm16 is imm16e=0xa & imm16 & imm16ev { local addr:3 = 0x100000; pagePAddr(addr,10,EPAGE,imm16ev); export addr; } +opr16a: imm16 is imm16e=0xb & imm16 & imm16ev { local addr:3 = 0x100000; pagePAddr(addr,10,EPAGE,imm16ev); export addr; } + +opr16a: imm16 is imm16e=0xc & imm16 & imm16ev { local addr:3 = 0; pageCAddr(addr,10,0xFF,imm16ev); export addr; } +opr16a: imm16 is imm16e=0xd & imm16 & imm16ev { local addr:3 = 0; pageCAddr(addr,10,0xFF,imm16ev); export addr; } +opr16a: imm16 is imm16e=0xe & imm16 & imm16ev { local addr:3 = 0; pageCAddr(addr,10,0xFF,imm16ev); export addr; } +opr16a: imm16 is imm16e=0xf & imm16 & imm16ev { local addr:3 = 0; pageCAddr(addr,10,0xFF,imm16ev); export addr; } + +# known RPAGE offsets +opr16a: imm16 is imm16p=0x1 & imm16 & imm16rv { local addr:3 = 0; pagePAddr(addr,12,RPAGE,imm16rv); export addr; } +opr16a: imm16 is imm16p=0x2 & imm16 & imm16rv { local addr:3 = 0; pageCAddr(addr,12,0xFE,imm16rv); export addr; } +opr16a: imm16 is imm16p=0x3 & imm16 & imm16rv { local addr:3 = 0; pageCAddr(addr,12,0xFF,imm16rv); export addr; } + +# known PPAGE offsets +opr16a: imm16 is imm16p=0x4 & imm16 & imm16pv { local addr:3 = 0x400000; pageCAddr(addr,14,0xFD,imm16pv); export addr; } +opr16a: imm16 is imm16p=0x5 & imm16 & imm16pv { local addr:3 = 0x400000; pageCAddr(addr,14,0xFD,imm16pv); export addr; } +opr16a: imm16 is imm16p=0x6 & imm16 & imm16pv { local addr:3 = 0x400000; pageCAddr(addr,14,0xFD,imm16pv); export addr; } +opr16a: imm16 is imm16p=0x7 & imm16 & imm16pv { local addr:3 = 0x400000; pageCAddr(addr,14,0xFD,imm16pv); export addr; } + +opr16a: imm16 is imm16p=0x8 & imm16 & imm16pv { local addr:3 = 0x400000; pagePAddr(addr,14,PPAGE,imm16pv & 0x3fff); export addr; } +opr16a: imm16 is imm16p=0x9 & imm16 & imm16pv { local addr:3 = 0x400000; pagePAddr(addr,14,PPAGE,imm16pv & 0x3fff); export addr; } +opr16a: imm16 is imm16p=0xa & imm16 & imm16pv { local addr:3 = 0x400000; pagePAddr(addr,14,PPAGE,imm16pv & 0x3fff); export addr; } +opr16a: imm16 is imm16p=0xb & imm16 & imm16pv { local addr:3 = 0x400000; pagePAddr(addr,14,PPAGE,imm16pv & 0x3fff); export addr; } + +opr16a: imm16 is imm16p=0xC & imm16 & imm16pv { local addr:3 = 0x400000; pageCAddr(addr,14,0xFF,imm16pv); export addr; } +opr16a: imm16 is imm16p=0xD & imm16 & imm16pv { local addr:3 = 0x400000; pageCAddr(addr,14,0xFF,imm16pv); export addr; } +opr16a: imm16 is imm16p=0xE & imm16 & imm16pv { local addr:3 = 0x400000; pageCAddr(addr,14,0xFF,imm16pv); export addr; } +opr16a: imm16 is imm16p=0xF & imm16 & imm16pv { local addr:3 = 0x400000; pageCAddr(addr,14,0xFF,imm16pv); export addr; } + +opr16a: imm16 is imm16e & imm16 { local addr:3 = imm16; export addr; } + +opr8a: imm8 is imm8 { export *[const]:3 imm8; } + +opr8a_8: imm8 is UseGPAGE=0 & imm8 { export *:1 imm8; } +opr8a_8: imm8 is UseGPAGE=1 & imm8 { local addr:3 = 0; pagePAddr(addr,16,GPAGE,imm8); export *:1 addr; } +opr8a_16: imm8 is UseGPAGE=0 & imm8 { export *:2 imm8; } +opr8a_16: imm8 is UseGPAGE=1 & imm8 { local addr:3 = 0; pagePAddr(addr,16,GPAGE,imm8); export *:2 addr; } + +opr16a_8: opr16a is UseGPAGE=0 & opr16a { export *:1 opr16a; } +opr16a_8: imm16 is UseGPAGE=1 & imm16 { local addr:3 = 0; pagePAddr(addr,16,GPAGE,imm16); export *:1 addr; } +opr16a_16: opr16a is UseGPAGE=0 & opr16a { export *:2 opr16a; } +opr16a_16: imm16 is UseGPAGE=1 & imm16 { local addr:3 = 0; pagePAddr(addr,16,GPAGE,imm16); export *:2 addr; } + +iopr8i: "#"imm8 is imm8 { export *[const]:1 imm8; } +iopr16i: "#"imm16 is imm16 { export *[const]:2 imm16; } +msk8: imm8 is imm8 { export *[const]:1 imm8; } +page: imm8 is imm8 { export *[const]:1 imm8; } + +#PageDest: dest is imm16p=0x8 & imm16 & imm16pv ; imm8 [ dest = (imm8 << 16) | imm16; ] { export *:1 dest; } +#PageDest: dest is imm16p=0x9 & imm16 & imm16pv ; imm8 [ dest = (imm8 << 16) | imm16; ] { export *:1 dest; } +#PageDest: dest is imm16p=0xa & imm16 & imm16pv ; imm8 [ dest = (imm8 << 16) | imm16; ] { export *:1 dest; } +#PageDest: dest is imm16p=0xb & imm16 & imm16pv ; imm8 [ dest = (imm8 << 16) | imm16; ] { export *:1 dest; } +#PageDest: dest is imm16p=0xc & imm16 & imm16pv ; imm8 [ dest = ($(MAXFLASHPage) << 16) | imm16; ] { export *:1 dest; } +#PageDest: dest is imm16p=0xd & imm16 & imm16pv ; imm8 [ dest = ($(MAXFLASHPage) << 16) | imm16; ] { export *:1 dest; } +#PageDest: dest is imm16p=0xe & imm16 & imm16pv ; imm8 [ dest = ($(MAXFLASHPage) << 16) | imm16; ] { export *:1 dest; } +#PageDest: dest is imm16p=0xf & imm16 & imm16pv ; imm8 [ dest = ($(MAXFLASHPage) << 16) | imm16; ] { export *:1 dest; } +PageDest: opr16a is opr16a; page { export opr16a; } + +@else + + +@if SIZE=="3" +opr16a: imm16 is imm16p=0x0 & imm16 & imm16pv { local addr:3 = 0; pageCAddr(addr,14,0x3D,imm16pv); export addr; } +opr16a: imm16 is imm16p=0x1 & imm16 & imm16pv { local addr:3 = 0; pageCAddr(addr,14,0x3D,imm16pv); export addr; } +opr16a: imm16 is imm16p=0x2 & imm16 & imm16pv { local addr:3 = 0; pageCAddr(addr,14,0x3D,imm16pv); export addr; } +opr16a: imm16 is imm16p=0x3 & imm16 & imm16pv { local addr:3 = 0; pageCAddr(addr,14,0x3D,imm16pv); export addr; } + +opr16a: imm16 is imm16p=0x4 & imm16 & imm16pv { local addr:3 = 0; pageCAddr(addr,14,0x3E,imm16pv); export addr; } +opr16a: imm16 is imm16p=0x5 & imm16 & imm16pv { local addr:3 = 0; pageCAddr(addr,14,0x3E,imm16pv); export addr; } +opr16a: imm16 is imm16p=0x6 & imm16 & imm16pv { local addr:3 = 0; pageCAddr(addr,14,0x3E,imm16pv); export addr; } +opr16a: imm16 is imm16p=0x7 & imm16 & imm16pv { local addr:3 = 0; pageCAddr(addr,14,0x3E,imm16pv); export addr; } + +opr16a: imm16 is imm16p=0x8 & imm16 & imm16pv { local addr:3 = 0; pagePAddr(addr,14,PPAGE,imm16pv & 0x3fff); export addr; } +opr16a: imm16 is imm16p=0x9 & imm16 & imm16pv { local addr:3 = 0; pagePAddr(addr,14,PPAGE,imm16pv & 0x3fff); export addr; } +opr16a: imm16 is imm16p=0xa & imm16 & imm16pv { local addr:3 = 0; pagePAddr(addr,14,PPAGE,imm16pv & 0x3fff); export addr; } +opr16a: imm16 is imm16p=0xb & imm16 & imm16pv { local addr:3 = 0; pagePAddr(addr,14,PPAGE,imm16pv & 0x3fff); export addr; } + +opr16a: imm16 is imm16p=0xc & imm16 & imm16pv { local addr:3 = 0; pageCAddr(addr,14,0x3F,imm16pv); export addr; } +opr16a: imm16 is imm16p=0xd & imm16 & imm16pv { local addr:3 = 0; pageCAddr(addr,14,0x3F,imm16pv); export addr; } +opr16a: imm16 is imm16p=0xe & imm16 & imm16pv { local addr:3 = 0; pageCAddr(addr,14,0x3F,imm16pv); export addr; } +opr16a: imm16 is imm16p=0xf & imm16 & imm16pv { local addr:3 = 0; pageCAddr(addr,14,0x3F,imm16pv); export addr; } + +page: imm8 is imm8 { export *[const]:1 imm8; } + +PageDest: opr16a is opr16a; page { export opr16a; } + +@elif SIZE=="2" +opr16a: imm16 is imm16 { local addr:$(SIZE) = imm16; export addr; } +@endif + +opr8a: imm8 is imm8 { local addr:$(SIZE) = imm8; export addr; } + +opr8a_8: imm8 is UseGPAGE=0 & imm8 { export *:1 imm8; } +opr8a_16: imm8 is UseGPAGE=0 & imm8 { export *:2 imm8; } + +opr16a_8: opr16a is opr16a { export *:1 opr16a; } +opr16a_16: opr16a is opr16a { export *:2 opr16a; } + +iopr8i: "#"imm8 is imm8 { export *[const]:1 imm8; } +iopr16i: "#"imm16 is imm16 { export *[const]:2 imm16; } +msk8: imm8 is imm8 { export *[const]:1 imm8; } + +@endif + + +# +# Postbyte Code (xb) address decoding +# for indexed addressing modes: IDX, IDX1, IDX2, [D,IDX] and [IDX2] +# +# +# per page 29, 30, and 33 +# + +#********** +# IDX +#********** +# +# rr0nnnnn +# +# 5-bit constant offset n = -16 to +15 +IDX_a: 0,rr7_6 is rr7_6 & xb5_5=0 & nn4_0=0 + { export rr7_6; } + +# TODO make sure that nn4_0 is a signed extension +IDX_b: nn4_0, rr7_6 is rr7_6 & xb5_5=0 & nn4_0 + { address:2 = rr7_6 + nn4_0; export address; } + +# rr1pnnnn +# +# used xb7_5 in all of these to prevent rr7_6a from ever being 0b11, and overlapping the 111rr0zs decodes +# +# Auto pre-decrement +IDX_c: nn3_0, -rr7_6a is (xb7_5=0b001 | xb7_5=0b011 | xb7_5=0b101) & rr7_6a & p4_4=0 & decrement3_3=1 & nn3_0 + { rr7_6a = rr7_6a + nn3_0; address:2 = rr7_6a; export address; } + +# Auto pre-increment +IDX_d: nn3_0, +rr7_6a is (xb7_5=0b001 | xb7_5=0b011 | xb7_5=0b101) & rr7_6a & p4_4=0 & decrement3_3=0 & nn3_0 + { rr7_6a = rr7_6a + nn3_0; address:2 = rr7_6a; export address; } + +# Auto post-decrement +IDX_e: nn3_0, rr7_6a- is (xb7_5=0b001 | xb7_5=0b011 | xb7_5=0b101) & rr7_6a & p4_4=1 & decrement3_3=1 & nn3_0 + { address:2 = rr7_6a; rr7_6a = rr7_6a + nn3_0; export address; } + +# Auto post-increment +IDX_f: nn3_0, rr7_6a+ is (xb7_5=0b001 | xb7_5=0b011 | xb7_5=0b101) & rr7_6a & p4_4=1 & decrement3_3=0 & nn3_0 + { address:2 = rr7_6a; rr7_6a = rr7_6a + nn3_0; export address; } + +# 111rr1aa +# +# Accumulator unsigned 8-bit offset indexed +IDX_g: aa0_0, rr4_3 is xb7_5=0b111 & rr4_3 & xb2_1=0b10 & aa0_0 + { address:2 = rr4_3 + zext(aa0_0); export address; } +IDX_g: aa0_0, PC is xb7_5=0b111 & rr4_3=3 & xb2_1=0b10 & aa0_0 & PC + { address:2 = inst_next + zext(aa0_0); export address; } + +# Accumulator 16-bit offset indexed +IDX_h: D, rr4_3 is xb7_5=0b111 & rr4_3 & xb2_0=0b110 & D + { address:2 = rr4_3 + D; export address; } +IDX_h: D, PC is xb7_5=0b111 & rr4_3=3 & xb2_0=0b110 & D & PC + { address:2 = inst_next + D; export address; } + +#********** +# IDX1 +#********** +# +# 111rr0zs imm8 +# +# Constant offset (9-bit signed) +IDX_i: opr9, rr4_3 is xb7_5=0b111 & rr4_3 & xb2_2=0 & z1_1=0 & ss0_0 ; imm8 [ opr9 = (ss0_0 << 8) | imm8; ] + { address:2 = rr4_3 + opr9; export address; } + +IDX_i_PCRel: target is ss0_0 ; imm8 [ target = inst_next + (ss0_0 << 8) | imm8; ] { export *[const]:2 target; } +IDX_i: opr9, PC is (xb7_5=0b111 & rr4_3=3 & xb2_2=0 & z1_1=0 & ss0_0 ; imm8) & IDX_i_PCRel & PC [ opr9 = (ss0_0 << 8) | imm8; ] + { export IDX_i_PCRel; } + +#********** +# IDX2 +#********** +# +# 111rr0zs simm16 +# +# Constant offset (16-bit signed) +IDX_k: simm16, rr4_3 is xb7_5=0b111 & rr4_3 & xb2_2=0 & z1_1=1 & s0_0=0; simm16 + { address:2 = rr4_3 + simm16; export address; } + +IDX_k_PCRel: target is simm16 [ target = inst_next + simm16; ] { export *[const]:2 target; } +IDX_k: simm16, PC is xb7_5=0b111 & rr4_3=3 & xb2_2=0 & z1_1=1 & s0_0=0; simm16 & PC & IDX_k_PCRel + { export IDX_k_PCRel; } + +#********** +# [IDX2] +#********** +# +# 111rr011 simm16 +# +# 16-bit offset indexed-indirect + +IDX_l: [simm16, rr4_3] is xb7_5=0b111 & rr4_3 & xb2_2=0 & z1_1=1 & s0_0=1; simm16 + { address:2 = rr4_3 + simm16; Load2(address,address); export address; } + +IDX_l_PCRel: target is simm16 [ target = inst_next + simm16; ] { export *[const]:2 target; } +IDX_l: [simm16, PC] is xb7_5=0b111 & rr4_3=3 & xb2_2=0 & z1_1=1 & s0_0=1; simm16 & PC & IDX_l_PCRel + { address:2 = IDX_l_PCRel; Load2(address,address); export address; } + +#********** +# [D,IDX] +#********** +# +# 111rr111 +# +# Accumulator D offset indexed-indirect +IDX_m: [D, rr4_3] is xb7_5=0b111 & rr4_3 & xb2_0=0b111 & D + { address:2 = rr4_3 + D; Load2(address,address); export address; } + +IDX_m: [D, PC] is xb7_5=0b111 & rr4_3=3 & xb2_0=0b111 & D & PC + { address:2 = inst_next + D; Load2(address,address); export address; } + +###################################################################### +###################################################################### +# +# effective address of IDX, IDX1, IDX2 +# +indexed3: IDX_a is IDX_a { export IDX_a; } +indexed3: IDX_b is IDX_b { export IDX_b; } +indexed3: IDX_c is IDX_c { export IDX_c; } +indexed3: IDX_d is IDX_d { export IDX_d; } +indexed3: IDX_e is IDX_e { export IDX_e; } +indexed3: IDX_f is IDX_f { export IDX_f; } +indexed3: IDX_g is IDX_g { export IDX_g; } +indexed3: IDX_h is IDX_h { export IDX_h; } +indexed3: IDX_i is IDX_i { export IDX_i; } +indexed3: IDX_k is IDX_k { export IDX_k; } +# not indexed3: IDX_l is IDX_l { export IDX_l; } +# not indexed3: IDX_m is IDX_m { export IDX_m; } + +# +# effective address of [IDX2], [D,IDX] +# +# not indexedindexed3: IDX_a is IDX_a { export IDX_a; } +# not indexedindexed3: IDX_b is IDX_b { export IDX_b; } +# not indexedindexed3: IDX_c is IDX_c { export IDX_c; } +# not indexedindexed3: IDX_d is IDX_d { export IDX_d; } +# not indexedindexed3: IDX_e is IDX_e { export IDX_e; } +# not indexedindexed3: IDX_f is IDX_f { export IDX_f; } +# not indexedindexed3: IDX_g is IDX_g { export IDX_g; } +# not indexedindexed3: IDX_h is IDX_h { export IDX_h; } +# not indexedindexed3: IDX_i is IDX_i { export IDX_i; } +# not indexedindexed3: IDX_k is IDX_k { export IDX_k; } +@ifdef HCS12 +indexed2: IDX_l is IDX_l { export IDX_l; } +indexed2: IDX_m is IDX_m { export IDX_m; } +@endif + +# +# effective address of IDX, IDX1, IDX2, [IDX2], [D,IDX] +# +indexed5: IDX_a is IDX_a { export IDX_a; } +indexed5: IDX_b is IDX_b { export IDX_b; } +indexed5: IDX_c is IDX_c { export IDX_c; } +indexed5: IDX_d is IDX_d { export IDX_d; } +indexed5: IDX_e is IDX_e { export IDX_e; } +indexed5: IDX_f is IDX_f { export IDX_f; } +indexed5: IDX_g is IDX_g { export IDX_g; } +indexed5: IDX_h is IDX_h { export IDX_h; } +indexed5: IDX_i is IDX_i { export IDX_i; } +indexed5: IDX_k is IDX_k { export IDX_k; } +indexed5: IDX_l is IDX_l { export IDX_l; } +indexed5: IDX_m is IDX_m { export IDX_m; } + +# +# effective address of IDX +# +indexed1: IDX_a is IDX_a { export IDX_a; } +indexed1: IDX_b is IDX_b { export IDX_b; } +indexed1: IDX_c is IDX_c { export IDX_c; } +indexed1: IDX_d is IDX_d { export IDX_d; } +indexed1: IDX_e is IDX_e { export IDX_e; } +indexed1: IDX_f is IDX_f { export IDX_f; } +indexed1: IDX_g is IDX_g { export IDX_g; } +indexed1: IDX_h is IDX_h { export IDX_h; } +# not indexed1: IDX_i is IDX_i { export IDX_i; } +# not indexed1: IDX_k is IDX_k { export IDX_k; } +# not indexed1: iIDX_l is iIDX_l { export iIDX_l; } +# not indexed1: IDX_m is IDX_m { export IDX_m; } + + +# +# indexed0_x - exports the effective address (EA) +# indexed1_x - exports a single byte at the effective address +# indexed2_x - exports a double byte at the effective address +# + +@ifndef HCS12X +indexed1_1: indexed1 is indexed1 { + local paddr:$(SIZE) = 0; + GetPagedAddr(indexed1,paddr); + export *:1 paddr; +} +@endif + +@ifdef HCS12 +indexed2_1: indexed1 is indexed1 { + local paddr:$(SIZE) = 0; + GetPagedAddr(indexed1,paddr); + export *:2 paddr; +} +@else +indexed2_1: indexed1 is indexed1 { + export *:2 indexed1; +} +@endif + +@ifdef HCS12 +indexed0_2: indexed2 is indexed2 { + local val = indexed2; export val; +} +@endif + + +indexed0_3: indexed3 is indexed3 { + local val = indexed3; export val; +} +@ifdef HCS12 +indexed1_3: indexed3 is indexed3 { + local paddr:$(SIZE) = 0; + GetPagedAddr(indexed3,paddr); + export *:1 paddr; +} +@else +indexed1_3: indexed3 is indexed3 { + export *:1 indexed3; +} +@endif + +@ifdef HCS12 +indexed2_3: indexed3 is indexed3 { + local paddr:$(SIZE) = 0; + GetPagedAddr(indexed3,paddr); + export *:2 paddr; +} +@endif + +@ifdef HCS12 +indexedA_5: indexed5 is UseGPAGE=0 & indexed5 { + local paddr:$(SIZE) = 0; + GetPagedAddr(indexed5,paddr); + export paddr; +} +@else +indexedA_5: indexed5 is UseGPAGE=0 & indexed5 { + export indexed5; +} +@endif + +@ifdef HCS12X +indexedA_5: indexed5 is UseGPAGE=1 & indexed5 { + local addr:$(SIZE) = (zext(GPAGE) << 16) | zext(indexed5); + export addr; +} +@endif + +@ifdef HCS12 +indexed1_5: indexed5 is UseGPAGE=0 & indexed5 { + local paddr:$(SIZE) = 0; + GetPagedAddr(indexed5,paddr); + export *:1 paddr; +} +@else +indexed1_5: indexed5 is UseGPAGE=0 & indexed5 { + export *:1 indexed5; +} +@endif + +@ifdef HCS12X +indexed1_5: indexed5 is UseGPAGE=1 & indexed5 { + local addr:$(SIZE) = (zext(GPAGE) << 16) | zext(indexed5); + export *:1 addr; +} +@endif + +@ifdef HCS12 +indexed2_5: indexed5 is UseGPAGE=0 & indexed5 { + local paddr:$(SIZE) = 0; + GetPagedAddr(indexed5,paddr); + export *:2 paddr; +} +@else +indexed2_5: indexed5 is UseGPAGE=0 & indexed5 { + export indexed5; +} +@endif + +@ifdef HCS12X +indexed2_5: indexed5 is UseGPAGE=1 & indexed5 { + local addr:$(SIZE) = (zext(GPAGE) << 16) | zext(indexed5); + export *:2 addr; +} +@endif + +# range -128 through +127 +rel8: reloc is rel [ reloc = inst_next + rel; ] { export *:1 reloc; } + +# range -256 through +255 +rel9: reloc is sign12_12 & rr7_0 [ reloc = inst_next + ((sign12_12 << 8) | rr7_0); ] { export *:1 reloc; } + +# positive range 0 through +65535 +rel16: reloc is simm16 [ reloc = inst_next + simm16; ] { export *:1 reloc; } + + +op2_opr16a_8: opr16a_8 is opr16a_8 { export opr16a_8; } +op2_opr16a_16: opr16a_16 is opr16a_16 { export opr16a_16; } + +@if defined(HCS12X) +op2_indexed1_5: indexed1_5 is indexed1_5 { export indexed1_5; } +@else +op2_indexed1_1: indexed1_1 is indexed1_1 { export indexed1_1; } +@endif + +@if defined(HCS12X) +op2_indexed2_5: indexed2_5 is indexed2_5 { export indexed2_5; } +@else +op2_indexed2_1: indexed2_1 is indexed2_1 { export indexed2_1; } +@endif + +################################################################ +# Macros +################################################################ + + + +macro additionWithCarry(operand1, operand2, result) { + local Ccopy = zext($(C)); + local AFmask = -1 >> 4; + $(H) = (((operand1 & AFmask) + (operand2 & AFmask) + Ccopy) & (AFmask + 1)) != 0; + $(C) = carry(operand1, operand2); + local tempResult = operand1 + operand2; + $(C) = $(C) || carry(tempResult, Ccopy); + $(V) = $(V) ^^ scarry(tempResult, Ccopy); + result = tempResult + Ccopy; + $(N) = (result s< 0); + $(Z) = (result == 0); +} + + + +macro addition_flags1(operand1, operand2,result) { + local AFmask = -1 >> 4; + $(H) = (((operand1 & AFmask) + (operand2 & AFmask)) & (AFmask + 1)) != 0; + + $(N) = (result s< 0); + $(Z) = (result == 0); + $(V) = scarry(operand1,operand2); + $(C) = carry(operand1,operand2); +} + +macro addition_flags2(operand1, operand2, result) { + $(N) = (result s< 0); + $(Z) = (result == 0); + $(V) = scarry(operand1,operand2); + $(C) = carry(operand1,operand2); +} + +macro subtraction_flags1(register, operand, result) { + $(V) = sborrow(register,operand); + $(N) = (result s< 0); + $(Z) = (result == 0); + $(C) = register < operand; +} + +macro subtraction_flags2(register, operand, result) { + $(V) = sborrow(register,operand); + $(N) = (result s< 0); + $(Z) = (result == 0); + $(C) = register < operand; +} + +macro V_equals_0() { + $(V) = 0; +} + +macro V_equals_C() { + $(V) = $(C); +} + +macro V_equals_N_xor_C() { + $(V) = $(N) ^ $(C); +} + +macro V_CMP_flag(register, operand) { + $(V) = sborrow(register,operand); +} + +macro V_DEC_flag(operand) { + $(V) = sborrow(operand,1); +} + +macro V_DEC_flag2(operand) { + $(V) = sborrow(operand,1); +} + +macro V_INC_flag(operand) { + $(V) = scarry(operand,1); +} + +macro V_INC_flag2(operand) { + $(V) = scarry(operand,1); +} + +macro V_NEG_flag(operand) { + $(V) = sborrow(0,operand); +} + +macro V_NEG_flag2(operand) { + $(V) = sborrow(0,operand); +} + +macro Pull1(operand) { +@if SIZE=="3" + setHCSphysPage(SP); + paddr:$(SIZE) = segment(physPage,SP); +@else + paddr:$(SIZE) = SP; +@endif + operand = *paddr; + SP = SP + 1; +} + +macro Pull2(operand) { +@if SIZE=="3" + setHCSphysPage(SP); + paddr:$(SIZE) = segment(physPage,SP); +@else + paddr:$(SIZE) = SP; +@endif + + operand = *paddr; + SP = SP + 2; +} + +macro Push1(operand) { + SP = SP - 1; + +@if SIZE=="3" + setHCSphysPage(SP); + paddr:$(SIZE) = segment(physPage,SP); +@else + paddr:$(SIZE) = SP; +@endif + + *paddr = operand; +} + +macro Push2(operand) { + SP = SP - 2; + +@if SIZE=="3" + setHCSphysPage(SP); + paddr:$(SIZE) = segment(physPage,SP); +@else + paddr:$(SIZE) = SP; +@endif + + *paddr = operand; +} + +macro setCCR( operand ) { + # when CCR is the destination, cannot set the X bit unless it is already set in CCR + CCR = operand & (CCR | 0b10111111); +} + +macro setCCRW( operand ) { + # when CCRW is the destination, cannot set the X bit unless it is already set in CCRW + CCRW = operand & (CCRW | 0b1111111110111111); +} + +################################################################ +# Constructors +################################################################ + +with : XGATE=0 { +@ifdef HCS12X +:^instruction is op8=0x18; instruction [ Prefix18=1; ] {} +@else +:^instruction is op8=0x18; instruction [ Prefix18=1; ] {} +@endif + +:ABA is (Prefix18=1 & op8=0x06) +{ + result:1 = A + B; + addition_flags1(A, B, result); + A = result; +} + +:ABX is Prefix18=0 & (op16=0x1AE5) +{ + IX = zext(B) + IX; +} + +:ABY is Prefix18=0 & (op16=0x19ED) +{ + IY = zext(B) + IY; +} + +:ADCA iopr8i is Prefix18=0 & (op8=0x89); iopr8i +{ + op1:1 = iopr8i; + + local result:1; + additionWithCarry(A, op1, result); + + A = result; +} + +:ADCA opr8a_8 is Prefix18=0 & (op8=0x99); opr8a_8 +{ + op1:1 = opr8a_8; + + local result:1; + additionWithCarry(A, op1, result); + + A = result; +} + +:ADCA opr16a_8 is Prefix18=0 & (op8=0xB9); opr16a_8 +{ + op1:1 = opr16a_8; + + local result:1; + additionWithCarry(A, op1, result); + + A = result; +} + +:ADCA indexed1_5 is Prefix18=0 & (op8=0xA9); indexed1_5 +{ + op1:1 = indexed1_5; + + result:1 = A + op1 + $(C); + addition_flags1(A, op1, result); + A = result; +} + +:ADCB iopr8i is Prefix18=0 & (op8=0xC9); iopr8i +{ + op1:1 = iopr8i; + + local result:1; + additionWithCarry(A, op1, result); + + B = result; +} + +:ADCB opr8a_8 is Prefix18=0 & (op8=0xD9); opr8a_8 +{ + op1:1 = opr8a_8; + + result:1 = B + op1 + $(C); + addition_flags1(B, op1, result); + B = result; +} + +:ADCB opr16a_8 is Prefix18=0 & (op8=0xF9); opr16a_8 +{ + op1:1 = opr16a_8; + + local result:1; + additionWithCarry(B, op1, result); + + B = result; +} + +:ADCB indexed1_5 is Prefix18=0 & (op8=0xE9); indexed1_5 +{ + op1:1 = indexed1_5; + + local result:1; + additionWithCarry(B, op1, result); + + B = result; +} + +:ADDA iopr8i is Prefix18=0 & (op8=0x8B); iopr8i +{ + op1:1 = iopr8i; + + result:1 = A + op1; + addition_flags1(A, op1, result); + + A = result; +} + +:ADDA opr8a_8 is Prefix18=0 & (op8=0x9B); opr8a_8 +{ + op1:1 = opr8a_8; + + result:1 = A + op1; + addition_flags1(A, op1, result); + A = result; +} + +:ADDA opr16a_8 is Prefix18=0 & (op8=0xBB); opr16a_8 +{ + op1:1 = opr16a_8; + + result:1 = A + op1; + addition_flags1(A, op1, result); + A = result; +} + +:ADDA indexed1_5 is Prefix18=0 & (op8=0xAB); indexed1_5 +{ + op1:1 = indexed1_5; + + result:1 = A + op1; + addition_flags1(A, op1, result); + A = result; +} + +:ADDB iopr8i is Prefix18=0 & (op8=0xCB); iopr8i +{ + op1:1 = iopr8i; + + result:1 = B + op1; + addition_flags1(B, op1, result); + B = result; +} + +:ADDB opr8a_8 is Prefix18=0 & (op8=0xDB); opr8a_8 +{ + op1:1 = opr8a_8; + + result:1 = B + op1; + addition_flags1(B, op1, result); + B = result; +} + +:ADDB opr16a_8 is Prefix18=0 & (op8=0xFB); opr16a_8 +{ + op1:1 = opr16a_8; + + result:1 = B + op1; + addition_flags1(B, op1, result); + B = result; +} + +:ADDB indexed1_5 is Prefix18=0 & (op8=0xEB); indexed1_5 +{ + op1:1 = indexed1_5; + + result:1 = B + op1; + addition_flags1(B, op1, result); + B = result; +} + +:ADDD iopr16i is Prefix18=0 & (op8=0xC3); iopr16i +{ + op1:2 = iopr16i; + + result:2 = D + op1; + addition_flags2(D, op1, result); + D = result; +} + +:ADDD opr8a_16 is Prefix18=0 & (op8=0xD3); opr8a_16 +{ + op1:2 = opr8a_16; + + result:2 = D + op1; + addition_flags2(D, op1, result); + D = result; +} + +:ADDD opr16a_16 is Prefix18=0 & (op8=0xF3); opr16a_16 +{ + op1:2 = opr16a_16; + + result:2 = D + op1; + addition_flags2(D, op1, result); + D = result; +} + +:ADDD indexed2_5 is Prefix18=0 & (op8=0xE3); indexed2_5 +{ + op1:2 = indexed2_5; + + result:2 = D + op1; + addition_flags2(D, op1, result); + D = result; +} + +@if defined(HCS12X) +:ADDX iopr16i is Prefix18=1 & (op8=0x8B); iopr16i +{ + op1:2 = iopr16i; + + result:2 = IX + op1; + addition_flags2(IX, op1, result); + IX = result; +} +@endif + +@if defined(HCS12X) +:ADDX opr8a_16 is Prefix18=1 & (op8=0x9B); opr8a_16 +{ + op1:2 = opr8a_16; + + result:2 = IX + op1; + addition_flags2(IX, op1, result); + IX = result; +} +@endif + +@if defined(HCS12X) +:ADDX opr16a_16 is Prefix18=1 & (op8=0xBB); opr16a_16 +{ + op1:2 = opr16a_16; + + result:2 = IX + op1; + addition_flags2(IX, op1, result); + IX = result; +} +@endif + +@if defined(HCS12X) +:ADDX indexed2_5 is Prefix18=1 & (op8=0xAB); indexed2_5 +{ + op1:2 = indexed2_5; + + result:2 = IX + op1; + addition_flags2(IX, op1, result); + IX = result; +} +@endif + +@if defined(HCS12X) +:ADDY iopr16i is Prefix18=1 & (op8=0xCB); iopr16i +{ + op1:2 = iopr16i; + + result:2 = IY + op1; + addition_flags2(IY, op1, result); + IY = result; +} +@endif + +@if defined(HCS12X) +:ADDY opr8a_16 is Prefix18=1 & (op8=0xDB); opr8a_16 +{ + op1:2 = opr8a_16; + + result:2 = IY + op1; + addition_flags2(IY, op1, result); + IY = result; +} +@endif + +@if defined(HCS12X) +:ADDY opr16a_16 is Prefix18=1 & (op8=0xFB); opr16a_16 +{ + op1:2 = opr16a_16; + + result:2 = IY + op1; + addition_flags2(IY, op1, result); + IY = result; +} +@endif + +@if defined(HCS12X) +:ADDY indexed2_5 is Prefix18=1 & (op8=0xEB); indexed2_5 +{ + op1:2 = indexed2_5; + + result:2 = IY + op1; + addition_flags2(IY, op1, result); + IY = result; +} +@endif + +@if defined(HCS12X) +:ADED iopr16i is Prefix18=1 & (op8=0xC3); iopr16i +{ + op1:2 = iopr16i; + + result:2 = D + op1 + zext($(C)); + addition_flags2(D, op1, result); + D = result; +} +@endif + +@if defined(HCS12X) +:ADED opr8a_16 is Prefix18=1 & (op8=0xD3); opr8a_16 +{ + op1:2 = opr8a_16; + + result:2 = D + op1 + zext($(C)); + addition_flags2(D, op1, result); + D = result; +} +@endif + +@if defined(HCS12X) +:ADED opr16a_16 is Prefix18=1 & (op8=0xF3); opr16a_16 +{ + op1:2 = opr16a_16; + + result:2 = D + op1 + zext($(C)); + addition_flags2(D, op1, result); + D = result; +} +@endif + +@if defined(HCS12X) +:ADED indexed2_5 is Prefix18=1 & (op8=0xE3); indexed2_5 +{ + op1:2 = indexed2_5; + + result:2 = D + op1 + zext($(C)); + addition_flags2(D, op1, result); + D = result; +} +@endif + +@if defined(HCS12X) +:ADEX iopr16i is Prefix18=1 & (op8=0x89); iopr16i +{ + op1:2 = iopr16i; + + result:2 = IX + op1 + zext($(C)); + addition_flags2(IX, op1, result); + IX = result; +} +@endif + +@if defined(HCS12X) +:ADEX opr8a_16 is Prefix18=1 & (op8=0x99); opr8a_16 +{ + op1:2 = opr8a_16; + + result:2 = IX + op1 + zext($(C)); + addition_flags2(IX, op1, result); + IX = result; +} +@endif + +@if defined(HCS12X) +:ADEX opr16a_16 is Prefix18=1 & (op8=0xb9); opr16a_16 +{ + op1:2 = opr16a_16; + + result:2 = IX + op1 + zext($(C)); + addition_flags2(IX, op1, result); + IX = result; +} +@endif + +@if defined(HCS12X) +:ADEX indexed2_5 is Prefix18=1 & (op8=0xa9); indexed2_5 +{ + op1:2 = indexed2_5; + + result:2 = IX + op1 + zext($(C)); + addition_flags2(IX, op1, result); + IX = result; +} +@endif + +@if defined(HCS12X) +:ADEY iopr16i is Prefix18=1 & (op8=0xC9); iopr16i +{ + op1:2 = iopr16i; + + result:2 = IY + op1 + zext($(C)); + addition_flags2(IY, op1, result); + IY = result; +} +@endif + +@if defined(HCS12X) +:ADEY opr8a_16 is Prefix18=1 & (op8=0xD9); opr8a_16 +{ + op1:2 = opr8a_16; + + result:2 = IY + op1 + zext($(C)); + addition_flags2(IY, op1, result); + IY = result; +} +@endif + +@if defined(HCS12X) +:ADEY opr16a_16 is Prefix18=1 & (op8=0xF9); opr16a_16 +{ + op1:2 = opr16a_16; + + result:2 = IY + op1 + zext($(C)); + addition_flags2(IY, op1, result); + IY = result; +} +@endif + +@if defined(HCS12X) +:ADEY indexed2_5 is Prefix18=1 & (op8=0xE9); indexed2_5 +{ + op1:2 = indexed2_5; + + result:2 = IY + op1 + zext($(C)); + addition_flags2(IY, op1, result); + IY = result; +} +@endif + +:ANDA iopr8i is Prefix18=0 & (op8=0x84); iopr8i +{ + A = A & iopr8i; + V_equals_0(); + $(Z) = (A == 0); + $(N) = (A s< 0); +} + +:ANDA opr8a_8 is Prefix18=0 & (op8=0x94); opr8a_8 +{ + A = A & opr8a_8; + V_equals_0(); + $(Z) = (A == 0); + $(N) = (A s< 0); +} + +:ANDA opr16a_8 is Prefix18=0 & (op8=0xB4); opr16a_8 +{ + A = A & opr16a_8; + V_equals_0(); + $(Z) = (A == 0); + $(N) = (A s< 0); +} + +:ANDA indexed1_5 is Prefix18=0 & (op8=0xA4); indexed1_5 +{ + A = A & indexed1_5; + V_equals_0(); + $(Z) = (A == 0); + $(N) = (A s< 0); +} + +:ANDB iopr8i is Prefix18=0 & (op8=0xC4); iopr8i +{ + B = B & iopr8i; + V_equals_0(); + $(Z) = (B == 0); + $(N) = (B s< 0); +} + +:ANDB opr8a_8 is Prefix18=0 & (op8=0xD4); opr8a_8 +{ + B = B & opr8a_8; + V_equals_0(); + $(Z) = (B == 0); + $(N) = (B s< 0); +} + +:ANDB opr16a_8 is Prefix18=0 & (op8=0xF4); opr16a_8 +{ + B = B & opr16a_8; + V_equals_0(); + $(Z) = (B == 0); + $(N) = (B s< 0); +} + +:ANDB indexed1_5 is Prefix18=0 & (op8=0xE4); indexed1_5 +{ + B = B & indexed1_5; + V_equals_0(); + $(Z) = (B == 0); + $(N) = (B s< 0); +} + +:ANDCC iopr8i is Prefix18=0 & (op8=0x10); iopr8i +{ + CCR = CCR & iopr8i; +} + +@if defined(HCS12X) +:ANDX iopr16i is Prefix18=1 & (op8=0x84); iopr16i +{ + IX = IX & iopr16i; + V_equals_0(); + $(Z) = (IX == 0); + $(N) = (IX s< 0); +} +@endif + +@if defined(HCS12X) +:ANDX opr8a_16 is Prefix18=1 & (op8=0x94); opr8a_16 +{ + IX = IX & opr8a_16; + V_equals_0(); + $(Z) = (IX == 0); + $(N) = (IX s< 0); +} +@endif + +@if defined(HCS12X) +:ANDX opr16a_16 is Prefix18=1 & (op8=0xB4); opr16a_16 +{ + IX = IX & opr16a_16; + V_equals_0(); + $(Z) = (IX == 0); + $(N) = (IX s< 0); +} +@endif + +@if defined(HCS12X) +:ANDX indexed2_5 is Prefix18=1 & (op8=0xA4); indexed2_5 +{ + IX = IX & indexed2_5; + V_equals_0(); + $(Z) = (IX == 0); + $(N) = (IX s< 0); +} +@endif + +@if defined(HCS12X) +:ANDY iopr16i is Prefix18=1 & (op8=0xC4); iopr16i +{ + IY = IY & iopr16i; + V_equals_0(); + $(Z) = (IY == 0); + $(N) = (IY s< 0); +} +@endif + +@if defined(HCS12X) +:ANDY opr8a_16 is Prefix18=1 & (op8=0xD4); opr8a_16 +{ + IY = IY & opr8a_16; + V_equals_0(); + $(Z) = (IY == 0); + $(N) = (IY s< 0); +} +@endif + +@if defined(HCS12X) +:ANDY opr16a_16 is Prefix18=1 & (op8=0xF4); opr16a_16 +{ + IY = IY & opr16a_16; + V_equals_0(); + $(Z) = (IY == 0); + $(N) = (IY s< 0); +} +@endif + +@if defined(HCS12X) +:ANDY indexed2_5 is Prefix18=1 & (op8=0xE4); indexed2_5 +{ + IY = IY & indexed2_5; + V_equals_0(); + $(Z) = (IY == 0); + $(N) = (IY s< 0); +} +@endif + +:ASL opr16a_8 is Prefix18=0 & (op8=0x78); opr16a_8 +{ + tmp:1 = opr16a_8; + $(C) = tmp[7,1]; + tmp = tmp << 1; + opr16a_8 = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + V_equals_N_xor_C(); +} + +:ASL indexed1_5 is Prefix18=0 & (op8=0x68); indexed1_5 +{ + tmp:1 = indexed1_5; + $(C) = tmp[7,1]; + tmp = tmp << 1; + indexed1_5 = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + V_equals_N_xor_C(); +} + +:ASLA is Prefix18=0 & op8=0x48 +{ + $(C) = A[7,1]; + A = A << 1; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_N_xor_C(); +} + +:ASLB is Prefix18=0 & op8=0x58 +{ + $(C) = B[7,1]; + B = B << 1; + $(Z) = (B == 0); + $(N) = (B s< 0); + V_equals_N_xor_C(); +} + +:ASLD is Prefix18=0 & op8=0x59 +{ + $(C) = D[15,1]; + D = D << 1; + $(Z) = (D == 0); + $(N) = (D s< 0); + V_equals_N_xor_C(); +} + +@if defined(HCS12X) +:ASLW opr16a_16 is Prefix18=1 & (op8=0x78); opr16a_16 +{ + local tmp = opr16a_16; + $(C) = tmp[15,1]; + tmp = tmp << 1; + opr16a_16 = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS12X) +:ASLW indexed2_5 is Prefix18=1 & (op8=0x68); indexed2_5 +{ + local tmp = indexed2_5; + $(C) = tmp[15,1]; + tmp = tmp << 1; + indexed2_5 = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS12X) +:ASLX is Prefix18=1 & op8=0x48 +{ + $(C) = IX[15,1]; + IX = IX << 1; + $(Z) = (IX == 0); + $(N) = (IX s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS12X) +:ASLY is Prefix18=1 & op8=0x58 +{ + $(C) = IY[15,1]; + IY = IY << 1; + $(Z) = (IY == 0); + $(N) = (IY s< 0); + V_equals_N_xor_C(); +} +@endif + +:ASR opr16a_8 is Prefix18=0 & (op8=0x77); opr16a_8 +{ + tmp:1 = opr16a_8; + $(C) = tmp[0,1]; + tmp = tmp s>> 1; + opr16a_8 = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + V_equals_N_xor_C(); +} + +:ASR indexed1_5 is Prefix18=0 & (op8=0x67); indexed1_5 +{ + tmp:1 = indexed1_5; + $(C) = tmp[0,1]; + tmp = tmp s>> 1; + indexed1_5 = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + V_equals_N_xor_C(); +} + +:ASRA is Prefix18=0 & op8=0x47 +{ + $(C) = A[0,1]; + A = A s>> 1; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_N_xor_C(); +} + +:ASRB is Prefix18=0 & op8=0x57 +{ + $(C) = B[0,1]; + B = B s>> 1; + $(Z) = (B == 0); + $(N) = (B s< 0); + V_equals_N_xor_C(); +} + +@if defined(HCS12X) +:ASRW opr16a_16 is Prefix18=1 & (op8=0x77); opr16a_16 +{ + local tmp = opr16a_16; + $(C) = tmp[0,1]; + tmp = tmp s>> 1; + opr16a_16 = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS12X) +:ASRW indexed2_5 is Prefix18=1 & (op8=0x67); indexed2_5 +{ + local tmp = indexed2_5; + $(C) = tmp[0,1]; + tmp = tmp s>> 1; + indexed2_5 = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS12X) +:ASRX is Prefix18=1 & op8=0x47 +{ + $(C) = IX[0,1]; + IX = IX s>> 1; + $(Z) = (IX == 0); + $(N) = (IX s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS12X) +:ASRY is Prefix18=1 & op8=0x57 +{ + $(C) = IY[0,1]; + IY = IY s>> 1; + $(Z) = (IY == 0); + $(N) = (IY s< 0); + V_equals_N_xor_C(); +} +@endif + +:BCC rel8 is Prefix18=0 & op8=0x24; rel8 +{ + if ($(C) == 0) goto rel8; +} + +:BCLR opr8a_8, msk8 is Prefix18=0 & (op8=0x4D); opr8a_8; msk8 +{ + op1:1 = opr8a_8; + op1 = op1 & ~msk8; + opr8a_8 = op1; + $(N) = (op1 s< 0); + $(Z) = (op1 == 0); + V_equals_0(); +} + +:BCLR opr16a_8, msk8 is Prefix18=0 & (op8=0x1D); opr16a_8; msk8 +{ + op1:1 = opr16a_8; + op1 = op1 & ~msk8; + opr16a_8 = op1; + $(N) = (op1 s< 0); + $(Z) = (op1 == 0); + V_equals_0(); +} + +:BCLR indexed1_3, msk8 is Prefix18=0 & (op8=0x0D); indexed1_3; msk8 +{ + op1:1 = indexed1_3; + op1 = op1 & ~msk8; + indexed1_3 = op1; + $(N) = (op1 s< 0); + $(Z) = (op1 == 0); + V_equals_0(); +} + +:BCS rel8 is Prefix18=0 & op8=0x25; rel8 +{ + if ($(C) == 1) goto rel8; +} + +:BEQ rel8 is Prefix18=0 & op8=0x27; rel8 +{ + if ($(Z) == 1) goto rel8; +} + +:BGE rel8 is Prefix18=0 & op8=0x2C; rel8 +{ + if (($(N) ^ $(V)) == 1) goto rel8; +} + +@if defined(HCS12) +:BGND is Prefix18=0 & op8=0x00 +{ + BDM_return:$(SIZE) = inst_next; + # this could return BDM location, or BDM_return + PCE = backgroundDebugMode(BDM_return); + goto [PCE]; +} +@endif + +:BGT rel8 is Prefix18=0 & op8=0x2E; rel8 +{ + if (($(Z) | ($(N) ^ $(V))) == 0) goto rel8; +} + +:BHI rel8 is Prefix18=0 & op8=0x22; rel8 +{ + if (($(C) | $(Z)) == 0) goto rel8; +} + +#:BHS rel8 is op8=0x24; rel8 See BCC + +:BITA iopr8i is Prefix18=0 & (op8=0x85); iopr8i +{ + result:1 = A & iopr8i; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_equals_0(); +} + +:BITA opr8a_8 is Prefix18=0 & (op8=0x95); opr8a_8 +{ + result:1 = A & opr8a_8; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_equals_0(); +} + +:BITA opr16a_8 is Prefix18=0 & (op8=0xB5); opr16a_8 +{ + result:1 = A & opr16a_8; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_equals_0(); +} + +:BITA indexed1_5 is Prefix18=0 & (op8=0xA5); indexed1_5 +{ + result:1 = A & indexed1_5; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_equals_0(); +} + +:BITB iopr8i is Prefix18=0 & (op8=0xC5); iopr8i +{ + result:1 = B & iopr8i; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_equals_0(); +} + +:BITB opr8a_8 is Prefix18=0 & (op8=0xD5); opr8a_8 +{ + result:1 = B & opr8a_8; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_equals_0(); +} + +:BITB opr16a_8 is Prefix18=0 & (op8=0xF5); opr16a_8 +{ + result:1 = B & opr16a_8; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_equals_0(); +} + +:BITB indexed1_5 is Prefix18=0 & (op8=0xE5); indexed1_5 +{ + result:1 = B & indexed1_5; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_equals_0(); +} + +@if defined(HCS12X) +:BITX iopr16i is Prefix18=1 & (op8=0x85); iopr16i +{ + local result = IX & iopr16i; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS12X) +:BITX opr8a_16 is Prefix18=1 & (op8=0x95); opr8a_16 +{ + local result = IX & opr8a_16; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS12X) +:BITX opr16a_16 is Prefix18=1 & (op8=0xB5); opr16a_16 +{ + local result = IX & opr16a_16; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS12X) +:BITX indexed2_5 is Prefix18=1 & (op8=0xA5); indexed2_5 +{ + local result = IX & indexed2_5; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS12X) +:BITY iopr16i is Prefix18=1 & (op8=0xC5); iopr16i +{ + local result = IY & iopr16i; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS12X) +:BITY opr8a_16 is Prefix18=1 & (op8=0xD5); opr8a_16 +{ + local result = IY & opr8a_16; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS12X) +:BITY opr16a_16 is Prefix18=1 & (op8=0xF5); opr16a_16 +{ + local result = IY & opr16a_16; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS12X) +:BITY indexed2_5 is Prefix18=1 & (op8=0xE5); indexed2_5 +{ + local result = IY & indexed2_5; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_equals_0(); +} +@endif + + +:BLE rel8 is Prefix18=0 & op8=0x2F; rel8 +{ + if ($(Z) | ($(N) ^ $(V))) goto rel8; +} + +#:BLO rel8 is op8=0x25; rel8 see BCS + +:BLS rel8 is Prefix18=0 & op8=0x23; rel8 +{ + if (($(C) | $(Z)) == 1) goto rel8; +} + +:BLT rel8 is Prefix18=0 & op8=0x2D; rel8 +{ + if (($(N) ^ $(V)) ==1) goto rel8; +} + +:BMI rel8 is Prefix18=0 & op8=0x2B; rel8 +{ + if ($(N) == 1) goto rel8; +} + +:BNE rel8 is Prefix18=0 & op8=0x26; rel8 +{ + if ($(Z) == 0) goto rel8; +} + +:BPL rel8 is Prefix18=0 & op8=0x2A; rel8 +{ + if ($(N) == 0) goto rel8; +} + +:BRA rel8 is Prefix18=0 & op8=0x20; rel8 +{ + goto rel8; +} + +:BRCLR opr8a_8, msk8, rel8 is Prefix18=0 & op8=0x4F; opr8a_8; msk8; rel8 +{ + result:1 = opr8a_8 & msk8; + if (result == 0) goto rel8; +} + +:BRCLR opr16a_8, msk8, rel8 is Prefix18=0 & op8=0x1F; opr16a_8; msk8; rel8 +{ + result:1 = opr16a_8 & msk8; + if (result == 0) goto rel8; +} + +:BRCLR indexed1_3, msk8, rel8 is Prefix18=0 & op8=0x0F; indexed1_3; msk8; rel8 +{ + result:1 = indexed1_3 & msk8; + if (result == 0) goto rel8; +} + +# branch never is a two-byte nop +SkipNextInstr: dest is epsilon [ dest = inst_next + 1; ] { export *[RAM]:1 dest; } + +:BRN SkipNextInstr is Prefix18=0 & op8=0x21 & SkipNextInstr +{ + goto SkipNextInstr; +} + +:BRSET opr8a_8, msk8, rel8 is Prefix18=0 & op8=0x4E; opr8a_8; msk8; rel8 +{ + result:1 = ~opr8a_8 & msk8; + if (result != 0) goto rel8; +} + +:BRSET opr16a_8, msk8, rel8 is Prefix18=0 & op8=0x1E; opr16a_8; msk8; rel8 +{ + result:1 = ~opr16a_8 & msk8; + if (result != 0) goto rel8; +} + +:BRSET indexed1_3, msk8, rel8 is Prefix18=0 & op8=0x0E; indexed1_3; msk8; rel8 +{ + result:1 = ~indexed1_3 & msk8; + if (result != 0) goto rel8; +} + +:BSET opr8a_8, msk8 is Prefix18=0 & op8=0x4C; opr8a_8; msk8 +{ + result:1 = opr8a_8 | msk8; + opr8a_8 = result; + $(N) = (result s< 0); + $(Z) = (result == 0); + V_equals_0(); +} + +:BSET opr16a_8, msk8 is Prefix18=0 & op8=0x1C; opr16a_8; msk8 +{ + result:1 = opr16a_8 | msk8; + opr16a_8 = result; + $(N) = (result s< 0); + $(Z) = (result == 0); + V_equals_0(); +} + +:BSET indexed1_3, msk8 is Prefix18=0 & op8=0x0C; indexed1_3; msk8 +{ + result:1 = indexed1_3 | msk8; + indexed1_3 = result; + $(N) = (result s< 0); + $(Z) = (result == 0); + V_equals_0(); +} + +:BSR rel8 is Prefix18=0 & op8=0x07; rel8 +{ + tmp:2 = inst_next; + Push2( tmp ); + + call rel8; +} + +@if defined(HCS12X) +:BTAS opr8a_8, msk8 is Prefix18=1 & (op8=0x35); opr8a_8; msk8 +{ + op1:1 = opr8a_8; + tmp:1 = op1 & msk8; + $(N) = tmp[7,1]; + $(Z) = (tmp == 0); + $(V) = 0; + opr8a_8 = op1 | msk8; +} +@endif + +@if defined(HCS12X) +:BTAS opr16a_8, msk8 is Prefix18=1 & (op8=0x36); opr16a_8; msk8 +{ + op1:1 = opr16a_8; + tmp:1 = op1 & msk8; + $(N) = tmp[7,1]; + $(Z) = (tmp == 0); + $(V) = 0; + opr16a_8 = op1 | msk8; +} +@endif + +@if defined(HCS12X) +:BTAS indexed1_3, msk8 is Prefix18=1 & (op8=0x37); indexed1_3; msk8 +{ + op1:1 = indexed1_3; + tmp:1 = op1 & msk8; + $(N) = tmp[7,1]; + $(Z) = (tmp == 0); + $(V) = 0; + indexed1_3 = op1 | msk8; +} +@endif + + +:BVC rel8 is Prefix18=0 & op8=0x28; rel8 +{ + if ($(V) == 0) goto rel8; +} + +:BVS rel8 is Prefix18=0 & op8=0x29; rel8 +{ + if ($(V) == 1) goto rel8; +} + +@ifdef HCS12 +CallDest: PageDest, imm8 is (imm16; imm8) & PageDest { + PPAGE = imm8; + + build PageDest; + + export PageDest; +} + +:CALL CallDest is Prefix18=0 & op8=0x4A; CallDest +{ + tmp:2 = inst_next; + Push2( tmp ); + + local ppage_tmp:1 = PPAGE; + Push1( PPAGE ); + + build CallDest; + + local dest:$(SIZE) = CallDest; + call [dest]; + + PPAGE = ppage_tmp; +} + +:CALL indexed2_3, page is Prefix18=0 & (op8=0x4B); indexed2_3; page +{ + tmp:2 = inst_next; + Push2( tmp ); + + local ppage_tmp:1 = PPAGE; + Push1( PPAGE ); + PPAGE = page; + + build indexed2_3; + + local dest:$(SIZE); + GetPagedAddr(indexed2_3,dest); + call [dest]; + PPAGE = ppage_tmp; +} + +:CALL indexed0_2 is Prefix18=0 & (op8=0x4B); indexed0_2 +{ + tmp:2 = inst_next; + Push2( tmp ); + + local ppage_tmp:1 = PPAGE; + Push1( PPAGE ); + Load1(PPAGE, indexed0_2 + 2); + + local addr:2; + Load2(addr,indexed0_2); + + local dest:$(SIZE); + GetPagedAddr(addr,dest); + call [dest]; + + PPAGE = ppage_tmp; +} +@endif + +:CBA is (Prefix18=1 & op8=0x17) +{ + tmp:1 = A - B; + $(N) = (tmp s< 0); + $(Z) = (tmp == 0); + V_CMP_flag(A, B); + $(C) = (B > A); +} + +:CLC is Prefix18=0 & op16=0x10FE +{ + $(C) = 0; +} + +:CLI is Prefix18=0 & op16=0x10EF +{ + $(I) = 0; +} + +:CLR opr16a_8 is Prefix18=0 & (op8=0x79); opr16a_8 +{ + opr16a_8 = 0; + $(N) = 0; + $(Z) = 1; + V_equals_0(); + $(C) = 0; +} + +:CLR indexed1_5 is Prefix18=0 & (op8=0x69); indexed1_5 +{ + indexed1_5 = 0; + $(N) = 0; + $(Z) = 1; + V_equals_0(); + $(C) = 0; +} + +:CLRA is Prefix18=0 & op8=0x87 +{ + A = 0; + $(N) = 0; + $(Z) = 1; + V_equals_0(); + $(C) = 0; +} + +:CLRB is Prefix18=0 & op8=0xC7 +{ + B = 0; + $(N) = 0; + $(Z) = 1; + V_equals_0(); + $(C) = 0; +} + +@if defined(HCS12X) +:CLRW opr16a_16 is Prefix18=1 & (op8=0x79); opr16a_16 +{ + opr16a_16 = 0; + $(N) = 0; + $(Z) = 1; + V_equals_0(); + $(C) = 0; +} +@endif + +@if defined(HCS12X) +:CLRW indexed2_5 is Prefix18=1 & (op8=0x69); indexed2_5 +{ + indexed2_5 = 0; + $(N) = 0; + $(Z) = 1; + V_equals_0(); + $(C) = 0; +} +@endif + +@if defined(HCS12X) +:CLRX is Prefix18=1 & op8=0x87 +{ + IX = 0; + $(N) = 0; + $(Z) = 1; + V_equals_0(); + $(C) = 0; +} +@endif + +@if defined(HCS12X) +:CLRY is Prefix18=1 & op8=0xC7 +{ + IY = 0; + $(N) = 0; + $(Z) = 1; + V_equals_0(); + $(C) = 0; +} +@endif + +:CLV is Prefix18=0 & op16=0x10FD +{ + $(V) = 0; +} + +:CMPA iopr8i is Prefix18=0 & (op8=0x81); iopr8i +{ + op1:1 = iopr8i; + tmp:1 = A - op1; + $(N) = (tmp s< 0); + $(Z) = (tmp == 0); + V_CMP_flag(A, op1); + $(C) = (op1 > A); +} + +:CMPA opr8a_8 is Prefix18=0 & (op8=0x91); opr8a_8 +{ + op1:1 = opr8a_8; + tmp:1 = A - op1; + $(N) = (tmp s< 0); + $(Z) = (tmp == 0); + V_CMP_flag(A, op1); + $(C) = (op1 > A); +} + +:CMPA opr16a_8 is Prefix18=0 & (op8=0xB1); opr16a_8 +{ + op1:1 = opr16a_8; + tmp:1 = A - op1; + $(N) = (tmp s< 0); + $(Z) = (tmp == 0); + V_CMP_flag(A, op1); + $(C) = (op1 > A); +} + +:CMPA indexed1_5 is Prefix18=0 & (op8=0xA1); indexed1_5 +{ + op1:1 = indexed1_5; + tmp:1 = A - op1; + $(N) = (tmp s< 0); + $(Z) = (tmp == 0); + V_CMP_flag(A, op1); + $(C) = (op1 > A); +} + +:CMPB iopr8i is Prefix18=0 & (op8=0xC1); iopr8i +{ + op1:1 = iopr8i; + tmp:1 = B - op1; + $(N) = (tmp s< 0); + $(Z) = (tmp == 0); + V_CMP_flag(B, op1); + $(C) = (op1 > B); +} + +:CMPB opr8a_8 is Prefix18=0 & (op8=0xD1); opr8a_8 +{ + op1:1 = opr8a_8; + tmp:1 = B - op1; + $(N) = (tmp s< 0); + $(Z) = (tmp == 0); + V_CMP_flag(B, op1); + $(C) = (op1 > B); +} + +:CMPB opr16a_8 is Prefix18=0 & (op8=0xF1); opr16a_8 +{ + op1:1 = opr16a_8; + tmp:1 = B - op1; + $(N) = (tmp s< 0); + $(Z) = (tmp == 0); + V_CMP_flag(B, op1); + $(C) = (op1 > B); +} + +:CMPB indexed1_5 is Prefix18=0 & (op8=0xE1); indexed1_5 +{ + op1:1 = indexed1_5; + tmp:1 = B - op1; + $(N) = (tmp s< 0); + $(Z) = (tmp == 0); + V_CMP_flag(B, op1); + $(C) = (op1 > B); +} + +:COM opr16a_8 is Prefix18=0 & (op8=0x71); opr16a_8 +{ + tmp:1 = ~opr16a_8; + opr16a_8 = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = 1; + V_equals_0(); +} + +:COM indexed1_5 is Prefix18=0 & (op8=0x61); indexed1_5 +{ + tmp:1 = ~indexed1_5; + indexed1_5 = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = 1; + V_equals_0(); +} + +:COMA is Prefix18=0 & op8=0x41 +{ + A = ~A; + $(Z) = (A == 0); + $(N) = (A s< 0); + $(C) = 1; + V_equals_0(); +} + +:COMB is Prefix18=0 & op8=0x51 +{ + B = ~B; + $(Z) = (B == 0); + $(N) = (B s< 0); + $(C) = 1; + V_equals_0(); +} + +@if defined(HCS12X) +:COMW opr16a_16 is Prefix18=1 & (op8=0x71); opr16a_16 +{ + local tmp = ~opr16a_16; + opr16a_16 = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = 1; + V_equals_0(); +} +@endif + +@if defined(HCS12X) +:COMW indexed2_5 is Prefix18=1 & (op8=0x61); indexed2_5 +{ + local tmp = ~indexed2_5; + indexed2_5 = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = 1; + V_equals_0(); +} +@endif + +@if defined(HCS12X) +:COMX is Prefix18=1 & op8=0x41 +{ + IX = ~IX; + $(Z) = (IX == 0); + $(N) = (IX s< 0); + $(C) = 1; + V_equals_0(); +} +@endif + +@if defined(HCS12X) +:COMY is Prefix18=1 & op8=0x51 +{ + IY = ~IY; + $(Z) = (IY == 0); + $(N) = (IY s< 0); + $(C) = 1; + V_equals_0(); +} +@endif + +:CPD iopr16i is Prefix18=0 & (op8=0x8C); iopr16i +{ + op1:2 = iopr16i; + tmp:2 = D - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > D); + V_CMP_flag(D, op1); +} + +:CPD opr8a_16 is Prefix18=0 & (op8=0x9C); opr8a_16 +{ + op1:2 = opr8a_16; + tmp:2 = D - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > D); + V_CMP_flag(D, op1); +} + +:CPD opr16a_16 is Prefix18=0 & (op8=0xBC); opr16a_16 +{ + op1:2 = opr16a_16; + tmp:2 = D - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > D); + V_CMP_flag(D, op1); +} + +:CPD indexed2_5 is Prefix18=0 & (op8=0xAC); indexed2_5 +{ + op1:2 = indexed2_5; + tmp:2 = D - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > D); + V_CMP_flag(D, op1); +} + +@if defined(HCS12X) +:CPED iopr16i is Prefix18=1 & (op8=0x8C); iopr16i +{ + op1:2 = iopr16i; + tmp:2 = D - (op1 + zext($(C))); + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > D); + V_CMP_flag(D, op1); +} +@endif + +@if defined(HCS12X) +:CPED opr8a_16 is Prefix18=1 & (op8=0x9C); opr8a_16 +{ + op1:2 = opr8a_16; + tmp:2 = D - (op1 + zext($(C))); + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > D); + V_CMP_flag(D, op1); +} +@endif + +@if defined(HCS12X) +:CPED opr16a_16 is Prefix18=1 & (op8=0xBC); opr16a_16 +{ + op1:2 = opr16a_16; + tmp:2 = D - (op1 + zext($(C))); + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > D); + V_CMP_flag(D, op1); +} +@endif + +@if defined(HCS12X) +:CPED indexed2_5 is Prefix18=1 & (op8=0xAC); indexed2_5 +{ + op1:2 = indexed2_5; + tmp:2 = D - (op1 + zext($(C))); + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > D); + V_CMP_flag(D, op1); +} +@endif + +@if defined(HCS12X) +:CPES iopr16i is Prefix18=1 & (op8=0x8F); iopr16i +{ + op1:2 = iopr16i; + tmp:2 = SP - (op1 + zext($(C))); + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > SP); + V_CMP_flag(SP, op1); +} +@endif + +@if defined(HCS12X) +:CPES opr8a_16 is Prefix18=1 & (op8=0x9F); opr8a_16 +{ + op1:2 = opr8a_16; + tmp:2 = SP - (op1 + zext($(C))); + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > SP); + V_CMP_flag(SP, op1); +} +@endif + +@if defined(HCS12X) +:CPES opr16a_16 is Prefix18=1 & (op8=0xBF); opr16a_16 +{ + op1:2 = opr16a_16; + tmp:2 = SP - (op1 + zext($(C))); + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > SP); + V_CMP_flag(SP, op1); +} +@endif + +@if defined(HCS12X) +:CPES indexed2_5 is Prefix18=1 & (op8=0xAF); indexed2_5 +{ + op1:2 = indexed2_5; + tmp:2 = SP - (op1 + zext($(C))); + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > SP); + V_CMP_flag(SP, op1); +} +@endif + +@if defined(HCS12X) +:CPEX iopr16i is Prefix18=1 & (op8=0x8E); iopr16i +{ + op1:2 = iopr16i; + tmp:2 = IX - (op1 + zext($(C))); + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > IX); + V_CMP_flag(IX, op1); +} +@endif + +@if defined(HCS12X) +:CPEX opr8a_16 is Prefix18=1 & (op8=0x9E); opr8a_16 +{ + op1:2 = opr8a_16; + tmp:2 = IX - (op1 + zext($(C))); + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > IX); + V_CMP_flag(IX, op1); +} +@endif + +@if defined(HCS12X) +:CPEX opr16a_16 is Prefix18=1 & (op8=0xBE); opr16a_16 +{ + op1:2 = opr16a_16; + tmp:2 = IX - (op1 + zext($(C))); + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > IX); + V_CMP_flag(IX, op1); +} +@endif + +@if defined(HCS12X) +:CPEX indexed2_5 is Prefix18=1 & (op8=0xAE); indexed2_5 +{ + op1:2 = indexed2_5; + tmp:2 = IX - (op1 + zext($(C))); + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > IX); + V_CMP_flag(IX, op1); +} +@endif + +@if defined(HCS12X) +:CPEY iopr16i is Prefix18=1 & (op8=0x8D); iopr16i +{ + op1:2 = iopr16i; + tmp:2 = IY - (op1 + zext($(C))); + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > IY); + V_CMP_flag(IY, op1); +} +@endif + +@if defined(HCS12X) +:CPEY opr8a_16 is Prefix18=1 & (op8=0x9D); opr8a_16 +{ + op1:2 = opr8a_16; + tmp:2 = IY - (op1 + zext($(C))); + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > IY); + V_CMP_flag(IY, op1); +} +@endif + +@if defined(HCS12X) +:CPEY opr16a_16 is Prefix18=1 & (op8=0xBD); opr16a_16 +{ + op1:2 = opr16a_16; + tmp:2 = IY - (op1 + zext($(C))); + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > IY); + V_CMP_flag(IY, op1); +} +@endif + +@if defined(HCS12X) +:CPEY indexed2_5 is Prefix18=1 & (op8=0xAD); indexed2_5 +{ + op1:2 = indexed2_5; + tmp:2 = IY - (op1 + zext($(C))); + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > IY); + V_CMP_flag(IY, op1); +} +@endif + +SkipNext2Bytes: dest is epsilon [ dest = inst_next + 2; ] { export *[RAM]:1 dest; } + +:CPS loc is Prefix18=0 & (op8=0x8F) & SkipNext2Bytes [ loc = (inst_next & 0xffffff); ] +{ + local addr:$(SIZE) = inst_next; + local op1:2 = *[RAM]:2 addr; + tmp:2 = SP - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > SP); + V_CMP_flag(SP, op1); + goto SkipNext2Bytes; +} + +:CPS opr8a_16 is Prefix18=0 & (op8=0x9F); opr8a_16 +{ + op1:2 = opr8a_16; + tmp:2 = SP - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > SP); + V_CMP_flag(SP, op1); +} + +:CPS loc is Prefix18=0 & (op8=0xBF) & SkipNext2Bytes [ loc = (inst_next & 0xffffff); ] +{ + local addr:$(SIZE) = inst_next; + local op1:2 = *[RAM]:2 addr; + Load2(op1, op1); + tmp:2 = SP - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > SP); + V_CMP_flag(SP, op1); + goto SkipNext2Bytes; +} + +:CPS indexed2_5 is Prefix18=0 & (op8=0xAF); indexed2_5 +{ + op1:2 = indexed2_5; + tmp:2 = SP - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > SP); + V_CMP_flag(SP, op1); +} + +:CPX iopr16i is Prefix18=0 & (op8=0x8E); iopr16i +{ + op1:2 = iopr16i; + tmp:2 = IX - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > IX); + V_CMP_flag(IX, op1); +} + +:CPX opr8a_16 is Prefix18=0 & (op8=0x9E); opr8a_16 +{ + op1:2 = opr8a_16; + tmp:2 = IX - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > IX); + V_CMP_flag(IX, op1); +} + +:CPX opr16a_16 is Prefix18=0 & (op8=0xBE); opr16a_16 +{ + op1:2 = opr16a_16; + tmp:2 = IX - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > IX); + V_CMP_flag(IX, op1); +} + +:CPX indexed2_5 is Prefix18=0 & (op8=0xAE); indexed2_5 +{ + op1:2 = indexed2_5; + tmp:2 = IX - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > IX); + V_CMP_flag(IX, op1); +} + +:CPY iopr16i is Prefix18=0 & (op8=0x8D); iopr16i +{ + op1:2 = iopr16i; + tmp:2 = IY - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > IY); + V_CMP_flag(IY, op1); +} + +:CPY opr8a_16 is Prefix18=0 & (op8=0x9D); opr8a_16 +{ + op1:2 = opr8a_16; + tmp:2 = IY - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > IY); + V_CMP_flag(IY, op1); +} + +:CPY opr16a_16 is Prefix18=0 & (op8=0xBD); opr16a_16 +{ + op1:2 = opr16a_16; + tmp:2 = IY - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > IY); + V_CMP_flag(IY, op1); +} + +:CPY indexed2_5 is Prefix18=0 & (op8=0xAD); indexed2_5 +{ + op1:2 = indexed2_5; + tmp:2 = IY - op1; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + $(C) = (op1 > IY); + V_CMP_flag(IY, op1); +} + +:DAA is Prefix18=1 & op8=0x07 +{ + A = decimalAdjustAccumulator(A, $(C), $(H)); + $(C) = decimalAdjustCarry(A, $(C), $(H)); + $(Z) = (A == 0); + $(N) = (A s< 0); + #V is undefined +} + +:DBEQ byte9_8, rel9 is Prefix18=0 & op8=0x04; op15_13=0x0 & size10_10=0 & byte9_8 & rel9 +{ + byte9_8 = byte9_8 - 1; + if (byte9_8 == 0) goto rel9; +} + +:DBEQ word9_8, rel9 is Prefix18=0 & op8=0x04; op15_13=0x0 & size10_10=1 & word9_8 & rel9 +{ + word9_8 = word9_8 - 1; + if (word9_8 == 0) goto rel9; +} + +:DBNE byte9_8, rel9 is Prefix18=0 & op8=0x04; op15_13=0x1 & size10_10=0 & byte9_8 & rel9 +{ + byte9_8 = byte9_8 - 1; + if (byte9_8 != 0) goto rel9; +} + +:DBNE word9_8, rel9 is Prefix18=0 & op8=0x04; op15_13=0x1 & size10_10=1 & word9_8 & rel9 +{ + word9_8 = word9_8 - 1; + if (word9_8 != 0) goto rel9; +} + +:DEC opr16a_8 is Prefix18=0 & (op8=0x73); opr16a_8 +{ + tmp:1 = opr16a_8; + result:1 = tmp - 1; + opr16a_8 = result; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_DEC_flag(tmp); +} + +:DEC indexed1_5 is Prefix18=0 & (op8=0x63); indexed1_5 +{ + tmp:1 = indexed1_5; + result:1 = tmp - 1; + indexed1_5 = result; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_DEC_flag(tmp); +} + +:DECA is Prefix18=0 & op8=0x43 +{ + tmp:1 = A; + A = tmp - 1; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_DEC_flag(tmp); +} + +:DECB is Prefix18=0 & op8=0x53 +{ + tmp:1 = B; + B = tmp - 1; + $(Z) = (B == 0); + $(N) = (B s< 0); + V_DEC_flag(tmp); +} + +@if defined(HCS12X) +:DECW opr16a_16 is Prefix18=1 & (op8=0x73); opr16a_16 +{ + local tmp = opr16a_16; + local result = tmp - 1; + opr16a_16 = result; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_DEC_flag2(tmp); +} +@endif + +@if defined(HCS12X) +:DECW indexed2_5 is Prefix18=1 & (op8=0x63); indexed2_5 +{ + local tmp = indexed2_5; + local result = tmp - 1; + indexed2_5 = result; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_DEC_flag2(tmp); +} +@endif + +@if defined(HCS12X) +:DECX is Prefix18=1 & op8=0x43 +{ + local tmp = IX; + IX = tmp - 1; + $(Z) = (IX == 0); + $(N) = (IX s< 0); + V_DEC_flag2(tmp); +} +@endif + +@if defined(HCS12X) +:DECY is Prefix18=1 & op8=0x53 +{ + local tmp = IY; + IY = tmp - 1; + $(Z) = (IY == 0); + $(N) = (IY s< 0); + V_DEC_flag2(tmp); +} +@endif + +:DES is Prefix18=0 & op16=0x1B9F +{ + SP = SP - 1; +} + +:DEX is Prefix18=0 & op8=0x09 +{ + IX = IX - 1; + $(Z) = (IX == 0); +} + +:DEY is Prefix18=0 & op8=0x03 +{ + IY = IY - 1; + $(Z) = (IY == 0); +} + +:EDIV is Prefix18=0 & op8=0x11 +{ + tmp:4 = (zext(IY) << 16) | (zext(D)); + resultQ:4 = tmp / zext(IX); + resultR:4 = tmp % zext(IX); + IY = resultQ:2; + D = resultR:2; + $(N) = (IY s< 0); + $(Z) = (IY == 0); + $(V) = (resultQ > 0x0000FFFF); + $(C) = (IX == 0); +} + +:EDIVS is Prefix18=1 & op8=0x14 +{ + tmp:4 = (zext(IY) << 16) | (zext(D)); + resultQ:4 = tmp s/ sext(IX); + resultR:4 = tmp s% sext(IX); + IY = resultQ:2; + D = resultR:2; + $(N) = (IY s< 0); + $(Z) = (IY == 0); + $(V) = (resultQ s> 0x00007FFF) | (resultQ s< 0x00008000); + $(C) = (IX == 0); +} + +:EMACS opr16a is Prefix18=1 & op8=0x12; opr16a +{ + local valx:2 = 0; + local valy:2 = 0; + Load2(valx,IX); + Load2(valy,IY); + result:4 = sext(valx) * sext(valy); + Store(opr16a, result); + $(N) = (result s< 0); + $(Z) = (result == 0); + $(V) = (result s> 0x000000007FFFFFFF) | (result s< 0x0000000080000000); + $(C) = (result > 0x00000000FFFFFFFF); +} + +:EMAXD indexed2_5 is Prefix18=1 & op8=0x1A; indexed2_5 +{ + result:4 = zext(D) - zext(indexed2_5); + if (D > indexed2_5) goto ; + D = indexed2_5; + + + $(N) = (result:2 s< 0); + $(Z) = (result:2 == 0); + $(V) = (result s> 0x00007FFF) | (result s< 0x00008000); + $(C) = (result > 0x0000FFFF); +} + +:EMAXM indexed2_5 is Prefix18=1 & op8=0x1E; indexed2_5 +{ + result:4 = zext(D) - zext(indexed2_5); + if (D > indexed2_5) goto ; + indexed2_5 = D; + + + $(N) = (result:2 s< 0); + $(Z) = (result:2 == 0); + $(V) = (result s> 0x00007FFF) | (result s< 0x00008000); + $(C) = (result > 0x0000FFFF); +} + +:EMIND indexed2_5 is Prefix18=1 & op8=0x1B; indexed2_5 +{ + result:4 = zext(D) - zext(indexed2_5); + if (D < indexed2_5) goto ; + D = indexed2_5; + + + $(N) = (result:2 s< 0); + $(Z) = (result:2 == 0); + $(V) = (result s> 0x00007FFF) | (result s< 0x00008000); + $(C) = (result > 0x0000FFFF); +} + +:EMINM indexed2_5 is Prefix18=1 & op8=0x1F; indexed2_5 +{ + result:4 = zext(D) - zext(indexed2_5); + if (D < indexed2_5) goto ; + indexed2_5 = D; + + + $(N) = (result:2 s< 0); + $(Z) = (result:2 == 0); + $(V) = (result s> 0x00007FFF) | (result s< 0x00008000); + $(C) = (result > 0x0000FFFF); +} + +:EMUL is Prefix18=0 & op8=0x13 +{ + result:4 = zext(D) * zext(IY); + IY = result(2); + D = result:2; + $(N) = result[31,1]; + $(Z) = (result == 0); + $(C) = result[15,1]; +} + +:EMULS is Prefix18=1 & op8=0x13 +{ + result:4 = sext(D) * sext(IY); + IY = result(2); + D = result:2; + $(N) = result[31,1]; + $(Z) = (result == 0); + $(C) = result[15,1]; +} + +:EORA iopr8i is Prefix18=0 & (op8=0x88); iopr8i +{ + op1:1 = iopr8i; + A = A ^ op1; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} + +:EORA opr8a_8 is Prefix18=0 & (op8=0x98); opr8a_8 +{ + op1:1 = opr8a_8; + A = A ^ op1; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} + +:EORA opr16a_8 is Prefix18=0 & (op8=0xB8); opr16a_8 +{ + op1:1 = opr16a_8; + A = A ^ op1; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} + +:EORA indexed1_5 is Prefix18=0 & (op8=0xA8); indexed1_5 +{ + op1:1 = indexed1_5; + A = A ^ op1; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} + +:EORB iopr8i is Prefix18=0 & (op8=0xC8); iopr8i +{ + op1:1 = iopr8i; + B = B ^ op1; + $(Z) = (B == 0); + $(N) = (B s< 0); + V_equals_0(); +} + +:EORB opr8a_8 is Prefix18=0 & (op8=0xD8); opr8a_8 +{ + op1:1 = opr8a_8; + B = B ^ op1; + $(Z) = (B == 0); + $(N) = (B s< 0); + V_equals_0(); +} + +:EORB opr16a_8 is Prefix18=0 & (op8=0xF8); opr16a_8 +{ + op1:1 = opr16a_8; + B = B ^ op1; + $(Z) = (B == 0); + $(N) = (B s< 0); + V_equals_0(); +} + +:EORB indexed1_5 is Prefix18=0 & (op8=0xE8); indexed1_5 +{ + op1:1 = indexed1_5; + B = B ^ op1; + $(Z) = (B == 0); + $(N) = (B s< 0); + V_equals_0(); +} + +@if defined(HCS12X) +:EORX iopr16i is Prefix18=1 & (op8=0x88); iopr16i +{ + local op1 = iopr16i; + IX = IX ^ op1; + $(Z) = (IX == 0); + $(N) = (IX s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS12X) +:EORX opr8a_16 is Prefix18=1 & (op8=0x98); opr8a_16 +{ + local op1 = opr8a_16; + IX = IX ^ op1; + $(Z) = (IX == 0); + $(N) = (IX s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS12X) +:EORX opr16a_16 is Prefix18=1 & (op8=0xB8); opr16a_16 +{ + local op1 = opr16a_16; + IX = IX ^ op1; + $(Z) = (IX == 0); + $(N) = (IX s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS12X) +:EORX indexed2_5 is Prefix18=1 & (op8=0xA8); indexed2_5 +{ + local op1 = indexed2_5; + IX = IX ^ op1; + $(Z) = (IX == 0); + $(N) = (IX s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS12X) +:EORY iopr16i is Prefix18=1 & (op8=0xC8); iopr16i +{ + local op1 = iopr16i; + IY = IY ^ op1; + $(Z) = (IY == 0); + $(N) = (IY s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS12X) +:EORY opr8a_16 is Prefix18=1 & (op8=0xD8); opr8a_16 +{ + local op1 = opr8a_16; + IY = IY ^ op1; + $(Z) = (IY == 0); + $(N) = (IY s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS12X) +:EORY opr16a_16 is Prefix18=1 & (op8=0xF8); opr16a_16 +{ + local op1 = opr16a_16; + IY = IY ^ op1; + $(Z) = (IY == 0); + $(N) = (IY s< 0); + V_equals_0(); +} +@endif + +@if defined(HCS12X) +:EORY indexed2_5 is Prefix18=1 & (op8=0xE8); indexed2_5 +{ + local op1 = indexed2_5; + IY = IY ^ op1; + $(Z) = (IY == 0); + $(N) = (IY s< 0); + V_equals_0(); +} +@endif + +:ETBL indexed2_1 is Prefix18=1 & op8=0x3F; indexed2_1 +{ + D = ETBL( indexed2_1, B ); + $(N) = (D s< 0); + $(Z) = (D == 0); + $(C) = ETBL_Cflag( indexed2_1, B ); +} + +# this case 'C0' or 'C8', does not display similarly to other members of either its row or column +:EXG D, A is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0x0 & ( columns7_4=0xC ) ) | + + ( rows3_0=0x8 & ( columns7_4=0xC ) ) + ) & + D & A +{ + tmp:1 = B; + B = A; + A = tmp; +} + +# this case 'C1' or 'C9', does not work similarly to other members of either its row or column +:EXG D, B is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0x1 & ( columns7_4=0xC ) ) | + + ( rows3_0=0x9 & ( columns7_4=0xC ) ) + ) & + D & B +{ + B = B; + A = 0xFF; +} + +# this case '84' or '8C', does not work similarly to other members of either its row or column +:EXG A, D is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0x4 & ( columns7_4=0x8 ) ) | + + ( rows3_0=0xC & ( columns7_4=0x8 ) ) + ) & + A & D +{ + D = zext(A); +} + +# this case '94' or '9C', does not work similarly to other members of either its row or column +:EXG B, D is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0x4 & ( columns7_4=0x9 ) ) | + + ( rows3_0=0xC & ( columns7_4=0x9 ) ) + ) & + B & D +{ + D = zext(B); +} + +# this case 'A8', does not work the same as 'A0' +:EXG CCRH, A is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0x8 & ( columns7_4=0xA ) ) + ) & + CCRH & A +{ + tmp:1 = CCRH; + CCRH = A; + A = tmp; +} + +# this case '8A', does not work the same as '82' +:EXG A, CCRH is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0xA & ( columns7_4=0x8 ) ) + ) & + A & CCRH +{ + tmp:1 = A; + A = CCRH; + CCRH = tmp; +} + +# this case 'AA', does not display the same as 'A2' +:EXG CCRW, "CCRW" is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0xA & ( columns7_4=0xA ) ) + ) & + CCRW +{ + CCRW = CCRW; +} + +:EXG bytes_ABCl_6_4, bytes_ABCl_2_0 is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0x0 & ( columns7_4=0x8 | columns7_4=0x9 ) ) | + ( rows3_0=0x1 & ( columns7_4=0x8 | columns7_4=0x9 ) ) | + + ( rows3_0=0x8 & ( columns7_4=0x8 | columns7_4=0x9 ) ) | + ( rows3_0=0x9 & ( columns7_4=0x8 | columns7_4=0x9 ) ) + ) & + bytes_ABCl_6_4 & bytes_ABCl_2_0 +{ + tmp:1 = bytes_ABCl_2_0; + bytes_ABCl_2_0 = bytes_ABCl_6_4; + bytes_ABCl_6_4 = tmp; +} + +:EXG bytes_ABCl_6_4, CCR is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0x2 & ( columns7_4=0x8 | columns7_4=0x9 ) ) | + + ( rows3_0=0xA & ( columns7_4=0x9 ) ) + ) & + bytes_ABCl_6_4 & CCR +{ + tmp:1 = bytes_ABCl_6_4; + bytes_ABCl_6_4 = CCR; + setCCR( tmp ); +} + +:EXG CCR, bytes_ABCl_2_0 is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0x0 & ( columns7_4=0xA ) ) | + ( rows3_0=0x1 & ( columns7_4=0xA ) ) | + ( rows3_0=0x2 & ( columns7_4=0xA ) ) | + + ( rows3_0=0x9 & ( columns7_4=0xA ) ) + ) & + CCR & bytes_ABCl_2_0 +{ + tmp:1 = bytes_ABCl_2_0; + bytes_ABCl_2_0 = CCR; + setCCR( tmp ); +} + +:EXG bytes_T3l_XlYlSl_6_4, A is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0x0 & ( columns7_4=0xB | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) + ) & + bytes_T3l_XlYlSl_6_4 & words_T3_XYS_6_4 & A +{ + tmp:2 = zext(A); + A = bytes_T3l_XlYlSl_6_4; + words_T3_XYS_6_4 = tmp; +} + +:EXG bytes_T3h_XhYhSh_6_4, A is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0x8 & ( columns7_4=0xB | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) + ) & + bytes_T3h_XhYhSh_6_4 & words_T3_XYS_6_4 & A +{ + tmp:2 = zext(A); + A = bytes_T3h_XhYhSh_6_4; + words_T3_XYS_6_4 = tmp; +} + +:EXG bytes_T3l_XlYlSl_6_4, B is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0x1 & ( columns7_4=0xB | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) + ) & + bytes_T3l_XlYlSl_6_4 & words_T3_XYS_6_4 & B +{ + tmp:2 = 0xFF00 | zext(B); + B = bytes_T3l_XlYlSl_6_4; + words_T3_XYS_6_4 = tmp; +} + +:EXG bytes_T3l_XlYlSl_6_4, B is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0x9 & ( columns7_4=0xB | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) + ) & + bytes_T3l_XlYlSl_6_4 & B +{ + tmp:1 = B; + B = bytes_T3l_XlYlSl_6_4; + bytes_T3l_XlYlSl_6_4 = tmp; +} + +:EXG bytes_T3lDlXlYlSl_6_4, CCR is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0x2 & ( columns7_4=0xB | columns7_4=0xC | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) + ) & + bytes_T3lDlXlYlSl_6_4 & words_T3DXYS_6_4 & CCR +{ + tmp:2 = 0xFF00 | zext(CCR); + # when CCR is the destination, cannot set the X bit unless it is already set in CCR + setCCR( bytes_T3lDlXlYlSl_6_4 ); + words_T3DXYS_6_4 = tmp; +} + +:EXG words_T3DXYS_6_4, CCRW is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0xA & ( columns7_4=0xB | columns7_4=0xC | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) + ) & + words_T3DXYS_6_4 & CCRW +{ + tmp:2 = CCRW; + setCCRW( words_T3DXYS_6_4 ); + words_T3DXYS_6_4 = tmp; +} + +# this case 'CB', does not work similarly to other members of either its row or column +:EXG D, TMP1 is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0xB & ( columns7_4=0xC ) ) + ) & + D & TMP1 +{ + tmp:2 = D; + D = TMP1; + TMP1 = tmp; +} + +# this case 'BC', does not work similarly to other members of either its row or column +:EXG TMP1, D is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0xC & ( columns7_4=0xB ) ) + ) & + TMP1 & D +{ + tmp:2 = TMP1; + TMP1 = D; + D = tmp; +} + +:EXG words_T3DXYS_6_4, words_T2DXYS_2_0 is Prefix18=0 & ( op8=0xB7 ); + ( +# Case "C5" is handled by XGDX +# Case "C6" is handled by XGDY + ( rows3_0=0x3 & ( columns7_4=0xB | columns7_4=0xC | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) | + ( rows3_0=0x4 & ( columns7_4=0xB | columns7_4=0xC | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) | + ( rows3_0=0x5 & ( columns7_4=0xB | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) | + ( rows3_0=0x6 & ( columns7_4=0xB | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) | + ( rows3_0=0x7 & ( columns7_4=0xB | columns7_4=0xC | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) | + + ( rows3_0=0xB & ( columns7_4=0xB | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) | + ( rows3_0=0xC & ( columns7_4=0xC | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) | + ( rows3_0=0xD & ( columns7_4=0xB | columns7_4=0xC | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) | + ( rows3_0=0xE & ( columns7_4=0xB | columns7_4=0xC | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) | + ( rows3_0=0xF & ( columns7_4=0xB | columns7_4=0xC | columns7_4=0xD | columns7_4=0xE | columns7_4=0xF ) ) + ) & + words_T3DXYS_6_4 & words_T2DXYS_2_0 +{ + tmp:2 = words_T3DXYS_6_4; + words_T3DXYS_6_4 = words_T2DXYS_2_0; + words_T2DXYS_2_0 = tmp; +} + +:EXG bytes_ABCl_6_4, words_T2DXYS_2_0 is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0x3 & ( columns7_4=0x8 | columns7_4=0x9 ) ) | + + ( rows3_0=0x5 & ( columns7_4=0x8 | columns7_4=0x9 ) ) | + ( rows3_0=0x6 & ( columns7_4=0x8 | columns7_4=0x9 ) ) | + ( rows3_0=0x7 & ( columns7_4=0x8 | columns7_4=0x9 ) ) + ) & + bytes_ABCl_6_4 & words_T2DXYS_2_0 & bytes_T2lDlXlYlSl_2_0 +{ + tmp:2 = zext(bytes_ABCl_6_4); + bytes_ABCl_6_4 = bytes_T2lDlXlYlSl_2_0; + words_T2DXYS_2_0 = tmp; +} + +:EXG bytes_ABCl_6_4, bytes_T2hDhXhYhSh_2_0 is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0xB & ( columns7_4=0x8 ) ) | + + ( rows3_0=0xD & ( columns7_4=0x8 ) ) | + ( rows3_0=0xE & ( columns7_4=0x8 ) ) | + ( rows3_0=0xF & ( columns7_4=0x8 ) ) + ) & + bytes_ABCl_6_4 & bytes_T2hDhXhYhSh_2_0 +{ + tmp:1 = bytes_ABCl_6_4; + bytes_ABCl_6_4 = bytes_T2hDhXhYhSh_2_0; + bytes_T2hDhXhYhSh_2_0 = tmp; +} + +# only column 9 with rows B, (skip C), D, E, and F +:EXG bytes_ABCl_6_4, bytes_T2lDlXlYlSl_2_0 is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0xB & ( columns7_4=0x9 ) ) | + + ( rows3_0=0xD & ( columns7_4=0x9 ) ) | + ( rows3_0=0xE & ( columns7_4=0x9 ) ) | + ( rows3_0=0xF & ( columns7_4=0x9 ) ) + ) & + bytes_ABCl_6_4 & bytes_T2lDlXlYlSl_2_0 +{ + tmp:1 = bytes_ABCl_6_4; + bytes_ABCl_6_4 = bytes_T2lDlXlYlSl_2_0; + bytes_T2lDlXlYlSl_2_0 = tmp; +} + +:EXG CCR, words_T2DXYS_2_0 is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0x3 & ( columns7_4=0xA ) ) | + ( rows3_0=0x4 & ( columns7_4=0xA ) ) | + ( rows3_0=0x5 & ( columns7_4=0xA ) ) | + ( rows3_0=0x6 & ( columns7_4=0xA ) ) | + ( rows3_0=0x7 & ( columns7_4=0xA ) ) + ) & + CCR & words_T2DXYS_2_0 & bytes_T2lDlXlYlSl_2_0 +{ + tmp:2 = zext(CCR); + setCCR( bytes_T2lDlXlYlSl_2_0 ); + words_T2DXYS_2_0 = tmp; +} + +:EXG CCRW, words_T2DXYS_2_0 is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0xB & ( columns7_4=0xA ) ) | + ( rows3_0=0xC & ( columns7_4=0xA ) ) | + ( rows3_0=0xD & ( columns7_4=0xA ) ) | + ( rows3_0=0xE & ( columns7_4=0xA ) ) | + ( rows3_0=0xF & ( columns7_4=0xA ) ) + ) & + CCRW & words_T2DXYS_2_0 +{ + tmp:2 = CCRW; + setCCRW( words_T2DXYS_2_0 ); + words_T2DXYS_2_0 = tmp; +} + +:FDIV is Prefix18=1 & op8=0x11 +{ + $(V) = (IX <= D); + $(C) = (IX == 0); + tmp:4 = (zext(D) << 16); + resultQ:4 = tmp / zext(IX); + resultR:4 = tmp % zext(IX); + IX = resultQ:2; + D = resultR:2; + $(Z) = (IX == 0); +} + +#:GLDAA is op16=0x1896 See GPAGE extended LDAA +#:GLDAA is op16=0x18B6 See GPAGE extended LDAA +#:GLDAA is op16=0x18A6 See GPAGE extended LDAA + +#:GLDAB is op16=0x18D6 See GPAGE extended LDAB +#:GLDAB is op16=0x18F6 See GPAGE extended LDAB +#:GLDAB is op16=0x18E6 See GPAGE extended LDAB + +#:GLDD is op16=0x18DC See GPAGE extended LDD +#:GLDD is op16=0x18FC See GPAGE extended LDD +#:GLDD is op16=0x18EC See GPAGE extended LDD + +#:GLDS is op16=0x18DF See GPAGE extended LDS +#:GLDS is op16=0x18FF See GPAGE extended LDS +#:GLDS is op16=0x18EF See GPAGE extended LDS + +#:GLDX is op16=0x18DE See GPAGE extended LDX +#:GLDX is op16=0x18FE See GPAGE extended LDX +#:GLDX is op16=0x18EE See GPAGE extended LDX + +#:GLDY is op16=0x18DD See GPAGE extended LDY +#:GLDY is op16=0x18FD See GPAGE extended LDY +#:GLDY is op16=0x18ED See GPAGE extended LDY + +#:GSTAA is op16=0x185A See GPAGE extended STAA +#:GSTAA is op16=0x187A See GPAGE extended STAA +#:GSTAA is op16=0x186A See GPAGE extended STAA + +#:GSTAB is op16=0x185B See GPAGE extended STAB +#:GSTAB is op16=0x187B See GPAGE extended STAB +#:GSTAB is op16=0x186B See GPAGE extended STAB + +#:GSTD is op16=0x185C See GPAGE extended STD +#:GSTD is op16=0x187C See GPAGE extended STD +#:GSTD is op16=0x186C See GPAGE extended STD + +#:GSTS is op16=0x185F See GPAGE extended STS +#:GSTS is op16=0x187F See GPAGE extended STS +#:GSTS is op16=0x186F See GPAGE extended STS + +#:GSTX is op16=0x185E See GPAGE extended STX +#:GSTX is op16=0x187E See GPAGE extended STX +#:GSTX is op16=0x186E See GPAGE extended STX + +#:GSTY is op16=0x185D See GPAGE extended STY +#:GSTY is op16=0x187D See GPAGE extended STY +#:GSTY is op16=0x186D See GPAGE extended STY + + +:IBEQ byte9_8, rel9 is Prefix18=0 & op8=0x04; op15_13=0x4 & size10_10=0 & byte9_8 & rel9 +{ + byte9_8 = byte9_8 + 1; + if (byte9_8 == 0) goto rel9; +} + +:IBEQ word9_8, rel9 is Prefix18=0 & op8=0x04; op15_13=0x4 & size10_10=1 & word9_8 & rel9 +{ + word9_8 = word9_8 + 1; + if (word9_8 == 0) goto rel9; +} + +:IBNE byte9_8, rel9 is Prefix18=0 & op8=0x04; op15_13=0x5 & size10_10=0 & byte9_8 & rel9 +{ + byte9_8 = byte9_8 + 1; + if (byte9_8 != 0) goto rel9; +} + +:IBNE word9_8, rel9 is Prefix18=0 & op8=0x04; op15_13=0x5 & size10_10=1 & word9_8 & rel9 +{ + word9_8 = word9_8 + 1; + if (word9_8 != 0) goto rel9; +} + +:IDIV is Prefix18=1 & op8=0x10 +{ + $(C) = (IX == 0); + resultQ:2 = D / IX; + resultR:2 = D % IX; + IX = resultQ; + D = resultR; + $(Z) = (IX == 0); + $(V) = 0; +} + +:IDIVS is Prefix18=1 & op8=0x15 +{ + $(C) = (IX == 0); + resultQ:4 = sext(D) s/ sext(IX); + resultR:4 = sext(D) s% sext(IX); + IX = resultQ:2; + D = resultR:2; + $(N) = (IX s< 0); + $(Z) = (IX == 0); + $(V) = (resultQ s> 0x00007FFF) | (resultQ s< 0x00008000); +} + +:INC opr16a_8 is Prefix18=0 & (op8=0x72); opr16a_8 +{ + tmp:1 = opr16a_8; + result:1 = tmp + 1; + opr16a_8 = result; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_INC_flag(tmp); +} + +:INC indexed1_5 is Prefix18=0 & (op8=0x62); indexed1_5 +{ + tmp:1 = indexed1_5; + result:1 = tmp + 1; + indexed1_5 = result; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_INC_flag(tmp); +} + +:INCA is Prefix18=0 & op8=0x42 +{ + tmp:1 = A; + A = tmp + 1; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_INC_flag(tmp); +} + +:INCB is Prefix18=0 & op8=0x52 +{ + tmp:1 = B; + B = tmp + 1; + $(Z) = (B == 0); + $(N) = (B s< 0); + V_INC_flag(tmp); +} + +@if defined(HCS12X) +:INCW opr16a_16 is Prefix18=1 & (op8=0x72); opr16a_16 +{ + tmp:2 = opr16a_16; + result:2 = tmp + 1; + opr16a_16 = result; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_INC_flag2(tmp); +} +@endif + +@if defined(HCS12X) +:INCW indexed2_5 is Prefix18=1 & (op8=0x62); indexed2_5 +{ + tmp:2 = indexed2_5; + result:2 = tmp + 1; + indexed2_5 = result; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_INC_flag2(tmp); +} +@endif + +@if defined(HCS12X) +:INCX is Prefix18=1 & op8=0x42 +{ + local tmp = IX; + IX = tmp + 1; + $(Z) = (IX == 0); + $(N) = (IX s< 0); + V_INC_flag2(tmp); +} +@endif + +@if defined(HCS12X) +:INCY is Prefix18=1 & op8=0x52 +{ + local tmp = IY; + IY = tmp + 1; + $(Z) = (IY == 0); + $(N) = (IY s< 0); + V_INC_flag2(tmp); +} +@endif + +:INS is Prefix18=0 & op16=0x1B81 +{ + SP = SP + 1; +} + +:INX is Prefix18=0 & op8=0x08 +{ + IX = IX + 1; + $(Z) = (IX == 0); +} + +:INY is Prefix18=0 & op8=0x02 +{ + IY = IY + 1; + $(Z) = (IY == 0); +} + +:JMP opr16a is Prefix18=0 & (op8=0x06); opr16a +{ + goto [opr16a]; +} + +:JMP indexedA_5 is Prefix18=0 & (op8=0x05); indexedA_5 +{ + goto [indexedA_5]; +} + +:JSR opr8a is Prefix18=0 & (op8=0x17); opr8a +{ + tmp:2 = inst_next; + Push2( tmp ); + + call [opr8a]; +} + +:JSR opr16a is Prefix18=0 & (op8=0x16); opr16a +{ + tmp:2 = inst_next; + Push2( tmp ); + + call [opr16a]; +} + +:JSR indexedA_5 is Prefix18=0 & (op8=0x15); indexedA_5 +{ + tmp:2 = inst_next; + Push2( tmp ); + + call [indexedA_5]; +} + +:LBCC rel16 is Prefix18=1 & op8=0x24; rel16 +{ + if ($(C) == 0) goto rel16; +} + +:LBCS rel16 is Prefix18=1 & op8=0x25; rel16 +{ + if ($(C) == 1) goto rel16; +} + +:LBEQ rel16 is Prefix18=1 & op8=0x27; rel16 +{ + if ($(Z) == 1) goto rel16; +} + +:LBGE rel16 is Prefix18=1 & op8=0x2C; rel16 +{ + if (($(N) ^ $(V)) == 1) goto rel16; +} + +:LBGT rel16 is Prefix18=1 & op8=0x2E; rel16 +{ + if (($(Z) | ($(N) ^ $(V))) == 0) goto rel16; +} + +:LBHI rel16 is Prefix18=1 & op8=0x22; rel16 +{ + if (($(C) | $(Z)) == 0) goto rel16; +} + +#:LBHS rel16 is Prefix18=1 & op8=0x24; rel16 See LBCC + +:LBLE rel16 is Prefix18=1 & op8=0x2F; rel16 +{ + if ($(Z) | ($(N) ^ $(V))) goto rel16; +} + +#:LBLO rel16 is Prefix18=1 & op8=0x25; rel16 see LBCS + +:LBLS rel16 is Prefix18=1 & op8=0x23; rel16 +{ + if (($(C) | $(Z)) == 1) goto rel16; +} + +:LBLT rel16 is Prefix18=1 & op8=0x2D; rel16 +{ + if (($(N) ^ $(V)) == 1) goto rel16; +} + +:LBMI rel16 is Prefix18=1 & op8=0x2B; rel16 +{ + if ($(N) == 1) goto rel16; +} + +:LBNE rel16 is Prefix18=1 & op8=0x26; rel16 +{ + if ($(Z) == 0) goto rel16; +} + +:LBPL rel16 is Prefix18=1 & op8=0x2A; rel16 +{ + if ($(N) == 0) goto rel16; +} + +:LBRA rel16 is Prefix18=1 & op8=0x20; rel16 +{ + goto rel16; +} + +# branch never is a four-byte nop +:LBRN rel16 is Prefix18=1 & op8=0x21; rel16 +{ +} + +:LBVC rel16 is Prefix18=1 & op8=0x28; rel16 +{ + if ($(V) == 0) goto rel16; +} + +:LBVS rel16 is Prefix18=1 & op8=0x29; rel16 +{ + if ($(V) == 1) goto rel16; +} + +:LDAA iopr8i is Prefix18=0 & (op8=0x86); iopr8i +{ + A = iopr8i; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} + +GPaged: "G" is Prefix18=1 [ UseGPAGE=1; ] {} +GPaged: is Prefix18=0 [ UseGPAGE=0; ] {} + +:^GPaged^"LDAA" opr8a_8 is GPaged & (op8=0x96); opr8a_8 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + A = opr8a_8; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} + +:^GPaged^"LDAA" opr16a_8 is GPaged & (op8=0xB6); opr16a_8 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + A = opr16a_8; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} + +:^GPaged^"LDAA" indexed1_5 is GPaged & (op8=0xA6); indexed1_5 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + A = indexed1_5; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} + +:LDAB iopr8i is Prefix18=0 & (op8=0xC6); iopr8i +{ + B = iopr8i; + $(Z) = (B == 0); + $(N) = (B s< 0); + V_equals_0(); +} + +:^GPaged^"LDAB" opr8a_8 is GPaged & (op8=0xD6); opr8a_8 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + B = opr8a_8; + $(Z) = (B == 0); + $(N) = (B s< 0); + V_equals_0(); +} + +:^GPaged^"LDAB" opr16a_8 is GPaged & (op8=0xF6); opr16a_8 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + B = opr16a_8; + $(Z) = (B == 0); + $(N) = (B s< 0); + V_equals_0(); +} + +:^GPaged^"LDAB" indexed1_5 is GPaged & (op8=0xE6); indexed1_5 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + B = indexed1_5; + $(Z) = (B == 0); + $(N) = (B s< 0); + V_equals_0(); +} + +:LDD iopr16i is Prefix18=0 & (op8=0xCC); iopr16i +{ + D = iopr16i; + $(Z) = (D == 0); + $(N) = (D s< 0); + V_equals_0(); +} + +:^GPaged^"LDD" opr8a_16 is GPaged & (op8=0xDC); opr8a_16 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + D = opr8a_16; + $(Z) = (D == 0); + $(N) = (D s< 0); + V_equals_0(); +} + +:^GPaged^"LDD" opr16a_16 is GPaged & (op8=0xFC); opr16a_16 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + D = opr16a_16; + $(Z) = (D == 0); + $(N) = (D s< 0); + V_equals_0(); +} + +:^GPaged^"LDD" indexed2_5 is GPaged & (op8=0xEC); indexed2_5 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + D = indexed2_5; + $(Z) = (D == 0); + $(N) = (D s< 0); + V_equals_0(); +} + + +define pcodeop LoadStack; + +:LDS iopr16i is Prefix18=0 & (op8=0xCF); iopr16i +{ + SP = LoadStack(iopr16i); + $(Z) = (SP == 0); + $(N) = (SP s< 0); + V_equals_0(); +} + +:^GPaged^"LDS" opr8a_16 is GPaged & (op8=0xDF); opr8a_16 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + SP = LoadStack(opr8a_16); + $(Z) = (SP == 0); + $(N) = (SP s< 0); + V_equals_0(); +} + +:^GPaged^"LDS" opr16a_16 is GPaged & (op8=0xFF); opr16a_16 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + SP = LoadStack(opr16a_16); + $(Z) = (SP == 0); + $(N) = (SP s< 0); + V_equals_0(); +} + +:^GPaged^"LDS" indexed2_5 is GPaged & (op8=0xEF); indexed2_5 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + SP = LoadStack(indexed2_5); + $(Z) = (SP == 0); + $(N) = (SP s< 0); + V_equals_0(); +} + +:LDX iopr16i is Prefix18=0 & (op8=0xCE); iopr16i +{ + IX = iopr16i; + $(Z) = (IX == 0); + $(N) = (IX s< 0); + V_equals_0(); +} + +:^GPaged^"LDX" opr8a_16 is GPaged & (op8=0xDE); opr8a_16 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + IX = opr8a_16; + $(Z) = (IX == 0); + $(N) = (IX s< 0); + V_equals_0(); +} + +:^GPaged^"LDX" opr16a_16 is GPaged & (op8=0xFE); opr16a_16 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + IX = opr16a_16; + $(Z) = (IX == 0); + $(N) = (IX s< 0); + V_equals_0(); +} + +:^GPaged^"LDX" indexed2_5 is GPaged & (op8=0xEE); indexed2_5 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + IX = indexed2_5; + $(Z) = (IX == 0); + $(N) = (IX s< 0); + V_equals_0(); +} + +:LDY iopr16i is Prefix18=0 & (op8=0xCD); iopr16i +{ + IY = iopr16i; + $(Z) = (IY == 0); + $(N) = (IY s< 0); + V_equals_0(); +} + +:^GPaged^"LDY" opr8a_16 is GPaged & (op8=0xDD); opr8a_16 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + IY = opr8a_16; + $(Z) = (IY == 0); + $(N) = (IY s< 0); + V_equals_0(); +} + +:^GPaged^"LDY" opr16a_16 is GPaged & (op8=0xFD); opr16a_16 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + IY = opr16a_16; + $(Z) = (IY == 0); + $(N) = (IY s< 0); + V_equals_0(); +} + +:^GPaged^"LDY" indexed2_5 is GPaged & (op8=0xED); indexed2_5 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + IY = indexed2_5; + $(Z) = (IY == 0); + $(N) = (IY s< 0); + V_equals_0(); +} + +:LEAS indexed0_3 is Prefix18=0 & (op8=0x1B); indexed0_3 +{ + SP = indexed0_3; +} + +:LEAX indexed0_3 is Prefix18=0 & (op8=0x1A); indexed0_3 +{ + IX = indexed0_3; +} + +:LEAY indexed0_3 is Prefix18=0 & (op8=0x19); indexed0_3 +{ + IY = indexed0_3; +} + +## Logical Shift left is same as arithmetic shift left +#:LSL is (op8=0x68 | op8=0x78) +#:LSLA is op8=0x48 +#:LSLB is op8=0x58 +#:LSLD is op8=0x59 + +#:LSLW is op16=0x1878 | op16=0x1868 see ASLW +#:LSLX is op16=0x1848 see ASLX +#:LSLY is op16=0x1858 see ASLY + +:LSR opr16a_8 is Prefix18=0 & (op8=0x74); opr16a_8 +{ + tmp:1 = opr16a_8; + $(C) = tmp & 1; + tmp = tmp >> 1; + opr16a_8 = tmp; + $(Z) = (tmp == 0); + $(N) = 0; + V_equals_C(); +} + +:LSR indexed1_5 is Prefix18=0 & (op8=0x64); indexed1_5 +{ + tmp:1 = indexed1_5; + $(C) = tmp & 1; + tmp = tmp >> 1; + indexed1_5 = tmp; + $(Z) = (tmp == 0); + $(N) = 0; + V_equals_C(); +} + +:LSRA is Prefix18=0 & op8=0x44 +{ + $(C) = A[0,1]; + A = (A >> 1); + $(Z) = (A == 0); + $(N) = 0; + V_equals_C(); +} + +:LSRB is Prefix18=0 & op8=0x54 +{ + $(C) = B[0,1]; + B = (B >> 1); + $(Z) = (B == 0); + $(N) = 0; + V_equals_C(); +} + +:LSRD is Prefix18=0 & op8=0x49 +{ + $(C) = D[0,1]; + D = (D >> 1); + $(Z) = (D == 0); + $(N) = 0; + V_equals_C(); +} + +@if defined(HCS12X) +:LSRW opr16a_16 is Prefix18=1 & (op8=0x74); opr16a_16 +{ + local tmp = opr16a_16; + $(C) = tmp[0,1]; + tmp = tmp >> 1; + opr16a_16 = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS12X) +:LSRW indexed2_5 is Prefix18=1 & (op8=0x64); indexed2_5 +{ + local tmp = indexed2_5; + $(C) = tmp[0,1]; + tmp = tmp >> 1; + indexed2_5 = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS12X) +:LSRX is Prefix18=1 & op8=0x44 +{ + $(C) = IX[0,1]; + IX = IX >> 1; + $(Z) = (IX == 0); + $(N) = (IX s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS12X) +:LSRY is Prefix18=1 & op8=0x54 +{ + $(C) = IY[0,1]; + IY = IY >> 1; + $(Z) = (IY == 0); + $(N) = (IY s< 0); + V_equals_N_xor_C(); +} +@endif + +:MAXA indexed1_5 is Prefix18=1 & op8=0x18; indexed1_5 +{ + tmp:1 = indexed1_5; + result:2 = zext(A) - zext(tmp); + if (A > tmp) goto ; + A = tmp; + + + $(N) = (result:1 s< 0); + $(Z) = (result:1 == 0); + $(V) = (result s> 0x007F) | (result s< 0x0080); + $(C) = (result > 0x00FF); +} + +:MAXM indexed1_5 is Prefix18=1 & op8=0x1C; indexed1_5 +{ + tmp:1 = indexed1_5; + result:4 = zext(A) - zext(tmp); + if (tmp > A) goto ; + indexed1_5 = A; + + + $(N) = (result:2 s< 0); + $(Z) = (result:2 == 0); + $(V) = (result s> 0x007F) | (result s< 0x0080); + $(C) = (result > 0x00FF); +} + +:MEM is Prefix18=0 & op8=0x01 +{ + local val:1 = GradeOfMembership(A, IX, IY); + Store(IY, val); + IY = IY + 1; + IX = IX + 4; +} + +:MINA indexed1_5 is Prefix18=1 & op8=0x19; indexed1_5 +{ + tmp:1 = indexed1_5; + result:2 = zext(A) - zext(tmp); + if (A < tmp) goto ; + A = tmp; + + + $(N) = (result:1 s< 0); + $(Z) = (result:1 == 0); + $(V) = (result s> 0x007F) | (result s< 0x0080); + $(C) = (result > 0x00FF); +} + +:MINM indexed1_5 is Prefix18=1 & op8=0x1D; indexed1_5 +{ + tmp:1 = indexed1_5; + result:4 = zext(A) - zext(tmp); + if (tmp < A) goto ; + indexed1_5 = A; + + + $(N) = (result:2 s< 0); + $(Z) = (result:2 == 0); + $(V) = (result s> 0x007F) | (result s< 0x0080); + $(C) = (result > 0x00FF); +} + +:MOVB iopr8i, opr16a_8 is Prefix18=1 & op8=0x0B; iopr8i; opr16a_8 +{ + opr16a_8 = iopr8i; +} + +@if defined(HCS12X) +:MOVB iopr8i, indexed1_5 is Prefix18=1 & op8=0x08; indexed1_5; iopr8i +{ + indexed1_5 = iopr8i; +} +@else +:MOVB iopr8i, indexed1_1 is Prefix18=1 & op8=0x08; indexed1_1; iopr8i +{ + indexed1_1 = iopr8i; +} +@endif + +:MOVB opr16a_8, op2_opr16a_8 is Prefix18=1 & op8=0x0C; opr16a_8; op2_opr16a_8 +{ + build opr16a_8; + local tmp = opr16a_8; + build op2_opr16a_8; + op2_opr16a_8 = tmp; +} + +@if defined(HCS12X) +:MOVB opr16a_8, indexed1_5 is Prefix18=1 & op8=0x09; indexed1_5; opr16a_8 +{ + indexed1_5 = opr16a_8; +} +@else +:MOVB opr16a_8, indexed1_1 is Prefix18=1 & op8=0x09; indexed1_1; opr16a_8 +{ + indexed1_1 = opr16a_8; +} +@endif + +@if defined(HCS12X) +:MOVB indexed1_5, opr16a_8 is Prefix18=1 & op8=0x0D; indexed1_5; opr16a_8 +{ + opr16a_8 = indexed1_5; +} +@else +:MOVB indexed1_1, opr16a_8 is Prefix18=1 & op8=0x0D; indexed1_1; opr16a_8 +{ + opr16a_8 = indexed1_1; +} +@endif + +@if defined(HCS12X) +:MOVB indexed1_5, op2_indexed1_5 is Prefix18=1 & op8=0x0A; indexed1_5; op2_indexed1_5 +{ + # two operands share a lower level subconstructor + # MUST do the builds and store the value, or the first operands results will be overwritten + build indexed1_5; + local tmp = indexed1_5; + build op2_indexed1_5; + op2_indexed1_5 = tmp; +} +@else +:MOVB indexed1_1, op2_indexed1_1 is Prefix18=1 & op8=0x0A; indexed1_1; op2_indexed1_1 +{ + # two operands share a lower level subconstructor + # MUST do the builds and store the value, or the first operands results will be overwritten + build indexed1_1; + local tmp = indexed1_1; + build op2_indexed1_1; + op2_indexed1_1 = tmp; +} +@endif + +:MOVW iopr16i, opr16a_16 is Prefix18=1 & op8=0x03; iopr16i; opr16a_16 +{ + opr16a_16 = iopr16i; +} + +@if defined(HCS12X) +:MOVW iopr16i, indexed2_5 is Prefix18=1 & op8=0x00; indexed2_5; iopr16i +{ + indexed2_5 = iopr16i; +} +@else +:MOVW iopr16i, indexed2_1 is Prefix18=1 & op8=0x00; indexed2_1; iopr16i +{ + indexed2_1 = iopr16i; +} +@endif + +:MOVW opr16a_16, op2_opr16a_16 is Prefix18=1 & op8=0x04; opr16a_16; op2_opr16a_16 +{ + # two operands share a lower level subconstructor + # MUST do the builds and store the value, or the first operands results will be overwritten + build opr16a_16; + local tmp = opr16a_16; + build op2_opr16a_16; + op2_opr16a_16 = tmp; +} + +@if defined(HCS12X) +:MOVW opr16a_16, indexed2_5 is Prefix18=1 & op8=0x01; indexed2_5; opr16a_16 +{ + indexed2_5 = opr16a_16; +} +@else +:MOVW opr16a_16, indexed2_1 is Prefix18=1 & op8=0x01; indexed2_1; opr16a_16 +{ + indexed2_1 = opr16a_16; +} +@endif + +@if defined(HCS12X) +:MOVW indexed2_5, opr16a_16 is Prefix18=1 & op8=0x05; indexed2_5; opr16a_16 +{ + opr16a_16 = indexed2_5; +} +@else +:MOVW indexed2_1, opr16a_16 is Prefix18=1 & op8=0x05; indexed2_1; opr16a_16 +{ + opr16a_16 = indexed2_1; +} +@endif + +@if defined(HCS12X) +:MOVW indexed2_5, op2_indexed2_5 is Prefix18=1 & op8=0x02; indexed2_5; op2_indexed2_5 +{ + # two operands share a lower level subconstructor + # MUST do the builds and store the value, or the first operands results will be overwritten + build indexed2_5; + local tmp = indexed2_5; + build op2_indexed2_5; + op2_indexed2_5 = tmp; +} +@else +:MOVW indexed2_1, op2_indexed2_1 is Prefix18=1 & op8=0x02; indexed2_1; op2_indexed2_1 +{ + # two operands share a lower level subconstructor + # MUST do the builds and store the value, or the first operands results will be overwritten + build indexed2_1; + local tmp = indexed2_1; + build op2_indexed2_1; + op2_indexed2_1 = tmp; +} +@endif + + +:MUL is Prefix18=0 & op8=0x12 +{ + D = zext(A) * zext(B); + $(C) = B[7,1]; +} + +:NEG opr16a_8 is Prefix18=0 & (op8=0x70); opr16a_8 +{ + tmp:1 = opr16a_8; + result:1 = -tmp; + opr16a_8 = result; + $(C) = (result != 0); + $(Z) = (result == 0); + $(N) = (result s< 0); + V_NEG_flag(tmp); +} + +:NEG indexed1_5 is Prefix18=0 & (op8=0x60); indexed1_5 +{ + tmp:1 = indexed1_5; + result:1 = -tmp; + indexed1_5 = result; + $(C) = (result != 0); + $(Z) = (result == 0); + $(N) = (result s< 0); + V_NEG_flag(tmp); +} + +:NEGA is Prefix18=0 & op8=0x40 +{ + tmp:1 = A; + A = -tmp; + $(C) = (A != 0); + $(Z) = (A == 0); + $(N) = (A s< 0); + V_NEG_flag(tmp); +} + +:NEGB is Prefix18=0 & op8=0x50 +{ + tmp:1 = B; + B = -tmp; + $(C) = (B != 0); + $(Z) = (B == 0); + $(N) = (B s< 0); + V_NEG_flag(tmp); +} + +@if defined(HCS12X) +:NEGW opr16a_16 is Prefix18=1 & (op8=0x70); opr16a_16 +{ + tmp:2 = opr16a_16; + result:2 = -tmp; + opr16a_16 = result; + $(C) = (result != 0); + $(Z) = (result == 0); + $(N) = (result s< 0); + V_NEG_flag2(tmp); +} +@endif + +@if defined(HCS12X) +:NEGW indexed2_5 is Prefix18=1 & (op8=0x60); indexed2_5 +{ + tmp:2 = indexed2_5; + result:2 = -tmp; + indexed2_5 = result; + $(C) = (result != 0); + $(Z) = (result == 0); + $(N) = (result s< 0); + V_NEG_flag2(tmp); +} +@endif + +@if defined(HCS12X) +:NEGX is Prefix18=1 & op8=0x40 +{ + tmp:2 = IX; + IX = -tmp; + $(C) = (IX != 0); + $(Z) = (IX == 0); + $(N) = (IX s< 0); + V_NEG_flag2(tmp); +} +@endif + +@if defined(HCS12X) +:NEGY is Prefix18=1 & op8=0x50 +{ + tmp:2 = IY; + IY = -tmp; + $(C) = (IY != 0); + $(Z) = (IY == 0); + $(N) = (IY s< 0); + V_NEG_flag2(tmp); +} +@endif + +:NOP is Prefix18=0 & op8=0xA7 +{ +} + +:ORAA iopr8i is Prefix18=0 & (op8=0x8A); iopr8i +{ + A = A | iopr8i; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} + +:ORAA opr8a_8 is Prefix18=0 & (op8=0x9A); opr8a_8 +{ + A = A | opr8a_8; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} + +:ORAA opr16a_8 is Prefix18=0 & (op8=0xBA); opr16a_8 +{ + A = A | opr16a_8; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} + +:ORAA indexed1_5 is Prefix18=0 & (op8=0xAA); indexed1_5 +{ + A = A | indexed1_5; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} + +:ORAB iopr8i is Prefix18=0 & (op8=0xCA); iopr8i +{ + B = B | iopr8i; + $(Z) = (B == 0); + $(N) = (B s< 0); + V_equals_0(); +} + +:ORAB opr8a_8 is Prefix18=0 & (op8=0xDA); opr8a_8 +{ + B = B | opr8a_8; + $(Z) = (B == 0); + $(N) = (B s< 0); + V_equals_0(); +} + +:ORAB opr16a_8 is Prefix18=0 & (op8=0xFA); opr16a_8 +{ + B = B | opr16a_8; + $(Z) = (B == 0); + $(N) = (B s< 0); + V_equals_0(); +} + +:ORAB indexed1_5 is Prefix18=0 & (op8=0xEA); indexed1_5 +{ + B = B | indexed1_5; + $(Z) = (B == 0); + $(N) = (B s< 0); + V_equals_0(); +} + +:ORCC iopr8i is Prefix18=0 & (op8=0x14); iopr8i +{ + CCR = CCR | (iopr8i & 0b10111111); +} + +@if defined(HCS12X) +:ORX iopr16i is Prefix18=1 & (op8=0x8A); iopr16i +{ + IX = IX | iopr16i; + V_equals_0(); + $(Z) = (IX == 0); + $(N) = (IX s< 0); +} +@endif + +@if defined(HCS12X) +:ORX opr8a_16 is Prefix18=1 & (op8=0x9A); opr8a_16 +{ + IX = IX | opr8a_16; + V_equals_0(); + $(Z) = (IX == 0); + $(N) = (IX s< 0); +} +@endif + +@if defined(HCS12X) +:ORX opr16a_16 is Prefix18=1 & (op8=0xBA); opr16a_16 +{ + IX = IX | opr16a_16; + V_equals_0(); + $(Z) = (IX == 0); + $(N) = (IX s< 0); +} +@endif + +@if defined(HCS12X) +:ORX indexed2_5 is Prefix18=1 & (op8=0xAA); indexed2_5 +{ + IX = IX | indexed2_5; + V_equals_0(); + $(Z) = (IX == 0); + $(N) = (IX s< 0); +} +@endif + +@if defined(HCS12X) +:ORY iopr16i is Prefix18=1 & (op8=0xCA); iopr16i +{ + IY = IY | iopr16i; + V_equals_0(); + $(Z) = (IY == 0); + $(N) = (IY s< 0); +} +@endif + +@if defined(HCS12X) +:ORY opr8a_16 is Prefix18=1 & (op8=0xDA); opr8a_16 +{ + IY = IY | opr8a_16; + V_equals_0(); + $(Z) = (IY == 0); + $(N) = (IY s< 0); +} +@endif + +@if defined(HCS12X) +:ORY opr16a_16 is Prefix18=1 & (op8=0xFA); opr16a_16 +{ + IY = IY | opr16a_16; + V_equals_0(); + $(Z) = (IY == 0); + $(N) = (IY s< 0); +} +@endif + +@if defined(HCS12X) +:ORY indexed2_5 is Prefix18=1 & (op8=0xEA); indexed2_5 +{ + IY = IY | indexed2_5; + V_equals_0(); + $(Z) = (IY == 0); + $(N) = (IY s< 0); +} +@endif + +:PSHA is Prefix18=0 & op8=0x36 +{ + Push1( A ); +} + +:PSHB is Prefix18=0 & op8=0x37 +{ + Push1( B ); +} + +:PSHC is Prefix18=0 & op8=0x39 +{ + Push1( CCR ); +} + +@if defined(HCS12X) +:PSHCW is Prefix18=1 & op8=0x39 +{ + Push2( CCRW ); +} +@endif + +:PSHD is Prefix18=0 & op8=0x3B +{ + Push2( D ); +} + +:PSHX is Prefix18=0 & op8=0x34 +{ + Push2( IX ); +} + +:PSHY is Prefix18=0 & op8=0x35 +{ + Push2( IY ); +} + +:PULA is Prefix18=0 & op8=0x32 +{ + Pull1( A ); +} + +:PULB is Prefix18=0 & op8=0x33 +{ + Pull1( B ); +} + +:PULC is Prefix18=0 & op8=0x38 +{ + Pull1( CCR ); +} + +@if defined(HCS12X) +:PULCW is Prefix18=1 & op8=0x38 +{ + Pull2( CCRW ); +} +@endif + +:PULD is Prefix18=0 & op8=0x3A +{ + Pull2( D ); +} + +:PULX is Prefix18=0 & op8=0x30 +{ + Pull2( IX ); +} + +:PULY is Prefix18=0 & op8=0x31 +{ + Pull2( IY ); +} + +:REV is Prefix18=1 & op8=0x3A +{ + tempIX:2 = MinMaxRuleEvaluation(IX, IY, A, $(V)); + $(V) = MinMaxRuleEvaluationCorrect(IX, IY, A, $(V)); + + IX = tempIX; +} + +:REVW is Prefix18=1 & op8=0x3B +{ + tempIX:2 = MinMaxRuleEvaluationWeighted(IX, IY, A, $(V), $(C)); + tempIY:2 = MinMaxRuleEvaluationWeighted(IX, IY, A, $(V), $(C)); + $(V) = MinMaxRuleEvaluationWeightedCorrect(IX, IY, A, $(V), $(C)); + + IX = tempIX; + IY = tempIY; +} + +:ROL opr16a_8 is Prefix18=0 & (op8=0x75); opr16a_8 +{ + tmpC:1 = $(C); + op1:1 = opr16a_8; + $(C) = op1 >> 7; + result:1 = op1 << 1; + result = result | tmpC; + opr16a_8 = result; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_equals_N_xor_C(); +} + +:ROL indexed1_5 is Prefix18=0 & (op8=0x65); indexed1_5 +{ + tmpC:1 = $(C); + op1:1 = indexed1_5; + $(C) = op1 >> 7; + result:1 = op1 << 1; + result = result | tmpC; + indexed1_5 = result; + $(Z) = (result == 0); + $(N) = (result s< 0); + V_equals_N_xor_C(); +} + +:ROLA is Prefix18=0 & op8=0x45 +{ + tmpC:1 = $(C) ; + $(C) = A >> 7; + A = A << 1; + A = A | tmpC; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_N_xor_C(); +} + +:ROLB is Prefix18=0 & op8=0x55 +{ + tmpC:1 = $(C) ; + $(C) = B >> 7; + B = B << 1; + B = B | tmpC; + $(Z) = (B == 0); + $(N) = (B s< 0); + V_equals_N_xor_C(); +} + +@if defined(HCS12X) +:ROLW opr16a_16 is Prefix18=1 & (op8=0x75); opr16a_16 +{ + local tmp = opr16a_16; + local tmpC = $(C); + $(C) = tmp[15,1]; + tmp = tmp << 1; + tmp = tmp | zext(tmpC); + opr16a_16 = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS12X) +:ROLW indexed2_5 is Prefix18=1 & (op8=0x65); indexed2_5 +{ + local tmp = indexed2_5; + local tmpC = $(C); + $(C) = tmp[15,1]; + tmp = tmp << 1; + tmp = tmp | zext(tmpC); + indexed2_5 = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS12X) +:ROLX is Prefix18=1 & op8=0x45 +{ + local tmpC = $(C); + $(C) = IX[15,1]; + IX = IX << 1; + IX = IX | zext(tmpC); + $(Z) = (IX == 0); + $(N) = (IX s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS12X) +:ROLY is Prefix18=1 & op8=0x55 +{ + local tmpC = $(C); + $(C) = IY[15,1]; + IY = IY << 1; + IY = IY | zext(tmpC); + $(Z) = (IY == 0); + $(N) = (IY s< 0); + V_equals_N_xor_C(); +} +@endif + +:ROR opr16a_8 is Prefix18=0 & (op8=0x76); opr16a_8 +{ + tmpC:1 = $(C) << 7; + tmp:1 = opr16a_8; + $(C) = tmp & 1; + tmp = tmp >> 1; + tmp = tmp | tmpC; + opr16a_8 = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + V_equals_N_xor_C(); +} + +:ROR indexed1_5 is Prefix18=0 & (op8=0x66); indexed1_5 +{ + tmpC:1 = $(C) << 7; + tmp:1 = indexed1_5; + $(C) = tmp & 1; + tmp = tmp >> 1; + tmp = tmp | tmpC; + indexed1_5 = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + V_equals_N_xor_C(); +} + +:RORA is Prefix18=0 & op8=0x46 +{ + tmpC:1 = $(C) << 7; + $(C) = A & 1; + A = A >> 1; + A = A | tmpC; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_N_xor_C(); +} + +:RORB is Prefix18=0 & op8=0x56 +{ + tmpC:1 = $(C) << 7; + $(C) = B & 1; + B = B >> 1; + B = B | tmpC; + $(Z) = (B == 0); + $(N) = (B s< 0); + V_equals_N_xor_C(); +} + +@if defined(HCS12X) +:RORW opr16a_16 is Prefix18=1 & (op8=0x76); opr16a_16 +{ + local tmp = opr16a_16; + local tmpC = $(C); + $(C) = tmp[0,1]; + tmp = tmp >> 1; + tmp = tmp | (zext(tmpC) << 15); + opr16a_16 = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS12X) +:RORW indexed2_5 is Prefix18=1 & (op8=0x66); indexed2_5 +{ + local tmp = indexed2_5; + local tmpC = $(C); + $(C) = tmp[0,1]; + tmp = tmp >> 1; + tmp = tmp | (zext(tmpC) << 15); + indexed2_5 = tmp; + $(Z) = (tmp == 0); + $(N) = (tmp s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS12X) +:RORX is Prefix18=1 & op8=0x46 +{ + local tmpC = $(C); + $(C) = IX[0,1]; + IX = IX >> 1; + IX = IX | (zext(tmpC) << 15); + $(Z) = (IX == 0); + $(N) = (IX s< 0); + V_equals_N_xor_C(); +} +@endif + +@if defined(HCS12X) +:RORY is Prefix18=1 & op8=0x56 +{ + local tmpC = $(C); + $(C) = IY[0,1]; + IY = IY >> 1; + IY = IY | (zext(tmpC) << 15); + $(Z) = (IY == 0); + $(N) = (IY s< 0); + V_equals_N_xor_C(); +} +@endif + +@ifdef HCS12 +:RTC is Prefix18=0 & op8=0x0A +{ + Pull1( PPAGE ); + + tmp:2 = 0; + Pull2( tmp ); + + return [tmp]; +} +@endif + +:RTI is Prefix18=0 & op8=0x0B +{ + tmp:2 = 0; + Pull1( CCR ); + Pull1( B ); + Pull1( A ); + Pull2( IX ); + Pull2( IY ); + Pull2( tmp ); # as ordered on page 289, not as documented in RTI description + + return [tmp]; +} + +:RTS is Prefix18=0 & op8=0x3D +{ + tmp:2 = 0; + Pull2( tmp ); + + return [tmp]; +} + +:SBA is Prefix18=1 & (op8=0x16) +{ + result:1 = A - B; + subtraction_flags1(A, B, result); + A = result; +} + +:SBCA iopr8i is Prefix18=0 & (op8=0x82); iopr8i +{ + op1:1 = iopr8i; + + result:1 = A - op1 - $(C); + subtraction_flags1(A, op1, result); + A = result; +} + +:SBCA opr8a_8 is Prefix18=0 & (op8=0x92); opr8a_8 +{ + op1:1 = opr8a_8; + + result:1 = A - op1 - $(C); + subtraction_flags1(A, op1, result); + A = result; +} + +:SBCA opr16a_8 is Prefix18=0 & (op8=0xB2); opr16a_8 +{ + op1:1 = opr16a_8; + + result:1 = A - op1 - $(C); + subtraction_flags1(A, op1, result); + A = result; +} + +:SBCA indexed1_5 is Prefix18=0 & (op8=0xA2); indexed1_5 +{ + op1:1 = indexed1_5; + + result:1 = A - op1 - $(C); + subtraction_flags1(A, op1, result); + A = result; +} + +:SBCB iopr8i is Prefix18=0 & (op8=0xC2); iopr8i +{ + op1:1 = iopr8i; + + result:1 = B - op1 - $(C); + subtraction_flags1(B, op1, result); + B = result; +} + +:SBCB opr8a_8 is Prefix18=0 & (op8=0xD2); opr8a_8 +{ + op1:1 = opr8a_8; + + result:1 = B - op1 - $(C); + subtraction_flags1(B, op1, result); + B = result; +} + +:SBCB opr16a_8 is Prefix18=0 & (op8=0xF2); opr16a_8 +{ + op1:1 = opr16a_8; + + result:1 = B - op1 - $(C); + subtraction_flags1(B, op1, result); + B = result; +} + +:SBCB indexed1_5 is Prefix18=0 & (op8=0xE2); indexed1_5 +{ + op1:1 = indexed1_5; + + result:1 = B - op1 - $(C); + subtraction_flags1(B, op1, result); + B = result; +} + +@if defined(HCS12X) +:SBED iopr16i is Prefix18=1 & (op8=0x83); iopr16i +{ + op1:2 = iopr16i; + + result:2 = D - op1 - zext($(C)); + subtraction_flags2(D, op1, result); + D = result; +} +@endif + +@if defined(HCS12X) +:SBED opr8a_16 is Prefix18=1 & (op8=0x93); opr8a_16 +{ + op1:2 = opr8a_16; + + result:2 = D - op1 - zext($(C)); + subtraction_flags2(D, op1, result); + D = result; +} +@endif + +@if defined(HCS12X) +:SBED opr16a_16 is Prefix18=1 & (op8=0xB3); opr16a_16 +{ + op1:2 = opr16a_16; + + result:2 = D - op1 - zext($(C)); + subtraction_flags2(D, op1, result); + D = result; +} +@endif + +@if defined(HCS12X) +:SBED indexed2_5 is Prefix18=1 & (op8=0xA3); indexed2_5 +{ + op1:2 = indexed2_5; + + result:2 = D - op1 - zext($(C)); + subtraction_flags2(D, op1, result); + D = result; +} +@endif + +@if defined(HCS12X) +:SBEX iopr16i is Prefix18=1 & (op8=0x82); iopr16i +{ + op1:2 = iopr16i; + + result:2 = IX - op1 - zext($(C)); + subtraction_flags2(IX, op1, result); + IX = result; +} +@endif + +@if defined(HCS12X) +:SBEX opr8a_16 is Prefix18=1 & (op8=0x92); opr8a_16 +{ + op1:2 = opr8a_16; + + result:2 = IX - op1 - zext($(C)); + subtraction_flags2(IX, op1, result); + IX = result; +} +@endif + +@if defined(HCS12X) +:SBEX opr16a_16 is Prefix18=1 & (op8=0xB2); opr16a_16 +{ + op1:2 = opr16a_16; + + result:2 = IX - op1 - zext($(C)); + subtraction_flags2(IX, op1, result); + IX = result; +} +@endif + +@if defined(HCS12X) +:SBEX indexed2_5 is Prefix18=1 & (op8=0xA2); indexed2_5 +{ + op1:2 = indexed2_5; + + result:2 = IX - op1 - zext($(C)); + subtraction_flags2(IX, op1, result); + IX = result; +} +@endif + +@if defined(HCS12X) +:SBEY iopr16i is Prefix18=1 & (op8=0xC2); iopr16i +{ + op1:2 = iopr16i; + + result:2 = IY - op1 - zext($(C)); + subtraction_flags2(IY, op1, result); + IY = result; +} +@endif + +@if defined(HCS12X) +:SBEY opr8a_16 is Prefix18=1 & (op8=0xD2); opr8a_16 +{ + op1:2 = opr8a_16; + + result:2 = IY - op1 - zext($(C)); + subtraction_flags2(IY, op1, result); + IY = result; +} +@endif + +@if defined(HCS12X) +:SBEY opr16a_16 is Prefix18=1 & (op8=0xF2); opr16a_16 +{ + op1:2 = opr16a_16; + + result:2 = IY - op1 - zext($(C)); + subtraction_flags2(IY, op1, result); + IY = result; +} +@endif + +@if defined(HCS12X) +:SBEY indexed2_5 is Prefix18=1 & (op8=0xE2); indexed2_5 +{ + op1:2 = indexed2_5; + + result:2 = IY - op1 - zext($(C)); + subtraction_flags2(IY, op1, result); + IY = result; +} +@endif + +:SEC is Prefix18=0 & op16=0x1401 +{ + $(C) = 1; +} + +:SEI is Prefix18=0 & op16=0x1410 +{ + $(I) = 1; +} + +:SEV is Prefix18=0 & op16=0x1402 +{ + $(V) = 1; +} + + + +@if defined(HCS12X) +:SEX A, D is Prefix18=0 & op8=0xB7; + ( + ( rows3_0=0xC & ( columns7_4=0x0 ) ) + ) & + A & D +{ + D = sext( A ); +} +@endif + +@if defined(HCS12X) +:SEX B, D is Prefix18=0 & op8=0xB7; + ( + ( rows3_0=0xC & ( columns7_4=0x1 ) ) + ) & + B & D +{ + D = sext( B ); +} +@endif + +@if defined(HCS12X) +:SEX D, IX is Prefix18=0 & op8=0xB7; + ( + ( rows3_0=0xD & ( columns7_4=0x4 ) ) + ) & + D & IX +{ + # generate the sign extension upper word and assign it to destination + local tmp:4 = sext( D ); + IX = tmp(2); +} +@endif + +@if defined(HCS12X) +:SEX D, IY is Prefix18=0 & op8=0xB7; + ( + ( rows3_0=0xE & ( columns7_4=0x4 ) ) + ) & + D & IY +{ + # generate the sign extension upper word and assign it to destination + local tmp:4 = sext( D ); + IY = tmp(2); +} +@endif + +:SEX abc5_4, dxys2_0 is Prefix18=0 & op8=0xB7; + ( + ( rows3_0=0x3 & ( columns7_4=0x0 | columns7_4=0x1 | columns7_4=0x2 ) ) | + ( rows3_0=0x4 & ( columns7_4=0x0 | columns7_4=0x1 | columns7_4=0x2 ) ) | + ( rows3_0=0x5 & ( columns7_4=0x0 | columns7_4=0x1 | columns7_4=0x2 ) ) | + ( rows3_0=0x6 & ( columns7_4=0x0 | columns7_4=0x1 | columns7_4=0x2 ) ) | + ( rows3_0=0x7 & ( columns7_4=0x0 | columns7_4=0x1 | columns7_4=0x2 ) ) + ) & + abc5_4 & dxys2_0 +{ + dxys2_0 = sext(abc5_4); +} + +:^GPaged^"STAA" opr8a_8 is GPaged & (op8=0x5A); opr8a_8 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + opr8a_8 = A; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} + +:^GPaged^"STAA" opr16a_8 is GPaged & (op8=0x7A); opr16a_8 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + opr16a_8 = A; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} + +:^GPaged^"STAA" indexed1_5 is GPaged & (op8=0x6A); indexed1_5 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + indexed1_5 = A; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} + +:^GPaged^"STAB" opr8a_8 is GPaged & (op8=0x5B); opr8a_8 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + opr8a_8 = B; + $(Z) = (B == 0); + $(N) = (B s< 0); + V_equals_0(); +} + +:^GPaged^"STAB" opr16a_8 is GPaged & (op8=0x7B); opr16a_8 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + opr16a_8 = B; + $(Z) = (B == 0); + $(N) = (B s< 0); + V_equals_0(); +} + +:^GPaged^"STAB" indexed1_5 is GPaged & (op8=0x6B); indexed1_5 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + indexed1_5 = B; + $(Z) = (B == 0); + $(N) = (B s< 0); + V_equals_0(); +} + +:^GPaged^"STD" opr8a_16 is GPaged & (op8=0x5C); opr8a_16 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + opr8a_16 = D; + $(Z) = (D == 0); + $(N) = (D s< 0); + V_equals_0(); +} + +:^GPaged^"STD" opr16a_16 is GPaged & (op8=0x7C); opr16a_16 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + opr16a_16 = D; + $(Z) = (D == 0); + $(N) = (D s< 0); + V_equals_0(); +} + +:^GPaged^"STD" indexed2_5 is GPaged & (op8=0x6C); indexed2_5 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + indexed2_5 = D; + $(Z) = (D == 0); + $(N) = (D s< 0); + V_equals_0(); +} + +:STOP is Prefix18=1 & op8=0x3E +{ + if ($(S) == 0) goto ; + tmp:2 = inst_next; + Push2( tmp ); + Push2( IY ); + Push2( IX ); + Push1( A ); + Push1( B ); + Push1( CCR ); + stop(); + +} + +:^GPaged^"STS" opr8a_16 is GPaged & (op8=0x5F); opr8a_16 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + opr8a_16 = SP; + $(Z) = (SP == 0); + $(N) = (SP s< 0); + V_equals_0(); +} + +:^GPaged^"STS" opr16a_16 is GPaged & (op8=0x7F); opr16a_16 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + opr16a_16 = SP; + $(Z) = (SP == 0); + $(N) = (SP s< 0); + V_equals_0(); +} + +:^GPaged^"STS" indexed2_5 is GPaged & (op8=0x6F); indexed2_5 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + indexed2_5 = SP; + $(Z) = (SP == 0); + $(N) = (SP s< 0); + V_equals_0(); +} + +:^GPaged^"STX" opr8a_16 is GPaged & (op8=0x5E); opr8a_16 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + opr8a_16 = IX; + $(Z) = (IX == 0); + $(N) = (IX s< 0); + V_equals_0(); +} + +:^GPaged^"STX" opr16a_16 is GPaged & (op8=0x7E); opr16a_16 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + opr16a_16 = IX; + $(Z) = (IX == 0); + $(N) = (IX s< 0); + V_equals_0(); +} + +:^GPaged^"STX" indexed2_5 is GPaged & (op8=0x6E); indexed2_5 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + indexed2_5 = IX; + $(Z) = (IX == 0); + $(N) = (IX s< 0); + V_equals_0(); +} + +:^GPaged^"STY" opr8a_16 is GPaged & (op8=0x5D); opr8a_16 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + opr8a_16 = IY; + $(Z) = (IY == 0); + $(N) = (IY s< 0); + V_equals_0(); +} + +:^GPaged^"STY" opr16a_16 is GPaged & (op8=0x7D); opr16a_16 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + opr16a_16 = IY; + $(Z) = (IY == 0); + $(N) = (IY s< 0); + V_equals_0(); +} + +:^GPaged^"STY" indexed2_5 is GPaged & (op8=0x6D); indexed2_5 [ UseGPAGE=Prefix18; ] +{ + build GPaged; + indexed2_5 = IY; + $(Z) = (IY == 0); + $(N) = (IY s< 0); + V_equals_0(); +} + +:SUBA iopr8i is Prefix18=0 & (op8=0x80); iopr8i +{ + op1:1 = iopr8i; + + result:1 = A - op1; + subtraction_flags1(A, op1, result); + A = result; +} + +:SUBA opr8a_8 is Prefix18=0 & (op8=0x90); opr8a_8 +{ + op1:1 = opr8a_8; + + result:1 = A - op1; + subtraction_flags1(A, op1, result); + A = result; +} + +:SUBA opr16a_8 is Prefix18=0 & (op8=0xB0); opr16a_8 +{ + op1:1 = opr16a_8; + + result:1 = A - op1; + subtraction_flags1(A, op1, result); + A = result; +} + +:SUBA indexed1_5 is Prefix18=0 & (op8=0xA0); indexed1_5 +{ + op1:1 = indexed1_5; + + result:1 = A - op1; + subtraction_flags1(A, op1, result); + A = result; +} + +:SUBB iopr8i is Prefix18=0 & (op8=0xC0); iopr8i +{ + op1:1 = iopr8i; + + result:1 = B - op1; + subtraction_flags1(B, op1, result); + B = result; +} + +:SUBB opr8a_8 is Prefix18=0 & (op8=0xD0); opr8a_8 +{ + op1:1 = opr8a_8; + + result:1 = B - op1; + subtraction_flags1(B, op1, result); + B = result; +} + +:SUBB opr16a_8 is Prefix18=0 & (op8=0xF0); opr16a_8 +{ + op1:1 = opr16a_8; + + result:1 = B - op1; + subtraction_flags1(B, op1, result); + B = result; +} + +:SUBB indexed1_5 is Prefix18=0 & (op8=0xE0); indexed1_5 +{ + op1:1 = indexed1_5; + + result:1 = B - op1; + subtraction_flags1(B, op1, result); + B = result; +} + +:SUBD iopr16i is Prefix18=0 & (op8=0x83); iopr16i +{ + op1:2 = iopr16i; + + result:2 = D - op1; + subtraction_flags2(D, op1, result); + D = result; +} + +:SUBD opr8a_16 is Prefix18=0 & (op8=0x93); opr8a_16 +{ + op1:2 = opr8a_16; + + result:2 = D - op1; + subtraction_flags2(D, op1, result); + D = result; +} + +:SUBD opr16a_16 is Prefix18=0 & (op8=0xB3); opr16a_16 +{ + op1:2 = opr16a_16; + + result:2 = D - op1; + subtraction_flags2(D, op1, result); + D = result; +} + +:SUBD indexed2_5 is Prefix18=0 & (op8=0xA3); indexed2_5 +{ + op1:2 = indexed2_5; + + result:2 = D - op1; + subtraction_flags2(D, op1, result); + D = result; +} + +@if defined(HCS12X) +:SUBX iopr16i is Prefix18=1 & (op8=0x80); iopr16i +{ + op1:2 = iopr16i; + + result:2 = IX - op1; + subtraction_flags2(IX, op1, result); + IX = result; +} +@endif + +@if defined(HCS12X) +:SUBX opr8a_16 is Prefix18=1 & (op8=0x90); opr8a_16 +{ + op1:2 = opr8a_16; + + result:2 = IX - op1; + subtraction_flags2(IX, op1, result); + IX = result; +} +@endif + +@if defined(HCS12X) +:SUBX opr16a_16 is Prefix18=1 & (op8=0xB0); opr16a_16 +{ + op1:2 = opr16a_16; + + result:2 = IX - op1; + subtraction_flags2(IX, op1, result); + IX = result; +} +@endif + +@if defined(HCS12X) +:SUBX indexed2_5 is Prefix18=1 & (op8=0xA0); indexed2_5 +{ + op1:2 = indexed2_5; + + result:2 = IX - op1; + subtraction_flags2(IX, op1, result); + IX = result; +} +@endif + +@if defined(HCS12X) +:SUBY iopr16i is Prefix18=1 & (op8=0xC0); iopr16i +{ + op1:2 = iopr16i; + + result:2 = IY - op1; + subtraction_flags2(IY, op1, result); + IY = result; +} +@endif + +@if defined(HCS12X) +:SUBY opr8a_16 is Prefix18=1 & (op8=0xD0); opr8a_16 +{ + op1:2 = opr8a_16; + + result:2 = IY - op1; + subtraction_flags2(IY, op1, result); + IY = result; +} +@endif + +@if defined(HCS12X) +:SUBY opr16a_16 is Prefix18=1 & (op8=0xF0); opr16a_16 +{ + op1:2 = opr16a_16; + + result:2 = IY - op1; + subtraction_flags2(IY, op1, result); + IY = result; +} +@endif + +@if defined(HCS12X) +:SUBY indexed2_5 is Prefix18=1 & (op8=0xE0); indexed2_5 +{ + op1:2 = indexed2_5; + + result:2 = IY - op1; + subtraction_flags2(IY, op1, result); + IY = result; +} +@endif + +:SWI is Prefix18=0 & op8=0x3F +{ + tmp:2 = inst_next; + Push2( tmp ); + Push2( IY ); + Push2( IX ); + Push1( A ); + Push1( B ); + Push1( CCR ); + + $(I) = 1; + + addr:2 = $(VECTOR_SWI); + call [addr]; +} + +:TAB is Prefix18=1 & op8=0x0E +{ + B = A; + $(Z) = (B == 0); + $(N) = (B s< 0); + V_equals_0(); +} + +:TAP is Prefix18=0 & op16=0xB702 +{ + setCCR( A ); +} + +:TBA is Prefix18=1 & op8=0x0F +{ + A = B; + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); +} + +:TBEQ byte9_8, rel9 is Prefix18=0 & op8=0x04; op15_13=0x2 & size10_10=0 & byte9_8 & rel9 +{ + if (byte9_8 == 0) goto rel9; +} + +:TBEQ word9_8, rel9 is Prefix18=0 & op8=0x04; op15_13=0x2 & size10_10=1 & word9_8 & rel9 +{ + if (word9_8 == 0) goto rel9; +} + +:TBL indexed1_3 is Prefix18=1 & op8=0x3D; indexed1_3 +{ + A = TableLookupAndInterpolate(indexed1_3, B); + $(Z) = (A == 0); + $(N) = (A s< 0); +@if defined(HC12) + $(C) = TableLookupAndInterpolateRoundable(indexed1_3, B); +@endif +} + +:TBNE byte9_8, rel9 is Prefix18=0 & op8=0x04; op15_13=0x3 & size10_10=0 & byte9_8 & rel9 +{ + if (byte9_8 != 0) goto rel9; +} + +:TBNE word9_8, rel9 is Prefix18=0 & op8=0x04; op15_13=0x3 & size10_10=1 & word9_8 & rel9 +{ + if (word9_8 != 0) goto rel9; +} + +:TFR bytes_ABClT3lBXlYlSl_6_4, bytes_ABCl_2_0 is Prefix18=0 & ( op8=0xB7 ); + ( +# The case "20" is covered by TPA + ( rows3_0=0x0 & ( columns7_4=0x0 | columns7_4=0x1 | columns7_4=0x3 | columns7_4=0x4 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) | + ( rows3_0=0x1 & ( columns7_4=0x0 | columns7_4=0x1 | columns7_4=0x2 | columns7_4=0x3 | columns7_4=0x4 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) | + + ( rows3_0=0x8 & ( columns7_4=0x0 | columns7_4=0x1 | columns7_4=0x4 ) ) | + ( rows3_0=0x9 & ( columns7_4=0x0 | columns7_4=0x1 | columns7_4=0x2 | columns7_4=0x3 | columns7_4=0x4 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) + ) & + bytes_ABClT3lBXlYlSl_6_4 & bytes_ABCl_2_0 +{ + bytes_ABCl_2_0 = bytes_ABClT3lBXlYlSl_6_4; +} + +:TFR bytes_ABClT3lBXlYlSl_6_4, CCR is Prefix18=0 & ( op8=0xB7 ); + ( +# The case "02" is covered by TAP + ( rows3_0=0x2 & ( columns7_4=0x1 | columns7_4=0x2 | columns7_4=0x3 | columns7_4=0x4 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) | + + ( rows3_0=0xA & ( columns7_4=0x1 ) ) + ) & + bytes_ABClT3lBXlYlSl_6_4 & CCR +{ + setCCR( bytes_ABClT3lBXlYlSl_6_4 ); +} + +:TFR bytes_ABChT3hBXhYhSh_6_4, A is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0x8 & ( columns7_4=0x2 | columns7_4=0x3 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) + ) & + bytes_ABChT3hBXhYhSh_6_4 & A +{ + A = bytes_ABChT3hBXhYhSh_6_4; +} + +:TFR A, CCRH is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0xA & ( columns7_4=0x0 ) ) + ) & + A & CCRH +{ + CCRH = A; +} + +:TFR words_CT3DXYS_6_4, CCRW is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0xA & ( columns7_4=0x2 | columns7_4=0x3 | columns7_4=0x4 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) + ) & + words_CT3DXYS_6_4 & CCRW +{ + setCCRW( words_CT3DXYS_6_4 ); +} + +:TFR words_T3DXYS_6_4, words_T2DXYS_2_0 is Prefix18=0 & ( op8=0xB7 ); + ( +# The case "57" is covered by TXS +# The case "67" is covered by TYS +# The case "75" is covered by TSX +# The case "76" is covered by TSY + ( rows3_0=0x3 & ( columns7_4=0x3 | columns7_4=0x4 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) | + ( rows3_0=0x4 & ( columns7_4=0x3 | columns7_4=0x4 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) | + ( rows3_0=0x5 & ( columns7_4=0x3 | columns7_4=0x4 | columns7_4=0x5 | columns7_4=0x6 ) ) | + ( rows3_0=0x6 & ( columns7_4=0x3 | columns7_4=0x4 | columns7_4=0x5 | columns7_4=0x6 ) ) | + ( rows3_0=0x7 & ( columns7_4=0x3 | columns7_4=0x4 | columns7_4=0x7 ) ) | + + ( rows3_0=0xB & ( columns7_4=0x3 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) | + ( rows3_0=0xC & ( columns7_4=0x4 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) | + ( rows3_0=0xD & ( columns7_4=0x3 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) | + ( rows3_0=0xE & ( columns7_4=0x3 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) | + ( rows3_0=0xF & ( columns7_4=0x3 | columns7_4=0x4 | columns7_4=0x5 | columns7_4=0x6 | columns7_4=0x7 ) ) + ) & + words_T3DXYS_6_4 & words_T2DXYS_2_0 +{ + words_T2DXYS_2_0 = words_T3DXYS_6_4; +} + +:TFR D, TMP1 is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0xB & ( columns7_4=0x4 ) ) + ) & + D & TMP1 +{ + TMP1 = D; +} + +:TFR TMP1, D is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0xC & ( columns7_4=0x3 ) ) + ) & + TMP1 & D +{ + D = TMP1; +} + +:TFR CCRW, words_T2DXYS_2_0 is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0xB & ( columns7_4=0x2 ) ) | + ( rows3_0=0xC & ( columns7_4=0x2 ) ) | + ( rows3_0=0xD & ( columns7_4=0x2 ) ) | + ( rows3_0=0xE & ( columns7_4=0x2 ) ) | + ( rows3_0=0xF & ( columns7_4=0x2 ) ) + ) & + CCRW & words_T2DXYS_2_0 +{ + words_T2DXYS_2_0 = CCRW; +} + +:TFR A, bytes_T2h_XhYhSh_2_0 is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0xB & ( columns7_4=0x0 ) ) | + + ( rows3_0=0xD & ( columns7_4=0x0 ) ) | + ( rows3_0=0xE & ( columns7_4=0x0 ) ) | + ( rows3_0=0xF & ( columns7_4=0x0 ) ) + ) & + A & bytes_T2h_XhYhSh_2_0 +{ + bytes_T2h_XhYhSh_2_0 = A; +} + +:TFR A, bytes_T2l_XlYlSl_2_0 is Prefix18=0 & ( op8=0xB7 ); + ( + ( rows3_0=0xB & ( columns7_4=0x1 ) ) | + + ( rows3_0=0xD & ( columns7_4=0x1 ) ) | + ( rows3_0=0xE & ( columns7_4=0x1 ) ) | + ( rows3_0=0xF & ( columns7_4=0x1 ) ) + ) & + A & bytes_T2l_XlYlSl_2_0 +{ + bytes_T2l_XlYlSl_2_0 = A; +} + +:TPA is Prefix18=0 & op16=0xB720 +{ + A = CCR; +} + +# TODO Not working properly with context regis ter for Prefix18 +:TRAP trapnum is Prefix18=1 & op8=0x30 & trapnum +{ + tmp:2 = inst_next; + Push2( tmp ); + Push2( IY ); + Push2( IX ); + Push1( A ); + Push1( B ); + Push1( CCR ); + + $(I) = 1; + + addr:2 = $(VECTOR_TRAP); + call [addr]; +} + +:TST opr16a_8 is Prefix18=0 & (op8=0xF7); opr16a_8 +{ + op1:1 = opr16a_8; + $(Z) = (op1 == 0); + $(N) = (op1 s< 0); + V_equals_0(); + $(C) = 0; +} + +:TST indexed1_5 is Prefix18=0 & (op8=0xE7); indexed1_5 +{ + op1:1 = indexed1_5; + $(Z) = (op1 == 0); + $(N) = (op1 s< 0); + V_equals_0(); + $(C) = 0; +} + +:TSTA is Prefix18=0 & op8=0x97 +{ + $(Z) = (A == 0); + $(N) = (A s< 0); + V_equals_0(); + $(C) = 0; +} + +:TSTB is Prefix18=0 & op8=0xD7 +{ + $(Z) = (B == 0); + $(N) = (B s< 0); + V_equals_0(); + $(C) = 0; +} + +@if defined(HCS12X) +:TSTW opr16a_16 is Prefix18=1 & (op8=0xF7); opr16a_16 +{ + op1:2 = opr16a_16; + $(Z) = (op1 == 0); + $(N) = (op1 s< 0); + V_equals_0(); + $(C) = 0; +} +@endif + +@if defined(HCS12X) +:TSTW indexed2_5 is Prefix18=1 & (op8=0xE7); indexed2_5 +{ + op1:2 = indexed2_5; + $(Z) = (op1 == 0); + $(N) = (op1 s< 0); + V_equals_0(); + $(C) = 0; +} +@endif + +:TSTX is Prefix18=1 & op8=0x97 +{ + $(Z) = (IX == 0); + $(N) = (IX s< 0); + V_equals_0(); +} + + +:TSTY is Prefix18=1 & op8=0xD7 +{ + $(Z) = (IY == 0); + $(N) = (IY s< 0); + V_equals_0(); +} + +:TSX is Prefix18=0 & op16=0xB775 +{ + IX = SP; +} + +:TSY is Prefix18=0 & op16=0xB776 +{ + IY = SP; +} + +:TXS is Prefix18=0 & op16=0xB757 +{ + SP = IX; +} + +:TYS is Prefix18=0 & op16=0xB767 +{ + SP = IY; +} + +:WAI is Prefix18=0 & op8=0x3E +{ + tmp:2 = inst_next; + Push2( tmp ); + Push2( IY ); + Push2( IX ); + Push1( A ); + Push1( B ); + Push1( CCR ); + + WaitForInterrupt(); +} + +:WAV is Prefix18=1 & op8=0x3C +{ + tempIY:2 = WeightedAverageSOPHigh(B, IY, IX); + tempD:2 = WeightedAverageSOPLow (B, IY, IX); + tempIX:2 = WeightedAverageSOW(B, IY, IX); + + B = 0; + + IY = tempIY; + D = tempD; + IX = tempIX; +} + +:WAVR is Prefix18=0 & op8=0x3C +{ + WeightedAverageResume(); +} + +:XGDX is Prefix18=0 & op16=0xB7C5 +{ + tmp:2 = IX; + IX = D; + D = tmp; +} + +:XGDY is Prefix18=0 & op16=0xB7C6 +{ + tmp:2 = IY; + IY = D; + D = tmp; +} + +} # End with : XGATE=0 diff --git a/python/icicle/Ghidra/Processors/HCS12/data/languages/XGATE.sinc b/python/icicle/Ghidra/Processors/HCS12/data/languages/XGATE.sinc new file mode 100644 index 0000000..c03f63b --- /dev/null +++ b/python/icicle/Ghidra/Processors/HCS12/data/languages/XGATE.sinc @@ -0,0 +1,993 @@ +# sleigh specification file for XGATE MCU peripheral co-processor + +################################################################ +# Registers +################################################################ + +# register R0 always contains the value 0 +define register offset=0x100 size=2 [R0 R1 R2 R3 R4 R5 R6 R7]; +define register offset=0x100 size=1 [R0.H R0.L R1.H R1.L R2.H R2.L R3.H R3.L R4.H R4.L R5.H R5.L R6.H R6.L R7.H R7.L]; +define register offset=0x110 size=2 [XPC XCCR]; +define register offset=0x120 size=1 [XC XV XZ XN]; + +# Individual status bits within the XCCR +@define XN "XN" # XCCR[3,1] # Negative Flag +@define XZ "XZ" # XCCR[2,1] # Zero Flag +@define XV "XV" # XCCR[1,1] # Overflow Flag +@define XC "XC" # XCCR[0,1] # Carry Flag + +################################################################ +# Tokens +################################################################ +define token XOpWord16 (16) + xop16 = (0,15) + opcode = (11,15) + reg8 = (8,10) + reg8_lo = (8,10) + reg8_hi = (8,10) + imm3 = (8,10) + op9_10 = (9,10) + bit_10 = (10,10) + immrel9 = (0,9) signed + immrel8 = (0,8) signed + xop8 = (0,7) + reg5 = (5,7) + ximm4 = (4,7) + ximm8 = (0,7) + op4 = (0,4) + op3 = (0,3) + offs5 = (0,5) + reg2 = (2,4) + op2 = (0,1) +; + +################################################################ +# Attach variables +################################################################ + +attach variables [reg8 reg5 reg2] [R0 R1 R2 R3 R4 R5 R6 R7]; + +attach variables [reg8_lo ] [R0.L R1.L R2.L R3.L R4.L R5.L R6.L R7.L]; +attach variables [reg8_hi ] [R0.H R1.H R2.H R3.H R4.H R5.H R6.H R7.H]; + +################################################################ +# Pseudo Instructions +################################################################ + +define pcodeop findFirstOne; +define pcodeop leftShiftCarry; +define pcodeop rightShiftCarry; +define pcodeop parity; +define pcodeop clearSemaphore; +define pcodeop setSemaphore; +define pcodeop setInterruptFlag; +define pcodeop TerminateThread; + +################################################################ +# Macros Instructions +################################################################ + +macro default_flags(result) +{ + $(XZ) = (result == 0); + $(XN) = (result s< 0); + $(XV) = 0; + #$(XC) not affected +} + +macro addition_flags(operand1, operand2, result) +{ + $(XN) = (result s< 0); + $(XZ) = ((result == 0) & ($(XZ)==1)); + $(XV) = (((operand1 & operand2 & ~result) | (~operand1 & ~operand2 & result)) & 0x8000) != 0; + $(XC) = (((operand1 & operand2) | (operand2 & ~result) | (~result & operand1)) & 0x8000) != 0; +} + +macro subtraction_flags(register, operand, result) { + $(XN) = (result s< 0); + $(XZ) = (result == 0); + $(XV) = ( ((register & ~operand & ~result) | (~register & operand & result)) & 0x8000 ) != 0; + $(XC) = ( ((~register & operand) | (operand & result) | (~register & result)) & 0x8000 ) != 0; +} + +macro subtraction_flagsB(register, operand, result) { + $(XN) = (result s< 0); + $(XZ) = (result == 0); + $(XV) = ( ((register & ~operand & ~result) | (~register & operand & result)) & 0x80 ) != 0; + $(XC) = ( ((~register & operand) | (operand & result) | (result & ~register)) & 0x80 ) != 0; +} + +macro subtraction_flagsC(register, operand, result) { + $(XN) = (result s< 0); + $(XZ) = ( (result == 0) & ($(XZ) == 1)); + $(XV) = ( ((register & ~operand & ~result) | (~register & operand & result)) & 0x8000 ) != 0; + $(XC) = ( ((~register & operand) | (operand & result) | (~register & result)) & 0x8000 ) != 0; +} + +macro shiftFlags(result,old) +{ + $(XN) = (result s< 0); + $(XZ) = (result == 0); + tmp:2 = (old >> 15) ^ (result >> 15); + $(XV) = tmp(1); +} + +macro getbit(res,in,bitnum) { + res = ((in >> bitnum) & 1) != 0; +} + +# +# computes a fake PPAGE page mapping based on the 16 bit input address +# The XGATE memory is mapped to the pages of physical memory +# Warning: This might not be the correct mapping on all XGATE processors +# +# 0000-07ff = 0x00_0000 - 0x00_07ff +# 0800-7fff = 0x78_0800 - XGFLASH_HIGH +# 8000-ffff = 0x0f_0800 - 0x0f_ffff +# +macro computePage(addr) { + local isReg:1 = addr < 0x800; + local isFlash:1 = addr >= 0x800 & addr < 0x7fff; + local isRam:1 = addr >= 0x8000; + physPage = (zext(isReg) * 0x0)+ (zext(isFlash) * (0x78 << 16)) + (zext(isRam) * (0xf<<16)); +} + +################################################################ +# Constructors +################################################################ + +#rel9 defined in HCS_HC12.sinc +# range -256 through +255 +with : XGATE=1 { +rel9: reloc is immrel8 [ reloc = inst_next + (immrel8 * 2); ] { export *:1 reloc; } + +# range -512 through +512 +rel10: reloc is immrel9 [ reloc = inst_next + (immrel9 * 2); ] { export *:1 reloc; } + +rd : reg8 is reg8 { export reg8; } + +rs1: reg5 is reg5 & reg5=0 { export 0:2; } +rs1: reg5 is reg5 { export reg5; } + +rs2: reg2 is reg2 & reg2=0 { export 0:2; } +rs2: reg2 is reg2 { export reg2; } + + +rd_lo: reg8 is reg8 & reg8_lo { export reg8_lo; } +rd_hi: reg8 is reg8 & reg8_hi { export reg8_hi; } + + + +# Add with carry +:ADC rd, rs1, rs2 is opcode=0x3 & rd & rs1 & rs2 & op2=0x3 +{ + local result:2 = rs1 + rs2 + zext($(XC)); + rd = result; + + addition_flags(rs1, rs2, result); +} + +# Add without carry +:ADD rd, rs1, rs2 is opcode=0x3 & rd & rs1 & rs2 & op2=0x2 +{ + local result:2 = rs1 + rs2; + rd = result; + + addition_flags(rs1, rs2, result); +} + +# Add immediate 8-bit constant (high byte) +:ADDH rd, ximm8 is opcode=0x1d & rd & ximm8 +{ + local val:2 = ximm8 << 8; + local result:2 = rd + val; + + addition_flags(rd, val, result); + + rd = result; +} + +# Add immediate 8-bit constant (low byte) +:ADDL rd, ximm8 is opcode=0x1c & rd & ximm8 +{ + local result:2 = rd + ximm8; + + $(XN) = (result s< 0); + $(XZ) = ((result == 0) & ($(XZ)==1)); + $(XV) = ((~rd & result) & 0x8000) != 0; + $(XC) = ((rd & ~result) & 0x8000) != 0; + rd = result; +} + +# Logical AND +:AND rd, rs1, rs2 is opcode=0x2 & rd & rs1 & rs2 & op2=0x0 +{ + rd = rs1 & rs2; + + default_flags(rd); +} + +# Logical AND immediate 8-bit constant (high byte) +:ANDH rd, ximm8 is opcode=0x11 & rd & ximm8 & rd_hi +{ + rd_hi = rd_hi & ximm8; + + default_flags(rd_hi); +} + +# Logical AND immediate 8-bit constant (low byte) +:ANDL rd, ximm8 is opcode=0x10 & rd & ximm8 & rd_lo +{ + rd_lo = rd_lo & ximm8; + + default_flags(rd_lo); +} + +# Arithmetic Shift Right +:ASR rd, ximm4 is opcode=0x1 & rd & ximm4 & op3=0x9 +{ + getbit($(XC), rd, ximm4-1); + rd = rd s>> ximm4; + + default_flags(rd); +} + +:ASR rd, rs1 is opcode=0x1 & rd & rs1 & op4=0x11 +{ + getbit($(XC), rd, rs1-1); + rd = rd s>> rs1; + + default_flags(rd); +} + +# Branch if Carry Cleared +:BCC rel9 is opcode=0x4 & op9_10=0x0 & rel9 +{ + if ($(XC) == 0) goto rel9; +} + + +# Branch if Carry Set +:BCS rel9 is opcode=0x4 & op9_10=0x1 & rel9 +{ + if ($(XC) == 1) goto rel9; +} + +# Branch of Equal +:BEQ rel9 is opcode=0x4 & op9_10=0x3 & rel9 +{ + if ($(XZ) == 1) goto rel9; +} + +# Bit Field Extract +:BFEXT rd, rs1, rs2 is opcode=0xc & rd & rs1 & rs2 & op2=0x3 +{ + local origin:2 = rs2 & 0xf; + local width:2 = (rs2 >> 4) & 0xf; + local mask:2 = (0xffff >> (16-(width + 1))) << origin; + local result:2 = (rs1 & mask) >> origin; + + rd = result; + + default_flags(rd); +} + +# Bit Field Find First One +:BFFO rd, rs1 is opcode=0x1 & rd & rs1 & op4=0x10 +{ + # 15 - count leading zeros + tmp:2 = rs1; + $(XC) = (rd == 0); + #TODO: implement findFirstOne behavior + rd = findFirstOne(tmp); + + default_flags(rd); +} + +# Bit Field Insert +:BFINS rd, rs1, rs2 is opcode=0xd & rd & rs1 & rs2 & op2=0x3 +{ + local origin:2 = rs2 & 0xf; + local width:2 = (rs2 >> 4) & 0xf; + local mask:2 = (0xffff >> (16-(width + 1))) << origin; + local result:2 = (rs1 & mask); + + rd = (rd & ~mask) | result; + + default_flags(rd); +} + +# Bit Field Insert and Invert +:BFINSI rd, rs1, rs2 is opcode=0xe & rd & rs1 & rs2 & op2=0x3 +{ + local origin:2 = rs2 & 0xf; + local width:2 = (rs2 >> 4) & 0xf; + local mask:2 = (0xffff >> (16-(width + 1))) << origin; + local result:2 = (~rs1 & mask); + + rd = (rd & ~mask) | result; + + default_flags(rd); +} + +# Bit Field Insert and XNOR +:BFINSX rd, rs1, rs2 is opcode=0xf & rd & rs1 & rs2 & op2=0x3 +{ + local origin:2 = rs2 & 0xf; + local width:2 = (rs2 >> 4) & 0xf; + local mask:2 = (0xffff >> (16-(width + 1))) << origin; + local result:2 = (~(rs1 ^ rd) & mask); + + rd = (rd & ~mask) | result; + + default_flags(rd); +} + +# Branch if Greater than or Equal to Zero +:BGE rel9 is opcode=0x6 & op9_10=0x2 & rel9 +{ + if (($(XN) ^ $(XV)) == 0) goto rel9; +} + +# Branch if Greater than Zero +:BGT rel9 is opcode=0x7 & op9_10=0x0 & rel9 +{ + if (($(XZ) | ($(XN) ^ $(XV))) == 0) goto rel9; +} + +# Branch if Higher +:BHI rel9 is opcode=0x6 & op9_10=0x0 & rel9 +{ + if (($(XC) | $(XZ)) == 0) goto rel9; +} + +#:BHS rel9 is opcode=0x4 & op9_10=0x0 & rel9 see BCC + +# Bit Test immediate 8-bit constant (high byte) +:BITH rd, ximm8 is opcode=0x13 & rd & ximm8 & rd_hi +{ + local val = rd_hi & ximm8; + + default_flags(val); +} + +# Bit Test immediate 8-bit constant (low byte) +:BITL reg8, ximm8 is opcode=0x12 & reg8 & ximm8 & rd_lo +{ + local val = rd_lo & ximm8; + + default_flags(val); +} + +# Branch if Less or Equal to Zero +:BLE rel9 is opcode=0x7 & op9_10=0x1 & rel9 +{ + if ($(XZ) | ($(XN) ^ $(XV))) goto rel9; +} + +#:BLO rel9 is opcode=0x4 & op9_10=0x1 & rel9 See BCS + +# Branch if Lower or Same +:BLS rel9 is opcode=0x6 & op9_10=0x1 & rel9 +{ + if (($(XC) | $(XZ)) == 1) goto rel9; +} + +# Branch of Lower than Zero +:BLT rel9 is opcode=0x6 & op9_10=0x3 & rel9 +{ + if (($(XN) ^ $(XV)) == 1) goto rel9; +} + +# Branch if Minus +:BMI rel9 is opcode=0x5 & op9_10=0x1 & rel9 +{ + if ($(XN) == 1) goto rel9; +} + +# Branch if Not Equal +:BNE rel9 is opcode=0x4 & op9_10=0x2 & rel9 +{ + if ($(XZ) == 0) goto rel9; +} + +# Branch if Plus +:BPL rel9 is opcode=0x5 & op9_10=0x0 & rel9 +{ + if ($(XN) == 0) goto rel9; +} + +# Branch Always +:BRA rel10 is opcode=0x7 & bit_10=0x1 & rel10 +{ + goto rel10; +} +# Break +:BRK is xop16=0x0 +{ + # put xgate into debug mode and set breakpoint + goto inst_next; +} + +# Branch if Overflow Cleared +:BVC rel9 is opcode=0x5 & op9_10=0x2 & rel9 +{ + if ($(XV) == 0) goto rel9; +} + +# Branch if Overflow Set +:BVS rel9 is opcode=0x5 & op9_10=0x3 & rel9 +{ + if ($(XV) == 2) goto rel9; +} + +# Compare +# synonym for SUB R0, RS1, RS2 +:CMP rs1, rs2 is opcode=0x3 & reg8=0x0 & rs1 & rs2 & op2=0x0 +{ + tmp:2 = rs1 - rs2; + subtraction_flags(rs1, rs2, tmp); +} + +# Compare Immediate 8-bit constant (low byte) +:CMPL rd, ximm8 is opcode=0x1a & rd & ximm8 +{ + local val:1 = rd:1; + local tmp:1 = val - ximm8; + local xtmp:1 = ximm8; + subtraction_flagsB(val, xtmp, tmp); +} + +# One's Complement +:COM rd, rs2 is opcode=0x2 & rd & reg5=0x0 & rs2 & op2=0x3 +{ + local val:2 = ~rs2; + rd = val; + + default_flags(rd); +} + +:COM rd is opcode=0x2 & rd & reg5=0x0 & rs2 & reg8=reg2 & op2=0x3 +{ + local val:2 = ~rs2; + rd = val; + + default_flags(rd); +} + +# Compare with Carry +:CPC rs1, rs2 is opcode=0x3 & reg8=0x0 & rs1 & rs2 & op2=0x1 +{ + local tmp:2 = rs1 - rs2 - zext($(XC)); + subtraction_flags(rs1, rs2, tmp); +} + +# Compare Immediate 8-bit constant with carry (high byte) +:CPCH rd, ximm8 is opcode=0x1b & rd & ximm8 +{ + local val:2 = rd >> 8; + local tmp:1 = val(1) - ximm8 - $(XC); + local xtmp:1 = ximm8; + subtraction_flagsB(val(1), xtmp, tmp); +} + +# Clear Semaphore +:CSEM rd is opcode=0x0 & rd & xop8=0xf0 +{ + # treat as NOP + clearSemaphore(rd); +} + +:CSEM imm3 is opcode=0x0 & imm3 & xop8=0xf1 +{ + local sem:1 = imm3; + clearSemaphore(sem); +} + + +# Logical Shift Left with Carry +:CSL rd, ximm4 is opcode=0x1 & rd & ximm4 & op3=0xa +{ + local Ctmp:2 = zext($(XC)); + local shift:2 = ((ximm4-1)%16+1); + local oldRd:2 = rd >> 15; + getbit($(XC), rd, 16-shift); + leftShiftCarry(rd,Ctmp,shift,rd); + shiftFlags(rd,oldRd); +} + +:CSL rd, rs1 is opcode=0x1 & rd & rs1 & op4=0x12 +{ + local Ctmp:2 = zext($(XC)); + #if rs1 > 16, then rs1 = 16 + local rsgt:2 = zext(rs1>16); + local rslt:2 = zext(rs1<16); + local shift:2 = rs1*rsgt + 16*rslt; + local oldRd:2 = rd >> 15; + getbit($(XC), rd, 16-shift); + leftShiftCarry(rd,Ctmp,shift,rd); + shiftFlags(rd,oldRd); +} + +# Logical Shift Right with Carry +:CSR rd, ximm4 is opcode=0x1 & rd & ximm4 & op3=0xb +{ + local Ctmp:2 = zext($(XC)); + local shift:2 = ((ximm4-1)%16+1); + local oldRd:2 = rd >> 15; + getbit($(XC), rd, shift-1); + rightShiftCarry(rd,Ctmp,shift,rd); + shiftFlags(rd,oldRd); +} + +:CSR rd, rs1 is opcode=0x1 & rd & rs1 & op4=0x13 +{ + local Ctmp:2 = zext($(XC)); + #if rs1 > 16, then rs1 = 16 + local rsgt:2 = zext(rs1>16); + local rslt:2 = zext(rs1<16); + local shift:2 = rs1*rsgt + 16*rslt; + local oldRd:2 = rd >> 15; + getbit($(XC), rd, shift-1); + rightShiftCarry(rd,Ctmp,shift,rd); + shiftFlags(rd,oldRd); +} + +:CSR rd, rs1 is opcode=0x1 & rd & rs1 & reg5=0 & op4=0x13 +{ + $(XN) = (rd s< 0); + $(XZ) = (rd == 0); + $(XV) = 0; + # $(XC) is unaffected +} + +# Jump and Link +:JAL rd is opcode=0x0 & rd & xop8=0xf6 +{ + local dest:2 = rd; + rd = inst_next; + call [dest]; +} + +# Load byte from memory (low byte) +:LDB rd, (rs1, offs5) is opcode=0x8 & rd & rs1 & offs5 +{ + local addr = rs1 + offs5; + computePage(addr); + local dst:3 = segment(PPAGE,addr); + local val:1 = *:1 (dst); + rd = (rd & 0xff00) | zext(val); +} + +:LDB rd, (rs1, rs2) is opcode=0xc & rd & rs1 & rs2 & op2=0x0 +{ + local addr = rs1 + rs2; + computePage(addr); + local dst:3 = segment(PPAGE,addr); + local val:1 = *:1 (dst); + rd = (rd & 0xff00) | zext(val); +} + +:LDB rd, (rs1, rs2+) is opcode=0xc & rd & rs1 & rs2 & op2=0x1 +{ + local addr = rs1 + rs2; + computePage(addr); + local dst:3 = segment(PPAGE,addr); + local val:1 = *:1 (dst); + rd = (rd & 0xff00) | zext(val); + rs1 = rs1 + 1; +} + +:LDB rd, (rs1, -rs2) is opcode=0xc & rd & rs1 & rs2 & op2=0x2 +{ + rs2 = rs2 - 1; + local addr = rs1 + rs2; + computePage(addr); + local dst:3 = segment(PPAGE,addr); + local val:1 = *:1 (dst); + rd = (rd & 0xff00) | zext(val); +} + + +# Load Immediate 8-bit constant (high byte) +:LDH rd, ximm8 is opcode=0x1f & rd & ximm8 & rd_hi +{ + rd_hi = ximm8; +} + + +# Load Immediate 8-bit constant (low byte) +:LDL rd, ximm8 is opcode=0x1e & rd & ximm8 +{ + rd = ximm8; +} + +# Load Word from Memory +:LDW rd, (rs1, offs5) is opcode=0x9 & rd & rs1 & offs5 +{ + local addr = rs1 + offs5; + computePage(addr); + local dst:3 = segment(PPAGE,addr); + local val:2 = *:2 (dst); + rd = val; +} + +:LDW rd, (rs1, rs2) is opcode=0xd & rd & rs1 & rs2 & op2=0x0 +{ + local addr = rs1 + rs2; + computePage(addr); + local dst:3 = segment(PPAGE,addr); + local val:2 = *:2 (dst); + rd = val; +} + +:LDW rd, (rs1, rs2+) is opcode=0xd & rd & rs1 & rs2 & op2=0x1 +{ + local addr = rs1 + rs2; + computePage(addr); + local dst:3 = segment(PPAGE,addr); + local val:2 = *:2 (dst); + rd = val; + rs1 = rs1 + 2; +} +:LDW rd, (rs1, -rs2) is opcode=0xd & rd & rs1 & rs2 & op2=0x2 +{ + rs2 = rs2 - 2; + local addr = rs1 + rs2; + computePage(addr); + local dst:3 = segment(PPAGE,addr); + local val:2 = *:2 (dst); + rd = val; +} + +# Logical Shift Left +:LSL rd, ximm4 is opcode=0x1 & rd & ximm4 & op3=0xc +{ + local shift:2 = ((ximm4-1)%16+1); + getbit($(XC), rd, 16-shift); + local oldRd:2 = rd >> 15; + rd = rd << shift; + shiftFlags(rd,oldRd); +} + +:LSL rd, rs1 is opcode=0x1 & rd & rs1 & op4=0x14 +{ + getbit($(XC), rd, 16-rs1); + local oldRd:2 = rd >> 15; + rd = rd << rs1; + shiftFlags(rd,oldRd); +} + +# Logical Shift Right +:LSR rd, ximm4 is opcode=0x1 & rd & ximm4 & op3=0xd +{ + getbit($(XC), rd, ximm4-1); + local oldRd:2 = rd >> 15; + rd = rd >> ximm4; + shiftFlags(rd,oldRd); +} + +:LSR rd, rs1 is opcode=0x1 & rd & rs1 & op4=0x15 +{ + getbit($(XC), rd, rs1-1); + local oldRd:2 = (rd >> 15); + rd = rd >> rs1; + shiftFlags(rd,oldRd); +} + +# Move Register Content +# Synonym for OR RD, R0, RS +:MOV rd, rs2 is opcode=0x2 & rd & reg5=0 & rs2 & op2=0x2 +{ + rd = rs2; + + default_flags(rd); +} + +# Two's Complement +:NEG rd, rs2 is opcode=0x3 & rd & reg8!=0 & reg5=0x0 & rs2 & op2=0x0 +{ + local tmp:2 = -rs2; + rd = tmp; + $(XN) = (rd s< 0); + $(XZ) = (rd == 0); + $(XV) = (((rs2 & rd) & 0x8000) != 0); + $(XC) = (((rs2 | rd) & 0x8000) != 0); +} + +:NEG rd is opcode=0x3 & rd & reg5=0x0 & rs2 & reg2=reg8 & op2=0x0 +{ + local tmp:2 = -rs2; + rd = tmp; + $(XN) = (rd s< 0); + $(XZ) = (rd == 0); + $(XV) = (((rs2 & rd) & 0x8000) != 0); + $(XC) = (((rs2 | rd) & 0x8000) != 0); +} + +# No Op +:NOP is xop16=0x100 {} + +# Logical OR +:OR rd, rs1, rs2 is opcode=0x2 & rd & rs1 & rs2 & op2=0x2 +{ + local result:2 = rs1 | rs2; + rd = result; + + default_flags(result); +} + +# Logical OR Immediate 8-bit Constant (high byte) +:ORH rd, ximm8 is opcode=0x15 & rd & ximm8 & rd_hi +{ + rd_hi = rd_hi | ximm8; + + default_flags(rd_hi); +} + +# Logical OR Immediate 8-bit Constant (low byte) +:ORL rd, ximm8 is opcode=0x14 & rd & ximm8 & rd_lo +{ + rd_lo = rd_lo | ximm8; + + default_flags(rd_lo); +} + +# Calculate Parity +:PAR rd is opcode=0x0 & rd & xop8=0xf5 +{ + parity(rd, $(XC)); + + default_flags(rd); +} + +# Rotate Left +:ROL rd, ximm4 is opcode=0x1 & rd & ximm4 & op3=0xe +{ + local cnt:2 = ximm4; + rd = (rd << cnt) | (rd >> (16 - cnt)); + + default_flags(rd); +} + +:ROL rd, rs1 is opcode=0x1 & rd & rs1 & op4=0x16 +{ + local cnt:2 = rs1 & 0xf; + rd = (rd << cnt) | (rd >> (16 - cnt)); + + default_flags(rd); +} + +# Rotate Right +:ROR rd, ximm4 is opcode=0x1 & rd & ximm4 & op3=0xf +{ + local cnt:2 = ximm4; + rd = (rd >> cnt) | (rd << (16 - cnt)); + + default_flags(rd); +} + +:ROR rd, rs1 is opcode=0x1 & rd & rs1 & op4=0x17 +{ + local cnt:2 = rs1 & 0xf; + rd = (rd >> cnt) | (rd << (16 - cnt)); + + default_flags(rd); +} +# Return to Scheduler +# Implement as NOP for now +:RTS is xop16=0x0200 { + XPC = TerminateThread(); + return [XPC]; +} + +# Subtract with Carry +:SBC rd, rs1, rs2 is opcode=0x3 & rd & rs1 & rs2 & op2=0x1 +{ + local result:2 = rs1 - rs2 - zext($(XC)); + rd = result; + subtraction_flagsC(rs1, rs2, result); +} + +# Sign Extent Byte to Word +:SEX rd is opcode=0x0 & rd & xop8=0xf4 +{ + local result:1 = rd:1 & 0xff; + rd = sext(result); + + default_flags(rd); +} +# Set Interrupt Flag +# TODO: implement interrupt flags +:SIF is xop16=0x0300 +{ + setInterruptFlag(); +} + +:SIF rd is opcode=0x0 & rd & xop8=0xf7 +{ + setInterruptFlag(); +} + +# Set Semaphore +# TODO: implement semaphores +:SSEM imm3 is opcode=0x0 & imm3 & xop8=0xf2 +{ + local sem:1 = imm3; + setSemaphore(sem); +} + +:SSEM rd is opcode=0x0 & rd & xop8=0xf3 +{ + setSemaphore(rd); +} + +# Store Byte to Memory (low byte) +:STB rd, (rs1, offs5) is opcode=0xa & rd & rs1 & offs5 +{ + local addr = rs1 + offs5; + computePage(addr); + local dst:3 = segment(PPAGE,addr); + local val:1 = rd:1; + *dst = val; +} + +:STB rd, (rs1, rs2) is opcode=0xe & rd & rs1 & rs2 & op2=0x0 +{ + local addr = rs1 + rs2; + computePage(addr); + local dst:3 = segment(PPAGE,addr); + local val:1 = rd:1; + *dst = val; +} + +:STB rd, (rs1, rs2+) is opcode=0xe & rd & rs1 & rs2 & op2=0x1 +{ + local addr = rs1 + rs2; + computePage(addr); + local dst:3 = segment(PPAGE,addr); + local val:1 = rd:1; + *dst = val; + rs2 = rs2 + 1; +} + +:STB rd, (rs1, -rs2) is opcode=0xe & rd & rs1 & rs2 & op2=0x2 +{ + rs2 = rs2 - 1; + local addr = rs1 + rs2; + computePage(addr); + local dst:3 = segment(PPAGE,addr); + local val:1 = rd:1; + *dst = val; +} + +# Store Word to Memory +:STW rd, (rs1, offs5) is opcode=0xb & rd & rs1 & offs5 +{ + local addr = rs1 + offs5; + computePage(addr); + local dst:3 = segment(PPAGE,addr); + local val:2 = rd; + *dst = val; +} + +:STW rd, (rs1, rs2) is opcode=0xf & rd & rs1 & rs2 & op2=0x0 +{ + local addr = rs1 + rs2; + computePage(addr); + local dst:3 = segment(PPAGE,addr); + local val:2 = rd; + *dst = val; + rs2 = rs2 + 1; +} + +:STW rd, (rs1, rs2+) is opcode=0xf & rd & rs1 & rs2 & op2=0x1 +{ + local addr = rs1 + rs2; + computePage(addr); + local dst:3 = segment(PPAGE,addr); + local val:2 = rd; + *dst = val; + rs2 = rs2 + 2; +} + +:STW rd, (rs1, -rs2) is opcode=0xf & rd & rs1 & rs2 & op2=0x2 +{ + rs2 = rs2 - 2; + local addr = rs1 + rs2; + computePage(addr); + local dst:3 = segment(PPAGE,addr); + local val:2 = rd; + *dst = val; +} + +# Subtract without Carry +:SUB rd, rs1, rs2 is opcode=0x3 & rd & rs1 & rs2 & op2=0x0 +{ + local result:2 = rs1 - rs2; + rd = result; + + subtraction_flags(rs1, rs2, result); +} + + +# Subtract Immediate 8-bit constant (high byte) +:SUBH rd, ximm8 is opcode=0x19 & rd & ximm8 +{ + local val:2 = ximm8 << 8; + local result:2 = rd - val; + + subtraction_flags(rd, val, result); + + rd = result; +} + +# Subtract Immediate 8-bit constant (low byte) +:SUBL rd, ximm8 is opcode=0x18 & rd & ximm8 +{ + local val:2 = ximm8; + local result:2 = rd - val; + + $(XN) = (result s< 0); + $(XZ) = ((result == 0) & ($(XZ)==1)); + $(XV) = ((~rd & result) & 0x8000) != 0; + $(XC) = ((rd & ~result) & 0x8000) != 0; + rd = result; +} + +# Transfer from and to Special Registers +:TFR rd, XCCR is opcode=0x0 & rd & xop8=0xf8 & XCCR +{ + local val:1 = ((($(XN) << 1) | $(XZ) << 1) | $(XV) << 1) | $(XC); + rd = zext(val); +} + +:TFR XCCR, rd is opcode=0x0 & rd & xop8=0xf9 & XCCR +{ + XCCR = rd & 0xf; + $(XN) = rd[3,1]; + $(XZ) = rd[2,1]; + $(XV) = rd[1,1]; + $(XC) = rd[0,1]; +} + +:TFR rd, XPC is opcode=0x0 & rd & xop8=0xfa & XPC +{ + rd = inst_next + 2; +} + +# Test Register +# Synonym for SUB R0, RS, R0 +:TST rs1 is opcode=0x3 & reg8=0x0 & rs1 & reg2=0x0 & op2=0x0 +{ + local result:2 = rs1; + + subtraction_flags(rs1,0,result); +} + +# Logical Exclusive NOR +:XNOR rd, rs1, rs2 is opcode=0x2 & rd & rs1 & rs2 & op2=0x3 +{ + local result:2 = ~(rs1 ^ rs2); + rd = result; + + default_flags(result); +} + +# Logical Exclusive NOR Immediate 8-bit constant (high byte) +:XNORH rd, ximm8 is opcode=0x17 & rd & ximm8 & rd_hi +{ + rd_hi = ~(rd_hi ^ ximm8); + + default_flags(rd_hi); +} + +# Logical Exclusive NOR Immediate 8-bit constant (low byte) +:XNORL rd, ximm8 is opcode=0x16 & rd & ximm8 & rd_lo +{ + rd_lo= ~(rd_lo^ ximm8); + + default_flags(rd_lo); +} + +} \ No newline at end of file diff --git a/python/icicle/Ghidra/Processors/JVM/data/languages/JVM.cspec b/python/icicle/Ghidra/Processors/JVM/data/languages/JVM.cspec new file mode 100644 index 0000000..a1e6dc8 --- /dev/null +++ b/python/icicle/Ghidra/Processors/JVM/data/languages/JVM.cspec @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/JVM/data/languages/JVM.ldefs b/python/icicle/Ghidra/Processors/JVM/data/languages/JVM.ldefs new file mode 100644 index 0000000..f260947 --- /dev/null +++ b/python/icicle/Ghidra/Processors/JVM/data/languages/JVM.ldefs @@ -0,0 +1,17 @@ + + + + + Generic JVM + + + + diff --git a/python/icicle/Ghidra/Processors/JVM/data/languages/JVM.opinion b/python/icicle/Ghidra/Processors/JVM/data/languages/JVM.opinion new file mode 100644 index 0000000..1e2114f --- /dev/null +++ b/python/icicle/Ghidra/Processors/JVM/data/languages/JVM.opinion @@ -0,0 +1,5 @@ + + + + + diff --git a/python/icicle/Ghidra/Processors/JVM/data/languages/JVM.pspec b/python/icicle/Ghidra/Processors/JVM/data/languages/JVM.pspec new file mode 100644 index 0000000..5b9340f --- /dev/null +++ b/python/icicle/Ghidra/Processors/JVM/data/languages/JVM.pspec @@ -0,0 +1,71 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/JVM/data/languages/JVM.slaspec b/python/icicle/Ghidra/Processors/JVM/data/languages/JVM.slaspec new file mode 100644 index 0000000..25dcdfd --- /dev/null +++ b/python/icicle/Ghidra/Processors/JVM/data/languages/JVM.slaspec @@ -0,0 +1,2158 @@ +# Stack Convention: +# 1) Stack grows to smaller addresses (Subtract to push) +# 2) Stack pointer points to a valid item on the stack + +# A Java "word" can hold a boolean, byte, short, float, int, reference, or returnAddress. +# Two "words" hold a long or a double +@define SIZE "4" # Number of bytes in the Java Word +@define DOUBLE_SIZE "8" +@define INT_SUPPORT "1" + + + +############################################################################### +# Basic Definitions +############################################################################### +define endian=big; +define alignment=1; + +define space ram type=ram_space size=$(SIZE) default; +define space register type=register_space size=$(SIZE); +define space constantPool type=ram_space size=$(SIZE); +define space localVariableArray type=ram_space size=$(SIZE); +define space parameterSpace type=ram_space size=$(SIZE); + +define register offset = 0x0 size=$(DOUBLE_SIZE) [cat2_return_value]; +define register offset = 0x0 size=$(SIZE) [_ return_value SP PC switch_target return_address call_target LVA]; + +#define register offset = 0x0 size=$(DOUBLE_SIZE) [cat2_return_value]; +#define register offset = 0x8 size=$(SIZE) [return_value SP PC switch_target return_address call_target LVA]; + +define register offset=0x100 size=16 [ switch_ctrl ]; + +@define CPOOL_ANEWARRAY "0:4" +@define CPOOL_CHECKCAST "1:4" +@define CPOOL_GETFIELD "2:4" +@define CPOOL_GETSTATIC "3:4" + +#also used for ldc_w +@define CPOOL_LDC "4:4" + +@define CPOOL_LDC2_W "5:4" +@define CPOOL_INSTANCEOF "6:4" +@define CPOOL_INVOKEDYNAMIC "7:4" +@define CPOOL_INVOKEINTERFACE "8:4" +@define CPOOL_INVOKESPECIAL "9:4" +@define CPOOL_INVOKESTATIC "10:4" +@define CPOOL_INVOKEVIRTUAL "11:4" +@define CPOOL_MULTIANEWARRAY "12:4" +@define CPOOL_NEW "13:4" +@define CPOOL_NEWARRAY "14:4" +@define CPOOL_PUTSTATIC "15:4" +@define CPOOL_PUTFIELD "16:4" +@define CPOOL_ARRAYLENGTH "17:4" + +# +#defined ops ending in "CallOther" are used for pcode injection +# + +define pcodeop getFieldCallOther; +define pcodeop getStaticCallOther; +define pcodeop ldcCallOther; +define pcodeop ldc_wCallOther; +define pcodeop ldc2_wCallOther; +define pcodeop invokedynamicCallOther; +define pcodeop invokeinterfaceCallOther; +define pcodeop invokespecialCallOther; +define pcodeop invokestaticCallOther; +define pcodeop invokevirtualCallOther; +define pcodeop multianewarrayCallOther; +define pcodeop putStaticCallOther; +define pcodeop putFieldCallOther; + +# +# defined ops ending in "Op" are black-box instructions +# + +define pcodeop athrowOp; +define pcodeop checkcastOp; +define pcodeop dremOp; +define pcodeop fremOp; +define pcodeop monitorenterOp; +define pcodeop monitorexitOp; +define pcodeop multianewarrayOp; +define pcodeop multianewarrayProcessAdditionalDimensionsOp; +define pcodeop throwExceptionOp; + +############################################################################### +# Context +############################################################################### + +define context switch_ctrl + switch_low = (0,31) noflow + switch_high = (32,63) noflow + switch_num = (64,95) noflow + in_table_switch = (96,97) noflow + in_lookup_switch = (98,99) noflow + alignmentPad = (100,101) noflow + padVal = (100,101) noflow +; + + +############################################################################### +# TOKENS +############################################################################### +define token opcode (8) + op = (0,7) +; + +define token w_opcode (16) + w_op = (0,15) +; + +define token data8 (8) + n = (0,3) + m = (4,7) + atype = (0,7) + byte = (0,7) + byte1 = (0,7) + byte2 = (0,7) + byte3 = (0,7) + byte4 = (0,7) + sbyte = (0,7) signed + branch = (0,7) signed + branchbyte1 = (0,7) signed + branchbyte2 = (0,7) + branchbyte3 = (0,7) + branchbyte4 = (0,7) + index = (0,7) + indexbyte1 = (0,7) + indexbyte2 = (0,7) + constant = (0,7) + constantbyte1= (0,7) + constantbyte2= (0,7) + nargs = (0,7) + method = (0,7) + defaultbyte1 = (0,7) + defaultbyte2 = (0,7) + defaultbyte3 = (0,7) + defaultbyte4 = (0,7) + highbyte1 = (0,7) + highbyte2 = (0,7) + highbyte3 = (0,7) + highbyte4 = (0,7) + lowbyte1 = (0,7) + lowbyte2 = (0,7) + lowbyte3 = (0,7) + lowbyte4 = (0,7) + npairsbyte1 = (0,7) + npairsbyte2 = (0,7) + npairsbyte3 = (0,7) + npairsbyte4 = (0,7) + dimensions = (0,7) + blank1 = (0,7) + blank2 = (0,7) + count = (0,7) + pad = (0,7) + pad1 = (0,7) + pad2 = (0,7) + pad3 = (0,7) + wide_op = (0,7) +; + +define token switch (8) + matchbyte1 = (0,7) + matchbyte2 = (0,7) + matchbyte3 = (0,7) + matchbyte4 = (0,7) + offsetbyte1 = (0,7) + offsetbyte2 = (0,7) + offsetbyte3 = (0,7) + offsetbyte4 = (0,7) +; + +############################################################################### +# Macros +############################################################################### +macro push(x) +{ + SP = SP - $(SIZE); + *:$(SIZE) SP = x; +} + +macro pop(x) +{ + x = *:$(SIZE) SP; + SP = SP + $(SIZE); +} + +macro push2(x) +{ + SP = SP - $(DOUBLE_SIZE); + *:$(DOUBLE_SIZE) SP = x:$(DOUBLE_SIZE); +} + +macro pop2(x) +{ + x = *:$(DOUBLE_SIZE) SP; + SP = SP + $(DOUBLE_SIZE); +} + +############################################################################### +# Pseudo Instructions +############################################################################### +Branch:addr is branchbyte1; branchbyte2 [ addr = inst_start + (branchbyte1<<8 | branchbyte2); ] +{ + export *:$(SIZE) addr; +} + +Branch_w:addr is branchbyte1; branchbyte2; branchbyte3; branchbyte4 [ addr = inst_start + ((branchbyte1 << 24) | (branchbyte2 << 16) | (branchbyte3 << 8) | branchbyte4); ] +{ + export *:$(SIZE) addr; +} + +Default:"default" addr is defaultbyte1; defaultbyte2; defaultbyte3; defaultbyte4 [ addr = inst_start + ((defaultbyte1<<24) | (defaultbyte2<<16) | (defaultbyte3 << 8) | defaultbyte4); ] +{ + export *:$(SIZE) addr; +} + +############################################################################### +# Constructors +############################################################################### +:aaload is (in_table_switch=0 & in_lookup_switch=0 & op=0x32) +{ + _index :$(SIZE) = 0; + _arrayref :$(SIZE) = 0; + pop(_index); + pop(_arrayref); + _offset:$(SIZE) = _arrayref + $(SIZE) * _index; + _value:$(SIZE) = *[ram] _offset; + push(_value); +} + +:aastore is (in_table_switch=0 & in_lookup_switch=0 & op=0x53) +{ + _index :$(SIZE) = 0; + _arrayref :$(SIZE) = 0; + _value :$(SIZE) = 0; + + pop(_value); + pop(_index); + pop(_arrayref); + _offset:$(SIZE) = _arrayref + $(SIZE) * _index; + *[ram]:$(SIZE) _offset = _value; +} + +:aconst_null is (in_table_switch=0 & in_lookup_switch=0 & op=0x01) +{ + push(0:4); +} + +:aload index is (in_table_switch=0 & in_lookup_switch=0 & op=0x19); index +{ + LVA = $(SIZE) * index; + _objectref :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA); + push(_objectref); +} + +:aload_0 is (in_table_switch=0 & in_lookup_switch=0 & op=0x2a) +{ + LVA = 0; + _objectref :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA); + push(_objectref); +} + +:aload_1 is (in_table_switch=0 & in_lookup_switch=0 & op=0x2b) +{ + LVA = 1 * $(SIZE); + _objectref :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA); + push(_objectref); +} + +:aload_2 is (in_table_switch=0 & in_lookup_switch=0 & op=0x2c) +{ + LVA = 2 * $(SIZE); + _objectref :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA); + push(_objectref); +} + +:aload_3 is (in_table_switch=0 & in_lookup_switch=0 & op=0x2d) +{ + LVA = 3 * $(SIZE); + _objectref :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA); + push(_objectref); +} + +:anewarray index is (in_table_switch=0 & in_lookup_switch=0 & op=0xbd); indexbyte1; indexbyte2 [ index = indexbyte1<<8 | indexbyte2; ] +{ + _count :$(SIZE) = 0; + _arrayref :$(SIZE) = 0; + pop(_count); + _ref: $(SIZE) = cpool(0:4,index,$(CPOOL_ANEWARRAY)); + _arrayref = newobject(_ref,_count); + push(_arrayref); +} + +:areturn is (in_table_switch=0 & in_lookup_switch=0 & op=0xb0) +{ + pop(return_value); + return [return_address]; +} + +:arraylength is (in_table_switch=0 & in_lookup_switch=0 & op=0xbe) +{ + _arrayref :$(SIZE) = 0; + _length :$(SIZE) = 0; + pop(_arrayref); + _length = cpool(_arrayref, 0:4, $(CPOOL_ARRAYLENGTH)); + push(_length); +} + +:astore index is (in_table_switch=0 & in_lookup_switch=0 & op=0x3a); index +{ + _value :$(SIZE) = 0; + pop(_value); + LVA = index*$(SIZE); + *[localVariableArray]:$(SIZE) (LVA) = _value; +} + +:astore_0 is (in_table_switch=0 & in_lookup_switch=0 & op=0x4b) +{ + _value :$(SIZE) = 0; + pop(_value); + LVA = 0; + *[localVariableArray]:$(SIZE) (LVA) = _value; +} + +:astore_1 is (in_table_switch=0 & in_lookup_switch=0 & op=0x4c) +{ + _value :$(SIZE) = 0; + pop(_value); + LVA = 1 * $(SIZE); + *[localVariableArray]:$(SIZE) (LVA) = _value; +} + +:astore_2 is (in_table_switch=0 & in_lookup_switch=0 & op=0x4d) +{ + _value :$(SIZE) = 0; + pop(_value); + LVA = 2 * $(SIZE); + *[localVariableArray]:$(SIZE) (LVA) = _value; + +} + +:astore_3 is (in_table_switch=0 & in_lookup_switch=0 & op=0x4e) +{ + _value :$(SIZE) = 0; + pop(_value); + LVA = 3 * $(SIZE); + *[localVariableArray]:$(SIZE) (LVA) = _value; +} + +:athrow is (in_table_switch=0 & in_lookup_switch=0 & op=0xbf) +{ + _objectref :$(SIZE) = 0; + pop(_objectref); + athrowOp(_objectref); + + SP = SP; + goto ; +} + +:baload is (in_table_switch=0 & in_lookup_switch=0 & op=0x33) +{ + _index :$(SIZE) = 0; + _arrayref :$(SIZE) = 0; + _value:1 = 0; + pop(_index); + pop(_arrayref); + _offset: $(SIZE) = _arrayref + _index; + _value = *[ram]:1 _offset; + _valueSignExtended:$(SIZE) = sext(_value); + push(_valueSignExtended); +} + +:bastore is (in_table_switch=0 & in_lookup_switch=0 & op=0x54) +{ + _value :$(SIZE) = 0; + _index :$(SIZE) = 0; + _arrayref :$(SIZE) = 0; + pop(_value); + pop(_index); + pop(_arrayref); + _offset: $(SIZE) = _arrayref + _index; + *[ram]:1 _offset = _value:1; +} + +:bipush sbyte is (in_table_switch=0 & in_lookup_switch=0 & op=0x10); sbyte +{ + _value:$(SIZE) = sext(sbyte:1); + push(_value); +} + +:caload is (in_table_switch=0 & in_lookup_switch=0 & op=0x34) +{ + _index :$(SIZE) = 0; + _arrayref :$(SIZE) = 0; + _value:2 = 0; + pop(_index); + pop(_arrayref); + _offset: $(SIZE) = _arrayref + 2 * _index; + _value = *[ram]:2 _offset; + _valueZeroExtended:$(SIZE) = zext(_value); + push(_valueZeroExtended); +} + +:castore is (in_table_switch=0 & in_lookup_switch=0 & op = 0x55) +{ + _value :$(SIZE) = 0; + _index :$(SIZE) = 0; + _arrayref :$(SIZE) = 0; + pop(_value); + pop(_index); + pop(_arrayref); + _offset: $(SIZE) = _arrayref + 2 * _index; + *[ram]:2 _offset = _value:2; +} + +:checkcast index is (in_table_switch=0 & in_lookup_switch=0 & op=0xc0); indexbyte1; indexbyte2 [ index = indexbyte1<<8 | indexbyte2; ] +{ + #_object: $(SIZE) = *:$(SIZE) SP; + #throwExceptionOp(_object); + + #_res:1 = cpool(_object,index,$(CPOOL_CHECKCAST)); + #throwExceptionOp(_res); + + + #_ref: $(SIZE) = cpool(0:4,index,$(CPOOL_CHECKCAST)); + #checkcastOp(_object,_ref); + + _object:$(SIZE) = 0; + pop(_object); + _object = cpool(_object,index,$(CPOOL_CHECKCAST)); + push(_object); + + #_res:1 = cpool(_object,index,$(CPOOL_CHECKCAST)); + #_result:$(SIZE) = zext(_res); + #push(_result); +} + +:d2f is (in_table_switch=0 & in_lookup_switch=0 & op=0x90) +{ + _double :$(DOUBLE_SIZE) = 0; + _float :$(SIZE) = 0; + pop2(_double); + _float = float2float(_double); + push(_float); +} + +#this is not exactly the algorithm that the JVM uses to convert doubles to ints +#should be good enough +:d2i is (in_table_switch=0 & in_lookup_switch=0 & op=0x8e) +{ + _double :$(DOUBLE_SIZE) = 0; + _int :$(DOUBLE_SIZE) = 0; + pop2(_double); + _int = round(_double); + push(_int:$(SIZE)); +} + +#this is not exactly the algorithm that the JVM uses to convert doubles to longs +:d2l is (in_table_switch=0 & in_lookup_switch=0 & op=0x8f) +{ + _double :$(DOUBLE_SIZE) = 0; + _long :$(DOUBLE_SIZE) = 0; + pop2(_double); + _long = round(_double); + push2(_long); +} + +:dadd is (in_table_switch=0 & in_lookup_switch=0 & op=0x63) +{ + _value1 :$(DOUBLE_SIZE) = 0; + _value2 :$(DOUBLE_SIZE) = 0; + _result :$(DOUBLE_SIZE) = 0; + pop2(_value2); + pop2(_value1); + _result = _value1 f+ _value2; + push2(_result); +} + +:daload is (in_table_switch=0 & in_lookup_switch=0 & op=0x31) +{ + _index :$(SIZE) = 0; + _arrayref :$(SIZE) = 0; + _value :$(DOUBLE_SIZE) = 0; + pop(_index); + pop(_arrayref); + _offset: $(SIZE) = _arrayref + $(DOUBLE_SIZE) * _index; + _value = *[ram]:$(DOUBLE_SIZE) _offset; + push2(_value); +} + +:dastore is (in_table_switch=0 & in_lookup_switch=0 & op=0x52) +{ + _value :$(DOUBLE_SIZE) = 0; + _index:$(SIZE) = 0; + _arrayref:$(SIZE) = 0; + pop2(_value); + pop(_index); + pop(_arrayref); + _offset: $(SIZE) = _arrayref + $(DOUBLE_SIZE) * _index; + *[ram]:$(DOUBLE_SIZE) _offset = _value; +} + +:dcmpg is (in_table_switch=0 & in_lookup_switch=0 & op=0x98) +{ + _value2 :$(DOUBLE_SIZE) = 0; + _value1 :$(DOUBLE_SIZE) = 0; + _result :$(SIZE) = 0; + pop2(_value2); + pop2(_value1); + _result = zext(_value1 f> _value2) + zext(_value1 f>= _value2) - 1; + push(_result); +} + +:dcmpl is (in_table_switch=0 & in_lookup_switch=0 & op=0x97) +{ + _value2 :$(DOUBLE_SIZE) = 0; + _value1 :$(DOUBLE_SIZE) = 0; + _result :$(SIZE) = 0; + pop2(_value2); + pop2(_value1); + _result = zext(_value1 f> _value2) + zext(_value1 f>= _value2) - 1; + push(_result); +} + +:dconst_0 is (in_table_switch=0 & in_lookup_switch=0 & op=0x0e) +{ + _int :$(DOUBLE_SIZE) = 0; + _double :$(DOUBLE_SIZE) = int2float(_int); + push2(_double); +} + +:dconst_1 is (in_table_switch=0 & in_lookup_switch=0 & op=0x0f) +{ + _int :$(DOUBLE_SIZE) = 1; + _double :$(DOUBLE_SIZE) = int2float(_int); + push2(_double); +} + +:ddiv is (in_table_switch=0 & in_lookup_switch=0 & op=0x6f) +{ + _value2 :$(DOUBLE_SIZE) = 0; + _value1 :$(DOUBLE_SIZE) = 0; + _result :$(DOUBLE_SIZE) = 0; + pop2(_value2); + pop2(_value1); + _result = _value1 f/ _value2; + push2(_result); +} + +:dload index is (in_table_switch=0 & in_lookup_switch=0 & op=0x18); index +{ + LVA = index*$(SIZE); + _value :$(DOUBLE_SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA); + push2(_value); +} + +:dload_0 is (in_table_switch=0 & in_lookup_switch=0 & op=0x26) +{ + LVA = 0; + _value :$(DOUBLE_SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA); + push2(_value); +} + +:dload_1 is (in_table_switch=0 & in_lookup_switch=0 & op=0x27) +{ + LVA = 1 * $(SIZE); + _value :$(DOUBLE_SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA); + push2(_value); +} + +:dload_2 is (in_table_switch=0 & in_lookup_switch=0 & op=0x28) +{ + LVA = 2 * $(SIZE); + _value :$(DOUBLE_SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA); + push2(_value); +} + +:dload_3 is (in_table_switch=0 & in_lookup_switch=0 & op=0x29) +{ + LVA = 3 * $(SIZE); + _value :$(DOUBLE_SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA); + push2(_value); +} + +:dmul is (in_table_switch=0 & in_lookup_switch=0 & op=0x6b) +{ + _value2 :$(DOUBLE_SIZE) = 0; + _value1 :$(DOUBLE_SIZE) = 0; + _result :$(DOUBLE_SIZE) = 0; + pop2(_value2); + pop2(_value1); + _result = _value1 f* _value2; + push2(_result); +} + +:dneg is (in_table_switch=0 & in_lookup_switch=0 & op=0x77) +{ + _value :$(DOUBLE_SIZE) = 0; + _result :$(DOUBLE_SIZE) = 0; + pop2(_value); + _result = f- _value; + push2(_result); +} + +:drem is (in_table_switch=0 & in_lookup_switch=0 & op=0x73) +{ + _value2 :$(DOUBLE_SIZE) = 0; + _value1 :$(DOUBLE_SIZE) = 0; + _result :$(DOUBLE_SIZE) = 0; + pop2(_value2); + pop2(_value1); + _result = dremOp(_value1, _value2); + push2(_result); +} + +:dreturn is (in_table_switch=0 & in_lookup_switch=0 & op=0xaf) +{ + pop2(cat2_return_value); + return [return_address]; +} + +:dstore index is (in_table_switch=0 & in_lookup_switch=0 & op=0x39); index +{ + _value :$(DOUBLE_SIZE) = 0; + pop2(_value); + LVA = index*$(SIZE); + *[localVariableArray]:$(DOUBLE_SIZE) (LVA) = _value; +} + +:dstore_0 is (in_table_switch=0 & in_lookup_switch=0 & op=0x47) +{ + _value :$(DOUBLE_SIZE) = 0; + pop2(_value); + LVA = 0; + *[localVariableArray]:$(DOUBLE_SIZE) (LVA) = _value; +} + +:dstore_1 is (in_table_switch=0 & in_lookup_switch=0 & op=0x48) +{ + _value :$(DOUBLE_SIZE) = 0; + pop2(_value); + LVA = 1 * $(SIZE); + *[localVariableArray]:$(DOUBLE_SIZE) (LVA) = _value; +} + +:dstore_2 is (in_table_switch=0 & in_lookup_switch=0 & op=0x49) +{ + _value :$(DOUBLE_SIZE) = 0; + pop2(_value); + LVA = 2 * $(SIZE); + *[localVariableArray]:$(DOUBLE_SIZE) (LVA) = _value; +} + +:dstore_3 is (in_table_switch=0 & in_lookup_switch=0 & op=0x4a) +{ + _value :$(DOUBLE_SIZE) = 0; + pop2(_value); + LVA = 3 * $(SIZE); + *[localVariableArray]:$(DOUBLE_SIZE) (LVA) = _value; +} + +:dsub is (in_table_switch=0 & in_lookup_switch=0 & op=0x67) +{ + _value2 :$(DOUBLE_SIZE) = 0; + _value1 :$(DOUBLE_SIZE) = 0; + _result :$(DOUBLE_SIZE) = 0; + pop2(_value2); + pop2(_value1); + _result = _value1 f- _value2; + push2(_result); +} + +:dup is (in_table_switch=0 & in_lookup_switch=0 & op=0x59) +{ + local word = *:$(SIZE) SP; + push(word); +} + +:dup_x1 is (in_table_switch=0 & in_lookup_switch=0 & op=0x5a) +{ + _value1 :$(SIZE) = 0; + _value2 :$(SIZE) = 0; + pop(_value1); + pop(_value2); + push(_value1); + push(_value2); + push(_value1); +} + +:dup_x2 is (in_table_switch=0 & in_lookup_switch=0 & op=0x5b) +{ + _value1 :$(SIZE) = 0; + _value2 :$(SIZE) = 0; + _value3 :$(SIZE) = 0; + pop(_value1); + pop(_value2); + pop(_value3); + push(_value1); + push(_value3); + push(_value2); + push(_value1); +} + +:dup2 is (in_table_switch=0 & in_lookup_switch=0 & op=0x5c) +{ + _value1 :$(SIZE) = 0; + _value2 :$(SIZE) = 0; + pop(_value1); + pop(_value2); + push(_value2); + push(_value1); + push(_value2); + push(_value1); +} + +:dup2_x1 is (in_table_switch=0 & in_lookup_switch=0 & op=0x5d) +{ + _value1 :$(SIZE) = 0; + _value2 :$(SIZE) = 0; + _value3 :$(SIZE) = 0; + pop(_value1); + pop(_value2); + pop(_value3); + push(_value2); + push(_value1); + push(_value3); + push(_value2); + push(_value1); +} + +:dup2_x2 is (in_table_switch=0 & in_lookup_switch=0 & op=0x5e) +{ + _value1 :$(SIZE) = 0; + _value2 :$(SIZE) = 0; + _value3 :$(SIZE) = 0; + _value4 :$(SIZE) = 0; + pop(_value1); + pop(_value2); + pop(_value3); + pop(_value4); + push(_value2); + push(_value1); + push(_value4); + push(_value3); + push(_value2); + push(_value1); +} + +:f2d is (in_table_switch=0 & in_lookup_switch=0 & op=0x8d) +{ + _value :$(SIZE) = 0; + _result :$(DOUBLE_SIZE) = 0; + pop(_value); + _result = float2float(_value); + push2(_result); +} + +#not exactly how the JVM converts floats to ints but close enough +:f2i is (in_table_switch=0 & in_lookup_switch=0 & op=0x8b) +{ + _value :$(SIZE) = 0; + _result :$(SIZE) = 0; + pop(_value); + _result = round(_value); + push(_result); +} + +#not exactly how the JVM converts floats to longs +:f2l is (in_table_switch=0 & in_lookup_switch=0 & op=0x8c) +{ + _value :$(SIZE) = 0; + _value2 :$(DOUBLE_SIZE) = 0; + _result :$(DOUBLE_SIZE) = 0; + pop(_value); + _value2 = float2float(_value); + _result = round(_value2); + push2(_result); +} + +:fadd is (in_table_switch=0 & in_lookup_switch=0 & op=0x62) +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + _result :$(SIZE) = 0; + pop(_value2); + pop(_value1); + _result = _value1 f+ _value2; + push(_result); +} + +:faload is (in_table_switch=0 & in_lookup_switch=0 & op=0x30) +{ + _index :$(SIZE) = 0; + _arrayref :$(SIZE) = 0; + _value :$(SIZE) = 0; + pop(_index); + pop(_arrayref); + local _offset = _arrayref + ($(SIZE) * _index); + _value = *[ram] (_offset); + push(_value); +} + +:fastore is (in_table_switch=0 & in_lookup_switch=0 & op=0x51) +{ + _value :$(SIZE) = 0; + _index:$(SIZE) = 0; + _arrayref:$(SIZE) = 0; + pop(_value); + pop(_index); + pop(_arrayref); + local _offset = _arrayref + ($(SIZE) * _index); + *[ram] _offset = _value; +} + +:fcmpg is (in_table_switch=0 & in_lookup_switch=0 & op=0x96) +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + _result :$(SIZE) = 0; + pop(_value2); + pop(_value1); + _result = zext(_value1 f> _value2) + zext(_value1 f>= _value2) - 1; + push(_result); +} + +:fcmpl is (in_table_switch=0 & in_lookup_switch=0 & op=0x95) +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + _result :$(SIZE) = 0; + pop(_value2); + pop(_value1); + _result = zext(_value1 f> _value2) + zext(_value1 f>= _value2) - 1; + push(_result); +} + +:fconst_0 is (in_table_switch=0 & in_lookup_switch=0 & op=0x0b) +{ + f :$(SIZE) = 0; + fAsFloat:$(SIZE) = int2float(f); + push(fAsFloat); +} + +:fconst_1 is (in_table_switch=0 & in_lookup_switch=0 & op=0x0c) +{ + f :$(SIZE) = 1; + fAsFloat:$(SIZE) = int2float(f); + push(fAsFloat); +} + +:fconst_2 is (in_table_switch=0 & in_lookup_switch=0 & op=0x0d) +{ + f :$(SIZE) = 2; + fAsFloat:$(SIZE) = int2float(f); + push(fAsFloat); +} + +:fdiv is (in_table_switch=0 & in_lookup_switch=0 & op=0x6e) +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + _result :$(SIZE) = 0; + pop(_value2); + pop(_value1); + _result = _value1 f/ _value2; + push(_result); +} + +:fload index is (in_table_switch=0 & in_lookup_switch=0 & op=0x17); index +{ + LVA = $(SIZE) * index; + _value :$(SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA); + push(_value); +} + +:fload_0 is (in_table_switch=0 & in_lookup_switch=0 & op=0x22) +{ + LVA = 0; + _value :$(SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA); + push(_value); +} + +:fload_1 is (in_table_switch=0 & in_lookup_switch=0 & op=0x23) +{ + LVA = 1 * $(SIZE); + _value :$(SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA); + push(_value); +} + +:fload_2 is (in_table_switch=0 & in_lookup_switch=0 & op=0x24) +{ + LVA = 2 * $(SIZE); + _value :$(SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA); + push(_value); +} + +:fload_3 is (in_table_switch=0 & in_lookup_switch=0 & op=0x25) +{ + LVA = 3 * $(SIZE); + _value :$(SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA); + push(_value); +} + +:fmul is (in_table_switch=0 & in_lookup_switch=0 & op=0x6a) +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + _result :$(SIZE) = 0; + pop(_value2); + pop(_value1); + _result = _value1 f* _value2; + push(_result); +} + +:fneg is (in_table_switch=0 & in_lookup_switch=0 & op=0x76) +{ + _value :$(SIZE) = 0; + _result :$(SIZE) = 0; + pop(_value); + _result = f- _value; + push(_result); +} + +:frem is (in_table_switch=0 & in_lookup_switch=0 & op=0x72) +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + _result :$(SIZE) = 0; + pop(_value2); + pop(_value1); + _result = fremOp(_value1, _value2); + push(_result); +} + +:freturn is (in_table_switch=0 & in_lookup_switch=0 & op=0xae) +{ + pop(return_value); + return [return_address]; +} + +:fstore index is (in_table_switch=0 & in_lookup_switch=0 & op=0x38); index +{ + _value :$(SIZE) = 0; + pop(_value); + LVA = index*$(SIZE); + *[localVariableArray]:$(SIZE) (LVA) = _value; +} + +:fstore_0 is (in_table_switch=0 & in_lookup_switch=0 & op=0x43) +{ + _value :$(SIZE) = 0; + pop(_value); + LVA = 0; + *[localVariableArray]:$(SIZE) (LVA) = _value; +} + +:fstore_1 is (in_table_switch=0 & in_lookup_switch=0 & op=0x44) +{ + _value :$(SIZE) = 0; + pop(_value); + LVA = 1 * $(SIZE); + *[localVariableArray]:$(SIZE) (LVA) = _value; +} +:fstore_2 is (in_table_switch=0 & in_lookup_switch=0 & op=0x45) +{ + _value :$(SIZE) = 0; + pop(_value); + LVA = 2 * $(SIZE); + *[localVariableArray]:$(SIZE) (LVA) = _value; +} +:fstore_3 is (in_table_switch=0 & in_lookup_switch=0 & op=0x46) +{ + _value :$(SIZE) = 0; + pop(_value); + LVA = 3 * $(SIZE); + *[localVariableArray]:$(SIZE) (LVA) = _value; +} + +:fsub is (in_table_switch=0 & in_lookup_switch=0 & op=0x66) +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + _result :$(SIZE) = 0; + pop(_value2); + pop(_value1); + _result = _value1 f- _value2; + push(_result); +} + +:getfield index is (in_table_switch=0 & in_lookup_switch=0 & op=0xb4 ); indexbyte1; indexbyte2 [ index = indexbyte1<<8 | indexbyte2; ] +{ + getFieldCallOther(index:2); +} + + +:getstatic index is (in_table_switch=0 & in_lookup_switch=0 & op=0xb2); indexbyte1; indexbyte2 [index = indexbyte1 << 8 | indexbyte2;] +{ + getStaticCallOther(index:2); +} + +:goto Branch is (in_table_switch=0 & in_lookup_switch=0 & op=0xa7); Branch +{ + goto Branch; +} + +:goto_w Branch_w is (in_table_switch=0 & in_lookup_switch=0 & op=0xc8); Branch_w +{ + goto Branch_w; +} + +:i2b is (in_table_switch=0 & in_lookup_switch=0 & op=0x91) +{ + _value :$(SIZE) = 0; + _result :$(SIZE) = 0; + pop(_value); + local _byte = _value:1; + _result = sext(_byte); + push(_result); +} + +:i2c is (in_table_switch=0 & in_lookup_switch=0 & op=0x92) +{ + _value :$(SIZE) = 0; + _result :$(SIZE) = 0; + pop(_value); + local _char = _value:2; + _result = zext(_char); + push(_result); +} + +:i2d is (in_table_switch=0 & in_lookup_switch=0 & op=0x87) +{ + _value :$(SIZE) = 0; + _resultAsLong :$(DOUBLE_SIZE) = 0; + _resultAsDouble :$(DOUBLE_SIZE) = 0; + pop(_value); + _resultAsLong = sext(_value); + _resultAsDouble = int2float(_resultAsLong); + push2(_resultAsDouble); +} + +:i2f is (in_table_switch=0 & in_lookup_switch=0 & op=0x86) +{ + _value :$(SIZE) = 0; + _result :$(SIZE) = 0; + pop(_value); + _result = int2float(_value); + push(_result); +} + +:i2l is (in_table_switch=0 & in_lookup_switch=0 & op=0x85) +{ + _value :$(SIZE) = 0; + _result :$(DOUBLE_SIZE) = 0; + pop(_value); + _result = sext(_value); + push2(_result); +} + +:i2s is (in_table_switch=0 & in_lookup_switch=0 & op=0x93) +{ + _value :$(SIZE) = 0; + _result :$(SIZE) = 0; + pop(_value); + local _short = _value:2; + _result = sext(_short); + push(_result); +} + +:iadd is (in_table_switch=0 & in_lookup_switch=0 & op=0x60) +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + _result :$(SIZE) = 0; + pop(_value2); + pop(_value1); + _result = _value1 + _value2; + push(_result); +} + +:iaload is (in_table_switch=0 & in_lookup_switch=0 & op=0x2e) +{ + _index :$(SIZE) = 0; + _arrayref :$(SIZE) = 0; + _value :$(SIZE) = 0; + pop(_index); + pop(_arrayref); + local _offset = _arrayref + ($(SIZE) * _index); + _value = *[ram] (_offset); + push(_value); +} + +:iand is (in_table_switch=0 & in_lookup_switch=0 & op=0x7e) +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + _result :$(SIZE) = 0; + pop(_value2); + pop(_value1); + _result = _value1 & _value2; + push(_result); +} + +:iastore is (in_table_switch=0 & in_lookup_switch=0 & op=0x4f) +{ + _value :$(SIZE) = 0; + _index:$(SIZE) = 0; + _arrayref:$(SIZE) = 0; + pop(_value); + pop(_index); + pop(_arrayref); + local _offset = _arrayref + ($(SIZE) * _index); + *[ram] _offset = _value; +} + +:iconst_m1 is (in_table_switch=0 & in_lookup_switch=0 & op=0x02) +{ + _i :$(SIZE) = -1; + push(_i); +} + +:iconst_0 is (in_table_switch=0 & in_lookup_switch=0 & op=0x03) +{ + _i :$(SIZE) = 0; + push(_i); +} + +:iconst_1 is (in_table_switch=0 & in_lookup_switch=0 & op=0x04) +{ + _i :$(SIZE) = 1; + push(_i); +} + +:iconst_2 is (in_table_switch=0 & in_lookup_switch=0 & op=0x05) +{ + _i :$(SIZE) = 2; + push(_i); +} + +:iconst_3 is (in_table_switch=0 & in_lookup_switch=0 & op=0x06) +{ + _i :$(SIZE) = 3; + push(_i); +} + +:iconst_4 is (in_table_switch=0 & in_lookup_switch=0 & op=0x07) +{ + _i :$(SIZE) = 4; + push(_i); +} + +:iconst_5 is (in_table_switch=0 & in_lookup_switch=0 & op=0x08) +{ + _i :$(SIZE) = 5; + push(_i); +} + +:idiv is (in_table_switch=0 & in_lookup_switch=0 & op=0x6c) +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + _result :$(SIZE) = 0; + pop(_value2); + pop(_value1); + _result = _value1 s/ _value2; + push(_result); +} + +:if_acmpeq Branch is (in_table_switch=0 & in_lookup_switch=0 & op=0xa5); Branch +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + pop(_value2); + pop(_value1); + if( _value1 == _value2 ) goto Branch; +} + +:if_acmpne Branch is (in_table_switch=0 & in_lookup_switch=0 & op=0xa6); Branch +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + pop(_value2); + pop(_value1); + if( _value1 != _value2 ) goto Branch; +} + +:if_icmpeq Branch is (in_table_switch=0 & in_lookup_switch=0 & op=0x9f); Branch +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + pop(_value2); + pop(_value1); + if( _value1 == _value2 ) goto Branch; +} + +:if_icmpne Branch is (in_table_switch=0 & in_lookup_switch=0 & op=0xa0); Branch +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + pop(_value2); + pop(_value1); + if( _value1 != _value2 ) goto Branch; +} + +:if_icmplt Branch is (in_table_switch=0 & in_lookup_switch=0 & op=0xa1); Branch +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + pop(_value2); + pop(_value1); + if( _value1 s< _value2 ) goto Branch; +} + +:if_icmpge Branch is (in_table_switch=0 & in_lookup_switch=0 & op=0xa2); Branch +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + pop(_value2); + pop(_value1); + if( _value1 s>= _value2 ) goto Branch; +} + +:if_icmpgt Branch is (in_table_switch=0 & in_lookup_switch=0 & op=0xa3); Branch +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + pop(_value2); + pop(_value1); + if( _value1 s> _value2 ) goto Branch; +} + +:if_icmple Branch is (in_table_switch=0 & in_lookup_switch=0 & op=0xa4); Branch +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + pop(_value2); + pop(_value1); + if( _value1 s<= _value2 ) goto Branch; +} + +:ifeq Branch is (in_table_switch=0 & in_lookup_switch=0 & op=0x99); Branch +{ + _value :$(SIZE) = 0; + pop(_value); + if( _value == 0 ) goto Branch; +} + +:ifne Branch is (in_table_switch=0 & in_lookup_switch=0 & op=0x9a); Branch +{ + _value :$(SIZE) = 0; + pop(_value); + if( _value != 0 ) goto Branch; +} + +:iflt Branch is (in_table_switch=0 & in_lookup_switch=0 & op=0x9b); Branch +{ + _value :$(SIZE) = 0; + pop(_value); + if( _value s< 0 ) goto Branch; +} + +:ifge Branch is (in_table_switch=0 & in_lookup_switch=0 & op=0x9c); Branch +{ + _value :$(SIZE) = 0; + pop(_value); + if( _value s>= 0 ) goto Branch; +} + +:ifgt Branch is (in_table_switch=0 & in_lookup_switch=0 & op=0x9d); Branch +{ + _value :$(SIZE) = 0; + pop(_value); + if( _value s> 0 ) goto Branch; +} + +:ifle Branch is (in_table_switch=0 & in_lookup_switch=0 & op=0x9e); Branch +{ + _value :$(SIZE) = 0; + pop(_value); + if( _value s<= 0 ) goto Branch; +} + +:ifnonnull Branch is (in_table_switch=0 & in_lookup_switch=0 & op=0xc7); Branch +{ + _value :$(SIZE) = 0; + pop(_value); + if ( _value != 0) goto Branch; +} + +:ifnull Branch is (in_table_switch=0 & in_lookup_switch=0 & op=0xc6); Branch +{ + _value :$(SIZE) = 0; + pop(_value); + if ( _value == 0) goto Branch; +} + +:iinc index, constant is (in_table_switch=0 & in_lookup_switch=0 & op=0x84); index; constant +{ + _const :$(SIZE) = 0; + LVA = index*$(SIZE); + _const = sext(constant:1); + *[localVariableArray]:$(SIZE) (LVA) = (*[localVariableArray]:$(SIZE) (LVA)) + _const; +} + +:iload index is (in_table_switch=0 & in_lookup_switch=0 & op=0x15); index +{ + LVA = index*$(SIZE); + _value :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA); + push(_value); +} + +:iload_0 is (in_table_switch=0 & in_lookup_switch=0 & op=0x1a) +{ + LVA = 0; + _value :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA); + push(_value); +} + +:iload_1 is (in_table_switch=0 & in_lookup_switch=0 & op=0x1b) +{ + LVA = 1 * $(SIZE); + _value :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA); + push(_value); +} + +:iload_2 is (in_table_switch=0 & in_lookup_switch=0 & op=0x1c) +{ LVA = 2 * $(SIZE); + _value :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA); + push(_value); +} + +:iload_3 is (in_table_switch=0 & in_lookup_switch=0 & op=0x1d) +{ + LVA = 3 * $(SIZE); + _value :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA); + push(_value); +} + +:imul is (in_table_switch=0 & in_lookup_switch=0 & op=0x68) +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + _result :$(SIZE) = 0; + pop(_value2); + pop(_value1); + _result = _value1 * _value2; + push(_result); +} + +:ineg is (in_table_switch=0 & in_lookup_switch=0 & op=0x74) +{ + _value :$(SIZE) = 0; + _result :$(SIZE) = 0; + pop(_value); + _result = -_value; + push(_result); +} + +:instanceof index is (in_table_switch=0 & in_lookup_switch=0 & op=0xc1); indexbyte1; indexbyte2 [ index = indexbyte1<<8 | indexbyte2; ] +{ + _object:$(SIZE) = 0; + pop(_object); + _res:1 = cpool(_object,index,$(CPOOL_INSTANCEOF)); + _result:$(SIZE) = zext(_res); + push(_result); +} + + +:invokedynamic index, blank1, blank2 is (in_table_switch=0 & in_lookup_switch=0 & op=0xba); indexbyte1; indexbyte2; blank1; blank2 [ index = indexbyte1<<8 | indexbyte2; ] +{ + invokedynamicCallOther(index:2); +} + +:invokeinterface index, count, blank1 is (in_table_switch=0 & in_lookup_switch=0 & op=0xb9); indexbyte1; indexbyte2; count; blank1 [ index = indexbyte1<<8 | indexbyte2; ] +{ + invokeinterfaceCallOther(index:2); +} + +:invokespecial index is (in_table_switch=0 & in_lookup_switch=0 & op=0xb7); indexbyte1; indexbyte2 [ index = indexbyte1<<8 | indexbyte2; ] +{ + invokespecialCallOther(index:2); +} + +:invokestatic index is (in_table_switch=0 & in_lookup_switch=0 & op=0xb8); indexbyte1; indexbyte2 [ index = indexbyte1<<8 | indexbyte2; ] +{ + invokestaticCallOther(index:2); +} + +:invokevirtual index is (in_table_switch=0 & in_lookup_switch=0 & op=0xb6); indexbyte1; indexbyte2 [ index = indexbyte1<<8 | indexbyte2; ] +{ + invokevirtualCallOther(index:2); + +} + +:ior is (in_table_switch=0 & in_lookup_switch=0 & op=0x80) +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + _result :$(SIZE) = 0; + + pop(_value2); + pop(_value1); + _result = _value1 | _value2; + push(_result); +} + +:irem is (in_table_switch=0 & in_lookup_switch=0 & op=0x70) +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + _result :$(SIZE) = 0; + + pop(_value2); + pop(_value1); + _result = _value1 s% _value2; + push(_result); +} + +:ireturn is (in_table_switch=0 & in_lookup_switch=0 & op=0xac) +{ + pop(return_value); + return [return_address]; +} + +:ishl is (in_table_switch=0 & in_lookup_switch=0 & op=0x78) +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + _result :$(SIZE) = 0; + + pop(_value2); + pop(_value1); + _result = _value1 << (_value2 & 0x1f); + push(_result); +} + +:ishr is (in_table_switch=0 & in_lookup_switch=0 & op=0x7a) +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + _result :$(SIZE) = 0; + + pop(_value2); + pop(_value1); + _result = _value1 s>> (_value2 & 0x1f); + push(_result); +} + +:istore index is (in_table_switch=0 & in_lookup_switch=0 & op=0x36); index +{ + _value :$(SIZE) = 0; + pop(_value); + LVA = index*$(SIZE); + *[localVariableArray]:$(SIZE) (LVA) = _value; +} + +:istore_0 is (in_table_switch=0 & in_lookup_switch=0 & op=0x3b) +{ + _value :$(SIZE) = 0; + pop(_value); + LVA = 0; + *[localVariableArray]:$(SIZE) (LVA) =_value; +} + +:istore_1 is (in_table_switch=0 & in_lookup_switch=0 & op=0x3c) +{ + _value :$(SIZE) = 0; + pop(_value); + LVA = 1 * $(SIZE); + *[localVariableArray]:$(SIZE) (LVA) =_value; +} + +:istore_2 is (in_table_switch=0 & in_lookup_switch=0 & op=0x3d) +{ + _value :$(SIZE) = 0; + pop(_value); + LVA = 2 * $(SIZE); + *[localVariableArray]:$(SIZE) (LVA) =_value; +} + +:istore_3 is (in_table_switch=0 & in_lookup_switch=0 & op=0x3e) +{ + _value :$(SIZE) = 0; + pop(_value); + LVA = 3 * $(SIZE); + *[localVariableArray]:$(SIZE) (LVA) =_value; +} + +:isub is (in_table_switch=0 & in_lookup_switch=0 & op=0x64) +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + _result :$(SIZE) = 0; + + pop(_value2); + pop(_value1); + _result = _value1 - _value2; + push(_result); +} + +:iushr is (in_table_switch=0 & in_lookup_switch=0 & op=0x7c) +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + _result :$(SIZE) = 0; + + pop(_value2); + pop(_value1); + _result = _value1 >> (_value2 & 0x1f); + push(_result); +} + +:ixor is (in_table_switch=0 & in_lookup_switch=0 & op=0x82) +{ + _value2 :$(SIZE) = 0; + _value1 :$(SIZE) = 0; + _result :$(SIZE) = 0; + + pop(_value2); + pop(_value1); + _result = _value1 ^ _value2; + push(_result); +} + +:jsr Branch is (in_table_switch=0 & in_lookup_switch=0 & op=0xa8); Branch +{ + retAddr :$(SIZE) = inst_next; + push(retAddr); + goto Branch; +} + +:jsr_w Branch_w is (in_table_switch=0 & in_lookup_switch=0 & op=0xc9); Branch_w +{ + retAddr :$(SIZE) = inst_next; + push(retAddr); + goto Branch_w; +} + +:l2d is (in_table_switch=0 & in_lookup_switch=0 & op=0x8a) +{ + _value :$(DOUBLE_SIZE) = 0; + _result :$(DOUBLE_SIZE) = 0; + pop2(_value); + _result = int2float(_value); + push2(_result); +} + +:l2f is (in_table_switch=0 & in_lookup_switch=0 & op=0x89) +{ + _value :$(DOUBLE_SIZE) = 0; + _result :$(SIZE) = 0; + pop2(_value); + _result = int2float(_value); + push(_result); +} + +:l2i is (in_table_switch=0 & in_lookup_switch=0 & op=0x88) +{ + _value :$(DOUBLE_SIZE) = 0; + _result :$(SIZE) = 0; + pop2(_value); + _result = _value:$(SIZE); + push(_result); +} + +:ladd is (in_table_switch=0 & in_lookup_switch=0 & op=0x61) +{ + _value1 :$(DOUBLE_SIZE) = 0; + _value2 :$(DOUBLE_SIZE) = 0; + _result :$(DOUBLE_SIZE) = 0; + pop2(_value2); + pop2(_value1); + _result = _value1 + _value2; + push2(_result); +} + +:laload is (in_table_switch=0 & in_lookup_switch=0 & op=0x2f) +{ + _index :$(SIZE) = 0; + _arrayref :$(SIZE) = 0; + _value :$(DOUBLE_SIZE) = 0; + pop(_index); + pop(_arrayref); + local _offset = _arrayref + ($(DOUBLE_SIZE) * _index); + _value = *[ram]:$(DOUBLE_SIZE) (_offset); + push2(_value); + +} + +:land is (in_table_switch=0 & in_lookup_switch=0 & op=0x7f) +{ + _value2 :$(DOUBLE_SIZE) = 0; + _value1 :$(DOUBLE_SIZE) = 0; + _result :$(DOUBLE_SIZE) = 0; + pop2(_value2); + pop2(_value1); + _result = _value1 & _value2; + push2(_result); +} + +:lastore is (in_table_switch=0 & in_lookup_switch=0 & op=0x50) +{ + _value :$(DOUBLE_SIZE) = 0; + _index:$(SIZE) = 0; + _arrayref:$(SIZE) = 0; + pop2(_value); + pop(_index); + pop(_arrayref); + local _offset = _arrayref + ($(DOUBLE_SIZE) * _index); + *[ram]:$(DOUBLE_SIZE) _offset = _value; + +} + +:lcmp is (in_table_switch=0 & in_lookup_switch=0 & op=0x94) +{ + _value2 :$(DOUBLE_SIZE) = 0; + _value1 :$(DOUBLE_SIZE) = 0; + _result :$(SIZE) = 0; + pop2(_value2); + pop2(_value1); + _result = zext(_value1 s> _value2) + zext(_value1 s>= _value2) - 1; + push(_result); +} + +:lconst_0 is (in_table_switch=0 & in_lookup_switch=0 & op=0x09) +{ + _l :$(DOUBLE_SIZE) = 0; + push2(_l); +} + +:lconst_1 is (in_table_switch=0 & in_lookup_switch=0 & op=0x0a) +{ + _l :$(DOUBLE_SIZE) = 1; + push2(_l); +} + +:ldc index is (in_table_switch=0 & in_lookup_switch=0 & op=0x12); index +{ + ldcCallOther(index:1); +} + +:ldc_w index is (in_table_switch=0 & in_lookup_switch=0 & op=0x13); indexbyte1; indexbyte2 [ index = indexbyte1 << 8 | indexbyte2; ] +{ + ldc_wCallOther(index:2); +} + +:ldc2_w index is (in_table_switch=0 & in_lookup_switch=0 & op=0x14); indexbyte1; indexbyte2 [ index = indexbyte1 << 8 | indexbyte2; ] +{ + ldc2_wCallOther(index:2); +} + +:ldiv is (in_table_switch=0 & in_lookup_switch=0 & op=0x6d) +{ + _value2 :$(DOUBLE_SIZE) = 0; + _value1 :$(DOUBLE_SIZE) = 0; + _result :$(DOUBLE_SIZE) = 0; + pop2(_value2); + pop2(_value1); + _result = _value1 s/ _value2; + push2(_result); +} + +:lload index is (in_table_switch=0 & in_lookup_switch=0 & op=0x16); index +{ + LVA = index * $(SIZE); + _value :$(DOUBLE_SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA); + push2(_value); +} + +:lload_0 is (in_table_switch=0 & in_lookup_switch=0 & op=0x1e) +{ + LVA = 0; + _value :$(DOUBLE_SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA); + push2(_value); +} + +:lload_1 is (in_table_switch=0 & in_lookup_switch=0 & op=0x1f) +{ + LVA = 1 * $(SIZE); + _value :$(DOUBLE_SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA); + push2(_value); +} + +:lload_2 is (in_table_switch=0 & in_lookup_switch=0 & op=0x20) +{ + LVA = 2 * $(SIZE); + _value :$(DOUBLE_SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA); + push2(_value); +} + +:lload_3 is (in_table_switch=0 & in_lookup_switch=0 & op=0x21) +{ + LVA = 3 * $(SIZE); + _value :$(DOUBLE_SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA); + push2(_value); +} + +:lmul is (in_table_switch=0 & in_lookup_switch=0 & op=0x69) +{ + _value2 :$(DOUBLE_SIZE) = 0; + _value1 :$(DOUBLE_SIZE) = 0; + _result :$(DOUBLE_SIZE) = 0; + pop2(_value2); + pop2(_value1); + _result = _value1 * _value2; + push2(_result); +} + +:lneg is (in_table_switch=0 & in_lookup_switch=0 & op=0x75) +{ + _value :$(DOUBLE_SIZE) = 0; + _result :$(DOUBLE_SIZE) = 0; + pop2(_value); + _result= -_value; + push2(_result); +} + +################################################################################################## +# lookupswitch +################################################################################################## + +#compute and display one match,offset pair +LookupSwitch_match:match _offset is matchbyte1; matchbyte2; matchbyte3; matchbyte4; offsetbyte1; offsetbyte2; offsetbyte3; offsetbyte4 [match = (matchbyte1 << 24) | (matchbyte2 << 16) | (matchbyte3 << 8) | (matchbyte4); _offset = inst_start + ((offsetbyte1 << 24) | (offsetbyte2 << 16) | (offsetbyte3 << 8) | (offsetbyte4)); ] +{ +} + +#consume one match,offset pair and decrement the switch number +:^LookupSwitch_match, instruction is (in_lookup_switch=1 & in_table_switch=0); LookupSwitch_match; instruction [switch_num = switch_num - 1;] +{ +} + +#leave the switch statement +:""LookupSwitch_match is (in_lookup_switch=1 & switch_num=1 & in_table_switch=0); LookupSwitch_match [in_lookup_switch=0;] +{ +} + +define pcodeop switchAssist; + +padSwitch: "" is alignmentPad = 3 & padVal & op ; pad1; pad2; pad3 { export *[const]:1 padVal; } +padSwitch: "" is alignmentPad = 2 & padVal & op ; pad1; pad2 { export *[const]:1 padVal; } +padSwitch: "" is alignmentPad = 1 & padVal & op ; pad1 { export *[const]:1 padVal; } +padSwitch: "" is alignmentPad = 0 & padVal & op { export *[const]:1 padVal; } + +#Note: "Default" constructor does not play nice with switchAssist injection... +dolookupswitch: _default, npairs is alignmentPad & defaultbyte1; defaultbyte2; defaultbyte3; defaultbyte4; npairsbyte1; npairsbyte2; npairsbyte3; npairsbyte4 [ npairs = (npairsbyte1 << 24) | (npairsbyte2 << 16) | (npairsbyte3 << 8) | npairsbyte4; _default = inst_start + ((defaultbyte1 << 24) | (defaultbyte2 << 16) | (defaultbyte3 << 8) | defaultbyte4); switch_num = npairs; in_lookup_switch = 1;] +{ + local _padding:1 = alignmentPad; + local _opcodeAddr:$(SIZE) = inst_start; + local _key:$(SIZE) = 0; + pop(_key); + local _address:$(SIZE) = switchAssist(_key,_opcodeAddr,_padding,_default:$(SIZE),npairs:$(SIZE)); + goto [ _address ]; +} + +:lookupswitch dolookupswitch, instruction is in_lookup_switch=0 & in_table_switch=0 & op=0xab & alignmentPad = 0 ; dolookupswitch; instruction +{ + build dolookupswitch; +} +:lookupswitch dolookupswitch, instruction is in_lookup_switch=0 & in_table_switch=0 & op=0xab & alignmentPad = 1 ; pad1; dolookupswitch; instruction +{ + build dolookupswitch; +} +:lookupswitch dolookupswitch, instruction is in_lookup_switch=0 & in_table_switch=0 & op=0xab & alignmentPad = 2 ; pad1; pad2; dolookupswitch; instruction +{ + build dolookupswitch; +} +:lookupswitch dolookupswitch, instruction is in_lookup_switch=0 & in_table_switch=0 & op=0xab & alignmentPad = 3 ; pad1; pad2; pad3; dolookupswitch; instruction +{ + build dolookupswitch; +} + + +:lor is (in_table_switch=0 & in_lookup_switch=0 & op=0x81) +{ + _value2 :$(DOUBLE_SIZE) = 0; + _value1 :$(DOUBLE_SIZE) = 0; + _result :$(DOUBLE_SIZE) = 0; + pop2(_value2); + pop2(_value1); + _result = _value1 | _value2; + push2(_result); +} + +:lrem is (in_table_switch=0 & in_lookup_switch=0 & op=0x71) +{ + _value2 :$(DOUBLE_SIZE) = 0; + _value1 :$(DOUBLE_SIZE) = 0; + _result :$(DOUBLE_SIZE) = 0; + pop2(_value2); + pop2(_value1); + _result = _value1 s% _value2; + push2(_result); +} + +:lreturn is (in_table_switch=0 & in_lookup_switch=0 & op=0xad) +{ + pop2(cat2_return_value); + return [return_address]; +} + +:lshl is (in_table_switch=0 & in_lookup_switch=0 & op=0x79) +{ + _value2 :$(SIZE) = 0; + _value1 :$(DOUBLE_SIZE) = 0; + _result :$(DOUBLE_SIZE) = 0; + pop(_value2); + pop2(_value1); + _result = _value1 << (_value2 & 0x3f); + push2(_result); +} + +:lshr is (in_table_switch=0 & in_lookup_switch=0 & op=0x7b) +{ + _value2 :$(SIZE) = 0; + _value1 :$(DOUBLE_SIZE) = 0; + _result :$(DOUBLE_SIZE) = 0; + pop(_value2); + pop2(_value1); + _result = _value1 s>> (_value2 & 0x3f); + push2(_result); +} + +:lstore index is (in_table_switch=0 & in_lookup_switch=0 & op=0x37); index +{ + _value :$(DOUBLE_SIZE) = 0; + pop2(_value); + LVA = index * $(SIZE); + *[localVariableArray]:$(DOUBLE_SIZE) (LVA) = _value; +} + +:lstore_0 is (in_table_switch=0 & in_lookup_switch=0 & op=0x3f) +{ + _value :$(DOUBLE_SIZE) = 0; + pop2(_value); + LVA = 0; + *[localVariableArray]:$(DOUBLE_SIZE) (LVA) =_value; +} + +:lstore_1 is (in_table_switch=0 & in_lookup_switch=0 & op=0x40) +{ +_value :$(DOUBLE_SIZE) = 0; + pop2(_value); + LVA = 1 * $(SIZE); + *[localVariableArray]:$(DOUBLE_SIZE) (LVA) =_value; +} + +:lstore_2 is (in_table_switch=0 & in_lookup_switch=0 & op=0x41) +{ + _value :$(DOUBLE_SIZE) = 0; + pop2(_value); + LVA = 2 * $(SIZE); + *[localVariableArray]:$(DOUBLE_SIZE) (LVA) =_value; +} + +:lstore_3 is (in_table_switch=0 & in_lookup_switch=0 & op=0x42) +{ + _value :$(DOUBLE_SIZE) = 0; + pop2(_value); + LVA = 3 * $(SIZE); + *[localVariableArray]:$(DOUBLE_SIZE) (LVA) =_value; +} + +:lsub is (in_table_switch=0 & in_lookup_switch=0 & op=0x65) +{ + _value2 :$(DOUBLE_SIZE) = 0; + _value1 :$(DOUBLE_SIZE) = 0; + _result :$(DOUBLE_SIZE) = 0; + pop2(_value2); + pop2(_value1); + _result = _value1 - _value2; + push2(_result); +} + +:lushr is (in_table_switch=0 & in_lookup_switch=0 & op=0x7d) +{ + _value2 :$(SIZE) = 0; + _value1 :$(DOUBLE_SIZE) = 0; + _result :$(DOUBLE_SIZE) = 0; + pop(_value2); + pop2(_value1); + _result = _value1 >> (_value2 & 0x3f); + push2(_result); +} + +:lxor is (in_table_switch=0 & in_lookup_switch=0 & op=0x83) +{ + _value2 :$(DOUBLE_SIZE) = 0; + _value1 :$(DOUBLE_SIZE) = 0; + _result :$(DOUBLE_SIZE) = 0; + pop2(_value2); + pop2(_value1); + _result = _value1 ^ _value2; + push2(_result); +} + +:monitorenter is (in_table_switch=0 & in_lookup_switch=0 & op=0xc2) +{ + _objectref :$(SIZE) = 0; + pop(_objectref); + monitorenterOp(_objectref); +} + +:monitorexit is (in_table_switch=0 & in_lookup_switch=0 & op=0xc3) +{ + _objectref :$(SIZE) = 0; + pop(_objectref); + monitorexitOp(_objectref); +} + +:multianewarray index is (in_table_switch=0 & in_lookup_switch=0 & op=0xc5); indexbyte1; indexbyte2; dimensions [index = indexbyte1<<8 | indexbyte2;] +{ + multianewarrayCallOther(index:2,dimensions:1); +} + +:new index is (in_table_switch=0 & in_lookup_switch=0 & op=0xbb); indexbyte1; indexbyte2 [ index = indexbyte1<<8 | indexbyte2; ] +{ + local _className = cpool(0:4,index,$(CPOOL_NEW)); + _ref: $(SIZE) = newobject(_className); + push(_ref); +} + +:newarray atype is (in_table_switch=0 & in_lookup_switch=0 & op=0xbc); atype +{ + _count:$(SIZE)=0; + _arrayref:$(SIZE)=0; + pop(_count); + _ref:$(SIZE) = cpool(0:4,atype:1,$(CPOOL_NEWARRAY)); + _arrayref = newobject(_ref, _count); + push(_arrayref); +} + +:nop is (in_table_switch=0 & in_lookup_switch=0 & in_lookup_switch=0 & op=0x00) +{ +} + +:pop is (in_table_switch=0 & in_lookup_switch=0 & op=0x57) +{ + SP = SP + $(SIZE); +} + +:pop2 is (in_table_switch=0 & in_lookup_switch=0 & op=0x58) +{ + SP = SP + $(DOUBLE_SIZE); +} + +:putfield index is (in_table_switch=0 & in_lookup_switch=0 & op=0xb5); indexbyte1; indexbyte2 [ index = indexbyte1 << 8 | indexbyte2; ] +{ + putFieldCallOther(index:2); +} + +:putstatic index is (in_table_switch=0 & in_lookup_switch=0 & op=0xb3); indexbyte1; indexbyte2 [index = indexbyte1 << 8 | indexbyte2; ] +{ + putStaticCallOther(index:2); +} + +:ret index is (in_table_switch=0 & in_lookup_switch=0 & op=0xa9); index +{ + LVA = index * $(SIZE); + _value:$(SIZE) = *[localVariableArray]:$(SIZE) (LVA); + goto [_value]; +} + +:return is (in_table_switch=0 & in_lookup_switch=0 & op=0xb1) +{ + return [return_address]; +} + +:saload is (in_table_switch=0 & in_lookup_switch=0 & op=0x35) +{ + _index :$(SIZE) = 0; + _arrayref :$(SIZE) = 0; + _value:2 = 0; + pop(_index); + pop(_arrayref); + _offset: $(SIZE) = _arrayref + _index * 2; + _value = *[ram]:2 _offset; + _valueSignExtended:$(SIZE) = sext(_value); + push(_valueSignExtended); +} + +:sastore is (in_table_switch=0 & in_lookup_switch=0 & op=0x56) +{ + _value :$(SIZE) = 0; + _index :$(SIZE) = 0; + _arrayref :$(SIZE) = 0; + pop(_value); + pop(_index); + pop(_arrayref); + local _offset = _arrayref + _index * 2; + *[ram]:$(SIZE) _offset = _value:2; +} + +:sipush short is (in_table_switch=0 & in_lookup_switch=0 & op=0x11); byte1; byte2 [ short = byte1<<8 | byte2; ] +{ + _result:$(SIZE) = sext(short:2); + push(_result); +} + +:swap is (in_table_switch=0 & in_lookup_switch=0 & op=0x5f) +{ + _value1 :$(SIZE) = 0; + _value2 :$(SIZE) = 0; + pop(_value1); + pop(_value2); + push(_value1); + push(_value2); +} + +######################################################################################################################## +# tableswitch +######################################################################################################################## + +#compute and display one switch offset +Switch_offset:_offset is offsetbyte1; offsetbyte2; offsetbyte3; offsetbyte4 [ _offset = inst_start + ((offsetbyte1<<24) | (offsetbyte2<<16) | (offsetbyte3<<8) | offsetbyte4); ] +{ +} + +# Switch entry that's not the last one. +# no pcode def - this construction is just for consuming all of the bytes of a tableswitch instructions +# decrements the switch number +:^Switch_offset, instruction is (in_table_switch=1 & in_lookup_switch=0); Switch_offset; instruction [switch_num = switch_num - 1;] +{ +} + +#Last switch entry. Get out of switch context. +:""Switch_offset is (in_table_switch=1 & in_lookup_switch=0 &switch_num=0); Switch_offset [ in_table_switch=0; ] +{ +} + +dotableswitch: Default, low, high is alignmentPad & Default;lowbyte1; lowbyte2; lowbyte3; lowbyte4; highbyte1; highbyte2; highbyte3; highbyte4 [ low = (lowbyte1 << 24) | (lowbyte2 << 16) | (lowbyte3 << 8) | lowbyte4; high = (highbyte1 << 24) | (highbyte2 << 16) | (highbyte3 << 8) | highbyte4; switch_low = low; switch_num = high - low; switch_high = high; in_table_switch = 1; ] + +{ + local _offset :$(SIZE) = 0; + local idx :$(SIZE) = 0; + local padding:$(SIZE) = alignmentPad; + + pop(idx); + if (idx s< low) goto Default; + if (idx s> high) goto Default; + #opcode_address + byte_for_opcode + padding + default + low + high = start of table + _offset = inst_start + 1 + padding + 4 + 4 + 4 + 4*(idx-low); + switch_target = inst_start + *:$(SIZE)(_offset); + goto [switch_target]; +} + +:tableswitch dotableswitch, instruction is in_table_switch=0 & in_lookup_switch=0 & op=0xaa & alignmentPad=0; dotableswitch; instruction +{ + build dotableswitch; +} +:tableswitch dotableswitch, instruction is in_table_switch=0 & in_lookup_switch=0 & op=0xaa & alignmentPad=1; pad1; dotableswitch; instruction +{ + build dotableswitch; +} +:tableswitch dotableswitch, instruction is in_table_switch=0 & in_lookup_switch=0 & op=0xaa & alignmentPad=2; pad1; pad2; dotableswitch; instruction +{ + build dotableswitch; +} +:tableswitch dotableswitch, instruction is in_table_switch=0 & in_lookup_switch=0 & op=0xaa & alignmentPad=3; pad1; pad2; pad3; dotableswitch; instruction +{ + build dotableswitch; +} + +#wide loads +:wide_iload index is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc415); indexbyte1; indexbyte2 [index = (indexbyte1 << 8) | indexbyte2; ] +{ + LVA = index * $(SIZE); + _value :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA); + push(_value); +} + +:wide_fload index is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc417); indexbyte1; indexbyte2 [index = (indexbyte1 << 8) | indexbyte2; ] +{ + LVA = index * $(SIZE); + _value :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA); + push(_value); +} + +:wide_aload index is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc419); indexbyte1; indexbyte2 [index = (indexbyte1 << 8) | indexbyte2; ] +{ + LVA = index * $(SIZE); + _value :$(SIZE) = *[localVariableArray]:$(SIZE) (LVA); + push(_value); +} + +:wide_lload index is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc416); indexbyte1; indexbyte2 [index = (indexbyte1 << 8) | indexbyte2; ] +{ + LVA = index * $(SIZE); + _value :$(DOUBLE_SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA); + push2(_value); +} + +:wide_dload index is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc418); indexbyte1; indexbyte2 [index = (indexbyte1 << 8) | indexbyte2; ] +{ + LVA = index * $(SIZE); + _value :$(DOUBLE_SIZE) = *[localVariableArray]:$(DOUBLE_SIZE) (LVA); + push2(_value); +} + + +#wide stores +:wide_istore index is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc436); indexbyte1; indexbyte2 [index = (indexbyte1 << 8) | indexbyte2;] +{ + _value :$(SIZE) = 0; + pop(_value); + LVA = index * $(SIZE); + *[localVariableArray]:$(SIZE) (LVA) = _value; +} + +:wide_fstore index is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc438); indexbyte1; indexbyte2 [index = (indexbyte1 << 8) | indexbyte2;] +{ + _value :$(SIZE) = 0; + pop(_value); + LVA = index * $(SIZE); + *[localVariableArray]:$(SIZE) (LVA) = _value; +} + +:wide_astore index is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc43a); indexbyte1; indexbyte2 [index = (indexbyte1 << 8) | indexbyte2;] +{ + _value :$(SIZE) = 0; + pop(_value); + LVA = index * $(SIZE); + *[localVariableArray]:$(SIZE) (LVA) = _value; +} + +:wide_lstore index is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc437); indexbyte1; indexbyte2 [index = (indexbyte1 << 8) | indexbyte2;] +{ + _value :$(DOUBLE_SIZE) = 0; + pop2(_value); + LVA = index * $(SIZE); + *[localVariableArray]:$(DOUBLE_SIZE) (LVA) = _value; +} + +:wide_dstore index is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc439); indexbyte1; indexbyte2 [index = (indexbyte1 << 8) | indexbyte2;] +{ + _value :$(DOUBLE_SIZE) = 0; + pop2(_value); + LVA = index * $(SIZE); + *[localVariableArray]:$(DOUBLE_SIZE) (LVA) = _value; +} + +#wide ret +:wide_ret index is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc4a9); indexbyte1; indexbyte2 [index = (indexbyte1 << 8) | indexbyte2;] +{ + LVA = index * $(SIZE); + _value:$(SIZE) = *[localVariableArray]:$(SIZE) (LVA); + goto [_value]; +} + +#wide inc - instruction is called wide format 2 by JVM specification but iinc_w by javap +:iinc_w index, constant is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc484); indexbyte1; indexbyte2; constantbyte1; constantbyte2 [ index = (indexbyte1 << 8) | indexbyte2; constant = (constantbyte1 << 8) | constantbyte2;] +{ + fullIndex: $(SIZE) = 4*zext(index:2); + fullConstant: $(SIZE) = sext(constant:2); + intVal:$(SIZE) = *[localVariableArray]:$(SIZE) (fullIndex); + *[localVariableArray]:$(SIZE) (fullIndex) = (intVal + fullConstant); +} diff --git a/python/icicle/Ghidra/Processors/M8C/data/languages/m8c.cspec b/python/icicle/Ghidra/Processors/M8C/data/languages/m8c.cspec new file mode 100644 index 0000000..7f56146 --- /dev/null +++ b/python/icicle/Ghidra/Processors/M8C/data/languages/m8c.cspec @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/M8C/data/languages/m8c.ldefs b/python/icicle/Ghidra/Processors/M8C/data/languages/m8c.ldefs new file mode 100644 index 0000000..466b797 --- /dev/null +++ b/python/icicle/Ghidra/Processors/M8C/data/languages/m8c.ldefs @@ -0,0 +1,15 @@ + + + + + Cypress M8C Microcontroller Family + + + diff --git a/python/icicle/Ghidra/Processors/M8C/data/languages/m8c.opinion b/python/icicle/Ghidra/Processors/M8C/data/languages/m8c.opinion new file mode 100644 index 0000000..32f57be --- /dev/null +++ b/python/icicle/Ghidra/Processors/M8C/data/languages/m8c.opinion @@ -0,0 +1,5 @@ + + + + + diff --git a/python/icicle/Ghidra/Processors/M8C/data/languages/m8c.pspec b/python/icicle/Ghidra/Processors/M8C/data/languages/m8c.pspec new file mode 100644 index 0000000..ed56ec9 --- /dev/null +++ b/python/icicle/Ghidra/Processors/M8C/data/languages/m8c.pspec @@ -0,0 +1,88 @@ + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/M8C/data/languages/m8c.slaspec b/python/icicle/Ghidra/Processors/M8C/data/languages/m8c.slaspec new file mode 100644 index 0000000..390722d --- /dev/null +++ b/python/icicle/Ghidra/Processors/M8C/data/languages/m8c.slaspec @@ -0,0 +1,977 @@ +# sleigh specification file for Cypress M8C + +define endian=big; +define alignment=1; + + +define space CODE type=ram_space size=2 default; +define space RAM type=ram_space size=1; +define space BANK0 type=ram_space size=1; +define space BANK1 type=ram_space size=1; +define space register type=register_space size=1; + + +################################################################ +# Registers +################################################################ + +define register offset=0x00 size=1 [ A X SP F]; +define register offset=0x10 size=2 [ PC ]; +define register offset=0x30 size=4 [ contextreg ]; + +# individual bits within Flags Register F + +@define XIO "F[4,1]" # Extend I/O bank select +@define S "F[3,1]" # Supervisor code +@define C "F[2,1]" # Carry +@define Z "F[1,1]" # Zero +@define IE "F[0,1]" # Global Interrupt Enable + + +define context contextreg + regbank=(0,0) +; + +################################################################ +# Tokens +################################################################ + +define token opcode (8) + op8 = (0,7) + op71 = (1,7) + op73 = (3,7) + op74 = (4,7) + op20 = (0,2) + op10 = (0,1) + op0 = (0,0) +; + +define token data8 (8) + addr8 = (0,7) + imm8 = (0,7) + simm8 = (0,7) signed + rel = (0,7) signed + rsb = (4,4) + sign = (7,7) +; + +define token data16 (16) + imm16 = (0,15) + simm16 = (0,15) signed + addr16 = (0,15) +; + +define token relinstr (16) + op4 = (12,15) + srel12 = (0,11) signed +; + +################################################################ +# Pseudo Instructions +################################################################ + +define pcodeop halt; +define pcodeop nop; +define pcodeop syscall; + +macro push8(val) +{ + *[RAM]:1 SP = val; + SP = SP + 1; +} + +macro push16(val) +{ + *[RAM]:2 SP = val; + SP = SP + 2; +} + +macro pop8(val) +{ + SP = SP - 1; + val = *[RAM]:1 SP; +} + +macro pop16(val) +{ + SP = SP - 2; + val = *[RAM]:2 SP; +} + +macro compflags(op1, op2) +{ + tmp1:1 = op1; + tmp2:1 = op2; + $(C) = (tmp1 < tmp2); + $(Z) = (tmp1 == tmp2); +} + +macro testflags(op1, op2) +{ + $(Z) = ((op1 & op2) == 0); +} + +macro addflags(op1, op2) +{ + t1:2 = zext(op1); + t2:2 = zext(op2); + tmp:2 = t1 + t2; + $(C) = tmp > 255; + $(Z) = (((op1 + op2) & 0xFF) == 0); +} + +macro resultflags(result) +{ + $(C) = result s< 0; + $(Z) = result == 0; +} + +macro zeroflag(result) +{ + $(Z) = result == 0; +} + +################################################################ +# Addressing tables +################################################################ + +regAorX: A is op0=0 & A { export A; } +regAorX: X is op0=1 & X { export X; } +Addr8: addr8 is addr8 { export *[RAM]:1 addr8; } +SAddr8: addr8 is addr8 { export *[RAM]:1 addr8; } +XAddr8: [X+simm8] is X & simm8 & sign=0 { ptr:1 = X + simm8; export *[RAM]:1 ptr; } +XAddr8: [X+simm8] is X & simm8 & sign=1 { ptr:1 = X - ~simm8; export *[RAM]:1 ptr; } +Addr8Incr: [Addr8]"++" is Addr8 { export Addr8; } + +RAddr8: addr8 is addr8 & regbank=0 { export *[BANK0]:1 addr8; } +RAddr8: addr8 is addr8 & regbank=1 { export *[BANK1]:1 addr8; } +RXAddr8: [X+simm8] is X & simm8 & regbank=0 { ptr:1 = X + simm8; export *[BANK0]:1 ptr; } +RXAddr8: [X+simm8] is X & simm8 & regbank=1 { ptr:1 = X + simm8; export *[BANK1]:1 ptr; } + +Imm8: "#"imm8 is imm8 { export *[const]:1 imm8; } + +Addr16: addr16 is addr16 { export *:2 addr16; } +RelAddr: reladdr is srel12 [ reladdr = inst_start + 1 + srel12; ] { export *:2 reladdr; } +CallAddr: calladdr is srel12 [ calladdr = inst_start + 2 + srel12; ] { export *:2 calladdr; } +IndexAddr: indexaddr is srel12 [ indexaddr = inst_start + 2 + srel12;] { export *[CODE]:2 indexaddr; } + +################################################################ +# Constructors +################################################################ + +:ADC A, Imm8 is op73=0x01 & op20=0x01 & A; Imm8 +{ + A = A + Imm8 + $(C); + resultflags(A); +} + +:ADC A, Addr8 is op73=0x01 & op20=0x02 & A; Addr8 +{ + A = A + Addr8 + $(C); + resultflags(A); +} + +:ADC A, XAddr8 is op73=0x01 & op20=0x03 & A; XAddr8 +{ + A = A + XAddr8 + $(C); + resultflags(A); +} + +:ADC Addr8, A is op73=0x01 & op20=0x04 & A; Addr8 +{ + tmp:1 = Addr8 + A + $(C); + Addr8 = tmp; + resultflags(tmp); +} + +:ADC XAddr8, A is op73=0x01 & op20=0x05 & A; XAddr8 +{ + tmp:1 = XAddr8 + A + $(C); + XAddr8 = tmp; + resultflags(tmp); +} + +:ADC Addr8, Imm8 is op73=0x01 & op20=0x06; Addr8; Imm8 +{ + tmp:1 = Addr8 + Imm8 + $(C); + Addr8 = tmp; + resultflags(tmp); + +} + +:ADC XAddr8, Imm8 is op73=0x01 & op20=0x07; XAddr8; Imm8 +{ + tmp:1 = XAddr8 + Imm8 + $(C); + XAddr8 = tmp; + resultflags(tmp); + +} + +:ADD A, Imm8 is op73=0x00 & op20=0x01 & A; Imm8 +{ + addflags(A, Imm8); + A = A + Imm8; +} + +:ADD A, Addr8 is op73=0x00 & op20=0x02 & A; Addr8 +{ + addflags(A, Addr8); + A = A + Addr8; +} + +:ADD A, XAddr8 is op73=0x00 & op20=0x03 & A; XAddr8 +{ + addflags(A, XAddr8); + A = A + XAddr8; +} + +:ADD Addr8, A is op73=0x00 & op20=0x04 & A; Addr8 +{ + addflags(Addr8, A); + Addr8 = Addr8 + A; +} + +:ADD XAddr8, A is op73=0x00 & op20=0x05 & A; XAddr8 +{ + addflags(XAddr8, A); + XAddr8 = XAddr8 + A; +} + +:ADD Addr8, Imm8 is op73=0x00 & op20=0x06; Addr8; Imm8 +{ + addflags(Addr8, Imm8); + Addr8 = Addr8 + Imm8; +} + +:ADD XAddr8, Imm8 is op73=0x00 & op20=0x07; XAddr8; Imm8 +{ + addflags(XAddr8, Imm8); + XAddr8 = XAddr8 + Imm8; +} + +:ADD SP, simm8 is op8=0x38 & SP; simm8 +{ + SP = SP + simm8; +} + +:AND A, Imm8 is op73=0x04 & op20=0x01 & A; Imm8 +{ + A = A & Imm8; + zeroflag(A); +} + +:AND A, Addr8 is op73=0x04 & op20=0x02 & A; Addr8 +{ + A = A & Addr8; + zeroflag(A); +} + +:AND A, XAddr8 is op73=0x04 & op20=0x03 & A; XAddr8 +{ + A = A & XAddr8; + zeroflag(A); +} + +:AND Addr8, A is op73=0x04 & op20=0x04 & A; Addr8 +{ + tmp:1 = Addr8 & A; + Addr8 = tmp; + zeroflag(tmp); +} + +:AND XAddr8, A is op73=0x04 & op20=0x05 & A; XAddr8 +{ + tmp:1 = XAddr8 & A; + XAddr8 = tmp; + zeroflag(tmp); +} + +:AND Addr8, Imm8 is op73=0x04 & op20=0x06; Addr8; Imm8 +{ + tmp:1 = Addr8 & Imm8; + Addr8 = tmp; + zeroflag(tmp); +} + +:AND XAddr8, Imm8 is op73=0x04 & op20=0x07; XAddr8; Imm8 +{ + tmp:1 = XAddr8 & Imm8; + XAddr8 = tmp; + zeroflag(tmp); +} + +:AND RAddr8, Imm8 is op8=0x41; RAddr8; Imm8 +{ + tmp:1 = RAddr8 & Imm8; + RAddr8 = tmp; + zeroflag(tmp); +} + +:AND RXAddr8, Imm8 is op8=0x42; RXAddr8; Imm8 +{ + tmp:1 = RXAddr8 & Imm8; + RXAddr8 = tmp; + zeroflag(tmp); +} + +:AND F, imm8 is op8=0x70 & F; imm8 & rsb + [ regbank = regbank & rsb; globalset(inst_next, regbank); ] +{ + F = F & imm8; +} + +:ASL A is op8=0x64 & A +{ + A = A << 1:1; +} + +:ASL Addr8 is op8=0x65; Addr8 +{ + Addr8 = Addr8 << 1:1; +} + +:ASL XAddr8 is op8=0x66; XAddr8 +{ + XAddr8 = XAddr8 << 1:1; +} + +:ASR A is op8=0x67 & A +{ + A = A >> 1:1; +} + +:ASR Addr8 is op8=0x68; Addr8 +{ + Addr8 = Addr8 >> 1:1; +} + +:ASR XAddr8 is op8=0x69; XAddr8 +{ + XAddr8 = XAddr8 >> 1:1; +} + +:CALL CallAddr is op4=0x9 & CallAddr +{ + ret:2 = inst_next; + push16(ret); + call CallAddr; +} + +:CMP A, Imm8 is op8=0x39 & A; Imm8 +{ + compflags(A, Imm8); +} + +:CMP A, Addr8 is op8=0x3A & A; Addr8 +{ + + compflags(A, Addr8); +} + +:CMP A, XAddr8 is op8=0x3B & A; XAddr8 +{ + compflags(A, XAddr8); +} + +:CMP Addr8, Imm8 is op8=0x3C; Addr8; Imm8 +{ + compflags(Addr8, Imm8); +} + +:CMP XAddr8, Imm8 is op8=0x3D; XAddr8; Imm8 +{ + temp:1 = XAddr8; + compflags(temp, Imm8); +} + +:CPL A is op8=0x73 & A +{ + A = ~A; +} + +:DEC regAorX is op71=0x3C & regAorX +{ + regAorX = regAorX - 1:1; + resultflags(regAorX); +} + +:DEC Addr8 is op71=0x3D & op0=0; Addr8 +{ + Addr8 = Addr8 - 1:1; + resultflags(Addr8); +} + +:DEC XAddr8 is op71=0x3D & op0=1; XAddr8 +{ + XAddr8 = XAddr8 - 1:1; + resultflags(XAddr8); +} + +:HALT is op8=0x30 +{ + halt(); +} + +:INC regAorX is op71=0x3A & regAorX +{ + addflags(regAorX, 1:1); + regAorX = regAorX + 1:1; +} + +:INC Addr8 is op71=0x3B & op0=0; Addr8 +{ + addflags(Addr8, 1:1); + Addr8 = Addr8 + 1:1; +} + +:INC XAddr8 is op71=0x3B & op0=1; XAddr8 +{ + addflags(XAddr8, 1:1); + XAddr8 = XAddr8 + 1:1; +} + +:INDEX IndexAddr is op4=0xF & IndexAddr & srel12 +{ + ptr:2 = inst_start + 2 + srel12 + zext(A); + A = *[CODE]:1 ptr; +} + +:JACC RelAddr is op4=0xE & RelAddr +{ + tmp:2 = sext(A); + target:2 = RelAddr + sext(A); + goto [target]; +} + +:JC RelAddr is op4=0xC & RelAddr +{ + if ($(C) != 0) goto RelAddr; +} + +:JMP RelAddr is op4=0x8 & RelAddr +{ + goto RelAddr; +} + +:JNC RelAddr is op4=0xD & RelAddr +{ + if ($(C) == 0) goto RelAddr; +} + +:JNZ RelAddr is op4=0xB & RelAddr +{ + if ($(Z) == 0) goto RelAddr; +} + +:JZ RelAddr is op4=0xA & RelAddr +{ + if ($(Z) == 1) goto RelAddr; +} + +:LCALL Addr16 is op8=0x7C; Addr16 +{ + ret:2 = inst_next; + push16(ret); + call Addr16; +} + +:LJMP Addr16 is op8=0x7D; Addr16 +{ + goto Addr16; +} + +:MOV X, SP is op8=0x4F & X & SP +{ + X = SP; +} + +:MOV A, Imm8 is op8=0x50 & A; Imm8 +{ + A = Imm8; + zeroflag(A); +} + +:MOV A, Addr8 is op8=0x51 & A; Addr8 +{ + A = Addr8; + zeroflag(A); +} + +:MOV A, XAddr8 is op8=0x52 & A; XAddr8 +{ + A = XAddr8; + zeroflag(A); +} + +:MOV Addr8, A is op8=0x53 & A; Addr8 +{ + Addr8 = A; +} + +:MOV XAddr8, A is op8=0x54 & A; XAddr8 +{ + XAddr8 = A; +} + +:MOV Addr8, Imm8 is op8=0x55; Addr8; Imm8 +{ + Addr8 = Imm8; +} + +:MOV XAddr8, Imm8 is op8=0x56; XAddr8; Imm8 +{ + XAddr8 = Imm8; +} + +:MOV X, Imm8 is op8=0x57 & X; Imm8 +{ + X = Imm8; +} + +:MOV X, Addr8 is op8=0x58 & X; Addr8 +{ + X = Addr8; +} + +:MOV X, XAddr8 is op8=0x59 & X; XAddr8 +{ + X = XAddr8; +} + +:MOV Addr8, X is op8=0x5A & X; Addr8 +{ + Addr8 = X; +} + +:MOV A, X is op8=0x5B & A & X +{ + A = X; + zeroflag(A); +} + +:MOV X, A is op8=0x5C & A & X +{ + X = A; +} + +:MOV A, RAddr8 is op8=0x5D & A; RAddr8 +{ + A = RAddr8; + zeroflag(A); +} + +:MOV A, RXAddr8 is op8=0x5E & A; RXAddr8 +{ + A = RXAddr8; + zeroflag(A); +} + +:MOV Addr8, SAddr8 is op8=0x5F; Addr8; SAddr8 +{ + Addr8 = SAddr8; +} + +:MOV RAddr8, A is op8=0x60 & A; RAddr8 +{ + RAddr8 = A; +} + +:MOV RXAddr8, A is op8=0x61 & A; RXAddr8 +{ + RXAddr8 = A; +} + +:MOV RAddr8, Imm8 is op8=0x62; RAddr8; Imm8 +{ + RAddr8 = Imm8; +} + +:MOV RXAddr8, Imm8 is op8=0x63; RXAddr8; Imm8 +{ + RXAddr8 = Imm8; +} + +:MVI A, Addr8Incr is op8=0x3E & A; Addr8Incr +{ + ptr:1 = Addr8Incr; + A = *[RAM]:1 ptr; + zeroflag(A); + Addr8Incr = ptr + 1:1; +} + +:MVI Addr8Incr, A is op8=0x3F & A; Addr8Incr +{ + ptr:1 = Addr8Incr; + *[RAM]:1 ptr = A; + Addr8Incr = ptr + 1:1; +} + +:NOP is op8=0x40 +{ + nop(); +} + +:OR A, Imm8 is op73=0x05 & op20=0x01 & A; Imm8 +{ + A = A | Imm8; + zeroflag(A); +} + +:OR A, Addr8 is op73=0x05 & op20=0x02 & A; Addr8 +{ + A = A | Addr8; + zeroflag(A); +} + +:OR A, XAddr8 is op73=0x05 & op20=0x03 & A; XAddr8 +{ + A = A | XAddr8; + zeroflag(A); +} + +:OR Addr8, A is op73=0x05 & op20=0x04 & A; Addr8 +{ + tmp:1 = Addr8 | A; + zeroflag(tmp); + Addr8 = tmp; +} + +:OR XAddr8, A is op73=0x05 & op20=0x05 & A; XAddr8 +{ + tmp:1 = XAddr8 | A; + zeroflag(tmp); + XAddr8 = tmp; +} + +:OR Addr8, Imm8 is op73=0x05 & op20=0x06; Addr8; Imm8 +{ + tmp:1 = Addr8 | Imm8; + zeroflag(tmp); + Addr8 = tmp; +} + +:OR XAddr8, Imm8 is op73=0x05 & op20=0x07; XAddr8; Imm8 +{ + tmp:1 = XAddr8 | Imm8; + zeroflag(tmp); + XAddr8 = tmp; +} + +:OR RAddr8, Imm8 is op8=0x43; RAddr8; Imm8 +{ + tmp:1 = RAddr8 | Imm8; + zeroflag(tmp); + RAddr8 = tmp; +} + +:OR RXAddr8, Imm8 is op8=0x44; RXAddr8; Imm8 +{ + tmp:1 = RXAddr8 | Imm8; + zeroflag(tmp); + RXAddr8 = tmp; +} + +:OR F, imm8 is op8=0x71 & F; imm8 & rsb + [ regbank = regbank | rsb; globalset(inst_next, regbank); ] +{ + F = F | imm8; +} + +:POP X is op8=0x20 & X +{ + pop8(X); +} + +:POP A is op8=0x18 & A +{ + pop8(A); +} + +:PUSH X is op8=0x10 & X +{ + push8(X); +} + +:PUSH A is op8=0x08 & A +{ + push8(A); +} + +:RETI is op8=0x7E +{ + pc:2 = 0; + pop16(pc); + return[pc]; +} + +:RET is op8=0x7F +{ + pc:2 = 0; + pop16(pc); + return[pc]; +} + +:RLC A is op8=0x6A & A +{ + c:1 = (A & 0x80) >> 7:1; + A = (A << 1:1) | $(C); + $(C) = c; +} + +:RLC Addr8 is op8=0x6B; Addr8 +{ + tmp:1 = Addr8; + c:1 = (tmp & 0x80) >> 7:1; + Addr8 = (tmp << 1) | $(C); + $(C) = c; +} + +:RLC XAddr8 is op8=0x6C; XAddr8 +{ + tmp:1 = XAddr8; + c:1 = (tmp & 0x80) >> 7:1; + XAddr8 = (tmp << 1) | $(C); + $(C) = c; +} + +:ROMX is op8=0x28 +{ + msb:2 = zext(A) << 8:1; + ptr:2 = msb | zext(X); + A = *[CODE]:1 ptr; + zeroflag(A); +} + +:RRC A is op8=0x6D & A +{ + c:1 = A & 0x01:1; + A = (A >> 1) | ($(C) << 7:1); + $(C) = c; +} + +:RRC Addr8 is op8=0x6E; Addr8 +{ + tmp:1 = Addr8; + c:1 = tmp & 0x01:1; + Addr8 = (tmp >> 1:1) | ($(C) << 7:1); + $(C) = c; +} + +:RRC XAddr8 is op8=0x6F; XAddr8 +{ + tmp:1 = XAddr8; + c:1 = tmp & 0x01; + XAddr8 = (tmp >> 1:1) | ($(C) << 7:1); + $(C) = c; +} + +:SBB A, Imm8 is op73 = 0x03 & op20=0x01 & A; Imm8 +{ + A = A - (Imm8 + $(C)); + resultflags(A); +} + +:SBB A, Addr8 is op73 = 0x03 & op20=0x02 & A; Addr8 +{ + A = A - (Addr8 + $(C)); + resultflags(A); +} + +:SBB A, XAddr8 is op73 = 0x03 & op20=0x03 & A; XAddr8 +{ + A = A - (XAddr8 + $(C)); + resultflags(A); +} + +:SBB Addr8, A is op73 = 0x03 & op20=0x04 & A; Addr8 +{ + tmp:1 = Addr8 - (A + $(C)); + resultflags(tmp); + Addr8 = tmp; +} + +:SBB XAddr8, A is op73 = 0x03 & op20=0x05 & A; XAddr8 +{ + tmp:1 = XAddr8 - (A + $(C)); + resultflags(tmp); + XAddr8 = tmp; +} + +:SBB Addr8, Imm8 is op73 = 0x03 & op20=0x06; Addr8; Imm8 +{ + tmp:1 = Addr8 - (Imm8 + $(C)); + resultflags(tmp); + Addr8 = tmp; +} + +:SBB XAddr8, Imm8 is op73 = 0x03 & op20=0x07; XAddr8; Imm8 +{ + local tmp = XAddr8 - (Imm8 + $(C)); + resultflags(tmp); + XAddr8 = tmp; +} + +:SSC is op8=0x00 +{ + syscall(A); +} + +:SUB A, Imm8 is op73 = 0x02 & op20=0x01 & A; Imm8 +{ + A = A - Imm8; + resultflags(A); +} + +:SUB A, Addr8 is op73 = 0x02 & op20=0x02 & A; Addr8 +{ + A = A - Addr8; + resultflags(A); +} + +:SUB A, XAddr8 is op73 = 0x02 & op20=0x03 & A; XAddr8 +{ + A = A - XAddr8; + resultflags(A); +} + +:SUB Addr8, A is op73 = 0x02 & op20=0x04 & A; Addr8 +{ + tmp:1 = Addr8 - A; + resultflags(tmp); + Addr8 = tmp; +} + +:SUB XAddr8, A is op73 = 0x02 & op20=0x05 & A; XAddr8 +{ + tmp:1 = XAddr8 - A; + resultflags(tmp); + XAddr8 = tmp; +} + +:SUB Addr8, Imm8 is op73 = 0x02 & op20=0x06; Addr8; Imm8 +{ + tmp:1 = Addr8 - Imm8; + resultflags(tmp); + Addr8 = tmp; +} + +:SUB XAddr8, Imm8 is op73 = 0x02 & op20=0x07; XAddr8; Imm8 +{ + tmp:1 = XAddr8 - Imm8; + resultflags(tmp); + XAddr8 = tmp; +} + +:SWAP A, X is op8=0x4B & A & X +{ + tmp:1 = A; + A = X; + X = tmp; +} + +:SWAP regAorX, Addr8 is op71=0x26 & regAorX; Addr8 +{ + tmp:1 = regAorX; + regAorX = Addr8; + Addr8 = tmp; +} + +:SWAP A, SP is op8=0x4E & A & SP +{ + tmp:1 = A; + A = SP; + SP = tmp; +} + +:TST Addr8, Imm8 is op8=0x47; Addr8; Imm8 +{ + tmp:1 = Addr8; + testflags(tmp, Imm8); +} + +:TST XAddr8, Imm8 is op8=0x48; XAddr8; Imm8 +{ + tmp:1 = XAddr8; + testflags(tmp, Imm8); +} + +:TST RAddr8, Imm8 is op8=0x49; RAddr8; Imm8 +{ + tmp:1 = RAddr8; + testflags(tmp, Imm8); +} + +:TST RXAddr8, Imm8 is op8=0x4A; RXAddr8; Imm8 +{ + tmp:1 = RXAddr8; + testflags(tmp, Imm8); +} + +:XOR A, Imm8 is op73=0x06 & op20=0x01 & A; Imm8 +{ + A = A ^ Imm8; + zeroflag(A); +} + +:XOR A, Addr8 is op73=0x06 & op20=0x02 & A; Addr8 +{ + A = A ^ Addr8; + zeroflag(A); +} + +:XOR A, XAddr8 is op73=0x06 & op20=0x03 & A; XAddr8 +{ + A = A ^ XAddr8; + zeroflag(A); +} + +:XOR Addr8, A is op73=0x06 & op20=0x04 & A; Addr8 +{ + tmp:1 = Addr8 ^ A; + zeroflag(Addr8); + Addr8 = tmp; +} + +:XOR XAddr8, A is op73=0x06 & op20=0x05 & A; XAddr8 +{ + tmp:1 = XAddr8 ^ A; + zeroflag(tmp); + XAddr8 = tmp; +} + +:XOR Addr8, Imm8 is op73=0x06 & op20=0x06; Addr8; Imm8 +{ + tmp:1 = Addr8 ^ Imm8; + zeroflag(tmp); + Addr8 = tmp; +} + +:XOR XAddr8, Imm8 is op73=0x06 & op20=0x07; XAddr8; Imm8 +{ + tmp:1 = XAddr8 ^ Imm8; + zeroflag(tmp); + XAddr8 = tmp; +} + +:XOR RAddr8, Imm8 is op8=0x45; RAddr8; Imm8 +{ + tmp:1 = RAddr8 ^ Imm8; + zeroflag(tmp); + RAddr8 = tmp; +} + +:XOR RXAddr8, Imm8 is op8=0x46; RXAddr8; Imm8 +{ + tmp:1 = RXAddr8 ^ Imm8; + zeroflag(tmp); + RXAddr8 = tmp; +} + +:XOR F, imm8 is op8=0x72 & F; imm8 & rsb + [ regbank = regbank ^ rsb; globalset(inst_next, regbank); ] +{ + tmp:1 = F ^ imm8; + resultflags(tmp); + F = tmp; +} + diff --git a/python/icicle/Ghidra/Processors/MC6800/data/languages/6800.ldefs b/python/icicle/Ghidra/Processors/MC6800/data/languages/6800.ldefs new file mode 100644 index 0000000..fe2fcf9 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MC6800/data/languages/6800.ldefs @@ -0,0 +1,33 @@ + + + + 6809 Microprocessor + + + + + + + + + Hitachi 6309 Microprocessor, extension of 6809, 6309 addressing modes, missing many instructions + + + + \ No newline at end of file diff --git a/python/icicle/Ghidra/Processors/MC6800/data/languages/6805.cspec b/python/icicle/Ghidra/Processors/MC6800/data/languages/6805.cspec new file mode 100644 index 0000000..73d0466 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MC6800/data/languages/6805.cspec @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/MC6800/data/languages/6805.ldefs b/python/icicle/Ghidra/Processors/MC6800/data/languages/6805.ldefs new file mode 100644 index 0000000..d9ad948 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MC6800/data/languages/6805.ldefs @@ -0,0 +1,15 @@ + + + + 6805 Microcontroller Family + + + + \ No newline at end of file diff --git a/python/icicle/Ghidra/Processors/MC6800/data/languages/6805.pspec b/python/icicle/Ghidra/Processors/MC6800/data/languages/6805.pspec new file mode 100644 index 0000000..c7b09d5 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MC6800/data/languages/6805.pspec @@ -0,0 +1,38 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/MC6800/data/languages/6805.slaspec b/python/icicle/Ghidra/Processors/MC6800/data/languages/6805.slaspec new file mode 100644 index 0000000..23d42bb --- /dev/null +++ b/python/icicle/Ghidra/Processors/MC6800/data/languages/6805.slaspec @@ -0,0 +1,669 @@ +# sleigh specification file for Motorola 6805 +define endian=big; +define alignment=1; + +define space RAM type=ram_space size=2 default; +define space register type=register_space size=1; + +define register offset=0x00 size=1 [ A X ]; +define register offset=0x20 size=2 [ PC SP]; +define register offset=0x30 size=1 [H I N Z C]; # status bits + +define RAM offset=0x3ffc size=2 [ SWI_VECTOR ]; +#TOKENS + +define token opbyte (8) + op = (0,7) + op4_7 = (4,7) + op4_6 = (4,6) + n = (1,3) + bit_0 = (0,0) +; + +define token data8 (8) + imm8 = (0,7) + rel = (0,7) signed +; + +define token data (16) + imm16 = (0,15) +; +################################################################ +# Pseudo Instructions +################################################################ + +define pcodeop readIRQ; + +################################################################ +REL: reloc is rel [ reloc = inst_next + rel; ] { export *:2 reloc; } + +OP1: "#"imm8 is op4_6=2; imm8 { tmp:1 = imm8; export tmp; } +OP1: imm8 is op4_6=3; imm8 { export *:1 imm8; } +OP1: imm16 is op4_6=4; imm16 { export *:1 imm16; } +OP1: imm16,X is op4_6=5 & X; imm16 { tmp:2 = imm16 + zext(X); export *:1 tmp; } +OP1: imm8,X is op4_6=6 & X; imm8 { tmp:2 = imm8 + zext(X); export *:1 tmp; } +OP1: X is op4_6=7 & X { tmp:2 = zext(X); export *:1 tmp; } + +ADDR: imm8 is op4_6=3; imm8 { export *:1 imm8; } +ADDR: imm16 is op4_6=4; imm16 { export *:1 imm16; } +ADDRI: imm16,X is op4_6=5 & X; imm16 { tmp:2 = imm16 + zext(X); export tmp; } +ADDRI: imm8,X is op4_6=6 & X; imm8 { tmp:2 = imm8 + zext(X); export tmp; } +ADDRI: X is op4_6=7 & X { tmp:2 = zext(X); export tmp; } + + +DIRECT: imm8 is imm8 { export *:1 imm8; } + +:ADC OP1 is (op=0xA9 | op=0xB9 | op=0xC9 | op=0xD9 | op=0xE9 | op=0xF9) ... & OP1 +{ + local op1 = OP1; + + # compute half carry + local halfop1 = op1 & 0xF; + local halfA = A & 0xF; + local halfresult = halfop1 + halfA + C; + H = (halfresult >> 4) & 1; + + local result = A + op1; + local tmpC = carry(A, op1); + + A = result + C; + C = carry(result, C); + C = C | tmpC; + Z = (A == 0); + N = (A s< 0); +} +:ADD OP1 is (op=0xAB | op=0xBB | op=0xCB | op=0xDB | op=0xEB | op=0xFB) ... & OP1 +{ + local op1 = OP1; + + # compute half carry + local halfop1 = op1 & 0xF; + local halfA = A & 0xF; + local halfresult = halfop1 + halfA; + H = (halfresult >> 4) & 1; + + C = carry(A, op1); + A = A + op1; + Z = (A == 0); + N = (A s< 0); +} + +:AND OP1 is (op=0xA4 | op=0xB4 | op=0xC4 | op=0xD4 | op=0xE4 | op=0xF4) ... & OP1 +{ + A = A & OP1; + Z = (A == 0); + N = (A s< 0); +} + +:ASLA is op=0x48 +{ + C = A >> 7; + A = A << 1; + Z = (A == 0); + N = (A s< 0); +} +:ASLX is op=0x58 +{ + C = X >> 7; + X = X << 1; + Z = (X == 0); + N = (X s< 0); +} +:ASL OP1 is (op=0x38 | op=0x68 | op=0x78) ... & OP1 +{ + local tmp = OP1; + C = tmp >> 7; + tmp = tmp << 1; + OP1 = tmp; + Z = (tmp == 0); + N = (tmp s< 0); +} +:ASRA is op=0x47 +{ + C = A & 1; + A = A s>> 1; + Z = (A == 0); + N = (A s< 0); +} +:ASRX is op=0x57 +{ + C = X & 1; + X = X s>> 1; + Z = (X == 0); + N = (X s< 0); +} +:ASR OP1 is (op=0x37 | op=0x67 | op=0x77) ... & OP1 +{ + local tmp = OP1; + C = tmp & 1; + tmp = tmp s>> 1; + OP1 = tmp; + Z = (tmp == 0); + N = (tmp s< 0); +} + +:BCC REL is op=0x24;REL +{ + if (C == 0) goto REL; +} + +:BCLR n,DIRECT is op4_7=1 & bit_0=1 & n; DIRECT { + local mask = ~(1 << n); + DIRECT = DIRECT & mask; +} +:BCS REL is op=0x25;REL +{ + if (C) goto REL; +} +:BEQ REL is op=0x27;REL +{ + if (Z) goto REL; +} +:BHCC REL is op=0x28;REL +{ + if (H == 0) goto REL; +} +:BHCS REL is op=0x29;REL +{ + if (H) goto REL; +} +:BHI REL is op=0x22;REL +{ + local tmp = C + Z; + if (tmp == 0) goto REL; +} + +#:BHS REL is op=0x24;REL See BCC + +:BIH REL is op=0x2F;REL +{ + tmp:1 = readIRQ(); + if (tmp) goto REL; +} +:BIL REL is op=0x2E;REL +{ + tmp:1 = readIRQ(); + if (tmp == 0) goto REL; +} +:BIT OP1 is (op=0xA5 | op=0xB5 | op=0xC5 | op=0xD5 | op=0xE5 | op=0xF5) ... & OP1 +{ + local result = A & OP1; + Z = (result == 0); + N = (result s< 0); +} +#:BLO REL is op=0x25;REL see BCS + +:BLS REL is op=0x23;REL +{ + local tmp = C + Z; + if (tmp) goto REL; +} + +:BMC REL is op=0x2C;REL +{ + if (I == 0) goto REL; +} +:BMI REL is op=0x2B;REL +{ + if (N) goto REL; +} +:BMS REL is op=0x2D;REL +{ + if (I) goto REL; +} +:BNE REL is op=0x26;REL +{ + if (Z == 0) goto REL; +} +:BPL REL is op=0x2A;REL +{ + if (N == 0) goto REL; +} +:BRA REL is op=0x20;REL +{ + goto REL; +} + +:BRN REL is op=0x21;REL +{ +} + +:BRCLR n,DIRECT,REL is op4_7=0 & bit_0=1 & n; DIRECT; REL +{ + local mask = (1 << n); + local result = DIRECT & mask; + if (result == 0) goto REL; +} + +:BRSET n,DIRECT,REL is op4_7=0 & bit_0=0 & n; DIRECT; REL +{ + local mask = (1 << n); + local result = DIRECT & mask; + if (result != 0) goto REL; +} + +:BSET n,DIRECT is op4_7=1 & bit_0=0 & n; DIRECT { + local mask = (1 << n); + DIRECT = DIRECT | mask; +} + +:BSR REL is op=0xAD; REL +{ + SP=SP-1; + *:2 SP = inst_next; + SP=SP-1; + call REL; +} + +:CLC is op=0x98 +{ + C = 0; +} + +:CLI is op=0x9A +{ + I = 0; +} +:CLRA is op=0x4F +{ + A = 0; + Z = 1; + N = 0; +} +:CLRX is op=0x5F +{ + X = 0; + Z = 1; + N = 0; +} +:CLR OP1 is (op=0x3F | op=0x6F | op=0x7F) ... & OP1 +{ + OP1 = 0; + Z = 1; + N = 0; +} +:CMP OP1 is (op=0xA1 | op=0xB1 | op=0xC1 | op=0xD1 | op=0xE1 | op=0xF1) ... & OP1 +{ + local op1 = OP1; + local tmp = A - op1; + Z = tmp == 0; + N = tmp s< 0; + C = (A < op1); +} + +:COMA is op=0x43 +{ + A = ~A; + Z = (A == 0); + N = (A s< 0); + C = 1; +} +:COMX is op=0x53 +{ + X = ~X; + Z = (X == 0); + N = (X s< 0); + C = 1; +} +:COM OP1 is (op=0x33 | op=0x63 | op=0x73) ... & OP1 +{ + local tmp = ~OP1; + OP1 = tmp; + Z = (tmp == 0); + N = (tmp s< 0); + C = 1; +} +:CPX OP1 is (op=0xA3 | op=0xB3 | op=0xC3 | op=0xD3 | op=0xE3 | op=0xF3) ... & OP1 +{ + local op1 = OP1; + local tmp = X - op1; + Z = tmp == 0; + N = tmp s< 0; + C = (X < op1); +} +:DECA is op=0x4A +{ + A = A - 1; + Z = (A == 0); + N = (A s< 0); +} +:DECX is op=0x5A +{ + X = X - 1; + Z = (X == 0); + N = (X s< 0); +} +:DEC OP1 is (op=0x3A | op=0x6A | op=0x7A) ... & OP1 +{ + local tmp = OP1 - 1; + OP1 = tmp; + Z = (tmp == 0); + N = (tmp s< 0); +} +:EOR OP1 is (op=0xA8 | op=0xB8 | op=0xC8 | op=0xD8 | op=0xE8 | op=0xF8) ... & OP1 +{ + local op1 = OP1; + A = A ^ op1; + Z = A == 0; + N = A s< 0; +} +:INCA is op=0x4C +{ + A = A + 1; + Z = (A == 0); + N = (A s< 0); +} +:INCX is op=0x5C +{ + X = X + 1; + Z = (X == 0); + N = (X s< 0); +} +:INC OP1 is (op=0x3C | op=0x6C | op=0x7C) ... & OP1 +{ + local tmp = OP1 + 1; + OP1 = tmp; + Z = (tmp == 0); + N = (tmp s< 0); +} +:JMP ADDR is (op=0xBC | op=0xCC) ... & ADDR +{ + goto ADDR; +} + +:JMP ADDRI is (op=0xDC | op=0xEC | op=0xFC) ... & ADDRI +{ + goto [ADDRI]; +} + + +:JSR ADDR is (op=0xBD | op=0xCD) ... & ADDR +{ + *:2 (SP-1) = inst_next; + SP=SP-2; + call ADDR; +} +:JSR ADDRI is (op=0xDD | op=0xED | op=0xFD) ... & ADDRI +{ + *:2 (SP-1) = inst_next; + SP=SP-2; + call [ADDRI]; +} + +:LDA OP1 is (op=0xA6 | op=0xB6 | op=0xC6 | op=0xD6 | op=0xE6 | op=0xF6) ... & OP1 +{ + A = OP1; + Z = A == 0; + N = A s< 0; +} + +:LDX OP1 is (op=0xAE | op=0xBE | op=0xCE | op=0xDE | op=0xEE | op=0xFE) ... & OP1 +{ + X = OP1; + Z = X == 0; + N = X s< 0; +} + +## Logical Shift left is same as arithmetic shift left +#:LSLA is op=0x48 +#:LSLX is op=0x58 +#:LSL OP1 is (op=0x38 | op=0x68 | op=0x78) ... & OP1 +:LSRA is op=0x44 +{ + C = A & 1; + A = A >> 1; + Z = (A == 0); + N = 0; +} +:LSRX is op=0x54 +{ + C = X & 1; + X = X >> 1; + Z = (X == 0); + N = 0; +} +:LSR OP1 is (op=0x34 | op=0x64 | op=0x74) ... & OP1 +{ + local tmp = OP1; + C = tmp & 1; + tmp = tmp >> 1; + OP1 = tmp; + Z = (tmp == 0); + N = 0; +} + +:MUL is op=0x42 +{ + op1:2 = zext(A); + op2:2 = zext(X); + local result = op1 * op2; + A = result:1; + result = result >> 8; + X = result:1; +} + +:NEGA is op=0x40 +{ + C = A != 0; + A = -A; + Z = (A == 0); + N = (A s< 0); +} +:NEGX is op=0x50 +{ + C = X != 0; + X = -X; + Z = (X == 0); + N = (X s< 0); +} +:NEG OP1 is (op=0x30 | op=0x60 | op=0x70) ... & OP1 +{ + local op1 = OP1; + C = op1 != 0; + OP1 = -op1; + Z = (op1 == 0); + N = (op1 s< 0); +} + +:NOP is op = 0x9D +{ +} + +:ORA OP1 is (op=0xAA | op=0xBA | op=0xCA | op=0xDA | op=0xEA | op=0xFA) ... & OP1 +{ + A = A | OP1; + Z = (A == 0); + N = (A s< 0); +} + +:ROLA is op=0x49 +{ + local tmp = C ; + C = A >> 7; + A = A << 1; + A = A | tmp; + Z = (A == 0); + N = (A s< 0); +} +:ROLX is op=0x59 +{ + local tmp = C; + C = X >> 7; + X = X << 1; + X = X | tmp; + Z = (X == 0); + N = (X s< 0); +} +:ROL OP1 is (op=0x39 | op=0x69 | op=0x79) ... & OP1 +{ + local tmpC = C; + local op1 = OP1; + C = op1 >> 7; + local result = op1 << 1; + result = result | tmpC; + OP1 = result; + Z = (result == 0); + N = (result s< 0); +} +:RORA is op=0x46 +{ + local tmpC = C << 7; + C = A & 1; + A = A s>> 1; + A = A | tmpC; + Z = (A == 0); + N = (A s< 0); +} +:RORX is op=0x56 +{ + local tmpC = C << 7; + C = X & 1; + X = X s>> 1; + X = X | tmpC; + Z = (X == 0); + N = (X s< 0); +} +:ROR OP1 is (op=0x36 | op=0x66 | op=0x76) ... & OP1 +{ + local tmpC = C << 7; + local tmp = OP1; + C = tmp & 1; + tmp = tmp s>> 1; + tmp = tmp | tmpC; + OP1 = tmp; + Z = (tmp == 0); + N = (tmp s< 0); +} + +:RSP is op = 0x9C +{ + SP = 0xff; +} + +:RTI is op = 0x80 +{ + SP = SP+1; + local ccr = *:1 SP; + H = ccr[4,1]; + I = ccr[3,1]; + N = ccr[2,1]; + Z = ccr[1,1]; + C = ccr[0,1]; + + SP = SP+1; + A = *:1 SP; + + SP = SP+1; + X = *:1 SP; + SP = SP+1; + tmp:2 = *:2 SP; + SP = SP+1; + + return [tmp]; +} + +:RTS is op = 0x81 +{ + SP = SP+1; + tmp:2 = *:2 SP; + SP = SP+1; + + return [tmp]; +} + +:SBC OP1 is (op=0xA2 | op=0xB2 | op=0xC2 | op=0xD2 | op=0xE2 | op=0xF2) ... & OP1 +{ + local op1 = OP1; + local tmp = A - op1 - C; + Z = tmp == 0; + N = tmp s< 0; + C = ((A <= op1) * C) | (A < op1); + A = tmp; +} + +:SEC is op = 0x99 +{ + C = 1; +} + +:SEI is op = 0x9B +{ + I = 1; +} + +:STA OP1 is (op=0xB7 | op=0xC7 | op=0xD7 | op=0xE7 | op=0xF7) ... & OP1 +{ + OP1 = A; + Z = A == 0; + N = A s< 0; +} + +:STOP is op=0x8E +{ + I = 0; +} + +:STX OP1 is (op=0xBF | op=0xCF | op=0xDF | op=0xEF | op=0xFF) ... & OP1 +{ + OP1 = X; + Z = X == 0; + N = X s< 0; +} + +:SUB OP1 is (op=0xA0 | op=0xB0 | op=0xC0 | op=0xD0 | op=0xE0 | op=0xF0) ... & OP1 +{ + local op1 = OP1; + C = (A < op1); + A = A - op1; + Z = A == 0; + N = A s< 0; + A = A; +} + +:SWI is op=0x83 +{ + SP=SP-1; + *:2 SP = inst_next; + SP=SP-1; + *:1 SP = X; + SP=SP-1; + *:1 SP = A; + tmp:1 = 0b11100000 | (H << 4) | (I << 3) | (N << 2) | ( Z << 1) | C; + SP=SP-1; + *:1 SP = tmp; + I = 1; + call [SWI_VECTOR]; +} + +:TAX is op=0x97 +{ + X = A; +} + +:TSTA is op=0x4D +{ + Z = (A == 0); + N = (A s< 0); +} +:TSTX is op=0x5D +{ + Z = (X == 0); + N = (X s< 0); +} +:TST OP1 is (op=0x3D | op=0x6D | op=0x7D) ... & OP1 +{ + local op1 = OP1; + Z = (op1 == 0); + N = (op1 s< 0); +} + +:TXA is op=0x9F +{ + A = X; +} + +:WAIT is op=0x8f +{ + I = 0; +} + diff --git a/python/icicle/Ghidra/Processors/MC6800/data/languages/6809.cspec b/python/icicle/Ghidra/Processors/MC6800/data/languages/6809.cspec new file mode 100644 index 0000000..6368f91 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MC6800/data/languages/6809.cspec @@ -0,0 +1,37 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/MC6800/data/languages/6809.pspec b/python/icicle/Ghidra/Processors/MC6800/data/languages/6809.pspec new file mode 100644 index 0000000..0256aff --- /dev/null +++ b/python/icicle/Ghidra/Processors/MC6800/data/languages/6809.pspec @@ -0,0 +1,5 @@ + + + + + diff --git a/python/icicle/Ghidra/Processors/MC6800/data/languages/6809.slaspec b/python/icicle/Ghidra/Processors/MC6800/data/languages/6809.slaspec new file mode 100644 index 0000000..d1ddee1 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MC6800/data/languages/6809.slaspec @@ -0,0 +1,8 @@ +# sleigh specification file for Motorola 6809 + +@define M6809 "" + +@include "6x09.sinc" +@include "6x09_push.sinc" +@include "6x09_pull.sinc" +@include "6x09_exg_tfr.sinc" diff --git a/python/icicle/Ghidra/Processors/MC6800/data/languages/6x09.sinc b/python/icicle/Ghidra/Processors/MC6800/data/languages/6x09.sinc new file mode 100644 index 0000000..881a824 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MC6800/data/languages/6x09.sinc @@ -0,0 +1,1397 @@ +# sleigh specification file for Motorola 6809/Hitachi 6309 + +define endian=big; +define alignment=1; + +@define SWI3_VECTOR "0xFFF2" +@define SWI2_VECTOR "0xFFF4" +@define FIRQ_VECTOR "0xFFF6" +@define IRQ_VECTOR "0xFFF8" +@define SWI_VECTOR "0xFFFA" +@define NMI_VECTOR "0xFFFC" +@define RST_VECTOR "0xFFFE" + +define space RAM type=ram_space size=2 default; +define space register type=register_space size=1; + +@ifdef H6309 +# 8-bit registers A, B, E, F, MD +define register offset=0 size=1 [ A B E F MD ]; +# 16-bit registers D, W +define register offset=0 size=2 [ D W ]; +# 16-bit register V +define register offset=12 size=2 [ V ]; +# 32-bit register Q +define register offset=0 size=4 [ Q ]; +@else +# 8-bit registers A, B +define register offset=0 size=1 [ A B ]; +# 16-bit register D +define register offset=0 size=2 [ D ]; +@endif + +# 8-bit condition code register, direct page register +define register offset=8 size=1 [ CC DP ]; +# 16-bit registers: +# PC: Program counter +# S: Stack pointer +# U: alternate stack pointer/index register +# X,Y: index register +define register offset=16 size=2 [ PC X Y U S ]; + +# Pseudo registers used for EXG instruction. +define register offset=32 size=2 [ exg16_r0 exg16_r1 ]; +define register offset=32 size=1 [ exg8h_r0 exg8l_r0 exg8h_r1 exg8l_r1 ]; + +# define status bits: (See also 8051/z80). +@define C "CC[0,1]" # C: Carry (or borrow) flag +@define V "CC[1,1]" # V: Overflow flag +@define Z "CC[2,1]" # Z: Zero result +@define N "CC[3,1]" # N: Negative result (twos complement) +@define I "CC[4,1]" # I: IRQ interrupt masked +@define H "CC[5,1]" # H: Half carry flag +@define F "CC[6,1]" # F: FIRQ interrupt masked +@define E "CC[7,1]" # E: Entire register state stacked + +define token opbyte (8) + op = (0,7) + op45 = (4,5) + op47 = (4,7) +; + +define token data8 (8) + imm8 = (0,7) + simm8 = (0,7) signed + simm5 = (0,4) signed + idxMode = (0,4) + noOffset5 = (7,7) + idxReg = (5,6) + imm80 = (0,0) + imm81 = (1,1) + imm82 = (2,2) + imm83 = (3,3) + imm84 = (4,4) + imm85 = (5,5) + imm86 = (6,6) + imm87 = (7,7) + reg0_exg = (4,7) + reg1_exg = (0,3) +; + +define token data (16) + imm16 = (0,15) + simm16 = (0,15) signed +; + +attach variables [ idxReg ] [ X Y U S ]; + +EA: simm5,idxReg is simm5 & idxReg & noOffset5=0 +{ + local offs:1 = simm5; + local addr:2 = idxReg + sext(offs); + export addr; +} +EA: ","^idxReg is idxReg & noOffset5=1 & idxMode=0b00100 # no offset +{ + local addr:2 = idxReg; + export addr; +} +EA: simm8,idxReg is idxReg & noOffset5=1 & idxMode=0b01000; simm8 # 8-bit offset +{ + local addr:2 = idxReg + simm8; + export addr; +} +EA: simm16,idxReg is idxReg & noOffset5=1 & idxMode=0b01001; simm16 # 16-bit offset +{ + local addr:2 = idxReg + simm16; + export addr; +} + +@ifdef H6309 +EA: ","^W is idxReg=0b00 & noOffset5=1 & idxMode=0b01111 & W # no offset +{ + local addr:2 = W; + export addr; +} +EA: simm16,W is idxReg=0b01 & noOffset5=1 & idxMode=0b01111; simm16 & W # 16-bit offset +{ + local addr:2 = W + simm16; + export addr; +} +@endif # H6309 + +EA: A,idxReg is idxReg & noOffset5=1 & idxMode=0b00110 & A # A,R +{ + local addr:2 = idxReg + sext(A); + export addr; +} +EA: B,idxReg is idxReg & noOffset5=1 & idxMode=0b00101 & B # B,R +{ + local addr:2 = idxReg + sext(B); + export addr; +} +EA: D,idxReg is idxReg & noOffset5=1 & idxMode=0b01011 & D # D,R +{ + local addr:2 = idxReg + D; + export addr; +} + +@ifdef H6309 +EA: E,idxReg is idxReg & noOffset5=1 & idxMode=0b00111 & E # E,R +{ + local addr:2 = idxReg + sext(E); + export addr; +} +EA: F,idxReg is idxReg & noOffset5=1 & idxMode=0b01010 & F # F,R +{ + local addr:2 = idxReg + sext(F); + export addr; +} +EA: W,idxReg is idxReg & noOffset5=1 & idxMode=0b01110 & W # W,R +{ + local addr:2 = idxReg + W; + export addr; +} +@endif # H6309 + + +EA: ","^idxReg^"+" is idxReg & noOffset5=1 & idxMode=0b00000 # ,R+ +{ + addr:2 = idxReg; + idxReg = idxReg + 1; + export addr; +} +EA: ","^idxReg^"++" is idxReg & noOffset5=1 & idxMode=0b00001 # ,R++ +{ + local addr:2 = idxReg; + idxReg = idxReg + 2; + export addr; +} +EA: ",-"^idxReg is idxReg & noOffset5=1 & idxMode=0b00010 # ,-R +{ + idxReg = idxReg - 1; + local addr:2 = idxReg; + export addr; +} +EA: ",--"^idxReg is idxReg & noOffset5=1 & idxMode=0b00011 # ,--R +{ + idxReg = idxReg - 2; + local addr:2 = idxReg; + export addr; +} + +@ifdef H6309 +EA: ","^W^"++" is idxReg=0b10 & noOffset5=1 & idxMode=0b01111 & W # ,W++ +{ + local addr:2 = W; + W = W + 2; + export addr; +} +EA: ",--"^W is idxReg=0b11 & noOffset5=1 & idxMode=0b01111 & W # ,--W +{ + W = W - 2; + local addr:2 = W; + export addr; +} +@endif # H6309 + +EA: addr,"PCR" is noOffset5=1 & idxMode=0b01100; simm8 [ addr = inst_next + simm8; ] +{ + export *[const]:2 addr; +} +EA: addr,"PCR" is noOffset5=1 & idxMode=0b01101; simm16 [ addr = inst_next + simm16; ] +{ + export *[const]:2 addr; +} +EA: "[,"idxReg"]" is idxReg & noOffset5=1 & idxMode=0b10100 +{ + local addr:2 = *:2 idxReg; + export addr; +} +EA: "["simm8,idxReg"]" is idxReg & noOffset5=1 & idxMode=0b11000; simm8 +{ + local offs:1 = simm8; + local addr:2 = idxReg + sext(offs); + addr = *:2 addr; + export addr; +} +EA: "["simm16,idxReg"]" is idxReg & noOffset5=1 & idxMode=0b11001; simm16 +{ + local addr:2 = idxReg + simm16; + addr = *:2 addr; + export addr; +} + +@ifdef H6309 +EA: "[,"W"]" is idxReg=0b00 & noOffset5=1 & idxMode=0b10000 & W +{ + local addr:2 = *:2 W; + export addr; +} +EA: "["simm16,W"]" is idxReg=0b01 & noOffset5=1 & idxMode=0b10000; simm16 & W +{ + local addr:2 = W + simm16; + addr = *:2 addr; + export addr; +} +@endif # H6309 + +EA: "["^A,idxReg"]" is A & idxReg & noOffset5=1 & idxMode=0b10110 +{ + local addr:2 = idxReg + sext(A); + addr = *:2 addr; + export addr; +} +EA: "["^B,idxReg"]" is B & idxReg & noOffset5=1 & idxMode=0b10101 +{ + local addr:2 = idxReg + sext(B); + addr = *:2 addr; + export addr; +} +EA: "["^D,idxReg"]" is D & idxReg & noOffset5=1 & idxMode=0b11011 +{ + local addr:2 = idxReg + D; + addr = *:2 addr; + export addr; +} + +@ifdef H6309 +EA: "["^E,idxReg"]" is E & idxReg & noOffset5=1 & idxMode=0b10111 +{ + local addr:2 = idxReg + sext(E); + addr = *:2 addr; + export addr; +} +EA: "["^F,idxReg"]" is F & idxReg & noOffset5=1 & idxMode=0b11010 +{ + local addr:2 = idxReg + sext(F); + addr = *:2 addr; + export addr; +} +EA: "["^W,idxReg"]" is W & idxReg & noOffset5=1 & idxMode=0b11110 +{ + local addr:2 = idxReg + W; + addr = *:2 addr; + export addr; +} +@endif # H6309 + + +EA: "[,"idxReg"++]" is idxReg & noOffset5=1 & idxMode=0b10001 +{ + local addr:2 = idxReg; + addr = *:2 addr; + idxReg = idxReg + 2; + export addr; +} +EA: "[,--"idxReg"]" is idxReg & noOffset5=1 & idxMode=0b10011 +{ + idxReg = idxReg - 2; + local addr:2 = idxReg; + addr = *:2 addr; + export addr; +} + +@ifdef H6309 +EA: "[,"^W^"++]" is W & idxReg=0b10 & noOffset5=1 & idxMode=0b10000 +{ + local addr:2 = W; + addr = *:2 addr; + W = W + 2; + export addr; +} +EA: "[,--"^W^"]" is W & idxReg=0b11 & noOffset5=1 & idxMode=0b10000 +{ + W = W - 2; + local addr:2 = W; + addr = *:2 addr; + export addr; +} +@endif # H6309 + +EA: "["addr",PCR]" is noOffset5=1 & idxMode=0b11100; simm8 [ addr = inst_next + simm8; ] +{ + local eaddr:2 = inst_next + simm8; + eaddr = *:2 eaddr; + export eaddr; +} +EA: "["addr",PCR]" is noOffset5=1 & idxMode=0b11101; simm16 [ addr = inst_next + simm16; ] +{ + local eaddr:2 = inst_next + simm16; + eaddr = *:2 eaddr; + export eaddr; +} + +EA: "["imm16"]" is noOffset5=1 & idxReg=0b00 & idxMode=0b11111; imm16 +{ + local eaddr:2 = imm16; + eaddr = *:2 eaddr; + export eaddr; +} + +################################################################ +# Constructors +################################################################ + +PAGE2: is op=0x10 { } # PAGE2 opcode prefix (0x10) +PAGE3: is op=0x11 { } # PAGE3 opcode prefix (0x11) + +IMMED1: "#"imm8 is imm8 { export *[const]:1 imm8; } + +REL: addr is simm8 [ addr = inst_next + simm8; ] { export *:2 addr; } +REL2: addr is simm16 [ addr = inst_next + simm16; ] { export *:2 addr; } + +# 1-byte operand, immediate/direct/indexed/extended addressing mode +OP1: "#"imm8 is op45=0; imm8 +{ + export *[const]:1 imm8; +} +OP1: "<"imm8 is (op47=0 | op47=9 | op47=0xD); imm8 +{ + local tmp:2 = (zext(DP) << 8) + imm8; + export *:1 tmp; +} +OP1: EA is op45=2; EA +{ + local tmp:2 = EA; + export *:1 tmp; +} +OP1: imm16 is op45=3; imm16 +{ + export *:1 imm16; +} + +# 2-byte operand, direct/indexed/extended addressing mode +OP2: "#"imm16 is (op47=8 | op47=0xC); imm16 +{ + export *[const]:2 imm16; +} + +OP2: "<"imm8 is (op47=0 | op47=9 | op47=0xD); imm8 +{ + local tmp:2 = (zext(DP) << 8) + imm8; + export *:2 tmp; +} +OP2: EA is (op47=3 | op47=6 | op47=0xA | op47=0xE); EA +{ + local tmp:2 = EA; + export *:2 tmp; +} +OP2: imm16 is (op47=7 | op47=0xB | op47=0xF); imm16 +{ + export *:2 imm16; +} + +#JMP and JSR treat the direct/indexed/extended address modes differently +OP2J: "<"imm8 is (op47=0 | op47=9); imm8 +{ + local tmp:2 = (zext(DP) << 8) + imm8; + export tmp; +} +OP2J: EA is (op47=6 | op47=0xA); EA +{ + export EA; +} +OP2J: imm16 is (op47=7 | op47=0xB ); imm16 +{ + export *[const]:2 imm16; +} + +################################################################ +# Macros +################################################################ + +macro setNZFlags(result) +{ + $(Z) = (result == 0); + $(N) = (result s< 0); +} + +macro setHFlag(reg, op) +{ + local mask = 0x0F; # Low nibble mask + + $(H) = (((reg & mask) + (op & mask)) >> 4) & 1; +} + +# Negate twos complement value in op. +# P-code INT_2COMP. +macro negate(op) +{ + $(V) = (op == 0x80); + $(C) = (op != 0); + op = -op; + setNZFlags(op); +} + +# Logical complement of op. (0 => 1; 1 => 0) +# P-code INT_NEGATE. +macro complement(op) +{ + $(V) = 0; + $(C) = 1; + A = ~A; + setNZFlags(op); +} + +macro logicalShiftRight(op) +{ + $(C) = op & 1; + op = op >> 1; + $(Z) = (op == 0); + $(N) = 0; +} + +macro rotateRightWithCarry(op) +{ + local carryOut = $(C) << 7; + $(C) = op & 1; + op = (op s>> 1) | carryOut; + setNZFlags(op); +} + +macro rotateLeftWithCarry(op) +{ + local carryIn = $(C); + $(C) = op >> 7; + op = (op << 1) | carryIn; + setNZFlags(op); +} + +# Signed shift right. +# P-code INT_SRIGHT. +macro arithmeticShiftRight(op) +{ + $(C) = op & 1; + op = (op s>> 1); + setNZFlags(op); +} + +macro logicalShiftLeft(op) +{ + $(C) = (op >> 7); + op = op << 1; + $(Z) = (op == 0); + $(N) = (op >> 7); +} + +macro increment(op) +{ + $(V) = (op == 0x7F); + op = op + 1; + setNZFlags(op); +} + +macro decrement(op) +{ + $(V) = (op == 0x80); + op = op - 1; + setNZFlags(op); +} + +macro test(op) +{ + $(V) = 0; + setNZFlags(op); +} + +macro clear(op) +{ + $(V) = 0; + op = 0; + $(Z) = 1; + $(N) = 0; +} + +macro addition(reg, op) +{ + $(C) = carry(reg, op); + $(V) = scarry(reg, op); + + reg = reg + op; + + setNZFlags(reg); +} + +macro additionWithCarry(reg, op) +{ + local carryIn = zext($(C)); + local mask = 0x0F; # Low nibble mask + local tmpResult = reg + op; + + $(H) = (((reg & mask) + (op & mask) + carryIn) >> 4) & 1; + $(C) = carry(reg, op) || carry(tmpResult, carryIn); + $(V) = scarry(reg, op) ^^ scarry(tmpResult, carryIn); + + reg = tmpResult + carryIn; + + setNZFlags(reg); +} + +macro subtraction(reg, op) +{ + $(V) = sborrow(reg, op); + reg = reg - op; + setNZFlags(reg); + $(C) = (reg < op); +} + +macro subtractionWithCarry(reg, op) +{ + local carryIn = zext($(C)); + local tmpResult = reg - op; + + $(C) = (reg < op) || (tmpResult < carryIn); + $(V) = sborrow(reg, op) ^^ sborrow(tmpResult, carryIn); + + reg = tmpResult - carryIn; + + setNZFlags(reg); +} + +macro compare(reg, op) +{ + $(V) = sborrow(reg, op); + local tmp = reg - op; + setNZFlags(tmp); + $(C) = (tmp < op); +} + +macro logicalAnd(reg, op) +{ + reg = reg & op; + setNZFlags(reg); + $(V) = 0; +} + +macro logicalOr(reg, op) +{ + reg = reg | op; + setNZFlags(reg); + $(V) = 0; +} + +macro logicalExclusiveOr(reg, op) +{ + reg = reg ^ op; + setNZFlags(reg); + $(V) = 0; +} + +macro bitTest(reg, op) +{ + local tmp = reg & op; + setNZFlags(tmp); + $(V) = 0; +} + +macro loadRegister(reg, op) +{ + reg = op; + setNZFlags(reg); + $(V) = 0; +} + +macro storeRegister(reg, op) +{ + op = reg; + setNZFlags(reg); + $(V) = 0; +} + +# Push 1 byte operand op1 +macro Push1(reg, op) +{ + reg = reg - 1; + *:1 reg = op; +} + +# Push 2 byte operand op2 +macro Push2(reg, op) +{ + reg = reg - 1; + *:2 reg = op; + reg = reg - 1; +} + +# Pull 1 byte operand op1 +macro Pull1(reg, op) +{ + op = *:1 reg; + reg = reg + 1; +} + +# Pull 2 byte operand op2 +macro Pull2(reg, op) +{ + reg = reg + 1; + op = *:2 reg; + reg = reg + 1; +} + +macro PushUYXDpD() +{ + Push2(S, U); + Push2(S, Y); + Push2(S, X); + Push1(S, DP); + Push2(S, D); +} + +macro PullDDpXYU() +{ + Pull2(S, D); + Pull1(S, DP); + Pull2(S, X); + Pull2(S, Y); + Pull2(S, U); +} + +macro PushEntireState() +{ + local tmp:2 = inst_next; + + $(E) = 1; + Push2(S, tmp); # return PC address + PushUYXDpD(); + Push1(S, CC); +} + +################################################################ +# Instructions +################################################################ + +################################################################ +# Opcode 0x00 - 0x0F, relative addressing +# Opcode 0x40 - 0x4F, register A addressing +# Opcode 0x50 - 0x5F, register B addressing +# Opcode 0x60 - 0x6F, indexed addressing +# Opcode 0x70 - 0x7F, extended addressing +################################################################ + +:NEGA is op=0x40 +{ + negate(A); +} + +:NEGB is op=0x50 +{ + negate(B); +} + +:NEG OP1 is (op=0x00 | op=0x60 | op=0x70) ... & OP1 +{ + negate(OP1); +} + +:COMA is op=0x43 +{ + complement(A); +} + +:COMB is op=0x53 +{ + complement(B); +} + +:COM OP1 is (op=0x03 | op=0x63 | op=0x73) ... & OP1 +{ + complement(OP1); +} + +:LSRA is op=0x44 +{ + logicalShiftRight(A); +} + +:LSRB is op=0x54 +{ + logicalShiftRight(B); +} + +:LSR OP1 is (op=0x04 | op=0x64 | op=0x74) ... & OP1 +{ + logicalShiftRight(OP1); +} + +:RORA is op=0x46 +{ + rotateRightWithCarry(A); +} + +:RORB is op=0x56 +{ + rotateRightWithCarry(B); +} + +:ROR OP1 is (op=0x06 | op=0x66 | op=0x76) ... & OP1 +{ + rotateRightWithCarry(OP1); +} + +:ASRA is op=0x47 +{ + arithmeticShiftRight(A); +} + +:ASRB is op=0x57 +{ + arithmeticShiftRight(B); +} + +:ASR OP1 is (op=0x07 | op=0x67 | op=0x77) ... & OP1 +{ + arithmeticShiftRight(OP1); +} + +:LSLA is op=0x48 +{ + logicalShiftLeft(A); +} + +:LSLB is op=0x58 +{ + logicalShiftLeft(B); +} + +:LSL OP1 is (op=0x08 | op=0x68 | op=0x78) ... & OP1 +{ + logicalShiftLeft(OP1); +} + +:ROLA is op=0x49 +{ + rotateLeftWithCarry(A); +} + +:ROLB is op=0x59 +{ + rotateLeftWithCarry(B); +} + +:ROL OP1 is (op=0x09 | op=0x69 | op=0x79) ... & OP1 +{ + rotateLeftWithCarry(OP1); +} + +:DECA is op=0x4A +{ + decrement(A); +} + +:DECB is op=0x5A +{ + decrement(B); +} + +:DEC OP1 is (op=0x0A | op=0x6A | op=0x7A) ... & OP1 +{ + decrement(OP1); +} + +:INCA is op=0x4C +{ + increment(A); +} + +:INCB is op=0x5C +{ + increment(B); +} + +:INC OP1 is (op=0x0C | op=0x6C | op=0x7C) ... & OP1 +{ + increment(OP1); +} + +:TSTA is op=0x4D +{ + test(A); +} + +:TSTB is op=0x5D +{ + test(B); +} + +:TST OP1 is (op=0x0D | op=0x6D | op=0x7D) ... & OP1 +{ + test(OP1); +} + +:JMP OP2J is (op=0x0E | op=0x6E | op=0x7E) ... & OP2J +{ + local target = OP2J; + goto [target]; +} + +:CLRA is op=0x4F +{ + clear(A); +} + +:CLRB is op=0x5F +{ + clear(B); +} + +:CLR OP1 is (op=0x0F | op=0x6F | op=0x7F) ... & OP1 +{ + clear(OP1); +} + +################################################################ +# Opcode 0x10 - 0x1F, misc. addressing +################################################################ + +:NOP is op=0x12 +{ +} + +:SYNC is op=0x13 +{ +} + +:LBRA REL2 is op=0x16; REL2 +{ + goto REL2; +} + +:LBSR REL2 is op=0x17; REL2 +{ + local tmp:2 = inst_next; + Push2(S, tmp); + call REL2; +} + +:DAA is op=0x19 +{ + local highA:1 = A >> 4; + local lowA:1 = A & 0x0F; + local cc1 = ($(C) == 1 | highA > 9 | (highA > 8) & (lowA > 9)); + local cc2 = ($(H) == 1 | lowA > 9); + + if ( cc1 & cc2 ) + goto ; + if ( cc1 ) + goto ; + if ( cc2 ) + goto ; + goto ; + + + $(C) = carry(A, 0x66); + A = A + 0x66; + goto ; + + $(C) = carry(A, 0x60); + A = A + 0x60; + goto ; + + $(C) = carry(A, 0x06); + A = A + 0x06; + goto ; + + + setNZFlags(A); +} + +:ORCC IMMED1 is op=0x1A; IMMED1 +{ + CC = CC | IMMED1; +} + +:ANDCC IMMED1 is op=0x1C; IMMED1 +{ + CC = CC & IMMED1; +} + +:SEX is op=0x1D +{ + D = sext(B); +} + +################################################################ +# Opcode 0x20 - 0x2F, relative addressing +################################################################ + +:BRA REL is op=0x20; REL +{ + goto REL; +} + +:BRN REL is op=0x21; REL +{ +} + +:BHI REL is op=0x22; REL +{ + local tmp = $(C) + $(Z); + if (tmp == 0) goto REL; +} + +:BLS REL is op=0x23; REL +{ + local tmp = $(C) + $(Z); + if (tmp) goto REL; +} + +#:BHS REL is op=0x24; REL # See BCC + +:BCC REL is op=0x24; REL +{ + if ($(C) == 0) goto REL; +} + +#:BLO REL is op=0x25; REL # see BCS + +:BCS REL is op=0x25; REL +{ + if ($(C)) goto REL; +} + +:BNE REL is op=0x26; REL +{ + if ($(Z) == 0) goto REL; +} + +:BEQ REL is op=0x27; REL +{ + if ($(Z)) goto REL; +} + +:BVC REL is op=0x28; REL +{ + if ($(V) == 0) goto REL; +} + +:BVS REL is op=0x29; REL +{ + if ($(V)) goto REL; +} + +:BPL REL is op=0x2A; REL +{ + if ($(N) == 0) goto REL; +} + +:BMI REL is op=0x2B; REL +{ + if ($(N)) goto REL; +} + +:BGE REL is op=0x2C; REL +{ + if ($(N) == $(V)) goto REL; +} + +:BLT REL is op=0x2D; REL +{ + local tmp = $(C) ^ $(Z); + if (tmp) goto REL; +} + +:BGT REL is op=0x2E; REL +{ + if (($(N) == $(V)) & $(C)) goto REL; +} + +:BLE REL is op=0x2F; REL +{ + local tmp = $(N) ^ $(V); + if (tmp | $(Z)) goto REL; +} + +################################################################ +# Opcode 0x30 - 0x3F, misc. addressing +################################################################ + +:LEAX EA is op=0x30; EA +{ + X = EA; +} + +:LEAY EA is op=0x31; EA +{ + Y = EA; +} + +:LEAS EA is op=0x32; EA +{ + S = EA; +} + +:LEAU EA is op=0x33; EA +{ + U = EA; +} + +:RTS is op=0x39 +{ + local addr:2; + Pull2(S, addr); + return [addr]; +} + +:ABX is op=0x3A +{ + X = X + zext(B); +} + +:RTI is op=0x3B +{ + local addr:2; + Pull1(S, CC); + if ($(E)==0) goto ; + PullDDpXYU(); + + Pull2(S, addr); + return [addr]; +} + +:CWAI IMMED1 is op=0x3C; IMMED1 +{ + CC = CC & IMMED1; + PushEntireState(); +} + +:MUL is op=0x3D +{ + D = zext(A) * zext(B); + $(Z) = (D == 0); + $(C) = B >> 7; +} + +:SWI is op=0x3F +{ + PushEntireState(); + $(I) = 1; + $(F) = 1; + tmp:2 = $(SWI_VECTOR); + call [tmp]; +} + +################################################################ +# Opcode 0x80 - 0x8F, immediate addressing +# Opcode 0x90 - 0x9F, direct addressing +# Opcode 0xA0 - 0xAF, indexed addressing +# Opcode 0xB0 - 0xBF, extended addressing +# Opcode 0xC0 - 0xCF, immediate addressing +# Opcode 0xD0 - 0xDF, direct addressing +# Opcode 0xE0 - 0xEF, indexed addressing +# Opcode 0xF0 - 0xFF, extended addressing +################################################################ + +:SUBA OP1 is (op=0x80 | op=0x90 | op=0xA0 | op=0xB0) ... & OP1 +{ + subtraction(A, OP1); +} + +:SUBB OP1 is (op=0xC0 | op=0xD0 | op=0xE0 | op=0xF0) ... & OP1 +{ + subtraction(B, OP1); +} + +:CMPA OP1 is (op=0x81 | op=0x91 | op=0xA1 | op=0xB1) ... & OP1 +{ + compare(A, OP1); +} + +:CMPB OP1 is (op=0xC1 | op=0xD1 | op=0xE1 | op=0xF1) ... & OP1 +{ + compare(B, OP1); +} + +:SBCA OP1 is (op=0x82 | op=0x92 | op=0xA2 | op=0xB2) ... & OP1 +{ + subtractionWithCarry(A, OP1); +} + +:SBCB OP1 is (op=0xC2 | op=0xD2 | op=0xE2 | op=0xF2) ... & OP1 +{ + subtractionWithCarry(B, OP1); +} + +:SUBD OP2 is (op=0x83 | op=0x93 | op=0xA3 | op=0xB3) ... & OP2 +{ + subtraction(D, OP2); +} + +:ADDD OP2 is (op=0xC3 | op=0xD3 | op=0xE3 | op=0xF3) ... & OP2 +{ + addition(D, OP2); +} + +:ANDA OP1 is (op=0x84 | op=0x94 | op=0xA4 | op=0xB4) ... & OP1 +{ + logicalAnd(A, OP1); +} + +:ANDB OP1 is (op=0xC4 | op=0xD4 | op=0xE4 | op=0xF4) ... & OP1 +{ + logicalAnd(B, OP1); +} + +:BITA OP1 is (op=0x85 | op=0x95 | op=0xA5 | op=0xB5) ... & OP1 +{ + bitTest(A, OP1); +} + +:BITB OP1 is (op=0xC5 | op=0xD5 | op=0xE5 | op=0xF5) ... & OP1 +{ + bitTest(B, OP1); +} + +:LDA OP1 is (op=0x86 | op=0x96 | op=0xA6 | op=0xB6) ... & OP1 +{ + loadRegister(A, OP1); +} + +:LDB OP1 is (op=0xC6 | op=0xD6 | op=0xE6 | op=0xF6) ... & OP1 +{ + loadRegister(B, OP1); +} + +:STA OP1 is (op=0x97 | op=0xA7 | op=0xB7) ... & OP1 +{ + storeRegister(A, OP1); +} + +:STB OP1 is (op=0xD7 | op=0xE7 | op=0xF7) ... & OP1 +{ + storeRegister(B, OP1); +} + +:EORA OP1 is (op=0x88 | op=0x98 | op=0xA8 | op=0xB8) ... & OP1 +{ + logicalExclusiveOr(A, OP1); +} + +:EORB OP1 is (op=0xC8 | op=0xD8 | op=0xE8 | op=0xF8) ... & OP1 +{ + logicalExclusiveOr(B, OP1); +} + +:ADCA OP1 is (op=0x89 | op=0x99 | op=0xA9 | op=0xB9) ... & OP1 +{ + additionWithCarry(A, OP1); +} + +:ADCB OP1 is (op=0xC9 | op=0xD9 | op=0xE9 | op=0xF9) ... & OP1 +{ + additionWithCarry(B, OP1); +} + +:ORA OP1 is (op=0x8A | op=0x9A | op=0xAA | op=0xBA) ... & OP1 +{ + logicalOr(A, OP1); +} + +:ORB OP1 is (op=0xCA | op=0xDA | op=0xEA | op=0xFA) ... & OP1 +{ + logicalOr(B, OP1); +} + +:ADDA OP1 is (op=0x8B | op=0x9B | op=0xAB | op=0xBB) ... & OP1 +{ + setHFlag(A, OP1); + addition(A, OP1); +} + +:ADDB OP1 is (op=0xCB | op=0xDB | op=0xEB | op=0xFB) ... & OP1 +{ + setHFlag(A, OP1); + addition(B, OP1); +} + +:CMPX OP2 is (op=0x8C | op=0x9C | op=0xAC | op=0xBC) ... & OP2 +{ + compare(X, OP2); +} + +:LDD OP2 is (op=0xCC | op=0xDC | op=0xEC | op=0xFC) ... & OP2 +{ + loadRegister(D, OP2); +} + +:BSR REL is op=0x8D; REL +{ + local addr:2 = inst_next; + Push2(S, addr); + call REL; +} + +:JSR OP2J is (op=0x9D | op=0xAD | op=0xBD) ... & OP2J +{ + local addr:2 = inst_next; + Push2(S, addr); + local target = OP2J; + call [target]; +} + +:STD OP2 is (op=0xDD | op=0xED | op=0xFD) ... & OP2 +{ + storeRegister(D, OP2); +} + +:LDX OP2 is (op=0x8E | op=0x9E | op=0xAE | op=0xBE) ... & OP2 +{ + loadRegister(X, OP2); +} + +:LDU OP2 is (op=0xCE | op=0xDE | op=0xEE | op=0xFE) ... & OP2 +{ + loadRegister(U, OP2); +} + +:STX OP2 is (op=0x9F | op=0xAF | op=0xBF) ... & OP2 +{ + storeRegister(X, OP2); +} + +:STU OP2 is (op=0xDF | op=0xEF | op=0xFF) ... & OP2 +{ + storeRegister(X, OP2); +} + +################################################################ +# Page 2 Opcodes (prefix 0x10) +################################################################ +:LBRN REL2 is PAGE2; op=0x21; REL2 +{ +} + +:LBHI REL2 is PAGE2; op=0x22; REL2 +{ + local tmp = $(C) + $(Z); + if (tmp == 0) goto REL2; +} + +:LBLS REL2 is PAGE2; op=0x23; REL2 +{ + local tmp = $(C) + $(Z); + if (tmp) goto REL2; +} + +:LBCC REL2 is PAGE2; op=0x24; REL2 +{ + if ($(C) == 0) goto REL2; +} + +#:LBLO REL2 is PAGE2; op=0x25; REL2 # see LBCS + +:LBCS REL2 is PAGE2; op=0x25; REL2 +{ + if ($(C)) goto REL2; +} + +:LBNE REL2 is PAGE2; op=0x26; REL2 +{ + if ($(Z) == 0) goto REL2; +} + +:LBEQ REL2 is PAGE2; op=0x27; REL2 +{ + if ($(Z)) goto REL2; +} + +:LBVC REL2 is PAGE2; op=0x28; REL2 +{ + if ($(V) == 0) goto REL2; +} + +:LBVS REL2 is PAGE2; op=0x29; REL2 +{ + if ($(V)) goto REL2; +} + +:LBPL REL2 is PAGE2; op=0x2A; REL2 +{ + if ($(N) == 0) goto REL2; +} + +:LBMI REL2 is PAGE2; op=0x2B; REL2 +{ + if ($(N)) goto REL2; +} + +:LBGE REL2 is PAGE2; op=0x2C; REL2 +{ + if ($(N) == $(V)) goto REL2; +} + +:LBLT REL2 is PAGE2; op=0x2D; REL2 +{ + local tmp = $(C) ^ $(Z); + if (tmp) goto REL2; +} + +:LBGT REL2 is PAGE2; op=0x2E; REL2 +{ + if (($(N) == $(V)) & $(C)) goto REL2; +} + +:LBLE REL2 is PAGE2; op=0x2F; REL2 +{ + local tmp = $(N) ^ $(V); + if (tmp | $(Z)) goto REL2; +} + +:SWI2 is PAGE2; op=0x3F +{ + PushEntireState(); + tmp:2 = $(SWI2_VECTOR); + call [tmp]; +} + +:CMPD OP2 is PAGE2; (op=0x83 | op=0x93 | op=0xA3 | op=0xB3) ... & OP2 +{ + compare(D, OP2); +} + +:CMPY OP2 is PAGE2; (op=0x8C | op=0x9C | op=0xAC | op=0xBC) ... & OP2 +{ + compare(Y, OP2); +} + +:LDY OP2 is PAGE2; (op=0x8E | op=0x9E | op=0xAE | op=0xBE) ... & OP2 +{ + loadRegister(Y, OP2); +} + +:STY OP2 is PAGE2; (op=0x9F | op=0xAF | op=0xBF) ... & OP2 +{ + storeRegister(Y, OP2); +} + +:LDS OP2 is PAGE2; (op=0xCE | op=0xDE | op=0xEE | op=0xFE) ... & OP2 +{ + loadRegister(S, OP2); +} + +:STS OP2 is PAGE2; (op=0xDF | op=0xEF | op=0xFF) ... & OP2 +{ + storeRegister(S, OP2); +} + +################################################################ +# Page 3 Opcodes (prefix 0x11) +################################################################ + +:SWI3 is PAGE3; op=0x3F +{ + PushEntireState(); + tmp:2 = $(SWI3_VECTOR); + call [tmp]; +} + +:CMPU OP2 is PAGE3; (op=0x83 | op=0x93 | op=0xA3 | op=0xB3) ... & OP2 +{ + compare(U, OP2); +} + +:CMPS OP2 is PAGE3; (op=0x8C | op=0x9C | op=0xAC | op=0xBC) ... & OP2 +{ + compare(S, OP2); +} + diff --git a/python/icicle/Ghidra/Processors/MC6800/data/languages/6x09_exg_tfr.sinc b/python/icicle/Ghidra/Processors/MC6800/data/languages/6x09_exg_tfr.sinc new file mode 100644 index 0000000..cebcdd5 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MC6800/data/languages/6x09_exg_tfr.sinc @@ -0,0 +1,170 @@ +# sleigh specification file for Motorola 6809/Hitachi 6309 + +################################################################ +# EXG, TFR helper +################################################################ + +@ifdef H6309 +EXG_r0Tmp: D is reg0_exg=0 & D { exg16_r0 = D; } +EXG_r0Tmp: X is reg0_exg=1 & X { exg16_r0 = X; } +EXG_r0Tmp: Y is reg0_exg=2 & Y { exg16_r0 = Y; } +EXG_r0Tmp: U is reg0_exg=3 & U { exg16_r0 = U; } +EXG_r0Tmp: S is reg0_exg=4 & S { exg16_r0 = S; } +EXG_r0Tmp: PC is reg0_exg=5 & PC { exg16_r0 = inst_next; } +EXG_r0Tmp: W is reg0_exg=6 & W { exg16_r0 = 0x0; } +EXG_r0Tmp: V is reg0_exg=7 & V { exg16_r0 = 0x0; } +EXG_r0Tmp: A is reg0_exg=8 & A { exg8l_r0 = A; exg8h_r0 = A; } +EXG_r0Tmp: B is reg0_exg=9 & B { exg8l_r0 = B; exg8h_r0 = B; } +EXG_r0Tmp: CC is reg0_exg=10 & CC { exg8l_r0 = CC; exg8h_r0 = CC;} +EXG_r0Tmp: DP is reg0_exg=11 & DP { exg8l_r0 = DP; exg8h_r0 = DP;} +EXG_r0Tmp: 0 is reg0_exg=12 { exg16_r0 = 0x0; } +EXG_r0Tmp: 0 is reg0_exg=13 { exg16_r0 = 0x0; } +EXG_r0Tmp: E is reg0_exg=14 & E { exg8l_r0 = E; exg8h_r0 = E; } +EXG_r0Tmp: F is reg0_exg=15 & F { exg8l_r0 = F; exg8h_r0 = F; } + +EXG_r1Tmp: D is reg1_exg=0 & D { exg16_r1 = D; } +EXG_r1Tmp: X is reg1_exg=1 & X { exg16_r1 = X; } +EXG_r1Tmp: Y is reg1_exg=2 & Y { exg16_r1 = Y; } +EXG_r1Tmp: U is reg1_exg=3 & U { exg16_r1 = U; } +EXG_r1Tmp: S is reg1_exg=4 & S { exg16_r1 = S; } +EXG_r1Tmp: PC is reg1_exg=5 & PC { exg16_r1 = inst_next; } +EXG_r1Tmp: W is reg1_exg=6 & W { exg16_r1 = 0x0; } +EXG_r1Tmp: V is reg1_exg=7 & V { exg16_r1 = 0x0; } +EXG_r1Tmp: A is reg1_exg=8 & A { exg8l_r1 = A; exg8h_r1 = A; } +EXG_r1Tmp: B is reg1_exg=9 & B { exg8l_r1 = B; exg8h_r1 = B; } +EXG_r1Tmp: CC is reg1_exg=10 & CC { exg8l_r1 = CC; exg8h_r1 = CC;} +EXG_r1Tmp: DP is reg1_exg=11 & DP { exg8l_r1 = DP; exg8h_r1 = DP;} +EXG_r1Tmp: 0 is reg1_exg=12 { exg16_r1 = 0x0; } +EXG_r1Tmp: 0 is reg1_exg=13 { exg16_r1 = 0x0; } +EXG_r1Tmp: E is reg1_exg=14 & E { exg8l_r1 = E; exg8h_r1 = E; } +EXG_r1Tmp: F is reg1_exg=15 & F { exg8l_r1 = F; exg8h_r1 = F; } + +EXG_r0Set: D is reg0_exg=0 & D { D = exg16_r1; } +EXG_r0Set: X is reg0_exg=1 & X { X = exg16_r1; } +EXG_r0Set: Y is reg0_exg=2 & Y { Y = exg16_r1; } +EXG_r0Set: U is reg0_exg=3 & U { U = exg16_r1; } +EXG_r0Set: S is reg0_exg=4 & S { S = exg16_r1; } +EXG_r0Set: PC is reg0_exg=5 & PC { PC = exg16_r1; } # must GOTO +EXG_r0Set: W is reg0_exg=6 & W { W = exg16_r1; } +EXG_r0Set: V is reg0_exg=7 & V { V = exg16_r1; } +EXG_r0Set: A is reg0_exg=8 & A { A = exg8h_r1; } +EXG_r0Set: B is reg0_exg=9 & B { B = exg8l_r1; } +EXG_r0Set: CC is reg0_exg=10 & CC { CC = exg8l_r1; } +EXG_r0Set: DP is reg0_exg=11 & DP { DP = exg8h_r1; } +EXG_r0Set: 0 is reg0_exg=12 { } +EXG_r0Set: 0 is reg0_exg=13 { } +EXG_r0Set: E is reg0_exg=14 & E { E = exg8h_r1; } +EXG_r0Set: F is reg0_exg=15 & F { F = exg8l_r1; } + +EXG_r1Set: D is reg1_exg=0 & D { D = exg16_r0; } +EXG_r1Set: X is reg1_exg=1 & X { X = exg16_r0; } +EXG_r1Set: Y is reg1_exg=2 & Y { Y = exg16_r0; } +EXG_r1Set: U is reg1_exg=3 & U { U = exg16_r0; } +EXG_r1Set: S is reg1_exg=4 & S { S = exg16_r0; } +EXG_r1Set: PC is reg1_exg=5 & PC { PC = exg16_r0; } # must GOTO +EXG_r1Set: W is reg1_exg=6 & W { W = exg16_r0; } +EXG_r1Set: V is reg1_exg=7 & V { V = exg16_r0; } +EXG_r1Set: A is reg1_exg=8 & A { A = exg8h_r0; } +EXG_r1Set: B is reg1_exg=9 & B { B = exg8l_r0; } +EXG_r1Set: CC is reg1_exg=10 & CC { CC = exg8l_r0; } +EXG_r1Set: DP is reg1_exg=11 & DP { DP = exg8h_r0; } +EXG_r1Set: 0 is reg1_exg=12 { } +EXG_r1Set: 0 is reg1_exg=13 { } +EXG_r1Set: E is reg1_exg=14 & E { E = exg8h_r0; } +EXG_r1Set: F is reg1_exg=15 & F { F = exg8l_r0; } +@endif + +@ifdef M6809 +EXG_r0Tmp: D is reg0_exg=0 & D { exg16_r0 = D; } +EXG_r0Tmp: X is reg0_exg=1 & X { exg16_r0 = X; } +EXG_r0Tmp: Y is reg0_exg=2 & Y { exg16_r0 = Y; } +EXG_r0Tmp: U is reg0_exg=3 & U { exg16_r0 = U; } +EXG_r0Tmp: S is reg0_exg=4 & S { exg16_r0 = S; } +EXG_r0Tmp: PC is reg0_exg=5 & PC { exg16_r0 = inst_next; } +EXG_r0Tmp: "inv" is reg0_exg=6 { exg16_r0 = 0xFFFF; } +EXG_r0Tmp: "inv" is reg0_exg=7 { exg16_r0 = 0xFFFF; } +EXG_r0Tmp: A is reg0_exg=8 & A { exg8l_r0 = A; exg8h_r0 = 0xFF; } +EXG_r0Tmp: B is reg0_exg=9 & B { exg8l_r0 = B; exg8h_r0 = 0xFF; } +EXG_r0Tmp: CC is reg0_exg=10 & CC { exg8l_r0 = CC; exg8h_r0 = CC;} +EXG_r0Tmp: DP is reg0_exg=11 & DP { exg8l_r0 = DP; exg8h_r0 = DP;} +EXG_r0Tmp: "inv" is reg0_exg=12 { exg16_r0 = 0xFFFF; } +EXG_r0Tmp: "inv" is reg0_exg=13 { exg16_r0 = 0xFFFF; } +EXG_r0Tmp: "inv" is reg0_exg=14 { exg16_r0 = 0xFFFF; } +EXG_r0Tmp: "inv" is reg0_exg=15 { exg16_r0 = 0xFFFF; } + +EXG_r1Tmp: D is reg1_exg=0 & D { exg16_r1 = D; } +EXG_r1Tmp: X is reg1_exg=1 & X { exg16_r1 = X; } +EXG_r1Tmp: Y is reg1_exg=2 & Y { exg16_r1 = Y; } +EXG_r1Tmp: U is reg1_exg=3 & U { exg16_r1 = U; } +EXG_r1Tmp: S is reg1_exg=4 & S { exg16_r1 = S; } +EXG_r1Tmp: PC is reg1_exg=5 & PC { exg16_r1 = inst_next; } +EXG_r1Tmp: "inv" is reg1_exg=6 { exg16_r1 = 0xFFFF; } +EXG_r1Tmp: "inv" is reg1_exg=7 { exg16_r1 = 0xFFFF; } +EXG_r1Tmp: A is reg1_exg=8 & A { exg8l_r1 = A; exg8h_r1 = 0xFF; } +EXG_r1Tmp: B is reg1_exg=9 & B { exg8l_r1 = B; exg8h_r1 = 0xFF; } +EXG_r1Tmp: CC is reg1_exg=10 & CC { exg8l_r1 = CC; exg8h_r1 = 0xFF;} +EXG_r1Tmp: DP is reg1_exg=11 & DP { exg8l_r1 = DP; exg8h_r1 = 0xFF;} +EXG_r1Tmp: "inv" is reg1_exg=12 { exg16_r1 = 0xFFFF; } +EXG_r1Tmp: "inv" is reg1_exg=13 { exg16_r1 = 0xFFFF; } +EXG_r1Tmp: "inv" is reg1_exg=14 { exg16_r1 = 0xFFFF; } +EXG_r1Tmp: "inv" is reg1_exg=15 { exg16_r1 = 0xFFFF; } + +EXG_r0Set: D is reg0_exg=0 & D { D = exg16_r1; } +EXG_r0Set: X is reg0_exg=1 & X { X = exg16_r1; } +EXG_r0Set: Y is reg0_exg=2 & Y { Y = exg16_r1; } +EXG_r0Set: U is reg0_exg=3 & U { U = exg16_r1; } +EXG_r0Set: S is reg0_exg=4 & S { S = exg16_r1; } +EXG_r0Set: PC is reg0_exg=5 & PC { PC = exg16_r1; } # must GOTO +EXG_r0Set: "inv" is reg0_exg=6 { } +EXG_r0Set: "inv" is reg0_exg=7 { } +EXG_r0Set: A is reg0_exg=8 & A { A = exg8l_r1; } +EXG_r0Set: B is reg0_exg=9 & B { B = exg8l_r1; } +EXG_r0Set: CC is reg0_exg=10 & CC { CC = exg8l_r1; } +EXG_r0Set: DP is reg0_exg=11 & DP { DP = exg8l_r1; } +EXG_r0Set: "inv" is reg0_exg=12 { } +EXG_r0Set: "inv" is reg0_exg=13 { } +EXG_r0Set: "inv" is reg0_exg=14 { } +EXG_r0Set: "inv" is reg0_exg=15 { } + +EXG_r1Set: D is reg1_exg=0 & D { D = exg16_r0; } # Must to r1 set first so A,D = A,B switch +EXG_r1Set: X is reg1_exg=1 & X { X = exg16_r0; } +EXG_r1Set: Y is reg1_exg=2 & Y { Y = exg16_r0; } +EXG_r1Set: U is reg1_exg=3 & U { U = exg16_r0; } +EXG_r1Set: S is reg1_exg=4 & S { S = exg16_r0; } +EXG_r1Set: PC is reg1_exg=5 & PC { PC = exg16_r0; } # must GOTO +EXG_r1Set: "inv" is reg1_exg=6 { } +EXG_r1Set: "inv" is reg1_exg=7 { } +EXG_r1Set: A is reg1_exg=8 & A { A = exg8l_r0; } +EXG_r1Set: B is reg1_exg=9 & B { B = exg8l_r0; } +EXG_r1Set: CC is reg1_exg=10 & CC { CC = exg8l_r0; } +EXG_r1Set: DP is reg1_exg=11 & DP { DP = exg8l_r0; } +EXG_r1Set: "inv" is reg1_exg=12 { } +EXG_r1Set: "inv" is reg1_exg=13 { } +EXG_r1Set: "inv" is reg1_exg=14 { } +EXG_r1Set: "inv" is reg1_exg=15 { } +@endif + +EXG_GOTO: is reg0_exg=5 | reg1_exg=5 { goto [PC]; } +EXG_GOTO: is reg0_exg & reg1_exg { } # PC not set + +TFR_GOTO: is reg1_exg=5 { goto [PC]; } +TFR_GOTO: is reg1_exg { } # PC not set + +# Exchange two registers +:EXG EXG_r0Set,EXG_r1Set is op=0x1E; EXG_r0Set & EXG_r1Set & EXG_r0Tmp & EXG_r1Tmp & EXG_GOTO +{ + build EXG_r0Tmp; + build EXG_r1Tmp; + build EXG_r1Set; + build EXG_r0Set; + build EXG_GOTO; +} + +# Transfer register to another register +:TFR EXG_r0Tmp,EXG_r1Set is op=0x1F; EXG_r1Set & EXG_r0Tmp & TFR_GOTO +{ + build EXG_r0Tmp; + build EXG_r1Set; + build TFR_GOTO; +} + diff --git a/python/icicle/Ghidra/Processors/MC6800/data/languages/6x09_pull.sinc b/python/icicle/Ghidra/Processors/MC6800/data/languages/6x09_pull.sinc new file mode 100644 index 0000000..21a4a50 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MC6800/data/languages/6x09_pull.sinc @@ -0,0 +1,48 @@ +# sleigh specification file for Motorola 6809/Hitachi 6309 + +################################################################# +# PULS helper +################################################################ + +puls0: CC is CC & imm80=1 { Pull1(S, CC); } +puls0: is imm80=0 { } +puls1: puls0" "A is A & imm81=1 & puls0 { Pull1(S, A); } +puls1: puls0 is imm81=0 & puls0 { } +puls2: puls1" "B is B & imm82=1 & puls1 { Pull1(S, B); } +puls2: puls1 is imm82=0 & puls1 { } +puls3: puls2" "DP is DP & imm83=1 & puls2 { Pull1(S, DP); } +puls3: puls2 is imm83=0 & puls2 { } +puls4: puls3" "X is X & imm84=1 & puls3 { Pull2(S, X); } +puls4: puls3 is imm84=0 & puls3 { } +puls5: puls4" "Y is Y & imm85=1 & puls4 { Pull2(S, Y); } +puls5: puls4 is imm85=0 & puls4 { } +puls6: puls5" "U is U & imm86=1 & puls5 { Pull2(S, U); } +puls6: puls5 is imm86=0 & puls5 { } +puls7: puls6" "PC is PC & imm87=1 & puls6 { local t:2 = 0; Pull2(S, t); goto [t]; } +puls7: puls6 is imm87=0 & puls6 { } + +:PULS puls7 is op=0x35; puls7 { } + +################################################################ +# PULU helper +################################################################ + +pulu0: CC is CC & imm80=1 { Pull1(U, CC); } +pulu0: is imm80=0 { } +pulu1: pulu0" "A is A & imm81=1 & pulu0 { Pull1(U, A); } +pulu1: pulu0 is imm81=0 & pulu0 { } +pulu2: pulu1" "B is B & imm82=1 & pulu1 { Pull1(U, B); } +pulu2: pulu1 is imm82=0 & pulu1 { } +pulu3: pulu2" "DP is DP & imm83=1 & pulu2 { Pull1(U, DP); } +pulu3: pulu2 is imm83=0 & pulu2 { } +pulu4: pulu3" "X is X & imm84=1 & pulu3 { Pull2(U, X); } +pulu4: pulu3 is imm84=0 & pulu3 { } +pulu5: pulu4" "Y is Y & imm85=1 & pulu4 { Pull2(U, Y); } +pulu5: pulu4 is imm85=0 & pulu4 { } +pulu6: pulu5" "S is S & imm86=1 & pulu5 { Pull2(U, S); } +pulu6: pulu5 is imm86=0 & pulu5 { } +pulu7: pulu6" "PC is PC & imm87=1 & pulu6 { local t:2 = 0; Pull2(U, t); goto [t]; } +pulu7: pulu6 is imm87=0 & pulu6 { } + +:PULU pulu7 is op=0x37; pulu7 { } + diff --git a/python/icicle/Ghidra/Processors/MC6800/data/languages/6x09_push.sinc b/python/icicle/Ghidra/Processors/MC6800/data/languages/6x09_push.sinc new file mode 100644 index 0000000..4c1a3d1 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MC6800/data/languages/6x09_push.sinc @@ -0,0 +1,47 @@ +# sleigh specification file for Motorola 6809/Hitachi 6309 + +################################################################ +# PSHS helper +################################################################ + +pshs0: CC is CC & imm80=1 { Push1(S, CC); } +pshs0: is imm80=0 { } +pshs1: pshs0" "A is A & imm81=1 & pshs0 { Push1(S, A); } +pshs1: pshs0 is imm81=0 & pshs0 { } +pshs2: pshs1" "B is B & imm82=1 & pshs1 { Push1(S, B); } +pshs2: pshs1 is imm82=0 & pshs1 { } +pshs3: pshs2" "DP is DP & imm83=1 & pshs2 { Push1(S, DP); } +pshs3: pshs2 is imm83=0 & pshs2 { } +pshs4: pshs3" "X is X & imm84=1 & pshs3 { Push2(S, X); } +pshs4: pshs3 is imm84=0 & pshs3 { } +pshs5: pshs4" "Y is Y & imm85=1 & pshs4 { Push2(S, Y); } +pshs5: pshs4 is imm85=0 & pshs4 { } +pshs6: pshs5" "U is U & imm86=1 & pshs5 { Push2(S, U); } +pshs6: pshs5 is imm86=0 & pshs5 { } +pshs7: pshs6" "PC is PC & imm87=1 & pshs6 { local t:2 = inst_next; Push2(S, t); } +pshs7: pshs6 is imm87=0 & pshs6 { } + +:PSHS pshs7 is op=0x34; pshs7 { } +################################################################ +# PSHU helper +################################################################ + +pshu0: CC is CC & imm80=1 { Push1(S, CC); } +pshu0: is imm80=0 { } +pshu1: pshu0" "A is A & imm81=1 & pshu0 { Push1(S, A); } +pshu1: pshu0 is imm81=0 & pshu0 { } +pshu2: pshu1" "B is B & imm82=1 & pshu1 { Push1(S, B); } +pshu2: pshu1 is imm82=0 & pshu1 { } +pshu3: pshu2" "DP is DP & imm83=1 & pshu2 { Push1(U, DP); } +pshu3: pshu2 is imm83=0 & pshu2 { } +pshu4: pshu3" "X is X & imm84=1 & pshu3 { Push2(U, X); } +pshu4: pshu3 is imm84=0 & pshu3 { } +pshu5: pshu4" "Y is Y & imm85=1 & pshu4 { Push2(U, Y); } +pshu5: pshu4 is imm85=0 & pshu4 { } +pshu6: pshu5" "S is S & imm86=1 & pshu5 { Push2(U, S); } +pshu6: pshu5 is imm86=0 & pshu5 { } +pshu7: pshu6" "PC is PC & imm87=1 & pshu6 { local t:2 = inst_next; Push2(U, t); } +pshu7: pshu6 is imm87=0 & pshu6 { } + +:PSHU pshu7 is op=0x36; pshu7 { } + diff --git a/python/icicle/Ghidra/Processors/MC6800/data/languages/H6309.slaspec b/python/icicle/Ghidra/Processors/MC6800/data/languages/H6309.slaspec new file mode 100644 index 0000000..0f82d8b --- /dev/null +++ b/python/icicle/Ghidra/Processors/MC6800/data/languages/H6309.slaspec @@ -0,0 +1,10 @@ +# sleigh specification file for Hitachi 6309 +# Compatible with MC6809 with some extended instructions +# and addressing modes + +@define H6309 "" + +@include "6x09.sinc" +@include "6x09_push.sinc" +@include "6x09_pull.sinc" +@include "6x09_exg_tfr.sinc" diff --git a/python/icicle/Ghidra/Processors/MCS96/data/languages/MCS96.cspec b/python/icicle/Ghidra/Processors/MCS96/data/languages/MCS96.cspec new file mode 100644 index 0000000..8fc7c87 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MCS96/data/languages/MCS96.cspec @@ -0,0 +1,31 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/MCS96/data/languages/MCS96.ldefs b/python/icicle/Ghidra/Processors/MCS96/data/languages/MCS96.ldefs new file mode 100644 index 0000000..bb3d161 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MCS96/data/languages/MCS96.ldefs @@ -0,0 +1,16 @@ + + + + + Intel MCS-96 Microcontroller Family + + + diff --git a/python/icicle/Ghidra/Processors/MCS96/data/languages/MCS96.pspec b/python/icicle/Ghidra/Processors/MCS96/data/languages/MCS96.pspec new file mode 100644 index 0000000..a668e82 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MCS96/data/languages/MCS96.pspec @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/MCS96/data/languages/MCS96.sinc b/python/icicle/Ghidra/Processors/MCS96/data/languages/MCS96.sinc new file mode 100644 index 0000000..25e9562 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MCS96/data/languages/MCS96.sinc @@ -0,0 +1,1368 @@ + +define endian=little; + +define alignment=1; + +define space RAM type=ram_space size=2 wordsize=1 default; +define space register type=register_space size=1; + +################################################################ +# Registers +################################################################ +define register offset=0x00 size=2 [ PSW ]; + +define register offset=0x10 size=2 [ PC ]; + +define register offset=0x18 size=2 [ SP ]; + +# Special registers +define RAM offset=0x00 size=1 +[ + ZRlo ZRhi AD_resultlo AD_resulthi HSI_timelo HSI_timehi + HSI_status SBUF INT_MASK INT_PEND TIMER1lo TIMER1hi + TIMER2lo TIMER2hi PORT0 PORT1 PORT2 SP_STAT INT_PEND1 + INT_MASK1 WSR IOS0 IOS1 IOS2 +]; + +define RAM offset=0x00 size=2 +[ + ZR AD_result HSI_time + HSI_SBUF INTERRUPT TIMER1 + TIMER2 PORT01 PORT2_SPS INT1 + WSR_IOS0 IOS12 +]; + +define RAM offset=0x00 size=4 +[ + ZR_AD HSI INT_TIMER1 + TIMER2_PORT01 PORT2_INT1 + WSR_IOS012 +]; + +# Stack pointer +define RAM offset=0x18 size=1 [ SPlo SPhi]; +define RAM offset=0x18 size=2 [ SPR ]; +define RAM offset=0x18 size=4 [ SPR1A ]; + + +# Byte registers +define RAM offset=0x1a size=1 +[ + R1A R1B R1C R1D R1E R1F + R20 R21 R22 R23 R24 R25 R26 R27 + R28 R29 R2A R2B R2C R2D R2E R2F + R30 R31 R32 R33 R34 R35 R36 R37 + R38 R39 R3A R3B R3C R3D R3E R3F + R40 R41 R42 R43 R44 R45 R46 R47 + R48 R49 R4A R4B R4C R4D R4E R4F + R50 R51 R52 R53 R54 R55 R56 R57 + R58 R59 R5A R5B R5C R5D R5E R5F + R60 R61 R62 R63 R64 R65 R66 R67 + R68 R69 R6A R6B R6C R6D R6E R6F + R70 R71 R72 R73 R74 R75 R76 R77 + R78 R79 R7A R7B R7C R7D R7E R7F + R80 R81 R82 R83 R84 R85 R86 R87 + R88 R89 R8A R8B R8C R8D R8E R8F + R90 R91 R92 R93 R94 R95 R96 R97 + R98 R99 R9A R9B R9C R9D R9E R9F + RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 + RA8 RA9 RAA RAB RAC RAD RAE RAF + RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 + RB8 RB9 RBA RBB RBC RBD RBE RBF + RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 + RC8 RC9 RCA RCB RCC RCD RCE RCF + RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 + RD8 RD9 RDA RDB RDC RDD RDE RDF + RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7 + RE8 RE9 REA REB REC RED REE REF + RF0 RF1 RF2 RF3 RF4 RF5 RF6 RF7 + RF8 RF9 RFA RFB RFC RFD RFE RFF + R100 R101 R102 R103 R104 R105 R106 R107 + R108 R109 R10A R10B R10C R10D R10E R10F + R110 R111 R112 R113 R114 R115 R116 R117 + R118 R119 R11A R11B R11C R11D R11E R11F + R120 R121 R122 R123 R124 R125 R126 R127 + R128 R129 R12A R12B R12C R12D R12E R12F + R130 R131 R132 R133 R134 R135 R136 R137 + R138 R139 R13A R13B R13C R13D R13E R13F + R140 R141 R142 R143 R144 R145 R146 R147 + R148 R149 R14A R14B R14C R14D R14E R14F + R150 R151 R152 R153 R154 R155 R156 R157 + R158 R159 R15A R15B R15C R15D R15E R15F + R160 R161 R162 R163 R164 R165 R166 R167 + R168 R169 R16A R16B R16C R16D R16E R16F + R170 R171 R172 R173 R174 R175 R176 R177 + R178 R179 R17A R17B R17C R17D R17E R17F + R180 R181 R182 R183 R184 R185 R186 R187 + R188 R189 R18A R18B R18C R18D R18E R18F + R190 R191 R192 R193 R194 R195 R196 R197 + R198 R199 R19A R19B R19C R19D R19E R19F + R1A0 R1A1 R1A2 R1A3 R1A4 R1A5 R1A6 R1A7 + R1A8 R1A9 R1AA R1AB R1AC R1AD R1AE R1AF + R1B0 R1B1 R1B2 R1B3 R1B4 R1B5 R1B6 R1B7 + R1B8 R1B9 R1BA R1BB R1BC R1BD R1BE R1BF + R1C0 R1C1 R1C2 R1C3 R1C4 R1C5 R1C6 R1C7 + R1C8 R1C9 R1CA R1CB R1CC R1CD R1CE R1CF + R1D0 R1D1 R1D2 R1D3 R1D4 R1D5 R1D6 R1D7 + R1D8 R1D9 R1DA R1DB R1DC R1DD R1DE R1DF + R1E0 R1E1 R1E2 R1E3 R1E4 R1E5 R1E6 R1E7 + R1E8 R1E9 R1EA R1EB R1EC R1ED R1EE R1EF + R1F0 R1F1 R1F2 R1F3 R1F4 R1F5 R1F6 R1F7 + R1F8 R1F9 R1FA R1FB R1FC R1FD R1FE R1FF +]; + +# Word registers +define RAM offset=0x1a size=2 +[ + RW1A RW1C RW1E + RW20 RW22 RW24 RW26 RW28 RW2A RW2C RW2E + RW30 RW32 RW34 RW36 RW38 RW3A RW3C RW3E + RW40 RW42 RW44 RW46 RW48 RW4A RW4C RW4E + RW50 RW52 RW54 RW56 RW58 RW5A RW5C RW5E + RW60 RW62 RW64 RW66 RW68 RW6A RW6C RW6E + RW70 RW72 RW74 RW76 RW78 RW7A RW7C RW7E + RW80 RW82 RW84 RW86 RW88 RW8A RW8C RW8E + RW90 RW92 RW94 RW96 RW98 RW9A RW9C RW9E + RWA0 RWA2 RWA4 RWA6 RWA8 RWAA RWAC RWAE + RWB0 RWB2 RWB4 RWB6 RWB8 RWBA RWBC RWBE + RWC0 RWC2 RWC4 RWC6 RWC8 RWCA RWCC RWCE + RWD0 RWD2 RWD4 RWD6 RWD8 RWDA RWDC RWDE + RWE0 RWE2 RWE4 RWE6 RWE8 RWEA RWEC RWEE + RWF0 RWF2 RWF4 RWF6 RWF8 RWFA RWFC RWFE + RW100 RW102 RW104 RW106 RW108 RW10A RW10C RW10E + RW110 RW112 RW114 RW116 RW118 RW11A RW11C RW11E + RW120 RW122 RW124 RW126 RW128 RW12A RW12C RW12E + RW130 RW132 RW134 RW136 RW138 RW13A RW13C RW13E + RW140 RW142 RW144 RW146 RW148 RW14A RW14C RW14E + RW150 RW152 RW154 RW156 RW158 RW15A RW15C RW15E + RW160 RW162 RW164 RW166 RW168 RW16A RW16C RW16E + RW170 RW172 RW174 RW176 RW178 RW17A RW17C RW17E + RW180 RW182 RW184 RW186 RW188 RW18A RW18C RW18E + RW190 RW192 RW194 RW196 RW198 RW19A RW19C RW19E + RW1A0 RW1A2 RW1A4 RW1A6 RW1A8 RW1AA RW1AC RW1AE + RW1B0 RW1B2 RW1B4 RW1B6 RW1B8 RW1BA RW1BC RW1BE + RW1C0 RW1C2 RW1C4 RW1C6 RW1C8 RW1CA RW1CC RW1CE + RW1D0 RW1D2 RW1D4 RW1D6 RW1D8 RW1DA RW1DC RW1DE + RW1E0 RW1E2 RW1E4 RW1E6 RW1E8 RW1EA RW1EC RW1EE + RW1F0 RW1F2 RW1F4 RW1F6 RW1F8 RW1FA RW1FC RW1FE +]; + +# Double-word registers +define RAM offset=0x1c size=4 +[ + RL1C + RL20 RL24 RL28 RL2C RL30 RL34 RL38 RL3C + RL40 RL44 RL48 RL4C RL50 RL54 RL58 RL5C + RL60 RL64 RL68 RL6C RL70 RL74 RL78 RL7C + RL80 RL84 RL88 RL8C RL90 RL94 RL98 RL9C + RLA0 RLA4 RLA8 RLAC RLB0 RLB4 RLB8 RLBC + RLC0 RLC4 RLC8 RLCC RLD0 RLD4 RLD8 RLDC + RLE0 RLE4 RLE8 RLEC RLF0 RLF4 RLF8 RLFC + RL100 RL104 RL108 RL10C RL110 RL114 RL118 RL11C + RL120 RL124 RL128 RL12C RL130 RL134 RL138 RL13C + RL140 RL144 RL148 RL14C RL150 RL154 RL158 RL15C + RL160 RL164 RL168 RL16C RL170 RL174 RL178 RL17C + RL180 RL184 RL188 RL18C RL190 RL194 RL198 RL19C + RL1A0 RL1A4 RL1A8 RL1AC RL1B0 RL1B4 RL1B8 RL1BC + RL1C0 RL1C4 RL1C8 RL1CC RL1D0 RL1D4 RL1D8 RL1DC + RL1E0 RL1E4 RL1E8 RL1EC RL1F0 RL1F4 RL1F8 RL1FC +]; + +# Individual status bits within the Program Status Word +@define Z "PSW[7,1]" # Zero Flag +@define N "PSW[6,1]" # Negative Flag +@define V "PSW[5,1]" # Overflow Flag +@define VT "PSW[4,1]" # Overflow Trap Flag +@define C "PSW[3,1]" # Carry Flag +@define PSE "PSW[2,1]" # Peripheral Transaction Server flag +@define I "PSW[1,1]" # global Interrupt disable bit +@define ST "PSW[0,1]" # STicky bit Flag + +################################################################ +# Tokens +################################################################ +# All instructions have a single-byte opcode except for a +# handful of multiplication/division instructions which have +# a two-byte op-code with the first byte as 'FE' +define token opbyte (8) + op8 = (0,7) + op6 = (2,7) + op5 = (3,7) + cond = (0,3) + op4 = (4,7) + aa = (0,1) + bitno = (0,2) + highb = (4,7) + imm8 = (0,7) signed # immediate + simm8 = (0,7) signed # immediate + baop = (0,7) # byte register + breg8 = (0,7) # byte register + dbreg = (0,7) # byte register + waop = (0,7) # word register + wreg8 = (0,7) # word register + dwreg = (0,7) # word register + lreg = (0,7) # long/double register + dlreg = (0,7) # long/double register + imm7 = (1,7) + iwreg7 = (1,7) + addbit8 = (0,0) +; + +define token opword (16) + imm16 = ( 0, 15 ) + disp16 = (0,15) signed + op16 = (3,7) + jmp11_hi = (0,2) signed #relative offset + jmp11_lo = (8,15) +; + +attach variables [ baop breg8 dbreg ] +[ + ZRlo ZRhi AD_resultlo AD_resulthi HSI_timelo HSI_timehi + HSI_status SBUF INT_MASK INT_PEND TIMER1lo TIMER1hi + TIMER2lo TIMER2hi PORT0 PORT1 PORT2 SP_STAT INT_PEND1 + INT_MASK1 WSR IOS0 IOS1 IOS2 SPlo SPhi + R1A R1B R1C R1D R1E R1F + R20 R21 R22 R23 R24 R25 R26 R27 + R28 R29 R2A R2B R2C R2D R2E R2F + R30 R31 R32 R33 R34 R35 R36 R37 + R38 R39 R3A R3B R3C R3D R3E R3F + R40 R41 R42 R43 R44 R45 R46 R47 + R48 R49 R4A R4B R4C R4D R4E R4F + R50 R51 R52 R53 R54 R55 R56 R57 + R58 R59 R5A R5B R5C R5D R5E R5F + R60 R61 R62 R63 R64 R65 R66 R67 + R68 R69 R6A R6B R6C R6D R6E R6F + R70 R71 R72 R73 R74 R75 R76 R77 + R78 R79 R7A R7B R7C R7D R7E R7F + R80 R81 R82 R83 R84 R85 R86 R87 + R88 R89 R8A R8B R8C R8D R8E R8F + R90 R91 R92 R93 R94 R95 R96 R97 + R98 R99 R9A R9B R9C R9D R9E R9F + RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 + RA8 RA9 RAA RAB RAC RAD RAE RAF + RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 + RB8 RB9 RBA RBB RBC RBD RBE RBF + RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 + RC8 RC9 RCA RCB RCC RCD RCE RCF + RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 + RD8 RD9 RDA RDB RDC RDD RDE RDF + RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7 + RE8 RE9 REA REB REC RED REE REF + RF0 RF1 RF2 RF3 RF4 RF5 RF6 RF7 + RF8 RF9 RFA RFB RFC RFD RFE RFF +]; + +attach variables [ waop wreg8 dwreg ] +[ + ZR _ AD_result _ HSI_time _ + HSI_SBUF _ INTERRUPT _ TIMER1 _ + TIMER2 _ PORT01 _ PORT2_SPS _ INT1 _ + WSR_IOS0 _ IOS12 _ SP _ + RW1A _ RW1C _ RW1E _ + RW20 _ RW22 _ RW24 _ RW26 _ RW28 _ RW2A _ RW2C _ RW2E _ + RW30 _ RW32 _ RW34 _ RW36 _ RW38 _ RW3A _ RW3C _ RW3E _ + RW40 _ RW42 _ RW44 _ RW46 _ RW48 _ RW4A _ RW4C _ RW4E _ + RW50 _ RW52 _ RW54 _ RW56 _ RW58 _ RW5A _ RW5C _ RW5E _ + RW60 _ RW62 _ RW64 _ RW66 _ RW68 _ RW6A _ RW6C _ RW6E _ + RW70 _ RW72 _ RW74 _ RW76 _ RW78 _ RW7A _ RW7C _ RW7E _ + RW80 _ RW82 _ RW84 _ RW86 _ RW88 _ RW8A _ RW8C _ RW8E _ + RW90 _ RW92 _ RW94 _ RW96 _ RW98 _ RW9A _ RW9C _ RW9E _ + RWA0 _ RWA2 _ RWA4 _ RWA6 _ RWA8 _ RWAA _ RWAC _ RWAE _ + RWB0 _ RWB2 _ RWB4 _ RWB6 _ RWB8 _ RWBA _ RWBC _ RWBE _ + RWC0 _ RWC2 _ RWC4 _ RWC6 _ RWC8 _ RWCA _ RWCC _ RWCE _ + RWD0 _ RWD2 _ RWD4 _ RWD6 _ RWD8 _ RWDA _ RWDC _ RWDE _ + RWE0 _ RWE2 _ RWE4 _ RWE6 _ RWE8 _ RWEA _ RWEC _ RWEE _ + RWF0 _ RWF2 _ RWF4 _ RWF6 _ RWF8 _ RWFA _ RWFC _ RWFE _ +]; + +attach variables [iwreg7] +[ + ZR AD_result HSI_time + HSI_SBUF INTERRUPT TIMER1 + TIMER2 PORT01 PORT2_SPS INT1 + WSR_IOS0 IOS12 SP + RW1A RW1C RW1E + RW20 RW22 RW24 RW26 RW28 RW2A RW2C RW2E + RW30 RW32 RW34 RW36 RW38 RW3A RW3C RW3E + RW40 RW42 RW44 RW46 RW48 RW4A RW4C RW4E + RW50 RW52 RW54 RW56 RW58 RW5A RW5C RW5E + RW60 RW62 RW64 RW66 RW68 RW6A RW6C RW6E + RW70 RW72 RW74 RW76 RW78 RW7A RW7C RW7E + RW80 RW82 RW84 RW86 RW88 RW8A RW8C RW8E + RW90 RW92 RW94 RW96 RW98 RW9A RW9C RW9E + RWA0 RWA2 RWA4 RWA6 RWA8 RWAA RWAC RWAE + RWB0 RWB2 RWB4 RWB6 RWB8 RWBA RWBC RWBE + RWC0 RWC2 RWC4 RWC6 RWC8 RWCA RWCC RWCE + RWD0 RWD2 RWD4 RWD6 RWD8 RWDA RWDC RWDE + RWE0 RWE2 RWE4 RWE6 RWE8 RWEA RWEC RWEE + RWF0 RWF2 RWF4 RWF6 RWF8 RWFA RWFC RWFE +]; + +attach variables [ lreg dlreg ] +[ + ZR_AD _ _ _ HSI _ _ _ INT_TIMER1 _ _ _ + TIMER2_PORT01 _ _ _ PORT2_INT1 _ _ _ + WSR_IOS012 _ _ _ SPR1A _ _ _ + RL1C _ _ _ + RL20 _ _ _ RL24 _ _ _ RL28 _ _ _ RL2C _ _ _ RL30 _ _ _ RL34 _ _ _ RL38 _ _ _ RL3C _ _ _ + RL40 _ _ _ RL44 _ _ _ RL48 _ _ _ RL4C _ _ _ RL50 _ _ _ RL54 _ _ _ RL58 _ _ _ RL5C _ _ _ + RL60 _ _ _ RL64 _ _ _ RL68 _ _ _ RL6C _ _ _ RL70 _ _ _ RL74 _ _ _ RL78 _ _ _ RL7C _ _ _ + RL80 _ _ _ RL84 _ _ _ RL88 _ _ _ RL8C _ _ _ RL90 _ _ _ RL94 _ _ _ RL98 _ _ _ RL9C _ _ _ + RLA0 _ _ _ RLA4 _ _ _ RLA8 _ _ _ RLAC _ _ _ RLB0 _ _ _ RLB4 _ _ _ RLB8 _ _ _ RLBC _ _ _ + RLC0 _ _ _ RLC4 _ _ _ RLC8 _ _ _ RLCC _ _ _ RLD0 _ _ _ RLD4 _ _ _ RLD8 _ _ _ RLDC _ _ _ + RLE0 _ _ _ RLE4 _ _ _ RLE8 _ _ _ RLEC _ _ _ RLF0 _ _ _ RLF4 _ _ _ RLF8 _ _ _ RLFC _ _ _ +]; + +immed8: imm8 is imm8 { export *[const]:1 imm8; } + +simmed8: simm8 is simm8 { export *[const]:1 simm8; } + +immed16: imm16 is imm16 { export *[const]:2 imm16; } + +baop8: baop is baop & baop=0 { export 0:1; } +baop8: baop is baop & baop=1 { export 0:1; } +baop8: baop is baop { export baop; } + +waop16: waop is waop & waop=0 { export 0:2; } +waop16: waop is waop { export waop; } + +iwreg: iwreg7 is iwreg7 & iwreg7=0 { export 0:2; } +iwreg: iwreg7 is iwreg7 { export iwreg7; } + +breg: breg8 is breg8 & breg8=0 { export 0:1; } +breg: breg8 is breg8 & breg8=1 { export 0:1; } +breg: breg8 is breg8 { export breg8; } + +wreg: wreg8 is wreg8 & wreg8=0 { export 0:2; } +wreg: wreg8 is wreg8 { export wreg8; } + +# See reference manual pp. 29-30 and note 1 on page 113 +# 1-byte operands +oper8: baop8 is aa=0x0; baop8 { export baop8; } #direct +oper8: "#"immed8 is aa=0x1; immed8 { export immed8; } #immediate +oper8: "["iwreg"]" is aa=0x2; iwreg & addbit8=0 { + local tmp = iwreg; + export *[RAM]:1 tmp; +} #indirect +oper8: "["iwreg"]+" is aa=0x2; iwreg & addbit8=1 { + local tmp = iwreg; + iwreg = iwreg + 1; + export *[RAM]:1 tmp; +} #indirect+ +oper8: simmed8"["iwreg"]" is aa=0x3; iwreg & addbit8=0; simmed8 { + local tmp = iwreg; + tmp = tmp + sext(simmed8); + export *[RAM]:1 tmp; +} #indexed short +oper8: immed16", LOOKUP["iwreg"]" is aa=0x3; iwreg & addbit8=1; immed16 { + local tmp = iwreg; + tmp = tmp + immed16; + export *[RAM]:1 tmp; +} #indexed long + +# 2-byte operands +oper16: waop16 is aa=0x0; waop16 { export waop16; } #direct +oper16: "#"immed16 is aa=0x1; immed16 { export immed16; } #immediate +oper16: "["iwreg"]" is aa=0x2; iwreg & addbit8=0 { + local tmp = iwreg; + export *[RAM]:2 tmp; +} #indirect +oper16: "["iwreg"]+" is aa=0x2; iwreg & addbit8=1 { + local tmp = iwreg; + iwreg = iwreg + 2; + export *[RAM]:2 tmp; +} #indirect +oper16: simmed8"["iwreg"]" is aa=0x3; iwreg & addbit8=0; simmed8 { + local tmp = iwreg; + tmp = tmp + sext(simmed8); + export *[RAM]:2 tmp; +} #indexed short +oper16: immed16", TABLE["iwreg"]" is aa=0x3 ; iwreg & addbit8=1; immed16 { + local tmp = iwreg; + tmp = tmp + immed16; + export *[RAM]:2 tmp; +} #indexed long + +# range -128 through +127 +jmpdest: reloc is simm8 [ reloc = inst_next + simm8; ] { export *:1 reloc; } + +# range -1023 through 1024 +jmpdest11: reloc is jmp11_hi & jmp11_lo [reloc = inst_next + ((jmp11_hi << 8) | jmp11_lo);] { export *:2 reloc; } +jmpdest16: reloc is disp16 [reloc = inst_next + disp16;] { export *:2 reloc; } + +################################################################ +# Pseudo Instructions +################################################################ +#define pcodeop blockMove; +define pcodeop idlePowerdown; +define pcodeop normalize; + +################################################################ +# Macros +################################################################ +macro push(val) { + SP = SP - 2; + *:2 SP = val; +} + +macro pop(val) { + val = *:2 SP; + SP = SP + 2; +} + +macro resetFlags() { + PSW = 0; +} + +macro resultFlags(res) { + $(Z) = (res == 0); + $(N) = (res s< 0); + $(C) = 0; + $(V) = 0; +} + +macro additionFlags(op1, op2, res) { + $(Z) = (res == 0); + $(N) = (res s< 0); + $(C) = carry(op1, op2); + $(V) = scarry(op1, op2); + $(VT) = $(V) | $(VT); +} + +macro subtractFlags(op1, op2, res) { + $(N) = (res s< 0); + $(Z) = (res == 0); + $(C) = (op1 < op2) == 0; + $(V) = sborrow(op1, op2); + $(VT) = $(VT) | $(V); +} + +macro stickyFlagW(source, shift) { + local mask:2 = -1; + mask = (mask >> (16 - shift + 1)) * zext(shift > 1); + local result:2 = source & mask; + + $(ST) = (result != 0); +} + +macro stickyFlagB(source, shift) { + local mask:1 = -1; + mask = (mask >> (8 - shift + 1)) * (shift > 1); + local result:1 = source & mask; + + $(ST) = (result != 0); +} + +macro stickyFlagL(source, shift) { + local mask:4 = -1; + mask = (mask >> (32 - shift + 1)) * zext(shift > 1); + local result:4 = source & mask; + + $(ST) = (result != 0); +} + +macro blockMove(ptrs, cntreg) { + local tsptr:4 = (ptrs & 0xffff0000) >> 0x10; + local srcPtr:2 = tsptr(2); + local dstPtr:2 = ptrs(2); + local cnt = cntreg; + + local data:2 = *srcPtr; + *dstPtr = data; + srcPtr = srcPtr + 2; + dstPtr = dstPtr + 2; + cnt = cnt - 1; + if cnt != 0 goto ; + ptrs = zext(dstPtr) | (zext(srcPtr) << 0x10); +} + +macro setShiftLeftCarryFlag(shiftee,amount) { + shifting:1 = amount != 0; + local tmp = ((shiftee >> (16-amount)) & 1); + $(C) = (shifting & tmp:1); +} + +macro setShiftRightCarryFlag(shiftee,amount) { + shifting:1 = amount != 0; + local tmp = (shiftee >> (amount-1)) & 1; + $(C) = (shifting & tmp:1); +} + +macro setSignedShiftRightCarryFlag(shiftee,amount) { + shifting:1 = amount != 0; + local tmp = (shiftee s>> (amount-1)) & 1; + $(C) = (shifting & tmp:1); +} + +################################################################ +# Constructors +################################################################ +# 2-op +:ADD wreg, oper16 is op6=0x19 ... & oper16; wreg { + local tmpD = wreg + oper16; + additionFlags(wreg, oper16, tmpD); + wreg = tmpD; +} + +# 3 op +:ADD dwreg, wreg, oper16 is op6=0x11 ... & oper16; wreg; dwreg { + local tmpD = wreg + oper16; + dwreg = tmpD; + additionFlags(wreg, oper16, tmpD); +} + +# 2-op +:ADDB breg, oper8 is op6=0x1d ... & oper8; breg { + local tmp = breg + oper8; + additionFlags(breg, oper8, tmp); + breg = tmp; +} + +:ADDB dbreg, breg, oper8 is op6=0x15 ... & oper8; breg; dbreg { + local tmp = breg + oper8; + dbreg = tmp; + additionFlags(breg, oper8, tmp); +} + +:ADDC wreg, oper16 is op6=0x29 ... & oper16; wreg { + local tmp = oper16 + zext($(C)); + local res = wreg + tmp; + local oldz = $(Z); + additionFlags(wreg, tmp, res); + $(Z) = oldz & $(Z); # only cleared, not set + wreg = res; +} + +:ADDCB breg, oper8 is op6=0x2d ... & oper8; breg { + local tmp = oper8 + $(C); + local res =breg + tmp; + local oldz = $(Z); + additionFlags(breg, tmp, res); + $(Z) = oldz & $(Z); # only cleared, not set + breg = res; +} + +# 2-op +:AND wreg, oper16 is op6=0x18 ... & oper16; wreg { + wreg = wreg & oper16; + resultFlags(wreg); +} + +# 3-op +:AND dwreg, wreg, oper16 is op6=0x10 ... & oper16; wreg; dwreg { + dwreg = wreg & oper16; + resultFlags(dwreg); +} + +:ANDB breg, oper8 is op6=0x1c ... & oper8; breg { + breg = breg & oper8; + resultFlags(breg); +} + +:ANDB dbreg, breg, oper8 is op6=0x14 ... & oper8; breg; dbreg { + dbreg = breg & oper8; + resultFlags(dbreg); +} + +:BMOV lreg, wreg is op8=0xc1; wreg ; lreg { + blockMove(lreg, wreg); +} + +:BMOVI lreg, wreg is op8=0xcd; wreg; lreg { + blockMove(lreg, wreg); +} + +:BR [ wreg ] is op8=0xe3; wreg { + goto [wreg]; +} + +:CLR wreg is op8=0x1; wreg { + wreg = 0; + $(Z) = 1; + $(N) = 0; + $(C) = 0; + $(V) = 0; +} + +:CLRB breg is op8=0x11; breg { + breg = 0; + $(Z) = 1; + $(N) = 0; + $(C) = 0; + $(V) = 0; +} + +:CLRC is op8=0xf8 { + $(C) = 0; +} + +:CLRVT is op8=0xfc { + $(VT) = 0; +} + +:CMP wreg, oper16 is op6=0x22 ... & oper16; wreg { + op1:2 = oper16; + tmp:2 = wreg - op1; + subtractFlags(wreg, op1, tmp); +} + +:CMPB breg, oper8 is op6=0x26 ... & oper8; breg { + op1:1 = oper8; + tmp:1 = breg - op1; + subtractFlags(breg, op1, tmp); +} + +@if defined(C196KB) || defined(C196KC) +:CMPL dlreg, lreg is op8=0xc5; lreg; dlreg { + op1:4 = lreg; + tmp:4 = dlreg - op1; + $(N) = (tmp s< 0); + $(Z) = (tmp == 0); + $(C) = scarry(dlreg, op1); + $(V) = (((dlreg & ~op1 & ~tmp) | (~dlreg & op1 & tmp)) & 0x80000000 ) != 0; + $(VT) = $(VT) | $(V); +} + +@endif + +:DEC wreg is op8=0x05; wreg { + local tmp = wreg - 1; + subtractFlags(wreg, 1, tmp); + wreg = tmp; +} + +:DECB breg is op8=0x15; breg { + local tmp = breg - 1; + subtractFlags(breg, 1, tmp); + breg = tmp; +} + +:DI is op8=0xfa { + $(I) = 0; +} + +:DIV lreg, oper16 is op8=0xfe; op6=0x23 ... & oper16; lreg { + local num = lreg; + local den = oper16; + local div = num s/ sext(den); + local rem = num s% sext(den); + lreg = zext(div:2 << 16) | rem; +@if defined(C196KB) || defined(C196KC) + $(V) = ((div s> 0x7fff) | (div s< 0x8001)); +@endif + $(VT) = $(VT) | $(V); +} + +:DIVB wreg, oper8 is op8=0xfe; op6=0x27 ... & oper8; wreg { + local num = wreg; + local den = oper8; + local div = num s/ sext(den); + local rem = num s% sext(den); + wreg = zext(div:1 << 8) | rem; +@if defined(C196KB) || defined(C196KC) + $(V) = ((div s> 0x7f) | (div s< 0x81)); +@endif + $(VT) = $(VT) | $(V); +} + +:DIVU lreg, oper16 is op6=0x23 ... & oper16; lreg { + local num = lreg; + local den = oper16; + local div = num / zext(den); + local rem = num % zext(den); + lreg = zext(div:2 << 16) | rem; + $(V) = (div > 0xffff); + $(VT) = $(VT) | $(V); +} + +:DIVUB wreg, oper8 is op6=0x27 ... & oper8; wreg { + local num = wreg; + local den = oper8; + local div = num / zext(den); + local rem = num % zext(den); + wreg = zext(div:1 << 8) | rem; + $(V) = (div > 0xff); + $(VT) = $(VT) | $(V); +} + +:DJNZ breg, jmpdest is op8=0xe0; breg; jmpdest { + breg = breg - 1; + if (breg != 0) goto jmpdest; +} + +@if defined(C196KB) || defined(C196KC) +:DJNZW wreg, jmpdest is op8=0xe1; wreg; jmpdest { + wreg = wreg - 1; + if (wreg != 0) goto jmpdest; +} + +@endif + +@if defined(C196KC) +:DPTS is op8=0xec { + $(PSE) = 0; +} + +@endif + +:EI is op8=0xfb { + $(I) = 1; +} + +@if defined(C196KC) +:EPTS is op8=0xed { + $(PSE) = 1; +} + +@endif + +:EXT lreg is op8=0x6; lreg { + tmp:4 = lreg & 0xffff; + lreg = sext(tmp); + resultFlags(lreg); +} + +:EXTB wreg is op8=0x16; wreg { + tmp:2 = wreg & 0xff; + wreg = sext(tmp); + resultFlags(wreg); +} + +:INC wreg is op8=0x7; wreg { + local tmp = wreg + 1; + additionFlags(wreg, 1, tmp); + wreg = tmp; +} + +:INCB breg is op8=0x17; breg { + local tmp = breg + 1; + additionFlags(breg, 1, tmp); + breg = tmp; +} + +@if defined(C196KB) || defined(C196KC) +:IDLPD "#"immed8 is op8=0xf6; immed8 { + idlePowerdown(); + $(Z) = 0; + $(N) = 0; + $(C) = 0; + $(V) = 0; + $(VT) = 0; + $(ST) = 0; +} + +@endif + +:JBC breg, bitno, jmpdest is op5=0x6 & bitno; breg; jmpdest { + local bit = (breg >> bitno) & 0x1; + if (bit == 0) goto jmpdest; +} + +:JBS breg, bitno, jmpdest is op5=0x7 & bitno; breg; jmpdest { + local bit = (breg >> bitno) & 0x1; + if (bit == 1) goto jmpdest; +} + +cc: "NST" is cond=0 { tmp:1 = ($(ST) == 0); export tmp; } +cc: "NH" is cond=1 { tmp:1 = (($(C) == 0) | ($(Z) == 1)); export tmp; } +cc: "GT" is cond=2 { tmp:1 = (($(N) == 0) & ($(Z) == 0)); export tmp; } +cc: "NC" is cond=3 { tmp:1 = ($(C) == 0); export tmp; } +cc: "NVT" is cond=4 { tmp:1 = ($(VT) == 0); $(VT) = 0; export tmp; } +cc: "NV" is cond=5 { tmp:1 = ($(V) == 0); export tmp; } +cc: "GE" is cond=6 { tmp:1 = ($(N) == 0); export tmp; } +cc: "NE" is cond=7 { tmp:1 = ($(Z) == 0); export tmp; } +cc: "ST" is cond=8 { tmp:1 = ($(ST) == 1); export tmp; } +cc: "H" is cond=9 { tmp:1 = (($(C) == 1) & ($(Z) == 0)); export tmp; } +cc: "LE" is cond=10 { tmp:1 = (($(N) == 1) | ($(Z) == 1)); export tmp; } +cc: "C" is cond=11 { tmp:1 = ($(C) == 1); export tmp; } +cc: "VT" is cond=12 { tmp:1 = ($(VT) == 1); $(VT) = 0; export tmp; } +cc: "V" is cond=13 { tmp:1 = ($(V) == 1); export tmp; } +cc: "LT" is cond=14 { tmp:1 = ($(N) == 1); export tmp; } +cc: "E" is cond=15 { tmp:1 = ($(Z) == 1); export tmp; } + +:J^cc jmpdest is op4=0xd & cc; jmpdest +{if (cc) goto jmpdest;} + + +:LCALL jmpdest16 is op8=0xef; jmpdest16 { + ret:2 = inst_next; + push(ret); + call jmpdest16; +} + +:LD wreg, oper16 is op6=0x28 ... & oper16; wreg { + wreg = oper16; +} + +:LDB breg, oper8 is op6=0x2c ... & oper8; breg { + breg = oper8; +} + +:LDBSE wreg, oper8 is op6=0x2f ... & oper8; wreg { + wreg = sext(oper8); +} + +:LDBZE wreg, oper8 is op6=0x2b ... & oper8; wreg { + wreg = zext(oper8); +} + +:LJMP jmpdest16 is op8=0xe7; jmpdest16 { + goto jmpdest16; +} + +# 2-op +:MUL lreg, oper16 is op8=0xfe; op6=0x1b ... & oper16; lreg { + tmpD:4 = sext(lreg:2); + tmpS:4 = sext(oper16); + tmpD = tmpD * tmpS; + lreg = tmpD; +} + +# 3-op +:MUL lreg, wreg, oper16 is op8=0xfe; op6=0x13 ... & oper16; wreg; lreg { + tmpD:4 = sext(wreg); + tmpS:4 = sext(oper16); + tmpD = tmpD * tmpS; + lreg = tmpD; +} + +# 2-op +:MULB wreg, oper8 is op8=0xfe; op6=0x1f ... & oper8; wreg { + tmpD:2 = sext(wreg:1); + tmpS:2 = sext(oper8); + tmpD = tmpD * tmpS; + wreg = tmpD; +} + +# 3-op +:MULB wreg, breg, oper8 is op8=0xfe; op6=0x17 ... & oper8; breg; wreg { + tmpD:2 = sext(breg); + tmpS:2 = sext(oper8); + tmpD = tmpD * tmpS; + wreg = tmpD; +} + +# 2-op +:MULU lreg, oper16 is op6=0x1b ... & oper16; lreg { + tmpD:4 = zext(lreg:2); + tmpS:4 = zext(oper16); + tmpD = tmpD * tmpS; + lreg = tmpD; +} + +# 3-op +:MULU lreg, wreg, oper16 is op6=0x13 ... & oper16; wreg; lreg { + tmpD:4 = zext(wreg); + tmpS:4 = zext(oper16); + tmpD = tmpD * tmpS; + lreg = tmpD; +} + +# 2-op +:MULUB wreg, oper8 is op6=0x1f ... & oper8; wreg { + tmpD:2 = zext(wreg:1); + tmpS:2 = zext(oper8); + tmpD = tmpD * tmpS; + wreg = tmpD; +} + +# 3-op +:MULUB wreg, breg, oper8 is op6=0x17 ... & oper8; breg; wreg { + local tmpD:2 = zext(breg); + local tmpS:2 = zext(oper8); + tmpD = tmpD * tmpS; + wreg = tmpD; +} + +:NEG wreg is op8=0x03; wreg { + local tmp:2 = -wreg; + local zero:2 = 0; + subtractFlags(zero, wreg, tmp); + wreg = tmp; +} + +:NEGB breg is op8=0x13; breg { + local tmp:1 = -breg; + local zero:1 = 0; + subtractFlags(zero, breg, tmp); + breg = tmp; +} + +:NOP is op8=0xfd { } #NOP + +:NORML lreg, breg is op8=0xf; breg; lreg { + #The LONG-INTEGER operand is normalized; i.e., it is shifted to the left until its + #most significant bit is 1. If the most significant bit is still 0 after 31 shifts, the + #process stops and the zero flag is set. The number of shifts actually performed + #is stored in the second operand. + normalize(lreg, breg); + $(Z) = (lreg == 0); + $(C) = 0; +# $(N) is undefined +} + +:NOT wreg is op8 = 0x2; wreg { + wreg = ~wreg; + resultFlags(wreg); +} + +:NOTB breg is op8=0x12; breg { + breg = ~breg; + resultFlags(breg); +} + +:OR wreg, oper16 is op6=0x20 ... & oper16; wreg { + tmpD:2 = wreg; + tmpS:2 = oper16; + tmpD = tmpD | tmpS; + wreg = tmpD; + resultFlags(wreg); +} + +:ORB breg, oper8 is op6=0x24 ... & oper8; breg { + tmpD:1 = breg; + tmpS:1 = oper8; + tmpD = tmpD | tmpS; + breg = tmpD; + resultFlags(breg); +} + +:POP oper16 is op6=0x33 ... & oper16 { + local result:2 = 0; + pop(result); + oper16 = result; +} + +@if defined(C196KB) || defined(C196KC) +:POPA is op8=0xf5 { + local result:2 = 0; + pop(result); + WSR = result:1 & 0xff; + local resultHi = result >> 8; + INT_MASK1 = resultHi:1; + pop(result); + INT_MASK = result:1 & 0xff; + resultHi = result >> 8; + PSW = resultHi:1; +} + +@endif + +:POPF is op8=0xf3 { + local result:2 = 0; + pop(result); + PSW = result:1; + local resultHi = result >> 8; + INT_MASK = resultHi:1; +} + +:PUSH oper16 is op6=0x32 ... & oper16 { + val:2 = oper16; + push(val); +} + +@if defined(C196KB) || defined(C196KC) +:PUSHA is op8=0xf4 { + local val:2 = (zext(INT_MASK) << 8) | zext(WSR); + push(val); + val = (zext(INT_MASK) << 8) | zext(PSW); + push(val); + resetFlags(); +} + +@endif + +:PUSHF is op8=0xf2 { + val:2 = (zext(INT_MASK) << 8) | zext(PSW); + push(val); + resetFlags(); +} + +:RET is op8=0xf0 { + local retDest:2 = 0; + pop(retDest); + return [retDest]; +} + +:RST is op8=0xff { + resetFlags(); + PC = 0x2080; + goto [PC]; +} + +:SCALL jmpdest11 is op16=0x5 & jmpdest11 { + ret:2 = inst_next; + push(ret); + call jmpdest11; +} + +:SETC is op8=0xf9 { + $(C) = 1; +} + +:SHL wreg, "#"immed8 is op8=0x09; immed8 & (highb = 0x0); wreg { + local source = wreg; + local shift = immed8; + setShiftLeftCarryFlag(source, shift); + local res = source << shift; + $(Z) = (res == 0); + $(V) = 0; + $(VT) = $(VT) | $(V); + wreg = res; +} + +:SHL wreg, breg is op8=0x09; breg & (highb != 0x0); wreg { + local source = wreg; + local shift = breg; + setShiftLeftCarryFlag(source, shift); + local res = source << shift; + $(Z) = (res == 0); + $(V) = 0; + $(VT) = $(VT) | $(V); + wreg = res; +} + +:SHLB dbreg, "#"immed8 is op8=0x19; immed8 & (highb = 0x0); dbreg { + local source = dbreg; + local shift = immed8; + setShiftLeftCarryFlag(source, shift); + local res = source << shift; + $(Z) = (res == 0); + $(V) = 0; + $(VT) = $(VT) | $(V); + dbreg = res; +} + +:SHLB dbreg, breg is op8=0x19; breg & (highb != 0x0); dbreg { + local source = dbreg; + local shift = breg; + setShiftLeftCarryFlag(source, shift); + local res = source << shift; + $(Z) = (res == 0); + $(V) = 0; + $(VT) = $(VT) | $(V); + dbreg = res; +} + +:SHLL lreg, "#"immed8 is op8=0x0d; immed8 & (highb = 0x0); lreg { + local source = lreg; + local shift = immed8; + setShiftLeftCarryFlag(source, shift); + local res = source << shift; + $(Z) = (res == 0); + $(V) = 0; + $(VT) = $(VT) | $(V); + lreg = res; +} + +:SHLL lreg, breg is op8=0x0d; breg & (highb != 0x0); lreg { + local source = lreg; + local shift = breg; + setShiftLeftCarryFlag(source, shift); + local res = source << shift; + $(Z) = (res == 0); + $(V) = 0; + $(VT) = $(VT) | $(V); + lreg = res; +} + +:SHR wreg, "#"immed8 is op8=0x08; immed8 & (highb = 0x0); wreg { + local source = wreg; + local shift = immed8; + $(ST) = 0; + setShiftRightCarryFlag(source, shift); + local res = source >> shift; + $(Z) = (res == 0); + $(N) = 0; + $(V) = 0; + wreg = res; + stickyFlagW(source, shift); +} + +:SHR wreg, breg is op8=0x08; breg & (highb != 0x0); wreg { + local source = wreg; + local shift = breg; + setShiftRightCarryFlag(source, shift); + local res = source >> shift; + $(Z) = (res == 0); + $(N) = 0; + $(V) = 0; + wreg = res; + stickyFlagW(source, shift); +} + +:SHRA wreg, "#"immed8 is op8=0x0a; immed8 & (highb = 0x0); wreg { + local source = wreg; + local shift = immed8; + setSignedShiftRightCarryFlag(source, shift); + local res = source s>> shift; + $(Z) = (res == 0); + $(N) = (res s< 0); + $(V) = 0; + wreg = res; + stickyFlagW(source, shift); +} + +:SHRA wreg, breg is op8=0x0a; breg & (highb != 0x0); wreg { + local source = wreg; + local shift = breg; + setSignedShiftRightCarryFlag(source, shift); + local res = source s>> shift; + $(Z) = (res == 0); + $(N) = (res s< 0); + $(V) = 0; + wreg = res; + stickyFlagW(source, shift); +} + +:SHRAB dbreg, "#"immed8 is op8=0x1a; immed8 & (highb = 0x0); dbreg { + local source = dbreg; + local shift = immed8; + setSignedShiftRightCarryFlag(source, shift); + local res = source s>> shift; + $(Z) = (res == 0); + $(N) = (res s< 0); + $(V) = 0; + dbreg = res; + stickyFlagB(source, shift); +} + +:SHRAB dbreg, breg is op8=0x1a; breg & (highb != 0x0); dbreg { + local source = dbreg; + local shift = breg; + setSignedShiftRightCarryFlag(source, shift); + local res = source s>> shift; + $(Z) = (res == 0); + $(N) = (res s< 0); + $(V) = 0; + dbreg = res; + stickyFlagB(source, shift); +} + +:SHRAL lreg, "#"immed8 is op8=0x0e; immed8 & (highb = 0x0); lreg { + local source = lreg; + local shift = immed8; + setSignedShiftRightCarryFlag(source, shift); + local res = source s>> shift; + $(Z) = (res == 0); + $(N) = (res s< 0); + $(V) = 0; + lreg = res; + stickyFlagL(source, shift); +} + +:SHRAL lreg, breg is op8=0x0e; breg & (highb != 0x0); lreg { + local source = lreg; + local shift = breg; + setSignedShiftRightCarryFlag(source, shift); + local res = source s>> shift; + $(Z) = (res == 0); + $(N) = (res s< 0); + $(V) = 0; + lreg = res; + stickyFlagL(source, shift); +} + +:SHRB dbreg, "#"immed8 is op8=0x18; immed8 & (highb = 0x0); dbreg { + local source = dbreg; + local shift = immed8; + setShiftRightCarryFlag(source, shift); + local res = source >> shift; + $(Z) = (res == 0); + $(N) = 0; + $(V) = 0; + dbreg = res; + stickyFlagB(source, shift); +} + +:SHRB dbreg, breg is op8=0x18; breg & (highb != 0x0); dbreg { + local source = dbreg; + local shift = breg; + setShiftRightCarryFlag(source, shift); + local res = source >> shift; + $(Z) = (res == 0); + $(N) = 0; + $(V) = 0; + dbreg = res; + stickyFlagB(source, shift); +} + +:SHRL lreg, "#"immed8 is op8=0x0c; immed8 & (highb = 0x0); lreg { + local source = lreg; + local shift = immed8; + setShiftRightCarryFlag(source, shift); + local res = source >> shift; + $(Z) = (res == 0); + $(N) = 0; + $(V) = 0; + lreg = res; + stickyFlagL(source, shift); +} + +:SHRL lreg, breg is op8=0x0c; breg & (highb != 0x0); lreg { + local source = lreg; + local shift = breg; + setShiftRightCarryFlag(source, shift); + local res = source >> shift; + $(Z) = (res == 0); + $(N) = 0; + $(V) = 0; + lreg = res; + stickyFlagL(source, shift); +} + +:SJMP jmpdest11 is op16=0x4 & jmpdest11 { + goto jmpdest11; +} + +:SKIP is op8=0x00 { + local tmp:1 = 0; + tmp = tmp; # avoid warning +} #2-byte NOP + +:ST wreg, oper16 is op6=0x30 ... & oper16; wreg { + oper16 = wreg; +} + +:STB breg, oper8 is op6=0x31 ... & oper8; breg { + oper8 = breg; +} + +# 2-op +:SUB wreg, oper16 is op6=0x1a ... & oper16; wreg { + local tmp = wreg - oper16; + subtractFlags(wreg, oper16, tmp); + wreg = tmp; +} + +# 3 op +:SUB dwreg, wreg, oper16 is op6=0x12 ... & oper16; wreg; dwreg { + dwreg = wreg - oper16; + subtractFlags(wreg, oper16, dwreg); +} + +# 2-op +:SUBB breg, oper8 is op6=0x1e ... & oper8; breg { + local tmp = breg - oper8; + subtractFlags(breg, oper8, tmp); +} + +:SUBB dbreg, breg, oper8 is op6=0x16 ... & oper8; breg; dbreg { + dbreg = breg - oper8; + subtractFlags(breg, oper8, dbreg); +} + +:SUBC wreg, oper16 is op6=0x2a ... & oper16; wreg { + local tmp = wreg - oper16 - zext(1 - $(C)); + local oldz = $(Z); + subtractFlags(wreg, oper16-zext(1-$(C)), tmp); + wreg = tmp; + $(Z) = oldz & $(Z); +} + +:SUBCB breg, oper8 is op6=0x2e ... & oper8; breg { + local tmp = breg - oper8 - zext(1 - $(C)); + local oldz = $(Z); + subtractFlags(breg, oper8-zext(1-$(C)), tmp); + breg = tmp; + $(Z) = oldz & $(Z); +} + +@if defined(C196KC) +:TIJMP dwreg, "["wreg"]" "#"immed8 is op8=0xe2; wreg; immed8; dwreg { + local index = *wreg; + local jmpOffset = zext(index & immed8); + local tBase = dwreg; + local destX = (jmpOffset << 1) + tBase; + local jmpDest = *:2 destX; + + goto [jmpDest]; +} + +@endif + +:TRAP is op8=0xf7 { + ret:2 = inst_next; + push(ret); + trapv:2 = 0x2010; + PC = *trapv; + goto [PC]; +} + +:XOR wreg, oper16 is op6=0x21 ... & oper16; wreg { + tmpD:2 = wreg; + tmpS:2 = oper16; + tmpD = tmpD ^ tmpS; + wreg = tmpD; + resultFlags(wreg); +} + +@if defined(C196KC) +:XCH wreg, waop16 is op8=0x04; waop16; wreg { + local tmp = wreg; + wreg = waop16; + waop16 = tmp; +} + +:XCH wreg, immed8", TABLE["iwreg"]" is op8=0x0b; iwreg & addbit8=0; immed8; wreg { + local tmp = iwreg; + tmp = tmp + sext(immed8); + local val = *[RAM]:2 tmp; + + local wreg_tmp = wreg; + wreg = val; + *[RAM]:2 tmp = wreg_tmp; +} + +:XCH wreg, immed16", TABLE["iwreg"]" is op8=0x0b; iwreg & addbit8=1; immed16; wreg { + local tmp = iwreg; + tmp = tmp + immed16; + local val = *[RAM]:2 tmp; + + local wreg_tmp = wreg; + wreg = val; + *[RAM]:2 tmp = wreg_tmp; +} + +@endif + +@if defined(C196KC) +:XCHB breg, baop8 is op8=0x14 ; baop8; breg { + local tmp = breg; + breg = baop8; + baop8 = tmp; +} + +:XCHB breg, immed8", TABLE["iwreg"]" is op8=0x1b ; iwreg & addbit8=0; immed8; breg { + local tmp = iwreg; + tmp = tmp + sext(immed8); + local val = *[RAM]:1 tmp; + + local wreg_tmp = breg; + breg = val; + *[RAM]:1 tmp = wreg_tmp; +} + +:XCHB breg, immed16", TABLE["iwreg"]" is op8=0x1b ; iwreg & addbit8=1; immed16; breg { + local tmp = iwreg; + tmp = tmp + sext(immed16); + local val = *[RAM]:1 tmp; + + local wreg_tmp = breg; + breg = val; + *[RAM]:1 tmp = wreg_tmp; +} + +@endif + +:XORB breg, oper8 is op6=0x25 ... & oper8; breg { + tmpD:1 = breg; + tmpS:1 = oper8; + tmpD = tmpD ^ tmpS; + breg = tmpD; + resultFlags(breg); +} + + + diff --git a/python/icicle/Ghidra/Processors/MCS96/data/languages/MCS96.slaspec b/python/icicle/Ghidra/Processors/MCS96/data/languages/MCS96.slaspec new file mode 100644 index 0000000..75ee965 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MCS96/data/languages/MCS96.slaspec @@ -0,0 +1,4 @@ +@define C196KB "1" +@define C196KC "1" + +@include "MCS96.sinc" diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/MIPS.opinion b/python/icicle/Ghidra/Processors/MIPS/data/languages/MIPS.opinion new file mode 100644 index 0000000..00a1625 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/MIPS.opinion @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips.dwarf b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips.dwarf new file mode 100644 index 0000000..24c6d53 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips.dwarf @@ -0,0 +1,21 @@ + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips.ldefs b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips.ldefs new file mode 100644 index 0000000..21fe52d --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips.ldefs @@ -0,0 +1,309 @@ + + + + MIPS32 32-bit addresses, big endian, with mips16e + + + + + + + + + MIPS32 32-bit addresses, little endian, with mips16e + + + + + + + + + MIPS32 Release-6 32-bit addresses, big endian, with microMIPS + + + + + + MIPS32 Release-6 32-bit addresses, little endian, with microMIPS + + + + + + MIPS64 64-bit addresses, big endian, with mips16e + + + + + + + + MIPS64 64-bit addreses, little endian, with mips16e + + + + + + + + + MIPS64 64-bit addresses, big endian, with microMIPS + + + + + + + MIPS64 64-bit addresses, little endian, with microMIPS + + + + + + + + MIPS64 Release-6 64-bit addresses, big endian, with microMIPS + + + + + + + MIPS64 Release-6 64-bit addresses, little endian, with microMIPS + + + + + + + + MIPS64 32-bit addresses, big endian, with mips16e + + + + + + + + + + + + MIPS64 32-bit addresses, little endian, with mips16e + + + + + + + + + + + + + MIPS64 32-bit addresses, little endian, with microMIPS + + + + + + + + + + + + MIPS64 32-bit addresses, big endian, with microMIPS + + + + + + + + + + + MIPS64 Release-6 big endian with 32 bit addressing and microMIPS + + + + + + + + + + + MIPS64 Release-6 with 32-bit addresses, little endian, with microMIPS + + + + + + + + + + + + MIPS32 32-bit addresses, big endian, with microMIPS + + + + + + + MIPS32 32-bit addresses, little endian, with microMIPS + + + + + + diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips.sinc b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips.sinc new file mode 100755 index 0000000..a2660f7 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips.sinc @@ -0,0 +1,1014 @@ +# MIPS Common specification file for 32 and 64-bit processors +# Appropriate defines (MIPS32, MIPS64, MIPS64_32ADDRS) must be +# specified before including this file + +# The following Coprocessor configuration is supported: +# COP0: integrated CPU virtual memory and exception handler +# COP1: Floating-point Unit (FPU) +# COP2: +# COP3: Used for MIPS64 FPU extended instructions (see COP1X) +# +# ################################ +# +# Notes for the elf header e_flags "secondary" field in the MIPS.opinion file. +# +# "-" indicates don't care +# +# 0x5------- MIPS32 Release 1, 32-bit addresses, ABI is o32, FREGSIZE = 4, gcc -mips32 +# Example: 0x50001001, secondary="1342181377" +# +# 0x6-----2- MIPS64 Release 1, 32-bit addresses, ABI is n32, FREGSIZE = 8, gcc -mips64 +# +# 0x6-----0- MIPS64 Release 1, 64-bit addresses, ABI is n64, FREGSIZE = 8, gcc -mips64 -mabi-64 +# +# 0x7------- MIPS32 Release 2, ABI is o32, gcc -mips32r2 to r5 +# if 0x00000200 is set then FREGSIZE = 8 else FREGSIZE = 4 +# 0x70001001, secondary="1879052289" +# with mips16: 0x74001001 +# +# 0x8-----2- MIPS64 Release 2, 32-bit addresses, ABI is n32, FREGSIZE = 8, gcc -mips64r2 to r5 +# 0x80000021, secondary="2147483681" +# +# 0x8-----0- MIPS64 Release 2, 64-bit addresses, ABI is n64, gcc -mips64r2 to r5 -mabi-64 +# 0x80000001 +# +# 0x9------- MIPS32 Release 6, ABI is o32, gcc -mips32r6 +# if 0x00000200 is set then FREGSIZE = 8 else FREGSIZE = 4 +# +# 0xa-----2- MIPS64 Release 6, 32-bit addresses, ABI is n32, FREGSIZE = 8, gcc -mips64r6 +# 0xa0000421 +# +# 0xa-----0- MIPS64 Release 6, 64-bit addresses, ABI is n64, FREGSIZE = 8, gcc -mips64r6 -mabi-64 +# +# Masks: +# +# 0x04000000 MIPS-16 +# +# 0x02000000 MicroMIPS +# +# ################################ +# +# Notes about register names and function args: +# +# Function args are passed in a0 - a3, which are the same as $4 - $7, other args are on the stack +# Floating point args are in f12 and f14 +# +# Function return values are stored in v0 (and v1 if the regs are 32-bit and return type is 64-bits) +# v0 and v1 are the same as general purpose regs $2 and $3 +# Floating point return values are in f0 (and f1 if needed for binding) +# +# $29 is the stack pointer sp +# $30 is the frame pointer fp also called s8 +# $31 is the return address ra +# +# ################################ +# There is now support for single and double floating point instructions, with the following limitations: +# +# The PS paired single fmt1 format is not implemented. In paired single instructions, +# the specified 64-bit floating point register operands are each considered as two separate +# 32-bit floating points numbers, and they are processed in parallel with the same instuction. +# (This is supposed to be the first microprocessor implementation of SIMD.) +# +# Only COP1 Floating point coprocessor unit 1 is supported (there is no support for unit 2) +# +# Some notes about MIPS Floating Point, derived from the FPU table on page 87 of the MIPS +# Architecture Volume 1, 2014 +# +# FPU configuration is stored in a 32-bit read-only Floating Point Implementation Register (FIR), +# this is also known as CP1 Control Register 0. +# Bit 22, called F64 or also called the FR bit, is = 1 when you have 64-bit FPRs, +# else if the FR bit = 0 then you have 32-bit FPRs +# +# The macro FREGSIZE = 4 for 32-bit FPRs, and = 8 for 64-bit FPRs +# +# Other info is in the FCSR register, CP1 Register 31. +# Bit 23 is one condition code, and bits 25-31 is the FCC with other condition codes, +# which are set after a compare. Note this FCRE register is removed in Release 6. +# +# MIPS32 Release 1: +# The FPU (floating point unit) has 32 32-bit FPRs +# 64-bit floating point doubles are stored in even-odd pairs of FPRs +# F64 = 0 +# +# MIPS32 Release 2 and later: +# FPU has 32 64-bit FPRs +# F64 = 1 +# Use these gcc options to get 64-bit floating point instructions: -mips32r2 -mfp64 +# (gcc default is 32-bit FPRs) +# +# MIPS64 Release 1 - 5 +# The FPU has 32 64-bit FPRs +# F64 = 1 +# +# MIPS32 Release 6: +# In "strictly 32-bit" mode there are 32 32-bit FPRs, and bonding of two 32-bit FPRs to support +# 64-bit floating point is not allowed +# F64 = 0 +# +# MIPS64 Release 6: +# FPU has 32 64-bit FPRs, when F64 = 1 +# In "strictly 32-bit" mode there are 32 32-bit FPRs, and bonding of two 32-bit FPRs is not allowed +# F64 = 0 +# +# Release 6: +# Floating point condition codes are removed, and replaced by a new CMP.condn.fmt instruction +# The PS paired-single format in floating point instructions is removed - this was when +# two 32-bit floats were stuffed into one 64-bit FPR, and supported SIMD. +# +# In function calls, floating point args are passed in FPRs f12 to f15, and the return value is in f0 +# +# When you have 32-bit FPRs, then 64-bit double floats are created by bonding a pair of 32-bit FPRs. +# f0 is the low half or has the LSB or also called lower word of the double, and +# f1 is the high half or has the MSB or also called upper word of the double +# +# When you have a 64-bit longword integer: +# For function return longword values: +# $2 (same as v0) holds the MSB top half of the longword +# $3 (same as v1) holds the LSB bottom half of the longword +# +# Note that when FREGSIZE = 8 (ie, 64-bit FPRs) and you have a single 32-bit float, then the +# 32-bit float data is stored in bits 0-31 of the FPR. (Bits 32-63 are "unused".) +# +# Note that when conversions are done to/from floats, doubles, ints, and longs (64-bit) that rounding +# errors can occur in the simulator, so equality comparisons should be done carefully. +# +# ################################ +# +#----- +@ifdef MIPS64 + +@ifdef MIPS64_32ADDRS # used for 64-bit mips restricted to 32-bit addresses + +@define REGSIZE "8" # General purpose register size (8 or 4) +@define FREGSIZE "8" # Floating point register size (8 or 4) +@define ADDRSIZE "4" # Memory address size (8 or 4, virtual and physical) +@define DREGSIZE "16" # 2x REGSIZE used for accumulators +@define SIZETO4 "4" # In 32-bit mode, no truncation needed +@define ADDRCAST ":4" # need to down cast to pointer size +@define NEEDCAST "1" + +@else # full 64 bit ptrs + +@define REGSIZE "8" # General purpose register size (8 or 4) +@define FREGSIZE "8" # Floating point register size (8 or 4) +@define ADDRSIZE "8" # Memory address size (8 or 4, virtual and physical) +@define DREGSIZE "16" # 2x REGSIZE used for accumulators +@define SIZETO4 "4" # In 64-bit mode, use when need to do 32-bit operation +@define ADDRCAST "" # no need to down cast to pointer size + +@endif #MIPS64_32ADDRS + + +@else # MIPS32 + +@define REGSIZE "4" # General purpose register size (8 or 4) +# FREGSIZE for mips32 is set in slaspec file +@define ADDRSIZE "4" # Memory address size (8 or 4, virtual and physical) +@define DOUBLE "8" # 2x REGSIZE used for accumulators +@define DREGSIZE "8" +@define SIZETO4 "4" +@define ADDRCAST "" # no need to down cast to pointer size + +@endif +#----- + +define endian=$(ENDIAN); + +define alignment=2; + +define space ram type=ram_space size=$(ADDRSIZE) default; +define space register type=register_space size=4; + +# General purpose registers +define register offset=0 size=$(REGSIZE) [ + zero at v0 v1 + a0 a1 a2 a3 + t0 t1 t2 t3 + t4 t5 t6 t7 + s0 s1 s2 s3 + s4 s5 s6 s7 + t8 t9 k0 k1 + gp sp s8 ra + pc +]; + +@ifdef MIPS64 +# We need the 32-bit pieces of the main registers for the 32-bit instructions +@if ENDIAN == "big" +define register offset=0 size=4 [ + zero_hi zero_lo at_hi at_lo v0_hi v0_lo v1_hi v1_lo + a0_hi a0_lo a1_hi a1_lo a2_hi a2_lo a3_hi a3_lo + t0_hi t0_lo t1_hi t1_lo t2_hi t2_lo t3_hi t3_lo + t4_hi t4_lo t5_hi t5_lo t6_hi t6_lo t7_hi t7_lo + s0_hi s0_lo s1_hi s1_lo s2_hi s2_lo s3_hi s3_lo + s4_hi s4_lo s5_hi s5_lo s6_hi s6_lo s7_hi s7_lo + t8_hi t8_lo t9_hi t9_lo k0_hi k0_lo k1_hi k1_lo + gp_hi gp_lo sp_hi sp_lo s8_hi s8_lo ra_hi ra_lo + pc_hi pc_lo +]; +@else +define register offset=0 size=4 [ + zero_lo zero_hi at_lo at_hi v0_lo v0_hi v1_lo v1_hi + a0_lo a0_hi a1_lo a1_hi a2_lo a2_hi a3_lo a3_hi + t0_lo t0_hi t1_lo t1_hi t2_lo t2_hi t3_lo t3_hi + t4_lo t4_hi t5_lo t5_hi t6_lo t6_hi t7_lo t7_hi + s0_lo s0_hi s1_lo s1_hi s2_lo s2_hi s3_lo s3_hi + s4_lo s4_hi s5_lo s5_hi s6_lo s6_hi s7_lo s7_hi + t8_lo t8_hi t9_lo t9_hi k0_lo k0_hi k1_lo k1_hi + gp_lo gp_hi sp_lo sp_hi s8_lo s8_hi ra_lo ra_hi + pc_lo pc_hi +]; +@endif # ENDIAN + +@endif # MIPS64 + +# Floating point registers +@if FREGSIZE == "4" +@if ENDIAN == "big" +# For 64-bit Double floating point operands need to bond two 32-bit FPRs +define register offset=0x1000 size=4 [ + f1 f0 f3 f2 f5 f4 f7 f6 + f9 f8 f11 f10 f13 f12 f15 f14 + f17 f16 f19 f18 f21 f20 f23 f22 + f25 f24 f27 f26 f29 f28 f31 f30 +]; +@else +define register offset=0x1000 size=4 [ + f0 f1 f2 f3 f4 f5 f6 f7 + f8 f9 f10 f11 f12 f13 f14 f15 + f16 f17 f18 f19 f20 f21 f22 f23 + f24 f25 f26 f27 f28 f29 f30 f31 +]; +@endif # ENDIAN + +# Note ftD, fsD, and fdD and frD have been added to support 64-bit double floats +define register offset=0x1000 size=8 [ + f0_1 f2_3 f4_5 f6_7 + f8_9 f10_11 f12_13 f14_15 + f16_17 f18_19 f20_21 f22_23 + f24_25 f26_27 f28_29 f30_31 +]; +@else # FREGSIZE == "8" +define register offset=0x1000 size=8 [ + f0 f1 f2 f3 f4 f5 f6 f7 + f8 f9 f10 f11 f12 f13 f14 f15 + f16 f17 f18 f19 f20 f21 f22 f23 + f24 f25 f26 f27 f28 f29 f30 f31 +]; +@endif # FREGSIZE + +# Floating point control registers (common to both MIPS32 and MIPS64) +define register offset=0x1200 size=4 [ + fir fccr fexr fenr fcsr +]; + +# COP-0 control registers, sel=0 +define register offset=0x2000 size=$(REGSIZE) [ + Index Random EntryLo0 EntryLo1 + Context PageMask Wired HWREna + BadVAddr Count EntryHi Compare + Status Cause EPC PRId + Config LLAddr WatchLo WatchHi + XContext cop0_reg21 cop0_reg22 Debug + DEPC PerfCnt ErrCtl CacheErr + TagLo TagHi ErrorEPC DESAVE +]; + +# COP-0 control registers, sel=1 +define register offset=0x2100 size=$(REGSIZE) [ + MVPControl VPEControl TCStatus cop0_reg3.1 + ContextConfig PageGrain SRSConf0 cop0_reg7.1 + cop0_reg8.1 cop0_reg9.1 cop0_reg10.1 cop0_reg11.1 + IntCtl cop0_reg13.1 cop0_reg14.1 EBase + Config1 cop0_reg17.1 WatchLo.1 WatchHi.1 + cop0_reg20.1 cop0_reg21.1 cop0_reg22.1 TraceControl + cop0_reg24.1 PerfCnt.1 cop0_reg26.1 CacheErr.1 + DataLo.1 DataHi.1 cop0_reg30.1 cop0_reg31.1 +]; + +# COP-0 control registers, sel=2 +define register offset=0x2200 size=$(REGSIZE) [ + MVPConf0 VPEConf0 TCBind cop0_reg3.2 + cop0_reg4.2 cop0_reg5.2 SRSConf1 cop0_reg7.2 + cop0_reg8.2 cop0_reg9.2 cop0_reg10.2 cop0_reg11.2 + SRSCtl cop0_reg13.2 cop0_reg14.2 cop0_reg15.2 + Config2 cop0_reg17.2 WatchLo.2 WatchHi.2 + cop0_reg20.2 cop0_reg21.2 cop0_reg22.2 TraceControl2 + cop0_reg24.2 PerfCnt.2 cop0_reg26.2 CacheErr.2 + TagLo.2 TagHi.2 cop0_reg30.2 cop0_reg31.2 +]; + +# COP-0 control registers, sel=3 +define register offset=0x2300 size=$(REGSIZE) [ + MVPConf1 VPEConf1 TCRestart cop0_reg3.3 + cop0_reg4.3 cop0_reg5.3 SRSConf2 cop0_reg7.3 + cop0_reg8.3 cop0_reg9.3 cop0_reg10.3 cop0_reg11.3 + SRSMap cop0_reg13.3 cop0_reg14.3 cop0_reg15.3 + Config3 cop0_reg17.3 WatchLo.3 WatchHi.3 + cop0_reg20.3 cop0_reg21.3 cop0_reg22.3 UserTraceData + cop0_reg24.3 PerfCnt.3 cop0_reg26.3 CacheErr.3 + DataLo.3 DataHi.3 cop0_reg30.3 cop0_reg31.3 +]; + +# COP-0 control registers, sel=4 +define register offset=0x2400 size=$(REGSIZE) [ + cop0_reg0.4 YQMask TCHalt cop0_reg3.4 + cop0_reg4.4 cop0_reg5.4 SRSConf3 cop0_reg7.4 + cop0_reg8.4 cop0_reg9.4 cop0_reg10.4 cop0_reg11.4 + cop0_reg12.4 cop0_reg13.4 cop0_reg14.4 cop0_reg15.4 + cop0_reg16.4 cop0_reg17.4 WatchLo.4 WatchHi.4 + cop0_reg20.4 cop0_reg21.4 cop0_reg22.4 TraceBPC + cop0_reg24.4 PerfCnt.4 cop0_reg26.4 CacheErr.4 + TagLo.4 TagHi.4 cop0_reg30.4 cop0_reg31.4 +]; + +# COP-0 control registers, sel=5 +define register offset=0x2500 size=$(REGSIZE) [ + cop0_reg0.5 VPESchedule TCContext cop0_reg3.5 + cop0_reg4.5 cop0_reg5.5 SRSConf4 cop0_reg7.5 + cop0_reg8.5 cop0_reg9.5 cop0_reg10.5 cop0_reg11.5 + cop0_reg12.5 cop0_reg13.5 cop0_reg14.5 cop0_reg15.5 + cop0_reg16.5 cop0_reg17.5 WatchLo.5 WatchHi.5 + cop0_reg20.5 cop0_reg21.5 cop0_reg22.5 cop0_reg23.5 + cop0_reg24.5 PerfCnt.5 cop0_reg26.5 CacheErr.5 + DataLo.5 DataHi.5 cop0_reg30.5 cop0_reg31.5 +]; + +# COP-0 control registers, sel=6 +define register offset=0x2600 size=$(REGSIZE) [ + cop0_reg0.6 VPEScheFBack TCSchedule cop0_reg3.6 + cop0_reg4.6 cop0_reg5.6 cop0_reg6.6 cop0_reg7.6 + cop0_reg8.6 cop0_reg9.6 cop0_reg10.6 cop0_reg11.6 + cop0_reg12.6 cop0_reg13.6 cop0_reg14.6 cop0_reg15.6 + cop0_reg16.6 cop0_reg17.6 WatchLo.6 WatchHi.6 + cop0_reg20.6 cop0_reg21.6 cop0_reg22.6 cop0_reg23.6 + cop0_reg24.6 PerfCnt.6 cop0_reg26.6 CacheErr.6 + TagLo.6 TagHi.6 cop0_reg30.6 cop0_reg31.6 +]; + +# COP-0 control registers, sel=7 +define register offset=0x2700 size=$(REGSIZE) [ + cop0_reg0.7 VPEOpt TCScheFBack cop0_reg3.7 + cop0_reg4.7 cop0_reg5.7 cop0_reg6.7 cop0_reg7.7 + cop0_reg8.7 cop0_reg9.7 cop0_reg10.7 cop0_reg11.7 + cop0_reg12.7 cop0_reg13.7 cop0_reg14.7 cop0_reg15.7 + cop0_reg16.7 cop0_reg17.7 WatchLo.7 WatchHi.7 + cop0_reg20.7 cop0_reg21.7 cop0_reg22.7 cop0_reg23.7 + cop0_reg24.7 PerfCnt.7 cop0_reg26.7 CacheErr.7 + DataLo.7 DataHi.7 cop0_reg30.7 cop0_reg31.7 +]; + +# Some other internal registers +define register offset=0x3000 size=$(REGSIZE) [ +@if ENDIAN == "big" + hi lo hi1 lo1 hi2 lo2 hi3 lo3 +@else + lo hi lo1 hi1 lo2 hi2 lo3 hi3 +@endif # ENDIAN + tsp +]; + +# MIPS dsp lo/hi combined registers +define register offset=0x3000 size=$(DREGSIZE) [ ac0 ac1 ac2 ac3 ]; + +define register offset=0x3100 size=$(REGSIZE) [ DSPControl ]; + +define register offset=0x3200 size=$(REGSIZE) [ + HW_CPUNUM HW_SYNCI_STEP HW_CC HW_CCRe + HW_PerfCtr HW_XNP HW_RES6 HW_RES7 + HW_RES8 HW_RES9 HW_RES10 HW_RES11 + HW_RES12 HW_RES13 HW_RES14 HW_RES15 + HW_RES16 HW_RES17 HW_RES18 HW_RES19 + HW_RES20 HW_RES21 HW_RES22 HW_RES23 + HW_RES24 HW_RES25 HW_RES26 HW_RES27 + HW_RES28 HW_ULR HW_RESIM30 HW_RESIM31 +]; + +@ifdef ISA_VARIANT +define register offset=0x3F00 size=1 [ ISAModeSwitch ]; +@endif + +# Dummy registers for multi-threading +define register offset=0x3300 size=$(REGSIZE) [ + thread_zero thread_at thread_v0 thread_v1 thread_a0 thread_a1 thread_a2 thread_a3 + thread_t0 thread_t1 thread_t2 thread_t3 thread_t4 thread_t5 thread_t6 thread_t7 + thread_s0 thread_s1 thread_s2 thread_s3 thread_s4 thread_s5 thread_s6 thread_s7 + thread_t8 thread_t9 thread_k0 thread_k1 thread_gp thread_sp thread_s8 thread_ra + + thread_f0 thread_f1 thread_f2 thread_f3 thread_f4 thread_f5 thread_f6 thread_f7 + thread_f8 thread_f9 thread_f10 thread_f11 thread_f12 thread_f13 thread_f14 thread_f15 + thread_f16 thread_f17 thread_f18 thread_f19 thread_f20 thread_f21 thread_f22 thread_f23 + thread_f24 thread_f25 thread_f26 thread_f27 thread_f28 thread_f29 thread_f30 thread_f31 + + thread_lo0 thread_hi0 thread_acx0 _ thread_lo1 thread_hi1 thread_acx1 _ + thread_lo2 thread_hi2 thread_acx2 _ thread_lo3 thread_hi3 thread_acx3 _ + + thread_fir thread_fccr thread_fexr thread_fenr thread_fcsr +]; + +# Define context bits +define register offset=0x4000 size=4 contextreg; +define context contextreg + PAIR_INSTRUCTION_FLAG=(0,0) noflow # =1 paired instruction + REL6=(31,31) # =1 Release 6, =0 Pre release 6, (Fixed, set via pspec) + RELP=(30,30) # =1 Mips16e, =0 MicroMips. REL6, RELP can't both be 1 (Fixed, set via pspec) +@ifdef ISA_VARIANT + ISA_MODE=(1,1) # =1 Decode using alternate ISA, variable. + LowBitCodeMode = (1,1) # =1 if low bit of instruction address is set on a branch +#below here is for mips16e. Overlaps with micromips + ext_isjal=(2,2) noflow + ext_value=(3,13) noflow + ext_value_select=(3,5) noflow + ext_value_1005=(3,8) noflow + ext_value_1004=(3,9) noflow + ext_value_sa40=(3,7) noflow + ext_value_xreg=(3,5) noflow + ext_value_frame=(6,9) noflow + ext_value_areg=(10,13) noflow + ext_value_b0=(13,13) noflow + ext_value_b1=(12,12) noflow + ext_value_b2=(11,11) noflow + ext_value_b3=(10,10) noflow + ext_value_saz=(8,13) noflow + ext_value_1511=(9,13) noflow + ext_value_1511s=(9,13) signed noflow + ext_value_1411=(10,13) noflow + ext_value_1411s=(10,13) signed noflow + ext_tgt_2521=(3,7) noflow + ext_tgt_2016=(8,12) noflow + ext_tgt_x=(13,13) noflow + ext_is_ext=(14,14) noflow + ext_m16r32=(15,19) noflow + ext_m16r32a=(15,19) noflow + ext_reg_high=(15,16) noflow + ext_reg_low=(17,19) noflow + ext_svrs_sreg=(20,24) noflow + ext_svrs_xs=(20,22) noflow + ext_svrs_s1=(23,23) noflow + ext_svrs_s0=(24,24) noflow + ext_done=(25,25) noflow + ext_delay=(26,27) noflow +#below here is for micromips. Overlaps with mips16e + ext_t4_name=(2,5) noflow + ext_t4=(2,5) noflow + ext_tra=(6,6) noflow + ext_32_code=(7,16) noflow + ext_32_codes=(7,16) signed noflow + ext_32_addim=(10,16) noflow + ext_32_addims=(10,16) signed noflow + ext_32_imm2=(15,16) noflow + ext_32_imm2s=(15,16) signed noflow + ext_32_imm3=(14,16) noflow + ext_32_imm3s=(14,16) signed noflow + ext_32_imm5=(12,16) noflow + ext_32_imm5s=(12,16) signed noflow + ext_32_imm6=(11,16) noflow + ext_32_rlist=(7,11) noflow + ext_32_base=(12,16) noflow + ext_32_basea=(12,16) noflow + + ext_32_rd=(7,11) noflow + ext_32_rdset=(7,11) noflow + ext_32_rs1=(7,11) noflow + ext_32_rs1lo=(7,11) noflow + ext_32_rs1set=(7,11) noflow + ext_16_rs=(7,9) noflow + ext_16_rslo=(7,8) noflow + ext_16_rshi=(9,9) noflow + + ext_off16_s=(7,22) signed noflow + ext_off16_u=(7,22) noflow +@endif # ISA_VARIANT +; + + + +# Instruction fields + +define token instr(32) + prime = (26,31) + bit25 = (25,25) + zero2425 = (24,25) + zero2325 = (23,25) + zero1 = (22,25) + rs32 = (21,25) + frD = (21,25) + rs = (21,25) + fr = (21,25) + base = (21,25) + format = (21,25) + copop = (21,25) + mfmc0 = (21,25) + zero21 = (21,25) + jsub = (21,25) + sa_dsp2 = (21,25) + shift21 = (21,25) + sz = (21,25) + + acf = (21,22) + acflo = (21,22) + acfhi = (21,22) + shift20 = (20,25) + breakcode = (6,25) + off26 = (0,25) signed # 26 bit signed offset, e.g. balc, bc + ind26 = (0,25) # 26 bit unsigned index, e.g. jal + copfill = (6,24) + cofun = (0,24) + off21 = (0,20) signed # 21 bit signed offset in conditional branch/link + off16 = (0,15) signed # 16 bit signed offset in conditional branch/link + bit21 = (21,21) + bitz19 = (19,20) + pcrel = (19,20) + pcrel2 = (18,20) + cc = (18,20) + immed1625 = (16,25) signed + immed1623 = (16,23) signed + rt32 = (16,20) + rt = (16,20) + rtmtdsp = (16,20) + RT0thread = (16,20) + RTthread = (16,20) + FTthread = (16,20) + FCTthread = (16,20) + ftD = (16,20) + ft = (16,20) + index = (16,20) + hint = (16,20) + cop1code = (16,20) + synci = (16,20) + cond = (16,20) + op = (16,20) + zero1620 = (16,20) + + zero1619 = (16,19) + lohiacx = (16,19) + nd = (17,17) + tf = (16,16) + zero1320 = (13,20) + zero1315 = (13,15) + szero = (11,25) + mask = (11,20) + baser6 = (11,15) + rd32 = (11,15) + rd = (11,15) + rdmtdsp = (11,15) + rd0_0 = (11,15) + rd0_1 = (11,15) + rd0_2 = (11,15) + rd0_3 = (11,15) + rd0_4 = (11,15) + rd0_5 = (11,15) + rd0_6 = (11,15) + rd0_7 = (11,15) + rd_hw = (11,15) + cp2cprSel0 = (11,15) + cp2cprSel1 = (11,15) + cp2cprSel2 = (11,15) + cp2cprSel3 = (11,15) + cp2cprSel4 = (11,15) + cp2cprSel5 = (11,15) + cp2cprSel6 = (11,15) + cp2cprSel7 = (11,15) + fsD = (11,15) + fs = (11,15) + RD0thread = (11,15) + RDthread = (11,15) + FDthread = (11,15) + FCRthread = (16,20) + sa_dsp = (11,15) + fs_unk = (11,15) + fs_fcr = (11,15) + zero4 = (11,15) + msbd = (11,15) + + lohiacx2 = (11,14) + aclo = (11,12) + achi = (11,12) + ac = (11,12) + bp = (11,12) + bit10 = (10,10) + spec2 = (9,10) + spec3 = (8,10) + simmed9 = (7,15) + zero2 = (7,10) + code = (6,15) + fdD = (6,10) + fd = (6,10) + stype = (6,10) + sa = (6,10) + lsb = (6,10) + fct2 = (6,10) + zero5 = (6,10) + wsbh = (6,10) + + bp3 = (6,8) + sel_0608 = (6,8) + sa2 = (6,7) + bp2 = (6,7) + zero6 = (3,10) + bigfunct = (0,10) + fct = (0,5) + bshfl = (0,5) + bit6 = (6,6) + zero3 = (0,4) + bit5 = (5,5) + h = (4,4) + op4 = (3,5) + bit3 = (3,3) + sel = (0,2) + format1X = (0,2) + simmed19 = (0,18) signed + simmed18 = (0,17) signed + immed = (0,15) + simmed = (0,15) signed + simmseq = (6,15) signed + simmed11 = (0,10) +; + +attach variables [ rs rt rd base index baser6 ] [ + zero at v0 v1 a0 a1 a2 a3 + t0 t1 t2 t3 t4 t5 t6 t7 + s0 s1 s2 s3 s4 s5 s6 s7 + t8 t9 k0 k1 gp sp s8 ra +]; + +attach variables [ rd_hw ] [ + HW_CPUNUM HW_SYNCI_STEP HW_CC HW_CCRe + HW_PerfCtr HW_XNP HW_RES6 HW_RES7 + HW_RES8 HW_RES9 HW_RES10 HW_RES11 + HW_RES12 HW_RES13 HW_RES14 HW_RES15 + HW_RES26 HW_RES17 HW_RES18 HW_RES19 + HW_RES20 HW_RES21 HW_RES22 HW_RES23 + HW_RES24 HW_RES25 HW_RES26 HW_RES27 + HW_RES28 HW_ULR HW_RESIM30 HW_RESIM31 +]; + +@ifdef MIPS64 +attach variables [ rs32 rt32 rd32 ] [ + zero_lo at_lo v0_lo v1_lo a0_lo a1_lo a2_lo a3_lo + t0_lo t1_lo t2_lo t3_lo t4_lo t5_lo t6_lo t7_lo + s0_lo s1_lo s2_lo s3_lo s4_lo s5_lo s6_lo s7_lo + t8_lo t9_lo k0_lo k1_lo gp_lo sp_lo s8_lo ra_lo +]; +@else +# For MIPS32 these are the same as rs, rt, and rd +attach variables [ rs32 rt32 rd32 ] [ + zero at v0 v1 a0 a1 a2 a3 + t0 t1 t2 t3 t4 t5 t6 t7 + s0 s1 s2 s3 s4 s5 s6 s7 + t8 t9 k0 k1 gp sp s8 ra +]; +@endif + +attach variables [ fs ft fd fr ] [ + f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 + f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 +]; + +@if FREGSIZE == "4" +# For 64-bit floating point Double instruction operands need to bond two 32-bit FPRs +attach variables [ fsD ftD fdD frD ] [ + f0_1 _ f2_3 _ f4_5 _ f6_7 _ + f8_9 _ f10_11 _ f12_13 _ f14_15 _ + f16_17 _ f18_19 _ f20_21 _ f22_23 _ + f24_25 _ f26_27 _ f28_29 _ f30_31 _ +]; +@else # FREGSIZE == "8" +attach variables [ fsD ftD fdD frD ] [ + f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 + f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 +]; +@endif + +# Only a few Floating Point Control (FCR) registers are defined +attach variables [ fs_fcr ] [ + fir _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + _ fccr fexr _ fenr _ _ fcsr +]; + +attach variables [ rd0_0 ] [ + Index Random EntryLo0 EntryLo1 + Context PageMask Wired HWREna + BadVAddr Count EntryHi Compare + Status Cause EPC PRId + Config LLAddr WatchLo WatchHi + XContext cop0_reg21 cop0_reg22 Debug + DEPC PerfCnt ErrCtl CacheErr + TagLo TagHi ErrorEPC DESAVE +]; + +attach variables [ rd0_1 ] [ + MVPControl VPEControl TCStatus cop0_reg3.1 + ContextConfig PageGrain SRSConf0 cop0_reg7.1 + cop0_reg8.1 cop0_reg9.1 cop0_reg10.1 cop0_reg11.1 + IntCtl cop0_reg13.1 cop0_reg14.1 EBase + Config1 cop0_reg17.1 WatchLo.1 WatchHi.1 + cop0_reg20.1 cop0_reg21.1 cop0_reg22.1 TraceControl + cop0_reg24.1 PerfCnt.1 cop0_reg26.1 CacheErr.1 + DataLo.1 DataHi.1 cop0_reg30.1 cop0_reg31.1 +]; + +attach variables [ rd0_2 ] [ + MVPConf0 VPEConf0 TCBind cop0_reg3.2 + cop0_reg4.2 cop0_reg5.2 SRSConf1 cop0_reg7.2 + cop0_reg8.2 cop0_reg9.2 cop0_reg10.2 cop0_reg11.2 + SRSCtl cop0_reg13.2 cop0_reg14.2 cop0_reg15.2 + Config2 cop0_reg17.2 WatchLo.2 WatchHi.2 + cop0_reg20.2 cop0_reg21.2 cop0_reg22.2 TraceControl2 + cop0_reg24.2 PerfCnt.2 cop0_reg26.2 CacheErr.2 + TagLo.2 TagHi.2 cop0_reg30.2 cop0_reg31.2 +]; + +attach variables [ rd0_3 ] [ + MVPConf1 VPEConf1 TCRestart cop0_reg3.3 + cop0_reg4.3 cop0_reg5.3 SRSConf2 cop0_reg7.3 + cop0_reg8.3 cop0_reg9.3 cop0_reg10.3 cop0_reg11.3 + SRSMap cop0_reg13.3 cop0_reg14.3 cop0_reg15.3 + Config3 cop0_reg17.3 WatchLo.3 WatchHi.3 + cop0_reg20.3 cop0_reg21.3 cop0_reg22.3 UserTraceData + cop0_reg24.3 PerfCnt.3 cop0_reg26.3 CacheErr.3 + DataLo.3 DataHi.3 cop0_reg30.3 cop0_reg31.3 +]; + +attach variables [ rd0_4 ] [ + cop0_reg0.4 YQMask TCHalt cop0_reg3.4 + cop0_reg4.4 cop0_reg5.4 SRSConf3 cop0_reg7.4 + cop0_reg8.4 cop0_reg9.4 cop0_reg10.4 cop0_reg11.4 + cop0_reg12.4 cop0_reg13.4 cop0_reg14.4 cop0_reg15.4 + cop0_reg16.4 cop0_reg17.4 WatchLo.4 WatchHi.4 + cop0_reg20.4 cop0_reg21.4 cop0_reg22.4 TraceBPC + cop0_reg24.4 PerfCnt.4 cop0_reg26.4 CacheErr.4 + TagLo.4 TagHi.4 cop0_reg30.4 cop0_reg31.4 +]; + +attach variables [ rd0_5 ] [ + cop0_reg0.5 VPESchedule TCContext cop0_reg3.5 + cop0_reg4.5 cop0_reg5.5 SRSConf4 cop0_reg7.5 + cop0_reg8.5 cop0_reg9.5 cop0_reg10.5 cop0_reg11.5 + cop0_reg12.5 cop0_reg13.5 cop0_reg14.5 cop0_reg15.5 + cop0_reg16.5 cop0_reg17.5 WatchLo.5 WatchHi.5 + cop0_reg20.5 cop0_reg21.5 cop0_reg22.5 cop0_reg23.5 + cop0_reg24.5 PerfCnt.5 cop0_reg26.5 CacheErr.5 + DataLo.5 DataHi.5 cop0_reg30.5 cop0_reg31.5 +]; + +attach variables [ rd0_6 ] [ + cop0_reg0.6 VPEScheFBack TCSchedule cop0_reg3.6 + cop0_reg4.6 cop0_reg5.6 cop0_reg6.6 cop0_reg7.6 + cop0_reg8.6 cop0_reg9.6 cop0_reg10.6 cop0_reg11.6 + cop0_reg12.6 cop0_reg13.6 cop0_reg14.6 cop0_reg15.6 + cop0_reg16.6 cop0_reg17.6 WatchLo.6 WatchHi.6 + cop0_reg20.6 cop0_reg21.6 cop0_reg22.6 cop0_reg23.6 + cop0_reg24.6 PerfCnt.6 cop0_reg26.6 CacheErr.6 + TagLo.6 TagHi.6 cop0_reg30.6 cop0_reg31.6 +]; + +attach variables [ rd0_7 ] [ + cop0_reg0.7 VPEOpt TCScheFBack cop0_reg3.7 + cop0_reg4.7 cop0_reg5.7 cop0_reg6.7 cop0_reg7.7 + cop0_reg8.7 cop0_reg9.7 cop0_reg10.7 cop0_reg11.7 + cop0_reg12.7 cop0_reg13.7 cop0_reg14.7 cop0_reg15.7 + cop0_reg16.7 cop0_reg17.7 WatchLo.7 WatchHi.7 + cop0_reg20.7 cop0_reg21.7 cop0_reg22.7 cop0_reg23.7 + cop0_reg24.7 PerfCnt.7 cop0_reg26.7 CacheErr.7 + DataLo.7 DataHi.7 cop0_reg30.7 cop0_reg31.7 +]; + +attach variables [ aclo acflo ] [ lo lo1 lo2 lo3 ]; +attach variables [ achi acfhi ] [ hi hi1 hi2 hi3 ]; +attach variables [ ac acf ] [ ac0 ac1 ac2 ac3 ]; + +attach names hint [ + "load" "store" "hint2" "hint3" "load_streamed" "store_streamed" "load_retained" "store_retained" + "hint8" "hint9" "hint10" "hint11" "hint12" "hint13" "hint14" "hint15" + "hint16" "hint17" "hint18" "hint19" "hint20" "hint21" "hint22" "hint23" "hint24" + "writeback_invalidate" "hint26" "hint27" "hint28" "hint29" "PrepareForStore" "hint31" ]; + +attach variables [RTthread RDthread] [ + thread_zero thread_at thread_v0 thread_v1 thread_a0 thread_a1 thread_a2 thread_a3 + thread_t0 thread_t1 thread_t2 thread_t3 thread_t4 thread_t5 thread_t6 thread_t7 + thread_s0 thread_s1 thread_s2 thread_s3 thread_s4 thread_s5 thread_s6 thread_s7 + thread_t8 thread_t9 thread_k0 thread_k1 thread_gp thread_sp thread_s8 thread_ra +]; + +attach variables [ FTthread FDthread ] [ + thread_f0 thread_f1 thread_f2 thread_f3 thread_f4 thread_f5 thread_f6 thread_f7 + thread_f8 thread_f9 thread_f10 thread_f11 thread_f12 thread_f13 thread_f14 thread_f15 + thread_f16 thread_f17 thread_f18 thread_f19 thread_f20 thread_f21 thread_f22 thread_f23 + thread_f24 thread_f25 thread_f26 thread_f27 thread_f28 thread_f29 thread_f30 thread_f31 +]; + +attach variables [ rtmtdsp rdmtdsp ] [ + thread_lo0 thread_hi0 thread_acx0 _ thread_lo1 thread_hi1 thread_acx1 _ + thread_lo2 thread_hi2 thread_acx2 _ thread_lo3 thread_hi3 thread_acx3 _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ +]; + +attach variables [ FCTthread FCRthread ] [ + thread_fir _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + _ thread_fccr thread_fexr _ thread_fenr _ _ thread_fcsr +]; + +# Subconstructors +RD0: rd0_0 is rd0_0 & sel=0 { export rd0_0; } +RD0: rd0_1 is rd0_1 & sel=1 { export rd0_1; } +RD0: rd0_2 is rd0_2 & sel=2 { export rd0_2; } +RD0: rd0_3 is rd0_3 & sel=3 { export rd0_3; } +RD0: rd0_4 is rd0_4 & sel=4 { export rd0_4; } +RD0: rd0_5 is rd0_5 & sel=5 { export rd0_5; } +RD0: rd0_6 is rd0_6 & sel=6 { export rd0_6; } +RD0: rd0_7 is rd0_7 & sel=7 { export rd0_7; } + +RD: rd is rd { export rd; } +RDsrc: rd is rd { export rd; } +RDsrc: rd is rd & rd=0 { export 0:$(REGSIZE); } + +RS: rs is rs { export rs; } +RSsrc: rs is rs { export rs; } +RSsrc: rs is rs & rs=0 { export 0:$(REGSIZE); } + +RT: rt is rt { export rt; } +RTsrc: rt is rt { export rt; } +RTsrc: rt is rt & rt=0 { export 0:$(REGSIZE); } + +RD32: rd is rd & rd32 { export rd32; } +RS32src: rs is rs & rs32 { export rs32; } +RS32src: rs is rs & rs32=0 { export 0:4; } +RT32: rt is rt & rt32 { export rt32; } +RT32src: rt is rt & rt32 { export rt32; } +RT32src: rt is rt & rt32=0 { export 0:4; } + +@ifdef NEEDCAST +macro MemSrcCast(dest,src) { + dest = *(src:$(ADDRSIZE)); +} +macro MemDestCast(dest,src) { + *(dest:$(ADDRSIZE)) = src; +} +macro ValCast(dest,src) { + dest = src:$(ADDRSIZE); +} +@else +macro MemSrcCast(dest,src) { + dest = *(src); +} +macro MemDestCast(dest,src) { + *(dest) = src; +} +macro ValCast(dest,src) { + dest = src; +} +@endif + +OFF_BASE: simmed(base) is simmed & base { tmp:$(REGSIZE) = base + simmed; tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; } +INDEX_BASE: index(base) is index & base { tmp:$(REGSIZE) = base + index; tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; } + +OFF_BASER6: simmed(base) is REL6=0 & simmed & base { tmp:$(REGSIZE) = base + simmed; tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; } +OFF_BASER6: simmed9(base) is REL6=1 & simmed9 & base { tmp:$(REGSIZE) = base + simmed9; tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; } + +S18L3: val is simmed18 [ val = simmed18 << 3; ] { export *[const]:4 val; } +S19L2: val is simmed19 [ val = simmed19 << 2; ] { export *[const]:4 val; } +S16L16: val is simmed [ val = simmed << 16; ] { export *[const]:4 val; } +S16L32: val is simmed [ val = simmed << 32; ] { export *[const]:8 val; } +S16L48: val is simmed [ val = simmed << 48; ] { export *[const]:8 val; } +SAV: val is sa2 [ val = sa2+1; ] { export *[const]:1 val; } + +Rel16: reloc is off16 [ reloc=inst_start+4+4*off16; ] { export *:$(ADDRSIZE) reloc; } +Rel21: reloc is off21 [ reloc=inst_start+4+4*off21; ] { export *:$(ADDRSIZE) reloc; } +Rel26: reloc is off26 [ reloc=inst_start+4+4*off26; ] { export *:$(ADDRSIZE) reloc; } +Abs26: reloc is ind26 [ reloc=((inst_start+4) $and 0xfffffffff0000000) | 4*ind26; ] { export *:$(ADDRSIZE) reloc; } + +InsSize: mysize is msbd & lsb [ mysize = msbd - lsb + 1; ] { tmp:1 = mysize; export tmp; } +ExtSize: mysize is msbd [ mysize = msbd + 1; ] { tmp:1 = mysize; export tmp; } + +@ifdef MIPS64 +DextmSize: mysize is msbd [ mysize = msbd + 1 + 32; ] { tmp:1 = mysize; export tmp; } +DXuPos: pos is lsb [ pos = lsb + 32; ] { tmp:1 = pos; export tmp; } +DinsXSize: mysize is msbd & lsb [ mysize = msbd - lsb + 1 + 32; ] { tmp:1 = mysize; export tmp; } +@endif + +macro JXWritePC(addr) { +@ifdef ISA_VARIANT + ISAModeSwitch = (addr & 0x1) != 0; + tmp:$(REGSIZE) = -2; + tmp = tmp & addr; + pc = tmp; +@else + pc=addr; +@endif +} + +# Floating point formats +#fmt: "S" is format=0x10 { } +#fmt: "D" is format=0x11 { } +#fmt: "W" is format=0x14 { } +#fmt: "L" is format=0x15 { } +#fmt: "PS" is format=0x16 { } + +fmt1: "S" is format=0x10 { } +fmt1: "D" is format=0x11 { } +fmt1: "PS" is format=0x16 { } + +fmt2: "S" is format=0x10 { } +fmt2: "D" is format=0x11 { } + +fmt3: "S" is format=0x10 { } +fmt3: "W" is format=0x14 { } +fmt3: "L" is format=0x15 { } + +fmt4: "D" is format=0x11 { } +fmt4: "W" is format=0x14 { } +fmt4: "L" is format=0x15 { } + +fmt5: "S" is format1X=0x0 { } +fmt5: "D" is format1X=0x1 { } +fmt5: "PS" is format1X=0x6 { } + +# Release 6 and later: +fmt6: "S" is format=0x14 { } +fmt6: "D" is format=0x15 { } + +# Custom Pcode Operations +# +# To add a new pcodeop op that is implemented in Java code: +# +# In this directory: +# ./ghidra/Ghidra/Processors/MIPS/src/main/java/ghidra/program/emulation +# Edit this file to register a new Java method that implements the pcodeop: +# MIPSEmulateInstructionStateModifier.java +# (Be sure to also import the new class) +# +# The mips.pspec file must have this key set (this has already been done): +# +# +# Add the Java class file for the new pcodeop here: +# ./ghidra/Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/pcode/emulate/callother +# +define pcodeop break; +define pcodeop trap; +define pcodeop wait; +define pcodeop syscall; +define pcodeop cacheOp; +define pcodeop signalDebugBreakpointException; +define pcodeop disableInterrupts; +define pcodeop enableInterrupts; +define pcodeop hazzard; +define pcodeop lockload; +define pcodeop lockwrite; +define pcodeop synch; +define pcodeop tlbop; +define pcodeop bitSwap; +define pcodeop disableProcessor; +define pcodeop enableProcessor; +define pcodeop signalReservedInstruction; +define pcodeop TLB_invalidate; +define pcodeop TLB_invalidate_flush; +define pcodeop TLB_probe_for_matching_entry; +define pcodeop TLB_read_indexed_entryHi; +define pcodeop TLB_read_indexed_entryLo0; +define pcodeop TLB_read_indexed_entryLo1; +define pcodeop TLB_read_indexed_entryPageMask; +define pcodeop TLB_write_indexed_entry; +define pcodeop TLB_write_random_entry; + +# prefetch(vaddr, hint); +define pcodeop prefetch; + +# getFpCondition(cc) +define pcodeop getFpCondition; + +# getCopCondition(cop_num, cc) +define pcodeop getCopCondition; + +# setCopControlWord(cop_num, reg_num, value) +define pcodeop setCopControlWord; + +# getCopControlWord(cop_num, reg_num) +define pcodeop getCopControlWord; + +# copFunction(cop_num, func) +define pcodeop copFunction; + +# getCopReg(cop_num, reg_num) +define pcodeop getCopReg; +define pcodeop getCopRegH; + +# setCopReg(cop_num, reg_num, value) +define pcodeop setCopReg; +define pcodeop setCopRegH; + +# extractField(value, msbd, lsb) +define pcodeop extractField; + +# setShadow(sgpr, value) +define pcodeop setShadow; + +# getHWRegister(reg, sel) +define pcodeop getHWRegister; + +# gpr = getShadow(sgpr) +define pcodeop getShadow; diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips16.sinc b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips16.sinc new file mode 100644 index 0000000..5977d4d --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips16.sinc @@ -0,0 +1,761 @@ +################ +# +# MIPS16e +# +# From MIPS32 Architecture for PRogrammers Volume IV-a: +# The MIPS16e Application Specific Extension to the MIPS32 +# Architecture. +# +# Document #: MD00076 Rev 2.63 July 16, 2013 +# +################ + +define token m16instr (16) + m16_op=(11,15) + m16_i_imm=(0,4) + m16_rx=(8,10) + m16_rxa=(8,10) + m16_ri_imm=(0,4) + m16_ri_z=(5,7) + m16_ry=(5,7) + m16_rya=(5,7) + m16_rr_f=(0,4) + m16_rr_nd=(7,7) + m16_rr_l=(6,6) + m16_rr_ra=(5,5) + m16_rr_z=(5,7) + m16_rri_imm=(0,4) + m16_rz=(2,4) + m16_rza=(2,4) + m16_rrr_f=(0,1) + m16_rria_f=(4,4) + m16_rria_imm=(0,3) + m16_rria_simm=(0,3) signed + m16_shft_sa=(2,4) + m16_shft_f=(0,1) + m16_i8_f=(8,10) + m16_i8_imm=(0,4) + m16_is8_imm=(0,7) signed + m16_mv_rz=(0,2) + m16_mv_rza=(0,2) + m16_i8_rz=(5,7) + m16_i8_r32=(0,4) + m16_i8_r32a=(0,4) + m16_i8_r32_20=(5,7) + m16_i8_r32_43=(3,4) + m16_i8_svrs=(8,10) + m16_i8_sw=(8,10) + m16_iu8_imm=(0,7) + m16_b_imm=(0,4) + m16_b_z=(5,10) + m16_cb_z=(5,7) + m16_b_off=(0,10) signed + m16_cb_off=(0,7) signed + m16_svrs_s=(7,7) + m16_svrs_ra=(6,6) + m16_svrs_s0=(5,5) + m16_svrs_s1=(4,4) + m16_svrs_frame=(0,3) + m16_ext_val=(0,10) + m16_tgt_1500=(0,15) + m16_tgt_2521=(0,4) + m16_tgt_2016=(5,9) + m16_jal=(10,10) + m16_code=(5,10) +; + +attach variables [ m16_rx m16_ry m16_rz m16_mv_rz ] + [ s0 s1 v0 v1 a0 a1 a2 a3 ]; + +attach variables [ ext_m16r32 m16_i8_r32 ] [ + zero at v0 v1 a0 a1 a2 a3 + t0 t1 t2 t3 t4 t5 t6 t7 + s0 s1 s2 s3 s4 s5 s6 s7 + t8 t9 k0 k1 gp sp s8 ra +]; + +@ifdef MIPS64 +attach variables [ m16_rxa m16_rya m16_rza m16_mv_rza] + [ s0_lo s1_lo v0_lo v1_lo a0_lo a1_lo a2_lo a3_lo ]; + +attach variables [ ext_m16r32a m16_i8_r32a ] [ + zero_lo at_lo v0_lo v1_lo a0_lo a1_lo a2_lo a3_lo + t0_lo t1_lo t2_lo t3_lo t4_lo t5_lo t6_lo t7_lo + s0_lo s1_lo s2_lo s3_lo s4_lo s5_lo s6_lo s7_lo + t8_lo t9_lo k0_lo k1_lo gp_lo sp_lo s8_lo ra_lo +]; + +RZ: m16_rz is m16_rz { export m16_rz; } + +@else # !MIPS64 +attach variables [ m16_rxa m16_rya m16_rza m16_mv_rza ] + [ s0 s1 v0 v1 a0 a1 a2 a3 ]; + +attach variables [ ext_m16r32a m16_i8_r32a ] [ + zero at v0 v1 a0 a1 a2 a3 + t0 t1 t2 t3 t4 t5 t6 t7 + s0 s1 s2 s3 s4 s5 s6 s7 + t8 t9 k0 k1 gp sp s8 ra +]; + +RZ: is epsilon {} + +@endif # MIPS64 + +RX: m16_rx is m16_rx { export m16_rx; } +RX32: m16_rx is m16_rx & m16_rxa { export m16_rxa; } +RY32: m16_ry is m16_ry & m16_rya { export m16_rya; } +RZ32: m16_rz is m16_rz & m16_rza { export m16_rza; } + + +attach names [ ext_svrs_sreg][ + _ "s0" "s1" "s0-s1" + "s2" "s0,s2" "s1-s2" "s0-s2" + "s2-s3" "s0,s2-s3" "s1-s3" "s0-s3" + "s2-s4" "s0,s2-s4" "s1-s4" "s0-s4" + "s2-s5" "s0,s2-s5" "s1-s5" "s0-s5" + "s2-s6" "s0,s2-s6" "s1-s6" "s0-s6" + "s2-s7" "s0,s2-s7" "s1-s7" "s0-s7" + "s2-s8" "s0,s2-s8" "s1-s8" "s0-s8" +]; + +Abs26_m16: reloc is m16_tgt_1500 & ext_tgt_2016 & ext_tgt_2521 [ reloc=((inst_start+4) $and 0xfffffffff0000000)+4*(m16_tgt_1500 | (ext_tgt_2016 << 16) | (ext_tgt_2521 << 21)); ] { export *:$(ADDRSIZE) reloc; } +Rel16_m16: reloc is ext_is_ext=1 & m16_b_z=0 & m16_b_imm & ext_value_1005 & ext_value_1511s [ reloc=inst_start+4+2*((ext_value_1511s << 11) | (ext_value_1005 << 5) | m16_b_imm); ] { export *:$(ADDRSIZE) reloc; } +Rel16_m16: reloc is ext_is_ext=0 & m16_b_off [ reloc=inst_start+2+2*m16_b_off; ] { export *:$(ADDRSIZE) reloc; } + +CRel16_m16: reloc is ext_is_ext=1 & m16_cb_z=0 & m16_b_imm & ext_value_1005 & ext_value_1511s [ reloc=inst_start+4+2*((ext_value_1511s << 11) | (ext_value_1005 << 5) | m16_b_imm); ] { export *:$(ADDRSIZE) reloc; } +CRel16_m16: reloc is ext_is_ext=0 & m16_cb_off [ reloc=inst_start+2+2*m16_cb_off; ] { export *:$(ADDRSIZE) reloc; } + +:^instruction is ISA_MODE=1 & RELP=1 & m16_op=0b11110 & ext_done=0 & ext_isjal=0 & m16_ext_val; instruction [ext_value=m16_ext_val; ext_is_ext=1; ext_done=1; ] { build instruction; } +:^instruction is ISA_MODE=1 & RELP=1 & m16_op=0b00011 & ext_done=0 & ext_isjal=0 & m16_jal & m16_tgt_2016 & m16_tgt_2521; instruction [ext_tgt_2016=m16_tgt_2016; ext_tgt_2521=m16_tgt_2521; ext_tgt_x=m16_jal; ext_isjal=1; ext_done=1; ] { build instruction; } + +EXT_I: val is m16_i_imm [ val = m16_i_imm << 2; ] { export *[const]:2 val; } +EXT_IS0: val is m16_i_imm [ val = m16_i_imm << 0; ] { export *[const]:2 val; } +EXT_IS1: val is m16_i_imm [ val = m16_i_imm << 1; ] { export *[const]:2 val; } +EXT_RI: val is ext_value_1511 & ext_value_1005 & m16_ri_imm [val = (ext_value_1511 << 11) | (ext_value_1005 << 5) | m16_ri_imm; ] { export *[const]:2 val; } +EXT_RRIA: val is ext_is_ext=1 & ext_value_1411s & ext_value_1004 & m16_rria_imm [ val=(ext_value_1411s << 11) | (ext_value_1004 << 4) | m16_rria_imm; ] { export *[const]:2 val; } +EXT_RRIA: m16_rria_simm is ext_is_ext=0 & m16_rria_simm { export *[const]:2 m16_rria_simm; } + +EXT_IS8: val is ext_is_ext=1 & ext_value_1511s & ext_value_1005 & m16_i8_imm [val=(ext_value_1511s << 11) | (ext_value_1005 << 5) | m16_i8_imm; ] { export *[const]:2 val; } +EXT_IS8: m16_is8_imm is ext_is_ext=0 & m16_is8_imm { export *[const]:2 m16_is8_imm; } +EXT_IS8L3: val is ext_is_ext=0 & ext_value_1511 & ext_value_1005 & m16_is8_imm [val = m16_is8_imm << 3; ] { export *[const]:2 val; } + +EXT_IU8: val is ext_is_ext=1 & ext_value_1511 & ext_value_1005 & m16_i8_imm [val = (ext_value_1511 << 11) | (ext_value_1005 << 5) | m16_i8_imm; ] { export *[const]:2 val; } +EXT_IU8: val is ext_is_ext=0 & m16_iu8_imm [val = m16_iu8_imm << 2; ] { export *[const]:2 val; } + +EXT_LIU8: val is ext_is_ext=1 & m16_ri_z=0 & ext_value_1511 & ext_value_1005 & m16_i8_imm [val = (ext_value_1511 << 11) | (ext_value_1005 << 5) | m16_i8_imm; ] { export *[const]:2 val; } +EXT_LIU8: m16_iu8_imm is ext_is_ext=0 & m16_iu8_imm { export *[const]:2 m16_iu8_imm; } + +EXT_SHIFT: ext_value_sa40 is ext_is_ext=1 & ext_value_saz=0 & m16_shft_sa=0 & ext_value_sa40 { export *[const]:1 ext_value_sa40;} +EXT_SHIFT: val is ext_is_ext=0 & m16_shft_sa=0 [val = 8; ] { export *[const]:1 val;} +EXT_SHIFT: m16_shft_sa is ext_is_ext=0 & m16_shft_sa { export *[const]:1 m16_shft_sa;} + +EXT_SET: val is ext_is_ext=1 & m16_ri_z=0 & ext_value_1511 & ext_value_1005 & m16_i8_imm [val = (ext_value_1511 << 11) | (ext_value_1005 << 5) | m16_i8_imm; ] { export *[const]:4 val; } +EXT_SET: m16_iu8_imm is ext_is_ext=0 & m16_iu8_imm { export *[const]:4 m16_iu8_imm; } + +OFF_M16: EXT_IS8(m16_rx) is ext_is_ext=1 & EXT_IS8 & m16_rx { tmp:$(REGSIZE) = m16_rx + sext(EXT_IS8); tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; } +OFF_M16: EXT_I(m16_rx) is ext_is_ext=0 & EXT_I & m16_rx { tmp:$(REGSIZE) = m16_rx + zext(EXT_I); tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; } +OFF_M16S0: EXT_IS8(m16_rx) is ext_is_ext=1 & EXT_IS8 & m16_rx { tmp:$(REGSIZE) = m16_rx + sext(EXT_IS8); tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; } +OFF_M16S0: EXT_IS0(m16_rx) is ext_is_ext=0 & EXT_IS0 & m16_rx { tmp:$(REGSIZE) = m16_rx + zext(EXT_IS0); tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; } +OFF_M16S1: EXT_IS8(m16_rx) is ext_is_ext=1 & EXT_IS8 & m16_rx { tmp:$(REGSIZE) = m16_rx + sext(EXT_IS8); tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; } +OFF_M16S1: EXT_IS1(m16_rx) is ext_is_ext=0 & EXT_IS1 & m16_rx { tmp:$(REGSIZE) = m16_rx + zext(EXT_IS1); tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; } + +OFF_M16PC: EXT_IS8(pc) is ext_is_ext=1 & m16_i8_rz=0 & EXT_IS8 & pc { tmp:$(REGSIZE) = (inst_start + sext(EXT_IS8)) & 0xFFFFFFFC; tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; } +OFF_M16PC: val(pc) is ext_is_ext=0 & m16_iu8_imm & pc & ext_delay [ val = m16_iu8_imm << 2; ] { tmp:$(REGSIZE) = (inst_start + val - (ext_delay << 1)) & 0xFFFFFFFC; tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; } + +OFF_M16SP: EXT_IS8(sp) is ext_is_ext=1 & m16_i8_rz=0 & EXT_IS8 & sp { tmp:$(REGSIZE) = sp + sext(EXT_IS8); tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; } +OFF_M16SP: val(sp) is ext_is_ext=0 & m16_iu8_imm & sp [ val = m16_iu8_imm << 2; ] { tmp:$(REGSIZE) = sp + val; tmpscaled:$(ADDRSIZE) = 0; ValCast(tmpscaled,tmp); export tmpscaled; } + +EXT_FRAME: val is ext_value_frame=0 & m16_svrs_frame=0 [val = 128; ] {export *[const]:2 val;} +EXT_FRAME: val is ext_value_frame & m16_svrs_frame [val = ((ext_value_frame << 4) | m16_svrs_frame) << 3;] {export *[const]:2 val;} + +REGRS_STAT: is ext_value_areg {} +REGRS_STAT: ",a3" is (ext_value_areg=1 | ext_value_areg=5 | ext_value_areg=9 |ext_value_areg=0xd) { + tsp = tsp-4; + MemSrcCast(a3,tsp); +} +REGRS_STAT: ",a2-a3" is (ext_value_areg=2 | ext_value_areg=6 | ext_value_areg=0xa) { + tsp = tsp-4; + MemSrcCast(a3,tsp); + tsp = tsp-4; + MemSrcCast(a2,tsp); +} +REGRS_STAT: ",a1-a3" is (ext_value_areg=3 | ext_value_areg=7) { + tsp = tsp-4; + MemSrcCast(a3,tsp); + tsp = tsp-4; + MemSrcCast(a2,tsp); + tsp = tsp-4; + MemSrcCast(a1,tsp); +} +REGRS_STAT: ",a0-a3" is ext_value_areg=0xB { + tsp = tsp-4; + MemSrcCast(a3,tsp); + tsp = tsp-4; + MemSrcCast(a2,tsp); + tsp = tsp-4; + MemSrcCast(a1,tsp); + tsp = tsp-4; + MemSrcCast(a0,tsp); +} + +REST_STAT: is ext_value_areg=0 | ext_value_areg=4 | ext_value_areg=8 | ext_value_areg=0xc | ext_value_areg=0xe {} +REST_STAT: REGRS_STAT is REGRS_STAT { + build REGRS_STAT; +} + + +REGSV_STAT: is ext_value_areg {} +REGSV_STAT: ",a3" is (ext_value_areg=1 | ext_value_areg=5 | ext_value_areg=9 | ext_value_areg=0xd) { + tsp = tsp-4; + MemDestCast(tsp,a3); +} +REGSV_STAT: ",a2-a3" is (ext_value_areg=2 | ext_value_areg=6 | ext_value_areg=0xa) { + tsp = tsp-4; + MemDestCast(tsp,a3); + tsp = tsp-4; + MemDestCast(tsp,a2); +} +REGSV_STAT: ",a1-a3" is (ext_value_areg=3 | ext_value_areg=7) { + tsp = tsp-4; + MemDestCast(tsp,a3); + tsp = tsp-4; + MemDestCast(tsp,a2); + tsp = tsp-4; + MemDestCast(tsp,a1); +} +REGSV_STAT: ",a0-a3" is ext_value_areg=0xb { + tsp = tsp-4; + MemDestCast(tsp,a3); + tsp = tsp-4; + MemDestCast(tsp,a2); + tsp = tsp-4; + MemDestCast(tsp,a1); + tsp = tsp-4; + MemDestCast(tsp,a0); +} + +SAVE_STAT: is ext_value_areg=0 | ext_value_areg=4 | ext_value_areg=8 | ext_value_areg=0xc | ext_value_areg=0xe {} +SAVE_STAT: REGSV_STAT is REGSV_STAT { + build REGSV_STAT; +} + +REGSV_BLD1: is ext_value_b2=0 {} +REGSV_BLD1: "a0," is ext_value_b2=1 { + ptr:$(REGSIZE) = sp; + MemDestCast(ptr,a0); +} + +REGSV_BLD2: REGSV_BLD1 is REGSV_BLD1 { build REGSV_BLD1; } +REGSV_BLD2: "a0-a1," is ext_value_b3=1 & ext_value_b2=0 & (ext_value_b1=0 | ext_value_b0=0) { + ptr:$(REGSIZE) = sp; + MemDestCast(ptr,a0); + ptr = sp+4; + MemDestCast(ptr,a1); +} + +REGSV_BLD3: REGSV_BLD2 is REGSV_BLD2 { build REGSV_BLD2; } +REGSV_BLD3: "a0-a2," is ext_value_b3=1 & ext_value_b2=1 & ext_value_b1=0 { + ptr:$(REGSIZE) = sp; + MemDestCast(ptr,a0); + ptr = sp+4; + MemDestCast(ptr,a1); + ptr = sp+8; + MemDestCast(ptr,a2); +} + +REGSV_BLD4: REGSV_BLD3 is REGSV_BLD3 { build REGSV_BLD3; } +REGSV_BLD4: "a0-a3," is ext_value_areg=0b1110 { + ptr:$(REGSIZE) = sp; + MemDestCast(ptr,a0); + ptr = sp+4; + MemDestCast(ptr,a1); + ptr = sp+8; + MemDestCast(ptr,a2); + ptr = sp+12; + MemDestCast(ptr,a3); +} + +SAVE_ARG: is ext_value_areg=0 | ext_value_areg=1 | ext_value_areg=2 | ext_value_areg=3 | ext_value_areg=0xb | ext_value_areg=0xf {} +SAVE_ARG: REGSV_BLD4 is REGSV_BLD4 { + build REGSV_BLD4; +} + +REGRS_S0: is m16_svrs_s0 {} +REGRS_S0: is m16_svrs_s0=1 { tsp = tsp-$(REGSIZE); MemSrcCast(s0,tsp); } + +REGRS_S1: is m16_svrs_s1 {} +REGRS_S1: is m16_svrs_s1=1 { tsp = tsp-$(REGSIZE); MemSrcCast(s1,tsp); } + +REGRS_S8: is ext_value_xreg=6 {} +REGRS_S8: is ext_value_xreg { tsp = tsp-$(REGSIZE); MemSrcCast(s8,tsp); } + +REGRS_S7: is ext_value_xreg=5 {} +REGRS_S7: is REGRS_S8 { build REGRS_S8; tsp = tsp-$(REGSIZE); MemSrcCast(s7,tsp); } + +REGRS_S6: is ext_value_xreg=4 {} +REGRS_S6: is REGRS_S7 { build REGRS_S7; tsp = tsp-$(REGSIZE); MemSrcCast(s6,tsp); } + +REGRS_S5: is ext_value_xreg=3 {} +REGRS_S5: is REGRS_S6 { build REGRS_S6; tsp = tsp-$(REGSIZE); MemSrcCast(s5,tsp); } + +REGRS_S4: is ext_value_xreg=2 {} +REGRS_S4: is REGRS_S5 { build REGRS_S5; tsp = tsp-$(REGSIZE); MemSrcCast(s4,tsp); } + +REGRS_S3: is ext_value_xreg=1 {} +REGRS_S3: is REGRS_S4 { build REGRS_S4; tsp = tsp-$(REGSIZE); MemSrcCast(s3,tsp); } + +REGRS_S2: is ext_value_xreg=0 {} +REGRS_S2: is REGRS_S3 { build REGRS_S3; tsp = tsp-$(REGSIZE); MemSrcCast(s2,tsp); } + +REST_SREG: is m16_svrs_s0=0 & m16_svrs_s1=0 & ext_value_xreg=0 {} +REST_SREG: ","ext_svrs_sreg is m16_svrs_s0 & m16_svrs_s1 & ext_value_xreg & ext_svrs_sreg & REGRS_S0 & REGRS_S1 & REGRS_S2 + [ext_svrs_s0=m16_svrs_s0;ext_svrs_s1=m16_svrs_s1;ext_svrs_xs=ext_value_xreg;] { + build REGRS_S2; + build REGRS_S1; + build REGRS_S0; +} + +REGSV_S0: is m16_svrs_s0 {} +REGSV_S0: is m16_svrs_s0=1 { tsp = tsp-$(REGSIZE); MemDestCast(tsp,s0);} + +REGSV_S1: is m16_svrs_s1 {} +REGSV_S1: is m16_svrs_s1=1 { tsp = tsp-$(REGSIZE); MemDestCast(tsp,s1); } + +REGSV_S8: is ext_value_xreg=6 {} +REGSV_S8: is ext_value_xreg { tsp = tsp-$(REGSIZE); MemDestCast(tsp,s8); } + +REGSV_S7: is ext_value_xreg=5 {} +REGSV_S7: is REGSV_S8 { build REGSV_S8; tsp = tsp-$(REGSIZE); MemDestCast(tsp,s7); } + +REGSV_S6: is ext_value_xreg=4 {} +REGSV_S6: is REGSV_S7 { build REGSV_S7; tsp = tsp-$(REGSIZE); MemDestCast(tsp,s6); } + +REGSV_S5: is ext_value_xreg=3 {} +REGSV_S5: is REGSV_S6 { build REGSV_S6; tsp = tsp-$(REGSIZE); MemDestCast(tsp,s5); } + +REGSV_S4: is ext_value_xreg=2 {} +REGSV_S4: is REGSV_S5 { build REGSV_S5; tsp = tsp-$(REGSIZE); MemDestCast(tsp,s4); } + +REGSV_S3: is ext_value_xreg=1 {} +REGSV_S3: is REGSV_S4 { build REGSV_S4; tsp = tsp-$(REGSIZE); MemDestCast(tsp,s3); } + +REGSV_S2: is ext_value_xreg=0 {} +REGSV_S2: is REGSV_S3 { build REGSV_S3; tsp = tsp-$(REGSIZE); MemDestCast(tsp,s2); } + +SAVE_SREG: is m16_svrs_s0=0 & m16_svrs_s1=0 & ext_value_xreg=0 {} +SAVE_SREG: ","ext_svrs_sreg is m16_svrs_s0 & m16_svrs_s1 & ext_value_xreg & ext_svrs_sreg & REGSV_S0 & REGSV_S1 & REGSV_S2 + [ext_svrs_s0=m16_svrs_s0;ext_svrs_s1=m16_svrs_s1;ext_svrs_xs=ext_value_xreg;] { + build REGSV_S2; + build REGSV_S1; + build REGSV_S0; +} + +REST_RA: is m16_svrs_ra=0 {} +REST_RA: ",ra" is m16_svrs_ra=1 { + tsp = tsp-$(REGSIZE); + MemSrcCast(ra,tsp); +} + +SAVE_RA: is m16_svrs_ra=0 {} +SAVE_RA: ",ra" is m16_svrs_ra=1 { + tsp = tsp-$(REGSIZE); + MemDestCast(tsp,ra); +} + +REST_TOP: EXT_FRAME^REST_RA^REST_SREG^REST_STAT is EXT_FRAME & REST_RA & REST_SREG & REST_STAT { + build EXT_FRAME; + + tmp:2 = EXT_FRAME; + tsp = sp+zext(tmp); + + build REST_RA; + build REST_SREG; + build REST_STAT; + + sp = sp+zext(tmp); +} + +SAVE_TOP: SAVE_ARG^EXT_FRAME^SAVE_RA^SAVE_SREG^SAVE_STAT is EXT_FRAME & SAVE_RA & SAVE_SREG & SAVE_ARG & SAVE_STAT { + tsp = sp; + + build SAVE_ARG; + build SAVE_RA; + build SAVE_SREG; + build SAVE_STAT; + build EXT_FRAME; + + tmp:2 = EXT_FRAME; + sp = sp - zext(tmp); +} + +# The non-extended PC relative clears the lower 2 bits *after* the add. +# The extended version clears the lower 2 bits *before* the add. The difference in how they do it is correct +:addiu RX32, pc, EXT_IU8 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b00001 & ext_is_ext=0 & RX32 & EXT_IU8 & pc & ext_delay & RX { + tmp:4 = zext(EXT_IU8); + tmpa:4 = ext_delay; + RX32 = (inst_start + tmp - (tmpa << 1)) & 0xFFFFFFFC; +@ifdef MIPS64 + RX = sext(RX32); +@endif +} +:addiu RX32, pc, EXT_IS8 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b00001 & ext_is_ext=1 & RX32 & EXT_IS8 & pc & RX { + tmp:4 = sext(EXT_IS8); + RX32 = (inst_start & 0xFFFFFFFC) + tmp; +@ifdef MIPS64 + RX = sext(RX32); +@endif +} + +:addiu RX32, EXT_IS8 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01001 & RX32 & EXT_IS8 & RX { + tmp:4 = sext(EXT_IS8); + RX32 = RX32 + tmp; +@ifdef MIPS64 + RX = sext(RX32); +@endif +} + +:addiu RY32, RX32, EXT_RRIA is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01000 & m16_rria_f=0 & RX32 & RY32 & EXT_RRIA & RX { + tmp:4 = sext(EXT_RRIA); + RY32 = RX32 + tmp; +@ifdef MIPS64 + RX = sext(RX32); +@endif +} + +:addiu sp, EXT_IS8L3 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01100 & m16_i8_f=0b011 & ext_is_ext=0 & sp & EXT_IS8L3 { + tmp:$(REGSIZE) = sext(EXT_IS8L3); + sp = sp + tmp; +} + +:addiu sp, EXT_IS8 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01100 & m16_i8_f=0b011 & ext_is_ext=1 & sp & EXT_IS8 { + tmp:$(REGSIZE) = sext(EXT_IS8); + sp = sp + tmp; +} + +:addiu RX32, sp, EXT_IU8 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b00000 & ext_is_ext=0 & sp & RX32 & EXT_IU8 & RX { + tmp:4 = zext(EXT_IU8); + RX32 = sp:4 + tmp; +@ifdef MIPS64 + RX = sext(RX32); +@endif +} + +:addiu RX32, sp, EXT_IS8 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b00000 & ext_is_ext=1 & sp & RX32 & EXT_IS8 & RX { + tmp:4 = sext(EXT_IS8); + RX32 = sp:4 + tmp; +@ifdef MIPS64 + RX = sext(RX32); +@endif +} + +:addu RZ32, RX32, RY32 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=0 & m16_op=0b11100 & m16_rrr_f=0b01 & RX32 & RY32 & RZ32 & RZ { + RZ32 = RX32 + RY32; +@ifdef MIPS64 + RZ = sext(RZ32); +@endif +} + +:and m16_rx, m16_ry is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b01100 & m16_rx & m16_ry { + m16_rx = m16_rx & m16_ry; +} + +:asmacro ext_value_select is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & m16_op=0b11100 & ext_value_select { +} + +:b Rel16_m16 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b00010 & Rel16_m16 { + goto Rel16_m16; +} + +:beqz RX32, CRel16_m16 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b00100 & RX32 & CRel16_m16 { + if (RX32 == 0) goto CRel16_m16; +} + +:bnez RX32, CRel16_m16 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b00101 & RX32 & CRel16_m16 { + if (RX32 != 0) goto CRel16_m16; +} + +:break m16_code is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b00101 & m16_code { + tmp:4=m16_code; + trap(tmp); +} + +:bteqz CRel16_m16 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01100 & m16_i8_f=0b000 & CRel16_m16 { + if (t8 == 0) goto CRel16_m16; +} + +:btnez CRel16_m16 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01100 & m16_i8_f=0b001 & CRel16_m16 { + if (t8 != 0) goto CRel16_m16; +} + +:cmp m16_rx, m16_ry is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b01010 & m16_rx & m16_ry { + t8 = m16_rx ^ m16_ry; +} + +:cmpi m16_rx, m16_iu8_imm is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01110 & ext_is_ext=0 & m16_rx & m16_iu8_imm { + tmpa:1 = m16_iu8_imm; + tmp:$(REGSIZE) = zext(tmpa); + t8 = m16_rx ^ tmp; +} + +:cmpi m16_rx, EXT_RI is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01110 & ext_is_ext=1 & m16_rx & EXT_RI { + tmp:$(REGSIZE) = zext(EXT_RI); + t8 = m16_rx ^ tmp; +} + +:div RX32, RY32 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b11010 & RX32 & RY32 { + if (RY32 == 0) goto ; + lo = sext(RX32 s/ RY32); + hi = sext(RX32 s% RY32); + +} + +:divu RX32, RY32 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b11011 & RX32 & RY32 { + if (RY32 == 0) goto ; + lo = sext(RX32 / RY32); + hi = sext(RX32 % RY32); + +} + +:jal Abs26_m16 is ISA_MODE=1 & RELP=1 & ext_isjal=1 & ext_tgt_x=0 & Abs26_m16 [ ext_delay=0b10; globalset(inst_next, ext_delay);] { + ra = inst_next | 0x1; + delayslot( 1 ); + call Abs26_m16; + #double check gpr31 bit +} + +:jalr m16_rx is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_nd=0 & m16_rr_l=1 & m16_rr_ra=0 & m16_rr_f=0b00000 & m16_rx [globalset(inst_next, ext_delay);] { + JXWritePC(m16_rx); + ra = inst_next | 0x1; + delayslot( 1 ); + call [pc]; +} + +:jalrc m16_rx is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_nd=1 & m16_rr_l=1 & m16_rr_ra=0 & m16_rr_f=0b00000 & m16_rx { + JXWritePC(m16_rx); + ra = inst_next | 0x1; + call [pc]; +} + +:jalx Abs26_m16 is ISA_MODE=1 & RELP=1 & ext_isjal=1 & ext_tgt_x=1 & Abs26_m16 [ ISA_MODE = 0; globalset(Abs26_m16, ISA_MODE); + globalset(inst_next, ext_delay); ] { + ra = inst_next | 0x1; + delayslot( 1 ); + ISAModeSwitch = 0; + call Abs26_m16; +} + +:jr ra is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_nd=0 & m16_rr_l=0 & m16_rr_ra=1 & ra & m16_rr_f=0b00000 & m16_rx=0 [globalset(inst_next, ext_delay);] { + JXWritePC(ra); + delayslot( 1 ); + return [pc]; +} + +:jr m16_rx is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_nd=0 & m16_rr_l=0 & m16_rr_ra=0 & m16_rr_f=0b00000 & m16_rx [globalset(inst_next, ext_delay);] { + JXWritePC(m16_rx); + delayslot( 1 ); + goto [pc]; +} + +:jrc ra is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_nd=1 & m16_rr_l=0 & m16_rr_ra=1 & ra & m16_rr_f=0b00000 & m16_rx=0 { + JXWritePC(ra); + return [pc]; +} + +:jrc m16_rx is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_nd=1 & m16_rr_l=0 & m16_rr_ra=0 & m16_rr_f=0b00000 & m16_rx { + JXWritePC(m16_rx); + goto [pc]; +} + +:lb m16_ry, OFF_M16S0 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b10000 & m16_ry & OFF_M16S0 { + m16_ry = sext(*[ram]:1 OFF_M16S0); +} + +:lbu m16_ry, OFF_M16S0 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b10100 & m16_ry & OFF_M16S0 { + m16_ry = zext(*[ram]:1 OFF_M16S0); +} + +:lh m16_ry, OFF_M16S1 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b10001 & m16_ry & OFF_M16S1 { + m16_ry = sext(*[ram]:2 OFF_M16S1); +} + +:lhu m16_ry, OFF_M16S1 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b10101 & m16_ry & OFF_M16S1 { + m16_ry = zext(*[ram]:2 OFF_M16S1); +} + +:li m16_rx, EXT_LIU8 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01101 & m16_rx & EXT_LIU8 { + m16_rx = zext(EXT_LIU8); +} + +:lw m16_ry, OFF_M16 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b10011 & m16_ry & OFF_M16 { + m16_ry = sext(*[ram]:4 OFF_M16); +} + +:lw m16_rx, OFF_M16PC is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b10110 & m16_rx & OFF_M16PC & ext_delay { + m16_rx = sext(*[ram]:4 OFF_M16PC); +} + +:lw m16_rx, OFF_M16SP is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b10010 & m16_rx & OFF_M16SP { + m16_rx = sext(*[ram]:4 OFF_M16SP); +} + +:mfhi m16_rx is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b10000 & m16_rr_z=0 & m16_rx { + m16_rx = hi; +} + +:mflo m16_rx is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b10010 & m16_rr_z=0 & m16_rx { + m16_rx = lo; +} + +:move ext_m16r32, m16_mv_rz is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01100 & m16_i8_f=0b101 & ext_m16r32 & m16_mv_rz & m16_i8_r32_20 & m16_i8_r32_43 [ ext_reg_low = m16_i8_r32_20; ext_reg_high = m16_i8_r32_43 ; ] { + ext_m16r32 = m16_mv_rz; +} + +:move m16_ry, m16_i8_r32 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01100 & m16_i8_f=0b111 & m16_ry & m16_i8_r32 { + m16_ry = m16_i8_r32; +} + +:mult RX32, RY32 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b11000 & RX32 & RY32 { + tmp1:8 = sext( RX32 ); + tmp2:8 = sext( RY32 ); + prod:8 = tmp1 * tmp2; + lo = sext(prod:4); + prod = prod >> 32; + hi = sext(prod:4); +} + +:multu RX32, RY32 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b11001 & RX32 & RY32 { + tmp1:8 = zext( RX32 ); + tmp2:8 = zext( RY32 ); + prod:8 = tmp1 * tmp2; + lo = sext(prod:4); + prod = prod >> 32; + hi = sext(prod:4); +} + +:neg RX, RY32 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b01011 & RX & RY32 { + RX = sext(0-RY32); +} + +:not m16_rx, m16_ry is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b01111 & m16_rx & m16_ry { + m16_rx = ~m16_ry; +} + +# nop is technically a special case of a move instruction that moves 0 to 0 +:nop is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01100 & m16_i8_f=0b101 & m16_i8_imm=0 & m16_ri_z=0 {} + +:or m16_rx, m16_ry is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b01101 & m16_rx & m16_ry { + m16_rx = m16_rx | m16_ry; +} + + +# save/restore argument format +#,,,, +:restore REST_TOP is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01100 & m16_i8_f=0b100 & m16_svrs_s=0 & REST_TOP { + build REST_TOP; +} + +:save SAVE_TOP is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01100 & m16_i8_f=0b100 & m16_svrs_s=1 & SAVE_TOP { + build SAVE_TOP; +} + +:sb RY32, OFF_M16S0 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11000 & RY32 & OFF_M16S0 { + *[ram]:1 OFF_M16S0 = RY32:1; +} + +:sdbbp m16_code is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b00001 & m16_code { + signalDebugBreakpointException(); +} + +:seb m16_rx is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b10001 & m16_rr_z=0b100 & m16_rx { + tmp:1 = m16_rx:1; + tmpb:$(REGSIZE) = sext(tmp); + m16_rx = tmpb; +} + +:seh m16_rx is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b10001 & m16_rr_z=0b101 & m16_rx { + tmp:2 = m16_rx:2; + tmpb:$(REGSIZE) = sext(tmp); + m16_rx = tmpb; +} + +:sh m16_ry, OFF_M16S1 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11001 & m16_ry & OFF_M16S1 { + *[ram]:2 OFF_M16S1 = m16_ry:2; +} + +:sll m16_rx, m16_ry, EXT_SHIFT is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b00110 & m16_shft_f=0b00 & m16_rx & m16_ry & EXT_SHIFT { + m16_rx = m16_ry << EXT_SHIFT; +} + +:sllv m16_ry, m16_rx is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b00100 & m16_rx & m16_ry { + m16_ry = m16_ry << (m16_rx & 0x1f); +} + +:slt m16_rx, m16_ry is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b00010 & m16_rx & m16_ry { + t8 = zext( m16_rx s< m16_ry ); +} + +:slti m16_rx, EXT_SET is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01010 & m16_rx & EXT_SET { + tmpa:4 = EXT_SET; + tmp:$(REGSIZE) = sext(tmpa); + t8 = zext( m16_rx s< tmp); +} + +:sltiu m16_rx, EXT_SET is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01011 & m16_rx & EXT_SET { + tmpa:4 = EXT_SET; + tmp:$(REGSIZE) = sext(tmpa); + t8 = zext( m16_rx < tmp); +} + +:sltu m16_rx, m16_ry is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b00011 & m16_rx & m16_ry { + t8 = zext( m16_rx < m16_ry ); +} + +:sra m16_rx, m16_ry, EXT_SHIFT is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b00110 & m16_shft_f=0b11 & m16_rx & m16_ry & EXT_SHIFT { + m16_rx = m16_ry s>> EXT_SHIFT; +} + +:srav m16_ry, m16_rx is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b00111 & m16_rx & m16_ry { + m16_ry = m16_ry s>> (m16_rx & 0x1f); +} + +:srl m16_rx, m16_ry, EXT_SHIFT is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b00110 & m16_shft_f=0b10 & m16_rx & m16_ry & EXT_SHIFT { + m16_rx = m16_ry >> EXT_SHIFT; +} + +:srlv m16_ry, m16_rx is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b00110 & m16_rx & m16_ry { + m16_ry = m16_ry >> (m16_rx & 0x1f); +} + +:subu RZ32, RX32, RY32 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=0 & m16_op=0b11100 & m16_rrr_f=0b11 & RX32 & RY32 & RZ32 & RZ { + RZ32 = RX32 - RY32; +@ifdef MIPS64 + RZ = sext(RZ32); +@endif +} + +:sw m16_ry, OFF_M16 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11011 & m16_ry & OFF_M16 { + *[ram]:4 OFF_M16 = m16_ry:4; +} + +:sw m16_rx, OFF_M16SP is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11010 & m16_rx & OFF_M16SP { + *[ram]:4 OFF_M16SP = m16_rx:4; +} + +:sw ra, OFF_M16SP is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01100 & m16_i8_sw=0b010 & ra & OFF_M16SP { + *[ram]:4 OFF_M16SP = ra:4; +} + +:xor m16_rx, m16_ry is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_f=0b01110 & m16_rx & m16_ry { + m16_rx = m16_rx ^ m16_ry; +} + +:zeb m16_rx is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_z=0b000 & m16_rr_f=0b10001 & m16_rx { + tmp:1 = m16_rx:1; + m16_rx = zext(tmp); +} + +:zeh m16_rx is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b11101 & m16_rr_z=0b001 & m16_rr_f=0b10001 & m16_rx { + tmp:2 = m16_rx:2; + m16_rx = zext(tmp); +} diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32.pspec b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32.pspec new file mode 100644 index 0000000..f4cb53e --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32.pspec @@ -0,0 +1,78 @@ + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32Instructions.sinc b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32Instructions.sinc new file mode 100644 index 0000000..2b8577f --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32Instructions.sinc @@ -0,0 +1,1744 @@ +############################ +# +# MIPS32 +# Basic and FP (COP1) instructions +# +# (See bottom of file for MIPS64 instructions included with MIPS32) +# +############################ + +@if defined(ISA_VARIANT) +@define AMODE "ISA_MODE=0" # ISA_MODE must restrict MIPS instruction decoding and require ISA_MODE=0 +@else +@define AMODE "epsilon" # Mips16 instructions not supported - Mips32 only +@endif + +# 0000 00ss ssst tttt dddd d000 0010 0000 +:add RD32, RS32src, RT32src is $(AMODE) & prime=0 & sa=0 & fct=0x20 & RD32 & RS32src & RT32src & RD { + RD32 = RS32src + RT32src; +@ifdef MIPS64 + RD = sext(RD32); +@endif +} + +# 0010 01ss ssst tttt iiii iiii iiii iiii +:addiu RT32, RS32src, simmed is $(AMODE) & prime=9 & RT32 & RS32src & simmed & RT { + RT32 = RS32src + simmed; +@ifdef MIPS64 + RT = sext(RT32); +@endif +} + +# 0000 00ss ssst tttt dddd d000 0010 0001 +:addu RD32, RS32src, RT32src is $(AMODE) & prime=0 & fct=0x21 & RS32src & RT32src & RD32 & sa=0 & RD { + RD32 = RS32src + RT32src; +@ifdef MIPS64 + RD = sext(RD32); +@endif +} + +# 0000 00ss ssst tttt dddd d000 0010 0100 +:and RD, RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x24 & RSsrc & RTsrc & RD & sa=0 { + RD = RSsrc & RTsrc; +} + +# 0011 00ss ssst tttt iiii iiii iiii iiii +:andi RT, RSsrc, immed is $(AMODE) & prime=0xC & RSsrc & RT & immed { + RT = RSsrc & immed; +} + +# 0001 0000 0000 0000 iiii iiii iiii iiii +:b Rel16 is $(AMODE) & prime=4 & rs=0 & rt=0 & Rel16 { + delayslot(1); + goto Rel16; +} + +# 0001 00ss ssst tttt iiii iiii iiii iiii +:beq RSsrc, RTsrc, Rel16 is $(AMODE) & prime=4 & RSsrc & RTsrc & Rel16 { + delayflag:1 = ( RSsrc == RTsrc ); + delayslot( 1 ); + if delayflag goto Rel16; +} + +# 0000 01ss sss0 0001 iiii iiii iiii iiii +:bgez RSsrc, Rel16 is $(AMODE) & prime=1 & cond=1 & RSsrc & Rel16 { + delayflag:1 = ( RSsrc s>= 0 ); + delayslot( 1 ); + if delayflag goto Rel16; +} +# 0001 11ss sss0 0000 iiii iiii iiii iiii +:bgtz RSsrc, Rel16 is $(AMODE) & prime=7 & cond=0 & RSsrc & Rel16 { + delayflag:1 = ( RSsrc s> 0 ); + delayslot( 1 ); + if delayflag goto Rel16; +} +# 0001 10ss sss0 0000 iiii iiii iiii iiii +:blez RSsrc, Rel16 is $(AMODE) & prime=6 & cond=0 & RSsrc & Rel16 { + delayflag:1 = ( RSsrc s<= 0 ); + delayslot( 1 ); + if delayflag goto Rel16; +} + +# 0000 01ss sss0 0000 iiii iiii iiii iiii +:bltz RSsrc, Rel16 is $(AMODE) & prime=1 & cond=0 & RSsrc & Rel16 { + delayflag:1 = ( RSsrc s< 0 ); + delayslot( 1 ); + if delayflag goto Rel16; +} +# 0001 01ss ssst tttt iiii iiii iiii iiii +:bne RSsrc, RTsrc, Rel16 is $(AMODE) & prime=5 & RSsrc & RTsrc & Rel16 { + delayflag:1 = ( RSsrc != RTsrc ); + delayslot( 1 ); + if delayflag goto Rel16; +} + +# 0000 00cc cccc cccc cccc cccc cc00 1101 +:break breakcode is $(AMODE) & prime=0 & fct=0xD & breakcode { + tmp:4=breakcode; + trap(tmp); +} + +# 1011 11bb bbbo oooo iiii iiii iiii iiii +:cache op, OFF_BASER6 is $(AMODE) & ((prime=0x2F & REL6=0) | (prime=0x1F & REL6=1 & fct=0x25 & bit6=0)) & OFF_BASER6 & op { + cacheOp(op:1, OFF_BASER6); +} + +:cachee op, OFF_BASER6 is $(AMODE) & prime=0x1F & fct=0x1B & bit6=0 & OFF_BASER6 & op { + cacheOp(op:1, OFF_BASER6); +} + +:cfc0 RT, RD0 is $(AMODE) & prime=0x10 & copop=2 & RT & RD0 & bigfunct=0 { + RT = sext( RD0:$(SIZETO4) ); +} + +# 0100 1000 010t tttt ssss s000 0000 0000 +:cfc2 RT, immed is $(AMODE) & prime=0x12 & copop=2 & RT & immed { + tmp:4 = getCopControlWord( 2:1, immed:4 ); + RT = sext(tmp); +} + +# Special case of ADDU +# 0000 0000 0000 0000 dddd d000 0010 0001 +:clear RD is $(AMODE) & prime=0 & fct=0x21 & rs=0 & rt=0 & RD & sa=0 { + RD = 0; +} + +define pcodeop special2; + +# 0111 00ss ssst tttt dddd daaa aaxx xyyy +# valid values of x and y: +# x: 0 y: 3,6,7 +# x: 1 y: 0-7 +# x: 2 y: 0-7 +# x: 3 y: 0-7 +# x: 4 y: 2,3,6,7 +# x: 5 y: 0-7 +# x: 6 y: 0-7 +# x: 7 y: 0-6 +:SPECIAL2 RD, RSsrc, RTsrc, sa, fct is $(AMODE) & prime=0x1C & sa & RD & RSsrc & RTsrc & fct { + tmp:1 = fct; + tmp2:1 = sa; + RD = special2(RSsrc, RTsrc, tmp2, tmp); +} + +# 0100 101c cccc cccc cccc cccc cccc cccc +:cop2 cofun is $(AMODE) & prime=0x12 & bit25=1 & cofun { + arg:4 = cofun; + copFunction(2:1, arg); +} + +:ctc0 RTsrc, RD0 is $(AMODE) & prime=0x10 & copop=6 & RTsrc & RD0 & bigfunct=0 { + RD0 = RTsrc; +} +# 0100 1000 110t tttt iiii iiii iiii iiii +:ctc2 RTsrc, immed is $(AMODE) & prime=0x12 & copop=6 & RTsrc & immed { + setCopControlWord( 2:1, immed:4, RTsrc ); +} + +# 0100 0010 0000 0000 0000 0000 0001 1111 +:deret is $(AMODE) & prime=0x10 & bit25=1 & copfill=0x0 & fct=0x1F { + return[DEPC]; +} + +# 0100 0001 011t tttt 0110 0000 0000 0000 +:di is $(AMODE) & prime=0x10 & mfmc0=0x0B & rd=0x0C & fct2=0x0 & bit5=0x0 & zero3=0x0 & rt=0x0 { + zero = Status; + Status = Status & -2; # clearing last bit (ffff..fffe == -2 signed) +} +:di RT is $(AMODE) & prime=0x10 & mfmc0=0x0B & rd=0x0C & fct2=0x0 & bit5=0x0 & zero3=0x0 & RT { + RT = Status; + Status = Status & -2; # clearing last bit (ffff..fffe == -2 signed) +} + +# 0000 0000 0000 0000 0000 0000 1100 0000 +:ehb is $(AMODE) & prime=0x0 & rs=0x0 & rt=0x0 & rd=0x0 & fct2=0x3 & fct=0x0 { +} + +# 0100 0001 011t tttt 0110 0000 0010 0000 +:ei is $(AMODE) & prime=0x10 & mfmc0=0x0B & rd=0x0C & fct2=0x0 & bit5=0x01 & zero3=0x0 & rt=0x0 { + zero = Status; + Status = Status | 1; +} +:ei RT is $(AMODE) & prime=0x10 & mfmc0=0x0B & rd=0x0C & fct2=0x0 & bit5=0x01 & zero3=0x0 & RT { + RT = Status; + Status = Status | 1; +} + +# MIPS R3000 and prior only, replaced with ERET in R4000 and later +# 0100 0010 0000 0000 0000 0000 0001 0000 +:rfe is $(AMODE) & prime=0x10 & fct=0x10 & bit25=1 & copfill=0 { + local currentStatus = Status; + Status = (currentStatus & 0xfffffff0) | ((currentStatus & 0x3c) >> 2); +} + +# 0100 0010 0000 0000 0000 0000 0001 1000 +:eret is $(AMODE) & prime=0x10 & fct=0x18 & bit25=1 & copfill=0 { + return[EPC]; +} + +:eretnc is $(AMODE) & prime=0x10 & fct=0x18 & bit25=1 & copfill=1 { + return[EPC]; +} + +# 0111 11ss ssst tttt mmmm mLLL LL00 0000 +:ext RT, RSsrc, lsb, ExtSize is $(AMODE) & prime=0x1F & fct=0x0 & RT & RSsrc & lsb & msbd & ExtSize { + # Extract Bit Field + # RT = extractField(RSsrc, msbd:1, lsb:1); + # Note that msbd = size - 1 + rs_tmp:$(REGSIZE) = RSsrc << ($(REGSIZE) * 8 - (msbd + lsb + 1)); + rs_tmp = rs_tmp >> ($(REGSIZE) * 8 - (msbd + 1)); + RT = zext(rs_tmp); +} + +# 0111 11ss ssst tttt mmmm mLLL LL00 0100 +:ins RT, RSsrc, lsb, InsSize is $(AMODE) & prime=0x1F & fct=0x04 & RT & RTsrc & RSsrc & lsb & msbd & InsSize { + tmpa:$(REGSIZE) = -1; + tmpa = tmpa >> ($(REGSIZE) * 8 - InsSize); + tmpb:$(REGSIZE) = RSsrc & tmpa; + tmpa = tmpa << lsb; + tmpa = ~tmpa; + tmpb = tmpb << lsb; + RT = (RT & tmpa) | tmpb; +} + +# 0000 10aa aaaa aaaa aaaa aaaa aaaa aaaa +:j Abs26 is $(AMODE) & prime=2 & Abs26 { + delayslot( 1 ); + goto Abs26; +} +# 0000 11aa aaaa aaaa aaaa aaaa aaaa aaaa +:jal Abs26 is $(AMODE) & prime=3 & Abs26 { + ra = inst_next; + delayslot( 1 ); + call Abs26; +} +@ifdef ISA_VARIANT +# 0000 00ss sss0 0000 dddd dhhh hh00 1001 +:jalr RD, RSsrc is $(AMODE) & prime=0 & fct=9 & RSsrc & rt=0 & RD { + build RD; + build RSsrc; + JXWritePC(RSsrc); + RD = inst_next; + delayslot( 1 ); + call [pc]; +} +:jalr RSsrc is $(AMODE) & prime=0 & fct=9 & RSsrc & rt=0 & rd=0x1F { + build RSsrc; + JXWritePC(RSsrc); + ra = inst_next; + delayslot( 1 ); + call [pc]; +} +@else +# 0000 00ss sss0 0000 dddd dhhh hh00 1001 +:jalr RD, RSsrc is $(AMODE) & prime=0 & fct=9 & RSsrc & rt=0 & RD { + RD = inst_next; + delayslot( 1 ); + tmp:$(ADDRSIZE) = 0; + ValCast(tmp,RSsrc); + call [tmp]; +} +:jalr RSsrc is $(AMODE) & prime=0 & fct=9 & RSsrc & rt=0 & rd=0x1F { + ra = inst_next; + delayslot( 1 ); + tmp:$(ADDRSIZE) = 0; + ValCast(tmp,RSsrc); + call [tmp]; +} +@endif +@ifdef ISA_VARIANT +# 0000 00ss sss0 0000 dddd d1hh hh00 1001 +:jalr.hb RD, RSsrc is $(AMODE) & prime=0 & fct=9 & RSsrc & rt=0 & RD & bit10=1 { + build RD; + build RSsrc; + JXWritePC(RSsrc); + RD = inst_next; + delayslot( 1 ); + call [pc]; +} +:jalr.hb RSsrc is $(AMODE) & prime=0 & fct=9 & RSsrc & rt=0 & rd=0x1F & bit10=1 { + build RSsrc; + JXWritePC(RSsrc); + ra = inst_next; + delayslot( 1 ); + call [pc]; +} +@else +# 0000 00ss sss0 0000 dddd d1hh hh00 1001 +:jalr.hb RD, RSsrc is $(AMODE) & prime=0 & fct=9 & RSsrc & rt=0 & RD & bit10=1 { + RD = inst_next; + delayslot( 1 ); + tmp:$(ADDRSIZE) = 0; + ValCast(tmp,RSsrc); + call [tmp]; +} +:jalr.hb RSsrc is $(AMODE) & prime=0 & fct=9 & RSsrc & rt=0 & rd=0x1F & bit10=1 { + ra = inst_next; + delayslot( 1 ); + tmp:$(ADDRSIZE) = 0; + ValCast(tmp,RSsrc); + call [tmp]; +} +@endif + +@ifdef ISA_VARIANT +# 0000 00ss sss0 0000 0000 0hhh hh00 1000 +:jr RSsrc is $(AMODE) & prime=0 & ((REL6=0 & fct=8) | (REL6=1 & fct=0x09)) & RSsrc & rt=0 & rd=0 { + build RSsrc; + JXWritePC(RSsrc); + delayslot(1); + goto [pc]; +} +@else +# 0000 00ss sss0 0000 0000 0hhh hh00 1000 +:jr RSsrc is $(AMODE) & prime=0 & ((REL6=0 & fct=8) | (REL6=1 & fct=0x09)) & RSsrc & rt=0 & rd=0 { + delayslot(1); + tmp:$(ADDRSIZE) = 0; + ValCast(tmp,RSsrc); + goto [tmp]; +} +@endif +@ifdef ISA_VARIANT +# 0000 00ss sss0 0000 0000 01hh hh00 1000 +:jr.hb RSsrc is $(AMODE) & prime=0 & ((REL6=0 & fct=8) | (REL6=1 & fct=0x09)) & RSsrc & rt=0 & rd=0 & bit10=1 { + build RSsrc; + JXWritePC(RSsrc); + delayslot(1); + goto [pc]; +} +@else +# 0000 00ss sss0 0000 0000 01hh hh00 1000 +:jr.hb RSsrc is $(AMODE) & prime=0 & ((REL6=0 & fct=8) | (REL6=1 & fct=0x09)) & RSsrc & rt=0 & rd=0 & bit10=1 { + delayslot(1); + tmp:$(ADDRSIZE) = 0; + ValCast(tmp,RSsrc); + goto [tmp]; +} +@endif + +# Special case of JR +# 0000 0011 1110 0000 0000 0hhh hh00 1000 +@ifdef ISA_VARIANT +:jr ra is $(AMODE) & prime=0 & ((REL6=0 & fct=8) | (REL6=1 & fct=0x09)) & rs=0x1F & ra & rt=0 & rd=0 & sa=0 { + JXWritePC(ra); + delayslot(1); + return[pc]; +} +@else +:jr ra is $(AMODE) & prime=0 & ((REL6=0 & fct=8) | (REL6=1 & fct=0x09)) & rs=0x1F & ra & rt=0 & rd=0 & sa=0 { + delayslot(1); + return[ra]; +} +@endif + + + + +# 1000 00bb bbbt tttt iiii iiii iiii iiii +:lb RT, OFF_BASE is $(AMODE) & prime=0x20 & OFF_BASE & RT { + RT = sext(*[ram]:1 OFF_BASE); +} + +:lbe RT, OFF_BASER6 is $(AMODE) & prime=0x1F & fct=0x2C & bit6=0 & OFF_BASER6 & RT { + RT = sext(*[ram]:1 OFF_BASER6); +} + +# 1001 00bb bbbt tttt iiii iiii iiii iiii +:lbu RT, OFF_BASE is $(AMODE) & prime=0x24 & OFF_BASE & RT { + RT = zext( *[ram]:1 OFF_BASE ); +} + +:lbue RT, OFF_BASER6 is $(AMODE) & prime=0x1F & fct=0x28 & bit6=0 & OFF_BASER6 & RT { + RT = zext( *[ram]:1 OFF_BASER6 ); +} + +# 1000 01bb bbbt tttt iiii iiii iiii iiii +:lh RT, OFF_BASE is $(AMODE) & prime=0x21 & OFF_BASE & RT { + RT = sext( *[ram]:2 OFF_BASE ); +} + +:lhe RT, OFF_BASER6 is $(AMODE) & prime=0x1F & fct=0x2D & bit6=0 & OFF_BASER6 & RT { + RT = sext( *[ram]:2 OFF_BASER6 ); +} + +# 1001 01bb bbbt tttt iiii iiii iiii iiii +:lhu RT, OFF_BASE is $(AMODE) & prime=0x25 & OFF_BASE & RT { + RT = zext( *[ram]:2 OFF_BASE ); +} + +:lhue RT, OFF_BASER6 is $(AMODE) & prime=0x1F & fct=0x29 & bit6=0 & OFF_BASER6 & RT { + RT = zext( *[ram]:2 OFF_BASER6 ); +} + +:lle RT, OFF_BASER6 is $(AMODE) & prime=0x1F & fct=0x2E & bit6=0 & OFF_BASER6 & RT { + RT = sext(*[ram]:4 OFF_BASER6); +} + +# 1000 11bb bbbt tttt iiii iiii iiii iiii +:lw RT, OFF_BASE is $(AMODE) & prime=0x23 & OFF_BASE & RT { + RT = sext( *[ram]:4 OFF_BASE ); +} + +:lwe RT, OFF_BASER6 is $(AMODE) & prime=0x1F & fct=0x2F & bit6=0 & OFF_BASER6 & RT { + RT = sext( *[ram]:4 OFF_BASER6 ); +} + +:lbx RD, INDEX_BASE is $(AMODE) & prime=0x1F & RD & fct=10 & fct2=22 & INDEX_BASE { + RD = sext(*[ram]:1 INDEX_BASE); +} + + +:lhux RD, INDEX_BASE is $(AMODE) & prime=0x1F & RD & fct=10 & fct2=20 & INDEX_BASE { + RD = zext(*[ram]:2 INDEX_BASE); +} + +@ifdef MIPS64 +:lwux RD, INDEX_BASE is $(AMODE) & prime=0x1F & RD & fct=10 & fct2=16 & INDEX_BASE { + RD = zext(*[ram]:4 INDEX_BASE); +} +@endif + +# 0100 0000 000t tttt dddd d000 0000 0sss +:mfc0 RT, RD0 is $(AMODE) & prime=0x10 & copop=0 & RT & RD0 & zero6=0 { + RT = sext( RD0:$(SIZETO4) ); +} + +# 0100 1000 000t tttt iiii iiii iiii iiii +:mfc2 RT, immed is $(AMODE) & prime=0x12 & copop=0 & RT & immed { + tmp:$(REGSIZE) = getCopReg(2:1, immed:4); + RT = sext( tmp ); +} + +# 0100 1000 011t tttt iiii iiii iiii iiii +:mfhc2 RT, immed is $(AMODE) & prime=0x12 & copop=3 & RT & fs & immed { + tmp:$(REGSIZE) = getCopReg(2:1, immed:4); + RT = sext(tmp >> 32); +} + +# Special case of ADDIU +# 0010 0100 000t tttt iiii iiii iiii iiii +:li RT, simmed is $(AMODE) & prime=9 & rs=0 & RT & simmed { + RT = simmed; +} +# Special case of ADDU +# 0000 0000 000t tttt dddd d000 0010 0001 +:move RD, RTsrc is $(AMODE) & prime=0 & fct=0x21 & rs=0 & RD & RTsrc & sa=0 { + RD = RTsrc; +} +# Special case of ADDU +# 0000 00ss sss0 0000 dddd d000 0010 0001 +:move RD, RSsrc is $(AMODE) & prime=0 & fct=0x21 & RSsrc & rt=0 & RD & sa=0 { + RD = RSsrc; +} + +# 0100 0000 100t tttt dddd d000 0000 0sss +:mtc0 RTsrc, RD0, sel is $(AMODE) & prime=0x10 & copop=4 & RTsrc & RD0 & zero6=0 & sel { + setCopReg(0:1, RD0, RTsrc, sel:1); +} +# 0100 1000 100t tttt iiii iiii iiii iiii +:mtc2 RTsrc, immed is $(AMODE) & prime=0x12 & copop=4 & RTsrc & immed { + setCopReg(2:1, immed:4, RTsrc); +} + +:mthc0 RTsrc, RD0, sel is $(AMODE) & prime=0x10 & copop=6 & RTsrc & RD0 & zero6=0 & sel { + setCopReg(0:1, RD0, RTsrc, sel:1); +} + +# 0100 1000 111t tttt iiii iiii iiii iiii +:mthc2 RTsrc, immed is $(AMODE) & prime=0x12 & copop=0x07 & RTsrc & immed { + arg:4 = immed; + tmp:4 = RTsrc:$(SIZETO4); + low:4 = getCopReg(2:1, arg); + val:8 = (zext(tmp) << 32) + zext(low); + setCopReg(2:1, arg, val); +} + +:nal is $(AMODE) & REL6=0 & prime=1 & cond=0x10 & zero21=0 { + ra = inst_next; + delayslot(1); +} + +# 0000 0000 0000 0000 0000 0000 0000 0000 +:nop is $(AMODE) & prime=0 & rs=0 & rt=0 & rd=0 & sa=0 & fct=0 { +} + +# 0000 00ss ssst tttt dddd d000 0010 0111 +:nor RD, RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x27 & RSsrc & RTsrc & RD & sa=0 { + RD = ~(RSsrc | RTsrc); +} +# 0000 00ss ssst tttt dddd d000 0010 0101 +:or RD, RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x25 & RSsrc & RTsrc & RD & sa=0 { + RD = RSsrc | RTsrc; +} +# 0011 01ss ssst tttt iiii iiii iiii iiii +:ori RT, RSsrc, immed is $(AMODE) & prime=0xD & RSsrc & RT & immed { + RT = RSsrc | immed; +} + +:pause is $(AMODE) & prime=0 & szero=0 & fct=0 & fct2=0x05 { + wait(); +} + +:pref hint, OFF_BASE is $(AMODE) & prime=0x33 & hint & OFF_BASE { + prefetch(OFF_BASE, hint:1); +} + +:prefe hint, OFF_BASER6 is $(AMODE) & prime=0x1F & fct=0x23 & bit6=0 & OFF_BASER6 & hint { + prefetch(OFF_BASER6, hint:1); +} + +# 0111 1100 000t tttt dddd d000 0011 1011 +:rdhwr RT, rd_hw is $(AMODE) & prime=0x1F & rs=0 & fct2=0 & fct=0x3B & RT & rd_hw & rd!=4 { + RT = getHWRegister(rd_hw); +} + +# 0111 1100 000t tttt dddd d000 0011 1011 +:rdhwr RT, rd_hw, sel_0608 is $(AMODE) & REL6=1 & prime=0x1F & rs=0 & spec2=0 & fct=0x3B & RT & rd_hw & rd=4 & sel_0608 { + RT = getHWRegister(rd_hw, sel_0608:1); +} + +# 0100 0001 010t tttt dddd d000 0000 0000 +:rdpgpr RD, RT is $(AMODE) & prime=0x10 & rs=10 & bigfunct=0 & RD & RT { + RD = getShadow(RT); +} + +# 0000 0000 001t tttt dddd daaa aa00 0010 +:rotr RD32, RT32src, sa is $(AMODE) & prime=0 & zero1=0 & bit21=1 & fct=2 & RD32 & RT32src & sa & RD { + tmp1:4 = RT32src >> sa; + tmp2:4 = RT32src << (32 - sa); + RD32 = tmp1 + tmp2; +@ifdef MIPS64 + RD = sext(RD32); +@endif +} +# 0000 00ss ssst tttt dddd d000 0100 0110 +:rotrv RD32, RT32src, RS32src is $(AMODE) & prime=0 & zero2=0 & bit6=1 & fct=6 & RD32 & RT32src & RS32src & RD { + shift:4 = RS32src & 0x1f; + tmp1:4 = RT32src >> shift; + tmp2:4 = RT32src << (32 - shift); + RD32 = tmp1 + tmp2; +@ifdef MIPS64 + RD = sext(RD32); +@endif +} + +# 1010 00bb bbbt tttt iiii iiii iiii iiii +:sb RTsrc, OFF_BASE is $(AMODE) & prime=0x28 & OFF_BASE & RTsrc { + *[ram]:1 OFF_BASE = RTsrc:1; +} + +:sbe RTsrc, OFF_BASER6 is $(AMODE) & prime=0x1F & fct=0x1C & bit6=0 & OFF_BASER6 & RTsrc { + *[ram]:1 OFF_BASER6 = RTsrc:1; +} + +:sce RTsrc, OFF_BASER6 is $(AMODE) & prime=0x1F & fct=0x1E & bit6=0 & OFF_BASER6 & RTsrc { + *[ram]:4 OFF_BASER6 = RTsrc:$(SIZETO4); + RTsrc = 1; +} + +# 0111 00cc cccc cccc cccc cccc cc11 1111 +:sdbbp breakcode is $(AMODE) & prime=0x1C & fct=0x3F & breakcode { + signalDebugBreakpointException(); +} + +@ifndef COPR_C +# 1111 10bb bbbt tttt iiii iiii iiii iiii +:sdc2 RTsrc, OFF_BASE is $(AMODE) & prime=0x3E & OFF_BASE & RTsrc { + *[ram]:8 OFF_BASE = getCopReg(2:1, RTsrc); +} +@endif + +# 0111 1100 000t tttt dddd d100 0010 0000 +:seb RD, RTsrc is $(AMODE) & prime=0x1F & rs=0 & fct2=0x10 & fct=0x20 & RD & RTsrc { + RD = sext( RTsrc:1 ); +} +# 0111 1100 000t tttt dddd d110 0010 0000 +:seh RD, RTsrc is $(AMODE) & prime=0x1F & rs=0 & fct2=0x18 & fct=0x20 & RD & RTsrc { + RD = sext( RTsrc:2 ); +} +# 1010 01bb bbbt tttt iiii iiii iiii iiii +:sh RTsrc, OFF_BASE is $(AMODE) & prime=0x29 & OFF_BASE & RTsrc { + *[ram]:2 OFF_BASE = RTsrc:2; +} + +:she RTsrc, OFF_BASER6 is $(AMODE) & prime=0x1F & fct=0x1D & bit6=0 & OFF_BASER6 & RTsrc { + *[ram]:2 OFF_BASER6 = RTsrc:2; +} + +# 0000 0000 000t tttt dddd daaa aa00 0000 +:sll RD32, RT32src, sa is $(AMODE) & prime=0 & fct=0 & rs=0 & RD32 & RT32src & sa & RD { + RD32 = RT32src << sa; +@ifdef MIPS64 + RD = sext(RD32); +@endif +} +# 0000 00ss ssst tttt dddd d000 0000 0100 +:sllv RD32, RT32src, RS32src is $(AMODE) & prime=0 & fct=4 & RS32src & RT32src & RD32 & sa=0 & RD { + shift:4 = RS32src & 0x1f; + RD32 = RT32src << shift; +@ifdef MIPS64 + RD = sext(RD32); +@endif +} +# 0000 00ss ssst tttt dddd d000 0010 1010 +:slt RD, RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x2A & RSsrc & RTsrc & RD & sa=0 { + RD = zext( RSsrc s< RTsrc ); +} +# 0010 10ss ssst tttt iiii iiii iiii iiii +:slti RT, RSsrc, simmed is $(AMODE) & prime=10 & RSsrc & RT & simmed { + RT = zext( RSsrc s< simmed ); +} +# 0010 11ss ssst tttt iiii iiii iiii iiii +:sltiu RT, RSsrc, simmed is $(AMODE) & prime=0xB & RSsrc & RT & simmed { + RT = zext( RSsrc < simmed ); +} +# 0000 00ss ssst tttt dddd d000 0010 1011 +:sltu RD, RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x2B & RSsrc & RTsrc & RD & sa=0 { + RD = zext( RSsrc < RTsrc ); +} + +# 0000 0000 000t tttt dddd daaa aa00 0011 +:sra RD32, RT32src, sa is $(AMODE) & prime=0 & fct=3 & rs=0 & RT32src & RD32 & sa & RD { + RD32 = RT32src s>> sa; +@ifdef MIPS64 + RD = sext(RD32); +@endif +} +# 0000 00ss ssst tttt dddd d000 0000 0111 +:srav RD32, RT32src, RS32src is $(AMODE) & prime=0 & fct=7 & RS32src & RT32src & RD32 & sa=0 & RD { + shift:4 = RS32src & 0x1f; + RD32 = RT32src s>> shift; +@ifdef MIPS64 + RD = sext(RD32); +@endif +} +# 0000 0000 000t tttt dddd daaa aa00 0010 +:srl RD32, RT32src, sa is $(AMODE) & prime=0 & fct=2 & rs=0 & RT32src & RD32 & sa & RD { + RD32 = RT32src >> sa; +@ifdef MIPS64 + RD = sext(RD32); +@endif +} +# 0000 00ss ssst tttt dddd d000 0000 0110 +:srlv RD32, RT32src, RS32src is $(AMODE) & prime=0 & fct=6 & RS32src & RT32src & RD32 & sa=0 & RD { + shift:4 = RS32src & 0x1f; + RD32 = RT32src >> shift; +@ifdef MIPS64 + RD = sext(RD32); +@endif +} + +# 0000 0000 0000 0000 0000 0000 0100 0000 +:ssnop is $(AMODE) & prime=0 & rs=0 & rt=0 & rd=0 & sa=1 & fct=0 { +} + +# 0000 00ss ssst tttt dddd d000 0010 0010 +:sub RD32, RS32src, RT32src is $(AMODE) & prime=0 & fct=0x22 & RS32src & RT32src & RD32 & sa=0 & RD { + RD32 = RS32src - RT32src; +@ifdef MIPS64 + RD = sext(RD32); +@endif +} +# 0000 00ss ssst tttt dddd d000 0010 0011 +:subu RD32, RS32src, RT32src is $(AMODE) & prime=0 & fct=0x23 & RS32src & RT32src & RD32 & sa=0 & RD { + RD32 = RS32src - RT32src; +@ifdef MIPS64 + RD = sext(RD32); +@endif +} + +# 1010 11bb bbbt tttt iiii iiii iiii iiii +:sw RTsrc, OFF_BASE is $(AMODE) & prime=0x2B & OFF_BASE & RTsrc { + *[ram]:4 OFF_BASE = RTsrc:$(SIZETO4); +} + +@ifndef COPR_C +# 1110 10bb bbbt tttt iiii iiii iiii iiii +:swc2 hint, OFF_BASE is $(AMODE) & prime=0x3A & OFF_BASE & hint { + tmp:4 = getCopReg(2:1, hint:4); + *[ram]:4 OFF_BASE = tmp; +} +@endif + +:swe RTsrc, OFF_BASER6 is $(AMODE) & prime=0x1F & fct=0x1F & bit6=0 & OFF_BASER6 & RTsrc { + *[ram]:4 OFF_BASER6 = RTsrc:$(SIZETO4); +} + +define pcodeop SYNC; + +# 0000 0000 0000 0000 0000 0yyy yy00 1111 +:sync scalar is $(AMODE) & prime=0 & fct=0xF & szero=0 & stype [ scalar = stype + 0; ] { + SYNC(scalar:1); +} + +# 0000 01bb bbb1 1111 iiii iiii iiii iiii +:synci OFF_BASE is $(AMODE) & prime=1 & OFF_BASE & synci=0x1F { +} + +# 0000 00cc cccc cccc cccc cccc cc00 1100 +:syscall is $(AMODE) & prime=0 & fct=0xC & breakcode { + tmp:4=breakcode; + syscall(tmp); +} + +# 0000 00ss ssst tttt cccc cccc cc11 0100 +:teq RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x34 & RSsrc & RTsrc & code { + if (RSsrc != RTsrc) goto ; + tmp:2=code; + trap(tmp); + +} +# 0000 00ss ssst tttt cccc cccc cc11 0000 +:tge RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x30 & RSsrc & RTsrc & code { + if (RSsrc < RTsrc) goto ; + tmp:2=code; + trap(tmp); + +} +# 0000 00ss ssst tttt cccc cccc cc11 0001 +:tgeu RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x31 & RSsrc & RTsrc & code { + if (RSsrc < RTsrc) goto ; + tmp:2=code; + trap(tmp); + +} + +:tlbinv is $(AMODE) & prime=0x10 & bit25=1 & copfill=0x00 & fct=0x03 { + TLB_invalidate(Index, EntryHi); +} + +:tlbinvf is $(AMODE) & prime=0x10 & bit25=1 & copfill=0x00 & fct=0x04 { + TLB_invalidate_flush(Index); +} + +:tlbp is $(AMODE) & prime=0x10 & bit25=1 & copfill=0x00 & fct=0x08 { + Index = TLB_probe_for_matching_entry(EntryHi); +} + +:tlbr is $(AMODE) & prime=0x10 & bit25=1 & copfill=0x00 & fct=0x01 { + EntryHi = TLB_read_indexed_entryHi(Index); + EntryLo0 = TLB_read_indexed_entryLo0(Index); + EntryLo1 = TLB_read_indexed_entryLo1(Index); + PageMask = TLB_read_indexed_entryPageMask(Index); +} + +:tlbwi is $(AMODE) & prime=0x10 & bit25=1 & copfill=0x00 & fct=0x02 { + TLB_write_indexed_entry(Index, EntryHi, EntryLo0, EntryLo1, PageMask); +} + +:tlbwr is $(AMODE) & prime=0x10 & bit25=1 & copfill=0x00 & fct=0x06 { + TLB_write_random_entry(Random, EntryHi, EntryLo0, EntryLo1, PageMask); +} + +# 0000 00ss ssst tttt cccc cccc cc11 0010 +:tlt RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x32 & RSsrc & RTsrc & code { + if (RSsrc s>= RTsrc) goto ; + tmp:2=code; + trap(tmp); + +} +# 0000 00ss ssst tttt cccc cccc cc11 0011 +:tltu RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x33 & RSsrc & RTsrc & code { + if (RSsrc >= RTsrc) goto ; + tmp:2=code; + trap(tmp); + +} +# 0000 00ss ssst tttt cccc cccc cc11 0110 +:tne RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x36 & RSsrc & RTsrc & code { + if (RSsrc == RTsrc) goto ; + tmp:2=code; + trap(tmp); + +} + +# 0100 001c cccc cccc cccc cccc cc10 0000 +:wait is $(AMODE) & prime=0x10 & fct=0x20 & copfill & bit25=1 { + tmp:4 = copfill; + wait(tmp); +} + +# 0100 0001 110t tttt dddd d000 0000 0000 +:wrpgpr RD, RTsrc is $(AMODE) & prime=0x10 & format=0xE & RTsrc & RD & bigfunct=0 { + setShadow(RD, RTsrc); +} + +# 0111 1100 000t tttt dddd d000 1010 0000 +:wsbh RD, RTsrc is $(AMODE) & prime=0x1F & format=0 & RTsrc & RD & wsbh=2 & bshfl=0x20 { + tmp1:$(REGSIZE) = RTsrc & 0xff; + tmp2:$(REGSIZE) = (RTsrc >> 8) & 0xff; + tmp3:$(REGSIZE) = (RTsrc >> 16) & 0xff; + tmp4:$(REGSIZE) = (RTsrc >> 24) & 0xff; + RD = (tmp3 << 24) | (tmp4 << 16) | (tmp1 << 8) | (tmp2); +} + +# 0000 00ss ssst tttt dddd d000 0010 0110 +:xor RD, RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x26 & RSsrc & RTsrc & RD & sa=0 { + RD = RSsrc ^ RTsrc; +} +# 0011 10ss ssst tttt iiii iiii iiii iiii +:xori RT, RSsrc, immed is $(AMODE) & prime=0xE & RSsrc & RT & immed { + RT = RSsrc ^ immed; +} + +############################ +# +# MIPS64 Instructions to be included with all MIPS32 processors +# +############################ + +## Allow MIPS 64 instructions below for compilers +## using a 64-bit chip, but really keeping things to 32-bits + +# Special case of daddu +# 0000 00ss ssst tttt dddd d000 0010 1101 +:clear RD is $(AMODE) & prime=0 & fct=0x2D & rs=0 & rt=0 & RD & sa=0 { + RD = 0; +} + +# 0000 00ss ssst tttt dddd d000 0010 1100 +:dadd RD, RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x2C & RSsrc & RTsrc & RD & sa=0 { + RD = RSsrc + RTsrc; +} +# 0110 01ss ssst tttt iiii iiii iiii iiii +:daddiu RT, RSsrc, simmed is $(AMODE) & prime=0x19 & RSsrc & RT & simmed { + RT = RSsrc + simmed; +} +# 0000 00ss ssst tttt dddd d000 0010 1101 +:daddu RD, RSsrc, RTsrc is $(AMODE) & prime=0 & fct=0x2D & RSsrc & RTsrc & RD & sa=0 { + RD = RSsrc + RTsrc; +} + +#### +# +# Pre-6 semantics +# +#### +# 0010 00ss ssst tttt iiii iiii iiii iiii +:addi RT32, RS32src, simmed is $(AMODE) & REL6=0 & prime=8 & RT32 & RS32src & simmed & RT { + RT32 = RS32src + simmed; +@ifdef MIPS64 + RT = sext(RT32); +@endif +} + +# 0000 01ss sss1 0001 iiii iiii iiii iiii +:bal Rel16 is $(AMODE) & REL6=0 & prime=1 & cond=0x11 & rs=0 & Rel16 { + ra = inst_next; + delayslot( 1 ); + call Rel16; +} + +# Special case PIC +:bal Rel16 is $(AMODE) & REL6=0 & prime=1 & cond=0x11 & rs=0 & off16=1 & Rel16 { + ra = inst_next; + delayslot( 1 ); + goto Rel16; +} + +# 0100 1001 000c cc00 iiii iiii iiii iiii +:bc2f Rel16 is $(AMODE) & REL6=0 & prime=0x12 & copop=8 & cc=0 & nd=0 & tf=0 & Rel16 { + tmp:1 = getCopCondition(2:1, 0:1); + delayslot(1); + if (tmp != 0) goto inst_next; + goto Rel16; +} +:bc2f cc,Rel16 is $(AMODE) & REL6=0 & prime=0x12 & copop=8 & cc & nd=0 & tf=0 & Rel16 { + tmp:1 = getCopCondition(2:1, cc:1); + delayslot(1); + if (tmp != 0) goto inst_next; + goto Rel16; +} +# 0100 1001 000c cc10 iiii iiii iiii iiii +:bc2fl Rel16 is $(AMODE) & REL6=0 & prime=0x12 & copop=8 & cc=0 & nd=1 & tf=0 & Rel16 { + tmp:1 = getCopCondition(2:1, 0:1); + if (tmp != 0) goto inst_next; + delayslot(1); + goto Rel16; +} +:bc2fl cc,Rel16 is $(AMODE) & REL6=0 & prime=0x12 & copop=8 & cc & nd=1 & tf=0 & Rel16 { + tmp:1 = getCopCondition(2:1, cc:1); + if (tmp != 0) goto inst_next; + delayslot(1); + goto Rel16; +} +# 0100 1001 000c cc01 iiii iiii iiii iiii +:bc2t Rel16 is $(AMODE) & REL6=0 & prime=0x12 & copop=8 & cc=0 & nd=0 & tf=1 & Rel16 { + tmp:1 = getCopCondition(2:1, 0:1); + delayslot(1); + if (tmp == 0) goto inst_next; + goto Rel16; +} +:bc2t cc,Rel16 is $(AMODE) & REL6=0 & prime=0x12 & copop=8 & cc & nd=0 & tf=1 & Rel16 { + tmp:1 = getCopCondition(2:1, cc:1); + delayslot(1); + if (tmp == 0) goto inst_next; + goto Rel16; +} +# 0100 1001 000c cc11 iiii iiii iiii iiii +:bc2tl Rel16 is $(AMODE) & REL6=0 & prime=0x12 & copop=8 & cc=0 & nd=1 & tf=1 & Rel16 { + tmp:1 = getCopCondition(2:1, 0:1); + if (tmp == 0) goto inst_next; + delayslot(1); + goto Rel16; +} +:bc2tl cc,Rel16 is $(AMODE) & REL6=0 & prime=0x12 & copop=8 & cc & nd=1 & tf=1 & Rel16 { + tmp:1 = getCopCondition(2:1, cc:1); + if (tmp == 0) goto inst_next; + delayslot(1); + goto Rel16; +} + +# 0101 00ss ssst tttt iiii iiii iiii iiii +:beql RSsrc, RTsrc, Rel16 is $(AMODE) & REL6=0 & prime=0x14 & RSsrc & RTsrc & Rel16 { + if (!(RSsrc==RTsrc)) goto inst_next; + delayslot(1); + goto Rel16; +} + +:bgezal RSsrc, Rel16 is $(AMODE) & REL6=0 & prime=1 & cond=0x11 & RSsrc & Rel16 { + ra = inst_next; + delayflag:1 = ( RSsrc s>= 0 ); + delayslot( 1 ); + if (!delayflag) goto inst_next; + call Rel16; +} + +# 0000 01ss sss1 0011 iiii iiii iiii iiii +:bgezall RSsrc, Rel16 is $(AMODE) & REL6=0 & prime=1 & cond=0x13 & RSsrc & Rel16 { + ra = inst_next; + if (!(RSsrc s>= 0)) goto inst_next; + delayslot( 1 ); + call Rel16; +} +# 0000 01ss sss0 0011 iiii iiii iiii iiii +:bgezl RSsrc, Rel16 is $(AMODE) & REL6=0 & prime=1 & cond=3 & RSsrc & Rel16 { + if (!(RSsrc s>= 0)) goto inst_next; + delayslot(1); + goto Rel16; +} +# 0101 11ss sss0 0000 iiii iiii iiii iiii +:bgtzl RSsrc, Rel16 is $(AMODE) & REL6=0 & prime=0x17 & cond=0 & RSsrc & Rel16 { + if (!(RSsrc s> 0)) goto inst_next; + delayslot(1); + goto Rel16; +} +# 0101 10ss sss0 0000 iiii iiii iiii iiii +:blezl RSsrc, Rel16 is $(AMODE) & REL6=0 & prime=0x16 & cond=0 & RSsrc & Rel16 { + if (!(RSsrc s<= 0)) goto inst_next; + delayslot(1); + goto Rel16; +} +# 0000 01ss sss1 0000 iiii iiii iiii iiii +:bltzal RSsrc, Rel16 is $(AMODE) & REL6=0 & prime=1 & cond=0x10 & RSsrc & Rel16 { + ra = inst_next; + delayflag:1 = ( RSsrc s< 0 ); + delayslot( 1 ); + if (!delayflag) goto inst_next; + call Rel16; +} +# 0000 01ss sss1 0010 iiii iiii iiii iiii +:bltzall RSsrc, Rel16 is $(AMODE) & REL6=0 & prime=1 & cond=0x12 & RSsrc & Rel16 { + ra = inst_next; + if (!(RSsrc s< 0)) goto inst_next; + delayslot(1); + call Rel16; +} +# 0000 01ss sss0 0010 iiii iiii iiii iiii +:bltzl RSsrc, Rel16 is $(AMODE) & REL6=0 & prime=1 & cond=2 & RSsrc & Rel16 { + if (!(RSsrc s< 0)) goto inst_next; + delayslot(1); + goto Rel16; +} +# 0101 01ss ssst tttt iiii iiii iiii iiii +:bnel RSsrc, RTsrc, Rel16 is $(AMODE) & REL6=0 & prime=0x15 & RSsrc & RTsrc & Rel16 { + if (!(RSsrc!=RTsrc)) goto inst_next; + delayslot(1); + goto Rel16; +} + +# 0111 00ss ssst tttt dddd d000 0010 0001 +:clo RD, RSsrc is $(AMODE) & REL6=0 & prime=0x1C & sa=0x0 & fct=0x21 & RD & RSsrc { + # Count leading ones in a word + RD = lzcount( ~RSsrc ); +} + +# 0111 00ss ssst tttt dddd d000 0010 0000 +:clz RD, RSsrc is $(AMODE) & REL6=0 & prime=0x1C & sa=0x0 & fct=0x20 & RD & RSsrc { + # Count leading zeros in a word + RD = lzcount( RSsrc ); +} + +# 0000 00ss ssst tttt 0000 0000 0001 1010 +:div RS32src, RT32src is $(AMODE) & REL6=0 & prime=0 & fct=0x1A & RS32src & RT32src & rd=0 & sa=0 { + lo = sext(RS32src s/ RT32src); + hi = sext(RS32src s% RT32src); +} +# 0000 00ss ssst tttt 0000 0000 0001 1011 +:divu RS32src, RT32src is $(AMODE) & REL6=0 & prime=0 & fct=0x1B & RS32src & RT32src & rd=0 & sa=0 { + lo = sext(RS32src / RT32src); + hi = sext(RS32src % RT32src); +} +@ifdef ISA_VARIANT +# 0111 01aa aaaa aaaa aaaa aaaa aaaa aaaa +:jalx Abs26 is $(AMODE) & REL6=0 & prime=0x1D & Abs26 [ ISA_MODE = 1; globalset(Abs26, ISA_MODE);] { + ra = inst_next; + delayslot( 1 ); + ISAModeSwitch = 1; + call Abs26; +} +@endif + +@ifndef COPR_C +# 1101 10bb bbbt tttt iiii iiii iiii iiii +:ldc2 rt, OFF_BASE is $(AMODE) & REL6=0 & prime=0x36 & OFF_BASE & rt { + setCopReg(2:1, rt, *[ram]:8 OFF_BASE); +} +@endif + +# 1100 00bb bbbt tttt iiii iiii iiii iiii +:ll RT, OFF_BASE is $(AMODE) & REL6=0 & prime=0x30 & OFF_BASE & RT { + RT = sext(*[ram]:4 OFF_BASE); +} + +# 0011 1100 000t tttt iiii iiii iiii iiii +:lui RT, immed is $(AMODE) & REL6=0 & prime=0xF & rs=0 & RT & immed { + tmp:4 = immed << 16; + RT = sext(tmp); +} + +@ifndef COPR_C +# 1100 10bb bbbt tttt iiii iiii iiii iiii +:lwc2 rt, OFF_BASE is $(AMODE) & REL6=0 & prime=0x32 & OFF_BASE & rt { + setCopReg( 2:1, rt, *[ram]:4 OFF_BASE ); +} +@endif + +@if ENDIAN == "big" +# 1000 10bb bbbt tttt iiii iiii iiii iiii +:lwl RT, OFF_BASE is $(AMODE) & REL6=0 & prime=0x22 & OFF_BASE & RT & RTsrc { + shft:$(ADDRSIZE) = OFF_BASE & 0x3; + addr:$(ADDRSIZE) = OFF_BASE - shft; + valOrig:4 = RTsrc:$(SIZETO4) & (0xffffffff >> ((4-shft) * 8)); + valLoad:4 = *(addr) << (shft * 8); + RT = sext( valLoad | valOrig ); +} + +# 1001 10bb bbbt tttt iiii iiii iiii iiii +:lwr RT, OFF_BASE is $(AMODE) & REL6=0 & prime=0x26 & OFF_BASE & RT & RTsrc { + shft:$(ADDRSIZE) = OFF_BASE & 0x3; + addr:$(ADDRSIZE) = OFF_BASE - shft; + valOrig:4 = RTsrc:$(SIZETO4) & (0xffffffff << ((shft+1) * 8)); + valLoad:4 = *(addr) >> ((3-shft) * 8); + RT = sext( valOrig | valLoad ); +} +:lwle RTsrc, OFF_BASER6 is $(AMODE) & REL6=0 & prime=0x1F & fct=0x19 & bit6=0 & OFF_BASER6 & RTsrc & RT { + shft:$(ADDRSIZE) = OFF_BASER6 & 0x3; + addr:$(ADDRSIZE) = OFF_BASER6 - shft; + valOrig:4 = RTsrc:$(SIZETO4) & (0xffffffff >> ((4-shft) * 8)); + valLoad:4 = *(addr) << (shft * 8); + RT = sext( valLoad | valOrig ); +} + +:lwre RTsrc, OFF_BASER6 is $(AMODE) & REL6=0 & prime=0x1F & fct=0x1A & bit6=0 & OFF_BASER6 & RTsrc & RT { + shft:$(ADDRSIZE) = OFF_BASER6 & 0x3; + addr:$(ADDRSIZE) = OFF_BASER6 - shft; + valOrig:4 = RTsrc:$(SIZETO4) & (0xffffffff << ((shft+1) * 8)); + valLoad:4 = *(addr) >> ((3-shft) * 8); + RT = sext( valOrig | valLoad ); +} +@else +:lwl RT, OFF_BASE is $(AMODE) & REL6=0 & prime=0x22 & OFF_BASE & RT & RTsrc { + shft:$(ADDRSIZE) = OFF_BASE & 0x3; + addr:$(ADDRSIZE) = OFF_BASE - shft; + valOrig:4 = RTsrc:$(SIZETO4) & (0xffffffff >> ((shft+1)* 8)); + valLoad:4 = *(addr) << ((3-shft) * 8); + RT = sext( valLoad | valOrig ); +} + +# 1001 10bb bbbt tttt iiii iiii iiii iiii +:lwr RT, OFF_BASE is $(AMODE) & REL6=0 & prime=0x26 & OFF_BASE & RT & RTsrc { + shft:$(ADDRSIZE) = OFF_BASE & 0x3; + addr:$(ADDRSIZE) = OFF_BASE - shft; + valOrig:4 = RTsrc:$(SIZETO4) & (0xffffffff << ((4-shft)* 8)); + valLoad:4 = *(addr) >> (shft * 8); + RT = sext( valOrig | valLoad ); +} +:lwle RTsrc, OFF_BASER6 is $(AMODE) & REL6=0 & prime=0x1F & fct=0x19 & bit6=0 & OFF_BASER6 & RTsrc & RT { + shft:$(ADDRSIZE) = OFF_BASER6 & 0x3; + addr:$(ADDRSIZE) = OFF_BASER6 - shft; + valOrig:4 = RTsrc:$(SIZETO4) & (0xffffffff >> ((shft+1)* 8)); + valLoad:4 = *(addr) << ((3-shft) * 8); + RT = sext( valLoad | valOrig ); +} + +:lwre RTsrc, OFF_BASER6 is $(AMODE) & REL6=0 & prime=0x1F & fct=0x1A & bit6=0 & OFF_BASER6 & RTsrc & RT { + shft:$(ADDRSIZE) = OFF_BASER6 & 0x3; + addr:$(ADDRSIZE) = OFF_BASER6 - shft; + valOrig:4 = RTsrc:$(SIZETO4) & (0xffffffff << ((4-shft)* 8)); + valLoad:4 = *(addr) >> (shft * 8); + RT = sext( valOrig | valLoad ); +} +@endif + +# lwl and lwr almost always come in pairs. +# When the analyzer does finds a matching lwl/lwr pair, the pcode is simplified so that +# lwl does all the loading while lwr is a no-op +@if ENDIAN == "big" +:lwl RT, OFF_BASE is $(AMODE) & REL6=0 & prime=0x22 & OFF_BASE & RT & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] { + RT = sext( *[ram]:4 OFF_BASE ); +} +:lwr RT, OFF_BASE is $(AMODE) & REL6=0 & prime=0x26 & OFF_BASE & RT & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 0; ] { +} +@else +:lwl RT, OFF_BASE is $(AMODE) & REL6=0 & prime=0x22 & OFF_BASE & RT & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] { +} +:lwr RT, OFF_BASE is $(AMODE) & REL6=0 & prime=0x26 & OFF_BASE & RT & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 0; ] { + RT = sext( *[ram]:4 OFF_BASE ); +} +@endif + +# 0111 00ss ssst tttt 000a a000 0000 0000 +:madd RS32src, RT32src is $(AMODE) & REL6=0 & prime=0x1C & zero1315=0x0 & fct2=0x0 & fct=0x0 & RS32src & RT32src & ac=0 & achi & aclo { + tmp1:8 = sext(RS32src); + tmp2:8 = sext(RT32src); + prod:8 = tmp1 * tmp2; + aclo = aclo & 0xffffffff; # Make sure any upper bits of lo don't contribute to sum + sum:8 = (zext(achi) << 32) + zext(aclo) + prod; + aclo = sext(sum:4); + sum = sum >> 32; + achi = sext(sum:4); +} + +# 0111 00ss ssst tttt 000a a000 0000 0001 +:maddu RS32src, RT32src is $(AMODE) & REL6=0 & prime=0x1C & zero1315=0x0 & fct2=0x0 & fct=0x01 & RS32src & RT32src & ac=0 & achi & aclo { + tmp1:8 = zext(RS32src); + tmp2:8 = zext(RT32src); + prod:8 = tmp1 * tmp2; + aclo = aclo & 0xffffffff; # Make sure any upper bits of lo don't contribute to sum + sum:8 = (zext(achi) << 32) + zext(aclo) + prod; + aclo = sext(sum:4); + sum = sum >> 32; + achi = sext(sum:4); +} + +# 0000 0000 0aa0 0000 dddd d000 0001 0000 +:mfhi RD is $(AMODE) & REL6=0 & prime=0 & fct=0x10 & RD & zero5=0 & zero1620=0 & zero2325=0 & acf=0 & acfhi { + RD = acfhi; +} + +# 0000 0000 0aa0 0000 dddd d000 0001 0010 +:mflo RD is $(AMODE) & REL6=0 & prime=0 & fct=0x12 & RD & zero5=0 & zero1620=0 & zero2325=0 & acf=0 & acflo { + RD = acflo; +} + +# 0000 00ss ssst tttt dddd d000 0000 1011 +:movn RD, RSsrc, RTsrc is $(AMODE) & REL6=0 & prime=0 & zero5=0 & fct=0xB & RD & RSsrc & RTsrc { + if (RTsrc == 0) goto ; + RD = RSsrc; + +} + +# 0000 00ss ssst tttt dddd d000 0000 1010 +:movz RD, RSsrc, RTsrc is $(AMODE) & REL6=0 & prime=0 & zero5=0 & fct=10 & RD & RSsrc & RTsrc { + if (RTsrc != 0) goto ; # We can't use goto inst_next because it fails if we are in a delay slot + RD = RSsrc; + +} + + +# 0111 00ss ssst tttt 000a a000 0000 0100 +:msub RS32src, RT32src is $(AMODE) & REL6=0 & prime=0x1C & fct2=0 & fct=0x04 & RS32src & RT32src & zero1315=0 & aclo & achi { + tmp1:8 = sext(RS32src); + tmp2:8 = sext(RT32src); + prod:8 = tmp1 * tmp2; + aclo = aclo & 0xffffffff; # Make sure any upper bits of lo don't contribute to sum + sum:8 = (zext(achi) << 32) + zext(aclo) - prod; + aclo = sext(sum:4); + sum = sum >> 32; + achi = sext(sum:4); +} + +# 0111 00ss ssst tttt 000a a000 0000 0101 +:msubu RS32src, RT32src is $(AMODE) & REL6=0 & prime=0x1C & fct2=0 & fct=0x05 & RS32src & RT32src & zero1315=0 & ac=0 & aclo & achi { + tmp1:8 = zext(RS32src); + tmp2:8 = zext(RT32src); + prod:8 = tmp1 * tmp2; + aclo = aclo & 0xffffffff; # Make sure any upper bits of lo don't contribute to sum + sum:8 = (zext(achi) << 32) + zext(aclo) - prod; + aclo = sext(sum:4); + sum = sum >> 32; + achi = sext(sum:4); +} + +# 0000 00ss sss0 0000 000a a000 0001 0001 +:mthi RSsrc is $(AMODE) & REL6=0 & prime=0 & fct=0x11 & RSsrc & zero5=0 & zero1320=0 & ac=0 & achi { + achi = RSsrc; +} + +# 0000 00ss sss0 0000 000a a000 0001 0011 +:mtlo RSsrc is $(AMODE) & REL6=0 & prime=0 & fct=0x13 & RSsrc & zero5=0 & zero1320=0 & ac=0 & aclo { + aclo = RSsrc; +} + +# 0111 00ss ssst tttt dddd d000 0000 0010 +:mul RD, RS32src, RT32src is $(AMODE) & REL6=0 & prime=0x1C & sa=0x0 & fct=0x02 & RD & RS32src & RT32src { + tmp1:8 = sext( RS32src ); + tmp2:8 = sext( RT32src ); + prod:8 = tmp1 * tmp2; + RD = sext( prod:4 ); +} + +# 0000 00ss ssst tttt 000a a000 0001 1000 +:mult RS32src, RT32src is $(AMODE) & REL6=0 & prime=0 & fct=0x18 & RS32src & RT32src & zero5=0 & zero1315=0 & aclo & achi { + tmp1:8 = sext( RS32src ); + tmp2:8 = sext( RT32src ); + prod:8 = tmp1 * tmp2; + aclo = sext(prod:4); + prod = prod >> 32; + achi = sext(prod:4); +} + +# 0000 00ss ssst tttt 000a a000 0001 1001 +:multu RS32src, RT32src is $(AMODE) & REL6=0 & prime=0 & fct=0x19 & RS32src & RT32src & zero5=0 & zero1315=0 & aclo & achi { + tmp1:8 = zext( RS32src ); + tmp2:8 = zext( RT32src ); + prod:8 = tmp1 * tmp2; + aclo = sext(prod:4); + prod = prod >> 32; + achi = sext(prod:4); +} + +# 0100 0110 110t tttt ssss sddd dd10 1100 +:pll.ps fd, fs, ft is $(AMODE) & REL6=0 & prime=0x11 & format=0x16 & fct=0x2C & ft & fs & fd + unimpl + +# 0100 0110 110t tttt ssss sddd dd10 1101 +:plu.ps fd, fs, ft is $(AMODE) & REL6=0 & prime=0x11 & format=0x16 & fct=0x2D & ft & fs & fd + unimpl + +#:prefx + +# 0100 0110 110t tttt ssss sddd dd10 1110 +:pul.ps fd, fs, ft is $(AMODE) & REL6=0 & prime=0x11 & format=0x16 & fct=0x2E & fd & fs & ft + unimpl +# 0100 0110 110t tttt ssss sddd dd10 1111 +:puu.ps fd, fs, ft is $(AMODE) & REL6=0 & prime=0x11 & format=0x16 & fct=0x2F & fd & fs & ft + unimpl + +# 1110 00bb bbbt tttt iiii iiii iiii iiii +:sc RTsrc, OFF_BASE is $(AMODE) & REL6=0 & prime=0x38 & OFF_BASE & RT & RTsrc { + *[ram]:4 OFF_BASE = RTsrc:$(SIZETO4); + RT = 1; +} + +@if ENDIAN == "big" +# 1010 10bb bbbt tttt iiii iiii iiii iiii +:swl RTsrc, OFF_BASE is $(AMODE) & REL6=0 & prime=0x2A & OFF_BASE & RTsrc { + tmpRT:4 = RTsrc:$(SIZETO4); + shft:$(ADDRSIZE) = OFF_BASE & 0x3; + addr:$(ADDRSIZE) = OFF_BASE - shft; + valOrig:4 = *(addr) & (0xffffffff << ((4-shft) * 8)); + valStore:4 = tmpRT >> (shft * 8); + *(addr) = valOrig | valStore; +} +# 1011 10bb bbbt tttt iiii iiii iiii iiii +:swr RTsrc, OFF_BASE is $(AMODE) & REL6=0 & prime=0x2E & OFF_BASE & RTsrc { + tmpRT:4 = RTsrc:$(SIZETO4); + shft:$(ADDRSIZE) = OFF_BASE & 0x3; + addr:$(ADDRSIZE) = OFF_BASE - shft; + valOrig:4 = *(addr) & (0xffffffff >> ((shft+1) * 8)); + valStore:4 = tmpRT << ((3-shft)*8); + *(addr) = valOrig | valStore; +} +:swle RTsrc, OFF_BASER6 is $(AMODE) & REL6=0 & prime=0x1F & fct=0x21 & bit6=0 & OFF_BASER6 & RTsrc & RT { + tmpRT:4 = RTsrc:$(SIZETO4); + shft:$(ADDRSIZE) = OFF_BASER6 & 0x3; + addr:$(ADDRSIZE) = OFF_BASER6 - shft; + valOrig:4 = *(addr) & (0xffffffff << ((4-shft) * 8)); + valStore:4 = tmpRT >> (shft * 8); + *(addr) = valOrig | valStore; +} +:swre RTsrc, OFF_BASER6 is $(AMODE) & REL6=0 & prime=0x1F & fct=0x22 & bit6=0 & OFF_BASER6 & RTsrc & RT { + tmpRT:4 = RTsrc:$(SIZETO4); + shft:$(ADDRSIZE) = OFF_BASER6 & 0x3; + addr:$(ADDRSIZE) = OFF_BASER6 - shft; + valOrig:4 = *(addr) & (0xffffffff >> ((shft+1) * 8)); + valStore:4 = tmpRT << ((3-shft)*8); + *(addr) = valOrig | valStore; +} + +@else +# 1010 10bb bbbt tttt iiii iiii iiii iiii +:swl RTsrc, OFF_BASE is $(AMODE) & REL6=0 & prime=0x2A & OFF_BASE & RTsrc { + tmpRT:4 = RTsrc:$(SIZETO4); + shft:$(ADDRSIZE) = OFF_BASE & 0x3; + addr:$(ADDRSIZE) = OFF_BASE - shft; + valOrig:4 = *(addr) & (0xffffffff << ((shft+1) * 8)); + valStore:4 = tmpRT >> ((3-shft) * 8); + *(addr) = valOrig | valStore; +} +# 1011 10bb bbbt tttt iiii iiii iiii iiii +:swr RTsrc, OFF_BASE is $(AMODE) & REL6=0 & prime=0x2E & OFF_BASE & RTsrc { + tmpRT:4 = RTsrc:$(SIZETO4); + shft:$(ADDRSIZE) = OFF_BASE & 0x3; + addr:$(ADDRSIZE) = OFF_BASE - shft; + valOrig:4 = *(addr) & (0xffffffff >> ((4-shft) * 8)); + valStore:4 = tmpRT << (shft*8); + *(addr) = valOrig | valStore; +} +:swle RTsrc, OFF_BASER6 is $(AMODE) & REL6=0 & prime=0x1F & fct=0x21 & bit6=0 & OFF_BASER6 & RTsrc & RT { + tmpRT:4 = RTsrc:$(SIZETO4); + shft:$(ADDRSIZE) = OFF_BASER6 & 0x3; + addr:$(ADDRSIZE) = OFF_BASER6 - shft; + valOrig:4 = *(addr) & (0xffffffff << ((shft+1) * 8)); + valStore:4 = tmpRT >> ((3-shft) * 8); + *(addr) = valOrig | valStore; +} +:swre RTsrc, OFF_BASER6 is $(AMODE) & REL6=0 & prime=0x1F & fct=0x22 & bit6=0 & OFF_BASER6 & RTsrc & RT { + tmpRT:4 = RTsrc:$(SIZETO4); + shft:$(ADDRSIZE) = OFF_BASER6 & 0x3; + addr:$(ADDRSIZE) = OFF_BASER6 - shft; + valOrig:4 = *(addr) & (0xffffffff >> ((4-shft) * 8)); + valStore:4 = tmpRT << (shft*8); + *(addr) = valOrig | valStore; +} + +@endif + +# When the analyzer finds a matching swl/swr pair, the pcode is simplified so that +# swl does all the storing while swr is a no-op +@if ENDIAN == "big" +:swl RTsrc, OFF_BASE is $(AMODE) & REL6=0 & prime=0x2A & OFF_BASE & RTsrc & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] { + *[ram]:4 OFF_BASE = RTsrc:$(SIZETO4); +} +:swr RTsrc, OFF_BASE is $(AMODE) & REL6=0 & prime=0x2E & OFF_BASE & RTsrc & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 0; ]{ +} +@else +:swl RTsrc, OFF_BASE is $(AMODE) & REL6=0 & prime=0x2A & OFF_BASE & RTsrc & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] { +} +:swr RTsrc, OFF_BASE is $(AMODE) & REL6=0 & prime=0x2E & OFF_BASE & RTsrc & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 0; ]{ + *[ram]:4 OFF_BASE = RTsrc:$(SIZETO4); +} +@endif + +# 0000 01ss sss0 1100 iiii iiii iiii iiii +:teqi RSsrc, simmed is $(AMODE) & REL6=0 & prime=1 & cond=0xC & RSsrc & simmed { + if (RSsrc != simmed) goto ; + trap(); + +} +# 0000 01ss sss0 1000 iiii iiii iiii iiii +:tgei RSsrc, simmed is $(AMODE) & REL6=0 & prime=1 & cond=8 & RSsrc & simmed { + if (RSsrc s< simmed) goto ; + trap(); + +} +# 0000 01ss sss0 1001 iiii iiii iiii iiii +:tgeiu RSsrc, simmed is $(AMODE) & REL6=0 & prime=1 & cond=9 & RSsrc & simmed { + if (RSsrc < simmed) goto ; + trap(); + +} +# 0000 01ss sss0 1010 iiii iiii iiii iiii +:tlti RSsrc, simmed is $(AMODE) & REL6=0 & prime=1 & cond=10 & RSsrc & simmed { + if (RSsrc s>= simmed) goto ; + trap(); + +} +# 0000 01ss sss0 1011 iiii iiii iiii iiii +:tltiu RSsrc, simmed is $(AMODE) & REL6=0 & prime=1 & cond=0xB & RSsrc & simmed { + if (RSsrc >= simmed) goto ; + trap(); + +} +# 0000 01ss sss0 1110 iiii iiii iiii iiii +:tnei RSsrc, simmed is $(AMODE) & REL6=0 & prime=1 & cond=0xE & RSsrc & simmed { + if (RSsrc == simmed) goto ; + trap(); + +} + +############################ +# +# MIPS64 Instructions to be included with all MIPS32 processors +# +############################ + +## Allow MIPS 64 instructions below for compilers +## using a 64-bit chip, but really keeping things to 32-bits +# 0110 00ss ssst tttt iiii iiii iiii iiii +:daddi RT, RSsrc, simmed is $(AMODE) & REL6=0 & prime=0x18 & RSsrc & RT & simmed { + RT = RSsrc + simmed; +} + +#### +# +# Release 6 semantics +# +#### + +:addiupc RSsrc, S19L2 is $(AMODE) & REL6=1 & prime=0x3B & bitz19=0 & RSsrc & S19L2 { + RSsrc = inst_start + sext(S19L2); +} + +:align RD, RS32src, RT32src, bp2 is $(AMODE) & REL6=1 & prime=0x1F & spec3=0x2 & fct=0x20 & bp2 & RS32src & RT32src & RD { + tmp:4 = RT32src << (8 * bp2); + tmp = tmp | (RS32src >> (32 - (8 * bp2))); + RD = sext(tmp); +} + +:aluipc RSsrc, S16L16 is $(AMODE) & REL6=1 & prime=0x3B & op=0x1F & RSsrc & S16L16 { + RSsrc = inst_start + sext(S16L16); + RSsrc = RSsrc & ~0xFFFF; +} + +:aui RTsrc, RSsrc, S16L16 is $(AMODE) & REL6=1 & prime=0x0F & RSsrc & RTsrc & S16L16 { + RTsrc = RSsrc + sext(S16L16); +} + +:auipc RSsrc, S16L16 is $(AMODE) & REL6=1 & prime=0x3B & op=0x1E & RSsrc & S16L16 { + RSsrc = inst_start + sext(S16L16); +} + +# 0000 0100 0001 0001 iiii iiii iiii iiii +:bal Rel16 is $(AMODE) & REL6=1 & prime=0x01 & cond=0x11 & rs=0 & Rel16 { + ra = inst_next; + delayslot(1); + call Rel16; +} + +:bal Rel16 is $(AMODE) & REL6=1 & prime=0x01 & cond=0x11 & rs=0 & off16=1 & Rel16 { + ra = inst_next; + delayslot(1); + goto Rel16; +} + +:balc Rel26 is $(AMODE) & REL6=1 & prime=0x3A & Rel26 { + ra = inst_next; + call Rel26; +} + +:bc Rel26 is $(AMODE) & REL6=1 & prime=0x32 & Rel26 { + goto Rel26; +} + +:bc2eqz op, Rel16 is $(AMODE) & REL6=1 & prime=0x12 & copop=0x09 & op & Rel16 { + tmp:1 = getCopCondition(2:1, op:1); + if (tmp == 0) goto inst_next; + goto Rel16; +} + +:bc2nez op, Rel16 is $(AMODE) & REL6=1 & prime=0x12 & copop=0x0D & op & Rel16 { + tmp:1 = getCopCondition(2:1, op:1); + if (tmp != 0) goto inst_next; + goto Rel16; +} + +:bad1 is $(AMODE) & REL6=1 & prime=0x06 & rs=0 & rt=0 unimpl +:blezalc RTsrc, Rel16 is $(AMODE) & REL6=1 & prime=0x06 & rs=0 & RTsrc & Rel16 { + if (RTsrc s> 0) goto inst_next; + ra = inst_next; + call Rel16; +} + +:bgezalc RTsrc, Rel16 is $(AMODE) & REL6=1 & prime=0x06 & rs=rt & rt!=0 & RTsrc & Rel16 { + if (RTsrc s< 0) goto inst_next; + ra = inst_next; + call Rel16; +} + +:bgeuc RSsrc, RTsrc, Rel16 is $(AMODE) & REL6=1 & prime=0x06 & rt!=0 & rs!=rt & RSsrc & RTsrc & Rel16 { + if (RSsrc >= RTsrc) goto Rel16; +} + +:bad2 is $(AMODE) & REL6=1 & prime=0x07 & rs=0 & rt=0 unimpl +:bgtzalc RTsrc, Rel16 is $(AMODE) & REL6=1 & prime=0x07 & rs=0 & RTsrc & Rel16 { + if (RTsrc s<= 0) goto inst_next; + ra = inst_next; + call Rel16; +} + +:bltzalc RTsrc, Rel16 is $(AMODE) & REL6=1 & prime=0x07 & rs=rt & rt!=0 & RTsrc & Rel16 { + if (RTsrc s>= 0) goto inst_next; + ra = inst_next; + call Rel16; +} + +:bltuc RSsrc, RTsrc, Rel16 is $(AMODE) & REL6=1 & prime=0x07 & rt!=0 & rs!=rt & RSsrc & RTsrc & Rel16 { + if (RSsrc < RTsrc) goto Rel16; +} + + +:beqzalc RTsrc, Rel16 is $(AMODE) & REL6=1 & prime=0x08 & rs=0 & rt!=0 & RTsrc & Rel16 { + if (RTsrc s> 0) goto inst_next; + ra = inst_next; + call Rel16; +} + +:beqc RSsrc, RTsrc, Rel16 is $(AMODE) & REL6=1 & prime=0x08 & rs!=0 & rs 0x7FFFFFFF) || (tmpS s< -2147483648); +@if REGSIZE == "8" + tmpF = tmpF || (RTsrc s> 0x7FFFFFFF) || (RTsrc s< -2147483648) || (RSsrc s> 0x7FFFFFFF) || (RSsrc s< -2147483648); +@endif + if (tmpF == 1) goto Rel16; +} + +:bnezalc RTsrc, Rel16 is $(AMODE) & REL6=1 & prime=0x18 & rs=0 & rt!=0 & RTsrc & Rel16 { + if (RTsrc == 0) goto inst_next; + ra = inst_next; + call Rel16; +} + +:bnec RSsrc, RTsrc, Rel16 is $(AMODE) & REL6=1 & prime=0x18 & rs!=0 & rs 0x7FFFFFFF) || (tmpS s< -2147483648); +@if REGSIZE == "8" + tmpF = tmpF || (RTsrc s> 0x7FFFFFFF) || (RTsrc s< -2147483648) || (RSsrc s> 0x7FFFFFFF) || (RSsrc s< -2147483648); +@endif + if (tmpF == 0) goto Rel16; +} + +:bad3 is $(AMODE) & REL6=1 & prime=0x16 & rs=0 & rt=0 unimpl +:blezc RTsrc, Rel16 is $(AMODE) & REL6=1 & prime=0x16 & rs=0 & rt!=0 & RTsrc & Rel16 { + if (RTsrc s<= 0) goto Rel16; +} +:bgezc RTsrc, Rel16 is $(AMODE) & REL6=1 & prime=0x16 & rs=rt & rt!=0 & RTsrc & Rel16 { + if (RTsrc s>= 0) goto Rel16; +} +:bgec RSsrc, RTsrc, Rel16 is $(AMODE) & REL6=1 & prime=0x16 & RSsrc & RTsrc & Rel16 { + if (RSsrc s>= RTsrc) goto Rel16; +} + + +:bad4 is $(AMODE) & REL6=1 & prime=0x17 & rs=0 & rt=0 unimpl +:bgtzc RTsrc, Rel16 is $(AMODE) & REL6=1 & prime=0x17 & rs=0 & rt!=0 & RTsrc & Rel16 { + if (RTsrc s> 0) goto Rel16; +} + +:bltzc RTsrc, Rel16 is $(AMODE) & REL6=1 & prime=0x17 & rs=rt & rt!=0 & RTsrc & Rel16 { + if (RTsrc s< 0) goto Rel16; +} + +:bltc RSsrc, RTsrc, Rel16 is $(AMODE) & REL6=1 & prime=0x17 & RSsrc & RTsrc & Rel16 { + if (RSsrc s< RTsrc) goto Rel16; +} + +# The jic instruction takes care of the 'bad' case here +:beqzc RSsrc, Rel21 is $(AMODE) & REL6=1 & prime=0x36 & RSsrc & Rel21 { + if (RSsrc == 0) goto Rel21; +} + +# The jialc instruction takes care of the 'bad' case here +:bnezc RSsrc, Rel21 is $(AMODE) & REL6=1 & prime=0x3E & RSsrc & Rel21 { + if (RSsrc != 0) goto Rel21; +} + +:bitswap RD, RT32src is $(AMODE) & REL6=1 & prime=0x1F & zero21=0 & fct2=0 & bshfl=0x20 & RT32src & RD { + tmp:4 = bitSwap(RT32src); + RD = sext(tmp); +} + +:clo RD, RSsrc is $(AMODE) & REL6=1 & prime=0x00 & op=0 & sa=0x1 & fct=0x11 & RD & RSsrc { + RD = lzcount( ~RSsrc ); +} + +:clz RD, RSsrc is $(AMODE) & REL6=1 & prime=0x00 & op=0 & sa=0x1 & fct=0x10 & RD & RSsrc { + RD = lzcount( RSsrc ); +} + +:div RD, RS32src, RT32src is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1A & fct2=0x02 & RD & RS32src & RT32src { + tmp:4 = RS32src s/ RT32src; + RD = sext(tmp); +} + +:mod RD, RS32src, RT32src is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1A & fct2=0x03 & RD & RS32src & RT32src { + tmp:4 = RS32src s% RT32src; + RD = sext(tmp); +} + +:divu RD, RS32src, RT32src is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1B & fct2=0x02 & RD & RS32src & RT32src { + tmp:4 = RS32src / RT32src; + RD = sext(tmp); +} + +:modu RD, RS32src, RT32src is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1B & fct2=0x03 & RD & RS32src & RT32src { + tmp:4 = RS32src % RT32src; + RD = sext(tmp); +} + +:dvp RT is $(AMODE) & REL6=1 & prime=0x10 & mfmc0=0x0B & fct=0x24 & RT & RD0 & zero5=0 & zero4=0 { + disableProcessor(RT); +} + +:evp RT is $(AMODE) & REL6=1 & prime=0x10 & mfmc0=0x0B & fct=0x04 & RT & RD0 & zero5=0 & zero4=0 { + enableProcessor(RT); +} + +# NOTE: Unlike almost every other branch/jump that has an immediate, the immediate is *IS NOT* shifted. This allows +# this instruction to serve same function as jalx in pre-6. +:jialc RTsrc, simmed is $(AMODE) & REL6=1 & prime=0x3E & jsub=0x00 & RTsrc & simmed { + build RTsrc; + tmp:$(REGSIZE) = sext(simmed:2) + RTsrc; + JXWritePC(tmp); + ra = inst_next; + call [pc]; +} + +:jic RTsrc, simmed is $(AMODE) & REL6=1 & prime=0x36 & jsub=0x00 & RTsrc & simmed { + build RTsrc; + tmp:$(REGSIZE) = sext(simmed:2) + RTsrc; + JXWritePC(tmp); + goto [pc]; +} + +:jic RTsrc, simmed is $(AMODE) & REL6=1 & prime=0x36 & jsub=0x00 & RTsrc & simmed & immed=0x00 & rt=0x1f { + build RTsrc; + JXWritePC(ra); + return [pc]; +} + +@ifndef COPR_C +:ldc2 RTsrc, simmed11(baser6) is $(AMODE) & REL6=1 & prime=0x12 & copop=0x0E & simmed11 & baser6 & RTsrc { + tmp:$(REGSIZE) = simmed11; + tmp = tmp + baser6; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + setCopReg(2:1, RTsrc, *[ram]:8 tmpa); +} +@endif + +:ll RT, OFF_BASER6 is $(AMODE) & REL6=1 & prime=0x1F & fct=0x36 & bit6=0 & OFF_BASER6 & RT { + RT = sext(*[ram]:4 OFF_BASER6); +} + +:llx RT, OFF_BASER6 is $(AMODE) & REL6=1 & prime=0x1F & fct=0x36 & bit6=1 & OFF_BASER6 & RT { + RT = sext(*[ram]:4 OFF_BASER6); +} + +:llxe RT, OFF_BASER6 is $(AMODE) & REL6=1 & prime=0x1F & fct=0x27 & bit6=1 & OFF_BASER6 & RT { + RT = sext(*[ram]:4 OFF_BASER6); +} + +:lsa RD, RS32src, RT32src, SAV is $(AMODE) & REL6=1 & prime=0x00 & fct=0x05 & spec3=0 & SAV & RD & RS32src & RT32src { + tmp:4 = (RS32src << SAV) + RT32src; + RD = sext(tmp); +} + +@ifndef COPR_C +:lwc2 RTsrc, simmed11(baser6) is $(AMODE) & REL6=1 & prime=0x12 & copop=0x0A & simmed11 & baser6 & RTsrc { + tmp:$(REGSIZE) = simmed11; + tmp = tmp + baser6; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + setCopReg( 2:1, RTsrc, *[ram]:4 tmpa); +} +@endif + +:lwpc RS, S19L2 is $(AMODE) & REL6=1 & prime=0x3B & pcrel=0x1 & RS & S19L2 { + tmp:$(REGSIZE) = inst_start + sext(S19L2); + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + RS = sext(*[ram]:4 tmpa); +} + +:mul RD, RS32src, RT32src is $(AMODE) & REL6=1 & prime=0x00 & fct=0x18 & fct2=0x02 & RD & RS32src & RT32src { + tmpS:8 = sext(RS32src); + tmpT:8 = sext(RT32src); + tmpS = tmpS * tmpT; + tmp:4 = tmpS[0,32]; + RD = sext(tmp); +} + +:muh RD, RS32src, RT32src is $(AMODE) & REL6=1 & prime=0x00 & fct=0x18 & fct2=0x03 & RD & RS32src & RT32src { + tmpS:8 = sext(RS32src); + tmpT:8 = sext(RT32src); + tmpS = tmpS * tmpT; + tmp:4 = tmpS[32,32]; + RD = sext(tmp); +} + +:mulu RD, RS32src, RT32src is $(AMODE) & REL6=1 & prime=0x00 & fct=0x19 & fct2=0x02 & RD & RS32src & RT32src { + tmpS:8 = zext(RS32src); + tmpT:8 = zext(RT32src); + tmpS = tmpS * tmpT; + tmp:4 = tmpS[0,32]; + RD = sext(tmp); +} + +:muhu RD, RS32src, RT32src is $(AMODE) & REL6=1 & prime=0x00 & fct=0x19 & fct2=0x03 & RD & RS32src & RT32src { + tmpS:8 = zext(RS32src); + tmpT:8 = zext(RT32src); + tmpS = tmpS * tmpT; + tmp:4 = tmpS[32,32]; + RD = sext(tmp); +} + +:scx RTsrc, OFF_BASER6 is $(AMODE) & REL6=1 & prime=0x1F & fct=0x26 & bit6=1 & OFF_BASER6 & RTsrc { + *[ram]:4 OFF_BASER6 = RTsrc:$(SIZETO4); +} + +:scxe RTsrc, OFF_BASER6 is $(AMODE) & REL6=1 & prime=0x1F & fct=0x1E & bit6=1 & OFF_BASER6 & RTsrc { + *[ram]:4 OFF_BASER6 = RTsrc:$(SIZETO4); + RTsrc = 1; +} + +:seleqz RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x35 & fct2=0x00 & RD & RSsrc & RTsrc { + # We use tmp to cover case where rs and rd are the same reg + tmps:$(REGSIZE) = RSsrc; + tmpt:$(REGSIZE) = RTsrc; + RD = 0; + if (tmpt != 0) goto ; + RD = tmps; + +} + +:selnez RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x37 & fct2=0x00 & RD & RSsrc & RTsrc { + # We use tmp to cover case where rs and rd are the same reg + tmps:$(REGSIZE) = RSsrc; + tmpt:$(REGSIZE) = RTsrc; + RD = 0; + if (tmpt == 0) goto ; + RD = tmps; + +} + +:sigrie immed is $(AMODE) & REL6=1 & prime=0x01 & zero21=0 & cond=0x17 & immed { + signalReservedInstruction(immed:2); +} + + +@include "mipsfloat.sinc" diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32R6.pspec b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32R6.pspec new file mode 100644 index 0000000..6bcce3f --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32R6.pspec @@ -0,0 +1,79 @@ + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32R6be.slaspec b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32R6be.slaspec new file mode 100644 index 0000000..bb06d70 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32R6be.slaspec @@ -0,0 +1,11 @@ +# SLA specification file for MIPS32 big endian + +@define ENDIAN "big" +@define FREGSIZE "8" +@define ISA_VARIANT "" + +@include "mips.sinc" +@include "mips32Instructions.sinc" +@include "mips16.sinc" +@include "mipsmicro.sinc" +@include "mips_dsp.sinc" diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32R6le.slaspec b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32R6le.slaspec new file mode 100644 index 0000000..5355fd4 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32R6le.slaspec @@ -0,0 +1,11 @@ +# SLA specification file for MIPS32 little endian + +@define ENDIAN "little" +@define FREGSIZE "8" +@define ISA_VARIANT "" + +@include "mips.sinc" +@include "mips32Instructions.sinc" +@include "mips16.sinc" +@include "mipsmicro.sinc" +@include "mips_dsp.sinc" \ No newline at end of file diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32_fp64.cspec b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32_fp64.cspec new file mode 100644 index 0000000..2e061b2 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32_fp64.cspec @@ -0,0 +1,88 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32be.cspec b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32be.cspec new file mode 100644 index 0000000..3c52fcd --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32be.cspec @@ -0,0 +1,107 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32be.slaspec b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32be.slaspec new file mode 100644 index 0000000..76b9077 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32be.slaspec @@ -0,0 +1,12 @@ +# SLA specification file for MIPS32 big endian + +@define ENDIAN "big" +@define FREGSIZE "4" +@define ISA_VARIANT "" + +@include "mips.sinc" +@include "mips32Instructions.sinc" +@include "mips16.sinc" +@include "mipsmicro.sinc" +@include "mips_mt.sinc" +@include "mips_dsp.sinc" diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32be_eabi.cspec b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32be_eabi.cspec new file mode 100644 index 0000000..7236a93 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32be_eabi.cspec @@ -0,0 +1,123 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32le.cspec b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32le.cspec new file mode 100644 index 0000000..c439a5d --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32le.cspec @@ -0,0 +1,106 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32le.slaspec b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32le.slaspec new file mode 100644 index 0000000..3620d20 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32le.slaspec @@ -0,0 +1,12 @@ +# SLA specification file for MIPS32 little endian + +@define ENDIAN "little" +@define FREGSIZE "4" +@define ISA_VARIANT "" + +@include "mips.sinc" +@include "mips32Instructions.sinc" +@include "mips16.sinc" +@include "mipsmicro.sinc" +@include "mips_mt.sinc" +@include "mips_dsp.sinc" diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32le_eabi.cspec b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32le_eabi.cspec new file mode 100644 index 0000000..f4a6692 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32le_eabi.cspec @@ -0,0 +1,123 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32micro.pspec b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32micro.pspec new file mode 100644 index 0000000..2db2de7 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips32micro.pspec @@ -0,0 +1,79 @@ + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64.cspec b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64.cspec new file mode 100644 index 0000000..e654191 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64.cspec @@ -0,0 +1,111 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64.pspec b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64.pspec new file mode 100644 index 0000000..0dca002 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64.pspec @@ -0,0 +1,79 @@ + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64Instructions.sinc b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64Instructions.sinc new file mode 100644 index 0000000..786cd32 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64Instructions.sinc @@ -0,0 +1,444 @@ + +############################ +# +# MIPS64 Instructions +# +############################ + +# 0111 00ss ssst tttt dddd d000 0010 0101 +:dclo RD, RSsrc is $(AMODE) & ((REL6=0 & prime=0x1C & sa=0x0 & fct=0x25) | (REL6=1 & prime=0x00 & sa=0x1 & fct=0x13 & op=0)) & RD & RSsrc { + RD = lzcount( ~RSsrc ); +} +# 0111 00ss ssst tttt dddd d000 0010 0100 +:dclz RD, RSsrc is $(AMODE) & ((REL6=0 & prime=0x1C & sa=0x0 & fct=0x24) | (REL6=1 & prime=0x00 & sa=0x1 & fct=0x12 & op=0)) & RD & RSsrc { + RD = lzcount( RSsrc ); +} + +# 0111 11ss ssst tttt mmmm mLLL LL00 0011 +:dext RT, RSsrc, lsb, ExtSize is $(AMODE) & prime=0x1F & fct=0x03 & RT & RSsrc & lsb & msbd & ExtSize { + val:8 = (RSsrc >> lsb); + val = val & (0xffffffff >> (32 - ExtSize)); + RT = zext(val); +} + +# 0111 11ss ssst tttt mmmm mLLL LL00 0001 +:dextm RT, RSsrc, lsb, DextmSize is $(AMODE) & prime=0x1F & fct=0x01 & RT & RSsrc & lsb & msbd & DextmSize { + val:8 = (RSsrc >> lsb); + val = val & (0xffffffffffffffff >> (64 - DextmSize)); + RT = zext(val); +} +# 0111 11ss ssst tttt mmmm mLLL LL00 0010 +:dextu RT, RSsrc, DXuPos, ExtSize is $(AMODE) & prime=0x1F & fct=0x02 & RT & RSsrc & lsb & msbd & DXuPos & ExtSize { + val:8 = (RSsrc >> DXuPos); + val = val & (0xffffffff >> (32 - ExtSize)); + RT = zext(val); +} + +# 0111 11ss ssst tttt mmmm mLLL LL00 0111 +:dins RT, RSsrc, lsb, InsSize is $(AMODE) & prime=0x1F & fct=0x07 & RT & RTsrc & RSsrc & lsb & msbd & InsSize { + tmpa:$(REGSIZE) = -1; + tmpa = tmpa >> ($(REGSIZE)*8 - InsSize); + tmpb:$(REGSIZE) = RSsrc & tmpa; + tmpa = tmpa << lsb; + tmpa = ~tmpa; + tmpb = tmpb << lsb; + RT = (RT & tmpa) | tmpb; +} + +# 0111 11ss ssst tttt mmmm mLLL LL00 0101 +:dinsm RT, RSsrc, lsb, DinsXSize is $(AMODE) & prime=0x1F & fct=0x05 & RT & RTsrc & RSsrc & lsb & msbd & DinsXSize { + tmpa:$(REGSIZE) = -1; + tmpa = tmpa >> ($(REGSIZE)*8 - DinsXSize); + tmpb:$(REGSIZE) = RSsrc & tmpa; + tmpa = tmpa << lsb; + tmpa = ~tmpa; + tmpb = tmpb << lsb; + RT = (RT & tmpa) | tmpb; +} + +# 0111 11ss ssst tttt mmmm mLLL LL00 0110 +:dinsu RT, RSsrc, DXuPos, InsSize is $(AMODE) & prime=0x1F & fct=0x06 & RT & RTsrc & RSsrc & lsb & msbd & DXuPos & InsSize { + tmpa:$(REGSIZE) = -1; + tmpa = tmpa >> ($(REGSIZE)*8 - InsSize); + tmpb:$(REGSIZE) = RSsrc & tmpa; + tmpa = tmpa << DXuPos; + tmpa = ~tmpa; + tmpb = tmpb << DXuPos; + RT = (RT & tmpa) | tmpb; +} + +# 0100 0000 001t tttt dddd d000 0000 0eee +:dmfc0 RT, RD0 is $(AMODE) & prime=16 & copop=1 & RT & RD0 & zero6=0 { + RT = RD0; +} +:dmfc1 RT, fs is $(AMODE) & prime=17 & copop=1 & RT & fs & bigfunct=0 { + RT = fs; +} +:dmfc2 RT, immed is $(AMODE) & prime=18 & copop=1 & RT & immed { + RT = getCopReg(2:1, immed:4); +} + +# 0100 0000 101t tttt dddd d000 0000 0eee +:dmtc0 RTsrc, RD0 is $(AMODE) & prime=16 & copop=5 & RTsrc & RD0 & zero6=0 { + RD0 = RTsrc; +} +# 0100 0100 101t tttt ssss s000 0000 0000 +:dmtc1 RTsrc, fs is $(AMODE) & prime=17 & copop=5 & RTsrc & fs & bigfunct=0 { + fs = RTsrc; +} +:dmtc2 RTsrc, immed is $(AMODE) & prime=18 & copop=5 & RTsrc & immed { + setCopReg(2:1, immed:4, RTsrc); +} + +# 0000 0000 001t tttt dddd daaa aa11 1010 +:drotr RD, RTsrc, sa is $(AMODE) & prime=0x0 & zero1=0x0 & bit21=0x1 & fct=0x3A & RD & RTsrc & sa { + tmp:8 = RTsrc; + tmp1:8 = tmp >> sa; + tmp2:8 = tmp << (64 - sa); + RD = tmp1 + tmp2; +} +# 0000 0000 001t tttt dddd daaa aa11 1110 +:drotr32 RD, RTsrc, sa is $(AMODE) & prime=0x0 & zero1=0x0 & bit21=0x1 & fct=0x3E & RD & RTsrc & sa { + shift:1 = sa + 32; + tmp:8 = RTsrc; + tmp1:8 = tmp >> shift; + tmp2:8 = tmp << (64 - shift); + RD = tmp1 + tmp2; +} +# 0000 00ss ssst tttt dddd d000 0101 0110 +:drotrv RD, RTsrc, RSsrc is $(AMODE) & prime=0x0 & zero2=0x0 & bit6=0x1 & fct=0x16 & RD & RTsrc & RSsrc { + shift:8 = RSsrc & 0x3f; + tmp:8 = RTsrc; + tmp1:8 = tmp >> shift; + tmp2:8 = tmp << (32 - shift); + RD = tmp1 + tmp2; +} + +# 0111 1100 000t tttt dddd d000 1010 0100 +:dsbh RD, RTsrc is $(AMODE) & prime=0x1F & rs=0x0 & fct2=0x02 & fct=0x24 & RD & RTsrc { + tmp1:8 = RTsrc & 0xff; + tmp2:8 = (RTsrc >> 8) & 0xff; + tmp3:8 = (RTsrc >> 16) & 0xff; + tmp4:8 = (RTsrc >> 24) & 0xff; + tmp5:8 = (RTsrc >> 32) & 0xff; + tmp6:8 = (RTsrc >> 40) & 0xff; + tmp7:8 = (RTsrc >> 48) & 0xff; + tmp8:8 = (RTsrc >> 56) & 0xff; + RD = (tmp7 << 56) | (tmp8 << 48) | (tmp5 << 40) | (tmp6 << 32) + | (tmp3 << 24) | (tmp4 << 16) | (tmp1 << 8) | (tmp2); +} +# 0111 1100 000t tttt dddd d001 0110 0100 +:dshd RD, RTsrc is$(AMODE) & prime=0x1F & rs=0x0 & fct2=0x05 & fct=0x24 & RD & RTsrc { + tmp1:8 = RTsrc & 0xffff; + tmp2:8 = (RTsrc >> 16) & 0xffff; + tmp3:8 = (RTsrc >> 32) & 0xffff; + tmp4:8 = (RTsrc >> 48) & 0xffff; + RD = (tmp1 << 48) | (tmp2 << 32) | (tmp3 << 16) | tmp4; +} + +# 0000 0000 000t tttt dddd daaa aa11 1000 +:dsll RD, RTsrc, sa is $(AMODE) & prime=0 & fct=56 & rs=0 & RTsrc & RD & sa { + RD = RTsrc << sa; +} +# 0000 0000 000t tttt dddd daaa aa11 1100 +:dsll32 RD, RTsrc, sa is $(AMODE) & prime=0 & fct=60 & rs=0 & RTsrc & RD & sa { + RD = RTsrc << (sa + 32); +} +# 0000 00ss ssst tttt dddd d000 0001 0100 +:dsllv RD, RTsrc, RSsrc is $(AMODE) & prime=0 & fct=20 & RSsrc & RTsrc & RD & sa=0 { + RD = RTsrc << RSsrc; +} +# 0000 0000 000t tttt dddd daaa aa11 1011 +:dsra RD, RTsrc, sa is $(AMODE) & prime=0 & fct=59 & rs=0 & RTsrc & RD & sa { + RD = RTsrc s>> sa; +} +# 0000 0000 000t tttt dddd daaa aa11 1111 +:dsra32 RD, RTsrc, sa is $(AMODE) & prime=0 & fct=63 & rs=0 & RTsrc & RD & sa { + RD = RTsrc s>> (sa + 32); +} +# 0000 00ss ssst tttt dddd d000 0001 0111 +:dsrav RD, RTsrc, RSsrc is $(AMODE) & prime=0 & fct=23 & RSsrc & RTsrc & RD & sa=0 { + RD = RTsrc s>> RSsrc; +} +# 0000 0000 000t tttt dddd daaa aa11 1010 +:dsrl RD, RTsrc, sa is $(AMODE) & prime=0 & fct=58 & rs=0 & RTsrc & RD & sa { + RD = RTsrc >> sa; +} +# 0000 0000 000t tttt dddd daaa aa11 1110 +:dsrl32 RD, RTsrc, sa is $(AMODE) & prime=0 & fct=62 & rs=0 & RTsrc & RD & sa { + RD = RTsrc >> (sa + 32); +} +# 0000 00ss ssst tttt dddd d000 0101 0110 +:dsrlv RD, RTsrc, RSsrc is $(AMODE) & prime=0 & fct=22 & RSsrc & RTsrc & RD & sa=0 { + RD = RTsrc >> RSsrc; +} + +# 0000 00ss ssst tttt dddd d000 0010 1110 +:dsub RD, RSsrc, RTsrc is $(AMODE) & prime=0 & fct=46 & RSsrc & RTsrc & RD & sa=0 { + RD = RSsrc - RTsrc; +} +# 0000 00ss ssst tttt dddd d000 0010 1111 +:dsubu RD, RSsrc, RTsrc is $(AMODE) & prime=0 & fct=47 & RSsrc & RTsrc & RD & sa=0 { + RD = RSsrc - RTsrc; +} + +# 1101 11bb bbbt tttt iiii iiii iiii iiii +:ld RT, OFF_BASE is $(AMODE) & prime=55 & OFF_BASE & RT { + RT = *[ram]:8 OFF_BASE; +} + +@if ENDIAN == "big" +# 0110 10bb bbbt tttt iiii iiii iiii iiii +:ldl RT, OFF_BASE is $(AMODE) & prime=26 & OFF_BASE & RT { + shft:$(ADDRSIZE) = OFF_BASE & 0x7; + addr:$(ADDRSIZE) = OFF_BASE - shft; + valOrig:8 = RT & (0xffffffffffffffff >> ((8-shft) * 8)); + valLoad:8 = *(addr) << (shft * 8); + RT = valLoad | valOrig; +} +# 0110 11bb bbbt tttt iiii iiii iiii iiii +:ldr RT, OFF_BASE is $(AMODE) & prime=27 & OFF_BASE & RT { + # no-op + # see ldl instruction + + shft:$(ADDRSIZE) = OFF_BASE & 0x7; + addr:$(ADDRSIZE) = OFF_BASE - shft; + valOrig:8 = RT & (0xffffffffffffffff << ((shft+1) * 8)); + valLoad:8 = *(addr) >> ((7-shft) * 8); + RT = valOrig | valLoad; +} +@else # ENDIAN == "little +# 0110 10bb bbbt tttt iiii iiii iiii iiii +:ldl RT, OFF_BASE is $(AMODE) & prime=26 & OFF_BASE & RT { + shft:$(ADDRSIZE) = OFF_BASE & 0x7; + addr:$(ADDRSIZE) = OFF_BASE - shft; + valOrig:8 = RT & (0xffffffffffffffff >> ((shft+1) * 8)); + valLoad:8 = *(addr) << ((7-shft) * 8); + RT = valLoad | valOrig; +} +# 0110 11bb bbbt tttt iiii iiii iiii iiii +:ldr RT, OFF_BASE is $(AMODE) & prime=27 & OFF_BASE & RT { + # no-op + # see ldl instruction + + shft:$(ADDRSIZE) = OFF_BASE & 0x7; + addr:$(ADDRSIZE) = OFF_BASE - shft; + valOrig:8 = RT & (0xffffffffffffffff << ((8-shft) * 8)); + valLoad:8 = *(addr) >> (shft * 8); + RT = valOrig | valLoad; +} +@endif # ENDIAN + +# ldl and ldr almost always come in pairs. +# When the analyzer does finds a matching ldl/ldr pair, the pcode is simplified so that +# ldl does all the loading while ldr is a no-op +@if ENDIAN == "big" +:ldl RT, OFF_BASE is $(AMODE) & prime=26 & OFF_BASE & RT & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] { + RT = *[ram]:8 OFF_BASE; +} +:ldr RT, OFF_BASE is $(AMODE) & prime=27 & OFF_BASE & RT & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 0; ] { +} +@else +:ldl RT, OFF_BASE is $(AMODE) & prime=26 & OFF_BASE & RT & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] { +} +:ldr RT, OFF_BASE is $(AMODE) & prime=27 & OFF_BASE & RT & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 0; ] { + RT = *[ram]:8 OFF_BASE; +} +@endif + +# 1101 00bb bbbt tttt iiii iiii iiii iiii +:lld RT, OFF_BASE is $(AMODE) & prime=52 & OFF_BASE & RT { + RT = *[ram]:8 OFF_BASE; +} +# 1001 11bb bbbt tttt iiii iiii iiii iiii +:lwu RT, OFF_BASE is $(AMODE) & prime=39 & OFF_BASE & RT { + RT = zext( *[ram]:4 OFF_BASE ); +} + +# 1111 00bb bbbt tttt iiii iiii iiii iiii +:scd RTsrc, OFF_BASE is $(AMODE) & prime=60 & OFF_BASE & RT & RTsrc { + *[ram]:8 OFF_BASE = RTsrc; + RT = 1; +} +# 1111 11bb bbbt tttt iiii iiii iiii iiii +:sd RTsrc, OFF_BASE is $(AMODE) & prime=63 & OFF_BASE & RTsrc { + *[ram]:8 OFF_BASE = RTsrc; +} + +@if ENDIAN == "big" +# 1011 00bb bbbt tttt iiii iiii iiii iiii +:sdl RTsrc, OFF_BASE is $(AMODE) & prime=44 & OFF_BASE & RTsrc { + shft:$(ADDRSIZE) = OFF_BASE & 0x7; + addr:$(ADDRSIZE) = OFF_BASE - shft; + valOrig:8 = *(addr) & (0xffffffffffffffff << ((8-shft) * 8)); + valStore:8 = RTsrc >> (shft * 8); + *(addr) = valOrig | valStore; +} +# 1011 01bb bbbt tttt iiii iiii iiii iiii +:sdr RTsrc, OFF_BASE is $(AMODE) & prime=45 & OFF_BASE & RTsrc { + shft:$(ADDRSIZE) = OFF_BASE & 0x7; + addr:$(ADDRSIZE) = OFF_BASE - shft; + valOrig:8 = *(addr) & (0xffffffffffffffff >> ((shft+1) * 8)); + valStore:8 = RTsrc << ((7-shft)*8); + *(addr) = valStore | valOrig; +} +@else # ENDIAN == "little +# 1011 00bb bbbt tttt iiii iiii iiii iiii +:sdl RTsrc, OFF_BASE is $(AMODE) & prime=44 & OFF_BASE & RTsrc { + shft:$(ADDRSIZE) = OFF_BASE & 0x7; + addr:$(ADDRSIZE) = OFF_BASE - shft; + valOrig:8 = *(addr) & (0xffffffffffffffff << ((shft+1) * 8)); + valStore:8 = RTsrc >> ((7-shft) * 8); + *(addr) = valOrig | valStore; +} +# 1011 01bb bbbt tttt iiii iiii iiii iiii +:sdr RTsrc, OFF_BASE is $(AMODE) & prime=45 & OFF_BASE & RTsrc { + shft:$(ADDRSIZE) = OFF_BASE & 0x7; + addr:$(ADDRSIZE) = OFF_BASE - shft; + valOrig:8 = *(addr) & (0xffffffffffffffff >> ((8-shft) * 8)); + valStore:8 = RTsrc << (shft*8); + *(addr) = valStore | valOrig; +} +@endif # ENDIAN + +# When the analyzer finds a matching sdl/sdr pair, the pcode is simplified so that +# sdl does all the storing while sdr is a no-op +@if ENDIAN == "big" +:sdl RTsrc, OFF_BASE is $(AMODE) & prime=44 & OFF_BASE & RTsrc & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] { + *[ram]:8 OFF_BASE = RTsrc; +} +:sdr RTsrc, OFF_BASE is $(AMODE) & prime=45 & OFF_BASE & RTsrc & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 0; ] { +} +@else +:sdl RTsrc, OFF_BASE is $(AMODE) & prime=44 & OFF_BASE & RTsrc & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] { +} +:sdr RTsrc, OFF_BASE is $(AMODE) & prime=45 & OFF_BASE & RTsrc & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 0; ] { + *[ram]:8 OFF_BASE = RTsrc; +} +@endif +#### +# +# Pre-6 semantics +# +#### +# 0000 00ss ssst tttt 0000 0000 0001 1110 +:ddiv RSsrc, RTsrc is $(AMODE) & REL6=0 & prime=0 & fct=30 & RSsrc & RTsrc & rd=0 & sa=0 { + lo = RSsrc s/ RTsrc; + hi = RSsrc s% RTsrc; +} +# 0000 00ss ssst tttt 0000 0000 0001 1111 +:ddivu RSsrc, RTsrc is $(AMODE) & REL6=0 & prime=0 & fct=31 & RSsrc & RTsrc & rd=0 & sa=0 { + lo = RSsrc / RTsrc; + hi = RSsrc % RTsrc; +} + +# 0000 00ss ssst tttt 0000 0000 0001 1100 +:dmult RSsrc, RTsrc is $(AMODE) & REL6=0 & prime=0 & fct=28 & RSsrc & RTsrc & rd=0 & sa=0 { + prod:16 = sext( RSsrc ) * sext( RTsrc ); + lo = prod(0); + hi = prod(8); +} +# 0000 00ss ssst tttt 0000 0000 0001 1101 +:dmultu RSsrc, RTsrc is $(AMODE) & REL6=0 & prime=0 & fct=29 & RSsrc & RTsrc & rd=0 & sa=0 { + prod:16 = zext( RSsrc ) * zext( RTsrc ); + lo = prod(0); + hi = prod(8); +} + + +#### +# +# Release 6 semantics +# +#### +:dalign RD, RSsrc, RTsrc, bp3 is $(AMODE) & REL6=1 & prime=0x1F & spec2=0x1 & fct=0x24 & bp3 & RSsrc & RTsrc & RD { + tmp:8 = RTsrc << (8 * bp3); + tmp = tmp | (RSsrc >> (64 - (8 * bp3))); + RD = sext(tmp); +} + +:daui RTsrc, RSsrc, S16L16 is $(AMODE) & REL6=1 & prime=0x1D & rs!=0 & RSsrc & RTsrc & S16L16 { + RTsrc = RSsrc + sext(S16L16); +} + +:dahi RSsrc, S16L32 is $(AMODE) & REL6=1 & prime=0x01 & op=0x06 & RSsrc & S16L32 { + RSsrc = RSsrc + sext(S16L32); +} + +:dati RSsrc, S16L48 is $(AMODE) & REL6=1 & prime=0x01 & op=0x1E & RSsrc & S16L48 { + RSsrc = RSsrc + sext(S16L48); +} + +:dbitswap RD, RTsrc is $(AMODE) & REL6=1 & prime=0x1F & zero21=0 & fct2=0 & bshfl=0x24 & RTsrc & RD { + RD = bitSwap(RTsrc); +} + +:ddiv RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1E & fct2=0x02 & RD & RSsrc & RTsrc { + RD = RSsrc s/ RTsrc; +} + +:dmod RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1E & fct2=0x03 & RD & RSsrc & RTsrc { + RD = RSsrc s% RTsrc; +} + +:ddivu RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1F & fct2=0x02 & RD & RSsrc & RTsrc { + RD = RSsrc / RTsrc; +} + +:dmodu RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1F & fct2=0x03 & RD & RSsrc & RTsrc { + RD = RSsrc % RTsrc; +} + +:dmul RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1C & fct2=0x02 & RD & RSsrc & RTsrc { + tmpS:16 = sext(RSsrc); + tmpT:16 = sext(RTsrc); + tmpS = tmpS * tmpT; + RD = tmpS[0,64]; +} + +:dmuh RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1C & fct2=0x03 & RD & RSsrc & RTsrc { + tmpS:16 = sext(RSsrc); + tmpT:16 = sext(RTsrc); + tmpS = tmpS * tmpT; + RD = tmpS[64,64]; +} + +:dmulu RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1D & fct2=0x02 & RD & RSsrc & RTsrc { + tmpS:16 = zext(RSsrc); + tmpT:16 = zext(RTsrc); + tmpS = tmpS * tmpT; + RD = tmpS[0,64]; +} + +:dmuhu RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1D & fct2=0x03 & RD & RSsrc & RTsrc { + tmpS:16 = zext(RSsrc); + tmpT:16 = zext(RTsrc); + tmpS = tmpS * tmpT; + RD = tmpS[64,64]; +} + +:dlsa RD, RSsrc, RTsrc, SAV is $(AMODE) & REL6=1 & prime=0x00 & fct=0x15 & spec3=0 & SAV & RD & RSsrc & RTsrc { + RD = (RSsrc << SAV) + RTsrc; +} + +:ldpc RS, S18L3 is $(AMODE) & REL6=1 & prime=0x3B & pcrel2=0x6 & RS & S18L3 { + tmp:8 = inst_start + sext(S18L3); + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + RS = sext(*[ram]:8 tmpa); +} + +:lldx RT, OFF_BASER6 is $(AMODE) & REL6=1 & prime=0x1F & fct=0x37 & bit6=1 & OFF_BASER6 & RT { + RT = *[ram]:8 OFF_BASER6; +} + +:lwupc RS, S19L2 is $(AMODE) & REL6=1 & prime=0x3B & pcrel=0x2 & RS & S19L2 { + tmp:8 = inst_start + sext(S19L2); + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + RS = zext(*[ram]:4 tmpa); +} + +:sdcx RTsrc, OFF_BASER6 is $(AMODE) & REL6=1 & prime=0x1E & fct=0x27 & bit6=1 & OFF_BASER6 & RTsrc { + *[ram]:8 OFF_BASER6 = RTsrc; +} diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64R6.pspec b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64R6.pspec new file mode 100644 index 0000000..53695d3 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64R6.pspec @@ -0,0 +1,79 @@ + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64_32_n32.cspec b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64_32_n32.cspec new file mode 100644 index 0000000..255cb36 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64_32_n32.cspec @@ -0,0 +1,136 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64_32_o32.cspec b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64_32_o32.cspec new file mode 100644 index 0000000..1b01bf4 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64_32_o32.cspec @@ -0,0 +1,128 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64_32_o64.cspec b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64_32_o64.cspec new file mode 100644 index 0000000..bbb7a45 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64_32_o64.cspec @@ -0,0 +1,98 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64be.slaspec b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64be.slaspec new file mode 100644 index 0000000..5bf0368 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64be.slaspec @@ -0,0 +1,12 @@ +# SLA specification file for MIPS r5000 big endian + +@define ENDIAN "big" +@define MIPS64 "" +@define ISA_VARIANT "" + +@include "mips.sinc" +@include "mips32Instructions.sinc" +@include "mips16.sinc" +@include "mipsmicro.sinc" +@include "mips64Instructions.sinc" +@include "mips_dsp.sinc" diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64le.slaspec b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64le.slaspec new file mode 100644 index 0000000..abce05d --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64le.slaspec @@ -0,0 +1,13 @@ +# SLA specification file for MIPS r5000 little endian + +@define ENDIAN "little" +@define MIPS64 "" +@define ISA_VARIANT "" + +@include "mips.sinc" +@include "mips32Instructions.sinc" +@include "mips16.sinc" +@include "mipsmicro.sinc" +@include "mips64Instructions.sinc" +@include "mips_dsp.sinc" + diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64micro.pspec b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64micro.pspec new file mode 100644 index 0000000..7819d36 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips64micro.pspec @@ -0,0 +1,77 @@ + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips_dsp.sinc b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips_dsp.sinc new file mode 100644 index 0000000..e4c1835 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips_dsp.sinc @@ -0,0 +1,1242 @@ + +define pcodeop ABSQ_S.PH; +define pcodeop ABSQ_S.QB; +define pcodeop ABSQ_S.W; +define pcodeop ADDQ.PH; +define pcodeop ADDQ_S.W; +define pcodeop ADDQH.PH; +define pcodeop ADDQH.W; +define pcodeop ADDSC; +define pcodeop ADDU.PH; +define pcodeop ADDU.QB; +define pcodeop ADDWC; +define pcodeop ADDUH.QB; +define pcodeop BITREV; +define pcodeop DPA.W.PH; +define pcodeop DPAQ_S.W.PH; +define pcodeop DPAQ_SA.L.W; +define pcodeop DPAQX_S.W.PH; +define pcodeop DPAQX_SA.W.PH; +define pcodeop DPAU.H.QBL; +define pcodeop DPAU.H.QBR; +define pcodeop DPAX.W.PH; +define pcodeop DPS.W.PH; +define pcodeop DPSQ_S.W.PH; +define pcodeop DPSQ_SA.L.W; +define pcodeop DPSQX_S.W.PH; +define pcodeop DPSQX_SA.W.PH; +define pcodeop DPSU.H.QBL; +define pcodeop DPSU.H.QBR; +define pcodeop DPSX.W.PH; +define pcodeop EXTP; +define pcodeop EXTPDP; +define pcodeop EXTPDPV; +define pcodeop EXTPV; +define pcodeop EXTR.W; +define pcodeop EXTR_S.H; +define pcodeop EXTRV.W; +define pcodeop EXTRV_S.H; +define pcodeop INSV; +define pcodeop MAQ_S.W.PHL; +define pcodeop MAQ_S.W.PHR; +define pcodeop MUL.PH; +define pcodeop MULEQ_S.W.PHL; +define pcodeop MULEQ_S.W.PHR; +define pcodeop MULEU_S.PH.QBL; +define pcodeop MULEU_S.PH.QBR; +define pcodeop MULQ_RS.PH; +define pcodeop MULQ_RS.W; +define pcodeop MULQ_S.PH; +define pcodeop MULQ_S.W; +define pcodeop MULSA.W.PH; +define pcodeop MULSAQ_S.W.PH; +define pcodeop PRECEQ.W.PHL; +define pcodeop PRECEQ.W.PHR; +define pcodeop PRECEQU.PH.QBL; +define pcodeop PRECEQU.PH.QBLA; +define pcodeop PRECEQU.PH.QBR; +define pcodeop PRECEQU.PH.QBRA; +define pcodeop PRECEU.PH.QBL; +define pcodeop PRECEU.PH.QBLA; +define pcodeop PRECEU.PH.QBR; +define pcodeop PRECEU.PH.QBRA; +define pcodeop PRECR.QB.PH; +define pcodeop PRECR_SRA.PH.W; +define pcodeop PRECRQ.PH.W; +define pcodeop PRECRQ.QB.PH; +define pcodeop PRECRQU_S.QB.PH; +define pcodeop PRECRQ_RS.PH.W; +define pcodeop RADDU.W.QB; +define pcodeop REPLV.PH; +define pcodeop REPLV.QB; +define pcodeop SHLL.PH; +define pcodeop SHLL.QB; +define pcodeop SHLLV.PH; +define pcodeop SHLLV.QB; +define pcodeop SHLLV_S.W; +define pcodeop SHLL_S.W; +define pcodeop SHRA.QB; +define pcodeop SHRA.PH; +define pcodeop SHRAV.PH; +define pcodeop SHRAV.QB; +define pcodeop SHRAV_R.W; +define pcodeop SHRA_R.W; +define pcodeop SHRL.PH; +define pcodeop SHRL.QB; +define pcodeop SHRLV.PH; +define pcodeop SHRLV.QB; +define pcodeop SUBQ.PH; +define pcodeop SUBQ_S.W; +define pcodeop SUBQH.PH; +define pcodeop SUBQH.W; +define pcodeop SUBU.PH; +define pcodeop SUBU.QB; +define pcodeop SUBUH.QB; + + +# ABSQ_S.PH Purpose: Find Absolute Value of Two Fractional Halfwords +:absq_s.ph RD, RTsrc is $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x9 & fct=0x12 { + RD = ABSQ_S.PH(RTsrc); +} + + +# ABSQ_S.QB Purpose: Find Absolute Value of Four Fractional Byte Values +:absq_s.qb RD, RTsrc is $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x1 & fct=0x12 { + RD = ABSQ_S.QB(RTsrc); +} + + +# ABSQ_S.W Purpose: Find Absolute Value of Fractional Word +:absq_s.w RD, RTsrc is $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x11 & fct=0x12 { + RD = ABSQ_S.W(RTsrc); +} + + +# ADDQ[_S].PH Purpose: Add Fractional Halfword Vectors +:addq.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xa & fct=0x10 { + RD = ADDQ.PH(RSsrc, RTsrc); +} + +:addq_s.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xe & fct=0x10 { + RD = ADDQ.PH(RSsrc, RTsrc); +} + + +# ADDQ_S.W Purpose: Add Fractional Words +:addq_s.w RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x16 & fct=0x10 { + RD = ADDQ_S.W(RSsrc, RTsrc); +} + + +# ADDQH[_R].PH Purpose: Add Fractional Halfword Vectors And Shift Right to Halve Results +:addqh.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x8 & fct=0x18 { + RD = ADDQH.PH(RSsrc, RTsrc); +} + +:addqh_r.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xa & fct=0x18 { + RD = ADDQH.PH(RSsrc, RTsrc); +} + + +# ADDQH[_R].W Purpose: Add Fractional Words And Shift Right to Halve Results +:addqh.w RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x10 & fct=0x18 { + RD = ADDQH.W(RSsrc, RTsrc); +} + +:addqh_r.w RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x12 & fct=0x18 { + RD = ADDQH.W(RSsrc, RTsrc); +} + + +# ADDSC Purpose: Add Signed Word and Set Carry Bit +:addsc RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x10 & fct=0x10 { + RD = ADDSC(RSsrc, RTsrc); +} + + +# ADDU[_S].PH Purpose: Unsigned Add Integer Halfwords +:addu.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x8 & fct=0x10 { + RD = ADDU.PH(RSsrc, RTsrc); +} + +:addu_s.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xc & fct=0x10 { + RD = ADDU.PH(RSsrc, RTsrc); +} + + +# ADDU[_S].QB Purpose: Unsigned Add Quad Byte Vectors +:addu.qb RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x0 & fct=0x10 { + RD = ADDU.QB(RSsrc, RTsrc); +} + +:addu_s.qb RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x4 & fct=0x10 { + RD = ADDU.QB(RSsrc, RTsrc); +} + + +# ADDWC Purpose: Add Word with Carry Bit +:addwc RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x11 & fct=0x10 { + RD = ADDWC(RSsrc, RTsrc); +} + + +# ADDUH[_R].QB Purpose: Unsigned Add Vector Quad-Bytes And Right Shift to Halve Results +:adduh.qb RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x0 & fct=0x18 { + RD = ADDUH.QB(RSsrc, RTsrc); +} + +:adduh_r.qb RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x2 & fct=0x18 { + RD = ADDUH.QB(RSsrc, RTsrc); +} + + +# APPEND Purpose: Left Shift and Append Bits to the LSB +:append RTsrc, RSsrc, sa_dsp is $(AMODE) & prime=0x1f & RSsrc & RTsrc & sa_dsp & fct2=0x0 & fct=0x31 { + RSval:$(REGSIZE) = RSsrc & (2^sa_dsp-1); + RTsrc = (RTsrc << sa_dsp) | (RSval); +} + + +# BALIGN Purpose: Byte Align Contents from Two Registers +:balign RTsrc, RSsrc, bp is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & bp & fct2=0x10 & fct=0x31 { + RTsrc = (RTsrc << 8*bp) | (RSsrc >> 8*(4-bp)); +} + + +# BITREV Purpose: Bit-Reverse Halfword +:bitrev RD, RTsrc is $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x1b & fct=0x12 { + RD = BITREV(RTsrc); +} + + +# BPOSGE32 Purpose: Branch on Greater Than or Equal To Value 32 in DSPControl Pos Field +:bposge32 Rel16 is $(AMODE) & prime=0x1 & zero21=0x0 & op=0x1c & Rel16 { + dsp_pos:$(REGSIZE) = DSPControl & 0x1f; + if (dsp_pos < 32) goto inst_next; + delayslot(1); + goto Rel16; +} + +# BPOSGE32C Purpose: Branch on Greater Than or Equal To Value 32 in DSPControl Pos Field Compact +# no branch delay +:bposge32c Rel16 is $(AMODE) & prime=0x1 & zero21=0x0 & op=0x1a & Rel16 { + dsp_pos:$(REGSIZE) = DSPControl & 0x1f; + if (dsp_pos < 32) goto inst_next; + goto Rel16; +} + +# CMP.cond.PH Purpose: Compare Vectors of Signed Integer Halfword Values +:cmp.eq.ph RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero4=0x0 & fct2=0x8 & fct=0x11 { + tmp_rs:2 = RSsrc(0) & 0xffff; + tmp_rt:2 = RTsrc(0) & 0xffff; + cca:1 = (tmp_rs == tmp_rt); + tmp_rs = RSsrc(2) & 0xffff; + tmp_rt = RTsrc(2) & 0xffff; + ccb:1 = (tmp_rs == tmp_rt); + flags:$(REGSIZE) = 0xfcffffff; + DSPControl = (DSPControl & flags) | zext(cca << 24) | zext(ccb << 25); +} + +:cmp.lt.ph RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero4=0x0 & fct2=0x9 & fct=0x11 { + tmp_rs:2 = RSsrc(0) & 0xffff; + tmp_rt:2 = RTsrc(0) & 0xffff; + cca:1 = (tmp_rs s< tmp_rt); + tmp_rs = RSsrc(2) & 0xffff; + tmp_rt = RTsrc(2) & 0xffff; + ccb:1 = (tmp_rs s< tmp_rt); + flags:$(REGSIZE) = 0xfcffffff; + DSPControl = (DSPControl & flags) | zext(cca << 24) | zext(ccb << 25); +} + +:cmp.le.ph RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero4=0x0 & fct2=0xa & fct=0x11 { + tmp_rs:2 = RSsrc(0) & 0xffff; + tmp_rt:2 = RTsrc(0) & 0xffff; + cca:1 = (tmp_rs s<= tmp_rt); + tmp_rs = RSsrc(2) & 0xffff; + tmp_rt = RTsrc(2) & 0xffff; + ccb:1 = (tmp_rs s<= tmp_rt); + flags:$(REGSIZE) = 0xfcffffff; + DSPControl = (DSPControl & flags) | zext(cca << 24) | zext(ccb << 25); +} + + +# CMPGDU.cond.QB Purpose: Compare Unsigned Vector of Four Bytes and Write Result to GPR and DSPControl +:cmpgdu.eq.qb RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x18 & fct=0x11 { + tmp_rs:1 = RSsrc(0) & 0xff; + tmp_rt:1 = RTsrc(0) & 0xff; + cca:$(REGSIZE) = zext(tmp_rs == tmp_rt); + tmp_rs = RSsrc(1) & 0xff; + tmp_rt = RTsrc(1) & 0xff; + ccb:$(REGSIZE) = zext(tmp_rs == tmp_rt); + tmp_rs = RSsrc(2) & 0xff; + tmp_rt = RTsrc(2) & 0xff; + ccc:$(REGSIZE) = zext(tmp_rs == tmp_rt); + tmp_rs = RSsrc(3) & 0xff; + tmp_rt = RTsrc(3) & 0xff; + ccd:$(REGSIZE) = zext(tmp_rs == tmp_rt); + flags:$(REGSIZE) = 0xf0ffffff; + DSPControl = (DSPControl & flags) | (ccd << 27) | (ccc << 26) | (ccb << 25) | (cca << 24); + RD = (ccd << 3) | (ccc << 2) | (ccb << 1) | (cca); +} + +:cmpgdu.lt.qb RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x19 & fct=0x11 { + tmp_rs:1 = RSsrc(0) & 0xff; + tmp_rt:1 = RTsrc(0) & 0xff; + cca:$(REGSIZE) = zext(tmp_rs < tmp_rt); + tmp_rs = RSsrc(1) & 0xff; + tmp_rt = RTsrc(1) & 0xff; + ccb:$(REGSIZE) = zext(tmp_rs < tmp_rt); + tmp_rs = RSsrc(2) & 0xff; + tmp_rt = RTsrc(2) & 0xff; + ccc:$(REGSIZE) = zext(tmp_rs < tmp_rt); + tmp_rs = RSsrc(3) & 0xff; + tmp_rt = RTsrc(3) & 0xff; + ccd:$(REGSIZE) = zext(tmp_rs < tmp_rt); + flags:$(REGSIZE) = 0xf0ffffff; + DSPControl = (DSPControl & flags) | (cca << 24) | (ccb << 25) | (ccc << 26) | (ccd << 27); + RD = (cca) | (ccb << 1) | (ccc << 2) | (ccd << 3); +} + +:cmpgdu.le.qb RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x1a & fct=0x11 { + tmp_rs:1 = RSsrc(0) & 0xff; + tmp_rt:1 = RTsrc(0) & 0xff; + cca:$(REGSIZE) = zext(tmp_rs <= tmp_rt); + tmp_rs = RSsrc(1) & 0xff; + tmp_rt = RTsrc(1) & 0xff; + ccb:$(REGSIZE) = zext(tmp_rs <= tmp_rt); + tmp_rs = RSsrc(2) & 0xff; + tmp_rt = RTsrc(2) & 0xff; + ccc:$(REGSIZE) = zext(tmp_rs <= tmp_rt); + tmp_rs = RSsrc(3) & 0xff; + tmp_rt = RTsrc(3) & 0xff; + ccd:$(REGSIZE) = zext(tmp_rs <= tmp_rt); + flags:$(REGSIZE) = 0xf0ffffff; + DSPControl = (DSPControl & flags) | (cca << 24) | (ccb << 25) | (ccc << 26) | (ccd << 27); + RD = (cca) | (ccb << 1) | (ccc << 2) | (ccd << 3); +} + + +# CMPGU.cond.QB Purpose: Compare Vectors of Unsigned Byte Values and Write Results to a GPR +:cmpgu.eq.qb RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x4 & fct=0x11 { + tmp_rs:1 = RSsrc(0) & 0xff; + tmp_rt:1 = RTsrc(0) & 0xff; + cca:1 = (tmp_rs == tmp_rt); + tmp_rs = RSsrc(1) & 0xff; + tmp_rt = RTsrc(1) & 0xff; + ccb:1 = (tmp_rs == tmp_rt); + tmp_rs = RSsrc(2) & 0xff; + tmp_rt = RTsrc(2) & 0xff; + ccc:1 = (tmp_rs == tmp_rt); + tmp_rs = RSsrc(3) & 0xff; + tmp_rt = RTsrc(3) & 0xff; + ccd:1 = (tmp_rs == tmp_rt); + RD = zext(cca) | zext(ccb << 1) | zext(ccc << 2) | zext(ccd << 3); +} + +:cmpgu.lt.qb RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x5 & fct=0x11 { + tmp_rs:1 = RSsrc(0) & 0xff; + tmp_rt:1 = RTsrc(0) & 0xff; + cca:1 = (tmp_rs < tmp_rt); + tmp_rs = RSsrc(1) & 0xff; + tmp_rt = RTsrc(1) & 0xff; + ccb:1 = (tmp_rs < tmp_rt); + tmp_rs = RSsrc(2) & 0xff; + tmp_rt = RTsrc(2) & 0xff; + ccc:1 = (tmp_rs < tmp_rt); + tmp_rs = RSsrc(3) & 0xff; + tmp_rt = RTsrc(3) & 0xff; + ccd:1 = (tmp_rs < tmp_rt); + RD = zext(cca) | zext(ccb << 1) | zext(ccc << 2) | zext(ccd << 3); +} + +:cmpgu.le.qb RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x6 & fct=0x11 { + tmp_rs:1 = RSsrc(0) & 0xff; + tmp_rt:1 = RTsrc(0) & 0xff; + cca:1 = (tmp_rs <= tmp_rt); + tmp_rs = RSsrc(1) & 0xff; + tmp_rt = RTsrc(1) & 0xff; + ccb:1 = (tmp_rs <= tmp_rt); + tmp_rs = RSsrc(2) & 0xff; + tmp_rt = RTsrc(2) & 0xff; + ccc:1 = (tmp_rs <= tmp_rt); + tmp_rs = RSsrc(3) & 0xff; + tmp_rt = RTsrc(3) & 0xff; + ccd:1 = (tmp_rs <= tmp_rt); + RD = zext(cca) | zext(ccb << 1) | zext(ccc << 2) | zext(ccd << 3); +} + + +# CMPU.cond.QB Purpose: Compare Vectors of Unsigned Byte Values +:cmpu.eq.qb RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero4=0x0 & fct2=0x0 & fct=0x11 { + tmp_rs:1 = RSsrc(0) & 0xff; + tmp_rt:1 = RTsrc(0) & 0xff; + cca:1 = (tmp_rs == tmp_rt); + tmp_rs = RSsrc(1) & 0xff; + tmp_rt = RTsrc(1) & 0xff; + ccb:1 = (tmp_rs == tmp_rt); + tmp_rs = RSsrc(2) & 0xff; + tmp_rt = RTsrc(2) & 0xff; + ccc:1 = (tmp_rs == tmp_rt); + tmp_rs = RSsrc(3) & 0xff; + tmp_rt = RTsrc(3) & 0xff; + ccd:1 = (tmp_rs == tmp_rt); + flags:$(REGSIZE) = 0xf0ffffff; + DSPControl = (DSPControl & flags) | zext(cca << 24) | zext(ccb << 25) | zext(ccc << 26) | zext(ccd << 27); +} + +:cmpu.lt.qb RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero4=0x0 & fct2=0x1 & fct=0x11 { + tmp_rs:1 = RSsrc(0) & 0xff; + tmp_rt:1 = RTsrc(0) & 0xff; + cca:1 = (tmp_rs < tmp_rt); + tmp_rs = RSsrc(1) & 0xff; + tmp_rt = RTsrc(1) & 0xff; + ccb:1 = (tmp_rs < tmp_rt); + tmp_rs = RSsrc(2) & 0xff; + tmp_rt = RTsrc(2) & 0xff; + ccc:1 = (tmp_rs < tmp_rt); + tmp_rs = RSsrc(3) & 0xff; + tmp_rt = RTsrc(3) & 0xff; + ccd:1 = (tmp_rs < tmp_rt); + flags:$(REGSIZE) = 0xf0ffffff; + DSPControl = (DSPControl & flags) | zext(cca << 24) | zext(ccb << 25) | zext(ccc << 26) | zext(ccd << 27); +} + +:cmpu.le.qb RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero4=0x0 & fct2=0x2 & fct=0x11 { + tmp_rs:1 = RSsrc(0) & 0xff; + tmp_rt:1 = RTsrc(0) & 0xff; + cca:1 = (tmp_rs <= tmp_rt); + tmp_rs = RSsrc(1) & 0xff; + tmp_rt = RTsrc(1) & 0xff; + ccb:1 = (tmp_rs <= tmp_rt); + tmp_rs = RSsrc(2) & 0xff; + tmp_rt = RTsrc(2) & 0xff; + ccc:1 = (tmp_rs <= tmp_rt); + tmp_rs = RSsrc(3) & 0xff; + tmp_rt = RTsrc(3) & 0xff; + ccd:1 = (tmp_rs <= tmp_rt); + flags:$(REGSIZE) = 0xf0ffffff; + DSPControl = (DSPControl & flags) | zext(cca << 24) | zext(ccb << 25) | zext(ccc << 26) | zext(ccd << 27); +} + + +# DPA.W.PH Purpose: Dot Product with Accumulate on Vector Integer Halfword Elements +:dpa.w.ph ac, RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x0 & fct=0x30 { + ac = DPA.W.PH(ac, RSsrc, RTsrc); +} + + +# DPAQ_S.W.PH Purpose: Dot Product with Accumulation on Fractional Halfword Elements +:dpaq_s.w.ph ac, RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x4 & fct=0x30 { + ac = DPAQ_S.W.PH(ac, RSsrc, RTsrc); +} + + +# DPAQ_SA.L.W Purpose: Dot Product with Accumulate on Fractional Word Element +:dpaq_sa.l.w ac, RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0xc & fct=0x30 { + ac = DPAQ_SA.L.W(ac, RSsrc, RTsrc); +} + + +# DPAQX_S.W.PH Purpose: Cross Dot Product with Accumulation on Fractional Halfword Elements +:dpaqx_s.w.ph ac, RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x18 & fct=0x30 { + ac = DPAQX_S.W.PH(ac, RSsrc, RTsrc); +} + + +# DPAQX_SA.W.PH Purpose: Cross Dot Product with Accumulation on Fractional Halfword Elements +:dpaqx_sa.w.ph ac, RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x1a & fct=0x30 { + ac = DPAQX_SA.W.PH(ac, RSsrc, RTsrc); +} + + +# DPAU.H.QBL Purpose: Dot Product with Accumulate on Vector Unsigned Byte Elements +:dpau.h.qbl ac, RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x3 & fct=0x30 { + ac = DPAU.H.QBL(ac, RSsrc, RTsrc); +} + + +# DPAU.H.QBR Purpose: Dot Product with Accumulate on Vector Unsigned Byte Elements +:dpau.h.qbr ac, RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x7 & fct=0x30 { + ac = DPAU.H.QBR(ac, RSsrc, RTsrc); +} + + +# DPAX.W.PH Purpose: Cross Dot Product with Accumulate on Vector Integer Halfword Elements +:dpax.w.ph ac, RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x8 & fct=0x30 { + ac = DPAX.W.PH(ac, RSsrc, RTsrc); +} + + +# DPS.W.PH Purpose: Dot Product with Subtract on Vector Integer Half-Word Elements +:dps.w.ph ac, RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x1 & fct=0x30 { + ac = DPS.W.PH(ac, RSsrc, RTsrc); +} + + +# DPSQ_S.W.PH Purpose: Dot Product with Subtraction on Fractional Halfword Elements +:dpsq_s.w.ph ac, RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x5 & fct=0x30 { + ac = DPSQ_S.W.PH(ac, RSsrc, RTsrc); +} + + +# DPSQ_SA.L.W Purpose: Dot Product with Subtraction on Fractional Word Element +:dpsq_sa.l.w ac, RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0xd & fct=0x30 { + ac = DPSQ_SA.L.W(ac, RSsrc, RTsrc); +} + + +# DPSQX_S.W.PH Purpose: Cross Dot Product with Subtraction on Fractional Halfword Elements +:dpsqx_s.w.ph ac, RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x19 & fct=0x30 { + ac = DPSQX_S.W.PH(ac, RSsrc, RTsrc); +} + + +# DPSQX_SA.W.PH Purpose: Cross Dot Product with Subtraction on Fractional Halfword Elements +:dpsqx_sa.w.ph ac, RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x1b & fct=0x30 { + ac = DPSQX_SA.W.PH(ac, RSsrc, RTsrc); +} + + +# DPSU.H.QBL Purpose: Dot Product with Subtraction on Vector Unsigned Byte Elements +:dpsu.h.qbl ac, RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0xb & fct=0x30 { + ac = DPSU.H.QBL(ac, RSsrc, RTsrc); +} + + +# DPSU.H.QBR Purpose: Dot Product with Subtraction on Vector Unsigned Byte Elements +:dpsu.h.qbr ac, RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0xf & fct=0x30 { + ac = DPSU.H.QBR(ac, RSsrc, RTsrc); +} + + +# DPSX.W.PH Purpose: Cross Dot Product with Subtract on Vector Integer Halfword Elements +:dpsx.w.ph ac, RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x9 & fct=0x30 { + ac = DPSX.W.PH(ac, RSsrc, RTsrc); +} + + +# EXTP Purpose: Extract Fixed Bitfield From Arbitrary Position in Accumulator to GPR +:extp RT, ac, sz is $(AMODE) & prime=0x1f & sz & RT & zero1315=0x0 & ac & fct2=0x2 & fct=0x38 { + RT = EXTP(ac, sz:1); +} + + +# EXTPDP Purpose: Extract Fixed Bitfield From Arbitrary Position in Accumulator to GPR and Decrement Pos +:extpdp RT, ac, sz is $(AMODE) & prime=0x1f & sz & RT & zero1315=0x0 & ac & fct2=0xa & fct=0x38 { + RT = EXTPDP(ac, sz:1); +} + + +# EXTPDPV Purpose: Extract Variable Bitfield From Arbitrary Position in Accumulator to GPR and Decrement Pos +:extpdpv RT, ac, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RT & zero1315=0x0 & ac & fct2=0xb & fct=0x38 { + RT = EXTPDPV(ac, RSsrc); +} + + +# EXTPV Purpose: Extract Variable Bitfield From Arbitrary Position in Accumulator to GPR +:extpv RT, ac, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RT & zero1315=0x0 & ac & fct2=0x3 & fct=0x38 { + RT = EXTPV(ac, RSsrc); +} + + +# EXTR[_RS].W Purpose: Extract Word Value With Right Shift From Accumulator to GPR +:extr.w RT, ac, shift21 is $(AMODE) & prime=0x1f & shift21 & RT & zero1315=0x0 & ac & fct2=0x0 & fct=0x38 { + val:$(DREGSIZE) = ac >> shift21:1; + result:4 = val(0); + RT = zext(result); +} + +:extr_r.w RT, ac, shift21 is $(AMODE) & prime=0x1f & shift21 & RT & zero1315=0x0 & ac & fct2=0x4 & fct=0x38 { + val:$(DREGSIZE) = ac >> shift21:1; + result:4 = val(0); + RT = EXTR.W(result, 1:1); +} + +:extr_rs.w RT, ac, shift21 is $(AMODE) & prime=0x1f & shift21 & RT & zero1315=0x0 & ac & fct2=0x6 & fct=0x38 { + val:$(DREGSIZE) = ac >> shift21:1; + result:4 = val(0); + RT = EXTR.W(result, 2:1); +} + + +# EXTR_S.H Purpose: Extract Halfword Value From Accumulator to GPR With Right Shift and Saturate +:extr_s.h RT, ac, shift21 is $(AMODE) & prime=0x1f & shift21 & RT & zero1315=0x0 & ac & fct2=0xe & fct=0x38 { + val:$(DREGSIZE) = ac >> shift21:1; + result:2 = val(0); + RT = EXTR_S.H(result); +} + + +# EXTRV[_RS].W Purpose: Extract Word Value With Variable Right Shift From Accumulator to GPR +:extrv.w RT, ac, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RT & zero1315=0x0 & ac & fct2=0x1 & fct=0x38 { + shift:1 = RSsrc(0) & 0x3f; + val:$(DREGSIZE) = ac >> shift; + result:4 = val(0); + RT = EXTRV.W(result, 0:1); +} + +:extrv_r.w RT, ac, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RT & zero1315=0x0 & ac & fct2=0x5 & fct=0x38 { + shift:1 = RSsrc(0) & 0x3f; + val:$(DREGSIZE) = ac >> shift; + result:4 = val(0); + RT = EXTRV.W(result, 1:1); +} + +:extrv_rs.w RT, ac, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RT & zero1315=0x0 & ac & fct2=0x7 & fct=0x38 { + shift:1 = RSsrc(0) & 0x3f; + val:$(DREGSIZE) = ac >> shift; + result:4 = val(0); + RT = EXTRV.W(result, 2:1); +} + + +# EXTRV_S.H Purpose: Extract Halfword Value Variable From Accumulator to GPR With Right Shift and Saturate +:extrv_s.h RT, ac, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RT & zero1315=0x0 & ac & fct2=0xf & fct=0x38 { + shift:1 = RSsrc(0) & 0x3f; + val:$(DREGSIZE) = ac >> shift; + result:2 = val(0); + RT = EXTR_S.H(result); +} + + +# INSV Purpose: Insert Bit Field Variable +:insv RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero4=0x0 & fct2=0x0 & fct=0xc { + RTsrc = INSV(RTsrc, RSsrc); +} + + +# LBUX Purpose: Load Unsigned Byte Indexed +:lbux RD, INDEX_BASE is $(AMODE) & prime=0x1f & INDEX_BASE & RD & fct2=0x6 & fct=0xa { + RD = zext(*[ram]:1 INDEX_BASE); +} + +@ifdef MIPS64 +# LDX Load Doubleword Indexed +:ldx RD, INDEX_BASE is $(AMODE) & prime=0x1F & RD & fct=10 & fct2=8 & INDEX_BASE { + RD = *[ram]:8 INDEX_BASE; +} +@endif + +# LHX Purpose: Load Halfword Indexed +:lhx RD, INDEX_BASE is $(AMODE) & prime=0x1f & INDEX_BASE & RD & fct2=0x4 & fct=0xa { + RD = sext(*[ram]:2 INDEX_BASE); +} + + +# LWX Purpose: Load Word Indexed +:lwx RD, INDEX_BASE is $(AMODE) & prime=0x1f & INDEX_BASE & RD & fct2=0x0 & fct=0xa { +@ifdef MIPS64 + RD = sext(*[ram]:4 INDEX_BASE); +@else + RD = *[ram]:4 INDEX_BASE; +@endif +} + +# MADD Purpose: Multiply Word and Add to Accumulator +:madd ac, RS32src, RT32src is $(AMODE) & prime=0x1c & RS32src & RT32src & zero1315=0x0 & ac & fct2=0x0 & fct=0x0 { + tmp1:$(DREGSIZE) = zext(RS32src); + tmp2:$(DREGSIZE) = zext(RT32src); + prod:$(DREGSIZE) = tmp1 * tmp2; + ac = ac + prod; +} + + +# MADDU Purpose: Multiply Unsigned Word and Add to Accumulator +:maddu ac, RS32src, RT32src is $(AMODE) & prime=0x1c & RS32src & RT32src & zero1315=0x0 & ac & fct2=0x0 & fct=0x1 { + tmp1:$(DREGSIZE) = zext(RS32src); + tmp2:$(DREGSIZE) = zext(RT32src); + prod:$(DREGSIZE) = tmp1 * tmp2; + ac = ac + prod; + +} + + +# MAQ_S[A].W.PHL Purpose: Multiply with Accumulate Single Vector Fractional Halfword Element +:maq_s.w.phl ac, RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x14 & fct=0x30 { + ac = MAQ_S.W.PHL(RSsrc, RTsrc); +} + +:maq_sa.w.phl ac, RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x10 & fct=0x30 { + ac = MAQ_S.W.PHL(RSsrc, RTsrc); +} + + +# MAQ_S[A].W.PHR Purpose: Multiply with Accumulate Single Vector Fractional Halfword Element +:maq_s.w.phr ac, RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x16 & fct=0x30 { + ac = MAQ_S.W.PHR(RSsrc, RTsrc); +} + +:maq_sa.w.phr ac, RSsrc, RTsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x12 & fct=0x30 { + ac = MAQ_S.W.PHR(RSsrc, RTsrc); +} + + +# MFHI Purpose: Move from HI register +:mfhi RD, acfhi is $(AMODE) & prime=0x0 & zero2325=0x0 & acfhi & zero1620=0x0 & RD & fct2=0x0 & fct=0x10 { + RD = acfhi; +} + + +# MFLO Purpose: Move from LO register +:mflo RD, acflo is $(AMODE) & prime=0x0 & zero2325=0x0 & acflo & zero1620=0x0 & RD & fct2=0x0 & fct=0x12 { + RD = acflo; +} + + +# MODSUB Purpose: Modular Subtraction on an Index Value +:modsub RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x12 & fct=0x10 { + decr:1 = RTsrc(0); + lastIdx:2 = RTsrc(1); + equals:1 = (RSsrc == 0); + RD = (zext(equals) * zext(lastIdx)) + (zext(!equals) * (RSsrc - zext(decr))); +} + + +# MSUB Purpose: Multiply Word and Subtract from Accumulator +:msub ac, RS32src, RT32src is $(AMODE) & prime=0x1c & RS32src & RT32src & zero1315=0x0 & ac & aclo & achi & fct2=0x0 & fct=0x4 { + tmp1:$(DREGSIZE) = sext(RS32src); + tmp2:$(DREGSIZE) = sext(RT32src); + prod:$(DREGSIZE) = tmp1 * tmp2; + ac = ac - prod; +} + + +# MSUBU Purpose: Multiply Unsigned Word and Add to Accumulator + +:msubu ac, RS32src, RT32src is $(AMODE) & prime=0x1c & RS32src & RT32src & zero1315=0x0 & ac & fct2=0x0 & fct=0x5 { + tmp1:$(DREGSIZE) = zext(RS32src); + tmp2:$(DREGSIZE) = zext(RT32src); + prod:$(DREGSIZE) = tmp1 * tmp2; + ac = ac - prod; +} + + +# MTHI Purpose: Move to HI register +:mthi RS, achi is $(AMODE) & prime=0x0 & RS & zero1320=0x0 & achi & fct2=0x0 & fct=0x11 { + RS = achi; +} + + +# MTHLIP Purpose: Copy LO to HI and a GPR to LO and Increment Pos by 32 +:mthlip RS, ac is $(AMODE) & prime=0x1f & RS & zero1320=0x0 & ac & aclo & achi & fct2=0x1f & fct=0x38 { + achi = aclo; + aclo = RS; + # increment DSPControl pos field by 32 +} + + +# MTLO Purpose: Move to LO register +:mtlo RS, aclo is $(AMODE) & prime=0x0 & RS & zero1320=0x0 & aclo & fct2=0x0 & fct=0x13 { + RS=aclo; +} + + +# MUL[_S].PH Purpose: Multiply Vector Integer HalfWords to Same Size Products +:mul.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xc & fct=0x18 { + RD = MUL.PH(RSsrc, RTsrc); +} + +:mul_s.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xe & fct=0x18 { + RD = MUL.PH(RSsrc, RTsrc); +} + + +# MULEQ_S.W.PHL Purpose: Multiply Vector Fractional Left Halfwords to Expanded Width Products +:muleq_s.w.phl RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x1c & fct=0x10 { + RD = MULEQ_S.W.PHL(RSsrc, RTsrc); +} + + +# MULEQ_S.W.PHR Purpose: Multiply Vector Fractional Right Halfwords to Expanded Width Products +:muleq_s.w.phr RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x1d & fct=0x10 { + RD = MULEQ_S.W.PHR(RSsrc, RTsrc); +} + + +# MULEU_S.PH.QBL Purpose: Multiply Unsigned Vector Left Bytes by Halfwords to Halfword Products +:muleu_s.ph.qbl RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x6 & fct=0x10 { + RD = MULEU_S.PH.QBL(RSsrc, RTsrc); +} + + +# MULEU_S.PH.QBR Purpose: Multiply Unsigned Vector Right Bytes with halfwords to Half Word Products +:muleu_s.ph.qbr RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x7 & fct=0x10 { + RD = MULEU_S.PH.QBR(RSsrc, RTsrc); +} + + +# MULQ_RS.PH Purpose: Multiply Vector Fractional Halfwords to Fractional Halfword Products +:mulq_rs.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x1f & fct=0x10 { + RD = MULQ_RS.PH(RSsrc, RTsrc); +} + + +# MULQ_RS.W Purpose: Multiply Fractional Words to Same Size Product with Saturation and Rounding +:mulq_rs.w RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x17 & fct=0x18 { + RD = MULQ_RS.W(RSsrc, RTsrc); +} + + +# MULQ_S.PH Purpose: Multiply Vector Fractional Half-Words to Same Size Products +:mulq_s.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x1e & fct=0x10 { + RD = MULQ_S.PH(RSsrc, RTsrc); +} + + +# MULQ_S.W Purpose: Multiply Fractional Words to Same Size Product with Saturation +:mulq_s.w RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x16 & fct=0x18 { + RD = MULQ_S.W(RSsrc, RTsrc); +} + + +# MULSA.W.PH Purpose: Multiply and Subtract Vector Integer Halfword Elements and Accumulate +:mulsa.w.ph ac, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x2 & fct=0x30 { + ac = MULSA.W.PH(RSsrc, RTsrc); +} + + +# MULSAQ_S.W.PH Purpose: Multiply And Subtract Vector Fractional Halfwords And Accumulate +:mulsaq_s.w.ph ac, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & zero1315=0x0 & ac & fct2=0x6 & fct=0x30 { + ac = MULSAQ_S.W.PH(RSsrc, RTsrc); +} + + +# MULT Purpose: Multiply Word +:mult ac, RS32src, RT32src is $(AMODE) & prime=0x0 & RS32src & RT32src & zero1315=0x0 & ac & fct2=0x0 & fct=0x18 { + tmp1:$(DREGSIZE) = sext( RS32src ); + tmp2:$(DREGSIZE) = sext( RT32src ); + ac = tmp1 * tmp2; +} + + +# MULTU Purpose: Multiply Unsigned Word +:multu ac, RS32src, RT32src is $(AMODE) & prime=0x0 & RS32src & RT32src & zero1315=0x0 & ac & fct2=0x0 & fct=0x19 { + tmp1:$(DREGSIZE) = zext( RS32src ); + tmp2:$(DREGSIZE) = zext( RT32src ); + ac = tmp1 * tmp2; +} + + +# PACKRL.PH Purpose: Pack a Vector of Halfwords from Vector Halfword Sources +:packrl.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xe & fct=0x11 { + src1:2 = RSsrc(0); + src2:2 = RTsrc(2); + RD = zext(src1 << 16) + zext(src2); +} + + +# PICK.PH Purpose: Pick a Vector of Halfword Values Based on Condition Code Bits +:pick.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xb & fct=0x11 { + cc24:1 = DSPControl[24,1]; + cc25:1 = DSPControl[25,1]; + + val1:2 = RSsrc(0); + val2:2 = RTsrc(0); + tmp1:2 = (zext(cc24 == 1) * val1) + ((zext(cc24==0)) * val2); + + val1 = RSsrc(2); + val2 = RTsrc(2); + tmp2:2 = (zext(cc25 == 1) * val1) + ((zext(cc25==0)) * val2); + + RD = zext(tmp1) + zext(tmp2 << 16); +} + + +# PICK.QB Purpose: Pick a Vector of Byte Values Based on Condition Code Bits +:pick.qb RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x3 & fct=0x11 { + local cc1:1 = DSPControl[24,1]; + local cc2:1 = DSPControl[25,1]; + local cc3:1 = DSPControl[26,1]; + local cc4:1 = DSPControl[27,1]; + + local val1:1 = RSsrc(0); + local val2:1 = RTsrc(0); + local tmp1:1 = ((cc1 == 1) * val1) + (((cc1==0)) * val2); + + val1 = RSsrc(1); + val2 = RTsrc(1); + local tmp2:1 = ((cc2 == 1) * val1) + (((cc2==0)) * val2); + + val1 = RSsrc(2); + val2 = RTsrc(2); + local tmp3:1 = ((cc3 == 1) * val1) + (((cc3==0)) * val2); + + val1 = RSsrc(3); + val2 = RTsrc(3); + local tmp4:1 = ((cc4 == 1) * val1) + (((cc4==0)) * val2); + + RD = zext(tmp1) + zext(tmp2 << 8) + zext(tmp3 << 16) + zext(tmp4 << 24); +} + + +# PRECEQ.W.PHL Purpose: Precision Expand Fractional Halfword to Fractional Word Value +:preceq.w.phl RD, RTsrc is $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0xc & fct=0x12 { + RD = PRECEQ.W.PHL(RTsrc); +} + + +# PRECEQ.W.PHR Purpose: Precision Expand Fractional Halfword to Fractional Word Value +:preceq.w.phr RD, RTsrc is $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0xd & fct=0x12 { + RD = PRECEQ.W.PHR(RTsrc); +} + + +# PRECEQU.PH.QBL Purpose: Precision Expand two Unsigned Bytes to Fractional Halfword Values +:precequ.ph.qbl RD, RTsrc is $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x4 & fct=0x12 { + RD = PRECEQU.PH.QBL(RTsrc); +} + + +# PRECEQU.PH.QBLA Purpose: Precision Expand two Unsigned Bytes to Fractional Halfword Values +:precequ.ph.qbla RD, RTsrc is $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x6 & fct=0x12 { + RD = PRECEQU.PH.QBLA(RTsrc); +} + + +# PRECEQU.PH.QBR Purpose: Precision Expand two Unsigned Bytes to Fractional Halfword Values +:precequ.ph.qbr RD, RTsrc is $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x5 & fct=0x12 { + RD = PRECEQU.PH.QBR(RTsrc); +} + + +# PRECEQU.PH.QBRA Purpose: Precision Expand two Unsigned Bytes to Fractional Halfword Values +:precequ.ph.qbra RD, RTsrc is $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x7 & fct=0x12 { + RD = PRECEQU.PH.QBRA(RTsrc); +} + + +# PRECEU.PH.QBL Purpose: Precision Expand Two Unsigned Bytes to Unsigned Halfword Values +:preceu.ph.qbl RD, RTsrc is $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x1c & fct=0x12 { + RD = PRECEU.PH.QBL(RTsrc); +} + + +# PRECEU.PH.QBLA Purpose: Precision Expand Two Unsigned Bytes to Unsigned Halfword Values +:preceu.ph.qbla RD, RTsrc is $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x1e & fct=0x12 { + RD = PRECEU.PH.QBLA(RTsrc); +} + + +# PRECEU.PH.QBR Purpose: Precision Expand two Unsigned Bytes to Unsigned Halfword Values +:preceu.ph.qbr RD, RTsrc is $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x1d & fct=0x12 { + RD = PRECEU.PH.QBR(RTsrc); +} + + +# PRECEU.PH.QBRA Purpose: Precision Expand Two Unsigned Bytes to Unsigned Halfword Values +:preceu.ph.qbra RD, RTsrc is $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x1f & fct=0x12 { + RD = PRECEU.PH.QBRA(RTsrc); +} + + +# PRECR.QB.PH Purpose: Precision Reduce Four Integer Halfwords to Four Bytes +:precr.qb.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xd & fct=0x11 { + RD = PRECR.QB.PH(RSsrc, RTsrc); +} + + +# PRECR_SRA[_R].PH.W Purpose: Precision Reduce Two Integer Words to Halfwords after a Right Shift +:precr_sra.ph.w rt, rs, sa_dsp is $(AMODE) & prime=0x1f & rs & rt & sa_dsp & fct2=0x1e & fct=0x11 { + PRECR_SRA.PH.W(); +} + +:precr_sra_r.ph.w rt, rs, sa_dsp is $(AMODE) & prime=0x1f & rs & rt & sa_dsp & fct2=0x1f & fct=0x11 { + PRECR_SRA.PH.W(); +} + + +# PRECRQ.PH.W Purpose: Precision Reduce Fractional Words to Fractional Halfwords +:precrq.ph.w RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x14 & fct=0x11 { + RD = PRECRQ.PH.W(RSsrc, RTsrc); +} + + +# PRECRQ.QB.PH Purpose: Precision Reduce Four Fractional Halfwords to Four Bytes +:precrq.qb.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xc & fct=0x11 { + RD = PRECRQ.QB.PH(RSsrc, RTsrc); +} + + +# PRECRQU_S.QB.PH Purpose: Precision Reduce Fractional Halfwords to Unsigned Bytes With Saturation +:precrqu_s.qb.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xf & fct=0x11 { + RD = PRECRQU_S.QB.PH(RSsrc, RTsrc); +} + + +# PRECRQ_RS.PH.W Purpose: Precision Reduce Fractional Words to Halfwords With Rounding and Saturation +:precrq_rs.ph.w RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x15 & fct=0x11 { + RD = PRECRQ_RS.PH.W(RSsrc, RTsrc); +} + + +# PREPEND Purpose: Right Shift and Prepend Bits to the MSB +:prepend RT, RSsrc, sa_dsp is $(AMODE) & prime=0x1f & RSsrc & RT & sa_dsp & fct2=0x1 & fct=0x31 { + shift_val:1 = sa_dsp; + trunc_val:1 = ($(REGSIZE) * 8) - shift_val; + temp:$(REGSIZE) = (RSsrc << shift_val) + (RT >> trunc_val); + RT = (zext(shift_val == 0) * RT) + (zext(shift_val != 0) * temp); +} + + +# RADDU.W.QB Purpose: Unsigned Reduction Add Vector Quad Bytes +:raddu.w.qb RD, RSsrc is $(AMODE) & prime=0x1f & RSsrc & zero1620=0x0 & RD & fct2=0x14 & fct=0x10 { + RD = RADDU.W.QB(RSsrc); +} + + +# RDDSP Purpose: Read DSPControl Register Fields to a GPR +:rddsp RD, immed1625 is $(AMODE) & prime=0x1f & immed1625 & RD & fct2=0x12 & fct=0x38 { + RD = DSPControl & immed1625:$(REGSIZE); +} + +:rddsp RD is $(AMODE) & prime=0x1f & immed1625=0x1f & RD & fct2=0x12 & fct=0x38 { + RD = DSPControl; +} + + +# REPL.PH Purpose: Replicate Immediate Integer into all Vector Element Positions +:repl.ph RD, immed1625 is $(AMODE) & prime=0x1f & immed1625 & RD & fct2=0xa & fct=0x12 { + val:2 = immed1625; + repl:$(REGSIZE) = sext(val) << 16 | zext(val); + RD = repl; +} + + +# REPL.QB Purpose: Replicate Immediate Integer into all Vector Element Positions +:repl.qb RD, immed1623 is $(AMODE) & prime=0x1f & zero2425=0x0 & immed1623 & RD & fct2=0x2 & fct=0x12 { + byte:1 = immed1623; + RD = sext((byte << 24) | (byte << 16) | (byte << 8) | (byte)); +} + + +# REPLV.PH Purpose: Replicate a Halfword into all Vector Element Positions +:replv.ph RD, RTsrc is $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0xb & fct=0x12 { + RD = REPLV.PH(RTsrc); +} + + +# REPLV.QB Purpose: Replicate Byte into all Vector Element Positions +:replv.qb RD, RTsrc is $(AMODE) & prime=0x1f & zero21=0x0 & RTsrc & RD & fct2=0x3 & fct=0x12 { + RD = REPLV.QB(RTsrc); +} + + +# SHILO Purpose: Shift an Accumulator Value Leaving the Result in the Same Accumulator +:shilo ac, shift20 is $(AMODE) & prime=0x1f & shift20 & zero1619=0x0 & zero1315=0x0 & ac & fct2=0x1a & fct=0x38 { + shift_val:1 = shift20; + ac = (zext(shift_val s>= 0) * (ac >> shift_val)) + (zext(shift_val s< 0) * (ac << (-shift_val))); +} + + +# SHILOV Purpose: Variable Shift of Accumulator Value Leaving the Result in the Same Accumulator +:shilov ac, RSsrc is $(AMODE) & prime=0x1f & RSsrc & zero1620=0x0 & zero1315=0x0 & ac & fct2=0x1b & fct=0x38 { + shift_val:1 = RSsrc(1) & 0x7f; + ac = (zext(shift_val s>= 0) * (ac >> shift_val)) + (zext(shift_val s< 0) * (ac << (-shift_val))); +} + + +# SHLL[_S].PH Purpose: Shift Left Logical Vector Pair Halfwords +:shll.ph RD, RTsrc, sa_dsp2 is $(AMODE) & prime=0x1f & bit25=0x0 & sa_dsp2 & RTsrc & RD & fct2=0x8 & fct=0x13 { + shift_val:1 = sa_dsp2; + RD = SHLL.PH(RTsrc, shift_val); +} + +:shll_s.ph RD, RTsrc, sa_dsp2 is $(AMODE) & prime=0x1f & bit25=0x0 & sa_dsp2 & RTsrc & RD & fct2=0xc & fct=0x13 { + shift_val:1 = sa_dsp2; + RD= SHLL.PH(RTsrc, shift_val); +} + + +# SHLL.QB Purpose: Shift Left Logical Vector Quad Bytes +:shll.qb RD, RTsrc, sa_dsp2 is $(AMODE) & prime=0x1f & sa_dsp2 & RTsrc & RD & fct2=0x0 & fct=0x13 { + shift_val:1 = sa_dsp2; + RD = SHLL.QB(RTsrc, shift_val); +} + + +# SHLLV[_S].PH Purpose: Shift Left Logical Variable Vector Pair Halfwords +:shllv.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xa & fct=0x13 { + RD = SHLLV.PH(RTsrc, RSsrc); +} + +:shllv_s.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xe & fct=0x13 { + RD = SHLLV.PH(RTsrc, RSsrc); +} + + +# SHLLV.QB Purpose: Shift Left Logical Variable Vector Quad Bytes +:shllv.qb RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x2 & fct=0x13 { + RD = SHLLV.QB(RTsrc, RSsrc); +} + + +# SHLLV_S.W Purpose: Shift Left Logical Variable Vector Word +:shllv_s.w RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x16 & fct=0x13 { + RD = SHLLV_S.W(RTsrc, RSsrc); +} + + +# SHLL_S.W Purpose: Shift Left Logical Word with Saturation +:shll_s.w RD, RTsrc, sa_dsp2 is $(AMODE) & prime=0x1f & sa_dsp2 & RTsrc & RD & fct2=0x14 & fct=0x13 { + shift_val:1 = sa_dsp2; + RD = SHLL_S.W(RTsrc, shift_val); +} + + +# SHRA[_R].QB Purpose: Shift Right Arithmetic Vector of Four Bytes +:shra.qb RD, RTsrc, sa_dsp2 is $(AMODE) & prime=0x1f & sa_dsp2 & RTsrc & RD & fct2=0x4 & fct=0x13 { + shift_val:1 = sa_dsp2; + RD = SHRA.QB(RTsrc, shift_val); +} + +:shra_r.qb RD, RTsrc, sa_dsp2 is $(AMODE) & prime=0x1f & sa_dsp2 & RTsrc & RD & fct2=0x5 & fct=0x13 { + shift_val:1 = sa_dsp2; + RD = SHRA.QB(RTsrc, shift_val); +} + + +# SHRA[_R].PH Purpose: Shift Right Arithmetic Vector Pair Halfwords +:shra.ph RD, RTsrc, sa_dsp2 is $(AMODE) & prime=0x1f & bit25=0x0 & sa_dsp2 & RTsrc & RD & fct2=0x9 & fct=0x13 { + shift_val:1 = sa_dsp2; + RD = SHRA.PH(RTsrc, shift_val); +} + +:shra_r.ph RD, RTsrc, sa_dsp2 is $(AMODE) & prime=0x1f & bit25=0x0 & sa_dsp2 & RTsrc & RD & fct2=0xd & fct=0x13 { + shift_val:1 = sa_dsp2; + RD = SHRA.PH(RTsrc, shift_val); +} + + +# SHRAV[_R].PH Purpose: Shift Right Arithmetic Variable Vector Pair Halfwords +:shrav.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xb & fct=0x13 { + RD = SHRAV.PH(RTsrc, RSsrc); +} + +:shrav_r.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xf & fct=0x13 { + RD = SHRAV.PH(RTsrc, RSsrc); +} + + +# SHRAV[_R].QB Purpose: Shift Right Arithmetic Variable Vector of Four Bytes +:shrav.qb RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x6 & fct=0x13 { + RD = SHRAV.QB(RTsrc, RSsrc); +} + +:shrav_r.qb RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x7 & fct=0x13 { + RD = SHRAV.QB(RTsrc, RSsrc); +} + + +# SHRAV_R.W Purpose: Shift Right Arithmetic Variable Word with Rounding +:shrav_r.w RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x17 & fct=0x13 { + RD = SHRAV_R.W(RTsrc, RSsrc); +} + + +# SHRA_R.W Purpose: Shift Right Arithmetic Word with Rounding +:shra_r.w RD, RTsrc, sa_dsp2 is $(AMODE) & prime=0x1f & sa_dsp2 & RTsrc & RD & fct2=0x15 & fct=0x13 { + shift_val:1 = sa_dsp2; + RD = SHRA_R.W(RTsrc, shift_val); +} + + +# SHRL.PH Purpose: Shift Right Logical Two Halfwords +:shrl.ph RD, RTsrc, sa_dsp2 is $(AMODE) & prime=0x1f & bit25=0x0 & sa_dsp2 & RTsrc & RD & fct2=0x19 & fct=0x13 { + shift_val:1 = sa_dsp2; + RD = SHRL.PH(RTsrc, shift_val); +} + + +# SHRL.QB Purpose: Shift Right Logical Vector Quad Bytes +:shrl.qb RD, RTsrc, sa_dsp2 is $(AMODE) & prime=0x1f & sa_dsp2 & RTsrc & RD & fct2=0x1 & fct=0x13 { + shift_val:1 = sa_dsp2; + RD = SHRL.QB(RTsrc, shift_val); +} + + +# SHRLV.PH Purpose: Shift Variable Right Logical Pair of Halfwords +:shrlv.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x1b & fct=0x13 { + RD = SHRLV.PH(RTsrc, RSsrc); +} + + +# SHRLV.QB Purpose: Shift Right Logical Variable Vector Quad Bytes +:shrlv.qb RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x3 & fct=0x13 { + RD = SHRLV.QB(RTsrc, RSsrc); +} + + +# SUBQ[_S].PH Purpose: Subtract Fractional Halfword Vector +:subq.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xb & fct=0x10 { + RD = SUBQ.PH(RSsrc, RTsrc); +} + +:subq_s.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xf & fct=0x10 { + RD = SUBQ.PH(RSsrc, RTsrc); +} + + +# SUBQ_S.W Purpose: Subtract Fractional Word +:subq_s.w RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x17 & fct=0x10 { + RD = SUBQ_S.W(RSsrc, RTsrc); +} + + +# SUBQH[_R].PH Purpose: Subtract Fractional Halfword Vectors And Shift Right to Halve Results +:subqh.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x9 & fct=0x18 { + RD = SUBQH.PH(RSsrc, RTsrc); +} + +:subqh_r.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xb & fct=0x18 { + RD = SUBQH.PH(RSsrc, RTsrc); +} + + +# SUBQH[_R].W Purpose: Subtract Fractional Words And Shift Right to Halve Results +:subqh.w RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x11 & fct=0x18 { + RD = SUBQH.W(RSsrc, RTsrc); +} + +:subqh_r.w RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x13 & fct=0x18 { + RD = SUBQH.W(RSsrc, RTsrc); +} + + +# SUBU[_S].PH Purpose: Subtract Unsigned Integer Halfwords +:subu.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x9 & fct=0x10 { + RD = SUBU.PH(RSsrc, RTsrc); +} + +:subu_s.ph RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0xd & fct=0x10 { + RD = SUBU.PH(RSsrc, RTsrc); +} + + +# SUBU[_S].QB Purpose: Subtract Unsigned Quad Byte Vector +:subu.qb RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x1 & fct=0x10 { + RD = SUBU.QB(RSsrc, RTsrc); +} + +:subu_s.qb RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x5 & fct=0x10 { + RD = SUBU.QB(RSsrc, RTsrc); +} + + +# SUBUH[_R].QB Purpose: Subtract Unsigned Bytes And Right Shift to Halve Results +:subuh.qb RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x1 & fct=0x18 { + RD = SUBUH.QB(RSsrc, RTsrc); +} + +:subuh_r.qb RD, RTsrc, RSsrc is $(AMODE) & prime=0x1f & RSsrc & RTsrc & RD & fct2=0x3 & fct=0x18 { + RD = SUBUH.QB(RSsrc, RTsrc); +} + + +# WRDSP Purpose: Write Fields to DSPControl Register from a GPR +:wrdsp RSsrc, mask is $(AMODE) & prime=0x1f & RSsrc & mask & fct2=0x13 & fct=0x38 { + DSPControl = (RSsrc & mask); +} + +:wrdsp RSsrc is $(AMODE) & prime=0x1f & RSsrc & mask=0x1f & fct2=0x13 & fct=0x38 { + DSPControl = RSsrc; +} diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mips_mt.sinc b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips_mt.sinc new file mode 100644 index 0000000..b1d4c14 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mips_mt.sinc @@ -0,0 +1,152 @@ +define pcodeop fork; +define pcodeop move_from_thread_context; +define pcodeop move_from_thread_cp0; +define pcodeop move_from_thread_gpr; +define pcodeop move_from_thread_dsp; +define pcodeop move_from_thread_fpr; +define pcodeop move_from_thread_fpcr; +define pcodeop move_from_thread_cop2_data; +define pcodeop move_from_thread_cop2_control; +define pcodeop move_to_thread_context; +define pcodeop move_to_thread_cp0; +define pcodeop move_to_thread_gpr; +define pcodeop move_to_thread_dsp; +define pcodeop move_to_thread_fpr; +define pcodeop move_to_thread_fpcr; +define pcodeop move_to_thread_cop2_data; +define pcodeop move_to_thread_cop2_control; +define pcodeop yield; + +# Disable multi-threaded execution. Returns VPEControl +:dmt RT is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xB & rd32=0x1 & zero5=0xF & fct=0x1 & RT { + # Clear VPEControl IE bit (bit 15) + RT = VPEControl; VPEControl = VPEControl & ~0x8000; #VPEControl[15,1] = 0; +} + +# Disable Virtual Processor Execution. Returns VPEControl +:dvpe RT is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xB & rd32=0x0 & zero5=0x0 & fct=0x1 & RT { + # Clear MVPControl EVP bit (bit 0) + RT = MVPControl; MVPControl = MVPControl & ~0x1; +} + +# Enable multi-threaded execution. Returns VPEControl +:emt RT is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xB & rd32=0x1 & zero5=0xF & fct=0x21 & RT { + # Set VPEControl TE bit (bit 15) + RT = VPEControl; VPEControl = VPEControl | 0x8000; # VPEControl[15,1] = 1; +} + +# Enable Virtual Processor Execution. Returns VPEControl +:evpe RT is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xB & rd32=0x0 & zero5=0x0 & fct=0x21 & RT { +# Set MVPControl EVP bit (bit 0)h + RT = MVPControl; + MVPControl = MVPControl | 0x1; +} + +:fork "Thread_GPR["^RDsrc^"]", RSsrc, RTsrc is $(AMODE) & REL6=0 & prime=0x1F & zero5=0x0 & fct=0x8 & RDsrc & RSsrc & RTsrc { + fork(RDsrc, RSsrc, RTsrc); +} + +# Move From Thread Context +# MFTR general instruction +:mftr RD, RTsrc, bit5, sel, h is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0x8 & bit5 & h & bit3=0 & sel & RD & RTsrc { + tmp:$(REGSIZE) = move_from_thread_context(RTsrc, bit5:1, sel:1, h:1); + RD = tmp; +} + +# MFTR instructions have many idioms for sub-decodings +# Move from coprocessor 0 register rt, sel=sel +:mftc0 RD, "Thread_Co0["^RT0thread^"]", sel is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0x8 & bit5=0 & bit3=0 & RD & RT0thread & sel { + RD = move_from_thread_cp0(RT0thread:1, sel:1); +} + +:mftc0 RD, "Thread_Co0["^RT0thread^"]" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0x8 & bit5=0 & bit3=0 & RD & RT0thread & sel=0 { + RD = move_from_thread_cp0(RT0thread:1, 0:1); +} + +# Move from GPR[rt] +:mftgpr RD, "Thread_GPR["^RTthread^"]" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0x8 & bit5=1 & bit3=0 & sel=0x0 & RD & RTthread { + RD = move_from_thread_gpr(RTthread); +} + +RtDSP: "lo" is lohiacx=0 { } +RtDSP: "hi" is lohiacx=1 { } +RtDSP: "acx" is lohiacx=2 { } +RtDSP: "dsp" is rtmtdsp=16 { } + + +:mft^RtDSP RD, rtmtdsp is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0x8 & bit5=1 & bit3=0 & sel=0x1 & RD & RtDSP & rtmtdsp { + RD = move_from_thread_dsp(rtmtdsp); +} + +# Move from FPR[rt] +:mftc1 RD, "Thread_FPR["^FTthread^"]" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0x8 & bit5=1 & h=0 & bit3=0 & sel=0x2 & RD & FTthread { + RD = move_from_thread_fpr(FTthread, 0:1); +} + +:mfthc1 RD, "Thread_FPR["^FTthread^"]" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0x8 & bit5=1 & h=1 & bit3=0 & sel=0x2 & RD & FTthread { + RD = move_from_thread_fpr(FTthread, 1:1); +} + +# Move from FPCR[rt] +:cftc1 RD, "Thread_FPCR["^FCTthread^"]" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0x8 & bit5=1 & bit3=0 & sel=0x3 & RD & FCTthread { + RD = move_from_thread_fpcr(FCTthread); +} + +# Skipping for now: MFTR for C0P2 Data and C0P2 Control (bit5=1, sel=4/5) + +# Move to Thread Context +# MTTR general instruction +:mttr RDsrc, RTsrc, bit5, sel, h is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xc & bit5 & h & bit3=0 & sel & RDsrc & RTsrc { + move_to_thread_context(RDsrc, RTsrc, bit5:1, sel:1, h:1); +} + +# MTTR instructions have many idioms for sub-decodings +# Move rt to coprocessor 0 register rd, sel=sel +:mttc0 RTsrc, "Thread_Co0["^RD0thread^"]", sel is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xc & bit5=0 & bit3=0 & RTsrc & RD0thread & sel { + move_to_thread_cp0(RD0thread:1, RTsrc, sel:1); +} + +:mttc0 RTsrc, "Thread_Co0["^RD0thread^"]" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xc & bit5=0 & bit3=0 & RTsrc & RD0thread & sel=0 { + move_to_thread_cp0(RD0thread:1, RTsrc, 0:1); +} + +# Move to GPR[rd] +:mttgpr RTsrc, "Thread_GPR["^RDthread^"]" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xc & bit5=1 & bit3=0 & sel=0x0 & RTsrc & RDthread { + move_to_thread_gpr(RDthread, RTsrc); +} + +RdDSP: "lo" is lohiacx2=0 { } +RdDSP: "hi" is lohiacx2=1 { } +RdDSP: "acx" is lohiacx2=2 { } +RdDSP: "dsp" is rdmtdsp=16 { } + +# Move to DSP[rd] +:mtt^RdDSP RTsrc, rdmtdsp is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xc & bit5=1 & bit3=0 & sel=0x1 & RTsrc & RdDSP & rdmtdsp { + move_to_thread_dsp(rdmtdsp, RTsrc); +} + +# Move to FPR[rd] +:mttc1 RTsrc, "Thread_FPR["^FDthread^"]" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xC & bit5=1 & h=0 & bit3=0 & sel=0x2 & RTsrc & FDthread { + move_to_thread_fpr(FDthread, RTsrc, 0:1); +} + +:mtthc1 RTsrc, "Thread_FPR["^FDthread^"]" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xC & bit5=1 & h=1 & bit3=0 & sel=0x2 & RTsrc & FDthread { + move_to_thread_fpr(FDthread, RTsrc, 1:1); +} + +# Move to FPCR[rd] +:cttc1 RTsrc, "Thread_FPCR["^FCRthread^"]" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xC & bit5=1 & bit3=0 & sel=0x3 & RTsrc & FCRthread { + move_to_thread_fpcr(FCRthread, RTsrc); +} + +# Skipping for now: MTTR for C0P2 Data and C0P2 control (bit5=1, sel=4/5) + +# Conditionally Deschedule or Deallocate the Current Thread +:yield RD, RSsrc is $(AMODE) & REL6=0 & prime=0x1F & op=0 & zero5=0x0 & fct=0x9 & RD & RSsrc { + yield(RSsrc); + RD = RSsrc & YQMask; +} + +:yield RSsrc is $(AMODE) & REL6=0 & prime=0x1F & op=0 & zero5=0x0 & fct=0x9 & rd=0 & RSsrc { + yield(RSsrc); +} diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mipsfloat.sinc b/python/icicle/Ghidra/Processors/MIPS/data/languages/mipsfloat.sinc new file mode 100644 index 0000000..0696908 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mipsfloat.sinc @@ -0,0 +1,1243 @@ + +############################ +# +# MIPS Floating Point (COP1 - coprocessor 1) instructions +# includes arithmetic, compares, branch on FP condition flag, conversions +# Also Coprocessor 0 instructions +# +# Note a MIPS word is 32-bits, and a long is a 64-bit integer +# +# mipsP6float.sinc contains floating point instructions that are in pre-Release 6 but not in Release 6 +# +# mipsR6float.sinc contains floating point instructions that are in Release 6 and later +# +############################ + +define pcodeop mipsFloatPS; + +# 0100 01ff fff0 0000 ssss sddd dd00 0101 +:abs.S fd, fs is $(AMODE) & prime=17 & fct=5 & fmt1 & format=0x10 & fs & fd { + fd[0,32] = abs( fs:4 ); +} +:abs.D fd, fs is $(AMODE) & prime=17 & fct=5 & fmt1 & format=0x11 & fs & fd & fsD & fdD { + fdD = abs(fsD); +} +:abs.PS fd, fs is $(AMODE) & REL6=0 & prime=17 & fct=5 & fmt1 & fs & fd & format=0x16 & fdD & fsD { + fdD = mipsFloatPS(fsD); +} + +# 0100 01ff ffft tttt ssss sddd dd00 0000 +:add.S fd, fs, ft is $(AMODE) & prime=17 & fct=0 & fmt1 & format=0x10 & ft & fs & fd { + fd[0,32] = fs:4 f+ ft:4; +} +:add.D fd, fs, ft is $(AMODE) & prime=17 & fct=0 & fmt1 & format=0x11 & ft & fs & fd & ftD & fsD & fdD { + fdD = fsD f+ ftD; +} +:add.PS fd, fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=0 & fmt1 & ft & fs & fd & format=0x16 & ftD & fsD & fdD { + fdD = mipsFloatPS(fsD, ftD); +} + +# 0100 01ff fff0 0000 ssss sddd dd00 1010 +:ceil.l.S fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x0A & fmt2 & fd & fs & format=0x10 & fdD { + # Note this instruction is in release 2 and later + fd_tmp:4 = ceil(fs:4); # Note that ceil returns a float the same size as its argument + fdD = trunc(fd_tmp); # Note that trunc converts a float to an integer +} + +:ceil.l.D fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x0A & fmt2 & fd & fs & format=0x11 & fsD & fdD { + # Note this instruction is in release 2 and later + fsD_tmp:8 = ceil(fsD); # Note that ceil returns a float the same size as its argument + fdD = trunc(fsD_tmp); # Convert to 64-bit integer +} +# 0100 01ff fff0 0000 ssss sddd dd00 1110 +:ceil.w.S fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x0E & fmt2 & fd & fs & format=0x10 { + fs_ceil_tmp:4 = ceil(fs:4); # Note that ceil returns a float the same size as its argument + fd[0,32] = trunc(fs_ceil_tmp); +} +:ceil.w.D fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x0E & fmt2 & fd & fs & format=0x11 & fsD { + fs_tmp:8 = ceil(fsD); # Note that ceil returns a float the same size as its argument + fd[0,32] = trunc( fs_tmp ); # Need to set only 32 bits of fd +} + +# 0100 0100 010t tttt ssss s000 0000 0000 +:cfc1 RT, fs_unk is $(AMODE) & prime=17 & copop=2 & RT & fs_unk & bigfunct=0 { + tmp:4 = getCopControlWord( 1:1, fs_unk:4 ); + RT = sext(tmp); +} +:cfc1 RT, fs_fcr is $(AMODE) & prime=17 & copop=2 & RT & fs_fcr & (fs=0 | fs=25 | fs=26 | fs=28 | fs=31) & bigfunct=0 { + RT = sext(fs_fcr); +} +# Since we don't track the state of the FCSR bits, no sense in introducing complex code +#:cfc1 RT, fs_fcr is $(AMODE) & prime=17 & copop=2 & RT & fs_fcr & fs=25 & bigfunct=0 { +# tmp1:4 = (fcsr & 0x00800000) >> 23; +# tmp2:4 = (fcsr & 0xfe000000) >> 24; +# RT = sext(tmp2 + tmp1); +#} +#:cfc1 RT, fs_fcr is $(AMODE) & prime=17 & copop=2 & RT & fs_fcr & fs=26 & bigfunct=0 { +# tmp1:4 = fcsr & 0x0003f07c; +# RT = sext(tmp1); +#} +#:cfc1 RT, fs_fcr is $(AMODE) & prime=17 & copop=2 & RT & fs_fcr & fs=28 & bigfunct=0 { +# tmp1:4 = fcsr & 0x00000f83; +# tmp2:4 = (fcsr & 0x01000000) >> 24; +# RT = sext(tmp1 + tmp2); +#} +#:cfc1 RT, fs_fcr is $(AMODE) & prime=17 & copop=2 & RT & fs_fcr & fs=31 & bigfunct=0 { +# RT = sext(fcsr); +#} + +# 0100 0100 110t tttt ssss s000 0000 0000 +:ctc1 RTsrc, fs_unk is $(AMODE) & prime=17 & copop=6 & RTsrc & fs_unk & bigfunct=0 { + setCopControlWord( 1:1, fs_unk:4, RTsrc ); +} +:ctc1 RTsrc, fs_fcr is $(AMODE) & prime=17 & copop=6 & RTsrc & fs_fcr & (fs=0 | fs=25 | fs=26 | fs=28 | fs=31) & bigfunct=0 { + fs_fcr = RTsrc:$(SIZETO4); +} + +# 0100 01ff fff0 0000 ssss sddd dd10 0001 +:cvt.d.S fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x21 & fmt3 & fd & fs & format=0x10 & fdD { + # Convert from single float to double float + fdD = float2float(fs:4); +} +:cvt.d.W fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x21 & fmt3 & fd & fs & format=0x14 & fdD { + # Convert from 32-bit int word source to double float + fs_tmp:4 = fs:4; + fdD = int2float(fs_tmp); +} +:cvt.d.L fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x21 & fmt3 & fd & fs & format=0x15 & fdD & fsD { + # Note this instruction is in release 2 and later + # Convert from 64-bit long source to double float + fdD = int2float(fsD); +} +# 0100 01ff fff0 0000 ssss sddd dd10 0101 +:cvt.l.S fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x25 & fmt2 & fd & fs & format=0x10 & fdD { + # Note this instruction is in release 2 and later + # Convert from single float source to 64-bit long integer, using the fcsr RM rounding mode bits + rm_tmp:1 = fcsr[0,2]; # Get RM rounding mode bits + fs_tmp:4 = fs:4; # Get the lower 32-bits as a floating point single + fs_cvt_tmp:4 = 0; + if (rm_tmp == 0) goto ; + fs_cvt_tmp = floor(fs_tmp); # RM is 1, no rounding, and floor returns a float + goto ; + + fs_cvt_tmp = round(fs_tmp); # round returns a float + + fdD = trunc(fs_cvt_tmp); # trunc returns an integer +} +:cvt.l.D fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x25 & fmt2 & fd & fs & format=0x11 & fsD & fdD { + # Note this instruction is in release 2 and later + # Convert from double float to 64-bit long integer, using fcsr RM rounding mode bits + rm_tmp:1 = fcsr[0,2]; # Get RM rounding mode bits + if (rm_tmp == 0) goto ; + fd_tmp:8 = floor(fsD); # RM is 1, no rounding + goto ; + + fd_tmp = round(fsD); + + fdD = trunc(fd_tmp); +} +# 0100 0110 000t tttt ssss sddd dd10 0110 +:cvt.PS.S fd, fs, ft is $(AMODE) & REL6=0 & prime=0x11 & format=0x10 & fct=0x26 & fd & fs & ft & ftD & fsD & fdD { + fdD = mipsFloatPS(fsD, ftD); +} + +# 0100 01ff fff0 0000 ssss sddd dd10 0000 +:cvt.s.D fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x20 & fmt4 & fd & fs & format=0x11 & fsD { + fd[0,32] = float2float(fsD); +} +:cvt.s.W fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x20 & fmt4 & fd & fs & format=0x14 { + fd[0,32] = int2float(fs:4); +} +:cvt.s.L fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x20 & fmt4 & fd & fs & format=0x15 & fsD { + # Note this instruction is in release 2 and later + fd[0,32] = int2float(fsD); +} +# 0100 0110 1100 0000 ssss sddd dd10 1000 +:cvt.s.pl fd, fs is $(AMODE) & REL6=0 & prime=0x11 & format=0x16 & ft=0x0 & fct=0x28 & fd & fs & fdD & fsD { + fdD = mipsFloatPS(fsD); +} +# 0100 0110 1100 0000 ssss sddd dd10 0000 +:cvt.s.pu fd, fs is $(AMODE) & REL6=0 & prime=0x11 & format=0x16 & ft=0x0 & fct=0x20 & fd & fs & fdD & fsD { + fdD = mipsFloatPS(fsD); +} + +# 0100 01ff fff0 0000 ssss sddd dd10 0100 +:cvt.w.S fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x24 & fmt2 & fd & fs & format=0x10 { + # Convert from single float source to 32-bit integer word, using the fcsr RM rounding mode bits + rm_tmp:1 = fcsr[0,2]; # Get RM rounding mode bits + fs_tmp:4 = fs:4; + fs_cvt_tmp:4 = 0; + if (rm_tmp == 0) goto ; + fs_cvt_tmp = floor(fs_tmp); # RM is 1, no rounding, and floor returns a float + goto ; + + fs_cvt_tmp = round(fs_tmp); # round returns a float + + fd[0,32] = trunc(fs_cvt_tmp); # trunc returns an integer +} +:cvt.w.D fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x24 & fmt2 & fd & fs & format=0x11 & fsD { + # Convert from double float source to 32-bit integer word, using the fcsr RM rounding mode bits + rm_tmp:1 = fcsr[0,2]; # Get RM rounding mode bits + if (rm_tmp == 0) goto ; + fs_tmp:8 = floor(fsD); # RM is 1, no rounding + goto ; + + fs_tmp = round(fsD); + + fd[0,32] = trunc(fs_tmp); +} + +# 0100 01ff ffft tttt ssss sddd dd00 0011 +:div.S fd, fs, ft is $(AMODE) & prime=17 & fct=3 & fmt2 & ft & fs & fd & format=0x10 { + fd[0,32] = fs:4 f/ ft:4; +} +:div.D fd, fs, ft is $(AMODE) & prime=17 & fct=3 & fmt2 & ft & fs & fd & format=0x11 & fdD & fsD & ftD { + fdD = fsD f/ ftD; +} + +# 0100 01ff fff0 0000 ssss sddd dd00 1011 +:floor.l.S fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x0B & fmt2 & fd & fs & format=0x10 & fdD { + # Note this instruction is in release 2 and later + # Convert floor of single float to a 64-bit long integer + fd_tmp:4 = floor(fs:4); # returns a float + fdD = trunc(fd_tmp); # converts float to int +} +:floor.l.D fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x0B & fmt2 & fd & fs & format=0x11 & fdD & fsD { + # Note this instruction is in release 2 and later + fsD_tmp:8 = floor(fsD); + fdD = trunc(fsD_tmp); +} +# 0100 01ff fff0 0000 ssss sddd dd00 1111 +:floor.w.S fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x0F & fmt2 & fd & fs & format=0x10 { + # Floor of single float copied to a 32-bit integer word + fd_tmp:4 = floor(fs:4); # returns a float + fd = trunc(fd_tmp); # converts float to int +} +:floor.w.D fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x0F & fmt2 & fd & fs & format=0x11 & fsD { + # Floor of double float to a 32-bit integer word + fd[0,32] = trunc(floor(fsD)); +} + +# 1101 01bb bbbt tttt iiii iiii iiii iiii +:ldc1 ft, OFF_BASE is $(AMODE) & prime=53 & OFF_BASE & ft & ftD { + ftD = *[ram]:8 OFF_BASE; +} + +# 1111 01bb bbbt tttt iiii iiii iiii iiii +:sdc1 ft, OFF_BASE is $(AMODE) & prime=61 & OFF_BASE & ft & ftD { + *[ram]:8 OFF_BASE = ftD; +} + +# 1100 01bb bbbt tttt iiii iiii iiii iiii +:lwc1 ft, OFF_BASE is $(AMODE) & prime=49 & OFF_BASE & ft { + ft[0,32] = *[ram]:4 OFF_BASE; +} + +# 0100 0100 000t tttt ssss s000 0000 0000 +:mfc1 RT, fs is $(AMODE) & prime=17 & copop=0 & RT & fs & bigfunct=0 { + # Move just a word, 32-bits + RT = sext( fs:$(SIZETO4) ); +} + +# 0100 0100 011t tttt ssss s000 0000 0000 +:mfhc1 RT, fs is $(AMODE) & prime=17 & copop=3 & bigfunct=0 & RT & fs & fsD { + RT = sext(fsD[32,32]); +} + +# 0100 01ff fff0 0000 ssss sddd dd00 0110 +:mov.S fd, fs is $(AMODE) & prime=17 & fct=6 & fmt1 & fs & fd & format=0x10 { + fd[0,32] = fs:4; +} +:mov.D fd, fs is $(AMODE) & prime=17 & fct=6 & fmt1 & fs & fd & format=0x11 & fdD & fsD { + fdD = fsD; +} +:mov.PS fd, fs is $(AMODE) & REL6=0 & prime=17 & fct=6 & fmt1 & fs & fd & format=0x16 & fsD & fdD { + fdD = mipsFloatPS(fsD); +} + +# 0100 0100 100t tttt dddd d000 0000 0000 +:mtc1 RTsrc, fs is $(AMODE) & prime=17 & copop=4 & RTsrc & fs & bigfunct=0 { + # Move 32-bits of RTsrc to Low Half of FPR fs + fs[0,32] = RTsrc:$(SIZETO4); +} + +# 0100 0100 111t tttt ssss s000 0000 0000 +:mthc1 RTsrc, fs is $(AMODE) & prime=17 & copop=0x07 & bigfunct=0x0 & RTsrc & fs & fsD { + # Move 32-bits of RTsrc to High Half of FPR + fsD[32,32] = RTsrc:4; +} + +# 0100 01ff ffft tttt ssss sddd dd00 0010 +:mul.S fd, fs, ft is $(AMODE) & prime=17 & fct=2 & fmt1 & ft & fs & fd & format=0x10 { + fd[0,32] = fs:4 f* ft:4; # need to only get the single float 32-bit (fs might be 64-bits) +} +:mul.D fd, fs, ft is $(AMODE) & prime=17 & fct=2 & fmt1 & ft & fs & fd & format=0x11 & fdD & fsD & ftD { + fdD = fsD f* ftD; +} +:mul.PS fd, fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=2 & fmt1 & ft & fs & fd & format=0x16 & ftD & fsD & fdD { + fdD = mipsFloatPS(fsD, ftD); +} + +# 0100 01ff fff0 0000 ssss sddd dd00 0111 +:neg.S fd, fs is $(AMODE) & prime=17 & fct=7 & fmt1 & fs & fd & format=0x10 { + fd[0,32] = f- fs:4; +} +:neg.D fd, fs is $(AMODE) & prime=17 & fct=7 & fmt1 & fs & fd & format=0x11 & fdD & fsD { + fdD = f- fsD; +} +:neg.PS fd, fs is $(AMODE) & REL6=0 & prime=17 & fct=7 & fmt1 & fs & fd & format=0x16 & fsD & fdD { + fdD = mipsFloatPS(fsD); +} + +# 0100 01ff fff0 0000 ssss sddd dd01 0101 +:recip.S fd, fs is $(AMODE) & prime=17 & ft=0 & fct=21 & fmt2 & fd & fs & format=0x10 { + fd[0,32] = 1:4 f/ fs:4; +} +:recip.D fd, fs is $(AMODE) & prime=17 & ft=0 & fct=21 & fmt2 & fd & fs & format=0x11 & fdD & fsD { + fdD = 1:8 f/ fsD; +} + +# 0100 01ff fff0 0000 ssss sddd dd00 1000 +:round.l.S fd, fs is $(AMODE) & prime=17 & ft=0 & fct=8 & fmt2 & fd & fs & format=0x10 & fdD { + # Note this instruction is in release 2 and later + fd_tmp:4 = round(fs:4); # round returns a float of the same size are the arg + fdD = trunc(fd_tmp); # trunc converts to any size integer +} +:round.l.D fd, fs is $(AMODE) & prime=17 & ft=0 & fct=8 & fmt2 & fd & fs &format=0x11 & fsD & fdD { + # Note this instruction is in release 2 and later + fsD_tmp:8 = round(fsD); + fdD = trunc(fsD_tmp); +} +# 0100 01ff fff0 0000 ssss sddd dd00 1100 +:round.w.S fd, fs is $(AMODE) & prime=17 & ft=0 & fct=12 & fmt2 & fd & fs & format=0x10 { + fd_tmp:4 = round(fs:4); + fd = trunc(fd_tmp); +} +:round.w.D fd, fs is $(AMODE) & prime=17 & ft=0 & fct=12 & fmt2 & fd & fs & format=0x11 & fsD { + fdD_tmp:8 = round(fsD); # round returns a float, not an int + fd[0,32] = trunc(fdD_tmp); # We need only a 32-bit integer +} + +# 0100 01ff fff0 0000 ssss sddd dd01 0110 +:rsqrt.S fd, fs is $(AMODE) & prime=17 & ft=0 & fct=22 & fmt2 & fd & fs & format=0x10 { + fd[0,32] = 1:4 f/ sqrt(fs:4); +} +:rsqrt.D fd, fs is $(AMODE) & prime=17 & ft=0 & fct=22 & fmt2 & fd & fs & format=0x11 & fdD & fsD { + fdD = 1:8 f/ sqrt(fsD); +} + +# 0100 01ff fff0 0000 ssss sddd dd00 0100 +:sqrt.S fd, fs is $(AMODE) & prime=17 & ft=0 & fct=4 & fmt2 & fd & fs & format=0x10 { + fd[0,32] = sqrt(fs:4); +} +:sqrt.D fd, fs is $(AMODE) & prime=17 & ft=0 & fct=4 & fmt2 & fd & fs & format=0x11 & fsD & fdD { + fdD = sqrt(fsD); +} + +# 0100 01ff ffft tttt ssss sddd dd00 0001 +:sub.S fmt1 fd, fs, ft is $(AMODE) & prime=17 & fct=1 & fmt1 & ft & fs & fd & format=0x10 { + fd[0,32] = fs:4 f- ft:4; +} +:sub.D fmt1 fd, fs, ft is $(AMODE) & prime=17 & fct=1 & fmt1 & ft & fs & fd & format=0x11 & fdD & fsD & ftD { + fdD = fsD f- ftD; +} +:sub.PS fmt1 fd, fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=1 & fmt1 & ft & fs & fd & format=0x16 & ftD & fsD & fdD { + fdD = mipsFloatPS(fsD, ftD); +} + +# 1110 01bb bbbt tttt iiii iiii iiii iiii +:swc1 ft, OFF_BASE is $(AMODE) & prime=57 & OFF_BASE & ft { + *[ram]:4 OFF_BASE = ft:$(SIZETO4); +} + +# 0100 01ff fff0 0000 ssss sddd dd00 1001 +:trunc.l.S fd, fs is $(AMODE) & prime=17 & cop1code=0 & fmt2 & fs & fd & fct=9 & format=0x10 & fdD { + # Note this instruction is in release 2 and later + fd = trunc(fs:4); +} +:trunc.l.D fd, fs is $(AMODE) & prime=17 & cop1code=0 & fmt2 & fs & fd & fct=9 & format=0x11 & fdD & fsD { + # Note this instruction is in release 2 and later + fdD = trunc(fsD); +} +# 0100 01ff fff0 0000 ssss sddd dd00 1101 +:trunc.w.S fd, fs is $(AMODE) & prime=17 & cop1code=0 & fmt2 & fs & fd & fct=13 & format=0x10 { + fd[0,32] = trunc(fs:4); +} +:trunc.w.D fd, fs is $(AMODE) & prime=17 & cop1code=0 & fmt2 & fs & fd & fct=13 & format=0x11 & fsD { + fd[0,32] = trunc(fsD); +} + +############################ +# +# COP1X (Extended FP) +# +############################ + +# 0100 11ss ssst tttt ssss sddd dd01 1110 +:alnv.PS fd, fs, ft, rs is $(AMODE) & REL6=0 & prime=0x13 & fct=0x1E & rs & ft & fs & fd & ftD & fsD & fdD { + fdD = mipsFloatPS(fsD, ftD); +} + +# 0100 11bb bbbi iiii 0000 0ddd dd00 0001 +:ldxc1 fd, INDEX_BASE is $(AMODE) & REL6=0 & prime=0x13 & zero4=0 & fct=0x01 & INDEX_BASE & fd & fdD { + fdD = *[ram]:8 INDEX_BASE; +} + +# 0100 11bb bbbi iiii 0000 0ddd dd00 0101 +:luxc1 fd, INDEX_BASE is $(AMODE) & REL6=0 & prime=0x13 & zero4=0 & fct=0x05 & INDEX_BASE & fd & fdD { + ptr:$(ADDRSIZE) = INDEX_BASE & -16:$(ADDRSIZE); + fdD = *[ram]:8 ptr; +} + +# 0100 11bb bbbi iiii 0000 0ddd dd00 0000 +:lwxc1 fd, INDEX_BASE is $(AMODE) & REL6=0 & prime=0x13 & zero4=0 & fct=0x0 & INDEX_BASE & fd { + fd[0,32] = *[ram]:4 INDEX_BASE; +} + +# 0100 11rr rrrt tttt ssss sddd dd10 0fff +:madd.S fd, fr, fs, ft is $(AMODE) & REL6=0 & prime=0x13 & op4=0x04 & fmt5 & fd & fr & fs & ft & format1X=0x0 { + fd[0,32] = (fs:4 f* ft:4) f+ fr:4; # must do floating arithmetic in 32 bit +} +:madd.D fd, fr, fs, ft is $(AMODE) & REL6=0 & prime=0x13 & op4=0x04 & fmt5 & fd & fr & fs & ft & + format1X=0x1 & fdD & fsD & frD & ftD { + fdD = (fsD f* ftD) f+ frD; +} +:madd.PS fd, fr, fs, ft is $(AMODE) & REL6=0 & prime=0x13 & op4=0x04 & fmt5 & fd & fr & fs & ft & format1X=0x6 & ftD & fsD & fdD { + fdD = mipsFloatPS(fsD, ftD); +} + +# 0100 11rr rrrt tttt ssss sddd dd10 1fff +:msub.S fd, fr, fs, ft is $(AMODE) & REL6=0 & prime=0x13 & op4=0x05 & fmt5 & fd & fr & fs & ft & format1X=0x0 { + fd[0,32] = (fs:4 f* ft:4) f- fr:4; # must do floating arithmetic in 32 bit +} +:msub.D fd, fr, fs, ft is $(AMODE) & REL6=0 & prime=0x13 & op4=0x05 & fmt5 & fd & fr & fs & ft & + format1X=0x1 & fdD & fsD & ftD & frD { + fdD = (fsD f* ftD) f- frD; +} +:msub.PS fd, fr, fs, ft is $(AMODE) & REL6=0 & prime=0x13 & op4=0x05 & fmt5 & fd & fr & fs & ft & format1X=0x6 & ftD & fsD & fdD { + fdD = mipsFloatPS(fsD, ftD); +} + +# 0100 11rr rrrt tttt ssss sddd dd11 0fff +:nmadd.S fd, fr, fs, ft is $(AMODE) & REL6=0 & prime=0x13 & op4=0x06 & fmt5 & fd & fr & fs & ft & format1X=0x0 { + fd[0,32] = f- (fs:4 f* ft:4) f+ fr:4; # must do floating arithmetic in 32 bit +} +:nmadd.D fd, fr, fs, ft is $(AMODE) & REL6=0 & prime=0x13 & op4=0x06 & fmt5 & fd & fr & fs & ft & + format1X=0x1 & fdD & fsD & ftD & frD { + fdD = f- ((fsD f* ftD) f+ frD); +} +:nmadd.PS fd, fr, fs, ft is $(AMODE) & REL6=0 & prime=0x13 & op4=0x06 & fmt5 & fd & fr & fs & ft & format1X=0x6 & ftD & fsD & fdD { + fdD = mipsFloatPS(fsD, ftD); +} + +# 0100 11rr rrrt tttt ssss sddd dd11 1fff +:nmsub.S fd, fr, fs, ft is $(AMODE) & REL6=0 & prime=0x13 & op4=0x07 & fmt5 & fd & fr & fs & ft & format1X=0x0 { + fd[0,32] = f- (fs:4 f* ft:4) f- fr:4; # must do floating arithmetic in 32 bit +} +:nmsub.D fd, fr, fs, ft is $(AMODE) & REL6=0 & prime=0x13 & op4=0x07 & fmt5 & fd & fr & fs & ft & + format1X=0x1 & fdD & fsD & ftD & frD { + fdD = f- ((fsD f* ftD) f- frD); +} +:nmsub.PS fd, fr, fs, ft is $(AMODE) & REL6=0 & prime=0x13 & op4=0x07 & fmt5 & fd & fr & fs & ft & format1X=0x6 & ftD & fsD & fdD { + fdD = mipsFloatPS(fsD, ftD); +} + +# 0100 11bb bbbi iiii hhhh h000 0000 1111 +:prefx hint, INDEX_BASE is $(AMODE) & REL6=0 & prime=0x13 & zero5=0x0 & fct=0x0F & hint & INDEX_BASE { + prefetch(INDEX_BASE, hint:1); +} +# 0100 11bb bbbi iiii ssss s000 0000 1001 +:sdxc1 fs, INDEX_BASE is $(AMODE) & REL6=0 & prime=0x13 & zero5=0x0 & fct=0x09 & fs & fsD & INDEX_BASE { + *[ram]:8 INDEX_BASE = fsD; +} +# 0100 11bb bbbi iiii ssss s000 0000 1101 +:suxc1 fs, INDEX_BASE is $(AMODE) & REL6=0 & prime=19 & fct=13 & INDEX_BASE & fs & fsD { + INDEX_BASE = INDEX_BASE & 0xfffffffffffffff0; + *[ram]:8 INDEX_BASE = fsD; +} +# 0100 11bb bbbi iiii ssss s000 0000 1000 +:swxc1 fs, INDEX_BASE is $(AMODE) & REL6=0 & prime=19 & INDEX_BASE & fs & fd=0 & fct=8 { + *[ram]:4 INDEX_BASE = fs:$(SIZETO4); +} +#### +# +# Pre-6 semantics +# +#### +# 0100 0101 000c cc00 iiii iiii iiii iiii +:bc1f Rel16 is $(AMODE) & REL6=0 & prime=17 & copop=8 & cc=0 & nd=0 & tf=0 & Rel16 { + tmp:1 = fcsr[23,1]; # The floating point condition bit + delayslot(1); + if (tmp != 0) goto inst_next; + goto Rel16; +} +:bc1f cc,Rel16 is $(AMODE) & REL6=0 & prime=17 & copop=8 & cc & nd=0 & tf=0 & Rel16 { + # tmp:1 = getFpCondition(cc:1); # Note that other cc conditions are not implemented + tmp:1 = fcsr[23,1]; # The floating point condition bit + delayslot(1); + if (tmp != 0) goto inst_next; + goto Rel16; +} +# 0100 0101 000c cc10 iiii iiii iiii iiii +:bc1fl Rel16 is $(AMODE) & REL6=0 & prime=17 & copop=8 & cc=0 & nd=1 & tf=0 & Rel16 { + tmp:1 = fcsr[23,1]; + if (tmp != 0) goto inst_next; + delayslot(1); + goto Rel16; +} +:bc1fl cc,Rel16 is $(AMODE) & REL6=0 & prime=17 & copop=8 & cc & nd=1 & tf=0 & Rel16 { + # tmp:1 = getFpCondition(cc:1); + tmp:1 = fcsr[23,1]; # The floating point condition bit + if (tmp != 0) goto inst_next; + delayslot(1); + goto Rel16; +} + +# 0100 0101 000c cc01 iiii iiii iiii iiii +:bc1t Rel16 is $(AMODE) & REL6=0 & prime=17 & copop=8 & cc=0 & nd=0 & tf=1 & Rel16 { + tmp:1 = fcsr[23,1]; + delayslot(1); + if (tmp == 0) goto inst_next; + goto Rel16; +} +:bc1t cc,Rel16 is $(AMODE) & REL6=0 & prime=17 & copop=8 & cc & nd=0 & tf=1 & Rel16 { + # tmp:1 = getFpCondition(cc:1); + tmp:1 = fcsr[23,1]; # The floating point condition bit + delayslot(1); + if (tmp == 0) goto inst_next; + goto Rel16; +} +# 0100 0101 000c cc11 iiii iiii iiii iiii +:bc1tl Rel16 is $(AMODE) & REL6=0 & prime=17 & copop=8 & cc=0 & nd=1 & tf=1 & Rel16 { + tmp:1 = fcsr[23,1]; + if (tmp == 0) goto inst_next; + delayslot(1); + goto Rel16; +} +:bc1tl cc,Rel16 is $(AMODE) & REL6=0 & prime=17 & copop=8 & cc & nd=1 & tf=1 & Rel16 { + # tmp:1 = getFpCondition(cc:1); + tmp:1 = fcsr[23,1]; # The floating point condition bit + if (tmp == 0) goto inst_next; + delayslot(1); + goto Rel16; +} + +# The pre-release 6 floating point compare instructions, c.condn.S or .D, set the fcsr bit 23 + +macro trapIfNaN(x1, x2) { } +macro trapIfSNaN(x1, x2) { } + +:c.f.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=48 & fmt1 & format=0x10 & fs & ft { + trapIfSNaN(fs:4, ft:4); # Trap if either operand is a Signaling NaN + fcsr[23,1] = 0; # Always false +} +:c.f.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=48 & fmt1 & format=0x11 & fs & ft & fsD & ftD { + trapIfSNaN(fsD, ftD); + fcsr[23,1] = 0; +} +:c.f.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=48 & fmt1 & fs & ft & format=0x16 & ftD & fsD & fdD { + fcsr[23,1] = mipsFloatPS(fsD, ftD); +} + +:c.un.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=49 & fmt1 & format=0x10 & fs & ft { + trapIfSNaN(fs:4, ft:4); + fcsr[23,1] = nan(fs:4) || nan(ft:4); # True if operands are NaN +} +:c.un.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=49 & fmt1 & fs & ft & format=0x11 & fsD & ftD { + trapIfSNaN(fsD, ftD); + fcsr[23,1] = nan(fsD) || nan(ftD); +} +:c.un.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=49 & fmt1 & fs & ft & format=0x16 & ftD & fsD { + fcsr[23,1] = mipsFloatPS(fsD, ftD); +} + +:c.eq.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=50 & fmt1 & format=0x10 & fs & ft { + trapIfSNaN(fs:4, ft:4); + fcsr[23,1] = (fs:4 f== ft:4); +} +:c.eq.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=50 & fmt1 & fs & ft & format=0x11 & fsD & ftD { + trapIfSNaN(fsD, ftD); + fcsr[23,1] = (fsD f== ftD); +} +:c.eq.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=50 & fmt1 & fs & ft & format=0x16 & ftD & fsD { + fcsr[23,1] = mipsFloatPS(fsD, ftD); +} + +:c.ueq.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=51 & fmt1 & format=0x10 & fs & ft { + trapIfSNaN(fs:4, ft:4); + fcsr[23,1] = (fs:4 f== ft:4); +} +:c.ueq.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=51 & fmt1 & fs & ft & format=0x11 & fsD & ftD { + trapIfSNaN(fsD, ftD); + fcsr[23,1] = (fsD f== ftD); +} +:c.ueq.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=51 & fmt1 & fs & ft & format=0x16 & ftD & fsD { + fcsr[23,1] = mipsFloatPS(fsD, ftD); +} + +:c.olt.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=52 & fmt1 & format=0x10 & fs & ft { + trapIfSNaN(fs:4, ft:4); + fcsr[23,1] = (fs:4 f< ft:4); +} +:c.olt.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=52 & fmt1 & fs & ft & format=0x11 & fsD & ftD { + trapIfSNaN(fsD, ftD); + fcsr[23,1] = (fsD f< ftD); +} +:c.olt.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=52 & fmt1 & fs & ft & format=0x16 & ftD & fsD { + fcsr[23,1] = mipsFloatPS(fsD, ftD); +} + +:c.ult.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=53 & fmt1 & format=0x10 & fs & ft { + trapIfSNaN(fs:4, ft:4); + fcsr[23,1] = (fs:4 f< ft:4) || nan(fs:4) || nan(ft:4); # Less than or NaN +} +:c.ult.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=53 & fmt1 & fs & ft & format=0x11 & fsD & ftD { + trapIfSNaN(fsD, ftD); + fcsr[23,1] = (fsD f< ftD) || nan(fsD) || nan(ftD); +} +:c.ult.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=53 & fmt1 & fs & ft & format=0x16 & ftD & fsD { + fcsr[23,1] = mipsFloatPS(fsD, ftD); +} + +:c.ole.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=54 & fmt1 & format=0x10 & fs & ft { + trapIfSNaN(fs:4, ft:4); + fcsr[23,1] = (fs:4 f<= ft:4); +} +:c.ole.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=54 & fmt1 & fs & ft & format=0x11 & fsD & ftD { + trapIfSNaN(fsD, ftD); + fcsr[23,1] = (fsD f<= ftD); +} +:c.ole.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=54 & fmt1 & fs & ft & format=0x16 & ftD & fsD { + fcsr[23,1] = mipsFloatPS(fsD, ftD); +} + +:c.ule.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=55 & fmt1 & format=0x10 & fs & ft { + trapIfSNaN(fs:4, ft:4); + fcsr[23,1] = (fs:4 f<= ft:4) || nan(fs:4) || nan(ft:4); # Less than or equal or NaN +} +:c.ule.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=55 & fmt1 & fs & ft & format=0x11 & fsD & ftD { + trapIfSNaN(fsD, ftD); + fcsr[23,1] = (fsD f<= ftD) || nan(fsD) || nan(ftD); +} +:c.ule.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=55 & fmt1 & fs & ft & format=0x16 & ftD & fsD { + fcsr[23,1] = mipsFloatPS(fsD, ftD); +} + +# The pre-release 6 floating point compare instructions that trap if either operand is NaN (either QNaN or SNaN) + +:c.sf.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=56 & fmt1 & fs & ft & format=0x10 { + trapIfNaN(fs:4, ft:4); + fcsr[23,1] = 0; # Always false +} +:c.sf.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=56 & fmt1 & fs & ft & format=0x11 & fsD & ftD { + trapIfNaN(fsD, ftD); + fcsr[23,1] = 0; +} +:c.sf.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=56 & fmt1 & fs & ft & format=0x16 & ftD & fsD { + fcsr[23,1] = mipsFloatPS(fsD, ftD); +} + +:c.ngle.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=57 & fmt1 & format=0x10 & fs & ft { + trapIfNaN(fs:4, ft:4); + fcsr[23,1] = nan(fs:4) || nan(ft:4); +} +:c.ngle.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=57 & fmt1 & fs & ft & format=0x11 & fsD & ftD { + trapIfNaN(fsD, ftD); + fcsr[23,1] = nan(fsD) || nan(ftD); +} +:c.ngle.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=57 & fmt1 & fs & ft & format=0x16 & ftD & fsD { + fcsr[23,1] = mipsFloatPS(fsD, ftD); +} + +:c.seq.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=58 & fmt1 & format=0x10 & fs & ft { + trapIfNaN(fs:4, ft:4); + fcsr[23,1] = (fs:4 f== ft:4); +} +:c.seq.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=58 & fmt1 & fs & ft & format=0x11 & fsD & ftD { + trapIfNaN(fsD, ftD); + fcsr[23,1] = (fsD f== ftD); +} +:c.seq.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=58 & fmt1 & fs & ft & format=0x16 & ftD & fsD { + fcsr[23,1] = mipsFloatPS(fsD, ftD); +} + +:c.ngl.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=59 & fmt1 & format=0x10 & fs & ft { + trapIfNaN(fs:4, ft:4); + fcsr[23,1] = (fs:4 f== ft:4) || nan(fs:4) || nan(ft:4); +} +:c.ngl.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=59 & fmt1 & fs & ft & format=0x11 & fsD & ftD { + trapIfNaN(fsD, ftD); + fcsr[23,1] = (fsD f== ftD) || nan(fsD) || nan(ftD); +} +:c.ngl.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=59 & fmt1 & fs & ft & format=0x16 & ftD & fsD { + fcsr[23,1] = mipsFloatPS(fsD, ftD); +} + +:c.lt.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=60 & fmt1 & format=0x10 & fs & ft { + trapIfNaN(fs:4, ft:4); + fcsr[23,1] = (fs:4 f< ft:4); +} +:c.lt.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=60 & fmt1 & fs & ft & format=0x11 & fsD & ftD { + trapIfNaN(fsD, ftD); + fcsr[23,1] = (fsD f< ftD); +} +:c.lt.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=60 & fmt1 & fs & ft & format=0x16 & ftD & fsD { + fcsr[23,1] = mipsFloatPS(fsD, ftD); +} + +:c.nge.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=61 & fmt1 & format=0x10 & fs & ft { + trapIfNaN(fs:4, ft:4); + fcsr[23,1] = (fs:4 f< ft:4) || nan(fs:4) || nan(ft:4); +} +:c.nge.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=61 & fmt1 & fs & ft & format=0x11 & fsD & ftD { + trapIfNaN(fsD, ftD); + fcsr[23,1] = (fsD f< ftD) || nan(fsD) || nan(ftD); +} +:c.nge.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=61 & fmt1 & fs & ft & format=0x16 & ftD & fsD { + fcsr[23,1] = mipsFloatPS(fsD, ftD); +} + +:c.le.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=62 & fmt1 & format=0x10 & fs & ft { + trapIfNaN(fs:4, ft:4); + fcsr[23,1] = (fs:4 f<= ft:4); +} +:c.le.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=62 & fmt1 & fs & ft & format=0x11 & fsD & ftD { + trapIfNaN(fsD, ftD); + fcsr[23,1] = (fsD f<= ftD); +} +:c.le.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=62 & fmt1 & fs & ft & format=0x16 & ftD & fsD { + fcsr[23,1] = mipsFloatPS(fsD, ftD); +} + +:c.ngt.S fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=63 & fmt1 & format=0x10 & fs & ft { + trapIfNaN(fs:4, ft:4); + fcsr[23,1] = (fs:4 f<= ft:4) || nan(fs:4) || nan(ft:4); # Less than or equal or NaN +} +:c.ngt.D fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=63 & fmt1 & fs & ft & format=0x11 & fsD & ftD { + trapIfNaN(fsD, ftD); + fcsr[23,1] = (fsD f<= ftD) || nan(fsD) || nan(ftD); +} +:c.ngt.PS fs, ft is $(AMODE) & REL6=0 & prime=17 & fct=63 & fmt1 & fs & ft & format=0x16 & ftD & fsD { + fcsr[23,1] = mipsFloatPS(fsD, ftD); +} + +# 0000 00ss sssc cc00 dddd d000 0000 0001 +:movf RD, RSsrc, cc is $(AMODE) & REL6=0 & prime=0 & nd=0 & tf=0 & zero5=0 & fct=1 & RD & RSsrc & cc { + # Move if FP condition flag is false + tmp:1 = fcsr[23,1]; + if (tmp != 0) goto ; + RD = RSsrc; + +} + +# 0100 01ff fffc cc00 ssss sddd dd01 0001 +:movf.S fd, fs, cc is $(AMODE) & REL6=0 & prime=17 & nd=0 & tf=0 & fct=17 & fmt1 & fd & fs & cc & format=0x10 { + # Move if FP condition flag is false + tmp:1 = fcsr[23,1]; + if (tmp != 0) goto ; + fd[0,32] = fs:4; + +} +:movf.D fd, fs, cc is $(AMODE) & REL6=0 & prime=17 & nd=0 & tf=0 & fct=17 & fmt1 & fd & fs & cc & format=0x11 & fdD & fsD { + # Move if FP condition flag is false + tmp:1 = fcsr[23,1]; + if (tmp != 0) goto ; + fdD = fsD; + +} +:movf.PS fd, fs, cc is $(AMODE) & REL6=0 & prime=17 & nd=0 & tf=0 & fct=17 & fmt1 & fd & fs & cc & format=0x16 & fsD & fdD { + fdD = mipsFloatPS(fcsr[23,1], fsD); +} + +# 0100 01ff ffft tttt ssss sddd dd01 0011 +:movn.S fd, fs, RTsrc is $(AMODE) & REL6=0 & prime=17 & fct=19 & fmt1 & fd & fs & RTsrc & format=0x10 { + if (RTsrc == 0) goto ; + fd[0,32] = fs:4; + +} +:movn.D fd, fs, RTsrc is $(AMODE) & REL6=0 & prime=17 & fct=19 & fmt1 & fd & fs & RTsrc & format=0x11 & fdD & fsD { + if (RTsrc == 0) goto ; + fdD = fsD; + +} +:movn.PS fd, fs, RTsrc is $(AMODE) & REL6=0 & prime=17 & fct=19 & fmt1 & fd & fs & RTsrc & format=0x16 & fsD & fdD { + fdD = mipsFloatPS(fcsr[23,1], fsD); +} + +# 0000 00ss sssc cc01 dddd d000 0000 0001 +:movt RD, RSsrc, cc is $(AMODE) & REL6=0 & prime=0 & nd=0 & tf=1 & zero5=0 & fct=1 & RD & RSsrc & cc { + # Move if FP condition flag is true + tmp:1 = fcsr[23,1]; + if (tmp != 1) goto ; + RD = RSsrc; + +} + +# 0100 01ff fffc cc01 ssss sddd dd01 0001 +:movt.S fd, fs, cc is $(AMODE) & REL6=0 & prime=17 & nd=0 & tf=1 & fct=17 & fmt1 & fd & fs & cc & format=0x10 { + # Move if FP condition flag is true + tmp:1 = fcsr[23,1]; + if (tmp != 1) goto ; + fd[0,32] = fs:4; + +} +:movt.D fd, fs, cc is $(AMODE) & REL6=0 & prime=17 & nd=0 & tf=1 & fct=17 & fmt1 & fd & fs & cc & format=0x11 & fdD & fsD { + # Move if FP condition flag is true + tmp:1 = fcsr[23,1]; + if (tmp != 1) goto ; + fdD = fsD; + +} +:movt.PS fd, fs, cc is $(AMODE) & REL6=0 & prime=17 & nd=0 & tf=1 & fct=17 & fmt1 & fd & fs & cc & format=0x16 & fsD & ftD & fdD { + fdD = mipsFloatPS(fsD, ftD); +} + +# 0100 01ff ffft tttt ssss sddd dd01 0010 +:movz.S fd, fs, RTsrc is $(AMODE) & REL6=0 & prime=17 & fct=18 & fmt1 & fd & fs & RTsrc & format=0x10 { + if (RTsrc != 0) goto ; + fd[0,32] = fs:4; + +} +:movz.D fd, fs, RTsrc is $(AMODE) & REL6=0 & prime=17 & fct=18 & fmt1 & fd & fs & RTsrc & format=0x11 & fdD & fsD { + if (RTsrc != 0) goto ; + fdD = fsD; + +} +:movz.PS fd, fs, RTsrc is $(AMODE) & REL6=0 & prime=17 & fct=18 & fmt1 & fd & fs & RTsrc & format=0x16 & fsD & fdD { + fdD = mipsFloatPS(RTsrc, fsD); +} + +#### +# +# Release 6 semantics +# +#### +:bc1eqz ft,Rel16 is $(AMODE) & REL6=1 & prime=0x11 & format=0x09 & Rel16 & ft { + # Branch if FPR ft LSB equals 0 (false) (This insn replaces bc1f) + tmp:1 = ft[0,8] & 0x01; # Only need to check the LSB + delayslot(1); + if (tmp == 0x00) goto Rel16; +} + +:bc1nez ft,Rel16 is $(AMODE) & REL6=1 & prime=0x11 & format=0x0d & Rel16 & ft & ftD { + # Branch if FPR ft LSB equals 1 (true) (This insn replaces bc1t) + tmp:1 = ft[0,8] & 0x01; # Only need to check the LSB + delayslot(1); + if (tmp == 0x01) goto Rel16; +} + +:class.S fd,fs is $(AMODE) & REL6=1 & prime=0x11 & format=0x10 & op=0x00 & fct=0x1b & fd & fs { + # Set fd to the 10-bit mask that is the IEEE floating point class of the value in fs + # Bit 0: signaling SNaN + # Bit 1: quiet QNaN + # Bit 2: negative infinity + + # Bit 3: negative normalized number + # Bit 4: negative subnormal, ie denormalized + # Bit 5: negative zero + # Bit 6: positive infinity + # Bit 7: positive normal + # Bit 8: positive subnormal + # Bit 9: positive zero + # Bits 31-10 are set to 0 + + tmp_fs:4 = fs:4; # Get just the 4 byte single floating point value + tmp_exponent:4 = zext(tmp_fs[23,8]); + tmp_fraction:4 = zext(tmp_fs[0,23]); + tmp_sign:4 = zext(tmp_fs[31,1]); + tmp_b1:4 = zext(tmp_fs[22,1]); # High order bit of fraction, used for NaN + + tmp_SNaN:4 = zext((tmp_exponent == 0x0ff) && (tmp_fraction != 0x0) && (tmp_b1 == 0x0)); + tmp_QNaN:4 = zext((tmp_exponent == 0x0ff) && (tmp_fraction != 0x0) && (tmp_b1 == 0x01)); + tmp_Neg_Infinity:4 = zext((tmp_sign == 0x01) && (tmp_exponent == 0x0ff) && (tmp_fraction == 0x0)); + tmp_Neg_Normal:4 = zext((tmp_sign == 0x01) && (tmp_exponent != 0x0) && (tmp_exponent != 0x0ff)); + tmp_Neg_Subnormal:4 = zext((tmp_sign == 0x01) && (tmp_exponent == 0x0) && (tmp_fraction != 0x0)); + tmp_Neg_Zero:4 = zext((tmp_sign == 0x01) && (tmp_exponent == 0x0) && (tmp_fraction == 0x0)); + tmp_Pos_Infinity:4 = zext((tmp_sign == 0x0) && (tmp_exponent == 0x0ff) && (tmp_fraction == 0x0)); + tmp_Pos_Normal:4 = zext((tmp_sign == 0x0) && (tmp_exponent != 0x0) && (tmp_exponent != 0x0ff)); + tmp_Pos_Subnormal:4 = zext((tmp_sign == 0x0) && (tmp_exponent == 0x0) && (tmp_fraction != 0x0)); + tmp_Pos_Zero:4 = zext((tmp_sign == 0x0) && (tmp_exponent == 0x0) && (tmp_fraction == 0x0)); + + tmp_fd:4 = 0; + tmp_fd = tmp_SNaN | (tmp_QNaN << 1) | (tmp_Neg_Infinity << 2) | (tmp_Neg_Normal << 3) | + (tmp_Neg_Subnormal << 4) | (tmp_Neg_Zero << 5) | (tmp_Pos_Infinity << 6) | + (tmp_Pos_Normal << 7) | (tmp_Pos_Subnormal << 8) | (tmp_Pos_Zero << 9); + + fd = zext(tmp_fd); +} + +:class.D fd,fs is $(AMODE) & REL6=1 & prime=0x11 & format=0x11 & op=0x00 & fct=0x1b & fd & fs & fdD & fsD { + # Set fd to the 10-bit mask that is the IEEE floating point class of the value in fs + # Bit 0: signaling SNaN + # Bit 1: quiet QNaN + # Bit 2: negative infinity + # Bit 3: negative normalized number + # Bit 4: negative subnormal, ie denormalized + # Bit 5: negative zero + # Bit 6: positive infinity + # Bit 7: positive normal + # Bit 8: positive subnormal + # Bit 9: positive zero + # Bits 31-10 are set to 0 + + tmp_fs:8 = fsD; + tmp_sign:4 = zext(tmp_fs[63,1]); + tmp_exponent:4 = zext(tmp_fs[52,11]); + tmp_fraction:8 = zext(tmp_fs[0,51]); + tmp_b1:4 = zext(tmp_fs[51,1]); # High order bit of fraction, used for NaN + + tmp_SNaN:4 = zext((tmp_exponent == 0x07ff) && (tmp_fraction != 0x0) && (tmp_b1 == 0x0)); + tmp_QNaN:4 = zext((tmp_exponent == 0x07ff) && (tmp_fraction != 0x0) && (tmp_b1 == 0x01)); + tmp_Neg_Infinity:4 = zext((tmp_sign == 0x01) && (tmp_exponent == 0x07ff) && (tmp_fraction == 0x0)); + tmp_Neg_Normal:4 = zext((tmp_sign == 0x01) && (tmp_exponent != 0x0) && (tmp_exponent != 0x07ff)); + tmp_Neg_Subnormal:4 = zext((tmp_sign == 0x01) && (tmp_exponent == 0x0) && (tmp_fraction != 0x0)); + tmp_Neg_Zero:4 = zext((tmp_sign == 0x01) && (tmp_exponent == 0x0) && (tmp_fraction == 0x0)); + tmp_Pos_Infinity:4 = zext((tmp_sign == 0x0) && (tmp_exponent == 0x07ff) && (tmp_fraction == 0x0)); + tmp_Pos_Normal:4 = zext((tmp_sign == 0x0) && (tmp_exponent != 0x0) && (tmp_exponent != 0x07ff)); + tmp_Pos_Subnormal:4 = zext((tmp_sign == 0x0) && (tmp_exponent == 0x0) && (tmp_fraction != 0x0)); + tmp_Pos_Zero:4 = zext((tmp_sign == 0x0) && (tmp_exponent == 0x0) && (tmp_fraction == 0x0)); + + tmp_fd:4 = 0; + tmp_fd = tmp_SNaN | (tmp_QNaN << 1) | (tmp_Neg_Infinity << 2) | (tmp_Neg_Normal << 3) | + (tmp_Neg_Subnormal << 4) | (tmp_Neg_Zero << 5) | (tmp_Pos_Infinity << 6) | + (tmp_Pos_Normal << 7) | (tmp_Pos_Subnormal << 8) | (tmp_Pos_Zero << 9); + + fdD = zext(tmp_fd); +} + +:sel.S fd,fs,ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x10 & fct=0x10 & fd & fs & ft { + # Floating point select, if LSB of fd == 1 then fd = ft, else fd = fs + # Note that the data in the FPRs might be 32-bit ints, ie there's no interpretation of the values + tmp:1 = (fd[0,1] == 0x01); + fd = (zext(tmp) * ft) | (zext(tmp == 0x0) * fs); +} +:sel.D fd,fs,ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x11 & fct=0x10 & fd & fs & ft & fdD & fsD & ftD { + # Floating point select, if LSB of fd == 1 then fd = ft, else fd = fs + # Note that the data in the FPRs might be 64-bit ints, ie there's no interpretation of the values + tmp:1 = (fdD[0,1] == 0x01); + fdD = (zext(tmp) * ftD) | (zext(tmp == 0x0) * fsD); +} + +# +# The R6 floating point compare cmp instruction is described on page 146 of the +# MIPS64 Architecture Volume II ISA manual +# +# Note that when the condition is true the target FPR is set to all ones, and to 0 if false. +# If the target is 32-bit and you have 64-bit FPRs, then setting the top word is optional +# +# Note that when the format is Single and you have 64-bit FPRS, +# then you need to first pull out the 32-bit float word and then pass that to the correct p-code +# +# TBD: Note that when fct bits 5 and 4 (left most 2 bits) are 01 then the condition is negated +# + +:cmp.af.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x00 & bit5=0 & fmt6 & format=0x14 & fd & fs & ft { + trapIfSNaN(fs:4, ft:4); # Trap if either operand is a Signaling NaN + fd = 0x0; # Always false +} +:cmp.af.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x00 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & ft & fsD & ftD { + trapIfSNaN(fsD, ftD); + fdD = 0x0; +} + +:cmp.un.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x01 & bit5=0 & fmt6 & format=0x14 & fd & fs & ft { + trapIfSNaN(fs:4, ft:4); + fd[0,32] = sext((nan(fs:4) || nan(ft:4)) * 0xff); # True if operands are NaN +} +:cmp.un.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x01 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD { + trapIfSNaN(fsD, ftD); + fdD = sext((nan(fsD) || nan(ftD)) * 0xff); +} + +:cmp.or.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x11 & bit5=0 & fmt6 & format=0x14 & fd & fs & ft { + trapIfSNaN(fs:4, ft:4); + fd[0,32] = sext( (!(nan(fs:4) || nan(ft:4))) * 0xff); # The negated predicate of "c.un" +} +:cmp.or.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x11 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD { + trapIfSNaN(fsD, ftD); + fdD = sext( (!(nan(fsD) || nan(ftD))) * 0xff); +} + +:cmp.eq.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x02 & bit5=0 & fmt6 & format=0x14 & fd & fs & ft { + trapIfSNaN(fs:4, ft:4); + fd[0,32] = sext((fs:4 f== ft:4) * 0xff); +} +:cmp.eq.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x02 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD { + trapIfSNaN(fsD, ftD); + fdD = sext((fsD f== ftD) * 0xff); +} + +:cmp.une.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x12 & bit5=0 & fmt6 & format=0x14 & fd & fs & ft { + # The negated predicate of cmp.eq + trapIfSNaN(fs:4, ft:4); + fd[0,32] = sext((fs:4 f!= ft:4) * 0xff); +} +:cmp.une.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x12 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD { + trapIfSNaN(fsD, ftD); + fdD = sext((fsD f!= ftD) * 0xff); +} + +:cmp.ueq.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x03 & bit5=0 & fmt6 & format=0x14 & fd & fs & ft { + # NaN or equal + trapIfSNaN(fs:4, ft:4); + fd[0,32] = sext( ( nan(fs:4) || nan(ft:4) || (fs:4 f== ft:4) ) * 0xff); +} +:cmp.ueq.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x03 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD { + trapIfSNaN(fsD, ftD); + fdD = sext( ( nan(fsD) || nan(ftD) || (fsD f== ftD) ) * 0xff); +} + +:cmp.ne.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x13 & bit5=0 & fmt6 & format=0x14 & fd & fs & ft { + # The negated predicate of cmp.ueq + trapIfSNaN(fs:4, ft:4); + fd[0,32] = sext( (!( ( nan(fs:4) || nan(ft:4) || (fs:4 f== ft:4) ))) * 0xff); +} +:cmp.ne.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x13 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD { + trapIfSNaN(fsD, ftD); + fdD = sext( (!( ( nan(fsD) || nan(ftD) || (fsD f== ftD) ))) * 0xff); +} + +:cmp.lt.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x04 & bit5=0 & fmt6 & format=0x14 & fd & fs & ft { + trapIfSNaN(fs:4, ft:4); + fd[0,32] = sext((fs:4 f< ft:4) * 0xff); +} +:cmp.lt.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x04 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD { + trapIfSNaN(fsD, ftD); + fdD = sext((fsD f< ftD) * 0xff); +} + +:cmp.ult.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x05 & bit5=0 & fmt6 & format=0x14 & fd & fs & ft { + # NaN or less than + trapIfSNaN(fs:4, ft:4); + fd[0,32] = sext( ( nan(fs:4) || nan(ft:4) || (fs:4 f< ft:4) ) * 0xff); +} +:cmp.ult.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x05 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD { + trapIfSNaN(fsD, ftD); + fdD = sext( ( nan(fsD) || nan(ftD) || (fsD f< ftD) ) * 0xff); +} + +:cmp.le.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x06 & bit5=0 & fmt6 & format=0x14 & fd & fs & ft { + # Less than or equal + trapIfSNaN(fs:4, ft:4); + fd[0,32] = sext((fs:4 f<= ft:4) * 0xff); +} +:cmp.le.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x06 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD { + trapIfSNaN(fsD, ftD); + fdD = sext((fsD f<= ftD) * 0xff); +} + +:cmp.ule.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x07 & bit5=0 & fmt6 & format=0x14 & fd & fs & ft { + # NaN or less than or equal + trapIfSNaN(fs:4, ft:4); + fd[0,32] = sext( ( nan(fs:4) || nan(ft:4) || (fs:4 f<= ft:4) ) * 0xff); +} +:cmp.ule.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x07 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD { + trapIfSNaN(fsD, ftD); + fdD = sext( ( nan(fsD) || nan(ftD) || (fsD f<= ftD) ) * 0xff); +} + +# The cmp instructions that signal (ie trap) if either of the operands are NaN + +:cmp.saf.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x08 & bit5=0 & fmt6 & format=0x14 & fd & fs & ft { + trapIfNaN(fs:4, ft:4); + fd = 0x0; # Always false +} +:cmp.saf.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x08 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD { + trapIfNaN(fsD, ftD); + fdD = 0x0; +} + +:cmp.sun.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x09 & bit5=0 & fmt6 & format=0x14 & fd & fdD & fs & fsD & ft & ftD { + trapIfNaN(fs:4, ft:4); + fd[0,32] = sext((nan(fs:4) || nan(ft:4)) * 0xff); +} +:cmp.sun.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x09 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD { + trapIfNaN(fsD, ftD); + fdD = sext((nan(fsD) || nan(ftD)) * 0xff); +} + +:cmp.sor.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x19 & bit5=0 & fmt6 & format=0x14 & fd & fdD & fs & fsD & ft & ftD { + trapIfNaN(fs:4, ft:4); + fd[0,32] = sext( (!(nan(fs:4) || nan(ft:4))) * 0xff); # negate of cmp.sun +} +:cmp.sor.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x19 & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD { + trapIfNaN(fsD, ftD); + fdD = sext( (!(nan(fsD) || nan(ftD))) * 0xff); +} + +:cmp.seq.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x0a & bit5=0 & fmt6 & format=0x14 & fd & fs & ft { + trapIfNaN(fs:4, ft:4); + fd[0,32] = sext((fs:4 f== ft:4) * 0xff); +} +:cmp.seq.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x0a & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD { + trapIfNaN(fsD, ftD); + fdD = sext((fsD f== ftD) * 0xff); +} + +:cmp.sune.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x1a & bit5=0 & fmt6 & format=0x14 & fd & fs & ft { + trapIfNaN(fs:4, ft:4); + fd[0,32] = sext((fs:4 f!= ft:4) * 0xff); +} +:cmp.sune.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x1a & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD { + trapIfNaN(fsD, ftD); + fdD = sext((fsD f!= ftD) * 0xff); +} + +:cmp.sueq.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x0b & bit5=0 & fmt6 & format=0x14 & fd & fs & ft { + # NaN or equal + trapIfNaN(fs:4, ft:4); + fd[0,32] = sext( ( nan(fs:4) || nan(ft:4) || (fs:4 f== ft:4) ) * 0xff); +} +:cmp.sueq.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x0b & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD { + trapIfNaN(fsD, ftD); + fdD = sext( ( nan(fsD) || nan(ftD) || (fsD f== ftD) ) * 0xff); +} + +:cmp.sne.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x1b & bit5=0 & fmt6 & format=0x14 & fd & fs & ft { + trapIfNaN(fs:4, ft:4); # negate of cmp.sueq + fd[0,32] = sext( (! ( nan(fs:4) || nan(ft:4) || (fs:4 f== ft:4) )) * 0xff); +} +:cmp.sne.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x1b & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD { + trapIfNaN(fsD, ftD); + fdD = sext( (! ( nan(fsD) || nan(ftD) || (fsD f== ftD) )) * 0xff); +} + +:cmp.slt.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x0c & bit5=0 & fmt6 & format=0x14 & fd & fs & ft { + trapIfNaN(fs:4, ft:4); + fd[0,32] = sext( (fs:4 f< ft:4) * 0xff); +} +:cmp.slt.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x0c & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD { + trapIfNaN(fsD, ftD); + fdD = sext( (fsD f< ftD) * 0xff); +} + +:cmp.sult.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x0d & bit5=0 & fmt6 & format=0x14 & fd & fs & ft { + trapIfNaN(fs:4, ft:4); + fd[0,32] = sext( ( nan(fs:4) || nan(ft:4) || (fs:4 f< ft:4) ) * 0xff); +} +:cmp.sult.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x0d & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD { + trapIfNaN(fsD, ftD); + fdD = sext( ( nan(fsD) || nan(ftD) || (fsD f< ftD) ) * 0xff); +} + +:cmp.sle.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x0e & bit5=0 & fmt6 & format=0x14 & fd & fs & ft { + trapIfNaN(fs:4, ft:4); + fd[0,32] = sext( (fs:4 f<= ft:4) * 0xff); +} +:cmp.sle.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x0e & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD { + trapIfNaN(fsD, ftD); + fdD = sext( (fsD f<= ftD) * 0xff); +} + +:cmp.sule.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x0f & bit5=0 & fmt6 & format=0x14 & fd & fs & ft { + trapIfNaN(fs:4, ft:4); + fd[0,32] = sext( ( nan(fs:4) || nan(ft:4) || (fs:4 f<= ft:4) ) * 0xff); +} +:cmp.sule.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & fct=0x0f & bit5=0 & fmt6 & format=0x15 & fd & fdD & fs & fsD & ft & ftD { + trapIfNaN(fsD, ftD); + fdD = sext( ( nan(fsD) || nan(ftD) || (fsD f<= ftD) ) * 0xff); +} + +:rint.S fd, fs is $(AMODE) & REL6=1 & prime=0x11 & format=0x10 & cop1code=0x0 & fs & fd & fct=0x1a { + # floating point round to integral floating point + rm_tmp:1 = fcsr[0,2]; # Get RM rounding mode bits + fs_tmp:4 = fs:4; + if (rm_tmp == 0) goto ; + fd[0,32] = floor(fs_tmp); # RM is 1, no rounding, and floor returns a float + goto ; + + fd[0,32] = round(fs_tmp); # round returns a float + +} + +:rint.D fd, fs is $(AMODE) & REL6=1 & prime=0x11 & format=0x11 & cop1code=0x0 & fs & fd & fsD & fdD & fct=0x1a { + # floating point round to integral floating point + rm_tmp:1 = fcsr[0,2]; # Get RM rounding mode bits + if (rm_tmp == 0) goto ; + fdD = floor(fsD); # RM is 1, no rounding, and floor returns a float + goto ; + + fdD = round(fsD); # round returns a float + +} + +:min.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x10 & cop1code=0x0 & fs & fd & ft & fct=0x1c { + # set floating point fd to the min of fs and ft, TBD special case for NaN + tmp_cond:1 = fs:4 f< ft:4; + fd[0,32] = (fs:4 * zext(tmp_cond == 1)) | (ft:4 * zext(tmp_cond == 0) ); +} +:min.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x11 & cop1code=0x0 & fs & fd & ft & fct=0x1c + & fsD & fdD & ftD { + tmp_cond:1 = fsD f< ftD; + fdD = zext( (fsD * zext(tmp_cond == 1)) | (ftD * zext(tmp_cond == 0) ) ); +} + +:max.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x10 & cop1code=0x0 & fs & fd & ft & fct=0x1d { + # set floating point fd to the max of fs and ft, TBD special case for NaN + tmp_cond:1 = fs:4 f> ft:4; + fd[0,32] = (fs:4 * zext(tmp_cond == 1)) | (ft:4 * zext(tmp_cond == 0) ); +} +:max.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x11 & cop1code=0x0 & fs & fd & ft & fct=0x1d + & fsD & fdD & ftD { + tmp_cond:1 = fsD f> ftD; + fdD = zext( (fsD * zext(tmp_cond == 1)) | (ftD * zext(tmp_cond == 0) ) ); +} + +:mina.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x10 & cop1code=0x0 & fs & fd & ft & fct=0x1e { + # set floating point fd to the min of absolute values of fs and ft, TBD special case for NaN + tmp_cond:1 = abs(fs:4) f< abs(ft:4); + fd[0,32] = (fs:4 * zext(tmp_cond == 1)) | (ft:4 * zext(tmp_cond == 0) ); +} +:mina.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x11 & cop1code=0x0 & fs & fd & ft & fct=0x1e + & fsD & fdD & ftD { + tmp_cond:1 = abs(fsD) f< abs(ftD); + fdD = zext( (fsD * zext(tmp_cond == 1)) | (ftD * zext(tmp_cond == 0) ) ); +} + +:maxa.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x10 & cop1code=0x0 & fs & fd & ft & fct=0x1f { + # set floating point fd to the max of absolute values of fs and ft, TBD special case for NaN + tmp_cond:1 = abs(fs:4) f> abs(ft:4); + fd[0,32] = (fs:4 * zext(tmp_cond == 1)) | (ft:4 * zext(tmp_cond == 0) ); +} +:maxa.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x11 & cop1code=0x0 & fs & fd & ft & fct=0x1f + & fsD & fdD & ftD { + tmp_cond:1 = abs(fsD) f> abs(ftD); + fdD = zext( (fsD * zext(tmp_cond == 1)) | (ftD * zext(tmp_cond == 0) ) ); +} + +:maddf.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x10 & cop1code=0x0 & fs & fd & ft & fct=0x18 { + # set floating point fd = fd + fs * ft, using 32-bit floating values + fd[0,32] = fd:4 f+ (fs:4 f* ft:4); +} +:maddf.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x11 & cop1code=0x0 & fs & fd & ft & fct=0x18 + & fsD & fdD & ftD { + fdD = fdD f+ (fsD f* ftD); +} + +:msubf.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x10 & cop1code=0x0 & fs & fd & ft & fct=0x19 { + # set floating point fd = fd - fs * ft, using 32-bit floating values + fd[0,32] = fd:4 f- (fs:4 f* ft:4); +} +:msubf.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x11 & cop1code=0x0 & fs & fd & ft & fct=0x19 + & fsD & fdD & ftD { + fdD = fdD f- (fsD f* ftD); +} + +:seleqz.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x10 & cop1code=0x0 & fs & fd & ft & fct=0x14 { + # Set floating point register fd to fs if ft[0] == 0, else if == 1 then set fd to 0, TBD special case for NaN + # Note that the description of these select instructions in the MIPS manual does not properly use the C conditional operator + fd = zext(fs * zext(ft[0,1] == 0)); +} +:seleqz.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x11 & cop1code=0x0 & fs & fd & ft & fct=0x14 + & fsD & fdD & ftD { + fdD = zext(fsD * zext(ftD[0,1] == 0)); +} + +:selnez.S fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x10 & cop1code=0x0 & fs & fd & ft & fct=0x17 { + # set floating point register fd to fs if ft[0] == 1, else if == 0 then set fd to 0, TBD special case for NaN + fd = zext(fs * zext(ft[0,1] == 1)); +} +:selnez.D fd, fs, ft is $(AMODE) & REL6=1 & prime=0x11 & format=0x11 & cop1code=0x0 & fs & fd & ft & fct=0x17 + & fsD & fdD & ftD { + fdD = zext(fsD * zext(ftD[0,1] == 1)); +} diff --git a/python/icicle/Ghidra/Processors/MIPS/data/languages/mipsmicro.sinc b/python/icicle/Ghidra/Processors/MIPS/data/languages/mipsmicro.sinc new file mode 100644 index 0000000..f9fc0d9 --- /dev/null +++ b/python/icicle/Ghidra/Processors/MIPS/data/languages/mipsmicro.sinc @@ -0,0 +1,3883 @@ +define token micinstr (16) + mic_op=(10,15) + mic_code=(0,9) + mic_code4=(0,3) + mic_code4s=(0,3) signed + mic_code4r6=(6,9) + mic_off4r6=(4,7) + + mic_base0=(0,4) + mic_base4=(4,6) + mic_index=(5,9) + + mic_rd7=(7,9) + mic_rd7lo=(7,9) + mic_rd1=(1,3) + mic_rd1lo=(7,9) + + mic_rs0=(0,2) + mic_rs0lo=(0,2) + mic_rs1=(1,3) + mic_rs1lo=(1,3) + mic_rs4=(4,6) + mic_rs4lo=(4,6) + mic_rs7=(7,9) + mic_rs7lo=(7,9) + + mic_rt3=(3,5) + mic_rt3lo=(3,5) + mic_rt4=(4,6) + mic_rt4lo=(4,6) + mic_rt7=(7,9) + mic_rt7lo=(7,9) + + + + mic_rd32_5=(5,9) + mic_rd32_5lo=(5,9) + mic_rd32_11=(11,15) + mic_rd32_0=(0,4) + + mic_rs32_0=(0,4) + mic_rs32_0a=(0,4) + mic_rs32_0b=(0,4) + mic_rs32_0lo=(0,4) + mic_rs32_hw=(0,4) + mic_rs32_5=(5,9) + + mic_rt32_0=(0,4) + mic_rt32_5=(5,9) + mic_rt32_5a=(5,9) + mic_rt32_5lo=(5,9) + + mic_fd=(0,4) + mic_fdD=(0,4) + mic_fs=(0,4) + mic_fsD=(0,4) + mic_fs_5=(5,9) + mic_fsD_5=(5,9) + mic_ft_0=(0,4) + mic_ft_5=(5,9) + mic_ftD_5=(5,9) + mic_ct=(0,4) + + mic_stype=(0,4) + mic_funci=(5,9) + mic_cop5=(5,9) + mic_impl=(0,4) + mic_pcf=(0,4) + mic_pcz=(3,4) + mic_cc=(2,4) + mic_pcf2=(2,4) + mic_cp2z=(0,1) + mic_rlist=(5,9) + mic_imm10=(0,9) + mic_imm9=(1,9) + mic_imm9s=(1,9) signed + mic_imm9e=(0,8) + mic_imm7=(0,6) + mic_imm6=(1,6) + mic_imm6r6=(0,5) + mic_imm5=(0,4) + mic_imm5s=(0,4) signed + mic_imm5r6=(5,9) + mic_imm4=(1,4) + mic_imm4s=(1,4) signed + mic_imm3=(1,3) + mic_imm03=(0,3) + mic_imm02=(0,2) + mic_imm01=(0,1) + mic_bit0=(0,0) + mic_bit01=(0,1) + mic_bit3=(3,3) + mic_bit10=(10,10) + mic_sub2=(5,9) + mic_csub=(6,9) + mic_csubr6=(0,3) + mic_jalr=(5,9) + mic_jalrr6=(0,4) + mic_off12=(0,11) + mic_off10=(0,9) + mic_soff10=(0,9) signed + mic_off7=(0,6) + mic_soff7=(0,6) signed + mic_off4=(0,3) + mic_break=(4,9) + mic_breakr6=(0,5) + mic_ja32=(6,15) + mic_list=(4,5) + mic_listr6=(8,9) + mic_cofun=(3,15) + mic_encrs=(1,3) + mic_encrt=(4,6) + mic_encrd=(7,9) + mic_encre=(7,9) + mic_encrt2=(7,9) + mic_sa=(1,3) +; + +define token micinstrb (16) + micb_imm16=(0,15) + micb_simm16=(0,15) signed + micb_poolax=(0,5) + micb_poolfx=(0,5) + micb_bp=(9,10) + micb_bp8=(8,10) + micb_flt6=(6,12) + micb_fmt14=(14,14) + micb_fmt=(13,14) + micb_fmt8=(8,9) + micb_fmt9=(9,10) + micb_fmt10=(10,11) + micb_spec=(0,5) + micb_axf=(6,15) + micb_axf2=(0,9) + micb_axf3=(6,11) + micb_code10=(6,15) + micb_asel=(6,8) + micb_fxf=(6,15) + micb_fxf2=(0,10) + micb_fxf3=(0,7) + micb_fxf4=(6,13) + micb_fxf5=(0,8) + micb_bit10=(10,10) + micb_bit11=(11,11) + micb_bit12=(12,12) + micb_bit15=(15,15) + micb_cc=(13,15) + + micb_rd32=(11,15) + micb_rd32lo=(11,15) + micb_rs32=(6,10) + + micb_fd=(11,15) + micb_fdD=(11,15) + + micb_fr=(6,10) + micb_frD=(6,10) + + micb_rx=(6,10) + micb_pos=(6,10) + micb_size=(11,15) + micb_sa=(11,15) + micb_sa9=(9,10) + micb_hint=(11,15) + micb_offset12=(0,11) + micb_offset12s=(0,11) signed + micb_offset11=(0,10) + micb_offset11s=(0,10) signed + micb_offset9=(0,8) + micb_offset9s=(0,8) signed + micb_func12=(12,15) + micb_trap=(6,11) + micb_cond=(6,9) + micb_cond2=(6,10) + micb_sub9=(9,11) + micb_cop=(0,2) + micb_cofun=(3,15) + micb_z14=(14,15) + micb_z12=(12,15) + micb_z11=(11,12) + micb_z9=(9,10) + micb_z68=(6,8) + micb_z67=(6,7) + micb_sel=(11,13) + micb_cpf=(6,10) +; + +attach variables [ mic_rd7 mic_rd1 mic_rt4 mic_rs1 mic_rs7 mic_rs0 mic_rs4 mic_rt3 mic_rt7 mic_base4 ] + [ s0 s1 v0 v1 a0 a1 a2 a3 ]; + +attach variables [ mic_rs32_hw ] [ + HW_CPUNUM HW_SYNCI_STEP HW_CC HW_CCRe + HW_PerfCtr HW_XNP HW_RES6 HW_RES7 + HW_RES8 HW_RES9 HW_RES10 HW_RES11 + HW_RES12 HW_RES13 HW_RES14 HW_RES15 + HW_RES16 HW_RES17 HW_RES18 HW_RES19 + HW_RES20 HW_RES21 HW_RES22 HW_RES23 + HW_RES24 HW_RES25 HW_RES26 HW_RES27 + HW_RES28 HW_ULR HW_RESIM30 HW_RESIM31 +]; + +@ifdef MIPS64 +attach variables [ mic_rd7lo mic_rd1lo mic_rt4lo mic_rs1lo mic_rs7lo mic_rs0lo mic_rs4lo mic_rt3lo mic_rt7lo ] + [ s0_lo s1_lo v0_lo v1_lo a0_lo a1_lo a2_lo a3_lo ]; + +attach variables [ mic_rs32_0lo mic_rt32_5lo micb_rd32lo mic_rd32_5lo ext_32_rs1lo] [ + zero_lo at_lo v0_lo v1_lo a0_lo a1_lo a2_lo a3_lo + t0_lo t1_lo t2_lo t3_lo t4_lo t5_lo t6_lo t7_lo + s0_lo s1_lo s2_lo s3_lo s4_lo s5_lo s6_lo s7_lo + t8_lo t9_lo k0_lo k1_lo gp_lo sp_lo s8_lo ra_lo +]; +@else +attach variables [ mic_rd7lo mic_rd1lo mic_rt4lo mic_rs1lo mic_rs7lo mic_rs0lo mic_rs4lo mic_rt3lo mic_rt7lo ] + [ s0 s1 v0 v1 a0 a1 a2 a3 ]; + +attach variables [ mic_rs32_0lo mic_rt32_5lo micb_rd32lo mic_rd32_5lo ext_32_rs1lo] [ + zero at v0 v1 a0 a1 a2 a3 + t0 t1 t2 t3 t4 t5 t6 t7 + s0 s1 s2 s3 s4 s5 s6 s7 + t8 t9 k0 k1 gp sp s8 ra +]; +@endif + + +attach variables [ mic_encrs mic_encrt ext_16_rs] + [ zero s1 v0 v1 s0 s2 s3 s4 ]; + +attach variables [ mic_encrt2] + [ zero s1 v0 v1 a0 a1 a2 a3 ]; + +attach variables [ mic_encrd] + [ a1 a1 a2 a0 a0 a0 a0 a0 ]; + +attach variables [ mic_encre] + [ a2 a3 a3 s5 s6 a1 a2 a3 ]; + +attach variables [ mic_rd32_5 mic_rs32_0 mic_rs32_5 mic_rt32_5 mic_rd32_11 mic_rd32_0 ext_32_base micb_rd32 ext_32_rd micb_rs32 mic_base0 ext_32_rs1 mic_index] [ + zero at v0 v1 a0 a1 a2 a3 + t0 t1 t2 t3 t4 t5 t6 t7 + s0 s1 s2 s3 s4 s5 s6 s7 + t8 t9 k0 k1 gp sp s8 ra +]; + +attach variables [ mic_fs mic_ft_5 micb_fd micb_fr mic_fs_5 mic_fd] [ + f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 + f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 +]; + +@if FREGSIZE == "4" +# For 64-bit floating point Double instruction operands need to bond two 32-bit FPRs +attach variables [ mic_fsD mic_ftD_5 micb_fdD micb_frD mic_fsD_5 mic_fdD] [ + f0_1 _ f2_3 _ f4_5 _ f6_7 _ + f8_9 _ f10_11 _ f12_13 _ f14_15 _ + f16_17 _ f18_19 _ f20_21 _ f22_23 _ + f24_25 _ f26_27 _ f28_29 _ f30_31 _ +]; +@else # FREGSIZE == "8" +attach variables [ mic_fsD mic_ftD_5 micb_fdD micb_frD mic_fsD_5 mic_fdD] [ + f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 + f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 +]; +@endif + +attach names [ ext_t4_name][ + _ "s0" "s0-s1" "s0-s2" + "s0-s3" "s0-s4" "s0-s5" "s0-s6" + "s0-s7" "s0-s8" _ _ + _ _ _ _ +]; + +RD5L: mic_rd32_5 is mic_rd32_5 & mic_rd32_5lo { export mic_rd32_5lo; } +RD5L: mic_rd32_5 is mic_rd32_5 & mic_rd32_5lo=0 { tmp:4 = 0; export tmp; } + +RD7R1: mic_rd7 is mic_rd7 & REL6=0 { export mic_rd7; } +RD7R1: mic_rd1 is mic_rd1 & REL6=1 { export mic_rd1; } + +RSEXTL: ext_32_rs1 is ext_32_rs1 & ext_32_rs1lo { export ext_32_rs1lo; } +RSEXTL: ext_32_rs1 is ext_32_rs1 & ext_32_rs1lo=0 { tmp:4 = 0; export tmp; } + +RS0L: mic_rs32_0 is mic_rs32_0 & mic_rs32_0lo { export mic_rs32_0lo; } +RS0L: mic_rs32_0 is mic_rs32_0 & mic_rs32_0lo=0 { tmp:4 = 0; export tmp; } +RS4L: mic_rs4 is mic_rs4 & mic_rs4lo { export mic_rs4lo; } + +RS0R4: mic_rs0 is mic_rs0 & REL6=0 { export mic_rs0; } +RS0R4: mic_rs4 is mic_rs4 & REL6=1 { export mic_rs4; } +RS0R5: mic_rs32_0 is mic_rs32_0 & REL6=0 { export mic_rs32_0; } +RS0R5: mic_rs32_0 is mic_rs32_0 & mic_rs32_0=0 & REL6=0 { tmp:$(REGSIZE) = 0; export tmp; } +RS0R5: mic_rs32_5 is mic_rs32_5 & REL6=1 { export mic_rs32_5; } +RS0R5: mic_rs32_5 is mic_rs32_5 & mic_rs32_5=0 & REL6=1 { tmp:$(REGSIZE) = 0; export tmp; } + +RS1R7L: mic_rs1 is mic_rs1 & mic_rs1lo & REL6=0 { export mic_rs1lo; } +RS1R7L: mic_rs7 is mic_rs7 & mic_rs7lo & REL6=1 { export mic_rs7lo; } + +RT4L: mic_rt4 is mic_rt4 & mic_rt4lo { export mic_rt4lo; } +RT5L: mic_rt32_5 is mic_rt32_5 & mic_rt32_5lo { export mic_rt32_5lo; } +RT5L: mic_rt32_5 is mic_rt32_5 & mic_rt32_5lo=0 { tmp:4 = 0; export tmp; } + + +RT3R7: mic_rt3 is mic_rt3 & REL6=0 { export mic_rt3; } +RT3R7: mic_rt7 is mic_rt7 & REL6=1 { export mic_rt7; } + +RST7R5: mic_rs7 is mic_rs7 & REL6=0 { export mic_rs7; } +RST7R5: mic_rt32_5 is mic_rt32_5 & REL6=1 { export mic_rt32_5; } +RST7R5: mic_rt32_5 is mic_rt32_5 & mic_rt32_5=0 & REL6=1 { tmp:$(REGSIZE) = 0; export tmp; } + + +RT5RD5: ext_32_rd is ext_32_rd & REL6=0 { export ext_32_rd; } +RT5RD5: ext_32_rd is ext_32_rd & ext_32_rd=0 & REL6=0 { tmp:$(REGSIZE) = 0; export tmp; } +RT5RD5: micb_rd32 is micb_rd32 & REL6=1 { export micb_rd32; } +RT5RD5: micb_rd32 is micb_rd32 & micb_rd32=0 & REL6=1 { tmp:$(REGSIZE) = 0; export tmp; } + +RS0RT5: mic_rs32_0 is mic_rs32_0 & REL6=0 { export mic_rs32_0; } +RS0RT5: mic_rs32_0 is mic_rs32_0 & mic_rs32_0=0 & REL6=0 { tmp:$(REGSIZE) = 0; export tmp; } +RS0RT5: mic_rt32_5 is mic_rt32_5 & REL6=1 { export mic_rt32_5; } +RS0RT5: mic_rt32_5 is mic_rt32_5 & mic_rt32_5=0 & REL6=1 { tmp:$(REGSIZE) = 0; export tmp; } + +ENCRS: mic_encrs is mic_encrs & REL6=0 { export mic_encrs; } +ENCRS: mic_encrs is mic_encrs & mic_encrs=0 & REL6=0 { tmp:$(REGSIZE) = 0; export tmp; } +ENCRS: ext_16_rs is ext_16_rs & REL6=1 { export ext_16_rs; } +ENCRS: ext_16_rs is ext_16_rs & ext_16_rs=0 & REL6=1 { tmp:$(REGSIZE) = 0; export tmp; } + +Abs26_mic1: reloc is ext_32_code & micb_imm16 [ reloc=((inst_start+4) $and 0xfffffffff8000000)+2*(micb_imm16 | (ext_32_code << 16)); ] { export *:$(ADDRSIZE) reloc; } +Abs26_mic2: reloc is ext_32_code & micb_imm16 [ reloc=((inst_start+4) $and 0xfffffffff0000000)+4*(micb_imm16 | (ext_32_code << 16)); ] { export *:$(ADDRSIZE) reloc; } +Rel26_mic: reloc is micb_imm16 [ reloc=inst_start+4+2*((ext_32_codes << 16) | micb_imm16); ] { export *:$(ADDRSIZE) reloc; } +Rel21_mic: reloc is micb_imm16 [ reloc=inst_start+4+2*((ext_32_imm5s << 16) | micb_imm16); ] { export *:$(ADDRSIZE) reloc; } +Rel16_mic: reloc is micb_simm16 [ reloc=inst_start+4+2*micb_simm16; ] { export *:$(ADDRSIZE) reloc; } +Rel10_mic: reloc is mic_soff10 [ reloc=inst_start+2+2*mic_soff10; ] { export *:$(ADDRSIZE) reloc; } +Rel7_mic: reloc is mic_soff7 [ reloc=inst_start+2+2*mic_soff7; ] { export *:$(ADDRSIZE) reloc; } + +EXT_CODE3: val is mic_imm3=0 [ext_off16_s = 0x0001; val = ext_off16_s; ] { export *[const]:2 val; } +EXT_CODE3: val is mic_imm3=7 [ext_off16_s = 0xFFFF; val = ext_off16_s; ] { export *[const]:2 val; } +EXT_CODE3: val is mic_imm3 [ext_off16_s = mic_imm3 << 2; val = ext_off16_s; ] { export *[const]:2 val; } + +EXT_CODE4A: val is mic_imm03=0x0 [ext_off16_u = 0x80; val = ext_off16_u; ] { export *[const]:2 val; } +EXT_CODE4A: val is mic_imm03=0x1 [ext_off16_u = 0x1; val = ext_off16_u; ] { export *[const]:2 val; } +EXT_CODE4A: val is mic_imm03=0x2 [ext_off16_u = 0x2; val = ext_off16_u; ] { export *[const]:2 val; } +EXT_CODE4A: val is mic_imm03=0x3 [ext_off16_u = 0x3; val = ext_off16_u; ] { export *[const]:2 val; } +EXT_CODE4A: val is mic_imm03=0x4 [ext_off16_u = 0x4; val = ext_off16_u; ] { export *[const]:2 val; } +EXT_CODE4A: val is mic_imm03=0x5 [ext_off16_u = 0x7; val = ext_off16_u; ] { export *[const]:2 val; } +EXT_CODE4A: val is mic_imm03=0x6 [ext_off16_u = 0x8; val = ext_off16_u; ] { export *[const]:2 val; } +EXT_CODE4A: val is mic_imm03=0x7 [ext_off16_u = 0xf; val = ext_off16_u; ] { export *[const]:2 val; } +EXT_CODE4A: val is mic_imm03=0x8 [ext_off16_u = 0x10; val = ext_off16_u; ] { export *[const]:2 val; } +EXT_CODE4A: val is mic_imm03=0x9 [ext_off16_u = 0x1f; val = ext_off16_u; ] { export *[const]:2 val; } +EXT_CODE4A: val is mic_imm03=0xa [ext_off16_u = 0x20; val = ext_off16_u; ] { export *[const]:2 val; } +EXT_CODE4A: val is mic_imm03=0xb [ext_off16_u = 0x3f; val = ext_off16_u; ] { export *[const]:2 val; } +EXT_CODE4A: val is mic_imm03=0xc [ext_off16_u = 0x40; val = ext_off16_u; ] { export *[const]:2 val; } +EXT_CODE4A: val is mic_imm03=0xd [ext_off16_u = 0xff; val = ext_off16_u; ] { export *[const]:2 val; } +EXT_CODE4A: val is mic_imm03=0xe [ext_off16_u = 0x8000; val = ext_off16_u; ] { export *[const]:2 val; } +EXT_CODE4A: val is mic_imm03=0xf [ext_off16_u = 0xffff; val = ext_off16_u; ] { export *[const]:2 val; } + +EXT_CODE4B: val is mic_code4=0xf [ ext_off16_s = 0xffff; val = ext_off16_s; ] { export *[const]:2 val; } +EXT_CODE4B: val is mic_code4 [ ext_off16_s = mic_code4; val = ext_off16_s; ] { export *[const]:2 val; } + +EXT_CODE4C: val is mic_code4 [ val = mic_code4 << 1; ] { export *[const]:2 val; } + +EXT_CODE4D: val is mic_code4s [ val = mic_code4s << 2; ] { export *[const]:2 val; } + +EXT_CODE4E: val is mic_code4 & REL6=0 [ val = mic_code4 << 2; ] { export *[const]:2 val; } +EXT_CODE4E: val is mic_off4r6 & REL6=1 [ val = mic_off4r6 << 2; ] { export *[const]:2 val; } +EXT_CODE5R6: val is mic_imm5r6 [ val = mic_imm5r6 << 2; ] { export *[const]:2 val; } + + +EXT_CODE5: val is mic_imm5 [ val = mic_imm5 << 2; ] { export *[const]:2 val; } + +EXT_CODE7: val is mic_imm7=0x7f [ ext_off16_s = 0xffff; val = ext_off16_s; ] { export *[const]:2 val; } +EXT_CODE7: val is mic_imm7 [ ext_off16_s = mic_imm7; val = ext_off16_s; ] { export *[const]:2 val; } + +EXT_CODE7A: val is mic_soff7 [ val = mic_soff7 << 2; ] { export *[const]:2 val; } + +EXT_CODE9: val is mic_imm9=0x000 [ext_off16_s = 0x0100; val = ext_off16_s << 2; ] { export *[const]:2 val; } +EXT_CODE9: val is mic_imm9=0x001 [ext_off16_s = 0x0101; val = ext_off16_s << 2; ] { export *[const]:2 val; } +EXT_CODE9: val is mic_imm9=0x1fe [ext_off16_s = 0xfefe; val = ext_off16_s << 2; ] { export *[const]:2 val; } +EXT_CODE9: val is mic_imm9=0x1ff [ext_off16_s = 0xfeff; val = ext_off16_s << 2; ] { export *[const]:2 val; } +EXT_CODE9: val is mic_imm9s [ val = mic_imm9s << 2; ] { export *[const]:2 val; } + +EXT_CODE9E: val is micb_offset9s [ val = micb_offset9s << 0; ] { export *[const]:2 val; } +EXT_CODE12: val is micb_offset12s [ val = micb_offset12s << 0; ] { export *[const]:2 val; } + +EXT_CODE16: val is micb_code10 [ val = (ext_32_imm6 << 10) | micb_code10; ] { export *[const]:2 val; } + +EXT_MS16: val is micb_simm16 [ val = micb_simm16 << 0; ] { export *[const]:2 val; } +EXT_MS18: val is micb_imm16 [ val = (ext_32_imm2s << 19) | (micb_imm16 << 3); ] { export *[const]:4 val; } + +EXT_MS19: val is micb_imm16 [ val = (ext_32_imm3s << 18) | (micb_imm16 << 2); ] { export *[const]:4 val; } + +EXT_MS32: val is micb_simm16 [ val = micb_simm16 << 16; ] { export *[const]:4 val; } +EXT_MS48: val is micb_simm16 [ val = micb_simm16 << 32; ] { export *[const]:8 val; } +EXT_MS64: val is micb_simm16 [ val = micb_simm16 << 48; ] { export *[const]:8 val; } + +EXT_MSPC: val is ext_32_imm3s & micb_imm16 & REL6=1 [val = (ext_32_imm3s << 18) | (micb_imm16 << 2); ] { export *[const]:4 val; } + +EXT_MSPC: val is ext_32_addims & micb_imm16 & REL6=0 [val = (ext_32_addims << 18) | (micb_imm16 << 2); ] { export *[const]:4 val; } + +EXT_MU23: val is ext_32_code & micb_cofun [val = (ext_32_code << 13) | micb_cofun; ] { export *[const]:4 val; } + +EXT_MU6: val is mic_imm6 [val = mic_imm6 << 2; ] { export *[const]:1 val; } + +EXT_SA: val is mic_sa=0 [ val = 8; ] { export *[const]:1 val; } +EXT_SA: val is mic_sa [ val = mic_sa << 0; ] {export *[const]:1 val; } + +EXT_SA9: val is micb_sa9 [ val = micb_sa9+1; ] { export *[const]:1 val; } + +DIDISP: is mic_rs32_0=0 {} +DIDISP: mic_rs32_0 is mic_rs32_0 {} + +RTIMP: is mic_rt32_5=31 {} +RTIMP: mic_rt32_5", " is mic_rt32_5 {} + +SIZEP: val is micb_size [ val = micb_size+1; ] { export *[const]:1 val; } +SIZEPLG: val is micb_size [ val = micb_size+1+32; ] { export *[const]:1 val; } +SIZEQ: val is micb_size & micb_pos [ val = micb_size + 1 - micb_pos; ] { export *[const]:1 val; } +SIZEQLG: val is micb_size & micb_pos [ val = micb_size + 1 - micb_pos + 32; ] { export *[const]:1 val; } +POSHI: val is micb_pos [ val = micb_pos+32; ] { export *[const]:1 val; } + +CPSEL: is micb_sel=0 {} +CPSEL: ", "micb_sel is micb_sel {} + +STYPE: is mic_stype=0 {} +STYPE: val is mic_stype [ val = mic_stype << 0; ] {} + +SDB16: mic_code4 is mic_code4 & REL6=0 { export *[const]:1 mic_code4; } +SDB16: mic_code4r6 is mic_code4r6 & REL6=1 { export *[const]:1 mic_code4r6; } + +SA32: val is micb_sa [ val = micb_sa+32; ] { export *[const]:1 val; } + +COP2CC: is mic_cc=0 {} +COP2CC: val", " is mic_cc [ val = mic_cc << 0; ] {} + +LOAD_S8: is ext_t4=8 {} +LOAD_S8: is ext_t4 { MemSrcCast(s8,tsp); tsp = tsp+$(REGSIZE); } + +LOAD_S7: is ext_t4=7 {} +LOAD_S7: is LOAD_S8 { MemSrcCast(s7,tsp); tsp = tsp+$(REGSIZE); build LOAD_S8; } + +LOAD_S6: is ext_t4=6 {} +LOAD_S6: is LOAD_S7 { MemSrcCast(s6,tsp); tsp = tsp+$(REGSIZE); build LOAD_S7; } + +LOAD_S5: is ext_t4=5 {} +LOAD_S5: is LOAD_S6 {MemSrcCast(s5,tsp); tsp = tsp+$(REGSIZE); build LOAD_S6; } + +LOAD_S4: is ext_t4=4 {} +LOAD_S4: is LOAD_S5 { MemSrcCast(s4,tsp); tsp = tsp+$(REGSIZE); build LOAD_S5; } + +LOAD_S3: is ext_t4=3 {} +LOAD_S3: is LOAD_S4 { MemSrcCast(s3,tsp); tsp = tsp+$(REGSIZE); build LOAD_S4; } + +LOAD_S2: is ext_t4=2 {} +LOAD_S2: is LOAD_S3 { MemSrcCast(s2,tsp); tsp = tsp+$(REGSIZE); build LOAD_S3; } + +LOAD_S1: is ext_t4=1 {} +LOAD_S1: is LOAD_S2 { MemSrcCast(s1,tsp); tsp = tsp+$(REGSIZE); build LOAD_S2; } + +LOAD_S0: is ext_t4=0 {} +LOAD_S0: is LOAD_S1 { MemSrcCast(s0,tsp); tsp = tsp+$(REGSIZE); build LOAD_S1; } + +LOAD_SREG: is ext_t4=0 {} +LOAD_SREG: ext_t4_name"," is LOAD_S0 & ext_t4_name { build LOAD_S0; } + +LOAD_RA: is ext_tra=0 {} +LOAD_RA: "ra," is ext_tra=1 { MemSrcCast(ra,tsp); tsp = tsp+$(REGSIZE); } + +LOAD_TOP: LOAD_SREG^LOAD_RA EXT_CODE12(ext_32_base) is LOAD_SREG & LOAD_RA & ext_32_base & ext_32_rlist & EXT_CODE12 [ext_t4 = ext_32_rlist $and 0xf; ext_tra = ext_32_rlist >> 4; ] { + build EXT_CODE12; + + tmp:$(REGSIZE) = sext(EXT_CODE12); + tsp = ext_32_base + tmp; + + build LOAD_SREG; + build LOAD_RA; +} +LOAD_TOP16: LOAD_SREG^ra,EXT_CODE4E(sp) is mic_list & REL6=0 & LOAD_SREG & EXT_CODE4E & ra & sp [ext_t4 = mic_list+1;] { + build EXT_CODE4E; + + tmp:$(REGSIZE) = zext(EXT_CODE4E); + tsp = sp + tmp; + + build LOAD_SREG; + MemSrcCast(ra,tsp); +} +LOAD_TOP16: LOAD_SREG^ra,EXT_CODE4E(sp) is mic_listr6 & REL6=1 & LOAD_SREG & EXT_CODE4E & ra & sp [ext_t4 = mic_listr6+1;] { + build EXT_CODE4E; + + tmp:$(REGSIZE) = zext(EXT_CODE4E); + tsp = sp + tmp; + + build LOAD_SREG; + MemSrcCast(ra,tsp); +} + + +STORE_S8: is ext_t4=8 {} +STORE_S8: is ext_t4 { MemDestCast(tsp,s8); tsp = tsp+$(REGSIZE); } + +STORE_S7: is ext_t4=7 {} +STORE_S7: is STORE_S8 { MemDestCast(tsp,s7); tsp = tsp+$(REGSIZE); build STORE_S8; } + +STORE_S6: is ext_t4=6 {} +STORE_S6: is STORE_S7 { MemDestCast(tsp,s6); tsp = tsp+$(REGSIZE); build STORE_S7; } + +STORE_S5: is ext_t4=5 {} +STORE_S5: is STORE_S6 { MemDestCast(tsp,s5); tsp = tsp+$(REGSIZE); build STORE_S6; } + +STORE_S4: is ext_t4=4 {} +STORE_S4: is STORE_S5 { MemDestCast(tsp,s4); tsp = tsp+$(REGSIZE); build STORE_S5; } + +STORE_S3: is ext_t4=3 {} +STORE_S3: is STORE_S4 { MemDestCast(tsp,s3); tsp = tsp+$(REGSIZE); build STORE_S4; } + +STORE_S2: is ext_t4=2 {} +STORE_S2: is STORE_S3 { MemDestCast(tsp,s2); tsp = tsp+$(REGSIZE); build STORE_S3; } + +STORE_S1: is ext_t4=1 {} +STORE_S1: is STORE_S2 { MemDestCast(tsp,s1); tsp = tsp+$(REGSIZE); build STORE_S2; } + +STORE_S0: is ext_t4=0 {} +STORE_S0: is STORE_S1 { MemDestCast(tsp,s0); tsp = tsp+$(REGSIZE); build STORE_S1; } + +STORE_SREG: is ext_t4=0 {} +STORE_SREG: ext_t4_name"," is STORE_S0 & ext_t4_name { build STORE_S0; } + +STORE_RA: is ext_tra=0 {} +STORE_RA: "ra," is ext_tra=1 { MemDestCast(tsp,ra); tsp = tsp+$(REGSIZE); } + +STORE_TOP: STORE_SREG^STORE_RA EXT_CODE12(ext_32_base) is STORE_SREG & STORE_RA & ext_32_base & ext_32_rlist & EXT_CODE12 [ext_t4 = ext_32_rlist $and 0xf; ext_tra = ext_32_rlist >> 4; ] { + build EXT_CODE12; + + tmp:$(REGSIZE) = sext(EXT_CODE12); + tsp = ext_32_base + tmp; + + build STORE_SREG; + build STORE_RA; +} +STORE_TOP16: STORE_SREG^ra,EXT_CODE4E(sp) is mic_list & REL6=0 & STORE_SREG & EXT_CODE4E & ra & sp [ext_t4 = mic_list+1;] { + build EXT_CODE4E; + + tmp:$(REGSIZE) = zext(EXT_CODE4E); + tsp = sp + tmp; + + build STORE_SREG; + MemDestCast(tsp,ra); +} +STORE_TOP16: STORE_SREG^ra,EXT_CODE4E(sp) is mic_listr6 & REL6=1 & STORE_SREG & EXT_CODE4E & ra & sp [ext_t4 = mic_listr6+1;] { + build EXT_CODE4E; + + tmp:$(REGSIZE) = zext(EXT_CODE4E); + tsp = sp + tmp; + + build STORE_SREG; + MemDestCast(tsp,ra); +} + +#### +# +# Common semantics +# +#### + +:abs.S mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_bit15=0 & micb_fmt=0 & micb_poolfx=0b111011 & micb_flt6=0b0001101 { + fs_tmp:4 = mic_fs:4; + fd_tmp:4 = abs(fs_tmp); + mic_ft_5 = zext(fd_tmp); +} + +:abs.D mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5; micb_bit15=0 & micb_fmt=1 & micb_poolfx=0b111011 & micb_flt6=0b0001101 { + mic_ftD_5 = abs(mic_fsD); +} + +:add micb_rd32, RS0L, RT5L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & RT5L ; micb_axf2=0b0100010000 & micb_bit10=0 & micb_rd32 { + tmps:8 = zext(RS0L); + tmpt:8 = zext(RT5L); + tmps = tmps + tmpt; + tmpt = tmps >> 32; + if (tmpt != 0) goto ; + micb_rd32 = sext(tmps:4); + +} + +:add.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_fd & micb_bit10=0 & micb_fmt8=0 & micb_fxf3=0b00110000 { + fd_tmp:4 = mic_fs:4 f+ mic_ft_5:4; + micb_fd = zext(fd_tmp); +} + +:add.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_bit10=0 & micb_fmt8=1 & micb_fxf3=0b00110000 { + micb_fdD = mic_fsD f+ mic_ftD_5; +} + +:addiu mic_rt32_5, RS0L, EXT_MS16 is ISA_MODE=1 & RELP=0 & mic_op=0b001100 & RS0L & mic_rt32_5 ; EXT_MS16 { + tmp:4 = sext(EXT_MS16); + tmp = tmp + RS0L; + mic_rt32_5 = sext(tmp); +} + +:addiupc RST7R5, EXT_MSPC is ISA_MODE=1 & RELP=0 & mic_op=0b011110 & RST7R5 & mic_imm7 & (REL6=0 | (REL6=1 & mic_pcz=0)); EXT_MSPC [ ext_32_addim=mic_imm7; ] { + tmpa:$(REGSIZE) = inst_start & ~3; + tmpb:$(REGSIZE) = sext(EXT_MSPC); + RST7R5 = tmpa + tmpb; +} + +:addiur1sp mic_rd7, EXT_MU6 is ISA_MODE=1 & RELP=0 & mic_op=0b011011 & mic_bit0=1 & mic_rd7 & EXT_MU6 { +@if REGSIZE == "4" + tmp:4 = sp + zext(EXT_MU6); +@else + tmp:4 = sp_lo + zext(EXT_MU6); +@endif + mic_rd7 = sext(tmp); +} + +:addiur2 mic_rd7, RS4L, EXT_CODE3 is ISA_MODE=1 & RELP=0 & mic_op=0b011011 & mic_bit0=0 & RS4L & mic_rd7 & EXT_CODE3 { + tmp:4 = RS4L + sext(EXT_CODE3); + mic_rd7 = sext(tmp); +} + +:addiusp EXT_CODE9 is ISA_MODE=1 & RELP=0 & mic_op=0b010011 & mic_bit0=1 & EXT_CODE9 { +@if REGSIZE == "4" + tmp:4 = sp + sext(EXT_CODE9); +@else + tmp:4 = sp_lo + sext(EXT_CODE9); +@endif + sp = sext(tmp); +} + +:addius5 RD5L, mic_imm4s is ISA_MODE=1 & RELP=0 & mic_op=0b010011 & mic_bit0=0 & mic_rd32_5 & RD5L & mic_imm4s { + tmp:4 = mic_imm4s; + tmp = tmp + RD5L; + mic_rd32_5 = sext(tmp); +} + +:addu micb_rd32, RS0L, RT5L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & RT5L ; micb_axf2=0b0101010000 & micb_bit10=0 & micb_rd32 { + tmp:4 = RS0L + RT5L; + micb_rd32 = sext(tmp); +} + +:addu16 RD7R1, RT4L, RS1R7L is ISA_MODE=1 & RELP=0 & mic_op=0b000001 & mic_bit0=0 & RD7R1 & RT4L & RS1R7L { + tmp:4 = RT4L + RS1R7L; + RD7R1 = sext(tmp); +} + +:and micb_rd32, mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b1001010000 & micb_bit10=0 & micb_rd32 { + micb_rd32 = mic_rs32_0 & mic_rt32_5; +} + +:and16 RT3R7, RS0R4 is ISA_MODE=1 & RELP=0 & mic_op=0b010001 & RT3R7 & RS0R4 & ((mic_csub=0b0010 & REL6=0) | (mic_csubr6=0b0001 & REL6=1)) { + RT3R7 = RT3R7 & RS0R4; +} + +:andi mic_rt32_5, mic_rs32_0, micb_imm16 is ISA_MODE=1 & RELP=0 & mic_op=0b110100 & mic_rs32_0 & mic_rt32_5 ; micb_imm16 { + tmp:$(REGSIZE) = micb_imm16; + mic_rt32_5 = mic_rs32_0 & tmp; +} + +:andi16 mic_rd7, mic_rs4, EXT_CODE4A is ISA_MODE=1 & RELP=0 & mic_op=0b001011 & mic_rd7 & mic_rs4 & EXT_CODE4A { + mic_rd7 = mic_rs4 & zext(EXT_CODE4A); +} + +:break is ISA_MODE=1 & RELP=0 & mic_op=0b000000 ; micb_poolax=0b000111 { + break(); +} + +:break16 is ISA_MODE=1 & RELP=0 & mic_op=0b010001 & SDB16 & ((mic_break=0b101000 & REL6=0) | (mic_breakr6=0b011011 & REL6=1)) { + break(); +} + +:cachee mic_cop5, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_cop5 & mic_base0 ; micb_func12=0b1010 & micb_sub9=0b011 & EXT_CODE9E { + cacheOp(); +} + +:ceil.l.S mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_ftD_5 ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b01001100 { + fd_tmp:4 = ceil(mic_fs:4); + mic_ftD_5 = trunc(fd_tmp); +} + +:ceil.l.D mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b01001100 { + fsD_tmp:8 = ceil(mic_fsD); + mic_ftD_5 = trunc(fsD_tmp); +} + +:ceil.w.S mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b01101100 { + fs_ceil_tmp:4 = ceil(mic_fs:4); + fd_tmp:4 = trunc(fs_ceil_tmp); + mic_ft_5 = zext(fd_tmp); +} + +:ceil.w.D mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b01101100 { + fs_tmp:8 = ceil(mic_fsD); + fd_tmp:4 = trunc(fs_tmp); + mic_ft_5 = zext(fd_tmp); +} + +:cfc1 mic_rt32_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_rt32_5 & mic_fs ; micb_poolfx=0b111011 & micb_fxf=0b0001000000 { + mic_rt32_5 = getCopControlWord( 1:1, mic_fs:4 ); +} + +:cfc2 mic_rt32_5, mic_impl is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_impl ; micb_poolfx=0b111100 & micb_axf=0b1100110100 { + tmpa:1 = 2; + tmpb:1 = mic_impl; + mic_rt32_5 = getCopControlWord(tmpa,tmpb); +} + +:clo mic_rt32_5, RS0L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & RS0L ; micb_poolax=0b111100 & micb_axf=0b0100101100 { + mic_rt32_5 = lzcount( ~RS0L ); +} + +:clz mic_rt32_5, RS0L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & RS0L ; micb_poolax=0b111100 & micb_axf=0b0101101100 { + mic_rt32_5 = lzcount( RS0L ); +} + +:cop2 EXT_MU23 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_code ; micb_cop=0b010 & EXT_MU23 [ ext_32_code=mic_code; ] { + tmp:1 = 2; + copFunction(tmp,EXT_MU23); +} + +:ctc1 RT5L, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & RT5L & mic_fs ; micb_poolfx=0b111011 & micb_fxf=0b0001100000 { + setCopControlWord( 1:1, mic_fs:4, RT5L ); +} + +:ctc2 mic_rt32_5, mic_impl is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_impl ; micb_poolax=0b111100 & micb_axf=0b1101110100 { + tmpa:1 = 2; + tmpb:1 = mic_impl; + setCopControlWord(tmpa,tmpb,mic_rt32_5); +} + +:cvt.d.S mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_ftD_5 ; micb_bit15=0 & micb_fmt=0 & micb_poolfx=0b111011 & micb_flt6=0b1001101 { + fs_tmp:4 = mic_fs:4; + mic_ftD_5 = float2float(fs_tmp); +} + +:cvt.d.W mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_ftD_5 ; micb_bit15=0 & micb_fmt=1 & micb_poolfx=0b111011 & micb_flt6=0b1001101 { + fs_tmp:4 = mic_fs:4; + mic_ftD_5 = int2float(fs_tmp); +} + +:cvt.d.L mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_bit15=0 & micb_fmt=2 & micb_poolfx=0b111011 & micb_flt6=0b1001101 { + mic_ftD_5 = int2float(mic_fsD); +} + +:cvt.l.S mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_ftD_5 ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b00000100 { + rm_tmp:1 = fcsr[0,2]; + fs_tmp:4 = mic_fs:4; + fs_cvt_tmp:4 = 0; + if (rm_tmp == 0) goto ; + fs_cvt_tmp = floor(fs_tmp); # RM is 1, no rounding, and floor returns a float + goto ; + + fs_cvt_tmp = round(fs_tmp); # round returns a float + + mic_ftD_5 = trunc(fs_cvt_tmp); +} + +:cvt.l.D mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b00000100 { + rm_tmp:1 = fcsr[0,2]; # Get RM rounding mode bits + if (rm_tmp == 0) goto ; + fd_tmp:8 = floor(mic_fsD); # RM is 1, no rounding + goto ; + + fd_tmp = round(mic_fsD); + + mic_ftD_5 = trunc(fd_tmp); +} + +:cvt.s.D mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD ; micb_bit15=0 & micb_fmt=0 & micb_poolfx=0b111011 & micb_flt6=0b1101101 { + fd_tmp:4 = float2float(mic_fsD); + mic_ft_5 = zext(fd_tmp); +} + +:cvt.s.W mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_bit15=0 & micb_fmt=1 & micb_poolfx=0b111011 & micb_flt6=0b1101101 { + fs_tmp:4 = mic_fs:4; + fd_tmp:4 = int2float(fs_tmp); + mic_ft_5 = zext(fd_tmp); +} + +:cvt.s.L mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD ; micb_bit15=0 & micb_fmt=2 & micb_poolfx=0b111011 & micb_flt6=0b1101101 { + fd_tmp:4 = int2float(mic_fsD); + mic_ft_5 = zext(fd_tmp); +} + +:cvt.w.S mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b00100100 { + rm_tmp:1 = fcsr[0,2]; # Get RM rounding mode bits + fs_tmp:4 = mic_fs:4; + fs_cvt_tmp:4 = 0; + if (rm_tmp == 0) goto ; + fs_cvt_tmp = floor(fs_tmp); # RM is 1, no rounding, and floor returns a float + goto ; + + fs_cvt_tmp = round(fs_tmp); # round returns a float + + fd_tmp:4 = trunc(fs_cvt_tmp); + mic_ft_5 = zext(fd_tmp); # trunc returns an integer +} + +:cvt.w.D mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD ; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b00100100 { + rm_tmp:1 = fcsr[0,2]; # Get RM rounding mode bits + if (rm_tmp == 0) goto ; + fs_tmp:8 = floor(mic_fsD); # RM is 1, no rounding + goto ; + + fs_tmp = round(mic_fsD); + + fd_tmp:4 = trunc(fs_tmp); + mic_ft_5 = zext(fd_tmp); # In 64-bit FPUs, fd might be 64-bits, so need to set top half to something +} + +:deret is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_code=0 ; micb_poolax=0b111100 & micb_axf=0b1110001101 {} + +:di DIDISP is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5=0 & DIDISP ; micb_poolax=0b111100 & micb_axf=0b0100011101 { + disableInterrupts(DIDISP); +} + +:div.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_fd & micb_bit10=0 & micb_fmt8=0 & micb_fxf3=0b11110000 { + fs_tmp:4 = mic_fs:4; # need to only get the single float 32-bit (mic_fs might be 64-bits) + ft_tmp:4 = mic_ft_5:4; + fd_tmp:4 = fs_tmp f/ ft_tmp; + micb_fd = zext(fd_tmp); +} + +:div.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_fdD & micb_fd & micb_bit10=0 & micb_fmt8=1 & micb_fxf3=0b11110000 { + micb_fdD = mic_fsD f/ mic_ftD_5; +} + +:ehb is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_code=0b0000000000 ; micb_poolax=0 & micb_rx=0 & micb_rd32=3 { + hazzard(); +} + +:ei DIDISP is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5=0 & DIDISP ; micb_poolax=0b111100 & micb_axf=0b0101011101 { + enableInterrupts(DIDISP); +} + +:eret is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_code=0 ; micb_poolax=0b111100 & micb_axf=0b1111001101 {} + +:eretnc is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_code=1 ; micb_poolax=0b111100 & micb_axf=0b1111001101 {} + +:ext mic_rt32_5, RS0L, micb_pos, SIZEP is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & RS0L ; micb_poolax=0b101100 & micb_pos & SIZEP { + tmpa:4 = 0xFFFFFFFF; + tmpa = tmpa >> (32 - SIZEP); + tmpb:4 = RS0L; + tmpb = (tmpb >> micb_pos) & tmpa; + mic_rt32_5 = sext(tmpb); +} + +:floor.l.S mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_ftD_5 ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b00001100 { + fs_tmp:4 = mic_fs:4; + fd_tmp:4 = floor(fs_tmp); # returns a float + mic_ftD_5 = trunc(fd_tmp); # converts float to int +} + +:floor.l.D mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b00001100 { + fsD_tmp:8 = floor(mic_fsD); + mic_ftD_5 = trunc(fsD_tmp); +} + +:floor.w.S mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b00101100 { + fs_tmp:4 = mic_fs:4; + fd_tmp:4 = floor(fs_tmp); # returns a float + mic_ft_5 = trunc(fd_tmp); # converts float to int +} + +:floor.w.D mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD ; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b00101100 { + fs_tmp:8 = floor(mic_fsD); + fd_tmp:4 = trunc(fs_tmp); + mic_ft_5 = zext(fd_tmp); +} + +:ins RT5L, RS0L, micb_pos, SIZEQ is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & RS0L & RT5L ; micb_poolax=0b001100 & micb_pos & SIZEQ { + tmpa:4 = 0xFFFFFFFF; + tmpa = tmpa >> (32 - SIZEQ); + tmpb:4 = RS0L & tmpa; + tmpa = tmpa << micb_pos; + tmpa = ~tmpa; + tmpb = tmpb << micb_pos; + RT5L = (RT5L & tmpa) | tmpb; + mic_rt32_5 = sext(RT5L); +} + +:lb mic_rt32_5, EXT_MS16(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b000111 & mic_rt32_5 & mic_base0 ; EXT_MS16 { + tmp:$(REGSIZE) = sext(EXT_MS16); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt32_5 = sext(*[ram]:1 tmpa); +} + +:lbe mic_rt32_5, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_rt32_5 & mic_base0 ; micb_func12=0b0110 & micb_sub9=0b100 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt32_5 = sext(*[ram]:1 tmpa); +} + +:lbu mic_rt32_5, EXT_MS16(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b000101 & mic_rt32_5 & mic_base0 ; EXT_MS16 { + tmp:$(REGSIZE) = sext(EXT_MS16); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt32_5 = zext(*[ram]:1 tmpa); +} + +:lbue mic_rt32_5, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_rt32_5 & mic_base0 ; micb_func12=0b0110 & micb_sub9=0b000 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt32_5 = zext(*[ram]:1 tmpa); +} + +:lbu16 mic_rt7, EXT_CODE4B(mic_base4) is ISA_MODE=1 & RELP=0 & mic_op=0b000010 & mic_rt7 & mic_base4 & EXT_CODE4B { + tmp:$(REGSIZE) = sext(EXT_CODE4B); + tmp = tmp + mic_base4; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt7 = zext(*[ram]:1 tmpa); +} + +:ldc1 mic_ft_5, EXT_MS16(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b101111 & mic_base0 & mic_ft_5 & mic_ftD_5; EXT_MS16 { + tmp:$(REGSIZE) = sext(EXT_MS16); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_ftD_5 = *[ram]:8 tmpa; +} + +:ldc2 mic_rt32_5, EXT_CODE12(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b001000 & mic_rt32_5 & mic_base0 ; micb_func12=0b0010 & EXT_CODE12 { + tmp:$(REGSIZE) = sext(EXT_CODE12); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + setCopReg(2:1,mic_rt32_5,*[ram]:8 tmpa); +} + +:lh mic_rt32_5, EXT_MS16(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b001111 & mic_rt32_5 & mic_base0 ; EXT_MS16 { + tmp:$(REGSIZE) = sext(EXT_MS16); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt32_5 = sext(*[ram]:2 tmpa); +} + +:lhe mic_rt32_5, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_rt32_5 & mic_base0 ; micb_func12=0b0110 & micb_sub9=0b101 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt32_5 = sext(*[ram]:2 tmpa); +} + +:lhu mic_rt32_5, EXT_MS16(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b001101 & mic_rt32_5 & mic_base0 ; EXT_MS16 { + tmp:$(REGSIZE) = sext(EXT_MS16); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt32_5 = zext(*[ram]:2 tmpa); +} + +:lhue mic_rt32_5, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_rt32_5 & mic_base0 ; micb_func12=0b0110 & micb_sub9=0b001 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt32_5 = zext(*[ram]:2 tmpa); +} + +:lhu16 mic_rt7, EXT_CODE4C(mic_base4) is ISA_MODE=1 & RELP=0 & mic_op=0b001010 & mic_rt7 & mic_base4 & EXT_CODE4C { + tmp:$(REGSIZE) = sext(EXT_CODE4C); + tmp = tmp + mic_base4; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt7 = zext(*[ram]:2 tmpa); +} + +:li16 mic_rd7, EXT_CODE7 is ISA_MODE=1 & RELP=0 & mic_op=0b111011 & mic_rd7 & EXT_CODE7 { + mic_rd7 = sext(EXT_CODE7); +} + +:ll mic_rt32_5, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_rt32_5 & mic_base0 ; micb_func12=0b0011 & micb_sub9=0 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt32_5 = sext(*[ram]:4 tmpa); + lockload(tmp); +} + +:lle mic_rt32_5, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_rt32_5 & mic_base0 ; micb_func12=0b0110 & micb_sub9=0b110 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt32_5 = sext(*[ram]:4 tmpa); + lockload(tmp); +} + +:lui RS0RT5, micb_imm16 is ISA_MODE=1 & RELP=0 & RS0RT5 & ((mic_op=0b010000 & mic_sub2=0b01101 & REL6=0) | (mic_op=0b000100 & mic_rs32_0=0 & REL6=1)); micb_imm16 { + tmp:4 = micb_imm16; + tmp = tmp << 16; + RS0RT5 = sext(tmp); +} + +:lw mic_rt32_5, EXT_MS16(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b111111 & mic_rt32_5 & mic_base0 ; EXT_MS16 { + tmp:$(REGSIZE) = sext(EXT_MS16); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt32_5 = sext(*[ram]:4 tmpa); +} + +:lwe mic_rt32_5, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_rt32_5 & mic_base0 ; micb_func12=0b0110 & micb_sub9=0b111 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt32_5 = sext(*[ram]:4 tmpa); +} + +:lw16 mic_rt7, EXT_CODE4D(mic_base4) is ISA_MODE=1 & RELP=0 & mic_op=0b011010 & mic_rt7 & mic_base4 & EXT_CODE4D { + tmp:$(REGSIZE) = sext(EXT_CODE4D); + tmp = tmp + mic_base4; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt7 = sext(*[ram]:4 tmpa); +} + +:lwm16 LOAD_TOP16 is ISA_MODE=1 & RELP=0 & mic_op=0b010001 & LOAD_TOP16 & ((mic_csub=0b0100 & REL6=0) | (mic_csubr6=0b0010 & REL6=1)) { + build LOAD_TOP16; +} + +:lwm32 LOAD_TOP is ISA_MODE=1 & RELP=0 & mic_op=0b001000 & mic_base0 & mic_rlist ; micb_func12=0b0101 & LOAD_TOP [ ext_32_basea=mic_base0; ext_32_rlist=mic_rlist; ] { + build LOAD_TOP; +} + +:lwc1 mic_ft_5, EXT_MS16(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b100111 & mic_base0 & mic_ft_5 ; EXT_MS16 { + tmp:$(REGSIZE) = sext(EXT_MS16); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_ft_5 = sext( *[ram]:4 tmpa); +} + +:lwc2 mic_rt32_5, EXT_CODE12(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b001000 & mic_rt32_5 & mic_base0 ; micb_func12=0b0000 & EXT_CODE12 { + tmp:$(REGSIZE) = sext(EXT_CODE12); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + setCopReg(2:1,mic_rt32_5,*[ram]:4 tmpa); +} + +:lwp mic_rd32_5, EXT_CODE12(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b001000 & mic_rd32_5 & mic_base0 & ext_32_rd ; micb_func12=0b0001 & EXT_CODE12 [ext_32_rdset = mic_rd32_5+1;] { + tmp:$(REGSIZE) = sext(EXT_CODE12); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rd32_5 = sext( *[ram]:4 tmpa); + tmp = tmp + 4; + ValCast(tmpa,tmp); + ext_32_rd = sext( *[ram]:4 tmpa); +} + +:lwgp mic_rt7, EXT_CODE7A(gp) is ISA_MODE=1 & RELP=0 & mic_op=0b011001 & mic_rt7 & gp & EXT_CODE7A { + tmp:$(REGSIZE) = sext(EXT_CODE7A); + tmp = tmp + gp; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt7 = sext( *[ram]:4 tmpa); +} + +:lwsp mic_rt32_5, EXT_CODE5(sp) is ISA_MODE=1 & RELP=0 & mic_op=0b010010 & mic_rt32_5 & sp & EXT_CODE5 { + tmp:$(REGSIZE) = zext(EXT_CODE5); + tmp = tmp + sp; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt32_5 = sext( *[ram]:4 tmpa); +} + +:lwxs micb_rd32, mic_index(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_index & mic_base0 ; micb_bit10=0 & micb_rd32 & ((micb_axf2=0b0100011000 & REL6=0) | (micb_axf2=0b0100000000 & REL6=1)) { + tmp:$(REGSIZE) = mic_base0 + (mic_index << 2); + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + micb_rd32 = sext( *[ram]:4 tmpa); +} + +:mfc0 mic_rt32_5, mic_rs32_0, CPSEL is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0 & mic_rt32_5 ; micb_z14=0 & micb_cpf=0b00011 & micb_poolax=0b111100 & CPSEL { + mic_rt32_5 = getCopReg(0:1,mic_rs32_0,CPSEL); +} + +:mfc1 mic_rt32_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_rt32_5 & mic_fs ; micb_poolfx=0b111011 & micb_fxf=0b0010000000 { + mic_rt32_5 = sext(mic_fs:4); +} + +:mfc2 mic_rt32_5, mic_impl is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_impl ; micb_poolax=0b111100 & micb_axf=0b0100110100 { + mic_rt32_5 = getCopReg(2:1,mic_impl:1); +} + +:mfhc0 mic_rt32_5, mic_rs32_0, CPSEL is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0 & mic_rt32_5 ; micb_z14=0 & micb_cpf=0b00011 & micb_poolax=0b110100 & CPSEL { + mic_rt32_5 = getCopRegH(0:1,mic_rs32_0,CPSEL); +} + +:mfhc1 mic_rt32_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_rt32_5 & mic_fs & mic_fsD ; micb_poolfx=0b111011 & micb_fxf=0b0011000000 { + tmp:4 = mic_fsD[32,32]; + mic_rt32_5 = sext(tmp); +} + +:mfhc2 mic_rt32_5, mic_impl is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_impl ; micb_poolax=0b111100 & micb_axf=0b1000110100 { + mic_rt32_5 = getCopRegH(2:1,mic_impl:1); +} + +:mov.S mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_bit15=0 & micb_fmt=0 & micb_poolfx=0b111011 & micb_flt6=0b0000001 { + mic_ft_5 = zext(mic_fs:4); +} + +:mov.D mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_bit15=0 & micb_fmt=1 & micb_poolfx=0b111011 & micb_flt6=0b0000001 { + mic_ftD_5 = mic_fsD; +} + +:move16 mic_rd32_5, mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b000011 & mic_rd32_5 & mic_rs32_0 { + mic_rd32_5 = mic_rs32_0; +} + +# The docs are not clear if this format is pre and/or post R6. +:movep mic_encrd, mic_encre, ENCRS, mic_encrt is ISA_MODE=1 & RELP=0 & mic_op=0b100001 & mic_bit0=0 & mic_encrd & mic_encre & ENCRS & mic_encrt & mic_bit3 & mic_bit01 [ext_16_rshi=mic_bit3; ext_16_rslo=mic_bit01;] { + mic_encrd = ENCRS; + mic_encre = mic_encrt; +} + +:mtc0 mic_rt32_5, mic_rs32_0, CPSEL is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0 & mic_rt32_5 ; micb_z14=0 & micb_cpf=0b01011 & micb_poolax=0b111100 & CPSEL { + setCopReg(0:1,mic_rs32_0,mic_rt32_5,CPSEL); +} + +:mtc1 RT5L, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & RT5L & mic_fs ; micb_poolfx=0b111011 & micb_fxf=0b0010100000 { + mic_fs[0,32] = RT5L; +} + +:mtc2 mic_rt32_5, mic_impl is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_impl ; micb_poolax=0b111100 & micb_axf=0b0101110100 { + setCopReg(2:1,mic_rt32_5,mic_impl:1); +} + +:mthc0 mic_rt32_5, mic_rs32_0, CPSEL is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0 & mic_rt32_5 ; micb_z14=0 & micb_cpf=0b01011 & micb_poolax=0b110100 & CPSEL { + setCopRegH(0:1,mic_rs32_0,mic_rt32_5,CPSEL); +} + +:mthc1 RT5L, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & RT5L & mic_fs & mic_fsD ; micb_poolfx=0b111011 & micb_fxf=0b0011100000 { + mic_fsD[32,32] = RT5L; +} + +:mthc2 mic_rt32_5, mic_impl is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_impl ; micb_poolax=0b111100 & micb_axf=0b1001110100 { + setCopRegH(2:1,mic_rt32_5,mic_impl:1); +} + +:mul micb_rd32, RS0L, RT5L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & RT5L ; micb_rd32 & micb_bit10=0 & ((micb_axf2=0b1000010000 & REL6=0) | (micb_axf2=0b0000011000 & REL6=1)) { + tmp:4 = RS0L * RT5L; + micb_rd32 = sext(tmp); +} + +:mul.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_fd & micb_bit10=0 & micb_fmt8=0 & micb_fxf3=0b10110000 { + fd_tmp:4 = mic_fs:4 f* mic_ft_5:4; + micb_fd = zext(fd_tmp); +} + +:mul.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_bit10=0 & micb_fmt8=1 & micb_fxf3=0b10110000 { + micb_fdD = mic_fsD f* mic_ftD_5; +} + +:neg.S mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_bit15=0 & micb_fmt=0 & micb_poolfx=0b111011 & micb_flt6=0b0101101 { + fs_tmp:4 = mic_fs:4; + fd_tmp:4 = f- fs_tmp; + mic_ft_5 = zext(fd_tmp); +} + +:neg.D mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5; micb_bit15=0 & micb_fmt=1 & micb_poolfx=0b111011 & micb_flt6=0b0101101 { + mic_ftD_5 = f- mic_fsD; +} + +# This is a special case of sll +:nop is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0=0 & mic_rt32_5=0 ; micb_sa=0 & micb_axf2=0b0000000000 & micb_bit10=0 { +} + +:nor micb_rd32, mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b1011010000 & micb_bit10=0 & micb_rd32 { + micb_rd32 = ~(mic_rs32_0 | mic_rt32_5); +} + +:not16 RT3R7, RS0R4 is ISA_MODE=1 & RELP=0 & mic_op=0b010001 & RT3R7 & RS0R4 & ((mic_csub=0b0000 & REL6=0) | (mic_csubr6=0b0000 & REL6=1)) { + RT3R7 = ~RS0R4; +} + +:or micb_rd32, mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b1010010000 & micb_bit10=0 & micb_rd32 { + micb_rd32 = mic_rs32_0 | mic_rt32_5; +} + +:ori mic_rt32_5, mic_rs32_0, micb_imm16 is ISA_MODE=1 & RELP=0 & mic_op=0b010100 & mic_rs32_0 & mic_rt32_5 ; micb_imm16 { + tmp:$(REGSIZE) = micb_imm16; + mic_rt32_5 = mic_rs32_0 | tmp; +} + +:or16 RT3R7, RS0R4 is ISA_MODE=1 & RELP=0 & mic_op=0b010001 & RT3R7 & RS0R4 & ((mic_csub=0b0011 & REL6=0) | (mic_csubr6=0b1001 & REL6=1)) { + RT3R7 = RT3R7 | RS0R4; +} + +:pause is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0=0 & mic_rt32_5=0 ; micb_sa=0b00101 & micb_axf2=0b0000000000 & micb_bit10=0 { + wait(); +} + +:pref mic_cop5, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_cop5 & mic_base0 ; micb_func12=0b0100 & micb_sub9=0b000 & EXT_CODE9E { + tmp:$(REGSIZE) = zext(EXT_CODE9E); + tmp = tmp + mic_base0; + prefetch(mic_cop5:1,tmp); +} + +:prefe mic_cop5, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_cop5 & mic_base0 ; micb_func12=0b1010 & micb_sub9=0b010 & EXT_CODE9E { + tmp:$(REGSIZE) = zext(EXT_CODE9E); + tmp = tmp + mic_base0; + prefetch(mic_cop5:1,tmp); +} + +:rdpgpr mic_rt32_5, mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_axf=0b1110000101 { + mic_rt32_5 = getShadow(mic_rs32_0); +} + +:recip.S mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b01001000 { + fd_tmp:4 = 1:4 f/ mic_fs:4; + mic_ft_5 = zext(fd_tmp); +} + +:recip.D mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_ftD_5 & mic_fsD ; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b01001000 { + mic_ftD_5 = 1:8 f/ mic_fsD; +} + +:rotr mic_rt32_5, RS0L, micb_sa is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & mic_rt32_5 ; micb_sa & micb_axf2=0b0011000000 & micb_bit10=0 { + tmpa:4 = RS0L >> micb_sa; + tmpb:4 = RS0L << (32 - micb_sa); + tmpa = tmpa | tmpb; + mic_rt32_5 = sext(tmpa); +} + +:rotrv micb_rd32, RT5L, RS0L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & RT5L ; micb_rd32 & micb_axf2=0b0011010000 & micb_bit10=0 { + tmpr:1 = RS0L[0,5]; + tmpa:4 = RT5L >> tmpr; + tmpb:4 = RT5L << (32 - tmpr); + tmpa = tmpa | tmpb; + micb_rd32 = sext(tmpa); +} + +:round.l.S mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_ftD_5 ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b11001100 { + fd_tmp:4 = round(mic_fs:4); # round returns a float of the same size are the arg + mic_ftD_5 = trunc(fd_tmp); # trunc converts to any size integer +} + +:round.l.D mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b11001100 { + fsD_tmp:8 = round(mic_fsD); + mic_ftD_5 = trunc(fsD_tmp); +} + +:round.w.S mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_ftD_5 ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b11101100 { + fd_tmp:4 = round(mic_fs:4); + mic_ft_5 = trunc(fd_tmp); +} + +:round.w.D mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD ; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b11101100 { + fdD_tmp:8 = round(mic_fsD); # round returns a float, not an int + fd_tmp:4 = trunc(fdD_tmp); # We need only a 32-bit integer + mic_ft_5 = zext(fd_tmp); # But fill the top half with 0s if we have a 64-bit FPU +} + +:rsqrt.S mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b00001000 { + fd_tmp:4 = 1:4 f/ sqrt(mic_fs:4); + mic_ft_5 = zext(fd_tmp); +} + +:rsqrt.D mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b00001000 { + mic_ftD_5 = 1:8 f/ sqrt( mic_fsD ); +} + +:sb RT5L, EXT_MS16(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b000110 & RT5L & mic_base0 ; EXT_MS16 { + tmp:$(REGSIZE) = sext(EXT_MS16); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:1 tmpa = RT5L:1; +} + +:sbe RT5L, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & RT5L & mic_base0 ; micb_func12=0b1010 & micb_sub9=0b100 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:1 tmpa = RT5L:1; +} + +:sb16 mic_encrt2, mic_off4(mic_base4) is ISA_MODE=1 & RELP=0 & mic_op=0b100010 & mic_encrt2 & mic_base4 & mic_off4 { + tmp:$(REGSIZE) = mic_off4; + tmp = tmp + mic_base4; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:1 tmpa = mic_encrt2:1; +} + +:sc RT5L, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & RT5L & mic_base0 ; micb_func12=0b1011 & micb_sub9=0b000 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + lockwrite(tmp); + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:4 tmpa = RT5L; + RT5L = 1; +} + +:sce RT5L, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & RT5L & mic_base0 ; micb_func12=0b1010 & micb_sub9=0b110 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:4 tmpa = RT5L; + lockwrite(tmp); +} + +:sdbbp mic_code is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_code ; micb_poolax=0b111100 & micb_axf=0b1101101101 { + break(mic_code:2); +} + +:sdbbp16 SDB16 is ISA_MODE=1 & RELP=0 & mic_op=0b100010 & SDB16 & ((mic_break=0b101100 & REL6=0) | (mic_breakr6=0b111011 & REL6=1)) { + break(SDB16); +} + +:sdc1 mic_ft_5, EXT_MS16(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b101110 & mic_base0 & mic_ft_5 & mic_ftD_5 ; EXT_MS16 { + tmp:$(REGSIZE) = sext(EXT_MS16); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:8 tmpa = mic_ftD_5; +} + +:sdc2 mic_rt32_5, EXT_CODE12(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_rt32_5 & mic_base0 ; micb_func12=0b1010 & EXT_CODE12 { + tmp:$(REGSIZE) = sext(EXT_CODE12); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:8 tmpa = getCopReg(2:1,mic_rt32_5); +} + +:seb mic_rt32_5, RS0L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & RS0L ; micb_poolax=0b111100 & micb_axf=0b0010101100 { + mic_rt32_5 = sext(RS0L:1); +} + +:seh mic_rt32_5, RS0L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & RS0L ; micb_poolax=0b111100 & micb_axf=0b0011101100 { + mic_rt32_5 = sext(RS0L:2); +} + +:sh RT5L, EXT_MS16(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b001110 & RT5L & mic_base0 ; EXT_MS16 { + tmp:$(REGSIZE) = sext(EXT_MS16); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:2 tmpa = RT5L:2; +} + +:she RT5L, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & RT5L & mic_base0 ; micb_func12=0b1010 & micb_sub9=0b101 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:2 tmpa = RT5L:2; +} + +:sh16 mic_encrt2, EXT_CODE4C(mic_base4) is ISA_MODE=1 & RELP=0 & mic_op=0b101010 & mic_encrt2 & mic_base4 & EXT_CODE4C { + tmp:$(REGSIZE) = sext(EXT_CODE4C); + tmp = tmp + mic_base4; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:2 tmpa = mic_encrt2:2; +} + +:sll mic_rt32_5, RS0L, micb_sa is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & mic_rt32_5 ; micb_sa & micb_axf2=0b0000000000 & micb_bit10=0 { + mic_rt32_5 = sext(RS0L << micb_sa); +} + +:sllv micb_rd32, RT5L, RS0L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & RT5L ; micb_axf2=0b0000010000 & micb_bit10=0 & micb_rd32 { + tmp:1 = RS0L[0,5]; + micb_rd32 = sext(RT5L << tmp); +} + +:sll16 mic_rd7, RT4L, EXT_SA is ISA_MODE=1 & RELP=0 & mic_op=0b001001 & mic_bit0=0 & mic_rd7 & RT4L & EXT_SA { + mic_rd7 = sext(RT4L << EXT_SA); +} + +:slt micb_rd32, mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b1101010000 & micb_bit10=0 & micb_rd32 { + tmp:1 = mic_rs32_0 s< mic_rt32_5; + micb_rd32 = zext(tmp); +} + +:slti mic_rt32_5, mic_rs32_0, EXT_MS16 is ISA_MODE=1 & RELP=0 & mic_op=0b100100 & mic_rs32_0 & mic_rt32_5 ; EXT_MS16 { + tmp:$(REGSIZE) = sext(EXT_MS16); + tmpa:1 = mic_rs32_0 s< tmp; + mic_rt32_5 = zext(tmpa); +} + +:sltiu mic_rt32_5, mic_rs32_0, EXT_MS16 is ISA_MODE=1 & RELP=0 & mic_op=0b101100 & mic_rs32_0 & mic_rt32_5 ; EXT_MS16 { + tmp:$(REGSIZE) = sext(EXT_MS16); + tmpa:1 = mic_rs32_0 < tmp; + mic_rt32_5 = zext(tmpa); +} + +:sltu micb_rd32, mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b1110010000 & micb_bit10=0 & micb_rd32 { + tmp:1 = mic_rs32_0 < mic_rt32_5; + micb_rd32 = zext(tmp); +} + +:sqrt.S mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b00101000 { + fd_tmp:4 = sqrt(mic_fs:4); + mic_ft_5 = zext(fd_tmp); +} + +:sqrt.D mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b00101000 { + mic_ftD_5 = sqrt(mic_fsD); +} + +:sra mic_rt32_5, RS0L, micb_sa is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & mic_rt32_5 ; micb_sa & micb_axf2=0b0010000000 & micb_bit10=0 { + mic_rt32_5 = sext(RS0L s>> micb_sa); +} + +:srav micb_rd32, RT5L, RS0L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & RT5L ; micb_axf2=0b0010010000 & micb_bit10=0 & micb_rd32 { + tmp:1 = RS0L[0,5]; + micb_rd32 = sext(RT5L s>> tmp); +} + +:srl mic_rt32_5, RS0L, micb_sa is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & mic_rt32_5 ; micb_sa & micb_axf2=0b0001000000 & micb_bit10=0 { + mic_rt32_5 = sext(RS0L >> micb_sa); +} + +:srlv micb_rd32, RT5L, RS0L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & RT5L ; micb_axf2=0b0001010000 & micb_bit10=0 & micb_rd32 { + tmp:1 = RS0L[0,5]; + micb_rd32 = sext(RT5L >> tmp); +} + +:srl16 mic_rd7, RT4L, EXT_SA is ISA_MODE=1 & RELP=0 & mic_op=0b001001 & mic_bit0=1 & mic_rd7 & RT4L & EXT_SA { + mic_rd7 = sext(RT4L >> EXT_SA); +} + +:ssnop is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0=0 & mic_rt32_5=0 ; micb_sa=1 & micb_axf2=0b0000000000 & micb_bit10=0 {} + +:sub micb_rd32, RS0L, RT5L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & RT5L ; micb_axf2=0b0110010000 & micb_bit10=0 & micb_rd32 { +# Do we want this check? + #tmpa:8 = sext(RS0L); + #tmpb:8 = sext(RT5L); + #tmpa = tmpa - tmpb; + #if (tmpa[31,1] != tmpa[32,1]) goto ; + micb_rd32 = sext(RS0L - RT5L); + # +} + +:sub.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_fd & micb_bit10=0 & micb_fmt8=0 & micb_fxf3=0b01110000 { + fd_tmp:4 = mic_fs:4 f- mic_ft_5:4; + micb_fd = zext(fd_tmp); +} + +:sub.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_fdD & micb_fd & micb_bit10=0 & micb_fmt8=1 & micb_fxf3=0b01110000 { + micb_fdD = mic_fsD f- mic_ftD_5; +} + +:subu micb_rd32, RS0L, RT5L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & RS0L & RT5L ; micb_axf2=0b0111010000 & micb_bit10=0 & micb_rd32 { + micb_rd32 = sext(RS0L - RT5L); +} + +:subu16 RD7R1, RS1R7L, RT4L is ISA_MODE=1 & RELP=0 & mic_op=0b000001 & mic_bit0=1 & RD7R1 & RT4L & RS1R7L { + RD7R1 = sext(RS1R7L - RT4L); +} + +:sw RT5L, EXT_MS16(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b111110 & RT5L & mic_base0 ; EXT_MS16 { + tmp:$(REGSIZE) = sext(EXT_MS16); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:4 tmpa = RT5L:4; +} + +:swe RT5L, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & RT5L & mic_base0 ; micb_func12=0b1010 & micb_sub9=0b111 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:4 tmpa = RT5L:4; +} + +:sw16 mic_encrt2, EXT_CODE4E(mic_base4) is ISA_MODE=1 & RELP=0 & mic_op=0b111010 & mic_encrt2 & mic_base4 & EXT_CODE4E { + tmp:$(REGSIZE) = sext(EXT_CODE4E); + tmp = tmp + mic_base4; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:4 tmpa = mic_encrt2:4; +} + +:swc1 mic_ft_5, EXT_MS16(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b100110 & mic_base0 & mic_ft_5 ; EXT_MS16 { + tmp:$(REGSIZE) = sext(EXT_MS16); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:4 tmpa = mic_ft_5:4; +} + +:swc2 mic_rt32_5, micb_offset11s(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b001000 & mic_rt32_5 & mic_base0 ; micb_func12=0b1000 & micb_bit11=0 & micb_offset11s { + tmp:$(REGSIZE) = micb_offset11s; + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:4 tmpa = getCopReg(2:1,mic_rt32_5); +} + +:swsp RT5L, EXT_CODE5(sp) is ISA_MODE=1 & RELP=0 & mic_op=0b110010 & RT5L & sp & EXT_CODE5 { + tmp:$(REGSIZE) = zext(EXT_CODE5); + tmp = tmp + sp; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:4 tmpa = RT5L; +} + +:swp RT5L, EXT_CODE12(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b001000 & RT5L & mic_base0 & RSEXTL & mic_rs32_5; micb_func12=0b1001 & EXT_CODE12 [ext_32_rs1set = mic_rs32_5+1;] { + tmp:$(REGSIZE) = sext(EXT_CODE12); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:4 tmpa = RT5L; + tmp = tmp + 4; + ValCast(tmpa,tmp); + *[ram]:4 tmpa = RSEXTL; +} + +:swm16 STORE_TOP16 is ISA_MODE=1 & RELP=0 & mic_op=0b010001 & STORE_TOP16 & ((mic_csub=0b0101 & REL6=0) | (mic_csubr6=0b1010 & REL6=1)) { + build STORE_TOP16; +} + +:swm32 STORE_TOP is ISA_MODE=1 & RELP=0 & mic_op=0b001000 & mic_base0 & mic_rlist ; micb_func12=0b1101 & STORE_TOP [ ext_32_basea=mic_base0; ext_32_rlist=mic_rlist; ] { + build STORE_TOP; +} + +:sync STYPE is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_funci=0 & STYPE ; micb_poolax=0b111100 & micb_axf=0b0110101101 { + synch(STYPE); +} + +:synci EXT_MS16(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & mic_base0 & ((mic_funci=0b10000 & REL6=0) | (mic_funci=0b01100 & REL6=1)); EXT_MS16 { + tmp:$(REGSIZE) = sext(EXT_MS16); + tmp = tmp + mic_base0; + synch(tmp); +} + +:syscall is ISA_MODE=1 & RELP=0 & mic_op=0b000000 ; micb_poolax=0b111100 & micb_axf=0b1000101101 { + syscall(); +} + +:teq mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_trap=0b000000 { + if (mic_rs32_0 != mic_rt32_5) goto ; + trap(); + +} + +:tge mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_trap=0b001000 { + if (mic_rt32_5 s< mic_rs32_0) goto ; + trap(); + +} + +:tgeu mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_trap=0b010000 { + if (mic_rt32_5 < mic_rs32_0) goto ; + trap(); + +} + +:tlbinv is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_code=0 ; micb_poolax=0b111100 & micb_axf=0b0100001101 { + tlbop(0:1); +} + +:tlbinvf is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_code=0 ; micb_poolax=0b111100 & micb_axf=0b0101001101 { + tlbop(1:1); +} + +:tlbp is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_code=0 ; micb_poolax=0b111100 & micb_axf=0b0000001101 { + tlbop(2:1); +} + +:tlbr is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_code=0 ; micb_poolax=0b111100 & micb_axf=0b0001001101 { + tlbop(3:1); +} + +:tlbwi is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_code=0 ; micb_poolax=0b111100 & micb_axf=0b0010001101 { + tlbop(4:1); +} + +:tlbwr is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_code=0 ; micb_poolax=0b111100 & micb_axf=0b0011001101 { + tlbop(5:1); +} + +:tlt mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_trap=0b100000 { + if (mic_rt32_5 s>= mic_rs32_0) goto ; + trap(); + +} + +:tltu mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_trap=0b101000 { + if (mic_rt32_5 >= mic_rs32_0) goto ; + trap(); + +} + +:tne mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_trap=0b110000 { + if (mic_rt32_5 == mic_rs32_0) goto ; + trap(); + +} + +:trunk.l.S mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b10001100 { + mic_ft_5 = trunc(mic_fs:4); +} + +:trunk.l.D mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b10001100 { + mic_ftD_5 = trunc(mic_fsD); +} + +:trunk.w.S mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs ; micb_bit15=0 & micb_fmt14=0 & micb_poolfx=0b111011 & micb_fxf4=0b10101100 { + fd_tmp:4 = trunc(mic_fs:4); + mic_ft_5 = zext(fd_tmp); +} + +:trunk.w.D mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD ; micb_bit15=0 & micb_fmt14=1 & micb_poolfx=0b111011 & micb_fxf4=0b10101100 { + fd_tmp:4 = trunc(mic_fsD); + mic_ft_5 = zext(fd_tmp); +} + +:wait is ISA_MODE=1 & RELP=0 & mic_op=0b000000 ; micb_poolax=0b111100 & micb_axf=0b1001001101 { + wait(); +} + +:wrpgpr mic_rt32_5, mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_axf=0b1111000101 { + setShadow(mic_rt32_5,mic_rs32_0); +} + +:wsbh mic_rt32_5, RS0L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & RS0L ; micb_poolax=0b111100 & micb_axf=0b0111101100 { + tmp1:4 = zext(RS0L[24,8]); + tmp2:4 = zext(RS0L[16,8]); + tmp3:4 = zext(RS0L[8,8]); + tmp4:4 = zext(RS0L[0,8]); + tmp5:4 = (tmp2 << 24) | (tmp1 << 16) | (tmp4 << 8) | tmp3; + mic_rt32_5 = sext(tmp5); +} + +:xor micb_rd32, mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b1100010000 & micb_bit10=0 & micb_rd32 { + micb_rd32 = mic_rs32_0 ^ mic_rt32_5; +} + +:xori mic_rt32_5, mic_rs32_0, micb_imm16 is ISA_MODE=1 & RELP=0 & mic_op=0b011100 & mic_rs32_0 & mic_rt32_5 ; micb_imm16 { + tmp:$(REGSIZE) = micb_imm16; + mic_rt32_5 = mic_rs32_0 ^ tmp; +} + +:xor16 RT3R7, RS0R4 is ISA_MODE=1 & RELP=0 & mic_op=0b010001 & RT3R7 & RS0R4 & ((mic_csub=0b0001 & REL6=0) | (mic_csubr6=0b1000 & REL6=1)) { + RT3R7 = RT3R7 ^ RS0R4; +} + +@ifdef MIPS64 +:dadd micb_rd32, mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0100010000 & micb_bit10=0 & micb_rd32 { + # The dest doesn't get modified if there's an overflow. As our sleigh max size is 64bits, checking for this is a little complicated. + # Should we include this check or not? +# tmpsl:8 = zext(mic_rs32_0:4); +# tmptl:8 = zext(mic_rt32_5:4); +# tmpsh:8 = zext(mic_rs32_0[32,32]); +# tmpth:8 = zext(mic_rt32_5[32,32]); +# tmpres:8 = tmpsl + tmptl; +# tmpres = tmpres >> 32; +# tmpres = tmpres + tmpsh + tmpth; +# tmpres = tmpres >> 32; +# if (tmpres == 1) goto ; + micb_rd32 = mic_rs32_0 + mic_rt32_5; +# +} + +:daddiu mic_rt32_5, mic_rs32_0, EXT_MS16 is ISA_MODE=1 & RELP=0 & mic_op=0b010111 & mic_rs32_0 & mic_rt32_5 ; EXT_MS16 { + tmp:8 = sext(EXT_MS16); + mic_rt32_5 = mic_rs32_0 + tmp; +} + +:daddu micb_rd32, mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0101010000 & micb_bit10=0 & micb_rd32 { + micb_rd32 = mic_rs32_0 + mic_rt32_5; +} + +:dclo mic_rt32_5, mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_axf=0b0100101100 { + mic_rt32_5 = lzcount( ~mic_rs32_0 ); +} + +:dclz mic_rt32_5, mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_axf=0b0101101100 { + mic_rt32_5 = lzcount( mic_rs32_0 ); +} + +:dext mic_rt32_5, mic_rs32_0, micb_pos, SIZEP is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b101100 & micb_pos & SIZEP { + tmpa:8 = 0xFFFFFFFFFFFFFFFF; + tmpa = tmpa >> (64 - SIZEP); + tmpb:8 = mic_rs32_0; + tmpb = (tmpb >> micb_pos) & tmpa; + mic_rt32_5 = tmpb; +} + +:dextm mic_rt32_5, mic_rs32_0, micb_pos, SIZEPLG is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b100100 & micb_pos & SIZEPLG { + tmpa:8 = 0xFFFFFFFFFFFFFFFF; + tmpa = tmpa >> (64 - SIZEPLG); + tmpb:8 = mic_rs32_0; + tmpb = (tmpb >> micb_pos) & tmpa; + mic_rt32_5 = tmpb; +} + +:dextu mic_rt32_5, mic_rs32_0, POSHI, SIZEP is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b010100 & POSHI & SIZEP { + tmpa:8 = 0xFFFFFFFFFFFFFFFF; + tmpa = tmpa >> (64 - SIZEP); + tmpb:8 = mic_rs32_0; + tmpb = (tmpb >> POSHI) & tmpa; + mic_rt32_5 = tmpb; +} + +:dins mic_rt32_5, mic_rs32_0, micb_pos, SIZEQ is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b001100 & micb_pos & SIZEQ { + tmpa:8 = 0xFFFFFFFFFFFFFFFF; + tmpa = tmpa >> (64 - SIZEQ); + tmpb:8 = mic_rs32_0 & tmpa; + tmpa = tmpa << micb_pos; + tmpa = ~tmpa; + tmpb = tmpb << micb_pos; + mic_rt32_5 = (mic_rt32_5 & tmpa) | tmpb; +} + +:dinsm mic_rt32_5, mic_rs32_0, micb_pos, SIZEQLG is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b000100 & micb_pos & SIZEQLG { + tmpa:8 = 0xFFFFFFFFFFFFFFFF; + tmpa = tmpa >> (64 - SIZEQLG); + tmpb:8 = mic_rs32_0 & tmpa; + tmpa = tmpa << micb_pos; + tmpa = ~tmpa; + tmpb = tmpb << micb_pos; + mic_rt32_5 = (mic_rt32_5 & tmpa) | tmpb; +} + +:dinsu mic_rt32_5, mic_rs32_0, POSHI, SIZEQ is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b110100 & POSHI & SIZEQ { + tmpa:8 = 0xFFFFFFFFFFFFFFFF; + tmpa = tmpa >> (64 - SIZEQ); + tmpb:8 = mic_rs32_0 & tmpa; + tmpa = tmpa << POSHI; + tmpa = ~tmpa; + tmpb = tmpb << POSHI; + mic_rt32_5 = (mic_rt32_5 & tmpa) | tmpb; +} + +:dmfc0 mic_rt32_5, mic_rs32_0, CPSEL is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; micb_z14=0 & micb_cpf=0b00011 & micb_poolax=0b111100 & CPSEL { + mic_rt32_5 = getCopReg(0:1,mic_rs32_0,CPSEL); +} + +:dmfc1 mic_rt32_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_rt32_5 & mic_fs & mic_fsD ; micb_poolfx=0b111011 & micb_fxf=0b0010010000 { + mic_rt32_5 = mic_fsD; +} + +:dmfc2 mic_rt32_5, mic_impl is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_impl ; micb_poolax=0b111100 & micb_axf=0b0110110100 { + mic_rt32_5 = getCopReg(2:1,mic_impl:1); +} + +:dmtc0 mic_rt32_5, mic_rs32_0, CPSEL is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; micb_z14=0 & micb_cpf=0b01011 & micb_poolax=0b111100 & CPSEL { + setCopReg(0:1,mic_rs32_0,mic_rt32_5,CPSEL); +} + +:dmtc1 mic_rt32_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_rt32_5 & mic_fs & mic_fsD ; micb_poolfx=0b111011 & micb_fxf=0b0010110000 { + mic_fsD = mic_rt32_5; +} + +:dmtc2 mic_rt32_5, mic_impl is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_rt32_5 & mic_impl ; micb_poolax=0b000011 & micb_axf=0b0111110100 { + setCopReg(2:1,mic_rt32_5,mic_impl:1); +} + +:drotr mic_rt32_5, mic_rs32_0, micb_sa is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; micb_sa & micb_axf2=0b0011000000 & micb_bit10=0 { + tmpa:8 = mic_rs32_0 >> micb_sa; + tmpb:8 = mic_rs32_0 << (64 - micb_sa); + tmpa = tmpa | tmpb; + mic_rt32_5 = tmpa; +} + +:drotr32 mic_rt32_5, mic_rs32_0, SA32 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; SA32 & micb_axf2=0b0011001000 & micb_bit10=0 { + tmpa:8 = mic_rs32_0 >> SA32; + tmpb:8 = mic_rs32_0 << (64 - SA32); + tmpa = tmpa | tmpb; + mic_rt32_5 = tmpa; +} + +:drotrv micb_rd32, mic_rt32_5, RS0L is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & RS0L & mic_rt32_5 ; micb_rd32 & micb_axf2=0b0011010000 & micb_bit10=0 { + tmpr:1 = RS0L[0,6]; + tmpa:8 = mic_rt32_5 >> tmpr; + tmpb:8 = mic_rt32_5 << (64 - tmpr); + tmpa = tmpa | tmpb; + micb_rd32 = tmpa; +} + +:dsbh mic_rt32_5, mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_axf=0b0111101100 { + tmp1:8 = zext(mic_rs32_0[56,8]); + tmp2:8 = zext(mic_rs32_0[48,8]); + tmp3:8 = zext(mic_rs32_0[40,8]); + tmp4:8 = zext(mic_rs32_0[32,8]); + tmp5:8 = zext(mic_rs32_0[24,8]); + tmp6:8 = zext(mic_rs32_0[16,8]); + tmp7:8 = zext(mic_rs32_0[8,8]); + tmp8:8 = zext(mic_rs32_0[0,8]); + tmp9:8 = (tmp2 << 56) | (tmp1 << 48) | (tmp4 << 40) | (tmp3 << 32) | (tmp6 << 24) | (tmp5 << 16) | (tmp8 << 8) | tmp7; + mic_rt32_5 = tmp9; +} + +:dshd mic_rt32_5, mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b111100 & micb_axf=0b1111101100 { + tmp1:8 = zext(mic_rs32_0[48,16]); + tmp2:8 = zext(mic_rs32_0[32,16]); + tmp3:8 = zext(mic_rs32_0[16,16]); + tmp4:8 = zext(mic_rs32_0[0,16]); + tmp5:8 = (tmp4 << 48) | (tmp3 << 32) | (tmp2 << 16) | tmp1; + mic_rt32_5 = tmp5; +} + +:dsll mic_rt32_5, mic_rs32_0, micb_sa is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; micb_sa & micb_axf2=0b0000000000 & micb_bit10=0 { + mic_rt32_5 = mic_rs32_0 << micb_sa; +} + +:dsll32 mic_rt32_5, mic_rs32_0, SA32 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; SA32 & micb_axf2=0b0000001000 & micb_bit10=0 { + mic_rt32_5 = mic_rs32_0 << SA32; +} + +:dsllv micb_rd32, mic_rt32_5, RS0L is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & RS0L & mic_rt32_5 ; micb_axf2=0b0000010000 & micb_bit10=0 & micb_rd32 { + tmps:1 = RS0L[0,6]; + micb_rd32 = mic_rt32_5 << tmps; +} + +:dsra mic_rt32_5, mic_rs32_0, micb_sa is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; micb_sa & micb_axf2=0b0010000000 & micb_bit10=0 { + mic_rt32_5 = mic_rs32_0 s>> micb_sa; +} + +:dsra32 mic_rt32_5, mic_rs32_0, SA32 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; SA32 & micb_axf2=0b0010000100 & micb_bit10=0 { + mic_rt32_5 = mic_rs32_0 s>> SA32; +} + +:dsrav micb_rd32, mic_rt32_5, RS0L is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & RS0L & mic_rt32_5 ; micb_axf2=0b0010010000 & micb_bit10=0 & micb_rd32 { + tmps:1 = RS0L[0,6]; + micb_rd32 = mic_rt32_5 s>> tmps; +} + +:dsrl mic_rt32_5, mic_rs32_0, micb_sa is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; micb_sa & micb_axf2=0b0001000000 & micb_bit10=0 { + mic_rt32_5 = mic_rs32_0 >> micb_sa; +} + +:dsrl32 mic_rt32_5, mic_rs32_0, SA32 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; SA32 & micb_axf2=0b0001001000 & micb_bit10=0 { + mic_rt32_5 = mic_rs32_0 >> SA32; +} + +:dsrlv micb_rd32, mic_rt32_5, RS0L is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & RS0L & mic_rt32_5 ; micb_axf2=0b0001010000 & micb_bit10=0 & micb_rd32 { + tmps:1 = RS0L[0,6]; + micb_rd32 = mic_rt32_5 >> tmps; +} + +:dsub micb_rd32, mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0110010000 & micb_bit10=0 & micb_rd32 { +# Do we want to test for this? + #tmpt:1 = zext(mic_rt32_5[63,1]); + #tmps:1 = zext(mic_rs32_0[63,1]); + #tmp:8 = mic_rs32_0 - mic_rt32_5; + #tmpa:1 = zext(tmp[63,1]); + #if ((tmpa ^ tmps) & (tmpt ^ tmps)) goto ; + micb_rd32 = mic_rs32_0 - mic_rt32_5; + # +} + +:dsubu micb_rd32, mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0111010000 & micb_bit10=0 & micb_rd32 { + micb_rd32 = mic_rs32_0 - mic_rt32_5; +} + +:ld mic_rt32_5, EXT_MS16(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b110111 & mic_rt32_5 & mic_base0 ; EXT_MS16 { + tmp:$(REGSIZE) = sext(EXT_MS16); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt32_5 = *[ram]:8 tmpa; +} + +:lld mic_rt32_5, EXT_CODE12(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_rt32_5 & mic_base0 ; micb_func12=0b0111 & EXT_CODE12 { + tmp:$(REGSIZE) = sext(EXT_CODE12); + tmp = tmp + mic_base0; + lockload(tmp); + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt32_5 = *[ram]:8 tmpa; +} + +:lwu mic_rt32_5, EXT_CODE12(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_rt32_5 & mic_base0 ; micb_func12=0b1110 & EXT_CODE12 { + tmp:$(REGSIZE) = sext(EXT_CODE12); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + tmpb:4 = *[ram]:4 tmpa; + mic_rt32_5 = zext(tmpb); +} + +:scd mic_rt32_5, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & mic_rt32_5 & mic_base0 ; micb_func12=0b1111 & micb_sub9=0b000 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + lockwrite(tmp); + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:8 tmpa = mic_rt32_5; + mic_rt32_5 = 1; +} + +:sd mic_rt32_5, EXT_MS16(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b110110 & mic_rt32_5 & mic_base0 ; EXT_MS16 { + tmp:$(REGSIZE) = sext(EXT_MS16); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:8 tmpa = mic_rt32_5; +} + +@endif + + +#### +# +# Pre-6 semantics +# +#### +:abs.PS mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_bit15=0 & micb_fmt=2 & micb_poolfx=0b111011 & micb_flt6=0b0001101 { + mic_ftD_5 = mipsFloatPS(mic_fsD); +} + +:add.PS micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_bit10=0 & micb_fmt8=2 & micb_fxf3=0b00110000 { + micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:addi mic_rt32_5, RS0L, EXT_MS16 is ISA_MODE=1 & RELP=0 & mic_op=0b000100 & REL6=0 & RS0L & mic_rt32_5; EXT_MS16 { + tmp:4 = sext(EXT_MS16); + tmp = tmp + RS0L; + mic_rt32_5 = sext(tmp); +} + +:alnv.ps micb_fd, mic_fs, mic_ft_5, micb_rs32 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_rs32 & micb_poolfx=0b011001 { + micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:b Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_rs32_0=0 & mic_rt32_5=0 ; Rel16_mic { + delayslot( 1 ); + goto Rel16_mic; +} + +:b16 Rel10_mic is ISA_MODE=1 & RELP=0 & mic_op=0b110011 & REL6=0 & Rel10_mic { + delayslot( 1 ); + goto Rel10_mic; +} + +:bal Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b00011 & mic_rs32_0=0 ; Rel16_mic { + ra = inst_next | 0x1; + delayslot( 1 ); + call Rel16_mic; +} + +:bc1f COP2CC^Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b11100 & mic_cp2z=0 & COP2CC ; Rel16_mic { + # tmp:1 = getFpCondition(cc:1); # Note that other cc conditions are not implemented + tmp:1 = fcsr[23,1]; # The floating point condition bit + delayslot(1); + if (tmp != 0) goto inst_next; + goto Rel16_mic; +} + +:bc1t COP2CC^Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b11101 & mic_cp2z=0 & COP2CC ; Rel16_mic { + # tmp:1 = getFpCondition(cc:1); + tmp:1 = fcsr[23,1]; # The floating point condition bit + delayslot(1); + if (tmp == 0) goto inst_next; + goto Rel16_mic; +} + +:bc2f COP2CC^Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b10100 & mic_cp2z=0 & COP2CC ; Rel16_mic { + tmp:1 = getCopCondition(2:1, COP2CC); + delayslot(1); + if (tmp != 0) goto inst_next; + goto Rel16_mic; +} + +:bc2t COP2CC^Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b10101 & mic_cp2z=0 & COP2CC ; Rel16_mic { + tmp:1 = getCopCondition(2:1, COP2CC); + delayslot(1); + if (tmp == 0) goto inst_next; + goto Rel16_mic; +} + +:beq mic_rs32_0, mic_rt32_5, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b100101 & REL6=0 & mic_rs32_0 & mic_rt32_5; Rel16_mic { + delayflag:1 = ( mic_rs32_0 == mic_rt32_5 ); + delayslot( 1 ); + if (delayflag) goto Rel16_mic; +} + +:beqz16 mic_rs7, Rel7_mic is ISA_MODE=1 & RELP=0 & mic_op=0b100011 & REL6=0 & mic_rs7 & Rel7_mic { + delayflag:1 = ( mic_rs7 == 0 ); + delayslot( 1 ); + if (delayflag) goto Rel7_mic; +} + +:beqzc mic_rs32_0, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b00111 & mic_rs32_0 ; Rel16_mic { + if (mic_rs32_0 == 0) goto Rel16_mic; +} + +:bgez mic_rs32_0, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b00010 & mic_rs32_0 ; Rel16_mic { + delayflag:1 = (mic_rs32_0 s>= 0); + delayslot( 1 ); + if (delayflag) goto Rel16_mic; +} + +:bgezal mic_rs32_0, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b00011 & mic_rs32_0 ; Rel16_mic { + delayflag:1 = (mic_rs32_0 s>= 0); + ra = inst_next | 0x1; + delayslot( 1 ); + if (delayflag) goto Rel16_mic; +} + +:bgezals mic_rs32_0, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b10011 & mic_rs32_0 ; Rel16_mic { + delayflag:1 = (mic_rs32_0 s>= 0); + ra = inst_next | 0x1; + delayslot( 1 ); + if (delayflag) goto Rel16_mic; +} + +:bgtz mic_rs32_0, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b00110 & mic_rs32_0 ; Rel16_mic { + delayflag:1 = (mic_rs32_0 s> 0); + delayslot( 1 ); + if (delayflag) goto Rel16_mic; +} + +:blez mic_rs32_0, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b00100 & mic_rs32_0 ; Rel16_mic { + delayflag:1 = (mic_rs32_0 s<= 0); + delayslot( 1 ); + if (delayflag) goto Rel16_mic; +} + +:bltz mic_rs32_0, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b00000 & mic_rs32_0 ; Rel16_mic { + delayflag:1 = (mic_rs32_0 s< 0); + delayslot( 1 ); + if (delayflag) goto Rel16_mic; +} + +:bltzal mic_rs32_0, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b00001 & mic_rs32_0 ; Rel16_mic { + delayflag:1 = (mic_rs32_0 s< 0); + ra = inst_next | 0x1; + delayslot( 1 ); + if (delayflag) goto Rel16_mic; +} + +:bltzals mic_rs32_0, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b10001 & mic_rs32_0 ; Rel16_mic { + delayflag:1 = (mic_rs32_0 s< 0); + ra = inst_next | 0x1; + delayslot( 1 ); + if (delayflag) goto Rel16_mic; +} + +:bne mic_rs32_0, mic_rt32_5, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b101101 & REL6=0 & mic_rs32_0 & mic_rt32_5 ; Rel16_mic { + delayflag:1 = (mic_rs32_0 != mic_rt32_5); + delayslot( 1 ); + if (delayflag) goto Rel16_mic; +} + +:bnez16 mic_rs7, Rel7_mic is ISA_MODE=1 & RELP=0 & mic_op=0b101011 & REL6=0 & mic_rs7 & Rel7_mic { + delayflag:1 = (mic_rs7 != 0); + delayslot( 1 ); + if (delayflag) goto Rel7_mic; +} + +:bnezc mic_rs32_0, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_sub2=0b00101 & mic_rs32_0 ; Rel16_mic { + if (mic_rs32_0 != 0) goto Rel16_mic; +} + +:c.f.S micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=0 & micb_poolfx=0b111100 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN + fcsr[23,1] = 0; # Always false, no trap +} +:c.f.D micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=0 & micb_poolfx=0b111100 { + trapIfSNaN(mic_fsD, mic_ftD_5); + fcsr[23,1] = 0; # Always false, no trap +} +:c.f.PS micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=0 & micb_poolfx=0b111100 { + fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:c.un.S micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=1 & micb_poolfx=0b111100 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN + fcsr[23,1] = nan(mic_fs:4) || nan(mic_ft_5:4); # True if an operand is NaN, no trap +} + +:c.un.D micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=1 & micb_poolfx=0b111100 { + trapIfSNaN(mic_fsD, mic_ftD_5); + fcsr[23,1] = nan(mic_fsD) || nan(mic_ftD_5); # True if an operand is NaN, no trap +} + +:c.un.PS micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=1 & micb_poolfx=0b111100 { + fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:c.eq.S micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=2 & micb_poolfx=0b111100 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN + fcsr[23,1] = (mic_fs:4 f== mic_ft_5:4); # No trap +} + +:c.eq.D micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=2 & micb_poolfx=0b111100 { + trapIfSNaN(mic_fsD, mic_ftD_5); + fcsr[23,1] = (mic_fsD f== mic_ftD_5); +} + +:c.eq.PS micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=2 & micb_poolfx=0b111100 { + fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:c.ueq.S micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=3 & micb_poolfx=0b111100 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN + fcsr[23,1] = (mic_fs:4 f== mic_ft_5:4); # No trap +} + +:c.ueq.D micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=3 & micb_poolfx=0b111100 { + trapIfSNaN(mic_fsD, mic_ftD_5); + fcsr[23,1] = (mic_fsD f== mic_ftD_5); # No trap +} + +:c.ueq.PS micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=3 & micb_poolfx=0b111100 { + fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:c.olt.S micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=4 & micb_poolfx=0b111100 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN + fcsr[23,1] = (mic_fs:4 f< mic_ft_5:4); # No trap +} + +:c.olt.D micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=4 & micb_poolfx=0b111100 { + trapIfSNaN(mic_fsD, mic_ftD_5); + fcsr[23,1] = (mic_fsD f< mic_ftD_5); # No trap +} + +:c.olt.PS micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=4 & micb_poolfx=0b111100 { + fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:c.ult.S micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=5 & micb_poolfx=0b111100 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN + fcsr[23,1] = (mic_fs:4 f< mic_ft_5:4) || nan(mic_fs:4) || nan(mic_ft_5:4); # Less than or NaN No trap +} + +:c.ult.D micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=5 & micb_poolfx=0b111100 { + trapIfSNaN(mic_fsD, mic_ftD_5); + fcsr[23,1] = (mic_fsD f< mic_ftD_5) || nan(mic_fsD) || nan(mic_ftD_5); # No trap +} + +:c.ult.PS micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=5 & micb_poolfx=0b111100 { + fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:c.ole.S micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=6 & micb_poolfx=0b111100 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN + fcsr[23,1] = (mic_fs:4 f<= mic_ft_5:4); # No trap +} + +:c.ole.D micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=6 & micb_poolfx=0b111100 { + trapIfSNaN(mic_fsD, mic_ftD_5); + fcsr[23,1] = (mic_fsD f<= mic_ftD_5); # No trap +} + +:c.ole.PS micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=6 & micb_poolfx=0b111100 { + fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:c.ule.S micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=7 & micb_poolfx=0b111100 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN + fcsr[23,1] = (mic_fs:4 f<= mic_ft_5:4) || nan(mic_fs:4) || nan(mic_ft_5:4); # Less than or equal or NaN No trap +} + +:c.ule.D micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=7 & micb_poolfx=0b111100 { + trapIfSNaN(mic_fsD, mic_ftD_5); + fcsr[23,1] = (mic_fsD f<= mic_ftD_5) || nan(mic_fsD) || nan(mic_ftD_5); # No trap +} + +:c.ule.PS micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=7 & micb_poolfx=0b111100 { + fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:c.sf.S micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=8 & micb_poolfx=0b111100 { + trapIfNaN(mic_fs:4, mic_ft_5:4); + fcsr[23,1] = 0; # Always false, trap if either operand is NaN +} + +:c.sf.D micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=8 & micb_poolfx=0b111100 { + trapIfNaN(mic_fsD, mic_ftD_5); + fcsr[23,1] = 0; # Always false, trap +} + +:c.sf.PS micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=8 & micb_poolfx=0b111100 { + fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:c.ngle.S micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=9 & micb_poolfx=0b111100 { + trapIfNaN(mic_fs:4, mic_ft_5:4); + fcsr[23,1] = nan(mic_fs:4) || nan(mic_ft_5:4); # True if an operand is NaN, trap +} + +:c.ngle.D micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=9 & micb_poolfx=0b111100 { + trapIfNaN(mic_fsD, mic_ftD_5); + fcsr[23,1] = nan(mic_fsD) || nan(mic_ftD_5); # True if an operand is NaN, trap +} + +:c.ngle.PS micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=9 & micb_poolfx=0b111100 { + fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:c.seq.S micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=10 & micb_poolfx=0b111100 { + trapIfNaN(mic_fs:4, mic_ft_5:4); + fcsr[23,1] = (mic_fs:4 f== mic_ft_5:4); # trap +} + +:c.seq.D micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=10 & micb_poolfx=0b111100 { + trapIfNaN(mic_fsD, mic_ftD_5); + fcsr[23,1] = (mic_fsD f== mic_ftD_5); # trap +} + +:c.seq.PS micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=10 & micb_poolfx=0b111100 { + fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:c.ngl.S micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=11 & micb_poolfx=0b111100 { + trapIfNaN(mic_fs:4, mic_ft_5:4); + fcsr[23,1] = (mic_fs:4 f== mic_ft_5:4) || nan(mic_fs:4) || nan(mic_ft_5:4); # trap +} + +:c.ngl.D micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=11 & micb_poolfx=0b111100 { + trapIfNaN(mic_fsD, mic_ftD_5); + fcsr[23,1] = (mic_fsD f== mic_ftD_5) || nan(mic_fsD) || nan(mic_ftD_5); # trap +} + +:c.ngl.PS micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=11 & micb_poolfx=0b111100 { + fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:c.lt.S micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=12 & micb_poolfx=0b111100 { + trapIfNaN(mic_fs:4, mic_ft_5:4); + fcsr[23,1] = (mic_fs:4 f< mic_ft_5:4); # trap +} + +:c.lt.D micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=12 & micb_poolfx=0b111100 { + trapIfNaN(mic_fsD, mic_ftD_5); + fcsr[23,1] = (mic_fsD f< mic_ftD_5); # trap +} + +:c.lt.PS micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=12 & micb_poolfx=0b111100 { + fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:c.nge.S micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=13 & micb_poolfx=0b111100 { + trapIfNaN(mic_fs:4, mic_ft_5:4); + fcsr[23,1] = (mic_fs:4 f< mic_ft_5:4) || nan(mic_fs:4) || nan(mic_ft_5:4); # trap +} + +:c.nge.D micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=13 & micb_poolfx=0b111100 { + trapIfNaN(mic_fsD, mic_ftD_5); + fcsr[23,1] = (mic_fsD f< mic_ftD_5) || nan(mic_fsD) || nan(mic_ftD_5); # trap +} + +:c.nge.PS micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=13 & micb_poolfx=0b111100 { + fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:c.le.S micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=14 & micb_poolfx=0b111100 { + trapIfNaN(mic_fs:4, mic_ft_5:4); + fcsr[23,1] = (mic_fs:4 f<= mic_ft_5:4); # Less than or equal trap +} + +:c.le.D micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=14 & micb_poolfx=0b111100 { + trapIfNaN(mic_fsD, mic_ftD_5); + fcsr[23,1] = (mic_fsD f<= mic_ftD_5); # trap +} + +:c.le.PS micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=14 & micb_poolfx=0b111100 { + fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:c.ngt.S micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs ; micb_cc & micb_bit12=0 & micb_fmt10=0 & micb_cond=15 & micb_poolfx=0b111100 { + trapIfNaN(mic_fs:4, mic_ft_5:4); + fcsr[23,1] = (mic_fs:4 f<= mic_ft_5:4) || nan(mic_fs:4) || nan(mic_ft_5:4); # Less than or equal or NaN trap +} + +:c.ngt.D micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=1 & micb_cond=15 & micb_poolfx=0b111100 { + trapIfNaN(mic_fsD, mic_ftD_5); + fcsr[23,1] = (mic_fsD f<= mic_ftD_5) || nan(mic_fsD) || nan(mic_ftD_5); # trap +} + +:c.ngt.PS micb_cc, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_cc & micb_bit12=0 & micb_fmt10=2 & micb_cond=15 & micb_poolfx=0b111100 { + fcsr[23,1] = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:cache mic_cop5, EXT_CODE12(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b001000 & REL6=0 & mic_cop5 & mic_base0 ; micb_func12=0b0110 & EXT_CODE12 { + cacheOp(); +} + +:cvt.PS micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_fxf2=0b00110000000 { + micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:cvt.s.PL mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_bit15=0 & micb_poolfx=0b111011 & micb_fxf4=0b10000100 { + mic_ftD_5 = mipsFloatPS(mic_fsD); +} + +:cvt.s.PU mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5 ; micb_bit15=0 & micb_poolfx=0b111011 & micb_fxf4=0b10100100 { + mic_ftD_5 = mipsFloatPS(mic_fsD); +} + +:div RT5L, RS0L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & RS0L & RT5L ; micb_poolax=0b111100 & micb_axf=0b1010101100 { + lo = sext(RS0L s/ RT5L); + hi = sext(RS0L s% RT5L); +} + +:divu RS0L, RT5L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & RS0L & RT5L ; micb_poolax=0b111100 & micb_axf=0b1011101100 { + lo = sext(RS0L / RT5L); + hi = sext(RS0L % RT5L); +} + +:j Abs26_mic1 is ISA_MODE=1 & RELP=0 & mic_op=0b110101 & REL6=0 & mic_code ; Abs26_mic1 [ ext_32_code = mic_code; ] { + delayslot( 1 ); + goto Abs26_mic1; +} + +:jal Abs26_mic1 is ISA_MODE=1 & RELP=0 & mic_op=0b111101 & REL6=0 & mic_code ; Abs26_mic1 [ ext_32_code = mic_code; ] { + ra = inst_next | 0x1; + delayslot( 1 ); + call Abs26_mic1; +} + +:jalr RTIMP^mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rs32_0 & mic_rt32_5 & RTIMP ; micb_axf=0b0000111100 & micb_poolax=0b111100 { + JXWritePC(mic_rs32_0); + mic_rt32_5 = inst_next | 0x1; + delayslot( 1 ); + call [pc]; +} + +:jalr.hb RTIMP^mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rs32_0 & mic_rt32_5 & RTIMP ; micb_axf=0b0001111100 & micb_poolax=0b111100 { + JXWritePC(mic_rs32_0); + mic_rt32_5 = inst_next | 0x1; + delayslot( 1 ); + call [pc]; +} + +:jalr16 mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=0 & mic_jalr=0b01110 & mic_rs32_0 { + JXWritePC(mic_rs32_0); + ra = inst_next | 0x1; + delayslot( 1 ); + call [pc]; +} + +:jalrs16 mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=0 & mic_jalr=0b01111 & mic_rs32_0 { + JXWritePC(mic_rs32_0); + ra = inst_next | 0x1; + delayslot( 1 ); + call [pc]; +} + +:jalrs RTIMP^mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rs32_0 & mic_rt32_5 & RTIMP ; micb_axf=0b0100111100 & micb_poolax=0b111100 { + JXWritePC(mic_rs32_0); + mic_rt32_5 = inst_next | 0x1; + delayslot( 1 ); + call [pc]; +} + +:jalrs.hb RTIMP^mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rs32_0 & mic_rt32_5 & RTIMP ; micb_axf=0b0101111100 & micb_poolax=0b111100 { + JXWritePC(mic_rs32_0); + mic_rt32_5 = inst_next | 0x1; + delayslot( 1 ); + call [pc]; +} + +:jals Abs26_mic1 is ISA_MODE=1 & RELP=0 & mic_op=0b011101 & REL6=0 & mic_code ; Abs26_mic1 [ ext_32_code = mic_code; ] { + ra = inst_next | 0x1; + delayslot( 1 ); + call Abs26_mic1; +} + +:jalx Abs26_mic2 is ISA_MODE=1 & RELP=0 & mic_op=0b111100 & REL6=0 & mic_code ; Abs26_mic2 [ ext_32_code = mic_code; ISA_MODE = 0; globalset(Abs26_mic2, ISA_MODE);] { + ra = inst_next | 0x1; + delayslot( 1 ); + ISAModeSwitch = 0; + call Abs26_mic2; +} + +:jr mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rs32_0 & mic_rt32_5=0 ; micb_axf=0b0000111100 & micb_poolax=0b111100 { + JXWritePC(mic_rs32_0); + delayslot( 1 ); + goto [pc]; +} + +:jr.hb mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rs32_0 & mic_rt32_5=0 ; micb_axf=0b0001111100 & micb_poolax=0b111100 { + JXWritePC(mic_rs32_0); + delayslot( 1 ); + goto [pc]; +} + +:jr16 mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=0 & mic_jalr=0b01100 & mic_rs32_0 { + JXWritePC(mic_rs32_0); + delayslot( 1 ); + goto [pc]; +} + +:jr16 ra is ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=0 & mic_jalr=0b01100 & mic_rs32_0=31 & ra { + JXWritePC(ra); + delayslot( 1 ); + return [pc]; +} + +:jraddiusp EXT_CODE5 is ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=0 & mic_jalr=0b11000 & EXT_CODE5 { + tmp:4 = zext(EXT_CODE5); +@if REGSIZE == "4" + sp = sp + tmp; +@else + sp_lo = sp_lo + tmp; + sp = sext(sp_lo); +@endif + JXWritePC(ra); + return [pc]; +} + +:jrc mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=0 & mic_jalr=0b01101 & mic_rs32_0 { + JXWritePC(mic_rs32_0); + goto [pc]; +} + +:jrc ra is ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=0 & mic_jalr=0b01101 & mic_rs32_0=31 & ra { + JXWritePC(ra); + return [pc]; +} + +@if ENDIAN == "big" + +:lwl mic_rt32_5, EXT_CODE12(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b0000 & EXT_CODE12 { + tmp:$(REGSIZE) = sext(EXT_CODE12); + tmp = tmp + mic_base0; + shft:$(REGSIZE) = tmp & 0x3; + addr:$(REGSIZE) = tmp - shft; + valOrig:4 = mic_rt32_5:$(SIZETO4) & (0xffffffff >> ((4-shft) * 8)); + valLoad:4 = 0; + MemSrcCast(valLoad,addr); + valLoad = valLoad << (shft * 8); + mic_rt32_5 = sext( valLoad | valOrig ); +} + +:lwle mic_rt32_5, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b0110 & micb_sub9=0b010 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + shft:$(REGSIZE) = tmp & 0x3; + addr:$(REGSIZE) = tmp - shft; + valOrig:4 = mic_rt32_5:$(SIZETO4) & (0xffffffff >> ((4-shft) * 8)); + valLoad:4 = 0; + MemSrcCast(valLoad,addr); + valLoad = valLoad << (shft * 8); + mic_rt32_5 = sext( valLoad | valOrig ); +} + +:lwr mic_rt32_5, EXT_CODE12(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b0001 & EXT_CODE12 { + tmp:$(REGSIZE) = sext(EXT_CODE12); + tmp = tmp + mic_base0; + shft:$(REGSIZE) = tmp & 0x3; + addr:$(REGSIZE) = tmp - shft; + valOrig:4 = mic_rt32_5:$(SIZETO4) & (0xffffffff << ((shft+1) * 8)); + valLoad:4 = 0; + MemSrcCast(valLoad,addr); + valLoad = valLoad >> ((3-shft) * 8); + mic_rt32_5 = sext( valOrig | valLoad ); +} + +:lwre mic_rt32_5, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b0110 & micb_sub9=0b011 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + shft:$(REGSIZE) = tmp & 0x3; + addr:$(REGSIZE) = tmp - shft; + valOrig:4 = mic_rt32_5:$(SIZETO4) & (0xffffffff << ((shft+1) * 8)); + valLoad:4 = 0; + MemSrcCast(valLoad,addr); + valLoad = valLoad >> ((3-shft) * 8); + mic_rt32_5 = sext( valOrig | valLoad ); +} + +@else + +:lwl mic_rt32_5, EXT_CODE12(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b0000 & EXT_CODE12 { + tmp:$(REGSIZE) = sext(EXT_CODE12); + tmp = tmp + mic_base0; + shft:$(REGSIZE) = tmp & 0x3; + addr:$(REGSIZE) = tmp - shft; + valOrig:4 = mic_rt32_5:$(SIZETO4) & (0xffffffff >> ((shft+1)* 8)); + valLoad:4 = 0; + MemSrcCast(valLoad,addr); + valLoad = valLoad << ((3-shft) * 8); + mic_rt32_5 = sext( valLoad | valOrig ); +} + +:lwle mic_rt32_5, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b0110 & micb_sub9=0b010 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + shft:$(REGSIZE) = tmp & 0x3; + addr:$(REGSIZE) = tmp - shft; + valOrig:4 = mic_rt32_5:$(SIZETO4) & (0xffffffff >> ((shft+1)* 8)); + valLoad:4 = 0; + MemSrcCast(valLoad,addr); + valLoad = valLoad << ((3-shft) * 8); + mic_rt32_5 = sext( valLoad | valOrig ); +} + +:lwr mic_rt32_5, EXT_CODE12(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b0001 & EXT_CODE12 { + tmp:$(REGSIZE) = sext(EXT_CODE12); + tmp = tmp + mic_base0; + shft:$(REGSIZE) = tmp & 0x3; + addr:$(REGSIZE) = tmp - shft; + valOrig:4 = mic_rt32_5:$(SIZETO4) & (0xffffffff << ((4-shft)* 8)); + valLoad:4 = 0; + MemSrcCast(valLoad,addr); + valLoad = valLoad >> (shft * 8); + mic_rt32_5 = sext( valOrig | valLoad ); +} + +:lwre mic_rt32_5, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b0110 & micb_sub9=0b011 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + shft:$(REGSIZE) = tmp & 0x3; + addr:$(REGSIZE) = tmp - shft; + valOrig:4 = mic_rt32_5:$(SIZETO4) & (0xffffffff << ((4-shft)* 8)); + valLoad:4 = 0; + MemSrcCast(valLoad,addr); + valLoad = valLoad >> (shft * 8); + mic_rt32_5 = sext( valOrig | valLoad ); +} + +@endif +# lwl and lwr almost always come in pairs. +# When the analyzer does finds a matching lwl/lwr pair, the pcode is simplified so that +# lwl does all the loading while lwr is a no-op +@if ENDIAN == "big" +:lwl mic_rt32_5, EXT_CODE12(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 & PAIR_INSTRUCTION_FLAG=1 ; micb_func12=0b0000 & EXT_CODE12 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] { + tmp:$(REGSIZE) = sext(EXT_CODE12); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt32_5 = sext( *[ram]:4 tmpa ); +} +:lwr mic_rt32_5, EXT_CODE12(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 & PAIR_INSTRUCTION_FLAG=1 ; micb_func12=0b0001 & EXT_CODE12 [ PAIR_INSTRUCTION_FLAG = 0; ] { +} +@else +:lwl mic_rt32_5, EXT_CODE12(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 & PAIR_INSTRUCTION_FLAG=1 ; micb_func12=0b0000 & EXT_CODE12 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] { +} +:lwr mic_rt32_5, EXT_CODE12(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 & PAIR_INSTRUCTION_FLAG=1 ; micb_func12=0b0001 & EXT_CODE12 [ PAIR_INSTRUCTION_FLAG = 0; ] { + tmp:$(REGSIZE) = sext(EXT_CODE12); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt32_5 = sext( *[ram]:4 tmpa ); +} +@endif + + + +:lwxc1 micb_fd, mic_index(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_index & mic_base0 ; micb_fd & micb_fxf2=0b00001001000 { + tmpa:$(REGSIZE) = mic_index + mic_base0; + tmpb:$(ADDRSIZE) = 0; + ValCast(tmpb,tmpa); + tmp:4 = *[ram]:4 tmpb; + micb_fd = (micb_fd ^ 0xffffffff) + zext(tmp); +} + +:madd RS0L, RT5L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & RT5L & RS0L ; micb_poolax=0b111100 & micb_axf=0b1100101100 { + tmp1:8 = sext(RS0L); + tmp2:8 = sext(RT5L); + prod:8 = tmp1 * tmp2; + lo = lo & 0xffffffff; # Make sure any upper bits of lo don't contribute to sum + sum:8 = (zext(hi) << 32) + zext(lo) + prod; + lo = sext(sum:4); + sum = sum >> 32; + hi = sext(sum:4); +} + +:madd.S micb_fd, micb_fr, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 ; micb_fd & micb_fr & micb_poolfx=0b000001 { + fd_tmp:4 = (mic_fs:4 f* mic_ft_5:4) f+ micb_fr:4; + micb_fd = zext(fd_tmp); +} + +:madd.D micb_fd, micb_fr, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_ftD_5 & mic_fsD; micb_fd & micb_fdD & micb_fr &micb_frD & micb_poolfx=0b001001 { + micb_fdD = (mic_fsD f* mic_ftD_5) f+ micb_frD; +} + +:madd.PS micb_fd, micb_fr, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_ftD_5 & mic_fsD ; micb_fd & micb_fdD & micb_fr & micb_poolfx=0b010001 { + micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:maddu RS0L, RT5L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & RT5L & RS0L ; micb_poolax=0b111100 & micb_axf=0b1101101100 { + tmp1:8 = zext(RS0L); + tmp2:8 = zext(RT5L); + prod:8 = tmp1 * tmp2; + lo = lo & 0xffffffff; # Make sure any upper bits of lo don't contribute to sum + sum:8 = (zext(hi) << 32) + zext(lo) + prod; + lo = sext(sum:4); + sum = sum >> 32; + hi = sext(sum:4); +} + +:mfhi mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rt32_5=0 & mic_rs32_0 ; micb_poolax=0b111100 & micb_axf=0b0000110101 { + mic_rs32_0 = hi; +} + +:mfhi16 mic_rd32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=0 & mic_sub2=0b10000 & mic_rd32_0 { + mic_rd32_0 = hi; +} + +:mflo mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rt32_5=0 & mic_rs32_0 ; micb_poolax=0b111100 & micb_axf=0b0001110101 { + mic_rs32_0 = lo; +} + +:mflo16 mic_rd32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=0 & mic_sub2=0b10010 & mic_rd32_0 { + mic_rd32_0 = lo; +} + +:mov.PS mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_ftD_5 & mic_fsD ; micb_bit15=0 & micb_fmt=2 & micb_poolfx=0b111011 & micb_flt6=0b0000001 { + mic_ftD_5 = mipsFloatPS(mic_fsD); +} + +:movf mic_rt32_5, mic_rs32_0, micb_cc is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_rs32_0 & mic_rt32_5 ; micb_cc & micb_poolfx=0b111011 & micb_flt6=0b0000101 { + tmp:1 = fcsr[23,1]; # was getFpCondition(cc:1); + if (tmp != 0) goto ; + mic_rt32_5 = mic_rs32_0; + +} + +:movf.S mic_ft_5, mic_fs, micb_cc is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 ; micb_cc & micb_fmt9=0 & micb_z11=0 & micb_fxf5=0b000100000 { + tmp:1 = fcsr[23,1]; # was getFpCondition(cc:1); + if (tmp != 0) goto ; + fs_tmp:4 = mic_fs:4; + mic_ft_5 = zext(fs_tmp); + +} + +:movf.D mic_ft_5, mic_fs, micb_cc is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_cc & micb_fmt9=1 & micb_z11=0 & micb_fxf5=0b000100000 { + tmp:1 = fcsr[23,1]; # was getFpCondition(cc:1); + if (tmp != 0) goto ; + mic_ftD_5 = mic_fsD; + +} + +:movf.PS mic_ft_5, mic_fs, micb_cc is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_ftD_5 & mic_fsD ; micb_cc & micb_fmt9=2 & micb_z11=0 & micb_fxf5=0b000100000 { + mic_ftD_5 = mipsFloatPS(mic_fsD); +} + + +:movn micb_rd32, mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0000011000 & micb_bit10=0 & micb_rd32 { + if (mic_rt32_5 == 0) goto ; + micb_rd32 = mic_rs32_0; + +} + +:movn.S micb_fd, mic_fs, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_rt32_5 & mic_fs ; micb_fd & micb_bit10=0 & micb_fmt8=0 & micb_fxf3=0b00111000 { + if (mic_rt32_5 == 0) goto ; + fs_tmp:4 = mic_fs:4; + micb_fd = zext(fs_tmp); + +} + +:movn.D micb_fd, mic_fs, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_rt32_5 & mic_fs & mic_fsD ; micb_fdD & micb_fd & micb_bit10=0 & micb_fmt8=1 & micb_fxf3=0b00111000 { + if (mic_rt32_5 == 0) goto ; + micb_fdD = mic_fsD; + +} + +:movn.PS micb_fd, mic_fs, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_rt32_5 & mic_fs & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_bit10=0 & micb_fmt8=2 & micb_fxf3=0b00111000 { + micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:movt mic_rt32_5, mic_rs32_0, micb_cc is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_rs32_0 & mic_rt32_5 ; micb_cc & micb_poolfx=0b111011 & micb_flt6=0b0100101 { + tmp:1 = fcsr[23,1]; # was getFpCondition(cc:1); + if (tmp == 0) goto ; + mic_rt32_5 = mic_rs32_0; + +} + +:movt.S mic_ft_5, mic_fs, micb_cc is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 ; micb_cc & micb_fmt9=0 & micb_z11=0 & micb_fxf5=0b001100000 { + tmp:1 = fcsr[23,1]; # was getFpCondition(cc:1); + if (tmp == 0) goto ; + fs_tmp:4 = mic_fs:4; + mic_ft_5 = zext(fs_tmp); + +} + +:movt.D mic_ft_5, mic_fs, micb_cc is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5; micb_cc & micb_fmt9=1 & micb_z11=0 & micb_fxf5=0b001100000 { + tmp:1 = fcsr[23,1]; # was getFpCondition(cc:1); + if (tmp == 0) goto ; + mic_ftD_5 = mic_fsD; + +} + +:movt.PS mic_ft_5, mic_fs, micb_cc is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_ftD_5 & mic_fsD ; micb_cc & micb_fmt9=2 & micb_z11=0 & micb_fxf5=0b001100000 { + mic_ftD_5 = mipsFloatPS(mic_fsD); +} + +:movz micb_rd32, mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0001011000 & micb_bit10=0 & micb_rd32 { + if (mic_rt32_5 != 0) goto ; + micb_rd32 = mic_rs32_0; + +} + +:movz.S micb_fd, mic_fs, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_rt32_5 & mic_fs ; micb_fd & micb_bit10=0 & micb_fmt8=0 & micb_fxf3=0b01111000 { + if (mic_rt32_5 != 0) goto ; + fs_tmp:4 = mic_fs:4; + micb_fd = zext(fs_tmp); + +} + +:movz.D micb_fd, mic_fs, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_rt32_5 & mic_fs & mic_fsD ; micb_fdD & micb_fd & micb_bit10=0 & micb_fmt8=1 & micb_fxf3=0b01111000 { + if (mic_rt32_5 != 0) goto ; + micb_fdD = mic_fsD; + +} + +:movz.PS micb_fd, mic_fs, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_rt32_5 & mic_fs & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_bit10=0 & micb_fmt8=2 & micb_fxf3=0b01111000 { + micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:msub RS0L, RT5L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & RT5L & RS0L ; micb_poolax=0b111100 & micb_axf=0b1110101100 { + tmp1:8 = sext(RS0L); + tmp2:8 = sext(RT5L); + prod:8 = tmp1 * tmp2; + lo = lo & 0xffffffff; # Make sure any upper bits of lo don't contribute to sum + sum:8 = (zext(hi) << 32) + zext(lo) - prod; + lo = sext(sum:4); + sum = sum >> 32; + hi = sext(sum:4); +} + +:msub.S micb_fd, micb_fr, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 ; micb_fd & micb_fr & micb_poolfx=0b100001 { + fd_tmp:4 = (mic_fs:4 f* mic_ft_5:4) f- micb_fr:4; + micb_fd = zext(fd_tmp); +} + +:msub.D micb_fd, micb_fr, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5; micb_fdD & micb_frD & micb_fd & micb_fr & micb_poolfx=0b101001 { + micb_fdD = (mic_fsD f* mic_ftD_5) f- micb_frD; +} + +:msub.PS micb_fd, micb_fr, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_fr & micb_poolfx=0b110001 { + micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:msubu RS0L, RT5L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & RT5L & RS0L ; micb_poolax=0b111100 & micb_axf=0b1111101100 { + tmp1:8 = zext(RS0L); + tmp2:8 = zext(RT5L); + prod:8 = tmp1 * tmp2; + lo = lo & 0xffffffff; # Make sure any upper bits of lo don't contribute to sum + sum:8 = (zext(hi) << 32) + zext(lo) - prod; + lo = sext(sum:4); + sum = sum >> 32; + hi = sext(sum:4); +} + +:mthi mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rt32_5=0 & mic_rs32_0 ; micb_poolax=0b111100 & micb_axf=0b0010110101 { + hi = mic_rs32_0; +} + +:mtlo mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rt32_5=0 & mic_rs32_0 ; micb_poolax=0b111100 & micb_axf=0b0011110101 { + lo = mic_rs32_0; +} + +:mul.PS micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_bit10=0 & micb_fmt8=2 & micb_fxf3=0b10110000 { + micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:mult RS0L, RT5L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & RT5L & RS0L ; micb_poolax=0b111100 & micb_axf=0b1000101100 { + tmps:8 = sext(RS0L); + tmpt:8 = sext(RT5L); + tmpr:8= tmps * tmpt; + lo = sext(tmpr[0,32]); + hi = sext(tmpr[32,32]); +} + +:multu RS0L, RT5L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & RT5L & RS0L ; micb_poolax=0b111100 & micb_axf=0b1001101100 { + tmps:8 = zext(RS0L); + tmpt:8 = zext(RT5L); + tmpr:8= tmps * tmpt; + lo = sext(tmpr[0,32]); + hi = sext(tmpr[32,32]); +} + +:neg.PS mic_ft_5, mic_fs is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_ft_5 & mic_fs & mic_ftD_5 & mic_fsD ; micb_bit15=0 & micb_fmt=2 & micb_poolfx=0b111011 & micb_flt6=0b0101101 { + mic_ftD_5 = mipsFloatPS(mic_fsD); +} + +:pll.PS micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_fxf2=0b00010000000 { + micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:plu.PS micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_fxf2=0b00011000000 { + micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:prefx micb_hint, mic_index(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_index & mic_base0 ; micb_axf2=0b0110100000 & micb_bit10=0 & micb_hint { + tmp:$(REGSIZE) = mic_index + mic_base0; + prefetch(tmp,micb_hint:1); +} + +:pul.PS micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_fxf2=0b00100000000 { + micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:puu.PS micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_fxf2=0b00101000000 { + micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +:rdhwr mic_rt32_5, mic_rs32_hw is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=0 & mic_rt32_5 & mic_rs32_hw ; micb_poolax=0b111100 & micb_axf=0b0110101100 { + mic_rt32_5 = getHWRegister(mic_rs32_hw); +} + +:sub.PS micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & mic_ft_5 & mic_fs & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_bit10=0 & micb_fmt8=2 & micb_fxf3=0b01110000 { + micb_fdD = mipsFloatPS(mic_fsD, mic_ftD_5); +} + +@if ENDIAN == "big" + +:swl mic_rt32_5, EXT_CODE12(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b1000 & EXT_CODE12 { + tmp:$(REGSIZE) = sext(EXT_CODE12); + tmp = tmp + mic_base0; + tmpRT:4 = mic_rt32_5:$(SIZETO4); + shft:$(REGSIZE) = tmp & 0x3; + addr:$(REGSIZE) = tmp - shft; + valOrig:4 = 0; + MemSrcCast(valOrig,addr); + valOrig = valOrig & (0xffffffff << ((4-shft) * 8)); + valStore:4 = (tmpRT >> (shft * 8)) | valOrig; + MemDestCast(addr,valStore); +} + +:swle mic_rt32_5, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b1010 & micb_sub9=0b000 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + tmpRT:4 = mic_rt32_5:$(SIZETO4); + shft:$(REGSIZE) = tmp & 0x3; + addr:$(REGSIZE) = tmp - shft; + valOrig:4 = 0; + MemSrcCast(valOrig,addr); + valOrig = valOrig & (0xffffffff << ((4-shft) * 8)); + valStore:4 = (tmpRT >> (shft * 8)) | valOrig; + MemDestCast(addr,valStore); +} + +:swr mic_rt32_5, EXT_CODE12(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b1001 & EXT_CODE12 { + tmp:$(REGSIZE) = sext(EXT_CODE12); + tmp = tmp + mic_base0; + tmpRT:4 = mic_rt32_5:$(SIZETO4); + shft:$(REGSIZE) = tmp & 0x3; + addr:$(REGSIZE) = tmp - shft; + valOrig:4 = 0; + MemSrcCast(valOrig,addr); + valOrig = valOrig & (0xffffffff >> ((shft+1) * 8)); + valStore:4 = (tmpRT << ((3-shft)*8)) | valOrig; + MemDestCast(addr,valStore); +} + +:swre mic_rt32_5, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b1010 & micb_sub9=0b001 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + tmpRT:4 = mic_rt32_5:$(SIZETO4); + shft:$(REGSIZE) = tmp & 0x3; + addr:$(REGSIZE) = tmp - shft; + valOrig:4 = 0; + MemSrcCast(valOrig,addr); + valOrig = valOrig & (0xffffffff >> ((shft+1) * 8)); + valStore:4 = (tmpRT << ((3-shft)*8)) | valOrig; + MemDestCast(addr,valStore); +} + +@else + +:swl mic_rt32_5, EXT_CODE12(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b1000 & EXT_CODE12 { + tmp:$(REGSIZE) = sext(EXT_CODE12); + tmp = tmp + mic_base0; + tmpRT:4 = mic_rt32_5:$(SIZETO4); + shft:$(REGSIZE) = tmp & 0x3; + addr:$(REGSIZE) = tmp - shft; + valOrig:4 = 0; + MemSrcCast(valOrig,addr); + valOrig = valOrig & (0xffffffff << ((shft+1) * 8)); + valStore:4 = (tmpRT >> ((3-shft) * 8)) | valOrig; + MemDestCast(addr,valStore); +} + +:swle mic_rt32_5, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b1010 & micb_sub9=0b000 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + tmpRT:4 = mic_rt32_5:$(SIZETO4); + shft:$(REGSIZE) = tmp & 0x3; + addr:$(REGSIZE) = tmp - shft; + valOrig:4 = 0; + MemSrcCast(valOrig,addr); + valOrig = valOrig & (0xffffffff << ((shft+1) * 8)); + valStore:4 = (tmpRT >> ((3-shft) * 8)) | valOrig; + MemDestCast(addr,valStore); +} + +:swr mic_rt32_5, EXT_CODE12(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b1001 & EXT_CODE12 { + tmp:$(REGSIZE) = sext(EXT_CODE12); + tmp = tmp + mic_base0; + tmpRT:4 = mic_rt32_5:$(SIZETO4); + shft:$(REGSIZE) = tmp & 0x3; + addr:$(REGSIZE) = tmp - shft; + valOrig:4 = 0; + MemSrcCast(valOrig,addr); + valOrig = valOrig & (0xffffffff >> ((4-shft) * 8)); + valStore:4 = (tmpRT << (shft*8)) | valOrig; + MemDestCast(addr,valStore); +} + +:swre mic_rt32_5, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 ; micb_func12=0b1010 & micb_sub9=0b001 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + tmpRT:4 = mic_rt32_5:$(SIZETO4); + shft:$(REGSIZE) = tmp & 0x3; + addr:$(REGSIZE) = tmp - shft; + valOrig:4 = 0; + MemSrcCast(valOrig,addr); + valOrig = valOrig & (0xffffffff >> ((4-shft) * 8)); + valStore:4 = (tmpRT << (shft*8)) | valOrig; + MemDestCast(addr,valStore); +} + +@endif +# When the analyzer finds a matching swl/swr pair, the pcode is simplified so that +# swl does all the storing while swr is a no-op +@if ENDIAN == "big" +:swl mic_rt32_5, EXT_CODE12(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 & PAIR_INSTRUCTION_FLAG=1 ; micb_func12=0b1000 & EXT_CODE12 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] { + tmp:$(REGSIZE) = sext(EXT_CODE12); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:4 tmpa = mic_rt32_5:$(SIZETO4); +} +:swr mic_rt32_5, EXT_CODE12(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 & PAIR_INSTRUCTION_FLAG=1 ; micb_func12=0b1001 & EXT_CODE12 [ PAIR_INSTRUCTION_FLAG = 0; ] { +} +@else +:swl mic_rt32_5, EXT_CODE12(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 & PAIR_INSTRUCTION_FLAG=1 ; micb_func12=0b1000 & EXT_CODE12 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] { +} +:swr mic_rt32_5, EXT_CODE12(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=0 & mic_rt32_5 & mic_base0 & PAIR_INSTRUCTION_FLAG=1 ; micb_func12=0b1001 & EXT_CODE12 [ PAIR_INSTRUCTION_FLAG = 0; ] { + tmp:$(REGSIZE) = sext(EXT_CODE12); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:4 tmpa = mic_rt32_5:$(SIZETO4); +} +@endif + +:sdxc1 micb_fd, mic_index(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_index & mic_base0 ; micb_fd & micb_fdD & micb_fxf2=0b00100001000 { + tmp:$(REGSIZE) = mic_index + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:8 tmpa = micb_fdD; +} + +:swxc1 micb_fd, mic_index(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_index & mic_base0 ; micb_fd & micb_fxf2=0b00010001000 { + tmp:$(REGSIZE) = mic_index + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:4 tmpa = micb_fd:4; +} + +:teqi mic_rs32_0, EXT_MS16 is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_funci=0b01110 & mic_rs32_0 ; EXT_MS16 { + tmp:$(REGSIZE) = sext(EXT_MS16); + if (mic_rs32_0 != tmp) goto ; + trap(); + +} + +:tgei mic_rs32_0, EXT_MS16 is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_funci=0b01001 & mic_rs32_0 ; EXT_MS16 { + tmp:$(REGSIZE) = sext(EXT_MS16); + if (tmp s< mic_rs32_0) goto ; + trap(); + +} + +:tgeiu mic_rs32_0, EXT_MS16 is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_funci=0b01011 & mic_rs32_0 ; EXT_MS16 { + tmp:$(REGSIZE) = sext(EXT_MS16); + if (tmp < mic_rs32_0) goto ; + trap(); + +} + +:tlti mic_rs32_0, EXT_MS16 is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_funci=0b01000 & mic_rs32_0 ; EXT_MS16 { + tmp:$(REGSIZE) = sext(EXT_MS16); + if (tmp s>= mic_rs32_0) goto ; + trap(); + +} + +:tltiu mic_rs32_0, EXT_MS16 is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_funci=0b01010 & mic_rs32_0 ; EXT_MS16 { + tmp:$(REGSIZE) = sext(EXT_MS16); + if (tmp >= mic_rs32_0) goto ; + trap(); + +} + +:tnei mic_rs32_0, EXT_MS16 is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=0 & mic_funci=0b01100 & mic_rs32_0 ; EXT_MS16 { + tmp:$(REGSIZE) = sext(EXT_MS16); + if (mic_rs32_0 == tmp) goto ; + trap(); + +} + +@ifdef MIPS64 +:ddiv mic_rt32_5, mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=0 & mic_rs32_0 & mic_rt32_5 ; micb_poolax=0b111100 & micb_axf=0b1010101100 { + lo = mic_rs32_0 s/ mic_rt32_5; + hi = mic_rs32_0 s% mic_rt32_5; +} + +:ddivu mic_rt32_5, mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=0 & mic_rs32_0 & mic_rt32_5 ; micb_poolax=0b111100 & micb_axf=0b1011101100 { + lo = mic_rs32_0 / mic_rt32_5; + hi = mic_rs32_0 % mic_rt32_5; +} + +:luxc1 micb_fd, mic_index(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_index & mic_base0 ; micb_fd & micb_fxf2=0b00101001000 { + tmp:$(REGSIZE) = mic_index + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + ptr:$(ADDRSIZE) = tmpa; + micb_fd = *[ram]:8 ptr; +} + + +@endif + +#### +# +# Release 6 semantics +# +#### +:align micb_rd32, RS0L, RT5L, micb_bp is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & RT5L & RS0L ; micb_poolax=0b011111 & micb_z68=0 & micb_rd32 & micb_bp { + tmp:4 = RT5L << (8 * micb_bp); + tmp = tmp | (RS0L >> (32 - (8 * micb_bp))); + micb_rd32 = sext(tmp); +} + +:aluipc mic_rt32_5, EXT_MS32 is ISA_MODE=1 & RELP=0 & mic_op=0b011110 & REL6=1 & mic_pcf=0b11111 & mic_rt32_5 ; EXT_MS32 { + tmp:$(REGSIZE) = sext(EXT_MS32); + tmp = tmp + inst_start; + tmp = tmp & ~0xFFFF; + mic_rt32_5 = tmp; +} + +:aui mic_rt32_5, RS0L, EXT_MS32 is ISA_MODE=1 & RELP=0 & mic_op=0b000100 & REL6=1 & mic_rt32_5 & RS0L ; EXT_MS32 { + tmp:4 = RS0L + EXT_MS32; + mic_rt32_5 = sext(tmp); +} + +:auipc mic_rt32_5, EXT_MS32 is ISA_MODE=1 & RELP=0 & mic_op=0b011110 & REL6=1 & mic_pcf=0b11110 & mic_rt32_5 ; EXT_MS32 { + tmp:$(REGSIZE) = sext(EXT_MS32); + tmp = tmp + inst_start; + mic_rt32_5 = tmp; +} + +# Check this. Says left shift by 1 bit, but then says 4 byte alligned. BC instruction is simlar though it says left shift by 2 bits. +# Either way, there is a mistake in the documentation +:balc Rel26_mic is ISA_MODE=1 & RELP=0 & mic_op=0b101101 & REL6=1 ; Rel26_mic { + ra = inst_next | 0x1; + call Rel26_mic; +} + +:bc Rel26_mic is ISA_MODE=1 & RELP=0 & mic_op=0b100101 & REL6=1 ; Rel26_mic { + goto Rel26_mic; +} + +:bc16 Rel10_mic is ISA_MODE=1 & RELP=0 & mic_op=0b110011 & REL6=1 & Rel10_mic { + goto Rel10_mic; +} + +:bc1eqzc mic_ft_0, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=1 & mic_funci=0b01000 & mic_ft_0; Rel16_mic { + tmp:1 = mic_ft_0[0,8] & 0x01; # Only need to check the LSB + if (tmp == 0x00) goto Rel16_mic; +} + +:bc1nezc mic_ft_0, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=1 & mic_funci=0b01001 & mic_ft_0; Rel16_mic { + tmp:1 = mic_ft_0[0,8] & 0x01; # Only need to check the LSB + if (tmp == 0x01) goto Rel16_mic; +} + +:bc2eqzc mic_ct, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=1 & mic_funci=0b01010 & mic_ct; Rel16_mic { + tmp:1 = getCopCondition(2:1, mic_ct:1); + if (tmp == 0) goto inst_next; + goto Rel16_mic; +} + +:bc2nezc mic_ct, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=1 & mic_funci=0b01011 & mic_ct; Rel16_mic { + tmp:1 = getCopCondition(2:1, mic_ct:1); + if (tmp == 1) goto inst_next; + goto Rel16_mic; +} + +:beqzc16 mic_rs7, Rel7_mic is ISA_MODE=1 & RELP=0 & mic_op=0b100011 & REL6=1 & mic_rs7 & Rel7_mic { + if (mic_rs7 == 0) goto Rel7_mic; +} + +:bnezc16 mic_rs7, Rel7_mic is ISA_MODE=1 & RELP=0 & mic_op=0b101011 & REL6=1 & mic_rs7 & Rel7_mic { + if (mic_rs7 != 0) goto Rel7_mic; +} + +# Some of the branch instructions have a != in the pattern description in mips documentation. +# In order to avoid pattern blowup in sleigh, I use some fake instructions as sinks when possible. +# It was not possible to avoid all instances of != in the constructors +:bad1 is ISA_MODE=1 & RELP=0 & mic_op=0b110000 & REL6=1 & mic_code=0; Rel16_mic unimpl +:blezalc mic_rt32_5, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b110000 & REL6=1 & mic_rs32_0=0 & mic_rt32_5; Rel16_mic { + if (mic_rt32_5 s> 0) goto inst_next; + ra = inst_next | 0x1; + call Rel16_mic; +} + +:bgezalc mic_rt32_5, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b110000 & REL6=1 & mic_rt32_5 & mic_rt32_5=mic_rs32_0 & mic_rt32_5a!=0; Rel16_mic { + if (mic_rt32_5 s< 0) goto inst_next; + ra = inst_next | 0x1; + call Rel16_mic; +} + +:bgeuc mic_rs32_0,mic_rt32_5,Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b110000 & REL6=1 & mic_rt32_5 & mic_rs32_0; Rel16_mic { + if (mic_rs32_0 >= mic_rt32_5) goto Rel16_mic; +} + +:bad2 is ISA_MODE=1 & RELP=0 & mic_op=0b111000 & REL6=1 & mic_code=0; Rel16_mic unimpl +:bgtzalc mic_rt32_5, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b111000 & REL6=1 & mic_rs32_0=0 & mic_rt32_5; Rel16_mic { + if (mic_rt32_5 s<= 0) goto inst_next; + ra = inst_next | 0x1; + call Rel16_mic; +} + +:bltzalc mic_rt32_5, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b111000 & REL6=1 & mic_rt32_5 & mic_rt32_5=mic_rs32_0 & mic_rt32_5a!=0; Rel16_mic { + if (mic_rt32_5 s>= 0) goto inst_next; + ra = inst_next | 0x1; + call Rel16_mic; +} +:bltuc mic_rs32_0,mic_rt32_5,Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b111000 & REL6=1 & mic_rt32_5 & mic_rs32_0; Rel16_mic { + if (mic_rs32_0 < mic_rt32_5) goto Rel16_mic; +} + +# for this case, bovc is the catch-all. +:beqzalc mic_rt32_5, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b011101 & REL6=1 & mic_rs32_0=0 & mic_rt32_5 & mic_rt32_5a!=0; Rel16_mic { + if (mic_rt32_5 != 0) goto inst_next; + ra = inst_next | 0x1; + call Rel16_mic; +} + +:beqc mic_rs32_0, mic_rt32_5, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b011101 & REL6=1 & mic_rt32_5 & mic_rs32_0 & mic_rs32_0a!=0 & mic_rs32_0b 0x7FFFFFFF) || (tmpS s< -2147483648); +@if REGSIZE == "8" + tmpF = tmpF || (mic_rt32_5 s> 0x7FFFFFFF) || (mic_rt32_5 s< -2147483648) || (mic_rs32_0 s> 0x7FFFFFFF) || (mic_rs32_0 s< -2147483648); +@endif + if (tmpF == 1) goto Rel16_mic; +} + +# for this case, bnvc is the catch-all. +:bnezalc mic_rt32_5, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b011111 & REL6=1 & mic_rs32_0=0 & mic_rt32_5 & mic_rt32_5a!=0; Rel16_mic { + if (mic_rt32_5 == 0) goto inst_next; + ra = inst_next | 0x1; + call Rel16_mic; +} + +:bnec mic_rs32_0, mic_rt32_5, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b011111 & REL6=1 & mic_rt32_5 & mic_rs32_0 & mic_rs32_0a!=0 & mic_rs32_0b 0x7FFFFFFF) || (tmpS s< -2147483648); +@if FREGSIZE == "8" + tmpF = tmpF || (mic_rt32_5 s> 0x7FFFFFFF) || (mic_rt32_5 s< -2147483648) || (mic_rs32_0 s> 0x7FFFFFFF) || (mic_rs32_0 s< -2147483648); +@endif + if (tmpF == 0) goto Rel16_mic; +} + +:bad3 is ISA_MODE=1 & RELP=0 & mic_op=0b111001 & REL6=1 & mic_code=0; Rel16_mic unimpl +:blezc mic_rt32_5, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b111001 & REL6=1 & mic_rs32_0=0 & mic_rt32_5; Rel16_mic { + if (mic_rt32_5 s<= 0) goto Rel16_mic; +} + +:bgezc mic_rt32_5, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b111001 & REL6=1 & mic_rt32_5 & mic_rt32_5=mic_rs32_0 & mic_rt32_5a!=0; Rel16_mic { + if (mic_rt32_5 s>= 0) goto Rel16_mic; +} + +:bgec mic_rs32_0,mic_rt32_5,Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b111001 & REL6=1 & mic_rt32_5 & mic_rs32_0; Rel16_mic { + if (mic_rs32_0 s>= mic_rt32_5) goto Rel16_mic; +} + +:bad4 is ISA_MODE=1 & RELP=0 & mic_op=0b110001 & REL6=1 & mic_code=0; Rel16_mic unimpl +:bgtzc mic_rt32_5, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b110001 & REL6=1 & mic_rs32_0=0 & mic_rt32_5; Rel16_mic { + if (mic_rt32_5 s> 0) goto Rel16_mic; +} + +:bltzc mic_rt32_5, Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b110001 & REL6=1 & mic_rt32_5 & mic_rt32_5=mic_rs32_0 & mic_rt32_5a!=0; Rel16_mic { + if (mic_rt32_5 s< 0) goto Rel16_mic; +} + +:bltc mic_rs32_0,mic_rt32_5,Rel16_mic is ISA_MODE=1 & RELP=0 & mic_op=0b110001 & REL6=1 & mic_rt32_5 & mic_rs32_0; Rel16_mic { + if (mic_rs32_0 s< mic_rt32_5) goto Rel16_mic; +} + +:beqzc mic_rs32_5, Rel21_mic is ISA_MODE=1 & RELP=0 & mic_op=0b100000 & REL6=1 & mic_rs32_5 & mic_imm5; Rel21_mic [ext_32_imm5 = mic_imm5;] { + if (mic_rs32_5 == 0) goto Rel21_mic; +} + +:bad6 is ISA_MODE=1 & RELP=0 & mic_op=0b10100 & REL6=1 & mic_rs32_5=0; Rel21_mic unimpl +:bnezc mic_rs32_5, Rel21_mic is ISA_MODE=1 & RELP=0 & mic_op=0b10100 & REL6=1 & mic_rs32_5 & mic_imm5; Rel21_mic [ext_32_imm5 = mic_imm5;] { + if (mic_rs32_5 != 0) goto Rel21_mic; +} + +:bitswap mic_rd32_0, RT5L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & RT5L & mic_rd32_0 ; micb_poolax=0b111100 & micb_axf3=0b101100 & micb_z12=0 { + tmp:4 = bitSwap(RT5L); + mic_rd32_0 = sext(tmp); +} + +:cache mic_cop5, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b001000 & REL6=1 & mic_cop5 & mic_base0 ; micb_func12=0b0110 & micb_sub9=0 & EXT_CODE9E { + cacheOp(); +} + +:class.S mic_fd, mic_fs_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs_5 & mic_fd ; micb_size=0 & micb_fmt9=0 & micb_fxf5=0b001100000 { + tmp_fs:4 = mic_fs_5:4; # Get just the 4 byte single floating point value + tmp_exponent:4 = zext(tmp_fs[23,8]); + tmp_fraction:4 = zext(tmp_fs[0,23]); + tmp_sign:4 = zext(tmp_fs[31,1]); + tmp_b1:4 = zext(tmp_fs[22,1]); # High order bit of fraction, used for NaN + + tmp_SNaN:4 = zext((tmp_exponent == 0x0ff) && (tmp_fraction != 0x0) && (tmp_b1 == 0x0)); + tmp_QNaN:4 = zext((tmp_exponent == 0x0ff) && (tmp_fraction != 0x0) && (tmp_b1 == 0x01)); + tmp_Neg_Infinity:4 = zext((tmp_sign == 0x01) && (tmp_exponent == 0x0ff) && (tmp_fraction == 0x0)); + tmp_Neg_Normal:4 = zext((tmp_sign == 0x01) && (tmp_exponent != 0x0) && (tmp_exponent != 0x0ff)); + tmp_Neg_Subnormal:4 = zext((tmp_sign == 0x01) && (tmp_exponent == 0x0) && (tmp_fraction != 0x0)); + tmp_Neg_Zero:4 = zext((tmp_sign == 0x01) && (tmp_exponent == 0x0) && (tmp_fraction == 0x0)); + tmp_Pos_Infinity:4 = zext((tmp_sign == 0x0) && (tmp_exponent == 0x0ff) && (tmp_fraction == 0x0)); + tmp_Pos_Normal:4 = zext((tmp_sign == 0x0) && (tmp_exponent != 0x0) && (tmp_exponent != 0x0ff)); + tmp_Pos_Subnormal:4 = zext((tmp_sign == 0x0) && (tmp_exponent == 0x0) && (tmp_fraction != 0x0)); + tmp_Pos_Zero:4 = zext((tmp_sign == 0x0) && (tmp_exponent == 0x0) && (tmp_fraction == 0x0)); + + tmp_fd:4 = 0; + tmp_fd = tmp_SNaN | (tmp_QNaN << 1) | (tmp_Neg_Infinity << 2) | (tmp_Neg_Normal << 3) | + (tmp_Neg_Subnormal << 4) | (tmp_Neg_Zero << 5) | (tmp_Pos_Infinity << 6) | + (tmp_Pos_Normal << 7) | (tmp_Pos_Subnormal << 8) | (tmp_Pos_Zero << 9); + + mic_fd = zext(tmp_fd); +} + +:class.D mic_fd, mic_fs_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs_5 & mic_fd & mic_fsD_5 & mic_fdD ; micb_size=0 & micb_fmt9=1 & micb_fxf5=0b001100000 { + tmp_fs:8 = mic_fsD_5; + tmp_sign:4 = zext(tmp_fs[63,1]); + tmp_exponent:4 = zext(tmp_fs[52,11]); + tmp_fraction:8 = zext(tmp_fs[0,51]); + tmp_b1:4 = zext(tmp_fs[51,1]); # High order bit of fraction, used for NaN + + tmp_SNaN:4 = zext((tmp_exponent == 0x07ff) && (tmp_fraction != 0x0) && (tmp_b1 == 0x0)); + tmp_QNaN:4 = zext((tmp_exponent == 0x07ff) && (tmp_fraction != 0x0) && (tmp_b1 == 0x01)); + tmp_Neg_Infinity:4 = zext((tmp_sign == 0x01) && (tmp_exponent == 0x07ff) && (tmp_fraction == 0x0)); + tmp_Neg_Normal:4 = zext((tmp_sign == 0x01) && (tmp_exponent != 0x0) && (tmp_exponent != 0x07ff)); + tmp_Neg_Subnormal:4 = zext((tmp_sign == 0x01) && (tmp_exponent == 0x0) && (tmp_fraction != 0x0)); + tmp_Neg_Zero:4 = zext((tmp_sign == 0x01) && (tmp_exponent == 0x0) && (tmp_fraction == 0x0)); + tmp_Pos_Infinity:4 = zext((tmp_sign == 0x0) && (tmp_exponent == 0x07ff) && (tmp_fraction == 0x0)); + tmp_Pos_Normal:4 = zext((tmp_sign == 0x0) && (tmp_exponent != 0x0) && (tmp_exponent != 0x07ff)); + tmp_Pos_Subnormal:4 = zext((tmp_sign == 0x0) && (tmp_exponent == 0x0) && (tmp_fraction != 0x0)); + tmp_Pos_Zero:4 = zext((tmp_sign == 0x0) && (tmp_exponent == 0x0) && (tmp_fraction == 0x0)); + + tmp_fd:4 = 0; + tmp_fd = tmp_SNaN | (tmp_QNaN << 1) | (tmp_Neg_Infinity << 2) | (tmp_Neg_Normal << 3) | + (tmp_Neg_Subnormal << 4) | (tmp_Neg_Zero << 5) | (tmp_Pos_Infinity << 6) | + (tmp_Pos_Normal << 7) | (tmp_Pos_Subnormal << 8) | (tmp_Pos_Zero << 9); + + mic_fdD = zext(tmp_fd); +} + +#:cmp.condn.fmt +:cmp.af.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x00 & micb_poolfx=0b000101 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN + micb_fd = 0x0; +} + +:cmp.af.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x00 & micb_poolfx=0b010101 { + trapIfSNaN(mic_fsD, mic_ftD_5); + micb_fdD = 0x0; +} + +:cmp.un.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x01 & micb_poolfx=0b000101 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN + micb_fd = sext((nan(mic_fs:4) || nan(mic_ft_5:4)) * 0xff); +} + +:cmp.un.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_cond2=0x01 & micb_poolfx=0b010101 { + trapIfSNaN(mic_fsD, mic_ftD_5); + micb_fdD = sext((nan(mic_fsD) || nan(mic_ftD_5)) * 0xff); +} + +:cmp.eq.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x02 & micb_poolfx=0b000101 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN + micb_fd = sext((mic_fs:4 f== mic_ft_5:4) * 0xff); +} + +:cmp.eq.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x02 & micb_poolfx=0b010101 { + trapIfSNaN(mic_fsD, mic_ftD_5); + micb_fdD = sext((mic_fsD f== mic_ftD_5) * 0xff); +} + +:cmp.ueq.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x03 & micb_poolfx=0b000101 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN + micb_fd = sext( ( nan(mic_fs:4) || nan(mic_ft_5:4) || (mic_fs:4 f== mic_ft_5:4) ) * 0xff); +} + +:cmp.ueq.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x03 & micb_poolfx=0b010101 { + trapIfSNaN(mic_fsD, mic_ftD_5); + micb_fdD = sext( ( nan(mic_fsD) || nan(mic_ftD_5) || (mic_fsD f== mic_ftD_5) ) * 0xff); +} + +:cmp.lt.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x04 & micb_poolfx=0b000101 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN + micb_fd = sext((mic_fs:4 f< mic_ft_5:4) * 0xff); +} + +:cmp.lt.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x04 & micb_poolfx=0b010101 { + trapIfSNaN(mic_fsD, mic_ftD_5); + micb_fdD = sext((mic_fsD f< mic_ftD_5) * 0xff); +} + +:cmp.ult.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x05 & micb_poolfx=0b000101 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN + micb_fd = sext( ( nan(mic_fs:4) || nan(mic_ft_5:4) || (mic_fs:4 f< mic_ft_5:4) ) * 0xff); +} + +:cmp.ult.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x05 & micb_poolfx=0b010101 { + trapIfSNaN(mic_fsD, mic_ftD_5); + micb_fdD = sext( ( nan(mic_fsD) || nan(mic_ftD_5) || (mic_fsD f< mic_ftD_5) ) * 0xff); +} + +:cmp.le.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x06 & micb_poolfx=0b000101 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN + micb_fd = sext((mic_fs:4 f<= mic_ft_5:4) * 0xff); +} + +:cmp.le.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x06 & micb_poolfx=0b010101 { + trapIfSNaN(mic_fsD, mic_ftD_5); + micb_fdD = sext((mic_fsD f<= mic_ftD_5) * 0xff); +} + +:cmp.ule.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x07 & micb_poolfx=0b000101 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); # Trap if either operand is a Signaling NaN + micb_fd = sext( ( nan(mic_fs:4) || nan(mic_ft_5:4) || (mic_fs:4 f<= mic_ft_5:4) ) * 0xff); +} + +:cmp.ule.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x07 & micb_poolfx=0b010101 { + trapIfSNaN(mic_fsD, mic_ftD_5); + micb_fdD = sext( ( nan(mic_fsD) || nan(mic_ftD_5) || (mic_fsD f<= mic_ftD_5) ) * 0xff); +} + +:cmp.saf.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x08 & micb_poolfx=0b000101 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); + micb_fd = 0x0; +} + +:cmp.saf.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x08 & micb_poolfx=0b010101 { + trapIfNaN(mic_fsD, mic_ftD_5); + micb_fdD = 0x0; +} + +:cmp.sun.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x09 & micb_poolfx=0b000101 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); + micb_fd = sext((nan(mic_fs:4) || nan(mic_ft_5:4)) * 0xff); +} + +:cmp.sun.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x09 & micb_poolfx=0b010101 { + trapIfNaN(mic_fsD, mic_ftD_5); + micb_fdD = sext((nan(mic_fsD) || nan(mic_ftD_5)) * 0xff); +} + +:cmp.seq.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x0A & micb_poolfx=0b000101 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); + micb_fd = sext((mic_fs:4 f== mic_ft_5:4) * 0xff); +} + +:cmp.seq.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x0A & micb_poolfx=0b010101 { + trapIfNaN(mic_fsD, mic_ftD_5); + micb_fdD = sext((mic_fsD f== mic_ftD_5) * 0xff); +} + +:cmp.sueq.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x0B & micb_poolfx=0b000101 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); + micb_fd = sext( ( nan(mic_fs:4) || nan(mic_ft_5:4) || (mic_fs:4 f== mic_ft_5:4) ) * 0xff); +} + +:cmp.sueq.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x0B & micb_poolfx=0b010101 { + trapIfNaN(mic_fsD, mic_ftD_5); + micb_fdD = sext( ( nan(mic_fsD) || nan(mic_ftD_5) || (mic_fsD f== mic_ftD_5) ) * 0xff); +} + +:cmp.slt.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x0C & micb_poolfx=0b000101 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); + micb_fd = sext( (mic_fs:4 f< mic_ft_5:4) * 0xff); +} + +:cmp.slt.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x0C & micb_poolfx=0b010101 { + trapIfNaN(mic_fsD, mic_ftD_5); + micb_fdD = sext( (mic_fsD f< mic_ftD_5) * 0xff); +} + +:cmp.sult.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x0D & micb_poolfx=0b000101 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); + micb_fd = sext( ( nan(mic_fs:4) || nan(mic_ft_5:4) || (mic_fs:4 f< mic_ft_5:4) ) * 0xff); +} + +:cmp.sult.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x0D & micb_poolfx=0b010101 { + trapIfNaN(mic_fsD, mic_ftD_5); + micb_fdD = sext( ( nan(mic_fsD) || nan(mic_ftD_5) || (mic_fsD f< mic_ftD_5) ) * 0xff); +} + +:cmp.sle.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x0E & micb_poolfx=0b000101 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); + micb_fd = sext( (mic_fs:4 f<= mic_ft_5:4) * 0xff); +} + +:cmp.sle.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x0E & micb_poolfx=0b010101 { + trapIfNaN(mic_fsD, mic_ftD_5); + micb_fdD = sext( (mic_fsD f<= mic_ftD_5) * 0xff); +} + +:cmp.sule.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x0F & micb_poolfx=0b000101 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); + micb_fd = sext( ( nan(mic_fs:4) || nan(mic_ft_5:4) || (mic_fs:4 f<= mic_ft_5:4) ) * 0xff); +} + +:cmp.sule.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x0F & micb_poolfx=0b010101 { + trapIfNaN(mic_fsD, mic_ftD_5); + micb_fdD = sext( ( nan(mic_fsD) || nan(mic_ftD_5) || (mic_fsD f<= mic_ftD_5) ) * 0xff); +} + +:cmp.or.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x11 & micb_poolfx=0b000101 { + trapIfSNaN(mic_fs:4, mic_ft_5:4); + micb_fd = sext( (!(nan(mic_fs:4) || nan(mic_ft_5:4))) * 0xff); # The negated predicate of "c.un" +} + +:cmp.or.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x11 & micb_poolfx=0b010101 { + trapIfSNaN(mic_fsD, mic_ftD_5); + micb_fdD = sext( (!(nan(mic_fsD) || nan(mic_ftD_5))) * 0xff); +} + +:cmp.une.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x12 & micb_poolfx=0b000101 { + # The negated predicate of cmp.eq + trapIfSNaN(mic_fs:4, mic_ft_5:4); + micb_fd = sext((mic_fs:4 f!= mic_ft_5:4) * 0xff); +} + +:cmp.une.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x12 & micb_poolfx=0b010101 { + trapIfSNaN(mic_fsD, mic_ftD_5); + micb_fdD = sext((mic_fsD f!= mic_ftD_5) * 0xff); +} + +:cmp.ne.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x13 & micb_poolfx=0b000101 { + # The negated predicate of cmp.ueq + trapIfSNaN(mic_fs:4, mic_ft_5:4); + micb_fd = sext( (!( ( nan(mic_fs:4) || nan(mic_ft_5:4) || (mic_fs:4 f== mic_ft_5:4) ))) * 0xff); +} + +:cmp.ne.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x13 & micb_poolfx=0b010101 { + trapIfSNaN(mic_fsD, mic_ftD_5); + micb_fdD = sext( (!( ( nan(mic_fsD) || nan(mic_ftD_5) || (mic_fsD f== mic_ftD_5) ))) * 0xff); +} + +:cmp.sor.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x19 & micb_poolfx=0b000101 { + trapIfNaN(mic_fs:4, mic_ft_5:4); + micb_fd = sext( (!(nan(mic_fs:4) || nan(mic_ft_5:4))) * 0xff); # negate of cmp.sun +} + +:cmp.sor.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x19 & micb_poolfx=0b010101 { + trapIfNaN(mic_fsD, mic_ftD_5); + micb_fdD = sext( (!(nan(mic_fsD) || nan(mic_ftD_5))) * 0xff); +} + +:cmp.sune.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x1A & micb_poolfx=0b000101 { + trapIfNaN(mic_fs:4, mic_ft_5:4); + micb_fd = sext((mic_fs:4 f!= mic_ft_5:4) * 0xff); +} + +:cmp.sune.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x1A & micb_poolfx=0b010101 { + trapIfNaN(mic_fsD, mic_ftD_5); + micb_fdD = sext((mic_fsD f!= mic_ftD_5) * 0xff); +} + +:cmp.sne.S micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_cond2=0x1B & micb_poolfx=0b000101 { + trapIfNaN(mic_fs:4, mic_ft_5:4); # negate of cmp.sueq + micb_fd = sext( (! ( nan(mic_fs:4) || nan(mic_ft_5:4) || (mic_fs:4 f== mic_ft_5:4) )) * 0xff); +} + +:cmp.sne.D micb_fd, mic_fs, mic_ft_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_cond2=0x1B & micb_poolfx=0b010101 { + trapIfNaN(mic_fsD, mic_ftD_5); + micb_fdD = sext( (! ( nan(mic_fsD) || nan(mic_ftD_5) || (mic_fsD f== mic_ftD_5) )) * 0xff); +} + +:div micb_rd32, RS0L, RT5L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & RS0L & RT5L ; micb_axf2=0b0100011000 & micb_bit10=0 & micb_rd32 { + tmp:4 = RS0L s/ RT5L; + micb_rd32 = sext(tmp); +} + +:divu micb_rd32, RS0L, RT5L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & RS0L & RT5L ; micb_axf2=0b0110011000 & micb_bit10=0 & micb_rd32 { + tmp:4 = RS0L / RT5L; + micb_rd32 = sext(tmp); +} + +:dvp STYPE is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_funci=0 & STYPE ; micb_poolax=0b111100 & micb_axf=0b0001100101 { + disableProcessor(STYPE); +} + +:evp STYPE is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & mic_funci=0 & STYPE ; micb_poolax=0b111100 & micb_axf=0b0011100101 { + enableProcessor(STYPE); +} + +:jalrc RTIMP^mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & mic_rt32_5 & mic_rs32_0 & RTIMP ; micb_axf=0b0000111100 & micb_poolax=0b111100 { + JXWritePC(mic_rs32_0); + mic_rt32_5 = inst_next | 0x1; + call [pc]; +} + +:jalrc.hb RTIMP^mic_rs32_0 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & mic_rt32_5 & mic_rs32_0 & RTIMP ; micb_axf=0b0001111100 & micb_poolax=0b111100 { + JXWritePC(mic_rs32_0); + mic_rt32_5 = inst_next | 0x1; + call [pc]; +} + +:jalrc16 mic_rs32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=1 & mic_jalrr6=0b01110 & mic_rs32_5 { + JXWritePC(mic_rs32_5); + ra = inst_next | 0x1; + call [pc]; +} + +:jialc mic_rt32_0, EXT_MS16 is ISA_MODE=1 & RELP=0 & mic_op=0b101000 & REL6=1 & mic_index=0 & mic_rt32_0 ; EXT_MS16 { + tmp:$(REGSIZE) = mic_rt32_0 + sext(EXT_MS16); + JXWritePC(tmp); + ra = inst_next | 0x1; + goto [pc]; +} + +:jic mic_rt32_0, EXT_MS16 is ISA_MODE=1 & RELP=0 & mic_op=0b100000 & REL6=1 & mic_index=0 & mic_rt32_0 ; EXT_MS16 { + tmp:$(REGSIZE) = mic_rt32_0 + sext(EXT_MS16); + JXWritePC(tmp); + goto [pc]; +} + +:jrcaddiusp EXT_CODE5R6 is ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=1 & mic_jalrr6=0b10011 & EXT_CODE5R6 { + tmp:$(REGSIZE) = zext(EXT_CODE5R6); + sp = sp + tmp; + JXWritePC(ra); + goto [pc]; +} + +:jrc16 mic_rs32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=1 & mic_jalrr6=0b01100 & mic_rs32_5 { + JXWritePC(mic_rs32_5); + goto [pc]; +} + +:jrc16 ra is ISA_MODE=1 & RELP=0 & mic_op=0b010001 & REL6=1 & mic_jalrr6=0b01100 & mic_rs32_5=31 & ra { + JXWritePC(ra); + return [pc]; +} + +:llx mic_rt32_5, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=1 & mic_rt32_5 & mic_base0 ; micb_func12=0b0001 & micb_sub9=0b000 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt32_5 = sext(*[ram]:4 tmpa); + lockload(tmp); +} + +:llxe mic_rt32_5, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=1 & mic_rt32_5 & mic_base0 ; micb_func12=0b0110 & micb_sub9=0b010 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt32_5 = sext(*[ram]:4 tmpa); + lockload(tmp); +} + +:lsa micb_rd32, RS0L, RT5L, EXT_SA9 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & RS0L & RT5L ; micb_poolax=0b001111 & micb_asel=0b000 & EXT_SA9 & micb_rd32 { + tmp:4 = (RS0L << EXT_SA9) + RT5L; + micb_rd32 = sext(tmp); +} + +:lwpc mic_rt32_5, EXT_MS19 is ISA_MODE=1 & RELP=0 & mic_op=0b011110 & REL6=1 & mic_pcz=0b01 & mic_rt32_5 & mic_imm02 ; EXT_MS19 [ ext_32_imm3=mic_imm02; ] { + tmp:$(REGSIZE) = inst_start + sext(EXT_MS19); + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + tmpl:4 = *[ram]:4 tmpa; + mic_rt32_5 = sext(tmpl); +} + +:lwupc mic_rt32_5, EXT_MS19 is ISA_MODE=1 & RELP=0 & mic_op=0b011110 & REL6=1 & mic_pcz=0b10 & mic_rt32_5 & mic_imm02 ; EXT_MS19 [ ext_32_imm3=mic_imm02; ] { + tmp:$(REGSIZE) = inst_start + sext(EXT_MS19); + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + tmpl:4 = *[ram]:4 tmpa; + mic_rt32_5 = zext(tmpl); +} + +:maddf.S mic_ft_5, mic_fs, micb_fd is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_fmt9=0 & micb_fxf5=0b110111000 { + tmp:4 = micb_fd:4 f+ (mic_fs:4 f* mic_ft_5:4); + micb_fd = zext(tmp); +} + +:maddf.D mic_ft_5, mic_fs, micb_fd is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_fmt9=1 & micb_fxf5=0b110111000 { + micb_fdD = micb_fdD f+ (mic_fsD f* mic_ftD_5); +} + +:max.S mic_ft_5, mic_fs, micb_fd is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_fmt9=0 & micb_fxf5=0b000001011 { + # set floating point fd to the max of fs and ft, TBD special case for NaN + tmp_cond:1 = mic_fs:4 f> mic_ft_5:4; + micb_fd = zext( (mic_fs:4 * zext(tmp_cond == 1)) | (mic_ft_5:4 * zext(tmp_cond == 0) ) ); +} + +:max.D mic_ft_5, mic_fs, micb_fd is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_fmt9=1 & micb_fxf5=0b000001011 { + tmp_cond:1 = mic_fsD f> mic_ftD_5; + micb_fdD = zext( (mic_fsD * zext(tmp_cond == 1)) | (mic_ftD_5 * zext(tmp_cond == 0) ) ); +} + +:maxa.S mic_ft_5, mic_fs, micb_fd is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_fmt9=0 & micb_fxf5=0b000101011 { + # set floating point fd to the max of absolute values of fs and ft, TBD special case for NaN + tmp_cond:1 = abs(mic_fs:4) f> abs(mic_ft_5:4); + micb_fd = zext( (mic_fs:4 * zext(tmp_cond == 1)) | (mic_ft_5:4 * zext(tmp_cond == 0) ) ); +} + +:maxa.D mic_ft_5, mic_fs, micb_fd is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_fmt9=1 & micb_fxf5=0b000101011 { + tmp_cond:1 = abs(mic_fsD) f> abs(mic_ftD_5); + micb_fdD = zext( (mic_fsD * zext(tmp_cond == 1)) | (mic_ftD_5 * zext(tmp_cond == 0) ) ); +} + +:min.S mic_ft_5, mic_fs, micb_fd is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_fmt9=0 & micb_fxf5=0b000000011 { + # set floating point fd to the min of fs and ft, TBD special case for NaN + tmp_cond:1 = mic_fs:4 f< mic_ft_5:4; + micb_fd = zext( (mic_fs:4 * zext(tmp_cond == 1)) | (mic_ft_5:4 * zext(tmp_cond == 0) ) ); +} + +:min.D mic_ft_5, mic_fs, micb_fd is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_fmt9=1 & micb_fxf5=0b000000011 { + tmp_cond:1 = mic_fsD f< mic_ftD_5; + micb_fdD = zext( (mic_fsD * zext(tmp_cond == 1)) | (mic_ftD_5 * zext(tmp_cond == 0) ) ); +} + +:mina.S mic_ft_5, mic_fs, micb_fd is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_fmt9=0 & micb_fxf5=0b000100011 { + # set floating point fd to the min of absolute values of fs and ft, TBD special case for NaN + tmp_cond:1 = abs(mic_fs:4) f< abs(mic_ft_5:4); + micb_fd = zext( (mic_fs:4 * zext(tmp_cond == 1)) | (mic_ft_5:4 * zext(tmp_cond == 0) ) ); +} + +:mina.D mic_ft_5, mic_fs, micb_fd is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_fmt9=1 & micb_fxf5=0b000100011 { + tmp_cond:1 = abs(mic_fsD) f< abs(mic_ftD_5); + micb_fdD = zext( (mic_fsD * zext(tmp_cond == 1)) | (mic_ftD_5 * zext(tmp_cond == 0) ) ); +} + +:mod micb_rd32, RS0L, RT5L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & RS0L & RT5L ; micb_axf2=0b0101011000 & micb_bit10=0 & micb_rd32 { + tmp:4 = RS0L s% RT5L; + micb_rd32 = sext(tmp); +} + +:modu micb_rd32, RS0L, RT5L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & RS0L & RT5L ; micb_axf2=0b0111011000 & micb_bit10=0 & micb_rd32 { + tmp:4 = RS0L % RT5L; + micb_rd32 = sext(tmp); +} + +:msubf.S mic_ft_5, mic_fs, micb_fd is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_fmt9=0 & micb_fxf5=0b111111000 { + # set floating point fd = fd - fs * ft, using 32-bit floating values + tmp:4 = micb_fd:4 f- (mic_fs:4 f* mic_ft_5:4); + micb_fd = zext(tmp); +} + +:msubf.D mic_ft_5, mic_fs, micb_fd is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_fmt9=1 & micb_fxf5=0b111111000 { + micb_fdD = micb_fdD f- (mic_fsD f* mic_ftD_5); +} + +:muh micb_rd32, RS0L, RT5L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & RS0L & RT5L ; micb_axf2=0b0001011000 & micb_bit10=0 & micb_rd32 { + tmpS:8 = sext(RS0L); + tmpT:8 = sext(RT5L); + tmpS = tmpS * tmpT; + tmp:4 = tmpS[32,32]; + micb_rd32 = sext(tmp); +} + +:mulu micb_rd32, RS0L, RT5L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & RS0L & RT5L ; micb_axf2=0b0010011000 & micb_bit10=0 & micb_rd32 { + tmpS:8 = zext(RS0L); + tmpT:8 = zext(RT5L); + tmpS = tmpS * tmpT; + tmp:4 = tmpS[0,32]; + micb_rd32 = sext(tmp); +} + +:muhu micb_rd32, RS0L, RT5L is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & RS0L & RT5L ; micb_axf2=0b0011011000 & micb_bit10=0 & micb_rd32 { + tmpS:8 = zext(RS0L); + tmpT:8 = zext(RT5L); + tmpS = tmpS * tmpT; + tmp:4 = tmpS[32,32]; + micb_rd32 = sext(tmp); +} + +#sel only valid for PerfCtr +:rdhwr mic_rt32_5, mic_rs32_hw, micb_sel is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & mic_rt32_5 & mic_rs32_hw & mic_rs32_0=4; micb_sel & micb_z14=0 & micb_bit10=0 & micb_axf2=0b0111000000 { + mic_rt32_5 = getHWRegister(mic_rs32_hw, micb_sel:1); +} + +:rdhwr mic_rt32_5, mic_rs32_hw is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & mic_rt32_5 & mic_rs32_hw & mic_rs32_0!=4; micb_sel=0 & micb_z14=0 & micb_bit10=0 & micb_axf2=0b0111000000 { + mic_rt32_5 = getHWRegister(mic_rs32_hw); +} + +:rint.S mic_fd, mic_fs_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs_5 & mic_fd ; micb_fd=0 & micb_fmt9=0 & micb_fxf5=0b000100000 { + # floating point round to integral floating point + rm_tmp:1 = fcsr[0,2]; # Get RM rounding mode bits + fs_tmp:4 = mic_fs_5:4; + fs_cvt_tmp:4 = 0; + if (rm_tmp == 0) goto ; + fs_cvt_tmp = floor(fs_tmp); # RM is 1, no rounding, and floor returns a float + goto ; + + fs_cvt_tmp = round(fs_tmp); # round returns a float + + mic_fd = zext(fs_cvt_tmp); +} + +:rint.D mic_fd, mic_fs_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs_5 & mic_fd & mic_fsD_5 & mic_fdD; micb_fd=0 & micb_fmt9=1 & micb_fxf5=0b000100000 { + # floating point round to integral floating point + rm_tmp:1 = fcsr[0,2]; # Get RM rounding mode bits + if (rm_tmp == 0) goto ; + mic_fdD = floor(mic_fsD_5); # RM is 1, no rounding, and floor returns a float + goto ; + + mic_fdD = round(mic_fsD_5); # round returns a float + +} + +:scx RT5L, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=1 & RT5L & mic_base0 ; micb_func12=0b1001 & micb_sub9=0b000 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + lockwrite(tmp); + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:4 tmpa = RT5L; + RT5L = 1; +} + +:scxe RT5L, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=1 & RT5L & mic_base0 ; micb_func12=0b1010 & micb_sub9=0b000 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:4 tmpa = RT5L; + lockwrite(tmp); +} + +:seleqz micb_rd32, mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0101000000 & micb_bit10=0 & micb_rd32 { + # We use tmp to cover case where rs and rd are the same reg + tmps:$(REGSIZE) = mic_rs32_0; + tmpt:$(REGSIZE) = mic_rt32_5; + micb_rd32 = 0; + if (tmpt != 0) goto inst_next; + micb_rd32 = tmps; +} + +:selnez micb_rd32, mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0110000000 & micb_bit10=0 & micb_rd32 { + # We use tmp to cover case where rs and rd are the same reg + tmps:$(REGSIZE) = mic_rs32_0; + tmpt:$(REGSIZE) = mic_rt32_5; + micb_rd32 = 0; + if (tmpt == 0) goto inst_next; + micb_rd32 = tmps; +} + +:sel.S mic_ft_5, mic_fs, micb_fd is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_ft_5 ; micb_fd & micb_fmt9=0 & micb_fxf5=0b010111000 { + tmp:1 = (micb_fd[0,1] == 0x01); + micb_fd = (zext(tmp) * mic_ft_5) | (zext(tmp == 0x0) * mic_fs); +} + +:sel.D mic_ft_5, mic_fs, micb_fd is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=0 & mic_fs & mic_fsD & mic_ft_5 & mic_ftD_5; micb_fd & micb_fdD & micb_fmt9=1 & micb_fxf5=0b010111000 { + tmp:1 = (micb_fdD[0,1] == 0x01); + micb_fdD = (zext(tmp) * mic_ftD_5) | (zext(tmp == 0x0) * mic_fsD); +} + +:seleqz.S mic_ft_5, mic_fs, micb_fd is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_fmt9=0 & micb_fxf5=0b000111000 { + micb_fd = zext(mic_fs * zext(mic_ft_5[0,1] == 0)); +} + +:seleqz.D mic_ft_5, mic_fs, micb_fd is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5; micb_fd & micb_fdD & micb_fmt9=1 & micb_fxf5=0b000111000 { + micb_fdD = zext(mic_fsD * zext(mic_ftD_5[0,1] == 0)); +} + +:selnez.S mic_ft_5, mic_fs, micb_fd is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 ; micb_fd & micb_fmt9=0 & micb_fxf5=0b001111000 { + micb_fd = zext(mic_fs * zext(mic_ft_5[0,1] == 1)); +} + +:selnez.D mic_ft_5, mic_fs, micb_fd is ISA_MODE=1 & RELP=0 & mic_op=0b010101 & REL6=1 & mic_fs & mic_ft_5 & mic_fsD & mic_ftD_5 ; micb_fd & micb_fdD & micb_fmt9=1 & micb_fxf5=0b001111000 { + micb_fdD = zext(mic_fsD * zext(mic_ftD_5[0,1] == 1)); +} + +:sigrie EXT_CODE16 is ISA_MODE=1 & RELP=0 & mic_op=0b000000 & REL6=1 & mic_code4r6=0 & mic_imm6r6; micb_poolax=0b111111 & EXT_CODE16 [ ext_32_imm6 = mic_imm6r6; ] { + signalReservedInstruction(EXT_CODE16); +} + +@ifdef MIPS64 +:dalign micb_rd32, mic_rs32_0, mic_rt32_5, micb_bp8 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rt32_5 & mic_rs32_0 ; micb_poolax=0b011100 & micb_z67=0 & micb_rd32 & micb_bp8 { + tmp:8 = mic_rt32_5 << (8 * micb_bp8); + micb_rd32 = tmp | (mic_rs32_0 >> (64 - (8 * micb_bp8))); +} + +:dahi mic_rs32_0, EXT_MS48 is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=1 & mic_funci=0b10001 & mic_rs32_0 ; EXT_MS48 { + mic_rs32_0 = mic_rs32_0 + EXT_MS48; +} + +:dati mic_rs32_0, EXT_MS64 is ISA_MODE=1 & RELP=0 & mic_op=0b010000 & REL6=1 & mic_funci=0b10000 & mic_rs32_0 ; EXT_MS64 { + mic_rs32_0 = mic_rs32_0 + EXT_MS64; +} + +:daui mic_rt32_5, mic_rs32_0, EXT_MS32 is ISA_MODE=1 & RELP=0 & mic_op=0b111100 & REL6=1 & mic_rt32_5 & mic_rs32_0 ; EXT_MS32 { + mic_rt32_5 = mic_rs32_0 + sext(EXT_MS32); +} + +:dbitswap mic_rd32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rt32_5 & mic_rd32_0 ; micb_poolax=0b111100 & micb_axf3=0b101100 & micb_z12=0 { + mic_rd32_0 = bitSwap(mic_rt32_5); +} + +:ddiv micb_rd32, mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0100011000 & micb_bit10=0 & micb_rd32 { + micb_rd32 = mic_rs32_0 s/ mic_rt32_5; +} + +:ddivu micb_rd32, mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0110011000 & micb_bit10=0 & micb_rd32 { + micb_rd32 = mic_rs32_0 / mic_rt32_5; +} + +:dlsa micb_rd32, mic_rs32_0, mic_rt32_5, EXT_SA9 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rs32_0 & mic_rt32_5 ; micb_poolax=0b000100 & micb_asel=0b100 & EXT_SA9 & micb_rd32 { + micb_rd32 = (mic_rs32_0 << EXT_SA9) + mic_rt32_5; +} + +:dmod micb_rd32, mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0101011000 & micb_bit10=0 & micb_rd32 { + micb_rd32 = mic_rs32_0 s% mic_rt32_5; +} + +:dmodu micb_rd32, mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0111011000 & micb_bit10=0 & micb_rd32 { + micb_rd32 = mic_rs32_0 % mic_rt32_5; +} + +:dmul micb_rd32, mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0000011000 & micb_bit10=0 & micb_rd32 { + micb_rd32 = mic_rs32_0 * mic_rt32_5; +} + +:dmuh micb_rd32, mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0001011000 & micb_bit10=0 & micb_rd32 { + tmp:16 = sext(mic_rs32_0) * sext(mic_rt32_5); + micb_rd32 = tmp(8); +} + +:dmulu micb_rd32, mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0010011000 & micb_bit10=0 & micb_rd32 { + micb_rd32 = mic_rs32_0 * mic_rt32_5; +} + +:dmuhu micb_rd32, mic_rs32_0, mic_rt32_5 is ISA_MODE=1 & RELP=0 & mic_op=0b010110 & REL6=1 & mic_rs32_0 & mic_rt32_5 ; micb_axf2=0b0011011000 & micb_bit10=0 & micb_rd32 { + tmp:16 = zext(mic_rs32_0) * zext(mic_rt32_5); + micb_rd32 = tmp(8); +} + +:ldpc mic_rt32_5, EXT_MS18 is ISA_MODE=1 & RELP=0 & mic_op=0b011110 & REL6=1 & mic_pcf2=0b110 & mic_rt32_5 & mic_imm01 ; EXT_MS18 [ ext_32_imm2=mic_imm01; ] { + tmp:8 = inst_start + sext(EXT_MS18); + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt32_5 = *[ram]:8 tmpa; +} + +:lldx mic_rt32_5, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=1 & mic_rt32_5 & mic_base0 ; micb_func12=0b0101 & micb_sub9=0b000 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + mic_rt32_5 = sext(*[ram]:4 tmpa); + lockload(tmp); +} + +# The documentation is partly wrong for this instruction and generates a conflict (same pattern) as lldx instruction. The op-code map section of the document +# does have the difference between this and the lldx so I went with that. +:scdx mic_rt32_5, EXT_CODE9E(mic_base0) is ISA_MODE=1 & RELP=0 & mic_op=0b011000 & REL6=1 & mic_rt32_5 & mic_base0 ; micb_func12=0b1101 & micb_sub9=0b000 & EXT_CODE9E { + tmp:$(REGSIZE) = sext(EXT_CODE9E); + tmp = tmp + mic_base0; + lockwrite(tmp); + tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:8 tmpa = mic_rt32_5; + mic_rt32_5 = 1; +} + +@endif diff --git a/python/icicle/Ghidra/Processors/PA-RISC/data/languages/pa-risc.ldefs b/python/icicle/Ghidra/Processors/PA-RISC/data/languages/pa-risc.ldefs new file mode 100644 index 0000000..c6550a7 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PA-RISC/data/languages/pa-risc.ldefs @@ -0,0 +1,18 @@ + + + + + Generic PA-RISC 32-bit big endian + + + + + diff --git a/python/icicle/Ghidra/Processors/PA-RISC/data/languages/pa-risc.opinion b/python/icicle/Ghidra/Processors/PA-RISC/data/languages/pa-risc.opinion new file mode 100644 index 0000000..240b489 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PA-RISC/data/languages/pa-risc.opinion @@ -0,0 +1,5 @@ + + + + + diff --git a/python/icicle/Ghidra/Processors/PA-RISC/data/languages/pa-risc.sinc b/python/icicle/Ghidra/Processors/PA-RISC/data/languages/pa-risc.sinc new file mode 100644 index 0000000..0f375be --- /dev/null +++ b/python/icicle/Ghidra/Processors/PA-RISC/data/languages/pa-risc.sinc @@ -0,0 +1,1746 @@ +# PA-RISC common specification file for 32 and 64-bit processors +# Appropriate defines (PARISC32, PARISC64) must be +# specified before including this file + +# Known Issues: +# The branch target is annotated onto the line following the branch, not the branch itself +# There may still be issues with condition codes and instructions like INST,=,N r2,r3,r2 that write back into one of the input argument registers. +# The condition uses the final value in r2, when it should use the value passed in to r2 before the operation. +# The implementation of space registers is incorrect. There should really be a 64 bit address space with space register in the upper 64 bits. +# Right now, the space register is either ignored or else just added to the base address. +# Some of the pcode could be simplified. + + +# Attention- Sometimes the source and destination registers can be the same registers. +# When you write to a destination reg, it's important that your pcode always keeps a temp copy +# of the original if you later refer to a source reg. + + +# Register conventions +# +# r0 is always 0 +# r1 scratch register, caller saved +# r2 is rp is the return pointer +# r3 to r18 callee saves +# r19 to r22 caller saves +# r23 is arg3 +# r24 is arg2 +# r25 is arg1 +# r26 is arg0 +# r27 is the global data pointer dp and must be set to the .data symbol in the elf header +# r28 is ret0 the subroutine return value, high order word if a 64-bit return value +# r29 is ret1 the low order word of a 64-bit return value +# r30 is sp the stack pointer +# r31 is the millicode return pointer +# +# fr0 is farg0 if floating arg is 32-bits, 64-bit args are in farg1 high and low +# fr1 is farg0 if floating arg is 32-bits +# fr2 is farg0 if floating arg is 32-bits, 64-bit args are in farg3 high and low +# fr0 is farg0 if floating arg is 32-bits +# fr4 is fret floating point return (8 bytes) +# +# Note- only two double arguments can be passed in registers. +# If a function return value is larger than 64 bits, then the caller passes the address in r28 +# +# Note- function calls and returns are usually through relocation stubs +# + +#----- +@ifdef PARISC64 +@define REGSIZE "8" # General purpose register size (8 or 4) +@define ADDRSIZE "8" # Memory address size (8 bytes in 64 bit mode) + +@else # PARISC32 +@define REGSIZE "4" # General purpose register size (8 or 4) +@define ADDRSIZE "4" # Memory address size (8 bytes, using the space registers as the upper 32 bits and the regular base and offset as the lower 32 bits) +@endif +#----- + +define endian=$(ENDIAN); + +define alignment=4; + +# I'm not sure what to set for the sizes of these spaces -- TODO set these correctly +define space ram type=ram_space size=$(ADDRSIZE) default; +define space register type=register_space size=4; # this is a large enough address space to address all the registers. Two bytes would probably be enough + +# General purpose registers +define register offset=0 size=$(REGSIZE) [ + r0 r1 rp r3 + r4 r5 r6 r7 + r8 r9 r10 r11 + r12 r13 r14 r15 + r16 r17 r18 r19 + r20 r21 r22 r23 + r24 r25 r26 dp + r28 r29 sp r31 +]; + +# Floating point registers +define register offset=0x1000 size=8 [ + fr0 fpe23 fpe45 fpe67 fr4 fr5 fr6 fr7 + fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15 + fr16 fr17 fr18 fr19 fr20 fr21 fr22 fr23 + fr24 fr25 fr26 fr27 fr28 fr29 fr30 fr31 +]; + +define register offset=0x1000 size=4 [ + fr0R fr0L fpe2 fpe3 fpe4 fpe5 fpe6 fpe7 + fr4L fr4R fr5L fr5R fr6L fr6R fr7L fr7R + fr8L fr8R fr9L fr9R fr10L fr10R + fr11L fr11R fr12L fr12R fr13L fr13R fr14L fr14R + fr15L fr15R fr16L fr16R fr17L fr17R fr18L fr18R + fr19L fr19R fr20L fr20R fr21L fr21R fr22L fr22R + fr23L fr23R fr24L fr24R fr25L fr25R fr26L fr26R + fr27L fr27R fr28L fr28R fr29L fr29R fr30L fr30R + fr31L fr31R +]; + +# Floating Point Status Register +# Only the compare bit and the compare queue are implemented here +# and the Condition Queue is only 8 bits, rather than 10 +define register offset=0x1100 size=1 [ + compareBit compareQueue +]; + +# Shadow Registers +define register offset=0x2000 size=$(REGSIZE) [ + shr0 shr1 shr2 shr3 shr4 shr5 shr6 +]; + +# Space Registers +define register offset=0x3000 size=4 [ + sr0 sr1 sr2 sr3 sr4 sr5 sr6 sr7 +]; + +# Processor Status Word +define register offset=0x4000 size=1 [ + pswY pswZ pswE pswS pswT pswH pswL pswN pswX pswB pswC pswV pswM pswCB pswG pswF pswR pswQ pswP pswD pswI +]; + +# Control Registers +define register offset=0x5000 size=4 [ + cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 + cr8 cr9 cr10 sar cr12 cr13 cr14 cr15 + cr16 cr17 cr18 cr19 cr20 cr21 cr22 cr23 + cr24 cr25 cr26 cr27 cr28 cr29 cr30 cr31 +]; + +# instruction address offset and instruction address space queues +# these are used for branching, to compute target addresses and deal with branch delay slots +define register offset=0x6000 size=4 [ + iasq_front iasq_back iaoq_front iaoq_back +]; + +# special hidden registers to support the nullify and delay slot features of PA-RISC +define register offset=0x7000 size=1 [nullifyCond nullifyNextCond branchCond branchExecuted]; +define register offset=0x7100 size=4 [branchIndDest nullifyCondResult]; + +define register offset=0x7200 size=12 contextreg; +define context contextreg + + # transient context + phase = (0,2) noflow + temp1 = (3,3) + + # stored context + nullifyEnable = (4,4) noflow + branchCouldBeNullified = (5,5) noflow + branchEnable = (6,6) noflow + branchType = (7,9) noflow +# These do not appear to be used: +# branchIsInd = (7,7) noflow +# branchIsCond = (8,8) noflow +# branchIsCall = (9,9) noflow + branchIsReturn = (10,10) noflow # used for returns + padding = (10,31) noflow + branchImmDest = (32,63) noflow + temp32 = (64,95) noflow +; + +@define COMMON "phase=1 " + +# Instruction fields + +define token instr(32) + opfam = (26,31) + cr = (21,25) + crname2 = (21,25) + freg2 = (21,25) + freg2sgl = (21,25) + fr2half = (21,25) + fusedr2 = (21,25) + reg2 = (21,25) + b = (21,25) + bboffset = (21,25) + crname1 = (21,25) + bit20 = (20,20) signed + fpc1sub2 = (17,20) + highIm10 = (16,25) + reg1 = (16,20) + fusedr1 = (16,20) + freg1 = (16,20) + freg1sgl = (16,20) + fr1half = (16,20) + r = (16,20) + highIm5 = (16,20) signed + highIm5less16 = (17,20) + tr = (16,20) + x = (16,20) + w1 = (16,20) + bit16 = (16,16) + fpc1sub = (15,16) + srbit1 = (15,15) + s = (14,15) + srbit0 = (14,14) + im13 = (13,25) signed + SEDCondSym = (13,15) + RegUnitCondSym = (13,15) + InvUnitCondSym = (13,15) + RegLogicCondSym = (13,15) + InvLogicCondSym = (13,15) + RegAddCondSym = (13,15) + InvAddCondSym = (13,15) + RegCSCondSym = (13,15) + InvCSCondSym = (13,15) + c = (13,15) + fpsub = (13,15) + srbit2 = (13,13) + fpdf = (13,14) + fixeddf = (13,14) + fpdfraw = (13,14) + fixedsf = (13,14) + a = (13,13) + u = (13,13) + fpr1x = (12,12) + f = (12,12) + fv = (12,12) + zero = (12,12) + one = (12,12) + subop1012 = (10,12) + im15 = (11,25) + sopim10 = (11,20) signed + sopim5 = (11,15) signed + fpta = (11,15) + fusedta = (11,15) + fpsf = (11,12) + fpsfraw = (11,12) + fpfmt = (11,12) + fpfmt1bit = (11,11) + bit11 = (11,11) + cc = (10,11) + ldcc = (10,11) + stcc = (10,11) + ldcwcc = (10,11) + bit10 = (10,10) + sopim17 = (9,25) + pmuop = (9,13) + specop = (9,10) + fpclass = (9,10) + bit9 = (9,9) + bit8 = (8,8) + fpx = (8,8) + bits78 = (7,8) + fpr2x = (7,7) + fpra = (6,10) + fusedra = (6,10) + ext4 = (6,9) + C = (6,9) + subop = (6,9) + sysopshifted= (6,13) + sysopshiftedshort = (6,12) + op = (6,11) + sfu = (6,8) + fp0czero = (6,8) + fptx = (6,6) + bit6 = (6,6) + sysop = (5,12) + i2 = (5,11) + bits59 = (5,9) + cp = (5,9) + fusedfmt = (5,5) + bit5 = (5,5) + m = (5,5) + spn = (5,5) + w2 = (2,12) + w2_2 = (2,2) + w2less2 = (3,12) + n = (1,1) + im26 = (0,25) signed + sim21 = (0,20) signed + sim14 = (0,13) signed + im21less0 = (1,20) + im21_1_12 = (1,11) + im21_12_14 = (12,13) + im21_14_16 = (14,15) + im21_16_21 = (16,20) + im14 = (0,13) + im14less0 = (1,13) + im11 = (0,10) signed + im11less0 = (1,11) + sim5 = (0,4) signed + im5 = (0,4) + im5less0 = (1,4) + fpcond = (0,4) + fptest = (0,4) + fpt = (0,4) + fptsgl = (0,4) + fusedrt = (0,4) + fpthalf = (0,4) + crnamet = (0,4) + t = (0,4) + bit0 = (0,0) + w = (0,0) +; + +# general purpose registers +attach variables [reg1 reg2 t r b x] [ + r0 r1 rp r3 r4 r5 r6 r7 + r8 r9 r10 r11 r12 r13 r14 r15 + r16 r17 r18 r19 r20 r21 r22 r23 + r24 r25 r26 dp r28 r29 sp r31 +]; + +# fp registers - 64 bit doubles +attach variables [ freg2 freg1 fpt fpra fpta ] [ + fr0 fpe23 fpe45 fpe67 fr4 fr5 fr6 fr7 + fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15 + fr16 fr17 fr18 fr19 fr20 fr21 fr22 fr23 + fr24 fr25 fr26 fr27 fr28 fr29 fr30 fr31 +]; + +# 64 bit fp registers when used as 32 bit (.sgl completer) +# This mapping goes from bit pattern N -> register NL +attach variables [ freg2sgl freg1sgl fptsgl ] [ + fr0L fpe2 fpe4 fpe6 fr4L fr5L fr6L fr7L + fr8L fr9L fr10L fr11L fr12L fr13L fr14L fr15L + fr16L fr17L fr18L fr19L fr20L fr21L fr22L fr23L + fr24L fr25L fr26L fr27L fr28L fr29L fr30L fr31L +]; + +# 32 bit single precision mode fpra fpta for mult-add and mult-sub instructions +attach variables [ fusedra fusedta fusedr2 fusedr1 fusedrt ] [ + fr16L fr17L fr18L fr19L fr20L fr21L fr22L fr23L + fr24L fr25L fr26L fr27L fr28L fr29L fr30L fr31L + fr16R fr17R fr18R fr19R fr20R fr21R fr22R fr23R + fr24R fr25R fr26R fr27R fr28R fr29R fr30R fr31R +]; + +# control registers +attach variables [ cr ] [ + cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 + cr8 cr9 cr10 sar cr12 cr13 cr14 cr15 + cr16 cr17 cr18 cr19 cr20 cr21 cr22 cr23 + cr24 cr25 cr26 cr27 cr28 cr29 cr30 cr31 +]; + +# control registers by their purpose names +attach names [ crname2 crname1 crnamet ] [ + RCTR CR1 CR2 CR3 CR4 CR5 CR6 CR7 + PID1 PID2 CCR SAR PID3 PID4 IVA EIEM + ITMR IIASQ IIAOQ IIR ISR IOR IPSW EIRR + TMP0 TMP1 TMP2 TMP3 TMP4 TMP5 TMP6 TMP7 +]; + +attach names [ ldcc ] [ + none resv sl resv +]; + +attach names [ stcc ] [ + none BC SL resv +]; + +attach names [ ldcwcc ] [ + none CO resv resv +]; + +# Table 5-7 +attach names [ SEDCondSym ] [ + "" ",=" ",<" ",OD" ",TR" ",<>" ",>=" ",EV" +]; + +attach names [ RegUnitCondSym ] [ + "" _ ",SBZ" ",SHZ" ",SDC" _ ",SBC" ",SHC" +]; + +attach names [ InvUnitCondSym ] [ + "" _ ",NBZ" ",NHZ" ",NDC" _ ",NBC" ",NHC" +]; + +attach names [ RegLogicCondSym ] [ + "" ",=" ",<" ",<=" _ _ _ ",OD" +]; + +attach names [ InvLogicCondSym ] [ + "" ",<>" ",>=" ",>" _ _ _ ",EV" +]; + +# Table 5-4 +attach names [ RegAddCondSym ] [ + "" ",=" ",<" ",<=" ",NUV" ",ZNV" ",SV" ",OD" +]; + +attach names [ InvAddCondSym ] [ + "" ",<>" ",>=" ",>" ",UV" ",VNZ" ",NSV" ",EV" +]; + +attach names [ RegCSCondSym ] [ + "" ",=" ",<" ",<=" ",<<" ",<<=" ",SV" ",OD" +]; + +attach names [ InvCSCondSym ] [ + "" ",<>" ",>=" ",>" ",>>=" ",>>" ",NSV" ",EV" +]; + +# the different tests used by the FTEST instruction +attach names [ fptest ] [ + "" "ACC" "REJ" _ _ "ACC8" "REJ8" _ _ "ACC6" _ _ _ "ACC4" _ _ _ "ACC2" _ _ _ _ _ _ _ _ _ _ _ _ _ _ +]; + +# the floating point number types +attach names [ fpsf fpdf fpfmt ] [ + ",SGL" ",DBL" ",QUAD" _ +]; + +attach names [ fpfmt1bit ] [ + ",SGL" ",DBL" +]; + +# the fixed point number types +attach names [ fixedsf fixeddf ] [ + ",UW" ",UD" ",UQ" _ +]; + +# the floating point number types for fused ops +attach names [ fusedfmt ] [ + ",DBL" ",SGL" +]; + + +###################################################################################### +# caret instruction builders for nullify and branch +###################################################################################### +# These all assume a fall through from a preceding branch +# If there is a branch into the delay slot of a different branch, +# then the branch logic will still be present from the preceding instruction +# and the control flow will branch to that destination. +# This case should result in a red bookmark due to the disassembly context difference +# These all also assume that the instruction following a branch (in the delay slot) +# does not nullify its succeeding instruction +####################################################################################### +# no branch, no nullify +# previous instruction was not a branch and did not nullify this instruction +:^instruction is phase=0 & branchEnable=0 & nullifyEnable=0 & instruction [ phase=1; ] { + nullifyNextCond=0; + build instruction; + nullifyCond=nullifyNextCond; +} + +# previous instruction was not a branch, but may have conditionally nullified this instruction +:^instruction is phase=0 & branchEnable=0 & nullifyEnable=1 & instruction [ phase=1; ] { + local wasNullified = nullifyCond; + nullifyCond = 0; + nullifyNextCond=0; + if (wasNullified) goto ; + build instruction; + nullifyCond=nullifyNextCond; + +} + +# +# Handle branches that don't nullify their branch delay slot instructions +# These instructions themselves may have been nullified, so we need to +# check and conditionally execute the branch based on that. +# +# Need to reset branchCond = 0 before build instruction because the insruction does not reset it, +# and if branchcond is not reset, then it persists to subsequent instructions. + +immediateDest: is branchImmDest { export *:$(ADDRSIZE) branchImmDest; } + +# previous instruction was a branch, but this instruction was not nullified +# but branch instruction could have been nullified +# branchType = 0, unconditional immediate branch +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=0 & branchCouldBeNullified=1 & instruction & immediateDest [ phase=1; ] { + nullifyCond = 0; + nullifyNextCond = 0; + local previousBranchExecuted = branchExecuted; + branchCond = 0; + branchExecuted = 0; + build instruction; + if ( previousBranchExecuted ) goto immediateDest; + nullifyCond=nullifyNextCond; +} + +# previous instruction was a branch, but this instruction was not nullified +# branchType = 0, unconditional immediate branch +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=0 & branchCouldBeNullified=0 & instruction & immediateDest [ phase=1; ] { + nullifyCond = 0; + nullifyNextCond = 0; + branchCond = 0; + branchExecuted=0; + build instruction; + goto immediateDest; +} + +# branchType = 1, unconditional immediate call +# this doesn't handle the case where the inst in the delay slot nullifies the next instruction +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=1 & branchCouldBeNullified=1 & instruction & immediateDest [ phase=1; ] { + nullifyCond = 0; + nullifyNextCond = 0; + local previousBranchExecuted = branchExecuted; + branchCond = 0; + branchExecuted = 0; + build instruction; + if ( ! previousBranchExecuted ) goto ; + call immediateDest; + + nullifyCond=nullifyNextCond; +} + +# branchType = 1, unconditional immediate call +# this doesn't handle the case where the inst in the delay slot nullifies the next instruction +# this is the case where the branch could not have been nullified +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=1 & branchCouldBeNullified=0 & instruction & immediateDest [ phase=1; ] { + nullifyCond = 0; + nullifyNextCond = 0; + branchExecuted = 0; + build instruction; + call immediateDest; +} + +# branchType = 2, conditional immediate branch +# the preceding instruction was a branch that may or may not have been taken and may or may not have been nullified +# but was not nullifying itself (the delay slot must execute) +# this doesn't handle the case where the instruction in the branch delay slot nullifies the next instruction +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=2 & branchCouldBeNullified=1 & instruction & immediateDest [ phase=1; ] { + nullifyCond = 0; + nullifyNextCond=0; + local previousBranchExecuted = branchExecuted; + branchExecuted = 0; + local previousBranchCond = branchCond; + branchCond = 0; + build instruction; + if (previousBranchCond && previousBranchExecuted) goto immediateDest; + nullifyCond=nullifyNextCond; +} + +# branchType = 2, conditional immediate branch +# the preceding instruction was a branch that may or may not have been taken and may or may not have been nullified +# but was not nullifying itself (the delay slot must execute) +# this doesn't handle the case where the instruction in the branch delay slot nullifies the next instruction +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=2 & branchCouldBeNullified=0 & instruction & immediateDest [ phase=1; ] { + nullifyCond = 0; + nullifyNextCond = 0; + branchExecuted = 0; + local previousBranchCond = branchCond; + branchCond = 0; + build instruction; + if (previousBranchCond) goto immediateDest; + nullifyCond=nullifyNextCond;} + +# branchType = 3, conditional immediate call, (currently not used, may not exist in PA-RISC) +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=3 & branchCouldBeNullified=1 & instruction & immediateDest [ phase=1; ] { + nullifyNextCond=0; + local previousBranchExecuted = branchExecuted; + local previousBranchCond = branchCond; + branchCond = 0; + branchExecuted = 0; + build instruction; + if ( ! (previousBranchCond && previousBranchExecuted) ) goto ; + call immediateDest; + + nullifyCond=nullifyNextCond; +} + +# branchType = 3, conditional immediate call, (currently not used, may not exist in PA-RISC) +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=3 & branchCouldBeNullified=0 & instruction & immediateDest [ phase=1; ] { + nullifyNextCond=0; + local previousBranchCond = branchCond; + branchCond = 0; + branchExecuted = 0; + build instruction; + if ( ! (previousBranchCond) ) goto ; + call immediateDest; + + nullifyCond=nullifyNextCond; +} + +# branchType = 4, unconditional indirect branch +# the preceding instruction was a branch that did not nullify its branch delay slot inst +# The branch is indirect and may have been nullified +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchCouldBeNullified=1 & branchType=4 & instruction [ phase=1; ] { + nullifyCond = 0; + nullifyNextCond = 0; + local previousBranchExecuted = branchExecuted; + branchExecuted = 0; + build instruction; + if ( ! previousBranchExecuted ) goto ; + goto [branchIndDest]; + + nullifyCond=nullifyNextCond; +} + +# branchType = 4, unconditional indirect branch and also return +# the preceding instruction was a branch that did not nullify its branch delay slot inst +# The branch is indirect and WAS NOT nullified +# +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchCouldBeNullified=0 & branchType=4 & instruction & branchIsReturn=0 [ phase=1; ] { + nullifyCond = 0; + nullifyNextCond = 0; + branchExecuted = 0; + build instruction; + goto [branchIndDest]; +} + +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchCouldBeNullified=0 & branchType=4 & instruction & branchIsReturn=1 [ phase=1; ] { + nullifyCond = 0; + nullifyNextCond = 0; + branchExecuted = 0; + build instruction; + return [branchIndDest]; +} + + +# branchType = 5, unconditional indirect call +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=5 & branchCouldBeNullified=1 & instruction [ phase=1; ] { + nullifyCond = 0; + nullifyNextCond = 0; + local previousBranchExecuted = branchExecuted; + branchExecuted = 0; + build instruction; + if ( ! previousBranchExecuted ) goto ; + call [branchIndDest]; + + nullifyCond=nullifyNextCond; +} + +# branchType = 5, unconditional indirect call +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=5 & branchCouldBeNullified=0 & instruction [ phase=1; ] { + nullifyCond = 0; + nullifyNextCond = 0; + branchExecuted = 0; + build instruction; + call [branchIndDest]; +} + +# branchType = 6, conditional indirect branch +# previous instruction was a conditional branch that may or may not be taken and may have been nullified +# however, the branch does not nullify the inst in its branch delay slot +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=6 & branchCouldBeNullified=1 & instruction [ phase=1; ] { + nullifyCond = 0; + nullifyNextCond=0; + local previousBranchExecuted = branchExecuted; + local previousBranchCond = branchCond; + branchCond = 0; + branchExecuted = 0; + build instruction; + if ( ! previousBranchExecuted || ! previousBranchCond) goto ; + goto [branchIndDest]; + + nullifyCond=nullifyNextCond; +} + +# branchType = 6, conditional indirect branch +# previous instruction was a conditional branch that may or may not be taken and may have been nullified +# however, the branch does not nullify the inst in its branch delay slot +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=6 & branchCouldBeNullified=0 & instruction [ phase=1; ] { + nullifyCond = 0; + nullifyNextCond=0; + branchExecuted = 0; + local previousBranchCond = branchCond; + branchCond = 0; + build instruction; + if ( ! previousBranchCond ) goto ; + goto [branchIndDest]; + + nullifyCond=nullifyNextCond; +} + +# branchType = 7, conditional indirect call +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=7 & branchCouldBeNullified=1 & instruction [ phase=1; ] { + nullifyCond = 0; + nullifyNextCond=0; + local previousBranchExecuted = branchExecuted; + local previousBranchCond = branchCond; + branchCond = 0; + branchExecuted = 0; + build instruction; + if ( ! previousBranchExecuted || ! previousBranchCond) goto ; + call [branchIndDest]; + + nullifyCond=nullifyNextCond; +} + +# branchType = 7, conditional indirect call +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=0 & branchType=7 & branchCouldBeNullified=0 & instruction [ phase=1; ] { + nullifyCond = 0; + nullifyNextCond=0; + branchExecuted = 0; + local previousBranchCond= branchCond; + branchCond = 0; + build instruction; + if ( ! previousBranchCond) goto ; + call [branchIndDest]; + + nullifyCond=nullifyNextCond; +} + +# +# Handle branches with nullification -- the branch may nullify its branch delay slot +# + +# branchType = 0, unconditional immediate branch +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=0 & branchCouldBeNullified=1 & instruction & immediateDest [ phase=1; ] { + local nullify = nullifyCond; + nullifyCond = 0; + nullifyNextCond = 0; + local previousBranchExecuted = branchExecuted; + branchExecuted = 0; + if (nullify) goto ; + build instruction; + + if ( previousBranchExecuted ) goto immediateDest; + nullifyCond=nullifyNextCond; +} + +# branchType = 0, unconditional immediate branch +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=0 & branchCouldBeNullified=0 & instruction & immediateDest [ phase=1; ] { + local nullify = nullifyCond; + nullifyCond = 0; + nullifyNextCond = 0; + branchExecuted = 0; + if (nullify) goto ; + build instruction; + + goto immediateDest; +} + +# branchType = 1, unconditional immediate call +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=1 & branchCouldBeNullified=1 & instruction & immediateDest [ phase=1; ] { + local nullify = nullifyCond; + nullifyCond = 0; + nullifyNextCond = 0; + local previousBranchExecuted = branchExecuted; + branchExecuted = 0; + if (nullify) goto ; + build instruction; + + if ( ! previousBranchExecuted ) goto ; + call immediateDest; + + nullifyCond=nullifyNextCond; +} + +# branchType = 1, unconditional immediate call +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=1 & branchCouldBeNullified=0 & instruction & immediateDest [ phase=1; ] { + local nullify = nullifyCond; + nullifyCond = 0; + nullifyNextCond = 0; + branchExecuted = 0; + if (nullify) goto ; + build instruction; + + call immediateDest; +} + +# branchType = 2, conditional immediate branch +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=2 & branchCouldBeNullified=1 & instruction & immediateDest [ phase=1; ] { + local nullify = nullifyCond; + nullifyCond = 0; + nullifyNextCond=0; + local previousBranchExecuted = branchExecuted; + branchExecuted = 0; + local previousBranchCond = branchCond; + branchCond = 0; + if (nullify) goto ; + build instruction; + + if (previousBranchCond && previousBranchExecuted) goto immediateDest; + nullifyCond=nullifyNextCond; +} + +# branchType = 2, conditional immediate branch +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=2 & branchCouldBeNullified=0 & instruction & immediateDest [ phase=1; ] { + local nullify = nullifyCond; + nullifyCond = 0; + nullifyNextCond=0; + branchExecuted = 0; + local previousBranchCond = branchCond; + branchCond = 0; # Need to reset branchCond + if (nullify) goto ; + build instruction; + + if (previousBranchCond) goto immediateDest; + nullifyCond=nullifyNextCond; +} + +# branchType = 3, conditional immediate call +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=3 & branchCouldBeNullified=1 & instruction & immediateDest [ phase=1; ] { + local nullify = nullifyCond; + nullifyNextCond=0; + local previousBranchExecuted = branchExecuted; + local previousBranchCond = branchCond; + branchCond = 0; + branchExecuted = 0; + if (nullify) goto ; + build instruction; + + if ( ! (previousBranchCond && previousBranchExecuted) ) goto ; + call immediateDest; + + nullifyCond=nullifyNextCond; +} + +# branchType = 3, conditional immediate call +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=3 & branchCouldBeNullified=0 & instruction & immediateDest [ phase=1; ] { + local nullify = nullifyCond; + nullifyNextCond=0; + local previousBranchCond = branchCond; + branchCond = 0; + branchExecuted = 0; + if (nullify) goto ; + build instruction; + + if ( ! previousBranchCond ) goto ; + call immediateDest; + + nullifyCond=nullifyNextCond; +} + +# branchType = 4, unconditional indirect branch +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=4 & branchCouldBeNullified=1 & instruction [ phase=1; ] { + local nullify = nullifyCond; + nullifyCond = 0; + nullifyNextCond = 0; + local previousBranchExecuted = branchExecuted; + branchExecuted = 0; + if (nullify) goto ; + build instruction; + + if ( ! previousBranchExecuted ) goto ; + goto [branchIndDest]; + + nullifyCond=nullifyNextCond; +} + +# branchType = 4, unconditional indirect branch +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=4 & branchCouldBeNullified=0 & instruction [ phase=1; ] { + local nullify = nullifyCond; + nullifyCond = 0; + nullifyNextCond = 0; + branchExecuted = 0; + if (nullify) goto ; + build instruction; + + goto [branchIndDest]; +} + +# branchType = 5, unconditional indirect call +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=5 & branchCouldBeNullified=1 & instruction [ phase=1; ] { + local nullify = nullifyCond; + nullifyCond = 0; + nullifyNextCond = 0; + local previousBranchExecuted = branchExecuted; + branchExecuted = 0; + if (nullify) goto ; + build instruction; + + if ( ! previousBranchExecuted ) goto ; + call [branchIndDest]; + + nullifyCond=nullifyNextCond; +} + +# branchType = 5, unconditional indirect call +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=5 & branchCouldBeNullified=0 & instruction [ phase=1; ] { + local nullify = nullifyCond; + nullifyCond = 0; + nullifyNextCond = 0; + branchExecuted = 0; + if (nullify) goto ; + build instruction; + + call [branchIndDest]; +} + +# branchType = 6, conditional indirect branch +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=6 & branchCouldBeNullified=1 & instruction [ phase=1; ] { + local nullify = nullifyCond; + nullifyCond = 0; + nullifyNextCond=0; + local previousBranchExecuted = branchExecuted; + branchExecuted = 0; + local previousBranchCond = branchCond; + branchCond = 0; + if (nullify) goto ; + build instruction; + + if ( ! previousBranchExecuted || ! previousBranchCond) goto ; + goto [branchIndDest]; + + nullifyCond=nullifyNextCond; +} + +# branchType = 6, conditional indirect branch +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=6 & branchCouldBeNullified=0 & instruction [ phase=1; ] { + local nullify = nullifyCond; + nullifyCond = 0; + nullifyNextCond=0; + branchExecuted = 0; + local previousBranchCond = branchCond; + branchCond = 0; + if (nullify) goto ; + build instruction; + + if ( ! previousBranchCond) goto ; + goto [branchIndDest]; + + nullifyCond=nullifyNextCond; +} + +# branchType = 7, conditional indirect call +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=7 & branchCouldBeNullified=1 & instruction [ phase=1; ] { + local nullify = nullifyCond; + nullifyNextCond=0; + local previousBranchExecuted = branchExecuted; + branchExecuted = 0; + local previousBranchCond = branchCond; + branchCond = 0; + if (nullify) goto ; + build instruction; + + if ( ! previousBranchExecuted || ! previousBranchCond) goto ; + call [branchIndDest]; + + nullifyCond=nullifyNextCond; +} + +# branchType = 7, conditional indirect call +:^instruction is phase=0 & branchEnable=1 & nullifyEnable=1 & branchType=7 & branchCouldBeNullified=0 & instruction [ phase=1; ] { + local nullify = nullifyCond; + nullifyNextCond=0; + branchExecuted = 0; + local previousBranchCond = branchCond; + branchCond = 0; + if (nullify) goto ; + build instruction; + + if ( ! previousBranchCond ) goto ; + call [branchIndDest]; + + nullifyCond=nullifyNextCond; +} + +############################################################ +# Subconstructors +############################################################ + +############################# +# general purpose registers selected +# by different fields for different purposes (index, base, general, src, target, ...) +############################# +R1: reg1 is reg1 & reg1=0 { export 0:$(REGSIZE); } +R1: reg1 is reg1 { export reg1; } +R1dst: reg1 is reg1 { export reg1; } + +R2: reg2 is reg2 & reg2=0 { export 0:$(REGSIZE); } +R2: reg2 is reg2 { export reg2; } +R2dst: reg2 is reg2 { export reg2; } + +RT: t is t { export t; } + +RB: b is b & b=0 { export 0:$(REGSIZE); } +RB: b is b { export b; } + +RX: is x=0 { export 0:$(REGSIZE); } +RX: x is x { export x; } + +RR: r is r & r=0 { export 0:$(REGSIZE); } +RR: r is r { export r; } + +SAR: "SAR" is epsilon { export sar; } +SR0: sr0 is sr0 { export sr0; } +R31: r31 is r31 { export r31; } + +# 64 bit fp register access +FPR164: freg1 is freg1 { export freg1; } +FPR264: freg2 is freg2 { export freg2; } +FPRT64: fpt is fpt { export fpt; } + +# register encoding for fused ops (fmpyadd, fmpysub) +FUSEDR1: fusedr1 is fusedr1 { export fusedr1; } +FUSEDR2: fusedr2 is fusedr2 { export fusedr2; } +FUSEDRA: fusedra is fusedra { export fusedra; } +FUSEDTA: fusedta is fusedta { export fusedta; } +FUSEDRT: fusedrt is fusedrt { export fusedrt; } + +# 32 bit fp register access, lower half (L) and upper half (R) +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 0 { export fr0L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 1 { export fpe2; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 2 { export fpe4; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 3 { export fpe6; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 4 { export fr4L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 5 { export fr5L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 6 { export fr6L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 7 { export fr7L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 8 { export fr8L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 9 { export fr9L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 10 { export fr10L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 11 { export fr11L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 12 { export fr12L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 13 { export fr13L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 14 { export fr14L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 15 { export fr15L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 16 { export fr16L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 17 { export fr17L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 18 { export fr18L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 19 { export fr19L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 20 { export fr20L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 21 { export fr21L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 22 { export fr22L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 23 { export fr23L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 24 { export fr24L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 25 { export fr25L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 26 { export fr26L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 27 { export fr27L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 28 { export fr28L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 29 { export fr29L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 30 { export fr30L; } +FPR132: freg1^"L" is fpr1x = 0 & freg1 & fr1half = 31 { export fr31L; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 0 { export fr0R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 1 { export fpe3; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 2 { export fpe5; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 3 { export fpe7; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 4 { export fr4R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 5 { export fr5R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 6 { export fr6R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 7 { export fr7R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 8 { export fr8R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 9 { export fr9R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 10 { export fr10R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 11 { export fr11R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 12 { export fr12R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 13 { export fr13R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 14 { export fr14R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 15 { export fr15R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 16 { export fr16R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 17 { export fr17R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 18 { export fr18R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 19 { export fr19R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 20 { export fr20R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 21 { export fr21R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 22 { export fr22R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 23 { export fr23R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 24 { export fr24R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 25 { export fr25R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 26 { export fr26R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 27 { export fr27R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 28 { export fr28R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 29 { export fr29R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 30 { export fr30R; } +FPR132: freg1^"R" is freg1 & fpr1x = 1 & fr1half = 31 { export fr31R; } + +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 0 { export fr0L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 1 { export fpe2; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 2 { export fpe4; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 3 { export fpe6; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 4 { export fr4L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 5 { export fr5L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 6 { export fr6L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 7 { export fr7L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 8 { export fr8L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 9 { export fr9L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 10 { export fr10L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 11 { export fr11L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 12 { export fr12L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 13 { export fr13L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 14 { export fr14L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 15 { export fr15L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 16 { export fr16L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 17 { export fr17L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 18 { export fr18L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 19 { export fr19L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 20 { export fr20L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 21 { export fr21L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 22 { export fr22L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 23 { export fr23L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 24 { export fr24L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 25 { export fr25L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 26 { export fr26L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 27 { export fr27L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 28 { export fr28L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 29 { export fr29L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 30 { export fr30L; } +FPR232: freg2^"L" is fpr2x = 0 & freg2 & fr2half = 31 { export fr31L; } + +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 0 { export fr0R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 1 { export fpe3; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 2 { export fpe5; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 3 { export fpe7; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 4 { export fr4R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 5 { export fr5R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 6 { export fr6R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 7 { export fr7R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 8 { export fr8R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 9 { export fr9R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 10 { export fr10R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 11 { export fr11R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 12 { export fr12R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 13 { export fr13R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 14 { export fr14R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 15 { export fr15R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 16 { export fr16R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 17 { export fr17R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 18 { export fr18R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 19 { export fr19R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 20 { export fr20R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 21 { export fr21R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 22 { export fr22R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 23 { export fr23R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 24 { export fr24R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 25 { export fr25R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 26 { export fr26R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 27 { export fr27R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 28 { export fr28R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 29 { export fr29R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 30 { export fr30R; } +FPR232: freg2^"R" is freg2 & fpr2x = 1 & fr2half = 31 { export fr31R; } + +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 0 { export fr0L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 1 { export fpe2; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 2 { export fpe4; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 3 { export fpe6; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 4 { export fr4L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 5 { export fr5L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 6 { export fr6L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 7 { export fr7L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 8 { export fr8L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 9 { export fr9L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 10 { export fr10L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 11 { export fr11L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 12 { export fr12L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 13 { export fr13L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 14 { export fr14L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 15 { export fr15L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 16 { export fr16L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 17 { export fr17L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 18 { export fr18L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 19 { export fr19L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 20 { export fr20L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 21 { export fr21L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 22 { export fr22L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 23 { export fr23L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 24 { export fr24L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 25 { export fr25L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 26 { export fr26L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 27 { export fr27L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 28 { export fr28L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 29 { export fr29L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 30 { export fr30L; } +FPRT32: fpt^"L" is fptx = 0 & fpt & fpthalf = 31 { export fr31L; } + +# 32 bit fp register access, upper half (R) +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 0 { export fr0R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 1 { export fpe3; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 2 { export fpe5; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 3 { export fpe7; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 4 { export fr4R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 5 { export fr5R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 6 { export fr6R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 7 { export fr7R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 8 { export fr8R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 9 { export fr9R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 10 { export fr10R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 11 { export fr11R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 12 { export fr12R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 13 { export fr13R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 14 { export fr14R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 15 { export fr15R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 16 { export fr16R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 17 { export fr17R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 18 { export fr18R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 19 { export fr19R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 20 { export fr20R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 21 { export fr21R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 22 { export fr22R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 23 { export fr23R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 24 { export fr24R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 25 { export fr25R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 26 { export fr26R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 27 { export fr27R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 28 { export fr28R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 29 { export fr29R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 30 { export fr30R; } +FPRT32: fpt^"R" is fptx = 1 & fpt & fpthalf = 31 { export fr31R; } + + +fpcmp: ",FALSE?" is fpcond=0 { result:1 = 0; export result; } +fpcmp: ",false" is fpcond=1 { result:1 = 0; export result; } +fpcmp: ",?" is fpcond=2 { result:1 = 0; export result; } +fpcmp: ",!<=>" is fpcond=3 { result:1 = 0; export result; } +fpcmp: ",=" is fpcond=4 & FPR132 & FPR232 { result:1 = FPR232 f== FPR132; export result; } +fpcmp: ",=T" is fpcond=5 & FPR132 & FPR232 { result:1 = FPR232 f== FPR132; export result; } +fpcmp: ",?=" is fpcond=6 & FPR132 & FPR232 { result:1 = FPR232 f== FPR132; export result; } +fpcmp: ",!<>" is fpcond=7 & FPR132 & FPR232 { result:1 = FPR232 f== FPR132; export result; } +fpcmp: ",!?>=" is fpcond=8 & FPR132 & FPR232 { result:1 = FPR232 f< FPR132; export result; } +fpcmp: ",<" is fpcond=9 & FPR132 & FPR232 { result:1 = FPR232 f< FPR132; export result; } +fpcmp: ",?<" is fpcond=10 & FPR132 & FPR232 { result:1 = FPR232 f< FPR132; export result; } +fpcmp: ",!>=" is fpcond=11 & FPR132 & FPR232 { result:1 = FPR232 f< FPR132; export result; } +fpcmp: ",!?>" is fpcond=12 & FPR132 & FPR232 { result:1 = FPR232 f<= FPR132; export result; } +fpcmp: ",<=" is fpcond=13 & FPR132 & FPR232 { result:1 = FPR232 f<= FPR132; export result; } +fpcmp: ",?<=" is fpcond=14 & FPR132 & FPR232 { result:1 = FPR232 f<= FPR132; export result; } +fpcmp: ",!>" is fpcond=15 & FPR132 & FPR232 { result:1 = FPR232 f<= FPR132; export result; } +fpcmp: ",!?<=" is fpcond=16 & FPR132 & FPR232 { result:1 = FPR232 f> FPR132; export result; } +fpcmp: ",>" is fpcond=17 & FPR132 & FPR232 { result:1 = FPR232 f> FPR132; export result; } +fpcmp: ",?>" is fpcond=18 & FPR132 & FPR232 { result:1 = FPR232 f> FPR132; export result; } +fpcmp: ",!<=" is fpcond=19 & FPR132 & FPR232 { result:1 = FPR232 f> FPR132; export result; } +fpcmp: ",!?<" is fpcond=20 & FPR132 & FPR232 { result:1 = FPR232 f>= FPR132; export result; } +fpcmp: ",>=" is fpcond=21 & FPR132 & FPR232 { result:1 = FPR232 f>= FPR132; export result; } +fpcmp: ",?>=" is fpcond=22 & FPR132 & FPR232 { result:1 = FPR232 f>= FPR132; export result; } +fpcmp: ",!<;" is fpcond=23 & FPR132 & FPR232 { result:1 = FPR232 f>= FPR132; export result; } +fpcmp: ",!?=" is fpcond=24 & FPR132 & FPR232 { result:1 = FPR232 f!= FPR132; export result; } +fpcmp: ",<>" is fpcond=25 & FPR132 & FPR232 { result:1 = FPR232 f!= FPR132; export result; } +fpcmp: ",!=" is fpcond=26 & FPR132 & FPR232 { result:1 = FPR232 f!= FPR132; export result; } +fpcmp: ",!=T" is fpcond=27 & FPR132 & FPR232 { result:1 = FPR232 f!= FPR132; export result; } +fpcmp: ",!?" is fpcond=28 { result:1 = 1; export result; } +fpcmp: ",<=>" is fpcond=29 { result:1 = 1; export result; } +fpcmp: ",TRUE?" is fpcond=30 { result:1 = 1; export result; } +fpcmp: ",TRUE" is fpcond=31 { result:1 = 1; export result; } + +fpcmp64: ",FALSE?" is fpcond=0 { result:1 = 0; export result; } +fpcmp64: ",false" is fpcond=1 { result:1 = 0; export result; } +fpcmp64: ",?" is fpcond=2 { result:1 = 0; export result; } +fpcmp64: ",!<=>;" is fpcond=3 { result:1 = 0; export result; } +fpcmp64: ",=" is fpcond=4 & FPR164 & FPR264 { result:1 = FPR264 f== FPR164; export result; } +fpcmp64: ",=T" is fpcond=5 & FPR164 & FPR264 { result:1 = FPR264 f== FPR164; export result; } +fpcmp64: ",?=" is fpcond=6 & FPR164 & FPR264 { result:1 = FPR264 f== FPR164; export result; } +fpcmp64: ",!<>" is fpcond=7 & FPR164 & FPR264 { result:1 = FPR264 f== FPR164; export result; } +fpcmp64: ",!?>=" is fpcond=8 & FPR164 & FPR264 { result:1 = FPR264 f< FPR164; export result; } +fpcmp64: ",<" is fpcond=9 & FPR164 & FPR264 { result:1 = FPR264 f< FPR164; export result; } +fpcmp64: ",?<" is fpcond=10 & FPR164 & FPR264 { result:1 = FPR264 f< FPR164; export result; } +fpcmp64: ",!>=" is fpcond=11 & FPR164 & FPR264 { result:1 = FPR264 f< FPR164; export result; } +fpcmp64: ",!?>" is fpcond=12 & FPR164 & FPR264 { result:1 = FPR264 f<= FPR164; export result; } +fpcmp64: ",<=" is fpcond=13 & FPR164 & FPR264 { result:1 = FPR264 f<= FPR164; export result; } +fpcmp64: ",?<=" is fpcond=14 & FPR164 & FPR264 { result:1 = FPR264 f<= FPR164; export result; } +fpcmp64: ",!>" is fpcond=15 & FPR164 & FPR264 { result:1 = FPR264 f<= FPR164; export result; } +fpcmp64: ",!?<=" is fpcond=16 & FPR164 & FPR264 { result:1 = FPR264 f> FPR164; export result; } +fpcmp64: ",>" is fpcond=17 & FPR164 & FPR264 { result:1 = FPR264 f> FPR164; export result; } +fpcmp64: ",?>" is fpcond=18 & FPR164 & FPR264 { result:1 = FPR264 f> FPR164; export result; } +fpcmp64: ",!<=" is fpcond=19 & FPR164 & FPR264 { result:1 = FPR264 f> FPR164; export result; } +fpcmp64: ",!?<" is fpcond=20 & FPR164 & FPR264 { result:1 = FPR264 f>= FPR164; export result; } +fpcmp64: ",>=" is fpcond=21 & FPR164 & FPR264 { result:1 = FPR264 f>= FPR164; export result; } +fpcmp64: ",?>=" is fpcond=22 & FPR164 & FPR264 { result:1 = FPR264 f>= FPR164; export result; } +fpcmp64: ",!<" is fpcond=23 & FPR164 & FPR264 { result:1 = FPR264 f>= FPR164; export result; } +fpcmp64: ",!?=" is fpcond=24 & FPR164 & FPR264 { result:1 = FPR264 f!= FPR164; export result; } +fpcmp64: ",<>" is fpcond=25 & FPR164 & FPR264 { result:1 = FPR264 f!= FPR164; export result; } +fpcmp64: ",!=" is fpcond=26 & FPR164 & FPR264 { result:1 = FPR264 f!= FPR164; export result; } +fpcmp64: ",!=T" is fpcond=27 & FPR164 & FPR264 { result:1 = FPR264 f!= FPR164; export result; } +fpcmp64: ",!?" is fpcond=28 { result:1 = 1; export result; } +fpcmp64: ",<=>" is fpcond=29 { result:1 = 1; export result; } +fpcmp64: ",TRUE?" is fpcond=30 { result:1 = 1; export result; } +fpcmp64: ",TRUE" is fpcond=31 { result:1 = 1; export result; } + + +################################# +# space register subconstructors +################################# +SR: "srN" is s = 0 { export 0:4; } +SR: sr1 is s = 1 & sr1 { export sr1; } +SR: sr2 is s = 2 & sr2 { export sr2; } +SR: sr3 is s = 3 & sr3 { export sr3; } + +SR3bit: sr0 is srbit2=0 & srbit1=0 & srbit0=0 & sr0 { export sr0; } +SR3bit: sr1 is srbit2=0 & srbit1=0 & srbit0=1 & sr1 { export sr1; } +SR3bit: sr2 is srbit2=0 & srbit1=1 & srbit0=0 & sr2 { export sr2; } +SR3bit: sr3 is srbit2=0 & srbit1=1 & srbit0=1 & sr3 { export sr3; } +SR3bit: sr4 is srbit2=1 & srbit1=0 & srbit0=0 & sr4 { export sr4; } +SR3bit: sr5 is srbit2=1 & srbit1=0 & srbit0=1 & sr5 { export sr5; } +SR3bit: sr6 is srbit2=1 & srbit1=1 & srbit0=0 & sr6 { export sr6; } +SR3bit: sr7 is srbit2=1 & srbit1=1 & srbit0=1 & sr7 { export sr7; } + +# These two are the cosmetic constructors for printing purposes +# They print out SR,RB or else just RB if the space register is determined by the lower bits of RB +# s=0 means use the least significant two bits of the address in RB as the space register selection (added to 4) +SRRB: (RB) is RB & s=0 { } +# s=1-3 means use SR1 - SR3 +SRRB: (SR,RB) is SR & RB { } + +# BE uses three bits for the space register +SRRB3bit: (SR3bit,RB) is SR3bit & RB { } + +# these are the semantic constructors dealing with space registers +# this first one gets the value in the appropriate space register and returns it. +# it is used by LDSID. +SRVAL: SR is SR & RB & s=0 { + local selbits = (RB >> 30); + srreg:4 = &sr4 + 4 * selbits; + spc:4 = *[register] srreg; + export spc; +} + +SRVAL: sr1 is sr1 & s=1 { export sr1; } +SRVAL: sr2 is sr2 & s=2 { export sr2; } +SRVAL: sr3 is sr3 & s=3 { export sr3; } + +# TODO This is broken until we decide on how to handle space registers and a 64 bit extended address space +SPCBASE: is SRVAL & RB { +# space:$(ADDRSIZE) = zext(SRVAL); + off:$(ADDRSIZE) = zext(RB); # need to decide whether to remove the lower bits to hide privilege-- TODO & 0xFFFFFFFFFFFFFFFC; +# address:$(ADDRSIZE) = (space << 32) | offset; +# export address; + export off; +} + +############################################### +# encodings for branches +############################################### +# 12 bit displacement encoded using assemble_12 +displacement2W: target is w & w2 [ target = (1-(w*2)) * ( ((w2 & 0x1) << 10) | ((w2>>1) & 0x3FF) ); ] { temp:$(ADDRSIZE) = target; export temp; } +#branchTarget2W: target is w & w2 [ target = inst_start + 8 + 4 * ( (w * 0xFFFFFFFFFFFFF800) | ((w2 & 0x1) << 10) | ((w2>>1) & 0x3FF) ); ] { temp:$(ADDRSIZE) = target; export temp; } +# this has the space register added +#branchTarget2W: target is w & w2 [ target = inst_start + 8 + 4 * ( (w * 0xFFFFFFFFFFFFF800) | ((w2 & 0x1) << 10) | ((w2>>1) & 0x3FF) ); ] { temp:$(ADDRSIZE) = target; temp = temp + (iasq_front<<32); export *:$(ADDRSIZE) temp; } +##### good before caret branchTarget2W: target is w & w2 [ target = inst_start + 8 + 4 * ( (w * 0xFFFFFFFFFFFFF800) | ((w2 & 0x1) << 10) | ((w2>>1) & 0x3FF) ); ] { export *:$(ADDRSIZE) target; } +#branchTarget2W: target is w & w2 [ +branchTarget2W: target is w & w2less2 & w2_2 + [ +# target = inst_start + 8 + 4 * ( (w * 0xFFFFFFFFFFFFF800) | ((w2 & 0x1) << 10) | ((w2>>1) & 0x3FF) ); + target = inst_start + 8 + 4 * ( + ((-1 * w) << 11) | + (w2_2 << 10) | + w2less2 + ); + temp32 = branchImmDest; + branchImmDest = target; + globalset(inst_next, branchImmDest); + branchImmDest = temp32; + ] + { export *:$(ADDRSIZE) target; } + + +# 17 bit displacement encoded using assemble_17 +#displacement3W: target is w & w1 & w2 [ target = 4 * ( (w * 0xFFFFFFFFFFFF0000) | (w1 << 11) | ((w2 & 0x1) << 10) | ((w2>>1) & 0x3FF) ); ] { temp:$(ADDRSIZE) = target; export temp; } +displacement3W: target is w & w1 & w2less2 & w2_2 [ target = 4 * ( + ((-1 * w) << 16) | + (w1 << 11) | + (w2_2 << 10) | + w2less2 +);] { temp:$(ADDRSIZE) = target; export temp; } +#branchTarget3W: target is w & w1 & w2 [ target = inst_start + 8 + 4 * ( (w * 0xFFFFFFFFFFFF0000) | (w1 << 11) | ((w2 & 0x1) << 10) | ((w2>>1) & 0x3FF) ); ] { temp:$(ADDRSIZE) = target; export temp; } +#branchTarget3W: target is w & w1 & w2 [ target = inst_start + 8 + 4 * ( (w * 0xFFFFFFFFFFFF0000) | (w1 << 11) | ((w2 & 0x1) << 10) | ((w2>>1) & 0x3FF) ); ] { temp:$(ADDRSIZE) = target; target = target + (iasq_front << 32); export temp; } +#####good before caret branchTarget3W: target is w & w1 & w2 [ target = inst_start + 8 + 4 * ( (w * 0xFFFFFFFFFFFF0000) | (w1 << 11) | ((w2 & 0x1) << 10) | ((w2>>1) & 0x3FF) ); ] { export *:$(ADDRSIZE) target; } +#branchTarget3W: target is w & w1 & w2 +branchTarget3W: target is w & w1 & w2less2 & w2_2 + [ +# target = inst_start + 8 + 4 * ( (w * 0xFFFFFFFFFFFF0000) | (w1 << 11) | ((w2 & 0x1) << 10) | ((w2>>1) & 0x3FF) ); + target = inst_start + 8 + 4 * ( + ((-1 * w) << 16) | + (w1 << 11) | + (w2_2 << 10) | + w2less2 + ); + temp32 = branchImmDest; + branchImmDest = target; + globalset(inst_next, branchImmDest); + branchImmDest = temp32; + ] + { export *:$(ADDRSIZE) target; } + +# simple IP relative branch +IPRelativeIndexedTarget: is RX +{ + target:$(ADDRSIZE) = inst_start + (RX<<3) + 8; + branchIndDest = target; + export target; +} + +# vectored (base register plus index register) branch +IndexedTarget: is RX & RB + { + target:$(ADDRSIZE) = (RX<<3) + RB; + branchIndDest = target; + export target; + } + +# vectored (base register plus index register -- but index register is r0 so skip it since this is a return) branch +ReturnTarget: is RB + { + branchIndDest = RB; + export RB; + } + +# generate the target address for an external branch +externalTarget: displacement3W^SRRB3bit is RB & displacement3W & SRRB3bit { +# spaceID:$(ADDRSIZE) = zext(SRVAL); +# spaceID = spaceID << 32; +# spaceID:$(ADDRSIZE) = 0; +# currently ignoring the spaceID TODO FIX THIS? +# target = spaceID + sext(RB) + sext(displacement3W); + target:$(ADDRSIZE) = sext(displacement3W) + sext(RB); + branchIndDest = target; + export target; +} + +shiftC: shift is cp [ shift=31-cp; ] { amount:4 = shift; export amount; } +shiftCLen: shift is im5 [ shift=32-im5; ] { amount:4 = shift; export amount; } + +#lse14: offset is sim14 & bit0 [ offset = (-1 * bit0) * ( (sim14 >> 1) & 0x1FFF ); ] { temp:4 = offset; export temp; } +#lse14: offset is sim14 & bit0 [ offset = (-1 * 0x2000 * bit0) | ( (sim14 >> 1) & 0x1FFF ); ] { temp:4 = sext(offset:4); export temp; } +lse14: off is im14less0 & bit0 [ off = ((-1 * bit0) << 13) | im14less0; ] { temp:4 = sext(off:4); export temp; } +####lse14: offset is sim14 & bit0 [ offset = (0xFFFFFFFFFFFFE000 * bit0) | ( (sim14 >> 1) & 0x1FFF ); ] { temp:4 = offset; export temp; } + +#lse5: offset is sim5 & bit0 [ offset = (-1 * 0x10 * bit0) | ( (sim5 >> 1) & 0xF ); ] { temp:1 = sext(offset:1); export temp; } +lse5: off is im5less0 & bit0 [ off = ((-1 * bit0) << 4) | im5less0; ] { temp:1 = sext(off:1); export temp; } + +#highlse5: offset is highIm5 & bit16 [ offset = (-1 * 0x10 * bit16) | ( (highIm5 >> 1) & 0xF ); ] { temp:1 = offset; export temp; } +highlse5: off is highIm5less16 & bit16 [ off = ((-1 * bit16) << 4) | highIm5less16; ] { temp:1 = off; export temp; } + +#lse21: offset is sim21 [ offset = ( ((sim21 & 0x1) * 0xFFFFFFFFFFF00000) | ((sim21 & 0xFFE) << 8) | ((sim21 & 0xC000) >> 7) | ((sim21 & 0x1F0000) >> 14) | ((sim21 & 0x3000) >> 12) ) << 11 ; ] { temp:$(REGSIZE) = offset; export temp; } +lse21: off is im21less0 & bit0 & im21_1_12 & im21_12_14 & im21_14_16 & im21_16_21 [ + off = ( + ((-1 * bit0) << 20) | + (im21_1_12 << 9) | + (im21_14_16 << 7) | + (im21_16_21 << 2) | + im21_12_14 + ) << 11; +] { temp:$(REGSIZE) = off; export temp; } + +# Note for the im11 11-bit immediate, the sign is in bit 0, and the rest of the value is in bit 1 to 10. +# Negative numbers are stored 2s complement, with bit0 set to 1. +# +# Need to set temp32 to lse11 since the value of lse11 does not propogate so well to uplevel tables, maybe a compiler bug +# +#lse11: immed is im11 & bit0 +lse11: immed is im11less0 & bit0 + [ immed = ((-1*bit0) << 10) | im11less0; temp32 = immed; ] +# [ immed = (bit0 * 0xFFFFFFFFFFFFFC00) | ( (im11 >> 1) & 0x3FF ); temp32 = immed; ] + { temp:4 = immed; export temp; } + +OFF_BASE_14: lse14^SRRB is lse14 & SRRB & SPCBASE { temp:$(ADDRSIZE) = SPCBASE + sext(lse14); export temp; } + +############################# +# condition codes +############################# + +# shift conditions. There are no inverted forms of these conditions. +ShiftCond: is c=0 { export 0:1; } # never +ShiftCond: is c=1 & RT { tmp:1 = (nullifyCondResult == 0) ; export tmp; } # equal +ShiftCond: is c=2 & RT { tmp:1 = (((nullifyCondResult >> ($(REGSIZE)*8 - 1)) & 1) != 0) ; export tmp; } # leftmost bit is one +ShiftCond: is c=3 & RT { tmp:1 = ((nullifyCondResult & 0x1) != 0) ; export tmp; } # rightmost bit is 1 (odd) +ShiftCond: is c=4 { export 1:1; } # always +ShiftCond: is c=5 & RT { tmp:1 = (nullifyCondResult != 0) ; export tmp; } # some bits are one +ShiftCond: is c=6 & RT { tmp:1 = (((nullifyCondResult >> ($(REGSIZE)*8 - 1)) & 1) == 0) ; export tmp; } # leftmost bit is zero +ShiftCond: is c=7 & RT { tmp:1 = ((nullifyCondResult & 0x1) == 0) ; export tmp; } # rightmost bit is zero (even) + +ShiftCondNullify: is c=0 { } +ShiftCondNullify: is ShiftCond [ nullifyEnable = 1; globalset(inst_next, nullifyEnable); ] +{ + nullifyNextCond = ShiftCond; +} + +# deposit conditions. There are no inverted forms of these conditions. +DepCond: is c=0 { export 0:1; } # never +DepCond: is c=1 { tmp:1 = (nullifyCondResult == 0) ; export tmp; } # equal +DepCond: is c=2 { tmp:1 = (nullifyCondResult s< 0) ; export tmp; } # leftmost bit is one (< 0) +DepCond: is c=3 { tmp:1 = ((nullifyCondResult & 0x1) == 1) ; export tmp; } # rightmost bit is 1 (odd) +DepCond: is c=4 { export 1:1; } # always +DepCond: is c=5 { tmp:1 = (nullifyCondResult != 0) ; export tmp; } # some bits are one +DepCond: is c=6 { tmp:1 = (nullifyCondResult s>= 0) ; export tmp; } # leftmost bit is zero (>=) +DepCond: is c=7 { tmp:1 = ((nullifyCondResult & 0x1) == 0) ; export tmp; } # rightmost bit is zero (even) + +DepCondNullify: is c=0 { } +DepCondNullify: is DepCond [nullifyEnable = 1; globalset(inst_next, nullifyEnable); ] +{ + nullifyNextCond = DepCond; +} + +# extract conditions. The extract ops target R1, not R2 like deposit does +ExtrCond: is c=0 { export 0:1; } # never +ExtrCond: is c=1 { tmp:1 = (nullifyCondResult == 0); export tmp; } # equal +ExtrCond: is c=2 { tmp:1 = (((nullifyCondResult >> ($(REGSIZE)*8 - 1)) & 1) != 0); export tmp; } # leftmost bit is one +ExtrCond: is c=3 { tmp:1 = ((nullifyCondResult & 0x1) != 0) ; export tmp; } # rightmost bit is 1 (odd) +ExtrCond: is c=4 { export 1:1; } # always +ExtrCond: is c=5 { tmp:1 = (nullifyCondResult != 0); export tmp; } # some bits are one +ExtrCond: is c=6 { tmp:1 = (((nullifyCondResult >> ($(REGSIZE)*8 - 1)) & 1) == 0); export tmp; } # leftmost bit is zero +ExtrCond: is c=7 { tmp:1 = ((nullifyCondResult & 0x1) == 0); export tmp; } # rightmost bit is zero (even) + +ExtrCondNullify: is c=0 { } +ExtrCondNullify: is ExtrCond [ nullifyEnable = 1; globalset(inst_next, nullifyEnable); ] +{ + nullifyNextCond = ExtrCond; +} + + +# a subset of the SED conditions used for bit tests +BVBCond: is c=2 & R1 { tmp:1 = ((R1 >> (31-sar)) & 0x1) == 1 ; export tmp; } # target bit is one +BVBCond: is c=6 & R1 { tmp:1 = ((R1 >> (31-sar)) & 0x1) == 0 ; export tmp; } # target bit is zero + +BBCond: is c=2 & R1 & bboffset { tmp:1 = ((R1 >> (31-bboffset)) & 0x1) == 1 ; export tmp; } # target bit is one +BBCond: is c=6 & R1 & bboffset { tmp:1 = ((R1 >> (31-bboffset)) & 0x1) == 0 ; export tmp; } # target bit is zero + +# +# unit conditions for checking byte ranges within a word +# +RegUnitCond: is c=0 { export 0:1; } # never +RegUnitCond: is c=2 & RT { tmp:1 = (RT:1 == 0) || ((RT:2 & 0xFF00) == 0) || ((RT:3 & 0xFF0000) == 0) || ((RT & 0xFF000000) == 0) ; export tmp; } # some byte zero +RegUnitCond: is c=3 & RT { tmp:1 = ((RT:2 & 0xFFFF) == 0) || ((RT & 0xFFFF0000) == 0) ; export tmp; } # some halfword zero +RegUnitCond: is c=4 { export 0:1; } # some digit carry -- TODO FIGURE OUT BCD +RegUnitCond: is c=6 { export 0:1; } # some byte carry -- TODO BCD +RegUnitCond: is c=7 { export 0:1; } # some halfword carry -- TODO BCD + +UnitCond: "" is RegUnitCond & fv=0 { export RegUnitCond; } +UnitCond: "" is RegUnitCond & fv=1 { tmp:1 = ! RegUnitCond; export tmp; } + +UnitCondNullify: is c=0 & fv=0 { } +UnitCondNullify: is UnitCond [ nullifyEnable = 1; globalset(inst_next, nullifyEnable); ] +{ + nullifyNextCond = UnitCond; +} + +UnitCondSym: RegUnitCondSym is RegUnitCondSym & fv=0 { } +UnitCondSym: InvUnitCondSym is InvUnitCondSym & fv=1 { } + +# +##### The Add Conditions from table 5-4 on page 5-5 +# +RegAddCond: is c = 0 { export 0:1; } # never +RegAddCond: is c = 1 & R1 & R2 { tmp:1 = (R1 == R2) ; export tmp; } # equal +RegAddCond: is c = 2 & R1 & R2 { tmp:1 = (R1 s< -R2) ; export tmp; } # signed less than negative of R2 +RegAddCond: is c = 3 & R1 & R2 { tmp:1 = (R1 s<= R2) ; export tmp; } # signed less than or equal to R2 +RegAddCond: is c = 4 & R1 & R2 { tmp:1 = ! carry(R1,R2) ; export tmp; } # unsigned sum does not overflow +RegAddCond: is c = 5 & R1 & R2 { tmp:1 = (R1 + R2) == 0 ; export tmp; } # sum is zero or no overflow (why two definitions??) +RegAddCond: is c = 6 & R1 & R2 { tmp:1 = scarry(R1,R2); export tmp; } # signed sum overflows +RegAddCond: is c = 7 & R1 & R2 { tmp:1 = ((R1+R2) & 0x1) == 0x1 ; export tmp; } # sum is odd + +AddCond: is RegAddCond & fv=0 { export RegAddCond; } +AddCond: is RegAddCond & fv=1 { tmp:1 = ! RegAddCond; export tmp; } + +AddCondNullify: is c=0 & fv=0 { } +AddCondNullify: is AddCond [ nullifyEnable=1; globalset(inst_next, nullifyEnable); ] +{ + nullifyNextCond = AddCond; +} + +AddCondSym: RegAddCondSym is RegAddCondSym & fv=0 { } +AddCondSym: InvAddCondSym is InvAddCondSym & fv=1 { } + +RegAddCondI: is c = 0 { export 0:1; } # never +RegAddCondI: is c = 1 & highlse5 & R2 { val:$(REGSIZE) = sext(highlse5:1); tmp:1 = (val == -R2) ; export tmp; } # equal to negated +RegAddCondI: is c = 2 & highlse5 & R2 { val:$(REGSIZE) = sext(highlse5:1); tmp:1 = (val s< -R2) ; export tmp; } # signed less than negated R2 +RegAddCondI: is c = 3 & highlse5 & R2 { val:$(REGSIZE) = sext(highlse5:1); tmp:1 = (val s<= -R2) ; export tmp; } # signed less than or equal to R2 +RegAddCondI: is c = 4 & highlse5 & R2 { val:$(REGSIZE) = sext(highlse5:1); tmp:1 = ! carry(val,R2) ; export tmp; } # unsigned sum does not overflow +RegAddCondI: is c = 5 & highlse5 & R2 { val:$(REGSIZE) = sext(highlse5:1); tmp:1 = (val + R2) == 0 ; export tmp; } # sum is zero or no overflow (why two definitions??) +RegAddCondI: is c = 6 & highlse5 & R2 { val:$(REGSIZE) = sext(highlse5:1); tmp:1 = scarry(val,R2); export tmp; } # signed sum overflows +RegAddCondI: is c = 7 & highlse5 & R2 { val:$(REGSIZE) = sext(highlse5:1); tmp:1 = ((val+R2) & 0x1) == 0x1 ; export tmp; } # sum is odd + + +# Some notes- +# lse11 is derived from an 11-bit immediate, so we need to take 2 bytes, not 1 byte as in the original coding +# R2 must sometimes be negated before the comparison, as per the manual, Table 5-4 +# The arithmetic comparison must be performed on a larger size temp than the original, so that negating 0x80000000 works correctly +# temp32 is used because the value of lse11 in the pcode does not flow so well to here - maybe a compiler bug? +# + +RegAddCondI11: is c = 0 { export 0:1; } # never + +RegAddCondI11: is temp32 & c = 1 & lse11 & R2 { + val:8 = sext(temp32:2); tmp_R2:8 = sext(R2); + tmp:1 = (val == -tmp_R2) ; export tmp; } # equal + +RegAddCondI11: is temp32 & c = 2 & lse11 & R2 { + val:8 = sext(temp32:2); tmp_R2:8 = sext(R2); + tmp:1 = (val s< -tmp_R2) ; export tmp; } # signed less than negative of R2 + +RegAddCondI11: is temp32 & c = 3 & lse11 & R2 { + val:8 = sext(temp32:2); tmp_R2:8 = sext(R2); + tmp:1 = (val s<= -tmp_R2) ; export tmp; } # signed less than or equal to R2 + +RegAddCondI11: is temp32 & c = 4 & lse11 & R2 { + val:$(REGSIZE) = sext(temp32:2); + tmp:1 = ! carry(val,R2) ; export tmp; } # unsigned sum does not overflow + +RegAddCondI11: is temp32 & c = 5 & lse11 & R2 { + # Don't need 64-bit arithmetic here + val:$(REGSIZE) = sext(temp32:2); + tmp:1 = (val + R2) == 0 ; export tmp; } # sum is zero or no overflow (why two definitions??) + +RegAddCondI11: is temp32 & c = 6 & lse11 & R2 { + val:$(REGSIZE) = sext(temp32:2); + tmp:1 = scarry(val,R2); export tmp; } # signed sum overflows + +RegAddCondI11: is temp32 & c = 7 & lse11 & R2 { + val:8 = sext(temp32:2); tmp_R2:8 = sext(R2); + tmp:1 = ((val+tmp_R2) & 0x1) == 0x1 ; export tmp; } # sum is odd + +AddCondI11: is RegAddCondI11 & fv=0 { export RegAddCondI11; } +AddCondI11: is RegAddCondI11 & fv=1 { temp:1 = ! RegAddCondI11; export temp; } + +AddCondI11Nullify: is c=0 & fv=0 { } +AddCondI11Nullify: is AddCondI11 [ nullifyEnable=1; globalset(inst_next, nullifyEnable); ] +{ + nullifyNextCond = AddCondI11; +} + +# +#### Compare / Subtract Instructions +# +RegCSCond: is c=0 & R1 & R2 { export 0:1; } # never +RegCSCond: is c=1 & R1 & R2 { tmp:1 = (R1 == R2) ; export tmp; } # equal +RegCSCond: is c=2 & R1 & R2 { tmp:1 = (R1 s< R2) ; export tmp; } # signed less than +RegCSCond: is c=3 & R1 & R2 { tmp:1 = (R1 s<= R2) ; export tmp; } # signed less than equal +RegCSCond: is c=4 & R1 & R2 { tmp:1 = (R1 < R2) ; export tmp; } # unsigned less than +RegCSCond: is c=5 & R1 & R2 { tmp:1 = (R1 <= R2) ; export tmp; } # unsigned less than equal +RegCSCond: is c=6 & R1 & R2 { tmp:1 = sborrow(R1,R2) ; export tmp; } # signed minus overflows (borrows) +RegCSCond: is c=7 & R1 & R2 { tmp:1 = ((R1 - R2) & 0x1) == 1 ; export tmp; } # odd + +CSCond: is fv=0 & RegCSCond { export RegCSCond; } +CSCond: is fv=1 & RegCSCond { tmp:1 = ! RegCSCond; export tmp; } + +CSCondNullify: is c=0 & fv=0 { } +CSCondNullify: is CSCond [ nullifyEnable = 1; globalset(inst_next, nullifyEnable); ] +{ + nullifyNextCond = CSCond; +} + +CSCondSym: RegCSCondSym is RegCSCondSym & fv=0 { } +CSCondSym: InvCSCondSym is InvCSCondSym & fv=1 { } + +# The Compare or Subtract conditions compared with 5 bit immediates +# This is used in the COMIB[TF] instructions. The inverted versions are never used. +RegCSCondI: is c=0 & R2 & highlse5 { export 0:1; } # never +RegCSCondI: is c=1 & R2 & highlse5 { val:$(REGSIZE) = sext(highlse5); tmp:1 = (val == R2) ; export tmp; } # equal +RegCSCondI: is c=2 & R2 & highlse5 { val:$(REGSIZE) = sext(highlse5); tmp:1 = (val s< R2) ; export tmp; } # signed less than +RegCSCondI: is c=3 & R2 & highlse5 { val:$(REGSIZE) = sext(highlse5); tmp:1 = (val s<= R2) ; export tmp; } # signed less than equal +RegCSCondI: is c=4 & R2 & highlse5 { val:$(REGSIZE) = sext(highlse5); tmp:1 = (val < R2) ; export tmp; } # unsigned less than +RegCSCondI: is c=5 & R2 & highlse5 { val:$(REGSIZE) = sext(highlse5); tmp:1 = (val <= R2) ; export tmp; } # unsigned less than equal +RegCSCondI: is c=6 & R2 & highlse5 { val:$(REGSIZE) = sext(highlse5); local diff = (val - R2); tmp:1 = (val s> 0 && R2 s> 0 && diff s< 0) || (val s< 0 && R2 s< 0 && diff s> 0) ; export tmp; } # overflow +RegCSCondI: is c=7 & R2 & highlse5 { val:$(REGSIZE) = sext(highlse5); tmp:1 = ((val - R2) & 0x1) == 1 ; export tmp; } # odd + +# The Compare or Subtract conditions compared with 11 bit immediates. These are used with the SUBI[O] and COMICLR instructions. Both regular and inverted forms are used. +RegCSCondI11: is c=0 & R2 & lse11 { export 0:1; } # never +RegCSCondI11: is c=1 & R2 & lse11 { val:$(REGSIZE) = sext(lse11); tmp:1 = (val == R2) ; export tmp; } # equal +RegCSCondI11: is c=2 & R2 & lse11 { val:$(REGSIZE) = sext(lse11); tmp:1 = (val s< R2) ; export tmp; } # signed less than +RegCSCondI11: is c=3 & R2 & lse11 { val:$(REGSIZE) = sext(lse11); tmp:1 = (val s<= R2) ; export tmp; } # signed less than equal +RegCSCondI11: is c=4 & R2 & lse11 { val:$(REGSIZE) = sext(lse11); tmp:1 = (val < R2) ; export tmp; } # unsigned less than +RegCSCondI11: is c=5 & R2 & lse11 { val:$(REGSIZE) = sext(lse11); tmp:1 = (val <= R2) ; export tmp; } # unsigned less than equal +RegCSCondI11: is c=6 & R2 & lse11 { val:$(REGSIZE) = sext(lse11); local diff = (val - R2); tmp:1 = (val s> 0 && R2 s> 0 && diff s< 0) || (val s< 0 && R2 s< 0 && diff s> 0) ; export tmp; } # overflow +RegCSCondI11: is c=7 & R2 & lse11 { val:$(REGSIZE) = sext(lse11); tmp:1 = ((val - R2) & 0x1) == 1 ; export tmp; } # odd + +CSCondI11: is RegCSCondI11 & fv=0 { export RegCSCondI11; } +CSCondI11: is RegCSCondI11 & fv=1 { temp:1 = ! RegCSCondI11; export temp; } + +CSCondI11Nullify: is c=0 & fv=0 { } +CSCondI11Nullify: is CSCondI11 [ nullifyEnable = 1; globalset(inst_next, nullifyEnable); ] +{ + nullifyNextCond = CSCondI11; +} + +# +#### Logical Conditions +# +RegLogicCond: is c=0 { export 0:1; } # never +RegLogicCond: is c=1 & RT { tmp:1 = (RT == 0) ; export tmp; } # equal, all zeros +RegLogicCond: is c=2 & RT { tmp:1 = (RT & 0x80000000) != 0 ; export tmp; } # <, leftmost bit is 1 +RegLogicCond: is c=3 & RT { tmp:1 = ((RT & 0x80000000) != 0) || RT == 0 ; export tmp; } # <=, leftmost bit is 1 or all bits are zero +RegLogicCond: is c=7 & RT { tmp:1 = (RT & 0x1) == 0x1; export tmp; } # odd, rightmost bit is 1 + +LogicCond: is fv=0 & RegLogicCond { tmp:1 = RegLogicCond; export tmp; } # non-inverted cases +LogicCond: is fv=1 & RegLogicCond { tmp:1 = ! RegLogicCond; export tmp; } # inverted cases + +LogicCondSym: RegLogicCondSym is RegLogicCondSym & fv=0 { } +LogicCondSym: InvLogicCondSym is InvLogicCondSym & fv=1 { } + +LogicCondNullify: is c=0 & fv=0 { } +LogicCondNullify: is LogicCond [ nullifyEnable = 1; globalset(inst_next, nullifyEnable); ] +{ + nullifyNextCond = LogicCond; +} + +########################################## +# Completers from the tables in chapter 5 +########################################## + +# Table 5-11 on page 5-22 +# The shifted form for byte doesn't shift, as byte addressing is single byte aligned +indexedByteAccessCmplt: is u=0 & m=0 & RX & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext(RX); export off; } # none +indexedByteAccessCmplt: ",M" is u=0 & m=1 & RX & RB & SPCBASE { off:$(ADDRSIZE) = SPCBASE; RB = RB + RX; export off; } # M, modify, post inc by RX +indexedByteAccessCmplt: ",S" is u=1 & m=0 & RX & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext(RX); export off; } # S, shift left by 2 +indexedByteAccessCmplt: ",SM" is u=1 & m=1 & RX & RB & SPCBASE { off:$(ADDRSIZE) = SPCBASE; RB = RB + sext(RX); export off; } # SM, shift and modify + +# The shifted form for halfword shifts by 2 bytes, since that is the size of a halfword +indexedHalfwordAccessCmplt: is u=0 & m=0 & RX & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext(RX); export off; } # none +indexedHalfwordAccessCmplt: ",M" is u=0 & m=1 & RX & RB & SPCBASE { off:$(ADDRSIZE) = SPCBASE; RB = RB + RX; export off; } # M, modify, post inc by RX +indexedHalfwordAccessCmplt: ",S" is u=1 & m=0 & RX & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext((RX << 1)); export off; } # S, shift left by 1 +indexedHalfwordAccessCmplt: ",SM" is u=1 & m=1 & RX & RB & SPCBASE { off:$(ADDRSIZE) = SPCBASE; RB = RB + sext(RX << 1); export off; } # SM, shift and modify + +# The shifted form for words shifts by 2 (x4), since words are aligned on 4 and increment by 4 +indexedWordAccessCmplt: is u=0 & m=0 & RX & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext(RX); export off; } # none +indexedWordAccessCmplt: ",M" is u=0 & m=1 & RX & RB & SPCBASE { off:$(ADDRSIZE) = SPCBASE; RB = RB + RX; export off; } # M, modify, post inc by RX +indexedWordAccessCmplt: ",S" is u=1 & m=0 & RX & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext((RX << 2)); export off; } # S, shift left by 2 +indexedWordAccessCmplt: ",SM" is u=1 & m=1 & RX & RB & SPCBASE { off:$(ADDRSIZE) = SPCBASE; RB = RB + sext(RX << 2); export off; } # SM, shift and modify + +# same as above, but shifts by 3 bits. Used for the LDCWX instruction +indexedDoublewordAccessCmplt: is u=0 & m=0 & RX & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext(RX); export off; } # none +indexedDoublewordAccessCmplt: ",M" is u=0 & m=1 & RX & RB & SPCBASE { off:$(ADDRSIZE) = SPCBASE; RB = RB + RX; export off; } # M, modify, post inc by RX +indexedDoublewordAccessCmplt: ",S" is u=1 & m=0 & RX & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext((RX << 3)); export off; } # S, shift left by 3 NOTE YES THIS IS 3 +indexedDoublewordAccessCmplt: ",SM" is u=1 & m=1 & RX & RB & SPCBASE { off:$(ADDRSIZE) = SPCBASE; RB = RB + sext(RX << 3); export off; } # SM, shift and modify + +# Table 5-12 on Page 5-24 +# these are for loads, e.g. ldws +shortDispCmplt: is m=0 & highlse5 & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext(highlse5); export off; } # no modification +shortDispCmplt: ",MA" is u=0 & m=1 & RB & RX & SPCBASE & highlse5 { off:$(ADDRSIZE) = SPCBASE; RB = RB + sext(highlse5); export off; } # modify after +shortDispCmplt: ",MB" is u=1 & m=1 & RB & RX & SPCBASE & highlse5 { local lse = sext(highlse5); off:$(ADDRSIZE) = SPCBASE + sext(lse); RB = RB + lse; export off; } # modify before + +# short displacement for stores, e.g. stws +storeShortDispCmplt: is m=0 & lse5 & SPCBASE { off:$(ADDRSIZE) = SPCBASE + sext(lse5); export off; } # no modification +storeShortDispCmplt: ",MA" is u=0 & m=1 & RB & RX & SPCBASE & lse5 { off:$(ADDRSIZE) = SPCBASE; RB = RB + sext(lse5); export off; } # modify after +storeShortDispCmplt: ",MB" is u=1 & m=1 & RB & RX & SPCBASE & lse5 { local lse = sext(lse5); off:$(ADDRSIZE) = SPCBASE + sext(lse); RB = RB + lse; export off; } # modify before + +# Table 5-13 on page 5-26 +storeBytesShortCmplt: is u=0 & m=0 & SPCBASE & lse5 { off:$(ADDRSIZE) = SPCBASE + sext(lse5); export off; } # none / beginning, don't modify base register +storeBytesShortCmplt: ",BM" is u=0 & m=1 & SPCBASE & RR & lse5 { off:$(ADDRSIZE) = SPCBASE + sext(lse5); RR = (RR + sext(lse5)) & 0xFFFFFFFC; export off; } # beginning, modify base register +storeBytesShortCmplt: ",E" is u=1 & m=0 & SPCBASE & lse5 { off:$(ADDRSIZE) = SPCBASE + sext(lse5); export off; } # ending, don't modify +storeBytesShortCmplt: ",EM" is u=1 & m=1 & SPCBASE & RR & lse5 { off:$(ADDRSIZE) = SPCBASE + sext(lse5); RR = (RR + sext(lse5)) & 0xFFFFFFFC; export off; } # ending, modify + +# u fixed at 0, Table 5-11 on page 5-22, for LPA and related system level opcodes +sysCmplt: is m=0 { } +sysCmplt: ",M" is m=1 { } + +# Table 5-8 on page 5-17 +loadCC: is cc=0 { } +loadCC: ",SL" is cc=2 { } + +# Table 5-9 on page 5-18 +storeCC: is cc=0 { } +storeCC: ",BC" is cc=1 { } +storeCC: ",SL" is cc=2 { } + +# Table 5-10 on page 5-18 +loadClearCC: is cc=0 { } +loadClearCC: ",CO" is cc=1 { } + +# nullification as used with branches +#####nullifyForBranch: is n=0 { export 0:1; } +#####nullifyForBranch: ",N" is n=1 { export 1:1; } +# caret versions +nullifyForBranch: is n=0 { export 0:1; } +nullifyForBranch: ",N" is n=1 [ nullifyEnable = 1; globalset(inst_next, nullifyEnable); ] { export 1:1; } + +nullifySymForBranch: is n=0 { } +nullifySymForBranch: ",N" is n=1 { } + +# nullification as used with special function unit ops +nullifyForSpecial: is spn=0 { } +nullifyForSpecial: ",N" is spn=1 { } + +# Floating point completers +#csize: "SGL" is fpsize=0 & opfam=0x0C { } +#csize: "DBL" is fpsize=1 & opfam=0x0C { } +#csize: "QUAD" is fpsize=3 & opfam=0x0C { } + +#esize: "SGL" is fpsize=0 & opfam=0x0E { } +#esize: "DBL" is fpsize=1 & opfam=0x0E { } + +SFU: sfu is sfu { } + + diff --git a/python/icicle/Ghidra/Processors/PA-RISC/data/languages/pa-risc32.cspec b/python/icicle/Ghidra/Processors/PA-RISC/data/languages/pa-risc32.cspec new file mode 100644 index 0000000..b7a57f4 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PA-RISC/data/languages/pa-risc32.cspec @@ -0,0 +1,70 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PA-RISC/data/languages/pa-risc32.pspec b/python/icicle/Ghidra/Processors/PA-RISC/data/languages/pa-risc32.pspec new file mode 100644 index 0000000..e5ed661 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PA-RISC/data/languages/pa-risc32.pspec @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PA-RISC/data/languages/pa-risc32be.slaspec b/python/icicle/Ghidra/Processors/PA-RISC/data/languages/pa-risc32be.slaspec new file mode 100644 index 0000000..03148ca --- /dev/null +++ b/python/icicle/Ghidra/Processors/PA-RISC/data/languages/pa-risc32be.slaspec @@ -0,0 +1,8 @@ +# SLA specification file for PA-RISC 32 bit big endian + +@define ENDIAN "big" +@define BITS "32" + +@include "pa-risc.sinc" +@include "pa-riscInstructions.sinc" + diff --git a/python/icicle/Ghidra/Processors/PA-RISC/data/languages/pa-riscInstructions.sinc b/python/icicle/Ghidra/Processors/PA-RISC/data/languages/pa-riscInstructions.sinc new file mode 100644 index 0000000..7e5211d --- /dev/null +++ b/python/icicle/Ghidra/Processors/PA-RISC/data/languages/pa-riscInstructions.sinc @@ -0,0 +1,1884 @@ +############################ +# +# PA-RISC 1.1 Instructions +# +############################ + +with : phase=1 { + +############################ +# Load and Store and Address Generation Instructions +############################ +:LDW OFF_BASE_14,R1dst is opfam=0x12 & OFF_BASE_14 & R1dst { + addr:$(ADDRSIZE) = OFF_BASE_14; + R1dst = zext(*[ram]:4 addr) ; + } + +:LDH OFF_BASE_14,R1dst is opfam=0x11 & OFF_BASE_14 & R1dst { + addr:$(ADDRSIZE) = OFF_BASE_14; + R1dst = zext(*[ram]:2 addr) ; +} + +:LDB OFF_BASE_14,R1dst is opfam=0x10 & OFF_BASE_14 & R1dst { + addr:$(ADDRSIZE) = OFF_BASE_14; + R1dst = zext(*[ram]:1 addr) ; +} + +:STW R1,OFF_BASE_14 is opfam=0x1A & OFF_BASE_14 & R1 { + addr:$(ADDRSIZE) = OFF_BASE_14; + *[ram]:4 addr = R1:4; + } + +:STH R1,OFF_BASE_14 is opfam=0x19 & R1 & OFF_BASE_14 { + addr:$(ADDRSIZE) = OFF_BASE_14; + *[ram]:2 addr = R1:2; +} +:STB R1,OFF_BASE_14 is opfam=0x18 & OFF_BASE_14 & R1 { + addr:$(ADDRSIZE) = OFF_BASE_14; + *[ram]:1 addr = R1:1; +} + +:LDW^",M" OFF_BASE_14,R1dst is opfam=0x13 & OFF_BASE_14 & R1dst & RB & SPCBASE & lse14 { + off:$(ADDRSIZE) = 0; + if (lse14 s>= 0x0) goto ; + off = sext(lse14); + + addr:$(ADDRSIZE) = SPCBASE + off; + RB = RB + lse14; + R1dst = zext( *[ram]:4 addr ); +} + +:STW^",M" R1,OFF_BASE_14 is opfam=0x1B & OFF_BASE_14 & R1 & RB & SPCBASE & lse14 { + addr:$(ADDRSIZE) = SPCBASE; + local imm = sext(lse14); + if (imm s>= 0x0) goto ; + addr = addr + imm; + + *[ram]:4 addr = R1; + RB = RB + imm; +} + +# LDWX +:LDW^indexedWordAccessCmplt^loadCC RX^SRRB,RT is opfam=0x03 & subop=2 & zero=0 & indexedWordAccessCmplt & loadCC & RX & RT & SRRB { + address:$(ADDRSIZE) = indexedWordAccessCmplt; + RT = zext(*[ram]:4 address) ; + } + + #LDHX +:LDH^indexedHalfwordAccessCmplt^loadCC RX^SRRB,RT is opfam=0x03 & subop=1 & zero=0 & indexedHalfwordAccessCmplt & loadCC & RX & SRRB & RT { + address:$(ADDRSIZE) = indexedHalfwordAccessCmplt; + RT = zext(*[ram]:2 address) ; +} + +#LDBX +:LDB^indexedByteAccessCmplt^loadCC RX^SRRB,RT is opfam=0x03 & subop=0 & zero=0 & indexedByteAccessCmplt & loadCC & RX & SRRB & RT { + address:$(ADDRSIZE) = indexedByteAccessCmplt; + RT = zext(*[ram]:1 address) ; +} + +# same as LDWX, except that it checks privilege levels +:LDWAX^indexedWordAccessCmplt^loadCC RX(RB),RT is opfam=0x03 & subop=6 & zero=0 & s=0 & indexedWordAccessCmplt & loadCC & RX & SRRB & RB & RT { + address:$(ADDRSIZE) = indexedWordAccessCmplt; + RT = zext(*[ram]:4 address) ; +} + +:LDCWX^indexedDoublewordAccessCmplt^loadClearCC RX^SRRB,RT is opfam=0x03 & subop=7 & zero=0 & indexedDoublewordAccessCmplt & loadClearCC & RX & SRRB & RT { + address:$(ADDRSIZE) = indexedDoublewordAccessCmplt; + RT = zext(*[ram]:4 address); + *[ram]:4 address = 0:4; + } + +# LDWS +:LDW^shortDispCmplt^loadCC highlse5^SRRB,RT is opfam=0x03 & subop=2 & one=1 & shortDispCmplt & loadCC & highlse5 & SRRB & RT { + addr:$(ADDRSIZE) = shortDispCmplt; + RT = zext(*[ram]:4 addr) ; +} + +# LDHS +:LDH^shortDispCmplt^loadCC highlse5^SRRB,RT is opfam=0x03 & subop=1 & one=1 & shortDispCmplt & loadCC & highlse5 & SRRB & RT { + addr:$(ADDRSIZE) = shortDispCmplt; + RT = zext(*[ram]:2 addr) ; +} + +# LDBS +:LDB^shortDispCmplt^loadCC highlse5^SRRB,RT is opfam=0x03 & subop=0 & one=1 & shortDispCmplt & loadCC & highlse5 & SRRB & RT { + addr:$(ADDRSIZE) = shortDispCmplt; + RT = zext(*[ram]:1 addr) ; +} + +#STWS +:STW^storeShortDispCmplt^storeCC RR,lse5^SRRB is opfam=0x03 & subop=0xA & one=1 & storeShortDispCmplt & storeCC & lse5 & SRRB & RR { + addr:$(ADDRSIZE) = storeShortDispCmplt; + *[ram]:4 addr = RR:4; +} + +#STHS +:STH^storeShortDispCmplt^storeCC RR,lse5^SRRB is opfam=0x03 & subop=0x9 & one=1 & storeShortDispCmplt & storeCC & lse5 & SRRB & RR { + addr:$(ADDRSIZE) = storeShortDispCmplt; + *[ram]:2 addr = RR:2; +} + +#STBS +:STB^storeShortDispCmplt^storeCC RR,lse5^SRRB is opfam=0x03 & subop=0x8 & one=1 & storeShortDispCmplt & storeCC & lse5 & SRRB & RR { + addr:$(ADDRSIZE) = storeShortDispCmplt; + *[ram]:1 addr = RR:1; +} + +:LDWAS^shortDispCmplt^loadCC highlse5(RB),RT is opfam=0x03 & subop=6 & one=1 & shortDispCmplt & loadCC & highlse5 & RB & RT { + addr:$(ADDRSIZE) = shortDispCmplt; + RT = zext(*[ram]:4 addr) ; +} + +:LDCWS^shortDispCmplt^loadClearCC highlse5^SRRB,RT is opfam=0x03 & subop=7 & one=1 & shortDispCmplt & loadClearCC & highlse5 & SRRB & RT { + address:$(ADDRSIZE) = shortDispCmplt; + RT = zext(*:4 address); + *[ram]:4 address = 0:4; +} + +:STWAS^shortDispCmplt^storeCC RR,lse5(RB) is opfam=0x03 & subop=0xE & one=1 & shortDispCmplt & storeCC & lse5 & RB & RR { + addr:$(ADDRSIZE) = shortDispCmplt; + *[ram] :4 addr = RR:4; +} + +# This is the "begin" version for big endian. I am not doing the little endian version. +:STBYS^storeBytesShortCmplt^storeCC RR,lse5^SRRB is opfam=0x03 & subop=0xC & one=1 & storeBytesShortCmplt & storeCC & lse5 & SRRB & RR & u=0 { + # get the address, which is most likely not word aligned + addr:$(ADDRSIZE) = storeBytesShortCmplt; + # figure out how many bytes need to be written + local numBytes = 4 - (addr & 0x3); + # this is the address where we stop (one byte past the last address to which we write) + local finalAddr = addr + numBytes; + # copy the contents of RR + data:$(REGSIZE) = RR >> ((4 - numBytes) * 8); + # use a for loop to write out the 1,2,3, or 4 bytes + + if (addr == finalAddr) goto ; + *[ram]:1 addr = data:1; + data = data >> 8; + addr = addr + 1; + goto ; + +} + +# This is the "end" version for big endian. I am not doing the little endian version. +:STBYS^storeBytesShortCmplt^storeCC RR,lse5^SRRB is opfam=0x03 & subop=0xC & one=1 & storeBytesShortCmplt & storeCC & lse5 & SRRB & RR & u=1 { + # get the address, which is most likely not word aligned + addr:$(ADDRSIZE) = storeBytesShortCmplt; + # figure out how many bytes need to be written + local numBytes = (addr & 0x3); + # now make a word aligned address + addr = addr & 0x3; + # this is the address where we stop (one byte past the last address to which we write) + local finalAddr = addr + numBytes; + # copy the contents of RR + data:$(REGSIZE) = RR >> ((4 - numBytes) * 8); + + # use a for loop to write out the 1,2,3, or 4 bytes + + if (addr == finalAddr) goto ; + *[ram]:1 addr = data:1; + data = data >> 8; + addr = addr + 1; + goto ; + +} + +# Note: LDO and LDIL do not access memory, they just load an address into a register +# LDI is a pseudo-op that is commonly used to load immediate values into registers. The values may or may not be addresses. +:LDO lse14(RB),R1dst is opfam=0x0D & lse14 & RB & R1dst { + R1dst = RB + lse14; + } + +# LDO is often used as a copy operator, so when the offset is zero, we display it as a copy +:COPY RB,R1dst is opfam=0x0D & im14=0 & RB & R1dst { + R1dst = RB; + } + +:LDI lse14,R1dst is opfam=0x0D & b=0 & lse14 & R1dst { + R1dst = lse14; +} + +:LDIL lse21,R2 is opfam=0x08 & R2 & lse21 { + R2 = lse21; +} + +# this instruction adds lse21 + R2 and puts the result into the hard coded r1 register +# (not the register specified by bitfield reg1, the actual register r1) +:ADDIL lse21, R2, r1 is opfam=0x0A & R2 & lse21 & r1 { + r1 = R2 + lse21; +} + +################################################################################ +# Branch Instructions +################################################################################ + +################################################################################ +# unconditional immediate calls +################################################################################ +# non-nullifying unconditional immediate call +:B^",L"^nullifyForBranch branchTarget3W,R2dst is opfam=0x3A & c=0x0 & R2dst & nullifyForBranch & n=0 & branchTarget3W & $(COMMON) + [ + branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 1; # unconditional imm call + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + R2dst = inst_start+8; + branchExecuted = 1; +} + +# nullifying unconditional immediate call +# special case that doesn't need the deferral mechanism +:B^",L"^nullifySymForBranch branchTarget3W,R2dst is opfam=0x3A & c=0x0 & R2dst & nullifySymForBranch & n=1 & branchTarget3W & $(COMMON) +{ + R2dst = inst_start+8; + call branchTarget3W; +} + +################################################################################ +# unconditional immediate branches +# since PA-RISC doesn't have a straight branch without link, it uses branch and link into the R0 register. +# By having a second op for it, we can use a goto and prevent analysis tools from thinking this is a legitimate subroutine call +################################################################################ +# non-nullifying unconditional immediate branch (no link) +:B^nullifyForBranch branchTarget3W is opfam=0x3A & c=0x0 & reg2=0 & nullifyForBranch & n=0 & branchTarget3W & $(COMMON) + [ + branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 0; # unconditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + + ] +{ + branchExecuted = 1; +} + +# nullifying unconditional immediate branch (no link) +# This is a special case, as we just do the branch and don't use +# our defered branching mechanism +:B^nullifySymForBranch branchTarget3W is opfam=0x3A & c=0x0 & reg2=0 & nullifySymForBranch & n=1 & branchTarget3W & $(COMMON) +{ + goto branchTarget3W; +} + +################################################################################ +# conditional immediate branches - comparison with registers +################################################################################ +:CMPBT^RegCSCondSym^nullifyForBranch R1,R2,branchTarget2W is opfam=0x20 & R1 & R2 & nullifyForBranch & n=0 & branchTarget2W & RegCSCondSym & RegCSCond & $(COMMON) + [ branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 2; # conditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + branchCond = RegCSCond; + branchExecuted = 1; +} + + :CMPBT^RegCSCondSym^nullifyForBranch R1,R2,branchTarget2W is opfam=0x20 & R1 & R2 & nullifyForBranch & n=1 & branchTarget2W & displacement2W & RegCSCondSym & RegCSCond & $(COMMON) + [ branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 2; # conditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + branchCond = RegCSCond; + branchExecuted = 1; + nullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) ); +} + +:CMPBF^RegCSCondSym^nullifyForBranch R1,R2,branchTarget2W is opfam=0x22 & R1 & R2 & nullifyForBranch & n=0 & branchTarget2W & RegCSCondSym & RegCSCond & $(COMMON) + [ branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 2; # conditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + branchCond = ! RegCSCond; + branchExecuted = 1; +} + +:CMPBF^RegCSCondSym^nullifyForBranch R1,R2,branchTarget2W is opfam=0x22 & R1 & R2 & nullifyForBranch & n=1 & branchTarget2W & displacement2W & RegCSCondSym & RegCSCond & $(COMMON) + [ branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 2; # conditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + branchCond = ! RegCSCond; + branchExecuted = 1; + nullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) ); +} + +################################################################################ +# conditional immediate branches -- comparison with immediates +################################################################################ +:CMPIBT^RegCSCondSym^nullifyForBranch highlse5,R2,branchTarget2W is opfam=0x21 & highlse5 & R2 & nullifyForBranch & branchTarget2W & RegCSCondSym & RegCSCondI & n=0 & $(COMMON) + [ branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 2; # conditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + branchCond = RegCSCondI; + branchExecuted = 1; +} + +:CMPIBT^RegCSCondSym^nullifyForBranch highlse5,R2,branchTarget2W is opfam=0x21 & highlse5 & R2 & nullifyForBranch & branchTarget2W & displacement2W & RegCSCondSym & RegCSCondI & n=1 & $(COMMON) + [ branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 2; # conditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + branchCond = RegCSCondI; + branchExecuted = 1; + nullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) ); +} + +:CMPIBF^RegCSCondSym^nullifyForBranch highlse5,R2,branchTarget2W is opfam=0x23 & highlse5 & R2 & nullifyForBranch & branchTarget2W & RegCSCondSym & RegCSCondI & n=0 & $(COMMON) + [ branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 2; # conditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + branchCond = !RegCSCondI; + branchExecuted = 1; +} + +:CMPIBF^RegCSCondSym^nullifyForBranch highlse5,R2,branchTarget2W is opfam=0x23 & highlse5 & R2 & nullifyForBranch & branchTarget2W & displacement2W & RegCSCondSym & RegCSCondI & n=1 & $(COMMON) + [ branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 2; # conditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + branchCond = !RegCSCondI; + branchExecuted = 1; + nullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) ); +} + +################################################################################ +# unconditional indirect calls & branches +################################################################################ +# IP relative unconditional indirect call +:BLR^nullifyForBranch RR,R2dst is opfam=0x3A & c=0x2 & R2dst & nullifyForBranch & RR & IPRelativeIndexedTarget & n=0 & $(COMMON) + [ + branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 5; # unconditional indirect call + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + R2dst = inst_start+8; + branchExecuted = 1; +} + +# IP relative unconditional indirect call +:BLR^nullifySymForBranch RR,R2dst is opfam=0x3A & c=0x2 & R2dst & nullifySymForBranch & RR & IPRelativeIndexedTarget & n=1 & $(COMMON) +{ + R2dst = inst_start+8; + call [branchIndDest]; +} + +# vectored (offset register plus index register) unconditional indirect branch +:BV^nullifyForBranch RX(RB) is opfam=0x3A & c=0x6 & RB & nullifyForBranch & RX & IndexedTarget & bit0=0 & n=0 & $(COMMON) + [ + branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 4; # unconditional indirect branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + branchExecuted = 1; +} + +# vectored (offset register plus index register) unconditional indirect branch +:BV^nullifySymForBranch RX(RB) is opfam=0x3A & c=0x6 & RB & nullifySymForBranch & RX & IndexedTarget & bit0=0 & n=1 & $(COMMON) +{ + goto [branchIndDest]; +} + +# this is the idiom for return from subroutine +# currently we pull it out so we don't print out the R0, but we could modify this to do a return... +:BV^nullifyForBranch (RB) is opfam=0x3A & c=0x6 & RB & nullifyForBranch & reg1=0 & ReturnTarget & bit0=0 & n=0 & $(COMMON) + [ + branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 4; # unconditional indirect branch + globalset(inst_next, branchType); + branchIsReturn=1; + globalset(inst_next, branchIsReturn); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + branchExecuted = 1; +} + +# this is the idiom for return from subroutine +# currently we pull it out so we don't print out the R0, but we could modify this to do a return... +:BV^nullifyForBranch (RB) is opfam=0x3A & c=0x6 & RB & nullifyForBranch & reg1=0 & ReturnTarget & bit0=0 & n=1 & $(COMMON) +{ + return [branchIndDest]; +} + +########################### + +#### MOVB + +:MOVB^SEDCondSym^nullifyForBranch R1,R2dst,branchTarget2W is opfam=0x32 & R2dst & R1 & nullifyForBranch & branchTarget2W & DepCond & SEDCondSym & n=0 & $(COMMON) + [ branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 2; # conditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + R2dst = R1; + nullifyCondResult = R1; + build DepCond; # force the condition evaluation after the move + branchCond = DepCond; + branchExecuted = 1; +} + +:MOVB^SEDCondSym^nullifyForBranch R1,R2dst,branchTarget2W is opfam=0x32 & R2dst & R1 & nullifyForBranch & branchTarget2W & displacement2W & DepCond & SEDCondSym & n=1 & $(COMMON) + [ branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 2; # conditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + R2dst = R1; + nullifyCondResult = R1; + build DepCond; # force the condition evaluation after the move + branchCond = DepCond; + branchExecuted = 1; + nullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) ); +} + +########################### + +#### MOVIB + +:MOVIB^SEDCondSym^nullifyForBranch im5,R2dst,branchTarget2W is opfam=0x33 & R2dst & im5 & nullifyForBranch & branchTarget2W & DepCond & SEDCondSym & n=0 & $(COMMON) + [ branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 2; # conditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + R2dst = sext(im5:1); + nullifyCondResult = sext(im5:1); + build DepCond; # force the condition evaluation after the move + branchExecuted = 1; + branchCond = DepCond; +} + +:MOVIB^SEDCondSym^nullifyForBranch im5,R2dst,branchTarget2W is opfam=0x33 & R2dst & im5 & nullifyForBranch & branchTarget2W & displacement2W & DepCond & SEDCondSym & n=1 & $(COMMON) + [ branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 2; # conditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + R2dst = sext(im5:1); + nullifyCondResult = sext(im5:1); + build DepCond; # force the condition evaluation after the move + branchCond = DepCond; + branchExecuted = 1; + nullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) ); +} + +########################### +:ADDBT^RegAddCondSym^nullifyForBranch R1,R2dst,branchTarget2W is opfam=0x28 & R1 & R2dst & R2 & nullifyForBranch & branchTarget2W & RegAddCond & RegAddCondSym & n=0 & $(COMMON) + [ branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 2; # conditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + build RegAddCond; # force the condition evaluation before the move + branchCond = RegAddCond; + branchExecuted = 1; + R2dst = R1 + R2; +} + +:ADDBT^RegAddCondSym^nullifyForBranch R1,R2dst,branchTarget2W is opfam=0x28 & R1 & R2dst & R2 & nullifyForBranch & branchTarget2W & displacement2W & RegAddCond & RegAddCondSym & n=1 & $(COMMON) + [ branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 2; # conditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + build RegAddCond; # force the condition evaluation before the move + branchCond = RegAddCond; + branchExecuted = 1; + nullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) ); + + R2dst = R1 + R2; +} + +########################### +:ADDBF^RegAddCondSym^nullifyForBranch R1,R2dst,branchTarget2W is opfam=0x2A & R1 & R2dst & R2 & nullifyForBranch & branchTarget2W & RegAddCond & RegAddCondSym & n=0 & $(COMMON) + [ branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 2; # conditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + build RegAddCond; # force the condition evaluation before the move + branchCond = !RegAddCond; + branchExecuted = 1; + R2dst = R1 + R2; +} + +:ADDBF^RegAddCondSym^nullifyForBranch R1,R2dst,branchTarget2W is opfam=0x2A & R1 & R2 & R2dst & nullifyForBranch & branchTarget2W & displacement2W & RegAddCondSym & RegAddCond & n=1 & $(COMMON) + [ branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 2; # conditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + build RegAddCond; # force the condition evaluation before the move + branchCond = !RegAddCond; + branchExecuted = 1; + nullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) ); + R2dst = R1 + R2; +} + +########################### +:ADDIBT^RegAddCondSym^nullifyForBranch highlse5,R2dst,branchTarget2W is opfam=0x29 & highlse5 & R2 & R2dst & nullifyForBranch & branchTarget2W & RegAddCondI & RegAddCondSym & n=0 & $(COMMON) + [ branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 2; # conditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + build RegAddCondI; # force the condition evaluation before the move + branchCond = RegAddCondI; + branchExecuted = 1; + R2dst = R2 + sext(highlse5); +} + +:ADDIBT^RegAddCondSym^nullifyForBranch highlse5,R2dst,branchTarget2W is opfam=0x29 & highlse5 & R2 & R2dst & nullifyForBranch & branchTarget2W & displacement2W & RegAddCondI & RegAddCondSym & n=1 & $(COMMON) + [ branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 2; # conditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + build RegAddCondI; # force the condition evaluation before the move + branchCond = RegAddCondI; + branchExecuted = 1; + nullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) ); + R2dst = R2 + sext(highlse5); +} + +:ADDIBF^RegAddCondSym^nullifyForBranch highlse5,R2dst,branchTarget2W is opfam=0x2B & highlse5 & R2 & R2dst & nullifyForBranch & branchTarget2W & RegAddCondI & RegAddCondSym & n=0 & $(COMMON) + [ branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 2; # conditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + build RegAddCondI; # force the condition evaluation before the move + branchCond = ! RegAddCondI; + branchExecuted = 1; + R2dst = R2 + sext(highlse5); +} + +:ADDIBF^RegAddCondSym^nullifyForBranch highlse5,R2dst,branchTarget2W is opfam=0x2B & highlse5 & R2 & R2dst & nullifyForBranch & branchTarget2W & displacement2W & RegAddCondI & RegAddCondSym & n=1 & $(COMMON) + [ branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 2; # conditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + build RegAddCondI; # force the condition evaluation before the move + branchCond = ! RegAddCondI; + branchExecuted = 1; + nullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) ); + R2dst = R2 + sext(highlse5); +} + +####################################### +:BB^SEDCondSym^nullifyForBranch R1,SAR,branchTarget2W is opfam=0x30 & branchTarget2W & nullifyForBranch & R1 & BVBCond & SEDCondSym & SAR & n=0 & $(COMMON) + [ branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 2; # conditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + branchCond = BVBCond; + branchExecuted = 1; +} + +:BB^SEDCondSym^nullifyForBranch R1,SAR,branchTarget2W is opfam=0x30 & branchTarget2W & nullifyForBranch & displacement2W & R1 & BVBCond & SEDCondSym & SAR & n=1 & $(COMMON) + [ branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 2; # conditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + branchCond = BVBCond; + branchExecuted = 1; + nullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) ); +} + +####################################### +:BB^SEDCondSym^nullifyForBranch R1,bboffset,branchTarget2W is opfam=0x31 & branchTarget2W & nullifyForBranch & R1 & BBCond & SEDCondSym & n=0 & bboffset & $(COMMON) + [ branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 2; # conditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + branchCond = BBCond; + branchExecuted = 1; +} + +:BB^SEDCondSym^nullifyForBranch R1,bboffset,branchTarget2W is opfam=0x31 & branchTarget2W & displacement2W & nullifyForBranch & R1 & BBCond & SEDCondSym & n=1 & bboffset & $(COMMON) + [ branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 2; # conditional imm branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + branchCond = BBCond; + branchExecuted = 1; + nullifyNextCond = ( ! branchCond && (displacement2W s< 0)) || ( branchCond && (displacement2W s>= 0) ); +} + +####################################### +# These instructions change the privilege level or the space register +define pcodeop changePrivLevel; +define pcodeop changeSpace; +define pcodeop getCurrentSpace; + +:BE^nullifyForBranch externalTarget is opfam=0x38 & nullifyForBranch & externalTarget & SR3bit & n=0 & $(COMMON) + [ + branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 4; # unconditional indirect branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + iasq_front = SR3bit; # set the space ID to the new space ID + # with the current deferral system, this will mean the sr is wrong during the delay slot + branchExecuted = 1; +} + +:BE^nullifyForBranch externalTarget is opfam=0x38 & nullifyForBranch & externalTarget & SR3bit & n=1 & $(COMMON) +{ + iasq_front = SR3bit; # set the space ID to the new space ID + goto [externalTarget]; +} + +:BE^",L"^nullifyForBranch externalTarget,SR0,R31 is opfam=0x39 & nullifyForBranch & SR0 & R31 & SR3bit & externalTarget & n=0 & $(COMMON) + [ + branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 5; # unconditional indirect call + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + r31 = inst_next+4; # store the link/return address + sr0 = iasq_front; # store the link/return space ID + iasq_front = SR3bit; # set the space ID to the new space ID + # with the current deferral system, this will mean the sr is wrong during the delay slot + branchExecuted = 1; +} + +:BE^",L"^nullifyForBranch externalTarget,SR0,R31 is opfam=0x39 & nullifyForBranch & SR0 & R31 & SR3bit & externalTarget & n=1 & $(COMMON) +{ + r31 = inst_next+4; # store the link/return address + sr0 = iasq_front; # store the link/return space ID + iasq_front = SR3bit; # set the space ID to the new space ID + call [externalTarget]; +} + +:B^",GATE"^nullifyForBranch branchTarget3W,R2dst is opfam=0x3A & c=0x1 & R2dst & nullifyForBranch & branchTarget3W & n=0 & $(COMMON) + [ + branchEnable = 1; + globalset(inst_next, branchEnable); + branchType = 0; # unconditional immediate branch + globalset(inst_next, branchType); + branchCouldBeNullified = nullifyEnable; + globalset(inst_next, branchCouldBeNullified); + ] +{ + R2dst = changePrivLevel(); + branchExecuted = 1; +} + +:B^",GATE"^nullifyForBranch branchTarget3W,R2dst is opfam=0x3A & c=0x1 & R2dst & nullifyForBranch & branchTarget3W & n=1 & $(COMMON) +{ + R2dst = changePrivLevel(); + goto [branchTarget3W]; +} + + +####################################### +####################################### +# General Arithmetic/Logic Instructions +####################################### +####################################### +define pcodeop trap; + +:ADD^AddCondSym R1,R2,RT is opfam=0x02 & op=0x18 & m=0 & R1 & R2 & RT & AddCondNullify & AddCondSym { + pswCB = carry(R1,R2); + RT = R1 + R2; + build AddCondNullify; +} + +# this version intentionally does not set the carry bits +:ADD^",L"^AddCondSym R1,R2,RT is opfam=0x02 & op=0x28 & m=0 & R1 & R2 & RT & AddCondNullify & AddCondSym { + RT = R1 + R2; + build AddCondNullify; +} + +:ADDO^AddCondSym R1,R2,RT is opfam=0x02 & op=0x38 & m=0 & R1 & R2 & RT & AddCondSym & AddCondNullify { + if (scarry(R1,R2)) goto ; + pswCB = carry(R1,R2); + RT = R1 + R2; + goto ; + + trap(); + + build AddCondNullify; +} + +:ADD^",C"^AddCondSym R1,R2,RT is opfam=0x02 & op=0x1C & m=0 & R1 & R2 & RT & AddCondSym & AddCondNullify { + local partialSum = R2 + zext(pswCB); + pswCB = carry(partialSum, R1); + RT = partialSum + R1; + build AddCondNullify; +} + +# TODO This may need some work +:ADD^",CO"^AddCondSym R1,R2,RT is opfam=0x02 & op=0x3C & m=0 & R1 & R2 & RT & AddCondSym & AddCondNullify { + local partialSum = R2 + zext(pswCB); + partialCarry:1 = carry(R2, zext(pswCB)); + partialOverflow:1 = scarry(R2, zext(pswCB)); + takeTrap:1 = partialOverflow == 0x1:1; + if (takeTrap) goto ; + RT = partialSum + R1; + finalCarry:1 = carry(partialSum, R1); + finalOverflow:1 = scarry(partialSum, R1); + takeTrap = finalOverflow == 0x1:1; + if (takeTrap) goto ; + goto ; + + trap(); + + pswCB = partialCarry ^ finalCarry; + build AddCondNullify; +} + +:SH1ADD^AddCondSym R1,R2,RT is opfam=0x02 & op=0x19 & m=0 & R1 & R2 & RT & AddCond & AddCondSym & AddCondNullify { + local shiftedR1 = R1 << 1; + pswCB = carry(shiftedR1,R2); + RT = shiftedR1 + R2; + build AddCondNullify; +} + +:SH1ADDL^AddCondSym R1,R2,RT is opfam=0x02 & op=0x29 & m=0 & R1 & R2 & RT & AddCondNullify & AddCondSym { + local shiftedR1 = R1 << 1; + RT = shiftedR1 + R2; + build AddCondNullify; +} + +:SH1ADDO^SEDCondSym R1,R2,RT is opfam=0x02 & op=0x39 & m=0 & R1 & R2 & RT & AddCondNullify & SEDCondSym { + local shiftedR1 = R1 << 1; + if (scarry(shiftedR1, R2)) goto ; + pswCB = carry(shiftedR1,R2); + RT = shiftedR1 + R2; + goto ; + + trap(); + + build AddCondNullify; +} + +:SH2ADD^SEDCondSym R1,R2,RT is opfam=0x02 & op=0x1A & m=0 & R1 & R2 & RT & AddCondNullify & SEDCondSym { + local shiftedR1 = R1 << 2; + pswCB = carry(shiftedR1,R2); + RT = shiftedR1 + R2; + build AddCondNullify; +} + +:SH2ADDL^AddCondSym R1,R2,RT is opfam=0x02 & op=0x2A & m=0 & R1 & R2 & RT & AddCondNullify & AddCondSym { + local shiftedR1 = R1 << 2; + RT = shiftedR1 + R2; + build AddCondNullify; +} + +:SH2ADDO^AddCondSym R1,R2,RT is opfam=0x02 & op=0x3A & m=0 & R1 & R2 & RT & AddCondNullify & AddCondSym { + local shiftedR1 = R1 << 2; + if (scarry(shiftedR1, R2)) goto ; + pswCB = carry(shiftedR1,R2); + RT = shiftedR1 + R2; + goto ; + + trap(); + + build AddCondNullify; +} + +:SH3ADD^AddCondSym R1,R2,RT is opfam=0x02 & op=0x1B & m=0 & R1 & R2 & RT & AddCondNullify & AddCondSym { + local shiftedR1 = R1 << 3; + pswCB = carry(shiftedR1,R2); + RT = shiftedR1 + R2; + build AddCondNullify; +} + +:SH3ADDL^AddCondSym R1,R2,RT is opfam=0x02 & op=0x2B & m=0 & R1 & R2 & RT & AddCondNullify & AddCondSym { + local shiftedR1 = R1 << 3; + RT = shiftedR1 + R2; + build AddCondNullify; +} + +:SH3ADDO^AddCondSym R1,R2,RT is opfam=0x02 & op=0x3B & m=0 & R1 & R2 & RT & AddCondNullify & AddCondSym { + local shiftedR1 = R1 << 3; + if (scarry(shiftedR1, R2)) goto ; + pswCB = carry(shiftedR1,R2); + RT = shiftedR1 + R2; + goto ; + + trap(); + + build AddCondNullify; +} + +:SUB^CSCondSym R1,R2,RT is opfam=0x02 & op=0x10 & m=0 & R1 & R2 & RT & CSCondSym & CSCondNullify { + pswCB = ! (R1 < R2); + RT = R1 - R2; + build CSCondNullify; +} + +:SUB",O"^CSCondSym R1,R2,RT is opfam=0x02 & op=0x30 & m=0 & R1 & R2 & RT & CSCondSym & CSCondNullify { + if (sborrow(R1,R2)) goto ; + pswCB = ! (R1 < R2); + RT = R1 - R2; + build CSCondNullify; + goto ; + + trap(); + +} + +:SUB",B"^CSCondSym R1,R2,RT is opfam=0x02 & op=0x14 & m=0 & R1 & R2 & RT & CSCondSym & CSCondNullify { + right:$(REGSIZE) = ~R2 + zext(pswCB); + pswCB = ! (R1 < right); #! carry(R1, right); + RT = R1 + right; + build CSCondNullify; +} + +:SUB",BO"^CSCondSym R1,R2,RT is opfam=0x02 & op=0x34 & m=0 & R1 & R2 & RT & CSCondSym & CSCondNullify { + right:$(REGSIZE) = ~R2 + zext(pswCB); + if (sborrow(R1,right)) goto ; + pswCB = ! (R1 < right); + RT = R1 + right; + build CSCondNullify; + goto ; + + trap(); + +} + +# subtract and trap on condition +# this instruction does not have a nullify form +:SUB",T"^CSCondSym R1,R2,RT is opfam=0x02 & op=0x13 & m=0 & R1 & R2 & RT & CSCondSym & CSCond { + pswCB = ! (R1 < R2); + RT = R1 - R2; + build CSCond; + if (CSCond) goto ; + goto ; + + trap(); + +} + +:SUB",TO"^CSCondSym R1,R2,RT is opfam=0x02 & op=0x33 & m=0 & R1 & R2 & RT & CSCondSym & CSCond { + if (sborrow(R1,R2)) goto ; + pswCB = ! (R1; + goto ; + + trap(); + +} + +# R1 is partial remainder, R2 is denominator, RT is updated partial remainder +:DS^CSCondSym R1,R2,RT is opfam=0x02 & op=0x11 & m=0 & R1 & R2 & RT & CSCondSym & CSCondNullify { + local origR2 = R2; + left:$(REGSIZE) = (R1 << 1) | zext(pswCB); + if (pswV) goto ; + right:$(REGSIZE) = R2; + goto ; + + right = ~R2 + 1; + + + RT = left + right; + + pswCB = carry(left,right); + +# handle pswV -- I'm using R2 here, the book says R2, but non-restoring algorithms usually use R1, so +# this could be the error. + shiftBit:1 = ((origR2 >> 31) & 0x1) == 1; + pswV = pswCB ^ shiftBit; + +# handle nullification -- TODO This condition is special and the stock CSCondNullify won't work -- broken -- see page 5-103 + build CSCondNullify; +} + +:CMPCLR^CSCondSym R1,R2,RT is opfam=0x02 & op=0x22 & m=0 & R1 & R2 & RT & CSCondSym & CSCondNullify +{ + build CSCondNullify; # must do this before setting register + RT = 0; +} + +# COPY is a pseudo-op using OR to move values between registers +:COPY R1,RT is opfam=0x02 & op=0x09 & m=0 & R1 & reg2=0 & RT & c=0 & fv=0 { + RT = R1; + } + +# nop is a pseudo-op for OR R0,R0, which is one way to make a nop +:NOP is opfam=0x02 & op=0x09 & m=0 & reg1=0 & reg2=0 & t=0 & c=0 & fv=0 { } # intentionally left blank + +:OR^LogicCondSym R1,R2,RT is opfam=0x02 & op=0x09 & m=0 & R1 & R2 & RT & LogicCondSym & LogicCondNullify { + RT = R1 | R2; + build LogicCondNullify; +} + +:XOR^LogicCondSym R1,R2,RT is opfam=0x02 & op=0x0A & m=0 & R1 & R2 & RT & LogicCondSym & LogicCondNullify { + RT = R1 ^ R2; + build LogicCondNullify; +} + +:AND^LogicCondSym R1,R2,RT is opfam=0x02 & op=0x08 & m=0 & R1 & R2 & RT & LogicCondSym & LogicCondNullify { + RT = R1 & R2; + build LogicCondNullify; +} + +:ANDCM^LogicCondSym R1,R2,RT is opfam=0x02 & op=0x00 & m=0 & R1 & R2 & RT & LogicCondSym & LogicCondNullify { + RT = R1 & ~R2; + build LogicCondNullify; +} + +:UXOR^UnitCondSym R1,R2,RT is opfam=0x02 & op=0x0E & m=0 & R1 & R2 & RT & UnitCondSym & UnitCondNullify { + RT = R1 ^ R2; + build UnitCondNullify; +} + +:UADDCM^UnitCondSym R1,R2,RT is opfam=0x02 & op=0x26 & m=0 & R1 & R2 & RT & UnitCondSym & UnitCondNullify { + RT = R1 + ~R2; + build UnitCondNullify; + +} + +:UADDCMT^UnitCondSym R1,R2,RT is opfam=0x02 & op=0x27 & m=0 & R1 & R2 & RT & UnitCond & UnitCondSym { + if (UnitCond) goto ; + RT = R1 + ~R2; + goto ; + + trap(); + +} + +:ADDI^AddCondSym lse11,R2,R1dst is opfam=0x2D & bit11=0 & lse11 & R2 & R1dst & AddCondSym & AddCondI11Nullify { + tmp:$(REGSIZE) = R2; # Don't clobber the original value, when R1 is the same as R2 + R1dst = R2 + lse11; + pswCB = carry(tmp,lse11); + build AddCondI11Nullify; +} + +# PA1.1 this is ADDIO, PA2.0 is ADDI,TSV (trap on signed overflow) +:ADDI^",TSV"^AddCondSym lse11,R2,R1dst is opfam=0x2D & bit11=1 & lse11 & R2 & R1dst & AddCondSym & AddCondI11Nullify { + tmp:$(REGSIZE) = R2; # Don't clobber the original value, when R1 is the same as R2 + if (scarry(R2, lse11) == 1:1) goto ; + R1dst = R2 + lse11; + pswCB = carry(tmp,sext(lse11)); + goto ; + + trap(); + + build AddCondI11Nullify; +} + +# PA11 this is ADDIT, PA2.0 this is ADDI,TC +:ADDI^",TC"^AddCondSym lse11,R2,R1dst is opfam=0x2C & bit11=0 & lse11 & R2 & R1dst & AddCondSym & AddCondI11 { + tmp:$(REGSIZE) = R2; # Don't clobber the original value, when R1 is the same as R2 + R1dst = R2 + lse11; + build AddCondI11; + if (AddCondI11) goto ; + pswCB = carry(tmp,lse11); + goto ; + + trap(); + +} + +# PA11 this is ADDITO, PA2.0 this is ADDI,TC,TSV +:ADDI^",TC,TSV"^AddCondSym lse11,R2,R1dst is opfam=0x2C & bit11=1 & lse11 & R2 & R1dst & AddCondSym & AddCondI11 { + tmp:$(REGSIZE) = R2; # Don't clobber the original value, when R1 is the same as R2 + R1dst = R2 + lse11; + build AddCondI11; + if (AddCondI11) goto ; + if (scarry(tmp, lse11) == 1:1) goto ; + pswCB = carry(tmp,lse11); + goto ; + + trap(); + +} + +:SUBI^CSCondSym lse11,R2,R1dst is opfam=0x25 & bit11=0 & lse11 & R2 & R1dst & CSCondI11Nullify & CSCondSym { + tmp:$(REGSIZE) = R2; # Don't clobber the original value, when R1 is the same as R2 + R1dst = lse11 - R2; + pswCB = !(lse11 < tmp); + build CSCondI11Nullify; +} + +:SUBI^",TSV"^CSCondSym lse11,R2,R1dst is opfam=0x25 & bit11=1 & lse11 & R2 & R1dst & CSCondI11 & CSCondSym & CSCondI11Nullify { + tmp:$(REGSIZE) = R2; # Don't clobber the original value, when R1 is the same as R2 + if (sborrow(lse11, R2) == 1:1) goto ; + R1dst = lse11 - R2; + pswCB = !(lse11 < tmp); + goto ; + + trap(); + + build CSCondI11Nullify; +} + +:CMPICLR^CSCondSym lse11,R2,R1dst is opfam=0x24 & bit11=0 & lse11 & R2 & R1dst & CSCondI11Nullify & CSCondSym +{ + R1dst = 0; +} + +:SHRPW^SEDCondSym R1,R2,SAR,RT is opfam=0x34 & subop1012=0 & bits59=0 & R1 & R2 & RT & ShiftCondNullify & SEDCondSym & SAR { + left:8 = zext( (R1 & 0x7FFFFFFF) ) << 32; + concat:8 = left | zext(R2); + concat = concat >> SAR; + nullifyCondResult=concat:$(REGSIZE); + RT = concat:4; + + build ShiftCondNullify; +} + +# previously this was shd, now is shrpw form 14 +:SHRPW^SEDCondSym R1,R2,shiftC,RT is opfam=0x34 & R2 & R1 & subop1012=2 & shiftC & RT & SEDCondSym & ShiftCondNullify { + left:8 = zext( (R1 & 0x7FFFFFFF) ) << 32; + concat:8 = left | zext(R2); + concat = concat >> shiftC; + nullifyCondResult=concat:$(REGSIZE); + RT = concat:4; + + build ShiftCondNullify; +} + +# extract unsigned using SAR +:EXTRW",U"^SEDCondSym R2,SAR,shiftCLen,R1dst is opfam=0x34 & bits59=0 & subop1012=4 & R2 & shiftCLen & R1dst & SEDCondSym & ExtrCondNullify & SAR { + local value = R2 >> (31-SAR); + mask:4 = 0xffffffff >> (32 - shiftCLen); + nullifyCondResult = value & mask; + R1dst = nullifyCondResult; + + build ExtrCondNullify; +} + +# extract signed using SAR +:EXTRW",S"^SEDCondSym R2,SAR,shiftCLen,R1dst is opfam=0x34 & bits59=0 & subop1012=5 & R2 & shiftCLen & R1dst & SEDCondSym & ExtrCondNullify & SAR { + local value = R2 s>> (31-SAR); + value = value << (32 - shiftCLen); + value = value s>> (32 - shiftCLen); + nullifyCondResult = value; + R1dst = value; + build ExtrCondNullify; +} + +# extract unsigned using immediate +:EXTRW^",U"^SEDCondSym R2,cp,shiftCLen,R1dst is opfam=0x34 & subop1012=6 & cp & R2 & shiftCLen & R1dst & SEDCondSym & ExtrCondNullify & shiftC { + local value = R2 >> shiftC; + mask:4 = 0xffffffff >> (32-shiftCLen); + nullifyCondResult = value & mask; + R1dst = nullifyCondResult; + + build ExtrCondNullify; +} + +# extract signed using immediate +:EXTRW^",S"^SEDCondSym R2,cp,shiftCLen,R1dst is opfam=0x34 & subop1012=7 & cp & R2 & shiftC & shiftCLen & R1dst & SEDCondSym & ExtrCondNullify { + local value = R2 s>> shiftC; + value = value << (32 - shiftCLen); + value = value s>> (32 - shiftCLen); + nullifyCondResult = value; + R1dst = value; + build ExtrCondNullify; +} + +# non-zeroing SAR version (VDEP) +:DEPW^SEDCondSym R1,SAR,shiftCLen,R2dst is opfam=0x35 & bits59=0 & subop1012=1 & R1 & R2 & R2dst & shiftCLen & DepCondNullify & SEDCondSym & SAR { + mask:4 = 0xffffffff >> (32-shiftCLen); + local value = R1 & mask; + value = value << (31-SAR); + mask = mask << (31-SAR); + local result = R2 & ~mask; + result = result | value; + R2dst = result; + nullifyCondResult = result; + + build DepCondNullify; +} + +# non-zeroing constant version (DEP) +:DEPW^SEDCondSym R1,shiftC,shiftCLen,R2dst is opfam=0x35 & subop1012=3 & shiftC & shiftCLen & R1 & R2 & R2dst & DepCondNullify & SEDCondSym & cp { + mask:4 = 0xffffffff >> (32-shiftCLen); + local value = R1 & mask; + value = value << cp; + mask = mask << cp; + local result = R2 & ~mask; + result = result | value; + R2dst = result; + nullifyCondResult = result; + build DepCondNullify; +} + +# non-zeroing immediate SAR version (VDEPI) +:DEPWI^SEDCondSym highlse5,SAR,shiftCLen,R2dst is opfam=0x35 & bits59=0 & subop1012=5 & shiftCLen & highlse5 & R2 & R2dst & DepCondNullify & SEDCondSym & SAR { + mask:4 = 0xffffffff >> (32 - shiftCLen); + depbits:4 = sext(highlse5); + depbits = sext(depbits); + local value = depbits & mask; + value = value << (31-SAR); + mask = mask << (31-SAR); + local result = R2 & ~mask; + result = result | value; + R2dst = result; + nullifyCondResult = result; + build DepCondNullify; +} + +# non-zeroing immediate constant version (DEPI) +:DEPWI^SEDCondSym highlse5,shiftC,shiftCLen,R2dst is opfam=0x35 & subop1012=7 & shiftC & highlse5 & R2 & R2dst & shiftCLen & DepCondNullify & SEDCondSym & cp { + mask:4 = 0xffffffff >> (32-shiftCLen); + depbits:4 = sext(highlse5); + local value = depbits & mask; + value = value << cp; + mask = mask << cp; + local result = R2 & ~mask; + result = result | value; + R2dst = result; + nullifyCondResult = result; + build DepCondNullify; +} + +# DEPW,Z SAR version (ZVDEP) +:DEPW",Z"^SEDCondSym R1,SAR,shiftCLen,R2dst is opfam=0x35 & bits59=0 & subop1012=0 & R1 & shiftCLen & R2 & R2dst & DepCondNullify & SEDCondSym & SAR { + mask:4 = 0xffffffff >> (32-shiftCLen); + local value = R1 & mask; + value = value << (31-SAR); + R2dst = value; + nullifyCondResult = value; + build DepCondNullify; +} + +# DEPW,Z constant version (ZDEP) +:DEPW^",Z"^SEDCondSym R1,shiftC,shiftCLen,R2dst is opfam=0x35 & subop1012=2 & shiftC & R2 & R2dst & shiftCLen & R1 & DepCondNullify & SEDCondSym & cp { + mask:4 = 0xffffffff >> (32-shiftCLen); + local value = R1 & mask; + value = value << cp; + R2dst = value; + nullifyCondResult = value; + build DepCondNullify; +} + +# DEPWI,Z SAR version (ZVDEPI) +:DEPWI",Z"^SEDCondSym highlse5,SAR,shiftCLen,R2dst is opfam=0x35 & SAR & bits59=0 & subop1012=4 & shiftCLen & highlse5 & R2dst & DepCondNullify & SEDCondSym { + mask:4 = 0xffffffff >> (32-shiftCLen); + depbits:4 = sext(highlse5); + local value = depbits & mask; + value = value << (31-SAR); + R2dst = value; + nullifyCondResult = value; + build DepCondNullify; +} + +# DEPWI,Z constant version (ZDEPI) +:DEPWI",Z"^SEDCondSym highlse5,shiftC,shiftCLen,R2dst is opfam=0x35 & subop1012=6 & shiftC & highlse5 & R2dst & shiftCLen & DepCondNullify & SEDCondSym & cp { + mask:4 = 0xffffffff >> (32-shiftCLen); + depbits:4 = sext(highlse5); + local value = depbits & mask; + value = value << cp; + nullifyCondResult = value; + R2dst = value; + + build DepCondNullify; +} + + +# BCD instructions +:DCOR^UnitCondSym R2,RT is opfam=0x02 & op=0x2E & R2 & reg1=0x0 & RT & UnitCond & UnitCondSym { } # TODO +:IDCOR^UnitCondSym R2,RT is opfam=0x02 & op=0x2F & R2 & reg1=0x0 & RT & UnitCond & UnitCondSym { } # TODO + +################################################# +# System Instructions +################################################# +define pcodeop break; +:BREAK im5,im13 is opfam=0x0 & sysop=0x00 & im5 & im13 { break(); } + +:RFI is opfam=0x0 & sysop=0x60 & im5=0x0 { + iaoq_back = cr18; + iaoq_front = cr18; + iasq_back = cr17; + iasq_front = cr17; + upperBits:8 = zext(iasq_front); + lowerBits:8 = zext(iaoq_front); + local returnAddr = (upperBits << 32) | lowerBits; + goto [returnAddr]; + } + +:RFI^",R" is opfam=0x0 & sysop=0x65 & im5=0x0 { + r1 = shr0; + r8 = shr1; + r9 = shr2; + r16 = shr3; + r17 = shr4; + r24 = shr5; + r25 = shr6; + # psw = ipsw; + + iaoq_back = cr18; + iaoq_front = cr18; + iasq_back = cr17; + iasq_front = cr17; + upperBits:8 = zext(iasq_front); + lowerBits:8 = zext(iaoq_front); + returnAddr:8 = (upperBits << 32) | lowerBits; + goto [returnAddr]; +} + +:SSM highIm10,RT is opfam=0x0 & sysop=0x6B & c=0x0 & highIm10 & RT { + widePswG:4 = zext(pswG); + widePswF:4 = zext(pswG); + widePswR:4 = zext(pswG); + widePswP:4 = zext(pswG); + widePswD:4 = zext(pswG); + widePswI:4 = zext(pswG); + RT = (widePswG << 31) | (widePswF << 30) | (widePswR << 29) | (widePswP << 27) | (widePswD << 26) | (widePswI << 25); + pswG = pswG || (highIm10 & 0x40); + pswF = pswF || (highIm10 & 0x20); + pswR = pswR || (highIm10 & 0x10); + pswP = pswP || (highIm10 & 0x4); + pswD = pswD || (highIm10 & 0x2); + pswI = pswI || (highIm10 & 0x1); +} + +:RSM highIm10,RT is opfam=0x0 & sysop=0x73 & c=0x0 & highIm10 & RT { + widePswG:4 = zext(pswG); + widePswF:4 = zext(pswG); + widePswR:4 = zext(pswG); + widePswP:4 = zext(pswG); + widePswD:4 = zext(pswG); + widePswI:4 = zext(pswG); + RT = (widePswG << 31) | (widePswF << 30) | (widePswR << 29) | (widePswP << 27) | (widePswD << 26) | (widePswI << 25); + pswG = pswG && ((highIm10 & 0x40:1) == 0); + pswF = pswF && ((highIm10 & 0x20:1) == 0); + pswR = pswR && ((highIm10 & 0x10:1) == 0); + pswP = pswP && ((highIm10 & 0x4:1) == 0); + pswD = pswD && ((highIm10 & 0x2:1) == 0); + pswI = pswI && ((highIm10 & 0x1:1) == 0); + } + +:MTSM R1 is opfam=0x0 & sysop=0xC3 & c=0x0 & im5=0 & R1 { + pswG = ((R1 & 0x00000040:4) != 0); + pswF = (R1 & 0x00000020:4) != 0; + pswR = (R1 & 0x00000010:4) != 0; + pswQ = (R1 & 0x00000008:4) != 0; + pswP = (R1 & 0x00000004:4) != 0; + pswD = (R1 & 0x00000002:4) != 0; + pswI = (R1 & 0x00000001:4) != 0; +} + +:LDSID SRRB,RT is opfam=0x0 & sysop=0x85 & u=0 & RT & SRRB & SR & SRVAL { + RT = SRVAL; +} + +:MTSP R1,SR3bit is opfam=0x0 & sysop=0xC1 & im5=0 & R1 & SR3bit { + SR3bit = R1; + } + +:MTCTL R1,crname2 is opfam=0x0 & sysop=0xC2 & im5=0 & R1 & crname2 & cr { + cr = R1; + } + +:MTSAR R1 is opfam=0x0 & sysop=0xC2 & im5=0 & R1 & crname2 & cr=11 { + sar = (R1 & 0x1F); + } + +:MFSP SR3bit,RT is opfam=0x0 & sysop=0x25 & reg1=0x0 & RT & SR3bit { + RT = SR3bit; +} + +:MFCTL crname2,RT is opfam=0x0 & sysop=0x45 & RT & crname2 & reg1=0 & cr { + RT = cr; +} + +# this instruction is PA-RISC 2.0 only, but here to avoid disassembler comparison issues +:MFIA RT is opfam=0x0 & sysop=0xA5 & RT & reg1=0 { + RT = iaoq_front; +} + +define pcodeop sync; +:SYNC is opfam=0x0 & sysop=0x20 & im5=0 & c=0 & bit20=0 { sync(); } # sync cache +:SYNCDMA is opfam=0x0 & sysop=0x20 & im5=0 & c=0 & bit20=1 { sync(); } # sync DMA +define pcodeop probe; +:PROBER SRRB,R1,RT is opfam=0x1 & sysopshifted=0x46 & m=0 & SRRB & R1 & RT & SPCBASE { RT = probe(R1, SPCBASE); } # probe read +:PROBERI SRRB,highIm5,RT is opfam=0x1 & sysopshifted=0xC6 & m=0 & SRRB & highIm5 & RT & SPCBASE { RT = probe(highIm5:1, SPCBASE); } # probe read imm +:PROBEW SRRB,R1,RT is opfam=0x1 & sysopshifted=0x47 & m=0 & SRRB & R1 & RT & SPCBASE { RT = probe(R1, SPCBASE); } # probe write +:PROBEWI SRRB,highIm5,RT is opfam=0x1 & sysopshifted=0xC7 & m=0 & SRRB & highIm5 & RT & SPCBASE { RT = probe(highIm5:1, SPCBASE); } # probe write imm +define pcodeop physicalAddress; +:LPA^sysCmplt RX^SRRB,RT is opfam=0x1 & sysopshifted=0x4D & sysCmplt & RX & SRRB & RT & SPCBASE { RT = physicalAddress(SPCBASE); } # virt to phy addr translation +define pcodeop coherenceIndex; +:LCI RX^SRRB,RT is opfam=0x1 & sysopshifted=0x4C & m=0 & RX & SRRB & RT & SPCBASE { RT = coherenceIndex(SPCBASE); } # load coherence index +define pcodeop purgeTLB; +:PDTLB^sysCmplt RX^SRRB3bit is opfam=0x1 & sysopshifted=0x48 & RX & SRRB3bit & sysCmplt & m=0 & SPCBASE { purgeTLB(RX, SPCBASE); } +:PDTLB^sysCmplt RX^SRRB3bit is opfam=0x1 & sysopshifted=0x48 & RX & SRRB3bit & sysCmplt & m=1 & SPCBASE & RB { RB = RB + RX; purgeTLB(RX, SPCBASE); } + +:PITLB^sysCmplt RX^SRRB3bit is opfam=0x1 & sysopshifted=0x8 & RX & SRRB3bit & sysCmplt & m=0 & SPCBASE { purgeTLB(RX, SPCBASE); } +:PITLB^sysCmplt RX^SRRB3bit is opfam=0x1 & sysopshifted=0x8 & RX & SRRB3bit & sysCmplt & m=1 & SPCBASE & RB { RB = RB + RX; purgeTLB(RX, SPCBASE); } + +:PDTLBE^sysCmplt RX^SRRB3bit is opfam=0x1 & sysopshifted=0x49 & RX & SRRB3bit & sysCmplt & m=0 & SPCBASE { purgeTLB(RX, SPCBASE); } +:PDTLBE^sysCmplt RX^SRRB3bit is opfam=0x1 & sysopshifted=0x49 & RX & SRRB3bit & sysCmplt & m=1 & SPCBASE & RB { RB = RB + RX; purgeTLB(RX, SPCBASE); } + +:PITLBE^sysCmplt RX^SRRB3bit is opfam=0x1 & sysopshifted=0x9 & RX & SRRB3bit & sysCmplt & m=0 & SPCBASE { purgeTLB(RX, SPCBASE); } +:PITLBE^sysCmplt RX^SRRB3bit is opfam=0x1 & sysopshifted=0x9 & RX & SRRB3bit & sysCmplt & m=1 & SPCBASE & RB { RB = RB + RX; purgeTLB(RX, SPCBASE); } + +define pcodeop insertTLBEntry; +:IDTLBA R1,SRRB is opfam=0x1 & sysopshifted=0x41 & m=0 & SRRB & R1 & SPCBASE & im5=0 { insertTLBEntry(SPCBASE, R1); } +:IITLBA R1,(SR3bit,RB) is opfam=0x1 & sysopshiftedshort=0x01 & m=0 & SR3bit & RB & R1 & im5=0 { insertTLBEntry(SR3bit, RB, R1); } +:IDTLBP R1,SRRB is opfam=0x1 & sysopshifted=0x40 & m=0 & SRRB & R1 & SPCBASE & im5=0 { insertTLBEntry(SPCBASE, R1); } +:IITLBP R1,(SR3bit,RB) is opfam=0x1 & sysopshiftedshort=0x00 & m=0 & im5=0 & SR3bit & RB & R1 { insertTLBEntry(SR3bit, RB, R1); } +:IITLBT R1, R2 is opfam=0x1 & sysopshiftedshort=0x20 & m=0 & im5=0 & fpsub=0 & R2 & R1 { insertTLBEntry(R1, R2); } + +define pcodeop purgeCache; +:PDC^indexedWordAccessCmplt RX^SRRB is opfam=0x1 & sysopshifted=0x4E & indexedWordAccessCmplt & RX & SRRB & SPCBASE & im5=0 & m=0 { purgeCache(SPCBASE, RX); } +:PDC^indexedWordAccessCmplt RX^SRRB is opfam=0x1 & sysopshifted=0x4E & indexedWordAccessCmplt & RX & SRRB & SPCBASE & RB & im5=0 & m=1 { purgeCache(SPCBASE, RX); RB = RB + RX; } + +:FDC^indexedWordAccessCmplt RX^SRRB is opfam=0x1 & sysopshifted=0x4A & indexedWordAccessCmplt & RX & SRRB & SPCBASE & m=0 { purgeCache(SPCBASE, RX); } +:FDC^indexedWordAccessCmplt RX^SRRB is opfam=0x1 & sysopshifted=0x4A & indexedWordAccessCmplt & RX & SRRB & SPCBASE & RB & m=1 { purgeCache(SPCBASE, RX); RB = RB + RX; } + +:FIC^indexedWordAccessCmplt RX(SR3bit,RB) is opfam=0x1 & sysopshiftedshort=0x0A & indexedWordAccessCmplt & RX & SR3bit & RB & m=0 { purgeCache(SR3bit, RB, RX); } +:FIC^indexedWordAccessCmplt RX(SR3bit,RB) is opfam=0x1 & sysopshiftedshort=0x0A & indexedWordAccessCmplt & RX & SR3bit & RB & m=1 { purgeCache(SR3bit, RB, RX); RB = RB + RX;} + +:FDCE^indexedWordAccessCmplt RX^SRRB is opfam=0x1 & sysopshifted=0x4B & indexedWordAccessCmplt & RX & SRRB & SPCBASE & m=0 { purgeCache(SPCBASE, RX); } +:FDCE^indexedWordAccessCmplt RX^SRRB is opfam=0x1 & sysopshifted=0x4B & indexedWordAccessCmplt & RX & SRRB & SPCBASE & RB & m=1 { purgeCache(SPCBASE, RX); RB = RB + RX; } + +:FICE^indexedWordAccessCmplt RX(SR3bit,RB) is opfam=0x1 & sysopshiftedshort=0x0B & indexedWordAccessCmplt & RX & SR3bit & RB & m=0 { purgeCache(SR3bit, RB, RX); } +:FICE^indexedWordAccessCmplt RX(SR3bit,RB) is opfam=0x1 & sysopshiftedshort=0x0B & indexedWordAccessCmplt & RX & SR3bit & RB & m=1 { purgeCache(SR3bit, RB, RX); RB = RB + RX; } + +define pcodeop diag; +:DIAG im26 is opfam=0x05 & im26 { diag(im26:4); } + +################################################# +# Coprocessor and Special Function Instructions +################################################# +:SPOP0,SFU^nullifyForSpecial sop is opfam=0x04 & specop=0 & SFU & nullifyForSpecial & im5 & im15 [ sop=(im15 << 5) | im5; ] unimpl +:SPOP1,SFU^nullifyForSpecial sop is opfam=0x04 & specop=1 & SFU & nullifyForSpecial & im5 & sopim10 [ sop=(sopim10 << 5) | im5; ] unimpl +:SPOP2,SFU^nullifyForSpecial sop R2 is opfam=0x04 & specop=2 & SFU & nullifyForSpecial & R2 & im5 & sopim5 [ sop=(sopim5 << 5) | im5; ] unimpl +:SPOP3,SFU^nullifyForSpecial sop R1,R2 is opfam=0x04 & specop=3 & SFU & nullifyForSpecial & R1 & R2 & im5 & sopim5 [ sop=(sopim5 << 5) | im5; ] unimpl +:COPR,SFU,sop^nullifyForSpecial is opfam=0x0C & SFU & nullifyForSpecial & im5 & sopim17 [ sop=(sopim17 << 5) | im5; ] unimpl + +:CLDW,SFU^indexedWordAccessCmplt^loadCC RX^SRRB,RT is opfam=0x09 & bit9=0 & zero=0 & RX & SRRB & RT & SFU & indexedWordAccessCmplt & loadCC unimpl +:CLDD,SFU^indexedDoublewordAccessCmplt^loadCC RX^SRRB,RT is opfam=0x0B & bit9=0 & zero=0 & RX & SRRB & RT & SFU & indexedDoublewordAccessCmplt & loadCC unimpl +:CSTW,SFU^indexedWordAccessCmplt^storeCC RT,RX^SRRB is opfam=0x09 & bit9=1 & zero=0 & RX & SRRB & RT & SFU & indexedWordAccessCmplt & storeCC unimpl +:CSTD,SFU^indexedDoublewordAccessCmplt^storeCC RT,RX^SRRB is opfam=0x0B & bit9=1 & zero=0 & RX & SRRB & RT & SFU & indexedDoublewordAccessCmplt & storeCC unimpl + +:CLDW,SFU^shortDispCmplt^loadCC highlse5^SRRB,RT is opfam=0x09 & bit9=0 & one=1 & SRRB & RT & SFU & highlse5 & shortDispCmplt & loadCC unimpl +:CLDD,SFU^shortDispCmplt^loadCC highlse5^SRRB,RT is opfam=0x0B & bit9=0 & one=1 & SRRB & RT & SFU & highlse5 & shortDispCmplt & loadCC unimpl +:CSTW,SFU^shortDispCmplt^storeCC RT,highlse5^SRRB is opfam=0x09 & bit9=1 & one=1 & SRRB & RT & SFU & highlse5 & shortDispCmplt & storeCC unimpl +:CSTD,SFU^shortDispCmplt^storeCC RT,highlse5^SRRB is opfam=0x0B & bit9=1 & one=1 & SRRB & RT & SFU & highlse5 & shortDispCmplt & storeCC unimpl + + +################################################# +# Floating Point Instructions +################################################# +# These ld/st instructions are the same as the coprocessor instructions, with an SFU of zero or one + +# Floating Point Loads, 32 bit, indirect/indexed +:FLDW^indexedWordAccessCmplt^loadCC RX^SRRB,FPRT32 is opfam=0x09 & zero=0 & bit9=0 & bits78=0 & indexedWordAccessCmplt & loadCC & SRRB & RX & FPRT32 & SPCBASE & u=0 & m=0 { + addr:$(ADDRSIZE) = SPCBASE + sext(RX); + FPRT32 = zext(*:4 addr); +} + +:FLDW^indexedWordAccessCmplt^loadCC RX^SRRB,FPRT32 is opfam=0x09 & zero=0 & bit9=0 & bits78=0 & indexedWordAccessCmplt & loadCC & SRRB & RX & FPRT32 & SPCBASE & u=1 & m=0 { + addr:$(ADDRSIZE) = SPCBASE + (sext(RX) << 2); + FPRT32 = zext(*:4 addr); +} + +:FLDW^indexedWordAccessCmplt^loadCC RX^SRRB,FPRT32 is opfam=0x09 & zero=0 & bit9=0 & bits78=0 & indexedWordAccessCmplt & loadCC & SRRB & RX & RB & FPRT32 & SPCBASE & u=0 & m=1 { + addr:$(ADDRSIZE) = SPCBASE + sext(RX); + FPRT32 = zext(*:4 addr); + RB = RB + RX; +} + +:FLDW^indexedWordAccessCmplt^loadCC RX^SRRB,FPRT32 is opfam=0x09 & zero=0 & bit9=0 & bits78=0 & indexedWordAccessCmplt & loadCC & SRRB & RB & RX & FPRT32 & SPCBASE & u=1 & m=1 { + addr:$(ADDRSIZE) = SPCBASE + (sext(RX) << 2); + FPRT32 = zext(*:4 addr); + RB = RB + RX; +} + +# Floating Point Loads, 64 bit, indirect/indexed +:FLDD^indexedDoublewordAccessCmplt^loadCC RX^SRRB,FPRT64 is opfam=0x0B & zero=0 & bit9=0 & sfu=0 & indexedDoublewordAccessCmplt & loadCC & SRRB & RX & FPRT64 & SPCBASE & u=0 & m=0 { + addr:$(ADDRSIZE) = SPCBASE + sext(RX); + FPRT64 = zext(*:8 addr); +} + +:FLDD^indexedDoublewordAccessCmplt^loadCC RX^SRRB,FPRT64 is opfam=0x0B & zero=0 & bit9=0 & sfu=0 & indexedDoublewordAccessCmplt & loadCC & SRRB & RX & FPRT64 & SPCBASE & u=1 & m=0 { + addr:$(ADDRSIZE) = SPCBASE + (sext(RX) << 2); + FPRT64 = zext(*:8 addr); +} + +:FLDD^indexedDoublewordAccessCmplt^loadCC RX^SRRB,FPRT64 is opfam=0x0B & zero=0 & bit9=0 & sfu=0 & indexedDoublewordAccessCmplt & loadCC & SRRB & RX & RB & FPRT64 & SPCBASE & u=0 & m=1 { + addr:$(ADDRSIZE) = SPCBASE + sext(RX); + FPRT64 = zext(*:8 addr); + RB = RB + RX; +} + +:FLDD^indexedDoublewordAccessCmplt^loadCC RX^SRRB,FPRT64 is opfam=0x0B & zero=0 & bit9=0 & sfu=0 & indexedDoublewordAccessCmplt & loadCC & SRRB & RB & RX & FPRT64 & SPCBASE & u=1 & m=1 { + addr:$(ADDRSIZE) = SPCBASE + (sext(RX) << 3); + FPRT64 = zext(*:8 addr); + RB = RB + RX; +} + + +# Floating Point Stores -- 32 and 64 bits +:FSTW^indexedWordAccessCmplt^storeCC FPRT32,RX^SRRB is opfam=0x09 & zero=0 & bit9=1 & bits78=0 & indexedWordAccessCmplt & storeCC & SRRB & RX & FPRT32 & SPCBASE & u=0 & m=0 { + addr:$(ADDRSIZE) = SPCBASE + sext(RX); + *addr = FPRT32:4; +} + +:FSTW^indexedWordAccessCmplt^storeCC FPRT32,RX^SRRB is opfam=0x09 & zero=0 & bit9=1 & bits78=0 & indexedWordAccessCmplt & storeCC & SRRB & RX & FPRT32 & SPCBASE & u=1 & m=0 { + addr:$(ADDRSIZE) = SPCBASE + (sext(RX) << 2); + *addr = FPRT32:4; +} + +:FSTW^indexedWordAccessCmplt^storeCC FPRT32,RX^SRRB is opfam=0x09 & zero=0 & bit9=1 & bits78=0 & indexedWordAccessCmplt & storeCC & SRRB & RX & RB & FPRT32 & SPCBASE & u=0 & m=1 { + addr:$(ADDRSIZE) = SPCBASE + sext(RX); + *addr = FPRT32:4; + RB = RB + RX; +} + +:FSTW^indexedWordAccessCmplt^storeCC FPRT32,RX^SRRB is opfam=0x09 & zero=0 & bit9=1 & bits78=0 & indexedWordAccessCmplt & storeCC & SRRB & RX & RB & FPRT32 & SPCBASE & u=1 & m=1 { + addr:$(ADDRSIZE) = SPCBASE + (sext(RX) << 2); + *addr = FPRT32:4; + RB = RB + RX; +} + +:FSTD^indexedDoublewordAccessCmplt^storeCC FPRT64,RX^SRRB is opfam=0x0B & zero=0 & bit9=1 & bits78=0 & indexedDoublewordAccessCmplt & storeCC & SRRB & RX & FPRT64 & SPCBASE & u=0 & m=0 { + addr:$(ADDRSIZE) = SPCBASE + sext(RX); + *addr = FPRT64:8; +} + +:FSTD^indexedDoublewordAccessCmplt^storeCC FPRT64,RX^SRRB is opfam=0x0B & zero=0 & bit9=1 & bits78=0 & indexedDoublewordAccessCmplt & storeCC & SRRB & RX & FPRT64 & SPCBASE & u=1 & m=0 { + addr:$(ADDRSIZE) = SPCBASE + (sext(RX) << 3); + *addr = FPRT64:8; +} + +:FSTD^indexedDoublewordAccessCmplt^storeCC FPRT64,RX^SRRB is opfam=0x0B & zero=0 & bit9=1 & bits78=0 & indexedDoublewordAccessCmplt & storeCC & SRRB & RX & RB & FPRT64 & SPCBASE & u=0 & m=1 { + addr:$(ADDRSIZE) = SPCBASE + sext(RX); + *addr = FPRT64:8; + RB = RB + RX; +} + +:FSTD^indexedDoublewordAccessCmplt^storeCC FPRT64,RX^SRRB is opfam=0x0B & zero=0 & bit9=1 & bits78=0 & indexedDoublewordAccessCmplt & storeCC & SRRB & RX & RB & FPRT64 & SPCBASE & u=1 & m=1 { + addr:$(ADDRSIZE) = SPCBASE + (sext(RX) << 2); + *addr = FPRT64:8; + RB = RB + RX; +} + + +# Floating Point Load Word with Short Displacement, no modification to RB +:FLDW^shortDispCmplt^loadCC highlse5^SRRB,FPRT32 is opfam=0x09 & one=1 & bit9=0 & bits78=0 & shortDispCmplt & loadCC & SRRB & SPCBASE & FPRT32 & highlse5 & m=0 { + addr:$(ADDRSIZE) = SPCBASE + sext(highlse5); + FPRT32 = zext(*:4 addr); +} + +# Floating Point Load Word with Short Displacement, post-modification to RB +:FLDW^shortDispCmplt^loadCC highlse5^SRRB,FPRT32 is opfam=0x09 & one=1 & bit9=0 & bits78=0 & shortDispCmplt & loadCC & SRRB & SPCBASE & FPRT32 & RB & highlse5 & m=1 & u=0 { + addr:$(ADDRSIZE) = SPCBASE; + FPRT32 = zext(*:4 addr); + RB = RB + sext(highlse5); +} + +# Floating Point Load Word with Short Displacement, pre-modification to RB +:FLDW^shortDispCmplt^loadCC highlse5^SRRB,FPRT32 is opfam=0x09 & one=1 & bit9=0 & bits78=0 & shortDispCmplt & loadCC & SRRB & RB & SPCBASE & FPRT32 & highlse5 & m=1 & u=1 { + addr:$(ADDRSIZE) = SPCBASE + sext(highlse5); + FPRT32 = zext(*:4 addr); + RB = RB + sext(highlse5); +} + +:FLDD^shortDispCmplt^loadCC highlse5^SRRB,FPRT64 is opfam=0x0B & one=1 & bit6=0 & bits78=0 & bit9=0 & shortDispCmplt & loadCC & SRRB & SPCBASE & FPRT64 & highlse5 & m=0 { + addr:$(ADDRSIZE) = SPCBASE + sext(highlse5); + FPRT64 = zext(*:8 addr); +} + +:FLDD^shortDispCmplt^loadCC highlse5^SRRB,FPRT64 is opfam=0x0B & one=1 & bit6=0 & bits78=0 & bit9=0 & shortDispCmplt & loadCC & SRRB & RB & SPCBASE & FPRT64 & highlse5 & m=1 & u=0 { + addr:$(ADDRSIZE) = SPCBASE; + FPRT64 = zext(*:8 addr); + RB = RB + sext(highlse5); +} + +:FLDD^shortDispCmplt^loadCC highlse5^SRRB,FPRT64 is opfam=0x0B & one=1 & bit6=0 & bits78=0 & bit9=0 & shortDispCmplt & loadCC & SRRB & RB & SPCBASE & FPRT64 & highlse5 & m=1 & u=1 { + addr:$(ADDRSIZE) = SPCBASE + sext(highlse5); + FPRT64 = zext(*:8 addr); + RB = RB + sext(highlse5); +} + +:FSTW^shortDispCmplt^storeCC FPRT32,highlse5^SRRB is opfam=0x09 & one=1 & bits78=0 & bit9=1 & shortDispCmplt & storeCC & SRRB & SPCBASE & FPRT32 & highlse5 & m=0 { + addr:$(ADDRSIZE) = SPCBASE + sext(highlse5); + *addr = FPRT32:4; +} + +:FSTW^shortDispCmplt^storeCC FPRT32,highlse5^SRRB is opfam=0x09 & one=1 & bits78=0 & bit9=1 & shortDispCmplt & storeCC & SRRB & SPCBASE & RB & FPRT32 & highlse5 & m=1 & u=0 { + addr:$(ADDRSIZE) = SPCBASE; + *addr = FPRT32:4; + RB = RB + sext(highlse5); +} + +:FSTW^shortDispCmplt^storeCC FPRT32,highlse5^SRRB is opfam=0x09 & one=1 & bits78=0 & bit9=1 & shortDispCmplt & storeCC & SRRB & SPCBASE & RB & FPRT32 & highlse5 & m=1 & u=1 { + addr:$(ADDRSIZE) = SPCBASE + sext(highlse5); + *addr = FPRT32:4; + RB = RB + sext(highlse5); +} + +:FSTD^shortDispCmplt^storeCC FPRT64,highlse5^SRRB is opfam=0x0B & one=1 & bit6=0 & bits78=0 & bit9=1 & shortDispCmplt & storeCC & SRRB & SPCBASE & FPRT64 & highlse5 & m=0 { + addr:$(ADDRSIZE) = SPCBASE + sext(highlse5); + *addr = FPRT64:8; +} + +:FSTD^shortDispCmplt^storeCC FPRT64,highlse5^SRRB is opfam=0x0B & one=1 & bit6=0 & bits78=0 & bit9=1 & shortDispCmplt & storeCC & SRRB & RB & SPCBASE & FPRT64 & highlse5 & u=0 & m=1 { + addr:$(ADDRSIZE) = SPCBASE; + *addr = FPRT64:8; + RB = RB + sext(highlse5); +} + +:FSTD^shortDispCmplt^storeCC FPRT64,highlse5^SRRB is opfam=0x0B & one=1 & bit6=0 & bits78=0 & bit9=1 & shortDispCmplt & storeCC & SRRB & RB & SPCBASE & FPRT64 & highlse5 & u=1 & m=1 { + addr:$(ADDRSIZE) = SPCBASE + sext(highlse5); + *addr = FPRT64:8; + RB = RB + sext(highlse5); +} + +# Floating Point Format Conversion Instructions +:FCNV^fpsf^fpdf FPR232,FPRT32 is opfam=0x0E & fpclass=1 & fpc1sub=0 & fpc1sub2=0 & FPR232 & FPRT32 & fpsf & fpdf { + FPRT32 = float2float(FPR232); +} + +:FCNV^fpsf^fpdf FPR264,FPRT64 is opfam=0x0C & fpclass=1 & fpc1sub=0 & fpc1sub2=0 & sfu=0 & bit5=0 & FPR264 & FPRT64 & fpsf & fpsfraw=0 & fpdf & freg2sgl & fptsgl { +# if src format is sgl, this is sgl to dbl +# if src format is dbl, this is dbl to sgl +# sgl to sgl or dbl to dbl don't make sense +# and we don't support quad right now + FPRT64 = float2float(freg2sgl); +} + +:FCNV^fpsf^fpdf FPR264,FPRT64 is opfam=0x0C & fpclass=1 & fpc1sub=0 & fpc1sub2=0 & sfu=0 & bit5=0 & FPR264 & FPRT64 & fpsf & fpsfraw=1 & fpdf & freg2sgl & fptsgl { +# if src format is sgl, this is sgl to dbl +# if src format is dbl, this is dbl to sgl +# sgl to sgl or dbl to dbl don't make sense +# and we don't support quad right now + fptsgl = float2float(FPR264); +} + +:FCNVXF^fpsf^fpdf FPR232,FPRT32 is opfam=0x0E & fpclass=1 & fpc1sub=1 & fpc1sub2=0 & FPR232 & FPRT32 & fpsf & fpdf { + FPRT32 = int2float(FPR232); +} + +# int2float -- support single/double size ints and single/double floats +# so handle 4 different cases +:FCNVXF^fixedsf^fpdf FPR264,FPRT64 is opfam=0x0C & fpclass=1 & fpc1sub=1 & fpc1sub2=0 & FPR264 & FPRT64 & sfu=0 & fixedsf & fpdf & fptsgl & freg2sgl & fpsfraw=0 & fpdfraw=0 { + fptsgl = int2float(freg2sgl); +} + +:FCNVXF^fixedsf^fpdf FPR264,FPRT64 is opfam=0x0C & fpclass=1 & fpc1sub=1 & fpc1sub2=0 & FPR264 & FPRT64 & sfu=0 & fixedsf & fpdf & fptsgl & freg2sgl & fpsfraw=0 & fpdfraw=1 { + FPRT64 = int2float(freg2sgl); +} + +:FCNVXF^fixedsf^fpdf FPR264,FPRT64 is opfam=0x0C & fpclass=1 & fpc1sub=1 & fpc1sub2=0 & FPR264 & FPRT64 & sfu=0 & fixedsf & fpdf & fptsgl & freg2sgl & fpsfraw=1 & fpdfraw=0 { + fptsgl = int2float(FPR264); +} + +:FCNVXF^fixedsf^fpdf FPR264,FPRT64 is opfam=0x0C & fpclass=1 & fpc1sub=1 & fpc1sub2=0 & FPR264 & FPRT64 & sfu=0 & fixedsf & fpdf & fptsgl & freg2sgl & fpsfraw=1 & fpdfraw=1 { + FPRT64 = int2float(FPR264); +} + +:FCNVFX^fpsf^fixeddf FPR232,FPRT32 is opfam=0x0E & fpclass=1 & fpc1sub=2 & fpc1sub2=0 & FPR232 & FPRT32 & fpsf & fixeddf { + temp:4 = round(FPR232); + FPRT32 = trunc(temp); +} + +:FCNVFX^fpsf^fixeddf FPR264,FPRT64 is opfam=0x0C & fpclass=1 & fpc1sub=2 & fpc1sub2=0 & sfu=0 & FPR264 & FPRT64 & fpsf & fpsfraw=1 & fixeddf & fptsgl & freg2sgl { + local temp:8 = FPR264; + temp = round(temp); + FPRT64 = trunc(temp); +} + +:FCNVFX^fpsf^fixeddf FPR264,FPRT64 is opfam=0x0C & fpclass=1 & fpc1sub=2 & fpc1sub2=0 & sfu=0 & FPR264 & FPRT64 & fpsf & fpsfraw=0 & fixeddf & fptsgl & freg2sgl { + local temp:8 = float2float(freg2sgl); # convert single precision to double + temp = round(temp); + FPRT64 = trunc(temp); +} + +:FCNVFXT^fpsf^fixeddf FPR232,FPRT32 is opfam=0x0E & fpclass=1 & fpc1sub=3 & fpc1sub2=0 & FPR232 & FPRT32 & fpsf & fixeddf { + FPRT32 = trunc(FPR232); +} + +:FCNVFXT^fpsf^fixeddf FPR264,FPRT64 is opfam=0x0C & fpclass=1 & fpc1sub=3 & fpc1sub2=0 & sfu=0 & FPR264 & FPRT64 & fpsf & fpsfraw=1 & fixeddf & fpsfraw & fptsgl & freg2sgl { + local value:4 = float2float(FPR264); # convert double precision to single + fptsgl = trunc(value); +} + +:FCNVFXT^fpsf^fixeddf FPR264,FPRT64 is opfam=0x0C & fpclass=1 & fpc1sub=3 & fpc1sub2=0 & sfu=0 & FPR264 & FPRT64 & fpsf & fpsfraw=0 & fixeddf & fpsfraw & fptsgl & freg2sgl { + local value:4 = freg2sgl; # get single precision value from left half of 64 bit register + fptsgl = trunc(value); +} + + # Floating Point Functions +:FCPY^fpfmt FPR232,FPRT32 is opfam=0x0E & fpclass=0 & fpsub=2 & freg1=0 & FPR232 & FPRT32 & fpfmt { + FPRT32 = FPR232; +} + +:FCPY^fpfmt FPR264,FPRT64 is opfam=0x0C & fpclass=0 & fpsub=2 & freg1=0 & FPR264 & FPRT64 & fpfmt & fpsfraw=1 & fptsgl & freg2sgl { + fptsgl = freg2sgl; +} + +:FCPY^fpfmt FPR264,FPRT64 is opfam=0x0C & fpclass=0 & fpsub=2 & freg1=0 & FPR264 & FPRT64 & fpfmt & fpsfraw=0 & fptsgl & freg2sgl { + FPRT64 = FPR264; +} + +:FABS^fpfmt FPR232,FPRT32 is opfam=0x0E & fpclass=0 & fpsub=3 & freg1=0 & bit5=0 & bit8=0 & FPR232 & FPRT32 & fpfmt { + FPRT32 = abs(FPR232); +} + +:FABS^fpfmt FPR264,FPRT64 is opfam=0x0C & fpclass=0 & fpsub=3 & freg1=0 & bits59=0 & bit10=0 & FPR264 & FPRT64 & fpfmt { + FPRT64 = abs(FPR264); +} + +:FSQRT^fpfmt FPR232,FPRT32 is opfam=0x0E & fpclass=0 & fpsub=4 & freg1=0 & FPR232 & FPRT32 & fpfmt { + FPRT32 = sqrt(FPR232); +} +:FSQRT^fpfmt FPR264,FPRT64 is opfam=0x0C & fpclass=0 & fpsub=4 & freg1=0 & FPR264 & FPRT64 & fpfmt { + FPRT64 = sqrt(FPR264); +} + +:FRND^fpfmt FPR232,FPRT32 is opfam=0x0E & fpclass=0 & fpsub=5 & FPR232 & FPRT32 & fpfmt { + FPRT32 = round(FPR232); + } + +:FRND^fpfmt FPR264,FPRT64 is opfam=0x0C & fpclass=0 & fpsub=5 & FPR264 & FPRT64 & fpfmt { + FPRT64 = round(FPR264); +} + +:FADD^fpfmt FPR232,FPR132,FPRT32 is opfam=0x0E & fpclass=3 & fpsub=0 & FPR232 & FPR132 & FPRT32 & fpfmt { + FPRT32 = FPR132 f+ FPR232; +} + +:FADD^fpfmt FPR264,FPR164,FPRT64 is opfam=0x0C & fpclass=3 & fpsub=0 & FPR264 & FPRT64 & FPR164 & fpfmt & fpsfraw=0 & freg1sgl & freg2sgl & fptsgl { + fptsgl = freg1sgl f+ freg2sgl; +} + +:FADD^fpfmt FPR264,FPR164,FPRT64 is opfam=0x0C & fpclass=3 & fpsub=0 & FPR264 & FPRT64 & FPR164 & fpfmt & fpsfraw=1 & freg1sgl & freg2sgl & fptsgl { + FPRT64 = FPR164 f+ FPR264; +} + +:FSUB^fpfmt FPR232,FPR132,FPRT32 is opfam=0x0E & fpclass=3 & fpsub=1 & FPR232 & FPR132 & FPRT32 & fpfmt { + FPRT32 = FPR232 f- FPR132; +} + +:FSUB^fpfmt FPR264,FPR164,FPRT64 is opfam=0x0C & fpclass=3 & fpsub=1 & FPR264 & FPRT64 & FPR164 & fpfmt & fpsfraw=0 & fptsgl & freg1sgl & freg2sgl { + fptsgl = freg2sgl f- freg1sgl; +} + +:FSUB^fpfmt FPR264,FPR164,FPRT64 is opfam=0x0C & fpclass=3 & fpsub=1 & FPR264 & FPRT64 & FPR164 & fpfmt & fpsfraw=1 & fptsgl & freg1sgl & freg2sgl { + FPRT64 = FPR264 f- FPR164; +} + +:FMPY^fpfmt FPR232,FPR132,FPRT32 is opfam=0x0E & fpclass=3 & fpsub=2 & bit8=0 & FPR232 & FPR132 & FPRT32 & fpfmt { + FPRT32 = FPR132 f* FPR232; +} + +:FMPY^fpfmt FPR264,FPR164,FPRT64 is opfam=0x0C & fpclass=3 & fpsub=2 & bit8=0 & FPR264 & FPRT64 & FPR164 & fpfmt & fpsfraw=0 & fptsgl & freg1sgl & freg2sgl { + fptsgl = freg1sgl f* freg2sgl; +} + +:FMPY^fpfmt FPR264,FPR164,FPRT64 is opfam=0x0C & fpclass=3 & fpsub=2 & bit8=0 & FPR264 & FPRT64 & FPR164 & fpfmt & fpsfraw=1 & fptsgl & freg1sgl & freg2sgl { + FPRT64 = FPR164 f* FPR264; +} + +:FDIV^fpfmt FPR232,FPR132,FPRT32 is opfam=0x0E & fpclass=3 & fpsub=3 & FPR232 & FPR132 & FPRT32 & fpfmt { + FPRT32 = FPR232 f/ FPR132; +} + +:FDIV^fpfmt FPR264,FPR164,FPRT64 is opfam=0x0C & fpclass=3 & fpsub=3 & FPR264 & FPRT64 & FPR164 & fpfmt & fpsfraw=0 & fptsgl & freg1sgl & freg2sgl { + fptsgl = freg2sgl f/ freg1sgl; +} + +:FDIV^fpfmt FPR264,FPR164,FPRT64 is opfam=0x0C & fpclass=3 & fpsub=3 & FPR264 & FPRT64 & FPR164 & fpfmt & fpsfraw=1 & fptsgl & freg1sgl & freg2sgl { + FPRT64 = FPR264 f/ FPR164; +} + +# 64 bit version +:FMPYADD^fusedfmt FPR264,FPR164,FPRT64,fpra,fpta is opfam=0x06 & FPR264 & FPR164 & FPRT64 & fusedfmt & fpra & fpta & bit5=0 { + FPRT64 = FPR164 f* FPR264; + fpta = fpta f+ fpra; +} + +# 32 bit version -- this uses a special encoding of the 32 bit registers and can only use 16-31{LR}, not the lower registers +:FMPYADD^fusedfmt FUSEDR2,FUSEDR1,FUSEDRT,FUSEDRA,FUSEDTA is opfam=0x06 & FUSEDR2 & FUSEDR1 & FUSEDRT & fusedfmt & FUSEDRA & FUSEDTA & bit5=1 { + FUSEDRT = FUSEDR1 f* FUSEDR2; + FUSEDTA = FUSEDTA f+ FUSEDRA; + +} + +:FMPYSUB^fusedfmt FPR264,FPR164,FPRT64,fpra,fpta is opfam=0x26 & FPR264 & FPR164 & FPRT64 & fusedfmt & fpra & fpta & bit5=0 { + FPRT64 = FPR164 f* FPR264; + fpta = fpta f- fpra; +} + +:FMPYSUB^fusedfmt FUSEDR2,FUSEDR1,FUSEDRT,FUSEDRA,FUSEDTA is opfam=0x26 & FUSEDR2 & FUSEDR1 & FUSEDRT & fusedfmt & FUSEDRA & FUSEDTA & bit5=1 { + FUSEDRT = FUSEDR1 f* FUSEDR2; + FUSEDTA = FUSEDTA f- FUSEDRA; +} + +# Fixed Point / Integer Multiply +:XMPYU^fpfmt FPR232,FPR132,FPRT64 is opfam=0x0E & fpclass=3 & fpsub=2 & bit8=1 & FPR232 & FPR132 & FPRT64 & fpfmt & fptsgl { + arg1:8 = zext(FPR232); + arg2:8 = zext(FPR132); + prod:8 = arg1 * arg2; + FPRT64 = prod; + } + +# Floating Point Compare +# 32 bit register comparison +:FCMP^fpfmt1bit^fpcmp FPR232,FPR132 is opfam=0x0E & fpclass=2 & fpsub=0 & FPR232 & FPR132 & fpfmt1bit & bit11=0 & fpcmp { + local result:1 = 0:1; + # shift the previous compareBit onto the compareQueue + compareQueue = (compareQueue << 1); + compareQueue = compareQueue | compareBit; + result = fpcmp; + compareBit = result; +} + +:FCMP^fpfmt1bit^fpcmp64 FPR232,FPR132 is opfam=0x0E & fpclass=2 & fpsub=0 & FPR232 & FPR132 & fpfmt1bit & bit11=1 & fpcmp64 { + local result:1 = 0:1; + # shift the previous compareBit onto the compareQueue + compareQueue = (compareQueue << 1); + compareQueue = compareQueue | compareBit; + result = fpcmp64; + compareBit = result; +} + +# 64 bit register comparison +:FCMP^fpfmt^fpcmp FPR264,FPR164 is opfam=0x0C & fpclass=2 & fpsub=0 & FPR264 & FPR164 & fpfmt & fpsfraw=0 & fpcmp { + local result:1 = 0:1; + # shift the previous compareBit onto the compareQueue + compareQueue = (compareQueue << 1); + compareQueue = compareQueue | compareBit; + result = fpcmp; + compareBit = result; +} + +:FCMP^fpfmt^fpcmp64 FPR264,FPR164 is opfam=0x0C & fpclass=2 & fpsub=0 & FPR264 & FPR164 & fpfmt & fpsfraw=1 & fpcmp64 { + local result:1 = 0:1; + # shift the previous compareBit onto the compareQueue + compareQueue = (compareQueue << 1); + compareQueue = compareQueue | compareBit; + result = fpcmp64; + compareBit = result; +} + +:FTEST^fptest is opfam=0x0C & fpclass=2 & fpsub=1 & fptest & $(COMMON) + [ + nullifyEnable = 1; + globalset(inst_next, nullifyEnable); + ] +{ + nullifyNextCond = compareBit; +} + +# Misc Floating Point Functions +:COPR.0.0 is opfam=0x0C & im26=0x0 { } + +############################################################### +# Performance Montioring Unit Instructions +############################################################### +:PMENB is opfam=0x0C & bit5=0 & sfu=0x2 & pmuop=0x3 { } +:PMDIS is opfam=0x0C & bit5=0 & sfu=0x2 & pmuop=0x1 { } + +} # end with : phase=1 diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/PIC24.cspec b/python/icicle/Ghidra/Processors/PIC/data/languages/PIC24.cspec new file mode 100644 index 0000000..470be63 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/PIC24.cspec @@ -0,0 +1,112 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/PIC24.ldefs b/python/icicle/Ghidra/Processors/PIC/data/languages/PIC24.ldefs new file mode 100644 index 0000000..72c7a94 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/PIC24.ldefs @@ -0,0 +1,92 @@ + + + + + PIC-24E + + + + PIC-24F + + + + PIC-24H + + + + dsPIC30F + + + + + dsPIC33F + + + + + dsPIC33E + + + + + dsPIC33C + + + + diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/PIC24.opinion b/python/icicle/Ghidra/Processors/PIC/data/languages/PIC24.opinion new file mode 100644 index 0000000..e96a025 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/PIC24.opinion @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/PIC24.pspec b/python/icicle/Ghidra/Processors/PIC/data/languages/PIC24.pspec new file mode 100644 index 0000000..f132054 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/PIC24.pspec @@ -0,0 +1,28 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/PIC24.sinc b/python/icicle/Ghidra/Processors/PIC/data/languages/PIC24.sinc new file mode 100644 index 0000000..dc03122 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/PIC24.sinc @@ -0,0 +1,8029 @@ +#TODO: relative branches are not computed as addresses in [] + +# TODO: byte oriented inst_next/inst_start must be changed to word oriented when storing into reg/stack... + + +# NOTE: No support for stack pointer limit register (SPLIM) +# NOTE: Some registers are larger than PIC defines. +# NOTE: No support for signal emulation. +# NOTE: No support for mapping a 32Kbyte section of program memory space into upper 32 Kbytes of data address space. +# NOTE: No repeat loop status bit. +# NOTE: Split flags register, which could cause side effects. +# NOTE: pwrsav pcode is not defined. +# TODO: Support for fractional multiplier mode. +# TODO: Check ACCA and ACCB staturation modes. +# TODO: Check accumulator staturation and rounding modes. +# TODO: Test Stack Frame Active (SFA) status bit. + +# Basic ================================================================================ + +#define endian=little; # little endian only +define alignment=2; # 2 signifies how the PC moves per instruction + +define space ram type=ram_space size=2; # (2x8=)16-bit address space +define space register type=register_space size=2; # (2x8=)16-bit address space +define space rom type=ram_space size=3 wordsize=2 default ; # (3x8=)24-bit address space + # (2x8=)16-bit word per address + # 24-bit canonical instruction: + # address : code + # 0 : byte2 | byte1 + # 1 : pad | byte3 + # 2 : byte2 | byte1 + # 3 : pad | byte3 + # . + # . + # . + # etc + + +# Registers ============================================================================ + +define ram offset=0 size=2 [ + W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 +]; + +define ram offset=0 size=4 [ + W1W0 W3W2 W5W4 W7W6 W9W8 W11W10 W13W12 W15W14 +]; + +# define ram offset=28 size=3 [ FP ]; +# define ram offset=32 size=3 [ SP ]; + +# Note: This assumes little endian only +define ram offset=0 size=1 [ + W0byte _ W1byte _ W2byte _ W3byte _ + W4byte _ W5byte _ W6byte _ W7byte _ + W8byte _ W9byte _ W10byte _ W11byte _ + W12byte _ W13byte _ W14byte _ W15byte _ +]; + +define register offset=0 size=2 [ + SHADOW_W0 SHADOW_W1 SHADOW_W2 SHADOW_W3 +]; + +define ram offset=0x20 size=2 [ SPLIM ]; # Stack Pointer Limit + +# Note: ACCxU implemented here as a 16 bit, actual register is only 8 bits in PIC3x +# Note: This assumes little endian only +define ram offset=0x22 size=2 [ + ACCAL ACCAH ACCAU + ACCBL ACCBH ACCBU +]; + +# Note: Like above ACCx implemented here as a 48 bit, actual register is only 40 bits in PIC3x +define ram offset=0x22 size=6 [ + ACCA + ACCB +]; + +define ram offset=0x2E size=3 [ PC ]; + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +define ram offset=0x32 size=2 [ DSRPAG ]; # 9bit Data Space Read Page Address +define ram offset=0x34 size=2 [ DSWPAG ]; # 8bit Data Space Write Page Address +define ram offset=0x36 size=2 [ RCOUNT ]; # Repeat counter +# TODO: Re-implement with shadow stack +# define ram offset=0x38 size=2 [ DCOUNT ]; # 13 bits long DO Loop counter +define ram offset=0x54 size=1 [ TBLPAG ]; # 7bit Data Table Page Address +@else +define ram offset=0x32 size=1 [ TBLPAG ]; # 8bit Data Table Page Address +define ram offset=0x34 size=1 [ PSVPAG ]; # Program Memory Visibility Page Address Pointer +define ram offset=0x36 size=2 [ RCOUNT ]; # Repeat counter +define ram offset=0x38 size=2 [ DCOUNT ]; # 13 bits long DO Loop counter +define ram offset=0x3A size=3 [ DOSTART ]; +define ram offset=0x3C size=3 [ DOEND ]; +@endif + +define ram offset=0x44 size=2 [ CORCON ]; # Core Control Register +define ram offset=0x46 size=2 [ MODCON ]; +define ram offset=0x48 size=2 [ XMODSRT ]; +define ram offset=0x4A size=2 [ XMODEND ]; +define ram offset=0x4C size=2 [ YMODSRT ]; +define ram offset=0x4E size=2 [ YMODEND ]; +define ram offset=0x50 size=2 [ XBREV ]; +define ram offset=0x52 size=2 [ DISICNT ]; # Disable Interrupts Counter + +# Control registers +define register offset=1024 size=1 [ + SRL + SRH +]; + +# SR component register fields (pseudo) +define register offset=1536 size=1 [ + SRH_OA + SRH_OB + SRH_SA + SRH_SB + SRH_OAB + SRH_SAB + SRH_DA + SRH_DC + + SRL_IPL2 + SRL_IPL1 + SRL_IPL0 + SRL_RA + SRL_N + SRL_OV + SRL_Z + SRL_C + + DISI + + SHADOW_SRH_DC + + SHADOW_SRL_N + SHADOW_SRL_OV + SHADOW_SRL_Z + SHADOW_SRL_C +]; + + +# System register - Program Counter +# Note: actual PC is 23-bits wide, with a fixed 0 for the zeroeth bit +define register offset=2048 size=3 [ + # dsPIC33E uses array of registers to have 4 deep zero overhead do loops +@if defined(dsPIC33E) || defined(dsPIC33C) + DOSTART # 24 bits long bit23=bit0=0 DO Loop Start Address + DOSTART1 + DOSTART2 + DOSTART3 + DOEND # 24 bits long bit23=bit0=0 DO Loop End Address + DOEND1 + DOEND2 + DOEND3 +@endif + DOSTART_SHADOW + DOEND_SHADOW +]; + + +# System register - CPU Core Control Register # ????? connect this to meta-model? +define register offset=2560 size=2 [ + WDTcount # ????? formal name not documented, true size unknown + WDTprescalarA # ????? formal name not documented, true size unknown + WDTprescalarB # ????? formal name not documented, true size unknown +]; + + +# CORCON component register fields (pseudo) +define register offset=3072 size=1 [ + CORCON_VAR + CORCON_IPL3 + CORCON_PSV + CORCON_SFA +@if defined(dsPIC33E) || defined(dsPIC33C) + CORCON_DL # DO loop nesting level status bits (3 bit long) +@endif +]; + + +# NOTE: Technically this section only apply to dsPIC30F, dsPIC33F, dsPIC33E, and dsPIC33C but we will allow all profiles to see it. + +# This supports the zero overhead do loop specific registers +define register offset=4096 size=2 [ + +# dsPIC33E uses array of registers to have 4 deep zero overhead do loops +@if defined(dsPIC33E) || defined(dsPIC33C) + DCOUNT # 13 bits long DO Loop counter + DCOUNT1 + DCOUNT2 + DCOUNT3 +@else +# dsPIC30 and dsPIC33F use shadow register to have allow one level deep zero overhead do loop (doesn't hurt to have in other variants) + DCOUNT_SHADOW +@endif +]; + +# This supports the "skip next instruction" conditionals +define register offset=4608 size=1 [ + SkipNextFlag # pseudo run-time register to flag skipping over this instruction (making it a NOP) +]; + + +# contextreg is our instruction context +# here we are only using it for zero overhead do loops + +# NOTE: At first i used size=2 and it seem to be having problems? +define register offset=5120 size=4 [ contextreg ]; + +define context contextreg + blockEnd=(0,0) noflow # Flag to indicate end do zero overhead do loop + phase=(2,3) # Flag to indicate that we are in the middle of a instruction and not to change context + repeatInstr=(4,4) noflow # Flag to indicate end of repeat instruction loop + skipInstr=(5,5) noflow + # Flag to indicate that we are in the next instruction after a "skip next instruction" command +; + +# Tokens ============================================================================ + +define token instr(32) + padding=(24,31) # padding for 4th byte that is not decoded in actual processor + OP_31_0 =(0,31) + OP_31_4 =(4,31) + + OP_23_0 =(0,23) + OP_23_1 =(1,23) + OP_23_4 =(4,23) + OP_23_11=(11,23) + OP_23_12=(12,23) + OP_23_14=(14,23) + OP_23_15=(15,23) + OP_23_16=(16,23) + OP_23_18=(18,23) + OP_23_19=(19,23) + OP_23_20=(20,23) + + OP_21_20=(20,21) + + OP_19_16=(16,19) + OP_19_17=(17,19) + OP_19_18=(18,19) + + OP_15_8 =(8,15) + OP_15_12=(12,15) + OP_15_14=(14,15) + + OP_14_0 =(0,14) + OP_14_4 =(4,14) + OP_14_6 =(6,14) + OP_14_7 =(7,14) + OP_14_11=(11,14) + OP_14_12=(12,14) + + OP_13_4 =(4,13) + + OP_11_7 =(7,11) + OP_11_8 =(8,11) + OP_11_10=(10,11) + + OP_10_8 =(8,10) + OP_10_7 =(7,10) + OP_10_4 =(4,10) + + OP_9_4 =(4,9) + OP_9_8 =(8,9) + + OP_7_0 =(0,7) + OP_7_4 =(4,7) + OP_7_5 =(5,7) + OP_7_6 =(6,7) + + OP_6_0 =(0,6) + OP_6_4 =(4,6) + OP_6_5 =(5,6) + + OP_5_4 =(4,5) + + OP_3_0 =(0,3) + + OP_1_0 =(0,1) + + OP_19 =(19,19) + OP_15 =(15,15) + OP_14 =(14,14) + OP_13 =(13,13) + OP_12 =(12,12) + OP_11 =(11,11) + OP_7 =(7,7) + OP_6 =(6,6) + OP_5 =(5,5) + OP_3 =(3,3) + OP_0 =(0,0) + + TOK_n =(16,16) + TOK_A =(15,15) + TOK_B =(14,14) + TOK_Bb =(10,10) + TOK_CCCC =(16,19) + TOK_D =(13,13) + TOK_W =(6,6) + TOK_Z =(15,15) + TOK_Zb =(11,11) + + TOK_f12 =(1,12) + TOK_f13 =(0,12) + TOK_f15 =(1,15) + TOK_f15b =(4,18) + TOK_k3 =(0,2) + TOK_k4 =(0,3) + TOK_k5 =(0,4) + TOK_k6 =(0,5) signed + TOK_k8a =(0,4) + TOK_k4b =(4,7) + TOK_k8b =(7,9) + TOK_k8c =(4,11) + TOK_k10 =(4,13) + TOK_k14 =(0,13) + TOK_k15 =(0,14) + TOK_k16 =(4,19) + TOK_k16t =(0,15) + + TOK_r4 =(7,10) signed + TOK_bit4word =(0,0) + TOK_b3 =(13,15) + TOK_b1 =(0,0) + TOK_b4 =(12,15) + TOK_n6 =(4,9) signed + TOK_n7 =(0,6) + TOK_n15 =(1,15) + TOK_n16 =(0,15) signed + + TOK_0 =(0,0) + TOK_7 =(7,7) + TOK_13 =(13,13) + + TOK_3_0_Wreg =(0,3) # 16-bit full reg + TOK_3_0_Breg =(0,3) # 8-bit LSB of reg + TOK_3_1_Dreg =(1,3) # 32-bit reg pair, e.g., W1:W0 + TOK_3_1_Dregn =(1,3) # 32-bit reg pair name, e.g., W0 + + TOK_4_0_U =(0,4) + + TOK_6_4_U =(4,6) + + TOK_9_0_U =(0,9) + + TOK_10_7_Wreg =(7,10) # 16-bit full reg + TOK_10_7_Breg =(7,10) # 8-bit LSB of reg + TOK_10_7_Wregp =(7,10) # 16-bit full reg offset by one + TOK_10_8_Dreg =(8,10) # 32-bit reg pair, e.g., W1:W0 + TOK_10_8_Dregn =(8,10) # 32-bit reg pair name, e.g., W0 + + TOK_11_8_Wreg =(8,11) # 16-bit full reg + + TOK_13_11_U =(11,13) + + TOK_14_12_Dreg =(12,14) # 32-bit reg pair, e.g., W1:W0 + TOK_14_12_Dregn=(12,14) # 32-bit reg pair name, e.g., W0 + TOK_14_11_Wreg =(11,14) # 16-bit full reg + TOK_14_11_Wregn=(11,14) # 16-bit full reg offset by one + TOK_14_11_Breg =(11,14) # 8-bit LSB of reg + + TOK_18_15_Wreg =(15,18) # 16-bit full reg + TOK_18_15_Breg =(15,18) # 8-bit LSB of reg + TOK_18_15_S =(15,18) signed + + TOK_17_16_mm =(16,17) + TOK_18_16_mmm =(16,18) + TOK_13_12_xx =(12,13) + TOK_13_12_kk =(12,13) + TOK_11_10_yy =(10,11) + TOK_11_10_PP =(10,11) + TOK_9_6_iiii =(6,9) + TOK_5_2_jjjj =(2,5) + TOK_1_0_aa =(0,1) + ; + + + + +# Attach variables ===================================================== + +# attach normal registers +attach variables [ TOK_18_15_Wreg TOK_3_0_Wreg TOK_10_7_Wreg TOK_11_8_Wreg TOK_14_11_Wreg ] [ + + W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 +]; + +attach variables [ TOK_14_11_Wregn ] [ + _ W0 W1 W2 W3 W4 W5 W6 + W7 W8 W9 W10 W11 W12 W13 W14 +]; + +attach variables [ TOK_10_7_Wregp ] [ + W0 W1 W2 W3 W4 W5 W6 W7 + W8 W9 W10 W11 W12 W13 W14 W0 +]; + +# attach lower byte sub-registers +attach variables [ TOK_18_15_Breg TOK_3_0_Breg TOK_10_7_Breg TOK_14_11_Breg ] [ + + W0byte W1byte W2byte W3byte W4byte W5byte W6byte W7byte + W8byte W9byte W10byte W11byte W12byte W13byte W14byte W15byte +]; + +# attach double registers (ref by even reg only) +attach variables [ TOK_3_1_Dreg TOK_10_8_Dreg TOK_14_12_Dreg ] [ + + W1W0 W3W2 W5W4 W7W6 W9W8 W11W10 W13W12 W15W14 +]; +attach variables [ TOK_3_1_Dregn TOK_10_8_Dregn TOK_14_12_Dregn ] [ + + W0 W2 W4 W6 W8 W10 W12 W14 +]; + + +# Sub-constructors ==================================================================== + +@define WSconstraint "(OP_6=0 | OP_5=0)" +@define WDconstraint "(OP_13=0 | OP_12=0)" + +# Use must be constrained by $(WSconstraint) +Ws_t: TOK_3_0_Wreg is TOK_6_4_U=0x0 & TOK_3_0_Wreg + { export TOK_3_0_Wreg; } + +Ws_t: "["TOK_3_0_Wreg"]" is TOK_6_4_U=0x1 & TOK_3_0_Wreg + { export *[ram]:2 TOK_3_0_Wreg; } + +Ws_t: "["TOK_3_0_Wreg"--]" is TOK_6_4_U=0x2 & TOK_3_0_Wreg + { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg - 2; export *[ram]:2 tmp; } + +Ws_t: "["TOK_3_0_Wreg"++]" is TOK_6_4_U=0x3 & TOK_3_0_Wreg + { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg + 2; export *[ram]:2 tmp; } + +Ws_t: "[--"TOK_3_0_Wreg"]" is TOK_6_4_U=0x4 & TOK_3_0_Wreg + { TOK_3_0_Wreg = TOK_3_0_Wreg - 2; export *[ram]:2 TOK_3_0_Wreg; } + +Ws_t: "[++"TOK_3_0_Wreg"]" is TOK_6_4_U=0x5 & TOK_3_0_Wreg + { TOK_3_0_Wreg = TOK_3_0_Wreg + 2; export *[ram]:2 TOK_3_0_Wreg; } + + +# Use must be constrained by $(WSconstraint) +Wsd_t: TOK_3_0_Wreg is TOK_6_4_U=0x0 & TOK_3_0_Wreg & TOK_3_1_Dreg & OP_0=0 + { export TOK_3_1_Dreg; } + +Wsd_t: "["TOK_3_0_Wreg"]" is TOK_6_4_U=0x1 & TOK_3_0_Wreg + { export *[ram]:4 TOK_3_0_Wreg; } + +Wsd_t: "["TOK_3_0_Wreg"--]" is TOK_6_4_U=0x2 & TOK_3_0_Wreg + { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg - 4; export *[ram]:4 tmp; } + +Wsd_t: "["TOK_3_0_Wreg"++]" is TOK_6_4_U=0x3 & TOK_3_0_Wreg + { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg + 4; export *[ram]:4 tmp; } + +Wsd_t: "[--"TOK_3_0_Wreg"]" is TOK_6_4_U=0x4 & TOK_3_0_Wreg + { TOK_3_0_Wreg = TOK_3_0_Wreg - 4; export *[ram]:4 TOK_3_0_Wreg; } + +Wsd_t: "[++"TOK_3_0_Wreg"]" is TOK_6_4_U=0x5 & TOK_3_0_Wreg + { TOK_3_0_Wreg = TOK_3_0_Wreg + 4; export *[ram]:4 TOK_3_0_Wreg; } + + +# Use must be constrained by $(WSconstraint) +Wsnd_t: TOK_3_0_Wreg is TOK_13_11_U=0x0 & TOK_3_0_Wreg & TOK_3_1_Dreg & OP_0=0 + { export TOK_3_1_Dreg; } + +Wsnd_t: "["TOK_3_0_Wreg"]" is TOK_13_11_U=0x1 & TOK_3_0_Wreg + { export *[ram]:4 TOK_3_0_Wreg; } + +Wsnd_t: "["TOK_3_0_Wreg"--]" is TOK_13_11_U=0x2 & TOK_3_0_Wreg + { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg - 4; export *[ram]:4 tmp; } + +Wsnd_t: "["TOK_3_0_Wreg"++]" is TOK_13_11_U=0x3 & TOK_3_0_Wreg + { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg + 4; export *[ram]:4 tmp; } + +Wsnd_t: "[--"TOK_3_0_Wreg"]" is TOK_13_11_U=0x4 & TOK_3_0_Wreg + { TOK_3_0_Wreg = TOK_3_0_Wreg - 4; export *[ram]:4 TOK_3_0_Wreg; } + +Wsnd_t: "[++"TOK_3_0_Wreg"]" is TOK_13_11_U=0x5 & TOK_3_0_Wreg + { TOK_3_0_Wreg = TOK_3_0_Wreg + 4; export *[ram]:4 TOK_3_0_Wreg; } + + +# Use must be constrained by $(WSconstraint) +Wsb_t: TOK_3_0_Wreg is TOK_6_4_U=0x0 & TOK_3_0_Wreg + { export TOK_3_0_Wreg; } + +Wsb_t: "["TOK_3_0_Wreg"]" is TOK_6_4_U=0x1 & TOK_3_0_Wreg + { export *[ram]:2 TOK_3_0_Wreg; } + +Wsb_t: "["TOK_3_0_Wreg"--]" is TOK_6_4_U=0x2 & TOK_3_0_Wreg + { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg - 2; export *[ram]:2 tmp; } + +Wsb_t: "["TOK_3_0_Wreg"++]" is TOK_6_4_U=0x3 & TOK_3_0_Wreg + { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg + 2; export *[ram]:2 tmp; } + +Wsb_t: "[--"TOK_3_0_Wreg"]" is TOK_6_4_U=0x4 & TOK_3_0_Wreg + { TOK_3_0_Wreg = TOK_3_0_Wreg - 2; export *[ram]:2 TOK_3_0_Wreg; } + +Wsb_t: "[++"TOK_3_0_Wreg"]" is TOK_6_4_U=0x5 & TOK_3_0_Wreg + { TOK_3_0_Wreg = TOK_3_0_Wreg + 2; export *[ram]:2 TOK_3_0_Wreg; } + + +# Use must be constrained by $(WSconstraint) +Wsbyte_t: TOK_3_0_Wreg is TOK_6_4_U=0x0 & TOK_3_0_Wreg & TOK_3_0_Breg + { export TOK_3_0_Breg; } + +Wsbyte_t: "["TOK_3_0_Wreg"]" is TOK_6_4_U=0x1 & TOK_3_0_Wreg + { export *[ram]:1 TOK_3_0_Wreg; } + +Wsbyte_t: "["TOK_3_0_Wreg"--]" is TOK_6_4_U=0x2 & TOK_3_0_Wreg + { local tmp = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg - 1; export *[ram]:1 tmp; } + +Wsbyte_t: "["TOK_3_0_Wreg"++]" is TOK_6_4_U=0x3 & TOK_3_0_Wreg + { local tmp = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg + 1; export *[ram]:1 tmp; } + +Wsbyte_t: "[--"TOK_3_0_Wreg"]" is TOK_6_4_U=0x4 & TOK_3_0_Wreg + { TOK_3_0_Wreg = TOK_3_0_Wreg - 1; export *[ram]:1 TOK_3_0_Wreg; } + +Wsbyte_t: "[++"TOK_3_0_Wreg"]" is TOK_6_4_U=0x5 & TOK_3_0_Wreg + { TOK_3_0_Wreg = TOK_3_0_Wreg + 1; export *[ram]:1 TOK_3_0_Wreg; } + + +# Use must be constrained by $(WSconstraint) +Wsbbyte_t: TOK_3_0_Wreg is TOK_6_4_U=0x0 & TOK_3_0_Wreg & TOK_3_0_Breg + { export TOK_3_0_Breg; } + +Wsbbyte_t: "["TOK_3_0_Wreg"]" is TOK_6_4_U=0x1 & TOK_3_0_Wreg + { export *[ram]:1 TOK_3_0_Wreg; } + +Wsbbyte_t: "["TOK_3_0_Wreg"--]" is TOK_6_4_U=0x2 & TOK_3_0_Wreg + { local tmp = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg - 1; export *[ram]:1 tmp; } + +Wsbbyte_t: "["TOK_3_0_Wreg"++]" is TOK_6_4_U=0x3 & TOK_3_0_Wreg + { local tmp = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg + 1; export *[ram]:1 tmp; } + +Wsbbyte_t: "[--"TOK_3_0_Wreg"]" is TOK_6_4_U=0x4 & TOK_3_0_Wreg + { TOK_3_0_Wreg = TOK_3_0_Wreg - 1; export *[ram]:1 TOK_3_0_Wreg; } + +Wsbbyte_t: "[++"TOK_3_0_Wreg"]" is TOK_6_4_U=0x5 & TOK_3_0_Wreg + { TOK_3_0_Wreg = TOK_3_0_Wreg + 1; export *[ram]:1 TOK_3_0_Wreg; } + + +# Use must be constrained by $(WDconstraint) +Wd_t: TOK_10_7_Wreg is TOK_13_11_U=0x0 & TOK_10_7_Wreg + { export TOK_10_7_Wreg; } + +Wd_t: "["TOK_10_7_Wreg"]" is TOK_13_11_U=0x1 & TOK_10_7_Wreg + { export *[ram]:2 TOK_10_7_Wreg; } + +Wd_t: "["TOK_10_7_Wreg"--]" is TOK_13_11_U=0x2 & TOK_10_7_Wreg + { local tmp = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg - 2; export *[ram]:2 tmp; } + +Wd_t: "["TOK_10_7_Wreg"++]" is TOK_13_11_U=0x3 & TOK_10_7_Wreg + { local tmp = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg + 2; export *[ram]:2 tmp; } + +Wd_t: "[--"TOK_10_7_Wreg"]" is TOK_13_11_U=0x4 & TOK_10_7_Wreg + { TOK_10_7_Wreg = TOK_10_7_Wreg - 2; export *[ram]:2 TOK_10_7_Wreg; } + +Wd_t: "[++"TOK_10_7_Wreg"]" is TOK_13_11_U=0x5 & TOK_10_7_Wreg + { TOK_10_7_Wreg = TOK_10_7_Wreg + 2; export *[ram]:2 TOK_10_7_Wreg; } + + +# Use must be constrained by $(WDconstraint) +Wdd_t: TOK_10_7_Wreg is TOK_13_11_U=0x0 & TOK_10_7_Wreg & TOK_10_8_Dreg & OP_7=0 + { export TOK_10_8_Dreg; } + +Wdd_t: "["TOK_10_7_Wreg"]" is TOK_13_11_U=0x1 & TOK_10_7_Wreg + { export *[ram]:4 TOK_10_7_Wreg; } + +Wdd_t: "["TOK_10_7_Wreg"--]" is TOK_13_11_U=0x2 & TOK_10_7_Wreg + { local tmp = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg - 4; export *[ram]:4 tmp; } + +Wdd_t: "["TOK_10_7_Wreg"++]" is TOK_13_11_U=0x3 & TOK_10_7_Wreg + { local tmp = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg + 4; export *[ram]:4 tmp; } + +Wdd_t: "[--"TOK_10_7_Wreg"]" is TOK_13_11_U=0x4 & TOK_10_7_Wreg + { TOK_10_7_Wreg = TOK_10_7_Wreg - 4; export *[ram]:4 TOK_10_7_Wreg; } + +Wdd_t: "[++"TOK_10_7_Wreg"]" is TOK_13_11_U=0x5 & TOK_10_7_Wreg + { TOK_10_7_Wreg = TOK_10_7_Wreg + 4; export *[ram]:4 TOK_10_7_Wreg; } + + +# Use must be constrained by $(WDconstraint) +Wdbyte_t: TOK_10_7_Wreg is TOK_13_11_U=0x0 & TOK_10_7_Wreg & TOK_10_7_Breg + { export TOK_10_7_Breg; } + +Wdbyte_t: "["TOK_10_7_Wreg"]" is TOK_13_11_U=0x1 & TOK_10_7_Wreg + { export *[ram]:1 TOK_10_7_Wreg; } + +Wdbyte_t: "["TOK_10_7_Wreg"--]" is TOK_13_11_U=0x2 & TOK_10_7_Wreg + { local tmp = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg - 1; export *[ram]:1 tmp; } + +Wdbyte_t: "["TOK_10_7_Wreg"++]" is TOK_13_11_U=0x3 & TOK_10_7_Wreg + { local tmp = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg + 1; export *[ram]:1 tmp; } + +Wdbyte_t: "[--"TOK_10_7_Wreg"]" is TOK_13_11_U=0x4 & TOK_10_7_Wreg + { TOK_10_7_Wreg = TOK_10_7_Wreg - 1; export *[ram]:1 TOK_10_7_Wreg; } + +Wdbyte_t: "[++"TOK_10_7_Wreg"]" is TOK_13_11_U=0x5 & TOK_10_7_Wreg + { TOK_10_7_Wreg = TOK_10_7_Wreg + 1; export *[ram]:1 TOK_10_7_Wreg; } + + +# A lot like WdWRD_t +movWs: TOK_3_0_Wreg is TOK_6_4_U=0x0 & TOK_3_0_Wreg + { export TOK_3_0_Wreg; } + +movWs: "["TOK_3_0_Wreg"]" is TOK_6_4_U=0x1 & TOK_3_0_Wreg + { export *[ram]:2 TOK_3_0_Wreg; } + +movWs: "["TOK_3_0_Wreg"--]" is TOK_6_4_U=0x2 & TOK_3_0_Wreg + { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg - 2; export *[ram]:2 tmp; } + +movWs: "["TOK_3_0_Wreg"++]" is TOK_6_4_U=0x3 & TOK_3_0_Wreg + { local tmp = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg + 2; export *[ram]:2 tmp; } + +movWs: "[--"TOK_3_0_Wreg"]" is TOK_6_4_U=0x4 & TOK_3_0_Wreg + { TOK_3_0_Wreg = TOK_3_0_Wreg - 2; export *[ram]:2 TOK_3_0_Wreg; } + +movWs: "[++"TOK_3_0_Wreg"]" is TOK_6_4_U=0x5 & TOK_3_0_Wreg + { TOK_3_0_Wreg = TOK_3_0_Wreg + 2; export *[ram]:2 TOK_3_0_Wreg; } + +movWs: "["TOK_3_0_Wreg"+"TOK_18_15_Wreg"]" is TOK_6_4_U=0x6 & TOK_18_15_Wreg & TOK_3_0_Wreg + { local tmp = (TOK_3_0_Wreg + TOK_18_15_Wreg); export *[ram]:2 tmp; } + +movWs: "["TOK_3_0_Wreg"+"TOK_18_15_Wreg"]" is TOK_6_4_U=0x7 & TOK_18_15_Wreg & TOK_3_0_Wreg + { local tmp = (TOK_3_0_Wreg + TOK_18_15_Wreg); export *[ram]:2 tmp; } + + +movWsbyte: TOK_3_0_Wreg is TOK_6_4_U=0x0 & TOK_3_0_Wreg & TOK_3_0_Breg + { export TOK_3_0_Breg; } + +movWsbyte: "["TOK_3_0_Wreg"]" is TOK_6_4_U=0x1 & TOK_3_0_Wreg + { export *[ram]:1 TOK_3_0_Wreg; } + +movWsbyte: "["TOK_3_0_Wreg"--]" is TOK_6_4_U=0x2 & TOK_3_0_Wreg + { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg - 1; export *[ram]:1 tmp; } + +movWsbyte: "["TOK_3_0_Wreg"++]" is TOK_6_4_U=0x3 & TOK_3_0_Wreg + { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg + 1; export *[ram]:1 tmp; } + +movWsbyte: "[--"TOK_3_0_Wreg"]" is TOK_6_4_U=0x4 & TOK_3_0_Wreg + { TOK_3_0_Wreg = TOK_3_0_Wreg - 1; export *[ram]:1 TOK_3_0_Wreg; } + +movWsbyte: "[++"TOK_3_0_Wreg"]" is TOK_6_4_U=0x5 & TOK_3_0_Wreg + { TOK_3_0_Wreg = TOK_3_0_Wreg + 1; export *[ram]:1 TOK_3_0_Wreg; } + +movWsbyte: "["TOK_3_0_Wreg"+"TOK_18_15_Wreg"]" is TOK_6_4_U=0x6 & TOK_18_15_Wreg & TOK_3_0_Wreg + { tmp:2 = (TOK_3_0_Wreg + TOK_18_15_Wreg); export *[ram]:1 tmp; } + +movWsbyte: "["TOK_3_0_Wreg"+"TOK_18_15_Wreg"]" is TOK_6_4_U=0x7 & TOK_18_15_Wreg & TOK_3_0_Wreg + { tmp:2 = (TOK_3_0_Wreg + TOK_18_15_Wreg); export *[ram]:1 tmp; } + + + +movWd: TOK_10_7_Wreg is TOK_13_11_U=0x0 & TOK_10_7_Wreg + { export TOK_10_7_Wreg; } + +movWd: "["TOK_10_7_Wreg"]" is TOK_13_11_U=0x1 & TOK_10_7_Wreg + { export *[ram]:2 TOK_10_7_Wreg; } + +movWd: "["TOK_10_7_Wreg"--]" is TOK_13_11_U=0x2 & TOK_10_7_Wreg + { tmp:2 = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg - 2; export *[ram]:2 tmp; } + +movWd: "["TOK_10_7_Wreg"++]" is TOK_13_11_U=0x3 & TOK_10_7_Wreg + { tmp:2 = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg + 2; export *[ram]:2 tmp; } + +movWd: "[--"TOK_10_7_Wreg"]" is TOK_13_11_U=0x4 & TOK_10_7_Wreg + { TOK_10_7_Wreg = TOK_10_7_Wreg - 2; export *[ram]:2 TOK_10_7_Wreg; } + +movWd: "[++"TOK_10_7_Wreg"]" is TOK_13_11_U=0x5 & TOK_10_7_Wreg + { TOK_10_7_Wreg = TOK_10_7_Wreg + 2; export *[ram]:2 TOK_10_7_Wreg; } + +movWd: "["TOK_10_7_Wreg"+"TOK_18_15_Wreg"]" is TOK_13_11_U=0x6 & TOK_18_15_Wreg & TOK_10_7_Wreg + { tmp:2 = (TOK_10_7_Wreg + TOK_18_15_Wreg); export *[ram]:2 tmp; } + +movWd: "["TOK_10_7_Wreg"+"TOK_18_15_Wreg"]" is TOK_13_11_U=0x7 & TOK_18_15_Wreg & TOK_10_7_Wreg + { tmp:2 = (TOK_10_7_Wreg + TOK_18_15_Wreg); export *[ram]:2 tmp; } + + + +movWdbyte: TOK_10_7_Wreg is TOK_13_11_U=0x0 & TOK_10_7_Wreg & TOK_10_7_Breg + { export TOK_10_7_Breg; } + +movWdbyte: "["TOK_10_7_Wreg"]" is TOK_13_11_U=0x1 & TOK_10_7_Wreg + { export *[ram]:1 TOK_10_7_Wreg; } + +movWdbyte: "["TOK_10_7_Wreg"--]" is TOK_13_11_U=0x2 & TOK_10_7_Wreg + { tmp:2 = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg - 1; export *[ram]:1 tmp; } + +movWdbyte: "["TOK_10_7_Wreg"++]" is TOK_13_11_U=0x3 & TOK_10_7_Wreg + { tmp:2 = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg + 1; export *[ram]:1 tmp; } + +movWdbyte: "[--"TOK_10_7_Wreg"]" is TOK_13_11_U=0x4 & TOK_10_7_Wreg + { TOK_10_7_Wreg = TOK_10_7_Wreg - 1; export *[ram]:1 TOK_10_7_Wreg; } + +movWdbyte: "[++"TOK_10_7_Wreg"]" is TOK_13_11_U=0x5 & TOK_10_7_Wreg + { TOK_10_7_Wreg = TOK_10_7_Wreg + 1; export *[ram]:1 TOK_10_7_Wreg; } + +movWdbyte: "["TOK_10_7_Wreg"+"TOK_18_15_Wreg"]" is TOK_13_11_U=0x6 & TOK_18_15_Wreg & TOK_10_7_Wreg + { tmp:2 = (TOK_10_7_Wreg + TOK_18_15_Wreg); export *[ram]:1 tmp; } + +movWdbyte: "["TOK_10_7_Wreg"+"TOK_18_15_Wreg"]" is TOK_13_11_U=0x7 & TOK_18_15_Wreg & TOK_10_7_Wreg + { tmp:2 = (TOK_10_7_Wreg + TOK_18_15_Wreg); export *[ram]:1 tmp; } + + + + + +Wn_t: TOK_3_0_Wreg is TOK_3_0_Wreg + { export TOK_3_0_Wreg; } + +Wnbyte_t: TOK_3_0_Wreg is TOK_3_0_Wreg & TOK_3_0_Breg + { export TOK_3_0_Breg; } + +Wnd_t: TOK_10_7_Wreg is TOK_10_7_Wreg + { export TOK_10_7_Wreg; } + +Wndd_t: TOK_10_8_Dregn is TOK_10_8_Dreg & TOK_10_8_Dregn + { export TOK_10_8_Dreg; } + +Wnda_t: TOK_10_7_Wreg is TOK_10_7_Wreg + { export TOK_10_7_Wreg; } + +Wnbf_t: TOK_11_8_Wreg is TOK_11_8_Wreg + { export TOK_11_8_Wreg; } + +Wdpp_t: "["TOK_10_7_Wreg"++]" is TOK_10_7_Wreg + { local tmp = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg + 2; export *[ram]:2 tmp; } + +Wndabyte_t: TOK_10_7_Wreg is TOK_10_7_Wreg & TOK_10_7_Breg + { export TOK_10_7_Breg; } + +Wndb_t: TOK_3_0_Wreg is TOK_3_0_Wreg + { export TOK_3_0_Wreg; } + +Wndbyte_t: TOK_3_0_Wreg is TOK_3_0_Wreg & TOK_3_0_Breg + { export TOK_3_0_Breg; } + +Wns_t: TOK_3_0_Wreg is TOK_3_0_Wreg + { export TOK_3_0_Wreg; } + +Wnsbyte_t: TOK_3_0_Wreg is TOK_3_0_Wreg & TOK_3_0_Breg + { export TOK_3_0_Breg; } + +Wb_t: TOK_18_15_Wreg is TOK_18_15_Wreg + { export TOK_18_15_Wreg; } + +Wbbyte_t: TOK_18_15_Wreg is TOK_18_15_Wreg & TOK_18_15_Breg + { export TOK_18_15_Breg; } + +Wbb_t: TOK_14_11_Wreg is TOK_14_11_Wreg + { export TOK_14_11_Wreg; } + +Wbds_t: TOK_14_12_Dregn is TOK_14_12_Dreg & TOK_14_12_Dregn + { export TOK_14_12_Dreg; } + +Wbbbyte_t: TOK_14_11_Wreg is TOK_14_11_Wreg & TOK_14_11_Breg + { export TOK_14_11_Breg; } + +Wnb_t: TOK_3_0_Wreg is TOK_3_0_Wreg + { export TOK_3_0_Wreg; } + +Wnbbyte_t: TOK_3_0_Wreg is TOK_3_0_Wreg & TOK_3_0_Breg + { export TOK_3_0_Breg; } + +Wbd_t: TOK_14_11_Wreg is TOK_14_11_Wreg + { export TOK_14_11_Wreg; } + +WREG_t: ",wreg" is TOK_B=0 & TOK_D=0 + { export W0; } + +WREG_t: "" is TOK_B=0 & TOK_D=1 & TOK_f13 + { export *[ram]:2 TOK_f13; } + +WREGbyte_t: ",wreg" is TOK_B=1 & TOK_D=0 + { export W0byte; } + +WREGbyte_t: "" is TOK_B=1 & TOK_D=1 & TOK_f13 + { export *[ram]:1 TOK_f13; } + +WREGb_t: "wreg" is TOK_B=0 & TOK_D=0 + { export W0; } + +WREGbbyte_t: "wreg" is TOK_B=1 & TOK_D=0 + { export W0byte; } + +WREG_W0_t: "wreg" is TOK_B=0 + { export W0; } + +WREG_W0byte_t: "wreg" is TOK_B=1 + { export W0byte; } + +f13b_t: TOK_f13 is TOK_B=0 & TOK_D=1 & TOK_f13 + { export *[ram]:2 TOK_f13; } + +f13bbyte_t: TOK_f13 is TOK_B=1 & TOK_D=1 & TOK_f13 + { export *[ram]:1 TOK_f13; } + +f12_t: val is TOK_f12 [ val = TOK_f12 << 1; ] + { export *[ram]:2 val; } + +f13_t: TOK_f13 is TOK_B=0 & TOK_f13 + { export *[ram]:2 TOK_f13; } + +f13byte_t: TOK_f13 is TOK_B=1 & TOK_f13 + { export *[ram]:1 TOK_f13; } + +f15_t: addr is TOK_f15 + [ addr = ( TOK_f15 << 1 ); ] { export *[ram]:2 addr; } + +f15b_t: addr is TOK_f15b + [ addr = ( TOK_f15b << 1 ); ] { export *[ram]:2 addr; } + +k3_t: "#"TOK_k3 is TOK_k3 + { export *[const]:1 TOK_k3; } + +k4_t: "#"TOK_k4 is TOK_k4 + { export *[const]:1 TOK_k4; } + +k5: "#"TOK_k5 is TOK_k5 + { export *[const]:2 TOK_k5; } + +k5_t: "#"TOK_k5 is TOK_B=0 & TOK_k5 + { export *[const]:2 TOK_k5; } + +k5byte_t: "#"TOK_k5 is TOK_B=1 & TOK_k5 + { export *[const]:1 TOK_k5; } + +k5_B10_t: "#"TOK_k5 is TOK_Bb=0 & TOK_k5 + { export *[const]:2 TOK_k5; } + +k5byte_B10_t: "#"TOK_k5 is TOK_Bb=1 & TOK_k5 + { export *[const]:1 TOK_k5; } + + +k10_t: "#"TOK_k10 is TOK_B=0 & TOK_k10 + { export *[const]:2 TOK_k10; } + +k10byte_t: "#"TOK_k10 is TOK_B=1 & TOK_13_12_xx=0 & TOK_k10 + { export *[const]:1 TOK_k10; } + +k13_12_t: "#"TOK_13_12_kk is TOK_13_12_kk + { export *[const]:1 TOK_13_12_kk; } + +k14_t: "#"TOK_k14 is TOK_k14 + { export *[const]:2 TOK_k14; } + +k15_t: "#"TOK_k15 is TOK_k15 + { export *[const]:2 TOK_k15; } + +k16_t: "#"TOK_k16 is TOK_k16 + { export *[const]:2 TOK_k16; } + +bit4_t: "#"bit4 is TOK_b3 & TOK_b1 [ bit4 = (TOK_b1 << 3) | TOK_b3; ] + { export *[const]:1 bit4; } + +bit4byte_t: ".w" is TOK_bit4word=1 { } #display only + +bit4byte_t: ".b" is TOK_bit4word=0 { } #display only + +Bbit4_t: "#"TOK_b4 is TOK_b4 + { export *[const]:1 TOK_b4; } + +n15_t: TOK_n15 is TOK_n15 { export *:3 TOK_n15; } +n16_t: dest is TOK_n16 [ dest = inst_next + ( TOK_n16 << 1 ); ] { export *:3 dest; } +dest24_t: dest is TOK_n15 ; TOK_n7 [ dest = (( TOK_n7 << 16 ) $or ( TOK_n15 << 1 )); ] { export *:3 dest; } + +WordInstNext: winstNext is epsilon [ winstNext = inst_next + 0; ] { export *[const]:3 winstNext; } +WordInstNext4: winstNext is epsilon [ winstNext = inst_next + 0; ] { export *[const]:4 winstNext; } + +WnDest_t: TOK_3_0_Wreg is TOK_3_0_Wreg { dest:3 = zext(TOK_3_0_Wreg & 0xFFFE); export dest; } +WnRDest_t: TOK_3_0_Wreg is TOK_3_0_Wreg { dest:3 = 2 * zext(TOK_3_0_Wreg); export dest; } + + +# *2 +WsSlit10_t: "["TOK_3_0_Wreg"+"val"]" is TOK_18_15_S & TOK_13_11_U & TOK_6_4_U & TOK_3_0_Wreg + [ val = ((TOK_18_15_S << 6) $or (TOK_13_11_U << 3) $or TOK_6_4_U) << 1; ] + { tmp:2 = (TOK_3_0_Wreg + val); export *[ram]:2 tmp; } + +WsSlit10byte_t: "["TOK_3_0_Wreg"+"val"]" is TOK_18_15_S & TOK_13_11_U & TOK_6_4_U & TOK_3_0_Wreg + [ val = (TOK_18_15_S << 6) $or (TOK_13_11_U << 3) $or TOK_6_4_U; ] + { tmp:2 = (TOK_3_0_Wreg + val); export *[ram]:1 tmp; } + +# *2 +WdSlit10_t: "["TOK_10_7_Wreg"+"val"]" is TOK_18_15_S & TOK_13_11_U & TOK_10_7_Wreg & TOK_6_4_U + [ val = ((TOK_18_15_S << 6) $or (TOK_13_11_U << 3) $or TOK_6_4_U) << 1; ] + { tmp:2 = (TOK_10_7_Wreg + val); export *[ram]:2 tmp; } + +WdSlit10byte_t: "["TOK_10_7_Wreg"+"val"]" is TOK_18_15_S & TOK_13_11_U & TOK_10_7_Wreg & TOK_6_4_U + [ val = (TOK_18_15_S << 6) $or (TOK_13_11_U << 3) $or TOK_6_4_U; ] + { tmp:2 = (TOK_10_7_Wreg + val); export *[ram]:1 tmp; } + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +n6_t: dest is TOK_n6 [ dest = inst_next + ( 2 * TOK_n6 ); ] + { export *:3 dest; } + +k8_t: "#"k8 is TOK_k8b & TOK_k8a [ k8 = (TOK_k8b << 5) | TOK_k8a; ] + { export *[const]:2 k8; } + +k8byte_t: "#"k8 is TOK_k8b & TOK_k8a [ k8 = (TOK_k8b << 5) | TOK_k8a; ] + { export *[const]:1 k8; } + +WnWn1_t: TOK_3_0_Wreg is TOK_3_0_Wreg & TOK_14_11_Wreg + { dest:3 = ( ( zext( TOK_14_11_Wreg & 0x007F ) << 16 ) | zext( TOK_3_0_Wreg & 0xFFFE ) ); export *:3 dest; } +@endif + + + +@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C) +Wbsft_t: TOK_3_0_Wreg is TOK_3_0_Wreg + { export TOK_3_0_Wreg; } + +ACCA_t: ACCA is TOK_A=0 & ACCA + { export ACCA; } + +ACCB_t: ACCB is TOK_A=1 & ACCB + { export ACCB; } + + +r4_t: is TOK_r4 & OP_10_7=0 + { export *[const]:1 TOK_r4; } + +r4_t: ",#"TOK_r4 is TOK_r4 + { export *[const]:1 TOK_r4; } + +k6_t: "#"TOK_k6 is TOK_k6 + { export *[const]:1 TOK_k6; } + + + +WsWRO_t: TOK_3_0_Wreg is TOK_6_4_U=0x0 & TOK_3_0_Wreg + { export TOK_3_0_Wreg; } + +WsWRO_t: "["TOK_3_0_Wreg"]" is TOK_6_4_U=0x1 & TOK_3_0_Wreg + { export *[ram]:2 TOK_3_0_Wreg; } + +WsWRO_t: "["TOK_3_0_Wreg"--]" is TOK_6_4_U=0x2 & TOK_3_0_Wreg + { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg - 2; export *[ram]:2 tmp; } + +WsWRO_t: "["TOK_3_0_Wreg"++]" is TOK_6_4_U=0x3 & TOK_3_0_Wreg + { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg + 2; export *[ram]:2 tmp; } + +WsWRO_t: "[--"TOK_3_0_Wreg"]" is TOK_6_4_U=0x4 & TOK_3_0_Wreg + { TOK_3_0_Wreg = TOK_3_0_Wreg - 2; export *[ram]:2 TOK_3_0_Wreg; } + +WsWRO_t: "[++"TOK_3_0_Wreg"]" is TOK_6_4_U=0x5 & TOK_3_0_Wreg + { TOK_3_0_Wreg = TOK_3_0_Wreg + 2; export *[ram]:2 TOK_3_0_Wreg; } + +WsWRO_t: "["TOK_3_0_Wreg"+"TOK_18_15_Wreg"]" is TOK_6_4_U=0x6 & TOK_18_15_Wreg & TOK_3_0_Wreg + { tmp:2 = (TOK_3_0_Wreg + TOK_18_15_Wreg); export *[ram]:2 tmp; } + +WsWRO_t: "["TOK_3_0_Wreg"+"TOK_18_15_Wreg"]" is TOK_6_4_U=0x7 & TOK_18_15_Wreg & TOK_3_0_Wreg + { tmp:2 = (TOK_3_0_Wreg + TOK_18_15_Wreg); export *[ram]:2 tmp; } + + +WdWRO_t: TOK_3_0_Wreg is TOK_6_4_U=0x0 & TOK_3_0_Wreg + { export TOK_3_0_Wreg; } + +WdWRO_t: "["TOK_3_0_Wreg"]" is TOK_6_4_U=0x1 & TOK_3_0_Wreg + { export *[ram]:2 TOK_3_0_Wreg; } + +WdWRO_t: "["TOK_3_0_Wreg"--]" is TOK_6_4_U=0x2 & TOK_3_0_Wreg + { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg - 2; export *[ram]:2 tmp; } + +WdWRO_t: "["TOK_3_0_Wreg"++]" is TOK_6_4_U=0x3 & TOK_3_0_Wreg + { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg + 2; export *[ram]:2 tmp; } + +WdWRO_t: "[--"TOK_3_0_Wreg"]" is TOK_6_4_U=0x4 & TOK_3_0_Wreg + { TOK_3_0_Wreg = TOK_3_0_Wreg - 2; export *[ram]:2 TOK_3_0_Wreg; } + +WdWRO_t: "[++"TOK_3_0_Wreg"]" is TOK_6_4_U=0x5 & TOK_3_0_Wreg + { TOK_3_0_Wreg = TOK_3_0_Wreg + 2; export *[ram]:2 TOK_3_0_Wreg; } + +WdWRO_t: "["TOK_3_0_Wreg"+"TOK_18_15_Wreg"]" is TOK_6_4_U=0x6 & TOK_18_15_Wreg & TOK_3_0_Wreg + { tmp:2 = (TOK_3_0_Wreg + TOK_18_15_Wreg); export *[ram]:2 tmp; } + +WdWRO_t: "["TOK_3_0_Wreg"+"TOK_18_15_Wreg"]" is TOK_6_4_U=0x7 & TOK_18_15_Wreg & TOK_3_0_Wreg + { tmp:2 = (TOK_3_0_Wreg + TOK_18_15_Wreg); export *[ram]:2 tmp; } + + + + +Wx_t: ",["W8"]," is TOK_9_6_iiii=0x0 & W8 + { export *[ram]:2 W8; } + +Wx_t: ",["W8"]+=2," is TOK_9_6_iiii=0x1 & W8 + { tmp:2 = W8; W8 = W8 + 2; export *[ram]:2 tmp; } + +Wx_t: ",["W8"]+=4," is TOK_9_6_iiii=0x2 & W8 + { tmp:2 = W8; W8 = W8 + 4; export *[ram]:2 tmp; } + +Wx_t: ",["W8"]+=6," is TOK_9_6_iiii=0x3 & W8 + { tmp:2 = W8; W8 = W8 + 6; export *[ram]:2 tmp; } + +Wx_t: "" is TOK_9_6_iiii=0x4 # No Prefetch for X Data Space + { tmp:2 = 0; export tmp; } + +Wx_t: ",["W8"]-=6," is TOK_9_6_iiii=0x5 & W8 + { tmp:2 = W8; W8 = W8 - 6; export *[ram]:2 tmp; } + +Wx_t: ",["W8"]-=4," is TOK_9_6_iiii=0x6 & W8 + { tmp:2 = W8; W8 = W8 - 4; export *[ram]:2 tmp; } + +Wx_t: ",["W8"]-=2," is TOK_9_6_iiii=0x7 & W8 + { tmp:2 = W8; W8 = W8 - 2; export *[ram]:2 tmp; } + +Wx_t: ",["W9"]," is TOK_9_6_iiii=0x8 & W9 + { export *[ram]:2 W9; } + +Wx_t: ",["W9"]+=2," is TOK_9_6_iiii=0x9 & W9 + { tmp:2 = W9; W9 = W9 + 2; export *[ram]:2 tmp; } + +Wx_t: ",["W9"]+=4," is TOK_9_6_iiii=0xA & W9 + { tmp:2 = W9; W9 = W9 + 4; export *[ram]:2 tmp; } + +Wx_t: ",["W9"]+=6," is TOK_9_6_iiii=0xB & W9 + { tmp:2 = W9; W9 = W9 + 6; export *[ram]:2 tmp; } + +Wx_t: ",["W9"+"W12"]," is TOK_9_6_iiii=0xC & W9 & W12 + { tmp:2 = (W9 + W12); export *[ram]:2 tmp; } + +Wx_t: ",["W9"]-=6," is TOK_9_6_iiii=0xD & W9 + { tmp:2 = W9; W9 = W9 - 6; export *[ram]:2 tmp; } + +Wx_t: ",["W9"]-=4," is TOK_9_6_iiii=0xE & W9 + { tmp:2 = W9; W9 = W9 - 4; export *[ram]:2 tmp; } + +Wx_t: ",["W9"]-=2," is TOK_9_6_iiii=0xF & W9 + { tmp:2 = W9; W9 = W9 - 2; export *[ram]:2 tmp; } + + + +Wxd_t: ","W4 is TOK_13_12_xx=0x0 & W4 + { export W4; } + +Wxd_t: ","W5 is TOK_13_12_xx=0x1 & W5 + { export W5; } + +Wxd_t: ","W6 is TOK_13_12_xx=0x2 & W6 + { export W6; } + +Wxd_t: ","W7 is TOK_13_12_xx=0x3 & W7 + { export W7; } + + + +Wy_t: ",["W10"]," is TOK_5_2_jjjj=0x0 & W10 + { export *[ram]:2 W10; } + +Wy_t: ",["W10"]+=2," is TOK_5_2_jjjj=0x1 & W10 + { tmp:2 = W10; W10 = W10 + 2; export *[ram]:2 tmp; } + +Wy_t: ",["W10"]+=4," is TOK_5_2_jjjj=0x2 & W10 + { tmp:2 = W10; W10 = W10 + 4; export *[ram]:2 tmp; } + +Wy_t: ",["W10"]+=6," is TOK_5_2_jjjj=0x3 & W10 + { tmp:2 = W10; W10 = W10 + 6; export *[ram]:2 tmp; } + +Wy_t: "" is TOK_5_2_jjjj=0x4 # No Prefetch for Y Data Space + { tmp:2 = 0; export tmp; } + +Wy_t: ",["W10"]-=6," is TOK_5_2_jjjj=0x5 & W10 + { tmp:2 = W10; W10 = W10 - 6; export *[ram]:2 tmp; } + +Wy_t: ",["W10"]-=4," is TOK_5_2_jjjj=0x6 & W10 + { tmp:2 = W10; W10 = W10 - 4; export *[ram]:2 tmp; } + +Wy_t: ",["W10"]-=2," is TOK_5_2_jjjj=0x7 & W10 + { tmp:2 = W10; W10 = W10 - 2; export *[ram]:2 tmp; } + +Wy_t: ",["W11"]" is TOK_5_2_jjjj=0x8 & W11 + { export *[ram]:2 W11; } + +Wy_t: ",["W11"]+=2," is TOK_5_2_jjjj=0x9 & W11 + { tmp:2 = W11; W11 = W11 + 2; export *[ram]:2 tmp; } + +Wy_t: ",["W11"]+=4," is TOK_5_2_jjjj=0xA & W11 + { tmp:2 = W11; W11 = W11 + 4; export *[ram]:2 tmp; } + +Wy_t: ",["W11"]+=6," is TOK_5_2_jjjj=0xB & W11 + { tmp:2 = W11; W11 = W11 + 6; export *[ram]:2 tmp; } + +Wy_t: ",["W11"+"W12"]," is TOK_5_2_jjjj=0xC & W11 & W12 + { tmp:2 = (W11 + W12); export *[ram]:2 tmp; } + +Wy_t: ",["W11"]-=6," is TOK_5_2_jjjj=0xD & W11 + { tmp:2 = W11; W11 = W11 - 6; export *[ram]:2 tmp; } + +Wy_t: ",["W11"]-=4," is TOK_5_2_jjjj=0xE & W11 + { tmp:2 = W11; W11 = W11 - 4; export *[ram]:2 tmp; } + +Wy_t: ",["W11"]-=2," is TOK_5_2_jjjj=0xF & W11 + { tmp:2 = W11; W11 = W11 - 2; export *[ram]:2 tmp; } + + + +WmWm_t: W4"*W4" is TOK_17_16_mm=0x0 & W4 + { tmp:6 = (sext(W4) * sext(W4)); export tmp; } + +WmWm_t: W5"*W5" is TOK_17_16_mm=0x1 & W5 + { tmp:6 = (sext(W5) * sext(W5)); export tmp; } + +WmWm_t: W6"*W6" is TOK_17_16_mm=0x2 & W6 + { tmp:6 = (sext(W6) * sext(W6)); export tmp; } + +WmWm_t: W7"*W7" is TOK_17_16_mm=0x3 & W7 + { tmp:6 = (sext(W7) * sext(W7)); export tmp; } + + + +WmWn_t: W4"*"W5 is TOK_18_16_mmm=0x0 & W4 & W5 + { tmp:6 = (sext(W4) * sext(W5)); export tmp; } + +WmWn_t: W4"*"W6 is TOK_18_16_mmm=0x1 & W4 & W6 + { tmp:6 = (sext(W4) * sext(W6)); export tmp; } + +WmWn_t: W4"*"W7 is TOK_18_16_mmm=0x2 & W4 & W7 + { tmp:6 = (sext(W4) * sext(W7)); export tmp; } + +WmWn_t: "invalid" is TOK_18_16_mmm=0x3 + { tmp:6 = 0; export tmp; } + +WmWn_t: W5"*"W6 is TOK_18_16_mmm=0x4 & W5 & W6 + { tmp:6 = (sext(W5) * sext(W6)); export tmp; } + +WmWn_t: W5"*"W7 is TOK_18_16_mmm=0x5 & W5 & W7 + { tmp:6 = (sext(W5) * sext(W7)); export tmp; } + +WmWn_t: W6"*"W7 is TOK_18_16_mmm=0x6 & W6 & W7 + { tmp:6 = (sext(W6) * sext(W7)); export tmp; } + +WmWn_t: "invalid" is TOK_18_16_mmm=0x7 + { tmp:6 = 0; export tmp; } + + + +Wyd_t: ","W4 is TOK_11_10_yy=0x0 & W4 + { export W4; } + +Wyd_t: ","W5 is TOK_11_10_yy=0x1 & W5 + { export W5; } + +Wyd_t: ","W6 is TOK_11_10_yy=0x2 & W6 + { export W6; } + +Wyd_t: ","W7 is TOK_11_10_yy=0x3 & W7 + { export W7; } + + +AWB_t: ","W13 is TOK_1_0_aa=0x0 & W13 + { export W13; } + +AWB_t: ",["W13"]+=2" is TOK_1_0_aa=0x1 & W13 + { tmp:2 = W13; W13 = W13 + 2; export *[ram]:2 tmp; } + +AWB_t: "" is TOK_1_0_aa=0x2 # No write back + { tmp:2 = 0; export tmp; } + +AWB_t: ",invalid" is TOK_1_0_aa=0x3 # invalid + { tmp:2 = 0; export tmp; } +@endif + + +# Use must be constrained by $(WSconstraint) +WsMUL_t: TOK_3_0_Wreg is TOK_6_4_U=0x0 & TOK_3_0_Wreg + { export TOK_3_0_Wreg; } + +WsMUL_t: "["TOK_3_0_Wreg"]" is TOK_6_4_U=0x1 & TOK_3_0_Wreg + { export *[ram]:2 TOK_3_0_Wreg; } + +WsMUL_t: "["TOK_3_0_Wreg"--]" is TOK_6_4_U=0x2 & TOK_3_0_Wreg + { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg - 2; export *[ram]:2 tmp; } + +WsMUL_t: "["TOK_3_0_Wreg"++]" is TOK_6_4_U=0x3 & TOK_3_0_Wreg + { tmp:2 = TOK_3_0_Wreg; TOK_3_0_Wreg = TOK_3_0_Wreg + 2; export *[ram]:2 tmp; } + +WsMUL_t: "[--"TOK_3_0_Wreg"]" is TOK_6_4_U=0x4 & TOK_3_0_Wreg + { TOK_3_0_Wreg = TOK_3_0_Wreg - 2; export *[ram]:2 TOK_3_0_Wreg; } + +WsMUL_t: "[++"TOK_3_0_Wreg"]" is TOK_6_4_U=0x5 & TOK_3_0_Wreg + { TOK_3_0_Wreg = TOK_3_0_Wreg + 2; export *[ram]:2 TOK_3_0_Wreg; } + + + +# Use must be constrained by $(WDconstraint) +WdMUL_t: TOK_10_7_Wreg is TOK_13_11_U=0x0 & TOK_10_7_Wreg + { export TOK_10_7_Wreg; } + +WdMUL_t: "["TOK_10_7_Wreg"]" is TOK_13_11_U=0x1 & TOK_10_7_Wreg + { export *[ram]:2 TOK_10_7_Wreg; } + +WdMUL_t: "["TOK_10_7_Wreg"--]" is TOK_13_11_U=0x2 & TOK_10_7_Wreg + { tmp:2 = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg - 2; export *[ram]:2 tmp; } + +WdMUL_t: "["TOK_10_7_Wreg"++]" is TOK_13_11_U=0x3 & TOK_10_7_Wreg + { tmp:2 = TOK_10_7_Wreg; TOK_10_7_Wreg = TOK_10_7_Wreg + 2; export *[ram]:2 tmp; } + +WdMUL_t: "[--"TOK_10_7_Wreg"]" is TOK_13_11_U=0x4 & TOK_10_7_Wreg + { TOK_10_7_Wreg = TOK_10_7_Wreg - 2; export *[ram]:2 TOK_10_7_Wreg; } + +WdMUL_t: "[++"TOK_10_7_Wreg"]" is TOK_13_11_U=0x5 & TOK_10_7_Wreg + { TOK_10_7_Wreg = TOK_10_7_Wreg + 2; export *[ram]:2 TOK_10_7_Wreg; } + + +# Use must be constrained by $(WSconstraint) +WsROM_t: "["TOK_3_0_Wreg"]" is TOK_6_4_U=0x1 & TOK_3_0_Wreg + { addr:3 = (zext(TBLPAG)<<16) | zext(TOK_3_0_Wreg); export addr; } + +WsROM_t: "["TOK_3_0_Wreg"--]" is TOK_6_4_U=0x2 & TOK_3_0_Wreg + { tmp:2 = TOK_3_0_Wreg; addr:3 = (zext(TBLPAG)<<16) | zext(tmp); TOK_3_0_Wreg = tmp - 2; export addr; } + +WsROM_t: "["TOK_3_0_Wreg"++]" is TOK_6_4_U=0x3 & TOK_3_0_Wreg + { tmp:2 = TOK_3_0_Wreg; addr:3 = (zext(TBLPAG)<<16) | zext(tmp); TOK_3_0_Wreg = tmp + 2; export addr; } + +WsROM_t: "[--"TOK_3_0_Wreg"]" is TOK_6_4_U=0x4 & TOK_3_0_Wreg + { tmp:2 = TOK_3_0_Wreg - 2; addr:3 = (zext(TBLPAG)<<16) | zext(tmp); TOK_3_0_Wreg = tmp; export addr; } + +WsROM_t: "[++"TOK_3_0_Wreg"]" is TOK_6_4_U=0x5 & TOK_3_0_Wreg + { tmp:2 = TOK_3_0_Wreg + 2; addr:3 = (zext(TBLPAG)<<16) | zext(tmp); TOK_3_0_Wreg = tmp; export addr; } + + +# Use must be constrained by $(WDconstraint) +WdROM_t: "["TOK_10_7_Wreg"]" is TOK_13_11_U=0x1 & TOK_10_7_Wreg + { addr:3 = (zext(TBLPAG)<<16) | zext(TOK_10_7_Wreg); export addr; } + +WdROM_t: "["TOK_10_7_Wreg"--]" is TOK_13_11_U=0x2 & TOK_10_7_Wreg + { tmp:2 = TOK_10_7_Wreg; addr:3 = (zext(TBLPAG)<<16) | zext(tmp); TOK_10_7_Wreg = tmp - 2; export addr; } + +WdROM_t: "["TOK_10_7_Wreg"++]" is TOK_13_11_U=0x3 & TOK_10_7_Wreg + { tmp:2 = TOK_10_7_Wreg; addr:3 = (zext(TBLPAG)<<16) | zext(tmp); TOK_10_7_Wreg = tmp + 2; export addr; } + +WdROM_t: "[--"TOK_10_7_Wreg"]" is TOK_13_11_U=0x4 & TOK_10_7_Wreg + { tmp:2 = TOK_10_7_Wreg - 2; addr:3 = (zext(TBLPAG)<<16) | zext(tmp); TOK_10_7_Wreg = tmp; export addr; } + +WdROM_t: "[++"TOK_10_7_Wreg"]" is TOK_13_11_U=0x5 & TOK_10_7_Wreg + { tmp:2 = TOK_10_7_Wreg + 2; addr:3 = (zext(TBLPAG)<<16) | zext(tmp); TOK_10_7_Wreg = tmp; export addr; } + + +# Macros ========================================================================== + +## 16-bit working register math flag support + +# for decimal carry of a byte +macro testSRH_DCbyte(a) { + SRH_DC = ( 0x10 & a ) != 0; +} + +# for decimal carry of a word +macro testSRH_DCword(a) { + SRH_DC = ( 0x100 & a ) != 0; +} + +# for negative of a byte or word +macro testSRL_N(a) { + SRL_N = (a s< 0); +} + +# for (signed) addition of bytes or words: a + b +macro testSRL_OVadd(a,b) { + SRL_OV = scarry(a,b); +} + +# for (signed) addition of words with carry: a + b + c +macro testSRL_OVaddc(a,b,c) { + tmp:4 = sext(a) + sext(b) + zext(c); + SRL_OV = (tmp s< -0x00008000) || (tmp s> 0x00007FFF); +} + +# for (signed) addition of bytes with carry: a + b + c +macro testSRL_OVaddcByte(a,b,c) { + tmp:2 = sext(a) + sext(b) + zext(c); + SRL_OV = (tmp s< -0x0080) || (tmp s> 0x007F); +} + +# for (signed) subtraction of bytes or words: a - b +macro testSRL_OVsub(a,b) { + SRL_OV = sborrow(a,b); +} + +# for (signed) subtraction of words with carry: a - b - c +macro testSRL_OVsubc(a,b,c) { + tmp:4 = sext(a) - sext(b) - zext(c); + SRL_OV = (tmp s< -0x00008000) || (tmp s> 0x00007FFF); +} + +# for (signed) subtraction of bytes with carry: a - b - c +macro testSRL_OVsubcByte(a,b,c) { + tmp:2 = sext(a) - sext(b) - zext(c); + SRL_OV = (tmp s< -0x0080) || (tmp s> 0x007F); +} + +# for zero of a byte or word +macro testSRL_Z(a) { + SRL_Z = (a == 0); +} + +# for zero sticky of a byte or word +macro testSRL_Zsticky(a) { + SRL_Z = SRL_Z && (a == 0); +} + +macro addflags(a,b) { + SRL_C = carry(a,b); + SRL_OV = scarry(a,b); +} + +macro addflagsWithCarry(a,b,c) { + local ab = a + b; + SRL_C = carry(a,b) || carry(ab,c); + SRL_OV = scarry(a,b) || scarry(ab,c); +} + +macro subflags(a,b) { + SRL_C = a >= b; # inverted for borrow + SRL_OV = sborrow(a,b); +} + +macro subflagsWithCarry(a,b,c) { + local bc = b + c; + SRL_C = (a >= b) && (a >= bc); # inverted for borrow + SRL_OV = sborrow(a,b) || sborrow(a,bc); +} + + +## 40-bit ACCA and ACCB register math flag support + +# for addition (signed) +macro testSRH_OA() { + SRH_OA = ( ACCA & 0xFFFF00000000 ) != 0; + SRH_OAB = SRH_OA || SRH_OB; +} + +# for addition (signed) +macro testSRH_OB() { + SRH_OB = ( ACCB & 0xFFFF00000000 ) != 0; + SRH_OAB = SRH_OA || SRH_OB; +} + +# for addition (signed) +# Note: sticky bits +macro testSRH_SA() { + SRH_SA = SRH_SA | ( ( ACCA & 0x000100000000 ) != 0 ); + SRH_SAB = SRH_SAB | SRH_SA; +} + +# for addition (signed) +# Note: sticky bits +macro testSRH_SB() { + SRH_SB = SRH_SB | ( ( ACCB & 0x000100000000 ) != 0 ); + SRH_SAB = SRH_SAB | SRH_SB; +} + + +# 1000 0000 +@define SRH_OAbit "0x80" + +# 0100 0000 +@define SRH_OBbit "0x40" + +# 0010 0000 +@define SRH_SAbit "0x20" + +# 0001 0000 +@define SRH_SBbit "0x10" + +# 0000 1000 +@define SRH_OABbit "0x08" + +# 0000 0100 +@define SRH_SABbit "0x04" + +# 0000 0010 +@define SRH_DAbit "0x02" + +# 0000 0001 +@define SRH_DCbit "0x01" + + +# SR component register fields (pseudo) +macro unpackSRH( unpackByte ) { + SRH_OA = ( $(SRH_OAbit) & unpackByte ) != 0; + SRH_OB = ( $(SRH_OBbit) & unpackByte ) != 0; + SRH_SA = ( $(SRH_SAbit) & unpackByte ) != 0; + SRH_SB = ( $(SRH_SBbit) & unpackByte ) != 0; + SRH_OAB = ( $(SRH_OABbit) & unpackByte ) != 0; + SRH_SAB = ( $(SRH_SABbit) & unpackByte ) != 0; + SRH_DA = ( $(SRH_DAbit) & unpackByte ) != 0; + SRH_DC = ( $(SRH_DCbit) & unpackByte ) != 0; +} + + +macro packSRH( packByte ) { + packByte = (SRH_OA * $(SRH_OAbit)) | + (SRH_OB * $(SRH_OBbit)) | + (SRH_SA * $(SRH_SAbit)) | + (SRH_SB * $(SRH_SBbit)) | + (SRH_OAB * $(SRH_OABbit)) | + (SRH_SAB * $(SRH_SABbit)) | + (SRH_DA * $(SRH_DAbit)) | + (SRH_DC * $(SRH_DCbit)) ; +} + + +# 1000 0000 +@define SRL_IPL2bit "0x80" + +# 0100 0000 +@define SRL_IPL1bit "0x40" + +# 0010 0000 +@define SRL_IPL0bit "0x20" + +# 0001 0000 +@define SRL_RAbit "0x10" + +# 0000 1000 +@define SRL_Nbit "0x08" + +# 0000 0100 +@define SRL_OVbit "0x04" + +# 0000 0010 +@define SRL_Zbit "0x02" + +# 0000 0001 +@define SRL_Cbit "0x01" + + +macro unpackSRL( unpackByte ) { + SRL_IPL2 = ( $(SRL_IPL2bit) & unpackByte ) != 0; + SRL_IPL1 = ( $(SRL_IPL1bit) & unpackByte ) != 0; + SRL_IPL0 = ( $(SRL_IPL0bit) & unpackByte ) != 0; + SRL_RA = ( $(SRL_RAbit) & unpackByte ) != 0; + SRL_N = ( $(SRL_Nbit) & unpackByte ) != 0; + SRL_OV = ( $(SRL_OVbit) & unpackByte ) != 0; + SRL_Z = ( $(SRL_Zbit) & unpackByte ) != 0; + SRL_C = ( $(SRL_Cbit) & unpackByte ) != 0; +} + + +macro packSRL( packByte ) { + packByte = (SRL_IPL2 * $(SRL_IPL2bit)) | + (SRL_IPL1 * $(SRL_IPL1bit)) | + (SRL_IPL0 * $(SRL_IPL0bit)) | + (SRL_RA * $(SRL_RAbit)) | + (SRL_N * $(SRL_Nbit)) | + (SRL_OV * $(SRL_OVbit)) | + (SRL_Z * $(SRL_Zbit)) | + (SRL_C * $(SRL_Cbit)) ; +} + + +# Constructors ==================================================================== + + +@if defined(dsPIC30) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C) +# The "blockEnd" is the flag to indicate where the goto to cause the loop must be inserted. +# Previously an :do instruction figured out the address it needed an goto to be inserted and do something like +# do: .... [ blockEnd=1; globalset(addressForGoto,blockEnd); ] which will cause the context bit blockEnd to be +# set on the end of loop address. + +# PHASE-0 Handle end-of-loop + +getDOSTART: is epsilon { export *:3 DOSTART; } + +:^instruction is phase=0 & blockEnd=1 & instruction & getDOSTART [ phase = 1; ] { + +@if defined(dsPIC30F) || defined(dsPIC33F) + DCOUNT = DCOUNT - 1; + if (DCOUNT != 0) goto getDOSTART; + + DCOUNT = DCOUNT_SHADOW; + DOEND = DOEND_SHADOW; + DOSTART = DOSTART_SHADOW; +@endif +@if defined(dsPIC33E) || defined(dsPIC33C) + DL:2 = zext(CORCON_DL); + *[register]:2 (&:2 DCOUNT + DL*2) = (*[register]:2 (&:2 DCOUNT + DL*2)) - 1; + count:2 = *[register]:2 (&:2 DCOUNT + DL*2); + if (count != 0) goto getDOSTART; + + # stack 4 levels deep but we don't enforce this + CORCON_DL = CORCON_DL - 1; +@endif + +} +@endif + +:^instruction is phase=0 & instruction [ phase = 1; ] { + build instruction; +} + +# PHASE-1 Handle repeat / skip + +:^instruction is phase=1 & repeatInstr=1 & instruction [ phase = 2; ] { + + if (RCOUNT == 0) goto ; + RCOUNT = RCOUNT - 1; + build instruction; + goto inst_start; + +} + + + +# TODO: Why is context/^instruction used instead of simply having skip instructions branch around next instruction? + +# skipNext global support: +:^instruction is phase=1 & skipInstr=1 & instruction [ phase = 2; ] { + + if ( SkipNextFlag == 1 ) goto ; + build instruction; + +} + +:^instruction is phase=1 & instruction [ phase = 2; ] { + build instruction; +} + + + +with : phase = 2 { + +:add.w f13_t^WREG_t is OP_23_20=0xB & OP_19_16=0x4 & OP_15=0 & WREG_t & f13_t { + + local src = f13_t; + addflags( src, W0 ); + + local result = src + W0; + WREG_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); + testSRH_DCword( result ); +} + + +:add.b f13byte_t^WREGbyte_t is OP_23_20=0xB & OP_19_16=0x4 & OP_15=0 & WREGbyte_t & f13byte_t { + + local src = f13byte_t; + addflags( src, W0byte ); + + local result = src + W0byte; + WREGbyte_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); + testSRH_DCbyte( result ); +} + + +:add.w k10_t,Wn_t is OP_23_20=0xB & OP_19_16=0x0 & OP_15=0 & k10_t & Wn_t { + + local src = k10_t; + addflags( src, Wn_t ); + + local result = src + Wn_t; + Wn_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); + testSRH_DCword( result ); +} + + +:add.b k10byte_t,Wnbyte_t is OP_23_20=0xB & OP_19_16=0x0 & OP_15=0 & k10byte_t & Wnbyte_t { + + local src = k10byte_t; + addflags( src, Wnbyte_t ); + + local result = src + Wnbyte_t; + Wnbyte_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); + testSRH_DCbyte( result ); +} + + +:add.w Wb_t,k5_t,Wd_t is OP_23_20=0x4 & OP_19=0x0 & OP_6_5=0x3 & Wb_t & $(WDconstraint) & Wd_t & k5_t { + + addflags( k5_t, Wb_t ); + + local result = k5_t + Wb_t; + build Wd_t; + Wd_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); + testSRH_DCword( result ); +} + + +:add.b Wbbyte_t,k5byte_t,Wdbyte_t is + OP_23_20=0x4 & OP_19=0x0 & OP_6_5=0x3 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & k5byte_t { + + addflags( k5byte_t, Wbbyte_t ); + + local result = k5byte_t + Wbbyte_t; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); + testSRH_DCbyte( result ); +} + + +:add.w Wb_t,Ws_t,Wd_t is OP_23_20=0x4 & OP_19=0x0 & TOK_B=0 & Wb_t & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t { + + local src = Ws_t; + addflags( Wb_t, src ); + + local result = Wb_t + src; + build Wd_t; + Wd_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); + testSRH_DCword( result ); +} + +:add.b Wbbyte_t,Wsbyte_t,Wdbyte_t is OP_23_20=0x4 & OP_19=0x0 & TOK_B=1 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { + + local src = Wsbyte_t; + addflags( Wbbyte_t, src ); + + local result = Wbbyte_t + src; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); + testSRH_DCbyte( result ); +} + + +@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C) +:add ACCA_t is OP_23_20=0xC & OP_19_16=0xB & ACCA_t & OP_14_12=0x0 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 { + + ACCA = ACCA + ACCB; + testSRH_OA(); + testSRH_SA(); +} + +:add ACCB_t is OP_23_20=0xC & OP_19_16=0xB & ACCB_t & OP_14_12=0x0 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 { + + ACCB = ACCA + ACCB; + testSRH_OB(); + testSRH_SB(); +} +@endif + + +@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C) +:add WsWRO_t^r4_t,ACCA_t is OP_23_20=0xC & OP_19_16=0x9 & ACCA_t & r4_t & WsWRO_t { + + ACCA = (sext(WsWRO_t) << (16 - r4_t)) + ACCA; + testSRH_OA(); + testSRH_SA(); +} + +:add WsWRO_t^r4_t,ACCB_t is OP_23_20=0xC & OP_19_16=0x9 & ACCB_t & r4_t & WsWRO_t { + + ACCB = (sext(WsWRO_t) << (16 - r4_t)) + ACCB; + testSRH_OB(); + testSRH_SB(); +} +@endif + + +:addc.w f13_t^WREG_t is OP_23_20=0xB & OP_19_16=0x4 & OP_15=1 & WREG_t & f13_t { + + local c:2 = zext(SRL_C); + local src = f13_t; + addflagsWithCarry( src, W0, c ); + + local result = src + W0 + c; + WREG_t = result; + + testSRL_N ( result ); + testSRL_Zsticky( result ); + testSRH_DCword ( result ); +} + +:addc.b f13byte_t^WREGbyte_t is OP_23_20=0xB & OP_19_16=0x4 & OP_15=1 & WREGbyte_t & f13byte_t { + + local c = SRL_C; + local src = f13byte_t; + addflagsWithCarry( src, W0byte, c ); + + local result = src + W0byte + c; + WREGbyte_t = result; + + testSRL_N ( result ); + testSRL_Zsticky( result ); + testSRH_DCbyte ( result ); +} + + +:addc.w k10_t,Wn_t is OP_23_20=0xB & OP_19_16=0x0 & OP_15=1 & k10_t & Wn_t { + + local c:2 = zext(SRL_C); + addflagsWithCarry( k10_t, Wn_t, c ); + + Wn_t = k10_t + Wn_t + c; + + testSRL_N ( Wn_t ); + testSRL_Zsticky( Wn_t ); + testSRH_DCword ( Wn_t ); +} + + +:addc.b k10byte_t,Wnbyte_t is OP_23_20=0xB & OP_19_16=0x0 & OP_15=1 & k10byte_t & Wnbyte_t { + + local c = SRL_C; + addflagsWithCarry( k10byte_t, Wnbyte_t, c ); + + Wnbyte_t = k10byte_t + Wnbyte_t + c; + + testSRL_N ( Wnbyte_t ); + testSRL_Zsticky( Wnbyte_t ); + testSRH_DCbyte ( Wnbyte_t ); +} + + +:addc.w Wb_t,k5_t,Wd_t is OP_23_20=0x4 & OP_19=0x1 & OP_6_5=0x3 & Wb_t & $(WDconstraint) & Wd_t & k5_t { + + local c:2 = zext(SRL_C); + addflagsWithCarry( k5_t, Wb_t, c ); + + local result = k5_t + Wb_t + c; + build Wd_t; + Wd_t = result; + + testSRL_N ( result ); + testSRL_Zsticky( result ); + testSRH_DCword ( result ); +} + + +:addc.b Wbbyte_t,k5byte_t,Wdbyte_t is + OP_23_20=0x4 & OP_19=0x1 & OP_6_5=0x3 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & k5byte_t { + + local c = SRL_C; + addflagsWithCarry( k5byte_t, Wbbyte_t, c ); + + local result = k5byte_t + Wbbyte_t + c; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N ( result ); + testSRL_Zsticky( result ); + testSRH_DCbyte ( result ); +} + + +:addc.w Wb_t,Ws_t,Wd_t is OP_23_20=0x4 & OP_19=0x1 & TOK_B=0 & Wb_t & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t { + + local c:2 = zext(SRL_C); + local src = Ws_t; + addflagsWithCarry( Wb_t, src, c ); + + local result = Wb_t + src + c; + build Wd_t; + Wd_t = result; + + testSRL_N ( result ); + testSRL_Zsticky( result ); + testSRH_DCword ( result ); +} + + +:addc.b Wbbyte_t,Wsbyte_t,Wdbyte_t is OP_23_20=0x4 & OP_19=0x1 & TOK_B=1 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { + + local c = SRL_C; + local src = Wsbyte_t; + addflagsWithCarry( Wbbyte_t, src, c ); + + local result = Wbbyte_t + src + c; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N ( result ); + testSRL_Zsticky( result ); + testSRH_DCbyte ( result ); +} + + +:and.w f13_t^WREG_t is OP_23_20=0xB & OP_19_16=0x6 & OP_15=0 & WREG_t & f13_t { + + WREG_t = f13_t & W0; + + testSRL_N ( WREG_t ); + testSRL_Z ( WREG_t ); +} + + +:and.b f13byte_t^WREGbyte_t is OP_23_20=0xB & OP_19_16=0x6 & OP_15=0 & WREGbyte_t & f13byte_t { + + WREGbyte_t = f13byte_t & W0byte; + + testSRL_N ( WREGbyte_t ); + testSRL_Z ( WREGbyte_t ); +} + + +:and.w k10_t,Wn_t is OP_23_20=0xB & OP_19_16=0x2 & OP_15=0 & k10_t & Wn_t { + + Wn_t = k10_t & Wn_t; + + testSRL_N ( Wn_t ); + testSRL_Z ( Wn_t ); +} + + +:and.b k10byte_t,Wnbyte_t is OP_23_20=0xB & OP_19_16=0x2 & OP_15=0 & k10byte_t & Wnbyte_t { + + Wnbyte_t = k10byte_t & Wnbyte_t; + + testSRL_N ( Wnbyte_t ); + testSRL_Z ( Wnbyte_t ); +} + + +:and.w Wb_t,k5_t,Wd_t is OP_23_20=0x6 & OP_19=0x0 & OP_6_5=0x3 & Wb_t & $(WDconstraint) & Wd_t & k5_t { + + local result = k5_t & Wb_t; + Wd_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); +} + + +:and.b Wbbyte_t,k5byte_t,Wdbyte_t is + OP_23_20=0x6 & OP_19=0x0 & OP_6_5=0x3 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & k5byte_t { + + local result = k5byte_t & Wbbyte_t; + Wdbyte_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); +} + + +:and.w Wb_t,Ws_t,Wd_t is OP_23_20=0x6 & OP_19=0x0 & TOK_B=0 & Wb_t & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t { + + local result = Wb_t & Ws_t; + build Wd_t; + Wd_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); +} + + +:and.b Wbbyte_t,Wsbyte_t,Wdbyte_t is OP_23_20=0x6 & OP_19=0x0 & TOK_B=1 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { + + local result = Wbbyte_t & Wsbyte_t; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); +} + + +:asr.w f13_t^WREG_t is OP_23_20=0xD & OP_19_16=0x5 & OP_15=1 & WREG_t & f13_t { + + local src = f13_t; + SRL_C = ( src & 1 ) != 0; + WREG_t = src s>> 1; + + testSRL_N ( WREG_t ); + testSRL_Z ( WREG_t ); +} + + +:asr.b f13byte_t^WREGbyte_t is OP_23_20=0xD & OP_19_16=0x5 & OP_15=1 & WREGbyte_t & f13byte_t { + + local src = f13byte_t; + SRL_C = ( src & 1 ) != 0; + WREGbyte_t = src s>> 1; + + testSRL_N ( WREGbyte_t ); + testSRL_Z ( WREGbyte_t ); +} + + +:asr.w Ws_t,Wd_t is OP_23_20=0xD & OP_19_16=0x1 & OP_15=0x1 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t { + + local src = Ws_t; + + SRL_C = ( src & 1 ) != 0; + local result = src s>> 1; + build Wd_t; + Wd_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); +} + + +:asr.b Wsbyte_t,Wdbyte_t is OP_23_20=0xD & OP_19_16=0x1 & OP_15=0x1 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { + + local src = Wsbyte_t; + + SRL_C = ( src & 1 ) != 0; + local result = src s>> 1; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); +} + + +:asr.w Wbd_t,k4_t,Wnd_t is OP_23_20=0xD & OP_19_16=0xE & OP_15=0x1 & OP_6_4=0x4 & Wbd_t & Wnd_t & k4_t { + + Wnd_t = Wbd_t s>> k4_t; + + testSRL_N ( Wnd_t ); + testSRL_Z ( Wnd_t ); +} + + +:asr.w Wbd_t,Wns_t,Wnd_t is OP_23_20=0xD & OP_19_16=0xE & OP_15=0x1 & OP_6_4=0x0 & Wbd_t & Wnd_t & Wns_t { + + Wnd_t = Wbd_t s>> ( Wns_t & 0x001F ); + + testSRL_N ( Wnd_t ); + testSRL_Z ( Wnd_t ); +} + + +# The pdf manual is very confusing for this instruction. The final conclusion is that the .B +# is really a pseudo instruction and that everything is actually encoded as a word with the +# 'f' bits being left shifted by 1 +:bclr.w f12_t,bit4_t is OP_23_20=0xA & OP_19_16=0x9 & bit4_t & f12_t { + + local mask:2 = ~(1 << bit4_t); + f12_t = f12_t & mask; +} + + +# DSRPAG ????? +:bclr.w Wsb_t,Bbit4_t is + OP_23_20=0xA & OP_19_16=0x1 & Bbit4_t & OP_11=0x0 & TOK_Bb=0 & OP_9_8=0x0 & OP_7=0x0 & $(WSconstraint) & Wsb_t { + + local mask:2 = ~(1 << Bbit4_t); + Wsb_t = Wsb_t & mask; +} + + +:bclr.b Wsbbyte_t,Bbit4_t is + OP_23_20=0xA & OP_19_16=0x1 & Bbit4_t & OP_11=0x0 & TOK_Bb=1 & OP_9_8=0x0 & OP_7=0x0 & $(WSconstraint) & Wsbbyte_t { + + local mask:1 = ~(1 << Bbit4_t); + Wsbbyte_t = Wsbbyte_t & mask; +} + + +@if defined(dsPIC33C) +:bfext TOK_k4 "#"wid5, Wsb_t, Wnbf_t is + OP_23_16=0x0A & OP_15_12=0x8 & Wnbf_t & TOK_k4b & TOK_k4; + OP_23_16=0x0 & OP_15_8=0x0 & OP_7=0x0 & Wsb_t +[wid5 = TOK_k4b - TOK_k4 + 1;] +{ + local mask:2 = (0xff >> (16-(wid5 + 1))) << TOK_k4; + local result:2 = (Wsb_t & mask) >> TOK_k4; + Wnbf_t = result; +} + +:bfext TOK_k4 "#"wid5, n15_t, Wnbf_t is + OP_23_16=0x0A & OP_15_12=0xA & Wnbf_t & TOK_k4b & TOK_k4; + OP_23_16=0x0 & OP_0=0x0 & n15_t +[wid5 = TOK_k4b - TOK_k4 + 1;] +{ + local mask:2 = (0xff >> (16-(wid5 + 1))) << TOK_k4; + local word = *:2 n15_t; + local result:2 = (word & mask) >> TOK_k4; + Wnbf_t = result; +} + +:bfins TOK_k4 "#"wid5, Wnbf_t, Wsb_t is + OP_23_16=0x0A & OP_15_12=0x0 & Wnbf_t & TOK_k4b & TOK_k4; + OP_23_16=0x0 & OP_15_8=0x0 & OP_7=0x0 & Wsb_t +[wid5 = TOK_k4b - TOK_k4 + 1;] +{ + local mask:2 = (0xff >> (16-(wid5 + 1))) << TOK_k4; + local result:2 = (Wnbf_t & mask) >> TOK_k4; + Wsb_t = result; +} + +:bfins TOK_k4 "#"wid5, Wnbf_t, n15_t is + OP_23_16=0x0A & OP_15_12=0x2 & Wnbf_t & TOK_k4b & TOK_k4; + OP_23_16=0x0 & OP_0=0x0 & n15_t +[wid5 = TOK_k4b - TOK_k4 + 1;] +{ + local mask:2 = (0xff >> (16-(wid5 + 1))) << TOK_k4; + local result:2 = (Wnbf_t & mask) >> TOK_k4; + *:2 n15_t = result; +} + + +@endif + + +@if defined(dsPIC24F) || defined(dsPIC33E) || defined(dsPIC33C) +define pcodeop bootswap; +:bootswp is OP_23_0=0xFE2000 { + bootswap(); +} +@endif + + +:bra n16_t is OP_23_20=0x3 & OP_19_16=0x7 & n16_t { + + goto n16_t; +} + + +@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) +:bra Wns_t is OP_23_20=0x0 & OP_19_16=0x1 & OP_15_12=0x6 & OP_11_8=0x0 & OP_7_4=0x0 & Wns_t & WordInstNext { + + #Note: identical operation as below, unique targets + dest:3 = WordInstNext + 2 * sext(Wns_t); + goto [dest]; +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:bra Wns_t is OP_23_20=0x0 & OP_19_16=0x1 & OP_15_12=0x0 & OP_11_8=0x6 & OP_7_4=0x0 & Wns_t { + + #Note: identical operation as above, unique targets + # inst_next is byte oriented here, and word oriented inside of [ ]; + dest:3 = (inst_next/2) + 2 * sext(Wns_t); + goto [dest]; +} +@endif + + +cond1: "c" is TOK_CCCC=0x1 { tmpBool:1 = SRL_C; export tmpBool; } +cond1: "ge" is TOK_CCCC=0xD { tmpBool:1 = ((SRL_N && SRL_OV) || (!SRL_N && !SRL_OV)); export tmpBool; } +#Note: same as branch C, not supported in disassembly +# cond1: "geu" is TOK_CCCC=0x1 { tmpBool:1 = SRL_C ); export tmpBool; } +cond1: "gt" is TOK_CCCC=0xC + { tmpBool:1 = ((!SRL_Z && SRL_N && SRL_OV) || (!SRL_Z && !SRL_N && !SRL_OV)); export tmpBool; } +cond1: "gtu" is TOK_CCCC=0xE { tmpBool:1 = SRL_C && !SRL_Z; export tmpBool; } +cond1: "le" is TOK_CCCC=0x4 + { tmpBool:1 = (SRL_Z || (SRL_N && !SRL_OV) || (!SRL_N && SRL_OV)); export tmpBool; } +cond1: "leu" is TOK_CCCC=0x6 { tmpBool:1 = (!SRL_C || SRL_Z); export tmpBool; } +cond1: "lt" is TOK_CCCC=0x5 { tmpBool:1 = ((SRL_N && !SRL_OV) || (!SRL_N && SRL_OV)); export tmpBool; } +cond1: "n" is TOK_CCCC=0x3 { tmpBool:1 = (SRL_N); export tmpBool; } +cond1: "nc" is TOK_CCCC=0x9 { tmpBool:1 = (!SRL_C); export tmpBool; } +cond1: "nn" is TOK_CCCC=0xB { tmpBool:1 = (!SRL_N); export tmpBool; } +cond1: "nov" is TOK_CCCC=0x8 { tmpBool:1 = (!SRL_OV); export tmpBool; } +cond1: "nz" is TOK_CCCC=0xA { tmpBool:1 = (!SRL_Z); export tmpBool; } +cond2: "oa" is TOK_CCCC=0xC { tmpBool:1 = (SRH_OA); export tmpBool; } +cond2: "ob" is TOK_CCCC=0xD { tmpBool:1 = (SRH_OB); export tmpBool; } +cond1: "ov" is TOK_CCCC=0x0 { tmpBool:1 = (SRL_OV); export tmpBool; } +cond2: "sa" is TOK_CCCC=0xE { tmpBool:1 = (SRH_SA); export tmpBool; } +cond2: "sb" is TOK_CCCC=0xF { tmpBool:1 = (SRH_SB); export tmpBool; } +cond1: "z" is TOK_CCCC=0x2 { tmpBool:1 = (SRL_Z); export tmpBool; } + + + +## +## +## +## conditional branch for the 16-bit status branches above +## +## +## +:bra cond1,n16_t is OP_23_20=0x3 & cond1 & n16_t { + + if ( cond1 ) goto n16_t; +} + + +## +## +## +## conditional branch for the 40-bit status branches above +## +## +## +:bra cond2,n16_t is OP_23_20=0x0 & cond2 & n16_t { + + if ( cond2 ) goto n16_t; +} + + +:bset.w f12_t,bit4_t is OP_23_20=0xA & OP_19_16=0x8 & bit4byte_t & bit4_t & f12_t { + + local mask:2 = 1 << bit4_t; + f12_t = f12_t | mask; +} + + +:bset.w Wsb_t,Bbit4_t is + OP_23_20=0xA & OP_19_16=0x0 & Bbit4_t & OP_11=0x0 & TOK_Bb=0 & OP_9_8=0x0 & OP_7=0x0 & $(WSconstraint) & Wsb_t { + + local mask:2 = 1 << Bbit4_t; + Wsb_t = Wsb_t | mask; +} + + +:bset.b Wsbbyte_t,Bbit4_t is + OP_23_20=0xA & OP_19_16=0x0 & Bbit4_t & OP_11=0x0 & TOK_Bb=1 & OP_9_8=0x0 & OP_7=0x0 & $(WSconstraint) & Wsbbyte_t { + + local mask:1 = 1 << Bbit4_t; + Wsbbyte_t = Wsbbyte_t | mask; +} + + +:bsw.c Ws_t,Wbd_t is OP_23_20=0xA & OP_19_16=0xD & TOK_Z=0 & Wbd_t & OP_10_8=0x0 & OP_7=0x0 & $(WSconstraint) & Ws_t { + + # clear the bit and or flag in; write the bit + local bit = Wbd_t & 0xF; + Ws_t = ( Ws_t & ~(1 << bit) ) | (zext(SRL_C) << bit); +} + + +:bsw.z Ws_t,Wbd_t is OP_23_20=0xA & OP_19_16=0xD & TOK_Z=1 & Wbd_t & OP_10_8=0x0 & OP_7=0x0 & $(WSconstraint) & Ws_t { + + # clear the bit and or flag in; write the bit + local bit = Wbd_t & 0xF; + Ws_t = ( Ws_t & ~(1 << bit) ) | (zext(SRL_Z) << bit); +} + + +:btg^bit4byte_t f12_t,bit4_t is OP_23_20=0xA & OP_19_16=0xA & bit4byte_t & bit4_t & f12_t { + + local mask:2 = 1 << bit4_t; + f12_t = f12_t ^ mask; +} + + +# DSRPAG ????? +:btg.w Wsb_t,Bbit4_t is + OP_23_20=0xA & OP_19_16=0x2 & Bbit4_t & OP_11=0x0 & TOK_Bb=0 & OP_9_8=0x0 & OP_7=0x0 & $(WSconstraint) & Wsb_t { + + local mask:2 = 1 << Bbit4_t; + Wsb_t = Wsb_t ^ mask; +} + + +:btg.b Wsbbyte_t,Bbit4_t is + OP_23_20=0xA & OP_19_16=0x2 & Bbit4_t & OP_11=0x0 & TOK_Bb=1 & OP_9_8=0x0 & OP_7=0x0 & $(WSconstraint) & Wsbbyte_t { + + local mask:1 = 1 << Bbit4_t; + Wsbbyte_t = Wsbbyte_t ^ mask; +} + + +:btsc^bit4byte_t f12_t,bit4_t is OP_23_20=0xA & OP_19_16=0xF & bit4byte_t & bit4_t & f12_t + [ skipInstr = 1; globalset(inst_next,skipInstr); ] { + + local mask:2 = 1 << bit4_t; + SkipNextFlag = ( ( f12_t & mask ) == 0 ); +} + + +:btsc.w Wsb_t,Bbit4_t is OP_23_16=0xa7 & OP_11_7=0x0 & Bbit4_t & $(WSconstraint) & Wsb_t + [ skipInstr = 1; globalset(inst_next,skipInstr); ] { + + local mask:2 = 1 << Bbit4_t; + SkipNextFlag = ( ( Wsb_t & mask ) == 0 ); +} + + +:btss^bit4byte_t f12_t,bit4_t is OP_23_20=0xA & OP_19_16=0xE & bit4byte_t & bit4_t & f12_t + [ skipInstr = 1; globalset(inst_next,skipInstr); ] { + + local mask:2 = 1 << bit4_t; + SkipNextFlag = ( ( f12_t & mask ) != 0 ); +} + + +:btss.w Wsb_t,Bbit4_t is OP_23_16=0xa6 & OP_11_7=0x0 & Bbit4_t & $(WSconstraint) & Wsb_t + [ skipInstr = 1; globalset(inst_next,skipInstr); ] { + + local mask:2 = 1 << Bbit4_t; + SkipNextFlag = ( ( Wsb_t & mask ) != 0 ); +} + + +:btst.w f12_t,bit4_t is OP_23_20=0xA & OP_19_16=0xB & bit4byte_t & bit4_t & f12_t { + + local mask:2 = 1 << bit4_t; + SRL_Z = ( ( f12_t & mask ) == 0 ); +} + + +# 1010 0011 1111 0000 0000 0001 +:btst.c Wsb_t,Bbit4_t is + + OP_23_16=0xa3 & OP_10_7=0x0 & + Bbit4_t & TOK_Zb=0 & OP_10_8=0x0 & $(WSconstraint) & Wsb_t { + + local mask:2 = 1 << Bbit4_t; + + # set C to value of bit + SRL_C = ( Wsb_t & mask ) != 0; +} + + +:btst.z Wsb_t,Bbit4_t is + + OP_23_20=0xA & OP_19_16=0x3 & Bbit4_t & TOK_Zb=1 & OP_10_8=0x0 & OP_7=0x0 & $(WSconstraint) & Wsb_t { + + local mask:2 = 1 << Bbit4_t; + + # set Z to value of bit complemented + SRL_Z = ( Wsb_t & mask ) == 0; +} + + +:btst.c Ws_t,Wbd_t is OP_23_20=0xA & OP_19_16=0x5 & TOK_Z=0 & Wbd_t & OP_10_8=0x0 & OP_7=0x0 & $(WSconstraint) & Ws_t { + + # set C to value of bit + SRL_C = ( Ws_t & (1 << (Wbd_t & 0xF)) ) != 0; +} + + +:btst.z Ws_t,Wbd_t is OP_23_20=0xA & OP_19_16=0x5 & TOK_Z=1 & Wbd_t & OP_10_8=0x0 & OP_7=0x0 & $(WSconstraint) & Ws_t { + + # set Z to value of bit complemented + SRL_Z = ( Ws_t & (1 << (Wbd_t & 0xF)) ) == 0; +} + + +:btsts^bit4byte_t f12_t,bit4_t is OP_23_20=0xA & OP_19_16=0xC & bit4byte_t & bit4_t & f12_t { + + local mask:2 = 1 << bit4_t; + + # set Z to value of bit complemented + SRL_Z = ( ( f12_t & mask ) == 0 ); + + # set value of bit to 1 + f12_t = f12_t | mask; +} + + +# DSRPAG ????? +:btsts.c Wsb_t,Bbit4_t is OP_23_20=0xA & OP_19_16=0x4 & Bbit4_t & TOK_Zb=0 & OP_10_8=0x0 & OP_7=0x0 & $(WSconstraint) & Wsb_t { + + local mask:2 = 1 << Bbit4_t; + local wsSrc = Wsb_t; + + # set C to value of bit + SRL_C = ( wsSrc & mask ) != 0; + + # set value of bit to 1 + Wsb_t = wsSrc | mask; +} + + +:btsts.z Wsb_t,Bbit4_t is OP_23_20=0xA & OP_19_16=0x4 & Bbit4_t & TOK_Zb=1 & OP_10_8=0x0 & OP_7=0x0 & $(WSconstraint) & Wsb_t { + + local mask:2 = 1 << Bbit4_t; + local wsSrc = Wsb_t; + + # set Z to value of bit complemented + SRL_Z = ( wsSrc & mask ) == 0; + + # set value of bit to 1 + Wsb_t = wsSrc | mask; +} + + +@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) +:call dest24_t is ( OP_23_20=0x0 & OP_19_16=0x2 & OP_0=0x0 & WordInstNext4; + OP_23_20=0x0 & OP_19_16=0x0 & OP_15_12=0x0 & OP_11_8=0x0 & OP_7=0x0 ) & dest24_t { + + *[ram]:4 W15 = WordInstNext4; + W15 = W15 + 4; + + call dest24_t; +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:call dest24_t is ( OP_23_20=0x0 & OP_19_16=0x2 & OP_0=0x0; + OP_23_20=0x0 & OP_19_16=0x0 & OP_15_12=0x0 & OP_11_8=0x0 & OP_7=0x0 ) & dest24_t { + + *[ram]:4 W15 = (inst_next / 2) | zext(CORCON_SFA); + W15 = W15 + 4; + + call dest24_t; +} +@endif + + +@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) +:call WnDest_t is OP_23_20=0x0 & OP_19_16=0x1 & OP_15_12=0x0 & OP_11_8=0x0 & OP_7_4=0x0 & WnDest_t & WordInstNext4 { + + *[ram]:4 W15 = WordInstNext4; + W15 = W15 + 4; + + call [WnDest_t]; +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:call WnDest_t is OP_23_20=0x0 & OP_19_16=0x1 & OP_15_12=0x0 & OP_11_8=0x0 & OP_7_4=0x0 & WnDest_t & WordInstNext4 { + + *[ram]:4 W15 = WordInstNext4 | zext(CORCON_SFA); + W15 = W15 + 4; + + call [WnDest_t]; +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:call.l WnWn1_t is OP_23_20=0x0 & OP_19_16=0x1 & OP_15=0x1 & WnWn1_t & OP_10_8=0x0 & OP_7_4=0x0 & WordInstNext4 { + + *[ram]:4 W15 = WordInstNext4 | zext(CORCON_SFA); + W15 = W15 + 4; + + call [WnWn1_t]; +} +@endif + + +:clr.w f13b_t is OP_23_20=0xE & OP_19_16=0xF & OP_15=0 & f13b_t { + + f13b_t = 0; +} + + +:clr.w WREGb_t is OP_23_20=0xE & OP_19_16=0xF & OP_15=0 & WREGb_t { + + WREGb_t = 0; +} + + +:clr.b f13bbyte_t is OP_23_20=0xE & OP_19_16=0xF & OP_15=0 & f13bbyte_t { + + f13bbyte_t = 0; +} + + +:clr.b WREGbbyte_t is OP_23_20=0xE & OP_19_16=0xF & OP_15=0 & WREGbbyte_t { + + WREGbbyte_t = 0; +} + + +:clr.w Wd_t is OP_23_20=0xE & OP_19_16=0xB & OP_15=0x0 & TOK_B=0 & $(WDconstraint) & Wd_t & OP_6_4=0x0 & OP_3_0=0x0 { + + Wd_t = 0; +} + + +:clr.b Wdbyte_t is OP_23_20=0xE & OP_19_16=0xB & OP_15=0x0 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & OP_6_4=0x0 & OP_3_0=0x0 { + + Wdbyte_t = 0; +} + +@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C) +# +# Note: The following constructors have three optional parameters, Wx, Wy and AWB. To implement them +# without if-then-else constructs, the permutations were made. The TOK tokens correspond, in order, +# with the elements that are removed (commented out) from the constructor when the "no prefetch" +# or "no write back" cases occur. Corresponding sub-constructors were also removed from the display +# section because an unused destination would otherwise be displayed (i.e. "clr ACCAW4W4" -> "clr ACCA"). +# + +## +## +## ACCA series +## +## + +:clr ACCA_t is + OP_23_20=0xC & OP_19_16=0x3 & ACCA_t & OP_14=0x0 & + TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # 0 -> ACCA + ACCA = 0; + SRH_OA = 0; + SRH_SA = 0; + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCB rounded -> AWB +# AWB_t = ACCBH; +} + + +:clr ACCA_t^AWB_t is + OP_23_20=0xC & OP_19_16=0x3 & ACCA_t & OP_14=0x0 & + TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # 0 -> ACCA + ACCA = 0; + SRH_OA = 0; + SRH_SA = 0; + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCB rounded -> AWB + AWB_t = ACCBH; +} + + +:clr ACCA_t^Wy_t^Wyd_t is + OP_23_20=0xC & OP_19_16=0x3 & ACCA_t & OP_14=0x0 & + TOK_9_6_iiii=0x4 & TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # 0 -> ACCA + ACCA = 0; + SRH_OA = 0; + SRH_SA = 0; + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCB rounded -> AWB +# AWB_t = ACCBH; +} + + +:clr ACCA_t^Wy_t^Wyd_t^AWB_t is + OP_23_20=0xC & OP_19_16=0x3 & ACCA_t & OP_14=0x0 & + TOK_9_6_iiii=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # 0 -> ACCA + ACCA = 0; + SRH_OA = 0; + SRH_SA = 0; + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCB rounded -> AWB + AWB_t = ACCBH; +} + + +:clr ACCA_t^Wx_t^Wxd_t is + OP_23_20=0xC & OP_19_16=0x3 & ACCA_t & OP_14=0x0 & + TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # 0 -> ACCA + ACCA = 0; + SRH_OA = 0; + SRH_SA = 0; + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCB rounded -> AWB +# AWB_t = ACCBH; +} + + +:clr ACCA_t^Wx_t^Wxd_t^AWB_t is + OP_23_20=0xC & OP_19_16=0x3 & ACCA_t & OP_14=0x0 & + TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # 0 -> ACCA + ACCA = 0; + SRH_OA = 0; + SRH_SA = 0; + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCB rounded -> AWB + AWB_t = ACCBH; +} + + +:clr ACCA_t^Wx_t^Wxd_t^Wy_t^Wyd_t is + OP_23_20=0xC & OP_19_16=0x3 & ACCA_t & OP_14=0x0 & + TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # 0 -> ACCA + ACCA = 0; + SRH_OA = 0; + SRH_SA = 0; + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCB rounded -> AWB +# AWB_t = ACCBH; +} + + +:clr ACCA_t^Wx_t^Wxd_t^Wy_t^Wyd_t^AWB_t is + OP_23_20=0xC & OP_19_16=0x3 & ACCA_t & OP_14=0x0 & + + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # 0 -> ACCA + ACCA = 0; + SRH_OA = 0; + SRH_SA = 0; + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCB rounded -> AWB + AWB_t = ACCBH; +} + +## +## +## ACCB series +## +## + +:clr ACCB_t is + OP_23_20=0xC & OP_19_16=0x3 & ACCB_t & OP_14=0x0 & + TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + ACCB = 0; + SRH_OB = 0; + SRH_SB = 0; + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCA rounded -> AWB +# AWB_t = ACCAH; +} + + +:clr ACCB_t^AWB_t is + OP_23_20=0xC & OP_19_16=0x3 & ACCB_t & OP_14=0x0 & + TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + ACCB = 0; + SRH_OB = 0; + SRH_SB = 0; + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCA rounded -> AWB + AWB_t = ACCAH; +} + + +:clr ACCB_t^Wy_t^Wyd_t is + OP_23_20=0xC & OP_19_16=0x3 & ACCB_t & OP_14=0x0 & + TOK_9_6_iiii=0x4 & TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + ACCB = 0; + SRH_OB = 0; + SRH_SB = 0; + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCA rounded -> AWB +# AWB_t = ACCAH; +} + + +:clr ACCB_t^Wy_t^Wyd_t^AWB_t is + OP_23_20=0xC & OP_19_16=0x3 & ACCB_t & OP_14=0x0 & + TOK_9_6_iiii=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + ACCB = 0; + SRH_OB = 0; + SRH_SB = 0; + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCA rounded -> AWB + AWB_t = ACCAH; +} + + +:clr ACCB_t^Wy_t^Wyd_t^AWB_t is + OP_23_20=0xC & OP_19_16=0x3 & ACCB_t & OP_14=0x0 & + TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + ACCB = 0; + SRH_OB = 0; + SRH_SB = 0; + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCA rounded -> AWB +# AWB_t = ACCAH; +} + + +:clr ACCB_t^Wx_t^Wxd_t^AWB_t is + OP_23_20=0xC & OP_19_16=0x3 & ACCB_t & OP_14=0x0 & + TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + ACCB = 0; + SRH_OB = 0; + SRH_SB = 0; + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCA rounded -> AWB + AWB_t = ACCAH; +} + + +:clr ACCB_t^Wx_t^Wxd_t^Wy_t^Wyd_t is + OP_23_20=0xC & OP_19_16=0x3 & ACCB_t & OP_14=0x0 & + TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + ACCB = 0; + SRH_OB = 0; + SRH_SB = 0; + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCA rounded -> AWB +# AWB_t = ACCAH; +} + + +:clr ACCB_t^Wx_t^Wxd_t^Wy_t^Wyd_t^AWB_t is + OP_23_20=0xC & OP_19_16=0x3 & ACCB_t & OP_14=0x0 & + + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + ACCB = 0; + SRH_OB = 0; + SRH_SB = 0; + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCA rounded -> AWB + AWB_t = ACCAH; +} +@endif + + +:clrwdt is OP_23_20=0xF & OP_19_16=0xE & OP_15_12=0x6 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 { + + WDTcount = 0; # ????? formal name not documented + WDTprescalarA = 0; # ????? formal name not documented + WDTprescalarB = 0; # ????? formal name not documented +} + + +:com.w f13_t^WREG_t is OP_23_20=0xE & OP_19_16=0xE & OP_15=1 & WREG_t & f13_t { + + WREG_t = ~f13_t; + + testSRL_N ( WREG_t ); + testSRL_Z ( WREG_t ); +} + +:com.b f13byte_t^WREGbyte_t is OP_23_20=0xE & OP_19_16=0xE & OP_15=1 & WREGbyte_t & f13byte_t { + + WREGbyte_t = ~f13byte_t; + + testSRL_N ( WREGbyte_t ); + testSRL_Z ( WREGbyte_t ); +} + + +:com.w Ws_t,Wd_t is OP_23_20=0xE & OP_19_16=0xA & OP_15=0x1 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t { + + local result = ~Ws_t; + build Wd_t; + Wd_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); +} + + +:com.b Wsbyte_t,Wdbyte_t is OP_23_20=0xE & OP_19_16=0xA & OP_15=0x1 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { + + local result = ~Wsbyte_t; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); +} + + +:cp.w f13_t is OP_23_20=0xE & OP_19_16=0x3 & OP_15=0 & OP_13=0 & f13_t { + + local src = f13_t; + subflags( src, W0 ); + + local tmp:2 = src - W0; + + testSRL_N ( tmp ); + testSRL_Z ( tmp ); + testSRH_DCword( tmp ); +} + + +:cp.b f13byte_t is OP_23_20=0xE & OP_19_16=0x3 & OP_15=0 & OP_13=0 & f13byte_t { + + local src = f13byte_t; + subflags( src, W0byte ); + + local tmp:1 = src - W0byte; + + testSRL_N ( tmp ); + testSRL_Z ( tmp ); + testSRH_DCbyte( tmp ); +} + + +@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) +:cp.w Wbb_t,k5_B10_t is OP_23_20=0xE & OP_19_16=0x1 & OP_15=0x0 & OP_9_8=0x0 & OP_7_5=0x3 & Wbb_t & k5_B10_t { + + subflags( Wbb_t, k5_B10_t ); + + tmp:2 = Wbb_t - k5_B10_t; + + testSRL_N ( tmp ); + testSRL_Z ( tmp ); + testSRH_DCword( tmp ); +} + + +:cp.b Wbbbyte_t,k5byte_B10_t is + OP_23_20=0xE & OP_19_16=0x1 & OP_15=0x0 & OP_9_8=0x0 & OP_7_5=0x3 & Wbbbyte_t & k5byte_B10_t { + + subflags( Wbbbyte_t, k5byte_B10_t ); + + tmp:1 = Wbbbyte_t - k5byte_B10_t; + + testSRL_N ( tmp ); + testSRL_Z ( tmp ); + testSRH_DCbyte( tmp ); +} +@endif + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) + +:cp.w Wbb_t,k8_t is OP_23_20=0xE & OP_19_16=0x1 & OP_15=0x0 & TOK_Bb=0 & OP_6_5=0x3 & Wbb_t & k8_t { + + subflags( Wbb_t, k8_t ); + + tmp:2 = Wbb_t - k8_t; + + testSRL_N ( tmp ); + testSRL_Z ( tmp ); + testSRH_DCword( tmp ); +} + + +:cp.b Wbbbyte_t,k8byte_t is OP_23_20=0xE & OP_19_16=0x1 & OP_15=0x0 & TOK_Bb=1 & OP_6_5=0x3 & Wbbbyte_t & k8byte_t { + + subflags( Wbbbyte_t, k8byte_t ); + + tmp:1 = Wbbbyte_t - k8byte_t; + + testSRL_N ( tmp ); + testSRL_Z ( tmp ); + testSRH_DCbyte( tmp ); +} +@endif + + +:cp.w Wbb_t,Wsb_t is OP_23_20=0xE & OP_19_16=0x1 & OP_15=0x0 & TOK_Bb=0 & OP_9_8=0x0 & OP_7=0x0 & Wbb_t & $(WSconstraint) & Wsb_t { + + local src = Wsb_t; + subflags( Wbb_t, src ); + + tmp:2 = Wbb_t - src; + + testSRL_N ( tmp ); + testSRL_Z ( tmp ); + testSRH_DCword( tmp ); +} + + +:cp.b Wbbbyte_t,Wsbbyte_t is + OP_23_20=0xE & OP_19_16=0x1 & OP_15=0x0 & TOK_Bb=1 & OP_9_8=0x0 & OP_7=0x0 & Wbbbyte_t & $(WSconstraint) & Wsbbyte_t { + + local src = Wsbbyte_t; + subflags( Wbbbyte_t, src ); + + tmp:1 = Wbbbyte_t - src; + + testSRL_N ( tmp ); + testSRL_Z ( tmp ); + testSRH_DCbyte( tmp ); +} + + +:cp0.w f13_t is OP_23_20=0xE & OP_19_16=0x2 & OP_15=0 & OP_13=0 & f13_t { + + local src = f13_t; + local zero:2 = 0; + subflags( src, zero ); + + testSRL_N ( src ); + testSRL_Z ( src ); + testSRH_DCword( src ); +} + + +:cp0.b f13byte_t is OP_23_20=0xE & OP_19_16=0x2 & OP_15=0 & OP_13=0 & f13byte_t { + + local src = f13byte_t; + local zero:1 = 0; + subflags( src, zero ); + + testSRL_N ( src ); + testSRL_Z ( src ); + testSRH_DCbyte( src ); +} + + +:cp0.w Wsb_t is OP_23_20=0xE & OP_19_16=0x0 & OP_15_12=0x0 & OP_11=0x0 & TOK_Bb=0 & OP_9_8=0x0 & OP_7=0x0 & $(WSconstraint) & Wsb_t { + + local src = Wsb_t; + local zero:2 = 0; + subflags( src, zero ); + + testSRL_N ( src ); + testSRL_Z ( src ); + testSRH_DCword( src ); +} + + +:cp0.b Wsbbyte_t is OP_23_20=0xE & OP_19_16=0x0 & OP_15_12=0x0 & OP_11=0x0 & TOK_Bb=1 & OP_9_8=0x0 & OP_7=0x0 & $(WSconstraint) & Wsbbyte_t { + + local src = Wsbbyte_t; + local zero:1 = 0; + subflags( src, zero ); + + testSRL_N ( src ); + testSRL_Z ( src ); + testSRH_DCbyte( src ); +} + + +:cpb.w f13_t is OP_23_20=0xE & OP_19_16=0x3 & OP_15=1 & OP_13=0 & f13_t { + + local notCarry:2 = zext(!SRL_C); + local src = f13_t; + subflagsWithCarry( src, W0, notCarry ); + + tmp:2 = src - W0 - notCarry; + + testSRL_N ( tmp ); + testSRL_Zsticky( tmp ); + testSRH_DCword ( tmp ); +} + + +:cpb.b f13byte_t is OP_23_20=0xE & OP_19_16=0x3 & OP_15=1 & OP_13=0 & f13byte_t { + + local notCarry = !SRL_C; + local src = f13byte_t; + subflagsWithCarry( src, W0byte, notCarry ); + + tmp:1 = src - W0byte - notCarry; + + testSRL_N ( tmp ); + testSRL_Zsticky( tmp ); + testSRH_DCbyte ( tmp ); +} + + +@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) +:cpb.w Wb_t,k5_t is OP_23_20=0xE & OP_19_16=0x1 & OP_15=0x1 & OP_9_8=0x0 & OP_7_5=0x3 & Wb_t & k5_t { + + local notCarry:2 = zext(!SRL_C); + subflagsWithCarry( Wb_t, k5_t, notCarry ); + + tmp:2 = Wb_t - k5_t - notCarry; + + testSRL_N ( tmp ); + testSRL_Zsticky( tmp ); + testSRH_DCword ( tmp ); +} + + +:cpb.b Wbbyte_t,k5byte_t is + OP_23_20=0xE & OP_19_16=0x1 & OP_15=0x1 & OP_9_8=0x0 & OP_7_5=0x3 & Wbbyte_t & k5byte_t { + + local notCarry = !SRL_C; + subflagsWithCarry( Wbbyte_t, k5byte_t, notCarry ); + + tmp:1 = Wbbyte_t - k5byte_t - notCarry; + + testSRL_N ( tmp ); + testSRL_Zsticky( tmp ); + testSRH_DCbyte ( tmp ); +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:cpb.w Wbb_t,k8_t is OP_23_20=0xE & OP_19_16=0x1 & OP_15=0x1 & TOK_Bb=0 & OP_6_5=0x3 & Wbb_t & k8_t { + + local notCarry:2 = zext(!SRL_C); + subflagsWithCarry( Wbb_t, k8_t, notCarry ); + + tmp:2 = Wbb_t - k8_t - notCarry; + + testSRL_N ( tmp ); + testSRL_Zsticky( tmp ); + testSRH_DCword ( tmp ); +} + + +:cpb.b Wbbbyte_t,k8byte_t is OP_23_20=0xE & OP_19_16=0x1 & OP_15=0x1 & TOK_Bb=1 & OP_6_5=0x3 & Wbbbyte_t & k8byte_t { + + local notCarry = !SRL_C; + subflagsWithCarry( Wbbbyte_t, k8byte_t, notCarry ); + + tmp:1 = Wbbbyte_t - k8byte_t - notCarry; + + testSRL_N ( tmp ); + testSRL_Zsticky( tmp ); + testSRH_DCbyte ( tmp ); +} +@endif + + +:cpb.w Wbb_t,Wsb_t is OP_23_20=0xE & OP_19_16=0x1 & OP_15=0x1 & TOK_Bb=0 & OP_9_8=0x0 & OP_7=0x0 & Wbb_t & $(WSconstraint) & Wsb_t { + + local notCarry:2 = zext(!SRL_C); + local src = Wsb_t; + subflagsWithCarry( Wbb_t, src, notCarry ); + + tmp:2 = Wbb_t - src - notCarry; + + testSRL_N ( tmp ); + testSRL_Zsticky( tmp ); + testSRH_DCword ( tmp ); +} + + +:cpb.b Wbbbyte_t,Wsbbyte_t is + OP_23_20=0xE & OP_19_16=0x1 & OP_15=0x1 & TOK_Bb=1 & OP_9_8=0x0 & OP_7=0x0 & Wbbbyte_t & $(WSconstraint) & Wsbbyte_t { + + local notCarry = !SRL_C; + local src = Wsbbyte_t; + subflagsWithCarry( Wbbbyte_t, src, notCarry ); + + tmp:1 = Wbbbyte_t - src - notCarry; + + testSRL_N ( tmp ); + testSRL_Zsticky( tmp ); + testSRH_DCbyte ( tmp ); +} + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:cpbeq.w Wbb_t,Wnb_t,n6_t is OP_23_20=0xE & OP_19_16=0x7 & OP_15=0x1 & TOK_Bb=0 & Wbb_t & n6_t & Wnb_t { + + if (Wbb_t == Wnb_t) goto n6_t; # ????? what about the flags, examples show them setting? +} + + +:cpbeq.b Wbbbyte_t,Wnbbyte_t,n6_t is + OP_23_20=0xE & OP_19_16=0x7 & OP_15=0x1 & TOK_Bb=1 & Wbbbyte_t & n6_t & Wnbbyte_t { + + if (Wbbbyte_t == Wnbbyte_t) goto n6_t; +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:cpbgt.w Wbb_t,Wnb_t,n6_t is OP_23_20=0xE & OP_19_16=0x6 & OP_15=0x0 & TOK_Bb=0 & Wbb_t & n6_t & Wnb_t { + + if (Wbb_t s> Wnb_t) goto n6_t; # ????? what about the flags, examples show them setting? +} + + +:cpbgt.b Wbbbyte_t,Wnbbyte_t,n6_t is + OP_23_20=0xE & OP_19_16=0x6 & OP_15=0x0 & TOK_Bb=1 & Wbbbyte_t & n6_t & Wnbbyte_t { + + if (Wbbbyte_t s> Wnbbyte_t) goto n6_t; +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:cpblt.w Wbb_t,Wnb_t,n6_t is OP_23_20=0xE & OP_19_16=0x6 & OP_15=0x1 & TOK_Bb=0 & Wbb_t & n6_t & Wnb_t { + + if (Wbb_t s< Wnb_t) goto n6_t; # ????? what about the flags, examples show them setting? +} + + +:cpblt.b Wbbbyte_t,Wnbbyte_t,n6_t is + OP_23_20=0xE & OP_19_16=0x6 & OP_15=0x1 & TOK_Bb=1 & Wbbbyte_t & n6_t & Wnbbyte_t { + + if (Wbbbyte_t s< Wnbbyte_t) goto n6_t; +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:cpbne.w Wbb_t,Wnb_t,n6_t is OP_23_20=0xE & OP_19_16=0x7 & OP_15=0x0 & TOK_Bb=0 & Wbb_t & n6_t & Wnb_t { + + if (Wbb_t != Wnb_t) goto n6_t; # ????? what about the flags, examples show them setting? +} + + +:cpbne.b Wbbbyte_t,Wnbbyte_t,n6_t is OP_23_20=0xE & OP_19_16=0x7 & OP_15=0x0 & TOK_Bb=1 & Wbbbyte_t & n6_t & Wnbbyte_t { + + if (Wbbbyte_t != Wnbbyte_t) goto n6_t; +} +@endif + + +@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) +:cpseq.w Wbb_t,Wnb_t is + OP_23_20=0xE & OP_19_16=0x7 & OP_15=0x1 & TOK_Bb=0 & Wbb_t & OP_9_8=0x0 & OP_7_4=0x0 & Wnb_t + [ skipInstr = 1; globalset(inst_next,skipInstr); ] { + + SkipNextFlag = (Wbb_t == Wnb_t); # ????? what about the flags, examples show them setting? +} + + +:cpseq.b Wbbbyte_t,Wnbbyte_t is + OP_23_20=0xE & OP_19_16=0x7 & OP_15=0x1 & TOK_Bb=1 & Wbbbyte_t & OP_9_8=0x0 & OP_7_4=0x0 & Wnbbyte_t + [ skipInstr = 1; globalset(inst_next,skipInstr); ] { + + SkipNextFlag = (Wbbbyte_t == Wnbbyte_t); +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:cpseq.w Wbb_t,Wnb_t is + OP_23_20=0xE & OP_19_16=0x7 & OP_15=0x1 & TOK_Bb=0 & Wbb_t & OP_9_8=0x0 & OP_7_4=0x1 & Wnb_t + [ skipInstr = 1; globalset(inst_next,skipInstr); ] { + + SkipNextFlag = (Wbb_t == Wnb_t); # ????? what about the flags, examples show them setting? +} + + +:cpseq.b Wbbbyte_t,Wnbbyte_t is + OP_23_20=0xE & OP_19_16=0x7 & OP_15=0x1 & TOK_Bb=1 & Wbbbyte_t & OP_9_8=0x0 & OP_7_4=0x1 & Wnbbyte_t + [ skipInstr = 1; globalset(inst_next,skipInstr); ] { + + SkipNextFlag = (Wbbbyte_t == Wnbbyte_t); +} +@endif + + +@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) +:cpsgt.w Wbb_t,Wnb_t is + OP_23_20=0xE & OP_19_16=0x6 & OP_15=0x0 & TOK_Bb=0 & Wbb_t & OP_9_8=0x0 & OP_7_4=0x0 & Wnb_t + [ skipInstr = 1; globalset(inst_next,skipInstr); ] { + + SkipNextFlag = (Wbb_t s> Wnb_t); # ????? what about the flags, examples show them setting? +} + + +:cpsgt.b Wbbbyte_t,Wnbbyte_t is + OP_23_20=0xE & OP_19_16=0x6 & OP_15=0x0 & TOK_Bb=1 & Wbbbyte_t & OP_9_8=0x0 & OP_7_4=0x0 & Wnbbyte_t + [ skipInstr = 1; globalset(inst_next,skipInstr); ] { + + SkipNextFlag = (Wbbbyte_t s> Wnbbyte_t); +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:cpsgt.w Wbb_t,Wnb_t is + OP_23_20=0xE & OP_19_16=0x6 & OP_15=0x0 & TOK_Bb=0 & Wbb_t & OP_9_8=0x0 & OP_7_4=0x1 & Wnb_t + [ skipInstr = 1; globalset(inst_next,skipInstr); ] { + + SkipNextFlag = (Wbb_t s> Wnb_t); # ????? what about the flags, examples show them setting? +} + + +:cpsgt.b Wbbbyte_t,Wnbbyte_t is + OP_23_20=0xE & OP_19_16=0x6 & OP_15=0x0 & TOK_Bb=1 & Wbbbyte_t & OP_9_8=0x0 & OP_7_4=0x1 & Wnbbyte_t + [ skipInstr = 1; globalset(inst_next,skipInstr); ] { + + SkipNextFlag = (Wbbbyte_t s> Wnbbyte_t); +} +@endif + + +@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) +:cpslt.w Wbb_t,Wnb_t is + OP_23_20=0xE & OP_19_16=0x6 & OP_15=0x1 & TOK_Bb=0 & Wbb_t & OP_9_8=0x0 & OP_7_4=0x0 & Wnb_t + [ skipInstr = 1; globalset(inst_next,skipInstr); ] { + + SkipNextFlag = (Wbb_t s< Wnb_t); # ????? what about the flags, examples show them setting? +} + + +:cpslt.b Wbbbyte_t,Wnbbyte_t is + OP_23_20=0xE & OP_19_16=0x6 & OP_15=0x1 & TOK_Bb=1 & Wbbbyte_t & OP_9_8=0x0 & OP_7_4=0x0 & Wnbbyte_t + [ skipInstr = 1; globalset(inst_next,skipInstr); ] { + + SkipNextFlag = (Wbbbyte_t s< Wnbbyte_t); +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:cpslt.w Wbb_t,Wnb_t is + OP_23_20=0xE & OP_19_16=0x6 & OP_15=0x1 & TOK_Bb=0 & Wbb_t & OP_9_8=0x0 & OP_7_4=0x1 & Wnb_t + [ skipInstr = 1; globalset(inst_next,skipInstr); ] { + + SkipNextFlag = (Wbb_t s< Wnb_t); # ????? what about the flags, examples show them setting? +} + + +:cpslt.b Wbbbyte_t,Wnbbyte_t is + OP_23_20=0xE & OP_19_16=0x6 & OP_15=0x1 & TOK_Bb=1 & Wbbbyte_t & OP_9_8=0x0 & OP_7_4=0x1 & Wnbbyte_t + [ skipInstr = 1; globalset(inst_next,skipInstr); ] { + + SkipNextFlag = (Wbbbyte_t s< Wnbbyte_t); +} +@endif + + +@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) +:cpsne.w Wbb_t,Wnb_t is + OP_23_20=0xE & OP_19_16=0x7 & OP_15=0x0 & TOK_Bb=0 & Wbb_t & OP_9_8=0x0 & OP_7_4=0x0 & Wnb_t + [ skipInstr = 1; globalset(inst_next,skipInstr); ] { + + SkipNextFlag = (Wbb_t != Wnb_t); # ????? what about the flags, examples show them setting? +} + + +:cpsne.b Wbbbyte_t,Wnbbyte_t is + OP_23_20=0xE & OP_19_16=0x7 & OP_15=0x0 & TOK_Bb=1 & Wbbbyte_t & OP_9_8=0x0 & OP_7_4=0x0 & Wnbbyte_t + [ skipInstr = 1; globalset(inst_next,skipInstr); ] { + + SkipNextFlag = (Wbbbyte_t != Wnbbyte_t); +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:cpsne.w Wbb_t,Wnb_t is + OP_23_20=0xE & OP_19_16=0x7 & OP_15=0x0 & TOK_Bb=0 & Wbb_t & OP_9_8=0x0 & OP_7_4=0x1 & Wnb_t + [ skipInstr = 1; globalset(inst_next,skipInstr); ] { + + SkipNextFlag = (Wbb_t != Wnb_t); # ????? what about the flags, examples show them setting? +} + + +:cpsne.b Wbbbyte_t,Wnbbyte_t is + OP_23_20=0xE & OP_19_16=0x7 & OP_15=0x0 & TOK_Bb=1 & Wbbbyte_t & OP_9_8=0x0 & OP_7_4=0x1 & Wnbbyte_t + [ skipInstr = 1; globalset(inst_next,skipInstr); ] { + + SkipNextFlag = (Wbbbyte_t != Wnbbyte_t); +} +@endif + + +@if defined(dsPIC33E) || defined(dsPIC33C) +define pcodeop contextswap; +:ctxtswp k3_t is OP_23_4=0xFE200 & OP_3=0x0 & k3_t { + contextswap(k3_t); +} + +:ctxtswp Wndb_t is OP_23_4=0xFEF00 & Wndb_t { + contextswap(Wndb_t); +} +@endif + +:daw.b Wnsbyte_t is OP_23_20=0xF & OP_19_16=0xD & OP_15_12=0x4 & OP_11_8=0x0 & OP_7_4=0x0 & Wnsbyte_t { + + if !( ( ( Wnsbyte_t & 0x0F ) > 0x09 ) || SRH_DC ) goto ; + Wnsbyte_t = Wnsbyte_t + 0x06; + + + if !( ( ( Wnsbyte_t & 0xF0 ) > 0x90 ) || SRL_C ) goto ; + Wnsbyte_t = Wnsbyte_t + 0x60; + SRL_C = 1; + +} + + +:dec.w f13_t,^WREG_t is OP_23_20=0xE & OP_19_16=0xD & OP_15=0 & WREG_t & f13_t { + + local src = f13_t; + local one:2 = 1; + subflags( src, one ); + + WREG_t = src - one; + + testSRL_N ( WREG_t ); + testSRL_Z ( WREG_t ); + testSRH_DCword( WREG_t ); +} + + +:dec.b f13byte_t^WREGbyte_t is OP_23_20=0xE & OP_19_16=0xD & OP_15=0 & WREGbyte_t & f13byte_t { + + local src = f13byte_t; + local one:1 = 1; + subflags( src, one ); + + WREGbyte_t = src - one; + + testSRL_N ( WREGbyte_t ); + testSRL_Z ( WREGbyte_t ); + testSRH_DCbyte( WREGbyte_t ); +} + + +:dec.w Ws_t,Wd_t is OP_23_20=0xE & OP_19_16=0x9 & OP_15=0x0 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t { + + local src = Ws_t; + local one:2 = 1; + subflags( src, one ); + + local result = src - one; + build Wd_t; + Wd_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); + testSRH_DCword( result ); +} + + +:dec.b Wsbyte_t,Wdbyte_t is OP_23_20=0xE & OP_19_16=0x9 & OP_15=0x0 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { + + local src = Wsbyte_t; + local one:1 = 1; + subflags( src, one ); + + local result = src - one; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); + testSRH_DCbyte( result ); +} + + +:dec2.w f13_t^WREG_t is OP_23_20=0xE & OP_19_16=0xD & OP_15=1 & WREG_t & f13_t { + + local src = f13_t; + local two:2 = 2; + subflags( src, two ); + + WREG_t = src - two; + + testSRL_N ( WREG_t ); + testSRL_Z ( WREG_t ); + testSRH_DCword( WREG_t ); +} + + +:dec2.b f13byte_t^WREGbyte_t is OP_23_20=0xE & OP_19_16=0xD & OP_15=1 & WREGbyte_t & f13byte_t { + + local src = f13byte_t; + local two:1 = 2; + subflags( src, two ); + + WREGbyte_t = src - two; + + testSRL_N ( WREGbyte_t ); + testSRL_Z ( WREGbyte_t ); + testSRH_DCbyte( WREGbyte_t ); +} + + +:dec2.w Ws_t,Wd_t is OP_23_20=0xE & OP_19_16=0x9 & OP_15=0x1 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t { + + local src = Ws_t; + local two:2 = 2; + subflags( src, two ); + + local result = src - two; + build Wd_t; + Wd_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); + testSRH_DCword( result ); +} + + +:dec2.b Wsbyte_t,Wdbyte_t is OP_23_20=0xE & OP_19_16=0x9 & OP_15=0x1 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { + + local src = Wsbyte_t; + local two:1 = 2; + subflags( src, two ); + + local result = src - two; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); + testSRH_DCbyte( result ); +} + + +:disi k14_t is OP_23_20=0xF & OP_19_16=0xC & OP_15_14=0x0 & k14_t { + + DISICNT = k14_t; + DISI = 1; +} + + +:repeat" 0x11 div.sw" TOK_10_7_Wreg,TOK_3_0_Wreg is + OP_31_0=0x090011; + OP_23_20=0xD & OP_19_16=0x8 & OP_15=0x0 & TOK_10_7_Wreg & TOK_W=0 & OP_5_4=0x0 & TOK_3_0_Wreg { + + # Note: this implementation is not iterative, like the actual op. + # Rather, it will decompile accurately and emulate correctly using the Sleigh divide support. + local div:2 = sext(TOK_10_7_Wreg) s/ sext(TOK_3_0_Wreg); + local rem:2 = sext(TOK_10_7_Wreg) s% sext(TOK_3_0_Wreg); + + W0 = div:1; + W1 = rem:1; + + testSRL_N ( W1 ); + + # overflow as defined in note 2 + SRL_OV = (TOK_10_7_Wreg == 0x8000) && (TOK_3_0_Wreg == 0xFFFF); + + testSRL_Z ( W1 ); + + # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis + SRL_C = 0; +} + +define pcodeop pic30_div; +define pcodeop pic30_rem; + +:div.sw TOK_10_7_Wreg,TOK_3_0_Wreg is + OP_23_20=0xD & OP_19_16=0x8 & OP_15=0x0 & TOK_10_7_Wreg & TOK_W=0 & OP_5_4=0x0 & TOK_3_0_Wreg { + local div:2 = pic30_div(TOK_10_7_Wreg,TOK_3_0_Wreg); + local rem:2 = pic30_rem(TOK_10_7_Wreg,TOK_3_0_Wreg); + + W0 = div; + W1 = rem; + + testSRL_N ( W1 ); + # overflow as defined in note 2 + SRL_OV = (TOK_10_7_Wreg == 0x8000) && (TOK_3_0_Wreg == 0xFFFF); + testSRL_Z ( W1 ); + + # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis + SRL_C = 0; +} + +define pcodeop isDivideOverflow; + +:repeat" 0x11 div.sd" TOK_10_8_Dregn,TOK_3_0_Wreg is + OP_31_0=0x090011; + OP_23_20=0xD & OP_19_16=0x8 & OP_15=0x0 & + TOK_10_8_Dreg & TOK_10_8_Dregn & OP_7=0 & TOK_W=1 & OP_5_4=0x0 & TOK_3_0_Wreg { + + # overflow as defined in note 2 + SRL_OV = isDivideOverflow(TOK_10_8_Dreg, TOK_3_0_Wreg); + + # Note: this implementation is not iterative, like the actual op. + # Rather, it will decompile accurately and emulate correctly using the Sleigh divide support. + local div:4 = TOK_10_8_Dreg s/ sext(TOK_3_0_Wreg); + local rem:4 = TOK_10_8_Dreg s% sext(TOK_3_0_Wreg); + W0 = div:2; + W1 = rem:2; + + testSRL_N ( W1 ); + testSRL_Z ( W1 ); + + # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis + SRL_C = 0; +} + +:div.sd TOK_10_8_Dregn,TOK_3_0_Wreg is + OP_23_20=0xD & OP_19_16=0x8 & OP_15=0x0 & + TOK_10_8_Dreg & TOK_10_8_Dregn & OP_7=0 & TOK_W=1 & OP_5_4=0x0 & TOK_3_0_Wreg { + + # overflow as defined in note 2 + SRL_OV = isDivideOverflow(TOK_10_8_Dreg, TOK_3_0_Wreg); + + local div:4 = pic30_div(TOK_10_8_Dreg,TOK_3_0_Wreg); + local rem:4 = pic30_rem(TOK_10_8_Dreg,TOK_3_0_Wreg); + + W0 = div:2; + W1 = rem:2; + + testSRL_N ( W1 ); + testSRL_Z ( W1 ); + + # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis + SRL_C = 0; +} + + +:repeat" 0x11 div.uw" TOK_10_7_Wreg,TOK_3_0_Wreg is + OP_31_0=0x090011; + OP_23_20=0xD & OP_19_16=0x8 & OP_15=0x1 & + TOK_10_7_Wreg & TOK_W=0 & OP_5_4=0x0 & TOK_3_0_Wreg { + + # Note: this implementation is not iterative, like the actual op. + # Rather, it will decompile accurately and emulate correctly using the Sleigh divide support. + local div:2 = zext(TOK_10_7_Wreg) / zext(TOK_3_0_Wreg); + local rem:2 = zext(TOK_10_7_Wreg) % zext(TOK_3_0_Wreg); + + W0 = div:1; + W1 = rem:1; + + testSRL_N ( W1 ); + + # overflow as defined in note 2 + SRL_OV = 0; + + testSRL_Z ( W1 ); + + # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis + SRL_C = 0; +} + +:div.uw TOK_10_7_Wreg,TOK_3_0_Wreg is + OP_23_20=0xD & OP_19_16=0x8 & OP_15=0x1 & + TOK_10_7_Wreg & TOK_W=0 & OP_5_4=0x0 & TOK_3_0_Wreg { + local div:2 = pic30_div(TOK_10_7_Wreg,TOK_3_0_Wreg); + local rem:2 = pic30_rem(TOK_10_7_Wreg,TOK_3_0_Wreg); + + W0 = div; + W1 = rem; + + testSRL_N ( W1 ); + + # overflow as defined in note 2 + SRL_OV = 0; + + testSRL_Z ( W1 ); + + # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis + SRL_C = 0; +} + +:repeat" 0x11 div.ud" TOK_10_8_Dregn,TOK_3_0_Wreg is + OP_31_0=0x090011; + OP_23_20=0xD & OP_19_16=0x8 & OP_15=0x1 & + TOK_10_8_Dreg & TOK_10_8_Dregn & OP_7=0 & TOK_W=1 & OP_5_4=0x0 & TOK_3_0_Wreg { + + # overflow as defined in note 2 + SRL_OV = isDivideOverflow(TOK_10_8_Dreg, TOK_3_0_Wreg); + + # Note: this implementation is not iterative, like the actual op. + # Rather, it will decompile accurately and emulate correctly using the Sleigh divide support. + local div:4 = TOK_10_8_Dreg / sext(TOK_3_0_Wreg); + local rem:4 = TOK_10_8_Dreg % sext(TOK_3_0_Wreg); + W0 = div:2; + W1 = rem:2; + + testSRL_N ( W1 ); + testSRL_Z ( W1 ); + + # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis + SRL_C = 0; +} + +:div.ud TOK_10_8_Dregn,TOK_3_0_Wreg is + OP_23_20=0xD & OP_19_16=0x8 & OP_15=0x1 & + TOK_10_8_Dreg & TOK_10_8_Dregn & OP_7=0 & TOK_W=1 & OP_5_4=0x0 & TOK_3_0_Wreg { + + # overflow as defined in note 2 + SRL_OV = isDivideOverflow(TOK_10_8_Dreg, TOK_3_0_Wreg); + + local div:4 = pic30_div(TOK_10_8_Dreg,TOK_3_0_Wreg); + local rem:4 = pic30_rem(TOK_10_8_Dreg,TOK_3_0_Wreg); + W0 = div:2; + W1 = rem:2; + + + testSRL_N ( W1 ); + testSRL_Z ( W1 ); + + # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis + SRL_C = 0; +} + + +@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C) +:repeat" 0x11 divf" TOK_14_11_Wreg,TOK_3_0_Wreg is + OP_31_0=0x090011; + OP_23_20=0xD & OP_19_16=0x9 & OP_15=0x0 & + TOK_14_11_Wreg & OP_10_8=0x0 & OP_7_4=0x0 & TOK_3_0_Wreg { + + dividend:4 = (sext(TOK_14_11_Wreg) << 16); + local tmp0:4 = dividend s/ sext(TOK_3_0_Wreg); + W0 = tmp0:2; + local tmp1 = dividend s% sext(TOK_3_0_Wreg); + W1 = tmp1:2; + + testSRL_N ( W1 ); + + # overflow as defined in note 1 + SRL_OV = (TOK_14_11_Wreg s>= TOK_3_0_Wreg); + + testSRL_Z ( W1 ); + + # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis + SRL_C = 0; +} + +:divf TOK_14_11_Wreg,TOK_3_0_Wreg is + OP_23_20=0xD & OP_19_16=0x9 & OP_15=0x0 & + TOK_14_11_Wreg & OP_10_8=0x0 & OP_7_4=0x0 & TOK_3_0_Wreg { + + # Note: this implementation is not iterative, like the actual op. + # Rather, it will decompile accurately and emulate correctly using the Sleigh divide support. + local dividend:4 = (sext(TOK_14_11_Wreg) << 16); + local tmp0:4 = pic30_div(dividend,TOK_3_0_Wreg); + W0 = tmp0:2; + local tmp1:4 = pic30_rem(dividend,TOK_3_0_Wreg); + W1 = tmp1:2; + + testSRL_N ( W1 ); + + # overflow as defined in note 1 + SRL_OV = (TOK_14_11_Wreg s>= TOK_3_0_Wreg); + + testSRL_Z ( W1 ); + + # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis + SRL_C = 0; +} +@endif + + +@if defined(dsPIC33C) +define pcodeop pic30_fdiv; +define pcodeop pic30_frem; + +:divf2 TOK_14_11_Wreg,TOK_3_0_Wreg is + OP_23_20=0xD & OP_19_16=0x9 & OP_15=0x0 & + TOK_14_11_Wreg & OP_10_8=0x0 & OP_7_4=0x2 & TOK_3_0_Wreg & TOK_14_11_Wregn { + + # Note: this implementation is not iterative, like the actual op. + # Rather, it will decompile accurately and emulate correctly using the Sleigh divide support. + local dividend:4 = (sext(TOK_14_11_Wreg) << 16); + local tmp0:4 = pic30_fdiv(dividend,TOK_3_0_Wreg,TOK_14_11_Wregn); + local tmp1:4 = pic30_frem(dividend,TOK_3_0_Wreg,TOK_14_11_Wregn); + TOK_14_11_Wregn = tmp0:2; + TOK_14_11_Wreg = tmp1:2; + + testSRL_N ( TOK_14_11_Wreg ); + + # overflow as defined in note 1 + SRL_OV = (TOK_14_11_Wreg s>= TOK_3_0_Wreg); + + testSRL_Z ( TOK_14_11_Wreg ); + + # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis + SRL_C = 0; +} + +define pcodeop pic30_div2; +define pcodeop pic30_rem2; +:div2.sw TOK_10_7_Wreg,TOK_3_0_Wreg is + OP_23_20=0xD & OP_19_16=0x8 & OP_15=0x0 & TOK_10_7_Wreg & TOK_10_7_Wregp & TOK_W=0 & OP_5_4=0x2 & TOK_3_0_Wreg { + local div:2 = pic30_div(TOK_10_7_Wreg,TOK_3_0_Wreg); + local rem:2 = pic30_rem(TOK_10_7_Wreg,TOK_3_0_Wreg); + + TOK_10_7_Wreg = div; + TOK_10_7_Wregp = rem; + + testSRL_N ( TOK_10_7_Wregp ); + # overflow as defined in note 2 + SRL_OV = (TOK_10_7_Wreg == 0x8000) && (TOK_3_0_Wreg == 0xFFFF); + testSRL_Z ( TOK_10_7_Wregp ); + + # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis + SRL_C = 0; +} + +:div2.sd TOK_10_8_Dregn,TOK_3_0_Wreg is + OP_23_20=0xD & OP_19_16=0x8 & OP_15=0x0 & + TOK_10_8_Dreg & TOK_10_8_Dregn & OP_7=0 & TOK_W=1 & OP_5_4=0x2 & TOK_3_0_Wreg { + + # overflow as defined in note 2 + SRL_OV = isDivideOverflow(TOK_10_8_Dreg, TOK_3_0_Wreg); + + local div:2 = pic30_div2(TOK_10_8_Dreg,TOK_3_0_Wreg); + local rem:2 = pic30_rem2(TOK_10_8_Dreg,TOK_3_0_Wreg); + + TOK_10_8_Dreg = (zext(rem) << 16) + zext(div); + + testSRL_N ( rem ); + testSRL_Z ( rem ); + + # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis + SRL_C = 0; +} + + +:div2.uw TOK_10_7_Wreg,TOK_3_0_Wreg is + OP_23_20=0xD & OP_19_16=0x8 & OP_15=0x1 & TOK_10_7_Wreg & TOK_10_7_Wregp & TOK_W=0 & OP_5_4=0x2 & TOK_3_0_Wreg { + local div:2 = pic30_div(TOK_10_7_Wreg,TOK_3_0_Wreg); + local rem:2 = pic30_rem(TOK_10_7_Wreg,TOK_3_0_Wreg); + + TOK_10_7_Wreg = div; + TOK_10_7_Wregp = rem; + + testSRL_N ( TOK_10_7_Wregp ); + # overflow as defined in note 2 + SRL_OV = 0; + testSRL_Z ( TOK_10_7_Wregp ); + + # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis + SRL_C = 0; +} + +:div2.ud TOK_10_8_Dregn,TOK_3_0_Wreg is + OP_23_20=0xD & OP_19_16=0x8 & OP_15=0x1 & + TOK_10_8_Dreg & TOK_10_8_Dregn & OP_7=0 & TOK_W=1 & OP_5_4=0x2 & TOK_3_0_Wreg { + + # overflow as defined in note 2 + SRL_OV = isDivideOverflow(TOK_10_8_Dreg, TOK_3_0_Wreg); + + local div:2 = pic30_div2(TOK_10_8_Dreg,TOK_3_0_Wreg); + local rem:2 = pic30_rem2(TOK_10_8_Dreg,TOK_3_0_Wreg); + + TOK_10_8_Dreg = (zext(rem) << 16) + zext(div); + + testSRL_N ( rem ); + testSRL_Z ( rem ); + + # Carry is modified, but modification is not defined, just assign to 0 for data flow analysis + SRL_C = 0; +} +@endif + + +@if defined(dsPIC30F) || defined(dsPIC33F) +:do k14_t,n16_t is OP_23_20=0x0 & OP_19_16=0x8 & OP_15_14=0x0 & k14_t ; + OP_23_20=0x0 & OP_19_16=0x0 & n16_t & WordInstNext + [ blockEnd=1; globalset(n16_t,blockEnd);] +{ + DCOUNT_SHADOW = DCOUNT; + DCOUNT = k14_t + 1; + DOEND_SHADOW = DOEND; + DOEND = &n16_t; + DOSTART_SHADOW = DOSTART; + DOSTART = WordInstNext; +} +@endif + + +@if defined(dsPIC33E) || defined(dsPIC33C) +:do k15_t,n16_t is OP_23_20=0x0 & OP_19_16=0x8 & OP_15=0x0 & k15_t ; + OP_23_20=0x0 & OP_19_16=0x0 & n16_t & WordInstNext + [ blockEnd=1; globalset(n16_t,blockEnd); ] +{ + # stack 4 levels deep but we don't enforce this + DL:2 = zext(CORCON_DL); + *[register]:2 (&:2 DCOUNT + DL*2) = k15_t + 1; + *[register]:3 (&:2 DOEND + DL*2) = &n16_t; + *[register]:3 (&:2 DOSTART + DL*2) = WordInstNext; + CORCON_DL = CORCON_DL + 1; +} +@endif + + +@if defined(dsPIC30F) || defined(dsPIC33F) +:do Wns_t,n16_t is OP_23_20=0x0 & OP_19_16=0x8 & OP_15_12=0x8 & OP_11_8=0x0 & OP_7_4=0x0 & Wns_t ; + OP_23_20=0x0 & OP_19_16=0x0 & n16_t & WordInstNext + [ blockEnd=1; globalset(n16_t,blockEnd); ] +{ + DCOUNT_SHADOW = DCOUNT; + DCOUNT = Wns_t + 1; + DOEND_SHADOW = DOEND; + DOEND = &n16_t; + DOSTART_SHADOW = DOSTART; + DOSTART = WordInstNext; +} +@endif + + +@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C) +:ed WmWm_t,ACCA_t,Wx_t,Wy_t,Wxd_t is + OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCA_t & OP_14=0x1 & + Wxd_t & OP_11_10=0x0 & Wx_t & Wy_t & OP_1_0=0x3 { + +# Note: MAC-class instruction + + # (Wm)*(Wm) -> ACCA + ACCA = WmWm_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx] - [Wy]) -> Wxd + # (Wx) +/- kx -> Wx + # (Wy) +/- ky -> Wy + Wxd_t = Wx_t - Wy_t; +} + + +:ed WmWm_t,ACCB_t,Wx_t,Wy_t,Wxd_t is + OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCB_t & OP_14=0x1 & + Wxd_t & OP_11_10=0x0 & Wx_t & Wy_t & OP_1_0=0x3 { + +# Note: MAC-class instruction + + # (Wm)*(Wm) -> ACCB + ACCB = WmWm_t; + testSRH_OB(); + testSRH_SB(); + + # ([Wx] - [Wy]) -> Wxd + # (Wx) +/- kx -> Wx + # (Wy) +/- ky -> Wy + Wxd_t = Wx_t - Wy_t; +} +@endif + + +@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C) +:edac WmWm_t,ACCA_t,Wx_t,Wy_t,Wxd_t is + OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCA_t & OP_14=0x1 & + Wxd_t & OP_11_10=0x0 & Wx_t & Wy_t & OP_1_0=0x2 { + +# Note: MAC-class instruction + + # ACCA + (Wm)*(Wm) -> ACCA + ACCA = ACCA + WmWm_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx] - [Wy]) -> Wxd + # (Wx) +/- kx -> Wx + # (Wy) +/- ky -> Wy + Wxd_t = Wx_t - Wy_t; +} + + +:edac WmWm_t,ACCB_t,Wx_t,Wy_t,Wxd_t is + OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCB_t & OP_14=0x1 & + Wxd_t & OP_11_10=0x0 & Wx_t & Wy_t & OP_1_0=0x2 { + +# Note: MAC-class instruction + + # ACCB + (Wm)*(Wm) -> ACCB + ACCB = ACCB + WmWm_t; + testSRH_OB(); + testSRH_SB(); + + # ([Wx] - [Wy]) -> Wxd + # (Wx) +/- kx -> Wx + # (Wy) +/- ky -> Wy + Wxd_t = Wx_t - Wy_t; +} +@endif + + +:exch Wns_t,Wnd_t is + OP_23_20=0xF & OP_19_16=0xD & OP_15_12=0x0 & OP_11=0x0 & Wnd_t & OP_6_4=0x0 & Wns_t { + + tmp:2 = Wnd_t; + Wnd_t = Wns_t; + Wns_t = tmp; +} + + +# OP_23_20=0x0 & OP_19_16=0x0 & OP_15_12=0x0 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 { +:fbcl Ws_t,Wnd_t is OP_23_20=0xD & OP_19_16=0xF & OP_15_12=0x0 & OP_11=0x0 & Wnd_t & $(WSconstraint) & Ws_t { + + local src = Ws_t; + + sign:2 = src & 0x8000; + temp:2 = src << 1; + shift:2 = 0; + + + if !( (shift < 15) && ((temp & 0x8000) == sign) ) goto ; + temp = temp << 1; + shift = shift + 1; + goto ; + + + + SRL_C = (shift == 15); + Wnd_t = -shift; +} + +# TODO: locate encoding details for FEX instruction +# :fex + +:ff1l Ws_t,Wnd_t is OP_23_20=0xC & OP_19_16=0xF & OP_15_12=0x8 & OP_11=0x0 & Wnd_t & $(WSconstraint) & Ws_t { + + temp:2 = Ws_t; + shift:2 = 1; + + + if !( (shift < 17) && ((temp & 0x8000) == 0) ) goto ; + temp = temp << 1; + shift = shift + 1; + goto ; + + + + # If (Shift == Max_Shift) + # C = 1 + # 0 (Wnd) + # Else + # C = 0 + # Shift (Wnd) + # + SRL_C = (shift == 17); + Wnd_t = shift * zext(!SRL_C); +} + + +:ff1r Ws_t,Wnd_t is OP_23_20=0xC & OP_19_16=0xF & OP_15_12=0x0 & OP_11=0x0 & Wnd_t & $(WSconstraint) & Ws_t { + + temp:2 = Ws_t; + shift:2 = 1; + + + if !( (shift < 17) && ((temp & 0x0001) == 0) ) goto ; + temp = temp >> 1; + shift = shift + 1; + goto ; + + + + # If (Shift == Max_Shift) + # C = 1 + # 0 (Wnd) + # Else + # C = 0 + # Shift (Wnd) + # + SRL_C = (shift == 17); + Wnd_t = shift * zext(!SRL_C); +} + + +@if defined(dsPIC33C) +define pcodeop force_data_range; + +:flim Wbds_t, Ws_t is OP_23_16=0xE4 & OP_15=0x0 & OP_10_7=0x0 & Wbds_t & Ws_t { + force_data_range(Ws_t, Wbds_t); +} + +:flim.v Wbds_t, Ws_t, Wnd_t is OP_23_16=0xE5 & OP_15=1 & Wnd_t & Wbds_t & Ws_t{ + Wnd_t = force_data_range(Ws_t, Wbds_t); +} +@endif + + +:goto dest24_t is ( OP_23_20=0x0 & OP_19_16=0x4 & OP_0=0x0 ; + OP_23_20=0x0 & OP_19_16=0x0 & OP_15_12=0x0 & OP_11_8=0x0 & OP_7=0x0 ) & dest24_t { + + goto dest24_t; +} + + +@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) +:goto WnDest_t is OP_23_20=0x0 & OP_19_16=0x1 & OP_15_12=0x4 & OP_11_8=0x0 & OP_7_4=0x0 & WnDest_t { + + goto [WnDest_t]; +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:goto WnDest_t is OP_23_20=0x0 & OP_19_16=0x1 & OP_15_12=0x0 & OP_11_8=0x4 & OP_7_4=0x0 & WnDest_t { + + goto [WnDest_t]; +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:goto.l WnWn1_t is OP_23_20=0x0 & OP_19_16=0x1 & OP_15=0x1 & WnWn1_t & OP_10_8=0x4 & OP_7_4=0x0 { + + goto [WnWn1_t]; +} +@endif + + +:inc.w f13_t^WREG_t is OP_23_20=0xE & OP_19_16=0xC & OP_15=0 & WREG_t & f13_t { + + local src = f13_t; + local one:2 = 1; + addflags( src, one ); + + WREG_t = src + one; + + testSRL_N ( WREG_t ); + testSRL_Z ( WREG_t ); + testSRH_DCword( WREG_t ); +} + + +:inc.b f13byte_t^WREGbyte_t is OP_23_20=0xE & OP_19_16=0xC & OP_15=0 & WREGbyte_t & f13byte_t { + + local src = f13byte_t; + local one:1 = 1; + addflags( src, one ); + + WREGbyte_t = src + one; + + testSRL_N ( WREGbyte_t ); + testSRL_Z ( WREGbyte_t ); + testSRH_DCbyte( WREGbyte_t ); +} + + +:inc.w Ws_t,Wd_t is OP_23_20=0xE & OP_19_16=0x8 & OP_15=0x0 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t { + + local src = Ws_t; + local one:2 = 1; + addflags( src, one ); + + local result = src + one; + build Wd_t; + Wd_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); + testSRH_DCword( result ); +} + +:inc.b Wsbyte_t,Wdbyte_t is OP_23_20=0xE & OP_19_16=0x8 & OP_15=0x0 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { + + local src = Wsbyte_t; + local one:1 = 1; + addflags( src, one ); + + local result = src + one; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); + testSRH_DCbyte( result ); +} + + +:inc2.w f13_t^WREG_t is OP_23_16=0xEC & OP_15=1 & WREG_t & f13_t { + + local src = f13_t; + local two:2 = 2; + addflags( src, two ); + + WREG_t = src + two; + + testSRL_N ( WREG_t ); + testSRL_Z ( WREG_t ); + testSRH_DCword( WREG_t ); +} + + +:inc2.b f13byte_t^WREGbyte_t is OP_23_16=0xEC & OP_15=1 & WREGbyte_t & f13byte_t { + + local src = f13byte_t; + local two:1 = 2; + addflags( src, two ); + + WREGbyte_t = src + two; + + testSRL_N ( WREGbyte_t ); + testSRL_Z ( WREGbyte_t ); + testSRH_DCbyte( WREGbyte_t ); +} + + +:inc2.w Ws_t,Wd_t is OP_23_16=0xE8 & OP_15=0x1 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t { + + local src = Ws_t; + local two:2 = 2; + addflags( src, two ); + + local result = src + two; + build Wd_t; + Wd_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); + testSRH_DCword( result ); +} + +:inc2.b Wsbyte_t,Wdbyte_t is OP_23_16=0xE8 & OP_15=0x1 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { + + local src = Wsbyte_t; + local two:1 = 2; + addflags( src, two ); + + local result = src + two; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); + testSRH_DCbyte( result ); +} + + +:ior.w f13_t^WREG_t is OP_23_20=0xB & OP_19_16=0x7 & OP_15=0 & WREG_t & f13_t { + + WREG_t = f13_t | W0; + + testSRL_N ( WREG_t ); + testSRL_Z ( WREG_t ); +} + + +:ior.b f13byte_t^WREGbyte_t is OP_23_20=0xB & OP_19_16=0x7 & OP_15=0 & WREGbyte_t & f13byte_t { + + WREGbyte_t = f13byte_t | W0byte; + + testSRL_N ( WREGbyte_t ); + testSRL_Z ( WREGbyte_t ); +} + + +:ior.w k10_t,Wn_t is OP_23_20=0xB & OP_19_16=0x3 & OP_15=0 & k10_t & Wn_t { + + Wn_t = k10_t | Wn_t; + + testSRL_N ( Wn_t ); + testSRL_Z ( Wn_t ); +} + + +:ior.b k10byte_t,Wnbyte_t is OP_23_20=0xB & OP_19_16=0x3 & OP_15=0 & k10byte_t & Wnbyte_t { + + Wnbyte_t = k10byte_t | Wnbyte_t; + + testSRL_N ( Wnbyte_t ); + testSRL_Z ( Wnbyte_t ); +} + + +:ior.w Wb_t,k5_t,Wd_t is OP_23_20=0x7 & OP_19=0x0 & OP_6_5=0x3 & Wb_t & $(WDconstraint) & Wd_t & k5_t { + + local result = k5_t | Wb_t; + build Wd_t; + Wd_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); +} + + +:ior.b Wbbyte_t,k5byte_t,Wdbyte_t is + OP_23_20=0x7 & OP_19=0x0 & OP_6_5=0x3 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & k5byte_t { + + local result = k5byte_t | Wbbyte_t; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); +} + + +:ior.w Wb_t,Ws_t,Wd_t is OP_23_20=0x7 & OP_19=0x0 & TOK_B=0 & Wb_t & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t { + + local result = Wb_t | Ws_t; + build Wd_t; + Wd_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); +} + +:ior.b Wbbyte_t,Wsbyte_t,Wdbyte_t is OP_23_20=0x7 & OP_19=0x0 & TOK_B=1 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { + + local result = Wbbyte_t | Wsbyte_t; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); +} + + +@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C) +:lac WsWRO_t^r4_t,ACCA_t is OP_23_20=0xC & OP_19_16=0xA & ACCA_t & r4_t & WsWRO_t { + + ACCA = (sext(WsWRO_t) << (16 - r4_t)); + testSRH_OA(); + testSRH_SA(); +} + +:lac WsWRO_t^r4_t,ACCB_t is OP_23_20=0xC & OP_19_16=0xA & ACCB_t & r4_t & WsWRO_t { + + ACCB = (sext(WsWRO_t) << (16 - r4_t)); + testSRH_OB(); + testSRH_SB(); +} +@endif + + +@if defined(dsPIC33C) +:lac.d Wsd_t^r4_t,ACCA_t is OP_23_16=0xDB & OP_14_11=0x0 & ACCA_t & r4_t & Wsd_t { + + ACCA = (sext(Wsd_t) << (16 - r4_t)); + testSRH_OA(); + testSRH_SA(); +} + +:lac.d Wsd_t^r4_t,ACCB_t is OP_23_16=0xDB & OP_14_11=0x0 & ACCB_t & r4_t & Wsd_t { + + ACCB = (sext(Wsd_t) << (16 - r4_t)); + testSRH_OB(); + testSRH_SB(); +} +@endif + + +@if defined(dsPIC33C) +PSV_t: Ws_t is Ws_t { + local psv_addr = (Ws_t & 0xf7 ) + (DSRPAG & 0xff) << 0xf; + export *[rom]:3 psv_addr; +} + +EDS_t: Wdpp_t is Wdpp_t { + local eds_addr = (Wdpp_t & 0xf7 ) + (DSWPAG & 0xff) << 0xf; + export *[rom]:2 eds_addr; +} + +define pcodeop loadslave; +:ldslv PSV_t, EDS_t, k13_12_t is OP_23_16=0x03 & OP_15_14=0x0 & OP_11=0 & k13_12_t & EDS_t & PSV_t { + EDS_t = loadslave(PSV_t, k13_12_t); +} +@endif + + +@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) +:lnk k14_t is OP_23_20=0xF & OP_19_16=0xA & OP_15_14=0x0 & k14_t & OP_0=0x0 { + + *[ram]:2 W15 = W14; + W15 = W15 + 2; + + W14 = W15; + W15 = W15 + k14_t; +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:lnk k14_t is OP_23_20=0xF & OP_19_16=0xA & OP_15_14=0x0 & k14_t & OP_0=0x0 { + + *[ram]:2 W15 = W14; + W15 = W15 + 2; + + W14 = W15; + CORCON_SFA = 1; + W15 = W15 + k14_t; +} +@endif + + +:lsr.w f13_t^WREG_t is OP_23_20=0xD & OP_19_16=0x5 & OP_15=0 & WREG_t & f13_t { + + local src = f13_t; + SRL_C = ( src & 0x0001 ) != 0; + + WREG_t = src >> 1; + + testSRL_N ( WREG_t ); + testSRL_Z ( WREG_t ); +} + + +:lsr.b f13byte_t^WREGbyte_t is OP_23_20=0xD & OP_19_16=0x5 & OP_15=0 & WREGbyte_t & f13byte_t { + + local src = f13byte_t; + SRL_C = ( src & 0x01 ) != 0; + + WREGbyte_t = src >> 1; + + testSRL_N ( WREGbyte_t ); + testSRL_Z ( WREGbyte_t ); +} + + +:lsr.w Ws_t,Wd_t is OP_23_20=0xD & OP_19_16=0x1 & OP_15=0x0 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t { + + local src = Ws_t; + SRL_C = ( src & 0x0001 ) != 0; + + local result = src >> 1; + build Wd_t; + Wd_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); +} + +:lsr.b Wsbyte_t,Wdbyte_t is OP_23_20=0xD & OP_19_16=0x1 & OP_15=0x0 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { + + local src = Wsbyte_t; + SRL_C = ( src & 0x01 ) != 0; + + local result = src >> 1; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N ( Wdbyte_t ); + testSRL_Z ( Wdbyte_t ); +} + + +:lsr.w Wbd_t,k4_t,Wnd_t is OP_23_20=0xD & OP_19_16=0xE & OP_15=0x0 & OP_6_4=0x4 & Wbd_t & Wnd_t & k4_t { + + Wnd_t = Wbd_t >> k4_t; + + testSRL_N ( Wnd_t ); + testSRL_Z ( Wnd_t ); +} + + +:lsr.w Wbd_t,Wns_t,Wnd_t is OP_23_20=0xD & OP_19_16=0xE & OP_15=0x0 & OP_6_4=0x0 & Wbd_t & Wnd_t & Wns_t { + + Wnd_t = Wbd_t >> ( Wns_t & 0x001F ); + + testSRL_N ( Wnd_t ); + testSRL_Z ( Wnd_t ); +} + + +@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C) +## +## +## ACCA series +## +## + +:mac WmWn_t,ACCA_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x0 & + TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCA + (Wm)*(Wn) -> ACCA + ACCA = ACCA + WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCB rounded -> AWB +# AWB_t = ACCBH; +} + + +:mac WmWn_t,ACCA_t^AWB_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x0 & + TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCA + (Wm)*(Wn) -> ACCA + ACCA = ACCA + WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCB rounded -> AWB + AWB_t = ACCBH; +} + + +:mac WmWn_t,ACCA_t^Wy_t^Wyd_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x0 & + TOK_9_6_iiii=0x4 & TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCA + (Wm)*(Wn) -> ACCA + ACCA = ACCA + WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCB rounded -> AWB +# AWB_t = ACCBH; +} + + +:mac WmWn_t,ACCA_t^Wy_t^Wyd_t^AWB_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x0 & + TOK_9_6_iiii=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCA + (Wm)*(Wn) -> ACCA + ACCA = ACCA + WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCB rounded -> AWB + AWB_t = ACCBH; +} + + +:mac WmWn_t,ACCA_t^Wx_t^Wxd_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x0 & + TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCA + (Wm)*(Wn) -> ACCA + ACCA = ACCA + WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCB rounded -> AWB +# AWB_t = ACCBH; +} + + +:mac WmWn_t,ACCA_t^Wx_t^Wxd_t^AWB_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x0 & + TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCA + (Wm)*(Wn) -> ACCA + ACCA = ACCA + WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCB rounded -> AWB + AWB_t = ACCBH; +} + + +:mac WmWn_t,ACCA_t^Wx_t^Wxd_t^Wy_t^Wyd_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x0 & + TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCA + (Wm)*(Wn) -> ACCA + ACCA = ACCA + WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCB rounded -> AWB +# AWB_t = ACCBH; +} + + +:mac WmWn_t,ACCA_t^Wx_t^Wxd_t^Wy_t^Wyd_t^AWB_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x0 & + + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCA + (Wm)*(Wn) -> ACCA + ACCA = ACCA + WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCB rounded -> AWB + AWB_t = ACCBH; +} + + +## +## +## ACCB series +## +## + +:mac WmWn_t,ACCB_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x0 & + TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCB + (Wm)*(Wn) -> ACCB + ACCB = ACCB + WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCA rounded -> AWB +# AWB_t = ACCAH; +} + + +:mac WmWn_t,ACCB_t^AWB_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x0 & + TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCB + (Wm)*(Wn) -> ACCB + ACCB = ACCB + WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCA rounded -> AWB + AWB_t = ACCAH; +} + + +:mac WmWn_t,ACCB_t^Wy_t^Wyd_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x0 & + TOK_9_6_iiii=0x4 & TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCB + (Wm)*(Wn) -> ACCB + ACCB = ACCB + WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCA rounded -> AWB +# AWB_t = ACCAH; +} + + +:mac WmWn_t,ACCB_t^Wy_t^Wyd_t^AWB_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x0 & + TOK_9_6_iiii=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCB + (Wm)*(Wn) -> ACCB + ACCB = ACCB + WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCA rounded -> AWB + AWB_t = ACCAH; +} + + +:mac WmWn_t,ACCB_t^Wx_t^Wxd_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x0 & + TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCB + (Wm)*(Wn) -> ACCB + ACCB = ACCB + WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCA rounded -> AWB +# AWB_t = ACCAH; +} + + +:mac WmWn_t,ACCB_t^Wx_t^Wxd_t^AWB_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x0 & + TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCB + (Wm)*(Wn) -> ACCB + ACCB = ACCB + WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCA rounded -> AWB + AWB_t = ACCAH; +} + + +:mac WmWn_t,ACCB_t^Wx_t^Wxd_t^Wy_t^Wyd_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x0 & + TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCB + (Wm)*(Wn) -> ACCB + ACCB = ACCB + WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCA rounded -> AWB +# AWB_t = ACCAH; +} + + +:mac WmWn_t,ACCB_t^Wx_t^Wxd_t^Wy_t^Wyd_t^AWB_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x0 & + + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCB + (Wm)*(Wn) -> ACCB + ACCB = ACCB + WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCA rounded -> AWB + AWB_t = ACCAH; +} +@endif + + +@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C) +## +## +## ACCA series +## +## + +:mac WmWm_t,ACCA_t is + OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCA_t & OP_14=0x0 & OP_1_0=0x0 & + TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # ACCA + (Wm)*(Wm) -> ACCA + ACCA = ACCA + WmWm_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; +} + + +:mac WmWm_t,ACCA_t^Wy_t^Wyd_t is + OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCA_t & OP_14=0x0 & OP_1_0=0x0 & + TOK_9_6_iiii=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # ACCA + (Wm)*(Wm) -> ACCA + ACCA = ACCA + WmWm_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; +} + + +:mac WmWm_t,ACCA_t^Wx_t^Wxd_t is + OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCA_t & OP_14=0x0 & OP_1_0=0x0 & + TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # ACCA + (Wm)*(Wm) -> ACCA + ACCA = ACCA + WmWm_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; +} + + +:mac WmWm_t,ACCA_t^Wx_t^Wxd_t^Wy_t^Wyd_t is + OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCA_t & OP_14=0x0 & OP_1_0=0x0 & + + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # ACCA + (Wm)*(Wm) -> ACCA + ACCA = ACCA + WmWm_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; +} + + +## +## +## ACCB series +## +## + +:mac WmWm_t,ACCB_t is + OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCB_t & OP_14=0x0 & OP_1_0=0x0 & + TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # ACCB + (Wm)*(Wm) -> ACCB + ACCB = ACCB + WmWm_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; +} + + +:mac WmWm_t,ACCB_t^Wy_t^Wyd_t is + OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCB_t & OP_14=0x0 & OP_1_0=0x0 & + TOK_9_6_iiii=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # ACCB + (Wm)*(Wm) -> ACCB + ACCB = ACCB + WmWm_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; +} + + +:mac WmWm_t,ACCB_t^Wx_t^Wxd_t is + OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCB_t & OP_14=0x0 & OP_1_0=0x0 & + TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # ACCB + (Wm)*(Wm) -> ACCB + ACCB = ACCB + WmWm_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; +} + + +:mac WmWm_t,ACCB_t^Wx_t^Wxd_t^Wy_t^Wyd_t is + OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCB_t & OP_14=0x0 & OP_1_0=0x0 & + + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # ACCB + (Wm)*(Wm) -> ACCB + ACCB = ACCB + WmWm_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; +} +@endif + + +@if defined(dsPIC33C) + +:max ACCA_t is OP_23_16=0xCE & ACCA_t & OP_14_0=0x1000 { + local val = ACCA_t - ACCB; + ACCA_t = (ACCA)*zext(val s<= 0) + (ACCB)*zext(val s> 0); + SRL_Z = zext(val s<= 0); + SRL_N = 0; + SRL_OV = 0; +} + +:max ACCB_t is OP_23_16=0xCE & ACCB_t & OP_14_0=0x1000 { + local val = ACCB_t - ACCA; + ACCB_t = (ACCB)*zext(val s<= 0) + (ACCA)*zext(val s> 0); + SRL_Z = zext(val s<= 0); + SRL_N = 0; + SRL_OV = 0; +} + + +:max.v ACCA_t, Ws_t is OP_23_16=0xCE & ACCA_t & OP_14_7=0x30 & Ws_t { + local val = ACCA_t - ACCB; + ACCA_t = (ACCA)*zext(val s<= 0) + (ACCB)*zext(val s> 0); + Ws_t = (val:2)*zext(val s> 0); + SRL_Z = zext(val s<= 0); + SRL_N = 0; + SRL_OV = 0; +} + +:max.v ACCB_t, Ws_t is OP_23_16=0xCE & ACCB_t & OP_14_7=0x30 & Ws_t { + local val = ACCB_t - ACCA; + ACCB_t = (ACCB)*zext(val s<= 0) + (ACCA)*zext(val s> 0); + Ws_t = (val:2)*zext(val s> 0); + SRL_Z = zext(val s<= 0); + SRL_N = 0; + SRL_OV = 0; +} + + +:min ACCA_t is OP_23_16=0xCE & ACCA_t & OP_14_0=0x3000 { + local val = ACCA_t - ACCB; + ACCA_t = (ACCA)*zext(val s>= 0) + (ACCB)*zext(val s< 0); + SRL_Z = zext(val s>= 0); + SRL_N = zext(val s< 0); + SRL_OV = 0; +} + +:min ACCB_t is OP_23_16=0xCE & ACCB_t & OP_14_0=0x3000 { + local val = ACCB_t - ACCA; + ACCB_t = (ACCB)*zext(val s>= 0) + (ACCA)*zext(val s< 0); + SRL_Z = zext(val s>= 0); + SRL_N = zext(val s< 0); + SRL_OV = 0; +} + +:min.v ACCA_t, Ws_t is OP_23_16=0xCE & ACCA_t & OP_14_7=0x70 & Ws_t { + local val = ACCA_t - ACCB; + ACCA_t = (ACCA)*zext(val s>= 0) + (ACCB)*zext(val s< 0); + Ws_t = (val:2)*zext(val s< 0); + SRL_Z = zext(val s>= 0); + SRL_N = zext(val s< 0); + SRL_OV = 0; +} + +:min.v ACCB_t, Ws_t is OP_23_16=0xCE & ACCB_t & OP_14_7=0x70 & Ws_t { + local val = ACCB_t - ACCA; + ACCB_t = (ACCB)*zext(val s>= 0) + (ACCA)*zext(val s< 0); + Ws_t = (val:2)*zext(val s< 0); + SRL_Z = zext(val s>= 0); + SRL_N = zext(val s< 0); + SRL_OV = 0; +} + + +:minz ACCA_t is OP_23_16=0xCE & ACCA_t & OP_14_0=0x3400 { + if (SRL_Z == 0) goto inst_next; + local val = ACCA_t - ACCB; + ACCA_t = (ACCA)*zext(val s>= 0) + (ACCB)*zext(val s< 0); + SRL_Z = zext(val s>= 0); + SRL_N = zext(val s< 0); + SRL_OV = 0; +} + +:minz ACCB_t is OP_23_16=0xCE & ACCB_t & OP_14_0=0x3400 { + if (SRL_Z == 0) goto inst_next; + local val = ACCB_t - ACCA; + ACCB_t = (ACCB)*zext(val s>= 0) + (ACCA)*zext(val s< 0); + SRL_Z = zext(val s>= 0); + SRL_N = zext(val s< 0); + SRL_OV = 0; +} + +:minz.v ACCA_t, Ws_t is OP_23_16=0xCE & ACCA_t & OP_14_7=0x78 & Ws_t { + if (SRL_Z == 0) goto inst_next; + local val = ACCA_t - ACCB; + ACCA_t = (ACCA)*zext(val s>= 0) + (ACCB)*zext(val s< 0); + Ws_t = (val:2)*zext(val s< 0); + SRL_Z = zext(val s>= 0); + SRL_N = zext(val s< 0); + SRL_OV = 0; +} + +:minz.v ACCB_t, Ws_t is OP_23_16=0xCE & ACCB_t & OP_14_7=0x78 & Ws_t { + if (SRL_Z == 0) goto inst_next; + local val = ACCB_t - ACCA; + ACCB_t = (ACCB)*zext(val s>= 0) + (ACCA)*zext(val s< 0); + Ws_t = (val:2)*zext(val s< 0); + SRL_Z = zext(val s>= 0); + SRL_N = zext(val s< 0); + SRL_OV = 0; +} +@endif + + +:mov.w f13_t^WREG_t is OP_23_20=0xB & OP_19_16=0xF & OP_15=1 & WREG_t & f13_t { + + WREG_t = f13_t; + + testSRL_N ( WREG_t ); + testSRL_Z ( WREG_t ); +} + + +:mov.b f13byte_t^WREGbyte_t is OP_23_20=0xB & OP_19_16=0xF & OP_15=1 & WREGbyte_t & f13byte_t { + + WREGbyte_t = f13byte_t; + + testSRL_N ( WREGbyte_t ); + testSRL_Z ( WREGbyte_t ); +} + + +:mov.w WREG_W0_t,f13_t is OP_23_20=0xB & OP_19_16=0x7 & OP_15=1 & WREG_W0_t & OP_13=1 & f13_t { + + f13_t = WREG_W0_t; +} + + +:mov.b WREG_W0byte_t,f13byte_t is OP_23_20=0xB & OP_19_16=0x7 & OP_15=1 & WREG_W0byte_t & OP_13=1 & f13byte_t { + + f13byte_t = WREG_W0byte_t; +} + + +:mov.w f15b_t,Wndb_t is OP_23_20=0x8 & OP_19=0x0 & f15b_t & Wndb_t { + + Wndb_t = f15b_t; +} + + +:mov.w Wns_t,f15b_t is OP_23_20=0x8 & OP_19=0x1 & f15b_t & Wns_t { + + f15b_t = Wns_t; +} + + +:mov.b TOK_k8c,Wndbyte_t is OP_23_20=0xB & OP_19_16=0x3 & OP_15_12=0xC & TOK_k8c & Wndbyte_t { + + Wndbyte_t = TOK_k8c; +} + + +:mov.w k16_t,Wndb_t is OP_23_20=0x2 & k16_t & Wndb_t { + + Wndb_t = k16_t; +} + + +:mov.w WsSlit10_t,Wnda_t is OP_23_20=0x9 & OP_19=0 & TOK_B=0 & WsSlit10_t & Wnda_t { + + Wnda_t = WsSlit10_t; +} + +:mov.b WsSlit10byte_t,Wndabyte_t is OP_23_20=0x9 & OP_19=0 & TOK_B=1 & WsSlit10byte_t & Wndabyte_t { + + Wndabyte_t = WsSlit10byte_t; +} + + +:mov.w Wn_t,WdSlit10_t is OP_23_20=0x9 & OP_19=1 & TOK_B=0 & WdSlit10_t & Wn_t { + + WdSlit10_t = Wn_t; +} + +:mov.b Wnbyte_t,WdSlit10byte_t is OP_23_20=0x9 & OP_19=1 & TOK_B=1 & WdSlit10byte_t & Wnbyte_t { + + WdSlit10byte_t = Wnbyte_t; +} + + +:mov.w movWs,movWd is OP_23_20=0x7 & OP_19=1 & TOK_B=0 & movWd & movWs { + + local result = movWs; + build movWd; + movWd = result; +} + + +:mov.b movWsbyte,movWdbyte is OP_23_20=0x7 & OP_19=1 & TOK_B=1 & movWdbyte & movWsbyte { + + local result = movWsbyte; + build movWdbyte; + movWdbyte = result; +} + + +:mov.d Wsd_t,Wndd_t is + OP_23_20=0xB & OP_19_16=0xE & OP_15_12=0x0 & OP_11=0x0 & Wndd_t & OP_7=0x0 & $(WSconstraint) & Wsd_t { + + Wndd_t = Wsd_t; +} + + +:mov.d TOK_3_1_Dregn,Wdd_t is + OP_23_20=0xb & OP_19_16=0xe & OP_15_14=0x2 & OP_6_4=0x0 & TOK_3_1_Dreg & TOK_3_1_Dregn & OP_0=0 & $(WDconstraint) & Wdd_t { + + local result = TOK_3_1_Dreg; + build Wdd_t; + Wdd_t = result; +} + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +TOK_9_0_U_t: is TOK_9_0_U { export *[const]:2 TOK_9_0_U; } + +:movpag TOK_9_0_U_t,DSRPAG is OP_23_20=0xF & OP_19_16=0xE & OP_15_12=0xC & TOK_11_10_PP=0 & TOK_9_0_U_t & DSRPAG { + DSRPAG = TOK_9_0_U_t; +} + +:movpag TOK_9_0_U_t,DSWPAG is OP_23_20=0xF & OP_19_16=0xE & OP_15_12=0xC & TOK_11_10_PP=1 & TOK_9_0_U_t & DSWPAG { + DSWPAG = TOK_9_0_U_t; +} + +:movpag TOK_9_0_U_t,TBLPAG is OP_23_20=0xF & OP_19_16=0xE & OP_15_12=0xC & TOK_11_10_PP=2 & TOK_9_0_U_t & TBLPAG { + TBLPAG = TOK_9_0_U_t:1; +} + +:movpag TOK_3_0_Wreg,DSRPAG is OP_23_20=0xF & OP_19_16=0xE & OP_15_12=0xD & TOK_11_10_PP=0 & OP_9_4=0x0 & TOK_3_0_Wreg & DSRPAG { + DSRPAG = TOK_3_0_Wreg; +} +:movpag TOK_3_0_Wreg,DSWPAG is OP_23_20=0xF & OP_19_16=0xE & OP_15_12=0xD & TOK_11_10_PP=1 & OP_9_4=0x0 & TOK_3_0_Wreg & DSWPAG { + DSWPAG = TOK_3_0_Wreg; +} +:movpag TOK_3_0_Wreg,TBLPAG is OP_23_20=0xF & OP_19_16=0xE & OP_15_12=0xD & TOK_11_10_PP=2 & OP_9_4=0x0 & TOK_3_0_Wreg & TBLPAG { + TBLPAG = TOK_3_0_Wreg:1; +} +@endif + + +@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C) +## +## +## ACCA series +## +## + +:movsac ACCA_t is + OP_23_20=0xC & OP_19_16=0x7 & ACCA_t & OP_14=0x0 & + TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCB rounded -> AWB +# AWB_t = ACCBH; +} + + +:movsac ACCA_t^AWB_t is + OP_23_20=0xC & OP_19_16=0x7 & ACCA_t & OP_14=0x0 & + TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCB rounded -> AWB + AWB_t = ACCBH; +} + + +:movsac ACCA_t^Wy_t^Wyd_t is + OP_23_20=0xC & OP_19_16=0x7 & ACCA_t & OP_14=0x0 & + TOK_9_6_iiii=0x4 & TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCB rounded -> AWB +# AWB_t = ACCBH; +} + + +:movsac ACCA_t^Wy_t^Wyd_t^AWB_t is + OP_23_20=0xC & OP_19_16=0x7 & ACCA_t & OP_14=0x0 & + TOK_9_6_iiii=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCB rounded -> AWB + AWB_t = ACCBH; +} + + +:movsac ACCA_t^Wx_t^Wxd_t is + OP_23_20=0xC & OP_19_16=0x7 & ACCA_t & OP_14=0x0 & + TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCB rounded -> AWB +# AWB_t = ACCBH; +} + + +:movsac ACCA_t^Wx_t^Wxd_t^AWB_t is + OP_23_20=0xC & OP_19_16=0x7 & ACCA_t & OP_14=0x0 & + TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCB rounded -> AWB + AWB_t = ACCBH; +} + + +:movsac ACCA_t^Wx_t^Wxd_t^Wy_t^Wyd_t is + OP_23_20=0xC & OP_19_16=0x7 & ACCA_t & OP_14=0x0 & + TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCB rounded -> AWB +# AWB_t = ACCBH; +} + + +:movsac ACCA_t^Wx_t^Wxd_t^Wy_t^Wyd_t^AWB_t is + OP_23_20=0xC & OP_19_16=0x7 & ACCA_t & OP_14=0x0 & + + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCB rounded -> AWB + AWB_t = ACCBH; +} + + +## +## +## ACCB series +## +## + +:movsac ACCB_t is + OP_23_20=0xC & OP_19_16=0x7 & ACCB_t & OP_14=0x0 & + TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCA rounded -> AWB +# AWB_t = ACCAH; +} + + +:movsac ACCB_t^AWB_t is + OP_23_20=0xC & OP_19_16=0x7 & ACCB_t & OP_14=0x0 & + TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCA rounded -> AWB + AWB_t = ACCAH; +} + + +:movsac ACCB_t^Wy_t^Wyd_t is + OP_23_20=0xC & OP_19_16=0x7 & ACCB_t & OP_14=0x0 & + TOK_9_6_iiii=0x4 & TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCA rounded -> AWB +# AWB_t = ACCAH; +} + + +:movsac ACCB_t^Wy_t^Wyd_t^AWB_t is + OP_23_20=0xC & OP_19_16=0x7 & ACCB_t & OP_14=0x0 & + TOK_9_6_iiii=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCA rounded -> AWB + AWB_t = ACCAH; +} + + +:movsac ACCB_t^Wx_t^Wxd_t is + OP_23_20=0xC & OP_19_16=0x7 & ACCB_t & OP_14=0x0 & + TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCA rounded -> AWB +# AWB_t = ACCAH; +} + + +:movsac ACCB_t^Wx_t^Wxd_t^AWB_t is + OP_23_20=0xC & OP_19_16=0x7 & ACCB_t & OP_14=0x0 & + TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCA rounded -> AWB + AWB_t = ACCAH; +} + + +:movsac ACCB_t^Wx_t^Wxd_t^Wy_t^Wyd_t is + OP_23_20=0xC & OP_19_16=0x7 & ACCB_t & OP_14=0x0 & + TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCA rounded -> AWB +# AWB_t = ACCAH; +} + + +:movsac ACCB_t^Wx_t^Wxd_t^Wy_t^Wyd_t^AWB_t is + OP_23_20=0xC & OP_19_16=0x7 & ACCB_t & OP_14=0x0 & + + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCA rounded -> AWB + AWB_t = ACCAH; +} +@endif + + +@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C) +:mpy WmWn_t,ACCA_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x0 & OP_1_0=0x3 & + TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # (Wm)*(Wn) -> ACCA + ACCA = WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; +} + + +:mpy WmWn_t,ACCA_t^Wy_t^Wyd_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x0 & OP_1_0=0x3 & + TOK_9_6_iiii=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # (Wm)*(Wn) -> ACCA + ACCA = WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; +} + + +:mpy WmWn_t,ACCA_t^Wx_t^Wxd_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x0 & OP_1_0=0x3 & + TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # (Wm)*(Wn) -> ACCA + ACCA = WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; +} + + +:mpy WmWn_t,ACCA_t^Wx_t^Wxd_t^Wy_t^Wyd_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x0 & OP_1_0=0x3 & + + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # (Wm)*(Wn) -> ACCA + ACCA = WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; +} + + +## +## +## ACCB series +## +## + +:mpy WmWn_t,ACCB_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x0 & OP_1_0=0x3 & + TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # (Wm)*(Wn) -> ACCB + ACCB = WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; +} + + +:mpy WmWn_t,ACCB_t^Wy_t^Wyd_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x0 & OP_1_0=0x3 & + TOK_9_6_iiii=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # (Wm)*(Wn) -> ACCB + ACCB = WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; +} + + +:mpy WmWn_t,ACCB_t^Wx_t^Wxd_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x0 & OP_1_0=0x3 & + TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # (Wm)*(Wn) -> ACCB + ACCB = WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; +} + + +:mpy WmWn_t,ACCB_t^Wx_t^Wxd_t^Wy_t^Wyd_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x0 & OP_1_0=0x3 & + + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # (Wm)*(Wn) -> ACCB + ACCB = WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; +} +@endif + + +@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C) +:mpy WmWm_t,ACCA_t is + OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCA_t & OP_14=0x0 & OP_1_0=0x1 & + TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # (Wm)*(Wm) -> ACCA + ACCA = WmWm_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; +} + + +:mpy WmWm_t,ACCA_t^Wy_t^Wyd_t is + OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCA_t & OP_14=0x0 & OP_1_0=0x1 & + TOK_9_6_iiii=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # (Wm)*(Wm) -> ACCA + ACCA = WmWm_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; +} + + +:mpy WmWm_t,ACCA_t^Wx_t^Wxd_t is + OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCA_t & OP_14=0x0 & OP_1_0=0x1 & + TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # (Wm)*(Wm) -> ACCA + ACCA = WmWm_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; +} + + +:mpy WmWm_t,ACCA_t^Wx_t^Wxd_t^Wy_t^Wyd_t is + OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCA_t & OP_14=0x0 & OP_1_0=0x1 & + + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # (Wm)*(Wm) -> ACCA + ACCA = WmWm_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; +} + + +## +## +## ACCB series +## +## + +:mpy WmWm_t,ACCB_t is + OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCB_t & OP_14=0x0 & OP_1_0=0x1 & + TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # (Wm)*(Wm) -> ACCB + ACCB = WmWm_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; +} + + +:mpy WmWm_t,ACCB_t^Wy_t^Wyd_t is + OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCB_t & OP_14=0x0 & OP_1_0=0x1 & + TOK_9_6_iiii=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # (Wm)*(Wm) -> ACCB + ACCB = WmWm_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; +} + + +:mpy WmWm_t,ACCB_t^Wx_t^Wxd_t is + OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCB_t & OP_14=0x0 & OP_1_0=0x1 & + TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # (Wm)*(Wm) -> ACCB + ACCB = WmWm_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; +} + + +:mpy WmWm_t,ACCB_t^Wx_t^Wxd_t^Wy_t^Wyd_t is + OP_23_20=0xF & OP_19_18=0x0 & WmWm_t & ACCB_t & OP_14=0x0 & OP_1_0=0x1 & + + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # (Wm)*(Wm) -> ACCB + ACCB = WmWm_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; +} +@endif + + +@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C) +:mpy.n WmWn_t,ACCA_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x1 & OP_1_0=0x3 & + TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # -(Wm)*(Wn) -> ACCA + ACCA = -WmWn_t; + testSRH_OA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; +} + + +:mpy.n WmWn_t,ACCA_t^Wy_t^Wyd_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x1 & OP_1_0=0x3 & + TOK_9_6_iiii=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # -(Wm)*(Wn) -> ACCA + ACCA = -WmWn_t; + testSRH_OA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; +} + + +:mpy.n WmWn_t,ACCA_t^Wx_t^Wxd_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x1 & OP_1_0=0x3 & + TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # -(Wm)*(Wn) -> ACCA + ACCA = -WmWn_t; + testSRH_OA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; +} + + +:mpy.n WmWn_t,ACCA_t^Wx_t^Wxd_t^Wy_t^Wyd_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x1 & OP_1_0=0x3 & + + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # -(Wm)*(Wn) -> ACCA + ACCA = -WmWn_t; + testSRH_OA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; +} + + +## +## +## ACCB series +## +## + +:mpy.n WmWn_t,ACCB_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x1 & OP_1_0=0x3 & + TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # -(Wm)*(Wn) -> ACCB + ACCB = -WmWn_t; + testSRH_OA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; +} + + +:mpy.n WmWn_t,ACCB_t^Wy_t^Wyd_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x1 & OP_1_0=0x3 & + TOK_9_6_iiii=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # -(Wm)*(Wn) -> ACCB + ACCB = -WmWn_t; + testSRH_OA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; +} + + +:mpy.n WmWn_t,ACCB_t^Wx_t^Wxd_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x1 & OP_1_0=0x3 & + TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # -(Wm)*(Wn) -> ACCB + ACCB = -WmWn_t; + testSRH_OA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; +} + + +:mpy.n WmWn_t,ACCB_t^Wx_t^Wxd_t^Wy_t^Wyd_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x1 & OP_1_0=0x3 & + + Wxd_t & Wyd_t & Wx_t & Wy_t { + +# Note: MAC-class instruction + + # -(Wm)*(Wn) -> ACCB + ACCB = -WmWn_t; + testSRH_OA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; +} +@endif + + +@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C) +:msc WmWn_t,ACCA_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x1 & + TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCA - (Wm)*(Wn) -> ACCA + ACCA = ACCA - WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCB rounded -> AWB +# AWB_t = ACCBH; +} + + +:msc WmWn_t,ACCA_t^AWB_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x1 & + TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCA - (Wm)*(Wn) -> ACCA + ACCA = ACCA - WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCB rounded -> AWB + AWB_t = ACCBH; +} + + +:msc WmWn_t,ACCA_t^Wy_t^Wyd_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x1 & + TOK_9_6_iiii=0x4 & TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCA - (Wm)*(Wn) -> ACCA + ACCA = ACCA - WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCB rounded -> AWB +# AWB_t = ACCBH; +} + + +:msc WmWn_t,ACCA_t^Wy_t^Wyd_t^AWB_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x1 & + TOK_9_6_iiii=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCA - (Wm)*(Wn) -> ACCA + ACCA = ACCA - WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCB rounded -> AWB + AWB_t = ACCBH; +} + + +:msc WmWn_t,ACCA_t^Wx_t^Wxd_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x1 & + TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCA - (Wm)*(Wn) -> ACCA + ACCA = ACCA - WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCB rounded -> AWB +# AWB_t = ACCBH; +} + + +:msc WmWn_t,ACCA_t^Wx_t^Wxd_t^AWB_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x1 & + TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCA - (Wm)*(Wn) -> ACCA + ACCA = ACCA - WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCB rounded -> AWB + AWB_t = ACCBH; +} + + +:msc WmWn_t,ACCA_t^Wx_t^Wxd_t^Wy_t^Wyd_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x1 & + TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCA - (Wm)*(Wn) -> ACCA + ACCA = ACCA - WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCB rounded -> AWB +# AWB_t = ACCBH; +} + + +:msc WmWn_t,ACCA_t^Wx_t^Wxd_t^Wy_t^Wyd_t^AWB_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCA_t & OP_14=0x1 & + + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCA - (Wm)*(Wn) -> ACCA + ACCA = ACCA - WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCB rounded -> AWB + AWB_t = ACCBH; +} + + +## +## +## ACCB series +## +## + +:msc WmWn_t,ACCB_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x1 & + TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCB - (Wm)*(Wn) -> ACCB + ACCB = ACCB - WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCA rounded -> AWB +# AWB_t = ACCAH; +} + + +:msc WmWn_t,ACCB_t^AWB_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x1 & + TOK_9_6_iiii=0x4 & TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCB - (Wm)*(Wn) -> ACCB + ACCB = ACCB - WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCA rounded -> AWB + AWB_t = ACCAH; +} + + +:msc WmWn_t,ACCB_t^Wy_t^Wyd_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x1 & + TOK_9_6_iiii=0x4 & TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCB - (Wm)*(Wn) -> ACCB + ACCB = ACCB - WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCA rounded -> AWB +# AWB_t = ACCAH; +} + + +:msc WmWn_t,ACCB_t^Wy_t^Wyd_t^AWB_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x1 & + TOK_9_6_iiii=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCB - (Wm)*(Wn) -> ACCB + ACCB = ACCB - WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx +# Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCA rounded -> AWB + AWB_t = ACCAH; +} + + +:msc WmWn_t,ACCB_t^Wx_t^Wxd_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x1 & + TOK_5_2_jjjj=0x4 & TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCB - (Wm)*(Wn) -> ACCB + ACCB = ACCB - WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCA rounded -> AWB +# AWB_t = ACCAH; +} + + +:msc WmWn_t,ACCB_t^Wx_t^Wxd_t^AWB_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x1 & + TOK_5_2_jjjj=0x4 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCB - (Wm)*(Wn) -> ACCB + ACCB = ACCB - WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy +# Wyd_t = Wy_t; + + # ACCA rounded -> AWB + AWB_t = ACCAH; +} + + +:msc WmWn_t,ACCB_t^Wx_t^Wxd_t^Wy_t^Wyd_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x1 & + TOK_1_0_aa=0x2 & + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCB - (Wm)*(Wn) -> ACCB + ACCB = ACCB - WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCA rounded -> AWB +# AWB_t = ACCAH; +} + + +:msc WmWn_t,ACCB_t^Wx_t^Wxd_t^Wy_t^Wyd_t^AWB_t is + OP_23_20=0xC & OP_19=0x0 & WmWn_t & ACCB_t & OP_14=0x1 & + + Wxd_t & Wyd_t & Wx_t & Wy_t & AWB_t { + +# Note: MAC-class instruction + + # ACCB - (Wm)*(Wn) -> ACCB + ACCB = ACCB - WmWn_t; + testSRH_OA(); + testSRH_SA(); + + # ([Wx]) -> Wxd + # (Wx) +/- kx -> Wx + Wxd_t = Wx_t; + + # ([Wy]) -> Wyd + # (Wy) +/- ky -> Wy + Wyd_t = Wy_t; + + # ACCA rounded -> AWB + AWB_t = ACCAH; +} +@endif + + +:mul.w f13_t is OP_23_16=0xbc & OP_15=0 & OP_13=0x0 & OP_14=0 & f13_t { + + W3W2 = zext(f13_t) * zext(W0); +} +:mul.b f13byte_t is OP_23_16=0xbc & OP_15=0 & OP_13=0x0 & OP_14=1 & f13byte_t { + + W2 = zext(f13byte_t) * zext(W0byte); +} + + +:mul.ss Wbd_t,WsMUL_t,Wndd_t is + OP_23_20=0xb & OP_19_16=0x9 & OP_15=1 & Wbd_t & Wndd_t & OP_7=0 & $(WSconstraint) & WsMUL_t { + + Wndd_t = sext(Wbd_t) * sext(WsMUL_t); +} + + +@if defined(dsPIC33E) || defined(dsPIC33C) +A7_t: ACCA is TOK_7=0 & ACCA + { export ACCA; } + +A7_t: ACCB is TOK_7=1 & ACCB + { export ACCB; } + +:mul.ss Wbd_t,WsMUL_t,A7_t is OP_23_20=0xb & OP_19_16=0x9 & OP_15=1 & Wbd_t & OP_10_8=0x7 & A7_t & $(WSconstraint) & WsMUL_t { + + A7_t = sext(Wbd_t) * sext(WsMUL_t); +} +@endif + + +:mul.su Wbd_t,k5,Wndd_t is OP_23_20=0xb & OP_19_16=0x9 & OP_15=0 & Wbd_t & Wndd_t & OP_7=0 & OP_6_5=3 & k5 { + + Wndd_t = sext(Wbd_t) * zext(k5); +} + +:mul.su Wbd_t,WsMUL_t,Wndd_t is OP_23_20=0xb & OP_19_16=0x9 & OP_15=0 & Wbd_t & Wndd_t & OP_7=0 & $(WSconstraint) & WsMUL_t { + + Wndd_t = sext(Wbd_t) * zext(WsMUL_t); +} + + +@if defined(dsPIC33E) || defined(dsPIC33C) +:mul.su Wbd_t,WsMUL_t,A7_t is + OP_23_20=0xb & OP_19_16=0x9 & OP_15=0 & Wbd_t & OP_10_8=0x7 & A7_t & $(WSconstraint) & WsMUL_t { + + A7_t = sext(Wbd_t) * zext(WsMUL_t); +} + + +:mul.su Wbd_t,k5,A7_t is + OP_23_20=0xb & OP_19_16=0x9 & OP_15=0 & Wbd_t & OP_10_8=0x7 & A7_t & OP_6_5=0x3 & k5 { + + A7_t = sext(Wbd_t) * zext(k5); +} +@endif + + +:mul.us Wbd_t,WsMUL_t,Wndd_t is + OP_23_20=0xb & OP_19_16=0x8 & OP_15=1 & Wbd_t & Wndd_t & OP_7=0 & $(WSconstraint) & WsMUL_t { + + Wndd_t = zext(Wbd_t) * sext(WsMUL_t); +} + + +@if defined(dsPIC33E) || defined(dsPIC33C) +:mul.us Wbd_t,WsMUL_t,A7_t is + OP_23_20=0xb & OP_19_16=0x8 & OP_15=1 & Wbd_t & OP_10_8=0x7 & A7_t & $(WSconstraint) & WsMUL_t { + + A7_t = zext(Wbd_t) * sext(WsMUL_t); +} +@endif + + +:mul.uu Wbd_t,k5,Wndd_t is + OP_23_20=0xb & OP_19_16=0x8 & OP_15=0 & Wbd_t & Wndd_t & OP_7=0 & OP_6_5=0x3 & k5 { + + Wndd_t = zext(Wbd_t) * zext(k5); +} + +:mul.uu Wbd_t,WsMUL_t,Wndd_t is OP_23_20=0xb & OP_19_16=0x8 & OP_15=0 & Wbd_t & Wndd_t & OP_7=0 & $(WSconstraint) & WsMUL_t { + + Wndd_t = zext(Wbd_t) * zext(WsMUL_t); +} + + +@if defined(dsPIC33E) || defined(dsPIC33C) +:mul.uu Wbd_t,WsMUL_t,A7_t is + OP_23_20=0xb & OP_19_16=0x8 & OP_15=0 & Wbd_t & OP_10_8=0x7 & A7_t & $(WSconstraint) & WsMUL_t { + + A7_t = zext(Wbd_t) * zext(WsMUL_t); +} + + +:mul.uu Wbd_t,k5,A7_t is + OP_23_20=0xb & OP_19_16=0x8 & OP_15=0 & Wbd_t & OP_10_8=0x7 & A7_t & OP_6_5=0x3 & k5 { + + A7_t = zext(Wbd_t) * zext(k5); +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:mulw.ss Wbd_t,WsMUL_t,Wndd_t is + OP_23_20=0xb & OP_19_16=0x9 & OP_15=1 & Wbd_t & Wndd_t & OP_7=1 & $(WSconstraint) & WsMUL_t { + + Wndd_t = sext(Wbd_t) * sext(WsMUL_t); +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:mulw.su Wbd_t,WsMUL_t,Wndd_t is + OP_23_20=0xb & OP_19_16=0x9 & OP_15=0 & Wbd_t & Wndd_t & OP_7=1 & $(WSconstraint) & WsMUL_t { + + Wndd_t = sext(Wbd_t) * zext(WsMUL_t); +} + + +:mulw.su Wbd_t,k5_t,Wndd_t is + OP_23_20=0xb & OP_19_16=0x9 & OP_15=0 & Wbd_t & Wndd_t & OP_7=1 & OP_6_5=3 & k5_t { + + Wndd_t = sext(Wbd_t) * zext(k5_t); +} +@endif + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) + +:mulw.us Wbd_t,WsMUL_t,Wndd_t is + OP_23_20=0xb & OP_19_16=0x8 & OP_15=1 & Wbd_t & Wndd_t & OP_7=1 & $(WSconstraint) & WsMUL_t { + + Wndd_t = zext(Wbd_t) * sext(WsMUL_t); +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:mulw.uu Wbd_t,WsMUL_t,Wndd_t is + OP_23_20=0xb & OP_19_16=0x8 & OP_15=0 & Wbd_t & Wndd_t & OP_7=1 & $(WSconstraint) & WsMUL_t { + + Wndd_t = zext(Wbd_t) * zext(WsMUL_t); +} + + +:mulw.uu Wbd_t,k5_t,Wndd_t is + OP_23_20=0xb & OP_19_16=0x8 & OP_15=0 & Wbd_t & Wndd_t & OP_7=1 & OP_6_5=3 & k5_t { + + Wndd_t = zext(Wbd_t) * zext(k5_t); +} +@endif + + +:neg.w f13_t^WREG_t is OP_23_16=0xee & OP_15=0 & OP_14=0 & WREG_t & f13_t { + + WREG_t = -f13_t; + + SRH_DC = 0; + SRL_OV = 0; + SRL_C = 0; + testSRL_N(WREG_t); + testSRL_Z(WREG_t); +} + +:neg.b f13byte_t^WREGbyte_t is OP_23_16=0xee & OP_15=0 & OP_14=1 & WREGbyte_t & f13byte_t { + + WREGbyte_t = -f13byte_t; + + SRH_DC = 0; + SRL_OV = 0; + SRL_C = 0; + testSRL_N(WREGbyte_t); + testSRL_Z(WREGbyte_t); +} + + +:neg.w Ws_t,Wd_t is OP_23_16=0xea & OP_15=0 & OP_14=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t { + + local result = -Ws_t; + build Wd_t; + Wd_t = result; + + SRH_DC = 0; + SRL_OV = 0; + SRL_C = 0; + testSRL_N(result); + testSRL_Z(result); +} + +:neg.b Wsbyte_t,Wdbyte_t is OP_23_16=0xea & OP_15=0 & OP_14=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { + + local result = -Wsbyte_t; + build Wdbyte_t; + Wdbyte_t = result; + + SRH_DC = 0; + SRL_OV = 0; + SRL_C = 0; + testSRL_N(result); + testSRL_Z(result); +} + + +@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C) +:neg ACCA_t is OP_23_20=0xC & OP_19_16=0xB & ACCA_t & + OP_14_12=0x1 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 { + + ACCA = -ACCA; + testSRH_OA(); + testSRH_SA(); +} + +:neg ACCB_t is OP_23_20=0xC & OP_19_16=0xB & ACCB_t & + OP_14_12=0x1 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 { + + ACCB = -ACCB; + testSRH_OB(); + testSRH_SB(); +} +@endif + + +:nop is OP_23_16=0x0 { + # No definition on purpose +} + + +# +:nopr is OP_23_16=0xff { + # No definition on purpose +} + + +:pop f15_t is OP_23_20=0xF & OP_19_16=0x9 & f15_t & OP_0=0x0 { + + W15 = W15 - 2; + f15_t = *[ram]:2 W15; +} + + +:pop movWd is OP_23_20=0x7 & OP_19=0x1 & movWd & OP_14=0x0 & OP_6_4=0x4 & OP_3_0=0xF { + + W15 = W15 - 2; + local result = *[ram]:2 W15; + build movWd; + movWd = result; +} + + +:pop.d Wndd_t is OP_23_20=0xB & OP_19_16=0xE & OP_15_12=0x0 & OP_11=0x0 & Wndd_t & OP_7_4=0x4 & OP_3_0=0xF { + + W15 = W15 - 4; + Wndd_t = *[ram]:4 W15; +} + + +:pop.s is OP_23_20=0xF & OP_19_16=0xE & OP_15_12=0x8 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 { + + W0 = SHADOW_W0; + W1 = SHADOW_W1; + W2 = SHADOW_W2; + W3 = SHADOW_W3; + + SRL_C = SHADOW_SRL_C; + SRL_Z = SHADOW_SRL_Z; + SRL_OV = SHADOW_SRL_OV; + SRL_N = SHADOW_SRL_N; + SRH_DC = SHADOW_SRH_DC; +} + + +:push f15_t is OP_23_20=0xF & OP_19_16=0x8 & f15_t & OP_0=0x0 { + + *[ram]:2 W15 = f15_t; + W15 = W15 + 2; +} + + +:push movWs is OP_23_20=0x7 & OP_19=0x1 & movWs & OP_14_12=0x1 & OP_11_8=0xF & OP_7=0x1 { + + *[ram]:2 W15 = movWs; + W15 = W15 + 2; +} + + +:push.d TOK_3_1_Dregn is OP_23_20=0xB & OP_19_16=0xE & OP_15_12=0x9 & OP_11_8=0xF & OP_7_4=0x8 & TOK_3_1_Dreg & TOK_3_1_Dregn & OP_0=0x0 { + + *[ram]:4 W15 = TOK_3_1_Dreg; + W15 = W15 + 4; +} + + +:push.s is OP_23_20=0xF & OP_19_16=0xE & OP_15_12=0xA & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 { + + SHADOW_W0 = W0; + SHADOW_W1 = W1; + SHADOW_W2 = W2; + SHADOW_W3 = W3; + + SHADOW_SRL_C = SRL_C; + SHADOW_SRL_Z = SRL_Z; + SHADOW_SRL_OV = SRL_OV; + SHADOW_SRL_N = SRL_N; + SHADOW_SRH_DC = SRH_DC; +} + + +define pcodeop pwrsavOp; + +:pwrsav OP_0 is OP_23_1=0x7f2000 & OP_0 { + pwrsavOp(); +} + + +@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) +:rcall n16_t is OP_23_20=0x0 & OP_19_16=0x7 & n16_t & WordInstNext4 { + *[ram]:4 W15 = WordInstNext4; + W15 = W15 + 4; + + call n16_t; +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:rcall n16_t is OP_23_20=0x0 & OP_19_16=0x7 & n16_t & WordInstNext4 { + *[ram]:4 W15 = WordInstNext4 | zext(CORCON_SFA); + W15 = W15 + 4; + CORCON_SFA = 0; + + call n16_t; +} +@endif + + +@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) +:rcall WnRDest_t is OP_23_20=0x0 & OP_19_16=0x1 & OP_15_12=0x2 & OP_11_8=0x0 & OP_7_4=0x0 & WnRDest_t & WordInstNext4 { + *[ram]:4 W15 = WordInstNext4; + W15 = W15 + 4; + + call [WnRDest_t]; +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:rcall WnRDest_t is OP_23_20=0x0 & OP_19_16=0x1 & OP_15_12=0x0 & OP_11_8=0x2 & OP_7_4=0x0 & WnRDest_t & WordInstNext4 { + *[ram]:4 W15 = WordInstNext4 | zext(CORCON_SFA); + W15 = W15 + 4; + CORCON_SFA = 0; + + call [WnRDest_t]; +} +@endif + + +@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) +:repeat k14_t is OP_23_14=0x24 & k14_t + [ repeatInstr=1; globalset(inst_next,repeatInstr); ] +{ + RCOUNT = k14_t + 1; +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:repeat k15_t is OP_23_16=0x09 & OP_15=0 & k15_t + [ repeatInstr=1; globalset(inst_next,repeatInstr); ] +{ + RCOUNT = k15_t + 1; +} +@endif + + +@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) +:repeat TOK_3_0_Wreg is OP_23_4=0x9800 & TOK_3_0_Wreg + [ repeatInstr=1; globalset(inst_next,repeatInstr); ] +{ + RCOUNT = TOK_3_0_Wreg & 0x7FFF; +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:repeat TOK_3_0_Wreg is OP_23_4=0x9800 & TOK_3_0_Wreg + [ repeatInstr=1; globalset(inst_next,repeatInstr); ] +{ + RCOUNT = TOK_3_0_Wreg; +} +@endif + + +:reset is OP_23_0=0xfe0000 { + SRH_OA = 0; + SRH_OB = 0; + SRH_OAB = 0; + SRH_SA = 0; + SRH_SB = 0; + SRH_SAB = 0; + SRH_DA = 0; + SRH_DC = 0; + SRL_IPL2 = 0; + SRL_IPL1 = 0; + SRL_IPL0 = 0; + SRL_RA = 0; + SRL_N = 0; + SRL_OV = 0; + SRL_Z = 0; + SRL_C = 0; + CORCON_SFA = 0; + PC = 0; + goto [PC]; +} + + +@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) +:retfie is OP_23_20=0x0 & OP_19_16=0x6 & OP_15_12=0x4 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 { + W15 = W15 - 4; + local tmp = *[ram]:4 W15; + tmpSRL:1 = tmp(3); + unpackSRL( tmpSRL ); + CORCON_IPL3 = (tmp & 0x00800000) != 0; + return [tmp & 0x7FFFFF]; +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:retfie is OP_23_20=0x0 & OP_19_16=0x6 & OP_15_12=0x4 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 { + W15 = W15 - 4; + local tmp = *[ram]:4 W15; + tmpSRL:1 = tmp(3); + unpackSRL( tmpSRL ); + CORCON_IPL3 = (tmp & 0x00800000) != 0; + CORCON_SFA = (tmp & 0x1) != 0; + return [tmp & 0x7FFFFE]; +} +@endif + + +@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) +:retlw.w k10_t,Wn_t is OP_23_20=0x0 & OP_19_16=0x5 & OP_15=0 & k10_t & Wn_t { + W15 = W15 - 4; + local tmp = *[ram]:4 W15; + tmpSRL:1 = tmp(3); + unpackSRL( tmpSRL ); + CORCON_IPL3 = (tmp & 0x00800000) != 0; + Wn_t = k10_t; + return [tmp & 0x7FFFFF]; +} + + +:retlw.b k10byte_t,Wnbyte_t is OP_23_20=0x0 & OP_19_16=0x5 & OP_15=0 & k10byte_t & Wnbyte_t { + W15 = W15 - 4; + local tmp = *[ram]:4 W15; + tmpSRL:1 = tmp(3); + unpackSRL( tmpSRL ); + CORCON_IPL3 = (tmp & 0x00800000) != 0; + Wnbyte_t = k10byte_t; + return [tmp & 0x7FFFFF]; +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:retlw.w k10_t,Wn_t is OP_23_20=0x0 & OP_19_16=0x5 & OP_15=0 & k10_t & Wn_t { + W15 = W15 - 4; + local tmp = *[ram]:4 W15; + tmpSRL:1 = tmp(3); + unpackSRL( tmpSRL ); + CORCON_IPL3 = (tmp & 0x00800000) != 0; + CORCON_SFA = (tmp & 0x1) != 0; + Wn_t = k10_t; + return [tmp & 0x7FFFFE]; +} + + +:retlw.b k10byte_t,Wnbyte_t is OP_23_20=0x0 & OP_19_16=0x5 & OP_15=0 & k10byte_t & Wnbyte_t { + W15 = W15 - 4; + local tmp = *[ram]:4 W15; + tmpSRL:1 = tmp(3); + unpackSRL( tmpSRL ); + CORCON_IPL3 = (tmp & 0x00800000) != 0; + CORCON_SFA = (tmp & 0x1) != 0; + Wnbyte_t = k10byte_t; + return [tmp & 0x7FFFFE]; +} +@endif + + +@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) +:return is OP_23_20=0x0 & OP_19_16=0x6 & OP_15_12=0x0 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 { + W15 = W15 - 4; + local tmp = *[ram]:4 W15; + return [tmp & 0x7FFFFF]; +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:return is OP_23_20=0x0 & OP_19_16=0x6 & OP_15_12=0x0 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 { + W15 = W15 - 4; + local tmp = *[ram]:4 W15; + CORCON_SFA = ( tmp & 0x0001 ) != 0; + tmp = tmp & 0x7FFFFE; + return [tmp]; +} +@endif + + +:rlc.w f13_t^WREG_t is OP_23_16=0xd6 & OP_15=1 & WREG_t & f13_t { + + local src = f13_t; + WREG_t = ( src << 1 ) | zext(SRL_C); + testSRL_N(WREG_t); + testSRL_Z(WREG_t); + SRL_C = ( src & 0x8000 ) != 0; +} + +:rlc.b f13byte_t^WREGbyte_t is OP_23_16=0xd6 & OP_15=1 & WREGbyte_t & f13byte_t { + + local src = f13byte_t; + WREGbyte_t = ( src << 1 ) | SRL_C; + testSRL_N(WREGbyte_t); + testSRL_Z(WREGbyte_t); + SRL_C = ( src & 0x80 ) != 0; +} + + +:rlc.w Ws_t,Wd_t is OP_23_16=0xd2 & OP_15=1 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t { + + local src = Ws_t; + local result = (src << 1) | zext(SRL_C); + build Wd_t; + Wd_t = result; + + testSRL_N(result); + testSRL_Z(result); + SRL_C = (src & 0x8000) != 0; +} + + +:rlc.b Wsbyte_t,Wdbyte_t is OP_23_16=0xd2 & OP_15=1 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { + + local src = Wsbyte_t; + local result = (src << 1) | SRL_C; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N(result); + testSRL_Z(result); + SRL_C = (src & 0x80) != 0; +} + + +:rlnc.w f13_t^WREG_t is OP_23_16=0xd6 & OP_15=0 & WREG_t & f13_t { + + local src = f13_t; + WREG_t = (src << 1) | ((src & 0x8000) >> 15); + testSRL_N(WREG_t); + testSRL_Z(WREG_t); +} +:rlnc.b f13byte_t^WREGbyte_t is OP_23_16=0xd6 & OP_15=0 & WREGbyte_t & f13byte_t { + + local src = f13byte_t; + WREGbyte_t = (src << 1) | ((src & 0x80) >> 7); + testSRL_N(WREGbyte_t); + testSRL_Z(WREGbyte_t); +} + + +:rlnc.w Ws_t,Wd_t is OP_23_16=0xd2 & OP_15=0 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t { + + local src = Ws_t; + local result = (src << 1) | ((src & 0x8000) >> 15); + build Wd_t; + Wd_t = result; + + testSRL_N(result); + testSRL_Z(result); +} + +:rlnc.b Wsbyte_t,Wdbyte_t is OP_23_16=0xd2 & OP_15=0 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { + + local src = Wsbyte_t; + local result = (src << 1) | ((src & 0x80) >> 7); + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N(result); + testSRL_Z(result); +} + + +:rrc.w f13_t^WREG_t is OP_23_16=0xd7 & OP_15=1 & WREG_t & f13_t { + + local src = f13_t; + WREG_t = ((zext(SRL_C)) * 0x8000) | (src >> 1); + testSRL_N(WREG_t); + testSRL_Z(WREG_t); + SRL_C = (src & 1) != 0; +} + + +:rrc.b f13byte_t^WREGbyte_t is OP_23_16=0xd7 & OP_15=1 & WREGbyte_t & f13byte_t { + + local src = f13byte_t; + WREGbyte_t = (SRL_C * 0x80) | (src >> 1) ; + testSRL_N(WREGbyte_t); + testSRL_Z(WREGbyte_t); + SRL_C = (src & 1) != 0; +} + + +:rrc.w Ws_t,Wd_t is OP_23_16=0xd3 & OP_15=1 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t { + + local src = Ws_t; + local result = ((zext(SRL_C)) * 0x8000) | (src >> 1); + build Wd_t; + Wd_t = result; + + testSRL_N(result); + testSRL_Z(result); + SRL_C = (src & 1) != 0; +} + + +:rrc.b Wsbyte_t,Wdbyte_t is OP_23_16=0xd3 & OP_15=1 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { + + local src = Wsbyte_t; + local result = (SRL_C * 0x80) | (src >> 1); + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N(result); + testSRL_Z(result); + SRL_C = (src & 1) != 0; +} + + +:rrnc.w f13_t^WREG_t is OP_23_16=0xd7 & OP_15=0 & TOK_B=0 & WREG_t & f13_t { + + local src = f13_t; + WREG_t = (src >> 1) | ((src & 1) * 0x8000); + testSRL_N(WREG_t); + testSRL_Z(WREG_t); +} + + +:rrnc.b f13byte_t^WREGbyte_t is OP_23_16=0xd7 & OP_15=0 & TOK_B=1 & WREGbyte_t & f13byte_t { + + local src = f13byte_t; + WREGbyte_t = (src >> 1) | ((src & 1) * 0x80); + testSRL_N(WREGbyte_t); + testSRL_Z(WREGbyte_t); +} + + +:rrnc.w Ws_t,Wd_t is OP_23_16=0xd3 & OP_15=0 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t { + + local src = Ws_t; + local result = (src >> 1) | ((src & 1) * 0x8000); + build Wd_t; + Wd_t = result; + + testSRL_N(Wd_t); + testSRL_Z(Wd_t); +} + + +:rrnc.b Wsbyte_t,Wdbyte_t is OP_23_16=0xd3 & OP_15=0 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { + + local src = Wsbyte_t; + local result = (src >> 1) | ((src & 1) * 0x80); + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N(result); + testSRL_Z(result); +} + + +@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C) +:sac ACCA_t^r4_t,WdWRO_t is OP_23_20=0xC & OP_19_16=0xC & ACCA_t & r4_t & WdWRO_t { + + local tmp:6 = ACCA s>> (16 + r4_t); + WdWRO_t = tmp:2; +} + +:sac ACCB_t^r4_t,WdWRO_t is OP_23_20=0xC & OP_19_16=0xC & ACCB_t & r4_t & WdWRO_t { + + local tmp:6 = ACCB s>> (16 + r4_t); + WdWRO_t = tmp:2; +} +@endif + + +@if defined(dsPIC33C) +:sac.d ACCA_t^r4_t,Wsnd_t is OP_23_16=0xDC & OP_14=0x0 & OP_7_4=0x0 & ACCA_t & r4_t & Wsnd_t { + + local tmp:6 = ACCA s>> (16 + r4_t); + Wsnd_t = tmp:2; +} + +:sac.d ACCB_t^r4_t,Wsnd_t is OP_23_16=0xDC & OP_14=0x0 & OP_7_4=0x0 & ACCB_t & r4_t & Wsnd_t { + + local tmp:6 = ACCB s>> (16 + r4_t); + Wsnd_t = tmp:2; +} +@endif + + +@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C) +:sac.r ACCA_t^r4_t,WdWRO_t is OP_23_20=0xC & OP_19_16=0xD & ACCA_t & r4_t & WdWRO_t { + + local tmp:6 = ( ACCA + (0x80000000 >> (16 - r4_t)) ) s>> (16 + r4_t); + WdWRO_t = tmp:2; +} + +:sac.r ACCB_t^r4_t,WdWRO_t is OP_23_20=0xC & OP_19_16=0xD & ACCB_t & r4_t & WdWRO_t { + + local tmp:6 = ( ACCB + (0x80000000 >> (16 - r4_t)) ) s>> (16 + r4_t); + WdWRO_t = tmp:2; +} +@endif + + +:se Ws_t,Wnd_t is OP_23_11=0x1f60 & Wnd_t & $(WSconstraint) & Ws_t { + + Wnd_t = sext(Ws_t:1); + testSRL_N(Wnd_t); + testSRL_Z(Wnd_t); + SRL_C = !SRL_N; +} + + +:setm.w f13_t^WREG_t is OP_23_16=0xef & OP_15=1 & WREG_t & f13_t { + + WREG_t = 0xFFFF; +} + +:setm.b f13byte_t^WREGbyte_t is OP_23_16=0xef & OP_15=1 & WREGbyte_t & f13byte_t { + + WREGbyte_t = 0xFF; +} + + +:setm.w Wd_t is OP_23_16=0xeb & OP_15=1 & OP_6_0=0x0 & TOK_B=0 & $(WDconstraint) & Wd_t { + + Wd_t = 0xFFFF; +} + + +:setm.b Wdbyte_t is OP_23_16=0xeb & OP_15=1 & OP_6_0=0x0 & TOK_B=1 & $(WDconstraint) & Wdbyte_t { + + Wdbyte_t = 0xFF; +} + + +@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C) +:sftac ACCA_t,k6_t is + OP_23_20=0xC & OP_19_16=0x8 & ACCA_t & OP_14_12=0x0 & OP_11_8=0x0 & OP_7_6=0x1 & k6_t { + + local tmp:8 = (sext(ACCA) << (16 - k6_t)) >> 16; + ACCA = tmp:6; + testSRH_OA(); + testSRH_SA(); +} + +:sftac ACCB_t,k6_t is + OP_23_20=0xC & OP_19_16=0x8 & ACCB_t & OP_14_12=0x0 & OP_11_8=0x0 & OP_7_6=0x1 & k6_t { + + local tmp:8 = (sext(ACCB) << (16 - k6_t)) >> 16; + ACCB = tmp:6; + testSRH_OB(); + testSRH_SB(); +} +@endif + + +@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C) +:sftac ACCA_t,Wbsft_t is + OP_23_20=0xC & OP_19_16=0x8 & ACCA_t & OP_14_12=0x0 & OP_11_8=0x0 & OP_7_4=0x0 & Wbsft_t { + + local tmp:8 = (sext(ACCA) << (16 - Wbsft_t)) >> 16; + ACCA = tmp:6; + testSRH_OA(); + testSRH_SA(); +} + +:sftac ACCB_t,Wbsft_t is + OP_23_20=0xC & OP_19_16=0x8 & ACCB_t & OP_14_12=0x0 & OP_11_8=0x0 & OP_7_4=0x0 & Wbsft_t { + + local tmp:8 = (sext(ACCB) << (16 - Wbsft_t)) >> 16; + ACCB = tmp:6; + testSRH_OB(); + testSRH_SB(); +} +@endif + + +:sl.w f13_t^WREG_t is OP_23_20=0xD & OP_19_16=0x4 & OP_15=0x0 & WREG_t & f13_t { + + local src = f13_t; + WREG_t = src << 1; + testSRL_N(WREG_t); + testSRL_Z(WREG_t); + SRL_C = ((src & 0x8000) != 0); +} + + +:sl.b f13byte_t^WREGbyte_t is OP_23_20=0xD & OP_19_16=0x4 & OP_15=0x0 & WREGbyte_t & f13byte_t { + + local src = f13byte_t; + WREGbyte_t = src << 1; + testSRL_N(WREGbyte_t); + testSRL_Z(WREGbyte_t); + SRL_C = ((src & 0x80) != 0); +} + + +:sl.w Ws_t,Wd_t is OP_23_20=0xD & OP_19_16=0x0 & OP_15=0x0 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t { + + local src = Ws_t; + local result = src << 1; + build Wd_t; + Wd_t = result; + + testSRL_N(result); + testSRL_Z(result); + SRL_C = ((src & 0x8000) != 0); +} + +:sl.b Wsbyte_t,Wdbyte_t is OP_23_20=0xD & OP_19_16=0x0 & OP_15=0x0 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { + + local src = Wsbyte_t; + local result = src << 1; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N(result); + testSRL_Z(result); + SRL_C = ((src & 0x80) != 0); +} + + +:sl Wbd_t,k4_t,Wnd_t is OP_23_20=0xD & OP_19_16=0xD & OP_15=0x0 & Wbd_t & Wnd_t & OP_6_4=0x4 & k4_t { + + Wnd_t = Wbd_t << k4_t; + testSRL_N(Wnd_t); + testSRL_Z(Wnd_t); +} + + +:sl Wbd_t,Wns_t,Wnd_t is OP_23_20=0xD & OP_19_16=0xD & OP_15=0x0 & Wbd_t & Wnd_t & OP_6_4=0x0 & Wns_t { + + Wnd_t = Wbd_t << (Wns_t & 0x1F); + testSRL_N(Wnd_t); + testSRL_Z(Wnd_t); +} + +# SSTEP - ICD instruction compatible with Microchips ICD debugging hardware +# TODO: locate encoding details for SSTEP instruction +# define pcodeop sstep; +# :sstep is OP_23_0=?? { +# sstep(); # In-Circuit Debugger (ICD) Single Step +# } + +:sub.w f13_t^WREG_t is OP_23_20=0xB & OP_19_16=0x5 & OP_15=0 & WREG_t & f13_t { + + local src = f13_t; + subflags( src, W0 ); + + WREG_t = src - W0; + + testSRL_N ( WREG_t ); + testSRL_Z ( WREG_t ); + testSRH_DCword( WREG_t ); +} + + +:sub.b f13byte_t^WREGbyte_t is OP_23_20=0xB & OP_19_16=0x5 & OP_15=0 & WREGbyte_t & f13byte_t { + + local src = f13byte_t; + subflags( src, W0byte ); + + WREGbyte_t = src - W0byte; + + testSRL_N ( WREGbyte_t ); + testSRL_Z ( WREGbyte_t ); + testSRH_DCbyte( WREGbyte_t ); +} + + +:sub.w k10_t,Wn_t is OP_23_20=0xB & OP_19_16=0x1 & OP_15=0 & k10_t & Wn_t { + + subflags( Wn_t, k10_t ); + + Wn_t = Wn_t - k10_t; + + testSRL_N ( Wn_t ); + testSRL_Z ( Wn_t ); + testSRH_DCword( Wn_t ); +} + + +:sub.b k10byte_t,Wnbyte_t is OP_23_20=0xB & OP_19_16=0x1 & OP_15=0 & k10byte_t & Wnbyte_t { + + subflags( Wnbyte_t, k10byte_t ); + + Wnbyte_t = Wnbyte_t - k10byte_t; + + testSRL_N ( Wnbyte_t ); + testSRL_Z ( Wnbyte_t ); + testSRH_DCbyte( Wnbyte_t ); +} + + +:sub.w Wb_t,k5_t,Wd_t is OP_23_20=0x5 & OP_19=0x0 & OP_6_5=0x3 & Wb_t & $(WDconstraint) & Wd_t & k5_t { + + subflags( Wb_t, k5_t ); + + local result = Wb_t - k5_t; + build Wd_t; + Wd_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); + testSRH_DCword( result ); +} + + +:sub.b Wbbyte_t,k5byte_t,Wdbyte_t is + OP_23_20=0x5 & OP_19=0x0 & OP_6_5=0x3 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & k5byte_t { + + subflags( Wbbyte_t, k5byte_t ); + + local result = Wbbyte_t - k5byte_t; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); + testSRH_DCbyte( result ); +} + + +:sub.w Wb_t,Ws_t,Wd_t is OP_23_20=0x5 & OP_19=0x0 & TOK_B=0 & Wb_t & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t { + + local src = Ws_t; + subflags( Wb_t, src ); + + local result = Wb_t - src; + build Wd_t; + Wd_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); + testSRH_DCword( result ); +} + + +:sub.b Wbbyte_t,Wsbyte_t,Wdbyte_t is OP_23_20=0x5 & OP_19=0x0 & TOK_B=1 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { + + local src = Wsbyte_t; + subflags( Wbbyte_t, src ); + + local result = Wbbyte_t - src; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); + testSRH_DCbyte( result ); +} + + +@if defined(dsPIC30F) || defined(dsPIC33F) || defined(dsPIC33E) || defined(dsPIC33C) +:sub ACCA_t is + OP_23_20=0xC & OP_19_16=0xB & ACCA_t & OP_14_12=0x3 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 { + + ACCA = ACCB - ACCA; + testSRH_OA(); + testSRH_SA(); +} + +:sub ACCB_t is + OP_23_20=0xC & OP_19_16=0xB & ACCB_t & OP_14_12=0x3 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 { + + ACCB = ACCA - ACCB; + testSRH_OB(); + testSRH_SB(); +} +@endif + + +:subb.w f13_t^WREG_t is OP_23_20=0xB & OP_19_16=0x5 & OP_15=1 & WREG_t & f13_t { + + local notCarry:2 = zext(!SRL_C); + subflagsWithCarry( f13_t, W0, notCarry ); + + WREG_t = f13_t - W0 - notCarry; + + testSRL_N ( WREG_t ); + testSRL_Zsticky( WREG_t ); + testSRH_DCword ( WREG_t ); +} + +:subb.b f13byte_t^WREGbyte_t is OP_23_20=0xB & OP_19_16=0x5 & OP_15=1 & WREGbyte_t & f13byte_t { + + local notCarry = !SRL_C; + subflagsWithCarry( f13byte_t, W0byte, notCarry ); + + WREGbyte_t = f13byte_t - W0byte - notCarry; + + testSRL_N ( WREGbyte_t ); + testSRL_Zsticky( WREGbyte_t ); + testSRH_DCbyte ( WREGbyte_t ); +} + + +:subb.w k10_t,Wn_t is OP_23_20=0xB & OP_19_16=0x1 & OP_15=1 & k10_t & Wn_t { + + local notCarry:2 = zext(!SRL_C); + subflagsWithCarry( Wn_t, k10_t, notCarry ); + + Wn_t = Wn_t - k10_t - notCarry; + + testSRL_N ( Wn_t ); + testSRL_Zsticky( Wn_t ); + testSRH_DCword ( Wn_t ); +} + + +:subb.b k10byte_t,Wnbyte_t is OP_23_20=0xB & OP_19_16=0x1 & OP_15=1 & k10byte_t & Wnbyte_t { + + local notCarry = !SRL_C; + subflagsWithCarry( Wnbyte_t, k10byte_t, notCarry ); + + Wnbyte_t = Wnbyte_t - k10byte_t - notCarry; + + testSRL_N ( Wnbyte_t ); + testSRL_Zsticky( Wnbyte_t ); + testSRH_DCbyte ( Wnbyte_t ); +} + + +:subb.w Wb_t,k5_t,Wd_t is OP_23_20=0x5 & OP_19=0x1 & OP_6_5=0x3 & Wb_t & $(WDconstraint) & Wd_t & k5_t { + + local notCarry:2 = zext(!SRL_C); + subflagsWithCarry( Wb_t, k5_t, notCarry ); + + local result = Wb_t - k5_t - notCarry; + build Wd_t; + Wd_t = result; + + testSRL_N ( result ); + testSRL_Zsticky( result ); + testSRH_DCword ( result ); +} + +:subb.b Wbbyte_t,k5byte_t,Wdbyte_t is + OP_23_20=0x5 & OP_19=0x1 & OP_6_5=0x3 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & k5byte_t { + + local notCarry = !SRL_C; + subflagsWithCarry( Wbbyte_t, k5byte_t, notCarry ); + + local result = Wbbyte_t - k5byte_t - notCarry; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N ( result ); + testSRL_Zsticky( result ); + testSRH_DCbyte ( result ); +} + + +:subb.w Wb_t,Ws_t,Wd_t is OP_23_20=0x5 & OP_19=0x1 & TOK_B=0 & Wb_t & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t { + + local notCarry:2 = zext(!SRL_C); + local src = Ws_t; + subflagsWithCarry( Wb_t, src, notCarry ); + + local result = Wb_t - src - notCarry; + build Wd_t; + Wd_t = result; + + testSRL_N ( result ); + testSRL_Zsticky( result ); + testSRH_DCword ( result ); +} + + +:subb.b Wbbyte_t,Wsbyte_t,Wdbyte_t is OP_23_20=0x5 & OP_19=0x1 & TOK_B=1 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { + + local notCarry = !SRL_C; + local src = Wsbyte_t; + subflagsWithCarry( Wbbyte_t, src, notCarry ); + + local result = Wbbyte_t - src - notCarry; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N ( result ); + testSRL_Zsticky( result ); + testSRH_DCbyte ( result ); +} + + +:subbr.w f13_t^WREG_t is OP_23_20=0xB & OP_19_16=0xD & OP_15=1 & WREG_t & f13_t { + + local notCarry:2 = zext(!SRL_C); + local src = f13_t; + subflagsWithCarry( W0, src, notCarry ); + + WREG_t = W0 - src - notCarry; + + testSRL_N ( WREG_t ); + testSRL_Zsticky( WREG_t ); + testSRH_DCword ( WREG_t ); +} + +:subbr.b f13byte_t^WREGbyte_t is OP_23_20=0xB & OP_19_16=0xD & OP_15=1 & WREGbyte_t & f13byte_t { + + local notCarry = !SRL_C; + local src = f13byte_t; + subflagsWithCarry( W0byte, src, notCarry ); + + WREGbyte_t = W0byte - src - notCarry; + + testSRL_N ( WREGbyte_t ); + testSRL_Zsticky( WREGbyte_t ); + testSRH_DCbyte ( WREGbyte_t ); +} + + +:subbr.w Wb_t,k5_t,Wd_t is OP_23_20=0x1 & OP_19=0x1 & OP_6_5=0x3 & Wb_t & $(WDconstraint) & Wd_t & k5_t { + + local notCarry:2 = zext(!SRL_C); + subflagsWithCarry( k5_t, Wb_t, notCarry ); + + local result = k5_t - Wb_t - notCarry; + build Wd_t; + Wd_t = result; + + testSRL_N ( result ); + testSRL_Zsticky( result ); + testSRH_DCword ( result ); +} + + +:subbr.b Wbbyte_t,k5byte_t,Wdbyte_t is + OP_23_20=0x1 & OP_19=0x1 & OP_6_5=0x3 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & k5byte_t { + + local notCarry = !SRL_C; + subflagsWithCarry( k5byte_t, Wbbyte_t, notCarry ); + + local result = k5byte_t - Wbbyte_t - notCarry; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N ( result ); + testSRL_Zsticky( result ); + testSRH_DCbyte ( result ); +} + + +:subbr.w Wb_t,Ws_t,Wd_t is OP_23_20=0x1 & OP_19=0x1 & TOK_B=0 & Wb_t & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t { + + local notCarry:2 = zext(!SRL_C); + local src = Ws_t; + subflagsWithCarry( src, Wb_t, notCarry ); + + local result = src - Wb_t - notCarry; + build Wd_t; + Wd_t = result; + + testSRL_N ( result ); + testSRL_Zsticky( result ); + testSRH_DCword ( result ); +} + + +:subbr.b Wbbyte_t,Wsbyte_t,Wdbyte_t is OP_23_20=0x1 & OP_19=0x1 & TOK_B=1 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { + + local notCarry = !SRL_C; + local src = Wsbyte_t; + subflagsWithCarry( src, Wbbyte_t, notCarry ); + + local result = src - Wbbyte_t - notCarry; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N ( result ); + testSRL_Zsticky( result ); + testSRH_DCbyte ( result ); +} + + +:subr.w f13_t^WREG_t is OP_23_20=0xB & OP_19_16=0xD & OP_15=0 & WREG_t & f13_t { + + local src = f13_t; + subflags( W0, src ); + + WREG_t = W0 - src; + + testSRL_N ( WREG_t ); + testSRL_Z ( WREG_t ); + testSRH_DCword( WREG_t ); +} + + +:subr.b f13byte_t^WREGbyte_t is OP_23_20=0xB & OP_19_16=0xD & OP_15=0 & WREGbyte_t & f13byte_t { + + local src = f13byte_t; + subflags( W0byte, src ); + + WREGbyte_t = W0byte - src; + + testSRL_N ( WREGbyte_t ); + testSRL_Z ( WREGbyte_t ); + testSRH_DCbyte( WREGbyte_t ); +} + + +:subr.w Wb_t,k5_t,Wd_t is OP_23_20=0x1 & OP_19=0x0 & OP_6_5=0x3 & Wb_t & $(WDconstraint) & Wd_t & k5_t { + + subflags( k5_t, Wb_t ); + + local result = k5_t - Wb_t; + build Wd_t; + Wd_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); + testSRH_DCword( result ); +} + + +:subr.b Wbbyte_t,k5byte_t,Wdbyte_t is + OP_23_20=0x1 & OP_19=0x0 & OP_6_5=0x3 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & k5byte_t { + + subflags( k5byte_t, Wbbyte_t ); + + local result = k5byte_t - Wbbyte_t; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); + testSRH_DCbyte( result ); +} + + +:subr.w Wb_t,Ws_t,Wd_t is OP_23_20=0x1 & OP_19=0x0 & TOK_B=0 & Wb_t & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t { + + local src = Ws_t; + subflags( src, Wb_t ); + + local result = src - Wb_t; + build Wd_t; + Wd_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); + testSRH_DCword( result ); +} + + +:subr.b Wbbyte_t,Wsbyte_t,Wdbyte_t is OP_23_20=0x1 & OP_19=0x0 & TOK_B=1 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { + + local src = Wsbyte_t; + subflags( src, Wbbyte_t ); + + local result = src - Wbbyte_t; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N ( result ); + testSRL_Z ( result ); + testSRH_DCbyte( result ); +} + + +:swap.w Wn_t is OP_23_20=0xF & OP_19_16=0xD & OP_15=1 & OP_13_4=0x0 & TOK_B=0 & Wn_t { + + Wn_t = ((Wn_t & 0xFF) << 8) | ((Wn_t & 0xFF00) >> 8); +} + + +:swap.b Wnbyte_t is OP_23_20=0xF & OP_19_16=0xD & OP_15=1 & OP_13_4=0x0 & TOK_B=1 & Wnbyte_t { + + Wnbyte_t = ((Wnbyte_t & 0xF) << 4) | ((Wnbyte_t & 0xF0) >> 4); +} + + +# constructor Encoding: 1011 1010 1Bqq qddd dppp ssss +:tblrdh.w WsROM_t,Wd_t is OP_23_20=0xB & OP_19_16=0xA & OP_15=1 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & WsROM_t { + + local src = WsROM_t; + local result = zext( *[rom]:1 (src | 1) ); + build Wd_t; + Wd_t = result; +} + +:tblrdh.b WsROM_t,Wdbyte_t is OP_23_20=0xB & OP_19_16=0xA & OP_15=1 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & WsROM_t { + + local src = WsROM_t; + local result:1 = 0; + + if ( (src & 0x1) != 0) goto ; + result = *[rom]:1 (src | 1); + + + build Wdbyte_t; + Wdbyte_t = result; +} + + +# constructor Encoding: 1011 1010 0Bqq qddd dppp ssss +:tblrdl.w WsROM_t,Wd_t is OP_23_20=0xB & OP_19_16=0xA & OP_15=0 & TOK_B=0 & $(WDconstraint) & Wd_t & $(WSconstraint) & WsROM_t { + local src = WsROM_t; + local result = *[rom]:2 (src & 0xfffffe); + build Wd_t; + Wd_t = result; +} + +:tblrdl.b WsROM_t,Wdbyte_t is OP_23_20=0xB & OP_19_16=0xA & OP_15=0 & TOK_B=1 & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & WsROM_t { + local src = WsROM_t; + local lbit = src & 1; + local val = *[rom]:2 (src & 0xfffffe); + if (lbit == 0) goto ; + val = val >> 8; + + local result = val:1; + build Wdbyte_t; + Wdbyte_t = result; +} + + +:tblwth.w Ws_t,WdROM_t is OP_23_20=0xB & OP_19_16=0xB & OP_15=1 & TOK_B=0 & $(WDconstraint) & WdROM_t & $(WSconstraint) & Ws_t { + + local src = Ws_t; + local addr = WdROM_t | 1; # add 1, should be word alligned + # writing to upper byte PM<23:16>, can't write to padding byte + *[rom]:1 addr = src; +} + +:tblwth.b Wsbyte_t,WdROM_t is OP_23_20=0xB & OP_19_16=0xB & OP_15=1 & TOK_B=1 & $(WDconstraint) & WdROM_t & $(WSconstraint) & Wsbyte_t { + + local src = Wsbyte_t; + local addr = WdROM_t; + local lbit = addr & 1; + + if ( lbit != 0) goto ; + addr = addr | 1; + *[rom]:1 addr = src; + + +} + + +:tblwtl.w Ws_t,WdROM_t is OP_23_20=0xB & OP_19_16=0xB & OP_15=0 & TOK_B=0 & $(WDconstraint) & WdROM_t & $(WSconstraint) & Ws_t { + + local src = Ws_t; + local addr = WdROM_t & 0xfffffe; + *[rom]:2 addr = src; +} + +:tblwtl.b Wsbyte_t,WdROM_t is OP_23_20=0xB & OP_19_16=0xB & OP_15=0 & TOK_B=1 & $(WDconstraint) & WdROM_t & $(WSconstraint) & Wsbyte_t { + + local src = zext(Wsbyte_t); + local addr = WdROM_t; + local lobit = addr & 1; + local val = *[rom]:2 addr; + local mask = 0xff00; + # if dest is not word aligned, then write to PM<15:7> + if (lobit == 0) goto ; + mask = mask >> 8; # writing to second byte of word, protect low byte + src = src << 8; + + *[rom]:2 addr = (val & mask) | src; +} + + +@if defined(dsPIC30F) || defined(dsPIC33F) +define pcodeop Vector; + +:trap TOK_n,TOK_k16t is OP_23_20=0 & OP_19_17=5 & TOK_n & TOK_k16t & WordInstNext4 { + *[ram]:4 W15 = WordInstNext4; + W15 = W15 + 4; + + *[ram]:2 W15 = TOK_k16t; + + ptr:3 = Vector(TOK_n:1); # uncertain about vector storage + + call [ptr]; +} +@endif + + +@if defined(dsPIC33C) +define pcodeop verifyslave; +:vfslv PSV_t, EDS_t, k13_12_t is OP_23_16=0x03 & OP_15_14=0x2 & OP_11=0 & k13_12_t & EDS_t & PSV_t { + verifyslave(PSV_t, EDS_t, k13_12_t); +} +@endif + + +@if defined(PIC24F) || defined(PIC24H) || defined(dsPIC30F) || defined(dsPIC33F) +:ulnk is OP_23_20=0xF & OP_19_16=0xA & OP_15_12=0x08 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 { + + W15 = W14; + W15 = W15 - 2; + + W14 = *[ram]:2 W15; +} +@endif + + +@if defined(PIC24E) || defined(dsPIC33E) || defined(dsPIC33C) +:ulnk is OP_23_20=0xF & OP_19_16=0xA & OP_15_12=0x08 & OP_11_8=0x0 & OP_7_4=0x0 & OP_3_0=0x0 { + + W15 = W14; + W15 = W15 - 2; + + W14 = *[ram]:2 W15; + CORCON_SFA = 0; +} +@endif + +# URUN - ICD instruction compatible with Microchips ICD debugging hardware +define pcodeop urun; +:urun is OP_23_0=0xDAC000 { + urun(); # In-Circuit Debugger (ICD) Run +} + +:xor.w f13_t^WREG_t is OP_23_20=0xB & OP_19_16=0x6 & OP_15=1 & WREG_t & f13_t { + + WREG_t = W0 ^ f13_t; + testSRL_N(WREG_t); + testSRL_Z(WREG_t); +} + +:xor.b f13byte_t^WREGbyte_t is OP_23_20=0xB & OP_19_16=0x6 & OP_15=1 & WREGbyte_t & f13byte_t { + + WREGbyte_t = W0byte ^ f13byte_t; + testSRL_N(WREGbyte_t); + testSRL_Z(WREGbyte_t); +} + + +:xor.w k10_t,Wn_t is OP_23_20=0xB & OP_19_16=0x2 & OP_15=1 & k10_t & Wn_t { + + Wn_t = Wn_t ^ k10_t; + testSRL_N(Wn_t); + testSRL_Z(Wn_t); +} + +:xor.b k10byte_t,Wnbyte_t is OP_23_20=0xB & OP_19_16=0x2 & OP_15=1 & k10byte_t & Wnbyte_t { + + Wnbyte_t = Wnbyte_t ^ k10byte_t; + testSRL_N(Wnbyte_t); + testSRL_Z(Wnbyte_t); +} + + +:xor.w Wb_t,k5_t,Wd_t is OP_23_20=0x6 & OP_19=0x1 & Wb_t & $(WDconstraint) & Wd_t & OP_6_5=0x3 & k5_t { + + Wd_t = Wb_t ^ k5_t; + testSRL_N(Wd_t); + testSRL_Z(Wd_t); +} + +:xor.b Wbbyte_t,k5byte_t,Wdbyte_t is OP_23_20=0x6 & OP_19=0x1 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & OP_6_5=0x3 & k5byte_t { + + Wdbyte_t = Wbbyte_t ^ k5byte_t; + testSRL_N(Wdbyte_t); + testSRL_Z(Wdbyte_t); +} + + +:xor.w Wb_t,Ws_t,Wd_t is OP_23_20=0x6 & OP_19=0x1 & TOK_B=0 & Wb_t & $(WDconstraint) & Wd_t & $(WSconstraint) & Ws_t { + + local result = Wb_t ^ Ws_t; + build Wd_t; + Wd_t = result; + + testSRL_N(result); + testSRL_Z(result); +} + +:xor.b Wbbyte_t,Wsbyte_t,Wdbyte_t is OP_23_20=0x6 & OP_19=0x1 & TOK_B=1 & Wbbyte_t & $(WDconstraint) & Wdbyte_t & $(WSconstraint) & Wsbyte_t { + + local result = Wbbyte_t ^ Wsbyte_t; + build Wdbyte_t; + Wdbyte_t = result; + + testSRL_N(result); + testSRL_Z(result); +} + + +:ze Ws_t,Wnd_t is OP_23_20=0xF & OP_19_16=0xB & OP_15_12=0x8 & OP_11=0x0 & Wnd_t & $(WSconstraint) & Ws_t { + + local result = zext(Ws_t:1); + build Wnd_t; + Wnd_t = result; + + SRL_N = 0; + testSRL_Z(result); + SRL_C = 1; +} + + +# UNVERIFIED - not found in manual but was produced by toolchain for PIC30F2010 +# There appear to be a few variations of this encoding produced by toolchain +# but do not decode with objdump +define pcodeop break; +:break is OP_23_0=0xDA4000 { + break(); +} + +} # end with : phase = 2 diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/PIC24E.slaspec b/python/icicle/Ghidra/Processors/PIC/data/languages/PIC24E.slaspec new file mode 100644 index 0000000..5bb8b4a --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/PIC24E.slaspec @@ -0,0 +1,9 @@ +# This module defines Microchip PIC-24. + +# Based on "Microchip 16-bit MCU and DSC Programmer's Reference Manual (c)2005-2011 (i.e. PIC24_InstructionSet.pdf) + +define endian=little; # little endian only + +@define PIC24E "1" + +@include "PIC24.sinc" diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/PIC24F.slaspec b/python/icicle/Ghidra/Processors/PIC/data/languages/PIC24F.slaspec new file mode 100644 index 0000000..893d36c --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/PIC24F.slaspec @@ -0,0 +1,9 @@ +# This module defines Microchip PIC-24. + +# Based on "Microchip 16-bit MCU and DSC Programmer's Reference Manual (c)2005-2011 (i.e. PIC24_InstructionSet.pdf) + +define endian=little; # little endian only + +@define PIC24F "1" + +@include "PIC24.sinc" diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/PIC24H.slaspec b/python/icicle/Ghidra/Processors/PIC/data/languages/PIC24H.slaspec new file mode 100644 index 0000000..97a6fdc --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/PIC24H.slaspec @@ -0,0 +1,9 @@ +# This module defines Microchip PIC-24. + +# Based on "Microchip 16-bit MCU and DSC Programmer's Reference Manual (c)2005-2011 (i.e. PIC24_InstructionSet.pdf) + +define endian=little; # little endian only + +@define PIC24H "1" + +@include "PIC24.sinc" diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/PIC30.dwarf b/python/icicle/Ghidra/Processors/PIC/data/languages/PIC30.dwarf new file mode 100644 index 0000000..4f79ae1 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/PIC30.dwarf @@ -0,0 +1,21 @@ + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/PIC33.dwarf b/python/icicle/Ghidra/Processors/PIC/data/languages/PIC33.dwarf new file mode 100644 index 0000000..f3643f0 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/PIC33.dwarf @@ -0,0 +1,21 @@ + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/dsPIC30F.slaspec b/python/icicle/Ghidra/Processors/PIC/data/languages/dsPIC30F.slaspec new file mode 100644 index 0000000..2a0949b --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/dsPIC30F.slaspec @@ -0,0 +1,9 @@ +# This module defines Microchip PIC-24. + +# Based on "Microchip 16-bit MCU and DSC Programmer's Reference Manual (c)2005-2011 (i.e. PIC24_InstructionSet.pdf) + +define endian=little; # little endian only + +@define dsPIC30F "1" + +@include "PIC24.sinc" diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/dsPIC33C.slaspec b/python/icicle/Ghidra/Processors/PIC/data/languages/dsPIC33C.slaspec new file mode 100644 index 0000000..db48b4c --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/dsPIC33C.slaspec @@ -0,0 +1,7 @@ +# This module defines Microchip PIC-24. + +define endian=little; # little endian only + +@define dsPIC33C "1" + +@include "PIC24.sinc" diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/dsPIC33E.slaspec b/python/icicle/Ghidra/Processors/PIC/data/languages/dsPIC33E.slaspec new file mode 100644 index 0000000..b663aef --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/dsPIC33E.slaspec @@ -0,0 +1,9 @@ +# This module defines Microchip PIC-24. + +# Based on "Microchip 16-bit MCU and DSC Programmer's Reference Manual (c)2005-2011 (i.e. PIC24_InstructionSet.pdf) + +define endian=little; # little endian only + +@define dsPIC33E "1" + +@include "PIC24.sinc" diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/dsPIC33F.slaspec b/python/icicle/Ghidra/Processors/PIC/data/languages/dsPIC33F.slaspec new file mode 100644 index 0000000..a10e26a --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/dsPIC33F.slaspec @@ -0,0 +1,9 @@ +# This module defines Microchip PIC-24. + +# Based on "Microchip 16-bit MCU and DSC Programmer's Reference Manual (c)2005-2011 (i.e. PIC24_InstructionSet.pdf) + +define endian=little; # little endian only + +@define dsPIC33F "1" + +@include "PIC24.sinc" diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic12.sinc b/python/icicle/Ghidra/Processors/PIC/data/languages/pic12.sinc new file mode 100644 index 0000000..08eb48e --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic12.sinc @@ -0,0 +1,63 @@ +# +# PIC-12 Main Section +# includes constants, memory space and common register space definitions +# + +# STATUS bit definitions +@define STATUS_PA0_BIT 5 +@define STATUS_Z_BIT 2 +@define STATUS_DC_BIT 1 +@define STATUS_C_BIT 0 + +# STATUS bit masks used for setting +@define STATUS_PA_MASK 0x60 +@define STATUS_Z_MASK 0x04 +@define STATUS_DC_MASK 0x02 +@define STATUS_C_MASK 0x01 + +# STATUS bit masks used for clearing +@define STATUS_PA_CLEARMASK 0x9F +@define STATUS_Z_CLEARMASK 0xFB +@define STATUS_DC_CLEARMASK 0xFD +@define STATUS_C_CLEARMASK 0xFE + +@define FSR_BSEL_MASK 0x60 # FSR<5:6> Bank Select bits : Direct Addressing + +define endian=little; +define alignment=2; + +# Instruction Memory (ROM-based) +define space CODE type=ram_space wordsize=2 size=2 default; + +# General Purpose Register Memory consists of 2-banks of 32-bytes each +# Bank selection occurs using FSR bits <6:5> +define space DATA type=ram_space size=1; + +# HWSTACK consists of a 2-word by 12-bit RAM and a corresponding to a hidden stack pointer (STKPTR). +define space HWSTACK type=ram_space wordsize=2 size=1; # WORDSIZE is actually 12-bits + +define space register type=register_space size=2; + +# Program Counter (9-bits) - PC Latch: PCL +define register offset=0x0000 size=2 [ PC ]; + +# Stack Pointer +define register offset=0x0002 size=1 [ STKPTR ]; + +# Working register +define register offset=0x0003 size=1 [ W ]; + +# PC Latch register (real register is memory based) +define register offset=0x0004 size=1 [ PCL ]; + +# File Selection register (real register is memory based) +define register offset=0x0005 size=1 [ FSR ]; + +# STATUS register (real register is memory based) +define register offset=0x0006 size=1 [ STATUS ]; + +# Status bit registers (these do not really exist and must get reflected into the STATUS byte register) +define register offset=0x0007 size=1 [ PA Z DC C ]; + +# Option Register +define register offset=0x00b size=1 [ OPTION ]; diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic12_instructions.sinc b/python/icicle/Ghidra/Processors/PIC/data/languages/pic12_instructions.sinc new file mode 100644 index 0000000..6ae0ca2 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic12_instructions.sinc @@ -0,0 +1,624 @@ +# +# PIC-12 Instruction Section +# includes token definitions, macros, sub-constructors and instruction definitions +# + +# Little-endian bit numbering +define token instr16(16) + op12 = (0,11) + op6 = (6,11) + op4 = (8,11) + op3 = (9,11) + d = (5,5) + b3 = (5,7) + f5 = (0,4) + f5h = (4,4) + k8 = (0,7) + k9 = (0,8) +; + +# +# Unsupported Operations +# + +define pcodeop clearWatchDogTimer; + +define pcodeop sleep; + +# +# MACROS +# + +# Pack status bits into STATUS register +macro packStatus() { +# STATUS = (PA << $(STATUS_PA0_BIT)) +# | (Z << $(STATUS_Z_BIT)) +# | (DC << $(STATUS_DC_BIT)) +# | (C << $(STATUS_C_BIT)); +} + +# Unpack status bits from STATUS register +macro unpackStatus() { +# PA = (STATUS & $(STATUS_PA_MASK)) >> $(STATUS_PA0_BIT); +# Z = ((STATUS & $(STATUS_Z_MASK)) != 0); +# DC = ((STATUS & $(STATUS_DC_MASK)) != 0); +# C = ((STATUS & $(STATUS_C_MASK)) != 0); +} + +macro setResultFlags(result) { + Z = (result == 0); +} + +macro setAddCCarryFlag(op1,op2) { + C = (carry(op1,C) || carry(op2,op1 + C)); +} + +macro setAddCDigitCarryFlag(op1,op2) { + # op1 and op2 are assumed to be 8-bit values + local tmp1 = op1 << 4; + local tmp2 = op2 << 4; + DC = (carry(tmp1,DC) || carry(tmp2,tmp1 + DC)); +} + +macro setAddCFlags(op1,op2) { + setAddCCarryFlag(op1,op2); + setAddCDigitCarryFlag(op1,op2); +} + +macro setAddFlags(op1,op2) { + C = carry(op1,op2); + DC = carry(op1<<4,op2<<4); +} + +macro setSubtractCCarryFlag(op1,op2) { + local notC = ~C; + C = ((op1 < notC) || (op2 < (op1 - notC))); +} + +macro setSubtractCDigitCarryFlag(op1,op2) { + # op1 and op2 are assumed to be 8-bit values + local notDC = ~DC; + local tmp1 = op1 << 4; + local tmp2 = op2 << 4; + local tmp3 = (tmp1 - notDC) << 4; + DC = ((tmp1 < notDC) || (tmp2 < tmp3)); +} + +macro setSubtractCFlags(op1,op2) { + setSubtractCCarryFlag(op1,op2); + setSubtractCDigitCarryFlag(op1,op2); +} + +macro setSubtractFlags(op1,op2) { + # op1 and op2 are assumed to be 8-bit values + # NOTE: carry flag is SET if there is NO borrow + C = (op1 >= op2); + DC = ((op1<<4) < (op2<<4)); +} + +macro push(val) { # TODO: Uncertain about this !! + *[HWSTACK]:2 STKPTR = val; + STKPTR = STKPTR + 2; +} + +macro pop(val) { # TODO: Uncertain about this !! + STKPTR = STKPTR - 2; + val = *[HWSTACK]:2 STKPTR; +} + +# +# SUB-CONSTRUCTORS +# + +# File register index (f5!=0): bank selection determined by FSR<5:6> bits +fREGLoc: f5 is f5 { + addr:1 = (FSR & $(FSR_BSEL_MASK)) + f5; + export *[DATA]:1 addr; +} + +# File register index (f5=0): INDF use implies indirect data access using FSR value +fREGLoc: "INDF" is f5=0 { + addr:1 = FSR; # only low order 7-bits are used for indirect address + export *[DATA]:1 addr; +} + +# File register index : low 16-bytes of each bank always mapped to Bank-0 +fREGLoc: f5 is f5h=0x0 & f5 { export *[DATA]:1 f5; } + +# Special File Registers which have been mirrored into the register space +# to improve decompiler results +fREGLoc: "STATUS" is f5=0x03 { packStatus(); export STATUS; } +fREGLoc: "FSR" is f5=0x04 { export FSR; } +fREGLoc: "PCL" is f5=0x02 { export PCL; } + +# File register index (bank selection determined by RP bits in STATUS reg) +srcREG: fREGLoc is fREGLoc { export fREGLoc; } +#srcREG: "STATUS" is f5=0x03 { packStatus(); export STATUS; } +#srcREG: "FSR" is f5=0x04 { export FSR; } +srcREG: "PCL" is f5=0x02 { + # PCL and PA1:PA0 is latched + addr:2 = inst_start >> 1; # Compenstate for CODE wordsize + PCL = addr:1; + addr = (addr >> 9) & 0x3; + PA = addr:1; + export PCL; +} + +# Destination register (either srcREG or W) +destREG: "0" is d=0 { export W; } +destREG: "1" is d=1 & srcREG { export srcREG; } +#destREG: "1" is d=1 & f5=0x03 { export STATUS; } +#destREG: "1" is d=1 & f5=0x04 { export FSR; } +#destREG: "1" is d=1 & f5=0x02 { +# # Storing to PCL causes a branch, +# # PC<8> is always cleared for CALL and modifying instructions. +# # The MOVWF, ADDWF, BSF and BCF definition below has a specific case to handle this write to PCL +# export PCL; +#} +#destREG: "1" is d=1 & f5=0x00 & fREGLoc { +# # INDF use (indirect data access) +# export *[DATA]:1 fREGLoc; +#} + +# Destination operand representation (w: W register is destination; f: specified srcREG is destination) +D: "w" is d=0 { } +D: "f" is d=1 { } + +# Absolute addresses generated from k8 or k9 and STATUS.PA +absAddr8: k8 is k8 { + addr:2 = (zext(PA) << 9) + k8; + export addr; +} +absAddr9: k9 is k9 { + addr:2 = (zext(PA) << 9) + k9; + export addr; +} + +# Skip instruction address +skipInst: inst_skip is op12 [ inst_skip = inst_next + 1; ] {export *[CODE]:2 inst_skip; } + +# Immediate Data (Literal operation) +imm8: "#"k8 is k8 { export *[const]:1 k8; } + +# Bit identifier +bit: "#"b3 is b3 { export *[const]:1 b3; } + +# PC register write - instruction must set PC with PCLATH/PCL and perform branch operation +pcl: "PC" is f5=0x02 { export PCL; } + +# STATUS register +status: "STATUS" is f5=0x03 { export STATUS; } + +# +# BYTE-ORIENTED FILE REGISTER OPERATIONS +# + +:ADDWF srcREG, D is op6=0x07 & srcREG & D & destREG { + # ---- 0001 11df ffff + # 0000 0001 1100 0000 -> ADDWF INDF, 0 + # 0000 0001 1110 0000 -> ADDWF INDF, 1 + # 0000 0001 1101 0010 -> ADDWF 0x12, 0 + # 0000 0001 1111 0010 -> ADDWF 0x12, 1 + tmp:1 = srcREG; + setAddFlags(W, tmp); + tmp = W + tmp; + destREG = tmp; + setResultFlags(tmp); +} + +:ADDWF pcl, D is op6=0x07 & D & pcl { + # ---- 0001 11df ffff + # 0000 0001 1110 0010 -> ADDWF PCL, w, ACCESS + addr:2 = (inst_start >> 1) & 0x3f; # shift compenstates for CODE wordsize + tmpLo:1 = addr:1; + PA = addr(1); + setAddFlags(tmpLo, W); + tmpLo = tmpLo + W; + setResultFlags(tmpLo); + addr = (zext(PA) << 9) + zext(tmpLo); + PCL = tmpLo; + goto [addr]; +} + +:ANDLW imm8 is op4=0xe & imm8 { + # ---- 1110 kkkk kkkk + # 0000 1110 0001 0010 -> ANDLW #0x12 + W = W & imm8; + setResultFlags(W); +} + +:ANDWF srcREG, D is op6=0x05 & srcREG & D & destREG { + # ---- 0001 01df ffff + # 0000 0001 0100 0000 -> ANDWF INDF, 0 + # 0000 0001 0110 0000 -> ANDWF INDF, 1 + # 0000 0001 0101 0010 -> ANDWF 0x12, 0 + # 0000 0001 0111 0010 -> ANDWF 0x12, 1 + tmp:1 = W & srcREG; + destREG = tmp; + setResultFlags(tmp); +} + +:BCF srcREG, bit is op4=0x4 & bit & srcREG { + # ---- 0100 bbbf ffff + # 0000 0100 1000 0000 -> BCF INDF, #0x4 + # 0000 0100 1001 0010 -> BCF 0x12, #0x4 + local bitmask = ~(1 << bit); + srcREG = srcREG & bitmask; +} + +:BCF status, bit is op4=0x4 & b3=0 & bit & status { + # ---- 0100 bbbf ffff + # 0000 0100 0000 0000 -> BCF STATUS, #C + C = 0; + local bitmask = ~(1 << bit); + STATUS = STATUS & bitmask; +} + +:BCF status, bit is op4=0x4 & b3=1 & bit & status { + # ---- 0100 bbbf ffff + # 0000 0100 0010 0000 -> BCF STATUS, #DC + DC = 0; + local bitmask = ~(1 << bit); + STATUS = STATUS & bitmask; +} + +:BCF status, bit is op4=0x4 & b3=2 & bit & status { + # ---- 0100 bbbf ffff + # 0000 0100 0100 0000 -> BCF STATUS, #Z + Z = 0; + local bitmask = ~(1 << bit); + STATUS = STATUS & bitmask; +} + +:BCF status, bit is op4=0x4 & b3=5 & bit & status { + # ---- 0100 bbbf ffff + # 0000 0100 1010 0000 -> BCF STATUS, #PA0 + PA = PA & 0x1; + local bitmask = ~(1 << bit); + STATUS = STATUS & bitmask; +} + +:BCF status, bit is op4=0x4 & b3=6 & bit & status { + # ---- 0100 bbbf ffff + # 0000 0100 1100 0000 -> BCF STATUS, #PA1 + PA = PA & 0x2; + local bitmask = ~(1 << bit); + STATUS = STATUS & bitmask; +} + +:BSF srcREG, bit is op4=0x5 & bit & srcREG { + # ---- 0101 bbbf ffff + # 0000 0101 1000 0000 -> BSF INDF, #0x4 + # 0000 0101 1001 0010 -> BSF 0x12, #0x4 + local bitmask = 1 << bit; + srcREG = srcREG | bitmask; +} + +:BSF status, bit is op4=0x5 & b3=0 & bit & status { + # ---- 0101 bbbf ffff + # 0000 0101 0000 0000 -> BSF STATUS, #C + C = 1; + local bitmask = 1 << bit; + STATUS = STATUS | bitmask; +} + +:BSF status, bit is op4=0x5 & b3=1 & bit & status { + # ---- 0101 bbbf ffff + # 0000 0101 0010 0000 -> BSF STATUS, #DC + DC = 1; + local bitmask = 1 << bit; + STATUS = STATUS | bitmask; +} + +:BSF status, bit is op4=0x5 & b3=2 & bit & status { + # ---- 0101 bbbf ffff + # 0000 0101 0100 0000 -> BSF STATUS, #Z + Z = 1; + local bitmask = 1 << bit; + STATUS = STATUS | bitmask; +} + +:BSF status, bit is op4=0x5 & b3=5 & bit & status { + # ---- 0101 bbbf ffff + # 0000 0101 1010 0000 -> BSF STATUS, #PA0 + PA = PA | 0x1; + local bitmask = 1 << bit; + STATUS = STATUS | bitmask; +} + +:BSF status, bit is op4=0x5 & b3=6 & bit & status { + # ---- 0101 bbbf ffff + # 0000 0101 1100 0000 -> BSF STATUS, #PA1 + PA = PA | 0x2; + local bitmask = 1 << bit; + STATUS = STATUS | bitmask; +} + +:BTFSC srcREG, bit is op4=0x6 & bit & srcREG & skipInst { + # ---- 0110 bbbf ffff + # 0000 0110 1000 0000 -> BTFSC INDF, #0x4 + # 0000 0110 1001 0010 -> BTFSC 0x12, #0x4 + local bitmask = 1 << bit; + local tmp = srcREG & bitmask; + if (tmp == 0) goto skipInst; +} + +:BTFSC status, bit is op4=0x6 & b3=0 & bit & status & skipInst { + # ---- 0110 bbbf ffff + # 0000 0110 0000 0000 -> BTFSC STATUS, #C + if (C == 0) goto skipInst; +} + +:BTFSC status, bit is op4=0x6 & b3=1 & bit & status & skipInst { + # ---- 0110 bbbf ffff + # 0000 0110 0010 0000 -> BTFSC STATUS, #DC + if (DC == 0) goto skipInst; +} + +:BTFSC status, bit is op4=0x6 & b3=2 & bit & status & skipInst { + # ---- 0110 bbbf ffff + # 0000 0110 0100 0000 -> BTFSC STATUS, #Z + if (Z == 0) goto skipInst; +} + +:BTFSS srcREG, bit is op4=0x7 & bit & srcREG & skipInst { + # ---- 0111 bbbf ffff + # 0000 0111 1000 0000 -> BTFSS INDF, #0x4 + # 0000 0111 1001 0010 -> BTFSS 0x12, #0x4 + local bitmask = 1 << bit; + local tmp = srcREG & bitmask; + if (tmp != 0) goto skipInst; +} + +:BTFSS status, bit is op4=0x7 & b3=0 & bit & status & skipInst { + # ---- 0111 bbbf ffff + # 0000 0111 0000 0000 -> BTFSS STATUS, #C + if (C != 0) goto skipInst; +} + +:BTFSS status, bit is op4=0x7 & b3=1 & bit & status & skipInst { + # ---- 0111 bbbf ffff + # 0000 0111 0010 0000 -> BTFSS STATUS, #DC + if (DC != 0) goto skipInst; +} + +:BTFSS status, bit is op4=0x7 & b3=2 & bit & status & skipInst { + # ---- 0111 bbbf ffff + # 0000 0111 0100 0000 -> BTFSS STATUS, #Z + if (Z != 0) goto skipInst; +} + +:CALL absAddr8 is op4=0x9 & absAddr8 { + # ---- 1001 kkkk kkkk + # 0000 1001 0010 0011 -> CALL 0x23 + # 0000 1001 0001 0000 -> CALL 0x10 + push(&:2 inst_next); + call [absAddr8]; +} + +:CLRF srcREG is op6=0x01 & d=1 & srcREG { + # ---- 0000 011f ffff + # 0000 0000 0110 0000 -> CLRF INDF + # 0000 0000 0111 0010 -> CLRF 0x12 + srcREG = 0; + Z = 1; +} + +:CLRW is op6=0x01 & d=0 & f5=0 { + # ---- 0000 0100 0000 + # 0000 0001 0000 0000 -> CLRW + W = 0; + Z = 1; +} + +:CLRWDT is op12=0x0004 { + # ---- 0000 0000 0100 + # Clear Watchdog Timer - Not Implemented + clearWatchDogTimer(); +} + +:COMF srcREG, D is op6=0x09 & srcREG & D & destREG { + # ---- 0010 01df ffff + # 0000 0010 0100 0000 -> COMF INDF, 0 + # 0000 0010 0110 0000 -> COMF INDF, 1 + # 0000 0010 0101 0010 -> COMF 0x12, 0 + # 0000 0010 0111 0010 -> COMF 0x12, 1 + tmp:1 = ~srcREG; + destREG = tmp; + setResultFlags(tmp); +} + +:DECF srcREG, D is op6=0x03 & srcREG & D & destREG { + # ---- 0000 11df ffff + # 0000 0000 1100 0000 -> DECF INDF, 0 + # 0000 0000 1110 0000 -> DECF INDF, 1 + # 0000 0000 1101 0010 -> DECF 0x12, 0 + # 0000 0000 1111 0010 -> DECF 0x12, 1 + tmp:1 = srcREG - 1; + destREG = tmp; + setResultFlags(tmp); +} + +:DECFSZ srcREG, D is op6=0x0b & srcREG & D & destREG & skipInst { + # ---- 0010 11df ffff + # 0000 0010 1100 0000 -> DECFSZ INDF, 0 + # 0000 0010 1110 0000 -> DECFSZ INDF, 1 + # 0000 0010 1101 0010 -> DECFSZ 0x12, 0 + # 0000 0010 1111 0010 -> DECFSZ 0x12, 1 + tmp:1 = srcREG - 1; + destREG = tmp; + if (tmp == 0) goto skipInst; +} + +:GOTO absAddr9 is op3=0x5 & absAddr9 { + # ---- 101k kkkk kkkk + # 0000 1011 0010 0011 -> GOTO 0x123 + # 0000 1010 0001 0000 -> GOTO 0x10 + goto [absAddr9]; +} + +:INCF srcREG, D is op6=0x0a & srcREG & D & destREG { + # ---- 0010 10df ffff + # 0000 0010 1000 0000 -> INCF INDF, 0 + # 0000 0010 1010 0000 -> INCF INDF, 1 + # 0000 0010 1001 0010 -> INCF 0x12, 0 + # 0000 0010 1011 0010 -> INCF 0x12, 1 + tmp:1 = srcREG + 1; + destREG = tmp; + setResultFlags(tmp); +} + +:INCFSZ srcREG, D is op6=0x0f & srcREG & D & destREG & skipInst { + # ---- 0011 11df ffff + # 0000 0011 1100 0000 -> INCFSZ INDF, 0 + # 0000 0011 1110 0000 -> INCFSZ INDF, 1 + # 0000 0011 1101 0010 -> INCFSZ 0x12, 0 + # 0000 0011 1111 0010 -> INCFSZ 0x12, 1 + tmp:1 = srcREG + 1; + destREG = tmp; + if (tmp == 0) goto skipInst; +} + +:IORLW imm8 is op4=0xd & imm8 { + # ---- 1101 kkkk kkkk + # 0000 1101 0001 0010 -> IORLW #0x12 + W = W | imm8; + setResultFlags(W); +} + +:IORWF srcREG, D is op6=0x04 & srcREG & D & destREG { + # ---- 0001 00df ffff + # 0000 0001 0000 0000 -> IORWF INDF, 0 + # 0000 0001 0010 0000 -> IORWF INDF, 1 + # 0000 0001 0001 0010 -> IORWF 0x20, 0 + # 0000 0001 0011 0010 -> IORWF 0x20, 1 + tmp:1 = W | srcREG; + destREG = tmp; + setResultFlags(tmp); +} + +:MOVLW imm8 is op4=0xc & imm8 { + # ---- 1100 kkkk kkkk + # 0000 1100 0001 0010 -> MOVLW #0x12 + W = imm8; +} + +:MOVF srcREG, D is op6=0x08 & srcREG & D & destREG { + # ---- 0010 00df ffff + # 0000 0010 0000 0000 -> MOVF INDF, 0 + # 0000 0010 0010 0000 -> MOVF INDF, 1 + # 0000 0010 0001 0010 -> MOVF 0x12, 0 + # 0000 0010 0011 0010 -> MOVF 0x12, 1 + tmp:1 = srcREG; + destREG = tmp; + setResultFlags(tmp); +} + +:MOVWF srcREG is op6=0x00 & d=1 & srcREG { + # ---- 0000 001f ffff + # 0000 0000 0010 0000 -> MOVWF INDF + # 0000 0000 0011 0010 -> MOVWF 0x12 + srcREG = W; +} + +:MOVWF pcl is op6=0x00 & pcl { + # ---- 0000 001f ffff + # 0000 0000 0010 0010 -> MOVWF PCL + PCL = W; + addr:2 = (zext(PA) << 9) + zext(PCL); + goto [addr]; +} + +:NOP is op12=0x00 { + # ---- 0000 0000 0000 +} + +:OPTION is op12=0x0002 { + # ---- 0000 0000 0010 + OPTION = W; +} + +:RETLW imm8 is op4=0x8 & imm8 { + # ---- 1000 kkkk kkkk + # 0000 1000 0001 0010 -> RETLW #0x12 + W = imm8; + retAddr:2 = 0; + pop(retAddr); + return [retAddr]; +} + +:RLF srcREG, D is op6=0x0d & srcREG & D & destREG { + # ---- 0011 01df ffff + # 0000 0011 0100 0000 -> RLF INDF, 0 + # 0000 0011 0110 0000 -> RLF INDF, 1 + # 0000 0011 0101 0010 -> RLF 0x12, 0 + # 0000 0011 0111 0010 -> RLF 0x12, 1 + local tmpC = C; + tmp:1 = srcREG; + C = (tmp s< 0); + tmp = (tmp << 1) | tmpC; + destREG = tmp; + setResultFlags(tmp); +} + +:RRF srcREG, D is op6=0x0c & srcREG & D & destREG { + # ---- 0011 00df ffff + # 0000 0011 0000 0000 -> RRF INDF, 0 + # 0000 0011 0010 0000 -> RRF INDF, 1 + # 0000 0011 0001 0010 -> RRF 0x12, 0 + # 0000 0011 0011 0010 -> RRF 0x12, 1 + local tmpC = C << 7; + tmp:1 = srcREG; + C = (tmp & 1) != 0; + tmp = (tmp >> 1) | tmpC; + destREG = tmp; + setResultFlags(tmp); +} + +:SLEEP is op12=0x0003 { + # ---- 0000 0000 0011 + # Sleep - Not Implemented + sleep(); +} + +:SUBWF srcREG, D is op6=0x02 & srcREG & D & destREG { + # ---- 0000 10df ffff + # 0000 0000 1000 0000 -> SUBWF INDF, 0 + # 0000 0000 1010 0000 -> SUBWF INDF, 1 + # 0000 0000 1001 0010 -> SUBWF 0x12, 0 + # 0000 0000 1011 0010 -> SUBWF 0x12, 1 + tmp:1 = srcREG; + setSubtractFlags(tmp, W); + tmp = tmp - W; + destREG = tmp; + setResultFlags(tmp); +} + +:SWAPF srcREG, D is op6=0x0e & srcREG & D & destREG { + # ---- 0011 10df ffff + # 0000 0011 1000 0000 -> SUBWF INDF, 0 + # 0000 0011 1010 0000 -> SUBWF INDF, 1 + # 0000 0011 1001 0010 -> SUBWF 0x12, 0 + # 0000 0011 1011 0010 -> SUBWF 0x12, 1 + tmp:1 = srcREG; + destREG = (tmp << 4) | (tmp >> 4); +} + +:XORLW imm8 is op4=0xf & imm8 { + # ---- 1111 kkkk kkkk + # 0000 1111 0001 0010 -> XORLW #0x12 + W = imm8 ^ W; + setResultFlags(W); +} + +:XORWF srcREG, D is op6=0x06 & srcREG & D & destREG { + # ---- 0001 10df ffff + # 0000 0001 1000 0000 -> XORWF INDF, 0 + # 0000 0001 1010 0000 -> XORWF INDF, 1 + # 0000 0001 1001 0010 -> XORWF 0x12, 0 + # 0000 0001 1011 0010 -> XORWF 0x12, 1 + tmp:1 = W ^ srcREG; + destREG = tmp; + setResultFlags(tmp); +} + diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic12c5xx.cspec b/python/icicle/Ghidra/Processors/PIC/data/languages/pic12c5xx.cspec new file mode 100644 index 0000000..7de2963 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic12c5xx.cspec @@ -0,0 +1,40 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic12c5xx.ldefs b/python/icicle/Ghidra/Processors/PIC/data/languages/pic12c5xx.ldefs new file mode 100644 index 0000000..884846f --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic12c5xx.ldefs @@ -0,0 +1,17 @@ + + + + + PIC-12C5xx + + + + diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic12c5xx.pspec b/python/icicle/Ghidra/Processors/PIC/data/languages/pic12c5xx.pspec new file mode 100644 index 0000000..7cb5971 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic12c5xx.pspec @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic12c5xx.slaspec b/python/icicle/Ghidra/Processors/PIC/data/languages/pic12c5xx.slaspec new file mode 100644 index 0000000..b20bed1 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic12c5xx.slaspec @@ -0,0 +1,28 @@ +@define PROCESSOR "PIC_12C5XX" + +@include "pic12.sinc" + +# +# NOTES - +# 1. If a specific PIC-12 has a different register set, this file and the pic12c5xx.specl file may be copied/renamed and +# slightly modified to specify a the correct Register File Map. +# + +# Bank-0 File Registers +define DATA offset=0x00 size=1 [ + INDF TMR0 PCL.0 STATUS.0 FSR.0 OSCCAL GPIO +]; + +@include "pic12_instructions.sinc" + +# IO Tristate Register +define register offset=0x0020 size=1 [ TRIS ]; + +# TRIS register +trisREG: "6" is f5=0x6 { export TRIS; } + +:TRIS trisREG is op6=0x00 & d=0 & trisREG { + # ---- 0000 0000 0fff + # 0000 0000 0000 0110 -> TRIS 6 + trisREG = W; +} diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic16.cspec b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16.cspec new file mode 100644 index 0000000..edc5273 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16.cspec @@ -0,0 +1,45 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic16.ldefs b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16.ldefs new file mode 100644 index 0000000..af82b20 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16.ldefs @@ -0,0 +1,31 @@ + + + + + PIC-16(C,CR)XXX + + + + + + PIC-16F(L)XXX + + + + diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic16.pspec b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16.pspec new file mode 100644 index 0000000..4133f95 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16.pspec @@ -0,0 +1,96 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic16.sinc b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16.sinc new file mode 100644 index 0000000..d7144da --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16.sinc @@ -0,0 +1,95 @@ +# +# PIC-16 Main Section +# includes constants, memory space and common register space definitions +# + +# STATUS bit definitions +@define STATUS_IRP_BIT 7 +@define STATUS_RP0_BIT 5 +@define STATUS_Z_BIT 2 +@define STATUS_DC_BIT 1 +@define STATUS_C_BIT 0 + +# STATUS bit masks used for setting +@define STATUS_IRP_MASK 0x80 +@define STATUS_RP_MASK 0x60 +@define STATUS_Z_MASK 0x04 +@define STATUS_DC_MASK 0x02 +@define STATUS_C_MASK 0x01 + +# STATUS bit masks used for clearing +@define STATUS_IRP_CLEARMASK 0x7F +@define STATUS_RP_CLEARMASK 0x9F +@define STATUS_Z_CLEARMASK 0xFB +@define STATUS_DC_CLEARMASK 0xFD +@define STATUS_C_CLEARMASK 0xFE + +define endian=little; +define alignment=2; + +# Instruction Memory (ROM-based) +define space CODE type=ram_space wordsize=2 size=2 default; + +# General Purpose Register Memory consists of 4-banks of 255-bytes for PIC16, +# or 32-banks of 255 bytes each for PIC_16F. +# Bank selection occurs using STATUS register bits RP0 & RP1 +define space DATA type=ram_space size=2; + +# HWSTACK consists of a 8-word by 13-bit RAM and a corresponding to a hidden stack pointer (STKPTR). +define space HWSTACK type=ram_space wordsize=2 size=1; # WORDSIZE is actually 13-bits + +define space register type=register_space size=2; + +# Program Counter (13-bits) - PC Latch: PCLATH / PCL +define register offset=0x0000 size=2 [ PC ]; + +# Stack Pointer +define register offset=0x0002 size=1 [ STKPTR ]; + +# Working register +define register offset=0x0003 size=1 [ W SkipNext ]; + +# Status bit registers (these do not really exist and must get reflected into the STATUS byte register) +@if PROCESSOR == "PIC_16" +define register offset=0x0007 size=1 [ IRP RP ]; +@elif PROCESSOR == "PIC_16F" +define register offset=0x0007 size=1 [ IRP RP ]; +@endif + +@define C "STATUS[0,1]" +@define DC "STATUS[1,1]" +@define Z "STATUS[2,1]" +@define PD "STATUS[3,1]" +@define TO "STATUS[4,1]" +@define PA0 "STATUS[5,1]" + +# +# WARNING! - Reflection of these DATA-based registers with the corresponding register +# is not fully implemented due to the complexity of doing so within this language specification. +# Reflection of certain registers (e.g., STATUS) within other memory banks is also not modeled. +# +# NOTES - +# 1. Chips with voltage comparator and reference functions may replace A/D registers (ADCON0 and ADCON1) with (VMCON and VRCON) +# Instances of this include PIC16F627A/628A/648A (there could be others) +# 2. If a specific PIC-16 has a different register set, this file and the pic16.pspec file may be copied/renamed and +# slightly modified to specify a the correct Register File Map. +# + +# +# Bank-0 File Registers +# +@if PROCESSOR == "PIC_16" +define DATA offset=0x0000 size=1 [ + INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H +]; + +@elif PROCESSOR == "PIC_16F" +define DATA offset=0x0000 size=1 [ + INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON _ _ _ _ +]; + +define DATA offset=0x0004 size=2 [ FSR0 FSR1 ]; + +@endif + +# Additional Data Bank data registers are defined in the .PSPEC file. diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic16.slaspec b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16.slaspec new file mode 100644 index 0000000..ca116f1 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16.slaspec @@ -0,0 +1,5 @@ +@define PROCESSOR "PIC_16" + +@include "pic16.sinc" + +@include "pic16_instructions.sinc" diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic16_instructions.sinc b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16_instructions.sinc new file mode 100644 index 0000000..5dda8d7 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16_instructions.sinc @@ -0,0 +1,969 @@ +# +# PIC-16 Instruction Section +# includes token definitions, macros, sub-constructors and instruction definitions +# +# PC register write - instruction must set PC with PCLATH/PCL and perform branch operation + +# Little-endian bit numbering +define token instr16(16) + op14 = (0,13) + op12 = (2,13) + op11 = (3,13) + op9 = (5,13) + op7 = (7,13) + op6 = (8,13) + op5 = (9,13) + op4 = (10,13) + op3 = (11,13) + d = (7,7) + b3 = (7,9) + IntConBits = (7,9) + StatusBit = (7,9) + f7 = (0,6) + lf7 = (0,3) + uf7 = (4,6) + fsr = (2,2) + fsrk = (6,6) + fregCore = (0,3) + k5 = (0,4) + k7 = (0,6) + k8 = (0,7) + sk9 = (0,8) signed + k11 = (0,10) + sk6 = (0,5) signed + l5 = (0,4) # low order 5-bits of instr16 + mm = (0,1) +; + +define register offset=0x100 size=4 contextreg; +define context contextreg + doPseudo = (0,0) + possibleSkip = (1,1) noflow +; + + +@if PROCESSOR == "PIC_16" +attach variables [ fregCore ] [ + INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON _ _ _ _ +]; + +@elif PROCESSOR == "PIC_16F" +attach variables [ fregCore ] [ + INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR W PCLATH INTCON _ _ _ _ +]; + +attach names [IntConBits] [ IOCIF INTF TMR0IF IOCIE INTE TMR0IE PEIE GIE ]; + +attach variables [ fsr fsrk ] [ FSR0 FSR1 ]; + +@endif + +# +# Unsupported Operations +# + +define pcodeop clearWatchDogTimer; + +define pcodeop sleep; +define pcodeop reset; + +# +# MACROS +# + +# Pack status bits into STATUS register +macro packStatus() { +# STATUS = (IRP << $(STATUS_IRP_BIT)) +# | (RP << $(STATUS_RP0_BIT)) +# | (Z << $(STATUS_Z_BIT)) +# | (DC << $(STATUS_DC_BIT)) +# | (C << $(STATUS_C_BIT)); +} + +# Unpack status bits from STATUS register +macro unpackStatus() { +# IRP = ((STATUS & $(STATUS_IRP_MASK)) != 0); +# RP = (STATUS & $(STATUS_RP_MASK)) >> $(STATUS_RP0_BIT); +# Z = ((STATUS & $(STATUS_Z_MASK)) != 0); +# DC = ((STATUS & $(STATUS_DC_MASK)) != 0); +# C = ((STATUS & $(STATUS_C_MASK)) != 0); +} + +macro setResultFlags(result) { + $(Z) = (result == 0); +} + +macro setAddCCarryFlag(op1,op2) { + local tc = $(C); + $(C) = (carry(op1,tc) || carry(op2,op1 + tc)); +} + +macro setAddCDigitCarryFlag(op1,op2) { + # op1 and op2 are assumed to be 8-bit values + local tmp1 = op1 << 4; + local tmp2 = op2 << 4; + local tdc = $(DC); + $(DC) = (carry(tmp1,tdc) || carry(tmp2,tmp1 + tdc)); +} + +macro setAddCFlags(op1,op2) { + setAddCCarryFlag(op1,op2); + setAddCDigitCarryFlag(op1,op2); +} + +macro setAddFlags(op1,op2) { + $(C)= carry(op1,op2); + $(DC) = carry(op1<<4,op2<<4); +} + +macro setSubtractCCarryFlag(op1,op2) { + local tc = $(C); + local notC = !tc; + $(C) = op2 >= !tc & op1 >= (op2 - !tc); +} + +macro setSubtractCDigitCarryFlag(op1,op2) { + # op1 and op2 are assumed to be 8-bit values + local notDC = ~$(DC); + local tmp1 = op1 << 4; + local tmp2 = op2 << 4; + local tmp3 = (tmp1 - notDC) << 4; + $(DC) = ((tmp1 < notDC) || (tmp2 < tmp3)); +} + +macro setSubtractCFlags(op1,op2) { + setSubtractCCarryFlag(op1,op2); + setSubtractCDigitCarryFlag(op1,op2); +} + +macro setSubtractFlags(op1,op2) { + # op1 and op2 are assumed to be 8-bit values + # NOTE: carry flag is SET if there is NO borrow + $(C) = (op1 >= op2); + $(DC) = ((op1<<4) < (op2<<4)); +} + +macro push(val) { # TODO: Uncertain about this !! + *[HWSTACK]:2 STKPTR = val; + STKPTR = STKPTR + 2; +} + +macro pop(val) { # TODO: Uncertain about this !! + STKPTR = STKPTR - 2; + val = *[HWSTACK]:2 STKPTR; +} + +# +# SUB-CONSTRUCTORS +# + +# File register index (f7!=0): bank selection determined by RP bits in STATUS reg +@if PROCESSOR == "PIC_16" +srcREG: f7 is f7 { + addr:2 = (zext(RP) << 7) + f7; + export *[DATA]:1 addr; +} +@elif PROCESSOR == "PIC_16F" +srcREG: f7 is f7 { + addr:2 = (zext(BSR) << 7) + f7; + export *[DATA]:1 addr; +} +@endif + +# Top 16 bytes are shared RAM on PIC16 and PIC16F +srcREG: fv is uf7=0x7 & lf7 [fv = 0x70 + lf7; ] { + addr:2 = fv; + export *[DATA]:1 addr; +} + +# File register index (f7=0): INDF use implies indirect data access using FSR value and IRP bit in STATUS reg +@if PROCESSOR == "PIC_16" +srcREG: fregCore is f7=0 & fregCore { + addr:2 = (zext(IRP) << 8) + zext(FSR); + export *[DATA]:1 addr; +} +srcREG: fregCore is f7=1 & fregCore { + rpval:2 = zext(RP == 1) + zext(RP == 2); + addr:2 = (zext(rpval) << 7) + 1; + export *[DATA]:1 addr; +} +@elif PROCESSOR == "PIC_16F" +srcREG: fregCore is f7=0 & fregCore { + addr:2 = FSR0; + export *[DATA]:1 addr; +} + +srcREG: fregCore is f7=1 & fregCore { + addr:2 = FSR1; + export *[DATA]:1 addr; +} +@endif + +# Special File Registers always mapped to Bank-0 +srcREG: fregCore is f7=0x02 & fregCore { + # PCL and PCLATH must be latched + addr:2 = inst_start >> 1; # Compensate for CODE wordsize + PCL = addr:1; + PCLATH = addr(1); + export PCL; +} + +srcREG: fregCore is f7=0x03 & fregCore { export fregCore; } +srcREG: fregCore is f7=0x04 & fregCore { export fregCore; } +@if PROCESSOR == "PIC_16F" +srcREG: fregCore is f7=0x05 & fregCore { export fregCore; } +srcREG: fregCore is f7=0x06 & fregCore { export fregCore; } +srcREG: fregCore is f7=0x07 & fregCore { export fregCore; } +srcREG: fregCore is f7=0x08 & fregCore { export fregCore; } +srcREG: fregCore is f7=0x09 & fregCore { export fregCore; } +@endif +srcREG: fregCore is f7=0x0a & fregCore { export fregCore; } +srcREG: fregCore is f7=0x0b & fregCore { export fregCore; } + + +# Destination register (either srcREG or W) +destREG: "0" is d=0 { export W; } + +# Destination register: bank selection determined by RP bits in STATUS reg +destREG: "1" is d=1 & f7 & srcREG { export srcREG; } + +# Destination register: Special File Registers always mapped to Bank-0 +destREG: "1" is d=1 & f7=0x02 & fregCore { export fregCore; } # PCL (special behavior reqd) + +# Destination operand representation (w: W register is destination; f: specified srcREG is destination) +D: "w" is d=0 { } +D: "f" is d=1 { } + +# Absolute address generated from k11 and PCLATH<4:3> +absAddr11: k11 is k11 { + addr:2 = ((zext(PCLATH) & 0x78) << 8) + k11; + export addr; +} + +@if PROCESSOR == "PIC_16F" + +# Absolute address generated from k11 and PCLATH<4:3> +relAddr9: addr is sk9 [ addr = inst_next + sk9; ] { + export *[CODE]:2 addr; +} + +@endif + +# Immediate Data (Literal operation) +imm8: "#"k8 is k8 { export *[const]:1 k8; } + +@if PROCESSOR == "PIC_16F" +# Immediate Data (Literal operation) +imm7: "#"k7 is k7 { export *[const]:1 k7; } + +# Immediate Data (Literal operation) +imm5: "#"k5 is k5 { export *[const]:1 k5; } +@endif + +# Bit identifier +bit: "#"b3 is b3 { export *[const]:1 b3; } + +# TRIS register (TODO: not sure if this TRIS mapping is correct - see TRIS instruction) +@if PROCESSOR == "PIC_16" +trisREG: "5" is l5=5 { local trl:2 = 0x89; export *[DATA]:1 trl; } # TRISA +trisREG: "6" is l5=6 { local trl:2 = 0x187; export *[DATA]:1 trl; } # TRISB +trisREG: "7" is l5=7 { local trl:2 = 0x188; export *[DATA]:1 trl; } # TRISC +@elif PROCESSOR == "PIC_16F" +trisREG: "5" is l5=5 { local trl:2 = 0x10C; export *[DATA]:1 trl; } # TRISA +trisREG: "6" is l5=6 { local trl:2 = 0x10D; export *[DATA]:1 trl; } # TRISB +trisREG: "7" is l5=7 { local trl:2 = 0x10E; export *[DATA]:1 trl; } # TRISC +@endif + +:^instruction is possibleSkip=1 & instruction [ possibleSkip=0; ] { + if (SkipNext) goto inst_next; + build instruction; +} + + + +# +# BYTE-ORIENTED FILE REGISTER OPERATIONS +# + +@if PROCESSOR == "PIC_16F" + +:ADDFSR fsrk, sk6 is op7=0x62 & fsrk & sk6 { + fsrk = fsrk + sk6; +} +@endif + +:ADDLW imm8 is op6=0x3e & imm8 { + # --11 111x kkkk kkkk + # 0011 1110 0001 0010 -> ADDLW #0x12 + setAddFlags(W, imm8); + W = W + imm8; + setResultFlags(W); +} + +:ADDWF srcREG, D is op6=0x07 & srcREG & D & destREG { + # --00 0111 dfff ffff + # 0000 0111 0000 0000 -> ADDWF INDF, 0 + # 0000 0111 1000 0000 -> ADDWF INDF, 1 + # 0000 0111 0010 0000 -> ADDWF 0x20, 0 + # 0000 0111 1010 0000 -> ADDWF 0x20, 1 + val:1 = srcREG; + setAddFlags(W, val); + val = W + val; + setResultFlags(val); + destREG = val; +} + +:ADDWF PC, D is op6=0x07 & D & d=1 & f7=0x02 & PC { + # --00 0111 dfff ffff + # 0000 0111 1000 0010 -> ADDWF PCL, w, ACCESS + addr:2 = inst_start >> 1; # Compenstate for CODE wordsize + PCLATH = addr(1); + tmp:1 = addr:1; + setAddFlags(tmp, W); + tmp = tmp + W; + addr = (zext(PCLATH) << 8) + zext(tmp); + PCL = tmp; + setResultFlags(tmp); + goto [addr]; +} + +:ADDWFC srcREG, D is op6=0x3D & srcREG & D & destREG { + val:1 = srcREG; + local tmpC = $(C); + + setAddFlags(W, val); + val = W + val; + local tc = $(C); + + setAddFlags(val,tmpC); + $(C) = $(C) | tc; + val = val + tmpC; + + setResultFlags(val); + destREG = val; +} + +:ADDWFC PC, D is op6=0x3D & D & d=1 & f7=0x02 & PC { + # --00 0111 dfff ffff + # 0000 0111 1000 0010 -> ADDWF PCL, w, ACCESS + addr:2 = inst_start >> 1; # Compenstate for CODE wordsize + PCLATH = addr(1); + val:1 = addr:1; + + local tmpC = $(C); + setAddFlags(W, val); + local tc = $(C); + val = W + val; + + setAddFlags(val,tmpC); + $(C) = $(C) | tc; + val = val + tmpC; + + addr = (zext(PCLATH) << 8) + zext(val); + PCL = val; + setResultFlags(val); + goto [addr]; +} + +:ANDLW imm8 is op6=0x39 & imm8 { + # --11 1001 kkkk kkkk + # 0011 1001 0001 0010 -> ANDLW #0x12 + W = W & imm8; + setResultFlags(W); +} + +:ANDWF srcREG, D is op6=0x05 & srcREG & D & destREG { + # --00 0101 dfff ffff + # 0000 0101 0000 0000 -> ANDWF INDF, 0 + # 0000 0101 1000 0000 -> ANDWF INDF, 1 + # 0000 0101 0010 0000 -> ANDWF 0x20, 0 + # 0000 0101 1010 0000 -> ANDWF 0x20, 1 + val:1 = srcREG; + val = W & val; + setResultFlags(val); + destREG = val; +} + +:ASRF srcREG, D is op6=0x37 & srcREG & D & destREG { + # --11 0111 dfff ffff + $(C) = srcREG & 0x1; + val:1 = srcREG s>> 1; + setResultFlags(val); + destREG = val; +} + +:BCF srcREG, bit is op4=0x4 & srcREG & bit { + # --01 00bb bfff ffff + # 0001 0010 0000 0000 -> BCF INDF, #0x4 + # 0001 0010 0010 0000 -> BCF 0x20, #0x4 + local bitmask = ~(1 << bit); + srcREG = srcREG & bitmask; +} + + +:BCF srcREG, IntConBits is op4=0x4 & f7=0xb & bit & srcREG & IntConBits { + local bitmask = ~(1 << bit); + srcREG = srcREG & bitmask; +} + +:BCF STATUS, "C" is op4=0x4 & b3=0 & f7=0x3 & STATUS { + # --01 00bb bfff ffff + # 0001 0000 0000 0011 -> BCF STATUS, #C + $(C) = 0; +} + +:BCF STATUS, "DC" is op4=0x4 & b3=1 & f7=0x3 & STATUS & bit { + # --01 00bb bfff ffff + # 0001 0000 1000 0011 -> BCF STATUS, #DC + $(DC) = 0; +} + + +:BCF STATUS, "Z" is op4=0x4 & b3=2 & f7=0x3 & STATUS & bit { + # --01 00bb bfff ffff + # 0001 0001 0000 0011 -> BCF STATUS, #Z + $(Z) = 0; +} + + +:BCF STATUS, "RP0" is op4=0x4 & b3=5 & f7=0x3 & STATUS & bit { + # --01 00bb bfff ffff + # 0001 0010 1000 0011 -> BCF STATUS, #RP0 + RP = RP & 0x2; + local bitmask = ~(1 << bit); + STATUS = STATUS & bitmask; +} + + +:BCF STATUS, "RP1" is op4=0x4 & b3=6 & f7=0x3 & STATUS & bit { + # --01 00bb bfff ffff + # 0001 0011 0000 0011 -> BCF STATUS, #RP1 + RP = RP & 0x1; + local bitmask = ~(1 << bit); + STATUS = STATUS & bitmask; +} + + +:BCF STATUS, "IRP" is op4=0x4 & b3=7 & f7=0x3 & STATUS & bit { + # --01 00bb bfff ffff + # 0001 0011 1000 0011 -> BCF STATUS, #IRP + IRP = 0; + local bitmask = ~(1 << bit); + STATUS = STATUS & bitmask; +} + +:BSF srcREG, bit is op4=0x5 & bit & srcREG { + # --01 01bb bfff ffff + # 0001 0110 0000 0000 -> BSF INDF, #0x4 + # 0001 0110 0010 0000 -> BSF 0x20, #0x4 + local bitmask = 1 << bit; + srcREG = srcREG | bitmask; +} + +:BSF srcREG, IntConBits is op4=0x5 & f7=0xb & bit & srcREG & IntConBits { + local bitmask = 1 << bit; + srcREG = srcREG | bitmask; +} + +:BSF STATUS, "C" is op4=0x5 & b3=0 & f7=0x3 & STATUS { + # --01 01bb bfff ffff + # 0001 0100 0000 0011 -> BSF STATUS, #C + $(C) = 1; +} + +:BSF STATUS, "DC" is op4=0x5 & b3=1 & f7=0x3 & STATUS { + # --01 01bb bfff ffff + # 0001 0100 1000 0011 -> BSF STATUS, #DC + $(DC) = 1; +} + +:BSF STATUS, "Z" is op4=0x5 & b3=2 & f7=0x3 & STATUS & bit { + # --01 01bb bfff ffff + # 0001 0111 0000 0011 -> BSF STATUS, #Z + $(Z) = 1; +} + +:BSF STATUS, "RP0" is op4=0x5 & b3=5 & f7=0x3 & STATUS & bit { + # --01 01bb bfff ffff + # 0001 0110 1000 0011 -> BSF STATUS, #RP0 + RP = RP | 0x1; + local bitmask = 1 << bit; + STATUS = STATUS | bitmask; +} + +:BSF STATUS, "RP1" is op4=0x5 & b3=6 & f7=0x3 & STATUS & bit { + # --01 01bb bfff ffff + # 0001 0111 0000 0011 -> BSF STATUS, #RP1 + RP = RP | 0x2; + local bitmask = 1 << bit; + STATUS = STATUS | bitmask; +} + + +:BSF STATUS, "IRP" is op4=0x5 & b3=7 & f7=0x3 & STATUS & bit { + # --01 01bb bfff ffff + # 0001 0111 1000 0011 -> BSF STATUS, #IRP + IRP = 1; + local bitmask = 1 << bit; + STATUS = STATUS | bitmask; +} + +:BTFSC srcREG, bit is op4=0x6 & bit & srcREG [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] { + # --01 10bb bfff ffff + # 0001 1010 0000 0000 -> BTFSC INDF, #0x4 + # 0001 1010 0010 0000 -> BTFSC 0x20, #0x4 + local bitmask = 1 << bit; + local tmp = srcREG & bitmask; + SkipNext = (tmp == 0); +} + +:BC absAddr11 is doPseudo=1 & op4=0x6 & b3=0 & bit & f7=0x3 ; op3=0x5 & absAddr11 { + if ($(C) == 0) goto inst_next; + goto [absAddr11]; +} + +@if PROCESSOR == "PIC_16F" + +:BRA relAddr9 is op5=0x19 & relAddr9 { + goto [relAddr9]; +} + +:BRW is op14=0xb { + # inst_next is byte, not word offset, need to load PC with word offset + PC = (inst_next >> 1) + zext(W); + goto [PC]; +} + +@endif + +:BTFSC STATUS, bit is op4=0x6 & b3=0 & bit & f7=0x3 & STATUS [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] { + # --01 10bb bfff ffff + # 0001 1000 0000 0011 -> BTFSC STATUS, #C + SkipNext = ($(C) == 0); +} + +:SKPC is doPseudo=1 & op4=0x6 & b3=0 & bit & f7=0x3 [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] { + SkipNext = ($(C) == 1); +} + +:SKPNC is doPseudo=1 & op4=0x7 & b3=0 & bit & f7=0x3 [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] { + SkipNext = ($(C) != 1); +} + +:SKPZ is doPseudo=1 & op4=0x6 & b3=2 & bit & f7=0x3 [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] { + SkipNext = ($(Z) == 1); +} + +:SKPNZ is doPseudo=1 & op4=0x7 & b3=2 & bit & f7=0x3 [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] { + SkipNext = ($(Z) != 1); +} + +:BTFSC STATUS, bit is op4=0x6 & b3=1 & bit & f7=0x3 & STATUS [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] { + # --01 10bb bfff ffff + # 0001 1000 1000 0011 -> BTFSC STATUS, #DC + SkipNext = ($(DC) == 0); +} + +:BZ absAddr11 is doPseudo=1 & op4=0x6 & b3=2 & bit & f7=0x3 ; op3=0x5 & absAddr11 { + if ($(Z) == 0) goto inst_next; + goto [absAddr11]; +} + +:BTFSC STATUS, bit is op4=0x6 & b3=2 & bit & f7=0x3 & STATUS [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] { + # --01 10bb bfff ffff + # 0001 1001 0000 0011 -> BTFSC STATUS, #Z + SkipNext = ($(Z) == 0); +} + +:BTFSS srcREG, bit is op4=0x7 & bit & srcREG [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] { + # --01 11bb bfff ffff + # 0001 1110 0000 0000 -> BTFSS INDF, #0x4 + # 0001 1110 0010 0000 -> BTFSS 0x20, #0x4 + local bitmask = 1 << bit; + local tmp = srcREG & bitmask; + SkipNext = (tmp != 0); +} + +:BNC absAddr11 is doPseudo=1 & op4=0x7 & b3=0 & bit & f7=0x3 ; op3=0x5 & absAddr11 { + if ($(C) != 0) goto inst_next; + goto [absAddr11]; +} + +:BTFSS STATUS, bit is op4=0x7 & b3=0 & bit & f7=0x3 & STATUS [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] { + # --01 11bb bfff ffff + # 0001 1100 0000 0011 -> BTFSS STATUS, #C + SkipNext = ($(C) != 0); +} + +:BTFSS STATUS, bit is op4=0x7 & b3=1 & bit & f7=0x3 & STATUS [ possibleSkip = 1; globalset(inst_next,possibleSkip); ]{ + # --01 11bb bfff ffff + # 0001 1100 1000 0011 -> BTFSS STATUS, #DC + SkipNext = ($(DC) != 0); +} + +:BNZ absAddr11 is doPseudo=1 & op4=0x7 & b3=2 & bit & f7=0x3 ; op3=0x5 & absAddr11 { + if ($(Z) != 0) goto inst_next; + goto [absAddr11]; +} + +:BTFSS STATUS, bit is op4=0x7 & b3=2 & bit & f7=0x3 & STATUS [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] { + # --01 11bb bfff ffff + # 0001 1101 0000 0011 -> BTFSS STATUS, #Z + SkipNext = ($(Z) != 0); +} + +:CALL absAddr11 is op3=0x4 & absAddr11 { + # --10 0kkk kkkk kkkk + # 0010 0001 0010 0011 -> CALL 0x123 + # 0010 0000 0001 0000 -> CALL 0x10 + push(&:2 inst_next); + call [absAddr11]; +} + +:CALLW is op14=0x000a { + # --00 0000 0000 1010 + push(&:2 inst_next); + call [W]; +} + +:CLRF srcREG is op6=0x01 & d=1 & srcREG { + # --00 0001 1fff ffff + # 0000 0001 1000 0000 -> CLRF INDF + # 0000 0001 1010 0000 -> CLRF 0x20 + srcREG = 0; + $(Z) = 1; +} + +:CLRF STATUS is op6=0x01 & d=1 & f7=0x3 & STATUS { + # --00 0001 1fff ffff + # 0000 0001 1000 0011 -> CLRF STATUS + STATUS = 0; + IRP = 0; + RP = 0; + $(Z) = 0; + $(DC) = 0; + $(C) = 0; +} + +:CLRW is op12=0b000001000000 & mm { + # --00 0001 0xxx xxxx + # 0000 0001 0000 0000 -> CLRW + W = 0; + $(Z) = 1; +} + +:CLRWDT is op14=0x0064 { + # --00 0000 0110 0100 + # Clear Watchdog Timer - Not Implemented + clearWatchDogTimer(); +} + +:COMF srcREG, D is op6=0x09 & srcREG & D & destREG { + # --00 1001 dfff ffff + # 0000 1001 0000 0000 -> COMF INDF, 0 + # 0000 1001 1000 0000 -> COMF INDF, 1 + # 0000 1001 0010 0000 -> COMF 0x20, 0 + # 0000 1001 1010 0000 -> COMF 0x20, 1 + tmp:1 = ~srcREG; + destREG = tmp; + setResultFlags(tmp); +} + +:DECF srcREG, D is op6=0x03 & srcREG & D & destREG { + # --00 0011 dfff ffff + # 0000 0011 0000 0000 -> DECF INDF, 0 + # 0000 0011 1000 0000 -> DECF INDF, 1 + # 0000 0011 0010 0000 -> DECF 0x20, 0 + # 0000 0011 1010 0000 -> DECF 0x20, 1 + val:1 = srcREG - 1; + destREG = val; + setResultFlags(val); +} + +:DECFSZ srcREG, D is op6=0x0b & srcREG & D & destREG [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] { + # --00 1011 dfff ffff + # 0000 1011 0000 0000 -> DECFSZ INDF, 0 + # 0000 1011 1000 0000 -> DECFSZ INDF, 1 + # 0000 1011 0010 0000 -> DECFSZ 0x20, 0 + # 0000 1011 1010 0000 -> DECFSZ 0x20, 1 + val:1 = srcREG - 1; + destREG = val; + SkipNext = (val == 0); +} + +:GOTO absAddr11 is op3=0x5 & absAddr11 { + # --10 1kkk kkkk kkkk + # 0010 1001 0010 0011 -> GOTO 0x123 + # 0010 1000 0001 0000 -> GOTO 0x10 + goto [absAddr11]; +} + +:INCF srcREG, D is op6=0x0a & srcREG & D & destREG { + # --00 1010 dfff ffff + # 0000 1010 0000 0000 -> INCF INDF, 0 + # 0000 1010 1000 0000 -> INCF INDF, 1 + # 0000 1010 0010 0000 -> INCF 0x20, 0 + # 0000 1010 1010 0000 -> INCF 0x20, 1 + val:1 = srcREG + 1; + destREG = val; + setResultFlags(val); +} + +:INCFSZ srcREG, D is op6=0x0f & srcREG & D & destREG [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] { + # --00 1111 dfff ffff + # 0000 1111 0000 0000 -> INCFSZ INDF, 0 + # 0000 1111 1000 0000 -> INCFSZ INDF, 1 + # 0000 1111 0010 0000 -> INCFSZ 0x20, 0 + # 0000 1111 1010 0000 -> INCFSZ 0x20, 1 + val:1 = srcREG + 1; + destREG = val; + SkipNext = (val == 0); +} + +:IORLW imm8 is op6=0x38 & imm8 { + # --11 1000 kkkk kkkk + # 0011 1000 0001 0010 -> IORLW #0x12 + W = W | imm8; + setResultFlags(W); +} + +:IORWF srcREG, D is op6=0x04 & srcREG & D & destREG { + # --00 0100 dfff ffff + # 0000 0100 0000 0000 -> IORWF INDF, 0 + # 0000 0100 1000 0000 -> IORWF INDF, 1 + # 0000 0100 0010 0000 -> IORWF 0x20, 0 + # 0000 0100 1010 0000 -> IORWF 0x20, 1 + val:1 = W | srcREG; + destREG = val; + setResultFlags(val); +} + +@if PROCESSOR == "PIC_16F" + +srcFSR: "++"fsr is fsr & mm=0 { fsr = fsr + 1; addr:2 = fsr; export *[DATA]:1 addr; } +srcFSR: "--"fsr is fsr & mm=1 { fsr = fsr - 1; addr:2 = fsr; export *[DATA]:1 addr; } +srcFSR: fsr"++" is fsr & mm=2 { addr:2 = fsr; fsr = fsr + 1; export *[DATA]:1 addr; } +srcFSR: fsr"--" is fsr & mm=3 { addr:2 = fsr; fsr = fsr - 1; export *[DATA]:1 addr; } + +srcFSRk: sk6"["fsrk"]" is fsrk & sk6 { + addr:2 = fsrk + sk6; export *[DATA]:1 addr; +} + +:LSLF srcREG, D is op6=0x35 & srcREG & D & destREG { + # --11 0101 dfff ffff + $(C) = (srcREG & 80) != 0; + val:1 = srcREG << 1; + setResultFlags(val); + destREG = val; +} + +:LSRF srcREG, D is op6=0x36 & srcREG & D & destREG { + # --11 0110 dfff ffff + $(C) = srcREG & 0x1; + val:1 = srcREG >> 1; + setResultFlags(val); + destREG = val; +} + +:MOVIW srcFSR is op11=2 & srcFSR { + W = srcFSR; + setResultFlags(W); +} + +:MOVIW srcFSRk is op7=0x7e & srcFSRk { + W = srcFSRk; + setResultFlags(W); +} + +:MOVWI srcFSR is op11=3 & srcFSR { + srcFSR = W; +} + +:MOVWI srcFSRk is op7=0x7f & srcFSRk { + srcFSRk = W; +} + +:MOVLB imm5 is op9=0x1 & imm5 { + BSR = imm5; +} + +:MOVLP imm7 is op7=0x63 & imm7 { + PCLATH = imm7; +} +@endif + +:MOVLW imm8 is op6=0x30 & imm8 { + # --11 00xx kkkk kkkk + # 0011 0000 0001 0010 -> MOVLW #0x12 + W = imm8; +} + +:MOVF srcREG, D is op6=0x08 & srcREG & D & destREG { + # --00 1000 dfff ffff + # 0000 1000 0000 0000 -> MOVF INDF, 0 + # 0000 1000 1000 0000 -> MOVF INDF, 1 + # 0000 1000 0010 0000 -> MOVF 0x20, 0 + # 0000 1000 1010 0000 -> MOVF 0x20, 1 + val:1 = srcREG; + destREG = val; + setResultFlags(val); +} + +:MOVWF srcREG is op6=0x00 & d=1 & srcREG { + # --00 0000 1fff ffff + # 0000 0000 1000 0000 -> MOVWF INDF + # 0000 0000 1010 0000 -> MOVWF 0x20 + srcREG = W; +} + +:MOVWF PC is op6=0x00 & d=1 & f7=0x02 & PC { + # --00 0000 1fff ffff + # 0000 0000 1000 0010 -> MOVWF PCL + PCL = W; + addr:2 = (zext(PCLATH) << 8) + zext(PCL); + goto [addr]; +} + +:NOP is op6=0 & d=0 & l5=0 { + # --00 0000 0xx0 0000 +} + +:OPTION is op14=0x0062 { + # --00 0000 0110 0010 + OPTION = W; +} + +:RESET is op14=0x0001 { + reset(); + goto 0x0; +} + +:RETFIE is op14=0x0009 { + # --00 0000 0000 1001 + INTCON = 0x80 | INTCON; # set INTCON.GIE bit + retAddr:4 = 0; + pop(retAddr); + return [retAddr]; +} + +:RETLW imm8 is op4=0xd & imm8 { + # --11 01xx kkkk kkkk + # 0011 0100 0001 0010 -> RETLW #0x12 + W = imm8; + retAddr:4 = 0; + pop(retAddr); + return [retAddr]; +} + +:RETURN is op14=0x0008 { + # --00 0000 0000 1000 + retAddr:4 = 0; + pop(retAddr); + return [retAddr]; +} + +:RLF srcREG, D is op6=0x0d & srcREG & D & destREG { + # --00 1101 dfff ffff + # 0000 1101 0000 0000 -> RLF INDF, 0 + # 0000 1101 1000 0000 -> RLF INDF, 1 + # 0000 1101 0010 0000 -> RLF 0x20, 0 + # 0000 1101 1010 0000 -> RLF 0x20, 1 + local tmpC = $(C); + val:1 = srcREG; + $(C) = (val s< 0); + val = (val << 1) | tmpC; + destREG = val; + setResultFlags(val); +} + +:RRF srcREG, D is op6=0x0c & srcREG & D & destREG { + # --00 1100 dfff ffff + # 0000 1100 0000 0000 -> RRF INDF, 0 + # 0000 1100 1000 0000 -> RRF INDF, 1 + # 0000 1100 0010 0000 -> RRF 0x20, 0 + # 0000 1100 1010 0000 -> RRF 0x20, 1 + local tmpC = $(C) << 7; + val:1 = srcREG; + $(C) = (val & 1) != 0; + val = (val >> 1) | tmpC; + destREG = val; + setResultFlags(val); +} + +:SLEEP is op14=0x0063 { + # --00 0000 0110 0011 + # Sleep - Not Implemented + sleep(); +} + +:SUBLW imm8 is op6=0x3c & imm8 { + # --11 110x kkkk kkkk + # 0011 1100 0001 0010 -> SUBLW #0x12 + setSubtractFlags(imm8, W); + W = imm8 - W; + setResultFlags(W); +} + +:SUBWF srcREG, D is op6=0x02 & srcREG & D & destREG { + # --00 0010 dfff ffff + # 0000 0010 0000 0000 -> SUBWF INDF, 0 + # 0000 0010 1000 0000 -> SUBWF INDF, 1 + # 0000 0010 0010 0000 -> SUBWF 0x20, 0 + # 0000 0010 1010 0000 -> SUBWF 0x20, 1 + val:1 = srcREG; + setSubtractFlags(val, W); + val = val - W; + setResultFlags(val); + destREG = val; +} + +:SUBWFB srcREG, D is op6=0x3b & srcREG & D & destREG { + val:1 = srcREG; + bor:1 = !$(C); + + setSubtractFlags(val, W); + val = val - W; + tb:1 = $(C); + + setSubtractFlags(val,bor); + # first subtraction could cause borrow + $(C) = $(C) & tb; # borrow if C not set + val = val - bor; + + setResultFlags(val); + destREG = val; +} + +:SWAPF srcREG, D is op6=0x0e & srcREG & D & destREG { + # --00 1110 dfff ffff + # 0000 1110 0000 0000 -> SUBWF INDF, 0 + # 0000 1110 1000 0000 -> SUBWF INDF, 1 + # 0000 1110 0010 0000 -> SUBWF 0x20, 0 + # 0000 1110 1010 0000 -> SUBWF 0x20, 1 + val:1 = srcREG; + destREG = (val << 4) | (val >> 4); +} + +:TRIS trisREG is op9=0x3 & trisREG { + # --00 0000 0110 0fff + # 0000 0000 0110 0101 -> TRIS 5 + trisREG = W; +} + +:XORLW imm8 is op6=0x3a & imm8 { + # --11 1010 kkkk kkkk + # 0011 1010 0001 0010 -> XORLW #0x12 + W = imm8 ^ W; + setResultFlags(W); +} + +:XORWF srcREG, D is op6=0x06 & srcREG & D & destREG { + # --00 0110 dfff ffff + # 0000 0110 0000 0000 -> XORWF INDF, 0 + # 0000 0110 1000 0000 -> XORWF INDF, 1 + # 0000 0110 0010 0000 -> XORWF 0x20, 0 + # 0000 0110 1010 0000 -> XORWF 0x20, 1 + val:1 = W ^ srcREG; + destREG = val; + setResultFlags(val); +} diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic16c5x.cspec b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16c5x.cspec new file mode 100644 index 0000000..0a8b191 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16c5x.cspec @@ -0,0 +1,37 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic16c5x.ldefs b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16c5x.ldefs new file mode 100644 index 0000000..23c805a --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16c5x.ldefs @@ -0,0 +1,17 @@ + + + + + PIC-16C5x + + + + diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic16c5x.pspec b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16c5x.pspec new file mode 100644 index 0000000..75a965f --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16c5x.pspec @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic16c5x.slaspec b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16c5x.slaspec new file mode 100644 index 0000000..86bd371 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16c5x.slaspec @@ -0,0 +1,30 @@ +@define PROCESSOR "PIC_12C5XX" + +@include "pic12.sinc" + +# +# NOTES - +# 1. If a specific PIC-12 has a different register set, this file and the pic12c5xx.specl file may be copied/renamed and +# slightly modified to specify a the correct Register File Map. +# + +# Bank-0 File Registers +define DATA offset=0x00 size=1 [ + INDF TMR0 PCL.0 STATUS.0 FSR.0 PORTA PORTB PORTC +]; + +@include "pic12_instructions.sinc" + +# IO Tristate Registers +define register offset=0x0020 size=1 [ TRISA TRISB TRISC ]; + +# TRIS register +trisREG: "5" is f5=0x5 { export TRISA; } +trisREG: "6" is f5=0x6 { export TRISB; } +trisREG: "7" is f5=0x7 { export TRISC; } + +:TRIS trisREG is op6=0x00 & d=0 & trisREG { + # ---- 0000 0000 0fff + # 0000 0000 0000 0110 -> TRIS 6 + trisREG = W; +} diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic16f.cspec b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16f.cspec new file mode 100644 index 0000000..5ec51e0 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16f.cspec @@ -0,0 +1,45 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic16f.pspec b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16f.pspec new file mode 100644 index 0000000..44a15b6 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16f.pspec @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic16f.slaspec b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16f.slaspec new file mode 100644 index 0000000..ac87840 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic16f.slaspec @@ -0,0 +1,5 @@ +@define PROCESSOR "PIC_16F" + +@include "pic16.sinc" + +@include "pic16_instructions.sinc" diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic17c7xx.cspec b/python/icicle/Ghidra/Processors/PIC/data/languages/pic17c7xx.cspec new file mode 100644 index 0000000..2f48a8c --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic17c7xx.cspec @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic17c7xx.ldefs b/python/icicle/Ghidra/Processors/PIC/data/languages/pic17c7xx.ldefs new file mode 100644 index 0000000..8e39834 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic17c7xx.ldefs @@ -0,0 +1,16 @@ + + + + + PIC-17C7xx + + + diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic17c7xx.pspec b/python/icicle/Ghidra/Processors/PIC/data/languages/pic17c7xx.pspec new file mode 100644 index 0000000..6cee3f5 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic17c7xx.pspec @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic17c7xx.sinc b/python/icicle/Ghidra/Processors/PIC/data/languages/pic17c7xx.sinc new file mode 100644 index 0000000..2e9d066 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic17c7xx.sinc @@ -0,0 +1,55 @@ +# +# PIC-17C7xx Main Section +# includes constants, memory space and common register space definitions +# + +@define SFR_BASE 0x0F80 +@define BANK15_BASE 0x0F00 + +# ALUSTA bit definitions +@define STATUS_OV_BIT 3 +@define STATUS_Z_BIT 2 +@define STATUS_DC_BIT 1 +@define STATUS_C_BIT 0 + +# ALUSTA bit masks used for clearing +@define STATUS_OV_CLEARMASK 0xF7 +@define STATUS_Z_CLEARMASK 0xFB +@define STATUS_DC_CLEARMASK 0xFD +@define STATUS_C_CLEARMASK 0xFE + +define endian=little; +define alignment=2; + +# Instruction Memory (ROM-based) +define space CODE type=ram_space wordsize=2 size=2 default; + +# General Purpose Register Memory +# 0x00 - 0x0f : Unbanked registers +# 0x10 - 0x17 : Banked registers (9 banks controlled by lower nibble of BSR) +# 0x18 - 0x19 : Unbanked registers +# 0x1a - 0x1f : Unbanked GPRs +# 0x20 - 0xff : Banked GPRs (4 banks controlled by upper nibble of BSR) +define space DATA type=ram_space size=2; + +# The HWSTACK consists of a 16_word by 16_bit RAM and a corresponding 4_bit STKPTR register (which is not readable or writable). +# There is no means of directly accessing the stack space other than via a CALL, RETURN, RETLW or RETFIE +define space HWSTACK type=ram_space size=1; # implemented as independently addressable bytes (each location is 2-bytes wide) + +define space register type=register_space size=2; + +# Program Counter +define register offset=0x0000 size=2 [ PC ]; + +# Stack Pointer (4-bits) +define register offset=0x0004 size=1 [ STKPTR ]; + +# ALUSTA bit registers (these do not really exist and must get reflected into the STATUS byte register) +define register offset=0x0005 size=1 [ FS32 FS10 OV Z DC C ]; + +# Table Latch (not visible) +define register offset=0x0010 size=1 [ TBLATL TBLATH ]; +define register offset=0x0010 size=2 [ TBLAT ]; + +# Mirrored registers for improved decompiler behavior +define register offset=0x0020 size=1 [ WREG ]; diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic17c7xx.slaspec b/python/icicle/Ghidra/Processors/PIC/data/languages/pic17c7xx.slaspec new file mode 100644 index 0000000..3be8c76 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic17c7xx.slaspec @@ -0,0 +1,67 @@ +@define PROCESSOR "PIC_17C7xx" + +@include "pic17c7xx.sinc" + +# 0x00 - 0x0f (Unbanked - BSR ignored, WREG hidden and mirrored in register space) +define DATA offset=0x000 size=1 [ + INDF0 FSR0 PCL PCLATH ALUSTA T0STA CPUSTA INTSTA INDF1 FSR1 _ TMR0L TMR0H TBLPTRL TBLPTRH BSR +]; + +# Bank-0 0x10 - 0x17 (lower nibble of BSR determines bank, i.e. address<11:8>) +define DATA offset=0x010 size=1 [ + PORTA DDRB PORTB RCSTA1 RCREG1 TXSTA1 TXREG1 SPBRG1 +]; + +# Bank-1 0x10 - 0x17 (lower nibble of BSR determines bank, i.e. address<11:8>) +define DATA offset=0x110 size=1 [ + DDRC PORTC DDRD PORTD DDRE PORTE PIR1 PIE1 +]; + +# Bank-2 0x10 - 0x17 (lower nibble of BSR determines bank, i.e. address<11:8>) +define DATA offset=0x210 size=1 [ + TMR1 TMR2 TMR3L TMR3H PR1 PR2 PR3LCA1L PR3HCA1H +]; + +# Bank-3 0x10 - 0x17 (lower nibble of BSR determines bank, i.e. address<11:8>) +define DATA offset=0x310 size=1 [ + PW1DCL PW2DCL PW1DCH PW2DCH CA2L CA2H TCON1 TCON2 +]; + +# Bank-4 0x10 - 0x17 (lower nibble of BSR determines bank, i.e. address<11:8>) +define DATA offset=0x410 size=1 [ + PIR2 PIE2 _ RCSTA2 RCREG2 TXSTA2 TXREG2 SPBRG2 +]; + +# Bank-5 0x10 - 0x17 (lower nibble of BSR determines bank, i.e. address<11:8>) +define DATA offset=0x510 size=1 [ + DDRF PORTF DDRG PORTG ADCON0 ADCON1 ADRESL ADRESH +]; + +# Bank-6 0x10 - 0x17 (lower nibble of BSR determines bank, i.e. address<11:8>) +define DATA offset=0x610 size=1 [ + SSPADD SSPCON1 SSPCON2 SSPSTAT SSPBUF +]; + +# Bank-7 0x10 - 0x17 (lower nibble of BSR determines bank, i.e. address<11:8>) +define DATA offset=0x710 size=1 [ + PW3DCL PW3DCH CA3L CA3H CA4L CA4H TCON3 +]; + +# Bank-8 0x10 - 0x17 (lower nibble of BSR determines bank, i.e. address<11:8>) +define DATA offset=0x810 size=1 [ + DDRH PORTH DDRJ PORTJ +]; + +# 0x18 - 0x1f (Unbanked - BSR ignored) +define DATA offset=0x018 size=1 [ + PRODL PRODH +]; + +define DATA offset=0x00d size=2 [ TBLPTR ]; +define DATA offset=0x002 size=2 [ PCLAT ]; + +define DATA offset=0x018 size=2 [ PROD ]; + +define DATA offset=0x516 size=2 [ ADRES ]; + +@include "pic17c7xx_instructions.sinc" diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic17c7xx_instructions.sinc b/python/icicle/Ghidra/Processors/PIC/data/languages/pic17c7xx_instructions.sinc new file mode 100644 index 0000000..66b8694 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic17c7xx_instructions.sinc @@ -0,0 +1,916 @@ +# +# PIC-17C7xx Instruction Section +# includes token definitions, macros, sub-constructors and instruction definitions +# + +# 16-bit instruction token uses big-endian bit numbering which agrees with +# instruction bit numbering with PIC documentation. +# 15-14-13-12-11-10-9-8-7-6-5-4-3-2-1-0 +define token instr16(16) + op16 = (0,15) + op8 = (8,15) + op7 = (9,15) + op6 = (10,15) + op5 = (11,15) + op3 = (13,15) + t = (9,9) + d = (8,8) + s = (8,8) + i = (8,8) + b3 = (8,10) + p5_4 = (12,12) + p5_3 = (11,11) + p5 = (8,12) + p5reg = (8,12) + u4hi = (4,7) + u4lo = (0,3) + f8 = (0,7) + f8hi = (5,7) + f8_4 = (4,4) + f8_3 = (3,3) + f8reg = (0,4) + k8 = (0,7) + k8_h = (4,7) + k8_l = (0,3) + k13 = (0,12) +; + +attach variables [ f8reg p5reg ] [ + INDF0 FSR0 PCL PCLATH ALUSTA T0STA CPUSTA INTSTA + INDF1 FSR1 WREG TMR0L TMR0H TBLPTRL TBLPTRH BSR + _ _ _ _ _ _ _ _ + PRODL PRODH _ _ _ _ _ _ +]; + +attach variables [ t ] [ TBLATL TBLATH ]; + +# +# Special PIC-17 Operations +# + +# Return a decimal adjusted value for the value provided (see DAW instruction) +define pcodeop decimalAdjust; + +# Perform a Master Clear Reset +define pcodeop reset; + +define pcodeop clearWatchDogTimer; + +define pcodeop sleep; + +# +# MACROS +# + +macro setResultFlags(result) { + Z = (result == 0); +} + +macro setAddCOverflowFlag(op1,op2) { + local tmpC = C & 1; + OV = scarry(op1,tmpC) || scarry(op2,op1 + tmpC); +} + +macro setAddCCarryFlag(op1,op2) { + local tmpC = C & 1; + C = carry(op1,tmpC) || carry(op2,op1 + tmpC); +} + +macro setAddCDigitCarryFlag(op1,op2) { + # op1 and op2 are assumed to be 8-bit values + local tmp1 = op1 << 4; + local tmp2 = op2 << 4; + local tmpDC = DC & 1; + DC = carry(tmp1,tmpDC) || carry(tmp2,tmp1 + tmpDC); +} + +macro setAddCFlags(op1,op2) { + setAddCCarryFlag(op1,op2); + setAddCDigitCarryFlag(op1,op2); + setAddCOverflowFlag(op1,op2); +} + +macro setAddFlags(op1,op2) { + C = carry(op1,op2); + DC = carry(op1<<4,op2<<4); + OV = scarry(op1,op2); +} + +macro setSubtractCOverflowFlag(op1,op2) { + local notC = ~(C & 1); + OV = sborrow(op1,notC) || sborrow(op2,op1 - notC); +} + +macro setSubtractCCarryFlag(op1,op2) { + local notC = ~(C & 1); + C = (op1 < notC) || (op2 < (op1 - notC)); +} + +macro setSubtractCDigitCarryFlag(op1,op2) { + # op1 and op2 are assumed to be 8-bit values + local notDC = ~(DC & 1); + local tmp1 = op1 << 4; + local tmp2 = op2 << 4; + local tmp3 = (tmp1 - notDC) << 4; + DC = (tmp1 < notDC) || (tmp2 < tmp3); +} + +macro setSubtractCFlags(op1,op2) { + setSubtractCCarryFlag(op1,op2); + setSubtractCDigitCarryFlag(op1,op2); + setSubtractCOverflowFlag(op1,op2); +} + +macro setSubtractFlags(op1,op2) { + # op1 and op2 are assumed to be 8-bit values + # NOTE: carry flag is SET if there is NO borrow + C = (op1 >= op2); + DC = ((op1<<4) < (op2<<4)); + OV = sborrow(op1,op2); +} + +macro push(val) { # TODO: Uncertain about this !! +# CheckStackFull(); + *[HWSTACK]:2 STKPTR = val; + STKPTR = STKPTR + 2; +} + +macro pop(rval) { # TODO: Uncertain about this !! +# CheckStackUnderflow(); + STKPTR = STKPTR - 2; + rval = *[HWSTACK]:2 STKPTR; +} + +# +# SUB-CONSTRUCTORS +# + +# PC register write - instruction must set PCLATH/PCL and perform branch operation +fPC: "PC" is f8=0x02 { export PCL; } +pPC: "PC" is p5=0x02 { export PCL; } + +# ALUSTA register +fALUSTA: f8reg is f8=0x04 & f8reg { export f8reg; } +#pALUSTA: p5reg is p5=0x04 & p5reg { export p5reg; } + +# +# f Register subconstructors +# + +# 0x00-0x0f Unbanked registers +fREGLoc: f8reg is f8hi=0 & f8_4=0 & f8reg { export f8reg; } + +# 0x10-0x1f Banked registers +fREGLoc: f8 is f8hi=0 & f8_4=1 & f8_3=0 & f8 { ptr:2 = (zext(BSR & 0x0f) << 8) + f8; export *[DATA]:1 ptr; } + +# 0x18-0x19 Unbanked registers (PRODL,PRODH) +fREGLoc: f8reg is f8=0x18 & f8reg { export f8reg; } +fREGLoc: f8reg is f8=0x19 & f8reg { export f8reg; } + +# Unbanked general purpose RAM +fREGLoc: f8 is f8hi=0 & f8_4=1 & f8_3=1 & f8 { export *[DATA]:1 f8; } + +# Banked general purpose RAM +fREGLoc: f8 is f8 { ptr:2 = (zext(BSR & 0xf0) << 4) + f8; export *[DATA]:1 ptr; } + + +# Indirect File Register access - INDF0 +fREGLoc: f8reg is f8=0x00 & f8reg { + addr:1 = FSR0; + val:1 = ((FS10 == 0x1) * 1) + ((FS10 == 0x0) * -1); + FSR0 = addr + val; + export *[DATA]:1 addr; +} + +# Indirect File Register access - INDF1 +fREGLoc: f8reg is f8=0x08 & f8reg { + addr:1 = FSR1; + val:1 = ((FS32 == 0x1) * 1) + ((FS32 == 0x0) * -1); + FSR1 = addr + val; + export *[DATA]:1 addr; +} + + +# +# p Register subconstructors +# + +# 0x00-0x0f Unbanked registers +pREGLoc: p5reg is p5_4=0 & p5reg { export p5reg; } + +# 0x10-0x17 Banked registers +pREGLoc: p5 is p5_4=1 & p5_3=0 & p5 { ptr:2 = (zext(BSR & 0x0f) << 8) + p5; export *[DATA]:1 ptr; } + +# 0x18-0x19 Unbanked registers (PRODL,PRODH) +pREGLoc: p5reg is p5=0x18 & p5reg { export p5reg; } +pREGLoc: p5reg is p5=0x19 & p5reg { export p5reg; } + +# Unbanked general purpose RAM +pREGLoc: p5 is p5_4=1 & p5_3=1 & p5 { export *[DATA]:1 p5; } + +# Indirect File Register access - INDF0 +pREGLoc: p5reg is p5=0x00 & p5reg { + addr:1 = FSR0; + val:1 = ((FS10 == 0x1) * 1) + ((FS10 == 0x0) * -1); + FSR0 = addr + val; + export *[DATA]:1 addr; +} + +# Indirect File Register access - INDF1 +pREGLoc: p5reg is p5=0x08 & p5reg { + addr:1 = FSR1; + val:1 = ((FS32 == 0x1) * 1) + ((FS32 == 0x0) * -1); + FSR1 = addr + val; + export *[DATA]:1 addr; +} + + +# Direct File register data +srcFREG: fREGLoc is fREGLoc { export fREGLoc; } + +# PCL read - latch PC into PCL and PCLATH +srcFREG: "PC" is f8=0x02 { + PCLAT = inst_start; + export PCL; +} + +# Destination register (always fREGLoc) +destFREG: fREGLoc is fREGLoc { export fREGLoc; } + +# Destination register (either fREGLoc or WREG) +destREG: "0" is d=0 { export WREG; } +destREG: "1" is d=1 & fREGLoc { export fREGLoc; } + +# Direct File register data +srcPREG: pREGLoc is pREGLoc { export pREGLoc; } + +# PCL read - latch PC into PCL and PCLATH +srcPREG: "PC" is p5=0x02 { + PCLAT = inst_start; + export PCL; +} + +# Destination register (always pREGLoc) +destPREG: pREGLoc is pREGLoc { export pREGLoc; } + +# Destination operand representation (w: W register is destination; f: specified fREG is destination) +D: "w" is d=0 { } +D: "f" is d=1 { } + +# s-flag used by those instructions which can optionally store result in both srcFREG and WREG +S: "0" is s=0 { } +S: "1" is s=1 { } + +# Table read/write i-flag +I: "0" is i=0 { } +I: "1" is i=1 { } + +# Table read/write t-flag identifies table latch register (high or low byte) +T: t is t { export t; } + +# Relative instruction location with an 8K page +shortAddr: nLoc is k13 [ nLoc = (inst_next & 0xe000) + k13; ] { + tmp:2 = nLoc:2 >> 8; + PCLATH = tmp:1; + export *[CODE]:2 nLoc; +} + +# Absolute instruction location within 64K space (PCLATH contain upper 8-bits) +longAddr: k8 is k8 { + addr:2 = (zext(PCLATH) << 8) + k8; + export addr; +} + +# Skip instruction address +skipInst: inst_skip is op16 [ inst_skip = inst_next + 1; ] {export *[CODE]:2 inst_skip; } + +# Immediate Data (Literal operation) +imm8: "#"k8 is k8 { export *[const]:1 k8; } +imm8h: "#"k8_h is k8_h { export *[const]:1 k8_h; } +imm8l: "#"k8_l is k8_l { export *[const]:1 k8_l; } + +# Bit identifier +bit: "#"b3 is b3 { export *[const]:1 b3; } + + +# +# Instructions +# + +:ADDLW imm8 is op8=0xb1 & imm8 { + # 1011 0001 kkkk kkkk + tmp1:1 = WREG; + tmp2:1 = imm8; + setAddFlags(tmp1, tmp2); + local tmp = tmp1 + tmp2; + WREG = tmp; + setResultFlags(tmp); +} + +:ADDWF srcFREG, D is op7=0x07 & D & srcFREG & destREG { + # 0000 111d ffff ffff + tmp1:1 = srcFREG; # read only once! + tmp2:1 = WREG; + setAddFlags(tmp1, tmp2); + local tmp = tmp1 + tmp2; + destREG = tmp; + setResultFlags(tmp); +} + +:ADDWF fPC, D is op7=0x07 & D & d=1 & fPC { + # 0000 111d ffff ffff + # 0000 1110 ffff ffff -> ADDWF PCL, w + addr:2 = inst_start >> 1; # Compenstate for CODE wordsize + addrHi:1 = addr(1); + PCLATH = addrHi; + addrLo:1 = addr:1; + tmpW:1 = WREG; + setAddFlags(addrLo, tmpW); + addrLo = addrLo + tmpW; + addr = (zext(addrHi) << 8) + zext(addrLo); + setResultFlags(addrLo); + goto [addr]; +} + +:ADDWFC srcFREG, D is op7=0x08 & D & srcFREG & destREG { + # 0001 000d ffff ffff + local tmpC = C & 1; + tmp1:1 = srcFREG; # read only once! + tmp2:1 = WREG; + setAddCFlags(tmp1, tmp2); + local tmp = tmp1 + tmp2 + tmpC; + destREG = tmp; + setResultFlags(tmp); +} + +:ANDLW imm8 is op8=0xb5 & imm8 { + # 1011 0101 kkkk kkkk + tmp:1 = WREG & imm8; + WREG = tmp; + setResultFlags(tmp); +} + +:ANDWF srcFREG, D is op7=0x05 & D & srcFREG & destREG { + # 0000 101d ffff ffff + tmp:1 = srcFREG & WREG; + destREG = tmp; + setResultFlags(tmp); +} + +:BCF srcFREG, bit is op5=0x11 & bit & srcFREG { + # 1000 1bbb ffff ffff + local bitmask = ~(1 << bit); + srcFREG = srcFREG & bitmask; +} + +:BCF fALUSTA, bit is op5=0x11 & b3=0 & fALUSTA & bit { + # 1000 1000 0000 0100 -> BCF ALUSTA, #C + C = 0; +} + +:BCF fALUSTA, bit is op5=0x11 & b3=1 & fALUSTA & bit { + # 1000 1001 0000 0100 -> BCF ALUSTA, #DC + DC = 0; +} + +:BCF fALUSTA, bit is op5=0x11 & b3=2 & fALUSTA & bit { + # 1000 1010 0000 0100 -> BCF ALUSTA, #Z + Z = 0; +} + +:BCF fALUSTA, bit is op5=0x11 & b3=3 & fALUSTA & bit { + # 1000 1011 0000 0100 -> BCF ALUSTA, #OV + OV = 0; +} + +:BCF fALUSTA, bit is op5=0x11 & b3=4 & fALUSTA & bit { + # 1000 1100 0000 0100 -> BCF ALUSTA, #FS0 + FS10 = FS10 & 0x2; +} + +:BCF fALUSTA, bit is op5=0x11 & b3=5 & fALUSTA & bit { + # 1000 1101 0000 0100 -> BCF ALUSTA, #FS1 + FS10 = FS10 & 0x1; +} + +:BCF fALUSTA, bit is op5=0x11 & b3=6 & fALUSTA & bit { + # 1000 1110 0000 0100 -> BCF ALUSTA, #FS2 + FS32 = FS32 & 0x2; +} + +:BCF fALUSTA, bit is op5=0x11 & b3=7 & fALUSTA & bit { + # 1000 1111 0000 0100 -> BCF ALUSTA, #FS3 + FS32 = FS32 & 0x1; +} + +:BSF srcFREG, bit is op5=0x10 & bit & srcFREG { + # 1000 0bbb ffff ffff + local bitmask = 1 << bit; + srcFREG = srcFREG | bitmask; +} + +:BSF fALUSTA, bit is op5=0x10 & b3=0 & bit & fALUSTA { + # 1000 0000 0000 0100 -> BSF ALUSTA, #C + C = 1; +} + +:BSF fALUSTA, bit is op5=0x10 & b3=1 & bit & fALUSTA { + # 1000 0000 0000 0100 -> BSF ALUSTA, #DC + DC = 1; +} + +:BSF fALUSTA, bit is op5=0x10 & b3=2 & bit & fALUSTA { + # 1000 0000 0000 0100 -> BSF ALUSTA, #Z + Z = 1; +} + +:BSF fALUSTA, bit is op5=0x10 & b3=3 & bit & fALUSTA { + # 1000 0000 0000 0100 -> BSF ALUSTA, #OV + OV = 1; +} + +:BSF fALUSTA, bit is op5=0x10 & b3=4 & bit & fALUSTA { + # 1000 0000 0000 0100 -> BSF ALUSTA, #FS0 + FS10 = FS10 | 0x1; +} + +:BSF fALUSTA, bit is op5=0x10 & b3=5 & bit & fALUSTA { + # 1000 0000 0000 0100 -> BSF ALUSTA, #FS1 + FS10 = FS10 | 0x2; +} + +:BSF fALUSTA, bit is op5=0x10 & b3=6 & bit & fALUSTA { + # 1000 0000 0000 0100 -> BSF ALUSTA, #FS2 + FS32 = FS32 | 0x1; +} + +:BSF fALUSTA, bit is op5=0x10 & b3=7 & bit & fALUSTA { + # 1000 0000 0000 0100 -> BSF ALUSTA, #FS3 + FS32 = FS32 | 0x2; +} + +:BTFSC srcFREG, bit is op5=0x13 & bit & srcFREG & skipInst { + # 1001 1bbb ffff ffff + local bitmask = 1 << bit; + local tmp = srcFREG & bitmask; + if (tmp == 0) goto skipInst; +} + +:BTFSC fALUSTA, bit is op5=0x13 & b3=0 & bit & fALUSTA & skipInst { + # 1001 1000 0000 0100 -> BTFSC STATUS, #C + if (C == 0) goto skipInst; +} + +:BTFSC fALUSTA, bit is op5=0x13 & b3=1 & bit & fALUSTA & skipInst { + # 1001 1001 0000 0100 -> BTFSC STATUS, #DC + if (DC == 0) goto skipInst; +} + +:BTFSC fALUSTA, bit is op5=0x13 & b3=2 & bit & fALUSTA & skipInst { + # 1001 1010 0000 0100 -> BTFSC STATUS, #Z + if (Z == 0) goto skipInst; +} + +:BTFSC fALUSTA, bit is op5=0x13 & b3=3 & bit & fALUSTA & skipInst { + # 1001 1011 0000 0100 -> BTFSC STATUS, #OV + if (OV == 0) goto skipInst; +} + +:BTFSS srcFREG, bit is op5=0x12 & bit & srcFREG & skipInst { + # 1001 0bbb ffff ffff + local bitmask = 1 << bit; + local tmp = srcFREG & bitmask; + if (tmp != 0) goto skipInst; +} + +:BTFSS fALUSTA, bit is op5=0x12 & b3=0 & bit & fALUSTA & skipInst { + # 1001 1000 0000 0100 -> BTFSS STATUS, #C + if (C != 0) goto skipInst; +} + +:BTFSS fALUSTA, bit is op5=0x12 & b3=1 & bit & fALUSTA & skipInst { + # 1001 1001 0000 0100 -> BTFSS STATUS, #DC + if (DC != 0) goto skipInst; +} + +:BTFSS fALUSTA, bit is op5=0x12 & b3=2 & bit & fALUSTA & skipInst { + # 1001 1010 0000 0100 -> BTFSS STATUS, #Z + if (Z != 0) goto skipInst; +} + +:BTFSS fALUSTA, bit is op5=0x12 & b3=3 & bit & fALUSTA & skipInst { + # 1001 1011 0000 0100 -> BTFSS STATUS, #OV + if (OV != 0) goto skipInst; +} + +:BTG srcFREG, bit is op5=0x7 & bit & srcFREG & skipInst { + # 0011 1bbb ffff ffff + local bitmask = 1 << bit; + tmp:1 = srcFREG; + srcFREG = ~(tmp & bitmask) | (tmp & ~bitmask); +} + +:CALL shortAddr is op3=0x7 & shortAddr { + # 111k kkkk kkkk kkkk + push(&:2 inst_next); + call shortAddr; +} + +# Special case for Call which appears to correspond to uninitialized +:BADCALL shortAddr is op16=0xffff & shortAddr { addr:2 = shortAddr; return [addr]; } + +:CLRF destFREG, S is op7=0x14 & s=0 & S & destFREG { + # 0010 1000 ffff ffff + destFREG = 0; + WREG = 0; +} + +:CLRF destFREG, S is op7=0x14 & s=1 & S & destFREG { + # 0010 1001 ffff ffff + destFREG = 0; +} + +:CLRF fALUSTA, S is op7=0x14 & s=0 & S & fALUSTA { + # 0010 1000 0000 0100 + C = 0; + DC = 0; + Z = 0; + OV = 0; + FS10 = 0; + FS32 = 0; + WREG = 0; +} + +:CLRF fALUSTA, S is op7=0x14 & s=1 & S & fALUSTA { + # 0010 1001 0000 0100 + C = 0; + DC = 0; + Z = 0; + OV = 0; + FS10 = 0; + FS32 = 0; +} + +:CLRWDT is op16=0x0004 { + # 0000 0000 0000 0100 + clearWatchDogTimer(); +} + +:COMF srcFREG, D is op7=0x09 & D & srcFREG & destREG { + # 0001 001d ffff ffff + tmp:1 = ~srcFREG; + destREG = tmp; + setResultFlags(tmp); +} + +:CPFSEQ srcFREG is op8=0x31 & srcFREG & skipInst { + # 0011 0001 ffff ffff + if (srcFREG == WREG) goto skipInst; +} + +:CPFSGT srcFREG is op8=0x32 & srcFREG & skipInst { + # 0011 0010 ffff ffff + if (srcFREG > WREG) goto skipInst; +} + +:CPFSLT srcFREG is op8=0x30 & srcFREG & skipInst { + # 0011 0000 ffff ffff + if (srcFREG < WREG) goto skipInst; +} + +:DAW destFREG, S is op7=0x17 & s=0 & S & destFREG { + # 0010 1110 ffff ffff + tmp:1 = decimalAdjust(WREG); + destFREG = tmp; + WREG = tmp; +} + +:DAW destFREG, S is op7=0x17 & s=1 & S & destFREG { + # 0010 1111 ffff ffff + tmp:1 = decimalAdjust(WREG); + destFREG = tmp; + setResultFlags(tmp); +} + +:DECF srcFREG, D is op7=0x03 & D & srcFREG & destREG { + # 0000 011d ffff ffff + tmp:1 = srcFREG; + setSubtractFlags(tmp, 1); + tmp = tmp - 1; + destREG = tmp; + setResultFlags(tmp); +} + +:DECFSZ srcFREG, D is op7=0x0b & D & srcFREG & destREG & skipInst { + # 0001 011d ffff ffff + val:1 = srcFREG - 1; + destREG = val; + if (val == 0) goto skipInst; +} + +:DCFSNZ srcFREG, D is op7=0x13 & D & srcFREG & destREG & skipInst { + # 0010 011d ffff ffff + val:1 = srcFREG - 1; + destREG = val; + if (val != 0) goto skipInst; +} + +:GOTO shortAddr is op3=0x6 & shortAddr { + # 110k kkkk kkkk kkkk + goto shortAddr; +} + +:INCF srcFREG, D is op7=0x0a & D & srcFREG & destREG { + # 0001 010d ffff ffff + tmp:1 = srcFREG; # read once only! + setAddFlags(tmp, 1); + tmp = tmp + 1; + destREG = tmp; + setResultFlags(tmp); +} + +:INCFSZ srcFREG, D is op7=0x0f & D & srcFREG & destREG & skipInst { + # 0001 111d ffff ffff + val:1 = srcFREG + 1; + destREG = val; + if (val == 0) goto skipInst; +} + +:INFSNZ srcFREG, D is op7=0x12 & D & srcFREG & destREG & skipInst { + # 0010 010d ffff ffff + val:1 = srcFREG + 1; + destREG = val; + if (val != 0) goto skipInst; +} + +:IORLW imm8 is op8=0xb3 & imm8 { + # 1011 0011 kkkk kkkk + tmp:1 = WREG | imm8; + WREG = tmp; + setResultFlags(tmp); +} + +:IORWF srcFREG, D is op7=0x04 & D & srcFREG & destREG { + # 0000 100d ffff ffff + tmp:1 = WREG | srcFREG; + destREG = tmp; + setResultFlags(tmp); +} + +:LCALL longAddr is op8=0xb7 & longAddr { + # 1011 0111 kkkk kkkk + push(&:2 inst_next); + call [longAddr]; +} + +:MOVFP srcFREG, destPREG is op3=0x3 & srcFREG & destPREG { + # 011p pppp ffff ffff + destPREG = srcFREG; +} + +:MOVFP srcFREG, pPC is op3=0x3 & srcFREG & pPC { + # 0110 0010 ffff ffff + addr:2 = (zext(PCLATH) << 8) + zext(srcFREG); + goto [addr]; +} + +:MOVLB imm8l is op8=0xb8 & u4hi=0 & imm8l { + # 1011 1000 0000 kkkk + BSR = (BSR & 0xf0) | imm8l; +} + +:MOVLR imm8h is op7=0x5d & u4lo=0 & imm8h { + # 1011 101x kkkk 0000 + BSR = (BSR & 0x0f) | (imm8h << 4); +} + +:MOVLW imm8 is op8=0xb0 & imm8 { + # 1011 0000 kkkk kkkk + WREG = imm8; +} + +:MOVPF srcPREG, destFREG is op3=0x2 & srcPREG & destFREG { + # 010p pppp ffff ffff + tmp:1 = srcPREG; + destFREG = tmp; + setResultFlags(tmp); +} + +:MOVPF srcPREG, fPC is op3=0x2 & srcPREG & fPC { + tmp:1 = srcPREG; + addr:2 = (zext(PCLATH) << 8) + zext(tmp); + setResultFlags(tmp); + goto [addr]; +} + +:MOVWF destFREG is op8=0x01 & destFREG { + # 0000 0001 ffff ffff + destFREG = WREG; +} + +:MOVWF fPC is op8=0x01 & fPC { + addr:2 = (zext(PCLATH) << 8) + zext(WREG); + goto [addr]; +} + +:MULLW imm8 is op8=0xbc & imm8 { + # 1011 1100 kkkk kkkk + PROD = zext(WREG) * zext(imm8); +} + +:MULLWF srcFREG is op8=0x34 & srcFREG { + # 0011 0100 ffff ffff + PROD = zext(WREG) * zext(srcFREG); +} + +:NEGW destFREG, S is op7=0x16 & s=0 & S & destFREG { + # 0010 110s ffff ffff + tmp:1 = -WREG; + destFREG = tmp; + WREG = tmp; + C = (tmp s< 0); + OV = sborrow(0,tmp); + setResultFlags(tmp); +} + +:NEGW destFREG, S is op7=0x16 & s=1 & S & destFREG { + # 0010 110s ffff ffff + tmp:1 = -WREG; + destFREG = tmp; + C = (tmp s< 0); + OV = sborrow(0,tmp); + setResultFlags(tmp); +} + +:NOP is op16=0x0 { } + +:RETFIE is op16=0x0005 { + # 0000 0000 0000 0101 + retAddr:2 = 0; + pop(retAddr); + return [retAddr]; +} + +:RETLW imm8 is op8=0xb6 & imm8 { + # 1011 0110 kkkk kkkk + WREG = imm8; + retAddr:2 = 0; + pop(retAddr); + return [retAddr]; +} + +:RETURN is op16=0x0002 { + # 0000 0000 0000 0010 + retAddr:2 = 0; + pop(retAddr); + return [retAddr]; +} + +:RLCF srcFREG, D is op7=0x0d & D & srcFREG & destREG { + # 0001 101d ffff ffff + local tmpC = C; + val:1 = srcFREG; + C = (val s< 0); + val = (val << 1) | tmpC; + destREG = val; +} + +:RLNCF srcFREG, D is op7=0x11 & D & srcFREG & destREG { + # 0010 001d ffff ffff + tmp:1 = srcFREG << 1; + destREG = tmp; +} + +:RRCF srcFREG, D is op7=0x0c & D & srcFREG & destREG { + # 0001 100d ffff ffff + local tmpC = C << 7; + tmp:1 = srcFREG; + C = (tmp & 1) != 0; + tmp = (tmp >> 1) | tmpC; + destREG = tmp; +} + +:RRNCF srcFREG, D is op7=0x10 & D & srcFREG & destREG { + # 0010 000d ffff ffff + tmp:1 = srcFREG >> 1; + destREG = tmp; +} + +:SETF destFREG, S is op7=0x15 & s=0 & S & destFREG { + # 0010 1010 ffff ffff + destFREG = 0xff; + WREG = 0xff; +} + +:SETF destFREG, S is op7=0x15 & s=1 & S & destFREG { + # 0010 1011 ffff ffff + destFREG = 0xff; +} + +:SETF fALUSTA, S is op7=0x15 & s=0 & S & fALUSTA { + # 0010 1010 0000 0100 + C = 1; + DC = 1; + Z = 1; + OV = 1; + FS10 = 0x3; + FS32 = 0x3; + WREG = 0xff; +} + +:SETF fALUSTA, S is op7=0x15 & s=1 & S & fALUSTA { + # 0010 1011 0000 0100 + C = 1; + DC = 1; + Z = 1; + OV = 1; + FS10 = 0x3; + FS32 = 0x3; +} + +:SLEEP is op16=0x0003 { + # 0000 0000 0000 0011 + sleep(); +} + +:SUBLW imm8 is op8=0xb2 & imm8 { + # 1011 0010 kkkk kkkk + tmp:1 = imm8; + tmpW:1 = WREG; + setSubtractFlags(tmp, tmpW); + tmp = tmp - tmpW; + WREG = tmp; + setResultFlags(tmp); +} + +:SUBWF srcFREG, D is op7=0x02 & D & srcFREG & destREG { + # 0000 010d ffff ffff + tmp:1 = srcFREG; + tmpW:1 = WREG; + setSubtractFlags(tmp, tmpW); + tmp = tmp - tmpW; + destREG = tmp; + setResultFlags(tmp); +} + +:SUBWFB srcFREG, D is op7=0x01 & D & srcFREG & destREG { + # 0000 001d ffff ffff + local notC = ~(C & 1); + tmp:1 = srcFREG; + tmpW:1 = WREG; + setSubtractCFlags(tmp, tmpW); + tmp = tmp - tmpW - notC; + destREG = tmp; + setResultFlags(tmp); +} + +:SWAPF srcFREG, D is op7=0x0e & D & srcFREG & destREG { + # 0001 110d ffff ffff + tmp:1 = srcFREG; + destREG = (tmp << 4) | (tmp >> 4); +} + +:TABLRD T, I, destFREG is op6=0x2a & T & I & i & destFREG { + # 1010 10ti ffff ffff + destFREG = T; + ptr:2 = TBLPTR; + TBLAT = *[CODE]:2 ptr; + TBLPTR = ptr + i; +} + +:TABLWT T, I, srcFREG is op6=0x2b & T & I & i & srcFREG { + # 1010 11ti ffff ffff + T = srcFREG; + ptr:2 = TBLPTR; + *[CODE]:2 ptr = TBLAT; + TBLPTR = ptr + i; +} + +:TLRD T, destFREG is op6=0x28 & T & destFREG { + # 1010 00tx ffff ffff + destFREG = T; +} + +:TLWT T, srcFREG is op6=0x29 & T & srcFREG { + # 1010 01tx ffff ffff + T = srcFREG; +} + +:TSTFSZ srcFREG is op8=0x33 & srcFREG & skipInst { + # 0011 0011 ffff ffff + if (srcFREG == 0) goto skipInst; +} + +:XORLW imm8 is op8=0xb4 & imm8 { + # 1011 0100 kkkk kkkk + tmp:1 = WREG ^ imm8; + WREG = tmp; + setResultFlags(tmp); +} + +:XORWF srcFREG, D is op7=0x06 & D & srcFREG & destREG { + # 0000 110d ffff ffff + tmp:1 = WREG ^ srcFREG; + destREG = tmp; + setResultFlags(tmp); +} diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic18.cspec b/python/icicle/Ghidra/Processors/PIC/data/languages/pic18.cspec new file mode 100644 index 0000000..152254a --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic18.cspec @@ -0,0 +1,45 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic18.ldefs b/python/icicle/Ghidra/Processors/PIC/data/languages/pic18.ldefs new file mode 100644 index 0000000..c7eab9b --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic18.ldefs @@ -0,0 +1,17 @@ + + + + + PIC-18 + + + + diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic18.pspec b/python/icicle/Ghidra/Processors/PIC/data/languages/pic18.pspec new file mode 100644 index 0000000..20181d6 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic18.pspec @@ -0,0 +1,47 @@ + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic18.sinc b/python/icicle/Ghidra/Processors/PIC/data/languages/pic18.sinc new file mode 100644 index 0000000..07067f7 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic18.sinc @@ -0,0 +1,78 @@ +# +# PIC-18 Main Section +# includes constants, memory space and common register space definitions +# + +@define SFR_BASE 0x0F80 +@define BANK15_BASE 0x0F00 + +# STATUS bit definitions +@define STATUS_N_BIT 4 +@define STATUS_OV_BIT 3 +@define STATUS_Z_BIT 2 +@define STATUS_DC_BIT 1 +@define STATUS_C_BIT 0 + +# STATUS bit masks used for clearing +@define STATUS_N_CLEARMASK 0xEF +@define STATUS_OV_CLEARMASK 0xF7 +@define STATUS_Z_CLEARMASK 0xFB +@define STATUS_DC_CLEARMASK 0xFD +@define STATUS_C_CLEARMASK 0xFE + +@define STATUS_N_Z_MASK 0x14 + +# STACK bit defintions +@define STKPTR_STKFUL_BIT 7 +@define STKPTR_STKUNF_BIT 6 + +# STACK bit masks +@define STKPTR_SP_MASK 0x1F +@define STKPTR_NOT_SP_MASK 0xE0 +@define STKPTR_STKFUL_MASK 0x80 +@define STKPTR_STKUNF_MASK 0x40 + +define endian=little; +define alignment=2; + +# Instruction Memory (ROM-based) +define space CODE type=ram_space size=3 default; + +# General Purpose Register Memory consists of 16-banks of 255-bytes each +define space DATA type=ram_space size=2; + +# The HWSTACK consists of a 31_word by 21_bit RAM and a corresponding 8_bit STKPTR register. +# The real STKPTR register format is: +# bit 7: Stack Full Flag (STKFUL) - See Note below +# bit 6: Stack Underflow Flag (STKUNF) - See Note below +# bit 5: +# bit 4_0: stack pointer location within the 31_word by 21_bit +# Each stack entry generally contains a 21_bit Program Counter value. +# The top_of_stack entry (last push) may be accessed via the SFR registers TOSU, TOSH, and TOSL: +# bit 20_16: TOSU +# bit 15_8: TOSH +# bit 7_0: TOSL +# When accessing these top_of_stack registers, the global interrupts should/must be disabled. +# +# NOTE: This PIC-18 pcode implementation does not implement the STKFUL and STKUNF bits. +# The entire STKPTR register is treated as an address offset into the stack space for simplification. +# STKPTR value must be multiplied. +# +define space HWSTACK type=ram_space size=1; # implemented as independently addressable bytes (each location is 4-bytes wide) + +define space register type=register_space size=2; + +# Program Counter +define register offset=0x0000 size=3 [ PC ]; + +# Bad Register (needed only for attach usage) +define register offset=0x0003 size=1 [ BAD ]; + +# Stack Pointer +define register offset=0x0004 size=1 [ STKPTR ]; + +# Status bit registers (these do not really exist and must get reflected into the STATUS byte register) +define register offset=0x0005 size=1 [ N OV Z DC C ]; + +# Shadow registers (not visible) +define register offset=0x000a size=1 [ WS STATUSS BSRS ]; diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic18.slaspec b/python/icicle/Ghidra/Processors/PIC/data/languages/pic18.slaspec new file mode 100644 index 0000000..59a11df --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic18.slaspec @@ -0,0 +1,40 @@ +@define PROCESSOR "PIC_18" + +@include "pic18.sinc" + +# +# NOTES - +# 1. If a specific PIC-18 has a different register set, this file and the pic18.pspec file may be copied/renamed and +# slightly modified to specify a the correct Register File Map. The following register definitions must be preserved: +# STATUS, STKPTR, PCLAT (PCL, PCLATH, PCLATU), TOS (TOSL, TOSH, TOSU), FSR0 (FSR0L, FSR0H), FSR1 (FSR1L, FSR1H), FSR2 (FSR2L, FSR2H), +# PROD (PRODL, PRODH) +# + +define DATA offset=0x0f60 size=1 [ + sfrF60 sfrF61 sfrF62 sfrF63 sfrF64 sfrF65 sfrF66 sfrF67 sfrF68 sfrF69 sfrF6A RCSTA2 TXSTA2 TXREG2 RCREG2 SPBREG2 + CCP5CON CCP5RL CCPR5H CCP4CON CCPR4L CCPR4H T4CON PR4 TMR4 sfrF79 sfrF7A sfrF7B sfrF7C sfrF7D sfrF7E sfrF7F + PORTA PORTB PORTC PORTD PORTE PORTF PORTG PORTH PORTJ LATA LATB LATC LATD LATE LATF LATG + LATH LATJ TRISA TRISB TRISC TRISD TRISE TRISF TRISG TRISH TRISJ sfrF9B MEMCON PIE1 PIR1 IPR1 + PIE2 PIR2 IPR2 PIE3 PIR3 IPR3 EECON1 EECON2 EEDATA EEADR EEADRH RCSTA1 TXSTA1 TXREG1 RCREG1 SPBRG1 + PSPCON T3CON TMR3L TMR3H CMCON CVRCON sfrFB6 CCP3CON CCP3RL CCP3RH CCP2CON CCPR2L CCPR2H CCP1CON CCPR1L CCPR1H + ADCON2 ADCON1 ADCON0 ADRESL ADRESH SSPCON2 SSPCON1 SSPSTAT SSPADD SSPBUF T2CON PR2 TMR2 T1CON TMR1L TMR1H + RCON WDTCON LVDCON OSCCON sfrFD4 T0CON TMR0L TMR0H STATUS FSR2L FSR2H PLUSW2 PREINC2 POSTDEC2 POSTINC2 INDF2 + BSR FSR1L FSR1H PLUSW1 PREINC1 POSTDEC1 POSTINC1 INDF1 WREG FSR0L FSR0H PLUSW0 PREINC0 POSTDEC0 POSTINC0 INDF0 + INTCON3 INTCON2 INTCON PRODL PRODH TABLAT TBLPTRL TBLPTRH TBLPTRU PCL PCLATH PCLATU .STKPTR TOSL TOSH TOSU +]; + +define DATA offset=0x0fbb size=2 [ CCPR2 ]; +define DATA offset=0x0fbe size=2 [ CCPR1 ]; +define DATA offset=0x0fc3 size=2 [ ADRES ]; +define DATA offset=0x0fce size=2 [ TMR1 ]; +define DATA offset=0x0fd6 size=2 [ TMR0 ]; +define DATA offset=0x0fd9 size=2 [ FSR2 ]; +define DATA offset=0x0fe1 size=2 [ FSR1 ]; +define DATA offset=0x0fe9 size=2 [ FSR0 ]; +define DATA offset=0x0ff3 size=2 [ PROD ]; + +define DATA offset=0x0ff6 size=3 [ TBLPTR ]; +define DATA offset=0x0ff9 size=3 [ PCLAT ]; +define DATA offset=0x0ffd size=3 [ TOS ]; + +@include "pic18_instructions.sinc" diff --git a/python/icicle/Ghidra/Processors/PIC/data/languages/pic18_instructions.sinc b/python/icicle/Ghidra/Processors/PIC/data/languages/pic18_instructions.sinc new file mode 100644 index 0000000..a5c5fa8 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PIC/data/languages/pic18_instructions.sinc @@ -0,0 +1,1700 @@ +# +# PIC-18 Instruction Section +# includes token definitions, macros, sub-constructors and instruction definitions +# + +# The bytes are imported from the file in a 16-bit little-endian word format. This, combined +# with the little-endian mode used by this language results in an unusual instruction format. +# The 16-bit instruction token uses what appears to be big endian bit numbering, whereas the +# 32-bit instruction token uses somewhat of a hybrid bit numbering (see below). + +# 16-bit instruction token uses big-endian bit numbering which agrees with +# instruction bit numbering with PIC documentation. +# 15-14-13-12-11-10-9-8-7-6-5-4-3-2-1-0 +define token instr16(16) + op4 = (12,15) + op5 = (11,15) + op6 = (10,15) + op8 = (8,15) + op12 = (4,15) + op16 = (0,15) + d = (9,9) + a = (8,8) + _xfsr = (6,7) + xfsr = (6,7) + f8_57 = (5,7) + f8 = (0,7) + freg = (0,7) + b3 = (9,11) + k8 = (0,7) + k6 = (0,5) + n11 = (0,10) signed + n8 = (0,7) signed + s_0 = (0,0) +; + +# 32-bit instruction token uses a hybrid bit numbering: +# Natural bit numbering (used by documentation): +# 31-30-29-28-27-26-25-24-23-22-21-20-19-18-17-16-15-14-13-12-11-10-09-08-07-06-05-04-03-02-01-00 +# Hybrid bit nubering used by token: +# 15-14-13-12-11-10-09-08-07-06-05-04-03-02-01-00-31-30-29-28-27-26-25-24-23-22-21-20-19-18-17-16 +define token instr32(32) + lop4 = (12,15) + lop5 = (11,15) + lop7 = (9,15) + lop8 = (8,15) + lop9 = (7,15) + lop10 = (6,15) + _fsr = (4,5) + fsr = (4,5) + kh = (0,3) + s_8 = (8,8) + n20_l = (0,7) # low order 8 bits of n20 + zs = (0,6) + fs_h = (8,11) + fs_57 = (5,7) + fs = (0,11) + fsreg = (0,7) + qual4 = (28,31) + qual8 = (24,31) + fd_h = (24,27) + fd_57 = (21,23) + fd = (16,27) + fdreg = (16,23) + kl = (16,23) + n20_h = (16,27) # high order 12 bits of n20 + zd = (16,22) +; + +attach variables [ freg fsreg fdreg ] [ + BAD _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + sfrF60 sfrF61 sfrF62 sfrF63 sfrF64 sfrF65 sfrF66 sfrF67 sfrF68 sfrF69 sfrF6A RCSTA2 TXSTA2 TXREG2 RCREG2 SPBREG2 + CCP5CON CCP5RL CCPR5H CCP4CON CCPR4L CCPR4H T4CON PR4 TMR4 sfrF79 sfrF7A sfrF7B sfrF7C sfrF7D sfrF7E sfrF7F + PORTA PORTB PORTC PORTD PORTE PORTF PORTG PORTH PORTJ LATA LATB LATC LATD LATE LATF LATG + LATH LATJ TRISA TRISB TRISC TRISD TRISE TRISF TRISG TRISH TRISJ sfrF9B MEMCON PIE1 PIR1 IPR1 + PIE2 PIR2 IPR2 PIE3 PIR3 IPR3 EECON1 EECON2 EEDATA EEADR EEADRH RCSTA1 TXSTA1 TXREG1 RCREG1 SPBRG1 + PSPCON T3CON TMR3L TMR3H CMCON CVRCON sfrFB6 CCP3CON CCP3RL CCP3RH CCP2CON CCPR2L CCPR2H CCP1CON CCPR1L CCPR1H + ADCON2 ADCON1 ADCON0 ADRESL ADRESH SSPCON2 SSPCON1 SSPSTAT SSPADD SSPBUF T2CON PR2 TMR2 T1CON TMR1L TMR1H + RCON WDTCON LVDCON OSCCON sfrFD4 T0CON TMR0L TMR0H STATUS FSR2L FSR2H PLUSW2 PREINC2 POSTDEC2 POSTINC2 INDF2 + BSR FSR1L FSR1H PLUSW1 PREINC1 POSTDEC1 POSTINC1 INDF1 WREG FSR0L FSR0H PLUSW0 PREINC0 POSTDEC0 POSTINC0 INDF0 + INTCON3 INTCON2 INTCON PRODL PRODH TABLAT TBLPTRL TBLPTRH TBLPTRU PCL PCLATH PCLATU STKPTR TOSL TOSH TOSU +]; + +# attach variables [ _fsr _xfsr ] [ FSR0 FSR1 FSR2 _ ]; + +# +# Special PIC-18 Operations +# + +# If stack is full (SP==0x1F) STKFUL gets set, if STVREN is set the processor will reset +#define pcodeop CheckStackFull; + +# If stack is empty (SP==0) STKUNF gets set, if STVREN is set the processor will reset +#define pcodeop CheckStackUnderflow; + +# Return a decimal adjusted value for the value provided (see DAW instruction) +define pcodeop decimalAdjust; + +# Perform a Master Clear Reset +define pcodeop reset; + +define pcodeop clearWatchDogTimer; + +define pcodeop sleep; + +# +# MACROS +# + +macro setResultFlags(result) { + N = (result s< 0); + Z = (result == 0); +} + +macro setAddCOverflowFlag(op1,op2) { + local tmpC = C & 1; + OV = scarry(op1,tmpC) || scarry(op2,op1 + tmpC); +} + +macro setAddCCarryFlag(op1,op2) { + local tmpC = C & 1; + C = carry(op1,tmpC) || carry(op2,op1 + tmpC); +} + +macro setAddCDigitCarryFlag(op1,op2) { + # op1 and op2 are assumed to be 8-bit values + local tmp1 = op1 << 4; + local tmp2 = op2 << 4; + local tmpDC = DC & 1; + DC = carry(tmp1,tmpDC) || carry(tmp2,tmp1 + tmpDC); +} + +macro setAddCFlags(op1,op2) { + setAddCCarryFlag(op1,op2); + setAddCDigitCarryFlag(op1,op2); + setAddCOverflowFlag(op1,op2); +} + +macro setAddFlags(op1,op2) { + C = carry(op1,op2); + DC = carry(op1<<4,op2<<4); + OV = scarry(op1,op2); +} + +macro setSubtractCOverflowFlag(op1,op2) { + local notC = ~(C & 1); + OV = sborrow(op1,notC) || sborrow(op2,op1 - notC); +} + +macro setSubtractCCarryFlag(op1,op2) { + local notC = ~(C & 1); + C = (op1 < notC) || (op2 < (op1 - notC)); +} + +macro setSubtractCDigitCarryFlag(op1,op2) { + # op1 and op2 are assumed to be 8-bit values + local notDC = ~(DC & 1); + local tmp1 = op1 << 4; + local tmp2 = op2 << 4; + local tmp3 = (tmp1 - notDC) << 4; + DC = (tmp1 < notDC) || (tmp2 < tmp3); +} + +macro setSubtractCFlags(op1,op2) { + setSubtractCCarryFlag(op1,op2); + setSubtractCDigitCarryFlag(op1,op2); + setSubtractCOverflowFlag(op1,op2); +} + +macro setSubtractFlags(op1,op2) { + # op1 and op2 are assumed to be 8-bit values + # NOTE: carry flag is SET if there is NO borrow + C = (op1 >= op2); + DC = ((op1<<4) < (op2<<4)); + OV = sborrow(op1,op2); +} + +macro push(val) { # TODO: Uncertain about this !! +# CheckStackFull(); + *[HWSTACK]:4 STKPTR = val; + STKPTR = STKPTR + 4; +} + +macro pop(rval) { # TODO: Uncertain about this !! +# CheckStackUnderflow(); + STKPTR = STKPTR - 4; + rval = *[HWSTACK]:4 STKPTR; +} + +# +# SUB-CONSTRUCTORS +# + +# PC register write - instruction must set PCLATH/PCL and perform branch operation +pcl: "PC" is a=0 & f8=0xf9 { export PCL; } + +# STATUS register +status: freg is a=0 & f8=0xd8 & freg { export STATUS; } + +# File Register specified by an 8-bit file register offset within Bank specified by BSR +fREGLoc: f8 is a=1 & f8 { # (Banked mode) + addr:2 = (zext(BSR) << 8) + f8; + export *[DATA]:1 addr; +} + +# File Register specified by an 8-bit offset within "Access Bank" +# The partitioning of the access bank may differ between specific PIC18 chips. +# Some partition at 0x80 (i.e., PIC18Cxx2), while more advanced PIC18 chips partition at 0x60 (i.e., PIC18Fxx20). +# This implementation partitions the access bank mode at 0x60. +# +# TODO: Need to add another language PIC18C that has the SFR start at 0xf80 +# +fREGLoc: f8 is a=0 & f8_57=0x0 & f8 { export *[DATA]:1 f8; } # 0x00-0x1f (Access mode) +fREGLoc: f8 is a=0 & f8_57=0x1 & f8 { export *[DATA]:1 f8; } # 0x20-0x3f (Access mode) +fREGLoc: f8 is a=0 & f8_57=0x2 & f8 { export *[DATA]:1 f8; } # 0x40-0x5f (Access mode) +fREGLoc: freg is a=0 & freg { export freg; } # 0xf60-0xfff (Access mode) + +# TOSL - access mirrored into stack space using STKPTR +fREGLoc: freg is a=0 & f8=0xfd & freg { + addr:1 = STKPTR + 1; + export *[HWSTACK]:1 addr; +} + +# TOSH - access mirrored into stack space using STKPTR +fREGLoc: freg is a=0 & f8=0xfe & freg { + addr:1 = STKPTR + 2; + export *[HWSTACK]:1 addr; +} + +# TOSU - access mirrored into stack space using STKPTR +fREGLoc: freg is a=0 & f8=0xff & freg { + addr:1 = STKPTR + 3; + export *[HWSTACK]:1 addr; +} + +# Indirect File Register access - INDF0 +fREGLoc: freg is a=0 & f8=0xef & freg { + addr:2 = FSR0; + export *[DATA]:1 addr; +} + +# Indirect File Register access - INDF1 +fREGLoc: freg is a=0 & f8=0xe7 & freg { + addr:2 = FSR1; + export *[DATA]:1 addr; +} + +# Indirect File Register access - INDF2 +fREGLoc: freg is a=0 & f8=0xdf & freg { + addr:2 = FSR2; + export *[DATA]:1 addr; +} + +# Post-increment File Register access - POSTINC0 +fREGLoc: freg is a=0 & f8=0xee & freg { + addr:2 = FSR0; + FSR0 = FSR0 + 1; + export *[DATA]:1 addr; +} + +# Post-increment File Register access - POSTINC1 +fREGLoc: freg is a=0 & f8=0xe6 & freg { + addr:2 = FSR1; + FSR1 = FSR1 + 1; + export *[DATA]:1 addr; +} + +# Post-increment File Register access - POSTINC2 +fREGLoc: freg is a=0 & f8=0xde & freg { + addr:2 = FSR2; + FSR2 = FSR2 + 1; + export *[DATA]:1 addr; +} + +# Post-decrement File Register access - POSTDEC0 +fREGLoc: freg is a=0 & f8=0xed & freg { + addr:2 = FSR0; + FSR0 = FSR0 - 1; + export *[DATA]:1 addr; +} + +# Post-decrement File Register access - POSTDEC1 +fREGLoc: freg is a=0 & f8=0xe5 & freg { + addr:2 = FSR1; + FSR1 = FSR1 - 1; + export *[DATA]:1 addr; +} + +# Post-decrement File Register access - POSTDEC2 +fREGLoc: freg is a=0 & f8=0xdd & freg { + addr:2 = FSR2; + FSR2 = FSR2 - 1; + export *[DATA]:1 addr; +} + +# Pre-increment File Register access - PREINC0 +fREGLoc: freg is a=0 & f8=0xec & freg { + FSR0 = FSR0 + 1; + addr:2 = FSR0; + export *[DATA]:1 addr; +} + +# Pre-increment File Register access - PREINC1 +fREGLoc: freg is a=0 & f8=0xe4 & freg { + FSR1 = FSR1 + 1; + addr:2 = FSR1; + export *[DATA]:1 addr; +} + +# Pre-increment File Register access - PREINC2 +fREGLoc: freg is a=0 & f8=0xdc & freg { + FSR2 = FSR2 + 1; + addr:2 = FSR2; + export *[DATA]:1 addr; +} + +# Pre-increment w/WREG-Offset File Register access - PLUSW0 +fREGLoc: freg is a=0 & f8=0xeb & freg { + FSR0 = FSR0 + 1; + addr:2 = FSR0 + sext(WREG); + export *[DATA]:1 addr; +} + +# Pre-increment w/WREG-Offset File Register access - PLUSW1 +fREGLoc: freg is a=0 & f8=0xe3 & freg { + FSR1 = FSR1 + 1; + addr:2 = FSR1 + sext(WREG); + export *[DATA]:1 addr; +} + +# Pre-increment w/WREG-Offset File Register access - PLUSW2 +fREGLoc: freg is a=0 & f8=0xdb & freg { + FSR2 = FSR2 + 1; + addr:2 = FSR2 + sext(WREG); + export *[DATA]:1 addr; +} + +# Direct File register data +srcREG: fREGLoc is fREGLoc { export fREGLoc; } + +# PCL read - latch PC into PCL, PCLATH, and PCLATU +srcREG: "PC" is a=0 & f8=0xf9 { + PCLAT = inst_start; + export PCL; +} + +# Destination register (either srcREG or WREG) +destREG: "0" is d=0 { export WREG; } +destREG: "1" is d=1 & srcREG { export srcREG; } +#destREG: "1" is d=1 & f8=0xf9 { +# # Storing to PCL must write the PC using both the stored PCL (PC<7:0>), PCLATH (PC<15:8>) and PCLATU (PC<21:16>) +# # The ADDWF and MOVWF definitions below have a specific case to handle this write to PCL +# export PCL; +#} + +# Destination operand representation (w: W register is destination; f: specified fREG is destination) +D: "w" is d=0 { } +D: "f" is d=1 { } + +# Source File Registers specified by a 12-bit absolute offsets within 32-bit instriction +srcREG32: fs is fs { export *[DATA]:1 fs; } # 0x000-0xeff +srcREG32: fs is fs_h=0xf & fs_57=0 & fs { export *[DATA]:1 fs; } # 0xf00-0xf1f +srcREG32: fs is fs_h=0xf & fs_57=1 & fs { export *[DATA]:1 fs; } # 0xf20-0xf3f +srcREG32: fs is fs_h=0xf & fs_57=2 & fs { export *[DATA]:1 fs; } # 0xf40-0xf5f +srcREG32: fsreg is fs_h=0xf & fsreg { export fsreg; } # 0xf60-0xfff + +# PCL read - latch PC into PCL, PCLATH, and PCLATU +srcREG32: "PC" is fs=0xff9 { + PCLAT = inst_start; + export PCL; +} + +# TOSL - access mirrored into stack space using STKPTR +srcREG32: fsreg is fs=0xffd & fsreg { + addr:1 = STKPTR + 1; + export *[HWSTACK]:1 addr; +} + +# TOSH - access mirrored into stack space using STKPTR +srcREG32: fsreg is fs=0xffe & fsreg { + addr:1 = STKPTR + 2; + export *[HWSTACK]:1 addr; +} + +# TOSU - access mirrored into stack space using STKPTR +srcREG32: fsreg is fs=0xfff & fsreg { + addr:1 = STKPTR + 3; + export *[HWSTACK]:1 addr; +} + +# Indirect File Register access - INDF0 +srcREG32: fsreg is fs=0xfef & fsreg { + addr:2 = FSR0; + export *[DATA]:1 addr; +} + +# Indirect File Register access - INDF1 +srcREG32: fsreg is fs=0xfe7 & fsreg { + addr:2 = FSR1; + export *[DATA]:1 addr; +} + +# Indirect File Register access - INDF2 +srcREG32: fsreg is fs=0xfdf & fsreg { + addr:2 = FSR2; + export *[DATA]:1 addr; +} + +# Post-increment File Register access - POSTINC0 +srcREG32: fsreg is fs=0xfee & fsreg { + addr:2 = FSR0; + FSR0 = FSR0 + 1; + export *[DATA]:1 addr; +} + +# Post-increment File Register access - POSTINC1 +srcREG32: fsreg is fs=0xfe6 & fsreg { + addr:2 = FSR1; + FSR1 = FSR1 + 1; + export *[DATA]:1 addr; +} + +# Post-increment File Register access - POSTINC2 +srcREG32: fsreg is fs=0xfde & fsreg { + addr:2 = FSR2; + FSR2 = FSR2 + 1; + export *[DATA]:1 addr; +} + +# Post-decrement File Register access - POSTDEC0 +srcREG32: fsreg is fs=0xfed & fsreg { + addr:2 = FSR0; + FSR0 = FSR0 - 1; + export *[DATA]:1 addr; +} + +# Post-decrement File Register access - POSTDEC1 +srcREG32: fsreg is fs=0xfe5 & fsreg { + addr:2 = FSR1; + FSR1 = FSR1 - 1; + export *[DATA]:1 addr; +} + +# Post-decrement File Register access - POSTDEC2 +srcREG32: fsreg is fs=0xfdd & fsreg { + addr:2 = FSR2; + FSR2 = FSR2 - 1; + export *[DATA]:1 addr; +} + +# Pre-increment File Register access - PREINC0 +srcREG32: fsreg is fs=0xfec & fsreg { + FSR0 = FSR0 + 1; + addr:2 = FSR0; + export *[DATA]:1 addr; +} + +# Pre-increment File Register access - PREINC1 +srcREG32: fsreg is fs=0xfe4 & fsreg { + FSR1 = FSR1 + 1; + addr:2 = FSR1; + export *[DATA]:1 addr; +} + +# Pre-increment File Register access - PREINC2 +srcREG32: fsreg is fs=0xfdc & fsreg { + FSR2 = FSR2 + 1; + addr:2 = FSR2; + export *[DATA]:1 addr; +} + +# Pre-increment w/WREG-Offset File Register access - PLUSW0 +srcREG32: fsreg is fs=0xfeb & fsreg { + FSR0 = FSR0 + 1; + addr:2 = FSR0 + sext(WREG); + export *[DATA]:1 addr; +} + +# Pre-increment w/WREG-Offset File Register access - PLUSW1 +srcREG32: fsreg is fs=0xfe3 & fsreg { + FSR1 = FSR1 + 1; + addr:2 = FSR1 + sext(WREG); + export *[DATA]:1 addr; +} + +# Pre-increment w/WREG-Offset File Register access - PLUSW2 +srcREG32: fsreg is fs=0xfdb & fsreg { + FSR2 = FSR2 + 1; + addr:2 = FSR2 + sext(WREG); + export *[DATA]:1 addr; +} + +# Destination File Registers specified by a 12-bit absolute offsets within 32-bit instriction +destREG32: fd is fd { export *[DATA]:1 fd; } # 0x000-0xeff +destREG32: fd is fd_h=0xf & fd_57=0 & fd { export *[DATA]:1 fd; } # 0xf00-0xf1f +destREG32: fd is fd_h=0xf & fd_57=1 & fd { export *[DATA]:1 fd; } # 0xf20-0xf3f +destREG32: fd is fd_h=0xf & fd_57=2 & fd { export *[DATA]:1 fd; } # 0xf40-0xf5f +destREG32: fdreg is fd_h=0xf & fdreg { export fdreg; } # 0xf60-0xfff + +#destREG32: "PCL" is fd=0xff9 { +# # Storing to PCL must write the PC using both the stored PCL (PC<7:0>), PCLATH (PC<15:8>) and PCLATU (PC<21:16>) +# # The MOVFF and MOVSF definitions below have a specific case to handle this write to PCL +# export PCL; +#} + +# TOSL - access mirrored into stack space using STKPTR +destREG32: fdreg is fd=0xffd & fdreg { + addr:1 = STKPTR + 1; + export *[HWSTACK]:1 addr; +} + +# TOSH - access mirrored into stack space using STKPTR +destREG32: fdreg is fd=0xffe & fdreg { + addr:1 = STKPTR + 2; + export *[HWSTACK]:1 addr; +} + +# TOSU - access mirrored into stack space using STKPTR +destREG32: fdreg is fd=0xfff & fdreg { + addr:1 = STKPTR + 3; + export *[HWSTACK]:1 addr; +} + +# Indirect File Register access - INDF0 +destREG32: fdreg is fd=0xfef & fdreg { + addr:2 = FSR0; + export *[DATA]:1 addr; +} + +# Indirect File Register access - INDF1 +destREG32: fdreg is fd=0xfe7 & fdreg { + addr:2 = FSR1; + export *[DATA]:1 addr; +} + +# Indirect File Register access - INDF2 +destREG32: fdreg is fd=0xfdf & fdreg { + addr:2 = FSR2; + export *[DATA]:1 addr; +} + +# Post-increment File Register access - POSTINC0 +destREG32: fdreg is fd=0xfee & fdreg { + addr:2 = FSR0; + FSR0 = FSR0 + 1; + export *[DATA]:1 addr; +} + +# Post-increment File Register access - POSTINC1 +destREG32: fdreg is fd=0xfe6 & fdreg { + addr:2 = FSR1; + FSR1 = FSR1 + 1; + export *[DATA]:1 addr; +} + +# Post-increment File Register access - POSTINC2 +destREG32: fdreg is fd=0xfde & fdreg { + addr:2 = FSR2; + FSR2 = FSR2 + 1; + export *[DATA]:1 addr; +} + +# Post-decrement File Register access - POSTDEC0 +destREG32: fdreg is fd=0xfed & fdreg { + addr:2 = FSR0; + FSR0 = FSR0 - 1; + export *[DATA]:1 addr; +} + +# Post-decrement File Register access - POSTDEC1 +destREG32: fdreg is fd=0xfe5 & fdreg { + addr:2 = FSR1; + FSR1 = FSR1 - 1; + export *[DATA]:1 addr; +} + +# Post-decrement File Register access - POSTDEC2 +destREG32: fdreg is fd=0xfdd & fdreg { + addr:2 = FSR2; + FSR2 = FSR2 - 1; + export *[DATA]:1 addr; +} + +# Pre-increment File Register access - PREINC0 +destREG32: fdreg is fd=0xfec & fdreg { + FSR0 = FSR0 + 1; + addr:2 = FSR0; + export *[DATA]:1 addr; +} + +# Pre-increment File Register access - PREINC1 +destREG32: fdreg is fd=0xfe4 & fdreg { + FSR1 = FSR1 + 1; + addr:2 = FSR1; + export *[DATA]:1 addr; +} + +# Pre-increment File Register access - PREINC2 +destREG32: fdreg is fd=0xfdc & fdreg { + FSR2 = FSR2 + 1; + addr:2 = FSR2; + export *[DATA]:1 addr; +} + +# Pre-increment w/WREG-Offset File Register access - PLUSW0 +destREG32: fdreg is fd=0xfeb & fdreg { + FSR0 = FSR0 + 1; + addr:2 = FSR0 + sext(WREG); + export *[DATA]:1 addr; +} + +# Pre-increment w/WREG-Offset File Register access - PLUSW1 +destREG32: fdreg is fd=0xfe3 & fdreg { + FSR1 = FSR1 + 1; + addr:2 = FSR1 + sext(WREG); + export *[DATA]:1 addr; +} + +# Pre-increment w/WREG-Offset File Register access - PLUSW2 +destREG32: fdreg is fd=0xfdb & fdreg { + FSR2 = FSR2 + 1; + addr:2 = FSR2 + sext(WREG); + export *[DATA]:1 addr; +} + +# Absolute 20-bit instruction location constructed from nl:8 and nh:12 +absAddr21: nLoc is n20_h & n20_l [ nLoc = (n20_h << 9) + (n20_l << 1); ] { export *[CODE]:2 nLoc; } + +# Relative 8-bit and 11-bit instruction offsets +relAddr8: nLoc is n8 [ nLoc = inst_next + (n8 << 1); ] { export *[CODE]:2 nLoc; } +relAddr11: nLoc is n11 [ nLoc = inst_next + (n11 << 1); ] { export *[CODE]:2 nLoc; } + +# Skip instruction address (could jump into middle of 32-bit instruction which appears as NOP) +skipInst: inst_skip is op16 [ inst_skip = inst_next + 2; ] {export *[CODE]:2 inst_skip; } + +# Immediate Data (Literal operation) +imm6: "#"k6 is k6 { export *[const]:1 k6; } +imm8: "#"k8 is k8 { export *[const]:1 k8; } +imm12: "#"kVal is kl & kh [ kVal = (kh << 8) + kl; ] { export *[const]:2 kVal; } + +# Bit identifier +bit: "#"b3 is b3 { export *[const]:1 b3; } + +# FSR Register (see LFSR) +FSRn: "FSR0" is fsr=0 & _fsr { export FSR0; } +FSRn: "FSR1" is fsr=1 & _fsr { export FSR1; } +FSRn: "FSR2" is fsr=2 & _fsr { export FSR2; } + +# FSR Register (see Extended Instructions) +xFSRn: "FSR0" is xfsr=0 & _xfsr { export FSR0; } +xFSRn: "FSR1" is xfsr=1 & _xfsr { export FSR1; } +xFSRn: "FSR2" is xfsr=2 & _xfsr { export FSR2; } + +# Source and Destination FSR2 Indexed Operand +ZS: zs"[FSR2]" is zs { fsLoc:2 = FSR2 + zs; export *[DATA]:1 fsLoc; } +ZD: zd"[FSR2]" is zd { fdLoc:2 = FSR2 + zd; export *[DATA]:1 fdLoc; } + +# Access Bank mode +A: "ACCESS" is a=0 { } +A: "BANKED" is a=1 { } + +# +# BYTE-ORIENTED FILE REGISTER OPERATIONS +# + +:ADDWF srcREG, D, A is op6=0x09 & srcREG & A & destREG & D { + # 0010 01da ffff ffff + # 0010 0100 0000 0000 -> ADDWF DAT_DATA_0000, w, ACCESS + # 0010 0101 0000 0000 -> ADDWF REG0x0, w, BANKED + # 0010 0100 1101 1000 -> ADDWF STATUS, w, ACCESS + # 0010 0101 1101 1000 -> ADDWF REG0xD8, w, BANKED + # 0010 0110 0000 0000 -> ADDWF DAT_DATA_0000, f, ACCESS + # 0010 0111 0000 0000 -> ADDWF REG0x0, f, BANKED + # 0010 0110 1101 1000 -> ADDWF STATUS, f, ACCESS + # 0010 0111 1101 1000 -> ADDWF REG0xD8, f, BANKED + # 0010 0100 1111 1001 -> ADDWF PC, w, ACCESS + tmp:1 = srcREG; # read only once! + setAddFlags(tmp, WREG); + tmp = tmp + WREG; + destREG = tmp; + setResultFlags(tmp); +} + +:ADDWF pcl, D, A is op6=0x09 & A & D & d=1 & pcl { + # 0010 01da ffff ffff + # 0010 0110 1111 1001 -> ADDWF PC, f, ACCESS + addr:3 = inst_start; + PCLAT = addr; + addrHi:2 = addr(1); + addrLo:1 = addr:1; + tmpW:1 = WREG; + setAddFlags(addrLo, tmpW); + addrLo = addrLo + tmpW; + addr = (zext(addrHi) << 8) + zext(addrLo); + setResultFlags(addrLo); + goto [addr]; +} + +:ADDWFC srcREG, D, A is op6=0x08 & srcREG & destREG & D & A { + # 0010 00da ffff ffff + # 0010 0000 0000 0000 -> ADDWFC DAT_DATA_0000, w, ACCESS + # 0010 0001 0000 0000 -> ADDWFC REG0x0, w, BANKED + # 0010 0000 1101 1000 -> ADDWFC STATUS, w, ACCESS + # 0010 0001 1101 1000 -> ADDWFC REG0xD8, w, BANKED + # 0010 0010 0000 0000 -> ADDWFC DAT_DATA_0000, f, ACCESS + # 0010 0011 0000 0000 -> ADDWFC REG0x0, f, BANKED + # 0010 0010 1101 1000 -> ADDWFC STATUS, f, ACCESS + # 0010 0011 1101 1000 -> ADDWFC REG0xD8, f, BANKED + local tmpC = C & 1; + tmp:1 = srcREG; + setAddCFlags(tmp, WREG); + tmp = tmp + WREG + tmpC; + destREG = tmp; + setResultFlags(tmp); +} + +:ANDWF srcREG, D, A is op6=0x05 & srcREG & destREG & D & A { + # 0001 01da ffff ffff + # 0001 0100 0000 0000 -> ANDWF DAT_DATA_0000, w, ACCESS + # 0001 0101 0000 0000 -> ANDWF REG0x0, w, BANKED + # 0001 0100 1101 1000 -> ANDWF STATUS, w, ACCESS + # 0001 0101 1101 1000 -> ANDWF REG0xD8, w, BANKED + # 0001 0110 0000 0000 -> ANDWF DAT_DATA_0000, f, ACCESS + # 0001 0111 0000 0000 -> ANDWF REG0x0, f, BANKED + # 0001 0110 1101 1000 -> ANDWF STATUS, f, ACCESS + # 0001 0111 1101 1000 -> ANDWF REG0xD8, f, BANKED + tmp:1 = srcREG & WREG; + destREG = tmp; + setResultFlags(tmp); +} + +:CLRF srcREG, A is op6=0x1a & d=1 & srcREG & A { + # 0110 101a ffff ffff + # 0110 1010 0000 0000 -> CLRF DAT_DATA_0000, 0 + # 0110 1011 0000 0000 -> CLRF REG0x0, 1 + # 0110 1010 1101 1000 -> CLRF STATUS, 0 + # 0110 1011 1101 1000 -> CLRF REG0xD8, 1 + srcREG = 0; + Z = 1; +} + +:COMF srcREG, D, A is op6=0x07 & srcREG & destREG & D & A { + # 0001 11da ffff ffff + # 0001 1100 0000 0000 -> COMF DAT_DATA_0000, w, ACCESS + # 0001 1101 0000 0000 -> COMF REG0x0, w, BANKED + # 0001 1100 1101 1000 -> COMF STATUS, w, ACCESS + # 0001 1101 1101 1000 -> COMF REG0xD8, w, BANKED + # 0001 1110 0000 0000 -> COMF DAT_DATA_0000, f, ACCESS + # 0001 1111 0000 0000 -> COMF REG0x0, f, BANKED + # 0001 1110 1101 1000 -> COMF STATUS, f, ACCESS + # 0001 1111 1101 1000 -> COMF REG0xD8, f, BANKED + tmp:1 = ~srcREG; + destREG = tmp; + setResultFlags(tmp); +} + +:CPFSEQ srcREG, A is op6=0x18 & d=1 & srcREG & A & skipInst { + # 0110 001a ffff ffff + # 0110 0010 0000 0000 -> CPFSEQ DAT_DATA_0000, 0 + # 0110 0011 0000 0000 -> CPFSEQ REG0x0, 1 + # 0110 0010 1101 1000 -> CPFSEQ STATUS, 0 + # 0110 0011 1101 1000 -> CPFSEQ REG0xD8, 1 + if (srcREG == WREG) goto skipInst; +} + +:CPFSGT srcREG, A is op6=0x19 & d=0 & srcREG & A & skipInst { + # 0110 010a ffff ffff + # 0110 0100 0000 0000 -> CPFSGT DAT_DATA_0000, 0 + # 0110 0101 0000 0000 -> CPFSGT REG0x0, 1 + # 0110 0100 1101 1000 -> CPFSGT STATUS, 0 + # 0110 0101 1101 1000 -> CPFSGT REG0xD8, 1 + if (srcREG > WREG) goto skipInst; +} + +:CPFSLT srcREG, A is op6=0x18 & d=0 & srcREG & A & skipInst { + # 0110 000a ffff ffff + # 0110 0000 0000 0000 -> CPFSLT DAT_DATA_0000, 0 + # 0110 0001 0000 0000 -> CPFSLT REG0x0, 1 + # 0110 0000 1101 1000 -> CPFSLT STATUS, 0 + # 0110 0001 1101 1000 -> CPFSLT REG0xD8, 1 + if (srcREG < WREG) goto skipInst; +} + +:DECF srcREG, D, A is op6=0x01 & srcREG & destREG & D & A { + # 0000 01da ffff ffff + # 0000 0100 0000 0000 -> DECF DAT_DATA_0000, w, ACCESS + # 0000 0101 0000 0000 -> DECF REG0x0, w, BANKED + # 0000 0100 1101 1000 -> DECF STATUS, w, ACCESS + # 0000 0101 1101 1000 -> DECF REG0xD8, w, BANKED + # 0000 0110 0000 0000 -> DECF DAT_DATA_0000, f, ACCESS + # 0000 0111 0000 0000 -> DECF REG0x0, f, BANKED + # 0000 0110 1101 1000 -> DECF STATUS, f, ACCESS + # 0000 0111 1101 1000 -> DECF REG0xD8, f, BANKED + tmp:1 = srcREG; + setSubtractFlags(tmp, 1); + tmp = tmp - 1; + destREG = tmp; + setResultFlags(tmp); +} + +:DECFSZ srcREG, D, A is op6=0x0b & srcREG & destREG & D & A & skipInst { + # 0010 11da ffff ffff + # 0010 1100 0000 0000 -> DECFSZ DAT_DATA_0000, w, ACCESS + # 0010 1101 0000 0000 -> DECFSZ REG0x0, w, BANKED + # 0010 1100 1101 1000 -> DECFSZ STATUS, w, ACCESS + # 0010 1101 1101 1000 -> DECFSZ REG0xD8, w, BANKED + # 0010 1110 0000 0000 -> DECFSZ DAT_DATA_0000, f, ACCESS + # 0010 1111 0000 0000 -> DECFSZ REG0x0, f, BANKED + # 0010 1110 1101 1000 -> DECFSZ STATUS, f, ACCESS + # 0010 1111 1101 1000 -> DECFSZ REG0xD8, f, BANKED + tmp:1 = srcREG - 1; + destREG = tmp; + if (tmp == 0) goto skipInst; +} + +:DCFSNZ srcREG, D, A is op6=0x13 & srcREG & destREG & D & A & skipInst { + # 0100 11da ffff ffff + # 0100 1100 0000 0000 -> DCFSNZ DAT_DATA_0000, w, ACCESS + # 0100 1101 0000 0000 -> DCFSNZ REG0x0, w, BANKED + # 0100 1100 1101 1000 -> DCFSNZ STATUS, w, ACCESS + # 0100 1101 1101 1000 -> DCFSNZ REG0xD8, w, BANKED + # 0100 1110 0000 0000 -> DCFSNZ DAT_DATA_0000, f, ACCESS + # 0100 1111 0000 0000 -> DCFSNZ REG0x0, f, BANKED + # 0100 1110 1101 1000 -> DCFSNZ STATUS, f, ACCESS + # 0100 1111 1101 1000 -> DCFSNZ REG0xD8, f, BANKED + tmp:1 = srcREG - 1; + destREG = tmp; + if (tmp != 0) goto skipInst; +} + +:INCF srcREG, D, A is op6=0x0a & srcREG & destREG & D & A { + # 0010 10da ffff ffff + # 0010 1000 0000 0000 -> INCF DAT_DATA_0000, w, ACCESS + # 0010 1001 0000 0000 -> INCF REG0x0, w, BANKED + # 0010 1000 1101 1000 -> INCF STATUS, w, ACCESS + # 0010 1001 1101 1000 -> INCF REG0xD8, w, BANKED + # 0010 1010 0000 0000 -> INCF DAT_DATA_0000, f, ACCESS + # 0010 1011 0000 0000 -> INCF REG0x0, f, BANKED + # 0010 1010 1101 1000 -> INCF STATUS, f, ACCESS + # 0010 1011 1101 1000 -> INCF REG0xD8, f, BANKED + tmp:1 = srcREG; # read once only! + setAddFlags(tmp, 1); + tmp = tmp + 1; + destREG = tmp; + setResultFlags(tmp); +} + +:INCFSZ srcREG, D, A is op6=0x0f & srcREG & destREG & D & A & skipInst { + # 0011 11da ffff ffff + # 0011 1100 0000 0000 -> INCFSZ DAT_DATA_0000, w, ACCESS + # 0011 1101 0000 0000 -> INCFSZ REG0x0, w, BANKED + # 0011 1100 1101 1000 -> INCFSZ STATUS, w, ACCESS + # 0011 1101 1101 1000 -> INCFSZ REG0xD8, w, BANKED + # 0011 1110 0000 0000 -> INCFSZ DAT_DATA_0000, f, ACCESS + # 0011 1111 0000 0000 -> INCFSZ REG0x0, f, BANKED + # 0011 1110 1101 1000 -> INCFSZ STATUS, f, ACCESS + # 0011 1111 1101 1000 -> INCFSZ REG0xD8, f, BANKED + tmp:1 = srcREG + 1; + destREG = tmp; + if (tmp == 0) goto skipInst; +} + +:INFSNZ srcREG, D, A is op6=0x12 & srcREG & destREG & D & A & skipInst { + # 0100 10da ffff ffff + # 0100 1000 0000 0000 -> INFSNZ DAT_DATA_0000, w, ACCESS + # 0100 1001 0000 0000 -> INFSNZ REG0x0, w, BANKED + # 0100 1000 1101 1000 -> INFSNZ STATUS, w, ACCESS + # 0100 1001 1101 1000 -> INFSNZ REG0xD8, w, BANKED + # 0100 1010 0000 0000 -> INFSNZ DAT_DATA_0000, f, ACCESS + # 0100 1011 0000 0000 -> INFSNZ REG0x0, f, BANKED + # 0100 1010 1101 1000 -> INFSNZ STATUS, f, ACCESS + # 0100 1011 1101 1000 -> INFSNZ REG0xD8, f, BANKED + tmp:1 = srcREG + 1; + destREG = tmp; + if (tmp != 0) goto skipInst; +} + +:IORWF srcREG, D, A is op6=0x04 & srcREG & destREG & D & A { + # 0001 00da ffff ffff + # 0001 0000 0000 0000 -> IORWF DAT_DATA_0000, w, ACCESS + # 0001 0001 0000 0000 -> IORWF REG0x0, w, BANKED + # 0001 0000 1101 1000 -> IORWF STATUS, w, ACCESS + # 0001 0001 1101 1000 -> IORWF REG0xD8, w, BANKED + # 0001 0010 0000 0000 -> IORWF DAT_DATA_0000, f, ACCESS + # 0001 0011 0000 0000 -> IORWF REG0x0, f, BANKED + # 0001 0010 1101 1000 -> IORWF STATUS, f, ACCESS + # 0001 0011 1101 1000 -> IORWF REG0xD8, f, BANKED + tmp:1 = srcREG | WREG; + destREG = tmp; + setResultFlags(tmp); +} + +:MOVF srcREG, D, A is op6=0x14 & srcREG & destREG & D & A { + # 0101 00da ffff ffff + # 0101 0000 0000 0000 -> MOVF DAT_DATA_0000, w, ACCESS + # 0101 0001 0000 0000 -> MOVF REG0x0, w, BANKED + # 0101 0000 1101 1000 -> MOVF STATUS, w, ACCESS + # 0101 0001 1101 1000 -> MOVF REG0xD8, w, BANKED + # 0101 0010 0000 0000 -> MOVF DAT_DATA_0000, f, ACCESS + # 0101 0011 0000 0000 -> MOVF REG0x0, f, BANKED + # 0101 0010 1101 1000 -> MOVF STATUS, f, ACCESS + # 0101 0011 1101 1000 -> MOVF REG0xD8, f, BANKED + + # 0101 0000 1110 1111 -> MOVF INDF0, w, ACCESS + # 0101 0000 1110 0111 -> MOVF INDF1, w, ACCESS + # 0101 0000 1101 1111 -> MOVF INDF2, w, ACCESS + + tmp:1 = srcREG; + destREG = tmp; + setResultFlags(tmp); +} + +:MOVFF srcREG32, destREG32 is lop4=0x0c & srcREG32 & qual4=0x0f & destREG32 { + # 1100 ssss ssss ssss 1111 dddd dddd dddd + # 1100 0000 0000 0000 1111 1111 1101 1000 -> MOVFF DAT_DATA_0000, STATUS + destREG32 = srcREG32; +} + +:MOVFF srcREG32, destREG32 is lop4=0x0c & srcREG32 & qual4=0x0f & destREG32 & fd=0xff9 { + # 1100 ssss ssss ssss 1111 dddd dddd dddd + # 1100 0000 0000 0000 1111 1111 1111 1001 -> MOVFF DAT_DATA_0000, PCL + addr:3 = (zext(PCLATU) << 16) + (zext(PCLATH) << 8) + zext(srcREG32); + goto [addr]; +} + +:MOVWF srcREG, A is op6=0x1b & d=0x1 & srcREG & A { + # 0110 111a ffff ffff + # 0110 1110 0000 0000 -> MOVWF DAT_DATA_0000, 0 + # 0110 1111 0000 0000 -> MOVWF REG0x0, 1 + # 0110 1110 1101 1000 -> MOVWF STATUS, 0 + # 0110 1111 1101 1000 -> MOVWF REG0xD8, 1 + srcREG = WREG; +} + +:MOVWF pcl, A is op6=0x1b & A & pcl { + # 0110 111a ffff ffff + # 0110 1110 1111 1001 -> MOVWF PCL, 0 + addr:3 = (zext(PCLATU) << 16) + (zext(PCLATH) << 8) + zext(WREG); + goto [addr]; +} + +:MULWF srcREG, A is op6=0x00 & d=0x1 & srcREG & A { + # 0000 001a ffff ffff + # 0000 0010 0000 0000 -> MULWF DAT_DATA_0000, 0 + # 0000 0011 0000 0000 -> MULWF REG0x0, 1 + # 0000 0010 1101 1000 -> MULWF STATUS, 0 + # 0000 0011 1101 1000 -> MULWF REG0xD8, 1 + tmp1:2 = zext(srcREG); + tmp2:2 = zext(WREG); + PROD = tmp1 * tmp2; +} + +:NEGF srcREG, A is op6=0x1b & d=0x0 & srcREG & A { + # 0110 110a ffff ffff + # 0110 1100 0000 0000 -> NEGF DAT_DATA_0000, 0 + # 0110 1101 0000 0000 -> NEGF REG0x0, 1 + # 0110 1100 1101 1000 -> NEGF STATUS, 0 + # 0110 1101 1101 1000 -> NEGF REG0xD8, 1 + tmp:1 = -srcREG; + srcREG = tmp; + C = (tmp s> 0); + OV = sborrow(0,tmp); + setResultFlags(tmp); +} + +:RLCF srcREG, D, A is op6=0x0d & srcREG & destREG & D & A { + # 0011 01da ffff ffff + # 0011 0100 0000 0000 -> RLCF DAT_DATA_0000, w, ACCESS + # 0011 0101 0000 0000 -> RLCF REG0x0, w, BANKED + # 0011 0100 1101 1000 -> RLCF STATUS, w, ACCESS + # 0011 0101 1101 1000 -> RLCF REG0xD8, w, BANKED + # 0011 0110 0000 0000 -> RLCF DAT_DATA_0000, f, ACCESS + # 0011 0111 0000 0000 -> RLCF REG0x0, f, BANKED + # 0011 0110 1101 1000 -> RLCF STATUS, f, ACCESS + # 0011 0111 1101 1000 -> RLCF REG0xD8, f, BANKED + local tmpC = C & 1; + tmp:1 = srcREG; + C = (tmp s< 0); + tmp = (tmp << 1) | tmpC; + destREG = tmp; + setResultFlags(tmp); +} + +:RLNCF srcREG, D, A is op6=0x11 & srcREG & destREG & D & A { + # 0100 01da ffff ffff + # 0100 0100 0000 0000 -> RLNCF DAT_DATA_0000, w, ACCESS + # 0100 0101 0000 0000 -> RLNCF REG0x0, w, BANKED + # 0100 0100 1101 1000 -> RLNCF STATUS, w, ACCESS + # 0100 0101 1101 1000 -> RLNCF REG0xD8, w, BANKED + # 0100 0110 0000 0000 -> RLNCF DAT_DATA_0000, f, ACCESS + # 0100 0111 0000 0000 -> RLNCF REG0x0, f, BANKED + # 0100 0110 1101 1000 -> RLNCF STATUS, f, ACCESS + # 0100 0111 1101 1000 -> RLNCF REG0xD8, f, BANKED + tmp:1 = srcREG << 1; + destREG = tmp; + setResultFlags(tmp); +} + +:RRCF srcREG, D, A is op6=0x0c & srcREG & destREG & D & A { + # 0011 00da ffff ffff + # 0011 0000 0000 0000 -> RRCF DAT_DATA_0000, w, ACCESS + # 0011 0001 0000 0000 -> RRCF REG0x0, w, BANKED + # 0011 0000 1101 1000 -> RRCF STATUS, w, ACCESS + # 0011 0001 1101 1000 -> RRCF REG0xD8, w, BANKED + # 0011 0010 0000 0000 -> RRCF DAT_DATA_0000, f, ACCESS + # 0011 0011 0000 0000 -> RRCF REG0x0, f, BANKED + # 0011 0010 1101 1000 -> RRCF STATUS, f, ACCESS + # 0011 0011 1101 1000 -> RRCF REG0xD8, f, BANKED + local tmpC = C << 7; + tmp:1 = srcREG; + C = (tmp & 1); + tmp = (tmp >> 1) | tmpC; + destREG = tmp; + setResultFlags(tmp); +} + +:RRNCF srcREG, D, A is op6=0x10 & srcREG & destREG & D & A { + # 0100 00da ffff ffff + # 0100 0000 0000 0000 -> RRNCF DAT_DATA_0000, w, ACCESS + # 0100 0001 0000 0000 -> RRNCF REG0x0, w, BANKED + # 0100 0000 1101 1000 -> RRNCF STATUS, w, ACCESS + # 0100 0001 1101 1000 -> RRNCF REG0xD8, w, BANKED + # 0100 0010 0000 0000 -> RRNCF DAT_DATA_0000, f, ACCESS + # 0100 0011 0000 0000 -> RRNCF REG0x0, f, BANKED + # 0100 0010 1101 1000 -> RRNCF STATUS, f, ACCESS + # 0100 0011 1101 1000 -> RRNCF REG0xD8, f, BANKED + tmp:1 = srcREG >> 1; + destREG = tmp; + setResultFlags(tmp); +} + +:SETF srcREG, A is op6=0x1a & d=0x0 & srcREG & A { + # 0110 100a ffff ffff + # 0110 1000 0000 0000 -> SETF DAT_DATA_0000, 0 + # 0110 1001 0000 0000 -> SETF REG0x0, 1 + # 0110 1000 1101 1000 -> SETF STATUS, 0 + # 0110 1001 1101 1000 -> SETF REG0xD8, 1 + srcREG = 0xff; +} + +:SUBFWB srcREG, D, A is op6=0x15 & srcREG & destREG & D & A { + # 0101 01da ffff ffff + # 0101 0100 0000 0000 -> SUBFWB DAT_DATA_0000, w, ACCESS + # 0101 0101 0000 0000 -> SUBFWB REG0x0, w, BANKED + # 0101 0100 1101 1000 -> SUBFWB STATUS, w, ACCESS + # 0101 0101 1101 1000 -> SUBFWB REG0xD8, w, BANKED + # 0101 0110 0000 0000 -> SUBFWB DAT_DATA_0000, f, ACCESS + # 0101 0111 0000 0000 -> SUBFWB REG0x0, f, BANKED + # 0101 0110 1101 1000 -> SUBFWB STATUS, f, ACCESS + # 0101 0111 1101 1000 -> SUBFWB REG0xD8, f, BANKED + local notC = ~(C & 1); + tmp:1 = srcREG; + setSubtractCFlags(WREG, tmp); + tmp = WREG - tmp - notC; + destREG = tmp; + setResultFlags(tmp); +} + +:SUBWF srcREG, D, A is op6=0x17 & srcREG & destREG & D & A { + # 0101 11da ffff ffff + # 0101 1100 0000 0000 -> SUBWF DAT_DATA_0000, w, ACCESS + # 0101 1101 0000 0000 -> SUBWF REG0x0, w, BANKED + # 0101 1100 1101 1000 -> SUBWF STATUS, w, ACCESS + # 0101 1101 1101 1000 -> SUBWF REG0xD8, w, BANKED + # 0101 1110 0000 0000 -> SUBWF DAT_DATA_0000, f, ACCESS + # 0101 1111 0000 0000 -> SUBWF REG0x0, f, BANKED + # 0101 1110 1101 1000 -> SUBWF STATUS, f, ACCESS + # 0101 1111 1101 1000 -> SUBWF REG0xD8, f, BANKED + tmp:1 = srcREG; + setSubtractFlags(tmp, WREG); + tmp = tmp - WREG; + destREG = tmp; + setResultFlags(tmp); +} + +:SUBWFB srcREG, D, A is op6=0x16 & srcREG & destREG & D & A { + # 0101 10da ffff ffff + # 0101 1000 0000 0000 -> SUBWFB DAT_DATA_0000, w, ACCESS + # 0101 1001 0000 0000 -> SUBWFB REG0x0, w, BANKED + # 0101 1000 1101 1000 -> SUBWFB STATUS, w, ACCESS + # 0101 1001 1101 1000 -> SUBWFB REG0xD8, w, BANKED + # 0101 1010 0000 0000 -> SUBWFB DAT_DATA_0000, f, ACCESS + # 0101 1011 0000 0000 -> SUBWFB REG0x0, f, BANKED + # 0101 1010 1101 1000 -> SUBWFB STATUS, f, ACCESS + # 0101 1011 1101 1000 -> SUBWFB REG0xD8, f, BANKED + local notC = ~(C & 1); + tmp:1 = srcREG; + setSubtractCFlags(tmp, WREG); + tmp = tmp - WREG - notC; + destREG = tmp; + setResultFlags(tmp); +} + +:SWAPF srcREG, D, A is op6=0x0e & srcREG & destREG & D & A { + # 0011 10da ffff ffff + # 0011 1000 0000 0000 -> SWAPF DAT_DATA_0000, w, ACCESS + # 0011 1001 0000 0000 -> SWAPF REG0x0, w, BANKED + # 0011 1000 1101 1000 -> SWAPF STATUS, w, ACCESS + # 0011 1001 1101 1000 -> SWAPF REG0xD8, w, BANKED + # 0011 1010 0000 0000 -> SWAPF DAT_DATA_0000, f, ACCESS + # 0011 1011 0000 0000 -> SWAPF REG0x0, f, BANKED + # 0011 1010 1101 1000 -> SWAPF STATUS, f, ACCESS + # 0011 1011 1101 1000 -> SWAPF REG0xD8, f, BANKED + tmp:1 = srcREG; + destREG = (tmp << 4) | (tmp >> 4); +} + +:TSTFSZ srcREG, A is op6=0x19 & d=0x1 & srcREG & A & skipInst { + # 0110 011a ffff ffff + # 0110 0110 0000 0000 -> TSTFSZ DAT_DATA_0000, 0 + # 0110 0111 0000 0000 -> TSTFSZ REG0x0, 1 + # 0110 0110 1101 1000 -> TSTFSZ STATUS, 0 + # 0110 0111 1101 1000 -> TSTFSZ REG0xD8, 1 + if (srcREG == 0) goto skipInst; +} + +:XORWF srcREG, D, A is op6=0x06 & srcREG & destREG & D & A { + # 0001 10da ffff ffff + # 0001 1000 0000 0000 -> XORWF DAT_DATA_0000, w, ACCESS + # 0001 1001 0000 0000 -> XORWF REG0x0, w, BANKED + # 0001 1000 1101 1000 -> XORWF STATUS, w, ACCESS + # 0001 1001 1101 1000 -> XORWF REG0xD8, w, BANKED + # 0001 1010 0000 0000 -> XORWF DAT_DATA_0000, f, ACCESS + # 0001 1011 0000 0000 -> XORWF REG0x0, f, BANKED + # 0001 1010 1101 1000 -> XORWF STATUS, f, ACCESS + # 0001 1011 1101 1000 -> XORWF REG0xD8, f, BANKED + tmp:1 = WREG ^ srcREG; + destREG = tmp; + setResultFlags(tmp); +} + + +# +# BIT-ORIENTED FILE REGISTER OPERATIONS +# + +:BCF srcREG, bit, A is op4=0x09 & srcREG & bit & A { + # 1001 bbba ffff ffff + # 1001 0010 0000 0000 -> BCF DAT_DATA_0000, #0x1, 0 + # 1001 0101 0000 0000 -> BCF REG0x0, #0x2, 1 + # 1001 0010 1101 1000 -> BCF STATUS, #0x1, 0 + # 1001 0101 1101 1000 -> BCF REG0xD8, #0x2, 1 + local bitmask = ~(1 << bit); + srcREG = srcREG & bitmask; +} + +:BCF status, bit, A is op4=0x09 & status & b3=0 & bit & A { + # 1001 bbba ffff ffff + # 1001 0000 1101 1000 -> BCF STATUS, #C, 0 + C = 0; + local bitmask = ~(1 << bit); + STATUS = STATUS & bitmask; +} + +:BCF status, bit, A is op4=0x09 & status & b3=1 & bit & A { + # 1001 bbba ffff ffff + # 1001 0010 1101 1000 -> BCF STATUS, #DC, 0 + DC = 0; + local bitmask = ~(1 << bit); + STATUS = STATUS & bitmask; +} + +:BCF status, bit, A is op4=0x09 & status & b3=2 & bit & A { + # 1001 bbba ffff ffff + # 1001 0100 1101 1000 -> BCF STATUS, #Z, 0 + Z = 0; + local bitmask = ~(1 << bit); + STATUS = STATUS & bitmask; +} + +:BCF status, bit, A is op4=0x09 & status & b3=3 & bit & A { + # 1001 bbba ffff ffff + # 1001 0110 1101 1000 -> BCF STATUS, #OV, 0 + OV = 0; + local bitmask = ~(1 << bit); + STATUS = STATUS & bitmask; +} + +:BCF status, bit, A is op4=0x09 & status & b3=4 & bit & A { + # 1001 bbba ffff ffff + # 1001 1000 1101 1000 -> BCF STATUS, #N, 0 + N = 0; + local bitmask = ~(1 << bit); + STATUS = STATUS & bitmask; +} + +:BSF srcREG, bit, A is op4=0x08 & srcREG & bit & A { + # 1000 bbba ffff ffff + # 1000 0010 0000 0000 -> BSF DAT_DATA_0000, #0x1, 0 + # 1000 0101 0000 0000 -> BSF REG0x0, #0x2, 1 + # 1000 0010 1101 1000 -> BSF STATUS, #0x1, 0 + # 1000 0101 1101 1000 -> BSF REG0xD8, #0x2, 1 + local bitmask = 1 << bit; + srcREG = srcREG | bitmask; +} + +:BSF status, bit, A is op4=0x08 & status & b3=0 & bit & A { + # 1000 bbba ffff ffff + # 1000 0000 1101 1000 -> BSF STATUS, #C, 0 + C = 1; + local bitmask = 1 << bit; + STATUS = STATUS | bitmask; +} + +:BSF status, bit, A is op4=0x08 & status & b3=1 & bit & A { + # 1000 bbba ffff ffff + # 1000 0010 1101 1000 -> BSF STATUS, #DC, 0 + DC = 1; + local bitmask = 1 << bit; + STATUS = STATUS | bitmask; +} + +:BSF status, bit, A is op4=0x08 & status & b3=2 & bit & A { + # 1000 bbba ffff ffff + # 1000 0100 1101 1000 -> BSF STATUS, #Z, 0 + Z = 1; + local bitmask = 1 << bit; + STATUS = STATUS | bitmask; +} + +:BSF status, bit, A is op4=0x08 & status & b3=3 & bit & A { + # 1000 bbba ffff ffff + # 1000 0110 1101 1000 -> BSF STATUS, #OV, 0 + OV = 1; + local bitmask = 1 << bit; + STATUS = STATUS | bitmask; +} + +:BSF status, bit, A is op4=0x08 & status & b3=4 & bit & A { + # 1000 bbba ffff ffff + # 1000 1000 1101 1000 -> BSF STATUS, #N, 0 + N = 1; + local bitmask = 1 << bit; + STATUS = STATUS | bitmask; +} + +:BTFSC srcREG, bit, A is op4=0x0b & srcREG & bit & A & skipInst { + # 1011 bbba ffff ffff + # 1011 0010 0000 0000 -> BTFSC DAT_DATA_0000, #0x1, 0 + # 1011 0101 0000 0000 -> BTFSC REG0x0, #0x2, 1 + # 1011 0010 1101 1000 -> BTFSC STATUS, #0x1, 0 + # 1011 0101 1101 1000 -> BTFSC REG0xD8, #0x2, 1 + local bitmask = 1 << bit; + local tmp = srcREG & bitmask; + if (tmp == 0) goto skipInst; +} + +:BTFSC status, bit, A is op4=0x0b & b3=0 & bit & status & A & skipInst { + # 1011 bbba ffff ffff + # 1011 0000 1101 1000 -> BTFSC STATUS, #C, 0 + if ((C & 1) == 0) goto skipInst; +} + +:BTFSC status, bit, A is op4=0x0b & b3=1 & bit & status & A & skipInst { + # 1011 bbba ffff ffff + # 1011 0000 1101 1000 -> BTFSC STATUS, #DC, 0 + if ((DC & 1) == 0) goto skipInst; +} + +:BTFSC status, bit, A is op4=0x0b & b3=2 & bit & status & A & skipInst { + # 1011 bbba ffff ffff + # 1011 0000 1101 1000 -> BTFSC STATUS, #Z, 0 + if ((Z & 1) == 0) goto skipInst; +} + +:BTFSC status, bit, A is op4=0x0b & b3=3 & bit & status & A & skipInst { + # 1011 bbba ffff ffff + # 1011 0110 1101 1000 -> BTFSC STATUS, #OV, 0 + if ((OV & 1) == 0) goto skipInst; +} + +:BTFSC status, bit, A is op4=0x0b & b3=4 & bit & status & A & skipInst { + # 1011 bbba ffff ffff + # 1011 1000 1101 1000 -> BTFSC STATUS, #N, 0 + if ((N & 1) == 0) goto skipInst; +} + +:BTFSS srcREG, bit, A is op4=0x0a & srcREG & bit & A & skipInst { + # 1010 bbba ffff ffff + # 1010 0010 0000 0000 -> BTFSS DAT_DATA_0000, #0x1, 0 + # 1010 0101 0000 0000 -> BTFSS REG0x0, #0x2, 1 + # 1010 0010 1101 1000 -> BTFSS STATUS, #0x1, 0 + # 1010 0101 1101 1000 -> BTFSS REG0xD8, #0x2, 1 + local bitmask = 1 << bit; + local tmp = srcREG & bitmask; + if (tmp != 0) goto skipInst; +} + +:BTFSS status, bit, A is op4=0x0a & b3=0 & bit & status & A & skipInst { + # 1010 bbba ffff ffff + # 1010 0000 1101 1000 -> BTFSS STATUS, #C, 0 + if ((C & 1) != 0) goto skipInst; +} + +:BTFSS status, bit, A is op4=0x0a & b3=1 & bit & status & A & skipInst { + # 1010 bbba ffff ffff + # 1010 0010 1101 1000 -> BTFSS STATUS, #DC, 0 + if ((DC & 1) != 0) goto skipInst; +} + +:BTFSS status, bit, A is op4=0x0a & b3=2 & bit & status & A & skipInst { + # 1010 bbba ffff ffff + # 1010 0100 1101 1000 -> BTFSS STATUS, #Z, 0 + if ((Z & 1) != 0) goto skipInst; +} + +:BTFSS status, bit, A is op4=0x0a & b3=3 & bit & status & A & skipInst { + # 1010 bbba ffff ffff + # 1010 0110 1101 1000 -> BTFSS STATUS, #OV, 0 + if ((OV & 1) != 0) goto skipInst; +} + +:BTFSS status, bit, A is op4=0x0a & b3=4 & bit & status & A & skipInst { + # 1010 bbba ffff ffff + # 1010 1000 1101 1000 -> BTFSS STATUS, #N, 0 + if ((N & 1) != 0) goto skipInst; +} + +:BTG srcREG, bit, A is op4=0x07 & srcREG & bit & A { + # 0111 bbba ffff ffff + # 0111 0010 0000 0000 -> BTG DAT_DATA_0000, #0x1, 0 + # 0111 0101 0000 0000 -> BTG REG0x0, #0x2, 1 + # 0111 0010 1101 1000 -> BTG STATUS, #0x1, 0 + # 0111 0101 1101 1000 -> BTG REG0xD8, #0x2, 1 + local bitmask = 1 << bit; + tmp:1 = srcREG; + srcREG = ~(tmp & bitmask) | (tmp & ~bitmask); +} + +# +# CONTROL OPERATIONS +# + +:BC relAddr8 is op8=0xe2 & relAddr8 { + # 1110 0010 nnnn nnnn + # 1110 0010 0001 0000 -> BC LAB_CODE_XXXX + if ((C & 1) != 0) goto relAddr8; +} + +:BN relAddr8 is op8=0xe6 & relAddr8 { + # 1110 0110 nnnn nnnn + # 1110 0110 0001 0000 -> BN LAB_CODE_XXXX + if ((N & 1) != 0) goto relAddr8; +} + +:BNC relAddr8 is op8=0xe3 & relAddr8 { + # 1110 0011 nnnn nnnn + # 1110 0011 0001 0000 -> BNC LAB_CODE_XXXX + if ((C & 1) == 0) goto relAddr8; +} + +:BNN relAddr8 is op8=0xe7 & relAddr8 { + # 1110 0111 nnnn nnnn + # 1110 0111 0001 0000 -> BNN LAB_CODE_XXXX + if ((N & 1) == 0) goto relAddr8; +} + +:BNOV relAddr8 is op8=0xe5 & relAddr8 { + # 1110 0101 nnnn nnnn + # 1110 0101 0001 0000 -> BNOV LAB_CODE_XXXX + if ((OV & 1) == 0) goto relAddr8; +} + +:BNZ relAddr8 is op8=0xe1 & relAddr8 { + # 1110 0001 nnnn nnnn + # 1110 0001 0001 0000 -> BNZ LAB_CODE_XXXX + if ((Z & 1) == 0) goto relAddr8; +} + +:BOV relAddr8 is op8=0xe4 & relAddr8 { + # 1110 0100 nnnn nnnn + # 1110 0100 0001 0000 -> BOV LAB_CODE_XXXX + if ((OV & 1) != 0) goto relAddr8; +} + +:BRA relAddr11 is op5=0x1a & relAddr11 { + # 1101 0nnn nnnn nnnn + # 1101 0001 0001 0000 -> BRA LAB_CODE_XXXX (inst_next+0x220) + goto relAddr11; +} + +:BZ relAddr8 is op8=0xe0 & relAddr8 { + # 1110 0000 nnnn nnnn + # 1110 0000 0001 0000 -> BZ LAB_CODE_XXXX + if ((Z & 1) != 0) goto relAddr8; +} + +:CALL absAddr21, s_8 is lop8=0xec & absAddr21 & s_8 { + # 1110 110s kkkk kkkk 1111 kkkk kkkk kkkk + # 1110 1100 0100 0101 1111 0001 0010 0011 -> CALL SUB_CODE_02468a, 0 + push(&:3 inst_next); + call absAddr21; +} + +:CALL absAddr21, s_8 is lop8=0xed & absAddr21 & s_8 { + # 1110 110s kkkk kkkk 1111 kkkk kkkk kkkk + # 1110 1101 0100 0101 1111 0001 0010 0011 -> CALL SUB_CODE_02468a, 1 + WS = WREG; + STATUSS = STATUS; + BSRS = BSR; + push(&:3 inst_next); + call absAddr21; +} + +:CLRWDT is op16=0x0004 { + # 0000 0000 0000 0100 + clearWatchDogTimer(); +} + +:DAW is op16=0x0007 { + # 0000 0000 0000 0111 + tmp:1 = decimalAdjust(WREG); + WREG = tmp; + setResultFlags(tmp); +} + +:GOTO absAddr21 is lop8=0xef & absAddr21 { + # 1110 1111 kkkk kkkk 1111 kkkk kkkk kkkk + # 1110 1111 0100 0101 1111 0001 0010 0011 -> GOTO LAB_CODE_02468a + goto absAddr21; +} + +:NOP is op16=0x0000 { } + +:NOP is op4=0x0f { } + +:POP is op16=0x0006 { + # 0000 0000 0000 0110 + tmp:4 = 0; + pop(tmp); +} + +:PUSH is op16=0x0005 { + # 0000 0000 0000 0101 + push(&:3 inst_next); +} + +:RCALL relAddr11 is op5=0x1b & relAddr11 { + # 1101 1nnn nnnn nnnn + # 1101 1001 0000 0000 -> CALL SUB_CODE_XXXX + push(&:3 inst_next); + call relAddr11; +} + +:RESET is op16=0x00ff { + # 0000 0000 1111 1111 + reset(); +} + +:RETFIE s_0 is op16=0x0010 & s_0 { # TODO: Set GIE/GIEH and/or PEIE/GIEL + # 0000 0000 0001 0000 + retAddr:4 = 0; + pop(retAddr); + return [retAddr]; +} + +:RETFIE s_0 is op16=0x0011 & s_0 { # TODO: Set GIE/GIEH and/or PEIE/GIEL + # 0000 0000 0001 0001 + WREG = WS; + STATUS = STATUSS; + BSR = BSRS; + retAddr:4 = 0; + pop(retAddr); + return [retAddr]; +} + +:RETURN s_0 is op16=0x0012 & s_0 { + # 0000 0000 0001 0010 + retAddr:4 = 0; + pop(retAddr); + return [retAddr]; +} + +:RETURN s_0 is op16=0x0013 & s_0 { + # 0000 0000 0001 0011 + WREG = WS; + STATUS = STATUSS; + BSR = BSRS; + retAddr:4 = 0; + pop(retAddr); + return [retAddr]; +} + +:SLEEP is op16=0x0003 { + # 0000 0000 0000 0011 + sleep(); +} + +# +# LITERAL OPERATIONS +# + +:ADDLW imm8 is op8=0x0f & imm8 { + # 0000 1111 kkkk kkkk + # 0000 1111 0001 0010 -> ADDLW #0x12 + setAddFlags(imm8, WREG); + WREG = WREG + imm8; + setResultFlags(WREG); +} + +:ANDLW imm8 is op8=0xb & imm8 { + # 0000 1011 kkkk kkkk + # 0000 1011 0001 0010 -> ANDLW #0x12 + WREG = WREG & imm8; + setResultFlags(WREG); +} + +:IORLW imm8 is op8=0x9 & imm8 { + # 0000 1001 kkkk kkkk + # 0000 1001 0001 0010 -> IORLW #0x12 + WREG = WREG | imm8; + setResultFlags(WREG); +} + +:LFSR FSRn, imm12 is lop10=0x3b8 & fsr<3 & FSRn & imm12 { + # 1110 1110 00ff kkkk 1111 0000 kkkk kkkk + # 1110 1110 0001 0001 1111 0000 0010 0011 -> LFSR FSR1, 0x123 + FSRn = imm12; +} + +:MOVLB imm8 is op8=0x01 & imm8 { # Manual is inconsistent imm4 vs. imm8 + # 0000 0001 kkkk kkkk + # 0000 0001 0001 0010 -> MOVLB #0x12 + BSR = imm8; +} + +:MOVLW imm8 is op8=0x0e & imm8 { + # 0000 1110 kkkk kkkk + # 0000 1110 0001 0010 -> MOVLW #0x12 + WREG = imm8; +} + +:MULLW imm8 is op8=0x0d & imm8 { + # 0000 1101 kkkk kkkk + # 0000 1101 0001 0010 -> MULLW #0x12 + tmp1:2 = zext(imm8); + tmp2:2 = zext(WREG); + PROD = tmp1 * tmp2; +} + +:RETLW imm8 is op8=0x0c & imm8 { + # 0000 1100 kkkk kkkk + # 0000 1100 0001 0010 -> RETLW #0x12 + WREG = imm8; + retAddr:4 = 0; + pop(retAddr); + return [retAddr]; +} + +:SUBLW imm8 is op8=0x08 & imm8 { + # 0000 1000 kkkk kkkk + # 0000 1000 0001 0010 -> SUBLW #0x12 + setSubtractFlags(imm8, WREG); + WREG = imm8 - WREG; + setResultFlags(WREG); +} + +:XORLW imm8 is op8=0x0a & imm8 { + # 0000 1010 kkkk kkkk + # 0000 1010 0001 0010 -> XORLW #0x12 + WREG = WREG ^ imm8; + setResultFlags(WREG); +} + +# +# DATA MEMORY <-> PROGRAM MEMORY OPERATIONS +# + +:TBLRD* is op16=0x0008 { + # 0000 0000 0000 1000 + ptr:3 = TBLPTR; + TABLAT = *[CODE] ptr; +} + +:TBLRD*+ is op16=0x0009 { + # 0000 0000 0000 1001 + ptr:3 = TBLPTR; + TABLAT = *[CODE] ptr; + ptr = ptr + 1; + TBLPTR = ptr; +} + +:TBLRD*- is op16=0x000a { + # 0000 0000 0000 1010 + ptr:3 = TBLPTR; + TABLAT = *[CODE] ptr; + ptr = ptr - 1; + TBLPTR = ptr; +} + +:TBLRD+* is op16=0x000b { + # 0000 0000 0000 1011 + ptr:3 = TBLPTR; + ptr = ptr + 1; + TBLPTR = ptr; + TABLAT = *[CODE] ptr; +} + +:TBLWT* is op16=0x000c { + # 0000 0000 0000 1100 + ptr:3 = TBLPTR; + *[CODE] ptr = TABLAT; +} + +:TBLWT*+ is op16=0x000d { + # 0000 0000 0000 1101 + ptr:3 = TBLPTR; + *[CODE] ptr = TABLAT; + TBLPTR = ptr + 1; +} + +:TBLWT*- is op16=0x000e { + # 0000 0000 0000 1110 + ptr:3 = TBLPTR; + *[CODE] ptr = TABLAT; + TBLPTR = ptr - 1; +} + +:TBLWT+* is op16=0x000f { + # 0000 0000 0000 1111 + ptr:3 = TBLPTR; + ptr = ptr + 1; + TBLPTR = ptr; + *[CODE] ptr = TABLAT; +} + +# +# EXTENDED INSTRUCTION SET +# + +:ADDFSR xFSRn, imm6 is op8=0xe8 & xfsr<3 & xFSRn & imm6 { + # 1110 1000 ffkk kkkk + # 1110 1000 1001 0010 -> ADDFSR FSR2, #0x12 + xFSRn = xFSRn + zext(imm6); +} + +:ADDULNK imm6 is op8=0xe8 & xfsr=3 & imm6 { + # 1110 1000 11kk kkkk + # 1110 1000 1101 0010 -> ADDULNK #0x12 + retAddr:4 = 0; + pop(retAddr); + FSR2 = FSR2 + zext(imm6); + return [retAddr]; +} + +:CALLW is op16=0x0014 { + # 0000 0000 0001 0100 + loc:3 = (zext(PCLATU) << 16) | (zext(PCLATH) << 8) | zext(WREG); + push(&:3 inst_next); + call [loc]; +} + +:MOVSF ZS, destREG32 is lop9=0x1d6 & ZS & qual4=0xf & destREG32 { + # 1110 1011 0zzz zzzz 1111 ffff ffff ffff + # 1110 1011 0001 0010 1111 0001 0010 0011 -> MOVSF 0x12[FSR2], DAT_DATA_0123 + destREG32 = ZS; +} + +:MOVSF ZS, destREG32 is lop9=0x1d6 & ZS & qual4=0xf & destREG32 & fd=0xff9 { + # 1110 1011 0zzz zzzz 1111 ffff ffff ffff + # 1110 1011 0001 0010 1111 1111 1111 1001 -> MOVSF 0x12[FSR2], PCL + addr:3 = (zext(PCLATU) << 16) + (zext(PCLATH) << 8) + zext(ZS); + goto [addr]; +} + +:MOVSS ZS, ZD is lop9=0x1d7 & ZS & ZD { + # 1110 1011 1sss ssss 1111 xxxx xddd dddd + # s: corresponds to zs + # d: corresponds to zd + # x: appear to be unused bits (don't care) + # 1110 1011 1001 0010 1111 1111 1100 0101 -> MOVSS 0x12[FSR2], 0x45[FSR2] + ZD = ZS; +} + +:PUSHL imm8 is op8=0xfa & imm8 { + # 1111 1010 kkkk kkkk + # 1111 1010 0001 0010 -> PUSHL #0x12 + local loc = FSR2; + *[DATA]:1 loc = imm8; + FSR2 = loc - 1; +} + +:SUBFSR xFSRn, imm6 is op8=0xe9 & xfsr<3 & xFSRn & imm6 { + # 1110 1001 ffkk kkkk + # 1110 1001 0101 0010 -> SUBFSR FSR1, 0x12 + xFSRn = xFSRn - zext(imm6); +} + +:SUBULNK imm6 is op8=0xe9 & xfsr=3 & imm6 { + # 1110 1001 11kk kkkk + # 1110 1001 1101 0010 -> SUBULNK #0x12 + retAddr:4 = 0; + pop(retAddr); + FSR2 = FSR2 - zext(imm6); + return [retAddr]; +} diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/4xx.sinc b/python/icicle/Ghidra/Processors/PowerPC/data/languages/4xx.sinc new file mode 100644 index 0000000..392e96c --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/4xx.sinc @@ -0,0 +1,7 @@ +#dcread r0,0,r0 0x7c 00 03 cc +:dcread S,RA_OR_ZERO,B is OP=31 & S & B & (XOP_1_10=486 | XOP_1_10=326) & BIT_0=0 & RA_OR_ZERO +{ + # ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + S = dataCacheRead(RA_OR_ZERO,B); +} + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/FPRC.sinc b/python/icicle/Ghidra/Processors/PowerPC/data/languages/FPRC.sinc new file mode 100644 index 0000000..e8b33db --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/FPRC.sinc @@ -0,0 +1,210 @@ + +period: "" is Rc=0 { setSummaryFPSCR(); } +period: "." is Rc=1 { setSummaryFPSCR(); cr1flags(); } + +# Floating Convert To Integer Doubleword Unsigned + +:fctidu^period fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=942 & period +{ + # src is rounded to integer + + fT = trunc(round(fB)); + + # if src is Nan, result is 0 and VXSNAN is set to 1 + + fT = fT * zext(nan(fB) == 0); + fp_vxsnan = fp_vxsnan | nan(fB); + + # if src > 2^64 - 1, result is 0xffff_ffff_ffff_ffff and VXCVI is set to 1 + + bigi:16 = 0xffffffffffffffff; + bigf:8 = int2float(bigi); + fT = fT - (0xffffffffffffffff + fT) * zext(fB f> bigf); + fp_vxcvi = fp_vxcvi | (fB f> bigf); + + # if rounded value < 0, result is 0 and VXCVI is set to 1 + + fp_vxcvi = fp_vxcvi | (fT s< 0); + fT = fT * zext(fT s> 0); + + build period; +} + +# Floating Convert To Integer Doubleword Unsigned with round toward Zero + +:fctiduz^period fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=943 & period +{ + # src is rounded to integer + + fT = trunc(fB); + + # if src is Nan, result is 0 and VXSNAN is set to 1 + + fT = fT * zext(nan(fB) == 0); + fp_vxsnan = fp_vxsnan | nan(fB); + + # if src > 2^64 - 1, result is 0xffff_ffff_ffff_ffff and VXCVI is set to 1 + + bigi:16 = 0xffffffffffffffff; + bigf:8 = int2float(bigi); + fT = fT - (0xffffffffffffffff + fT) * zext(fB f> bigf); + fp_vxcvi = fp_vxcvi | (fB f> bigf); + + # if rounded value < 0, result is 0 and VXCVI is set to 1 + + fp_vxcvi = fp_vxcvi | (fT s< 0); + fT = fT * zext(fT s> 0); + + build period; +} + +# Floating Convert To Integer Word Unsigned + +:fctiwu^period fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=142 & period +{ + # src is rounded to integer + + fT = trunc(round(fB)); + + # if src is NaN then result is 0 and VXSNAN is set to 1 + + fT = fT * zext(nan(fB) == 0); + fp_vxsnan = fp_vxsnan | nan(fB); + + # if src > 2^32 - 1, result is 0xffff_ffff and VXCVI is set to 1 + + bigi:16 = 0xffffffff; + bigf:8 = int2float(bigi); + fT = fT - (0xffffffff + fT) * zext(fB f> bigf); + fp_vxcvi = fp_vxcvi | (fB f> bigf); + + # if rounded value < 0, result is 0 and VXCVI is set to 1 + + fp_vxcvi = fp_vxcvi | (fT s< 0); + fT = fT * zext(fT s> 0); + + build period; +} + +# Floating Convert To Integer Word Unsigned with round toward Zero + +:fctiwuz^period fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=143 & period +{ + # src is rounded to integer + + fT = trunc(fB); + + # if src is NaN then result is 0 and VXNAN is set to 1 + + fT = fT * zext(nan(fB) == 0); + fp_vxsnan = fp_vxsnan | nan(fB); + + # if src > 2^32 - 1, result is 0xffff_ffff and VXCVI is set to 1 + + bigi:16 = 0xffffffff; + bigf:8 = int2float(bigi); + fT = fT - (0xffffffff + fT) * zext(fB f> bigf); + fp_vxcvi = fp_vxcvi | (fB f> bigf); + + # if rounded value < 0, result is 0 and VXCVI is set to 1 + + fp_vxcvi = fp_vxcvi | (fT s< 0); + fT = fT * zext(fT s> 0); + + build period; +} + +# Floating Convert From Integer Doubleword Unsigned X-form + +:fcfidu^period fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=974 & period +{ + # convert source to unsigned int by extension + + local tmpI:8 = zext(fB); + + # src is converted to floating point + + fT = int2float(tmpI); + + # FPSCR is class and sign of result + + setFPRF(fT); + + build period; +} + +# Floating Convert From Integer Doubleword Single X-form + +:fcfids^period fT,fB is $(NOTVLE) & OP=59 & fT & BITS_16_20=0 & fB & XOP_1_10=846 & period +{ + # src is converted to single-precision floating point + + local tmpF:4 = int2float(fB); + + # convert the result to double-precision + + fT = float2float(tmpF); + + # FPSCR is class and sign of result + + setFPRF(fT); + + build period; +} + +# fcfidus fT,fB +# Floating Convert From Integer Doubleword Unsigned Single + +:fcfidus^period fT,fB is $(NOTVLE) & OP=59 & fT & BITS_16_20=0 & fB & XOP_1_10=974 & period +{ + # convert source to unsigned int by extension + + local tmpI:8 = zext(fB); + + # src is converted to single-precision floating point + + local tmpF:4 = int2float(tmpI); + + # src is converted to double-precision + + fT = float2float(tmpF); + + # FPSCR is class and sign of result + + setFPRF(fT); + + build period; +} + +# Floating Test for software Divide + +:ftdiv CRFD,fA,fB is $(NOTVLE) & OP=63 & CRFD & BITS_21_22=0 & fA & fB & XOP_1_10=128 & BIT_0=0 +{ + zero:8 = int2float(0:1); + + # fe if fA or fB is Nan or infinity, or if fB is 0 + # and other conditions on the exponents + + fe_flag:1 = nan(fA) | nan(fB) | (fB f== zero); + + # fg if fA or fB are infinite, or fB is NaN or denomrmalized or zero + + fg_flag:1 = nan(fB) | (fB f== zero); + CRFD = (fg_flag << 2) | (fe_flag << 1); +} + +# Floating Test for software Square Root + +:ftsqrt CRFD,fB is $(NOTVLE) & OP=63 & CRFD & BITS_21_22=0 & BITS_16_20=0 & fB & XOP_1_10=160 & BIT_0=0 +{ + zero:8 = int2float(0:1); + + # fe if fB is zero, NAN, infinity, or negative + + fe_flag:1 = nan(fB) | (fB f< zero); + + # fg if fB is zero, infinity, or denormalized + + fg_flag:1 = nan(fB) | (fB f== zero); + CRFD = (fg_flag << 2) | (fe_flag << 1); +} diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/PowerPC.opinion b/python/icicle/Ghidra/Processors/PowerPC/data/languages/PowerPC.opinion new file mode 100644 index 0000000..dddc58e --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/PowerPC.opinion @@ -0,0 +1,21 @@ + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/SPEF_SCR.sinc b/python/icicle/Ghidra/Processors/PowerPC/data/languages/SPEF_SCR.sinc new file mode 100644 index 0000000..11bfd1e --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/SPEF_SCR.sinc @@ -0,0 +1,130 @@ +# Based on "PowerISA Version 2.06 Revision B" document dated July 23, 2010 +# Category: SPE.Embedded Float Vector Instructions + +# version 1.0 + +define register offset=0x600 size=1 [ + spef_sovh spef_ovh spef_fgh spef_fxh spef_finvh spef_fdbzh spef_funfh spef_fovfh + spef_reserved1 spef_reserved2 + spef_finxs spef_finvs spef_fdbzs spef_funfs spef_fovfs + spef_reserved3 + spef_sov spef_ov spef_fg spef_fx spef_finv spef_fdbz spef_funf spef_fovf + spef_reserved4 + spef_finxe spef_finve spef_fdbze spef_funfe spef_fovfe spef_frmc0 spef_frmc1 +]; + + +macro setSPEFSCR_L(result) { + spef_finv = nan(result); + spef_finvs = spef_finvs | spef_finv; +} + + +macro setSPEFSCR_H(result) { + spef_finvh = nan(result); + spef_finvs = spef_finvs | spef_finvh; +} + + +macro setSummarySPEFSCR() { + spef_sov = spef_sov | spef_ov; + + spef_sovh = spef_sovh | spef_ovh; + + spef_finxs = spef_finxs | spef_fx | spef_fxh; + spef_finvs = spef_finvs | spef_finv | spef_finvh; + spef_fdbzs = spef_fdbzs | spef_fdbz | spef_fdbzh; + spef_funfs = spef_funfs | spef_funf | spef_funfh; + spef_fovfs = spef_fovfs | spef_fovf | spef_fovfh; +} + + +macro setSPEFSCRAddFlags_L(op1, op2, result) { + setSPEFSCR_L(result); + spef_fx = spef_fx | nan(op1) | nan(op2); + spef_finv = spef_fx; + setSummarySPEFSCR(); +} + + +macro setSPEFSCRAddFlags_H(op1, op2, result) { + setSPEFSCR_H(result); + spef_fxh = spef_fxh | nan(op1) | nan(op2); + spef_finvh = spef_fxh; + setSummarySPEFSCR(); +} + + +macro setSPEFSCRDivFlags_L(op1, op2, result) { + setSPEFSCR_L(result); + spef_fdbz = spef_fdbz | (op2 f== 0); + spef_fx = spef_fx | nan(op1) | nan(op2); + spef_finv = spef_fx; + setSummarySPEFSCR(); +} + + +macro setSPEFSCRDivFlags_H(op1, op2, result) { + setSPEFSCR_H(result); + spef_fdbzh = spef_fdbzh | (op2 f== 0); + spef_fxh = spef_fxh | nan(op1) | nan(op2); + spef_finvh = spef_fxh; + setSummarySPEFSCR(); +} + + +macro setSPEFSCRMulFlags_L(op1, op2, result) { + setSPEFSCR_L(result); + spef_fx = spef_fx | nan(op1) | nan(op2); + spef_finv = spef_fx; + setSummarySPEFSCR(); +} + + +macro setSPEFSCRMulFlags_H(op1, op2, result) { + setSPEFSCR_H(result); + spef_fxh = spef_fxh | nan(op1) | nan(op2); + spef_finvh = spef_fxh; + setSummarySPEFSCR(); +} + + +macro setSPEFSCRSubFlags_L(op1, op2, result) { + setSPEFSCR_L(result); + spef_fx = spef_fx | nan(op1) | nan(op2); + spef_finv = spef_fx; + setSummarySPEFSCR(); +} + + +macro setSPEFSCRSubFlags_H(op1, op2, result) { + setSPEFSCR_H(result); + spef_fxh = spef_fxh | nan(op1) | nan(op2); + spef_finvh = spef_fxh; + setSummarySPEFSCR(); +} + + +macro packSPEFSCR(tmp) { + packbits(tmp, + spef_sovh, spef_ovh, spef_fgh, spef_fxh, spef_finvh, spef_fdbzh, spef_funfh, spef_fovfh, + spef_reserved1, spef_reserved2, + spef_finxs, spef_finvs, spef_fdbzs, spef_funfs, spef_fovfs, + spef_reserved3, + spef_sov, spef_ov, spef_fg, spef_fx, spef_finv, spef_fdbz, spef_funf, spef_fovf, + spef_reserved4, + spef_finxe, spef_finve, spef_fdbze, spef_funfe, spef_fovfe, spef_frmc0, spef_frmc1 ); +} + + +macro unpackSPEFSCR(tmp) { + unpackbits(tmp, + spef_sovh, spef_ovh, spef_fgh, spef_fxh, spef_finvh, spef_fdbzh, spef_funfh, spef_fovfh, + spef_reserved1, spef_reserved2, + spef_finxs, spef_finvs, spef_fdbzs, spef_funfs, spef_fovfs, + spef_reserved3, + spef_sov, spef_ov, spef_fg, spef_fx, spef_finv, spef_fdbz, spef_funf, spef_fovf, + spef_reserved4, + spef_finxe, spef_finve, spef_fdbze, spef_funfe, spef_fovfe, spef_frmc0, spef_frmc1 ); +} + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/SPE_APU.sinc b/python/icicle/Ghidra/Processors/PowerPC/data/languages/SPE_APU.sinc new file mode 100644 index 0000000..56536a0 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/SPE_APU.sinc @@ -0,0 +1,3125 @@ +# Based on "EREF: A Reference for Motorola Book E and e500 Core" document version 01/2004 Rev2 +# Instructions that are specific to the (PowerPC) e500 core are implemented as auxiliary processing units (APUs) +# Signal Processing Engine APU (SPE APU) + +@ifdef BIT_64 +@define MEMMASK "0xFFFFFFFFFFFFFFFF" +@else +@define MEMMASK "0xFFFFFFFF" +@endif + + +# There are three versions of e500 core, namely e500v1, the e500v2, and the e500mc. +# A 64-bit evolution of the e500mc core is called e5500 core. +# All PowerQUICC 85xx devices are based on e500v1 or e500v2 cores. + +# The SPE, and embedded SPFP functionality is implemented in +# the MPC8540, the MPC8560 and in their derivatives (that is, in +# all PowerQUICC III devices). However, these instructions will +# not be supported in devices subsequent to PowerQUICC III. + +# version 1.0 + +# SPEFSCR.OVH Integer Overflow High bit 33 +# SPEFSCR.OV Integer Overflow bit 49 +# SPEFSCR.SOVH Summary Integer Overflow High bit 32 +# SPEFSCR.SOV Summary Integer Overflow bit 48 + +# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh +# SPEFSCR.SOV = SPEFSCR.SOV | ovl + +# The SPE requires a GPR register file with thirty-two +# 64-bit registers. For 32-bit implementations, instructions +# that normally operate on a 32-bit register file +# access and change only the least significant 32-bits of +# the GPRs leaving the most significant 32-bits +# unchanged. For 64-bit implementations, operation of +# these instructions is unchanged, i.e. those instructions +# continue to operate on the 64-bit registers as they +# would if the SPE was not implemented. Most SPE +# instructions view the 64-bit register as being composed +# of a vector of two elements, each of which is 32 bits +# wide (some instructions read or write 16-bit elements). +# The most significant 32-bits are called the upper word, +# high word or even word. The least significant 32-bits +# are called the lower word, low word or odd word. +# Unless otherwise specified, SPE instructions write all +# 64-bits of the destination register. + +# Key to some symbols used in descriptions +# RT.l => low part of RT 0-31 bits +# RT.h => high part of RT 32-63 bits +# RT.t => total RT 0-63 bits +# temp.b31 => bit 31 of temp +# temp.B1 => byte 1 of temp +# temp.S0 => first 2 bytes +# ABS() +# EXTZ() => Result of extending x on the left with sign bits +# SATURATE() => +# ONESCOMP() => one's complement +# CR.bsub(..:..)=> bit range +# >u => unsigned greaterthan +# EQUIV => Equivalence logical operators = (a ^ (ONESCOMP(B))) +# *si Signed-integer multiplication +# *ui Unsigned-integer multiplication + +# *gsf +# Guarded signed fractional multiplication. +# Result of multiplying 2 signed fractional +# quantities having bit length 16 taking the +# least significant 31 bits of the sign +# extended product and concatenating a 0 +# to the least significant bit forming a +# guarded signed fractional result of 64 bits. +# Since guarded signed fractional multiplication +# produces a 64-bit result, fractional +# input quantities of -1 and -1 can produce +# +1 in the intermediate product. Two 16-bit +# fractional quantities, a and b are multiplied, +# as shown below: +# ea0:31 = EXTS(a) +# eb0:31 = EXTS(b) +# prod0:63 = ea X eb +# eprod0:63 = EXTS(prod32:63) +# result0:63 = eprod1:63 || 0b0 + +define pcodeop GuardedSignedFractionalMultiplication; + +# *sf +# Signed fractional multiplication. Result of +# multiplying 2 signed fractional quantities +# having bit length n taking the least significant +# 2n-1 bits of the sign extended product +# and concatenating a 0 to the least significant +# bit forming a signed fractional result +# of 2n bits. Two 16-bit signed fractional +# quantities, a and b are multiplied, as +# shown below: +# ea0:31 = EXTS(a) +# eb0:31 = EXTS(b) +# prod0:63 = ea X eb +# prod0:63 = EXTS(prod32:63) +# result0:31 = eprod33:63 || 0b0 + +define pcodeop SignedFractionalMultiplication; + +# ================================================================== + +# ======================================================================= +# Page D-10 + +# evabs RT,RA +# ISA-cmt: Vector Absolute Value +# evabs rD,rA 010 0000 1000 SPE_APU_Vector_Instructions +:evabs D,A is OP=4 & D & A & XOP_0_10=0x208 & BITS_11_15=0 { + # RT.l = ABS(RA.l); + # RT.h = ABS(RA.h); + + temp:8 = zext(A); + lo:8 = (( temp & (0x00000000FFFFFFFF) ) ); + lo = zext( ((lo:4 + (lo:4 >> 32)) ^ (lo:4 >> 32)) ); + hi:8 = (( temp & (0xFFFFFFFF00000000) ) >> 32); + hi = zext( ((hi:4 + (hi:4 >> 32)) ^ (hi:4 >> 32)) ); + D = (( zext(hi) << 32) | zext(lo) ); +} + +# evaddiw RT,RB,UI +# ISA-cmt: Vector Add Immediate Word +# evaddiw rD,BU_UIMM,rB 010 0000 0010 SPE_APU_Vector_Instructions +:evaddiw D,B,BU_UIMM is OP=4 & D & BU_UIMM & B & XOP_0_10=0x202 { + # RT.l = RB.l + EXTZ(UI); + # RT.h = RB.h + EXTZ(UI); + + tmp:8 = BU_UIMM; + lo:8 = (( B & (0x00000000FFFFFFFF) ) ) + (tmp & 0xFFFF); + hi:8 = (( B & (0xFFFFFFFF00000000) ) >> 32) + (tmp & 0xFFFF); + D = (( zext(hi) << 32) | zext(lo) ); +} + +# evaddsmiaaw RT,RA +# ISA-cmt: Vector Add Signed, Modulo, Integer to Accumulator Word +# evaddsmiaaw rD,rA 100 1100 1001 SPE_APU_Vector_Instructions +:evaddsmiaaw D,A is OP=4 & D & A & XOP_0_10=0x4C9 & BITS_11_15=0 { + # RT.l = ACC.l + RA.l; + # RT.h = ACC.h + RA.h; + # ACC.t = RT.t; + + lo:8 = (( ACC & (0x00000000FFFFFFFF) ) ) + (( A & (0x00000000FFFFFFFF) ) ); + hi:8 = (( ACC & (0xFFFFFFFF00000000) ) >> 32) + (( A & (0xFFFFFFFF00000000) ) >> 32); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# macro SATURATE(ov,carry, sat_ovn, sat_ov, val) { +# sat = (ov * carray)*sat_ovn + (ov * !carray)*sat_ov + (! ov) * val; +# } + +# evaddssiaaw RT,RA +# ISA-cmt: Vector Add Signed, Saturate, Integer to Accumulator Word +# evaddssiaaw rD,rA 100 1100 0001 SPE_APU_Vector_Instructions +define pcodeop VectorAddSignedSaturateIntgerToAccumulatorWord1; +define pcodeop VectorAddSignedSaturateIntgerToAccumulatorWord2; +:evaddssiaaw D,A is OP=4 & D & A & XOP_0_10=0x4C1 & BITS_11_15=0 { + # TODO definition complicated SATURATE() + # temp.t = EXTS(ACC.l) + EXTS(RA.l); + # ovh = temp.b31 ^ temp.b32; + # RT.l = SATURATE(ovh, temp.b31, 0x8000_0000, 0x7FFF_FFFF, temp.h); + # temp.t = EXTS(ACC.h) + EXTS(RA.h); + # ovl = temp.31 ^ temp.32; + # RT.h = SATURATE(ovl, temp.b31, 0x8000_0000, 0x7FFF_FFFF, temp.h); + # ACC.t = RT.t; + # SPEFSCR.ovh = ovh; + # SPEFSCR.ov = ov; + # SPEFSCR.sovh = SPEFSCR.sovh | ovh; + # SPEFSCR.sov = SPEFSCR.sov | ovh; + +# temp:8 = sext( extrBytes(ACC,8,4,0) ) + sext( extrBytes(A,8,4,0) ); +# ovh = getBits(temp,31,31,8) ^ getBits(temp,32,32,8); +# SATURATE(ovh, getBits(temp,31,31,8), 0x80000000,0x7FFFFFFF, temp); +# lo = sat; + + D = VectorAddSignedSaturateIntgerToAccumulatorWord1(ACC, A); + spr200 = VectorAddSignedSaturateIntgerToAccumulatorWord2(ACC, A); +} + +# evaddumiaaw RT,RA +# ISA-cmt: Vector Add Unsigned, Modulo, Integer to Accumulator Word +# evaddumiaaw rD,rA 100 1100 1000 SPE_APU_Vector_Instructions +:evaddumiaaw D,A is OP=4 & D & A & XOP_0_10=0x4C8 & BITS_11_15=0 { + # RT.l = ACC.l + RA.l; + # RT.h = ACC.h + RA.h; + # ACC.t = RT.t; + + lo:8 = (( ACC & (0x00000000FFFFFFFF) ) ) + (( A & (0x00000000FFFFFFFF) ) ); + hi:8 = (( ACC & (0xFFFFFFFF00000000) ) >> 32) + (( A & (0xFFFFFFFF00000000) ) >> 32); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evaddusiaaw RT,RA +# ISA-cmt: Vector Add Unsigned, Saturate, Integer to Accumulator Word +# evaddusiaaw rD,rA 100 1100 0000 +define pcodeop VectorAddUnsignedSaturateIntegerToAccumulatorWord1; +define pcodeop VectorAddUnsignedSaturateIntegerToAccumulatorWord2; +:evaddusiaaw D,A is OP=4 & D & A & XOP_0_10=0x4C0 & BITS_11_15=0 { + # TODO definition complicated SATURATE() + # temp.t = EXTZ(ACC.l) + EXTZ(RA.l); + # ovh = temp.b31; + # RT.l = SATURATE(ovh, temp.31, 0xFFFF_FFFF, 0xFFFF_FFFF, temp.h); + # ovl = temp.b31 + # RT.h = SATURATE(ovl, temp.31, 0xFFFF_FFFF, 0xFFFF_FFFF, temp.h); + # ACC.t = RT.t; + # SPEFSCR.ovh = ovh; + # SPEFSCR.ov = SPESCR.sovh | ovh; + # SPEFSCR.sovh = SPESCR.sov | ovl; + + D = VectorAddUnsignedSaturateIntegerToAccumulatorWord1(ACC, A); + spr200 = VectorAddUnsignedSaturateIntegerToAccumulatorWord2(ACC, A); +} + +# evaddw RT,RA,RB +# ISA-cmt: Vector Add Word +# evaddw rD,rA,rB 010 0000 0000 +:evaddw D,A,B is OP=4 & D & A & B & XOP_0_10=0x200 { + # RT.l = RA.l + RB.l; + # RT.h = RA.h + RB.h; + + lo:8 = (( A & (0x00000000FFFFFFFF) ) ) + (( B & (0x00000000FFFFFFFF) ) ); + hi:8 = (( A & (0xFFFFFFFF00000000) ) >> 32) + (( B & (0xFFFFFFFF00000000) ) >> 32); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evand RT,RA,RB +# ISA-cmt: Vector AND +# evand rD,rA,rB 010 0001 0001 +:evand D,A,B is OP=4 & D & A & B& XOP_0_10=0x211 { + # RT.l = RA.l & RB.l; + # RT.h = RA.h & RB.h; + + lo:8 = (( A & (0x00000000FFFFFFFF) ) ) & (( B & (0x00000000FFFFFFFF) ) ); + hi:8 = (( A & (0xFFFFFFFF00000000) ) >> 32) & (( B & (0xFFFFFFFF00000000) ) >> 32); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evandc RT,RA,RB +# ISA-cmt: Vector AND with Complement +# evandc rD,rA,rB 010 0001 0010 +:evandc D,A,B is OP=4 & D & A & B & XOP_0_10=0x212 { + # RT.l = RA.l & (ONESCOMP(RB.l)); + # RT.h = RA.h & (ONESCOMP(RB.h)); + + lo:8 = (( A & (0x00000000FFFFFFFF) ) ) & (~ (( B & (0x00000000FFFFFFFF) ) )); + hi:8 = (( A & (0xFFFFFFFF00000000) ) >> 32) & (~ (( B & (0xFFFFFFFF00000000) ) >> 32)); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evcmpeq BF,RA,RB +# ISA-cmt: Vector Compare Equal +# evcmpeq crfD,rA,rB 010 0011 0100 +:evcmpeq crfD,A,B is OP=4 & crfD & A & B & XOP_0_10=0x234 & BITS_21_22=0 { + # ah = RA.l + # al = RA.h + # bh = RB.l + # bl = RB.h + # if (ah == bh) { + # ch = 1; + # } else { + # ch = 0; + # } + # if (al == bl) { + # cl = 1; + # } else { + # cl = 0; + # } + # CR.bsub(4xBF+32:4xBF+35) = ch || cl || (ch | cl) || (ch & cl); + + lo:$(REGISTER_SIZE) = (A & 0x00000000FFFFFFFF); + hi:$(REGISTER_SIZE) = ((A & 0xFFFFFFFF00000000) >> 32); + b_lo:$(REGISTER_SIZE) = (B & 0x00000000FFFFFFFF); + b_hi:$(REGISTER_SIZE) = ((B & 0xFFFFFFFF00000000) >> 32); + + if (hi == b_hi) goto ; + ch:1 = 0; + + ch = 1; + if (lo == b_lo) goto ; + cl:1 = 0; + + ch = 1; + crfD = (ch | (cl < 1) | ((ch|cl) < 2) | ((ch&cl) < 3)); +} + +# evcmpgts BF,RA,RB +# ISA-cmt: Vector Compare Greater Than Signed +# evcmpgts crfD,rA,rB 010 0011 0001 +:evcmpgts crfD,A,B is OP=4 & crfD & A & B & XOP_0_10=0x231 & BITS_21_22=0 { + # ah = RA.l; + # al = RA.h; + # bh = RB.l; + # bl = RB.h; + # if (ah > bh) { + # ch = 1; + # } else { + # ch = 0; + # } + # if (al > bl) { + # cl = 1; + # } else { + # ch = 0; + # } + # CR.bsub(4xBF+32:4xBF+35) = ch || cl || (ch | cl) || (ch & cl); + + lo:$(REGISTER_SIZE) = (A & 0x00000000FFFFFFFF); + hi:$(REGISTER_SIZE) = ((A & 0xFFFFFFFF00000000) >> 32); + b_lo:$(REGISTER_SIZE) = (B & 0x00000000FFFFFFFF); + b_hi:$(REGISTER_SIZE) = ((B & 0xFFFFFFFF00000000) >> 32); + + if (hi s> b_hi) goto ; + ch:1 = 0; + + ch = 1; + + if (lo s> b_lo) goto ; + cl:1 = 0; + + cl = 1; + crfD = (ch | (cl < 1) | ((ch|cl) < 2) | ((ch&cl) < 3)); +} + +# evcmpgtu BF,RA,RB +# ISA-cmt: Vector Compare Greater Than Unsigned +# evcmpgtu crfD,rA,rB 010 0011 0000 +:evcmpgtu crfD,A,B is OP=4 & crfD & A & B & XOP_0_10=0x230 & BITS_21_22=0 { + # ah = RA.l; + # al = RA.h; + # bh = RB.l; + # bl = RB.h; + # if (ah >u bh) { + # ch = 1; + # } else { + # ch = 0; + # } + # if (al >u bl) { + # cl = 1; + # } else { + # cl = 0; + # } + # CR.bsub(4xBF+32:4xBF+35) = ch || cl || (ch | cl) || (ch & cl); + + lo:$(REGISTER_SIZE) = (A & 0x00000000FFFFFFFF); + hi:$(REGISTER_SIZE) = ((A & 0xFFFFFFFF00000000) >> 32); + b_lo:$(REGISTER_SIZE) = (B & 0x00000000FFFFFFFF); + b_hi:$(REGISTER_SIZE) = ((B & 0xFFFFFFFF00000000) >> 32); + + if (hi > b_hi) goto ; + ch:1 = 0; + + ch = 1; + + if (lo > b_lo) goto ; + cl:1 = 0; + + cl = 1; + + crfD = (ch | (cl < 1) | ((ch|cl) < 2) | ((ch&cl) < 3)); +} + +# evcmplts BF,RA,RB +# ISA-cmt: Vector Compare Less Than Signed +# evcmplts crfD,rA,rB 010 0011 0011 +:evcmplts crfD,A,B is OP=4 & crfD & A & B & XOP_0_10=0x233 & BITS_21_22=0 { + # ah = RA.l; + # al = RA.h; + # bh = RB.l; + # bl = RB.h; + # if (ah < bh) { + # ch = 1; + # } else { + # ch = 0; + # } + # if (al < bl) { + # cl = 1; + # } else { + # cl = 0; + # } + # CR.bsub(4xBF+32:4xBF+35) = ch || ch || (ch | cl) || (ch & cl); + + lo:$(REGISTER_SIZE) = (A & 0x00000000FFFFFFFF); + hi:$(REGISTER_SIZE) = ((A & 0xFFFFFFFF00000000) >> 32); + b_lo:$(REGISTER_SIZE) = (B & 0x00000000FFFFFFFF); + b_hi:$(REGISTER_SIZE) = ((B & 0xFFFFFFFF00000000) >> 32); + + if (hi s< b_hi) goto ; + ch:1 = 0; + + ch = 1; + + if (lo s< b_lo) goto ; + cl:1 = 0; + + cl = 1; + + crfD = (ch | (cl < 1) | ((ch|cl) < 2) | ((ch&cl) < 3)); +} + +# evcmpltu BF,RA,RB +# ISA-cmt: Vector Compare Less Than Unsigned +# evcmpltu crfD,rA,rB 010 0011 0010 +:evcmpltu crfD,A,B is OP=4 & crfD & A & B & XOP_0_10=0x232 & BITS_21_22=0 { + # ah = RA.l; + # al = RA.h; + # bh = RB.l; + # bl = RB.h; + # if (ah > 32); + b_lo:$(REGISTER_SIZE) = (B & 0x00000000FFFFFFFF); + b_hi:$(REGISTER_SIZE) = ((B & 0xFFFFFFFF00000000) >> 32); + + if (hi < b_hi) goto ; + ch:1 = 0; + + ch = 1; + + if (lo < b_lo) goto ; + cl:1 = 0; + + cl = 1; + + crfD = (ch | (cl < 1) | ((ch|cl) < 2) | ((ch&cl) < 3)); +} + +# evcntlsw RT,RA +# ISA-cmt: Vector Count Leading Signed Bits Word +# evcntlsw rD,rA 010 0000 1110 +define pcodeop VectorCountLeadingSignBitsWord; +:evcntlsw D,A is OP=4 & D & A & XOP_0_10=0x20E & BITS_11_15=0 { + # TODO definition complicated + # n = 0; + # s = RA.b(n); + # do while (n < 32) { + # if (RA.b(n) != s) { + # leave; + # } else { + # n = n + 1; + # } + # RT.l = n; + # n = 0; + # s = RA.b(n+32); + # do while (n < 32) { + # if (RA.b(n+32) != s) { + # leave; + # } + # n = n + 1; + # } + # RT.h = n; + # } + + D = VectorCountLeadingSignBitsWord(A); +} + +# evcntlzw RT,RA +# ISA-cmt: Vector Count Leading Zeros Word +# evcntlzw rD,rA 010 0000 1101 +define pcodeop VectorCountLeadingZerosWord; +:evcntlzw D,A is OP=4 & D & A & XOP_0_10=0x20D & BITS_11_15=0 { + # TODO definition + # n = 0; + # do while (n < 32) { + # if (RA.b(n) = 1) { + # leave; + # } else { + # n = n + 1; + # } + # } + # RT.l = n; + # n = 0; + # do while (n < 32) { + # if (RA.b(n+32) == 1) { + # leave; + # } else { + # n = n + 1; + # } + # } + # RT.h = n; + + D = VectorCountLeadingZerosWord(A); +} + +# evdivws RT,RA,RB +# ISA-cmt: Vector Divide Word Signed +# evdivws rD,rA,rB 100 1100 0110 +define pcodeop VectorDivideWordSigned1; +define pcodeop VectorDivideWordSigned2; +:evdivws D,A,B is OP=4 & D & A & B & XOP_0_10=0x4C6 { + # TODO definition complicated +# SPEFSCR.OVH = ovh; +# SPEFSCR.OV = ovl; +# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh; +# SPEFSCR.SOV = SPEFSCR.SOV | ovl; + + D = VectorDivideWordSigned1(A,B); + flags:8 = VectorDivideWordSigned2(A,B); + + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evdivwu RT,RA,RB +# ISA-cmt: Vector Divide Word Unsigned +# evdivwu rD,rA,rB 100 1100 0111 +define pcodeop VectorDivideWordUnsigned1; +define pcodeop VectorDivideWordUnsigned2; +:evdivwu D,A,B is OP=4 & D & A & B & XOP_0_10=0x4C7 { + # TODO definition complicated +# SPEFSCR.OV = ovl +# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh +# SPEFSCR.SOV = SPEFSCR.SOV | ovl + + D = VectorDivideWordUnsigned1(A,B); + flags:8 = VectorDivideWordUnsigned2(A,B); + + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + + +# eveqv RT,RA,RB +# ISA-cmt: Vector Equivalent +# eveqv rD,rA,rB 010 0001 1001 +:eveqv D,A,B is OP=4 & D & A & B & XOP_0_10=0x219 { + # RT.l = EQUIV(RA.l, RB.l); + # RT.h = EQUIV(RA.h, RB.h); + + lo:$(REGISTER_SIZE) = (A & 0x00000000FFFFFFFF); + hi:$(REGISTER_SIZE) = ((A & 0xFFFFFFFF00000000) >> 32); + b_lo:$(REGISTER_SIZE) = (B & 0x00000000FFFFFFFF); + b_hi:$(REGISTER_SIZE) = ((B & 0xFFFFFFFF00000000) >> 32); + + lo = lo ^ b_lo; # TODO check + hi = hi ^ b_hi; + + D = ((hi << 32) | lo); +} + +# evextsb RT,RA +# ISA-cmt: Vector Extend Sign Byte +# evextsb rD,rA 010 0000 1010 +:evextsb D,A is OP=4 & D & A & XOP_0_10=0x20A & BITS_11_15=0 { + # RT.l = EXTS(RA.B3); + # RT.h = EXTS(RA.B7); + + lo:$(REGISTER_SIZE) = (( A & (0x00000000FF000000) ) >> 24); + hi:$(REGISTER_SIZE) = (( A & (0xFF00000000000000) ) >> 56); + lo = sext(lo:1); + hi = sext(hi:1); + D = (( zext(hi) << 32) | zext(lo) ); +} + +# evextsh RT,RA +# ISA-cmt: Vector Extend Sign Halfword +# evextsh rD,rA, 010 0000 1011 +:evextsh D,A is OP=4 & D & A & XOP_0_10=0x20B & BITS_11_15=0 { + # RT.l = EXTS(RA.S1); + # RT.h = EXTS(RA.S3); + + lo:$(REGISTER_SIZE) = (( A & (0x00000000FFFF0000) ) >> 16); + hi:$(REGISTER_SIZE) = (( A & (0xFFFF000000000000) ) >> 48); + lo = sext(lo:2); + hi = sext(hi:2); + D = (( zext(hi) << 32) | zext(lo) ); +} + +# ======================================================================= +# Page D-11 + +# evldd RT,D(RA) +# ISA-cmt: Vector Load Double Word into Double Word +# evldd rD,d(rA) +define pcodeop VectorLoadDoubleWordIntoDoubleWord; +# TODO: defined in evx.sinc +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + EXTZ(UI*8); +# RT = MEM(EA,8); + +#:evldd D,A is OP=4 & D & A & XOP_0_10=769 & BITS_11_15=0 { + # TODO: defined in evx.sinc +# VectorLoadDoubleWordIntoDoubleWord(D,A); +#} + +# evlddx RT,RA,RB +# ISA-cmt: Vector Load Double Word into Double Word Indexed +# evlddx +# define pcodeop vectorLoadDoubleWordIntoDoubleWordIndexed1; +# TODO: defined in evx.sinc +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + RB; +# RT = MEM(EA, 8); + +# :evlddx S,A,B is OP=4 & S & A & B & XOP_0_10=768 { +# TODO: defined in evx.sinc +# vectorLoadDoubleWordIntoDoubleWordIndexed1(S,A,B); +#} + +# evldh RT,D(RA) +# ISA-cmt: Vector Load Double into Four Halfwords +# evldh rD,rA 011 0000 0101 + + +:evldh RT,EVUIMM_8_RAt is OP=4 & A & D & RT & EVUIMM_8 & EVUIMM_8_RAt & XOP_0_10=0x305 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + EXTZ(UI*8); +# RT.S0 = MEM(EA, 2); +# RT.S1 = MEM(EA+2, 2); +# RT.S2 = MEM(EA+4, 2); +# RT.S3 = MEM(EA+6, 2); + + EA:8 = A + zext(EVUIMM_8_RAt); + *:2 (RT) = *:2 ((EA) & $(MEMMASK)); + *:2 (RT+2) = *:2 ((EA+2) & $(MEMMASK)); + *:2 (RT+4) = *:2 ((EA+4) & $(MEMMASK)); + *:2 (RT+6) = *:2 ((EA+6) & $(MEMMASK)); +} + +# evldhx RT,RA,RB +# ISA-cmt: Vector Load Double into Four Halfwords Indexed +# evldhx rD,rA,rB 011 0000 0100 + +:evldhx D,A,B is OP=4 & A & D & B & XOP_0_10=0x304 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + RB; +# RT.S0 = MEM(EA, 2); +# RT.S1 = MEM(EA+2, 2); +# RT.S2 = MEM(EA+4, 2); +# RT.S3 = MEM(EA+6, 2); + + EA:8 = A + B; + *:2 (D) = *:2 ((EA) & $(MEMMASK)); + *:2 (D+2) = *:2 ((EA+2) & $(MEMMASK)); + *:2 (D+4) = *:2 ((EA+4) & $(MEMMASK)); + *:2 (D+6) = *:2 ((EA+6) & $(MEMMASK)); +} + +# evldw RT,D(RA) +# ISA-cmt: Vector Load Double into Two Words +# evldw rD,rA 011 0000 0011 +:evldw RT,EVUIMM_8_RAt is OP=4 & A & D & RT & EVUIMM_8 & EVUIMM_8_RAt & XOP_0_10=0x303 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + EXTZ(UI*8); +# RT.l = MEM(EA, 4); +# RT.h = MEM(EA+4, 4); + + EA:$(REGISTER_SIZE) = A + zext(EVUIMM_8_RAt); + *:4 (RT) = *:4 ((EA) & $(MEMMASK)); + *:4 (RT+4) = *:4 ((EA+4) & $(MEMMASK)); +} + +# evldwx RT,RA,RB +# ISA-cmt: Vector Load Double into Two Words Indexed +# evldwx rD,rA,rB 011 0000 0010 +:evldwx D,A,B is OP=4 & A & B & D & XOP_0_10=0x302 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + RB; +# RT.l = MEM(EA, 4); +# RT.h = MEM(EA+4, 4); + + EA:$(REGISTER_SIZE) = A + B; + *:4 (D) = *:4 ((EA) & $(MEMMASK)); + *:4 (D+4) = *:4 ((EA+4) & $(MEMMASK)); +} + +# evlhhesplat RT,D(RA) +# ISA-cmt: Vector Load Halfword into Halfwords Even and Splat +# evlhhesplat rD,rA 011 0000 1001 +:evlhhesplat RT,EVUIMM_2_RAt is OP=4 & A & RT & EVUIMM_2_RAt & D & XOP_0_10=0x309 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + EXTZ(UI*2); +# RT.S0 = MEM(EA,2); +# RT.S1 = 0x0000; +# RT.S2 = MEM(EA,2); +# RT.S3 = 0x0000; + + EA:$(REGISTER_SIZE) = A + zext(EVUIMM_2_RAt); + *:2 (RT) = *:2 ((EA) & $(MEMMASK)); + *:2 (RT+2) = 0x0000; + *:2 (RT+4) = *:2 ((EA) & $(MEMMASK)); + *:2 (RT+6) = 0x0000; +} + +# evlhhesplatx RT,RA,RB +# ISA-cmt: Vector Load Halfword into Halfwords Even and Splat Indexed +# evlhhesplatx rD,rA,rB 011 0000 1000 +:evlhhesplatx D,A,B is OP=4 & A & B & D & XOP_0_10=0x308 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + RB; +# RT.S0 = MEM(EA, 2); +# RT.S1 = 0x0000; +# RT.S2 = MEM(EA, 2); +# RT.S3 = 0x0000; + + EA:$(REGISTER_SIZE) = A + B; + *:2 (D) = *:2 ((EA) & $(MEMMASK)); + *:2 (D+2) = 0x0000; + *:2 (D+4) = *:2 ((EA) & $(MEMMASK)); + *:2 (D+6) = 0x0000; +} + +# evlhhossplat RT,D(RA) +# ISA-cmt: Vector Load Halfword into Halfword Odd Signed and Splat +# evlhhossplat rD,rA 011 0000 1111 +:evlhhossplat RT,EVUIMM_2_RAt is OP=4 & A & RT & EVUIMM_2_RAt & D & XOP_0_10=0x30F { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + EXTZ(UI*2); +# RT.l = EXTS(MEM(EA, 2)); +# RT.h = EXTS(MEM(EA, 2)); + + EA:$(REGISTER_SIZE) = A + zext(EVUIMM_2_RAt); + *:4 (RT) = sext( *:2 (((EA) & $(MEMMASK)))); + *:4 (RT+4) = sext( *:2 (((EA) & $(MEMMASK)))); +} + +# evlhhossplatx RT,RA,RB +# ISA-cmt: Vector Load Halfword into Halfword Odd Signed and Splat Indexed +# evlhhossplatx rD,rA,rB 011 0000 1110 +:evlhhossplatx D,A,B is OP=4 & A & B & D & XOP_0_10=0x30E { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + RB; +# RT.l = EXTS(MEM(EA, 2)); +# RT.h = EXTS(MEM(EA, 2)); + + EA:$(REGISTER_SIZE) = A + B; + *:4 (D) = sext( *:2 (((EA) & $(MEMMASK)))); + *:4 (D+4) = sext( *:2 (((EA) & $(MEMMASK)))); +} + +# evlhhousplat RT,D(RA) +# ISA-cmt: Vector Load Halfword into Halfword Odd Unsigned and Splat +# evlhhousplat rD,rA 011 0000 1101 +:evlhhousplat RT,EVUIMM_2_RAt is OP=4 & A & RT & EVUIMM_2_RAt & D & XOP_0_10=0x30D { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + EXTZ(UI*2); +# RT.l = EXTZ(MEM(EA, 2)); +# RT.h = EXTZ(MEM(EA, 2)); + + EA:$(REGISTER_SIZE) = A + zext(EVUIMM_2_RAt); + *:4 (RT) = zext( *:2 (((EA) & $(MEMMASK)))); + *:4 (RT+4) = zext( *:2 (((EA) & $(MEMMASK)))); +} + +# evlhhousplatx RT,RA,RB +# ISA-cmt: Vector Load Halfword into Halfword Odd Unsigned and Splat Indexed +# evlhhousplatx rD,rA,rB 011 0000 1100 +:evlhhousplatx D,A,B is OP=4 & A & B & D & XOP_0_10=0x30C { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + RB; +# RT.l = EXTZ(MEM(EA, 2)); +# RT.h = EXTZ(MEM(EA, 2)); + + EA:$(REGISTER_SIZE) = A + B; + *:4 (D) = zext( *:2 (((EA) & $(MEMMASK)))); + *:4 (D) = zext( *:2 (((EA) & $(MEMMASK)))); +} + +# evlwhe RT,D(RA) +# ISA-cmt: Vector Load Word into Two Halfwords Even +# evlwhe rD,rA 011 0001 0001 +# evlwhe confict with mullhwu. +# define pcodeop VectorLoadWordIntoTwoHalfWordsEven; +# :evlwhe D,A is OP=4 & A & EVUIMM_4 & D & XOP_0_10=0x311 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + EXTZ(UI*4); +# RT.S0 = MEM(EA, 2); +# RT.S1 = 0x0000; +# RT.S2 = MEM(EA+2, 2); +# RT.S3 = 0x0000; + +# VectorLoadWordIntoTwoHalfWordsEven(D,A); +# } + +# ================================================================= +# Page D-12 + +# evlwhex RT,RA,RB +# ISA-cmt: Vector Load Word into Two Halfwords Even Indexed +# evlwhex rD,rA 011 0001 0000 +# evlwhex confict with mullhwu +# define pcodeop VectorLoadWordIntoTwoHalfWordsEvenIndexed; +# :evlwhex D,A is OP=4 & B & A & D & XOP_0_10=0x310 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b+ RB; +# RT.S0 = MEM(EA, 2); +# RT.S1 = 0x0000; +# RT.S2 = MEM(EA + 2, 2); +# RT.S3 = 0x0000; + +# VectorLoadWordIntoTwoHalfWordsEvenIndexed(D,A); +# } + +# evlwhos RT,D(RA) +# ISA-cmt: Vector Load Word into Two Halfwords Odd Signed (with sign extension) +# evlwhos rD,rA 011 0001 0111 +:evlwhos RT,EVUIMM_4_RAt is OP=4 & A & EVUIMM_4_RAt & RT & D & XOP_0_10=0x317 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + EXTZ(UI*4); +# RT.l = EXTS(MEM(EA, 2)); +# RT.h = EXTS(MEM(EA+2, 2)); + + EA:$(REGISTER_SIZE) = A + zext(EVUIMM_4_RAt); + *:4 (RT) = sext( *:2 (((EA) & $(MEMMASK)))); + *:4 (RT+4) = sext( *:2 (((EA+2) & $(MEMMASK)))); +} + +# evlwhosx RT,RA,RB +# ISA-cmt: Vector Load Word into Two Halfwords Odd Signed Indexed (with sign extension) +# evlwhosx rD,rA,rB 011 0001 0110 +:evlwhosx D,A,B is OP=4 & A & B & D & XOP_0_10=0x316 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + RB; +# RT.l = EXTS(MEM(EA,2)); +# RT.h = EXTS(MEM(EA+2, 2)); + + EA:$(REGISTER_SIZE) = A + B; + *:4 (D) = sext( *:2 (((EA) & $(MEMMASK)))); + *:4 (D+4) = sext( *:2 (((EA+2) & $(MEMMASK)))); +} + +# evlwhou RT,D(RA) +# ISA-cmt: Vector Load Word into Two Halfwords Odd Unsigned (zero-extended) +# evlwhou rD,rA 011 0001 0101 +:evlwhou RT,EVUIMM_4_RAt is OP=4 & A & EVUIMM_4_RAt & RT & D & XOP_0_10=0x315 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + EXTZ(UI*4); +# RT.l = EXTZ(MEM(EA, 2)); +# RT.h = EXTZ(MEM(EA+2, 2)); + + EA:$(REGISTER_SIZE) = A + zext(EVUIMM_4_RAt); + *:4 (RT) = zext( *:2 (((EA) & $(MEMMASK)))); + *:4 (RT+4) = zext( *:2 (((EA+2) & $(MEMMASK)))); +} + +# evlwhoux RT,RA,RB +# ISA-cmt: Vector Load Word into Two Halfwords Odd Unsigned Indexed (zero-extended) +# evlwhoux rD,rA,rB 011 0001 0100 +:evlwhoux D,A,B is OP=4 & A & B & D & XOP_0_10=0x314 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + RB; +# RT.l = EXTZ(MEM(EA,2)); +# RT.h = EXTZ(MEM(EA+2,2)); + + EA:$(REGISTER_SIZE) = A + B; + *:4 (D) = zext( *:2 (((EA) & $(MEMMASK)))); + *:4 (D+4) = zext( *:2 (((EA+2) & $(MEMMASK)))); +} + +# evlwhsplat RT,D(RA) +# ISA-cmt: Vector Load Word into Two Halfwords and Splat +# evlwhsplat rD,rA 011 0001 1101 +:evlwhsplat RS,EVUIMM_4_RAt is OP=4 & A & B & D & XOP_0_10=0x31D & EVUIMM_4_RAt & RS { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + EXTZ(UI*4); +# RT.S0 = MEM(EA,2); +# RT.S1 = MEM(EA,2); +# RT.S2 = MEM(EA+2,2); +# RT.S3 = MEM(EA+2,2); + + EA:$(REGISTER_SIZE) = A + zext(EVUIMM_4_RAt); + *:2 (RS) = *:2 ((EA) & $(MEMMASK)); + *:2 (RS+2) = *:2 ((EA) & $(MEMMASK)); + *:2 (RS+4) = *:2 ((EA+2) & $(MEMMASK)); + *:2 (RS+6) = *:2 ((EA+2) & $(MEMMASK)); +} + +# evlwhsplatx RT,RA,RB +# ISA-cmt: Vector Load Word into Two Halfwords and Splat Indexed +# evlwhsplatx rD,rA,rB 011 0001 1100 +:evlwhsplatx D,A,B is OP=4 & A & B & D & XOP_0_10=0x31C { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + RB; +# RT.S0 = MEM(EA,2); +# RT.S1 = MEM(EA,2); +# RT.S2 = MEM(EA+2,2); +# RT.S3 = MEM(EA+2,2); + + EA:$(REGISTER_SIZE) = A + B; + *:2 (D) = *:2 ((EA) & $(MEMMASK)); + *:2 (D+2) = *:2 ((EA) & $(MEMMASK)); + *:2 (D+4) = *:2 ((EA+2) & $(MEMMASK)); + *:2 (D+6) = *:2 ((EA+2) & $(MEMMASK)); +} + +# evlwwsplat RT,D(RA) +# ISA-cmt: Vector Load Word into Word and Splat +# evlwwsplat rD,rA 011 0001 1001 +# define pcodeop VectorLoadWordIntoWordAndSplat; +# evlwwsplat conficts with maclhwu. +# :evlwwsplat RT,EVUIMM_4_RAt is OP=4 & A & D & EVUIMM_4_RAt & RT & XOP_0_10=0x319 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + EXTZ(UI*4); +# RT.l = MEM(EA,4); +# RT.h = MEM(EA,4); + +# VectorLoadWordIntoWordAndSplat(D,A); +# } + +# evlwwsplatx RT,RA,RB +# ISA-cmt: Vector Load Word into Word and Splat Indexed +# evlwwsplatx rD,rA,rB 011 0001 1000 +# define pcodeop VectorLoadWordIntoWordAndSplatIndexed; +# evlwwsplatx conficts with maclhwu +# :evlwwsplatx D,A,B is OP=4 & A & B & D & XOP_0_10=0x318 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + RB; +# RT.l = MEM(EA,4); +# RT.h = MEM(EA,4); + +# VectorLoadWordIntoWordAndSplatIndexed(D,A,B); +# } + +# evmergehi RT,RA,RB +# ISA-cmt: Vector Merge High +# evmergehi rD,rA,rB 010 0010 1100 +# defined evx.sinc XXX +# define pcodeop VectorMergeHigh; +# :evmergehi D,A,B is OP=4 & A & B & D & XOP_0_10=0x22C { +# RT.l = RA.l; +# RT.h = RB.h; + +# VectorMergeHigh(D,A,B); +# } + +# evmergehilo RT,RA,RB +# ISA-cmt: Vector Merge High/Low +# evmergehilo rD,rA,rB 010 0010 1110 +#define pcodeop VectorMergeHighLow; +#:evmergehilo D,A,B is OP=4 & A & B & D & XOP_0_10=0x22E { +# RT.l = RA.l; +# RT.h = RA.h; + +# lo = (A & 0x00000000FFFFFFFF); +# hi = ((A & 0xFFFFFFFF00000000) >> 32); +# b_lo = (B & 0x00000000FFFFFFFF); +# b_hi = ((B & 0xFFFFFFFF00000000) >> 32); +# +# lo = lo; +# hi = b_hi; +# +# D = ((hi << 32) | lo); +#} + +# evmergelo RT,RA,RB +# ISA-cmt: Vector Merge Low +# evmergelo rD,rA,rB 010 0010 1101 +# defined evx.sinc XXX +# define pcodeop VectorMergeLow; +# :evmergelo D,A,B is OP=4 & A & B & D & XOP_0_10=0x22D { +# RT.l = RA.h; +# RT.h = RA.l; + +# VectorMergeLow(D,A,B); +# } + +# evmergelohi RT,RA,RB +# ISA-cmt: Vector Merge Low/High +# evmergelohi rD,rA,rB 010 0010 1111 +#:evmergelohi D,A,B is OP=4 & D & A & B & XOP_0_10=0x22F { +# RT.l = RA.h; +# RT.h = RA.l; + +# lo = (A & 0x00000000FFFFFFFF); +# hi = ((A & 0xFFFFFFFF00000000) >> 32); +# b_lo = (B & 0x00000000FFFFFFFF); +# b_hi = ((B & 0xFFFFFFFF00000000) >> 32); +# +# lo = lo; +# hi = b_lo; +# +# D = ((hi << 32) | lo); +#} + + +# evmhegsmfaa RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Fractional and Accumulate +# evmhegsmfaa rD,rA,rB 101 0010 1011 +:evmhegsmfaa D,A,B is OP=4 & A & B & D & XOP_0_10=0x52B { +# u64 temp; +# temp = RA.S2 *gsf RB.S2; +# RT = ACC + temp; +# ACC = RT; + + D = ACC + GuardedSignedFractionalMultiplication( (( A & (0x0000FFFFFFFF0000) ) >> 16) , (( B & (0x0000FFFFFFFF0000) ) >> 16) ); + ACC = D; +} + +# evmhegsmfan RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Fractional and Accumulate Negative +# evmhegsmfan rD,rA,rB 101 1010 1011 +:evmhegsmfan D,A,B is OP=4 & A & B & D & XOP_0_10=0x5AB { +# u64 temp; +# temp = RA.S2 *gsf RB.S2; +# RT = ACC - temp; +# ACC = RT; + + D = ACC - GuardedSignedFractionalMultiplication( (( A & (0x0000FFFFFFFF0000) ) >> 16) , (( B & (0x0000FFFFFFFF0000) ) >> 16) ); + ACC = D; +} + +# evmhegsmiaa RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Integer and Accumulate +# evmhegsmiaa rD,rA,rB 101 0010 1001 +:evmhegsmiaa D,A,B is OP=4 & A & B & D & XOP_0_10=0x529 { +# u64 temp; +# temp.l = RA.l2 *si RB.l2; +# temp.h = EXTS(temp.l); +# RT = ACC + temp; +# ACC = RT; + + lo:8 = (( A & (0x0000FFFF00000000) ) >> 32) * (( B & (0x0000FFFF00000000) ) >> 32); + hi:8 = sext(lo:2); + lo = (( zext(hi) << 32) | zext(lo) ); + D = ACC + lo; + ACC = D; +} + + +# evmhegsmian RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Integer and Accumulate Negative +# evmhegsmian rD,rA,rB 101 1010 1001 +:evmhegsmian D,A,B is OP=4 & A & B & D & XOP_0_10=0x5A9 { +# u64 temp; +# temp.l = RA.S2 *si RB.S2; +# temp = EXTS(temp.l); +# RT = ACC - temp; +# ACC = RT; + + lo:8 = (( A & (0x0000FFFF00000000) ) >> 32) * (( B & (0x0000FFFF00000000) ) >> 32); + hi:8 = sext(lo:2); + lo = (( zext(hi) << 32) | zext(lo) ); + D = ACC - lo; + ACC = D; +} + +# evmhegumiaa RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Guarded, Unsigned, Modulo, Integer and Accumulate +# evmhegumiaa rD,rA,rB 101 0010 1000 +:evmhegumiaa D,A,B is OP=4 & A & B & D & XOP_0_10=0x528 { +# u64 temp; +# temp.l = RA.S2 *ui RB.S2; +# temp = EXTZ(temp.l); +# RT = ACC + temp; +# ACC = RT; + + temp:$(REGISTER_SIZE) = (( A & (0x0000FFFF00000000) ) >> 32) * (( B & (0x0000FFFF00000000) ) >> 32); + temp = zext(temp:4); + D = ACC + temp; + ACC = D; +} + +# evmhegumian RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Guarded, Unsigned, Modulo, Integer and Accumulate Negative +# evmhegumian rD,rA,rB 101 1010 1000 +:evmhegumian D,A,B is OP=4 & A & B & D & XOP_0_10=0x5A8 { +# u64 temp; +# temp.l = RA.S2 *ui RB.S2; +# temp = EXTZ(temp); +# RT = ACC - temp; +# ACC = RT; + + temp:$(REGISTER_SIZE) = (( A & (0x0000FFFF00000000) ) >> 32) * (( B & (0x0000FFFF00000000) ) >> 32); + temp = zext(temp:4); + D = ACC - temp; + ACC = D; +} + +# evmhesmf RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Modulo, Fractional +# evmhesmf rD,rA,rB 100 0000 1011 +:evmhesmf D,A,B is OP=4 & A & B & D & XOP_0_10=0x40B { +# RT = RA.S0 *sf RB.S0; +# RT.S2 = RA.S2 *sf RB.S2; + + D = SignedFractionalMultiplication( (( A & (0x0000000000000000) ) >> 16) , (( B & (0x0000000000000000) ) >> 16) ); + D = (D & 0xFFFF) | ( (SignedFractionalMultiplication((( A & (0x0000FFFFFFFF0000) ) >> 16),(( B & (0x0000FFFFFFFF0000) ) >> 16)) ) << 16); +} + +# evmhesmfa RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Modulo, Fractional to Accumulator +# evmhesmfa rD,rA,rB 100 0010 1011 +:evmhesmfa D,A,B is OP=4 & A & B & D & XOP_0_10=0x42B { +# RT.l = RA.S0 *sf RB.S0; +# RT.h = RA.S2 *sf RB.S2; +# ACC = RT; + + D = SignedFractionalMultiplication( (( A & (0x0000000000000000) ) >> 16) , (( B & (0x0000000000000000) ) >> 16) ); + D = (D & 0xFFFF) | ( (SignedFractionalMultiplication((( A & (0x0000FFFFFFFF0000) ) >> 16),(( B & (0x0000FFFFFFFF0000) ) >> 16)) ) << 16); + ACC = D; +} + +# evmhesmfaaw RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Modulo, Fractional and Accumulate into Words +# evmhesmfaaw rD,rA,rB 101 0000 1011 +:evmhesmfaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x50B { +# u64 temp; +# temp = RA.S0 *sf RB.S0; +# RT.l = ACC.l + temp.l; +# temp.l = RA.S2 *sf RB.S2; +# RT = ACC.h + temp.l; +# ACC = RT; + + lo:$(REGISTER_SIZE) = (( ACC & (0x0000000000000000) ) >> 32) + SignedFractionalMultiplication( (( A & (0x0000000000000000) ) >> 16) , (( B & (0x0000000000000000) ) >> 16) ); + hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) + SignedFractionalMultiplication( (( A & (0x0000FFFFFFFF0000) ) >> 16) , (( B & (0x0000FFFFFFFF0000) ) >> 16) ); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evmhesmfanw RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Modulo, Fractional and Accumulate Negative into Words +# evmhesmfanw rD,rA,rB 101 1000 1011 +:evmhesmfanw D,A,B is OP=4 & A & B & D & XOP_0_10=0x58B { +# u64 temp; +# temp.l = RA.S0 *sf RB.S0; +# RT.l = ACC.l - temp.l; +# temp.l = RA.S2 *sf RB.S2; +# RT.h = ACC.h - temp; +# ACC = RT; + + lo:$(REGISTER_SIZE) = (( ACC & (0x0000000000000000) ) >> 32) - SignedFractionalMultiplication( (( A & (0x0000000000000000) ) >> 16) , (( B & (0x0000000000000000) ) >> 16) ); + hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) - SignedFractionalMultiplication( (( A & (0x0000FFFFFFFF0000) ) >> 16) , (( B & (0x0000FFFFFFFF0000) ) >> 16) ); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evmhesmi RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Modulo, Integer +# evmhesmi rD,rA,rB 100 0000 1001 +:evmhesmi D,A,B is OP=4 & A & B & D & XOP_0_10=0x409 { +# RT.l = RA.S0 *si RB.S0; +# RT.h = RA.S2 *si RB.S2; + + lo:$(REGISTER_SIZE) = (( A & (0x000000000000FFFF) ) ) * (( B & (0x000000000000FFFF) ) ); + hi:$(REGISTER_SIZE) = (( A & (0x0000FFFF00000000) ) >> 32) * (( B & (0x0000FFFF00000000) ) >> 32); + D = (( zext(hi) << 32) | zext(lo) ); +} + +# evmhesmia RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Modulo, Integer to Accumulator +# evmhesmia rD,rA,rB 100 0010 1001 +:evmhesmia D,A,B is OP=4 & A & B & D & XOP_0_10=0x429 { +# RT.l = RA.S0 *si RB.S0; +# RT.h = RA.S2 *si RB.s2; +# ACC = RT; + + lo:$(REGISTER_SIZE) = (( A & (0x000000000000FFFF) ) ) * (( B & (0x000000000000FFFF) ) ); + hi:$(REGISTER_SIZE) = (( A & (0x0000FFFF00000000) ) >> 32) * (( B & (0x0000FFFF00000000) ) >> 32); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evmhesmiaaw rD,rA,rB 101 0000 1001 +# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Modulo, Integer and Accumulate into Words +:evmhesmiaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x509 { +# u64 temp; +# temp.l = RA.S0 *si RB.S0; +# RT.l = ACC.l + temp.l; +# temp.l = RA.S2 *si RB.S2; +# RT.h = ACC.h + temp.l; +# ACC = RT; + + lo:$(REGISTER_SIZE) = (( ACC & (0x00000000FFFFFFFF) ) ) + ((( A & (0x000000000000FFFF) ) ) * (( B & (0x000000000000FFFF) ) )); + hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) + ((( A & (0x0000FFFF00000000) ) >> 32) * (( B & (0x0000FFFF00000000) ) >> 32)); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evmhesmianw RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Modulo, Integer and Accumulate Negative into Words +# evmhesmianw rD,rA,rB 101 1000 1001 +:evmhesmianw D,A,B is OP=4 & A & B & D & XOP_0_10=0x589 { +# u64 temp; +# temp.l = RA.S0 *si RB.S0; +# RT.l = ACC.l - temp.l; +# temp.l = RA.S2 *si RB.S2; +# RT.S2 = ACC.S2 - temp.l; +# ACC = RT; + + lo:$(REGISTER_SIZE) = (( ACC & (0x00000000FFFFFFFF) ) ) - ((( A & (0x000000000000FFFF) ) ) * (( B & (0x000000000000FFFF) ) )); + hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) - ((( A & (0x0000FFFF00000000) ) >> 32) * (( B & (0x0000FFFF00000000) ) >> 32)); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evmhessf RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Saturate, Fractional +# evmhessf rD,rA,rB 100 0000 0011 +define pcodeop VectorMultiplyHalfWordsEvenSignedSaturateFractional1; +define pcodeop VectorMultiplyHalfWordsEvenSignedSaturateFractional2; +:evmhessf D,A,B is OP=4 & A & B & D & XOP_0_10=0x403 { + # TODO definition complicated +# SPEFSCR.OVH = movh; +# SPEFSCR.OV = movl; +# SPEFSCR.SOVH = SPEFSCR.SOVH | movh; +# SPEFSCR.SOV = SPEFSCR.SOV | movl; + + D = VectorMultiplyHalfWordsEvenSignedSaturateFractional1(A,B); + flags:8 = VectorMultiplyHalfWordsEvenSignedSaturateFractional2(A,B); + + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evmhessfa RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Saturate, Fractional to Accumulator +# evmhessfa rD,rA,rB 100 0010 0011 +define pcodeop VectorMultiplyHalfWordsEvenSignedSaturateFractionalAccumulate1; +define pcodeop VectorMultiplyHalfWordsEvenSignedSaturateFractionalAccumulate2; +:evmhessfa D,A,B is OP=4 & A & B & D & XOP_0_10=0x423 { +# SPEFSCR.OVH = movh; +# SPEFSCR.OV = movl; +# SPEFSCR.SOVH = SPEFSCR.SOVH | movh; +# SPEFSCR.SOV = SPEFSCR.SOV | movl; + # TODO definition complicated + D = VectorMultiplyHalfWordsEvenSignedSaturateFractionalAccumulate1(A,B); + ACC = D; + flags:8 = VectorMultiplyHalfWordsEvenSignedSaturateFractionalAccumulate2(A,B); + + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evmhessfaaw RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Saturate, Fractional and Accumulate into Words +# evmhessfaaw rD,rA,rB 101 0000 0011 +define pcodeop VectorMultiplyHalfWordsEvenSignedSaturateFractionalAndAccumulateIntoWords1; +define pcodeop VectorMultiplyHalfWordsEvenSignedSaturateFractionalAndAccumulateIntoWords2; +:evmhessfaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x503 { +# SPEFSCR.OVH = ovh | movh +# SPEFSCR.OV = ovl| movl +# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh | movh +# SPEFSCR.SOV = SPEFSCR.SOV | ovl| movl + # TODO definition complicated + D = VectorMultiplyHalfWordsEvenSignedSaturateFractionalAndAccumulateIntoWords1(A,B,ACC,spr200); + flags:8 = VectorMultiplyHalfWordsEvenSignedSaturateFractionalAndAccumulateIntoWords2(A,B,ACC,spr200); + ACC = D; + + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evmhessfanw RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Saturate, Fractional and Accumulate Negative into Words +# evmhessfanw rD,rA,rB 101 1000 0011 +define pcodeop VectorMultiplyHalfWordsEvenSignedSaturateFractionalAndAccumulateNegativeIntoWords1; +define pcodeop VectorMultiplyHalfWordsEvenSignedSaturateFractionalAndAccumulateNegativeIntoWords2; +:evmhessfanw D,A,B is OP=4 & A & B & D & XOP_0_10=0x583 { +# SPEFSCR.OVH = ovh | movh; +# SPEFSCR.OV = ovl| movl; +# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh | movh; +# SPEFSCR.SOV = SPEFSCR.SOV | ovl| movl; + # TODO definition complicated + D = VectorMultiplyHalfWordsEvenSignedSaturateFractionalAndAccumulateNegativeIntoWords1(A,B,ACC,spr200); + flags:8 = VectorMultiplyHalfWordsEvenSignedSaturateFractionalAndAccumulateNegativeIntoWords2(A,B,ACC,spr200); + ACC = D; + + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evmhessiaaw RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Saturate, Integer and Accumulate into Words +# evmhessiaaw rD,rA,rB 101 0000 0001 +define pcodeop VectorMultiplyHalfWordsEvenSignedSaturateIntegerAndAccumulateIntoWords1; +define pcodeop VectorMultiplyHalfWordsEvenSignedSaturateIntegerAndAccumulateIntoWords2; +:evmhessiaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x501 { +# SPEFSCR.OVH = ovh; +# SPEFSCR.OV = ovl; +# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh; +# SPEFSCR.SOV = SPEFSCR.SOV | ovl; + # TODO definition complicated + D = VectorMultiplyHalfWordsEvenSignedSaturateIntegerAndAccumulateIntoWords1(A,B,ACC,spr200); + flags:8 = VectorMultiplyHalfWordsEvenSignedSaturateIntegerAndAccumulateIntoWords2(A,B,ACC,spr200); + ACC = D; + + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evmhessianw RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Signed, Saturate, Integer and Accumulate Negative into Words +# evmhessianw rD,rA,rB 101 1000 0001 +define pcodeop VectorMultiplyHalfWordsEvenSignedSaturateIntegerAndAccumulateNegativeIntoWords1; +define pcodeop VectorMultiplyHalfWordsEvenSignedSaturateIntegerAndAccumulateNegativeIntoWords2; +:evmhessianw D,A,B is OP=4 & A & B & D & XOP_0_10=0x581 { +# SPEFSCR.OVH = ovh; +# SPEFSCR.OV = ovl; +# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh; +# SPEFSCR.SOV = SPEFSCR.SOV | ovl; +# TODO definition complicated + D = VectorMultiplyHalfWordsEvenSignedSaturateIntegerAndAccumulateNegativeIntoWords1(A,B,ACC,spr200); + flags:8 = VectorMultiplyHalfWordsEvenSignedSaturateIntegerAndAccumulateNegativeIntoWords2(A,B,ACC,spr200); + ACC = D; + + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# ================================================================= +# Page D-13 + +# evmheumi RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer +# evmheumi rD,rA,rB 100 0000 1000 +:evmheumi D,A,B is OP=4 & A & B & D & XOP_0_10=0x408 { +# RT.l = RA.S0 *ui RB.S0; +# RT.h = RA.S2 *ui RB.S2; + + lo:$(REGISTER_SIZE) = (( A & (0x0000000000000000) ) >> 16) * (( B & (0x0000000000000000) ) >> 16); + hi:$(REGISTER_SIZE) = (( A & (0x0000FFFFFFFF0000) ) >> 16) * (( B & (0x0000FFFFFFFF0000) ) >> 16); + D = (( zext(hi) << 32) | zext(lo) ); +} + +# evmheumia RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer to Accumulator +# evmheumia rD,rA,rB 100 0010 1000 +:evmheumia D,A,B is OP=4 & A & B & D & XOP_0_10=0x428 { +# RT.l = RA.S0 *ui RB.S0; +# RT.h = RA.S2 *ui RB.S2; +# ACC = RT; + + lo:$(REGISTER_SIZE) = (( A & (0x0000000000000000) ) >> 16) * (( B & (0x0000000000000000) ) >> 16); + hi:$(REGISTER_SIZE) = (( A & (0x0000FFFFFFFF0000) ) >> 16) * (( B & (0x0000FFFFFFFF0000) ) >> 16); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evmheumiaaw RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer and Accumulate into Words +# evmheumiaaw rD,rA,rB 101 0000 1000 +:evmheumiaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x508 { +# u64 temp; +# temp.l = RA.S0 *ui RB.S0; +# RT.l = ACC.l + temp.l; +# temp.l = RA.S2 *ui RB.S2; +# RT.h = ACC.h + temp.l; +# ACC = RT; + + lo:$(REGISTER_SIZE) = (( ACC & (0x0000000000000000) ) >> 32) + (( A & (0x0000000000000000) ) >> 16) * (( B & (0x0000000000000000) ) >> 16); + hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) + (( A & (0x0000FFFFFFFF0000) ) >> 16) * (( B & (0x0000FFFFFFFF0000) ) >> 16); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evmheumianw RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer and Accumulate Negative into Words +# evmheumianw rD,rA,rB 101 1000 1000 +:evmheumianw D,A,B is OP=4 & A & B & D & XOP_0_10=0x588 { +# u64 temp; +# temp.l = RA.S0 *ui RB.S0; +# RT.l = ACC.l - temp.l; +# temp.l = RA.S2 *ui RB.S2; +# RT.h = ACC.h - temp.l; +# ACC = RT; + + lo:$(REGISTER_SIZE) = (( ACC & (0x0000000000000000) ) >> 32) - (( A & (0x0000000000000000) ) >> 16) * (( B & (0x0000000000000000) ) >> 16); + hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) - (( A & (0x0000FFFFFFFF0000) ) >> 16) * (( B & (0x0000FFFFFFFF0000) ) >> 16); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evmheusiaaw RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Unsigned, Saturate, Integer and Accumulate into Words +# evmheusiaaw rD,rA,rB 101 0000 0000 +define pcodeop VectorMultiplyHalfWordsEvenUnsignedSaturateIntegerAndAccumulateIntoWords1; +define pcodeop VectorMultiplyHalfWordsEvenUnsignedSaturateIntegerAndAccumulateIntoWords2; +:evmheusiaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x500 { +# SPEFSCR.OVH = ovh; +# SPEFSCR.OV = ovl; +# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh; +# SPEFSCR.SOV = SPEFSCR.SOV | ovl; + # TODO definition complicated + D = VectorMultiplyHalfWordsEvenUnsignedSaturateIntegerAndAccumulateIntoWords1(A,B,ACC,spr200); + flags:8 = VectorMultiplyHalfWordsEvenUnsignedSaturateIntegerAndAccumulateIntoWords2(A,B,ACC,spr200); + ACC = D; + + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evmheusianw RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Even, Unsigned, Saturate, Integer and Accumulate Negative into Words +# evmheusianw rD,rA,rB 101 1000 0000 +define pcodeop evmheusianwOP1; +define pcodeop evmheusianwOP2; +:evmheusianw D,A,B is OP=4 & A & B & D & XOP_0_10=0x580 { +# SPEFSCR.OVH = ovh; +# SPEFSCR.OV = ovl; +# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh; +# SPEFSCR.SOV = SPEFSCR.SOV | ovl; + # TODO definition complicated + D = evmheusianwOP1(A,B,ACC,spr200); + flags:8 = evmheusianwOP2(A,B,ACC,spr200); + ACC = D; + + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evmhogsmfaa RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Fractional and Accumulate +# evmhogsmfaa rD,rA,rB 101 0010 1111 +:evmhogsmfaa D,A,B is OP=4 & A & B & D & XOP_0_10=0x52F { +# u64 temp; +# temp = RA.S3 *gsf RB.S3; +# RT = ACC + temp; +# ACC = RT; + + D = ACC + GuardedSignedFractionalMultiplication( (( A & (0xFFFFFFFFFFFF0000) ) >> 16) , (( B & (0xFFFFFFFFFFFF0000) ) >> 16) ); + ACC = D; +} + +# evmhogsmfan RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Fractional and Accumulate Negative +# evmhogsmfan rD,rA,rB 101 1010 1111 +:evmhogsmfan D,A,B is OP=4 & A & B & D & XOP_0_10=0x5AF { +# u64 temp; +# temp = RA.S3 *gsf RB.S3; +# RT = ACC - temp; +# ACC = RT; + + D = ACC - GuardedSignedFractionalMultiplication( (( A & (0xFFFFFFFFFFFF0000) ) >> 16) , (( B & (0xFFFFFFFFFFFF0000) ) >> 16) ); + ACC = D; +} + +# evmhogsmiaa RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Integer and Accumulate +# evmhogsmiaa rD,rA,rB 101 0010 1101 +:evmhogsmiaa D,A,B is OP=4 & A & B & D & XOP_0_10=0x52D { +# u64 temp; +# temp.l = RA.S3 *si RB.S3; +# temp = EXTS(temp.l); +# RT = ACC + temp; +# ACC = RT; + + lo:$(REGISTER_SIZE) = (( A & (0xFFFF000000000000) ) >> 48); + lo = sext(lo:2); + D = ACC + lo; + ACC = D; +} + +# evmhogsmian RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Integer and Accumulate Negative +# evmhogsmian rD,rA,rB 101 1010 1101 +:evmhogsmian D,A,B is OP=4 & A & B & D & XOP_0_10=0x5AD { +# u64 temp; +# temp.l = RA.S3 *si RB.S3; +# temp = EXTS(temp); +# RT = ACC - temp; +# ACC = RT; + + lo:$(REGISTER_SIZE) = (( A & (0xFFFF000000000000) ) >> 48); + lo = sext(lo:2); + D = ACC - lo; + ACC = D; +} + +# evmhogumiaa RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Guarded, Unsigned, Modulo, Integer and Accumulate +# evmhogumiaa rD,rA,rB 101 0010 1100 +:evmhogumiaa D,A,B is OP=4 & A & B & D & XOP_0_10=0x52C { +# u64 temp; +# tempo.l = RA.S3 *ui RB.S3; +# temp = EXTZ(temp.l); +# RT = ACC + temp; +# ACC = RT; + + temp:8 = (( A & (0xFFFFFFFFFFFF0000) ) >> 16) * (( B & (0xFFFFFFFFFFFF0000) ) >> 16); + temp = zext( (( temp & (0x0000000000000000) ) >> 32) ); + D = ACC + temp; + ACC = D; +} + +# evmhogumian RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Guarded, Unsigned, Modulo, Integer and Accumulate Negative +# evmhogumian rD,rA,rB 101 1010 1100 +:evmhogumian D,A,B is OP=4 & A & B & D & XOP_0_10=0x5AC { +# u64 temp; +# temp.l = RA.S3 *ui RB.S3; +# temp = EXTZ(temp.l); +# RT = ACC - temp; +# ACC = RT; + + temp:8 = (( A & (0xFFFFFFFFFFFF0000) ) >> 16) * (( B & (0xFFFFFFFFFFFF0000) ) >> 16); + temp = zext( (( temp & (0x0000000000000000) ) >> 32) ); + D = ACC - temp; + ACC = D; +} + +# evmhosmf RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional +# evmhosmf rD,rA,rB 100 0000 1111 +:evmhosmf D,A,B is OP=4 & A & B & D & XOP_0_10=0x40F { +# RT.l = RA.S1 *sf RB.S1; +# RT.h = RA.S3 *sf RB.S3; + + lo:8 = SignedFractionalMultiplication( (( A & (0x00000000FFFF0000) ) >> 16) , (( B & (0x00000000FFFF0000) ) >> 16) ); + hi:8 = SignedFractionalMultiplication( (( A & (0xFFFFFFFFFFFF0000) ) >> 16) , (( B & (0xFFFFFFFFFFFF0000) ) >> 16) ); + D = (( zext(hi) << 32) | zext(lo) ); +} + +# evmhosmfa RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional to Accumulator +# evmhosmfa rD,rA,rB 100 0010 1111 +:evmhosmfa D,A,B is OP=4 & A & B & D & XOP_0_10=0x42F { +# RT.l = RA.S1 *sf RB.S1; +# RT.h = RA.S3 *sf RB.S3; +# ACC = RT; + + lo:8 = SignedFractionalMultiplication( (( A & (0x00000000FFFF0000) ) >> 16) , (( B & (0x00000000FFFF0000) ) >> 16) ); + hi:8 = SignedFractionalMultiplication( (( A & (0xFFFFFFFFFFFF0000) ) >> 16) , (( B & (0xFFFFFFFFFFFF0000) ) >> 16) ); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evmhosmfaaw RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional and Accumulate into Words +# evmhosmfaaw rD,rA,rB 101 0000 1111 +:evmhosmfaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x50F { +# u64 temp; +# temp.l = RA.S1 *sf RB.S1; +# RT.l = ACC.l + temp.l; +# temp.l = RA.S3 *sf RB.S3; +# RT.h = ACC.h + temp.l; +# ACC = RT; + + lo:$(REGISTER_SIZE) = (( ACC & (0x0000000000000000) ) >> 32) + SignedFractionalMultiplication( (( A & (0x00000000FFFF0000) ) >> 16) , (( B & (0x00000000FFFF0000) ) >> 16) ); + hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) + SignedFractionalMultiplication( (( A & (0xFFFFFFFFFFFF0000) ) >> 16) , (( B & (0xFFFFFFFFFFFF0000) ) >> 16) ); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evmhosmfanw RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional and Accumulate Negative into Words +# evmhosmfanw rD,rA,rB 101 1000 1111 +:evmhosmfanw D,A,B is OP=4 & A & B & D & XOP_0_10=0x58F { +# u64 temp; +# temp.l = RA.S1 *sf RB.S1; +# RT.l = ACC.l - temp.l; +# temp.l = RA.S3 *sf RB.S3; +# RT.h = ACC.h - temp.l; +# ACC = RT; + + lo:$(REGISTER_SIZE) = (( ACC & (0x0000000000000000) ) >> 32) - SignedFractionalMultiplication( (( A & (0x00000000FFFF0000) ) >> 16) , (( B & (0x00000000FFFF0000) ) >> 16) ); + hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) - SignedFractionalMultiplication( (( A & (0xFFFFFFFFFFFF0000) ) >> 16) , (( B & (0xFFFFFFFFFFFF0000) ) >> 16) ); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evmhosmi RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Modulo, Integer +# evmhosmi rD,rA,rB 100 0000 1101 +:evmhosmi D,A,B is OP=4 & A & B & D & XOP_0_10=0x40D { +# RT.l = RA.S1 *si RB.S1; +# RT.h = RA.S3 *si RB.S3; + + lo:$(REGISTER_SIZE) = (( A & (0x00000000FFFF0000) ) >> 16) * (( B & (0x00000000FFFF0000) ) >> 16); + hi:$(REGISTER_SIZE) = (( A & (0xFFFF000000000000) ) >> 48) * (( B & (0xFFFF000000000000) ) >> 48); + D = (( zext(hi) << 32) | zext(lo) ); +} + +# evmhosmia RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Modulo, Integer to Accumulator +# evmhosmia rD,rA,rB 100 0010 1101 +:evmhosmia D,A,B is OP=4 & A & B & D & XOP_0_10=0x42D { +# RT.l = RA.S1 *si RB.S1; +# RT.h = RA.S3 *si RB.S3; +# ACC = RT; + + lo:$(REGISTER_SIZE) = (( A & (0x00000000FFFF0000) ) >> 16) * (( B & (0x00000000FFFF0000) ) >> 16); + hi:$(REGISTER_SIZE) = (( A & (0xFFFF000000000000) ) >> 48) * (( B & (0xFFFF000000000000) ) >> 48); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evmhosmiaaw RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Modulo, Integer and Accumulate into Words +# evmhosmiaaw rD,rA,rB 101 0000 1101 +:evmhosmiaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x50D { +# u64 temp; +# temp.l = RA.S1 *si RB.S1; +# RT.l = ACC.l + temp.l; +# temp.l = RA.S3 *si RB.S3; +# RT.h = ACC.h + temp.l; +# ACC = RT; + + lo:$(REGISTER_SIZE) = (( ACC & (0x00000000FFFFFFFF) ) ) + ((( A & (0x00000000FFFF0000) ) >> 16) * (( B & (0x00000000FFFF0000) ) >> 16)); + hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) + ((( A & (0xFFFF000000000000) ) >> 48) * (( B & (0xFFFF000000000000) ) >> 48)); + D = (( zext(hi) << 32) | zext(lo) ); +} + +# evmhosmianw RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Modulo, Integer and Accumulate Negative into Words +# evmhosmianw rD,rA,rB 101 1000 1101 +:evmhosmianw D,A,B is OP=4 & A & B & D & XOP_0_10=0x58D { +# u64 temp; +# temp.l = RA.S1 *si RB.S1; +# RT.l = ACC.l - temp.l; +# temp.l = RA.S3 *si RB.SI; +# RT.h = ACC.h - temp.l; +# ACC = RT; + + lo:$(REGISTER_SIZE) = (( ACC & (0x00000000FFFFFFFF) ) ) - ((( A & (0x00000000FFFF0000) ) >> 16) * (( B & (0x00000000FFFF0000) ) >> 16)); + hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) - ((( A & (0xFFFF000000000000) ) >> 48) * (( B & (0xFFFF000000000000) ) >> 48)); + D = (( zext(hi) << 32) | zext(lo) ); +} + +# evmhossf RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional +# evmhossf rD,rA,rB 100 0000 0111 +define pcodeop VectorMultiplyHalfWordsOddSignedSaturateFractionalToAccumulator1; +define pcodeop VectorMultiplyHalfWordsOddSignedSaturateFractionalToAccumulator2; +:evmhossf D,A,B is OP=4 & A & B & D & XOP_0_10=0x407 { +# SPEFSCR.OVH = movh; +# SPEFSCR.OV = movl; +# SPEFSCR.SOVH = SPEFSCR.SOVH | movh; +# SPEFSCR.SOV = SPEFSCR.SOV | movl; + # TODO definition complicated + D = VectorMultiplyHalfWordsOddSignedSaturateFractionalToAccumulator1(A,B); + flags:8 = VectorMultiplyHalfWordsOddSignedSaturateFractionalToAccumulator2(A,B); + + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evmhossfa rD,rA,rB 100 0010 0111 +# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional to Accumulator +define pcodeop VectorMultiplyHalfWordsOddSignedSaturateFractionalToAccumulator2a; +define pcodeop VectorMultiplyHalfWordsOddSignedSaturateFractionalToAccumulator2b; +:evmhossfa D,A,B is OP=4 & A & B & D & XOP_0_10=0x427 { +# SPEFSCR.OVH = movh; +# SPEFSCR.OV = movl; +# SPEFSCR.SOVH = SPEFSCR.SOVH | movh; +# SPEFSCR.SOV = SPEFSCR.SOV | movl; + # TODO definition complicated + D = VectorMultiplyHalfWordsOddSignedSaturateFractionalToAccumulator2a(A,B); + flags:8 = VectorMultiplyHalfWordsOddSignedSaturateFractionalToAccumulator2b(A,B); + + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evmhossfaaw RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional and Accumulate into Words +# evmhossfaaw rD,rA,rB 101 0000 0111 +define pcodeop VectorMultiplyHalfWordsOddSignedSaturateFractionalAndAccumulateIntoWords1; +define pcodeop VectorMultiplyHalfWordsOddSignedSaturateFractionalAndAccumulateIntoWords2; +:evmhossfaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x507 { +# SPEFSCR.OVH = ovh | movh; +# SPEFSCR.OV = ovl| movl; +# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh | movh; +# SPEFSCR.SOV = SPEFSCR.SOV | ovl| movl; + # TODO definition complicated + D = VectorMultiplyHalfWordsOddSignedSaturateFractionalAndAccumulateIntoWords1(A,B,ACC,spr200); + flags:8 = VectorMultiplyHalfWordsOddSignedSaturateFractionalAndAccumulateIntoWords2(A,B,ACC,spr200); + ACC = D; + + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evmhossfanw RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional and Accumulate Negative into Words +# evmhossfanw rD,rA,rB 101 1000 0111 +define pcodeop VectorMultiplyHalfWordsOddSignedSaturateFractionalAndAccumulateNegativeIntoWords1; +define pcodeop VectorMultiplyHalfWordsOddSignedSaturateFractionalAndAccumulateNegativeIntoWords2; +:evmhossfanw D,A,B is OP=4 & A & B & D & XOP_0_10=0x587 { +# SPEFSCR.OVH = ovh | movh; +# SPEFSCR.OV = ovl| movl; +# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh | movh; +# SPEFSCR.SOV = SPEFSCR.SOV | ovl| movl; + # TODO definition complicated + D = VectorMultiplyHalfWordsOddSignedSaturateFractionalAndAccumulateNegativeIntoWords1(A,B,ACC,spr200); + flags:8 = VectorMultiplyHalfWordsOddSignedSaturateFractionalAndAccumulateNegativeIntoWords2(A,B,ACC,spr200); + ACC = D; + + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evmhossiaaw RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Saturate, Integer and Accumulate into Words +# evmhossiaaw rD,rA,rB 101 0000 0101 +define pcodeop VectorMultiplyHalfWordsOddSignedSaturateIntegerAndAccumulateIntoWords1; +define pcodeop VectorMultiplyHalfWordsOddSignedSaturateIntegerAndAccumulateIntoWords2; +:evmhossiaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x505 { +# SPEFSCR.OVH = ovh; +# SPEFSCR.OV = ovl; +# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh; +# SPEFSCR.SOV = SPEFSCR.SOV | ovl; + # TODO definition complicated + D = VectorMultiplyHalfWordsOddSignedSaturateIntegerAndAccumulateIntoWords1(A,B,ACC,spr200); + flags:8 = VectorMultiplyHalfWordsOddSignedSaturateIntegerAndAccumulateIntoWords2(A,B,ACC,spr200); + ACC = D; + + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evmhossianw RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Signed, Saturate, Integer and Accumulate Negative into Words +# evmhossianw rD,rA,rB 101 1000 0101 +define pcodeop VectorMultiplyHalfWordsOddSignedSaturateIntegerAndAccumulateNegativeIntoWords1; +define pcodeop VectorMultiplyHalfWordsOddSignedSaturateIntegerAndAccumulateNegativeIntoWords2; +:evmhossianw D,A,B is OP=4 & A & B & D & XOP_0_10=0x585 { +# SPEFSCR.OVH = ovh; +# SPEFSCR.OV = ovl; +# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh; +# SPEFSCR.SOV = SPEFSCR.SOV | ovl; + # TODO definition complicated + D = VectorMultiplyHalfWordsOddSignedSaturateIntegerAndAccumulateNegativeIntoWords1(A,B,ACC,spr200); + ACC = D; + flags:8 = VectorMultiplyHalfWordsOddSignedSaturateIntegerAndAccumulateNegativeIntoWords2(A,B,ACC,spr200); + + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evmhoumi RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer +# evmhoumi rD,rA,rB 100 0000 1100 +:evmhoumi D,A,B is OP=4 & A & B & D & XOP_0_10=0x40C { +# RT.l = RA.S1 *ui RB.S1; +# RT.h = RA.S3 *ui RB.S3; + + lo:$(REGISTER_SIZE) = (( A & (0x00000000FFFF0000) ) >> 16) * (( B & (0x00000000FFFF0000) ) >> 16); + hi:$(REGISTER_SIZE) = (( A & (0xFFFFFFFFFFFF0000) ) >> 16) * (( B & (0xFFFFFFFFFFFF0000) ) >> 16); + D = (( zext(hi) << 32) | zext(lo) ); +} + +# evmhoumia RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer to Accumulator +# evmhoumia rD,rA,rB 100 0010 1100 +:evmhoumia D,A,B is OP=4 & A & B & D & XOP_0_10=0x42C { +# RT.l = RA.S1 *ui RB.S1; +# RT.h = RA.S3 *ui RB.S3; +# ACC = RT; + + lo:$(REGISTER_SIZE) = (( A & (0x00000000FFFF0000) ) >> 16) * (( B & (0x00000000FFFF0000) ) >> 16); + hi:$(REGISTER_SIZE) = (( A & (0xFFFFFFFFFFFF0000) ) >> 16) * (( B & (0xFFFFFFFFFFFF0000) ) >> 16); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evmhoumiaaw RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer and Accumulate into Words +# evmhoumiaaw rD,rA,rB 101 0000 1100 +:evmhoumiaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x50C { +# u64 temp; +# temp = RA.S1 *ui RB.S1; +# RT.l = ACC.l + temp.l; +# temp.l = RA.S3 *ui RB.S3; +# RT.h = ACC.h + temp.l; +# ACC = RT; + + lo:$(REGISTER_SIZE) = (( ACC & (0x0000000000000000) ) >> 32) + ((( A & (0x00000000FFFF0000) ) >> 16) * (( B & (0x00000000FFFF0000) ) >> 16)); + hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) + ((( A & (0xFFFFFFFFFFFF0000) ) >> 16) * (( B & (0xFFFFFFFFFFFF0000) ) >> 16)); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evmhoumianw RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer and Accumulate Negative into Words +# evmhoumianw rD,rA,rB 101 1000 1100 +:evmhoumianw D,A,B is OP=4 & A & B & D & XOP_0_10=0x58C { +# u64 temp; +# temp = RA.S1 *ui RB.S1; +# RT.l = ACC.l - temp.l; +# temp.l = RA.S3 *ui RB.S3; +# RT.h = ACC.h - temp.l; +# ACC = RT; + + lo:$(REGISTER_SIZE) = (( ACC & (0x0000000000000000) ) >> 32) - ((( A & (0x00000000FFFF0000) ) >> 16) * (( B & (0x00000000FFFF0000) ) >> 16)); + hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) - ((( A & (0xFFFFFFFFFFFF0000) ) >> 16) * (( B & (0xFFFFFFFFFFFF0000) ) >> 16)); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evmhousiaaw RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Unsigned, Saturate, Integer and Accumulate into Words +# evmhousiaaw rD,rA,rB 101 0000 0100 +define pcodeop VectorMultiplyHalfWordsOddUnsignedSaturateIntegerAndAccumulateIntoWords1; +define pcodeop VectorMultiplyHalfWordsOddUnsignedSaturateIntegerAndAccumulateIntoWords2; +:evmhousiaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x504 { +# SPEFSCR.OVH = ovh; +# SPEFSCR.OV = ovl; +# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh; +# SPEFSCR.SOV = SPEFSCR.SOV | ovl; + # TODO definition complicated + D = VectorMultiplyHalfWordsOddUnsignedSaturateIntegerAndAccumulateIntoWords1(A,B,ACC,spr200); + ACC = D; + flags:8 = VectorMultiplyHalfWordsOddUnsignedSaturateIntegerAndAccumulateIntoWords2(A,B,ACC,spr200); + + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evmhousianw RT,RA,RB +# ISA-cmt: Vector Multiply Halfwords, Odd, Unsigned, Saturate, Integer and Accumulate Negative into Words +# evmhousianw rD,rA,rB 101 1000 0100 +define pcodeop VectorMultiplyHalfWordsOddUnsignedSaturateIntegerAndAccumulateNegativeIntoWords1; +define pcodeop VectorMultiplyHalfWordsOddUnsignedSaturateIntegerAndAccumulateNegativeIntoWords2; +:evmhousianw D,A,B is OP=4 & A & B & D & XOP_0_10=0x584 { +# SPEFSCR.OVH = ovh; +# SPEFSCR.OV = ovl; +# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh; +# SPEFSCR.SOV = SPEFSCR.SOV | ovl; + # TODO definition complicated + D = VectorMultiplyHalfWordsOddUnsignedSaturateIntegerAndAccumulateNegativeIntoWords1(A,B,ACC,spr200); + ACC = D; + flags:8 = VectorMultiplyHalfWordsOddUnsignedSaturateIntegerAndAccumulateNegativeIntoWords2(A,B,ACC,spr200); + + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# ================================================================= +# Page D-14 + +# evmra RT,RA +# ISA-cmt: Initialize Accumulator +# evmra rD,rA 100 1100 0100 +# defined evx.sinc +# define pcodeop InitializeAccumulator; +# :evmra D,A is OP=4 & A & D & XOP_0_10=0x4C4 { +# ACC = RA; +# RT = RA; + +# ACC = A; +# D = A; + +# InitializeAccumulator(D,A); +# } + +# evmwhsmf RT,RA,RB +# ISA-cmt: Vector Multiply Word High Signed, Modulo, Fractional +# evmwhsmf rD,rA,rB 100 0100 1111 +:evmwhsmf D,A,B is OP=4 & A & B & D & XOP_0_10=0x44F { +# u64 temp; +# temp = RA.l *sf RB.l; +# RT.l = temp.l; +# temp = RA.h *sf RB.h; +# RT.h = temp.l; + + lo:8 = SignedFractionalMultiplication( (( A & (0x0000000000000000) ) >> 32) , (( B & (0x0000000000000000) ) >> 32) ); + hi:8 = SignedFractionalMultiplication( (( A & (0xFFFFFFFF00000000) ) >> 32) , (( B & (0xFFFFFFFF00000000) ) >> 32) ); + D = (( zext(hi) << 32) | zext(lo) ); +} + +# evmwhsmfa RT,RA,RB +# ISA-cmt: Vector Multiply Word High Signed, Modulo, Fractional to Accumulator +# evmwhsmfa rD,rA,rB 100 0110 1111 +:evmwhsmfa D,A,B is OP=4 & A & B & D & XOP_0_10=0x46F { +# u64 temp; +# temp = RA.l *sf RB.l; +# RT.l = temp.l; +# temp = RA.h *sf RB.h; +# RT.h = temp.l; +# ACC = RT; + + lo:8 = SignedFractionalMultiplication( (( A & (0x0000000000000000) ) >> 32) , (( B & (0x0000000000000000) ) >> 32) ); + hi:8 = SignedFractionalMultiplication( (( A & (0xFFFFFFFF00000000) ) >> 32) , (( B & (0xFFFFFFFF00000000) ) >> 32) ); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evmwhsmi RT,RA,RB +# ISA-cmt: Vector Multiply Word High Signed, Modulo, Integer +# evmwhsmi rD,rA,rB 100 0100 1101 +:evmwhsmi D,A,B is OP=4 & A & B & D & XOP_0_10=0x44D { +# u64 temp; +# temp = RA.l *si RB.l; +# RT.l = temp.l; +# temp = RA.h *si RB.h; +# RT.h = temp.l; + + lo:$(REGISTER_SIZE) = ((( A & (0x00000000FFFFFFFF) ) ) * (( B & (0x00000000FFFFFFFF) ) )) & 0xFFFFFFFF; + hi:$(REGISTER_SIZE) = ((( A & (0xFFFFFFFF00000000) ) >> 32) * (( B & (0xFFFFFFFF00000000) ) >> 32)) & 0xFFFFFFFF; + D = (( zext(hi) << 32) | zext(lo) ); +} + +# evmwhsmia RT,RA,RB +# ISA-cmt: Vector Multiply Word High Signed, Modulo, Integer to Accumulator +# evmwhsmia rD,rA,rB 100 0110 1101 +:evmwhsmia D,A,B is OP=4 & A & B & D & XOP_0_10=0x46D { +# u64 temp; +# temp = RA.l *si RB.l; +# RT.l = temp.l; +# temp = RA.h *si RB.h; +# RT.h = temp.l; +# ACC = RT; + + lo:$(REGISTER_SIZE) = ((( A & (0x00000000FFFFFFFF) ) ) * (( B & (0x00000000FFFFFFFF) ) )) & 0xFFFFFFFF; + hi:$(REGISTER_SIZE) = ((( A & (0xFFFFFFFF00000000) ) >> 32) * (( B & (0xFFFFFFFF00000000) ) >> 32)) & 0xFFFFFFFF; + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evmwhssf RT,RA,RB +# ISA-cmt: Vector Multiply Word High Signed, Saturate, Fractional +# evmwhssf rD,rA,rB 100 0100 0111 +define pcodeop VectorMultiplyWordHighSignedSaturateFractional1; +define pcodeop VectorMultiplyWordHighSignedSaturateFractional2; +:evmwhssf D,A,B is OP=4 & A & B & D & XOP_0_10=0x447 { +# SPEFSCR.OVH = movh; +# SPEFSCR.OV = movl; +# SPEFSCR.SOVH = SPEFSCR.SOVH | movh; +# SPEFSCR.SOV = SPEFSCR.SOV | movl; + # TODO definition complicated + D = VectorMultiplyWordHighSignedSaturateFractional1(A,B); + flags:8 = VectorMultiplyWordHighSignedSaturateFractional2(A,B); + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evmwhssfa RT,RA,RB +# ISA-cmt: Vector Multiply Word High Signed, Saturate, Fractional to Accumulator +# evmwhssfa rD,rA,rB 100 0110 0111 +define pcodeop VectorMultiplyWordHighSignedSaturateFractionalToAccumulator1; +define pcodeop VectorMultiplyWordHighSignedSaturateFractionalToAccumulator2; +:evmwhssfa D,A,B is OP=4 & A & B & D & XOP_0_10=0x467 { +# SPEFSCR.OVH = movh; +# SPEFSCR.OV = movl; +# SPEFSCR.SOVH = SPEFSCR.SOVH | movh; +# SPEFSCR.SOV = SPEFSCR.SOV | movl; + # TODO definition complicated + D = VectorMultiplyWordHighSignedSaturateFractionalToAccumulator1(A,B); + ACC = D; + flags:8 = VectorMultiplyWordHighSignedSaturateFractionalToAccumulator2(A,B); + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evmwhumi RT,RA,RB +# ISA-cmt: Vector Multiply Word High Unsigned, Modulo, Integer +# evmwhumi rD,rA,rB 100 0100 1100 +:evmwhumi D,A,B is OP=4 & A & B & D & XOP_0_10=0x44C { +# u64 temp; +# temp = RA.l *ui RB.l; +# RT.l = temp.l; +# temp = RA.h *ui RB.h; +# RT.h = temp.l; + + lo:$(REGISTER_SIZE) = (( A & (0x0000000000000000) ) >> 32) * (( B & (0x0000000000000000) ) >> 32); + lo = lo:4; + hi:$(REGISTER_SIZE) = (( A & (0xFFFFFFFF00000000) ) >> 32) * (( B & (0xFFFFFFFF00000000) ) >> 32); + hi = hi:4; + D = (( zext(hi) << 32) | zext(lo) ); +} + +# evmwhumia RT,RA,RB +# ISA-cmt: Vector Multiply Word High Unsigned, Modulo, Integer to Accumulator +# evmwhumia rD,rA,rB 100 0110 1100 +:evmwhumia D,A,B is OP=4 & A & B & D & XOP_0_10=0x46C { +# u64 temp; +# temp = RA.l *ui RB.l; +# RT.l = temp.l; +# temp = RA.h *ui RB.h; +# RT.h = temp.l; +# ACC = RT; + + lo:$(REGISTER_SIZE) = (( A & (0x0000000000000000) ) >> 32) * (( B & (0x0000000000000000) ) >> 32); + lo = lo:4; + hi:$(REGISTER_SIZE) = (( A & (0xFFFFFFFF00000000) ) >> 32) * (( B & (0xFFFFFFFF00000000) ) >> 32); + hi = hi:4; + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evmwlsmi rD,rA,rB +# ISA-cmt: Vector Multiply Word Low Signed, Modulo, Integer and Accumulate into Words +# define VectorMultiplyWordLowUnsigned,ModuloInteger; +# YYY No definition in manual + +# evmwhusiaaw rD,rA,rB 101 0100 0100 +# TODO Not in PowerISA Version 2.06 manual? +define pcodeop evmwhusiaawOP; +:evmwhusiaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x544 { evmwhusiaawOP(D,A,B); } + +# evmwhusianw rD,rA,rB 101 1100 0100 +# TODO Not in PowerISA Version 2.06 manual? +define pcodeop evmwhusianwOP; +:evmwhusianw D,A,B is OP=4 & A & B & D & XOP_0_10=0x5C4 { + evmwhusianwOP(D,A,B,ACC); +} + +# evmwlsmiaaw RT,RA,RB +# ISA-cmt: Vector Multiply Word Low Signed, Modulo, Integer and Accumulate into Words +# evmwlsmiaaw ?? +# u64 temp; +# temp = RA.l *si RB.l; +# RT.l = ACC.l + temp.h; +# temp = RA.h *si RB.h; +# RT.h = ACC.h + temp.h; +# ACC = RT; + +# evmwlsmianw RT,RA,RB +# ISA-cmt: Vector Multiply Word Low Signed, Modulo, Integer and Accumulate Negative in Words +# evmwlsmianw ?? +# u64 temp; +# temp = RA.l *si RB.l; +# RT.l = ACC.l - temp.h; +# temp = RA.h *si RB.h; +# RT.h = ACC.h - temp.h; +# ACC = RT; + +# evmwlssiaaw RT,RA,RB +# ISA-cmt: Vector Multiply Word Low Signed, aturate, Integer and Accumulate into Words +# evmwlssiaaw rD,rA,rB 101 0100 0001 +define pcodeop VectorMultiplyWordLowSignedSaturateIntegerAndAccumulateInWords1; +define pcodeop VectorMultiplyWordLowSignedSaturateIntegerAndAccumulateInWords2; +:evmwlssiaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x541 { +# SPEFSCR.OVH = ovh; +# SPEFSCR.OV = ovl; +# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh; +# SPEFSCR.SOV = SPEFSCR.SOV | ovl; + # TODO definition complicated + D = VectorMultiplyWordLowSignedSaturateIntegerAndAccumulateInWords1(A,B,ACC,spr200); + ACC = D; + flags:8 = VectorMultiplyWordLowSignedSaturateIntegerAndAccumulateInWords2(A,B,ACC,spr200); + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evmwlumi RT,RA,RB +# ISA-cmt: Vector Multiply Word Low Unsigned, Modulo, Integer +# evmwlumi rD,rA,rB 100 0100 1000 +:evmwlumi D,A,B is OP=4 & A & B & D & XOP_0_10=0x448 { +# u64 temp; +# temp = RA.l *ui RB.l; +# RT.l = temp.h; +# temp = RA.h *ui RB.h; +# RT.h = temp.h; + + lo:8 = (( A & (0x0000000000000000) ) >> 32) * (( B & (0x0000000000000000) ) >> 32); + lo = (( lo & (0xFFFFFFFF00000000) ) >> 32); + hi:8 = (( A & (0xFFFFFFFF00000000) ) >> 32) * (( B & (0xFFFFFFFF00000000) ) >> 32); + lo = (( hi & (0xFFFFFFFF00000000) ) >> 32); + D = (( zext(hi) << 32) | zext(lo) ); +} + +# evmwlumia RT,RA,RB +# ISA-cmt: Vector Multiply Word Low Unsigned, Modulo, Integer to Accumulator +# evmwlumia rD,rA,rB 100 0110 1000 +:evmwlumia D,A,B is OP=4 & A & B & D & XOP_0_10=0x468 { +# u64 temp; +# temp = RA.l *ui RB.l; +# RT.l = temp.h; +# temp = RA.h *ui RB.h; +# RT.h = temp.h; +# ACC = RT; + + lo:8 = (( A & (0x0000000000000000) ) >> 32) * (( B & (0x0000000000000000) ) >> 32); + lo = (( lo & (0xFFFFFFFF00000000) ) >> 32); + hi:8 = (( A & (0xFFFFFFFF00000000) ) >> 32) * (( B & (0xFFFFFFFF00000000) ) >> 32); + lo = (( hi & (0xFFFFFFFF00000000) ) >> 32); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evmwlumiaaw RT,RA,RB +# ISA-cmt: Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate into Words +# evmwlumiaaw rD,rA,rB 101 0100 1000 +:evmwlumiaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x548 { +# u64 temp; +# temp = RA.l *ui RB.l; +# RT.l = ACC.l + temp.h; +# temp = RA.h *ui RB.h; +# RT.h = ACC.h + temp.h; +# ACC = RT; + + lo:$(REGISTER_SIZE) = (( ACC & (0x0000000000000000) ) >> 32) + ((( A & (0x0000000000000000) ) >> 32) * (( B & (0x0000000000000000) ) >> 32)); + hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) + ((( A & (0xFFFFFFFF00000000) ) >> 32) * (( B & (0xFFFFFFFF00000000) ) >> 32)); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evmwlumianw RT,RA,RB +# ISA-cmt: Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate Negative in Words +# evmwlumianw rD,rA,rB 101 1100 1000 +:evmwlumianw D,A,B is OP=4 & A & B & D & XOP_0_10=0x5C8 { +# u64 temp; +# temp = RA.l *ui RB.l; +# RT.l = ACC.l - temp.h; +# temp = RA.h *ui RB.h; +# RT.h = ACC.h - temp.h; +# ACC = RT; + + lo:$(REGISTER_SIZE) = (( ACC & (0x0000000000000000) ) >> 32) - ((( A & (0x0000000000000000) ) >> 32) * (( B & (0x0000000000000000) ) >> 32)); + hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) - ((( A & (0xFFFFFFFF00000000) ) >> 32) * (( B & (0xFFFFFFFF00000000) ) >> 32)); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evmwlusiaaw RT,RA,RB +# ISA-cmt: Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate into Words +# evmwlusiaaw rD,rA,rB 101 0100 0000 +define pcodeop VectorMultiplyWordLowUnsignedSaturateIntegerAndAccumulateInWords1; +define pcodeop VectorMultiplyWordLowUnsignedSaturateIntegerAndAccumulateInWords2; +:evmwlusiaaw D,A,B is OP=4 & A & B & D & XOP_0_10=0x540 { +# SPEFSCR.OVH = ovh; +# SPEFSCR.OV = ovl; +# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh; +# SPEFSCR.SOV = SPEFSCR.SOV | ovl; + # TODO definition complicated + D = VectorMultiplyWordLowUnsignedSaturateIntegerAndAccumulateInWords1(A,B,ACC,spr200); + ACC = D; + flags:8 = VectorMultiplyWordLowUnsignedSaturateIntegerAndAccumulateInWords2(A,B,ACC,spr200); + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evmwlusianw RT,RA,RB +# ISA-cmt: Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate Negative in Words +# evmwlusianw rD,rA,rB 101 1100 0000 +define pcodeop VectorMultiplyWordLowUnsignedSaturateIntegerAndAccumulateNegativeInWords1; +define pcodeop VectorMultiplyWordLowUnsignedSaturateIntegerAndAccumulateNegativeInWords2; +:evmwlusianw D,A,B is OP=4 & A & B & D & XOP_0_10=0x5C0 { +# SPEFSCR.OVH = ovh; +# SPEFSCR.OV = ovl; +# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh; +# SPEFSCR.SOV = SPEFSCR.SOV | ovl; + # TODO definition complicated + D = VectorMultiplyWordLowUnsignedSaturateIntegerAndAccumulateNegativeInWords1(D,A,B,ACC,spr200); + ACC = D; + flags:8 = VectorMultiplyWordLowUnsignedSaturateIntegerAndAccumulateNegativeInWords2(D,A,B,ACC,spr200); + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evmwsmf RT,RA,RB +# ISA-cmt: Vector Multiply Word Signed, Modulo, Fractional +# evmwsmf rD,rA,rB 100 0101 1011 +:evmwsmf D,A,B is OP=4 & A & B & D & XOP_0_10=0x45B { +# RT = RA.h *sf RB.h; + + D = SignedFractionalMultiplication( (( A & (0xFFFFFFFF00000000) ) >> 32) , (( B & (0xFFFFFFFF00000000) ) >> 32) ); +} + +# evmwsmfa RT,RA,RB +# ISA-cmt: Vector Multiply Word Signed, Modulo, Fractional to Accumulator +# evmwsmfa rD,rA,rB 100 0111 1011 +:evmwsmfa D,A,B is OP=4 & A & B & D & XOP_0_10=0x47B { +# RT = RA.h *sf RB.h; +# ACC = RT; + + D = SignedFractionalMultiplication( (( A & (0xFFFFFFFF00000000) ) >> 32) , (( B & (0xFFFFFFFF00000000) ) >> 32) ); + ACC = D; +} + +# evmwsmfaa RT,RA,RB +# ISA-cmt: Vector Multiply Word Signed, Modulo, Fractional and Accumulate +# evmwsmfaa rD,rA,rB 101 0101 1011 101 0101 1011 +:evmwsmfaa D,A,B is OP=4 & A & B & D & XOP_0_10=0x55B { +# u64 temp; +# temp = RA.h *sf RB.h; +# RT = ACC + temp; +# ACC = RT; + + D = ACC + ( SignedFractionalMultiplication( (( A & (0xFFFFFFFF00000000) ) >> 32) , (( B & (0xFFFFFFFF00000000) ) >> 32) ) ); + ACC = D; +} + +# evmwsmfan RT,RA,RB +# ISA-cmt: Vector Multiply Word Signed, Modulo, Fractional and Accumulate Negative +# evmwsmfan rD,rA,rB 101 1101 1011 +:evmwsmfan D,A,B is OP=4 & A & B & D & XOP_0_10=0x5DB { +# u64 temp; +# temp = RA.h *sf RB.h; +# RT = ACC - temp; +# ACC = RT; + + D = ACC - ( SignedFractionalMultiplication( (( A & (0xFFFFFFFF00000000) ) >> 32) , (( B & (0xFFFFFFFF00000000) ) >> 32) ) ); + ACC = D; +} + +# evmwsmi RT,RA,RB +# ISA-cmt: Vector Multiply Word Signed, Modulo, Integer +# evmwsmi rD,rA,rB 100 0101 1001 +# evmwsmi confict with machhwo. +# :evmwsmi D,A,B is OP=4 & A & B & D & XOP_0_10=0x459 { +# RT = RA.h *si RB.h; + +# } + +# evmwsmia RT,RA,RB +# ISA-cmt: Vector Multiply Word Signed, Modulo, Integer to Accumulator +# evmwsmia rD,rA,rB 100 0111 1001 +:evmwsmia D,A,B is OP=4 & A & B & D & XOP_0_10=0x479 { +# RT = RA.h *si RB.h; +# ACC = RT; + + D = (( A & (0xFFFFFFFF00000000) ) >> 32) * (( B & (0xFFFFFFFF00000000) ) >> 32); + ACC = D; +} + +# evmwsmiaa RT,RA,RB +# ISA-cmt: Vector Multiply Word Signed, Modulo, Integer and Accumulate +# evmwsmiaa rD,rA,rB 101 0101 1001 +# YYY duplicate??? +# define pcodeop VectorMultiplyWordSignedModuloIntegerAndAccumulate2; +# u64 temp; +# temp = RA.h *si RB.h; +# RT = ACC + temp; +# ACC = RT; + +# :evmwsmiaa D,A,B is OP=4 & A & B & D & XOP_0_10=0x559 { +# u64 temp; +# temp = RA.h *si RB.h; +# RT = ACC + temp; +# ACC = RT; +#} + +# evmwsmian RT,RA,RB +# ISA-cmt: Vector Multiply Word Signed, Modulo, Integer and Accumulate Negative +# evmwsmian rD,rA,rB 101 1101 1001 +# evmwsmian confict with macchwso. +# ppc_instructions.sinc :macchwso. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=236 & Rc=1 +# define pcodeop VectorMultiplyWordSignedModuloIntegerAndAccumulateNegative; +# :evmwsmian D,A,B is OP=4 & A & B & D & XOP_0_10=0x5D9 { +# u64 temp; +# temp = RA.h *si RB.h; +# RT = ACC - temp; +# ACC = RT; +# } + +# evmwssf RT,RA,RB +# ISA-cmt: Vector Multiply Word Signed, Saturate, Fractional +# evmwssf rD,rA,rB 100 0101 0011 +define pcodeop VectorMultiplyWordSignedSaturateFractional1; +define pcodeop VectorMultiplyWordSignedSaturateFractional2; +:evmwssf D,A,B is OP=4 & A & B & D & XOP_0_10=0x453 { +# SPEFSCR.OVH = 0; +# SPEFSCR.OV = mov; +# SPEFSCR.SOV = SPEFSCR.SOV | mov; + # TODO definition + D = VectorMultiplyWordSignedSaturateFractional1(D,A,B,ACC); + ACC = D; + flags:8 = VectorMultiplyWordSignedSaturateFractional2(D,A,B,ACC); + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evmwssfa RT,RA,RB +# ISA-cmt: Vector Multiply Word Signed, Saturate, Fractional to Accumulator +# evmwssfa rD,rA,rB 100 0111 0011 +define pcodeop VectorMultiplyWordSignedSaturateFractionalAndAccumulate1a; +define pcodeop VectorMultiplyWordSignedSaturateFractionalAndAccumulate1b; +:evmwssfa D,A,B is OP=4 & A & B & D & XOP_0_10=0x473 { +# SPEFSCR.OVH = 0; +# SPEFSCR.OV = mov; +# SPEFSCR.SOV = SPEFSCR.SOV | mov; + # TODO definition + D = VectorMultiplyWordSignedSaturateFractionalAndAccumulate1a(D,A,B,ACC); + ACC = D; + flags:8 = VectorMultiplyWordSignedSaturateFractionalAndAccumulate1b(D,A,B,ACC); + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evmwssfaa RT,RA,RB +# ISA-cmt: Vector Multiply Word Signed, Saturate, Fractional and Accumulate +# evmwssfaa rD,rA,rB 101 0101 0011 +define pcodeop VectorMultiplyWordSignedSaturateFractionalAndAccumulate2a; +define pcodeop VectorMultiplyWordSignedSaturateFractionalAndAccumulate2b; +:evmwssfaa D,A,B is OP=4 & A & B & D & XOP_0_10=0x553 { +# SPEFSCR.OVH = 0; +# SPEFSCR.OV = ov | mov; +# SPEFSCR.SOV = SPEFSCR.SOV | ov | mov; + # TODO definition + D = VectorMultiplyWordSignedSaturateFractionalAndAccumulate2a(A,B,ACC); + flags:8 = VectorMultiplyWordSignedSaturateFractionalAndAccumulate2b(A,B,ACC); + ACC = D; + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evmwssfan RT,RA,RB +# ISA-cmt: Vector Multiply Word Signed, Saturate, Fractional and Accumulate Negative +# evmwssfan rD,rA,rB 101 1101 0011 +define pcodeop VectorMultiplyWordSignedSaturateFractionalAndAccumulateNegative1; +define pcodeop VectorMultiplyWordSignedSaturateFractionalAndAccumulateNegative2; +:evmwssfan D,A,B is OP=4 & A & B & D & XOP_0_10=0x5D3 { +# SPEFSCR.OVH = 0; +# SPEFSCR.OV = ov | mov; +# SPEFSCR.SOV = SPEFSCR.SOV | ov | mov; + # TODO definition + D = VectorMultiplyWordSignedSaturateFractionalAndAccumulateNegative1(A,B,ACC,spr200); + flags:8 = VectorMultiplyWordSignedSaturateFractionalAndAccumulateNegative2(A,B,ACC,spr200); + ACC = D; + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evmwumi RT,RA,RB +# ISA-cmt: Vector Multiply Word Unsigned, Modulo, Integer +# evmwumi rD,rA,rB 100 01A1 1000 A=0 +# evmwumi confict with machhwo +# define pcodeop VectorMultiplyWordUnsignedModuloInteger; +# :evmwumi D,A,B is OP=4 & A & B & D & XOP_0_10=0x458 { +# RT = RA.h *ui RB.h; +# VectorMultiplyWordUnsignedModuloInteger(D,A,B,ACC); +# } + +# evmwumia RT,RA,RB +# ISA-cmt: Vector Multiply Word Unsigned, Modulo, Integer to Accumulator +# evmwumia rD,rA,rB 100 01A1 1000 A=1 +:evmwumia D,A,B is OP=4 & A & B & D & XOP_0_10=0x478 { +# RT = RA.h *ui RB.h; +# ACC = RT; + + D = (( A & (0xFFFFFFFF00000000) ) >> 32) * (( B & (0xFFFFFFFF00000000) ) >> 32); + ACC = D; +} + +# evmwumiaa RT,RA,RB +# ISA-cmt: Vector Multiply Word Unsigned, Modulo, Integer and Accumulate +# evmwumiaa rD,rA,rB 101 0101 1000 +# evmwumiaa confict with macchwo +# :evmwumiaa D,A,B is OP=4 & A & B & D & XOP_0_10=0x558 { +# u64 temp; +# temp = RA.h *ui RB.h; +# RT = ACC + temp; +# ACC = RT; + +# VectorMultiplyWordUnsignedModuloIntegerAndAccumulate2(D,A,B,ACC); +# } + +# evmwumian RT,RA,RB +# ISA-cmt: Vector Multiply Word Unsigned, Modulo, Integer and Accumulate Negative +# evmwumian rD,rA,rB 101 1101 1000 +# evmwumian confict with macchwso +# :evmwumian D,A,B is OP=4 & A & B & D & XOP_0_10=0x5D8 { +# u64 temp; +# temp = RA.h *ui RB.h; +# RT = ACC - temp; +# ACC = RT; + +# VectorMultiplyWordUnsignedModuloIntegerAndAccumulateNegative(D,A,B,ACC); +# } + +# ================================================================= +# Page D-15 + +# evnand RT,RA,RB +# ISA-cmt: Vector NAND +# evnand rD,rA,rB 010 0001 1110 +:evnand D,A,B is OP=4 & A & B & D & XOP_0_10=0x21E { +# RT.l = ONESCOMP(RA.l & RB.l); +# RT.h = ONESCOMP(RA.h & RB.h); + + lo:$(REGISTER_SIZE) = ~ ( (( A & (0x00000000FFFFFFFF) ) ) & (( B & (0x00000000FFFFFFFF) ) ) ); + hi:$(REGISTER_SIZE) = ~ ( (( A & (0xFFFFFFFF00000000) ) >> 32) & (( B & (0xFFFFFFFF00000000) ) >> 32) ); + D = (( zext(hi) << 32) | zext(lo) ); +} + +# evneg RT,RA +# ISA-cmt: Vector Negate +# evneg rD,rA 010 0000 1001 +:evneg D,A is OP=4 & A & D & XOP_0_10=0x209 & BITS_11_15=0 { +# RT.l = NEG(RA.l); +# RT.h = NEG(RA.h); + + lo:$(REGISTER_SIZE) = - (( A & (0x00000000FFFFFFFF) ) ); + hi:$(REGISTER_SIZE) = - (( A & (0xFFFFFFFF00000000) ) >> 32); + D = (( zext(hi) << 32) | zext(lo) ); +} + +# evnor RT,RA,RB +# ISA-cmt: Vector NOR +# evnor rD,rA,rB 010 0001 1000 +:evnor D,A,B is OP=4 & A & B & D & XOP_0_10=0x218 { +# RT.l = ONESCOMP(RA.l | RB.l); +# RT.h = ONESCOMP(RA.h | RB.h); + + lo:$(REGISTER_SIZE) = ~ ( (( A & (0x00000000FFFFFFFF) ) ) | (( B & (0x00000000FFFFFFFF) ) ) ); + hi:$(REGISTER_SIZE) = ~ ( (( A & (0xFFFFFFFF00000000) ) >> 32) | (( B & (0xFFFFFFFF00000000) ) >> 32) ); + D = (( zext(hi) << 32) | zext(lo) ); +} + +# evnot => evnor + +# evor RT,RA,RB +# ISA-cmt: Vector OR +# evor rD,rA,rB 010 0001 0111 +:evor D,A,B is OP=4 & A & B & D & XOP_0_10=0x217 { +# RT.l = RA.l | RB.l; +# RT.h = RA.h | RB.h; + + lo:$(REGISTER_SIZE) = (( A & (0x00000000FFFFFFFF) ) ) | (( B & (0x00000000FFFFFFFF) ) ); + hi:$(REGISTER_SIZE) = (( A & (0xFFFFFFFF00000000) ) >> 32) | (( B & (0xFFFFFFFF00000000) ) >> 32); + D = (( zext(hi) << 32) | zext(lo) ); +} + +# evorc RT,RA,RB +# ISA-cmt: Vector OR with Complement +# evorc rD,rA,rB 010 0001 1011 +:evorc D,A,B is OP=4 & A & B & D & XOP_0_10=0x21B { +# RT.l = RA.l | ONESCOMP(RB.l); +# RT.h = RA.h | ONESCOMP(RB.h); + + lo:$(REGISTER_SIZE) = (( A & (0x00000000FFFFFFFF) ) ) | (~ (( B & (0x00000000FFFFFFFF) ) )); + hi:$(REGISTER_SIZE) = (( A & (0xFFFFFFFF00000000) ) >> 32) | (~ (( B & (0xFFFFFFFF00000000) ) >> 32)); + D = (( zext(hi) << 32) | zext(lo) ); +} + +define pcodeop ROTL64; + +# evrlw RT,RA,RB +# ISA-cmt: Vector Rotate Left Word +# evrlw rD,rA,rB 010 0010 1000 +:evrlw D,A,B is OP=4 & A & B & D & XOP_0_10=0x228 { +# nh = RB.bsub(27:31); +# nl = RB.bsub(59:63); +# RT.l = ROTL(RA.l, nh); +# RT.h = ROTL(RA.h, nl); + + nh:$(REGISTER_SIZE) = ((B & 0x00000000f8000000) >> 27); + nl:$(REGISTER_SIZE) = ((B & 0xf800000000000000) >> 59); + lo:8 = ROTL64( (( A & (0x00000000FFFFFFFF) ) ) ,nh); + hi:8 = ROTL64( (( A & (0xFFFFFFFF00000000) ) >> 32) ,nl); + D = (( zext(hi) << 32) | zext(lo) ); +} + +# evrlwi RT,RA,UI +# ISA-cmt: Vector Rotate Left Word Immediate +# evrlwi rD,rA,EVUIMM 010 0010 1010 +:evrlwi D,A,EVUIMM is OP=4 & A & D & EVUIMM & XOP_0_10=0x22A { +# n = UI; +# RT.l = ROTL(RA.l, n); +# RT.h = ROTL(RA.h, n); + + n:8 = EVUIMM; + lo:8 = ROTL64( (( A & (0x00000000FFFFFFFF) ) ) ,n); + hi:8 = ROTL64( (( A & (0xFFFFFFFF00000000) ) >> 32) ,n); + D = (( zext(hi) << 32) | zext(lo) ); +} + +# evrndw RT,RA +# ISA-cmt: Vector Round Word +# evrndw rD,rA 010 0000 1100 +:evrndw D,A is OP=4 & A & D & UIMM & XOP_0_10=0x20C { +# RT.l = (RA.l + 0x00008000) & 0xFFFF0000; +# RT.h = (RA.h + 0x00008000) & 0xFFFF0000; + + lo:$(REGISTER_SIZE) = ((( A & (0x00000000FFFFFFFF) ) ) + 0x00008000) & 0xFFFF0000; + hi:$(REGISTER_SIZE) = ((( A & (0x00FFFFFFFF00000000) ) >> 32) + 0x00008000) & 0xFFFF0000; + D = (( zext(hi) << 32) | zext(lo) ); +} + +# SPECIAL ** YYY +# evsel RT,RA,RB,BFA +# ISA-cmt: Vector Select +# evsel rD,rA,rB,crS 0100 1111 +# define pcodeop VectorSelect; +# :evsel D,A,B,crS is OP=4 & A & B & D & crS & XOP_3_10=0x4F { + # TODO definition complicated +# VectorSelect(D,A,B,crS); +# } + +# evslw RT,RA,RB +# ISA-cmt: Vector Shift Left Word +# evslw rD,rA,rB 010 0010 0100 +:evslw D,A,B is OP=4 & A & B & D & XOP_0_10=0x224 { +# nh = RB.bsub(26:31); +# nl = RB.bsub(58:63); +# RT.l = SL(RA.l,nh); +# RT.h = SL(RA.h,nl); + + nh:$(REGISTER_SIZE) = ((B & 0x00000000fc000000) >> 26); + nl:$(REGISTER_SIZE) = ((B & 0xfc00000000000000) >> 58); + lo:$(REGISTER_SIZE) = ((( A & (0x00000000FFFFFFFF) ) ) << nh); + hi:$(REGISTER_SIZE) = ((( A & (0xFFFFFFFF00000000) ) >> 32) << nl); + D = (( zext(hi) << 32) | zext(lo) ); +} + +# c RT,RA,UI +# ISA-cmt: Vector Shift Left Word Immediate +# evslwi rD,rA,EVUIMM 010 0010 0110 +:evslwi D,A,EVUIMM is OP=4 & A & D & EVUIMM & XOP_0_10=0x226 { +# n = UI; +# RT.l = SL(RA.l, n); +# RT.h = SL(RA.h, n); + + n:8 = EVUIMM; + lo:8 = (( A & (0x00000000FFFFFFFF) ) ) << n; + hi:8 = (( A & (0xFFFFFFFF00000000) ) >> 32) << n; + D = (( zext(hi) << 32) | zext(lo) ); +} + +# evsplatfi RT,SI +# ISA-cmt: Vector Splat Fractional Immediate +# evsplatfi rD,BU_SIMM 010 0010 1011 +define pcodeop VectorSplatFractionalImmediate; +:evsplatfi D,BU_SIMM is OP=4 & D & BU_SIMM & XOP_0_10=0x22B { + # TODO definition +# RT0:31 􀁉 SI || 270 +# RT32:63 􀁉 SI || 270 +# The value specified by SI is padded with trailing zeros +# and placed in both elements of RT. The SI ends up in +# bit positions RT0:4 and RT32:36. + + D = VectorSplatFractionalImmediate(); +} + + +# BU_SIMMt: is BU_SIMM [ val = BU_SIMM; ] { tmp:8 = sext(BU_SIMM); export tmp; } + +# evsplati RT,SI +# ISA-cmt: Vector Splat Immediate +# evsplati rD,BU_SIMM 010 0010 1001 +define pcodeop VectorSplatImmediate; +:evsplati D,BU_SIMM is OP=4 & D & BU_SIMM & XOP_0_10=0x229 { +# RT.l = EXTS(SI); +# RT.h = EXTS(SI); + +# lo:8 = BU_SIMMt; # sign or zext +# hi:8 = BU_SIMM; +# D = 64From2_32(hi,lo); + + D = VectorSplatImmediate(); +} + +# evsrwis RT,RA,UI +# ISA-cmt: Vector Shift Right Word Immediate Signed +# evsrwis rD,rA,EVUIMM 010 0010 0011 +define pcodeop VectorShiftRightWordImmediateSigned; +:evsrwis D,A,EVUIMM is OP=4 & A & D & EVUIMM & XOP_0_10=0x223 { + # TODO definition +# n 􀁉 UI +# RT0:31 􀁉 EXTS((RA)0:31-n) +# RT32:63 􀁉 EXTS((RA)32:63-n) +# Both high and low elements of RA are shifted right by +# the 5-bit UI value. Bits in the most significant positions +# vacated by the shift are filled with a copy of the sign bit. + + D = VectorShiftRightWordImmediateSigned(A); +} + +# evsrwiu RT,RA,UI +# ISA-cmt: Vector Shift Right Word Immediate Unsigned +# evsrwiu rD,rA,EVUIMM 010 0010 0010 +define pcodeop VectorShiftRightWordImmediateUnsigned; +:evsrwiu D,A,EVUIMM is OP=4 & A & D & EVUIMM & XOP_0_10=0x222 { + # TODO definition +# n 􀁉 UI +# RT0:31 􀁉 EXTZ((RA)0:31-n) +# RT32:63 􀁉 EXTZ((RA)32:63-n) +# Both high and low elements of RA are shifted right by +# the 5-bit UI value; zeros are shifted into the most significant +# position. + D = VectorShiftRightWordImmediateUnsigned(A); +} + +# evsrws RT,RA,RB +# ISA-cmt: Vector Shift Right Word Signed +# evsrws rD,rA,rB 010 0010 0001 +:evsrws D,A,B is OP=4 & A & B & D & XOP_0_10=0x221 { +# nh = RB.bsub(26:31); +# hl = RB.bsub(58:63); +# RT.l = EXTS(RA.bsub(0:32-nh)); +# RT.h = EXTS(RA.bsub(32:63-nl)); + + nh:$(REGISTER_SIZE) = 32-((B & 0x00000000fc000000) >> 26); + nl:$(REGISTER_SIZE) = 63-((B & 0xfc00000000000000) >> 58); + tmp:$(REGISTER_SIZE) = (A & ((0xFFFFFFFFFFFFFFFF >> (64 - ((nh) - (0) + 1))) << (0)) >> 0); + lo:8 = sext(tmp:4); + tmp = (A & ((0xFFFFFFFFFFFFFFFF >> (64 - ((nl) - (32) + 1))) << (32)) >> 32); + hi:8 = sext(tmp:4); + D = (( zext(hi) << 32) | zext(lo) ); +} + +# evsrwu RT,RA,RB +# ISA-cmt: Vector Shift Right Word Unsigned +# evsrwu rD,rA,rB 010 0010 0000 +:evsrwu D,A,B is OP=4 & A & B & D & XOP_0_10=0x220 { +# nh = RB.bsub(26:31); +# nl = RB.bsub(58:63); +# RT.l = EXTZ(RA.bsub(0:32-nh)); +# RT.h = EXTZ(RA.bsub(32:63-nl)); + + nh:$(REGISTER_SIZE) = 32-((B & 0x00000000fc000000) >> 26); + nl:$(REGISTER_SIZE) = 63-((B & 0xfc00000000000000) >> 58); + tmp:$(REGISTER_SIZE) = (A & ((0xFFFFFFFFFFFFFFFF >> (64 - ((nh) - (0) + 1))) << (0)) >> 0); + lo:8 = zext(tmp:4); + tmp = (A & ((0xFFFFFFFFFFFFFFFF >> (64 - ((nl) - (32) + 1))) << (32)) >> 32); + hi:8 = zext(tmp:4); + D = (( zext(hi) << 32) | zext(lo) ); +} + +# evstdd RS,D(RA) +# ISA-cmt: Vector Store Double of Double +# evstdd rD,rA,EVUIMM_8 011 0010 0001 +# defined evx.sinc EJ XXX +#define pcodeop VectorStoreDoubleOfDouble; +#:evstdd D,A,EVUIMM_8 is OP=4 & A & D & EVUIMM_8 & XOP_0_10=0x321 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + EXTZ(UI*8); +# MEM(EA,8) = RS; + +# VectorStoreDoubleOfDouble(D,A); +# } + +# evstddx RS,RA,RB +# ISA-cmt: Vector Store Double of Double Indexed +# evstddx rS,rA,rB 011 0010 0000 +# defined evx.sinc EJ XXX +# define pcodeop VectorStoreDoubleOfDoubleIndexed; +# :evstddx S,A,B is OP=4 & A & S & B & XOP_0_10=0x320 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + RB; +# MEM(EA,8) = RS; + +# VectorStoreDoubleOfDoubleIndexed(S,A,B); +# } +# :evstddx RS,RA_OR_ZERO,RB is OP=4 & RS & RA_OR_ZERO & RB & XOP_0_10=800 +# { +# ea = RA_OR_ZERO + RB; +# *:8 ($(EATRUNC)) = RS; +# } + +# evstdh RS,D(RA) +# ISA-cmt: Vector Store Double of Four Halfwords +# evstdh rS,rA,EVUIMM_8 011 0010 0101 +:evstdh S,EVUIMM_8_RAt is OP=4 & A & S & EVUIMM_8 & EVUIMM_8_RAt & XOP_0_10=0x325 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + EXTZ(UI*8); +# MEM(EA,2) = RS.S0; +# MEM(EA+2,2) = RS.S1; +# MEM(EA+4,2) = RS.S2; +# MEM(EA+6,2) = RS.S3; + + EA:$(REGISTER_SIZE) = A + zext(EVUIMM_8_RAt); + *:2 (EA) = *:2 ((S) & $(MEMMASK)); + *:2 (EA+2) = *:2 ((S+2) & $(MEMMASK)); + *:2 (EA+4) = *:2 ((S+4) & $(MEMMASK)); + *:2 (EA+6) = *:2 ((S+4) & $(MEMMASK)); +} + +# evstdhx RS,RA,RB +# ISA-cmt: Vector Store Double of Four Halfwords Indexed +# evstdhx rS,rA,rB 011 0010 0100 +:evstdhx S,A,B is OP=4 & A & B & S & XOP_0_10=0x324 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + RB; +# MEM(EA,2) = RS.S0; +# MEM(EA+2,2) = RS.S1; +# MEM(EA+4,2) = RS.S2; +# MEM(EA+6,2) = RS.S3; + + EA:$(REGISTER_SIZE) = A + B; + *:2 (EA) = *:2 ((S) & $(MEMMASK)); + *:2 (EA+2) = *:2 ((S+2) & $(MEMMASK)); + *:2 (EA+4) = *:2 ((S+4) & $(MEMMASK)); + *:2 (EA+6) = *:2 ((S+6) & $(MEMMASK)); +} + +# evstdw RS,D(RA) +# ISA-cmt: Vector Store Double of Two Words +# evstdw rS,rA,EVUIMM_8 011 0010 0011 +:evstdw S,EVUIMM_8_RAt is OP=4 & A & S & EVUIMM_8 & EVUIMM_8_RAt & XOP_0_10=0x323 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + EXTZ(UI*8); +# MEM(EA,4) = RS.l; +# MEM(EA+4,4) = RS.h; + + EA:$(REGISTER_SIZE) = A + zext(EVUIMM_8_RAt); + *:4 (EA) = *:4 ((S) & $(MEMMASK)); + *:4 (EA+4) = *:4 ((S+4) & $(MEMMASK)); +} + +# evstdwx RS,RA,RB +# ISA-cmt: Vector Store Double of Two Words Indexed +# evstdwx rS,rA,rB 011 0010 0010 +:evstdwx S,A,B is OP=4 & A & B & S & XOP_0_10=0x322 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + RB; +# MEM(EA,4) = RS.l; +# MEM(EA+4,4) = RS.h; + + EA:$(REGISTER_SIZE) = A + B; + *:4 (EA) = *:4 ((S) & $(MEMMASK)); + *:4 (EA+4) = *:4 ((S+4) & $(MEMMASK)); +} + +# evstwhe RS,D(RA) +# ISA-cmt: Vector Store Word of Two Halfwords from Even +# evstwhe rS,rA,EVUIMM_4 011 0011 0001 +:evstwhe S,EVUIMM_4_RAt is OP=4 & A & S & EVUIMM_4_RAt & XOP_0_10=0x331 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + EXTZ(UI*4); +# MEM(EA,2) = RS.S0; +# MEM(EA+2,2) = RS.S2; + + EA:$(REGISTER_SIZE) = A + zext(EVUIMM_4_RAt); + *:2 (EA) = *:2 ((S) & $(MEMMASK)); + *:2 (EA+2) = *:2 ((S+2) & $(MEMMASK)); +} + +# evstwhex RS,RA,RB +# ISA-cmt: Vector Store Word of Two Halfwords from Even Indexed +# evstwhex rS,rA,rB 011 0011 0000 +:evstwhex S,A,B is OP=4 & A & B & S & XOP_0_10=0x330 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + RB; +# MEM(EA,2) = RS.S0; +# MEM(EA+2,2) = RS.S2; + + EA:$(REGISTER_SIZE) = A + B; + *:2 (EA) = *:2 ((S) & $(MEMMASK)); + *:2 (EA+2) = *:2 ((S+2) & $(MEMMASK)); +} + +# evstwho RS,D(RA) +# ISA-cmt: Vector Store Word of Two Halfwords from Odd +# evstwho rS,rA,EVUIMM_4 011 0011 0101 +:evstwho S,EVUIMM_4_RAt is OP=4 & A & S & EVUIMM_4_RAt & XOP_0_10=0x335 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + EXTZ(UI*4); +# MEM(EA,2) = RS.S1; +# MEM(EA+2,2) = RS.S3; + + EA:$(REGISTER_SIZE) = A + zext(EVUIMM_4_RAt); + *:2 (EA) = *:2 ((S+2) & $(MEMMASK)); + *:2 (EA+2) = *:2 ((S+6) & $(MEMMASK)); +} + +# evstwhox RS,RA,RB +# ISA-cmt: Vector Store Word of Two Halfwords from Odd Indexed +# evstwhox rS,rA,rB 011 0011 0100 +:evstwhox S,A,B is OP=4 & A & B & S & XOP_0_10=0x334 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + RB; +# MEM(EA,2) = RS.S1; +# MEM(EA+2,2) = RS.S3; + + EA:$(REGISTER_SIZE) = A + B; + *:2 (EA) = *:2 ((S+2) & $(MEMMASK)); + *:2 (EA+2) = *:2 ((S+6) & $(MEMMASK)); +} + +# evstwwe RS,D(RA) +# ISA-cmt: Vector Store Word of Word from Even +# evstwwe rS,rA,EVUIMM_4 011 0011 1001 +#define pcodeop VectorStoreWordOfWordFromEven; +#:evstwwe S,EVUIMM_4_RAt is OP=4 & A & S & EVUIMM_4_RAt & XOP_0_10=0x339 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + EXTZ(UI*4); +# MEM(EA,4) = RS; + +# VectorStoreWordOfWordFromEven(S,A); +# } + +# evstwwex RS,RA,RB +# ISA-cmt: Vector Store Word of Word from Even Indexed +# evstwwex rS,rA,rB 011 0011 1000 +#define pcodeop VectorStoreWordOfWordFromEvenIndexed; +#:evstwwex S,A,B is OP=4 & A & B & S & XOP_0_10=0x338 { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + RB; +# MEM(EA,4) = RS; + +# VectorStoreWordOfWordFromEvenIndexed(S,A,B); +# } + +# evstwwo RS,D(RA) +# ISA-cmt: Vector Store Word of Word from Odd +# evstwwo rS,rA,EVUIMM_4 011 0011 1101 +:evstwwo S,EVUIMM_4_RAt is OP=4 & A & S & EVUIMM_4_RAt & XOP_0_10=0x33D { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + EXTZ(UI*4); +# MEM(EA,4) = RS.h; + + EA:$(REGISTER_SIZE) = A + zext(EVUIMM_4_RAt); + *:4 (EA) = *:4 ((S+4) & $(MEMMASK)); +} + +# evstwwox RS,RA,RB +# ISA-cmt: Vector Store Word of Word from Odd Indexed +# evstwwox rS,rA,rB 011 0011 1100 +:evstwwox S,A,B is OP=4 & A & B & S & XOP_0_10=0x33C { +# if (RA == 0) { +# b = 0; +# } else { +# b = RA; +# } +# EA = b + RB; +# MEM(EA,4) = RS.h; + + EA:$(REGISTER_SIZE) = A + B; + *:4 (EA) = *:4 ((S+4) & $(MEMMASK)); +} + +# evsubfsmiaaw RT,RA +# ISA-cmt: Vector Subtract Signed, Modulo, Integer to Accumulator Word +# evsubfsmiaaw rD,rA 100 0011 1011 +:evsubfsmiaaw D,A is OP=4 & A & D & XOP_0_10=0x4CB & BITS_11_15=0 { +# RT.l = ACC.l - RA.l; +# RT.h = ACC.h - RA.h; +# ACC = RT; + + lo:$(REGISTER_SIZE) = (( ACC & (0x00000000FFFFFFFF) ) ) - (( A & (0x00000000FFFFFFFF) ) ); + hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) - (( A & (0xFFFFFFFF00000000) ) >> 32); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# ================================================================= +# Page D-16 + +# evsubfssiaaw RT,RA +# ISA-cmt: Vector Subtract Signed, Saturate, Integer to Accumulator Word +# evsubfssiaaw rD,rA 100 1100 0011 +define pcodeop VectorSubtractSignedSaturateIntegerToAccumulatorWord1; +define pcodeop VectorSubtractSignedSaturateIntegerToAccumulatorWord2; +:evsubfssiaaw D,A is OP=4 & A & D & XOP_0_10=0x4C3 & BITS_11_15=0 { +# SPEFSCR.OVH = ovh; +# SPEFSCR.OV = ovl; +# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh; +# SPEFSCR.SOV = SPEFSCR.SOV | ovl; + # TODO definition complicated + D = VectorSubtractSignedSaturateIntegerToAccumulatorWord1(A,ACC); + flags:8 = VectorSubtractSignedSaturateIntegerToAccumulatorWord2(A,ACC,spr200); + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evsubfumiaaw RT,RA +# ISA-cmt: Vector Subtract Unsigned, Modulo, Integer to Accumulator Word +# evsubfumiaaw rD,rA 100 1100 1010 +:evsubfumiaaw D,A is OP=4 & A & D & XOP_0_10=0x4CA & BITS_11_15=0 { +# RT.l = ACC.l - RA.l; +# RT.h = ACC.h - RA.h; +# ACC = RT; + + lo:$(REGISTER_SIZE) = (( ACC & (0x0000000000000000) ) >> 32) - (( A & (0x0000000000000000) ) >> 32); + hi:$(REGISTER_SIZE) = (( ACC & (0xFFFFFFFF00000000) ) >> 32) - (( A & (0xFFFFFFFF00000000) ) >> 32); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evsubfusiaaw RT,RA +# ISA-cmt: Vector Subtract Unsigned, Saturate, Integer to Accumulator Word +# evsubfusiaaw rD,rA 100 1100 0010 +define pcodeop VectorSubtractUnsignedSaturateIntegerToAccumulatorWord1; +define pcodeop VectorSubtractUnsignedSaturateIntegerToAccumulatorWord2; +# SPEFSCR.OVH = ovh; +# SPEFSCR.OV = ovl; +# SPEFSCR.SOVH = SPEFSCR.SOVH | ovh; +# SPEFSCR.SOV = SPEFSCR.SOV | ovl; +:evsubfusiaaw D,A is OP=4 & A & D & XOP_0_10=0x4C2 & BITS_11_15=0 { + # TODO definition complicated + VectorSubtractUnsignedSaturateIntegerToAccumulatorWord1(D,A,ACC,spr200); + flags:8 = VectorSubtractUnsignedSaturateIntegerToAccumulatorWord2(D,A,ACC,spr200); + spr200 = (spr200 & (~ (0x200000000)) ) | (flags & (0x200000000)); + spr200 = (spr200 & (~ (0x2000000000000)) ) | (flags & (0x2000000000000)); + spr200 = spr200 | (flags & (0x100000000)); + spr200 = spr200 | (flags & (0x1000000000000)); +} + +# evsubfw RT,RA,RB +# ISA-cmt: Vector Subtract from Word +# evsubfw rD,rA,rB 010 0000 0100 +:evsubfw D,A,B is OP=4 & A & B & D & XOP_0_10=0x204 { +# RT.l = RB.l - RA.l; +# RT.h = RB.h - RA.h; + + lo:$(REGISTER_SIZE) = (( B & (0x00000000FFFFFFFF) ) ) - (( A & (0x00000000FFFFFFFF) ) ); + hi:$(REGISTER_SIZE) = (( B & (0xFFFFFFFF00000000) ) >> 32) - (( A & (0xFFFFFFFF00000000) ) >> 32); + D = (( zext(hi) << 32) | zext(lo) ); + ACC = D; +} + +# evsubifw RT,UI,RB +# ISA-cmt: Vector Subtract Immediate from Word +# evsubifw rD,UIMM,rB 010 0000 0110 +:evsubifw D,BITS_16_20,B is OP=4 & D & BITS_16_20 & B & XOP_0_10=0x206 { +# RT.l = RB.l - EXTZ(UI); +# RT.h = RB.h - EXTZ(UI); + + tmp:8 = BITS_16_20*1; + lo:$(REGISTER_SIZE) = (( B & (0x0000000000000000) ) >> 32) - tmp; + hi:$(REGISTER_SIZE) = (( B & (0xFFFFFFFF00000000) ) >> 32) - tmp; + D = (( zext(hi) << 32) | zext(lo) ); +} + +# evsubiw => evsubifw + +# evsubw => evsubfw + +# evxor RT,RA,RB +# ISA-cmt: Vector XOR +# evxor rD,rA,rB 010 0001 0110 +# defined evx.sinc EJ XXX +# define pcodeop VectorXOR; +# : D = 64From2_32(hi,lo); +# :evxor S,A,B is OP=4 & S & A & B & XOP_0_10=0x216 { +# RT.l = RA.l ^ RB.l; +# RT.h = RA.h ^ RB.h; + +# VectorXOR(S,A,B); +# lo = A:2 ^ B:2; +# hi = A(2) ^ B(2); +# D:2 = lo; +# D(2) = hi; +# } + +# TODO evmwlssianw RT,RA,RB +# TODO complicated + + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/SPE_EFSD.sinc b/python/icicle/Ghidra/Processors/PowerPC/data/languages/SPE_EFSD.sinc new file mode 100644 index 0000000..e7d6aab --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/SPE_EFSD.sinc @@ -0,0 +1,798 @@ +# Based on "PowerISA Version 2.06 Revision B" document dated July 23, 2010 +# Category: SPE.Embedded Float Scalar Double + +# version 1.0 + +# ================================================================= +# Page 576 + +# efdabs rT,rA +# ISA-cmt: efdabs - Floating-Point Double-Precision Absolute Value +# ISA-info: efdabs - Form "EVX" Page 576 Category "SP.FD" +# binutils: e500.d: 34: 10 a4 02 e4 efdabs r5,r4 +:efdabs D,A is OP=4 & D & A & BITS_11_15=0 & XOP_0_10=740 +{ + D = abs( A ); +} + +# ================================================================= +# Page 577 + +# efdadd rT,rA,rB +# ISA-cmt: efdadd - Floating-Point Double-Precision Add +# ISA-info: efdadd - Form "EVX" Page 577 Category "SP.FD" +# binutils: e500.d: 40: 10 a4 1a e0 efdadd r5,r4,r3 +:efdadd D,A,B is OP=4 & D & A & B & XOP_0_10=736 +{ + D = A f+ B; + setSPEFSCRAddFlags_L( A, B, D ); +} + + +# ================================================================= +# Page 582 + +# efdcfs rT,rB +# ISA-cmt: efdcfs - Floating-Point Double-Precision Convert from Single-Precision +# ISA-info: efdcfs - Form "EVX" Page 582 Category "SP.FD" +# binutils: e500.d: a4: 10 a0 22 ef efdcfs r5,r4 +:efdcfs D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=751 +{ + D = float2float( B:4 ); + setSPEFSCR_L( D ); + setSummarySPEFSCR(); +} + + +# ================================================================= +# Page 580 + +# efdcfsf rT,rB +# ISA-cmt: efdcfsf - Convert Floating-Point Double-Precision from Signed Fraction +# ISA-info: efdcfsf - Form "EVX" Page 580 Category "SP.FD" +# binutils: e500.d: 7c: 10 a0 22 f3 efdcfsf r5,r4 +:efdcfsf D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=755 +{ + # load fractional divisor as a float + tmpA:4 = 0x80000000; + tmpA = int2float( tmpA ); + setSPEFSCR_L( tmpA ); + + # check if negative + if ( ( B:4 & 0x80000000 ) != 0 ) goto ; + + # float the fractional portion of register B + tmpB:4 = int2float( B:4 ); + setSPEFSCR_L( tmpB ); + tmpB = tmpB f/ tmpA; + setSPEFSCRDivFlags_L( tmpB, tmpA, tmpB ); + + goto ; + + + + # float the fractional portion of register B, 2's complement negate + tmpB = int2float( -( B:4 ) ); + setSPEFSCR_L( tmpB ); + tmpB = tmpB f/ tmpA; + setSPEFSCRDivFlags_L( tmpB, tmpA, tmpB ); + + # negate the float + tmpB = f-( tmpB ); + setSPEFSCR_L( tmpB ); + + + + tmpC:8 = float2float( tmpB ); + setSPEFSCR_L( tmpC ); + + setSummarySPEFSCR(); + + D = tmpC; +} + + +# ================================================================= +# Page 579 + +# efdcfsi rT,rB +# ISA-cmt: efdcfsi - Convert Floating-Point Double-Precision from Signed Integer +# ISA-info: efdcfsi - Form "EVX" Page 579 Category "SP.FD" +# binutils: e500.d: 6c: 10 a0 22 f1 efdcfsi r5,r4 +:efdcfsi D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=753 +{ + # check if negative + if ( ( B:4 & 0x80000000 ) != 0 ) goto ; + + # float the integer portion of register B + tmpB:8 = int2float( B:4 ); + setSPEFSCR_L( tmpB ); + + goto ; + + + + # float the integer portion of register B, 2's complement negate + tmpB = int2float( -( B:4 ) ); + setSPEFSCR_L( tmpB ); + + # negate the float + tmpB = f-( tmpB ); + setSPEFSCR_L( tmpB ); + + + + setSummarySPEFSCR(); + + D = tmpB; +} + + +# ================================================================= +# Page 580 + +# efdcfsid rT,rB +# ISA-cmt: efdcfsid - Convert Floating-Point Double-Precision from Signed Integer Doubleword +# ISA-info: efdcfsid - Form "EVX" Page 580 Category "SP.FD" +# binutils: e500.d: 70: 10 a0 22 e3 efdcfsid r5,r4 +:efdcfsid D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=739 +{ + # check if negative + if ( ( B & 0x8000000000000000 ) != 0 ) goto ; + + # float the integer portion of register B + tmpB:8 = int2float( B ); + setSPEFSCR_L( tmpB ); + + goto ; + + + + # float the integer portion of register B, 2's complement negate + tmpB = int2float( -( B ) ); + setSPEFSCR_L( tmpB ); + + # negate the float + tmpB = f-( tmpB ); + setSPEFSCR_L( tmpB ); + + + + setSummarySPEFSCR(); + + D = tmpB; +} + + +# ================================================================= +# Page 580 + +# efdcfuf rT,rB +# ISA-cmt: efdcfuf - Convert Floating-Point Double-Precision from Unsigned Fraction +# ISA-info: efdcfuf - Form "EVX" Page 580 Category "SP.FD" +# binutils: e500.d: 80: 10 a0 22 f2 efdcfuf r5,r4 +:efdcfuf D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=754 +{ + # load fractional divisor as a float + tmpA:8 = 0x0000000100000000; + tmpA = int2float( tmpA ); + setSPEFSCR_L( tmpA ); + + # float the fractional portion of register B + tmpB:8 = int2float( B:4 ); + setSPEFSCR_L( tmpB ); + tmpB = tmpB f/ tmpA; + setSPEFSCRDivFlags_L( tmpB, tmpA, tmpB ); + + D = tmpB; +} + + +# ================================================================= +# Page 579 + +#efdcfui rT,rB +# ISA-cmt: efdcfui - Convert Floating-Point Double-Precision from Unsigned Integer +# ISA-info: efdcfui - Form "EVX" Page 579 Category "SP.FD" +# binutils: e500.d: 74: 10 a0 22 f0 efdcfui r5,r4 +:efdcfui D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=752 +{ + tmp:8 = int2float( B:4 ); + setSPEFSCR_L( tmp ); + + setSummarySPEFSCR(); + + D = tmp; +} + + +# ================================================================= +# Page 580 + +#efdcfuid rT,rB +# ISA-cmt: efdcfuid - Convert Floating-Point Double-Precision from Unsigned Integer Doubleword +# ISA-info: efdcfuid - Form "EVX" Page 580 Category "SP.FD" +# binutils: e500.d: 78: 10 a0 22 e2 efdcfuid r5,r4 +:efdcfuid D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=738 +{ + tmp:8 = int2float( B ); + setSPEFSCR_L( tmp ); + + setSummarySPEFSCR(); + + D = tmp; +} + + +# ================================================================= +# Page 578 + +# efdcmpeq CRFD,rA,rB +# ISA-cmt: efdcmpeq - Floating-Point Double-Precision Compare Equal +# ISA-info: efdcmpeq - Form "EVX" Page 578 Category "SP.FD" +# binutils: e500.d: 58: 12 84 1a ee efdcmpeq cr5,r4,r3 +:efdcmpeq CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=750 +{ + CRFD = A f== B; +} + + +# ================================================================= +# Page 578 + +# efdcmpgt CRFD,rA,rB +# ISA-cmt: efdcmpgt - Floating-Point Double-Precision Compare Greater Than +# ISA-info: efdcmpgt - Form "EVX" Page 578 Category "SP.FD" +# binutils: e500.d: 50: 12 84 1a ec efdcmpgt cr5,r4,r3 +:efdcmpgt CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=748 +{ + CRFD = A f> B; +} + + +# ================================================================= +# Page 578 + +# efdcmplt CRFD,rA,rB +# ISA-cmt: efdcmplt - Floating-Point Double-Precision Compare Less Than +# ISA-info: efdcmplt - Form "EVX" Page 578 Category "SP.FD" +# binutils: e500.d: 54: 12 84 1a ed efdcmplt cr5,r4,r3 +:efdcmplt CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=749 +{ + CRFD = A f< B; +} + + +# ================================================================= +# Page 578 + +# efdctsf rT,rB +# ISA-cmt: efdctsf - Convert Floating-Point Double-Precision to Signed Fraction +# ISA-info: efdctsf - Form "EVX" Page 582 Category "SP.FD" +# binutils: e500.d: 9c: 10 a0 22 f7 efdctsf r5,r4 +:efdctsf D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=759 +{ + # multiply by 0x8000 0000 0000 0000 to scale the fraction up to integer range + + # load fractional multiplier as a float + tmpM:8 = 0x8000000000000000; + tmpM = int2float( tmpM ); + setSPEFSCR_L( tmpM ); + + # load saturation limit as a float + tmpL:8 = 0x8000000000000000 - 1; + tmpL = int2float( tmpL ); + setSPEFSCR_L( tmpL ); + + # scale the saturation limit to a fractional float + tmpL = tmpL f/ tmpM; + setSPEFSCRDivFlags_L( tmpL, tmpM, tmpL ); + + tmpB:8 = B; + + # check if less than or equal to positive saturation limit + if ( tmpB f<= tmpL ) goto ; + + # set to positive saturation + tmpB = tmpL; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + goto ; + + + + # check if greater than or equal to negative saturation limit + tmpL = f-( tmpL ); + if ( tmpB f>= tmpL ) goto ; + + # set to negative saturation + tmpB = tmpL; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + # scale the fractional portion up to integer side of mantissa + tmpB = tmpB f* tmpM; + setSPEFSCRMulFlags_L( tmpB, tmpM, tmpB ); + + # truncate back to signed fraction format + tmpC:8 = trunc( tmpB ); + setSPEFSCR_L( tmpB ); + + setSummarySPEFSCR(); + + D = tmpC; +} + + +# ================================================================= +# Page 580 + +# efdctsi rT,rB +# ISA-cmt: efdctsi - Convert Floating-Point Double-Precision to Signed Integer +# ISA-info: efdctsi - Form "EVX" Page 580 Category "SP.FD" +# binutils: e500.d: 84: 10 a0 22 f5 efdctsi r5,r4 +:efdctsi D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=757 +{ + # create zero float constant + tmpA:8 = 0; + tmpA = int2float( tmpA ); + + # check if negative + if ( B f< tmpA ) goto ; + + tmpB:8 = round( B ); + setSPEFSCR_L( tmpB ); + + # limit to positive saturation + if ( tmpB <= 0x000000007FFFFFFF ) goto ; + tmpB = 0x000000007FFFFFFF; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + goto ; + + + + # negate the float + tmpB = round( f-( B ) ); + setSPEFSCR_L( tmpB ); + + # limit to negative saturation + if ( tmpB <= 0x0000000080000000 ) goto ; + tmpB = 0x0000000080000000; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + # negate the signed int + tmpB = -( tmpB ); + + + + setSummarySPEFSCR(); + + # assign to lower word of D + D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpB:4 ); +} + + +# ================================================================= +# Page 581 + +# efdctsidz rT,rB +# ISA-cmt: efdctsidz - Convert Floating-Point Double-Precision to Signed Integer Doubleword with Round toward Zero +# ISA-info: efdctsidz - Form "EVX" Page 581 Category "SP.FD" +# binutils: e500.d: 88: 10 a0 22 eb efdctsidz r5,r4 +# Note: This may not work correctly as the number approaches saturation; too little (16 digits) precision in mantissa +:efdctsidz D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=747 +{ + # create zero float constant + tmpA:8 = 0; + tmpA = int2float( tmpA ); + + tmpB:8 = B; + + # check if negative + if ( tmpB f< tmpA ) goto ; + + # load saturation limit as a float + tmpL:8 = 0x8000000000000000 - 1; + tmpL = int2float( tmpL ); + setSPEFSCR_L( tmpL ); + + # limit to saturation + if ( tmpB <= tmpL ) goto ; + tmpB = tmpL; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + tmpB = trunc( tmpB ); + setSPEFSCR_L( tmpB ); + + goto ; + + + + # load saturation limit as a float + tmpL = 0x8000000000000000; + tmpL = int2float( tmpL ); + setSPEFSCR_L( tmpL ); + + # negate float (make positive) + tmpB = f-( tmpB ); + + # limit to saturation + if ( tmpB <= tmpL ) goto ; + tmpB = tmpL; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + tmpB = trunc( tmpB ); + setSPEFSCR_L( tmpB ); + + # negate the signed int + tmpB = -( tmpB ); + + + + setSummarySPEFSCR(); + + D = tmpB; +} + + +# ================================================================= +# Page 582 + +# efdctsiz rT,rB +# ISA-cmt: efdctsiz - Convert Floating-Point Double-Precision to Signed Integer with Round toward Zero +# ISA-info: efdctsiz - Form "EVX" Page 582 Category "SP.FD" +# binutils: e500.d: 8c: 10 a0 22 fa efdctsiz r5,r4 +:efdctsiz D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=762 +{ + # create zero float constant + tmpA:8 = 0; + tmpA = int2float( tmpA ); + + # check if negative + if ( B f< tmpA ) goto ; + + tmpB:8 = trunc( B ); + setSPEFSCR_L( tmpB ); + + # limit to positive saturation + if ( tmpB <= 0x000000007FFFFFFF ) goto ; + tmpB = 0x000000007FFFFFFF; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + goto ; + + + + # negate the float + tmpB = trunc( f-( B ) ); + setSPEFSCR_L( tmpB ); + + # limit to negative saturation + if ( tmpB <= 0x0000000080000000 ) goto ; + tmpB = 0x0000000080000000; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + # negate the signed int + tmpB = -( tmpB ); + + + + setSummarySPEFSCR(); + + # assign to lower word of D + D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpB:4 ); +} + + +# ================================================================= +# Page 582 + +# efdctuf rT,rB +# ISA-cmt: efdctuf - Convert Floating-Point Double-Precision to Unsigned Fraction +# ISA-info: efdctuf - Form "EVX" Page 582 Category "SP.FD" +# binutils: e500.d: a0: 10 a0 22 f6 efdctuf r5,r4 +:efdctuf D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=758 +{ + # multiply by 0x0000 0001 0000 0000 to scale the fraction up to integer range + + # load fractional multiplier as a float + tmpM:8 = 0x0000000100000000; + tmpM = int2float( tmpM ); + setSPEFSCR_L( tmpM ); + + # load saturation limit as a float + tmpL:8 = 0x0000000100000000 - 1; + tmpL = int2float( tmpL ); + setSPEFSCR_L( tmpL ); + + # scale the saturation limit to a fractional float + tmpL = tmpL f/ tmpM; + setSPEFSCRDivFlags_L( tmpL, tmpM, tmpL ); + + # get B float up to 64 bit width + tmpB:8 = B; + setSPEFSCR_L( tmpB ); + + # check if less than or equal to positive saturation limit + if ( tmpB f<= tmpL ) goto ; + + # set to saturation + tmpB = tmpL; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + # scale the fractional portion up to integer side of mantissa + tmpB = tmpB f* tmpM; + setSPEFSCRMulFlags_L( tmpB, tmpM, tmpB ); + + # truncate back to integer + tmpC:4 = trunc( tmpB ); + setSPEFSCR_L( tmpC ); + + setSummarySPEFSCR(); + + # assign to lower word of D + D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpC ); +} + + +# ================================================================= +# Page 580 + +# efdctui rT,rB +# ISA-cmt: efdctui - Convert Floating-Point Double-Precision to Unsigned Integer +# ISA-info: efdctui - Form "EVX" Page 580 Category "SP.FD" +# binutils: e500.d: 90: 10 a0 22 f4 efdctui r5,r4 +:efdctui D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=756 +{ + tmpB:8 = B; + + # load saturation limit as a float + tmpL:8 = 0x00000000FFFFFFFF; + tmpL = int2float( tmpL ); + setSPEFSCR_L( tmpL ); + + # limit to saturation + if ( tmpB f<= tmpL ) goto ; + tmpB = tmpL; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + # round back to integer + tmpC:4 = trunc(round( tmpB )); + setSPEFSCR_L( tmpB ); + + setSummarySPEFSCR(); + + # assign to lower word of D + D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpC ); +} + + +# ================================================================= +# Page 581 + +# efdctuidz rT,rB +# ISA-cmt: efdctuidz - Convert Floating-Point Double-Precision to Unsigned Integer Doubleword with Round toward Zero +# ISA-info: efdctuidz - Form "EVX" Page 581 Category "SP.FD" +# binutils: e500.d: 94: 10 a0 22 ea efdctuidz r5,r4 +:efdctuidz D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=746 +{ + tmpB:8 = B; + + # load saturation limit as a float + tmpL:8 = 0xFFFFFFFFFFFFFFFF; + tmpL = int2float( tmpL ); + setSPEFSCR_L( tmpL ); + + # limit to saturation + if ( tmpB f<= tmpL ) goto ; + tmpB = tmpL; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + tmpB = trunc( tmpB ); + + setSummarySPEFSCR(); + + D = tmpB; +} + + +# ================================================================= +# Page 582 + +# efdctuiz rT,rB +# ISA-cmt: efdctuiz - Convert Floating-Point Double-Precision to Unsigned Integer with Round toward Zero +# ISA-info: efdctuiz - Form "EVX" Page 582 Category "SP.FD" +# binutils: e500.d: 98: 10 a0 22 f8 efdctuiz r5,r4 +:efdctuiz D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=760 +{ + tmpB:8 = B; + + # load saturation limit as a float + tmpL:8 = 0x00000000FFFFFFFF; + tmpL = int2float( tmpL ); + setSPEFSCR_L( tmpL ); + + # limit to saturation + if ( tmpB f<= tmpL ) goto ; + tmpB = tmpL; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + tmpB = trunc( tmpB ); + + setSummarySPEFSCR(); + + # assign to lower word of D + D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpB:4 ); +} + + +# ================================================================= +# Page 577 + +# efddiv rT,rA,rB +# ISA-cmt: efddiv - Floating-Point Double-Precision Divide +# ISA-info: efddiv - Form "EVX" Page 577 Category "SP.FD" +# binutils: e500.d: 4c: 10 a4 1a e9 efddiv r5,r4,r3 +:efddiv D,A,B is OP=4 & D & A & B & XOP_0_10=745 +{ + D = A f/ B; + setSPEFSCRDivFlags_L( A, B, D ); +} + + +# ================================================================= +# Page 577 + +# efdmul rT,rA,rB +# ISA-cmt: efdmul - Floating-Point Double-Precision Multiply +# ISA-info: efdmul - Form "EVX" Page 577 Category "SP.FD" +# binutils: e500.d: 48: 10 a4 1a e8 efdmul r5,r4,r3 +:efdmul D,A,B is OP=4 & D & A & B & XOP_0_10=744 +{ + D = A f* B; + setSPEFSCRMulFlags_L( A, B, D ); +} + + +# ================================================================= +# Page 576 + +# efdnabs rT,rA +# ISA-cmt: efdnabs - Floating-Point Double-Precision Negative Absolute Value +# ISA-info: efdnabs - Form "EVX" Page 576 Category "SP.FD" +# binutils: e500.d: 38: 10 a4 02 e5 efdnabs r5,r4 +:efdnabs D,A is OP=4 & D & A & BITS_11_15=0 & XOP_0_10=741 +{ + D = f- ( abs( A ) ); +} + + +# ================================================================= +# Page 577 + +# efdneg rT,rA +# ISA-cmt: efdneg - Floating-Point Double-Precision Negate +# ISA-info: efdneg - Form "EVX" Page 576 Category "SP.FD" +# binutils: e500.d: 3c: 10 a4 02 e6 efdneg r5,r4 +:efdneg D,A is OP=4 & D & A & BITS_11_15=0 & XOP_0_10=742 +{ + D = f-( A ); +} + + +# ================================================================= +# Page 577 + +# efdsub rT,rA,rB +# ISA-cmt: efdsub - Floating-Point Double-Precision Subtract +# ISA-info: efdsub - Form "EVX" Page 577 Category "SP.FD" +# binutils: e500.d: 44: 10 a4 1a e1 efdsub r5,r4,r3 +:efdsub D,A,B is OP=4 & D & A & B & XOP_0_10=737 +{ + D = A f- B; + setSPEFSCRSubFlags_L( A, B, D ); +} + + +# ================================================================= +# Page 579 + +# efdtsteq CRFD,rA,rB +# ISA-cmt: efdtsteq - Floating-Point Double-Precision Test Equal +# ISA-info: efdtsteq - Form "EVX" Page 579 Category "SP.FD" +# binutils: e500.d: 68: 12 84 1a fe efdtsteq cr5,r4,r3 +:efdtsteq CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=766 +{ + CRFD = A f== B; +} + + +# ================================================================= +# Page 578 + +# efdtstgt CRFD,rA,rB +# ISA-cmt: efdtstgt - Floating-Point Double-Precision Test Greater Than +# ISA-info: efdtstgt - Form "EVX" Page 578 Category "SP.FD" +# binutils: e500.d: 5c: 12 84 1a fc efdtstgt cr5,r4,r3 +# binutils: e500.d: 60: 12 84 1a fc efdtstgt cr5,r4,r3 +:efdtstgt CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=764 +{ + CRFD = A f> B; +} + + +# ================================================================= +# Page 579 + +# efdtstlt CRFD,rA,rB +# ISA-cmt: efdtstlt - Floating-Point Double-Precision Test Less Than +# ISA-info: efdtstlt - Form "EVX" Page 579 Category "SP.FD" +# binutils: e500.d: 64: 12 84 1a fd efdtstlt cr5,r4,r3 +:efdtstlt CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=765 +{ + CRFD = A f< B; +} + + +# ================================================================= +# Page 583 + +# efscfd rT,rB +# ISA-cmt: efscfd - Floating-Point Single-Precision Convert from Double-Precision +# ISA-info: efscfd - Form "EVX" Page 583 Category "SP.FD" +# binutils: e500.d: 30: 10 a0 22 cf efscfd r5,r4 +:efscfd D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=719 +{ + tmpB:4 = float2float( B ); + setSPEFSCR_L( tmpB ); + setSummarySPEFSCR(); + + # assign to lower word of D + D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpB ); +} diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/SPE_EFV.sinc b/python/icicle/Ghidra/Processors/PowerPC/data/languages/SPE_EFV.sinc new file mode 100644 index 0000000..b71ddd3 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/SPE_EFV.sinc @@ -0,0 +1,1491 @@ +# Based on "PowerISA Version 2.06 Revision B" document dated July 23, 2010 +# Category: SPE.Embedded Float Vector Instructions + + +# ================================================================= +# Page 561 + +# evfsabs rT,rA +# ISA-cmt: evfsabs - Vector Floating-Point Single-Precision Absolute Value +# ISA-info: evfsabs - Form "EVX" Page 561 Category "SP.FV" +# binutils: mytest.d: 1e0: 10 22 02 84 evfsabs r1,r2 +:evfsabs D,A is OP=4 & D & A & BITS_11_15=0 & XOP_0_10=644 +{ + # + # low section + # + tmpA:4 = abs( A:4 ); + + # + # high section + # + tmpB:4 = abs( A(4) ); + + # move results into upper and lower words + tmpC:8 = zext( tmpB ); + tmpC = ( tmpC << 32 ) | zext( tmpA ); + + D = tmpC; +} + +# ================================================================= +# Page 562 + +# evfsadd rT,rA,rB +# ISA-cmt: evfsadd - Vector Floating-Point Single-Precision Add +# ISA-info: evfsadd - Form "EVX" Page 562 Category "SP.FV" +# binutils: mytest.d: 1d8: 10 22 1a 80 evfsadd r1,r2,r3 +:evfsadd D,A,B is OP=4 & D & A & B & XOP_0_10=640 +{ + # + # low section + # + tmpA:4 = A:4 f+ B:4; + setSPEFSCRAddFlags_L( A:4, B:4, tmpA ); + + # + # high section + # + tmpB:4 = A(4) f+ B(4); + + # SLEIGH had a problem with using A(4) and B(4) directly here + tmpD:4 = A(4); + tmpE:4 = B(4); + setSPEFSCRAddFlags_H( tmpD, tmpE, tmpB ); + + # move results into upper and lower words + tmpC:8 = zext( tmpB ); + tmpC = ( tmpC << 32 ) | zext( tmpA ); + + D = tmpC; +} + + +# ================================================================= +# Page 566 + +# evfscfsf rT,rB +# ISA-cmt: evfscfsf - Vector Convert Floating-Point Single-Precision from Signed Fraction +# ISA-info: evfscfsf - Form "EVX" Page 566 Category "SP.FV" +# binutils: mytest.d: 20c: 10 20 12 93 evfscfsf r1,r2 +:evfscfsf D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=659 +{ + # load fractional divisor as a float + tmpA:4 = 0x80000000; + tmpA = int2float( tmpA ); + setSPEFSCR_L( tmpA ); + + # + # low section + # + tmpE:4 = B:4; + + # check if negative + if ( ( tmpE & 0x80000000 ) != 0 ) goto ; + + # float the fractional portion of register B + tmpB:4 = int2float( tmpE ); + setSPEFSCR_L( tmpB ); + tmpC:4 = tmpB f/ tmpA; + setSPEFSCRDivFlags_L( tmpB, tmpA, tmpC ); + + goto ; + + + + # float the fractional portion of register B, 2's complement negate + tmpB = int2float( -( tmpE ) ); + setSPEFSCR_L( tmpB ); + tmpC = tmpB f/ tmpA; + setSPEFSCRDivFlags_L( tmpB, tmpA, tmpC ); + + # negate the float + tmpC = f-( tmpC ); + setSPEFSCR_L( tmpC ); + + + + setSummarySPEFSCR(); + + # + # high section + # + tmpE = B(4); + + # check if negative + if ( ( tmpE & 0x80000000 ) != 0 ) goto ; + + # float the fractional portion of register B + tmpB = int2float( tmpE ); + setSPEFSCR_H( tmpB ); + tmpD:4 = tmpB f/ tmpA; + setSPEFSCRDivFlags_H( tmpB, tmpA, tmpD ); + + goto ; + + + + # float the fractional portion of register B, 2's complement negate + tmpB = int2float( -( tmpE ) ); + setSPEFSCR_H( tmpB ); + tmpD = tmpB f/ tmpA; + setSPEFSCRDivFlags_H( tmpB, tmpA, tmpD ); + + # negate the float + tmpD = f-( tmpD ); + setSPEFSCR_H( tmpD ); + + + + setSummarySPEFSCR(); + + + # move results into upper and lower words + tmpZ:8 = zext( tmpD ); + tmpZ = ( tmpZ << 32 ) | zext( tmpC ); + + D = tmpZ; +} + + +# ================================================================= +# Page 566 + +# evfscfsi rT,rB +# ISA-cmt: evfscfsi - Vector Convert Floating-Point Single-Precision from Signed Integer +# ISA-info: evfscfsi - Form "EVX" Page 566 Category "SP.FV" +# binutils: mytest.d: 204: 10 20 12 91 evfscfsi r1,r2 +:evfscfsi D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=657 +{ + # + # low section + # + tmpE:4 = B:4; + + # check if negative + if ( ( tmpE & 0x80000000 ) != 0 ) goto ; + + # float the integer portion of register B + tmpB:4 = int2float( tmpE ); + setSPEFSCR_L( tmpB ); + + goto ; + + + + # float the integer portion of register B, 2's complement negate + tmpB = int2float( -( tmpE ) ); + setSPEFSCR_L( tmpB ); + + # negate the float + tmpB = f-( tmpB ); + setSPEFSCR_L( tmpB ); + + + + setSummarySPEFSCR(); + + + # + # high section + # + tmpE = B(4); + + # check if negative + if ( ( tmpE & 0x80000000 ) != 0 ) goto ; + + # float the integer portion of register B + tmpC:4 = int2float( tmpE ); + setSPEFSCR_H( tmpC ); + + goto ; + + + + # float the integer portion of register B, 2's complement negate + tmpC = int2float( -( tmpE ) ); + setSPEFSCR_H( tmpC ); + + # negate the float + tmpC = f-( tmpC ); + setSPEFSCR_H( tmpC ); + + + + setSummarySPEFSCR(); + + + # move results into upper and lower words + tmpZ:8 = zext( tmpC ); + tmpZ = ( tmpZ << 32 ) | zext( tmpB ); + + D = tmpZ; +} + + +# ================================================================= +# Page 566 + +# evfscfuf rT,rB +# ISA-cmt: evfscfuf - Vector Convert Floating-Point Single-Precision from Unsigned Fraction +# ISA-info: evfscfuf - Form "EVX" Page 566 Category "SP.FV" +# binutils: mytest.d: 208: 10 20 12 92 evfscfuf r1,r2 +:evfscfuf D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=658 +{ + # load fractional divisor as a float + tmpA:8 = 0x0000000100000000; + tmpF:4 = int2float( tmpA ); + setSPEFSCR_L( tmpF ); + + # + # low section + # + tmpE:4 = B:4; + + # float the fractional portion of register B + tmpB:4 = int2float( tmpE ); + setSPEFSCR_L( tmpB ); + tmpC:4 = tmpB f/ tmpF; + setSPEFSCRDivFlags_L( tmpB, tmpF, tmpC ); + + # + # high section + # + tmpE = B(4); + + # float the fractional portion of register B + tmpB = int2float( tmpE ); + setSPEFSCR_H( tmpB ); + tmpD:4 = tmpB f/ tmpF; + setSPEFSCRDivFlags_H( tmpB, tmpF, tmpD ); + + # move results into upper and lower words + tmpZ:8 = zext( tmpD ); + tmpZ = ( tmpZ << 32 ) | zext( tmpC ); + + D = tmpZ; +} + + +# ================================================================= +# Page 566 + +#evfscfui rT,rB +# ISA-cmt: evfscfui - Vector Convert Floating-Point Single-Precision from Unsigned Integer +# ISA-info: evfscfui - Form "EVX" Page 566 Category "SP.FV" +# binutils: mytest.d: 200: 10 20 12 90 evfscfui r1,r2 +:evfscfui D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=656 +{ + # + # low section + # + tmpE:4 = B:4; + + tmpC:4 = int2float( tmpE ); + setSPEFSCR_L( tmpC ); + + # + # high section + # + tmpE = B(4); + + tmpD:4 = int2float( tmpE ); + setSPEFSCR_H( tmpD ); + + setSummarySPEFSCR(); + + + # move results into upper and lower words + tmpZ:8 = zext( tmpD ); + tmpZ = ( tmpZ << 32 ) | zext( tmpC ); + + D = tmpZ; +} + + +# ================================================================= +# Page 564 + +# evfscmpeq CRFD,rA,rB +# ISA-cmt: evfscmpeq - Vector Floating-Point Single-Precision Compare Equal +# ISA-info: evfscmpeq - Form "EVX" Page 564 Category "SP.FV" +# binutils: mytest.d: 1fc: 10 82 1a 8e evfscmpeq cr1,r2,r3 +:evfscmpeq CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=654 +{ + tmpA:4 = A:4; + tmpB:4 = B:4; + tmpC:4 = A(4); + tmpD:4 = B(4); + + tmpL:1 = tmpA f== tmpB; + tmpH:1 = tmpC f== tmpD; + + CRFD = (8 * tmpH ) + (4 * tmpL ) + (2 * (tmpH | tmpL) ) + (tmpH & tmpL); +} + + +# ================================================================= +# Page 563 + +# evfscmpgt CRFD,rA,rB +# ISA-cmt: evfscmpgt - Vector Floating-Point Single-Precision Compare Greater Than +# ISA-info: evfscmpgt - Form "EVX" Page 563 Category "SP.FV" +# binutils: mytest.d: 1f4: 10 82 1a 8c evfscmpgt cr1,r2,r3 +:evfscmpgt CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=652 +{ + tmpA:4 = A:4; + tmpB:4 = B:4; + tmpC:4 = A(4); + tmpD:4 = B(4); + + tmpL:1 = tmpA f> tmpB; + tmpH:1 = tmpC f> tmpD; + + CRFD = (8 * tmpH ) + (4 * tmpL ) + (2 * (tmpH | tmpL) ) + (tmpH & tmpL); +} + + +# ================================================================= +# Page 563 + +# evfscmplt CRFD,rA,rB +# ISA-cmt: evfscmplt - Vector Floating-Point Single-Precision Compare Less Than +# ISA-info: evfscmplt - Form "EVX" Page 563 Category "SP.FV" +# binutils: mytest.d: 1f8: 10 82 1a 8d evfscmplt cr1,r2,r3 +:evfscmplt CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=653 +{ + tmpA:4 = A:4; + tmpB:4 = B:4; + tmpC:4 = A(4); + tmpD:4 = B(4); + + tmpL:1 = tmpA f< tmpB; + tmpH:1 = tmpC f< tmpD; + + CRFD = (8 * tmpH ) + (4 * tmpL ) + (2 * (tmpH | tmpL) ) + (tmpH & tmpL); +} + + +# ================================================================= +# Page 568 + +# evfsctsf rT,rB +# ISA-cmt: evfsctsf - Vector Convert Floating-Point Single-Precision to Signed Fraction +# ISA-info: evfsctsf - Form "EVX" Page 568 Category "SP.FV" +# binutils: mytest.d: 21c: 10 20 12 97 evfsctsf r1,r2 +:evfsctsf D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=663 +{ + # multiply by 0x8000 0000 to scale the fraction up to integer range + + # load fractional multiplier as a float + tmpM:4 = 0x80000000; + tmpM = int2float( tmpM ); + setSPEFSCR_L( tmpM ); + + # load saturation limit as a float + tmpS:4 = 0x80000000 - 1; + tmpS = int2float( tmpS ); + setSPEFSCR_L( tmpS ); + + # scale the saturation limit to a fractional float + tmpS = tmpS f/ tmpM; + setSPEFSCRDivFlags_L( tmpS, tmpM, tmpS ); + + # form negative saturation limit + tmpN:4 = f-( tmpS ); + + # + # low section + # + tmpB:4 = B:4; + + # check if less than or equal to positive saturation limit + if ( tmpB f<= tmpS ) goto ; + + # set to positive saturation + tmpB = tmpS; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + goto ; + + + + # check if greater than or equal to negative saturation limit + if ( tmpB f>= tmpN ) goto ; + + # set to negative saturation + tmpB = tmpN; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + # scale the fractional portion up to integer side of mantissa + tmpB = tmpB f* tmpM; + setSPEFSCRMulFlags_L( tmpB, tmpM, tmpB ); + + # truncate back to signed fraction format + tmpL:4 = trunc( tmpB ); + setSPEFSCR_L( tmpL ); + + setSummarySPEFSCR(); + + + # + # high section + # + tmpB = B(4); + + # check if less than or equal to positive saturation limit + if ( tmpB f<= tmpS ) goto ; + + # set to positive saturation + tmpB = tmpS; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + goto ; + + + + # check if greater than or equal to negative saturation limit + if ( tmpB f>= tmpN ) goto ; + + # set to negative saturation + tmpB = tmpN; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + # scale the fractional portion up to integer side of mantissa + tmpB = tmpB f* tmpM; + setSPEFSCRMulFlags_H( tmpB, tmpM, tmpB ); + + # truncate back to signed fraction format + tmpH:4 = trunc( tmpB ); + setSPEFSCR_H( tmpH ); + + setSummarySPEFSCR(); + + # move results into upper and lower words + tmpZ:8 = zext( tmpH ); + tmpZ = ( tmpZ << 32 ) | zext( tmpL ); + + D = tmpZ; +} + + +# ================================================================= +# Page 567 + +# evfsctsi rT,rB +# ISA-cmt: evfsctsi - Vector Convert Floating-Point Single-Precision to Signed Integer +# ISA-info: evfsctsi - Form "EVX" Page 567 Category "SP.FV" +# binutils: mytest.d: 214: 10 20 12 95 evfsctsi r1,r2 +:evfsctsi D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=661 +{ + # create zero float constant + tmpA:4 = 0; + tmpA = int2float( tmpA ); + + # + # low section + # + tmpB:4 = B:4; + + # check if negative + if ( tmpB f< tmpA ) goto ; + + tmpB = round( tmpB ); + setSPEFSCR_L( tmpB ); + + # limit to positive saturation + if ( tmpB <= 0x000000007FFFFFFF ) goto ; + tmpB = 0x000000007FFFFFFF; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + tmpL:4 = tmpB; + + goto ; + + + + # negate the float + tmpB = round( f-( tmpB ) ); + setSPEFSCR_L( tmpB ); + + # limit to negative saturation + if ( tmpB <= 0x0000000080000000 ) goto ; + tmpB = 0x0000000080000000; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + # negate the signed int + tmpL = -( tmpB ); + + + + setSummarySPEFSCR(); + + # + # high section + # + tmpB = B(4); + + # check if negative + if ( tmpB f< tmpA ) goto ; + + tmpB = round( tmpB ); + setSPEFSCR_H( tmpB ); + + # limit to positive saturation + if ( tmpB <= 0x000000007FFFFFFF ) goto ; + tmpB = 0x000000007FFFFFFF; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + tmpH:4 = tmpB; + + goto ; + + + + # negate the float + tmpB = round( f-( tmpB ) ); + setSPEFSCR_H( tmpB ); + + # limit to negative saturation + if ( tmpB <= 0x0000000080000000 ) goto ; + tmpB = 0x0000000080000000; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + # negate the signed int + tmpH = -( tmpB ); + + + + setSummarySPEFSCR(); + + # move results into upper and lower words + tmpZ:8 = zext( tmpH ); + tmpZ = ( tmpZ << 32 ) | zext( tmpL ); + + D = tmpZ; +} + + +# ================================================================= +# Page 567 + +# evfsctsiz rT,rB +# ISA-cmt: evfsctsiz - Vector Convert Floating-Point Single-Precision to Signed Integer with Round toward Zero +# ISA-info: evfsctsiz - Form "EVX" Page 567 Category "SP.FV" +# binutils: mytest.d: 224: 10 20 12 9a evfsctsiz r1,r2 +:evfsctsiz D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=666 +{ + # create zero float constant + tmpA:8 = 0; + tmpA = int2float( tmpA ); + + # create positive saturation float constant + tmpS:8 = 0x000000007FFFFFFF; + tmpS = int2float( tmpS ); + + # create negative saturation float constant + tmpN:8 = 0x0000000080000000; + tmpN = int2float( tmpN ); + + # + # low section + # + tmpB:8 = float2float( B:4 ); + + # check if negative + if ( tmpB f< tmpA ) goto ; + + # limit to positive saturation + if ( tmpB f<= tmpS ) goto ; + tmpB = tmpS; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + tmpL:4 = trunc( tmpB ); + setSPEFSCR_L( tmpL ); + + goto ; + + + + + # negate the float + tmpB = f-( tmpB ); + + # limit to negative saturation + if ( tmpB f<= tmpN ) goto ; + tmpB = tmpN; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + # negate the signed int + tmpL = -( trunc( tmpB ) ); + setSPEFSCR_L( tmpL ); + + + + setSummarySPEFSCR(); + + # + # high section + # + tmpE:4 = B(4); + tmpB = float2float( tmpE ); + + # check if negative + if ( tmpB f< tmpA ) goto ; + + # limit to positive saturation + if ( tmpB f<= tmpS ) goto ; + tmpB = tmpS; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + tmpH:4 = trunc( tmpB ); + setSPEFSCR_H( tmpH ); + + goto ; + + + + + # negate the float + tmpB = f-( tmpB ); + + # limit to negative saturation + if ( tmpB f<= tmpN ) goto ; + tmpB = tmpN; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + # negate the signed int + tmpH = -( trunc( tmpB ) ); + setSPEFSCR_H( tmpH ); + + + + setSummarySPEFSCR(); + + # move results into upper and lower words + tmpZ:8 = zext( tmpH ); + tmpZ = ( tmpZ << 32 ) | zext( tmpL ); + + D = tmpZ; +} + + +# ================================================================= +# Page 568 + +# evfsctuf rT,rB +# ISA-cmt: evfsctuf - Vector Convert Floating-Point Single-Precision to Unsigned Fraction +# ISA-info: evfsctuf - Form "EVX" Page 568 Category "SP.FV" +# binutils: mytest.d: 218: 10 20 12 96 evfsctuf r1,r2 +:evfsctuf D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=662 +{ + # multiply by 0x0000 0001 0000 0000 to scale the fraction up to integer range + + # load fractional multiplier as a float + tmpM:8 = 0x0000000100000000; + tmpM = int2float( tmpM ); + setSPEFSCR_L( tmpM ); + + # load saturation limit as a float + tmpS:8 = 0x0000000100000000 - 1; + tmpS = int2float( tmpS ); + setSPEFSCR_L( tmpS ); + + # scale the saturation limit to a fractional float + tmpS = tmpS f/ tmpM; + setSPEFSCRDivFlags_L( tmpS, tmpM, tmpS ); + + # + # low section + # + # get B float up to 64 bit width + tmpE:4 = B:4; + tmpB:8 = float2float( tmpE ); + setSPEFSCR_L( tmpB ); + + # check if less than or equal to positive saturation limit + if ( tmpB f<= tmpS ) goto ; + + # set to saturation + tmpB = tmpS; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + # scale the fractional portion up to integer side of mantissa + tmpB = tmpB f* tmpM; + setSPEFSCRMulFlags_L( tmpB, tmpM, tmpB ); + + # truncate back to integer + tmpL:4 = trunc( tmpB ); + setSPEFSCR_L( tmpL ); + + setSummarySPEFSCR(); + + # + # high section + # + # get B float up to 64 bit width + tmpE = B(4); + tmpB = float2float( tmpE ); + setSPEFSCR_H( tmpB ); + + # check if less than or equal to positive saturation limit + if ( tmpB f<= tmpS ) goto ; + + # set to saturation + tmpB = tmpS; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + # scale the fractional portion up to integer side of mantissa + tmpB = tmpB f* tmpM; + setSPEFSCRMulFlags_H( tmpB, tmpM, tmpB ); + + # truncate back to integer + tmpH:4 = trunc( tmpB ); + setSPEFSCR_H( tmpH ); + + setSummarySPEFSCR(); + + # move results into upper and lower words + tmpZ:8 = zext( tmpH ); + tmpZ = ( tmpZ << 32 ) | zext( tmpL ); + + D = tmpZ; +} + + +# ================================================================= +# Page 567 + +# evfsctui rT,rB +# ISA-cmt: evfsctui - Vector Convert Floating-Point Single-Precision to Unsigned Integer +# ISA-info: evfsctui - Form "EVX" Page 567 Category "SP.FV" +# binutils: mytest.d: 210: 10 20 12 94 evfsctui r1,r2 +:evfsctui D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=660 +{ + # load saturation limit as a float + tmpS:8 = 0x00000000FFFFFFFF; + tmpS = int2float( tmpS ); + setSPEFSCR_L( tmpS ); + + # + # low section + # + tmpE:4 = B:4; + tmpB:8 = float2float( tmpE ); + + # limit to saturation + if ( tmpB f<= tmpS ) goto ; + tmpB = tmpS; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + # round back to integer + tmpL:4 = trunc(round( tmpB )); + setSPEFSCR_L( tmpL ); + + setSummarySPEFSCR(); + + # + # high section + # + tmpE = B(4); + tmpB = float2float( tmpE ); + + # limit to saturation + if ( tmpB f<= tmpS ) goto ; + tmpB = tmpS; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + # round back to integer + tmpH:4 = trunc(round( tmpB )); + setSPEFSCR_H( tmpH ); + + setSummarySPEFSCR(); + + # move results into upper and lower words + tmpZ:8 = zext( tmpH ); + tmpZ = ( tmpZ << 32 ) | zext( tmpL ); + + D = tmpZ; +} + + +# ================================================================= +# Page 567 + +# evfsctuiz rT,rB +# ISA-cmt: evfsctuiz - Vector Convert Floating-Point Single-Precision to Unsigned Integer with Round toward Zero +# ISA-info: evfsctuiz - Form "EVX" Page 567 Category "SP.FV" +# binutils: mytest.d: 220: 10 20 12 98 evfsctuiz r1,r2 +:evfsctuiz D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=664 +{ + # load saturation limit as a float + tmpS:8 = 0x00000000FFFFFFFF; + tmpS = int2float( tmpS ); + setSPEFSCR_L( tmpS ); + + # + # low section + # + tmpE:4 = B:4; + tmpB:8 = float2float( tmpE ); + + # limit to saturation + if ( tmpB f<= tmpS ) goto ; + tmpB = tmpS; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + tmpL:4 = trunc( tmpB ); + + setSummarySPEFSCR(); + + # + # high section + # + tmpE = B(4); + tmpB = float2float( tmpE ); + + # limit to saturation + if ( tmpB f<= tmpS ) goto ; + tmpB = tmpS; + spef_fx = 1; + spef_finxs = 1; + spef_fg = 1; + + + + tmpH:4 = trunc( tmpB ); + + setSummarySPEFSCR(); + + # move results into upper and lower words + tmpZ:8 = zext( tmpH ); + tmpZ = ( tmpZ << 32 ) | zext( tmpL ); + + D = tmpZ; +} + + +# ================================================================= +# Page 562 + +# evfsdiv rT,rA,rB +# ISA-cmt: evfsdiv - Vector Floating-Point Single-Precision Divide +# ISA-info: evfsdiv - Form "EVX" Page 562 Category "SP.FV" +# binutils: mytest.d: 1f0: 10 22 1a 89 evfsdiv r1,r2,r3 +:evfsdiv D,A,B is OP=4 & D & A & B & XOP_0_10=649 +{ + tmpAL:4 = A:4; + tmpAH:4 = A(4); + tmpBL:4 = B:4; + tmpBH:4 = B(4); + + tmpL:4 = tmpAL f/ tmpBL; + setSPEFSCRDivFlags_L( tmpAL, tmpBL, tmpL ); + + tmpH:4 = tmpAH f/ tmpBH; + setSPEFSCRDivFlags_H( tmpAH, tmpBH, tmpH ); + + # move results into upper and lower words + tmpZ:8 = zext( tmpH ); + tmpZ = ( tmpZ << 32 ) | zext( tmpL ); + + D = tmpZ; +} + + +# ================================================================= +# Page 562 + +# evfsmul rT,rA,rB +# ISA-cmt: evfsmul - Vector Floating-Point Single-Precision Multiply +# ISA-info: evfsmul - Form "EVX" Page 562 Category "SP.FV" +# binutils: mytest.d: 1ec: 10 22 1a 88 evfsmul r1,r2,r3 +:evfsmul D,A,B is OP=4 & D & A & B & XOP_0_10=648 +{ + tmpAL:4 = A:4; + tmpAH:4 = A(4); + tmpBL:4 = B:4; + tmpBH:4 = B(4); + + tmpL:4 = tmpAL f* tmpBL; + setSPEFSCRMulFlags_L( tmpAL, tmpBL, tmpL ); + + tmpH:4 = tmpAH f* tmpBH; + setSPEFSCRMulFlags_H( tmpAH, tmpBH, tmpH ); + + # move results into upper and lower words + tmpZ:8 = zext( tmpH ); + tmpZ = ( tmpZ << 32 ) | zext( tmpL ); + + D = tmpZ; +} + + +# ================================================================= +# Page 561 + +# evfsnabs rT,rA +# ISA-cmt: evfsnabs - Vector Floating-Point Single-Precision Negative Absolute Value +# ISA-info: evfsnabs - Form "EVX" Page 561 Category "SP.FV" +# binutils: mytest.d: 1e4: 10 22 02 85 evfsnabs r1,r2 +:evfsnabs D,A is OP=4 & D & A & BITS_11_15=0 & XOP_0_10=645 +{ + tmpAL:4 = A:4; + tmpAH:4 = A(4); + + tmpL:4 = f- ( abs( tmpAL ) ); + + tmpH:4 = f- ( abs( tmpAH ) ); + + # move results into upper and lower words + tmpZ:8 = zext( tmpH ); + tmpZ = ( tmpZ << 32 ) | zext( tmpL ); + + D = tmpZ; +} + + +# ================================================================= +# Page 561 + +# evfsneg rT,rA +# ISA-cmt: evfsneg - Vector Floating-Point Single-Precision Negate +# ISA-info: evfsneg - Form "EVX" Page 561 Category "SP.FV" +# binutils: mytest.d: 1e8: 10 22 02 86 evfsneg r1,r2 +:evfsneg D,A is OP=4 & D & A & BITS_11_15=0 & XOP_0_10=646 +{ + tmpAL:4 = A:4; + tmpAH:4 = A(4); + + tmpL:4 = f-( tmpAL ); + + tmpH:4 = f-( tmpAH ); + + # move results into upper and lower words + tmpZ:8 = zext( tmpH ); + tmpZ = ( tmpZ << 32 ) | zext( tmpL ); + + D = tmpZ; +} + + +# ================================================================= +# Page 562 + +# evfssub rT,rA,rB +# ISA-cmt: evfssub - Vector Floating-Point Single-Precision Subtract +# ISA-info: evfssub - Form "EVX" Page 562 Category "SP.FV" +# binutils: mytest.d: 1dc: 10 22 1a 81 evfssub r1,r2,r3 +:evfssub D,A,B is OP=4 & D & A & B & XOP_0_10=641 +{ + tmpAL:4 = A:4; + tmpAH:4 = A(4); + tmpBL:4 = B:4; + tmpBH:4 = B(4); + + tmpL:4 = tmpAL f- tmpBL; + setSPEFSCRSubFlags_L( tmpAL, tmpBL, tmpL ); + + tmpH:4 = tmpAH f- tmpBH; + setSPEFSCRSubFlags_H( tmpAH, tmpBH, tmpH ); + +} + + +# ================================================================= +# Page 565 + +# evfststeq CRFD,rA,rB +# ISA-cmt: evfststeq - Vector Floating-Point Single-Precision Test Equal +# ISA-info: evfststeq - Form "EVX" Page 565 Category "SP.FV" +# binutils: mytest.d: 230: 10 82 1a 9e evfststeq cr1,r2,r3 +:evfststeq CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=670 +{ + tmpA:4 = A:4; + tmpB:4 = B:4; + tmpC:4 = A(4); + tmpD:4 = B(4); + + tmpL:1 = tmpA f== tmpB; + tmpH:1 = tmpC f== tmpD; + + CRFD = (8 * tmpH ) + (4 * tmpL ) + (2 * (tmpH | tmpL) ) + (tmpH & tmpL); +} + + +# ================================================================= +# Page 564 + +# evfststgt CRFD,rA,rB +# ISA-cmt: evfststgt - Vector Floating-Point Single-Precision Test Greater Than +# ISA-info: evfststgt - Form "EVX" Page 564 Category "SP.FV" +# binutils: mytest.d: 228: 10 82 1a 9c evfststgt cr1,r2,r3 +:evfststgt CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=668 +{ + tmpA:4 = A:4; + tmpB:4 = B:4; + tmpC:4 = A(4); + tmpD:4 = B(4); + + tmpL:1 = tmpA f> tmpB; + tmpH:1 = tmpC f> tmpD; + + CRFD = (8 * tmpH ) + (4 * tmpL ) + (2 * (tmpH | tmpL) ) + (tmpH & tmpL); +} + + +# ================================================================= +# Page 565 + +# evfststlt CRFD,rA,rB +# ISA-cmt: evfststlt - Vector Floating-Point Single-Precision Test Less Than +# ISA-info: evfststlt - Form "EVX" Page 565 Category "SP.FV" +# binutils: mytest.d: 22c: 10 82 1a 9d evfststlt cr1,r2,r3 +:evfststlt CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=669 +{ + tmpA:4 = A:4; + tmpB:4 = B:4; + tmpC:4 = A(4); + tmpD:4 = B(4); + + tmpL:1 = tmpA f< tmpB; + tmpH:1 = tmpC f< tmpD; + + CRFD = (8 * tmpH ) + (4 * tmpL ) + (2 * (tmpH | tmpL) ) + (tmpH & tmpL); +} + + +# ================================================================= +# Page 915 + +# evlddepx rT,rA,rB +# Note: context is not supported +:evlddepx D,RA_OR_ZERO,B is OP=31 & D & RA_OR_ZERO & B & XOP_1_10=799 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + D = *:8(ea); +} + + + +# ================================================================= +# Page 519 + +# evlwhe RT,D(RA) +# evlwhe rT,rA,UI +:evlwhe D,EVUIMM_4_RAt is OP=4 & D & EVUIMM_4_RAt & RA_OR_ZERO & UI & XOP_0_10=785 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + (UI * 4); + + # move results into upper and lower words + tmpZ:8 = zext( *:2(ea + 2) ); + tmpZ = ( tmpZ << 32 ) | zext( *:2(ea) ); + + D = tmpZ; +} + + + +# ================================================================= +# Page 519 + +# evlwhex rT,rA,rB +# ISA-cmt: evlwhex - Vector Load Word into Two Halfwords Even Indexed +# ISA-info: evlwhex - Form "EVX" Page 519 Category "SP" +# binutils: mytest.d: 238: 10 22 1b 10 evlwhex r1,r2,r3 +:evlwhex D,RA_OR_ZERO,B is OP=4 & D & RA_OR_ZERO & B & XOP_0_10=784 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + + # move results into upper and lower words + tmpZ:8 = zext( *:2(ea + 2) ); + tmpZ = ( tmpZ << 32 ) | zext( *:2(ea) ); + + D = tmpZ; +} + + + +# ================================================================= +# Page 521 + +# evlwwsplat RT,D(RA) +# evlwwsplat rT,rA,UI +# ISA-cmt: evlwwsplat - Vector Load Word into Word and Splat +# ISA-info: evlwwsplat - Form "EVX" Page 521 Category "SP" +# binutils: NO-EXAMPLE - evlwwsplat +# collides with maclhwu +:evlwwsplat D,EVUIMM_4_RAt is OP=4 & D & RA_OR_ZERO & EVUIMM_4_RAt & UI & XOP_0_10=793 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + (UI * 4); + + # move results into upper and lower words + tmpZ:8 = zext( *:4(ea) ); + tmpZ = ( tmpZ << 32 ) | zext( *:4(ea) ); + + D = tmpZ; +} + + + +# ================================================================= +# Page 521 + +# evlwwsplatx rT,rA,rB +# ISA-cmt: evlwwsplatx - Vector Load Word into Word and Splat Indexed +# ISA-info: evlwwsplatx - Form "EVX" Page 521 Category "SP" +# binutils: mytest.d: 23c: 10 22 1b 18 evlwwsplatx r1,r2,r3 +# collides with maclhwu +:evlwwsplatx D,RA_OR_ZERO,B is OP=4 & D & RA_OR_ZERO & B & XOP_0_10=792 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + + # move results into upper and lower words + tmpZ:8 = zext( *:4(ea) ); + tmpZ = ( tmpZ << 32 ) | zext( *:4(ea) ); + + D = tmpZ; +} + + +# ================================================================= +# Page 541 + +# evmwlsmiaaw rT,rA,rB +# ISA-cmt: evmwlsmiaaw - Vector Multiply Word Low Signed +# ISA-info: evmwlsmiaaw - Form "EVX" Page 541 Category "SP" +# binutils: mytest.d: 248: 10 22 1d 49 evmwlsmiaaw r1,r2,r3 +:evmwlsmiaaw D,A,B is OP=4 & D & A & B & XOP_0_10=1353 +{ + tmpACCL:4 = ACC:4; + tmpACCH:4 = ACC(4); + + tmpAL:8 = zext( A:4 ); + tmp:4 = A(4); + tmpAH:8 = zext( tmp ); + tmpBL:8 = zext( B:4 ); + tmp = B(4); + tmpBH:8 = zext( tmp ); + + temp:8 = tmpAH * tmpBH; + tmpD:4 = tmpACCH + temp:4; + D = ( zext( tmpD ) ) << 32; + temp = tmpAL * tmpBL; + tmpDL:4 = tmpACCL + temp:4; + D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpDL ); + ACC = D; +} + + +# ================================================================= +# Page 541 + +# evmwlsmianw rT,rA,rB +# ISA-cmt: evmwlsmianw - Vector Multiply Word Low Signed +# ISA-info: evmwlsmianw - Form "EVX" Page 541 Category "SP" +# binutils: mytest.d: 254: 10 22 1d c9 evmwlsmianw r1,r2,r3 +:evmwlsmianw D,A,B is OP=4 & D & A & B & XOP_0_10=1481 +{ + tmpACCL:4 = ACC:4; + tmpACCH:4 = ACC(4); + + tmpAL:8 = zext( A:4 ); + tmp:4 = A(4); + tmpAH:8 = zext( tmp ); + tmpBL:8 = zext( B:4 ); + tmp = B(4); + tmpBH:8 = zext( tmp ); + + temp:8 = tmpAH * tmpBH; + tmpD:4 = tmpACCH - temp:4; + D = ( zext( tmpD ) ) << 32; + temp = tmpAL * tmpBL; + tmpDL:4 = tmpACCL - temp:4; + D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpDL ); + ACC = D; +} + + +# ================================================================= +# Page 541 + +# evmwlssianw rT,rA,rB +# ISA-cmt: evmwlssianw - Vector Multiply Word Low Signed +# ISA-info: evmwlssianw - Form "EVX" Page 541 Category "SP" +# binutils: mytest.d: 250: 10 22 1d c1 evmwlssianw r1,r2,r3 +:evmwlssianw D,A,B is OP=4 & D & A & B & XOP_0_10=1473 +{ + tmpACCL:4 = ACC:4; + tmpACCH:4 = ACC(4); + + tmpAL:8 = zext( A:4 ); + tmp:4 = A(4); + tmpAH:8 = zext( tmp ); + tmpBL:8 = zext( B:4 ); + tmp = B(4); + tmpBH:8 = zext( tmp ); + + temp:8 = tmpAH * tmpBH; + temp = sext( tmpACCH ) - sext( temp:4 ); + tmpOVH:1 = temp[32,1] ^ temp[31,1]; + + # check for saturation + if ( tmpOVH == 0 ) goto ; + + if ( temp[32,1] == 1 ) goto ; + D = ( D & 0x00000000FFFFFFFF ) | 0x7FFFFFFF00000000; + goto ; + + + D = ( D & 0x00000000FFFFFFFF ) | 0x8000000000000000; + goto ; + + + D = ( D & 0x00000000FFFFFFFF ) | ( zext( temp:4 ) << 32 ); + + + + + temp = tmpAL * tmpBL; + temp = sext( tmpACCL ) - sext( temp:4 ); + tmpOVL:1 = temp[32,1] ^ temp[31,1]; + + # check for saturation + if ( tmpOVL == 0 ) goto ; + + if ( temp[32,1] == 1 ) goto ; + D = ( D & 0xFFFFFFFF00000000 ) | 0x000000007FFFFFFF; + goto ; + + + D = ( D & 0xFFFFFFFF00000000 ) | 0x0000000080000000; + goto ; + + + D = ( D & 0xFFFFFFFF00000000 ) | zext( temp:4 ); + + + + + ACC = D; + + spef_ovh = tmpOVH; + spef_ov = tmpOVL; + spef_sovh = spef_sovh | tmpOVH; + spef_sov = spef_sov | tmpOVL; +} + + + +# ================================================================= +# Page 544 + +# evmwsmi rT,rA,rB +# ISA-cmt: evmwsmi - Vector Multiply Word Signed +# ISA-info: evmwsmi - Form "EVX" Page 544 Category "SP" +# binutils: mytest.d: 244: 10 22 1c 59 evmwsmi r1,r2,r3 +# collides with machhwo +:evmwsmi D,A,B is OP=4 & D & A & B & XOP_0_10=1113 +{ + tmpAL:8 = zext( A:4 ); + tmpBL:8 = zext( B:4 ); + + D = tmpAL * tmpBL; +} + + + +# ================================================================= +# Page 544 + +# evmwsmiaa rT,rA,rB +# ISA-cmt: evmwsmiaa - Vector Multiply Word Signed +# ISA-info: evmwsmiaa - Form "EVX" Page 544 Category "SP" +# binutils: mytest.d: 24c: 10 22 1d 59 evmwsmiaa r1,r2,r3 +# collides with macchwo. +:evmwsmiaa D,A,B is OP=4 & D & A & B & XOP_0_10=1369 +{ + tmpAL:8 = zext( A:4 ); + tmpBL:8 = zext( B:4 ); + + temp:8 = tmpAL * tmpBL; + D = ACC + temp; + ACC = D; +} + + + + +# ================================================================= +# Page 544 + +# evmwsmian rT,rA,rB +# ISA-cmt: evmwsmian - Vector Multiply Word Signed +# ISA-info: evmwsmian - Form "EVX" Page 544 Category "SP" +# binutils: mytest.d: 25c: 10 22 1d d9 evmwsmian r1,r2,r3 +# collides with macchwso. +:evmwsmian D,A,B is OP=4 & D & A & B & XOP_0_10=1497 +{ + tmpAL:8 = zext( A:4 ); + tmpBL:8 = zext( B:4 ); + + temp:8 = tmpAL * tmpBL; + D = ACC - temp; + ACC = D; +} + + + +# ================================================================= +# Page 546 + +# evmwumi rT,rA,rB +# ISA-cmt: evmwumi - Vector Multiply Word Unsigned +# ISA-info: evmwumi - Form "EVX" Page 546 Category "SP" +# binutils: mytest.d: 240: 10 22 1c 58 evmwumi r1,r2,r3 +# collides with machhwo +:evmwumi D,A,B is OP=4 & D & A & B & XOP_0_10=1112 +{ + tmpAL:8 = zext( A:4 ); + tmpBL:8 = zext( B:4 ); + + D = tmpAL * tmpBL; +} + + + +# ================================================================= +# Page 547 + +# evmwumian rT,rA,rB +# ISA-cmt: evmwumian - Vector Multiply Word Unsigned +# ISA-info: evmwumian - Form "EVX" Page 547 Category "SP" +# binutils: mytest.d: 258: 10 22 1d d8 evmwumian r1,r2,r3 +# collides with macchwso +:evmwumian D,A,B is OP=4 & D & A & B & XOP_0_10=1496 +{ + tmpAL:8 = zext( A:4 ); + tmpBL:8 = zext( B:4 ); + + temp:8 = tmpAL * tmpBL; + D = ACC - temp; + ACC = D; +} + + +# ================================================================= +# Page 549 + +# evsel rT,rA,rB +# ISA-cmt: evsel - Vector Select +# ISA-info: evsel - Form "EVS" Page 549 Category "SP" +# binutils: mytest.d: 1d4: 10 22 1a 7c evsel r1,r2,r3,cr4 +:evsel D,A,B,BFA is OP=4 & D & A & B & XOP_3_10=79 & BFA +{ + + tmpAL:8 = zext( A:4 ); + tmp:4 = A(4); + tmpAH:8 = zext( tmp ); + tmpBL:8 = zext( B:4 ); + tmp = B(4); + tmpBH:8 = zext( tmp ); + + tmpBFA:1 = BFA; + + if ( tmpBFA[3,1] == 0 ) goto ; + D = ( D & 0x00000000FFFFFFFF ) | ( tmpAH << 32 ); + goto ; + + + D = ( D & 0x00000000FFFFFFFF ) | ( tmpBH << 32 ); + + + + if ( tmpBFA[2,1] == 0 ) goto ; + D = ( D & 0xFFFFFFFF00000000 ) | tmpAL; + goto ; + + + D = ( D & 0xFFFFFFFF00000000 ) | tmpBL; + + +} + + +# ================================================================= +# Page 915 + +# evstddepx rT,rA,rB +# Note: context is not supported +:evstddepx D,RA_OR_ZERO,B is OP=31 & D & RA_OR_ZERO & B & XOP_1_10=927 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + *:8(ea) = D; +} + + + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/Scalar_SPFP.sinc b/python/icicle/Ghidra/Processors/PowerPC/data/languages/Scalar_SPFP.sinc new file mode 100644 index 0000000..f1c10de --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/Scalar_SPFP.sinc @@ -0,0 +1,472 @@ +# Based on "EREF: A Reference for Freescale Book E and e500 Core" document version 01/2004 Rev 2.0 +# Instructions that are specific to the (PowerPC) e500 core are implemented as auxiliary processing units (APUs) +# Embedded Vector and Scalar Single-Precision Floating-Point APUs (SPFP APU) + +# There are three versions of e500 core, namely e500v1, the e500v2, and the e500mc. +# A 64-bit evolution of the e500mc core is called e5500 core. +# All PowerQUICC 85xx devices are based on e500v1 or e500v2 cores. + + +# ================================================================= +# Page 408 + +# efsabs rT,rA 010 1100 0100 +#define pcodeop FloatingPointAbsoluteValue; +:efsabs D,A is OP=4 & D & A & XOP_0_10=0x2C4 & BITS_11_15=0 +{ + # assign to lower word of D + D = ( D & 0xFFFFFFFF00000000 ) | zext( abs( A:4 ) ); +} + +# efsadd rT,rA,rB 010 1100 0000 +#define pcodeop FloatingPointAdd; +:efsadd D,A,B is OP=4 & D & A & B & XOP_0_10=0x2C0 +{ + # assign to lower word of D + D = ( D & 0xFFFFFFFF00000000 ) | zext( A:4 f+ B:4 ); + setFPAddFlags( A:4, B:4, D:4 ); +} + +# ================================================================= +# Page 410 + +# efscfsf rT,rB 010 1101 0011 +#define pcodeop ConvertFloatingPointFromSignedFraction; +:efscfsf D,B is OP=4 & D & B & XOP_0_10=0x2D3 & BITS_16_20=0 +{ + # load fractional divisor as a float + tmpA:4 = 0x80000000; + tmpA = int2float( tmpA ); + setFPRF( tmpA ); + + # check if negative + if ( ( B:4 & 0x80000000 ) != 0 ) goto ; + + # float the fractional portion of register B + tmpB:4 = int2float( B:4 ); + setFPRF( tmpB ); + tmpB = tmpB f/ tmpA; + setFPDivFlags( tmpB, tmpA, tmpB ); + + goto ; + + + + # float the fractional portion of register B, 2's complement negate + tmpB = int2float( -( B:4 ) ); + setFPRF( tmpB ); + tmpB = tmpB f/ tmpA; + setFPDivFlags( tmpB, tmpA, tmpB ); + + # negate the float + tmpB = f-( tmpB ); + setFPRF( tmpB ); + + + + setSummaryFPSCR(); + + # assign to lower word of D + D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpB ); +} + +# efscfsi rT,rB 010 1101 0001 +#define pcodeop ConvertFloatingPointFromSignedInteger; +:efscfsi D,B is OP=4 & D & B & XOP_0_10=0x2D1 & BITS_16_20=0 +{ + # check if negative + if ( ( B:4 & 0x80000000 ) != 0 ) goto ; + + # float the integer portion of register B + tmpB:4 = int2float( B:4 ); + setFPRF( tmpB ); + + goto ; + + + + # float the integer portion of register B, 2's complement negate + tmpB = int2float( -( B:4 ) ); + setFPRF( tmpB ); + + # negate the float + tmpB = f-( tmpB ); + setFPRF( tmpB ); + + + + setSummaryFPSCR(); + + # assign to lower word of D + D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpB ); +} + +# efscfuf rT,rB 010 1101 0010 +define pcodeop ConvertFloatingPointFromUnsignedFraction; +:efscfuf D,B is OP=4 & D & B & XOP_0_10=0x2D2 & BITS_16_20=0 +{ + # load fractional divisor as a float + tmpA:8 = 0x0000000100000000; + tmpA = int2float( tmpA ); + setFPRF( tmpA ); + + # float the fractional portion of register B + tmpB:8 = int2float( B:4 ); + setFPRF( tmpB ); + tmpB = tmpB f/ tmpA; + setFPDivFlags( tmpB, tmpA, tmpB ); + + tmpC:4 = float2float( tmpB ); + setFPRF( tmpC ); + + setSummaryFPSCR(); + + # assign to lower word of D + D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpC ); +} + +# rT,rB 010 1101 0000 +#define pcodeop ConvertFloatingPointFromUnsignedInteger; +:efscfui D,B is OP=4 & D & B & XOP_0_10=0x2D0 & BITS_16_20=0 +{ + tmp:4 = int2float( B:4 ); + setFPRF( tmp ); + + # assign to lower word of D + D = ( D & 0xFFFFFFFF00000000 ) | zext( tmp ); + setSummaryFPSCR(); +} + +# efscmpeq CRFD,rA,rB 010 1100 1110 +#define pcodeop FloatingPointCompareEqual; +:efscmpeq CRFD,A,B is OP=4 & CRFD & A & B & XOP_0_10=0x2CE & BITS_21_22=0 +{ + CRFD[2,1] = A:4 f== B:4; +} + +# ================================================================= +# Page 415 + +# efscmpgt CRFD,rA,rB 010 1100 1100 +#define pcodeop FloatingPointCompareGreaterThan; +:efscmpgt CRFD,A,B is OP=4 & CRFD & A & B & XOP_0_10=0x2CC & BITS_21_22=0 +{ + CRFD[2,1] = A:4 f> B:4; +} + +# efscmplt CRFD,rA,rB 010 1100 1101 +#define pcodeop FloatingPointCompareLessThan; +:efscmplt CRFD,A,B is OP=4 & CRFD & A & B & XOP_0_10=0x2CD & BITS_21_22=0 +{ + CRFD[2,1] = A:4 f< B:4; +} + +# efsctsf rT,rB 010 1101 0111 +#define pcodeop ConvertFloatingPointToSignedFraction; +:efsctsf D,B is OP=4 & D & B & XOP_0_10=0x2D7 & BITS_16_20=0 +{ + # multiply by 0x0000 0000 8000 0000 to scale the fraction up to integer range + + # load fractional multiplier as a float + tmpM:8 = 0x0000000080000000; + tmpM = int2float( tmpM ); + setFPRF( tmpM ); + + # load saturation limit as a float + tmpL:8 = 0x0000000080000000 - 1; + tmpL = int2float( tmpL ); + setFPRF( tmpL ); + + # scale the saturation limit to a fractional float + tmpL = tmpL f/ tmpM; + setFPDivFlags( tmpL, tmpM, tmpL ); + + # get B float up to 64 bit width + tmpB:8 = float2float( B:4 ); + setFPRF( tmpB ); + + # check if less than or equal to positive saturation limit + if ( tmpB f<= tmpL ) goto ; + + # set to positive saturation + tmpB = tmpL; + + goto ; + + + + # check if greater than or equal to negative saturation limit + tmpL = f-( tmpL ); + if ( tmpB f>= tmpL ) goto ; + + # set to negative saturation + tmpB = tmpL; + + + + # scale the fractional portion up to integer side of mantissa + tmpB = tmpB f* tmpM; + setFPMulFlags( tmpB, tmpM, tmpB ); + + # truncate back to signed fraction format + tmpC:4 = trunc( tmpB ); + setFPRF( tmpB ); + + setSummaryFPSCR(); + + # assign to lower word of D + D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpC ); +} + + +# efsctsi rT,rB 010 1101 0101 +#define pcodeop ConvertFloatingPointToSignedInteger; +:efsctsi D,B is OP=4 & D & B & XOP_0_10=0x2D5 & BITS_16_20=0 +{ + # create zero float constant + tmpA:4 = 0; + tmpA = int2float( tmpA ); + + # check if negative + if ( B:4 f< tmpA ) goto ; + + tmpB:8 = trunc(round( B:4 )); + setFPRF( tmpB ); + + # limit to positive saturation + if ( tmpB <= 0x000000007FFFFFFF ) goto ; + tmpB = 0x000000007FFFFFFF; + + + + goto ; + + + + # negate the float + tmpB = trunc(round( f-( B:4 ) )); + setFPRF( tmpB ); + + # limit to negative saturation + if ( tmpB <= 0x0000000080000000 ) goto ; + tmpB = 0x0000000080000000; + + + + # negate the signed int + tmpB = -( tmpB ); + + + + setSummaryFPSCR(); + + # assign to lower word of D + D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpB:4 ); +} + +# efsctsiz rT,rB 010 1101 1010 +#define pcodeop ConvertFloatingPointToSignedIntegerWithRoundTowardZero; +:efsctsiz D,B is OP=4 & D & B & XOP_0_10=0x2DA & BITS_16_20=0 +{ + # create zero float constant + tmpA:4 = 0; + tmpA = int2float( tmpA ); + + # check if negative + if ( B:4 f< tmpA ) goto ; + + tmpB:8 = trunc( B:4 ); + setFPRF( tmpB ); + + # limit to saturation + if ( tmpB <= 0x000000007FFFFFFF ) goto ; + tmpB = 0x000000007FFFFFFF; + + + + goto ; + + + + # negate the float + tmpB = trunc( f-( B:4 ) ); + setFPRF( tmpB ); + + # limit to saturation + if ( tmpB <= 0x0000000080000000 ) goto ; + tmpB = 0x0000000080000000; + + + + # negate the signed int + tmpB = -( tmpB ); + + + + setSummaryFPSCR(); + + # assign to lower word of D + D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpB:4 ); +} + +# ================================================================= +# Page 420 + +# efsctuf rT,rB 010 1101 0110 +#define pcodeop ConvertFloatingPointToUnsignedFraction; +:efsctuf D,B is OP=4 & D & B & XOP_0_10=0x2D6 & BITS_16_20=0 +{ + # multiply by 0x0000 0001 0000 0000 to scale the fraction up to integer range + + # load fractional multiplier as a float + tmpM:8 = 0x0000000100000000; + tmpM = int2float( tmpM ); + setFPRF( tmpM ); + + # load saturation limit as a float + tmpL:8 = 0x0000000100000000 - 1; + tmpL = int2float( tmpL ); + setFPRF( tmpL ); + + # scale the saturation limit to a fractional float + tmpL = tmpL f/ tmpM; + setFPDivFlags( tmpL, tmpM, tmpL ); + + # get B float up to 64 bit width + tmpB:8 = float2float( B:4 ); + setFPRF( tmpB ); + + # check if less than or equal to positive saturation limit + if ( tmpB f<= tmpL ) goto ; + + # set to saturation + tmpB = tmpL; + + + + # scale the fractional portion up to integer side of mantissa + tmpB = tmpB f* tmpM; + setFPMulFlags( tmpB, tmpM, tmpB ); + + # truncate back to integer + tmpC:4 = trunc( tmpB ); + setFPRF( tmpC ); + + setSummaryFPSCR(); + + # assign to lower word of D + D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpC ); +} + +# efsctui rT,rB 010 1101 0100 +#define pcodeop ConvertFloatingPointToUnsignedInteger; +:efsctui D,B is OP=4 & D & B & XOP_0_10=0x2D4 & BITS_16_20=0 +{ + tmpB:8 = trunc(round( B:4 )); + setFPRF( tmpB ); + + # limit to saturation + if ( tmpB <= 0x000000007FFFFFFF ) goto ; + tmpB = 0x000000007FFFFFFF; + + + + setSummaryFPSCR(); + + # assign to lower word of D + D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpB:4 ); +} + +# efsctuiz rT,rB 010 1101 1000 +#define pcodeop ConvertFloatingPointToUnsignedIntegerWithRoundTowardZero; +:efsctuiz D,B is OP=4 & D & B & XOP_0_10=0x2D8 & BITS_16_20=0 +{ + tmpB:8 = trunc( B:4 ); + setFPRF( tmpB ); + + # limit to saturation + if ( tmpB <= 0x000000007FFFFFFF ) goto ; + tmpB = 0x000000007FFFFFFF; + + + + setSummaryFPSCR(); + + # assign to lower word of D + D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpB:4 ); +} + +# efsdiv rT,rA,rB 010 1100 1001 +#define pcodeop FloatingPointDivide; +:efsdiv D,A,B is OP=4 & D & A & B & XOP_0_10=0x2C9 +{ + # assign to lower word of D + D = ( D & 0xFFFFFFFF00000000 ) | zext( A:4 f/ B:4 ); + setFPDivFlags( A:4, B:4, D:4 ); +} + +# efsmul rT,rA,rB 010 1100 1000 +#define pcodeop FloatingPointMultiply; +:efsmul D,A,B is OP=4 & D & A & B & XOP_0_10=0x2C8 +{ + # assign to lower word of D + D = ( D & 0xFFFFFFFF00000000 ) | zext( A:4 f* B:4 ); + setFPMulFlags( A:4, B:4, D:4 ); +} + +# ================================================================= +# Page 425 + +# efsnabs rT,rA 010 1100 0101 +#define pcodeop FloatingPointNegativeAbsoluteValue; +:efsnabs D,A is OP=4 & D & A & XOP_0_10=0x2C5 & BITS_11_15=0 +{ + # assign to lower word of D + D = ( D & 0xFFFFFFFF00000000 ) | zext( f- ( abs( A:4 ) ) ); + setFPRF( D:4 ); + setSummaryFPSCR(); +} + +# efsneg rT,rA 010 1100 0110 +#define pcodeop FloatingPointNegate; +:efsneg D,A is OP=4 & D & A & XOP_0_10=0x2C6 & BITS_11_15=0 +{ + # assign to lower word of D + D = ( D & 0xFFFFFFFF00000000 ) | zext( f-( A:4 ) ); + setFPRF( D:4 ); + setSummaryFPSCR(); +} + +# efssub rT,rA,rB 010 1100 0001 +#define pcodeop FloatingPointSubtract; +:efssub D,A,B is OP=4 & D & A & B & XOP_0_10=0x2C1 +{ + # assign to lower word of D + D = ( D & 0xFFFFFFFF00000000 ) | zext( A:4 f- B:4 ); + setFPSubFlags( A:4, B:4, D:4 ); + setSummaryFPSCR(); +} + +# efststeq CRFD,rA,rB 010 1101 1110 +#define pcodeop FloatingPointTestEqual; +:efststeq CRFD,A,B is OP=4 & CRFD & A & B & XOP_0_10=0x2DE & BITS_21_22=0 +{ + CRFD[2,1] = A:4 f== B:4; +} + +# efststgt CRFD,rA,rB 010 1101 1100 +#define pcodeop FloatingPointTestGreaterThan; +:efststgt CRFD,A,B is OP=4 & CRFD & A & B & XOP_0_10=0x2DC & BITS_21_22=0 +{ + CRFD[2,1] = A:4 f> B:4; +} + +# ================================================================= +# Page 430 + +# efststlt CRFD,rA,rB 010 1101 1101 +#define pcodeop FloatingPointTestLessThan; +:efststlt CRFD,A,B is OP=4 & CRFD & A & B & XOP_0_10=0x2DD & BITS_21_22=0 +{ + CRFD[2,1] = A:4 f< B:4; +} diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/altivec.sinc b/python/icicle/Ghidra/Processors/PowerPC/data/languages/altivec.sinc new file mode 100644 index 0000000..7f4b339 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/altivec.sinc @@ -0,0 +1,1852 @@ +# altivec pcodes are stubbed out with pseudocode calls +define pcodeop dataStreamStop; +define pcodeop dataStreamStopAll; +define pcodeop dataStreamTouch; +define pcodeop dataStreamTouchSoon; +define pcodeop dataStreamTouchForStore; +define pcodeop dataStreamTouchForStoreTransient; +define pcodeop loadVectorElementByteIndexed; +define pcodeop loadVectorElementHalfWordIndexed; +define pcodeop loadVectorElementWordIndexed; +define pcodeop loadVectorForShiftLeft; +define pcodeop loadVectorForShiftRight; +define pcodeop loadVectorIndexed; +define pcodeop loadVectorIndexedLRU; +define pcodeop moveFromVectorStatusAndControlRegister; +define pcodeop moveToVectorStatusAndControlRegister; +define pcodeop storeVectorElementByteIndexed; +define pcodeop storeVectorElementHalfWordIndexed; +define pcodeop storeVectorElementWordIndexed; +define pcodeop storeVectorIndexed; +define pcodeop storeVectorIndexedLRU; +define pcodeop vectorAddCarryoutUnsignedWord; +define pcodeop vectorAddFloatingPoint; +define pcodeop vectorAddSignedByteSaturate; +define pcodeop vectorAddSignedHalfWordSaturate; +define pcodeop vectorAddSignedWordSaturate; +define pcodeop vectorAddUnsignedByteSaturate; +define pcodeop vectorAddUnsignedHalfWordModulo; +define pcodeop vectorAddUnsignedHalfWordSaturate; +define pcodeop vectorAddUnsignedWordSaturate; +define pcodeop vectorLogicalAnd; +define pcodeop vectorLogicalAndWithComplement; +define pcodeop vectorAverageSignedByte; +define pcodeop vectorAverageSignedHalfWord; +define pcodeop vectorAverageSignedWord; +define pcodeop vectorAverageUnsignedByte; +define pcodeop vectorAverageUnsignedHalfWord; +define pcodeop vectorAverageUnsignedWord; +define pcodeop vectorConvertFromSignedFixedPointWord; +define pcodeop vectorConvertFromUnsignedFixedPointWord; +define pcodeop vectorCompareBoundsFloatingPoint; +define pcodeop vectorCompareEqualToFloatingPoint; +define pcodeop vectorCompareEqualToUnsignedByte; +define pcodeop vectorCompareEqualToUnsignedHalfWord; +define pcodeop vectorCompareEqualToUnsignedWord; +define pcodeop vectorCompareGreaterThanOrEqualToFloatingPoint; +define pcodeop vectorCompareGreaterThanFloatingPoint; +define pcodeop vectorCompareGreaterThanSignedByte; +define pcodeop vectorCompareGreaterThanConditionRegisterSignedHalfWord; +define pcodeop vectorCompareGreaterThanSignedWord; +define pcodeop vectorCompareGreaterThanUnsignedByte; +define pcodeop vectorCompareGreaterThanUnsignedHalfWord; +define pcodeop vectorCompareGreaterThanUnsignedWord; +define pcodeop vectorConvertToSignedFixedPointWordSaturate; +define pcodeop vectorConvertToUnsignedFixedPointWordSaturate; +define pcodeop vector2RaisedToTheExponentEstimateFloatingPoint; +define pcodeop vectorLog2EstimateFloatingPoint; +define pcodeop vectorMultiplyAddFloatingPoint; +define pcodeop vectorMaximumFloatingPoint; +define pcodeop vectorMaximumSignedByte; +define pcodeop vectorMaximumSignedHalfWord; +define pcodeop vectorMaximumSignedWord; +define pcodeop vectorMaximumUnsignedByte; +define pcodeop vectorMaximumUnsignedHalfWord; +define pcodeop vectorMaximumUnsignedWord; +define pcodeop vectorMultiplyHighAndAddSignedHalfWordSaturate; +define pcodeop vectorMultiplyHighRoundAndAddSignedHalfWordSaturate; +define pcodeop vectorMinimumFloatingPoint; +define pcodeop vectorMinimumSignedByte; +define pcodeop vectorMinimumSignedHalfWord; +define pcodeop vectorMinimumSignedWord; +define pcodeop vectorMinimumUnsignedByte; +define pcodeop vectorMinimumUnsignedHalfWord; +define pcodeop vectorMinimumUnsignedWord; +define pcodeop vectorMultiplyLowAndAddUnsignedHalfWordModulo; +define pcodeop vectorMergeHighByte; +define pcodeop vectorMergeHighHalfWord; +define pcodeop vectorMergeHighWord; +define pcodeop vectorMergeLowByte; +define pcodeop vectorMergeLowHalfWord; +define pcodeop vectorMergeLowWord; +define pcodeop vectorMultiplySumMixedSignByteModulo; +define pcodeop vectorMultiplySumSignedHalfWordModulo; +define pcodeop vectorMultiplySumSignedHalfWordSaturate; +define pcodeop vectorMultiplySumUnsignedByteModulo; +define pcodeop vectorMultiplySumUnsignedHalfWordModulo; +define pcodeop vectorMultiplySumUnsignedHalfWordSaturate; +define pcodeop vectorMultiplyEvenSignedByte; +define pcodeop vectorMultiplyEvenSignedHalfWord; +define pcodeop vectorMultiplyEvenUnsignedByte; +define pcodeop vectorMultiplyEvenUnsignedHalfWord; +define pcodeop vectorMultiplyOddSignedByte; +define pcodeop vectorMultiplyOddSignedHalfWord; +define pcodeop vectorMultiplyOddUnsignedByte; +define pcodeop vectorMultiplyOddUnsignedHalfWord; +define pcodeop vectorNegativeMultiplySubtractFloatingPoint; +define pcodeop vectorLogicalNOR; +define pcodeop vectorLogicalOR; +define pcodeop vectorPackPixel32; +define pcodeop vectorPackSignedHalfWordSignedSaturate; +define pcodeop vectorPackSignedHalfWordUnsignedSaturate; +define pcodeop vectorPackSignedWordSignedSaturate; +define pcodeop vectorPackSignedWordUnsignedSaturate; +define pcodeop vectorPackUnsignedHalfWordUnsignedModulo; +define pcodeop vectorPackUnsignedHalfWordUnsignedSaturate; +define pcodeop vectorPackUnsignedWordUnsignedModulo; +define pcodeop vectorPackUnsignedWordUnsignedSaturate; +define pcodeop vectorReciprocalEstimateFloatingPoint; +define pcodeop vectorRoundToFloatingPointIntegerTowardMinusInfinity; +define pcodeop vectorRoundToFloatingPointIntegerNearest; +define pcodeop vectorRoundToFloatingPointIntegerTowardPluInfinity; +define pcodeop vectorRoundToFloatingPointIntegerTowardZero; +define pcodeop vectorRotateLeftIntegerByte; +define pcodeop vectorRotateLeftIntegerHalfWord; +define pcodeop vectorRotateLeftIntegerWord; +define pcodeop vectorReciprocalSquareRootEstimateFloatingPoint; +define pcodeop vectorConditionalSelect; +define pcodeop vectorShiftLeft; +define pcodeop vectorShiftLeftIntegerByte; +define pcodeop vectorShiftLeftDoubleByOctetImmediate; +define pcodeop vectorShiftLeftIntegerHalfWord; +define pcodeop vectorShiftLeftByOctet; +define pcodeop vectorShiftLeftIntegerWord; +define pcodeop vectorSplatByte; +define pcodeop vectorSplatHalfWord; +define pcodeop vectorSplatImmediateSignedByte; +define pcodeop vectorSplatImmediateSignedHalfWord; +define pcodeop vectorSplatImmediateSignedWord; +define pcodeop vectorSplatWord; +define pcodeop vectorShiftRight; +define pcodeop vectorShiftRightAlgebraicByte; +define pcodeop vectorShiftRightAlgebraicHalfWord; +define pcodeop vectorShiftRightAlgebraicWord; +define pcodeop vectorShiftRightByte; +define pcodeop vectorShiftRightHalfWord; +define pcodeop vectorShiftRightByOctet; +define pcodeop vectorShiftRightWord; +define pcodeop vectorSubtractCarryoutUnsignedWord; +define pcodeop vectorSubtractFloatingPoint; +define pcodeop vectorSubtractSignedByteSaturate; +define pcodeop vectorSubtractSignedHalfWordSaturate; +define pcodeop vectorSubtractSignedWordSaturate; +define pcodeop vectorSubtractUnsignedByteModulo; +define pcodeop vectorSubtractUnsignedByteSaturate; +define pcodeop vectorSubtractUnsignedHalfWordSaturate; +define pcodeop vectorSubtractUnsignedWordModulo; +define pcodeop vectorSubtractUnsignedWordSaturate; +define pcodeop vectorSumAcrossSignedWordSaturate; +define pcodeop vectorSumAcrossPartialSignedWordSaturate; +define pcodeop vectorSumAcrossPartialSignedByteSaturate; +define pcodeop vectorSumAcrossPartialSignedHalfWordSaturate; +define pcodeop vectorSumAcrossPartialUnsignedByteSaturate; +define pcodeop vectorUnpackHighPixel16; +define pcodeop vectorUnpackHighSignedByte; +define pcodeop vectorUnpackHighSignedHalfWord; +define pcodeop vectorUnpackLowPixel16; +define pcodeop vectorUnpackLowSignedByte; +define pcodeop vectorUnpackLowSignedHalfWord; + +# dss +:dss STRM is $(NOTVLE) & OP=31 & BIT_25=0 & BITS_23_24=0 & STRM & BITS_16_20=0 & BITS_11_15=0 & XOP_1_10=822 & Rc=0 +{ + dataStreamStop(STRM:1); +} + +# dssall +:dssall STRM is $(NOTVLE) & OP=31 & BIT_25=1 & BITS_23_24=0 & STRM & BITS_16_20=0 & BITS_11_15=0 & XOP_1_10=822 & Rc=0 +{ + dataStreamStopAll(STRM:1); +} + +:dst A,B,STRM is $(NOTVLE) & OP=31 & BIT_25=0 & BITS_23_24=0 & STRM & A & B & XOP_1_10=342 & Rc=0 +{ + dataStreamTouch(A,B,STRM:1); +} + +:dstt A,B,STRM is $(NOTVLE) & OP=31 & BIT_25=1 & BITS_23_24=0 & STRM & A & B & XOP_1_10=342 & Rc=0 +{ + dataStreamTouchSoon(A,B,STRM:1); +} + +:dstst A,B,STRM is $(NOTVLE) & OP=31 & BIT_25=0 & BITS_23_24=0 & STRM & A & B & XOP_1_10=374 & Rc=0 +{ + dataStreamTouchForStore(A,B,STRM:1); +} + +:dststt A,B,STRM is $(NOTVLE) & OP=31 & BIT_25=1 & BITS_23_24=0 & STRM & A & B & XOP_1_10=374 & Rc=0 +{ + dataStreamTouchForStoreTransient(A,B,STRM:1); +} + +:lvebx vrD,RA_OR_ZERO,B is OP=31 & vrD & RA_OR_ZERO & B & XOP_1_10=7 & Rc=0 +{ + tmp:$(REGISTER_SIZE) = (RA_OR_ZERO + B); + tmpb:1 = *[ram]:1 tmp; + eb:1 = tmp[0,4]; +# This looks backwards from what the manual says, but it's ok since byte 0 in the manual is MSB +# where as for us byte 0 is LSB +@if ENDIAN == "big" + eb = 0xF - eb; +@endif + eb = eb * 8; + vrD = (zext(tmpb) << eb); + #vrD = loadVectorElementByteIndexed(A,B); +} + +:lvehx vrD,A,B is OP=31 & vrD & A & B & XOP_1_10=39 & Rc=0 +{ # TODO defintion + vrD = loadVectorElementHalfWordIndexed(A,B); +} + +:lvewx vrD,A,B is OP=31 & vrD & A & B & XOP_1_10=71 & Rc=0 +{ # TODO definition + vrD = loadVectorElementWordIndexed(A,B); +} + +:lvsl vrD,A,B is OP=31 & vrD & A & B & XOP_1_10=6 & Rc=0 +{ # TODO definition + vrD = loadVectorForShiftLeft(A,B); +} + +:lvsr vrD,RA_OR_ZERO,B is OP=31 & vrD & RA_OR_ZERO & B & XOP_1_10=38 & Rc=0 +{ + tmp:$(REGISTER_SIZE) = (RA_OR_ZERO + B); + eb:1 = tmp[0,4]; + eb = eb * 8; + srca:32=0x0001020304050607; + srcb:32=0x08090a0b0c0d0e0f; + srcc:32=0x1011121314151617; + srcd:32=0x18191a1b1c1d1e1f; + src:32 = (srca << 192) | (srcb << 128) | (srcc << 64) | srcd; + src = src >> eb; + vrD = src:16; +} + +:lvx vrD,RA_OR_ZERO,B is OP=31 & vrD & RA_OR_ZERO & B & XOP_1_10=103 & Rc=0 +{ +# vrD = loadVectorIndexed(A,B); + build RA_OR_ZERO; + tmp:$(REGISTER_SIZE) = (RA_OR_ZERO + B) & 0xfffffffffffffff0; + vrD = *[ram]:16 tmp; +} + +:lvxl vrD,A,B is OP=31 & vrD & A & B & XOP_1_10=359 & Rc=0 +{ # TODO definition + vrD = loadVectorIndexedLRU(A,B); +} + +:mfvscr vrD is OP=4 & vrD & vrAR=0 & vrBR=0 & XOP_1_10=770 & Rc=0 +{ # TODO definition + vrD = moveFromVectorStatusAndControlRegister(); +} + +:mtvscr vrB is OP=4 & vrDR=0 & vrAR=0 & vrB & XOP_1_10=802 & Rc=0 +{ # TODO definition + moveToVectorStatusAndControlRegister(vrB); +} + +:stvebx vrS,RA_OR_ZERO,B is OP=31 & vrS & RA_OR_ZERO & B & XOP_1_10=135 & Rc=0 +{ # TODO definition + EA:$(REGISTER_SIZE) = RA_OR_ZERO + B; + *[ram]:1 EA = storeVectorElementByteIndexed(vrS,RA_OR_ZERO,B); +} + +:stvehx vrS,RA_OR_ZERO,B is OP=31 & vrS & RA_OR_ZERO & B & XOP_1_10=167 & Rc=0 +{ # TODO definition + EA:$(REGISTER_SIZE) = RA_OR_ZERO + B; + *[ram]:2 EA = storeVectorElementHalfWordIndexed(vrS,RA_OR_ZERO,B); +} + +:stvewx vrS,RA_OR_ZERO,B is OP=31 & vrS & RA_OR_ZERO & B & XOP_1_10=199 & Rc=0 +{ # TODO definition + EA:$(REGISTER_SIZE) = (RA_OR_ZERO + B) & 0xfffffffffffffffc; + *[ram]:4 EA = storeVectorElementWordIndexed(vrS,RA_OR_ZERO,B); +} + +:stvx vrS,RA_OR_ZERO,B is OP=31 & vrS & B & RA_OR_ZERO & XOP_1_10=231 & Rc=0 +{ + tmp:$(REGISTER_SIZE) = (RA_OR_ZERO + B) & 0xfffffffffffffff0; + *[ram]:16 tmp = vrS; +} + +:stvxl vrS,RA_OR_ZERO,B is OP=31 & vrS & B & RA_OR_ZERO & XOP_1_10=487 & Rc=0 +{ # TODO definition + tmp:$(REGISTER_SIZE) = (RA_OR_ZERO + B) & 0xfffffffffffffff0; + *[ram]:16 tmp = vrS; + # mark_as_not_likely_to_be_needed_again_anytime_soon(tmp); +} + +:vaddcuw vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=384 +{ # TODO definition + vrD = vectorAddCarryoutUnsignedWord(vrA,vrB); +} + +:vaddfp vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=10 +{ # TODO definition + vrD = vectorAddFloatingPoint(vrA,vrB); +} + +:vaddsbs vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=768 +{ # TODO definition + vrD = vectorAddSignedByteSaturate(vrA,vrB); +} + +:vaddshs vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=832 +{ # TODO definition + vrD = vectorAddSignedHalfWordSaturate(vrA,vrB); +} + +:vaddsws vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=896 +{ # TODO definition + vrD = vectorAddSignedWordSaturate(vrA,vrB); +} + +vaddubm_part1: is vrA_8_0 & vrA_8_1 & vrA_8_2 & vrA_8_3 & vrA_8_4 & vrA_8_5 & vrA_8_6 & vrA_8_7 + & vrB_8_0 & vrB_8_1 & vrB_8_2 & vrB_8_3 & vrB_8_4 & vrB_8_5 & vrB_8_6 & vrB_8_7 + & vrD_8_0 & vrD_8_1 & vrD_8_2 & vrD_8_3 & vrD_8_4 & vrD_8_5 & vrD_8_6 & vrD_8_7 +{ + vrD_8_0 = vrA_8_0 + vrB_8_0; + vrD_8_1 = vrA_8_1 + vrB_8_1; + vrD_8_2 = vrA_8_2 + vrB_8_2; + vrD_8_3 = vrA_8_3 + vrB_8_3; + vrD_8_4 = vrA_8_4 + vrB_8_4; + vrD_8_5 = vrA_8_5 + vrB_8_5; + vrD_8_6 = vrA_8_6 + vrB_8_6; + vrD_8_7 = vrA_8_7 + vrB_8_7; +} + +vaddubm_part2: is vrA_8_8 & vrA_8_9 & vrA_8_10 & vrA_8_11 & vrA_8_12 & vrA_8_13 & vrA_8_14 & vrA_8_15 + & vrB_8_8 & vrB_8_9 & vrB_8_10 & vrB_8_11 & vrB_8_12 & vrB_8_13 & vrB_8_14 & vrB_8_15 + & vrD_8_8 & vrD_8_9 & vrD_8_10 & vrD_8_11 & vrD_8_12 & vrD_8_13 & vrD_8_14 & vrD_8_15 +{ + vrD_8_8 = vrA_8_8 + vrB_8_8; + vrD_8_9 = vrA_8_9 + vrB_8_9; + vrD_8_10 = vrA_8_10 + vrB_8_10; + vrD_8_11 = vrA_8_11 + vrB_8_11; + vrD_8_12 = vrA_8_12 + vrB_8_12; + vrD_8_13 = vrA_8_13 + vrB_8_13; + vrD_8_14 = vrA_8_14 + vrB_8_14; + vrD_8_15 = vrA_8_15 + vrB_8_15; +} + +# A bug in sleigh compiler forces us to keep the number of imported symbols less than 35 (it slows to a halt pass there), that is why we have vaddubm_part1 & vaddubm_part2 +:vaddubm vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=0 & vaddubm_part1 & vaddubm_part2 +{ +} + +:vaddubs vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=512 +{ # TODO definition + vrD = vectorAddUnsignedByteSaturate(vrA,vrB); +} + +:vadduhm vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=64 + & vrA_16_0 & vrA_16_1 & vrA_16_2 & vrA_16_3 & vrA_16_4 & vrA_16_5 & vrA_16_6 & vrA_16_7 + & vrB_16_0 & vrB_16_1 & vrB_16_2 & vrB_16_3 & vrB_16_4 & vrB_16_5 & vrB_16_6 & vrB_16_7 + & vrD_16_0 & vrD_16_1 & vrD_16_2 & vrD_16_3 & vrD_16_4 & vrD_16_5 & vrD_16_6 & vrD_16_7 +{ + vrD_16_0 = vrA_16_0 + vrB_16_0; + vrD_16_1 = vrA_16_1 + vrB_16_1; + vrD_16_2 = vrA_16_2 + vrB_16_2; + vrD_16_3 = vrA_16_3 + vrB_16_3; + vrD_16_4 = vrA_16_4 + vrB_16_4; + vrD_16_5 = vrA_16_5 + vrB_16_5; + vrD_16_6 = vrA_16_6 + vrB_16_6; + vrD_16_7 = vrA_16_7 + vrB_16_7; +} + +:vadduhs vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=576 +{ # TODO definition + vrD = vectorAddUnsignedHalfWordSaturate(vrA,vrB); +} + +:vadduwm vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=128 + & vrA_32_0 & vrA_32_1 & vrA_32_2 & vrA_32_3 + & vrB_32_0 & vrB_32_1 & vrB_32_2 & vrB_32_3 + & vrD_32_0 & vrD_32_1 & vrD_32_2 & vrD_32_3 +{ + vrD_32_0 = vrA_32_0 + vrB_32_0; + vrD_32_1 = vrA_32_1 + vrB_32_1; + vrD_32_2 = vrA_32_2 + vrB_32_2; + vrD_32_3 = vrA_32_3 + vrB_32_3; +} + +# Collides with vadduws +# :vadduws vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=640 +# { # TODO definition +# vrD = vectorAddUnsignedWordSaturate(vrA,vrB); +# } + +:vand vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1028 +{ # TODO definition + vrD = vectorLogicalAnd(vrA,vrB); +} + +:vandc vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1092 +{ # TODO definition + vrD = vectorLogicalAndWithComplement(vrA,vrB); +} + +:vavgsb vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1282 +{ # TODO definition + vrD = vectorAverageSignedByte(vrA,vrB); +} + +:vavgsh vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1346 +{ # TODO definition + vrD = vectorAverageSignedHalfWord(vrA,vrB); +} + +:vavgsw vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1410 +{ # TODO definition + vrD = vectorAverageSignedWord(vrA,vrB); +} + +:vavgub vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1026 +{ # TODO definition + vrD = vectorAverageUnsignedByte(vrA,vrB); +} + +:vavguh vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1090 +{ # TODO definition + vrD = vectorAverageUnsignedHalfWord(vrA,vrB); +} + +:vavguw vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1154 +{ # TODO definition + vrD = vectorAverageUnsignedWord(vrA,vrB); +} + +:vcfsx vrD,vrB,A_BITS is OP=4 & vrD & A_BITS & vrB & XOP_0_10=842 +{ # TODO definition + vrD = vectorConvertFromSignedFixedPointWord(vrB,A_BITS:1); +} + +:vcfux vrD,vrB,A_BITS is OP=4 & vrD & A_BITS & vrB & XOP_0_10=778 +{ # TODO definition + vrD = vectorConvertFromUnsignedFixedPointWord(vrB,A_BITS:1); +} + +:vcmpbfp vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=966 +{ # TODO definition + vrD = vectorCompareBoundsFloatingPoint(vrA,vrB); +} + +:vcmpbfp. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=966 +{ # TODO definition + # TODO change CR6 + vrD = vectorCompareBoundsFloatingPoint(vrA,vrB); +} + +:vcmpeqfp vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=198 +{ # TODO definition + # TODO change CR6 + vrD = vectorCompareEqualToFloatingPoint(vrA,vrB); +} + +:vcmpeqfp. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=198 +{ # TODO definition + vrD = vectorCompareEqualToFloatingPoint(vrA,vrB); +} + +:vcmpequb vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=6 +{ # TODO definition + # TODO change CR6 + vrD = vectorCompareEqualToUnsignedByte(vrA,vrB); +} + +:vcmpequb. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=6 +{ # TODO definition + # TODO change CR6 + vrD = vectorCompareEqualToUnsignedByte(vrA,vrB); +} + +:vcmpequh vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=70 +{ # TODO definition + # TODO change CR6 + vrD = vectorCompareEqualToUnsignedHalfWord(vrA,vrB); +} + +:vcmpequh. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=70 +{ # TODO definition + # TODO change CR6 + vrD = vectorCompareEqualToUnsignedHalfWord(vrA,vrB); +} + +:vcmpequw vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=134 +{ # TODO definition + # TODO change CR6 + vrD = vectorCompareEqualToUnsignedWord(vrA,vrB); +} + +:vcmpequw. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=134 +{ # TODO definition + # TODO change CR6 + vrD = vectorCompareEqualToUnsignedWord(vrA,vrB); +} + +:vcmpgefp vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=454 +{ # TODO definition + # TODO change CR6 + vrD = vectorCompareGreaterThanOrEqualToFloatingPoint(vrA,vrB); +} + +:vcmpgefp. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=454 +{ # TODO definition + # TODO change CR6 + vrD = vectorCompareGreaterThanOrEqualToFloatingPoint(vrA,vrB); +} + +:vcmpgtfp vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=710 +{ # TODO definition + # TODO change CR6 + vrD = vectorCompareGreaterThanFloatingPoint(vrA,vrB); +} + +:vcmpgtfp. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=710 +{ # TODO definition + # TODO change CR6 + vrD = vectorCompareGreaterThanFloatingPoint(vrA,vrB); +} + +:vcmpgtsb vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=774 +{ # TODO definition + # TODO change CR6 + vrD = vectorCompareGreaterThanSignedByte(vrA,vrB); +} + +:vcmpgtsb. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=774 +{ # TODO definition + # TODO change CR6 + vrD = vectorCompareGreaterThanSignedByte(vrA,vrB); +} + +:vcmpgtsh vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=838 +{ # TODO definition + # TODO change CR6 + vrD = vectorCompareGreaterThanConditionRegisterSignedHalfWord(vrA,vrB); +} + +:vcmpgtsh. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=838 +{ # TODO definition + # TODO change CR6 + vrD = vectorCompareGreaterThanConditionRegisterSignedHalfWord(vrA,vrB); +} + +:vcmpgtsw vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=902 +{ # TODO definition + # TODO change CR6 + vrD = vectorCompareGreaterThanSignedWord(vrA,vrB); +} + +:vcmpgtsw. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=902 +{ # TODO definition + # TODO change CR6 + vrD = vectorCompareGreaterThanSignedWord(vrA,vrB); +} + +:vcmpgtub vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=518 +{ # TODO definition + # TODO change CR6 + vrD = vectorCompareGreaterThanUnsignedByte(vrA,vrB); +} + +:vcmpgtub. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=518 +{ # TODO definition + # TODO change CR6 + vrD = vectorCompareGreaterThanUnsignedByte(vrA,vrB); +} + +:vcmpgtuh vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=582 +{ # TODO definition + # TODO change CR6 + vrD = vectorCompareGreaterThanUnsignedHalfWord(vrA,vrB); +} + +:vcmpgtuh. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=582 +{ # TODO definition + # TODO change CR6 + vrD = vectorCompareGreaterThanUnsignedHalfWord(vrA,vrB); +} + +:vcmpgtuw vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=0 & XOP_0_9=646 +{ # TODO definition + # TODO change CR6 + vrD = vectorCompareGreaterThanUnsignedWord(vrA,vrB); +} + +:vcmpgtuw. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & BIT_10=1 & XOP_0_9=646 +{ # TODO definition + # TODO change CR6 + vrD = vectorCompareGreaterThanUnsignedWord(vrA,vrB); +} + +:vctsxs vrD,vrB,A_BITS is OP=4 & vrD & A_BITS & vrB & XOP_0_10=970 +{ # TODO definition + vrD = vectorConvertToSignedFixedPointWordSaturate(vrB,A_BITS:1); +} + +:vctuxs vrD,vrB,A_BITS is OP=4 & vrD & A_BITS & vrB & XOP_0_10=906 +{ # TODO definition + vrD = vectorConvertToUnsignedFixedPointWordSaturate(vrB,A_BITS:1); +} + +:vexptefp vrD,vrB is OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=394 +{ # TODO definition + vrD = vector2RaisedToTheExponentEstimateFloatingPoint(vrB); +} + +:vlogefp vrD,vrB is OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=458 +{ # TODO definition + vrD = vectorLog2EstimateFloatingPoint(vrB); +} + +:vmaddfp vrD,vrA,vrC,vrB is OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=46 +{ # TODO definition + vrD = vectorMultiplyAddFloatingPoint(vrA,vrC,vrB); +} + +:vmaxfp vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1034 +{ # TODO definition + vrD = vectorMaximumFloatingPoint(vrA,vrB); +} + +:vmaxsb vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=258 +{ # TODO definition + vrD = vectorMaximumSignedByte(vrA,vrB); +} + +:vmaxsh vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=322 +{ # TODO definition + vrD = vectorMaximumSignedHalfWord(vrA,vrB); +} + +:vmaxsw vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=386 +{ # TODO definition + vrD = vectorMaximumSignedWord(vrA,vrB); +} + +:vmaxub vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=2 +{ # TODO definition + vrD = vectorMaximumUnsignedByte(vrA,vrB); +} + +:vmaxuh vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=66 +{ # TODO definition + vrD = vectorMaximumUnsignedHalfWord(vrA,vrB); +} + +:vmaxuw vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=130 +{ # TODO definition + vrD = vectorMaximumUnsignedWord(vrA,vrB); +} + +:vmhaddshs vrD,vrA,vrB,vrC is OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=32 +{ # TODO definition + vrD = vectorMultiplyHighAndAddSignedHalfWordSaturate(vrA,vrB,vrC); +} + +:vmhraddshs vrD,vrA,vrB,vrC is OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=33 +{ # TODO definition + vrD = vectorMultiplyHighRoundAndAddSignedHalfWordSaturate(vrA,vrB,vrC); +} + +:vminfp vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1098 +{ # TODO definition + vrD = vectorMinimumFloatingPoint(vrA,vrB); +} + +:vminsb vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=770 +{ # TODO definition + vrD = vectorMinimumSignedByte(vrA,vrB); +} + +:vminsh vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=834 +{ # TODO definition + vrD = vectorMinimumSignedHalfWord(vrA,vrB); +} + +:vminsw vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=898 +{ # TODO definition + vrD = vectorMinimumSignedWord(vrA,vrB); +} + +:vminub vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=514 +{ # TODO definition + vrD = vectorMinimumUnsignedByte(vrA,vrB); +} + +:vminuh vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=578 +{ # TODO definition + vrD = vectorMinimumUnsignedHalfWord(vrA,vrB); +} + +:vminuw vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=642 +{ # TODO definition + vrD = vectorMinimumUnsignedWord(vrA,vrB); +} + +:vmladduhm vrD,vrA,vrB,vrC is OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=34 +{ # TODO definition + vrD = vectorMultiplyLowAndAddUnsignedHalfWordModulo(vrA,vrB,vrC); +} + +:vmrghb vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=12 +{ # TODO definition + vrD = vectorMergeHighByte(vrA,vrB); +} + +:vmrghh vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=76 +{ # TODO definition + vrD = vectorMergeHighHalfWord(vrA,vrB); +} + +:vmrghw vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=140 +{ # TODO definition + vrD = vectorMergeHighWord(vrA,vrB); +} + +:vmrglb vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=268 +{ # TODO definition + vrD = vectorMergeLowByte(vrA,vrB); +} + +:vmrglh vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=332 +{ # TODO definition + vrD = vectorMergeLowHalfWord(vrA,vrB); +} + +:vmrglw vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=396 +{ # TODO definition + vrD = vectorMergeLowWord(vrA,vrB); +} + +:vmsummbm vrD,vrA,vrB,vrC is OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=37 +{ # TODO definition + vrD = vectorMultiplySumMixedSignByteModulo(vrA,vrB,vrC); +} + +:vmsumshm vrD,vrA,vrB,vrC is OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=40 +{ # TODO definition + vrD = vectorMultiplySumSignedHalfWordModulo(vrA,vrB,vrC); +} + +:vmsumshs vrD,vrA,vrB,vrC is OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=41 +{ # TODO definition + vrD = vectorMultiplySumSignedHalfWordSaturate(vrA,vrB,vrC); +} + +:vmsumubm vrD,vrA,vrB,vrC is OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=36 +{ # TODO definition + vrD = vectorMultiplySumUnsignedByteModulo(vrA,vrB,vrC); +} + +:vmsumuhm vrD,vrA,vrB,vrC is OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=38 +{ # TODO definition + vrD = vectorMultiplySumUnsignedHalfWordModulo(vrA,vrB,vrC); +} + +:vmsumuhs vrD,vrA,vrB,vrC is OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=39 +{ # TODO definition + vrD = vectorMultiplySumUnsignedHalfWordSaturate(vrA,vrB,vrC); +} + +:vmulesb vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=776 +{ # TODO definition + vrD = vectorMultiplyEvenSignedByte(vrA,vrB); +} + +:vmulesh vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=840 +{ # TODO definition + vrD = vectorMultiplyEvenSignedHalfWord(vrA,vrB); +} + +:vmuleub vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=520 +{ # TODO definition + vrD = vectorMultiplyEvenUnsignedByte(vrA,vrB); +} + +:vmuleuh vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=584 +{ # TODO definition + vrD = vectorMultiplyEvenUnsignedHalfWord(vrA,vrB); +} + +:vmulosb vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=264 +{ # TODO definition + vrD = vectorMultiplyOddSignedByte(vrA,vrB); +} + +:vmulosh vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=328 +{ # TODO definition + vrD = vectorMultiplyOddSignedHalfWord(vrA,vrB); +} + +:vmuloub vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=8 +{ # TODO definition + vrD = vectorMultiplyOddUnsignedByte(vrA,vrB); +} + +:vmulouh vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=72 +{ # TODO definition + vrD = vectorMultiplyOddUnsignedHalfWord(vrA,vrB); +} + +:vnmsubfp vrD,vrA,vrC,vrB is OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=47 +{ # TODO definition + vrD = vectorNegativeMultiplySubtractFloatingPoint(vrA,vrC,vrB); +} + +:vnor vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1284 +{ + vrD = ~(vrA | vrB); +} + +:vor vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1156 +{ + vrD = vrA | vrB; +} + +:vperm vrD,vrA,vrB,vrC is OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=43 +{ +# tmp:32 = (zext(vrA) << 128) | zext(vrB); +# tmp2:16 = 0; +# tmp3:32 = 0; +# cnt:1 = 15; +# +# tmp2 = (vrC >> (cnt * 8)) & 0x1F; +# tmp3 = tmp >> ((31 - tmp2) * 8); +# vrD = vrD << 8; +# vrD[0,8] = tmp3[0,8]; +# if (cnt == 0) goto ; +# cnt = cnt - 1; +# goto ; +# + vrD = vectorPermute(vrA,vrB,vrC); +} + +:vpkpx vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=782 +{ # TODO definition + vrD = vectorPackPixel32(vrA,vrB); +} + +:vpkshss vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=398 +{ # TODO definition + vrD = vectorPackSignedHalfWordSignedSaturate(vrA,vrB); +} + +:vpkshus vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=270 +{ # TODO definition + vrD = vectorPackSignedHalfWordUnsignedSaturate(vrA,vrB); +} + +:vpkswss vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=462 +{ # TODO definition + vrD = vectorPackSignedWordSignedSaturate(vrA,vrB); +} + +:vpkswus vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=334 +{ # TODO definition + vrD = vectorPackSignedWordUnsignedSaturate(vrA,vrB); +} + +:vpkuhum vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=14 +{ # TODO definition + vrD = vectorPackUnsignedHalfWordUnsignedModulo(vrA,vrB); +} + +:vpkuhus vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=142 +{ # TODO definitionXTF = + vrD = vectorPackUnsignedHalfWordUnsignedSaturate(vrA,vrB); +} + +:vpkuwum vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=78 +{ # TODO definition + vrD = vectorPackUnsignedWordUnsignedModulo(vrA,vrB); +} + +:vpkuwus vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=206 +{ # TODO definition + vrD = vectorPackUnsignedWordUnsignedSaturate(vrA,vrB); +} + +:vrefp vrD,vrB is OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=266 +{ # TODO definition + vrD = vectorReciprocalEstimateFloatingPoint(vrB); +} + +:vrfim vrD,vrB is OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=714 +{ # TODO definition + vrD = vectorRoundToFloatingPointIntegerTowardMinusInfinity(vrB); +} + +:vrfin vrD,vrB is OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=522 +{ # TODO definition + vrD = vectorRoundToFloatingPointIntegerNearest(vrB); +} + +:vrfip vrD,vrB is OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=650 +{ # TODO definition + vrD = vectorRoundToFloatingPointIntegerTowardPluInfinity(vrB); +} + +:vrfiz vrD,vrB is OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=586 +{ # TODO definition + vrD = vectorRoundToFloatingPointIntegerTowardZero(vrB); +} + +:vrlb vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=4 +{ # TODO definition + vrD = vectorRotateLeftIntegerByte(vrA,vrB); +} + +:vrlh vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=68 +{ # TODO definition + vrD = vectorRotateLeftIntegerHalfWord(vrA,vrB); +} + +:vrlw vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=132 +{ # TODO definition + vrD = vectorRotateLeftIntegerWord(vrA,vrB); +} + +:vrsqrtefp vrD,vrB is OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=330 +{ # TODO definition + vrD = vectorReciprocalSquareRootEstimateFloatingPoint(vrB); +} + +:vsel vrD,vrA,vrB,vrC is OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=42 +{ # TODO definition + vrD = vectorConditionalSelect(vrA,vrB,vrC); +} + +:vsl vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=452 +{ # TODO definition + vrD = vectorShiftLeft(vrA,vrB); +} + +:vslb vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=260 +{ # TODO definition + vrD = vectorShiftLeftIntegerByte(vrA,vrB); +} + +:vsldoi vrD,vrA,vrB,SHB is OP=4 & vrD & vrA & vrB & BIT_10=0 & SHB & XOP_0_5=44 +{ + tmp:32 = (zext(vrA) << 128) | zext(vrB); + tmp = tmp << (SHB:1 * 8); + vrD = tmp[128,128]; +} + +:vslh vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=324 +{ # TODO definition + vrD = vectorShiftLeftIntegerHalfWord(vrA,vrB); +} + +:vslo vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1036 +{ # TODO definition + vrD = vectorShiftLeftByOctet(vrA,vrB); +} + +:vslw vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=388 +{ # TODO definition + vrD = vectorShiftLeftIntegerWord(vrA,vrB); +} + +:vspltb vrD,vrB,UIMB is OP=4 & vrD & BITS_20_20=0 & UIMB & vrB & XOP_0_10=524 +{ + tmp:1 = (0xF - UIMB) * 8; + tmpa:16 = (vrB >> tmp) & 0xFF; + vrD = tmpa | (tmpa << 8) | (tmpa << 16) | (tmpa << 24) | (tmpa << 32) | (tmpa << 40) | (tmpa << 48) | (tmpa << 56); + vrD = vrD | (tmpa << 64) | (tmpa << 72) | (tmpa << 80) | (tmpa << 88) | (tmpa << 96) | (tmpa << 104) | (tmpa << 112) | (tmpa << 120); +} + +:vsplth vrD,vrB,UIMH is OP=4 & vrD & BITS_19_20=0 & UIMH & vrB & XOP_0_10=588 +{ # TODO definition + vrD = vectorSplatHalfWord(vrB,UIMH:1); +} + +:vspltisb vrD,A_BITSS is OP=4 & vrD & A_BITSS & B_BITS=0 & XOP_0_10=780 +{ # TODO definition + vrD = vectorSplatImmediateSignedByte(A_BITSS:1); +} + +:vspltish vrD,A_BITSS is OP=4 & vrD & A_BITSS & B_BITS=0 & XOP_0_10=844 +{ # TODO definition + vrD = vectorSplatImmediateSignedHalfWord(A_BITSS:1); +} + +:vspltisw vrD,A_BITSS is OP=4 & vrD & A_BITSS & B_BITS=0 & XOP_0_10=908 +{ + tmpw:4 = sext(A_BITSS:1); + tmp:16 = zext(tmpw); + vrD = (tmp) | (tmp << 32) | (tmp << 64) | (tmp << 96); +} + +# A better way to do this would be to make a subtable to interpret +# UIMW into the corresponding subword, then assign the subregisters of vrD +# to that value. +:vspltw vrD,vrB,UIMW is OP=4 & vrD & vrB & BITS_18_20=0 & UIMW & XOP_0_10=652 +{ + local b = (3 - UIMW) * 32; + local tmp:16 = (vrB >> b) & 0xffffffff; + vrD = (tmp) | (tmp << 32) | (tmp << 64) | (tmp << 96); +} + +:vsr vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=708 +{ # TODO definition + vrD = vectorShiftRight(vrA,vrB); +} + +:vsrab vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=772 +{ # TODO definition + vrD = vectorShiftRightAlgebraicByte(vrA,vrB); +} + +:vsrah vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=836 +{ # TODO definition + vrD = vectorShiftRightAlgebraicHalfWord(vrA,vrB); +} + +:vsraw vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=900 +{ # TODO definition + vrD = vectorShiftRightAlgebraicWord(vrA,vrB); +} + +:vsrb vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=516 +{ # TODO definition + vrD = vectorShiftRightByte(vrA,vrB); +} + +:vsrh vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=580 +{ # TODO definition + vrD = vectorShiftRightHalfWord(vrA,vrB); +} + +:vsro vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1100 +{ # TODO definition + vrD = vectorShiftRightByOctet(vrA,vrB); +} + +:vsrw vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=644 +{ # TODO definition + vrD = vectorShiftRightWord(vrA,vrB); +} + +:vsubcuw vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1408 +{ # TODO definition + vrD = vectorSubtractCarryoutUnsignedWord(vrA,vrB); +} + +:vsubfp vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=74 +{ # TODO definition + vrD = vectorSubtractFloatingPoint(vrA,vrB); +} + +:vsubsbs vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1792 +{ # TODO definition + vrD = vectorSubtractSignedByteSaturate(vrA,vrB); +} + +:vsubshs vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1856 +{ # TODO definition + vrD = vectorSubtractSignedHalfWordSaturate(vrA,vrB); +} + +:vsubsws vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1920 +{ # TODO definition + vrD = vectorSubtractSignedWordSaturate(vrA,vrB); +} + +:vsububm vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1024 +{ # TODO definition + vrD = vectorSubtractUnsignedByteModulo(vrA,vrB); +} + +:vsububs vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1536 +{ # TODO definition + vrD = vectorSubtractUnsignedByteSaturate(vrA,vrB); +} + +:vsubuhm vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1088 + & vrA_16_0 & vrA_16_1 & vrA_16_2 & vrA_16_3 & vrA_16_4 & vrA_16_5 & vrA_16_6 & vrA_16_7 + & vrB_16_0 & vrB_16_1 & vrB_16_2 & vrB_16_3 & vrB_16_4 & vrB_16_5 & vrB_16_6 & vrB_16_7 + & vrD_16_0 & vrD_16_1 & vrD_16_2 & vrD_16_3 & vrD_16_4 & vrD_16_5 & vrD_16_6 & vrD_16_7 +{ + vrD_16_0 = vrA_16_0 - vrB_16_0; + vrD_16_1 = vrA_16_1 - vrB_16_1; + vrD_16_2 = vrA_16_2 - vrB_16_2; + vrD_16_3 = vrA_16_3 - vrB_16_3; + vrD_16_4 = vrA_16_4 - vrB_16_4; + vrD_16_5 = vrA_16_5 - vrB_16_5; + vrD_16_6 = vrA_16_6 - vrB_16_6; + vrD_16_7 = vrA_16_7 - vrB_16_7; +} + +:vsubuhs vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1600 +{ # TODO definition + vrD = vectorSubtractUnsignedHalfWordSaturate(vrA,vrB); +} + +:vsubuwm vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1152 +{ # TODO definition + vrD = vectorSubtractUnsignedWordModulo(vrA,vrB); +} + +:vsubuws vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1664 +{ # TODO definition + vrD = vectorSubtractUnsignedWordSaturate(vrA,vrB); +} + +:vsumsws vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1928 +{ # TODO definition + vrD = vectorSumAcrossSignedWordSaturate(vrA,vrB); +} + +:vsum2sws vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1672 +{ # TODO definition + vrD = vectorSumAcrossPartialSignedWordSaturate(vrA,vrB); +} + +:vsum4sbs vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1800 +{ # TODO definition + vrD = vectorSumAcrossPartialSignedByteSaturate(vrA,vrB); +} + +:vsum4shs vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1608 +{ # TODO definition + vrD = vectorSumAcrossPartialSignedHalfWordSaturate(vrA,vrB); +} + +:vsum4ubs vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1544 +{ # TODO definition + vrD = vectorSumAcrossPartialUnsignedByteSaturate(vrA,vrB); +} + +:vupkhpx vrD,vrB is OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=846 +{ # TODO definition + vrD = vectorUnpackHighPixel16(vrB); +} + +:vupkhsb vrD,vrB is OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=526 +{ # TODO definition + vrD = vectorUnpackHighSignedByte(vrB); +} + +:vupkhsh vrD,vrB is OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=590 +{ # TODO definition + vrD = vectorUnpackHighSignedHalfWord(vrB); +} + +:vupklpx vrD,vrB is OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=974 +{ # TODO definition + vrD = vectorUnpackLowPixel16(vrB); +} + +:vupklsb vrD,vrB is OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=654 +{ # TODO definition + vrD = vectorUnpackLowSignedByte(vrB); +} + +:vupklsh vrD,vrB is OP=4 & vrD & A_BITS=0 & vrB & XOP_0_10=718 +{ # TODO definition + vrD = vectorUnpackLowSignedHalfWord(vrB); +} + +:vxor vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1220 +{ + vrD = vrA ^ vrB; +} + + +define pcodeop altv207_1; +define pcodeop altv207_2; +define pcodeop altv207_3; +define pcodeop altv207_4; +define pcodeop altv207_5; +define pcodeop altv207_6; +define pcodeop altv207_7; +define pcodeop altv207_8; +define pcodeop altv207_9; +define pcodeop altv207_10; +define pcodeop altv207_11; +define pcodeop altv207_12; +define pcodeop altv207_13; +define pcodeop altv207_14; +define pcodeop altv207_15; +define pcodeop altv207_16; +define pcodeop altv207_17; +define pcodeop altv207_18; +define pcodeop altv207_19; +define pcodeop altv207_20; +define pcodeop altv207_21; +define pcodeop altv207_22; +define pcodeop altv207_23; +define pcodeop altv207_24; +define pcodeop altv207_25; +define pcodeop altv207_26; +define pcodeop altv207_27; +define pcodeop altv207_28; +define pcodeop altv207_29; +define pcodeop altv207_30; +define pcodeop altv207_31; +define pcodeop altv207_32; +define pcodeop altv207_33; +define pcodeop altv207_34; +define pcodeop altv207_35; +define pcodeop altv207_36; +define pcodeop altv207_37; +define pcodeop altv207_38; +define pcodeop altv207_39; +define pcodeop altv207_40; +define pcodeop altv207_41; +define pcodeop altv207_42; +define pcodeop altv207_43; +define pcodeop altv207_44; +define pcodeop altv207_45; +define pcodeop altv207_46; +define pcodeop altv207_47; +define pcodeop altv207_48; +define pcodeop altv207_49; +define pcodeop altv207_50; +define pcodeop altv207_51; +define pcodeop altv207_52; +define pcodeop altv207_53; +define pcodeop altv207_54; +define pcodeop altv207_55; +define pcodeop altv207_56; +define pcodeop altv207_57; +define pcodeop altv207_58; +define pcodeop altv207_59; +define pcodeop altv207_60; +define pcodeop altv207_61; +define pcodeop altv207_62; +define pcodeop altv207_63; +define pcodeop altv207_64; +define pcodeop altv207_65; + +define pcodeop altv300_1; +define pcodeop altv300_2; +define pcodeop altv300_3; +define pcodeop altv300_4; +define pcodeop altv300_5; +define pcodeop altv300_6; +define pcodeop altv300_7; +define pcodeop altv300_8; +define pcodeop altv300_9; +define pcodeop altv300_10; +define pcodeop altv300_11; +define pcodeop altv300_12; +define pcodeop altv300_13; +define pcodeop altv300_14; +define pcodeop altv300_15; +define pcodeop altv300_16; +define pcodeop altv300_17; +define pcodeop altv300_18; +define pcodeop altv300_19; +define pcodeop altv300_20; +define pcodeop altv300_21; +define pcodeop altv300_22; +define pcodeop altv300_23; +define pcodeop altv300_24; +define pcodeop altv300_25; +define pcodeop altv300_26; +define pcodeop altv300_27; +define pcodeop altv300_28; +define pcodeop altv300_29; +define pcodeop altv300_30; +define pcodeop altv300_31; +define pcodeop altv300_32; +define pcodeop altv300_33; +define pcodeop altv300_34; +define pcodeop altv300_35; +define pcodeop altv300_36; +define pcodeop altv300_41; +define pcodeop altv300_42; +define pcodeop altv300_43; +define pcodeop altv300_44; +define pcodeop altv300_45; +define pcodeop altv300_46; +define pcodeop altv300_47; +define pcodeop altv300_48; +define pcodeop altv300_49; +define pcodeop altv300_50; +define pcodeop altv300_51; +define pcodeop altv300_52; +define pcodeop altv300_53; +define pcodeop altv300_54; +define pcodeop altv300_55; +define pcodeop altv300_56; +define pcodeop altv300_57; +define pcodeop altv300_58; +define pcodeop altv300_59; +define pcodeop altv300_60; +define pcodeop altv300_61; +define pcodeop altv300_62; +define pcodeop altv300_63; +define pcodeop altv300_64; +define pcodeop altv300_65; +define pcodeop altv300_66; +define pcodeop altv300_67; +define pcodeop altv300_68; +define pcodeop altv300_69; +define pcodeop altv300_70; +define pcodeop altv300_71; + +################# +# 2.07 additions +:bcdadd. vrD,vrA,vrB,PS is OP=4 & BIT_10=1 & XOP_0_8=1 & vrA & vrB & vrD & PS { + vrD = altv207_64(vrA,vrB,PS:1); +} + +:bcdsub. vrD,vrA,vrB,PS is OP=4 & BIT_10=1 & XOP_0_8=65 & vrA & vrB & vrD & PS { + vrD = altv207_65(vrA,vrB,PS:1); +} + + +:vaddcuq vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=320 { + vrD = altv207_1(vrA,vrB); +} + +:vaddecuq vrD,vrA,vrB,vrC is OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=61 { + vrD = altv207_2(vrA,vrB,vrC); +} + +:vaddeuqm vrD,vrA,vrB,vrC is OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=60 { + vrD = altv207_3(vrA,vrB,vrC); +} + +:vaddudm vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=192 { + vrD = altv207_4(vrA,vrB); +} + +:vadduqm vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=256 { + vrD = altv207_5(vrA,vrB); +} + +:vbpermq vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1356 { + vrD = altv207_6(vrA,vrB); +} + +:vcipher vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1288 { + vrD = altv207_7(vrA,vrB); +} + +:vcipherlast vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1289 { + vrD = altv207_8(vrA,vrB); +} + +:vclzb vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_10=1794 { + vrD = altv207_9(vrB); +} + +:vclzd vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_10=1986 { + vrD = altv207_10(vrB); +} + +:vclzh vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_10=1858 { + vrD = altv207_11(vrB); +} + +:vclzw vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_10=1922 { + vrD = altv207_12(vrB); +} + +:vcmpequd vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & Rc2=0 & XOP_0_9=199 { + vrD = altv207_13(vrA,vrB); +} + +:vcmpequd. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & Rc2=1 & XOP_0_9=199 { + vrD = altv207_14(vrA,vrB); +} + +:vcmpgtsd vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & Rc2=0 & XOP_0_9=967 { + vrD = altv207_15(vrA,vrB); +} + +:vcmpgtsd. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & Rc2=1 & XOP_0_9=967 { + vrD = altv207_16(vrA,vrB); +} + +:vcmpgtud vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & Rc2=0 & XOP_0_9=711 { + vrD = altv207_17(vrA,vrB); +} + +:vcmpgtud. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & Rc2=1 & XOP_0_9=711 { + vrD = altv207_18(vrA,vrB); +} + +:veqv vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1668 { + vrD = altv207_19(vrA,vrB); +} + +:vgbbd vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_10=1292 { + vrD = altv207_20(vrB); +} + +:vmaxsd vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=450 { + vrD = altv207_21(vrA,vrB); +} + +:vmaxud vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=194 { + vrD = altv207_22(vrA,vrB); +} + +:vminsd vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=962 { + vrD = altv207_23(vrA,vrB); +} + +:vminud vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=706 { + altv207_24(vrA,vrB); +} + +:vmrgew vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1932 { + vrD = altv207_25(vrA,vrB); +} + +:vmrgow vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1676 { + vrD = altv207_26(vrA,vrB); +} + +:vmulesw vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=904 { + vrD = altv207_27(vrA,vrB); +} + +:vmuleuw vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=648 { + vrD = altv207_28(vrA,vrB); +} + +:vmulosw vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=392 { + vrD = altv207_29(vrA,vrB); +} + +:vmulouw vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=136 { + vrD = altv207_30(vrA,vrB); +} + +:vmuluwm vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=137 { + vrD = altv207_31(vrA,vrB); +} + +:vnand vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1412 { + vrD = altv207_32(vrA,vrB); +} + +:vncipher vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1352 { + vrD = altv207_33(vrA,vrB); +} + +:vncipherlast vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1353 { + vrD = altv207_34(vrA,vrB); +} + +:vorc vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1348 { + vrD = altv207_35(vrA,vrB); +} + +:vpermxor vrD,vrA,vrB,vrC is OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=45 { + vrD = altv207_36(vrA,vrB,vrC); +} + +:vpksdss vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1486 { + vrD = altv207_37(vrA,vrB); +} + +:vpksdus vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1358 { + vrD = altv207_38(vrA,vrB); +} + +:vpkudum vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1102 { + vrD = altv207_39(vrA,vrB); +} + +:vpkudus vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1230 { + vrD = altv207_41(vrA,vrB); +} + +:vpmsumb vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1032 { + vrD = altv207_42(vrA,vrB); +} + +:vpmsumd vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1224 { + vrD = altv207_43(vrA,vrB); +} + +:vpmsumh vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1096 { + vrD = altv207_44(vrA,vrB); +} + +:vpmsumw vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1160 { + vrD = altv207_45(vrA,vrB); +} + +:vpopcntb vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_10=1795 { + vrD = altv207_46(vrB); +} + +:vpopcntd vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_10=1987 { + vrD = altv207_47(vrB); +} + +:vpopcnth vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_10=1859 { + vrD = altv207_48(vrB); +} + +:vpopcntw vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_10=1923 { + vrD = altv207_49(vrB); +} + +:vrld vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=196 { + vrD = altv207_50(vrA,vrB); +} + +:vsbox vrD,vrA is OP=4 & vrD & vrA & BITS_11_15=0 & XOP_0_10=1480 { + vrD = altv207_51(vrA); +} + +:vshasigmad vrD,vrA,ST,SIX is OP=4 & vrD & vrA & ST & SIX & XOP_0_10=1730 { + vrD = altv207_52(vrA,ST:1,SIX:1); +} + +:vshasigmaw vrD,vrA,ST,SIX is OP=4 & vrD & vrA & ST & SIX & XOP_0_10=1666 { + vrD = altv207_53(vrA,ST:1,SIX:1); +} + +:vsld vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1476 { + vrD = altv207_54(vrA,vrB); +} + +:vsrad vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=964 { + vrD = altv207_55(vrA,vrB); +} + +:vsrd vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1732 { + vrD = altv207_56(vrA,vrB); +} + +:vsubcuq vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1344 { + vrD = altv207_57(vrA,vrB); +} + +:vsubecuq vrD,vrA,vrB,vrC is OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=63 { + vrD = altv207_58(vrA,vrB,vrC); +} + +:vsubeuqm vrD,vrA,vrB,vrC is OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=62 { + vrD = altv207_59(vrA,vrB,vrC); +} + +:vsubudm vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1216 { + vrD = altv207_60(vrA,vrB); +} + +:vsubuqm vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1280 { + vrD = altv207_61(vrA,vrB); +} + +:vupkhsw vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_10=1614 { + vrD = altv207_62(vrB); +} + +:vupklsw vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_10=1742 { + vrD = altv207_63(vrB); +} + +################### +# v3.0 + +:bcdcfn. vrD,vrB,PS is OP=4 & vrD & vrB & BITS_16_20=7 & XOP_0_8=385 & BIT_10=1 & PS { + vrD = altv300_1(vrB,PS:1); +} + +:bcdcfsq. vrD,vrB,PS is OP=4 & vrD & vrB & BITS_16_20=2 & XOP_0_8=385 & BIT_10=1 & PS { + vrD = altv300_2(vrB,PS:1); +} + +:bcdcfz. vrD,vrB,PS is OP=4 & vrD & vrB & BITS_16_20=6 & XOP_0_8=385 & BIT_10=1 & PS { + vrD = altv300_3(vrB,PS:1); +} + +:bcdcpsgn. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=833 { + vrD = altv300_4(vrA,vrB); +} + +:bcdctn. vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=5 & XOP_0_8=385 & BIT_10=1 & BIT_9=0 { + vrD = altv300_5(vrB); +} + +:bcdctsq. vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_8=385 & BIT_10=1 & BIT_9=0 { + vrD = altv300_6(vrB); +} + +:bcdctz. vrD,vrB,PS is OP=4 & vrD & vrB & BITS_16_20=4 & XOP_0_8=385 & BIT_10=1 & PS { + vrD = altv300_7(vrB,PS:1); +} + +:bcds. vrD,vrA,vrB,PS is OP=4 & vrD & vrA & vrB & XOP_0_8=193 & BIT_10=1 & PS { + vrD = altv300_8(vrA,vrB,PS:1); +} + +:bcdsetsgn. vrD,vrB,PS is OP=4 & vrD & vrB & BITS_16_20=31 & XOP_0_8=385 & BIT_10=1 & PS { + vrD = altv300_9(vrB,PS:1); +} + +:bcdsr. vrD,vrA,vrB,PS is OP=4 & vrD & vrA & vrB & XOP_0_8=449 & BIT_10=1 & PS { + vrD = altv300_10(vrA,vrB,PS:1); +} + +:bcdtrunc. vrD,vrA,vrB,PS is OP=4 & vrD & vrA & vrB & XOP_0_8=257 & BIT_10=1 & PS { + vrD = altv300_12(vrA,vrB,PS:1); +} + +:bcdus. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_8=129 & BIT_10=1 { + vrD = altv300_13(vrA,vrB); +} + +:bcdutrunc. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_8=321 & BIT_10=1 { + vrD = altv300_14(vrA,vrB); +} + +:vabsdub vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1027 { + vrD = altv300_15(vrA,vrB); +} + +:vabsduh vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1091 { + vrD = altv300_16(vrA,vrB); +} + +:vabsduw vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1155 { + vrD = altv300_17(vrA,vrB); +} + +:vbpermd vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1484 { + vrD = altv300_18(vrA,vrB); +} + +:vclzlsbb vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=0 & XOP_0_10=1538 { + vrD = altv300_19(vrB); +} + +:vcmpneb vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & Rc2=0 & XOP_0_9=7 { + vrD = altv300_20(vrA,vrB); +} + +:vcmpneb. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & Rc2=1 & XOP_0_9=7 { + vrD = altv300_21(vrA,vrB); +} + +:vcmpneh vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & Rc2=0 & XOP_0_9=71 { + vrD = altv300_22(vrA,vrB); +} + +:vcmpneh. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & Rc2=1 & XOP_0_9=71 { + vrD = altv300_23(vrA,vrB); +} + +:vcmpnew vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & Rc2=0 & XOP_0_9=135 { + vrD = altv300_24(vrA,vrB); +} + +:vcmpnew. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & Rc2=1 & XOP_0_9=135 { + vrD = altv300_25(vrA,vrB); +} + +:vcmpnezb vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & Rc2=0 & XOP_0_9=263 { + vrD = altv300_26(vrA,vrB); +} + +:vcmpnezb. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & Rc2=1 & XOP_0_9=263 { + vrD = altv300_27(vrA,vrB); +} + +:vcmpnezh vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & Rc2=0 & XOP_0_9=327 { + vrD = altv300_28(vrA,vrB); +} + +:vcmpnezh. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & Rc2=1 & XOP_0_9=327 { + vrD = altv300_29(vrA,vrB); +} + +:vcmpnezw vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & Rc2=0 & XOP_0_9=391 { + vrD = altv300_30(vrA,vrB); +} + +:vcmpnezw. vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & Rc2=1 & XOP_0_9=391 { + vrD = altv300_31(vrA,vrB); +} + +:vctzb vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=28 & XOP_0_10=1538 { + vrD = altv300_32(vrB); +} + +:vctzh vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=29 & XOP_0_10=1538 { + vrD = altv300_33(vrB); +} + +:vctzd vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=31 & XOP_0_10=1538 { + vrD = altv300_34(vrB); +} + +:vctzlsbb vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=1 & XOP_0_10=1538 { + vrD = altv300_35(vrB); +} + +:vctzw vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=30 & XOP_0_10=1538 { + vrD = altv300_36(vrB); +} + +:vextractd vrD,vrB,UIMB is OP=4 & vrD & BITS_20_20=0 & UIMB & vrB & XOP_0_10=717 { + # if UIMB > 8 the result is undefined + vrD = (vrB >> (8 * (8 - UIMB))) & 0xffffffffffffffff; +} + +:vextractub vrD,vrB,UIMB is OP=4 & vrD & BITS_20_20=0 & UIMB & vrB & XOP_0_10=525 { + # if UIMB > 15 the result is undefined + vrD = (vrB >> (16 * (15 - UIMB))) & 0xff; +} + +:vextractuh vrD,vrB,UIMB is OP=4 & vrD & BITS_20_20=0 & UIMB & vrB & XOP_0_10=589 { + # if UIMB > 14 the result is undefined + vrD = (vrB >> (16 * (14 - UIMB))) & 0xffff; +} + +:vextractuw vrD,vrB,UIMB is OP=4 & vrD & BITS_20_20=0 & UIMB & vrB & XOP_0_10=653 { + # if UIMB > 12 the result is undefined + vrD = (vrB >> (16 * (12 - UIMB))) & 0xffffffff; +} + +:vextsb2d vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=24 & XOP_0_10=1538 { + vrD = altv300_41(vrB); +} + +:vextsb2w vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=16 & XOP_0_10=1538 { + vrD = altv300_42(vrB); +} + +:vextsh2d vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=25 & XOP_0_10=1538 { + vrD = altv300_43(vrB); +} + +:vextsh2w vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=17 & XOP_0_10=1538 { + vrD = altv300_44(vrB); +} + +:vextsw2d vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=26 & XOP_0_10=1538 { + vrD = altv300_45(vrB); +} + +:vextublx D,A,vrB is OP=4 & D & A & vrB & XOP_0_10=1549 { + D = altv300_46(A,vrB); +} + +:vextubrx D,A,vrB is OP=4 & D & A & vrB & XOP_0_10=1805 { + D = altv300_47(A,vrB); +} + +:vextuhlx D,A,vrB is OP=4 & D & A & vrB & XOP_0_10=1613 { + D = altv300_48(A,vrB); +} + +:vextuhrx D,A,vrB is OP=4 & D & A & vrB & XOP_0_10=1869 { + D = altv300_49(A,vrB); +} + +# beware the backwards bit/byte ordering in the manual +:vextuwlx D,A,vrB is OP=4 & D & A & vrB & XOP_0_10=1677 +{ + local offs:2 = (12 - zext(A[0,4])) * 8; + local out:16 = (vrB >> offs) & 0xffffffff; + D = out:4; +} + +:vextuwrx D,A,vrB is OP=4 & D & A & vrB & XOP_0_10=1933 { + D = altv300_51(A,vrB); +} + +:vinsertb vrD,vrB,UIMB is OP=4 & vrD & BITS_20_20=0 & UIMB & vrB & XOP_0_10=781 { + vrD = altv300_52(vrB,UIMB:1); +} + +:vinsertd vrD,vrB,UIMB is OP=4 & vrD & BITS_20_20=0 & UIMB & vrB & XOP_0_10=973 { + vrD = altv300_53(vrB,UIMB:1); +} + +:vinserth vrD,vrB,UIMB is OP=4 & vrD & BITS_20_20=0 & UIMB & vrB & XOP_0_10=845 { + vrD = altv300_54(vrB,UIMB:1); +} + +:vinsertw vrD,vrB,UIMB is OP=4 & vrD & BITS_20_20=0 & UIMB & vrB & XOP_0_10=909 { + vrD = altv300_55(vrB,UIMB:1); +} + +:vmul10cuq vrD,vrA is OP=4 & vrD & vrA & BITS_11_15=0 & XOP_0_10=1 { + vrD = altv300_56(vrA); +} + +:vmul10ecuq vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=65 { + vrD = altv300_57(vrA,vrB); +} + +:vmul10euq vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=577 { + vrD = altv300_58(vrA,vrB); +} + +:vmul10uq vrD,vrA is OP=4 & vrD & vrA & BITS_11_15=0 & XOP_0_10=513 { + vrD = altv300_59(vrA); +} + +:vnegd vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=7 & XOP_0_10=1538 { + vrD = altv300_60(vrB); +} + +:vnegw vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=6 & XOP_0_10=1538 { + vrD = altv300_61(vrB); +} + +:vpermr vrD,vrA,vrB,vrC is OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=59 { + vrD = altv300_62(vrA,vrB,vrC); +} + +:vprtybd vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=9 & XOP_0_10=1538 { + vrD = altv300_63(vrB); +} + +:vprtybq vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=10 & XOP_0_10=1538 { + vrD = altv300_64(vrB); +} + +:vprtybw vrD,vrB is OP=4 & vrD & vrB & BITS_16_20=8 & XOP_0_10=1538 { + vrD = altv300_65(vrB); +} + +:vrldmi vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=197 { + vrD = altv300_66(vrA,vrB); +} + +:vrldnm vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=453 { + vrD = altv300_67(vrA,vrB); +} + +:vrlwmi vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=133 { + vrD = altv300_68(vrA,vrB); +} + +:vrlwnm vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=389 { + vrD = altv300_69(vrA,vrB); +} + +:vslv vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1860 { + vrD = altv300_70(vrA,vrB); +} + +:vsrv vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1796 { + vrD = altv300_71(vrA,vrB); +} diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/evx.sinc b/python/icicle/Ghidra/Processors/PowerPC/data/languages/evx.sinc new file mode 100644 index 0000000..b47a5f1 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/evx.sinc @@ -0,0 +1,129 @@ + +@include "Scalar_SPFP.sinc" +@ifdef IS_ISA +@include "SPE_APU.sinc" +@endif + +define pcodeop vectorExclusiveOr; +define pcodeop vectorMergeHigh; +define pcodeop vectorMergeLow; +define pcodeop vectorLoadDoubleWordIntoDoubleWordIndexed; +define pcodeop vectorStoreDoubleOfDoubleIndexed; +define pcodeop initializeAccumulator; +define pcodeop vectorShiftRightWordSigned; +define pcodeop vectorShiftRightWordUnsigned; + +:evxor vrD_64_0,vrA_64_0,vrB_64_0 is OP=4 & vrD_64_0 & vrA_64_0 & vrB_64_0 & XOP_0_10=534 +{ + vrD_64_0 = vrA_64_0 ^ vrB_64_0; +} + +:evmergehi S,A,B is OP=4 & S & A & B & XOP_0_10=556 +{ + vectorMergeHigh(S,A,B); +} + +:evmergelo S,A,B is OP=4 & S & A & B & XOP_0_10=557 +{ + vectorMergeLow(S,A,B); +} + + +:evldd RT,dUI16PlusRAOrZeroAddress is OP=4 & RT & dUI16PlusRAOrZeroAddress & XOP_0_10=769 +{ + ea:$(REGISTER_SIZE) = dUI16PlusRAOrZeroAddress; + RT = *:8 ($(EATRUNC)); +} + +:evlddx RT,RA_OR_ZERO,RB is OP=4 & RT & RA_OR_ZERO & RB & XOP_0_10=768 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + RB; + RT = *:8 ($(EATRUNC)); +} + +@ifndef IS_ISA +:evsrws S,A,B is OP=4 & S & A & B & XOP_0_10=545 +{ + vectorShiftRightWordSigned(S,A,B); +} +@endif + +@ifndef IS_ISA +:evsrwu S,A,B is OP=4 & S & A & B & XOP_0_10=544 +{ + vectorShiftRightWordUnsigned(S,A,B); +} +@endif + +:evstdd RS,dUI16PlusRAOrZeroAddress is OP=4 & RS & dUI16PlusRAOrZeroAddress & XOP_0_10=801 +{ + ea:$(REGISTER_SIZE) = dUI16PlusRAOrZeroAddress; + *:8 ($(EATRUNC)) = RS; +} + +:evstddx RS,RA_OR_ZERO,RB is OP=4 & RS & RA_OR_ZERO & RB & XOP_0_10=800 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + RB; + *:8 ($(EATRUNC)) = RS; +} + +:evmra RT,RA is OP=4 & RT & RA & BITS_11_15=0 & XOP_0_10=1220 +{ + ACC = zext(RA); + RT = RA; +} + +# evmergehilo rD,rA,rB 010 0010 1110 +define pcodeop VectorMergeHighLow; +:evmergehilo D,A,B is OP=4 & A & B & D & XOP_0_10=558 { + local lo = (A & 0x00000000FFFFFFFF); + local hi = ((A & 0xFFFFFFFF00000000) >> 32); + #local b_lo:$(REGISTER_SIZE) = (B & 0x00000000FFFFFFFF); + local b_hi:$(REGISTER_SIZE) = ((B & 0xFFFFFFFF00000000) >> 32); + + lo = lo; + hi = b_hi; + + D = ((hi << 32) | lo); +} + +# evmergelohi rD,rA,rB 010 0010 1111 +:evmergelohi D,A,B is OP=4 & D & A & B & XOP_0_10=559 { + local lo = (A & 0x00000000FFFFFFFF); + local hi = ((A & 0xFFFFFFFF00000000) >> 32); + local b_lo:$(REGISTER_SIZE) = (B & 0x00000000FFFFFFFF); + #local b_hi:$(REGISTER_SIZE) = ((B & 0xFFFFFFFF00000000) >> 32); + + lo = lo; + hi = b_lo; + + D = ((hi << 32) | lo); +} + +# evstwwe rS,rA,UIMM 011 0011 1001 +:evstwwe RS,dUI16PlusRAOrZeroAddress is OP=4 & RS & dUI16PlusRAOrZeroAddress & XOP_0_10=0x339 +{ + ea:$(REGISTER_SIZE) = dUI16PlusRAOrZeroAddress; + *:4 ($(EATRUNC)) = RS:4; +} + +# evstwwex rS,rA,rB 011 0011 1000 +:evstwwex RS,RA_OR_ZERO,RB is OP=4 & RS & RA_OR_ZERO & RB & XOP_0_10=0x338 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + RB; + *:4 ($(EATRUNC)) = RS:4; +} + +:lvx vrD, RA_OR_ZERO, RB is OP=31 & vrD & RA_OR_ZERO & RB & XOP_1_10=103 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + RB; + vrD = *:16 ($(EATRUNC)); +} + +:stvx vrS, RA_OR_ZERO, RB is OP=31 & vrS & RA_OR_ZERO & RB & XOP_1_10=231 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + RB; + *:16 ($(EATRUNC)) = vrS; +} + + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/g2.sinc b/python/icicle/Ghidra/Processors/PowerPC/data/languages/g2.sinc new file mode 100644 index 0000000..1e1466a --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/g2.sinc @@ -0,0 +1,14 @@ + +define pcodeop tlbli; +define pcodeop tlbld; + +:tlbld B is $(NOTVLE) & OP=31 & BITS_21_25=0 & BITS_16_20=0 & B & XOP_1_10=978 & BIT_0=0 +{ + tlbld(B); +} + +:tlbli B is $(NOTVLE) & OP=31 & BITS_21_25=0 & BITS_16_20=0 & B & XOP_1_10=1010 & BIT_0=0 +{ + tlbli(B); +} + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/lmwInstructions.sinc b/python/icicle/Ghidra/Processors/PowerPC/data/languages/lmwInstructions.sinc new file mode 100644 index 0000000..d213a8e --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/lmwInstructions.sinc @@ -0,0 +1,101 @@ +LDMR0: is lsmul=1 {} +LDMR0: is epsilon { loadReg(r0); } + +LDMR1: is lsmul=2 {} +LDMR1: is LDMR0 { build LDMR0; loadReg(r1); } + +LDMR2: is lsmul=3 {} +LDMR2: is LDMR1 { build LDMR1; loadReg(r2); } + +LDMR3: is lsmul=4 {} +LDMR3: is LDMR2 { build LDMR2; loadReg(r3); } + +LDMR4: is lsmul=5 {} +LDMR4: is LDMR3 { build LDMR3; loadReg(r4); } + +LDMR5: is lsmul=6 {} +LDMR5: is LDMR4 { build LDMR4; loadReg(r5); } + +LDMR6: is lsmul=7 {} +LDMR6: is LDMR5 { build LDMR5; loadReg(r6); } + +LDMR7: is lsmul=8 {} +LDMR7: is LDMR6 { build LDMR6; loadReg(r7); } + +LDMR8: is lsmul=9 {} +LDMR8: is LDMR7 { build LDMR7; loadReg(r8); } + +LDMR9: is lsmul=10 {} +LDMR9: is LDMR8 { build LDMR8; loadReg(r9); } + +LDMR10: is lsmul=11 {} +LDMR10: is LDMR9 { build LDMR9; loadReg(r10); } + +LDMR11: is lsmul=12 {} +LDMR11: is LDMR10 { build LDMR10; loadReg(r11); } + +LDMR12: is lsmul=13 {} +LDMR12: is LDMR11 { build LDMR11; loadReg(r12); } + +LDMR13: is lsmul=14 {} +LDMR13: is LDMR12 { build LDMR12; loadReg(r13); } + +LDMR14: is lsmul=15 {} +LDMR14: is LDMR13 { build LDMR13; loadReg(r14); } + +LDMR15: is lsmul=16 {} +LDMR15: is LDMR14 { build LDMR14; loadReg(r15); } + +LDMR16: is lsmul=17 {} +LDMR16: is LDMR15 { build LDMR15; loadReg(r16); } + +LDMR17: is lsmul=18 {} +LDMR17: is LDMR16 { build LDMR16; loadReg(r17); } + +LDMR18: is lsmul=19 {} +LDMR18: is LDMR17 { build LDMR17; loadReg(r18); } + +LDMR19: is lsmul=20 {} +LDMR19: is LDMR18 { build LDMR18; loadReg(r19); } + +LDMR20: is lsmul=21 {} +LDMR20: is LDMR19 { build LDMR19; loadReg(r20); } + +LDMR21: is lsmul=22 {} +LDMR21: is LDMR20 { build LDMR20; loadReg(r21); } + +LDMR22: is lsmul=23 {} +LDMR22: is LDMR21 { build LDMR21; loadReg(r22); } + +LDMR23: is lsmul=24 {} +LDMR23: is LDMR22 { build LDMR22; loadReg(r23); } + +LDMR24: is lsmul=25 {} +LDMR24: is LDMR23 { build LDMR23; loadReg(r24); } + +LDMR25: is lsmul=26 {} +LDMR25: is LDMR24 { build LDMR24; loadReg(r25); } + +LDMR26: is lsmul=27 {} +LDMR26: is LDMR25 { build LDMR25; loadReg(r26); } + +LDMR27: is lsmul=28 {} +LDMR27: is LDMR26 { build LDMR26; loadReg(r27); } + +LDMR28: is lsmul=29 {} +LDMR28: is LDMR27 { build LDMR27; loadReg(r28); } + +LDMR29: is lsmul=30 {} +LDMR29: is LDMR28 { build LDMR28; loadReg(r29); } + +LDMR30: is lsmul=31 {} +LDMR30: is LDMR29 { build LDMR29; loadReg(r30); } + +LDMR31: is LDMR30 { build LDMR30; loadReg(r31); } + +:lmw D,dPlusRaOrZeroAddress is $(NOTVLE) & OP=46 & D & BITS_21_25 & dPlusRaOrZeroAddress & LDMR31 [ lsmul = BITS_21_25; ] +{ + tea = dPlusRaOrZeroAddress; + build LDMR31; +} + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/lswInstructions.sinc b/python/icicle/Ghidra/Processors/PowerPC/data/languages/lswInstructions.sinc new file mode 100644 index 0000000..4f3c081 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/lswInstructions.sinc @@ -0,0 +1,185 @@ +#lswi r0,0,7 0x7c 00 3c aa +#lswi r0,r2,7 0x7c 02 3c aa + +DYN_D1: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 1)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; } +DYN_D2: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 2)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; } +DYN_D3: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 3)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; } +DYN_D4: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 4)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; } +DYN_D5: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 5)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; } +DYN_D6: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 6)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; } +DYN_D7: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 7)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; } + +:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=0 & BH=0 & XOP_1_10=597 & BIT_0=0 + & DYN_D1 & DYN_D2 & DYN_D3 & DYN_D4 & DYN_D5 & DYN_D6 & DYN_D7 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + loadRegister(D,ea); + loadRegister(DYN_D1,ea); + loadRegister(DYN_D2,ea); + loadRegister(DYN_D3,ea); + loadRegister(DYN_D4,ea); + loadRegister(DYN_D5,ea); + loadRegister(DYN_D6,ea); + loadRegister(DYN_D7,ea); +} + +:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=0 & BH & XOP_1_10=597 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + sa:1 = BH; + loadRegisterPartial(D,ea,sa); +} + +:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=1 & BH=0 & XOP_1_10=597 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + loadRegister(D,ea); +} + +:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=1 & BH & XOP_1_10=597 & BIT_0=0 + & DYN_D1 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + loadRegister(D,ea); + sa:1 = BH; + loadRegisterPartial(DYN_D1,ea,sa); +} + + +:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=2 & BH=0 & XOP_1_10=597 & BIT_0=0 + & DYN_D1 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + loadRegister(D,ea); + loadRegister(DYN_D1,ea); +} + +:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=2 & BH & XOP_1_10=597 & BIT_0=0 + & DYN_D1 & DYN_D2 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + loadRegister(D,ea); + loadRegister(DYN_D1,ea); + sa:1 = BH; + loadRegisterPartial(DYN_D2,ea,sa); +} + +:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=3 & BH=0 & XOP_1_10=597 & BIT_0=0 + & DYN_D1 & DYN_D2 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + loadRegister(D,ea); + loadRegister(DYN_D1,ea); + loadRegister(DYN_D2,ea); +} + +:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=3 & BH & XOP_1_10=597 & BIT_0=0 + & DYN_D1 & DYN_D2 & DYN_D3 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + loadRegister(D,ea); + loadRegister(DYN_D1,ea); + loadRegister(DYN_D2,ea); + sa:1 = BH; + loadRegisterPartial(DYN_D3,ea,sa); +} + +:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=4 & BH=0 & XOP_1_10=597 & BIT_0=0 + & DYN_D1 & DYN_D2 & DYN_D3 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + loadRegister(D,ea); + loadRegister(DYN_D1,ea); + loadRegister(DYN_D2,ea); + loadRegister(DYN_D3,ea); +} + +:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=4 & BH & XOP_1_10=597 & BIT_0=0 + & DYN_D1 & DYN_D2 & DYN_D3 & DYN_D4 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + loadRegister(D,ea); + loadRegister(DYN_D1,ea); + loadRegister(DYN_D2,ea); + loadRegister(DYN_D3,ea); + sa:1 = BH; + loadRegisterPartial(DYN_D4,ea,sa); +} + +:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=5 & BH=0 & XOP_1_10=597 & BIT_0=0 + & DYN_D1 & DYN_D2 & DYN_D3 & DYN_D4 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + loadRegister(D,ea); + loadRegister(DYN_D1,ea); + loadRegister(DYN_D2,ea); + loadRegister(DYN_D3,ea); + loadRegister(DYN_D4,ea); +} + +:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=5 & BH & XOP_1_10=597 & BIT_0=0 + & DYN_D1 & DYN_D2 & DYN_D3 & DYN_D4 & DYN_D5 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + loadRegister(D,ea); + loadRegister(DYN_D1,ea); + loadRegister(DYN_D2,ea); + loadRegister(DYN_D3,ea); + loadRegister(DYN_D4,ea); + sa:1 = BH; + loadRegisterPartial(DYN_D5,ea,sa); +} + +:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=6 & BH=0 & XOP_1_10=597 & BIT_0=0 + & DYN_D1 & DYN_D2 & DYN_D3 & DYN_D4 & DYN_D5 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + loadRegister(D,ea); + loadRegister(DYN_D1,ea); + loadRegister(DYN_D2,ea); + loadRegister(DYN_D3,ea); + loadRegister(DYN_D4,ea); + loadRegister(DYN_D5,ea); +} + +:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=6 & BH & XOP_1_10=597 & BIT_0=0 + & DYN_D1 & DYN_D2 & DYN_D3 & DYN_D4 & DYN_D5 & DYN_D6 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + loadRegister(D,ea); + loadRegister(DYN_D1,ea); + loadRegister(DYN_D2,ea); + loadRegister(DYN_D3,ea); + loadRegister(DYN_D4,ea); + loadRegister(DYN_D5,ea); + sa:1 = BH; + loadRegisterPartial(DYN_D6,ea,sa); +} + +:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=7 & BH=0 & XOP_1_10=597 & BIT_0=0 + & DYN_D1 & DYN_D2 & DYN_D3 & DYN_D4 & DYN_D5 & DYN_D6 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + loadRegister(D,ea); + loadRegister(DYN_D1,ea); + loadRegister(DYN_D2,ea); + loadRegister(DYN_D3,ea); + loadRegister(DYN_D4,ea); + loadRegister(DYN_D5,ea); + loadRegister(DYN_D6,ea); +} + +:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=7 & BH & XOP_1_10=597 & BIT_0=0 + & DYN_D1 & DYN_D2 & DYN_D3 & DYN_D4 & DYN_D5 & DYN_D6 & DYN_D7 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + loadRegister(D,ea); + loadRegister(DYN_D1,ea); + loadRegister(DYN_D2,ea); + loadRegister(DYN_D3,ea); + loadRegister(DYN_D4,ea); + loadRegister(DYN_D5,ea); + loadRegister(DYN_D6,ea); + sa:1 = BH; + loadRegisterPartial(DYN_D7,ea,sa); +} diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/old/oldPPC.lang b/python/icicle/Ghidra/Processors/PowerPC/data/languages/old/oldPPC.lang new file mode 100644 index 0000000..0e242f5 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/old/oldPPC.lang @@ -0,0 +1,1196 @@ + + + + PowerPC:BE:32:DEPRECATED + PowerPC + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/old/oldPPC.trans b/python/icicle/Ghidra/Processors/PowerPC/data/languages/old/oldPPC.trans new file mode 100644 index 0000000..af53127 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/old/oldPPC.trans @@ -0,0 +1,7 @@ + + + Sleigh-PowerPC 32-bit + PowerPC:BE:32:default + + + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc.dwarf b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc.dwarf new file mode 100644 index 0000000..9bff0cc --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc.dwarf @@ -0,0 +1,19 @@ + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc.ldefs b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc.ldefs new file mode 100644 index 0000000..1d3dc8e --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc.ldefs @@ -0,0 +1,335 @@ + + + + + PowerPC 32-bit big endian w/Altivec, G2 + + + + + + + + PowerPC 32-bit little endian w/Altivec, G2 + + + + + + + + PowerPC 64-bit big endian w/Altivec, G2 + + + + + + + + PowerPC 64-bit big endian w/Altivec and 32 bit addressing, G2 + + + + + + + + PowerPC 64-bit little endian w/Altivec and 32 bit addressing, G2 + + + + + + + + + PowerPC 64-bit little endian w/Altivec, G2 + + + + + + + PowerPC 4xx 32-bit big endian embedded core + + + + + + + PowerPC 4xx 32-bit little endian embedded core + + + + + + + + Freescale MPC8280 32-bit big endian family (PowerQUICC-III) + + + + + + + PowerQUICC-III 32-bit big endian family + + + + + + + PowerQUICC-III 32-bit little endian family + + + + + + + + PowerQUICC-III e500 32-bit big-endian family + + + + + + + + PowerQUICC-III e500 32-bit little-endian family + + + + + + + + Power ISA 3.0 Big Endian w/EVX and 32-bit Addressing + + + + + + + + Power ISA 3.0 Little Endian w/EVX and 32-bit Addressing + + + + + + + + + Power ISA 3.0 Big Endian w/Altivec and 32-bit Addressing + + + + + + + + Power ISA 3.0 Little Endian w/Altivec and 32-bit Addressing + + + + + + + + + Power ISA 3.0 Big Endian w/Altivec + + + + + + + Power ISA 3.0 Little Endian w/Altivec + + + + + + + Power ISA 3.0 Big Endian w/VLE, EVX and 32-bit Addressing + + + + + + + Power ISA 3.0 Big Endian w/VLE, Altivec and 32-bit Addressing + + + + + + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32.pspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32.pspec new file mode 100644 index 0000000..8c9194e --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32.pspec @@ -0,0 +1,1223 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_4xx_be.slaspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_4xx_be.slaspec new file mode 100644 index 0000000..1a370be --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_4xx_be.slaspec @@ -0,0 +1,13 @@ +# SLA specification file for IBM PowerPC 4xx series core + +@define ENDIAN "big" + +@define REGISTER_SIZE "4" + +@define EATRUNC "ea" + +@define CTR_OFFSET "32" + +@include "ppc_common.sinc" +@include "4xx.sinc" + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_4xx_le.slaspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_4xx_le.slaspec new file mode 100644 index 0000000..91e7a93 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_4xx_le.slaspec @@ -0,0 +1,13 @@ +# SLA specification file for IBM PowerPC 4xx series core + +@define ENDIAN "little" + +@define REGISTER_SIZE "4" + +@define EATRUNC "ea" + +@define CTR_OFFSET "32" + +@include "ppc_common.sinc" +@include "4xx.sinc" + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_be.cspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_be.cspec new file mode 100644 index 0000000..ded16f6 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_be.cspec @@ -0,0 +1,126 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_be.slaspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_be.slaspec new file mode 100644 index 0000000..046f729 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_be.slaspec @@ -0,0 +1,14 @@ +# SLA specification file for PowerPC 32-bit big endian + +@define ENDIAN "big" + +@define REGISTER_SIZE "4" + +@define EATRUNC "ea" + +@define CTR_OFFSET "32" + +@include "ppc_common.sinc" +@include "altivec.sinc" +@include "g2.sinc" + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_be_Mac.cspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_be_Mac.cspec new file mode 100644 index 0000000..4029a5b --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_be_Mac.cspec @@ -0,0 +1,74 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + * (r1 + 0x14) = r2; + + + + + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_be.cspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_be.cspec new file mode 100644 index 0000000..ab242c7 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_be.cspec @@ -0,0 +1,80 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_be.slaspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_be.slaspec new file mode 100644 index 0000000..5a9b490 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_be.slaspec @@ -0,0 +1,29 @@ +# SLA specification file for IBM PowerPC e500 series core + +# NOTE: This language variant includes some registers and instructions not supported +# by the actual processor (e.g., floating pointer registers and associated instructions). +# The actual processor only supports a subset of the registers and instructions implemented. + +@define E500 + +@define ENDIAN "big" + +# Although a 32-bit architecture, 64-bit general purpose registers are supported. +# Language has been modeled using a 64-bit implementation with a 32-bit truncated +# memory space (see ldefs). + +@define REGISTER_SIZE "8" +@define BIT_64 "64" + +@define EATRUNC "ea" + +@define CTR_OFFSET "32" + +@define NoLegacyIntegerMultiplyAccumulate + +@include "ppc_common.sinc" +@include "quicciii.sinc" +@include "evx.sinc" +@include "SPEF_SCR.sinc" +@include "SPE_EFSD.sinc" +@include "SPE_EFV.sinc" diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_le.cspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_le.cspec new file mode 100644 index 0000000..616161e --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_le.cspec @@ -0,0 +1,79 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_le.slaspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_le.slaspec new file mode 100644 index 0000000..719c022 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_le.slaspec @@ -0,0 +1,29 @@ +# SLA specification file for IBM PowerPC e500 series core + +# NOTE: This language variant includes some registers and instructions not supported +# by the actual processor (e.g., floating pointer registers and associated instructions). +# The actual processor only supports a subset of the registers and instructions implemented. + +@define E500 + +@define ENDIAN "little" + +# Although a 32-bit architecture, 64-bit general purpose registers are supported. +# Language has been modeled using a 64-bit implementation with a 32-bit truncated +# memory space (see ldefs). + +@define REGISTER_SIZE "8" +@define BIT_64 "64" + +@define EATRUNC "ea" + +@define CTR_OFFSET "32" + +@define NoLegacyIntegerMultiplyAccumulate + +@include "ppc_common.sinc" +@include "quicciii.sinc" +@include "evx.sinc" +@include "SPEF_SCR.sinc" +@include "SPE_EFSD.sinc" +@include "SPE_EFV.sinc" diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_le.cspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_le.cspec new file mode 100644 index 0000000..1e36de3 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_le.cspec @@ -0,0 +1,126 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_le.slaspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_le.slaspec new file mode 100644 index 0000000..4cc253c --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_le.slaspec @@ -0,0 +1,11 @@ +# SLA specification file for PowerPC 32-bit little endian + +@define ENDIAN "little" + +@define REGISTER_SIZE "4" + +@define EATRUNC "ea" + +@include "ppc_common.sinc" +@include "altivec.sinc" +@include "g2.sinc" diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_mpc8270.pspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_mpc8270.pspec new file mode 100644 index 0000000..95fdbf3 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_mpc8270.pspec @@ -0,0 +1,1156 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_quicciii_be.slaspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_quicciii_be.slaspec new file mode 100644 index 0000000..d1636cf --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_quicciii_be.slaspec @@ -0,0 +1,14 @@ +# SLA specification file for IBM PowerPC 4xx series core + +@define ENDIAN "big" + +@define REGISTER_SIZE "4" + +@define EATRUNC "ea" + +@define CTR_OFFSET "32" + +@include "ppc_common.sinc" +@include "quicciii.sinc" +@include "evx.sinc" + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_quicciii_le.slaspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_quicciii_le.slaspec new file mode 100644 index 0000000..5f09364 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_32_quicciii_le.slaspec @@ -0,0 +1,14 @@ +# SLA specification file for IBM PowerPC 4xx series core + +@define ENDIAN "little" + +@define REGISTER_SIZE "4" + +@define EATRUNC "ea" + +@define CTR_OFFSET "32" + +@include "ppc_common.sinc" +@include "quicciii.sinc" +@include "evx.sinc" + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64.cspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64.cspec new file mode 100644 index 0000000..7220be7 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64.cspec @@ -0,0 +1,124 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + # Inject pcode when returning from a function call to place the r2Save + # value into 0x28(r1) which should be restored by the "ld r2,0x28(r1)" + # which immediately follows calls which comply with the PPC64 ABI spec. + local saveR2ptr = r1 + 0x28; + *:8 saveR2ptr = r2Save; + + + + + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64.pspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64.pspec new file mode 100644 index 0000000..028581a --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64.pspec @@ -0,0 +1,1220 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_32.cspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_32.cspec new file mode 100644 index 0000000..109b980 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_32.cspec @@ -0,0 +1,129 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_be.slaspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_be.slaspec new file mode 100644 index 0000000..6cc821a --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_be.slaspec @@ -0,0 +1,11 @@ +# SLA specification file for PowerPC 64-bit big endian + +@define ENDIAN "big" + +@define REGISTER_SIZE "8" +@define BIT_64 "64" +@define EATRUNC "ea:4" + +@include "ppc_common.sinc" +@include "altivec.sinc" +@include "g2.sinc" diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_be_Mac.cspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_be_Mac.cspec new file mode 100644 index 0000000..d36edb1 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_be_Mac.cspec @@ -0,0 +1,109 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_isa_altivec_be.slaspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_isa_altivec_be.slaspec new file mode 100644 index 0000000..7e2c7df --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_isa_altivec_be.slaspec @@ -0,0 +1,33 @@ +# SLA specification file for Power ISA Version 2.06 Revision B (July 23, 2010) +# ISA (Instruction Set Architecture) a trademarked name for PowerPC specifications from IBM. + +@define ENDIAN "big" + +@define IS_ISA "1" +@define NoLegacyIntegerMultiplyAccumulate "1" + +@define REGISTER_SIZE "8" +@define BIT_64 "64" + +@define EATRUNC "ea" + +@define CTR_OFFSET "32" + +@include "ppc_common.sinc" +@include "ppc_isa.sinc" + +@include "ppc_a2.sinc" +@include "quicciii.sinc" +@include "FPRC.sinc" + +# A given processor can be compliant with the PowerISA spec by including EITHER +# the embedded vector instructions (EVX) OR the AltiVec instructions +# However, these instruction sets overlap in their bit patterns, so Sleigh cannot support +# both at the same time. We have two language variants for PowerISA +# that specify which of these two vector specs is supported. +#@include "evx.sinc" +#@include "SPEF_SCR.sinc" +#@include "SPE_EFSD.sinc" +#@include "SPE_EFV.sinc" +## OR +@include "altivec.sinc" diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_isa_altivec_le.slaspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_isa_altivec_le.slaspec new file mode 100644 index 0000000..4bb1fe4 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_isa_altivec_le.slaspec @@ -0,0 +1,34 @@ +# SLA specification file for Power ISA Version 2.06 Revision B (July 23, 2010) +# ISA (Instruction Set Architecture) a trademarked name for PowerPC specifications from IBM. + +@define ENDIAN "little" + +@define IS_ISA "1" +@define NoLegacyIntegerMultiplyAccumulate "1" + +@define REGISTER_SIZE "8" +@define BIT_64 "64" + +@define EATRUNC "ea" + +@define CTR_OFFSET "32" + +@include "ppc_common.sinc" +@include "ppc_isa.sinc" + +@include "ppc_a2.sinc" +@include "quicciii.sinc" +@include "FPRC.sinc" + +# A given processor can be compliant with the PowerISA spec by including EITHER +# the embedded vector instructions (EVX) OR the AltiVec instructions +# However, these instruction sets overlap in their bit patterns, so Sleigh cannot support +# both at the same time. We have two language variants for PowerISA +# that specify which of these two vector specs is supported. +#@include "evx.sinc" +#@include "SPEF_SCR.sinc" +#@include "SPE_EFSD.sinc" +#@include "SPE_EFV.sinc" +# OR +@include "altivec.sinc" + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_isa_altivec_vle_be.slaspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_isa_altivec_vle_be.slaspec new file mode 100644 index 0000000..9a39b19 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_isa_altivec_vle_be.slaspec @@ -0,0 +1,35 @@ +# SLA specification file for Power ISA Version 2.06 Revision B (July 23, 2010) +# ISA (Instruction Set Architecture) a trademarked name for PowerPC specifications from IBM. + +@define ENDIAN "big" + +@define IS_ISA "1" +@define NoLegacyIntegerMultiplyAccumulate "1" + +@define REGISTER_SIZE "8" +@define BIT_64 "64" + +@define EATRUNC "ea" + +@define CTR_OFFSET "32" + +@include "ppc_common.sinc" +@include "ppc_isa.sinc" + +@include "ppc_a2.sinc" +@include "quicciii.sinc" +@include "FPRC.sinc" + +@include "ppc_vle.sinc" + +# A given processor can be compliant with the PowerISA spec by including EITHER +# the embedded vector instructions (EVX) OR the AltiVec instructions +# However, these instruction sets overlap in their bit patterns, so Sleigh cannot support +# both at the same time. We have two language variants for PowerISA +# that specify which of these two vector specs is supported. +#@include "evx.sinc" +#@include "SPEF_SCR.sinc" +#@include "SPE_EFSD.sinc" +#@include "SPE_EFV.sinc" +## OR +@include "altivec.sinc" diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_isa_be.slaspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_isa_be.slaspec new file mode 100644 index 0000000..8be6714 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_isa_be.slaspec @@ -0,0 +1,32 @@ +# SLA specification file for Power ISA Version 2.06 Revision B (July 23, 2010) +# ISA (Instruction Set Architecture) a trademarked name for PowerPC specifications from IBM. + +@define ENDIAN "big" + +@define IS_ISA "1" +@define NoLegacyIntegerMultiplyAccumulate "1" + +@define REGISTER_SIZE "8" +@define BIT_64 "64" + +@define EATRUNC "ea" + +@define CTR_OFFSET "32" + +@include "ppc_common.sinc" +@include "ppc_isa.sinc" + +@include "quicciii.sinc" +@include "FPRC.sinc" + +# A given processor can be compliant with the PowerISA spec by including EITHER +# the embedded vector instructions (EVX) OR the AltiVec instructions +# However, these instruction sets overlap in their bit patterns, so Sleigh cannot support +# both at the same time. We have two language variants for PowerISA +# that specify which of these two vector specs is supported. +@include "evx.sinc" +@include "SPEF_SCR.sinc" +@include "SPE_EFSD.sinc" +@include "SPE_EFV.sinc" +# OR +#@include "altivec.sinc" diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_isa_le.slaspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_isa_le.slaspec new file mode 100644 index 0000000..ec7f1f5 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_isa_le.slaspec @@ -0,0 +1,33 @@ +# SLA specification file for Power ISA Version 2.06 Revision B (July 23, 2010) +# ISA (Instruction Set Architecture) a trademarked name for PowerPC specifications from IBM. + +@define ENDIAN "little" + +@define IS_ISA "1" +@define NoLegacyIntegerMultiplyAccumulate "1" + +@define REGISTER_SIZE "8" +@define BIT_64 "64" + +@define EATRUNC "ea" + +@define CTR_OFFSET "32" + +@include "ppc_common.sinc" +@include "ppc_isa.sinc" + +@include "quicciii.sinc" +@include "FPRC.sinc" + +# A given processor can be compliant with the PowerISA spec by including EITHER +# the embedded vector instructions (EVX) OR the AltiVec instructions +# However, these instruction sets overlap in their bit patterns, so Sleigh cannot support +# both at the same time. We have two language variants for PowerISA +# that specify which of these two vector specs is supported. +@include "evx.sinc" +@include "SPEF_SCR.sinc" +@include "SPE_EFSD.sinc" +@include "SPE_EFV.sinc" +# OR +#@include "altivec.sinc" + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_isa_vle_be.slaspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_isa_vle_be.slaspec new file mode 100644 index 0000000..8a81dc5 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_isa_vle_be.slaspec @@ -0,0 +1,34 @@ +# SLA specification file for Power ISA Version 2.06 Revision B (July 23, 2010) +# ISA (Instruction Set Architecture) a trademarked name for PowerPC specifications from IBM. + +@define ENDIAN "big" + +@define IS_ISA "1" +@define NoLegacyIntegerMultiplyAccumulate "1" + +@define REGISTER_SIZE "8" +@define BIT_64 "64" + +@define EATRUNC "ea" + +@define CTR_OFFSET "32" + +@include "ppc_common.sinc" +@include "ppc_isa.sinc" + +@include "quicciii.sinc" +@include "FPRC.sinc" + +@include "ppc_vle.sinc" + +# A given processor can be compliant with the PowerISA spec by including EITHER +# the embedded vector instructions (EVX) OR the AltiVec instructions +# However, these instruction sets overlap in their bit patterns, so Sleigh cannot support +# both at the same time. We have two language variants for PowerISA +# that specify which of these two vector specs is supported. +@include "evx.sinc" +@include "SPEF_SCR.sinc" +@include "SPE_EFSD.sinc" +@include "SPE_EFV.sinc" +# OR +#@include "altivec.sinc" diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_le.slaspec b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_le.slaspec new file mode 100644 index 0000000..67e5c1c --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_64_le.slaspec @@ -0,0 +1,11 @@ +# SLA specification file for PowerPC 64-bit little endian + +@define ENDIAN "little" + +@define REGISTER_SIZE "8" +@define BIT_64 "64" +@define EATRUNC "ea:4" + +@include "ppc_common.sinc" +@include "altivec.sinc" +@include "g2.sinc" diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_a2.sinc b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_a2.sinc new file mode 100644 index 0000000..4de9773 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_a2.sinc @@ -0,0 +1,113 @@ + +# binutils: a2.d 88: 00 00 02 00 attn +# binutils: power4_32.d 28: 00 00 02 00 attn +# binutils: power4.d +64: 00 00 02 00 attn +# binutils: power6.d 54: 00 00 02 00 attn +# "attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476, {0} +define pcodeop attnOp; +:attn is $(NOTVLE) & OP=0 & XOP_1_10=256 & BITS_11_25=0 { attnOp(); } + +# binutils: a2.d 214: 7d 4b 01 a6 eratwe r10,r11,0 +# binutils: a2.d 218: 7d 4b 19 a6 eratwe r10,r11,3 +# {"eratwe", X(31,211), X_MASK, PPCA2, PPCNONE, {RS, RA, WS}}, +# WS=> { 0x7, 11, NULL, NULL, 0 }, +define pcodeop eratweOp; +:eratwe S,A is $(NOTVLE) & OP=31 & XOP_1_10=211 & S & A & BITS_11_13 & BITS_14_15 & BIT_0=0 { eratweOp(S,A); } + +# binutils: a2.d 200: 7d 4b 66 66 erativax r10,r11,r12 +# "erativax", X(31,819), X_MASK, PPCA2, PPCNONE, {RS, RA0, RB} +define pcodeop erativaxOp; +:erativax S,A,B is $(NOTVLE) & OP=31 & XOP_1_10=819 & S & A & B { erativaxOp(S,A,B); } + +# binutils: a2.d 1f4: 7c 0a 58 66 eratilx 0,r10,r11 +# binutils: a2.d 1f8: 7c 2a 58 66 eratilx 1,r10,r11 +# binutils: a2.d 1fc: 7c ea 58 66 eratilx 7,r10,r11 +# "eratilx", X(31,51), X_MASK, PPCA2, PPCNONE, {ERAT_T, RA, RB} +define pcodeop eratilxOp; +:eratilx BITS_21_23,A,B is $(NOTVLE) & OP=31 & XOP_1_10=51 & BITS_21_23 & A & B { eratilxOp(A,B); } + +# binutils: a2.d 210: 7d 4b 61 26 eratsx r10,r11,r12 +# "eratsx", XRC(31,147,0), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB} +define pcodeop eratsxOp; +:eratsx TH,A,B is $(NOTVLE) & OP=31 & XOP_1_10=147 & Rc=0 & TH & A & B { eratsxOp(TH,A,B); } + +# binutils: a2.d 20c: 7d 4b 61 27 eratsx\. r10,r11,r12 +# "eratsx.", XRC(31,147,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB} +define pcodeop eratsxXOp; +:eratsx. TH,A,B is $(NOTVLE) & OP=31 & XOP_1_10=147 & Rc=1 & TH & A & B { eratsxXOp(TH,A,B); } + +# "eratre", X(31,179), # binutils: a2.d 204: 7d 4b 01 66 eratre r10,r11,0 +# binutils: a2.d 208: 7d 4b 19 66 eratre r10,r11,3 +define pcodeop eratreOp; +:eratre TH,A,BITS_11_13 is $(NOTVLE) & OP=31 & XOP_1_10=179 & TH & A & BITS_11_13 { eratreOp(TH,A); } + +# binutils: a2.d 3e0: 7d 4b 63 2c icswx r10,r11,r12 +# "icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, PPCNONE, {RS, RA, RB} +define pcodeop icswxOp; +:icswx S,A,B is $(NOTVLE) & OP=31 & XOP_1_10=406 & Rc=0 & S & A & B { icswxOp(S,A,B); } + +# binutils: a2.d 3dc: 7d 4b 63 2d icswx\. r10,r11,r12 +# "icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, PPCNONE, {RS, RA, RB} +define pcodeop icswxDotOp; +:icswx. S,A,B is $(NOTVLE) & OP=31 & XOP_1_10=406 & Rc=1 & S & A & B { icswxDotOp(S,A,B); } + +# binutils: 476.d 49c: 7c 85 02 06 mfdcrx r4,r5 +# binutils: a2.d 520: 7d 4b 02 06 mfdcrx r10,r11 +# binutils: booke.d 28: 7c 85 02 06 mfdcrx r4,r5 +# binutils: booke_xcoff.d 24: 7c 85 02 06 mfdcrx r4,r5 +# "mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {S, A} +define pcodeop mfdcrxOp; +# :mfdcrx S,A is $(NOTVLE) & OP=31 & XOP_1_10=259 & S & A & BITS_11_15=0 { mfdcrxOp(S,A); } + +# binutils: a2.d 51c: 7d 4b 02 07 mfdcrx\. r10,r11 +# "mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA} +define pcodeop mfdcrxDotOp; +:mfdcrx. S,A is $(NOTVLE) & OP=31 & XOP_1_10=259 & Rc=1 & S & A & BITS_11_15=0 { mfdcrxDotOp(S,A); } + +# binutils: a2.d 564: 7d 6a 03 07 mtdcrx\. r10,r11 +define pcodeop mtdcrxDotOp; +:mtdcrx. A,S is $(NOTVLE) & OP=31 & XOP_1_10=387 & A & S & Rc=1 { mtdcrxDotOp(A,S); } + +# binutils: a2.d 884: 7c 00 01 6c wchkall +# binutils: a2.d 888: 7c 00 01 6c wchkall +# binutils: a2.d 88c: 7d 80 01 6c wchkall cr3 +# "wchkall", X(31,182), X_MASK, PPCA2, PPCNONE, {OBF} +define pcodeop wchkallOp; +:wchkall BITS_23_25 is $(NOTVLE) & OP=31 & XOP_1_10=182 & BITS_23_25 { wchkallOp(); } + +# binutils: a2.d 894: 7c 20 07 4c wclrall 1 +# "wclrall", X(31,934), XRARB_MASK, PPCA2, PPCNONE, {L} +define pcodeop wclrallOp; +:wclrall L is $(NOTVLE) & OP=31 & XOP_1_10=934 & L { wclrallOp(); } + +# binutils: a2.d 890: 7c 2a 5f 4c wclr 1,r10,r11 +# "wclr", X(31,934), X_MASK, PPCA2, PPCNONE, {L, RA0, RB} +define pcodeop wclrOp; +# :wclr L,A,B is $(NOTVLE) & OP=31 & XOP_1_10=934 & L & A & B { wclrOp(); } + +@ifdef IS_ISA +# binutils: 476.d 474: 7c 00 06 ac mbar +# binutils: 476.d 47c: 7c 20 06 ac mbar 1 +# "mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, PPCNONE, {MO} +define pcodeop mbarOp; +:mbar MO is OP=31 & XOP_1_10=854 & MO { mbarOp(); } +@endif + +# binutils: a2.d: 514: 7d 4a 3a 87 mfdcr\. r10,234 +:mfdcr. D, DCRN is $(NOTVLE) & OP=31 & D & DCRN & XOP_1_10=323 & BIT_0=1 +{ + D = DCRN; +} + +# binutils: a2.d: 55c: 7d 4a 3b 87 mtdcr\. 234,r10 +:mtdcr. DCRN, D is $(NOTVLE) & OP=31 & D & DCRN & XOP_1_10=451 & BIT_0=1 +{ + DCRN = D; +} + +# binutils: a2.d: 188: 7d 4b 61 fe dcbtstep r10,r11,r12 +# binutils: e500mc.d: a0: 7c 64 29 fe dcbtstep r3,r4,r5 +define pcodeop DataCacheBlockTouchForStoreByExternalPID; +:dcbtstep TH,A,B is OP=31 & TH & A & B & XOP_1_10=255 & BIT_0=0 { + DataCacheBlockTouchForStoreByExternalPID(TH,A,B); +} diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc new file mode 100644 index 0000000..aaa76cc --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc @@ -0,0 +1,2015 @@ +# PowerPC assembly SLA spec (size agnostic) + +# version 1.0 + +define endian=$(ENDIAN); + +define alignment=2; + +# -size: How many bytes make up an address +define space ram type=ram_space size=$(REGISTER_SIZE) default; + +# -size: How many bytes do we need for register addressing +define space register type=register_space size=4; + +# General registers (some pcode that follows depends on these registers being at +# offset 0 + +define register offset=0 size=$(REGISTER_SIZE) [ + r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 + r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 ]; + +@ifdef E500 +# Define 4-byte general purpose sub-registers (LSB) to be used by E500 compiler specification +# which must restrict parameter/return passing to low 4-bytes of the 8-byte general purpose registers. +@if ENDIAN == "big" +define register offset=0 size=4 [ + _ _r0 _ _r1 _ _r2 _ _r3 _ _r4 _ _r5 _ _r6 _ _r7 + _ _r8 _ _r9 _ _r10 _ _r11 _ _r12 _ _r13 _ _r14 _ _r15 + _ _r16 _ _r17 _ _r18 _ _r19 _ _r20 _ _r21 _ _r22 _ _r23 + _ _r24 _ _r25 _ _r26 _ _r27 _ _r28 _ _r29 _ _r30 _ _r31 ]; +@else +define register offset=0 size=4 [ + _r0 _ _r1 _ _r2 _ _r3 _ _r4 _ _r5 _ _r6 _ _r7 _ + _r8 _ _r9 _ _r10 _ _r11 _ _r12 _ _r13 _ _r14 _ _r15 _ + _r16 _ _r17 _ _r18 _ _r19 _ _r20 _ _r21 _ _r22 _ _r23 _ + _r24 _ _r25 _ _r26 _ _r27 _ _r28 _ _r29 _ _r30 _ _r31 _ ]; +@endif +@endif + +# XER flags +define register offset=0x400 size=1 [ xer_so xer_ov xer_ov32 xer_ca xer_ca32 xer_count ]; + +define register offset=0x500 size=1 [ fp_fx fp_fex fp_vx fp_ox + fp_ux fp_zx fp_xx fp_vxsnan + fp_vxisi fp_vxidi fp_vxzdz fp_vximz + fp_vxvc fp_fr fp_fi fp_c + fp_cc0 fp_cc1 fp_cc2 fp_cc3 + fp_reserve1 fp_vxsoft fp_vxsqrt fp_vxcvi + fp_ve fp_oe fp_ue fp_ze + fp_xe fp_ni fp_rn0 fp_rn1 ]; + +define register offset = 0x700 size =$(REGISTER_SIZE) [MSR]; +define register offset = 0x720 size=$(REGISTER_SIZE) [RESERVE_ADDRESS]; +define register offset = 0x728 size=1 [RESERVE]; +define register offset = 0x730 size=1 [RESERVE_LENGTH]; + +# Program Counter register: This register is not actually visible in the +# API for powerpc but it is needed to create a consistent model for the debugger +define register offset=0x780 size=$(REGISTER_SIZE) pc; + +@define SEG_REGISTER_BASE "0x800" +# Segment Registers +define register offset=$(SEG_REGISTER_BASE) size=4 [ sr0 sr1 sr2 sr3 sr4 sr5 sr6 sr7 sr8 sr9 sr10 sr11 sr12 sr13 sr14 sr15 ]; + +# Condition register flags +define register offset=0x900 size=1 [ cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 ]; +define register offset=0x900 size=8 [ crall ]; + +define register offset=0x980 size=$(REGISTER_SIZE) [ tea ]; + +# Fake storage used to help preserve r2 across function calls within the decompiler (see appropriate cspec) +define register offset=0x988 size=$(REGISTER_SIZE) [ r2Save ]; + +# Special Purpose Registers are defined with generic names with the exception of XER, LR, CTR, SRR0, SRR1, TBL(r/w), TBU(r/w) +# These names may be replaced within register_data section within a PPC variant's pspec file +define register offset=0x1000 size=$(REGISTER_SIZE) + [ spr000 XER spr002 spr003 spr004 spr005 spr006 spr007 LR CTR spr00a spr00b spr00c spr00d spr00e spr00f + spr010 spr011 spr012 spr013 spr014 spr015 spr016 spr017 spr018 spr019 SRR0 SRR1 spr01c spr01d spr01e spr01f + spr020 spr021 spr022 spr023 spr024 spr025 spr026 spr027 spr028 spr029 spr02a spr02b spr02c spr02d spr02e spr02f + spr030 spr031 spr032 spr033 spr034 spr035 spr036 spr037 spr038 spr039 CSRR0 CSRR1 spr03c spr03d spr03e spr03f + spr040 spr041 spr042 spr043 spr044 spr045 spr046 spr047 spr048 spr049 spr04a spr04b spr04c spr04d spr04e spr04f + spr050 spr051 spr052 spr053 spr054 spr055 spr056 spr057 spr058 spr059 spr05a spr05b spr05c spr05d spr05e spr05f + spr060 spr061 spr062 spr063 spr064 spr065 spr066 spr067 spr068 spr069 spr06a spr06b spr06c spr06d spr06e spr06f + spr070 spr071 spr072 spr073 spr074 spr075 spr076 spr077 spr078 spr079 spr07a spr07b spr07c spr07d spr07e spr07f + spr080 spr081 spr082 spr083 spr084 spr085 spr086 spr087 spr088 spr089 spr08a spr08b spr08c spr08d spr08e spr08f + spr090 spr091 spr092 spr093 spr094 spr095 spr096 spr097 spr098 spr099 spr09a spr09b spr09c spr09d spr09e spr09f + spr0a0 spr0a1 spr0a2 spr0a3 spr0a4 spr0a5 spr0a6 spr0a7 spr0a8 spr0a9 spr0aa spr0ab spr0ac spr0ad spr0ae spr0af + spr0b0 spr0b1 spr0b2 spr0b3 spr0b4 spr0b5 spr0b6 spr0b7 spr0b8 spr0b9 spr0ba spr0bb spr0bc spr0bd spr0be spr0bf + spr0c0 spr0c1 spr0c2 spr0c3 spr0c4 spr0c5 spr0c6 spr0c7 spr0c8 spr0c9 spr0ca spr0cb spr0cc spr0cd spr0ce spr0cf + spr0d0 spr0d1 spr0d2 spr0d3 spr0d4 spr0d5 spr0d6 spr0d7 spr0d8 spr0d9 spr0da spr0db spr0dc spr0dd spr0de spr0df + spr0e0 spr0e1 spr0e2 spr0e3 spr0e4 spr0e5 spr0e6 spr0e7 spr0e8 spr0e9 spr0ea spr0eb spr0ec spr0ed spr0ee spr0ef + spr0f0 spr0f1 spr0f2 spr0f3 spr0f4 spr0f5 spr0f6 spr0f7 spr0f8 spr0f9 spr0fa spr0fb spr0fc spr0fd spr0fe spr0ff + spr100 spr101 spr102 spr103 spr104 spr105 spr106 spr107 spr108 spr109 spr10a spr10b TBLr TBUr spr10e spr10f + spr110 spr111 spr112 spr113 spr114 spr115 spr116 spr117 spr118 spr119 spr11a spr11b TBLw TBUw spr11e spr11f + spr120 spr121 spr122 spr123 spr124 spr125 spr126 spr127 spr128 spr129 spr12a spr12b spr12c spr12d spr12e spr12f + spr130 spr131 spr132 spr133 spr134 spr135 spr136 spr137 spr138 spr139 spr13a spr13b spr13c spr13d spr13e spr13f + spr140 spr141 spr142 spr143 spr144 spr145 spr146 spr147 spr148 spr149 spr14a spr14b spr14c spr14d spr14e spr14f + spr150 spr151 spr152 spr153 spr154 spr155 spr156 spr157 spr158 spr159 spr15a spr15b spr15c spr15d spr15e spr15f + spr160 spr161 spr162 spr163 spr164 spr165 spr166 spr167 spr168 spr169 spr16a spr16b spr16c spr16d spr16e spr16f + spr170 spr171 spr172 spr173 spr174 spr175 spr176 spr177 spr178 spr179 spr17a spr17b spr17c spr17d spr17e spr17f + spr180 spr181 spr182 spr183 spr184 spr185 spr186 spr187 spr188 spr189 spr18a spr18b spr18c spr18d spr18e spr18f + spr190 spr191 spr192 spr193 spr194 spr195 spr196 spr197 spr198 spr199 spr19a spr19b spr19c spr19d spr19e spr19f + spr1a0 spr1a1 spr1a2 spr1a3 spr1a4 spr1a5 spr1a6 spr1a7 spr1a8 spr1a9 spr1aa spr1ab spr1ac spr1ad spr1ae spr1af + spr1b0 spr1b1 spr1b2 spr1b3 spr1b4 spr1b5 spr1b6 spr1b7 spr1b8 spr1b9 spr1ba spr1bb spr1bc spr1bd spr1be spr1bf + spr1c0 spr1c1 spr1c2 spr1c3 spr1c4 spr1c5 spr1c6 spr1c7 spr1c8 spr1c9 spr1ca spr1cb spr1cc spr1cd spr1ce spr1cf + spr1d0 spr1d1 spr1d2 spr1d3 spr1d4 spr1d5 spr1d6 spr1d7 spr1d8 spr1d9 spr1da spr1db spr1dc spr1dd spr1de spr1df + spr1e0 spr1e1 spr1e2 spr1e3 spr1e4 spr1e5 spr1e6 spr1e7 spr1e8 spr1e9 spr1ea spr1eb spr1ec spr1ed spr1ee spr1ef + spr1f0 spr1f1 spr1f2 spr1f3 spr1f4 spr1f5 spr1f6 spr1f7 spr1f8 spr1f9 spr1fa spr1fb spr1fc spr1fd spr1fe spr1ff + spr200 spr201 spr202 spr203 spr204 spr205 spr206 spr207 spr208 spr209 spr20a spr20b spr20c spr20d spr20e spr20f + spr210 spr211 spr212 spr213 spr214 spr215 spr216 spr217 spr218 spr219 spr21a spr21b spr21c spr21d spr21e spr21f + spr220 spr221 spr222 spr223 spr224 spr225 spr226 spr227 spr228 spr229 spr22a spr22b spr22c spr22d spr22e spr22f + spr230 spr231 spr232 spr233 spr234 spr235 spr236 spr237 spr238 spr239 spr23a spr23b spr23c spr23d spr23e spr23f + spr240 spr241 spr242 spr243 spr244 spr245 spr246 spr247 spr248 spr249 spr24a spr24b spr24c spr24d spr24e spr24f + spr250 spr251 spr252 spr253 spr254 spr255 spr256 spr257 spr258 spr259 spr25a spr25b spr25c spr25d spr25e spr25f + spr260 spr261 spr262 spr263 spr264 spr265 spr266 spr267 spr268 spr269 spr26a spr26b spr26c spr26d spr26e spr26f + spr270 spr271 spr272 spr273 spr274 spr275 spr276 spr277 spr278 spr279 spr27a spr27b spr27c spr27d spr27e spr27f + spr280 spr281 spr282 spr283 spr284 spr285 spr286 spr287 spr288 spr289 spr28a spr28b spr28c spr28d spr28e spr28f + spr290 spr291 spr292 spr293 spr294 spr295 spr296 spr297 spr298 spr299 spr29a spr29b spr29c spr29d spr29e spr29f + spr2a0 spr2a1 spr2a2 spr2a3 spr2a4 spr2a5 spr2a6 spr2a7 spr2a8 spr2a9 spr2aa spr2ab spr2ac spr2ad spr2ae spr2af + spr2b0 spr2b1 spr2b2 spr2b3 spr2b4 spr2b5 spr2b6 spr2b7 spr2b8 spr2b9 spr2ba spr2bb spr2bc spr2bd spr2be spr2bf + spr2c0 spr2c1 spr2c2 spr2c3 spr2c4 spr2c5 spr2c6 spr2c7 spr2c8 spr2c9 spr2ca spr2cb spr2cc spr2cd spr2ce spr2cf + spr2d0 spr2d1 spr2d2 spr2d3 spr2d4 spr2d5 spr2d6 spr2d7 spr2d8 spr2d9 spr2da spr2db spr2dc spr2dd spr2de spr2df + spr2e0 spr2e1 spr2e2 spr2e3 spr2e4 spr2e5 spr2e6 spr2e7 spr2e8 spr2e9 spr2ea spr2eb spr2ec spr2ed spr2ee spr2ef + spr2f0 spr2f1 spr2f2 spr2f3 spr2f4 spr2f5 spr2f6 spr2f7 spr2f8 spr2f9 spr2fa spr2fb spr2fc spr2fd spr2fe spr2ff + spr300 spr301 spr302 spr303 spr304 spr305 spr306 spr307 spr308 spr309 spr30a spr30b spr30c spr30d spr30e spr30f + spr310 spr311 spr312 spr313 spr314 spr315 spr316 spr317 spr318 spr319 spr31a spr31b spr31c spr31d spr31e spr31f + spr320 spr321 spr322 spr323 spr324 spr325 spr326 spr327 spr328 spr329 spr32a spr32b spr32c spr32d spr32e TAR + spr330 spr331 spr332 spr333 spr334 spr335 spr336 spr337 spr338 spr339 spr33a spr33b spr33c spr33d spr33e spr33f + spr340 spr341 spr342 spr343 spr344 spr345 spr346 spr347 spr348 spr349 spr34a spr34b spr34c spr34d spr34e spr34f + spr350 spr351 spr352 spr353 spr354 spr355 spr356 spr357 spr358 spr359 spr35a spr35b spr35c spr35d spr35e spr35f + spr360 spr361 spr362 spr363 spr364 spr365 spr366 spr367 spr368 spr369 spr36a spr36b spr36c spr36d spr36e spr36f + spr370 spr371 spr372 spr373 spr374 spr375 spr376 spr377 spr378 spr379 spr37a spr37b spr37c spr37d spr37e spr37f + spr380 spr381 spr382 spr383 spr384 spr385 spr386 spr387 spr388 spr389 spr38a spr38b spr38c spr38d spr38e spr38f + spr390 spr391 spr392 spr393 spr394 spr395 spr396 spr397 spr398 spr399 spr39a spr39b spr39c spr39d spr39e spr39f + spr3a0 spr3a1 spr3a2 spr3a3 spr3a4 spr3a5 spr3a6 spr3a7 spr3a8 spr3a9 spr3aa spr3ab spr3ac spr3ad spr3ae spr3af + spr3b0 spr3b1 spr3b2 spr3b3 spr3b4 spr3b5 spr3b6 spr3b7 spr3b8 spr3b9 spr3ba spr3bb spr3bc spr3bd spr3be spr3bf + spr3c0 spr3c1 spr3c2 spr3c3 spr3c4 spr3c5 spr3c6 spr3c7 spr3c8 spr3c9 spr3ca spr3cb spr3cc spr3cd spr3ce spr3cf + spr3d0 spr3d1 spr3d2 spr3d3 spr3d4 spr3d5 spr3d6 spr3d7 spr3d8 spr3d9 spr3da spr3db spr3dc spr3dd spr3de spr3df + spr3e0 spr3e1 spr3e2 spr3e3 spr3e4 spr3e5 spr3e6 spr3e7 spr3e8 spr3e9 spr3ea spr3eb spr3ec spr3ed spr3ee spr3ef + spr3f0 spr3f1 spr3f2 spr3f3 spr3f4 spr3f5 spr3f6 spr3f7 spr3f8 spr3f9 spr3fa spr3fb spr3fc spr3fd spr3fe spr3ff + ]; + + +# The floating point registers and the altivec vector registers OVERLAP to VSX registers +# This was not done correctly before and has now been fixed. Book 1, Chapter 7.2 has a +# very good diagram. + +# Support for Vector-Scalar Extension - i.e "VSX" + +define register offset=0x4000 size=16 + [ vs0 vs1 vs2 vs3 vs4 vs5 vs6 vs7 vs8 vs9 vs10 vs11 vs12 vs13 vs14 vs15 + vs16 vs17 vs18 vs19 vs20 vs21 vs22 vs23 vs24 vs25 vs26 vs27 vs28 vs29 vs30 vs31 + vs32 vs33 vs34 vs35 vs36 vs37 vs38 vs39 vs40 vs41 vs42 vs43 vs44 vs45 vs46 vs47 + vs48 vs49 vs50 vs51 vs52 vs53 vs54 vs55 vs56 vs57 vs58 vs59 vs60 vs61 vs62 vs63 + ]; +# Floating point registers +# These overlay the first 32 vsx regs with the gaps as indicated so fr0 is in vs0, fr1 is in vs1, etc. +# This also means we have to have 2 defs of this due to endian stuff. +@if ENDIAN == "big" +define register offset=0x4000 size=8 [ + f0 _ f1 _ f2 _ f3 _ f4 _ f5 _ f6 _ f7 _ f8 _ f9 _ f10 _ f11 _ f12 _ f13 _ f14 _ f15 _ + f16 _ f17 _ f18 _ f19 _ f20 _ f21 _ f22 _ f23 _ f24 _ f25 _ f26 _ f27 _ f28 _ f29 _ f30 _ f31 _ ]; + +@else +define register offset=0x4000 size=8 [ + _ f0 _ f1 _ f2 _ f3 _ f4 _ f5 _ f6 _ f7 _ f8 _ f9 _ f10 _ f11 _ f12 _ f13 _ f14 _ f15 + _ f16 _ f17 _ f18 _ f19 _ f20 _ f21 _ f22 _ f23 _ f24 _ f25 _ f26 _ f27 _ f28 _ f29 _ f30 _ f31 ]; +@endif + +# All the altivec regs need to start at offset 0x4200 +# Sleigh does not allow registers of the same size to overlay. This presents some issues as the normal +# Altivec registers overlay the top 32 VSX registers. What we have to do is use a sub-table to display +# the Altivec name, but export the matching VSX register. The original vrD, etc. tokens are now sub-tables. + +# Altivec vector registers (accessed by vrD vrA vrB vrS vrC) +# Altivec vector registers +#define register offset=0x4200 size=16 [ +# v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 +# v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 ]; + +@if ENDIAN == "big" + +# Create psydo sub-registers for the Altivec vector registers to allow better easier vector instructions by 8 byte subregisters +define register offset=0x4200 size=8 [ # 64 bit access to vrN registers (psydo-registers) (accessed by vrD_64_N vrA_64_N vrB_64_N vrS_64_N vrC_64_N) +vr0_64_0 vr0_64_1 +vr1_64_0 vr1_64_1 +vr2_64_0 vr2_64_1 +vr3_64_0 vr3_64_1 +vr4_64_0 vr4_64_1 +vr5_64_0 vr5_64_1 +vr6_64_0 vr6_64_1 +vr7_64_0 vr7_64_1 +vr8_64_0 vr8_64_1 +vr9_64_0 vr9_64_1 +vr10_64_0 vr10_64_1 +vr11_64_0 vr11_64_1 +vr12_64_0 vr12_64_1 +vr13_64_0 vr13_64_1 +vr14_64_0 vr14_64_1 +vr15_64_0 vr15_64_1 +vr16_64_0 vr16_64_1 +vr17_64_0 vr17_64_1 +vr18_64_0 vr18_64_1 +vr19_64_0 vr19_64_1 +vr20_64_0 vr20_64_1 +vr21_64_0 vr21_64_1 +vr22_64_0 vr22_64_1 +vr23_64_0 vr23_64_1 +vr24_64_0 vr24_64_1 +vr25_64_0 vr25_64_1 +vr26_64_0 vr26_64_1 +vr27_64_0 vr27_64_1 +vr28_64_0 vr28_64_1 +vr29_64_0 vr29_64_1 +vr30_64_0 vr30_64_1 +vr31_64_0 vr31_64_1 +]; + +# Create psydo sub-registers for the Altivec vector registers to allow better easier vector instructions by 4 byte subregisters +define register offset=0x4200 size=4 [ # 32 bit access to vrN registers (psydo-registers) (accessed by vrD_32_N vrA_32_N vrB_32_N vrS_32_N vrC_32_N) +vr0_32_0 vr0_32_1 vr0_32_2 vr0_32_3 +vr1_32_0 vr1_32_1 vr1_32_2 vr1_32_3 +vr2_32_0 vr2_32_1 vr2_32_2 vr2_32_3 +vr3_32_0 vr3_32_1 vr3_32_2 vr3_32_3 +vr4_32_0 vr4_32_1 vr4_32_2 vr4_32_3 +vr5_32_0 vr5_32_1 vr5_32_2 vr5_32_3 +vr6_32_0 vr6_32_1 vr6_32_2 vr6_32_3 +vr7_32_0 vr7_32_1 vr7_32_2 vr7_32_3 +vr8_32_0 vr8_32_1 vr8_32_2 vr8_32_3 +vr9_32_0 vr9_32_1 vr9_32_2 vr9_32_3 +vr10_32_0 vr10_32_1 vr10_32_2 vr10_32_3 +vr11_32_0 vr11_32_1 vr11_32_2 vr11_32_3 +vr12_32_0 vr12_32_1 vr12_32_2 vr12_32_3 +vr13_32_0 vr13_32_1 vr13_32_2 vr13_32_3 +vr14_32_0 vr14_32_1 vr14_32_2 vr14_32_3 +vr15_32_0 vr15_32_1 vr15_32_2 vr15_32_3 +vr16_32_0 vr16_32_1 vr16_32_2 vr16_32_3 +vr17_32_0 vr17_32_1 vr17_32_2 vr17_32_3 +vr18_32_0 vr18_32_1 vr18_32_2 vr18_32_3 +vr19_32_0 vr19_32_1 vr19_32_2 vr19_32_3 +vr20_32_0 vr20_32_1 vr20_32_2 vr20_32_3 +vr21_32_0 vr21_32_1 vr21_32_2 vr21_32_3 +vr22_32_0 vr22_32_1 vr22_32_2 vr22_32_3 +vr23_32_0 vr23_32_1 vr23_32_2 vr23_32_3 +vr24_32_0 vr24_32_1 vr24_32_2 vr24_32_3 +vr25_32_0 vr25_32_1 vr25_32_2 vr25_32_3 +vr26_32_0 vr26_32_1 vr26_32_2 vr26_32_3 +vr27_32_0 vr27_32_1 vr27_32_2 vr27_32_3 +vr28_32_0 vr28_32_1 vr28_32_2 vr28_32_3 +vr29_32_0 vr29_32_1 vr29_32_2 vr29_32_3 +vr30_32_0 vr30_32_1 vr30_32_2 vr30_32_3 +vr31_32_0 vr31_32_1 vr31_32_2 vr31_32_3 +]; + +# Create psydo sub-registers for the Altivec vector registers to allow better easier vector instructions by 2 byte subregisters +define register offset=0x4200 size=2 [ # 16 bit access to vrN registers (psydo-registers) (accessed by vrD_16_N vrA_16_N vrB_16_N vrS_16_N vrC_16_N) +vr0_16_0 vr0_16_1 vr0_16_2 vr0_16_3 vr0_16_4 vr0_16_5 vr0_16_6 vr0_16_7 +vr1_16_0 vr1_16_1 vr1_16_2 vr1_16_3 vr1_16_4 vr1_16_5 vr1_16_6 vr1_16_7 +vr2_16_0 vr2_16_1 vr2_16_2 vr2_16_3 vr2_16_4 vr2_16_5 vr2_16_6 vr2_16_7 +vr3_16_0 vr3_16_1 vr3_16_2 vr3_16_3 vr3_16_4 vr3_16_5 vr3_16_6 vr3_16_7 +vr4_16_0 vr4_16_1 vr4_16_2 vr4_16_3 vr4_16_4 vr4_16_5 vr4_16_6 vr4_16_7 +vr5_16_0 vr5_16_1 vr5_16_2 vr5_16_3 vr5_16_4 vr5_16_5 vr5_16_6 vr5_16_7 +vr6_16_0 vr6_16_1 vr6_16_2 vr6_16_3 vr6_16_4 vr6_16_5 vr6_16_6 vr6_16_7 +vr7_16_0 vr7_16_1 vr7_16_2 vr7_16_3 vr7_16_4 vr7_16_5 vr7_16_6 vr7_16_7 +vr8_16_0 vr8_16_1 vr8_16_2 vr8_16_3 vr8_16_4 vr8_16_5 vr8_16_6 vr8_16_7 +vr9_16_0 vr9_16_1 vr9_16_2 vr9_16_3 vr9_16_4 vr9_16_5 vr9_16_6 vr9_16_7 +vr10_16_0 vr10_16_1 vr10_16_2 vr10_16_3 vr10_16_4 vr10_16_5 vr10_16_6 vr10_16_7 +vr11_16_0 vr11_16_1 vr11_16_2 vr11_16_3 vr11_16_4 vr11_16_5 vr11_16_6 vr11_16_7 +vr12_16_0 vr12_16_1 vr12_16_2 vr12_16_3 vr12_16_4 vr12_16_5 vr12_16_6 vr12_16_7 +vr13_16_0 vr13_16_1 vr13_16_2 vr13_16_3 vr13_16_4 vr13_16_5 vr13_16_6 vr13_16_7 +vr14_16_0 vr14_16_1 vr14_16_2 vr14_16_3 vr14_16_4 vr14_16_5 vr14_16_6 vr14_16_7 +vr15_16_0 vr15_16_1 vr15_16_2 vr15_16_3 vr15_16_4 vr15_16_5 vr15_16_6 vr15_16_7 +vr16_16_0 vr16_16_1 vr16_16_2 vr16_16_3 vr16_16_4 vr16_16_5 vr16_16_6 vr16_16_7 +vr17_16_0 vr17_16_1 vr17_16_2 vr17_16_3 vr17_16_4 vr17_16_5 vr17_16_6 vr17_16_7 +vr18_16_0 vr18_16_1 vr18_16_2 vr18_16_3 vr18_16_4 vr18_16_5 vr18_16_6 vr18_16_7 +vr19_16_0 vr19_16_1 vr19_16_2 vr19_16_3 vr19_16_4 vr19_16_5 vr19_16_6 vr19_16_7 +vr20_16_0 vr20_16_1 vr20_16_2 vr20_16_3 vr20_16_4 vr20_16_5 vr20_16_6 vr20_16_7 +vr21_16_0 vr21_16_1 vr21_16_2 vr21_16_3 vr21_16_4 vr21_16_5 vr21_16_6 vr21_16_7 +vr22_16_0 vr22_16_1 vr22_16_2 vr22_16_3 vr22_16_4 vr22_16_5 vr22_16_6 vr22_16_7 +vr23_16_0 vr23_16_1 vr23_16_2 vr23_16_3 vr23_16_4 vr23_16_5 vr23_16_6 vr23_16_7 +vr24_16_0 vr24_16_1 vr24_16_2 vr24_16_3 vr24_16_4 vr24_16_5 vr24_16_6 vr24_16_7 +vr25_16_0 vr25_16_1 vr25_16_2 vr25_16_3 vr25_16_4 vr25_16_5 vr25_16_6 vr25_16_7 +vr26_16_0 vr26_16_1 vr26_16_2 vr26_16_3 vr26_16_4 vr26_16_5 vr26_16_6 vr26_16_7 +vr27_16_0 vr27_16_1 vr27_16_2 vr27_16_3 vr27_16_4 vr27_16_5 vr27_16_6 vr27_16_7 +vr28_16_0 vr28_16_1 vr28_16_2 vr28_16_3 vr28_16_4 vr28_16_5 vr28_16_6 vr28_16_7 +vr29_16_0 vr29_16_1 vr29_16_2 vr29_16_3 vr29_16_4 vr29_16_5 vr29_16_6 vr29_16_7 +vr30_16_0 vr30_16_1 vr30_16_2 vr30_16_3 vr30_16_4 vr30_16_5 vr30_16_6 vr30_16_7 +vr31_16_0 vr31_16_1 vr31_16_2 vr31_16_3 vr31_16_4 vr31_16_5 vr31_16_6 vr31_16_7 +]; + +# Create psydo sub-registers for the Altivec vector registers to allow better easier vector instructions by 1 byte subregisters +define register offset=0x4200 size=1 [ # 8 bit access to vrN registers (psydo-registers) (accessed by vrD_8_N vrA_8_N vrB_8_N vrS_8_N vrC_8_N) +vr0_8_0 vr0_8_1 vr0_8_2 vr0_8_3 vr0_8_4 vr0_8_5 vr0_8_6 vr0_8_7 vr0_8_8 vr0_8_9 vr0_8_10 vr0_8_11 vr0_8_12 vr0_8_13 vr0_8_14 vr0_8_15 +vr1_8_0 vr1_8_1 vr1_8_2 vr1_8_3 vr1_8_4 vr1_8_5 vr1_8_6 vr1_8_7 vr1_8_8 vr1_8_9 vr1_8_10 vr1_8_11 vr1_8_12 vr1_8_13 vr1_8_14 vr1_8_15 +vr2_8_0 vr2_8_1 vr2_8_2 vr2_8_3 vr2_8_4 vr2_8_5 vr2_8_6 vr2_8_7 vr2_8_8 vr2_8_9 vr2_8_10 vr2_8_11 vr2_8_12 vr2_8_13 vr2_8_14 vr2_8_15 +vr3_8_0 vr3_8_1 vr3_8_2 vr3_8_3 vr3_8_4 vr3_8_5 vr3_8_6 vr3_8_7 vr3_8_8 vr3_8_9 vr3_8_10 vr3_8_11 vr3_8_12 vr3_8_13 vr3_8_14 vr3_8_15 +vr4_8_0 vr4_8_1 vr4_8_2 vr4_8_3 vr4_8_4 vr4_8_5 vr4_8_6 vr4_8_7 vr4_8_8 vr4_8_9 vr4_8_10 vr4_8_11 vr4_8_12 vr4_8_13 vr4_8_14 vr4_8_15 +vr5_8_0 vr5_8_1 vr5_8_2 vr5_8_3 vr5_8_4 vr5_8_5 vr5_8_6 vr5_8_7 vr5_8_8 vr5_8_9 vr5_8_10 vr5_8_11 vr5_8_12 vr5_8_13 vr5_8_14 vr5_8_15 +vr6_8_0 vr6_8_1 vr6_8_2 vr6_8_3 vr6_8_4 vr6_8_5 vr6_8_6 vr6_8_7 vr6_8_8 vr6_8_9 vr6_8_10 vr6_8_11 vr6_8_12 vr6_8_13 vr6_8_14 vr6_8_15 +vr7_8_0 vr7_8_1 vr7_8_2 vr7_8_3 vr7_8_4 vr7_8_5 vr7_8_6 vr7_8_7 vr7_8_8 vr7_8_9 vr7_8_10 vr7_8_11 vr7_8_12 vr7_8_13 vr7_8_14 vr7_8_15 +vr8_8_0 vr8_8_1 vr8_8_2 vr8_8_3 vr8_8_4 vr8_8_5 vr8_8_6 vr8_8_7 vr8_8_8 vr8_8_9 vr8_8_10 vr8_8_11 vr8_8_12 vr8_8_13 vr8_8_14 vr8_8_15 +vr9_8_0 vr9_8_1 vr9_8_2 vr9_8_3 vr9_8_4 vr9_8_5 vr9_8_6 vr9_8_7 vr9_8_8 vr9_8_9 vr9_8_10 vr9_8_11 vr9_8_12 vr9_8_13 vr9_8_14 vr9_8_15 +vr10_8_0 vr10_8_1 vr10_8_2 vr10_8_3 vr10_8_4 vr10_8_5 vr10_8_6 vr10_8_7 vr10_8_8 vr10_8_9 vr10_8_10 vr10_8_11 vr10_8_12 vr10_8_13 vr10_8_14 vr10_8_15 +vr11_8_0 vr11_8_1 vr11_8_2 vr11_8_3 vr11_8_4 vr11_8_5 vr11_8_6 vr11_8_7 vr11_8_8 vr11_8_9 vr11_8_10 vr11_8_11 vr11_8_12 vr11_8_13 vr11_8_14 vr11_8_15 +vr12_8_0 vr12_8_1 vr12_8_2 vr12_8_3 vr12_8_4 vr12_8_5 vr12_8_6 vr12_8_7 vr12_8_8 vr12_8_9 vr12_8_10 vr12_8_11 vr12_8_12 vr12_8_13 vr12_8_14 vr12_8_15 +vr13_8_0 vr13_8_1 vr13_8_2 vr13_8_3 vr13_8_4 vr13_8_5 vr13_8_6 vr13_8_7 vr13_8_8 vr13_8_9 vr13_8_10 vr13_8_11 vr13_8_12 vr13_8_13 vr13_8_14 vr13_8_15 +vr14_8_0 vr14_8_1 vr14_8_2 vr14_8_3 vr14_8_4 vr14_8_5 vr14_8_6 vr14_8_7 vr14_8_8 vr14_8_9 vr14_8_10 vr14_8_11 vr14_8_12 vr14_8_13 vr14_8_14 vr14_8_15 +vr15_8_0 vr15_8_1 vr15_8_2 vr15_8_3 vr15_8_4 vr15_8_5 vr15_8_6 vr15_8_7 vr15_8_8 vr15_8_9 vr15_8_10 vr15_8_11 vr15_8_12 vr15_8_13 vr15_8_14 vr15_8_15 +vr16_8_0 vr16_8_1 vr16_8_2 vr16_8_3 vr16_8_4 vr16_8_5 vr16_8_6 vr16_8_7 vr16_8_8 vr16_8_9 vr16_8_10 vr16_8_11 vr16_8_12 vr16_8_13 vr16_8_14 vr16_8_15 +vr17_8_0 vr17_8_1 vr17_8_2 vr17_8_3 vr17_8_4 vr17_8_5 vr17_8_6 vr17_8_7 vr17_8_8 vr17_8_9 vr17_8_10 vr17_8_11 vr17_8_12 vr17_8_13 vr17_8_14 vr17_8_15 +vr18_8_0 vr18_8_1 vr18_8_2 vr18_8_3 vr18_8_4 vr18_8_5 vr18_8_6 vr18_8_7 vr18_8_8 vr18_8_9 vr18_8_10 vr18_8_11 vr18_8_12 vr18_8_13 vr18_8_14 vr18_8_15 +vr19_8_0 vr19_8_1 vr19_8_2 vr19_8_3 vr19_8_4 vr19_8_5 vr19_8_6 vr19_8_7 vr19_8_8 vr19_8_9 vr19_8_10 vr19_8_11 vr19_8_12 vr19_8_13 vr19_8_14 vr19_8_15 +vr20_8_0 vr20_8_1 vr20_8_2 vr20_8_3 vr20_8_4 vr20_8_5 vr20_8_6 vr20_8_7 vr20_8_8 vr20_8_9 vr20_8_10 vr20_8_11 vr20_8_12 vr20_8_13 vr20_8_14 vr20_8_15 +vr21_8_0 vr21_8_1 vr21_8_2 vr21_8_3 vr21_8_4 vr21_8_5 vr21_8_6 vr21_8_7 vr21_8_8 vr21_8_9 vr21_8_10 vr21_8_11 vr21_8_12 vr21_8_13 vr21_8_14 vr21_8_15 +vr22_8_0 vr22_8_1 vr22_8_2 vr22_8_3 vr22_8_4 vr22_8_5 vr22_8_6 vr22_8_7 vr22_8_8 vr22_8_9 vr22_8_10 vr22_8_11 vr22_8_12 vr22_8_13 vr22_8_14 vr22_8_15 +vr23_8_0 vr23_8_1 vr23_8_2 vr23_8_3 vr23_8_4 vr23_8_5 vr23_8_6 vr23_8_7 vr23_8_8 vr23_8_9 vr23_8_10 vr23_8_11 vr23_8_12 vr23_8_13 vr23_8_14 vr23_8_15 +vr24_8_0 vr24_8_1 vr24_8_2 vr24_8_3 vr24_8_4 vr24_8_5 vr24_8_6 vr24_8_7 vr24_8_8 vr24_8_9 vr24_8_10 vr24_8_11 vr24_8_12 vr24_8_13 vr24_8_14 vr24_8_15 +vr25_8_0 vr25_8_1 vr25_8_2 vr25_8_3 vr25_8_4 vr25_8_5 vr25_8_6 vr25_8_7 vr25_8_8 vr25_8_9 vr25_8_10 vr25_8_11 vr25_8_12 vr25_8_13 vr25_8_14 vr25_8_15 +vr26_8_0 vr26_8_1 vr26_8_2 vr26_8_3 vr26_8_4 vr26_8_5 vr26_8_6 vr26_8_7 vr26_8_8 vr26_8_9 vr26_8_10 vr26_8_11 vr26_8_12 vr26_8_13 vr26_8_14 vr26_8_15 +vr27_8_0 vr27_8_1 vr27_8_2 vr27_8_3 vr27_8_4 vr27_8_5 vr27_8_6 vr27_8_7 vr27_8_8 vr27_8_9 vr27_8_10 vr27_8_11 vr27_8_12 vr27_8_13 vr27_8_14 vr27_8_15 +vr28_8_0 vr28_8_1 vr28_8_2 vr28_8_3 vr28_8_4 vr28_8_5 vr28_8_6 vr28_8_7 vr28_8_8 vr28_8_9 vr28_8_10 vr28_8_11 vr28_8_12 vr28_8_13 vr28_8_14 vr28_8_15 +vr29_8_0 vr29_8_1 vr29_8_2 vr29_8_3 vr29_8_4 vr29_8_5 vr29_8_6 vr29_8_7 vr29_8_8 vr29_8_9 vr29_8_10 vr29_8_11 vr29_8_12 vr29_8_13 vr29_8_14 vr29_8_15 +vr30_8_0 vr30_8_1 vr30_8_2 vr30_8_3 vr30_8_4 vr30_8_5 vr30_8_6 vr30_8_7 vr30_8_8 vr30_8_9 vr30_8_10 vr30_8_11 vr30_8_12 vr30_8_13 vr30_8_14 vr30_8_15 +vr31_8_0 vr31_8_1 vr31_8_2 vr31_8_3 vr31_8_4 vr31_8_5 vr31_8_6 vr31_8_7 vr31_8_8 vr31_8_9 vr31_8_10 vr31_8_11 vr31_8_12 vr31_8_13 vr31_8_14 vr31_8_15 +]; +@else +define register offset=0x4200 size=8 [ # 64 bit access to vrN registers (psydo-registers) (accessed by vrD_64_N vrA_64_N vrB_64_N vrS_64_N vrC_64_N) +vr0_64_1 vr0_64_0 +vr1_64_1 vr1_64_0 +vr2_64_1 vr2_64_0 +vr3_64_1 vr3_64_0 +vr4_64_1 vr4_64_0 +vr5_64_1 vr5_64_0 +vr6_64_1 vr6_64_0 +vr7_64_1 vr7_64_0 +vr8_64_1 vr8_64_0 +vr9_64_1 vr9_64_0 +vr10_64_1 vr10_64_0 +vr11_64_1 vr11_64_0 +vr12_64_1 vr12_64_0 +vr13_64_1 vr13_64_0 +vr14_64_1 vr14_64_0 +vr15_64_1 vr15_64_0 +vr16_64_1 vr16_64_0 +vr17_64_1 vr17_64_0 +vr18_64_1 vr18_64_0 +vr19_64_1 vr19_64_0 +vr20_64_1 vr20_64_0 +vr21_64_1 vr21_64_0 +vr22_64_1 vr22_64_0 +vr23_64_1 vr23_64_0 +vr24_64_1 vr24_64_0 +vr25_64_1 vr25_64_0 +vr26_64_1 vr26_64_0 +vr27_64_1 vr27_64_0 +vr28_64_1 vr28_64_0 +vr29_64_1 vr29_64_0 +vr30_64_1 vr30_64_0 +vr31_64_1 vr31_64_0 +]; + +define register offset=0x4200 size=4 [ # 32 bit access to vrN registers (psydo-registers) (accessed by vrD_32_N vrA_32_N vrB_32_N vrS_32_N vrC_32_N) +vr0_32_3 vr0_32_2 vr0_32_1 vr0_32_0 +vr1_32_3 vr1_32_2 vr1_32_1 vr1_32_0 +vr2_32_3 vr2_32_2 vr2_32_1 vr2_32_0 +vr3_32_3 vr3_32_2 vr3_32_1 vr3_32_0 +vr4_32_3 vr4_32_2 vr4_32_1 vr4_32_0 +vr5_32_3 vr5_32_2 vr5_32_1 vr5_32_0 +vr6_32_3 vr6_32_2 vr6_32_1 vr6_32_0 +vr7_32_3 vr7_32_2 vr7_32_1 vr7_32_0 +vr8_32_3 vr8_32_2 vr8_32_1 vr8_32_0 +vr9_32_3 vr9_32_2 vr9_32_1 vr9_32_0 +vr10_32_3 vr10_32_2 vr10_32_1 vr10_32_0 +vr11_32_3 vr11_32_2 vr11_32_1 vr11_32_0 +vr12_32_3 vr12_32_2 vr12_32_1 vr12_32_0 +vr13_32_3 vr13_32_2 vr13_32_1 vr13_32_0 +vr14_32_3 vr14_32_2 vr14_32_1 vr14_32_0 +vr15_32_3 vr15_32_2 vr15_32_1 vr15_32_0 +vr16_32_3 vr16_32_2 vr16_32_1 vr16_32_0 +vr17_32_3 vr17_32_2 vr17_32_1 vr17_32_0 +vr18_32_3 vr18_32_2 vr18_32_1 vr18_32_0 +vr19_32_3 vr19_32_2 vr19_32_1 vr19_32_0 +vr20_32_3 vr20_32_2 vr20_32_1 vr20_32_0 +vr21_32_3 vr21_32_2 vr21_32_1 vr21_32_0 +vr22_32_3 vr22_32_2 vr22_32_1 vr22_32_0 +vr23_32_3 vr23_32_2 vr23_32_1 vr23_32_0 +vr24_32_3 vr24_32_2 vr24_32_1 vr24_32_0 +vr25_32_3 vr25_32_2 vr25_32_1 vr25_32_0 +vr26_32_3 vr26_32_2 vr26_32_1 vr26_32_0 +vr27_32_3 vr27_32_2 vr27_32_1 vr27_32_0 +vr28_32_3 vr28_32_2 vr28_32_1 vr28_32_0 +vr29_32_3 vr29_32_2 vr29_32_1 vr29_32_0 +vr30_32_3 vr30_32_2 vr30_32_1 vr30_32_0 +vr31_32_3 vr31_32_2 vr31_32_1 vr31_32_0 +]; + +# Create psydo sub-registers for the Altivec vector registers to allow better easier vector instructions by 2 byte subregisters +define register offset=0x4200 size=2 [ # 16 bit access to vrN registers (psydo-registers) (accessed by vrD_16_N vrA_16_N vrB_16_N vrS_16_N vrC_16_N) +vr0_16_7 vr0_16_6 vr0_16_5 vr0_16_4 vr0_16_3 vr0_16_2 vr0_16_1 vr0_16_0 +vr1_16_7 vr1_16_6 vr1_16_5 vr1_16_4 vr1_16_3 vr1_16_2 vr1_16_1 vr1_16_0 +vr2_16_7 vr2_16_6 vr2_16_5 vr2_16_4 vr2_16_3 vr2_16_2 vr2_16_1 vr2_16_0 +vr3_16_7 vr3_16_6 vr3_16_5 vr3_16_4 vr3_16_3 vr3_16_2 vr3_16_1 vr3_16_0 +vr4_16_7 vr4_16_6 vr4_16_5 vr4_16_4 vr4_16_3 vr4_16_2 vr4_16_1 vr4_16_0 +vr5_16_7 vr5_16_6 vr5_16_5 vr5_16_4 vr5_16_3 vr5_16_2 vr5_16_1 vr5_16_0 +vr6_16_7 vr6_16_6 vr6_16_5 vr6_16_4 vr6_16_3 vr6_16_2 vr6_16_1 vr6_16_0 +vr7_16_7 vr7_16_6 vr7_16_5 vr7_16_4 vr7_16_3 vr7_16_2 vr7_16_1 vr7_16_0 +vr8_16_7 vr8_16_6 vr8_16_5 vr8_16_4 vr8_16_3 vr8_16_2 vr8_16_1 vr8_16_0 +vr9_16_7 vr9_16_6 vr9_16_5 vr9_16_4 vr9_16_3 vr9_16_2 vr9_16_1 vr9_16_0 +vr10_16_7 vr10_16_6 vr10_16_5 vr10_16_4 vr10_16_3 vr10_16_2 vr10_16_1 vr10_16_0 +vr11_16_7 vr11_16_6 vr11_16_5 vr11_16_4 vr11_16_3 vr11_16_2 vr11_16_1 vr11_16_0 +vr12_16_7 vr12_16_6 vr12_16_5 vr12_16_4 vr12_16_3 vr12_16_2 vr12_16_1 vr12_16_0 +vr13_16_7 vr13_16_6 vr13_16_5 vr13_16_4 vr13_16_3 vr13_16_2 vr13_16_1 vr13_16_0 +vr14_16_7 vr14_16_6 vr14_16_5 vr14_16_4 vr14_16_3 vr14_16_2 vr14_16_1 vr14_16_0 +vr15_16_7 vr15_16_6 vr15_16_5 vr15_16_4 vr15_16_3 vr15_16_2 vr15_16_1 vr15_16_0 +vr16_16_7 vr16_16_6 vr16_16_5 vr16_16_4 vr16_16_3 vr16_16_2 vr16_16_1 vr16_16_0 +vr17_16_7 vr17_16_6 vr17_16_5 vr17_16_4 vr17_16_3 vr17_16_2 vr17_16_1 vr17_16_0 +vr18_16_7 vr18_16_6 vr18_16_5 vr18_16_4 vr18_16_3 vr18_16_2 vr18_16_1 vr18_16_0 +vr19_16_7 vr19_16_6 vr19_16_5 vr19_16_4 vr19_16_3 vr19_16_2 vr19_16_1 vr19_16_0 +vr20_16_7 vr20_16_6 vr20_16_5 vr20_16_4 vr20_16_3 vr20_16_2 vr20_16_1 vr20_16_0 +vr21_16_7 vr21_16_6 vr21_16_5 vr21_16_4 vr21_16_3 vr21_16_2 vr21_16_1 vr21_16_0 +vr22_16_7 vr22_16_6 vr22_16_5 vr22_16_4 vr22_16_3 vr22_16_2 vr22_16_1 vr22_16_0 +vr23_16_7 vr23_16_6 vr23_16_5 vr23_16_4 vr23_16_3 vr23_16_2 vr23_16_1 vr23_16_0 +vr24_16_7 vr24_16_6 vr24_16_5 vr24_16_4 vr24_16_3 vr24_16_2 vr24_16_1 vr24_16_0 +vr25_16_7 vr25_16_6 vr25_16_5 vr25_16_4 vr25_16_3 vr25_16_2 vr25_16_1 vr25_16_0 +vr26_16_7 vr26_16_6 vr26_16_5 vr26_16_4 vr26_16_3 vr26_16_2 vr26_16_1 vr26_16_0 +vr27_16_7 vr27_16_6 vr27_16_5 vr27_16_4 vr27_16_3 vr27_16_2 vr27_16_1 vr27_16_0 +vr28_16_7 vr28_16_6 vr28_16_5 vr28_16_4 vr28_16_3 vr28_16_2 vr28_16_1 vr28_16_0 +vr29_16_7 vr29_16_6 vr29_16_5 vr29_16_4 vr29_16_3 vr29_16_2 vr29_16_1 vr29_16_0 +vr30_16_7 vr30_16_6 vr30_16_5 vr30_16_4 vr30_16_3 vr30_16_2 vr30_16_1 vr30_16_0 +vr31_16_7 vr31_16_6 vr31_16_5 vr31_16_4 vr31_16_3 vr31_16_2 vr31_16_1 vr31_16_0 +]; + +# Create psydo sub-registers for the Altivec vector registers to allow better easier vector instructions by 1 byte subregisters +define register offset=0x4200 size=1 [ # 8 bit access to vrN registers (psydo-registers) (accessed by vrD_8_N vrA_8_N vrB_8_N vrS_8_N vrC_8_N) +vr0_8_15 vr0_8_14 vr0_8_13 vr0_8_12 vr0_8_11 vr0_8_10 vr0_8_9 vr0_8_8 vr0_8_7 vr0_8_6 vr0_8_5 vr0_8_4 vr0_8_3 vr0_8_2 vr0_8_1 vr0_8_0 +vr1_8_15 vr1_8_14 vr1_8_13 vr1_8_12 vr1_8_11 vr1_8_10 vr1_8_9 vr1_8_8 vr1_8_7 vr1_8_6 vr1_8_5 vr1_8_4 vr1_8_3 vr1_8_2 vr1_8_1 vr1_8_0 +vr2_8_15 vr2_8_14 vr2_8_13 vr2_8_12 vr2_8_11 vr2_8_10 vr2_8_9 vr2_8_8 vr2_8_7 vr2_8_6 vr2_8_5 vr2_8_4 vr2_8_3 vr2_8_2 vr2_8_1 vr2_8_0 +vr3_8_15 vr3_8_14 vr3_8_13 vr3_8_12 vr3_8_11 vr3_8_10 vr3_8_9 vr3_8_8 vr3_8_7 vr3_8_6 vr3_8_5 vr3_8_4 vr3_8_3 vr3_8_2 vr3_8_1 vr3_8_0 +vr4_8_15 vr4_8_14 vr4_8_13 vr4_8_12 vr4_8_11 vr4_8_10 vr4_8_9 vr4_8_8 vr4_8_7 vr4_8_6 vr4_8_5 vr4_8_4 vr4_8_3 vr4_8_2 vr4_8_1 vr4_8_0 +vr5_8_15 vr5_8_14 vr5_8_13 vr5_8_12 vr5_8_11 vr5_8_10 vr5_8_9 vr5_8_8 vr5_8_7 vr5_8_6 vr5_8_5 vr5_8_4 vr5_8_3 vr5_8_2 vr5_8_1 vr5_8_0 +vr6_8_15 vr6_8_14 vr6_8_13 vr6_8_12 vr6_8_11 vr6_8_10 vr6_8_9 vr6_8_8 vr6_8_7 vr6_8_6 vr6_8_5 vr6_8_4 vr6_8_3 vr6_8_2 vr6_8_1 vr6_8_0 +vr7_8_15 vr7_8_14 vr7_8_13 vr7_8_12 vr7_8_11 vr7_8_10 vr7_8_9 vr7_8_8 vr7_8_7 vr7_8_6 vr7_8_5 vr7_8_4 vr7_8_3 vr7_8_2 vr7_8_1 vr7_8_0 +vr8_8_15 vr8_8_14 vr8_8_13 vr8_8_12 vr8_8_11 vr8_8_10 vr8_8_9 vr8_8_8 vr8_8_7 vr8_8_6 vr8_8_5 vr8_8_4 vr8_8_3 vr8_8_2 vr8_8_1 vr8_8_0 +vr9_8_15 vr9_8_14 vr9_8_13 vr9_8_12 vr9_8_11 vr9_8_10 vr9_8_9 vr9_8_8 vr9_8_7 vr9_8_6 vr9_8_5 vr9_8_4 vr9_8_3 vr9_8_2 vr9_8_1 vr9_8_0 +vr10_8_15 vr10_8_14 vr10_8_13 vr10_8_12 vr10_8_11 vr10_8_10 vr10_8_9 vr10_8_8 vr10_8_7 vr10_8_6 vr10_8_5 vr10_8_4 vr10_8_3 vr10_8_2 vr10_8_1 vr10_8_0 +vr11_8_15 vr11_8_14 vr11_8_13 vr11_8_12 vr11_8_11 vr11_8_10 vr11_8_9 vr11_8_8 vr11_8_7 vr11_8_6 vr11_8_5 vr11_8_4 vr11_8_3 vr11_8_2 vr11_8_1 vr11_8_0 +vr12_8_15 vr12_8_14 vr12_8_13 vr12_8_12 vr12_8_11 vr12_8_10 vr12_8_9 vr12_8_8 vr12_8_7 vr12_8_6 vr12_8_5 vr12_8_4 vr12_8_3 vr12_8_2 vr12_8_1 vr12_8_0 +vr13_8_15 vr13_8_14 vr13_8_13 vr13_8_12 vr13_8_11 vr13_8_10 vr13_8_9 vr13_8_8 vr13_8_7 vr13_8_6 vr13_8_5 vr13_8_4 vr13_8_3 vr13_8_2 vr13_8_1 vr13_8_0 +vr14_8_15 vr14_8_14 vr14_8_13 vr14_8_12 vr14_8_11 vr14_8_10 vr14_8_9 vr14_8_8 vr14_8_7 vr14_8_6 vr14_8_5 vr14_8_4 vr14_8_3 vr14_8_2 vr14_8_1 vr14_8_0 +vr15_8_15 vr15_8_14 vr15_8_13 vr15_8_12 vr15_8_11 vr15_8_10 vr15_8_9 vr15_8_8 vr15_8_7 vr15_8_6 vr15_8_5 vr15_8_4 vr15_8_3 vr15_8_2 vr15_8_1 vr15_8_0 +vr16_8_15 vr16_8_14 vr16_8_13 vr16_8_12 vr16_8_11 vr16_8_10 vr16_8_9 vr16_8_8 vr16_8_7 vr16_8_6 vr16_8_5 vr16_8_4 vr16_8_3 vr16_8_2 vr16_8_1 vr16_8_0 +vr17_8_15 vr17_8_14 vr17_8_13 vr17_8_12 vr17_8_11 vr17_8_10 vr17_8_9 vr17_8_8 vr17_8_7 vr17_8_6 vr17_8_5 vr17_8_4 vr17_8_3 vr17_8_2 vr17_8_1 vr17_8_0 +vr18_8_15 vr18_8_14 vr18_8_13 vr18_8_12 vr18_8_11 vr18_8_10 vr18_8_9 vr18_8_8 vr18_8_7 vr18_8_6 vr18_8_5 vr18_8_4 vr18_8_3 vr18_8_2 vr18_8_1 vr18_8_0 +vr19_8_15 vr19_8_14 vr19_8_13 vr19_8_12 vr19_8_11 vr19_8_10 vr19_8_9 vr19_8_8 vr19_8_7 vr19_8_6 vr19_8_5 vr19_8_4 vr19_8_3 vr19_8_2 vr19_8_1 vr19_8_0 +vr20_8_15 vr20_8_14 vr20_8_13 vr20_8_12 vr20_8_11 vr20_8_10 vr20_8_9 vr20_8_8 vr20_8_7 vr20_8_6 vr20_8_5 vr20_8_4 vr20_8_3 vr20_8_2 vr20_8_1 vr20_8_0 +vr21_8_15 vr21_8_14 vr21_8_13 vr21_8_12 vr21_8_11 vr21_8_10 vr21_8_9 vr21_8_8 vr21_8_7 vr21_8_6 vr21_8_5 vr21_8_4 vr21_8_3 vr21_8_2 vr21_8_1 vr21_8_0 +vr22_8_15 vr22_8_14 vr22_8_13 vr22_8_12 vr22_8_11 vr22_8_10 vr22_8_9 vr22_8_8 vr22_8_7 vr22_8_6 vr22_8_5 vr22_8_4 vr22_8_3 vr22_8_2 vr22_8_1 vr22_8_0 +vr23_8_15 vr23_8_14 vr23_8_13 vr23_8_12 vr23_8_11 vr23_8_10 vr23_8_9 vr23_8_8 vr23_8_7 vr23_8_6 vr23_8_5 vr23_8_4 vr23_8_3 vr23_8_2 vr23_8_1 vr23_8_0 +vr24_8_15 vr24_8_14 vr24_8_13 vr24_8_12 vr24_8_11 vr24_8_10 vr24_8_9 vr24_8_8 vr24_8_7 vr24_8_6 vr24_8_5 vr24_8_4 vr24_8_3 vr24_8_2 vr24_8_1 vr24_8_0 +vr25_8_15 vr25_8_14 vr25_8_13 vr25_8_12 vr25_8_11 vr25_8_10 vr25_8_9 vr25_8_8 vr25_8_7 vr25_8_6 vr25_8_5 vr25_8_4 vr25_8_3 vr25_8_2 vr25_8_1 vr25_8_0 +vr26_8_15 vr26_8_14 vr26_8_13 vr26_8_12 vr26_8_11 vr26_8_10 vr26_8_9 vr26_8_8 vr26_8_7 vr26_8_6 vr26_8_5 vr26_8_4 vr26_8_3 vr26_8_2 vr26_8_1 vr26_8_0 +vr27_8_15 vr27_8_14 vr27_8_13 vr27_8_12 vr27_8_11 vr27_8_10 vr27_8_9 vr27_8_8 vr27_8_7 vr27_8_6 vr27_8_5 vr27_8_4 vr27_8_3 vr27_8_2 vr27_8_1 vr27_8_0 +vr28_8_15 vr28_8_14 vr28_8_13 vr28_8_12 vr28_8_11 vr28_8_10 vr28_8_9 vr28_8_8 vr28_8_7 vr28_8_6 vr28_8_5 vr28_8_4 vr28_8_3 vr28_8_2 vr28_8_1 vr28_8_0 +vr29_8_15 vr29_8_14 vr29_8_13 vr29_8_12 vr29_8_11 vr29_8_10 vr29_8_9 vr29_8_8 vr29_8_7 vr29_8_6 vr29_8_5 vr29_8_4 vr29_8_3 vr29_8_2 vr29_8_1 vr29_8_0 +vr30_8_15 vr30_8_14 vr30_8_13 vr30_8_12 vr30_8_11 vr30_8_10 vr30_8_9 vr30_8_8 vr30_8_7 vr30_8_6 vr30_8_5 vr30_8_4 vr30_8_3 vr30_8_2 vr30_8_1 vr30_8_0 +vr31_8_15 vr31_8_14 vr31_8_13 vr31_8_12 vr31_8_11 vr31_8_10 vr31_8_9 vr31_8_8 vr31_8_7 vr31_8_6 vr31_8_5 vr31_8_4 vr31_8_3 vr31_8_2 vr31_8_1 vr31_8_0 +]; + +@endif +# Define context bits +define register offset=0x6000 size=4 contextreg; +define context contextreg + linkreg=(0,1) # 0 - no LR set, 1 - LR set (used to flag branch instructions to be treated as calls) + vle=(2,2) # Used to control inclusion/disassembly of vle instructions. '1' means use vle see NOTVLE/ISVLE @define below + # FIXME! while allowing vle context to flow is incorrect, the PowerPC disassembly action will not work at all without it + # and could easily flow the incorrect context when traversing between VLE and non-VLE sections. + + # transient context + lsmul=(3,7) noflow # Used for Load/store multiple parsing + regp=(8,12) noflow # Used in powerISA quad word instructions + regpset=(8,12) noflow # Used in powerISA quad word instructions +; + +@define NOTVLE "vle=0" +@define ISVLE "vle=1" + +# Define Device Control Registers (specific to IBM PowerPC Embedded Controller, see instructions mfdcr/mtdcr) +# Device Control Registers are defined with generic names +# These names may be replaced within register_data section within a PPC variant's pspec file +define register offset=0x7000 size=$(REGISTER_SIZE) + [ dcr000 dcr001 dcr002 dcr003 dcr004 dcr005 dcr006 dcr007 dcr008 dcr009 dcr00a dcr00b dcr00c dcr00d dcr00e dcr00f + dcr010 dcr011 dcr012 dcr013 dcr014 dcr015 dcr016 dcr017 dcr018 dcr019 dcr01a dcr01b dcr01c dcr01d dcr01e dcr01f + dcr020 dcr021 dcr022 dcr023 dcr024 dcr025 dcr026 dcr027 dcr028 dcr029 dcr02a dcr02b dcr02c dcr02d dcr02e dcr02f + dcr030 dcr031 dcr032 dcr033 dcr034 dcr035 dcr036 dcr037 dcr038 dcr039 dcr03a dcr03b dcr03c dcr03d dcr03e dcr03f + dcr040 dcr041 dcr042 dcr043 dcr044 dcr045 dcr046 dcr047 dcr048 dcr049 dcr04a dcr04b dcr04c dcr04d dcr04e dcr04f + dcr050 dcr051 dcr052 dcr053 dcr054 dcr055 dcr056 dcr057 dcr058 dcr059 dcr05a dcr05b dcr05c dcr05d dcr05e dcr05f + dcr060 dcr061 dcr062 dcr063 dcr064 dcr065 dcr066 dcr067 dcr068 dcr069 dcr06a dcr06b dcr06c dcr06d dcr06e dcr06f + dcr070 dcr071 dcr072 dcr073 dcr074 dcr075 dcr076 dcr077 dcr078 dcr079 dcr07a dcr07b dcr07c dcr07d dcr07e dcr07f + dcr080 dcr081 dcr082 dcr083 dcr084 dcr085 dcr086 dcr087 dcr088 dcr089 dcr08a dcr08b dcr08c dcr08d dcr08e dcr08f + dcr090 dcr091 dcr092 dcr093 dcr094 dcr095 dcr096 dcr097 dcr098 dcr099 dcr09a dcr09b dcr09c dcr09d dcr09e dcr09f + dcr0a0 dcr0a1 dcr0a2 dcr0a3 dcr0a4 dcr0a5 dcr0a6 dcr0a7 dcr0a8 dcr0a9 dcr0aa dcr0ab dcr0ac dcr0ad dcr0ae dcr0af + dcr0b0 dcr0b1 dcr0b2 dcr0b3 dcr0b4 dcr0b5 dcr0b6 dcr0b7 dcr0b8 dcr0b9 dcr0ba dcr0bb dcr0bc dcr0bd dcr0be dcr0bf + dcr0c0 dcr0c1 dcr0c2 dcr0c3 dcr0c4 dcr0c5 dcr0c6 dcr0c7 dcr0c8 dcr0c9 dcr0ca dcr0cb dcr0cc dcr0cd dcr0ce dcr0cf + dcr0d0 dcr0d1 dcr0d2 dcr0d3 dcr0d4 dcr0d5 dcr0d6 dcr0d7 dcr0d8 dcr0d9 dcr0da dcr0db dcr0dc dcr0dd dcr0de dcr0df + dcr0e0 dcr0e1 dcr0e2 dcr0e3 dcr0e4 dcr0e5 dcr0e6 dcr0e7 dcr0e8 dcr0e9 dcr0ea dcr0eb dcr0ec dcr0ed dcr0ee dcr0ef + dcr0f0 dcr0f1 dcr0f2 dcr0f3 dcr0f4 dcr0f5 dcr0f6 dcr0f7 dcr0f8 dcr0f9 dcr0fa dcr0fb dcr0fc dcr0fd dcr0fe dcr0ff + dcr100 dcr101 dcr102 dcr103 dcr104 dcr105 dcr106 dcr107 dcr108 dcr109 dcr10a dcr10b dcr10c dcr10d dcr10e dcr10f + dcr110 dcr111 dcr112 dcr113 dcr114 dcr115 dcr116 dcr117 dcr118 dcr119 dcr11a dcr11b dcr11c dcr11d dcr11e dcr11f + dcr120 dcr121 dcr122 dcr123 dcr124 dcr125 dcr126 dcr127 dcr128 dcr129 dcr12a dcr12b dcr12c dcr12d dcr12e dcr12f + dcr130 dcr131 dcr132 dcr133 dcr134 dcr135 dcr136 dcr137 dcr138 dcr139 dcr13a dcr13b dcr13c dcr13d dcr13e dcr13f + dcr140 dcr141 dcr142 dcr143 dcr144 dcr145 dcr146 dcr147 dcr148 dcr149 dcr14a dcr14b dcr14c dcr14d dcr14e dcr14f + dcr150 dcr151 dcr152 dcr153 dcr154 dcr155 dcr156 dcr157 dcr158 dcr159 dcr15a dcr15b dcr15c dcr15d dcr15e dcr15f + dcr160 dcr161 dcr162 dcr163 dcr164 dcr165 dcr166 dcr167 dcr168 dcr169 dcr16a dcr16b dcr16c dcr16d dcr16e dcr16f + dcr170 dcr171 dcr172 dcr173 dcr174 dcr175 dcr176 dcr177 dcr178 dcr179 dcr17a dcr17b dcr17c dcr17d dcr17e dcr17f + dcr180 dcr181 dcr182 dcr183 dcr184 dcr185 dcr186 dcr187 dcr188 dcr189 dcr18a dcr18b dcr18c dcr18d dcr18e dcr18f + dcr190 dcr191 dcr192 dcr193 dcr194 dcr195 dcr196 dcr197 dcr198 dcr199 dcr19a dcr19b dcr19c dcr19d dcr19e dcr19f + dcr1a0 dcr1a1 dcr1a2 dcr1a3 dcr1a4 dcr1a5 dcr1a6 dcr1a7 dcr1a8 dcr1a9 dcr1aa dcr1ab dcr1ac dcr1ad dcr1ae dcr1af + dcr1b0 dcr1b1 dcr1b2 dcr1b3 dcr1b4 dcr1b5 dcr1b6 dcr1b7 dcr1b8 dcr1b9 dcr1ba dcr1bb dcr1bc dcr1bd dcr1be dcr1bf + dcr1c0 dcr1c1 dcr1c2 dcr1c3 dcr1c4 dcr1c5 dcr1c6 dcr1c7 dcr1c8 dcr1c9 dcr1ca dcr1cb dcr1cc dcr1cd dcr1ce dcr1cf + dcr1d0 dcr1d1 dcr1d2 dcr1d3 dcr1d4 dcr1d5 dcr1d6 dcr1d7 dcr1d8 dcr1d9 dcr1da dcr1db dcr1dc dcr1dd dcr1de dcr1df + dcr1e0 dcr1e1 dcr1e2 dcr1e3 dcr1e4 dcr1e5 dcr1e6 dcr1e7 dcr1e8 dcr1e9 dcr1ea dcr1eb dcr1ec dcr1ed dcr1ee dcr1ef + dcr1f0 dcr1f1 dcr1f2 dcr1f3 dcr1f4 dcr1f5 dcr1f6 dcr1f7 dcr1f8 dcr1f9 dcr1fa dcr1fb dcr1fc dcr1fd dcr1fe dcr1ff + dcr200 dcr201 dcr202 dcr203 dcr204 dcr205 dcr206 dcr207 dcr208 dcr209 dcr20a dcr20b dcr20c dcr20d dcr20e dcr20f + dcr210 dcr211 dcr212 dcr213 dcr214 dcr215 dcr216 dcr217 dcr218 dcr219 dcr21a dcr21b dcr21c dcr21d dcr21e dcr21f + dcr220 dcr221 dcr222 dcr223 dcr224 dcr225 dcr226 dcr227 dcr228 dcr229 dcr22a dcr22b dcr22c dcr22d dcr22e dcr22f + dcr230 dcr231 dcr232 dcr233 dcr234 dcr235 dcr236 dcr237 dcr238 dcr239 dcr23a dcr23b dcr23c dcr23d dcr23e dcr23f + dcr240 dcr241 dcr242 dcr243 dcr244 dcr245 dcr246 dcr247 dcr248 dcr249 dcr24a dcr24b dcr24c dcr24d dcr24e dcr24f + dcr250 dcr251 dcr252 dcr253 dcr254 dcr255 dcr256 dcr257 dcr258 dcr259 dcr25a dcr25b dcr25c dcr25d dcr25e dcr25f + dcr260 dcr261 dcr262 dcr263 dcr264 dcr265 dcr266 dcr267 dcr268 dcr269 dcr26a dcr26b dcr26c dcr26d dcr26e dcr26f + dcr270 dcr271 dcr272 dcr273 dcr274 dcr275 dcr276 dcr277 dcr278 dcr279 dcr27a dcr27b dcr27c dcr27d dcr27e dcr27f + dcr280 dcr281 dcr282 dcr283 dcr284 dcr285 dcr286 dcr287 dcr288 dcr289 dcr28a dcr28b dcr28c dcr28d dcr28e dcr28f + dcr290 dcr291 dcr292 dcr293 dcr294 dcr295 dcr296 dcr297 dcr298 dcr299 dcr29a dcr29b dcr29c dcr29d dcr29e dcr29f + dcr2a0 dcr2a1 dcr2a2 dcr2a3 dcr2a4 dcr2a5 dcr2a6 dcr2a7 dcr2a8 dcr2a9 dcr2aa dcr2ab dcr2ac dcr2ad dcr2ae dcr2af + dcr2b0 dcr2b1 dcr2b2 dcr2b3 dcr2b4 dcr2b5 dcr2b6 dcr2b7 dcr2b8 dcr2b9 dcr2ba dcr2bb dcr2bc dcr2bd dcr2be dcr2bf + dcr2c0 dcr2c1 dcr2c2 dcr2c3 dcr2c4 dcr2c5 dcr2c6 dcr2c7 dcr2c8 dcr2c9 dcr2ca dcr2cb dcr2cc dcr2cd dcr2ce dcr2cf + dcr2d0 dcr2d1 dcr2d2 dcr2d3 dcr2d4 dcr2d5 dcr2d6 dcr2d7 dcr2d8 dcr2d9 dcr2da dcr2db dcr2dc dcr2dd dcr2de dcr2df + dcr2e0 dcr2e1 dcr2e2 dcr2e3 dcr2e4 dcr2e5 dcr2e6 dcr2e7 dcr2e8 dcr2e9 dcr2ea dcr2eb dcr2ec dcr2ed dcr2ee dcr2ef + dcr2f0 dcr2f1 dcr2f2 dcr2f3 dcr2f4 dcr2f5 dcr2f6 dcr2f7 dcr2f8 dcr2f9 dcr2fa dcr2fb dcr2fc dcr2fd dcr2fe dcr2ff + dcr300 dcr301 dcr302 dcr303 dcr304 dcr305 dcr306 dcr307 dcr308 dcr309 dcr30a dcr30b dcr30c dcr30d dcr30e dcr30f + dcr310 dcr311 dcr312 dcr313 dcr314 dcr315 dcr316 dcr317 dcr318 dcr319 dcr31a dcr31b dcr31c dcr31d dcr31e dcr31f + dcr320 dcr321 dcr322 dcr323 dcr324 dcr325 dcr326 dcr327 dcr328 dcr329 dcr32a dcr32b dcr32c dcr32d dcr32e dcr32f + dcr330 dcr331 dcr332 dcr333 dcr334 dcr335 dcr336 dcr337 dcr338 dcr339 dcr33a dcr33b dcr33c dcr33d dcr33e dcr33f + dcr340 dcr341 dcr342 dcr343 dcr344 dcr345 dcr346 dcr347 dcr348 dcr349 dcr34a dcr34b dcr34c dcr34d dcr34e dcr34f + dcr350 dcr351 dcr352 dcr353 dcr354 dcr355 dcr356 dcr357 dcr358 dcr359 dcr35a dcr35b dcr35c dcr35d dcr35e dcr35f + dcr360 dcr361 dcr362 dcr363 dcr364 dcr365 dcr366 dcr367 dcr368 dcr369 dcr36a dcr36b dcr36c dcr36d dcr36e dcr36f + dcr370 dcr371 dcr372 dcr373 dcr374 dcr375 dcr376 dcr377 dcr378 dcr379 dcr37a dcr37b dcr37c dcr37d dcr37e dcr37f + dcr380 dcr381 dcr382 dcr383 dcr384 dcr385 dcr386 dcr387 dcr388 dcr389 dcr38a dcr38b dcr38c dcr38d dcr38e dcr38f + dcr390 dcr391 dcr392 dcr393 dcr394 dcr395 dcr396 dcr397 dcr398 dcr399 dcr39a dcr39b dcr39c dcr39d dcr39e dcr39f + dcr3a0 dcr3a1 dcr3a2 dcr3a3 dcr3a4 dcr3a5 dcr3a6 dcr3a7 dcr3a8 dcr3a9 dcr3aa dcr3ab dcr3ac dcr3ad dcr3ae dcr3af + dcr3b0 dcr3b1 dcr3b2 dcr3b3 dcr3b4 dcr3b5 dcr3b6 dcr3b7 dcr3b8 dcr3b9 dcr3ba dcr3bb dcr3bc dcr3bd dcr3be dcr3bf + dcr3c0 dcr3c1 dcr3c2 dcr3c3 dcr3c4 dcr3c5 dcr3c6 dcr3c7 dcr3c8 dcr3c9 dcr3ca dcr3cb dcr3cc dcr3cd dcr3ce dcr3cf + dcr3d0 dcr3d1 dcr3d2 dcr3d3 dcr3d4 dcr3d5 dcr3d6 dcr3d7 dcr3d8 dcr3d9 dcr3da dcr3db dcr3dc dcr3dd dcr3de dcr3df + dcr3e0 dcr3e1 dcr3e2 dcr3e3 dcr3e4 dcr3e5 dcr3e6 dcr3e7 dcr3e8 dcr3e9 dcr3ea dcr3eb dcr3ec dcr3ed dcr3ee dcr3ef + dcr3f0 dcr3f1 dcr3f2 dcr3f3 dcr3f4 dcr3f5 dcr3f6 dcr3f7 dcr3f8 dcr3f9 dcr3fa dcr3fb dcr3fc dcr3fd dcr3fe dcr3ff + ]; + +# ACC and SPEFSCR are part of the "EREF: A Reference for Motorola Book E and e500 Core" spec +# SPEFSCR is a reperposed spr200 +define register offset=0x10000 size=8 [ACC]; + +# OP=17 & BITS_21_25=0 & BITS_16_20=0(ok) & BITS_5_11=LEV & BITS_2_4=0 & BIT_1=1 & BIT_0=0 + +define token instr(32) + A=(16,20) + AA=(1,1) + A_BITS=(16,20) + A_BITSS=(16,20) signed + AX=(2,2) + B=(11,15) + B_BITS=(11,15) + BD=(2,15) signed + BF=(17,24) + BFA=(0,2) + BFA2=(18,20) + BF2=(23,25) + BH=(11,12) + BH_BITS=(11,12) + BH_RBE=(11,20) + BH_RET=(11,11) + BI_BITS=(16,20) + BI_CC=(16,17) + BI_CR=(18,20) + BIT_A=(25,25) + BIT_L=(21,21) + BIT_R=(21,21) + BIT_0=(0,0) + BIT_10=(10,10) + BIT_1=(1,1) + BIT_11=(11,11) + BIT_15=(15,15) + BIT_16=(16,16) + BIT_17=(17,17) + BIT_18=(18,18) + BIT_20=(20,20) + BIT_22=(22,22) + BIT_25=(25,25) + BIT_9=(9,9) + BIT_6=(6,6) + BITS_0_1=(0,1) + BITS_0_17=(0,17) + BITS_0_2=(0,2) + BITS_0_3=(0,3) + BITS_1_10=(1,10) + BITS_11_13=(11,13) + BITS_11_15=(11,15) + BITS_11_17=(11,17) + BITS_11_20=(11,20) + BITS_11_22=(11,22) + BITS_11_24=(11,24) + BITS_11_25=(11,25) + BITS_12_15=(12,15) + BITS_12_19=(12,19) + BITS_12_25=(12,25) + BITS_13_15=(13,15) + BITS_14_15=(14,15) + BITS_16_17=(12,15) + BITS_16_18=(16,18) + BITS_16_19=(16,19) + BITS_16_20=(16,20) + BITS_16_22=(16,22) + BITS_16_25=(16,25) + BITS_17_20=(17,20) + BITS_17_24=(17,24) + BITS_18_19=(18,19) + BITS_18_20=(18,20) + BITS_1_9=(1,9) + BITS_19_20=(19,20) + BITS_20_20=(20,20) + BITS_21_22=(21,22) + BITS_21_23=(21,23) + BITS_21_24=(7,10) + BITS_21_25=(21,25) + BITS_21_28=(21,28) + BITS_22_24=(22,24) + BITS_22_25=(22,25) + BITS_22_26=(22,26) + BITS_2_25=(2,25) + BITS_23_24=(23,24) + BITS_23_25=(23,25) + BITS_2_4=(2,4) + BITS_24_25=(24,25) + BITS_3_7=(3,7) + BITS_4_5=(4,5) + BITS_6_10=(6,10) + BO_0=(25,25) + BO_1=(24,24) + BO=(21,25) + BO_2=(23,23) + BO_3=(22, 22) + BO_BITS=(21,25) + BX=(1,1) + C=(6,10) + COND_BRANCH_CTRL=(22,25) + CR_A=(18,20) + CR_A_CC=(16,17) + CR_B=(13,15) + CR_B_CC=(11,12) + CRBD=(21,25) + CRBR=(6,10) + CR_D=(23,25) + CR_D_CC=(21,22) + crfD=(23,25) + CRFD=(23,25) + CRFS=(18,20) + CRM0=(19,19) + CRM1=(18,18) + CRM=(12,19) + CRM2=(17,17) + CRM3=(16,16) + CRM4=(15,15) + CRM5=(14,14) + CRM6=(13,13) + CRM7=(12,12) + CR_X=(8,10) + CR_X_CC=(6,7) + CT=(21,25) + CT2=(21,24) + CX=(3,3) + D0=(6,15) signed + D1=(16,20) + D2=(0,0) + D=(21,25) + Dp=(21,25) + DC6=(6,6) + DCM=(10,15) + DCMX=(16,22) + DCRN=(11,20) + DGM=(10,15) + DM=(8,9) + DM2=(2,2) + DQ=(4,15) + DQs=(4,15) signed + DS=(2,15) + DSs=(2,15) signed + DX=(16,20) + DUI=(21,25) + DUIS=(11,20) + EX=(0,0) + fA=(16,20) + fB=(11,15) + fC=(6,10) + fD=(21,25) + FM0=(24,24) + FM1=(23,23) + FM=(17,24) + FM2=(22,22) + FM3=(21,21) + FM4=(20,20) + FM5=(19,19) + FM6=(18,18) + FM7=(17,17) + FNC=(11,15) + fS=(21,25) + fT=(21,25) + IMM=(11,15) + + EVUIMM=(11,15) + BU_UIMM=(16,20) + BU_SIMM=(16,20) + EVUIMM_8=(11,15) + EVUIMM_4=(11,15) + EVUIMM_2=(11,15) + + L= (21,22) + L2=(21,21) + L16=(16,17) + LEV=(5,11) + LI=(2,25) signed + LK=(0,0) + MBH=(5,5) + MBL=(6,10) + ME=(1,5) + MO=(21,25) + MSR_L=(16,16) + NB= (11,15) + O=(9,9) + OE=(10,10) + OP=(26,31) + PS=(9,9) + Rc=(0,0) + Rc2=(10,10) + RMC=(9,10) + + RA=(16,20) + RB=(11,15) + RS=(21,25) + RT=(21,25) + R0=(0,0) + R16=(16,16) + + S=(21,25) + SBE=(11,11) + SH16=(10,15) + SHB=(6,9) + SHH=(1,1) + SHL=(11,15) + SHW=(8,9) + S8IMM=(0,7) signed + S5IMM=(11,15) signed + SIMM=(0,15) signed + SIMM_DS=(2,15) signed + SIMM_SIGN=(15,15) + SIX=(11,14) + SP=(19,20) + SPRVAL=(11,20) + SR=(16,19) + ST=(15,15) + STRM=(21,22) + SX=(0,0) + SX3=(3,3) + T=(21,25) + TOA=(21,25) + TBR=(11,20) + TH=(21,25) + TMP_6_10=(21,25) + TO=(21,25) + TX=(0,0) + TX3=(3,3) + UI=(11,15) + UI_11_s8=(16,20) + UI_16_s8=(11,15) + UI_16_s16=(0,15) + UIMM8=(11,18) + UIMM=(0,15) + UIM=(16,17) + UIMB=(16,19) + UIMH=(16,18) + UIMW=(16,17) + UIMT=(16,21) + + vrAR=(16,20) # AltVect Vector register vrN selector (128 bit) + vrAD=(16,20) + + vrA_64_0=(16,20) # AltVect Vector register vrN selector (64 bit) + vrA_64_1=(16,20) + + vrA_32_0=(16,20) # AltVect Vector register vrN selector (32 bit) + vrA_32_1=(16,20) + vrA_32_2=(16,20) + vrA_32_3=(16,20) + + vrA_16_0=(16,20) # AltVect Vector register vrN selector (16 bit) + vrA_16_1=(16,20) + vrA_16_2=(16,20) + vrA_16_3=(16,20) + vrA_16_4=(16,20) + vrA_16_5=(16,20) + vrA_16_6=(16,20) + vrA_16_7=(16,20) + + vrA_8_0=(16,20) # AltVect Vector register vrN selector (8 bit) + vrA_8_1=(16,20) + vrA_8_2=(16,20) + vrA_8_3=(16,20) + vrA_8_4=(16,20) + vrA_8_5=(16,20) + vrA_8_6=(16,20) + vrA_8_7=(16,20) + vrA_8_8=(16,20) + vrA_8_9=(16,20) + vrA_8_10=(16,20) + vrA_8_11=(16,20) + vrA_8_12=(16,20) + vrA_8_13=(16,20) + vrA_8_14=(16,20) + vrA_8_15=(16,20) + + vrBR=(11,15) # AltVect Vector register vrN selector (128 bit) + vrBD=(11,15) + + vrB_64_0=(11,15) # AltVect Vector register vrN selector (64 bit) + vrB_64_1=(11,15) + + vrB_32_0=(11,15) # AltVect Vector register vrN selector (32 bit) + vrB_32_1=(11,15) + vrB_32_2=(11,15) + vrB_32_3=(11,15) + + vrB_16_0=(11,15) # AltVect Vector register vrN selector (16 bit) + vrB_16_1=(11,15) + vrB_16_2=(11,15) + vrB_16_3=(11,15) + vrB_16_4=(11,15) + vrB_16_5=(11,15) + vrB_16_6=(11,15) + vrB_16_7=(11,15) + + vrB_8_0=(11,15) # AltVect Vector register vrN selector (8 bit) + vrB_8_1=(11,15) + vrB_8_2=(11,15) + vrB_8_3=(11,15) + vrB_8_4=(11,15) + vrB_8_5=(11,15) + vrB_8_6=(11,15) + vrB_8_7=(11,15) + vrB_8_8=(11,15) + vrB_8_9=(11,15) + vrB_8_10=(11,15) + vrB_8_11=(11,15) + vrB_8_12=(11,15) + vrB_8_13=(11,15) + vrB_8_14=(11,15) + vrB_8_15=(11,15) + + + vrCR=(6,10) # AltVect Vector register vrN selector (128 bit) + vrCD=(6,10) + + vrC_64_0=(6,10) # AltVect Vector register vrN selector (64 bit) + vrC_64_1=(6,10) + + vrC_32_0=(6,10) # AltVect Vector register vrN selector (32 bit) + vrC_32_1=(6,10) + vrC_32_2=(6,10) + vrC_32_3=(6,10) + + vrC_16_0=(6,10) # AltVect Vector register vrN selector (16 bit) + vrC_16_1=(6,10) + vrC_16_2=(6,10) + vrC_16_3=(6,10) + vrC_16_4=(6,10) + vrC_16_5=(6,10) + vrC_16_6=(6,10) + vrC_16_7=(6,10) + + + vrC_8_0=(6,10) # AltVect Vector register vrN selector (8 bit) + vrC_8_1=(6,10) + vrC_8_2=(6,10) + vrC_8_3=(6,10) + vrC_8_4=(6,10) + vrC_8_5=(6,10) + vrC_8_6=(6,10) + vrC_8_7=(6,10) + vrC_8_8=(6,10) + vrC_8_9=(6,10) + vrC_8_10=(6,10) + vrC_8_11=(6,10) + vrC_8_12=(6,10) + vrC_8_13=(6,10) + vrC_8_14=(6,10) + vrC_8_15=(6,10) + + + vrDR=(21,25) # AltVect Vector register vrN selector (128 bit) + vrDD=(21,25) + + vrD_64_0=(21,25) # AltVect Vector register vrN selector (64 bit) + vrD_64_1=(21,25) + + vrD_32_0=(21,25) # AltVect Vector register vrN selector (32 bit) + vrD_32_1=(21,25) + vrD_32_2=(21,25) + vrD_32_3=(21,25) + + vrD_16_0=(21,25) # AltVect Vector register vrN selector (16 bit) + vrD_16_1=(21,25) + vrD_16_2=(21,25) + vrD_16_3=(21,25) + vrD_16_4=(21,25) + vrD_16_5=(21,25) + vrD_16_6=(21,25) + vrD_16_7=(21,25) + + vrD_8_0=(21,25) # AltVect Vector register vrN selector (8 bit) + vrD_8_1=(21,25) + vrD_8_2=(21,25) + vrD_8_3=(21,25) + vrD_8_4=(21,25) + vrD_8_5=(21,25) + vrD_8_6=(21,25) + vrD_8_7=(21,25) + vrD_8_8=(21,25) + vrD_8_9=(21,25) + vrD_8_10=(21,25) + vrD_8_11=(21,25) + vrD_8_12=(21,25) + vrD_8_13=(21,25) + vrD_8_14=(21,25) + vrD_8_15=(21,25) + + + vrSR=(21,25) # AltVect Vector register vrN selector (128 bit) + vrSD=(21,25) + + vrS_64_0=(21,25) # AltVect Vector register vrN selector (64 bit) + vrS_64_1=(21,25) + + vrS_32_0=(21,25) # AltVect Vector register vrN selector (32 bit) + vrS_32_1=(21,25) + vrS_32_2=(21,25) + vrS_32_3=(21,25) + + vrS_16_0=(21,25) # AltVect Vector register vrN selector (16 bit) + vrS_16_1=(21,25) + vrS_16_2=(21,25) + vrS_16_3=(21,25) + vrS_16_4=(21,25) + vrS_16_5=(21,25) + vrS_16_6=(21,25) + vrS_16_7=(21,25) + + vrS_8_0=(21,25) # AltVect Vector register vrN selector (8 bit) + vrS_8_1=(21,25) + vrS_8_2=(21,25) + vrS_8_3=(21,25) + vrS_8_4=(21,25) + vrS_8_5=(21,25) + vrS_8_6=(21,25) + vrS_8_7=(21,25) + vrS_8_8=(21,25) + vrS_8_9=(21,25) + vrS_8_10=(21,25) + vrS_8_11=(21,25) + vrS_8_12=(21,25) + vrS_8_13=(21,25) + vrS_8_14=(21,25) + vrS_8_15=(21,25) + + WC=(21,22) + + XOP_0_10=(0,10) + XOP_0_5=(0,5) + XOP_0_8=(0,8) + XOP_0_9=(0,9) + XOP_1_10=(1,10) + XOP_1_4=(1,4) + XOP_1_5=(1,5) + XOP_1_8=(1,8) + XOP_1_9=(1,9) + XOP_2_10=(2,10) + XOP_2_4=(2,4) + XOP_3_5=(3,5) + XOP_3_10=(3,10) + XOP_3_9=(3,9) + XOP_7_10=(7,10) +# support VSX args + Avsa=(16,20) + Avsb=(16,20) + Bvsa=(11,15) + Bvsb=(11,15) + Cvsa=(6,10) + Cvsb=(6,10) + Svsa=(21,25) + Svsb=(21,25) + Svsbx=(21,25) + Tvsa=(21,25) + Tvsb=(21,25) + Tvsbx=(21,25) + + BD15_VLE=(1,15) signed + BD24_VLE=(1,24) signed + BF_VLE=(21,22) + BI_CC_VLE=(16,17) + BI_CR_VLE=(18,19) + BO_VLE=(20,21) + + IMM8=(0,7) + IMM_0_10_VLE=(0,10) + IMM_11_15_VLE=(11,14) + IMM_16_20_VLE=(16,20) + IMM_21_25_VLE=(21,25) + SIMM_11_14_VLE=(11,14) signed + SIMM_21_25_VLE=(21,25) signed + SCL_VLE=(8,9) + + LEV_VLE=(11,15) + XOP_8_VLE=(8,15) + XOP_11_VLE=(11,15) + XOP_12_VLE=(12,15) + + XOP_VLE=(22,25) +; + +define token instrvle(16) + OP4_VLE=(12,15) + OP5_VLE=(11,15) + OP6_VLE=(10,15) + OP15_VLE=(1,15) + OP16_VLE=(0,15) + + OIM5_VLE=(4,8) + OIM7_VLE=(4,10) + SD4_VLE=(8,11) + UI7_VLE=(4,10) + UI5_VLE=(4,8) + XORR_VLE=(8,9) + XOR_VLE=(4,9) + + ARX_VLE=(0,3) + ARY_VLE=(4,7) + RY_VLE=(4,7) + RZ_VLE=(4,7) + RX_VLE=(0,3) + + BO16_VLE=(10,10) + BIT9_VLE=(9,9) + BIT8_VLE=(8,8) + BI16_VLE=(8,9) + BITS_8_9=(8,9) + BD8_VLE=(0,7) signed + + LK8_VLE=(8,8) + LK0_VLE=(0,0) +; + +EVUIMM_2_RAt: val^"("^A^")" is A & EVUIMM_2 [ val = EVUIMM_2*2; ] { tmp:4 = A+(EVUIMM_2*2); export tmp; } +EVUIMM_4_RAt: val^"("^A^")" is A & EVUIMM_4 [ val = EVUIMM_4*4; ] { tmp:4 = A+(EVUIMM_4*4); export tmp; } +EVUIMM_8_RAt: val^"("^A^")" is A & EVUIMM_8 [ val = EVUIMM_8*8; ] { tmp:4 = A+(EVUIMM_8*8); export tmp; } + +attach variables [ T ] + [ vs0 vs1 vs2 vs3 vs4 vs5 vs6 vs7 vs8 vs9 vs10 vs11 vs12 vs13 vs14 vs15 + vs16 vs17 vs18 vs19 vs20 vs21 vs22 vs23 vs24 vs25 vs26 vs27 vs28 vs29 vs30 vs31 + ]; + +attach variables [ RX_VLE RY_VLE RZ_VLE] + [ r0 r1 r2 r3 r4 r5 r6 r7 r24 r25 r26 r27 r28 r29 r30 r31]; + +attach variables [ ARX_VLE ARY_VLE] + [ r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23]; + +attach variables [ D A B C S TH RA RB RS RT regp] + [ r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 + r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 ]; + +attach variables [ BFA BI_CR CRFD CRFS CR_A CR_B CR_D CR_X ] + [cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7] ; + +attach variables [ BI_CR_VLE BF_VLE ] + [cr0 cr1 cr2 cr3 ] ; + +attach variables [ fD fB fA fC fS fT ] + [ f0 f1 f2 f3 f4 f5 f6 f7 + f8 f9 f10 f11 f12 f13 f14 f15 + f16 f17 f18 f19 f20 f21 f22 f23 + f24 f25 f26 f27 f28 f29 f30 f31 ]; + +attach variables [ CRBD CRBR ] + [ fp_fx fp_fex fp_vx fp_ox + fp_ux fp_zx fp_xx fp_vxsnan + fp_vxisi fp_vxidi fp_vxzdz fp_vximz + fp_vxvc fp_fr fp_fi fp_c + fp_cc0 fp_cc1 fp_cc2 fp_cc3 + fp_reserve1 fp_vxsoft fp_vxsqrt fp_vxcvi + fp_ve fp_oe fp_ue fp_ze + fp_xe fp_ni fp_rn0 fp_rn1 + ]; + +attach variables SR [ + sr0 sr1 sr2 sr3 sr4 sr5 sr6 sr7 sr8 sr9 sr10 sr11 sr12 sr13 sr14 sr15 ]; + +## +## Attach the spr register to the token SPRVAL made up of the bits sprL/sprH +## the low bits are shifted up, so the table is inverted and indexed by sprH,sprL +## This could have been done by computing sprVal = sprH * 32 + sprL but it would +## have resulted in multiple instructions instead of the original single prototype. +## Thus this massive inverted table. +attach variables SPRVAL [ + spr000 spr020 spr040 spr060 spr080 spr0a0 spr0c0 spr0e0 spr100 spr120 spr140 spr160 spr180 spr1a0 spr1c0 spr1e0 spr200 spr220 spr240 spr260 spr280 spr2a0 spr2c0 spr2e0 spr300 spr320 spr340 spr360 spr380 spr3a0 spr3c0 spr3e0 + XER spr021 spr041 spr061 spr081 spr0a1 spr0c1 spr0e1 spr101 spr121 spr141 spr161 spr181 spr1a1 spr1c1 spr1e1 spr201 spr221 spr241 spr261 spr281 spr2a1 spr2c1 spr2e1 spr301 spr321 spr341 spr361 spr381 spr3a1 spr3c1 spr3e1 + spr002 spr022 spr042 spr062 spr082 spr0a2 spr0c2 spr0e2 spr102 spr122 spr142 spr162 spr182 spr1a2 spr1c2 spr1e2 spr202 spr222 spr242 spr262 spr282 spr2a2 spr2c2 spr2e2 spr302 spr322 spr342 spr362 spr382 spr3a2 spr3c2 spr3e2 + spr003 spr023 spr043 spr063 spr083 spr0a3 spr0c3 spr0e3 spr103 spr123 spr143 spr163 spr183 spr1a3 spr1c3 spr1e3 spr203 spr223 spr243 spr263 spr283 spr2a3 spr2c3 spr2e3 spr303 spr323 spr343 spr363 spr383 spr3a3 spr3c3 spr3e3 + spr004 spr024 spr044 spr064 spr084 spr0a4 spr0c4 spr0e4 spr104 spr124 spr144 spr164 spr184 spr1a4 spr1c4 spr1e4 spr204 spr224 spr244 spr264 spr284 spr2a4 spr2c4 spr2e4 spr304 spr324 spr344 spr364 spr384 spr3a4 spr3c4 spr3e4 + spr005 spr025 spr045 spr065 spr085 spr0a5 spr0c5 spr0e5 spr105 spr125 spr145 spr165 spr185 spr1a5 spr1c5 spr1e5 spr205 spr225 spr245 spr265 spr285 spr2a5 spr2c5 spr2e5 spr305 spr325 spr345 spr365 spr385 spr3a5 spr3c5 spr3e5 + spr006 spr026 spr046 spr066 spr086 spr0a6 spr0c6 spr0e6 spr106 spr126 spr146 spr166 spr186 spr1a6 spr1c6 spr1e6 spr206 spr226 spr246 spr266 spr286 spr2a6 spr2c6 spr2e6 spr306 spr326 spr346 spr366 spr386 spr3a6 spr3c6 spr3e6 + spr007 spr027 spr047 spr067 spr087 spr0a7 spr0c7 spr0e7 spr107 spr127 spr147 spr167 spr187 spr1a7 spr1c7 spr1e7 spr207 spr227 spr247 spr267 spr287 spr2a7 spr2c7 spr2e7 spr307 spr327 spr347 spr367 spr387 spr3a7 spr3c7 spr3e7 + LR spr028 spr048 spr068 spr088 spr0a8 spr0c8 spr0e8 spr108 spr128 spr148 spr168 spr188 spr1a8 spr1c8 spr1e8 spr208 spr228 spr248 spr268 spr288 spr2a8 spr2c8 spr2e8 spr308 spr328 spr348 spr368 spr388 spr3a8 spr3c8 spr3e8 + CTR spr029 spr049 spr069 spr089 spr0a9 spr0c9 spr0e9 spr109 spr129 spr149 spr169 spr189 spr1a9 spr1c9 spr1e9 spr209 spr229 spr249 spr269 spr289 spr2a9 spr2c9 spr2e9 spr309 spr329 spr349 spr369 spr389 spr3a9 spr3c9 spr3e9 + spr00a spr02a spr04a spr06a spr08a spr0aa spr0ca spr0ea spr10a spr12a spr14a spr16a spr18a spr1aa spr1ca spr1ea spr20a spr22a spr24a spr26a spr28a spr2aa spr2ca spr2ea spr30a spr32a spr34a spr36a spr38a spr3aa spr3ca spr3ea + spr00b spr02b spr04b spr06b spr08b spr0ab spr0cb spr0eb spr10b spr12b spr14b spr16b spr18b spr1ab spr1cb spr1eb spr20b spr22b spr24b spr26b spr28b spr2ab spr2cb spr2eb spr30b spr32b spr34b spr36b spr38b spr3ab spr3cb spr3eb + spr00c spr02c spr04c spr06c spr08c spr0ac spr0cc spr0ec TBLr spr12c spr14c spr16c spr18c spr1ac spr1cc spr1ec spr20c spr22c spr24c spr26c spr28c spr2ac spr2cc spr2ec spr30c spr32c spr34c spr36c spr38c spr3ac spr3cc spr3ec + spr00d spr02d spr04d spr06d spr08d spr0ad spr0cd spr0ed TBUr spr12d spr14d spr16d spr18d spr1ad spr1cd spr1ed spr20d spr22d spr24d spr26d spr28d spr2ad spr2cd spr2ed spr30d spr32d spr34d spr36d spr38d spr3ad spr3cd spr3ed + spr00e spr02e spr04e spr06e spr08e spr0ae spr0ce spr0ee spr10e spr12e spr14e spr16e spr18e spr1ae spr1ce spr1ee spr20e spr22e spr24e spr26e spr28e spr2ae spr2ce spr2ee spr30e spr32e spr34e spr36e spr38e spr3ae spr3ce spr3ee + spr00f spr02f spr04f spr06f spr08f spr0af spr0cf spr0ef spr10f spr12f spr14f spr16f spr18f spr1af spr1cf spr1ef spr20f spr22f spr24f spr26f spr28f spr2af spr2cf spr2ef spr30f TAR spr34f spr36f spr38f spr3af spr3cf spr3ef + spr010 spr030 spr050 spr070 spr090 spr0b0 spr0d0 spr0f0 spr110 spr130 spr150 spr170 spr190 spr1b0 spr1d0 spr1f0 spr210 spr230 spr250 spr270 spr290 spr2b0 spr2d0 spr2f0 spr310 spr330 spr350 spr370 spr390 spr3b0 spr3d0 spr3f0 + spr011 spr031 spr051 spr071 spr091 spr0b1 spr0d1 spr0f1 spr111 spr131 spr151 spr171 spr191 spr1b1 spr1d1 spr1f1 spr211 spr231 spr251 spr271 spr291 spr2b1 spr2d1 spr2f1 spr311 spr331 spr351 spr371 spr391 spr3b1 spr3d1 spr3f1 + spr012 spr032 spr052 spr072 spr092 spr0b2 spr0d2 spr0f2 spr112 spr132 spr152 spr172 spr192 spr1b2 spr1d2 spr1f2 spr212 spr232 spr252 spr272 spr292 spr2b2 spr2d2 spr2f2 spr312 spr332 spr352 spr372 spr392 spr3b2 spr3d2 spr3f2 + spr013 spr033 spr053 spr073 spr093 spr0b3 spr0d3 spr0f3 spr113 spr133 spr153 spr173 spr193 spr1b3 spr1d3 spr1f3 spr213 spr233 spr253 spr273 spr293 spr2b3 spr2d3 spr2f3 spr313 spr333 spr353 spr373 spr393 spr3b3 spr3d3 spr3f3 + spr014 spr034 spr054 spr074 spr094 spr0b4 spr0d4 spr0f4 spr114 spr134 spr154 spr174 spr194 spr1b4 spr1d4 spr1f4 spr214 spr234 spr254 spr274 spr294 spr2b4 spr2d4 spr2f4 spr314 spr334 spr354 spr374 spr394 spr3b4 spr3d4 spr3f4 + spr015 spr035 spr055 spr075 spr095 spr0b5 spr0d5 spr0f5 spr115 spr135 spr155 spr175 spr195 spr1b5 spr1d5 spr1f5 spr215 spr235 spr255 spr275 spr295 spr2b5 spr2d5 spr2f5 spr315 spr335 spr355 spr375 spr395 spr3b5 spr3d5 spr3f5 + spr016 spr036 spr056 spr076 spr096 spr0b6 spr0d6 spr0f6 spr116 spr136 spr156 spr176 spr196 spr1b6 spr1d6 spr1f6 spr216 spr236 spr256 spr276 spr296 spr2b6 spr2d6 spr2f6 spr316 spr336 spr356 spr376 spr396 spr3b6 spr3d6 spr3f6 + spr017 spr037 spr057 spr077 spr097 spr0b7 spr0d7 spr0f7 spr117 spr137 spr157 spr177 spr197 spr1b7 spr1d7 spr1f7 spr217 spr237 spr257 spr277 spr297 spr2b7 spr2d7 spr2f7 spr317 spr337 spr357 spr377 spr397 spr3b7 spr3d7 spr3f7 + spr018 spr038 spr058 spr078 spr098 spr0b8 spr0d8 spr0f8 spr118 spr138 spr158 spr178 spr198 spr1b8 spr1d8 spr1f8 spr218 spr238 spr258 spr278 spr298 spr2b8 spr2d8 spr2f8 spr318 spr338 spr358 spr378 spr398 spr3b8 spr3d8 spr3f8 + spr019 spr039 spr059 spr079 spr099 spr0b9 spr0d9 spr0f9 spr119 spr139 spr159 spr179 spr199 spr1b9 spr1d9 spr1f9 spr219 spr239 spr259 spr279 spr299 spr2b9 spr2d9 spr2f9 spr319 spr339 spr359 spr379 spr399 spr3b9 spr3d9 spr3f9 + SRR0 CSRR0 spr05a spr07a spr09a spr0ba spr0da spr0fa spr11a spr13a spr15a spr17a spr19a spr1ba spr1da spr1fa spr21a spr23a spr25a spr27a spr29a spr2ba spr2da spr2fa spr31a spr33a spr35a spr37a spr39a spr3ba spr3da spr3fa + SRR1 CSRR1 spr05b spr07b spr09b spr0bb spr0db spr0fb spr11b spr13b spr15b spr17b spr19b spr1bb spr1db spr1fb spr21b spr23b spr25b spr27b spr29b spr2bb spr2db spr2fb spr31b spr33b spr35b spr37b spr39b spr3bb spr3db spr3fb + spr01c spr03c spr05c spr07c spr09c spr0bc spr0dc spr0fc TBLw spr13c spr15c spr17c spr19c spr1bc spr1dc spr1fc spr21c spr23c spr25c spr27c spr29c spr2bc spr2dc spr2fc spr31c spr33c spr35c spr37c spr39c spr3bc spr3dc spr3fc + spr01d spr03d spr05d spr07d spr09d spr0bd spr0dd spr0fd TBUw spr13d spr15d spr17d spr19d spr1bd spr1dd spr1fd spr21d spr23d spr25d spr27d spr29d spr2bd spr2dd spr2fd spr31d spr33d spr35d spr37d spr39d spr3bd spr3dd spr3fd + spr01e spr03e spr05e spr07e spr09e spr0be spr0de spr0fe spr11e spr13e spr15e spr17e spr19e spr1be spr1de spr1fe spr21e spr23e spr25e spr27e spr29e spr2be spr2de spr2fe spr31e spr33e spr35e spr37e spr39e spr3be spr3de spr3fe + spr01f spr03f spr05f spr07f spr09f spr0bf spr0df spr0ff spr11f spr13f spr15f spr17f spr19f spr1bf spr1df spr1ff spr21f spr23f spr25f spr27f spr29f spr2bf spr2df spr2ff spr31f spr33f spr35f spr37f spr39f spr3bf spr3df spr3ff +]; + +## +## Attach the dcr register to the token DCRN made up of the bits dcrnL/dcrnH +## the low bits are shifted up, so the table is inverted and indexed by dcrnH,dcrnL +## This could have been done by computing DCRN = dcrnH * 32 + dcrnL but it would +## have resulted in multiple instructions instead of the original single prototype. +## Thus this massive inverted table. +attach variables DCRN [ + dcr000 dcr020 dcr040 dcr060 dcr080 dcr0a0 dcr0c0 dcr0e0 dcr100 dcr120 dcr140 dcr160 dcr180 dcr1a0 dcr1c0 dcr1e0 dcr200 dcr220 dcr240 dcr260 dcr280 dcr2a0 dcr2c0 dcr2e0 dcr300 dcr320 dcr340 dcr360 dcr380 dcr3a0 dcr3c0 dcr3e0 + dcr001 dcr021 dcr041 dcr061 dcr081 dcr0a1 dcr0c1 dcr0e1 dcr101 dcr121 dcr141 dcr161 dcr181 dcr1a1 dcr1c1 dcr1e1 dcr201 dcr221 dcr241 dcr261 dcr281 dcr2a1 dcr2c1 dcr2e1 dcr301 dcr321 dcr341 dcr361 dcr381 dcr3a1 dcr3c1 dcr3e1 + dcr002 dcr022 dcr042 dcr062 dcr082 dcr0a2 dcr0c2 dcr0e2 dcr102 dcr122 dcr142 dcr162 dcr182 dcr1a2 dcr1c2 dcr1e2 dcr202 dcr222 dcr242 dcr262 dcr282 dcr2a2 dcr2c2 dcr2e2 dcr302 dcr322 dcr342 dcr362 dcr382 dcr3a2 dcr3c2 dcr3e2 + dcr003 dcr023 dcr043 dcr063 dcr083 dcr0a3 dcr0c3 dcr0e3 dcr103 dcr123 dcr143 dcr163 dcr183 dcr1a3 dcr1c3 dcr1e3 dcr203 dcr223 dcr243 dcr263 dcr283 dcr2a3 dcr2c3 dcr2e3 dcr303 dcr323 dcr343 dcr363 dcr383 dcr3a3 dcr3c3 dcr3e3 + dcr004 dcr024 dcr044 dcr064 dcr084 dcr0a4 dcr0c4 dcr0e4 dcr104 dcr124 dcr144 dcr164 dcr184 dcr1a4 dcr1c4 dcr1e4 dcr204 dcr224 dcr244 dcr264 dcr284 dcr2a4 dcr2c4 dcr2e4 dcr304 dcr324 dcr344 dcr364 dcr384 dcr3a4 dcr3c4 dcr3e4 + dcr005 dcr025 dcr045 dcr065 dcr085 dcr0a5 dcr0c5 dcr0e5 dcr105 dcr125 dcr145 dcr165 dcr185 dcr1a5 dcr1c5 dcr1e5 dcr205 dcr225 dcr245 dcr265 dcr285 dcr2a5 dcr2c5 dcr2e5 dcr305 dcr325 dcr345 dcr365 dcr385 dcr3a5 dcr3c5 dcr3e5 + dcr006 dcr026 dcr046 dcr066 dcr086 dcr0a6 dcr0c6 dcr0e6 dcr106 dcr126 dcr146 dcr166 dcr186 dcr1a6 dcr1c6 dcr1e6 dcr206 dcr226 dcr246 dcr266 dcr286 dcr2a6 dcr2c6 dcr2e6 dcr306 dcr326 dcr346 dcr366 dcr386 dcr3a6 dcr3c6 dcr3e6 + dcr007 dcr027 dcr047 dcr067 dcr087 dcr0a7 dcr0c7 dcr0e7 dcr107 dcr127 dcr147 dcr167 dcr187 dcr1a7 dcr1c7 dcr1e7 dcr207 dcr227 dcr247 dcr267 dcr287 dcr2a7 dcr2c7 dcr2e7 dcr307 dcr327 dcr347 dcr367 dcr387 dcr3a7 dcr3c7 dcr3e7 + dcr008 dcr028 dcr048 dcr068 dcr088 dcr0a8 dcr0c8 dcr0e8 dcr108 dcr128 dcr148 dcr168 dcr188 dcr1a8 dcr1c8 dcr1e8 dcr208 dcr228 dcr248 dcr268 dcr288 dcr2a8 dcr2c8 dcr2e8 dcr308 dcr328 dcr348 dcr368 dcr388 dcr3a8 dcr3c8 dcr3e8 + dcr009 dcr029 dcr049 dcr069 dcr089 dcr0a9 dcr0c9 dcr0e9 dcr109 dcr129 dcr149 dcr169 dcr189 dcr1a9 dcr1c9 dcr1e9 dcr209 dcr229 dcr249 dcr269 dcr289 dcr2a9 dcr2c9 dcr2e9 dcr309 dcr329 dcr349 dcr369 dcr389 dcr3a9 dcr3c9 dcr3e9 + dcr00a dcr02a dcr04a dcr06a dcr08a dcr0aa dcr0ca dcr0ea dcr10a dcr12a dcr14a dcr16a dcr18a dcr1aa dcr1ca dcr1ea dcr20a dcr22a dcr24a dcr26a dcr28a dcr2aa dcr2ca dcr2ea dcr30a dcr32a dcr34a dcr36a dcr38a dcr3aa dcr3ca dcr3ea + dcr00b dcr02b dcr04b dcr06b dcr08b dcr0ab dcr0cb dcr0eb dcr10b dcr12b dcr14b dcr16b dcr18b dcr1ab dcr1cb dcr1eb dcr20b dcr22b dcr24b dcr26b dcr28b dcr2ab dcr2cb dcr2eb dcr30b dcr32b dcr34b dcr36b dcr38b dcr3ab dcr3cb dcr3eb + dcr00c dcr02c dcr04c dcr06c dcr08c dcr0ac dcr0cc dcr0ec dcr10c dcr12c dcr14c dcr16c dcr18c dcr1ac dcr1cc dcr1ec dcr20c dcr22c dcr24c dcr26c dcr28c dcr2ac dcr2cc dcr2ec dcr30c dcr32c dcr34c dcr36c dcr38c dcr3ac dcr3cc dcr3ec + dcr00d dcr02d dcr04d dcr06d dcr08d dcr0ad dcr0cd dcr0ed dcr10d dcr12d dcr14d dcr16d dcr18d dcr1ad dcr1cd dcr1ed dcr20d dcr22d dcr24d dcr26d dcr28d dcr2ad dcr2cd dcr2ed dcr30d dcr32d dcr34d dcr36d dcr38d dcr3ad dcr3cd dcr3ed + dcr00e dcr02e dcr04e dcr06e dcr08e dcr0ae dcr0ce dcr0ee dcr10e dcr12e dcr14e dcr16e dcr18e dcr1ae dcr1ce dcr1ee dcr20e dcr22e dcr24e dcr26e dcr28e dcr2ae dcr2ce dcr2ee dcr30e dcr32e dcr34e dcr36e dcr38e dcr3ae dcr3ce dcr3ee + dcr00f dcr02f dcr04f dcr06f dcr08f dcr0af dcr0cf dcr0ef dcr10f dcr12f dcr14f dcr16f dcr18f dcr1af dcr1cf dcr1ef dcr20f dcr22f dcr24f dcr26f dcr28f dcr2af dcr2cf dcr2ef dcr30f dcr32f dcr34f dcr36f dcr38f dcr3af dcr3cf dcr3ef + dcr010 dcr030 dcr050 dcr070 dcr090 dcr0b0 dcr0d0 dcr0f0 dcr110 dcr130 dcr150 dcr170 dcr190 dcr1b0 dcr1d0 dcr1f0 dcr210 dcr230 dcr250 dcr270 dcr290 dcr2b0 dcr2d0 dcr2f0 dcr310 dcr330 dcr350 dcr370 dcr390 dcr3b0 dcr3d0 dcr3f0 + dcr011 dcr031 dcr051 dcr071 dcr091 dcr0b1 dcr0d1 dcr0f1 dcr111 dcr131 dcr151 dcr171 dcr191 dcr1b1 dcr1d1 dcr1f1 dcr211 dcr231 dcr251 dcr271 dcr291 dcr2b1 dcr2d1 dcr2f1 dcr311 dcr331 dcr351 dcr371 dcr391 dcr3b1 dcr3d1 dcr3f1 + dcr012 dcr032 dcr052 dcr072 dcr092 dcr0b2 dcr0d2 dcr0f2 dcr112 dcr132 dcr152 dcr172 dcr192 dcr1b2 dcr1d2 dcr1f2 dcr212 dcr232 dcr252 dcr272 dcr292 dcr2b2 dcr2d2 dcr2f2 dcr312 dcr332 dcr352 dcr372 dcr392 dcr3b2 dcr3d2 dcr3f2 + dcr013 dcr033 dcr053 dcr073 dcr093 dcr0b3 dcr0d3 dcr0f3 dcr113 dcr133 dcr153 dcr173 dcr193 dcr1b3 dcr1d3 dcr1f3 dcr213 dcr233 dcr253 dcr273 dcr293 dcr2b3 dcr2d3 dcr2f3 dcr313 dcr333 dcr353 dcr373 dcr393 dcr3b3 dcr3d3 dcr3f3 + dcr014 dcr034 dcr054 dcr074 dcr094 dcr0b4 dcr0d4 dcr0f4 dcr114 dcr134 dcr154 dcr174 dcr194 dcr1b4 dcr1d4 dcr1f4 dcr214 dcr234 dcr254 dcr274 dcr294 dcr2b4 dcr2d4 dcr2f4 dcr314 dcr334 dcr354 dcr374 dcr394 dcr3b4 dcr3d4 dcr3f4 + dcr015 dcr035 dcr055 dcr075 dcr095 dcr0b5 dcr0d5 dcr0f5 dcr115 dcr135 dcr155 dcr175 dcr195 dcr1b5 dcr1d5 dcr1f5 dcr215 dcr235 dcr255 dcr275 dcr295 dcr2b5 dcr2d5 dcr2f5 dcr315 dcr335 dcr355 dcr375 dcr395 dcr3b5 dcr3d5 dcr3f5 + dcr016 dcr036 dcr056 dcr076 dcr096 dcr0b6 dcr0d6 dcr0f6 dcr116 dcr136 dcr156 dcr176 dcr196 dcr1b6 dcr1d6 dcr1f6 dcr216 dcr236 dcr256 dcr276 dcr296 dcr2b6 dcr2d6 dcr2f6 dcr316 dcr336 dcr356 dcr376 dcr396 dcr3b6 dcr3d6 dcr3f6 + dcr017 dcr037 dcr057 dcr077 dcr097 dcr0b7 dcr0d7 dcr0f7 dcr117 dcr137 dcr157 dcr177 dcr197 dcr1b7 dcr1d7 dcr1f7 dcr217 dcr237 dcr257 dcr277 dcr297 dcr2b7 dcr2d7 dcr2f7 dcr317 dcr337 dcr357 dcr377 dcr397 dcr3b7 dcr3d7 dcr3f7 + dcr018 dcr038 dcr058 dcr078 dcr098 dcr0b8 dcr0d8 dcr0f8 dcr118 dcr138 dcr158 dcr178 dcr198 dcr1b8 dcr1d8 dcr1f8 dcr218 dcr238 dcr258 dcr278 dcr298 dcr2b8 dcr2d8 dcr2f8 dcr318 dcr338 dcr358 dcr378 dcr398 dcr3b8 dcr3d8 dcr3f8 + dcr019 dcr039 dcr059 dcr079 dcr099 dcr0b9 dcr0d9 dcr0f9 dcr119 dcr139 dcr159 dcr179 dcr199 dcr1b9 dcr1d9 dcr1f9 dcr219 dcr239 dcr259 dcr279 dcr299 dcr2b9 dcr2d9 dcr2f9 dcr319 dcr339 dcr359 dcr379 dcr399 dcr3b9 dcr3d9 dcr3f9 + dcr01a dcr03a dcr05a dcr07a dcr09a dcr0ba dcr0da dcr0fa dcr11a dcr13a dcr15a dcr17a dcr19a dcr1ba dcr1da dcr1fa dcr21a dcr23a dcr25a dcr27a dcr29a dcr2ba dcr2da dcr2fa dcr31a dcr33a dcr35a dcr37a dcr39a dcr3ba dcr3da dcr3fa + dcr01b dcr03b dcr05b dcr07b dcr09b dcr0bb dcr0db dcr0fb dcr11b dcr13b dcr15b dcr17b dcr19b dcr1bb dcr1db dcr1fb dcr21b dcr23b dcr25b dcr27b dcr29b dcr2bb dcr2db dcr2fb dcr31b dcr33b dcr35b dcr37b dcr39b dcr3bb dcr3db dcr3fb + dcr01c dcr03c dcr05c dcr07c dcr09c dcr0bc dcr0dc dcr0fc dcr11c dcr13c dcr15c dcr17c dcr19c dcr1bc dcr1dc dcr1fc dcr21c dcr23c dcr25c dcr27c dcr29c dcr2bc dcr2dc dcr2fc dcr31c dcr33c dcr35c dcr37c dcr39c dcr3bc dcr3dc dcr3fc + dcr01d dcr03d dcr05d dcr07d dcr09d dcr0bd dcr0dd dcr0fd dcr11d dcr13d dcr15d dcr17d dcr19d dcr1bd dcr1dd dcr1fd dcr21d dcr23d dcr25d dcr27d dcr29d dcr2bd dcr2dd dcr2fd dcr31d dcr33d dcr35d dcr37d dcr39d dcr3bd dcr3dd dcr3fd + dcr01e dcr03e dcr05e dcr07e dcr09e dcr0be dcr0de dcr0fe dcr11e dcr13e dcr15e dcr17e dcr19e dcr1be dcr1de dcr1fe dcr21e dcr23e dcr25e dcr27e dcr29e dcr2be dcr2de dcr2fe dcr31e dcr33e dcr35e dcr37e dcr39e dcr3be dcr3de dcr3fe + dcr01f dcr03f dcr05f dcr07f dcr09f dcr0bf dcr0df dcr0ff dcr11f dcr13f dcr15f dcr17f dcr19f dcr1bf dcr1df dcr1ff dcr21f dcr23f dcr25f dcr27f dcr29f dcr2bf dcr2df dcr2ff dcr31f dcr33f dcr35f dcr37f dcr39f dcr3bf dcr3df dcr3ff +]; + +attach variables [vrDR vrAR vrBR vrSR vrCR] + [ vs32 vs33 vs34 vs35 vs36 vs37 vs38 vs39 vs40 vs41 vs42 vs43 vs44 vs45 vs46 vs47 + vs48 vs49 vs50 vs51 vs52 vs53 vs54 vs55 vs56 vs57 vs58 vs59 vs60 vs61 vs62 vs63 ]; + +## These attaches are for the Altivec instructions +attach names [ vrDD vrAD vrBD vrSD vrCD] + [ v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 + v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 ]; + +vrD: vrDD is vrDD & vrDR { export vrDR; } +vrA: vrAD is vrAD & vrAR { export vrAR; } +vrB: vrBD is vrBD & vrBR { export vrBR; } +vrC: vrCD is vrCD & vrCR { export vrCR; } +vrS: vrSD is vrSD & vrSR { export vrSR; } + +# AltVect Vector vrD sub-piece selectors + +# AltVect Vector vrD sub-piece selectors for size 64 +attach variables vrD_64_0 [vr0_64_0 vr1_64_0 vr2_64_0 vr3_64_0 vr4_64_0 vr5_64_0 vr6_64_0 vr7_64_0 vr8_64_0 vr9_64_0 vr10_64_0 vr11_64_0 vr12_64_0 vr13_64_0 vr14_64_0 vr15_64_0 vr16_64_0 vr17_64_0 vr18_64_0 vr19_64_0 vr20_64_0 vr21_64_0 vr22_64_0 vr23_64_0 vr24_64_0 vr25_64_0 vr26_64_0 vr27_64_0 vr28_64_0 vr29_64_0 vr30_64_0 vr31_64_0 ]; +attach variables vrD_64_1 [vr0_64_1 vr1_64_1 vr2_64_1 vr3_64_1 vr4_64_1 vr5_64_1 vr6_64_1 vr7_64_1 vr8_64_1 vr9_64_1 vr10_64_1 vr11_64_1 vr12_64_1 vr13_64_1 vr14_64_1 vr15_64_1 vr16_64_1 vr17_64_1 vr18_64_1 vr19_64_1 vr20_64_1 vr21_64_1 vr22_64_1 vr23_64_1 vr24_64_1 vr25_64_1 vr26_64_1 vr27_64_1 vr28_64_1 vr29_64_1 vr30_64_1 vr31_64_1 ]; + +# AltVect Vector vrD sub-piece selectors for size 32 +attach variables vrD_32_0 [vr0_32_0 vr1_32_0 vr2_32_0 vr3_32_0 vr4_32_0 vr5_32_0 vr6_32_0 vr7_32_0 vr8_32_0 vr9_32_0 vr10_32_0 vr11_32_0 vr12_32_0 vr13_32_0 vr14_32_0 vr15_32_0 vr16_32_0 vr17_32_0 vr18_32_0 vr19_32_0 vr20_32_0 vr21_32_0 vr22_32_0 vr23_32_0 vr24_32_0 vr25_32_0 vr26_32_0 vr27_32_0 vr28_32_0 vr29_32_0 vr30_32_0 vr31_32_0 ]; +attach variables vrD_32_1 [vr0_32_1 vr1_32_1 vr2_32_1 vr3_32_1 vr4_32_1 vr5_32_1 vr6_32_1 vr7_32_1 vr8_32_1 vr9_32_1 vr10_32_1 vr11_32_1 vr12_32_1 vr13_32_1 vr14_32_1 vr15_32_1 vr16_32_1 vr17_32_1 vr18_32_1 vr19_32_1 vr20_32_1 vr21_32_1 vr22_32_1 vr23_32_1 vr24_32_1 vr25_32_1 vr26_32_1 vr27_32_1 vr28_32_1 vr29_32_1 vr30_32_1 vr31_32_1 ]; +attach variables vrD_32_2 [vr0_32_2 vr1_32_2 vr2_32_2 vr3_32_2 vr4_32_2 vr5_32_2 vr6_32_2 vr7_32_2 vr8_32_2 vr9_32_2 vr10_32_2 vr11_32_2 vr12_32_2 vr13_32_2 vr14_32_2 vr15_32_2 vr16_32_2 vr17_32_2 vr18_32_2 vr19_32_2 vr20_32_2 vr21_32_2 vr22_32_2 vr23_32_2 vr24_32_2 vr25_32_2 vr26_32_2 vr27_32_2 vr28_32_2 vr29_32_2 vr30_32_2 vr31_32_2 ]; +attach variables vrD_32_3 [vr0_32_3 vr1_32_3 vr2_32_3 vr3_32_3 vr4_32_3 vr5_32_3 vr6_32_3 vr7_32_3 vr8_32_3 vr9_32_3 vr10_32_3 vr11_32_3 vr12_32_3 vr13_32_3 vr14_32_3 vr15_32_3 vr16_32_3 vr17_32_3 vr18_32_3 vr19_32_3 vr20_32_3 vr21_32_3 vr22_32_3 vr23_32_3 vr24_32_3 vr25_32_3 vr26_32_3 vr27_32_3 vr28_32_3 vr29_32_3 vr30_32_3 vr31_32_3 ]; + +# AltVect Vector vrD sub-piece selectors for size 16 +attach variables vrD_16_0 [vr0_16_0 vr1_16_0 vr2_16_0 vr3_16_0 vr4_16_0 vr5_16_0 vr6_16_0 vr7_16_0 vr8_16_0 vr9_16_0 vr10_16_0 vr11_16_0 vr12_16_0 vr13_16_0 vr14_16_0 vr15_16_0 vr16_16_0 vr17_16_0 vr18_16_0 vr19_16_0 vr20_16_0 vr21_16_0 vr22_16_0 vr23_16_0 vr24_16_0 vr25_16_0 vr26_16_0 vr27_16_0 vr28_16_0 vr29_16_0 vr30_16_0 vr31_16_0 ]; +attach variables vrD_16_1 [vr0_16_1 vr1_16_1 vr2_16_1 vr3_16_1 vr4_16_1 vr5_16_1 vr6_16_1 vr7_16_1 vr8_16_1 vr9_16_1 vr10_16_1 vr11_16_1 vr12_16_1 vr13_16_1 vr14_16_1 vr15_16_1 vr16_16_1 vr17_16_1 vr18_16_1 vr19_16_1 vr20_16_1 vr21_16_1 vr22_16_1 vr23_16_1 vr24_16_1 vr25_16_1 vr26_16_1 vr27_16_1 vr28_16_1 vr29_16_1 vr30_16_1 vr31_16_1 ]; +attach variables vrD_16_2 [vr0_16_2 vr1_16_2 vr2_16_2 vr3_16_2 vr4_16_2 vr5_16_2 vr6_16_2 vr7_16_2 vr8_16_2 vr9_16_2 vr10_16_2 vr11_16_2 vr12_16_2 vr13_16_2 vr14_16_2 vr15_16_2 vr16_16_2 vr17_16_2 vr18_16_2 vr19_16_2 vr20_16_2 vr21_16_2 vr22_16_2 vr23_16_2 vr24_16_2 vr25_16_2 vr26_16_2 vr27_16_2 vr28_16_2 vr29_16_2 vr30_16_2 vr31_16_2 ]; +attach variables vrD_16_3 [vr0_16_3 vr1_16_3 vr2_16_3 vr3_16_3 vr4_16_3 vr5_16_3 vr6_16_3 vr7_16_3 vr8_16_3 vr9_16_3 vr10_16_3 vr11_16_3 vr12_16_3 vr13_16_3 vr14_16_3 vr15_16_3 vr16_16_3 vr17_16_3 vr18_16_3 vr19_16_3 vr20_16_3 vr21_16_3 vr22_16_3 vr23_16_3 vr24_16_3 vr25_16_3 vr26_16_3 vr27_16_3 vr28_16_3 vr29_16_3 vr30_16_3 vr31_16_3 ]; +attach variables vrD_16_4 [vr0_16_4 vr1_16_4 vr2_16_4 vr3_16_4 vr4_16_4 vr5_16_4 vr6_16_4 vr7_16_4 vr8_16_4 vr9_16_4 vr10_16_4 vr11_16_4 vr12_16_4 vr13_16_4 vr14_16_4 vr15_16_4 vr16_16_4 vr17_16_4 vr18_16_4 vr19_16_4 vr20_16_4 vr21_16_4 vr22_16_4 vr23_16_4 vr24_16_4 vr25_16_4 vr26_16_4 vr27_16_4 vr28_16_4 vr29_16_4 vr30_16_4 vr31_16_4 ]; +attach variables vrD_16_5 [vr0_16_5 vr1_16_5 vr2_16_5 vr3_16_5 vr4_16_5 vr5_16_5 vr6_16_5 vr7_16_5 vr8_16_5 vr9_16_5 vr10_16_5 vr11_16_5 vr12_16_5 vr13_16_5 vr14_16_5 vr15_16_5 vr16_16_5 vr17_16_5 vr18_16_5 vr19_16_5 vr20_16_5 vr21_16_5 vr22_16_5 vr23_16_5 vr24_16_5 vr25_16_5 vr26_16_5 vr27_16_5 vr28_16_5 vr29_16_5 vr30_16_5 vr31_16_5 ]; +attach variables vrD_16_6 [vr0_16_6 vr1_16_6 vr2_16_6 vr3_16_6 vr4_16_6 vr5_16_6 vr6_16_6 vr7_16_6 vr8_16_6 vr9_16_6 vr10_16_6 vr11_16_6 vr12_16_6 vr13_16_6 vr14_16_6 vr15_16_6 vr16_16_6 vr17_16_6 vr18_16_6 vr19_16_6 vr20_16_6 vr21_16_6 vr22_16_6 vr23_16_6 vr24_16_6 vr25_16_6 vr26_16_6 vr27_16_6 vr28_16_6 vr29_16_6 vr30_16_6 vr31_16_6 ]; +attach variables vrD_16_7 [vr0_16_7 vr1_16_7 vr2_16_7 vr3_16_7 vr4_16_7 vr5_16_7 vr6_16_7 vr7_16_7 vr8_16_7 vr9_16_7 vr10_16_7 vr11_16_7 vr12_16_7 vr13_16_7 vr14_16_7 vr15_16_7 vr16_16_7 vr17_16_7 vr18_16_7 vr19_16_7 vr20_16_7 vr21_16_7 vr22_16_7 vr23_16_7 vr24_16_7 vr25_16_7 vr26_16_7 vr27_16_7 vr28_16_7 vr29_16_7 vr30_16_7 vr31_16_7 ]; + +# AltVect Vector vrD sub-piece selectors for size 8 +attach variables vrD_8_0 [vr0_8_0 vr1_8_0 vr2_8_0 vr3_8_0 vr4_8_0 vr5_8_0 vr6_8_0 vr7_8_0 vr8_8_0 vr9_8_0 vr10_8_0 vr11_8_0 vr12_8_0 vr13_8_0 vr14_8_0 vr15_8_0 vr16_8_0 vr17_8_0 vr18_8_0 vr19_8_0 vr20_8_0 vr21_8_0 vr22_8_0 vr23_8_0 vr24_8_0 vr25_8_0 vr26_8_0 vr27_8_0 vr28_8_0 vr29_8_0 vr30_8_0 vr31_8_0 ]; +attach variables vrD_8_1 [vr0_8_1 vr1_8_1 vr2_8_1 vr3_8_1 vr4_8_1 vr5_8_1 vr6_8_1 vr7_8_1 vr8_8_1 vr9_8_1 vr10_8_1 vr11_8_1 vr12_8_1 vr13_8_1 vr14_8_1 vr15_8_1 vr16_8_1 vr17_8_1 vr18_8_1 vr19_8_1 vr20_8_1 vr21_8_1 vr22_8_1 vr23_8_1 vr24_8_1 vr25_8_1 vr26_8_1 vr27_8_1 vr28_8_1 vr29_8_1 vr30_8_1 vr31_8_1 ]; +attach variables vrD_8_2 [vr0_8_2 vr1_8_2 vr2_8_2 vr3_8_2 vr4_8_2 vr5_8_2 vr6_8_2 vr7_8_2 vr8_8_2 vr9_8_2 vr10_8_2 vr11_8_2 vr12_8_2 vr13_8_2 vr14_8_2 vr15_8_2 vr16_8_2 vr17_8_2 vr18_8_2 vr19_8_2 vr20_8_2 vr21_8_2 vr22_8_2 vr23_8_2 vr24_8_2 vr25_8_2 vr26_8_2 vr27_8_2 vr28_8_2 vr29_8_2 vr30_8_2 vr31_8_2 ]; +attach variables vrD_8_3 [vr0_8_3 vr1_8_3 vr2_8_3 vr3_8_3 vr4_8_3 vr5_8_3 vr6_8_3 vr7_8_3 vr8_8_3 vr9_8_3 vr10_8_3 vr11_8_3 vr12_8_3 vr13_8_3 vr14_8_3 vr15_8_3 vr16_8_3 vr17_8_3 vr18_8_3 vr19_8_3 vr20_8_3 vr21_8_3 vr22_8_3 vr23_8_3 vr24_8_3 vr25_8_3 vr26_8_3 vr27_8_3 vr28_8_3 vr29_8_3 vr30_8_3 vr31_8_3 ]; +attach variables vrD_8_4 [vr0_8_4 vr1_8_4 vr2_8_4 vr3_8_4 vr4_8_4 vr5_8_4 vr6_8_4 vr7_8_4 vr8_8_4 vr9_8_4 vr10_8_4 vr11_8_4 vr12_8_4 vr13_8_4 vr14_8_4 vr15_8_4 vr16_8_4 vr17_8_4 vr18_8_4 vr19_8_4 vr20_8_4 vr21_8_4 vr22_8_4 vr23_8_4 vr24_8_4 vr25_8_4 vr26_8_4 vr27_8_4 vr28_8_4 vr29_8_4 vr30_8_4 vr31_8_4 ]; +attach variables vrD_8_5 [vr0_8_5 vr1_8_5 vr2_8_5 vr3_8_5 vr4_8_5 vr5_8_5 vr6_8_5 vr7_8_5 vr8_8_5 vr9_8_5 vr10_8_5 vr11_8_5 vr12_8_5 vr13_8_5 vr14_8_5 vr15_8_5 vr16_8_5 vr17_8_5 vr18_8_5 vr19_8_5 vr20_8_5 vr21_8_5 vr22_8_5 vr23_8_5 vr24_8_5 vr25_8_5 vr26_8_5 vr27_8_5 vr28_8_5 vr29_8_5 vr30_8_5 vr31_8_5 ]; +attach variables vrD_8_6 [vr0_8_6 vr1_8_6 vr2_8_6 vr3_8_6 vr4_8_6 vr5_8_6 vr6_8_6 vr7_8_6 vr8_8_6 vr9_8_6 vr10_8_6 vr11_8_6 vr12_8_6 vr13_8_6 vr14_8_6 vr15_8_6 vr16_8_6 vr17_8_6 vr18_8_6 vr19_8_6 vr20_8_6 vr21_8_6 vr22_8_6 vr23_8_6 vr24_8_6 vr25_8_6 vr26_8_6 vr27_8_6 vr28_8_6 vr29_8_6 vr30_8_6 vr31_8_6 ]; +attach variables vrD_8_7 [vr0_8_7 vr1_8_7 vr2_8_7 vr3_8_7 vr4_8_7 vr5_8_7 vr6_8_7 vr7_8_7 vr8_8_7 vr9_8_7 vr10_8_7 vr11_8_7 vr12_8_7 vr13_8_7 vr14_8_7 vr15_8_7 vr16_8_7 vr17_8_7 vr18_8_7 vr19_8_7 vr20_8_7 vr21_8_7 vr22_8_7 vr23_8_7 vr24_8_7 vr25_8_7 vr26_8_7 vr27_8_7 vr28_8_7 vr29_8_7 vr30_8_7 vr31_8_7 ]; +attach variables vrD_8_8 [vr0_8_8 vr1_8_8 vr2_8_8 vr3_8_8 vr4_8_8 vr5_8_8 vr6_8_8 vr7_8_8 vr8_8_8 vr9_8_8 vr10_8_8 vr11_8_8 vr12_8_8 vr13_8_8 vr14_8_8 vr15_8_8 vr16_8_8 vr17_8_8 vr18_8_8 vr19_8_8 vr20_8_8 vr21_8_8 vr22_8_8 vr23_8_8 vr24_8_8 vr25_8_8 vr26_8_8 vr27_8_8 vr28_8_8 vr29_8_8 vr30_8_8 vr31_8_8 ]; +attach variables vrD_8_9 [vr0_8_9 vr1_8_9 vr2_8_9 vr3_8_9 vr4_8_9 vr5_8_9 vr6_8_9 vr7_8_9 vr8_8_9 vr9_8_9 vr10_8_9 vr11_8_9 vr12_8_9 vr13_8_9 vr14_8_9 vr15_8_9 vr16_8_9 vr17_8_9 vr18_8_9 vr19_8_9 vr20_8_9 vr21_8_9 vr22_8_9 vr23_8_9 vr24_8_9 vr25_8_9 vr26_8_9 vr27_8_9 vr28_8_9 vr29_8_9 vr30_8_9 vr31_8_9 ]; +attach variables vrD_8_10 [vr0_8_10 vr1_8_10 vr2_8_10 vr3_8_10 vr4_8_10 vr5_8_10 vr6_8_10 vr7_8_10 vr8_8_10 vr9_8_10 vr10_8_10 vr11_8_10 vr12_8_10 vr13_8_10 vr14_8_10 vr15_8_10 vr16_8_10 vr17_8_10 vr18_8_10 vr19_8_10 vr20_8_10 vr21_8_10 vr22_8_10 vr23_8_10 vr24_8_10 vr25_8_10 vr26_8_10 vr27_8_10 vr28_8_10 vr29_8_10 vr30_8_10 vr31_8_10 ]; +attach variables vrD_8_11 [vr0_8_11 vr1_8_11 vr2_8_11 vr3_8_11 vr4_8_11 vr5_8_11 vr6_8_11 vr7_8_11 vr8_8_11 vr9_8_11 vr10_8_11 vr11_8_11 vr12_8_11 vr13_8_11 vr14_8_11 vr15_8_11 vr16_8_11 vr17_8_11 vr18_8_11 vr19_8_11 vr20_8_11 vr21_8_11 vr22_8_11 vr23_8_11 vr24_8_11 vr25_8_11 vr26_8_11 vr27_8_11 vr28_8_11 vr29_8_11 vr30_8_11 vr31_8_11 ]; +attach variables vrD_8_12 [vr0_8_12 vr1_8_12 vr2_8_12 vr3_8_12 vr4_8_12 vr5_8_12 vr6_8_12 vr7_8_12 vr8_8_12 vr9_8_12 vr10_8_12 vr11_8_12 vr12_8_12 vr13_8_12 vr14_8_12 vr15_8_12 vr16_8_12 vr17_8_12 vr18_8_12 vr19_8_12 vr20_8_12 vr21_8_12 vr22_8_12 vr23_8_12 vr24_8_12 vr25_8_12 vr26_8_12 vr27_8_12 vr28_8_12 vr29_8_12 vr30_8_12 vr31_8_12 ]; +attach variables vrD_8_13 [vr0_8_13 vr1_8_13 vr2_8_13 vr3_8_13 vr4_8_13 vr5_8_13 vr6_8_13 vr7_8_13 vr8_8_13 vr9_8_13 vr10_8_13 vr11_8_13 vr12_8_13 vr13_8_13 vr14_8_13 vr15_8_13 vr16_8_13 vr17_8_13 vr18_8_13 vr19_8_13 vr20_8_13 vr21_8_13 vr22_8_13 vr23_8_13 vr24_8_13 vr25_8_13 vr26_8_13 vr27_8_13 vr28_8_13 vr29_8_13 vr30_8_13 vr31_8_13 ]; +attach variables vrD_8_14 [vr0_8_14 vr1_8_14 vr2_8_14 vr3_8_14 vr4_8_14 vr5_8_14 vr6_8_14 vr7_8_14 vr8_8_14 vr9_8_14 vr10_8_14 vr11_8_14 vr12_8_14 vr13_8_14 vr14_8_14 vr15_8_14 vr16_8_14 vr17_8_14 vr18_8_14 vr19_8_14 vr20_8_14 vr21_8_14 vr22_8_14 vr23_8_14 vr24_8_14 vr25_8_14 vr26_8_14 vr27_8_14 vr28_8_14 vr29_8_14 vr30_8_14 vr31_8_14 ]; +attach variables vrD_8_15 [vr0_8_15 vr1_8_15 vr2_8_15 vr3_8_15 vr4_8_15 vr5_8_15 vr6_8_15 vr7_8_15 vr8_8_15 vr9_8_15 vr10_8_15 vr11_8_15 vr12_8_15 vr13_8_15 vr14_8_15 vr15_8_15 vr16_8_15 vr17_8_15 vr18_8_15 vr19_8_15 vr20_8_15 vr21_8_15 vr22_8_15 vr23_8_15 vr24_8_15 vr25_8_15 vr26_8_15 vr27_8_15 vr28_8_15 vr29_8_15 vr30_8_15 vr31_8_15 ]; + + +# AltVect Vector vrA sub-piece selectors + +# AltVect Vector vrA sub-piece selectors for size 64 +attach variables vrA_64_0 [vr0_64_0 vr1_64_0 vr2_64_0 vr3_64_0 vr4_64_0 vr5_64_0 vr6_64_0 vr7_64_0 vr8_64_0 vr9_64_0 vr10_64_0 vr11_64_0 vr12_64_0 vr13_64_0 vr14_64_0 vr15_64_0 vr16_64_0 vr17_64_0 vr18_64_0 vr19_64_0 vr20_64_0 vr21_64_0 vr22_64_0 vr23_64_0 vr24_64_0 vr25_64_0 vr26_64_0 vr27_64_0 vr28_64_0 vr29_64_0 vr30_64_0 vr31_64_0 ]; +attach variables vrA_64_1 [vr0_64_1 vr1_64_1 vr2_64_1 vr3_64_1 vr4_64_1 vr5_64_1 vr6_64_1 vr7_64_1 vr8_64_1 vr9_64_1 vr10_64_1 vr11_64_1 vr12_64_1 vr13_64_1 vr14_64_1 vr15_64_1 vr16_64_1 vr17_64_1 vr18_64_1 vr19_64_1 vr20_64_1 vr21_64_1 vr22_64_1 vr23_64_1 vr24_64_1 vr25_64_1 vr26_64_1 vr27_64_1 vr28_64_1 vr29_64_1 vr30_64_1 vr31_64_1 ]; + +# AltVect Vector vrA sub-piece selectors for size 32 +attach variables vrA_32_0 [vr0_32_0 vr1_32_0 vr2_32_0 vr3_32_0 vr4_32_0 vr5_32_0 vr6_32_0 vr7_32_0 vr8_32_0 vr9_32_0 vr10_32_0 vr11_32_0 vr12_32_0 vr13_32_0 vr14_32_0 vr15_32_0 vr16_32_0 vr17_32_0 vr18_32_0 vr19_32_0 vr20_32_0 vr21_32_0 vr22_32_0 vr23_32_0 vr24_32_0 vr25_32_0 vr26_32_0 vr27_32_0 vr28_32_0 vr29_32_0 vr30_32_0 vr31_32_0 ]; +attach variables vrA_32_1 [vr0_32_1 vr1_32_1 vr2_32_1 vr3_32_1 vr4_32_1 vr5_32_1 vr6_32_1 vr7_32_1 vr8_32_1 vr9_32_1 vr10_32_1 vr11_32_1 vr12_32_1 vr13_32_1 vr14_32_1 vr15_32_1 vr16_32_1 vr17_32_1 vr18_32_1 vr19_32_1 vr20_32_1 vr21_32_1 vr22_32_1 vr23_32_1 vr24_32_1 vr25_32_1 vr26_32_1 vr27_32_1 vr28_32_1 vr29_32_1 vr30_32_1 vr31_32_1 ]; +attach variables vrA_32_2 [vr0_32_2 vr1_32_2 vr2_32_2 vr3_32_2 vr4_32_2 vr5_32_2 vr6_32_2 vr7_32_2 vr8_32_2 vr9_32_2 vr10_32_2 vr11_32_2 vr12_32_2 vr13_32_2 vr14_32_2 vr15_32_2 vr16_32_2 vr17_32_2 vr18_32_2 vr19_32_2 vr20_32_2 vr21_32_2 vr22_32_2 vr23_32_2 vr24_32_2 vr25_32_2 vr26_32_2 vr27_32_2 vr28_32_2 vr29_32_2 vr30_32_2 vr31_32_2 ]; +attach variables vrA_32_3 [vr0_32_3 vr1_32_3 vr2_32_3 vr3_32_3 vr4_32_3 vr5_32_3 vr6_32_3 vr7_32_3 vr8_32_3 vr9_32_3 vr10_32_3 vr11_32_3 vr12_32_3 vr13_32_3 vr14_32_3 vr15_32_3 vr16_32_3 vr17_32_3 vr18_32_3 vr19_32_3 vr20_32_3 vr21_32_3 vr22_32_3 vr23_32_3 vr24_32_3 vr25_32_3 vr26_32_3 vr27_32_3 vr28_32_3 vr29_32_3 vr30_32_3 vr31_32_3 ]; + +# AltVect Vector vrA sub-piece selectors for size 16 +attach variables vrA_16_0 [vr0_16_0 vr1_16_0 vr2_16_0 vr3_16_0 vr4_16_0 vr5_16_0 vr6_16_0 vr7_16_0 vr8_16_0 vr9_16_0 vr10_16_0 vr11_16_0 vr12_16_0 vr13_16_0 vr14_16_0 vr15_16_0 vr16_16_0 vr17_16_0 vr18_16_0 vr19_16_0 vr20_16_0 vr21_16_0 vr22_16_0 vr23_16_0 vr24_16_0 vr25_16_0 vr26_16_0 vr27_16_0 vr28_16_0 vr29_16_0 vr30_16_0 vr31_16_0 ]; +attach variables vrA_16_1 [vr0_16_1 vr1_16_1 vr2_16_1 vr3_16_1 vr4_16_1 vr5_16_1 vr6_16_1 vr7_16_1 vr8_16_1 vr9_16_1 vr10_16_1 vr11_16_1 vr12_16_1 vr13_16_1 vr14_16_1 vr15_16_1 vr16_16_1 vr17_16_1 vr18_16_1 vr19_16_1 vr20_16_1 vr21_16_1 vr22_16_1 vr23_16_1 vr24_16_1 vr25_16_1 vr26_16_1 vr27_16_1 vr28_16_1 vr29_16_1 vr30_16_1 vr31_16_1 ]; +attach variables vrA_16_2 [vr0_16_2 vr1_16_2 vr2_16_2 vr3_16_2 vr4_16_2 vr5_16_2 vr6_16_2 vr7_16_2 vr8_16_2 vr9_16_2 vr10_16_2 vr11_16_2 vr12_16_2 vr13_16_2 vr14_16_2 vr15_16_2 vr16_16_2 vr17_16_2 vr18_16_2 vr19_16_2 vr20_16_2 vr21_16_2 vr22_16_2 vr23_16_2 vr24_16_2 vr25_16_2 vr26_16_2 vr27_16_2 vr28_16_2 vr29_16_2 vr30_16_2 vr31_16_2 ]; +attach variables vrA_16_3 [vr0_16_3 vr1_16_3 vr2_16_3 vr3_16_3 vr4_16_3 vr5_16_3 vr6_16_3 vr7_16_3 vr8_16_3 vr9_16_3 vr10_16_3 vr11_16_3 vr12_16_3 vr13_16_3 vr14_16_3 vr15_16_3 vr16_16_3 vr17_16_3 vr18_16_3 vr19_16_3 vr20_16_3 vr21_16_3 vr22_16_3 vr23_16_3 vr24_16_3 vr25_16_3 vr26_16_3 vr27_16_3 vr28_16_3 vr29_16_3 vr30_16_3 vr31_16_3 ]; +attach variables vrA_16_4 [vr0_16_4 vr1_16_4 vr2_16_4 vr3_16_4 vr4_16_4 vr5_16_4 vr6_16_4 vr7_16_4 vr8_16_4 vr9_16_4 vr10_16_4 vr11_16_4 vr12_16_4 vr13_16_4 vr14_16_4 vr15_16_4 vr16_16_4 vr17_16_4 vr18_16_4 vr19_16_4 vr20_16_4 vr21_16_4 vr22_16_4 vr23_16_4 vr24_16_4 vr25_16_4 vr26_16_4 vr27_16_4 vr28_16_4 vr29_16_4 vr30_16_4 vr31_16_4 ]; +attach variables vrA_16_5 [vr0_16_5 vr1_16_5 vr2_16_5 vr3_16_5 vr4_16_5 vr5_16_5 vr6_16_5 vr7_16_5 vr8_16_5 vr9_16_5 vr10_16_5 vr11_16_5 vr12_16_5 vr13_16_5 vr14_16_5 vr15_16_5 vr16_16_5 vr17_16_5 vr18_16_5 vr19_16_5 vr20_16_5 vr21_16_5 vr22_16_5 vr23_16_5 vr24_16_5 vr25_16_5 vr26_16_5 vr27_16_5 vr28_16_5 vr29_16_5 vr30_16_5 vr31_16_5 ]; +attach variables vrA_16_6 [vr0_16_6 vr1_16_6 vr2_16_6 vr3_16_6 vr4_16_6 vr5_16_6 vr6_16_6 vr7_16_6 vr8_16_6 vr9_16_6 vr10_16_6 vr11_16_6 vr12_16_6 vr13_16_6 vr14_16_6 vr15_16_6 vr16_16_6 vr17_16_6 vr18_16_6 vr19_16_6 vr20_16_6 vr21_16_6 vr22_16_6 vr23_16_6 vr24_16_6 vr25_16_6 vr26_16_6 vr27_16_6 vr28_16_6 vr29_16_6 vr30_16_6 vr31_16_6 ]; +attach variables vrA_16_7 [vr0_16_7 vr1_16_7 vr2_16_7 vr3_16_7 vr4_16_7 vr5_16_7 vr6_16_7 vr7_16_7 vr8_16_7 vr9_16_7 vr10_16_7 vr11_16_7 vr12_16_7 vr13_16_7 vr14_16_7 vr15_16_7 vr16_16_7 vr17_16_7 vr18_16_7 vr19_16_7 vr20_16_7 vr21_16_7 vr22_16_7 vr23_16_7 vr24_16_7 vr25_16_7 vr26_16_7 vr27_16_7 vr28_16_7 vr29_16_7 vr30_16_7 vr31_16_7 ]; + +# AltVect Vector vrA sub-piece selectors for size 8 +attach variables vrA_8_0 [vr0_8_0 vr1_8_0 vr2_8_0 vr3_8_0 vr4_8_0 vr5_8_0 vr6_8_0 vr7_8_0 vr8_8_0 vr9_8_0 vr10_8_0 vr11_8_0 vr12_8_0 vr13_8_0 vr14_8_0 vr15_8_0 vr16_8_0 vr17_8_0 vr18_8_0 vr19_8_0 vr20_8_0 vr21_8_0 vr22_8_0 vr23_8_0 vr24_8_0 vr25_8_0 vr26_8_0 vr27_8_0 vr28_8_0 vr29_8_0 vr30_8_0 vr31_8_0 ]; +attach variables vrA_8_1 [vr0_8_1 vr1_8_1 vr2_8_1 vr3_8_1 vr4_8_1 vr5_8_1 vr6_8_1 vr7_8_1 vr8_8_1 vr9_8_1 vr10_8_1 vr11_8_1 vr12_8_1 vr13_8_1 vr14_8_1 vr15_8_1 vr16_8_1 vr17_8_1 vr18_8_1 vr19_8_1 vr20_8_1 vr21_8_1 vr22_8_1 vr23_8_1 vr24_8_1 vr25_8_1 vr26_8_1 vr27_8_1 vr28_8_1 vr29_8_1 vr30_8_1 vr31_8_1 ]; +attach variables vrA_8_2 [vr0_8_2 vr1_8_2 vr2_8_2 vr3_8_2 vr4_8_2 vr5_8_2 vr6_8_2 vr7_8_2 vr8_8_2 vr9_8_2 vr10_8_2 vr11_8_2 vr12_8_2 vr13_8_2 vr14_8_2 vr15_8_2 vr16_8_2 vr17_8_2 vr18_8_2 vr19_8_2 vr20_8_2 vr21_8_2 vr22_8_2 vr23_8_2 vr24_8_2 vr25_8_2 vr26_8_2 vr27_8_2 vr28_8_2 vr29_8_2 vr30_8_2 vr31_8_2 ]; +attach variables vrA_8_3 [vr0_8_3 vr1_8_3 vr2_8_3 vr3_8_3 vr4_8_3 vr5_8_3 vr6_8_3 vr7_8_3 vr8_8_3 vr9_8_3 vr10_8_3 vr11_8_3 vr12_8_3 vr13_8_3 vr14_8_3 vr15_8_3 vr16_8_3 vr17_8_3 vr18_8_3 vr19_8_3 vr20_8_3 vr21_8_3 vr22_8_3 vr23_8_3 vr24_8_3 vr25_8_3 vr26_8_3 vr27_8_3 vr28_8_3 vr29_8_3 vr30_8_3 vr31_8_3 ]; +attach variables vrA_8_4 [vr0_8_4 vr1_8_4 vr2_8_4 vr3_8_4 vr4_8_4 vr5_8_4 vr6_8_4 vr7_8_4 vr8_8_4 vr9_8_4 vr10_8_4 vr11_8_4 vr12_8_4 vr13_8_4 vr14_8_4 vr15_8_4 vr16_8_4 vr17_8_4 vr18_8_4 vr19_8_4 vr20_8_4 vr21_8_4 vr22_8_4 vr23_8_4 vr24_8_4 vr25_8_4 vr26_8_4 vr27_8_4 vr28_8_4 vr29_8_4 vr30_8_4 vr31_8_4 ]; +attach variables vrA_8_5 [vr0_8_5 vr1_8_5 vr2_8_5 vr3_8_5 vr4_8_5 vr5_8_5 vr6_8_5 vr7_8_5 vr8_8_5 vr9_8_5 vr10_8_5 vr11_8_5 vr12_8_5 vr13_8_5 vr14_8_5 vr15_8_5 vr16_8_5 vr17_8_5 vr18_8_5 vr19_8_5 vr20_8_5 vr21_8_5 vr22_8_5 vr23_8_5 vr24_8_5 vr25_8_5 vr26_8_5 vr27_8_5 vr28_8_5 vr29_8_5 vr30_8_5 vr31_8_5 ]; +attach variables vrA_8_6 [vr0_8_6 vr1_8_6 vr2_8_6 vr3_8_6 vr4_8_6 vr5_8_6 vr6_8_6 vr7_8_6 vr8_8_6 vr9_8_6 vr10_8_6 vr11_8_6 vr12_8_6 vr13_8_6 vr14_8_6 vr15_8_6 vr16_8_6 vr17_8_6 vr18_8_6 vr19_8_6 vr20_8_6 vr21_8_6 vr22_8_6 vr23_8_6 vr24_8_6 vr25_8_6 vr26_8_6 vr27_8_6 vr28_8_6 vr29_8_6 vr30_8_6 vr31_8_6 ]; +attach variables vrA_8_7 [vr0_8_7 vr1_8_7 vr2_8_7 vr3_8_7 vr4_8_7 vr5_8_7 vr6_8_7 vr7_8_7 vr8_8_7 vr9_8_7 vr10_8_7 vr11_8_7 vr12_8_7 vr13_8_7 vr14_8_7 vr15_8_7 vr16_8_7 vr17_8_7 vr18_8_7 vr19_8_7 vr20_8_7 vr21_8_7 vr22_8_7 vr23_8_7 vr24_8_7 vr25_8_7 vr26_8_7 vr27_8_7 vr28_8_7 vr29_8_7 vr30_8_7 vr31_8_7 ]; +attach variables vrA_8_8 [vr0_8_8 vr1_8_8 vr2_8_8 vr3_8_8 vr4_8_8 vr5_8_8 vr6_8_8 vr7_8_8 vr8_8_8 vr9_8_8 vr10_8_8 vr11_8_8 vr12_8_8 vr13_8_8 vr14_8_8 vr15_8_8 vr16_8_8 vr17_8_8 vr18_8_8 vr19_8_8 vr20_8_8 vr21_8_8 vr22_8_8 vr23_8_8 vr24_8_8 vr25_8_8 vr26_8_8 vr27_8_8 vr28_8_8 vr29_8_8 vr30_8_8 vr31_8_8 ]; +attach variables vrA_8_9 [vr0_8_9 vr1_8_9 vr2_8_9 vr3_8_9 vr4_8_9 vr5_8_9 vr6_8_9 vr7_8_9 vr8_8_9 vr9_8_9 vr10_8_9 vr11_8_9 vr12_8_9 vr13_8_9 vr14_8_9 vr15_8_9 vr16_8_9 vr17_8_9 vr18_8_9 vr19_8_9 vr20_8_9 vr21_8_9 vr22_8_9 vr23_8_9 vr24_8_9 vr25_8_9 vr26_8_9 vr27_8_9 vr28_8_9 vr29_8_9 vr30_8_9 vr31_8_9 ]; +attach variables vrA_8_10 [vr0_8_10 vr1_8_10 vr2_8_10 vr3_8_10 vr4_8_10 vr5_8_10 vr6_8_10 vr7_8_10 vr8_8_10 vr9_8_10 vr10_8_10 vr11_8_10 vr12_8_10 vr13_8_10 vr14_8_10 vr15_8_10 vr16_8_10 vr17_8_10 vr18_8_10 vr19_8_10 vr20_8_10 vr21_8_10 vr22_8_10 vr23_8_10 vr24_8_10 vr25_8_10 vr26_8_10 vr27_8_10 vr28_8_10 vr29_8_10 vr30_8_10 vr31_8_10 ]; +attach variables vrA_8_11 [vr0_8_11 vr1_8_11 vr2_8_11 vr3_8_11 vr4_8_11 vr5_8_11 vr6_8_11 vr7_8_11 vr8_8_11 vr9_8_11 vr10_8_11 vr11_8_11 vr12_8_11 vr13_8_11 vr14_8_11 vr15_8_11 vr16_8_11 vr17_8_11 vr18_8_11 vr19_8_11 vr20_8_11 vr21_8_11 vr22_8_11 vr23_8_11 vr24_8_11 vr25_8_11 vr26_8_11 vr27_8_11 vr28_8_11 vr29_8_11 vr30_8_11 vr31_8_11 ]; +attach variables vrA_8_12 [vr0_8_12 vr1_8_12 vr2_8_12 vr3_8_12 vr4_8_12 vr5_8_12 vr6_8_12 vr7_8_12 vr8_8_12 vr9_8_12 vr10_8_12 vr11_8_12 vr12_8_12 vr13_8_12 vr14_8_12 vr15_8_12 vr16_8_12 vr17_8_12 vr18_8_12 vr19_8_12 vr20_8_12 vr21_8_12 vr22_8_12 vr23_8_12 vr24_8_12 vr25_8_12 vr26_8_12 vr27_8_12 vr28_8_12 vr29_8_12 vr30_8_12 vr31_8_12 ]; +attach variables vrA_8_13 [vr0_8_13 vr1_8_13 vr2_8_13 vr3_8_13 vr4_8_13 vr5_8_13 vr6_8_13 vr7_8_13 vr8_8_13 vr9_8_13 vr10_8_13 vr11_8_13 vr12_8_13 vr13_8_13 vr14_8_13 vr15_8_13 vr16_8_13 vr17_8_13 vr18_8_13 vr19_8_13 vr20_8_13 vr21_8_13 vr22_8_13 vr23_8_13 vr24_8_13 vr25_8_13 vr26_8_13 vr27_8_13 vr28_8_13 vr29_8_13 vr30_8_13 vr31_8_13 ]; +attach variables vrA_8_14 [vr0_8_14 vr1_8_14 vr2_8_14 vr3_8_14 vr4_8_14 vr5_8_14 vr6_8_14 vr7_8_14 vr8_8_14 vr9_8_14 vr10_8_14 vr11_8_14 vr12_8_14 vr13_8_14 vr14_8_14 vr15_8_14 vr16_8_14 vr17_8_14 vr18_8_14 vr19_8_14 vr20_8_14 vr21_8_14 vr22_8_14 vr23_8_14 vr24_8_14 vr25_8_14 vr26_8_14 vr27_8_14 vr28_8_14 vr29_8_14 vr30_8_14 vr31_8_14 ]; +attach variables vrA_8_15 [vr0_8_15 vr1_8_15 vr2_8_15 vr3_8_15 vr4_8_15 vr5_8_15 vr6_8_15 vr7_8_15 vr8_8_15 vr9_8_15 vr10_8_15 vr11_8_15 vr12_8_15 vr13_8_15 vr14_8_15 vr15_8_15 vr16_8_15 vr17_8_15 vr18_8_15 vr19_8_15 vr20_8_15 vr21_8_15 vr22_8_15 vr23_8_15 vr24_8_15 vr25_8_15 vr26_8_15 vr27_8_15 vr28_8_15 vr29_8_15 vr30_8_15 vr31_8_15 ]; + + +# AltVect Vector vrB sub-piece selectors + +# AltVect Vector vrB sub-piece selectors for size 64 +attach variables vrB_64_0 [vr0_64_0 vr1_64_0 vr2_64_0 vr3_64_0 vr4_64_0 vr5_64_0 vr6_64_0 vr7_64_0 vr8_64_0 vr9_64_0 vr10_64_0 vr11_64_0 vr12_64_0 vr13_64_0 vr14_64_0 vr15_64_0 vr16_64_0 vr17_64_0 vr18_64_0 vr19_64_0 vr20_64_0 vr21_64_0 vr22_64_0 vr23_64_0 vr24_64_0 vr25_64_0 vr26_64_0 vr27_64_0 vr28_64_0 vr29_64_0 vr30_64_0 vr31_64_0 ]; +attach variables vrB_64_1 [vr0_64_1 vr1_64_1 vr2_64_1 vr3_64_1 vr4_64_1 vr5_64_1 vr6_64_1 vr7_64_1 vr8_64_1 vr9_64_1 vr10_64_1 vr11_64_1 vr12_64_1 vr13_64_1 vr14_64_1 vr15_64_1 vr16_64_1 vr17_64_1 vr18_64_1 vr19_64_1 vr20_64_1 vr21_64_1 vr22_64_1 vr23_64_1 vr24_64_1 vr25_64_1 vr26_64_1 vr27_64_1 vr28_64_1 vr29_64_1 vr30_64_1 vr31_64_1 ]; + +# AltVect Vector vrB sub-piece selectors for size 32 +attach variables vrB_32_0 [vr0_32_0 vr1_32_0 vr2_32_0 vr3_32_0 vr4_32_0 vr5_32_0 vr6_32_0 vr7_32_0 vr8_32_0 vr9_32_0 vr10_32_0 vr11_32_0 vr12_32_0 vr13_32_0 vr14_32_0 vr15_32_0 vr16_32_0 vr17_32_0 vr18_32_0 vr19_32_0 vr20_32_0 vr21_32_0 vr22_32_0 vr23_32_0 vr24_32_0 vr25_32_0 vr26_32_0 vr27_32_0 vr28_32_0 vr29_32_0 vr30_32_0 vr31_32_0 ]; +attach variables vrB_32_1 [vr0_32_1 vr1_32_1 vr2_32_1 vr3_32_1 vr4_32_1 vr5_32_1 vr6_32_1 vr7_32_1 vr8_32_1 vr9_32_1 vr10_32_1 vr11_32_1 vr12_32_1 vr13_32_1 vr14_32_1 vr15_32_1 vr16_32_1 vr17_32_1 vr18_32_1 vr19_32_1 vr20_32_1 vr21_32_1 vr22_32_1 vr23_32_1 vr24_32_1 vr25_32_1 vr26_32_1 vr27_32_1 vr28_32_1 vr29_32_1 vr30_32_1 vr31_32_1 ]; +attach variables vrB_32_2 [vr0_32_2 vr1_32_2 vr2_32_2 vr3_32_2 vr4_32_2 vr5_32_2 vr6_32_2 vr7_32_2 vr8_32_2 vr9_32_2 vr10_32_2 vr11_32_2 vr12_32_2 vr13_32_2 vr14_32_2 vr15_32_2 vr16_32_2 vr17_32_2 vr18_32_2 vr19_32_2 vr20_32_2 vr21_32_2 vr22_32_2 vr23_32_2 vr24_32_2 vr25_32_2 vr26_32_2 vr27_32_2 vr28_32_2 vr29_32_2 vr30_32_2 vr31_32_2 ]; +attach variables vrB_32_3 [vr0_32_3 vr1_32_3 vr2_32_3 vr3_32_3 vr4_32_3 vr5_32_3 vr6_32_3 vr7_32_3 vr8_32_3 vr9_32_3 vr10_32_3 vr11_32_3 vr12_32_3 vr13_32_3 vr14_32_3 vr15_32_3 vr16_32_3 vr17_32_3 vr18_32_3 vr19_32_3 vr20_32_3 vr21_32_3 vr22_32_3 vr23_32_3 vr24_32_3 vr25_32_3 vr26_32_3 vr27_32_3 vr28_32_3 vr29_32_3 vr30_32_3 vr31_32_3 ]; + +# AltVect Vector vrB sub-piece selectors for size 16 +attach variables vrB_16_0 [vr0_16_0 vr1_16_0 vr2_16_0 vr3_16_0 vr4_16_0 vr5_16_0 vr6_16_0 vr7_16_0 vr8_16_0 vr9_16_0 vr10_16_0 vr11_16_0 vr12_16_0 vr13_16_0 vr14_16_0 vr15_16_0 vr16_16_0 vr17_16_0 vr18_16_0 vr19_16_0 vr20_16_0 vr21_16_0 vr22_16_0 vr23_16_0 vr24_16_0 vr25_16_0 vr26_16_0 vr27_16_0 vr28_16_0 vr29_16_0 vr30_16_0 vr31_16_0 ]; +attach variables vrB_16_1 [vr0_16_1 vr1_16_1 vr2_16_1 vr3_16_1 vr4_16_1 vr5_16_1 vr6_16_1 vr7_16_1 vr8_16_1 vr9_16_1 vr10_16_1 vr11_16_1 vr12_16_1 vr13_16_1 vr14_16_1 vr15_16_1 vr16_16_1 vr17_16_1 vr18_16_1 vr19_16_1 vr20_16_1 vr21_16_1 vr22_16_1 vr23_16_1 vr24_16_1 vr25_16_1 vr26_16_1 vr27_16_1 vr28_16_1 vr29_16_1 vr30_16_1 vr31_16_1 ]; +attach variables vrB_16_2 [vr0_16_2 vr1_16_2 vr2_16_2 vr3_16_2 vr4_16_2 vr5_16_2 vr6_16_2 vr7_16_2 vr8_16_2 vr9_16_2 vr10_16_2 vr11_16_2 vr12_16_2 vr13_16_2 vr14_16_2 vr15_16_2 vr16_16_2 vr17_16_2 vr18_16_2 vr19_16_2 vr20_16_2 vr21_16_2 vr22_16_2 vr23_16_2 vr24_16_2 vr25_16_2 vr26_16_2 vr27_16_2 vr28_16_2 vr29_16_2 vr30_16_2 vr31_16_2 ]; +attach variables vrB_16_3 [vr0_16_3 vr1_16_3 vr2_16_3 vr3_16_3 vr4_16_3 vr5_16_3 vr6_16_3 vr7_16_3 vr8_16_3 vr9_16_3 vr10_16_3 vr11_16_3 vr12_16_3 vr13_16_3 vr14_16_3 vr15_16_3 vr16_16_3 vr17_16_3 vr18_16_3 vr19_16_3 vr20_16_3 vr21_16_3 vr22_16_3 vr23_16_3 vr24_16_3 vr25_16_3 vr26_16_3 vr27_16_3 vr28_16_3 vr29_16_3 vr30_16_3 vr31_16_3 ]; +attach variables vrB_16_4 [vr0_16_4 vr1_16_4 vr2_16_4 vr3_16_4 vr4_16_4 vr5_16_4 vr6_16_4 vr7_16_4 vr8_16_4 vr9_16_4 vr10_16_4 vr11_16_4 vr12_16_4 vr13_16_4 vr14_16_4 vr15_16_4 vr16_16_4 vr17_16_4 vr18_16_4 vr19_16_4 vr20_16_4 vr21_16_4 vr22_16_4 vr23_16_4 vr24_16_4 vr25_16_4 vr26_16_4 vr27_16_4 vr28_16_4 vr29_16_4 vr30_16_4 vr31_16_4 ]; +attach variables vrB_16_5 [vr0_16_5 vr1_16_5 vr2_16_5 vr3_16_5 vr4_16_5 vr5_16_5 vr6_16_5 vr7_16_5 vr8_16_5 vr9_16_5 vr10_16_5 vr11_16_5 vr12_16_5 vr13_16_5 vr14_16_5 vr15_16_5 vr16_16_5 vr17_16_5 vr18_16_5 vr19_16_5 vr20_16_5 vr21_16_5 vr22_16_5 vr23_16_5 vr24_16_5 vr25_16_5 vr26_16_5 vr27_16_5 vr28_16_5 vr29_16_5 vr30_16_5 vr31_16_5 ]; +attach variables vrB_16_6 [vr0_16_6 vr1_16_6 vr2_16_6 vr3_16_6 vr4_16_6 vr5_16_6 vr6_16_6 vr7_16_6 vr8_16_6 vr9_16_6 vr10_16_6 vr11_16_6 vr12_16_6 vr13_16_6 vr14_16_6 vr15_16_6 vr16_16_6 vr17_16_6 vr18_16_6 vr19_16_6 vr20_16_6 vr21_16_6 vr22_16_6 vr23_16_6 vr24_16_6 vr25_16_6 vr26_16_6 vr27_16_6 vr28_16_6 vr29_16_6 vr30_16_6 vr31_16_6 ]; +attach variables vrB_16_7 [vr0_16_7 vr1_16_7 vr2_16_7 vr3_16_7 vr4_16_7 vr5_16_7 vr6_16_7 vr7_16_7 vr8_16_7 vr9_16_7 vr10_16_7 vr11_16_7 vr12_16_7 vr13_16_7 vr14_16_7 vr15_16_7 vr16_16_7 vr17_16_7 vr18_16_7 vr19_16_7 vr20_16_7 vr21_16_7 vr22_16_7 vr23_16_7 vr24_16_7 vr25_16_7 vr26_16_7 vr27_16_7 vr28_16_7 vr29_16_7 vr30_16_7 vr31_16_7 ]; + +# AltVect Vector vrB sub-piece selectors for size 8 +attach variables vrB_8_0 [vr0_8_0 vr1_8_0 vr2_8_0 vr3_8_0 vr4_8_0 vr5_8_0 vr6_8_0 vr7_8_0 vr8_8_0 vr9_8_0 vr10_8_0 vr11_8_0 vr12_8_0 vr13_8_0 vr14_8_0 vr15_8_0 vr16_8_0 vr17_8_0 vr18_8_0 vr19_8_0 vr20_8_0 vr21_8_0 vr22_8_0 vr23_8_0 vr24_8_0 vr25_8_0 vr26_8_0 vr27_8_0 vr28_8_0 vr29_8_0 vr30_8_0 vr31_8_0 ]; +attach variables vrB_8_1 [vr0_8_1 vr1_8_1 vr2_8_1 vr3_8_1 vr4_8_1 vr5_8_1 vr6_8_1 vr7_8_1 vr8_8_1 vr9_8_1 vr10_8_1 vr11_8_1 vr12_8_1 vr13_8_1 vr14_8_1 vr15_8_1 vr16_8_1 vr17_8_1 vr18_8_1 vr19_8_1 vr20_8_1 vr21_8_1 vr22_8_1 vr23_8_1 vr24_8_1 vr25_8_1 vr26_8_1 vr27_8_1 vr28_8_1 vr29_8_1 vr30_8_1 vr31_8_1 ]; +attach variables vrB_8_2 [vr0_8_2 vr1_8_2 vr2_8_2 vr3_8_2 vr4_8_2 vr5_8_2 vr6_8_2 vr7_8_2 vr8_8_2 vr9_8_2 vr10_8_2 vr11_8_2 vr12_8_2 vr13_8_2 vr14_8_2 vr15_8_2 vr16_8_2 vr17_8_2 vr18_8_2 vr19_8_2 vr20_8_2 vr21_8_2 vr22_8_2 vr23_8_2 vr24_8_2 vr25_8_2 vr26_8_2 vr27_8_2 vr28_8_2 vr29_8_2 vr30_8_2 vr31_8_2 ]; +attach variables vrB_8_3 [vr0_8_3 vr1_8_3 vr2_8_3 vr3_8_3 vr4_8_3 vr5_8_3 vr6_8_3 vr7_8_3 vr8_8_3 vr9_8_3 vr10_8_3 vr11_8_3 vr12_8_3 vr13_8_3 vr14_8_3 vr15_8_3 vr16_8_3 vr17_8_3 vr18_8_3 vr19_8_3 vr20_8_3 vr21_8_3 vr22_8_3 vr23_8_3 vr24_8_3 vr25_8_3 vr26_8_3 vr27_8_3 vr28_8_3 vr29_8_3 vr30_8_3 vr31_8_3 ]; +attach variables vrB_8_4 [vr0_8_4 vr1_8_4 vr2_8_4 vr3_8_4 vr4_8_4 vr5_8_4 vr6_8_4 vr7_8_4 vr8_8_4 vr9_8_4 vr10_8_4 vr11_8_4 vr12_8_4 vr13_8_4 vr14_8_4 vr15_8_4 vr16_8_4 vr17_8_4 vr18_8_4 vr19_8_4 vr20_8_4 vr21_8_4 vr22_8_4 vr23_8_4 vr24_8_4 vr25_8_4 vr26_8_4 vr27_8_4 vr28_8_4 vr29_8_4 vr30_8_4 vr31_8_4 ]; +attach variables vrB_8_5 [vr0_8_5 vr1_8_5 vr2_8_5 vr3_8_5 vr4_8_5 vr5_8_5 vr6_8_5 vr7_8_5 vr8_8_5 vr9_8_5 vr10_8_5 vr11_8_5 vr12_8_5 vr13_8_5 vr14_8_5 vr15_8_5 vr16_8_5 vr17_8_5 vr18_8_5 vr19_8_5 vr20_8_5 vr21_8_5 vr22_8_5 vr23_8_5 vr24_8_5 vr25_8_5 vr26_8_5 vr27_8_5 vr28_8_5 vr29_8_5 vr30_8_5 vr31_8_5 ]; +attach variables vrB_8_6 [vr0_8_6 vr1_8_6 vr2_8_6 vr3_8_6 vr4_8_6 vr5_8_6 vr6_8_6 vr7_8_6 vr8_8_6 vr9_8_6 vr10_8_6 vr11_8_6 vr12_8_6 vr13_8_6 vr14_8_6 vr15_8_6 vr16_8_6 vr17_8_6 vr18_8_6 vr19_8_6 vr20_8_6 vr21_8_6 vr22_8_6 vr23_8_6 vr24_8_6 vr25_8_6 vr26_8_6 vr27_8_6 vr28_8_6 vr29_8_6 vr30_8_6 vr31_8_6 ]; +attach variables vrB_8_7 [vr0_8_7 vr1_8_7 vr2_8_7 vr3_8_7 vr4_8_7 vr5_8_7 vr6_8_7 vr7_8_7 vr8_8_7 vr9_8_7 vr10_8_7 vr11_8_7 vr12_8_7 vr13_8_7 vr14_8_7 vr15_8_7 vr16_8_7 vr17_8_7 vr18_8_7 vr19_8_7 vr20_8_7 vr21_8_7 vr22_8_7 vr23_8_7 vr24_8_7 vr25_8_7 vr26_8_7 vr27_8_7 vr28_8_7 vr29_8_7 vr30_8_7 vr31_8_7 ]; +attach variables vrB_8_8 [vr0_8_8 vr1_8_8 vr2_8_8 vr3_8_8 vr4_8_8 vr5_8_8 vr6_8_8 vr7_8_8 vr8_8_8 vr9_8_8 vr10_8_8 vr11_8_8 vr12_8_8 vr13_8_8 vr14_8_8 vr15_8_8 vr16_8_8 vr17_8_8 vr18_8_8 vr19_8_8 vr20_8_8 vr21_8_8 vr22_8_8 vr23_8_8 vr24_8_8 vr25_8_8 vr26_8_8 vr27_8_8 vr28_8_8 vr29_8_8 vr30_8_8 vr31_8_8 ]; +attach variables vrB_8_9 [vr0_8_9 vr1_8_9 vr2_8_9 vr3_8_9 vr4_8_9 vr5_8_9 vr6_8_9 vr7_8_9 vr8_8_9 vr9_8_9 vr10_8_9 vr11_8_9 vr12_8_9 vr13_8_9 vr14_8_9 vr15_8_9 vr16_8_9 vr17_8_9 vr18_8_9 vr19_8_9 vr20_8_9 vr21_8_9 vr22_8_9 vr23_8_9 vr24_8_9 vr25_8_9 vr26_8_9 vr27_8_9 vr28_8_9 vr29_8_9 vr30_8_9 vr31_8_9 ]; +attach variables vrB_8_10 [vr0_8_10 vr1_8_10 vr2_8_10 vr3_8_10 vr4_8_10 vr5_8_10 vr6_8_10 vr7_8_10 vr8_8_10 vr9_8_10 vr10_8_10 vr11_8_10 vr12_8_10 vr13_8_10 vr14_8_10 vr15_8_10 vr16_8_10 vr17_8_10 vr18_8_10 vr19_8_10 vr20_8_10 vr21_8_10 vr22_8_10 vr23_8_10 vr24_8_10 vr25_8_10 vr26_8_10 vr27_8_10 vr28_8_10 vr29_8_10 vr30_8_10 vr31_8_10 ]; +attach variables vrB_8_11 [vr0_8_11 vr1_8_11 vr2_8_11 vr3_8_11 vr4_8_11 vr5_8_11 vr6_8_11 vr7_8_11 vr8_8_11 vr9_8_11 vr10_8_11 vr11_8_11 vr12_8_11 vr13_8_11 vr14_8_11 vr15_8_11 vr16_8_11 vr17_8_11 vr18_8_11 vr19_8_11 vr20_8_11 vr21_8_11 vr22_8_11 vr23_8_11 vr24_8_11 vr25_8_11 vr26_8_11 vr27_8_11 vr28_8_11 vr29_8_11 vr30_8_11 vr31_8_11 ]; +attach variables vrB_8_12 [vr0_8_12 vr1_8_12 vr2_8_12 vr3_8_12 vr4_8_12 vr5_8_12 vr6_8_12 vr7_8_12 vr8_8_12 vr9_8_12 vr10_8_12 vr11_8_12 vr12_8_12 vr13_8_12 vr14_8_12 vr15_8_12 vr16_8_12 vr17_8_12 vr18_8_12 vr19_8_12 vr20_8_12 vr21_8_12 vr22_8_12 vr23_8_12 vr24_8_12 vr25_8_12 vr26_8_12 vr27_8_12 vr28_8_12 vr29_8_12 vr30_8_12 vr31_8_12 ]; +attach variables vrB_8_13 [vr0_8_13 vr1_8_13 vr2_8_13 vr3_8_13 vr4_8_13 vr5_8_13 vr6_8_13 vr7_8_13 vr8_8_13 vr9_8_13 vr10_8_13 vr11_8_13 vr12_8_13 vr13_8_13 vr14_8_13 vr15_8_13 vr16_8_13 vr17_8_13 vr18_8_13 vr19_8_13 vr20_8_13 vr21_8_13 vr22_8_13 vr23_8_13 vr24_8_13 vr25_8_13 vr26_8_13 vr27_8_13 vr28_8_13 vr29_8_13 vr30_8_13 vr31_8_13 ]; +attach variables vrB_8_14 [vr0_8_14 vr1_8_14 vr2_8_14 vr3_8_14 vr4_8_14 vr5_8_14 vr6_8_14 vr7_8_14 vr8_8_14 vr9_8_14 vr10_8_14 vr11_8_14 vr12_8_14 vr13_8_14 vr14_8_14 vr15_8_14 vr16_8_14 vr17_8_14 vr18_8_14 vr19_8_14 vr20_8_14 vr21_8_14 vr22_8_14 vr23_8_14 vr24_8_14 vr25_8_14 vr26_8_14 vr27_8_14 vr28_8_14 vr29_8_14 vr30_8_14 vr31_8_14 ]; +attach variables vrB_8_15 [vr0_8_15 vr1_8_15 vr2_8_15 vr3_8_15 vr4_8_15 vr5_8_15 vr6_8_15 vr7_8_15 vr8_8_15 vr9_8_15 vr10_8_15 vr11_8_15 vr12_8_15 vr13_8_15 vr14_8_15 vr15_8_15 vr16_8_15 vr17_8_15 vr18_8_15 vr19_8_15 vr20_8_15 vr21_8_15 vr22_8_15 vr23_8_15 vr24_8_15 vr25_8_15 vr26_8_15 vr27_8_15 vr28_8_15 vr29_8_15 vr30_8_15 vr31_8_15 ]; + + +# AltVect Vector vrS sub-piece selectors + +# AltVect Vector vrS sub-piece selectors for size 64 +attach variables vrS_64_0 [vr0_64_0 vr1_64_0 vr2_64_0 vr3_64_0 vr4_64_0 vr5_64_0 vr6_64_0 vr7_64_0 vr8_64_0 vr9_64_0 vr10_64_0 vr11_64_0 vr12_64_0 vr13_64_0 vr14_64_0 vr15_64_0 vr16_64_0 vr17_64_0 vr18_64_0 vr19_64_0 vr20_64_0 vr21_64_0 vr22_64_0 vr23_64_0 vr24_64_0 vr25_64_0 vr26_64_0 vr27_64_0 vr28_64_0 vr29_64_0 vr30_64_0 vr31_64_0 ]; +attach variables vrS_64_1 [vr0_64_1 vr1_64_1 vr2_64_1 vr3_64_1 vr4_64_1 vr5_64_1 vr6_64_1 vr7_64_1 vr8_64_1 vr9_64_1 vr10_64_1 vr11_64_1 vr12_64_1 vr13_64_1 vr14_64_1 vr15_64_1 vr16_64_1 vr17_64_1 vr18_64_1 vr19_64_1 vr20_64_1 vr21_64_1 vr22_64_1 vr23_64_1 vr24_64_1 vr25_64_1 vr26_64_1 vr27_64_1 vr28_64_1 vr29_64_1 vr30_64_1 vr31_64_1 ]; + +# AltVect Vector vrS sub-piece selectors for size 32 +attach variables vrS_32_0 [vr0_32_0 vr1_32_0 vr2_32_0 vr3_32_0 vr4_32_0 vr5_32_0 vr6_32_0 vr7_32_0 vr8_32_0 vr9_32_0 vr10_32_0 vr11_32_0 vr12_32_0 vr13_32_0 vr14_32_0 vr15_32_0 vr16_32_0 vr17_32_0 vr18_32_0 vr19_32_0 vr20_32_0 vr21_32_0 vr22_32_0 vr23_32_0 vr24_32_0 vr25_32_0 vr26_32_0 vr27_32_0 vr28_32_0 vr29_32_0 vr30_32_0 vr31_32_0 ]; +attach variables vrS_32_1 [vr0_32_1 vr1_32_1 vr2_32_1 vr3_32_1 vr4_32_1 vr5_32_1 vr6_32_1 vr7_32_1 vr8_32_1 vr9_32_1 vr10_32_1 vr11_32_1 vr12_32_1 vr13_32_1 vr14_32_1 vr15_32_1 vr16_32_1 vr17_32_1 vr18_32_1 vr19_32_1 vr20_32_1 vr21_32_1 vr22_32_1 vr23_32_1 vr24_32_1 vr25_32_1 vr26_32_1 vr27_32_1 vr28_32_1 vr29_32_1 vr30_32_1 vr31_32_1 ]; +attach variables vrS_32_2 [vr0_32_2 vr1_32_2 vr2_32_2 vr3_32_2 vr4_32_2 vr5_32_2 vr6_32_2 vr7_32_2 vr8_32_2 vr9_32_2 vr10_32_2 vr11_32_2 vr12_32_2 vr13_32_2 vr14_32_2 vr15_32_2 vr16_32_2 vr17_32_2 vr18_32_2 vr19_32_2 vr20_32_2 vr21_32_2 vr22_32_2 vr23_32_2 vr24_32_2 vr25_32_2 vr26_32_2 vr27_32_2 vr28_32_2 vr29_32_2 vr30_32_2 vr31_32_2 ]; +attach variables vrS_32_3 [vr0_32_3 vr1_32_3 vr2_32_3 vr3_32_3 vr4_32_3 vr5_32_3 vr6_32_3 vr7_32_3 vr8_32_3 vr9_32_3 vr10_32_3 vr11_32_3 vr12_32_3 vr13_32_3 vr14_32_3 vr15_32_3 vr16_32_3 vr17_32_3 vr18_32_3 vr19_32_3 vr20_32_3 vr21_32_3 vr22_32_3 vr23_32_3 vr24_32_3 vr25_32_3 vr26_32_3 vr27_32_3 vr28_32_3 vr29_32_3 vr30_32_3 vr31_32_3 ]; + +# AltVect Vector vrS sub-piece selectors for size 16 +attach variables vrS_16_0 [vr0_16_0 vr1_16_0 vr2_16_0 vr3_16_0 vr4_16_0 vr5_16_0 vr6_16_0 vr7_16_0 vr8_16_0 vr9_16_0 vr10_16_0 vr11_16_0 vr12_16_0 vr13_16_0 vr14_16_0 vr15_16_0 vr16_16_0 vr17_16_0 vr18_16_0 vr19_16_0 vr20_16_0 vr21_16_0 vr22_16_0 vr23_16_0 vr24_16_0 vr25_16_0 vr26_16_0 vr27_16_0 vr28_16_0 vr29_16_0 vr30_16_0 vr31_16_0 ]; +attach variables vrS_16_1 [vr0_16_1 vr1_16_1 vr2_16_1 vr3_16_1 vr4_16_1 vr5_16_1 vr6_16_1 vr7_16_1 vr8_16_1 vr9_16_1 vr10_16_1 vr11_16_1 vr12_16_1 vr13_16_1 vr14_16_1 vr15_16_1 vr16_16_1 vr17_16_1 vr18_16_1 vr19_16_1 vr20_16_1 vr21_16_1 vr22_16_1 vr23_16_1 vr24_16_1 vr25_16_1 vr26_16_1 vr27_16_1 vr28_16_1 vr29_16_1 vr30_16_1 vr31_16_1 ]; +attach variables vrS_16_2 [vr0_16_2 vr1_16_2 vr2_16_2 vr3_16_2 vr4_16_2 vr5_16_2 vr6_16_2 vr7_16_2 vr8_16_2 vr9_16_2 vr10_16_2 vr11_16_2 vr12_16_2 vr13_16_2 vr14_16_2 vr15_16_2 vr16_16_2 vr17_16_2 vr18_16_2 vr19_16_2 vr20_16_2 vr21_16_2 vr22_16_2 vr23_16_2 vr24_16_2 vr25_16_2 vr26_16_2 vr27_16_2 vr28_16_2 vr29_16_2 vr30_16_2 vr31_16_2 ]; +attach variables vrS_16_3 [vr0_16_3 vr1_16_3 vr2_16_3 vr3_16_3 vr4_16_3 vr5_16_3 vr6_16_3 vr7_16_3 vr8_16_3 vr9_16_3 vr10_16_3 vr11_16_3 vr12_16_3 vr13_16_3 vr14_16_3 vr15_16_3 vr16_16_3 vr17_16_3 vr18_16_3 vr19_16_3 vr20_16_3 vr21_16_3 vr22_16_3 vr23_16_3 vr24_16_3 vr25_16_3 vr26_16_3 vr27_16_3 vr28_16_3 vr29_16_3 vr30_16_3 vr31_16_3 ]; +attach variables vrS_16_4 [vr0_16_4 vr1_16_4 vr2_16_4 vr3_16_4 vr4_16_4 vr5_16_4 vr6_16_4 vr7_16_4 vr8_16_4 vr9_16_4 vr10_16_4 vr11_16_4 vr12_16_4 vr13_16_4 vr14_16_4 vr15_16_4 vr16_16_4 vr17_16_4 vr18_16_4 vr19_16_4 vr20_16_4 vr21_16_4 vr22_16_4 vr23_16_4 vr24_16_4 vr25_16_4 vr26_16_4 vr27_16_4 vr28_16_4 vr29_16_4 vr30_16_4 vr31_16_4 ]; +attach variables vrS_16_5 [vr0_16_5 vr1_16_5 vr2_16_5 vr3_16_5 vr4_16_5 vr5_16_5 vr6_16_5 vr7_16_5 vr8_16_5 vr9_16_5 vr10_16_5 vr11_16_5 vr12_16_5 vr13_16_5 vr14_16_5 vr15_16_5 vr16_16_5 vr17_16_5 vr18_16_5 vr19_16_5 vr20_16_5 vr21_16_5 vr22_16_5 vr23_16_5 vr24_16_5 vr25_16_5 vr26_16_5 vr27_16_5 vr28_16_5 vr29_16_5 vr30_16_5 vr31_16_5 ]; +attach variables vrS_16_6 [vr0_16_6 vr1_16_6 vr2_16_6 vr3_16_6 vr4_16_6 vr5_16_6 vr6_16_6 vr7_16_6 vr8_16_6 vr9_16_6 vr10_16_6 vr11_16_6 vr12_16_6 vr13_16_6 vr14_16_6 vr15_16_6 vr16_16_6 vr17_16_6 vr18_16_6 vr19_16_6 vr20_16_6 vr21_16_6 vr22_16_6 vr23_16_6 vr24_16_6 vr25_16_6 vr26_16_6 vr27_16_6 vr28_16_6 vr29_16_6 vr30_16_6 vr31_16_6 ]; +attach variables vrS_16_7 [vr0_16_7 vr1_16_7 vr2_16_7 vr3_16_7 vr4_16_7 vr5_16_7 vr6_16_7 vr7_16_7 vr8_16_7 vr9_16_7 vr10_16_7 vr11_16_7 vr12_16_7 vr13_16_7 vr14_16_7 vr15_16_7 vr16_16_7 vr17_16_7 vr18_16_7 vr19_16_7 vr20_16_7 vr21_16_7 vr22_16_7 vr23_16_7 vr24_16_7 vr25_16_7 vr26_16_7 vr27_16_7 vr28_16_7 vr29_16_7 vr30_16_7 vr31_16_7 ]; + +# AltVect Vector vrS sub-piece selectors for size 8 +attach variables vrS_8_0 [vr0_8_0 vr1_8_0 vr2_8_0 vr3_8_0 vr4_8_0 vr5_8_0 vr6_8_0 vr7_8_0 vr8_8_0 vr9_8_0 vr10_8_0 vr11_8_0 vr12_8_0 vr13_8_0 vr14_8_0 vr15_8_0 vr16_8_0 vr17_8_0 vr18_8_0 vr19_8_0 vr20_8_0 vr21_8_0 vr22_8_0 vr23_8_0 vr24_8_0 vr25_8_0 vr26_8_0 vr27_8_0 vr28_8_0 vr29_8_0 vr30_8_0 vr31_8_0 ]; +attach variables vrS_8_1 [vr0_8_1 vr1_8_1 vr2_8_1 vr3_8_1 vr4_8_1 vr5_8_1 vr6_8_1 vr7_8_1 vr8_8_1 vr9_8_1 vr10_8_1 vr11_8_1 vr12_8_1 vr13_8_1 vr14_8_1 vr15_8_1 vr16_8_1 vr17_8_1 vr18_8_1 vr19_8_1 vr20_8_1 vr21_8_1 vr22_8_1 vr23_8_1 vr24_8_1 vr25_8_1 vr26_8_1 vr27_8_1 vr28_8_1 vr29_8_1 vr30_8_1 vr31_8_1 ]; +attach variables vrS_8_2 [vr0_8_2 vr1_8_2 vr2_8_2 vr3_8_2 vr4_8_2 vr5_8_2 vr6_8_2 vr7_8_2 vr8_8_2 vr9_8_2 vr10_8_2 vr11_8_2 vr12_8_2 vr13_8_2 vr14_8_2 vr15_8_2 vr16_8_2 vr17_8_2 vr18_8_2 vr19_8_2 vr20_8_2 vr21_8_2 vr22_8_2 vr23_8_2 vr24_8_2 vr25_8_2 vr26_8_2 vr27_8_2 vr28_8_2 vr29_8_2 vr30_8_2 vr31_8_2 ]; +attach variables vrS_8_3 [vr0_8_3 vr1_8_3 vr2_8_3 vr3_8_3 vr4_8_3 vr5_8_3 vr6_8_3 vr7_8_3 vr8_8_3 vr9_8_3 vr10_8_3 vr11_8_3 vr12_8_3 vr13_8_3 vr14_8_3 vr15_8_3 vr16_8_3 vr17_8_3 vr18_8_3 vr19_8_3 vr20_8_3 vr21_8_3 vr22_8_3 vr23_8_3 vr24_8_3 vr25_8_3 vr26_8_3 vr27_8_3 vr28_8_3 vr29_8_3 vr30_8_3 vr31_8_3 ]; +attach variables vrS_8_4 [vr0_8_4 vr1_8_4 vr2_8_4 vr3_8_4 vr4_8_4 vr5_8_4 vr6_8_4 vr7_8_4 vr8_8_4 vr9_8_4 vr10_8_4 vr11_8_4 vr12_8_4 vr13_8_4 vr14_8_4 vr15_8_4 vr16_8_4 vr17_8_4 vr18_8_4 vr19_8_4 vr20_8_4 vr21_8_4 vr22_8_4 vr23_8_4 vr24_8_4 vr25_8_4 vr26_8_4 vr27_8_4 vr28_8_4 vr29_8_4 vr30_8_4 vr31_8_4 ]; +attach variables vrS_8_5 [vr0_8_5 vr1_8_5 vr2_8_5 vr3_8_5 vr4_8_5 vr5_8_5 vr6_8_5 vr7_8_5 vr8_8_5 vr9_8_5 vr10_8_5 vr11_8_5 vr12_8_5 vr13_8_5 vr14_8_5 vr15_8_5 vr16_8_5 vr17_8_5 vr18_8_5 vr19_8_5 vr20_8_5 vr21_8_5 vr22_8_5 vr23_8_5 vr24_8_5 vr25_8_5 vr26_8_5 vr27_8_5 vr28_8_5 vr29_8_5 vr30_8_5 vr31_8_5 ]; +attach variables vrS_8_6 [vr0_8_6 vr1_8_6 vr2_8_6 vr3_8_6 vr4_8_6 vr5_8_6 vr6_8_6 vr7_8_6 vr8_8_6 vr9_8_6 vr10_8_6 vr11_8_6 vr12_8_6 vr13_8_6 vr14_8_6 vr15_8_6 vr16_8_6 vr17_8_6 vr18_8_6 vr19_8_6 vr20_8_6 vr21_8_6 vr22_8_6 vr23_8_6 vr24_8_6 vr25_8_6 vr26_8_6 vr27_8_6 vr28_8_6 vr29_8_6 vr30_8_6 vr31_8_6 ]; +attach variables vrS_8_7 [vr0_8_7 vr1_8_7 vr2_8_7 vr3_8_7 vr4_8_7 vr5_8_7 vr6_8_7 vr7_8_7 vr8_8_7 vr9_8_7 vr10_8_7 vr11_8_7 vr12_8_7 vr13_8_7 vr14_8_7 vr15_8_7 vr16_8_7 vr17_8_7 vr18_8_7 vr19_8_7 vr20_8_7 vr21_8_7 vr22_8_7 vr23_8_7 vr24_8_7 vr25_8_7 vr26_8_7 vr27_8_7 vr28_8_7 vr29_8_7 vr30_8_7 vr31_8_7 ]; +attach variables vrS_8_8 [vr0_8_8 vr1_8_8 vr2_8_8 vr3_8_8 vr4_8_8 vr5_8_8 vr6_8_8 vr7_8_8 vr8_8_8 vr9_8_8 vr10_8_8 vr11_8_8 vr12_8_8 vr13_8_8 vr14_8_8 vr15_8_8 vr16_8_8 vr17_8_8 vr18_8_8 vr19_8_8 vr20_8_8 vr21_8_8 vr22_8_8 vr23_8_8 vr24_8_8 vr25_8_8 vr26_8_8 vr27_8_8 vr28_8_8 vr29_8_8 vr30_8_8 vr31_8_8 ]; +attach variables vrS_8_9 [vr0_8_9 vr1_8_9 vr2_8_9 vr3_8_9 vr4_8_9 vr5_8_9 vr6_8_9 vr7_8_9 vr8_8_9 vr9_8_9 vr10_8_9 vr11_8_9 vr12_8_9 vr13_8_9 vr14_8_9 vr15_8_9 vr16_8_9 vr17_8_9 vr18_8_9 vr19_8_9 vr20_8_9 vr21_8_9 vr22_8_9 vr23_8_9 vr24_8_9 vr25_8_9 vr26_8_9 vr27_8_9 vr28_8_9 vr29_8_9 vr30_8_9 vr31_8_9 ]; +attach variables vrS_8_10 [vr0_8_10 vr1_8_10 vr2_8_10 vr3_8_10 vr4_8_10 vr5_8_10 vr6_8_10 vr7_8_10 vr8_8_10 vr9_8_10 vr10_8_10 vr11_8_10 vr12_8_10 vr13_8_10 vr14_8_10 vr15_8_10 vr16_8_10 vr17_8_10 vr18_8_10 vr19_8_10 vr20_8_10 vr21_8_10 vr22_8_10 vr23_8_10 vr24_8_10 vr25_8_10 vr26_8_10 vr27_8_10 vr28_8_10 vr29_8_10 vr30_8_10 vr31_8_10 ]; +attach variables vrS_8_11 [vr0_8_11 vr1_8_11 vr2_8_11 vr3_8_11 vr4_8_11 vr5_8_11 vr6_8_11 vr7_8_11 vr8_8_11 vr9_8_11 vr10_8_11 vr11_8_11 vr12_8_11 vr13_8_11 vr14_8_11 vr15_8_11 vr16_8_11 vr17_8_11 vr18_8_11 vr19_8_11 vr20_8_11 vr21_8_11 vr22_8_11 vr23_8_11 vr24_8_11 vr25_8_11 vr26_8_11 vr27_8_11 vr28_8_11 vr29_8_11 vr30_8_11 vr31_8_11 ]; +attach variables vrS_8_12 [vr0_8_12 vr1_8_12 vr2_8_12 vr3_8_12 vr4_8_12 vr5_8_12 vr6_8_12 vr7_8_12 vr8_8_12 vr9_8_12 vr10_8_12 vr11_8_12 vr12_8_12 vr13_8_12 vr14_8_12 vr15_8_12 vr16_8_12 vr17_8_12 vr18_8_12 vr19_8_12 vr20_8_12 vr21_8_12 vr22_8_12 vr23_8_12 vr24_8_12 vr25_8_12 vr26_8_12 vr27_8_12 vr28_8_12 vr29_8_12 vr30_8_12 vr31_8_12 ]; +attach variables vrS_8_13 [vr0_8_13 vr1_8_13 vr2_8_13 vr3_8_13 vr4_8_13 vr5_8_13 vr6_8_13 vr7_8_13 vr8_8_13 vr9_8_13 vr10_8_13 vr11_8_13 vr12_8_13 vr13_8_13 vr14_8_13 vr15_8_13 vr16_8_13 vr17_8_13 vr18_8_13 vr19_8_13 vr20_8_13 vr21_8_13 vr22_8_13 vr23_8_13 vr24_8_13 vr25_8_13 vr26_8_13 vr27_8_13 vr28_8_13 vr29_8_13 vr30_8_13 vr31_8_13 ]; +attach variables vrS_8_14 [vr0_8_14 vr1_8_14 vr2_8_14 vr3_8_14 vr4_8_14 vr5_8_14 vr6_8_14 vr7_8_14 vr8_8_14 vr9_8_14 vr10_8_14 vr11_8_14 vr12_8_14 vr13_8_14 vr14_8_14 vr15_8_14 vr16_8_14 vr17_8_14 vr18_8_14 vr19_8_14 vr20_8_14 vr21_8_14 vr22_8_14 vr23_8_14 vr24_8_14 vr25_8_14 vr26_8_14 vr27_8_14 vr28_8_14 vr29_8_14 vr30_8_14 vr31_8_14 ]; +attach variables vrS_8_15 [vr0_8_15 vr1_8_15 vr2_8_15 vr3_8_15 vr4_8_15 vr5_8_15 vr6_8_15 vr7_8_15 vr8_8_15 vr9_8_15 vr10_8_15 vr11_8_15 vr12_8_15 vr13_8_15 vr14_8_15 vr15_8_15 vr16_8_15 vr17_8_15 vr18_8_15 vr19_8_15 vr20_8_15 vr21_8_15 vr22_8_15 vr23_8_15 vr24_8_15 vr25_8_15 vr26_8_15 vr27_8_15 vr28_8_15 vr29_8_15 vr30_8_15 vr31_8_15 ]; + + +# AltVect Vector vrC sub-piece selectors + +# AltVect Vector vrC sub-piece selectors for size 64 +attach variables vrC_64_0 [vr0_64_0 vr1_64_0 vr2_64_0 vr3_64_0 vr4_64_0 vr5_64_0 vr6_64_0 vr7_64_0 vr8_64_0 vr9_64_0 vr10_64_0 vr11_64_0 vr12_64_0 vr13_64_0 vr14_64_0 vr15_64_0 vr16_64_0 vr17_64_0 vr18_64_0 vr19_64_0 vr20_64_0 vr21_64_0 vr22_64_0 vr23_64_0 vr24_64_0 vr25_64_0 vr26_64_0 vr27_64_0 vr28_64_0 vr29_64_0 vr30_64_0 vr31_64_0 ]; +attach variables vrC_64_1 [vr0_64_1 vr1_64_1 vr2_64_1 vr3_64_1 vr4_64_1 vr5_64_1 vr6_64_1 vr7_64_1 vr8_64_1 vr9_64_1 vr10_64_1 vr11_64_1 vr12_64_1 vr13_64_1 vr14_64_1 vr15_64_1 vr16_64_1 vr17_64_1 vr18_64_1 vr19_64_1 vr20_64_1 vr21_64_1 vr22_64_1 vr23_64_1 vr24_64_1 vr25_64_1 vr26_64_1 vr27_64_1 vr28_64_1 vr29_64_1 vr30_64_1 vr31_64_1 ]; + +# AltVect Vector vrC sub-piece selectors for size 32 +attach variables vrC_32_0 [vr0_32_0 vr1_32_0 vr2_32_0 vr3_32_0 vr4_32_0 vr5_32_0 vr6_32_0 vr7_32_0 vr8_32_0 vr9_32_0 vr10_32_0 vr11_32_0 vr12_32_0 vr13_32_0 vr14_32_0 vr15_32_0 vr16_32_0 vr17_32_0 vr18_32_0 vr19_32_0 vr20_32_0 vr21_32_0 vr22_32_0 vr23_32_0 vr24_32_0 vr25_32_0 vr26_32_0 vr27_32_0 vr28_32_0 vr29_32_0 vr30_32_0 vr31_32_0 ]; +attach variables vrC_32_1 [vr0_32_1 vr1_32_1 vr2_32_1 vr3_32_1 vr4_32_1 vr5_32_1 vr6_32_1 vr7_32_1 vr8_32_1 vr9_32_1 vr10_32_1 vr11_32_1 vr12_32_1 vr13_32_1 vr14_32_1 vr15_32_1 vr16_32_1 vr17_32_1 vr18_32_1 vr19_32_1 vr20_32_1 vr21_32_1 vr22_32_1 vr23_32_1 vr24_32_1 vr25_32_1 vr26_32_1 vr27_32_1 vr28_32_1 vr29_32_1 vr30_32_1 vr31_32_1 ]; +attach variables vrC_32_2 [vr0_32_2 vr1_32_2 vr2_32_2 vr3_32_2 vr4_32_2 vr5_32_2 vr6_32_2 vr7_32_2 vr8_32_2 vr9_32_2 vr10_32_2 vr11_32_2 vr12_32_2 vr13_32_2 vr14_32_2 vr15_32_2 vr16_32_2 vr17_32_2 vr18_32_2 vr19_32_2 vr20_32_2 vr21_32_2 vr22_32_2 vr23_32_2 vr24_32_2 vr25_32_2 vr26_32_2 vr27_32_2 vr28_32_2 vr29_32_2 vr30_32_2 vr31_32_2 ]; +attach variables vrC_32_3 [vr0_32_3 vr1_32_3 vr2_32_3 vr3_32_3 vr4_32_3 vr5_32_3 vr6_32_3 vr7_32_3 vr8_32_3 vr9_32_3 vr10_32_3 vr11_32_3 vr12_32_3 vr13_32_3 vr14_32_3 vr15_32_3 vr16_32_3 vr17_32_3 vr18_32_3 vr19_32_3 vr20_32_3 vr21_32_3 vr22_32_3 vr23_32_3 vr24_32_3 vr25_32_3 vr26_32_3 vr27_32_3 vr28_32_3 vr29_32_3 vr30_32_3 vr31_32_3 ]; + +# AltVect Vector vrC sub-piece selectors for size 16 +attach variables vrC_16_0 [vr0_16_0 vr1_16_0 vr2_16_0 vr3_16_0 vr4_16_0 vr5_16_0 vr6_16_0 vr7_16_0 vr8_16_0 vr9_16_0 vr10_16_0 vr11_16_0 vr12_16_0 vr13_16_0 vr14_16_0 vr15_16_0 vr16_16_0 vr17_16_0 vr18_16_0 vr19_16_0 vr20_16_0 vr21_16_0 vr22_16_0 vr23_16_0 vr24_16_0 vr25_16_0 vr26_16_0 vr27_16_0 vr28_16_0 vr29_16_0 vr30_16_0 vr31_16_0 ]; +attach variables vrC_16_1 [vr0_16_1 vr1_16_1 vr2_16_1 vr3_16_1 vr4_16_1 vr5_16_1 vr6_16_1 vr7_16_1 vr8_16_1 vr9_16_1 vr10_16_1 vr11_16_1 vr12_16_1 vr13_16_1 vr14_16_1 vr15_16_1 vr16_16_1 vr17_16_1 vr18_16_1 vr19_16_1 vr20_16_1 vr21_16_1 vr22_16_1 vr23_16_1 vr24_16_1 vr25_16_1 vr26_16_1 vr27_16_1 vr28_16_1 vr29_16_1 vr30_16_1 vr31_16_1 ]; +attach variables vrC_16_2 [vr0_16_2 vr1_16_2 vr2_16_2 vr3_16_2 vr4_16_2 vr5_16_2 vr6_16_2 vr7_16_2 vr8_16_2 vr9_16_2 vr10_16_2 vr11_16_2 vr12_16_2 vr13_16_2 vr14_16_2 vr15_16_2 vr16_16_2 vr17_16_2 vr18_16_2 vr19_16_2 vr20_16_2 vr21_16_2 vr22_16_2 vr23_16_2 vr24_16_2 vr25_16_2 vr26_16_2 vr27_16_2 vr28_16_2 vr29_16_2 vr30_16_2 vr31_16_2 ]; +attach variables vrC_16_3 [vr0_16_3 vr1_16_3 vr2_16_3 vr3_16_3 vr4_16_3 vr5_16_3 vr6_16_3 vr7_16_3 vr8_16_3 vr9_16_3 vr10_16_3 vr11_16_3 vr12_16_3 vr13_16_3 vr14_16_3 vr15_16_3 vr16_16_3 vr17_16_3 vr18_16_3 vr19_16_3 vr20_16_3 vr21_16_3 vr22_16_3 vr23_16_3 vr24_16_3 vr25_16_3 vr26_16_3 vr27_16_3 vr28_16_3 vr29_16_3 vr30_16_3 vr31_16_3 ]; +attach variables vrC_16_4 [vr0_16_4 vr1_16_4 vr2_16_4 vr3_16_4 vr4_16_4 vr5_16_4 vr6_16_4 vr7_16_4 vr8_16_4 vr9_16_4 vr10_16_4 vr11_16_4 vr12_16_4 vr13_16_4 vr14_16_4 vr15_16_4 vr16_16_4 vr17_16_4 vr18_16_4 vr19_16_4 vr20_16_4 vr21_16_4 vr22_16_4 vr23_16_4 vr24_16_4 vr25_16_4 vr26_16_4 vr27_16_4 vr28_16_4 vr29_16_4 vr30_16_4 vr31_16_4 ]; +attach variables vrC_16_5 [vr0_16_5 vr1_16_5 vr2_16_5 vr3_16_5 vr4_16_5 vr5_16_5 vr6_16_5 vr7_16_5 vr8_16_5 vr9_16_5 vr10_16_5 vr11_16_5 vr12_16_5 vr13_16_5 vr14_16_5 vr15_16_5 vr16_16_5 vr17_16_5 vr18_16_5 vr19_16_5 vr20_16_5 vr21_16_5 vr22_16_5 vr23_16_5 vr24_16_5 vr25_16_5 vr26_16_5 vr27_16_5 vr28_16_5 vr29_16_5 vr30_16_5 vr31_16_5 ]; +attach variables vrC_16_6 [vr0_16_6 vr1_16_6 vr2_16_6 vr3_16_6 vr4_16_6 vr5_16_6 vr6_16_6 vr7_16_6 vr8_16_6 vr9_16_6 vr10_16_6 vr11_16_6 vr12_16_6 vr13_16_6 vr14_16_6 vr15_16_6 vr16_16_6 vr17_16_6 vr18_16_6 vr19_16_6 vr20_16_6 vr21_16_6 vr22_16_6 vr23_16_6 vr24_16_6 vr25_16_6 vr26_16_6 vr27_16_6 vr28_16_6 vr29_16_6 vr30_16_6 vr31_16_6 ]; +attach variables vrC_16_7 [vr0_16_7 vr1_16_7 vr2_16_7 vr3_16_7 vr4_16_7 vr5_16_7 vr6_16_7 vr7_16_7 vr8_16_7 vr9_16_7 vr10_16_7 vr11_16_7 vr12_16_7 vr13_16_7 vr14_16_7 vr15_16_7 vr16_16_7 vr17_16_7 vr18_16_7 vr19_16_7 vr20_16_7 vr21_16_7 vr22_16_7 vr23_16_7 vr24_16_7 vr25_16_7 vr26_16_7 vr27_16_7 vr28_16_7 vr29_16_7 vr30_16_7 vr31_16_7 ]; + +# AltVect Vector vrC sub-piece selectors for size 8 +attach variables vrC_8_0 [vr0_8_0 vr1_8_0 vr2_8_0 vr3_8_0 vr4_8_0 vr5_8_0 vr6_8_0 vr7_8_0 vr8_8_0 vr9_8_0 vr10_8_0 vr11_8_0 vr12_8_0 vr13_8_0 vr14_8_0 vr15_8_0 vr16_8_0 vr17_8_0 vr18_8_0 vr19_8_0 vr20_8_0 vr21_8_0 vr22_8_0 vr23_8_0 vr24_8_0 vr25_8_0 vr26_8_0 vr27_8_0 vr28_8_0 vr29_8_0 vr30_8_0 vr31_8_0 ]; +attach variables vrC_8_1 [vr0_8_1 vr1_8_1 vr2_8_1 vr3_8_1 vr4_8_1 vr5_8_1 vr6_8_1 vr7_8_1 vr8_8_1 vr9_8_1 vr10_8_1 vr11_8_1 vr12_8_1 vr13_8_1 vr14_8_1 vr15_8_1 vr16_8_1 vr17_8_1 vr18_8_1 vr19_8_1 vr20_8_1 vr21_8_1 vr22_8_1 vr23_8_1 vr24_8_1 vr25_8_1 vr26_8_1 vr27_8_1 vr28_8_1 vr29_8_1 vr30_8_1 vr31_8_1 ]; +attach variables vrC_8_2 [vr0_8_2 vr1_8_2 vr2_8_2 vr3_8_2 vr4_8_2 vr5_8_2 vr6_8_2 vr7_8_2 vr8_8_2 vr9_8_2 vr10_8_2 vr11_8_2 vr12_8_2 vr13_8_2 vr14_8_2 vr15_8_2 vr16_8_2 vr17_8_2 vr18_8_2 vr19_8_2 vr20_8_2 vr21_8_2 vr22_8_2 vr23_8_2 vr24_8_2 vr25_8_2 vr26_8_2 vr27_8_2 vr28_8_2 vr29_8_2 vr30_8_2 vr31_8_2 ]; +attach variables vrC_8_3 [vr0_8_3 vr1_8_3 vr2_8_3 vr3_8_3 vr4_8_3 vr5_8_3 vr6_8_3 vr7_8_3 vr8_8_3 vr9_8_3 vr10_8_3 vr11_8_3 vr12_8_3 vr13_8_3 vr14_8_3 vr15_8_3 vr16_8_3 vr17_8_3 vr18_8_3 vr19_8_3 vr20_8_3 vr21_8_3 vr22_8_3 vr23_8_3 vr24_8_3 vr25_8_3 vr26_8_3 vr27_8_3 vr28_8_3 vr29_8_3 vr30_8_3 vr31_8_3 ]; +attach variables vrC_8_4 [vr0_8_4 vr1_8_4 vr2_8_4 vr3_8_4 vr4_8_4 vr5_8_4 vr6_8_4 vr7_8_4 vr8_8_4 vr9_8_4 vr10_8_4 vr11_8_4 vr12_8_4 vr13_8_4 vr14_8_4 vr15_8_4 vr16_8_4 vr17_8_4 vr18_8_4 vr19_8_4 vr20_8_4 vr21_8_4 vr22_8_4 vr23_8_4 vr24_8_4 vr25_8_4 vr26_8_4 vr27_8_4 vr28_8_4 vr29_8_4 vr30_8_4 vr31_8_4 ]; +attach variables vrC_8_5 [vr0_8_5 vr1_8_5 vr2_8_5 vr3_8_5 vr4_8_5 vr5_8_5 vr6_8_5 vr7_8_5 vr8_8_5 vr9_8_5 vr10_8_5 vr11_8_5 vr12_8_5 vr13_8_5 vr14_8_5 vr15_8_5 vr16_8_5 vr17_8_5 vr18_8_5 vr19_8_5 vr20_8_5 vr21_8_5 vr22_8_5 vr23_8_5 vr24_8_5 vr25_8_5 vr26_8_5 vr27_8_5 vr28_8_5 vr29_8_5 vr30_8_5 vr31_8_5 ]; +attach variables vrC_8_6 [vr0_8_6 vr1_8_6 vr2_8_6 vr3_8_6 vr4_8_6 vr5_8_6 vr6_8_6 vr7_8_6 vr8_8_6 vr9_8_6 vr10_8_6 vr11_8_6 vr12_8_6 vr13_8_6 vr14_8_6 vr15_8_6 vr16_8_6 vr17_8_6 vr18_8_6 vr19_8_6 vr20_8_6 vr21_8_6 vr22_8_6 vr23_8_6 vr24_8_6 vr25_8_6 vr26_8_6 vr27_8_6 vr28_8_6 vr29_8_6 vr30_8_6 vr31_8_6 ]; +attach variables vrC_8_7 [vr0_8_7 vr1_8_7 vr2_8_7 vr3_8_7 vr4_8_7 vr5_8_7 vr6_8_7 vr7_8_7 vr8_8_7 vr9_8_7 vr10_8_7 vr11_8_7 vr12_8_7 vr13_8_7 vr14_8_7 vr15_8_7 vr16_8_7 vr17_8_7 vr18_8_7 vr19_8_7 vr20_8_7 vr21_8_7 vr22_8_7 vr23_8_7 vr24_8_7 vr25_8_7 vr26_8_7 vr27_8_7 vr28_8_7 vr29_8_7 vr30_8_7 vr31_8_7 ]; +attach variables vrC_8_8 [vr0_8_8 vr1_8_8 vr2_8_8 vr3_8_8 vr4_8_8 vr5_8_8 vr6_8_8 vr7_8_8 vr8_8_8 vr9_8_8 vr10_8_8 vr11_8_8 vr12_8_8 vr13_8_8 vr14_8_8 vr15_8_8 vr16_8_8 vr17_8_8 vr18_8_8 vr19_8_8 vr20_8_8 vr21_8_8 vr22_8_8 vr23_8_8 vr24_8_8 vr25_8_8 vr26_8_8 vr27_8_8 vr28_8_8 vr29_8_8 vr30_8_8 vr31_8_8 ]; +attach variables vrC_8_9 [vr0_8_9 vr1_8_9 vr2_8_9 vr3_8_9 vr4_8_9 vr5_8_9 vr6_8_9 vr7_8_9 vr8_8_9 vr9_8_9 vr10_8_9 vr11_8_9 vr12_8_9 vr13_8_9 vr14_8_9 vr15_8_9 vr16_8_9 vr17_8_9 vr18_8_9 vr19_8_9 vr20_8_9 vr21_8_9 vr22_8_9 vr23_8_9 vr24_8_9 vr25_8_9 vr26_8_9 vr27_8_9 vr28_8_9 vr29_8_9 vr30_8_9 vr31_8_9 ]; +attach variables vrC_8_10 [vr0_8_10 vr1_8_10 vr2_8_10 vr3_8_10 vr4_8_10 vr5_8_10 vr6_8_10 vr7_8_10 vr8_8_10 vr9_8_10 vr10_8_10 vr11_8_10 vr12_8_10 vr13_8_10 vr14_8_10 vr15_8_10 vr16_8_10 vr17_8_10 vr18_8_10 vr19_8_10 vr20_8_10 vr21_8_10 vr22_8_10 vr23_8_10 vr24_8_10 vr25_8_10 vr26_8_10 vr27_8_10 vr28_8_10 vr29_8_10 vr30_8_10 vr31_8_10 ]; +attach variables vrC_8_11 [vr0_8_11 vr1_8_11 vr2_8_11 vr3_8_11 vr4_8_11 vr5_8_11 vr6_8_11 vr7_8_11 vr8_8_11 vr9_8_11 vr10_8_11 vr11_8_11 vr12_8_11 vr13_8_11 vr14_8_11 vr15_8_11 vr16_8_11 vr17_8_11 vr18_8_11 vr19_8_11 vr20_8_11 vr21_8_11 vr22_8_11 vr23_8_11 vr24_8_11 vr25_8_11 vr26_8_11 vr27_8_11 vr28_8_11 vr29_8_11 vr30_8_11 vr31_8_11 ]; +attach variables vrC_8_12 [vr0_8_12 vr1_8_12 vr2_8_12 vr3_8_12 vr4_8_12 vr5_8_12 vr6_8_12 vr7_8_12 vr8_8_12 vr9_8_12 vr10_8_12 vr11_8_12 vr12_8_12 vr13_8_12 vr14_8_12 vr15_8_12 vr16_8_12 vr17_8_12 vr18_8_12 vr19_8_12 vr20_8_12 vr21_8_12 vr22_8_12 vr23_8_12 vr24_8_12 vr25_8_12 vr26_8_12 vr27_8_12 vr28_8_12 vr29_8_12 vr30_8_12 vr31_8_12 ]; +attach variables vrC_8_13 [vr0_8_13 vr1_8_13 vr2_8_13 vr3_8_13 vr4_8_13 vr5_8_13 vr6_8_13 vr7_8_13 vr8_8_13 vr9_8_13 vr10_8_13 vr11_8_13 vr12_8_13 vr13_8_13 vr14_8_13 vr15_8_13 vr16_8_13 vr17_8_13 vr18_8_13 vr19_8_13 vr20_8_13 vr21_8_13 vr22_8_13 vr23_8_13 vr24_8_13 vr25_8_13 vr26_8_13 vr27_8_13 vr28_8_13 vr29_8_13 vr30_8_13 vr31_8_13 ]; +attach variables vrC_8_14 [vr0_8_14 vr1_8_14 vr2_8_14 vr3_8_14 vr4_8_14 vr5_8_14 vr6_8_14 vr7_8_14 vr8_8_14 vr9_8_14 vr10_8_14 vr11_8_14 vr12_8_14 vr13_8_14 vr14_8_14 vr15_8_14 vr16_8_14 vr17_8_14 vr18_8_14 vr19_8_14 vr20_8_14 vr21_8_14 vr22_8_14 vr23_8_14 vr24_8_14 vr25_8_14 vr26_8_14 vr27_8_14 vr28_8_14 vr29_8_14 vr30_8_14 vr31_8_14 ]; +attach variables vrC_8_15 [vr0_8_15 vr1_8_15 vr2_8_15 vr3_8_15 vr4_8_15 vr5_8_15 vr6_8_15 vr7_8_15 vr8_8_15 vr9_8_15 vr10_8_15 vr11_8_15 vr12_8_15 vr13_8_15 vr14_8_15 vr15_8_15 vr16_8_15 vr17_8_15 vr18_8_15 vr19_8_15 vr20_8_15 vr21_8_15 vr22_8_15 vr23_8_15 vr24_8_15 vr25_8_15 vr26_8_15 vr27_8_15 vr28_8_15 vr29_8_15 vr30_8_15 vr31_8_15 ]; + +################################################################ +# Pseudo Instructions +################################################################ + +define pcodeop clearHistory; +define pcodeop countTrailingZeros; +define pcodeop dataCacheBlockAllocate; +define pcodeop dataCacheBlockFlush; +define pcodeop dataCacheBlockInvalidate; +define pcodeop dataCacheBlockStore; +define pcodeop dataCacheBlockTouch; +define pcodeop dataCacheBlockTouchForStore; +define pcodeop dataCacheBlockClearToZero; +define pcodeop dataCacheCongruenceClassInvalidate; +define pcodeop dataCacheRead; +define pcodeop externalControlIn; +define pcodeop externalControlOut; +define pcodeop enforceInOrderExecutionIO; +define pcodeop instructionCacheBlockInvalidate; +define pcodeop instructionCacheBlockTouch; +define pcodeop instructionCacheCongruenceClassInvalidate; +define pcodeop instructionCacheRead; +define pcodeop instructionSynchronize; + + +define pcodeop floatAddOverflow; +define pcodeop floatDivOverflow; +define pcodeop floatAddRoundedUp; +define pcodeop floatDivRoundedUp; +define pcodeop floatAddInexact; +define pcodeop floatDivInexact; +define pcodeop floatAddUnderflow; +define pcodeop floatDivUnderflow; +define pcodeop floatInfinityAdd; +define pcodeop intToFloatRoundedUp; +define pcodeop intToFloatInexact; +define pcodeop invalidFloatToInt; +define pcodeop floatToIntRoundedUp; +define pcodeop floatToIntInexact; +define pcodeop floatInfinityDivide; +define pcodeop floatMaddInexact; +define pcodeop floatMaddRoundedUp; +define pcodeop floatMaddOverflow; +define pcodeop floatMaddUnderflow; +define pcodeop floatInfinityMulZero; + +define pcodeop floatMsubInexact; +define pcodeop floatMsubRoundedUp; +define pcodeop floatMsubOverflow; +define pcodeop floatMsubUnderflow; +define pcodeop floatInfinitySub; + +define pcodeop floatSubRoundedUp; +define pcodeop floatSubInexact; +define pcodeop floatSubOverflow; +define pcodeop floatSubUnderflow; + +define pcodeop floatMulRoundedUp; +define pcodeop floatMulOverflow; +define pcodeop floatMulUnderflow; +define pcodeop floatMulInexact; +define pcodeop sqrtInvalid; +define pcodeop floatSqrtRoundedUp; +define pcodeop floatSqrtInexact; + +define pcodeop eventInterrupt; +define pcodeop illegal; +define pcodeop message; +define pcodeop movebuffer; +define pcodeop stopT; +define pcodeop waitT; + +define pcodeop mematom; + +define pcodeop random; +define pcodeop returnFromInterrupt; +define pcodeop returnFromCriticalInterrupt; +define pcodeop returnFromDebugInterrupt; +define pcodeop returnFromGuestInterrupt; +define pcodeop returnFromMachineCheckInterrupt; +define pcodeop syscall; +define pcodeop slbInvalidateAll; +define pcodeop slbInvalidateEntry; +define pcodeop slbMoveFromEntryESID; +define pcodeop slbMoveFromEntryVSID; +define pcodeop slbMoveToEntry; +define pcodeop storeDoubleWordConditionalIndexed; +define pcodeop storeWordConditionalIndexed; +define pcodeop trapWord; +define pcodeop trapDoubleWordImmediate; +define pcodeop trapDoubleWord; +define pcodeop sync; +define pcodeop loadString; +define pcodeop storeString; + +define pcodeop xer_mac_update; + +define pcodeop macchw; +define pcodeop macchws; +define pcodeop macchwsu; +define pcodeop macchwu; + +define pcodeop machhw; +define pcodeop machhws; +define pcodeop machhwsu; +define pcodeop machhwu; + +define pcodeop maclhw; +define pcodeop maclhws; +define pcodeop maclhwsu; +define pcodeop maclhwu; + +define pcodeop mulchw; +define pcodeop mulchwu; + +define pcodeop mulhhw; +define pcodeop mulhhwu; + +define pcodeop mullhw; +define pcodeop mullhwu; + +define pcodeop nmacchw; +define pcodeop nmacchws; + +define pcodeop nmachhw; +define pcodeop nmachhws; + +define pcodeop nmaclhw; +define pcodeop nmaclhws; + +define pcodeop copytrans; +define pcodeop pastetrans; +define pcodeop transaction; +define pcodeop TLBRead; +define pcodeop TLBSearchIndexed; +define pcodeop TLBWrite; +define pcodeop WriteExternalEnable; +define pcodeop WriteExternalEnableImmediate; + +# This is really used in the altivec version, but since it's a registered pcode op +# and due to the way things get @included, this needs to be here +define pcodeop vectorPermute; + + +################################################################ +# Macros +################################################################ + +macro shiftCarry(value, sa) +{ + local mask = value; # force mask to have same size as value (may vary) + mask = (1 << sa) - 1; + xer_ca = (value s< 0) && ((value & mask)!=0); +} +macro getCrBit(crReg, bitIndex, result) +{ + tmp:1 = crReg >> (3-bitIndex); + result = tmp & 1; +} +macro setCrBit(crReg, bitIndex, bit) +{ + shift:1 = 3-bitIndex; + mask:1 = ~(1< 0)); # 0b010 + setCrBit(cr0, 2, (result == 0)); # 0b001 + setCrBit(cr0, 3, (xer_so & 1)); +} + +macro addOverflow(a,b) { + xer_ov = scarry(a,b); + xer_so = xer_so || xer_ov; +} + +macro subOverflow(a,b) { + xer_ov = sborrow(a,b); + xer_so = xer_so || xer_ov; +} + +macro addExtendedCarry(op1,op2){ + local carryIn:$(REGISTER_SIZE) = zext(xer_ca); + tmp:$(REGISTER_SIZE) = op2 + carryIn; + xer_ca = carry(op2, carryIn) || carry(op1, tmp); +} + +macro addExtendedOverflow(op1, op2) { + local carryIn:$(REGISTER_SIZE) = zext(xer_ca); + tmp:$(REGISTER_SIZE) = op1 + op2; + xer_ov = scarry(op1,op2) ^^ scarry(tmp, carryIn); + xer_so = xer_so || xer_ov; +} + +macro subExtendedCarry(op1,op2){ + local carryIn = zext(!xer_ca); + local CYa = op1 < op2; + local result = op1 - op2; + xer_ca = !(CYa || (result < carryIn) ); +} + +macro subExtendedOverflow(op1, op2) { + local carryIn = zext(!xer_ca); + local result = op1 - op2; + xer_ov = sborrow( op1, op2 ) ^^ sborrow( result, carryIn ); + xer_so = xer_so || xer_ov; +} + +# check b=0 or (a=0x80000000 and b=-1) +macro divOverflow(a,b) { + xer_ov = (b==0) || ((b==-1) && (a==0x80000000)); + xer_so = xer_so || xer_ov; +} +macro divZero(b) { + xer_ov = (b==0); + xer_so = xer_so || xer_ov; +} + +macro mulOverflow64(result) { + local tmp:4 = result(0); + local sext_tmp:8 = sext(tmp); + xer_ov = (sext_tmp != result); + xer_so = xer_so || xer_ov; +} + +macro mulOverflow128(result) { + local tmp:8 = result(0); + local sext_tmp:16 = sext(tmp); + xer_ov = (sext_tmp != result); + xer_so = xer_so || xer_ov; +} + +macro cr1flags() { + setCrBit(cr1, 0, fp_fx); + setCrBit(cr1, 1, fp_fex); + setCrBit(cr1, 2, fp_vx); + setCrBit(cr3, 2, fp_ox); +} +macro setFPRF(result) { + fp_cc0 = result f< 0; + fp_cc1 = result f> 0; + fp_cc2 = result f== 0; + fp_cc3 = nan(result); +} + +macro setSummaryFPSCR() { + fp_vx = fp_vxsnan | fp_vxisi | fp_vxidi | fp_vxzdz | fp_vximz | fp_vxvc | fp_vxsoft | fp_vxsqrt | fp_vxcvi; + fp_fx = fp_fx | fp_ox | fp_ux | fp_zx | fp_xx; + fp_fex = (fp_vx & fp_ve) ^ (fp_ox & fp_oe) ^ (fp_ux & fp_ue) ^ (fp_zx & fp_ze) ^ (fp_xx & fp_xe); +} + +macro setFPAddFlags(op1, op2, result) { + setFPRF(result); +# fp_fr = floatAddRoundedUp(op1, op2); +# fp_fi = floatAddInexact(op1, op2); +# fp_ox = fp_ox | floatAddOverflow(op1, op2); +# fp_ux = fp_ux | floatAddUnderflow(op1, op2); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(op1) | nan(op2); +# fp_vxisi = fp_vxisi | floatInfinityAdd(op1, op2); + setSummaryFPSCR(); +} +macro setFPDivFlags(op1, op2, result) { + setFPRF(result); +# fp_fr = floatDivRoundedUp(op1, op2); +# fp_fi = floatDivInexact(op1, op2); +# fp_ox = fp_ox | floatDivOverflow(op1, op2); +# fp_ux = fp_ux | floatDivUnderflow(op1, op2); + fp_zx = fp_zx | (op2 f== 0); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(op1) | nan(op2); +# fp_vxidi = fp_vxidi | floatInfinityDivide(op1, op2); + fp_vxzdz = fp_vxzdz | ((op1 f== 0) && (op2 f== 0)); + setSummaryFPSCR(); +} +macro setFPMulFlags(op1, op2, result) { + setFPRF(result); +# fp_fr = floatMulRoundedUp(op1, op2); +# fp_fi = floatMulInexact(op1, op2); +# fp_ox = fp_ox | floatMulOverflow(op1, op2); +# fp_ux = fp_ux | floatMulUnderflow(op1, op2); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(op1) | nan(op2); +# fp_vximz = fp_vximz | floatInfinityMulZero(op1, op2); + setSummaryFPSCR(); +} +macro setFPSubFlags(op1, op2, result) { + setFPRF(result); +# fp_fr = floatSubRoundedUp(op1, op2); +# fp_fi = floatSubInexact(op1, op2); +# fp_ox = fp_ox | floatSubOverflow(op1, op2); +# fp_ux = fp_ux | floatSubUnderflow(op1, op2); +# fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(op1) | nan(op2); +# fp_vxisi = fp_vxisi | floatInfinitySub(op1, op2); + setSummaryFPSCR(); +} + +macro loadRegister(reg, ea) { +@ifdef BIT_64 + reg = zext(*:4(ea)); +@else + reg = *:4(ea); +@endif + ea = ea+4; +} + +macro loadReg(reg) { +@ifdef BIT_64 + reg = zext(*:4(tea)); +@else + reg = *:4(tea); +@endif + tea = tea+4; +} + +macro loadRegisterPartial(reg, ea, sa) { + mask:$(REGISTER_SIZE) = 0xffffffff; + sa = ((4-sa) & 3) * 8; + mask = mask << sa; +@ifdef BIT_64 + reg = zext(*:4(ea)); +@else + reg = *:4(ea); +@endif + reg = reg & mask; + ea = ea + 4; +} + +macro storeRegister(reg, ea) { +@ifdef BIT_64 + tmp:8 = reg; # workaround + *:4(ea) = tmp:4; +@else + *:4(ea) = reg; +@endif + ea = ea+4; +} + +macro storeReg(reg) { +@ifdef BIT_64 + tmp:8 = reg; # workaround + *:4(tea) = tmp:4; +@else + *:4(tea) = reg; +@endif + tea = tea+4; +} + +macro storeRegisterPartial(reg, ea, sa) { +@ifdef BIT_64 + tmp:8 = reg; # workaround + *:4(ea) = tmp:4; +@else + *:4(ea) = reg; +@endif + ea = ea + 4; +} + + +macro packbits( D,a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15, + a16,a17,a18,a19,a20,a21,a22,a23,a24,a25,a26,a27,a28,a29,a30,a31) { + D = zext(a31) & 1; + D=D|(zext(a0)&1)<<31; D=D|(zext(a1)&1)<<30; D=D|(zext(a2)&1)<<29; D=D|(zext(a3)&1)<<28; + D=D|(zext(a4)&1)<<27; D=D|(zext(a5)&1)<<26; D=D|(zext(a6)&1)<<25; D=D|(zext(a7)&1)<<24; + D=D|(zext(a8)&1)<<23; D=D|(zext(a9)&1)<<22; D=D|(zext(a10)&1)<<21; D=D|(zext(a11)&1)<<20; + D=D|(zext(a12)&1)<<19; D=D|(zext(a13)&1)<<18; D=D|(zext(a14)&1)<<17; D=D|(zext(a15)&1)<<16; + D=D|(zext(a16)&1)<<15; D=D|(zext(a17)&1)<<14; D=D|(zext(a18)&1)<<13; D=D|(zext(a19)&1)<<12; + D=D|(zext(a20)&1)<<11; D=D|(zext(a21)&1)<<10; D=D|(zext(a22)&1)<<9; D=D|(zext(a23)&1)<<8; + D=D|(zext(a24)&1)<<7; D=D|(zext(a25)&1)<<6; D=D|(zext(a26)&1)<<5; D=D|(zext(a27)&1)<<4; + D=D|(zext(a28)&1)<<3; D=D|(zext(a29)&1)<<2; D=D|(zext(a30)&1)<<1; + } + +macro unpackbits(D,a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15, + a16,a17,a18,a19,a20,a21,a22,a23,a24,a25,a26,a27,a28,a29,a30,a31) { + a0=(D&0x80000000)!=0; a1=(D&0x40000000)!=0; a2=(D&0x20000000)!=0; a3=(D&0x10000000)!=0; + a4=(D&0x8000000)!=0; a5=(D&0x4000000)!=0; a6=(D&0x2000000)!=0; a7=(D&0x1000000)!=0; + a8=(D&0x800000)!=0; a9=(D&0x400000)!=0; a10=(D&0x200000)!=0; a11=(D&0x100000)!=0; + a12=(D&0x80000)!=0; a13=(D&0x40000)!=0; a14=(D&0x20000)!=0; a15=(D&0x10000)!=0; + a16=(D&0x8000)!=0; a17=(D&0x4000)!=0; a18=(D&0x2000)!=0; a19=(D&0x1000)!=0; + a20=(D&0x800)!=0; a21=(D&0x400)!=0; a22=(D&0x200)!=0; a23=(D&0x100)!=0; + a24=(D&0x80)!=0; a25=(D&0x40)!=0; a26=(D&0x20)!=0; a27=(D&0x10)!=0; + a28=(D&0x8)!=0; a29=(D&0x4)!=0; a30=(D&0x2)!=0; a31=(D&0x1)!=0; } + +macro packFPSCR(tmp) { + packbits(tmp, fp_fx, fp_fex, fp_vx, fp_ox, fp_ux, fp_zx, fp_xx, fp_vxsnan, + fp_vxisi, fp_vxidi, fp_vxzdz, fp_vximz, fp_vxvc, fp_fr, fp_fi, fp_c, + fp_cc0, fp_cc1, fp_cc2, fp_cc3, fp_reserve1, fp_vxsoft, fp_vxsqrt, + fp_vxcvi, fp_ve, fp_oe, fp_ue, fp_ze, fp_xe, fp_ni, fp_rn0, fp_rn1); +} +macro unpackFPSCR(tmp) { + unpackbits(tmp, fp_fx, fp_fex, fp_vx, fp_ox, + fp_ux, fp_zx, fp_xx, fp_vxsnan, + fp_vxisi, fp_vxidi, fp_vxzdz, fp_vximz, + fp_vxvc, fp_fr, fp_fi, fp_c, + fp_cc0, fp_cc1, fp_cc2, fp_cc3, + fp_reserve1, fp_vxsoft, fp_vxsqrt, fp_vxcvi, + fp_ve, fp_oe, fp_ue, fp_ze, + fp_xe, fp_ni, fp_rn0, fp_rn1); +} + + +################################################################ +# Sub-Constructors +################################################################ +REL_ABS: "a" is AA = 1 {} +REL_ABS: is AA = 0 {} + +addressLI: reloc is LI & AA=0 [ reloc = inst_start + LI*4;] { export *[ram]:4 reloc; } +addressLI: reloc is LI & AA=1 [ reloc = LI*4; ] { export *[ram]:4 reloc; } +addressBD: reloc is BD & AA=0 [ reloc = inst_start + BD*4; ] { export *[ram]:4 reloc; } +addressBD: reloc is BD & AA=1 [ reloc = BD*4; ] { export *[ram]:4 reloc; } + +OFF16SH: val is D0 & D1 & D2 [ val = ((D0 << 6) | (D1 << 1) | D2) << 16; ] { export *[const]:4 val;} + +# X 00-------------------------------06 07-07 08-----------10 11-----------13 14------15 16----------------------------------------------------------------------------31 +# X -----------------?-----------------|BO_1=1|-------?-------|-----BI_CR-----|--BI_CC---|---------------------------------------?----------------------------------------| +CC: "lt" is BI_CC=0 & BO_1=1 & BI_CR & BI_CC { tmp:1 = 0; getCrBit(BI_CR, BI_CC, tmp); export tmp; } +CC: "le" is BI_CC=1 & BO_1=0 & BI_CR & BI_CC { tmp:1 = 0; getCrBit(BI_CR, BI_CC, tmp); tmp = !tmp; export tmp; } +CC: "eq" is BI_CC=2 & BO_1=1 & BI_CR & BI_CC { tmp:1 = 0; getCrBit(BI_CR, BI_CC, tmp); export tmp; } +CC: "ge" is BI_CC=0 & BO_1=0 & BI_CR & BI_CC { tmp:1 = 0; getCrBit(BI_CR, BI_CC, tmp); tmp = !tmp; export tmp; } +CC: "gt" is BI_CC=1 & BO_1=1 & BI_CR & BI_CC { tmp:1 = 0; getCrBit(BI_CR, BI_CC, tmp); export tmp; } +CC: "ne" is BI_CC=2 & BO_1=0 & BI_CR & BI_CC { tmp:1 = 0; getCrBit(BI_CR, BI_CC, tmp); tmp = !tmp; export tmp; } +CC: "so" is BI_CC=3 & BO_1=1 & BI_CR & BI_CC { tmp:1 = 0; getCrBit(BI_CR, BI_CC, tmp); export tmp; } +CC: "ns" is BI_CC=3 & BO_1=0 & BI_CR & BI_CC { tmp:1 = 0; getCrBit(BI_CR, BI_CC, tmp); tmp = !tmp; export tmp; } + +TOm: "lt" is TO=16 { } +TOm: "le" is TO=20 { } +TOm: "eq" is TO=4 { } +TOm: "ge" is TO=12 { } +TOm: "gt" is TO=8 { } +TOm: "ne" is TO=24 { } +TOm: "llt" is TO=2 { } +TOm: "lle" is TO=6 { } +TOm: "lge" is TO=5 { } +TOm: "lgt" is TO=1 { } +TOm: "" is TO { } + +CTR_DEC: "z" is BO_3=1 {CTR = CTR-1; tmp:1 = (CTR == 0); export tmp; } +CTR_DEC: "nz" is BO_3=0 {CTR = CTR-1; tmp:1 = (CTR != 0); export tmp; } + +CC_TF: "t" is BO_1=1 {} +CC_TF: "f" is BO_1=0 {} + +# OP=19 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=129 & BIT_0=0 + + +# X 00---------------------------------------------------10 11-----------13 14------15 16----------------------------------------------------------------------------31 +# X ---------------------------?---------------------------|----BI_CR=0----|--BI_CC---|---------------------------------------?----------------------------------------| +CC_OP: "lt" is BI_CC=0 & BI_CR=0 & BI_CC { tmp:1 = 0; getCrBit(cr0, BI_CC, tmp); export tmp; } +CC_OP: "eq" is BI_CC=2 & BI_CR=0 & BI_CC { tmp:1 = 0; getCrBit(cr0, BI_CC, tmp); export tmp; } +CC_OP: "gt" is BI_CC=1 & BI_CR=0 & BI_CC { tmp:1 = 0; getCrBit(cr0, BI_CC, tmp); export tmp; } +CC_OP: "so" is BI_CC=3 & BI_CR=0 & BI_CC { tmp:1 = 0; getCrBit(cr0, BI_CC, tmp); export tmp; } +CC_OP: "4*"^BI_CR^"+lt" is BI_CC=0 & BI_CR & BI_CC { tmp:1 = 0; getCrBit(BI_CR, BI_CC, tmp); export tmp; } +CC_OP: "4*"^BI_CR^"+eq" is BI_CC=2 & BI_CR & BI_CC { tmp:1 = 0; getCrBit(BI_CR, BI_CC, tmp); export tmp; } +CC_OP: "4*"^BI_CR^"+gt" is BI_CC=1 & BI_CR & BI_CC { tmp:1 = 0; getCrBit(BI_CR, BI_CC, tmp); export tmp; } +CC_OP: "4*"^BI_CR^"+so" is BI_CC=3 & BI_CR & BI_CC { tmp:1 = 0; getCrBit(BI_CR, BI_CC, tmp); export tmp; } + +# X 00----------------------------------------------------------------------------15 16-----------18 19------20 21---------------------------------------------------31 +# X ---------------------------------------?----------------------------------------|----CR_B=0-----|-CR_B_CC--|---------------------------?---------------------------| +CC_B_OP: "lt" is CR_B_CC=0 & CR_B=0 & CR_B_CC { tmp:1 = 0; getCrBit(cr0, CR_B_CC, tmp); export tmp; } +CC_B_OP: "eq" is CR_B_CC=2 & CR_B=0 & CR_B_CC { tmp:1 = 0; getCrBit(cr0, CR_B_CC, tmp); export tmp; } +CC_B_OP: "gt" is CR_B_CC=1 & CR_B=0 & CR_B_CC { tmp:1 = 0; getCrBit(cr0, CR_B_CC, tmp); export tmp; } +CC_B_OP: "so" is CR_B_CC=3 & CR_B=0 & CR_B_CC { tmp:1 = 0; getCrBit(cr0, CR_B_CC, tmp); export tmp; } +CC_B_OP: "4*"^CR_B^"+lt" is CR_B_CC=0 & CR_B & CR_B_CC { tmp:1 = 0; getCrBit(CR_B, CR_B_CC, tmp); export tmp; } +CC_B_OP: "4*"^CR_B^"+eq" is CR_B_CC=2 & CR_B & CR_B_CC { tmp:1 = 0; getCrBit(CR_B, CR_B_CC, tmp); export tmp; } +CC_B_OP: "4*"^CR_B^"+gt" is CR_B_CC=1 & CR_B & CR_B_CC { tmp:1 = 0; getCrBit(CR_B, CR_B_CC, tmp); export tmp; } +CC_B_OP: "4*"^CR_B^"+so" is CR_B_CC=3 & CR_B & CR_B_CC { tmp:1 = 0; getCrBit(CR_B, CR_B_CC, tmp); export tmp; } + +# X 00-----------------------------------------------------------------------------------------------------20 21-----------23 24------25 26--------------------------31 +# X ----------------------------------------------------?----------------------------------------------------|----CR_X=0-----|-CR_X_CC--|--------------?---------------| +CC_X_OP: cr0 is CR_X_CC=0 & CR_X=0 & CR_X_CC & cr0 { tmp:1 = 0; getCrBit(cr0, CR_X_CC, tmp); export tmp; } +CC_X_OP: cr0 is CR_X_CC=1 & CR_X=0 & CR_X_CC & cr0 { tmp:1 = 0; getCrBit(cr0, CR_X_CC, tmp); export tmp; } +CC_X_OP: cr0 is CR_X_CC=2 & CR_X=0 & CR_X_CC & cr0 { tmp:1 = 0; getCrBit(cr0, CR_X_CC, tmp); export tmp; } +CC_X_OP: cr0 is CR_X_CC=3 & CR_X=0 & CR_X_CC & cr0 { tmp:1 = 0; getCrBit(cr0, CR_X_CC, tmp); export tmp; } +CC_X_OP: CR_X is CR_X_CC=0 & CR_X & CR_X_CC { tmp:1 = 0; getCrBit(CR_X, CR_X_CC, tmp); export tmp; } +CC_X_OP: CR_X is CR_X_CC=1 & CR_X & CR_X_CC { tmp:1 = 0; getCrBit(CR_X, CR_X_CC, tmp); export tmp; } +CC_X_OP: CR_X is CR_X_CC=2 & CR_X & CR_X_CC { tmp:1 = 0; getCrBit(CR_X, CR_X_CC, tmp); export tmp; } +CC_X_OP: CR_X is CR_X_CC=3 & CR_X & CR_X_CC { tmp:1 = 0; getCrBit(CR_X, CR_X_CC, tmp); export tmp; } + +CC_X_OPm: "lt" is CR_X_CC=0 & CR_X=0 & CR_X_CC { } +CC_X_OPm: "gt" is CR_X_CC=1 & CR_X=0 & CR_X_CC { } +CC_X_OPm: "eq" is CR_X_CC=2 & CR_X=0 & CR_X_CC { } +CC_X_OPm: "so" is CR_X_CC=3 & CR_X=0 & CR_X_CC { } +CC_X_OPm: "lt" is CR_X_CC=0 & CR_X & CR_X_CC { } +CC_X_OPm: "gt" is CR_X_CC=1 & CR_X & CR_X_CC { } +CC_X_OPm: "eq" is CR_X_CC=2 & CR_X & CR_X_CC { } +CC_X_OPm: "so" is CR_X_CC=3 & CR_X & CR_X_CC { } + +# X 00--------------------------05 06-----------08 09------10 11-----------------------------------------------------------------------------------------------------31 +# X --------------?---------------|----CR_D=0-----|-CR_D_CC--|----------------------------------------------------?----------------------------------------------------| +CC_D_OP: "lt" is CR_D_CC=0 & CR_D=0 & CR_D_CC { tmp:1 = 0; getCrBit(cr0, CR_D_CC, tmp); export tmp; } +CC_D_OP: "eq" is CR_D_CC=2 & CR_D=0 & CR_D_CC { tmp:1 = 0; getCrBit(cr0, CR_D_CC, tmp); export tmp; } +CC_D_OP: "gt" is CR_D_CC=1 & CR_D=0 & CR_D_CC { tmp:1 = 0; getCrBit(cr0, CR_D_CC, tmp); export tmp; } +CC_D_OP: "so" is CR_D_CC=3 & CR_D=0 & CR_D_CC { tmp:1 = 0; getCrBit(cr0, CR_D_CC, tmp); export tmp; } +CC_D_OP: "4*"^CR_D^"+lt" is CR_D_CC=0 & CR_D & CR_D_CC { tmp:1 = 0; getCrBit(CR_D, CR_D_CC, tmp); export tmp; } +CC_D_OP: "4*"^CR_D^"+eq" is CR_D_CC=2 & CR_D & CR_D_CC { tmp:1 = 0; getCrBit(CR_D, CR_D_CC, tmp); export tmp; } +CC_D_OP: "4*"^CR_D^"+gt" is CR_D_CC=1 & CR_D & CR_D_CC { tmp:1 = 0; getCrBit(CR_D, CR_D_CC, tmp); export tmp; } +CC_D_OP: "4*"^CR_D^"+so" is CR_D_CC=3 & CR_D & CR_D_CC { tmp:1 = 0; getCrBit(CR_D, CR_D_CC, tmp); export tmp; } + +RA_OR_ZERO: A is A { export A; } +RA_OR_ZERO: 0 is A=0 { export 0:$(REGISTER_SIZE); } + +RB_OR_ZERO: B is B { export B; } +RB_OR_ZERO: 0 is B=0 { export 0:$(REGISTER_SIZE); } + +RS_OR_ZERO: S is S { export S; } +RS_OR_ZERO: 0 is S=0 { export 0:$(REGISTER_SIZE); } + +@ifdef BIT_64 +MB: mbValue is MBH & MBL [ mbValue=(MBH<<5)|MBL; ] { export *[const]:4 mbValue; } +SH: shValue is SHH & SHL [ shValue=(SHH<<5)|SHL; ] { export *[const]:4 shValue; } + +rotmask: mask is MBL & ME [mask = ((((ME-MBL)>>8) $and 1)*0xffffffffffffffff) $xor (0x7fffffff>>ME) $xor (0xffffffff>>MBL); ] { export *[const]:8 mask; } + +rotmask_SH: masksh, mbValue, shValue is MBL & MBH & SHL & SHH + [ mbValue= (MBH<<5)|MBL; + shValue= (SHH<<5)|SHL; + masksh = ((((shValue-mbValue)>>8) $and 1)*0xffffffffffffffff) $xor ((0x7fffffffffffffff >> shValue) $xor (0xffffffffffffffff >> mbValue)); + ] +{ + local start:4 = mbValue; + local stop:4 = 63-shValue; + mask_tmp:8 = (zext(start > stop) * 0xffffffffffffffff) ^ (0x7fffffffffffffff>>stop) ^ (0xffffffffffffffff>>start); + export *[const]:8 mask_tmp; +} + +rotmask_Z: mask, mbValue is MBL & MBH [mbValue= (MBH<<5)|MBL; mask = ~(0xffffffffffffffff >> (mbValue+1)); ] +{ mask_tmp:8 = ~(0xffffffffffffffff >> (mbValue+1)); export *[const]:8 mask_tmp; } + +@else +rotmask: mask is MBL & ME [ mask = ((((ME-MBL)>>8) $and 1)*0xffffffff) $xor (0x7fffffff>>ME) $xor (0xffffffff>>MBL); ] { export *[const]:4 mask; } +@endif + +DSIZE: "w" is L {} # L is a don't care bit in 32-bit languages although it should always be 0 +@ifdef BIT_64 # L can only be 1 when in 64 bit language +DSIZE: "d" is L=1 {} +@endif + +@ifdef BIT_64 +REG_A: is L=0 & A {tmp:8 = sext(A:4); export tmp; } +REG_A: is L=1 & A {export A; } +REG_B: is L=0 & B {tmp:8 = sext(B:4); export tmp; } +REG_B: is L=1 & B {export B; } +@else # L is a don't care bit in 32-bit languages although it should always be 0 +REG_A: is A { export A; } +REG_B: is B { export B; } +@endif + +@ifdef BIT_64 +UREG_A: is L=0 & A {tmp:8 = zext(A:4); export tmp; } +UREG_A: is L=1 & A {export A; } +UREG_B: is L=0 & B {tmp:8 = zext(B:4); export tmp; } +UREG_B: is L=1 & B {export B; } +@else # L is a don't care bit in 32-bit languages although it should always be 0 +UREG_A: is A { export A; } +UREG_B: is B { export B; } +@endif + +dPlusRaOrZeroAddress: SIMM(RA_OR_ZERO) is SIMM & RA_OR_ZERO { tmp:$(REGISTER_SIZE) = RA_OR_ZERO+SIMM; export tmp; } +dPlusRaAddress: SIMM(A) is SIMM & A {tmp:$(REGISTER_SIZE) = A+SIMM; export tmp; } + +dUI16PlusRAOrZeroAddress: val^"("^RA_OR_ZERO^")" is RA_OR_ZERO & UI_16_s8 [ val = UI_16_s8 << 3; ] { ea:$(REGISTER_SIZE) = RA_OR_ZERO + val; export ea; } + +@ifdef BIT_64 +dsPlusRaAddress: simm_ds(A) is SIMM_DS & A [simm_ds = SIMM_DS << 2;] {tmp:8 = simm_ds + A;export tmp;} +dsPlusRaOrZeroAddress: simm_ds(RA_OR_ZERO) is SIMM_DS & RA_OR_ZERO [simm_ds = SIMM_DS << 2;] {tmp:8 = simm_ds + RA_OR_ZERO;export tmp;} +@endif + + +FPSCR_CRFS: is CRFS=0 {tmp:1 = fp_fx<<3 | fp_fex<<2 | fp_vx<<1 | fp_ox; fp_fx=0; fp_ox=0; export tmp;} +FPSCR_CRFS: is CRFS=1 {tmp:1 = fp_ux<<3 | fp_zx<<2 | fp_xx<<1 | fp_vxsnan; fp_ux=0; fp_zx=0; fp_xx=0; fp_ux=0;export tmp;} +FPSCR_CRFS: is CRFS=2 {tmp:1 = fp_vxisi<<3 | fp_vxidi<<2 | fp_vxzdz<<1 | fp_vximz; fp_vxisi=0; fp_vxidi=0; fp_vxzdz=0; fp_vximz=0; export tmp;} +FPSCR_CRFS: is CRFS=3 {tmp:1 = fp_vxvc<<3 | fp_fr<<2 | fp_fi<<1 | fp_c; fp_vxvc=0; export tmp;} +FPSCR_CRFS: is CRFS=4 {tmp:1 = fp_cc0<<3 | fp_cc1<<2 | fp_cc2<<1 | fp_cc3; export tmp;} +FPSCR_CRFS: is CRFS=5 {tmp:1 = fp_vxsoft<<2 | fp_vxsqrt<<1 | fp_vxcvi; fp_vxsoft=0; fp_vxsqrt=0; fp_vxcvi=0; export tmp;} +FPSCR_CRFS: is CRFS=6 {tmp:1 = fp_ve<<3 | fp_oe <<2 | fp_ue<<1 | fp_ze; export tmp;} +FPSCR_CRFS: is CRFS=7 {tmp:1 = fp_xe<<3 | fp_ni<<2 | fp_rn0<<1 | fp_rn1; export tmp;} + +CRM_CR: cr7 is CRM=1 & cr7 {tmp:4 = zext(cr7);export tmp;} +CRM_CR: cr6 is CRM=2 & cr6 {tmp:4 = zext(cr6) << 4;export tmp;} +CRM_CR: cr5 is CRM=4 & cr5 {tmp:4 = zext(cr5) << 8;export tmp;} +CRM_CR: cr4 is CRM=8 & cr4 {tmp:4 = zext(cr4) << 12;export tmp;} +CRM_CR: cr3 is CRM=16 & cr3 {tmp:4 = zext(cr3) << 16;export tmp;} +CRM_CR: cr2 is CRM=32 & cr2 {tmp:4 = zext(cr2) << 20;export tmp;} +CRM_CR: cr1 is CRM=64 & cr1 {tmp:4 = zext(cr1) << 24;export tmp;} +CRM_CR: cr0 is CRM=128 & cr0 {tmp:4 = zext(cr0) << 28;export tmp;} + + +################################################################ +# Instructions +################################################################ + + +@include "ppc_instructions.sinc" +@include "ppc_embedded.sinc" + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_embedded.sinc b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_embedded.sinc new file mode 100644 index 0000000..b87271d --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_embedded.sinc @@ -0,0 +1,216 @@ +# these are identified as part of the PowerPC Embedded Architecture + +#dcba 0,r0 0x7c 00 05 ec +:dcba RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=758 & BIT_0=0 & RA_OR_ZERO +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + dataCacheBlockAllocate(ea); +} + +#dcbf 0,r0 0x7c 00 00 ac +:dcbf RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=86 & BIT_0=0 & RA_OR_ZERO +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + dataCacheBlockFlush(ea); +} + +#dcbi 0,r0 0x7c 00 03 ac +:dcbi RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=470 & BIT_0=0 & RA_OR_ZERO +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + dataCacheBlockInvalidate(ea); +} + +#dcbst 0,r0 0x7c 00 00 6c +:dcbst RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=54 & BIT_0=0 & RA_OR_ZERO +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + dataCacheBlockStore(ea); +} + +#dcbt 0,r0 0x7c 00 02 2c +:dcbt RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=278 & BIT_0=0 & RA_OR_ZERO +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + dataCacheBlockTouch(ea); +} + +#dcbtst 0,r0 0x7c 00 01 ec +:dcbtst RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=246 & BIT_0=0 & RA_OR_ZERO +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + dataCacheBlockTouchForStore(ea); +} + +#dcbz 0,r0 0x7c 00 07 ec +:dcbz RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=1014 & BIT_0=0 & RA_OR_ZERO +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + dataCacheBlockClearToZero(ea); +} + +@ifndef IS_ISA +# this is equilent to "mbar 0" +#eieio 0x7c 00 06 ac +:eieio is $(NOTVLE) & OP=31 & BITS_21_25=0 & BITS_16_20=0 & BITS_11_15=0 & XOP_1_10=854 & BIT_0=0 +{ + enforceInOrderExecutionIO(); +} +@endif + +#icbi r0,r0 0x7c 00 07 ac +:icbi RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=982 & BIT_0=0 & RA_OR_ZERO +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + instructionCacheBlockInvalidate(ea); +} + +#icbt 0,r0 0x7c 00 02 0c +:icbt BITS_21_24,RA_OR_ZERO,B is OP=31 & BIT_25=0 & BITS_21_24 & RA_OR_ZERO & B & XOP_1_10=22 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + instructionCacheBlockTouch(ea); +} + +#isync 0x4c 00 01 2c +:isync is $(NOTVLE) & OP=19 & BITS_21_25=0 & BITS_16_20=0 & BITS_11_15=0 & XOP_1_10=150 & BIT_0=0 +{ + instructionSynchronize(); +} + +#mfdcr r0,DCRN 0x7c 00 02 86 +:mfdcr D, DCRN is OP=31 & D & DCRN & XOP_1_10=323 & BIT_0=0 +{ + D = DCRN; +} + +#mfmsr r0 0x7c 00 00 a6 +:mfmsr D is OP=31 & D & BITS_11_20=0 & XOP_1_10=83 & BIT_0=0 +{ + D = MSR; +} + +#mfspr r0 0x7c 00 02 a6 +:mfspr D,SPRVAL is OP=31 & D & SPRVAL & XOP_1_10=339 & BIT_0=0 +{ + D = SPRVAL; +} + +#mftb r0,TBLr 0x7c 0c 42 e6 +:mftb D,TBLr is $(NOTVLE) & OP=31 & D & TBR=392 & TBLr & XOP_1_10=371 & BIT_0=0 +{ + D = TBLr; +} +#mftb r0,TBUr 0x7c 0d 42 e6 +:mftb D,TBUr is $(NOTVLE) & OP=31 & D & TBR=424 & TBUr & XOP_1_10=371 & BIT_0=0 +{ + D = TBUr; +} + +#mtdcr DCRN,r0 0x7c 00 03 86 +:mtdcr DCRN, D is OP=31 & D & DCRN & XOP_1_10=451 & BIT_0=0 +{ + DCRN = D; +} + +# mtmsr varies from processor to processor. This version is consistent with PowerISA v2.07B +#mtmsr r0,0 0x7c 00 01 24 +:mtmsr S,0 is OP=31 & S & BITS_17_20=0 & MSR_L=0 & BITS_11_15=0 & XOP_1_10=146 & BIT_0=0 +{ + + bit59:$(REGISTER_SIZE) = (S >> 4) & 1; #bit 59 + bit58:$(REGISTER_SIZE) = (S >> 5) & 1; #bit 58 + bit49:$(REGISTER_SIZE) = (S >> 14) & 1; #bit 49 + bit48:$(REGISTER_SIZE) = (S >> 15) & 1; #bit 48 + + local mask:$(REGISTER_SIZE) = 0xffff6fcf; # preserves bits 32:47 49:50 52:57 60:62 + local tmp:$(REGISTER_SIZE) = S & mask; # 1111 1111 1111 1111 0110 1111 1100 1111 + + tmp = tmp | ((bit48 | bit49) << 15); # MSR 48 <- (RS) 48 | (RS) 49 + tmp = tmp | ((bit58 | bit49) << 5); # MSR 58 <- (RS) 58 | (RS) 49 + tmp = tmp | ((bit59 | bit49) << 4); # MSR 59 <- (RS) 59 | (RS) 49 + MSR = (MSR & ~mask) | tmp; +} + +#mtmsr r0,1 0x7c 01 01 24 +:mtmsr S,1 is OP=31 & S & BITS_17_20=0 & MSR_L=1 & BITS_11_15=0 & XOP_1_10=146 & BIT_0=0 +{ + mask:$(REGISTER_SIZE) = 0x8002; #preserves bits 48 and 62 + MSR = (MSR & ~mask) | (S & mask); +} + + +#mtspr spr000,r0 0x7c 00 02 a6 +:mtspr SPRVAL,S is OP=31 & SPRVAL & S & XOP_1_10=467 & BIT_0=0 +{ + SPRVAL = S; +} + +:mtspr SPRVAL,S is OP=31 & BITS_11_20=0x100 & BITS_21_25=0 & SPRVAL & S & XOP_1_10=467 & BIT_0=0 + [ linkreg=1; globalset(inst_next,linkreg); ] +{ + SPRVAL = S; +} + +:mtspr SPRVAL,S is linkreg=1 & OP=31 & BITS_11_20=0x100 & BITS_21_25=0 & SPRVAL & S & XOP_1_10=467 & BIT_0=0 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + SPRVAL = S; +} + +:rfci is $(NOTVLE) & OP=19 & BITS_21_25=0 & BITS_16_20=0 & BITS_11_15=0 & XOP_1_10=51 & BIT_0=0 +{ + MSR = returnFromCriticalInterrupt(MSR, CSRR1); + local ra = CSRR0; + return[ra]; + +} + +#rfi 0x4c 00 00 64 +:rfi is $(NOTVLE) & OP=19 & BITS_11_25=0 & XOP_1_10=50 & BIT_0=0 +{ + MSR = returnFromInterrupt(MSR, SRR1); + local ra = SRR0; + return[ra]; +} + + +#tlbre 0x7c 00 07 64 +:tlbre is OP=31 & XOP_1_10=946 +{ + TLBRead(); +} + +#tlbsx r0,r0,r0 0x7c 00 07 24 +:tlbsx D,RA_OR_ZERO,B is OP=31 & D & B & XOP_1_10=914 & RA_OR_ZERO & Rc=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + D = TLBSearchIndexed(D,ea); +} + +#tlbsx. r0,r0,r0 0x7c 00 07 25 +:tlbsx. D,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & D & B & XOP_1_10=914 & RA_OR_ZERO & Rc=1 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + D = TLBSearchIndexed(D,ea); + cr0flags(D); +} + +#tlbwe 0x7c 00 07 a4 +:tlbwe D,A,B_BITS is OP=31 & D & A & B_BITS & XOP_1_10=978 +{ + D = TLBWrite(D,A,B_BITS:1); +} + + +#wrtee r0 0x7c 00 01 06 +:wrtee S is OP=31 & S & XOP_1_10=131 +{ + WriteExternalEnable(S); +} + +#wrteei 0 0x7c 00 01 46 +:wrteei BIT_15 is OP=31 & BIT_15 & XOP_1_10=163 +{ + WriteExternalEnableImmediate(BIT_15:1); +} diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_instructions.sinc b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_instructions.sinc new file mode 100644 index 0000000..b9ca56c --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_instructions.sinc @@ -0,0 +1,4534 @@ +#=========================================================== +# ADD +#=========================================================== + +#add r1,r2,r3 0x7c 22 1a 14 +:add D,A,B is OP=31 & D & A & B & OE=0 & XOP_1_9=266 & Rc=0 +{ + D = A + B; +} + +#add. r1,r2,r3 0x7c 22 1a 15 +:add. D,A,B is OP=31 & D & A & B & OE=0 & XOP_1_9=266 & Rc=1 +{ + D = A + B; + cr0flags(D); +} + +#addo r1,r2,r3 0x7c 22 1e 14 +:addo D,A,B is OP=31 & D & A & B & OE=1 & XOP_1_9=266 & Rc=0 +{ + addOverflow(A,B); + D = A + B; +} + +#addo. r1,r2,r3 0x7c 22 1e 15 +:addo. D,A,B is OP=31 & D & A & B & OE=1 & XOP_1_9=266 & Rc=1 +{ + addOverflow(A,B); + D = A + B; + cr0flags(D); +} + +#addc r1,r2,r3 0x7c 22 18 14 +:addc D,A,B is OP=31 & D & A & B & OE=0 & XOP_1_9=10 & Rc=0 +{ + xer_ca = carry(A,B); + D = A + B; +} + +#addc. r1,r2,r3 0x7c 22 18 15 +:addc. D,A,B is OP=31 & D & A & B & OE=0 & XOP_1_9=10 & Rc=1 +{ + xer_ca = carry(A,B); + D = A + B; + cr0flags(D); +} + +#addco r1,r2,r3 0x7c 22 1c 14 +:addco D,A,B is OP=31 & D & A & B & OE=1 & XOP_1_9=10 & Rc=0 +{ + xer_ca = carry(A,B); + addOverflow( A, B ); + D = A + B; +} + +#addco. r1,r2,r3 0x7c 22 1c 15 +:addco. D,A,B is OP=31 & D & A & B & OE=1 & XOP_1_9=10 & Rc=1 +{ + xer_ca = carry(A,B); + addOverflow( A, B ); + D = A + B; + cr0flags(D); +} + +#adde r1,r2,r3 0x7c 22 19 14 +:adde D,A,B is OP=31 & D & A & B & OE=0 & XOP_1_9=138 & Rc=0 +{ + zextCarry:$(REGISTER_SIZE) = zext(xer_ca); + addExtendedCarry(A,B); + D=A + B + zextCarry; +} + +#adde. r1,r2,r3 0x7c 22 19 15 +:adde. D,A,B is OP=31 & D & A & B & OE=0 & XOP_1_9=138 & Rc=1 +{ + zextCarry:$(REGISTER_SIZE) = zext(xer_ca); + addExtendedCarry(A,B); + D=A + B + zextCarry; + cr0flags(D); +} + +#addeo r1,r2,r3 0x7c 22 1d 14 +:addeo D,A,B is OP=31 & D & A & B & OE=1 & XOP_1_9=138 & Rc=0 +{ + zextCarry:$(REGISTER_SIZE) = zext(xer_ca); + addExtendedOverflow(A,B); + addExtendedCarry(A,B); + D=A + B + zextCarry; +} + +#addeo. r1,r2,r3 0x7c 22 1d 15 +:addeo. D,A,B is OP=31 & D & A & B & OE=1 & XOP_1_9=138 & Rc=1 +{ + zextCarry:$(REGISTER_SIZE) = zext(xer_ca); + addExtendedOverflow(A,B); + addExtendedCarry(A,B); + D=A + B + zextCarry; + cr0flags(D); +} + +#addi r0,0x7fff 0x38 00 7f ff +#addi r0,1 0x38 01 00 01 +:addi D,A,SIMM is $(NOTVLE) & OP=14 & D & A & SIMM_SIGN=0 & SIMM +{ + D = A + SIMM; +} + +#li r0,1 0x38 00 00 01 # addi simplified mnemonic +:li D,SIMM is $(NOTVLE) & OP=14 & D & A=0 & SIMM_SIGN=1 & SIMM +{ + D = SIMM; +} + +#li r0,-0x1 0x38 00 FF FF # addi simplified mnemonic +:li D,SIMM is $(NOTVLE) & OP=14 & D & A=0 & SIMM_SIGN=0 & SIMM +{ + D = SIMM; +} + +#subi r0,r1,1 0x38 01 FF FF # addi simplified mnemonic +:subi D,A,tmp is $(NOTVLE) & OP=14 & D & A & SIMM_SIGN=1 & SIMM [ tmp = -SIMM; ] +{ + D = A + SIMM; +} + +#addic r0,r0,2 0x30 00 00 02 +:addic D,A,SIMM is $(NOTVLE) & OP=12 & D & A & SIMM_SIGN=0 & SIMM +{ + xer_ca=carry(A,SIMM); + D = A + SIMM; +} + +#subic r0,r0,2 0x30 00 FF FE # addi simplified mnemonic +:subic D,A,tmp is $(NOTVLE) & OP=12 & D & A & SIMM_SIGN=1 & SIMM [ tmp = -SIMM; ] +{ + xer_ca=carry(A,SIMM); + D = A + SIMM; +} + +#addic. r0,r0,5 0x34 00 00 05 +:addic. D,A,SIMM is $(NOTVLE) & OP=13 & D & A & SIMM_SIGN=0 & SIMM +{ + xer_ca = carry(A,SIMM); + D = A + SIMM; + cr0flags( D ); +} + +#subic. r0,r0,1 0x34 00 FF FF # addic. simplified mnemonic +:subic. D,A,tmp is $(NOTVLE) & OP=13 & D & A & SIMM_SIGN=1 & SIMM [ tmp = -SIMM; ] +{ + xer_ca=carry(A,SIMM); + D = A + SIMM; + cr0flags( D ); +} + +#addis r0,r1,1 0x3c 01 00 01 +:addis D,A,SIMM is $(NOTVLE) & OP=15 & D & A & SIMM_SIGN=0 & SIMM +{ + D = A + (SIMM:$(REGISTER_SIZE) << 16); +} + +#lis r0,1 0x3c 00 00 01 # addis simplified mnemonic +:lis D,SIMM is $(NOTVLE) & OP=15 & D & A=0 & SIMM_SIGN=1 & SIMM +{ + D = SIMM:$(REGISTER_SIZE) << 16; +} + +#lis r0,-1 0x3c 00 FF FF # addis simplified mnemonic +:lis D,SIMM is $(NOTVLE) & OP=15 & D & A=0 & SIMM_SIGN=0 & SIMM +{ + D = SIMM:$(REGISTER_SIZE) << 16; +} + +#subis r0,r1,1 0x3c 01 FF FF # addis simplified mnemonic +:subis D,A,tmp is $(NOTVLE) & OP=15 & D & A & SIMM_SIGN=1 & SIMM [ tmp = -SIMM; ] +{ + D = A + (SIMM:$(REGISTER_SIZE) << 16); +} + +#addme r0,r0 0x7c 00 01 D4 +:addme D,A is OP=31 & D & A & BITS_11_15=0 & OE=0 & XOP_1_9=234 & Rc=0 +{ + local zextCarry:$(REGISTER_SIZE) = zext(xer_ca); + local BVal:$(REGISTER_SIZE) = ~(0); + addExtendedCarry(A,BVal); + D=A + BVal + zextCarry; +} + +#addme. r0,r0 0x7c 00 01 D5 +:addme. D,A is OP=31 & D & A & BITS_11_15=0 & OE=0 & XOP_1_9=234 & Rc=1 +{ + local zextCarry:$(REGISTER_SIZE) = zext(xer_ca); + local BVal:$(REGISTER_SIZE) = ~(0); + addExtendedCarry(A,BVal); + D=A + BVal + zextCarry; + cr0flags(D); +} + +#addmeo r0,r0 0x7C 00 05 D4 +:addmeo D,A is OP=31 & D & A & BITS_11_15=0 & OE=1 & XOP_1_9=234 & Rc=0 +{ + local zextCarry:$(REGISTER_SIZE) = zext(xer_ca); + local BVal:$(REGISTER_SIZE) = ~(0); + addExtendedOverflow(A,BVal); + addExtendedCarry(A,BVal); + D=A + BVal + zextCarry; +} + +#addmeo. r0,r0 0x7C 00 05 D5 +:addmeo. D,A is OP=31 & D & A & BITS_11_15=0 & OE=1 & XOP_1_9=234 & Rc=1 +{ + local zextCarry:$(REGISTER_SIZE) = zext(xer_ca); + local BVal:$(REGISTER_SIZE) = ~(0); + addExtendedOverflow(A,BVal); + addExtendedCarry(A,BVal); + D=A + BVal + zextCarry; + cr0flags(D); +} + +#addze r0,r0 0x7C 00 01 94 +:addze D,A is OP=31 & D & A & BITS_11_15=0 & OE=0 & XOP_1_9=202 & Rc=0 +{ + zextedCarry:$(REGISTER_SIZE) = zext( xer_ca ); + xer_ca = carry(A,zextedCarry); + D = A + zextedCarry; +} + +#addze. r0,r0 0x7C 00 01 95 +:addze. D,A is OP=31 & D & A & BITS_11_15=0 & OE=0 & XOP_1_9=202 & Rc=1 +{ + zextedCarry:$(REGISTER_SIZE) = zext( xer_ca ); + xer_ca=carry(A,zextedCarry); + D = A + zextedCarry; + cr0flags( D ); +} + +#addzeo r0,r0 0x7C 00 05 94 +:addzeo D,A is OP=31 & D & A & BITS_11_15=0 & OE=1 & XOP_1_9=202 & Rc=0 +{ + zextedCarry:$(REGISTER_SIZE) = zext( xer_ca ); + xer_ca=carry(A,zextedCarry); + addOverflow(A,zextedCarry); + D = A + zextedCarry; +} + +#addzeo. r0,r0 0x7C 00 05 95 +:addzeo. D,A is OP=31 & D & A & BITS_11_15=0 & OE=1 & XOP_1_9=202 & Rc=1 +{ + zextedCarry:$(REGISTER_SIZE) = zext( xer_ca ); + xer_ca=carry(A,zextedCarry); + addOverflow(A,zextedCarry); + D = A + zextedCarry; + cr0flags( D ); +} + +#=========================================================== +# AND +#=========================================================== + +#and r0,r0,r0 0x7C 00 00 38 +:and A,S,B is OP=31 & S & A & B & XOP_1_10=28 & Rc=0 +{ + A = S & B; +} + +#and. r0,r0,r0 0x7C 00 00 39 +:and. A,S,B is OP=31 & S & A & B & XOP_1_10=28 & Rc=1 +{ + A = S & B; + cr0flags( A ); +} + +#andc r0,r0,r0 0x7C 00 00 78 +:andc A,S,B is OP=31 & S & A & B & XOP_1_10=60 & Rc=0 +{ + A = S & ~B; +} + +#andc. r0,r0,r0 0x7C 00 00 79 +:andc. A,S,B is OP=31 & S & A & B & XOP_1_10=60 & Rc=1 +{ + A = S & ~B; + cr0flags( A ); +} + +#andi. r0,r0,0xffff 0x70 00 ff ff +:andi. A,S,UIMM is $(NOTVLE) & OP=28 & S & A & UIMM +{ + A = S & UIMM:$(REGISTER_SIZE); + cr0flags( A ); +} + +#andis. r0,r0,1 0x74 00 00 01 +:andis. A,S,UIMM is $(NOTVLE) & OP=29 & A & S & UIMM +{ + A = S & (UIMM:$(REGISTER_SIZE) << 16); + cr0flags( A ); +} + +#=========================================================== +# Branch (op=18) +#=========================================================== + +#b 1008 0x48 00 00 08 (assuming a starting address of 1000) +#ba LAB_00000158 0x48 00 01 5a +:b^REL_ABS addressLI is $(NOTVLE) & OP=18 & REL_ABS & addressLI & LK=0 +{ + goto addressLI; +} + +:b^REL_ABS addressLI is linkreg=1 & OP=18 & REL_ABS & addressLI & LK=0 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + # don't do this anymore, detect another way + # call addressLI; + # return [LR]; + goto addressLI; +} + +#bl 0x48 00 00 09 +#bla 0x48 00 10 0f +:bl^REL_ABS addressLI is $(NOTVLE) & OP=18 & REL_ABS & addressLI & LK=1 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + r2Save = r2; # Save r2 (needed for branch to ppc64 call stub) + LR = inst_next; + call addressLI; +} + +# special case when branch is to fall-through instruction, just loading the link register +#bl 0x48 00 00 05 +:bl addressLI is $(NOTVLE) & OP=18 & REL_ABS & AA=0 & addressLI & LK=1 & LI=1 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + LR = inst_next; + goto addressLI; +} + +#=========================================================== +# Branch Conditional (op=16) +#=========================================================== + +#b sameAddr 0x42 80 00 00 +#ba LAB_0000 0x42 80 00 02 +:b^REL_ABS addressBD is $(NOTVLE) & OP=16 & addressBD & REL_ABS & BO_0=1 & BO_2=1 & LK=0 +{ + goto addressBD; +} + +:b^REL_ABS addressBD is linkreg=1 & OP=16 & addressBD & REL_ABS & BO_0=1 & BO_2=1 & LK=0 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + # don't do this anymore, detect another way + # call addressBD; + # return [LR]; + goto addressBD; +} + +#bl LAB_0000 0x42 80 00 01 +#bla LAB_0000 0x42 80 00 03 +:bl^REL_ABS addressBD is $(NOTVLE) & OP=16 & addressBD & REL_ABS & BO_0=1 & BO_2=1 & LK=1 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + LR = inst_next; + call addressBD; +} + +# special case when branch is to fall-through instruction, just loading the link register +#bl (Load LR) +:bl addressBD is $(NOTVLE) & OP=16 & addressBD & REL_ABS & BO_0=1 & BO_2=1 & BD=1 & LK=1 +{ + LR = inst_next; + goto addressBD; +} + + + +#blt LAB_0000 0x41 80 00 00 +:b^CC^REL_ABS addressBD is $(NOTVLE) & OP=16 & CC & addressBD & BO_0=0 & BO_2=1 & BI_CR= 0 & + REL_ABS & LK=0 + [ linkreg=0; globalset(inst_start,linkreg); ] # affects both flows, but not at this instruction +{ + if (CC) goto addressBD; +} +## do a special linkreg setting only if linkreg is set, since this happens all over the code +:b^CC^REL_ABS addressBD is linkreg=1 & OP=16 & CC & addressBD & BO_0=0 & BO_2=1 & BI_CR= 0 & + REL_ABS & LK=0 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (CC) goto addressBD; +} + +#bltl LAB_0000 0x41 80 00 01 +:b^CC^"l"^REL_ABS addressBD is $(NOTVLE) & OP=16 & CC & addressBD & BO_0=0 & BO_2=1 & BI_CR= 0 & + REL_ABS & LK=1 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!CC) goto inst_next; + LR = inst_next; + call addressBD; +} + +#bne cr2,LAB_xxxx 0x40 8a 00 00 +:b^CC^REL_ABS BI_CR,addressBD is $(NOTVLE) & OP=16 & CC & BI_CR & addressBD & BO_0=0 & BO_2=1 & + REL_ABS & LK=0 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (CC) goto addressBD; +} + +#bnel cr2,LAB_xxxx 0x40 8a 00 01 +:b^CC^"l"^REL_ABS BI_CR,addressBD is $(NOTVLE) & OP=16 & CC & BI_CR & addressBD & BO_0=0 & BO_2=1 & + REL_ABS & LK=1 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!CC) goto inst_next; + LR = inst_next; + call addressBD; +} + +#bdnz LAB_0000 0x42 00 00 00 +:bd^CTR_DEC^REL_ABS addressBD is $(NOTVLE) & OP=16 & CTR_DEC & REL_ABS & addressBD & BO_0=1 & BO_2=0 & LK=0 +{ + if (CTR_DEC) goto addressBD; +} + +#bdnzl FUN_0xxx 0x42 00 00 01 +#bdzla FUN_0000 0x42 40 00 03 +:bd^CTR_DEC^"l"^REL_ABS addressBD is $(NOTVLE) & OP=16 & CTR_DEC & REL_ABS & addressBD & BO_0=1 & BO_2=0 & LK=1 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!CTR_DEC) goto inst_next; + LR = inst_next; + call addressBD; +} + +#bdnzf lt,LAB_0000 0x40 00 00 00 +#bdnzf 4*cr2+eq,LAB_0000 0x40 0a 00 00 +:bd^CTR_DEC^CC_TF^REL_ABS CC_OP,addressBD is $(NOTVLE) & OP=16 & CC_TF & REL_ABS & CTR_DEC & CC_OP & addressBD & BO_0=0 & BO_2=0 & LK=0 +{ + if (CTR_DEC && CC_OP) goto addressBD; +} + +#bdzfl lt,FUN_0000 0x40 00 00 01 +#bdnzfl 4*cr2+eq,FUN_0000 0x40 0a 00 01 +:bd^CTR_DEC^CC_TF^"l"^REL_ABS CC_OP,addressBD is $(NOTVLE) & OP=16 & CC_TF & CTR_DEC & REL_ABS & CC_OP & addressBD & BO_0=0 & BO_2=0 & LK=1 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!(CTR_DEC && CC_OP)) goto inst_next; + LR = inst_next; + call addressBD; +} + + +#=========================================================== +# Branch Conditional CTR(op=19, xop=528) +#=========================================================== + + +#bctr 0x4E 80 04 20 +:bctr is $(NOTVLE) & OP=19 & BO_0=1 & BO_2=1 & LK=0 & BITS_13_15=0 & BH=0 & XOP_1_10=528 +{ + goto [CTR]; +} + +:bctr is $(NOTVLE) & linkreg=1 & OP=19 & BO_0=1 & BO_2=1 & LK=0 & BITS_13_15=0 & BH=0 & XOP_1_10=528 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + # don't do this anymore, detect another way + # call [CTR]; + # return [LR]; + goto [CTR]; +} + +:bctr BH is $(NOTVLE) & OP=19 & BO_0=1 & BO_2=1 & LK=0 & BITS_13_15=0 & BH & XOP_1_10=528 +{ + goto [CTR]; +} + +#bctrl 0x4e 80 04 21 +:bctrl is $(NOTVLE) & OP=19 & BO_0=1 & BO_2=1 & LK=1 & BITS_13_15=0 & BH=0 & XOP_1_10=528 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + LR = inst_next; + call [CTR]; +} +:bctrl BH is $(NOTVLE) & OP=19 & BO_0=1 & BO_2=1 & LK=1 & BITS_13_15=0 & BH & XOP_1_10=528 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + LR = inst_next; + call [CTR]; +} + +#bgectr 0x4c 80 04 20 +:b^CC^"ctr" is $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR= 0 & BH=0 & LK=0 & BITS_13_15=0 & XOP_1_10=528 +{ + if (!CC) goto inst_next; + goto [CTR]; +} +:b^CC^"ctr" BH is $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR= 0 & BH & BH_BITS!=0 & LK=0 & BITS_13_15=0 & XOP_1_10=528 +{ + if (!CC) goto inst_next; + goto [CTR]; +} + +#bgectrl 0x4c 80 04 21 +:b^CC^"ctrl" is $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR= 0 & BH=0 & LK=1 & BITS_13_15=0 & XOP_1_10=528 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!CC) goto inst_next; + LR = inst_next; + call [CTR]; +} +:b^CC^"ctrl" BH is $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR= 0 & BH & BH_BITS!=0 & LK=1 & BITS_13_15=0 & XOP_1_10=528 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!CC) goto inst_next; + LR = inst_next; + call [CTR]; +} + +#bgectr cr3 0x4c 8c 04 20 +:b^CC^"ctr" BI_CR is $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH=0 & LK=0 & BITS_13_15=0 & XOP_1_10=528 +{ + if (!CC) goto inst_next; + goto [CTR]; +} + +#bnectr cr2,#0x3 0x4c 8c 1c 20 +:b^CC^"ctr" BI_CR,BH is $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH & LK=0 & BITS_13_15=0 & XOP_1_10=528 +{ + if (!CC) goto inst_next; + goto [CTR]; +} + +#bgectrl cr2,LAB_xxxx 0x4c 8c 04 21 +:b^CC^"ctrl" BI_CR is $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH=0 & LK=1 & BITS_13_15=0 & XOP_1_10=528 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!CC) goto inst_next; + LR = inst_next; + call [CTR]; +} + +#bnectr cr2,#0x3 0x4c 8c 1c 21 +:b^CC^"ctrl" BI_CR,BH is $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH & LK=1 & BITS_13_15=0 & XOP_1_10=528 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!CC) goto inst_next; + LR = inst_next; + call [CTR]; +} + +#=========================================================== +# Branch Conditional to Link Register (op=19, XOP=16) +#=========================================================== + +#bclr 0x4E 80 00 20 +:blr is $(NOTVLE) & OP=19 & BO_0=1 & BO_2=1 & LK=0 & BITS_13_15=0 & BH=0 & XOP_1_10=16 +{ + return [LR]; +} +:blr BH is $(NOTVLE) & OP=19 & BO_0=1 & BO_2=1 & LK=0 & BITS_13_15=0 & BH & XOP_1_10=16 +{ + goto [LR]; +} + +#blrl 0x4e 80 00 21 +:blrl is $(NOTVLE) & OP=19 & BO_0=1 & BO_2=1 & LK=1 & BITS_13_15=0 & BH=0 & XOP_1_10=16 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + tmp:$(REGISTER_SIZE) = LR; + LR = inst_next; + call [tmp]; +} +:blrl BH is $(NOTVLE) & OP=19 & BO_0=1 & BO_2=1 & LK=1 & BITS_13_15=0 & BH & XOP_1_10=16 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + tmp:$(REGISTER_SIZE) = LR; + LR = inst_next; + call [tmp]; +} + +#bgelr 0x4c 80 00 20 +:b^CC^"lr" is $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR=0 & BH=0 & LK=0 & BITS_13_15=0 & XOP_1_10=16 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!CC) goto inst_next; + return [LR]; +} +:b^CC^"lr" BH is $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR=0 & BH & BH_BITS!=0 & LK=0 & BITS_13_15=0 & XOP_1_10=16 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!CC) goto inst_next; + goto [LR]; +} + +#bgelrl 0x4c 80 00 21 +:b^CC^"lrl" is $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR=0 & BH=0 & LK=1 & BITS_13_15=0 & XOP_1_10=16 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!CC) goto inst_next; + tmp:$(REGISTER_SIZE) = LR; + LR = inst_next; + call [tmp]; +} +:b^CC^"lrl" BH is $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR=0 & BH & BH_BITS!=0 & LK=1 & BITS_13_15=0 & XOP_1_10=16 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!CC) goto inst_next; + tmp:$(REGISTER_SIZE) = LR; + LR = inst_next; + call [tmp]; +} + +#bgelr cr2 0x4c 88 00 20 +:b^CC^"lr" BI_CR is $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH=0 & LK=0 & BITS_13_15=0 & XOP_1_10=16 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!CC) goto inst_next; + return [LR]; +} + +#bnelr cr2,#0x3 0x4c 8c 18 20 +:b^CC^"lr" BI_CR,BH is $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH & BH_BITS!=0 & LK=0 & BITS_13_15=0 & XOP_1_10=16 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!CC) goto inst_next; + goto [LR]; +} + +#bgelrl cr3 0x4c 8c 00 21 +:b^CC^"lrl" BI_CR is $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH=0 & LK=1 & BITS_13_15=0 & XOP_1_10=16 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!CC) goto inst_next; + tmp:$(REGISTER_SIZE) = LR; + LR = inst_next; + call [tmp]; +} + +#bnelr cr2,#0x3 0x4c 8c 18 21 +:b^CC^"lrl" BI_CR,BH is $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH & LK=1 & BITS_13_15=0 & XOP_1_10=16 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!CC) goto inst_next; + tmp:$(REGISTER_SIZE) = LR; + LR = inst_next; + call [tmp]; +} + +###### + +#bdnzlr 0x4e 00 00 20 +:bd^CTR_DEC^"lr" is $(NOTVLE) & OP=19 & BH=0 & CTR_DEC & BO_0=1 & BO_2=0 & LK=0 & BITS_13_15=0 & XOP_1_10=16 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!CTR_DEC) goto inst_next; + goto [LR]; +} +:bd^CTR_DEC^"lr" BH is $(NOTVLE) & OP=19 & BH & CTR_DEC & BO_0=1 & BO_2=0 & LK=0 & BITS_13_15=0 & XOP_1_10=16 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!CTR_DEC) goto inst_next; + goto [LR]; +} + +#bdnzlrl 0x4e 00 00 21 +:bd^CTR_DEC^"lrl" is $(NOTVLE) & OP=19 & CTR_DEC & BH=0 & BO_0=1 & BO_2=0 & LK=1 & BITS_13_15=0 & XOP_1_10=16 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!CTR_DEC) goto inst_next; + tmp:$(REGISTER_SIZE) = LR; + LR = inst_next; + call [tmp]; +} +:bd^CTR_DEC^"lrl" BH is $(NOTVLE) & OP=19 & CTR_DEC & BH & BO_0=1 & BO_2=0 & LK=1 & BITS_13_15=0 & XOP_1_10=16 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!CTR_DEC) goto inst_next; + tmp:$(REGISTER_SIZE) = LR; + LR = inst_next; + call [tmp]; +} + +#bdnzflr lt 0x4c 00 00 20 +#bdnzflr 4*cr2+eq 0x4c 0a 00 20 +:bd^CTR_DEC^CC_TF^"lr" CC_OP is $(NOTVLE) & OP=19 & CC_TF & CTR_DEC & CC_OP & BO_0=0 & BO_2=0 & BH=0 & LK=0 & BITS_13_15=0 & XOP_1_10=16 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!(CTR_DEC && CC_OP)) goto inst_next; + goto [LR]; +} + +#bdnzflr ge 0x4c 00 18 20 +#bdnzflr 4*cr2+eq 0x4c 0a 18 20 +:bd^CTR_DEC^CC_TF^"lr" CC_OP,BH is $(NOTVLE) & OP=19 & CC_TF & CTR_DEC & CC_OP & BO_0=0 & BO_2=0 & BH & LK=0 & BITS_13_15=0 & XOP_1_10=16 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!(CTR_DEC && CC_OP)) goto inst_next; + goto [LR]; +} + +#bdzflrl lt 0x4c 00 00 21 +#bdnzflrl 4*cr2+eq 0x4c 0a 00 21 +:bd^CTR_DEC^CC_TF^"lrl" CC_OP is $(NOTVLE) & OP=19 & CC_TF & CTR_DEC & CC_OP & BH=0 & BO_0=0 & BO_2=0 & LK=1 & BITS_13_15=0 & XOP_1_10=16 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!(CTR_DEC && CC_OP)) goto inst_next; + tmp:$(REGISTER_SIZE) = LR; + LR = inst_next; + call [tmp]; +} + +#bdzflrl lt 0x4c 00 18 21 +#bdnzflrl 4*cr2+eq 0x4c 0a 18 21 +:bd^CTR_DEC^CC_TF^"lrl" CC_OP,BH is $(NOTVLE) & OP=19 & CC_TF & CTR_DEC & CC_OP & BH & BO_0=0 & BO_2=0 & LK=1 & BITS_13_15=0 & XOP_1_10=16 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!(CTR_DEC && CC_OP)) goto inst_next; + tmp:$(REGISTER_SIZE) = LR; + LR = inst_next; + call [tmp]; +} + + +#=========================================================== +# CMP +#=========================================================== + +#cmpw r0,r1 0x7c 00 08 00 +#cmpd r0,r1 0x7c 20 08 00 (64 bit mode) +:cmp^DSIZE A,B is OP=31 & CRFD=0 & BIT_22=0 & DSIZE & A & B & REG_A & REG_B & XOP_1_10=0 & BIT_0=0 +{ + tmpA:$(REGISTER_SIZE) = REG_A; + tmpB:$(REGISTER_SIZE) = REG_B; + cr0 = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1); + +} + +#cmpw cr2,r0,r1 0x7d 00 08 00 +#cmpd cr2,r0,r1 0x7d 20 08 00 (64 bit mode) +:cmp^DSIZE CRFD,A,B is OP=31 & CRFD & BIT_22=0 & DSIZE & A & B & REG_A & REG_B & XOP_1_10=0 & BIT_0=0 +{ + tmpA:$(REGISTER_SIZE) = REG_A; + tmpB:$(REGISTER_SIZE) = REG_B; + CRFD = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1); +} + +############################### +#cmpwi r0,0x00 0x2c 00 00 00 +#cmpdi r0,0x00 0x2c 20 00 00 (64 bit mode) +:cmp^DSIZE^"i" A,SIMM is $(NOTVLE) & OP=11 & CRFD=0 & BIT_22=0 & DSIZE & A & REG_A & SIMM +{ + tmpA:$(REGISTER_SIZE) = REG_A; + tmpB:$(REGISTER_SIZE) = SIMM; + cr0 = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1); + +} + +#cmpwi cr2,r0,0x00 0x2d 00 00 00 +#cmpwi cr2,r0,0x00 0x2d 20 00 00 (64 bit mode) +:cmp^DSIZE^"i" CRFD,A,SIMM is $(NOTVLE) & OP=11 & CRFD & BIT_22=0 & DSIZE & A & B & REG_A & SIMM +{ + tmpA:$(REGISTER_SIZE) = REG_A; + tmpB:$(REGISTER_SIZE) = SIMM; + CRFD = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1); +} + +############################ +#cmplw r0,r1 0x7c 00 08 40 +#cmpld r0,r1 0x7c 20 08 40 (64 bit mode) +:cmpl^DSIZE A,B is OP=31 & CRFD=0 & BIT_22=0 & DSIZE & A & B & UREG_A & UREG_B & XOP_1_10=32 & BIT_0=0 +{ + tmpA:$(REGISTER_SIZE) = UREG_A; + tmpB:$(REGISTER_SIZE) = UREG_B; + cr0 = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1); + +} + +#cmplw cr2,r0,r1 0x7d 00 08 40 +#cmplw cr2,r0,r1 0x7d 20 08 40 (64 bit mode) +:cmpl^DSIZE CRFD,A,B is OP=31 & CRFD & BIT_22=0 & DSIZE & A & B & UREG_A & UREG_B & XOP_1_10=32 & BIT_0=0 +{ + tmpA:$(REGISTER_SIZE) = UREG_A; + tmpB:$(REGISTER_SIZE) = UREG_B; + CRFD = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1); +} + +############################### +#cmplwi r0,0x00 0x28 00 00 00 +#cmpldi r0,0x00 0x28 20 00 00 (64 bit mode) +:cmpl^DSIZE^"i" A,UIMM is $(NOTVLE) & OP=10 & CRFD=0 & BIT_22=0 & DSIZE & A & UREG_A & UIMM +{ + tmpA:$(REGISTER_SIZE) = UREG_A; + tmpB:$(REGISTER_SIZE) = UIMM; + cr0 = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1); + +} + +#cmplwi cr2,r0,0x00 0x29 00 00 00 +#cmplwi cr2,r0,0x00 0x29 20 00 00 (64 bit mode) +:cmpl^DSIZE^"i" CRFD,A,UIMM is $(NOTVLE) & OP=10 & CRFD & BIT_22=0 & DSIZE & A & B & UREG_A & UIMM +{ + tmpA:$(REGISTER_SIZE) = UREG_A; + tmpB:$(REGISTER_SIZE) = UIMM; + CRFD = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1); +} +#=========================================================== +# CNTLZx +#=========================================================== + +@ifdef BIT_64 +#cntlzd r0,r0 0x7c 00 00 74 +:cntlzd A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=58 & Rc=0 +{ + A = lzcount(S); +} + +#cntlzd. r0,r0 0x7c 00 00 75 +:cntlzd. A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=58 & Rc=1 +{ + A = lzcount(S); + cr0flags(A); +} +@endif + +#cntlzw r0,r0 0x7c 00 00 34 +:cntlzw A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=26 & Rc=0 +{ + A = lzcount(S:4); +} + +#cntlzw. r0,r0 0x7c 00 00 35 +:cntlzw. A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=26 & Rc=1 +{ + A = lzcount(S:4); + cr0flags(A); +} +#=========================================================== +# CRxxx +#=========================================================== +#crand lt,lt,lt 0x4c 00 02 02 +#crand 4*cr1+lt,4*cr2+gt,4*cr3+eq 0x4c 89 72 02 +:crand CC_D_OP,CC_OP,CC_B_OP is $(NOTVLE) & OP=19 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=257 & BIT_0=0 +{ + setCrBit(CR_D,CR_D_CC,CC_OP & CC_B_OP); +} + +#crandc lt,lt,lt 0x4c 00 01 02 +#crandc 4*cr1+lt,4*cr2+gt,4*cr3+eq 0x4c 89 71 02 +:crandc CC_D_OP,CC_OP,CC_B_OP is $(NOTVLE) & OP=19 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=129 & BIT_0=0 +{ + tmp1:1 = !CC_B_OP; + setCrBit(CR_D,CR_D_CC,CC_OP & tmp1); +} + +#creqv lt,lt,lt 0x4c 00 02 42 +#creqv 4*cr1+lt,4*cr2+gt,4*cr3+eq 0x4c 89 72 42 +:creqv CC_D_OP,CC_OP,CC_B_OP is $(NOTVLE) & OP=19 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=289 & BIT_0=0 +{ + setCrBit(CR_D,CR_D_CC,CC_B_OP == CC_OP); +} + +#crnand lt,lt,lt 0x4c 00 01 c2 +#crnand 4*cr1+lt,4*cr2+gt,4*cr3+eq 0x4c 89 71 c2 +:crnand CC_D_OP,CC_OP,CC_B_OP is $(NOTVLE) & OP=19 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=225 & BIT_0=0 +{ + setCrBit(CR_D,CR_D_CC,!(CC_B_OP & CC_OP)); +} + +#crnor lt,lt,lt 0x4c 00 00 42 +#crnor 4*cr1+lt,4*cr2+gt,4*cr3+eq 0x4c 89 70 42 +:crnor CC_D_OP,CC_OP,CC_B_OP is $(NOTVLE) & OP=19 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=33 & BIT_0=0 +{ + setCrBit(CR_D,CR_D_CC,!(CC_B_OP | CC_OP)); +} + +#cror lt,lt,lt 0x4c 00 03 82 +#cror 4*cr1+lt,4*cr2+gt,4*cr3+eq 0x4c 89 73 82 +:cror CC_D_OP,CC_OP,CC_B_OP is $(NOTVLE) & OP=19 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=449 & BIT_0=0 +{ + setCrBit(CR_D,CR_D_CC,(CC_B_OP | CC_OP)); +} + +#crorc lt,lt,lt 0x4c 00 03 42 +#crorc 4*cr1+lt,4*cr2+gt,4*cr3+eq 0x4c 89 73 42 +:crorc CC_D_OP,CC_OP,CC_B_OP is $(NOTVLE) & OP=19 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=417 & BIT_0=0 +{ + setCrBit(CR_D,CR_D_CC,((!CC_B_OP) | CC_OP)); +} + +#crxor lt,lt,lt 0x4c 00 01 82 +#crxor 4*cr1+lt,4*cr2+gt,4*cr3+eq 0x4c 89 71 82 +:crxor CC_D_OP,CC_OP,CC_B_OP is $(NOTVLE) & OP=19 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=193 & BIT_0=0 +{ + setCrBit(CR_D,CR_D_CC,(CC_B_OP ^ CC_OP)); +} + +@ifndef IS_ISA +# replace with dci command in ISA +#dccci 0,r0 0x7c 00 03 8c +:dccci RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=454 & BIT_0=0 & RA_OR_ZERO +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + dataCacheCongruenceClassInvalidate(ea); +} +@endif + +#=========================================================== +# DIVxx +#=========================================================== + +@ifdef BIT_64 +#divd r0,r0,r0 0x7c 00 03 d2 +:divd D,A,B is OP=31 & D & A & B & OE=0 & XOP_1_9=489 & Rc=0 +{ + D = A s/ B; +} + +#divd. r0,r0,r0 0x7c 00 03 d3 +:divd. D,A,B is OP=31 & D & A & B & OE=0 & XOP_1_9=489 & Rc=1 +{ + D = A s/ B; + cr0flags(D); +} + +#divdo r0,r0,r0 0x7c 00 07 d2 +:divdo D,A,B is OP=31 & D & A & B & OE=1 & XOP_1_9=489 & Rc=0 +{ + divOverflow(A,B); + D = A s/ B; +} + +#divdo. r0,r0,r0 0x7c 00 07 d3 +:divdo. D,A,B is OP=31 & D & A & B & OE=1 & XOP_1_9=489 & Rc=1 +{ + divOverflow(A,B); + D = A s/ B; + cr0flags(D); +} + +###################### +#divdu r0,r0,r0 0x7c 00 03 92 +:divdu D,A,B is OP=31 & D & A & B & OE=0 & XOP_1_9=457 & Rc=0 +{ + D = A / B; +} + +#divdu. r0,r0,r0 0x7c 00 03 93 +:divdu. D,A,B is OP=31 & D & A & B & OE=0 & XOP_1_9=457 & Rc=1 +{ + D = A / B; + cr0flags(D); +} + +#divduo r0,r0,r0 0x7c 00 07 92 +:divduo D,A,B is OP=31 & D & A & B & OE=1 & XOP_1_9=457 & Rc=0 +{ + divZero(B); + D = A / B; +} + +#divduo. r0,r0,r0 0x7c 00 07 93 +:divduo. D,A,B is OP=31 & D & A & B & OE=1 & XOP_1_9=457 & Rc=1 +{ + divZero(B); + D = A / B; + cr0flags(D); +} +@endif + +#############################3 +#divw r0,r0,r0 0x7c 00 03 d6 +:divw D,A,B is OP=31 & D & A & B & OE=0 & XOP_1_9=491 & Rc=0 +{ +@ifdef BIT_64 + D = sext(A:4 s/ B:4); +@else + D = A s/ B; +@endif +} + +#divw. r0,r0,r0 0x7c 00 03 d7 +:divw. D,A,B is OP=31 & D & A & B & OE=0 & XOP_1_9=491 & Rc=1 +{ +@ifdef BIT_64 + divOverflow(A:4,B:4); + D = sext(A:4 s/ B:4); + cr0flags(D:4); +@else + divOverflow(A,B); + D = A s/ B; + cr0flags(D); +@endif +} + +#divwo r0,r0,r0 0x7c 00 07 d6 +:divwo D,A,B is OP=31 & D & A & B & OE=1 & XOP_1_9=491 & Rc=0 +{ +@ifdef BIT_64 + divOverflow(A:4,B:4); + D = sext(A:4 s/ B:4); +@else + divOverflow(A,B); + D = A s/ B; +@endif +} + +#divwo. r0,r0,r0 0x7c 00 07 d7 +:divwo. D,A,B is OP=31 & D & A & B & OE=1 & XOP_1_9=491 & Rc=1 +{ +@ifdef BIT_64 + divOverflow(A:4,B:4); + D = sext(A:4 s/ B:4); + cr0flags(D:4); +@else + divOverflow(A,B); + D = A s/ B; + cr0flags(D); +@endif +} + +######################### +#divwu r0,r0,r0 0x7c 00 03 96 +:divwu D,A,B is OP=31 & D & A & B & OE=0 & XOP_1_9=459 & Rc=0 +{ +@ifdef BIT_64 + D = zext(A:4) / zext(B:4); +@else + D = A / B; +@endif +} + +#divwu. r0,r0,r0 0x7c 00 03 97 +:divwu. D,A,B is OP=31 & D & A & B & OE=0 & XOP_1_9=459 & Rc=1 +{ +@ifdef BIT_64 + D = zext(A:4) / zext(B:4); + cr0flags(D:4); +@else + D = A / B; + cr0flags(D); +@endif +} + +#divwuo r0,r0,r0 0x7c 00 07 96 +:divwuo D,A,B is OP=31 & D & A & B & OE=1 & XOP_1_9=459 & Rc=0 +{ +@ifdef BIT_64 + divZero(B:4); + D = zext(A:4) / zext(B:4); +@else + divZero(B); + D = A / B; +@endif +} + +#divwuo. r0,r0,r0 0x7c 00 07 97 +:divwuo. D,A,B is OP=31 & D & A & B & OE=1 & XOP_1_9=459 & Rc=1 +{ +@ifdef BIT_64 + divZero(B:4); + D = zext(A:4) / zext(B:4); + cr0flags(D:4); +@else + divZero(B); + D = A / B; + cr0flags(D); +@endif +} + +#=========================================================== +# ECxxx,EIxxx +#=========================================================== +#eciwx r0,r0,r0 0x7c 00 02 6c +:eciwx D,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & D & B & RA_OR_ZERO & XOP_1_10=310 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + D = externalControlIn(ea); +} + +#ecowx r0,r0,r0 0x7c 00 03 6c +:ecowx S,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & S & B & RA_OR_ZERO & XOP_1_10=438 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + externalControlOut(ea, S); +} + +#=========================================================== +# EQVx +#=========================================================== +#eqv r0,r0,r0 0x7c 00 02 38 +:eqv A,S,B is OP=31 & S & A & B & XOP_1_10=284 & Rc=0 +{ + A = ~(S ^ B); +} + +#eqv. r0,r0,r0 0x7c 00 02 39 +:eqv. A,S,B is OP=31 & S & A & B & XOP_1_10=284 & Rc=1 +{ + A = ~(S ^ B); + cr0flags(A); +} + +#=========================================================== +# EXTSBx +#=========================================================== +#extsb r0,r0 0x7c 00 07 74 +:extsb A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=954 & Rc=0 +{ + A = sext(S:1); +} + +#extsb. r0,r0 0x7c 00 07 75 +:extsb. A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=954 & Rc=1 +{ + A = sext(S:1); + cr0flags(A); +} + +#=========================================================== +# EXTSHx +#=========================================================== +#extsh r0,r0 0x7c 00 07 34 +:extsh A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=922 & Rc=0 +{ + A = sext(S:2); +} + +#extsh. r0,r0 0x7c 00 07 35 +:extsh. A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=922 & Rc=1 +{ + A = sext(S:2); + cr0flags(A); +} + +@ifdef BIT_64 +#extsw r0,r0 0x7c 00 07 b4 +:extsw A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=986 & Rc=0 +{ + A = sext(S:4); +} + +#extsw. r0,r0 0x7c 00 07 b5 +:extsw. A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=986 & Rc=1 +{ + A = sext(S:4); + cr0flags(A); +} +@endif + +#=========================================================== +# FABSx +#=========================================================== +#fabs fr,f1r 0xfc 00 02 10 +:fabs fD,fB is $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=264 & Rc=0 +{ + fD = abs(fB); +} + +#fabs. fr0,fr1 0xfc 00 02 11 +:fabs. fD,fB is $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=264 & Rc=1 +{ + fD = abs(fB); + cr1flags(); +} +#fadd fr0,fr0,fr0 0xfc 00 00 2a +:fadd fD,fA,fB is $(NOTVLE) & OP=63 & fD & fA & fB & BITS_6_10=0 & XOP_1_5=21 & Rc=0 +{ + local tmpfA = fA; + local tmpfB = fB; + fD = fA f+ fB; + setFPAddFlags(tmpfA,tmpfB,fD); +} + +#fadd. fr0,fr0,fr0 0xfc 00 00 2b +:fadd. fD,fA,fB is $(NOTVLE) & OP=63 & fD & fA & fB & BITS_6_10=0 & XOP_1_5=21 & Rc=1 +{ + local tmpfA = fA; + local tmpfB = fB; + fD = fA f+ fB; + setFPAddFlags(tmpfA,tmpfB,fD); + cr1flags(); +} + +#fadds fr0,fr0,fr0 0xec 00 00 2a +:fadds fD,fA,fB is $(NOTVLE) & OP=59 & fD & fA & fB & BITS_6_10=0 & XOP_1_5=21 & Rc=0 +{ + local tmpfA = fA; + local tmpfB = fB; + tmp:4 = float2float(fA f+ fB); + fD = float2float(tmp); + setFPAddFlags(tmpfA,tmpfB,fD); + +} + +#fadds. fr0,fr0,fr0 0xec 00 00 2b +:fadds. fD,fA,fB is $(NOTVLE) & OP=59 & fD & fA & fB & BITS_6_10=0 & XOP_1_5=21 & Rc=1 +{ + local tmpfA = fA; + local tmpfB = fB; + tmp:4 = float2float(fA f+ fB); + fD = float2float(tmp); + setFPAddFlags(tmpfA,tmpfB,fD); + cr1flags(); +} + +#=========================================================== +# FCFIDx +#=========================================================== +#fcfid fr0,fr0 0xfc 00 06 9c +:fcfid fD,fB is $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=846 & Rc=0 +{ + fD = int2float(fB); +} + +#fcfid. fr0,fr0 0xfc 00 06 9d +:fcfid. fD,fB is $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=846 & Rc=1 +{ + fD = int2float(fB); + setFPRF(fD); +# fp_fr = intToFloatRoundedUp(fB); +# fp_fi = intToFloatInexact(fB); + fp_xx = fp_xx | fp_fi; + setSummaryFPSCR(); + cr1flags(); +} + +#=========================================================== +# FCMPO +#=========================================================== +#fcmpo fr0,fr0,fr0 0xfc 00 00 40 +:fcmpo CRFD,fA,fB is $(NOTVLE) & OP=63 & CRFD & BITS_21_22=0 & fA & fB & XOP_1_10=32 & BIT_0=0 +{ + tmp:1 = nan(fA) | nan(fB); + fp_cc0 = (fA f< fB); + fp_cc1 = (fA f> fB); + fp_cc2 = (fA f== fB); + CRFD = (fp_cc0 << 3) | (fp_cc1 << 2) | (fp_cc2 << 1) | tmp; +} +#fcmpu fr0,fr0,fr0 0xfc 00 00 00 +:fcmpu CRFD,fA,fB is $(NOTVLE) & OP=63 & CRFD & BITS_21_22=0 & fA & fB & XOP_1_10=0 & BIT_0=0 +{ + tmp:1 = nan(fA) | nan(fB); + fp_cc0 = (fA f< fB); + fp_cc1 = (fA f> fB); + fp_cc2 = (fA f== fB); + CRFD = (fp_cc0 << 3) | (fp_cc1 << 2) | (fp_cc2 << 1) | tmp; +} + +#fctid fr0,fr0 0xfc 00 06 5c +:fctid fD,fB is $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=814 & Rc=0 +{ +# fp_fr = floatToIntRoundedUp(fB); +# fp_fi = floatToIntInexact(fB); + fp_vxsnan = fp_vxsnan | nan(fB); +# fp_vxcvi = fp_vxcvi | invalidFloatToInt(fB); +# fp_xx = fp_xx | fp_fi; + fD = trunc(fB); +} +#fctid. fr0,fr0 0xfc 00 06 5d +:fctid. fD,fB is $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=814 & Rc=1 +{ +# fp_fr = floatToIntRoundedUp(fB); +# fp_fi = floatToIntInexact(fB); + fp_xx = fp_xx | fp_fi; +# fp_vxsnan = fp_vxsnan | nan(fB); +# fp_vxcvi = fp_vxcvi | invalidFloatToInt(fB); + setSummaryFPSCR(); + cr1flags(); + fD = trunc(fB); +} +#fctidz fr0,fr0 0xfc 00 06 5e +:fctidz fD,fB is $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=815 & Rc=0 +{ + fp_fr = 0; +# fp_fi = floatToIntInexact(fB); + fp_vxsnan = fp_vxsnan | nan(fB); +# fp_vxcvi = fp_vxcvi | invalidFloatToInt(fB); + fp_xx = fp_xx | fp_fi; + fD = trunc(fB); +} +#fctidz. fr0,fr0 0xfc 00 06 5f +:fctidz. fD,fB is $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=815 & Rc=1 +{ + fp_fr = 0; +# fp_fi = floatToIntInexact(fB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(fB); +# fp_vxcvi = fp_vxcvi | invalidFloatToInt(fB); + setSummaryFPSCR(); + cr1flags(); + fD = trunc(fB); +} + +#fctiw fr0,fr0 0xfc 00 00 1c +:fctiw fD,fB is $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=14 & Rc=0 +{ +# fp_fr = floatToIntRoundedUp(fB); +# fp_fi = floatToIntInexact(fB); + fp_vxsnan = fp_vxsnan | nan(fB); +# fp_vxcvi = fp_vxcvi | invalidFloatToInt(fB); + fp_xx = fp_xx | fp_fi; + local intres:4; + intres = trunc(fB); + fD = sext(intres); +} +#fctiw. fr0,fr0 0xfc 00 00 1d +:fctiw. fD,fB is $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=14 & Rc=1 +{ +# fp_fr = floatToIntRoundedUp(fB); +# fp_fi = floatToIntInexact(fB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(fB); +# fp_vxcvi = fp_vxcvi | invalidFloatToInt(fB); + setSummaryFPSCR(); + cr1flags(); + local intres:4; + intres = trunc(fB); + fD = sext(intres); +} +#fctiwz fr0,fr0 0xfc 00 00 1e +:fctiwz fD,fB is $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=15 & Rc=0 +{ + fp_fr = 0; +# fp_fi = floatToIntInexact(fB); + fp_vxsnan = fp_vxsnan | nan(fB); +# fp_vxcvi = fp_vxcvi | invalidFloatToInt(fB); + fp_xx = fp_xx | fp_fi; + local intres:4; + intres = trunc(fB); + fD = sext(intres); +} +#fctiwz. fr0,fr0 0xfc 00 00 1f +:fctiwz. fD,fB is $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=15 & Rc=1 +{ + fp_fr = 0; +# fp_fi = floatToIntInexact(fB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(fB); +# fp_vxcvi = fp_vxcvi | invalidFloatToInt(fB); + setSummaryFPSCR(); + cr1flags(); + local intres:4; + intres = trunc(fB); + fD = sext(intres); +} + +#fdiv fr0,fr0,fr0 0xfc 00 00 24 +:fdiv fD,fA,fB is $(NOTVLE) & OP=63 & fD & fA & fB & BITS_6_10=0 & XOP_1_5=18 & Rc=0 +{ + local tmpfA = fA; + local tmpfB = fB; + fD = fA f/ fB; + setFPDivFlags(tmpfA,tmpfB,fD); +} +#fdiv. fr0,fr0,fr0 0xfc 00 00 25 +:fdiv. fD,fA,fB is $(NOTVLE) & OP=63 & fD & fA & fB & BITS_6_10=0 & XOP_1_5=18 & Rc=1 +{ + local tmpfA = fA; + local tmpfB = fB; + fD = fA f/ fB; + setFPDivFlags(tmpfA,tmpfB,fD); + cr1flags(); +} + +#fdivs fr0,fr0,fr0 0xec 00 00 24 +:fdivs fD,fA,fB is $(NOTVLE) & OP=59 & fD & fA & fB & BITS_6_10=0 & XOP_1_5=18 & Rc=0 +{ + local tmpfA = fA; + local tmpfB = fB; + tmp:4 = float2float(fA f/ fB); + fD = float2float(tmp); + setFPDivFlags(tmpfA,tmpfB,fD); +} +#fdivs. fr0,fr0,fr0 0xec 00 00 25 +:fdivs. fD,fA,fB is $(NOTVLE) & OP=59 & fD & fA & fB & BITS_6_10=0 & XOP_1_5=18 & Rc=1 +{ + local tmpfA = fA; + local tmpfB = fB; + tmp:4 = float2float(fA f/ fB); + fD = float2float(tmp); + setFPDivFlags(tmpfA,tmpfB,fD); + cr1flags(); +} + +#fmadd fr0,fr0,fr0,fr0 0xfc 00 00 3a +:fmadd fD,fA,fC,fB is $(NOTVLE) & OP=63 & fD & fA & fC & fB & XOP_1_5=29 & Rc=0 +{ + local tmpfA = fA; + local tmpfB = fB; + local tmpfC = fC; + tmp:8 = fA f* fC; + fD = tmp f+ fB; + setFPRF(fD); +# fp_fr = floatMaddRoundedUp(tmpfA, tmpfC, tmpfB); +# fp_fi = floatMaddInexact(tmpfA,tmpfC,tmpfB); +# fp_ox = fp_ox | floatMaddOverflow(tmpfA,tmpfC,tmpfB); +# fp_ux = fp_ux | floatMaddUnderflow(tmpfA,tmpfC,tmpfB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB); +# fp_vxisi = fp_vxisi | floatInfinityAdd(tmp, tmpfB); +# fp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC); + setSummaryFPSCR(); +} + +#fmadd. fr0,fr0,fr0,fr0 0xfc 00 00 3b +:fmadd. fD,fA,fC,fB is $(NOTVLE) & OP=63 & fD & fA & fC & fB & XOP_1_5=29 & Rc=1 +{ + local tmpfA = fA; + local tmpfB = fB; + local tmpfC = fC; + tmp:8 = fA f* fC; + fD = tmp f+ fB; + setFPRF(fD); +# fp_fr = floatMaddRoundedUp(tmpfA, tmpfC, tmpfB); +# fp_fi = floatMaddInexact(tmpfA,tmpfC,tmpfB); +# fp_ox = fp_ox | floatMaddOverflow(tmpfA,tmpfC,tmpfB); +# fp_ux = fp_ux | floatMaddUnderflow(tmpfA,tmpfC,tmpfB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB); +# fp_vxisi = fp_vxisi | floatInfinityAdd(tmp, tmpfB); +# fp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC); + setSummaryFPSCR(); + cr1flags(); +} + +#fmadds fr0,fr0,fr0,fr0 0xec 00 00 3a +:fmadds fD,fA,fC,fB is $(NOTVLE) & OP=59 & fD & fA & fC & fB & XOP_1_5=29 & Rc=0 +{ + local tmpfA = fA; + local tmpfB = fB; + local tmpfC = fC; + tmp:8 = fA f* fC; + tmp2:4 = float2float(tmp f+ fB); + fD = float2float(tmp2); + setFPRF(fD); +# fp_fr = floatMaddRoundedUp(tmpfA, tmpfC, tmpfB); +# fp_fi = floatMaddInexact(tmpfA,tmpfC,tmpfB); +# fp_ox = fp_ox | floatMaddOverflow(tmpfA,tmpfC,tmpfB); +# fp_ux = fp_ux | floatMaddUnderflow(tmpfA,tmpfC,tmpfB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB); +# fp_vxisi = fp_vxisi | floatInfinityAdd(tmp, tmpfB); +# fp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tm[fC); + setSummaryFPSCR(); +} + +#fmadds. fr0,fr0,fr0,fr0 0xec 00 00 3b +:fmadds. fD,fA,fC,fB is $(NOTVLE) & OP=59 & fD & fA & fC & fB & XOP_1_5=29 & Rc=1 +{ + local tmpfA = fA; + local tmpfB = fB; + local tmpfC = fC; + tmp:8 = fA f* fC; + tmp2:4 = float2float(tmp f+ fB); + fD = float2float(tmp2); + setFPRF(fD); +# fp_fr = floatMaddRoundedUp(tmpfA, tmpfC, tmpfB); +# fp_fi = floatMaddInexact(tmpfA,tmpfC,tmpfB); +# fp_ox = fp_ox | floatMaddOverflow(tmpfA,tmpfC,tmpfB); +# fp_ux = fp_ux | floatMaddUnderflow(tmpfA,tmpfC,tmpfB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB); +# fp_vxisi = fp_vxisi | floatInfinityAdd(tmp, tmpfB); +# fp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC); + setSummaryFPSCR(); + cr1flags(); +} + +#fmr fr0,fr0 0xfc 00 00 90 +:fmr fD,fB is $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=72 & Rc=0 +{ + fD = fB; +} +#fmr. fr0,fr0 0xfc 00 00 91 +:fmr. fD,fB is $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=72 & Rc=1 +{ + fD = fB; + cr1flags(); +} +#fmsub fr0,fr0,fr0,fr0 0xfc 00 00 38 +:fmsub fD,fA,fC,fB is $(NOTVLE) & OP=63 & fD & fA & fC & fB & XOP_1_5=28 & Rc=0 +{ + local tmpfA = fA; + local tmpfB = fB; + local tmpfC = fC; + tmp:8 = fA f* fC; + fD = tmp f- fB; + setFPRF(fD); +# fp_fr = floatMsubRoundedUp(tmpfA, tmpfC, tmpfB); +# fp_fi = floatMsubInexact(tmpfA,tmpfC,tmpfB); +# fp_ox = fp_ox | floatMsubOverflow(tmpfA,tmpfC,tmpfB); +# fp_ux = fp_ux | floatMsubUnderflow(tmpfA,tmpfC,tmpfB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB); +# fp_vxisi = fp_vxisi | floatInfinitySub(tmp, tmpfB); +# fp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC); + setSummaryFPSCR(); +} + +#fmsub. fr0,fr0,fr0,fr0 0xfc 00 00 39 +:fmsub. fD,fA,fC,fB is $(NOTVLE) & OP=63 & fD & fA & fC & fB & XOP_1_5=28 & Rc=1 +{ + local tmpfA = fA; + local tmpfB = fB; + local tmpfC = fC; + tmp:8 = fA f* fC; + tmp2:4 = float2float(tmp f- fB); + fD = float2float(tmp2); + setFPRF(fD); +# fp_fr = floatMsubRoundedUp(tmpfA, tmpfC, tmpfB); +# fp_fi = floatMsubInexact(tmpfA,tmpfC,tmpfB); +# fp_ox = fp_ox | floatMsubOverflow(tmpfA,tmpfC,tmpfB); +# fp_ux = fp_ux | floatMsubUnderflow(tmpfA,tmpfC,tmpfB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB); +# fp_vxisi = fp_vxisi | floatInfinitySub(tmp, tmpfB); +# fp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC); + setSummaryFPSCR(); + cr1flags(); +} + +#fmsubs fr0,fr0,fr0,fr0 0xec 00 00 38 +:fmsubs fD,fA,fC,fB is $(NOTVLE) & OP=59 & fD & fA & fC & fB & XOP_1_5=28 & Rc=0 +{ + local tmpfA = fA; + local tmpfB = fB; + local tmpfC = fC; + tmp:8 = fA f* fC; + tmp2:4 = float2float(tmp f- fB); + fD = float2float(tmp2); + setFPRF(fD); +# fp_fr = floatMsubRoundedUp(tmpfA, tmpfC, tmpfB); +# fp_fi = floatMsubInexact(tmpfA,tmpfC,tmpfB); +# fp_ox = fp_ox | floatMsubOverflow(tmpfA,tmpfC,tmpfB); +# fp_ux = fp_ux | floatMsubUnderflow(tmpfA,tmpfC,tmpfB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB); +# fp_vxisi = fp_vxisi | floatInfinitySub(tmp, tmpfB); +# fp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC); + setSummaryFPSCR(); +} + +#fmsubs. fr0,fr0,fr0,fr0 0xfc 00 00 39 +:fmsubs. fD,fA,fC,fB is $(NOTVLE) & OP=59 & fD & fA & fC & fB & XOP_1_5=28 & Rc=1 +{ + local tmpfA = fA; + local tmpfB = fB; + local tmpfC = fC; + tmp:8 = fA f* fC; + tmp2:4 = float2float(tmp f- fB); + fD = float2float(tmp2); + setFPRF(fD); +# fp_fr = floatMsubRoundedUp(tmpfA, tmpfC, tmpfB); +# fp_fi = floatMsubInexact(tmpfA,tmpfC,tmpfB); +# fp_ox = fp_ox | floatMsubOverflow(tmpfA,tmpfC,tmpfB); +# fp_ux = fp_ux | floatMsubUnderflow(tmpfA,tmpfC,tmpfB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB); +# fp_vxisi = fp_vxisi | floatInfinitySub(tmp, tmpfB); +# fp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC); + setSummaryFPSCR(); + cr1flags(); +} + +#fmul fr0,fr0,fr0 0xfc 00 00 32 +:fmul fD,fA,fC is $(NOTVLE) & OP=63 & fD & fA & fC & BITS_11_15=0 & XOP_1_5=25 & Rc=0 +{ + local tmpfA = fA; + local tmpfC = fC; + fD = fA f* fC; + setFPMulFlags(tmpfA,tmpfC,fD); +} +#fmul. fr0,fr0,fr0 0xfc 00 00 33 +:fmul. fD,fA,fC is $(NOTVLE) & OP=63 & fD & fA & fC & BITS_11_15=0 & XOP_1_5=25 & Rc=1 +{ + local tmpfA = fA; + local tmpfC = fC; + fD = fA f* fC; + setFPMulFlags(tmpfA,tmpfC,fD); + cr1flags(); +} + +#fmuls fr0,fr0,fr0 0xec 00 00 32 +:fmuls fD,fA,fC is $(NOTVLE) & OP=59 & fD & fA & fC & BITS_11_15=0 & XOP_1_5=25 & Rc=0 +{ + local tmpfA = fA; + local tmpfC = fC; + tmp:4 = float2float(fA f* fC); + fD = float2float(tmp); + setFPMulFlags(tmpfA,tmpfC,fD); +} + +#fmuls. fr0,fr0,fr0 0xec 00 00 33 +:fmuls. fD,fA,fC is $(NOTVLE) & OP=59 & fD & fA & fC & BITS_11_15=0 & XOP_1_5=25 & Rc=1 +{ + local tmpfA = fA; + local tmpfC = fC; + tmp:4 = float2float(fA f* fC); + fD = float2float(tmp); + setFPMulFlags(tmpfA,tmpfC,fD); + cr1flags(); +} + +#fnabs fr0,fr0 0xfc 00 01 10 +:fnabs fD,fB is $(NOTVLE) & OP=63 & fD & fB & BITS_16_20=0 & XOP_1_10=136 & Rc=0 +{ + fD = fB | 0x8000000000000000; +} + +#fnabs. fr0,fr0 0xfc 00 01 11 +:fnabs. fD,fB is $(NOTVLE) & OP=63 & fD & fB & BITS_16_20=0 & XOP_1_10=136 & Rc=1 +{ + fD = fB | 0x8000000000000000; + cr1flags(); +} + +#fneg fr0,fr0 0xfc 00 00 50 +:fneg fD,fB is $(NOTVLE) & OP=63 & fD & fB & BITS_16_20=0 & XOP_1_10=40 & Rc=0 +{ + fD = f- fB; +} + +#fneg. fr0,fr0 0xfc 00 00 51 +:fneg. fD,fB is $(NOTVLE) & OP=63 & fD & fB & BITS_16_20=0 & XOP_1_10=40 & Rc=1 +{ + fD = f- fB; + cr1flags(); +} + +#fnmadd fr0,fr0,fr0,fr0 0xfc 00 00 3e +:fnmadd fD,fA,fC,fB is $(NOTVLE) & OP=63 & fD & fA & fC & fB & XOP_1_5=31 & Rc=0 +{ + local tmpfA = fA; + local tmpfB = fB; + local tmpfC = fC; + tmp:8 = fA f* fC; + fD = f- (tmp f+ fB); + setFPRF(fD); +# fp_fr = floatMaddRoundedUp(tmpfA, tmpfC, tmpfB); +# fp_fi = floatMaddInexact(tmpfA,tmpfC,tmpfB); +# fp_ox = fp_ox | floatMaddOverflow(tmpfA,tmpfC,tmpfB); +# fp_ux = fp_ux | floatMaddUnderflow(tmpfA,tmpfC,tmpfB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB); +# fp_vxisi = fp_vxisi | floatInfinityAdd(tmp, tmpfB); +# fp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC); + setSummaryFPSCR(); +} + +#fnmadd. fr0,fr0,fr0,fr0 0xfc 00 00 3f +:fnmadd. fD,fA,fC,fB is $(NOTVLE) & OP=63 & fD & fA & fC & fB & XOP_1_5=31 & Rc=1 +{ + local tmpfA = fA; + local tmpfB = fB; + local tmpfC = fC; + tmp:8 = fA f* fC; + fD = f- (tmp f+ fB); + setFPRF(fD); +# fp_fr = floatMaddRoundedUp(tmpfA, tmpfC, tmpfB); +# fp_fi = floatMaddInexact(tmpfA,tmpfC,tmpfB); +# fp_ox = fp_ox | floatMaddOverflow(tmpfA,tmpfC,tmpfB); +# fp_ux = fp_ux | floatMaddUnderflow(tmpfA,tmpfC,tmpfB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB); +# fp_vxisi = fp_vxisi | floatInfinityAdd(tmp, tmpfB); +# fp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC); + setSummaryFPSCR(); + cr1flags(); +} + +#fnmadds fr0,fr0,fr0,fr0 0xec 00 00 3e +:fnmadds fD,fA,fC,fB is $(NOTVLE) & OP=59 & fD & fA & fC & fB & XOP_1_5=31 & Rc=0 +{ + local tmpfA = fA; + local tmpfB = fB; + local tmpfC = fC; + tmp:8 = fA f* fC; + tmp2:4 = float2float(tmp f+ fB); + fD = f- float2float(tmp2); + setFPRF(fD); +# fp_fr = floatMaddRoundedUp(tmpfA, tmpfC, tmpfB); +# fp_fi = floatMaddInexact(tmpfA,tmpfC,tmpfB); +# fp_ox = fp_ox | floatMaddOverflow(tmpfA,tmpfC,tmpfB); +# fp_ux = fp_ux | floatMaddUnderflow(tmpfA,tmpfC,tmpfB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB); +# fp_vxisi = fp_vxisi | floatInfinityAdd(tmp, tmpfB); +# fp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC); + setSummaryFPSCR(); +} + +#fnmadds. fr0,fr0,fr0,fr0 0xec 00 00 3f +:fnmadds. fD,fA,fC,fB is $(NOTVLE) & OP=59 & fD & fA & fC & fB & XOP_1_5=31 & Rc=1 +{ + local tmpfA = fA; + local tmpfB = fB; + local tmpfC = fC; + tmp:8 = fA f* fC; + tmp2:4 = float2float(tmp f+ fB); + fD = f- float2float(tmp2); + setFPRF(fD); +# fp_fr = floatMaddRoundedUp(tmpfA, tmpfC, tmpfB); +# fp_fi = floatMaddInexact(tmpfA,tmpfC,tmpfB); +# fp_ox = fp_ox | floatMaddOverflow(tmpfA,tmpfC,tmpfB); +# fp_ux = fp_ux | floatMaddUnderflow(tmpfA,tmpfC,tmpfB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB); +# fp_vxisi = fp_vxisi | floatInfinityAdd(tmp, tmpfB); +# fp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC); + setSummaryFPSCR(); + cr1flags(); +} + +#fnmsub fr0,fr0,fr0,fr0 0xfc 00 00 3c +:fnmsub fD,fA,fC,fB is $(NOTVLE) & OP=63 & fD & fA & fC & fB & XOP_1_5=30 & Rc=0 +{ + local tmpfA = fA; + local tmpfB = fB; + local tmpfC = fC; + tmp:8 = fA f* fC; + fD = f- (tmp f- fB); + setFPRF(fD); +# fp_fr = floatMsubRoundedUp(tmpfA, tmpfC, tmpfB); +# fp_fi = floatMsubInexact(tmpfA,tmpfC,tmpfB); +# fp_ox = fp_ox | floatMsubOverflow(tmpfA,tmpfC,tmpfB); +# fp_ux = fp_ux | floatMsubUnderflow(tmpfA,tmpfC,tmpfB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB); +# fp_vxisi = fp_vxisi | floatInfinitySub(tmp, tmpfB); +# fp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC); + setSummaryFPSCR(); +} + +#fnmsub. fr0,fr0,fr0,fr0 0xfc 00 00 3d +:fnmsub. fD,fA,fC,fB is $(NOTVLE) & OP=63 & fD & fA & fC & fB & XOP_1_5=30 & Rc=1 +{ + local tmpfA = fA; + local tmpfB = fB; + local tmpfC = fC; + tmp:8 = fA f* fC; + tmp2:4 = float2float(tmp f- fB); + fD = f- float2float(tmp2); + setFPRF(fD); +# fp_fr = floatMsubRoundedUp(tmpfA, tmpfC, tmpfB); +# fp_fi = floatMsubInexact(tmpfA,tmpfC,tmpfB); +# fp_ox = fp_ox | floatMsubOverflow(tmpfA,tmpfC,tmpfB); +# fp_ux = fp_ux | floatMsubUnderflow(tmpfA,tmpfC,tmpfB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB); +# fp_vxisi = fp_vxisi | floatInfinitySub(tmp, tmpfB); +# fp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC); + setSummaryFPSCR(); + cr1flags(); +} + +#fnmsubs fr0,fr0,fr0,fr0 0xec 00 00 3c +:fnmsubs fD,fA,fC,fB is $(NOTVLE) & OP=59 & fD & fA & fC & fB & XOP_1_5=30 & Rc=0 +{ + local tmpfA = fA; + local tmpfB = fB; + local tmpfC = fC; + tmp:8 = fA f* fC; + tmp2:4 = float2float(tmp f- fB); + fD = f- float2float(tmp2); + setFPRF(fD); +# fp_fr = floatMsubRoundedUp(tmpfA, tmpfC, tmpfB); +# fp_fi = floatMsubInexact(tmpfA,tmpfC,tmpfB); +# fp_ox = fp_ox | floatMsubOverflow(tmpfA,tmpfC,tmpfB); +# fp_ux = fp_ux | floatMsubUnderflow(tmpfA,tmpfC,tmpfB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB); +# fp_vxisi = fp_vxisi | floatInfinitySub(tmp, tmpfB); +# fp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC); + setSummaryFPSCR(); +} + +#fnmsubs. fr0,fr0,fr0,fr0 0xfc 00 00 3d +:fnmsubs. fD,fA,fC,fB is $(NOTVLE) & OP=59 & fD & fA & fC & fB & XOP_1_5=30 & Rc=1 +{ + local tmpfA = fA; + local tmpfB = fB; + local tmpfC = fC; + tmp:8 = fA f* fC; + tmp2:4 = float2float(tmp f- fB); + fD = f- float2float(tmp2); + setFPRF(fD); +# fp_fr = floatMsubRoundedUp(tmpfA, tmpfC, tmpfB); +# fp_fi = floatMsubInexact(tmpfA,tmpfC,tmpfB); +# fp_ox = fp_ox | floatMsubOverflow(tmpfA,tmpfC,tmpfB); +# fp_ux = fp_ux | floatMsubUnderflow(tmpfA,tmpfC,tmpfB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(tmpfA) | nan(tmpfC) | nan(tmpfB); +# fp_vxisi = fp_vxisi | floatInfinitySub(tmp, tmpfB); +# fp_vximz = fp_vximz | floatInfinityMulZero(tmpfA,tmpfC); + setSummaryFPSCR(); + cr1flags(); +} + +#fres fr0,fr0 0xec 00 00 30 +:fres fD,fB is $(NOTVLE) & OP=59 & fD & BITS_16_20 & fB & BITS_6_10=0 & XOP_1_5=24 & Rc=0 +{ + local tmpfB = fB; + one:8 = 1; + floatOne:8 = int2float(one); + tmp:4 = float2float(floatOne f/ fB); + fD = float2float(tmp); + setFPRF(fD); +# fp_fr = floatDivRoundedUp(floatOne, tmpfB); +# fp_fi = floatDivInexact(floatOne, tmpfB); +# fp_ox = fp_ox | floatDivOverflow(floatOne, tmpfB); +# fp_ux = fp_ux | floatDivUnderflow(floatOne, tmpfB); + fp_zx = fp_zx | (fB f== 0); + fp_vxsnan = fp_vxsnan | nan(tmpfB); + setSummaryFPSCR(); +} + +#fres. fr0,fr0 0xec 00 00 31 +:fres. fD,fB is $(NOTVLE) & OP=59 & fD & BITS_16_20 & fB & BITS_6_10=0 & XOP_1_5=24 & Rc=1 +{ + local tmpfB = fB; + one:8 = 1; + floatOne:8 = int2float(one); + tmp:4 = float2float(floatOne f/ fB); + fD = float2float(tmp); + setFPRF(fD); +# fp_fr = floatDivRoundedUp(floatOne, tmpfB); +# fp_fi = floatDivInexact(floatOne, tmpfB); +# fp_ox = fp_ox | floatDivOverflow(floatOne, tmpfB); +# fp_ux = fp_ux | floatDivUnderflow(floatOne, tmpfB); + fp_zx = fp_zx | (fB f== 0); + fp_vxsnan = fp_vxsnan | nan(tmpfB); + setSummaryFPSCR(); + cr1flags(); +} + +#frsp fr0,fr0 0xfc 00 00 18 +:frsp fD,fB is $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=12 & Rc=0 +{ + local tmpfB = fB; + #zero:8 = 0; + #floatZero:8 = int2float(zero); + tmp:4 = float2float(fB); + fD = float2float(tmp); + setFPRF(fD); +# fp_fr = floatAddRoundedUp(floatZero, tmpfB); +# fp_fi = floatAddInexact(floatZero, tmpfB); +# fp_ox = fp_ox | floatAddOverflow(floatZero, tmpfB); +# fp_ux = fp_ux | floatAddUnderflow(floatZero, tmpfB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(tmpfB); + setSummaryFPSCR(); +} + +#frsp. fr0,fr0 0xfc 00 00 19 +:frsp. fD,fB is $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & XOP_1_10=12 & Rc=1 +{ + local tmpfB = fB; + #zero:8 = 0; + #floatZero:8 = int2float(zero); + tmp:4 = float2float(fB); + fD = float2float(tmp); + setFPRF(fD); +# fp_fr = floatAddRoundedUp(floatZero, tmpfB); +# fp_fi = floatAddInexact(floatZero, tmpfB); +# fp_ox = fp_ox | floatAddOverflow(floatZero, tmpfB); +# fp_ux = fp_ux | floatAddUnderflow(floatZero, tmpfB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(tmpfB); + setSummaryFPSCR(); + cr1flags(); +} + +#frsqrte fr0,fr0 0xfc 00 00 34 +:frsqrte fD,fB is $(NOTVLE) & OP=63 & fD & BITS_16_20 & fB & BITS_6_10=0 & XOP_1_5=26 & Rc=0 +{ + local tmpfB = fB; + one:8 = 1; + floatOne:8 = int2float(one); + tmpSqrt:8 = sqrt(fB); + fD = (floatOne f/ tmpSqrt); + setFPRF(fD); +# fp_fr = floatDivRoundedUp(floatOne, tmpSqrt); +# fp_fi = floatDivInexact(floatOne, tmpSqrt); +# fp_ox = fp_ox | floatDivOverflow(floatOne, tmpSqrt); +# fp_ux = fp_ux | floatDivUnderflow(floatOne, tmpSqrt); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(tmpfB); + setSummaryFPSCR(); +} + +#frsqrte. fr0,fr0 0xfc 00 00 35 +:frsqrte. fD,fB is $(NOTVLE) & OP=63 & fD & BITS_16_20 & fB & BITS_6_10=0 & XOP_1_5=26 & Rc=1 +{ + local tmpfB = fB; + one:8 = 1; + floatOne:8 = int2float(one); + tmpSqrt:8 = sqrt(fB); + fD = (floatOne f/ tmpSqrt); + setFPRF(fD); +# fp_fr = floatDivRoundedUp(floatOne, tmpSqrt); +# fp_fi = floatDivInexact(floatOne, tmpSqrt); +# fp_ox = fp_ox | floatDivOverflow(floatOne, tmpSqrt); +# fp_ux = fp_ux | floatDivUnderflow(floatOne, tmpSqrt); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(tmpfB); + fp_vxsqrt = fp_vxsqrt | sqrtInvalid(tmpfB); + setSummaryFPSCR(); + cr1flags(); +} + +#fsel f0r,fr0,fr0,fr0 0xfc 00 00 2e +:fsel fD,fA,fC,fB is $(NOTVLE) & OP=63 & fD & fA & fB & fC & XOP_1_5=23 & Rc=0 +{ + local tmpfA = fA; + local tmpfB = fB; + zero:4=0; + fD=fC; + if (tmpfA f>= int2float(zero)) goto inst_next; + fD=tmpfB; +} + +#fsel. fr0,fr0,fr0,fr0 0xfc 00 00 2f +:fsel. fD,fA,fC,fB is $(NOTVLE) & OP=63 & fD & fA & fB & fC & XOP_1_5=23 & Rc=1 +{ + local tmpfA = fA; + local tmpfB = fB; + zero:4=0; + fD=fC; + if (tmpfA f>= int2float(zero)) goto ; + fD=tmpfB; + + cr1flags(); +} + +#fsqrt f0r,fr0 0xfc 00 00 2c +:fsqrt fD,fB is $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & BITS_6_10=0 & XOP_1_5=22 & Rc=0 +{ + local tmpfB = fB; + fD = sqrt(fB); + setFPRF(fD); +# fp_fr = floatSqrtRoundedUp(tmpfB); +# fp_fi = floatSqrtInexact(tmpfB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(tmpfB); +# fp_vxsqrt = fp_vxsqrt | sqrtInvalid(tmpfB); + setSummaryFPSCR(); +} + +#fsqrt. fr0,fr0 0xfc 00 00 2d +:fsqrt. fD,fB is $(NOTVLE) & OP=63 & fD & BITS_16_20=0 & fB & BITS_6_10=0 & XOP_1_5=22 & Rc=1 +{ + local tmpfB = fB; + fD = sqrt(fB); + setFPRF(fD); +# fp_fr = floatSqrtRoundedUp(tmpfB); +# fp_fi = floatSqrtInexact(tmpfB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(tmpfB); +# fp_vxsqrt = fp_vxsqrt | sqrtInvalid(tmpfB); + setSummaryFPSCR(); + cr1flags(); +} + +#fsqrts fr0,fr0 0xec 00 00 2c +:fsqrts fD,fB is $(NOTVLE) & OP=59 & fD & BITS_16_20=0 & fB & BITS_6_10=0 & XOP_1_5=22 & Rc=0 +{ + local tmpfB = fB; + tmp:4 = float2float(sqrt(fB)); + fD = float2float(tmp); + setFPRF(fD); +# fp_fr = floatSqrtRoundedUp(tmpfB); +# fp_fi = floatSqrtInexact(tmpfB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(tmpfB); +# fp_vxsqrt = fp_vxsqrt | sqrtInvalid(tmpfB); + setSummaryFPSCR(); +} + +#fsqrts. fr0,fr0 0xec 00 00 2d +:fsqrts. fD,fB is $(NOTVLE) & OP=59 & fD & BITS_16_20=0 & fB & BITS_6_10=0 & XOP_1_5=22 & Rc=1 +{ + local tmpfB = fB; + tmp:4 = float2float(sqrt(fB)); + fD = float2float(tmp); + setFPRF(fD); +# fp_fr = floatSqrtRoundedUp(tmpfB); +# fp_fi = floatSqrtInexact(tmpfB); + fp_xx = fp_xx | fp_fi; + fp_vxsnan = fp_vxsnan | nan(tmpfB); +# fp_vxsqrt = fp_vxsqrt | sqrtInvalid(tmpfB); + setSummaryFPSCR(); + cr1flags(); +} + +#fsub fr0,fr0,fr0 0xfc 00 00 28 +:fsub fD,fA,fB is $(NOTVLE) & OP=63 & fD & fA & fB & BITS_6_10=0 & XOP_1_5=20 & Rc=0 +{ + local tmpfA = fA; + local tmpfB = fB; + fD = fA f- fB; + setFPSubFlags(tmpfA,tmpfB,fD); +} + +#fsub. fr0,fr0,fr0 0xfc 00 00 29 +:fsub. fD,fA,fB is $(NOTVLE) & OP=63 & fD & fA & fB & BITS_6_10=0 & XOP_1_5=20 & Rc=1 +{ + local tmpfA = fA; + local tmpfB = fB; + fD = fA f- fB; + setFPSubFlags(tmpfA,tmpfB,fD); + cr1flags(); +} + +#fsubs fr0,fr0,fr0 0xec 00 00 28 +:fsubs fD,fA,fB is $(NOTVLE) & OP=59 & fD & fA & fB & BITS_6_10=0 & XOP_1_5=20 & Rc=0 +{ + local tmpfA = fA; + local tmpfB = fB; + tmp:4 = float2float(fA f- fB); + fD = float2float(tmp); + setFPSubFlags(tmpfA,tmpfB,fD); + +} + +#fsubs. fr0,fr0,fr0 0xec 00 00 29 +:fsubs. fD,fA,fB is $(NOTVLE) & OP=59 & fD & fA & fB & BITS_6_10=0 & XOP_1_5=20 & Rc=1 +{ + local tmpfA = fA; + local tmpfB = fB; + tmp:4 = float2float(fA f- fB); + fD = float2float(tmp); + setFPSubFlags(tmpfA,tmpfB,fD); + cr1flags(); +} + +@ifndef IS_ISA +# iccci is just a special form of ici +#iccci 0,r0 0x7c 00 07 8c +:iccci RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=966 & BIT_0=0 & RA_OR_ZERO +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + instructionCacheCongruenceClassInvalidate(ea); +} +@endif + +#icread 0,r0 0x7c 00 07 cc +:icread RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=998 & BIT_0=0 & RA_OR_ZERO +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + instructionCacheRead(ea); +} + +#lbz r0,3(0) 0x88 00 00 03 +#lbz r0,3(r2) 0x88 02 00 03 +:lbz D,dPlusRaOrZeroAddress is $(NOTVLE) & OP=34 & D & dPlusRaOrZeroAddress +{ + D = zext(*:1(dPlusRaOrZeroAddress)); + +} + +#lbzu r0,3(r2) 0x8c 02 00 03 +:lbzu D,dPlusRaAddress is $(NOTVLE) & OP=35 & D & dPlusRaAddress & A +{ + ea:$(REGISTER_SIZE) = dPlusRaAddress; + D = zext(*:1(ea)); + A = ea; +} + +#lbzux r0,r2,r0 0x7c 02 00 ee +:lbzux D,A,B is OP=31 & D & A & B & XOP_1_10=119 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = A+B; + D = zext(*:1(ea)); + A = ea; +} + +#lbzx r0,r2,r0 0x7c 02 00 ae +:lbzx D,RA_OR_ZERO,B is OP=31 & D & RA_OR_ZERO & B & XOP_1_10=87 & BIT_0=0 +{ + tmp:$(REGISTER_SIZE) = RA_OR_ZERO+B; + D = zext(*:1(tmp)); +} + +@ifdef BIT_64 +#ld r0,8(r2) 0xe8 02 00 08 +:ld D,dPlusRaOrZeroAddress is $(NOTVLE) & OP=58 & D & dPlusRaOrZeroAddress & BITS_0_1=0 +{ + D = *:8(dPlusRaOrZeroAddress); +} + +##ldarx r0,r0,r0 0x7c 00 00 a8 +#:ldarx T,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & T & RA_OR_ZERO & B & XOP_1_10=84 & TX +#{ +# ea = RA_OR_ZERO+B; +# RESERVE = 1; +# RESERVE_ADDRSS = ea; +# T = *:8(ea); +#} + +#ldu r0,8(r2) 0xe8 02 00 09 +:ldu D,dsPlusRaAddress is $(NOTVLE) & OP=58 & D & dsPlusRaAddress & A & BITS_0_1=1 +{ + ea:$(REGISTER_SIZE) = dsPlusRaAddress; + D = *:8(ea); + A = ea; +} + +#ldux r0,r2,r0 0x7c 02 00 6a +:ldux D,A,B is OP=31 & D & A & B & XOP_1_10=53 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = A+B; + D = *:8(ea); + A = ea; +} + +@ifndef IS_ISA +#ldarx r0,r2,r0 0x7c 02 00 2a +:ldarx D,RA_OR_ZERO,B is OP=31 & D & RA_OR_ZERO & B & XOP_1_10=21 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO+B; + D = *:8(ea); +} +@endif +@endif + +#lfd fr0,8(r2) 0xc8 02 00 08 +:lfd fD,dPlusRaOrZeroAddress is $(NOTVLE) & OP=50 & fD & dPlusRaOrZeroAddress +{ + fD = *:8(dPlusRaOrZeroAddress); +} + +#lfdu fr0,8(r2) 0xcc 02 00 08 +:lfdu fD,dPlusRaAddress is $(NOTVLE) & OP=51 & fD & dPlusRaAddress & A +{ + ea:$(REGISTER_SIZE) = dPlusRaAddress; + fD = *:8(ea); + A = ea; +} +#lfdux fr0,r2,r0 0x7c 02 04 ee +:lfdux fD,A,B is $(NOTVLE) & OP=31 & fD & A & B & XOP_1_10=631 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = A+B; + fD = *:8(ea); + A = ea; +} +#lfdx fr0,r2,r0 0x7c 02 04 ae +:lfdx fD,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & fD & RA_OR_ZERO & B & XOP_1_10=599 & BIT_0=0 +{ + fD = *:8(RA_OR_ZERO+B); +} + +#lfs fr0,8(r2) 0xc0 02 00 08 +:lfs fD,dPlusRaOrZeroAddress is $(NOTVLE) & OP=48 & fD & dPlusRaOrZeroAddress +{ + fD = float2float(*:4(dPlusRaOrZeroAddress)); +} +#lfsu fr0,8(r2) 0xc0 02 00 08 +:lfsu fD,dPlusRaAddress is $(NOTVLE) & OP=49 & fD & dPlusRaAddress & A +{ + ea:$(REGISTER_SIZE) = dPlusRaAddress; + fD = float2float(*:4(ea)); + A = ea; +} + +#lfsux fr0,r2,r0 0x7c 02 04 6e +:lfsux fD,A,B is $(NOTVLE) & OP=31 & fD & A & B & XOP_1_10=567 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = A+B; + fD = float2float(*:4(ea)); + A = ea; +} +#lfsx fr0,r2,r0 0x7c 02 04 2e +:lfsx fD,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & fD & RA_OR_ZERO & B & XOP_1_10=535 & BIT_0=0 +{ + fD = float2float(*:4(RA_OR_ZERO+B)); +} +#lha r0,4(0) 0xa8 00 00 04 +#lha r0,4(r2) 0xa8 02 00 04 +:lha D,dPlusRaOrZeroAddress is $(NOTVLE) & OP=42 & D & dPlusRaOrZeroAddress +{ + D = sext(*:2(dPlusRaOrZeroAddress)); + +} +#lhau r0,8(r2) 0xac 02 00 08 +:lhau D,dPlusRaAddress is $(NOTVLE) & OP=43 & D & dPlusRaAddress & A +{ + ea:$(REGISTER_SIZE) = dPlusRaAddress; + D = sext(*:2(ea)); + A = ea; +} +#lhaux r0,r2,r0 0x7c 02 02 ee +:lhaux D,A,B is OP=31 & D & A & B & XOP_1_10=375 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = A+B; + D = sext(*:2(ea)); + A = ea; +} +#lhax r0,r2,r0 0x7c 02 02 ae +:lhax D,RA_OR_ZERO,B is OP=31 & D & RA_OR_ZERO & B & XOP_1_10=343 & BIT_0=0 +{ + D = sext(*:2(RA_OR_ZERO+B)); +} + +#lhbrx r0,r2,r0 0x7c 02 06 2c +:lhbrx D,RA_OR_ZERO,B is OP=31 & D & RA_OR_ZERO & B & XOP_1_10=790 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO+B; + tmp:$(REGISTER_SIZE) = zext(*:1(ea+1)) << 8; + D = tmp | zext(*:1(ea)); +} + +#lhz r0,4(0) 0xa0 00 00 04 +#lhz r0,4(r2) 0xa0 02 00 04 +:lhz D,dPlusRaOrZeroAddress is $(NOTVLE) & OP=40 & D & dPlusRaOrZeroAddress +{ + D = zext(*:2(dPlusRaOrZeroAddress)); + +} + +#lhzu r0,4(r2) 0xa4 02 00 04 +:lhzu D,dPlusRaAddress is $(NOTVLE) & OP=41 & D & dPlusRaAddress & A +{ + ea:$(REGISTER_SIZE) = dPlusRaAddress; + D = zext(*:2(ea)); + A = ea; +} + +#lhzux r0,r2,r0 0x7c 02 02 6e +:lhzux D,A,B is OP=31 & D & A & B & XOP_1_10=311 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = A+B; + D = zext(*:2(ea)); + A = ea; +} +#lhzx r0,r2,r0 0x7c 02 02 2e +:lhzx D,RA_OR_ZERO,B is OP=31 & D & RA_OR_ZERO & B & XOP_1_10=279 & BIT_0=0 +{ + D = zext(*:2(RA_OR_ZERO+B)); +} + +# big stuffs +@include "lmwInstructions.sinc" + +@include "lswInstructions.sinc" + +#lswx r0,0,r0 0x7c 00 3c 2a +#lswx r0,r2,40 0x7c 02 3c 2a +define pcodeop lswxOp; +:lswx D,RA_OR_ZERO,B is OP=31 & D & RA_OR_ZERO & NB & BITS_21_25 & B & XOP_1_10=533 & BIT_0=0 +{ + D = lswxOp(D,RA_OR_ZERO,B); +} +@ifdef BIT_64 +#lwa r0,8(r2) 0xe8 02 00 0a +:lwa D,dsPlusRaOrZeroAddress is $(NOTVLE) & OP=58 & D & dsPlusRaOrZeroAddress & BITS_0_1=2 +{ + D = sext(*:4(dsPlusRaOrZeroAddress)); +} +@endif + +#lwarx r0,r0,r0 0x7c 00 00 28 +:lwarx D,RA_OR_ZERO,B is OP=31 & D & RA_OR_ZERO & B & XOP_1_10=20 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO+B; + #RESERVE = 1; + #RESERVE_ADDRSS:$(REGISTER_SIZE) = ea; +@ifdef BIT_64 + D = zext(*:4(ea)); +@else + D = *:4(ea); +@endif +} + +@ifdef BIT_64 +#lwaux r0,r2,r0 0x7c 02 02 ea +:lwaux D,A,B is OP=31 & D & A & B & XOP_1_10=373 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = A+B; + D = sext(*:4(ea)); + A = ea; +} +#lwax r0,r2,r0 0x7c 02 02 aa +:lwax D,RA_OR_ZERO,B is OP=31 & D & RA_OR_ZERO & B & XOP_1_10=341 & BIT_0=0 +{ + D = sext(*:4(RA_OR_ZERO)); +} +@endif + +#lwbrx r0,r2,r0 0x7c 02 04 2c +:lwbrx D,RA_OR_ZERO,B is OP=31 & D & RA_OR_ZERO & B & XOP_1_10=534 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO+B; + tmp1:$(REGISTER_SIZE) = zext(*:1(ea+3)) << 24; + tmp2:$(REGISTER_SIZE) = zext(*:1(ea+2)) << 16; + tmp3:$(REGISTER_SIZE) = zext(*:1(ea+1)) << 8; + D = tmp1 | tmp2 | tmp3 | zext(*:1(ea)); +} +#lwz r0,4(0) 0x80 00 00 04 +#lwz r0,4(r2) 0x80 02 00 04 +:lwz D,dPlusRaOrZeroAddress is $(NOTVLE) & OP=32 & D & dPlusRaOrZeroAddress +{ +@ifdef BIT_64 + D = zext(*:4(dPlusRaOrZeroAddress)); +@else + D = *:4(dPlusRaOrZeroAddress); +@endif +} + +#lwzu r0,4(r2) 0x84 02 00 04 +:lwzu D,dPlusRaAddress is $(NOTVLE) & OP=33 & D & dPlusRaAddress & A +{ + ea:$(REGISTER_SIZE) = dPlusRaAddress; +@ifdef BIT_64 + D = zext(*:4(ea)); +@else + D = *:4(ea); +@endif + A = ea; +} + +#lwzux r0,r2,r0 0x7c 02 00 6e +:lwzux D,A,B is OP=31 & D & A & B & XOP_1_10=55 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = A+B; +@ifdef BIT_64 + D = zext(*:4(ea)); +@else + D = *:4(ea); +@endif + A = ea; + +} +#lwzx r0,r2,r0 0x7c 02 00 2e +:lwzx D,RA_OR_ZERO,B is OP=31 & D & RA_OR_ZERO & B & XOP_1_10=23 & BIT_0=0 +{ +@ifdef BIT_64 + D = zext(*:4(RA_OR_ZERO+B)); +@else + D = *:4(RA_OR_ZERO+B); +@endif +} + +#macchw r0,r0,r0 0x10 00 01 58 +:macchw D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=172 & Rc=0 +{ + D = macchw(D, A, B); +} + +#macchw. r0,r0,r0 0x10 00 01 59 +:macchw. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=172 & Rc=1 +{ + D = macchw(D, A, B); + cr0flags(D); +} + +#macchwo r0,r0,r0 0x10 00 05 58 +:macchwo D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=172 & Rc=0 +{ + D = macchw(D, A, B); + xer_mac_update(D, A, B); +} + +@ifndef NoLegacyIntegerMultiplyAccumulate +#macchwo. r0,r0,r0 0x10 00 05 59 +:macchwo. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=172 & Rc=1 +{ + D = macchw(D, A, B); + xer_mac_update(D, A, B); + cr0flags(D); +} +@endif + +#macchws r0,r0,r0 0x10 00 01 d8 +:macchws D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=236 & Rc=0 +{ + D = macchws(D, A, B); +} + +#macchws. r0,r0,r0 0x10 00 01 d9 +:macchws. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=236 & Rc=1 +{ + D = macchws(D, A, B); + cr0flags(D); +} + +@ifndef NoLegacyIntegerMultiplyAccumulate +#macchwso r0,r0,r0 0x10 00 05 d8 +:macchwso D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=236 & Rc=0 +{ + D = macchws(D, A, B); + xer_mac_update(D, A, B); +} +@endif + +@ifndef NoLegacyIntegerMultiplyAccumulate +#macchwso. r0,r0,r0 0x10 00 05 d9 +:macchwso. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=236 & Rc=1 +{ + D = macchws(D, A, B); + xer_mac_update(D, A, B); + cr0flags(D); +} +@endif + +#macchwsu r0,r0,r0 0x10 00 01 98 +:macchwsu D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=204 & Rc=0 +{ + D = macchwsu(D, A, B); +} + +#macchwsu. r0,r0,r0 0x10 00 01 99 +:macchwsu. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=204 & Rc=1 +{ + D = macchwsu(D, A, B); + cr0flags(D); +} + +#macchwsuo r0,r0,r0 0x10 00 05 98 +:macchwsuo D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=204 & Rc=0 +{ + D = macchwsu(D, A, B); + xer_mac_update(D, A, B); +} + +#macchwsuo. r0,r0,r0 0x10 00 05 99 +:macchwsuo. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=204 & Rc=1 +{ + D = macchwsu(D, A, B); + xer_mac_update(D, A, B); + cr0flags(D); +} + +#macchwu r0,r0,r0 0x10 00 01 18 +:macchwu D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=140 & Rc=0 +{ + D = macchwu(D, A, B); +} + +#macchwu. r0,r0,r0 0x10 00 01 19 +:macchwu. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=140 & Rc=1 +{ + D = macchwu(D, A, B); + cr0flags(D); +} + +#macchwuo r0,r0,r0 0x10 00 05 18 +:macchwuo D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=140 & Rc=0 +{ + D = macchwu(D, A, B); + xer_mac_update(D, A, B); +} + +#macchwuo. r0,r0,r0 0x10 00 05 19 +:macchwuo. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=140 & Rc=1 +{ + D = macchwu(D, A, B); + xer_mac_update(D, A, B); + cr0flags(D); +} + + +#machhw r0,r0,r0 0x10 00 00 58 +:machhw D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=44 & Rc=0 +{ + D = machhw(D, A, B); +} + +#machhw. r0,r0,r0 0x10 00 00 59 +:machhw. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=44 & Rc=1 +{ + D = machhw(D, A, B); + cr0flags(D); +} + +@ifndef NoLegacyIntegerMultiplyAccumulate +#machhwo r0,r0,r0 0x10 00 04 58 +:machhwo D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=44 & Rc=0 +{ + D = machhw(D, A, B); + xer_mac_update(D, A, B); +} +@endif + +@ifndef NoLegacyIntegerMultiplyAccumulate +#machhwo. r0,r0,r0 0x10 00 04 59 +:machhwo. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=44 & Rc=1 +{ + D = machhw(D, A, B); + xer_mac_update(D, A, B); + cr0flags(D); +} +@endif + +#machhws r0,r0,r0 0x10 00 00 d8 +:machhws D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=108 & Rc=0 +{ + D = machhws(D, A, B); +} + +#machhws. r0,r0,r0 0x10 00 00 d9 +:machhws. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=108 & Rc=1 +{ + D = machhws(D, A, B); + cr0flags(D); +} + +#machhwso r0,r0,r0 0x10 00 04 d8 +:machhwso D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=108 & Rc=0 +{ + D = machhws(D, A, B); + xer_mac_update(D, A, B); +} + +#machhwso. r0,r0,r0 0x10 00 04 d9 +:machhwso. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=108 & Rc=1 +{ + D = machhws(D, A, B); + xer_mac_update(D, A, B); + cr0flags(D); +} + +#machhwsu r0,r0,r0 0x10 00 00 98 +:machhwsu D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=76 & Rc=0 +{ + D = machhwsu(D, A, B); +} + +#machhwsu. r0,r0,r0 0x10 00 00 99 +:machhwsu. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=76 & Rc=1 +{ + D = machhwsu(D, A, B); + cr0flags(D); +} + +#machhwsuo r0,r0,r0 0x10 00 04 98 +:machhwsuo D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=76 & Rc=0 +{ + D = machhwsu(D, A, B); + xer_mac_update(D, A, B); +} + +#machhwsuo. r0,r0,r0 0x10 00 04 99 +:machhwsuo. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=76 & Rc=1 +{ + D = machhwsu(D, A, B); + xer_mac_update(D, A, B); + cr0flags(D); +} + +#machhwu r0,r0,r0 0x10 00 00 18 +:machhwu D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=12 & Rc=0 +{ + D = machhwu(D, A, B); +} + +#machhwu. r0,r0,r0 0x10 00 00 19 +:machhwu. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=12 & Rc=1 +{ + D = machhwu(D, A, B); + cr0flags(D); +} + +#machhwuo r0,r0,r0 0x10 00 04 18 +:machhwuo D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=12 & Rc=0 +{ + D = machhwu(D, A, B); + xer_mac_update(D, A, B); +} + +#machhwuo. r0,r0,r0 0x10 00 04 19 +:machhwuo. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=12 & Rc=1 +{ + D = machhwu(D, A, B); + xer_mac_update(D, A, B); + cr0flags(D); +} + + +#maclhw r0,r0,r0 0x10 00 03 58 +:maclhw D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=428 & Rc=0 +{ + D = maclhw(D, A, B); +} + +#maclhw. r0,r0,r0 0x10 00 03 59 +:maclhw. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=428 & Rc=1 +{ + D = maclhw(D, A, B); + cr0flags(D); +} + +#maclhwo r0,r0,r0 0x10 00 07 58 +:maclhwo D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=428 & Rc=0 +{ + D = maclhw(D, A, B); + xer_mac_update(D, A, B); +} + +#maclhwo. r0,r0,r0 0x10 00 07 59 +:maclhwo. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=428 & Rc=1 +{ + D = maclhw(D, A, B); + xer_mac_update(D, A, B); + cr0flags(D); +} + +#maclhws r0,r0,r0 0x10 00 03 d8 +:maclhws D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=492 & Rc=0 +{ + D = maclhws(D, A, B); +} + +#maclhws. r0,r0,r0 0x10 00 03 d9 +:maclhws. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=492 & Rc=1 +{ + D = maclhws(D, A, B); + cr0flags(D); +} + +#maclhwso r0,r0,r0 0x10 00 07 d8 +:maclhwso D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=492 & Rc=0 +{ + D = maclhws(D, A, B); + xer_mac_update(D, A, B); +} + +#maclhwso. r0,r0,r0 0x10 00 07 d9 +:maclhwso. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=492 & Rc=1 +{ + D = maclhws(D, A, B); + xer_mac_update(D, A, B); + cr0flags(D); +} + +#maclhwsu r0,r0,r0 0x10 00 03 98 +:maclhwsu D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=460 & Rc=0 +{ + D = maclhwsu(D, A, B); +} + +#maclhwsu. r0,r0,r0 0x10 00 03 99 +:maclhwsu. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=460 & Rc=1 +{ + D = maclhwsu(D, A, B); + cr0flags(D); +} + +#maclhwsuo r0,r0,r0 0x10 00 07 98 +:maclhwsuo D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=460 & Rc=0 +{ + D = maclhwsu(D, A, B); + xer_mac_update(D, A, B); +} + +#maclhwsuo. r0,r0,r0 0x10 00 07 99 +:maclhwsuo. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=460 & Rc=1 +{ + D = maclhwsu(D, A, B); + xer_mac_update(D, A, B); + cr0flags(D); +} + +@ifndef NoLegacyIntegerMultiplyAccumulate +#maclhwu r0,r0,r0 0x10 00 03 18 +:maclhwu D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=396 & Rc=0 +{ + D = maclhwu(D, A, B); +} +@endif + +@ifndef NoLegacyIntegerMultiplyAccumulate +#maclhwu. r0,r0,r0 0x10 00 03 19 +:maclhwu. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=396 & Rc=1 +{ + D = maclhwu(D, A, B); + cr0flags(D); +} +@endif + +#maclhwuo r0,r0,r0 0x10 00 07 18 +:maclhwuo D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=396 & Rc=0 +{ + D = maclhwu(D, A, B); + xer_mac_update(D, A, B); +} + +#maclhwuo. r0,r0,r0 0x10 00 07 19 +:maclhwuo. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=396 & Rc=1 +{ + D = maclhwu(D, A, B); + xer_mac_update(D, A, B); + cr0flags(D); +} + +#mulchw r0,r0,r0 0x10 00 01 50 +:mulchw D,A,B is OP=4 & D & A & B & XOP_1_10=168 & Rc=0 +{ + D = mulchw(D, A, B); +} + +#mulchw. r0,r0,r0 0x10 00 01 51 +:mulchw. D,A,B is OP=4 & D & A & B & XOP_1_10=168 & Rc=1 +{ + D = mulchw(D, A, B); + cr0flags(D); +} + +#mulchwu r0,r0,r0 0x10 00 01 10 +:mulchwu D,A,B is OP=4 & D & A & B & XOP_1_10=136 & Rc=0 +{ + D = mulchwu(D, A, B); +} + +#mulchwu. r0,r0,r0 0x10 00 01 11 +:mulchwu. D,A,B is OP=4 & D & A & B & XOP_1_10=136 & Rc=1 +{ + D = mulchwu(D, A, B); + cr0flags(D); +} + +#mulhhw r0,r0,r0 0x10 00 00 50 +:mulhhw D,A,B is OP=4 & D & A & B & XOP_1_10=40 & Rc=0 +{ + D = mulhhw(D, A, B); +} + +#mulhhw. r0,r0,r0 0x10 00 00 51 +:mulhhw. D,A,B is OP=4 & D & A & B & XOP_1_10=40 & Rc=1 +{ + D = mulhhw(D, A, B); + cr0flags(D); +} + +#mulhhwu r0,r0,r0 0x10 00 00 10 +:mulhhwu D,A,B is OP=4 & D & A & B & XOP_1_10=8 & Rc=0 +{ + D = mulhhwu(D, A, B); +} + +#mulhhwu. r0,r0,r0 0x10 00 00 11 +:mulhhwu. D,A,B is OP=4 & D & A & B & XOP_1_10=8 & Rc=1 +{ + D = mulhhwu(D, A, B); + cr0flags(D); +} + +#mullhw r0,r0,r0 0x10 00 03 50 +:mullhw D,A,B is OP=4 & D & A & B & XOP_1_10=424 & Rc=0 +{ + D = mullhw(D, A, B); +} + +#mullhw. r0,r0,r0 0x10 00 03 51 +:mullhw. D,A,B is OP=4 & D & A & B & XOP_1_10=424 & Rc=1 +{ + D = mullhw(D, A, B); + cr0flags(D); +} + +@ifndef NoLegacyIntegerMultiplyAccumulate +# mulhwu r0,r0,r0 0x10 00 03 10 +:mullhwu D,A,B is OP=4 & D & A & B & XOP_1_10=392 & Rc=0 +{ + D = mullhwu(D, A, B); +} +@endif + +@ifndef NoLegacyIntegerMultiplyAccumulate +#mullhwu. r0,r0,r0 0x10 00 03 11 +:mullhwu. D,A,B is OP=4 & D & A & B & XOP_1_10=392 & Rc=1 +{ + D = mullhwu(D, A, B); + cr0flags(D); +} +@endif + +#nmacchw r0,r0,r0 0x10 00 01 5c +:nmacchw D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=174 & Rc=0 +{ + D = nmacchw(D, A, B); +} + +#nmacchw. r0,r0,r0 0x10 00 01 5d +:nmacchw. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=174 & Rc=1 +{ + D = nmacchw(D, A, B); + cr0flags(D); +} + +#nmacchwo r0,r0,r0 0x10 00 05 5c +:nmacchwo D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=174 & Rc=0 +{ + D = nmacchw(D, A, B); + xer_mac_update(D, A, B); +} + +#nmacchwo. r0,r0,r0 0x10 00 05 5d +:nmacchwo. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=174 & Rc=1 +{ + D = nmacchw(D, A, B); + xer_mac_update(D, A, B); + cr0flags(D); +} + +#nmacchws r0,r0,r0 0x10 00 01 dc +:nmacchws D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=238 & Rc=0 +{ + D = nmacchws(D, A, B); +} + +#nmacchws. r0,r0,r0 0x10 00 01 dd +:nmacchws. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=238 & Rc=1 +{ + D = nmacchws(D, A, B); + cr0flags(D); +} + +#nmacchwso r0,r0,r0 0x10 00 05 dc +:nmacchwso D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=238 & Rc=0 +{ + D = nmacchws(D, A, B); + xer_mac_update(D, A, B); +} + +#nmacchwso. r0,r0,r0 0x10 00 05 dd +:nmacchwso. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=238 & Rc=1 +{ + D = nmacchws(D, A, B); + xer_mac_update(D, A, B); + cr0flags(D); +} + +#nmachhw r0,r0,r0 0x10 00 00 5c +:nmachhw D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=46 & Rc=0 +{ + D = nmachhw(D, A, B); +} + +#nmachhw. r0,r0,r0 0x10 00 00 5d +:nmachhw. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=46 & Rc=1 +{ + D = nmachhw(D, A, B); + cr0flags(D); +} + +#nmachhwo r0,r0,r0 0x10 00 04 5c +:nmachhwo D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=46 & Rc=0 +{ + D = nmachhw(D, A, B); + xer_mac_update(D, A, B); +} + +#nmachhwo. r0,r0,r0 0x10 00 04 5d +:nmachhwo. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=46 & Rc=1 +{ + D = nmachhw(D, A, B); + xer_mac_update(D, A, B); + cr0flags(D); +} + +#nmachhws r0,r0,r0 0x10 00 00 dc +:nmachhws D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=110 & Rc=0 +{ + D = nmachhws(D, A, B); +} + +#nmachhws. r0,r0,r0 0x10 00 00 dd +:nmachhws. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=110 & Rc=1 +{ + D = nmachhws(D, A, B); + cr0flags(D); +} + +#nmachhwso r0,r0,r0 0x10 00 04 dc +:nmachhwso D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=110 & Rc=0 +{ + D = nmachhws(D, A, B); + xer_mac_update(D, A, B); +} + +#nmachhwso. r0,r0,r0 0x10 00 04 dd +:nmachhwso. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=110 & Rc=1 +{ + D = nmachhws(D, A, B); + xer_mac_update(D, A, B); + cr0flags(D); +} + +#nmaclhw r0,r0,r0 0x10 00 03 5c +:nmaclhw D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=430 & Rc=0 +{ + D = nmaclhw(D, A, B); +} + +#nmaclhw. r0,r0,r0 0x10 00 03 5d +:nmaclhw. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=430 & Rc=1 +{ + D = nmaclhw(D, A, B); + cr0flags(D); +} + +#nmaclhwo r0,r0,r0 0x10 00 07 5c +:nmaclhwo D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=430 & Rc=0 +{ + D = nmaclhw(D, A, B); + xer_mac_update(D, A, B); +} + +#nmaclhwo. r0,r0,r0 0x10 00 07 5d +:nmaclhwo. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=430 & Rc=1 +{ + D = nmaclhw(D, A, B); + xer_mac_update(D, A, B); + cr0flags(D); +} + +#nmaclhws r0,r0,r0 0x10 00 03 dc +:nmaclhws D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=494 & Rc=0 +{ + D = nmaclhws(D, A, B); +} + +#nmaclhws. r0,r0,r0 0x10 00 03 dd +:nmaclhws. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=494 & Rc=1 +{ + D = nmaclhws(D, A, B); + cr0flags(D); +} + +#nmaclhwso r0,r0,r0 0x10 00 07 dc +:nmaclhwso D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=494 & Rc=0 +{ + D = nmaclhws(D, A, B); + xer_mac_update(D, A, B); +} + +#nmaclhwso. r0,r0,r0 0x10 00 07 dd +:nmaclhwso. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=494 & Rc=1 +{ + D = nmaclhws(D, A, B); + xer_mac_update(D, A, B); + cr0flags(D); +} + +#mcrf cr0,cr0 0x4c 00 00 00 +:mcrf CRFD,CRFS is $(NOTVLE) & OP=19 & CRFD & BITS_21_22=0 & CRFS & BITS_0_17=0 +{ + CRFD = CRFS; +} + +#mcrfs cr0,cr0 0xfc 00 00 80 +:mcrfs CRFD,CRFS is $(NOTVLE) & OP=63 & CRFD & FPSCR_CRFS & BITS_21_22=0 & CRFS & BITS_11_17=0 & XOP_1_10=64 & BIT_0=0 +{ + CRFD = FPSCR_CRFS; +} + +#mcrxr cr0 0x7c 00 04 00 +:mcrxr CRFD is OP=31 & CRFD & BITS_11_22=0 & XOP_1_10=512 & BIT_0=0 +{ + CRFD = (xer_so & 1) << 3 | (xer_ov & 1) << 2 | (xer_ca & 1) << 1; + xer_so = 0; + xer_ov = 0; + xer_ca = 0; +} + +#mfcr r0 0x7c 00 00 26 +:mfcr D is OP=31 & D & BITS_11_20=0 & XOP_1_10=19 & BIT_0=0 +{ + tmp:4 = zext(cr0 & 0xf) << 28 | + zext(cr1 & 0xf) << 24 | + zext(cr2 & 0xf) << 20 | + zext(cr3 & 0xf) << 16 | + zext(cr4 & 0xf) << 12 | + zext(cr5 & 0xf) << 8 | + zext(cr6 & 0xf) << 4 | + zext(cr7 & 0xf); +@ifdef BIT_64 + D = zext(tmp); +@else + D = tmp; +@endif +} + +#mfocrf D,cr1 0x7c 31 00 26 +:mfocrf D,CRM_CR is OP=31 & D & BIT_20=1 & CRM_CR & BIT_11 & XOP_1_10=19 & BIT_0=0 +{ +@ifdef BIT_64 + D = zext(CRM_CR); +@else + D = CRM_CR; +@endif +} + +#mffs fD 0xfc 00 04 8e +:mffs fD is $(NOTVLE) & OP=63 & fD & BITS_11_20=0 & XOP_1_10=583 & Rc=0 +{ + tmp:4 = 0; + packFPSCR(tmp); + fD = zext(tmp); +} + +#mffs. fD 0xfc 00 04 8f +:mffs. fD is $(NOTVLE) & OP=63 & fD & BITS_11_20=0 & XOP_1_10=583 & Rc=1 +{ + tmp:4 = 0; + packFPSCR(tmp); + fD = zext(tmp); + cr1flags(); +} + +### is this pcode correct on 64-bit bridge? +#mfsr r0,r0 0x7c 00 04 a6 +:mfsr D,B is $(NOTVLE) & OP=31 & D & SR & BIT_20=0 & B & BITS_11_15=0 & XOP_1_10=595 & BIT_0=0 +{ +@ifdef BIT_64 + D = zext(SR); +@else + D = SR; +@endif +} +#mfsrin r0,r0 0x7c 00 05 26 +:mfsrin D,B is $(NOTVLE) & OP=31 & D & BITS_16_20=0 & B & XOP_1_10=659 & BIT_0=0 +{ +@ifdef BIT_64 + tmp:4 = (B:4 >> 28); +@else + tmp:$(REGISTER_SIZE) = (B >> 28); +@endif + D = *[register]:4 ($(SEG_REGISTER_BASE)+tmp); +} + +#mtcrf 10,r0 0x7c 01 01 20 +:mtcrf CRM,S is OP=31 & S & BIT_20=0 & CRM & CRM0 & CRM1 & CRM2 & CRM3 & CRM4 & CRM5 & CRM6 & CRM7 & BIT_11=0 & XOP_1_10=144 & BIT_0=0 +{ + tmp:$(REGISTER_SIZE) = (S >> 28) & 0xf; + cr0 = (cr0 * (CRM0:1 == 0)) | (tmp:1 * (CRM0:1 == 1)); + + tmp = (S >> 24) & 0xf; + cr1 = (cr1 * (CRM1:1 == 0)) | (tmp:1 * (CRM1:1 == 1)); + + tmp = (S >> 20) & 0xf; + cr2 = (cr2 * (CRM2:1 == 0)) | (tmp:1 * (CRM2:1 == 1)); + + tmp = (S >> 16) & 0xf; + cr3 = (cr3 * (CRM3:1 == 0)) | (tmp:1 * (CRM3:1 == 1)); + + tmp = (S >> 12) & 0xf; + cr4 = (cr4 * (CRM4:1 == 0)) | (tmp:1 * (CRM4:1 == 1)); + + tmp = (S >> 8) & 0xf; + cr5 = (cr5 * (CRM5:1 == 0)) | (tmp:1 * (CRM5:1 == 1)); + + tmp = (S >> 4) & 0xf; + cr6 = (cr6 * (CRM6:1 == 0)) | (tmp:1 * (CRM6:1 == 1)); + + tmp = S & 0xf; + cr7 = (cr7 * (CRM7:1 == 0)) | (tmp:1 * (CRM7:1 == 1)); +} + +#mtfsb0 fp_ux 0xfc 80 00 8c +:mtfsb0 CRBD is $(NOTVLE) & OP=63 & CRBD & BITS_11_20=0 & XOP_1_10=70 & Rc=0 +{ + CRBD = 0; +} +#mtfsb0. fp_ux 0xfc 80 00 8d +:mtfsb0. CRBD is $(NOTVLE) & OP=63 & CRBD & BITS_11_20=0 & XOP_1_10=70 & Rc=1 +{ + CRBD = 0; + cr1flags(); +} +#mtfsb1 fp_ux 0xfc 80 00 4c +:mtfsb1 CRBD is $(NOTVLE) & OP=63 & CRBD & BITS_11_20=0 & XOP_1_10=38 & Rc=0 +{ + CRBD = 1; +} +#mtfsb1. fp_ux 0xfc 80 00 4d +:mtfsb1. CRBD is $(NOTVLE) & OP=63 & CRBD & BITS_11_20=0 & XOP_1_10=38 & Rc=1 +{ + CRBD = 1; +} + +#mtfsf 10,fr0 0xfc 00 05 8e +:mtfsf FM,fB is $(NOTVLE) & OP=63 & BIT_25=0 & FM & FM0 & FM1 & FM2 & FM3 & FM4 & FM5 & FM6 & FM7 & BIT_16=0 & fB & XOP_1_10=711 & Rc=0 +{ + tmp:4 = 0; + packFPSCR(tmp); + + mask0:4 = zext((FM0:1 == 1)* 0xf) << 28; + mask1:4 = zext((FM1:1 == 1)* 0xf) << 24; + mask2:4 = zext((FM2:1 == 1)* 0xf) << 20; + mask3:4 = zext((FM3:1 == 1)* 0xf) << 16; + mask4:4 = zext((FM4:1 == 1)* 0xf) << 12; + mask5:4 = zext((FM5:1 == 1)* 0xf) << 8; + mask6:4 = zext((FM6:1 == 1)* 0xf) << 4; + mask7:4 = zext((FM7:1 == 1)* 0xf); + + mask:4 = mask0 | mask1 | mask2 | mask3 | mask4 | mask5 | mask6 | mask7; + + tmp1:4 = fB:4; + tmp2:4 = (tmp & ~mask) | (tmp1 & mask); + unpackFPSCR(tmp2); +} + +#mtfsf. 10,fr0 0xfc 00 05 8f +:mtfsf. FM,fB is $(NOTVLE) & OP=63 & BIT_25=0 & FM & FM0 & FM1 & FM2 & FM3 & FM4 & FM5 & FM6 & FM7 & BIT_16=0 & fB & XOP_1_10=711 & Rc=1 +{ + tmp:4 = 0; + packFPSCR(tmp); + + mask0:4 = zext((FM0:1 == 1)* 0xf) << 28; + mask1:4 = zext((FM1:1 == 1)* 0xf) << 24; + mask2:4 = zext((FM2:1 == 1)* 0xf) << 20; + mask3:4 = zext((FM3:1 == 1)* 0xf) << 16; + mask4:4 = zext((FM4:1 == 1)* 0xf) << 12; + mask5:4 = zext((FM5:1 == 1)* 0xf) << 8; + mask6:4 = zext((FM6:1 == 1)* 0xf) << 4; + mask7:4 = zext((FM7:1 == 1)* 0xf); + + mask:4 = mask0 | mask1 | mask2 | mask3 | mask4 | mask5 | mask6 | mask7; + + tmp1:4 = fB:4; + tmp2:4 = (tmp & ~mask) | (tmp1 & mask); + unpackFPSCR(tmp2); + cr1flags(); +} + +#mtfsfi 10,3 0xfc 00 01 0c +:mtfsfi crfD,IMM is $(NOTVLE) & OP=63 & crfD & BITS_16_22=0 & IMM & BIT_11=0 & XOP_1_10=134 & Rc=0 +{ + tmp:4 = 0; + packFPSCR(tmp); + shift:1 = 28-(crfD*4); + mask:4 = 0xf << shift; + tmp1:4 = IMM << shift; + tmp2:4 = (tmp & ~mask) | tmp1; + unpackFPSCR(tmp2); +} + +#mtfsfi. 10,3 0xfc 00 01 0d +:mtfsfi. crfD,IMM is $(NOTVLE) & OP=63 & crfD & BITS_16_22=0 & IMM & BIT_11=0 & XOP_1_10=134 & Rc=1 +{ + tmp:4 = 0; + packFPSCR(tmp); + shift:1 = 28-(crfD*4); + mask:4 = 0xf << shift; + tmp1:4 = IMM << shift; + tmp2:4 = (tmp & ~mask) | tmp1; + unpackFPSCR(tmp2); + cr1flags(); +} + +# This instruction is not exclusive to 64 bit processors, per page 1405 of the PowerISA manual. +# Prior to the Power ISA introduction, PowerPC architecture had 32-bit versions of the MSR in 32-bit implementations. +# Since this instruction requires 64-bit processsors, it is currently restricted to 64 bit machines. +# mtmsrd varies from processor to processor. This version is consistent with PowerISA v2.07B +@ifdef BIT_64 +#mtmsrd r0,0 0x7c 00 01 64 +:mtmsrd S,0 is $(NOTVLE) & OP=31 & S & BITS_17_20=0 & MSR_L=0 & BITS_11_15=0 & XOP_1_10=178 & BIT_0=0 +{ + local bit59:$(REGISTER_SIZE) = (S >> 4) & 1; #bit 59 + local bit58:$(REGISTER_SIZE) = (S >> 5) & 1; #bit 58 + local bit49:$(REGISTER_SIZE) = (S >> 14) & 1; #bit 49 + local bit48:$(REGISTER_SIZE) = (S >> 15) & 1; #bit 48 + + local bits2931:$(REGISTER_SIZE) = zext(S[32,3]); #bits 29-31 + local mbits2931:$(REGISTER_SIZE) = zext(MSR[32,3]); #bits 29-31 + local cond = (mbits2931 != 0x2)|(bits2931 != 0); + bits2931 = (zext(cond) * bits2931) + (zext(!cond) * mbits2931); + local mask:$(REGISTER_SIZE) =0xeffffff8ffff6fce; + tmp:8 = S & mask; #preserves (RS) 0:2 4:40 42:47 49:50 52:57 60:62 + + tmp = tmp | (bits2931) << 32; + tmp = tmp | ((bit48 | bit49) << 15); # MSR 48 <- (RS) 48 | (RS) 49 + tmp = tmp | ((bit58 | bit49) << 5); # MSR 58 <- (RS) 58 | (RS) 49 + tmp = tmp | ((bit59 | bit49) << 4); # MSR 59 <- (RS) 59 | (RS) 49 + MSR = (MSR & ~mask) | tmp; +} + +#mtmsrd r0,1 0x7c 01 01 64 +:mtmsrd S,1 is $(NOTVLE) & OP=31 & S & BITS_17_20=0 & MSR_L=1 & BITS_11_15=0 & XOP_1_10=178 & BIT_0=0 +{ + mask:$(REGISTER_SIZE) = 0x8002; + MSR = (MSR & ~mask) | (S & mask); +} +@endif + +CRM_val: crmval is CRM [crmval = CRM+0;] {export *[const]:1 crmval;} +#mtocrf 10,r0 0x7c 21 01 20 +:mtocrf CRM_val,S is OP=31 & S & BIT_20=1 & CRM_val & CRM0 & CRM1 & CRM2 & CRM3 & CRM4 & CRM5 & CRM6 & CRM7 & BIT_11=0 & XOP_1_10=144 & BIT_0=0 +{ + tmp:$(REGISTER_SIZE) = (S >> 28) & 0xf; + cr0 = (cr0 * (CRM_val != 128)) | (tmp:1 * (CRM_val == 128)); + + tmp = (S >> 24) & 0xf; + cr1 = (cr1 * (CRM_val != 64)) | (tmp:1 * (CRM_val == 64)); + + tmp = (S >> 20) & 0xf; + cr2 = (cr2 * (CRM_val != 32)) | (tmp:1 * (CRM_val == 32)); + + tmp = (S >> 16) & 0xf; + cr3 = (cr3 * (CRM_val != 16)) | (tmp:1 * (CRM_val == 16)); + + tmp = (S >> 12) & 0xf; + cr4 = (cr4 * (CRM_val != 8)) | (tmp:1 * (CRM_val == 8)); + + tmp = (S >> 8) & 0xf; + cr5 = (cr5 * (CRM_val != 4)) | (tmp:1 * (CRM_val == 4)); + + tmp = (S >> 4) & 0xf; + cr6 = (cr6 * (CRM_val != 2)) | (tmp:1 * (CRM_val == 2)); + + tmp = S & 0xf; + cr7 = (cr7 * (CRM_val != 1)) | (tmp:1 * (CRM_val == 1)); +} + +### is this pcode correct on 64-bit bridge? +#mtsr sr0,r0 0x7c 00 01 a4 +:mtsr SR,S is $(NOTVLE) & OP=31 & S & SR & BIT_20=0 & B & BITS_11_15=0 & XOP_1_10=210 & BIT_0=0 +{ +@ifdef BIT_64 + SR = S:4; +@else + SR = S; +@endif +} + +#mtsrd sr0,r0 0x7c 00 0 a4 +:mtsrd SR,S is $(NOTVLE) & OP=31 & S & BIT_20=0 & SR & BITS_11_15=0 & XOP_1_10=82 & BIT_0=0 +{ + SR = S:4; +} + +#mtsrdin r0,r0 0x7c 00 00 e4 +:mtsrdin S,B is $(NOTVLE) & OP=31 & S & BITS_16_20=0 & B & XOP_1_10=114 & BIT_0=0 +{ + local tmp = (B >> 28) & 0xf; + *[register]:4 ($(SEG_REGISTER_BASE)+tmp:4) = S:4; +} + +### is this pcode correct on 64-bit bridge? +#mtsrin r0,r0 0x7c 00 01 e4 +:mtsrin S,B is $(NOTVLE) & OP=31 & S & BITS_16_20=0 & B & XOP_1_10=242 & BIT_0=0 +{ +@ifdef BIT_64 + tmp:4 = (B:4 >> 28); +@else + tmp:$(REGISTER_SIZE) = (B >> 28); +@endif + *[register]:4 ($(SEG_REGISTER_BASE)+tmp) = S; +} + +@ifdef BIT_64 +#mulhd r0,r0 0x7c 00 00 92 +:mulhd D,A,B is OP=31 & D & A & B & BIT_10=0 & XOP_1_9=73 & Rc=0 +{ + tmp:16 = sext(A) * sext(B); + D = tmp(8); +} +#mulhd. r0,r0 0x7c 00 00 93 +:mulhd. D,A,B is OP=31 & D & A & B & BIT_10=0 & XOP_1_9=73 & Rc=1 +{ + tmp:16 = sext(A) * sext(B); + D = tmp(8); + cr0flags(D); +} + +#mulhdu r0,r0 0x7c 00 00 12 +:mulhdu D,A,B is OP=31 & D & A & B & BIT_10=0 & XOP_1_9=9 & Rc=0 +{ + tmp:16 = zext(A) * zext(B); + D = tmp(8); +} +#mulhdu. r0,r0 0x7c 00 00 13 +:mulhdu. D,A,B is OP=31 & D & A & B & BIT_10=0 & XOP_1_9=9 & Rc=1 +{ + tmp:16 = zext(A) * zext(B); + D = tmp(8); + cr0flags(D); +} + +@endif + +#mulhw r0,r0,r0 0x7c 00 00 96 +:mulhw D,A,B is OP=31 & D & A & B & BIT_10=0 & XOP_1_9=75 & Rc=0 +{ +@ifdef BIT_64 + tmp:8 = sext(A:4) * sext(B:4); + tmp2:4 = tmp(4); + D = zext(tmp2); +@else + tmp:8 = sext(A) * sext(B); + D = tmp(4); +@endif +} + +#mulhw. r0,r0,r0 0x7c 00 00 97 +:mulhw. D,A,B is OP=31 & D & A & B & BIT_10=0 & XOP_1_9=75 & Rc=1 +{ +@ifdef BIT_64 + tmp:8 = sext(A:4) * sext(B:4); + tmp2:4 = tmp(4); + D = zext(tmp2); +@else + tmp:8 = sext(A) * sext(B); + D = tmp(4); +@endif + cr0flags(D); +} + +#mulhwu r0,r0,r0 0x7c 00 00 16 +:mulhwu D,A,B is OP=31 & D & A & B & BIT_10=0 & XOP_1_9=11 & Rc=0 +{ +@ifdef BIT_64 + tmp:8 = zext(A:4) * zext(B:4); + tmp2:4 = tmp(4); + D=zext(tmp2); +@else + tmp:8 = zext(A) * zext(B); + D = tmp(4); +@endif +} +#mulhwu. r0,r0,r0 0x7c 00 00 17 +:mulhwu. D,A,B is OP=31 & D & A & B & BIT_10=0 & XOP_1_9=11 & Rc=1 +{ +@ifdef BIT_64 + tmp:8 = zext(A:4) * zext(B:4); + tmp2:4 = tmp(4); + D=zext(tmp2); +@else + tmp:8 = zext(A) * zext(B); + D = tmp(4); +@endif + cr0flags(D); +} + +@ifdef BIT_64 +#mulld r0, r0, r0 0x7C 00 01 D2 +:mulld D,A,B is OP=31 & D & A & B & OE=0 & XOP_1_9=233 & Rc=0 +{ + tmp:16 = sext(A) * sext(B); + D = tmp:8; +} + +#mulld. r0, r0, r0 0x7C 00 01 D3 +:mulld. D,A,B is OP=31 & D & A & B & OE=0 & XOP_1_9=233 & Rc=1 +{ + tmp:16 = sext(A) * sext(B); + D = tmp:8; + cr0flags(D); +} + +#mulldo r0, r0, r0 0x7C 00 05 D2 +:mulldo D,A,B is OP=31 & D & A & B & OE=1 & XOP_1_9=233 & Rc=0 +{ + tmp:16 = sext(A) * sext(B); + D = tmp:8; + mulOverflow128(tmp); +} + +#mulldo. r0, r0, r0 0x7C 00 05 D3 +:mulldo. D,A,B is OP=31 & D & A & B & OE=1 & XOP_1_9=233 & Rc=1 +{ + tmp:16 = sext(A) * sext(B); + D = tmp:8; + mulOverflow128(tmp); + cr0flags(D); +} + +@endif + +#mulli r0,r0,r0 0x1C 00 00 00 +:mulli D,A,SIMM is $(NOTVLE) & OP=7 & D & A & SIMM +{ + D = A * SIMM; +} + +#mullw r0,r0,r0 0x7C 00 01 D6 +:mullw D,A,B is OP=31 & D & A & B & OE=0 & XOP_1_9=235 & Rc=0 +{ +@ifdef BIT_64 + D = sext(A:4) * sext(B:4); +@else + D = A*B; +@endif +} + +#mullw. r0,r0,r0 0x7C 00 01 D7 +:mullw. D,A,B is OP=31 & D & A & B & OE=0 & XOP_1_9=235 & Rc=1 +{ +@ifdef BIT_64 + D = sext(A:4) * sext(B:4); +@else + D = A*B; +@endif + cr0flags(D); +} + +#mullwo r0,r0,r0 0x7C 00 05 D6 +:mullwo D,A,B is OP=31 & D & A & B & OE=1 & XOP_1_9=235 & Rc=0 +{ +@ifdef BIT_64 + D = sext(A:4) * sext(B:4); + mulOverflow64(D); +@else + tmp:8 = sext(A) * sext(B); + mulOverflow64(tmp); + D = tmp:4; +@endif +} + +#mullwo. r0,r0,r0 0x7C 00 05 D7 +:mullwo. D,A,B is OP=31 & D & A & B & OE=1 & XOP_1_9=235 & Rc=1 +{ +@ifdef BIT_64 + D = sext(A:4) * sext(B:4); + mulOverflow64(D); +@else + tmp:8 = sext(A) * sext(B); + mulOverflow64(tmp); + D = tmp:4; +@endif + cr0flags(D); +} + +#nand r0,r0,r0 0x7C 00 03 B8 +:nand A,S,B is OP=31 & S & A & B & XOP_1_10=476 & Rc=0 +{ + A = ~(S & B); +} + +#nand. r0,r0,r0 0x7C 00 03 B9 +:nand. A,S,B is OP=31 & S & A & B & XOP_1_10=476 & Rc=1 +{ + A = ~(S & B); + cr0flags( A ); +} + +#neg r0,r0 0x7C 00 00 D0 +:neg D,A is OP=31 & D & A & BITS_11_15=0 & OE=0 & XOP_1_9=104 & Rc=0 +{ + D = -A; +} + +#neg. r0,r0 0x7C 00 00 D1 +:neg. D,A is OP=31 & D & A & BITS_11_15=0 & OE=0 & XOP_1_9=104 & Rc=1 +{ + D = -A; + cr0flags( D ); +} + +#nego r0,r0 0x7C 00 04 D0 +:nego D,A is $(NOTVLE) & OP=31 & D & A & BITS_11_15=0 & OE=1 & XOP_1_9=104 & Rc=0 +{ + subOverflow(A,1); + D = -A; +} + +#nego. r0,r0 0x7C 00 04 D1 +:nego. D,A is OP=31 & D & A & BITS_11_15=0 & OE=1 & XOP_1_9=104 & Rc=1 +{ + subOverflow(A,1); + D = -A; + cr0flags( D ); +} + +#nor r0,r0,r0 0x7C 00 00 F8 +:nor A,S,B is OP=31 & A & S & B & XOP_1_10=124 & Rc=0 +{ + A = ~(S | B); +} + +#nor. r0,r0,r0 0x7C 00 00 F9 +:nor. A,S,B is OP=31 & A & S & B & XOP_1_10=124 & Rc=1 +{ + A = ~(S | B); + cr0flags(A); +} + +#or r0,r0,r0 0x7C 00 03 78 +:or A,S,B is OP=31 & A & S & B & XOP_1_10=444 & Rc=0 +{ + A = (S | B); +} + +#or. r0,r0,r0 0x7C 00 03 79 +:or. A,S,B is OP=31 & A & S & B & XOP_1_10=444 & Rc=1 +{ + A = (S | B); + cr0flags(A); +} + +#orc r0,r0,r0 0x7C 00 03 38 +:orc A,S,B is OP=31 & A & S & B & XOP_1_10=412 & Rc=0 +{ + A = S | ~B; +} + +#orc. r0,r0,r0 0x7C 00 03 39 +:orc. A,S,B is OP=31 & A & S & B & XOP_1_10=412 & Rc=1 +{ + A = S | ~B; + cr0flags(A); +} + +#ori r0,r0,r0 0x60 00 00 00 +:ori A,S,UIMM is $(NOTVLE) & OP=24 & A & S & UIMM +{ + A = S | UIMM; +} + +#oris r0,r0,r0 0x64 00 00 00 +:oris A,S,UIMM is $(NOTVLE) & OP=25 & A & S & UIMM +{ + A = S | (UIMM << 16); +} + +#rfid 0x4c 00 00 24 +:rfid is $(NOTVLE) & OP=19 & BITS_11_25=0 & XOP_1_10=18 & BIT_0=0 +{ + MSR = returnFromInterrupt(MSR, SRR1); + local ra = SRR0; + return[ra]; +} + +@ifdef BIT_64 +#rldcl r0,r0,r0,0 0x78 00 00 10 +:rldcl A,S,B,MB is $(NOTVLE) & OP=30 & S & A & B & MB & XOP_1_4=8 & Rc=0 +{ + shift:$(REGISTER_SIZE) = B & 0x3f; + tmp:$(REGISTER_SIZE)=(S<>(64-shift)); + A = tmp & (0xffffffffffffffff >> MB); +} +#rldcl. r0,r0,r0,0 0x78 00 00 11 +:rldcl. A,S,B,MB is $(NOTVLE) & OP=30 & S & A & B & MB & XOP_1_4=8 & Rc=1 +{ + shift:$(REGISTER_SIZE) = B & 0x3f; + tmp:$(REGISTER_SIZE)=(S<>(64-shift)); + A = tmp & (0xffffffffffffffff >> MB); + cr0flags(A); +} +#rldcr r0,r0,r0,0 0x78 00 00 12 +:rldcr A,S,B,MB is $(NOTVLE) & OP=30 & S & A & B & MB & XOP_1_4=9 & Rc=0 & rotmask_Z +{ + shift:$(REGISTER_SIZE) = B & 0x3f; + tmp:$(REGISTER_SIZE)=(S<>(64-shift)); + A = tmp & rotmask_Z; +} +#rldcr. r0,r0,r0,0 0x78 00 00 13 +:rldcr. A,S,B,MB is $(NOTVLE) & OP=30 & S & A & B & MB & XOP_1_4=9 & Rc=1 & rotmask_Z +{ + shift:$(REGISTER_SIZE) = B & 0x3f; + tmp:$(REGISTER_SIZE)=(S<>(64-shift)); + A = tmp & rotmask_Z; + cr0flags(A); +} + +#rldic r0,r0,r0,0 0x78 00 00 08 +:rldic A,S,SH,MB is $(NOTVLE) & OP=30 & S & A & B & SH & MB & XOP_2_4=2 & Rc=0 & rotmask_SH +{ + shift:4 = SH; + tmp:$(REGISTER_SIZE)=(S<>(64-shift)); + A = tmp & rotmask_SH; +} +#rldic. r0,r0,r0,0 0x78 00 00 09 +:rldic. A,S,SH,MB is $(NOTVLE) & OP=30 & S & A & B & SH & MB & XOP_2_4=2 & Rc=1 & rotmask_SH +{ + shift:4 = SH; + tmp:$(REGISTER_SIZE)=(S<>(64-shift)); + A = tmp & rotmask_SH; + cr0flags(A); +} + +#rldicl r0,r0,r0,0 0x78 00 00 00 +:rldicl A,S,SH,MB is $(NOTVLE) & OP=30 & S & A & B & SH & MB & XOP_2_4=0 & Rc=0 +{ + shift:4 = SH; + tmp:$(REGISTER_SIZE)=(S<>(64-shift)); + A = tmp & (0xffffffffffffffff >> MB); +} +#rldicl. r0,r0,r0,0 0x78 00 00 01 +:rldicl. A,S,SH,MB is $(NOTVLE) & OP=30 & S & A & B & SH & MB & XOP_2_4=0 & Rc=1 +{ + shift:4 = SH; + tmp:$(REGISTER_SIZE)=(S<>(64-shift)); + A = tmp & (0xffffffffffffffff >> MB); + cr0flags(A); +} +#rldicr r0,r0,r0,0 0x78 00 00 04 +:rldicr A,S,SH,MB is $(NOTVLE) & OP=30 & S & A & B & SH & MB & XOP_2_4=1 & Rc=0 +{ + shift:4 = SH; + tmp:$(REGISTER_SIZE)=(S<>(64-shift)); + A = tmp & (0xffffffffffffffff << (63-MB)); +} +#rldicr. r0,r0,r0,0 0x78 00 00 05 +:rldicr. A,S,SH,MB is $(NOTVLE) & OP=30 & S & A & B & SH & MB & XOP_2_4=1 & Rc=1 +{ + shift:4 = SH; + tmp:$(REGISTER_SIZE)=(S<>(64-shift)); + A = tmp & (0xffffffffffffffff << (63-MB)); + cr0flags(A); +} +#rldimi r0,r0,r0,0 0x78 00 00 0c +:rldimi A,S,SH,MB is $(NOTVLE) & OP=30 & S & A & B & SH & MB & XOP_2_4=3 & Rc=0 & rotmask_SH +{ + shift:4 = SH; + tmp:$(REGISTER_SIZE)=(S<>(64-shift)); + A = (tmp & rotmask_SH) | (A & ~rotmask_SH); +} +#rldimi. r0,r0,r0,0 0x78 00 00 0d +:rldimi. A,S,SH,MB is $(NOTVLE) & OP=30 & S & A & B & SH & MB & XOP_2_4=3 & Rc=1 & rotmask_SH +{ + shift:4 = SH; + tmp:$(REGISTER_SIZE)=(S<>(64-shift)); + A = (tmp & rotmask_SH) | (A & ~rotmask_SH); + cr0flags(A); +} +@endif + + + +#rlwimi r0,r0,0,0,0 0x50 00 00 00 +:rlwimi A,S,SHL,MBL,ME is $(NOTVLE) & OP=20 & S & A & SHL & MBL & ME & Rc=0 & rotmask +{ + shift:1 = SHL; +@ifdef BIT_64 + tmp:$(REGISTER_SIZE) = (S << 32) | (S & 0xffffffff); + tmp2:$(REGISTER_SIZE) = (tmp<>(64-shift)); + A = (tmp2 & rotmask) | (A & ~(rotmask)); +@else + tmp = (S<>(32-shift)); + A = (tmp & rotmask) | (A & ~rotmask); +@endif +} + +#rlwimi. r0,r0,0,0,0 0x50 00 00 01 +:rlwimi. A,S,SHL,MBL,ME is $(NOTVLE) & OP=20 & S & A & SHL & MBL & ME & Rc=1 & rotmask +{ + shift:1 = SHL; +@ifdef BIT_64 + tmp:$(REGISTER_SIZE) = (S << 32) | (S & 0xffffffff); + tmp2:$(REGISTER_SIZE) = (tmp<>(64-shift)); + A = (tmp2 & rotmask) | (A & ~(rotmask)); +@else + tmp = (S<>(32-shift)); + A = (tmp & rotmask) | (A & ~rotmask); +@endif + cr0flags(A); +} + +#rlwinm r0,r0,0,0,0 0x54 00 00 00 +:rlwinm A,S,SHL,MBL,ME is $(NOTVLE) & OP=21 & S & A & SHL & MBL & ME & Rc=0 & rotmask +{ + shift:1 = SHL; +@ifdef BIT_64 + tmp:$(REGISTER_SIZE) = (S << 32) | (S & 0xffffffff); + tmp2:$(REGISTER_SIZE) = (tmp<>(64-shift)); + A = tmp2 & rotmask; +@else + tmp = (S<>(32-shift)); + A = (tmp & rotmask); +@endif +} + +#rlwinm. r0,r0,0,0,0 0x54 00 00 01 +:rlwinm. A,S,SHL,MBL,ME is $(NOTVLE) & OP=21 & S & A & SHL & MBL & ME & Rc=1 & rotmask +{ + shift:1 = SHL; +@ifdef BIT_64 + tmp:$(REGISTER_SIZE) = (S << 32) | (S & 0xffffffff); + tmp2:$(REGISTER_SIZE) = (tmp<>(64-shift)); + A = tmp2 & rotmask; +@else + tmp = (S<>(32-shift)); + A = (tmp & rotmask); +@endif + cr0flags(A); +} + +#rlwnm r0,r0,0,0,0 0x5C 00 00 00 +:rlwnm A,S,B,MBL,ME is $(NOTVLE) & OP=23 & S & A & B & MBL & ME & Rc=0 & rotmask +{ + shift:$(REGISTER_SIZE) = B & 0x1f; +@ifdef BIT_64 + tmp:$(REGISTER_SIZE) = (S << 32) | (S & 0xffffffff); + tmp2:$(REGISTER_SIZE) = (tmp<>(64-shift)); + A = tmp2 & rotmask; +@else + tmp = (S<>(32-shift)); + A = (tmp & rotmask); +@endif +} + +#rlwnm. r0,r0,0,0,0 0x5C 00 00 01 +:rlwnm. A,S,B,MBL,ME is $(NOTVLE) & OP=23 & S & A & B & MBL & ME & Rc=1 & rotmask +{ + shift:$(REGISTER_SIZE) = B & 0x1f; +@ifdef BIT_64 + tmp:$(REGISTER_SIZE) = (S << 32) | (S & 0xffffffff); + tmp2:$(REGISTER_SIZE) = (tmp<>(64-shift)); + A = tmp2 & rotmask; +@else + tmp = (S<>(32-shift)); + A = (tmp & rotmask); +@endif + cr0flags(A); +} + +#sc 0x44 00 00 02 +:sc LEV is $(NOTVLE) & OP=17 & BITS_12_25=0 & LEV & BITS_2_4=0 & BIT_1=1 & BIT_0=0 +{ + syscall(); +} + +#slbia 0x7C 00 03 E4 +:slbia is $(NOTVLE) & OP=31 & BITS_11_25=0 & XOP_1_10=498 & BIT_0=0 +{ + slbInvalidateAll(); +} + +#slbie r0 0x7C 00 03 64 +:slbie B is $(NOTVLE) & OP=31 & BITS_16_20=0 & B & XOP_1_10=434 & BIT_0=0 +{ + slbInvalidateEntry(); +} + +#slbmfee r0,r0 0x7C 00 07 26 +:slbmfee D,B is $(NOTVLE) & OP=31 & D & BITS_16_20=0 & B & XOP_1_10=915 & BIT_0=0 +{ + slbMoveFromEntryESID(); +} + +#slbmfev r0,r0 0x7C 00 06 A6 +:slbmfev D,B is $(NOTVLE) & OP=31 & D & BITS_16_20=0 & B & XOP_1_10=851 & BIT_0=0 +{ + slbMoveFromEntryVSID(); +} + +#slbmte r0,r0 0x7C 00 03 24 +:slbmte S,B is $(NOTVLE) & OP=31 & S & BITS_16_20=0 & B & XOP_1_10=402 & BIT_0=0 +{ + slbMoveToEntry(); +} + +@ifdef BIT_64 +#sld r0,r0,r0 0x7C 00 00 36 +:sld A,S,B is OP=31 & S & A & B & XOP_1_10=27 & Rc=0 +{ + A = S << (B & 0x7f); +} + +#sld. 0x7C 00 00 37 +:sld. A,S,B is OP=31 & S & A & B & XOP_1_10=27 & Rc=1 +{ + A = S << (B & 0x7f); + cr0flags(A); +} +@endif + +#slw r0,r0,r0 0x7C 00 00 30 +:slw A,S,B is OP=31 & S & A & B & XOP_1_10=24 & Rc=0 +{ +@ifdef BIT_64 + shift:4 = B:4 & 0x3f; + tmp:4 = S:4 << shift; + A = zext(tmp); +@else + shift = B & 0x3f; + A = S << shift; +@endif +} + + +#slw. r0,r0,r0 0x7C 00 00 31 +:slw. A,S,B is OP=31 & S & A & B & XOP_1_10=24 & Rc=1 +{ +@ifdef BIT_64 + shift:4 = B:4 & 0x3f; + tmp:4 = S:4 << shift; + A = zext(tmp); +@else + shift = B & 0x3f; + A = S << shift; +@endif + cr0flags(A); +} + +@ifdef BIT_64 +#srad r0,r0,r0 0x7C 00 06 34 +:srad A,S,B is OP=31 & A & S & B & XOP_1_10=794 & Rc=0 +{ + tmp:$(REGISTER_SIZE) = B & 0x7f; + shiftCarry(S,tmp); + A = S s>> tmp; +} + +#srad. r0,r0,r0 0x7C 00 06 35 +:srad. A,S,B is OP=31 & A & S & B & XOP_1_10=794 & Rc=1 +{ + tmp:$(REGISTER_SIZE) = B & 0x7f; + shiftCarry(S,tmp); + A = S s>> tmp; + cr0flags(A); +} + +#sradi r0,r0,r0 0x7C 00 06 74 +:sradi A,S,SH is OP=31 & A & S & SH & XOP_2_10=413 & Rc=0 +{ + shiftCarry(S,SH); + A = S s>> SH; +} + +#sradi. r0,r0,r0 0x7C 00 06 75 +:sradi. A,S,SH is OP=31 & A & S & SH & XOP_2_10=413 & Rc=1 +{ + shiftCarry(S,SH); + A = S s>> SH; +} + +@endif + + +#sraw r0,r0,r0 0x7C 00 06 30 +:sraw A,S,B is OP=31 & A & S & B & XOP_1_10=792 & Rc=0 +{ +@ifdef BIT_64 + shift:4 = B:4 & 0x3f; + shiftCarry(S:4,shift); + tmp2:4 = S:4 s>> shift; + A = sext(tmp2); +@else + shift = B & 0x3f; + shiftCarry(S,shift); + A = S s>> shift; +@endif +} +#sraw. r0,r0,r0 0x7C 00 06 31 +:sraw. A,S,B is OP=31 & A & S & B & XOP_1_10=792 & Rc=1 +{ +@ifdef BIT_64 + shift:4 = B:4 & 0x3f; + shiftCarry(S:4,shift); + tmp2:4 = S:4 s>> shift; + A = sext(tmp2); +@else + shift = B & 0x3f; + shiftCarry(S,shift); + A = S s>> shift; +@endif + cr0flags(A); +} + +#srawi r0,r0,r0 0x7C 00 06 70 +:srawi A,S,SHL is OP=31 & A & S & SHL & XOP_1_10=824 & Rc=0 +{ +@ifdef BIT_64 + shift:4 = SHL; + shiftCarry(S:4,shift); + tmp2:4 = S:4 s>> shift; + A = sext(tmp2); +@else + shiftCarry(S,SHL); + A = S s>> SHL; +@endif +} +#srawi. r0,r0,r0 0x7C 00 06 71 +:srawi. A,S,SHL is OP=31 & A & S & SHL & XOP_1_10=824 & Rc=1 +{ +@ifdef BIT_64 + shift:4 = SHL; + shiftCarry(S:4,shift); + tmp2:4 = S:4 s>> shift; + A = sext(tmp2); +@else + shiftCarry(S,SHL); + A = S s>> SHL; +@endif + cr0flags(A); +} + +@ifdef BIT_64 +#srd r0,r0,r0 0x7C 00 04 36 +:srd A,S,B is OP=31 & S & A & B & XOP_1_10=539 & Rc=0 +{ + A = S >> (B & 0x7f); +} + +#srd. 0x7C 00 04 37 +:srd. A,S,B is OP=31 & S & A & B & XOP_1_10=539 & Rc=1 +{ + A = S >> (B & 0x7f); + cr0flags(A); +} +@endif + +#srw r0,r0,r0 0x7C 00 04 30 +:srw A,S,B is OP=31 & S & A & B & XOP_1_10=536 & Rc=0 +{ +@ifdef BIT_64 + shift:4 = B:4 & 0x3f; + tmp:4 = S:4 >> shift; + A = zext(tmp); +@else + shift = B & 0x3f; + A = S >> shift; +@endif +} + + +#srw. r0,r0,r0 0x7C 00 04 31 +:srw. A,S,B is OP=31 & S & A & B & XOP_1_10=536 & Rc=1 +{ +@ifdef BIT_64 + shift:4 = B:4 & 0x3f; + tmp:4 = S:4 >> shift; + A = zext(tmp); +@else + shift = B & 0x3f; + A = S >> shift; +@endif + cr0flags(A); +} + + + +#stb r0,3(0) 0x98 00 00 00 +#stb r0,3(r2) 0x98 02 00 00 +:stb S,dPlusRaOrZeroAddress is $(NOTVLE) & OP=38 & S & dPlusRaOrZeroAddress +{ + *:1(dPlusRaOrZeroAddress) = S:1; +} + +#stbu r0,3(0) 0x9c 00 00 00 +#stbu r0,3(r2) 0x9c 02 00 00 +:stbu S,dPlusRaAddress is $(NOTVLE) & OP=39 & S & dPlusRaAddress & A +{ + *:1(dPlusRaAddress) = S:1; + A = dPlusRaAddress; +} + +#stbux r0,r2,r0 0x7c 00 01 ee ### WARNING the B in this definition is different from manual - I think the manual is wrong +:stbux S,A,B is OP=31 & S & A & B & XOP_1_10=247 & BIT_0=0 +{ + tmp:$(REGISTER_SIZE) = A+B; # S may be same register as A + *tmp = S:1; # So do store before updating A + A = tmp; +} + +#stbx r0,r2,r0 0x7c 00 01 ae ### WARNING the B in this definition is different from manual - I think the manual is wrong +:stbx S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=215 & BIT_0=0 +{ + *(RA_OR_ZERO+B) = S:1; +} + +@ifdef BIT_64 +#std r0,8(0) 0xf8 00 00 08 +#std r0,8(r2) 0xf8 02 00 08 +:std S,dsPlusRaOrZeroAddress is $(NOTVLE) & OP=62 & S & dsPlusRaOrZeroAddress & BITS_0_1=0 +{ + *:8(dsPlusRaOrZeroAddress) = S; +} + +#Special case when saving r2 to stack prior to function call (for inline call stub case) +#std r2,0x28(r1) +:std r2,dsPlusRaOrZeroAddress is $(NOTVLE) & OP=62 & S=2 & r2 & A=1 & SIMM_DS=0xa & dsPlusRaOrZeroAddress & BITS_0_1=0 +{ + r2Save = r2; + *:8(dsPlusRaOrZeroAddress) = r2; +} + +#stdcx. r0,8(0) 0x7c 00 01 AD +:stdcx. S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=214 & BIT_0=1 +{ + EA:$(REGISTER_SIZE) = RA_OR_ZERO + B; + if (RESERVE == 0) goto inst_next; + *[ram]:8 EA = storeDoubleWordConditionalIndexed(S,RA_OR_ZERO,B); + # set when a stwcx. or stdcx. successfully completes + cr0flags(0:$(REGISTER_SIZE)); +} + +#stdu r0,8(0) 0xf8 00 00 01 +#stdu r0,8(r2) 0xf8 02 00 01 +:stdu S,dsPlusRaAddress is $(NOTVLE) & OP=62 & S & A & dsPlusRaAddress & BITS_0_1=1 +{ + *:8(dsPlusRaAddress) = S; + A = dsPlusRaAddress; +} + +#stdux r0,r2,r0 0x7c 00 01 6a +:stdux S,A,B is OP=31 & S & A & B & XOP_1_10=181 & BIT_0=0 +{ + local ea:$(REGISTER_SIZE) = A+B; + *:8(ea) = S; + A = ea; +} + +#stdx r0,r2,r0 0x7c 00 01 2a +:stdx S,RA_OR_ZERO,B is OP=31 & S & B & RA_OR_ZERO & XOP_1_10=149 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO+B; + *:8(ea) = S; +} + +@endif + +#stfd fr0,8(0) 0xD8 00 00 08 +#stfd fr0,8(r2) 0xD8 02 00 08 +:stfd fS,dPlusRaOrZeroAddress is $(NOTVLE) & OP=54 & fS & dPlusRaOrZeroAddress +{ + *:8(dPlusRaOrZeroAddress) = fS; +} + +#stfdu fr0,8(0) 0xDC 00 00 08 +#stfdu fr0,8(r2) 0xDC 02 00 08 +:stfdu fS,dPlusRaAddress is $(NOTVLE) & OP=55 & fS & dPlusRaAddress & A +{ + ea:$(REGISTER_SIZE) = dPlusRaAddress; + *:8(ea) = fS; + A = ea; +} + +#stfdux fr0,r2,r0 0x7C 00 05 EE +:stfdux fS,A,B is $(NOTVLE) & OP=31 & fS & A & B & XOP_1_10=759 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = A+B; + *:8(ea) = fS; + A = ea; +} + +#stfdx fr0,r0,r0 0x7C 00 05 AE +:stfdx fS,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & fS & B & RA_OR_ZERO & XOP_1_10=727 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO+B; + *:8(ea) = fS; +} + +#stfiwx fr0,r0,r0 0x7C 00 07 AE +:stfiwx fS,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & fS & B & RA_OR_ZERO & XOP_1_10=983 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO+B; + *:4(ea) = fS:4; +} + +#stfs fr0,8(0) 0xD0 00 00 08 +#stfs fr0,8(r2) 0xD0 02 00 08 +:stfs fS,dPlusRaOrZeroAddress is $(NOTVLE) & OP=52 & fS & dPlusRaOrZeroAddress +{ + tmp:4 = float2float(fS); + *:4(dPlusRaOrZeroAddress) = tmp; +} + +#stfsu fr0,8(0) 0xD4 00 00 08 +#stfsu fr0,8(r2) 0xD4 02 00 08 +:stfsu fS,dPlusRaAddress is $(NOTVLE) & OP=53 & fS & dPlusRaAddress & A +{ + tmp:4 = float2float(fS); + *:4(dPlusRaAddress) = tmp; + A = dPlusRaAddress; +} + +#stfsux fr0,r0,r0 0x7C 00 05 6E +:stfsux fS,A,B is $(NOTVLE) & OP=31 & fS & B & A & XOP_1_10=695 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = A + B; + tmp:4 = float2float(fS); + *:4(ea) = tmp; + A = ea; +} + +#stfsx fr0,r0,r0 0x7C 00 05 2E +:stfsx fS,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & fS & B & RA_OR_ZERO & XOP_1_10=663 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + tmp:4 = float2float(fS); + *:4(ea) = tmp; +} + +#sth r0,r0 0xB0 00 00 00 +:sth S,dPlusRaOrZeroAddress is $(NOTVLE) & OP=44 & S & dPlusRaOrZeroAddress +{ + *:2(dPlusRaOrZeroAddress) = S:2; +} + +#sthbrx r0,r0,r0 0x7C 00 07 2C +:sthbrx S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=918 & BIT_0=0 +{ + tmp:2 = zext(S:1) <<8; + tmp2:2 = S:2 >>8; + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + *:2(ea) = tmp2 | tmp; +} + +#sthu r0,r0 0xB4 00 00 00 +:sthu S,dPlusRaAddress is $(NOTVLE) & OP=45 & S & A & dPlusRaAddress +{ + *:2(dPlusRaAddress) = S:2; + A = dPlusRaAddress; +} + +#sthux r0,r0,r0 0x7C 00 03 6E +:sthux S,A,B is OP=31 & S & A & B & XOP_1_10=439 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = A + B; + *:2(ea) = S:2; + A = ea; +} + +#sthx r0,r0,r0 0x7C 00 03 2E +:sthx S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=407 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + *:2(ea) = S:2; +} + +#### +#stm instruction +@include "stmwInstructions.sinc" + +@include "stswiInstructions.sinc" +#stswi r0,r0,0 0x7c 00 05 aa +#:stswi S,A,NB is $(NOTVLE) & OP=31 & S & A & NB & XOP_1_10=725 & BIT_0=0 +#{ +# tmp:1 = NB; +# storeString(S,A,tmp); +#} + +#stswx r0,r0,0 0x7c 00 05 2a +define pcodeop stswxOp; +:stswx S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=661 & BIT_0=0 +{ + EA:$(REGISTER_SIZE) = RA_OR_ZERO + B; + *[ram]:1 EA = stswxOp(S,RA_OR_ZERO,B); +} + +#stw r0,r0,0 0x90 00 00 00 +:stw S,dPlusRaOrZeroAddress is $(NOTVLE) & OP=36 & S & dPlusRaOrZeroAddress +{ +@ifdef BIT_64 + *:4(dPlusRaOrZeroAddress) = S:4; +@else + *:4(dPlusRaOrZeroAddress) = S; +@endif +} + +#stwbrx r0,r0,0 0x7c 00 05 2c +:stwbrx S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=662 & BIT_0=0 +{ +@ifdef BIT_64 + value:4 = S:4; +@else + value:$(REGISTER_SIZE) = S; +@endif + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + tmp1:4 = value << 24; + tmp2:4 = (value << 8) & 0xff0000; + tmp3:4 = (value >> 8) & 0x00ff00; + tmp4:4 = value >> 24; + *:4(ea) = tmp1 | tmp2 | tmp3 | tmp4; +} + +#stwcx. r0,8(0) 0x7c 00 01 2D +:stwcx. S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=150 & BIT_0=1 +{ + EA:$(REGISTER_SIZE) = RA_OR_ZERO + B; + if (RESERVE == 0) goto inst_next; + *[ram]:4 EA = storeWordConditionalIndexed(S,RA_OR_ZERO,B); + # set when a stwcx. or stdcx. successfully completes + cr0flags(0:$(REGISTER_SIZE)); +} + +#stwu r0,r0 0x94 00 00 00 +:stwu S,dPlusRaAddress is $(NOTVLE) & OP=37 & S & A & dPlusRaAddress +{ +@ifdef BIT_64 + *:4(dPlusRaAddress) = S:4; +@else + *:4(dPlusRaAddress) = S; +@endif + A = dPlusRaAddress; +} + +#stwux r0,r0,r0 0x7C 00 01 6E +:stwux S,A,B is OP=31 & S & A & B & XOP_1_10=183 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = A + B; +@ifdef BIT_64 + *:4(ea) = S:4; +@else + *:4(ea) = S; +@endif + A = ea; +} + +#stwx r0,r0,r0 0x7C 00 01 2E +:stwx S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=151 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; +@ifdef BIT_64 + *:4(ea) = S:4; +@else + *:4(ea) = S; +@endif +} + + +#subf r0,r0,r0 0x7c 00 00 50 +:subf D,A,B is OP=31 & D & A & B & OE=0 & XOP_1_9=40 & Rc=0 +{ + D = B - A; +} + +#subf. r0,r0,r0 0x7c 00 00 51 +:subf. D,A,B is OP=31 & D & A & B & OE=0 & XOP_1_9=40 & Rc=1 +{ + D = B - A; + cr0flags(D); +} + +#subfo r1,r2,r3 0x7c 00 04 50 +:subfo D,A,B is OP=31 & D & A & B & OE=1 & XOP_1_9=40 & Rc=0 +{ + subOverflow(B,A); + D = B - A; +} + +#subfo. r1,r2,r3 0x7c 00 04 51 +:subfo. D,A,B is OP=31 & D & A & B & OE=1 & XOP_1_9=40 & Rc=1 +{ + subOverflow(B,A); + D = B - A; + cr0flags(D); +} + +#subfc r0,r0,r0 0x7c 00 00 10 +:subfc D,A,B is OP=31 & D & A & B & OE=0 & XOP_1_9=8 & Rc=0 +{ + xer_ca = (A <= B); + D = B - A; +} + +#subfc. r0,r0,r0 0x7c 00 00 11 +:subfc. D,A,B is OP=31 & D & A & B & OE=0 & XOP_1_9=8 & Rc=1 +{ + xer_ca = (A <= B); + D = B - A; + cr0flags(D); +} + +#subfco r0,r0,r0 0x7c 00 04 10 +:subfco D,A,B is OP=31 & D & A & B & OE=1 & XOP_1_9=8 & Rc=0 +{ + xer_ca = (A <= B); + subOverflow(B,A); + D = B - A; +} + +#subfco. r0,r0,r0 0x7c 00 04 11 +:subfco. D,A,B is OP=31 & D & A & B & OE=1 & XOP_1_9=8 & Rc=1 +{ + xer_ca = (A <= B); + subOverflow( B, A ); + D = B - A; + cr0flags(D); +} + +#subfe r0,r0,r0 0x7c 00 01 10 +:subfe D,A,B is OP=31 & D & A & B & OE=0 & XOP_1_9=136 & Rc=0 +{ + tmp:$(REGISTER_SIZE) = A + zext(!xer_ca); + subExtendedCarry(B,A); + D = B - tmp; +} + +#subfe. r0,r0,r0 0x7c 00 01 11 +:subfe. D,A,B is OP=31 & D & A & B & OE=0 & XOP_1_9=136 & Rc=1 +{ + tmp:$(REGISTER_SIZE) = A + zext(!xer_ca); + subExtendedCarry(B,A); + D = B - tmp; + cr0flags(D); +} + +#subfeo r0,r0,r0 0x7c 00 05 10 +:subfeo D,A,B is OP=31 & D & A & B & OE=1 & XOP_1_9=136 & Rc=0 +{ + tmp:$(REGISTER_SIZE) = zext(!xer_ca)+A; + subExtendedOverflow(B,A); + subExtendedCarry(B,A); + D = B - tmp; +} + +#subfeo. r0,r0,r0 0x7c 00 05 11 +:subfeo. D,A,B is OP=31 & D & A & B & OE=1 & XOP_1_9=136 & Rc=1 +{ + tmp:$(REGISTER_SIZE) = zext(!xer_ca)+A; + subExtendedOverflow(B,A); + subExtendedCarry(B,A); + D = B - tmp; + cr0flags(D); +} + +#subfic r0,r0,2 0x20 00 00 02 +:subfic D,A,SIMM is $(NOTVLE) & OP=8 & D & A & SIMM +{ + xer_ca = !(SIMM + b = (63 - (i*8+7)); + tmp = (S >> (63 - (i*8+7))); b = tmp & 1; # GetBit + s = s ^ b; + i = i + 1; + if (i < 8) goto ; + A = s; +} + +# PowerISA II: 3.3.12 Fixed-Point Logical Instructions +# CMT: Compare Bytes +# FORM: X-form +# binutils: 476.d: dc: 7c 83 2b f8 cmpb r3,r4,r5 +# binutils: 476.d: e0: 7c 83 2b f8 cmpb r3,r4,r5 +# binutils: a2.d: 104: 7d 6a 63 f8 cmpb r10,r11,r12 +# binutils: power6.d: 20: 7c 83 2b f8 cmpb r3,r4,r5 +# binutils: power7.d: 90: 7c 83 2b f8 cmpb r3,r4,r5 +# name cmpb code 7c0003f8 mask ff0700fc00000000 flags @POWER6 @476 @A2 operands 31 3b 38 0 0 0 0 0 +:cmpb S,A,B is $(NOTVLE) & OP=31 & S & A & B & XOP_1_10=508 & BIT_0=0 { # PCODE-YES + tmpS:8 = 0; + tmpB:8 = 0; + val:8 = 0; + zero:8 = 0; + ones:8 = 0xff; + + # Unrolled the loop + tmpS = (S >> 56) & 0xFF; # get next S byte + tmpB = (B >> 56) & 0xFF; # get next B byte + val = (zext(tmpS == tmpB) * ones) + (zext(tmpS != tmpB) * zero); + tmpS = (S >> 48) & 0xFF; # get next S byte + tmpB = (B >> 48) & 0xFF; # get next B byte + val = val << 8 | (zext(tmpS == tmpB) * ones) + (zext(tmpS != tmpB) * zero); + tmpS = (S >> 40) & 0xFF; # get next S byte + tmpB = (B >> 40) & 0xFF; # get next B byte + val = val << 8 | (zext(tmpS == tmpB) * ones) + (zext(tmpS != tmpB) * zero); + tmpS = (S >> 32) & 0xFF; # get next S byte + tmpB = (B >> 32) & 0xFF; # get next B byte + val = val << 8 | (zext(tmpS == tmpB) * ones) + (zext(tmpS != tmpB) * zero); + tmpS = (S >> 24) & 0xFF; # get next S byte + tmpB = (B >> 24) & 0xFF; # get next B byte + val = val << 8 | (zext(tmpS == tmpB) * ones) + (zext(tmpS != tmpB) * zero); + tmpS = (S >> 16) & 0xFF; # get next S byte + tmpB = (B >> 16) & 0xFF; # get next B byte + val = val << 8 | (zext(tmpS == tmpB) * ones) + (zext(tmpS != tmpB) * zero); + tmpS = (S >> 8) & 0xFF; # get next S byte + tmpB = (B >> 8) & 0xFF; # get next B byte + val = val << 8 | (zext(tmpS == tmpB) * ones) + (zext(tmpS != tmpB) * zero); + tmpS = S & 0xFF; # get next S byte + tmpB = B & 0xFF; # get next B byte + val = val << 8 | (zext(tmpS == tmpB) * ones) + (zext(tmpS != tmpB) * zero); + A = val; +} +# PowerISA II: 3.3.12 Fixed-Point Logical Instructions +# CMT: Bit Permute Doubleword [Category: Embedded.Phased-in, Server] +# FORM: X-form +# binutils: a2.d: fc: 7d 6a 61 f8 bpermd r10,r11,r12 +# binutils: power7.d: d8: 7e 27 d9 f8 bpermd r7,r17,r27 +# name bpermd code 7c0001f8 mask ff0700fc00000000 flags @POWER7 @A2 operands 31 3b 38 0 0 0 0 0 +define pcodeop BitPermuteDoubleword; +:bpermd A,S,B is $(NOTVLE) & OP=31 & S & A & B & XOP_1_10=252 & BIT_0=0 { + BitPermuteDoubleword(A,S,B); +} + +# PowerISA II: 3.3.12 Fixed-Point Logical Instructions +# CMT: Population Count Words [Category: Server] [Category: Embedded.Phased-In] +# FORM: X-form +# binutils: a2.d: 64c: 7d 6a 02 f4 popcntw r10,r11 +# binutils: power7.d: dc: 7e 8a 02 f4 popcntw r10,r20 +# name popcntw code 7c0002f4 mask ffff00fc00000000 flags @POWER7 @A2 operands 31 3b 0 0 0 0 0 0 +:popcntw A,S is $(NOTVLE) & OP=31 & S & A & XOP_1_10=378 & Rc & BITS_11_15=0 { + local tmp1:4 = S(0); + tmp1 = popcount(tmp1); + local tmp2:4 = S(4); + tmp2 = popcount(tmp2); + A = (zext(tmp2) << 32) + zext(tmp1); +} + +# PowerISA II: 3.3.12 Fixed-Point Logical Instructions +# CMT: Population Count Bytes +# FORM: X-form +# binutils: 476.d: 618: 7c 83 00 f4 popcntb r3,r4 +# binutils: a2.d: 644: 7d 6a 00 f4 popcntb r10,r11 +# name popcntb code 7c0000f4 mask ffff00fc00000000 flags @POWER5 operands 31 3b 0 0 0 0 0 0 +:popcntb A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=122 & BIT_0=0 { + local i:8 = 0; + local tmp:8 = 0; + local tmpb:1 = 0; + local mask:8 = 0xff; + + tmp = (S >> (i*8)); + tmpb = tmp(0); + tmpb = popcount(tmpb); + A = (A & ~(mask)) + (zext(tmpb) << (i*8)); + mask = mask << 8; + i = i + 1; + if (i < 8) goto ; +} + + +# PowerISA II: 3.3.12 Fixed-Point Logical Instructions +# CMT: Parity Word +# FORM: X-form +# binutils: 476.d: 61c: 7c 83 01 34 prtyw r3,r4 +# binutils: a2.d: 654: 7d 6a 01 34 prtyw r10,r11 +# binutils: power6.d: 10: 7c 83 01 34 prtyw r3,r4 +# binutils: power7.d: 80: 7c 83 01 34 prtyw r3,r4 +# name prtyw code 7c000134 mask ffff00fc00000000 flags @POWER6 @476 @A2 operands 31 3b 0 0 0 0 0 0 +:prtyw A,S is $(NOTVLE) & OP=31 & S & A & BITS_11_15=0 & XOP_1_10=154 & BIT_0=0 { + local temp:8 = S; + A[0,32] = zext(((popcount(temp & 0x01010101:8)) & 1:8) == 1:8); + A[32,32] = zext(((popcount(temp & 0x0101010100000000:8)) & 1:8) == 1:8); +} + +# ======================================================================= + +# PowerISA II: 4.4.1 Fixed-Point Load and Store Caching Inhibited Instructions +# CMT: Load Word and Zero Caching Inhibited Indexed +# binutils: power6.d: 2c: 7d 4b 66 2a lwzcix r10,r11,r12 +# binutils: power7.d: 94: 7d 4b 66 2a lwzcix r10,r11,r12 +# name lwzcix code 7c00062a mask ff0700fc00000000 flags @POWER6 operands 3b 32 38 0 0 0 0 0 +define pcodeop LoadWordAndZeroCachingInhibited; +:lwzcix TH,A,B is $(NOTVLE) & OP=31 & TH & A & B & XOP_1_10=789 & BIT_0=0 { # PCODE-YES + tmp:8 = *(A + B); + tmp = tmp << 32; + TH = tmp; +} + +# ======================================================================= + +# PowerISA II: 3.3.14 Binary Coded Decimal (BCD) Assist Instructions [Category: Embedded.Phased-in, Server] +# CMT: Convert Declets To Binary Coded Decimal +# FORM: X-form +# binutils: power6.d: f0: 7d 6a 02 34 cdtbcd r10,r11 +# name cdtbcd code 7c000234 mask ffff00fc00000000 flags @POWER6 operands 31 3b 0 0 0 0 0 0 +define pcodeop ConvertDecletsToBinaryCodedDecimal; +:cdtbcd A,S is $(NOTVLE) & OP=31 & S & A & XOP_1_10=282 & BITS_11_15=0 & BIT_0=0 { ConvertDecletsToBinaryCodedDecimal(S,A); } + +# PowerISA II: 3.3.14 Binary Coded Decimal (BCD) Assist Instructions [Category: Embedded.Phased-in, Server] +# CMT: Add and Generate Sixes +# FORM: XO-form +# binutils: power6.d: f4: 7d 4b 60 94 addg6s r10,r11,r12 +# name addg6s code 7c000094 mask ff0700fc00000000 flags @POWER6 operands 3b 31 38 0 0 0 0 0 +define pcodeop AddAndGenerateSixes; +:addg6s TH,A,B is $(NOTVLE) & OP=31 & TH & A & B & XOP_1_9=74 & BIT_10=0 & BIT_0=0 { # PCODE-YES + AddAndGenerateSixes(TH,A,B); +} + +# ========================================================================== + +# PowerISA II: 3.3.8 Fixed-Point Arithmetic Instructions +# CMT: Divide Word Extended [Category: Server] [Category: Embedded.Phased-In] +# FORM: XO-form +# binutils: power7.d: b8: 7d 4b 63 56 divwe r10,r11,r12 +# name divwe code 7c000356 mask ff0700fc00000000 flags @POWER7 @A2 operands 3b 31 38 0 0 0 0 0 +:divwe TH,A,B is $(NOTVLE) & OP=31 & TH & A & B & OE=0 & XOP_1_9=427 & Rc=0 { + tmp:8 = 0; + + # A high 4 bytes to a + tmp = tmp >> 32; + a:4 = tmp:4; + + # B high 4 bytes to b + tmp = tmp >> 32; + b:4 = tmp:4; + + # C + c:4 = (a s/ b); + + # C low 4 bytes to TH high 4 bytes + tmp = zext(c); + tmp = tmp << 32; + TH = tmp; +} + + +# PowerISA II: 3.3.8 Fixed-Point Arithmetic Instructions +# CMT: Divide Word Extended [Category: Server] [Category: Embedded.Phased-In] +# FORM: XO-form +# binutils: power7.d: bc: 7d 6c 6b 57 divwe. r11,r12,r13 +# name divwe. code 7c000357 mask ff0700fc00000000 flags @POWER7 @A2 operands 3b 31 38 0 0 0 0 0 +:divwe. TH,A,B is $(NOTVLE) & OP=31 & TH & A & B & OE=0 & XOP_1_9=427 & Rc=1 { + tmp:8 = 0; + + # A high 4 bytes to a + tmp = tmp >> 32; + a:4 = tmp:4; + + # B high 4 bytes to b + tmp = tmp >> 32; + b:4 = tmp:4; + + # C + c:4 = (a s/ b); + + # C low 4 bytes to TH high 4 bytes + tmp = zext(c); + tmp = tmp << 32; + TH = tmp; + + cr0flags(TH); +} + +# PowerISA II: 3.3.8 Fixed-Point Arithmetic Instructions +# CMT: Divide Word Extended [Category: Server] [Category: Embedded.Phased-In] +# FORM: XO-form +# binutils: power7.d: c0: 7d 8d 77 56 divweo r12,r13,r14 +# name divweo code 7c000756 mask ff0700fc00000000 flags @POWER7 @A2 operands 3b 31 38 0 0 0 0 0 +:divweo TH,A,B is $(NOTVLE) & OP=31 & TH & A & B & OE=1 & XOP_1_9=427 & Rc=0 { + tmp:8 = 0; + + # A high 4 bytes to a + tmp = tmp >> 32; + a:4 = tmp:4; + + # B high 4 bytes to b + tmp = tmp >> 32; + b:4 = tmp:4; + + # C + c:4 = (a s/ b); + + # C low 4 bytes to TH high 4 bytes + tmp = zext(c); + tmp = tmp << 32; + divOverflow(A,B); + TH = tmp; +} + +# PowerISA II: 3.3.8 Fixed-Point Arithmetic Instructions +# CMT: Divide Word Extended [Category: Server] [Category: Embedded.Phased-In] +# FORM: XO-form +# binutils: power7.d: c4: 7d ae 7f 57 divweo. r13,r14,r15 +# name divweo. code 7c000757 mask ff0700fc00000000 flags @POWER7 @A2 operands 3b 31 38 0 0 0 0 0 +define pcodeop DivideWordExtended4; +:divweo. TH,A,B is $(NOTVLE) & OP=31 & TH & A & B & OE=1 & XOP_1_9=427 & Rc=1 { + tmp:8 = 0; + + # A high 4 bytes to a + tmp = tmp >> 32; + a:4 = tmp:4; + + # B high 4 bytes to b + tmp = tmp >> 32; + b:4 = tmp:4; + + # C + c:4 = (a s/ b); + + # C low 4 bytes to TH high 4 bytes + tmp = zext(c); + tmp = tmp << 32; + divOverflow(A,B); + TH = tmp; + + cr0flags(TH); +} + +# PowerISA II: 3.3.8 Fixed-Point Arithmetic Instructions +# CMT: Divide Word Extended [Category: Server] [Category: Embedded.Phased-In] +# FORM: XO-form +# binutils: power7.d: c8: 7d 4b 63 16 divweu r10,r11,r12 +# name divweu code 7c000316 mask ff0700fc00000000 flags @POWER7 @A2 operands 3b 31 38 0 0 0 0 0 +:divweu TH,A,B is $(NOTVLE) & OP=31 & TH & A & B & OE=0 & Rc=0 & XOP_1_9=395 { + tmp:8 = 0; + + # A high 4 bytes to a + tmp = tmp >> 32; + a:4 = tmp:4; + + # B high 4 bytes to b + tmp = tmp >> 32; + b:4 = tmp:4; + + # C + c:4 = (a / b); + + # C low 4 bytes to TH high 4 bytes + tmp = zext(c); + tmp = tmp << 32; + TH = tmp; +} + +# PowerISA II: 3.3.8 Fixed-Point Arithmetic Instructions +# CMT: Divide Word Extended [Category: Server] [Category: Embedded.Phased-In] +# FORM: XO-form +# binutils: power7.d: cc: 7d 6c 6b 17 divweu. r11,r12,r13 +# name divweu. code 7c000317 mask ff0700fc00000000 flags @POWER7 @A2 operands 3b 31 38 0 0 0 0 0 +:divweu. TH,A,B is $(NOTVLE) & OP=31 & TH & A & B & OE=0 & Rc=1 & XOP_1_9=395 { + tmp:8 = 0; + + # A high 4 bytes to a + tmp = tmp >> 32; + a:4 = tmp:4; + + # B high 4 bytes to b + tmp = tmp >> 32; + b:4 = tmp:4; + + # C + c:4 = (a / b); + + # C low 4 bytes to TH high 4 bytes + tmp = zext(c); + tmp = tmp << 32; + TH = tmp; + + cr0flags(TH); +} + +# PowerISA II: 3.3.8 Fixed-Point Arithmetic Instructions +# CMT: Divide Word Extended Unsigned [Category: Server] [Category: Embedded.Phased-In] +# FORM: XO-form +# binutils: power7.d: d0: 7d 8d 77 16 divweuo r12,r13,r14 +# name divweuo code 7c000716 mask ff0700fc00000000 flags @POWER7 @A2 operands 3b 31 38 0 0 0 0 0 +:divweuo TH,A,B is $(NOTVLE) & OP=31 & TH & A & B & OE=1 & Rc=0 & XOP_1_9=395 { + tmp:8 = 0; + + # A high 4 bytes to a + tmp = tmp >> 32; + a:4 = tmp:4; + + # B high 4 bytes to b + tmp = tmp >> 32; + b:4 = tmp:4; + + # C + c:4 = (a / b); + + # C low 4 bytes to TH high 4 bytes + tmp = zext(c); + tmp = tmp << 32; + divOverflow(A,B); + TH = tmp; +} + +# PowerISA II: 3.3.8 Fixed-Point Arithmetic Instructions +# CMT: Divide Word Extended Unsigned [Category: Server] [Category: Embedded.Phased-In] +# FORM: XO-form +# binutils: power7.d: d4: 7d ae 7f 17 divweuo. r13,r14,r15 +# name divweuo. code 7c000717 mask ff0700fc00000000 flags @POWER7 @A2 operands 3b 31 38 0 0 0 0 0 +:divweuo. TH,A,B is $(NOTVLE) & OP=31 & TH & A & B & OE=1 & Rc=1 & XOP_1_9=395 { + tmp:8 = 0; + + # A high 4 bytes to a + tmp = tmp >> 32; + a:4 = tmp:4; + + # B high 4 bytes to b + tmp = tmp >> 32; + b:4 = tmp:4; + + # C + c:4 = (a / b); + + # C low 4 bytes to TH high 4 bytes + tmp = zext(c); + tmp = tmp << 32; + divOverflow(A,B); + TH = tmp; + + cr0flags(TH); +} + +# ======================================================================= + +# PowerISA II: 3.3.12.1 64-bit Fixed-Point Logical Instructions [Category: 64-Bit] +# CMT: Population Count Doubleword [Category: Server.64-bit] [Category: Embedded.64-bit.Phased-In] +# FORM: X-form +# binutils: a2.d: 648: 7d 6a 03 f4 popcntd r10,r11 +# binutils: power7.d: e0: 7e 8a 03 f4 popcntd r10,r20 +# name popcntd code 7c0003f4 mask ffff00fc00000000 flags @POWER7 @A2 operands 31 3b 0 0 0 0 0 0 +:popcntd A,S is $(NOTVLE) & OP=31 & S & A & XOP_1_10=506 & Rc & BITS_11_15=0 { + A = popcount(S); +} + +# ======================================================================= + +# PowerISA II: 3.3.4.1 64-Bit Load and Store with Byte Reversal Instructions [Category: 64-bit] +# CMT: Load Doubleword Byte-Reverse Indexed +# FORM: X-form +# Category: 64 +# binutils: a2.d: 418: 7d 4b 64 28 ldbrx r10,r11,r12 +# binutils: cell.d: 40: 7c 00 0c 28 ldbrx r0,0,r1 +# binutils: cell.d: 44: 7c 01 14 28 ldbrx r0,r1,r2 +# binutils: power7.d: e4: 7e 95 b4 28 ldbrx r20,r21,r22 +# name ldbrx code 7c000428 mask ff0700fc00000000 flags @POWER7 @CELL @A2 operands 3b 32 38 0 0 0 0 0 +define pcodeop LoadDoublewordByteReverseIndexed; +:ldbrx D,A,B is $(NOTVLE) & OP=31 & D & A & B & XOP_1_10=532 & Rc { D = LoadDoublewordByteReverseIndexed(D,A,B); } + +# ====================================================================== + +# PowerISA II: 4.4.2 Load and Reserve and Store Conditional Instructions +# CMT: Store Byte Conditional Indexed +# FORM: X-form +# binutils: power7.d: 164: 7d 4b 65 6d stbcx. r10,r11,r12 +# name stbcx. code 7c00056d mask ff0700fc00000000 flags @POWER7 operands 3b 32 38 0 0 0 0 0 +define pcodeop StoreByteConditionalIndexed; +:stbcx. S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=694 & Rc=1 { + EA:$(REGISTER_SIZE) = RA_OR_ZERO + B; + *[ram]:1 EA = StoreByteConditionalIndexed(S,RA_OR_ZERO,B); + setCrBit(cr0, 2, 1); +} + +# ====================================================================== + +# PowerISA II: 5.4.1 Move To/From System Register Instructions +# CMT: Move From Device Control Register Indexed [Category: Embedded.Device Control] +# FORM: X-form +# binutils: 476.d: 49c: 7c 85 02 06 mfdcrx r4,r5 +# binutils: a2.d: 520: 7d 4b 02 06 mfdcrx r10,r11 +# binutils: booke.d: 28: 7c 85 02 06 mfdcrx r4,r5 +# binutils: booke_xcoff.d: 24: 7c 85 02 06 mfdcrx r4,r5 +# name mfdcrx code 7c000206 mask ff0700fc00000000 flags @476 @BOOKE @A2 operands 3b 31 0 0 0 0 0 0 +define pcodeop MoveFromDeviceControlRegisterIndexed; +:mfdcrx D,A is OP=31 & D & A & XOP_1_9=259 & Rc=0 { # + MoveFromDeviceControlRegisterIndexed(D,A); +} + + +# PowerISA II: 5.4.1 Move To/From System Register Instructions +# CMT: Move To Device Control Register Indexed [Category: Embedded.Device Control] +# FORM: X-form +# binutils: 476.d: 4cc: 7c e6 03 06 mtdcrx r6,r7 +# binutils: a2.d: 568: 7d 6a 03 06 mtdcrx r10,r11 +# binutils: booke.d: 30: 7c e6 03 06 mtdcrx r6,r7 +# binutils: booke_xcoff.d: 2c: 7c e6 03 06 mtdcrx r6,r7 +# binutils: 4cc: 7c e6 03 06 mtdcrx r6,r7 +# name mtdcrx code 7c000306 mask ff0700fc00000000 flags @476 @BOOKE @A2 operands 31 3b 0 0 0 0 0 0 +define pcodeop MoveToDeviceControlRegisterIndexed; +:mtdcrx A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=387 & BIT_0=0 { MoveToDeviceControlRegisterIndexed(S,A); } # + +# ======================================================================== + +# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID] +# CMT: Data Cache Block Flush by External PID +# FORM: X-form +# binutils: a2.d: 154: 7c 0a 58 fe dcbfep r10,r11 +# binutils: e500mc.d: 9c: 7c 01 10 fe dcbfep r1,r2 +# name dcbfep code 7c0000fe mask ff07e0ff00000000 flags @E500MC @A2 operands 31 38 0 0 0 0 0 0 +define pcodeop DataCacheBlockFlushByExternalPID; +:dcbfep A,B is OP=31 & A & B & XOP_1_10=127 & BIT_0=0 & BITS_21_25=0 { # + DataCacheBlockFlushByExternalPID(A,B); +} + +# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID] +# CMT: Data Cache Block Store by External PID +# FORM: X-form +# binutils: a2.d: 168: 7c 0a 58 7e dcbstep r10,r11 +# binutils: e500mc.d: 98: 7c 1f 00 7e dcbstep r31,r0 +# name dcbstep code 7c00007e mask ff07e0ff00000000 flags @E500MC @A2 operands 31 38 0 0 0 0 0 0 +define pcodeop DataCacheBlockStoreByExternalPID; +:dcbstep A,B is OP=31 & BITS_21_25=0 & A & B & XOP_1_10=63 & BIT_0=0 { # + DataCacheBlockStoreByExternalPID(A,B); +} + + +# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID] +# CMT: Data Cache Block set to Zero by External PID +# FORM: X-form +# binutils: a2.d: 198: 7c 0a 5f fe dcbzep r10,r11 +# binutils: e500mc.d: a8: 7c 0b 67 fe dcbzep r11,r12 +# name dcbzep code 7c0007fe mask ff07e0ff00000000 flags @E500MC @A2 operands 31 38 0 0 0 0 0 0 +define pcodeop DataCacheBlockSetToZeroByExternalPID; +:dcbzep A,B is OP=31 & BITS_21_25=0 & A & B & XOP_1_10=1023 & BIT_0=0 { + DataCacheBlockSetToZeroByExternalPID(A,B); +} + +# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID] +# CMT: Instruction Cache Block Invalidate by External PID +# FORM: X-form +# binutils: a2.d: 3b8: 7c 0a 5f be icbiep r10,r11 +# binutils: e500mc.d: 10: 7c 09 57 be icbiep r9,r10 +# name icbiep code 7c0007be mask ff07e0ff00000000 flags @E500MC @A2 operands 31 38 0 0 0 0 0 0 +define pcodeop InstructionCacheBlockInvalidateByExternalPID; +:icbiep A,B is OP=31 & BITS_21_25=0 & A & B & XOP_1_10=991 & BIT_0=0 { + InstructionCacheBlockInvalidateByExternalPID(A,B); +} + +# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID] +# CMT: Load Floating-Point Double by External Process ID Indexed +# FORM: X-form +# binutils: a2.d: 438: 7e 8a 5c be lfdepx f20,r10,r11 +# binutils: e500mc.d: 50: 7d ae 7c be lfdepx f13,r14,r15 +# name lfdepx code 7c0004be mask ff0700fc00000000 flags @E500MC @A2 operands 22 31 38 0 0 0 0 0 +:lfdepx fT,RA_OR_ZERO,B is OP=31 & fT & B & RA_OR_ZERO & XOP_1_10=607 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO+B; + fT = *:8(ea); +} + + +# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID] +# CMT: Store Byte by External Process ID Indexed +# FORM: X-form +# binutils: a2.d: 700: 7d 4b 61 be stbepx r10,r11,r12 +# binutils: e500mc.d: 54: 7e 11 91 be stbepx r16,r17,r18 +# name stbepx code 7c0001be mask ff0700fc00000000 flags @E500MC @A2 operands 3b 31 38 0 0 0 0 0 +define pcodeop StoreByteByExternalProcessIDIndexed; +:stbepx S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=223 & BIT_0=0 { # + EA:$(REGISTER_SIZE) = RA_OR_ZERO + B; + *[ram]:1 EA = StoreByteByExternalProcessIDIndexed(S,RA_OR_ZERO,B); +} + +# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID] +# CMT: Store Halfword by External Process ID Indexed +# FORM: X-form +# binutils: a2.d: 784: 7d 4b 63 3e sthepx r10,r11,r12 +# binutils: e500mc.d: 58: 7e 74 ab 3e sthepx r19,r20,r21 +# name sthepx code 7c00033e mask ff0700fc00000000 flags @E500MC @A2 operands 3b 31 38 0 0 0 0 0 +define pcodeop StoreHalfwordByExternalProcessIDIndexed; +:sthepx S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=415 & BIT_0=0 { # + EA:$(REGISTER_SIZE) = RA_OR_ZERO + B; + *[ram]:2 EA = StoreHalfwordByExternalProcessIDIndexed(S,RA_OR_ZERO,B); +} + +# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID] +# CMT: Store Word by External Process ID Indexed +# FORM: X-form +# binutils: a2.d: 7b0: 7d 4b 61 3e stwepx r10,r11,r12 +# binutils: e500mc.d: 5c: 7e d7 c1 3e stwepx r22,r23,r24 +# name stwepx code 7c00013e mask ff0700fc00000000 flags @E500MC @A2 operands 3b 31 38 0 0 0 0 0 +define pcodeop StoreWordByExternalProcessIDIndexed; +:stwepx S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=159 & BIT_0=0 { # + EA:$(REGISTER_SIZE) = RA_OR_ZERO + B; + *[ram]:4 EA = StoreWordByExternalProcessIDIndexed(S,RA_OR_ZERO,B); +} + +# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID] +# CMT: Store Doubleword Byte-Reverse Indexed +# FORM: X-form +# binutils: a2.d: 71c: 7d 4b 65 28 stdbrx r10,r11,r12 +# binutils: cell.d: 48: 7c 00 0d 28 stdbrx r0,0,r1 +# binutils: cell.d: 4c: 7c 01 15 28 stdbrx r0,r1,r2 +# binutils: power7.d: e8: 7e 95 b5 28 stdbrx r20,r21,r22 +# name stdbrx code 7c000528 mask ff0700fc00000000 flags @POWER7 @CELL @A2 operands 3b 32 38 0 0 0 0 0 +define pcodeop StoreDoublewordByteReverseIndexed; +:stdbrx S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=660 & BIT_0=0 { # + EA:$(REGISTER_SIZE) = RA_OR_ZERO + B; + *[ram]:8 EA = StoreDoublewordByteReverseIndexed(S,RA_OR_ZERO,B); +} + +# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID] +# CMT: Store Doubleword Byte-Reverse Indexed +# FORM: X-form +# binutils: a2.d: 724: 7d 4b 61 3a stdepx r10,r11,r12 +# binutils: e500mc.d: 60: 7f 3a d9 3a stdepx r25,r26,r27 +# name stdepx code 7c00013a mask ff0700fc00000000 flags @E500MC @A2 operands 3b 31 38 0 0 0 0 0 +define pcodeop StoreDoublewordByteReverseIndexed1; +:stdepx S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=157 & BIT_0=0 { # + EA:$(REGISTER_SIZE) = RA_OR_ZERO + B; + *[ram]:8 EA = StoreDoublewordByteReverseIndexed1(S,RA_OR_ZERO,B); +} + + +# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID] +# CMT: Load Byte by External Process ID Indexed +# FORM: X-form +# binutils: a2.d 3ec: 7d 4b 60 be lbepx r10,r11,r12 +# binutils: e500mc.d 40: 7c 22 18 be lbepx r1,r2,r3 +# name lbepx code 7c0000be mask ff0700fc00000000 flags @E500MC @A2 operands 3b 31 38 0 0 0 0 0 +# Note: no support for context modeling here +:lbepx D,RA_OR_ZERO,B is OP=31 & D & RA_OR_ZERO & B & XOP_1_10=95 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO+B; + D = zext(*:1(ea)); +} + +# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID] +# CMT: Data Cache Block Touch by External PID +# FORM: X-form +# binutils: a2.d: 174: 7d 4b 62 7e dcbtep r10,r11,r12 +# binutils: e500mc.d: a4: 7c c7 42 7e dcbtep r6,r7,r8 +# NOTE: BITS_21_25 => TH (register) +# name dcbtep code 7c00027e mask ff0700fc00000000 flags @E500MC @A2 operands 3b 31 38 0 0 0 0 0 +# No PCODE necessary +define pcodeop DataCacheBlockTouchByExternalPID2; +:dcbtep TH,RA_OR_ZERO,B is OP=31 & TH & RA_OR_ZERO & B & XOP_1_10=319 & BIT_0=0 { + DataCacheBlockTouchByExternalPID2(TH,RA_OR_ZERO,B); +} + + +# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID] +# CMT: Load Doubleword by External Process ID Indexed +# FORM: X-form +# binutils: a2.d: 41c: 7d 4b 60 3a ldepx r10,r11,r12 +# binutils: e500mc.d: 4c: 7d 4b 60 3a ldepx r10,r11,r12 +# name ldepx code 7c00003a mask ff0700fc00000000 flags @E500MC @A2 operands 3b 31 38 0 0 0 0 0 +# Note: no support for context modeling here +:ldepx D,RA_OR_ZERO,B is OP=31 & D & RA_OR_ZERO & B & XOP_1_10=29 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO+B; + D = *:8(ea); +} + +# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID] +# CMT: Load Word by External Process ID Indexed +# FORM: X-form +# binutils: a2.d: 4c8: 7d 4b 60 3e lwepx r10,r11,r12 +# binutils: e500mc.d: 48: 7c e8 48 3e lwepx r7,r8,r9 +# Note: no support for context modeling here +:lwepx D,RA_OR_ZERO,B is OP=31 & D & RA_OR_ZERO & B & XOP_1_10=31 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO+B; + D = *:4(ea); +} + +# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID] +# CMT: Store Floating-Point Double by External Process ID Indexed +# FORM: X-form +# binutils: a2.d: 740: 7e 8a 5d be stfdepx f20,r10,r11 +# binutils: e500mc.d: 64: 7f 9d f5 be stfdepx f28,r29,r30 +# NOTE: BITS_21_25 => FRS (float register) => fS +# Note: no support for context modeling here +:stfdepx fS,RA_OR_ZERO,B is OP=31 & fS & B & RA_OR_ZERO & XOP_1_10=735 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO+B; + *:8(ea) = fS; +} + + +# PowerISA II: 5.4.3 External Process ID Instructions [Category: Embedded.External PID] +# CMT: Load Halfword by External Process ID Indexed +# FORM: X-form +# binutils: a2.d: 480: 7d 4b 62 3e lhepx r10,r11,r12 +# binutils: e500mc.d: 44: 7c 85 32 3e lhepx r4,r5,r6 +# Note: no support for context modeling here +:lhepx D,RA_OR_ZERO,B is OP=31 & D & RA_OR_ZERO & B & XOP_1_10=287 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO+B; + D = zext(*:2(ea)); +} + +# ======================================================================== + +# PowerISA II: 3.3.15.2 Move To/From System Registers [Category: Embedded] +# CMT: Move From Device Control Register User-mode Indexed [Category: Embedded.Device Control] +# FORM: X-form +# binutils: 476.d: 498: 7c 64 02 46 mfdcrux r3,r4 +define pcodeop MoveFromDeviceControlRegisterUserModeIndexed; +:mfdcrux RT,A is OP=31 & RT & A & BITS_11_15=0 & XOP_1_10=291 & BIT_0=0 +{ + +@ifdef BIT_64 + tmp:8 = dcr000 + (A * $(REGISTER_SIZE)); + RT = *[register]:8 (tmp:4); +@else + tmp = dcr000 + (A * $(REGISTER_SIZE)); + RT = *[register]:4 (tmp); +@endif + +} + +# PowerISA II: 3.3.15.2 Move To/From System Registers [Category: Embedded] +# CMT: Move To Device Control Register User-mode Indexed [Category: Embedded.Device Control] +# FORM: X-form +# binutils: 476.d: 4c8: 7c 83 03 46 mtdcrux r3,r4 +:mtdcrux S,A is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=419 & BIT_0=0 +{ +@ifdef BIT_64 + tmp:8 = dcr000 + (A * $(REGISTER_SIZE)); + *[register]:8 (tmp:4) = S; +@else + tmp = dcr000 + (A * $(REGISTER_SIZE)); + *[register]:4 (tmp) = S; +@endif + +} + + +# ======================================================================== + +# PowerISA II: Chapter 10. Legacy Move Assist Instruction [Category: Legacy Move Assist] +# CMT: Determine Leftmost Zero Byte +# FORM: X-form +# binutils: 476.d: 1a4: 7c 83 28 9c dlmzb r3,r4,r5 +# binutils: titan.d: 158: 7c 22 00 9c dlmzb r2,r1,r0 +define pcodeop DetermineLeftmostZeroByte; +:dlmzb S,A,B is OP=31 & S & A & B & XOP_1_10=78 & Rc=0 +{ + # search from left for the first occurrence of null byte + + # low 32 bits of RS concatenated with low 32 bits of RB +@ifdef BIT_64 + tmpD:8 = zext( S:4 ); +@else + tmpD:8 = zext( S ); +@endif + + tmpD = tmpD << 32; + +@ifdef BIT_64 + tmpD = tmpD | zext( B:4 ); +@else + tmpD = tmpD | zext( B ); +@endif + + tmpX:8 = 0; + + + + if ( tmpX == 8 ) goto ; + tmpX = tmpX + 1; + + if ( ( ( tmpD << ( (tmpX-1) * 8 ) ) & 0xFF00000000000000 ) != 0 ) goto ; + + + + # place byte number in register A and low 7 bits of XER +@ifdef BIT_64 + A = tmpX; + XER = ( XER & 0xFFFFFFFFFFFFFF80 ) | tmpX; +@else + A = tmpX:4; + XER = ( XER & 0xFFFFFF80 ) | tmpX:4; +@endif + +} + +# PowerISA II: Chapter 10. Legacy Move Assist Instruction [Category: Legacy Move Assist] +# CMT: Determine Leftmost Zero Byte +# FORM: X-form +# binutils: 476.d: 1a8: 7c 83 28 9d dlmzb\. r3,r4,r5 +# binutils: titan.d: 15c: 7c 22 00 9d dlmzb\. r2,r1,r0 +define pcodeop DetermineLeftmostZeroByte1; +:dlmzb. S,A,B is OP=31 & S & A & B & XOP_1_10=78 & Rc=1 +{ + # search from left for the first occurrence of null byte + + # low 32 bits of RS concatenated with low 32 bits of RB +@ifdef BIT_64 + tmpD:8 = zext( S:4 ); +@else + tmpD:8 = zext( S ); +@endif + + tmpD = tmpD << 32; + +@ifdef BIT_64 + tmpD = tmpD | zext( B:4 ); +@else + tmpD = tmpD | zext( B ); +@endif + + tmpX:8 = 0; + tmpY:8 = 0; + + + + if ( tmpX == 8 ) goto ; + tmpX = tmpX + 1; + + if ( ( ( tmpD << ( (tmpX - 1) * 8 ) ) & 0xFF00000000000000 ) != 0 ) goto ; + + # matched + tmpY = 1; + + + + # place byte number in register A and low 7 bits of XER +@ifdef BIT_64 + A = tmpX; + XER = ( XER & 0xFFFFFFFFFFFFFF80 ) | tmpX; +@else + A = tmpX:4; + XER = ( XER & 0xFFFFFF80 ) | tmpX:4; +@endif + + # Rc section + + # Set bit 35 of CR to SO + cr0 = (cr0 & 0xe) | zext( xer_so & 1); + + + # Set bits 32:34 of CR + if ( tmpY != 1 ) goto ; + + if ( tmpX >= 5 ) goto ; + cr0 = ( cr0 & 0x1 ) | 4; + goto ; + + + cr0 = ( cr0 & 0x1 ) | 8; + goto ; + + + cr0 = ( cr0 & 0x1 ) | 2; + +} + +# ======================================================================== + +# PowerISA II: 4.6.5 Floating-Point Move Instructions +# CMT: Floating Copy Sign +# FORM: X-form +# binutils: 476.d: 1f0: fd 4b 60 10 fcpsgn f10,f11,f12 +# binutils: a2.d: 268: fe 95 b0 10 fcpsgn f20,f21,f22 +:fcpsgn fT,fA,fB is $(NOTVLE) & OP=63 & fT & fA & fB & XOP_1_10=8 & Rc=0 +{ + fT = ( fB & 0x7FFFFFFFFFFFFFFF ) | ( fA & 0x8000000000000000 ); +} + +# PowerISA II: 4.6.5 Floating-Point Move Instructions +# CMT: Floating Copy Sign +# FORM: X-form +# binutils: 476.d: 1f4: fd 4b 60 11 fcpsgn\. f10,f11,f12 +# binutils: a2.d: 264: fe 95 b0 11 fcpsgn\. f20,f21,f22 +:fcpsgn. fT,fA,fB is $(NOTVLE) & OP=63 & fT & fA & fB & XOP_1_10=8 & Rc=1 +{ + fT = ( fB & 0x7FFFFFFFFFFFFFFF ) | ( fA & 0x8000000000000000 ); + cr1flags(); +} +# ======================================================================== + +# PowerISA II: 4.6.2 Floating-Point Load Instructions +# CMT: Load Floating-Point as Integer Word Algebraic Indexed +# FORM: X-form +# binutils: 476.d: 350: 7d 43 26 ae lfiwax f10,r3,r4 +# binutils: a2.d: 44c: 7e 8a 5e ae lfiwax f20,r10,r11 +define pcodeop LoadFloatingPointAsIntegerWordAlgebraicIndexed; +:lfiwax fT,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & fT & RA_OR_ZERO & B & XOP_1_10=855 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO+B; + fT = sext( *:4(ea) ); +} + +# PowerISA II: 4.6.2 Floating-Point Load Instructions +# CMT: Load Floating-Point as Integer Word and Zero Indexed [Category: Floating-Point.Phased-in] +# FORM: X-form +# bintutils: a2.d: 450: 7e 8a 5e ee lfiwzx f20,r10,r11 +# bintutils: power7.d: ec: 7d 40 56 ee lfiwzx f10,0,r10 +# bintutils: power7.d: f0: 7d 49 56 ee lfiwzx f10,r9,r10 +define pcodeop LoadFloatingPointAsIntegerWordAndZeroIndexed; +:lfiwzx fT,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & fT & RA_OR_ZERO & B & XOP_1_10=887 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO+B; + fT = zext( *:4(ea) ); +} + +# ======================================================================= + +# PowerISA II: A.1 Embedded Cache Initialization [Category: Embedded.Cache Initialization] +# CMT: Instruction Cache Invalidate +# FORM: X-form +# binutils: 476.d: 31c: 7c 20 07 8c ici 1 +# binutils: a2.d: 3d8: 7d 40 07 8c ici 10 +# Note: Using CT, but limited to 4 bits, not 5 (PPC bit 6 is 0 and is a don't care anyhow as CT is unused) +# No PCODE for this function +define pcodeop InstructionCacheInvalidate; +:ici CT is OP=31 & CT & BITS_16_20=0 & BITS_11_15=0 & XOP_1_10=966 & BIT_0=0 +{ + InstructionCacheInvalidate(); +} + +# PowerISA II: A.1 Embedded Cache Initialization [Category: Embedded.Cache Initialization] +# CMT: Data Cache Invalidate +# FORM: X-form +# Note: Using CT, but limited to 4 bits, not 5 (PPC bit 6 is 0 and is a don't care anyhow as CT is unused) +# No PCODE for this function +# binutils: 476.d: 180: 7c 20 03 8c dci 1 +# binutils: a2.d: 1a8: 7d 40 03 8c dci 10 +define pcodeop DataCacheInvalidate; +:dci CT is OP=31 & CT & BITS_11_20=0 & BITS_11_15=0 & XOP_1_10=454 & BIT_0=0 +{ + DataCacheInvalidate(); +} + +# ======================================================================= + +# PowerISA II: 4.3.1 Instruction Cache Instructions +# CMT: Instruction Cache Block Touch [Category: Embedded] +# FORM: X-form +# binutils: 476.d: 308: 7c a8 48 2c icbt 5,r8,r9 +# binutils: a2.d: 3bc: 7c 0a 58 2c icbt r10,r11 +# binutils: a2.d: 3c0: 7c ea 58 2c icbt 7,r10,r11 +# binutils: booke.d: 0: 7c a8 48 2c icbt 5,r8,r9 +# binutils: booke_xcoff.d: 8: 7c a8 48 2c icbt 5,r8,r9 +# Note: Using CT, but limited to 4 bits, not 5 (PPC bit 6 is 0 and is a don't care anyhow as CT is unused) +# No PCODE for this function +define pcodeop InstructionCacheBlockTouch; +:icbt CT,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & CT & RA_OR_ZERO & B & XOP_1_10=22 & BIT_0=0 +{ + InstructionCacheBlockTouch(RA_OR_ZERO,B); +} + +# ====================================================================== + +# PowerISA II: 4.6.6.1 Floating-Point Elementary Arithmetic Instructions +# CMT: Floating Reciprocal Square Root Estimate [Single] +# FORM: A-form +# binutils: 476.d: 2d0: ed c0 78 34 frsqrtes f14,f15 +# binutils: a2.d: 374: ee 80 a8 34 frsqrtes f20,f21 +# binutils: a2.d: 37c: ee 80 a8 34 frsqrtes f20,f21 +# binutils: a2.d: 384: ee 81 a8 34 frsqrtes f20,f21,1 +# binutils: power7.d: 184: ed c0 78 34 frsqrtes f14,f15 +# NOTE: binutils allows BITS_16_20=1 but manual says BITS_16_20=0. We take the manuals side. (pg 136) +:frsqrtes fT,fB is $(NOTVLE) & OP=59 & fT & fB & BITS_16_20=0 & BITS_6_10=0 & XOP_1_5=26 & Rc=0 +{ + # divide 1 by square root of fB to create reciprocal + tmp1:8 = 0x3FF0000000000000; + fT = tmp1 f/ sqrt( fB ); + setFPDivFlags(tmp1,fB,fT); +} + +# PowerISA II: 4.6.6.1 Floating-Point Elementary Arithmetic Instructions +# CMT: Floating Reciprocal Square Root Estimate [Single] +# FORM: A-form +# binutils: 476.d: 2d4: ed c0 78 35 frsqrtes. f14,f15 +# binutils: a2.d: 378: ee 80 a8 35 frsqrtes. f20,f21 +# binutils: a2.d: 380: ee 80 a8 35 frsqrtes. f20,f21 +# binutils: a2.d: 388: ee 81 a8 35 frsqrtes. f20,f21,1 +# binutils: power7.d: 188: ed c0 78 35 frsqrtes. f14,f15 +# NOTE: binutils allows BITS_16_20=1 but manual says BITS_16_20=0. We take the manuals side. (pg 136) +define pcodeop FloatingReciprocalSquareRootEstimate1; +:frsqrtes. fT,fB is $(NOTVLE) & OP=59 & fT & fB & BITS_16_20=0 & BITS_6_10=0 & XOP_1_5=26 & Rc=1 +{ + # divide 1 by square root of fB to create reciprocal + tmp1:8 = 0x3FF0000000000000; + fT = tmp1 f/ sqrt( fB ); + setFPDivFlags(tmp1,fB,fT); + cr1flags(); +} + +# PowerISA II: 4.6.6.1 Floating-Point Elementary Arithmetic Instructions +# CMT: Floating Reciprocal Estimate [Single] +# FORM: A-form +# binutils: 476.d: 290: fd c0 78 30 fre f14,f15 +# binutils: a2.d: 308: fe 80 a8 30 fre f20,f21 +# binutils: a2.d: 310: fe 80 a8 30 fre f20,f21 +# binutils: a2.d: 318: fe 81 a8 30 fre f20,f21,1 +# binutils: power7.d: 16c: fd c0 78 30 fre f14,f15 +# NOTE: binutils allows BITS_16_20!=0 but manual says BITS_16_20=0. We take the manuals side. (pg 135) +:fre fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & BITS_6_10=0 & XOP_1_5=24 & Rc=0 +{ + # divide 1 by fB to create reciprocal + tmp1:8 = 0x3FF0000000000000; + fT = tmp1 f/ fB; + setFPDivFlags(tmp1,fB,fT); +} + +# PowerISA II: 4.6.6.1 Floating-Point Elementary Arithmetic Instructions +# CMT: Floating Reciprocal Estimate [Single] +# FORM: A-form +# binutils: 476.d: 294: fd c0 78 31 fre. f14,f15 +# binutils: a2.d: 304: fe 80 a8 31 fre. f20,f21 +# binutils: a2.d: 30c: fe 80 a8 31 fre. f20,f21 +# binutils: a2.d: 314: fe 81 a8 31 fre. f20,f21,1 +# binutils: power7.d: 170: fd c0 78 31 fre. f14,f15 +# NOTE: binutils allows BITS_16_20!=0 but manual says BITS_16_20=0. We take the manuals side. (pg 135) +:fre. fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & BITS_6_10=0 & XOP_1_5=24 & Rc=1 +{ + # divide 1 by fB to create reciprocal + tmp1:8 = 0x3FF0000000000000; + fT = tmp1 f/ fB; + setFPDivFlags(tmp1,fB,fT); + cr1flags(); +} +# ====================================================================== + +# PowerISA II: 4.6.7.3 Floating Round to Integer Instructions +# CMT: Floating Round to Integer Minus +# FORM: X-form +# binutils: 476.d: 2a0: fd 40 5b d0 frim f10,f11 +# binutils: a2.d: 338: fe 80 ab d0 frim f20,f21 +:frim fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=488 & Rc=0 +{ + fT = floor( fB ); + setFPRF(fT); + setSummaryFPSCR(); +} + +# PowerISA II: 4.6.7.3 Floating Round to Integer Instructions +# CMT: Floating Round to Integer Minus +# FORM: X-form +# binutils: 476.d: 2a4: fd 40 5b d1 frim. f10,f11 +# binutils: a2.d: 334: fe 80 ab d1 frim. f20,f21 +:frim. fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=488 & Rc=1 +{ + fT = floor( fB ); + setFPRF(fT); + setSummaryFPSCR(); + cr1flags(); +} + +# PowerISA II: 4.6.7.3 Floating Round to Integer Instructions +# CMT: Floating Round to Integer Nearest +# FORM: X-form +# binutils: 476.d: 2a8: fd 40 5b 10 frin f10,f11 +# binutils: a2.d: 340: fe 80 ab 10 frin f20,f21 +:frin fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=392 & Rc=0 +{ + fT = round( fB ); + setFPRF(fT); + setSummaryFPSCR(); +} + +# PowerISA II: 4.6.7.3 Floating Round to Integer Instructions +# CMT: Floating Round to Integer Nearest +# FORM: X-form +# binutils: 476.d: 2ac: fd 40 5b 11 frin. f10,f11 +# binutils: a2.d: 33c: fe 80 ab 11 frin. f20,f21 +:frin. fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=392 & Rc=1 +{ + fT = round( fB ); + setFPRF(fT); + setSummaryFPSCR(); + cr1flags(); +} + +# PowerISA II: 4.6.7.3 Floating Round to Integer Instructions +# CMT: Floating Round to Integer Plus +# FORM: X-form +# binutils: 476.d: 2b0: fd 40 5b 90 frip f10,f11 +# binutils: a2.d: 348: fe 80 ab 90 frip f20,f21 +:frip fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=456 & Rc=0 +{ + fT = ceil( fB ); + setFPRF(fT); + setSummaryFPSCR(); +} + +# PowerISA II: 4.6.7.3 Floating Round to Integer Instructions +# CMT: Floating Round to Integer Plus +# FORM: X-form +# binutils: 476.d: 2b4: fd 40 5b 91 frip. f10,f11 +# binutils: a2.d: 344: fe 80 ab 91 frip. f20,f21 +:frip. fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=456 & Rc=1 +{ + fT = ceil( fB ); + setFPRF(fT); + setSummaryFPSCR(); + cr1flags(); +} + +# PowerISA II: 4.6.7.3 Floating Round to Integer Instructions +# CMT: Floating Round to Integer Toward Zero +# FORM: X-form +# binutils: 476.d: 2b8: fd 40 5b 50 friz f10,f11 +# binutils: a2.d: 350: fe 80 ab 50 friz f20,f21 +:friz fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=424 & Rc=0 +{ + fT = trunc( fB ); + setFPRF(fT); + setSummaryFPSCR(); +} + +# PowerISA II: 4.6.7.3 Floating Round to Integer Instructions +# CMT: Floating Round to Integer Toward Zero +# FORM: X-form +# binutils: 476.d: 2bc: fd 40 5b 51 friz. f10,f11 +# binutils: a2.d: 34c: fe 80 ab 51 friz. f20,f21 +define pcodeop FloatingRoundToIntegerTowardZero1; +:friz. fT,fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=0 & fB & XOP_1_10=424 & Rc=1 +{ + fT = trunc( fB ); + setFPRF(fT); + setSummaryFPSCR(); + cr1flags(); +} + +# ======================================================================= + +# PowerISA II: 4.4.4 Wait Instruction +# CMT: Wait +# FORM: X-form +# binutils: a2.d: 86c: 7c 00 00 7c wait +# binutils: a2.d: 870: 7c 00 00 7c wait +# binutils: e500mc.d: 1c: 7c 00 00 7c wait +# binutils: e500mc.d: 20: 7c 00 00 7c wait +# binutils: power7.d: 58: 7c 00 00 7c wait +# binutils: power7.d: 5c: 7c 00 00 7c wait +define pcodeop waitOp; +:wait BITS_21_22 is OP=31 & crfD=0 & BITS_21_22 & BITS_11_20=0 & XOP_1_10=62 & BIT_0=0 { waitOp(); } + +# ======================================================================= + +# PowerISA II: 4.3.1 System Linkage Instructions +# CMT: Return From Guest Interrupt [Category:Embedded.Hypervisor] +# FORM: XL-form +# binutils: e500mc.d: 0: 4c 00 00 4e rfdi +define pcodeop ReturnFromGuestInterrupt; +:rfgi is $(NOTVLE) & OP=19 & BITS_11_25=0 & XOP_1_10=102 & BIT_0=0 { + MSR = returnFromGuestInterrupt(MSR, spr17b); #GSRR1 + return[spr17a]; #GSRR0 +} + +# ======================================================================= + +# PowerISA II: 4.4.2.1 64-Bit Load and Reserve and Store Conditional Instructions [Category: 64-Bit] +# CMT: Load Doubleword And Reserve Indexed +# FORM: X-form +# binutils: a2.d: 410: 7d 4b 60 a8 ldarx r10,r11,r12 +# binutils: a2.d: 414: 7d 4b 60 a9 ldarx r10,r11,r12,1 +:ldarx TH,RA_OR_ZERO,B,BIT_0 is OP=31 & TH & RA_OR_ZERO & B & XOP_1_10=84 & BIT_0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO+B; + RESERVE = 1; + RESERVE_LENGTH = 8; + RESERVE_ADDRESS = ea; + TH = *:8 (ea); +} + +# ======================================================================= + +# PowerISA II: 4.4.1 Instruction Synchronize Instruction +# CMT: Load Word And Reserve Indexed +# FORM: X-form +# binutils: 476.d: 394: 7c 64 28 28 lwarx r3,r4,r5 +# binutils: 476.d: 398: 7c 64 28 28 lwarx r3,r4,r5 +# binutils: 476.d: 39c: 7c 64 28 29 lwarx r3,r4,r5,1 +# binutils: a2.d: 4b4: 7d 4b 60 28 lwarx r10,r11,r12 +# binutils: a2.d: 4b8: 7d 4b 60 29 lwarx r10,r11,r12,1 +:lwarx TH,RA_OR_ZERO,B,BIT_0 is OP=31 & TH & RA_OR_ZERO & B & XOP_1_10=20 & BIT_0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO+B; + RESERVE = 1; + RESERVE_LENGTH = 4; + RESERVE_ADDRESS = ea; + TH = zext( *:4 (ea) ); +} + +# ======================================================================= + +# PowerISA II: 11.3 Processor Control Instructions +# CMT: Message Clear +# FORM: X-form +# binutils: a2.d: 544: 7c 00 51 dc msgclr r10 +# binutils: e500mc.d: 14: 7c 00 69 dc msgclr r13 +define pcodeop MessageClear; +:msgclr B is OP=31 & BITS_21_25=0 & BITS_16_20=0 & B & XOP_1_10=238 & BIT_0=0 { MessageClear(B); } + +# PowerISA II: 11.3 Processor Control Instructions +# CMT: Message Send +# FORM: X-form +# binutils: a2.d: 548: 7c 00 51 9c msgsnd r10 +# binutils: e500mc.d: 18: 7c 00 71 9c msgsnd r14 +define pcodeop MessageSend; +:msgsnd B is OP=31 & BITS_21_25=0 & BITS_16_20=0 & B & XOP_1_10=206 & BIT_0=0 { MessageSend(); } + +# ======================================================================= + + +# PowerISA III: TLB Management Instructions (expanded by ISA 3.0) +# CMT: TLB Invalidate Entry (expands on form in ppc_instructions.sinc) +# FORM: X-form +:tlbie RB_OR_ZERO,RS_OR_ZERO,"2",BIT_17,BIT_16 is $(NOTVLE) & OP=31 & RS_OR_ZERO & RB_OR_ZERO & BIT_20=0 & BITS_18_19=2 & BIT_17 & BIT_16 & XOP_1_10=306 & BIT_0=0 { # RIC=2 + # RIC = 2 + # PRS = BIT_17 + # R = BIT_16 + TLBInvalidateEntry(RB_OR_ZERO,RS_OR_ZERO,2:1,BIT_17:1,BIT_16:1); +} +:tlbie RB_OR_ZERO,RS_OR_ZERO,BIT_18,BIT_17,"1" is $(NOTVLE) & OP=31 & RS_OR_ZERO & RB_OR_ZERO & BIT_20=0 & (BITS_18_19=0 | BITS_18_19=1) & BIT_18 & BIT_17 & BIT_16=1 & XOP_1_10=306 & BIT_0=0 { # RIC=0|1 & R=1 + # RIC = BITS_18_19 (0 or 1) + # PRS = BIT_17 + # R = 1 + TLBInvalidateEntry(RB_OR_ZERO,RS_OR_ZERO,BIT_18:1,BIT_17:1,1:1); +} +:tlbie RB_OR_ZERO,RS_OR_ZERO,"3","0","0" is $(NOTVLE) & OP=31 & RS_OR_ZERO & RB_OR_ZERO & BIT_20=0 & BITS_18_19=3 & BIT_17=0 & BIT_16=0 & XOP_1_10=306 & BIT_0=0 { # RIC=3 & PRS=0 & R=0 + # RIC = 3 + # PRS = 0 + # R = 0 + TLBInvalidateEntry(RB_OR_ZERO,RS_OR_ZERO,3:1,0:1,0:1); +} + +# PowerISA III: TLB Management Instructions (expanded by ISA 3.0) +# CMT: TLB Invalidate Entry Local (expands on form in ppc_instructions.sinc) +# FORM: X-form +:tlbiel RB_OR_ZERO,RS_OR_ZERO,"0","0","0" is $(NOTVLE) & OP=31 & RS_OR_ZERO & RB_OR_ZERO & BITS_16_20=0 & XOP_1_10=274 & BIT_0=0 { # RIC=0 & PRS=0 & R=0 + # RIC = 0 + # PRS = 0 + # R = 0 + TLBInvalidateEntryLocal(RB_OR_ZERO,RS_OR_ZERO,0:1,0:1,0:1); +} +:tlbiel RB_OR_ZERO,RS_OR_ZERO,"2",BIT_17,BIT_16 is $(NOTVLE) & OP=31 & RS_OR_ZERO & RB_OR_ZERO & BIT_20=0 & BITS_18_19=2 & BIT_17 & BIT_16 & XOP_1_10=274 & BIT_0=0 { # RIC=2 + # RIC = 2 + # PRS = BIT_17 + # R = BIT_16 + TLBInvalidateEntryLocal(RB_OR_ZERO,RS_OR_ZERO,2:1,BIT_17:1,BIT_16:1); +} +:tlbiel RB_OR_ZERO,RS_OR_ZERO,BIT_18,BIT_17,"1" is $(NOTVLE) & OP=31 & RS_OR_ZERO & RB_OR_ZERO & BIT_20=0 & (BITS_18_19=0 | BITS_18_19=1) & BIT_18 & BIT_17 & BIT_16=1 & XOP_1_10=274 & BIT_0=0 { # RIC=0|1 & R=1 + # RIC = BITS_18_19 (0 or 1) + # PRS = BIT_17 + # R = 1 + TLBInvalidateEntryLocal(RB_OR_ZERO,RS_OR_ZERO,BIT_18:1,BIT_17:1,1:1); +} + + +# PowerISA II: 6.11.4.9 TLB Management Instructions +# CMT: TLB Search and Reserve Indexed Category: Embedded.TLB Write Conditional] +# FORM: X-form +# binutils: a2.d: 848: 7c 0a 5e a5 tlbsrx\. r10,r11 +define pcodeop TLBSearchAndReserveIndexedCategory; +:tlbsrx. A,B is OP=31 & BITS_21_25=0 & A & B & XOP_1_10=850 & BIT_0=1 { TLBSearchAndReserveIndexedCategory(A,B,cr0); } + +# ======================================================================= + +# PowerISA II: 4.6.10 Floating-Point Status and Control Register Instructions +# CMT: Move To FPSCR Fields +# FORM: X-form +# binutils: 476.d: 4e0: fc 0c 55 8e mtfsf 6,f10 +# binutils: 476.d: 4e4: fc 0c 55 8e mtfsf 6,f10 +# binutils: 476.d: 4e8: fc 0d 55 8e mtfsf 6,f10,0,1 +# binutils: 476.d: 4ec: fe 0c 55 8e mtfsf 6,f10,1,0 +# binutils: a2.d: 580: fc 0c a5 8e mtfsf 6,f20 +# binutils: a2.d: 588: fc 0c a5 8e mtfsf 6,f20 +# binutils: a2.d: 590: fe 0d a5 8e mtfsf 6,f20,1,1 +# binutils: common.d: 210: fc 0c 55 8e mtfsf 6,f10 +# binutils: power6.d: b4: fc 0c 55 8e mtfsf 6,f10 +# binutils: power6.d: bc: fc 0c 55 8e mtfsf 6,f10 +# binutils: power6.d: c4: fc 0d 55 8e mtfsf 6,f10,0,1 +# binutils: power6.d: cc: fe 0c 55 8e mtfsf 6,f10,1,0 +define pcodeop MoveToFPSCRFields; +:mtfsf BITS_17_24,fB,BIT_25,BIT_16 is $(NOTVLE) & OP=63 & BIT_25 & BITS_17_24 & BIT_16 & fB & XOP_1_10=711 & Rc=0 { # PCODE + MoveToFPSCRFields(fB); +} + +# PowerISA II: 4.6.10 Floating-Point Status and Control Register Instructions +# CMT: Move To FPSCR Fields +# FORM: X-form +# binutils: 476.d: 4f0: fc 0c 5d 8f mtfsf. 6,f11 +# binutils: 476.d: 4f4: fc 0c 5d 8f mtfsf. 6,f11 +# binutils: 476.d: 4f8: fc 0d 5d 8f mtfsf. 6,f11,0,1 +# binutils: 476.d: 4fc: fe 0c 5d 8f mtfsf. 6,f11,1,0 +# binutils: a2.d: 57c: fc 0c a5 8f mtfsf. 6,f20 +# binutils: a2.d: 584: fc 0c a5 8f mtfsf. 6,f20 +# binutils: a2.d: 58c: fe 0d a5 8f mtfsf. 6,f20,1,1 +define pcodeop MoveToFPSCRFields1; +:mtfsf. BITS_17_24,fB,BIT_25,BIT_16 is $(NOTVLE) & OP=63 & BIT_25 & BITS_17_24 & BIT_16 & fB & XOP_1_10=711 & Rc=1 { # PCODE + MoveToFPSCRFields1(fB); +} + +# PowerISA II: 4.6.10 Floating-Point Status and Control Register Instructions +# CMT: Move To FPSCR Field Immediate +# FORM: X-form +# binutils: 476.d: 500: ff 00 01 0c mtfsfi 6,0 +# binutils: 476.d: 504: ff 00 01 0c mtfsfi 6,0 +# binutils: 476.d: 508: ff 00 01 0c mtfsfi 6,0 +# binutils: 476.d: 50c: ff 01 01 0c mtfsfi 6,0,1 +# binutils: a2.d: 598: ff 00 01 0c mtfsfi 6,0 +# binutils: a2.d: 5a0: ff 00 d1 0c mtfsfi 6,13 +# binutils: a2.d: 5a8: ff 01 d1 0c mtfsfi 6,13,1 +# binutils: common.d: 218: ff 00 01 0c mtfsfi 6,0 +# binutils: power6.d: d4: ff 00 01 0c mtfsfi 6,0 +# binutils: power6.d: dc: ff 00 01 0c mtfsfi 6,0 +# binutils: power6.d: e4: ff 01 01 0c mtfsfi 6,0,1 +define pcodeop MoveToFPSCRFieldImmediate; +:mtfsfi BF2,BITS_12_15,BIT_16 is $(NOTVLE) & OP=63 & BF2 & BITS_21_22=0 & BITS_17_20=0 & BIT_16 & BITS_12_15 & BIT_11=0 & XOP_1_10=134 & Rc=0 { + MoveToFPSCRFieldImmediate(); +} + +# PowerISA II: 4.6.10 Floating-Point Status and Control Register Instructions +# CMT: Move To FPSCR Field Immediate +# FORM: X-form +# binutils: 476.d: 510: ff 00 f1 0d mtfsfi. 6,15 +# binutils: 476.d: 514: ff 00 f1 0d mtfsfi. 6,15 +# binutils: 476.d: 518: ff 00 f1 0d mtfsfi. 6,15 +# binutils: 476.d: 51c: ff 01 f1 0d mtfsfi. 6,15,1 +# binutils: a2.d: 594: ff 00 01 0d mtfsfi. 6,0 +# binutils: a2.d: 59c: ff 00 d1 0d mtfsfi. 6,13 +# binutils: a2.d: 5a4: ff 01 d1 0d mtfsfi. 6,13,1 +define pcodeop MoveToFPSCRFieldImmediate1; +:mtfsfi. BITS_23_25,BITS_12_15,BIT_16 is $(NOTVLE) & OP=63 & BITS_23_25 & BITS_21_22=0 & BITS_17_20=0 & BIT_16 & BITS_12_15 & BIT_11=0 & XOP_1_10=134 & Rc=1 { + MoveToFPSCRFieldImmediate1(); +} + +# ======================================================================= + +# PowerISA II: 3.3.15 Move To/From System Register Instructions +# CMT: Move To Condition Register Fields +# FORM: XFX-form +# binutils: 476.d: 48c: 7c 60 00 26 mfcr r3 +define pcodeop mfcrOp; +:mfcr TO is OP=31 & TO & BIT_20=0 & BITS_12_19=0 & XOP_1_10=190 & BIT_0=0 { mfcrOp(); } + +# ======================================================================= + +# PowerISA II: 5.6.1 DFP Arithmetic Instructions +# CMT: DFP Add [Quad] +# FORM: X-form +# binutils: power6.d: 38: fe 96 c0 04 daddq f20,f22,f24 +# binutils: power7.d: 9c: fe 96 c0 04 daddq f20,f22,f24 +define pcodeop daddqOp; +:daddq fT,fA,fB is $(NOTVLE) & OP=63 & fT & fA & fB & XOP_1_10=2 & Rc=0 { daddqOp(fA,fB); } + +# PowerISA II: 5.6.1 DFP Arithmetic Instructions +# CMT: DFP Add [Quad] +# FORM: X-form +define pcodeop daddqDotOp; +:daddq. fT,fA,fB is $(NOTVLE) & OP=63 & fT & fA & fB & XOP_1_10=2 & Rc=1 { daddqDotOp(fA); } + +# ======================================================================= + +# ======================================================================= +# binutils: 476.d: 30c: 7d ae 7b cc icbtls 13,r14,r15 +# binutils: a2.d: 3c4: 7c 0a 5b cc icbtls r10,r11 +# binutils: a2.d: 3c8: 7c ea 5b cc icbtls 7,r10,r11 +# binutils: e500.d: 10: 7d ae 7b cc icbtls 13,r14,r15 +# binutils: titan.d: 198: 7c 02 0b cc icbtls r2,r1 +# binutils: titan.d: 19c: 7c 02 0b cc icbtls r2,r1 +# binutils: titan.d: 1a0: 7c 22 0b cc icbtls 1,r2,r1 +# :icbtls BITS_21_24,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & BIT_25=0 & BITS_21_24 & B & XOP_1_10=486 & BIT_0=0 & RA_OR_ZERO +# { +# ea = RA_OR_ZERO + B; +# # prefetchInstructionCacheBlockLockSetX(ea); +# } +# Source for information on instructions: +# PowerISA_V2.06B_PUBLIC.pdf (dated: July 23, 2010) +# and binutils-2.21.1 +# Have test case for about 200 of these instructions + +# Extended Mnemonic +# xvmovdp XT,XB => xvcpsgndp XT,XB,XB +# xvmovsp XT,XB => xvcpsgnsp XT,XB,XB +# xxmrghd T,A,B => xxpermdi T,A,B,0b00 +# xxmrgld T,A,B => xxpermdi T,A,B,0b11 +# xxspltd T,A,0 => xxpermdi T,A,A,0b00 +# xxswapd T,A => xxpermdi T,A,A,0b10 + +@include "vsx.sinc" + +# binutils-descr: "brinc", VX (4, 527), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB} +define pcodeop brincOp; +# ISA-cmt: brinc - Bit Reversed Increment +# ISA-info: brinc - Form "EVX" Page 510 Category "SP" +# binutils: mytest.d: 1d0: 10 22 1a 0f brinc r1,r2,r3 +:brinc S,A,B is OP=4 & XOP_0_10=527 & S & A & B { brincOp(S,A,B); } + +# binutils-descr: "hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476, {0} +define pcodeop hrfidOp; +# ISA-info: hrfid - Form "XL" Page 739 Category "S" +# binutils: mytest.d: 0: 4c 00 02 24 hrfid +:hrfid is $(NOTVLE) & OP=19 & XOP_1_10=274 & BITS_11_25=0 & BIT_0=0 { hrfidOp(); } + +define pcodeop bcctrOp; +# ZZZ NO-PARSE XLLK - "bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH} +:bcctr BO,BI_BITS,BH is $(NOTVLE) & OP=19 & BO & BI_BITS & BITS_13_15=0 & BH & XOP_1_10=528 & LK=0 { bcctrOp(); } + +define pcodeop bcctrlOp; +# ZZZ NO-PARSE XLLK - "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH} +:bcctrl BO,BI_BITS,BH is $(NOTVLE) & OP=19 & BO & BI_BITS & BITS_13_15=0 & BH & XOP_1_10=528 & LK=1 { bcctrlOp(); } + +# binutils-descr: "lbarx", X(31,52), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH} +define pcodeop lbarxOp; +# ISA-cmt: lbarx - Load Byte and Reserve Indexed +# ISA-info: lbarx - Form "X" Page 689 Category "B" +# binutils: power7.d: 14c: 7d 4b 60 68 lbarx r10,r11,r12 +# binutils: power7.d: 150: 7d 4b 60 68 lbarx r10,r11,r12 +# binutils: power7.d: 154: 7d 4b 60 69 lbarx r10,r11,r12,1 +:lbarx RT,A,B,BIT_0 is OP=31 & XOP_1_10=52 & RT & A & B & BIT_0 { + A = A + B; + RT = *:1 A; +} + +# binutils-descr: "lharx", X(31,116), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH} +define pcodeop lharxOp; +# ISA-cmt: lharx - Load Halfword and Reserve Indexed +# ISA-info: lharx - Form "X" Page 690 Category "B" +# binutils: power7.d: 158: 7e 95 b0 e8 lharx r20,r21,r22 +# binutils: power7.d: 15c: 7e 95 b0 e8 lharx r20,r21,r22 +# binutils: power7.d: 160: 7e 95 b0 e9 lharx r20,r21,r22,1 +:lharx RT,A,B,BIT_0 is OP=31 & XOP_1_10=116 & RT & A & B & BIT_0 { + A = A + B; + RT = *:2 A; +} + +# binutils-descr: "ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, PPCNONE, {0} +define pcodeop ehprivOp; +# ISA-info: ehpriv - Form "XL" Page 889 Category "E.HV" +# binutils: NO-EXAMPLE - ehpriv +:ehpriv BITS_11_25 is OP=31 & BITS_11_25 & XOP_1_10=270 & BIT_0=0 { ehprivOp(); } + +# binutils-descr: "cbcdtd", X(31,314), XRB_MASK, POWER6, PPCNONE, {RA, RS} +define pcodeop cbcdtdOp; +# ISA-info: cbcdtd - Form "X" Page 97 Category "BCDA" +# binutils: power6.d: ec: 7d 6a 02 74 cbcdtd r10,r11 +:cbcdtd S,A is $(NOTVLE) & OP=31 & S & A & BITS_11_15=0 & XOP_1_10=314 & BIT_0=0 { cbcdtdOp(S,A); } + +# binutils-descr: "divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB} +define pcodeop divdeuOp; +# binutils: mytest.d: 4: 7c 64 2b 12 divdeu r3,r4,r5 +:divdeu RT,A,B is $(NOTVLE) & OP=31 & XOP_1_9=393 & OE=0 & Rc=0 & RT & A & B { + RT = A/B; +} + +# binutils-descr: "divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB} +define pcodeop divdeuDotOp; +# binutils: mytest.d: 8: 7c 64 2b 13 divdeu. r3,r4,r5 +:divdeu. RT,A,B is $(NOTVLE) & OP=31 & XOP_1_9=393 & OE=0 & Rc=1 & RT & A & B { + RT = A/B; + cr0flags(RT); +} + +# binutils-descr: "divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB} +define pcodeop divdeOp; +# binutils: mytest.d: c: 7c 64 2b 52 divde r3,r4,r5 +:divde RT,A,B is $(NOTVLE) & OP=31 & XOP_1_9=425 & OE=0 & Rc=0 & RT & A & B { + RT = A s/ B; +} + +# binutils-descr: "divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB} +define pcodeop divdeDotOp; +# binutils: mytest.d: 10: 7c 64 2b 53 divde. r3,r4,r5 +:divde. RT,A,B is $(NOTVLE) & OP=31 & XOP_1_9=425 & OE=0 & Rc=1 & RT & A & B { + RT = A s/ B; + cr0flags(RT); +} + +# binutils-descr: "dsn", X(31,483), XRT_MASK, E500MC, PPCNONE, {RA, RB} +define pcodeop dsnOp; +# ISA-info: dsn - Form "X" Page 710 Category "DS" +# binutils: e500mc.d: 3c: 7c 18 cb c6 dsn r24,r25 +:dsn A,B is OP=31 & XOP_1_10=483 & A & B & BITS_21_25=0 & BIT_0=0 { dsnOp(A,B); } + +# binutils-descr: "lbdx", X(31,515), X_MASK, E500MC, PPCNONE, {RT, RA, RB} +define pcodeop lbdxOp; +# ISA-info: lbdx - Form "X" Page 708 Category "DS" +# binutils: e500mc.d: 68: 7c 01 14 06 lbdx r0,r1,r2 +:lbdx RT,A,B is OP=31 & XOP_1_10=515 & RT & A & B & BIT_0=0 { RT = lbdxOp(RT,A,B); } + +# binutils-descr: "lhdx", X(31,547), X_MASK, E500MC, PPCNONE, {RT, RA, RB} +define pcodeop lhdxOp; +# ISA-info: lhdx - Form "X" Page 708 Category "DS" +# binutils: e500mc.d: 6c: 7d 8d 74 46 lhdx r12,r13,r14 +:lhdx RT,A,B is OP=31 & XOP_1_10=547 & RT & A & B & BIT_0=0 { RT = lhdxOp(RT,A,B); } + +# binutils-descr: "lwdx", X(31,579), X_MASK, E500MC, PPCNONE, {RT, RA, RB} +define pcodeop lwdxOp; +# ISA-info: lwdx - Form "X" Page 708 Category "DS" +# binutils: e500mc.d: 70: 7c 64 2c 86 lwdx r3,r4,r5 +:lwdx RT,A,B is OP=31 & XOP_1_10=579 & RT & A & B & BIT_0=0 { RT = lwdxOp(RT,A,B); } + +# binutils-descr: "lddx", X(31,611), X_MASK, E500MC, PPCNONE, {RT, RA, RB} +define pcodeop lddxOp; +# ISA-info: lddx - Form "X" Page 708 Category "DS" +# binutils: e500mc.d: 78: 7d f0 8c c6 lddx r15,r16,r17 +:lddx RT,A,B is OP=31 & XOP_1_10=611 & RT & A & B & BIT_0=0 { RT = lddxOp(RT,A,B); } + +# ISA-info: lddx - Form "X" Page 50 Category "DS" +:ldx RT,RA_OR_ZERO,B is OP=31 & XOP_1_10=21 & RT & RA_OR_ZERO & B & BIT_0=0 { + RT = *:8 (RA_OR_ZERO + B); +} + +# binutils-descr: "stbdx", X(31,643), X_MASK, E500MC, PPCNONE, {RS, RA, RB} +define pcodeop stbdxOp; +# ISA-info: stbdx - Form "X" Page 709 Category "DS" +# binutils: e500mc.d: 7c: 7c c7 45 06 stbdx r6,r7,r8 +:stbdx S,A,B is OP=31 & XOP_1_10=643 & S & A & B & BIT_0=0 { *[ram]:1 B =stbdxOp(S,A,B); } + +# binutils-descr: "sthdx", X(31,675), X_MASK, E500MC, PPCNONE, {RS, RA, RB} +define pcodeop sthdxOp; +# ISA-info: sthdx - Form "X" Page 709 Category "DS" +# binutils: e500mc.d: 80: 7e 53 a5 46 sthdx r18,r19,r20 +:sthdx S,A,B is OP=31 & XOP_1_10=675 & S & A & B & BIT_0=0 { *[ram]:2 B = sthdxOp(S,A,B); } + +# binutils-descr: "stwdx", X(31,707), X_MASK, E500MC, PPCNONE, {RS, RA, RB} +define pcodeop stwdxOp; +# ISA-info: stwdx - Form "X" Page 709 Category "DS" +# binutils: e500mc.d: 84: 7d 2a 5d 86 stwdx r9,r10,r11 +:stwdx S,A,B is OP=31 & XOP_1_10=707 & S & A & B & BIT_0=0 { *[ram]:4 B = stwdxOp(S,A,B); } + +# binutils-descr: "sthcx.", XRC(31,726,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB} +define pcodeop sthcxDotOp; +# ISA-info: sthcx. - Form "X" Page 692 Category "B" +# binutils: mytest.d: 14: 7c 64 2d ad sthcx. r3,r4,r5 +:sthcx. S,RA_OR_ZERO,B is OP=31 & XOP_1_10=726 & Rc=1 & S & RA_OR_ZERO & B { + EA:$(REGISTER_SIZE) = RA_OR_ZERO + B; + *[ram]:2 EA = sthcxDotOp(S,RA_OR_ZERO,B); + setCrBit(cr0, 2, 1); +} + +# binutils-descr: "stddx", X(31,739), X_MASK, E500MC, PPCNONE, {RS, RA, RB} +define pcodeop stddxOp; +# ISA-cmt: stddx - Store Doubleword with Decoration Indexed +# ISA-info: stddx - Form "X" Page 709 Category "DS" +# binutils: e500mc.d: 8c: 7e b6 bd c6 stddx r21,r22,r23 +:stddx S,A,B is OP=31 & XOP_1_10=739 & S & A & B & BIT_0=0 { *[ram]:8 B = stddxOp(S,A,B); } + +# binutils-descr: "lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRT, RA, RB} +define pcodeop lfdpxOp; +# ISA-cmt: lfdpx - Load Floating-Point Double Pair Indexed +# ISA-info: lfdpx - Form "X" Page 131 Category "FP.out" +# binutils: power6.d: 30: 7d ae 7e 2e lfdpx f13,r14,r15 +:lfdpx fT,A,B is $(NOTVLE) & OP=31 & XOP_1_10=791 & fT & A & B & BIT_0=0 { fT = lfdpxOp(fT,A,B); } + +# binutils-descr: "lfddx", X(31,803), X_MASK, E500MC, PPCNONE, {FRT, RA, RB} +define pcodeop lfddxOp; +# ISA-cmt: lfddx - Load Floating Doubleword with Decoration Indexed +# ISA-info: lfddx - Form "X" Page 708 Category "DS" +# binutils: e500mc.d: 74: 7f 5b e6 46 lfddx f26,r27,r28 +:lfddx fT,A,B is OP=31 & XOP_1_10=803 & fT & A & B & BIT_0=0 { fT = lfddxOp(fT,A,B); } + +# binutils-descr: "lhzcix", X(31,821), X_MASK, POWER6, PPCNONE, {RT, RA0, RB} +define pcodeop lhzcixOp; +# ISA-cmt: lhzcix - Load Halfword and Zero Caching Inhibited Indexed +# ISA-info: lhzcix - Form "X" Page 749 Category "S" +# binutils: mytest.d: 18: 7c 64 2e 6a lhzcix r3,r4,r5 +:lhzcix RT,A,B is $(NOTVLE) & OP=31 & XOP_1_10=821 & RT & A & B & BIT_0=0 { + A = A + B; + RT = *:2 A; +} + +# binutils-descr: "lbzcix", X(31,853), X_MASK, POWER6, PPCNONE, {RT, RA0, RB} +define pcodeop lbzcixOp; +# ISA-cmt: lbzcix - Load Byte and Zero Caching Inhibited Indexed +# ISA-info: lbzcix - Form "X" Page 749 Category "S" +# binutils: mytest.d: 1c: 7c 64 2e aa lbzcix r3,r4,r5 +:lbzcix RT,A,B is $(NOTVLE) & OP=31 & XOP_1_10=853 & RT & A & B & BIT_0=0 { + A = A + B; + RT = *:1 A; +} + +# binutils-descr: "eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0} +define pcodeop eieioOp; +# ISA-cmt: eieio - Enforce In-order Execution of I/O +# ISA-info: eieio - Form "X" Page 698 Category "S" +# binutils: mytest.d: 20: 7c 00 06 ac eieio +:eieio is $(NOTVLE) & OP=31 & XOP_1_10=854 & BITS_11_25=0 & BIT_0=0 { eieioOp(); } + + +# binutils-descr: "ldcix", X(31,885), X_MASK, POWER6, PPCNONE, {RT, RA0, RB} +# ISA-cmt: ldcix - Load Doubleword Caching Inhibited Indexed +# ISA-info: ldcix - Form "X" Page 749 Category "S" +# binutils: mytest.d: 24: 7c 64 2e ea ldcix r3,r4,r5 +:ldcix RT,A,B is $(NOTVLE) & OP=31 & XOP_1_10=885 & RT & A & B & BIT_0=0 { + A = A + B; + RT = *:8 A; +} + +# binutils-descr: "divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB} +# binutils: mytest.d: 28: 7c 64 2f 12 divdeuo r3,r4,r5 +:divdeuo RT,A,B is $(NOTVLE) & OP=31 & XOP_1_9=393 & OE=1 & Rc=0 & RT & A & B { + divOverflow(A,B); + RT = A/B; +} + +# binutils-descr: "divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB} +define pcodeop divdeuoDotOp; +# binutils: mytest.d: 2c: 7c 64 2f 13 divdeuo. r3,r4,r5 +:divdeuo. RT,A,B is $(NOTVLE) & OP=31 & XOP_1_9=393 & OE=1 & Rc=1 & RT & A & B { + divOverflow(A,B); + RT = A/B; + cr0flags(RT); +} + +# binutils-descr: "stwcix", X(31,917), X_MASK, POWER6, PPCNONE, {RS, RA0, RB} +define pcodeop stwcixOp; +# ISA-cmt: stwcix - Store Word Caching Inhibited Indexed +# ISA-info: stwcix - Form "X" Page 750 Category "S" +# binutils: mytest.d: 30: 7c 64 2f 2a stwcix r3,r4,r5 +:stwcix S,A,B is $(NOTVLE) & OP=31 & XOP_1_10=917 & S & A & B & BIT_0=0 { + A = A + B; + *:4 A = S; +} + +# binutils-descr: "stfdpx", X(31,919), X_MASK, POWER6, PPCNONE, {FRS, RA, RB} +define pcodeop stfdpxOp; +# ISA-cmt: stfdpx - Store Floating-Point Double Pair Indexed +# ISA-info: stfdpx - Form "X" Page 131 Category "FP.out" +# binutils: mytest.d: 34: 7c 64 2f 2e stfdpx f3,r4,r5 +:stfdpx fS,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & XOP_1_10=919 & fS & RA_OR_ZERO & B & BIT_0=0 { + EA:$(REGISTER_SIZE) = RA_OR_ZERO + B; + *[ram]:8 EA = stfdpxOp(fS,RA_OR_ZERO,B); +} + +# binutils-descr: "stfddx", X(31,931), X_MASK, E500MC, PPCNONE, {FRS, RA, RB} +define pcodeop stfddxOp; +# ISA-info: stfddx - Form "X" Page 709 Category "DS" +# binutils: e500mc.d: 88: 7f be ff 46 stfddx f29,r30,r31 +:stfddx fS,A,B is OP=31 & XOP_1_10=931 & fS & A & B & BIT_0=0 { *[ram]:8 B = stfddxOp(fS,A,B); } + +# binutils-descr: "divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB} +define pcodeop divdeoOp; +# binutils: mytest.d: 38: 7c 64 2f 52 divdeo r3,r4,r5 +:divdeo RT,A,B is $(NOTVLE) & OP=31 & XOP_1_9=425 & OE=1 & Rc=0 & RT & A & B { + divOverflow(A,B); + RT = A s/ B; +} + +# binutils-descr: "divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB} +define pcodeop divdeoDotOp; +# binutils: mytest.d: 3c: 7c 64 2f 53 divdeo. r3,r4,r5 +:divdeo. RT,A,B is $(NOTVLE) & OP=31 & XOP_1_9=425 & OE=1 & Rc=1 & RT & A & B { + divOverflow(A,B); + RT = A s/ B; + cr0flags(RT); +} + +# binutils-descr: "sthcix", X(31,949), X_MASK, POWER6, PPCNONE, {RS, RA0, RB} +define pcodeop sthcixOp; +# ISA-info: sthcix - Form "X" Page 750 Category "S" +# binutils: mytest.d: 40: 7c 64 2f 6a sthcix r3,r4,r5 +:sthcix S,A,B is $(NOTVLE) & OP=31 & XOP_1_10=949 & S & A & B & BIT_0=0 { + A = A + B; + *:2 A = S; +} + +define pcodeop slbfeeDotOp; +# ISA-info: slbfee - Form "X" Page 794 Category "?" +:slbfee. RT,B is $(NOTVLE) & OP=31 & RT & BITS_16_20=0 & B & XOP_1_10=979 & BIT_0=1 { slbfeeDotOp(RT,B); } + +# binutils-descr: "stbcix", X(31,981), X_MASK, POWER6, PPCNONE, {RS, RA0, RB} +define pcodeop stbcixOp; +# ISA-info: stbcix - Form "X" Page 750 Category "S" +# binutils: mytest.d: 44: 7c 64 2f aa stbcix r3,r4,r5 +:stbcix S,A,B is $(NOTVLE) & OP=31 & XOP_1_10=981 & S & A & B & BIT_0=0 { + A = A + B; + *:1 A = A; +} + +# binutils-descr: "stdcix", X(31,1013), X_MASK, POWER6, PPCNONE, {RS, RA0, RB} +define pcodeop stdcixOp; +# ISA-info: stdcix - Form "X" Page 750 Category "S" +# binutils: mytest.d: 48: 7c 64 2f ea stdcix r3,r4,r5 +:stdcix S,A,B is $(NOTVLE) & OP=31 & XOP_1_10=1013 & S & A & B & BIT_0=0 { + A = A + B; + *:8 A = S; +} + +# binutils-descr: "lq", OP(56), OP_MASK, POWER4, PPC476, {RTQ, DQ, RAQ} +# ISA-cmt: lq - Load Quadword +# ISA-info: lq - Form "DQ" Page 751 Category "LSQ" +# binutils: power4.d: +0: e0 83 00 00 lq r4,0\(r3\) +# binutils: power4.d: +4: e0 83 00 00 lq r4,0\(r3\) +:lq RT,A,DQ is $(NOTVLE) & OP=56 & RT & Dp & A & DQ & BITS_0_3=0 & regp [regpset = Dp+1;] { + ea:$(REGISTER_SIZE) = A + sext(DQ:2 << 4); +@if ENDIAN == "big" + RT = *:$(REGISTER_SIZE) ea; + regp = *:$(REGISTER_SIZE) (ea + $(REGISTER_SIZE)); +@else + RT = *:$(REGISTER_SIZE) (ea + $(REGISTER_SIZE)); + regp = *:$(REGISTER_SIZE) ea; +@endif +} + +define pcodeop lvepxOp; +:lvepx RT,A,B is OP=31 & RT & A & B & XOP_1_10=295 & BIT_0=0 { RT = lvepxOp(RT,A,B); } + +define pcodeop lvepxlOp; +:lvepxl RT,A,B is OP=31 & RT & A & B & XOP_1_10=263 & BIT_0=0 { RT = lvepxlOp(RT,A,B); } + +# binutils-descr: "lfdp", OP(57), OP_MASK, POWER6, POWER7, {FRT, D, RA0} +define pcodeop lfdpOp; +# ISA-cmt: lfdp - Load Floating-Point Double Pair +# ISA-info: lfdp - Form "DS" Page 131 Category "FP.out" +# binutils: NO-EXAMPLE - lfdp +:lfdp fT,A,DS is $(NOTVLE) & OP=57 & fT & A & DS & BITS_0_1=0 { fT = lfdpOp(fT,A,DS:2); } + +# binutils-descr: "dadd", XRC(59,2,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB} +define pcodeop daddOp; +# ISA-cmt: dadd - DFP Add +# binutils: power6.d: 34: ee 11 90 04 dadd f16,f17,f18 +# binutils: power7.d: 98: ee 11 90 04 dadd f16,f17,f18 +:dadd fT,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=2 & Rc=0 & fT & fA & fB { daddOp(fT,fA,fB); } + +# binutils-descr: "dadd.", XRC(59,2,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB} +define pcodeop daddDotOp; +# ISA-cmt: dadd. - DFP Add Rc +# binutils: mytest.d: 50: ec 43 20 05 dadd. f2,f3,f4 +:dadd. fT,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=2 & Rc=1 & fT & fA & fB { daddDotOp(fT,fA,fB); } + +# binutils-descr: "dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC} +define pcodeop dquaOp; +# ISA-cmt: dqua - DFP Quantize +# binutils: mytest.d: 54: ec 22 18 06 dqua f1,f2,f3,0 +:dqua fT,fA,fB,RMC is $(NOTVLE) & OP=59 & XOP_1_8=3 & Rc=0 & fT & fA & fB & RMC { dquaOp(fT,fA,fB); } + +# binutils-descr: "dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC} +define pcodeop dquaDotOp; +# ISA-cmt: dqua. - DFP Quantize Rc +# binutils: mytest.d: 58: ec 22 18 07 dqua. f1,f2,f3,0 +:dqua. fT,fA,fB,RMC is $(NOTVLE) & OP=59 & XOP_1_8=3 & Rc=1 & fT & fA & fB & RMC { dquaDotOp(fT,fA,fB); } + +# binutils-descr: "dmul", XRC(59,34,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB} +define pcodeop dmulOp; +# ISA-cmt: dmul - DFP Multiply +# binutils: mytest.d: 5c: ec 43 20 44 dmul f2,f3,f4 +:dmul fT,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=34 & Rc=0 & fT & fA & fB { dmulOp(fT,fA,fB); } + +# binutils-descr: "dmul.", XRC(59,34,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB} +define pcodeop dmulDotOp; +# ISA-cmt: dmul. - DFP Multiply Rc +# binutils: mytest.d: 60: ec 43 20 45 dmul. f2,f3,f4 +:dmul. fT,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=34 & Rc=1 & fT & fA & fB { dmulDotOp(fT,fA,fB); } + +# binutils-descr: "drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC} +define pcodeop drrndOp; +# ISA-cmt: drrnd - DFP Reround +# binutils: mytest.d: 64: ec 43 20 46 drrnd f2,f3,f4,0 +:drrnd fT,fA,fB,RMC is $(NOTVLE) & OP=59 & XOP_1_8=35 & Rc=0 & fT & fA & fB & RMC { drrndOp(fT,fA,fB); } + +# binutils-descr: "drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC} +define pcodeop drrndDotOp; +# ISA-cmt: drrnd. - DFP Reround Rc +# binutils: mytest.d: 68: ec 43 20 47 drrnd. f2,f3,f4,0 +:drrnd. fT,fA,fB,RMC is $(NOTVLE) & OP=59 & XOP_1_8=35 & Rc=1 & fT & fA & fB & RMC { drrndDotOp(fT,fA,fB); } + +# binutils-descr: "dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16} +define pcodeop dscliOp; +# ISA-cmt: dscli - DFP Shift Significand Left Immediate +# binutils: mytest.d: 6c: ec 43 10 84 dscli f2,f3,4 +# Y {OP 0 5 {}} {fT 6 10 {}} {fA 11 15 {}} {SH16 16 21 {}} {XOP_1_9 22 30 {}} {Rc 31 31 {}} +# X 00--------------------------05 06---------------------10 11---------------------15 16--------------------------21 22-----------------------------------------30 31-31 +# X --------OP=111011(59)---------|-----------fT------------|-----------fA------------|-------------SH16-------------|-------------XOP_1_9=1000010(66)-------------|Rc=0-| +:dscli fT,fA,SH16 is $(NOTVLE) & OP=59 & XOP_1_9=66 & Rc=0 & fT & fA & SH16 { dscliOp(fT,fA); } + +# binutils-descr: "dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16} +define pcodeop dscliDotOp; +# ISA-cmt: dscli. - DFP Shift Significand Left Immediate Rc +# binutils: mytest.d: 70: ec 43 10 85 dscli. f2,f3,4 +:dscli. fT,fA,SH16 is $(NOTVLE) & OP=59 & XOP_1_9=66 & Rc=1 & fT & fA & SH16 { dscliDotOp(fT,fA); } + +# binutils-descr: "dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCNONE, {TE, FRT,FRB,RMC} +define pcodeop dquaiOp; +# ISA-cmt: dquai - DFP Quantize Immediate +# binutils: mytest.d: 74: ec 62 20 86 dquai 2,f3,f4,0 +:dquai fT,BITS_16_20,fB,RMC is $(NOTVLE) & OP=59 & fT & BITS_16_20 & fB & RMC & XOP_1_8=67 & Rc=0 { dquaiOp(fT,fB); } + +# binutils-descr: "dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCNONE, {TE, FRT,FRB,RMC} +define pcodeop dquaiDotOp; +# ISA-cmt: dquai. - DFP Quantize Immediate Rc +# binutils: mytest.d: 78: ec 62 20 87 dquai. 2,f3,f4,0 +:dquai. fT,BITS_16_20,fB,RMC is $(NOTVLE) & OP=59 & fT & BITS_16_20 & fB & RMC & XOP_1_8=67 & Rc=1 { dquaiDotOp(fT,fB); } + +# binutils-descr: "dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16} +define pcodeop dscriOp; +# ISA-cmt: dscri - DFP Shift Significand Right Immediate +# binutils: mytest.d: 7c: ec 43 10 c4 dscri f2,f3,4 +:dscri fT,fA,SH16 is $(NOTVLE) & OP=59 & XOP_1_9=98 & Rc=0 & fT & fA & SH16 { dscriOp(fT,fA); } + +# binutils-descr: "dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16} +define pcodeop dscriDotOp; +# ISA-cmt: dscri. - DFP Shift Significand Right Immediate Rc +# binutils: mytest.d: 80: ec 43 10 c5 dscri. f2,f3,4 +:dscri. fT,fA,SH16 is $(NOTVLE) & OP=59 & XOP_1_9=98 & Rc=1 & fT & fA & SH16 { dscriDotOp(fT,fA); } + +# binutils-descr: "drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC} +define pcodeop drintxOp; +# ISA-cmt: drintx - DFP Round To FP Integer With Inexact +# binutils: mytest.d: 84: ec 61 20 c6 drintx 1,f3,f4,0 +:drintx fT,fB,RMC is $(NOTVLE) & OP=59 & fT & BITS_17_20=0 & BIT_16 & fB & RMC & XOP_1_8=99 & Rc=0 { drintxOp(fT,fB); } + +# binutils-descr: "drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC} +define pcodeop drintxDotOp; +# ISA-cmt: drintx - DFP Round To FP Integer With Inexact +# binutils: mytest.d: 84: ec 61 20 c6 drintx 1,f3,f4,0 +:drintx. fT,fB,RMC is $(NOTVLE) & OP=59 & fT & BITS_17_20=0 & BIT_16 & fB & RMC & XOP_1_8=99 & Rc=1 { drintxDotOp(fT,fB); } + +# binutils-descr: "dcmpo", X(59,130), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB} +define pcodeop dcmpoOp; +# ISA-cmt: dcmpo - DFP Compare Ordered +# ISA-info: dcmpo - Form "X" Page 179 Category "DFP" +# binutils: mytest.d: 8c: ed 03 21 04 dcmpo cr2,f3,f4 +:dcmpo CRFD,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=130 & CRFD & fA & fB & BITS_21_22=0 & BIT_0=0 { dcmpoOp(CRFD,fA,fB); } + +# binutils-descr: "dtstex", X(59,162), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB} +define pcodeop dtstexOp; +# ISA-cmt: dtstex - DFP Test Exponent +# ISA-info: dtstex - Form "X" Page 181 Category "DFP" +# binutils: mytest.d: 90: ed 03 21 44 dtstex cr2,f3,f4 +:dtstex CRFD,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=162 & CRFD & fA & fB & BITS_21_22=0 & BIT_0=0 { dtstexOp(CRFD,fA,fB); } + +# binutils-descr: "dtstdc", Z(59,194), Z_MASK, POWER6, PPCNONE, {BF, FRA, DCM} +define pcodeop dtstdcOp; +# ISA-cmt: dtstdc - DFP Test Data Class +# ISA-info: dtstdc - Form "Z23" Page 180 Category "DFP" +# binutils: mytest.d: 94: ed 03 11 84 dtstdc cr2,f3,4 +:dtstdc CRFD,fA,DCM is $(NOTVLE) & OP=59 & XOP_1_9=194 & CRFD & fA & DCM & BITS_21_22=0 & BIT_0=0 { dtstdcOp(CRFD,fA); } + +# binutils-descr: "dtstdg", Z(59,226), Z_MASK, POWER6, PPCNONE, {BF, FRA, DGM} +define pcodeop dtstdgOp; +# ISA-cmt: dtstdg - DFP Test Data Group +# ISA-info: dtstdg - Form "Z23" Page 180 Category "DFP" +# binutils: mytest.d: 98: ed 03 11 c4 dtstdg cr2,f3,4 +:dtstdg CRFD,fA,DGM is $(NOTVLE) & OP=59 & XOP_1_9=226 & CRFD & fA & DGM & BITS_21_22=0 & BIT_0=0 { dtstdgOp(CRFD,fA); } + +# binutils-descr: "drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC} +define pcodeop drintnOp; +# ISA-cmt: drintn - DFP Round To FP Integer Without Inexact +# binutils: mytest.d: 9c: ec 61 21 c6 drintn 1,f3,f4,0 +:drintn fT,fB,RMC is $(NOTVLE) & OP=59 & XOP_1_8=227 & Rc=0 & BIT_16 & fT & fB & RMC & BITS_17_20=0 { drintnOp(fT,fB); } + +# binutils-descr: "drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC} +define pcodeop drintnDotOp; +# ISA-cmt: drintn. - DFP Round To FP Integer Without Inexact Rc +# binutils: mytest.d: a0: ec 61 21 c7 drintn. 1,f3,f4,0 +:drintn. fT,fB,RMC is $(NOTVLE) & OP=59 & XOP_1_8=227 & Rc=1 & BIT_16 & fT & fB & RMC & BITS_17_20=0 { drintnDotOp(fT,fB); } + +# binutils-descr: "dctdp", XRC(59,258,0), X_MASK, POWER6, PPCNONE, {FRT, FRB} +define pcodeop dctdpOp; +# ISA-cmt: dctdp - DFP Convert To DFP Long +# binutils: mytest.d: a4: ec 40 1a 04 dctdp f2,f3 +:dctdp fT,fB is $(NOTVLE) & OP=59 & XOP_1_10=258 & Rc=0 & fT & fB & BITS_16_20=0 { dctdpOp(fT,fB); } + +# binutils-descr: "dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCNONE, {FRT, FRB} +define pcodeop dctdpDotOp; +# ISA-cmt: dctdp. - DFP Convert To DFP Long Rc +# binutils: mytest.d: a8: ec 40 1a 05 dctdp. f2,f3 +:dctdp. fT,fB is $(NOTVLE) & OP=59 & XOP_1_10=258 & Rc=1 & fT & fB & BITS_16_20=0 { dctdpDotOp(fT,fB); } + +# binutils-descr: "dctfix", XRC(59,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRB} +define pcodeop dctfixOp; +# ISA-cmt: dctfix - DFP Convert To Fixed +# binutils: mytest.d: ac: ec 40 1a 44 dctfix f2,f3 +:dctfix fT,fB is $(NOTVLE) & OP=59 & XOP_1_10=290 & Rc=0 & fT & fB & BITS_16_20=0 { dctfixOp(fT,fB); } + +# binutils-descr: "dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRB} +define pcodeop dctfixDotOp; +# ISA-cmt: dctfix. - DFP Convert To Fixed Rc +# binutils: mytest.d: b0: ec 40 1a 45 dctfix. f2,f3 +:dctfix. fT,fB is $(NOTVLE) & OP=59 & XOP_1_10=290 & Rc=1 & fT & fB & BITS_16_20=0 { dctfixDotOp(fT,fB); } + +# binutils-descr: "ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB} +define pcodeop ddedpdOp; +# ISA-cmt: ddedpd - DFP Decode DPD To BCD +# binutils: mytest.d: b4: ec 70 22 84 ddedpd 2,f3,f4 +:ddedpd fT,SP,fB is $(NOTVLE) & OP=59 & fT & SP & BITS_16_18=0 & fB & XOP_1_10=322 & Rc=0 { ddedpdOp(fT,fB); } # & BITS_16_18=0 + +# binutils-descr: "ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB} +define pcodeop ddedpdDotOp; +# ISA-cmt: ddedpd. - DFP Decode DPD To BCD Rc +# binutils: mytest.d: b8: ec 70 22 85 ddedpd. 2,f3,f4 +:ddedpd. fT,SP,fB is $(NOTVLE) & OP=59 & fT & SP & BITS_16_18=0 & fB & XOP_1_10=322 & Rc=1 { ddedpdDotOp(fT,fB); } # & BITS_16_18=0 + +# binutils-descr: "dxex", XRC(59,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRB} +define pcodeop dxexOp; +# ISA-cmt: dxex - DFP Extract Biased Exponent +# binutils: mytest.d: bc: ec 40 1a c4 dxex f2,f3 +:dxex fT,fB is $(NOTVLE) & OP=59 & XOP_1_10=354 & Rc=0 & fT & fB & BITS_16_20=0 { dxexOp(fT,fB); } + +# binutils-descr: "dxex.", XRC(59,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRB} +define pcodeop dxexDotOp; +# ISA-cmt: dxex. - DFP Extract Biased Exponent Rc +# binutils: mytest.d: c0: ec 40 1a c5 dxex. f2,f3 +:dxex. fT,fB is $(NOTVLE) & OP=59 & XOP_1_10=354 & Rc=1 & fT & fB & BITS_16_20=0 { dxexDotOp(fT,fB); } + +# binutils-descr: "dsub", XRC(59,514,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB} +define pcodeop dsubOp; +# ISA-cmt: dsub - DFP Subtract +# binutils: mytest.d: c4: ec 43 24 04 dsub f2,f3,f4 +:dsub fT,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=514 & Rc=0 & fT & fA & fB { dsubOp(fT,fA,fB); } + +# binutils-descr: "dsub.", XRC(59,514,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB} +define pcodeop dsubDotOp; +# ISA-cmt: dsub. - DFP Subtract Rc +# binutils: mytest.d: c8: ec 43 24 05 dsub. f2,f3,f4 +:dsub. fT,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=514 & Rc=1 & fT & fA & fB { dsubDotOp(fT,fA,fB); } + +# binutils-descr: "ddiv", XRC(59,546,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB} +define pcodeop ddivOp; +# ISA-cmt: ddiv - DFP Divide +# binutils: mytest.d: cc: ec 43 24 44 ddiv f2,f3,f4 +:ddiv fT,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=546 & Rc=0 & fT & fA & fB { ddivOp(fT,fA,fB); } + +# binutils-descr: "ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB} +define pcodeop ddivDotOp; +# ISA-cmt: ddiv. - DFP Divide Rc +# binutils: mytest.d: d0: ec 43 24 45 ddiv. f2,f3,f4 +:ddiv. fT,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=546 & Rc=1 & fT & fA & fB { ddivDotOp(fT,fA,fB); } + +# binutils-descr: "dcmpu", X(59,642), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB} +define pcodeop dcmpuOp; +# ISA-cmt: dcmpu - DFP Compare Unordered +# ISA-info: dcmpu - Form "X" Page 178 Category "DFP" +# binutils: mytest.d: d4: ed 03 25 04 dcmpu cr2,f3,f4 +:dcmpu CRFD,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=642 & CRFD & fA & fB & BITS_21_22=0 & BIT_0=0 { dcmpuOp(CRFD,fA,fB); } + +# binutils-descr: "dtstsf", X(59,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB} +define pcodeop dtstsfOp; +# ISA-cmt: dtstsf - DFP Test Significance +# ISA-info: dtstsf - Form "X" Page 182 Category "DFP" +# binutils: mytest.d: d8: ed 03 25 44 dtstsf cr2,f3,f4 +:dtstsf CRFD,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=674 & CRFD & fA & fB & BITS_21_22=0 & BIT_0=0 { dtstsfOp(CRFD,fA,fB); } + +# binutils-descr: "drsp", XRC(59,770,0), X_MASK, POWER6, PPCNONE, {FRT, FRB} +define pcodeop drspOp; +# ISA-cmt: drsp - DFP Round To DFP Short +# binutils: mytest.d: dc: ec 40 1e 04 drsp f2,f3 +:drsp fT,fB is $(NOTVLE) & OP=59 & XOP_1_10=770 & Rc=0 & fT & fB & BITS_16_20=0 { drspOp(fT,fB); } + +# binutils-descr: "drsp.", XRC(59,770,1), X_MASK, POWER6, PPCNONE, {FRT, FRB} +define pcodeop drspDotOp; +# ISA-cmt: drsp. - DFP Round To DFP Short Rc +# binutils: mytest.d: e0: ec 40 1e 05 drsp. f2,f3 +:drsp. fT,fB is $(NOTVLE) & OP=59 & XOP_1_10=770 & Rc=1 & fT & fB & BITS_16_20=0 { drspDotOp(fT,fB); } + +# binutils-descr: "dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCNONE, {FRT, FRB} +define pcodeop dcffixOp; +# ISA-cmt: dcffix - DFP Convert From Fixed +# binutils: power7.d: 144: ed 40 66 44 dcffix f10,f12 +:dcffix fT,fB is $(NOTVLE) & OP=59 & XOP_1_10=802 & Rc=0 & fT & fB & BITS_16_20=0 { dcffixOp(fT,fB); } + +# binutils-descr: "dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCNONE, {FRT, FRB} +define pcodeop dcffixDotOp; +# ISA-cmt: dcffix. - DFP Convert From Fixed Rc +# binutils: mytest.d: e4: ec 40 1e 45 dcffix. f2,f3 +:dcffix. fT,fB is $(NOTVLE) & OP=59 & XOP_1_10=802 & Rc=1 & fT & fB & BITS_16_20=0 { dcffixDotOp(fT,fB); } + +# binutils-descr: "denbcd", XRC(59,834,0), X_MASK, POWER6, PPCNONE, {S, FRT, FRB} +define pcodeop denbcdOp; +# ISA-cmt: denbcd - DFP Encode BCD To DPD +# binutils: mytest.d: e8: ec 70 26 84 denbcd 1,f3,f4 +:denbcd fT,fB is $(NOTVLE) & OP=59 & fT & BIT_20 & BITS_16_19=0 & fB & XOP_1_10=834 & Rc=0 { denbcdOp(fT,fB); } # & BITS_16_19=0 + +# binutils-descr: "denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCNONE, {S, FRT, FRB} +define pcodeop denbcdDotOp; +# ISA-cmt: denbcd. - DFP Encode BCD To DPD Rc +# binutils: mytest.d: ec: ec 70 26 85 denbcd. 1,f3,f4 +:denbcd. fT,fB is $(NOTVLE) & OP=59 & fT & BIT_20 & BITS_16_19=0 & fB & XOP_1_10=834 & Rc=1 { denbcdDotOp(fT,fB); } # & BITS_16_19=0 + +# binutils-descr: "diex", XRC(59,866,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB} +define pcodeop diexOp; +# ISA-cmt: diex - DFP Insert Biased Exponent +# binutils: mytest.d: f4: ec 43 26 c4 diex f2,f3,f4 +:diex fT,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=866 & Rc=0 & fT & fA & fB { diexOp(fT,fA,fB); } + +# binutils-descr: "diex.", XRC(59,866,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB} +define pcodeop diexDotOp; +# ISA-cmt: diex. - DFP Insert Biased Exponent Rc +# binutils: mytest.d: f8: ec 43 26 c5 diex. f2,f3,f4 +:diex. fT,fA,fB is $(NOTVLE) & OP=59 & XOP_1_10=866 & Rc=1 & fT & fA & fB { diexDotOp(fT,fA,fB); } + +# binutils-descr: "stfdp", OP(61), OP_MASK, POWER6, PPCNONE, {FRT, D, RA0} +define pcodeop stfdpOp; +# ISA-cmt: stfdp - Store Floating-Point Double Pair +# ISA-info: stfdp - Form "DS" Page 131 Category "FP.out" +# binutils: NO-EXAMPLE - stfdp +:stfdp fS,RA_OR_ZERO,DS is $(NOTVLE) & OP=61 & fS & RA_OR_ZERO & DS & BITS_0_1=0 { + EA:$(REGISTER_SIZE) = RA_OR_ZERO + sext(DS:2 << 2); + *[ram]:8 EA = stfdpOp(fS,RA_OR_ZERO,DS:2); +} + +# binutils-descr: "stq", DSO(62,2), DS_MASK, POWER4, PPC476, {RSQ, DS, RA0} +# ISA-cmt: stq - Store Quadword +# ISA-info: stq - Form "DS" Page 751 Category "LSQ" +# binutils: power4.d: +50: f8 c7 00 02 stq r6,0\(r7\) +# binutils: power4.d: +54: f8 c7 00 12 stq r6,16\(r7\) +# binutils: power4.d: +58: f8 c7 ff f2 stq r6,-16\(r7\) +# binutils: power4.d: +5c: f8 c7 80 02 stq r6,-32768\(r7\) +# binutils: power4.d: +60: f8 c7 7f f2 stq r6,32752\(r7\) +:stq RS,RA_OR_ZERO,DS is $(NOTVLE) & OP=62 & RS & Dp & RA_OR_ZERO & DS & BITS_0_1=2 & regp [regpset = Dp+1;] { + ea:$(REGISTER_SIZE) = RA_OR_ZERO + sext(DS:2 << 2); +@if ENDIAN == "big" + *:$(REGISTER_SIZE) ea = RS; + *:$(REGISTER_SIZE) (ea + $(REGISTER_SIZE)) = regp; +@else + *:$(REGISTER_SIZE) (ea + $(REGISTER_SIZE)) = RS; + *:$(REGISTER_SIZE) ea = regp; +@endif +} + +define pcodeop stvepxOp; +:stvepx S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=807 & BIT_0=0 { + EA:$(REGISTER_SIZE) = RA_OR_ZERO + B; + *[ram]:16 EA = stvepxOp(S, RA_OR_ZERO, B); +} + +define pcodeop stvepxlOp; +:stvepxl S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=775 & BIT_0=0 { + EA:$(REGISTER_SIZE) = RA_OR_ZERO + B; + *[ram]:16 EA = stvepxlOp(S, RA_OR_ZERO, B); +} + +# binutils-descr: "dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC} +define pcodeop dquaqOp; +# ISA-cmt: dquaq - DFP Quantize Quad +# binutils: mytest.d: 100: fc 43 24 06 dquaq f2,f3,f4,2 +:dquaq fT,fA,fB,RMC is $(NOTVLE) & OP=63 & fT & fA & fB & RMC & XOP_1_8=3 & Rc=0 { dquaqOp(); } + +# binutils-descr: "dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC} +define pcodeop dquaqDotOp; +# ISA-cmt: dquaq. - DFP Quantize Quad Rc +# binutils: mytest.d: 104: fc 43 24 07 dquaq. f2,f3,f4,2 +:dquaq. fT,fA,fB,RMC is $(NOTVLE) & OP=63 & fT & fA & fB & RMC & XOP_1_8=3 & Rc=1 { dquaqDotOp(); } + +# binutils-descr: "dmulq", XRC(63,34,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB} +define pcodeop dmulqOp; +# ISA-cmt: dmulq - DFP Multiply Quad +# binutils: mytest.d: 108: fc 43 20 44 dmulq f2,f3,f4 +:dmulq fT,fA,fB is $(NOTVLE) & OP=63 & XOP_1_10=34 & Rc=0 & fT & fA & fB { dmulqOp(fT,fA,fB); } + +# binutils-descr: "dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB} +define pcodeop dmulqDotOp; +# ISA-cmt: dmulq. - DFP Multiply Quad Rc +# binutils: mytest.d: 10c: fc 43 20 45 dmulq. f2,f3,f4 +:dmulq. fT,fA,fB is $(NOTVLE) & OP=63 & XOP_1_10=34 & Rc=1 & fT & fA & fB { dmulqDotOp(fT,fA,fB); } + +# binutils-descr: "drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC} +define pcodeop drrndqOp; +# ISA-cmt: drrndq - DFP Reround Quad +# binutils: mytest.d: 110: fc 43 22 46 drrndq f2,f3,f4,1 +:drrndq fT,fA,fB,RMC is $(NOTVLE) & OP=63 & fT & fA & fB & RMC & XOP_1_8=35 & Rc=0 { drrndqOp(fT,fA,fB); } + +# binutils-descr: "drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC} +define pcodeop drrndqDotOp; +# ISA-cmt: drrndq - DFP Reround Quad +# binutils: mytest.d: 110: fc 43 22 46 drrndq f2,f3,f4,1 +:drrndq. fT,fA,fB,RMC is $(NOTVLE) & OP=63 & fT & fA & fB & RMC & XOP_1_8=35 & Rc=1 { drrndqDotOp(fT,fA,fB); } + + +# binutils-descr: "dscliq", ZRC(63,66,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16} +define pcodeop dscliqOp; +# ISA-cmt: dscliq - DFP Shift Significand Left Immediate Quad +# binutils: mytest.d: 118: fc 43 10 84 dscliq f2,f3,4 +:dscliq fT,fA,SH16 is $(NOTVLE) & OP=63 & fT & fA & SH16 & XOP_1_9=66 & Rc=0 { dscliqOp(fT,fA); } + +# binutils-descr: "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16} +define pcodeop dscliqDotOp; +# ISA-cmt: dscliq. - DFP Shift Significand Left Immediate Quad Rc +# binutils: mytest.d: 11c: fc 43 10 85 dscliq. f2,f3,4 +:dscliq. fT,fA,SH16 is $(NOTVLE) & OP=63 & fT & fA & SH16 & XOP_1_9=66 & Rc=1 { dscliqDotOp(fT,fA); } + +# binutils-descr: "dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, PPCNONE, {TE, FRT, FRB, RMC} +define pcodeop dquaiqOp; +# ISA-cmt: dquaiq - DFP Quantize Immediate Quad +# binutils: mytest.d: 120: fc 62 24 86 dquaiq 2,f3,f4,2 +:dquaiq fT,A_BITS,fB,RMC is $(NOTVLE) & OP=63 & fT & A_BITS & fB & RMC & XOP_1_8=67 & Rc=0 { dquaiqOp(fT,fB); } + +# binutils-descr: "dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, PPCNONE, {TE, FRT, FRB, RMC} +define pcodeop dquaiqDotOp; +# ISA-cmt: dquaiq. - DFP Quantize Immediate Quad Rc +# binutils: mytest.d: 124: fc 62 24 87 dquaiq. 2,f3,f4,2 +:dquaiq. fT,A_BITS,fB,RMC is $(NOTVLE) & OP=63 & fT & A_BITS & fB & RMC & XOP_1_8=67 & Rc=1 { dquaiqDotOp(fT,fB); } + +# binutils-descr: "dscriq", ZRC(63,98,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16} +define pcodeop dscriqOp; +# ISA-cmt: dscriq - DFP Shift Significand Right Immediate Quad +# binutils: mytest.d: 128: fc 43 10 c4 dscriq f2,f3,4 +:dscriq fT,fA,SH16 is $(NOTVLE) & OP=63 & fT & fA & SH16 & XOP_1_9=98 & Rc=0 { dscriqOp(); } + +# binutils-descr: "dscriq.", ZRC(63,98,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16} +define pcodeop dscriqDotOp; +# ISA-cmt: dscriq. - DFP Shift Significand Right Immediate Quad Rc +# binutils: mytest.d: 12c: fc 43 10 c5 dscriq. f2,f3,4 +:dscriq. fT,fA,SH16 is $(NOTVLE) & OP=63 & fT & fA & SH16 & XOP_1_9=98 & Rc=1 { dscriqDotOp(); } + +# binutils-descr: "drintxq", ZRC(63,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC} +define pcodeop drintxqOp; +# ISA-cmt: drintxq - DFP Round To FP Integer With Inexact Quad +# binutils: mytest.d: 130: fc 61 22 c6 drintxq 1,f3,f4,1 +:drintxq fT,fB,RMC is $(NOTVLE) & OP=63 & fT & BITS_17_20=0 & BIT_16 & fB & RMC & XOP_1_8=99 & Rc=0 { drintxqOp(); } + +# binutils-descr: "drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC} +define pcodeop drintxqDotOp; +# ISA-cmt: drintxq. - DFP Round To FP Integer With Inexact Quad Rc +# binutils: mytest.d: 134: fc 61 22 c7 drintxq. 1,f3,f4,1 +:drintxq. fT,fB,RMC is $(NOTVLE) & OP=63 & fT & BITS_17_20=0 & BIT_16 & fB & RMC & XOP_1_8=99 & Rc=1 { drintxqDotOp(); } + +# binutils-descr: "dcmpoq", X(63,130), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB} +define pcodeop dcmpoqOp; +# ISA-cmt: dcmpoq - DFP Compare Ordered Quad +# ISA-info: dcmpoq - Form "X" Page 179 Category "DFP" +# binutils: mytest.d: 138: fd 03 21 04 dcmpoq cr2,f3,f4 +:dcmpoq CRFD,fA,fB is $(NOTVLE) & OP=63 & XOP_1_10=130 & CRFD & fA & fB & BITS_21_22=0 & BIT_0=0 { dcmpoqOp(CRFD,fA,fB); } + +# binutils-descr: "dtstexq", X(63,162), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB} +define pcodeop dtstexqOp; +# ISA-cmt: dtstexq - DFP Test Exponent Quad +# ISA-info: dtstexq - Form "X" Page 181 Category "DFP" +# binutils: mytest.d: 144: fd 03 21 44 dtstexq cr2,f3,f4 +:dtstexq CRFD,fA,fB is $(NOTVLE) & OP=63 & XOP_1_10=162 & CRFD & fA & fB & BITS_21_22=0 & BIT_0=0 { dtstexqOp(CRFD,fA,fB); } + +# binutils-descr: "dtstdcq", Z(63,194), Z_MASK, POWER6, PPCNONE, {BF, FRA, DCM} +define pcodeop dtstdcqOp; +# ISA-cmt: dtstdcq - DFP Test Data Class Quad +# ISA-info: dtstdcq - Form "Z22" Page 180 Category "DFP" +# binutils: mytest.d: 26c: fc 82 0d 84 dtstdcq cr1,f2,3 +:dtstdcq BF2,fA,DCM is $(NOTVLE) & OP=63 & BF2 & BITS_21_22=0 & fA & DCM & XOP_1_9=194 & BIT_0=0 { dtstdcqOp(fA); } + + +# binutils-descr: "dtstdgq", Z(63,226), Z_MASK, POWER6, PPCNONE, {BF, FRA, DGM} +define pcodeop dtstdgqOp; +# ISA-cmt: dtstdgq - DFP Test Data Group Quad +# ISA-info: dtstdgq - Form "Z22" Page 180 Category "DFP" +# binutils: mytest.d: 148: fd 03 11 c4 dtstdgq cr2,f3,4 +:dtstdgq BF2,fA,DGM is $(NOTVLE) & OP=63 & BF2 & BITS_21_22=0 & fA & DGM & XOP_1_9=226 & BIT_0=0 { dtstdgqOp(); } + +# binutils-descr: "drintnq", ZRC(63,227,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC} +define pcodeop drintnqOp; +# ISA-cmt: drintnq - DFP Round To FP Integer Without Inexact Quad +# binutils: mytest.d: 14c: fc 61 23 c6 drintnq 1,f3,f4,1 +:drintnq fT,fB,RMC is $(NOTVLE) & OP=63 & fT & BITS_17_20=0 & MSR_L & fB & RMC & XOP_1_8=227 & Rc=0 { drintnqOp(); } + +# binutils-descr: "drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC} +define pcodeop drintnqDotOp; +# ISA-cmt: drintnq. - DFP Round To FP Integer Without Inexact Quad Rc +# binutils: mytest.d: 150: fc 61 23 c7 drintnq. 1,f3,f4,1 +:drintnq. fT,fB,RMC is $(NOTVLE) & OP=63 & fT & BITS_17_20=0 & MSR_L & fB & RMC & XOP_1_8=227 & Rc=1 { drintnqDotOp(); } + +# binutils-descr: "dctqpq", XRC(63,258,0), X_MASK, POWER6, PPCNONE, {FRT, FRB} +define pcodeop dctqpqOp; +# ISA-cmt: dctqpq - DFP Convert To DFP Extended +# binutils: mytest.d: 154: fc 40 1a 04 dctqpq f2,f3 +:dctqpq fT,fB is $(NOTVLE) & OP=63 & XOP_1_10=258 & Rc=0 & fT & fB & BITS_16_20=0 { dctqpqOp(fT,fB); } + +# binutils-descr: "dctqpq.", XRC(63,258,1), X_MASK, POWER6, PPCNONE, {FRT, FRB} +define pcodeop dctqpqDotOp; +# ISA-cmt: dctqpq. - DFP Convert To DFP Extended Rc +# binutils: mytest.d: 158: fc 40 1a 05 dctqpq. f2,f3 +:dctqpq. fT,fB is $(NOTVLE) & OP=63 & XOP_1_10=258 & Rc=1 & fT & fB & BITS_16_20=0 { dctqpqDotOp(fT,fB); } + +# binutils-descr: "dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRB} +define pcodeop dctfixqOp; +# ISA-cmt: dctfixq - DFP Convert To Fixed Quad +# binutils: mytest.d: 15c: fc 40 1a 44 dctfixq f2,f3 +:dctfixq fT,fB is $(NOTVLE) & OP=63 & XOP_1_10=290 & Rc=0 & fT & fB & BITS_16_20=0 { dctfixqOp(fT,fB); } + +# binutils-descr: "dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRB} +define pcodeop dctfixqDotOp; +# ISA-cmt: dctfixq. - DFP Convert To Fixed Quad Rc +# binutils: mytest.d: 160: fc 40 1a 45 dctfixq. f2,f3 +:dctfixq. fT,fB is $(NOTVLE) & OP=63 & XOP_1_10=290 & Rc=1 & fT & fB & BITS_16_20=0 { dctfixqDotOp(fT,fB); } + +# binutils-descr: "ddedpdq", XRC(63,322,0), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB} +define pcodeop ddedpdqOp; +# ISA-cmt: ddedpdq - DFP Decode DPD To BCD Quad +# binutils: mytest.d: 164: fc 70 22 84 ddedpdq 2,f3,f4 +:ddedpdq fT,SP,fB is $(NOTVLE) & OP=63 & XOP_1_10=322 & Rc=0 & fT & fB & SP & BITS_16_18=0 { ddedpdqOp(fT,fB); } + +# binutils-descr: "ddedpdq.", XRC(63,322,1), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB} +define pcodeop ddedpdqDotOp; +# ISA-cmt: ddedpdq. - DFP Decode DPD To BCD Quad Rc +# binutils: mytest.d: 168: fc 70 22 85 ddedpdq. 2,f3,f4 +:ddedpdq. fT,SP,fB is $(NOTVLE) & OP=63 & XOP_1_10=322 & Rc=1 & fT & fB & SP & BITS_16_18=0 { ddedpdqDotOp(fT,fB); } + +# binutils-descr: "dxexq", XRC(63,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRB} +define pcodeop dxexqOp; +# ISA-cmt: dxexq - DFP Extract Biased Exponent Quad +# binutils: mytest.d: 16c: fc 40 1a c4 dxexq f2,f3 +:dxexq fT,fB is $(NOTVLE) & OP=63 & XOP_1_10=354 & Rc=0 & fT & fB & BITS_16_20=0 { dxexqOp(fT,fB); } + +# binutils-descr: "dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRB} +define pcodeop dxexqDotOp; +# ISA-cmt: dxexq. - DFP Extract Biased Exponent Quad Rc +# binutils: mytest.d: 170: fc 40 1a c5 dxexq. f2,f3 +:dxexq. fT,fB is $(NOTVLE) & OP=63 & XOP_1_10=354 & Rc=1 & fT & fB & BITS_16_20=0 { dxexqDotOp(fT,fB); } + +# binutils-descr: "dsubq", XRC(63,514,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB} +define pcodeop dsubqOp; +# ISA-cmt: dsubq - DFP Subtract Quad +# binutils: mytest.d: 174: fc 43 24 04 dsubq f2,f3,f4 +:dsubq fT,fA,fB is $(NOTVLE) & OP=63 & XOP_1_10=514 & Rc=0 & fT & fA & fB { dsubqOp(fT,fA,fB); } + +# binutils-descr: "dsubq.", XRC(63,514,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB} +define pcodeop dsubqDotOp; +# ISA-cmt: dsubq. - DFP Subtract Quad Rc +# binutils: mytest.d: 178: fc 43 24 05 dsubq. f2,f3,f4 +:dsubq. fT,fA,fB is $(NOTVLE) & OP=63 & XOP_1_10=514 & Rc=1 & fT & fA & fB { dsubqDotOp(fT,fA,fB); } + +# binutils-descr: "ddivq", XRC(63,546,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB} +define pcodeop ddivqOp; +# ISA-cmt: ddivq - DFP Divide Quad +# binutils: mytest.d: 17c: fc 43 24 44 ddivq f2,f3,f4 +:ddivq fT,fA,fB is $(NOTVLE) & OP=63 & XOP_1_10=546 & Rc=0 & fT & fA & fB { ddivqOp(fT,fA,fB); } + +# binutils-descr: "ddivq.", XRC(63,546,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB} +define pcodeop ddivqDotOp; +# ISA-cmt: ddivq. - DFP Divide Quad Rc +# binutils: mytest.d: 180: fc 43 24 45 ddivq. f2,f3,f4 +:ddivq. fT,fA,fB is $(NOTVLE) & OP=63 & XOP_1_10=546 & Rc=1 & fT & fA & fB { ddivqDotOp(fT,fA,fB); } + +# binutils-descr: "dcmpuq", X(63,642), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB} +define pcodeop dcmpuqOp; +# ISA-cmt: dcmpuq - DFP Compare Unordered Quad +# ISA-info: dcmpuq - Form "X" Page 179 Category "DFP" +# binutils: mytest.d: 184: fd 03 25 04 dcmpuq cr2,f3,f4 +:dcmpuq CRFD,fA,fB is $(NOTVLE) & OP=63 & XOP_1_10=642 & CRFD & fA & fB & BITS_21_22=0 & BIT_0=0 { dcmpuqOp(CRFD,fA,fB); } + +# binutils-descr: "dtstsfq", X(63,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB} +define pcodeop dtstsfqOp; +# ISA-cmt: dtstsfq - DFP Test Significance Quad +# ISA-info: dtstsfq - Form "X" Page 182 Category "DFP" +# binutils: mytest.d: 188: fd 03 25 44 dtstsfq cr2,f3,f4 +:dtstsfq CRFD,fA,fB is $(NOTVLE) & OP=63 & XOP_1_10=674 & CRFD & fA & fB & BITS_21_22=0 & BIT_0=0 { dtstsfqOp(CRFD,fA,fB); } + +# binutils-descr: "drdpq", XRC(63,770,0), X_MASK, POWER6, PPCNONE, {FRT, FRB} +define pcodeop drdpqOp; +# ISA-cmt: drdpq - DFP Round To DFP Long +# binutils: mytest.d: 18c: fc 40 1e 04 drdpq f2,f3 +:drdpq fT,fB is $(NOTVLE) & OP=63 & XOP_1_10=770 & Rc=0 & fT & fB & BITS_16_20=0 { drdpqOp(fT,fB); } + +# binutils-descr: "drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCNONE, {FRT, FRB} +define pcodeop drdpqDotOp; +# ISA-cmt: drdpq. - DFP Round To DFP Long Rc +# binutils: mytest.d: 190: fc 40 1e 05 drdpq. f2,f3 +:drdpq. fT,fB is $(NOTVLE) & OP=63 & XOP_1_10=770 & Rc=1 & fT & fB & BITS_16_20=0 { drdpqDotOp(fT,fB); } + +# binutils-descr: "dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCNONE, {FRT, FRB} +define pcodeop dcffixqOp; +# ISA-cmt: dcffixq - DFP Convert From Fixed Quad +# binutils: mytest.d: 194: fc 40 1e 44 dcffixq f2,f3 +:dcffixq fT,fB is $(NOTVLE) & OP=63 & XOP_1_10=802 & Rc=0 & fT & fB & BITS_16_20=0 { dcffixqOp(fT,fB); } + +# binutils-descr: "dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCNONE, {FRT, FRB} +define pcodeop dcffixqDotOp; +# ISA-cmt: dcffixq. - DFP Convert From Fixed Quad Rc +# binutils: mytest.d: 198: fc 40 1e 45 dcffixq. f2,f3 +:dcffixq. fT,fB is $(NOTVLE) & OP=63 & XOP_1_10=802 & Rc=1 & fT & fB & BITS_16_20=0 { dcffixqDotOp(fT,fB); } + +# binutils-descr: "denbcdq", XRC(63,834,0), X_MASK, POWER6, PPCNONE, {S, FRT, FRB} +define pcodeop denbcdqOp; +# ISA-cmt: denbcdq - DFP Encode BCD To DPD Quad +# binutils: mytest.d: 19c: fc 70 26 84 denbcdq 1,f3,f4 +:denbcdq fT,fB is $(NOTVLE) & OP=63 & XOP_1_10=834 & Rc=0 & BIT_20 & fT & fB & SR=0 { denbcdqOp(fT,fB); } + +# binutils-descr: "denbcdq.", XRC(63,834,1), X_MASK, POWER6, PPCNONE, {S, FRT, FRB} +define pcodeop denbcdqDotOp; +# ISA-cmt: denbcdq. - DFP Encode BCD To DPD Quad Rc +# binutils: mytest.d: 1a0: fc 70 26 85 denbcdq. 1,f3,f4 +:denbcdq. fT,fB is $(NOTVLE) & OP=63 & XOP_1_10=834 & Rc=1 & BIT_20 & fT & fB & SR=0 { denbcdqDotOp(fT,fB); } + +# binutils-descr: "diexq", XRC(63,866,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB} +define pcodeop diexqOp; +# ISA-cmt: diexq - DFP Insert Biased Exponent Quad +# binutils: mytest.d: 1a4: fc 43 26 c4 diexq f2,f3,f4 +:diexq fT,fA,fB is $(NOTVLE) & OP=63 & XOP_1_10=866 & Rc=0 & fT & fA & fB { diexqOp(fT,fA,fB); } + +# binutils-descr: "diexq.", XRC(63,866,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB} +define pcodeop diexqDotOp; +# ISA-cmt: diexq. - DFP Insert Biased Exponent Quad Rc +# binutils: mytest.d: 1a8: fc 43 26 c5 diexq. f2,f3,f4 +:diexq. fT,fA,fB is $(NOTVLE) & OP=63 & XOP_1_10=866 & Rc=1 & fT & fA & fB { diexqDotOp(fT,fA,fB); } + +# icbtls ct,ra,rb +# 31 / CT RA RB 486 / +# 0 6 7 11 16 21 31 +# 31 25 24 20 15 10 0 +#define pcodeop icbtlsOp; +#:icbtls CT2,A,B is $(NOTVLE) & OP=31 & BIT_25=0 & CT2 & A & B & XOP_1_10=486 & BIT_0=0 { icbtlsOp(A,B); } +define pcodeop InstructionCacheBlockLockSetX; +:icbtls CT,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & BIT_25=0 & CT & RA_OR_ZERO & B & XOP_1_10=486 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + InstructionCacheBlockLockSetX(ea); +} + +###################################### +# v2.07 non vsx additions. + +#=========================================================== +# Branch Conditional TAR(op=19, xop=560) +#=========================================================== + + +:bctar is $(NOTVLE) & OP=19 & BO_0=1 & BO_2=1 & LK=0 & BITS_13_15=0 & BH=0 & XOP_1_10=560 +{ + goto [TAR]; +} + +:bctar is linkreg=1 & OP=19 & BO_0=1 & BO_2=1 & LK=0 & BITS_13_15=0 & BH=0 & XOP_1_10=560 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + # don't do this anymore, detect another way + # call [CTR]; + # return [LR]; + goto [TAR]; +} + +:bctar BH is $(NOTVLE) & OP=19 & BO_0=1 & BO_2=1 & LK=0 & BITS_13_15=0 & BH & XOP_1_10=560 +{ + goto [TAR]; +} + +:bctarl is $(NOTVLE) & OP=19 & BO_0=1 & BO_2=1 & LK=1 & BITS_13_15=0 & BH=0 & XOP_1_10=560 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + LR = inst_next; + call [TAR]; +} +:bctarl BH is $(NOTVLE) & OP=19 & BO_0=1 & BO_2=1 & LK=1 & BITS_13_15=0 & BH & XOP_1_10=560 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + LR = inst_next; + call [TAR]; +} + +:b^CC^"ctar" is $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR= 0 & BH=0 & LK=0 & BITS_13_15=0 & XOP_1_10=560 +{ + if (!CC) goto inst_next; + goto [TAR]; +} +:b^CC^"ctar" BH is $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR= 0 & BH & BH_BITS!=0 & LK=0 & BITS_13_15=0 & XOP_1_10=560 +{ + if (!CC) goto inst_next; + goto [TAR]; +} + +:b^CC^"ctarl" is $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR= 0 & BH=0 & LK=1 & BITS_13_15=0 & XOP_1_10=560 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!CC) goto inst_next; + LR = inst_next; + call [TAR]; +} +:b^CC^"ctarl" BH is $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR= 0 & BH & BH_BITS!=0 & LK=1 & BITS_13_15=0 & XOP_1_10=560 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!CC) goto inst_next; + LR = inst_next; + call [TAR]; +} + +:b^CC^"ctar" BI_CR is $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH=0 & LK=0 & BITS_13_15=0 & XOP_1_10=560 +{ + if (!CC) goto inst_next; + goto [TAR]; +} + +:b^CC^"ctar" BI_CR,BH is $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH & LK=0 & BITS_13_15=0 & XOP_1_10=560 +{ + if (!CC) goto inst_next; + goto [TAR]; +} + +:b^CC^"ctarl" BI_CR is $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH=0 & LK=1 & BITS_13_15=0 & XOP_1_10=560 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!CC) goto inst_next; + LR = inst_next; + call [TAR]; +} + +:b^CC^"ctarl" BI_CR,BH is $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH & LK=1 & BITS_13_15=0 & XOP_1_10=560 + [ linkreg=0; globalset(inst_start,linkreg); ] +{ + if (!CC) goto inst_next; + LR = inst_next; + call [TAR]; +} + +:clrbhrb is $(NOTVLE) & OP=31 & XOP_1_10=430 & BITS_11_25=0 & BIT_0=0 { + clearHistory(); +} + +:fmrgew fT,fA,fB is $(NOTVLE) & OP=63 & fT & fA & fB & XOP_1_10=966 & Rc=0 { + fT[0,32] = fA:4; + fT[32,32] = fB:4; +} + +:fmrgow fT,fA,fB is $(NOTVLE) & OP=63 & fT & fA & fB & XOP_1_10=838 & Rc=0 { + fT[0,32] = fA(4); + fT[32,32] = fB(4); +} + +:lqarx D,RA_OR_ZERO,B,EX is OP=31 & D & RA_OR_ZERO & B & XOP_1_10=276 & EX & Dp & regp [regpset = Dp+1;] { + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; +@if ENDIAN == "big" + D = *:$(REGISTER_SIZE) ea; + regp = *:$(REGISTER_SIZE) (ea + $(REGISTER_SIZE)); +@else + D = *:$(REGISTER_SIZE) (ea + $(REGISTER_SIZE)); + regp = *:$(REGISTER_SIZE) ea; +@endif +} + +:mfbhrbe D,BH_RBE is $(NOTVLE) & OP=31 & XOP_1_10=302 & BIT_0=0 & D & BH_RBE { + D = movebuffer(BH_RBE:2); +} + +:msgclrp B is OP=31 & XOP_1_10=174 & BITS_16_25=0 & BIT_0=0 & B { + message(B); +} + +:msgsndp B is OP=31 & XOP_1_10=142 & BITS_16_25=0 & BIT_0=0 & B { + message(B); +} + +:rfebb SBE is $(NOTVLE) & OP=19 & XOP_1_10=146 & BITS_12_25=0 & BIT_0=0 & SBE { + eventInterrupt(SBE:1); +} + +:stqcx. S,RA_OR_ZERO,B is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=182 & BIT_0=1 & Dp & regp [regpset = Dp+1;] { + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; +@if ENDIAN == "big" + *:$(REGISTER_SIZE) ea = S; + *:$(REGISTER_SIZE) (ea + $(REGISTER_SIZE)) = regp; +@else + *:$(REGISTER_SIZE) (ea + $(REGISTER_SIZE)) = S; + *:$(REGISTER_SIZE) ea = regp; +@endif + setCrBit(cr0, 2, 1); +} + +:tabort. A is $(NOTVLE) & OP=31 & XOP_1_10=910 & BIT_0=1 & BITS_11_15=0 & BITS_21_25=0 & A { + transaction(A); +} + +:tabortdc. TOA,A,B is $(NOTVLE) & OP=31 & XOP_1_10=814 & BIT_0=1 & A & B & TOA { + transaction(TOA:1,A,B); +} + +:tabortdci. TOA,A,S5IMM is $(NOTVLE) & OP=31 & XOP_1_10=878 & BIT_0=1 & A & S5IMM & TOA { + transaction(TOA:1,A,S5IMM:1); +} + +:tabortwc. TOA,A,B is $(NOTVLE) & OP=31 & XOP_1_10=782 & BIT_0=1 & A & B & TOA { + transaction(TOA:1,A,B); +} + +:tabortwci. TOA,A,S5IMM is $(NOTVLE) & OP=31 & XOP_1_10=846 & BIT_0=1 & A & S5IMM & TOA { + transaction(TOA:1,A,S5IMM:1); +} + +:tbegin. BIT_R is $(NOTVLE) & OP=31 & XOP_1_10=654 & BIT_0=1 & BITS_11_20=0 & BITS_22_24=0 & BIT_R { + transaction(BIT_R:1); +} + +:tcheck BF2 is $(NOTVLE) & OP=31 & XOP_1_10=718 & BIT_0=0 & BITS_11_22=0 & BF2 { + transaction(BF2:1); +} + +:tend. BIT_A is $(NOTVLE) & OP=31 & XOP_1_10=686 & BIT_0=1 & BITS_11_24=0 & BIT_A { + transaction(BIT_A:1); +} + +:trechkpt. is $(NOTVLE) & OP=31 & XOP_1_10=1006 & BIT_0=1 & BITS_11_25=0 { + transaction(); +} + +:treclaim. A is $(NOTVLE) & OP=31 & XOP_1_10=942 & BIT_0=1 & BITS_11_15=0 & BITS_21_25=0 & A { + transaction(A); +} + +:tsr. BIT_L is $(NOTVLE) & OP=31 & XOP_1_10=750 & BIT_0=1 & BITS_11_20=0 & BITS_22_25=0 & BIT_L { + transaction(BIT_L:1); +} + +####################### +# v3.0 + +:addpcis D,OFF16SH is $(NOTVLE) & OP=19 & XOP_1_5=2 & D & OFF16SH { + D = inst_next + sext(OFF16SH); +} + +:cmpeqb CRFD,A,B is $(NOTVLE) & OP=31 & BITS_21_22=0 & BIT_0=0 & XOP_1_10=224 & A & B & CRFD { + tmpa:1 = A:1; + match:1 = (tmpa == B[0,8]) | (tmpa == B[8,8]) | (tmpa == B[16,8]) | (tmpa == B[24,8]); +@if REGISTER_SIZE == "8" + match = match | (tmpa == B[32,8]) | (tmpa == B[40,8]) | (tmpa == B[48,8]) | (tmpa == B[56,8]); +@endif + # 0b0 | match | 0b0 | 0b0 + CRFD = (match & 1) << 2; +} + +:cmprb CRFD,L2,A,B is $(NOTVLE) & OP=31 & BIT_22=0 & BIT_0=0 & XOP_1_10=192 & A & B & CRFD & L2 { + tmpin:1 = A:1; + tmp1lo:1 = B[16,8]; + tmp1hi:1 = B[24,8]; + tmp2lo:1 = B[0,8]; + tmp2hi:1 = B[8,8]; + in_range:1 = ((tmpin >= tmp2lo) & (tmpin <= tmp2hi)) | (((tmpin >= tmp1lo) & (tmpin <= tmp1hi)) * L2:1); + # 0b0 | in_range | 0b0 | 0b0 + CRFD = (in_range & 1) << 2; +} + +:cnttzw A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=538 & Rc=0 { + A = countTrailingZeros(S); +} + +:cnttzw. A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=538 & Rc=1 { + A = countTrailingZeros(S); + cr0flags(A); +} + +:cnttzd A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=570 & Rc=0 { + A = countTrailingZeros(S); +} + +:cnttzd. A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=570 & Rc=1 { + A = countTrailingZeros(S); + cr0flags(A); +} + +:copy RA_OR_ZERO,B,L2 is $(NOTVLE) & OP=31 & BITS_22_25=0 & BIT_0=0 & XOP_1_10=774 & RA_OR_ZERO & B & L2 { + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + copytrans(ea,L2:1); +} + +:cp_abort is $(NOTVLE) & OP=31 & BITS_11_25=0 & BIT_0=0 & XOP_1_10=838{ + copytrans(); +} + +:darn D,L16 is $(NOTVLE) & OP=31 & BITS_18_20=0 & BITS_11_15=0 & BIT_0=0 & XOP_1_10=755 & D & L16 { + D = random(L16:1); +} + +:dtstsfi CRFD,UIMT,fB is $(NOTVLE) & OP=59 & XOP_1_10=675 & CRFD & UIMT & fB & BIT_22=0 & BIT_0=0 { + dtstsfOp(CRFD,UIMT:1,fB); +} + +:dtstsfiq CRFD,UIMT,fB is $(NOTVLE) & OP=63 & XOP_1_10=675 & CRFD & UIMT & fB & BIT_22=0 & BIT_0=0 { + dtstsfOp(CRFD,UIMT:1,fB); +} + +:extswsli A,S,SH is OP=31 & A & S & SH & XOP_2_10=445 & Rc=0 { + tmp:8 = sext(S:4); + A = tmp << SH; +} + +:extswsli. A,S,SH is OP=31 & A & S & SH & XOP_2_10=445 & Rc=1 { + tmp:8 = sext(S:4); + A = tmp << SH; + cr0flags(A); +} + +:ldat D,RA_OR_ZERO,FNC is $(NOTVLE) & OP=31 & D & RA_OR_ZERO & FNC & XOP_1_10=614 & BIT_0=0 & Dp & regp [regpset = Dp+1;] { + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + tmp:$(REGISTER_SIZE) = *:8 ea; + mematom(ea,tmp,D,regp,FNC:1); + D = tmp; +} + +:ldmx D,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & D & RA_OR_ZERO & B & XOP_1_10=309 & BIT_0=0 { + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + D = *:8 ea; +} + +:lwat D,RA_OR_ZERO,FNC is $(NOTVLE) & OP=31 & D & RA_OR_ZERO & FNC & XOP_1_10=582 & BIT_0=0 & Dp & regp [regpset = Dp+1;] { + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + tmp:$(REGISTER_SIZE) = zext(*:4 ea); + mematom(ea,tmp,D,regp,FNC:1); + D = tmp; +} + +:maddhd D,A,B,C is $(NOTVLE) & OP=4 & D & A & B & C & XOP_0_5=48 { + tmpa:16 = sext(A); + tmpb:16 = sext(B); + tmpc:16 = sext(C); + tmpp:16 = (tmpa * tmpb) + tmpc; + D = tmpp(8); +} + +:maddhdu D,A,B,C is $(NOTVLE) & OP=4 & D & A & B & C & XOP_0_5=49 { + tmpa:16 = zext(A); + tmpb:16 = zext(B); + tmpc:16 = zext(C); + tmpp:16 = (tmpa * tmpb) + tmpc; + D = tmpp(8); +} + +:maddld D,A,B,C is $(NOTVLE) & OP=4 & D & A & B & C & XOP_0_5=51 { + tmpa:16 = sext(A); + tmpb:16 = sext(B); + tmpc:16 = sext(C); + tmpp:16 = (tmpa * tmpb) + tmpc; + D = tmpp:8; +} + +:mcrxrx CRFD is $(NOTVLE) & OP=31 & BITS_11_22=0 & BIT_0=0 & XOP_1_10=576 & CRFD { + CRFD = (xer_ov << 3) | (xer_ov32 << 2) | (xer_ca << 1) | (xer_ca32); +} + +:modsd D,A,B is $(NOTVLE) & OP=31 & D & A & B & XOP_1_10=777 & BIT_0=0 { + tmpa:16 = sext(A); + tmpb:16 = sext(B); + tmpd:16 = tmpa s% tmpb; + D = tmpd:$(REGISTER_SIZE); +} + +:modsw D,A,B is $(NOTVLE) & OP=31 & D & A & B & XOP_1_10=779 & BIT_0=0 { + tmpa:16 = sext(A:4); + tmpb:16 = sext(B:4); + tmpd:16 = tmpa s% tmpb; + D = tmpd:$(REGISTER_SIZE); +} + +:modud D,A,B is $(NOTVLE) & OP=31 & D & A & B & XOP_1_10=265 & BIT_0=0 { + tmpa:16 = zext(A); + tmpb:16 = zext(B); + tmpd:16 = tmpa % tmpb; + D = tmpd:$(REGISTER_SIZE); +} + +:moduw D,A,B is $(NOTVLE) & OP=31 & D & A & B & XOP_1_10=267 & BIT_0=0 { + tmpa:4 = zext(A:4); + tmpb:4 = zext(B:4); + tmpd:4 = tmpa % tmpb; + D = zext(tmpd); +} + +:msgsync is $(NOTVLE) & OP=31 & BITS_11_25=0 & BIT_0=0 & XOP_1_10=886 { + message(); +} + +:paste RA_OR_ZERO,B,0 is $(NOTVLE) & OP=31 & BITS_22_25=0 & XOP_1_10=902 & RA_OR_ZERO & B & L2=0 & Rc=0 { + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + pastetrans(ea); +} + +:paste. RA_OR_ZERO,B,1 is $(NOTVLE) & OP=31 & BITS_22_25=0 & XOP_1_10=902 & RA_OR_ZERO & B & L2=1 & Rc=1 { + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + pastetrans(ea); + setCrBit(cr0, 2, 1); +} + +:setb D,BFA is $(NOTVLE) & OP=31 & BITS_11_17=0 & BIT_0=0 & XOP_1_10=128 & D & BFA { + tmpcr:8 = 1 << (8 * BFA:1); + tmpr0:1 = (BFA & 0x8) != 0; + tmpr1:1 = (BFA & 0x4) != 0; + D = (-1 * zext(tmpr0)) + (1 * zext(tmpr0 == 0) * zext(tmpr1)); +} + +:slbieg S,B is $(NOTVLE) & OP=31 & BITS_16_20=0 & BIT_0=0 & XOP_1_10=466 & S & B { + slbInvalidateEntry(S,B); +} + +:slbsync is $(NOTVLE) & OP=31 & BITS_11_25=0 & BIT_0=0 & XOP_1_10=338 { + sync(); +} + +:stdat S,RA_OR_ZERO,FNC is $(NOTVLE) & OP=31 & S & RA_OR_ZERO & FNC & XOP_1_10=742 & BIT_0=0 & Dp & regp [regpset = Dp+1;] { + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + tmp:$(REGISTER_SIZE) = *:8 ea; + mematom(ea,tmp,S,regp,FNC:1); +} + +:stop is $(NOTVLE) & OP=19 & BITS_11_25=0 & BIT_0=0 & XOP_1_10=370 { + stopT(); +} + +:stwat S,RA_OR_ZERO,FNC is $(NOTVLE) & OP=31 & S & RA_OR_ZERO & FNC & XOP_1_10=710 & BIT_0=0 & Dp & regp [regpset = Dp+1;] { + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + tmp:$(REGISTER_SIZE) = zext(*:4 ea); + mematom(ea,tmp,S,regp,FNC:1); +} + +:wait WC is $(NOTVLE) & OP=31 & BITS_23_25=0 & BITS_11_20=0 & BIT_0=0 & XOP_1_10=30 & WC { + waitT(WC:1); +} diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc new file mode 100644 index 0000000..3b62834 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc @@ -0,0 +1,938 @@ + +CC16: "lt" is BI16_VLE=0 & BO16_VLE=1 & BI16_VLE { tmp:1 = 0; getCrBit(cr0, BI16_VLE, tmp); export tmp; } +CC16: "le" is BI16_VLE=1 & BO16_VLE=0 & BI16_VLE { tmp:1 = 0; getCrBit(cr0, BI16_VLE, tmp); tmp = !tmp; export tmp; } +CC16: "eq" is BI16_VLE=2 & BO16_VLE=1 & BI16_VLE { tmp:1 = 0; getCrBit(cr0, BI16_VLE, tmp); export tmp; } +CC16: "ge" is BI16_VLE=0 & BO16_VLE=0 & BI16_VLE { tmp:1 = 0; getCrBit(cr0, BI16_VLE, tmp); tmp = !tmp; export tmp; } +CC16: "gt" is BI16_VLE=1 & BO16_VLE=1 & BI16_VLE { tmp:1 = 0; getCrBit(cr0, BI16_VLE, tmp); export tmp; } +CC16: "ne" is BI16_VLE=2 & BO16_VLE=0 & BI16_VLE { tmp:1 = 0; getCrBit(cr0, BI16_VLE, tmp); tmp = !tmp; export tmp; } +CC16: "so" is BI16_VLE=3 & BO16_VLE=1 & BI16_VLE { tmp:1 = 0; getCrBit(cr0, BI16_VLE, tmp); export tmp; } +CC16: "ns" is BI16_VLE=3 & BO16_VLE=0 & BI16_VLE { tmp:1 = 0; getCrBit(cr0, BI16_VLE, tmp); tmp = !tmp; export tmp; } + + +CC32: "lt" is BI_CC_VLE=0 & BO_VLE=1 & BI_CR_VLE & BI_CC_VLE { tmp:1 = 0; getCrBit(BI_CR_VLE, BI_CC_VLE, tmp); export tmp; } +CC32: "le" is BI_CC_VLE=1 & BO_VLE=0 & BI_CR_VLE & BI_CC_VLE { tmp:1 = 0; getCrBit(BI_CR_VLE, BI_CC_VLE, tmp); tmp = !tmp; export tmp; } +CC32: "eq" is BI_CC_VLE=2 & BO_VLE=1 & BI_CR_VLE & BI_CC_VLE { tmp:1 = 0; getCrBit(BI_CR_VLE, BI_CC_VLE, tmp); export tmp; } +CC32: "ge" is BI_CC_VLE=0 & BO_VLE=0 & BI_CR_VLE & BI_CC_VLE { tmp:1 = 0; getCrBit(BI_CR_VLE, BI_CC_VLE, tmp); tmp = !tmp; export tmp; } +CC32: "gt" is BI_CC_VLE=1 & BO_VLE=1 & BI_CR_VLE & BI_CC_VLE { tmp:1 = 0; getCrBit(BI_CR_VLE, BI_CC_VLE, tmp); export tmp; } +CC32: "ne" is BI_CC_VLE=2 & BO_VLE=0 & BI_CR_VLE & BI_CC_VLE { tmp:1 = 0; getCrBit(BI_CR_VLE, BI_CC_VLE, tmp); tmp = !tmp; export tmp; } +CC32: "so" is BI_CC_VLE=3 & BO_VLE=1 & BI_CR_VLE & BI_CC_VLE { tmp:1 = 0; getCrBit(BI_CR_VLE, BI_CC_VLE, tmp); export tmp; } +CC32: "ns" is BI_CC_VLE=3 & BO_VLE=0 & BI_CR_VLE & BI_CC_VLE { tmp:1 = 0; getCrBit(BI_CR_VLE, BI_CC_VLE, tmp); tmp = !tmp; export tmp; } +CC32: "dnz" is BO_VLE=2 {CTR = CTR-1; tmp:1 = (CTR != 0); export tmp; } +CC32: "dz" is BO_VLE=3 {CTR = CTR-1; tmp:1 = (CTR == 0); export tmp; } + +addrBD8: reloc is BD8_VLE [ reloc = inst_start + (BD8_VLE << 1);] { export *[ram]:4 reloc; } +addrBD15: reloc is BD15_VLE [ reloc = inst_start + (BD15_VLE << 1);] { export *[ram]:4 reloc; } +addrBD24: reloc is BD24_VLE [ reloc = inst_start + (BD24_VLE << 1);] { export *[ram]:4 reloc; } + +d8PlusRaAddress: S8IMM(A) is S8IMM & A {tmp:$(REGISTER_SIZE) = A+S8IMM; export tmp; } +d8PlusRaOrZeroAddress: S8IMM(RA_OR_ZERO) is S8IMM & RA_OR_ZERO {tmp:$(REGISTER_SIZE) = RA_OR_ZERO+S8IMM; export tmp; } + +sd4PlusRxAddr: SD4_VLE(RX_VLE) is SD4_VLE & RX_VLE {tmp:$(REGISTER_SIZE) = RX_VLE+SD4_VLE; export tmp; } +sd4HPlusRxAddr: SD4_VLE(RX_VLE) is SD4_VLE & RX_VLE {tmp:$(REGISTER_SIZE) = RX_VLE+(SD4_VLE << 1); export tmp; } +sd4WPlusRxAddr: SD4_VLE(RX_VLE) is SD4_VLE & RX_VLE {tmp:$(REGISTER_SIZE) = RX_VLE+(SD4_VLE << 2); export tmp; } + +OIMM: val is UI5_VLE [ val = UI5_VLE+1; ] { export *[const]:$(REGISTER_SIZE) val; } + +@if REGISTER_SIZE == "4" +SCALE: val is BIT_10 & SCL_VLE & IMM8 [ val = (((0xFFFFFFFF << ((SCL_VLE*8) + 8)) | (0xFFFFFFFF >> (32 - (SCL_VLE*8)))) * BIT_10) | (IMM8 << (SCL_VLE*8)); ] { export *[const]:4 val;} +@else +# Due to the way this big >> would work in java (arithmetic), we have to modify the orig way this was done. +# (0xFFFFFFFFFFFFFFFF >> (64 - (SCL_VLE*8)) <--- Original +# (0x7FFFFFFFFFFFFFFF >> (63 - (SCL_VLE*8)) <--- New +# We 'pre-shift' by 1 and take 1 off the total we'd shift by. SCL_VLE*8 is at most 24 so we don't have to +# worry about a negative shift value. +SCALE: val is BIT_10 & SCL_VLE & IMM8 [ val = (((0xFFFFFFFFFFFFFFFF << ((SCL_VLE*8) + 8)) | (0x7FFFFFFFFFFFFFFF >> (63 - (SCL_VLE*8)))) * BIT_10) | (IMM8 << (SCL_VLE*8)); ] { export *[const]:8 val;} +@endif + +SIMM16: val is IMM_0_10_VLE & SIMM_21_25_VLE [ val = (SIMM_21_25_VLE << 11) | IMM_0_10_VLE ;] { export *[const]:2 val; } +SIMM20: val is IMM_0_10_VLE & IMM_16_20_VLE & SIMM_11_14_VLE [ val = (SIMM_11_14_VLE << 16 ) | (IMM_16_20_VLE << 11) | IMM_0_10_VLE ;] { export *[const]:4 val; } +IMM16: val is IMM_0_10_VLE & IMM_21_25_VLE [ val = (IMM_21_25_VLE << 11) | IMM_0_10_VLE ;] { export *[const]:2 val; } +IMM16B: val is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) | IMM_0_10_VLE ;] { export *[const]:2 val; } + +:e_b addrBD24 is $(ISVLE) & OP=30 & BIT_25=0 & LK=0 & addrBD24 { + goto addrBD24; +} + +:e_bl addrBD24 is $(ISVLE) & OP=30 & BIT_25=0 & LK=1 & addrBD24 { + LR = inst_next; + call addrBD24; +} + +:se_b addrBD8 is $(ISVLE) & OP6_VLE=58 & BIT9_VLE=0 & LK8_VLE=0 & addrBD8 { + goto addrBD8; +} + +:se_bl addrBD8 is $(ISVLE) & OP6_VLE=58 & BIT9_VLE=0 & LK8_VLE=1 & addrBD8 { + LR = inst_next; + call addrBD8; +} + +# NOTE: For the conditional branches, the "official" mnemonics have just bc and bcl. +# We use extended mnemonics so the display is understandable without having to cross- +# reference multiple tables. +:e_b^CC32 addrBD15 is $(ISVLE) & OP=30 & XOP_VLE=8 & LK=0 & addrBD15 & CC32 { + if (CC32 == 0) goto inst_next; + goto addrBD15; +} + +:e_b^CC32^"l" addrBD15 is $(ISVLE) & OP=30 & XOP_VLE=8 & LK=1 & addrBD15 & CC32 { + if (CC32 == 0) goto inst_next; + LR= inst_next; + call [addrBD15]; +} + +:se_b^CC16 addrBD8 is $(ISVLE) & OP5_VLE=28 & addrBD8 & CC16 { + if (CC16 == 0) goto inst_next; + goto addrBD8; +} +####### + +:se_bctr is $(ISVLE) & OP15_VLE=3 & LK0_VLE=0 { + tmp:$(REGISTER_SIZE) = CTR & ~1; + goto [tmp]; +} + +:se_bctrl is $(ISVLE) & OP15_VLE=3 & LK0_VLE=1 { + LR = inst_next; + tmp:$(REGISTER_SIZE) = CTR & ~1; + call [tmp]; +} + +:se_blr is $(ISVLE) & OP15_VLE=2 & LK0_VLE=0 { + tmp:$(REGISTER_SIZE) = LR & ~1; + return [tmp]; +} + +:se_blrl is $(ISVLE) & OP15_VLE=2 & LK0_VLE=1 { + tmp:$(REGISTER_SIZE) = LR & ~1; + LR = inst_next; + return [tmp]; +} + +:se_sc is $(ISVLE) & OP16_VLE=2 { + tmp:1 = 0; + syscall(tmp); +} + +:e_sc LEV_VLE is $(ISVLE) & OP=31 & XOP_1_10=36 & BIT_0=0 & BITS_16_20=0 & BITS_21_25=0 & LEV_VLE { + tmp:1 = LEV_VLE; + syscall(tmp); +} + +:e_sc is $(ISVLE) & OP=31 & XOP_1_10=36 & BIT_0=0 & BITS_16_20=0 & BITS_21_25=0 & LEV_VLE=0 { + tmp:1 = 0; + syscall(tmp); +} + +:se_illegal is $(ISVLE) & OP16_VLE=0 { + illegal(); +} + +:se_rfmci is $(ISVLE) & OP16_VLE=11 { + MSR = returnFromMachineCheckInterrupt(MSR, spr23b); #MCSRR1 + local ra = spr23a; #MCSRR0 + return[ra]; +} + +:se_rfci is $(ISVLE) & OP16_VLE=9 { + MSR = returnFromCriticalInterrupt(MSR, CSRR1); + local ra = CSRR0; + return[ra]; +} + +:se_rfi is $(ISVLE) & OP16_VLE=8 { + MSR = returnFromInterrupt(MSR, SRR1); + local ra = SRR0; + return[ra]; +} + +:se_rfdi is $(ISVLE) & OP16_VLE=10 { + MSR = returnFromDebugInterrupt(MSR, spr23f); #DSRR1 + local ra = spr23e; #DSRR0 + return[ra]; +} + +:se_rfgi is $(ISVLE) & OP16_VLE=12 { + MSR = returnFromGuestInterrupt(MSR, spr17b); #GSRR1 + local ra = spr17a; #GSRR0 + return[ra]; +} + +:e_crand CC_D_OP,CC_OP,CC_B_OP is $(ISVLE) & OP=31 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=257 & BIT_0=0 +{ + setCrBit(CR_D,CR_D_CC,CC_OP & CC_B_OP); +} + +:e_crandc CC_D_OP,CC_OP,CC_B_OP is $(ISVLE) & OP=31 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=129 & BIT_0=0 +{ + tmp1:1 = !CC_B_OP; + setCrBit(CR_D,CR_D_CC,CC_OP & tmp1); +} + +:e_creqv CC_D_OP,CC_OP,CC_B_OP is $(ISVLE) & OP=31 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=289 & BIT_0=0 +{ + setCrBit(CR_D,CR_D_CC,CC_B_OP == CC_OP); +} + +:e_crnand CC_D_OP,CC_OP,CC_B_OP is $(ISVLE) & OP=31 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=225 & BIT_0=0 +{ + setCrBit(CR_D,CR_D_CC,!(CC_B_OP & CC_OP)); +} + +:e_crnor CC_D_OP,CC_OP,CC_B_OP is $(ISVLE) & OP=31 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=33 & BIT_0=0 +{ + setCrBit(CR_D,CR_D_CC,!(CC_B_OP | CC_OP)); +} + +:e_cror CC_D_OP,CC_OP,CC_B_OP is $(ISVLE) & OP=31 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=449 & BIT_0=0 +{ + setCrBit(CR_D,CR_D_CC,(CC_B_OP | CC_OP)); +} + +:e_crorc CC_D_OP,CC_OP,CC_B_OP is $(ISVLE) & OP=31 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=417 & BIT_0=0 +{ + setCrBit(CR_D,CR_D_CC,(CC_B_OP | (!CC_OP))); +} + +:e_crxor CC_D_OP,CC_OP,CC_B_OP is $(ISVLE) & OP=31 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=193 & BIT_0=0 +{ + setCrBit(CR_D,CR_D_CC,(CC_B_OP ^ CC_OP)); +} + +:e_mcrf CRFD,CRFS is $(ISVLE) & OP=31 & CRFD & BITS_21_22=0 & CRFS & BITS_11_17=0 & XOP_1_10=16 & BIT_0=0 +{ + CRFD = CRFS; +} + +:e_lbz D,dPlusRaOrZeroAddress is $(ISVLE) & OP=12 & D & dPlusRaOrZeroAddress +{ + D = zext(*:1(dPlusRaOrZeroAddress)); +} + +:se_lbz RZ_VLE,sd4PlusRxAddr is $(ISVLE) & OP4_VLE=8 & RZ_VLE & sd4PlusRxAddr { + RZ_VLE = zext(*:1(sd4PlusRxAddr)); +} + +:e_lbzu D,d8PlusRaAddress is $(ISVLE) & OP=6 & D & A & XOP_8_VLE=0 & d8PlusRaAddress +{ + ea:$(REGISTER_SIZE) = d8PlusRaAddress; + D = zext(*:1(ea)); + A = ea; +} + +# e_ldmvcsrrw 6 (0b0001_10) 0b00101 RA 0b0001_0000 D8 +:e_ldmvcsrrw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x10 & BITS_21_25=5 +{ + tea = d8PlusRaOrZeroAddress; + loadReg(CSRR0); + loadReg(CSRR1); +} + +# e_ldmvdsrrw 6 (0b0001_10) 0b00110 RA 0b0001_0000 D8 +:e_ldmvdsrrw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x10 & BITS_21_25=6 +{ + tea = d8PlusRaOrZeroAddress; + loadReg(spr23e); #DSRR0 + loadReg(spr23f); #DSRR1 +} + +# e_ldmvgprw 6 (0b0001_10) 0b00000 RA 0b0001_0000 D8 +:e_ldmvgprw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x10 & BITS_21_25=0 +{ + tea = d8PlusRaOrZeroAddress; + loadReg(r0); + loadReg(r3); + loadReg(r4); + loadReg(r5); + loadReg(r6); + loadReg(r7); + loadReg(r8); + loadReg(r9); + loadReg(r10); + loadReg(r11); + loadReg(r12); +} + +# e_ldmvsprw 6 (0b0001_10) 0b00001 RA 0b0001_0000 D8 +:e_ldmvsprw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x10 & BITS_21_25=1 +{ + tea = d8PlusRaOrZeroAddress; + #TODO is there a better way to handle this, CR are 4 bit + # so crall can't be used. And not much code accesses + # CR in this way, also CRM_CR seems backwards? + # loadReg(CR); + local tmpCR:4 = *:4 tea; + cr0 = zext(tmpCR[0,4]); + cr1 = zext(tmpCR[4,4]); + cr2 = zext(tmpCR[8,4]); + cr3 = zext(tmpCR[12,4]); + cr4 = zext(tmpCR[16,4]); + cr5 = zext(tmpCR[20,4]); + cr6 = zext(tmpCR[24,4]); + cr7 = zext(tmpCR[28,4]); + tea = tea + 4; + loadReg(LR); + loadReg(CTR); + loadReg(XER); +} + +# e_ldmvsrrw 6 (0b0001_10) 0b00100 RA 0b0001_0000 D8 +:e_ldmvsrrw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x10 & BITS_21_25=4 +{ + tea = d8PlusRaOrZeroAddress; + loadReg(SRR0); + loadReg(SRR1); +} + +:e_lha D,dPlusRaOrZeroAddress is $(ISVLE) & OP=14 & D & dPlusRaOrZeroAddress +{ + D = sext(*:2(dPlusRaOrZeroAddress)); +} + +:e_lhz D,dPlusRaOrZeroAddress is $(ISVLE) & OP=22 & D & dPlusRaOrZeroAddress +{ + D = zext(*:2(dPlusRaOrZeroAddress)); +} + +:se_lhz RZ_VLE,sd4HPlusRxAddr is $(ISVLE) & OP4_VLE=10 & RZ_VLE & sd4HPlusRxAddr { + RZ_VLE = zext(*:2(sd4HPlusRxAddr)); +} + +:e_lhau D,d8PlusRaAddress is $(ISVLE) & OP=6 & D & A & XOP_8_VLE=3 & d8PlusRaAddress +{ + ea:$(REGISTER_SIZE) = d8PlusRaAddress; + D = sext(*:2(ea)); + A = ea; +} + +:e_lhzu D,d8PlusRaAddress is $(ISVLE) & OP=6 & D & A & XOP_8_VLE=1 & d8PlusRaAddress +{ + ea:$(REGISTER_SIZE) = d8PlusRaAddress; + D = zext(*:2(ea)); + A = ea; +} + +:e_lwz D,dPlusRaOrZeroAddress is $(ISVLE) & OP=20 & D & dPlusRaOrZeroAddress +{ + D = zext(*:4(dPlusRaOrZeroAddress)); +} + +:se_lwz RZ_VLE,sd4WPlusRxAddr is $(ISVLE) & OP4_VLE=12 & RZ_VLE & sd4WPlusRxAddr { + RZ_VLE = zext(*:4(sd4WPlusRxAddr)); +} + +:e_lwzu D,d8PlusRaAddress is $(ISVLE) & OP=6 & D & A & XOP_8_VLE=2 & d8PlusRaAddress +{ + ea:$(REGISTER_SIZE) = d8PlusRaAddress; + D = zext(*:4(ea)); + A = ea; +} + +:e_stb S,dPlusRaOrZeroAddress is $(ISVLE) & OP=13 & S & dPlusRaOrZeroAddress +{ + *:1(dPlusRaOrZeroAddress) = S:1; +} + +:se_stb RZ_VLE,sd4PlusRxAddr is $(ISVLE) & OP4_VLE=9 & RZ_VLE & sd4PlusRxAddr { + *:1(sd4PlusRxAddr) = RZ_VLE:1; +} + +:e_stbu S,d8PlusRaAddress is $(ISVLE) & OP=6 & XOP_8_VLE=4 & S & A & d8PlusRaAddress +{ + ea:$(REGISTER_SIZE) = d8PlusRaAddress; + *:1(ea) = S:1; + A = ea; +} + +:e_sth S,dPlusRaOrZeroAddress is $(ISVLE) & OP=23 & S & dPlusRaOrZeroAddress +{ + *:2(dPlusRaOrZeroAddress) = S:2; +} + +:se_sth RZ_VLE,sd4HPlusRxAddr is $(ISVLE) & OP4_VLE=11 & RZ_VLE & sd4HPlusRxAddr { + *:2(sd4HPlusRxAddr) = RZ_VLE:2; +} + +:sthu S,d8PlusRaAddress is $(ISVLE) & OP=6 & XOP_8_VLE=5 & S & A & d8PlusRaAddress +{ + ea:$(REGISTER_SIZE) = d8PlusRaAddress; + *:2(ea) = S:2; + A = ea; +} + +# e_stmvcsrrw 6 (0b0001_10) 0b00101 RA 0b0001_0001 D8 +:e_stmvcsrrw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x11 & BITS_21_25=5 +{ + tea = d8PlusRaOrZeroAddress; + storeReg(CSRR0); + storeReg(CSRR1); +} + +# e_stmvdsrrw 6 (0b0001_10) 0b00110 RA 0b0001_0001 D8 +:e_stmvdsrrw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x11 & BITS_21_25=6 +{ + tea = d8PlusRaOrZeroAddress; + storeReg(spr23e); #DSRR0 + storeReg(spr23f); #DSRR1 +} + +# e_stmvgprw 6 (0b0001_10) 0b00000 RA 0b0001_0001 D8 +:e_stmvgprw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x11 & BITS_21_25=0 +{ + tea = d8PlusRaOrZeroAddress; + storeReg(r0); + storeReg(r3); + storeReg(r4); + storeReg(r5); + storeReg(r6); + storeReg(r7); + storeReg(r8); + storeReg(r9); + storeReg(r10); + storeReg(r11); + storeReg(r12); +} + +# e_stmvsprw 6 (0b0001_10) 0b00001 RA 0b0001_0001 D8 +:e_stmvsprw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x11 & BITS_21_25=1 +{ + tea = d8PlusRaOrZeroAddress; + #TODO SEE TODO in e_ldmvsprw + # storeReg(CR); + local tmpCR:4 = 0; + tmpCR = tmpCR | zext((cr0 & 0xf) << 0); + tmpCR = tmpCR | zext((cr1 & 0xf) << 4); + tmpCR = tmpCR | zext((cr2 & 0xf) << 8); + tmpCR = tmpCR | zext((cr3 & 0xf) << 12); + tmpCR = tmpCR | zext((cr4 & 0xf) << 16); + tmpCR = tmpCR | zext((cr5 & 0xf) << 20); + tmpCR = tmpCR | zext((cr6 & 0xf) << 24); + tmpCR = tmpCR | zext((cr7 & 0xf) << 28); + *:4 tea = tmpCR; + tea = tea + 4; + storeReg(LR); + storeReg(CTR); + storeReg(XER); +} + +# e_stmvsrrw 6 (0b0001_10) 0b00100 RA 0b0001_0001 D8 +:e_stmvsrrw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x11 & BITS_21_25=4 +{ + tea = d8PlusRaOrZeroAddress; + storeReg(SRR0); + storeReg(SRR1); +} + +:e_stw S,dPlusRaOrZeroAddress is $(ISVLE) & OP=21 & S & dPlusRaOrZeroAddress +{ +@ifdef BIT_64 + *:4(dPlusRaOrZeroAddress) = S:4; +@else + *:4(dPlusRaOrZeroAddress) = S; +@endif +} + +:se_stw RZ_VLE,sd4WPlusRxAddr is $(ISVLE) & OP4_VLE=13 & RZ_VLE & sd4WPlusRxAddr { +@ifdef BIT_64 + *:4(sd4WPlusRxAddr) = RZ_VLE:4; +@else + *:4(sd4WPlusRxAddr) = RZ_VLE; +@endif +} + +:e_stwu S,d8PlusRaAddress is $(ISVLE) & OP=6 & XOP_8_VLE=6 & S & A & d8PlusRaAddress +{ + ea:$(REGISTER_SIZE) = d8PlusRaAddress; +@ifdef BIT_64 + *:4(ea) = S:4; +@else + *:4(ea) = S; +@endif + A = ea; +} + +:e_lmw D,d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & XOP_8_VLE=8 & D & BITS_21_25 & d8PlusRaOrZeroAddress & LDMR31 [ lsmul = BITS_21_25; ] +{ + tea = d8PlusRaOrZeroAddress; + build LDMR31; +} + +:e_stmw S,d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & XOP_8_VLE=9 & S & BITS_21_25 & d8PlusRaOrZeroAddress & STMR31 [ lsmul = BITS_21_25; ] +{ + tea = d8PlusRaOrZeroAddress; + build STMR31; +} + +:se_add RX_VLE,RY_VLE is $(ISVLE) & OP6_VLE=1 & BITS_8_9=0 & RX_VLE & RY_VLE { + RX_VLE = RX_VLE + RY_VLE; +} + +:e_add16i D,A,SIMM is $(ISVLE) & OP=7 & A & D & SIMM { + tmp:2 = SIMM; + D = A + sext(tmp); +} + +:e_add2i. A,SIMM16 is $(ISVLE) & OP=28 & XOP_11_VLE=17 & A & SIMM16 { + A = A + sext(SIMM16); + cr0flags(A); +} + +:e_add2is A,SIMM16 is $(ISVLE) & OP=28 & XOP_11_VLE=18 & A & SIMM16 { + tmp:$(REGISTER_SIZE) = sext(SIMM16); + tmp = tmp << 16; + A = A + tmp; +} + +:e_addi D,A,SCALE is $(ISVLE) & OP=6 & XOP_12_VLE=8 & BIT_11=0 & D & A & SCALE { + D = A + SCALE; +} + +:e_addi. D,A,SCALE is $(ISVLE) & OP=6 & XOP_12_VLE=8 & BIT_11=1 & D & A & SCALE { + D = A + SCALE; + cr0flags(D); +} + +:se_addi RX_VLE,OIMM is $(ISVLE) & OP6_VLE=8 & BIT9_VLE=0 & RX_VLE & OIMM { + RX_VLE = RX_VLE + OIMM; +} + +:e_addic D,A,SCALE is $(ISVLE) & OP=6 & XOP_12_VLE=9 & BIT_11=0 & D & A & SCALE { + xer_ca = carry(A,SCALE); + D = A + SCALE; +} + +:e_addic. D,A,SCALE is $(ISVLE) & OP=6 & XOP_12_VLE=9 & BIT_11=1 & D & A & SCALE { + xer_ca = carry(A,SCALE); + D = A + SCALE; + cr0flags(D); +} + +:se_sub RX_VLE,RY_VLE is $(ISVLE) & OP6_VLE=1 & BITS_8_9=2 & RX_VLE & RY_VLE { + RX_VLE = RX_VLE - RY_VLE; +} + +:se_subf RX_VLE,RY_VLE is $(ISVLE) & OP6_VLE=1 & BITS_8_9=3 & RX_VLE & RY_VLE { + RX_VLE = RY_VLE - RX_VLE; +} + +:e_subfic D,A,SCALE is $(ISVLE) & OP=6 & XOP_12_VLE=11 & BIT_11=0 & D & A & SCALE { + xer_ca = (A <= SCALE); + D = SCALE - A; +} + +:e_subfic. D,A,SCALE is $(ISVLE) & OP=6 & XOP_12_VLE=11 & BIT_11=1 & D & A & SCALE { + xer_ca = (A <= SCALE); + D = SCALE - A; + cr0flags(D); +} + +:se_subi RX_VLE,OIMM is $(ISVLE) & OP6_VLE=9 & BIT9_VLE=0 & RX_VLE & OIMM { + RX_VLE = RX_VLE - OIMM; +} + +:se_subi. RX_VLE,OIMM is $(ISVLE) & OP6_VLE=9 & BIT9_VLE=1 & RX_VLE & OIMM { + RX_VLE = RX_VLE - OIMM; + cr0flags(RX_VLE); +} + +:e_mulli D,A,SCALE is $(ISVLE) & OP=6 & XOP_11_VLE=20 & D & A & SCALE { + tmp1:16 = sext(A); + tmp2:16 = sext(SCALE); + tmpP:16 = tmp1 * tmp2; + D = tmpP:$(REGISTER_SIZE); +} + +:e_mull2i. A,SIMM16 is $(ISVLE) & OP=28 & XOP_11_VLE=20 & A & SIMM16 { + tmp1:16 = sext(A); + tmp2:16 = sext(SIMM16); + tmpP:16 = tmp1 * tmp2; + A = tmpP:$(REGISTER_SIZE); +} + +:se_mullw RX_VLE,RY_VLE is $(ISVLE) & OP6_VLE=1 & BITS_8_9=1 & RX_VLE & RY_VLE { + RX_VLE = RX_VLE * RY_VLE; +} + +:se_neg RX_VLE is $(ISVLE) & OP6_VLE=0 & XOR_VLE=3 & RX_VLE { + RX_VLE = ~RX_VLE + 1; +} + +:se_btsti RX_VLE,OIM5_VLE is $(ISVLE) & OP6_VLE=25 & BIT9_VLE=1 & RX_VLE & OIM5_VLE { + tmp:$(REGISTER_SIZE) = (RX_VLE >> (0x1F - OIM5_VLE)) & 0x1; + cr0flags(tmp); +} + +:e_cmp16i. A,SIMM16 is $(ISVLE) & OP=28 & XOP_11_VLE=19 & A & SIMM16 { + tmpA:4 = A:4; + tmpB:4 = sext(SIMM16); + cr0 = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1); +} + + +:e_cmpi BF_VLE,A,SCALE is $(ISVLE) & OP=6 & XOP_11_VLE=21 & BITS_23_25=0 & A & BF_VLE & SCALE { + tmpA:4 = A:4; + tmpB:4 = SCALE:4; + BF_VLE = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1); +} + +:se_cmp RX_VLE,RY_VLE is $(ISVLE) & OP6_VLE=3 & BITS_8_9=0 & RX_VLE & RY_VLE { + tmpA:4 = RX_VLE:4; + tmpB:4 = RY_VLE:4; + cr0 = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1); +} + +:se_cmpi RX_VLE,OIM5_VLE is $(ISVLE) & OP6_VLE=10 & BIT9_VLE=1 & RX_VLE & OIM5_VLE { + tmpA:4 = RX_VLE:4; + tmpB:4 = OIM5_VLE; + cr0 = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1); +} + +:e_cmpl16i. A,IMM16 is $(ISVLE) & OP=28 & XOP_11_VLE=21 & A & IMM16 { + tmpA:4 = A:4; + tmpB:4 = zext(IMM16); + cr0 = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1); +} + +:e_cmpli BF_VLE,A,SCALE is $(ISVLE) & OP=6 & XOP_11_VLE=21 & BITS_23_25=1 & A & BF_VLE & SCALE { + tmpA:4 = A:4; + tmpB:4 = SCALE:4; + BF_VLE = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1); +} + +:se_cmpl RX_VLE,RY_VLE is $(ISVLE) & OP6_VLE=3 & BITS_8_9=1 & RX_VLE & RY_VLE { + tmpA:4 = RX_VLE:4; + tmpB:4 = RY_VLE:4; + cr0 = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1); +} + +:se_cmpli RX_VLE,OIMM is $(ISVLE) & OP6_VLE=8 & BIT9_VLE=1 & RX_VLE & OIMM { + tmpA:4 = RX_VLE:4; + tmpB:4 = OIMM:4; + cr0 = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1); +} + +:e_cmph CRFD,A,B is $(ISVLE) & OP=31 & BITS_21_22=0 & BIT_0=0 & XOP_1_10=14 & A & B & CRFD { + tmpA:2 = A:2; + tmpB:2 = B:2; + CRFD = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1); +} + +:se_cmph RX_VLE,RY_VLE is $(ISVLE) & OP6_VLE=3 & BITS_8_9=2 & RX_VLE & RY_VLE { + tmpA:2 = RX_VLE:2; + tmpB:2 = RY_VLE:2; + cr0 = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1); +} + +:e_cmph16i. A,SIMM16 is $(ISVLE) & OP=28 & XOP_11_VLE=22 & A & SIMM16 { + tmpA:2 = A:2; + tmpB:2 = SIMM16; + cr0 = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1); +} + +:e_cmphl CRFD,A,B is $(ISVLE) & OP=31 & BITS_21_22=0 & BIT_0=0 & XOP_1_10=46 & A & B & CRFD { + tmpA:2 = A:2; + tmpB:2 = B:2; + tmpC:1 = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1); + CRFD = tmpC; +} + +:se_cmphl RX_VLE,RY_VLE is $(ISVLE) & OP6_VLE=3 & BITS_8_9=3 & RX_VLE & RY_VLE { + tmpA:2 = RX_VLE:2; + tmpB:2 = RY_VLE:2; + cr0 = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1); +} + +:e_cmphl16i. A,IMM16 is $(ISVLE) & OP=28 & XOP_11_VLE=23 & A & IMM16 { + tmpA:2 = A:2; + tmpB:2 = IMM16; + cr0 = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1); +} + +:e_and2i. D,IMM16B is $(ISVLE) & OP=28 & XOP_11_VLE=25 & D & IMM16B { + D = D & zext(IMM16B); + cr0flags(D); +} + +:e_and2is. D,IMM16B is $(ISVLE) & OP=28 & XOP_11_VLE=29 & D & IMM16B { + tmp:$(REGISTER_SIZE) = zext(IMM16B); + tmp = tmp << 16; + D = D & tmp; + cr0flags(D); +} + +:e_andi A,S,SCALE is $(ISVLE) & OP=6 & XOP_12_VLE=12 & BIT_11=0 & S & A & SCALE { + A = S & SCALE; +} + +:e_andi. A,S,SCALE is $(ISVLE) & OP=6 & XOP_12_VLE=12 & BIT_11=1 & S & A & SCALE { + A = S & SCALE; + cr0flags(A); +} + +:se_andi RX_VLE,OIM5_VLE is $(ISVLE) & OP6_VLE=11 & BIT9_VLE=1 & RX_VLE & OIM5_VLE { + tmp:1 = OIM5_VLE; + RX_VLE = RX_VLE & zext(tmp); +} + +:e_or2i D,IMM16B is $(ISVLE) & OP=28 & XOP_11_VLE=24 & D & IMM16B { + D = D | zext(IMM16B); +} + +:e_or2is D,IMM16B is $(ISVLE) & OP=28 & XOP_11_VLE=26 & D & IMM16B { + tmp:$(REGISTER_SIZE) = zext(IMM16B); + tmp = tmp << 16; + D = D | tmp; +} + +:e_ori A,S,SCALE is $(ISVLE) & OP=6 & XOP_12_VLE=13 & BIT_11=0 & S & A & SCALE { + A = S | SCALE; +} + +:e_ori. A,S,SCALE is $(ISVLE) & OP=6 & XOP_12_VLE=13 & BIT_11=1 & S & A & SCALE { + A = S | SCALE; + cr0flags(A); +} + +:e_xori A,S,SCALE is $(ISVLE) & OP=6 & XOP_12_VLE=14 & BIT_11=0 & S & A & SCALE { + A = S ^ SCALE; +} + +:e_xori. A,S,SCALE is $(ISVLE) & OP=6 & XOP_12_VLE=14 & BIT_11=1 & S & A & SCALE { + A = S ^ SCALE; + cr0flags(A); +} + +:se_and RX_VLE,RY_VLE is $(ISVLE) & OP6_VLE=17 & BIT9_VLE=1 & BIT8_VLE=0 & RX_VLE & RY_VLE { + RX_VLE = RX_VLE & RY_VLE; +} + +:se_and. RX_VLE,RY_VLE is $(ISVLE) & OP6_VLE=17 & BIT9_VLE=1 & BIT8_VLE=1 & RX_VLE & RY_VLE { + RX_VLE = RX_VLE & RY_VLE; + cr0flags(RX_VLE); +} + +:se_andc RX_VLE,RY_VLE is $(ISVLE) & OP6_VLE=17 & BITS_8_9=1 & RX_VLE & RY_VLE { + RX_VLE = RX_VLE & ~RY_VLE; +} + +:se_or RX_VLE,RY_VLE is $(ISVLE) & OP6_VLE=17 & BITS_8_9=0 & RX_VLE & RY_VLE { + RX_VLE = RX_VLE | RY_VLE; +} + +:se_not RX_VLE is $(ISVLE) & OP6_VLE=0 & XOR_VLE=2 & RX_VLE { + RX_VLE = ~RX_VLE; +} + +:se_bclri RX_VLE,OIM5_VLE is $(ISVLE) & OP6_VLE=24 & BIT9_VLE=0 & RX_VLE & OIM5_VLE { + tmp:$(REGISTER_SIZE) = 0x80000000 >> OIM5_VLE; + tmp = ~tmp; + RX_VLE = RX_VLE & tmp; +} + +:se_bgeni RX_VLE,OIM5_VLE is $(ISVLE) & OP6_VLE=24 & BIT9_VLE=1 & RX_VLE & OIM5_VLE { + RX_VLE = 0x80000000 >> OIM5_VLE; +} + +:se_bmaski RX_VLE,OIM5_VLE is $(ISVLE) & OP6_VLE=11 & BIT9_VLE=0 & RX_VLE & OIM5_VLE { + RX_VLE = ~0; + sa:4 = (8 * $(REGISTER_SIZE) - OIM5_VLE) * zext( OIM5_VLE != 0:1 ); + RX_VLE = RX_VLE >> sa; +} + +:se_bseti RX_VLE,OIM5_VLE is $(ISVLE) & OP6_VLE=25 & BIT9_VLE=0 & RX_VLE & OIM5_VLE { + tmp:$(REGISTER_SIZE) = 0x80000000 >> OIM5_VLE; + RX_VLE = RX_VLE | tmp; +} + +:se_extsb RX_VLE is $(ISVLE) & OP6_VLE=0 & XOR_VLE=13 & RX_VLE { + RX_VLE = sext(RX_VLE:1); +} + +:se_extsh RX_VLE is $(ISVLE) & OP6_VLE=0 & XOR_VLE=15 & RX_VLE { + RX_VLE = sext(RX_VLE:2); +} + +:se_extzb RX_VLE is $(ISVLE) & OP6_VLE=0 & XOR_VLE=12 & RX_VLE { + RX_VLE = zext(RX_VLE:1); +} + +:se_extzh RX_VLE is $(ISVLE) & OP6_VLE=0 & XOR_VLE=14 & RX_VLE { + RX_VLE = zext(RX_VLE:2); +} + +:e_li D,SIMM20 is $(ISVLE) & OP=28 & BIT_15=0 & D & SIMM20 { + D = sext(SIMM20); +} + +:se_li RX_VLE,OIM7_VLE is $(ISVLE) & OP5_VLE=9 & RX_VLE & OIM7_VLE { + RX_VLE = OIM7_VLE; +} + +:e_lis D,IMM16B is $(ISVLE) & OP=28 & XOP_11_VLE=28 & D & IMM16B { + tmp:$(REGISTER_SIZE) = zext(IMM16B); + D = tmp << 16; +} + +:se_mfar RX_VLE,ARY_VLE is $(ISVLE) & OP6_VLE=0 & BITS_8_9=3 & RX_VLE & ARY_VLE { + RX_VLE = ARY_VLE; +} + +:se_mr RX_VLE,RY_VLE is $(ISVLE) & OP6_VLE=0 & BITS_8_9=1 & RX_VLE & RY_VLE { + RX_VLE = RY_VLE; +} + +:se_mtar ARX_VLE,RY_VLE is $(ISVLE) & OP6_VLE=0 & BITS_8_9=2 & ARX_VLE & RY_VLE { + ARX_VLE = RY_VLE; +} + +:e_rlw A,S,B is $(ISVLE) & OP=31 & BIT_0=0 & XOP_1_10=280 & A & B & S { + tmpB:1 = B[0,5]; + tmpS:4 = S:4; + tmpA:4 = (tmpS << tmpB) | (tmpS >> (32 - tmpB)); + A = zext(tmpA); +} + +:e_rlw. A,S,B is $(ISVLE) & OP=31 & BIT_0=1 & XOP_1_10=280 & A & B & S { + tmpB:1 = B[0,5]; + tmpS:4 = S:4; + tmpA:4 = (tmpS << tmpB) | (tmpS >> (32 - tmpB)); + A = zext(tmpA); + cr0flags(A); +} + +:e_rlwi A,S,SHL is $(ISVLE) & OP=31 & BIT_0=0 & XOP_1_10=312 & A & SHL & S { + tmpS:4 = S:4; + tmpA:4 = (tmpS << SHL) | (tmpS >> (32 - SHL)); + A = zext(tmpA); +} + +:e_rlwi. A,S,SHL is $(ISVLE) & OP=31 & BIT_0=1 & XOP_1_10=312 & A & SHL & S { + tmpS:4 = S:4; + tmpA:4 = (tmpS << SHL) | (tmpS >> (32 - SHL)); + A = zext(tmpA); + cr0flags(A); +} + +# The manual uses MB instead of NB here, but because the "MB" symbol is already taken, NB it is +:e_rlwimi A,S,SHL,MBL,ME is $(ISVLE) & OP=29 & BIT_0=0 & MBL & ME & A & SHL & S { + tmpS:4 = S:4; + tmpA:4 = (tmpS << SHL) | (tmpS >> (32 - SHL)); + tmpM:4 = ~0:4; + if (ME:1 < MBL:1) goto ; + tmpM = tmpM << MBL; + tmpM = tmpM >> ((31-ME) + MBL); + tmpM = tmpM << (31-ME); + goto ; + + tmpM = tmpM << ME; + tmpM = tmpM >> ((31-MBL) + ME); + tmpM = tmpM << (31-MBL); + tmpM = ~tmpM; + + A = zext(tmpA & tmpM) | (A & zext(~tmpM)); +} + +:e_rlwinm A,S,SHL,MBL,ME is $(ISVLE) & OP=29 & BIT_0=1 & MBL & ME & A & SHL & S { + tmpS:4 = S:4; + tmpA:4 = (tmpS << SHL) | (tmpS >> (32 - SHL)); + tmpM:4 = ~0:4; + if (ME:1 < MBL:1) goto ; + tmpM = tmpM << MBL; + tmpM = tmpM >> ((31-ME) + MBL); + tmpM = tmpM << (31-ME); + goto ; + + tmpM = tmpM << ME; + tmpM = tmpM >> ((31-MBL) + ME); + tmpM = tmpM << (31-MBL); + tmpM = ~tmpM; + + A = zext(tmpA & tmpM); +} + +:e_slwi A,S,SHL is $(ISVLE) & OP=31 & BIT_0=0 & XOP_1_10=56 & A & SHL & S { + tmpS:4 = S:4; + tmpS = tmpS << SHL; + A = zext(tmpS); +} + +:e_slwi. A,S,SHL is $(ISVLE) & OP=31 & BIT_0=1 & XOP_1_10=56 & A & SHL & S { + tmpS:4 = S:4; + tmpS = tmpS << SHL; + A = zext(tmpS); + cr0flags(A); +} + +:se_slwi RX_VLE,OIM5_VLE is $(ISVLE) & OP6_VLE=27 & BIT9_VLE=0 & RX_VLE & OIM5_VLE { + tmpX:4 = RX_VLE:4; + tmpX = tmpX << OIM5_VLE; + RX_VLE = zext(tmpX); +} + +:se_slw RX_VLE,RY_VLE is $(ISVLE) & OP6_VLE=16 & BITS_8_9=2 & RX_VLE & RY_VLE { + tmpX:4 = RX_VLE:4; + tmpS:1 = RY_VLE[0,6]; + tmpX = tmpX << tmpS; + RX_VLE = zext(tmpX); +} + +:se_srawi RX_VLE,OIM5_VLE is $(ISVLE) & OP6_VLE=26 & BIT9_VLE=1 & RX_VLE & OIM5_VLE { + tmpX:4 = RX_VLE:4; + tmpX = tmpX s>> OIM5_VLE; + RX_VLE = sext(tmpX); + xer_ca = (RX_VLE s< 0) & (OIM5_VLE:1 != 0); +} + +:se_sraw RX_VLE,RY_VLE is $(ISVLE) & OP6_VLE=16 & BITS_8_9=1 & RX_VLE & RY_VLE { + tmpX:4 = RX_VLE:4; + tmpS:1 = RY_VLE[0,5]; + tmpX = tmpX s>> tmpS; + RX_VLE = sext(tmpX); + xer_ca = (RX_VLE s< 0) & (tmpS != 0); +} + +:e_srwi A,S,SHL is $(ISVLE) & OP=31 & BIT_0=0 & XOP_1_10=568 & A & SHL & S { + tmpS:4 = S:4; + tmpS = tmpS >> SHL; + A = zext(tmpS); +} + +:e_srwi. A,S,SHL is $(ISVLE) & OP=31 & BIT_0=1 & XOP_1_10=568 & A & SHL & S { + tmpS:4 = S:4; + tmpS = tmpS >> SHL; + A = zext(tmpS); + cr0flags(A); +} + +:se_srwi RX_VLE,OIM5_VLE is $(ISVLE) & OP6_VLE=26 & BIT9_VLE=0 & RX_VLE & OIM5_VLE { + tmpX:4 = RX_VLE:4; + tmpX = tmpX >> OIM5_VLE; + RX_VLE = zext(tmpX); +} + +:se_srw RX_VLE,RY_VLE is $(ISVLE) & OP6_VLE=16 & BITS_8_9=0 & RX_VLE & RY_VLE { + tmpX:4 = RX_VLE:4; + tmpS:1 = RY_VLE[0,5]; + tmpX = tmpX >> tmpS; + RX_VLE = zext(tmpX); +} + +:se_mfctr RX_VLE is $(ISVLE) & OP6_VLE=0 & XOR_VLE=10 & RX_VLE { + RX_VLE = CTR; +} + +:se_mtctr RX_VLE is $(ISVLE) & OP6_VLE=0 & XOR_VLE=11 & RX_VLE { + CTR = RX_VLE; +} + +:se_mflr RX_VLE is $(ISVLE) & OP6_VLE=0 & XOR_VLE=8 & RX_VLE { + RX_VLE = LR; +} + +:se_mtlr RX_VLE is $(ISVLE) & OP6_VLE=0 & XOR_VLE=9 & RX_VLE { + LR = RX_VLE; +} + +:se_isync is $(ISVLE) & OP16_VLE=1 { + instructionSynchronize(); +} diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/quicciii.sinc b/python/icicle/Ghidra/Processors/PowerPC/data/languages/quicciii.sinc new file mode 100644 index 0000000..8b7977b --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/quicciii.sinc @@ -0,0 +1,131 @@ +# These instructions show up in the Freescale PowerQUICC III instruction manual +# (not present elsewhere) + +define pcodeop dataCacheBlockClearLock; +define pcodeop prefetchDataCacheBlockLockSet; +define pcodeop prefetchDataCacheBlockLockSetX; +define pcodeop debuggerNotifyHalt; +define pcodeop instructionCacheBlockClearLock; +define pcodeop queryInstructionCacheBlockLock; +define pcodeop prefetchInstructionCacheBlockLockSetX; +define pcodeop memoryBarrier; +define pcodeop moveFromAPIDIndirect; +define pcodeop moveFromPerformanceMonitorRegister; +define pcodeop moveToPerformanceMonitorRegister; +define pcodeop invalidateTLB; + +#dcblc 0,0,r0 #FIXME +:dcblc CT,RA_OR_ZERO,B is OP=31 & CT & B & XOP_1_10=390 & BIT_0=0 & RA_OR_ZERO +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + dataCacheBlockClearLock(ea); +} + +#dcbtls 0,0,r0 #FIXME +:dcbtls CT,RA_OR_ZERO,B is OP=31 & CT & B & XOP_1_10=166 & BIT_0=0 & RA_OR_ZERO +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + prefetchDataCacheBlockLockSet(ea); +} + +#dcbtstls 0,0,r0 #FIXME +:dcbtstls CT,RA_OR_ZERO,B is OP=31 & CT & B & XOP_1_10=134 & BIT_0=0 & RA_OR_ZERO +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + prefetchDataCacheBlockLockSetX(ea); +} + +#dnh 0,0 #FIXME +:dnh DUI,DUIS is $(NOTVLE) & OP=19 & DUI & DUIS & XOP_1_10=198 & BIT_0=0 +{ + debuggerNotifyHalt(DUI:1,DUIS:2); +} + +#icblc 0,0,r0 #FIXME +:icblc CT,RA_OR_ZERO,B is OP=31 & CT & B & XOP_1_10=230 & BIT_0=0 & RA_OR_ZERO +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + instructionCacheBlockClearLock(CT:1,ea); +} + +:icblq CT,RA_OR_ZERO,B is OP=31 & CT & B & XOP_1_10=198 & BIT_0=1 & RA_OR_ZERO +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + cr0 = queryInstructionCacheBlockLock(CT:1,ea); +} + +#icbtls 0,0,r0 #FIXME +:icbtls CT,RA_OR_ZERO,B is OP=31 & CT & B & XOP_1_10=486 & BIT_0=0 & RA_OR_ZERO +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + prefetchInstructionCacheBlockLockSetX(ea); +} + +:isel^CC_X_OPm D,RA_OR_ZERO,B,CC_X_OP is OP=31 & D & RA_OR_ZERO & B & CC_X_OP & CC_X_OPm & XOP_1_5=15 +{ + local tmp:$(REGISTER_SIZE) = RA_OR_ZERO; + D = B; + if (!CC_X_OP) goto inst_next; + D = tmp; +# D = (zext(CC_X_OP) * RA_OR_ZERO) + (zext(!CC_X_OP) * B); +} + +@ifndef IS_ISA +#mbar 0 #FIXME +:mbar MO is OP=31 & MO & XOP_1_10=854 +{ + memoryBarrier(MO:1); +} +@endif + +#mfapidi r0,r1 #FIXME +:mfapidi D,A is $(NOTVLE) & OP=31 & D & A & XOP_1_10=275 +{ + D = moveFromAPIDIndirect(A); +} + +pmrn: pmr is BITS_16_20 & BITS_11_15 [ pmr = BITS_11_15 << 5 | BITS_16_20; ] { tmp:2 = pmr; export tmp; } + +#mfpmr r0,? #FIXME +:mfpmr D,pmrn is OP=31 & D & pmrn & XOP_1_10=334 & BIT_0=0 +{ + D = moveFromPerformanceMonitorRegister(pmrn); +} + +#mtpmr r0,? #FIXME +:mtpmr pmrn,S is OP=31 & S & pmrn & XOP_1_10=462 & BIT_0=0 +{ + moveToPerformanceMonitorRegister(pmrn, S); +} + +#rfdi #FIXME +:rfdi is $(NOTVLE) & OP=19 & XOP_1_10=39 +{ + MSR = returnFromDebugInterrupt(MSR, spr23f); #DSRR1 + local ra = spr23e; #DSRR0 + return[ra]; +} + +#rfmci #FIXME +:rfmci is $(NOTVLE) & OP=19 & XOP_0_10=76 +{ + MSR = returnFromMachineCheckInterrupt(MSR, spr23b); #MCSRR1 + local ra = spr23a; #MCSRR0 + return[ra]; +} + + +# PowerISA II: 6.11.4.9 TLB Management Instructions +# CMT: TLB Invalidate Local Indexed [Category: Embedded.Phased In]] +# FORM: X-form +define pcodeop TLBInvalidateLocalIndexed; # Outputs/affect TBD +:tlbilx BITS_21_22,RA_OR_ZERO,RB_OR_ZERO is $(NOTVLE) & OP=31 & CRFD=0 & BITS_21_22 & RA_OR_ZERO & RB_OR_ZERO & XOP_1_10=18 & BIT_0=0 { + TLBInvalidateLocalIndexed(BITS_21_22:1,RA_OR_ZERO,RB_OR_ZERO); +} + +#tlbivax 0,r0 #FIXME +:tlbivax RA_OR_ZERO,B is OP=31 & RA_OR_ZERO & B & XOP_1_10=786 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + invalidateTLB(ea); +} diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/stmwInstructions.sinc b/python/icicle/Ghidra/Processors/PowerPC/data/languages/stmwInstructions.sinc new file mode 100644 index 0000000..f39f275 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/stmwInstructions.sinc @@ -0,0 +1,101 @@ +STMR0: is lsmul=1 {} +STMR0: is epsilon { storeReg(r0); } + +STMR1: is lsmul=2 {} +STMR1: is STMR0 { build STMR0; storeReg(r1); } + +STMR2: is lsmul=3 {} +STMR2: is STMR1 { build STMR1; storeReg(r2); } + +STMR3: is lsmul=4 {} +STMR3: is STMR2 { build STMR2; storeReg(r3); } + +STMR4: is lsmul=5 {} +STMR4: is STMR3 { build STMR3; storeReg(r4); } + +STMR5: is lsmul=6 {} +STMR5: is STMR4 { build STMR4; storeReg(r5); } + +STMR6: is lsmul=7 {} +STMR6: is STMR5 { build STMR5; storeReg(r6); } + +STMR7: is lsmul=8 {} +STMR7: is STMR6 { build STMR6; storeReg(r7); } + +STMR8: is lsmul=9 {} +STMR8: is STMR7 { build STMR7; storeReg(r8); } + +STMR9: is lsmul=10 {} +STMR9: is STMR8 { build STMR8; storeReg(r9); } + +STMR10: is lsmul=11 {} +STMR10: is STMR9 { build STMR9; storeReg(r10); } + +STMR11: is lsmul=12 {} +STMR11: is STMR10 { build STMR10; storeReg(r11); } + +STMR12: is lsmul=13 {} +STMR12: is STMR11 { build STMR11; storeReg(r12); } + +STMR13: is lsmul=14 {} +STMR13: is STMR12 { build STMR12; storeReg(r13); } + +STMR14: is lsmul=15 {} +STMR14: is STMR13 { build STMR13; storeReg(r14); } + +STMR15: is lsmul=16 {} +STMR15: is STMR14 { build STMR14; storeReg(r15); } + +STMR16: is lsmul=17 {} +STMR16: is STMR15 { build STMR15; storeReg(r16); } + +STMR17: is lsmul=18 {} +STMR17: is STMR16 { build STMR16; storeReg(r17); } + +STMR18: is lsmul=19 {} +STMR18: is STMR17 { build STMR17; storeReg(r18); } + +STMR19: is lsmul=20 {} +STMR19: is STMR18 { build STMR18; storeReg(r19); } + +STMR20: is lsmul=21 {} +STMR20: is STMR19 { build STMR19; storeReg(r20); } + +STMR21: is lsmul=22 {} +STMR21: is STMR20 { build STMR20; storeReg(r21); } + +STMR22: is lsmul=23 {} +STMR22: is STMR21 { build STMR21; storeReg(r22); } + +STMR23: is lsmul=24 {} +STMR23: is STMR22 { build STMR22; storeReg(r23); } + +STMR24: is lsmul=25 {} +STMR24: is STMR23 { build STMR23; storeReg(r24); } + +STMR25: is lsmul=26 {} +STMR25: is STMR24 { build STMR24; storeReg(r25); } + +STMR26: is lsmul=27 {} +STMR26: is STMR25 { build STMR25; storeReg(r26); } + +STMR27: is lsmul=28 {} +STMR27: is STMR26 { build STMR26; storeReg(r27); } + +STMR28: is lsmul=29 {} +STMR28: is STMR27 { build STMR27; storeReg(r28); } + +STMR29: is lsmul=30 {} +STMR29: is STMR28 { build STMR28; storeReg(r29); } + +STMR30: is lsmul=31 {} +STMR30: is STMR29 { build STMR29; storeReg(r30); } + +STMR31: is STMR30 { build STMR30; storeReg(r31); } + +:stmw S,dPlusRaOrZeroAddress is $(NOTVLE) & OP=47 & S & BITS_21_25 & dPlusRaOrZeroAddress & STMR31 [ lsmul = BITS_21_25; ] +{ + tea = dPlusRaOrZeroAddress; + build STMR31; +} + diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/stswiInstructions.sinc b/python/icicle/Ghidra/Processors/PowerPC/data/languages/stswiInstructions.sinc new file mode 100644 index 0000000..cf7c809 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/stswiInstructions.sinc @@ -0,0 +1,186 @@ +#stswi r5,r3,0x02 7c a4 14 aa +#stswi r5,r4,0x08 7c a4 44 aa + + +DYN_S1: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 1)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; } +DYN_S2: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 2)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; } +DYN_S3: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 3)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; } +DYN_S4: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 4)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; } +DYN_S5: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 5)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; } +DYN_S6: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 6)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; } +DYN_S7: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 7)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; } + +:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=0 & BH=0 & XOP_1_10=725 & BIT_0=0 + & DYN_S1 & DYN_S2 & DYN_S3 & DYN_S4 & DYN_S5 & DYN_S6 & DYN_S7 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + storeRegister(S,ea); + storeRegister(DYN_S1,ea); + storeRegister(DYN_S2,ea); + storeRegister(DYN_S3,ea); + storeRegister(DYN_S4,ea); + storeRegister(DYN_S5,ea); + storeRegister(DYN_S6,ea); + storeRegister(DYN_S7,ea); +} + +:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=0 & BH & XOP_1_10=725 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + sa:1 = BH; + storeRegisterPartial(S,ea,sa); +} + +:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=1 & BH=0 & XOP_1_10=725 & BIT_0=0 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + storeRegister(S,ea); +} + +:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=1 & BH & XOP_1_10=725 & BIT_0=0 + & DYN_S1 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + storeRegister(S,ea); + sa:1 = BH; + storeRegisterPartial(DYN_S1,ea,sa); +} + + +:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=2 & BH=0 & XOP_1_10=725 & BIT_0=0 + & DYN_S1 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + storeRegister(S,ea); + storeRegister(DYN_S1,ea); +} + +:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=2 & BH & XOP_1_10=725 & BIT_0=0 + & DYN_S1 & DYN_S2 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + storeRegister(S,ea); + storeRegister(DYN_S1,ea); + sa:1 = BH; + storeRegisterPartial(DYN_S2,ea,sa); +} + +:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=3 & BH=0 & XOP_1_10=725 & BIT_0=0 + & DYN_S1 & DYN_S2 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + storeRegister(S,ea); + storeRegister(DYN_S1,ea); + storeRegister(DYN_S2,ea); +} + +:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=3 & BH & XOP_1_10=725 & BIT_0=0 + & DYN_S1 & DYN_S2 & DYN_S3 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + storeRegister(S,ea); + storeRegister(DYN_S1,ea); + storeRegister(DYN_S2,ea); + sa:1 = BH; + storeRegisterPartial(DYN_S3,ea,sa); +} + +:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=4 & BH=0 & XOP_1_10=725 & BIT_0=0 + & DYN_S1 & DYN_S2 & DYN_S3 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + storeRegister(S,ea); + storeRegister(DYN_S1,ea); + storeRegister(DYN_S2,ea); + storeRegister(DYN_S3,ea); +} + +:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=4 & BH & XOP_1_10=725 & BIT_0=0 + & DYN_S1 & DYN_S2 & DYN_S3 & DYN_S4 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + storeRegister(S,ea); + storeRegister(DYN_S1,ea); + storeRegister(DYN_S2,ea); + storeRegister(DYN_S3,ea); + sa:1 = BH; + storeRegisterPartial(DYN_S4,ea,sa); +} + +:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=5 & BH=0 & XOP_1_10=725 & BIT_0=0 + & DYN_S1 & DYN_S2 & DYN_S3 & DYN_S4 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + storeRegister(S,ea); + storeRegister(DYN_S1,ea); + storeRegister(DYN_S2,ea); + storeRegister(DYN_S3,ea); + storeRegister(DYN_S4,ea); +} + +:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=5 & BH & XOP_1_10=725 & BIT_0=0 + & DYN_S1 & DYN_S2 & DYN_S3 & DYN_S4 & DYN_S5 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + storeRegister(S,ea); + storeRegister(DYN_S1,ea); + storeRegister(DYN_S2,ea); + storeRegister(DYN_S3,ea); + storeRegister(DYN_S4,ea); + sa:1 = BH; + storeRegisterPartial(DYN_S5,ea,sa); +} + +:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=6 & BH=0 & XOP_1_10=725 & BIT_0=0 + & DYN_S1 & DYN_S2 & DYN_S3 & DYN_S4 & DYN_S5 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + storeRegister(S,ea); + storeRegister(DYN_S1,ea); + storeRegister(DYN_S2,ea); + storeRegister(DYN_S3,ea); + storeRegister(DYN_S4,ea); + storeRegister(DYN_S5,ea); +} + +:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=6 & BH & XOP_1_10=725 & BIT_0=0 + & DYN_S1 & DYN_S2 & DYN_S3 & DYN_S4 & DYN_S5 & DYN_S6 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + storeRegister(S,ea); + storeRegister(DYN_S1,ea); + storeRegister(DYN_S2,ea); + storeRegister(DYN_S3,ea); + storeRegister(DYN_S4,ea); + storeRegister(DYN_S5,ea); + sa:1 = BH; + storeRegisterPartial(DYN_S6,ea,sa); +} + +:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=7 & BH=0 & XOP_1_10=725 & BIT_0=0 + & DYN_S1 & DYN_S2 & DYN_S3 & DYN_S4 & DYN_S5 & DYN_S6 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + storeRegister(S,ea); + storeRegister(DYN_S1,ea); + storeRegister(DYN_S2,ea); + storeRegister(DYN_S3,ea); + storeRegister(DYN_S4,ea); + storeRegister(DYN_S5,ea); + storeRegister(DYN_S6,ea); +} + +:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=7 & BH & XOP_1_10=725 & BIT_0=0 + & DYN_S1 & DYN_S2 & DYN_S3 & DYN_S4 & DYN_S5 & DYN_S6 & DYN_S7 +{ + ea:$(REGISTER_SIZE) = RA_OR_ZERO; + storeRegister(S,ea); + storeRegister(DYN_S1,ea); + storeRegister(DYN_S2,ea); + storeRegister(DYN_S3,ea); + storeRegister(DYN_S4,ea); + storeRegister(DYN_S5,ea); + storeRegister(DYN_S6,ea); + sa:1 = BH; + storeRegisterPartial(DYN_S7,ea,sa); +} diff --git a/python/icicle/Ghidra/Processors/PowerPC/data/languages/vsx.sinc b/python/icicle/Ghidra/Processors/PowerPC/data/languages/vsx.sinc new file mode 100644 index 0000000..b922a31 --- /dev/null +++ b/python/icicle/Ghidra/Processors/PowerPC/data/languages/vsx.sinc @@ -0,0 +1,1665 @@ +# Source for information on instructions: +# PowerISA_V2.06B_PUBLIC.pdf (dated: July 23, 2010) +# and binutils-2.21.1 + +# version 1.0 + +# ========================================================================================================== +# VSX use of XA,XB,XC,XT +# ========================================================================================================== +# PowerPC VSX allows for VSX registers values to come from a combination of 2 different fields +# XA is the value of A and AX concatenated. (A has 5 bits and AX 1 so allows for 6 bits or 64 registers). +# XB is the value of B and BX concatenated. (B has 5 bits and BX 1 so allows for 6 bits or 64 registers). +# XC is the value of C and CX concatenated. (C has 5 bits and CX 1 so allows for 6 bits or 64 registers). +# XT is the value of T and TX concatenated. (T has 5 bits and TX 1 so allows for 6 bits or 64 registers). +# +# NOTE: A,B,C,T are all 5 bits long and AX,BX,CX,TX are all 1 bit long. +# +# In order to print the registers defined in XA,XB,XC,XT we need to play some tricks. +# Normally you use a "attach variables [ field ...] [ name1 ... ]; to attach names to fields but because +# we need to attach names to 2 fields and that is not directly supported in sleigh. +# +# We attach the low registers (0 to 31) to fields that overlap the normal A,B,C,T named Avsa, Bvsa, Bvsa, Bvsa. +# We attach the high registers (31 to 63) to fields that overlap the normal A,B,C,T named Avsb, Bvsb, Bvsb, Bvsb. +# +# Then we make constructors dependent on the AX,BX,CX,TX values to switch between them as needed. +#define token instr(32) +#... +# support VSX args +# Avsa=(16,20) +# Avsb=(16,20) +# Bvsa=(11,15) +# Bvsb=(11,15) +# Cvsa=(6,10) +# Cvsb=(6,10) +# Tvsa=(21,25) +# Tvsb=(21,25) +#... +#; +# Attach low VSX registers +attach variables [ Avsa Bvsa Cvsa Svsa Tvsa ] + [ vs0 vs1 vs2 vs3 vs4 vs5 vs6 vs7 vs8 vs9 vs10 vs11 vs12 vs13 vs14 vs15 + vs16 vs17 vs18 vs19 vs20 vs21 vs22 vs23 vs24 vs25 vs26 vs27 vs28 vs29 vs30 vs31 + ]; +# Attach hi VSX registers +attach variables [ Avsb Bvsb Cvsb Svsb Tvsb ] + [ vs32 vs33 vs34 vs35 vs36 vs37 vs38 vs39 vs40 vs41 vs42 vs43 vs44 vs45 vs46 vs47 + vs48 vs49 vs50 vs51 vs52 vs53 vs54 vs55 vs56 vs57 vs58 vs59 vs60 vs61 vs62 vs63 + ]; + +attach variables [ Svsbx Tvsbx ] + [ vr0_64_0 vr1_64_0 vr2_64_0 vr3_64_0 vr4_64_0 vr5_64_0 vr6_64_0 vr7_64_0 + vr8_64_0 vr9_64_0 vr10_64_0 vr11_64_0 vr12_64_0 vr13_64_0 vr14_64_0 vr15_64_0 + vr16_64_0 vr17_64_0 vr18_64_0 vr19_64_0 vr20_64_0 vr21_64_0 vr22_64_0 vr23_64_0 + vr24_64_0 vr25_64_0 vr26_64_0 vr27_64_0 vr28_64_0 vr29_64_0 vr30_64_0 vr31_64_0 + ]; +XA: Avsa is Avsa & AX=0 { export Avsa; } # Low register version of XA (i.e A and AX fields) +XA: Avsb is Avsb & AX=1 { export Avsb; } # Hi register version of XA (i.e A and AX fields) +XB: Bvsa is Bvsa & BX=0 { export Bvsa; } # Low register version of XB (i.e B and BX fields) +XB: Bvsb is Bvsb & BX=1 { export Bvsb; } # Hi register version of XB (i.e B and BX fields) +XC: Cvsa is Cvsa & CX=0 { export Cvsa; } # Low register version of XC (i.e C and CX fields) +XC: Cvsb is Cvsb & CX=1 { export Cvsb; } # Hi register version of XC (i.e C and CX fields) +XS: Svsa is Svsa & SX=0 { export Svsa; } +XS: Svsb is Svsb & SX=1 { export Svsb; } +XS3: Svsa is Svsa & SX3=0 { export Svsa; } +XS3: Svsb is Svsb & SX3=1 { export Svsb; } +XT: Tvsa is Tvsa & TX=0 { export Tvsa; } # Low register version of XT (i.e T and AT fields) +XT: Tvsb is Tvsb & TX=1 { export Tvsb; } # Hi register version of XT (i.e T and AT fields) +XT3: Tvsa is Tvsa & TX3=0 { export Tvsa; } # Low register version of XT (i.e T and AT fields) +XT3: Tvsb is Tvsb & TX3=1 { export Tvsb; } # Hi register version of XT (i.e T and AT fields) + +XSF: fS is fS & SX=0 { export fS; } +XSF: Svsbx is Svsbx & SX=1 { export Svsbx; } +XTF: fT is fT & TX=0 { export fT; } +XTF: Tvsbx is Tvsbx & TX=1 { export Tvsbx; } + + +DBUILD: val is DX & DM2 & DC6 [ val = (DC6 << 6) | (DM2 << 5) | DX; ] { export *[const]:1 val; } +# ========================================================================================================== +# ========================================================================================================== + +define pcodeop lxvdsxOp; +# ISA-info: lxvdsx - Form "XX1" Page 339 Category "VSX" +# binutils: vsx.d: 8: 7d 0a a2 99 lxvdsx vs40,r10,r20 +:lxvdsx XT,A,B is $(NOTVLE) & OP=31 & XT & A & B & XOP_1_10=332 & TX { XT = lxvdsxOp(A,B); } + +# lxsdx XT,RA,RB +# ISA-info: lxsdx - Form "XX1" Page 338 Category "VSX" +# binutils: vsx.d: 0: 7d 0a a4 99 lxsdx vs40,r10,r20 +:lxsdx XT,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & XT & RA_OR_ZERO & B & XOP_1_10=588 & TX { + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + XT[0,64] = *:8 ea; +} + +# name lxvd2x code 7c000698 mask fe0700fc00000000 flags @VSX operands 69 31 38 0 0 0 0 0 +:lxvd2x XT,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & XT & RA_OR_ZERO & B & XOP_1_10=844 { + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + XT[64,64] = *:8 ea; + XT[0,64] = *:8 (ea+8); +} + +define pcodeop stxsdxOp; +# ISA-info: stxsdx - Form "XX1" Page 340 Category "VSX" +# binutils: vsx.d: 10: 7d 0a a5 99 stxsdx vs40,r10,r20 +:stxsdx XT,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & XT & RA_OR_ZERO & B & XOP_1_10=716 & TX { + EA:$(REGISTER_SIZE) = RA_OR_ZERO + B; + *[ram]:8 EA = stxsdxOp(RA_OR_ZERO,B); +} + +# name stxvd2x code 7c000798 mask fe0700fc00000000 flags @VSX operands 69 31 38 0 0 0 0 0 +:stxvd2x XS,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & XS & RA_OR_ZERO & B & XOP_1_10=972 { + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + *:8 ea = XS(8); + *:8 (ea+8) = XS:8; +} + +# ISA-cmt: lxvw4x - Load VSR Vector Word*4 Indexed +# ISA-info: lxvw4x - Form "XX1" Page 339 Category "VSX" +# binutils: vsx.d: c: 7d 0a a6 19 lxvw4x vs40,r10,r20 +:lxvw4x XT,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & XT & RA_OR_ZERO & B & XOP_1_10=780 { + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + XT[96,32] = *:4 ea; + XT[64,32] = *:4 (ea + 4); + XT[32,32] = *:4 (ea + 8); + XT[0,32] = *:4 (ea + 12); +} + +# ISA-cmt: stxvw4x - Store VSR Vector Word*4 Indexed +# ISA-info: stxvw4x - Form "XX1" Page 341 Category "VSX" +# binutils: vsx.d: 18: 7d 0a a7 19 stxvw4x vs40,r10,r20 +:stxvw4x XS,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & XS & RA_OR_ZERO & B & XOP_1_10=908 { + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + *:16 ea = XS; +} + +# ISA-cmt: xxsldwi - VSX Shift Left Double by Word Immediate +# ISA-info: xxsldwi - Form "XX3" Page 501 Category "VSX" +# binutils: vsx.d: 270: f1 12 e2 17 xxsldwi vs40,vs50,vs60,2 +:xxsldwi XT,XA,XB,SHW is $(NOTVLE) & OP=60 & BIT_10 & SHW & BITS_3_7=2 & XA & XB & XT { + tmp:32 = (zext(XA) << 128) | zext(XB); + tmp = tmp >> ((7 - (SHW+3)) * 32); + XT = tmp:16; +} + +define pcodeop xxselOp; +# ISA-cmt: xxsel - VSX Select +# ISA-info: xxsel - Form "XX4" Page 500 Category "VSX" +# binutils: vsx.d: 26c: f1 12 e7 bf xxsel vs40,vs50,vs60,vs62 +:xxsel XT,XA,XB,XC is $(NOTVLE) & OP=60 & XT & XA & XB & XC & BITS_4_5=3 { xxselOp(XA,XB,XC); } + +define pcodeop xxpermdiOp; +# :xxpermdi BITS_21_25,TX,A,AX,B,BX,DM is $(NOTVLE) & OP=60 & XOP_3_10=10 & BITS_21_25 & TX & A & AX & B & BX & DM { xxpermdiOp(A,B); } +# ISA-cmt: xxpermdi - VSX Permute Doubleword Immediate +# ISA-info: xxpermdi - Form "XX3" Page 500 Category "VSX" +# binutils: power7.d: 30: f0 64 29 50 xxpermdi vs3,vs4,vs5,1 +# binutils: power7.d: 34: f1 6c 69 57 xxpermdi vs43,vs44,vs45,1 +# binutils: power7.d: 38: f0 64 2a 50 xxpermdi vs3,vs4,vs5,2 +# binutils: power7.d: 3c: f1 6c 6a 57 xxpermdi vs43,vs44,vs45,2 +# binutils: vsx.d: 23c: f1 12 e1 57 xxpermdi vs40,vs50,vs60,1 +# binutils: vsx.d: 240: f1 12 e2 57 xxpermdi vs40,vs50,vs60,2 +:xxpermdi XT,XA,XB,DM is $(NOTVLE) & OP=60 & OE & DM & BITS_3_7=10 & XA & XB & XT { xxpermdiOp(XA,XB,XT); } + +define pcodeop xxmrghwOp; +# ISA-cmt: xxmrghw - VSX Merge High Word +# ISA-info: xxmrghw - Form "XX3" Page 499 Category "VSX" +# binutils: vsx.d: 230: f1 12 e0 97 xxmrghw vs40,vs50,vs60 +:xxmrghw XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=18 & XA & XB & XT { xxmrghwOp(XA,XB,XT); } + +define pcodeop xsadddpOp; +# ISA-cmt: xsadddp - VSX Scalar Add Double-Precision +# ISA-info: xsadddp - Form "XX3" Page 342 Category "VSX" +# binutils: vsx.d: 20: f1 12 e1 07 xsadddp vs40,vs50,vs60 +:xsadddp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=32 & XA & XB & XT +{ + src1:8 = XA:8; + src2:8 = XB:8; + local src = src1 f+ src2; + XT[0,64] = src; +} + +define pcodeop xsmaddadpOp; +# ISA-cmt: xsmaddadp - VSX Scalar Multiply-Add Type-A Double-Precision +# ISA-info: xsmaddadp - Form "XX3" Page 365 Category "VSX" +# binutils: vsx.d: 54: f1 12 e1 0f xsmaddadp vs40,vs50,vs60 +:xsmaddadp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=33 & XA & XB & XT { xsmaddadpOp(XA,XB,XT); } + +define pcodeop xscmpudpOp; +# ISA-cmt: xscmpudp - VSX Scalar Compare Unordered Double-Precision +# ISA-info: xscmpudp - Form "XX3" Page 349 Category "VSX" +# binutils: vsx.d: 28: f0 92 e1 1e xscmpudp cr1,vs50,vs60 +:xscmpudp CRFD,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=35 & CRFD & BITS_21_22=0 & BIT_0=0 & XA & XB { xscmpudpOp(CRFD,XA,XB); } + +define pcodeop xssubdpOp; +# ISA-cmt: xssubdp - VSX Scalar Subtract Double-Precision +# ISA-info: xssubdp - Form "XX3" Page 393 Category "VSX" +# binutils: vsx.d: a8: f1 12 e1 47 xssubdp vs40,vs50,vs60 +:xssubdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=40 & XA & XB & XT { xssubdpOp(XA,XB,XT); } + +define pcodeop xsmaddmdpOp; +# ISA-cmt: xsmaddmdp - VSX Scalar Multiply-Add Type-M Double-Precision +# ISA-info: xsmaddmdp - Form "XX3" Page 365 Category "VSX" +# binutils: vsx.d: 58: f1 12 e1 4f xsmaddmdp vs40,vs50,vs60 +:xsmaddmdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=41 & XA & XB & XT { xsmaddmdpOp(XA,XB,XT); } + +define pcodeop xscmpodpOp; +# ISA-cmt: xscmpodp - VSX Scalar Compare Ordered Double-Precision +# ISA-info: xscmpodp - Form "XX3" Page 347 Category "VSX" +# binutils: vsx.d: 24: f0 92 e1 5e xscmpodp cr1,vs50,vs60 +:xscmpodp CRFD,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=43 & CRFD & BIT_0=0 & BITS_21_22=0 & XA & XB { xscmpodpOp(CRFD,XA,XB); } + +define pcodeop xsmuldpOp; +# ISA-cmt: xsmuldp - VSX Scalar Multiply Double-Precision +# ISA-info: xsmuldp - Form "XX3" Page 375 Category "VSX" +# binutils: vsx.d: 6c: f1 12 e1 87 xsmuldp vs40,vs50,vs60 +:xsmuldp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=48 & XA & XB & XT { xsmuldpOp(XA,XB,XT); } + +define pcodeop xsmsubadpOp; +# ISA-cmt: xsmsubadp - VSX Scalar Multiply-Subtract Type-A Double-Precision +# ISA-info: xsmsubadp - Form "XX3" Page 372 Category "VSX" +# binutils: vsx.d: 64: f1 12 e1 8f xsmsubadp vs40,vs50,vs60 +:xsmsubadp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=49 & XA & XB & XT { xsmsubadpOp(XA,XB,XT); } + +define pcodeop xxmrglwOp; +# ISA-cmt: xxmrglw - VSX Merge Low Word +# ISA-info: xxmrglw - Form "XX3" Page 499 Category "VSX" +# binutils: vsx.d: 234: f1 12 e1 97 xxmrglw vs40,vs50,vs60 +:xxmrglw XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=50 & XA & XB & XT { xxmrglwOp(XA,XB,XT); } + +define pcodeop xsdivdpOp; +# ISA-cmt: xsdivdp - VSX Scalar Divide Double-Precision +# ISA-info: xsdivdp - Form "XX3" Page 363 Category "VSX" +# binutils: vsx.d: 50: f1 12 e1 c7 xsdivdp vs40,vs50,vs60 +:xsdivdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=56 & XA & XB & XT { xsdivdpOp(XA,XB,XT); } + +define pcodeop xsmsubmdpOp; +# ISA-cmt: xsmsubmdp - VSX Scalar Multiply-Subtract Type-M Double-Precision +# ISA-info: xsmsubmdp - Form "XX3" Page 372 Category "VSX" +# binutils: vsx.d: 68: f1 12 e1 cf xsmsubmdp vs40,vs50,vs60 +:xsmsubmdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=57 & XA & XB & XT { xsmsubmdpOp(XA,XB,XT); } + +define pcodeop xstdivdpOp; +# ISA-cmt: xstdivdp - VSX Scalar Test for software Divide Double-Precision +# ISA-info: xstdivdp - Form "XX3" Page 395 Category "VSX" +# binutils: vsx.d: ac: f0 92 e1 ee xstdivdp cr1,vs50,vs60 +:xstdivdp CRFD,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=61 & CRFD & BIT_0=0 & BITS_21_22=0 & XA & XB { xstdivdpOp(CRFD,XA,XB); } + +define pcodeop xvaddspOp; +# ISA-cmt: xvaddsp - VSX Vector Add Single-Precision +# ISA-info: xvaddsp - Form "XX3" Page 402 Category "VSX" +# binutils: vsx.d: c0: f1 12 e2 07 xvaddsp vs40,vs50,vs60 +:xvaddsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=64 & XA & XB & XT { xvaddspOp(XA,XB,XT); } + +define pcodeop xvmaddaspOp; +# ISA-cmt: xvmaddasp - VSX Vector Multiply-Add Type-A Single-Precision +# ISA-info: xvmaddasp - Form "XX3" Page 437 Category "VSX" +# binutils: vsx.d: 164: f1 12 e2 0f xvmaddasp vs40,vs50,vs60 +:xvmaddasp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=65 & XA & XB & XT { xvmaddaspOp(XA,XB,XT); } + +define pcodeop xvcmpeqspOp; +# ISA-cmt: xvcmpeqsp - VSX Vector Compare Equal To Single-Precision +# ISA-info: xvcmpeqsp - Form "XX3" Page 405 Category "VSX" +# binutils: vsx.d: cc: f1 12 e2 1f xvcmpeqsp vs40,vs50,vs60 +:xvcmpeqsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=67 & BIT_10=0 & XA & XB & XT { xvcmpeqspOp(XA,XB,XT); } + +define pcodeop xvcmpeqspDotOp; +# ISA-cmt: xvcmpeqsp. - VSX Vector Compare Equal To Single-Precision & Record +# ISA-info: xvcmpeqsp. - Form "XX3" Page 405 Category "VSX" +# binutils: mytest.d: 1b8: f0 43 26 18 xvcmpeqsp. vs2,vs3,vs4 +:xvcmpeqsp. XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=67 & BIT_10=1 & XA & XB & XT { xvcmpeqspDotOp(XA,XB,XT); } + +define pcodeop xvsubspOp; +# ISA-cmt: xvsubsp - VSX Vector Subtract Single-Precision +# ISA-info: xvsubsp - Form "XX3" Page 491 Category "VSX" +# binutils: vsx.d: 208: f1 12 e2 47 xvsubsp vs40,vs50,vs60 +:xvsubsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=72 & XA & XB & XT { xvsubspOp(XA,XB,XT); } + +define pcodeop xscvdpuxwsOp; +# ISA-cmt: xscvdpuxws - VSX Scalar truncate Double-Precision to integer and Convert to Unsigned Fixed-Point Word format with Saturate +# ISA-info: xscvdpuxws - Form "XX2" Page 359 Category "VSX" +# binutils: vsx.d: 40: f1 00 e1 23 xscvdpuxws vs40,vs60 +:xscvdpuxws XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=72 & BITS_16_20=0 & XB & XT { xscvdpuxwsOp(XB,XT); } + +define pcodeop xvmaddmspOp; +# ISA-cmt: xvmaddmsp - VSX Vector Multiply-Add Type-M Single-Precision +# ISA-info: xvmaddmsp - Form "XX3" Page 440 Category "VSX" +# binutils: vsx.d: 168: f1 12 e2 4f xvmaddmsp vs40,vs50,vs60 +:xvmaddmsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=73 & XA & XB & XT { xvmaddmspOp(XA,XB,XT); } + +define pcodeop xsrdpiOp; +# ISA-cmt: xsrdpi - VSX Scalar Round to Double-Precision Integer +# ISA-info: xsrdpi - Form "XX2" Page 386 Category "VSX" +# binutils: vsx.d: 88: f1 00 e1 27 xsrdpi vs40,vs60 +:xsrdpi XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=73 & BITS_16_20=0 & XB & XT { xsrdpiOp(XB,XT); } + +define pcodeop xsrsqrtedpOp; +# ISA-cmt: xsrsqrtedp - VSX Scalar Reciprocal Square Root Estimate Double-Precision +# ISA-info: xsrsqrtedp - Form "XX2" Page 391 Category "VSX" +# binutils: vsx.d: a0: f1 00 e1 2b xsrsqrtedp vs40,vs60 +:xsrsqrtedp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=74 & BITS_16_20=0 & XB & XT { xsrsqrtedpOp(XB,XT); } + +define pcodeop xssqrtdpOp; +# ISA-cmt: xssqrtdp - VSX Scalar Square Root Double-Precision +# ISA-info: xssqrtdp - Form "XX2" Page 392 Category "VSX" +# binutils: vsx.d: a4: f1 00 e1 2f xssqrtdp vs40,vs60 +:xssqrtdp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=75 & BITS_16_20=0 & XB & XT { xssqrtdpOp(XB,XT); } + +define pcodeop xvcmpgtspOp; +# ISA-cmt: xvcmpgtsp - VSX Vector Compare Greater Than Single-Precision +# ISA-info: xvcmpgtsp - Form "XX3" Page 409 Category "VSX" +# binutils: vsx.d: ec: f1 12 e2 5f xvcmpgtsp vs40,vs50,vs60 +:xvcmpgtsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=75 & BIT_10=0 & XA & XB & XT { xvcmpgtspOp(XA,XB,XT); } + +define pcodeop xvcmpgtspDotOp; +# ISA-cmt: xvcmpgtsp. - VSX Vector Compare Greater Than Single-Precision & Record +# ISA-info: xvcmpgtsp. - Form "XX3" Page 409 Category "VSX" +# binutils: mytest.d: 1bc: f0 43 26 58 xvcmpgtsp. vs2,vs3,vs4 +:xvcmpgtsp. XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=75 & BIT_10=1 & XA & XB & XT { xvcmpgtspDotOp(XA,XB,XT); } + +define pcodeop xvmulspOp; +# ISA-cmt: xvmulsp - VSX Vector Multiply Single-Precision +# ISA-info: xvmulsp - Form "XX3" Page 459 Category "VSX" +# binutils: vsx.d: 190: f1 12 e2 87 xvmulsp vs40,vs50,vs60 +:xvmulsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=80 & XA & XB & XT { xvmulspOp(XA,XB,XT); } + +define pcodeop xvmsubaspOp; +# ISA-cmt: xvmsubasp - VSX Vector Multiply-Subtract Type-A Single-Precision +# ISA-info: xvmsubasp - Form "XX3" Page 451 Category "VSX" +# binutils: vsx.d: 184: f1 12 e2 8f xvmsubasp vs40,vs50,vs60 +:xvmsubasp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=81 & XA & XB & XT { xvmsubaspOp(XA,XB,XT); } + +define pcodeop xvcmpgespOp; +# ISA-cmt: xvcmpgesp - VSX Vector Compare Greater Than or Equal To Single-Precision +# ISA-info: xvcmpgesp - Form "XX3" Page 407 Category "VSX" +# binutils: vsx.d: dc: f1 12 e2 9f xvcmpgesp vs40,vs50,vs60 +:xvcmpgesp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=83 & BIT_10=0 & XA & XB & XT { xvcmpgespOp(XA,XB,XT); } + +define pcodeop xvcmpgespDotOp; +# ISA-cmt: xvcmpgesp. - VSX Vector Compare Greater Than or Equal To Single-Precision & Record +# ISA-info: xvcmpgesp. - Form "XX3" Page 407 Category "VSX" +# binutils: mytest.d: 1c0: f0 43 26 98 xvcmpgesp. vs2,vs3,vs4 +:xvcmpgesp. XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=83 & BIT_10=1 & XA & XB & XT { xvcmpgespDotOp(XA,XB,XT); } + +define pcodeop xvdivspOp; +# ISA-cmt: xvdivsp - VSX Vector Divide Single-Precision +# ISA-info: xvdivsp - Form "XX3" Page 435 Category "VSX" +# binutils: vsx.d: 158: f1 12 e2 c7 xvdivsp vs40,vs50,vs60 +:xvdivsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=88 & XA & XB & XT { xvdivspOp(XA,XB,XT); } + +define pcodeop xscvdpsxwsOp; +# ISA-cmt: xscvdpsxws - VSX Scalar truncate Double-Precision to integer and Convert to Signed Fixed-Point Word format with Saturate +# ISA-info: xscvdpsxws - Form "XX2" Page 355 Category "VSX" +# binutils: vsx.d: 38: f1 00 e1 63 xscvdpsxws vs40,vs60 +:xscvdpsxws XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=88 & BITS_16_20=0 & XB & XT { xscvdpsxwsOp(XB,XT); } + +define pcodeop xvmsubmspOp; +# ISA-cmt: xvmsubmsp - VSX Vector Multiply-Subtract Type-M Single-Precision +# ISA-info: xvmsubmsp - Form "XX3" Page 454 Category "VSX" +# binutils: vsx.d: 188: f1 12 e2 cf xvmsubmsp vs40,vs50,vs60 +:xvmsubmsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=89 & XA & XB & XT { xvmsubmspOp(XA,XB,XT); } + +define pcodeop xsrdpizOp; +# ISA-cmt: xsrdpiz - VSX Scalar Round to Double-Precision Integer toward Zero +# ISA-info: xsrdpiz - Form "XX2" Page 389 Category "VSX" +# binutils: vsx.d: 98: f1 00 e1 67 xsrdpiz vs40,vs60 +:xsrdpiz XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=89 & BITS_16_20=0 & XB & XT { xsrdpizOp(XB,XT); } + +define pcodeop xsredpOp; +# ISA-cmt: xsredp - VSX Scalar Reciprocal Estimate Double-Precision +# ISA-info: xsredp - Form "XX2" Page 390 Category "VSX" +# binutils: vsx.d: 9c: f1 00 e1 6b xsredp vs40,vs60 +:xsredp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=90 & BITS_16_20=0 & XB & XT { xsredpOp(XB,XT); } + +define pcodeop xvtdivspOp; +# ISA-cmt: xvtdivsp - VSX Vector Test for software Divide Single-Precision +# ISA-info: xvtdivsp - Form "XX3" Page 494 Category "VSX" +# binutils: vsx.d: 210: f0 92 e2 ee xvtdivsp cr1,vs50,vs60 +:xvtdivsp CRFD,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=93 & CRFD & BIT_0=0 & BITS_21_22=0 & XA & XB { xvtdivspOp(CRFD,XA,XB); } + +define pcodeop xvadddpOp; +# ISA-cmt: xvadddp - VSX Vector Add Double-Precision +# ISA-info: xvadddp - Form "XX3" Page 398 Category "VSX" +# binutils: vsx.d: bc: f1 12 e3 07 xvadddp vs40,vs50,vs60 +:xvadddp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=96 & XA & XB & XT { xvadddpOp(XA,XB,XT); } + +define pcodeop xvmaddadpOp; +# ISA-cmt: xvmaddadp - VSX Vector Multiply-Add Type-A Double-Precision +# ISA-info: xvmaddadp - Form "XX3" Page 437 Category "VSX" +# binutils: vsx.d: 15c: f1 12 e3 0f xvmaddadp vs40,vs50,vs60 +:xvmaddadp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=97 & XA & XB & XT { xvmaddadpOp(XA,XB,XT); } + +define pcodeop xvcmpeqdpOp; +# ISA-cmt: xvcmpeqdp - VSX Vector Compare Equal To Double-Precision +# ISA-info: xvcmpeqdp - Form "XX3" Page 404 Category "VSX" +# binutils: vsx.d: c4: f1 12 e3 1f xvcmpeqdp vs40,vs50,vs60 +:xvcmpeqdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=99 & BIT_10=0 & XA & XB & XT { xvcmpeqdpOp(XA,XB,XT); } + +define pcodeop xvcmpeqdpDotOp; +# ISA-cmt: xvcmpeqdp. - VSX Vector Compare Equal To Double-Precision & Record +# ISA-info: xvcmpeqdp. - Form "XX3" Page 404 Category "VSX" +# binutils: mytest.d: 1c4: f0 43 27 18 xvcmpeqdp. vs2,vs3,vs4 +:xvcmpeqdp. XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=99 & BIT_10=1 & XA & XB & XT { xvcmpeqdpDotOp(XA,XB,XT); } + +define pcodeop xvsubdpOp; +# ISA-cmt: xvsubdp - VSX Vector Subtract Double-Precision +# ISA-info: xvsubdp - Form "XX3" Page 489 Category "VSX" +# binutils: vsx.d: 204: f1 12 e3 47 xvsubdp vs40,vs50,vs60 +:xvsubdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=104 & XA & XB & XT { xvsubdpOp(XA,XB,XT); } + +define pcodeop xvmaddmdpOp; +# ISA-cmt: xvmaddmdp - VSX Vector Multiply-Add Type-M Double-Precision +# ISA-info: xvmaddmdp - Form "XX3" Page 440 Category "VSX" +# binutils: vsx.d: 160: f1 12 e3 4f xvmaddmdp vs40,vs50,vs60 +:xvmaddmdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=105 & XA & XB & XT { xvmaddmdpOp(XA,XB,XT); } + +define pcodeop xsrdpipOp; +# ISA-cmt: xsrdpip - VSX Scalar Round to Double-Precision Integer toward +Infinity +# ISA-info: xsrdpip - Form "XX2" Page 388 Category "VSX" +# binutils: vsx.d: 94: f1 00 e1 a7 xsrdpip vs40,vs60 +:xsrdpip XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=105 & BITS_16_20=0 & XB & XT { xsrdpipOp(XB,XT); } + +define pcodeop xstsqrtdpOp; +# ISA-cmt: xstsqrtdp - VSX Scalar Test for software Square Root Double-Precision +# ISA-info: xstsqrtdp - Form "XX2" Page 396 Category "VSX" +# binutils: vsx.d: b0: f0 80 e1 aa xstsqrtdp cr1,vs60 +:xstsqrtdp CRFD,XB is $(NOTVLE) & OP=60 & XOP_2_10=106 & CRFD & BIT_0=0 & BITS_21_22=0 & BITS_16_20=0 & XB { xstsqrtdpOp(CRFD,XB); } + +define pcodeop xsrdpicOp; +# ISA-cmt: xsrdpic - VSX Scalar Round to Double-Precision Integer using Current rounding mode +# ISA-info: xsrdpic - Form "XX2" Page 387 Category "VSX" +# binutils: vsx.d: 8c: f1 00 e1 af xsrdpic vs40,vs60 +:xsrdpic XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=107 & BITS_16_20=0 & XB & XT { xsrdpicOp(XB,XT); } + +define pcodeop xvcmpgtdpOp; +# ISA-cmt: xvcmpgtdp - VSX Vector Compare Greater Than Double-Precision +# ISA-info: xvcmpgtdp - Form "XX3" Page 408 Category "VSX" +# binutils: vsx.d: e4: f1 12 e3 5f xvcmpgtdp vs40,vs50,vs60 +:xvcmpgtdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=107 & BIT_10=0 & XA & XB & XT { xvcmpgtdpOp(XA,XB,XT); } + +define pcodeop xvcmpgtdpDotOp; +# ISA-cmt: xvcmpgtdp. - VSX Vector Compare Greater Than Double-Precision & Record +# ISA-info: xvcmpgtdp. - Form "XX3" Page 408 Category "VSX" +# binutils: mytest.d: 1c8: f0 43 27 58 xvcmpgtdp. vs2,vs3,vs4 +:xvcmpgtdp. XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=107 & BIT_10=1 & XA & XB & XT { xvcmpgtdpDotOp(XA,XB,XT); } + +define pcodeop xvmuldpOp; +# ISA-cmt: xvmuldp - VSX Vector Multiply Double-Precision +# ISA-info: xvmuldp - Form "XX3" Page 457 Category "VSX" +# binutils: vsx.d: 18c: f1 12 e3 87 xvmuldp vs40,vs50,vs60 +:xvmuldp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=112 & XA & XB & XT { xvmuldpOp(XA,XB,XT); } + +define pcodeop xvmsubadpOp; +# ISA-cmt: xvmsubadp - VSX Vector Multiply-Subtract Type-A Double-Precision +# ISA-info: xvmsubadp - Form "XX3" Page 451 Category "VSX" +# binutils: vsx.d: 17c: f1 12 e3 8f xvmsubadp vs40,vs50,vs60 +:xvmsubadp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=113 & XA & XB & XT { xvmsubadpOp(XA,XB,XT); } + +define pcodeop xvcmpgedpOp; +# ISA-cmt: xvcmpgedp - VSX Vector Compare Greater Than or Equal To Double-Precision +# ISA-info: xvcmpgedp - Form "XX3" Page 406 Category "VSX" +# binutils: vsx.d: d4: f1 12 e3 9f xvcmpgedp vs40,vs50,vs60 +:xvcmpgedp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=115 & BIT_10=0 & XA & XB & XT { xvcmpgedpOp(XA,XB,XT); } + +define pcodeop xvcmpgedpDotOp; +# ISA-cmt: xvcmpgedp. - VSX Vector Compare Greater Than or Equal To Double-Precision & Record +# ISA-info: xvcmpgedp. - Form "XX3" Page 406 Category "VSX" +# binutils: mytest.d: 1cc: f0 43 27 98 xvcmpgedp. vs2,vs3,vs4 +:xvcmpgedp. XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=115 & BIT_10=1 & XA & XB & XT { xvcmpgedpDotOp(XA,XB,XT); } + +define pcodeop xvdivdpOp; +# ISA-cmt: xvdivdp - VSX Vector Divide Double-Precision +# ISA-info: xvdivdp - Form "XX3" Page 433 Category "VSX" +# binutils: vsx.d: 154: f1 12 e3 c7 xvdivdp vs40,vs50,vs60 +:xvdivdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=120 & XA & XB & XT { xvdivdpOp(XA,XB,XT); } + +define pcodeop xvmsubmdpOp; +# ISA-cmt: xvmsubmdp - VSX Vector Multiply-Subtract Type-M Double-Precision +# ISA-info: xvmsubmdp - Form "XX3" Page 454 Category "VSX" +# binutils: vsx.d: 180: f1 12 e3 cf xvmsubmdp vs40,vs50,vs60 +:xvmsubmdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=121 & XA & XB & XT { xvmsubmdpOp(XA,XB,XT); } + +define pcodeop xsrdpimOp; +# ISA-cmt: xsrdpim - VSX Scalar Round to Double-Precision Integer toward -Infinity +# ISA-info: xsrdpim - Form "XX2" Page 388 Category "VSX" +# binutils: vsx.d: 90: f1 00 e1 e7 xsrdpim vs40,vs60 +:xsrdpim XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=121 & BITS_16_20=0 & XB & XT { xsrdpimOp(XB,XT); } + +define pcodeop xvtdivdpOp; +# ISA-cmt: xvtdivdp - VSX Vector Test for software Divide Double-Precision +# ISA-info: xvtdivdp - Form "XX3" Page 493 Category "VSX" +# binutils: vsx.d: 20c: f0 92 e3 ee xvtdivdp cr1,vs50,vs60 +:xvtdivdp CRFD,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=125 & CRFD & BIT_0=0 & BITS_21_22=0 & XA & XB { xvtdivdpOp(CRFD,XA,XB); } + +# ISA-cmt: xxland - VSX Logical AND +# ISA-info: xxland - Form "XX3" Page 496 Category "VSX" +# binutils: vsx.d: 21c: f1 12 e4 17 xxland vs40,vs50,vs60 +:xxland XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=130 & XA & XB & XT { + XT = XA & XB; +} + +define pcodeop xvcvspuxwsOp; +# ISA-cmt: xvcvspuxws - VSX Vector truncate Single-Precision to integer and Convert to Unsigned Fixed-Point Word Saturate +# ISA-info: xvcvspuxws - Form "XX2" Page 427 Category "VSX" +# binutils: vsx.d: 130: f1 00 e2 23 xvcvspuxws vs40,vs60 +:xvcvspuxws XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=136 & BI_BITS=0 & XB & XT { xvcvspuxwsOp(XB,XT); } + +define pcodeop xvrspiOp; +# ISA-cmt: xvrspi - VSX Vector Round to Single-Precision Integer +# ISA-info: xvrspi - Form "XX2" Page 482 Category "VSX" +# binutils: vsx.d: 1e0: f1 00 e2 27 xvrspi vs40,vs60 +:xvrspi XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=137 & BI_BITS=0 & XB & XT { xvrspiOp(XB,XT); } + +# ISA-cmt: xxlandc - VSX Logical AND with Complement +# ISA-info: xxlandc - Form "XX3" Page 496 Category "VSX" +# binutils: vsx.d: 220: f1 12 e4 57 xxlandc vs40,vs50,vs60 +:xxlandc XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=138 & XA & XB & XT { + XT = XA & (~XB); +} + +define pcodeop xvrsqrtespOp; +# ISA-cmt: xvrsqrtesp - VSX Vector Reciprocal Square Root Estimate Single-Precision +# ISA-info: xvrsqrtesp - Form "XX2" Page 486 Category "VSX" +# binutils: vsx.d: 1f8: f1 00 e2 2b xvrsqrtesp vs40,vs60 +:xvrsqrtesp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=138 & BI_BITS=0 & XB & XT { xvrsqrtespOp(XB,XT); } + +define pcodeop xvsqrtspOp; +# ISA-cmt: xvsqrtsp - VSX Vector Square Root Single-Precision +# ISA-info: xvsqrtsp - Form "XX2" Page 488 Category "VSX" +# binutils: vsx.d: 200: f1 00 e2 2f xvsqrtsp vs40,vs60 +:xvsqrtsp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=139 & BI_BITS=0 & XB & XT { xvsqrtspOp(XB,XT); } + +# ISA-cmt: xxlor - VSX Logical OR +# ISA-info: xxlor - Form "XX3" Page 497 Category "VSX" +# binutils: vsx.d: 228: f1 12 e4 97 xxlor vs40,vs50,vs60 +:xxlor XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=146 & XA & XB & XT { + XT = XA | XB; +} + +define pcodeop xvcvspsxwsOp; +# ISA-cmt: xvcvspsxws - VSX Vector truncate Single-Precision to integer and Convert to Signed Fixed-Point Word format with Saturate +# ISA-info: xvcvspsxws - Form "XX2" Page 423 Category "VSX" +# binutils: vsx.d: 128: f1 00 e2 63 xvcvspsxws vs40,vs60 +:xvcvspsxws XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=152 & BI_BITS=0 & XB & XT { xvcvspsxwsOp(XB,XT); } + +define pcodeop xvrspizOp; +# ISA-cmt: xvrspiz - VSX Vector Round to Single-Precision Integer toward Zero +# ISA-info: xvrspiz - Form "XX2" Page 484 Category "VSX" +# binutils: vsx.d: 1f0: f1 00 e2 67 xvrspiz vs40,vs60 +:xvrspiz XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=153 & BI_BITS=0 & XB & XT { xvrspizOp(XB,XT); } + +# ISA-cmt: xxlxor - VSX Logical XOR +# ISA-info: xxlxor - Form "XX3" Page 498 Category "VSX" +# binutils: vsx.d: 22c: f1 12 e4 d7 xxlxor vs40,vs50,vs60 +:xxlxor XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=154 & XA & XB & XT { + XT = XA ^ XB; +} + +define pcodeop xvrespOp; +# ISA-cmt: xvresp - VSX Vector Reciprocal Estimate Single-Precision +# ISA-info: xvresp - Form "XX2" Page 481 Category "VSX" +# binutils: vsx.d: 1dc: f1 00 e2 6b xvresp vs40,vs60 +:xvresp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=154 & BI_BITS=0 & XB & XT { xvrespOp(XB,XT); } + +define pcodeop xsmaxdpOp; +# ISA-cmt: xsmaxdp - VSX Scalar Maximum Double-Precision +# ISA-info: xsmaxdp - Form "XX3" Page 368 Category "VSX" +# binutils: vsx.d: 5c: f1 12 e5 07 xsmaxdp vs40,vs50,vs60 +:xsmaxdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=160 & XA & XB & XT { xsmaxdpOp(XA,XB,XT); } + +define pcodeop xsnmaddadpOp; +# ISA-cmt: xsnmaddadp - VSX Scalar Negative Multiply-Add Type-A Double-Precision +# ISA-info: xsnmaddadp - Form "XX3" Page 378 Category "VSX" +# binutils: vsx.d: 78: f1 12 e5 0f xsnmaddadp vs40,vs50,vs60 +:xsnmaddadp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=161 & XA & XB & XT { xsnmaddadpOp(XA,XB); } + +define pcodeop xxlnorOp; +# ISA-cmt: xxlnor - VSX Logical NOR +# ISA-info: xxlnor - Form "XX3" Page 497 Category "VSX" +# binutils: vsx.d: 224: f1 12 e5 17 xxlnor vs40,vs50,vs60 +:xxlnor XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=162 & XA & XB & XT { + XT = ~(XA | XB); +} + +define pcodeop xxspltwOp; +# ISA-cmt: xxspltw - VSX Splat Word +# ISA-info: xxspltw - Form "XX2" Page 501 Category "VSX" +# binutils: vsx.d: 274: f1 02 e2 93 xxspltw vs40,vs60,2 +:xxspltw XT,XB,UIM is $(NOTVLE) & OP=60 & XOP_2_10=164 & BITS_18_20=0 & UIM & XB & XT { xxspltwOp(XB,XT); } + +define pcodeop xsmindpOp; +# ISA-cmt: xsmindp - VSX Scalar Minimum Double-Precision +# ISA-info: xsmindp - Form "XX3" Page 370 Category "VSX" +# binutils: vsx.d: 60: f1 12 e5 47 xsmindp vs40,vs50,vs60 +:xsmindp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=168 & XA & XB & XT { xsmindpOp(XA,XB,XT); } + +define pcodeop xvcvuxwspOp; +# ISA-cmt: xvcvuxwsp - VSX Vector Convert and round Unsigned Fixed-Point Word to Single-Precision format +# ISA-info: xvcvuxwsp - Form "XX2" Page 432 Category "VSX" +# binutils: vsx.d: 150: f1 00 e2 a3 xvcvuxwsp vs40,vs60 +:xvcvuxwsp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=168 & BI_BITS=0 & XB & XT { xvcvuxwspOp(XB,XT); } + +define pcodeop xsnmaddmdpOp; +# ISA-cmt: xsnmaddmdp - VSX Scalar Negative Multiply-Add Type-M Double-Precision +# ISA-info: xsnmaddmdp - Form "XX3" Page 378 Category "VSX" +# binutils: vsx.d: 7c: f1 12 e5 4f xsnmaddmdp vs40,vs50,vs60 +:xsnmaddmdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=169 & XA & XB & XT { xsnmaddmdpOp(XA,XB,XT); } + +define pcodeop xvrspipOp; +# ISA-cmt: xvrspip - VSX Vector Round to Single-Precision Integer toward +Infinity +# ISA-info: xvrspip - Form "XX2" Page 483 Category "VSX" +# binutils: vsx.d: 1ec: f1 00 e2 a7 xvrspip vs40,vs60 +:xvrspip XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=169 & BI_BITS=0 & XB & XT { xvrspipOp(XB,XT); } + +define pcodeop xvtsqrtspOp; +# ISA-cmt: xvtsqrtsp - VSX Vector Test for software Square Root Single-Precision +# ISA-info: xvtsqrtsp - Form "XX2" Page 495 Category "VSX" +# binutils: vsx.d: 218: f0 80 e2 aa xvtsqrtsp cr1,vs60 +:xvtsqrtsp CRFD,XB is $(NOTVLE) & OP=60 & XOP_2_10=170 & CRFD & BITS_21_22=0 & BITS_16_20=0 & BIT_0=0 & XB { xvtsqrtspOp(CRFD,XB); } + +define pcodeop xvrspicOp; +# ISA-cmt: xvrspic - VSX Vector Round to Single-Precision Integer using Current rounding mode +# ISA-info: xvrspic - Form "XX2" Page 482 Category "VSX" +# binutils: vsx.d: 1e4: f1 00 e2 af xvrspic vs40,vs60 +:xvrspic XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=171 & BITS_16_20=0 & XB & XT { xvrspicOp(XB,XT); } + +define pcodeop xscpsgndpOp; +# ISA-cmt: xscpsgndp - VSX Scalar Copy Sign Double-Precision +# ISA-info: xscpsgndp - Form "XX3" Page 351 Category "VSX" +# binutils: vsx.d: 2c: f1 12 e5 87 xscpsgndp vs40,vs50,vs60 +:xscpsgndp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=176 & XA & XB & XT { xscpsgndpOp(XA,XB,XT); } + +define pcodeop xsnmsubadpOp; +# ISA-cmt: xsnmsubadp - VSX Scalar Negative Multiply-Subtract Type-A Double-Precision +# ISA-info: xsnmsubadp - Form "XX3" Page 383 Category "VSX" +# binutils: vsx.d: 80: f1 12 e5 8f xsnmsubadp vs40,vs50,vs60 +:xsnmsubadp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=177 & XA & XB & XT { xsnmsubadpOp(XA,XB,XT); } + +define pcodeop xvcvsxwspOp; +# ISA-cmt: xvcvsxwsp - VSX Vector Convert and round Signed Fixed-Point Word to Single-Precision format +# ISA-info: xvcvsxwsp - Form "XX2" Page 430 Category "VSX" +# binutils: vsx.d: 140: f1 00 e2 e3 xvcvsxwsp vs40,vs60 +:xvcvsxwsp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=184 & BITS_16_20=0 & XB & XT { xvcvsxwspOp(XB,XT); } + +define pcodeop xsnmsubmdpOp; +# ISA-cmt: xsnmsubmdp - VSX Scalar Negative Multiply-Subtract Type-M Double-Precision +# ISA-info: xsnmsubmdp - Form "XX3" Page 383 Category "VSX" +# binutils: vsx.d: 84: f1 12 e5 cf xsnmsubmdp vs40,vs50,vs60 +:xsnmsubmdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=185 & XA & XB & XT { xsnmsubmdpOp(XA,XB,XT); } + +define pcodeop xvrspimOp; +# ISA-cmt: xvrspim - VSX Vector Round to Single-Precision Integer toward -Infinity +# ISA-info: xvrspim - Form "XX2" Page 483 Category "VSX" +# binutils: vsx.d: 1e8: f1 00 e2 e7 xvrspim vs40,vs60 +:xvrspim XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=185 & BITS_16_20=0 & XB & XT { xvrspimOp(XB,XT); } + +define pcodeop xvmaxspOp; +# ISA-cmt: xvmaxsp - VSX Vector Maximum Single-Precision +# ISA-info: xvmaxsp - Form "XX3" Page 445 Category "VSX" +# binutils: vsx.d: 170: f1 12 e6 07 xvmaxsp vs40,vs50,vs60 +:xvmaxsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=192 & XA & XB & XT { xvmaxspOp(XA,XB,XT); } + +define pcodeop xvnmaddaspOp; +# ISA-cmt: xvnmaddasp - VSX Vector Negative Multiply-Add Type-A Single-Precision +# ISA-info: xvnmaddasp - Form "XX3" Page 463 Category "VSX" +# binutils: vsx.d: 1ac: f1 12 e6 0f xvnmaddasp vs40,vs50,vs60 +:xvnmaddasp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=193 & XA & XB & XT { xvnmaddaspOp(XA,XB,XT); } + +define pcodeop xvminspOp; +# ISA-cmt: xvminsp - VSX Vector Minimum Single-Precision +# ISA-info: xvminsp - Form "XX3" Page 449 Category "VSX" +# binutils: vsx.d: 178: f1 12 e6 47 xvminsp vs40,vs50,vs60 +:xvminsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=200 & XA & XB & XT { xvminspOp(XA,XB,XT); } + +define pcodeop xvcvdpuxwsOp; +# ISA-cmt: xvcvdpuxws - VSX Vector truncate Double-Precision to integer and Convert to Unsigned Fixed-Point Word format with Saturate +# ISA-info: xvcvdpuxws - Form "XX2" Page 418 Category "VSX" +# binutils: vsx.d: 11c: f1 00 e3 23 xvcvdpuxws vs40,vs60 +:xvcvdpuxws XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=200 & BITS_16_20=0 & XB & XT { xvcvdpuxwsOp(XB,XT); } + +define pcodeop xvnmaddmspOp; +# ISA-cmt: xvnmaddmsp - VSX Vector Negative Multiply-Add Type-M Single-Precision +# ISA-info: xvnmaddmsp - Form "XX3" Page 468 Category "VSX" +# binutils: vsx.d: 1b0: f1 12 e6 4f xvnmaddmsp vs40,vs50,vs60 +:xvnmaddmsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=201 & XA & XB & XT { xvnmaddmspOp(XA,XB,XT); } + +define pcodeop xvrdpiOp; +# ISA-cmt: xvrdpi - VSX Vector Round to Double-Precision Integer +# ISA-info: xvrdpi - Form "XX2" Page 477 Category "VSX" +# binutils: vsx.d: 1c4: f1 00 e3 27 xvrdpi vs40,vs60 +:xvrdpi XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=201 & BITS_16_20=0 & XB & XT { xvrdpiOp(XB,XT); } + +define pcodeop xvrsqrtedpOp; +# ISA-cmt: xvrsqrtedp - VSX Vector Reciprocal Square Root Estimate Double-Precision +# ISA-info: xvrsqrtedp - Form "XX2" Page 485 Category "VSX" +# binutils: vsx.d: 1f4: f1 00 e3 2b xvrsqrtedp vs40,vs60 +:xvrsqrtedp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=202 & BITS_16_20=0 & XB & XT { xvrsqrtedpOp(XB,XT); } + +define pcodeop xvsqrtdpOp; +# ISA-cmt: xvsqrtdp - VSX Vector Square Root Double-Precision +# ISA-info: xvsqrtdp - Form "XX2" Page 487 Category "VSX" +# binutils: vsx.d: 1fc: f1 00 e3 2f xvsqrtdp vs40,vs60 +:xvsqrtdp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=203 & BITS_16_20=0 & XB & XT { xvsqrtdpOp(XB,XT); } + +define pcodeop xvcpsgnspOp; +# ISA-cmt: xvcpsgnsp - VSX Vector Copy Sign Single-Precision +# ISA-info: xvcpsgnsp - Form "XX3" Page 410 Category "VSX" +# binutils: vsx.d: 100: f1 12 e6 87 xvcpsgnsp vs40,vs50,vs60 +:xvcpsgnsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=208 & XA & XB & XT { xvcpsgnspOp(XA,XB,XT); } + +define pcodeop xvnmsubaspOp; +# ISA-cmt: xvnmsubasp - VSX Vector Negative Multiply-Subtract Type-A Single-Precision +# ISA-info: xvnmsubasp - Form "XX3" Page 471 Category "VSX" +# binutils: vsx.d: 1bc: f1 12 e6 8f xvnmsubasp vs40,vs50,vs60 +:xvnmsubasp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=209 & XA & XB & XT { xvnmsubaspOp(XA,XB,XT); } + +define pcodeop xvcvdpsxwsOp; +# ISA-cmt: xvcvdpsxws - VSX Vector truncate Double-Precision to integer and Convert to Signed Fixed-Point Word Saturate +# ISA-info: xvcvdpsxws - Form "XX2" Page 414 Category "VSX" +# binutils: vsx.d: 114: f1 00 e3 63 xvcvdpsxws vs40,vs60 +:xvcvdpsxws XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=216 & BITS_16_20=0 & XB & XT { xvcvdpsxwsOp(XB,XT); } + +define pcodeop xvnmsubmspOp; +# ISA-cmt: xvnmsubmsp - VSX Vector Negative Multiply-Subtract Type-M Single-Precision +# ISA-info: xvnmsubmsp - Form "XX3" Page 474 Category "VSX" +# binutils: vsx.d: 1c0: f1 12 e6 cf xvnmsubmsp vs40,vs50,vs60 +:xvnmsubmsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=217 & XA & XB & XT { xvnmsubmspOp(XA,XB,XT); } + +define pcodeop xvrdpizOp; +# ISA-cmt: xvrdpiz - VSX Vector Round to Double-Precision Integer toward Zero +# ISA-info: xvrdpiz - Form "XX2" Page 479 Category "VSX" +# binutils: vsx.d: 1d4: f1 00 e3 67 xvrdpiz vs40,vs60 +:xvrdpiz XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=217 & BITS_16_20=0 & XB & XT { xvrdpizOp(XB,XT); } + +define pcodeop xvredpOp; +# ISA-cmt: xvredp - VSX Vector Reciprocal Estimate Double-Precision +# ISA-info: xvredp - Form "XX2" Page 480 Category "VSX" +# binutils: vsx.d: 1d8: f1 00 e3 6b xvredp vs40,vs60 +:xvredp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=218 & BITS_16_20=0 & XB & XT { xvredpOp(XB,XT); } + +define pcodeop xvmaxdpOp; +# ISA-cmt: xvmaxdp - VSX Vector Maximum Double-Precision +# ISA-info: xvmaxdp - Form "XX3" Page 443 Category "VSX" +# binutils: vsx.d: 16c: f1 12 e7 07 xvmaxdp vs40,vs50,vs60 +:xvmaxdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=224 & XA & XB & XT { xvmaxdpOp(XA,XB,XT); } + +define pcodeop xvnmaddadpOp; +# ISA-cmt: xvnmaddadp - VSX Vector Negative Multiply-Add Type-A Double-Precision +# ISA-info: xvnmaddadp - Form "XX3" Page 463 Category "VSX" +# binutils: vsx.d: 1a4: f1 12 e7 0f xvnmaddadp vs40,vs50,vs60 +:xvnmaddadp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=225 & XA & XB & XT { xvnmaddadpOp(XA,XB,XT); } + +define pcodeop xvmindpOp; +# ISA-cmt: xvmindp - VSX Vector Minimum Double-Precision +# ISA-info: xvmindp - Form "XX3" Page 447 Category "VSX" +# binutils: vsx.d: 174: f1 12 e7 47 xvmindp vs40,vs50,vs60 +:xvmindp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=232 & XA & XB & XT { xvmindpOp(XA,XB,XT); } + +define pcodeop xvnmaddmdpOp; +# ISA-cmt: xvnmaddmdp - VSX Vector Negative Multiply-Add Type-M Double-Precision +# ISA-info: xvnmaddmdp - Form "XX3" Page 468 Category "VSX" +# binutils: vsx.d: 1a8: f1 12 e7 4f xvnmaddmdp vs40,vs50,vs60 +:xvnmaddmdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=233 & XA & XB & XT { xvnmaddmdpOp(XA,XB,XT); } + +define pcodeop xvcvuxwdpOp; +# ISA-cmt: xvcvuxwdp - VSX Vector Convert Unsigned Fixed-Point Word to Double-Precision format +# ISA-info: xvcvuxwdp - Form "XX2" Page 432 Category "VSX" +# binutils: vsx.d: 14c: f1 00 e3 a3 xvcvuxwdp vs40,vs60 +:xvcvuxwdp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=232 & BITS_16_20=0 & XB & XT { xvcvuxwdpOp(XB,XT); } + +define pcodeop xvrdpipOp; +# ISA-cmt: xvrdpip - VSX Vector Round to Double-Precision Integer toward +Infinity +# ISA-info: xvrdpip - Form "XX2" Page 479 Category "VSX" +# binutils: vsx.d: 1d0: f1 00 e3 a7 xvrdpip vs40,vs60 +:xvrdpip XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=233 & BITS_16_20=0 & XB & XT { xvrdpipOp(XB,XT); } + +define pcodeop xvtsqrtdpOp; +# ISA-cmt: xvtsqrtdp - VSX Vector Test for software Square Root Double-Precision +# ISA-info: xvtsqrtdp - Form "XX2" Page 495 Category "VSX" +# binutils: vsx.d: 214: f0 80 e3 aa xvtsqrtdp cr1,vs60 +:xvtsqrtdp CRFD,XB is $(NOTVLE) & OP=60 & XOP_2_10=234 & CRFD & BITS_16_20=0 & BIT_0=0 & BITS_21_22=0 & XB { xvtsqrtdpOp(CRFD,XB); } + +define pcodeop xvrdpicOp; +# ISA-cmt: xvrdpic - VSX Vector Round to Double-Precision Integer using Current rounding mode +# ISA-info: xvrdpic - Form "XX2" Page 478 Category "VSX" +# binutils: vsx.d: 1c8: f1 00 e3 af xvrdpic vs40,vs60 +:xvrdpic XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=235 & BITS_16_20=0 & XB & XT { xvrdpicOp(XB,XT); } + +define pcodeop xvcpsgndpOp; +# ISA-cmt: xvcpsgndp - VSX Vector Copy Sign Double-Precision +# ISA-info: xvcpsgndp - Form "XX3" Page 410 Category "VSX" +# binutils: power7.d: 50: f0 64 2f 80 xvcpsgndp vs3,vs4,vs5 +# binutils: power7.d: 54: f1 6c 6f 87 xvcpsgndp vs43,vs44,vs45 +# binutils: vsx.d: f4: f1 12 e7 87 xvcpsgndp vs40,vs50,vs60 +:xvcpsgndp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=240 & XA & XB & XT { xvcpsgndpOp(XA,XB,XT); } + +define pcodeop xvnmsubadpOp; +# ISA-cmt: xvnmsubadp - VSX Vector Negative Multiply-Subtract Type-A Double-Precision +# ISA-info: xvnmsubadp - Form "XX3" Page 471 Category "VSX" +# binutils: vsx.d: 1b4: f1 12 e7 8f xvnmsubadp vs40,vs50,vs60 +:xvnmsubadp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=241 & XA & XB & XT { xvnmsubadpOp(XA,XB,XT); } + +define pcodeop xvcvsxwdpOp; +# ISA-cmt: xvcvsxwdp - VSX Vector Convert Signed Fixed-Point Word to Double-Precision format +# ISA-info: xvcvsxwdp - Form "XX2" Page 430 Category "VSX" +# binutils: vsx.d: 13c: f1 00 e3 e3 xvcvsxwdp vs40,vs60 +:xvcvsxwdp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=248 & BI_BITS=0 & XB & XT { xvcvsxwdpOp(XB,XT); } + +define pcodeop xvnmsubmdpOp; +# ISA-cmt: xvnmsubmdp - VSX Vector Negative Multiply-Subtract Type-M Double-Precision +# ISA-info: xvnmsubmdp - Form "XX3" Page 474 Category "VSX" +# binutils: vsx.d: 1b8: f1 12 e7 cf xvnmsubmdp vs40,vs50,vs60 +:xvnmsubmdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=249 & XA & XB & XT { xvnmsubmdpOp(XA,XB,XT); } + +define pcodeop xvrdpimOp; +# ISA-cmt: xvrdpim - VSX Vector Round to Double-Precision Integer toward -Infinity +# ISA-info: xvrdpim - Form "XX2" Page 478 Category "VSX" +# binutils: vsx.d: 1cc: f1 00 e3 e7 xvrdpim vs40,vs60 +:xvrdpim XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=249 & BITS_16_20=0 & XB & XT { xvrdpimOp(XB,XT); } + +define pcodeop xscvdpspOp; +# ISA-cmt: xscvdpsp - VSX Scalar Convert Double-Precision to Single-Precision +# ISA-info: xscvdpsp - Form "XX2" Page 352 Category "VSX" +# binutils: vsx.d: 30: f1 00 e4 27 xscvdpsp vs40,vs60 +:xscvdpsp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=265 & BITS_16_20=0 & XB & XT { xscvdpspOp(XB,XT); } + +define pcodeop xscvdpuxdsOp; +# ISA-cmt: xscvdpuxds - VSX Scalar truncate Double-Precision to integer and Convert to Unsigned Fixed-Point Doubleword format with Saturate +# ISA-info: xscvdpuxds - Form "XX2" Page 357 Category "VSX" +# binutils: vsx.d: 3c: f1 00 e5 23 xscvdpuxds vs40,vs60 +:xscvdpuxds XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=328 & BITS_16_20=0 & XB & XT { xscvdpuxdsOp(XB,XT); } + +define pcodeop xscvspdpOp; +# ISA-cmt: xscvspdp - VSX Scalar Convert Single-Precision to Double-Precision format +# binutils: vsx.d: 44: f1 00 e5 27 xscvspdp vs40,vs60 +:xscvspdp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=329 & BITS_16_20=0 & XB & XT { xscvspdpOp(XB,XT); } + +define pcodeop xscvdpsxdsOp; +# ISA-cmt: xscvdpsxds - VSX Scalar truncate Double-Precision to integer and Convert to Signed Fixed-Point Doubleword format with Saturate +# ISA-info: xscvdpsxds - Form "XX2" Page 353 Category "VSX" +# binutils: vsx.d: 34: f1 00 e5 63 xscvdpsxds vs40,vs60 +:xscvdpsxds XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=344 & BITS_16_20=0 & XB & XT { xscvdpsxdsOp(XB,XT); } + +define pcodeop xsabsdpOp; +# ISA-cmt: xsabsdp - VSX Scalar Absolute Value Double-Precision +# ISA-info: xsabsdp - Form "XX2" Page 341 Category "VSX" +# binutils: vsx.d: 1c: f1 00 e5 67 xsabsdp vs40,vs60 +:xsabsdp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=345 & XT & BITS_16_20=0 & XB { xsabsdpOp(XB,XT); } + +define pcodeop xscvuxddpOp; +# ISA-cmt: xscvuxddp - VSX Scalar Convert and round Unsigned Fixed-Point Doubleword to Double-Precision format +# binutils: vsx.d: 4c: f1 00 e5 a3 xscvuxddp vs40,vs60 +:xscvuxddp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=360 & BITS_16_20=0 & XB & XT { xscvuxddpOp(XB,XT); } + +define pcodeop xsnabsdpOp; +# ISA-cmt: xsnabsdp - VSX Scalar Negative Absolute Value Double-Precision +# ISA-info: xsnabsdp - Form "XX2" Page 377 Category "VSX" +# binutils: vsx.d: 70: f1 00 e5 a7 xsnabsdp vs40,vs60 +:xsnabsdp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=361 & BITS_16_20=0 & XB & XT { xsnabsdpOp(XB,XT); } + +define pcodeop xscvsxddpOp; +# ISA-cmt: xscvsxddp - VSX Scalar Convert and round Signed Fixed-Point Doubleword to Double-Precision format +# ISA-info: xscvsxddp - Form "XX2" Page 361 Category "VSX" +# binutils: vsx.d: 48: f1 00 e5 e3 xscvsxddp vs40,vs60 +:xscvsxddp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=376 & BITS_16_20=0 & XB & XT { xscvsxddpOp(XB,XT); } + +define pcodeop xsnegdpOp; +# ISA-cmt: xsnegdp - VSX Scalar Negate Double-Precision +# ISA-info: xsnegdp - Form "XX2" Page 377 Category "VSX" +# binutils: vsx.d: 74: f1 00 e5 e7 xsnegdp vs40,vs60 +:xsnegdp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=377 & BITS_16_20=0 & XB & XT { xsnegdpOp(XB,XT); } + +define pcodeop xvcvspuxdsOp; +# ISA-cmt: xvcvspuxds - VSX Vector truncate Single-Precision to integer and Convert to Unsigned Fixed-Point Doubleword format with Saturate +# ISA-info: xvcvspuxds - Form "XX2" Page 425 Category "VSX" +# binutils: vsx.d: 12c: f1 00 e6 23 xvcvspuxds vs40,vs60 +:xvcvspuxds XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=392 & BITS_16_20=0 & XB & XT { xvcvspuxdsOp(XB,XT); } + +define pcodeop xvcvdpspOp; +# ISA-cmt: xvcvdpsp - VSX Vector round and Convert Double-Precision to Single-Precision format +# ISA-info: xvcvdpsp - Form "XX2" Page 411 Category "VSX" +# binutils: vsx.d: 10c: f1 00 e6 27 xvcvdpsp vs40,vs60 +:xvcvdpsp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=393 & BITS_16_20=0 & XB & XT { xvcvdpspOp(XB,XT); } + +define pcodeop xvcvspsxdsOp; +# ISA-cmt: xvcvspsxds - VSX Vector truncate Single-Precision to integer and Convert to Signed Fixed-Point Doubleword format with Saturate +# ISA-info: xvcvspsxds - Form "XX2" Page 421 Category "VSX" +# binutils: vsx.d: 124: f1 00 e6 63 xvcvspsxds vs40,vs60 +:xvcvspsxds XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=408 & BITS_16_20=0 & XB & XT { xvcvspsxdsOp(XB,XT); } + +define pcodeop xvabsspOp; +# ISA-cmt: xvabssp - VSX Vector Absolute Value Single-Precision +# ISA-info: xvabssp - Form "XX2" Page 397 Category "VSX" +# binutils: vsx.d: b8: f1 00 e6 67 xvabssp vs40,vs60 +:xvabssp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=409 & BITS_16_20=0 & XB & XT { xvabsspOp(XB,XT); } + +define pcodeop xvcvuxdspOp; +# ISA-cmt: xvcvuxdsp - VSX Vector Convert and round Unsigned Fixed-Point Doubleword to Single-Precision format +# ISA-info: xvcvuxdsp - Form "XX2" Page 431 Category "VSX" +# binutils: vsx.d: 148: f1 00 e6 a3 xvcvuxdsp vs40,vs60 +:xvcvuxdsp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=424 & BITS_16_20=0 & XB & XT { xvcvuxdspOp(XB,XT); } + +define pcodeop xvnabsspOp; +# ISA-cmt: xvnabssp - VSX Vector Negative Absolute Value Single-Precision +# ISA-info: xvnabssp - Form "XX2" Page 461 Category "VSX" +# binutils: vsx.d: 198: f1 00 e6 a7 xvnabssp vs40,vs60 +:xvnabssp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=425 & BITS_16_20=0 & XB & XT { xvnabsspOp(XB,XT); } + +define pcodeop xvcvsxdspOp; +# ISA-cmt: xvcvsxdsp - VSX Vector Convert and round Signed Fixed-Point Doubleword to Single-Precision format +# ISA-info: xvcvsxdsp - Form "XX2" Page 429 Category "VSX" +# binutils: vsx.d: 138: f1 00 e6 e3 xvcvsxdsp vs40,vs60 +:xvcvsxdsp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=440 & BITS_16_20=0 & XB & XT { xvcvsxdspOp(XB,XT); } + +define pcodeop xvnegspOp; +# ISA-cmt: xvnegsp - VSX Vector Negate Single-Precision +# ISA-info: xvnegsp - Form "XX2" Page 462 Category "VSX" +# binutils: vsx.d: 1a0: f1 00 e6 e7 xvnegsp vs40,vs60 +:xvnegsp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=441 & BITS_16_20=0 & XB & XT { xvnegspOp(XB,XT); } + +define pcodeop xvcvdpuxdsOp; +# ISA-cmt: xvcvdpuxds - VSX Vector truncate Double-Precision to integer and Convert to Unsigned Fixed-Point Doubleword format with Saturate +# ISA-info: xvcvdpuxds - Form "XX2" Page 416 Category "VSX" +# binutils: vsx.d: 118: f1 00 e7 23 xvcvdpuxds vs40,vs60 +:xvcvdpuxds XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=456 & BITS_16_20=0 & XB & XT { xvcvdpuxdsOp(XB,XT); } + +define pcodeop xvcvspdpOp; +# ISA-cmt: xvcvspdp - VSX Vector Convert Single-Precision to Double-Precision +# ISA-info: xvcvspdp - Form "XX2" Page 420 Category "VSX" +# binutils: vsx.d: 120: f1 00 e7 27 xvcvspdp vs40,vs60 +:xvcvspdp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=457 & BITS_16_20=0 & XB & XT { xvcvspdpOp(XB,XT); } + +define pcodeop xvcvdpsxdsOp; +# ISA-cmt: xvcvdpsxds - VSX Vector truncate Double-Precision to integer and Convert to Signed Fixed-Point Doubleword Saturate +# ISA-info: xvcvdpsxds - Form "XX2" Page 412 Category "VSX" +# binutils: vsx.d: 110: f1 00 e7 63 xvcvdpsxds vs40,vs60 +:xvcvdpsxds XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=472 & BITS_16_20=0 & XB & XT { xvcvdpsxdsOp(XB,XT); } + +define pcodeop xvabsdpOp; +# ISA-cmt: xvabsdp - VSX Vector Absolute Value Double-Precision +# ISA-info: xvabsdp - Form "XX2" Page 397 Category "VSX" +# binutils: vsx.d: b4: f1 00 e7 67 xvabsdp vs40,vs60 +:xvabsdp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=473 & BITS_16_20=0 & XB & XT { xvabsdpOp(XB,XT); } + +define pcodeop xvcvuxddpOp; +# ISA-cmt: xvcvuxddp - VSX Vector Convert and round Unsigned Fixed-Point Doubleword to Double-Precision format +# ISA-info: xvcvuxddp - Form "XX2" Page 431 Category "VSX" +# binutils: vsx.d: 144: f1 00 e7 a3 xvcvuxddp vs40,vs60 +:xvcvuxddp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=488 & BITS_16_20=0 & XB & XT { xvcvuxddpOp(XB,XT); } + +define pcodeop xvnabsdpOp; +# ISA-cmt: xvnabsdp - VSX Vector Negative Absolute Value Double-Precision +# ISA-info: xvnabsdp - Form "XX2" Page 461 Category "VSX" +# binutils: vsx.d: 194: f1 00 e7 a7 xvnabsdp vs40,vs60 +:xvnabsdp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=489 & BITS_16_20=0 & XB & XT { xvnabsdpOp(XB,XT); } + +define pcodeop xvcvsxddpOp; +# ISA-cmt: xvcvsxddp - VSX Vector Convert and round Signed Fixed-Point Doubleword to Double-Precision format +# ISA-info: xvcvsxddp - Form "XX2" Page 429 Category "VSX" +# binutils: vsx.d: 134: f1 00 e7 e3 xvcvsxddp vs40,vs60 +:xvcvsxddp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=504 & BITS_16_20=0 & XB & XT { xvcvsxddpOp(XB,XT); } + +define pcodeop xvnegdpOp; +# ISA-cmt: xvnegdp - VSX Vector Negate Double-Precision +# ISA-info: xvnegdp - Form "XX2" Page 462 Category "VSX" +# binutils: vsx.d: 19c: f1 00 e7 e7 xvnegdp vs40,vs60 +:xvnegdp XT,XB is $(NOTVLE) & OP=60 & XOP_2_10=505 & BITS_16_20=0 & XB & XT { xvnegdpOp(XB,XT); } + +define pcodeop vsx207_1; +define pcodeop vsx207_2; +define pcodeop vsx207_3; +define pcodeop vsx207_5; +define pcodeop vsx207_8; +define pcodeop vsx207_9; +define pcodeop vsx207_10; +define pcodeop vsx207_11; +define pcodeop vsx207_12; +define pcodeop vsx207_13; +define pcodeop vsx207_14; +define pcodeop vsx207_15; +define pcodeop vsx207_16; +define pcodeop vsx207_17; +define pcodeop vsx207_18; +define pcodeop vsx207_19; +define pcodeop vsx207_20; +define pcodeop vsx207_21; +define pcodeop vsx207_22; +define pcodeop vsx207_23; +define pcodeop vsx207_24; +define pcodeop vsx207_25; +define pcodeop vsx207_26; +define pcodeop vsx207_27; +define pcodeop vsx207_28; +define pcodeop vsx207_29; +define pcodeop vsx207_30; + +define pcodeop vsx300_1; +define pcodeop vsx300_2; +define pcodeop vsx300_3; +define pcodeop vsx300_4; +define pcodeop vsx300_5; +define pcodeop vsx300_7; +define pcodeop vsx300_8; +define pcodeop vsx300_9; +define pcodeop vsx300_10; +define pcodeop vsx300_11; +define pcodeop vsx300_12; +define pcodeop vsx300_13; +define pcodeop vsx300_14; +define pcodeop vsx300_15; +define pcodeop vsx300_16; +define pcodeop vsx300_17; +define pcodeop vsx300_18; +define pcodeop vsx300_19; +define pcodeop vsx300_20; +define pcodeop vsx300_21; +define pcodeop vsx300_22; +define pcodeop vsx300_23; +define pcodeop vsx300_25; +define pcodeop vsx300_26; +define pcodeop vsx300_27; +define pcodeop vsx300_28; +define pcodeop vsx300_29; +define pcodeop vsx300_30; +define pcodeop vsx300_31; +define pcodeop vsx300_32; +define pcodeop vsx300_33; +define pcodeop vsx300_34; +define pcodeop vsx300_35; +define pcodeop vsx300_36; +define pcodeop vsx300_37; +define pcodeop vsx300_38; +define pcodeop vsx300_39; +define pcodeop vsx300_40; +define pcodeop vsx300_41; +define pcodeop vsx300_42; +define pcodeop vsx300_43; +define pcodeop vsx300_44; +define pcodeop vsx300_45; +define pcodeop vsx300_46; +define pcodeop vsx300_47; +define pcodeop vsx300_48; +define pcodeop vsx300_49; +define pcodeop vsx300_50; +define pcodeop vsx300_51; +define pcodeop vsx300_52; +define pcodeop vsx300_53; +define pcodeop vsx300_54; +define pcodeop vsx300_55; +define pcodeop vsx300_56; +define pcodeop vsx300_57; +define pcodeop vsx300_58; +define pcodeop vsx300_59; +define pcodeop vsx300_60; +define pcodeop vsx300_61; +define pcodeop vsx300_62; +define pcodeop vsx300_63; +define pcodeop vsx300_64; +define pcodeop vsx300_65; +define pcodeop vsx300_66; +define pcodeop vsx300_67; +define pcodeop vsx300_68; +define pcodeop vsx300_69; +define pcodeop vsx300_70; +define pcodeop vsx300_71; +define pcodeop vsx300_72; +define pcodeop vsx300_73; +define pcodeop vsx300_74; +define pcodeop vsx300_75; +define pcodeop vsx300_76; +define pcodeop vsx300_77; +define pcodeop vsx300_78; +define pcodeop vsx300_79; +define pcodeop vsx300_80; +define pcodeop vsx300_81; +define pcodeop vsx300_82; +define pcodeop vsx300_83; +define pcodeop vsx300_84; +define pcodeop vsx300_85; +define pcodeop vsx300_86; +define pcodeop vsx300_87; +define pcodeop vsx300_88; +define pcodeop vsx300_89; +define pcodeop vsx300_90; +define pcodeop vsx300_91; +define pcodeop vsx300_92; +define pcodeop vsx300_93; +define pcodeop vsx300_94; +define pcodeop vsx300_95; +define pcodeop vsx300_96; +define pcodeop vsx300_97; +define pcodeop vsx300_98; +define pcodeop vsx300_99; +define pcodeop vsx300_100; +define pcodeop vsx300_101; +define pcodeop vsx300_102; +define pcodeop vsx300_103; + +################# +# v2.07 additions +:lxsiwax XT,A,B is $(NOTVLE) & OP=31 & XT & A & B & XOP_1_10=76 { + XT = vsx207_1(A,B); +} + +:lxsiwzx XT,A,B is $(NOTVLE) & OP=31 & XT & A & B & XOP_1_10=12 { + XT = vsx207_2(A,B); +} + +:lxsspx XT,A,B is $(NOTVLE) & OP=31 & XT & A & B & XOP_1_10=524 { + XT = vsx207_3(A,B); +} + +:mfvsrd A,XSF is $(NOTVLE) & OP=31 & XOP_1_10=51 & BITS_11_15=0 & XSF & A { + A = XSF; +} + +:mfvsrwz A,XSF is $(NOTVLE) & OP=31 & XOP_1_10=115 & BITS_11_15=0 & XSF & A { + A[0,32] = XSF[0,32]; + A[32,32] = 0; +} + +:mtvsrd XTF,A is $(NOTVLE) & OP=31 & XOP_1_10=179 & BITS_11_15=0 & XTF & A { + XTF = A; +} + +:mtvsrwa XTF,A is $(NOTVLE) & OP=31 & XOP_1_10=211 & BITS_11_15=0 & XTF & A { + XTF = sext(A:4); +} + +:mtvsrwz XTF,A is $(NOTVLE) & OP=31 & XOP_1_10=243 & BITS_11_15=0 & XTF & A { + XTF = zext(A:4); +} + +:stxsiwx XS,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & XS & RA_OR_ZERO & B & XOP_1_10=140 { + EA:$(REGISTER_SIZE) = RA_OR_ZERO + B; + *[ram]:4 EA = vsx207_9(XS,RA_OR_ZERO,B); +} + +:stxsspx XS,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & XS & RA_OR_ZERO & B & XOP_1_10=652 { + EA:$(REGISTER_SIZE) = RA_OR_ZERO + B; + *[ram]:4 EA = vsx207_10(XS,RA_OR_ZERO,B); +} + +:xsaddsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=0 & XA & XB & XT { + XT = vsx207_11(XA,XB); +} + +:xscvdpspn XT,XB is $(NOTVLE) & OP=60 & BITS_16_20=0 & XOP_2_10=267 & XB & XT +{ + src:4 = float2float(XB:8); + XT[0,32] = src; +} + +:xscvspdpn XT,XB is $(NOTVLE) & OP=60 & BITS_16_20=0 & XOP_2_10=331 & XB & XT { + XT = vsx207_13(XB); +} + +:xscvsxdsp XT,XB is $(NOTVLE) & OP=60 & BITS_16_20=0 & XOP_2_10=312 & XB & XT { + XT = vsx207_14(XB); +} + +:xscvuxdsp XT,XB is $(NOTVLE) & OP=60 & BITS_16_20=0 & XOP_2_10=296 & XB & XT { + XT = vsx207_15(XB); +} + +:xsdivsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=24 & XA & XB & XT { + XT = vsx207_16(XA,XB); +} + +:xsmaddasp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=1 & XA & XB & XT { + XT = vsx207_17(XA,XB); +} + +:xsmaddmsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=9 & XA & XB & XT { + XT = vsx207_18(XA,XB); +} + +:xsmsubasp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=17 & XA & XB & XT { + XT = vsx207_19(XA,XB); +} + +:xsmsubmsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=25 & XA & XB & XT { + XT = vsx207_20(XA,XB); +} + +:xsmulsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=16 & XA & XB & XT { + XT = vsx207_21(XA,XB); +} + +:xsnmaddasp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=129 & XA & XB & XT { + XT = vsx207_22(XA,XB); +} + +:xsnmaddmsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=137 & XA & XB & XT { + XT = vsx207_23(XA,XB); +} + +:xsnmsubasp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=145 & XA & XB & XT { + XT = vsx207_24(XA,XB); +} + +:xsnmsubmsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=153 & XA & XB & XT { + XT = vsx207_25(XA,XB); +} + +:xsresp XT,XB is $(NOTVLE) & OP=60 & BITS_16_20=0 & XOP_2_10=26 & XB & XT { + XT = vsx207_26(XB); +} + +:xsrsp XT,XB is $(NOTVLE) & OP=60 & BITS_16_20=0 & XOP_2_10=281 & XB & XT { + XT = vsx207_27(XB); +} + +:xsrsqrtesp XT,XB is $(NOTVLE) & OP=60 & BITS_16_20=0 & XOP_2_10=10 & XB & XT { + XT = vsx207_28(XB); +} + +:xssqrtsp XT,XB is $(NOTVLE) & OP=60 & BITS_16_20=0 & XOP_2_10=11 & XB & XT { + XT = vsx207_29(XB); +} + +:xssubsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=8 & XA & XB & XT { + XT = vsx207_30(XA,XB); +} + +:xxleqv XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=186 & XA & XB & XT { + XT = ~(XA ^ XB); +} + +:xxlnand XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=178 & XA & XB & XT { + XT = ~(XA & XB); +} + +:xxlorc XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=170 & XA & XB & XT { + XT = XA | (~XB); +} + +####################### +# v3.0 + +# The endian behavior of the storage has not been modelled +:lxsd vrD,DSs(RA_OR_ZERO) is $(NOTVLE) & OP=57 & vrD & RA_OR_ZERO & BITS_0_1=2 & DSs { + ea:$(REGISTER_SIZE) = RA_OR_ZERO + (DSs << 2); + vrD[0,64] = *:8 ea; +} + +:lxsibzx XT,A,B is $(NOTVLE) & OP=31 & XT & A & B & XOP_1_10=781 { + XT = vsx300_2(A,B); +} + +:lxsihzx XT,A,B is $(NOTVLE) & OP=31 & XT & A & B & XOP_1_10=813 { + XT = vsx300_3(A,B); +} + +:lxssp vrD,DSs(RA_OR_ZERO) is $(NOTVLE) & OP=57 & vrD & RA_OR_ZERO & BITS_0_1=3 & DSs { + vrD = vsx300_4(DSs:2,RA_OR_ZERO); +} + +# The endian behavior of the storage has not been modelled +:lxv XT3,DQs(RA_OR_ZERO) is $(NOTVLE) & OP=61 & XT3 & RA_OR_ZERO & BITS_0_2=1 & DQs { + ea:$(REGISTER_SIZE) = RA_OR_ZERO + (DQs << 4); + XT3 = *:16 ea; +} + +:lxvx XT,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & XOP_1_5=12 & BIT_6=0 & XOP_7_10=4 & RA_OR_ZERO & B & XT { + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + XT = *:16 ea; +} + +:lxvb16x XT,A,B is $(NOTVLE) & OP=31 & XT & A & B & XOP_1_10=876 { + XT = vsx300_7(A,B); +} + +:lxvh8x XT,A,B is $(NOTVLE) & OP=31 & XT & A & B & XOP_1_10=812 { + XT = vsx300_8(A,B); +} + +:lxvl XT,A,B is $(NOTVLE) & OP=31 & XT & A & B & XOP_1_10=269 { + XT = vsx300_9(A,B); +} + +:lxvll XT,A,B is $(NOTVLE) & OP=31 & XT & A & B & XOP_1_10=301 { + XT = vsx300_10(A,B); +} + +:lxvwsx XT,A,B is $(NOTVLE) & OP=31 & XT & A & B & XOP_1_10=364 { + XT = vsx300_11(A,B); +} + +:mfvsrld A,XSF is $(NOTVLE) & OP=31 & XOP_1_10=307 & BITS_11_15=0 & XSF & A { + A = vsx300_12(XSF); +} + +:mtvsrdd XTF,A,B is $(NOTVLE) & OP=31 & XTF & A & B & XOP_1_10=435 { + XTF = vsx300_13(A,B); +} + +:mtvsrws XTF,A is $(NOTVLE) & OP=31 & XOP_1_10=403 & BITS_11_15=0 & XTF & A { + XTF = vsx300_14(A); +} + +:stxsd vrS,DSs(RA_OR_ZERO) is $(NOTVLE) & OP=61 & vrS & RA_OR_ZERO & BITS_0_1=2 & DSs { + vsx300_15(vrS,DSs:2,RA_OR_ZERO); +} + +:stxsibx XS,A,B is $(NOTVLE) & OP=31 & XS & A & B & XOP_1_10=909 { + vsx300_16(XS,A,B); +} + +:stxsihx XS,A,B is $(NOTVLE) & OP=31 & XS & A & B & XOP_1_10=941 { + vsx300_17(XS,A,B); +} + +:stxssp vrS,DSs(RA_OR_ZERO) is $(NOTVLE) & OP=61 & vrS & RA_OR_ZERO & BITS_0_1=3 & DSs { + vsx300_18(vrS,DSs:2,RA_OR_ZERO); +} + +# The endian behavior of the storage has not been modelled +:stxv XS3,DQs(RA_OR_ZERO) is $(NOTVLE) & OP=61 & XS3 & RA_OR_ZERO & BITS_0_2=5 & DQs { + ea:$(REGISTER_SIZE) = RA_OR_ZERO + (DQs << 4); + *:16 ea = XS3; +} + +:stxvb16x XS,A,B is $(NOTVLE) & OP=31 & XS & A & B & XOP_1_10=1004 { + vsx300_20(XS,A,B); +} + +:stxvh8x XS,A,B is $(NOTVLE) & OP=31 & XS & A & B & XOP_1_10=940 { + vsx300_21(XS,A,B); +} + +:stxvl XS,A,B is $(NOTVLE) & OP=31 & XS & A & B & XOP_1_10=397 { + vsx300_22(XS,A,B); +} + +:stxvll XS,A,B is $(NOTVLE) & OP=31 & XS & A & B & XOP_1_10=429 { + vsx300_23(XS,A,B); +} + +:stxvx XS,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & XS & RA_OR_ZERO & B & XOP_1_10=396 { + ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; + *:16 ea = XS; +} + +:xsabsqp vrD,vrB is $(NOTVLE) & OP=63 & BITS_16_20=0 & BIT_0=0 & XOP_1_10=804 & vrD & vrB { + vrD = vsx300_25(vrB); +} + +:xsaddqp vrD,vrA,vrB is $(NOTVLE) & OP=63 & XOP_1_10=4 & R0=0 & vrD & vrA & vrB { + vrD = vsx300_26(vrA,vrB); +} + +:xsaddqpo vrD,vrA,vrB is $(NOTVLE) & OP=63 & XOP_1_10=4 & R0=1 & vrD & vrA & vrB { + vrD = vsx300_27(vrA,vrB); +} + +:xscmpeqdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=3 & XA & XB & XT { + XT = vsx300_28(XA,XB); +} + +:xscmpexpdp BF2,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=59 & BITS_21_22=0 & BIT_0=0 & XA & XB & BF2 { + vsx300_29(BF2:1,XA,XB); +} + +:xscmpexpqp BF2,vrA,vrB is $(NOTVLE) & OP=63 & BITS_21_22=0 & BIT_0=0 & XOP_1_10=164 & R0=0 & BF2 & vrA & vrB { + vsx300_30(BF2:1,vrA,vrB); +} + +:xscmpgedp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=19 & XA & XB & XT { + XT = vsx300_31(XA,XB); +} + +:xscmpgtdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=11 & XA & XB & XT { + XT = vsx300_32(XA,XB); +} + +:xscmpnedp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=27 & XA & XB & XT { + XT = vsx300_33(XA,XB); +} + +:xscmpoqp BF2,vrA,vrB is $(NOTVLE) & OP=63 & XOP_1_10=132 & BITS_21_22=0 & BIT_0=0 & vrA & vrB & BF2 { + vsx300_34(BF2:1,vrA,vrB); +} + +:xscmpuqp BF2,vrA,vrB is $(NOTVLE) & OP=63 & XOP_1_10=644 & BITS_21_22=0 & BIT_0=0 & vrA & vrB & BF2 { + vsx300_35(BF2:1,vrA,vrB); +} + +:xscpsgnqp vrD,vrA,vrB is $(NOTVLE) & OP=63 & BIT_0=0 & XOP_1_10=100 & vrD & vrA & vrB { + vrD = vsx300_36(vrA,vrB); +} + +:xscvdphp XT,XB is $(NOTVLE) & OP=60 & BITS_16_20=17 & XOP_2_10=347 & XB & XT { + XT = vsx300_37(XB); +} + +:xscvdpqp vrD,vrB is $(NOTVLE) & OP=63 & BITS_16_20=22 & BIT_0=0 & XOP_1_10=836 & vrD & vrB { + vrD = vsx300_38(vrB); +} + +:xscvhpdp XT,XB is $(NOTVLE) & OP=60 & BITS_16_20=16 & XOP_2_10=347 & XB & XT { + XT = vsx300_39(XB); +} + +:xscvqpdp vrD,vrB is $(NOTVLE) & OP=63 & BITS_16_20=20 & XOP_1_10=836 & R0=0 & vrD & vrB { + vrD = vsx300_40(vrB); +} + +:xscvqpdpo vrD,vrB is $(NOTVLE) & OP=63 & BITS_16_20=20 & XOP_1_10=836 & R0=1 & vrD & vrB { + vrD = vsx300_41(vrB); +} + +:xscvqpsdz vrD,vrB is $(NOTVLE) & OP=63 & BITS_16_20=25 & XOP_1_10=836 & BIT_0=0 & vrD & vrB { + vrD = vsx300_42(vrB); +} + +:xscvqpswz vrD,vrB is $(NOTVLE) & OP=63 & BITS_16_20=9 & XOP_1_10=836 & BIT_0=0 & vrD & vrB { + vrD = vsx300_43(vrB); +} + +:xscvqpudz vrD,vrB is $(NOTVLE) & OP=63 & BITS_16_20=17 & XOP_1_10=836 & BIT_0=0 & vrD & vrB { + vrD = vsx300_44(vrB); +} + +:xscvqpuwz vrD,vrB is $(NOTVLE) & OP=63 & BITS_16_20=1 & XOP_1_10=836 & BIT_0=0 & vrD & vrB { + vrD = vsx300_45(vrB); +} + +:xscvsdqp vrD,vrB is $(NOTVLE) & OP=63 & BITS_16_20=10 & XOP_1_10=836 & BIT_0=0 & vrD & vrB { + vrD = vsx300_46(vrB); +} + +:xscvudqp vrD,vrB is $(NOTVLE) & OP=63 & BITS_16_20=2 & XOP_1_10=836 & BIT_0=0 & vrD & vrB { + vrD = vsx300_47(vrB); +} + +:xsdivqp vrD,vrA,vrB is $(NOTVLE) & OP=63 & XOP_1_10=548 & R0=0 & vrD & vrA & vrB { + vrD = vsx300_47(vrA,vrB); +} + +:xsdivqpo vrD,vrA,vrB is $(NOTVLE) & OP=63 & XOP_1_10=548 & R0=1 & vrD & vrA & vrB { + vrD = vsx300_48(vrA,vrB); +} + +:xsiexpdp XT,A,B is $(NOTVLE) & OP=60 & XT & A & B & XOP_1_10=918 { + vsx300_49(A,B); +} + +:xsiexpqp vrD,vrA,vrB is $(NOTVLE) & OP=63 & BIT_0=0 & XOP_1_10=868 & vrD & vrA & vrB { + vrD = vsx300_50(vrA,vrB); +} + +:xsmaddqp vrD,vrA,vrB is $(NOTVLE) & OP=63 & XOP_1_10=388 & R0=0 & vrD & vrA & vrB { + vrD = vsx300_51(vrA,vrB); +} + +:xsmaddqpo vrD,vrA,vrB is $(NOTVLE) & OP=63 & XOP_1_10=388 & R0=1 & vrD & vrA & vrB { + vrD = vsx300_52(vrA,vrB); +} + +:xsmaxcdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=128 & XA & XB & XT { + XT = vsx300_53(XA,XB); +} + +:xsmaxjdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=144 & XA & XB & XT { + XT = vsx300_54(XA,XB); +} + +:xsmincdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=136 & XA & XB & XT { + XT = vsx300_55(XA,XB); +} + +:xsminjdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=152 & XA & XB & XT { + XT = vsx300_56(XA,XB); +} + +:xsmsubqp vrD,vrA,vrB is $(NOTVLE) & OP=63 & XOP_1_10=420 & R0=0 & vrD & vrA & vrB { + vrD = vsx300_57(vrA,vrB); +} + +:xsmsubqpo vrD,vrA,vrB is $(NOTVLE) & OP=63 & XOP_1_10=420 & R0=1 & vrD & vrA & vrB { + vrD = vsx300_58(vrA,vrB); +} + +:xsmulqp vrD,vrA,vrB is $(NOTVLE) & OP=63 & XOP_1_10=36 & R0=0 & vrD & vrA & vrB { + vrD = vsx300_59(vrA,vrB); +} + +:xsmulqpo vrD,vrA,vrB is $(NOTVLE) & OP=63 & XOP_1_10=36 & R0=1 & vrD & vrA & vrB { + vrD = vsx300_60(vrA,vrB); +} + +:xsnabsqp vrD,vrB is $(NOTVLE) & OP=63 & BITS_16_20=8 & XOP_1_10=804 & BIT_0=0 & vrD & vrB { + vrD = vsx300_61(vrB); +} + +:xsnegqp vrD,vrB is $(NOTVLE) & OP=63 & BITS_16_20=16 & XOP_1_10=804 & BIT_0=0 & vrD & vrB { + vrD = vsx300_62(vrB); +} + +:xsnmaddqp vrD,vrA,vrB is $(NOTVLE) & OP=63 & XOP_1_10=452 & R0=0 & vrD & vrA & vrB { + vrD = vsx300_63(vrA,vrB); +} + +:xsnmaddqpo vrD,vrA,vrB is $(NOTVLE) & OP=63 & XOP_1_10=452 & R0=1 & vrD & vrA & vrB { + vrD = vsx300_64(vrA,vrB); +} + +:xsnmsubqp vrD,vrA,vrB is $(NOTVLE) & OP=63 & XOP_1_10=484 & R0=0 & vrD & vrA & vrB { + vrD = vsx300_65(vrA,vrB); +} + +:xsnmsubqpo vrD,vrA,vrB is $(NOTVLE) & OP=63 & XOP_1_10=484 & R0=1 & vrD & vrA & vrB { + vrD = vsx300_66(vrA,vrB); +} + +:xsrqpi R16,vrD,vrB,RMC is $(NOTVLE) & OP=63 & BITS_17_20=0 & XOP_1_8=5 & EX=0 & vrD & vrB & R16 & RMC { + vrD = vsx300_67(vrB,RMC:1,R16:1); +} + +:xsrqpix R16,vrD,vrB,RMC is $(NOTVLE) & OP=63 & BITS_17_20=0 & XOP_1_8=5 & EX=1 & vrD & vrB & R16 & RMC { + vrD = vsx300_68(vrB,RMC:1,R16:1); +} + +:xsrqpxp R16,vrD,vrB,RMC is $(NOTVLE) & OP=63 & BITS_17_20=0 & XOP_1_8=37 & BIT_0=0 & vrD & vrB & R16 & RMC { + vrD = vsx300_69(vrB,RMC:1,R16:1); +} + +:xssqrtqp vrD,vrB is $(NOTVLE) & OP=63 & BITS_16_20=27 & XOP_1_10=804 & R0=0 & vrD & vrB { + vrD = vsx300_70(vrB); +} + +:xssqrtqpo vrD,vrB is $(NOTVLE) & OP=63 & BITS_16_20=27 & XOP_1_10=804 & R0=1 & vrD & vrB { + vrD = vsx300_71(vrB); +} + +:xssubqp vrD,vrA,vrB is $(NOTVLE) & OP=63 & XOP_1_10=516 & R0=0 & vrD & vrA & vrB { + vrD = vsx300_72(vrA,vrB); +} + +:xssubqpo vrD,vrA,vrB is $(NOTVLE) & OP=63 & XOP_1_10=516 & R0=1 & vrD & vrA & vrB { + vrD = vsx300_73(vrA,vrB); +} + +:xststdcdp BF2,XB,DCMX is $(NOTVLE) & OP=60 & BIT_0=0 & XOP_2_10=362 & XB & BF2 & DCMX { + vsx300_74(XB,BF2:1,DCMX:1); +} + +:xststdcqp BF2,vrB,DCMX is $(NOTVLE) & OP=63 & XOP_1_10=708 & BIT_0=0 & vrB & BF2 & DCMX { + vsx300_75(vrB,BF2:1,DCMX:1); +} + +:xststdcsp BF2,XB,DCMX is $(NOTVLE) & OP=60 & BIT_0=0 & XOP_2_10=298 & XB & BF2 & DCMX { + vsx300_76(XB,BF2:1,DCMX:1); +} + +:xsxexpdp D,XB is $(NOTVLE) & OP=60 & BITS_16_20=0 & BIT_0=0 & XOP_2_10=347 & XB & D { + D = vsx300_77(XB); +} + +:xsxexpqp vrD,vrB is $(NOTVLE) & OP=63 & BITS_16_20=2 & XOP_1_10=804 & BIT_0=0 & vrD & vrB { + vrD = vsx300_78(vrB); +} + +:xsxsigdp D,XB is $(NOTVLE) & OP=60 & BITS_16_20=1 & BIT_0=0 & XOP_2_10=347 & XB & D { + D = vsx300_79(XB); +} + +:xsxsigqp vrD,vrB is $(NOTVLE) & OP=63 & BITS_16_20=18 & XOP_1_10=804 & BIT_0=0 & vrD & vrB { + vrD = vsx300_80(vrB); +} + +:xvcmpnedp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=123 & Rc2=0 & XA & XB & XT { + XT = vsx300_81(XA,XB); +} + +:xvcmpnedp. XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=123 & Rc2=1 & XA & XB & XT { + XT = vsx300_82(XA,XB); +} + +:xvcmpnesp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=91 & Rc2=0 & XA & XB & XT { + XT = vsx300_83(XA,XB); +} + +:xvcmpnesp. XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_9=91 & Rc2=1 & XA & XB & XT { + XT = vsx300_84(XA,XB); +} + +:xvcvhpsp XT,XB is $(NOTVLE) & OP=60 & BITS_16_20=24 & XOP_2_10=475 & XB & XT { + XT = vsx300_85(XB); +} + +:xvcvsphp XT,XB is $(NOTVLE) & OP=60 & BITS_16_20=25 & XOP_2_10=475 & XB & XT { + XT = vsx300_86(XB); +} + +:xviexpdp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=248 & XA & XB & XT { + XT = vsx300_87(XA,XB); +} + +:xviexpsp XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=216 & XA & XB & XT { + XT = vsx300_88(XA,XB); +} + +:xvtstdcdp XT,XB,DBUILD is $(NOTVLE) & OP=60 & XOP_3_5=5 & XOP_7_10=15 & XA & XB & XT & DBUILD { + XT = vsx300_89(XB,DBUILD); +} + +:xvtstdcsp XT,XB,DBUILD is $(NOTVLE) & OP=60 & XOP_3_5=5 & XOP_7_10=13 & XA & XB & XT & DBUILD { + XT = vsx300_90(XB,DBUILD); +} + +:xvxexpdp XT,XB is $(NOTVLE) & OP=60 & BITS_16_20=0 & XOP_2_10=475 & XB & XT { + XT = vsx300_91(XB); +} + +:xvxexpsp XT,XB is $(NOTVLE) & OP=60 & BITS_16_20=8 & XOP_2_10=475 & XB & XT { + XT = vsx300_92(XB); +} + +:xvxsigdp XT,XB is $(NOTVLE) & OP=60 & BITS_16_20=1 & XOP_2_10=475 & XB & XT { + XT = vsx300_93(XB); +} + +:xvxsigsp XT,XB is $(NOTVLE) & OP=60 & BITS_16_20=9 & XOP_2_10=475 & XB & XT { + XT = vsx300_94(XB); +} + +:xxbrd XT,XB is $(NOTVLE) & OP=60 & BITS_16_20=23 & XOP_2_10=475 & XB & XT { + XT = vsx300_95(XB); +} + +:xxbrh XT,XB is $(NOTVLE) & OP=60 & BITS_16_20=7 & XOP_2_10=475 & XB & XT { + XT = vsx300_96(XB); +} + +:xxbrq XT,XB is $(NOTVLE) & OP=60 & BITS_16_20=31 & XOP_2_10=475 & XB & XT { + XT = vsx300_97(XB); +} + +:xxbrw XT,XB is $(NOTVLE) & OP=60 & BITS_16_20=15 & XOP_2_10=475 & XB & XT { + XT = vsx300_98(XB); +} + +:xxextractuw XT,XB,UIMB is $(NOTVLE) & OP=60 & BIT_20=0 & XOP_2_10=165 & XB & XT & UIMB { + XT = vsx300_99(XB,UIMB:1); +} + +:xxinsertw XT,XB,UIMB is $(NOTVLE) & OP=60 & BIT_20=0 & XOP_2_10=181 & XB & XT & UIMB { + XT = vsx300_100(XB,UIMB:1); +} + +:xxperm XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=26 & XA & XB & XT { + XT = vsx300_101(XA,XB); +} + +:xxpermr XT,XA,XB is $(NOTVLE) & OP=60 & XOP_3_10=58 & XA & XB & XT { + XT = vsx300_102(XA,XB); +} + +:xxspltib XT,UIMM8 is $(NOTVLE) & OP=60 & BITS_19_20=0 & XOP_1_10=360 & XT & UIMM8 { + tmpa:16 = zext(UIMM8:1); + tmpa = tmpa | (tmpa << 8); + tmpa = tmpa | (tmpa << 16); + tmpa = tmpa | (tmpa << 32); + tmpa = tmpa | (tmpa << 64); + XT = tmpa; +} diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/RV32G.pspec b/python/icicle/Ghidra/Processors/RISCV/data/languages/RV32G.pspec new file mode 100644 index 0000000..b3b2a71 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/RV32G.pspec @@ -0,0 +1,19 @@ + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/RV32GC.pspec b/python/icicle/Ghidra/Processors/RISCV/data/languages/RV32GC.pspec new file mode 100644 index 0000000..133923e --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/RV32GC.pspec @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/RV32I.pspec b/python/icicle/Ghidra/Processors/RISCV/data/languages/RV32I.pspec new file mode 100644 index 0000000..7ece09e --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/RV32I.pspec @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/RV32IC.pspec b/python/icicle/Ghidra/Processors/RISCV/data/languages/RV32IC.pspec new file mode 100644 index 0000000..148daf4 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/RV32IC.pspec @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/RV32IMC.pspec b/python/icicle/Ghidra/Processors/RISCV/data/languages/RV32IMC.pspec new file mode 100644 index 0000000..b9f539d --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/RV32IMC.pspec @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/RV64G.pspec b/python/icicle/Ghidra/Processors/RISCV/data/languages/RV64G.pspec new file mode 100644 index 0000000..dcf939f --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/RV64G.pspec @@ -0,0 +1,19 @@ + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/RV64GC.pspec b/python/icicle/Ghidra/Processors/RISCV/data/languages/RV64GC.pspec new file mode 100644 index 0000000..2e75cb4 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/RV64GC.pspec @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/RV64I.pspec b/python/icicle/Ghidra/Processors/RISCV/data/languages/RV64I.pspec new file mode 100644 index 0000000..726e53d --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/RV64I.pspec @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/RV64IC.pspec b/python/icicle/Ghidra/Processors/RISCV/data/languages/RV64IC.pspec new file mode 100644 index 0000000..0944cda --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/RV64IC.pspec @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.csr.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.csr.sinc new file mode 100644 index 0000000..b29608f --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.csr.sinc @@ -0,0 +1,166 @@ +# RV32/RV64 Zicsr Standard Extension + + +# csrrc d,E,s 00003073 0000707f SIMPLE (0, 0) +:csrrc rdDst,csr,rs1 is rs1 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x3 & op1519 +{ + local tmprs1:$(XLEN) = rs1; + local oldcsr:$(XLEN) = csr:$(XLEN); + rdDst = oldcsr; + local tmp:$(XLEN) = op1519; + if (tmp == 0) goto inst_next; + local newcsr:$(XLEN) = oldcsr & ~tmprs1; + csr = newcsr; +} + + +# csrrci d,E,Z 00007073 0000707f SIMPLE (0, 0) +:csrrci rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7 +{ + local oldcsr:$(XLEN) = csr:$(XLEN); + rdDst = oldcsr; + local tmp:$(XLEN) = op1519; + if (tmp == 0) goto inst_next; + csr = csr & ~tmp; +} + + +# csrrs d,E,s 00002073 0000707f SIMPLE (0, 0) +:csrrs rdDst,csr,rs1 is rs1 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519 +{ + local tmprs1 = rs1; + local oldcsr:$(XLEN) = csr:$(XLEN); + rdDst = oldcsr; + local tmp:$(XLEN) = op1519; + if (tmp == 0) goto inst_next; + csr = csr | tmprs1; +} + + +# csrrsi d,E,Z 00006073 0000707f SIMPLE (0, 0) +:csrrsi rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6 +{ + local oldcsr:$(XLEN) = csr:$(XLEN); + rdDst = oldcsr; + local tmp:$(XLEN) = op1519; + if (tmp == 0) goto inst_next; + csr = csr | tmp; +} + + +# csrrw d,E,s 00001073 0000707f SIMPLE (0, 0) +:csrrw rdDst,csr,rs1 is rs1 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op1519 +{ + local tmprs1:$(XLEN) = rs1; + local oldcsr:$(XLEN) = csr:$(XLEN); + local tmp:$(XLEN) = op1519; + csr = tmprs1; + if (tmp == 0) goto inst_next; + rdDst = oldcsr; +} + + +# csrrwi d,E,Z 00005073 0000707f SIMPLE (0, 0) +:csrrwi rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 +{ + local oldcsr:$(XLEN) = csr:$(XLEN); + local tmp:$(XLEN) = op1519; + csr = tmp; + if (tmp == 0) goto inst_next; + rdDst = oldcsr; +} + + +# frcsr d 00302073 fffff07f SIMPLE (0, 0) +:frcsr rdDst is rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x60 +{ + rdDst = fcsr; +} + +# frflags d 00102073 fffff07f SIMPLE (0, 0) +:frflags rdDst is rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x20 +{ + rdDst = zext(fflags[0,5]); +} + +# frrm d 00202073 fffff07f SIMPLE (0, 0) +:frrm rdDst is rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x40 +{ + rdDst = frm; +} + +# fscsr s 00301073 fff07fff SIMPLE (0, 0) +:fscsr rs1 is rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0 & op2031=0x3 +{ + zero = fcsr; + fcsr = rs1; +} + +# fscsr d,s 00301073 fff0707f SIMPLE (0, 0) +:fscsr rdDst,rs1 is rs1 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x3 +{ + rdDst = fcsr; + fcsr = rs1; +} + + +# fsflags s 00101073 fff07fff SIMPLE (0, 0) +:fsflags rs1 is rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0 & op2031=0x1 +{ + zero = zext(fflags[0,5]); + fflags[0,5] = rs1[0,5]; +} + +# fsflags d,s 00101073 fff0707f SIMPLE (0, 0) +:fsflags rdDst,rs1 is rs1 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x1 +{ + rdDst = zext(fflags[0,5]); + fflags[0,5] = rs1[0,5]; +} + +# fsflagsi d,Z 00105073 fff0707f SIMPLE (0, 0) +:fsflagsi rdDst,op1519 is op1519 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op2031=0x1 +{ + rdDst = zext(fflags[0,5]); + local tmp:1 = op1519:1; + fflags[0,5] = tmp[0,5]; +} + +# fsflagsi Z 00105073 fff07fff SIMPLE (0, 0) +:fsflagsi op1519 is op1519 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op0711=0x0 & op2031=0x1 +{ + zero = zext(fflags[0,5]); + local tmp:1 = op1519:1; + fflags[0,5] = tmp[0,5]; +} + +# fsrm s 00201073 fff07fff SIMPLE (0, 0) +:fsrm rs1 is rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0 & op2031=0x2 +{ + zero = zext(frm[0,3]); + frm[0,3] = rs1[0,3]; +} + +# fsrm d,s 00201073 fff0707f SIMPLE (0, 0) +:fsrm rdDst,rs1 is rs1 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x2 +{ + rdDst = zext(frm[0,3]); + frm[0,3] = rs1[0,3]; +} + +# fsrmi d,Z 00205073 fff0707f SIMPLE (0, 0) +:fsrmi rdDst,op1519 is op1519 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op2031=0x2 +{ + rdDst = zext(frm[0,3]); + local tmp:1 = op1519:1; + frm[0,3] = tmp[0,3]; +} + +# fsrmi Z 00205073 fff07fff SIMPLE (0, 0) +:fsrmi op1519 is op1519 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op0711=0x0 & op2031=0x2 +{ + zero = zext(frm[0,3]); + local tmp:1 = op1519:1; + frm[0,3] = tmp[0,3]; +} + diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.custom.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.custom.sinc new file mode 100644 index 0000000..3b859a1 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.custom.sinc @@ -0,0 +1,155 @@ +# custom + +define pcodeop custom0; +define pcodeop custom0.rs1; +define pcodeop custom0.rs1.rs2; +define pcodeop custom0.rd; +define pcodeop custom0.rd.rs1; +define pcodeop custom0.rd.rs1.rs2; + +define pcodeop custom1; +define pcodeop custom1.rs1; +define pcodeop custom1.rs1.rs2; +define pcodeop custom1.rd; +define pcodeop custom1.rd.rs1; +define pcodeop custom1.rd.rs1.rs2; + +define pcodeop custom2; +define pcodeop custom2.rs1; +define pcodeop custom2.rs1.rs2; +define pcodeop custom2.rd; +define pcodeop custom2.rd.rs1; +define pcodeop custom2.rd.rs1.rs2; + +define pcodeop custom3; +define pcodeop custom3.rs1; +define pcodeop custom3.rs1.rs2; +define pcodeop custom3.rd; +define pcodeop custom3.rd.rs1; +define pcodeop custom3.rd.rs1.rs2; + +:custom0 is op0001=0x3 & op0204=0x2 & op0506=0x0 & op1214=0x0 +{ + custom0(); +} + +:custom0.rs1 rs1 is op0001=0x3 & op0204=0x2 & op0506=0x0 & op1214=0x2 & rs1 +{ + custom0.rs1(rs1); +} + +:custom0.rs1.rs2 rs1,rs2 is op0001=0x3 & op0204=0x2 & op0506=0x0 & op1214=0x3 & rs1 & rs2 +{ + custom0.rs1.rs2(rs1, rs2); +} + +:custom0.rd rd is op0001=0x3 & op0204=0x2 & op0506=0x0 & op1214=0x4 & rd +{ + rd = custom0.rd(); +} + +:custom0.rd.rs1 rd,rs1 is op0001=0x3 & op0204=0x2 & op0506=0x0 & op1214=0x6 & rd & rs1 +{ + rd = custom0.rd.rs1(rs1); +} + +:custom0.rd.rs1.rs2 rd,rs1,rs2 is op0001=0x3 & op0204=0x2 & op0506=0x0 & op1214=0x7 & rd & rs1 & rs2 +{ + rd = custom0.rd.rs1.rs2(rs1, rs2); +} + + +:custom1 is op0001=0x3 & op0204=0x2 & op0506=0x1 & op1214=0x0 +{ + custom1(); +} + +:custom1.rs1 rs1 is op0001=0x3 & op0204=0x2 & op0506=0x1 & op1214=0x2 & rs1 +{ + custom1.rs1(rs1); +} + +:custom1.rs1.rs2 rs1,rs2 is op0001=0x3 & op0204=0x2 & op0506=0x1 & op1214=0x3 & rs1 & rs2 +{ + custom1.rs1.rs2(rs1, rs2); +} + +:custom1.rd rd is op0001=0x3 & op0204=0x2 & op0506=0x1 & op1214=0x4 & rd +{ + rd = custom1.rd(); +} + +:custom1.rd.rs1 rd,rs1 is op0001=0x3 & op0204=0x2 & op0506=0x1 & op1214=0x6 & rd & rs1 +{ + rd = custom1.rd.rs1(rs1); +} + +:custom1.rd.rs1.rs2 rd,rs1,rs2 is op0001=0x3 & op0204=0x2 & op0506=0x1 & op1214=0x7 & rd & rs1 & rs2 +{ + rd = custom1.rd.rs1.rs2(rs1, rs2); +} + + +#TODO handle RV128 for custom-2/custom-3 + +:custom2 is op0001=0x3 & op0204=0x6 & op0506=0x2 & op1214=0x0 +{ + custom2(); +} + +:custom2.rs1 rs1 is op0001=0x3 & op0204=0x6 & op0506=0x2 & op1214=0x2 & rs1 +{ + custom2.rs1(rs1); +} + +:custom2.rs1.rs2 rs1,rs2 is op0001=0x3 & op0204=0x6 & op0506=0x2 & op1214=0x3 & rs1 & rs2 +{ + custom2.rs1.rs2(rs1, rs2); +} + +:custom2.rd rd is op0001=0x3 & op0204=0x6 & op0506=0x2 & op1214=0x4 & rd +{ + rd = custom2.rd(); +} + +:custom2.rd.rs1 rd,rs1 is op0001=0x3 & op0204=0x6 & op0506=0x2 & op1214=0x6 & rd & rs1 +{ + rd = custom2.rd.rs1(rs1); +} + +:custom2.rd.rs1.rs2 rd,rs1,rs2 is op0001=0x3 & op0204=0x6 & op0506=0x2 & op1214=0x7 & rd & rs1 & rs2 +{ + rd = custom2.rd.rs1.rs2(rs1, rs2); +} + + +:custom3 is op0001=0x3 & op0204=0x6 & op0506=0x3 & op1214=0x0 +{ + custom3(); +} + +:custom3.rs1 rs1 is op0001=0x3 & op0204=0x6 & op0506=0x3 & op1214=0x2 & rs1 +{ + custom3.rs1(rs1); +} + +:custom3.rs1.rs2 rs1,rs2 is op0001=0x3 & op0204=0x6 & op0506=0x3 & op1214=0x3 & rs1 & rs2 +{ + custom3.rs1.rs2(rs1, rs2); +} + +:custom3.rd rd is op0001=0x3 & op0204=0x6 & op0506=0x3 & op1214=0x4 & rd +{ + rd = custom3.rd(); +} + +:custom3.rd.rs1 rd,rs1 is op0001=0x3 & op0204=0x6 & op0506=0x3 & op1214=0x6 & rd & rs1 +{ + rd = custom3.rd.rs1(rs1); +} + +:custom3.rd.rs1.rs2 rd,rs1,rs2 is op0001=0x3 & op0204=0x6 & op0506=0x3 & op1214=0x7 & rd & rs1 & rs2 +{ + rd = custom3.rd.rs1.rs2(rs1, rs2); +} + diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.ilp32d.slaspec b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.ilp32d.slaspec new file mode 100644 index 0000000..81dbf05 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.ilp32d.slaspec @@ -0,0 +1,15 @@ +define endian=little; + +@define XLEN 4 +@define XLEN2 8 +@define FLEN 8 + +@define MXLEN_1 31 +@define MXLEN_2 30 + +@define ADDRSIZE "32" +@define FPSIZE "64" + +@include "riscv.reg.sinc" +@include "riscv.table.sinc" +@include "riscv.instr.sinc" diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.instr.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.instr.sinc new file mode 100644 index 0000000..743bdba --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.instr.sinc @@ -0,0 +1,1051 @@ +# This is just a top level to include the standards + +@if ADDRSIZE == "32" || ADDRSIZE == "64" || ADDRSIZE == "128" +@include "riscv.rv32i.sinc" +@include "riscv.rv32a.sinc" +@include "riscv.rv32m.sinc" +@include "riscv.rv32b.sinc" +@include "riscv.rv32p.sinc" +@include "riscv.rv32k.sinc" + +@if FPSIZE == "32" || FPSIZE == "64" || FPSIZE == "128" +@include "riscv.rv32f.sinc" +@endif + +@if FPSIZE == "64" || FPSIZE == "128" +@include "riscv.rv32d.sinc" +@endif + +@if FPSIZE == "128" +@include "riscv.rv32q.sinc" +@endif +@endif + +@if ADDRSIZE == "64" || ADDRSIZE == "128" +@include "riscv.rv64i.sinc" +@include "riscv.rv64a.sinc" +@include "riscv.rv64m.sinc" +@include "riscv.rv64b.sinc" +@include "riscv.rv64p.sinc" +@include "riscv.rv64k.sinc" + +@if FPSIZE == "32" || FPSIZE == "64" || FPSIZE == "128" +@include "riscv.rv64f.sinc" +@endif + +@if FPSIZE == "64" || FPSIZE == "128" +@include "riscv.rv64d.sinc" +@endif + +@if FPSIZE == "128" +@include "riscv.rv64q.sinc" +@endif +@endif + +@include "riscv.csr.sinc" +@include "riscv.priv.sinc" +@include "riscv.rvc.sinc" +@include "riscv.rvv.sinc" +@include "riscv.zi.sinc" + +@include "riscv.custom.sinc" + +# todos that may be possible, mostly just artifacts from my +# script to generate the initial SELIGH + + +#TODO ALIAS +# add d,CU,CV 00009002 0000f003 ALIAS (0, 0) +#:add crd,crs1,crs2 is crd & crs2 & crs1 & cop0001=0x2 & cop1315=0x4 & cop1212=0x1 +#{ +#} + +#TODO ALIAS +# add d,CV,CU 00009002 0000f003 ALIAS (0, 0) +#:add crd,crs2,crs1 is crd & crs1 & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x1 +#{ +#} + +#TODO ALIAS +# add d,CU,Co 00000001 0000e003 ALIAS (0, 0) +#:add crd,crs1,cimmI is crd & cimmI & crs1 & cop0001=0x1 & cop1315=0x0 +#{ +#} + +#TODO ALIAS +# add Ct,Cc,CK 00000000 0000e003 ALIAS (0, 0) +#:add cr0204s,sp,caddi4spnimm is caddi4spnimm & cr0204s & sp & cop0001=0x0 & cop1315=0x0 +#{ +#} + +#TODO ALIAS +# add Cc,Cc,CL 00006101 0000ef83 ALIAS (0, 0) +#TODO sp,sp,caddi16spimm caddi16spimm & sp & cop0001=0x1 & cop1315=0x3 +#:add sp,sp,caddi16spimm is caddi16spimm & sp & cop0001=0x1 & cop1315=0x3 +#{ +#} + +#TODO ALIAS +# add d,s,j 00000013 0000707f ALIAS (0, 0) +#:add rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 +#{ +#} + +#TODO ALIAS +# addi Ct,Cc,CK 00000000 0000e003 ALIAS (0, 0) +#:addi cr0204s,sp,caddi4spnimm is caddi4spnimm & cr0204s & sp & cop0001=0x0 & cop1315=0x0 +#{ +#} + +#TODO ALIAS +# addi d,CU,Cj 00000001 0000e003 ALIAS (0, 0) +#:addi crd,crs1,cimmI is crd & cimmI & crs1 & cop0001=0x1 & cop1315=0x0 +#{ +#} + +#TODO ALIAS +# addi d,CU,z 00000001 0000f07f ALIAS (0, 0) +#:addi crd,crs1,zero is crd & zero & crs1 & cop0001=0x1 & cop1315=0x0 & cop0206=0x0 & cop1212=0x0 +#{ +#} + +#TODO ALIAS +# addi Cc,Cc,CL 00006101 0000ef83 ALIAS (0, 0) +#TODO sp,sp,caddi16spimm caddi16spimm & sp & cop0001=0x1 & cop1315=0x3 +#:addi sp,sp,caddi16spimm is caddi16spimm & sp & cop0001=0x1 & cop1315=0x3 +#{ +#} + +#@if defined(RISCV64I) +#TODO ALIAS +# addiw d,CU,Co 00002001 0000e003 ALIAS (64, 0) +#TODO 32 64 +#:addiw crd,crs1,cimmI is crd & cimmI & crs1 & cop0001=0x1 & cop1315=0x1 +#{ +#} +#@endif + +#@if defined(RISCV64I) +#TODO ALIAS +# addw Cs,Cw,Ct 00009c21 0000fc63 ALIAS (64, 0) +#:addw cr0709s,cd0709s,cr0204s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x1 & cop1012=0x7 +#{ +#} +#@endif + +#@if defined(RISCV64I) +#TODO ALIAS +# addw Cs,Ct,Cw 00009c21 0000fc63 ALIAS (64, 0) +#:addw cr0709s,cr0204s,cd0709s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x1 & cop1012=0x7 +#{ +#} +#@endif + +#@if defined(RISCV64I) +#TODO ALIAS +# addw d,CU,Co 00002001 0000e003 ALIAS (64, 0) +#TODO crd,crs1,cimmI crd & cimmI & crs1 & cop0001=0x1 & cop1315=0x1 +#:addw crd,crs1,cimmI is crd & cimmI & crs1 & cop0001=0x1 & cop1315=0x1 +#{ +#} +#@endif + +#@if defined(RISCV64I) +#TODO ALIAS +# addw d,s,j 0000001b 0000707f ALIAS (64, 0) +#:addw rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x0 +#{ +#} +#@endif + +#TODO ALIAS +# and Cs,Cw,Ct 00008c61 0000fc63 ALIAS (0, 0) +#:and cr0709s,cd0709s,cr0204s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x3 & cop1012=0x3 +#{ +#} + +#TODO ALIAS +# and Cs,Ct,Cw 00008c61 0000fc63 ALIAS (0, 0) +#:and cr0709s,cr0204s,cd0709s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x3 & cop1012=0x3 +#{ +#} + +#TODO ALIAS +# and Cs,Cw,Co 00008801 0000ec03 ALIAS (0, 0) +#:and cr0709s,cd0709s,cimmI is cd0709s & cimmI & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x2 +#{ +#} + +#TODO ALIAS +# and d,s,j 00007013 0000707f ALIAS (0, 0) +#:and rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x7 +#{ +#} + +#TODO ALIAS +# andi Cs,Cw,Co 00008801 0000ec03 ALIAS (0, 0) +#:andi cr0709s,cd0709s,cimmI is cd0709s & cimmI & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x2 +#{ +#} + +#TODO ALIAS +# beq Cs,Cz,Cp 0000c001 0000e003 CONDBRANCH|ALIAS (0, 0) +#:beq cr0709s,zero,cbimm is cop0206=0 & cbimm & zero & cr0709s & cop0001=0x1 & cop1315=0x6 +#{ +#} + +#TODO ALIAS +# beqz Cs,Cp 0000c001 0000e003 CONDBRANCH|ALIAS (0, 0) +#:beqz cr0709s,cbimm is cbimm & cr0709s & cop0001=0x1 & cop1315=0x6 +#{ +#} + +#TODO ALIAS +# beqz s,p 00000063 01f0707f CONDBRANCH|ALIAS (0, 0) +#:beqz rs1,immSB is immSB & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x0 & op2024=0x0 +#{ +#} + +#TODO ALIAS +# bgez s,p 00005063 01f0707f CONDBRANCH|ALIAS (0, 0) +#:bgez rs1,immSB is immSB & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x5 & op2024=0x0 +#{ +#} + +#TODO ALIAS +# bgt t,s,p 00004063 0000707f CONDBRANCH|ALIAS (0, 0) +#:bgt rs2,rs1,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x4 +#{ +#} + +#TODO ALIAS +# bgtu t,s,p 00006063 0000707f CONDBRANCH|ALIAS (0, 0) +#:bgtu rs2,rs1,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x6 +#{ +#} + +#TODO ALIAS +# bgtz t,p 00004063 000ff07f CONDBRANCH|ALIAS (0, 0) +#:bgtz rs2,immSB is immSB & rs2 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x4 & op1519=0x0 +#{ +#} + +#TODO ALIAS +# ble t,s,p 00005063 0000707f CONDBRANCH|ALIAS (0, 0) +#:ble rs2,rs1,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x5 +#{ +#} + +#TODO ALIAS +# bleu t,s,p 00007063 0000707f CONDBRANCH|ALIAS (0, 0) +#:bleu rs2,rs1,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x7 +#{ +#} + +#TODO ALIAS +# blez t,p 00005063 000ff07f CONDBRANCH|ALIAS (0, 0) +#:blez rs2,immSB is immSB & rs2 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x5 & op1519=0x0 +#{ +#} + +#TODO ALIAS +# bltz s,p 00004063 01f0707f CONDBRANCH|ALIAS (0, 0) +#:bltz rs1,immSB is immSB & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x4 & op2024=0x0 +#{ +#} + +#TODO ALIAS +# bne Cs,Cz,Cp 0000e001 0000e003 CONDBRANCH|ALIAS (0, 0) +#:bne cr0709s,zero,cbimm is cop0206=0 & cbimm & zero & cr0709s & cop0001=0x1 & cop1315=0x7 +#{ +#} + +#TODO ALIAS +# bnez Cs,Cp 0000e001 0000e003 CONDBRANCH|ALIAS (0, 0) +#:bnez cr0709s,cbimm is cbimm & cr0709s & cop0001=0x1 & cop1315=0x7 +#{ +#} + +#TODO ALIAS +# bnez s,p 00001063 01f0707f CONDBRANCH|ALIAS (0, 0) +#:bnez rs1,immSB is immSB & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x1 & op2024=0x0 +#{ +#} + + +#@if defined(RISCV128I) +#TODO 128 +#:c.lq +#@endif + +#TODO ALIAS +# c.nop 00000001 0000ffff ALIAS (0, 0) +#:c.nop is cop0001=0x1 & cop1315=0x0 & cop0212=0x0 +#{ +#} + +#TODO ALIAS +# c.nop Cj 00000001 0000ef83 ALIAS (0, 0) +#:c.nop cimmI is cimmI & cop0001=0x1 & cop1315=0x0 & cop0711=0x0 +#{ +#} + +#TODO MACRO +# call d,c 00030000 00000015 MACRO (0, 64) + +#TODO MACRO +# call c 00008080 00000015 MACRO (0, 64) + +#TODO ALIAS +# csrc E,s 00003073 00007fff ALIAS (0, 0) +#:csrc csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x3 & op0711=0x0 +#{ +#} + +#TODO ALIAS +# csrc E,Z 00007073 00007fff ALIAS (0, 0) +#:csrc csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7 & op0711=0x0 +#{ +#} + +#TODO ALIAS +# csrci E,Z 00007073 00007fff ALIAS (0, 0) +#:csrci csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7 & op0711=0x0 +#{ +#} + +#TODO ALIAS +# csrr d,E 00002073 000ff07f ALIAS (0, 0) +#:csrr rd,csr is csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519=0x0 +#{ +#} + +#TODO ALIAS +# csrrc d,E,Z 00007073 0000707f ALIAS (0, 0) +#:csrrc rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7 +#{ +#} + +#TODO ALIAS +# csrrs d,E,Z 00006073 0000707f ALIAS (0, 0) +#:csrrs rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6 +#{ +#} + +#TODO ALIAS +# csrrw d,E,Z 00005073 0000707f ALIAS (0, 0) +#:csrrw rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 +#{ +#} + +#TODO ALIAS +# csrs E,s 00002073 00007fff ALIAS (0, 0) +#:csrs csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op0711=0x0 +#{ +#} + +#TODO ALIAS +# csrs E,Z 00006073 00007fff ALIAS (0, 0) +#:csrs csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6 & op0711=0x0 +#{ +#} + +#TODO ALIAS +# csrsi E,Z 00006073 00007fff ALIAS (0, 0) +#:csrsi csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6 & op0711=0x0 +#{ +#} + +#TODO ALIAS +# csrw E,s 00001073 00007fff ALIAS (0, 0) +#:csrw csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0 +#{ +#} + +#TODO ALIAS +# csrw E,Z 00005073 00007fff ALIAS (0, 0) +#:csrw csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op0711=0x0 +#{ +#} + +#TODO ALIAS +# csrwi E,Z 00005073 00007fff ALIAS (0, 0) +#:csrwi csr,rs1 is csr & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op0711=0x0 +#{ +#} + + + +#TODO ALIAS +# ebreak 00009002 0000ffff ALIAS (0, 0) +#:ebreak is cop0001=0x2 & cop1315=0x4 & cop0212=0x400 +#{ +#} + +#TODO ALIAS +# fabs.q D,U 26002053 fe00707f ALIAS (0, 0) +#:fabs.q fr0711,fr1519 is fr1519 & fr0711 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x13 & op2024=0x0 +#{ +#} + +#TODO ALIAS +# fence 0ff0000f ffffffff ALIAS (0, 0) +#:fence is op0001=0x3 & op0204=0x3 & op0506=0x0 & funct3=0x0 & fm=0x0 & op0711=0x0 & op1527=0x1fe0 +#{ +#} + +#TODO ALIAS +# fence.tso 8330000f ffffffff ALIAS (0, 0) +#:fence.tso is op0001=0x3 & op0204=0x3 & op0506=0x0 & funct3=0x0 & fm=0x8 & op0711=0x0 & op1527=0x660 +#{ +#} + +#TODO SEE fle.d +# fge.d d,T,S a2000053 fe00707f SIMPLE (0, 0) +# :fge.d rd,fr2024,fr1519 is fr2024 & fr1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x51 +# { +# } + +#TODO SEE fle.q +# fge.q d,T,S a6000053 fe00707f SIMPLE (0, 0) +# :fge.q rd,fr2024,fr1519 is fr2024 & fr1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x53 +# { +# } + +#TODO SEE fle.s +# fge.s d,T,S a0000053 fe00707f SIMPLE (0, 0) +# :fge.s rd,fr2024,fr1519 is fr2024 & fr1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x50 +# { +# } + +#TODO SEE flt.d +# fgt.d d,T,S a2001053 fe00707f SIMPLE (0, 0) +# :fgt.d rd,fr2024,fr1519 is fr2024 & fr1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x51 +# { +# } + +#TODO SEE flt.q +# fgt.q d,T,S a6001053 fe00707f SIMPLE (0, 0) +# :fgt.q rd,fr2024,fr1519 is fr2024 & fr1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x53 +# { +# } + +#TODO SEE flt.s +# fgt.s d,T,S a0001053 fe00707f SIMPLE (0, 0) +# :fgt.s rd,fr2024,fr1519 is fr2024 & fr1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x50 +# { +# } + +#TODO ALIAS +# fld D,Cn(Cc) 00002002 0000e003 QWORD|DREF|ALIAS (0, 8) +#TODO cfr0711,cldspimm(sp) cldspimm & cfr0711 & sp & cop0001=0x2 & cop1315=0x1 +#:fld cfr0711,cldspimm(sp) is cldspimm & cfr0711 & sp & cop0001=0x2 & cop1315=0x1 +#{ +#} + +#TODO ALIAS +# fld CD,Cl(Cs) 00002000 0000e003 QWORD|DREF|ALIAS (0, 8) +#TODO 32 64 +#:fld cfr0204s,cldimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x1 & cldimm +#{ +#} + +#TODO MACRO +# fld D,A,s 00000000 00000010 MACRO (0, 64) + +#TODO MACRO +# flq D,A,s 00000000 00000011 MACRO (0, 64) + + +#@if defined(RISCV32I) +#TODO ALIAS +# flw D,Cm(Cc) 00006002 0000e003 DWORD|DREF|ALIAD (32, 4) +#TODO cfr0711,clwspimm(sp) cfr0711 & clwspimm & sp & cop0001=0x2 & cop1315=0x3 +#:flw cfr0711,clwspimm(sp) is cfr0711 & clwspimm & sp & cop0001=0x2 & cop1315=0x3 +#{ +#} +#@endif + +#@if defined(RISCV32I) +#TODO ALIAS +# flw CD,Ck(Cs) 00006000 0000e003 DWORD|DREF|ALIAD (32, 4) +#:flw cfr0204s,clwimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x3 & clwimm +#{ +#} +#@endif + +#TODO MACRO +# flw D,A,s 00000000 0000000f MACRO (0, 64) + +#TODO ALIAS +# fmv.q D,U 26000053 fe00707f ALIAS (0, 0) +#:fmv.q fr0711,fr1519 is fr1519 & fr0711 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x13 & op2024=0x0 +#{ +#} + + +#TODO SEE fmv.w.x +# fmv.s.x D,s f0000053 fff0707f SIMPLE (0, 0) +# :fmv.s.x fr0711,rs1 is fr0711 & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x78 & op2024=0x0 +# { +# } + +#TODO SEE fmv.x.w +# fmv.x.s d,S e0000053 fff0707f SIMPLE (0, 0) +# :fmv.x.s rd,fr1519 is fr1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x70 & op2024=0x0 +# { +# } + + +#TODO ALIAS +# fneg.q D,U 26001053 fe00707f ALIAS (0, 0) +#:fneg.q fr0711,fr1519 is fr1519 & fr0711 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x13 & op2024=0x0 +#{ +#} + +#TODO SEE frcsr +# frsr d 00302073 fffff07f SIMPLE (0, 0) +# :frsr rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x60 +# { +# } + +#TODO ALIAS +# fsd CT,CN(Cc) 0000a002 0000e003 QWORD|DREF|ALIAS (0, 8) +#TODO cfr0206,csdspimm(sp) csdspimm & cfr0206 & sp & cop0001=0x2 & cop1315=0x5 +#:fsd cfr0206,csdspimm(sp) is csdspimm & cfr0206 & sp & cop0001=0x2 & cop1315=0x5 +#{ +#} + +#TODO ALIAS +# fsd CD,Cl(Cs) 0000a000 0000e003 QWORD|DREF|ALIAS (0, 8) +#TODO 32 64 +#:fsd cfr0204s,cldimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x5 & cldimm +#{ +#} + +#TODO MACRO +# fsd T,A,s 00000000 00000013 MACRO (0, 64) + +#TODO MACRO +# fsq T,A,s 00000000 00000014 MACRO (0, 64) + +#TODO SEE fscsr +# fssr s 00301073 fff07fff SIMPLE (0, 0) +# :fssr rs1 is rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0 & op2031=0x3 +# { +# } + +#TODO SEE fscsr +# fssr d,s 00301073 fff0707f SIMPLE (0, 0) +# :fssr rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x3 +# { +# } + +#@if defined(RISCV32I) +#TODO ALIAS +# fsw CT,CM(Cc) 0000e002 0000e003 DWORD|DREF|ALIAD (32, 4) +#TODO cfr0206,cswspimm(sp) cswspimm & cfr0206 & sp & cop0001=0x2 & cop1315=0x7 +#:fsw cfr0206,cswspimm(sp) is cswspimm & cfr0206 & sp & cop0001=0x2 & cop1315=0x7 +#{ +#} +#@endif + +#@if defined(RISCV32I) +#TODO ALIAS +# fsw CD,Ck(Cs) 0000e000 0000e003 DWORD|DREF|ALIAD (32, 4) +#:fsw cfr0204s,clwimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x7 & clwimm +#{ +#} +#@endif + +#TODO MACRO +# fsw T,A,s 00000000 00000012 MACRO (0, 64) + + +#TODO ALIAS +# j Ca 0000a001 0000e003 BRANCH|ALIAS (0, 0) +#:j cjimm is cjimm & cop0001=0x1 & cop1315=0x5 +#{ +#} + +#@if defined(RISCV32I) +#TODO ALIAS +# jal Ca 00002001 0000e003 JSR|ALIAS (32, 0) +#:jal cjimm is cjimm & cop0001=0x1 & cop1315=0x1 +#{ +#} +#@endif + +#TODO ALIAS +# jal a 000000ef 00000fff JSR|ALIAS (0, 0) +#:jal immUJ is immUJ & op0001=0x3 & op0204=0x3 & op0506=0x3 & op0711=0x1 +#{ +#} + +#TODO ALIAS +# jalr d 00009002 0000f07f JSR|ALIAS (0, 0) +#:jalr crd is crd & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x1 +#{ +#} + +#TODO ALIAS +# jalr s 000000e7 fff07fff JSR|ALIAS (0, 0) +#:jalr rs1 is rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x1 & op2031=0x0 +#{ +#} + +#TODO ALIAS +# jalr o(s) 000000e7 00007fff JSR|ALIAS (0, 0) +#:jalr immI(rs1) is immI & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x1 +#{ +#} + +#TODO ALIAS +# jalr s,j 000000e7 00007fff JSR|ALIAS (0, 0) +#:jalr rs1,immI is immI & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x1 +#{ +#} + +#TODO ALIAS +# jalr d,s 00000067 fff0707f JSR|ALIAS (0, 0) +#:jalr rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op2031=0x0 +#{ +#} + +#TODO SEE jalr +# jalr d,o(s) 00000067 0000707f JSR (0, 0) +# :jalr rd,immI(rs1) is immI & rs1 & rd & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 +# { +# } + +#TODO ALIAS +# jr d 00008002 0000f07f BRANCH|ALIAS (0, 0) +#:jr crd is crd & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x0 +#{ +#} + +#TODO ALIAS +# jr s,j 00000067 00007fff BRANCH|ALIAS (0, 0) +#:jr rs1,immI is immI & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0 +#{ +#} + +#TODO MACRO +# jump c,s 00000000 00000015 MACRO (0, 64) + +#TODO MACRO +# la d,B 00000000 00000000 MACRO (0, 64) + +#TODO MACRO +# la.tls.gd d,A 00000000 00000002 MACRO (0, 64) + +#TODO MACRO +# la.tls.ie d,A 00000000 00000003 MACRO (0, 64) + +#TODO MACRO +# lb d,A 00000000 00000004 MACRO (0, 64) + +#TODO MACRO +# lbu d,A 00000000 00000005 MACRO (0, 64) + +#@if defined(RISCV64I) +#TODO ALIAS +# ld d,Cn(Cc) 00006002 0000e003 QWORD|DREF|ALIAS (64, 8) +#TODO crd,cldspimm(sp) crd & cldspimm & sp & cop0001=0x2 & cop1315=0x3 +#:ld crd,cldspimm(sp) is crd & cldspimm & sp & cop0001=0x2 & cop1315=0x3 +#{ +#} +#@endif + +#@if defined(RISCV64I) +#TODO ALIAS +# ld Ct,Cl(Cs) 00006000 0000e003 QWORD|DREF|ALIAS (64, 8) +#TODO 64 128 +#:ld cr0204s,cldimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x3 & cldimm +#{ +#} +#@endif + +#@if defined(RISCV64I) +#TODO MACRO +# ld d,A 00000000 0000000a MACRO (64, 64) +#@endif + +#TODO MACRO +# lh d,A 00000000 00000006 MACRO (0, 64) + +#TODO MACRO +# lhu d,A 00000000 00000007 MACRO (0, 64) + +#TODO ALIAS +# li d,Cv 00006001 0000e003 ALIAS (0, 0) +#TODO crd,cbigimm crd & cbigimm & cop0001=0x1 & cop1315=0x3 +#:li crd,cbigimm is crd & cbigimm & cop0001=0x1 & cop1315=0x3 +#{ +#} + +#TODO ALIAS +# li d,Co 00004001 0000e003 ALIAS (0, 0) +#:li crd,cimmI is crd & cimmI & cop0001=0x1 & cop1315=0x2 +#{ +#} + +#TODO MACRO +# li d,I 00000000 00000017 MACRO (0, 64) + +#TODO MACRO +# lla d,B 00000000 00000001 MACRO (0, 64) + +#TODO ALIAS +# lui d,Cu 00006001 0000e003 ALIAS (0, 0) +#:lui crd,cbigimm is crd & cbigimm & cop0001=0x1 & cop1315=0x3 +#{ +#} + +#TODO ALIAS +# lw d,Cm(Cc) 00004002 0000e003 DWORD|DREF|ALIAD (0, 4) +#:lw crd,clwspimm(sp) is crd & sp & cop0001=0x2 & cop1315=0x2 & clwspimm +#{ +#} + +#TODO ALIAS +# lw Ct,Ck(Cs) 00004000 0000e003 DWORD|DREF|ALIAD (0, 4) +#:lw cr0204s,clwimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x2 & clwimm +#{ +#} + +#TODO MACRO +# lw d,A 00000000 00000008 MACRO (0, 64) + +#@if defined(RISCV64I) +#TODO MACRO +# lwu d,A 00000000 00000009 MACRO (64, 64) +#@endif + +#TODO ALIAS +# move d,CV 00008002 0000f003 ALIAS (0, 0) +#TODO crd,crs2 crd & crs2 & cop0001=0x2 & cop1315=0x4 +#:move crd,crs2 is crd & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x0 +#{ +#} + +#TODO ALIAS +# move d,s 00000013 fff0707f ALIAS (0, 0) +#:move rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op2031=0x0 +#{ +#} + +#TODO ALIAS +# mv d,CV 00008002 0000f003 ALIAS (0, 0) +#:mv crd,crs2 is crd & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x0 +#{ +#} + +#TODO ALIAS +# nop 00000001 0000ffff ALIAS (0, 0) +#:nop is cop0001=0x1 & cop1315=0x0 & cop0212=0x0 +#{ +#} + +#TODO ALIAS +# or Cs,Cw,Ct 00008c41 0000fc63 ALIAS (0, 0) +#:or cr0709s,cd0709s,cr0204s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x2 & cop1012=0x3 +#{ +#} + +#TODO ALIAS +# or Cs,Ct,Cw 00008c41 0000fc63 ALIAS (0, 0) +#:or cr0709s,cr0204s,cd0709s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x2 & cop1012=0x3 +#{ +#} + +#TODO ALIAS +# or d,s,j 00006013 0000707f ALIAS (0, 0) +#:or rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x6 +#{ +#} + +#TODO ALIAS +# rdcycle d c0002073 fffff07f ALIAS (0, 0) +#:rdcycle rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x18000 +#{ +#} + +#@if defined(RISCV32I) +#TODO ALIAS +# rdcycleh d c8002073 fffff07f ALIAS (32, 0) +#:rdcycleh rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x19000 +#{ +#} +#@endif + +#TODO ALIAS +# rdinstret d c0202073 fffff07f ALIAS (0, 0) +#:rdinstret rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x18040 +#{ +#} + +#@if defined(RISCV32I) +#TODO ALIAS +# rdinstreth d c8202073 fffff07f ALIAS (32, 0) +#:rdinstreth rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x19040 +#{ +#} +#@endif + +#TODO ALIAS +# rdtime d c0102073 fffff07f ALIAS (0, 0) +#:rdtime rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x18020 +#{ +#} + +#@if defined(RISCV32I) +#TODO ALIAS +# rdtimeh d c8102073 fffff07f ALIAS (32, 0) +#:rdtimeh rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x19020 +#{ +#} +#@endif + +#TODO MACRO +# sb t,A,s 00000000 0000000b MACRO (0, 64) + +#@if defined(RISCV64I) +#TODO ALIAS +# sd CV,CN(Cc) 0000e002 0000e003 QWORD|DREF|ALIAS (64, 8) +#TODO crs2,csdspimm(sp) csdspimm & crs2 & sp & cop0001=0x2 & cop1315=0x7 +#:sd crs2,csdspimm(sp) is csdspimm & crs2 & sp & cop0001=0x2 & cop1315=0x7 +#{ +#} +#@endif + +#@if defined(RISCV64I) +#TODO ALIAS +# sd Ct,Cl(Cs) 0000e000 0000e003 QWORD|DREF|ALIAS (64, 8) +#TODO 64 128 +#:sd cr0204s,cldimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x7 & cldimm +#{ +#} +#@endif + +#@if defined(RISCV64I) +#TODO MACRO +# sd t,A,s 00000000 0000000e MACRO (64, 64) +#@endif + +#TODO ALIAS +# seqz d,s 00103013 fff0707f ALIAS (0, 0) +#:seqz rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x3 & op2031=0x1 +#{ +#} + +#@if defined(RISCV64I) +#TODO ALIAS +# sext.w d,CU 00002001 0000f07f ALIAS (64, 0) +#TODO crd,crs1 crd & crs1 & cop0001=0x1 & cop1315=0x1 +#:sext.w crd,crs1 is crd & crs1 & cop0001=0x1 & cop1315=0x1 & cop0206=0x0 & cop1212=0x0 +#{ +#} +#@endif + +#@if defined(RISCV64I) +#TODO ALIAS +# sext.w d,s 0000001b fff0707f ALIAS (64, 0) +#:sext.w rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x0 & op2031=0x0 +#{ +#} +#@endif + +#TODO ALIAS +# sfence.vma 12000073 ffffffff ALIAS (0, 0) +#:sfence.vma is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x2400 +#{ +#} + +#TODO ALIAS +# sfence.vma s 12000073 fff07fff ALIAS (0, 0) +#:sfence.vma rs1 is rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031=0x120 +#{ +#} + +#TODO ALIAS +# sgt d,t,s 00002033 fe00707f ALIAS (0, 0) +#:sgt rd,rs2,rs1 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x2 & funct7=0x0 +#{ +#} + +#TODO ALIAS +# sgtu d,t,s 00003033 fe00707f ALIAS (0, 0) +#:sgtu rd,rs2,rs1 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x3 & funct7=0x0 +#{ +#} + +#TODO ALIAS +# sgtz d,t 00002033 fe0ff07f ALIAS (0, 0) +#:sgtz rd,rs2 is rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x2 & funct7=0x0 & op1519=0x0 +#{ +#} + +#TODO MACRO +# sh t,A,s 00000000 0000000c MACRO (0, 64) + +#TODO ALIAS +# sll d,CU,C> 00000002 0000e003 ALIAS (0, 0) +#:sll crd,crs1,c6imm is crd & c6imm & crs1 & cop0001=0x2 & cop1315=0x0 +#{ +#} + +#TODO ALIAS +# sll d,s,> 00001013 fc00707f ALIAS (0, 0) +#:sll rd,rs1,shamt6 is rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x1 & op2631=0x0 +#{ +#} + +#TODO ALIAS +# slli d,CU,C> 00000002 0000e003 ALIAS (0, 0) +#:slli crd,crs1,c6imm is crd & c6imm & crs1 & cop0001=0x2 & cop1315=0x0 +#{ +#} + +#@if defined(RISCV64I) +#TODO ALIAS +# sllw d,s,< 0000101b fe00707f ALIAS (64, 0) +#:sllw rd,rs1,shamt5 is rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x1 & op2531=0x0 +#{ +#} +#@endif + +#TODO ALIAS +# slt d,s,j 00002013 0000707f ALIAS (0, 0) +#:slt rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x2 +#{ +#} + +#TODO ALIAS +# sltu d,s,j 00003013 0000707f ALIAS (0, 0) +#:sltu rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x3 +#{ +#} + +#TODO ALIAS +# sltz d,s 00002033 fff0707f ALIAS (0, 0) +#:sltz rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x2 & funct7=0x0 & op2024=0x0 +#{ +#} + +#TODO ALIAS +# snez d,t 00003033 fe0ff07f ALIAS (0, 0) +#:snez rd,rs2 is rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x3 & funct7=0x0 & op1519=0x0 +#{ +#} + +#TODO ALIAS +# sra Cs,Cw,C> 00008401 0000ec03 ALIAS (0, 0) +#:sra cr0709s,cd0709s,c6imm is cd0709s & c6imm & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x1 +#{ +#} + +#TODO ALIAS +# sra d,s,> 40005013 fc00707f ALIAS (0, 0) +#:sra rd,rs1,shamt6 is rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x5 & op2631=0x10 +#{ +#} + +#TODO ALIAS +# srai Cs,Cw,C> 00008401 0000ec03 ALIAS (0, 0) +#:srai cr0709s,cd0709s,c6imm is cd0709s & c6imm & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x1 +#{ +#} + +#@if defined(RISCV64I) +#TODO ALIAS +# sraw d,s,< 4000501b fe00707f ALIAS (64, 0) +#:sraw rd,rs1,shamt5 is rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x5 & op2531=0x20 +#{ +#} +#@endif + + +#TODO ALIAS +# srl Cs,Cw,C> 00008001 0000ec03 ALIAS (0, 0) +#:srl cr0709s,cd0709s,c6imm is cd0709s & c6imm & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x0 +#{ +#} + +#TODO ALIAS +# srl d,s,> 00005013 fc00707f ALIAS (0, 0) +#:srl rd,rs1,shamt6 is rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x5 & op2631=0x0 +#{ +#} + +#TODO ALIAS +# srli Cs,Cw,C> 00008001 0000ec03 ALIAS (0, 0) +#:srli cr0709s,cd0709s,c6imm is cd0709s & c6imm & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x0 +#{ +#} + +#@if defined(RISCV64I) +#TODO ALIAS +# srlw d,s,< 0000501b fe00707f ALIAS (64, 0) +#:srlw rd,rs1,shamt5 is rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x5 & op2531=0x0 +#{ +#} +#@endif + +#TODO ALIAS +# sub Cs,Cw,Ct 00008c01 0000fc63 ALIAS (0, 0) +#:sub cr0709s,cd0709s,cr0204s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x0 & cop1012=0x3 +#{ +#} + +#@if defined(RISCV64I) +#TODO ALIAS +# subw Cs,Cw,Ct 00009c01 0000fc63 ALIAS (64, 0) +#:subw cr0709s,cd0709s,cr0204s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x0 & cop1012=0x7 +#{ +#} +#@endif + +#TODO ALIAS +# sw CV,CM(Cc) 0000c002 0000e003 DWORD|DREF|ALIAD (0, 4) +#:sw crs2,cswspimm(sp) is crs2 & sp & cop0001=0x2 & cop1315=0x6 & cswspimm +#{ +#} + +#TODO ALIAS +# sw Ct,Ck(Cs) 0000c000 0000e003 DWORD|DREF|ALIAD (0, 4) +#:sw cr0204s,clwimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x6 & clwimm +#{ +#} + +#TODO MACRO +# sw t,A,s 00000000 0000000d MACRO (0, 64) + +#TODO MACRO +# tail c 00030000 00000015 MACRO (0, 64) + +#TODO ALIAS +# unimp 00000000 0000ffff ALIAS (0, 0) +#:unimp is cop0001=0x0 & cop1315=0x0 & cop0212=0x0 +#{ +#} + + +#TODO ALIAS +# xor Cs,Cw,Ct 00008c21 0000fc63 ALIAS (0, 0) +#:xor cr0709s,cd0709s,cr0204s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x1 & cop1012=0x3 +#{ +#} + +#TODO ALIAS +# xor Cs,Ct,Cw 00008c21 0000fc63 ALIAS (0, 0) +#:xor cr0709s,cr0204s,cd0709s is cd0709s & cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x1 & cop1012=0x3 +#{ +#} + +#TODO ALIAS +# xor d,s,j 00004013 0000707f ALIAS (0, 0) +#:xor rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x4 +#{ +#} + diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.ldefs b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.ldefs new file mode 100644 index 0000000..ab3fbed --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.ldefs @@ -0,0 +1,149 @@ + + + + + + RISC-V 64 little base + + + + + + RISC-V 64 little base compressed + + + + + + RISC-V 64 little general purpose + + + + + + RISC-V 64 little general purpose compressed + + + + + + RISC-V 32 little default + + + + + + RISC-V 32 little base + + + + + + RISC-V 32 little base compressed + + + + + + RISC-V 32 little base compressed + + + + + + RISC-V 32 little general purpose + + + + + + RISC-V 32 little general purpose compressed + + + + + + RISC-V 32 little default + + + + + + diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.lp64d.slaspec b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.lp64d.slaspec new file mode 100644 index 0000000..c07b538 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.lp64d.slaspec @@ -0,0 +1,15 @@ +define endian=little; + +@define XLEN 8 +@define XLEN2 16 +@define FLEN 8 + +@define MXLEN_1 63 +@define MXLEN_2 62 + +@define ADDRSIZE "64" +@define FPSIZE "64" + +@include "riscv.reg.sinc" +@include "riscv.table.sinc" +@include "riscv.instr.sinc" diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.opinion b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.opinion new file mode 100644 index 0000000..4f550de --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.opinion @@ -0,0 +1,28 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.priv.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.priv.sinc new file mode 100644 index 0000000..818727a --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.priv.sinc @@ -0,0 +1,142 @@ +# RISC-V Privileged Instructions + +define pcodeop wfi; +define pcodeop sfence.vm; +define pcodeop sfence.vma; + +# Trap-Return + + +# dret 7b200073 ffffffff SIMPLE (0, 0) +:dret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0xf640 +{ + return [dpc]; +} + +# hret 20200073 ffffffff SIMPLE (0, 0) +# deprecated instruction in latest spec +#:hret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x4040 + +# mret 30200073 ffffffff SIMPLE (0, 0) +:mret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x6040 +{ + return [mepc]; +} + +# sret 10200073 ffffffff SIMPLE (0, 0) +:sret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x2040 +{ + return [sepc]; +} + + +# uret 00200073 ffffffff SIMPLE (0, 0) +:uret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x40 +{ + return [uepc]; +} + + +# Interrupt-Management + +# wfi 10500073 ffffffff SIMPLE (0, 0) +:wfi is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x20a0 +{ + wfi(); +} + + +# Supervisor Memory-Management + +# sfence.vm 10400073 ffffffff SIMPLE (0, 0) +:sfence.vm is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x2080 +{ + sfence.vm(); +} + +# sfence.vm s 10400073 fff07fff SIMPLE (0, 0) +:sfence.vm rs1 is rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031=0x104 +{ + sfence.vm(rs1); +} + +# sfence.vma s,t 12000073 fe007fff SIMPLE (0, 0) +:sfence.vma rs1,rs2 is rs2 & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2531=0x9 +{ + sfence.vma(rs1, rs2); +} + + + + +# Hypervisor Memory-Management +#TODO move to rv32h and rv64h? + +:hlv.b rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x30 & rs1 & rd & op2024=0x0 +{ + rd = sext(*[ram]:1 rs1); +} + +:hlv.bu rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x30 & rs1 & rd & op2024=0x1 +{ + rd = zext(*[ram]:1 rs1); +} + +:hlv.h rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x32 & rs1 & rd & op2024=0x0 +{ + rd = sext(*[ram]:2 rs1); +} + +:hlv.hu rd,rs1, is op0006=0x73 & funct3=0x4 & funct7=0x32 & rs1 & rd & op2024=0x1 +{ + rd = zext(*[ram]:2 rs1); +} + +:hlvx.hu rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x32 & rs1 & rd & op2024=0x3 +{ + rd = zext(*[ram]:2 rs1); +} + +:hlv.w rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x34 & rs1 & rd & op2024=0x0 +{ + assignW(rd, *[ram]:4 rs1); +} + +:hlvx.wu rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x34 & rs1 & rd & op2024=0x3 +{ + zassignW(rd, *[ram]:4 rs1); +} + +:hsv.b rs1,rs2 is op0006=0x73 & funct3=0x4 & funct7=0x31 & op0711=0x0 & rs1 & rs2 +{ + *[ram]:1 rs1 = rs2:1; +} + +:hsv.h rs1,rs2 is op0006=0x73 & funct3=0x4 & funct7=0x33 & op0711=0x0 & rs1 & rs2 +{ + *[ram]:2 rs1 = rs2:2; +} + +:hsv.w rs1,rs2 is op0006=0x73 & funct3=0x4 & funct7=0x35 & op0711=0x0 & rs1 & rs2 +{ + *[ram]:4 rs1 = rs2:4; +} + +@if ADDRSIZE == "64" + +:hlv.wu rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x34 & rs1 & rd & op2024=0x1 +{ + rd = zext(*[ram]:4 rs1); +} + +:hlv.d rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x36 & rs1 & rd & op2024=0x0 +{ + rd = *[ram]:8 rs1; +} + +:hsv.d rs1,rs2 is op0006=0x73 & funct3=0x4 & funct7=0x37 & op0711=0x0 & rs1 & rs2 +{ + *[ram]:8 rs1 = rs2; +} + +@endif diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.reg.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.reg.sinc new file mode 100644 index 0000000..5b09d07 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.reg.sinc @@ -0,0 +1,1373 @@ + +define alignment=2; + +define space ram type=ram_space size=$(XLEN) default; +define space register type=register_space size=4; + +define register offset=0x1000 size=$(XLEN) [ pc ]; + + +# 08-31 reserved +# 05-07 frm +# 000 - RNE - round to nearest, ties to even +# 001 - RTZ - round towards zero +# 010 - RDN - round down (towards -inf) +# 011 - RUP - round up (towards +inf) +# 100 - RMM - round to nearest, ties to max magnitude +# 101 - invalid +# 110 - invalid +# 111 - DYN - in rm field, selects dynamic rounding mode +# in rounding mode register, invalid +# 04 NV - invalid operation +# 03 DZ - divide by zero +# 02 OF - overflow +# 01 UF - underflow +# 00 NX - inexact +#define register offset=0x1008 size=4 [ fcsr ]; + +#TODO FIXME +#TODO This is really broken +#NOTE This is stolen from ppc_common, so it has something similar +define register offset=0x1010 size=$(XLEN) [ RESERVE_ADDRESS ]; +define register offset=0x1018 size=1 [ RESERVE ]; +define register offset=0x101C size=1 [ RESERVE_LENGTH ]; +#TODO FIXME + +#ATTN RV32E is the same instruction-set encoding, but only defines x0-x15 +# x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 +# z ra sp gp tp t0 t1 t2 s0 s1 a0 a1 a2 a3 a4 a5 +# x16 x17 x18 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28 x29 x30 x31 +# a6 a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6 +# register numbers 0x1000-0x101f +define register offset=0x2000 size=$(XLEN) [ zero ra sp gp tp t0 t1 t2 + s0 s1 a0 a1 a2 a3 a4 a5 + a6 a7 s2 s3 s4 s5 s6 s7 + s8 s9 s10 s11 t3 t4 t5 t6 ]; + +# register numbers 0x1020-0x103f +define register offset=0x3000 size=$(FLEN) [ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7 + fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5 + fa6 fa7 fs2 fs3 fs4 fs5 fs6 fs7 + fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ]; + +#TODO fix +@define VLEN "256" +define register offset=0x4000 size=$(VLEN) [ v0 v1 v2 v3 v4 v5 v6 v7 + v8 v9 v10 v11 v12 v13 v14 v15 + v16 v17 v18 v19 v20 v21 v22 v23 + v24 v25 v26 v27 v28 v29 v30 v31 ]; + + +define register offset=0x90000000 size=$(XLEN) [ + ustatus fflags frm fcsr uie utvec csr006 csr007 + vstart vxsat vxrm csr00b csr00c csr00d csr00e vcsr + csr010 csr011 csr012 csr013 csr014 csr015 csr016 csr017 + csr018 csr019 csr01a csr01b csr01c csr01d csr01e csr01f + csr020 csr021 csr022 csr023 csr024 csr025 csr026 csr027 + csr028 csr029 csr02a csr02b csr02c csr02d csr02e csr02f + csr030 csr031 csr032 csr033 csr034 csr035 csr036 csr037 + csr038 csr039 csr03a csr03b csr03c csr03d csr03e csr03f + uscratch uepc ucause utval uip csr045 csr046 csr047 + csr048 csr049 csr04a csr04b csr04c csr04d csr04e csr04f + csr050 csr051 csr052 csr053 csr054 csr055 csr056 csr057 + csr058 csr059 csr05a csr05b csr05c csr05d csr05e csr05f + csr060 csr061 csr062 csr063 csr064 csr065 csr066 csr067 + csr068 csr069 csr06a csr06b csr06c csr06d csr06e csr06f + csr070 csr071 csr072 csr073 csr074 csr075 csr076 csr077 + csr078 csr079 csr07a csr07b csr07c csr07d csr07e csr07f + csr080 csr081 csr082 csr083 csr084 csr085 csr086 csr087 + csr088 csr089 csr08a csr08b csr08c csr08d csr08e csr08f + csr090 csr091 csr092 csr093 csr094 csr095 csr096 csr097 + csr098 csr099 csr09a csr09b csr09c csr09d csr09e csr09f + csr0a0 csr0a1 csr0a2 csr0a3 csr0a4 csr0a5 csr0a6 csr0a7 + csr0a8 csr0a9 csr0aa csr0ab csr0ac csr0ad csr0ae csr0af + csr0b0 csr0b1 csr0b2 csr0b3 csr0b4 csr0b5 csr0b6 csr0b7 + csr0b8 csr0b9 csr0ba csr0bb csr0bc csr0bd csr0be csr0bf + csr0c0 csr0c1 csr0c2 csr0c3 csr0c4 csr0c5 csr0c6 csr0c7 + csr0c8 csr0c9 csr0ca csr0cb csr0cc csr0cd csr0ce csr0cf + csr0d0 csr0d1 csr0d2 csr0d3 csr0d4 csr0d5 csr0d6 csr0d7 + csr0d8 csr0d9 csr0da csr0db csr0dc csr0dd csr0de csr0df + csr0e0 csr0e1 csr0e2 csr0e3 csr0e4 csr0e5 csr0e6 csr0e7 + csr0e8 csr0e9 csr0ea csr0eb csr0ec csr0ed csr0ee csr0ef + csr0f0 csr0f1 csr0f2 csr0f3 csr0f4 csr0f5 csr0f6 csr0f7 + csr0f8 csr0f9 csr0fa csr0fb csr0fc csr0fd csr0fe csr0ff + sstatus csr101 sedeleg sideleg sie stvec scounteren csr107 + csr108 csr109 csr10a csr10b csr10c csr10d csr10e csr10f + csr110 csr111 csr112 csr113 csr114 csr115 csr116 csr117 + csr118 csr119 csr11a csr11b csr11c csr11d csr11e csr11f + csr120 csr121 csr122 csr123 csr124 csr125 csr126 csr127 + csr128 csr129 csr12a csr12b csr12c csr12d csr12e csr12f + csr130 csr131 csr132 csr133 csr134 csr135 csr136 csr137 + csr138 csr139 csr13a csr13b csr13c csr13d csr13e csr13f + sscratch sepc scause stval sip csr145 csr146 csr147 + csr148 csr149 csr14a csr14b csr14c csr14d csr14e csr14f + csr150 csr151 csr152 csr153 csr154 csr155 csr156 csr157 + csr158 csr159 csr15a csr15b csr15c csr15d csr15e csr15f + csr160 csr161 csr162 csr163 csr164 csr165 csr166 csr167 + csr168 csr169 csr16a csr16b csr16c csr16d csr16e csr16f + csr170 csr171 csr172 csr173 csr174 csr175 csr176 csr177 + csr178 csr179 csr17a csr17b csr17c csr17d csr17e csr17f + satp csr181 csr182 csr183 csr184 csr185 csr186 csr187 + csr188 csr189 csr18a csr18b csr18c csr18d csr18e csr18f + csr190 csr191 csr192 csr193 csr194 csr195 csr196 csr197 + csr198 csr199 csr19a csr19b csr19c csr19d csr19e csr19f + csr1a0 csr1a1 csr1a2 csr1a3 csr1a4 csr1a5 csr1a6 csr1a7 + csr1a8 csr1a9 csr1aa csr1ab csr1ac csr1ad csr1ae csr1af + csr1b0 csr1b1 csr1b2 csr1b3 csr1b4 csr1b5 csr1b6 csr1b7 + csr1b8 csr1b9 csr1ba csr1bb csr1bc csr1bd csr1be csr1bf + csr1c0 csr1c1 csr1c2 csr1c3 csr1c4 csr1c5 csr1c6 csr1c7 + csr1c8 csr1c9 csr1ca csr1cb csr1cc csr1cd csr1ce csr1cf + csr1d0 csr1d1 csr1d2 csr1d3 csr1d4 csr1d5 csr1d6 csr1d7 + csr1d8 csr1d9 csr1da csr1db csr1dc csr1dd csr1de csr1df + csr1e0 csr1e1 csr1e2 csr1e3 csr1e4 csr1e5 csr1e6 csr1e7 + csr1e8 csr1e9 csr1ea csr1eb csr1ec csr1ed csr1ee csr1ef + csr1f0 csr1f1 csr1f2 csr1f3 csr1f4 csr1f5 csr1f6 csr1f7 + csr1f8 csr1f9 csr1fa csr1fb csr1fc csr1fd csr1fe csr1ff + vsstatus csr201 csr202 csr203 vsie vstvec csr206 csr207 + csr208 csr209 csr20a csr20b csr20c csr20d csr20e csr20f + csr210 csr211 csr212 csr213 csr214 csr215 csr216 csr217 + csr218 csr219 csr21a csr21b csr21c csr21d csr21e csr21f + csr220 csr221 csr222 csr223 csr224 csr225 csr226 csr227 + csr228 csr229 csr22a csr22b csr22c csr22d csr22e csr22f + csr230 csr231 csr232 csr233 csr234 csr235 csr236 csr237 + csr238 csr239 csr23a csr23b csr23c csr23d csr23e csr23f + vsscratch vsepc vscause vstval vsip csr245 csr246 csr247 + csr248 csr249 csr24a csr24b csr24c csr24d csr24e csr24f + csr250 csr251 csr252 csr253 csr254 csr255 csr256 csr257 + csr258 csr259 csr25a csr25b csr25c csr25d csr25e csr25f + csr260 csr261 csr262 csr263 csr264 csr265 csr266 csr267 + csr268 csr269 csr26a csr26b csr26c csr26d csr26e csr26f + csr270 csr271 csr272 csr273 csr274 csr275 csr276 csr277 + csr278 csr279 csr27a csr27b csr27c csr27d csr27e csr27f + vsatp csr281 csr282 csr283 csr284 csr285 csr286 csr287 + csr288 csr289 csr28a csr28b csr28c csr28d csr28e csr28f + csr290 csr291 csr292 csr293 csr294 csr295 csr296 csr297 + csr298 csr299 csr29a csr29b csr29c csr29d csr29e csr29f + csr2a0 csr2a1 csr2a2 csr2a3 csr2a4 csr2a5 csr2a6 csr2a7 + csr2a8 csr2a9 csr2aa csr2ab csr2ac csr2ad csr2ae csr2af + csr2b0 csr2b1 csr2b2 csr2b3 csr2b4 csr2b5 csr2b6 csr2b7 + csr2b8 csr2b9 csr2ba csr2bb csr2bc csr2bd csr2be csr2bf + csr2c0 csr2c1 csr2c2 csr2c3 csr2c4 csr2c5 csr2c6 csr2c7 + csr2c8 csr2c9 csr2ca csr2cb csr2cc csr2cd csr2ce csr2cf + csr2d0 csr2d1 csr2d2 csr2d3 csr2d4 csr2d5 csr2d6 csr2d7 + csr2d8 csr2d9 csr2da csr2db csr2dc csr2dd csr2de csr2df + csr2e0 csr2e1 csr2e2 csr2e3 csr2e4 csr2e5 csr2e6 csr2e7 + csr2e8 csr2e9 csr2ea csr2eb csr2ec csr2ed csr2ee csr2ef + csr2f0 csr2f1 csr2f2 csr2f3 csr2f4 csr2f5 csr2f6 csr2f7 + csr2f8 csr2f9 csr2fa csr2fb csr2fc csr2fd csr2fe csr2ff + mstatus misa medeleg mideleg mie mtvec mcounteren csr307 + csr308 csr309 csr30a csr30b csr30c csr30d csr30e csr30f + mstatush csr311 csr312 csr313 csr314 csr315 csr316 csr317 + csr318 csr319 csr31a csr31b csr31c csr31d csr31e csr31f + mcountinhibit csr321 csr322 mhpmevent3 mhpmevent4 mhpmevent5 mhpmevent6 mhpmevent7 + mhpmevent8 mhpmevent9 mhpmevent10 mhpmevent11 mhpmevent12 mhpmevent13 mhpmevent14 mhpmevent15 + mhpmevent16 mhpmevent17 mhpmevent18 mhpmevent19 mhpmevent20 mhpmevent21 mhpmevent22 mhpmevent23 + mhpmevent24 mhpmevent25 mhpmevent26 mhpmevent27 mhpmevent28 mhpmevent29 mhpmevent30 mhpmevent31 + mscratch mepc mcause mtval mip csr345 csr346 csr347 + csr348 csr349 mtinst mtval2 csr34c csr34d csr34e csr34f + csr350 csr351 csr352 csr353 csr354 csr355 csr356 csr357 + csr358 csr359 csr35a csr35b csr35c csr35d csr35e csr35f + csr360 csr361 csr362 csr363 csr364 csr365 csr366 csr367 + csr368 csr369 csr36a csr36b csr36c csr36d csr36e csr36f + csr370 csr371 csr372 csr373 csr374 csr375 csr376 csr377 + csr378 csr379 csr37a csr37b csr37c csr37d csr37e csr37f + mbase mbound mibase mibound mdbase mdbound csr386 csr387 + csr388 csr389 csr38a csr38b csr38c csr38d csr38e csr38f + csr390 csr391 csr392 csr393 csr394 csr395 csr396 csr397 + csr398 csr399 csr39a csr39b csr39c csr39d csr39e csr39f + pmpcfg0 pmpcfg1 pmpcfg2 pmpcfg3 pmpcfg4 pmpcfg5 pmpcfg6 pmpcfg7 + pmpcfg8 pmpcfg9 pmpcfg10 pmpcfg11 pmpcfg12 pmpcfg13 pmpcfg14 pmpcfg15 + pmpaddr0 pmpaddr1 pmpaddr2 pmpaddr3 pmpaddr4 pmpaddr5 pmpaddr6 pmpaddr7 + pmpaddr8 pmpaddr9 pmpaddr10 pmpaddr11 pmpaddr12 pmpaddr13 pmpaddr14 pmpaddr15 + pmpaddr16 pmpaddr17 pmpaddr18 pmpaddr19 pmpaddr20 pmpaddr21 pmpaddr22 pmpaddr23 + pmpaddr24 pmpaddr25 pmpaddr26 pmpaddr27 pmpaddr28 pmpaddr29 pmpaddr30 pmpaddr31 + pmpaddr32 pmpaddr33 pmpaddr34 pmpaddr35 pmpaddr36 pmpaddr37 pmpaddr38 pmpaddr39 + pmpaddr40 pmpaddr41 pmpaddr42 pmpaddr43 pmpaddr44 pmpaddr45 pmpaddr46 pmpaddr47 + pmpaddr48 pmpaddr49 pmpaddr50 pmpaddr51 pmpaddr52 pmpaddr53 pmpaddr54 pmpaddr55 + pmpaddr56 pmpaddr57 pmpaddr58 pmpaddr59 pmpaddr60 pmpaddr61 pmpaddr62 pmpaddr63 + csr3f0 csr3f1 csr3f2 csr3f3 csr3f4 csr3f5 csr3f6 csr3f7 + csr3f8 csr3f9 csr3fa csr3fb csr3fc csr3fd csr3fe csr3ff + csr400 csr401 csr402 csr403 csr404 csr405 csr406 csr407 + csr408 csr409 csr40a csr40b csr40c csr40d csr40e csr40f + csr410 csr411 csr412 csr413 csr414 csr415 csr416 csr417 + csr418 csr419 csr41a csr41b csr41c csr41d csr41e csr41f + csr420 csr421 csr422 csr423 csr424 csr425 csr426 csr427 + csr428 csr429 csr42a csr42b csr42c csr42d csr42e csr42f + csr430 csr431 csr432 csr433 csr434 csr435 csr436 csr437 + csr438 csr439 csr43a csr43b csr43c csr43d csr43e csr43f + csr440 csr441 csr442 csr443 csr444 csr445 csr446 csr447 + csr448 csr449 csr44a csr44b csr44c csr44d csr44e csr44f + csr450 csr451 csr452 csr453 csr454 csr455 csr456 csr457 + csr458 csr459 csr45a csr45b csr45c csr45d csr45e csr45f + csr460 csr461 csr462 csr463 csr464 csr465 csr466 csr467 + csr468 csr469 csr46a csr46b csr46c csr46d csr46e csr46f + csr470 csr471 csr472 csr473 csr474 csr475 csr476 csr477 + csr478 csr479 csr47a csr47b csr47c csr47d csr47e csr47f + csr480 csr481 csr482 csr483 csr484 csr485 csr486 csr487 + csr488 csr489 csr48a csr48b csr48c csr48d csr48e csr48f + csr490 csr491 csr492 csr493 csr494 csr495 csr496 csr497 + csr498 csr499 csr49a csr49b csr49c csr49d csr49e csr49f + csr4a0 csr4a1 csr4a2 csr4a3 csr4a4 csr4a5 csr4a6 csr4a7 + csr4a8 csr4a9 csr4aa csr4ab csr4ac csr4ad csr4ae csr4af + csr4b0 csr4b1 csr4b2 csr4b3 csr4b4 csr4b5 csr4b6 csr4b7 + csr4b8 csr4b9 csr4ba csr4bb csr4bc csr4bd csr4be csr4bf + csr4c0 csr4c1 csr4c2 csr4c3 csr4c4 csr4c5 csr4c6 csr4c7 + csr4c8 csr4c9 csr4ca csr4cb csr4cc csr4cd csr4ce csr4cf + csr4d0 csr4d1 csr4d2 csr4d3 csr4d4 csr4d5 csr4d6 csr4d7 + csr4d8 csr4d9 csr4da csr4db csr4dc csr4dd csr4de csr4df + csr4e0 csr4e1 csr4e2 csr4e3 csr4e4 csr4e5 csr4e6 csr4e7 + csr4e8 csr4e9 csr4ea csr4eb csr4ec csr4ed csr4ee csr4ef + csr4f0 csr4f1 csr4f2 csr4f3 csr4f4 csr4f5 csr4f6 csr4f7 + csr4f8 csr4f9 csr4fa csr4fb csr4fc csr4fd csr4fe csr4ff + csr500 csr501 csr502 csr503 csr504 csr505 csr506 csr507 + csr508 csr509 csr50a csr50b csr50c csr50d csr50e csr50f + csr510 csr511 csr512 csr513 csr514 csr515 csr516 csr517 + csr518 csr519 csr51a csr51b csr51c csr51d csr51e csr51f + csr520 csr521 csr522 csr523 csr524 csr525 csr526 csr527 + csr528 csr529 csr52a csr52b csr52c csr52d csr52e csr52f + csr530 csr531 csr532 csr533 csr534 csr535 csr536 csr537 + csr538 csr539 csr53a csr53b csr53c csr53d csr53e csr53f + csr540 csr541 csr542 csr543 csr544 csr545 csr546 csr547 + csr548 csr549 csr54a csr54b csr54c csr54d csr54e csr54f + csr550 csr551 csr552 csr553 csr554 csr555 csr556 csr557 + csr558 csr559 csr55a csr55b csr55c csr55d csr55e csr55f + csr560 csr561 csr562 csr563 csr564 csr565 csr566 csr567 + csr568 csr569 csr56a csr56b csr56c csr56d csr56e csr56f + csr570 csr571 csr572 csr573 csr574 csr575 csr576 csr577 + csr578 csr579 csr57a csr57b csr57c csr57d csr57e csr57f + csr580 csr581 csr582 csr583 csr584 csr585 csr586 csr587 + csr588 csr589 csr58a csr58b csr58c csr58d csr58e csr58f + csr590 csr591 csr592 csr593 csr594 csr595 csr596 csr597 + csr598 csr599 csr59a csr59b csr59c csr59d csr59e csr59f + csr5a0 csr5a1 csr5a2 csr5a3 csr5a4 csr5a5 csr5a6 csr5a7 + scontext csr5a9 csr5aa csr5ab csr5ac csr5ad csr5ae csr5af + csr5b0 csr5b1 csr5b2 csr5b3 csr5b4 csr5b5 csr5b6 csr5b7 + csr5b8 csr5b9 csr5ba csr5bb csr5bc csr5bd csr5be csr5bf + csr5c0 csr5c1 csr5c2 csr5c3 csr5c4 csr5c5 csr5c6 csr5c7 + csr5c8 csr5c9 csr5ca csr5cb csr5cc csr5cd csr5ce csr5cf + csr5d0 csr5d1 csr5d2 csr5d3 csr5d4 csr5d5 csr5d6 csr5d7 + csr5d8 csr5d9 csr5da csr5db csr5dc csr5dd csr5de csr5df + csr5e0 csr5e1 csr5e2 csr5e3 csr5e4 csr5e5 csr5e6 csr5e7 + csr5e8 csr5e9 csr5ea csr5eb csr5ec csr5ed csr5ee csr5ef + csr5f0 csr5f1 csr5f2 csr5f3 csr5f4 csr5f5 csr5f6 csr5f7 + csr5f8 csr5f9 csr5fa csr5fb csr5fc csr5fd csr5fe csr5ff + hstatus csr601 hedeleg hideleg hie htimedelta hcounteren hgeie + csr608 csr609 csr60a csr60b csr60c csr60d csr60e csr60f + csr610 csr611 csr612 csr613 csr614 htimedeltah csr616 csr617 + csr618 csr619 csr61a csr61b csr61c csr61d csr61e csr61f + csr620 csr621 csr622 csr623 csr624 csr625 csr626 csr627 + csr628 csr629 csr62a csr62b csr62c csr62d csr62e csr62f + csr630 csr631 csr632 csr633 csr634 csr635 csr636 csr637 + csr638 csr639 csr63a csr63b csr63c csr63d csr63e csr63f + csr640 csr641 csr642 htval hip hvip csr646 csr647 + csr648 csr649 htinst csr64b csr64c csr64d csr64e csr64f + csr650 csr651 csr652 csr653 csr654 csr655 csr656 csr657 + csr658 csr659 csr65a csr65b csr65c csr65d csr65e csr65f + csr660 csr661 csr662 csr663 csr664 csr665 csr666 csr667 + csr668 csr669 csr66a csr66b csr66c csr66d csr66e csr66f + csr670 csr671 csr672 csr673 csr674 csr675 csr676 csr677 + csr678 csr679 csr67a csr67b csr67c csr67d csr67e csr67f + hgatp csr681 csr682 csr683 csr684 csr685 csr686 csr687 + csr688 csr689 csr68a csr68b csr68c csr68d csr68e csr68f + csr690 csr691 csr692 csr693 csr694 csr695 csr696 csr697 + csr698 csr699 csr69a csr69b csr69c csr69d csr69e csr69f + csr6a0 csr6a1 csr6a2 csr6a3 csr6a4 csr6a5 csr6a6 csr6a7 + hcontext csr6a9 csr6aa csr6ab csr6ac csr6ad csr6ae csr6af + csr6b0 csr6b1 csr6b2 csr6b3 csr6b4 csr6b5 csr6b6 csr6b7 + csr6b8 csr6b9 csr6ba csr6bb csr6bc csr6bd csr6be csr6bf + csr6c0 csr6c1 csr6c2 csr6c3 csr6c4 csr6c5 csr6c6 csr6c7 + csr6c8 csr6c9 csr6ca csr6cb csr6cc csr6cd csr6ce csr6cf + csr6d0 csr6d1 csr6d2 csr6d3 csr6d4 csr6d5 csr6d6 csr6d7 + csr6d8 csr6d9 csr6da csr6db csr6dc csr6dd csr6de csr6df + csr6e0 csr6e1 csr6e2 csr6e3 csr6e4 csr6e5 csr6e6 csr6e7 + csr6e8 csr6e9 csr6ea csr6eb csr6ec csr6ed csr6ee csr6ef + csr6f0 csr6f1 csr6f2 csr6f3 csr6f4 csr6f5 csr6f6 csr6f7 + csr6f8 csr6f9 csr6fa csr6fb csr6fc csr6fd csr6fe csr6ff + csr700 csr701 csr702 csr703 csr704 csr705 csr706 csr707 + csr708 csr709 csr70a csr70b csr70c csr70d csr70e csr70f + csr710 csr711 csr712 csr713 csr714 csr715 csr716 csr717 + csr718 csr719 csr71a csr71b csr71c csr71d csr71e csr71f + csr720 csr721 csr722 csr723 csr724 csr725 csr726 csr727 + csr728 csr729 csr72a csr72b csr72c csr72d csr72e csr72f + csr730 csr731 csr732 csr733 csr734 csr735 csr736 csr737 + csr738 csr739 csr73a csr73b csr73c csr73d csr73e csr73f + csr740 csr741 csr742 csr743 csr744 csr745 csr746 csr747 + csr748 csr749 csr74a csr74b csr74c csr74d csr74e csr74f + csr750 csr751 csr752 csr753 csr754 csr755 csr756 csr757 + csr758 csr759 csr75a csr75b csr75c csr75d csr75e csr75f + csr760 csr761 csr762 csr763 csr764 csr765 csr766 csr767 + csr768 csr769 csr76a csr76b csr76c csr76d csr76e csr76f + csr770 csr771 csr772 csr773 csr774 csr775 csr776 csr777 + csr778 csr779 csr77a csr77b csr77c csr77d csr77e csr77f + csr780 csr781 csr782 csr783 csr784 csr785 csr786 csr787 + csr788 csr789 csr78a csr78b csr78c csr78d csr78e csr78f + csr790 csr791 csr792 csr793 csr794 csr795 csr796 csr797 + csr798 csr799 csr79a csr79b csr79c csr79d csr79e csr79f + tselect tdata1 tdata2 tdata3 csr7a4 csr7a5 csr7a6 csr7a7 + mcontext csr7a9 csr7aa csr7ab csr7ac csr7ad csr7ae csr7af + dcsr dpc dscratch0 dscratch1 csr7b4 csr7b5 csr7b6 csr7b7 + csr7b8 csr7b9 csr7ba csr7bb csr7bc csr7bd csr7be csr7bf + csr7c0 csr7c1 csr7c2 csr7c3 csr7c4 csr7c5 csr7c6 csr7c7 + csr7c8 csr7c9 csr7ca csr7cb csr7cc csr7cd csr7ce csr7cf + csr7d0 csr7d1 csr7d2 csr7d3 csr7d4 csr7d5 csr7d6 csr7d7 + csr7d8 csr7d9 csr7da csr7db csr7dc csr7dd csr7de csr7df + csr7e0 csr7e1 csr7e2 csr7e3 csr7e4 csr7e5 csr7e6 csr7e7 + csr7e8 csr7e9 csr7ea csr7eb csr7ec csr7ed csr7ee csr7ef + csr7f0 csr7f1 csr7f2 csr7f3 csr7f4 csr7f5 csr7f6 csr7f7 + csr7f8 csr7f9 csr7fa csr7fb csr7fc csr7fd csr7fe csr7ff + csr800 csr801 csr802 csr803 csr804 csr805 csr806 csr807 + csr808 csr809 csr80a csr80b csr80c csr80d csr80e csr80f + csr810 csr811 csr812 csr813 csr814 csr815 csr816 csr817 + csr818 csr819 csr81a csr81b csr81c csr81d csr81e csr81f + csr820 csr821 csr822 csr823 csr824 csr825 csr826 csr827 + csr828 csr829 csr82a csr82b csr82c csr82d csr82e csr82f + csr830 csr831 csr832 csr833 csr834 csr835 csr836 csr837 + csr838 csr839 csr83a csr83b csr83c csr83d csr83e csr83f + csr840 csr841 csr842 csr843 csr844 csr845 csr846 csr847 + csr848 csr849 csr84a csr84b csr84c csr84d csr84e csr84f + csr850 csr851 csr852 csr853 csr854 csr855 csr856 csr857 + csr858 csr859 csr85a csr85b csr85c csr85d csr85e csr85f + csr860 csr861 csr862 csr863 csr864 csr865 csr866 csr867 + csr868 csr869 csr86a csr86b csr86c csr86d csr86e csr86f + csr870 csr871 csr872 csr873 csr874 csr875 csr876 csr877 + csr878 csr879 csr87a csr87b csr87c csr87d csr87e csr87f + csr880 csr881 csr882 csr883 csr884 csr885 csr886 csr887 + csr888 csr889 csr88a csr88b csr88c csr88d csr88e csr88f + csr890 csr891 csr892 csr893 csr894 csr895 csr896 csr897 + csr898 csr899 csr89a csr89b csr89c csr89d csr89e csr89f + csr8a0 csr8a1 csr8a2 csr8a3 csr8a4 csr8a5 csr8a6 csr8a7 + csr8a8 csr8a9 csr8aa csr8ab csr8ac csr8ad csr8ae csr8af + csr8b0 csr8b1 csr8b2 csr8b3 csr8b4 csr8b5 csr8b6 csr8b7 + csr8b8 csr8b9 csr8ba csr8bb csr8bc csr8bd csr8be csr8bf + csr8c0 csr8c1 csr8c2 csr8c3 csr8c4 csr8c5 csr8c6 csr8c7 + csr8c8 csr8c9 csr8ca csr8cb csr8cc csr8cd csr8ce csr8cf + csr8d0 csr8d1 csr8d2 csr8d3 csr8d4 csr8d5 csr8d6 csr8d7 + csr8d8 csr8d9 csr8da csr8db csr8dc csr8dd csr8de csr8df + csr8e0 csr8e1 csr8e2 csr8e3 csr8e4 csr8e5 csr8e6 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csreef + csref0 csref1 csref2 csref3 csref4 csref5 csref6 csref7 + csref8 csref9 csrefa csrefb csrefc csrefd csrefe csreff + csrf00 csrf01 csrf02 csrf03 csrf04 csrf05 csrf06 csrf07 + csrf08 csrf09 csrf0a csrf0b csrf0c csrf0d csrf0e csrf0f + csrf10 mvendorid marchid mimpid mhartid csrf15 csrf16 csrf17 + csrf18 csrf19 csrf1a csrf1b csrf1c csrf1d csrf1e csrf1f + csrf20 csrf21 csrf22 csrf23 csrf24 csrf25 csrf26 csrf27 + csrf28 csrf29 csrf2a csrf2b csrf2c csrf2d csrf2e csrf2f + csrf30 csrf31 csrf32 csrf33 csrf34 csrf35 csrf36 csrf37 + csrf38 csrf39 csrf3a csrf3b csrf3c csrf3d csrf3e csrf3f + csrf40 csrf41 csrf42 csrf43 csrf44 csrf45 csrf46 csrf47 + csrf48 csrf49 csrf4a csrf4b csrf4c csrf4d csrf4e csrf4f + csrf50 csrf51 csrf52 csrf53 csrf54 csrf55 csrf56 csrf57 + csrf58 csrf59 csrf5a csrf5b csrf5c csrf5d csrf5e csrf5f + csrf60 csrf61 csrf62 csrf63 csrf64 csrf65 csrf66 csrf67 + csrf68 csrf69 csrf6a csrf6b csrf6c csrf6d csrf6e csrf6f + csrf70 csrf71 csrf72 csrf73 csrf74 csrf75 csrf76 csrf77 + csrf78 csrf79 csrf7a csrf7b csrf7c csrf7d csrf7e csrf7f + csrf80 csrf81 csrf82 csrf83 csrf84 csrf85 csrf86 csrf87 + csrf88 csrf89 csrf8a csrf8b csrf8c csrf8d csrf8e csrf8f + csrf90 csrf91 csrf92 csrf93 csrf94 csrf95 csrf96 csrf97 + csrf98 csrf99 csrf9a csrf9b csrf9c csrf9d csrf9e csrf9f + csrfa0 csrfa1 csrfa2 csrfa3 csrfa4 csrfa5 csrfa6 csrfa7 + csrfa8 csrfa9 csrfaa csrfab csrfac csrfad csrfae csrfaf + csrfb0 csrfb1 csrfb2 csrfb3 csrfb4 csrfb5 csrfb6 csrfb7 + csrfb8 csrfb9 csrfba csrfbb csrfbc csrfbd csrfbe csrfbf + csrfc0 csrfc1 csrfc2 csrfc3 csrfc4 csrfc5 csrfc6 csrfc7 + csrfc8 csrfc9 csrfca csrfcb csrfcc csrfcd csrfce csrfcf + csrfd0 csrfd1 csrfd2 csrfd3 csrfd4 csrfd5 csrfd6 csrfd7 + csrfd8 csrfd9 csrfda csrfdb csrfdc csrfdd csrfde csrfdf + csrfe0 csrfe1 csrfe2 csrfe3 csrfe4 csrfe5 csrfe6 csrfe7 + csrfe8 csrfe9 csrfea csrfeb csrfec csrfed csrfee csrfef + csrff0 csrff1 csrff2 csrff3 csrff4 csrff5 csrff6 csrff7 + csrff8 csrff9 csrffa csrffb csrffc csrffd csrffe csrfff +]; + + +# SEE 3.1.1 Machine ISA Register misa +# (MXLEN-1, MXLEN-2) MXL - Machine XLEN {1: 32, 2: 64, 3: 128} +# Bit Character Description +# 0 A Atomic extension +# 1 B Tentatively reserved for Bit-Manipulation extension +# 2 C Compressed extension +# 3 D Double-precision floating-point extension +# 4 E RV32E base ISA +# 5 F Single-precision floating-point extension +# 6 G Additional standard extensions present +# 7 H Hypervisor extension +# 8 I RV32I/64I/128I base ISA +# 9 J Tentatively reserved for Dynamically Translated Languages extension +# 10 K Reserved +# 11 L Tentatively reserved for Decimal Floating-Point extension +# 12 M Integer Multiply/Divide extension +# 13 N User-level interrupts supported +# 14 O Reserved +# 15 P Tentatively reserved for Packed-SIMD extension +# 16 Q Quad-precision floating-point extension +# 17 R Reserved +# 18 S Supervisor mode implemented +# 19 T Tentatively reserved for Transactional Memory extension +# 20 U User mode implemented +# 21 V Tentatively reserved for Vector extension +# 22 W Reserved +# 23 X Non-standard extensions present +# 24 Y Reserved +# 25 Z Reserved +define context misa + RVA=(0,0) + RVB=(1,1) + RVC=(2,2) + RVD=(3,3) + RVE=(4,4) + RVF=(5,5) + RVG=(6,6) + RVH=(7,7) + RVI=(8,8) + RVJ=(9,9) + RVK=(10,10) + RVL=(11,11) + RVM=(12,12) + RVN=(13,13) + RVO=(14,14) + RVP=(15,15) + RVQ=(16,16) + RVR=(17,17) + RVS=(18,18) + RVT=(19,19) + RVU=(20,20) + RVV=(21,21) + RVW=(22,22) + RVX=(23,23) + RVY=(24,24) + RVZ=(25,25) + MXL=($(MXLEN_2), $(MXLEN_1)) +; + + +define token instr (32) + op0001=(0,1) + op0006=(0,6) + op0204=(2,4) + op0506=(5,6) + op0707=(7,7) + op0711=(7,11) + r0711=(7,11) + fr0711=(7,11) + v0711=(7,11) + op0811=(8,11) + op1214=(12,14) + funct3=(12,14) + op1219=(12,19) + op1231=(12,31) + sop1231=(12,31) signed + op1519=(15,19) + sop1519=(15,19) signed + subf5=(15,19) + r1519=(15,19) + fr1519=(15,19) + v1519=(15,19) + op1527=(15,27) + op1531=(15,31) + op2020=(20,20) + op2022=(20,22) + succ=(20,23) + op2023=(20,23) + op2024=(20,24) + r2024=(20,24) + fr2024=(20,24) + v2024=(20,24) + op2025=(20,25) + op2026=(20,26) + csr_0=(20,27) + csr_1=(20,27) + csr_2=(20,27) + csr_3=(20,27) + csr_4=(20,27) + csr_50=(20,26) + csr_58=(20,25) + csr_5C=(20,25) + csr_60=(20,26) + csr_68=(20,25) + csr_6C=(20,25) + csr_70=(20,26) + csr_78=(20,24) + csr_7A=(20,23) + csr_7B=(20,23) + csr_7C=(20,25) + csr_8=(20,27) + csr_90=(20,26) + csr_98=(20,25) + csr_9C=(20,25) + csr_A0=(20,26) + csr_A8=(20,25) + csr_AC=(20,25) + csr_B0=(20,26) + csr_B8=(20,25) + csr_BC=(20,25) + csr_C0=(20,26) + csr_C8=(20,25) + csr_CC=(20,25) + csr_D0=(20,26) + csr_D8=(20,25) + csr_DC=(20,25) + csr_E0=(20,26) + csr_E8=(20,25) + csr_EC=(20,25) + csr_F0=(20,26) + csr_F8=(20,25) + csr_FC=(20,25) + op2030=(20,30) + op2031=(20,31) + sop2031=(20,31) signed + op2121=(21,21) + op2130=(21,30) + op2222=(22,22) + op2323=(23,23) + op2324=(23,24) + op2424=(24,24) + op2427=(24,27) + pred=(24,27) + op2525=(25,25) + op2526=(25,26) + op2527=(25,27) + op2529=(25,29) + op2530=(25,30) + op2531=(25,31) + sop2531=(25,31) signed + funct7=(25,31) + wd=(26,26) + op2626=(26,26) + op2627=(26,27) + op2631=(26,31) + op2731=(27,31) + amoop=(27,31) + funct5=(27,31) + op2727=(27,27) + r2731=(27,31) + fr2731=(27,31) + op2828=(28,28) + op2829=(28,29) + fm=(28,31) + op2931=(29,31) + op3031=(30,31) + op3131=(31,31) + sop3131=(31,31) signed +; + +define token cinstr (16) + cop0001=(0,1) + cop0202=(2,2) + cop0203=(2,3) + cop0204=(2,4) + cr0204s=(2,4) + cfr0204s=(2,4) + cop0205=(2,5) + cop0206=(2,6) + cr0206=(2,6) + cfr0206=(2,6) + cop0212=(2,12) + cop0303=(3,3) + cop0304=(3,4) + cop0305=(3,5) + cop0404=(4,4) + cop0406=(4,6) + cop0505=(5,5) + cop0506=(5,6) + cop0512=(5,12) + cop0606=(6,6) + cop0707=(7,7) + cop0708=(7,8) + cop0709=(7,9) + cr0709s=(7,9) + cd0709s=(7,9) + cfr0709s=(7,9) + cop0710=(7,10) + cop0711=(7,11) + cr0711=(7,11) + cd0711=(7,11) + cfr0711=(7,11) + cop0712=(7,12) + cop0808=(8,8) + cop0909=(9,9) + cop0910=(9,10) + cop0912=(9,12) + cop1010=(10,10) + cop1011=(10,11) + cop1012=(10,12) + cop1111=(11,11) + cop1112=(11,12) + cop1212=(12,12) + scop1212=(12,12) signed + cop1315=(13,15) +; + + +attach variables [ r0711 r1519 r2024 r2731 ] + [ zero ra sp gp tp t0 t1 t2 s0 s1 a0 a1 a2 a3 a4 a5 + a6 a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6 ]; + +attach variables [ cr0206 cr0711 cd0711 ] + [ zero ra sp gp tp t0 t1 t2 s0 s1 a0 a1 a2 a3 a4 a5 + a6 a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6 ]; + +attach variables [ cr0204s cr0709s cd0709s ] + [ s0 s1 a0 a1 a2 a3 a4 a5 ]; + + +attach variables [ fr0711 fr1519 fr2024 fr2731 ] + [ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7 fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5 + fa6 fa7 fs2 fs3 fs4 fs5 fs6 fs7 fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ]; + +attach variables [ cfr0206 cfr0711 ] + [ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7 fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5 + fa6 fa7 fs2 fs3 fs4 fs5 fs6 fs7 fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ]; + +attach variables [ cfr0204s cfr0709s ] + [ fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5 ]; + + +attach variables [ v0711 v1519 v2024 ] + [ v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 + v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 ]; + + +attach variables [ csr_0 ] + [ ustatus fflags frm fcsr uie utvec csr006 csr007 + vstart vxsat vxrm csr00b csr00c csr00d csr00e vcsr + csr010 csr011 csr012 csr013 csr014 csr015 csr016 csr017 + csr018 csr019 csr01a csr01b csr01c csr01d csr01e csr01f + csr020 csr021 csr022 csr023 csr024 csr025 csr026 csr027 + csr028 csr029 csr02a csr02b csr02c csr02d csr02e csr02f + csr030 csr031 csr032 csr033 csr034 csr035 csr036 csr037 + csr038 csr039 csr03a csr03b csr03c csr03d csr03e csr03f + uscratch uepc ucause utval uip csr045 csr046 csr047 + csr048 csr049 csr04a csr04b csr04c csr04d csr04e csr04f + csr050 csr051 csr052 csr053 csr054 csr055 csr056 csr057 + csr058 csr059 csr05a csr05b csr05c csr05d csr05e csr05f + csr060 csr061 csr062 csr063 csr064 csr065 csr066 csr067 + csr068 csr069 csr06a csr06b csr06c csr06d csr06e csr06f + csr070 csr071 csr072 csr073 csr074 csr075 csr076 csr077 + csr078 csr079 csr07a csr07b csr07c csr07d csr07e csr07f + csr080 csr081 csr082 csr083 csr084 csr085 csr086 csr087 + csr088 csr089 csr08a csr08b csr08c csr08d csr08e csr08f + csr090 csr091 csr092 csr093 csr094 csr095 csr096 csr097 + csr098 csr099 csr09a csr09b csr09c csr09d csr09e csr09f + csr0a0 csr0a1 csr0a2 csr0a3 csr0a4 csr0a5 csr0a6 csr0a7 + csr0a8 csr0a9 csr0aa csr0ab csr0ac csr0ad csr0ae csr0af + csr0b0 csr0b1 csr0b2 csr0b3 csr0b4 csr0b5 csr0b6 csr0b7 + csr0b8 csr0b9 csr0ba csr0bb csr0bc csr0bd csr0be csr0bf + csr0c0 csr0c1 csr0c2 csr0c3 csr0c4 csr0c5 csr0c6 csr0c7 + csr0c8 csr0c9 csr0ca csr0cb csr0cc csr0cd csr0ce csr0cf + csr0d0 csr0d1 csr0d2 csr0d3 csr0d4 csr0d5 csr0d6 csr0d7 + csr0d8 csr0d9 csr0da csr0db csr0dc csr0dd csr0de csr0df + csr0e0 csr0e1 csr0e2 csr0e3 csr0e4 csr0e5 csr0e6 csr0e7 + csr0e8 csr0e9 csr0ea csr0eb csr0ec csr0ed csr0ee csr0ef + csr0f0 csr0f1 csr0f2 csr0f3 csr0f4 csr0f5 csr0f6 csr0f7 + csr0f8 csr0f9 csr0fa csr0fb csr0fc csr0fd csr0fe csr0ff ]; +attach variables [ csr_1 ] + [ sstatus csr101 sedeleg sideleg sie stvec scounteren csr107 + csr108 csr109 csr10a csr10b csr10c csr10d csr10e csr10f + csr110 csr111 csr112 csr113 csr114 csr115 csr116 csr117 + csr118 csr119 csr11a csr11b csr11c csr11d csr11e csr11f + csr120 csr121 csr122 csr123 csr124 csr125 csr126 csr127 + csr128 csr129 csr12a csr12b csr12c csr12d csr12e csr12f + csr130 csr131 csr132 csr133 csr134 csr135 csr136 csr137 + csr138 csr139 csr13a csr13b csr13c csr13d csr13e csr13f + sscratch sepc scause stval sip csr145 csr146 csr147 + csr148 csr149 csr14a csr14b csr14c csr14d csr14e csr14f + csr150 csr151 csr152 csr153 csr154 csr155 csr156 csr157 + csr158 csr159 csr15a csr15b csr15c csr15d csr15e csr15f + csr160 csr161 csr162 csr163 csr164 csr165 csr166 csr167 + csr168 csr169 csr16a csr16b csr16c csr16d csr16e csr16f + csr170 csr171 csr172 csr173 csr174 csr175 csr176 csr177 + csr178 csr179 csr17a csr17b csr17c csr17d csr17e csr17f + satp csr181 csr182 csr183 csr184 csr185 csr186 csr187 + csr188 csr189 csr18a csr18b csr18c csr18d csr18e csr18f + csr190 csr191 csr192 csr193 csr194 csr195 csr196 csr197 + csr198 csr199 csr19a csr19b csr19c csr19d csr19e csr19f + csr1a0 csr1a1 csr1a2 csr1a3 csr1a4 csr1a5 csr1a6 csr1a7 + csr1a8 csr1a9 csr1aa csr1ab csr1ac csr1ad csr1ae csr1af + csr1b0 csr1b1 csr1b2 csr1b3 csr1b4 csr1b5 csr1b6 csr1b7 + csr1b8 csr1b9 csr1ba csr1bb csr1bc csr1bd csr1be csr1bf + csr1c0 csr1c1 csr1c2 csr1c3 csr1c4 csr1c5 csr1c6 csr1c7 + csr1c8 csr1c9 csr1ca csr1cb csr1cc csr1cd csr1ce csr1cf + csr1d0 csr1d1 csr1d2 csr1d3 csr1d4 csr1d5 csr1d6 csr1d7 + csr1d8 csr1d9 csr1da csr1db csr1dc csr1dd csr1de csr1df + csr1e0 csr1e1 csr1e2 csr1e3 csr1e4 csr1e5 csr1e6 csr1e7 + csr1e8 csr1e9 csr1ea csr1eb csr1ec csr1ed csr1ee csr1ef + csr1f0 csr1f1 csr1f2 csr1f3 csr1f4 csr1f5 csr1f6 csr1f7 + csr1f8 csr1f9 csr1fa csr1fb csr1fc csr1fd csr1fe csr1ff ]; +attach variables [ csr_2 ] + [ vsstatus csr201 csr202 csr203 vsie vstvec csr206 csr207 + csr208 csr209 csr20a csr20b csr20c csr20d csr20e csr20f + csr210 csr211 csr212 csr213 csr214 csr215 csr216 csr217 + csr218 csr219 csr21a csr21b csr21c csr21d csr21e csr21f + csr220 csr221 csr222 csr223 csr224 csr225 csr226 csr227 + csr228 csr229 csr22a csr22b csr22c csr22d csr22e csr22f + csr230 csr231 csr232 csr233 csr234 csr235 csr236 csr237 + csr238 csr239 csr23a csr23b csr23c csr23d csr23e csr23f + vsscratch vsepc vscause vstval vsip csr245 csr246 csr247 + csr248 csr249 csr24a csr24b csr24c csr24d csr24e csr24f + csr250 csr251 csr252 csr253 csr254 csr255 csr256 csr257 + csr258 csr259 csr25a csr25b csr25c csr25d csr25e csr25f + csr260 csr261 csr262 csr263 csr264 csr265 csr266 csr267 + csr268 csr269 csr26a csr26b csr26c csr26d csr26e csr26f + csr270 csr271 csr272 csr273 csr274 csr275 csr276 csr277 + csr278 csr279 csr27a csr27b csr27c csr27d csr27e csr27f + vsatp csr281 csr282 csr283 csr284 csr285 csr286 csr287 + csr288 csr289 csr28a csr28b csr28c csr28d csr28e csr28f + csr290 csr291 csr292 csr293 csr294 csr295 csr296 csr297 + csr298 csr299 csr29a csr29b csr29c csr29d csr29e csr29f + csr2a0 csr2a1 csr2a2 csr2a3 csr2a4 csr2a5 csr2a6 csr2a7 + csr2a8 csr2a9 csr2aa csr2ab csr2ac csr2ad csr2ae csr2af + csr2b0 csr2b1 csr2b2 csr2b3 csr2b4 csr2b5 csr2b6 csr2b7 + csr2b8 csr2b9 csr2ba csr2bb csr2bc csr2bd csr2be csr2bf + csr2c0 csr2c1 csr2c2 csr2c3 csr2c4 csr2c5 csr2c6 csr2c7 + csr2c8 csr2c9 csr2ca csr2cb csr2cc csr2cd csr2ce csr2cf + csr2d0 csr2d1 csr2d2 csr2d3 csr2d4 csr2d5 csr2d6 csr2d7 + csr2d8 csr2d9 csr2da csr2db csr2dc csr2dd csr2de csr2df + csr2e0 csr2e1 csr2e2 csr2e3 csr2e4 csr2e5 csr2e6 csr2e7 + csr2e8 csr2e9 csr2ea csr2eb csr2ec csr2ed csr2ee csr2ef + csr2f0 csr2f1 csr2f2 csr2f3 csr2f4 csr2f5 csr2f6 csr2f7 + csr2f8 csr2f9 csr2fa csr2fb csr2fc csr2fd csr2fe csr2ff ]; +attach variables [ csr_3 ] + [ mstatus misa medeleg mideleg mie mtvec mcounteren csr307 + csr308 csr309 csr30a csr30b csr30c csr30d csr30e csr30f + mstatush csr311 csr312 csr313 csr314 csr315 csr316 csr317 + csr318 csr319 csr31a csr31b csr31c csr31d csr31e csr31f + mcountinhibit csr321 csr322 mhpmevent3 mhpmevent4 mhpmevent5 mhpmevent6 mhpmevent7 + mhpmevent8 mhpmevent9 mhpmevent10 mhpmevent11 mhpmevent12 mhpmevent13 mhpmevent14 mhpmevent15 + mhpmevent16 mhpmevent17 mhpmevent18 mhpmevent19 mhpmevent20 mhpmevent21 mhpmevent22 mhpmevent23 + mhpmevent24 mhpmevent25 mhpmevent26 mhpmevent27 mhpmevent28 mhpmevent29 mhpmevent30 mhpmevent31 + mscratch mepc mcause mtval mip csr345 csr346 csr347 + csr348 csr349 mtinst mtval2 csr34c csr34d csr34e csr34f + csr350 csr351 csr352 csr353 csr354 csr355 csr356 csr357 + csr358 csr359 csr35a csr35b csr35c csr35d csr35e csr35f + csr360 csr361 csr362 csr363 csr364 csr365 csr366 csr367 + csr368 csr369 csr36a csr36b csr36c csr36d csr36e csr36f + csr370 csr371 csr372 csr373 csr374 csr375 csr376 csr377 + csr378 csr379 csr37a csr37b csr37c csr37d csr37e csr37f + mbase mbound mibase mibound mdbase mdbound csr386 csr387 + csr388 csr389 csr38a csr38b csr38c csr38d csr38e csr38f + csr390 csr391 csr392 csr393 csr394 csr395 csr396 csr397 + csr398 csr399 csr39a csr39b csr39c csr39d csr39e csr39f + pmpcfg0 pmpcfg1 pmpcfg2 pmpcfg3 pmpcfg4 pmpcfg5 pmpcfg6 pmpcfg7 + pmpcfg8 pmpcfg9 pmpcfg10 pmpcfg11 pmpcfg12 pmpcfg13 pmpcfg14 pmpcfg15 + pmpaddr0 pmpaddr1 pmpaddr2 pmpaddr3 pmpaddr4 pmpaddr5 pmpaddr6 pmpaddr7 + pmpaddr8 pmpaddr9 pmpaddr10 pmpaddr11 pmpaddr12 pmpaddr13 pmpaddr14 pmpaddr15 + pmpaddr16 pmpaddr17 pmpaddr18 pmpaddr19 pmpaddr20 pmpaddr21 pmpaddr22 pmpaddr23 + pmpaddr24 pmpaddr25 pmpaddr26 pmpaddr27 pmpaddr28 pmpaddr29 pmpaddr30 pmpaddr31 + pmpaddr32 pmpaddr33 pmpaddr34 pmpaddr35 pmpaddr36 pmpaddr37 pmpaddr38 pmpaddr39 + pmpaddr40 pmpaddr41 pmpaddr42 pmpaddr43 pmpaddr44 pmpaddr45 pmpaddr46 pmpaddr47 + pmpaddr48 pmpaddr49 pmpaddr50 pmpaddr51 pmpaddr52 pmpaddr53 pmpaddr54 pmpaddr55 + pmpaddr56 pmpaddr57 pmpaddr58 pmpaddr59 pmpaddr60 pmpaddr61 pmpaddr62 pmpaddr63 + csr3f0 csr3f1 csr3f2 csr3f3 csr3f4 csr3f5 csr3f6 csr3f7 + csr3f8 csr3f9 csr3fa csr3fb csr3fc csr3fd csr3fe csr3ff ]; +attach variables [ csr_4 ] + [ csr400 csr401 csr402 csr403 csr404 csr405 csr406 csr407 + csr408 csr409 csr40a csr40b csr40c csr40d csr40e csr40f + csr410 csr411 csr412 csr413 csr414 csr415 csr416 csr417 + csr418 csr419 csr41a csr41b csr41c csr41d csr41e csr41f + csr420 csr421 csr422 csr423 csr424 csr425 csr426 csr427 + csr428 csr429 csr42a csr42b csr42c csr42d csr42e csr42f + csr430 csr431 csr432 csr433 csr434 csr435 csr436 csr437 + csr438 csr439 csr43a csr43b csr43c csr43d csr43e csr43f + csr440 csr441 csr442 csr443 csr444 csr445 csr446 csr447 + csr448 csr449 csr44a csr44b csr44c csr44d csr44e csr44f + csr450 csr451 csr452 csr453 csr454 csr455 csr456 csr457 + csr458 csr459 csr45a csr45b csr45c csr45d csr45e csr45f + csr460 csr461 csr462 csr463 csr464 csr465 csr466 csr467 + csr468 csr469 csr46a csr46b csr46c csr46d csr46e csr46f + csr470 csr471 csr472 csr473 csr474 csr475 csr476 csr477 + csr478 csr479 csr47a csr47b csr47c csr47d csr47e csr47f + csr480 csr481 csr482 csr483 csr484 csr485 csr486 csr487 + csr488 csr489 csr48a csr48b csr48c csr48d csr48e csr48f + csr490 csr491 csr492 csr493 csr494 csr495 csr496 csr497 + csr498 csr499 csr49a csr49b csr49c csr49d csr49e csr49f + csr4a0 csr4a1 csr4a2 csr4a3 csr4a4 csr4a5 csr4a6 csr4a7 + csr4a8 csr4a9 csr4aa csr4ab csr4ac csr4ad csr4ae csr4af + csr4b0 csr4b1 csr4b2 csr4b3 csr4b4 csr4b5 csr4b6 csr4b7 + csr4b8 csr4b9 csr4ba csr4bb csr4bc csr4bd csr4be csr4bf + csr4c0 csr4c1 csr4c2 csr4c3 csr4c4 csr4c5 csr4c6 csr4c7 + csr4c8 csr4c9 csr4ca csr4cb csr4cc csr4cd csr4ce csr4cf + csr4d0 csr4d1 csr4d2 csr4d3 csr4d4 csr4d5 csr4d6 csr4d7 + csr4d8 csr4d9 csr4da csr4db csr4dc csr4dd csr4de csr4df + csr4e0 csr4e1 csr4e2 csr4e3 csr4e4 csr4e5 csr4e6 csr4e7 + csr4e8 csr4e9 csr4ea csr4eb csr4ec csr4ed csr4ee csr4ef + csr4f0 csr4f1 csr4f2 csr4f3 csr4f4 csr4f5 csr4f6 csr4f7 + csr4f8 csr4f9 csr4fa csr4fb csr4fc csr4fd csr4fe csr4ff ]; +attach variables [ csr_50 ] + [ csr500 csr501 csr502 csr503 csr504 csr505 csr506 csr507 + csr508 csr509 csr50a csr50b csr50c csr50d csr50e csr50f + csr510 csr511 csr512 csr513 csr514 csr515 csr516 csr517 + csr518 csr519 csr51a csr51b csr51c csr51d csr51e csr51f + csr520 csr521 csr522 csr523 csr524 csr525 csr526 csr527 + csr528 csr529 csr52a csr52b csr52c csr52d csr52e csr52f + csr530 csr531 csr532 csr533 csr534 csr535 csr536 csr537 + csr538 csr539 csr53a csr53b csr53c csr53d csr53e csr53f + csr540 csr541 csr542 csr543 csr544 csr545 csr546 csr547 + csr548 csr549 csr54a csr54b csr54c csr54d csr54e csr54f + csr550 csr551 csr552 csr553 csr554 csr555 csr556 csr557 + csr558 csr559 csr55a csr55b csr55c csr55d csr55e csr55f + csr560 csr561 csr562 csr563 csr564 csr565 csr566 csr567 + csr568 csr569 csr56a csr56b csr56c csr56d csr56e csr56f + csr570 csr571 csr572 csr573 csr574 csr575 csr576 csr577 + csr578 csr579 csr57a csr57b csr57c csr57d csr57e csr57f ]; +attach variables [ csr_58 ] + [ csr580 csr581 csr582 csr583 csr584 csr585 csr586 csr587 + csr588 csr589 csr58a csr58b csr58c csr58d csr58e csr58f + csr590 csr591 csr592 csr593 csr594 csr595 csr596 csr597 + csr598 csr599 csr59a csr59b csr59c csr59d csr59e csr59f + csr5a0 csr5a1 csr5a2 csr5a3 csr5a4 csr5a5 csr5a6 csr5a7 + scontext csr5a9 csr5aa csr5ab csr5ac csr5ad csr5ae csr5af + csr5b0 csr5b1 csr5b2 csr5b3 csr5b4 csr5b5 csr5b6 csr5b7 + csr5b8 csr5b9 csr5ba csr5bb csr5bc csr5bd csr5be csr5bf ]; +attach variables [ csr_5C ] + [ csr5c0 csr5c1 csr5c2 csr5c3 csr5c4 csr5c5 csr5c6 csr5c7 + csr5c8 csr5c9 csr5ca csr5cb csr5cc csr5cd csr5ce csr5cf + csr5d0 csr5d1 csr5d2 csr5d3 csr5d4 csr5d5 csr5d6 csr5d7 + csr5d8 csr5d9 csr5da csr5db csr5dc csr5dd csr5de csr5df + csr5e0 csr5e1 csr5e2 csr5e3 csr5e4 csr5e5 csr5e6 csr5e7 + csr5e8 csr5e9 csr5ea csr5eb csr5ec csr5ed csr5ee csr5ef + csr5f0 csr5f1 csr5f2 csr5f3 csr5f4 csr5f5 csr5f6 csr5f7 + csr5f8 csr5f9 csr5fa csr5fb csr5fc csr5fd csr5fe csr5ff ]; +attach variables [ csr_60 ] + [ hstatus csr601 hedeleg hideleg hie htimedelta hcounteren hgeie + csr608 csr609 csr60a csr60b csr60c csr60d csr60e csr60f + csr610 csr611 csr612 csr613 csr614 htimedeltah csr616 csr617 + csr618 csr619 csr61a csr61b csr61c csr61d csr61e csr61f + csr620 csr621 csr622 csr623 csr624 csr625 csr626 csr627 + csr628 csr629 csr62a csr62b csr62c csr62d csr62e csr62f + csr630 csr631 csr632 csr633 csr634 csr635 csr636 csr637 + csr638 csr639 csr63a csr63b csr63c csr63d csr63e csr63f + csr640 csr641 csr642 htval hip hvip csr646 csr647 + csr648 csr649 htinst csr64b csr64c csr64d csr64e csr64f + csr650 csr651 csr652 csr653 csr654 csr655 csr656 csr657 + csr658 csr659 csr65a csr65b csr65c csr65d csr65e csr65f + csr660 csr661 csr662 csr663 csr664 csr665 csr666 csr667 + csr668 csr669 csr66a csr66b csr66c csr66d csr66e csr66f + csr670 csr671 csr672 csr673 csr674 csr675 csr676 csr677 + csr678 csr679 csr67a csr67b csr67c csr67d csr67e csr67f ]; +attach variables [ csr_68 ] + [ hgatp csr681 csr682 csr683 csr684 csr685 csr686 csr687 + csr688 csr689 csr68a csr68b csr68c csr68d csr68e csr68f + csr690 csr691 csr692 csr693 csr694 csr695 csr696 csr697 + csr698 csr699 csr69a csr69b csr69c csr69d csr69e csr69f + csr6a0 csr6a1 csr6a2 csr6a3 csr6a4 csr6a5 csr6a6 csr6a7 + hcontext csr6a9 csr6aa csr6ab csr6ac csr6ad csr6ae csr6af + csr6b0 csr6b1 csr6b2 csr6b3 csr6b4 csr6b5 csr6b6 csr6b7 + csr6b8 csr6b9 csr6ba csr6bb csr6bc csr6bd csr6be csr6bf ]; +attach variables [ csr_6C ] + [ csr6c0 csr6c1 csr6c2 csr6c3 csr6c4 csr6c5 csr6c6 csr6c7 + csr6c8 csr6c9 csr6ca csr6cb csr6cc csr6cd csr6ce csr6cf + csr6d0 csr6d1 csr6d2 csr6d3 csr6d4 csr6d5 csr6d6 csr6d7 + csr6d8 csr6d9 csr6da csr6db csr6dc csr6dd csr6de csr6df + csr6e0 csr6e1 csr6e2 csr6e3 csr6e4 csr6e5 csr6e6 csr6e7 + csr6e8 csr6e9 csr6ea csr6eb csr6ec csr6ed csr6ee csr6ef + csr6f0 csr6f1 csr6f2 csr6f3 csr6f4 csr6f5 csr6f6 csr6f7 + csr6f8 csr6f9 csr6fa csr6fb csr6fc csr6fd csr6fe csr6ff ]; +attach variables [ csr_70 ] + [ csr700 csr701 csr702 csr703 csr704 csr705 csr706 csr707 + csr708 csr709 csr70a csr70b csr70c csr70d csr70e csr70f + csr710 csr711 csr712 csr713 csr714 csr715 csr716 csr717 + csr718 csr719 csr71a csr71b csr71c csr71d csr71e csr71f + csr720 csr721 csr722 csr723 csr724 csr725 csr726 csr727 + csr728 csr729 csr72a csr72b csr72c csr72d csr72e csr72f + csr730 csr731 csr732 csr733 csr734 csr735 csr736 csr737 + csr738 csr739 csr73a csr73b csr73c csr73d csr73e csr73f + csr740 csr741 csr742 csr743 csr744 csr745 csr746 csr747 + csr748 csr749 csr74a csr74b csr74c csr74d csr74e csr74f + csr750 csr751 csr752 csr753 csr754 csr755 csr756 csr757 + csr758 csr759 csr75a csr75b csr75c csr75d csr75e csr75f + csr760 csr761 csr762 csr763 csr764 csr765 csr766 csr767 + csr768 csr769 csr76a csr76b csr76c csr76d csr76e csr76f + csr770 csr771 csr772 csr773 csr774 csr775 csr776 csr777 + csr778 csr779 csr77a csr77b csr77c csr77d csr77e csr77f ]; +attach variables [ csr_78 ] + [ csr780 csr781 csr782 csr783 csr784 csr785 csr786 csr787 + csr788 csr789 csr78a csr78b csr78c csr78d csr78e csr78f + csr790 csr791 csr792 csr793 csr794 csr795 csr796 csr797 + csr798 csr799 csr79a csr79b csr79c csr79d csr79e csr79f ]; +attach variables [ csr_7A ] + [ tselect tdata1 tdata2 tdata3 csr7a4 csr7a5 csr7a6 csr7a7 + mcontext csr7a9 csr7aa csr7ab csr7ac csr7ad csr7ae csr7af ]; +attach variables [ csr_7B ] + [ dcsr dpc dscratch0 dscratch1 csr7b4 csr7b5 csr7b6 csr7b7 + csr7b8 csr7b9 csr7ba csr7bb csr7bc csr7bd csr7be csr7bf ]; +attach variables [ csr_7C ] + [ csr7c0 csr7c1 csr7c2 csr7c3 csr7c4 csr7c5 csr7c6 csr7c7 + csr7c8 csr7c9 csr7ca csr7cb csr7cc csr7cd csr7ce csr7cf + csr7d0 csr7d1 csr7d2 csr7d3 csr7d4 csr7d5 csr7d6 csr7d7 + csr7d8 csr7d9 csr7da csr7db csr7dc csr7dd csr7de csr7df + csr7e0 csr7e1 csr7e2 csr7e3 csr7e4 csr7e5 csr7e6 csr7e7 + csr7e8 csr7e9 csr7ea csr7eb csr7ec csr7ed csr7ee csr7ef + csr7f0 csr7f1 csr7f2 csr7f3 csr7f4 csr7f5 csr7f6 csr7f7 + csr7f8 csr7f9 csr7fa csr7fb csr7fc csr7fd csr7fe csr7ff ]; +attach variables [ csr_8 ] + [ csr800 csr801 csr802 csr803 csr804 csr805 csr806 csr807 + csr808 csr809 csr80a csr80b csr80c csr80d csr80e csr80f + csr810 csr811 csr812 csr813 csr814 csr815 csr816 csr817 + csr818 csr819 csr81a csr81b csr81c csr81d csr81e csr81f + csr820 csr821 csr822 csr823 csr824 csr825 csr826 csr827 + csr828 csr829 csr82a csr82b csr82c csr82d csr82e csr82f + csr830 csr831 csr832 csr833 csr834 csr835 csr836 csr837 + csr838 csr839 csr83a csr83b csr83c csr83d csr83e csr83f + csr840 csr841 csr842 csr843 csr844 csr845 csr846 csr847 + csr848 csr849 csr84a csr84b csr84c csr84d csr84e csr84f + csr850 csr851 csr852 csr853 csr854 csr855 csr856 csr857 + csr858 csr859 csr85a csr85b csr85c csr85d csr85e csr85f + csr860 csr861 csr862 csr863 csr864 csr865 csr866 csr867 + csr868 csr869 csr86a csr86b csr86c csr86d csr86e csr86f + csr870 csr871 csr872 csr873 csr874 csr875 csr876 csr877 + csr878 csr879 csr87a csr87b csr87c csr87d csr87e csr87f + csr880 csr881 csr882 csr883 csr884 csr885 csr886 csr887 + csr888 csr889 csr88a csr88b csr88c csr88d csr88e csr88f + csr890 csr891 csr892 csr893 csr894 csr895 csr896 csr897 + csr898 csr899 csr89a csr89b csr89c csr89d csr89e csr89f + csr8a0 csr8a1 csr8a2 csr8a3 csr8a4 csr8a5 csr8a6 csr8a7 + csr8a8 csr8a9 csr8aa csr8ab csr8ac csr8ad csr8ae csr8af + csr8b0 csr8b1 csr8b2 csr8b3 csr8b4 csr8b5 csr8b6 csr8b7 + csr8b8 csr8b9 csr8ba csr8bb csr8bc csr8bd csr8be csr8bf + csr8c0 csr8c1 csr8c2 csr8c3 csr8c4 csr8c5 csr8c6 csr8c7 + csr8c8 csr8c9 csr8ca csr8cb csr8cc csr8cd csr8ce csr8cf + csr8d0 csr8d1 csr8d2 csr8d3 csr8d4 csr8d5 csr8d6 csr8d7 + csr8d8 csr8d9 csr8da csr8db csr8dc csr8dd csr8de csr8df + csr8e0 csr8e1 csr8e2 csr8e3 csr8e4 csr8e5 csr8e6 csr8e7 + csr8e8 csr8e9 csr8ea csr8eb csr8ec csr8ed csr8ee csr8ef + csr8f0 csr8f1 csr8f2 csr8f3 csr8f4 csr8f5 csr8f6 csr8f7 + csr8f8 csr8f9 csr8fa csr8fb csr8fc csr8fd csr8fe csr8ff ]; +attach variables [ csr_90 ] + [ csr900 csr901 csr902 csr903 csr904 csr905 csr906 csr907 + csr908 csr909 csr90a csr90b csr90c csr90d csr90e csr90f + csr910 csr911 csr912 csr913 csr914 csr915 csr916 csr917 + csr918 csr919 csr91a csr91b csr91c csr91d csr91e csr91f + csr920 csr921 csr922 csr923 csr924 csr925 csr926 csr927 + csr928 csr929 csr92a csr92b csr92c csr92d csr92e csr92f + csr930 csr931 csr932 csr933 csr934 csr935 csr936 csr937 + csr938 csr939 csr93a csr93b csr93c csr93d csr93e csr93f + csr940 csr941 csr942 csr943 csr944 csr945 csr946 csr947 + csr948 csr949 csr94a csr94b csr94c csr94d csr94e csr94f + csr950 csr951 csr952 csr953 csr954 csr955 csr956 csr957 + csr958 csr959 csr95a csr95b csr95c csr95d csr95e csr95f + csr960 csr961 csr962 csr963 csr964 csr965 csr966 csr967 + csr968 csr969 csr96a csr96b csr96c csr96d csr96e csr96f + csr970 csr971 csr972 csr973 csr974 csr975 csr976 csr977 + csr978 csr979 csr97a csr97b csr97c csr97d csr97e csr97f ]; +attach variables [ csr_98 ] + [ csr980 csr981 csr982 csr983 csr984 csr985 csr986 csr987 + csr988 csr989 csr98a csr98b csr98c csr98d csr98e csr98f + csr990 csr991 csr992 csr993 csr994 csr995 csr996 csr997 + csr998 csr999 csr99a csr99b csr99c csr99d csr99e csr99f + csr9a0 csr9a1 csr9a2 csr9a3 csr9a4 csr9a5 csr9a6 csr9a7 + csr9a8 csr9a9 csr9aa csr9ab csr9ac csr9ad csr9ae csr9af + csr9b0 csr9b1 csr9b2 csr9b3 csr9b4 csr9b5 csr9b6 csr9b7 + csr9b8 csr9b9 csr9ba csr9bb csr9bc csr9bd csr9be csr9bf ]; +attach variables [ csr_9C ] + [ csr9c0 csr9c1 csr9c2 csr9c3 csr9c4 csr9c5 csr9c6 csr9c7 + csr9c8 csr9c9 csr9ca csr9cb csr9cc csr9cd csr9ce csr9cf + csr9d0 csr9d1 csr9d2 csr9d3 csr9d4 csr9d5 csr9d6 csr9d7 + csr9d8 csr9d9 csr9da csr9db csr9dc csr9dd csr9de csr9df + csr9e0 csr9e1 csr9e2 csr9e3 csr9e4 csr9e5 csr9e6 csr9e7 + csr9e8 csr9e9 csr9ea csr9eb csr9ec csr9ed csr9ee csr9ef + csr9f0 csr9f1 csr9f2 csr9f3 csr9f4 csr9f5 csr9f6 csr9f7 + csr9f8 csr9f9 csr9fa csr9fb csr9fc csr9fd csr9fe csr9ff ]; +attach variables [ csr_A0 ] + [ csra00 csra01 csra02 csra03 csra04 csra05 csra06 csra07 + csra08 csra09 csra0a csra0b csra0c csra0d csra0e csra0f + csra10 csra11 csra12 csra13 csra14 csra15 csra16 csra17 + csra18 csra19 csra1a csra1b csra1c csra1d csra1e csra1f + csra20 csra21 csra22 csra23 csra24 csra25 csra26 csra27 + csra28 csra29 csra2a csra2b csra2c csra2d csra2e csra2f + csra30 csra31 csra32 csra33 csra34 csra35 csra36 csra37 + csra38 csra39 csra3a csra3b csra3c csra3d csra3e csra3f + csra40 csra41 csra42 csra43 csra44 csra45 csra46 csra47 + csra48 csra49 csra4a csra4b csra4c csra4d csra4e csra4f + csra50 csra51 csra52 csra53 csra54 csra55 csra56 csra57 + csra58 csra59 csra5a csra5b csra5c csra5d csra5e csra5f + csra60 csra61 csra62 csra63 csra64 csra65 csra66 csra67 + csra68 csra69 csra6a csra6b csra6c csra6d csra6e csra6f + csra70 csra71 csra72 csra73 csra74 csra75 csra76 csra77 + csra78 csra79 csra7a csra7b csra7c csra7d csra7e csra7f ]; +attach variables [ csr_A8 ] + [ csra80 csra81 csra82 csra83 csra84 csra85 csra86 csra87 + csra88 csra89 csra8a csra8b csra8c csra8d csra8e csra8f + csra90 csra91 csra92 csra93 csra94 csra95 csra96 csra97 + csra98 csra99 csra9a csra9b csra9c csra9d csra9e csra9f + csraa0 csraa1 csraa2 csraa3 csraa4 csraa5 csraa6 csraa7 + csraa8 csraa9 csraaa csraab csraac csraad csraae csraaf + csrab0 csrab1 csrab2 csrab3 csrab4 csrab5 csrab6 csrab7 + csrab8 csrab9 csraba csrabb csrabc csrabd csrabe csrabf ]; +attach variables [ csr_AC ] + [ csrac0 csrac1 csrac2 csrac3 csrac4 csrac5 csrac6 csrac7 + csrac8 csrac9 csraca csracb csracc csracd csrace csracf + csrad0 csrad1 csrad2 csrad3 csrad4 csrad5 csrad6 csrad7 + csrad8 csrad9 csrada csradb csradc csradd csrade csradf + csrae0 csrae1 csrae2 csrae3 csrae4 csrae5 csrae6 csrae7 + csrae8 csrae9 csraea csraeb csraec csraed csraee csraef + csraf0 csraf1 csraf2 csraf3 csraf4 csraf5 csraf6 csraf7 + csraf8 csraf9 csrafa csrafb csrafc csrafd csrafe csraff ]; +attach variables [ csr_B0 ] + [ mcycle csrb01 minstret mhpmcounter3 mhpmcounter4 mhpmcounter5 mhpmcounter6 mhpmcounter7 + mhpmcounter8 mhpmcounter9 mhpmcounter10 mhpmcounter11 mhpmcounter12 mhpmcounter13 mhpmcounter14 mhpmcounter15 + mhpmcounter16 mhpmcounter17 mhpmcounter18 mhpmcounter19 mhpmcounter20 mhpmcounter21 mhpmcounter22 mhpmcounter23 + mhpmcounter24 mhpmcounter25 mhpmcounter26 mhpmcounter27 mhpmcounter28 mhpmcounter29 mhpmcounter30 mhpmcounter31 + csrb20 csrb21 csrb22 csrb23 csrb24 csrb25 csrb26 csrb27 + csrb28 csrb29 csrb2a csrb2b csrb2c csrb2d csrb2e csrb2f + csrb30 csrb31 csrb32 csrb33 csrb34 csrb35 csrb36 csrb37 + csrb38 csrb39 csrb3a csrb3b csrb3c csrb3d csrb3e csrb3f + csrb40 csrb41 csrb42 csrb43 csrb44 csrb45 csrb46 csrb47 + csrb48 csrb49 csrb4a csrb4b csrb4c csrb4d csrb4e csrb4f + csrb50 csrb51 csrb52 csrb53 csrb54 csrb55 csrb56 csrb57 + csrb58 csrb59 csrb5a csrb5b csrb5c csrb5d csrb5e csrb5f + csrb60 csrb61 csrb62 csrb63 csrb64 csrb65 csrb66 csrb67 + csrb68 csrb69 csrb6a csrb6b csrb6c csrb6d csrb6e csrb6f + csrb70 csrb71 csrb72 csrb73 csrb74 csrb75 csrb76 csrb77 + csrb78 csrb79 csrb7a csrb7b csrb7c csrb7d csrb7e csrb7f ]; +attach variables [ csr_B8 ] + [ mcycleh csrb81 minstreth mhpmcounter3h mhpmcounter4h mhpmcounter5h mhpmcounter6h mhpmcounter7h + mhpmcounter8h mhpmcounter9h mhpmcounter10h mhpmcounter11h mhpmcounter12h mhpmcounter13h mhpmcounter14h mhpmcounter15h + mhpmcounter16h mhpmcounter17h mhpmcounter18h mhpmcounter19h mhpmcounter20h mhpmcounter21h mhpmcounter22h mhpmcounter23h + mhpmcounter24h mhpmcounter25h mhpmcounter26h mhpmcounter27h mhpmcounter28h mhpmcounter29h mhpmcounter30h mhpmcounter31h + csrba0 csrba1 csrba2 csrba3 csrba4 csrba5 csrba6 csrba7 + csrba8 csrba9 csrbaa csrbab csrbac csrbad csrbae csrbaf + csrbb0 csrbb1 csrbb2 csrbb3 csrbb4 csrbb5 csrbb6 csrbb7 + csrbb8 csrbb9 csrbba csrbbb csrbbc csrbbd csrbbe csrbbf ]; +attach variables [ csr_BC ] + [ csrbc0 csrbc1 csrbc2 csrbc3 csrbc4 csrbc5 csrbc6 csrbc7 + csrbc8 csrbc9 csrbca csrbcb csrbcc csrbcd csrbce csrbcf + csrbd0 csrbd1 csrbd2 csrbd3 csrbd4 csrbd5 csrbd6 csrbd7 + csrbd8 csrbd9 csrbda csrbdb csrbdc csrbdd csrbde csrbdf + csrbe0 csrbe1 csrbe2 csrbe3 csrbe4 csrbe5 csrbe6 csrbe7 + csrbe8 csrbe9 csrbea csrbeb csrbec csrbed csrbee csrbef + csrbf0 csrbf1 csrbf2 csrbf3 csrbf4 csrbf5 csrbf6 csrbf7 + csrbf8 csrbf9 csrbfa csrbfb csrbfc csrbfd csrbfe csrbff ]; +attach variables [ csr_C0 ] + [ cycle time instret hpmcounter3 hpmcounter4 hpmcounter5 hpmcounter6 hpmcounter7 + hpmcounter8 hpmcounter9 hpmcounter10 hpmcounter11 hpmcounter12 hpmcounter13 hpmcounter14 hpmcounter15 + hpmcounter16 hpmcounter17 hpmcounter18 hpmcounter19 hpmcounter20 hpmcounter21 hpmcounter22 hpmcounter23 + hpmcounter24 hpmcounter25 hpmcounter26 hpmcounter27 hpmcounter28 hpmcounter29 hpmcounter30 hpmcounter31 + vl vtype vlenb csrc23 csrc24 csrc25 csrc26 csrc27 + csrc28 csrc29 csrc2a csrc2b csrc2c csrc2d csrc2e csrc2f + csrc30 csrc31 csrc32 csrc33 csrc34 csrc35 csrc36 csrc37 + csrc38 csrc39 csrc3a csrc3b csrc3c csrc3d csrc3e csrc3f + csrc40 csrc41 csrc42 csrc43 csrc44 csrc45 csrc46 csrc47 + csrc48 csrc49 csrc4a csrc4b csrc4c csrc4d csrc4e csrc4f + csrc50 csrc51 csrc52 csrc53 csrc54 csrc55 csrc56 csrc57 + csrc58 csrc59 csrc5a csrc5b csrc5c csrc5d csrc5e csrc5f + csrc60 csrc61 csrc62 csrc63 csrc64 csrc65 csrc66 csrc67 + csrc68 csrc69 csrc6a csrc6b csrc6c csrc6d csrc6e csrc6f + csrc70 csrc71 csrc72 csrc73 csrc74 csrc75 csrc76 csrc77 + csrc78 csrc79 csrc7a csrc7b csrc7c csrc7d csrc7e csrc7f ]; +attach variables [ csr_C8 ] + [ cycleh timeh instreth hpmcounter3h hpmcounter4h hpmcounter5h hpmcounter6h hpmcounter7h + hpmcounter8h hpmcounter9h hpmcounter10h hpmcounter11h hpmcounter12h hpmcounter13h hpmcounter14h hpmcounter15h + hpmcounter16h hpmcounter17h hpmcounter18h hpmcounter19h hpmcounter20h hpmcounter21h hpmcounter22h hpmcounter23h + hpmcounter24h hpmcounter25h hpmcounter26h hpmcounter27h hpmcounter28h hpmcounter29h hpmcounter30h hpmcounter31h + csrca0 csrca1 csrca2 csrca3 csrca4 csrca5 csrca6 csrca7 + csrca8 csrca9 csrcaa csrcab csrcac csrcad csrcae csrcaf + csrcb0 csrcb1 csrcb2 csrcb3 csrcb4 csrcb5 csrcb6 csrcb7 + csrcb8 csrcb9 csrcba csrcbb csrcbc csrcbd csrcbe csrcbf ]; +attach variables [ csr_CC ] + [ csrcc0 csrcc1 csrcc2 csrcc3 csrcc4 csrcc5 csrcc6 csrcc7 + csrcc8 csrcc9 csrcca csrccb csrccc csrccd csrcce csrccf + csrcd0 csrcd1 csrcd2 csrcd3 csrcd4 csrcd5 csrcd6 csrcd7 + csrcd8 csrcd9 csrcda csrcdb csrcdc csrcdd csrcde csrcdf + csrce0 csrce1 csrce2 csrce3 csrce4 csrce5 csrce6 csrce7 + csrce8 csrce9 csrcea csrceb csrcec csrced csrcee csrcef + csrcf0 csrcf1 csrcf2 csrcf3 csrcf4 csrcf5 csrcf6 csrcf7 + csrcf8 csrcf9 csrcfa csrcfb csrcfc csrcfd csrcfe csrcff ]; +attach variables [ csr_D0 ] + [ csrd00 csrd01 csrd02 csrd03 csrd04 csrd05 csrd06 csrd07 + csrd08 csrd09 csrd0a csrd0b csrd0c csrd0d csrd0e csrd0f + csrd10 csrd11 csrd12 csrd13 csrd14 csrd15 csrd16 csrd17 + csrd18 csrd19 csrd1a csrd1b csrd1c csrd1d csrd1e csrd1f + csrd20 csrd21 csrd22 csrd23 csrd24 csrd25 csrd26 csrd27 + csrd28 csrd29 csrd2a csrd2b csrd2c csrd2d csrd2e csrd2f + csrd30 csrd31 csrd32 csrd33 csrd34 csrd35 csrd36 csrd37 + csrd38 csrd39 csrd3a csrd3b csrd3c csrd3d csrd3e csrd3f + csrd40 csrd41 csrd42 csrd43 csrd44 csrd45 csrd46 csrd47 + csrd48 csrd49 csrd4a csrd4b csrd4c csrd4d csrd4e csrd4f + csrd50 csrd51 csrd52 csrd53 csrd54 csrd55 csrd56 csrd57 + csrd58 csrd59 csrd5a csrd5b csrd5c csrd5d csrd5e csrd5f + csrd60 csrd61 csrd62 csrd63 csrd64 csrd65 csrd66 csrd67 + csrd68 csrd69 csrd6a csrd6b csrd6c csrd6d csrd6e csrd6f + csrd70 csrd71 csrd72 csrd73 csrd74 csrd75 csrd76 csrd77 + csrd78 csrd79 csrd7a csrd7b csrd7c csrd7d csrd7e csrd7f ]; +attach variables [ csr_D8 ] + [ csrd80 csrd81 csrd82 csrd83 csrd84 csrd85 csrd86 csrd87 + csrd88 csrd89 csrd8a csrd8b csrd8c csrd8d csrd8e csrd8f + csrd90 csrd91 csrd92 csrd93 csrd94 csrd95 csrd96 csrd97 + csrd98 csrd99 csrd9a csrd9b csrd9c csrd9d csrd9e csrd9f + csrda0 csrda1 csrda2 csrda3 csrda4 csrda5 csrda6 csrda7 + csrda8 csrda9 csrdaa csrdab csrdac csrdad csrdae csrdaf + csrdb0 csrdb1 csrdb2 csrdb3 csrdb4 csrdb5 csrdb6 csrdb7 + csrdb8 csrdb9 csrdba csrdbb csrdbc csrdbd csrdbe csrdbf ]; +attach variables [ csr_DC ] + [ csrdc0 csrdc1 csrdc2 csrdc3 csrdc4 csrdc5 csrdc6 csrdc7 + csrdc8 csrdc9 csrdca csrdcb csrdcc csrdcd csrdce csrdcf + csrdd0 csrdd1 csrdd2 csrdd3 csrdd4 csrdd5 csrdd6 csrdd7 + csrdd8 csrdd9 csrdda csrddb csrddc csrddd csrdde csrddf + csrde0 csrde1 csrde2 csrde3 csrde4 csrde5 csrde6 csrde7 + csrde8 csrde9 csrdea csrdeb csrdec csrded csrdee csrdef + csrdf0 csrdf1 csrdf2 csrdf3 csrdf4 csrdf5 csrdf6 csrdf7 + csrdf8 csrdf9 csrdfa csrdfb csrdfc csrdfd csrdfe csrdff ]; +attach variables [ csr_E0 ] + [ csre00 csre01 csre02 csre03 csre04 csre05 csre06 csre07 + csre08 csre09 csre0a csre0b csre0c csre0d csre0e csre0f + csre10 csre11 hgeip csre13 csre14 csre15 csre16 csre17 + csre18 csre19 csre1a csre1b csre1c csre1d csre1e csre1f + csre20 csre21 csre22 csre23 csre24 csre25 csre26 csre27 + csre28 csre29 csre2a csre2b csre2c csre2d csre2e csre2f + csre30 csre31 csre32 csre33 csre34 csre35 csre36 csre37 + csre38 csre39 csre3a csre3b csre3c csre3d csre3e csre3f + csre40 csre41 csre42 csre43 csre44 csre45 csre46 csre47 + csre48 csre49 csre4a csre4b csre4c csre4d csre4e csre4f + csre50 csre51 csre52 csre53 csre54 csre55 csre56 csre57 + csre58 csre59 csre5a csre5b csre5c csre5d csre5e csre5f + csre60 csre61 csre62 csre63 csre64 csre65 csre66 csre67 + csre68 csre69 csre6a csre6b csre6c csre6d csre6e csre6f + csre70 csre71 csre72 csre73 csre74 csre75 csre76 csre77 + csre78 csre79 csre7a csre7b csre7c csre7d csre7e csre7f ]; +attach variables [ csr_E8 ] + [ csre80 csre81 csre82 csre83 csre84 csre85 csre86 csre87 + csre88 csre89 csre8a csre8b csre8c csre8d csre8e csre8f + csre90 csre91 csre92 csre93 csre94 csre95 csre96 csre97 + csre98 csre99 csre9a csre9b csre9c csre9d csre9e csre9f + csrea0 csrea1 csrea2 csrea3 csrea4 csrea5 csrea6 csrea7 + csrea8 csrea9 csreaa csreab csreac csread csreae csreaf + csreb0 csreb1 csreb2 csreb3 csreb4 csreb5 csreb6 csreb7 + csreb8 csreb9 csreba csrebb csrebc csrebd csrebe csrebf ]; +attach variables [ csr_EC ] + [ csrec0 csrec1 csrec2 csrec3 csrec4 csrec5 csrec6 csrec7 + csrec8 csrec9 csreca csrecb csrecc csrecd csrece csrecf + csred0 csred1 csred2 csred3 csred4 csred5 csred6 csred7 + csred8 csred9 csreda csredb csredc csredd csrede csredf + csree0 csree1 csree2 csree3 csree4 csree5 csree6 csree7 + csree8 csree9 csreea csreeb csreec csreed csreee csreef + csref0 csref1 csref2 csref3 csref4 csref5 csref6 csref7 + csref8 csref9 csrefa csrefb csrefc csrefd csrefe csreff ]; +attach variables [ csr_F0 ] + [ csrf00 csrf01 csrf02 csrf03 csrf04 csrf05 csrf06 csrf07 + csrf08 csrf09 csrf0a csrf0b csrf0c csrf0d csrf0e csrf0f + csrf10 mvendorid marchid mimpid mhartid csrf15 csrf16 csrf17 + csrf18 csrf19 csrf1a csrf1b csrf1c csrf1d csrf1e csrf1f + csrf20 csrf21 csrf22 csrf23 csrf24 csrf25 csrf26 csrf27 + csrf28 csrf29 csrf2a csrf2b csrf2c csrf2d csrf2e csrf2f + csrf30 csrf31 csrf32 csrf33 csrf34 csrf35 csrf36 csrf37 + csrf38 csrf39 csrf3a csrf3b csrf3c csrf3d csrf3e csrf3f + csrf40 csrf41 csrf42 csrf43 csrf44 csrf45 csrf46 csrf47 + csrf48 csrf49 csrf4a csrf4b csrf4c csrf4d csrf4e csrf4f + csrf50 csrf51 csrf52 csrf53 csrf54 csrf55 csrf56 csrf57 + csrf58 csrf59 csrf5a csrf5b csrf5c csrf5d csrf5e csrf5f + csrf60 csrf61 csrf62 csrf63 csrf64 csrf65 csrf66 csrf67 + csrf68 csrf69 csrf6a csrf6b csrf6c csrf6d csrf6e csrf6f + csrf70 csrf71 csrf72 csrf73 csrf74 csrf75 csrf76 csrf77 + csrf78 csrf79 csrf7a csrf7b csrf7c csrf7d csrf7e csrf7f ]; +attach variables [ csr_F8 ] + [ csrf80 csrf81 csrf82 csrf83 csrf84 csrf85 csrf86 csrf87 + csrf88 csrf89 csrf8a csrf8b csrf8c csrf8d csrf8e csrf8f + csrf90 csrf91 csrf92 csrf93 csrf94 csrf95 csrf96 csrf97 + csrf98 csrf99 csrf9a csrf9b csrf9c csrf9d csrf9e csrf9f + csrfa0 csrfa1 csrfa2 csrfa3 csrfa4 csrfa5 csrfa6 csrfa7 + csrfa8 csrfa9 csrfaa csrfab csrfac csrfad csrfae csrfaf + csrfb0 csrfb1 csrfb2 csrfb3 csrfb4 csrfb5 csrfb6 csrfb7 + csrfb8 csrfb9 csrfba csrfbb csrfbc csrfbd csrfbe csrfbf ]; +attach variables [ csr_FC ] + [ csrfc0 csrfc1 csrfc2 csrfc3 csrfc4 csrfc5 csrfc6 csrfc7 + csrfc8 csrfc9 csrfca csrfcb csrfcc csrfcd csrfce csrfcf + csrfd0 csrfd1 csrfd2 csrfd3 csrfd4 csrfd5 csrfd6 csrfd7 + csrfd8 csrfd9 csrfda csrfdb csrfdc csrfdd csrfde csrfdf + csrfe0 csrfe1 csrfe2 csrfe3 csrfe4 csrfe5 csrfe6 csrfe7 + csrfe8 csrfe9 csrfea csrfeb csrfec csrfed csrfee csrfef + csrff0 csrff1 csrff2 csrff3 csrff4 csrff5 csrff6 csrff7 + csrff8 csrff9 csrffa csrffb csrffc csrffd csrffe csrfff ]; diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32a.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32a.sinc new file mode 100644 index 0000000..5196042 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32a.sinc @@ -0,0 +1,132 @@ +# RV32A Standard Extension + +# amoadd.w d,t,0(s) 0000202f fe00707f DWORD|DREF (0, 4) +:amoadd.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2W; + local tmp:4 = *[ram]:4 tmprs1; + assignW(rd, tmp); + tmp = tmp + tmprs2; + *[ram]:4 tmprs1 = tmp; +} + + +# amoand.w d,t,0(s) 6000202f fe00707f DWORD|DREF (0, 4) +:amoand.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0xc & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2W; + local tmp:4 = *[ram]:4 tmprs1; + assignW(rd, tmp); + tmp = tmp & tmprs2; + *[ram]:4 tmprs1 = tmp; +} + + +# amomax.w d,t,0(s) a000202f fe00707f DWORD|DREF (0, 4) +:amomax.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x14 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2W; + local tmp:4 = *[ram]:4 tmprs1; + assignW(rd, tmp); + if (tmprs2 s<= tmp) goto inst_next; + *[ram]:4 tmprs1 = tmprs2; +} + + +# amomaxu.w d,t,0(s) e000202f fe00707f DWORD|DREF (0, 4) +:amomaxu.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x1c & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2W; + local tmp:4 = *[ram]:4 tmprs1; + assignW(rd, tmp); + if (tmprs2 <= tmp) goto inst_next; + *[ram]:4 tmprs1 = tmprs2; +} + + +# amomin.w d,t,0(s) 8000202f fe00707f DWORD|DREF (0, 4) +:amomin.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x10 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2W; + local tmp:4 = *[ram]:4 tmprs1; + assignW(rd, tmp); + if (tmprs2 s>= tmp) goto inst_next; + *[ram]:4 tmprs1 = tmprs2; +} + + +# amominu.w d,t,0(s) c000202f fe00707f DWORD|DREF (0, 4) +:amominu.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x18 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2W; + local tmp:4 = *[ram]:4 tmprs1; + assignW(rd, tmp); + if (tmprs2 >= tmp) goto inst_next; + *[ram]:4 tmprs1 = tmprs2; +} + + +# amoor.w d,t,0(s) 4000202f fe00707f DWORD|DREF (0, 4) +:amoor.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x8 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2W; + local tmp:4 = *[ram]:4 tmprs1; + assignW(rd, tmp); + tmp = tmp | tmprs2; + *[ram]:4 tmprs1 = tmp; +} + + +# amoswap.w d,t,0(s) 0800202f fe00707f DWORD|DREF (0, 4) +:amoswap.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x1 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2W; + local tmp:4 = *[ram]:4 tmprs1; + assignW(rd, tmp); + *[ram]:4 tmprs1 = tmprs2; +} + + +# amoxor.w d,t,0(s) 2000202f fe00707f DWORD|DREF (0, 4) +:amoxor.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x4 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2W; + local tmp:4 = *[ram]:4 tmprs1; + assignW(rd, tmp); + tmp = tmp ^ tmprs2; + *[ram]:4 tmprs1 = tmp; +} + + +# lr.w d,0(s) 1000202f fff0707f DWORD|DREF (0, 4) +:lr.w^aqrl rd,(rs1) is rs1 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x2 & op2024=0x0 & aqrl +{ + RESERVE_ADDRESS = rs1; + RESERVE = 1; + RESERVE_LENGTH = 4; + assignW(rd, *[ram]:4 rs1); +} + + +# sc.w d,t,0(s) 1800202f fe00707f DWORD|DREF (0, 4) +:sc.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x3 & aqrl +{ + local tmprs2 = rs2W; + local tmprs1 = rs1; + rd = 1; + if ((RESERVE == 0)||(RESERVE_ADDRESS != tmprs1)||(RESERVE_LENGTH != 4)) goto inst_next; + *[ram]:4 tmprs1 = tmprs2; + rd = 0; + RESERVE_ADDRESS = 0; + RESERVE = 0; + RESERVE_LENGTH = 0; +} diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32b.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32b.sinc new file mode 100644 index 0000000..41512c1 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32b.sinc @@ -0,0 +1,131 @@ +# RV32 Bitmanip Extension + +:andn rd, rs1, rs2 is op0006=0x33 & op1214=0x7 & op2531=0x20 & rd & rs1 & rs2 unimpl + +:bdep rd, rs1, rs2 is op0006=0x33 & op1214=0x6 & op2531=0x24 & rd & rs1 & rs2 unimpl + +:bext rd, rs1, rs2 is op0006=0x33 & op1214=0x6 & op2531=0x4 & rd & rs1 & rs2 unimpl + +:bfp rd, rs1, rs2 is op0006=0x33 & op1214=0x7 & op2531=0x24 & rd & rs1 & rs2 unimpl + +:clmul rd, rs1, rs2 is op0006=0x33 & op1214=0x1 & op2531=0x5 & rd & rs1 & rs2 unimpl + +:clmulh rd, rs1, rs2 is op0006=0x33 & op1214=0x3 & op2531=0x5 & rd & rs1 & rs2 unimpl + +:clmulr rd, rs1, rs2 is op0006=0x33 & op1214=0x2 & op2531=0x5 & rd & rs1 & rs2 unimpl + +:clz rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x0 & op2531=0x30 & rd & rs1 unimpl + +:cmix rd, rs2, rs1, rs3 is op0006=0x33 & op1214=0x1 & op2526=0x3 & rd & rs1 & rs2 & rs3 unimpl + +:cmov rd, rs2, rs1, rs3 is op0006=0x33 & op1214=0x5 & op2526=0x3 & rd & rs1 & rs2 & rs3 unimpl + +:crc32.b rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x10 & op2531=0x30 & rd & rs1 unimpl + +:crc32.h rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x11 & op2531=0x30 & rd & rs1 unimpl + +:crc32.w rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x12 & op2531=0x30 & rd & rs1 unimpl + +:crc32c.b rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x18 & op2531=0x30 & rd & rs1 unimpl + +:crc32c.h rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x19 & op2531=0x30 & rd & rs1 unimpl + +:crc32c.w rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x1a & op2531=0x30 & rd & rs1 unimpl + +:ctz rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x1 & op2531=0x30 & rd & rs1 unimpl + +:fsl rd, rs1, rs3, rs2 is op0006=0x33 & op1214=0x1 & op2526=0x2 & rd & rs1 & rs2 & rs3 unimpl + +:fsr rd, rs1, rs3, rs2 is op0006=0x33 & op1214=0x5 & op2526=0x2 & rd & rs1 & rs2 & rs3 unimpl + +#TODO fix op2025 +#TODO this looks like a typo in 0.92 +:fsri rd, rs1, rs3, op2025 is op0006=0x33 & op1214=0x5 & op2626=0x1 & op2025 & rd & rs1 & rs3 unimpl + +:gorc rd, rs1, rs2 is op0006=0x33 & op1214=0x5 & op2531=0x14 & rd & rs1 & rs2 unimpl + +#TODO fix op2026 +:gorci rd, rs1, op2026 is op0006=0x13 & op1214=0x5 & op2731=0x5 & op2026 & rd & rs1 unimpl + +:grev rd, rs1, rs2 is op0006=0x33 & op1214=0x5 & op2531=0x34 & rd & rs1 & rs2 unimpl + +#TODO fix op2026 +:grevi rd, rs1, op2026 is op0006=0x13 & op1214=0x5 & op2731=0xd & op2026 & rd & rs1 unimpl + +:max rd, rs1, rs2 is op0006=0x33 & op1214=0x5 & op2531=0x5 & rd & rs1 & rs2 unimpl + +:maxu rd, rs1, rs2 is op0006=0x33 & op1214=0x7 & op2531=0x5 & rd & rs1 & rs2 unimpl + +:min rd, rs1, rs2 is op0006=0x33 & op1214=0x4 & op2531=0x5 & rd & rs1 & rs2 unimpl + +:minu rd, rs1, rs2 is op0006=0x33 & op1214=0x6 & op2531=0x5 & rd & rs1 & rs2 unimpl + +:orn rd, rs1, rs2 is op0006=0x33 & op1214=0x6 & op2531=0x20 & rd & rs1 & rs2 unimpl + +:pack rd, rs1, rs2 is op0006=0x33 & op1214=0x4 & op2531=0x4 & rd & rs1 & rs2 unimpl + +:packh rd, rs1, rs2 is op0006=0x33 & op1214=0x7 & op2531=0x4 & rd & rs1 & rs2 unimpl + +:packu rd, rs1, rs2 is op0006=0x33 & op1214=0x4 & op2531=0x24 & rd & rs1 & rs2 unimpl + +:pcnt rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x2 & op2531=0x30 & rd & rs1 unimpl + +:rol rd, rs1, rs2 is op0006=0x33 & op1214=0x1 & op2531=0x30 & rd & rs1 & rs2 unimpl + +:ror rd, rs1, rs2 is op0006=0x33 & op1214=0x5 & op2531=0x30 & rd & rs1 & rs2 unimpl + +#TODO fix op2026 +:rori rd, rs1, op2026 is op0006=0x13 & op1214=0x5 & op2731=0xc & op2026 & rd & rs1 unimpl + +:sbclr rd, rs1, rs2 is op0006=0x33 & op1214=0x1 & op2531=0x24 & rd & rs1 & rs2 unimpl + +#TODO fix op2026 +:sbclri rd, rs1, op2026 is op0006=0x13 & op1214=0x1 & op2731=0x9 & op2026 & rd & rs1 unimpl + +:sbext rd, rs1, rs2 is op0006=0x33 & op1214=0x5 & op2531=0x24 & rd & rs1 & rs2 unimpl + +#TODO fix op2026 +:sbexti rd, rs1, op2026 is op0006=0x13 & op1214=0x5 & op2731=0x9 & op2026 & rd & rs1 unimpl + +:sbinv rd, rs1, rs2 is op0006=0x33 & op1214=0x1 & op2531=0x34 & rd & rs1 & rs2 unimpl + +#TODO fix op2026 +:sbinvi rd, rs1, op2026 is op0006=0x13 & op1214=0x1 & op2731=0xd & op2026 & rd & rs1 unimpl + +:sbset rd, rs1, rs2 is op0006=0x33 & op1214=0x1 & op2531=0x14 & rd & rs1 & rs2 unimpl + +#TODO fix op2026 +:sbseti rd, rs1, op2026 is op0006=0x13 & op1214=0x1 & op2731=0x5 & op2026 & rd & rs1 unimpl + +:sext.b rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x4 & op2531=0x30 & rd & rs1 unimpl + +:sext.h rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x5 & op2531=0x30 & rd & rs1 unimpl + +:sh1add rd, rs1, rs2 is op0006=0x33 & op1214=0x2 & op2531=0x10 & rd & rs1 & rs2 unimpl + +:sh2add rd, rs1, rs2 is op0006=0x33 & op1214=0x4 & op2531=0x10 & rd & rs1 & rs2 unimpl + +:sh3add rd, rs1, rs2 is op0006=0x33 & op1214=0x6 & op2531=0x10 & rd & rs1 & rs2 unimpl + +:shfl rd, rs1, rs2 is op0006=0x33 & op1214=0x1 & op2531=0x4 & rd & rs1 & rs2 unimpl + +#TODO fix op2025 +:shfli rd, rs1, op2025 is op0006=0x13 & op1214=0x1 & op2631=0x2 & op2025 & rd & rs1 unimpl + +:slo rd, rs1, rs2 is op0006=0x33 & op1214=0x1 & op2531=0x10 & rd & rs1 & rs2 unimpl + +#TODO fix op2026 +:sloi rd, rs1, op2026 is op0006=0x13 & op1214=0x1 & op2731=0x4 & op2026 & rd & rs1 unimpl + +:sro rd, rs1, rs2 is op0006=0x33 & op1214=0x5 & op2531=0x10 & rd & rs1 & rs2 unimpl + +#TODO fix op2026 +:sroi rd, rs1, op2026 is op0006=0x13 & op1214=0x5 & op2731=0x4 & op2026 & rd & rs1 unimpl + +:unshfl rd, rs1, rs2 is op0006=0x33 & op1214=0x5 & op2531=0x4 & rd & rs1 & rs2 unimpl + +#TODO fix op2025 +:unshfli rd, rs1, op2025 is op0006=0x13 & op1214=0x5 & op2631=0x2 & op2025 & rd & rs1 unimpl + +:xnor rd, rs1, rs2 is op0006=0x33 & op1214=0x4 & op2531=0x20 & rd & rs1 & rs2 unimpl + diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32d.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32d.sinc new file mode 100644 index 0000000..e8d298b --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32d.sinc @@ -0,0 +1,246 @@ +# RV32D Standard Extension + + +# fadd.d D,S,T,m 02000053 fe00007f SIMPLE (0, 0) +:fadd.d frd,frs1D,frs2D,FRM is frs1D & frd & frs2D & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x1 +{ + frd = frs1D f+ frs2D; +} + + +# fclass.d d,S e2001053 fff0707f SIMPLE (0, 0) +:fclass.d rd,frs1D is frs1D & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x71 & op2024=0x0 +{ + #TODO + # rd = 0; + # rd[0, 1] = 0; #TODO - inf + # rd[1, 1] = 0; #TODO - norm num + # rd[2, 1] = 0; #TODO - subnorm num + # rd[3, 1] = 0; #TODO - 0 + # rd[4, 1] = 0; #TODO + 0 + # rd[5, 1] = 0; #TODO + norm num + # rd[6, 1] = 0; #TODO + subnorm num + # rd[7, 1] = 0; #TODO + inf + # rd[8, 1] = 0; #TODO snan + # rd[9, 1] = 0; #TODO qnan +} + + +# fcvt.d.s D,S 42000053 fff0707f SIMPLE (0, 0) +:fcvt.d.s frd,frs1S is frs1S & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x21 & op2024=0x0 +{ + local tmp:8 = float2float(frs1S); + frd = tmp; +} + + +# fcvt.d.w D,s d2000053 fff0707f SIMPLE (0, 0) +:fcvt.d.w frd,rs1W is frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x69 & op2024=0x0 +{ + local tmp:8 = int2float(rs1W); + frd = tmp; +} + + +# fcvt.d.wu D,s d2100053 fff0707f SIMPLE (0, 0) +:fcvt.d.wu frd,rs1W is frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x69 & op2024=0x1 +{ + #ATTN unsigned can be an issue here + local u32:$(XLEN2) = zext(rs1W); + local tmp:8 = int2float(u32); + frd = tmp; +} + + +# fcvt.s.d D,S,m 40100053 fff0007f SIMPLE (0, 0) +:fcvt.s.d frd,frs1D,FRM is frs1D & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x20 & op2024=0x1 +{ + local tmp:4 = float2float(frs1D); + frd = zext(tmp); +} + + +# fcvt.w.d d,S,m c2000053 fff0007f SIMPLE (0, 0) +:fcvt.w.d rdW,frs1D,FRM is frs1D & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x0 +{ + rdW = trunc(frs1D); +} + + +# fcvt.wu.d d,S,m c2100053 fff0007f SIMPLE (0, 0) +:fcvt.wu.d rdW,frs1D,FRM is frs1D & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x1 +{ + #TODO unsigned + rdW = trunc(frs1D); +} + + +# fdiv.d D,S,T,m 1a000053 fe00007f SIMPLE (0, 0) +:fdiv.d frd,frs1D,frs2D,FRM is frs1D & frd & frs2D & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xd +{ + frd = frs1D f/ frs2D; +} + + +# feq.d d,S,T a2002053 fe00707f SIMPLE (0, 0) +:feq.d rd,frs1D,frs2D is frs2D & frs1D & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x51 +{ + rd = zext(frs1D f== frs2D); +} + + +# fld D,o(s) 00003007 0000707f QWORD|DREF (0, 8) +:fld frd,immI(rs1) is immI & frd & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x0 & funct3=0x3 +{ + local ea:$(XLEN) = immI + rs1; + frd = *[ram]:$(DFLEN) ea; +} + + +# fle.d d,S,T a2000053 fe00707f SIMPLE (0, 0) +:fle.d rd,frs1D,frs2D is frs2D & frs1D & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x51 +{ + rd = zext(frs1D f<= frs2D); +} + + +# flt.d d,S,T a2001053 fe00707f SIMPLE (0, 0) +:flt.d rd,frs1D,frs2D is frs2D & frs1D & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x51 +{ + rd = zext(frs1D f< frs2D); +} +#endif + + +# fmadd.d D,S,T,R,m 02000043 0600007f SIMPLE (0, 0) +:fmadd.d frd,frs1D,frs2D,frs3D,FRM is frs1D & frd & frs2D & FRM & frs3D & op0001=0x3 & op0204=0x0 & op0506=0x2 & op2526=0x1 +{ + frd = (frs1D f* frs2D) f+ frs3D; +} + + +# fmax.d D,S,T 2a001053 fe00707f SIMPLE (0, 0) +:fmax.d frd,frs1D,frs2D is frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x15 +{ + #TODO redo this + local tmpfrs1 = frs1D; + local tmpfrs2 = frs2D; + frd = tmpfrs1; + if (nan(tmpfrs1) && nan(tmpfrs2)) goto inst_next; + if (nan(tmpfrs2)) goto inst_next; + frd = tmpfrs2; + if (nan(tmpfrs1)) goto inst_next; + if (tmpfrs2 f> tmpfrs1) goto inst_next; + frd = tmpfrs1; +} + + +# fmin.d D,S,T 2a000053 fe00707f SIMPLE (0, 0) +:fmin.d frd,frs1D,frs2D is frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x15 +{ + #TODO redo this + local tmpfrs1 = frs1D; + local tmpfrs2 = frs2D; + frd = tmpfrs1; + if (nan(tmpfrs1) && nan(tmpfrs2)) goto inst_next; + if (nan(tmpfrs2)) goto inst_next; + frd = tmpfrs2; + if (nan(tmpfrs1)) goto inst_next; + if (tmpfrs2 f<= tmpfrs1) goto inst_next; + frd = tmpfrs1; +} + + +# fmsub.d D,S,T,R,m 02000047 0600007f SIMPLE (0, 0) +:fmsub.d frd,frs1D,frs2D,frs3D,FRM is frs1D & frd & frs2D & FRM & frs3D & op0001=0x3 & op0204=0x1 & op0506=0x2 & op2526=0x1 +{ + frd = (frs1D f* frs2D) f- frs3D; +} + + +# fmul.d D,S,T,m 12000053 fe00007f SIMPLE (0, 0) +:fmul.d frd,frs1D,frs2D,FRM is frs1D & frd & frs2D & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x9 +{ + frd = frs1D f* frs2D; +} + + +# fnmadd.d D,S,T,R,m 0200004f 0600007f SIMPLE (0, 0) +:fnmadd.d frd,frs1D,frs2D,frs3D,FRM is frs1D & frd & frs2D & FRM & frs3D & op0001=0x3 & op0204=0x3 & op0506=0x2 & op2526=0x1 +{ + frd = (f- (frs1D f* frs2D)) f- frs3D; +} + + +# fnmsub.d D,S,T,R,m 0200004b 0600007f SIMPLE (0, 0) +:fnmsub.d frd,frs1D,frs2D,frs3D,FRM is frs1D & frd & frs2D & FRM & frs3D & op0001=0x3 & op0204=0x2 & op0506=0x2 & op2526=0x1 +{ + frd = (f- (frs1D f* frs2D)) f+ frs3D; +} + + +# fsd T,q(s) 00003027 0000707f QWORD|DREF (0, 8) +:fsd frs2D,immS(rs1) is frs2D & immS & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x1 & funct3=0x3 +{ + local ea:$(XLEN) = immS + rs1; + *[ram]:$(DFLEN) ea = frs2D; +} + + +# fsgnj.d D,S,T 22000053 fe00707f SIMPLE (0, 0) +:fsgnj.d frd,frs1D,frs2D is frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x11 +{ + local tmp:$(DFLEN) = frs1D; + tmp[63,1] = frs2D[63,1]; + frd = tmp; +} + +# fmv.d D,U 22000053 fe00707f ALIAS (0, 0) +:fmv.d frd,frs1D is frd & frs1D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x11 & op1519=op2024 +{ + frd = frs1D; +} + + +# fsgnjn.d D,S,T 22001053 fe00707f SIMPLE (0, 0) +:fsgnjn.d frd,frs1D,frs2D is frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x11 +{ + local tmp:$(DFLEN) = frs1D; + tmp[63,1] = !frs2D[63,1]; + frd = tmp; +} + +# fneg.d D,U 22001053 fe00707f ALIAS (0, 0) +:fneg.d frd,frs1D is frd & frs1D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x11 & op1519=op2024 +{ + frd = f- frs1D; +} + + +# fsgnjx.d D,S,T 22002053 fe00707f SIMPLE (0, 0) +:fsgnjx.d frd,frs1D,frs2D is frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x11 +{ + local tmp:$(DFLEN) = frs1D; + tmp[63,1] = tmp[63,1] ^ frs2D[63,1]; + frd = tmp; +} + +# fabs.d D,U 22002053 fe00707f ALIAS (0, 0) +:fabs.d frd,frs1D is frd & frs1D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x11 & op1519=op2024 +{ + frd = abs(frs1D); +} + + +# fsqrt.d D,S,m 5a000053 fff0007f SIMPLE (0, 0) +:fsqrt.d frd,frs1D,FRM is frs1D & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x2d & op2024=0x0 +{ + frd = sqrt(frs1D); +} + + +# fsub.d D,S,T,m 0a000053 fe00007f SIMPLE (0, 0) +:fsub.d frd,frs1D,frs2D,FRM is frs1D & frd & frs2D & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x5 +{ + frd = frs1D f- frs2D; +} diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32f.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32f.sinc new file mode 100644 index 0000000..e830008 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32f.sinc @@ -0,0 +1,254 @@ +# RV32F Standard Extension + +# fadd.s D,S,T,m 00000053 fe00007f SIMPLE (0, 0) +:fadd.s frd,frs1S,frs2S,FRM is frs1S & frd & frs2S & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x0 +{ + local tmp:4 = frs1S f+ frs2S; + fassignS(frd, tmp); +} + + +# fclass.s d,S e0001053 fff0707f SIMPLE (0, 0) +:fclass.s rd,frs1S is frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x70 & op2024=0x0 +{ + #TODO + # rd = 0; + # rd[0, 1] = 0; #TODO - inf + # rd[1, 1] = 0; #TODO - norm num + # rd[2, 1] = 0; #TODO - subnorm num + # rd[3, 1] = 0; #TODO - 0 + # rd[4, 1] = 0; #TODO + 0 + # rd[5, 1] = 0; #TODO + norm num + # rd[6, 1] = 0; #TODO + subnorm num + # rd[7, 1] = 0; #TODO + inf + # rd[8, 1] = 0; #TODO snan + # rd[9, 1] = 0; #TODO qnan +} + + +# fcvt.s.w D,s,m d0000053 fff0007f SIMPLE (0, 0) +:fcvt.s.w frd,rs1W,FRM is frd & FRM & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x0 +{ + local tmp:4 = int2float(rs1W); + fassignS(frd, tmp); +} + + +# fcvt.s.wu D,s,m d0100053 fff0007f SIMPLE (0, 0) +:fcvt.s.wu frd,rs1W,FRM is frd & FRM & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x1 +{ + #ATTN unsigned can be an issue here + local u32:$(XLEN2) = zext(rs1W); + local tmp:4 = int2float(u32); + fassignS(frd, tmp); +} + + +# fcvt.w.s d,S,m c0000053 fff0007f SIMPLE (0, 0) +:fcvt.w.s rdW,frs1S,FRM is frs1S & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x0 +{ + rdW = trunc(frs1S); +} + + +# fcvt.wu.s d,S,m c0100053 fff0007f SIMPLE (0, 0) +:fcvt.wu.s rdW,frs1S,FRM is frs1S & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x1 +{ + #TODO unsigned + rdW = trunc(frs1S); +} + + +# fdiv.s D,S,T,m 18000053 fe00007f SIMPLE (0, 0) +:fdiv.s frd,frs1S,frs2S,FRM is frs1S & frd & frs2S & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xc +{ + local tmp:4 = frs1S f/ frs2S; + fassignS(frd, tmp); +} + + +# feq.s d,S,T a0002053 fe00707f SIMPLE (0, 0) +:feq.s rd,frs1S,frs2S is frs2S & frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x50 +{ + rd = zext(frs1S f== frs2S); +} + + +# fle.s d,S,T a0000053 fe00707f SIMPLE (0, 0) +:fle.s rd,frs1S,frs2S is frs2S & frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x50 +{ + rd = zext(frs1S f<= frs2S); +} + + +# flt.s d,S,T a0001053 fe00707f SIMPLE (0, 0) +:flt.s rd,frs1S,frs2S is frs2S & frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x50 +{ + rd = zext(frs1S f< frs2S); +} + + +# flw D,o(s) 00002007 0000707f DWORD|DREF (0, 4) +:flw frd,immI(rs1) is immI & frd & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x0 & funct3=0x2 +{ + local ea:$(XLEN) = immI + rs1; + fassignS(frd, *[ram]:4 ea); +} + + +# fmadd.s D,S,T,R,m 00000043 0600007f SIMPLE (0, 0) +:fmadd.s frd,frs1S,frs2S,frs3S,FRM is frs1S & frd & frs2S & FRM & frs3S & op0001=0x3 & op0204=0x0 & op0506=0x2 & op2526=0x0 +{ + local tmp:4 = (frs1S f* frs2S) f+ frs3S; + fassignS(frd, tmp); +} + + +# fmax.s D,S,T 28001053 fe00707f SIMPLE (0, 0) +:fmax.s frd,frs1S,frs2S is frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x14 +{ + #TODO redo this + local tmpfrs1 = frs1S; + local tmpfrs2 = frs2S; + fassignS(frd, tmpfrs1); + if (nan(tmpfrs1) && nan(tmpfrs2)) goto inst_next; + if (nan(tmpfrs2)) goto inst_next; + fassignS(frd, tmpfrs2); + if (nan(tmpfrs1)) goto inst_next; + if (tmpfrs2 f>= tmpfrs1) goto inst_next; + fassignS(frd, tmpfrs1); +} + + +# fmin.s D,S,T 28000053 fe00707f SIMPLE (0, 0) +:fmin.s frd,frs1S,frs2S is frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x14 +{ + #TODO redo this + local tmpfrs1 = frs1S; + local tmpfrs2 = frs2S; + fassignS(frd, tmpfrs1); + if (nan(tmpfrs1) && nan(tmpfrs2)) goto inst_next; + if (nan(tmpfrs2)) goto inst_next; + fassignS(frd, tmpfrs2); + if (nan(tmpfrs1)) goto inst_next; + if (tmpfrs2 f<= tmpfrs1) goto inst_next; + fassignS(frd, tmpfrs1); +} + + +# fmsub.s D,S,T,R,m 00000047 0600007f SIMPLE (0, 0) +:fmsub.s frd,frs1S,frs2S,frs3S,FRM is frs1S & frd & frs2S & FRM & frs3S & op0001=0x3 & op0204=0x1 & op0506=0x2 & op2526=0x0 +{ + local tmp:4 = (frs1S f* frs2S) f- frs3S; + fassignS(frd, tmp); +} + + +# fmul.s D,S,T,m 10000053 fe00007f SIMPLE (0, 0) +:fmul.s frd,frs1S,frs2S,FRM is frs1S & frd & frs2S & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x8 +{ + local tmp:4 = frs1S f* frs2S; + fassignS(frd, tmp); +} + + +# fmv.w.x D,s f0000053 fff0707f SIMPLE (0, 0) +:fmv.w.x frd,rs1W is frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x78 & op2024=0x0 +{ + fassignS(frd, rs1W); +} + +# fmv.x.w d,S e0000053 fff0707f SIMPLE (0, 0) +:fmv.x.w rdW,frs1S is frs1S & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x70 & op2024=0x0 +{ + local tmpreg:4 = &frs1S; + local tmp:4 = *[register]:4 tmpreg; + rdW = tmp; +} + + +# fnmadd.s D,S,T,R,m 0000004f 0600007f SIMPLE (0, 0) +:fnmadd.s frd,frs1S,frs2S,frs3S,FRM is frs1S & frd & frs2S & FRM & frs3S & op0001=0x3 & op0204=0x3 & op0506=0x2 & op2526=0x0 +{ + local tmp:4 = (f- (frs1S f* frs2S)) f- frs3S; + fassignS(frd, tmp); +} + + +# fnmsub.s D,S,T,R,m 0000004b 0600007f SIMPLE (0, 0) +:fnmsub.s frd,frs1S,frs2S,frs3S,FRM is frs1S & frd & frs2S & FRM & frs3S & op0001=0x3 & op0204=0x2 & op0506=0x2 & op2526=0x0 +{ + local tmp:4 = (f- (frs1S f* frs2S)) f+ frs3S; + fassignS(frd, tmp); +} + + +# fsgnj.s D,S,T 20000053 fe00707f SIMPLE (0, 0) +:fsgnj.s frd,frs1S,frs2S is frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x10 +{ + local tmp:$(SFLEN) = frs1S; + tmp[31,1] = frs2S[31,1]; + fassignS(frd, tmp); +} + +# fmv.s D,U 20000053 fe00707f ALIAS (0, 0) +:fmv.s frd,frs1S is frd & frs1S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x10 & op1519=op2024 +{ + fassignS(frd, frs1S); +} + + +# fsgnjn.s D,S,T 20001053 fe00707f SIMPLE (0, 0) +:fsgnjn.s frd,frs1S,frs2S is frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x10 +{ + local tmp:$(SFLEN) = frs1S; + tmp[31,1] = !frs2S[31,1]; + fassignS(frd, tmp); +} + +# fneg.s D,U 20001053 fe00707f ALIAS (0, 0) +:fneg.s frd,frs1S is frs1S & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x10 & op1519=op2024 +{ + local tmp:4 = f- frs1S; + fassignS(frd, tmp); +} + + +# fsgnjx.s D,S,T 20002053 fe00707f SIMPLE (0, 0) +:fsgnjx.s frd,frs1S,frs2S is frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x10 +{ + local tmp:$(SFLEN) = frs1S; + tmp[31,1] = tmp[31,1] ^ frs2S[31,1]; + fassignS(frd, tmp); +} + +# fabs.s D,U 20002053 fe00707f ALIAS (0, 0) +:fabs.s frd,frs1S is frd & frs1S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x10 & op1519=op2024 +{ + local tmp:4 = abs(frs1S); + fassignS(frd, tmp); +} + + +# fsqrt.s D,S,m 58000053 fff0007f SIMPLE (0, 0) +:fsqrt.s frd,frs1S,FRM is frs1S & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x2c & op2024=0x0 +{ + local tmp:4 = sqrt(frs1S); + fassignS(frd, tmp); +} + + +# fsub.s D,S,T,m 08000053 fe00007f SIMPLE (0, 0) +:fsub.s frd,frs1S,frs2S,FRM is frs1S & frd & frs2S & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x4 +{ + local tmp:4 = frs1S f- frs2S; + fassignS(frd, tmp); +} + + +# fsw T,q(s) 00002027 0000707f DWORD|DREF (0, 4) +:fsw frs2S,immS(rs1) is frs2S & immS & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x1 & funct3=0x2 +{ + local ea:$(XLEN) = immS + rs1; + *[ram]:$(SFLEN) ea = frs2S; +} diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32i.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32i.sinc new file mode 100644 index 0000000..0fbdfac --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32i.sinc @@ -0,0 +1,382 @@ +# RV32I Base Instruction Set + +# add d,s,t 00000033 fe00707f SIMPLE (0, 0) +:add rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x0 +{ + rd = rs1 + rs2; +} + + +# addi d,s,j 00000013 0000707f SIMPLE (0, 0) +:addi rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 +{ + rd = rs1 + immI; +} + +# nop 00000013 ffffffff ALIAS (0, 0) +:nop is op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op0711=0x0 & op1531=0x0 +{ + local NOP:1 = 0; + NOP = NOP; +} + +# mv d,s 00000013 fff0707f ALIAS (0, 0) +:mv rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op2031=0x0 +{ + rd = rs1; +} + +# li d,j 00000013 000ff07f ALIAS (0, 0) +:li rd,immI is immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op1519=0x0 +{ + #TODO alias of addi rd,zero,0x0 is an issue + rd = immI; +} + +# Resolve conflict between: mv rd,zero and li rd,0x0 +# ATTN this implementation uses mv rd,zero +:mv rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op1531=0x0 +{ + rd = rs1; +} + + +# and d,s,t 00007033 fe00707f SIMPLE (0, 0) +:and rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x7 & funct7=0x0 +{ + rd = rs1 & rs2; +} + + +# andi d,s,j 00007013 0000707f SIMPLE (0, 0) +:andi rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x7 +{ + rd = rs1 & immI; +} + + +# auipc d,u 00000017 0000007f SIMPLE (0, 0) +:auipc rd,immU is immU & rd & op0001=0x3 & op0204=0x5 & op0506=0x0 +{ + rd = immU + inst_start; +} + + +# beq s,t,p 00000063 0000707f CONDBRANCH (0, 0) +:beq rs1,rs2,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x0 +{ + if (rs1 == rs2) goto immSB; +} + + +# bge s,t,p 00005063 0000707f CONDBRANCH (0, 0) +:bge rs1,rs2,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x5 +{ + if (rs1 s>= rs2) goto immSB; +} + + +# bgeu s,t,p 00007063 0000707f CONDBRANCH (0, 0) +:bgeu rs1,rs2,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x7 +{ + if (rs1 >= rs2) goto immSB; +} + + +# blt s,t,p 00004063 0000707f CONDBRANCH (0, 0) +:blt rs1,rs2,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x4 +{ + if (rs1 s< rs2) goto immSB; +} + + +# bltu s,t,p 00006063 0000707f CONDBRANCH (0, 0) +:bltu rs1,rs2,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x6 +{ + if (rs1 < rs2) goto immSB; +} + + +# bne s,t,p 00001063 0000707f CONDBRANCH (0, 0) +:bne rs1,rs2,immSB is immSB & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x3 & funct3=0x1 +{ + if (rs1 != rs2) goto immSB; +} + +# ebreak 00100073 ffffffff SIMPLE (0, 0) +:ebreak is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x20 +{ + ebreak(); +} + +# ecall 00000073 ffffffff SIMPLE (0, 0) +:ecall is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x0 +{ + ecall(); +} + + +# fence P,Q 0000000f f00fffff SIMPLE (0, 0) +:fence pred,succ is pred & succ & op0001=0x3 & op0204=0x3 & op0506=0x0 & funct3=0x0 & fm=0x0 & op0711=0x0 & op1519=0x0 +{ + fence(); +} + +# jal d,a 0000006f 0000007f JSR (0, 0) +# call for rd = RA|T0 set to inst_next +:jal rd,immUJ is immUJ & rd & (r0711=1 | r0711=5) & op0001=0x3 & op0204=0x3 & op0506=0x3 +{ + rd = inst_next; + call immUJ; +} + +# goto for all other rd set to inst_next +:jal rd,immUJ is immUJ & rd & r0711 & op0001=0x3 & op0204=0x3 & op0506=0x3 +{ + rd = inst_next; + goto immUJ; +} + +# j a 0000006f 00000fff BRANCH|ALIAS (0, 0) +:j immUJ is immUJ & op0001=0x3 & op0204=0x3 & op0506=0x3 & op0711=0x0 +{ + goto immUJ; +} + +# jalr d,s,j 00000067 0000707f JSR (0, 0) +# call for rd = RA|T0 set to inst_next +:jalr rd,rs1,immI is rs1 & immI & rd & (r0711=1 | r0711=5) & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 +{ + local ea:$(XLEN) = (rs1 + immI) & ~1; + rd = inst_next; + call [ea]; +} + +# goto for all other rd set to inst_next +:jalr rd,rs1,immI is rs1 & immI & rd & r0711 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 +{ + local ea:$(XLEN) = (rs1 + immI) & ~1; + rd = inst_next; + goto [ea]; +} + +# jr o(s) 00000067 00007fff BRANCH|ALIAS (0, 0) +:jr immI(rs1) is immI & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0 +{ + local ea:$(XLEN) = (rs1 + immI) & ~1; + goto [ea]; +} + +# jr s 00000067 fff07fff BRANCH|ALIAS (0, 0) +:jr rs1 is rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031=0x0 +{ + local ea:$(XLEN) = rs1 & ~1; + goto [ea]; +} + +# ret 00008067 ffffffff BRANCH|ALIAS (0, 0) +:ret is op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031=0x0 & op1519=1 +{ + local ea:$(XLEN) = ra & ~1; + return [ea]; +} + + +# lb d,o(s) 00000003 0000707f BYTE|DREF (0, 1) +:lb rd,immI(rs1) is immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x0 +{ + local ea:$(XLEN) = rs1 + immI; + rd = sext(*[ram]:1 ea); +} + + +# lbu d,o(s) 00004003 0000707f BYTE|DREF (0, 1) +:lbu rd,immI(rs1) is immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x4 +{ + local ea:$(XLEN) = rs1 + immI; + rd = zext(*[ram]:1 ea); +} + + +# lh d,o(s) 00001003 0000707f WORD|DREF (0, 2) +:lh rd,immI(rs1) is immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x1 +{ + local ea:$(XLEN) = rs1 + immI; + rd = sext(*[ram]:2 ea); +} + + +# lhu d,o(s) 00005003 0000707f WORD|DREF (0, 2) +:lhu rd,immI(rs1) is immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x5 +{ + local ea:$(XLEN) = rs1 + immI; + rd = zext(*[ram]:2 ea); +} + + +# lui d,u 00000037 0000007f SIMPLE (0, 0) +:lui rd,immU is immU & rd & op0001=0x3 & op0204=0x5 & op0506=0x1 +{ + rd = immU; +} + + +# lw d,o(s) 00002003 0000707f DWORD|DREF (0, 4) +:lw rd,immI(rs1) is immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x2 +{ + local ea:$(XLEN) = rs1 + immI; + assignW(rd, *[ram]:4 ea); +} + + +# or d,s,t 00006033 fe00707f SIMPLE (0, 0) +:or rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x6 & funct7=0x0 +{ + rd = rs1 | rs2; +} + + +# ori d,s,j 00006013 0000707f SIMPLE (0, 0) +:ori rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x6 +{ + rd = rs1 | immI; +} + + +# sb t,q(s) 00000023 0000707f BYTE|DREF (0, 1) +:sb rs2,immS(rs1) is immS & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x1 & funct3=0x0 +{ + local ea:$(XLEN) = rs1 + immS; + *[ram]:1 ea = rs2:1; +} + + +# sh t,q(s) 00001023 0000707f WORD|DREF (0, 2) +:sh rs2,immS(rs1) is immS & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x1 & funct3=0x1 +{ + local ea:$(XLEN) = rs1 + immS; + *[ram]:2 ea = rs2:2; +} + + +# sll d,s,t 00001033 fe00707f SIMPLE (0, 0) +:sll rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x1 & funct7=0x0 +{ + local shift:$(XLEN) = rs2 & ($(ADDRSIZE) - 1); + rd = rs1 << shift; +} + + +# slli d,s,> 00001013 fc00707f SIMPLE (0, 0) +:slli rd,rs1,shamt6 is rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x1 & op2631=0x0 +{ + rd = rs1 << shamt6; +} + + +# slt d,s,t 00002033 fe00707f SIMPLE (0, 0) +:slt rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x2 & funct7=0x0 +{ + rd = zext(rs1 s< rs2); +} + + +# slti d,s,j 00002013 0000707f SIMPLE (0, 0) +:slti rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x2 +{ + rd = zext(rs1 s< immI); +} + + +# sltiu d,s,j 00003013 0000707f SIMPLE (0, 0) +:sltiu rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x3 +{ + rd = zext(rs1 < immI); +} + + +# sltu d,s,t 00003033 fe00707f SIMPLE (0, 0) +:sltu rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x3 & funct7=0x0 +{ + rd = zext(rs1 < rs2); +} + + +# sra d,s,t 40005033 fe00707f SIMPLE (0, 0) +:sra rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x5 & funct7=0x20 +{ + local shift:$(XLEN) = rs2 & ($(ADDRSIZE) - 1); + rd = rs1 s>> shift; +} + + +# srai d,s,> 40005013 fc00707f SIMPLE (0, 0) +:srai rd,rs1,shamt6 is rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x5 & op2631=0x10 +{ + rd = rs1 s>> shamt6; +} + + +# srl d,s,t 00005033 fe00707f SIMPLE (0, 0) +:srl rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x5 & funct7=0x0 +{ + local shift:$(XLEN) = rs2 & ($(ADDRSIZE) - 1); + rd = rs1 >> shift; +} + + +# srli d,s,> 00005013 fc00707f SIMPLE (0, 0) +:srli rd,rs1,shamt6 is rs1 & shamt6 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x5 & op2631=0x0 +{ + rd = rs1 >> shamt6; +} + + +# sub d,s,t 40000033 fe00707f SIMPLE (0, 0) +:sub rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x20 +{ + rd = rs1 - rs2; +} + +# neg d,t 40000033 fe0ff07f ALIAS (0, 0) +:neg rd,rs2 is rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x20 & op1519=0x0 +{ + rd = -rs2; +} + + +# sw t,q(s) 00002023 0000707f DWORD|DREF (0, 4) +:sw rs2,immS(rs1) is immS & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x1 & funct3=0x2 +{ + local ea:$(XLEN) = rs1 + immS; + *[ram]:4 ea = rs2:4; +} + + +# unimp c0001073 ffffffff SIMPLE (0, 0) +:unimp is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op0711=0x0 & op1531=0x18000 +{ + local excaddr:$(XLEN) = inst_start; + local target:$(XLEN) = unimp(excaddr); + goto [target]; +} + + +# xor d,s,t 00004033 fe00707f SIMPLE (0, 0) +:xor rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x4 & funct7=0x0 +{ + rd = rs1 ^ rs2; +} + + +# xori d,s,j 00004013 0000707f SIMPLE (0, 0) +:xori rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x4 +{ + rd = rs1 ^ immI; +} + +# not d,s fff04013 fff0707f ALIAS (0, 0) +:not rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x4 & op2031=0xfff +{ + rd = ~rs1; +} diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32k.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32k.sinc new file mode 100644 index 0000000..243b744 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32k.sinc @@ -0,0 +1,59 @@ +# RV32 Crypto Extension +# NOTE 0.6.2 + +# bs 00001 rs2 rs1 010 rd 0101011 saes32.encs +:saes32.encs rd, rs1, rs2, bs is rd & rs1 & rs2 & bs & op0006=0x2b & op1214=0x2 & op2529=0x1 unimpl + +# bs 00000 rs2 rs1 010 rd 0101011 saes32.encsm +:saes32.encsm rd, rs1, rs2, bs is rd & rs1 & rs2 & bs & op0006=0x2b & op1214=0x2 & op2529=0x0 unimpl + +# bs 00011 rs2 rs1 010 rd 0101011 saes32.decs +:saes32.decs rd, rs1, rs2, bs is rd & rs1 & rs2 & bs & op0006=0x2b & op1214=0x2 & op2529=0x3 unimpl + +# bs 00010 rs2 rs1 010 rd 0101011 saes32.decsm +:saes32.decsm rd, rs1, rs2, bs is rd & rs1 & rs2 & bs & op0006=0x2b & op1214=0x2 & op2529=0x2 unimpl + +# 0000111 00000 rs1 111 rd 0101011 ssha256.sig0 +:ssha256.sig0 rd, rs1 is rd & rs1 & op0006=0x2b & op1214=0x7 & op2024=0x00 & op2531=0x07 unimpl + +# 0000111 00001 rs1 111 rd 0101011 ssha256.sig1 +:ssha256.sig1 rd, rs1 is rd & rs1 & op0006=0x2b & op1214=0x7 & op2024=0x01 & op2531=0x07 unimpl + +# 0000111 00010 rs1 111 rd 0101011 ssha256.sum0 +:ssha256.sum0 rd, rs1 is rd & rs1 & op0006=0x2b & op1214=0x7 & op2024=0x02 & op2531=0x07 unimpl + +# 0000111 00011 rs1 111 rd 0101011 ssha256.sum1 +:ssha256.sum1 rd, rs1 is rd & rs1 & op0006=0x2b & op1214=0x7 & op2024=0x03 & op2531=0x07 unimpl + +# 0001100 rs2 rs1 111 rd 0101011 ssha512.sum0r +:ssha512.sum0r rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x2b & op1214=0x7 & op2531=0x0c unimpl + +# 0001101 rs2 rs1 111 rd 0101011 ssha512.sum1r +:ssha512.sum1r rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x2b & op1214=0x7 & op2531=0x0d unimpl + +# 0001000 rs2 rs1 111 rd 0101011 ssha512.sig0l +:ssha512.sig0l rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x2b & op1214=0x7 & op2531=0x08 unimpl + +# 0001001 rs2 rs1 111 rd 0101011 ssha512.sig0h +:ssha512.sig0h rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x2b & op1214=0x7 & op2531=0x09 unimpl + +# 0001010 rs2 rs1 111 rd 0101011 ssha512.sig1l +:ssha512.sig1l rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x2b & op1214=0x7 & op2531=0x0a unimpl + +# 0001011 rs2 rs1 111 rd 0101011 ssha512.sig1h +:ssha512.sig1h rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x2b & op1214=0x7 & op2531=0x0b unimpl + +# 0000111 01000 rs1 111 rd 0101011 ssm3.p0 +:ssm3.p0 rd, rs1 is rd & rs1 & op0006=0x2b & op1214=0x7 & op2024=0x08 & op2531=0x07 unimpl + +# 0000111 01001 rs1 111 rd 0101011 ssm3.p1 +:ssm3.p1 rd, rs1 is rd & rs1 & op0006=0x2b & op1214=0x7 & op2024=0x09 & op2531=0x07 unimpl + +# bs 00100 rs2 rs1 011 rd 0101011 ssm4.ed +:ssm4.ed rd, rs1, rs2, bs is rd & rs1 & rs2 & bs & op0006=0x2b & op1214=0x3 & op2529=0x4 unimpl + +# bs 00101 rs2 rs1 011 rd 0101011 ssm4.ks +:ssm4.ks rd, rs1, rs2, bs is rd & rs1 & rs2 & bs & op0006=0x2b & op1214=0x3 & op2529=0x5 unimpl + +# 0000111 shamtw 01010 111 rd 0101011 pollentropy +:pollentropy rd, shamtw is rd & shamtw & op0006=0x2b & op1214=0x7 & op1519=0x0a & op2531=0x07 unimpl \ No newline at end of file diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32m.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32m.sinc new file mode 100644 index 0000000..f7202a3 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32m.sinc @@ -0,0 +1,65 @@ +# RV32M Standard Extension + +# div d,s,t 02004033 fe00707f SIMPLE (0, 0) +:div rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x4 & funct7=0x1 +{ + rd = rs1 s/ rs2; +} + + +# divu d,s,t 02005033 fe00707f SIMPLE (0, 0) +:divu rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x5 & funct7=0x1 +{ + rd = rs1 / rs2; +} + + +# mul d,s,t 02000033 fe00707f SIMPLE (0, 0) +:mul rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x1 +{ + rd = rs1 * rs2; +} + + +# mulh d,s,t 02001033 fe00707f SIMPLE (0, 0) +:mulh rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x1 & funct7=0x1 +{ + local trs1:$(XLEN2) = sext(rs1); + local trs2:$(XLEN2) = sext(rs2); + local tmp:$(XLEN2) = trs1 * trs2; + rd = tmp($(XLEN)); +} + + +# mulhsu d,s,t 02002033 fe00707f SIMPLE (0, 0) +:mulhsu rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x2 & funct7=0x1 +{ + local trs1:$(XLEN2) = sext(rs1); + local trs2:$(XLEN2) = zext(rs2); + local tmp:$(XLEN2) = trs1 * trs2; + rd = tmp($(XLEN)); +} + + +# mulhu d,s,t 02003033 fe00707f SIMPLE (0, 0) +:mulhu rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x3 & funct7=0x1 +{ + local trs1:$(XLEN2) = zext(rs1); + local trs2:$(XLEN2) = zext(rs2); + local tmp:$(XLEN2) = trs1 * trs2; + rd = tmp($(XLEN)); +} + + +# rem d,s,t 02006033 fe00707f SIMPLE (0, 0) +:rem rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x6 & funct7=0x1 +{ + rd = rs1 s% rs2; +} + + +# remu d,s,t 02007033 fe00707f SIMPLE (0, 0) +:remu rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x7 & funct7=0x1 +{ + rd = rs1 % rs2; +} diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32p.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32p.sinc new file mode 100644 index 0000000..749f6b3 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32p.sinc @@ -0,0 +1,996 @@ +# RV32 P Extension + + +# add16 rt, ra, rb ; rt.H[_x_] = ra.H[_x_] + rb.H[_x_]; ; (RV32: __x__=1..0, RV64: __x__=3..0) +:add16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x20 +{ + local tmp1:$(XLEN) = rs1; + local tmp2:$(XLEN) = rs2; + rd[ 0,16] = tmp1[ 0,16] + tmp2[ 0,16]; + rd[16,16] = tmp1[16,16] + tmp2[16,16]; +@if ADDRSIZE == "64" + rd[32,16] = tmp1[32,16] + tmp2[32,16]; + rd[48,16] = tmp1[48,16] + tmp2[48,16]; +@endif +} + + +# add64 rt, ra, rb ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = a64 + b64; + ; + ; r[tU].r[tL] = t64; +:add64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x60 +{ +@if ADDRSIZE == "32" + local dst:$(XLEN) = &rd; + local src1:$(XLEN) = &rs1; + local src2:$(XLEN) = &rs2; + *[register]:8 dst = *[register]:8 src1 + *[register]:8 src2; +@else + rd = rs1 + rs2; +@endif +} + + +# add8 rt, ra, rb ; rt.B[_x_] = ra.B[_x_] + rb.B[_x_]; ; (RV32: __x__=3..0, RV64: __x__=7..0) +:add8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x24 +{ + local tmp1:$(XLEN) = rs1; + local tmp2:$(XLEN) = rs2; + rd[ 0,8] = tmp1[ 0,8] + tmp2[ 0,8]; + rd[ 8,8] = tmp1[ 8,8] + tmp2[ 8,8]; + rd[16,8] = tmp1[16,8] + tmp2[16,8]; + rd[24,8] = tmp1[24,8] + tmp2[24,8]; +@if ADDRSIZE == "64" + rd[32,8] = tmp1[32,8] + tmp2[32,8]; + rd[40,8] = tmp1[40,8] + tmp2[40,8]; + rd[48,8] = tmp1[48,8] + tmp2[48,8]; + rd[56,8] = tmp1[56,8] + tmp2[56,8]; +@endif +} + + +# ave rt, ra, rb +:ave rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x70 +{ + local tmp:$(XLEN) = rs1 + rs2; + rd = (tmp / 2) + (tmp & 1); +} + + +# bitrev rt, ra, rb ; msb = rb[4:0]; // RV32 ; msb = rb[5:0]; // RV64 ; rev[0:msb] = ra[msb:0]; ; rt = ZE(rev[msb:0]); +:bitrev rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x73 unimpl + + +# bitrevi rt, ra, imm5u ; msb = imm5u; // RV32 ; msb = imm6u; // RV64 ; rev[0:msb] = ra[msb:0]; ; rt = ZE(rev[msb:0]); +:bitrevi rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x74 unimpl + + +# bpick rt, ra, rb, rc ; rt[_i_] = rc[_i_]? ra[_i_] : rb[_i_]; + ; (RV32: __i__=31..0, RV64: __i__=63..0) +:bpick rd,rs1,rs2,rs3 is op0006=0x3f & rd & rs1 & rs2 & rs3 & funct3=0x3 & funct7=0x00 unimpl + + +# bpick rt, ra, rb, rc ; rt[_i_] = rc[_i_]? ra[_i_] : rb[_i_]; + ; (RV32: __i__=31..0, RV64: __i__=63..0) +:bpick rd,rs1,rs2,rs3 is op0006=0x3f & rd & rs1 & rs2 & rs3 & funct3=0x3 & funct7=0x04 unimpl + + +# clo16 rt, ra +:clo16 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x0a unimpl + + +# clo32 rt, ra ; rt.W[_x_] = CLO(ra.W[_x_]) ; (RV32: __x__=0, RV64: __x__=1..0) +:clo32 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x12 unimpl + + +# clo8 rt, ra +:clo8 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x02 unimpl + + +# clrs16 rt, ra +:clrs16 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x08 unimpl + + +# clrs32 rt, ra ; rt.W[_x_] = CLRS(ra.W[_x_]) ; (RV32: __x__=0, RV64: __x__=1..0) +:clrs32 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x10 unimpl + + +# clrs8 rt, ra +:clrs8 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x00 unimpl + + +# clz16 rt, ra +:clz16 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x09 unimpl + + +# clz32 rt, ra ; rt.W[_x_] = CLZ(ra.W[_x_]) ; (RV32: __x__=0, RV64: __x__=1..0) +:clz32 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x11 unimpl + + +# clz8 rt, ra +:clz8 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x57 & subf5=0x01 unimpl + + +# cmpeq16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] == rb.H[_x_])? 0xffff : 0; ; (RV32: __x__=1..0, RV64: __x__=3..0) +:cmpeq16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x26 unimpl + + +# cmpeq8 rt, ra, rb ; rt.B[_x_] = (ra.B[_x_] == rb.B[_x_])? 0xff : 0; ; (RV32: __x__=3..0, RV64: __x__=7..0) +:cmpeq8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x27 unimpl + + +# cras16 rt, ra, rb ; rt.H[_x_] = ra.H[_x_] + rb.H[_x-1_]; + ; rt.H[_x-1_] = ra.H[_x-1_] – rb.H[_x_]; ; (RV32: __x__=1, RV64: __x__=1,3) +:cras16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x22 unimpl + + +# crsa16 rt, ra, rb ; rt.H[_x_] = ra.H[_x_] - rb.H[_x-1_]; + ; rt.H[_x-1_] = ra.H[_x-1_] + rb.H[_x_]; ; (RV32: __x__=1, RV64: __x__=1,3) +:crsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x23 unimpl + + +# insb rt, ra, imm3u ; byte_idx = imm2u; // RV32 ; byte_idx = imm3u; // RV64 ; rt.B[byte_idx] = ra.B[0]; +:insb rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x00 unimpl + + +# kabs16 rt, ra ; rt.H[_x_] = SAT.Q15(ABS(ra.H[_x_])); ; (RV32: __x__=1..0, RV64: __x__=3..0) +:kabs16 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x11 unimpl + + +# kabs32 rt, ra ; rt.W[_x_] = SAT.Q31(ABS(ra.W[_x_])); ; (RV64: __x__=1..0) +:kabs32 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x12 unimpl + + +# kabs8 rt, ra ; rt.B[_x_] = SAT.Q7(ABS(ra.B[_x_])); ; (RV32: __x__=3..0, RV64: __x__=7..0) +:kabs8 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x10 unimpl + + +# kabsw rt, ra ; rt = SAT.Q31(ABS(ra)); // RV32 ; rt = SE(SAT.Q31(ABS(ra.W[_0_]))); // RV64 +:kabsw rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x14 unimpl + + +# kadd16 rt, ra, rb ; rt.H[_x_] = SAT.Q15(ra.H[_x_] + rb.H[_x_]); ; (RV32: __x__=1..0, RV64: __x__=3..0) +:kadd16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x08 unimpl + + +# kadd64 rt, ra, rb ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = SAT.Q63(a64 + b64); + ; + ; r[tU].r[tL] = t64; +:kadd64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x48 unimpl + + +# kadd8 rt, ra, rb ; rt.B[_x_] = SAT.Q7(ra.B[_x_] + rb.B[_x_]); ; (RV32: __x__=3..0, RV64: __x__=7..0) +:kadd8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x0c unimpl + + +:kaddh rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x02 unimpl + + +:kaddw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x00 unimpl + + +# kcras16 rt, ra, rb ; rt.H[_x_] = SAT.Q15(ra.H[_x_] + rb.H[_x-1_]); + ; rt.H[_x-1_] = SAT.Q15(ra.H[_x-1_] – rb.H[_x_]); ; (RV32: __x__=1, RV64: __x__=1,3) +:kcras16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x0a unimpl + + +# kcrsa16 rt, ra, rb ; rt.H[_x_] = SAT.Q15(ra.H[_x_] - rb.H[_x-1_]); + ; rt.H[_x-1_] = SAT.Q15(ra.H[_x-1_] + rb.H[_x_]); ; (RV32: __x__=1, RV64: __x__=1,3) +:kcrsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x0b unimpl + + +:kdmabb rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x69 unimpl + + +:kdmabb16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x6b unimpl + + +:kdmabt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x71 unimpl + + +:kdmabt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x74 unimpl + + +:kdmatt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x79 unimpl + + +:kdmatt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x7c unimpl + + +:kdmbb rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x05 unimpl + + +:kdmbb16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x6c unimpl + + +:kdmbt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x0d unimpl + + +:kdmbt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x75 unimpl + + +:kdmtt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x15 unimpl + + +:kdmtt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x7d unimpl + + +# khm16 rt, ra, rb ; rt.H[_x_] = SAT.Q15((ra.H[_x_] s* rb.H[_x_]) >> 15); ; (RV32: __x__=1..0, RV64: __x__=3..0) +:khm16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x43 unimpl + + +# khm8 rt, ra, rb ; rt.B[_x_] = SAT.Q7((ra.B[_x_] s* rb.B[_x_]) >> 7); ; (RV32: __x__=3..0, RV64: __x__=7..0) +:khm8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x47 unimpl + + +:khmbb rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x06 unimpl + + +:khmbb16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x6d unimpl + + +:khmbt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x0e unimpl + + +:khmbt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x76 unimpl + + +:khmtt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x16 unimpl + + +:khmtt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x7e unimpl + + +# khmx16 rt, ra, rb ; rt.H[_x_] = SAT.Q15((ra.H[_x_] s* rb.H[_y_]) >> 15); ; (RV32: (_x,y_)=(1,0), (0,1), + ; RV64: (_x,y_)=(3,2),(2,3),(1,0), (0,1)) +:khmx16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x4b unimpl + + +# khmx8 rt, ra, rb ; rt.B[_x_] = SAT.Q7((ra.B[_x_] s* rb.B[_y_]) >> 7); ; (RV32: (_x,y_)=(3,2),(2,3),(1,0), (0,1), + ; RV64: (_x,y_)=(7,6),(6,7),(5,4), (4,5), (3,2), (2,3), (1,0), (0,1)) +:khmx8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x4f unimpl + + +# kmabb rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + ra.W[_x_].H[0]*rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0) +:kmabb rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x2d unimpl + + +# kmabt rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + ra.W[_x_].H[0]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0) +:kmabt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x35 unimpl + + +# kmada rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + ra.W[_x_].H[1]*rb.W[_x_].H[1] + ra.W[_x_].H[0]*rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0) +:kmada rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x24 unimpl + + +# kmadrs rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + ra.W[_x_].H[0]*rb.W[_x_].H[0] - ra.W[_x_].H[1]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0) +:kmadrs rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x36 unimpl + + +# kmads rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + ra.W[_x_].H[1]*rb.W[_x_].H[1] - ra.W[_x_].H[0]*rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0) +:kmads rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x2e unimpl + + +# kmar64 rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = SAT.Q63(c64 + ra*rb); + ; + ; r[tU].r[tL] = t64; +:kmar64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x4a unimpl + + +# kmatt rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + ra.W[_x_].H[1]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0) +:kmatt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x3d unimpl + + +# kmaxda rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + ra.W[_x_].H[1]*rb.W[_x_].H[0] + ra.W[_x_].H[0]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0) +:kmaxda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x25 unimpl + + +# kmaxds rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + ra.W[_x_].H[1]*rb.W[_x_].H[0] - ra.W[_x_].H[0]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0) +:kmaxds rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x3e unimpl + + +# kmda rt, ra, rb ; rt.W[_x_] = SAT.Q31(ra.W[_x_].H[1]*rb.W[_x_].H[1] + ra.W[_x_].H[0]*rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0) +:kmda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x1c unimpl + + +# kmmac rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + (ra.W[_x_]*rb.W[_x_])[63:32]); ; (RV32: __x__=0, RV64: __x__=1..0) +:kmmac rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x30 unimpl + + +:kmmac.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x38 unimpl + + +# kmmawb rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + (ra.W[_x_]*rb.W[_x_].H[0])[47:16]); ; (RV32: __x__=0, RV64: __x__=1..0) +:kmmawb rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x23 unimpl + + +:kmmawb.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x2b unimpl + + +# kmmawb2 rt, ra, rb ; a[_x_]=ra.W[_x_]; b[_x_]=rb.W[_x_]; ; if ((a[_x_]==0x80000000) & (b[_x_].L==0x8000)) \{ ; t[_x_]=0x7fffffff; OV=1;} else \{ ; t[_x_]= ((a[_x_]*b[_x_].L)<<1)[47:16]; ; } ; rt.W[_x_] = SAT.Q31(rt.W[x] + t[_x_]); ; (RV32: __x__=0, RV64: __x__=1..0) +:kmmawb2 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x67 unimpl + + +:kmmawb2.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x6e unimpl + + +# kmmawt rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] + (ra.W[_x_]*rb.W[_x_].H[1])[47:16]); ; (RV32: __x__=0, RV64: __x__=1..0) +:kmmawt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x33 unimpl + + +:kmmawt.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x3b unimpl + + +# kmmsb rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] - (ra.W[_x_]*rb.W[_x_])[63:32]); ; (RV32: __x__=0, RV64: __x__=1..0) +:kmmsb rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x21 unimpl + + +:kmmsb.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x29 unimpl + + +# kmmwb2 rt, ra, rb ; a[_x_]=ra.W[_x_]; b[_x_]=rb.W[_x_]; ; if ((a[_x_]==0x80000000) & (b[_x_].L==0x8000)) \{ ; t[_x_]=0x7fffffff; OV=1;} else \{ ; t[_x_]= ((a[_x_]*b[_x_].L)<<1)[47:16]; ; } ; rt.W[_x_] = t[_x_]; ; (RV32: __x__=0, RV64: __x__=1..0) +:kmmwb2 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x47 unimpl + + +:kmmwb2.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x4f unimpl + + +# kmmwt2 rt, ra, rb ; a[_x_]=ra.W[_x_]; b[_x_]=rb.W[_x_]; ; if ((a[_x_]==0x80000000) & (b[_x_].H==0x8000)) \{ ; t[_x_]=0x7fffffff; OV=1;} else \{ ; t[_x_]= ((a[_x_]*b[_x_].H)<<1)[47:16]; ; } ; rt.W[_x_] = t[_x_]; ; (RV32: __x__=0, RV64: __x__=1..0) +:kmmwt2 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x57 unimpl + + +# kmmwt2 rt, ra, rb ; a[_x_]=ra.W[_x_]; b[_x_]=rb.W[_x_]; ; if ((a[_x_]==0x80000000) & (b[_x_].H==0x8000)) \{ ; t[_x_]=0x7fffffff; OV=1;} else \{ ; t[_x_]= ((a[_x_]*b[_x_].H)<<1)[47:16]; ; } ; rt.W[_x_] = t[_x_]; ; (RV32: __x__=0, RV64: __x__=1..0) +:kmmwt2 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x77 unimpl + + +:kmmwt2.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x5f unimpl + + +:kmmwt2.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x7f unimpl + + +# kmsda rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] - ra.W[_x_].H[1]*rb.W[_x_].H[1] - ra.W[_x_].H[0]*rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0) +:kmsda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x26 unimpl + + +# kmsr64 rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = SAT.Q63(c64 – ra*rb); + ; + ; r[tU].r[tL] = t64; +:kmsr64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x4b unimpl + + +# kmsxda rt, ra, rb ; rt.W[_x_] = SAT.Q31(rt.W[_x_] - ra.W[_x_].H[1]*rb.W[_x_].H[0] - ra.W[_x_].H[0]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0) +:kmsxda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x27 unimpl + + +# kmxda rt, ra, rb ; rt.W[_x_] = SAT.Q31(ra.W[_x_].H[1]*rb.W[_x_].H[0] + ra.W[_x_].H[0]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0) +:kmxda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x1d unimpl + + +:ksll rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x13 unimpl + + +# ksll16 rt, ra, rb ; rt.H[_x_] = SAT.Q15(ra.H[_x_] << im4u); ; (RV32: __x__=1..0, RV64: __x__=3..0) +:ksll16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x32 unimpl + + +# ksll8 rt, ra, rb ; rt.B[_x_] = SAT.Q7(ra.B[_x_] << rb[2:0]); ; (RV32: __x__=3..0, RV64: __x__=7..0) +:ksll8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x36 unimpl + + +:kslli rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x1b unimpl + + +# kslra16 rt, ra, rb ; if (rb[4:0] < 0) + ; rt.H[_x_] = ra.H[_x_] s>> -rb[4:0]; ; if (rb[4:0] > 0) + ; rt.H[_x_] = SAT.Q15(ra.H[_x_] << rb[4:0]); ; (RV32: __x__=1..0, RV64: __x__=3..0) +:kslra16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x2b unimpl + + +:kslra16.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x33 unimpl + + +# kslra8 rt, ra, rb ; if (rb[3:0] < 0) + ; rt.B[_x_] = ra.B[_x_] s>> -rb[3:0]; ; if (rb[3:0] > 0) + ; rt.B[_x_] = SAT.Q7(ra.B[_x_] << rb[3:0]); ; (RV32: __x__=3..0, RV64: __x__=7..0) +:kslra8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x2f unimpl + + +:kslra8.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x37 unimpl + + +:kslraw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x37 unimpl + + +:kslraw.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x3f unimpl + + +# ksub16 rt, ra, rb ; rt.H[_x_] = SAT.Q15(ra.H[_x_] - rb.H[_x_]); ; (RV32: __x__=1..0, RV64: __x__=3..0) +:ksub16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x09 unimpl + + +# ksub64 rt, ra, rb ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = SAT.Q63(a64 - b64); + ; + ; r[tU].r[tL] = t64; +:ksub64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x49 unimpl + + +# ksub8 rt, ra, rb ; rt.B[_x_] = SAT.Q7(ra.B[_x_] - rb.B[_x_]); ; (RV32: __x__=3..0, RV64: __x__=7..0) +:ksub8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x0d unimpl + + +:ksubh rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x03 unimpl + + +:ksubw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x01 unimpl + + +# kwmmul rt, ra, rb ; rt.W[_x_] = SAT.Q31((ra.W[_x_]*rb.W[_x_] << 1)[63:32]); ; (RV32: __x__=0, RV64: __x__=1..0) +:kwmmul rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x31 unimpl + + +:kwmmul.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x39 unimpl + + +# maddr32 rt, ra, tb ; 11 +:maddr32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x62 unimpl + + +# maxw rt, ra, rb ; if (ra.W[0] >= rb.W[0]) \{ ; rt = SE(ra.W[0]); ; else \{ ; rt = SE(rb.W[0]); ; } +:maxw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x79 unimpl + + +# minw rt, ra, rb ; if (ra.W[0] >= rb.W[0]) \{ ; rt = SE(rb.W[0]); ; else \{ ; rt = SE(ra.W[0]); ; } +:minw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x78 unimpl + + +# msubr32 rt, ra, tb ; === ; <<< ; === RV64 Only Instructions ; The following tables list instructions that are only present in RV64. ; There are 30 SIMD 32-bit addition or subtraction instructions. ; .(RV64 Only) SIMD 32-bit Add/Subtract Instructions ; [cols="^.^1,<.^2,<.^2,<.^4",options="header",] +:msubr32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x63 unimpl + + +:mtlbi rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x7c unimpl + + +:mtlei rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x7d unimpl + + +# mulr64 rt, ra, rb ; RV32: ; mres[63:0] = ra u* rb; ; r[tU] = mres.W[1]; ; r[tL] = mres.W[0]; ; RV64: ; rt = ra.W[0] u* rb.W[0]; +:mulr64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x78 unimpl + + +# mulsr64 rt, ra, rb ; RV32: ; mres[63:0] = ra s* rb; ; r[tU] = mres.W[1]; ; r[tL] = mres.W[0]; ; RV64: ; rt = ra.W[0] s* rb.W[0]; +:mulsr64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x70 unimpl + + +:oneop rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x56 unimpl + + +:oneop2 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x57 unimpl + + +# pbsad rt, ra, rb ; absdiff[_x_] = ABS(ra.B[_x_] – rb.B[_x_]); ; rt = SUM(absdiff[_x_]); ; (RV32: __x__=3..0, RV64: __x__=7..0) +:pbsad rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x7e unimpl + + +# pbsada rt, ra, rb ; absdiff[_x_] = ABS(ra.B[_x_] – rb.B[_x_]); ; rt = rt + SUM(absdiff[_x_]); ; (RV32: __x__=3..0, RV64: __x__=7..0) +:pbsada rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x7f unimpl + + +# pkbb16 rt, ra, rb ; rt.W[_x_] = CONCAT(ra.W[_x_].H[0], rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0) +:pkbb16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x07 unimpl + + +# pkbt16 rt, ra, rb ; rt.W[_x_] = CONCAT(ra.W[_x_].H[0], rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0) +:pkbt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x0f unimpl + + +# pktb16 rt, ra, rb ; rt.W[_x_] = CONCAT(ra.W[_x_].H[1], rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0) +:pktb16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x1f unimpl + + +# pktt16 rt, ra, rb ; rt.W[_x_] = CONCAT(ra.W[_x_].H[1], rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0) +:pktt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x17 unimpl + + +# radd16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] + rb.H[_x_]) s>> 1; ; (RV32: __x__=1..0, RV64: __x__=3..0) +:radd16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x00 unimpl + + +# radd64 rt, ra, rb ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = (a64 + b64) s>>1; + ; + ; r[tU].r[tL] = t64; +:radd64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x40 unimpl + + +# radd8 rt, ra, rb ; rt.B[_x_] = (ra.B[_x_] + rb.B[_x_]) s>> 1; ; (RV32: __x__=3..0, RV64: __x__=7..0) +:radd8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x04 unimpl + + +# raddw rt, ra, rb ; res = (ra.W[0] + rb.W[0]) s>> 1; ; rt = SE(res); +:raddw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x10 unimpl + + +# rcras16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] + rb.H[_x-1_]) s>> 1; + ; rt.H[_x-1_] = (ra.H[_x-1_] – rb.H[_x_]) s>> 1; ; (RV32: __x__=1, RV64: __x__=1,3) +:rcras16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x02 unimpl + + +# rcrsa16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] - rb.H[_x-1_]) s>> 1; + ; rt.H[_x-1_] = (ra.H[_x-1_] + rb.H[_x_]) s>> 1; ; (RV32: __x__=1, RV64: __x__=1,3) +:rcrsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x03 unimpl + + +# rsub16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] - rb.H[_x_]) s>> 1; ; (RV32: __x__=1..0, RV64: __x__=3..0) +:rsub16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x01 unimpl + + +# rsub64 rt, ra, rb ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = (a64 - b64) s>>1; + ; + ; r[tU].r[tL] = t64; +:rsub64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x41 unimpl + + +# rsub8 rt, ra, rb ; rt.B[_x_] = (ra.B[_x_] - rb.B[_x_]) s>> 1; ; (RV32: __x__=3..0, RV64: __x__=7..0) +:rsub8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x05 unimpl + + +# rsubw rt, ra, rb ; res = (ra.W[0] - rb.W[0]) s>> 1; ; rt = SE(res); +:rsubw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x11 unimpl + + +:sclip16 rd,rs1,imm4u is op0006=0x3f & rd & rs1 & imm4u & op2424=0 & funct3=0x0 & funct7=0x42 unimpl + +:uclip16 rd,rs1,imm4u is op0006=0x3f & rd & rs1 & imm4u & op2424=1 & funct3=0x0 & funct7=0x42 unimpl + + +# sclip32 rt, ra, imm5u ; n = imm5u; + ; rt = SAT.Qn(ra.W[_x_]); ; (RV32: __x__=0, RV64: __x__=1..0) +:sclip32 rd,rs1,imm5u is op0006=0x3f & rd & rs1 & imm5u & funct3=0x0 & funct7=0x72 unimpl + + +:sclip8 rd,rs1,imm3u is op0006=0x3f & rd & rs1 & imm3u & op2324=0 & funct3=0x0 & funct7=0x46 unimpl + +:uclip8 rd,rs1,imm3u is op0006=0x3f & rd & rs1 & imm3u & op2324=2 & funct3=0x0 & funct7=0x46 unimpl + + +# scmple16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] {le} rb.H[_x_])? 0xffff : 0; ; (RV32: __x__=1..0, RV64: __x__=3..0) +:scmple16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x0e unimpl + + +# scmple8 rt, ra, rb ; rt.B[_x_] = (ra.B[_x_] {le} rb.B[_x_])? 0xff : 0; ; (RV32: __x__=3..0, RV64: __x__=7..0) +:scmple8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x0f unimpl + + +# scmplt16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] < rb.H[_x_])? 0xffff : 0; ; (RV32: __x__=1..0, RV64: __x__=3..0) +:scmplt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x06 unimpl + + +# scmplt8 rt, ra, rb ; rt.B[_x_] = (ra.B[_x_] < rb.B[_x_])? 0xff : 0; ; (RV32: __x__=3..0, RV64: __x__=7..0) +:scmplt8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x07 unimpl + + +# sll16 rt, ra, rb ; rt.H[_x_] = ra.H__x__ << rb[3:0]; ; (RV32: __x__=1..0, RV64: __x__=3..0) +:sll16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x2a unimpl + + +# sll8 rt, ra, rb ; rt.B[_x_] = ra.B[_x_] << rb[2:0]; ; (RV32: __x__=3..0, RV64: __x__=7..0) +:sll8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x2e unimpl + + +:slli16 rd,rs1,imm4u is op0006=0x3f & rd & rs1 & imm4u & op2424=0 & funct3=0x0 & funct7=0x3a unimpl + + +:kslli16 rd,rs1,imm4u is op0006=0x3f & rd & rs1 & imm4u & op2424=1 & funct3=0x0 & funct7=0x3a unimpl + + +:slli8 rd,rs1,imm3u is op0006=0x3f & rd & rs1 & imm3u & op2324=0 & funct3=0x0 & funct7=0x3e unimpl + + +:kslli8 rd,rs1,imm3u is op0006=0x3f & rd & rs1 & imm3u & op2324=1 & funct3=0x0 & funct7=0x3e unimpl + + +# smal rt, ra, rb ; RV32: ; a64 = r[aU].r[aL]; + ; t64 = a64 + rb.W[_0_].H[1]*rb.W[_0_].H[0]; + ; r[tU].r[tL] = t64; ; RV64: ; a64 = ra; + ; rt = a64 + rb.W[_1_].H[1]*rb.W[_1_].H[0] + rb.W[_0_].H[1]*rb.W[_0_].H[0]; +:smal rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x2f unimpl + + +# smalbb rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra.L*rb.L; + ; + ; r[tU].r[tL] = t64; +:smalbb rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x44 unimpl + + +# smalbt rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra.L*rb.H; + ; + ; r[tU].r[tL] = t64; +:smalbt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x4c unimpl + + +# smalda rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra.H*rb.H + ra.L*rb.L; + ; + ; r[tU].r[tL] = t64; +:smalda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x46 unimpl + + +# smaldrs rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra.L*rb.L - ra.H*rb.H; + ; + ; r[tU].r[tL] = t64; +:smaldrs rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x4d unimpl + + +# smalds rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra.H*rb.H - ra.L*rb.L; + ; + ; r[tU].r[tL] = t64; +:smalds rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x45 unimpl + + +# smaltt rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra.H*rb.H; + ; + ; r[tU].r[tL] = t64; +:smaltt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x54 unimpl + + +# smalxda rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra.H*rb.L + ra.L*rb.H; + ; + ; r[tU].r[tL] = t64; +:smalxda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x4e unimpl + + +# smalxds rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra.H*rb.L - ra.L*rb.H; + ; + ; r[tU].r[tL] = t64; +:smalxds rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x55 unimpl + + +# smaqa rt, ra, rb ; rt.W[x] = rt.W[x] + ra.W[x].B[3]*rb.W[x].B[3] + ra.W[x].B[2]*rb.W[x].B[2] ; + ra.W[x].B[1]*rb.W[x].B[1] + ra.W[x].B[0]*rb.W[x].B[0]); ; (RV32: x=0, RV64: x=1..0) ; Elements of ra and rb are signed numbers. +:smaqa rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x64 unimpl + + +# smaqa.su rt, ra, rb ; rt.W[x] = rt.W[x] + ra.W[x].B[3]*rb.W[x].B[3] + ra.W[x].B[2]*rb.W[x].B[2] + ; ra.W[x].B[1]*rb.W[x].B[1] + ra.W[x].B[0]*rb.W[x].B[0]); ; (RV32: x=0, RV64: x=1..0) ; Elements of ra are signed numbers. ; Elements of rb are unsigned numbers. +:smaqa.su rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x65 unimpl + + +# smar64 rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra*rb; // signed + ; + ; r[tU].r[tL] = t64; +:smar64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x42 unimpl + + +# smax16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] > rb.H[_x_])? ra.H[_x_] : rb.H[_x_]; ; (RV32: __x__=1..0, RV64: __x__=3..0) +:smax16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x41 unimpl + + +# smax8 rt, ra, rb ; rt.B[_x_] = (ra.B[_x_] > rb.B[_x_])? ra.B[_x_] : rb.B[_x_]; ; (RV32: __x__=3..0, RV64: __x__=7..0) +:smax8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x45 unimpl + + +# smbb16 rt, ra, rb ; rt.W[_x_] = ra.W[_x_].H[0]*rb.W[_x_].H[0]; ; (RV32: __x__=0, RV64: __x__=1..0) +:smbb16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x04 unimpl + + +# smbt16 rt, ra, rb ; rt.W[_x_] = ra.W[_x_].H[0]*rb.W[_x_].H[1]; ; (RV32: __x__=0, RV64: __x__=1..0) +:smbt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x0c unimpl + + +# smdrs rt, ra, rb ; rt.W[_x_] = (ra.W[_x_].H[0]*rb.W[_x_].H[0]) - (ra.W[_x_].H[1]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0) +:smdrs rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x34 unimpl + + +# smds rt, ra, rb ; rt.W[_x_] = (ra.W[_x_].H[1]*rb.W[_x_].H[1]) - (ra.W[_x_].H[0]*rb.W[_x_].H[0]); ; (RV32: __x__=0, RV64: __x__=1..0) +:smds rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x2c unimpl + + +# smin16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] < rb.H[_x_])? ra.H[_x_] : rb.H[_x_]; ; (RV32: __x__=1..0, RV64: __x__=3..0) +:smin16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x40 unimpl + + +# smin8 rt, ra, rb ; rt.B[_x_] = (ra.B[_x_] < rb.B[_x_])? ra.B[_x_] : rb.B[_x_]; ; (RV32: __x__=3..0, RV64: __x__=7..0) +:smin8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x44 unimpl + + +# smmul rt, ra, rb ; rt.W[_x_] = (ra.W[_x_]*rb.W[_x_])[63:32]; ; (RV32: __x__=0, RV64: __x__=1..0) +:smmul rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x20 unimpl + + +:smmul.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x28 unimpl + + +# smmwb rt, ra, rb ; rt.W[_x_] = (ra.W[_x_]*rb.W[_x_].H[0])[47:16]; ; (RV32: __x__=0, RV64: __x__=1..0) +:smmwb rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x22 unimpl + + +:smmwb.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x2a unimpl + + +# smmwt rt, ra, rb ; rt.W[_x_] = (ra.W[_x_]*rb.W[_x_].H[1])[47:16]; ; (RV32: __x__=0, RV64: __x__=1..0) +:smmwt rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x32 unimpl + + +:smmwt.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x3a unimpl + + +# smslda rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 - ra.H*rb.H - ra.L*rb.L; + ; + ; r[tU].r[tL] = t64; +:smslda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x56 unimpl + + +# smslxda rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 - ra.H*rb.L - ra.L*rb.H; + ; + ; r[tU].r[tL] = t64; +:smslxda rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x5e unimpl + + +# smsr64 rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 - ra*rb; // signed + ; + ; r[tU].r[tL] = t64; +:smsr64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x43 unimpl + + +# smtt16 rt, ra, rb ; rt.W[_x_] = ra.W[_x_].H[1]*rb.W[_x_].H[1]; ; (RV32: __x__=0, RV64: __x__=1..0) +:smtt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x14 unimpl + + +# smul16 rt, ra, rb ; RV32: ; r[tL] = ra.H[_0_] s* rb.H[_0_]; ; r[tH] = ra.H[_1_] s* rb.H[_1_]; ; RV64: ; rt.W[_0_] = ra.H[_0_] s* rb.H[_0_]; ; rt.W[_1_] = ra.H[_1_] s* rb.H[_1_]; +:smul16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x50 unimpl + + +:smul16h rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x60 unimpl + + +# smul8 rt, ra, rb ; RV32: ; r[tL].H[_0_] = ra.B[_0_] s* rb.B[_0_]; ; r[tL].H[_1_] = ra.B[_1_] s* rb.B[_1_]; ; r[tH].H[_0_] = ra.B[_2_] s* rb.B[_2_]; ; r[tH].H[_1_] = ra.B[_3_] s* rb.B[_3_]; ; RV64: ; rt.H[_0_] = ra.B[_0_] s* rb.B[_0_]; ; rt.H[_1_] = ra.B[_1_] s* rb.B[_1_]; ; rt.H[_2_] = ra.B[_2_] s* rb.B[_2_]; ; rt.H[_3_] = ra.B[_3_] s* rb.B[_3_]; +:smul8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x54 unimpl + + +# smulx16 rt, ra, rb ; RV32: ; r[tL] = ra.H[_0_] s* rb.H[_1_]; ; r[tH] = ra.H[_1_] s* rb.H[_0_]; ; RV64: ; rt.W[_0_] = ra.H[_0_] s* rb.H[_1_]; ; rt.W[_1_] = ra.H[_1_] s* rb.H[_0_]; +:smulx16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x51 unimpl + + +:smulx16h rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x61 unimpl + + +# smulx8 rt, ra, rb ; RV32: ; r[tL].H[_0_] = ra.B[_0_] s* rb.B[_1_]; ; r[tL].H[_1_] = ra.B[_1_] s* rb.B[_0_]; ; r[tH].H[_0_] = ra.B[_2_] s* rb.B[_3_]; ; r[tH].H[_1_] = ra.B[_3_] s* rb.B[_2_]; ; RV64: ; rt.H[_0_] = ra.B[_0_] s* rb.B[_1_]; ; rt.H[_1_] = ra.B[_1_] s* rb.B[_0_]; ; rt.H[_2_] = ra.B[_2_] s* rb.B[_3_]; ; rt.H[_3_] = ra.B[_3_] s* rb.B[_2_]; +:smulx8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x55 unimpl + + +# smxds rt, ra, rb ; rt.W[_x_] = (ra.W[_x_].H[1]*rb.W[_x_].H[0]) - (ra.W[_x_].H[0]*rb.W[_x_].H[1]); ; (RV32: __x__=0, RV64: __x__=1..0) +:smxds rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x3c unimpl + + +:sra.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x12 unimpl + + +# sra16 rt, ra, rb ; rt.H[_x_] = ra.H[_x_] s>> rb[3:0]; ; (RV32: __x__=1..0, RV64: __x__=3..0) +:sra16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x28 unimpl + + +:sra16.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x30 unimpl + + +# sra8 rt, ra, rb ; rt.B[_x_] = ra.B[_x_] s>> rb[2:0]; ; (RV32: __x__=3..0, RV64: __x__=7..0) +:sra8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x2c unimpl + + +:sra8.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x34 unimpl + + +:srai.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x6a unimpl + + +:srai16 rd,rs1,imm4u is op0006=0x3f & rd & rs1 & imm4u & op2424=0 & funct3=0x0 & funct7=0x38 unimpl + + +:srai16.u rd,rs1,imm4u is op0006=0x3f & rd & rs1 & imm4u & op2424=1 & funct3=0x0 & funct7=0x38 unimpl + + +:srai8 rd,rs1,imm3u is op0006=0x3f & rd & rs1 & imm3u & op2324=0 & funct3=0x0 & funct7=0x3c unimpl + + +:srai8.u rd,rs1,imm3u is op0006=0x3f & rd & rs1 & imm3u & op2324=1 & funct3=0x0 & funct7=0x3c unimpl + + +:sraiw.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x1a unimpl + + +# srl16 rt, ra, rb ; rt.H[_x_] = ra.H[_x_] u>> rb[3:0]; ; (RV32: __x__=1..0, RV64: __x__=3..0) +:srl16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x29 unimpl + + +:srl16.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x31 unimpl + + +# srl8 rt, ra, rb ; rt.B[_x_] = ra.B[_x_] u>> rb[2:0]; ; (RV32: __x__=3..0, RV64: __x__=7..0) +:srl8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x2d unimpl + + +:srl8.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x35 unimpl + + +:srli16 rd,rs1,imm4u is op0006=0x3f & rd & rs1 & imm4u & op2424=0 & funct3=0x0 & funct7=0x39 unimpl + + +:srli16.u rd,rs1,imm4u is op0006=0x3f & rd & rs1 & imm4u & op2424=1 & funct3=0x0 & funct7=0x39 unimpl + + +:srli8 rd,rs1,imm3u is op0006=0x3f & rd & rs1 & imm3u & op2324=0 & funct3=0x0 & funct7=0x3d unimpl + + +:srli8.u rd,rs1,imm3u is op0006=0x3f & rd & rs1 & imm3u & op2324=1 & funct3=0x0 & funct7=0x3d unimpl + + +# sub16 rt, ra, rb ; rt.H[_x_] = ra.H[_x_] - rb.H[_x_]; ; (RV32: __x__=1..0, RV64: __x__=3..0) +:sub16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x21 unimpl + + +# sub64 rt, ra, rb ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = a64 - b64; + ; + ; r[tU].r[tL] = t64; +:sub64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x61 unimpl + + +# sub8 rt, ra, rb ; rt.B[_x_] = ra.B[_x_] - rb.B[_x_]; ; (RV32: __x__=3..0, RV64: __x__=7..0) +:sub8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x25 unimpl + + +# sunpkd810 rt, ra ; rt.H[_x_] = SE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,1), (0,0) ; RV64: (_x,y_) = (3,5),(2,4),(1,1), (0,0) +:sunpkd810 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x08 unimpl + + +# sunpkd820 rt, ra ; rt.H[_x_] = SE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,2), (0,0) ; RV64: (_x,y_) = (3,6),(2,4),(1,2), (0,0) +:sunpkd820 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x09 unimpl + + +# sunpkd830 rt, ra ; rt.H[_x_] = SE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,3), (0,0) ; RV64: (_x,y_) = (3,7),(2,4),(1,3), (0,0) +:sunpkd830 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x0a unimpl + + +# sunpkd831 rt, ra ; rt.H[_x_] = SE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,3), (0,1) ; RV64: (_x,y_) = (3,7),(2,5),(1,3), (0,1) +:sunpkd831 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x0b unimpl + + +# sunpkd832 rt, ra ; rt.H[_x_] = SE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,3), (0,2) ; RV64: (_x,y_) = (3,7),(2,6),(1,3), (0,2) +:sunpkd832 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x13 unimpl + + +# swap16 rt, ra ; === ; <<< ; ==== 8-bit Misc Instructions ; There are 11 instructions here. ; .SIMD 8-bit Miscellaneous Instructions ; [cols="^.^1,<.^2,<.^2,<.^4",options="header",] +:swap16 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x19 unimpl + + +# swap8 rt, ra ; === ; <<< ; ==== 8-bit Unpacking Instructions ; There are 8 instructions here. ; .8-bit Unpacking Instructions ; [cols="^.^1,<.^2,<.^2,<.^4",options="header",] +:swap8 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x18 unimpl + + +# uclip32 rt, ra, imm5u ; m = imm5u; + ; rt = SAT.Um(ra.W[_x_]); ; (RV32: __x__=0, RV64: __x__=1..0) +:uclip32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x7a unimpl + + +# ucmple16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] u{le} rb.H[_x_])? 0xffff : 0; ; (RV32: __x__=1..0, RV64: __x__=3..0) +:ucmple16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x1e unimpl + + +# ucmple8 rt, ra, rb ; rt.B[_x_] = (ra.B[_x_] u{le} rb.B[_x_])? 0xff : 0; ; (RV32: __x__=3..0, RV64: __x__=7..0) +:ucmple8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x1f unimpl + + +# ucmplt16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] u< rb.H[_x_])? 0xffff : 0; ; (RV32: __x__=1..0, RV64: __x__=3..0) +:ucmplt16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x16 unimpl + + +# ucmplt8 rt, ra, rb ; rt.B[_x_] = (ra.B[_x_] u< rb.B[_x_])? 0xff : 0; ; (RV32: __x__=3..0, RV64: __x__=7..0) +:ucmplt8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x17 unimpl + + +# ukadd16 rt, ra, rb ; rt.H[_x_] = SAT.U16(ra.H[_x_] + rb.H[_x_]; ; (RV32: __x__=1..0, RV64: __x__=3..0) +:ukadd16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x18 unimpl + + +# ukadd64 rt, ra, rb ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = SAT.U64(a64 + b64); + ; + ; r[tU].r[tL] = t64; +:ukadd64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x58 unimpl + + +# ukadd8 rt, ra, rb ; rt.B[_x_] = SAT.U8(ra.B[_x_] + rb.B[_x_]); ; (RV32: __x__=3..0, RV64: __x__=7..0) +:ukadd8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x1c unimpl + + +:ukaddh rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x0a unimpl + + +:ukaddw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x08 unimpl + + +# ukcras16 rt, ra, rb ; rt.H[_x_] = SAT.U16(ra.H[_x_] + rb.H[_x-1_]); + ; rt.H[_x-1_] = SAT.U16(ra.H[_x-1_] – rb.H[_x_]); ; (RV32: __x__=1, RV64: __x__=1,3) +:ukcras16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x1a unimpl + + +# ukcrsa16 rt, ra, rb ; rt.H[_x_] = SAT.U16(ra.H[_x_] - rb.H[_x-1_]); + ; rt.H[_x-1_] = SAT.U16(ra.H[_x-1_] + rb.H[_x_]); ; (RV32: __x__=1, RV64: __x__=1,3) +:ukcrsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x1b unimpl + + +# ukmar64 rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = SAT.U64(c64 + ra*rb); + ; + ; r[tU].r[tL] = t64; +:ukmar64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x5a unimpl + + +# ukmsr64 rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = SAT.U64(c64 - ra*rb); + ; + ; r[tU].r[tL] = t64; +:ukmsr64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x5b unimpl + + +# uksub16 rt, ra, rb ; rt.H[_x_] = SAT.U16(ra.H[_x_] - rb.H[_x_]); ; (RV32: __x__=1..0, RV64: __x__=3..0) +:uksub16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x19 unimpl + + +# uksub64 rt, ra, rb ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = SAT.U64(a64 - b64); + ; + ; r[tU].r[tL] = t64; +:uksub64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x59 unimpl + + +# uksub8 rt, ra, rb ; rt.B[_x_] = SAT.U8(ra.B[_x_] - rb.B[_x_]); ; (RV32: __x__=3..0, RV64: __x__=7..0) +:uksub8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x1d unimpl + + +:uksubh rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x0b unimpl + + +:uksubw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x09 unimpl + + +# umaqa rt, ra, rb ; rt.W[x] = rt.W[x] + ra.W[x].B[3]*rb.W[x].B[3] + ra.W[x].B[2]*rb.W[x].B[2] ; + ra.W[x].B[1]*rb.W[x].B[1] + ra.W[x].B[0]*rb.W[x].B[0]); ; (RV32: x=0, RV64: x=1..0) ; Elements of ra and rb are unsigned numbers. +:umaqa rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x66 unimpl + + +# umar64 rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 + ra*rb; // unsigned + ; + ; r[tU].r[tL] = t64; +:umar64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x52 unimpl + + +# umax16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] u> rb.H[_x_])? ra.H[_x_] : rb.H[_x_]; ; (RV32: __x__=1..0, RV64: __x__=3..0) +:umax16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x49 unimpl + + +# umax8 rt, ra, rb ; rt.B[_x_] = (ra.B[_x_] u> rb.B[_x_])? ra.B[_x_] : rb.B[_x_]; ; (RV32: __x__=3..0, RV64: __x__=7..0) +:umax8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x4d unimpl + + +# umin16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] u< rb.H[_x_])? ra.H[_x_] : rb.H[_x_]; ; (RV32: __x__=1..0, RV64: __x__=3..0) +:umin16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x48 unimpl + + +# umin8 rt, ra, rb ; rt.B[_x_] = (ra.B[_x_] u< rb.B[_x_])? ra.B[_x_] : rb.B[_x_]; ; (RV32: __x__=3..0, RV64: __x__=7..0) +:umin8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x4c unimpl + + +# umsr64 rt, ra, rb ; c64 = r[tU].r[tL]; + ; + ; t64 = c64 - ra*rb; // unsigned + ; + ; r[tU].r[tL] = t64; +:umsr64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x53 unimpl + + +# umul16 rt, ra, rb ; RV32: ; r[tL] = ra.H[_0_] u* rb.H[_0_]; ; r[tH] = ra.H[_1_] u* rb.H[_1_]; ; RV64: ; rt.W[_0_] = ra.H[_0_] u* rb.H[_0_]; ; rt.W[_1_] = ra.H[_1_] u* rb.H[_1_]; +:umul16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x58 unimpl + + +:umul16h rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x68 unimpl + + +# umul8 rt, ra, rb ; RV32: ; r[tL].H[_0_] = ra.B[_0_] u* rb.B[_0_]; ; r[tL].H[_1_] = ra.B[_1_] u* rb.B[_1_]; ; r[tH].H[_0_] = ra.B[_2_] u* rb.B[_2_]; ; r[tH].H[_1_] = ra.B[_3_] u* rb.B[_3_]; ; RV64: ; rt.H[_0_] = ra.B[_0_] u* rb.B[_0_]; ; rt.H[_1_] = ra.B[_1_] u* rb.B[_1_]; ; rt.H[_2_] = ra.B[_2_] u* rb.B[_2_]; ; rt.H[_3_] = ra.B[_3_] u* rb.B[_3_]; +:umul8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x5c unimpl + + +# umulx16 rt, ra, rb ; RV32: ; r[tL] = ra.H[_0_] u* rb.H[_1_]; ; r[tH] = ra.H[_1_] u* rb.H[_0_]; ; RV64: ; rt.W[_0_] = ra.H[_0_] u* rb.H[_1_]; ; rt.W[_1_] = ra.H[_1_] u* rb.H[_0_]; +:umulx16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x59 unimpl + + +:umulx16h rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x69 unimpl + + +# umulx8 rt, ra, rb ; RV32: ; r[tL].H[_0_] = ra.B[_0_] u* rb.B[_1_]; ; r[tL].H[_1_] = ra.B[_1_] u* rb.B[_0_]; ; r[tH].H[_0_] = ra.B[_2_] u* rb.B[_3_]; ; r[tH].H[_1_] = ra.B[_3_] u* rb.B[_2_]; ; RV64: ; rt.H[_0_] = ra.B[_0_] u* rb.B[_1_]; ; rt.H[_1_] = ra.B[_1_] u* rb.B[_0_]; ; rt.H[_2_] = ra.B[_2_] u* rb.B[_3_]; ; rt.H[_3_] = ra.B[_3_] u* rb.B[_2_]; +:umulx8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x5d unimpl + + +# uradd16 rt, ra, rb ; rt.H[_x_] = (CONCAT(1'b0,ra.H[_x_]) + CONCAT(1'b0,rb.H[_x_])) >> 1; ; (RV32: __x__=1..0, RV64: __x__=3..0) +:uradd16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x10 unimpl + + +# uradd64 rt, ra, rb ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = (CONCAT(1'b0,a64) + CONCAT(1'b0,b64)) >>1; + ; + ; r[tU].r[tL] = t64; +:uradd64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x50 unimpl + + +# uradd8 rt, ra, rb ; rt.B[_x_] = (CONCAT(1'b0,ra.B[_x_]) + CONCAT(1'b0,rb.B[_x_])) >> 1; ; (RV32: __x__=3..0, RV64: __x__=7..0) +:uradd8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x14 unimpl + + +# uraddw rt, ra, rb ; res = (CONCAT(1'b0,ra.W[0]) + CONCAT(1'b0,rb.W[0])) >> 1; ; rt = SE(res); +:uraddw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x18 unimpl + + +# urcras16 rt, ra, rb ; rt.H[_x_] = (CONCAT(1'b0,ra.H[_x_]) + CONCAT(1'b0,rb.H[_x-1_])) >> 1; + ; rt.H[_x-1_] = (CONCAT(1'b0,ra.H[_x-1_]) – CONCAT(1'b0,rb.H[_x_])) >> 1; ; (RV32: __x__=1, RV64: __x__=1,3) +:urcras16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x12 unimpl + + +# urcrsa16 rt, ra, rb ; rt.H[_x_] = (CONCAT(1'b0,ra.H[_x_]) - CONCAT(1'b0,rb.H[_x-1_])) >> 1; + ; rt.H[_x-1_] = (CONCAT(1'b0,ra.H[_x-1_]) + CONCAT(1'b0,rb.H[_x_])) >> 1; ; (RV32: __x__=1, RV64: __x__=1,3) +:urcrsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x13 unimpl + + +# ursub16 rt, ra, rb ; rt.H[_x_] = (CONCAT(1'b0,ra.H[_x_]) - CONCAT(1'b0,rb.H[_x_])) >> 1; ; (RV32: __x__=1..0, RV64: __x__=3..0) +:ursub16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x11 unimpl + + +# ursub64 rt, ra, rb ; a64 = r[aU].r[aL]; b64 = r[bU].r[bL]; + ; + ; t64 = (CONCAT(1'b0,a64) - CONCAT(1'b0,b64)) >>1; + ; + ; r[tU].r[tL] = t64; +:ursub64 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x51 unimpl + + +# ursub8 rt, ra, rb ; rt.B[_x_] = (CONCAT(1'b0,ra.B[_x_]) - CONCAT(1'b0,rb.B[_x_])) >> 1; ; (RV32: __x__=3..0, RV64: __x__=7..0) +:ursub8 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x15 unimpl + + +# ursubw rt, ra, rb ; res = (CONCAT(1'b0,ra.W[0]) - CONCAT(1'b0,rb.W[0])) >> 1; ; rt = SE(res); +:ursubw rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x1 & funct7=0x19 unimpl + + +# wext rt, ra, rb ; a64 = r[aU].r[aL]; // RV32 ; a64 = ra; // RV64 ; lsb = rb[4:0]; ; exword = a64[(31+lsb):lsb]; ; rt = SE(exword); +:wext rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x67 unimpl + + +# wexti rt, ra, imm5u ; a64 = r[aU].r[aL]; // RV32 ; a64 = ra; // RV64 ; lsb = imm5u; ; exword = a64[(31+lsb):lsb]; ; rt = SE(exword); +:wexti rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x0 & funct7=0x6f unimpl + + +# zunpkd810 rt, ra ; rt.H[_x_] = ZE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,1), (0,0) ; RV64: (_x,y_) = (3,5),(2,4),(1,1), (0,0) +:zunpkd810 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x0c unimpl + + +# zunpkd820 rt, ra ; rt.H[_x_] = ZE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,2), (0,0) ; RV64: (_x,y_) = (3,6),(2,4),(1,2), (0,0) +:zunpkd820 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x0d unimpl + + +# zunpkd830 rt, ra ; rt.H[_x_] = ZE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,3), (0,0) ; RV64: (_x,y_) = (3,7),(2,4),(1,3), (0,0) +:zunpkd830 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x0e unimpl + + +# zunpkd831 rt, ra ; rt.H[_x_] = ZE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,3), (0,1) ; RV64: (_x,y_) = (3,7),(2,5),(1,3), (0,1) +:zunpkd831 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x0f unimpl + + +# zunpkd832 rt, ra ; rt.H[_x_] = ZE16(ra.B[_y_]); ; RV32: (_x,y_) = (1,3), (0,2) ; RV64: (_x,y_) = (3,7),(2,6),(1,3), (0,2) +:zunpkd832 rd,rs1 is op0006=0x3f & rd & rs1 & funct3=0x0 & funct7=0x56 & subf5=0x17 unimpl + + diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32q.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32q.sinc new file mode 100644 index 0000000..b033986 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv32q.sinc @@ -0,0 +1,236 @@ +# RV32Q Standard Extension + +# fadd.q D,S,T,m 06000053 fe00007f SIMPLE (0, 0) +:fadd.q frd,frs1,frs2,FRM is frs1 & frd & frs2 & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x3 +{ + frd = frs1 f+ frs2; +} + +# fclass.q d,S e6001053 fff0707f SIMPLE (0, 0) +:fclass.q rd,frs1 is frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x73 & op2024=0x0 +{ + #TODO + # rd = 0; + # rd[0, 1] = 0; #TODO - inf + # rd[1, 1] = 0; #TODO - norm num + # rd[2, 1] = 0; #TODO - subnorm num + # rd[3, 1] = 0; #TODO - 0 + # rd[4, 1] = 0; #TODO + 0 + # rd[5, 1] = 0; #TODO + norm num + # rd[6, 1] = 0; #TODO + subnorm num + # rd[7, 1] = 0; #TODO + inf + # rd[8, 1] = 0; #TODO snan + # rd[9, 1] = 0; #TODO qnan +} + + + +# fcvt.d.q D,S,m 42300053 fff0007f SIMPLE (0, 0) +:fcvt.d.q frd,frs1,FRM is frs1 & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x21 & op2024=0x3 +{ + #TODO double to quad +} + +# fcvt.q.d D,S 46100053 fff0707f SIMPLE (0, 0) +:fcvt.q.d frd,frs1 is frs1 & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x23 & op2024=0x1 +{ + frd = float2float(frs1); +} + +# fcvt.q.s D,S 46000053 fff0707f SIMPLE (0, 0) +:fcvt.q.s frd,frs1 is frs1 & frd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x23 & op2024=0x0 +{ + frd = float2float(frs1); +} + +# fcvt.q.w D,s d6000053 fff0707f SIMPLE (0, 0) +:fcvt.q.w frd,rs1 is frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x6b & op2024=0x0 +{ + frd = int2float(rs1); +} + +# fcvt.q.wu D,s d6100053 fff0707f SIMPLE (0, 0) +:fcvt.q.wu frd,rs1 is frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x6b & op2024=0x1 +{ + frd = int2float(rs1); +} + +# fcvt.s.q D,S,m 40300053 fff0007f SIMPLE (0, 0) +:fcvt.s.q frd,frs1,FRM is frs1 & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x20 & op2024=0x3 +{ + frd = float2float(frs1); +} + +# fcvt.w.q d,S,m c6000053 fff0007f SIMPLE (0, 0) +:fcvt.w.q rd,frs1,FRM is frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x0 +{ + rd = trunc(frs1); +} + +# fcvt.wu.q d,S,m c6100053 fff0007f SIMPLE (0, 0) +:fcvt.wu.q rd,frs1,FRM is frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x1 +{ + rd = trunc(frs1); +} + + +# fdiv.q D,S,T,m 1e000053 fe00007f SIMPLE (0, 0) +:fdiv.q frd,frs1,frs2,FRM is frs1 & frd & frs2 & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xf +{ + local tfrs1:$(QFLEN) = frs1; + local tfrs2:$(QFLEN) = frs2; + local result:$(QFLEN) = tfrs1 f/ tfrs2; + frd = result; +} + + +# feq.q d,S,T a6002053 fe00707f SIMPLE (0, 0) +:feq.q rd,frs1,frs2 is frs2 & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x53 +{ + rd = zext(frs1 f== frs2); +} + + +# fle.q d,S,T a6000053 fe00707f SIMPLE (0, 0) +:fle.q rd,frs1,frs2 is frs2 & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x53 +{ + rd = zext(frs1 f<= frs2); +} + +# flq D,o(s) 00004007 0000707f OWORD|DREF (0, 16) +:flq frd,immI(rs1) is immI & frd & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x0 & funct3=0x4 +{ + local ea:$(XLEN) = immI + rs1; + frd = *[ram]:16 ea; +} + + +# flt.q d,S,T a6001053 fe00707f SIMPLE (0, 0) +:flt.q rd,frs1,frs2 is frs2 & frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x53 +{ + rd = zext(frs1 f< frs2); +} + + + +# fmadd.q D,S,T,R,m 06000043 0600007f SIMPLE (0, 0) +:fmadd.q frd,frs1,frs2,frs3,FRM is frs1 & frd & frs2 & FRM & frs3 & op0001=0x3 & op0204=0x0 & op0506=0x2 & op2526=0x3 +{ + frd = (frs1 f* frs2) f+ frs3; +} + +# fmax.q D,S,T 2e001053 fe00707f SIMPLE (0, 0) +:fmax.q frd,frs1,frs2 is frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x17 +{ + local tmpfrs1 = frs1; + local tmpfrs2 = frs2; + frd = tmpfrs1; + if (nan(tmpfrs1) && nan(tmpfrs2)) goto inst_next; + if (nan(tmpfrs2)) goto inst_next; + frd = tmpfrs2; + if (nan(tmpfrs1)) goto inst_next; + if (tmpfrs2 f> tmpfrs1) goto inst_next; + frd = tmpfrs1; +} + +# fmin.q D,S,T 2e000053 fe00707f SIMPLE (0, 0) +:fmin.q frd,frs1,frs2 is frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x17 +{ + local tmpfrs1 = frs1; + local tmpfrs2 = frs2; + frd = tmpfrs1; + if (nan(tmpfrs1) && nan(tmpfrs2)) goto inst_next; + if (nan(tmpfrs2)) goto inst_next; + frd = tmpfrs2; + if (nan(tmpfrs1)) goto inst_next; + if (tmpfrs2 f<= tmpfrs1) goto inst_next; + frd = tmpfrs1; +} + +# fmsub.q D,S,T,R,m 06000047 0600007f SIMPLE (0, 0) +:fmsub.q frd,frs1,frs2,frs3,FRM is frs1 & frd & frs2 & FRM & frs3 & op0001=0x3 & op0204=0x1 & op0506=0x2 & op2526=0x3 +{ + frd = (frs1 f* frs2) f- frs3; +} + +# fmul.q D,S,T,m 16000053 fe00007f SIMPLE (0, 0) +:fmul.q frd,frs1,frs2,FRM is frs1 & frd & frs2 & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xb +{ + frd = frs1 f* frs2; +} + + +# fmv.q.x D,s f6000053 fff0707f SIMPLE (64, 0) +:fmv.q.x frd,rs1 is frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x7b & op2024=0x0 +{ + frd = int2float(rs1); +} + + +# fmv.x.q d,S e6000053 fff0707f SIMPLE (64, 0) +:fmv.x.q rd,frs1 is frs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x73 & op2024=0x0 +{ + local tmpreg:4 = &frs1; + local tmp:4 = *[register]:4 tmpreg; + assignW(rd, tmp); +} + + +# fnmadd.q D,S,T,R,m 0600004f 0600007f SIMPLE (0, 0) +:fnmadd.q frd,frs1,frs2,frs3,FRM is frs1 & frd & frs2 & FRM & frs3 & op0001=0x3 & op0204=0x3 & op0506=0x2 & op2526=0x3 +{ + frd = (f- (frs1 f* frs2)) f- frs3; +} + +# fnmsub.q D,S,T,R,m 0600004b 0600007f SIMPLE (0, 0) +:fnmsub.q frd,frs1,frs2,frs3,FRM is frs1 & frd & frs2 & FRM & frs3 & op0001=0x3 & op0204=0x2 & op0506=0x2 & op2526=0x3 +{ + frd = (f- (frs1 f* frs2)) f+ frs3; +} + + +# fsgnj.q D,S,T 26000053 fe00707f SIMPLE (0, 0) +:fsgnj.q frd,frs1,frs2 is frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x13 +{ local tmp = frs1; + tmp[127,1] = frs2[127,1]; + frd = tmp; +} + + +# fsgnjn.q D,S,T 26001053 fe00707f SIMPLE (0, 0) +:fsgnjn.q frd,frs1,frs2 is frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x13 +{ + local tmp = frs1; + tmp[127,1] = !frs2[127,1]; + frd = tmp; +} + + +# fsgnjx.q D,S,T 26002053 fe00707f SIMPLE (0, 0) +:fsgnjx.q frd,frs1,frs2 is frs1 & frd & frs2 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x13 +{ + local tmp = frs1; + tmp[127,1] = tmp[127,1] ^ frs2[127,1]; + frd = tmp; +} + + +:fsq frs2,immS(rs1) is frs2 & immS & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x1 & funct3=0x4 +{ + local ea:$(XLEN) = immS + rs1; + *[ram]:$(QFLEN) ea = frs2; +} + + +# fsqrt.q D,S,m 5e000053 fff0007f SIMPLE (0, 0) +:fsqrt.q frd,frs1,FRM is frs1 & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x2f & op2024=0x0 +{ + frd = sqrt(frs1); +} + + +# fsub.q D,S,T,m 0e000053 fe00007f SIMPLE (0, 0) +:fsub.q frd,frs1,frs2,FRM is frs1 & frd & frs2 & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x7 +{ + frd = frs1 f- frs2; +} diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64a.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64a.sinc new file mode 100644 index 0000000..cc9553d --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64a.sinc @@ -0,0 +1,132 @@ +# RV64A Standard Extension (in addition to RV32A) + +# amoadd.d d,t,0(s) 0000302f fe00707f QWORD|DREF (64, 8) +:amoadd.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x0 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2L; + local tmp:8 = *[ram]:8 tmprs1; + rdL = tmp; + tmp = tmp + tmprs2; + *[ram]:8 tmprs1 = tmp; +} + + +# amoand.d d,t,0(s) 6000302f fe00707f QWORD|DREF (64, 8) +:amoand.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0xc & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2L; + local tmp:8 = *[ram]:8 tmprs1; + rdL = tmp; + tmp = tmp & tmprs2; + *[ram]:8 tmprs1 = tmp; +} + + +# amomax.d d,t,0(s) a000302f fe00707f QWORD|DREF (64, 8) +:amomax.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x14 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2L; + local tmp:8 = *[ram]:8 tmprs1; + rdL = tmp; + if (tmprs2 s<= tmp) goto inst_next; + *[ram]:8 tmprs1 = tmprs2; +} + + +# amomaxu.d d,t,0(s) e000302f fe00707f QWORD|DREF (64, 8) +:amomaxu.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x1c & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2L; + local tmp:8 = *[ram]:8 tmprs1; + rdL = tmp; + if (tmprs2 <= tmp) goto inst_next; + *[ram]:8 tmprs1 = tmprs2; +} + + +# amomin.d d,t,0(s) 8000302f fe00707f QWORD|DREF (64, 8) +:amomin.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x10 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2L; + local tmp:8 = *[ram]:8 tmprs1; + rdL = tmp; + if (tmprs2 s>= tmp) goto inst_next; + *[ram]:8 tmprs1 = tmprs2; +} + + +# amominu.d d,t,0(s) c000302f fe00707f QWORD|DREF (64, 8) +:amominu.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x18 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2L; + local tmp:8 = *[ram]:8 tmprs1; + rdL = tmp; + if (tmprs2 >= tmp) goto inst_next; + *[ram]:8 tmprs1 = tmprs2; +} + + +# amoor.d d,t,0(s) 4000302f fe00707f QWORD|DREF (64, 8) +:amoor.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x8 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2L; + local tmp:8 = *[ram]:8 tmprs1; + rdL = tmp; + tmp = tmp | tmprs2; + *[ram]:8 tmprs1 = tmp; +} + + +# amoswap.d d,t,0(s) 0800302f fe00707f QWORD|DREF (64, 8) +:amoswap.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x1 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2L; + local tmp:8 = *[ram]:8 tmprs1; + rdL = tmp; + *[ram]:8 tmprs1 = tmprs2; +} + + +# amoxor.d d,t,0(s) 2000302f fe00707f QWORD|DREF (64, 8) +:amoxor.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x4 & aqrl +{ + local tmprs1 = rs1; + local tmprs2 = rs2L; + local tmp:8 = *[ram]:8 tmprs1; + rdL = tmp; + tmp = tmp ^ tmprs2; + *[ram]:8 tmprs1 = tmp; +} + + +# lr.d d,0(s) 1000302f fff0707f QWORD|DREF (64, 8) +:lr.d^aqrl rdL,(rs1) is rs1 & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x2 & op2024=0x0 & aqrl +{ + RESERVE_ADDRESS = rs1; + RESERVE = 1; + RESERVE_LENGTH = 8; + rdL = *[ram]:8 rs1; +} + + +# sc.d d,t,0(s) 1800302f fe00707f QWORD|DREF (64, 8) +:sc.d^aqrl rdL,rs2L,(rs1) is rs1 & rs2L & rdL & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x3 & op2731=0x3 & aqrl +{ + local tmprs2 = rs2L; + local tmprs1 = rs1; + rdL = 1; + if ((RESERVE == 0)||(RESERVE_ADDRESS != tmprs1)||(RESERVE_LENGTH != 8)) goto inst_next; + *[ram]:8 tmprs1 = tmprs2; + rdL = 0; + RESERVE_ADDRESS = 0; + RESERVE = 0; + RESERVE_LENGTH = 0; +} diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64b.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64b.sinc new file mode 100644 index 0000000..e836096 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64b.sinc @@ -0,0 +1,109 @@ +# RV64 Bitmanip Extension + +#TODO fix op2031 +:addiwu rd, rs1, op2031 is op0006=0x1b & op1214=0x4 & rd & op2031 & rs1 unimpl + +:addu.w rd, rs1, rs2 is op0006=0x3b & op1214=0x0 & op2531=0x4 & rd & rs1 & rs2 unimpl + +:addwu rd, rs1, rs2 is op0006=0x3b & op1214=0x0 & op2531=0x5 & rd & rs1 & rs2 unimpl + +:bdepw rd, rs1, rs2 is op0006=0x3b & op1214=0x6 & op2531=0x24 & rd & rs1 & rs2 unimpl + +:bextw rd, rs1, rs2 is op0006=0x3b & op1214=0x6 & op2531=0x4 & rd & rs1 & rs2 unimpl + +:bfpw rd, rs1, rs2 is op0006=0x3b & op1214=0x7 & op2531=0x24 & rd & rs1 & rs2 unimpl + +:bmatflip rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x3 & op2531=0x30 & rd & rs1 unimpl + +:bmator rd, rs1, rs2 is op0006=0x33 & op1214=0x3 & op2531=0x4 & rd & rs1 & rs2 unimpl + +:bmatxor rd, rs1, rs2 is op0006=0x33 & op1214=0x3 & op2531=0x24 & rd & rs1 & rs2 unimpl + +:clmulhw rd, rs1, rs2 is op0006=0x3b & op1214=0x3 & op2531=0x5 & rd & rs1 & rs2 unimpl + +:clmulrw rd, rs1, rs2 is op0006=0x3b & op1214=0x2 & op2531=0x5 & rd & rs1 & rs2 unimpl + +:clmulw rd, rs1, rs2 is op0006=0x3b & op1214=0x1 & op2531=0x5 & rd & rs1 & rs2 unimpl + +:clzw rd, rs1 is op0006=0x1b & op1214=0x1 & op2024=0x0 & op2531=0x30 & rd & rs1 unimpl + +:crc32.d rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x13 & op2531=0x30 & rd & rs1 unimpl + +:crc32c.d rd, rs1 is op0006=0x13 & op1214=0x1 & op2024=0x1b & op2531=0x30 & rd & rs1 unimpl + +:ctzw rd, rs1 is op0006=0x1b & op1214=0x1 & op2024=0x1 & op2531=0x30 & rd & rs1 unimpl + +:fslw rd, rs1, rs3, rs2 is op0006=0x3b & op1214=0x1 & op2526=0x2 & rd & rs1 & rs2 & rs3 unimpl + +#TODO fix op2024 +:fsriw rd, rs1, rs3, op2024 is op0006=0x1b & op1214=0x5 & op2526=0x2 & op2024 & rd & rs1 & rs3 unimpl + +:fsrw rd, rs1, rs3, rs2 is op0006=0x3b & op1214=0x5 & op2526=0x2 & rd & rs1 & rs2 & rs3 unimpl + +#TODO fix op2024 +:gorciw rd, rs1, op2024 is op0006=0x1b & op1214=0x5 & op2531=0x14 & op2024 & rd & rs1 unimpl + +:gorcw rd, rs1, rs2 is op0006=0x3b & op1214=0x5 & op2531=0x14 & rd & rs1 & rs2 unimpl + +#TODO fix op2024 +:greviw rd, rs1, op2024 is op0006=0x1b & op1214=0x5 & op2531=0x34 & op2024 & rd & rs1 unimpl + +:grevw rd, rs1, rs2 is op0006=0x3b & op1214=0x5 & op2531=0x34 & rd & rs1 & rs2 unimpl + +:packuw rd, rs1, rs2 is op0006=0x3b & op1214=0x4 & op2531=0x24 & rd & rs1 & rs2 unimpl + +:packw rd, rs1, rs2 is op0006=0x3b & op1214=0x4 & op2531=0x4 & rd & rs1 & rs2 unimpl + +:pcntw rd, rs1 is op0006=0x1b & op1214=0x1 & op2024=0x2 & op2531=0x30 & rd & rs1 unimpl + +:rolw rd, rs1, rs2 is op0006=0x3b & op1214=0x1 & op2531=0x30 & rd & rs1 & rs2 unimpl + +#TODO fix op2024 +:roriw rd, rs1, op2024 is op0006=0x1b & op1214=0x5 & op2531=0x30 & op2024 & rd & rs1 unimpl + +:rorw rd, rs1, rs2 is op0006=0x3b & op1214=0x5 & op2531=0x30 & rd & rs1 & rs2 unimpl + +#TODO fix op2024 +:sbclriw rd, rs1, op2024 is op0006=0x1b & op1214=0x1 & op2531=0x24 & op2024 & rd & rs1 unimpl + +:sbclrw rd, rs1, rs2 is op0006=0x3b & op1214=0x1 & op2531=0x24 & rd & rs1 & rs2 unimpl + +:sbextw rd, rs1, rs2 is op0006=0x3b & op1214=0x5 & op2531=0x24 & rd & rs1 & rs2 unimpl + +#TODO fix op2024 +:sbinviw rd, rs1, op2024 is op0006=0x1b & op1214=0x1 & op2531=0x34 & op2024 & rd & rs1 unimpl + +:sbinvw rd, rs1, rs2 is op0006=0x3b & op1214=0x1 & op2531=0x34 & rd & rs1 & rs2 unimpl + +#TODO fix op2024 +:sbsetiw rd, rs1, op2024 is op0006=0x1b & op1214=0x1 & op2531=0x14 & op2024 & rd & rs1 unimpl + +:sbsetw rd, rs1, rs2 is op0006=0x3b & op1214=0x1 & op2531=0x14 & rd & rs1 & rs2 unimpl + +:sh1addu.w rd, rs1, rs2 is op0006=0x3b & op1214=0x2 & op2531=0x10 & rd & rs1 & rs2 unimpl + +:sh2addu.w rd, rs1, rs2 is op0006=0x3b & op1214=0x4 & op2531=0x10 & rd & rs1 & rs2 unimpl + +:sh3addu.w rd, rs1, rs2 is op0006=0x3b & op1214=0x6 & op2531=0x10 & rd & rs1 & rs2 unimpl + +:shflw rd, rs1, rs2 is op0006=0x3b & op1214=0x1 & op2531=0x4 & rd & rs1 & rs2 unimpl + +#TODO fix op2026 +:slliu.w rd, rs1, op2026 is op0006=0x1b & op1214=0x1 & op2731=0x1 & op2026 & rd & rs1 unimpl + +#TODO fix op2024 +:sloiw rd, rs1, op2024 is op0006=0x1b & op1214=0x1 & op2531=0x10 & op2024 & rd & rs1 unimpl + +:slow rd, rs1, rs2 is op0006=0x3b & op1214=0x1 & op2531=0x10 & rd & rs1 & rs2 unimpl + +#TODO fix op2024 +:sroiw rd, rs1, op2024 is op0006=0x1b & op1214=0x5 & op2531=0x10 & op2024 & rd & rs1 unimpl + +:srow rd, rs1, rs2 is op0006=0x3b & op1214=0x5 & op2531=0x10 & rd & rs1 & rs2 unimpl + +:subu.w rd, rs1, rs2 is op0006=0x3b & op1214=0x0 & op2531=0x24 & rd & rs1 & rs2 unimpl + +:subwu rd, rs1, rs2 is op0006=0x3b & op1214=0x0 & op2531=0x25 & rd & rs1 & rs2 unimpl + +:unshflw rd, rs1, rs2 is op0006=0x3b & op1214=0x5 & op2531=0x4 & rd & rs1 & rs2 unimpl + diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64d.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64d.sinc new file mode 100644 index 0000000..0436594 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64d.sinc @@ -0,0 +1,47 @@ +# RV64D Standard Extension (in addition to RV32D) + +# fcvt.d.l D,s,m d2200053 fff0007f SIMPLE (64, 0) +:fcvt.d.l frd,rs1L,FRM is frd & FRM & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x69 & op2024=0x2 +{ + local tmp:8 = int2float(rs1L); + frd = tmp; +} + + +# fcvt.d.lu D,s,m d2300053 fff0007f SIMPLE (64, 0) +:fcvt.d.lu frd,rs1L,FRM is frd & FRM & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x69 & op2024=0x3 +{ + #ATTN unsigned can be an issue here + local u64:$(XLEN2) = zext(rs1L); + local tmp:8 = int2float(u64); + frd = tmp; +} + + +# fcvt.l.d d,S,m c2200053 fff0007f SIMPLE (64, 0) +:fcvt.l.d rdL,frs1D,FRM is frs1D & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x2 +{ + rdL = trunc(frs1D); +} + + +# fcvt.lu.d d,S,m c2300053 fff0007f SIMPLE (64, 0) +:fcvt.lu.d rdL,frs1D,FRM is frs1D & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x3 +{ + #TODO unsigned + rdL = trunc(frs1D); +} + + +# fmv.d.x D,s f2000053 fff0707f SIMPLE (64, 0) +:fmv.d.x frd,rs1L is frd & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x79 & op2024=0x0 +{ + frd = rs1L; +} + +:fmv.x.d rdL,frs1D is frs1D & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x71 & op2024=0x0 +{ + local tmpreg:4 = &frs1D; + local tmp:8 = *[register]:8 tmpreg; + rdL = tmp; +} diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64f.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64f.sinc new file mode 100644 index 0000000..9a88490 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64f.sinc @@ -0,0 +1,33 @@ +# RV64F Standard Extension (in addition to RV32F) + +# fcvt.l.s d,S,m c0200053 fff0007f SIMPLE (64, 0) +:fcvt.l.s rdL,frs1S,FRM is frs1S & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x2 +{ + rdL = trunc(frs1S); +} + + +# fcvt.lu.s d,S,m c0300053 fff0007f SIMPLE (64, 0) +:fcvt.lu.s rdL,frs1S,FRM is frs1S & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x3 +{ + #TODO unsigned + rdL = trunc(frs1S); +} + + +# fcvt.s.l D,s,m d0200053 fff0007f SIMPLE (64, 0) +:fcvt.s.l frd,rs1L,FRM is frd & FRM & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x2 +{ + local tmp:4 = int2float(rs1L); + fassignS(frd, tmp); +} + + +# fcvt.s.lu D,s,m d0300053 fff0007f SIMPLE (64, 0) +:fcvt.s.lu frd,rs1L,FRM is frd & FRM & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x3 +{ + #ATTN unsigned can be an issue here + local u64:$(XLEN2) = zext(rs1L); + local tmp:4 = int2float(u64); + fassignS(frd, tmp); +} diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64i.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64i.sinc new file mode 100644 index 0000000..c0ad6f0 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64i.sinc @@ -0,0 +1,121 @@ +# RV64I Base Instruction Set (in addition to RV32I) + +# addiw d,s,j 0000001b 0000707f SIMPLE (64, 0) +:addiw rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x0 +{ + local result = rs1 + immI; + rd = sext(result:4); +} + +:sext.w rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x0 & op2031=0 +{ + local result = rs1; + rd = sext(result:4); +} + + + +# addw d,s,t 0000003b fe00707f SIMPLE (64, 0) +:addw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x0 +{ + local tmpr1:4 = rs1:4; + local tmpr2:4 = rs2:4; + local result:4 = tmpr1 + tmpr2; + rd = sext(result); +} + + +# ld d,o(s) 00003003 0000707f QWORD|DREF (64, 8) +:ld rd,immI(rs1) is immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x3 +{ + local ea:$(XLEN) = rs1 + immI; + rd = *[ram]:8 ea; +} + + +# lwu d,o(s) 00006003 0000707f DWORD|DREF (64, 4) +:lwu rd,immI(rs1) is immI & rs1 & rd & op0001=0x3 & op0204=0x0 & op0506=0x0 & funct3=0x6 +{ + local ea:$(XLEN) = rs1 + immI; + rd = zext(*[ram]:4 ea); +} + + +# sd t,q(s) 00003023 0000707f QWORD|DREF (64, 8) +:sd rs2,immS(rs1) is immS & rs2 & rs1 & op0001=0x3 & op0204=0x0 & op0506=0x1 & funct3=0x3 +{ + local ea:$(XLEN) = rs1 + immS; + *[ram]:8 ea = rs2; +} + + +# slliw d,s,< 0000101b fe00707f SIMPLE (64, 0) +:slliw rd,rs1,shamt5 is rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x1 & op2531=0x0 +{ + local tmp:4 = rs1:4; + tmp = tmp << shamt5; + rd = sext(tmp); +} + + +# sllw d,s,t 0000103b fe00707f SIMPLE (64, 0) +:sllw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x1 & funct7=0x0 +{ + local shift:$(XLEN) = rs2 & 0x1f; + local tmp:4 = rs1:4; + tmp = tmp << shift; + rd = sext(tmp); +} + + +# sraiw d,s,< 4000501b fe00707f SIMPLE (64, 0) +:sraiw rd,rs1,shamt5 is rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x5 & op2531=0x20 +{ + local tmp:4 = rs1:4; + tmp = tmp s>> shamt5; + rd = sext(tmp); +} + + +# sraw d,s,t 4000503b fe00707f SIMPLE (64, 0) +:sraw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x5 & funct7=0x20 +{ + local shift:$(XLEN) = rs2 & 0x1f; + local tmp:4 = rs1:4; + tmp = tmp s>> shift; + rd = sext(tmp); +} + + +# srliw d,s,< 0000501b fe00707f SIMPLE (64, 0) +:srliw rd,rs1,shamt5 is rs1 & shamt5 & rd & op0001=0x3 & op0204=0x6 & op0506=0x0 & funct3=0x5 & op2531=0x0 +{ + local tmp:4 = rs1:4; + tmp = tmp >> shamt5; + rd = sext(tmp); +} + + +# srlw d,s,t 0000503b fe00707f SIMPLE (64, 0) +:srlw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x5 & funct7=0x0 +{ + local shift:$(XLEN) = rs2 & 0x1f; + local tmp:4 = rs1:4; + tmp = tmp >> shift; + rd = sext(tmp); +} + + +# subw d,s,t 4000003b fe00707f SIMPLE (64, 0) +:subw rd,rs1W,rs2W is rs1W & rs2W & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x20 +{ + local result = rs1W - rs2W; + rd = sext(result); +} + +# negw d,t 4000003b fe0ff07f ALIAS (64, 0) +:negw rd,rs2W is rs2W & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x20 & op1519=0x0 +{ + local tmp = -rs2W; + rd = sext(tmp); +} diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64k.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64k.sinc new file mode 100644 index 0000000..fc79f40 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64k.sinc @@ -0,0 +1,35 @@ +# RV64 Crypto Extension +# NOTE 0.6.2 + +# 0001010 rs2 rs1 010 rd 0101011 saes64.decs +:saes64.decs rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x5b & op1214=0x2 & op2531=0x0a unimpl + +# 0001001 rs2 rs1 010 rd 0101011 saes64.decsm +:saes64.decsm rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x5b & op1214=0x2 & op2531=0x09 unimpl + +# 0001000 rs2 rs1 010 rd 0101011 saes64.encs +:saes64.encs rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x5b & op1214=0x2 & op2531=0x08 unimpl + +# 0000111 rs2 rs1 010 rd 0101011 saes64.encsm +:saes64.encsm rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x5b & op1214=0x2 & op2531=0x07 unimpl + +# 0000110 00001 rs1 010 rd 0101011 saes64.imix +:saes64.imix rd, rs1 is rd & rs1 & op0006=0x5b & op1214=0x2 & op2024=0x01 & op2531=0x06 unimpl + +# 0000100 0 rcon rs1 010 rd 0101011 saes64.ks1 +:saes64.ks1 rd, rs1, rcon is rd & rs1 & rcon & op0006=0x5b & op1214=0x2 & op2424=0x0 & op2531=0x04 unimpl + +# 0000101 rs2 rs1 010 rd 0101011 saes64.ks2 +:saes64.ks2 rd, rs1, rs2 is rd & rs1 & rs2 & op0006=0x5b & op1214=0x2 & op2531=0x05 unimpl + +# 0000111 00100 rs1 111 rd 0101011 ssha512.sig0 +:ssha512.sig0 rd, rs1 is rd & rs1 & op0006=0x5b & op1214=0x7 & op2024=0x04 & op2531=0x07 unimpl + +# 0000111 00101 rs1 111 rd 0101011 ssha512.sig1 +:ssha512.sig1 rd, rs1 is rd & rs1 & op0006=0x5b & op1214=0x7 & op2024=0x05 & op2531=0x07 unimpl + +# 0000111 00110 rs1 111 rd 0101011 ssha512.sum0 +:ssha512.sum0 rd, rs1 is rd & rs1 & op0006=0x5b & op1214=0x7 & op2024=0x06 & op2531=0x07 unimpl + +# 0000111 00111 rs1 111 rd 0101011 ssha512.sum1 +:ssha512.sum1 rd, rs1 is rd & rs1 & op0006=0x5b & op1214=0x7 & op2024=0x07 & op2531=0x07 unimpl diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64m.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64m.sinc new file mode 100644 index 0000000..8da116d --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64m.sinc @@ -0,0 +1,44 @@ +# RV64M Standard Exention (in addition to RV32M) + +# divuw d,s,t 0200503b fe00707f SIMPLE (64, 0) +:divuw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x5 & funct7=0x1 +{ + local tmpr1:4 = rs1:4; + local tmpr2:4 = rs2:4; + rd = sext(tmpr1 / tmpr2); +} + + +# divw d,s,t 0200403b fe00707f SIMPLE (64, 0) +:divw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x4 & funct7=0x1 +{ + local tmpr1:4 = rs1:4; + local tmpr2:4 = rs2:4; + rd = sext(tmpr1 s/ tmpr2); +} + + +# mulw d,s,t 0200003b fe00707f SIMPLE (64, 0) +:mulw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x1 +{ + local tmp:4 = rs1:4 * rs2:4; + rd = sext(tmp); +} + + +# remuw d,s,t 0200703b fe00707f SIMPLE (64, 0) +:remuw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x7 & funct7=0x1 +{ + local tmpr1:4 = rs1:4; + local tmpr2:4 = rs2:4; + rd = sext(tmpr1 % tmpr2); +} + + +# remw d,s,t 0200603b fe00707f SIMPLE (64, 0) +:remw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x6 & funct7=0x1 +{ + local tmpr1:4 = rs1:4; + local tmpr2:4 = rs2:4; + rd = sext(tmpr1 s% tmpr2); +} diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64p.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64p.sinc new file mode 100644 index 0000000..33bc383 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64p.sinc @@ -0,0 +1,294 @@ +# RV64 P Extension + + +# add32 rt, ra, rb ; rt.W[_x_] = ra.W[_x_] + rb.W[_x_]; ; (RV64: __x__=1..0) +:add32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x20 unimpl + + +# cras32 rt, ra, rb ; rt.W[_x_] = ra.W[_x_] + rb.W[_x-1_]; + ; rt.W[_x-1_] = ra.W[_x-1_] – rb.W[_x_]; ; (RV64: __x__=1) +:cras32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x22 unimpl + + +# crsa32 rt, ra, rb ; rt.W[_x_] = ra.W[_x_] - rb.W[_x-1_]; + ; rt.W[_x-1_] = ra.W[_x-1_] + rb.W[_x_]; ; (RV64: __x__=1) +:crsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x23 unimpl + + +# kadd32 rt, ra, rb ; rt.W[_x_] = SAT.Q31(ra.W[_x_] + rb.W[_x_]); ; (RV64: __x__=1..0) +:kadd32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x08 unimpl + + +# kcras32 rt, ra, rb ; rt.W[_x_] = SAT.Q31(ra.W[_x_] + rb.W[_x-1_]); + ; rt.W[_x-1_] = SAT.Q31(ra.W[_x-1_] – rb.W[_x_]); ; (RV64: __x__=1) +:kcras32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x0a unimpl + + +# kcrsa32 rt, ra, rb ; rt.W[_x_] = SAT.Q31(ra.W[_x_] - rb.W[_x-1_]); + ; rt.W[_x-1_] = SAT.Q31(ra.W[_x-1_] + rb.W[_x_]); ; (RV64: __x__=1) +:kcrsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x0b unimpl + + +:kmabb32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x2d unimpl + + +:kmabt32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x35 unimpl + + +:kmadrs32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x36 unimpl + + +:kmads32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x2e unimpl + + +:kmatt32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x3d unimpl + + +:kmaxda32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x25 unimpl + + +:kmaxds32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x3e unimpl + + +:kmda32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x1c unimpl + + +:kmsda32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x26 unimpl + + +:kmsxda32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x27 unimpl + + +:kmxda32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x1d unimpl + + +# ksll32 rt, ra, rb ; rt.W[_x_] = SAT.Q31(ra.W[_x_] << rb[4:0]); ; (RV64: __x__=1..0) +:ksll32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x32 unimpl + + +# kslli32 rt, ra, im5u ; rt.W[_x_] = SAT.Q31(ra.W[_x_] << im5u); ; (RV64: __x__=1..0) +:kslli32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x42 unimpl + + +# kslra32 rt, ra, rb ; if (rb[5:0] < 0) + ; rt.W[_x_] = ra.W[_x_] s>> -rb[5:0]; ; if (rb[5:0] > 0) + ; rt.W[_x_] = SAT.Q31(ra.W[_x_] << rb[5:0]); ; (RV64: __x__=1..0) +:kslra32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x2b unimpl + + +:kslra32.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x33 unimpl + + +# kstas16 rt, ra, rb ; rt.H[_x_] = SAT.Q15(ra.H[_x_] + rb.H[_x_]); + ; rt.H[_x-1_] = SAT.Q15(ra.H[_x-1_] – rb.H[_x-1_]); ; (RV32: __x__=1, RV64: __x__=1,3) +:kstas16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x62 unimpl + + +# kstas32 rt, ra, rb ; rt.W[_x_] = SAT.Q31(ra.W[_x_] + rb.W[_x_]); + ; rt.W[_x-1_] = SAT.Q31(ra.W[_x-1_] – rb.W[_x-1_]); ; (RV64: __x__=1) +:kstas32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x60 unimpl + + +# kstsa16 rt, ra, rb ; rt.H[_x_] = SAT.Q15(ra.H[_x_] - rb.H[_x_]); + ; rt.H[_x-1_] = SAT.Q15(ra.H[_x-1_] + rb.H[_x-1_]); ; (RV32: __x__=1, RV64: __x__=1,3) +:kstsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x63 unimpl + + +# kstsa32 rt, ra, rb ; rt.W[_x_] = SAT.Q31(ra.W[_x_] - rb.W[_x_]); + ; rt.W[_x-1_] = SAT.Q31(ra.W[_x-1_] + rb.W[_x-1_]); ; (RV64: __x__=1) +:kstsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x61 unimpl + + +# ksub32 rt, ra, rb ; rt.W[_x_] = SAT.Q31(ra.W[_x_] - rb.W[_x_]); ; (RV64: __x__=1..0) +:ksub32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x09 unimpl + + +# pkbb32 rt, ra, rb ; rt = CONCAT(ra.W[_0_], rb.W[_0_]); +:pkbb32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x07 unimpl + + +# pkbt32 rt, ra, rb ; rt = CONCAT(ra.W[_0_], rb.W[_1_]); +:pkbt32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x0f unimpl + + +# pktb32 rt, ra, rb ; rt = CONCAT(ra.W[_1_], rb.W[_0_]); +:pktb32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x1f unimpl + + +# pktt32 rt, ra, rb ; rt = CONCAT(ra.W[_1_], rb.W[_1_]); +:pktt32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x17 unimpl + + +# radd32 rt, ra, rb ; rt.W[_x_] = (ra.W[_x_] + rb.W[_x_]) s>> 1; ; (RV64: __x__=1..0) +:radd32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x00 unimpl + + +# rcras32 rt, ra, rb ; rt.W[_x_] = (ra.W[_x_] + rb.W[_x-1_]) s>> 1; + ; rt.W[_x-1_] = (ra.W[_x-1_] – rb.W[_x_]) s>> 1; ; (RV64: __x__=1) +:rcras32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x02 unimpl + + +# rcrsa32 rt, ra, rb ; rt.W[_x_] = (ra.W[_x_] - rb.W[_x-1_]) s>> 1; + ; rt.W[_x-1_] = (ra.W[_x-1_] + rb.W[_x_]) s>> 1; ; (RV64: __x__=1) +:rcrsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x03 unimpl + + +# rstas16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] + rb.H[_x_]) s>> 1; + ; rt.H[_x-1_] = (ra.H[_x-1_] – rb.H[_x-1_]) s>> 1; ; (RV32: __x__=1, RV64: __x__=1,3) +:rstas16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x5a unimpl + + +# rstas32 rt, ra, rb ; rt.W[_x_] = (ra.W[_x_] + rb.W[_x_]) s>> 1; + ; rt.W[_x-1_] = (ra.W[_x-1_] – rb.W[_x-1_]) s>> 1; ; (RV64: __x__=1) +:rstas32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x58 unimpl + + +# rstsa16 rt, ra, rb ; rt.H[_x_] = (ra.H[_x_] - rb.H[_x_]) s>> 1; + ; rt.H[_x-1_] = (ra.H[_x-1_] + rb.H[_x-1_]) s>> 1; ; (RV32: __x__=1, RV64: __x__=1,3) +:rstsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x5b unimpl + + +# rstsa32 rt, ra, rb ; rt.W[_x_] = (ra.W[_x_] - rb.W[_x_]) s>> 1; + ; rt.W[_x-1_] = (ra.W[_x-1_] + rb.W[_x-1_]) s>> 1; ; (RV64: __x__=1) +:rstsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x59 unimpl + + +# rsub32 rt, ra, rb ; rt.W[_x_] = (ra.W[_x_] - rb.W[_x_]) s>> 1; ; (RV64: __x__=1..0) +:rsub32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x01 unimpl + + +# sll32 rt, ra, rb ; rt.W[_x_] = ra.W[_x_] << rb[4:0]; ; (RV64: __x__=1..0) +:sll32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x2a unimpl + + +# slli32 rt, ra, im5u ; rt.W[_x_] = ra.W[_x_] << im5u; ; (RV64: __x__=1..0) +:slli32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x3a unimpl + + +# smax32 rt, ra, rb ; rt.W[_x_] = (ra.W[_x_] > rb.W[_x_])? ra.W[_x_] : rb.W[_x_]; ; (RV64: __x__=1..0) +:smax32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x49 unimpl + + +:smbt32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x0c unimpl + + +:smdrs32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x34 unimpl + + +:smds32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x2c unimpl + + +# smin32 rt, ra, rb ; rt.W[_x_] = (ra.W[_x_] < rb.W[_x_])? ra.W[_x_] : rb.W[_x_]; ; (RV64: __x__=1..0) +:smin32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x48 unimpl + + +:smtt32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x14 unimpl + + +:smxds32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x3c unimpl + + +# sra32 rt, ra, rb ; rt.W[_x_] = ra.W[_x_] s>> rb[4:0]; ; (RV64: __x__=1..0) +:sra32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x28 unimpl + + +:sra32.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x30 unimpl + + +# srai32 rt, ra, im5u ; rt.W[_x_] = ra.W[_x_] s>> im5u; ; (RV64: __x__=1..0) +:srai32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x38 unimpl + + +:srai32.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x40 unimpl + + +# srl32 rt, ra, rb ; rt.W[_x_] = ra.W[_x_] u>> rb[4:0]; ; (RV64: __x__=1..0) +:srl32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x29 unimpl + + +:srl32.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x31 unimpl + + +# srli32 rt, ra, im5u ; rt.W[_x_] = ra.W[_x_] u>> im5u; ; (RV64: __x__=1..0) +:srli32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x39 unimpl + + +:srli32.u rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x41 unimpl + + +# stas16 rt, ra, rb ; rt.H[_x_] = ra.H[_x_] + rb.H[_x_]; + ; rt.H[_x-1_] = ra.H[_x-1_] – rb.H[_x-1_]; ; (RV32: __x__=1, RV64: __x__=1,3) +:stas16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x7a unimpl + + +# stas32 rt, ra, rb ; rt.W[_x_] = ra.W[_x_] + rb.W[_x_]; + ; rt.W[_x-1_] = ra.W[_x-1_] – rb.W[_x-1_]; ; (RV64: __x__=1) +:stas32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x78 unimpl + + +# stsa16 rt, ra, rb ; rt.H[_x_] = ra.H[_x_] - rb.H[_x_]; + ; rt.H[_x-1_] = ra.H[_x-1_] + rb.H[_x-1_]; ; (RV32: __x__=1, RV64: __x__=1,3) +:stsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x7b unimpl + + +# stsa32 rt, ra, rb ; rt.W[_x_] = ra.W[_x_] - rb.W[_x_]; + ; rt.W[_x-1_] = ra.W[_x-1_] + rb.W[_x-1_]; ; (RV64: __x__=1) +:stsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x79 unimpl + + +# sub32 rt, ra, rb ; rt.W[_x_] = ra.W[_x_] - rb.W[_x_]; ; (RV64: __x__=1..0) +:sub32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x21 unimpl + + +# ukadd32 rt, ra, rb ; rt.W[_x_] = SAT.U32(ra.W[_x_] + rb.W[_x_]; ; (RV64: __x__=1..0) +:ukadd32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x18 unimpl + + +# ukcras32 rt, ra, rb ; rt.W[_x_] = SAT.U32(ra.W[_x_] + rb.W[_x-1_]); + ; rt.W[_x-1_] = SAT.U32(ra.W[_x-1_] – rb.W[_x_]); ; (RV64: __x__=1) +:ukcras32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x1a unimpl + + +# ukcrsa32 rt, ra, rb ; rt.W[_x_] = SAT.U32(ra.W[_x_] - rb.W[_x-1_]); + ; rt.W[_x-1_] = SAT.U32(ra.W[_x-1_] + rb.W[_x_]); ; (RV64: __x__=1) +:ukcrsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x1b unimpl + + +# ukstas16 rt, ra, rb ; rt.H[_x_] = SAT.U16(ra.H[_x_] + rb.H[_x_]); + ; rt.H[_x-1_] = SAT.U16(ra.H[_x-1_] – rb.H[_x-1_]); ; (RV32: __x__=1, RV64: __x__=1,3) +:ukstas16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x72 unimpl + + +# ukstas32 rt, ra, rb ; rt.W[_x_] = SAT.U32(ra.W[_x_] + rb.W[_x_]); + ; rt.W[_x-1_] = SAT.U32(ra.W[_x-1_] – rb.W[_x-1_]); ; (RV64: __x__=1) +:ukstas32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x70 unimpl + + +# ukstsa16 rt, ra, rb ; rt.H[_x_] = SAT.U16(ra.H[_x_] - rb.H[_x_]); + ; rt.H[_x-1_] = SAT.U16(ra.H[_x-1_] + rb.H[_x-1_]); ; (RV32: __x__=1, RV64: __x__=1,3) +:ukstsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x73 unimpl + + +# ukstsa32 rt, ra, rb ; rt.W[_x_] = SAT.U32(ra.W[_x_] - rb.W[_x_]); + ; rt.W[_x-1_] = SAT.U32(ra.W[_x-1_] + rb.W[_x-1_]); ; (RV64: __x__=1) +:ukstsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x71 unimpl + + +# uksub32 rt, ra, rb ; rt.W[_x_] = SAT.U32(ra.W[_x_] - rb.W[_x_]); ; (RV64: __x__=1..0) +:uksub32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x19 unimpl + + +# umax32 rt, ra, rb ; rt.W[_x_] = (ra.W[_x_] u> rb.W[_x_])? ra.W[_x_] : rb.W[_x_]; ; (RV64: __x__=1..0) +:umax32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x51 unimpl + + +# umin32 rt, ra, rb ; rt.W[_x_] = (ra.W[_x_] u< rb.W[_x_])? ra.W[_x_] : rb.W[_x_]; ; (RV64: __x__=1..0) +:umin32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x50 unimpl + + +# uradd32 rt, ra, rb ; rt.W[_x_] = (CONCAT(1'b0,ra.W[_x_]) + CONCAT(1'b0,rb.W[_x_])) >> 1; ; (RV64: __x__=1..0) +:uradd32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x10 unimpl + + +# urcras32 rt, ra, rb ; rt.W[_x_] = (CONCAT(1'b0,ra.W[_x_]) + CONCAT(1'b0,rb.W[_x-1_])) >> 1; + ; rt.W[_x-1_] = (CONCAT(1'b0,ra.W[_x-1_]) – CONCAT(1'b0,rb.W[_x_])) >> 1; ; (RV64: __x__=1) +:urcras32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x12 unimpl + + +# urcrsa32 rt, ra, rb ; rt.W[_x_] = (CONCAT(1'b0,ra.W[_x_]) - CONCAT(1'b0,rb.W[_x-1_])) >> 1; + ; rt.W[_x-1_] = (CONCAT(1'b0,ra.W[_x-1_]) + CONCAT(1'b0,rb.W[_x_])) >> 1; ; (RV64: __x__=1) +:urcrsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x13 unimpl + + +# urstas16 rt, ra, rb ; rt.H[_x_] = (CONCAT(1'b0,ra.H[_x_]) + CONCAT(1'b0,rb.H[_x_])) >> 1; + ; rt.H[_x-1_] = (CONCAT(1'b0,ra.H[_x-1_]) – CONCAT(1'b0,rb.H[_x-1_])) >> 1; ; (RV32: __x__=1, RV64: __x__=1,3) +:urstas16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x6a unimpl + + +# urstas32 rt, ra, rb ; rt.W[_x_] = (CONCAT(1'b0,ra.W[_x_]) + CONCAT(1'b0,rb.W[_x_])) >> 1; + ; rt.W[_x-1_] = (CONCAT(1'b0,ra.W[_x-1_]) – CONCAT(1'b0,rb.W[_x-1_])) >> 1; ; (RV64: __x__=1) +:urstas32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x68 unimpl + + +# urstsa16 rt, ra, rb ; rt.H[_x_] = (CONCAT(1'b0,ra.H[_x_]) - CONCAT(1'b0,rb.H[_x_])) >> 1; + ; rt.H[_x-1_] = (CONCAT(1'b0,ra.H[_x-1_]) + CONCAT(1'b0,rb.H[_x-1_])) >> 1; ; (RV32: __x__=1, RV64: __x__=1,3) +:urstsa16 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x6b unimpl + + +# urstsa32 rt, ra, rb ; rt.W[_x_] = (CONCAT(1'b0,ra.W[_x_]) - CONCAT(1'b0,rb.W[_x_])) >> 1; + ; rt.W[_x-1_] = (CONCAT(1'b0,ra.W[_x-1_]) + CONCAT(1'b0,rb.W[_x-1_])) >> 1; ; (RV64: __x__=1) +:urstsa32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x69 unimpl + + +# ursub32 rt, ra, rb ; rt.W[_x_] = (CONCAT(1'b0,ra.W[_x_]) - CONCAT(1'b0,rb.W[_x_])) >> 1; ; (RV64: __x__=1..0) +:ursub32 rd,rs1,rs2 is op0006=0x3f & rd & rs1 & rs2 & funct3=0x2 & funct7=0x11 unimpl + + diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64q.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64q.sinc new file mode 100644 index 0000000..51849d3 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rv64q.sinc @@ -0,0 +1,28 @@ +# RV64Q Standard Extension (in addition to RV32Q) + +# fcvt.l.q d,S,m c6200053 fff0007f SIMPLE (64, 0) +:fcvt.l.q rd,frs1,FRM is frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x2 +{ + rd = trunc(frs1); +} + + +# fcvt.lu.q d,S,m c6300053 fff0007f SIMPLE (64, 0) +:fcvt.lu.q rd,frs1,FRM is frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x3 +{ + rd = trunc(frs1); +} + + +# fcvt.q.l D,s,m d6200053 fff0007f SIMPLE (64, 0) +:fcvt.q.l frd,rs1,FRM is frd & FRM & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x6b & op2024=0x2 +{ + frd = int2float(rs1); +} + + +# fcvt.q.lu D,s,m d6300053 fff0007f SIMPLE (64, 0) +:fcvt.q.lu frd,rs1,FRM is frd & FRM & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x6b & op2024=0x3 +{ + frd = int2float(rs1); +} diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rvc.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rvc.sinc new file mode 100644 index 0000000..480f1b6 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rvc.sinc @@ -0,0 +1,370 @@ +# RVC Standard Extension for Compressed Instructions + +# c.add d,CV 00009002 0000f003 SIMPLE (0, 0) +:c.add crd,crs2 is crd & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x1 +{ + crd = crd + crs2; +} + +# c.addi d,Co 00000001 0000e003 SIMPLE (0, 0) +# There may be other nop forms here if (cop0711=0) or (cop1212=0 & cop0206=0) +:c.addi crd,cimmI is crd & cimmI & cop0001=0x1 & cop1315=0x0 +{ + crd = crd + cimmI; +} + +:c.nop is cop0001=0x1 & cop1315=0x0 & cop0711=0 & cop1212=0 & cop0206=0 +{ + local NOP:1 = 0; + NOP = NOP; +} + +# c.addi16sp Cc,CL 00006101 0000ef83 SIMPLE (0, 0) +:c.addi16sp sp,caddi16spimm is cop0711=0x2 & caddi16spimm & sp & cop0001=0x1 & cop1315=0x3 +{ + sp = sp + caddi16spimm; +} + +# c.addi4spn Ct,Cc,CK 00000000 0000e003 SIMPLE (0, 0) +:c.addi4spn cr0204s,sp,caddi4spnimm is caddi4spnimm & cr0204s & sp & cop0001=0x0 & cop1315=0x0 +{ + cr0204s = sp + caddi4spnimm; +} + +@if (ADDRSIZE == "64") || (ADDRSIZE == "128") +# c.addiw d,Co 00002001 0000e003 SIMPLE (64, 0) +:c.addiw crd,cimmI is crd & cimmI & cop0001=0x1 & cop1315=0x1 +{ + local tmp:$(XLEN) = crd + cimmI; + crd = sext(tmp:$(WXLEN)); +} +@endif + +@if (ADDRSIZE == "64") || (ADDRSIZE == "128") +# c.addw Cs,Ct 00009c21 0000fc63 SIMPLE (64, 0) +:c.addw cr0709s,cr0204s is cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x1 & cop1012=0x7 +{ + local tmp:4 = cr0709s:4 + cr0204s:4; + cr0709s = sext(tmp); +} +@endif + +# c.and Cs,Ct 00008c61 0000fc63 SIMPLE (0, 0) +:c.and cr0709s,cr0204s is cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x3 & cop1012=0x3 +{ + cr0709s = cr0709s & cr0204s; +} + +# c.andi Cs,Co 00008801 0000ec03 SIMPLE (0, 0) +:c.andi cr0709s,cimmI is cimmI & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x2 +{ + cr0709s = cr0709s & cimmI; +} + +# c.beqz Cs,Cp 0000c001 0000e003 CONDBRANCH (0, 0) +:c.beqz cr0709s,cbimm is cbimm & cr0709s & cop0001=0x1 & cop1315=0x6 +{ + if (cr0709s == 0) goto cbimm; +} + +# c.bnez Cs,Cp 0000e001 0000e003 CONDBRANCH (0, 0) +:c.bnez cr0709s,cbimm is cbimm & cr0709s & cop0001=0x1 & cop1315=0x7 +{ + if (cr0709s != 0) goto cbimm; +} + +# c.ebreak 00009002 0000ffff SIMPLE (0, 0) +:c.ebreak is cop0001=0x2 & cop1315=0x4 & cop0212=0x400 +{ + ebreak(); +} + +@if ADDRSIZE == "32" || ADDRSIZE == "64" +@if FPSIZE == "64" +# c.fld CD,Cl(Cs) 00002000 0000e003 QWORD|DREF (0, 8) +:c.fld cfr0204s,cldimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x1 & cldimm +{ + local ea:$(XLEN) = cldimm:$(XLEN) + cr0709s; + cfr0204s = *[ram]:$(DFLEN) ea; +} + + +# c.fldsp D,Cn(Cc) 00002002 0000e003 QWORD|DREF (0, 8) +:c.fldsp cfrd,cldspimm(sp) is cfrd & sp & cop0001=0x2 & cop1315=0x1 & cldspimm +{ + local ea:$(XLEN) = cldspimm:$(XLEN) + sp; + cfrd = *[ram]:$(DFLEN) ea; +} +@endif +@endif + +@if ADDRSIZE == "32" +# c.flw CD,Ck(Cs) 00006000 0000e003 DWORD|DREF (32, 4) +:c.flw cfr0204s,clwimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x3 & clwimm +{ + local ea:$(XLEN) = clwimm:$(XLEN) + cr0709s; + cfr0204s = *[ram]:$(SFLEN) ea; +} + + +# c.flwsp D,Cm(Cc) 00006002 0000e003 DWORD|DREF (32, 4) +:c.flwsp cfrd,clwspimm(sp) is cfrd & sp & cop0001=0x2 & cop1315=0x3 & clwspimm +{ + local ea:$(XLEN) = clwspimm:$(XLEN) + sp; + cfrd = *[ram]:$(SFLEN) ea; +} +@endif + +@if ADDRSIZE == "32" || ADDRSIZE == "64" +@if FPSIZE == "64" +# c.fsd CD,Cl(Cs) 0000a000 0000e003 QWORD|DREF (0, 8) +:c.fsd cfr0204s,cldimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x5 & cldimm +{ + local ea:$(XLEN) = cldimm + cr0709s; + *[ram]:8 ea = cfr0204s; +} + +# c.fsdsp CT,CN(Cc) 0000a002 0000e003 QWORD|DREF (0, 8) +:c.fsdsp cfr0206,csdspimm(sp) is cfr0206 & sp & cop0001=0x2 & cop1315=0x5 & csdspimm +{ + local ea:$(XLEN) = csdspimm + sp; + *[ram]:8 ea = cfr0206; +} +@endif +@endif + +@if ADDRSIZE == "32" +@if FPSIZE == "32" || FPSIZE == "64" +# c.fsw CD,Ck(Cs) 0000e000 0000e003 DWORD|DREF (32, 4) +:c.fsw cfr0204s,clwimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x7 & clwimm +{ + local ea:$(XLEN) = clwimm + cr0709s; + *[ram]:4 ea = cfr0204s; +} + +# c.fswsp CT,CM(Cc) 0000e002 0000e003 DWORD|DREF (32, 4) +:c.fswsp cfr0206,cswspimm(sp) is cfr0206 & sp & cop0001=0x2 & cop1315=0x7 & cswspimm +{ + local ea:$(XLEN) = cswspimm + sp; + *[ram]:4 ea = cfr0206:4; +} +@endif +@endif + +# c.j Ca 0000a001 0000e003 BRANCH (0, 0) +:c.j cjimm is cjimm & cop0001=0x1 & cop1315=0x5 +{ + goto cjimm; +} + +@if ADDRSIZE == "32" +# c.jal Ca 00002001 0000e003 JSR (32, 0) +:c.jal cjimm is cjimm & cop0001=0x1 & cop1315=0x1 +{ + ra = inst_next; + call cjimm; +} +@endif + +# c.jalr d 00009002 0000f07f JSR (0, 0) +:c.jalr crd is crd & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x1 +{ + ra = inst_next; + call [crd]; +} + +# c.jr d 00008002 0000f07f BRANCH (0, 0) +:c.jr crd is crd & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x0 +{ + goto [crd]; +} + +# ret 00008082 0000ffff BRANCH|ALIAS (0, 0) +:ret is cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x0 & cop0711=1 +{ + return [ra]; +} + +@if (ADDRSIZE == "64") || (ADDRSIZE == "128") +# c.ld Ct,Cl(Cs) 00006000 0000e003 QWORD|DREF (64, 8) +:c.ld cr0204s,cldimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x3 & cldimm +{ + local ea:$(XLEN) = cldimm:$(XLEN) + cr0709s; + assignD(cr0204s, *[ram]:$(DXLEN) ea); +} +@endif + +@if ADDRSIZE == "128" +:c.lq cr0204s,clqimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x1 & clqimm +{ + local ea:$(XLEN) = clqimm:$(XLEN) + cr0709s; + cr0204s = *[ram]:$(QXLEN) ea; +} +@endif + +@if (ADDRSIZE == "64") || (ADDRSIZE == "128") +# c.ldsp d,Cn(Cc) 00006002 0000e003 QWORD|DREF (64, 8) +:c.ldsp crd,cldspimm(sp) is crd & sp & cop0001=0x2 & cop1315=0x3 & cldspimm +{ + local ea:$(XLEN) = cldspimm + sp; + assignD(crd, *[ram]:$(DXLEN) ea); +} +@endif + +@if ADDRSIZE == "128" +:c.lqsp crd,clqspimm(sp) is crd & sp & cop0001=0x2 & cop1315=0x1 & clqspimm +{ + local ea:$(XLEN) = clqspimm + sp; + crd = *[ram]:$(QXLEN) ea; +} +@endif + +# c.li d,Co 00004001 0000e003 SIMPLE (0, 0) +:c.li crd,cimmI is crd & cimmI & cop0001=0x1 & cop1315=0x2 +{ + crd = cimmI; +} + +# c.lui d,Cu 00006001 0000e003 SIMPLE (0, 0) +:c.lui crd,cbigimm is crd & cbigimm & cop0001=0x1 & cop1315=0x3 +{ + crd = cbigimm; +} + +# c.lw Ct,Ck(Cs) 00004000 0000e003 DWORD|DREF (0, 4) +:c.lw cr0204s,clwimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x2 & clwimm +{ + local ea:$(XLEN) = clwimm + cr0709s; + assignW(cr0204s, *[ram]:4 ea); +} + +# c.lwsp d,Cm(Cc) 00004002 0000e003 SIMPLE (0, 0) +:c.lwsp crd,clwspimm(sp) is crd & sp & cop0001=0x2 & cop1315=0x2 & clwspimm +{ + local ea:$(XLEN) = clwspimm + sp; + assignW(crd, *[ram]:4 ea); +} + +# c.mv d,CV 00008002 0000f003 SIMPLE (0, 0) +:c.mv crd,crs2 is crd & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x0 +{ + crd = crs2; +} + +# c.or Cs,Ct 00008c41 0000fc63 SIMPLE (0, 0) +:c.or cr0709s,cr0204s is cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x2 & cop1012=0x3 +{ + cr0709s = cr0709s | cr0204s; +} + +@if (ADDRSIZE == "64") || (ADDRSIZE == "128") +# c.sd Ct,Cl(Cs) 0000e000 0000e003 QWORD|DREF (64, 8) +:c.sd cr0204s,cldimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x7 & cldimm +{ + local ea:$(XLEN) = cldimm:$(XLEN) + cr0709s; + *[ram]:$(DXLEN) ea = cr0204s:$(DXLEN); +} + +# c.sdsp CV,CN(Cc) 0000e002 0000e003 QWORD|DREF (64, 8) +:c.sdsp crs2,csdspimm(sp) is crs2 & sp & cop0001=0x2 & cop1315=0x7 & csdspimm +{ + local ea:$(XLEN) = csdspimm:$(XLEN) + sp; + *[ram]:$(DXLEN) ea = crs2:$(DXLEN); +} +@endif + +# c.slli d,C> 00000002 0000e003 SIMPLE (0, 0) +:c.slli crd,c6imm is crd & c6imm & cop0001=0x2 & cop1315=0x0 +{ + crd = crd << c6imm; +} + +#TODO hint? +# c.slli64 d 00000002 0000f07f SIMPLE (0, 0) +:c.slli64 crd is crd & cop0001=0x2 & cop1315=0x0 & cop0206=0x0 & cop1212=0x0 +{ + crd = crd << 0; +} + +# c.srai Cs,C> 00008401 0000ec03 SIMPLE (0, 0) +:c.srai cr0709s,c6imm is c6imm & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x1 +{ + cr0709s = cr0709s s>> c6imm; +} + +#TODO hint? +# c.srai64 Cs 00008401 0000fc7f SIMPLE (0, 0) +:c.srai64 cr0709s is cr0709s & cop0001=0x1 & cop1315=0x4 & cop0206=0x0 & cop1012=0x1 +{ + cr0709s = cr0709s s>> 0; +} + +# c.srli Cs,C> 00008001 0000ec03 SIMPLE (0, 0) +:c.srli cr0709s,c6imm is c6imm & cr0709s & cop0001=0x1 & cop1315=0x4 & cop1011=0x0 +{ + cr0709s = cr0709s >> c6imm; +} + +#TODO hint? +# c.srli64 Cs 00008001 0000fc7f SIMPLE (0, 0) +:c.srli64 cr0709s is cr0709s & cop0001=0x1 & cop1315=0x4 & cop0206=0x0 & cop1012=0x0 +{ + cr0709s = cr0709s >> 0; +} + +# c.sub Cs,Ct 00008c01 0000fc63 SIMPLE (0, 0) +:c.sub cr0709s,cr0204s is cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x0 & cop1012=0x3 +{ + cr0709s = cr0709s - cr0204s; +} + +@if (ADDRSIZE == "64") || (ADDRSIZE == "128") +# c.subw Cs,Ct 00009c01 0000fc63 SIMPLE (64, 0) +:c.subw cr0709s,cr0204s is cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x0 & cop1012=0x7 +{ + local tmp:4 = cr0709s:4 - cr0204s:4; + cr0709s = sext(tmp); +} +@endif + +# c.sw Ct,Ck(Cs) 0000c000 0000e003 DWORD|DREF (0, 4) +:c.sw cr0204s,clwimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x6 & clwimm +{ + local ea:$(XLEN) = clwimm + cr0709s; + *[ram]:4 ea = cr0204s:4; +} + +@if ADDRSIZE == "128" +:c.sq cr0204s,clqimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x5 & clqimm +{ + local ea:$(XLEN) = clqimm + cr0709s; + *[ram]:16 ea = cr0204s; +} + +:c.sqsp crs2,csqspimm(sp) is crs2 & sp & cop0001=0x2 & cop1315=0x5 & csqspimm +{ + local ea:$(XLEN) = csqspimm + sp; + *[ram]:16 ea = crs2; +} +@endif + +# c.swsp CV,CM(Cc) 0000c002 0000e003 DWORD|DREF (0, 4) +:c.swsp crs2,cswspimm(sp) is crs2 & sp & cop0001=0x2 & cop1315=0x6 & cswspimm +{ + local ea:$(XLEN) = cswspimm + sp; + *[ram]:4 ea = crs2:4; +} + +# c.unimp 00000000 0000ffff SIMPLE (0, 0) +# would be better not to decode as it is used as padding +# +# :c.unimp is cop0001=0x0 & cop1315=0x0 & cop0212=0x0 +#{ +# trap(); +#} + +# c.xor Cs,Ct 00008c21 0000fc63 SIMPLE (0, 0) +:c.xor cr0709s,cr0204s is cr0204s & cr0709s & cop0001=0x1 & cop1315=0x4 & cop0506=0x1 & cop1012=0x3 +{ + cr0709s = cr0709s ^ cr0204s; +} diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rvv.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rvv.sinc new file mode 100644 index 0000000..f21ed22 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.rvv.sinc @@ -0,0 +1,1955 @@ +# Vector + +# sew: "e8" is vsew=0 {} +# sew: "e16" is vsew=1 {} +# sew: "e32" is vsew=2 {} +# sew: "e64" is vsew=3 {} +# sew: "e128" is vsew=4 {} +# sew: "e256" is vsew=5 {} +# sew: "e512" is vsew=6 {} +# sew: "e1024" is vsew=7 {} + +# vmul: "m1" is vlmul=0 {} +# vmul: "m2" is vlmul=1 {} +# vmul: "m4" is vlmul=2 {} +# vmul: "m8" is vlmul=3 {} +# vmul: "mf8" is vlmul=5 {} +# vmul: "mf4" is vlmul=6 {} +# vmul: "mf2" is vlmul=7 {} + +# vmask: "mu" is vma=0 {} +# vmask: "ma" is vma=1 {} +# vtail: "tu" is vta=0 {} +# vtail: "ta" is vta=1 {} + +#TODO possible tables +# mop=0 unit-stride VLE +# mop=2 strided VLSE +# mop=3 indexed VLXEI +# mop=0 unit-stride VSE +# mop=1 indexed-unordered VSUXEI +# mop=2 strided VSSE +# mop=3 indexed-ordered VSXEI +# lumop=0 unit-stride +# lumop=8 unit-stride,whole registers +# lumop=16 unit-stride fault-only-first +# sumop=0 unit-stride +# sumop=8 unit-stride,whole registers +# sumop=16 unit-stride fault-only-first +# nfields imm is nf [ imm = nf + 1; ] { export *[const]:1 imm; } + + +# vaadd.vv 31..26=0x09 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vaadd.vv vd, vs2, vs1, vm # roundoff_signed(vs2[i] + vs1[i], 1) +:vaadd.vv vd, vs2, vs1, vm is op2631=0x9 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vaadd.vx 31..26=0x09 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vaadd.vx vd, vs2, rs1, vm # roundoff_signed(vs2[i] + x[rs1], 1) +:vaadd.vx vd, vs2, rs1, vm is op2631=0x9 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vaaddu.vv 31..26=0x08 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vaaddu.vv vd, vs2, vs1, vm # roundoff_unsigned(vs2[i] + vs1[i], 1) +:vaaddu.vv vd, vs2, vs1, vm is op2631=0x8 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vaaddu.vx 31..26=0x08 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vaaddu.vx vd, vs2, rs1, vm # roundoff_unsigned(vs2[i] + x[rs1], 1) +:vaaddu.vx vd, vs2, rs1, vm is op2631=0x8 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vadc.vim 31..26=0x10 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vadc.vim vd, vs2, simm5, v0 # Vector-immediate +:vadc.vim vd, vs2, simm5, v0 is op2631=0x10 & op2525=0x0 & vs2 & simm5 & op1214=0x3 & v0 & vd & op0006=0x57 unimpl + +# vadc.vvm 31..26=0x10 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vadc.vvm vd, vs2, vs1, v0 # Vector-vector +:vadc.vvm vd, vs2, vs1, v0 is op2631=0x10 & op2525=0x0 & vs2 & vs1 & op1214=0x0 & v0 & vd & op0006=0x57 unimpl + +# vadc.vxm 31..26=0x10 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vadc.vxm vd, vs2, rs1, v0 # Vector-scalar +:vadc.vxm vd, vs2, rs1, v0 is op2631=0x10 & op2525=0x0 & vs2 & rs1 & op1214=0x4 & v0 & vd & op0006=0x57 unimpl + +# vadd.vi 31..26=0x00 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vadd.vi vd, vs2, simm5, vm # vector-immediate +:vadd.vi vd, vs2, simm5, vm is op2631=0x0 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vadd.vv 31..26=0x00 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vadd.vv vd, vs2, vs1, vm # Vector-vector +:vadd.vv vd, vs2, vs1, vm is op2631=0x0 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vadd.vx 31..26=0x00 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vadd.vx vd, vs2, rs1, vm # vector-scalar +:vadd.vx vd, vs2, rs1, vm is op2631=0x0 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vamoaddei16.v 31..27=0x00 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +# vamoaddei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamoaddei16.v vd, (rs1), vs2, vs3, vm is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl + +# vamoaddei16.v 31..27=0x00 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +# vamoaddei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamoaddei16.v zero, (rs1), vs2, vs3, vm is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & vd & op0006=0x2f unimpl + +# vamoaddei32.v 31..27=0x00 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +# vamoaddei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamoaddei32.v vd, (rs1), vs2, vs3, vm is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl + +# vamoaddei32.v 31..27=0x00 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +# vamoaddei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamoaddei32.v zero, (rs1), vs2, vs3, vm is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & vd & op0006=0x2f unimpl + +# vamoaddei64.v 31..27=0x00 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +# vamoaddei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamoaddei64.v vd, (rs1), vs2, vs3, vm is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl + +# vamoaddei64.v 31..27=0x00 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +# vamoaddei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamoaddei64.v zero, (rs1), vs2, vs3, vm is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & vd & op0006=0x2f unimpl + +# vamoaddei8.v 31..27=0x00 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +# vamoaddei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamoaddei8.v vd, (rs1), vs2, vs3, vm is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl + +# vamoaddei8.v 31..27=0x00 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +# vamoaddei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamoaddei8.v zero, (rs1), vs2, vs3, vm is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & vd & op0006=0x2f unimpl + +# vamoandei16.v 31..27=0x0c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +# vamoandei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamoandei16.v vd, (rs1), vs2, vs3, vm is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl + +# vamoandei16.v 31..27=0x0c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +# vamoandei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamoandei16.v zero, (rs1), vs2, vs3, vm is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & vd & op0006=0x2f unimpl + +# vamoandei32.v 31..27=0x0c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +# vamoandei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamoandei32.v vd, (rs1), vs2, vs3, vm is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl + +# vamoandei32.v 31..27=0x0c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +# vamoandei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamoandei32.v zero, (rs1), vs2, vs3, vm is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl + +# vamoandei64.v 31..27=0x0c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +# vamoandei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamoandei64.v vd, (rs1), vs2, vs3, vm is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl + +# vamoandei64.v 31..27=0x0c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +# vamoandei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamoandei64.v zero, (rs1), vs2, vs3, vm is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl + +# vamoandei8.v 31..27=0x0c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +# vamoandei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamoandei8.v vd, (rs1), vs2, vs3, vm is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl + +# vamoandei8.v 31..27=0x0c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +# vamoandei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamoandei8.v zero, (rs1), vs2, vs3, vm is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl + +# vamomaxei16.v 31..27=0x14 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +# vamomaxei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamomaxei16.v vd, (rs1), vs2, vs3, vm is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl + +# vamomaxei16.v 31..27=0x14 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +# vamomaxei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamomaxei16.v zero, (rs1), vs2, vs3, vm is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl + +# vamomaxei32.v 31..27=0x14 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +# vamomaxei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamomaxei32.v vd, (rs1), vs2, vs3, vm is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl + +# vamomaxei32.v 31..27=0x14 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +# vamomaxei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamomaxei32.v zero, (rs1), vs2, vs3, vm is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl + +# vamomaxei64.v 31..27=0x14 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +# vamomaxei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamomaxei64.v vd, (rs1), vs2, vs3, vm is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl + +# vamomaxei64.v 31..27=0x14 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +# vamomaxei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamomaxei64.v zero, (rs1), vs2, vs3, vm is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl + +# vamomaxei8.v 31..27=0x14 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +# vamomaxei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamomaxei8.v vd, (rs1), vs2, vs3, vm is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl + +# vamomaxei8.v 31..27=0x14 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +# vamomaxei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamomaxei8.v zero, (rs1), vs2, vs3, vm is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & vd & op0006=0x2f unimpl + +# vamomaxuei16.v 31..27=0x1c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +# vamomaxuei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamomaxuei16.v vd, (rs1), vs2, vs3, vm is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl + +# vamomaxuei16.v 31..27=0x1c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +# vamomaxuei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamomaxuei16.v zero, (rs1), vs2, vs3, vm is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl + +# vamomaxuei32.v 31..27=0x1c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +# vamomaxuei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamomaxuei32.v vd, (rs1), vs2, vs3, vm is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl + +# vamomaxuei32.v 31..27=0x1c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +# vamomaxuei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamomaxuei32.v zero, (rs1), vs2, vs3, vm is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl + +# vamomaxuei64.v 31..27=0x1c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +# vamomaxuei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamomaxuei64.v vd, (rs1), vs2, vs3, vm is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl + +# vamomaxuei64.v 31..27=0x1c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +# vamomaxuei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamomaxuei64.v zero, (rs1), vs2, vs3, vm is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl + +# vamomaxuei8.v 31..27=0x1c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +# vamomaxuei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamomaxuei8.v vd, (rs1), vs2, vs3, vm is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl + +# vamomaxuei8.v 31..27=0x1c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +# vamomaxuei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamomaxuei8.v zero, (rs1), vs2, vs3, vm is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl + +# vamominei16.v 31..27=0x10 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +# vamominei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamominei16.v vd, (rs1), vs2, vs3, vm is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl + +# vamominei16.v 31..27=0x10 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +# vamominei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamominei16.v zero, (rs1), vs2, vs3, vm is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl + +# vamominei32.v 31..27=0x10 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +# vamominei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamominei32.v vd, (rs1), vs2, vs3, vm is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl + +# vamominei32.v 31..27=0x10 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +# vamominei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamominei32.v zero, (rs1), vs2, vs3, vm is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl + +# vamominei64.v 31..27=0x10 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +# vamominei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamominei64.v vd, (rs1), vs2, vs3, vm is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl + +# vamominei64.v 31..27=0x10 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +# vamominei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamominei64.v zero, (rs1), vs2, vs3, vm is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl + +# vamominei8.v 31..27=0x10 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +# vamominei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamominei8.v vd, (rs1), vs2, vs3, vm is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl + +# vamominei8.v 31..27=0x10 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +# vamominei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamominei8.v zero, (rs1), vs2, vs3, vm is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl + +# vamominuei16.v 31..27=0x18 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +# vamominuei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamominuei16.v vd, (rs1), vs2, vs3, vm is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl + +# vamominuei16.v 31..27=0x18 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +# vamominuei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamominuei16.v zero, (rs1), vs2, vs3, vm is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl + +# vamominuei32.v 31..27=0x18 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +# vamominuei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamominuei32.v vd, (rs1), vs2, vs3, vm is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl + +# vamominuei32.v 31..27=0x18 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +# vamominuei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamominuei32.v zero, (rs1), vs2, vs3, vm is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl + +# vamominuei64.v 31..27=0x18 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +# vamominuei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamominuei64.v vd, (rs1), vs2, vs3, vm is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl + +# vamominuei64.v 31..27=0x18 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +# vamominuei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamominuei64.v zero, (rs1), vs2, vs3, vm is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl + +# vamominuei8.v 31..27=0x18 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +# vamominuei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamominuei8.v vd, (rs1), vs2, vs3, vm is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl + +# vamominuei8.v 31..27=0x18 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +# vamominuei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamominuei8.v zero, (rs1), vs2, vs3, vm is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl + +# vamoorei16.v 31..27=0x08 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +# vamoorei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamoorei16.v vd, (rs1), vs2, vs3, vm is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl + +# vamoorei16.v 31..27=0x08 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +# vamoorei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamoorei16.v zero, (rs1), vs2, vs3, vm is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl + +# vamoorei32.v 31..27=0x08 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +# vamoorei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamoorei32.v vd, (rs1), vs2, vs3, vm is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl + +# vamoorei32.v 31..27=0x08 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +# vamoorei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamoorei32.v zero, (rs1), vs2, vs3, vm is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl + +# vamoorei64.v 31..27=0x08 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +# vamoorei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamoorei64.v vd, (rs1), vs2, vs3, vm is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl + +# vamoorei64.v 31..27=0x08 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +# vamoorei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamoorei64.v zero, (rs1), vs2, vs3, vm is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl + +# vamoorei8.v 31..27=0x08 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +# vamoorei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamoorei8.v vd, (rs1), vs2, vs3, vm is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl + +# vamoorei8.v 31..27=0x08 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +# vamoorei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamoorei8.v zero, (rs1), vs2, vs3, vm is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl + +# vamoswapei16.v 31..27=0x01 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +# vamoswapei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamoswapei16.v vd, (rs1), vs2, vs3, vm is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl + +# vamoswapei16.v 31..27=0x01 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +# vamoswapei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamoswapei16.v zero, (rs1), vs2, vs3, vm is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl + +# vamoswapei32.v 31..27=0x01 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +# vamoswapei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamoswapei32.v vd, (rs1), vs2, vs3, vm is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl + +# vamoswapei32.v 31..27=0x01 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +# vamoswapei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamoswapei32.v zero, (rs1), vs2, vs3, vm is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl + +# vamoswapei64.v 31..27=0x01 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +# vamoswapei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamoswapei64.v vd, (rs1), vs2, vs3, vm is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl + +# vamoswapei64.v 31..27=0x01 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +# vamoswapei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamoswapei64.v zero, (rs1), vs2, vs3, vm is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl + +# vamoswapei8.v 31..27=0x01 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +# vamoswapei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamoswapei8.v vd, (rs1), vs2, vs3, vm is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl + +# vamoswapei8.v 31..27=0x01 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +# vamoswapei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamoswapei8.v zero, (rs1), vs2, vs3, vm is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl + +# vamoxorei16.v 31..27=0x04 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +# vamoxorei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamoxorei16.v vd, (rs1), vs2, vs3, vm is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl + +# vamoxorei16.v 31..27=0x04 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +# vamoxorei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamoxorei16.v zero, (rs1), vs2, vs3, vm is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl + +# vamoxorei32.v 31..27=0x04 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +# vamoxorei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamoxorei32.v vd, (rs1), vs2, vs3, vm is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl + +# vamoxorei32.v 31..27=0x04 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +# vamoxorei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamoxorei32.v zero, (rs1), vs2, vs3, vm is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl + +# vamoxorei64.v 31..27=0x04 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +# vamoxorei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamoxorei64.v vd, (rs1), vs2, vs3, vm is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl + +# vamoxorei64.v 31..27=0x04 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +# vamoxorei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamoxorei64.v zero, (rs1), vs2, vs3, vm is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl + +# vamoxorei8.v 31..27=0x04 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +# vamoxorei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 +:vamoxorei8.v vd, (rs1), vs2, vs3, vm is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl + +# vamoxorei8.v 31..27=0x04 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +# vamoxorei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 +:vamoxorei8.v zero, (rs1), vs2, vs3, vm is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & vd & op0006=0x2f unimpl + +# vand.vi 31..26=0x09 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vand.vi vd, vs2, simm5, vm # vector-immediate +:vand.vi vd, vs2, simm5, vm is op2631=0x9 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vand.vv 31..26=0x09 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vand.vv vd, vs2, vs1, vm # Vector-vector +:vand.vv vd, vs2, vs1, vm is op2631=0x9 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vand.vx 31..26=0x09 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vand.vx vd, vs2, rs1, vm # vector-scalar +:vand.vx vd, vs2, rs1, vm is op2631=0x9 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vasub.vv 31..26=0x0b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vasub.vv vd, vs2, vs1, vm # roundoff_signed(vs2[i] - vs1[i], 1) +:vasub.vv vd, vs2, vs1, vm is op2631=0xb & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vasub.vx 31..26=0x0b vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vasub.vx vd, vs2, rs1, vm # roundoff_signed(vs2[i] - x[rs1], 1) +:vasub.vx vd, vs2, rs1, vm is op2631=0xb & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vasubu.vv 31..26=0x0a vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vasubu.vv vd, vs2, vs1, vm # roundoff_unsigned(vs2[i] - vs1[i], 1) +:vasubu.vv vd, vs2, vs1, vm is op2631=0xa & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vasubu.vx 31..26=0x0a vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vasubu.vx vd, vs2, rs1, vm # roundoff_unsigned(vs2[i] - x[rs1], 1) +:vasubu.vx vd, vs2, rs1, vm is op2631=0xa & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vcompress.vm 31..26=0x17 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vcompress.vm vd, vs2, vs1 # Compress into vd elements of vs2 where vs1 is enabled +:vcompress.vm vd, vs2, vs1 is op2631=0x17 & op2525=0x1 & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vdiv.vv 31..26=0x21 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vdiv.vv vd, vs2, vs1, vm # Vector-vector +:vdiv.vv vd, vs2, vs1, vm is op2631=0x21 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vdiv.vx 31..26=0x21 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vdiv.vx vd, vs2, rs1, vm # vector-scalar +:vdiv.vx vd, vs2, rs1, vm is op2631=0x21 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vdivu.vv 31..26=0x20 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vdivu.vv vd, vs2, vs1, vm # Vector-vector +:vdivu.vv vd, vs2, vs1, vm is op2631=0x20 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vdivu.vx 31..26=0x20 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vdivu.vx vd, vs2, rs1, vm # vector-scalar +:vdivu.vx vd, vs2, rs1, vm is op2631=0x20 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vdot.vv 31..26=0x39 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vdot.vv vd, vs2, vs1, vm # Vector-vector +:vdot.vv vd, vs2, vs1, vm is op2631=0x39 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vdotu.vv 31..26=0x38 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vdotu.vv vd, vs2, vs1, vm # Vector-vector +:vdotu.vv vd, vs2, vs1, vm is op2631=0x38 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vfadd.vf 31..26=0x00 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfadd.vf vd, vs2, rs1, vm # vector-scalar +:vfadd.vf vd, vs2, rs1, vm is op2631=0x0 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfadd.vv 31..26=0x00 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfadd.vv vd, vs2, vs1, vm # Vector-vector +:vfadd.vv vd, vs2, vs1, vm is op2631=0x0 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfclass.v 31..26=0x13 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57 +# vfclass.v vd, vs2, vm # Vector-vector +:vfclass.v vd, vs2, vm is op2631=0x13 & vm & vs2 & op1519=0x10 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfcvt.f.x.v 31..26=0x12 vm vs2 19..15=0x03 14..12=0x1 vd 6..0=0x57 +# vfcvt.f.x.v vd, vs2, vm # Convert signed integer to float. +:vfcvt.f.x.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x3 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfcvt.f.xu.v 31..26=0x12 vm vs2 19..15=0x02 14..12=0x1 vd 6..0=0x57 +# vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. +:vfcvt.f.xu.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x2 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfcvt.rtz.x.f.v 31..26=0x12 vm vs2 19..15=0x07 14..12=0x1 vd 6..0=0x57 +# vfcvt.rtz.x.f.v vd, vs2, vm # Convert float to signed integer, truncating. +:vfcvt.rtz.x.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x7 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfcvt.rtz.xu.f.v 31..26=0x12 vm vs2 19..15=0x06 14..12=0x1 vd 6..0=0x57 +# vfcvt.rtz.xu.f.v vd, vs2, vm # Convert float to unsigned integer, truncating. +:vfcvt.rtz.xu.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x6 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfcvt.x.f.v 31..26=0x12 vm vs2 19..15=0x01 14..12=0x1 vd 6..0=0x57 +# vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. +:vfcvt.x.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfcvt.xu.f.v 31..26=0x12 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57 +# vfcvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. +:vfcvt.xu.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x0 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfdiv.vf 31..26=0x20 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfdiv.vf vd, vs2, rs1, vm # vector-scalar +:vfdiv.vf vd, vs2, rs1, vm is op2631=0x20 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfdiv.vv 31..26=0x20 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfdiv.vv vd, vs2, vs1, vm # Vector-vector +:vfdiv.vv vd, vs2, vs1, vm is op2631=0x20 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfdot.vv 31..26=0x39 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfdot.vv vd, vs2, vs1, vm # Vector-vector +:vfdot.vv vd, vs2, vs1, vm is op2631=0x39 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfirst.m 31..26=0x10 vm vs2 19..15=0x11 14..12=0x2 rd 6..0=0x57 +# vfirst.m rd, vs2, vm +:vfirst.m rd, vs2, vm is op2631=0x10 & vm & vs2 & op1519=0x11 & op1214=0x2 & rd & op0006=0x57 unimpl + +# vfmacc.vf 31..26=0x2c vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfmacc.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) + vd[i] +:vfmacc.vf vd, rs1, vs2, vm is op2631=0x2c & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfmacc.vv 31..26=0x2c vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] +:vfmacc.vv vd, vs1, vs2, vm is op2631=0x2c & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfmadd.vf 31..26=0x28 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfmadd.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vd[i]) + vs2[i] +:vfmadd.vf vd, rs1, vs2, vm is op2631=0x28 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfmadd.vv 31..26=0x28 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfmadd.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vd[i]) + vs2[i] +:vfmadd.vv vd, vs1, vs2, vm is op2631=0x28 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfmax.vf 31..26=0x06 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfmax.vf vd, vs2, rs1, vm # vector-scalar +:vfmax.vf vd, vs2, rs1, vm is op2631=0x6 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfmax.vv 31..26=0x06 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfmax.vv vd, vs2, vs1, vm # Vector-vector +:vfmax.vv vd, vs2, vs1, vm is op2631=0x6 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfmerge.vfm 31..26=0x17 25=0 vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfmerge.vfm vd, vs2, rs1, v0 # vd[i] = v0.mask[i] ? f[rs1] : vs2[i] +:vfmerge.vfm vd, vs2, rs1, v0 is op2631=0x17 & op2525=0x0 & vs2 & rs1 & op1214=0x5 & v0 & vd & op0006=0x57 unimpl + +# vfmin.vf 31..26=0x04 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfmin.vf vd, vs2, rs1, vm # vector-scalar +:vfmin.vf vd, vs2, rs1, vm is op2631=0x4 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfmin.vv 31..26=0x04 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfmin.vv vd, vs2, vs1, vm # Vector-vector +:vfmin.vv vd, vs2, vs1, vm is op2631=0x4 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfmsac.vf 31..26=0x2e vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfmsac.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) - vd[i] +:vfmsac.vf vd, rs1, vs2, vm is op2631=0x2e & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfmsac.vv 31..26=0x2e vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfmsac.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) - vd[i] +:vfmsac.vv vd, vs1, vs2, vm is op2631=0x2e & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfmsub.vf 31..26=0x2a vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfmsub.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vd[i]) - vs2[i] +:vfmsub.vf vd, rs1, vs2, vm is op2631=0x2a & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfmsub.vv 31..26=0x2a vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfmsub.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vd[i]) - vs2[i] +:vfmsub.vv vd, vs1, vs2, vm is op2631=0x2a & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfmul.vf 31..26=0x24 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfmul.vf vd, vs2, rs1, vm # vector-scalar +:vfmul.vf vd, vs2, rs1, vm is op2631=0x24 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfmul.vv 31..26=0x24 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfmul.vv vd, vs2, vs1, vm # Vector-vector +:vfmul.vv vd, vs2, vs1, vm is op2631=0x24 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfmv.f.s 31..26=0x10 25=1 vs2 19..15=0 14..12=0x1 rd 6..0=0x57 +# vfmv.f.s rd, vs2 # f[rd] = vs2[0] (rs1=0) +:vfmv.f.s rd, vs2 is op2631=0x10 & op2525=0x1 & vs2 & op1519=0x0 & op1214=0x1 & rd & op0006=0x57 unimpl + +# vfmv.s.f 31..26=0x10 25=1 24..20=0 rs1 14..12=0x5 vd 6..0=0x57 +# vfmv.s.f vd, rs1 # vd[0] = f[rs1] (vs2=0) +:vfmv.s.f vd, rs1 is op2631=0x10 & op2525=0x1 & op2024=0x0 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfmv.v.f 31..26=0x17 25=1 24..20=0 rs1 14..12=0x5 vd 6..0=0x57 +# vfmv.v.f vd, rs1 # vd[i] = f[rs1] +:vfmv.v.f vd, rs1 is op2631=0x17 & op2525=0x1 & op2024=0x0 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfncvt.f.f.w 31..26=0x12 vm vs2 19..15=0x14 14..12=0x1 vd 6..0=0x57 +# vfncvt.f.f.w vd, vs2, vm # Convert double-width float to single-width float. +:vfncvt.f.f.w vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x14 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfncvt.f.x.w 31..26=0x12 vm vs2 19..15=0x13 14..12=0x1 vd 6..0=0x57 +# vfncvt.f.x.w vd, vs2, vm # Convert double-width signed integer to float. +:vfncvt.f.x.w vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x13 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfncvt.f.xu.w 31..26=0x12 vm vs2 19..15=0x12 14..12=0x1 vd 6..0=0x57 +# vfncvt.f.xu.w vd, vs2, vm # Convert double-width unsigned integer to float. +:vfncvt.f.xu.w vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x12 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfncvt.rod.f.f.w 31..26=0x12 vm vs2 19..15=0x15 14..12=0x1 vd 6..0=0x57 +# vfncvt.rod.f.f.w vd, vs2, vm # Convert double-width float to single-width float, +:vfncvt.rod.f.f.w vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x15 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfncvt.rtz.x.f.w 31..26=0x12 vm vs2 19..15=0x17 14..12=0x1 vd 6..0=0x57 +# vfncvt.rtz.x.f.w vd, vs2, vm # Convert double-width float to signed integer, truncating. +:vfncvt.rtz.x.f.w vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x17 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfncvt.rtz.xu.f.w 31..26=0x12 vm vs2 19..15=0x16 14..12=0x1 vd 6..0=0x57 +# vfncvt.rtz.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer, truncating. +:vfncvt.rtz.xu.f.w vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x16 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfncvt.x.f.w 31..26=0x12 vm vs2 19..15=0x11 14..12=0x1 vd 6..0=0x57 +# vfncvt.x.f.w vd, vs2, vm # Convert double-width float to signed integer. +:vfncvt.x.f.w vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x11 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfncvt.xu.f.w 31..26=0x12 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57 +# vfncvt.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer. +:vfncvt.xu.f.w vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x10 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfnmacc.vf 31..26=0x2d vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfnmacc.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) - vd[i] +:vfnmacc.vf vd, rs1, vs2, vm is op2631=0x2d & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfnmacc.vv 31..26=0x2d vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfnmacc.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) - vd[i] +:vfnmacc.vv vd, vs1, vs2, vm is op2631=0x2d & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfnmadd.vf 31..26=0x29 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfnmadd.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vd[i]) - vs2[i] +:vfnmadd.vf vd, rs1, vs2, vm is op2631=0x29 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfnmadd.vv 31..26=0x29 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfnmadd.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vd[i]) - vs2[i] +:vfnmadd.vv vd, vs1, vs2, vm is op2631=0x29 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfnmsac.vf 31..26=0x2f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfnmsac.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) + vd[i] +:vfnmsac.vf vd, rs1, vs2, vm is op2631=0x2f & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfnmsac.vv 31..26=0x2f vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i] +:vfnmsac.vv vd, vs1, vs2, vm is op2631=0x2f & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfnmsub.vf 31..26=0x2b vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfnmsub.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vd[i]) + vs2[i] +:vfnmsub.vf vd, rs1, vs2, vm is op2631=0x2b & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfnmsub.vv 31..26=0x2b vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfnmsub.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vd[i]) + vs2[i] +:vfnmsub.vv vd, vs1, vs2, vm is op2631=0x2b & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfrdiv.vf 31..26=0x21 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfrdiv.vf vd, vs2, rs1, vm # scalar-vector, vd[i] = f[rs1]/vs2[i] +:vfrdiv.vf vd, vs2, rs1, vm is op2631=0x21 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfredmax.vs 31..26=0x07 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfredmax.vs vd, vs2, vs1, vm # Maximum value +:vfredmax.vs vd, vs2, vs1, vm is op2631=0x7 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfredmin.vs 31..26=0x05 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfredmin.vs vd, vs2, vs1, vm # Minimum value +:vfredmin.vs vd, vs2, vs1, vm is op2631=0x5 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfredosum.vs 31..26=0x03 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfredosum.vs vd, vs2, vs1, vm # Ordered sum +:vfredosum.vs vd, vs2, vs1, vm is op2631=0x3 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfredsum.vs 31..26=0x01 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfredsum.vs vd, vs2, vs1, vm # Unordered sum +:vfredsum.vs vd, vs2, vs1, vm is op2631=0x1 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfrsub.vf 31..26=0x27 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfrsub.vf vd, vs2, rs1, vm # Scalar-vector vd[i] = f[rs1] - vs2[i] +:vfrsub.vf vd, vs2, rs1, vm is op2631=0x27 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfsgnj.vf 31..26=0x08 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfsgnj.vf vd, vs2, rs1, vm # vector-scalar +:vfsgnj.vf vd, vs2, rs1, vm is op2631=0x8 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfsgnj.vv 31..26=0x08 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfsgnj.vv vd, vs2, vs1, vm # Vector-vector +:vfsgnj.vv vd, vs2, vs1, vm is op2631=0x8 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfsgnjn.vf 31..26=0x09 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfsgnjn.vf vd, vs2, rs1, vm # vector-scalar +:vfsgnjn.vf vd, vs2, rs1, vm is op2631=0x9 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfsgnjn.vv 31..26=0x09 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfsgnjn.vv vd, vs2, vs1, vm # Vector-vector +:vfsgnjn.vv vd, vs2, vs1, vm is op2631=0x9 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfsgnjx.vf 31..26=0x0a vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfsgnjx.vf vd, vs2, rs1, vm # vector-scalar +:vfsgnjx.vf vd, vs2, rs1, vm is op2631=0xa & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfsgnjx.vv 31..26=0x0a vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfsgnjx.vv vd, vs2, vs1, vm # Vector-vector +:vfsgnjx.vv vd, vs2, vs1, vm is op2631=0xa & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfslide1down.vf 31..26=0x0f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfslide1down.vf vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=f[rs1] +:vfslide1down.vf vd, vs2, rs1, vm is op2631=0xf & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfslide1up.vf 31..26=0x0e vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfslide1up.vf vd, vs2, rs1, vm # vd[0]=f[rs1], vd[i+1] = vs2[i] +:vfslide1up.vf vd, vs2, rs1, vm is op2631=0xe & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfsqrt.v 31..26=0x13 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57 +# vfsqrt.v vd, vs2, vm # Vector-vector square root +:vfsqrt.v vd, vs2, vm is op2631=0x13 & vm & vs2 & op1519=0x0 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfsub.vf 31..26=0x02 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfsub.vf vd, vs2, rs1, vm # Vector-scalar vd[i] = vs2[i] - f[rs1] +:vfsub.vf vd, vs2, rs1, vm is op2631=0x2 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfsub.vv 31..26=0x02 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfsub.vv vd, vs2, vs1, vm # Vector-vector +:vfsub.vv vd, vs2, vs1, vm is op2631=0x2 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfwadd.vf 31..26=0x30 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfwadd.vf vd, vs2, rs1, vm # vector-scalar +:vfwadd.vf vd, vs2, rs1, vm is op2631=0x30 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfwadd.vv 31..26=0x30 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfwadd.vv vd, vs2, vs1, vm # vector-vector +:vfwadd.vv vd, vs2, vs1, vm is op2631=0x30 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfwadd.wf 31..26=0x34 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfwadd.wf vd, vs2, rs1, vm # vector-scalar +:vfwadd.wf vd, vs2, rs1, vm is op2631=0x34 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfwadd.wv 31..26=0x34 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfwadd.wv vd, vs2, vs1, vm # vector-vector +:vfwadd.wv vd, vs2, vs1, vm is op2631=0x34 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfwcvt.f.f.v 31..26=0x12 vm vs2 19..15=0x0C 14..12=0x1 vd 6..0=0x57 +# vfwcvt.f.f.v vd, vs2, vm # Convert single-width float to double-width float. +:vfwcvt.f.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0xc & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfwcvt.f.x.v 31..26=0x12 vm vs2 19..15=0x0B 14..12=0x1 vd 6..0=0x57 +# vfwcvt.f.x.v vd, vs2, vm # Convert signed integer to double-width float. +:vfwcvt.f.x.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0xb & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfwcvt.f.xu.v 31..26=0x12 vm vs2 19..15=0x0A 14..12=0x1 vd 6..0=0x57 +# vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float. +:vfwcvt.f.xu.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0xa & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfwcvt.rtz.x.f.v 31..26=0x12 vm vs2 19..15=0x0F 14..12=0x1 vd 6..0=0x57 +# vfwcvt.rtz.x.f.v vd, vs2, vm # Convert float to double-width signed integer, truncating. +:vfwcvt.rtz.x.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0xf & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfwcvt.rtz.xu.f.v 31..26=0x12 vm vs2 19..15=0x0E 14..12=0x1 vd 6..0=0x57 +# vfwcvt.rtz.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer, truncating. +:vfwcvt.rtz.xu.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0xe & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfwcvt.x.f.v 31..26=0x12 vm vs2 19..15=0x09 14..12=0x1 vd 6..0=0x57 +# vfwcvt.x.f.v vd, vs2, vm # Convert float to double-width signed integer. +:vfwcvt.x.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x9 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfwcvt.xu.f.v 31..26=0x12 vm vs2 19..15=0x08 14..12=0x1 vd 6..0=0x57 +# vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer. +:vfwcvt.xu.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x8 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfwmacc.vf 31..26=0x3c vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfwmacc.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) + vd[i] +:vfwmacc.vf vd, rs1, vs2, vm is op2631=0x3c & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfwmacc.vv 31..26=0x3c vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfwmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] +:vfwmacc.vv vd, vs1, vs2, vm is op2631=0x3c & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfwmsac.vf 31..26=0x3e vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfwmsac.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) - vd[i] +:vfwmsac.vf vd, rs1, vs2, vm is op2631=0x3e & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfwmsac.vv 31..26=0x3e vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfwmsac.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) - vd[i] +:vfwmsac.vv vd, vs1, vs2, vm is op2631=0x3e & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfwmul.vf 31..26=0x38 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfwmul.vf vd, vs2, rs1, vm # vector-scalar +:vfwmul.vf vd, vs2, rs1, vm is op2631=0x38 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfwmul.vv 31..26=0x38 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfwmul.vv vd, vs2, vs1, vm # vector-vector +:vfwmul.vv vd, vs2, vs1, vm is op2631=0x38 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfwnmacc.vf 31..26=0x3d vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfwnmacc.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) - vd[i] +:vfwnmacc.vf vd, rs1, vs2, vm is op2631=0x3d & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfwnmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfwnmacc.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) - vd[i] +:vfwnmacc.vv vd, vs1, vs2, vm is op2631=0x3d & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfwnmsac.vf 31..26=0x3f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfwnmsac.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) + vd[i] +:vfwnmsac.vf vd, rs1, vs2, vm is op2631=0x3f & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfwnmsac.vv 31..26=0x3f vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfwnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i] +:vfwnmsac.vv vd, vs1, vs2, vm is op2631=0x3f & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfwredosum.vs 31..26=0x33 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfwredosum.vs vd, vs2, vs1, vm # Ordered sum +:vfwredosum.vs vd, vs2, vs1, vm is op2631=0x33 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfwredsum.vs vd, vs2, vs1, vm # Unordered sum +:vfwredsum.vs vd, vs2, vs1, vm is op2631=0x31 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfwsub.vf 31..26=0x32 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfwsub.vf vd, vs2, rs1, vm # vector-scalar +:vfwsub.vf vd, vs2, rs1, vm is op2631=0x32 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfwsub.vv 31..26=0x32 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfwsub.vv vd, vs2, vs1, vm # vector-vector +:vfwsub.vv vd, vs2, vs1, vm is op2631=0x32 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vfwsub.wf 31..26=0x36 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vfwsub.wf vd, vs2, rs1, vm # vector-scalar +:vfwsub.wf vd, vs2, rs1, vm is op2631=0x36 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vfwsub.wv 31..26=0x36 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vfwsub.wv vd, vs2, vs1, vm # vector-vector +:vfwsub.wv vd, vs2, vs1, vm is op2631=0x36 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vid.v 31..26=0x14 vm 24..20=0 19..15=0x11 14..12=0x2 vd 6..0=0x57 +# vid.v vd, vm # Write element ID to destination. +:vid.v vd, vm is op2631=0x14 & vm & op2024=0x0 & op1519=0x11 & op1214=0x2 & vd & op0006=0x57 unimpl + +# viota.m 31..26=0x14 vm vs2 19..15=0x10 14..12=0x2 vd 6..0=0x57 +# viota.m vd, vs2, vm +:viota.m vd, vs2, vm is op2631=0x14 & vm & vs2 & op1519=0x10 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vl1re16.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 +# vl1re16.v vd, (rs1) +:vl1re16.v vd, (rs1) is op2931=0x0 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl + +# vl1re32.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 +# vl1re32.v vd, (rs1) +:vl1re32.v vd, (rs1) is op2931=0x0 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl + +# vl1re64.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 +# vl1re64.v vd, (rs1) +:vl1re64.v vd, (rs1) is op2931=0x0 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl + +# vl1re8.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +# vl1re8.v vd, (rs1) +:vl1re8.v vd, (rs1) is op2931=0x0 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl + +# vl2re16.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 +# vl2re16.v vd, (rs1) +:vl2re16.v vd, (rs1) is op2931=0x1 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl + +# vl2re32.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 +# vl2re32.v vd, (rs1) +:vl2re32.v vd, (rs1) is op2931=0x1 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl + +# vl2re64.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 +# vl2re64.v vd, (rs1) +:vl2re64.v vd, (rs1) is op2931=0x1 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl + +# vl2re8.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +# vl2re8.v vd, (rs1) +:vl2re8.v vd, (rs1) is op2931=0x1 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl + +# vl4re16.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 +# vl4re16.v vd, (rs1) +:vl4re16.v vd, (rs1) is op2931=0x3 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl + +# vl4re32.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 +# vl4re32.v vd, (rs1) +:vl4re32.v vd, (rs1) is op2931=0x3 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl + +# vl4re64.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 +# vl4re64.v vd, (rs1) +:vl4re64.v vd, (rs1) is op2931=0x3 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl + +# vl4re8.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +# vl4re8.v vd, (rs1) +:vl4re8.v vd, (rs1) is op2931=0x3 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl + +# vl8re16.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 +# vl8re16.v vd, (rs1) +:vl8re16.v vd, (rs1) is op2931=0x7 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl + +# vl8re32.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 +# vl8re32.v vd, (rs1) +:vl8re32.v vd, (rs1) is op2931=0x7 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl + +# vl8re64.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 +# vl8re64.v vd, (rs1) +:vl8re64.v vd, (rs1) is op2931=0x7 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl + +# vl8re8.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +# vl8re8.v vd, (rs1) +:vl8re8.v vd, (rs1) is op2931=0x7 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl + +# vle1024.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x7 vd 6..0=0x07 +# vle1024.v vd, (rs1), vm # 1024-bit unit-stride load +:vle1024.v vd, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl + +# vle1024ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x7 vd 6..0=0x07 +# vle1024ff.v vd, (rs1), vm # 1024-bit unit-stride fault-only-first load +:vle1024ff.v vd, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl + +# vle128.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07 +# vle128.v vd, (rs1), vm # 128-bit unit-stride load +:vle128.v vd, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl + +# vle128ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x0 vd 6..0=0x07 +# vle128ff.v vd, (rs1), vm # 128-bit unit-stride fault-only-first load +:vle128ff.v vd, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl + +# vle16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07 +# vle16.v vd, (rs1), vm # 16-bit unit-stride load +:vle16.v vd, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl + +# vle16ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x5 vd 6..0=0x07 +# vle16ff.v vd, (rs1), vm # 16-bit unit-stride fault-only-first load +:vle16ff.v vd, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl + +# vle256.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07 +# vle256.v vd, (rs1), vm # 256-bit unit-stride load +:vle256.v vd, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl + +# vle256ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x5 vd 6..0=0x07 +# vle256ff.v vd, (rs1), vm # 256-bit unit-stride fault-only-first load +:vle256ff.v vd, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl + +# vle32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07 +# vle32.v vd, (rs1), vm # 32-bit unit-stride load +:vle32.v vd, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl + +# vle32ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x6 vd 6..0=0x07 +# vle32ff.v vd, (rs1), vm # 32-bit unit-stride fault-only-first load +:vle32ff.v vd, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl + +# vle512.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07 +# vle512.v vd, (rs1), vm # 512-bit unit-stride load +:vle512.v vd, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl + +# vle512ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x6 vd 6..0=0x07 +# vle512ff.v vd, (rs1), vm # 512-bit unit-stride fault-only-first load +:vle512ff.v vd, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl + +# vle64.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7 vd 6..0=0x07 +# vle64.v vd, (rs1), vm # 64-bit unit-stride load +:vle64.v vd, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl + +# vle64ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x7 vd 6..0=0x07 +# vle64ff.v vd, (rs1), vm # 64-bit unit-stride fault-only-first load +:vle64ff.v vd, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl + +# vle8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07 +# vle8.v vd, (rs1), vm # 8-bit unit-stride load +:vle8.v vd, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl + +# vle8ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x0 vd 6..0=0x07 +# vle8ff.v vd, (rs1), vm # 8-bit unit-stride fault-only-first load +:vle8ff.v vd, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl + +# vlse1024.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x7 vd 6..0=0x07 +# vlse1024.v vd, (rs1), rs2, vm # 1024-bit strided load +:vlse1024.v vd, (rs1), rs2, vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl + +# vlse128.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x0 vd 6..0=0x07 +# vlse128.v vd, (rs1), rs2, vm # 128-bit strided load +:vlse128.v vd, (rs1), rs2, vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl + +# vlse16.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5 vd 6..0=0x07 +# vlse16.v vd, (rs1), rs2, vm # 16-bit strided load +:vlse16.v vd, (rs1), rs2, vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl + +# vlse256.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x5 vd 6..0=0x07 +# vlse256.v vd, (rs1), rs2, vm # 256-bit strided load +:vlse256.v vd, (rs1), rs2, vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl + +# vlse32.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6 vd 6..0=0x07 +# vlse32.v vd, (rs1), rs2, vm # 32-bit strided load +:vlse32.v vd, (rs1), rs2, vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl + +# vlse512.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x6 vd 6..0=0x07 +# vlse512.v vd, (rs1), rs2, vm # 512-bit strided load +:vlse512.v vd, (rs1), rs2, vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl + +# vlse64.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7 vd 6..0=0x07 +# vlse64.v vd, (rs1), rs2, vm # 64-bit strided load +:vlse64.v vd, (rs1), rs2, vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl + +# vlse8.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0 vd 6..0=0x07 +# vlse8.v vd, (rs1), rs2, vm # 8-bit strided load +:vlse8.v vd, (rs1), rs2, vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl + +# vlxei1024.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 +# vlxei1024.v vd, (rs1), vs2, vm # 1024-bit indexed load of SEW data +:vlxei1024.v vd, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl + +# vlxei128.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 +# vlxei128.v vd, (rs1), vs2, vm # 128-bit indexed load of SEW data +:vlxei128.v vd, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl + +# vlxei16.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 +# vlxei16.v vd, (rs1), vs2, vm # 16-bit indexed load of SEW data +:vlxei16.v vd, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl + +# vlxei256.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 +# vlxei256.v vd, (rs1), vs2, vm # 256-bit indexed load of SEW data +:vlxei256.v vd, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl + +# vlxei32.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 +# vlxei32.v vd, (rs1), vs2, vm # 32-bit indexed load of SEW data +:vlxei32.v vd, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl + +# vlxei512.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 +# vlxei512.v vd, (rs1), vs2, vm # 512-bit indexed load of SEW data +:vlxei512.v vd, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl + +# vlxei64.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 +# vlxei64.v vd, (rs1), vs2, vm # 64-bit indexed load of SEW data +:vlxei64.v vd, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl + +# vlxei8.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 +# vlxei8.v vd, (rs1), vs2, vm # 8-bit indexed load of SEW data +:vlxei8.v vd, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl + +# vmacc.vv 31..26=0x2d vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] +:vmacc.vv vd, vs1, vs2, vm is op2631=0x2d & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vmacc.vx 31..26=0x2d vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] +:vmacc.vx vd, rs1, vs2, vm is op2631=0x2d & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vmadc.vim 31..26=0x11 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vmadc.vim vd, vs2, simm5, v0 # Vector-immediate +:vmadc.vim vd, vs2, simm5, v0 is op2631=0x11 & vm & vs2 & simm5 & op1214=0x3 & v0 & vd & op0006=0x57 unimpl + +# vmadc.vvm 31..26=0x11 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vmadc.vvm vd, vs2, vs1, v0 # Vector-vector +:vmadc.vvm vd, vs2, vs1, v0 is op2631=0x11 & vm & vs2 & vs1 & op1214=0x0 & v0 & vd & op0006=0x57 unimpl + +# vmadc.vxm 31..26=0x11 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vmadc.vxm vd, vs2, rs1, v0 # Vector-scalar +:vmadc.vxm vd, vs2, rs1, v0 is op2631=0x11 & vm & vs2 & rs1 & op1214=0x4 & v0 & vd & op0006=0x57 unimpl + +# vmadd.vv 31..26=0x29 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vmadd.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vd[i]) + vs2[i] +:vmadd.vv vd, vs1, vs2, vm is op2631=0x29 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vmadd.vx 31..26=0x29 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vmadd.vx vd, rs1, vs2, vm # vd[i] = (x[rs1] * vd[i]) + vs2[i] +:vmadd.vx vd, rs1, vs2, vm is op2631=0x29 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vmand.mm 31..26=0x19 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vmand.mm vd, vs2, vs1 # vd[i] = vs2.mask[i] && vs1.mask[i] +:vmand.mm vd, vs2, vs1 is op2631=0x19 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vmandnot.mm 31..26=0x18 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vmandnot.mm vd, vs2, vs1 # vd[i] = vs2.mask[i] && !vs1.mask[i] +:vmandnot.mm vd, vs2, vs1 is op2631=0x18 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vmax.vv 31..26=0x07 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vmax.vv vd, vs2, vs1, vm # Vector-vector +:vmax.vv vd, vs2, vs1, vm is op2631=0x7 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vmax.vx 31..26=0x07 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vmax.vx vd, vs2, rs1, vm # vector-scalar +:vmax.vx vd, vs2, rs1, vm is op2631=0x7 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vmaxu.vv 31..26=0x06 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vmaxu.vv vd, vs2, vs1, vm # Vector-vector +:vmaxu.vv vd, vs2, vs1, vm is op2631=0x6 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vmaxu.vx 31..26=0x06 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vmaxu.vx vd, vs2, rs1, vm # vector-scalar +:vmaxu.vx vd, vs2, rs1, vm is op2631=0x6 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vmerge.vim 31..26=0x17 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vmerge.vim vd, vs2, simm5, v0 # vd[i] = v0.mask[i] ? imm : vs2[i] +:vmerge.vim vd, vs2, simm5, v0 is op2631=0x17 & op2525=0x0 & vs2 & simm5 & op1214=0x3 & v0 & vd & op0006=0x57 unimpl + +# vmerge.vvm 31..26=0x17 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vmerge.vvm vd, vs2, vs1, v0 # vd[i] = v0.mask[i] ? vs1[i] : vs2[i] +:vmerge.vvm vd, vs2, vs1, v0 is op2631=0x17 & op2525=0x0 & vs2 & vs1 & op1214=0x0 & v0 & vd & op0006=0x57 unimpl + +# vmerge.vxm 31..26=0x17 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vmerge.vxm vd, vs2, rs1, v0 # vd[i] = v0.mask[i] ? x[rs1] : vs2[i] +:vmerge.vxm vd, vs2, rs1, v0 is op2631=0x17 & op2525=0x0 & vs2 & rs1 & op1214=0x4 & v0 & vd & op0006=0x57 unimpl + +# vmfeq.vf 31..26=0x18 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vmfeq.vf vd, vs2, rs1, vm # vector-scalar +:vmfeq.vf vd, vs2, rs1, vm is op2631=0x18 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vmfeq.vv 31..26=0x18 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vmfeq.vv vd, vs2, vs1, vm # Vector-vector +:vmfeq.vv vd, vs2, vs1, vm is op2631=0x18 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vmfge.vf 31..26=0x1f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vmfge.vf vd, vs2, rs1, vm # vector-scalar +:vmfge.vf vd, vs2, rs1, vm is op2631=0x1f & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vmfgt.vf 31..26=0x1d vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vmfgt.vf vd, vs2, rs1, vm # vector-scalar +:vmfgt.vf vd, vs2, rs1, vm is op2631=0x1d & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vmfle.vf 31..26=0x19 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vmfle.vf vd, vs2, rs1, vm # vector-scalar +:vmfle.vf vd, vs2, rs1, vm is op2631=0x19 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vmfle.vv 31..26=0x19 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vmfle.vv vd, vs2, vs1, vm # Vector-vector +:vmfle.vv vd, vs2, vs1, vm is op2631=0x19 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vmflt.vf 31..26=0x1b vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vmflt.vf vd, vs2, rs1, vm # vector-scalar +:vmflt.vf vd, vs2, rs1, vm is op2631=0x1b & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vmflt.vv 31..26=0x1b vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vmflt.vv vd, vs2, vs1, vm # Vector-vector +:vmflt.vv vd, vs2, vs1, vm is op2631=0x1b & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vmfne.vf 31..26=0x1c vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +# vmfne.vf vd, vs2, rs1, vm # vector-scalar +:vmfne.vf vd, vs2, rs1, vm is op2631=0x1c & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl + +# vmfne.vv 31..26=0x1c vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +# vmfne.vv vd, vs2, vs1, vm # Vector-vector +:vmfne.vv vd, vs2, vs1, vm is op2631=0x1c & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl + +# vmin.vv 31..26=0x05 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vmin.vv vd, vs2, vs1, vm # Vector-vector +:vmin.vv vd, vs2, vs1, vm is op2631=0x5 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vmin.vx 31..26=0x05 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vmin.vx vd, vs2, rs1, vm # vector-scalar +:vmin.vx vd, vs2, rs1, vm is op2631=0x5 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vminu.vv 31..26=0x04 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vminu.vv vd, vs2, vs1, vm # Vector-vector +:vminu.vv vd, vs2, vs1, vm is op2631=0x4 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vminu.vx 31..26=0x04 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vminu.vx vd, vs2, rs1, vm # vector-scalar +:vminu.vx vd, vs2, rs1, vm is op2631=0x4 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vmnand.mm 31..26=0x1d vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vmnand.mm vd, vs2, vs1 # vd[i] = !(vs2.mask[i] && vs1.mask[i]) +:vmnand.mm vd, vs2, vs1 is op2631=0x1d & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vmnor.mm 31..26=0x1e vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vmnor.mm vd, vs2, vs1 # vd[i] = !(vs2.mask[i] || vs1.mask[i]) +:vmnor.mm vd, vs2, vs1 is op2631=0x1e & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vmor.mm 31..26=0x1a vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vmor.mm vd, vs2, vs1 # vd[i] = vs2.mask[i] || vs1.mask[i] +:vmor.mm vd, vs2, vs1 is op2631=0x1a & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vmornot.mm 31..26=0x1c vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vmornot.mm vd, vs2, vs1 # vd[i] = vs2.mask[i] || !vs1.mask[i] +:vmornot.mm vd, vs2, vs1 is op2631=0x1c & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vmsbc.vvm 31..26=0x13 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vmsbc.vvm vd, vs2, vs1, v0 # Vector-vector +:vmsbc.vvm vd, vs2, vs1, v0 is op2631=0x13 & vm & vs2 & vs1 & op1214=0x0 & v0 & vd & op0006=0x57 unimpl + +# vmsbc.vxm 31..26=0x13 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vmsbc.vxm vd, vs2, rs1, v0 # Vector-scalar +:vmsbc.vxm vd, vs2, rs1, v0 is op2631=0x13 & vm & vs2 & rs1 & op1214=0x4 & v0 & vd & op0006=0x57 unimpl + +# vmsbf.m 31..26=0x14 vm vs2 19..15=0x01 14..12=0x2 vd 6..0=0x57 +# vmsbf.m vd, vs2, vm +:vmsbf.m vd, vs2, vm is op2631=0x14 & vm & vs2 & op1519=0x1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vmseq.vi 31..26=0x18 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vmseq.vi vd, vs2, simm5, vm # vector-immediate +:vmseq.vi vd, vs2, simm5, vm is op2631=0x18 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vmseq.vv 31..26=0x18 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vmseq.vv vd, vs2, vs1, vm # Vector-vector +:vmseq.vv vd, vs2, vs1, vm is op2631=0x18 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vmseq.vx 31..26=0x18 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vmseq.vx vd, vs2, rs1, vm # vector-scalar +:vmseq.vx vd, vs2, rs1, vm is op2631=0x18 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vmsgt.vi 31..26=0x1f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vmsgt.vi vd, vs2, simm5, vm # Vector-immediate +:vmsgt.vi vd, vs2, simm5, vm is op2631=0x1f & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vmsgt.vx 31..26=0x1f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vmsgt.vx vd, vs2, rs1, vm # Vector-scalar +:vmsgt.vx vd, vs2, rs1, vm is op2631=0x1f & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vmsgtu.vi 31..26=0x1e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vmsgtu.vi vd, vs2, simm5, vm # Vector-immediate +:vmsgtu.vi vd, vs2, simm5, vm is op2631=0x1e & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vmsgtu.vx 31..26=0x1e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vmsgtu.vx vd, vs2, rs1, vm # Vector-scalar +:vmsgtu.vx vd, vs2, rs1, vm is op2631=0x1e & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vmsif.m 31..26=0x14 vm vs2 19..15=0x03 14..12=0x2 vd 6..0=0x57 +# vmsif.m vd, vs2, vm +:vmsif.m vd, vs2, vm is op2631=0x14 & vm & vs2 & op1519=0x3 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vmsle.vi 31..26=0x1d vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vmsle.vi vd, vs2, simm5, vm # vector-immediate +:vmsle.vi vd, vs2, simm5, vm is op2631=0x1d & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vmsle.vv 31..26=0x1d vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vmsle.vv vd, vs2, vs1, vm # Vector-vector +:vmsle.vv vd, vs2, vs1, vm is op2631=0x1d & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vmsle.vx 31..26=0x1d vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vmsle.vx vd, vs2, rs1, vm # vector-scalar +:vmsle.vx vd, vs2, rs1, vm is op2631=0x1d & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vmsleu.vi 31..26=0x1c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vmsleu.vi vd, vs2, simm5, vm # Vector-immediate +:vmsleu.vi vd, vs2, simm5, vm is op2631=0x1c & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vmsleu.vv 31..26=0x1c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vmsleu.vv vd, vs2, vs1, vm # Vector-vector +:vmsleu.vv vd, vs2, vs1, vm is op2631=0x1c & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vmsleu.vx 31..26=0x1c vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vmsleu.vx vd, vs2, rs1, vm # vector-scalar +:vmsleu.vx vd, vs2, rs1, vm is op2631=0x1c & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vmslt.vv 31..26=0x1b vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vmslt.vv vd, vs2, vs1, vm # Vector-vector +:vmslt.vv vd, vs2, vs1, vm is op2631=0x1b & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vmslt.vx 31..26=0x1b vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vmslt.vx vd, vs2, rs1, vm # vector-scalar +:vmslt.vx vd, vs2, rs1, vm is op2631=0x1b & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vmsltu.vv 31..26=0x1a vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vmsltu.vv vd, vs2, vs1, vm # Vector-vector +:vmsltu.vv vd, vs2, vs1, vm is op2631=0x1a & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vmsltu.vx 31..26=0x1a vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vmsltu.vx vd, vs2, rs1, vm # Vector-scalar +:vmsltu.vx vd, vs2, rs1, vm is op2631=0x1a & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vmsne.vi 31..26=0x19 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vmsne.vi vd, vs2, simm5, vm # vector-immediate +:vmsne.vi vd, vs2, simm5, vm is op2631=0x19 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vmsne.vv 31..26=0x19 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vmsne.vv vd, vs2, vs1, vm # Vector-vector +:vmsne.vv vd, vs2, vs1, vm is op2631=0x19 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vmsne.vx 31..26=0x19 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vmsne.vx vd, vs2, rs1, vm # vector-scalar +:vmsne.vx vd, vs2, rs1, vm is op2631=0x19 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vmsof.m 31..26=0x14 vm vs2 19..15=0x02 14..12=0x2 vd 6..0=0x57 +# vmsof.m vd, vs2, vm +:vmsof.m vd, vs2, vm is op2631=0x14 & vm & vs2 & op1519=0x2 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vmul.vv 31..26=0x25 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vmul.vv vd, vs2, vs1, vm # Vector-vector +:vmul.vv vd, vs2, vs1, vm is op2631=0x25 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vmul.vx 31..26=0x25 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vmul.vx vd, vs2, rs1, vm # vector-scalar +:vmul.vx vd, vs2, rs1, vm is op2631=0x25 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vmulh.vv 31..26=0x27 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vmulh.vv vd, vs2, vs1, vm # Vector-vector +:vmulh.vv vd, vs2, vs1, vm is op2631=0x27 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vmulh.vx 31..26=0x27 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vmulh.vx vd, vs2, rs1, vm # vector-scalar +:vmulh.vx vd, vs2, rs1, vm is op2631=0x27 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vmulhsu.vv 31..26=0x26 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vmulhsu.vv vd, vs2, vs1, vm # Vector-vector +:vmulhsu.vv vd, vs2, vs1, vm is op2631=0x26 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vmulhsu.vx 31..26=0x26 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vmulhsu.vx vd, vs2, rs1, vm # vector-scalar +:vmulhsu.vx vd, vs2, rs1, vm is op2631=0x26 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vmulhu.vv 31..26=0x24 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vmulhu.vv vd, vs2, vs1, vm # Vector-vector +:vmulhu.vv vd, vs2, vs1, vm is op2631=0x24 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vmulhu.vx 31..26=0x24 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vmulhu.vx vd, vs2, rs1, vm # vector-scalar +:vmulhu.vx vd, vs2, rs1, vm is op2631=0x24 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vmv.s.x 31..26=0x10 25=1 24..20=0 rs1 14..12=0x6 vd 6..0=0x57 +# vmv.s.x vd, rs1 # vd[0] = x[rs1] (vs2=0) +:vmv.s.x vd, rs1 is op2631=0x10 & op2525=0x1 & op2024=0x0 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vmv.v.i 31..26=0x17 25=1 24..20=0 simm5 14..12=0x3 vd 6..0=0x57 +# vmv.v.i vd, simm5 # vd[i] = imm +:vmv.v.i vd, simm5 is op2631=0x17 & op2525=0x1 & op2024=0x0 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vmv.v.v 31..26=0x17 25=1 24..20=0 vs1 14..12=0x0 vd 6..0=0x57 +# vmv.v.v vd, vs1 # vd[i] = vs1[i] +:vmv.v.v vd, vs1 is op2631=0x17 & op2525=0x1 & op2024=0x0 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vmv.v.x 31..26=0x17 25=1 24..20=0 rs1 14..12=0x4 vd 6..0=0x57 +# vmv.v.x vd, rs1 # vd[i] = rs1 +:vmv.v.x vd, rs1 is op2631=0x17 & op2525=0x1 & op2024=0x0 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +#TODO this is broken +# vmv.x.s 31..26=0x10 25=1 vs2 19..15=0 14..12=0x2 vd 6..0=0x57 +# vmv.x.s rd, vs2 # x[rd] = vs2[0] (rs1=0) +:vmv.x.s rd, vs2 is op2631=0x10 & op2525=0x1 & vs2 & op1519=0x0 & op1214=0x2 & rd & vd & op0006=0x57 unimpl + +# vmv1r.v 31..26=0x27 25=1 vs2 19..15=0 14..12=0x3 vd 6..0=0x57 +# vmv1r.v vd, vs2 +:vmv1r.v vd, vs2 is op2631=0x27 & op2525=0x1 & vs2 & op1519=0x0 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vmv2r.v 31..26=0x27 25=1 vs2 19..15=1 14..12=0x3 vd 6..0=0x57 +# vmv2r.v vd, vs2 +:vmv2r.v vd, vs2 is op2631=0x27 & op2525=0x1 & vs2 & op1519=0x1 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vmv4r.v 31..26=0x27 25=1 vs2 19..15=3 14..12=0x3 vd 6..0=0x57 +# vmv4r.v vd, vs2 +:vmv4r.v vd, vs2 is op2631=0x27 & op2525=0x1 & vs2 & op1519=0x3 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vmv8r.v 31..26=0x27 25=1 vs2 19..15=7 14..12=0x3 vd 6..0=0x57 +# vmv8r.v vd, vs2 +:vmv8r.v vd, vs2 is op2631=0x27 & op2525=0x1 & vs2 & op1519=0x7 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vmxnor.mm 31..26=0x1f vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vmxnor.mm vd, vs2, vs1 # vd[i] = !(vs2.mask[i] ^^ vs1.mask[i]) +:vmxnor.mm vd, vs2, vs1 is op2631=0x1f & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vmxor.mm 31..26=0x1b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vmxor.mm vd, vs2, vs1 # vd[i] = vs2.mask[i] ^^ vs1.mask[i] +:vmxor.mm vd, vs2, vs1 is op2631=0x1b & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +#TODO this is broken +# vnclip.wi 31..26=0x2f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vnclip.wi vd, vs2, simm5, vm # vd[i] = clip(roundoff_signed(vs2[i], uimm5)) +:vnclip.wi vd, vs2, simm5, vm is op2631=0x2f & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vnclip.wv 31..26=0x2f vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vnclip.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_signed(vs2[i], vs1[i])) +:vnclip.wv vd, vs2, vs1, vm is op2631=0x2f & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vnclip.wx 31..26=0x2f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vnclip.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_signed(vs2[i], x[rs1])) +:vnclip.wx vd, vs2, rs1, vm is op2631=0x2f & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +#TODO this is broken +# vnclipu.wi 31..26=0x2e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vnclipu.wi vd, vs2, simm5, vm # vd[i] = clip(roundoff_unsigned(vs2[i], uimm5)) +:vnclipu.wi vd, vs2, simm5, vm is op2631=0x2e & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vnclipu.wv 31..26=0x2e vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vnclipu.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], vs1[i])) +:vnclipu.wv vd, vs2, vs1, vm is op2631=0x2e & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vnclipu.wx 31..26=0x2e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vnclipu.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], x[rs1])) +:vnclipu.wx vd, vs2, rs1, vm is op2631=0x2e & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vnmsac.vv 31..26=0x2f vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i] +:vnmsac.vv vd, vs1, vs2, vm is op2631=0x2f & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vnmsac.vx 31..26=0x2f vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vnmsac.vx vd, rs1, vs2, vm # vd[i] = -(x[rs1] * vs2[i]) + vd[i] +:vnmsac.vx vd, rs1, vs2, vm is op2631=0x2f & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vnmsub.vv 31..26=0x2b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vnmsub.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vd[i]) + vs2[i] +:vnmsub.vv vd, vs1, vs2, vm is op2631=0x2b & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vnmsub.vx 31..26=0x2b vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vnmsub.vx vd, rs1, vs2, vm # vd[i] = -(x[rs1] * vd[i]) + vs2[i] +:vnmsub.vx vd, rs1, vs2, vm is op2631=0x2b & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +#TODO this is broken +# vnsra.wi 31..26=0x2d vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vnsra.wi vd, vs2, simm5, vm # vector-immediate +:vnsra.wi vd, vs2, simm5, vm is op2631=0x2d & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vnsra.wv 31..26=0x2d vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vnsra.wv vd, vs2, vs1, vm # vector-vector +:vnsra.wv vd, vs2, vs1, vm is op2631=0x2d & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vnsra.wx 31..26=0x2d vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vnsra.wx vd, vs2, rs1, vm # vector-scalar +:vnsra.wx vd, vs2, rs1, vm is op2631=0x2d & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +#TODO this is broken +# vnsrl.wi 31..26=0x2c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vnsrl.wi vd, vs2, simm5, vm # vector-immediate +:vnsrl.wi vd, vs2, simm5, vm is op2631=0x2c & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vnsrl.wv 31..26=0x2c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vnsrl.wv vd, vs2, vs1, vm # vector-vector +:vnsrl.wv vd, vs2, vs1, vm is op2631=0x2c & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vnsrl.wx 31..26=0x2c vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vnsrl.wx vd, vs2, rs1, vm # vector-scalar +:vnsrl.wx vd, vs2, rs1, vm is op2631=0x2c & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vor.vi 31..26=0x0a vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vor.vi vd, vs2, simm5, vm # vector-immediate +:vor.vi vd, vs2, simm5, vm is op2631=0xa & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vor.vv 31..26=0x0a vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vor.vv vd, vs2, vs1, vm # Vector-vector +:vor.vv vd, vs2, vs1, vm is op2631=0xa & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vor.vx 31..26=0x0a vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vor.vx vd, vs2, rs1, vm # vector-scalar +:vor.vx vd, vs2, rs1, vm is op2631=0xa & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vpopc.m 31..26=0x10 vm vs2 19..15=0x10 14..12=0x2 rd 6..0=0x57 +# vpopc.m rd, vs2, vm # x[rd] = sum_i ( vs2.mask[i] && v0.mask[i] ) +:vpopc.m rd, vs2, vm is op2631=0x10 & vm & vs2 & op1519=0x10 & op1214=0x2 & rd & op0006=0x57 unimpl + +# vqmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vqmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] +:vqmacc.vv vd, vs1, vs2, vm is op2631=0x3d & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vqmacc.vx 31..26=0x3d vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vqmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] +:vqmacc.vx vd, rs1, vs2, vm is op2631=0x3d & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vqmaccsu.vv 31..26=0x3f vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vqmaccsu.vv vd, vs1, vs2, vm # vd[i] = +(signed(vs1[i]) * unsigned(vs2[i])) + vd[i] +:vqmaccsu.vv vd, vs1, vs2, vm is op2631=0x3f & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vqmaccsu.vx 31..26=0x3f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vqmaccsu.vx vd, rs1, vs2, vm # vd[i] = +(signed(x[rs1]) * unsigned(vs2[i])) + vd[i] +:vqmaccsu.vx vd, rs1, vs2, vm is op2631=0x3f & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vqmaccu.vv 31..26=0x3c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vqmaccu.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] +:vqmaccu.vv vd, vs1, vs2, vm is op2631=0x3c & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vqmaccu.vx 31..26=0x3c vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vqmaccu.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] +:vqmaccu.vx vd, rs1, vs2, vm is op2631=0x3c & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vqmaccus.vx 31..26=0x3e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vqmaccus.vx vd, rs1, vs2, vm # vd[i] = +(unsigned(x[rs1]) * signed(vs2[i])) + vd[i] +:vqmaccus.vx vd, rs1, vs2, vm is op2631=0x3e & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vredand.vs 31..26=0x01 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vredand.vs vd, vs2, vs1, vm # vd[0] = and( vs1[0] , vs2[*] ) +:vredand.vs vd, vs2, vs1, vm is op2631=0x1 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vredmax.vs 31..26=0x07 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vredmax.vs vd, vs2, vs1, vm # vd[0] = max( vs1[0] , vs2[*] ) +:vredmax.vs vd, vs2, vs1, vm is op2631=0x7 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vredmaxu.vs 31..26=0x06 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vredmaxu.vs vd, vs2, vs1, vm # vd[0] = maxu( vs1[0] , vs2[*] ) +:vredmaxu.vs vd, vs2, vs1, vm is op2631=0x6 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vredmin.vs 31..26=0x05 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vredmin.vs vd, vs2, vs1, vm # vd[0] = min( vs1[0] , vs2[*] ) +:vredmin.vs vd, vs2, vs1, vm is op2631=0x5 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vredminu.vs 31..26=0x04 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vredminu.vs vd, vs2, vs1, vm # vd[0] = minu( vs1[0] , vs2[*] ) +:vredminu.vs vd, vs2, vs1, vm is op2631=0x4 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vredor.vs 31..26=0x02 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vredor.vs vd, vs2, vs1, vm # vd[0] = or( vs1[0] , vs2[*] ) +:vredor.vs vd, vs2, vs1, vm is op2631=0x2 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vredsum.vs 31..26=0x00 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vredsum.vs vd, vs2, vs1, vm # vd[0] = sum( vs1[0] , vs2[*] ) +:vredsum.vs vd, vs2, vs1, vm is op2631=0x0 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vredxor.vs 31..26=0x03 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vredxor.vs vd, vs2, vs1, vm # vd[0] = xor( vs1[0] , vs2[*] ) +:vredxor.vs vd, vs2, vs1, vm is op2631=0x3 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vrem.vv 31..26=0x23 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vrem.vv vd, vs2, vs1, vm # Vector-vector +:vrem.vv vd, vs2, vs1, vm is op2631=0x23 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vrem.vx 31..26=0x23 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vrem.vx vd, vs2, rs1, vm # vector-scalar +:vrem.vx vd, vs2, rs1, vm is op2631=0x23 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vremu.vv 31..26=0x22 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vremu.vv vd, vs2, vs1, vm # Vector-vector +:vremu.vv vd, vs2, vs1, vm is op2631=0x22 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vremu.vx 31..26=0x22 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vremu.vx vd, vs2, rs1, vm # vector-scalar +:vremu.vx vd, vs2, rs1, vm is op2631=0x22 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +#TODO this is broken +# vrgather.vi 31..26=0x0c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vrgather.vi vd, vs2, simm5, vm # vd[i] = (uimm >= VLMAX) ? 0 : vs2[uimm] +:vrgather.vi vd, vs2, simm5, vm is op2631=0xc & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vrgather.vv 31..26=0x0c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vrgather.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; +:vrgather.vv vd, vs2, vs1, vm is op2631=0xc & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vrgather.vx 31..26=0x0c vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[x[rs1]] +:vrgather.vx vd, vs2, rs1, vm is op2631=0xc & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vrgatherei16.vv 31..26=0x0e vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vrgatherei16.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; +:vrgatherei16.vv vd, vs2, vs1, vm is op2631=0xe & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vrsub.vi 31..26=0x03 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vrsub.vi vd, vs2, simm5, vm # vd[i] = imm - vs2[i] +:vrsub.vi vd, vs2, simm5, vm is op2631=0x3 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vrsub.vx 31..26=0x03 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vrsub.vx vd, vs2, rs1, vm # vd[i] = rs1 - vs2[i] +:vrsub.vx vd, vs2, rs1, vm is op2631=0x3 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vs1r.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 +# vs1r.v vs3, (rs1) +:vs1r.v vs3, (rs1) is op2931=0x0 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl + +# vs2r.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 +# vs2r.v vs3, (rs1) +:vs2r.v vs3, (rs1) is op2931=0x1 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl + +# vs4r.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 +# vs4r.v vs3, (rs1) +:vs4r.v vs3, (rs1) is op2931=0x3 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl + +# vs8r.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 +# vs8r.v vs3, (rs1) +:vs8r.v vs3, (rs1) is op2931=0x7 & op2828=0x0 & op2627=0x0 & op2525=0x1 & op2024=0x8 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl + +# vsadd.vi 31..26=0x21 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vsadd.vi vd, vs2, simm5, vm # vector-immediate +:vsadd.vi vd, vs2, simm5, vm is op2631=0x21 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vsadd.vv 31..26=0x21 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vsadd.vv vd, vs2, vs1, vm # Vector-vector +:vsadd.vv vd, vs2, vs1, vm is op2631=0x21 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vsadd.vx 31..26=0x21 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vsadd.vx vd, vs2, rs1, vm # vector-scalar +:vsadd.vx vd, vs2, rs1, vm is op2631=0x21 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vsaddu.vi 31..26=0x20 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vsaddu.vi vd, vs2, simm5, vm # vector-immediate +:vsaddu.vi vd, vs2, simm5, vm is op2631=0x20 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vsaddu.vv 31..26=0x20 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vsaddu.vv vd, vs2, vs1, vm # Vector-vector +:vsaddu.vv vd, vs2, vs1, vm is op2631=0x20 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vsaddu.vx 31..26=0x20 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vsaddu.vx vd, vs2, rs1, vm # vector-scalar +:vsaddu.vx vd, vs2, rs1, vm is op2631=0x20 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vsbc.vvm 31..26=0x12 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vsbc.vvm vd, vs2, vs1, v0 # Vector-vector +:vsbc.vvm vd, vs2, vs1, v0 is op2631=0x12 & op2525=0x0 & vs2 & vs1 & op1214=0x0 & v0 & vd & op0006=0x57 unimpl + +# vsbc.vxm 31..26=0x12 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vsbc.vxm vd, vs2, rs1, v0 # Vector-scalar +:vsbc.vxm vd, vs2, rs1, v0 is op2631=0x12 & op2525=0x0 & vs2 & rs1 & op1214=0x4 & v0 & vd & op0006=0x57 unimpl + +# vse1024.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27 +# vse1024.v vs3, (rs1), vm # 1024-bit unit-stride store +:vse1024.v vs3, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl + +# vse128.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27 +# vse128.v vs3, (rs1), vm # 128-bit unit-stride store +:vse128.v vs3, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl + +# vse16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27 +# vse16.v vs3, (rs1), vm # 16-bit unit-stride store +:vse16.v vs3, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl + +# vse256.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27 +# vse256.v vs3, (rs1), vm # 256-bit unit-stride store +:vse256.v vs3, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl + +# vse32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27 +# vse32.v vs3, (rs1), vm # 32-bit unit-stride store +:vse32.v vs3, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl + +# vse512.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27 +# vse512.v vs3, (rs1), vm # 512-bit unit-stride store +:vse512.v vs3, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl + +# vse64.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27 +# vse64.v vs3, (rs1), vm # 64-bit unit-stride store +:vse64.v vs3, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl + +# vse8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27 +# vse8.v vs3, (rs1), vm # 8-bit unit-stride store +:vse8.v vs3, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl + +# vsetvl 31=1 30..25=0x0 rs2 rs1 14..12=0x7 rd 6..0=0x57 +# vsetvl rd, rs1, rs2 # rd = new vl, rs1 = AVL, rs2 = new vtype value +:vsetvl rd, rs1, rs2 is op3131=0x1 & op2530=0x0 & rs2 & rs1 & op1214=0x7 & rd & op0006=0x57 unimpl + +#TODO huh +# vsetvli 31=0 vtypei rs1 14..12=0x7 rd 6..0=0x57 +# vsetvli rd, rs1, vtypei # rd = new vl, rs1 = AVL, vtypei = new vtype setting +:vsetvli rd, rs1, vtypei is op3131=0x0 & vtypei & rs1 & op1214=0x7 & rd & op0006=0x57 unimpl + +# vsext.vf2 31..26=0x12 vm vs2 19..15=7 14..12=0x2 vd 6..0=0x57 +# vsext.vf2 vd, vs2, vm # Sign-extend SEW/2 source to SEW destination +:vsext.vf2 vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x7 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vsext.vf4 31..26=0x12 vm vs2 19..15=5 14..12=0x2 vd 6..0=0x57 +# vsext.vf4 vd, vs2, vm # Sign-extend SEW/4 source to SEW destination +:vsext.vf4 vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x5 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vsext.vf8 31..26=0x12 vm vs2 19..15=3 14..12=0x2 vd 6..0=0x57 +# vsext.vf8 vd, vs2, vm # Sign-extend SEW/8 source to SEW destination +:vsext.vf8 vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x3 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vslide1down.vx 31..26=0x0f vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] +:vslide1down.vx vd, vs2, rs1, vm is op2631=0xf & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vslide1up.vx 31..26=0x0e vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] +:vslide1up.vx vd, vs2, rs1, vm is op2631=0xe & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +#TODO this is broken +# vslidedown.vi 31..26=0x0f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vslidedown.vi vd, vs2, simm5[4:0], vm # vd[i] = vs2[i+uimm] +:vslidedown.vi vd, vs2, simm5[4:0], vm is op2631=0xf & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vslidedown.vx 31..26=0x0f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1] +:vslidedown.vx vd, vs2, rs1, vm is op2631=0xf & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +#TODO this is broken +# vslideup.vi 31..26=0x0e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vslideup.vi vd, vs2, simm5[4:0], vm # vd[i+uimm] = vs2[i] +:vslideup.vi vd, vs2, simm5[4:0], vm is op2631=0xe & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vslideup.vx 31..26=0x0e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vslideup.vx vd, vs2, rs1, vm # vd[i+rs1] = vs2[i] +:vslideup.vx vd, vs2, rs1, vm is op2631=0xe & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +#TODO this is broken +# vsll.vi 31..26=0x25 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vsll.vi vd, vs2, simm5, vm # vector-immediate +:vsll.vi vd, vs2, simm5, vm is op2631=0x25 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vsll.vv 31..26=0x25 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vsll.vv vd, vs2, vs1, vm # Vector-vector +:vsll.vv vd, vs2, vs1, vm is op2631=0x25 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vsll.vx 31..26=0x25 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vsll.vx vd, vs2, rs1, vm # vector-scalar +:vsll.vx vd, vs2, rs1, vm is op2631=0x25 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vsmul.vv 31..26=0x27 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vsmul.vv vd, vs2, vs1, vm # vd[i] = clip(roundoff_signed(vs2[i]*vs1[i], SEW-1)) +:vsmul.vv vd, vs2, vs1, vm is op2631=0x27 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vsmul.vx 31..26=0x27 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vsmul.vx vd, vs2, rs1, vm # vd[i] = clip(roundoff_signed(vs2[i]*x[rs1], SEW-1)) +:vsmul.vx vd, vs2, rs1, vm is op2631=0x27 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +#OTOD this is broken +# vsra.vi 31..26=0x29 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vsra.vi vd, vs2, simm5, vm # vector-immediate +:vsra.vi vd, vs2, simm5, vm is op2631=0x29 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vsra.vv 31..26=0x29 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vsra.vv vd, vs2, vs1, vm # Vector-vector +:vsra.vv vd, vs2, vs1, vm is op2631=0x29 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vsra.vx 31..26=0x29 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vsra.vx vd, vs2, rs1, vm # vector-scalar +:vsra.vx vd, vs2, rs1, vm is op2631=0x29 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +#TODO this is broken +# vsrl.vi 31..26=0x28 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vsrl.vi vd, vs2, simm5, vm # vector-immediate +:vsrl.vi vd, vs2, simm5, vm is op2631=0x28 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vsrl.vv 31..26=0x28 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vsrl.vv vd, vs2, vs1, vm # Vector-vector +:vsrl.vv vd, vs2, vs1, vm is op2631=0x28 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vsrl.vx 31..26=0x28 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vsrl.vx vd, vs2, rs1, vm # vector-scalar +:vsrl.vx vd, vs2, rs1, vm is op2631=0x28 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vsse1024.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27 +# vsse1024.v vs3, (rs1), rs2, vm # 1024-bit strided store +:vsse1024.v vs3, (rs1), rs2, vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl + +# vsse128.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27 +# vsse128.v vs3, (rs1), rs2, vm # 128-bit strided store +:vsse128.v vs3, (rs1), rs2, vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl + +# vsse16.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27 +# vsse16.v vs3, (rs1), rs2, vm # 16-bit strided store +:vsse16.v vs3, (rs1), rs2, vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl + +# vsse256.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27 +# vsse256.v vs3, (rs1), rs2, vm # 256-bit strided store +:vsse256.v vs3, (rs1), rs2, vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl + +# vsse32.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27 +# vsse32.v vs3, (rs1), rs2, vm # 32-bit strided store +:vsse32.v vs3, (rs1), rs2, vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl + +# vsse512.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27 +# vsse512.v vs3, (rs1), rs2, vm # 512-bit strided store +:vsse512.v vs3, (rs1), rs2, vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl + +# vsse64.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27 +# vsse64.v vs3, (rs1), rs2, vm # 64-bit strided store +:vsse64.v vs3, (rs1), rs2, vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl + +# vsse8.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27 +# vsse8.v vs3, (rs1), rs2, vm # 8-bit strided store +:vsse8.v vs3, (rs1), rs2, vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl + +#TODO this is broken +# vssra.vi 31..26=0x2b vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vssra.vi vd, vs2, simm5, vm # vd[i] = roundoff_signed(vs2[i], uimm) +:vssra.vi vd, vs2, simm5, vm is op2631=0x2b & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vssra.vv 31..26=0x2b vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vssra.vv vd, vs2, vs1, vm # vd[i] = roundoff_signed(vs2[i],vs1[i]) +:vssra.vv vd, vs2, vs1, vm is op2631=0x2b & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vssra.vx 31..26=0x2b vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vssra.vx vd, vs2, rs1, vm # vd[i] = roundoff_signed(vs2[i], x[rs1]) +:vssra.vx vd, vs2, rs1, vm is op2631=0x2b & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +#TODO this is broken +# vssrl.vi 31..26=0x2a vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vssrl.vi vd, vs2, simm5, vm # vd[i] = roundoff_unsigned(vs2[i], uimm) +:vssrl.vi vd, vs2, simm5, vm is op2631=0x2a & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vssrl.vv 31..26=0x2a vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vssrl.vv vd, vs2, vs1, vm # vd[i] = roundoff_unsigned(vs2[i], vs1[i]) +:vssrl.vv vd, vs2, vs1, vm is op2631=0x2a & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vssrl.vx 31..26=0x2a vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vssrl.vx vd, vs2, rs1, vm # vd[i] = roundoff_unsigned(vs2[i], x[rs1]) +:vssrl.vx vd, vs2, rs1, vm is op2631=0x2a & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vssub.vv 31..26=0x23 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vssub.vv vd, vs2, vs1, vm # Vector-vector +:vssub.vv vd, vs2, vs1, vm is op2631=0x23 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vssub.vx 31..26=0x23 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vssub.vx vd, vs2, rs1, vm # vector-scalar +:vssub.vx vd, vs2, rs1, vm is op2631=0x23 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vssubu.vv 31..26=0x22 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vssubu.vv vd, vs2, vs1, vm # Vector-vector +:vssubu.vv vd, vs2, vs1, vm is op2631=0x22 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vssubu.vx 31..26=0x22 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vssubu.vx vd, vs2, rs1, vm # vector-scalar +:vssubu.vx vd, vs2, rs1, vm is op2631=0x22 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vsub.vv 31..26=0x02 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vsub.vv vd, vs2, vs1, vm # Vector-vector +:vsub.vv vd, vs2, vs1, vm is op2631=0x2 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vsub.vx 31..26=0x02 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vsub.vx vd, vs2, rs1, vm # vector-scalar +:vsub.vx vd, vs2, rs1, vm is op2631=0x2 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vsuxei1024.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 +# vsuxei1024.v vs3, (rs1), vs2, vm # unordered 1024-bit indexed store of SEW data +:vsuxei1024.v vs3, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl + +# vsuxei128.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 +# vsuxei128.v vs3, (rs1), vs2, vm # unordered 128-bit indexed store of SEW data +:vsuxei128.v vs3, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl + +# vsuxei16.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 +# vsuxei16.v vs3, (rs1), vs2, vm # unordered 16-bit indexed store of SEW data +:vsuxei16.v vs3, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl + +# vsuxei256.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 +# vsuxei256.v vs3, (rs1), vs2, vm # unordered 256-bit indexed store of SEW data +:vsuxei256.v vs3, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl + +# vsuxei32.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 +# vsuxei32.v vs3, (rs1), vs2, vm # unordered 32-bit indexed store of SEW data +:vsuxei32.v vs3, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl + +# vsuxei512.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 +# vsuxei512.v vs3, (rs1), vs2, vm # unordered 512-bit indexed store of SEW data +:vsuxei512.v vs3, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl + +# vsuxei64.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 +# vsuxei64.v vs3, (rs1), vs2, vm # unordered 64-bit indexed store of SEW data +:vsuxei64.v vs3, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl + +# vsuxei8.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 +# vsuxei8.v vs3, (rs1), vs2, vm # unordered 8-bit indexed store of SEW data +:vsuxei8.v vs3, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl + +# vsxei1024.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 +# vsxei1024.v vs3, (rs1), vs2, vm # ordered 1024-bit indexed store of SEW data +:vsxei1024.v vs3, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl + +# vsxei128.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 +# vsxei128.v vs3, (rs1), vs2, vm # ordered 128-bit indexed store of SEW data +:vsxei128.v vs3, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl + +# vsxei16.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 +# vsxei16.v vs3, (rs1), vs2, vm # ordered 16-bit indexed store of SEW data +:vsxei16.v vs3, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl + +# vsxei256.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 +# vsxei256.v vs3, (rs1), vs2, vm # ordered 256-bit indexed store of SEW data +:vsxei256.v vs3, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl + +# vsxei32.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 +# vsxei32.v vs3, (rs1), vs2, vm # ordered 32-bit indexed store of SEW data +:vsxei32.v vs3, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl + +# vsxei512.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 +# vsxei512.v vs3, (rs1), vs2, vm # ordered 512-bit indexed store of SEW data +:vsxei512.v vs3, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl + +# vsxei64.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 +# vsxei64.v vs3, (rs1), vs2, vm # ordered 64-bit indexed store of SEW data +:vsxei64.v vs3, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl + +# vsxei8.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 +# vsxei8.v vs3, (rs1), vs2, vm # ordered 8-bit indexed store of SEW data +:vsxei8.v vs3, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl + +# vwadd.vv 31..26=0x31 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vwadd.vv vd, vs2, vs1, vm # vector-vector +:vwadd.vv vd, vs2, vs1, vm is op2631=0x31 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vwadd.vx 31..26=0x31 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vwadd.vx vd, vs2, rs1, vm # vector-scalar +:vwadd.vx vd, vs2, rs1, vm is op2631=0x31 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vwadd.wv 31..26=0x35 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vwadd.wv vd, vs2, vs1, vm # vector-vector +:vwadd.wv vd, vs2, vs1, vm is op2631=0x35 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vwadd.wx 31..26=0x35 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vwadd.wx vd, vs2, rs1, vm # vector-scalar +:vwadd.wx vd, vs2, rs1, vm is op2631=0x35 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vwaddu.vv 31..26=0x30 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vwaddu.vv vd, vs2, vs1, vm # vector-vector +:vwaddu.vv vd, vs2, vs1, vm is op2631=0x30 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vwaddu.vx 31..26=0x30 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vwaddu.vx vd, vs2, rs1, vm # vector-scalar +:vwaddu.vx vd, vs2, rs1, vm is op2631=0x30 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vwaddu.wv 31..26=0x34 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vwaddu.wv vd, vs2, vs1, vm # vector-vector +:vwaddu.wv vd, vs2, vs1, vm is op2631=0x34 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vwaddu.wx 31..26=0x34 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vwaddu.wx vd, vs2, rs1, vm # vector-scalar +:vwaddu.wx vd, vs2, rs1, vm is op2631=0x34 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vwmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vwmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] +:vwmacc.vv vd, vs1, vs2, vm is op2631=0x3d & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vwmacc.vx 31..26=0x3d vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vwmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] +:vwmacc.vx vd, rs1, vs2, vm is op2631=0x3d & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vwmaccsu.vv 31..26=0x3f vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vwmaccsu.vv vd, vs1, vs2, vm # vd[i] = +(signed(vs1[i]) * unsigned(vs2[i])) + vd[i] +:vwmaccsu.vv vd, vs1, vs2, vm is op2631=0x3f & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vwmaccsu.vx 31..26=0x3f vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vwmaccsu.vx vd, rs1, vs2, vm # vd[i] = +(signed(x[rs1]) * unsigned(vs2[i])) + vd[i] +:vwmaccsu.vx vd, rs1, vs2, vm is op2631=0x3f & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vwmaccu.vv 31..26=0x3c vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vwmaccu.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] +:vwmaccu.vv vd, vs1, vs2, vm is op2631=0x3c & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vwmaccu.vx 31..26=0x3c vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vwmaccu.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] +:vwmaccu.vx vd, rs1, vs2, vm is op2631=0x3c & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vwmaccus.vx 31..26=0x3e vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vwmaccus.vx vd, rs1, vs2, vm # vd[i] = +(unsigned(x[rs1]) * signed(vs2[i])) + vd[i] +:vwmaccus.vx vd, rs1, vs2, vm is op2631=0x3e & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vwmul.vv 31..26=0x3b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vwmul.vv vd, vs2, vs1, vm# vector-vector +:vwmul.vv vd, vs2, vs1, vm is op2631=0x3b & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vwmul.vx 31..26=0x3b vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vwmul.vx vd, vs2, rs1, vm # vector-scalar +:vwmul.vx vd, vs2, rs1, vm is op2631=0x3b & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vwmulsu.vv 31..26=0x3a vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vwmulsu.vv vd, vs2, vs1, vm # vector-vector +:vwmulsu.vv vd, vs2, vs1, vm is op2631=0x3a & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vwmulsu.vx 31..26=0x3a vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vwmulsu.vx vd, vs2, rs1, vm # vector-scalar +:vwmulsu.vx vd, vs2, rs1, vm is op2631=0x3a & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vwmulu.vv 31..26=0x38 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vwmulu.vv vd, vs2, vs1, vm # vector-vector +:vwmulu.vv vd, vs2, vs1, vm is op2631=0x38 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vwmulu.vx 31..26=0x38 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vwmulu.vx vd, vs2, rs1, vm # vector-scalar +:vwmulu.vx vd, vs2, rs1, vm is op2631=0x38 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vwredsum.vs vd, vs2, vs1, vm # 2*SEW = 2*SEW + sum(sign-extend(SEW)) +:vwredsum.vs vd, vs2, vs1, vm is op2631=0x31 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vwredsumu.vs 31..26=0x30 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vwredsumu.vs vd, vs2, vs1, vm # 2*SEW = 2*SEW + sum(zero-extend(SEW)) +:vwredsumu.vs vd, vs2, vs1, vm is op2631=0x30 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vwsub.vv 31..26=0x33 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vwsub.vv vd, vs2, vs1, vm # vector-vector +:vwsub.vv vd, vs2, vs1, vm is op2631=0x33 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vwsub.vx 31..26=0x33 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vwsub.vx vd, vs2, rs1, vm # vector-scalar +:vwsub.vx vd, vs2, rs1, vm is op2631=0x33 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vwsub.wv 31..26=0x37 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vwsub.wv vd, vs2, vs1, vm # vector-vector +:vwsub.wv vd, vs2, vs1, vm is op2631=0x37 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vwsub.wx 31..26=0x37 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vwsub.wx vd, vs2, rs1, vm # vector-scalar +:vwsub.wx vd, vs2, rs1, vm is op2631=0x37 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vwsubu.vv 31..26=0x32 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vwsubu.vv vd, vs2, vs1, vm # vector-vector +:vwsubu.vv vd, vs2, vs1, vm is op2631=0x32 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vwsubu.vx 31..26=0x32 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vwsubu.vx vd, vs2, rs1, vm # vector-scalar +:vwsubu.vx vd, vs2, rs1, vm is op2631=0x32 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vwsubu.wv 31..26=0x36 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +# vwsubu.wv vd, vs2, vs1, vm # vector-vector +:vwsubu.wv vd, vs2, vs1, vm is op2631=0x36 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vwsubu.wx 31..26=0x36 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +# vwsubu.wx vd, vs2, rs1, vm # vector-scalar +:vwsubu.wx vd, vs2, rs1, vm is op2631=0x36 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl + +# vxor.vi 31..26=0x0b vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +# vxor.vi vd, vs2, simm5, vm # vector-immediate +:vxor.vi vd, vs2, simm5, vm is op2631=0xb & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl + +# vxor.vv 31..26=0x0b vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +# vxor.vv vd, vs2, vs1, vm # Vector-vector +:vxor.vv vd, vs2, vs1, vm is op2631=0xb & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl + +# vxor.vx 31..26=0x0b vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +# vxor.vx vd, vs2, rs1, vm # vector-scalar +:vxor.vx vd, vs2, rs1, vm is op2631=0xb & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl + +# vzext.vf2 31..26=0x12 vm vs2 19..15=6 14..12=0x2 vd 6..0=0x57 +# vzext.vf2 vd, vs2, vm # Zero-extend SEW/2 source to SEW destination +:vzext.vf2 vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x6 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vzext.vf4 31..26=0x12 vm vs2 19..15=4 14..12=0x2 vd 6..0=0x57 +# vzext.vf4 vd, vs2, vm # Zero-extend SEW/4 source to SEW destination +:vzext.vf4 vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x4 & op1214=0x2 & vd & op0006=0x57 unimpl + +# vzext.vf8 31..26=0x12 vm vs2 19..15=2 14..12=0x2 vd 6..0=0x57 +# vzext.vf8 vd, vs2, vm # Zero-extend SEW/8 source to SEW destination +:vzext.vf8 vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x2 & op1214=0x2 & vd & op0006=0x57 unimpl + diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.table.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.table.sinc new file mode 100644 index 0000000..749ac3e --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.table.sinc @@ -0,0 +1,384 @@ + +#TODO these names are madeup. do real ones exist? +#TODO go through and use these instead of numbers +@define HFLEN 2 +@define SFLEN 4 +@define DFLEN 8 +@define QFLEN 16 + +@define HXLEN 2 +@define WXLEN 4 +@define DXLEN 8 +@define QXLEN 16 + + +define pcodeop unimp; +define pcodeop trap; +define pcodeop ebreak; +define pcodeop ecall; +define pcodeop fence; +define pcodeop fence.i; + + +# possible tokens: r0711 r1519 r2024 r2731 cr0206 cr0711 cd0711 +rs1: r1519 is r1519 { export r1519; } +rs1: zero is zero & op1519=0 { export 0:$(XLEN); } + +rs2: r2024 is r2024 { export r2024; } +rs2: zero is zero & op2024=0 { export 0:$(XLEN); } + +rs3: r2731 is r2731 { export r2731; } +rs3: zero is zero & op2731=0 { export 0:$(XLEN); } + +rd: r0711 is r0711 { export r0711; } +rd: zero is r0711 & zero & op0711=0 { local tempZero:$(XLEN) = 0; export tempZero; } +rdDst: r0711 is r0711 { export r0711; } + + +rs1W: r1519 is r1519 { local tmp:$(WXLEN) = r1519:$(WXLEN); export tmp; } +rs1W: zero is r1519 & zero & op1519=0 { export 0:$(WXLEN); } + +rs2W: r2024 is r2024 { local tmp:$(WXLEN) = r2024:$(WXLEN); export tmp; } +rs2W: zero is r2024 & zero & op2024=0 { export 0:$(WXLEN); } + +#TODO dest may be bad, might need an assign macro +rdW: r0711 is r0711 { local tmp:$(WXLEN) = r0711:$(WXLEN); export tmp; } +rdW: zero is r0711 & zero & op0711=0 { export 0:$(WXLEN); } + + + +#TODO does this need to be in an if/endif +@if ADDRSIZE == "64" +rs1L: r1519 is r1519 { local tmp:8 = r1519:8; export tmp; } +rs1L: zero is r1519 & zero & op1519=0 { export 0:8; } + +rs2L: r2024 is r2024 { local tmp:8 = r2024:8; export tmp; } +rs2L: zero is r2024 & zero & op2024=0 { export 0:8; } + +#TODO dest may be bad, might need an assign macro +rdL: r0711 is r0711 { export r0711; } +rdL: zero is r0711 & zero & op0711=0 { export 0:8; } +@endif + + +#TODO eh not sure if this is usable +# would only make sense to use this if the float operation +# tables for frd,frs1,frs2 could be different sizes or +# if the cast could use this export, but they have to export +# the same size and you cant 'local tmp:fmt' +# # 32-bit single-precision $(SFLEN) +# fmt: ".s" is op2526=0 { export $(SFLEN):1; } +# # 64-bit double-precision $(DFLEN) +# fmt: ".d" is op2526=1 { export $(DFLEN):1; } +# # 16-bit half-precision $(HFLEN) +# fmt: ".h" is op2526=2 { export $(HFLEN):1; } +# # 128-bit quad-precision $(QFLEN) +# fmt: ".q" is op2526=3 { export $(QFLEN):1; } + + +frd: fr0711 is fr0711 { export fr0711; } +frs1: fr1519 is fr1519 { export fr1519; } +frs2: fr2024 is fr2024 { export fr2024; } +frs3: fr2731 is fr2731 { export fr2731; } + +#TODO dest may be bad, might need an assign macro +#frdS: fr0711 is fr0711 { local tmp = fr0711:$(SFLEN); export tmp; } +frs1S: fr1519 is fr1519 { local tmp = fr1519:$(SFLEN); export tmp; } +frs2S: fr2024 is fr2024 { local tmp = fr2024:$(SFLEN); export tmp; } +frs3S: fr2731 is fr2731 { local tmp = fr2731:$(SFLEN); export tmp; } + +@if ((FPSIZE == "64") || (FPSIZE == "128")) +#TODO dest may be bad, might need an assign macro +#frdD: fr0711 is fr0711 { local tmp = fr0711:$(DFLEN); export tmp; } +frs1D: fr1519 is fr1519 { local tmp = fr1519:$(DFLEN); export tmp; } +frs2D: fr2024 is fr2024 { local tmp = fr2024:$(DFLEN); export tmp; } +frs3D: fr2731 is fr2731 { local tmp = fr2731:$(DFLEN); export tmp; } +@endif + +macro fassignS(dest, src) { +@if FPSIZE == "32" + dest = src; +@else + dest = zext(src); +@endif +} + + +macro assignW(dest, src) { +@if ADDRSIZE == "32" + dest = src; +@else + dest = sext(src); +@endif +} + +macro zassignW(dest, src) { +@if ADDRSIZE == "32" + dest = src; +@else + dest = zext(src); +@endif +} + +macro zassignD(dest, src) { +@if ADDRSIZE == "128" + dest = zext(src); +@else + dest = src; +@endif +} + +macro assignD(dest, src) { +@if ADDRSIZE == "128" + dest = sext(src); +@else + dest = src; +@endif +} + + +immI: sop2031 is sop2031 { local tmp:$(XLEN) = sop2031; export tmp; } + +immS: imm is op0711 & sop2531 [ imm = (sop2531 << 5) | op0711; ] { local tmp:$(XLEN) = imm; export tmp; } + +# used for goto +immSB: reloc is op0707 & op0811 & op2530 & sop3131 [ reloc = inst_start + ((sop3131 << 12) | (op2530 << 5) | (op0811 << 1) | (op0707 << 11)); ] { export *[ram]:$(XLEN) reloc; } +#immSB: reloc is op0707 & op0811 & op2530 & sop3131 [ reloc = inst_start + ((sop3131 << 12) | (op2530 << 5) | (op0811 << 1) | (op0707 << 11)); ] { export reloc; } + +immU: op1231 is op1231 & sop1231 { local tmp:$(XLEN) = sop1231 << 12; export tmp; } + +# used for goto +immUJ: reloc is op1219 & op2020 & op2130 & sop3131 [ reloc = inst_start + ((sop3131 << 20) | (op2130 << 1) | (op2020 << 11) | (op1219 << 12)); ] { export *[ram]:$(XLEN) reloc; } + +@if ADDRSIZE == "32" +shamt6: op2024 is op2024 & op2525=0 { local tmp:$(XLEN) = op2024; export tmp; } +@else +shamt5: op2024 is op2024 { local tmp:$(XLEN) = op2024; export tmp; } +shamt6: imm is op2024 & op2525 [ imm = (op2525 << 5) | op2024; ] { local tmp:$(XLEN) = imm; export tmp; } +@endif + +FRM: "rne" is op1214=0 { local tmp:1 = 0; export tmp; } +FRM: "rtz" is op1214=1 { local tmp:1 = 1; export tmp; } +FRM: "rdn" is op1214=2 { local tmp:1 = 2; export tmp; } +FRM: "rup" is op1214=3 { local tmp:1 = 3; export tmp; } +FRM: "rmm" is op1214=4 { local tmp:1 = 4; export tmp; } +# 5 Invalid. Reserved for future use +# 6 Invalid. Reserved for future use +FRM: "dyn" is op1214=7 { local tmp:1 = 7; export tmp; } + +# used to specify additional memory ordering constraints +aqrl: "" is op2526=0 { export 0:$(XLEN); } +aqrl: ".rl" is op2526=1 { export 1:$(XLEN); } +aqrl: ".aq" is op2526=2 { export 2:$(XLEN); } +aqrl: ".aqrl" is op2526=3 { export 3:$(XLEN); } + + + +crs1: cr0711 is cr0711 { export cr0711; } +crs1: zero is cr0711 & zero & cop0711=0 { export 0:$(XLEN); } + +crd: cd0711 is cd0711 { export cd0711; } +crd: zero is zero & cop0711=0 { export 0:$(XLEN); } + +crs2: cr0206 is cr0206 { export cr0206; } +crs2: zero is cr0206 & zero & cop0206=0 { export 0:$(XLEN); } + +cfrs1: cfr0711 is cfr0711 { export cfr0711; } + +cfrd: cfr0711 is cfr0711 { export cfr0711; } + +cfrs2: cfr0206 is cfr0206 { export cfr0206; } + +#ATTN Not doing tables for the RVC registers since there is no +# zero register to worry about + + + +cimmI: imm is scop1212 & cop0206 [ imm = (scop1212 << 5) | (cop0206); ] { local tmp:$(XLEN) = imm; export tmp; } + +# used for goto +cbimm: reloc is scop1212 & cop1011 & cop0506 & cop0304 & cop0202 [ reloc = inst_start + ((scop1212 << 8) | (cop0506 << 6) | (cop0202 << 5) | (cop1011 << 3) | (cop0304 << 1)); ] { export *[ram]:$(XLEN) reloc; } +#cbimm: reloc is scop1212 & cop1011 & cop0506 & cop0304 & cop0202 [ reloc = inst_start + ((scop1212 << 8) | (cop0506 << 6) | (cop0202 << 5) | (cop1011 << 3) | (cop0304 << 1)); ] { export reloc; } + +# used for goto +cjimm: reloc is scop1212 & cop1111 & cop0910 & cop0808 & cop0707 & cop0606 & cop0305 & cop0202 [ reloc = inst_start + ((scop1212 << 11) | (cop1111 << 4) | (cop0910 << 8) | (cop0808 << 10) | (cop0707 << 6) | (cop0606 << 7) | (cop0305 << 1) | (cop0202 << 5)); ] { export *[ram]:$(XLEN) reloc; } + + +nzuimm5: is cop0606=1 | cop0505=1 | cop0404=1 | cop0303 = 1 | cop0202=1 {} +nzuimm6: is cop1212=1 | cop0606=1 | cop0505=1 | cop0404=1 | cop0303 = 1 | cop0202=1 {} + +@if ADDRSIZE == "32" +c6imm: uimm is cop1212=0 & cop0206 & nzuimm5 [ uimm = (cop0206 + 0); ] { local tmp:$(XLEN) = uimm; export tmp; } +@elif ADDRSIZE == "64" +c6imm: uimm is cop1212 & cop0206 & nzuimm6 [ uimm = (cop1212 << 5) | (cop0206); ] { local tmp:$(XLEN) = uimm; export tmp; } +@elif ADDRSIZE == "128" +c6imm: uimm is cop1212 & cop0206 [ uimm = (cop1212 << 5) | (cop0206); ] { local tmp:$(XLEN) = uimm + (64 * (uimm == 0)); export tmp; } +@endif + +cbigimm: uimm is cop1212 & scop1212 & cop0206 & nzuimm6 [ uimm = (cop1212 << 5) | (cop0206); ] { local tmp:$(XLEN) = (scop1212 << 17) | (cop0206 << 12); export tmp; } + +nzcaddi4: is cop1212=1 | cop1111=1 | cop1010=1 | cop0909=1 | cop0808=1 | cop0707=1 | cop0606=1 | cop0505=1 {} + +caddi4spnimm: uimm is nzcaddi4 & cop1112 & cop0710 & cop0606 & cop0505 [ uimm = (cop0710 << 6) | (cop1112 << 4) | (cop0505 << 3) | (cop0606 << 2); ] { local tmp:$(XLEN) = uimm; export tmp; } + +caddi16spimm: imm is scop1212 & cop0606 & cop0505 & cop0304 & cop0202 & nzuimm6 [ imm = (scop1212 << 9) | (cop0304 << 7) | (cop0505 << 6) | (cop0202 << 5) | (cop0606 << 4); ] { local tmp:$(XLEN) = imm; export tmp; } + + +clwimm: uimm is cop1012 & cop0606 & cop0505 [ uimm = (cop1012 << 3) | (cop0606 << 2) | (cop0505 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; } + +clwspimm: uimm is cop1212 & cop0406 & cop0203 [ uimm = (cop1212 << 5) | (cop0406 << 2) | (cop0203 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; } + +cswspimm: uimm is cop0708 & cop0912 [ uimm = (cop0708 << 6) | (cop0912 << 2); ] { local tmp:$(XLEN) = uimm; export tmp; } + +cldimm: uimm is cop1012 & cop0506 [ uimm = (cop1012 << 3) | (cop0506 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; } + +cldspimm: uimm is cop1212 & cop0506 & cop0204 [ uimm = (cop1212 << 5) | (cop0506 << 3) | (cop0204 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; } + +csdspimm: uimm is cop0709 & cop1012 [ uimm = (cop0709 << 6) | (cop1012 << 3); ] { local tmp:$(XLEN) = uimm; export tmp; } + +@if ADDRSIZE == "128" +clqimm: uimm is cop1112 & cop1010 & cop0506 [ uimm = (cop1112 << 4) | (cop1010 << 8) | (cop0506 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; } + +clqspimm: uimm is cop1212 & cop0606 & cop0205 [ uimm = (cop1212 << 5) | (cop0606 << 4) | (cop0205 << 6); ] { local tmp:$(XLEN) = uimm; export tmp; } + +csqspimm: uimm is cop0710 & cop1112 [ uimm = (cop0710 << 6) | (cop1112 << 4); ] { local tmp:$(XLEN) = uimm; export tmp; } +@endif + + + + + +# SEE riscv-privileged.pdf Section 'CSR Listing' for description +# This implementation aligns with the table breakdown + +# csr[11:10] - read/write (00, 01, 10) or read-only (11) +# csr[9:8] - lowest privilege that can access the CSR + +# 0x000-0x0ff +with csr: op3031=0 & op2829=0 { + : csr_0 is csr_0 { export csr_0; } # user, standard read/write +} + +# 0x100-0x1ff +with csr: op3031=0 & op2829=1 { + : csr_1 is csr_1 { export csr_1; } # supervisor, standard read/write +} + +# 0x200-0x2ff +with csr: op3031=0 & op2829=2 { + : csr_2 is csr_2 { export csr_2; } # hypervisor, standard read/write +} + +# 0x300-0x3ff +with csr: op3031=0 & op2829=3 { + : csr_3 is csr_3 { export csr_3; } # machine, standard read/write +} + +# 0x400-0x4ff +with csr: op3031=1 & op2829=0 { + : csr_4 is csr_4 { export csr_4; } # user, standard read/write +} + +# 0x500-0x5ff +with csr: op3031=1 & op2829=1 { + : csr_50 is csr_50 & op2727=0 { export csr_50; } # supervisor, standard read/write + : csr_58 is csr_58 & op2627=2 { export csr_58; } # supervisor, standard read/write + : csr_5C is csr_5C & op2627=3 { export csr_5C; } # supervisor, custom read/write +} + +# 0x600-0x6ff +with csr: op3031=1 & op2829=2 { + : csr_60 is csr_60 & op2727=0 { export csr_60; } # hypervisor, standard read/write + : csr_68 is csr_68 & op2627=2 { export csr_68; } # hypervisor, standard read/write + : csr_6C is csr_6C & op2627=3 { export csr_6C; } # hypervisor, custom read/write +} + +# 0x700-0x7ff +with csr: op3031=1 & op2829=3 { + : csr_70 is csr_70 & op2727=0 { export csr_70; } # machine, standard read/write + : csr_78 is csr_78 & op2527=4 { export csr_78; } # machine, standard read/write + : csr_7A is csr_7A & op2427=0xa { export csr_7A; } # machine, standard read/write debug + : csr_7B is csr_7B & op2427=0xb { export csr_7B; } # machine, debug-mode-only + : csr_7C is csr_7C & op2627=3 { export csr_7C; } # machine, custom read/write +} + +# 0x800-0x8ff +with csr: op3031=2 & op2829=0 { + : csr_8 is csr_8 { export csr_8; } # user, custom read/write +} + +# 0x900-0x9ff +with csr: op3031=2 & op2829=1 { + : csr_90 is csr_90 & op2727=0 { export csr_90; } # supervisor, standard read/write + : csr_98 is csr_98 & op2627=2 { export csr_98; } # supervisor, standard read/write + : csr_9C is csr_9C & op2627=3 { export csr_9C; } # supervisor, custom read/write +} + +# 0xa00-0xaff +with csr: op3031=2 & op2829=2 { + : csr_A0 is csr_A0 & op2727=0 { export csr_A0; } # hypervisor, standard read/write + : csr_A8 is csr_A8 & op2627=2 { export csr_A8; } # hypervisor, standard read/write + : csr_AC is csr_AC & op2627=3 { export csr_AC; } # hypervisor, custom read/write +} + +# 0xb00-0xbff +with csr: op3031=2 & op2829=3 { + : csr_B0 is csr_B0 & op2727=0 { export csr_B0; } # machine, standard read/write + : csr_B8 is csr_B8 & op2627=2 { export csr_B8; } # machine, standard read/write + : csr_BC is csr_BC & op2627=3 { export csr_BC; } # machine, custom read/write +} + +# 0xc00-0xcff +with csr: op3031=3 & op2829=0 { + : csr_C0 is csr_C0 & op2727=0 { export csr_C0; } # user, standard read-only + : csr_C8 is csr_C8 & op2627=2 { export csr_C8; } # user, standard read-only + : csr_CC is csr_CC & op2627=3 { export csr_CC; } # user, custom read-only +} + +# 0xd00-0xdff +with csr: op3031=3 & op2829=1 { + : csr_D0 is csr_D0 & op2727=0 { export csr_D0; } # supervisor, standard read-only + : csr_D8 is csr_D8 & op2627=2 { export csr_D8; } # supervisor, standard read-only + : csr_DC is csr_DC & op2627=3 { export csr_DC; } # supervisor, custom read-only +} + +# 0xe00-0xeff +with csr: op3031=3 & op2829=2 { + : csr_E0 is csr_E0 & op2727=0 { export csr_E0; } # hypervisor, standard read-only + : csr_E8 is csr_E8 & op2627=2 { export csr_E8; } # hypervisor, standard read-only + : csr_EC is csr_EC & op2627=3 { export csr_EC; } # hypervisor, custom read-only +} + +# 0xf00-0xfff +with csr: op3031=3 & op2829=3 { + : csr_F0 is csr_F0 & op2727=0 { export csr_F0; } # machine, standard read-only + : csr_F8 is csr_F8 & op2627=2 { export csr_F8; } # machine, standard read-only + : csr_FC is csr_FC & op2627=3 { export csr_FC; } # machine, custom read-only +} + + + +vm: op2525 is op2525 { local tmp:1 = op2525; export tmp; } + +vs1: v1519 is v1519 { export v1519; } +vs2: v2024 is v2024 { export v2024; } +vs3: v0711 is v0711 { export v0711; } +vd: v0711 is v0711 { export v0711; } + +simm5: sop1519 is sop1519 { local tmp:$(XLEN) = sop1519; export tmp; } +# zimm: op1519 is op1519 { local tmp:$(XLEN) = op1519; export tmp; } + +nf: op2931 is op2931 { local tmp:$(XLEN) = op2931; export tmp; } + +vtypei: op2030 is op2030 { local tmp:$(XLEN) = op2030; export tmp; } + + +bs: op3031 is op3031 { local tmp:$(XLEN) = op3031; export tmp; } +rcon: op2023 is op2023 { local tmp:$(XLEN) = op2023; export tmp; } + +# imm=0 for baseline operation, nonzero values are reserved +shamtw: 0 is op2024=0 { local tmp:$(XLEN) = 0; export tmp; } + +imm3u: op2022 is op2022 { local tmp:$(XLEN) = op2022; export tmp; } +imm4u: op2023 is op2023 { local tmp:$(XLEN) = op2023; export tmp; } +imm5u: op2024 is op2024 { local tmp:$(XLEN) = op2024; export tmp; } diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.zi.sinc b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.zi.sinc new file mode 100644 index 0000000..54ff05b --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv.zi.sinc @@ -0,0 +1,7 @@ +# RV32/RV64 Zifencei Standard Extension + +# fence.i 0000100f ffffffff SIMPLE (0, 0) +:fence.i is op0001=0x3 & op0204=0x3 & op0506=0x0 & funct3=0x1 & fm=0x0 & op0711=0x0 & op1527=0x0 +{ + fence.i(); +} diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv32-fp.cspec b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv32-fp.cspec new file mode 100644 index 0000000..d2dc465 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv32-fp.cspec @@ -0,0 +1,132 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv32.cspec b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv32.cspec new file mode 100644 index 0000000..4a08e65 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv32.cspec @@ -0,0 +1,88 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv32.dwarf b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv32.dwarf new file mode 100644 index 0000000..f136b11 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv32.dwarf @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv64-fp.cspec b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv64-fp.cspec new file mode 100644 index 0000000..329cb03 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv64-fp.cspec @@ -0,0 +1,132 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv64.cspec b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv64.cspec new file mode 100644 index 0000000..1fe4fe3 --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv64.cspec @@ -0,0 +1,88 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv64.dwarf b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv64.dwarf new file mode 100644 index 0000000..ee3e8fa --- /dev/null +++ b/python/icicle/Ghidra/Processors/RISCV/data/languages/riscv64.dwarf @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/python/icicle/Ghidra/Processors/Sparc/data/languages/Sparc.opinion b/python/icicle/Ghidra/Processors/Sparc/data/languages/Sparc.opinion new file mode 100644 index 0000000..f970212 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Sparc/data/languages/Sparc.opinion @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Sparc/data/languages/SparcV9.ldefs b/python/icicle/Ghidra/Processors/Sparc/data/languages/SparcV9.ldefs new file mode 100644 index 0000000..9121216 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Sparc/data/languages/SparcV9.ldefs @@ -0,0 +1,32 @@ + + + + + Sparc V9 32-bit + + + + + + Sparc V9 64-bit + + + + + diff --git a/python/icicle/Ghidra/Processors/Sparc/data/languages/SparcV9.pspec b/python/icicle/Ghidra/Processors/Sparc/data/languages/SparcV9.pspec new file mode 100644 index 0000000..862d7ad --- /dev/null +++ b/python/icicle/Ghidra/Processors/Sparc/data/languages/SparcV9.pspec @@ -0,0 +1,21 @@ + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Sparc/data/languages/SparcV9.sinc b/python/icicle/Ghidra/Processors/Sparc/data/languages/SparcV9.sinc new file mode 100644 index 0000000..b78bff5 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Sparc/data/languages/SparcV9.sinc @@ -0,0 +1,1401 @@ +# SLA specification file for SPARC/64 + +define endian=big; + +define alignment=4; + +define space ram type=ram_space size=$(SIZE) default; +define space register type=register_space size=4; + +define register offset=0 size=$(SIZE) [ + g0 g1 g2 g3 g4 g5 g6 g7 + o0 o1 o2 o3 o4 o5 sp o7 + l0 l1 l2 l3 l4 l5 l6 l7 + i0 i1 i2 i3 i4 i5 fp i7 +]; + +# these are save locations for implementing register windows +# +define register offset=0x500 size=$(SIZE) [ + s_l0 s_l1 s_l2 s_l3 s_l4 s_l5 s_l6 s_l7 + s_i0 s_i1 s_i2 s_i3 s_i4 s_i5 s_fp s_i7 +]; + +define register offset=0x1000 size=$(SIZE) [ PC nPC _ TICK Y CCR _ PCR PIC GSR SOFTINT_SET SOFTINT_CLR SOFTINT TICK_CMPR STICK STICK_CMPR ]; + +define register offset=0x1100 size=$(SIZE) [ + asr7 asr8 asr9 asr10 asr11 asr12 asr13 asr14 asr15 + asr16 asr17 asr18 asr19 asr20 asr21 asr22 asr23 + asr24 asr25 asr26 asr27 asr28 asr29 asr30 asr31 +]; + +define register offset=0x3000 size=1 [ x_nf x_zf x_vf x_cf i_nf i_zf i_vf i_cf ]; + +define register offset=0x4000 size=1 [ ASI ]; +define register offset=0x4008 size=1 [ FPRS ]; + +define register offset=0x5000 size=$(SIZE) [ fsr ]; +#fcc0 is bits 10 and 11 of fsr +#fcc1 is bits 32 and 33 of fsr (64 bit only) +#fcc2 is bits 34 and 35 of fsr (64 bit only) +#fcc3 is bits 36 and 37 of fsr (64 bit only) +#model these as separate 1-byte varnodes +define register offset=0x5008 size=1 [ fcc0 fcc1 fcc2 fcc3 ]; +define register offset=0x5010 size=1 [ didrestore ]; +define register offset=0x5020 size=1 [ DECOMPILE_MODE ]; # Fake register + + +define register offset=0x6000 size=$(SIZE) [ + TPC1 TPC2 TPC3 TPC4 + TNPC1 TNPC2 TNPC3 TNPC4 + TSTATE1 TSTATE2 TSTATE3 TSTATE4 + TT1 TT2 TT3 TT4 + TCK TBA PSTATE TL + PIL CWP CANSAVE CANRESTORE CLEANWIN + OTHERWIN WSTATE FQ VER GL +]; + +define register offset=0x7000 size=$(SIZE) [ + HPSTATE1 HPSTATE2 HPSTATE3 HPSTATE4 + HTSTATE1 HTSTATE2 HTSTATE3 HTSTATE4 + RESV2_1 RESV2_2 RESV2_3 RESV2_4 + HINTP1 HINTP2 HINTP3 HINTP4 + RESV4_1 RESV4_2 RESV4_3 RESV4_4 + HTBA1 HTBA2 HTBA3 HTBA4 + HVER1 HVER2 HVER3 HVER4 +# TODO: actually RESV 6 - 29 registers... + RESV30_1 RESV30_2 RESV30_3 RESV30_4 + HSTICK_CMPR1 HSTICK_CMPR2 HSTICK_CMPR3 HSTICK_CMPR4 +]; + +# A window is 24 registers (96 or 192 bytes), most processors have 7 or 8. (g0->g7,o0->o7,l0->o7,i0->i7) +# When the window is overflowed the data must be purged to some backup memory, via user +# supplied function attached to a signal handler. +# When the window is underflowed the data must be read from some backup memory, via user +# supplied function attached to a signal handler. + +# There are 2 basic strategies we figured for this. +# One, create a bank of register space and read and write to it in a way that simulates +# how the sparc would really work, but the symbolic names become indexes. +# Two, save and restore logic does all the work. + +# window index is ((CWP+1)%NWINDOWS) +# CWP is an index from 0 to N of the windows. +# Size of CWP is implementation dependent (must be > 5 bits). + +# inputs i0 i1 i2 i3 i4 i5 fp i7 +# locals l0 l1 l2 l3 l4 l5 l6 l7 +# output o0 o1 o2 o3 o4 o5 sp o7 + +# fp w016 w036 w126 w236 w316 w336 w416 w436 w516 w536 +# sp w036 w126 w236 w316 w336 w416 w436 w616 w536 +# i7 w017 w037 w127 w217 w237 w327 w417 +# o7 w037 w127 w217 w237 w327 w417 + +define register offset=0x8000 size=$(SIZE) [ + w010 w011 w012 w013 w014 w015 w016 w017 + w020 w021 w022 w023 w024 w025 w026 w027 + w030 w031 w032 w033 w034 w035 w036 w037 + w110 w111 w112 w113 w114 w115 w116 w117 + w120 w121 w122 w123 w124 w125 w126 w127 + w130 w131 w132 w133 w134 w135 w136 w137 + w210 w211 w212 w213 w214 w215 w216 w217 + w220 w221 w222 w223 w224 w225 w226 w227 + w230 w231 w232 w233 w234 w235 w236 w237 + w310 w311 w312 w313 w314 w315 w316 w317 + w320 w321 w322 w323 w324 w325 w326 w327 + w330 w331 w332 w333 w334 w335 w336 w337 + w410 w411 w412 w413 w414 w415 w416 w417 + w420 w421 w422 w423 w424 w425 w426 w427 + w430 w431 w432 w433 w434 w435 w436 w437 + w510 w511 w512 w513 w514 w515 w516 w517 + w520 w521 w522 w523 w524 w525 w526 w527 + w530 w531 w532 w533 w534 w535 w536 w537 + w610 w611 w612 w613 w614 w615 w616 w617 + w620 w621 w622 w623 w624 w625 w626 w627 + w630 w631 w632 w633 w634 w635 w636 w637 + w710 w711 w712 w713 w714 w715 w716 w717 + w720 w721 w722 w723 w724 w725 w726 w727 + w730 w731 w732 w733 w734 w735 w736 w737 +]; + +# Floating-point registers +define register offset=0x2000 size=4 [ + fs0 fs1 fs2 fs3 fs4 fs5 fs6 fs7 + fs8 fs9 fs10 fs11 fs12 fs13 fs14 fs15 + fs16 fs17 fs18 fs19 fs20 fs21 fs22 fs23 + fs24 fs25 fs26 fs27 fs28 fs29 fs30 fs31 +]; + +define register offset=0x2000 size=8 [ + fd0 fd2 fd4 fd6 fd8 fd10 fd12 fd14 + fd16 fd18 fd20 fd22 fd24 fd26 fd28 fd30 + fd32 fd34 fd36 fd38 fd40 fd42 fd44 fd46 + fd48 fd50 fd52 fd54 fd56 fd58 fd60 fd62 +]; + +define register offset=0x2000 size=16 [ + fq0 fq4 fq8 fq12 fq16 fq20 fq24 fq28 + fq32 fq36 fq40 fq44 fq48 fq52 fq56 fq60 +]; + + + +define pcodeop segment; +define pcodeop sw_trap; +define pcodeop reset; + +define token instr(32) + op = (30,31) + disp30 = ( 0,29) signed + udisp22 = ( 0,21) + disp22 = ( 0,21) signed + disp19 = ( 0,18) signed + d16lo = ( 0,13) + d16hi = (20,21) signed + op2 = (22,24) + a = (29,29) + fpc = (27,29) + cond = (25,28) + cond4 = (14,17) + rcond2 = (25,27) + cc0 = (20,20) + cc1 = (21,21) + fccn = (20,21) + fccn2 = (25,26) + cc0_3 = (25,25) + cc1_3 = (26,26) + cc0_4 = (11,11) + cc1_4 = (12,12) + fccn_4 = (11,12) + cc2_4 = (18,18) + p = (19,19) + rd = (25,29) + rd_d = (25,29) + rd_asr = (25,29) + rd_zero = (25,29) + fsrd = (25,29) + fdrd = (25,29) + fqrd = (25,29) + prd = (25,29) + op3 = (19,24) + rs1 = (14,18) + rs1_zero = (14,18) + rs_asr = (14,18) + prs1 = (14,18) + fsrs1 = (14,18) + fdrs1 = (14,18) + fqrs1 = (14,18) + i = (13,13) + x = (12,12) + rcond3 = (10,12) + rs2 = ( 0, 4) + rs2_zero = ( 0, 4) + fsrs2 = ( 0, 4) + fdrs2 = ( 0, 4) + fqrs2 = ( 0, 4) + shcnt32 = ( 0, 4) + shcnt64 = ( 0, 5) + simm13 = ( 0,12) signed + simm11 = ( 0,10) signed + simm10 = ( 0, 9) signed + imm_asi = ( 5,12) + cmask = ( 4, 6) + mmask = ( 0, 3) + opf = ( 5,13) + opf5 = ( 5, 9) + opf6 = ( 5,10) + opf_cc = (11,13) + opf_low = ( 5,10) + opf_low_5_9 = ( 5,9) + fcn = (25,29) + swtrap = ( 0, 6) + bit28 = (28,28) + const22 = ( 0,21) + bit13 = (13,13) + bit18 = (18,18) +; + +attach variables [ rd rs1 rs2 ] [ g0 g1 g2 g3 g4 g5 g6 g7 + o0 o1 o2 o3 o4 o5 sp o7 + l0 l1 l2 l3 l4 l5 l6 l7 + i0 i1 i2 i3 i4 i5 fp i7 ]; + +@if SIZE=="4" +# The ldd, ldda, std, and stda insns access a pair of regs +define register offset=0 size=8 [ + g0_1 g2_3 g4_5 g6_7 + o0_1 o2_3 o4_5 sp_7 + l0_1 l2_3 l4_5 l6_7 + i0_1 i2_3 i4_5 fp_7 +]; + +attach variables [ rd_d ] [ + g0_1 _ g2_3 _ g4_5 _ g6_7 _ + o0_1 _ o2_3 _ o4_5 _ sp_7 _ + l0_1 _ l2_3 _ l4_5 _ l6_7 _ + i0_1 _ i2_3 _ i4_5 _ fp_7 _ + ]; + +@endif + +attach variables [ fccn fccn2 fccn_4 ] [ fcc0 fcc1 fcc2 fcc3 ]; + +#attach names [ rd rs1 rs2 ] [ "%g0" "%g1" "%g2" "%g3" "%g4" "%g5" "%g6" "%g7" +# "%o0" "%o1" "%o2" "%o3" "%o4" "%o5" "%sp" "%o7" +# "%l0" "%l1" "%l2" "%l3" "%l4" "%l5" "%l6" "%l7" +# "%i0" "%i1" "%i2" "%i3" "%i4" "%i5" "%fp" "%i7" ]; +# Window register table accessors =================================== +@define NUMREGWINS 8 +@define REGWINSZ 16 +@define LOCALOFF 8 +@define OUTOFF 16 + +# copy oN to iN +# CWP++ +macro save() { + +if (DECOMPILE_MODE) goto ; + # Save inputs + *[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+0)*$(SIZE)) = i0; + *[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+1)*$(SIZE)) = i1; + *[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+2)*$(SIZE)) = i2; + *[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+3)*$(SIZE)) = i3; + *[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+4)*$(SIZE)) = i4; + *[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+5)*$(SIZE)) = i5; + *[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+6)*$(SIZE)) = fp; + *[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+7)*$(SIZE)) = i7; + + # Save local + *[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+0+$(LOCALOFF))*$(SIZE)) = l0; + *[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+1+$(LOCALOFF))*$(SIZE)) = l1; + *[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+2+$(LOCALOFF))*$(SIZE)) = l3; + *[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+3+$(LOCALOFF))*$(SIZE)) = l3; + *[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+4+$(LOCALOFF))*$(SIZE)) = l4; + *[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+5+$(LOCALOFF))*$(SIZE)) = l5; + *[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+6+$(LOCALOFF))*$(SIZE)) = l6; + *[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+7+$(LOCALOFF))*$(SIZE)) = l7; + + + # what was outputs become inputs + i0 = o0; + i1 = o1; + i2 = o2; + i3 = o3; + i4 = o4; + i5 = o5; + fp = sp; + i7 = o7; + + # zero out locals + l0 = 0; + l1 = 0; + l2 = 0; + l3 = 0; + l4 = 0; + l5 = 0; + l6 = 0; + l7 = 0; + + CWP = CWP + 1; +} + +# copy iN ot oN +# CWP-- +macro restore() { + CWP = CWP - 1; + + # inputs once again become outputs + o0 = i0; # API return value + o1 = i1; + o2 = i2; + o3 = i3; + o4 = i4; + o5 = i5; + sp = fp; + o7 = i7; # address of CALLer address + +if (DECOMPILE_MODE) goto ; + # restore original inputs + i0 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+0)*$(SIZE))); + i1 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+1)*$(SIZE))); + i2 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+2)*$(SIZE))); + i3 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+3)*$(SIZE))); + i4 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+4)*$(SIZE))); + i5 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+5)*$(SIZE))); + fp = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+6)*$(SIZE))); + i7 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+7)*$(SIZE))); # address of CALLer address + # restore original locals + l0 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+0+$(LOCALOFF))*$(SIZE))); + l1 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+1+$(LOCALOFF))*$(SIZE))); + l2 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+2+$(LOCALOFF))*$(SIZE))); + l3 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+3+$(LOCALOFF))*$(SIZE))); + l4 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+4+$(LOCALOFF))*$(SIZE))); + l5 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+5+$(LOCALOFF))*$(SIZE))); + l6 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+6+$(LOCALOFF))*$(SIZE))); + l7 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+6+$(LOCALOFF))*$(SIZE))); + + +} + +#Register g0 in Sparc is always 0 + +#There are special cases for source operands RS1 and RS2 which just return the constant 0 when the +#specified register is g0 +RS1: rs1 is rs1 & rs1_zero=0 { export 0:$(SIZE); } +RS1: rs1 is rs1 { export rs1; } + +RS2: rs2 is rs2 & rs2_zero=0 { export 0:$(SIZE); } +RS2: rs2 is rs2 { export rs2; } + +#For the destination operand RD, we export a temporary varnode with value 0. +#This is because writes to g0 are allowed, but they have no visible effect (see the Sparc manual). +#This way the value of g0 won't appear to change when using the pcode emulator. +RD: rd is rd & rd_zero=0 { local tmp:$(SIZE) = 0; export tmp; } +RD: rd is rd { export rd; } + +regorimm: RS2 is i=0 & RS2 { export RS2; } +regorimm: simm13 is i=1 & simm13 { export *[const]:$(SIZE) simm13; } + +regorimm10: RS2 is i=0 & RS2 { export RS2; } +regorimm10: simm10 is i=1 & simm10 { export *[const]:$(SIZE) simm10; } + +regorimm11: RS2 is i=0 & RS2 { export RS2; } +regorimm11: simm11 is i=1 & simm11 { export *[const]:$(SIZE) simm11; } + +reg_or_shcnt: RS2 is i=0 & RS2 & rs2=0 { export 0:1; } +reg_or_shcnt: RS2 is i=0 & x=0 & RS2 { tmp:1=RS2:1; tmp = tmp & 0x1f; export tmp; } +reg_or_shcnt: RS2 is i=0 & x=1 & RS2 { tmp:1=RS2:1; tmp = tmp & 0x3f; export tmp; } + +reg_or_shcnt: shcnt32 is i=1 & x=0 & shcnt32 { export *[const]:1 shcnt32; } +reg_or_shcnt: shcnt64 is i=1 & x=1 & shcnt64 { export *[const]:1 shcnt64; } + +ea: [regorimm] is rs1=0 & regorimm { export regorimm; } # special case g0=zero +ea: [RS1+regorimm] is RS1 & regorimm { local tmp = RS1+regorimm; export tmp; } +ea: [RS1] is RS1 & i=1 & simm13=0x0 { export RS1; } #special case when adding zero + +retea: regorimm is rs1=0 & i=0 & regorimm { local tmp = regorimm; export tmp; } +retea: regorimm is rs1=0 & i=1 & regorimm { export *:$(SIZE) regorimm; } +retea: RS1+regorimm is RS1 & regorimm { local tmp = RS1+regorimm; export tmp; } +retea: RS1 is RS1 & i=1 & simm13=0x0 { local tmp = RS1; export tmp; } #special case when adding zero +retea: is rs1 & rs1_zero=31 & i=1 & simm13=0x8 { local tmp = rs1 + 0x8; export tmp; } # typical return from CALL instruction (suppress display) + +ea_alt: [RS1+RS2] imm_asi is i=0 & RS1 & RS2 & imm_asi { local tmp1:1 = imm_asi; local tmp = RS1+RS2+segment(tmp1); export tmp; } +ea_alt: [RS1+simm13] %ASI is i=1 & RS1 & simm13 & ASI { local tmp = RS1+simm13+segment(ASI); export tmp; } +ea_alt: [RS1] %ASI is i=1 & RS1 & simm13=0x0 & ASI { local tmp = RS1+segment(ASI); export tmp; } #special case when adding zero + +macro addflags(op1,op2) { + x_cf = carry(op1,op2); + x_vf = scarry(op1,op2); + + local tmp1 = op1:4; + local tmp2 = op2:4; + + i_cf = carry(tmp1,tmp2); + i_vf = scarry(tmp1,tmp2); +} + +macro taddflags(op1,op2) { + addflags(op1,op2); + i_vf = i_vf || ((op1 & 0x3) != 0) || ((op2 & 0x3) != 0); +} + +macro addflags32(op1,op2) { + i_cf = carry(op1,op2); + i_vf = scarry(op1,op2); +} + +macro addCarryFlags ( op1, op2 ) { + local op1_low_32:4 = op1:4; + local op2_low_32:4 = op2:4; + local CFcopy_4:4 = zext(i_cf); + local CFcopy:$(SIZE) = zext(i_cf); + local result:$(SIZE) = op1 + op2; + local result_low_32:4 = op1_low_32 + op2_low_32; + i_cf = carry( op1_low_32, op2_low_32) || carry( result_low_32, CFcopy_4 ); + x_cf = carry(op1,op2) || carry(result,CFcopy); + i_vf = scarry( op1_low_32, op2_low_32) ^^ scarry( result_low_32, CFcopy_4 ); + x_vf = scarry(op1, op2) ^^ scarry(result,CFcopy); +} + +macro subCarryFlags ( op1, op2 ) { + local op1_low_32:4 = op1:4; + local op2_low_32:4 = op2:4; + local CFcopy_4:4 = zext(i_cf); + local CFcopy:$(SIZE) = zext(i_cf); + local result:$(SIZE) = op1 - op2; + local result_low_32:4 = op1_low_32 - op2_low_32; + i_cf = (op1_low_32 < op2_low_32) || (result_low_32 < CFcopy_4); + x_cf = (op1 < op2) || (result < CFcopy); + i_vf = sborrow( op1_low_32, op2_low_32) ^^ sborrow( result_low_32, CFcopy_4); + x_vf = sborrow(op1, op2) ^^ sborrow(result,CFcopy); +} + +macro logicflags() { + x_cf = 0; + x_vf = 0; + + i_cf = 0; + i_vf = 0; +} + +macro subflags(op1,op2) { + x_cf = op1 < op2; + x_vf = sborrow(op1,op2); + + local tmp1 = op1:4; + local tmp2 = op2:4; + + i_cf = tmp1 < tmp2; + i_vf = sborrow(tmp1,tmp2); +} + +macro tsubflags(op1,op2){ + subflags(op1,op2); + i_vf = i_vf || ((op1 & 0x3) != 0) || ((op2 & 0x3) != 0); +} + +macro zeroflags(op1) { + x_zf = (op1 == 0); + x_nf = (op1 s< 0); + + local tmp1 = op1:4; + + i_zf = (tmp1 == 0); + i_nf = (tmp1 s< 0); +} + +macro packflags(ccr) { + ccr = zext((x_nf << 7) | (x_zf << 6) | (x_vf << 5) | (x_cf << 4) | (i_nf << 3) | (i_zf << 2) | (i_vf << 1) | (i_cf << 0)); +} + +macro unpackflags(ccr) { + x_nf = (ccr & 0x80)!=0; + x_zf = (ccr & 0x40)!=0; + x_vf = (ccr & 0x20)!=0; + x_cf = (ccr & 0x10)!=0; + i_nf = (ccr & 0x8)!=0; + i_zf = (ccr & 0x4)!=0; + i_vf = (ccr & 0x2)!=0; + i_cf = (ccr & 0x1)!=0; +} + +# --------------- +:add RS1,regorimm,RD is op=2 & RD & op3=0x0 & RS1 & regorimm {RD = RS1 + regorimm;} + +:addcc RS1,regorimm,RD is op=2 & RD & op3=0x10 & RS1 & regorimm +{ + addflags(RS1,regorimm); + RD = RS1 + regorimm; + zeroflags(RD); +} + +:addc RS1,regorimm,RD is op=2 & RD & op3=0x8 & RS1 & regorimm {RD = RS1 + regorimm + zext(i_cf);} + +:addccc RS1,regorimm,RD is op=2 & RD & op3=0x18 & RS1 & regorimm +{ + local original_i_cf:$(SIZE) = zext(i_cf); + addCarryFlags(RS1,regorimm); + RD = RS1 + regorimm + original_i_cf; + zeroflags(RD); +} +#----------------------- +:and RS1,regorimm,RD is op=2 & RD & op3=0x1 & RS1 & regorimm {RD = RS1 & regorimm;} + +:andcc RS1,regorimm,RD is op=2 & RD & op3=0x11 & RS1 & regorimm +{ + logicflags(); + RD = RS1 & regorimm; + zeroflags(RD); +} +:andn RS1,regorimm,RD is op=2 & RD & op3=0x5 & RS1 & regorimm {RD = RS1 & ~regorimm;} + +:andncc RS1,regorimm,RD is op=2 & RD & op3=0x15 & RS1 & regorimm +{ + logicflags(); + RD = RS1 & ~regorimm; + zeroflags(RD); +} + +:or RS1,regorimm,RD is op=2 & RD & op3=0x2 & RS1 & regorimm {RD = RS1 | regorimm;} + +:orcc RS1,regorimm,RD is op=2 & RD & op3=0x12 & RS1 & regorimm +{ + logicflags(); + RD = RS1 | regorimm; + zeroflags(RD); +} +:orn RS1,regorimm,RD is op=2 & RD & op3=0x6 & RS1 & regorimm {RD = RS1 | ~regorimm;} + +:orncc RS1,regorimm,RD is op=2 & RD & op3=0x16 & RS1 & regorimm +{ + logicflags(); + RD = RS1 | ~regorimm; + zeroflags(RD); +} +:xor RS1,regorimm,RD is op=2 & RD & op3=0x3 & RS1 & regorimm {RD = RS1 ^ regorimm;} + +:xorcc RS1,regorimm,RD is op=2 & RD & op3=0x13 & RS1 & regorimm +{ + logicflags(); + RD = RS1 ^ regorimm; + zeroflags(RD); +} + +:xnor RS1,regorimm,RD is op=2 & RD & op3=0x7 & RS1 & regorimm {RD = RS1 ^ ~regorimm;} + +:xnorcc RS1,regorimm,RD is op=2 & RD & op3=0x17 & RS1 & regorimm +{ + logicflags(); + RD = RS1 ^ ~regorimm; + zeroflags(RD); +} + +# --------------- +:ldsb ea,RD is op=3 & RD & op3=0x09 & ea { RD = sext(*:1 ea); } +:ldsh ea,RD is op=3 & RD & op3=0x0A & ea { RD = sext(*:2 ea); } +:ldsw ea,RD is op=3 & RD & op3=0x08 & ea { RD = sext(*:4 ea); } +:ldub ea,RD is op=3 & RD & op3=0x01 & ea { RD = zext(*:1 ea); } +:lduh ea,RD is op=3 & RD & op3=0x02 & ea { RD = zext(*:2 ea); } +:lduw ea,RD is op=3 & RD & op3=0x00 & ea { RD = zext(*:4 ea); } +:ldx ea,RD is op=3 & RD & op3=0x0b & ea { RD = *:$(SIZE) ea; } + +@if SIZE=="8" +:ldd ea,RD is op=3 & RD & op3=0x03 & ea { RD = *:$(SIZE) ea; } +@else +:ldd ea,RD is op=3 & RD & rd_d & op3=0x03 & ea { rd_d = *:8 ea; } + +@endif + +:ldsba ea_alt,RD is op=3 & RD & op3=0x19 & ea_alt { RD = sext(*:1 ea_alt); } +:ldsha ea_alt,RD is op=3 & RD & op3=0x1a & ea_alt { RD = sext(*:2 ea_alt); } +:ldswa ea_alt,RD is op=3 & RD & op3=0x18 & ea_alt { RD = sext(*:4 ea_alt); } +:lduba ea_alt,RD is op=3 & RD & op3=0x11 & ea_alt { RD = zext(*:1 ea_alt); } +:lduha ea_alt,RD is op=3 & RD & op3=0x12 & ea_alt { RD = zext(*:2 ea_alt); } +:lduwa ea_alt,RD is op=3 & RD & op3=0x10 & ea_alt { RD = zext(*:4 ea_alt); } + +:ldxa ea_alt,RD is op=3 & RD & op3=0x1b & ea_alt { RD = *:$(SIZE) ea_alt; } +:ldda ea_alt,RD is op=3 & RD & op3=0x13 & ea_alt { RD = *:$(SIZE) ea_alt; } + +#----------------- +:stb RD,ea is op=3 & RD & op3=0x05 & ea { *ea = RD:1; } +:sth RD,ea is op=3 & RD & op3=0x06 & ea { *ea = RD:2; } +:stw RD,ea is op=3 & RD & op3=0x04 & ea { *ea = RD:4; } + +@if SIZE=="8" +:stx RD,ea is op=3 & RD & op3=0x0e & ea { *ea = RD; } +:std RD,ea is op=3 & RD & op3=0x07 & ea { *ea = RD; } +@else +# size = 4, but this extended store instruction needs to write 8 bytes +:stx RD,ea is op=3 & RD & rd_d & op3=0x0e & ea { *ea = rd_d; } +:std RD,ea is op=3 & RD & rd_d & op3=0x07 & ea { *ea = rd_d; } +@endif + +:clrx ea is op=3 & rd=0 & op3=0x0e & ea { *ea = 0:8; } +:clrd ea is op=3 & rd=0 & op3=0x07 & ea { *ea = 0:8; } + +:stba RD,ea_alt is op=3 & RD & op3=0x15 & ea_alt { *ea_alt = RD:1; } +:stha RD,ea_alt is op=3 & RD & op3=0x16 & ea_alt { *ea_alt = RD:2; } +:stwa RD,ea_alt is op=3 & RD & op3=0x14 & ea_alt { *ea_alt = RD:4; } +:stxa RD,ea_alt is op=3 & RD & op3=0x1e & ea_alt { *ea_alt = RD; } +:stda RD,ea_alt is op=3 & RD & op3=0x17 & ea_alt { *ea_alt = RD; } +# --------------- + +:sub RS1,regorimm,RD is op=2 & RD & op3=0x4 & RS1 & regorimm +{ + RD = RS1 - regorimm; +} + +:subcc RS1,regorimm,RD is op=2 & RD & op3=0x14 & RS1 & regorimm +{ + subflags(RS1,regorimm); + RD = RS1 - regorimm; + zeroflags(RD); +} + +:subc RS1,regorimm,RD is op=2 & RD & op3=0xc & RS1 & regorimm +{ + RD = RS1 - regorimm - zext(i_cf); +} + +:subccc RS1,regorimm,RD is op=2 & RD & op3=0x1c & RS1 & regorimm +{ + local original_cf:$(SIZE) = zext(i_cf); + subCarryFlags(RS1,regorimm); + RD = RS1 - regorimm - original_cf; + zeroflags(RD); +} + +# --------------- + +:nop is op=0x0 & rd=0x0 & op2=0x4 & disp22=0x0 { } + +# ---------------COMPARES + +:cmp RS1,regorimm is op=0x2 & rd=0x0 & op3=0x14 & RS1 & regorimm +{ + subflags(RS1,regorimm); + local tmp = RS1 - regorimm; + zeroflags(tmp); +} + + +# ---------------MOVES + +:mov regorimm,RD is op=2 & RD & op3=0x2 & rs1=0 & regorimm {RD = regorimm;} + +# This will not work until the rs1 field in a token can be used without being +# part of the display portion below +RCOND: "z" is rcond3=1 & RS1 { tmp:1 = (RS1 == 0); export tmp; } +RCOND: "lez" is rcond3=2 & RS1 { tmp:1 = (RS1 s<= 0); export tmp; } +RCOND: "lz" is rcond3=3 & RS1 { tmp:1 = (RS1 s< 0); export tmp; } +RCOND: "nz" is rcond3=5 & RS1 { tmp:1 = (RS1 != 0); export tmp; } +RCOND: "gz" is rcond3=6 & RS1 { tmp:1 = (RS1 s> 0); export tmp; } +RCOND: "gez" is rcond3=7 & RS1 { tmp:1 = (RS1 s>= 0); export tmp; } + +:movr^RCOND RS1,regorimm10,RD is op=0x2 & RD & op3=0x2f & RCOND & regorimm10 & RS1 +{ + if !RCOND goto ; + RD = regorimm10; + +} + +#:movrz RS1,regorimm10,rd is op=0x2 & rd & op3=0x2f & RS1 & rcond3=1 & regorimm10 { if (RS1 == 0) goto inst_next; rd = regorimm10; } +#:movrlez RS1,regorimm10,rd is op=0x2 & rd & op3=0x2f & RS1 & rcond3=2 & regorimm10 { if (RS1 s<= 0) goto inst_next; rd = regorimm10; } +#:movrlz RS1,regorimm10,rd is op=0x2 & rd & op3=0x2f & RS1 & rcond3=3 & regorimm10 { if (RS1 s< 0) goto inst_next; rd = regorimm10; } +#:movrnz RS1,regorimm10,rd is op=0x2 & rd & op3=0x2f & RS1 & rcond3=5 & regorimm10 { if (RS1 != 0) goto inst_next; rd = regorimm10; } +#:movrgz RS1,regorimm10,rd is op=0x2 & rd & op3=0x2f & RS1 & rcond3=6 & regorimm10 { if (RS1 s> 0) goto inst_next; rd = regorimm10; } +#:movrgez RS1,regorimm10,rd is op=0x2 & rd & op3=0x2f & RS1 & rcond3=7 & regorimm10 { if (RS1 s>= 0) goto inst_next; rd = regorimm10; } +m_icc: "a" is cond4=0x8 { tmp:1=1; export tmp; } +m_icc: "n" is cond4=0x0 { tmp:1=0; export tmp; } +m_icc: "ne" is cond4=0x9 { tmp:1=!i_zf; export tmp; } +m_icc: "e" is cond4=0x1 { tmp:1=i_zf; export tmp; } +m_icc: "g" is cond4=0xa { tmp:1=!(i_zf || (i_nf ^^ i_vf)); export tmp; } +m_icc: "le" is cond4=0x2 { tmp:1=(i_zf || (i_nf ^^ i_vf)); export tmp; } +m_icc: "ge" is cond4=0xb { tmp:1=!(i_nf ^^ i_vf); export tmp; } +m_icc: "l" is cond4=0x3 { tmp:1=(i_nf ^^ i_vf); export tmp; } +m_icc: "gu" is cond4=0xc { tmp:1=!(i_cf || i_zf); export tmp; } +m_icc: "leu" is cond4=0x4 { tmp:1=(i_cf || i_zf); export tmp; } +m_icc: "cc" is cond4=0xd { tmp:1=!(i_cf); export tmp; } +m_icc: "cs" is cond4=0x5 { export i_cf; } +m_icc: "pos" is cond4=0xe { tmp:1=!(i_nf); export tmp; } +m_icc: "neg" is cond4=0x6 { export i_nf; } +m_icc: "vc" is cond4=0xf { tmp:1=!(i_vf); export tmp; } +m_icc: "vs" is cond4=0x7 { export i_vf; } + +m_xcc: "a" is cond4=0x8 { tmp:1=1; export tmp; } +m_xcc: "n" is cond4=0x0 { tmp:1=0; export tmp; } +m_xcc: "ne" is cond4=0x9 { tmp:1=!x_zf; export tmp; } +m_xcc: "e" is cond4=0x1 { tmp:1=x_zf; export tmp; } +m_xcc: "g" is cond4=0xa { tmp:1=!(x_zf || (x_nf ^^ x_vf)); export tmp; } +m_xcc: "le" is cond4=0x2 { tmp:1=(x_zf || (x_nf ^^ x_vf)); export tmp; } +m_xcc: "ge" is cond4=0xb { tmp:1=!(x_nf ^^ x_vf); export tmp; } +m_xcc: "l" is cond4=0x3 { tmp:1=(x_nf ^^ x_vf); export tmp; } +m_xcc: "gu" is cond4=0xc { tmp:1=!(x_cf || x_zf); export tmp; } +m_xcc: "leu" is cond4=0x4 { tmp:1=(x_cf || x_zf); export tmp; } +m_xcc: "cc" is cond4=0xd { tmp:1=!(x_cf); export tmp; } +m_xcc: "cs" is cond4=0x5 { export x_cf; } +m_xcc: "pos" is cond4=0xe { tmp:1=!(x_nf); export tmp; } +m_xcc: "neg" is cond4=0x6 { export x_nf; } +m_xcc: "vc" is cond4=0xf { tmp:1=!(x_vf); export tmp; } +m_xcc: "vs" is cond4=0x7 { export x_vf; } + +m_cc:m_icc is cc2_4=1 & cc1_4=0 & cc0_4=0 & m_icc { export m_icc; } +m_cc:m_xcc is cc2_4=1 & cc1_4=1 & cc0_4=0 & m_xcc { export m_xcc; } + +MICC: "%icc" is cc2_4=1 &cc1_4=0 { } +MICC: "%xcc" is cc2_4=1 &cc1_4=1 { } + +#conditional integer moves with floating-point conditions defined in constructor :mov^fmfcc +:mov^m_cc MICC,regorimm11,RD is op=0x2 & RD & op3=0x2c & bit18=1 & m_cc & MICC & regorimm11 +{ + if (!m_cc) goto ; + RD = regorimm11; + +} + +# ---------------BRANCHES +icc: "a" is cond=0x8 { tmp:1=1; export tmp; } +icc: "ne" is cond=0x9 { tmp:1=!i_zf; export tmp; } +icc: "e" is cond=0x1 { tmp:1=i_zf; export tmp; } +icc: "g" is cond=0xa { tmp:1=!(i_zf || (i_nf ^^ i_vf)); export tmp; } +icc: "le" is cond=0x2 { tmp:1=(i_zf || (i_nf ^^ i_vf)); export tmp; } +icc: "ge" is cond=0xb { tmp:1=!(i_nf ^^ i_vf); export tmp; } +icc: "l" is cond=0x3 { tmp:1=(i_nf ^^ i_vf); export tmp; } +icc: "gu" is cond=0xc { tmp:1=!(i_cf || i_zf); export tmp; } +icc: "leu" is cond=0x4 { tmp:1=(i_cf || i_zf); export tmp; } +icc: "cc" is cond=0xd { tmp:1=!(i_cf); export tmp; } +icc: "cs" is cond=0x5 { export i_cf; } +icc: "pos" is cond=0xe { tmp:1=!(i_nf); export tmp; } +icc: "neg" is cond=0x6 { export i_nf; } +icc: "vc" is cond=0xf { tmp:1=!(i_vf); export tmp; } +icc: "vs" is cond=0x7 { export i_vf; } + +xcc: "a" is cond=0x8 { tmp:1=1; export tmp; } +xcc: "ne" is cond=0x9 { tmp:1=!x_zf; export tmp; } +xcc: "e" is cond=0x1 { tmp:1=x_zf; export tmp; } +xcc: "g" is cond=0xa { tmp:1=!(x_zf || (x_nf ^^ x_vf)); export tmp; } +xcc: "le" is cond=0x2 { tmp:1=(x_zf || (x_nf ^^ x_vf)); export tmp; } +xcc: "ge" is cond=0xb { tmp:1=!(x_nf ^^ x_vf); export tmp; } +xcc: "l" is cond=0x3 { tmp:1=(x_nf ^^ x_vf); export tmp; } +xcc: "gu" is cond=0xc { tmp:1=!(x_cf || x_zf); export tmp; } +xcc: "leu" is cond=0x4 { tmp:1=(x_cf || x_zf); export tmp; } +xcc: "cc" is cond=0xd { tmp:1=!(x_cf); export tmp; } +xcc: "cs" is cond=0x5 { export x_cf; } +xcc: "pos" is cond=0xe { tmp:1=!(x_nf); export tmp; } +xcc: "neg" is cond=0x6 { export x_nf; } +xcc: "vc" is cond=0xf { tmp:1=!(x_vf); export tmp; } +xcc: "vs" is cond=0x7 { export x_vf; } + +cc: icc is cc1=0 & cc0=0 & icc { export icc; } +cc: xcc is cc1=1 & cc0=0 & xcc { export xcc; } + +d16off: reloc is d16hi & d16lo [reloc = inst_start+4*((d16hi<<14) | d16lo);] { export *:$(SIZE) reloc; } + +predict: ",pt" is p=1 { } +predict: ",pn" is p=0 { } + +:brz^predict RS1,d16off is op=0 & a=0 & bit28=0 & rcond2=0x1 & op2=0x3 & RS1 & d16off & predict { delayslot(1); if (RS1 == 0) goto d16off;} +:brlez^predict RS1,d16off is op=0 & a=0 & bit28=0 & rcond2=0x2 & op2=0x3 & RS1 & d16off & predict { delayslot(1); if (RS1 s<= 0) goto d16off;} +:brlz^predict RS1,d16off is op=0 & a=0 & bit28=0 & rcond2=0x3 & op2=0x3 & RS1 & d16off & predict { delayslot(1); if (RS1 s< 0) goto d16off;} +:brnz^predict RS1,d16off is op=0 & a=0 & bit28=0 & rcond2=0x5 & op2=0x3 & RS1 & d16off & predict { delayslot(1); if (RS1 != 0) goto d16off;} +:brgz^predict RS1,d16off is op=0 & a=0 & bit28=0 & rcond2=0x6 & op2=0x3 & RS1 & d16off & predict { delayslot(1); if (RS1 s> 0) goto d16off;} +:brgez^predict RS1,d16off is op=0 & a=0 & bit28=0 & rcond2=0x7 & op2=0x3 & RS1 & d16off & predict { delayslot(1); if (RS1 s>= 0) goto d16off;} + +:brz^",a"^predict RS1,d16off is op=0 & a=1 & bit28=0 & rcond2=0x1 & op2=0x3 & RS1 & d16off & predict { if (RS1 != 0) goto inst_next; delayslot(1); goto d16off;} +:brlez^",a"^predict RS1,d16off is op=0 & a=1 & bit28=0 & rcond2=0x2 & op2=0x3 & RS1 & d16off & predict { if (RS1 s> 0) goto inst_next; delayslot(1); goto d16off;} +:brlz^",a"^predict RS1,d16off is op=0 & a=1 & bit28=0 & rcond2=0x3 & op2=0x3 & RS1 & d16off & predict { if (RS1 s>= 0) goto inst_next; delayslot(1); goto d16off;} +:brnz^",a"^predict RS1,d16off is op=0 & a=1 & bit28=0 & rcond2=0x5 & op2=0x3 & RS1 & d16off & predict { if (RS1 == 0) goto inst_next; delayslot(1); goto d16off;} +:brgz^",a"^predict RS1,d16off is op=0 & a=1 & bit28=0 & rcond2=0x6 & op2=0x3 & RS1 & d16off & predict { if (RS1 s<= 0) goto inst_next; delayslot(1); goto d16off;} +:brgez^",a"^predict RS1,d16off is op=0 & a=1 & bit28=0 & rcond2=0x7 & op2=0x3 & RS1 & d16off & predict { if (RS1 s< 0) goto inst_next; delayslot(1); goto d16off;} + +BCC: "%icc" is cc0=0 & cc1=0 { } +BCC: "%xcc" is cc0=0 & cc1=1 { } + +reloff: reloc is disp22 [reloc=inst_start+(4*disp22);] { export *:$(SIZE) reloc; } +reloff64: reloc is disp19 [reloc=inst_start+(4*disp19);] { export *:$(SIZE) reloc; } + +skip: reloc is epsilon [reloc=inst_start+8;] { export *:$(SIZE) reloc; } + +:ba reloff is op=0x0 & op2=0x2 & a=0x0 & cond=0x8 & reloff { delayslot(1); goto reloff; } +:"ba,a" reloff is op=0x0 & op2=0x2 & a=0x1 & cond=0x8 & reloff { goto reloff; } + +:bn reloff is op=0x0 & op2=0x2 & a=0x0 & cond=0x0 & reloff { } +:"bn,a" reloff,skip is op=0x0 & op2=0x2 & a=0x1 & cond=0x0 & reloff & skip { goto skip; } + +:b^icc reloff is op=0x0 & op2=0x2 & a=0x0 & icc & reloff { delayslot(1); if (icc) goto reloff; } +:b^icc^",a" reloff is op=0x0 & op2=0x2 & a=0x1 & icc & reloff { if (!icc) goto inst_next; delayslot(1); goto reloff; } + +:bpa^predict reloff64 is op=0x0 & op2=0x1 & a=0x0 & cond=0x8 & reloff64 & predict { delayslot(1); goto reloff64; } +:"bpa,a"^predict reloff64 is op=0x0 & op2=0x1 & a=0x1 & cond=0x8 & reloff64 & predict { goto reloff64; } + +:bpn^predict reloff64 is op=0x0 & op2=0x1 & a=0x0 & cond=0x0 & reloff64 & predict { } +:"bpn,a"^predict reloff64,skip is op=0x0 & op2=0x1 & a=0x1 & cond=0x0 & reloff64 & predict & skip { goto skip; } + +:bp^cc^predict BCC,reloff64 is op=0x0 & op2=0x1 & a=0x0 & cond & cc & reloff64 & predict & BCC { delayslot(1); if (cc) goto reloff64; } +:bp^cc^",a"^predict BCC,reloff64 is op=0x0 & op2=0x1 & a=0x1 & cond & cc & reloff64 & predict & BCC { if (!cc) goto inst_next; delayslot(1); goto reloff64; } + +#:br^cc^predict reloff64 is op=0x0 & a=0x0 & op2=0x3 & cc & reloff64 & predict { delayslot(1); if (cc) goto reloff64; } +#:br^cc^",a"^predict reloff64 is op=0x0 & a=0x1 & op2=0x3 & cc & reloff64 & predict { if (!cc) goto inst_next; delayslot(1); goto reloff64; } +#---------------CALL +callreloff: reloc is disp30 [reloc=inst_start+4*disp30;] { export *:$(SIZE) reloc; } + +:call callreloff is op=0x1 & callreloff { + o7=inst_start; didrestore=0; delayslot(1); call callreloff; if (didrestore==0) goto inst_next; return [o7]; +} + +# changing to jump for PIC call if destination is right below this one. +:call callreloff is op=0x1 & disp30=2 & callreloff { + o7=inst_start; delayslot(1); goto callreloff; +} + +#----------------RET + +#----------------MULTIPLY AND DIVIDE 64 bit + +:mulx RS1,regorimm,RD is op=2 & RD & op3=0x09 & RS1 & regorimm {RD = RS1 * regorimm;} +:sdivx RS1,regorimm,RD is op=2 & RD & op3=0x2d & RS1 & regorimm {RD = RS1 s/ regorimm;} +:udivx RS1,regorimm,RD is op=2 & RD & op3=0x0d & RS1 & regorimm {RD = RS1 / regorimm;} + +#----------------MULTIPLY 32 bit +@if SIZE=="8" +:umul RS1,regorimm,RD is op=2 & RD & op3=0x0a & RS1 & regorimm {RD = zext(RS1:4) * zext(regorimm:4); Y=RD>>32;} +:smul RS1,regorimm,RD is op=2 & RD & op3=0x0b & RS1 & regorimm {RD = sext(RS1:4) * sext(regorimm:4); Y=RD>>32;} +:umulcc RS1,regorimm,RD is op=2 & RD & op3=0x1a & RS1 & regorimm {RD = zext(RS1:4) * zext(regorimm:4); Y=RD>>32; zeroflags(RD); logicflags();} +:smulcc RS1,regorimm,RD is op=2 & RD & op3=0x1b & RS1 & regorimm {RD = sext(RS1:4) * sext(regorimm:4); Y=RD>>32; zeroflags(RD); logicflags();} + +@else +# size = 4 +:umul RS1,regorimm,RD is op=2 & RD & op3=0x0a & RS1 & regorimm +{ + tmp_RS1:8 = zext(RS1); + tmp_regorimm:8 = zext(regorimm); + tmp:8 = tmp_RS1 * tmp_regorimm; + RD = tmp:4; tmp2:8 = tmp >> 32; + Y = tmp2:4; +} + +:smul RS1,regorimm,RD is op=2 & RD & op3=0x0b & RS1 & regorimm +{ + tmp_RS1:8 = sext(RS1); + tmp_regorimm:8 = sext(regorimm); + tmp:8 = tmp_RS1 * tmp_regorimm; + RD = tmp:4; tmp2:8 = tmp >> 32; + Y = tmp2:4; +} + +:umulcc RS1,regorimm,RD is op=2 & RD & op3=0x1a & RS1 & regorimm +{ + RD = zext(RS1:4) * zext(regorimm:4); + Y=RD>>32; + zeroflags(RD); + logicflags(); +} +:smulcc RS1,regorimm,RD is op=2 & RD & op3=0x1b & RS1 & regorimm +{ + RD = zext(RS1:4) * zext(regorimm:4); + Y=RD>>32; + zeroflags(RD); + logicflags(); +} + +@endif + +#----------------MULTIPLY Step + +:mulscc RS1,regorimm,RD is op=2 & RD & op3=0x24 & RS1 & regorimm +{ + local ccr:4 = zext(i_nf ^^ i_vf); + ccr = ccr << 31; + local shifted:4 = RS1:4 >> 1; + shifted = shifted | ccr; + local addend:4 = 0:4; + if ((Y & 0x1) == 0) goto ; + addend = regorimm:4; + + local sum:4 = addend + shifted; + addflags32(addend,shifted); + #upper 32 bits of RD are undefined according to the manual + local tbit:4 = (RS1:4 & 0x1:4) << 31; + RD = zext(sum); + zeroflags(RD); + #Y is 64 bits in Sparc 9 but the high 32 are fixed to 0 + Y = zext((Y:4 >> 1:4) | tbit); +} + +#----------------DIVIDE (64-bit / 32-bit) + +# NB- Beware, the plus + operator has higher precedence than shift << +# (These are Java rules. C rules have shift and + at the same level, so left to right) + +:udiv RS1,regorimm,RD is op=2 & RD & op3=0x0e & RS1 & regorimm +{ + numerator:$(SIZE)= (Y << 32) + (RS1 & 0xffffffff); + denom:$(SIZE) = regorimm & 0xffffffff; + RD = numerator / denom; +} +:sdiv RS1,regorimm,RD is op=2 & RD & op3=0x0f & RS1 & regorimm +{ + numerator:$(SIZE)= (Y << 32) + (RS1 & 0xffffffff); + denom:$(SIZE) = regorimm & 0xffffffff; + RD = numerator s/ denom; +} + +:udivcc RS1,regorimm,RD is op=2 & RD & op3=0x1e & RS1 & regorimm +{ + numerator:$(SIZE)= ( Y << 32) + (RS1 & 0xffffffff); + denom:$(SIZE) = regorimm & 0xffffffff; + RD = numerator / denom; + zeroflags(RD); + i_vf = RD > 0xffffffff; + i_cf = 0; + x_vf = 0; + x_cf = 0; +} +:sdivcc RS1,regorimm,RD is op=2 & RD & op3=0x1f & RS1 & regorimm +{ + numerator:$(SIZE)= (Y << 32) + (RS1 & 0xffffffff); + denom:$(SIZE) = regorimm & 0xffffffff; + RD = numerator s/ denom; + zeroflags(RD); + i_vf = (RD s>= 0x80000000) || (RD s<= -0x7ffffffff); + i_cf = 0; + x_vf = 0; + x_cf = 0; +} + +#---------------SHIFT + +:sll RS1,reg_or_shcnt,RD is op=0x2 & RD & op3=0x25 & x=0 & RS1 & reg_or_shcnt { RD=RS1<>reg_or_shcnt; } + +:sllx RS1,reg_or_shcnt,RD is op=0x2 & RD & op3=0x25 & x=1 & RS1 & reg_or_shcnt { RD=RS1<>reg_or_shcnt; } + +:sra RS1,reg_or_shcnt,RD is op=0x2 & RD & op3=0x27 & x=0 & RS1 & reg_or_shcnt { tmp:4=RS1:4; RD=sext(tmp s>> reg_or_shcnt); } +:srax RS1,reg_or_shcnt,RD is op=0x2 & RD & op3=0x27 & x=1 & RS1 & reg_or_shcnt { RD=RS1 s>> reg_or_shcnt; } + +# ASR read registers (some ASR #s not permitted for rd: 1, 7..15, other #s handled by rd: 3, 5, 6) +attach variables [ rs_asr ] [ Y _ CCR _ TICK _ _ _ + _ _ _ _ _ _ _ _ + PCR PIC asr18 GSR SOFTINT_SET SOFTINT_CLR SOFTINT TICK_CMPR + STICK STICK_CMPR asr26 asr27 asr28 asr29 asr30 asr31 ]; + +# ASR read registers +rsASR: "%"^ASI is rs_asr=3 & ASI { tmp:$(SIZE) = zext(ASI); export tmp; } +rsASR: "%"^PC is rs_asr=5 & PC { tmp:$(SIZE) = inst_start; export tmp; } +rsASR: "%"^FPRS is rs_asr=6 & FPRS { tmp:$(SIZE) = zext(FPRS); export tmp; } +rsASR: "%"^rs_asr is rs_asr { export rs_asr; } + +#---------------RD ASR special register (STBAR instruction must be defined after this instruction) +:rd rsASR,RD is op=0x2 & RD & op3=0x28 & rsASR & i=0 { RD = rsASR; } +:rd rsASR,RD is op=0x2 & RD & op3=0x28 & rs_asr=2 & rsASR & i=0 { packflags(RD); } # packed CCR register displayed + +# ASR write registers (some ASR #s not permitted for wr: 1, 4, 5, 7..15, other #s handled by wr: 2, 3, 6) +attach variables [ rd_asr ] [ Y _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ + PCR PIC asr18 GSR SOFTINT_SET SOFTINT_CLR SOFTINT TICK_CMPR + STICK STICK_CMPR asr26 asr27 asr28 asr29 asr30 asr31 ]; + +# ASR write registers +wrY: "%"^Y is rd_asr=0 & Y {export Y;} +wrCCR: "%"^CCR is rd_asr=2 & CCR { export CCR; } # packed CCR register displayed +wrASI: "%"^ASI is rd_asr=3 & ASI { export ASI; } +wrFPRS: "%"^FPRS is rd_asr=6 & FPRS { export FPRS; } +wrASR: "%"^rd_asr is rd_asr { export rd_asr; } + +#---------------WR ASR special register (SIR instruction must be defined after this instruction) +# NOTE: the following ASR register numbers are not allowed: 1, 4, 5, 7..14 +:wr RS1,regorimm,wrCCR is op=0x2 & RS1 & regorimm & op3=0x30 & rd_asr=2 & wrCCR { local tmp = RS1 ^ regorimm; unpackflags(tmp); } +:wr RS1,regorimm,wrASI is op=0x2 & RS1 & regorimm & op3=0x30 & rd_asr=3 & wrASI { local tmp = RS1 ^ regorimm; wrASI = tmp:1; } +:wr RS1,regorimm,wrFPRS is op=0x2 & RS1 & regorimm & op3=0x30 & rd_asr=6 & wrFPRS { local tmp = RS1 ^ regorimm; FPRS = tmp:1; } +:wr RS1,regorimm,wrY is op=0x2 & RS1 & regorimm & op3=0x30 & rd_asr=0 & wrY { Y = zext(RS1:4 ^ regorimm:4); } +:wr RS1,regorimm,wrASR is op=0x2 & RS1 & regorimm & op3=0x30 & wrASR { wrASR = RS1 ^ regorimm; } + +#---------------MISC +sethidisp: "%hi("^hi^")" is udisp22 [hi=udisp22<<10;] { export *[const]:$(SIZE) hi; } + +:sethi sethidisp,RD is RD & op=0x0 & op2=0x4 & sethidisp { RD=sethidisp; } + +:popc regorimm, RD is op=0x2 & RD & op3=0x2e & rs1=0 & regorimm { RD = popcount(regorimm); } + +:save RS1,regorimm,RD is op=0x2 & RD & op3=0x3c & RS1 & regorimm { local tmp = RS1 + regorimm; save(); RD = tmp; } + +:restore RS1,regorimm,RD is op=0x2 & RD & op3=0x3d & RS1 & regorimm { local tmp = RS1 + regorimm; restore(); didrestore=1; RD = tmp; } +:restore is op=0x2 & rd=0 & op3=0x3d { restore(); didrestore=1; } + +:return retea is op=0x2 & op3=0x39 & retea { build retea; restore(); delayslot(1); didrestore=1; return [retea]; } + +:jmpl retea,RD is op=0x2 & RD & op3=0x38 & retea { build retea; RD = inst_start; delayslot(1); goto [retea]; } + +# special case where link register is loaded with return address; functions as indirect call +:jmpl retea,RD is op=0x2 & RD & prd=15 & op3=0x38 & retea { build retea; RD = inst_start; delayslot(1); call [retea]; } + +:jmpl retea is op=0x2 & rd=0 & op3=0x38 & retea { build retea; delayslot(1); goto [retea]; } +:ret is op=0x2 & rd=0 & rs1=31 & op3=0x38 & i=1 & simm13=8 & retea { build retea; delayslot(1); return [retea]; } +:retl is op=0x2 & rd=0 & rs1=15 & op3=0x38 & i=1 & simm13=8 & retea { build retea; delayslot(1); return [retea]; } + +casa_ea: [RS1]imm_asi is i=0 & RS1 & imm_asi { local tmp1:1 = imm_asi; local tmp = RS1+segment(tmp1); export tmp; } +casa_ea: [RS1]%ASI is i=1 & RS1 & ASI { local tmp = RS1+segment(ASI); export tmp; } + +:casa casa_ea,RS2,RD is op=0x3 & RD & op3=0x3c & casa_ea & RS2 +{ + local tmp:4=RD:4; + RD=zext(*:4 casa_ea); + if ((RS2 & 0xFFFFFFFF)!=RD) goto ; + *:4 casa_ea=tmp; + +} +:casxa casa_ea,RS2,RD is op=0x3 & RD & op3=0x3e & casa_ea & RS2 +{ + local tmp=RD; + RD=*:$(SIZE) casa_ea; + if (RS2!=RD) goto ; + *:$(SIZE) casa_ea=tmp; + +} + +:impdef1 is op=0x2 & op3=0x36 unimpl +:impdef2 is op=0x2 & op3=0x37 unimpl + +:ldstub ea,RD is op=0x3 & RD & op3=0xd & ea { RD = zext(*:1 ea); *:1 ea = 0xFF; } +:ldstuba ea_alt,RD is op=0x3 & RD & op3=0x1d & ea_alt { RD = zext(*:1 ea_alt); *:1 ea_alt = 0xFF; } + +:swap ea,RD is op=0x3 & RD & op3=0xF & ea { tmp:4=RD:4; RD = zext(*:4 ea); *:4 ea = tmp; } +:swapa ea_alt,RD is op=0x3 & RD & op3=0x1F & ea_alt { tmp:4=RD:4; RD = zext(*:4 ea_alt); *:4 ea_alt = tmp; } + +:taddcc RS1,regorimm,RD is op=2 & RD & op3=0x20 & RS1 & regorimm +{ + taddflags(RS1,regorimm); + RD = RS1 + regorimm; + zeroflags(RD); +} +:taddcctv RS1,regorimm,RD is op=2 & RD & op3=0x22 & RS1 & regorimm +{ + taddflags(RS1,regorimm); + RD = RS1 + regorimm; + zeroflags(RD); +} +:tsubcc RS1,regorimm,RD is op=2 & RD & op3=0x21 & RS1 & regorimm +{ + tsubflags(RS1,regorimm); + RD = RS1 - regorimm; + zeroflags(RD); +} +:tsubcctv RS1,regorimm,RD is op=2 & RD & op3=0x23 & RS1 & regorimm +{ + tsubflags(RS1,regorimm); + RD = RS1 - regorimm; + zeroflags(RD); +} + +tcc: icc is cc1_4=0 & cc0_4=0 & icc { export icc; } +tcc: xcc is cc1_4=1 & cc0_4=0 & xcc { export xcc; } + +TICC: "%icc" is cc1_4=0 &cc0_4=0 { } +TICC: "%xcc" is cc1_4=1 &cc0_4=0 { } + +trap: RS1+RS2 is i=0 & RS1 & RS2 { local tmp = ((RS1 + RS2) & 0x7F); export tmp; } +trap: RS1+swtrap is i=1 & RS1 & swtrap { local tmp = ((RS1 + swtrap) & 0x7F); export tmp; } + +:t^tcc TICC, trap is op=0x2 & op3=0x3a & tcc & TICC & trap { sw_trap(trap); } + +membar_mask: is cmask & mmask { tmp:1 = (cmask << 4) | mmask; export tmp; } + +:membar membar_mask is op=0x2 & rd=0 & op3=0x28 & rs1=0xF & i=1 & membar_mask {} + +:stbar is op=0x2 & rd=0 & op3=0x28 & rs1=0xF & i=0 {} + +:sir simm13 is op=0x2 & rd=0xF & op3=0x30 & rs1=0x0 & i=1 & simm13 { reset(); } + +attach variables [ prs1 prd ] [ TPC1 TNPC1 TSTATE1 TT1 TCK TBA PSTATE TL + PIL CWP CANSAVE CANRESTORE CLEANWIN OTHERWIN WSTATE FQ + GL _ _ _ _ _ _ _ _ _ _ _ _ _ _ VER ]; + +tnpc: "%tnpc" is fcn { local reloc = zext(TL == 1)*&TNPC1 + zext(TL == 2)*&TNPC2 + zext(TL == 3)*&TNPC3 + zext(TL ==4)*&TNPC4; export reloc; } + +tpc: "%tpc" is fcn { local reloc = zext(TL == 1)*&TPC1 + zext(TL == 2)*&TPC2 + zext(TL == 3)*&TPC3 + zext(TL ==4)*&TPC4; export reloc; } + +tt: "%tt" is fcn { local tmp = zext(TL == 1)* &TT1 + zext(TL == 2)*&TT2 + zext(TL == 3)*&TT3 + zext(TL ==4)*&TT4; export tmp; } + +tstate: "%tstate" is fcn { local tmp = zext(TL == 1)* &TSTATE1 + zext(TL == 2)* &TSTATE2 + zext(TL == 3)* &TSTATE3 + zext(TL==4)* &TSTATE4; export tmp; } + +# prs1 is same bits as rs1 +# prd is same bits as rd +:rdpr prs1,RD is op=0x2 & RD & op3=0x2A & prs1 {RD = prs1; } +:rdpr tpc,RD is op=0x2 & prs1 = 0 & RD & op3=0x2A & tpc { RD = *[register]:$(SIZE) tpc; } +:rdpr tnpc,RD is op=0x2 & prs1 = 1 & RD & op3=0x2A & tnpc {RD = *[register]:$(SIZE) tnpc; } +:rdpr tt,RD is op=0x2 & prs1 = 2 & RD & op3=0x2A & tt { RD = *[register]:$(SIZE) tt; } +:rdpr tstate,RD is op=0x2 & prs1 = 3 & RD & op3=0x2A & tstate {RD = *[register]:$(SIZE) tstate;} + +:wrpr RS1,regorimm,prd is op=0x2 & prd & op3=0x32 & RS1 & regorimm {prd = RS1^regorimm; } +:wrpr RS1,regorimm,tpc is op=0x2 & prd = 0 & op3=0x32 & RS1 & regorimm & tpc { *[register]:$(SIZE) tpc = RS1^regorimm; } +:wrpr RS1,regorimm,tnpc is op=0x2 & prd = 1 & op3=0x32 & RS1 & regorimm & tnpc { *[register]:$(SIZE) tnpc = RS1^regorimm; } +:wrpr RS1,regorimm,tstate is op=0x2 & prd = 2 & op3=0x32 & RS1 & regorimm & tstate { *[register]:$(SIZE) tstate = RS1^regorimm; } +:wrpr RS1,regorimm,tt is op=0x2 & prd = 3 & op3=0x32 & RS1 & regorimm & tt { *[register]:$(SIZE) tt = RS1^regorimm; } + +hpstate: "%hpstate" is fcn { local reloc = zext(TL == 1)*&HPSTATE1 + zext(TL == 2)*&HPSTATE2 + zext(TL == 3)*&HPSTATE3 + zext(TL ==4)*&HPSTATE4; export reloc; } + +htstate: "%htstate" is fcn { local reloc = zext(TL == 1)*&HTSTATE1 + zext(TL == 2)*&HTSTATE2 + zext(TL == 3)*&HTSTATE3 + zext(TL ==4)*&HTSTATE4; export reloc; } + +hintp: "%hintp" is fcn { local reloc = zext(TL == 1)*&HINTP1 + zext(TL == 2)*&HINTP2 + zext(TL == 3)*&HINTP3 + zext(TL ==4)*&HINTP4; export reloc; } + +htba: "%htba" is fcn { local reloc = zext(TL == 1)*&HTBA1 + zext(TL == 2)*&HTBA2 + zext(TL == 3)*&HTBA3 + zext(TL ==4)*&HTBA4; export reloc; } + +hver: "%hver" is fcn { local reloc = zext(TL == 1)*&HVER1 + zext(TL == 2)*&HVER2 + zext(TL == 3)*&HVER3 + zext(TL ==4)*&HVER4; export reloc; } + +hsys_tick_cmpr: "%hstick_cmpr" is fcn { local reloc = zext(TL == 1)*&HSTICK_CMPR1 + zext(TL == 2)*&HSTICK_CMPR2 + zext(TL == 3)*&HSTICK_CMPR3 + zext(TL ==4)*&HSTICK_CMPR4; export reloc; } + +resv30: "%resv30" is fcn { local reloc = zext(TL == 1)*&RESV30_1 + zext(TL == 2)*&RESV30_2 + zext(TL == 3)*&RESV30_3 + zext(TL ==4)*&RESV30_4; export reloc; } + +:rdhpr hpstate,RD is op=0x2 & prs1 = 0 & RD & op3=0x29 & hpstate { RD = *[register]:$(SIZE) hpstate; } +:rdhpr htstate,RD is op=0x2 & prs1 = 1 & RD & op3=0x29 & htstate { RD = *[register]:$(SIZE) htstate; } +:rdhpr hintp,RD is op=0x2 & prs1 = 3 & RD & op3=0x29 & hintp { RD = *[register]:$(SIZE) hintp; } +:rdhpr htba,RD is op=0x2 & prs1 = 5 & RD & op3=0x29 & htba { RD = *[register]:$(SIZE) htba; } +:rdhpr hver,RD is op=0x2 & prs1 = 6 & RD & op3=0x29 & hver { RD = *[register]:$(SIZE) hver; } +:rdhpr hsys_tick_cmpr,RD is op=0x2 & prs1 = 31 & RD & op3=0x29 & hsys_tick_cmpr { RD = *[register]:$(SIZE) hsys_tick_cmpr; } +:rdhpr resv30,RD is op=0x2 & prs1 = 30 & RD & op3=0x29 & resv30 { RD = *[register]:$(SIZE) resv30; } + +:wrhpr RS1,regorimm,hpstate is op=0x2 & prd = 0 & op3=0x33 & RS1 & regorimm & hpstate { *[register]:$(SIZE) hpstate = RS1^regorimm; } +:wrhpr RS1,regorimm,htstate is op=0x2 & prd = 1 & op3=0x33 & RS1 & regorimm & htstate { *[register]:$(SIZE) htstate = RS1^regorimm; } +:wrhpr RS1,regorimm,hintp is op=0x2 & prd = 3 & op3=0x33 & RS1 & regorimm & hintp { *[register]:$(SIZE) hintp = RS1^regorimm; } +:wrhpr RS1,regorimm,htba is op=0x2 & prd = 5 & op3=0x33 & RS1 & regorimm & htba { *[register]:$(SIZE) htba = RS1^regorimm; } +:wrhpr RS1,regorimm,hsys_tick_cmpr is op=0x2 & prd = 31 & op3=0x33 & RS1 & regorimm & hsys_tick_cmpr { *[register]:$(SIZE) hsys_tick_cmpr = RS1^regorimm; } +:wrhpr RS1,regorimm,resv30 is op=0x2 & prd = 30 & op3=0x33 & RS1 & regorimm & resv30 { *[register]:$(SIZE) resv30 = RS1^regorimm; } + + + +:done is op = 2 & fcn = 0 & op3 = 0x3e & tnpc {TL=TL-1;return [tnpc]; } +:retry is op = 2 & fcn = 1 & op3 = 0x3e & tpc {TL=TL-1;return [tpc]; } + +:flush ea is op = 2 & op3 = 0x3b & ea {} +:flushw is op = 2 & op3 = 0x2b & i = 0 {} + +define pcodeop IllegalInstructionTrap; + +:illtrap const22 is op = 0 & op2 = 0 & const22 { + IllegalInstructionTrap(const22:4); + tmp:$(SIZE) = 0; # trap - don't fall-thru + return [ tmp ]; +} + +:prefetch ea,fcn is op=3 & fcn & op3 = 0x2d & ea {} +:prefetcha ea_alt,fcn is op=3 & fcn & op3 = 0x3d & ea_alt {} +:restored is op = 2 & fcn=1 & op3 = 0x31 {} +:saved is op = 2 & fcn = 0 & op3 = 0x31 {} + +attach variables [fsrd fsrs1 fsrs2 ] [ fs0 fs1 fs2 fs3 fs4 fs5 fs6 fs7 + fs8 fs9 fs10 fs11 fs12 fs13 fs14 fs15 + fs16 fs17 fs18 fs19 fs20 fs21 fs22 fs23 + fs24 fs25 fs26 fs27 fs28 fs29 fs30 fs31 ]; + +attach variables [fdrd fdrs1 fdrs2 ] [ fd0 fd32 fd2 fd34 fd4 fd36 fd6 fd38 + fd8 fd40 fd10 fd42 fd12 fd44 fd14 fd46 + fd16 fd48 fd18 fd50 fd20 fd52 fd22 fd54 + fd24 fd56 fd26 fd58 fd28 fd60 fd30 fd62 ]; + +attach variables [fqrd fqrs1 fqrs2 ] [ fq0 _ fq32 _ fq4 _ fq36 _ fq8 _ fq40 _ fq12 _ fq44 + _ fq16 _ fq48 _ fq20 _ fq52 _ fq24 _ fq56 _ fq28 _ fq60 _]; + +define pcodeop ld; +define pcodeop ldd; +define pcodeop ldq; +define pcodeop ldx; +define pcodeop lda; +define pcodeop ldda; +define pcodeop ldqa; +define pcodeop ld_fsr; +define pcodeop ldx_fsr; + +define pcodeop st; +define pcodeop std; +define pcodeop stq; +define pcodeop stx; +define pcodeop st_fsr; +define pcodeop stx_fsr; + +define pcodeop sta; +define pcodeop stda; +define pcodeop stqa; + +:fabss fsrs2,fsrd is op=0x2 & fsrd & op3=0x34 & opf=0x9 & fsrs2 { fsrd = abs(fsrs2); } +:fabsd fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & opf=0xa & fdrs2 { fdrd = abs(fdrs2); } +:fabsq fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & opf=0xb & fqrs2 { fqrd = abs(fqrs2); } + +:fadds fsrs1,fsrs2,fsrd is op=0x2 & fsrd & op3=0x34 & fsrs1 & opf=0x41 & fsrs2 { fsrd = fsrs1 f+ fsrs2; } +:faddd fdrs1,fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & fdrs1 & opf=0x42 & fdrs2 { fdrd = fdrs1 f+ fdrs2; } +:faddq fqrs1,fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & fqrs1 & opf=0x43 & fqrs2 { fqrd = fqrs1 f+ fqrs2; } + +:fdivs fsrs1,fsrs2,fsrd is op=0x2 & fsrd & op3=0x34 & fsrs1 & opf=0x4d & fsrs2 { fsrd = fsrs1 f/ fsrs2; } +:fdivd fdrs1,fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & fdrs1 & opf=0x4e & fdrs2 { fdrd = fdrs1 f/ fdrs2; } +:fdivq fqrs1,fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & fqrs1 & opf=0x4f & fqrs2 { fqrd = fqrs1 f/ fqrs2; } + +:fdmulq fdrs1,fdrs2,fqrd is op=0x2 & fqrd & op3=0x34 & fdrs1 & opf=0x6e & fdrs2 { + tmp1:16 = float2float(fdrs1); + tmp2:16 = float2float(fdrs2); + fqrd = tmp1 f* tmp2; +} +:fsmuld fsrs1,fsrs2,fdrd is op=0x2 & fdrd & op3=0x34 & fsrs1 & opf=0x69 & fsrs2 { + tmp1:8 = float2float(fsrs1); + tmp2:8 = float2float(fsrs2); + fdrd = tmp1 f* tmp2; +} + +:fitos fsrs2,fsrd is op=0x2 & fsrd & op3=0x34 & opf=0xc4 & fsrs2 { fsrd = int2float(fsrs2); } +:fitod fsrs2,fdrd is op=0x2 & fdrd & op3=0x34 & opf=0xc8 & fsrs2 { fdrd = int2float(fsrs2); } +:fitoq fsrs2,fqrd is op=0x2 & fqrd & op3=0x34 & opf=0xcc & fsrs2 { fqrd = int2float(fsrs2); } + +:fmovs fsrs2,fsrd is op=0x2 & fsrd & op3=0x34 & opf=0x1 & fsrs2 { fsrd = fsrs2; } +:fmovd fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & opf=0x2 & fdrs2 { fdrd = fdrs2; } +:fmovq fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & opf=0x3 & fqrs2 { fqrd = fqrs2; } + +:fmuls fsrs1,fsrs2,fsrd is op=0x2 & fsrd & op3=0x34 & fsrs1 & opf=0x49 & fsrs2 { fsrd = fsrs1 f* fsrs2; } +:fmuld fdrs1,fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & fdrs1 & opf=0x4a & fdrs2 { fdrd = fdrs1 f* fdrs2; } +:fmulq fqrs1,fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & fqrs1 & opf=0x4b & fqrs2 { fqrd = fqrs1 f* fqrs2; } + +:fnegs fsrs2,fsrd is op=0x2 & fsrd & op3=0x34 & opf=0x5 & fsrs2 { fsrd = f- fsrs2; } +:fnegd fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & opf=0x6 & fdrs2 { fdrd = f- fdrs2; } +:fnegq fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & opf=0x7 & fqrs2 { fqrd = f- fqrs2; } + +:fsubs fsrs1,fsrs2,fsrd is op=0x2 & fsrd & op3=0x34 & fsrs1 & opf=0x45 & fsrs2 { fsrd = fsrs1 f- fsrs2; } +:fsubd fdrs1,fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & fdrs1 & opf=0x46 & fdrs2 { fdrd = fdrs1 f- fdrs2; } +:fsubq fqrs1,fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & fqrs1 & opf=0x47 & fqrs2 { fqrd = fqrs1 f- fqrs2; } + +:fxtos fdrs2,fsrd is op=0x2 & fsrd & op3=0x34 & opf=0x84 & fdrs2 { fsrd = int2float(fdrs2); } +:fxtod fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & opf=0x88 & fdrs2 { fdrd = int2float(fdrs2); } +:fxtoq fdrs2,fqrd is op=0x2 & fqrd & op3=0x34 & opf=0x8c & fdrs2 { fqrd = int2float(fdrs2); } + +:fstoi fsrs2,fsrd is op=0x2 & fsrd & op3=0x34 & opf=0xd1 & fsrs2 { fsrd = trunc(fsrs2); } +:fdtoi fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & opf=0xd2 & fdrs2 { fdrd = trunc(fdrs2); } +:fqtoi fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & opf=0xd3 & fqrs2 { fqrd = trunc(fqrs2); } + +:fstox fsrs2,fsrd is op=0x2 & fsrd & op3=0x34 & opf=0x81 & fsrs2 { fsrd = trunc(fsrs2); } +:fdtox fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & opf=0x82 & fdrs2 { fdrd = trunc(fdrs2); } +:fqtox fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & opf=0x83 & fqrs2 { fqrd = trunc(fqrs2); } + +:fstod fsrs2,fdrd is op=0x2 & fdrd & op3=0x34 & opf=0xc9 & fsrs2 { fdrd = float2float(fsrs2); } +:fstoq fsrs2,fqrd is op=0x2 & fqrd & op3=0x34 & opf=0xcd & fsrs2 { fqrd = float2float(fsrs2); } + +:fdtos fdrs2,fsrd is op=0x2 & fsrd & op3=0x34 & opf=0xc6 & fdrs2 { fsrd = float2float(fdrs2); } +:fdtoq fdrs2,fqrd is op=0x2 & fqrd & op3=0x34 & opf=0xce & fdrs2 { fqrd = float2float(fdrs2); } + +:fqtos fdrs2,fsrd is op=0x2 & fsrd & op3=0x34 & opf=0xc7 & fdrs2 { fsrd = float2float(fdrs2); } +:fqtod fqrs2,fdrd is op=0x2 & fdrd & op3=0x34 & opf=0xcb & fqrs2 { fdrd = float2float(fqrs2); } + +:fsqrts fsrs2,fsrd is op=0x2 & fsrd & op3=0x34 & opf=0x29 & fsrs2 { fsrd = sqrt(fsrs2); } +:fsqrtd fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & opf=0x2a & fdrs2 { fdrd = sqrt(fdrs2); } +:fsqrtq fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & opf=0x2b & fqrs2 { fqrd = sqrt(fqrs2); } + +:ld ea,fsrd is op=3 & fsrd & op3=0x20 & ea { fsrd = *:4 ea; } +:ldd ea,fdrd is op=3 & fdrd & op3=0x23 & ea { fdrd = *:8 ea; } +:ldq ea,fqrd is op=3 & fqrd & op3=0x22 & ea { fqrd = *:16 ea; } +:ld ea,"%fsr" is op=3 & op3=0x21 & rd=0 & ea { fsr = *:2 ea; } +:ldx ea,"%fsr" is op=3 & op3=0x21 & rd=1 & ea { fsr = *:2 ea; } + +:lda ea_alt,fsrd is op=3 & fsrd & op3=0x30 & ea_alt { fsrd = *:4 ea_alt; } +:ldda ea_alt,fdrd is op=3 & fdrd & op3=0x33 & ea_alt { fdrd = *:8 ea_alt; } +:ldqa ea_alt,fqrd is op=3 & fqrd & op3=0x32 & ea_alt { fqrd = *:16 ea_alt; } + +:st fsrd,ea is op=3 & fsrd & op3=0x24 & ea { *ea = fsrd:4; } +:std fdrd,ea is op=3 & fdrd & op3=0x27 & ea { *ea = fdrd:8; } +:stq fqrd,ea is op=3 & fqrd & op3=0x26 & ea { *ea = fqrd:16; } +:st "%fsr",ea is op=3 & op3=0x25 & rd=0 & ea { *ea = fsr; } +:stx "%fsr",ea is op=3 & op3=0x25 & rd=1 & ea { *ea = fsr; } + +:sta fsrd,ea_alt is op=3 & fsrd & op3=0x34 & ea_alt { *ea_alt = fsrd:4; } +:stda fdrd,ea_alt is op=3 & fdrd & op3=0x37 & ea_alt { *ea_alt = fdrd:8; } +:stqa fqrd,ea_alt is op=3 & fqrd & op3=0x36 & ea_alt { *ea_alt = fqrd:16; } + +fcc0_or_fccn: is op2=6 { export fcc0; } +fcc0_or_fccn: is op2=5 & fccn { export fccn; } + +fcc: "u" is cond=0x7 & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 3); export tmp; } +fcc: "g" is cond=0x6 & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 2); export tmp; } +fcc: "ug" is cond=0x5 & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 2 || fcc0_or_fccn == 3); export tmp; } +fcc: "l" is cond=0x4 & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 1); export tmp; } +fcc: "ul" is cond=0x3 & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 1 || fcc0_or_fccn ==3); export tmp; } +fcc: "lg" is cond=0x2 & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 1 || fcc0_or_fccn ==2); export tmp; } +fcc: "ne" is cond=0x1 & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 1 || fcc0_or_fccn == 2 || fcc0_or_fccn ==3); export tmp; } +fcc: "e" is cond=0x9 & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 0); export tmp; } +fcc: "ue" is cond=0xa & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 0 || fcc0_or_fccn == 3); export tmp; } +fcc: "ge" is cond=0xb & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 0 || fcc0_or_fccn == 2); export tmp; } +fcc: "uge" is cond=0xc & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 0 || fcc0_or_fccn == 2 || fcc0_or_fccn == 3); export tmp; } +fcc: "le" is cond=0xd & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 0 || fcc0_or_fccn == 1); export tmp; } +fcc: "ule" is cond=0xe & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 0 || fcc0_or_fccn == 1 || fcc0_or_fccn ==3); export tmp; } +fcc: "o" is cond=0xf & fcc0_or_fccn { tmp:1=(fcc0_or_fccn == 0 || fcc0_or_fccn == 1 || fcc0_or_fccn ==2); export tmp; } + +:fba reloff is op=0x0 & op2=0x6 & a=0x0 & cond=0x8 & reloff { delayslot(1); goto reloff; } +:"fba,a" reloff is op=0x0 & op2=0x6 & a=0x1 & cond=0x8 & reloff { goto reloff; } + +:fbn reloff is op=0x0 & op2=0x6 & a=0x0 & cond=0x0 & reloff { } +:"fbn,a" reloff,skip is op=0x0 & op2=0x6 & a=0x1 & cond=0x0 & reloff & skip { goto skip; } + +:fb^fcc reloff is op=0x0 & op2=0x6 & a=0x0 & fcc & reloff { delayslot(1); if (fcc) goto reloff; } +:fb^fcc^",a" reloff is op=0x0 & op2=0x6 & a=0x1 & fcc & reloff { if (!fcc) goto inst_next; delayslot(1); goto reloff; } + +:fb^fcc^predict "%"fccn,reloff64 is op=0x0 & op2=0x5 & a=0x0 & fcc & reloff64 & predict & fccn { delayslot(1); if (fcc) goto reloff64; } +:fb^fcc^",a"^predict "%"^fccn,reloff64 is op=0x0 & op2=0x5 & a=0x1 & fcc & reloff64 & predict & fccn { if (!fcc) goto inst_next; delayslot(1); goto reloff64; } + +macro fcmp(f1, f2, fccn) { + # fcc value | relation + # 0 | f1 = f2 + # 1 | f1 < f2 + # 2 | f1 > f2 + # 3 | f1 or f2 NaN + fccn = (1*(f1 f< f2)) + (2*(f1 f> f2)) + (3*(nan(f1) || nan(f2))); +} + +:fcmps %fccn2,fsrs1,fsrs2 is op=0x2 & fpc=0 & fccn2 & op3=0x35 & opf=0x51 & fsrs1 & fsrs2 { fcmp(fsrs1, fsrs2, fccn2); } +:fcmpd %fccn2,fdrs1,fdrs2 is op=0x2 & fpc=0 & fccn2 & op3=0x35 & opf=0x52 & fdrs1 & fdrs2 { fcmp(fdrs1, fdrs2, fccn2); } +:fcmpq %fccn2,fqrs1,fqrs2 is op=0x2 & fpc=0 & fccn2 & op3=0x35 & opf=0x53 & fqrs1 & fqrs2 { fcmp(fqrs1, fqrs2, fccn2); } + +:fcmpes %fccn2,fsrs1,fsrs2 is op=0x2 & fpc=0 & fccn2 & op3=0x35 & opf=0x55 & fsrs1 & fsrs2 { fcmp(fsrs1, fsrs2, fccn2); } +:fcmped %fccn2,fdrs1,fdrs2 is op=0x2 & fpc=0 & fccn2 & op3=0x35 & opf=0x56 & fdrs1 & fdrs2 { fcmp(fdrs1, fdrs2, fccn2); } +:fcmpeq %fccn2,fqrs1,fqrs2 is op=0x2 & fpc=0 & fccn2 & op3=0x35 & opf=0x57 & fqrs1 & fqrs2 { fcmp(fqrs1, fqrs2, fccn2); } + +Z: is opf_cc=4 { export i_zf; } +Z: is opf_cc=6 { export x_zf; } + +C: is opf_cc=4 { export i_cf; } +C: is opf_cc=6 { export x_cf; } + +N: is opf_cc=4 { export i_nf; } +N: is opf_cc=6 { export x_nf; } + +V: is opf_cc=4 { export i_vf; } +V: is opf_cc=6 { export x_vf; } + +# floating-point move with integer condition codes +fmicc: "a" is cond4=0x8 { tmp:1=1; export tmp; } +fmicc: "n" is cond4=0x0 { tmp:1=0; export tmp; } +fmicc: "ne" is cond4=0x9 & Z { tmp:1=!Z; export tmp; } +fmicc: "e" is cond4=0x1 & Z { export Z; } +fmicc: "g" is cond4=0xa & Z & N & V { tmp:1=!(Z|(N^V)); export tmp; } +fmicc: "le" is cond4=0x2 & Z & N & V { tmp:1= (Z|(N^V)); export tmp; } +fmicc: "ge" is cond4=0xb & N & V { tmp:1=!(N^V); export tmp; } +fmicc: "l" is cond4=0x3 & N & V { tmp:1= (N^V); export tmp; } +fmicc: "gu" is cond4=0xc & C & Z { tmp:1=!(C|Z); export tmp; } +fmicc: "leu" is cond4=0x4 & C & Z { tmp:1= (C|Z); export tmp; } +fmicc: "cc" is cond4=0xd & C { tmp:1=!C; export tmp; } +fmicc: "cs" is cond4=0x5 & C { tmp:1=C; export tmp; } +fmicc: "pos" is cond4=0xe & N { tmp:1=!N; export tmp; } +fmicc: "neg" is cond4=0x6 & N { tmp:1=N; export tmp; } +fmicc: "vc" is cond4=0xf & V { tmp:1=!V; export tmp; } +fmicc: "vs" is cond4=0x7 & V { tmp:1=V; export tmp; } + +# floating-point move with floating-point condition codes +fmfcc: "a" is cond4=0x8 & fccn_4 { tmp:1=1:1; export tmp; } +fmfcc: "n" is cond4=0x0 & fccn_4 { tmp:1=0:1; export tmp; } +fmfcc: "u" is cond4=0x7 & fccn_4 { tmp:1=(fccn_4 == 3); export tmp; } +fmfcc: "g" is cond4=0x6 & fccn_4 { tmp:1=(fccn_4 == 2); export tmp; } +fmfcc: "ug" is cond4=0x5 & fccn_4 { tmp:1=(fccn_4 == 2 || fccn_4 == 3); export tmp; } +fmfcc: "l" is cond4=0x4 & fccn_4 { tmp:1=(fccn_4 == 1); export tmp; } +fmfcc: "ul" is cond4=0x3 & fccn_4 { tmp:1=(fccn_4 == 1 || fccn_4 ==3); export tmp; } +fmfcc: "lg" is cond4=0x2 & fccn_4 { tmp:1=(fccn_4 == 1 || fccn_4 ==2); export tmp; } +fmfcc: "ne" is cond4=0x1 & fccn_4 { tmp:1=(fccn_4 == 1 || fccn_4 == 2 || fccn_4 ==3); export tmp; } +fmfcc: "e" is cond4=0x9 & fccn_4 { tmp:1=(fccn_4 == 0); export tmp; } +fmfcc: "ue" is cond4=0xa & fccn_4 { tmp:1=(fccn_4 == 0 || fccn_4 == 3); export tmp; } +fmfcc: "ge" is cond4=0xb & fccn_4 { tmp:1=(fccn_4 == 0 || fccn_4 == 2); export tmp; } +fmfcc: "uge" is cond4=0xc & fccn_4 { tmp:1=(fccn_4 == 0 || fccn_4 == 2 || fccn_4 == 3); export tmp; } +fmfcc: "le" is cond4=0xd & fccn_4 { tmp:1=(fccn_4 == 0 || fccn_4 == 1); export tmp; } +fmfcc: "ule" is cond4=0xe & fccn_4 { tmp:1=(fccn_4 == 0 || fccn_4 == 1 || fccn_4 ==3); export tmp; } +fmfcc: "o" is cond4=0xf & fccn_4 { tmp:1=(fccn_4 == 0 || fccn_4 == 1 || fccn_4 ==2); export tmp; } + +fmfcc_or_fmicc: fmfcc is bit13=0 & fmfcc { export fmfcc; } +fmfcc_or_fmicc: fmicc is bit13=1 & fmicc { export fmicc; } + +fcc_icc_xcc: "%"^fccn_4 is bit13=0 & fccn_4 { } +fcc_icc_xcc: "%icc" is bit13=1 & opf_cc=4 { } +fcc_icc_xcc: "%xcc" is bit13=1 & opf_cc=6 { } + +:fmovs^fmfcc_or_fmicc fcc_icc_xcc,fsrs2,fsrd is op=2 & op3=0x35 & bit18=0 & fmfcc_or_fmicc & fcc_icc_xcc & opf_low=1 & fsrs2 & fsrd + { if !(fmfcc_or_fmicc) goto ; fsrd = fsrs2; } +:fmovd^fmfcc_or_fmicc fcc_icc_xcc,fdrs2,fdrd is op=2 & op3=0x35 & bit18=0 & fmfcc_or_fmicc & fcc_icc_xcc & opf_low=2 & fdrs2 & fdrd + { if !(fmfcc_or_fmicc) goto ; fdrd = fdrs2; } +:fmovq^fmfcc_or_fmicc fcc_icc_xcc,fqrs2,fqrd is op=2 & op3=0x35 & bit18=0 & fmfcc_or_fmicc & fcc_icc_xcc & opf_low=3 & fqrs2 & fqrd + { if !(fmfcc_or_fmicc) goto ; fqrd = fqrs2; } + +#conditional integer moves with integer conditions defined in constructor :mov^m_cc +:mov^fmfcc " %"^fccn_4,regorimm11,RD is op=2 & RD & op3=0x2c & bit18=0 & fmfcc & fccn_4 & regorimm11 +{ + if !(fmfcc) goto ; + RD = regorimm11; + +} + +fmovrcc: "z" is rcond3=0x1 & RS1 { tmp:1 = (RS1 == 0); export tmp; } +fmovrcc: "lez" is rcond3=0x2 & RS1 { tmp:1 = (RS1 s<= 0); export tmp; } +fmovrcc: "lz" is rcond3=0x3 & RS1 { tmp:1 = (RS1 s< 0); export tmp; } +fmovrcc: "nz" is rcond3=0x5 & RS1 { tmp:1 = (RS1 != 0); export tmp; } +fmovrcc: "gz" is rcond3=0x6 & RS1 { tmp:1 = (RS1 s> 0); export tmp; } +fmovrcc: "gez" is rcond3=0x7 & RS1 { tmp:1 = (RS1 s>= 0); export tmp; } + +:fmovrs^fmovrcc RS1,fsrs2,fsrd is op=2 & fsrd & op3=0x35 & bit13=0 & RS1 & fmovrcc & opf_low_5_9=0x5 & fsrs2 + { if !(fmovrcc) goto ; fsrd = fsrs2; } +:fmovrd^fmovrcc RS1,fdrs2,fdrd is op=2 & fdrd & op3=0x35 & bit13=0 & RS1 & fmovrcc & opf_low_5_9=0x6 & fdrs2 + { if !(fmovrcc) goto ; fdrd = fdrs2; } +:fmovrq^fmovrcc RS1,fqrs2,fqrd is op=2 & fqrd & op3=0x35 & bit13=0 & RS1 & fmovrcc & opf_low_5_9=0x7 & fqrs2 + { if !(fmovrcc) goto ; fqrd = fqrs2; } + +# Include support for the VIS1 vector instructions +@include "SparcVIS.sinc" diff --git a/python/icicle/Ghidra/Processors/Sparc/data/languages/SparcV9_32.cspec b/python/icicle/Ghidra/Processors/Sparc/data/languages/SparcV9_32.cspec new file mode 100644 index 0000000..28f5f30 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Sparc/data/languages/SparcV9_32.cspec @@ -0,0 +1,103 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Sparc/data/languages/SparcV9_32.slaspec b/python/icicle/Ghidra/Processors/Sparc/data/languages/SparcV9_32.slaspec new file mode 100644 index 0000000..c8c4fe1 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Sparc/data/languages/SparcV9_32.slaspec @@ -0,0 +1,4 @@ + +@define SIZE "4" + +@include "SparcV9.sinc" diff --git a/python/icicle/Ghidra/Processors/Sparc/data/languages/SparcV9_64.cspec b/python/icicle/Ghidra/Processors/Sparc/data/languages/SparcV9_64.cspec new file mode 100644 index 0000000..67ccac7 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Sparc/data/languages/SparcV9_64.cspec @@ -0,0 +1,190 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Sparc/data/languages/SparcV9_64.slaspec b/python/icicle/Ghidra/Processors/Sparc/data/languages/SparcV9_64.slaspec new file mode 100644 index 0000000..8b23b75 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Sparc/data/languages/SparcV9_64.slaspec @@ -0,0 +1,6 @@ +@define SIZE "8" + +@include "SparcV9.sinc" + + + diff --git a/python/icicle/Ghidra/Processors/Sparc/data/languages/SparcVIS.sinc b/python/icicle/Ghidra/Processors/Sparc/data/languages/SparcVIS.sinc new file mode 100644 index 0000000..f59e0da --- /dev/null +++ b/python/icicle/Ghidra/Processors/Sparc/data/languages/SparcVIS.sinc @@ -0,0 +1,445 @@ +# The Sparc VIS1 vector instruction set +# The opcodes below that have their pcodeop uncommented have been checked to make sure +# that the register width is correct. If the call to the pcodeop is still commented out +# that means that the register width may be incorrect. For example, a call to a 64 bit +# floating point register may really use a 32 bit register. +# VIS2 or VIS2+ instructions are not included in this file. + +define pcodeop alignaddr; +:alignaddr RS1,RS2,rd is opf = 0x18 & op3 = 0x36 & op = 0x2 & RS1 & RS2 & rd +{ + rd = alignaddr(RS1,RS2); +} + +define pcodeop alignaddrl; +:alignaddrl RS1,RS2,rd is opf = 0x1a & op3 = 0x36 & op = 0x2 & RS1 & RS2 & rd +{ + rd = alignaddrl(RS1,RS2); +} + +define pcodeop array16; +:array16 RS1,RS2,rd is opf = 0x12 & op3 = 0x36 & op = 0x2 & RS1 & RS2 & rd +{ + rd = array16(RS1,RS2); +} + +define pcodeop array32; +:array32 RS1,RS2,rd is opf = 0x14 & op3 = 0x36 & op = 0x2 & RS1 & RS2 & rd +{ + rd = array32(RS1,RS2); +} + +define pcodeop array8; +:array8 RS1,RS2,rd is opf = 0x10 & op3 = 0x36 & op = 0x2 & RS1 & RS2 & rd +{ + rd = array8(RS1,RS2); +} + +define pcodeop edge16cc; +:edge16cc RS1,RS2,rd is opf = 0x4 & op3 = 0x36 & op = 0x2 & RS1 & RS2 & rd +{ + rd = edge16cc(RS1,RS2); +} + +define pcodeop edge16lcc; +:edge16lcc RS1,RS2,rd is opf = 0x6 & op3 = 0x36 & op = 0x2 & RS1 & RS2 & rd +{ + rd = edge16lcc(RS1,RS2); +} + +define pcodeop edge32cc; +:edge32cc RS1,RS2,rd is opf = 0x8 & op3 = 0x36 & op = 0x2 & RS1 & RS2 & rd +{ + rd = edge32cc(RS1,RS2); +} + +define pcodeop edge32lcc; +:edge32lcc RS1,RS2,rd is opf = 0xa & op3 = 0x36 & op = 0x2 & RS1 & RS2 & rd +{ + rd = edge32lcc(RS1,RS2); +} + +define pcodeop edge8cc; +:edge8cc RS1,RS2,rd is opf = 0x0 & op3 = 0x36 & op = 0x2 & RS1 & RS2 & rd +{ + rd = edge8cc(RS1,RS2); +} + +define pcodeop edge8lcc; +:edge8lcc RS1,RS2,rd is opf = 0x2 & op3 = 0x36 & op = 0x2 & RS1 & RS2 & rd +{ + rd = edge8lcc(RS1,RS2); +} + +define pcodeop faligndata; +:faligndata fdrs1,fdrs2,fdrd is opf = 0x48 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = faligndata(fdrs1,fdrs2); +} + +define pcodeop fandd; +:fandd fdrs1,fdrs2,fdrd is opf = 0x70 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fandd(fdrs1,fdrs2); +} + +define pcodeop fandnot1d; +:fandnot1d fdrs1,fdrs2,fdrd is opf = 0x68 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fandnot1d(fdrs1,fdrs2); +} + +define pcodeop fandnot1s; +:fandnot1s fdrs1,fdrs2,fdrd is opf = 0x69 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fandnot1s(fdrs1,fdrs2); +} + +define pcodeop fandnot2d; +:fandnot2d fdrs1,fdrs2,fdrd is opf = 0x64 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fandnot2d(fdrs1,fdrs2); +} + +define pcodeop fandnot2s; +:fandnot2s fdrs1,fdrs2,fdrd is opf = 0x65 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fandnot2s(fdrs1,fdrs2); +} + +define pcodeop fands; +:fands fdrs1,fdrs2,fdrd is opf = 0x71 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fands(fdrs1,fdrs2); +} + +define pcodeop fexpand; +:fexpand fsrs2,fdrd is opf = 0x4d & op3 = 0x36 & op = 0x2 & fsrs2 & fdrd +{ + fdrd = fexpand(fsrs2); +} + +define pcodeop fmul8sux16; +:fmul8sux16 fdrs1,fdrs2,fdrd is opf = 0x36 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fmul8sux16(fdrs1,fdrs2); +} + +define pcodeop fmul8ulx16; +:fmul8ulx16 fdrs1,fdrs2,fdrd is opf = 0x37 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fmul8ulx16(fdrs1,fdrs2); +} + +define pcodeop fmul8x16; +:fmul8x16 fdrs1,fdrs2,fdrd is opf = 0x31 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fmul8x16(fdrs1,fdrs2); +} + +define pcodeop fmul8x16al; +:fmul8x16al fdrs1,fdrs2,fdrd is opf = 0x35 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fmul8x16al(fdrs1,fdrs2); +} + +define pcodeop fmul8x16au; +:fmul8x16au fdrs1,fdrs2,fdrd is opf = 0x33 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fmul8x16au(fdrs1,fdrs2); +} + +define pcodeop fmuld8sux16; +:fmuld8sux16 fdrs1,fdrs2,fdrd is opf = 0x38 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fmuld8sux16(fdrs1,fdrs2); +} + +define pcodeop fmuld8ulx16; +:fmuld8ulx16 fdrs1,fdrs2,fdrd is opf = 0x39 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fmuld8ulx16(fdrs1,fdrs2); +} + +define pcodeop fnandd; +:fnandd fdrs1,fdrs2,fdrd is opf = 0x6e & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fnandd(fdrs1,fdrs2); +} + +define pcodeop fnands; +:fnands fdrs1,fdrs2,fdrd is opf = 0x6f & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fnands(fdrs1,fdrs2); +} + +define pcodeop fnord; +:fnord fdrs1,fdrs2,fdrd is opf = 0x62 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fnord(fdrs1,fdrs2); +} + +define pcodeop fnors; +:fnors fdrs1,fdrs2,fdrd is opf = 0x63 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fnors(fdrs1,fdrs2); +} + +define pcodeop fnot1d; +:fnot1d fdrs1,fdrd is opf = 0x6a & op3 = 0x36 & op = 0x2 & fdrs1 & fdrd +{ + fdrd = fnot1d(fdrs1); +} + +define pcodeop fnot1s; +:fnot1s fdrs1,fdrd is opf = 0x6b & op3 = 0x36 & op = 0x2 & fdrs1 & fdrd +{ + fdrd = fnot1s(fdrs1); +} + +define pcodeop fnot2d; +:fnot2d fdrs2,fdrd is opf = 0x66 & op3 = 0x36 & op = 0x2 & fdrs2 & fdrd +{ + fdrd = fnot2d(fdrs2); +} + +define pcodeop fnot2s; +:fnot2s fdrs2,fdrd is opf = 0x67 & op3 = 0x36 & op = 0x2 & fdrs2 & fdrd +{ + fdrd = fnot2s(fdrs2); +} + +define pcodeop foned; +:foned fdrd is opf = 0x7e & op3 = 0x36 & op = 0x2 & fdrd +{ + fdrd = foned(); +} + +define pcodeop fones; +:fones fsrd is opf = 0x7f & op3 = 0x36 & op = 0x2 & fsrd +{ + fsrd = fones(); +} + +define pcodeop ford; +:ford fdrs1,fdrs2,fdrd is opf = 0x7c & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = ford(fdrs1,fdrs2); +} + +define pcodeop fornot1d; +:fornot1d fdrs1,fdrs2,fdrd is opf = 0x7a & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fornot1d(fdrs1,fdrs2); +} + +define pcodeop fornot1s; +:fornot1s fdrs1,fdrs2,fdrd is opf = 0x7b & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fornot1s(fdrs1,fdrs2); +} + +define pcodeop fornot2d; +:fornot2d fdrs1,fdrs2,fdrd is opf = 0x76 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fornot2d(fdrs1,fdrs2); +} + +define pcodeop fornot2s; +:fornot2s fdrs1,fdrs2,fdrd is opf = 0x77 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fornot2s(fdrs1,fdrs2); +} + +define pcodeop fors; +:fors fdrs1,fdrs2,fdrd is opf = 0x7d & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fors(fdrs1,fdrs2); +} + +define pcodeop fpack16; +:fpack16 fdrs2,fsrd is opf = 0x3b & op3=0x36 & op = 0x2 & fdrs2 & fsrd +{ + fsrd = fpack16(fdrs2); +} + +define pcodeop fpack32; +:fpack32 fdrs1,fdrs2,fdrd is opf = 0x3a & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fpack32(fdrs1,fdrs2); +} + +define pcodeop fpackfix; +:fpackfix fdrs2,fsrd is opf = 0x3d & op3 = 0x36 & op = 0x2 & fdrs2 & fsrd +{ + fsrd = fpackfix(fdrs2); +} + +define pcodeop fpadd16; +:fpadd16 fdrs1,fdrs2,fdrd is opf = 0x50 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fpadd16(fdrs1,fdrs2); +} + +define pcodeop fpadd16s; +:fpadd16s fdrs1,fdrs2,fdrd is opf = 0x51 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fpadd16s(fdrs1,fdrs2); +} + +define pcodeop fpadd32; +:fpadd32 fdrs1,fdrs2,fdrd is opf = 0x52 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fpadd32(fdrs1,fdrs2); +} + +define pcodeop fpadd32s; +:fpadd32s fdrs1,fdrs2,fdrd is opf = 0x53 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fpadd32s(fdrs1,fdrs2); +} + +define pcodeop fpcmpeq16; +:fpcmpeq16 fdrs1,fdrs2,rd is opf = 0x2a & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & rd +{ + rd = fpcmpeq16(fdrs1,fdrs2); +} + +define pcodeop fpcmpeq32; +:fpcmpeq32 fdrs1,fdrs2,rd is opf = 0x2e & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & rd +{ + rd = fpcmpeq32(fdrs1,fdrs2); +} + +define pcodeop fpcmpgt16; +:fpcmpgt16 fdrs1,fdrs2,rd is opf = 0x28 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & rd +{ + rd = fpcmpgt16(fdrs1,fdrs2); +} + +define pcodeop fpcmpgt32; +:fpcmpgt32 fdrs1,fdrs2,rd is opf = 0x2c & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & rd +{ + rd = fpcmpgt32(fdrs1,fdrs2); +} + +define pcodeop fpcmple16; +:fpcmple16 fdrs1,fdrs2,rd is opf = 0x20 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & rd +{ + rd = fpcmple16(fdrs1,fdrs2); +} + +define pcodeop fpcmple32; +:fpcmple32 fdrs1,fdrs2,rd is opf = 0x24 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & rd +{ + rd = fpcmple32(fdrs1,fdrs2); +} + +define pcodeop fpcmpne16; +:fpcmpne16 fdrs1,fdrs2,rd is opf = 0x22 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & rd +{ + rd = fpcmpne16(fdrs1,fdrs2); +} + +define pcodeop fpcmpne32; +:fpcmpne32 fdrs1,fdrs2,rd is opf = 0x26 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & rd +{ + rd = fpcmpne32(fdrs1,fdrs2); +} + +define pcodeop fpmerge; +:fpmerge fdrs1,fdrs2,fdrd is opf = 0x4b & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fpmerge(fdrs1,fdrs2); +} + +define pcodeop fpsub16; +:fpsub16 fdrs1,fdrs2,fdrd is opf = 0x54 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fpsub16(fdrs1,fdrs2); +} + +define pcodeop fpsub16s; +:fpsub16s fdrs1,fdrs2,fdrd is opf = 0x55 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fpsub16s(fdrs1,fdrs2); +} + +define pcodeop fpsub32; +:fpsub32 fdrs1,fdrs2,fdrd is opf = 0x56 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fpsub32(fdrs1,fdrs2); +} + +define pcodeop fpsub32s; +:fpsub32s fdrs1,fdrs2,fdrd is opf = 0x57 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fpsub32s(fdrs1,fdrs2); +} + +define pcodeop fsrc1d; +:fsrc1d fdrs1,fdrd is opf = 0x74 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrd +{ + fdrd = fsrc1d(fdrs1); +} + +define pcodeop fsrc1s; +:fsrc1s fdrs1,fdrd is opf = 0x75 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrd +{ + fdrd = fsrc1s(fdrs1); +} + +define pcodeop fsrc2d; +:fsrc2d fdrs2,fdrd is opf = 0x78 & op3 = 0x36 & op = 0x2 & fdrs2 & fdrd +{ + fdrd = fsrc2d(fdrs2); +} + +define pcodeop fsrc2s; +:fsrc2s fdrs2,fdrd is opf = 0x79 & op3 = 0x36 & op = 0x2 & fdrs2 & fdrd +{ + fdrd = fsrc2s(fdrs2); +} + +define pcodeop fxnord; +:fxnord fdrs1,fdrs2,fdrd is opf = 0x72 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fxnord(fdrs1,fdrs2); +} + +define pcodeop fxnors; +:fxnors fdrs1,fdrs2,fdrd is opf = 0x73 & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fxnors(fdrs1,fdrs2); +} + +define pcodeop fxord; +:fxord fdrs1,fdrs2,fdrd is opf = 0x6c & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fxord(fdrs1,fdrs2); +} + +define pcodeop fxors; +:fxors fdrs1,fdrs2,fdrd is opf = 0x6d & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = fxors(fdrs1,fdrs2); +} + +define pcodeop fzerod; +:fzerod fdrd is opf = 0x60 & op3 = 0x36 & op = 0x2 & fdrd +{ + fdrd = fzerod(); +} + +define pcodeop fzeros; +:fzeros fsrd is opf = 0x61 & op3 = 0x36 & op = 0x2 & fsrd +{ + fsrd = fzeros(); +} + +define pcodeop pdist; +:pdist fdrs1,fdrs2,fdrd is opf = 0x3e & op3 = 0x36 & op = 0x2 & fdrs1 & fdrs2 & fdrd +{ + fdrd = pdist(fdrs1,fdrs2); +} + diff --git a/python/icicle/Ghidra/Processors/SuperH/data/languages/sh-1.slaspec b/python/icicle/Ghidra/Processors/SuperH/data/languages/sh-1.slaspec new file mode 100644 index 0000000..b8ca66c --- /dev/null +++ b/python/icicle/Ghidra/Processors/SuperH/data/languages/sh-1.slaspec @@ -0,0 +1,4 @@ + +@define SH_VERSION "1" + +@include "superh.sinc" diff --git a/python/icicle/Ghidra/Processors/SuperH/data/languages/sh-2.slaspec b/python/icicle/Ghidra/Processors/SuperH/data/languages/sh-2.slaspec new file mode 100644 index 0000000..aaa0eea --- /dev/null +++ b/python/icicle/Ghidra/Processors/SuperH/data/languages/sh-2.slaspec @@ -0,0 +1,3 @@ +@define SH_VERSION "2" + +@include "superh.sinc" diff --git a/python/icicle/Ghidra/Processors/SuperH/data/languages/sh-2a.slaspec b/python/icicle/Ghidra/Processors/SuperH/data/languages/sh-2a.slaspec new file mode 100644 index 0000000..9f0d999 --- /dev/null +++ b/python/icicle/Ghidra/Processors/SuperH/data/languages/sh-2a.slaspec @@ -0,0 +1,4 @@ +@define SH_VERSION "2A" +@define FPU "1" + +@include "superh.sinc" diff --git a/python/icicle/Ghidra/Processors/SuperH/data/languages/superh.cspec b/python/icicle/Ghidra/Processors/SuperH/data/languages/superh.cspec new file mode 100644 index 0000000..2a06d7a --- /dev/null +++ b/python/icicle/Ghidra/Processors/SuperH/data/languages/superh.cspec @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/SuperH/data/languages/superh.ldefs b/python/icicle/Ghidra/Processors/SuperH/data/languages/superh.ldefs new file mode 100644 index 0000000..c105dbd --- /dev/null +++ b/python/icicle/Ghidra/Processors/SuperH/data/languages/superh.ldefs @@ -0,0 +1,37 @@ + + + + + SuperH SH-2A processor 32-bit big-endian + + + + SuperH SH-2 processor 32-bit big-endian + + + + SuperH SH-1 processor 32-bit big-endian + + + diff --git a/python/icicle/Ghidra/Processors/SuperH/data/languages/superh.pspec b/python/icicle/Ghidra/Processors/SuperH/data/languages/superh.pspec new file mode 100644 index 0000000..114b5c4 --- /dev/null +++ b/python/icicle/Ghidra/Processors/SuperH/data/languages/superh.pspec @@ -0,0 +1,5 @@ + + + + + diff --git a/python/icicle/Ghidra/Processors/SuperH/data/languages/superh.sinc b/python/icicle/Ghidra/Processors/SuperH/data/languages/superh.sinc new file mode 100644 index 0000000..ba58154 --- /dev/null +++ b/python/icicle/Ghidra/Processors/SuperH/data/languages/superh.sinc @@ -0,0 +1,2410 @@ +# All assembly defintions taken from: http://www.shared-ptr.com/sh_insns.html + +define endian=big; + +define alignment=1; + +define space ram type=ram_space size=4 wordsize=1 default; +define space register type=register_space size=4; + +define register offset=0 size=4 +[r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15]; + +define register offset=0x100 size=4 [sr gbr vbr mach macl pr pc]; + + +@if SH_VERSION == "2A" +define register offset=0x180 size=4 [tbr]; +@endif + +# SR Flags +@define T_FLAG "sr[0,1]" +@define S_FLAG "sr[1,1]" +@define I0_FLAG "sr[4,1]" +@define I1_FLAG "sr[5,1]" +@define I2_FLAG "sr[6,1]" +@define I3_FLAG "sr[7,1]" +@define Q_FLAG "sr[8,1]" +@define M_FLAG "sr[9,1]" +@define CS_FLAG "sr[13,1]" +@define BO_FLAG "sr[14,1]" + +@if defined(FPU) + +# Floating-Point Registers +define register offset=0x200 size=4 [ fr0 fr1 fr2 fr3 fr4 fr5 fr6 fr7 fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15 ]; +define register offset=0x200 size=8 [ dr0 dr2 dr4 dr6 dr8 dr10 dr12 dr14 ]; + +# Floating-Point System Registers +define register offset=0x300 size=4 [fpscr fpul]; + +# FPSCR Flags (initial value = H'0004 0001) +@define FP_RM "fpscr[0,2]" +@define FP_FLAG "fpscr[2,5]" +@define FP_ENABLE "fpscr[7,5]" +@define FP_CAUSE "fpscr[12,6]" +@define FP_DN "fpscr[18,1]" +@define FP_PR "fpscr[19,1]" +@define FP_SZ "fpscr[20,1]" +@define FP_QIS "fpscr[22,1]" + +@endif + +@if SH_VERSION == "2A" +# The register banks space is defined below, there are 512 banks, each is 80 bytes long +define register offset=0x10000 size=40960 [ resbank_base ]; +@endif + +define token instr16(16) + disp_00_03 = (0, 3) + sdisp_00_03 = (0, 3) signed + disp_00_07 = (0, 7) + sdisp_00_07 = (0, 7) signed + disp_00_11 = (0, 11) + sdisp_00_11 = (0, 11) signed + imm3_00_02 = (0, 2) + imm_00_07 = (0, 7) + simm_00_07 = (0, 7) signed + opcode_00_03 = (0, 3) + opcode_00_07 = (0, 7) + opcode_00_15 = (0, 15) + opcode_03_03 = (3, 3) + opcode_04_07 = (4, 7) + opcode_08_11 = (8, 11) + opcode_08_15 = (8, 15) + opcode_12_15 = (12, 15) + rm_04_07 = (4, 7) + rm_08_11 = (8, 11) + rn_04_07 = (4, 7) + rn_08_11 = (8, 11) + rm_imm_08_11 = (8, 11) + rn_imm_08_11 = (8, 11) +; + +@if SH_VERSION == "2A" +define token instr32(32) + l_disp_00_11 = (0, 11) + l_opcode_12_15 = (12, 15) + l_opcode_16_19 = (16, 19) + l_opcode_23_23 = (23, 23) + l_opcode_24_31 = (24, 31) + l_rm_20_23 = (20, 23) + l_rn_24_27 = (24, 27) + l_opcode_28_31 = (28, 31) + l_imm20_00_15 = (0, 15) + l_simm20_20_23 = (20, 23) signed + l_imm3_20_22 = (20, 22) +; + +attach variables [ l_rn_24_27 l_rm_20_23 ] [ + r0 r1 r2 r3 r4 r5 r6 r7 + r8 r9 r10 r11 r12 r13 r14 r15 +]; + +@endif + +attach variables [ rm_04_07 rm_08_11 rn_04_07 rn_08_11 ] [ + r0 r1 r2 r3 r4 r5 r6 r7 + r8 r9 r10 r11 r12 r13 r14 r15 +]; + +attach names [ rm_imm_08_11 rn_imm_08_11 ] [ + r0 r1 r2 r3 r4 r5 r6 r7 + r8 r9 r10 r11 r12 r13 r14 pr +]; + +@if defined(FPU) + +define token finstr16(16) + fop_00_07 = (0, 7) + fop_00_03 = (0, 3) + fop_04_07 = (4, 7) + fop_12_15 = (12, 15) + fop_08_08 = (8, 8) + fop_04_04 = (4, 4) + fop_00_15 = (0, 15) + + ffrn_08_11 = (8, 11) + ffrm_08_11 = (8, 11) + ffrn_04_07 = (4, 7) + ffrm_04_07 = (4, 7) + f_rm_04_07 = (4, 7) + f_rn_08_11 = (8, 11) + + fdrn_09_11 = (9, 11) + fdrm_09_11 = (9, 11) + fdrn_05_07 = (5, 7) + fdrm_05_07 = (5, 7) +; + + +define token finstr32(32) + lfdisp_00_11 = (0, 11) + lfop_28_31 = (28, 31) + lfop_12_19 = (12, 19) + lffrm_24_27 = (24, 27) + lffrn_24_27 = (24, 27) + lffrm_20_23 = (20, 23) + lf_rm_20_23 = (20, 23) + lf_rn_24_27 = (24, 27) + lffrn_20_23 = (20, 23) +; + +attach variables [ ffrn_08_11 ffrm_08_11 ffrn_04_07 ffrm_04_07 lffrm_24_27 lffrn_24_27 lffrm_20_23 lffrn_20_23 ] +[fr0 fr1 fr2 fr3 fr4 fr5 fr6 fr7 fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15]; + +attach variables [ f_rm_04_07 f_rn_08_11 lf_rm_20_23 lf_rn_24_27 ] +[r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15]; + +attach variables [ fdrn_09_11 fdrm_09_11 fdrn_05_07 fdrm_05_07 ] +[dr0 dr2 dr4 dr6 dr8 dr10 dr12 dr14]; + +@endif + + +# helpers for branch +target00_07: target is sdisp_00_07 [ target = (sdisp_00_07 << 1) + inst_start + 4; ] { + export *:4 target; +} + +target00_11: target is sdisp_00_11 [ target = (sdisp_00_11 << 1) + inst_start + 4; ] { + export *:4 target; +} + + +# +# Data Transfer Instructions +# + +:mov rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0011 +{ + rn_08_11 = rm_04_07; +} + +imm8: "#"^simm_00_07 is simm_00_07 { export *[const]:4 simm_00_07; } + +:mov imm8,rn_08_11 is opcode_12_15=0b1110 & rn_08_11 & imm8 +{ + rn_08_11 = imm8; +} + +disppc4: @(disp,pc) is disp_00_07 & pc + [ disp = (disp_00_07 << 2) + ((inst_start + 4) & 0xfffffffc); ] + { local tmp:4 = disp; export tmp; } + +disppc2: @(disp,pc) is disp_00_07 & pc + [ disp = (disp_00_07 << 1) + (inst_start + 4); ] + { local tmp:4 = disp; export tmp; } + +:mova disppc4,r0 is r0 & opcode_08_15=0b11000111 & disppc4 +{ + r0 = disppc4; +} + +:mov.w disppc2,rn_08_11 is opcode_12_15=0b1001 & rn_08_11 & disppc2 +{ + rn_08_11 = sext(*:2 disppc2); +} + +:mov.l disppc4,rn_08_11 is opcode_12_15=0b1101 & rn_08_11 & disppc4 +{ + rn_08_11 = *:4 disppc4; +} + +:mov.b @rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0000 +{ + rn_08_11 = sext(*:1 rm_04_07); +} + +:mov.w @rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0001 +{ + rn_08_11 = sext(*:2 rm_04_07); +} + +:mov.l @rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0010 +{ + rn_08_11 = *:4 rm_04_07; +} + +:mov.b rm_04_07,@rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0000 +{ + *:1 rn_08_11 = rm_04_07:1; +} + +:mov.w rm_04_07,@rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0001 +{ + *:2 rn_08_11 = rm_04_07:2; +} + +:mov.l rm_04_07,@rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0010 +{ + *:4 rn_08_11 = rm_04_07; +} + +# the following two instructions share the same opcodes but differ if rm == rn +:mov.b @rm_04_07+,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0100 & (opcode_04_07=opcode_08_11) +{ + rn_08_11 = sext(*:1 rm_04_07); +} + +:mov.b @rm_04_07+,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0100 +{ + rn_08_11 = sext(*:1 rm_04_07); + rm_04_07 = rm_04_07 + 1; +} + +# the following two instructions share the same opcodes but differ if rm == rn +:mov.w @rm_04_07+,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0101 & (opcode_04_07=opcode_08_11) +{ + rn_08_11 = sext(*:2 rm_04_07); +} + +:mov.w @rm_04_07+,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0101 & opcode_04_07 & opcode_08_11 +{ + rn_08_11 = sext(*:2 rm_04_07); + rm_04_07 = rm_04_07 + 2; +} + +# the following two instructions share the same opcodes but differ if rm == rn +:mov.l @rm_04_07+,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0110 & (opcode_04_07=opcode_08_11) +{ + rn_08_11 = *:4 rm_04_07; +} + +:mov.l @rm_04_07+,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0110 & opcode_04_07 & opcode_08_11 +{ + rn_08_11 = *:4 rm_04_07; + rm_04_07 = rm_04_07 + 4; +} + +:mov.b rm_04_07,@-rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0100 +{ + rn_08_11 = rn_08_11 -1; + *:1 rn_08_11 = rm_04_07; +} + +:mov.w rm_04_07,@-rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0101 +{ + rn_08_11 = rn_08_11 -2; + *:2 rn_08_11 = rm_04_07; +} + +:mov.l rm_04_07,@-rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0110 +{ + rn_08_11 = rn_08_11 -4; + *:4 rn_08_11 = rm_04_07; +} + +:mov.b @(disp_00_03,rm_04_07),r0 is r0 & opcode_08_15=0b10000100 & rm_04_07 & disp_00_03 +{ + r0 = sext(*:1 (disp_00_03 + rm_04_07)); +} + +:mov.w @(disp,rm_04_07),r0 is r0 & opcode_08_15=0b10000101 & rm_04_07 & disp_00_03 [ disp = disp_00_03 << 1; ] +{ + r0 = sext(*:2 (disp + rm_04_07)); +} + +:mov.l @(disp,rm_04_07),rn_08_11 is opcode_12_15=0b0101 & rn_08_11 & rm_04_07 & disp_00_03 [ disp = disp_00_03 << 2; ] +{ + rn_08_11 = *:4 (disp + rm_04_07); +} + +:mov.b r0,@(disp_00_03,rn_04_07) is r0 & opcode_08_15=0b10000000 & rn_04_07 & disp_00_03 +{ + *:1 (rn_04_07 + disp_00_03) = r0:1; +} + +:mov.w r0,@(disp,rn_04_07) is r0 & opcode_08_15=0b10000001 & rn_04_07 & disp_00_03 [ disp = disp_00_03 << 1; ] +{ + *:2 (rn_04_07 + disp) = r0:2; +} + +:mov.l rm_04_07,@(disp,rn_08_11) is opcode_12_15=0b0001 & rn_08_11 & rm_04_07 & disp_00_03 [ disp = disp_00_03 << 2; ] +{ + *:4 (rn_08_11 + disp) = rm_04_07; +} + +:mov.b @(r0,rm_04_07),rn_08_11 is r0 & opcode_12_15=0b0000 & rn_08_11 & rm_04_07 & opcode_00_03=0b1100 +{ + rn_08_11 = sext(*:1 (rm_04_07 + r0)); +} + +:mov.w @(r0,rm_04_07),rn_08_11 is r0 & opcode_12_15=0b0000 & rn_08_11 & rm_04_07 & opcode_00_03=0b1101 +{ + rn_08_11 = sext(*:2 (rm_04_07 + r0)); +} + +:mov.l @(r0,rm_04_07),rn_08_11 is r0 & opcode_12_15=0b0000 & rn_08_11 & rm_04_07 & opcode_00_03=0b1110 +{ + rn_08_11 = *:4 (rm_04_07 + r0); +} + +:mov.b rm_04_07,@(r0,rn_08_11) is r0 & opcode_12_15=0b0000 & rn_08_11 & rm_04_07 & opcode_00_03=0b0100 +{ + *:1 (rn_08_11 + r0) = rm_04_07:1; +} + +:mov.w rm_04_07,@(r0,rn_08_11) is r0 & opcode_12_15=0b0000 & rn_08_11 & rm_04_07 & opcode_00_03=0b0101 +{ + *:2 (rn_08_11 + r0) = rm_04_07:2; +} + +:mov.l rm_04_07,@(r0,rn_08_11) is r0 & opcode_12_15=0b0000 & rn_08_11 & rm_04_07 & opcode_00_03=0b0110 +{ + *:4 (rn_08_11 + r0) = rm_04_07:4; +} + +:mov.b @(disp_00_07,gbr),r0 is gbr & r0 & opcode_08_15=0b11000100 & disp_00_07 +{ + r0 = sext(*:1 (gbr + disp_00_07)); +} + +:mov.w @(disp,gbr),r0 is gbr & r0 & opcode_08_15=0b11000101 & disp_00_07 [disp = (disp_00_07 << 1); ] +{ + r0 = sext(*:2 (gbr + disp)); +} + +:mov.l @(disp,gbr),r0 is gbr & r0 & opcode_08_15=0b11000110 & disp_00_07 [disp = (disp_00_07 << 2); ] +{ + r0 = *:4 (gbr + disp); +} + +:mov.b r0,@(disp_00_07,gbr) is r0 & gbr & opcode_08_15=0b11000000 & disp_00_07 +{ + *:1 (gbr + disp_00_07) = r0:1; +} + +:mov.w r0,@(disp,gbr) is r0 & gbr & opcode_08_15=0b11000001 & disp_00_07 [disp = (disp_00_07 << 1); ] +{ + *:2 (gbr + disp) = r0:2; +} + +:mov.l r0,@(disp,gbr) is r0 & gbr & opcode_08_15=0b11000010 & disp_00_07 [disp = (disp_00_07 << 2); ] +{ + *:4 (gbr + disp) = r0:4; +} + +:movt rn_08_11 is opcode_12_15=0b0000 & rn_08_11 & opcode_00_07=0b00101001 +{ + rn_08_11 = zext($(T_FLAG)); +} + +@if SH_VERSION == "2A" + +# MOV.B R0, @Rn+ 0100nnnn10001011 R0 → (Rn), Rn + 1 → Rn +:mov.b r0, @rn_08_11+ + is r0 & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10001011 +{ + *:1 (rn_08_11) = r0; + rn_08_11 = rn_08_11 + 1; +} + +# MOV.W R0, @Rn+ 0100nnnn10011011 R0 → (Rn), Rn + 2 → Rn +:mov.w r0, @rn_08_11+ + is r0 & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10011011 +{ + *:2 (rn_08_11) = r0; + rn_08_11 = rn_08_11 + 2; +} + +# MOV.L R0, @Rn+ 0100nnnn10101011 R0 → (Rn), Rn + 4 → Rn +:mov.l r0, @rn_08_11+ + is r0 & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10101011 +{ + *:4 (rn_08_11) = r0; + rn_08_11 = rn_08_11 + 4; +} + +# MOV.B @-Rm, R0 0100mmmm11001011 Rm - 1 → Rm, (Rm) → sign extension → R0 +:mov.b @-rm_08_11, r0 + is r0 & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b11001011 +{ + rm_08_11 = rm_08_11 - 1; + r0 = sext(*:1 (rm_08_11)); +} + +# MOV.W @-Rm, R0 0100mmmm11011011 Rm - 2 → Rm, (Rm) → sign extension → R0 +:mov.w @-rm_08_11, r0 + is r0 & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b11011011 +{ + rm_08_11 = rm_08_11 - 2; + r0 = sext(*:2 (rm_08_11)); +} + +# MOV.L @-Rm, R0 0100mmmm11101011 Rm - 4 → Rm, (Rm) → R0 +:mov.l @-rm_08_11, r0 + is r0 & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b11101011 +{ + rm_08_11 = rm_08_11 - 4; + r0 = *:4 (rm_08_11); +} + +# MOV.B Rm, @(disp12, Rn) 0011nnnnmmmm0001 0000dddddddddddd Rm -> (disp+Rn) +:mov.b l_rm_20_23, @(l_disp_00_11, l_rn_24_27) is l_opcode_28_31=0b0011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b0000 & l_disp_00_11 +{ + *:1 (l_rn_24_27 + l_disp_00_11) = l_rm_20_23; +} + +# MOV.W Rm, @(disp12, Rn) 0011nnnnmmmm0001 0001dddddddddddd Rm → (disp×2+Rn) +:mov.w l_rm_20_23, @(disp, l_rn_24_27) + is l_opcode_28_31=0b0011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b0001 & l_disp_00_11 + [ disp = 2*l_disp_00_11; ] +{ + *:2 (l_rn_24_27 + disp) = l_rm_20_23; +} + +# MOV.L Rm, @(disp12, Rn) 0011nnnnmmmm0001 0010dddddddddddd Rm → (disp×4+Rn) +:mov.l l_rm_20_23, @(disp, l_rn_24_27) + is l_opcode_28_31=0b0011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b0010 & l_disp_00_11 + [ disp = 4*l_disp_00_11; ] +{ + *:4 (l_rn_24_27 + disp) = l_rm_20_23; +} + +# MOV.B @(disp12, Rm), Rn 0011nnnnmmmm0001 0100dddddddddddd (disp+Rm) → sign extension → Rn +:mov.b @(l_disp_00_11, l_rm_20_23), l_rn_24_27 is l_opcode_28_31=0b011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b0100 & l_disp_00_11 +{ + l_rn_24_27 = sext(*:1 (l_rm_20_23 + l_disp_00_11)); +} + +# MOV.W @(disp12, Rm), Rn 0011nnnnmmmm0001 0101dddddddddddd (disp×2+Rm) → sign extension → Rn +:mov.w @(disp, l_rm_20_23), l_rn_24_27 + is l_opcode_28_31=0b011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b0101 & l_disp_00_11 + [ disp = 2*l_disp_00_11; ] +{ + l_rn_24_27 = sext(*:2 (l_rm_20_23 + disp)); +} + +# MOV.L @(disp12, Rm), Rn 0011nnnnmmmm0001 0110dddddddddddd (disp×4+Rm) → Rn +:mov.l @(disp, l_rm_20_23), l_rn_24_27 + is l_opcode_28_31=0b011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b0110 & l_disp_00_11 + [ disp = (4*l_disp_00_11); ] +{ + l_rn_24_27 = *:4 (l_rm_20_23 + disp); +} + +# MOVU.B @(disp12,Rm), Rn 0011nnnnmmmm0001 1000dddddddddddd (disp+Rm) → zero extension → Rn +:movu.b @(l_disp_00_11, l_rm_20_23), l_rn_24_27 + is l_opcode_28_31=0b0011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b1000 & l_disp_00_11 +{ + l_rn_24_27 = zext(*:1 (l_disp_00_11 + l_rm_20_23)); +} + +# MOVU.W @(disp12,Rm), Rn 0011nnnnmmmm0001 1001dddddddddddd (disp×2+Rm) → zero extension → Rn +:movu.w @(disp, l_rm_20_23), l_rn_24_27 + is l_opcode_28_31=0b0011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b1001 & l_disp_00_11 + [ disp = l_disp_00_11 * 2; ] +{ + l_rn_24_27 = zext(*:2 (disp + l_rm_20_23)); +} + +simm20: "#"value is l_simm20_20_23 & l_imm20_00_15 + [ value = ((l_simm20_20_23 << 16) | l_imm20_00_15); ] + { export *[const]:4 value; } + +simm20s: "#"value is l_simm20_20_23 & l_imm20_00_15 + [ value = ((l_simm20_20_23 << 16) | l_imm20_00_15) << 8; ] + { export *[const]:4 value; } + + +# MOVI20 #imm20, Rn 0000nnnniiii0000 iiiiiiiiiiiiiiii imm → sign extension → Rn +:movi20 simm20, l_rn_24_27 + is l_opcode_28_31=0b0000 & l_rn_24_27 & l_opcode_16_19=0b0000 & simm20 +{ + l_rn_24_27 = simm20; +} + +# MOVI20S #imm20, Rn 0000nnnniiii0001 iiiiiiiiiiiiiiii imm<<8 → sign extension → Rn +:movi20s simm20s, l_rn_24_27 + is l_opcode_28_31=0b0000 & l_rn_24_27 & l_opcode_16_19=0b0001 & simm20s +{ + l_rn_24_27 = simm20s; +} + +# +# movm* instuctions are only in SH2A. They don't collide, but could be ifdef'ed for 2A only +# + +macro loadRegister(reg, ea) { + reg = *:4(ea); + ea = ea+4; +} + +macro storeRegister(reg, ea) { + ea = ea-4; + *:4(ea) = reg; +} + +MovMLReg1_0: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=0 { storeRegister(r0,r15); } +MovMLReg1_0store: is rm_imm_08_11 { storeRegister(r0,r15); } + +MovMLReg1_1: MovMLReg1_0 is MovMLReg1_0 { r0 = r0; } +MovMLReg1_1: rm_imm_08_11 is MovMLReg1_0store & rm_imm_08_11 & rm_08_11=1 { storeRegister(r1,r15); build MovMLReg1_0store; } +MovMLReg1_1store: is MovMLReg1_0store & rm_imm_08_11 { storeRegister(r1,r15); build MovMLReg1_0store; } + +MovMLReg1_2: MovMLReg1_1 is MovMLReg1_1 { r0 = r0; } +MovMLReg1_2: rm_imm_08_11 is MovMLReg1_1store & rm_imm_08_11 & rm_08_11=2 { storeRegister(r2,r15); build MovMLReg1_1store; } +MovMLReg1_2store: is MovMLReg1_1store & rm_imm_08_11 { storeRegister(r2,r15); build MovMLReg1_1store; } + +MovMLReg1_3: MovMLReg1_2 is MovMLReg1_2 { r0 = r0; } +MovMLReg1_3: rm_imm_08_11 is MovMLReg1_2store & rm_imm_08_11 & rm_08_11=3 { storeRegister(r3,r15); build MovMLReg1_2store; } +MovMLReg1_3store: is MovMLReg1_2store & rm_imm_08_11 { storeRegister(r3,r15); build MovMLReg1_2store; } + +MovMLReg1_4: MovMLReg1_3 is MovMLReg1_3 { r0 = r0; } +MovMLReg1_4: rm_imm_08_11 is MovMLReg1_3store & rm_imm_08_11 & rm_08_11=4 { storeRegister(r4,r15); build MovMLReg1_3store; } +MovMLReg1_4store: is MovMLReg1_3store & rm_imm_08_11 { storeRegister(r4,r15); build MovMLReg1_3store; } + +MovMLReg1_5: MovMLReg1_4 is MovMLReg1_4 { r0 = r0; } +MovMLReg1_5: rm_imm_08_11 is MovMLReg1_4store & rm_imm_08_11 & rm_08_11=5 { storeRegister(r5,r15); build MovMLReg1_4store; } +MovMLReg1_5store: is MovMLReg1_4store & rm_imm_08_11 { storeRegister(r5,r15); build MovMLReg1_4store; } + +MovMLReg1_6: MovMLReg1_5 is MovMLReg1_5 { r0 = r0; } +MovMLReg1_6: rm_imm_08_11 is MovMLReg1_5store & rm_imm_08_11 & rm_08_11=6 { storeRegister(r6,r15); build MovMLReg1_5store; } +MovMLReg1_6store: is MovMLReg1_5store & rm_imm_08_11 { storeRegister(r6,r15); build MovMLReg1_5store; } + +MovMLReg1_7: MovMLReg1_6 is MovMLReg1_6 { r0 = r0; } +MovMLReg1_7: rm_imm_08_11 is MovMLReg1_6store & rm_imm_08_11 & rm_08_11=7 { storeRegister(r7,r15); build MovMLReg1_6store; } +MovMLReg1_7store: is MovMLReg1_6store & rm_imm_08_11 { storeRegister(r7,r15); build MovMLReg1_6store; } + +MovMLReg1_8: MovMLReg1_7 is MovMLReg1_7 { r0 = r0; } +MovMLReg1_8: rm_imm_08_11 is MovMLReg1_7store & rm_imm_08_11 & rm_08_11=8 { storeRegister(r8,r15); build MovMLReg1_7store; } +MovMLReg1_8store: is MovMLReg1_7store & rm_imm_08_11 { storeRegister(r8,r15); build MovMLReg1_7store; } + +MovMLReg1_9: MovMLReg1_8 is MovMLReg1_8 { r0 = r0; } +MovMLReg1_9: rm_imm_08_11 is MovMLReg1_8store & rm_imm_08_11 & rm_08_11=9 { storeRegister(r9,r15); build MovMLReg1_8store; } +MovMLReg1_9store: is MovMLReg1_8store & rm_imm_08_11 { storeRegister(r9,r15); build MovMLReg1_8store; } + +MovMLReg1_10: MovMLReg1_9 is MovMLReg1_9 { r0 = r0; } +MovMLReg1_10: rm_imm_08_11 is MovMLReg1_9store & rm_imm_08_11 & rm_08_11=10 { storeRegister(r10,r15); build MovMLReg1_9store; } +MovMLReg1_10store: is MovMLReg1_9store & rm_imm_08_11 { storeRegister(r10,r15); build MovMLReg1_9store; } + +MovMLReg1_11: MovMLReg1_10 is MovMLReg1_10 { r0 = r0; } +MovMLReg1_11: rm_imm_08_11 is MovMLReg1_10store & rm_imm_08_11 & rm_08_11=11 { storeRegister(r11,r15); build MovMLReg1_10store; } +MovMLReg1_11store: is MovMLReg1_10store & rm_imm_08_11 { storeRegister(r11,r15); build MovMLReg1_10store; } + +MovMLReg1_12: MovMLReg1_11 is MovMLReg1_11 { r0 = r0; } +MovMLReg1_12: rm_imm_08_11 is MovMLReg1_11store & rm_imm_08_11 & rm_08_11=12 { storeRegister(r12,r15); build MovMLReg1_11store; } +MovMLReg1_12store: is MovMLReg1_11store & rm_imm_08_11 { storeRegister(r12,r15); build MovMLReg1_11store; } + +MovMLReg1_13: MovMLReg1_12 is MovMLReg1_12 { r0 = r0; } +MovMLReg1_13: rm_imm_08_11 is MovMLReg1_12store & rm_imm_08_11 & rm_08_11=13 { storeRegister(r13,r15); build MovMLReg1_12store; } +MovMLReg1_13store: is MovMLReg1_12store & rm_imm_08_11 { storeRegister(r13,r15); build MovMLReg1_12store; } + +MovMLReg1_14: MovMLReg1_13 is MovMLReg1_13 { r0 = r0; } +MovMLReg1_14: rm_imm_08_11 is MovMLReg1_13store & rm_imm_08_11 & rm_08_11=14 { storeRegister(r14,r15); build MovMLReg1_13store; } +MovMLReg1_14store: is MovMLReg1_13store & rm_imm_08_11 { storeRegister(r14,r15); build MovMLReg1_13store; } + +MovMLReg1_15: MovMLReg1_14 is MovMLReg1_14 { r0 = r0; } +MovMLReg1_15: rm_imm_08_11 is MovMLReg1_14store & rm_imm_08_11 & rm_08_11=15 { storeRegister(pr,r15); build MovMLReg1_14store; } + +MovMLReg1: MovMLReg1_15 is MovMLReg1_15 { + build MovMLReg1_15; +} + +# MOVML.L Rm, @-R15 0100mmmm11110001 +:movml.l MovMLReg1, @-r15 + is r15 & opcode_12_15=0b0100 & rm_imm_08_11 & opcode_00_07=0b11110001 & MovMLReg1 +{ + build MovMLReg1; +} + + +MovMLReg2_0: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=0 { loadRegister(r0,r15); } + +MovMLReg2_0load: is rm_imm_08_11 { loadRegister(r0,r15); } + +MovMLReg2_1: MovMLReg2_0 is MovMLReg2_0 { r0 = r0; } +MovMLReg2_1: rm_imm_08_11 is MovMLReg2_0load & rm_imm_08_11 & rm_08_11=1 { build MovMLReg2_0load; loadRegister(r1,r15); } +MovMLReg2_1load: is MovMLReg2_0load & rm_imm_08_11 { build MovMLReg2_0load; loadRegister(r1,r15); } + +MovMLReg2_2: MovMLReg2_1 is MovMLReg2_1 { r0 = r0; } +MovMLReg2_2: rm_imm_08_11 is MovMLReg2_1load & rm_imm_08_11 & rm_08_11=2 { build MovMLReg2_1load; loadRegister(r2,r15); } +MovMLReg2_2load: is MovMLReg2_1load & rm_imm_08_11 { build MovMLReg2_1load; loadRegister(r2,r15); } + +MovMLReg2_3: MovMLReg2_2 is MovMLReg2_2 { r0 = r0; } +MovMLReg2_3: rm_imm_08_11 is MovMLReg2_2load & rm_imm_08_11 & rm_08_11=3 { build MovMLReg2_2load; loadRegister(r3,r15); } +MovMLReg2_3load: is MovMLReg2_2load & rm_imm_08_11 { build MovMLReg2_2load; loadRegister(r3,r15); } + +MovMLReg2_4: MovMLReg2_3 is MovMLReg2_3 { r0 = r0; } +MovMLReg2_4: rm_imm_08_11 is MovMLReg2_3load & rm_imm_08_11 & rm_08_11=4 { build MovMLReg2_3load; loadRegister(r4,r15); } + +MovMLReg2_4load: is MovMLReg2_3load & rm_imm_08_11 { build MovMLReg2_3load; loadRegister(r4,r15); } + +MovMLReg2_5: MovMLReg2_4 is MovMLReg2_4 { r0 = r0; } +MovMLReg2_5: rm_imm_08_11 is MovMLReg2_4load & rm_imm_08_11 & rm_08_11=5 { build MovMLReg2_4load; loadRegister(r5,r15); } + +MovMLReg2_5load: is MovMLReg2_4load & rm_imm_08_11 { build MovMLReg2_4load; loadRegister(r5,r15); } + +MovMLReg2_6: MovMLReg2_5 is MovMLReg2_5 { r0 = r0; } +MovMLReg2_6: rm_imm_08_11 is MovMLReg2_5load & rm_imm_08_11 & rm_08_11=6 { build MovMLReg2_5load; loadRegister(r6,r15); } + +MovMLReg2_6load: is MovMLReg2_5load & rm_imm_08_11 { build MovMLReg2_5load; loadRegister(r6,r15); } + +MovMLReg2_7: MovMLReg2_6 is MovMLReg2_6 { r0 = r0; } +MovMLReg2_7: rm_imm_08_11 is MovMLReg2_6load & rm_imm_08_11 & rm_08_11=7 { build MovMLReg2_6load; loadRegister(r7,r15); } + +MovMLReg2_7load: is MovMLReg2_6load & rm_imm_08_11 { build MovMLReg2_6load; loadRegister(r7,r15); } + +MovMLReg2_8: MovMLReg2_7 is MovMLReg2_7 { r0 = r0; } +MovMLReg2_8: rm_imm_08_11 is MovMLReg2_7load & rm_imm_08_11 & rm_08_11=8 { build MovMLReg2_7load; loadRegister(r8,r15); } + +MovMLReg2_8load: is MovMLReg2_7load & rm_imm_08_11 { build MovMLReg2_7load; loadRegister(r8,r15); } + +MovMLReg2_9: MovMLReg2_8 is MovMLReg2_8 { r0 = r0; } +MovMLReg2_9: rm_imm_08_11 is MovMLReg2_8load & rm_imm_08_11 & rm_08_11=9 { build MovMLReg2_8load; loadRegister(r9,r15); } + +MovMLReg2_9load: is MovMLReg2_8load & rm_imm_08_11 { build MovMLReg2_8load; loadRegister(r9,r15); } + +MovMLReg2_10: MovMLReg2_9 is MovMLReg2_9 { r0 = r0; } +MovMLReg2_10: rm_imm_08_11 is MovMLReg2_9load & rm_imm_08_11 & rm_08_11=10 { build MovMLReg2_9load; loadRegister(r10,r15); } + +MovMLReg2_10load: is MovMLReg2_9load & rm_imm_08_11 { build MovMLReg2_9load; loadRegister(r10,r15); } + +MovMLReg2_11: MovMLReg2_10 is MovMLReg2_10 { r0 = r0; } +MovMLReg2_11: rm_imm_08_11 is MovMLReg2_10load & rm_imm_08_11 & rm_08_11=11 { build MovMLReg2_10load; loadRegister(r11,r15); } +MovMLReg2_11load: is MovMLReg2_10load & rm_imm_08_11 { build MovMLReg2_10load; loadRegister(r11,r15); } + +MovMLReg2_12: MovMLReg2_11 is MovMLReg2_11 { r0 = r0; } +MovMLReg2_12: rm_imm_08_11 is MovMLReg2_11load & rm_imm_08_11 & rm_08_11=12 { build MovMLReg2_11load; loadRegister(r12,r15); } + +MovMLReg2_12load: is MovMLReg2_11load & rm_imm_08_11 { build MovMLReg2_11load; loadRegister(r12,r15); } + +MovMLReg2_13: MovMLReg2_12 is MovMLReg2_12 { r0 = r0; } +MovMLReg2_13: rm_imm_08_11 is MovMLReg2_12load & rm_imm_08_11 & rm_08_11=13 { build MovMLReg2_12load; loadRegister(r13,r15); } + +MovMLReg2_13load: is MovMLReg2_12load & rm_imm_08_11 { build MovMLReg2_12load; loadRegister(r13,r15); } + +MovMLReg2_14: MovMLReg2_13 is MovMLReg2_13 { r0 = r0; } +MovMLReg2_14: rm_imm_08_11 is MovMLReg2_13load & rm_imm_08_11 & rm_08_11=14 { build MovMLReg2_13load; loadRegister(r14,r15); } + +MovMLReg2_14load: is MovMLReg2_13load & rm_imm_08_11 { build MovMLReg2_13load; loadRegister(r14,r15); } + +MovMLReg2_15: MovMLReg2_14 is MovMLReg2_14 { r0 = r0; } +MovMLReg2_15: rm_imm_08_11 is MovMLReg2_14load & rm_imm_08_11 & rm_08_11=15 { build MovMLReg2_14load; loadRegister(pr,r15); } + +MovMLReg2: MovMLReg2_15 is MovMLReg2_15 { + build MovMLReg2_15; +} + +# MOVML.L @R15+, Rn 0100nnnn11110101 +:movml.l @r15+, MovMLReg2 + is r15 & opcode_12_15=0b0100 & rn_imm_08_11 & opcode_00_07=0b11110101 & MovMLReg2 { + build MovMLReg2; +} + + +MovMUReg1_0: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=0 { storeRegister(r0,r15); } + +MovMUReg1_1: MovMUReg1_0 is MovMUReg1_0 { storeRegister(r1,r15); build MovMUReg1_0; } +MovMUReg1_1: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=1 { storeRegister(r1,r15); } + +MovMUReg1_2: MovMUReg1_1 is MovMUReg1_1 { storeRegister(r2,r15); build MovMUReg1_1; } +MovMUReg1_2: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=2 { storeRegister(r2,r15); } + +MovMUReg1_3: MovMUReg1_2 is MovMUReg1_2 { storeRegister(r3,r15); build MovMUReg1_2; } +MovMUReg1_3: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=3 { storeRegister(r3,r15); } + +MovMUReg1_4: MovMUReg1_3 is MovMUReg1_3 { storeRegister(r4,r15); build MovMUReg1_3; } +MovMUReg1_4: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=4 { storeRegister(r4,r15); } + +MovMUReg1_5: MovMUReg1_4 is MovMUReg1_4 { storeRegister(r5,r15); build MovMUReg1_4; } +MovMUReg1_5: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=5 { storeRegister(r5,r15); } + +MovMUReg1_6: MovMUReg1_5 is MovMUReg1_5 { storeRegister(r6,r15); build MovMUReg1_5; } +MovMUReg1_6: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=6 { storeRegister(r6,r15); } + +MovMUReg1_7: MovMUReg1_6 is MovMUReg1_6 { storeRegister(r7,r15); build MovMUReg1_6; } +MovMUReg1_7: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=7 { storeRegister(r7,r15); } + +MovMUReg1_8: MovMUReg1_7 is MovMUReg1_7 { storeRegister(r8,r15); build MovMUReg1_7; } +MovMUReg1_8: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=8 { storeRegister(r8,r15); } + +MovMUReg1_9: MovMUReg1_8 is MovMUReg1_8 { storeRegister(r9,r15); build MovMUReg1_8; } +MovMUReg1_9: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=9 { storeRegister(r9,r15); } + +MovMUReg1_10: MovMUReg1_9 is MovMUReg1_9 { storeRegister(r10,r15); build MovMUReg1_9; } +MovMUReg1_10: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=10 { storeRegister(r10,r15); } + +MovMUReg1_11: MovMUReg1_10 is MovMUReg1_10 { storeRegister(r11,r15); build MovMUReg1_10; } +MovMUReg1_11: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=11 { storeRegister(r11,r15); } + +MovMUReg1_12: MovMUReg1_11 is MovMUReg1_11 { storeRegister(r12,r15); build MovMUReg1_11; } +MovMUReg1_12: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=12 { storeRegister(r12,r15); } + +MovMUReg1_13: MovMUReg1_12 is MovMUReg1_12 { storeRegister(r13,r15); build MovMUReg1_12; } +MovMUReg1_13: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=13 { storeRegister(r13,r15); } + +MovMUReg1_14: MovMUReg1_13 is MovMUReg1_13 { storeRegister(r14,r15); build MovMUReg1_13; } +MovMUReg1_14: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=14 { storeRegister(r14,r15); } + +MovMUReg1_15: MovMUReg1_14 is MovMUReg1_14 { storeRegister(pr,r15); build MovMUReg1_14; } +MovMUReg1_15: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=15 { storeRegister(pr,r15); } + +MovMUReg1: MovMUReg1_15 is MovMUReg1_15 { + build MovMUReg1_15; +} + +# MOVMU.L Rm, @-R15 0100mmmm11110000 +:movmu.l MovMUReg1, @-r15 + is r15 & opcode_12_15=0b0100 & rm_imm_08_11 & opcode_00_07=0b11110000 & MovMUReg1 +{ + build MovMUReg1; +} + +MovMUReg2_0: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=0 { loadRegister(r0,r15); } + +MovMUReg2_1: MovMUReg2_0 is MovMUReg2_0 { build MovMUReg2_0; loadRegister(r1,r15); } +MovMUReg2_1: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=1 { loadRegister(r1,r15); } + +MovMUReg2_2: MovMUReg2_1 is MovMUReg2_1 { build MovMUReg2_1; loadRegister(r2,r15); } +MovMUReg2_2: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=2 { loadRegister(r2,r15); } + +MovMUReg2_3: MovMUReg2_2 is MovMUReg2_2 { build MovMUReg2_2; loadRegister(r3,r15); } +MovMUReg2_3: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=3 { loadRegister(r3,r15); } + +MovMUReg2_4: MovMUReg2_3 is MovMUReg2_3 { build MovMUReg2_3; loadRegister(r4,r15); } +MovMUReg2_4: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=4 { loadRegister(r4,r15); } + +MovMUReg2_5: MovMUReg2_4 is MovMUReg2_4 { build MovMUReg2_4; loadRegister(r5,r15); } +MovMUReg2_5: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=5 { loadRegister(r5,r15); } + +MovMUReg2_6: MovMUReg2_5 is MovMUReg2_5 { build MovMUReg2_5; loadRegister(r6,r15); } +MovMUReg2_6: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=6 { loadRegister(r6,r15); } + +MovMUReg2_7: MovMUReg2_6 is MovMUReg2_6 { build MovMUReg2_6; loadRegister(r7,r15); } +MovMUReg2_7: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=7 { loadRegister(r7,r15); } + +MovMUReg2_8: MovMUReg2_7 is MovMUReg2_7 { build MovMUReg2_7; loadRegister(r8,r15); } +MovMUReg2_8: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=8 { loadRegister(r8,r15); } + +MovMUReg2_9: MovMUReg2_8 is MovMUReg2_8 { build MovMUReg2_8; loadRegister(r9,r15); } +MovMUReg2_9: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=9 { loadRegister(r9,r15); } + +MovMUReg2_10: MovMUReg2_9 is MovMUReg2_9 { build MovMUReg2_9; loadRegister(r10,r15); } +MovMUReg2_10: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=10 { loadRegister(r10,r15); } + +MovMUReg2_11: MovMUReg2_10 is MovMUReg2_10 { build MovMUReg2_10; loadRegister(r11,r15); } +MovMUReg2_11: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=11 { loadRegister(r11,r15); } + +MovMUReg2_12: MovMUReg2_11 is MovMUReg2_11 { build MovMUReg2_11; loadRegister(r12,r15); } +MovMUReg2_12: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=12 { loadRegister(r12,r15); } + +MovMUReg2_13: MovMUReg2_12 is MovMUReg2_12 { build MovMUReg2_12; loadRegister(r13,r15); } +MovMUReg2_13: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=13 { loadRegister(r13,r15); } + +MovMUReg2_14: MovMUReg2_13 is MovMUReg2_13 { build MovMUReg2_13; loadRegister(r14,r15); } +MovMUReg2_14: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=14 { loadRegister(r14,r15); } + +MovMUReg2_15: MovMUReg2_14 is MovMUReg2_14 { build MovMUReg2_14; loadRegister(pr,r15); } +MovMUReg2_15: rm_imm_08_11 is rm_imm_08_11 & rm_08_11=15 { loadRegister(pr,r15); } + +MovMUReg2: MovMUReg2_15 is MovMUReg2_15 { + build MovMUReg2_15; +} + +# MOVMU.L @R15+, Rn 0100nnnn11110100 +:movmu.l @r15+, MovMUReg2 + is r15 & opcode_12_15=0b0100 & rn_imm_08_11 & opcode_00_07=0b11110100 & MovMUReg2 +{ + build MovMUReg2; +} + + +# MOVRT Rn 0000nnnn00111001 ~ T → Rn +:movrt rn_08_11 is opcode_12_15=0b0000 & rn_08_11 & opcode_00_07=0b00111001 +{ + rn_08_11 = zext($(T_FLAG) == 0); +} + +# NOTT 0000000001101000 ~ T → T +:nott is opcode_00_15=0b0000000001101000 +{ + $(T_FLAG) = ~$(T_FLAG); +} + +@endif + +:swap.b rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b1000 +{ + local temp0; + local temp1; + + temp0 = rm_04_07 & 0xFFFF0000; + temp1 = (rm_04_07 & 0x000000FF) << 8; + + rn_08_11 = (rm_04_07 & 0x0000FF00) >> 8; + rn_08_11 = rn_08_11 | temp1 | temp0; +} + +:swap.w rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b1001 +{ + local temp; + + temp = (rm_04_07 >> 16) & 0x0000FFFF; + + rn_08_11 = rm_04_07 << 16; + rn_08_11 = rn_08_11 | temp; +} + +:xtrct rm_04_07,rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b1101 +{ + local high; + local low; + + high = (rm_04_07 << 16) & 0xFFFF0000; + low = (rn_08_11 >> 16) & 0x0000FFFF; + rn_08_11 = high | low; +} + +# +# Arithmetic Operation Instructions +# +:add rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b1100 +{ + rn_08_11 = rn_08_11 + rm_04_07; +} + +:add simm_00_07,rn_08_11 is opcode_12_15=0b0111 & rn_08_11 & simm_00_07 +{ + rn_08_11 = rn_08_11 + simm_00_07; +} + +:addc rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b1110 +{ + local temp0; + local temp1; + + temp1 = rn_08_11 + rm_04_07; + temp0 = temp1; + + rn_08_11 = temp1 + zext($(T_FLAG)); + + $(T_FLAG) = (temp0 > temp1) | (temp1 > rn_08_11); +} + +:addv rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b1111 +{ + local dest:1; + local src:1; + local ans:1; + + dest = (rn_08_11 s< 0); + src = (rm_04_07 s< 0); + + src = src + dest; + rn_08_11 = rn_08_11 + rm_04_07; + + ans = (rn_08_11 s< 0); + + ans = ans + dest; + + $(T_FLAG) = (src == 0 || src == 2) && (ans == 1); +} + +:cmp"/eq" simm_00_07,r0 is r0 & opcode_08_15=0b10001000 & simm_00_07 +{ + $(T_FLAG) = (r0 == simm_00_07); +} + +:cmp"/eq" rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b0000 +{ + $(T_FLAG) = (rn_08_11 == rm_04_07); +} + +:cmp"/hs" rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b0010 +{ + $(T_FLAG) = (rn_08_11 >= rm_04_07); +} + +:cmp"/ge" rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b0011 +{ + $(T_FLAG) = (rn_08_11 s>= rm_04_07); +} + +:cmp"/hi" rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b0110 +{ + $(T_FLAG) = (rn_08_11 > rm_04_07); +} + +:cmp"/gt" rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b0111 +{ + $(T_FLAG) = (rn_08_11 s> rm_04_07); +} + +:cmp"/pl" rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00010101 +{ + $(T_FLAG) = (rn_08_11 s> 0); +} + +:cmp"/pz" rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00010001 +{ + $(T_FLAG) = (rn_08_11 s>= 0); +} + +:cmp"/str" rm_04_07,rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b1100 +{ + local temp:4; + local HH:4; + local HL:4; + local LH:4; + local LL:4; + + temp = rn_08_11 ^ rm_04_07; + + HH = (temp & 0xFF000000) >> 24; + HL = (temp & 0x00FF0000) >> 16; + LH = (temp & 0x0000FF00) >> 8; + LL = (temp & 0x000000FF); + + $(T_FLAG) = (HH != 0) && (HL != 0) && (LH != 0) && (LL != 0); +} + +@if SH_VERSION == "2A" + +# The pseudo code for clips in the super-h manual looks incorrect, +# this solution was contributed by @mumbel +:clips.b rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10010001 +{ + local uppercheck = (rn_08_11 s> 0x7f); + local lowercheck = (rn_08_11 s< -0x80); + if (!(uppercheck || lowercheck)) goto inst_next; + rn_08_11 = (0x0000007f * zext(uppercheck)) + (0xffffff80 * zext(lowercheck)); + $(CS_FLAG)=1; +} + +:clips.w rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10010101 +{ + local uppercheck = (rn_08_11 s> 0x7fff); + local lowercheck = (rn_08_11 s< -0x8000); + if (!(uppercheck || lowercheck)) goto inst_next; + rn_08_11 = (0x00007fff * zext(uppercheck)) + (0xffff8000 * zext(lowercheck)); + $(CS_FLAG)=1; +} + +:clipu.b rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10000001 +{ + if (rn_08_11 <= 0x000000ff) goto ; + rn_08_11 = 0x000000ff; + $(CS_FLAG) = 1; + +} + +:clipu.w rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10000101 +{ + if (rn_08_11 <= 0x0000ffff) goto ; + rn_08_11 = 0x0000ffff; + $(CS_FLAG) = 1; + +} + +@endif + +:div0s rm_04_07,rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0111 +{ + $(Q_FLAG) = !((rn_08_11 & 0x80000000) == 0); + $(M_FLAG) = !((rm_04_07 & 0x80000000) == 0); + + $(T_FLAG) = !($(M_FLAG) == $(Q_FLAG)); +} + +:div0u is opcode_00_15=0b0000000000011001 +{ + $(M_FLAG) = 0; + $(Q_FLAG) = 0; + $(T_FLAG) = 0; +} + +:div1 rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b0100 +{ + local tmp0:4; + local tmp1:1; + local tmp2:4; + local old_q:1; + local old_q_eq_m:1; + local m_eq_q:1; + + old_q = $(Q_FLAG); + $(Q_FLAG) = (0x80000000 & rn_08_11) != 0; + tmp2 = rm_04_07; + rn_08_11 = rn_08_11 << 1; + rn_08_11 = rn_08_11 | zext($(T_FLAG)); + old_q_eq_m = old_q == $(M_FLAG); + m_eq_q = $(M_FLAG) == $(Q_FLAG); + + tmp0 = rn_08_11; + # rn_08_11 = old_q_eq_m ? rn_08_11 - tmp2 : rn_08_11 + tmp2; + rn_08_11 = (zext(old_q_eq_m) * (rn_08_11 - tmp2)) + (zext(!old_q_eq_m) * (rn_08_11 + tmp2)); + # tmp1 = old_q_eq_m ? rn_08_11 > tmp0 : rn_08_11 < tmp0; + tmp1 = (old_q_eq_m * (rn_08_11 > tmp0)) + (!old_q_eq_m * (rn_08_11 < tmp0)); + # $(Q_FLAG) = m_eq_q ? tmp1 : tmp1 == 0; + $(Q_FLAG) = (m_eq_q * tmp1) + (!m_eq_q & (tmp1 == 0)); + + $(T_FLAG) = $(Q_FLAG) == $(M_FLAG); +} + +@if SH_VERSION == "2A" + +:divs r0, rn_08_11 is r0 & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10010100 +{ + rn_08_11 = rn_08_11 s/ r0; +} + +:divu r0, rn_08_11 is r0 & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10000100 +{ + rn_08_11 = rn_08_11 / r0; +} + +@endif + +@if (SH_VERSION == "2") || (SH_VERSION == "2A") +:dmuls.l rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b1101 +{ + local a:8 = sext(rn_08_11); + local b:8 = sext(rm_04_07); + local result:8 = a * b; + + mach = result(4); + macl = result:4; +} + +:dmulu.l rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b0101 +{ + local a:8 = zext(rn_08_11); + local b:8 = zext(rm_04_07); + local result:8 = a * b; + + mach = result(4); + macl = result:4; +} + +:dt rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00010000 +{ + rn_08_11 = rn_08_11 - 1; + $(T_FLAG) = (rn_08_11 == 0); +} +@endif + +:exts.b rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b1110 +{ + local temp:1 = rm_04_07:1; + rn_08_11 = sext(temp); +} + +:exts.w rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b1111 +{ + local temp:2 = rm_04_07:2; + rn_08_11 = sext(temp); +} + +:extu.b rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b1100 +{ + rn_08_11 = rm_04_07 & 0x000000FF; +} + +:extu.w rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b1101 +{ + rn_08_11 = rm_04_07 & 0x0000FFFF; +} + +@if (SH_VERSION == "2") || (SH_VERSION == "2A") +:mac.l @rm_04_07+,@rn_08_11+ is opcode_12_15=0b0000 & rn_08_11 & rm_04_07 & opcode_00_03=0b1111 +{ + # FIXME: review this instruction + + local RnL; + local RnH; + local RmL; + local RmH; + local Res0; + local Res1:4; + local Res2:4; + + local temp0; + local temp1:4; + local temp2:4; + local temp3; + + local tempm:4; + local tempn:4; + local fnLmL:4; + + tempn = *:4 rn_08_11; + rn_08_11 = rn_08_11 + 4; + tempm = *:4 rm_04_07; + rm_04_07 = rm_04_07 + 4; + + fnLmL = -1 * zext((tempn ^ tempm) s<0); + + if( tempn s>= 0) goto ; + tempn = 0 - tempn; + + + if( tempm s>= 0) goto ; + tempm = 0 - tempm; + + + + temp1 = tempn; + temp2 = tempm; + + RnL = temp1 & 0x0000FFFF; + RnH = (temp1 >> 16) & 0x0000FFFF; + RmL = temp2 & 0x0000FFFF; + RmH = (temp2 >> 16) & 0x0000FFFF; + temp0 = RmL * RnL; + temp1 = RmH * RnL; + temp2 = RmL * RnH; + temp3 = RmH * RnH; + + Res2 = 0; + Res1 = temp1 + temp2; + + if(Res2 >= temp1) goto ; + Res2 = Res2 + 0x00010000; + + + temp1 = (Res1 << 16) & 0xFFFF0000; + + Res0 = temp0 + temp1; + Res2 = Res2 + zext(Res0 < temp0); + + Res2 = Res2 + ((Res1 >> 16) & 0x0000FFFF) + temp3; + + if(fnLmL s>= 0) goto ; + Res2 = ~Res2; + + if(Res0 == 0) goto ; + Res0 = (~Res0) + 1; + goto ; + + + Res2 = Res2 + 1; + + + + if($(S_FLAG) != 1) goto ; + + Res0 = macl + Res0; + Res2 = Res2 + zext(macl > Res0); + + Res2 = Res2 + (mach & 0x0000FFFF); + + if((Res2 s>= 0) || Res2 >= 0xFFFF8000) goto ; + Res2 = 0xFFFF8000; + Res0 = 0x00000000; + + + if((Res2 s<= 0) || Res2 <= 0x00007FFF) goto ; + Res2 = 0x00007FFF; + Res0 = 0xFFFFFFFF; + + + mach = (Res2 & 0x0000FFFF) | (mach & 0xFFFF0000); + macl = Res0; + + goto ; + + + Res0 = macl + Res0; + Res2 = Res2 + zext(macl > Res0); + + Res2 = Res2 + mach; + mach = Res2; + macl = Res0; + + +} +@endif + +:mac.w @rm_04_07+,@rn_08_11+ is opcode_12_15=0b0100 & rn_08_11 & rm_04_07 & opcode_00_03=0b1111 +{ + # FIXME: review this instruction + + local tempm:4; + local tempn:4; + local dest; + local src:4; + local ans; + local templ:4; + + tempn = *:2 rn_08_11; + rn_08_11 = rn_08_11 + 2; + tempm = *:2 rm_04_07; + rm_04_07 = rm_04_07 + 2; + + templ = macl; + tempm = sext(tempn:2) * sext(tempm:2); + + dest = (macl s< 0); + + src = zext(1*(tempm s>= 0)); + tempn = sext(-1*(tempm s>= 0)); + + src = src + zext(dest); + macl = macl + tempm; + + ans = (macl s< 0); + + ans = ans + dest; + + # if (S == 1) + if($(S_FLAG) != 1) goto ; + + if(ans != 1) goto ; + +@if SH_VERSION == "1" + if(src != 0 && src != 2) goto ; + mach = mach | 0x00000001; + +@endif + + if(src == 0) goto ; + if(src == 2) goto ; + goto ; + + + macl = 0x7FFFFFFF; + goto ; + + + macl = 0x80000000; + goto ; + + # if (S != 1) + + + mach = mach + tempn; + + macl = macl + zext(1*(templ s> macl)); + +@if SH_VERSION == "1" + if((mach & 0x00000200) == 0) goto ; + mach = mach | 0xFFFFFC00; + goto ; + + mach = mach & 0x000003FF; +@endif + + +} + +@if (SH_VERSION == "2") || (SH_VERSION == "2A") +:mul.l rm_04_07,rn_08_11 is opcode_12_15=0b0000 & rn_08_11 & rm_04_07 & opcode_00_03=0b0111 +{ + macl = rn_08_11 * rm_04_07; +} +@endif + +@if SH_VERSION == "2A" +:mulr r0, rn_08_11 is r0 & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10000000 +{ + rn_08_11 = r0 * rn_08_11; +} +@endif + +:muls.w rm_04_07,rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b1111 +{ + macl = sext(rn_08_11:2 & 0xFFFF) * sext(rm_04_07:2 & 0xFFFF); +} + +:mulu.w rm_04_07,rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b1110 +{ + macl = (rn_08_11 & 0xFFFF) * (rm_04_07 & 0xFFFF); +} + +:neg rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b1011 +{ + rn_08_11 = 0 - rm_04_07; +} + +:negc rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b1010 +{ + local temp; + + temp = 0 - rm_04_07; + rn_08_11 = temp - zext($(T_FLAG)); + + # FIXME: should temp be signed or unsigned?? + # Documentation says if(0 < temp) not 0 != temp + $(T_FLAG) = (0 != temp) || (temp < rn_08_11); +} + +:sub rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b1000 +{ + rn_08_11 = rn_08_11 - rm_04_07; +} + +:subc rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b1010 +{ + local temp0; + local temp1; + + temp1 = rn_08_11 - rm_04_07; + temp0 = rn_08_11; + + rn_08_11 = temp1 - zext($(T_FLAG)); + + $(T_FLAG) = (temp0 < temp1 || temp1 < rn_08_11); +} + +:subv rm_04_07,rn_08_11 is opcode_12_15=0b0011 & rn_08_11 & rm_04_07 & opcode_00_03=0b1011 +{ + local dest; + local src; + local ans; + + dest = (rn_08_11 s< 0); + src = (rm_04_07 s< 0); + + src = src + dest; + rn_08_11 = rn_08_11 - rm_04_07; + + ans = (rn_08_11 s< 0); + ans = ans + dest; + + $(T_FLAG) = (src == 1) && (ans == 1); +} + +# +# Logic Operation Instructions +# +:and rm_04_07,rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b1001 +{ + rn_08_11 = rn_08_11 & rm_04_07; +} + +:and imm_00_07,r0 is r0 & opcode_08_15=0b11001001 & imm_00_07 +{ + r0 = (r0 & zext(imm_00_07:1)); +} + +:and.b imm_00_07,@(r0,gbr) is r0 & gbr & opcode_08_15=0b11001101 & imm_00_07 +{ + local temp:1 = *:1 (gbr + r0); + temp = temp & imm_00_07:1; + + *:1 (gbr + r0) = temp; +} + +:not rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0111 +{ + rn_08_11 = ~rm_04_07; +} + +:or rm_04_07,rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b1011 +{ + rn_08_11 = rn_08_11 | rm_04_07; +} + +:or imm_00_07,r0 is r0 & opcode_08_15=0b11001011 & imm_00_07 +{ + r0 = r0 | imm_00_07:4; +} + +:or.b imm_00_07,@(r0,gbr) is r0 & gbr & opcode_08_15=0b11001111 & imm_00_07 +{ + local temp:1 = *:1 (gbr + r0); + temp = temp | imm_00_07:1; + + *:1 (gbr + r0) = temp; +} + +:tas.b @rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00011011 +{ + local temp = *:1 rn_08_11; + + $(T_FLAG) = (temp == 0); + + temp = temp | 0x80; + + *:1 rn_08_11 = temp; +} + +:tst rm_04_07,rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b1000 +{ + $(T_FLAG) = ((rm_04_07 & rn_08_11) == 0); +} + +:tst imm_00_07,r0 is r0 & opcode_08_15=0b11001000 & imm_00_07 +{ + local temp = r0 & (imm_00_07 & 0x000000FF); + + $(T_FLAG) = (temp == 0); +} + +:tst.b imm_00_07,@(r0,gbr) is r0 & gbr & opcode_08_15=0b11001100 & imm_00_07 +{ + local temp = *:1 (gbr + r0); + temp = temp & (imm_00_07 & 0x000000FF); + + $(T_FLAG) = (temp == 0); +} + +:xor rm_04_07,rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b1010 +{ + rn_08_11 = rn_08_11 ^ rm_04_07; +} + +:xor imm_00_07,r0 is r0 & opcode_08_15=0b11001010 & imm_00_07 +{ + r0 = r0 ^ (imm_00_07 & 0x000000FF); +} + +:xor.b imm_00_07,@(r0,gbr) is r0 & gbr & opcode_08_15=0b11001110 & imm_00_07 +{ + local temp = *:1 (gbr + r0); + temp = temp & (imm_00_07 & 0x000000FF); + + *:1 (gbr + r0) = temp; +} + +# +#Shift Instructions +# +:rotcl rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00100100 +{ + local temp:1; + + temp = ((rn_08_11 & 0x80000000) != 0); + + rn_08_11 = (rn_08_11 << 1) | zext($(T_FLAG)); + + $(T_FLAG) = temp; +} + +:rotcr rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00100101 +{ + local temp:1; + + temp = !((rn_08_11 & 1) == 0); + + rn_08_11= (rn_08_11 >> 1) | (0x80000000 * zext($(T_FLAG))); + + $(T_FLAG) = temp; +} + +:rotl rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00000100 +{ + $(T_FLAG) = ((rn_08_11 & 0x80000000) != 0); + + rn_08_11 = (rn_08_11 << 1) | zext($(T_FLAG)); +} + +:rotr rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00000101 +{ + $(T_FLAG) = ((rn_08_11 & 0x1) != 0); + + rn_08_11 = (rn_08_11 >> 1) | (rn_08_11 << 31); +} + +@if SH_VERSION == "2A" +:shad rm_04_07, rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & rm_04_07 & opcode_00_03=0b1100 +{ + if (rm_04_07 s> 0) goto ; + if (rm_04_07 s<= -32) goto ; + # shift right + rn_08_11 = rn_08_11 s>> -rm_04_07; + goto ; + + rn_08_11 = rn_08_11 << (rm_04_07 & 0x0000001F); + goto ; + + rn_08_11 = -1 * zext(rn_08_11 s< 0); + +} +@endif + +:shal rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00100000 +{ + # clear or set T + $(T_FLAG) = ((rn_08_11 & 0x80000000) != 0); + + rn_08_11 = rn_08_11 << 1; +} + +:shar rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00100001 +{ + $(T_FLAG) = ((rn_08_11 & 1) == 1); + + rn_08_11 = rn_08_11 s>> 1; +} + +@if SH_VERSION == "2A" +:shld rm_04_07, rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & rm_04_07 & opcode_00_03=0b1101 +{ + if (rm_04_07 s> 0) goto ; + if (rm_04_07 s<= -32) goto ; + # shift right + rn_08_11 = rn_08_11 >> -rm_04_07; + goto ; + + rn_08_11 = rn_08_11 << (rm_04_07 & 0x0000001F); + goto ; + + rn_08_11 = 0; + +} +@endif + +:shll rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00000000 +{ + # clear or set T + $(T_FLAG) = ((rn_08_11 & 0x80000000) != 0); + + rn_08_11 = rn_08_11 << 1; +} + +:shll2 rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00001000 +{ + rn_08_11 = rn_08_11 << 2; +} + +:shll8 rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00011000 +{ + rn_08_11 = rn_08_11 << 8; +} + +:shll16 rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00101000 +{ + rn_08_11 = rn_08_11 << 16; +} + +:shlr rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00000001 +{ + # clear or set T + $(T_FLAG) = (rn_08_11 & 1) == 1; + + rn_08_11 = rn_08_11 >> 1; +} + +:shlr2 rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00001001 +{ + rn_08_11 = rn_08_11 >> 2; +} + +:shlr8 rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00011001 +{ + rn_08_11 = rn_08_11 >> 8; +} + +:shlr16 rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00101001 +{ + rn_08_11 = rn_08_11 >> 16; +} + +# +# Branch Instructions +# +:bf target00_07 is opcode_08_15=0b10001011 & target00_07 +{ + if ($(T_FLAG) == 0) goto target00_07; +} + +@if (SH_VERSION == "2") || (SH_VERSION == "2A") +:bf"/s" target00_07 is opcode_08_15=0b10001111 & target00_07 +{ + local cond = $(T_FLAG); + delayslot(1); + if (cond==0) goto target00_07; +} +@endif + +:bt target00_07 is opcode_08_15=0b10001001 & target00_07 +{ + if ($(T_FLAG) == 1) goto target00_07; +} + +@if (SH_VERSION == "2") || (SH_VERSION == "2A") +:bt"/s" target00_07 is opcode_08_15=0b10001101 & target00_07 +{ + local cond = $(T_FLAG); + delayslot(1); + if (cond==1) goto target00_07; +} +@endif + +:bra target00_11 is opcode_12_15=0b1010 & target00_11 +{ + delayslot(1); + goto target00_11; +} + +@if (SH_VERSION == "2") || (SH_VERSION == "2A") +:braf rm_08_11 is opcode_12_15=0b0000 & rm_08_11 & opcode_00_07=0b00100011 +{ + local dest:4 = inst_start + 4 + rm_08_11; + delayslot(1); + goto [dest]; +} +@endif + +:bsr target00_11 is opcode_12_15=0b1011 & target00_11 +{ + local _pr:4 = inst_next; + + delayslot(1); + + pr = _pr; + call target00_11; +} + +@if (SH_VERSION == "2") || (SH_VERSION == "2A") +:bsrf rm_08_11 is opcode_12_15=0b0000 & rm_08_11 & opcode_00_07=0b00000011 +{ + local _pr = inst_next; + local dest = rm_08_11 + inst_next; + + delayslot(1); + + pr = _pr; + call [dest]; +} +@endif + +:jmp @rm_08_11 is opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00101011 +{ + local _pc:4 = rm_08_11; + delayslot(1); + pc = _pc; + goto [pc]; +} + +:jsr @rm_08_11 is opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00001011 +{ + local _pr:4 = inst_next; + local _pc:4 = rm_08_11; + + delayslot(1); + + pr = _pr; + pc = _pc; + call [_pc]; +} + +:rts is opcode_00_15=0b0000000000001011 +{ + local _pc = pr; + delayslot(1); + pc = _pc; + return [pc]; +} + +@if SH_VERSION == "2A" + +# JSR/N @Rm 0100mmmm01001011 PC - 2 → PR, Rm → PC +:jsr"/n" @rm_08_11 + is opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b01001011 +{ + pr = inst_next; + call [rm_08_11]; +} + +# JSR/N @@(disp8, TBR) 10000011dddddddd PC - 2 → PR, (disp×4+TBR) → PC +:jsr"/n" @@(disp, tbr) + is tbr & opcode_08_15=0b10000011 & disp_00_07 + [ disp = disp_00_07*4; ] +{ + pr = inst_next; + call [tbr + disp*4]; +} + +# RTS/N 0000000001101011 PR → PC +:rts"/n" + is opcode_00_15=0b0000000001101011 +{ + return [pr]; +} + +:rtv"/n" rm_08_11 is opcode_12_15=0b0000 & rm_08_11 & opcode_00_07=0b01111011 +{ + r0 = rm_08_11; + return [pr]; +} + +@endif + + +# +# System Control Instructions +# +:clrmac is opcode_00_15=0b0000000000101000 +{ + mach = 0; + macl = 0; +} + +:clrt is opcode_00_15=0b0000000000001000 +{ + $(T_FLAG) = 0; +} + +@if SH_VERSION == "2A" +:ldbank @rm_08_11, r0 is r0 & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b11100101 +{ + local cnt = *:4 (rm_08_11); + local bn = (cnt & 0x0000FF80) >> 7; + local en = (cnt & 0x0000007C) >> 2; + local off = (bn * 80) + en * 4; + + local rb = &resbank_base + off; + + r0 = *[register]:4 (rb); +} + +:stbank r0, @rn_08_11 is r0 & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b11100001 +{ + local cnt = *:4 (rn_08_11); + local bn = (cnt & 0x0000FF80) >> 7; + local en = (cnt & 0x0000007C) >> 2; + local off = (bn * 80) + en * 4; + + local rb = &resbank_base + off; + + *[register]:4 (rb) = r0; +} + +:resbank is opcode_00_15=0b0000000001011011 +{ + # This can be left as NOP, as it's used for saving/restoring context on interrupts + r0 = r0; +} + +@endif + +:ldc rm_08_11,sr is sr & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00001110 +{ + sr = rm_08_11 & 0x0FFF0FFF; +} + +:ldc.l @rm_08_11+,sr is sr & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00000111 +{ + sr = *rm_08_11 & 0x0FFF0FFF; + rm_08_11 = rm_08_11 + 4; + +} + +:ldc rm_08_11,gbr is gbr & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00011110 +{ + gbr = rm_08_11; +} + +@if SH_VERSION == "2A" +:ldc rm_08_11, tbr is tbr & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b01001010 +{ + tbr = rm_08_11; +} +@endif + +:ldc.l @rm_08_11+,gbr is gbr & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00010111 +{ + gbr = *rm_08_11; + rm_08_11 = rm_08_11 + 4; +} + +:ldc rm_08_11,vbr is vbr & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00101110 +{ + vbr = rm_08_11; +} + +:ldc.l @rm_08_11+,vbr is vbr & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00100111 +{ + vbr = *rm_08_11; + rm_08_11 = rm_08_11 + 4; +} + +:lds rm_08_11,mach is mach & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00001010 +{ + mach = rm_08_11; + +@if SH_VERSION == "1" + # sign extend 10 bit signed value from rm + mach = (mach << (32-10)) s>> (32-10); +@endif +} + +:lds.l @rm_08_11+,mach is mach & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00000110 +{ + mach = *rm_08_11; + +@if SH_VERSION == "1" + # sign extend 10 bit signed value from rm + mach = (mach << (32-10)) s>> (32-10); +@endif + + rm_08_11 = rm_08_11 + 4; +} + +:lds rm_08_11,macl is macl & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00011010 +{ + macl = rm_08_11; +} + +:lds.l @rm_08_11+,macl is macl & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00010110 +{ + macl = *rm_08_11; + rm_08_11 = rm_08_11 + 4; +} + +:lds rm_08_11,pr is pr & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00101010 +{ + pr = rm_08_11; +} + +:lds.l @rm_08_11+,pr is pr & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b00100110 +{ + pr = *rm_08_11; + rm_08_11 = rm_08_11 + 4; +} + +:nop is opcode_00_15=0b0000000000001001 +{ + # FIXME: intentional nop + r0 = r0; # do this to suppress warning +} + +:rte is opcode_00_15=0b0000000000101011 +{ + _pc:4 = *r15; + r15 = r15 + 4; + + _sr:4 = *r15 & 0x000063F3; + r15 = r15 + 4; + + delayslot(1); + + pc = _pc; + sr = _sr; + + return [pc]; +} + +:sett is opcode_00_15=0b0000000000011000 +{ + $(T_FLAG) = 1; +} + +define pcodeop Sleep_Standby; + +:sleep is opcode_00_15=0b0000000000011011 +{ + Sleep_Standby(); +} + +:stc sr,rn_08_11 is sr & opcode_12_15=0b0000 & rn_08_11 & opcode_00_07=0b00000010 +{ + rn_08_11 = sr; +} + +:stc.l sr,@-rn_08_11 is sr & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00000011 +{ + rn_08_11 = rn_08_11 -4; + *rn_08_11 = sr; +} + +:stc gbr,rn_08_11 is gbr & opcode_12_15=0b0000 & rn_08_11 & opcode_00_07=0b00010010 +{ + rn_08_11 = gbr; +} + +@if SH_VERSION == "2A" +:stc tbr,rn_08_11 is tbr & opcode_12_15=0b0000 & rn_08_11 & opcode_00_07=0b01001010 +{ + rn_08_11 = tbr; +} +@endif + +:stc.l gbr,@-rn_08_11 is gbr & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00010011 +{ + rn_08_11 = rn_08_11 -4; + *rn_08_11 = gbr; +} + +:stc vbr,rn_08_11 is vbr & opcode_12_15=0b0000 & rn_08_11 & opcode_00_07=0b00100010 +{ + rn_08_11 = vbr; +} + +:stc.l vbr,@-rn_08_11 is vbr & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00100011 +{ + rn_08_11 = rn_08_11 -4; + *rn_08_11 = vbr; +} + +:sts mach,rn_08_11 is mach & opcode_12_15=0b0000 & rn_08_11 & opcode_00_07=0b00001010 +{ + rn_08_11 = mach; + +@if SH_VERSION == "1" + # sign extend 10 bit signed value from rm + rn_08_11 = (rn_08_11 << (32-10)) s>> (32-10); +@endif +} + +:sts.l mach,@-rn_08_11 is mach & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00000010 +{ + rn_08_11 = rn_08_11 - 4; + + local temp = mach; + +@if SH_VERSION == "1" + # sign extend 10 bit signed value from rm + temp = (temp << (32-10)) s>> (32-10); +@endif + + *rn_08_11 = temp; +} + +:sts macl,rn_08_11 is macl & opcode_12_15=0b0000 & rn_08_11 & opcode_00_07=0b00011010 +{ + rn_08_11 = macl; +} + +:sts.l macl,@-rn_08_11 is macl & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00010010 +{ + rn_08_11 = rn_08_11 -4; + *rn_08_11 = macl; +} + +:sts pr,rn_08_11 is pr & opcode_12_15=0b0000 & rn_08_11 & opcode_00_07=0b00101010 +{ + rn_08_11 = pr; +} + +:sts.l pr,@-rn_08_11 is pr & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b00100010 +{ + rn_08_11 = rn_08_11 -4; + *rn_08_11 = pr; +} + +:trapa imm_00_07 is opcode_08_15=0b11000011 & imm_00_07 +{ + r15 = r15 - 4; + *r15 = sr; + + r15 = r15 - 4; + *r15 = pc + 2; + + pc = *(vbr + (imm_00_07 * 4)); + call [pc]; +} + +@if defined(FPU) + +# +# Floating-Point Instructions +# + +# FABS FRn 1111nnnn01011101 |FRn| → FRn +:fabs ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b01011101 +{ + ffrn_08_11 = abs(ffrn_08_11); +} + +# TODO: FABS DRn 1111nnn001011101 |DRn| → DRn + +# FADD FRm, FRn 1111nnnnmmmm0000 FRn + FRm → FRn +:fadd ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b0000 +{ + ffrn_08_11 = ffrn_08_11 f+ ffrm_04_07; +} + +# TODO: FADD DRm, DRn 1111nnn0mmm00000 DRn + DRm → DRn + +# FCMP/EQ FRm, FRn 1111nnnnmmmm0100 (FRn=FRm)? 1:0 → T +:fcmp"/eq" ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b0100 +{ + $(T_FLAG) = (ffrn_08_11 f== ffrm_04_07); +} + +# TODO: FCMP/EQ DRm, DRn 1111nnn0mmm00100 (DRn=DRm)? 1:0 → T + +# FCMP/GT FRm, FRn 1111nnnnmmmm0101 (FRn>FRm)? 1:0 → T +:fcmp"/gt" ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b0101 +{ + $(T_FLAG) = (ffrn_08_11 f> ffrm_04_07); +} + +# TODO: FCMP/GT DRm, DRn 1111nnn0mmm00101 (DRn>DRm)? 1:0 → T + +# FCNVDS DRm, FPUL 1111mmm010111101 (float) DRm → FPUL +:fcnvds fdrm_09_11, fpul is fpul & fop_12_15=0b1111 & fdrm_09_11 & fop_08_08=0b0 & fop_00_07=0b10111101 +{ + fpul = float2float(fdrm_09_11); +} + +# FCNVSD FPUL, DRn 1111nnn010101101 (double) FPUL → DRn +:fcnvsd fpul, fdrn_09_11 is fpul & fop_12_15=0b1111 & fdrn_09_11 & fop_08_08=0b0 & fop_00_07=0b10101101 +{ + fdrn_09_11 = float2float(fpul); +} + +# FDIV FRm, FRn 1111nnnnmmmm0011 FRn/FRm → FRn +:fdiv ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b0011 +{ + ffrn_08_11 = ffrn_08_11 f/ ffrm_04_07; +} + +# TODO: FDIV DRm, DRn 1111nnn0mmm00011 DRn/DRm → DRn + +# FLDI0 FRn 1111nnnn10001101 0 × 00000000 → FRn +:fldi0 ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b10001101 +{ + ffrn_08_11 = 0x00000000; +} + +# FLDI1 FRn 1111nnnn10011101 0 × 3F800000 → FRn +:fldi1 ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b10011101 +{ + ffrn_08_11 = 0x3F800000; +} + + +# FLDS FRm, FPUL 1111mmmm00011101 FRm → FPUL +:flds ffrm_08_11, fpul is fpul & fop_12_15=0b1111 & ffrm_08_11 & fop_00_07=0b00011101 +{ + fpul = ffrm_08_11; +} + +# FLOAT FPUL,FRn 1111nnnn00101101 (float) FPUL → FRn +:float fpul, ffrn_08_11 is fpul & fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b00101101 +{ + ffrn_08_11 = int2float(fpul); +} + +# TODO: FLOAT FPUL,DRn 1111nnn000101101 (double) FPUL → DRn + +# FMAC FR0, FRm, FRn 1111nnnnmmmm1110 FR0 × FRm + FRn → FRn +:fmac fr0, ffrm_04_07, ffrn_08_11 is fr0 & fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b1110 +{ + ffrn_08_11 = ffrn_08_11 f+ (ffrm_04_07 f* fr0); +} + +# FMOV FRm, FRn 1111nnnnmmmm1100 FRm → FRn +:fmov ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b1100 +{ + ffrn_08_11 = ffrm_04_07; +} + +# TODO: FMOV DRm, DRn 1111nnn0mmm01100 DRm → DRn + +# FMOV.S @(R0, Rm), FRn 1111nnnnmmmm0110 (R0+Rm) → FRn +:fmov.s @(r0, f_rm_04_07), ffrn_08_11 is r0 & fop_12_15=0b1111 & ffrn_08_11 & f_rm_04_07 & fop_00_03=0b0110 +{ + ffrn_08_11 = *:4 (r0 + f_rm_04_07); +} + +# TODO: FMOV.D @(R0, Rm), DRn 1111nnn0mmmm0110 (R0+Rm) → DRn + +# FMOV.S @Rm+, FRn 1111nnnnmmmm1001 (Rm) → FRn, Rm+ = 4 +:fmov.s @f_rm_04_07+, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & f_rm_04_07 & fop_00_03=0b1001 +{ + ffrn_08_11 = *:4 (f_rm_04_07); + f_rm_04_07 = f_rm_04_07 + 4; +} + +# TODO: FMOV.D @Rm+, DRn 1111nnn0mmmm1001 (Rm) → DRn, Rm+ = 8 + +# FMOV.S @Rm, FRn 1111nnnnmmmm1000 (Rm) → FRn +:fmov.s @f_rm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & f_rm_04_07 & fop_00_03=0b1000 +{ + ffrn_08_11 = *:4 (f_rm_04_07); +} + +# TODO: FMOV.D @Rm, DRn 1111nnn0mmmm1000 (Rm) → DRn + +# FMOV.S @(disp12,Rm),FRn 0011nnnnmmmm0001 0111dddddddddddd (disp×4+Rm) → FRn +:fmov.s @(disp12, lf_rm_20_23), lffrn_24_27 + is lfop_28_31=0b0011 & lffrn_24_27 & lf_rm_20_23 & lfop_12_19=0b00010111 & lfdisp_00_11 + [ disp12 = lfdisp_00_11 * 4; ] +{ + lffrn_24_27 = *:4 (disp12 + lf_rm_20_23); +} + +# TODO: FMOV.D @(disp12,Rm),DRn 0011nnn0mmmm0001 0111dddddddddddd (disp×8+Rm) → DRn + +# FMOV.S FRm, @( R0,Rn ) 1111nnnnmmmm0111 FRm → (R0+Rn) +:fmov.s ffrm_04_07, @( r0, f_rn_08_11 ) is r0 & fop_12_15=0b1111 & f_rn_08_11 & ffrm_04_07 & fop_00_03=0b0111 +{ + *:4 (f_rn_08_11 + r0) = ffrm_04_07; +} + +# TODO: FMOV.D DRm, @( R0,Rn ) 1111nnnnmmm00111 DRm → (R0+Rn) + +# FMOV.S FRm, @-Rn 1111nnnnmmmm1011 Rn- = 4, FRm → (Rn) +:fmov.s ffrm_04_07, @-f_rn_08_11 is fop_12_15=0b1111 & f_rn_08_11 & ffrm_04_07 & fop_00_03=0b1011 +{ + f_rn_08_11 = f_rn_08_11 - 4; + *:4 (f_rn_08_11) = ffrm_04_07; +} + +# TODO: FMOV.D DRm, @-Rn 1111nnnnmmm01011 Rn- = 8, DRm → (Rn) + +# FMOV.S FRm, @Rn 1111nnnnmmmm1010 FRm → (Rn) +:fmov.s ffrm_04_07, @f_rn_08_11 is fop_12_15=0b1111 & f_rn_08_11 & ffrm_04_07 & fop_00_03=0b1010 +{ + *:4 (f_rn_08_11) = ffrm_04_07; +} + +# TODO: FMOV.D DRm, @Rn 1111nnnnmmm01010 DRm → (Rn) + +# FMOV.S FRm, @(disp12,Rn) 0011nnnnmmmm0001 0011dddddddddddd FRm → (disp×4+Rn) +:fmov.s lffrm_20_23, @(disp12, lf_rn_24_27) + is lfop_28_31=0b0011 & lf_rn_24_27 & lffrm_20_23 & lfop_12_19=0b00010011 & lfdisp_00_11 + [ disp12 = lfdisp_00_11 * 4; ] +{ + *:4 (disp12 + lf_rn_24_27) = lffrm_20_23; +} + + +# TODO: FMOV.D DRm, @(disp12,Rn) 0011nnnnmmm000010 011dddddddddddd DRm → (disp×8+Rn) + +# FMUL FRm, FRn 1111nnnnmmmm0010 FRn × FRm → FRn +:fmul ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b0010 +{ + ffrn_08_11 = ffrn_08_11 f* ffrm_04_07; +} + +# TODO: FMUL DRm, DRn 1111nnn0mmm00010 DRn × DRm → DRn +# FNEG FRn 1111nnnn01001101 -FRn → FRn +:fneg ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b01001101 +{ + ffrn_08_11 = f- ffrn_08_11; +} + +# TODO: FNEG DRn 1111nnn001001101 -DRn → DRn +# FSCHG 1111001111111101 FPSCR.SZ = ~ FPSCR.SZ +:fschg is fop_00_15=0b1111001111111101 +{ + $(FP_SZ) = ~ $(FP_SZ); +} + +# FSQRT FRn 1111nnnn01101101 √FRn → FRn +:fsqrt ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b01101101 +{ + ffrn_08_11 = sqrt(ffrn_08_11); +} + +# TODO: FSQRT DRn 1111nnn001101101 √DRn → DRn +# FSTS FPUL, FRn 1111nnnn00001101 FPUL → FRn +:fsts fpul, ffrn_08_11 is fpul & fop_12_15=0b1111 & ffrn_08_11 & fop_00_07=0b00001101 +{ + ffrn_08_11 = fpul; +} + +# FSUB FRm, FRn 1111nnnnmmmm0001 FRn - FRm → FRn +:fsub ffrm_04_07, ffrn_08_11 is fop_12_15=0b1111 & ffrn_08_11 & ffrm_04_07 & fop_00_03=0b0001 +{ + ffrn_08_11 = ffrn_08_11 f- ffrm_04_07; +} + +# TODO: FSUB DRm, DRn 1111nnn0mmm00001 DRn - DRm → DRn + +# FTRC FRm, FPUL 1111mmmm00111101 (long) FRm → FPUL +:ftrc ffrm_08_11, fpul is fpul & fop_12_15=0b1111 & ffrm_08_11 & fop_00_07=0b00111101 +{ + fpul = trunc(ffrm_08_11); +} + +# FTRC DRm, FPUL 1111mmm000111101 (long) DRm → FPUL + +@endif + + +@if defined(FPU) + +# +# FPU-related CPU Instructions +# + +# LDS Rm,FPSCR 0100mmmm01101010 Rm → FPSCR +:lds rm_08_11, fpscr is fpscr & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b01101010 +{ + fpscr = rm_08_11; +} + +# LDS Rm,FPUL 0100mmmm01011010 Rm → FPUL +:lds rm_08_11, fpul is fpul & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b01011010 +{ + fpul = rm_08_11; +} + +# LDS.L @Rm+, FPSCR 0100mmmm01100110 (Rm) → FPSCR, Rm+ = 4 +:lds.l @rm_08_11+, fpscr is fpscr & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b01100110 +{ + fpscr = *:4 (rm_08_11); + rm_08_11 = rm_08_11 + 4; +} + +# LDS.L @Rm+, FPUL 0100mmmm01010110 (Rm) → FPUL, Rm+ = 4 +:lds.l @rm_08_11+, fpul is fpul & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b01010110 +{ + fpul = *:4 (rm_08_11); + rm_08_11 = rm_08_11 + 4; +} + +# STS FPSCR, Rn 0000nnnn01101010 FPSCR → Rn +:sts fpscr, rn_08_11 is fpscr & opcode_12_15=0b0000 & rn_08_11 & opcode_00_07=0b01101010 +{ + rn_08_11 = fpscr; +} + +# STS FPUL,Rn 0000nnnn01011010 FPUL → Rn +:sts fpul, rn_08_11 is fpul & opcode_12_15=0b0000 & rn_08_11 & opcode_00_07=0b01011010 +{ + rn_08_11 = fpul; +} + +# STS.L FPSCR,@-Rn 0100nnnn01100010 Rn- = 4, fpscr → (Rn) +:sts.l fpscr, @-rn_08_11 is fpscr & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b01100010 +{ + rn_08_11 = rn_08_11 - 4; + *:4 (rn_08_11) = fpscr; +} + +# STS.L FPUL,@-Rn 0100nnnn01010010 Rn- = 4, FPUL → (Rn) +:sts.l fpul, @-rn_08_11 is fpul & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b01010010 +{ + rn_08_11 = rn_08_11 - 4; + *:4 (rn_08_11) = fpul; +} + +# @if defined(FPU) +@endif + + +@if SH_VERSION == "2A" + +# +# Bit Manipulation Instructions +# +# The BAND.B, BOR.B, and BXOR.B instructions perform logical operations between a bit in +# memory and the T bit, and store the result in the T bit. The BCLR.B and BSET.B instructions +# manipulate a bit in memory. The BST.B and BLD.B instructions execute a transfer between a bit +# in memory and the T bit. The BANDNOT.B and BORNOT.B instructions perform logical +# operations between the value resulting from inverting a bit in memory and the T bit, and store the +# result in the T bit. The BLDNOT.B instruction inverts a bit in memory and stores the result in the +# T bit. Bits other than the specified bit are not affected. +# + +# BAND.B #imm3, @(disp12,Rn) 0011nnnn0iii1001 0100dddddddddddd (imm of (disp+Rn)) & T → T +:band.b "#"l_imm3_20_22 @(l_disp_00_11, l_rn_24_27) + is l_opcode_28_31=0b0011 & l_rn_24_27 & l_opcode_23_23=0b0 & l_imm3_20_22 & l_opcode_16_19=0b1001 & l_opcode_12_15=0b0100 & l_disp_00_11 +{ + local b = *:1 (l_disp_00_11 + l_rn_24_27); + $(T_FLAG) = ((b & (1 << l_imm3_20_22)) & $(T_FLAG) != 0); +} + +# BANDNOT.B #imm3, @(disp12,Rn) 0011nnnn0iii1001 1100dddddddddddd ~ (imm of (disp+Rn)) & T → T +:bandnot.b "#"l_imm3_20_22, @(l_disp_00_11, l_rn_24_27) + is l_opcode_28_31=0b0011 & l_rn_24_27 & l_opcode_23_23=0b0 & l_imm3_20_22 & l_opcode_16_19=0b1001 & l_opcode_12_15=0b1100 & l_disp_00_11 +{ + local b = *:1 (l_disp_00_11 + l_rn_24_27); + $(T_FLAG) = ((~ (b & (1 << l_imm3_20_22)) & $(T_FLAG)) != 0); +} + +# BCLR.B #imm3, @(disp12,Rn) 0011nnnn0iii1001 0000dddddddddddd 0 → (imm of (disp+Rn)) +:bclr.b "#"l_imm3_20_22, @(l_disp_00_11, l_rn_24_27) + is l_opcode_28_31=0b0011 & l_rn_24_27 & l_opcode_23_23=0b0 & l_imm3_20_22 & l_opcode_16_19=0b1001 & l_opcode_12_15=0b0000 & l_disp_00_11 +{ + local addr = l_disp_00_11 + l_rn_24_27; + local b = *:1 (addr); + *:1 (addr) = b & (~(1 << l_imm3_20_22)); +} + +# BCLR #imm3, Rn 10000110nnnn0iii 0 → imm of Rn +:bclr "#"imm3_00_02, rn_04_07 + is opcode_08_15=0b10000110 & rn_04_07 & opcode_03_03=0b0 & imm3_00_02 +{ + local b = *:1 (rn_04_07); + *:1 (rn_04_07) = b & (~(1 << imm3_00_02)); +} + +# BLD.B #imm3, @(disp12,Rn) 0011nnnn0iii1001 0011dddddddddddd (imm of (disp+Rn)) → T +:bld.b "#"l_imm3_20_22, @(l_disp_00_11, l_rn_24_27) + is l_opcode_28_31=0b0011 & l_rn_24_27 & l_opcode_23_23=0b0 & l_imm3_20_22 & l_opcode_16_19=0b1001 & l_opcode_12_15=0b0011 & l_disp_00_11 +{ + local b = *:1 (l_disp_00_11 + l_rn_24_27); + $(T_FLAG) = ((b & (1 << l_imm3_20_22)) != 0); +} + +# BLD #imm3, Rn 10000111nnnn1iii imm of Rn → T +:bld "#"imm3_00_02, rn_04_07 + is opcode_08_15=0b10000111 & rn_04_07 & opcode_03_03=0b1 & imm3_00_02 +{ + local b = rn_04_07; + $(T_FLAG) = ((b & (1 << imm3_00_02)) != 0); +} + +# BLDNOT.B #imm3, @(disp12,Rn) 0011nnnn0iii1001 1011dddddddddddd ~ (imm of (disp+Rn)) → T +:bldnot.b "#"l_imm3_20_22, @(l_disp_00_11, l_rn_24_27) + is l_opcode_28_31=0b0011 & l_rn_24_27 & l_opcode_23_23=0b0 & l_imm3_20_22 & l_opcode_16_19=0b1001 & l_opcode_12_15=0b1011 & l_disp_00_11 +{ + local b = *:1 (l_disp_00_11 + l_rn_24_27); + $(T_FLAG) = ((b & (1 << l_imm3_20_22)) == 0); +} + +# BOR.B #imm3, @(disp12,Rn) 0011nnnn0iii1001 0101dddddddddddd (imm of (disp+ Rn)) | T → T +:bor.b "#"l_imm3_20_22, @(l_disp_00_11, l_rn_24_27) + is l_opcode_28_31=0b0011 & l_rn_24_27 & l_opcode_23_23=0b0 & l_imm3_20_22 & l_opcode_16_19=0b1001 & l_opcode_12_15=0b0101 & l_disp_00_11 +{ + local b = *:1 (l_disp_00_11 + l_rn_24_27); + local abit = b & (1 << l_imm3_20_22); + $(T_FLAG) = $(T_FLAG) | (abit != 0); +} + +# BORNOT.B #imm3, @(disp12,Rn) 0011nnnn0iii1001 1101dddddddddddd ~ (imm of (disp+ Rn)) | T → T +:bornot.b "#"l_imm3_20_22, @(l_disp_00_11, l_rn_24_27) + is l_opcode_28_31=0b0011 & l_rn_24_27 & l_opcode_23_23=0b0 & l_imm3_20_22 & l_opcode_16_19=0b1001 & l_opcode_12_15=0b1101 & l_disp_00_11 +{ + local b = *:1 (l_disp_00_11 + l_rn_24_27); + local abit = b & (1 << l_imm3_20_22); + $(T_FLAG) = $(T_FLAG) | (abit == 0); +} + +# BSET.B #imm3, @(disp12,Rn) 0011nnnn0iii1001 0001dddddddddddd 1 → (imm of (disp+Rn)) +:bset.b "#"l_imm3_20_22, @(l_disp_00_11, l_rn_24_27) + is l_opcode_28_31=0b0011 & l_rn_24_27 & l_opcode_23_23=0b0 & l_imm3_20_22 & l_opcode_16_19=0b1001 & l_opcode_12_15=0b0001 & l_disp_00_11 +{ + local b = *:1 (l_disp_00_11 + l_rn_24_27); + local newb = b | (1 << l_imm3_20_22); + *:1 (l_disp_00_11 + l_rn_24_27) = newb; +} + +# BSET #imm3, Rn 10000110nnnn1iii 1 → imm of Rn +:bset "#"imm3_00_02, rn_04_07 + is opcode_08_15=0b10000110 & rn_04_07 & opcode_03_03=0b1 & imm3_00_02 +{ + rn_04_07 = rn_04_07 | (1 << imm3_00_02); +} + +# BST.B #imm3 ,@(disp12,Rn) 0011nnnn0iii1001 0010dddddddddddd T → (imm of (disp+Rn)) +:bst.b "#"l_imm3_20_22, @(l_disp_00_11, l_rn_24_27) + is l_opcode_28_31=0b0011 & l_rn_24_27 & l_opcode_23_23=0b0 & l_imm3_20_22 & l_opcode_16_19=0b1001 & l_opcode_12_15=0b0010 & l_disp_00_11 +{ + local b = *:1 (l_disp_00_11 + l_rn_24_27); + local ibit = 1 << l_imm3_20_22; + b = (b | ibit) * ($(T_FLAG) != 0) + (b & (~ibit)) * ($(T_FLAG) == 0); + *:1 (l_disp_00_11 + l_rn_24_27) = b; +} + +# BST #imm3, Rn 10000111nnnn0iii T → imm of Rn +:bst "#"imm3_00_02, rn_04_07 + is opcode_08_15=0b10000111 & rn_04_07 & opcode_03_03=0b0 & imm3_00_02 +{ + local ibit = 1 << imm3_00_02; + rn_04_07 = (rn_04_07 | ibit) * zext($(T_FLAG) != 0) + (rn_04_07 & (~ibit)) * zext($(T_FLAG) == 0); +} + +# BXOR.B #imm3, @(disp12, Rn) 0011nnnn0iii1001 0110dddddddddddd (imm of (disp+ Rn)) ^ T → T +:bxor.b "#"l_imm3_20_22, @(l_disp_00_11, l_rn_24_27) + is l_opcode_28_31=0b0011 & l_rn_24_27 & l_opcode_23_23=0b0 & l_imm3_20_22 & l_opcode_16_19=0b1001 & l_opcode_12_15=0b0110 & l_disp_00_11 +{ + # extract bit to test + local b = *:1 (l_rn_24_27 + l_disp_00_11); + local abit = (b >> l_imm3_20_22) & 1; + + $(T_FLAG) = $(T_FLAG) ^ abit; +} + +@endif diff --git a/python/icicle/Ghidra/Processors/SuperH/data/languages/superh2a.cspec b/python/icicle/Ghidra/Processors/SuperH/data/languages/superh2a.cspec new file mode 100644 index 0000000..0114e1f --- /dev/null +++ b/python/icicle/Ghidra/Processors/SuperH/data/languages/superh2a.cspec @@ -0,0 +1,88 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/SuperH4/data/languages/SuperH4.ldefs b/python/icicle/Ghidra/Processors/SuperH4/data/languages/SuperH4.ldefs new file mode 100644 index 0000000..d51da4f --- /dev/null +++ b/python/icicle/Ghidra/Processors/SuperH4/data/languages/SuperH4.ldefs @@ -0,0 +1,33 @@ + + + + + SuperH-4(a) (SH4) big endian + + + + + + SuperH-4(a) (SH4) little endian + + + + + + diff --git a/python/icicle/Ghidra/Processors/SuperH4/data/languages/SuperH4.opinion b/python/icicle/Ghidra/Processors/SuperH4/data/languages/SuperH4.opinion new file mode 100644 index 0000000..42cc3a7 --- /dev/null +++ b/python/icicle/Ghidra/Processors/SuperH4/data/languages/SuperH4.opinion @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/SuperH4/data/languages/SuperH4.pspec b/python/icicle/Ghidra/Processors/SuperH4/data/languages/SuperH4.pspec new file mode 100644 index 0000000..41d2129 --- /dev/null +++ b/python/icicle/Ghidra/Processors/SuperH4/data/languages/SuperH4.pspec @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/SuperH4/data/languages/SuperH4.sinc b/python/icicle/Ghidra/Processors/SuperH4/data/languages/SuperH4.sinc new file mode 100644 index 0000000..039d05f --- /dev/null +++ b/python/icicle/Ghidra/Processors/SuperH4/data/languages/SuperH4.sinc @@ -0,0 +1,3133 @@ +# This module defines SuperH version 4, but should work against versions 1,2, and 3. +# There is a SuperH version 4A (which has 4 byte instruction length) which has instructions incompatable +# with this. + +# Based on "Renesas SH-4 Software Manual: Rev 6.00 2006.09 (i.e. rej09b0318_sh_4sm.pdf) + +# Here's a nice webpage with all the insns clearly shown +# http://shared-ptr.com/sh_insns.html + +# Address Space: +# SuperH 4A has a 29-bit and a 32-bit address space mode, +# and can do 32-bit addressing in 29-bit mode with virtual addressing. +# The SH4 has a 29-bit physical address space, but can do 32-bit with virtual addressing. +# +# WARNING: +# WARNING: +# WARNING: Currently set up for 29-bit only for computed jumps/calls. This needs to be configurable. +# WARNING: + +# NOTE: SuperH 4 and floating point disassembly and decompiling precision. +# Many of the floating point instructions can do either single or double precision calculations depending +# on a flag FPSCR_PR at runtime. This means at disassembly stage we don't have all the information required +# determine the arguments to some floating point instructions. + +# NOTE: SuperH 4 and floating point disassembly and decompiling (fmov lengths). +# Some of the instructions can read and write floating point values in 4 or 8 byte values depending on the +# flag FPSCR_SZ. This means at disassembly stage we don't have all the information required to determine the +# arguments to some floating point instructions. +# Note that the FPSCR_PR flag is never examined during any of the fmov insns. + +# NOTE: SuperH and banking +# When the RB flag is not set R1->R7 come from bank0 and when RB is set R1->R7 come from bank1. The RB mode is +# set in privileged mode. We don't currently simulate this behavior. + +# NOTE: SuperH and floating point banking +# When the flag FPSCR_FR is not set fr0->fr15 come from bank0 and when FPSCR.FR is set fr0->fr15 come from bank1. +# We don't currently simulate this behavior. + +# NOTE: SuperH and memory map registers +# There are 7 32bit control registers (SR, GBR, SSR, SPC, SGR, DBR, VBR) these are mapped to 2 different memory +# areas 0x1C000000 and 0xFC000000. We don't currently simulate this behavior. + +# NOTE: SuperH/Renesas return value convention. +# Renesas and gcc return most values from a function in r0 but floats are return in fr0 and doubles in dr0. +# Ghidra calling spec has no way of specifying this behavior so such return values are not handled correctly. + +# NOTE: SuperH/Renesas calling convention +# Renesas and gcc pass most values to a function via r4-r7 but floats are passed by fr4-fr7 and doubles in +# dr4, dr6, dr8, and dr10. + +# NOTE: floating point errors +# In implementing the floating point pcode we ignored many of the possible error conditions floating point +# could cause. This allows us to produce much better looking decompiled code. + +# NOTE: SuperH 4 Memory model +# SuperH 4 has a Memory Management Unit (i.e. MMU). Which means that depending on mode the memory can +# look very different. We don't model this behavior. We also don't simulate the MMU address translation, +# so all addresses are raw. + + +# Basic ================================================================================ + +define endian=$(ENDIAN); # Defined in file that includes this file + +define alignment=2; + +define space ram type=ram_space size=4 default; +define space register type=register_space size=4; + +# Registers ============================================================================ +# TODO deal with the 2 banks of registers +# TODO move os corret memory address +define register offset=0 size=4 [ + r0 r1 r2 r3 r4 r5 r6 r7 + r8 r9 r10 r11 r12 r13 r14 r15 + R0_BANK R1_BANK R2_BANK R3_BANK R4_BANK R5_BANK R6_BANK R7_BANK +]; + +# This is where "BANK0" is with RB=0 (normal), causes duplicate pair error in SLEIGH +#define register offset=0 size=4 [ +# R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 +#]; +# This is where "BANK1" is with RB=1 (privileged), causes duplicate pair error in SLEIGH +#define register offset=0 size=4 [ +# R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 +#]; +@if ENDIAN == "big" +define register offset=512 size=4 [ + fr0 fr1 fr2 fr3 fr4 fr5 fr6 fr7 fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15 + xf0 xf1 xf2 xf3 xf4 xf5 xf6 xf7 xf8 xf9 xf10 xf11 xf12 xf13 xf14 xf15 +]; + +@endif + +@if ENDIAN == "little" +define register offset=512 size=4 [ + fr1 fr0 fr3 fr2 fr5 fr4 fr7 fr6 fr9 fr8 fr11 fr10 fr13 fr12 fr15 fr14 + xf0 xf1 xf2 xf3 xf4 xf5 xf6 xf7 xf8 xf9 xf10 xf11 xf12 xf13 xf14 xf15 +]; + +@endif + +define register offset=512 size=8 [ + dr0 dr2 dr4 dr6 dr8 dr10 dr12 dr14 + xd0 xd2 xd4 xd6 xd8 xd10 xd12 xd14 +]; + +define register offset=512 size=16 [ + fv0 fv4 fv8 fv12 +]; + +# Control registers +define register offset=1024 size=4 [ + GBR SR SSR SPC VBR SGR DBR +]; + +# SR component register fields (pseudo) +define register offset=1536 size=1 [ + MD RB BL FD M Q IMASK S T +]; + +# System registers +define register offset=2048 size=4 [ + MACH MACL PR PC FPSCR FPUL +]; + +# FPSCR component register fields (pseudo) +define register offset=2560 size=1 [ + FPSCR_RM + FPSCR_FLAG + FPSCR_ENABLE + FPSCR_CAUSE + FPSCR_DN + FPSCR_PR + FPSCR_SZ + FPSCR_FR +]; + +@define T_FLAG "T" +@define S_FLAG "S" +@define IMASK "IMASK" +@define Q_FLAG "Q" +@define M_FLAG "M" +@define FD_FLAG "FD" +@define BL_FLAG "BL" +@define RB_FLAG "RB" +@define MD_FLAG "MD" + +@define FPSCR_RM "FPSCR_RM" +@define FPSCR_FLAG "FPSCR_FLAG" +@define FPSCR_ENABLE "FPSCR_ENABLE" +@define FPSCR_CAUSE "FPSCR_CAUSE" +@define FPSCR_DN "FPSCR_DN" +@define FPSCR_PR "FPSCR_PR" +@define FPSCR_SZ "FPSCR_SZ" +@define FPSCR_FR "FPSCR_FR" + +# +# SR pack and unpack support +# + +# 0000 0000 0000 0000 0000 0000 0000 0001 +@define T_MASK "0x00000001" + +# 0000 0000 0000 0000 0000 0000 0000 0010 +@define S_MASK "0x00000002" + +# 0000 0000 0000 0000 0000 0000 1111 0000 +@define IMASK_MASK "0x000000F0" + +# 0000 0000 0000 0000 0000 0001 0000 0000 +@define Q_MASK "0x00000100" + +# 0000 0000 0000 0000 0000 0010 0000 0000 +@define M_MASK "0x00000200" + +# 0000 0000 0000 0000 1000 0000 0000 0000 +@define FD_MASK "0x00008000" + +# 0001 0000 0000 0000 0000 0000 0000 0000 +@define BL_MASK "0x10000000" + +# 0010 0000 0000 0000 0000 0000 0000 0000 +@define RB_MASK "0x20000000" + +# 0100 0000 0000 0000 0000 0000 0000 0000 +@define MD_MASK "0x40000000" + +@define T_SHIFT " 0" +@define S_SHIFT " 1" +@define IMASK_SHIFT " 4" +@define Q_SHIFT " 8" +@define M_SHIFT " 9" +@define FD_SHIFT "15" +@define BL_SHIFT "28" +@define RB_SHIFT "29" +@define MD_SHIFT "30" + +macro genSRregister() { + + SR = + (zext(T) << $(T_SHIFT)) | + (zext(S) << $(S_SHIFT)) | + (zext(IMASK) << $(IMASK_SHIFT)) | + (zext(Q) << $(Q_SHIFT)) | + (zext(M) << $(M_SHIFT)) | + (zext(FD) << $(FD_SHIFT)) | + (zext(BL) << $(BL_SHIFT)) | + (zext(RB) << $(RB_SHIFT)) | + (zext(MD) << $(MD_SHIFT)); +} + +macro splitSRregister() { + + splitTemp:4 = (SR & $(T_MASK)) >> $(T_SHIFT); + T = splitTemp:1; + + splitTemp = (SR & $(S_MASK)) >> $(S_SHIFT); + S = splitTemp:1; + + splitTemp = (SR & $(IMASK_MASK)) >> $(IMASK_SHIFT); + IMASK = splitTemp:1; + + splitTemp = (SR & $(Q_MASK)) >> $(Q_SHIFT); + Q = splitTemp:1; + + splitTemp = (SR & $(M_MASK)) >> $(M_SHIFT); + M = splitTemp:1; + + splitTemp = (SR & $(FD_MASK)) >> $(FD_SHIFT); + FD = splitTemp:1; + + splitTemp = (SR & $(BL_MASK)) >> $(BL_SHIFT); + BL = splitTemp:1; + + splitTemp = (SR & $(RB_MASK)) >> $(RB_SHIFT); + RB = splitTemp:1; + + splitTemp = (SR & $(MD_MASK)) >> $(MD_SHIFT); + MD = splitTemp:1; +} + +# +# FPSCR pack and unpack support +# +@define FPSCR_RM_SHIFT " 0" +@define FPSCR_FLAG_SHIFT " 2" +@define FPSCR_ENABLE_SHIFT " 7" +@define FPSCR_CAUSE_SHIFT "12" +@define FPSCR_DN_SHIFT "18" +@define FPSCR_PR_SHIFT "19" +@define FPSCR_SZ_SHIFT "20" +@define FPSCR_FR_SHIFT "21" + + +# 0000 0000 0000 0000 0000 0000 0000 0011 +@define FPSCR_RM_MASK "0x00000003" + +# 0000 0000 0000 0000 0000 0000 0111 1100 +@define FPSCR_FLAG_MASK "0x0000007C" + +# 0000 0000 0000 0000 0000 1111 1000 0000 +@define FPSCR_ENABLE_MASK "0x00000F80" + +# 0000 0000 0000 0011 1111 0000 0000 0000 +@define FPSCR_CAUSE_MASK "0x0003F000" + +# 0000 0000 0000 0100 0000 0000 0000 0000 +@define FPSCR_DN_MASK "0x00040000" + +# 0000 0000 0000 1000 0000 0000 0000 0000 +@define FPSCR_PR_MASK "0x00080000" + +# 0000 0000 0001 0000 0000 0000 0000 0000 +@define FPSCR_SZ_MASK "0x00100000" + +# 0000 0000 0010 0000 0000 0000 0000 0000 +@define FPSCR_FR_MASK "0x00200000" + +# Bits 22-31 are not used + +macro genFPSCRregister() { + + FPSCR = + (zext(FPSCR_RM) << $(FPSCR_RM_SHIFT)) | + (zext(FPSCR_FLAG) << $(FPSCR_FLAG_SHIFT)) | + (zext(FPSCR_ENABLE) << $(FPSCR_ENABLE_SHIFT)) | + (zext(FPSCR_CAUSE) << $(FPSCR_CAUSE_SHIFT)) | + (zext(FPSCR_DN) << $(FPSCR_DN_SHIFT)) | + (zext(FPSCR_PR) << $(FPSCR_PR_SHIFT)) | + (zext(FPSCR_SZ) << $(FPSCR_SZ_SHIFT)) | + (zext(FPSCR_FR) << $(FPSCR_FR_SHIFT)); +} + +macro splitFPSCRregister() { + + splitTemp:4 = (FPSCR & $(FPSCR_RM_MASK)) >> $(FPSCR_RM_SHIFT); + FPSCR_RM = splitTemp:1; + + splitTemp = (FPSCR & $(FPSCR_FLAG_MASK)) >> $(FPSCR_FLAG_SHIFT); + FPSCR_FLAG = splitTemp:1; + + splitTemp = (FPSCR & $(FPSCR_ENABLE_MASK)) >> $(FPSCR_ENABLE_SHIFT); + FPSCR_ENABLE = splitTemp:1; + + splitTemp = (FPSCR & $(FPSCR_CAUSE_MASK)) >> $(FPSCR_CAUSE_SHIFT); + FPSCR_CAUSE = splitTemp:1; + + splitTemp = (FPSCR & $(FPSCR_DN_MASK)) >> $(FPSCR_DN_SHIFT); + FPSCR_DN = splitTemp:1; + + splitTemp = (FPSCR & $(FPSCR_PR_MASK)) >> $(FPSCR_PR_SHIFT); + FPSCR_PR = splitTemp:1; + + splitTemp = (FPSCR & $(FPSCR_SZ_MASK)) >> $(FPSCR_SZ_SHIFT); + FPSCR_SZ = splitTemp:1; + + splitTemp = (FPSCR & $(FPSCR_FR_MASK)) >> $(FPSCR_FR_SHIFT); + FPSCR_FR = splitTemp:1; +} + +# Fields ================================================================================= +define token instr(16) + OP_0 = (12,15) + OP_1 = ( 0, 3) + OP_2 = ( 8,15) + OP_3 = ( 0,15) + OP_4 = ( 0, 7) + OP_5 = ( 0, 8) + OP_6 = ( 8, 8) + OP_7 = ( 0, 4) + OP_8 = ( 0, 9) + OP_9 = ( 7, 7) + OP_10 = ( 4, 4) + + BANK = ( 4, 6) # bank register id + M_0 = ( 4, 7) # register id + M_1 = ( 5, 7) # register id + M_2 = ( 8, 9) # register id + FRM_0 = ( 4, 7) # float register id + DRM_1 = ( 5, 7) # double register id + XDM_1 = ( 5, 7) # double register id + XDRM = ( 4, 7) # double register id + FVM_2 = ( 8, 9) # fv register id + N_0 = ( 8,11) # register id + N_1 = ( 9,11) # register id + N_2 = (10,11) # register id + FRN_0 = ( 8,11) # float register id + FRN_1 = ( 8,10) # float register id + FRN_2 = ( 8,10) # float register id + DRN_0 = ( 8,10) # double register id + DRN_1 = ( 9,11) # double register id + XDN_1 = ( 9,11) # double register id + XDRN = ( 8,11) # float register id + FVN_2 = (10,11) # fv register id + I_0 = ( 0, 7) signed # immediate + I_1 = ( 0,11) signed # immediate + I_2 = ( 0, 3) signed # immediate + U_0 = ( 0, 7) # immediate + U_1 = ( 0,11) # immediate + U_2 = ( 0, 3) # immediate +; + +# Context variables ==================================================== +# Attach variables ===================================================== +# attach normal registers +attach variables [ N_0 M_0 ] [ + r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 +]; + +# attach float registers +attach variables [ FRN_0 FRM_0] [ + fr0 fr1 fr2 fr3 fr4 fr5 fr6 fr7 fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15 +]; + +attach variables [ FRN_1 ] [ + fr0 fr2 fr4 fr6 fr8 fr10 fr12 fr14 +]; + +attach variables [ FRN_2 ] [ + fr1 fr3 fr5 fr7 fr9 fr11 fr13 fr15 +]; + +# attach double registers +attach variables [ DRN_1 DRM_1 ] [ + dr0 dr2 dr4 dr6 dr8 dr10 dr12 dr14 +]; + +# attach double registers +attach variables [ DRN_0 ] [ + dr0 dr2 dr4 dr6 dr8 dr10 dr12 dr14 +]; + +# attach extended double registers +attach variables [ XDN_1 XDM_1 ] [ + xd0 xd2 xd4 xd6 xd8 xd10 xd12 xd14 +]; + +attach variables [ XDRN XDRM ] [ + dr0 xd0 dr2 xd2 dr4 xd4 dr6 xd6 dr8 xd8 dr10 xd10 dr12 xd12 dr14 xd14 +]; + +# attach vf registers +attach variables [ FVN_2 FVM_2 ] [ + fv0 fv4 fv8 fv12 +]; + +attach variables [ BANK ] [ + R0_BANK R1_BANK R2_BANK R3_BANK R4_BANK R5_BANK R6_BANK R7_BANK +]; + +# Tables ================================================================ +# Addressing Modes +# +# Register direct +# Rn EA is Rn. +# +# Register indirect +# @Rn Rn contains EA +# +# Register indirect with postincrement +# @Rn+ Rn contains EA +# After EA calculation: +# increment Rn by 1 for byte, 2 for word, 4 for long word, 8 quadword operand +# +# Register indirect with predecrement +# @-Rn Rn contains EA, +# Before EA calculation: +# increment Rn by 1 for byte, 2 for word, 4 for long word, 8 quadword operand +# +# Register indirect with displacement +# @(disp:4, Rn) EA is Rn + 4-bit displacement disp added. disp is zero extended, +# then multiplied by 1 for byte, 2 for word, 4 for long word operand size +# +# Indexed register indirect +# @(R0, Rn) EA is Rn + R0 +# +# GBR indirect with displacement +# @(disp:8,GBR) EA is GBR contents with 8-bit displacement added. +# 8-bit displacement disp added. disp is zero extended, +# then multiplied by 1 for byte, 2 for word, 4 for long word operand size +# +# Indexed GBR indirect +# @(R0, GBR) EA is GBR + R0 +# +# PC-relative with displacement +# @(disp:8, PC) EA is PC+4 + 8bit displacement. disp is zero extended, +# then multiplied by 1 for byte, 2 for word, 4 for long word operand size +# +# PC-relative +# disp:8 EA is PC+4 + 8-bit displacement. +# disp is sign-extended and multiplied by 2. +# +# PC-relative +# disp:12 EA is PC+4 + 12-bit displacement. +# disp is sign-extended and multiplied by 2. +# +# Rn EA is PC+4 + Rn. +# +M_0t: M_0 is M_0 { export M_0; } + +N_0t: N_0 is N_0 { export N_0; } + +N_0tjmp: @^N_0 is N_0 { export N_0; } + +I_0t: "#"^I_0 is I_0 { tmp:4 = I_0; export tmp; } + +U_0t: "#"^U_0 is U_0 { tmp:4 = U_0; export tmp; } +U_0t1: "#"^U_0^",@("^r0^","^GBR^")" is U_0 & r0 & GBR { tmp:1 = U_0; export tmp; } + +I_0t_r0: "#"I_0^","^r0 is I_0 & r0 { tmp:4 = I_0; export tmp; } + +U_0t_r0: "#"U_0^","^r0 is U_0 & r0 { tmp:4 = U_0; export tmp; } + +I_0tbranch: dest is I_0 [ dest = inst_start + I_0*2 + 4; ] { export *:4 dest; } + +I_1tbranch: dest is I_1 [ dest = inst_start + I_1*2 + 4; ] { export *:4 dest; } + +sr_N_0t: SR^","^N_0 is N_0 & SR { export N_0; } + +gbr_N_0t: GBR^","^N_0 is N_0 & GBR { export N_0; } + +vbr_N_0t: VBR^","^N_0 is N_0 & VBR { export N_0; } + +ssr_N_0t: SSR^","^N_0 is N_0 & SSR { export N_0; } + +spc_N_0t: SPC^","^N_0 is N_0 & SPC { export N_0; } + +sgr_N_0t: SGR^","^N_0 is N_0 & SGR { export N_0; } + +dbr_N_0t: DBR^","^N_0 is N_0 & DBR { export N_0; } + +sr_t: SR is OP_0 & SR { x:4 = 0; export x; } # dummy export, just looking for the display + +gbr_t: GBR is OP_0 & GBR { x:4 = 0; export x; } # dummy export, just looking for the display + +vbr_t: VBR is OP_0 & VBR { x:4 = 0; export x; } # dummy export, just looking for the display + +ssr_t: SSR is OP_0 & SSR { x:4 = 0; export x; } # dummy export, just looking for the display + +spc_t: SPC is OP_0 & SPC { x:4 = 0; export x; } # dummy export, just looking for the display + +sgr_t: SGR is OP_0 & SGR { x:4 = 0; export x; } # dummy export, just looking for the display + +dbr_t: DBR is OP_0 & DBR { x:4 = 0; export x; } # dummy export, just looking for the display + +N_0t_sr: N_0^","^SR is N_0 & SR { export N_0; } + +N_0t_gbr: N_0^","^GBR is N_0 & GBR { export N_0; } + +N_0t_vbr: N_0^","^VBR is N_0 & VBR { export N_0; } + +N_0t_ssr: N_0^","^SSR is N_0 & SSR { export N_0; } + +N_0t_spc: N_0^","^SPC is N_0 & SPC { export N_0; } + +# N_0t_sgr: N_0^","^SGR is N_0 & SGR { export N_0; } +N_0t_dbr: N_0^","^DBR is N_0 & DBR { export N_0; } + +N_0t_bank: N_0 is N_0 { export N_0; } + +N_0t_sr1: @^N_0^"+,"^SR is N_0 & SR { export N_0; } + +N_0t_gbr1: @^N_0^"+,"^GBR is N_0 & GBR { export N_0; } + +N_0t_vbr1: @^N_0^"+,"^VBR is N_0 & VBR { export N_0; } + +N_0t_ssr1: @^N_0^"+,"^SSR is N_0 & SSR { export N_0; } + +N_0t_spc1: @^N_0^"+,"^SPC is N_0 & SPC { export N_0; } + +# N_0t_sgr1: @^N_0^"+,"^SGR is N_0 & SGR { export N_0;} +N_0t_dbr1: @^N_0^"+,"^DBR is N_0 & DBR { export N_0; } + +N_0t_bank1: @^N_0^"+" is N_0 { export N_0; } + +FR0_t: fr0 is OP_0 & fr0 { export fr0; } + +XMTRX_t: "xmtrx" is OP_0 { x:4 = 0; export x; } # dummy export, just looking for the display + +mach_t: MACH is OP_0 & MACH { export MACH; } + +macl_t: MACL is OP_0 & MACL { export MACL; } + +fpul_t: FPUL is OP_0 & FPUL { export FPUL; } + +fpscr_t: "FPSCR" is OP_0 { x:4 = 0; export x; } # dummy export, just looking for the display + +mach_N_0t: MACH^","^N_0 is N_0 & MACH { export N_0; } + +macl_N_0t: MACL^","^N_0 is N_0 & MACL { export N_0; } + +pr_N_0t: PR^","^N_0 is N_0 & PR { export N_0; } + +fpul_N_0t: FPUL^","N_0 is N_0 & FPUL { export N_0; } + +fpscr_N_0t: "FPSCR"^","N_0 is N_0 { export N_0; } + +N_0t_mach: N_0^","^MACH is N_0 & MACH { export N_0; } + +N_0t_macl: N_0^","^MACL is N_0 & MACL { export N_0; } + +N_0t_pr: N_0^","^PR is N_0 & PR { export N_0; } + +N_0t_fpul: N_0^","^FPUL is N_0 & FPUL { export N_0; } + +N_0t_fpscr: N_0^",fpscr" is N_0 { export N_0; } + +N_0t_mach1: @^N_0^"+,"^MACH is N_0 & MACH { export N_0; } + +N_0t_macl1: @^N_0^"+,"^MACL is N_0 & MACL { export N_0; } + +N_0t_pr1: @^N_0^"+,"^PR is N_0 & PR { export N_0; } + +N_0t_fpul1: @^N_0^"+,"^FPUL is N_0 & FPUL { export N_0; } + +N_0t_fpscr1: @^N_0^"+,fpscr" is N_0 { export N_0; } + +M_0t_at1: @^M_0 is M_0 { export M_0; } + +N_0t_at1: @^N_0 is N_0 { export N_0; } + +M_0t_at: @^M_0^+ is M_0 { export M_0; } + +N_0t_at: @^N_0^+ is N_0 { export N_0; } + +FRM_0t: FRM_0 is FRM_0 { export FRM_0; } + +FRN_0t: FRN_0 is FRN_0 { export FRN_0; } + +DRM_1t: DRM_1 is DRM_1 { export DRM_1; } + +DRN_1t: DRN_1 is DRN_1 { export DRN_1; } + +FVM_2t: FVM_2 is FVM_2 { export FVM_2; } + +FVN_2t: FVN_2 is FVN_2 { export FVN_2; } + +N_0t_at_with_r0: "@("^r0^","^N_0^")" is N_0 & r0 { export N_0; } + +M_0t_at_with_r0: "@("^r0^","^M_0^")" is M_0 & r0 { export M_0; } + +N_0t_at_neg: "@-"^N_0 is N_0 { export N_0; } + +U_2t_M0_dispr01: "@("^disp^","^M_0^")" is U_2 & M_0 [ disp = U_2 * 1; ] { tmp4:4 = disp; export tmp4; } +U_2t_M0_dispr02: "@("^disp^","^M_0^")" is U_2 & M_0 [ disp = U_2 * 2; ] { tmp4:4 = disp; export tmp4; } +U_2t_M0_dispr04: "@("^disp^","^M_0^")" is U_2 & M_0 [ disp = U_2 * 4; ] { tmp4:4 = disp; export tmp4; } + +U_2t_N0_dispr04: "@("^disp^","^N_0^")" is U_2 & N_0 [ disp = U_2 * 4; ] { tmp4:4 = disp; export tmp4; } + +# Bug in SLEIGH, needed "* 1" +U_0t_gbr_at_1: "@("^disp,GBR^")" is U_0 & GBR [ disp = U_0 * 1; ] { tmp4:4 = disp + GBR; export tmp4; } +U_0t_gbr_at_2: "@("^disp,GBR^")" is U_0 & GBR [ disp = U_0 * 2; ] { tmp4:4 = disp + GBR; export tmp4; } +U_0t_gbr_at_4: "@("^disp,GBR^")" is U_0 & GBR [ disp = U_0 * 4; ] { tmp4:4 = disp + GBR; export tmp4; } + +# Note: The 4 byte (MOVA) case needs the masking of the PC bottom 2 bits, page 345, paragraph 1: +# "a value with the lower 2 bits adjusted to B00 is used in address calculation." +# Note: Only the 4 byte case needs the masking of the PC bottom 2 bits, page 336, paragraph 3: +# "A value with the lower 2 bits adjusted to B00 is used in address calculation." +# (The 2 byte case always has the PC LSBit at 0 because all instructions are 2 byte aligned.) +U_0t_2pc: dest is U_0 [ dest = inst_start + U_0*2 + 4; ] { export *:2 dest; } + +U_0t_4pc: dest is U_0 [ dest = ( inst_start & 0xfffffffc ) + U_0*4 + 4; ] { export *:4 dest; } + +BANKt: BANK is BANK { export BANK; } + +N_0txx: r0",@"^N_0 is r0 & N_0 { tmp:4 = N_0; export tmp; } + +# Constructors ======================================================================= +# Binary Addition +# pattern 0011nnnnmmmm1100 +# text add , +# arch arch_sh_up +:add M_0t,N_0t is OP_0=0x3 & N_0t & M_0t & OP_1=0xc { + + N_0t = N_0t + M_0t; +} + + +# Binary Addition +# pattern 0111nnnniiiiiiii +# text add #, +# arch arch_sh_up +:add I_0t,N_0t is OP_0=0x7 & N_0t & I_0t { + + N_0t = I_0t + N_0t; # NOTE I_0t already signed extended +} + + +# Binary Addition with Carry +# pattern 0011nnnnmmmm1110 +# text addc , +# arch arch_sh_up +:addc M_0t,N_0t is OP_0=0x3 & N_0t & M_0t & OP_1=0xe { + local Tcopy:4 = zext($(T_FLAG)); + $(T_FLAG) = carry( N_0t, M_0t ); + local result:4 = N_0t + M_0t; + $(T_FLAG) = $(T_FLAG) || carry( result, Tcopy ); + N_0t = result + Tcopy; +} + + +# Binary Addition with Overflow Check +# pattern 0011nnnnmmmm1111 +# text addv , +# arch arch_sh_up +:addv M_0t,N_0t is OP_0=0x3 & N_0t & M_0t & OP_1=0xf { + + $(T_FLAG) = scarry(N_0t,M_0t); + N_0t = N_0t + M_0t; +} + + +# Logical AND +# pattern 0010nnnnmmmm1001 +# text and , +# arch arch_sh_up +:and M_0t,N_0t is OP_0=0x2 & N_0t & M_0t & OP_1=0x9 { + + N_0t = N_0t & M_0t; +} + +# Logical AND +# pattern 11001001iiiiiiii +# text and #,R0 +# arch arch_sh_up +:and U_0t_r0 is OP_2=0xc9 & U_0t_r0 { + + r0 = r0 & U_0t_r0; +} + +# Logical AND +# pattern 11001101iiiiiiii +# text and.b #,@(R0,GBR) +# arch arch_sh_up +:and.b U_0t1 is OP_2=0xcd & U_0t1 { + + *:1 (GBR + r0) = (*:1 (GBR + r0)) & U_0t1; +} + + +# Conditional Branch +# pattern 10001011iiiiiiii +# text bf +# arch arch_sh_up +:bf I_0tbranch is OP_2=0x8b & I_0tbranch { + + if ( $(T_FLAG) == 0 ) goto I_0tbranch; +} + + +# Conditional Branch with Delay +# pattern 10001111iiiiiiii +# text bf/s +# arch arch_sh2_up +:bf^"/s" I_0tbranch is OP_2=0x8f & I_0tbranch { + + local cond = $(T_FLAG); + delayslot(1); + if ( cond == 0 ) goto I_0tbranch; +} + + +# Unconditional Branch +# pattern 1010iiiiiiiiiiii +# text bra +# arch arch_sh_up +:bra I_1tbranch is OP_0=0xa & I_1tbranch { + + delayslot(1); + goto I_1tbranch; +} + + +# Unconditional Branch +# pattern 0000nnnn00100011 +# text braf +# arch arch_sh2_up +:braf N_0 is OP_0=0x0 & N_0 & OP_4=0x23 { + + local dest = N_0 + inst_next; + delayslot(1); + goto [dest]; +} + + +# Branch to Subroutine Procedure +# pattern 1011iiiiiiiiiiii +# text bsr +# arch arch_sh_up +:bsr I_1tbranch is OP_0=0xb & I_1tbranch { + + delayslot(1); + call I_1tbranch; +} + + +# Branch to Subroutine Procedure +# pattern 0000nnnn00000011 +# text bsrf +# arch arch_sh2_up +:bsrf N_0 is OP_0=0x0 & N_0 & OP_4=0x3 { + + PR = inst_next; + local dest = N_0 + inst_next; + delayslot(1); + call [dest]; +} + + +# Conditional Branch +# pattern 10001001iiiiiiii +# text bt +# arch arch_sh_up +:bt I_0tbranch is OP_2=0x89 & I_0tbranch { + + if ( $(T_FLAG) == 1 ) goto I_0tbranch; +} + + +# Conditional Branch with Delay +# pattern 10001101iiiiiiii +# text bt/s +# arch arch_sh2_up +:bt^"/s" I_0tbranch is OP_2=0x8d & I_0tbranch { + local cond = $(T_FLAG); + delayslot(1); + if ( cond == 1 ) goto I_0tbranch; +} + + +# MAC Register Clear +# pattern 0000000000101000 +# text clrmac +# arch arch_sh_up +:clrmac is OP_3=0x28 { + + MACH = 0; + MACL = 0; +} + + +# S Bit Clear +# pattern 0000000001001000 +# text clrs +# arch arch_sh_up +:clrs is OP_3=0x48 { + + $(S_FLAG) = 0; +} + + +# T Bit Clear +# pattern 0000000000001000 +# text clrt +# arch arch_sh_up +:clrt is OP_3=0x8 { + + $(T_FLAG) = 0; +} + + +# Compare +# pattern 0011nnnnmmmm0000 +# text cmp/eq , +# arch arch_sh_up +:cmp^"/eq" M_0t,N_0t is OP_0=0x3 & N_0t & M_0t & OP_1=0x0 { + + $(T_FLAG) = ( N_0t == M_0t ); +} + + +# Compare +# pattern 0011nnnnmmmm0011 +# text cmp/ge , +# arch arch_sh_up +:cmp^"/ge" M_0t,N_0t is OP_0=0x3 & N_0t & M_0t & OP_1=0x3 { + + $(T_FLAG) = ( N_0t s>= M_0t ); +} + +# Compare +# pattern 0011nnnnmmmm0111 +# text cmp/gt , +# arch arch_sh_up +:cmp^"/gt" M_0t,N_0t is OP_0=0x3 & N_0t & M_0t & OP_1=0x7 { + + $(T_FLAG) = ( N_0t s> M_0t); +} + + +# Compare +# pattern 0011nnnnmmmm0110 +# text cmp/hi , +# arch arch_sh_up +:cmp^"/hi" M_0t,N_0t is OP_0=0x3 & N_0t & M_0t & OP_1=0x6 { + + $(T_FLAG) = ( N_0t > M_0t ); +} + + +# Compare +# pattern 0011nnnnmmmm0010 +# text cmp/hs , +# arch arch_sh_up +:cmp^"/hs" M_0t,N_0t is OP_0=0x3 & N_0t & M_0t & OP_1=0x2 { + + $(T_FLAG) = ( N_0t >= M_0t ); +} + + +# Compare +# pattern 0100nnnn00010101 +# text cmp/pl +# arch arch_sh_up +:cmp^"/pl" N_0t is OP_0=0x4 & N_0t & OP_4=0x15 { + + $(T_FLAG) = ( N_0t s> 0 ); +} + +# Compare +# pattern 0100nnnn00010001 +# text cmp/pz +# arch arch_sh_up +:cmp^"/pz" N_0t is OP_0=0x4 & N_0t & OP_4=0x11 { + + $(T_FLAG) = ( N_0t s>= 0 ); +} + + +# Compare +# pattern 0010nnnnmmmm1100 +# text cmp/str , +# arch arch_sh_up +:cmp^"/str" M_0t,N_0t is OP_0=0x2 & N_0t & M_0t & OP_1=0xc { + + temp:4 = M_0t ^ N_0t; + HH:4 = (temp & 0xFF000000) >> 24; + HL:4 = (temp & 0x00FF0000) >> 16; + LH:4 = (temp & 0x0000FF00) >> 8; + LL:4 = temp & 0x000000FF; + $(T_FLAG) = (HH == 0) || (HL == 0 ) || (LH == 0) || (LL == 0); +} + + +# Compare +# pattern 10001111iiiiiiii +# pattern 10001000iiiiiiii +# text cmp/eq #,R0 +# arch arch_sh_up +:cmp^"/eq" I_0t_r0 is OP_2=0x88 & I_0t_r0 { + + $(T_FLAG) = ( r0 == I_0t_r0 ); +} + + +# Initialization for Signed Division +# pattern 0010nnnnmmmm0111 +# text div0s , +# arch arch_sh_up +:div0s M_0t,N_0t is OP_0=0x2 & N_0t & M_0t & OP_1=0x7 { + + $(Q_FLAG) = ( (N_0t & 0x80000000) != 0 ); + $(M_FLAG) = ( (M_0t & 0x80000000) != 0 ); + $(T_FLAG) = ( $(M_FLAG) != $(Q_FLAG) ); +} + + +# Initialization for Unsigned Division +# pattern 0000000000011001 +# text div0u +# arch arch_sh_up +:div0u is OP_3=0x19 { + + $(M_FLAG) = 0; + $(Q_FLAG) = 0; + $(T_FLAG) = 0; +} + + +# Division +# pattern 0011nnnnmmmm0100 +# text div1 , +# arch arch_sh_up +:div1 M_0t,N_0t is OP_0=0x3 & OP_1=0x4 & M_0t & N_0t { + +#@ifdef DIV1_ORIGINAL_IS_BROKEN +# tmp2:4 = M_0t; +# N_0t = N_0t << 1; +# N_0t = N_0t | zext($(T_FLAG)); # ??? +# tmp0:4 = N_0t; +# N_0t = N_0t - zext((($(Q_FLAG)+$(M_FLAG))!=1))*tmp2 + zext(($(Q_FLAG)+$(M_FLAG))==1)*tmp2; +# tmp1:1 = ( (($(Q_FLAG)+$(M_FLAG))!=1)*(N_0t > tmp0) + (($(Q_FLAG)+$(M_FLAG))==1)*(N_0t < tmp0)); +# $(Q_FLAG) = ((0x80000000 & N_0t)!=0); +# Q1:1 = tmp1*($(Q_FLAG)!=0) + (tmp1==0)*($(Q_FLAG)==0); +# Q2:1 = tmp1*($(Q_FLAG)==0) + (tmp1==0)*($(Q_FLAG)!=0); +# $(Q_FLAG) = (($(M_FLAG)==1)*Q1 + ($(M_FLAG)!=1)*Q2); +# $(T_FLAG) = ($(Q_FLAG)==$(M_FLAG)); +#@endif # DIV1_ORIGINAL_IS_BROKEN +# DIV1_WITH_FORWARD_BRANCHES_WORKS_OK + local Rm:4 = M_0t; + local Rn:4 = N_0t; + local old_Q:1 = $(Q_FLAG); + $(Q_FLAG) = ((0x80000000 & Rn)!=0); + local tmp2:4 = Rm; + Rn = Rn << 1; + Rn = Rn | zext($(T_FLAG)); + local tmp0:4 = Rn; + local tmp1:1 = 0; + + if (old_Q == 0) && ($(M_FLAG) == 0) goto ; + if (old_Q == 0) && ($(M_FLAG) == 1) goto ; + if (old_Q == 1) && ($(M_FLAG) == 0) goto ; +# if (old_Q == 1) && ($(M_FLAG) == 1) ... + Rn = Rn - tmp2; + tmp1 = Rn > tmp0; + if ($(Q_FLAG) == 0) goto ; +# ($(Q_FLAG) == 1) + $(Q_FLAG) = tmp1; + goto ; + + $(Q_FLAG) = tmp1 == 0; + goto ; + + # (old_Q == 1) && ($(M_FLAG) == 0) + Rn = Rn + tmp2; + tmp1 = Rn < tmp0; + if ($(Q_FLAG) == 0) goto ; +# ($(Q_FLAG) == 1) + $(Q_FLAG) = tmp1 == 0; + goto ; + + $(Q_FLAG) = tmp1; + goto ; + + # (old_Q == 0) && ($(M_FLAG) == 1) + Rn = Rn + tmp2; + tmp1 = Rn < tmp0; + if ($(Q_FLAG) == 0) goto ; +# ($(Q_FLAG) == 1) + $(Q_FLAG) = tmp1; + goto ; + + $(Q_FLAG) = tmp1 == 0; + goto ; + + # (old_Q == 0) && ($(M_FLAG) == 0) + Rn = Rn - tmp2; + tmp1 = Rn > tmp0; + if ($(Q_FLAG) == 0) goto ; +# ($(Q_FLAG) == 1) + $(Q_FLAG) = tmp1 == 0; + goto ; + + $(Q_FLAG) = tmp1; + + + $(T_FLAG) = $(Q_FLAG) == $(M_FLAG); + N_0t = Rn; + +# DIV1_WITH_GOTOs_WORKS_OK + +# TODO: the following is currently broken, it should be fixed to eliminate gotos in the code above + +#@ifdef DIV1_STRAIGHT_CODE # BROKEN +# Rm:4 = M_0t; +# Rn:4 = N_0t; +# old_Q:1 = $(Q_FLAG); +# $(Q_FLAG) = ((0x80000000 & Rn)!=0); +# tmp2:4 = Rm; +# Rn = Rn << 1; +# Rn = Rn | zext($(T_FLAG)); +# tmp0:4 = Rn; +# +# oldQM_10_01_bool:1 = ( ( (old_Q == 1) && ($(M_FLAG) == 0) ) || ( (old_Q == 1) && ($(M_FLAG) == 0) ) ); +# oldQM_10_01:4 = zext(oldQM_10_01_bool) * 0xffffffff; +# +# oldQM_11_00_bool:1 = ( (old_Q == 1) && ($(M_FLAG) == 1) ) || ( (old_Q == 0) && ($(M_FLAG) == 0) ); +# oldQM_11_00:4 = zext(oldQM_11_00_bool) * 0xffffffff; + +# Rn = (oldQM_10_01 & (Rn + tmp2)) | (oldQM_11_00 & (Rn - tmp2)); + +# tmp1:1 = ( (oldQM_11_00 != 0) && (Rn > tmp0) ) | ( (oldQM_10_01 != 0) && (Rn < tmp0) ); + +# QM_10_01:1 = ( ( ($(Q_FLAG) == 1) && ($(M_FLAG) == 0) ) || ( ($(Q_FLAG) == 1) && ($(M_FLAG) == 0) ) ) * 0xff; +# QM_11_00:1 = ( ( ($(Q_FLAG) == 1) && ($(M_FLAG) == 1) ) || ( ($(Q_FLAG) == 0) && ($(M_FLAG) == 0) ) ) * 0xff; + +# $(Q_FLAG) = (QM_10_01 & tmp1) || (QM_11_00 & (tmp1 == 0)); + +# $(T_FLAG) = $(Q_FLAG) == $(M_FLAG); +# N_0t = Rn; +#@endif # DIV1_STRAIGHT_CODE +} + +# Signed Double-Length Multiplication +# pattern 0011nnnnmmmm1101 +# text dmuls.l , +# arch arch_sh2_up +:dmuls.l M_0t,N_0t is OP_0=0x3 & OP_1=0xd & M_0t & N_0t +{ + local temp:8 = sext(M_0t) * sext(N_0t); + MACL = temp[0,32]; + MACH = temp[32,32]; +} + +# Unsigned Double-Length Multiplication +# pattern 0011nnnnmmmm0101 +# text dmulu.l , +# arch arch_sh2_up +:dmulu.l M_0t,N_0t is OP_0=0x3 & OP_1=0x5 & M_0t & N_0t { + local temp:8 = zext(M_0t) * zext(N_0t); + MACL = temp[0,32]; + MACH = temp[32,32]; +} + +# Decrement and Test +# pattern 0100nnnn00010000 +# text dt +# arch arch_sh2_up +:dt N_0t is OP_0=0x4 & N_0t & OP_4=0x10 { + + N_0t = N_0t - 1; + $(T_FLAG) = ( N_0t == 0 ); +} + + +# Sign Extension +# pattern 0110nnnnmmmm1110 +# text exts.b , +# arch arch_sh_up +:exts.b M_0t,N_0t is OP_0=0x6 & N_0t & M_0t & OP_1=0xe { + + N_0t = sext(M_0t:1); +} + +# Sign Extension +# pattern 0110nnnnmmmm1111 +# text exts.w , +# arch arch_sh_up +:exts.w M_0t,N_0t is OP_0=0x6 & N_0t & M_0t & OP_1=0xf { + + N_0t = sext(M_0t:2); +} + + +# Zero Extension +# pattern 0110nnnnmmmm1100 +# text extu.b , +# arch arch_sh_up +:extu.b M_0t,N_0t is OP_0=0x6 & N_0t & M_0t & OP_1=0xc { + + N_0t = zext(M_0t:1); +} + + +# Zero Extension +# pattern 0110nnnnmmmm1101 +# text extu.w , +# arch arch_sh_up +:extu.w M_0t,N_0t is OP_0=0x6 & N_0t & M_0t & OP_1=0xd { + + N_0t = zext(M_0t:2); +} + + +# Floating-Point Absolute Value +# pattern 1111nnnn01011101 +# text fabs +# arch arch_sh2e_up +:fabs FRN_0 is + OP_0=0xf & FRN_0 & DRN_1 & OP_4=0x5d { + + if (!( $(FPSCR_PR) == 0 )) goto ; + FRN_0 = abs(FRN_0); + goto ; + + DRN_1 = abs(DRN_1); + +} + +# Floating-Point Addition +# pattern 1111nnnnmmmm0000 +# text fadd , +# arch arch_sh2a_or_sh4_up +:fadd FRM_0,FRN_0 is + OP_0=0xf & FRN_0 & DRN_1 & FRM_0 & DRM_1 & OP_1=0x0 { + + if (!( $(FPSCR_PR) == 0 )) goto ; + FRN_0 = FRN_0 f+ FRM_0; + goto ; + + DRN_1 = DRN_1 f+ DRM_1; + +} + +# Floating-Point Comparison +# pattern 1111nnnnmmmm0100 +# text fcmp/eq , +# arch arch_sh2e_up +:fcmp^"/eq" FRM_0t,FRN_0t is + OP_0=0xf & FRN_0t & DRN_1t & FRM_0t & DRM_1t & OP_6 & OP_10 & OP_1=0x4 { + if (!( $(FPSCR_PR) == 0 ) ) && (OP_6:1 == 0) && (OP_10:1 == 0) goto ; + $(T_FLAG) = ( FRN_0t f== FRM_0t ); + goto ; + + $(T_FLAG) = ( DRN_1t f== DRM_1t ); + +} + +# Floating-Point Comparison +# pattern 1111nnnnmmmm0101 +# text fcmp/gt , +# arch arch_sh2e_up +:fcmp^"/gt" FRM_0t,FRN_0t is + OP_0=0xf & FRM_0t & DRM_1t & FRN_0t & DRN_1t & OP_1=0x5 { + + if (!( $(FPSCR_PR) == 0 )) goto ; + $(T_FLAG) = ( FRN_0t f> FRM_0t ); + goto ; + + $(T_FLAG) = ( DRN_1t f> DRM_1t ); + +} + + +# Double-Precision to Single-Precision Conversion +# pattern 1111nnn010111101 +# text fcnvds ,FPUL +# even though reserved to DblPrec, should decode, may not know at the time. +# if this instruction shows up, it is most likely in DblPrec mode but not set +# arch arch_sh2a_or_sh4_up +:fcnvds DRN_1t,FPUL is OP_0=0xf & DRN_1t & OP_5=0x0bd & FPUL { + + # note: this instruction is undefined if not running in DblPrec mode. + FPUL = float2float( DRN_1t ); +} + + +# Single-Precision to Double-Precision Conversion +# pattern 1111nnn010101101 +# text fcnvsd FPUL, +# even though reserved to DblPrec, should decode, may not know at the time. +# if this instruction shows up, it is most likely in DblPrec mode but not set +# arch arch_sh2a_or_sh4_up +:fcnvsd FPUL,DRN_1t is OP_0=0xf & DRN_1t & OP_5=0xad & FPUL { + + # note: this instruction is undefined if not running in DblPrec mode. + DRN_1t = float2float( FPUL ); +} + + +# Floating-Point Division +# pattern 1111nnnnmmmm0011 +# text fdiv , +# arch arch_sh2e_up +:fdiv FRM_0t,FRN_0t is + OP_0=0xf & FRN_0t & DRN_1t & FRM_0t & DRM_1t & OP_1=0x3 { + + if (!( $(FPSCR_PR) == 0 )) goto ; + FRN_0t = ( FRN_0t f/ FRM_0t ); + goto ; + + DRN_1t = ( DRN_1t f/ DRM_1t ); + +} + +# Floating-Point Inner Product +# pattern 1111nnmm11101101 +# text fipr , +# even though reserved to DblPrec, should decode, may not know at the time. +# if this instruction shows up, it is most likely in DblPrec mode but not set +# arch arch_sh4_up +:fipr FVM_2t,FVN_2t is OP_0=0xf & FVN_2t & FVM_2t & OP_4=0xed { + + # note: this instruction is undefined if not running in SinglePrec mode. + if (!( $(FPSCR_PR) == 0 )) goto ; + # FVn dot FVm + temp1:4 = ( *[register]:4 (&:4 FVN_2t + 0) f* *[register]:4 (&:4 FVM_2t + 0) ); + temp1 = temp1 f+ ( *[register]:4 (&:4 FVN_2t + 4) f* *[register]:4 (&:4 FVM_2t + 4) ); + temp1 = temp1 f+ ( *[register]:4 (&:4 FVN_2t + 8) f* *[register]:4 (&:4 FVM_2t + 8) ); + temp1 = temp1 f+ ( *[register]:4 (&:4 FVN_2t + 12) f* *[register]:4 (&:4 FVM_2t + 12) ); + + # summation goes to FR[n + 3] + *[register]:4 (&:4 FVN_2t + 12) = temp1; + +} + +# 0.0 Load +# pattern 1111nnnn10001101 +# text fldi0 +# arch arch_sh2e_up +# +# Note- The manual says this applies only to single float destination regs +# +:fldi0 FRN_0t is OP_0=0xf & DRN_1t & FRN_0t & OP_4=0x8d { + tmp1:4 = 0; + FRN_0t = int2float(tmp1); +} + +# 1.0 Load +# pattern 1111nnnn10011101 +# text fldi1 +# arch arch_sh2e_up +# +# Note- the manual says FPSCR_PR applies only to single float regs, not to doubles. +# Manual also says FPSCR_PR should be 0, but gcc generates code where it's set to 1. +# +:fldi1 FRN_0t is OP_0=0xf & FRN_0t & DRN_1t & OP_4=0x9d { + tmp1:4 = 1; + FRN_0t = int2float(tmp1); +} + +# Transfer to System Register +# pattern 1111nnnn00011101 +# text flds ,FPUL +# arch # arch_sh2e_up +# Note: Field usage indicates FR[n], not FR[m]. +:flds FRN_0t,FPUL is OP_0=0xf & FRN_0t & OP_4=0x1d & FPUL { + + FPUL = FRN_0t; +} + +# Integer to Floating-Point Conversion +# pattern 1111nnnn00101101 +# text float FPUL, +# arch # arch_sh2e_up +:float FPUL,FRN_0t is + OP_0=0xf & OP_6 & FRN_0t & DRN_1t & OP_4=0x2d & FPUL { + # If bit 6 is set this this is an odd FP register number, so need to do single float operation. + # This is not in the manual but this seems to be the correct behavior. + if (!( $(FPSCR_PR) == 0 ) ) && (OP_6:1 == 0x0) goto ; + FRN_0t = int2float( FPUL ); + goto ; + + DRN_1t = int2float( FPUL ); + +} + +# Floating-Point Multiply and Accumulate +# pattern 1111nnnnmmmm1110 +# text fmac FR0,, +# arch arch_sh2e_up +:fmac FR0_t,FRM_0t,FRN_0t is OP_0=0xf & FRN_0t & FRM_0t & OP_1=0xe & FR0_t { + + if (!( $(FPSCR_PR) == 0 )) goto ; + FRN_0t = ( FR0_t f* FRM_0t ) f+ FRN_0t; + +} + +# Floating-Point Transfer #1-4 +# pattern 1111nnnnmmmm1100 +# text fmov , +# arch arch_sh2e_up +# +# Note- The manual says all the fmov insns should only look at the FPSCR_SZ flag +# to determine if this is a single or double float move. Ie, don't reference FPSCR_PR. +# +:fmov FRM_0,FRN_0 is + OP_0=0xf & FRN_0 & XDRN & FRM_0 & XDRM & OP_1=0xc { + if (!( $(FPSCR_SZ) == 0 )) goto ; + FRN_0 = FRM_0; + goto ; + + XDRN = XDRM; + +} + +# Floating-Point Transfer #5-6 +# pattern 1111nnn0mmmm1000 +# text fmov @, +# arch arch_sh2e_up +:fmov.s M_0t_at1,FRN_0 is + OP_0=0xf & XDRN & FRN_0 & M_0t_at1 & OP_1=0x8 { + + if (!( $(FPSCR_SZ) == 0 )) goto ; + FRN_0 = *:4 M_0t_at1; + goto ; + + XDRN = *:8 M_0t_at1; + +} + +# Floating-Point Transfer #7-8 +# pattern 1111nnnnmmmm1010 +# text fmov ,@ +# arch arch_sh2e_up +# +# Note- Manual says to ignore FPSCR_PR but FPSCR_SZ must = 0 +# +:fmov.s FRM_0,N_0t_at1 is + + OP_0=0xf & N_0t_at1 & FRM_0 & XDRM & OP_1=0xa { + if (!( $(FPSCR_SZ) == 0 )) goto ; + *:4 N_0t_at1 = FRM_0; + goto ; + + *:8 N_0t_at1 = XDRM; + +} + +# Floating-Point Transfer #9-10 +# pattern 1111nnnnmmmm1001 +# text fmov @+, +# arch arch_sh2e_up +:fmov.s M_0t_at,FRN_0 is + OP_0=0xf & XDRN & FRN_0 & M_0t_at & OP_1=0x9 { + + if (!( $(FPSCR_SZ) == 0 )) goto ; + FRN_0 = *:4 M_0t_at; + M_0t_at = M_0t_at + 4; + goto ; + + XDRN = *:8 M_0t_at; + M_0t_at = M_0t_at + 8; + +} + +# Floating-Point Transfer #11-12 +# pattern 1111nnnnmmm01011 +# text fmov ,@- +# arch arch_sh2e_up +:fmov.s FRM_0,N_0t_at_neg is + OP_0=0xf & N_0t_at_neg & XDRM & FRM_0 & OP_1=0xb { + + if (!( $(FPSCR_SZ) == 0 )) goto ; + N_0t_at_neg = N_0t_at_neg - 4; + *:4 N_0t_at_neg = FRM_0; + goto ; + + N_0t_at_neg = N_0t_at_neg - 8; + *:8 N_0t_at_neg = XDRM; + +} + +# Floating-Point Transfer #13-14 +# pattern 1111nnnnmmmm0110 +# text fmov @(R0,), +# arch arch_sh2e_up +:fmov.s M_0t_at_with_r0,FRN_0 is + OP_0=0xf & XDRN & FRN_0 & M_0t_at_with_r0 & OP_1=0x6 { + + if (!( $(FPSCR_SZ) == 0 )) goto ; + FRN_0 = *:4 (r0 + M_0t_at_with_r0); + goto ; + + XDRN = *:8 (r0 + M_0t_at_with_r0); + +} + +# Floating-Point Transfer #15-16 +# pattern 1111nnnnmmmm0111 +# text fmov @(R0,), +# arch arch_sh2e_up +:fmov FRM_0,N_0t_at_with_r0 is + OP_0=0xf & N_0t_at_with_r0 & XDRM & FRM_0 & OP_1=0x7 { + + if (!( $(FPSCR_SZ) == 0 )) goto ; + *:4 (r0 + N_0t_at_with_r0) = FRM_0; + goto ; + + *:8 (r0 + N_0t_at_with_r0) = XDRM; + +} + +# Floating-Point Multiplication +# pattern 1111nnnnmmmm0010 +# text fmul , +# arch arch_sh2e_up +:fmul FRM_0t,FRN_0t is + OP_0=0xf & FRN_0t & DRN_1t & FRM_0t & DRM_1t & OP_1=0x2 { + + if (!( $(FPSCR_PR) == 0 )) goto ; + FRN_0t = FRN_0t f* FRM_0t; + goto ; + + DRN_1t = DRN_1t f* DRM_1t; + +} + +# Floating-Point Sign Inversion +# pattern 1111nnnn01001101 +# text fneg +# arch arch_sh2e_up +:fneg FRN_0t is + OP_0=0xf & FRN_0t & DRN_1t & OP_6 & OP_4=0x4d { + + if (!( $(FPSCR_PR) == 0 )) && (OP_6:1 == 0) goto ; + FRN_0t = f- FRN_0t; + goto ; + + DRN_1t = f- DRN_1t; + +} + +# FR Bit Inversion +# pattern 1111101111111101 +# text frchg +# arch # arch_sh4_up +:frchg is + OP_3=0xfbfd { + + if (!( $(FPSCR_PR) == 0 )) goto ; + $(FPSCR_FR) = !$(FPSCR_FR); + FPSCR = FPSCR ^ 0x00200000; + +} + + +# SZ Bit Inversion +# pattern 1111001111111101 +# text fschg +# arch arch_sh2a_or_sh4a_up (not in sh4) +:fschg is + OP_3=0xf3fd { + + if (!( $(FPSCR_PR) == 0 )) goto ; + FPSCR = FPSCR ^ 0x00100000; + +} + +# PR Bit Inversion +# pattern 1111011111111101 +# text fpchg +# arch arch_sh2a_or_sh4_up +:fpchg is + OP_3=0xf7fd { + FPSCR = FPSCR ^ 0x00080000; +} + +# Floating-Point Square Root +# pattern 1111nnnn01101101 +# text fsqrt +# arch # arch_sh2a_or_sh3e_up +:fsqrt FRN_0t is + OP_0=0xf & FRN_0t & DRN_1t & OP_4=0x6d { + + if (!( $(FPSCR_PR) == 0 )) goto ; + FRN_0t = sqrt( FRN_0t ); + goto ; + + DRN_1t = sqrt( DRN_1t ); + +} + +# Floating Point Square Reciprocal Approximate +# pattern 1111nnnn01111101 +# text fsrra +# arch # arch_sh2a_or_sh3e_up +:fsrra FRN_0 is + OP_0=0xF & FRN_0 & OP_4=0x7D { + if (( $(FPSCR_PR) != 0 )) goto inst_next; + FRN_0 = int2float(1 :4) f/ sqrt( FRN_0 ); +} + +define pcodeop sin; +define pcodeop cos; + +# Floating Point Sine And Cosine Approximate +# pattern 1111nnn011111101 +# text fsca FPUL, +# arch # arch_sh2a_or_sh3e_up +:fsca FPUL,DRN_0 is + OP_0=0xF & FPUL & DRN_0 & FRN_1 & FRN_2 & OP_4=0xFD { + if (( $(FPSCR_PR) != 0 )) goto inst_next; + + angle:4 = int2float(0 :4); # float + fraction:4 = 0x0000FFFF; # long + + fraction = fraction & FPUL; # extract sub-rotation + angle = int2float(fraction); # convert to float + + two_pi:4 = 0x40c90fdb; # 6.2831855.. as 32-bit float + angle = (two_pi f* angle) f/ int2float(65536 :4); # convert to radian + + local _sin:4 = sin(angle); # call fake sin & cos + local _cos:4 = cos(angle); + + FRN_1 = float2float(_sin); # _sin goes to FR[n] + FRN_2 = float2float(_cos); # _cos goes to FR[n+1] +} + +# Transfer from System Register +# pattern 1111nnnn00001101 +# text fsts FPUL, +# arch arch_sh2e_up +:fsts FPUL,FRN_0t is OP_0=0xf & FRN_0t & OP_4=0xd & FPUL { + + FRN_0t = FPUL; +} + +# Floating-Point Subtraction +# pattern 1111nnnnmmmm0001 +# text fsub , +# arch arch_sh2e_up +:fsub FRM_0t,FRN_0t is + OP_0=0xf & FRN_0t & DRN_1t & FRM_0t & DRM_1t & OP_1=0x1 { + + if (!( $(FPSCR_PR) == 0 )) goto ; + FRN_0t = FRN_0t f- FRM_0t; + goto ; + + DRN_1t = DRN_1t f- DRM_1t; + +} + +# Conversion to Integer +# pattern 1111nnnn00111101 +# text ftrc ,FPUL +# # arch arch_sh2e_up +# Note: Field usage indicates FR[n], not FR[m]. +:ftrc FRN_0t,FPUL is + OP_0=0xf & FRN_0t & DRN_1t & OP_4=0x3d & FPUL { + + if (!( $(FPSCR_PR) == 0 )) goto ; + FPUL = trunc( FRN_0t ); + goto ; + + FPUL = trunc( DRN_1t ); + +} + +# Vector Transformation +# pattern 1111nn0111111101 +# text ftrv XMTRX_M4, +# arch # arch_sh4_up +:ftrv XMTRX_t,FVN_2t is OP_0=0xf & FVN_2t & OP_8=0x1fd & XMTRX_t { + + if (!( $(FPSCR_PR) == 0 )) goto ; + temp1:4 = ( xf0 f* *[register]:4 (&:4 FVN_2t + 0) ); + temp1 = temp1 f+ ( xf4 f* *[register]:4 (&:4 FVN_2t + 4) ); + temp1 = temp1 f+ ( xf8 f* *[register]:4 (&:4 FVN_2t + 8) ); + temp1 = temp1 f+ ( xf12 f* *[register]:4 (&:4 FVN_2t + 12) ); + + temp2:4 = ( xf1 f* *[register]:4 (&:4 FVN_2t + 0) ); + temp2 = temp2 f+ ( xf5 f* *[register]:4 (&:4 FVN_2t + 4) ); + temp2 = temp2 f+ ( xf9 f* *[register]:4 (&:4 FVN_2t + 8) ); + temp2 = temp2 f+ ( xf13 f* *[register]:4 (&:4 FVN_2t + 12) ); + + temp3:4 = ( xf2 f* *[register]:4 (&:4 FVN_2t + 0) ); + temp3 = temp3 f+ ( xf6 f* *[register]:4 (&:4 FVN_2t + 4) ); + temp3 = temp3 f+ ( xf10 f* *[register]:4 (&:4 FVN_2t + 8) ); + temp3 = temp3 f+ ( xf14 f* *[register]:4 (&:4 FVN_2t + 12) ); + + temp4:4 = ( xf3 f* *[register]:4 (&:4 FVN_2t + 0) ); + temp4 = temp4 f+ ( xf7 f* *[register]:4 (&:4 FVN_2t + 4) ); + temp4 = temp4 f+ ( xf11 f* *[register]:4 (&:4 FVN_2t + 8) ); + temp4 = temp4 f+ ( xf15 f* *[register]:4 (&:4 FVN_2t + 12) ); + + # summation goes to FR[n + 0] through FR[n + 3] + *[register]:4 (&:4 FVN_2t + 0) = temp1; + *[register]:4 (&:4 FVN_2t + 4) = temp2; + *[register]:4 (&:4 FVN_2t + 8) = temp3; + *[register]:4 (&:4 FVN_2t + 12) = temp4; + +} + +# Invalidate Instruction Cache block +# pattern 0000nnnn11100011 +# text icib @ +# arch arch_sh_up +define pcodeop InvalidateCacheBlock; + +:icbi N_0t_at1 is OP_0=0x0 & N_0t_at1 & OP_4=0xe3 { + tmp:4 = N_0t_at1; + InvalidateCacheBlock(tmp); +} + +# Unconditional Branch +# pattern 0100nnnn00101011 +# text jmp @ +# arch arch_sh_up +:jmp N_0tjmp is OP_0=0x4 & N_0tjmp & OP_4=0x2b { + + PC = N_0tjmp; + tmp:4 = PC; + delayslot(1); + goto [tmp]; +} + + +# Branch to Subroutine Procedure +# pattern 0100nnnn00001011 +# text jsr @ +# arch arch_sh_up +:jsr N_0tjmp is OP_0=0x4 & N_0tjmp & OP_4=0xb { + + PR = inst_next; + PC = N_0tjmp; + tmp:4 = PC; + delayslot(1); + call [tmp]; +} + + +# Load to Control Register +# pattern 0100nnnn00001110 +# text ldc ,SR +# arch arch_sh_up +:ldc N_0t_sr is OP_0=0x4 & N_0t_sr & OP_4=0xe { + + splitSRregister(); + SR = (N_0t_sr & 0x700083f3); +} + + +# Load to Control Register +# pattern 0100nnnn00011110 +# text ldc ,GBR +# arch arch_sh_up +:ldc N_0t_gbr is OP_0=0x4 & N_0t_gbr & OP_4=0x1e { + + GBR = N_0t_gbr; +} + + +# Load to Control Register +# pattern 0100nnnn00101110 +# text ldc ,VBR +# arch arch_sh_up +:ldc N_0t_vbr is OP_0=0x4 & N_0t_vbr & OP_4=0x2e { + + VBR = N_0t_vbr; +} + + +# pattern 0100nnnn00111110 +# text ldc ,SSR +# arch arch_sh3_nommu_up +:ldc N_0t_ssr is OP_0=0x4 & N_0t_ssr & OP_4=0x3e { + + SSR = N_0t_ssr; +} + + +# pattern 0100nnnn01001110 +# text ldc ,SPC +# arch arch_sh3_nommu_up +:ldc N_0t_spc is OP_0=0x4 & N_0t_spc & OP_4=0x4e { + + SPC = N_0t_spc; +} + + +# pattern 0100nnnn11111010 +# text ldc ,DBR +# arch arch_sh4_nommu_nofpu_up +:ldc N_0t_dbr is OP_0=0x4 & N_0t_dbr & OP_4=0xfa { + + DBR = N_0t_dbr; +} + +# pattern 0100nnnn1xxx1110 +# text ldc ,Rn_BANK +# arch arch_sh3_nommu_up +:ldc N_0t_bank,BANKt is OP_0=0x4 & N_0t_bank & OP_9=0x1 & BANKt & OP_1=0xe { + + BANKt = N_0t_bank; +} + + +# Load to Control Register +# pattern 0100nnnn00000111 +# text ldc.l @+,SR +# arch arch_sh_up +:ldc.l N_0t_sr1 is OP_0=0x4 & N_0t_sr1 & OP_4=0x7 { + + SR = (*:4 ( N_0t_sr1 )) & 0x700083F3; + splitSRregister(); + N_0t_sr1 = N_0t_sr1 + 4; +} + + +# Load to Control Register +# pattern 0100nnnn00010111 +# text ldc.l @+,GBR +# arch arch_sh_up +:ldc.l N_0t_gbr1 is OP_0=0x4 & N_0t_gbr1 & OP_4=0x17 { + + GBR = *:4 ( N_0t_gbr1 ); + N_0t_gbr1 = N_0t_gbr1 + 4; +} + + +# Load to Control Register +# pattern 0100nnnn00100111 +# text ldc.l @+,VBR +# arch arch_sh_up +:ldc.l N_0t_vbr1 is OP_0=0x4 & N_0t_vbr1 & OP_4=0x27 { + + VBR = *:4 ( N_0t_vbr1 ); + N_0t_vbr1 = N_0t_vbr1 + 4; +} + + +# pattern 0100nnnn00110111 +# text ldc.l @+,SSR +# arch arch_sh3_nommu_up +:ldc.l N_0t_ssr1 is OP_0=0x4 & N_0t_ssr1 & OP_4=0x37 { + + SSR = *:4 ( N_0t_ssr1 ); + N_0t_ssr1 = N_0t_ssr1 + 4; +} + + +# pattern 0100nnnn01000111 +# text ldc.l @+,SPC +# arch arch_sh3_nommu_up +:ldc.l N_0t_spc1 is OP_0=0x4 & N_0t_spc1 & OP_4=0x47 { + + SPC = *:4 ( N_0t_spc1 ); + N_0t_spc1 = N_0t_spc1 + 4; +} + + +# pattern 0100nnnn11110110 +# text ldc.l @+,DBR +# arch arch_sh4_nommu_nofpu_up +:ldc.l N_0t_dbr1 is OP_0=0x4 & N_0t_dbr1 & OP_4=0xf6 { + + DBR = *:4 ( N_0t_dbr1 ); + N_0t_dbr1 = N_0t_dbr1 + 4; +} + + +# pattern 0100nnnn1xxx0111 +# text ldc.l @+,Rn_BANK +# arch arch_sh3_nommu_up +:ldc.l N_0t_bank1,BANKt is OP_0=0x4 & N_0t_bank1 & OP_9=0x1 & BANKt & OP_1=0x7 { + + BANKt = *:4 ( N_0t_bank1 ); + N_0t_bank1 = N_0t_bank1 + 4; +} + + +# Load to FPU System Register +# pattern 0100nnnn01011010 +# text lds ,FPUL +# arch arch_sh2e_up +:lds N_0t_fpul is OP_0=0x4 & N_0t_fpul & OP_4=0x5a { + + FPUL = N_0t_fpul; +} + + +# Load to FPU System Register +# pattern 0100nnnn01010110 +# text lds.l @+,FPUL +# arch arch_sh2e_up +:lds.l N_0t_fpul1 is OP_0=0x4 & N_0t_fpul1 & OP_4=0x56 { + + FPUL = *:4 ( N_0t_fpul1 ); + N_0t_fpul1 = N_0t_fpul1 + 4; +} + + +# Load to FPU System Register +# pattern 0100nnnn01101010 +# text lds ,FPSCR +# arch arch_sh2e_up +# Note: FPSCR context cannot be supported from this instruction; contents of N_0 not known at disassembly time. +:lds N_0t_fpscr is OP_0=0x4 & N_0t_fpscr & OP_4=0x6a { + + FPSCR = N_0t_fpscr & 0x003FFFFF; + splitFPSCRregister(); +} + + +# Load to FPU System Register +# pattern 0100nnnn01100110 +# text lds.l @+,FPSCR +# arch arch_sh2e_up +# Note: FPSCR context cannot be supported from this instruction; contents of N_0 not known at disassembly time. +:lds.l N_0t_fpscr1 is OP_0=0x4 & N_0t_fpscr1 & OP_4=0x66 { + + FPSCR = (*:4 ( N_0t_fpscr1 )) & 0x003FFFFF; + splitFPSCRregister(); + N_0t_fpscr1 = N_0t_fpscr1 + 4; +} + + +# Load to FPU System Register +# pattern 0100nnnn00001010 +# text lds ,MACH +# arch arch_sh_up +:lds N_0t_mach is OP_0=0x4 & N_0t_mach & OP_4=0xa { + + MACH = N_0t_mach; +} + + +# Load to FPU System Register +# pattern 0100nnnn00011010 +# text lds ,MACL +# arch arch_sh_up +:lds N_0t_macl is OP_0=0x4 & N_0t_macl & OP_4=0x1a { + + MACL = N_0t_macl; +} + + +# Load to FPU System Register +# pattern 0100nnnn00101010 +# text lds ,PR +# arch arch_sh_up +:lds N_0t_pr is OP_0=0x4 & N_0t_pr & OP_4=0x2a { + + PR = N_0t_pr; +} + + +# Load to FPU System Register +# pattern 0100nnnn00000110 +# text lds.l @+,MACH +# arch arch_sh_up +:lds.l N_0t_mach1 is OP_0=0x4 & N_0t_mach1 & OP_4=0x6 { + + MACH = *:4 ( N_0t_mach1 ); + N_0t_mach1 = N_0t_mach1 + 4; +} + + +# Load to FPU System Register +# pattern 0100nnnn00010110 +# text lds.l @+,MACL +# arch arch_sh_up +:lds.l N_0t_macl1 is OP_0=0x4 & N_0t_macl1 & OP_4=0x16 { + + MACL = *:4 ( N_0t_macl1 ); + N_0t_macl1 = N_0t_macl1 + 4; +} + + +# Load to FPU System Register +# pattern 0100nnnn00100110 +# text lds.l @+,PR +# arch arch_sh_up +:lds.l N_0t_pr1 is OP_0=0x4 & N_0t_pr1 & OP_4=0x26 { + + PR = *:4 ( N_0t_pr1 ); + N_0t_pr1 = N_0t_pr1 + 4; +} + +define pcodeop LoadTranslationLookasideBuffer; + +# Load to TLB +# pattern 0000000000111000 +# text ldtlb +# arch arch_sh3_up +:ldtlb is OP_3=0x38 { LoadTranslationLookasideBuffer(); } + +# Double-Precision Multiply-and-Accumulate Operation +# pattern 0000nnnnmmmm1111 +# text mac.l @+,@+ +# arch arch_sh2_up +define pcodeop mac_lOp; +:mac.l M_0t_at,N_0t_at is OP_0=0x0 & OP_1=0xf & M_0t_at & N_0t_at { + local tmpM:8 = sext(*:4 M_0t_at); + local tmpN:8 = sext(*:4 N_0t_at); + local mac:8 = zext(MACL) + (zext(MACH) << 32); + local product:8 = tmpM * tmpN; + if ($(S_FLAG) == 0) goto ; + mac = mac_lOp(mac,product); + goto ; + + mac = mac + product; + + MACL = mac[0,32]; + MACH = mac[32,32]; + M_0t_at = M_0t_at + 4; + N_0t_at = N_0t_at + 4; +} + +# Single-Precision Multiply-and-Accumulate Operation +# pattern 0100nnnnmmmm1111 +# text mac.w @+,@+ +# arch arch_sh_up +define pcodeop mac_wOp; +:mac.w M_0t_at,N_0t_at is OP_0=0x4 & OP_1=0xf & M_0t_at & N_0t_at { + local tmpM:4 = sext(*:2 M_0t_at); + local tmpN:4 = sext(*:2 N_0t_at); + local mac:8 = zext(MACL) + (zext(MACH) << 32); + local product:4 = tmpN * tmpN; + if ($(S_FLAG) == 0) goto ; + mac = mac_wOp(mac,product); + goto ; + + mac = mac + sext(product); + + MACL = mac[0,32]; + MACH = mac[32,32]; + M_0t_at = M_0t_at + 2; + N_0t_at = N_0t_at + 2; +} + +# Data Transfer +# pattern 0110nnnnmmmm0011 +# text mov , +# arch arch_sh_up +:mov M_0t,N_0t is OP_0=0x6 & N_0t & M_0t & OP_1=0x3 { + + N_0t = M_0t; +} + + +# Data Transfer +# pattern 0010nnnnmmmm0000 +# text mov.b ,@ +# arch arch_sh_up +:mov.b M_0t,N_0t_at1 is OP_0=0x2 & N_0t_at1 & M_0t & OP_1=0x0 { + + *:1 ( N_0t_at1 ) = M_0t:1; +} + + +# Data Transfer +# pattern 0010nnnnmmmm0001 +# text mov.w ,@ +# arch arch_sh_up +:mov.w M_0t,N_0t_at1 is OP_0=0x2 & N_0t_at1 & M_0t & OP_1=0x1 { + + *:2 ( N_0t_at1 ) = M_0t:2; +} + + +# Data Transfer +# pattern 0010nnnnmmmm0010 +# text mov.l ,@ +# arch arch_sh_up +:mov.l M_0t,N_0t_at1 is OP_0=0x2 & N_0t_at1 & M_0t & OP_1=0x2 { + + *:4 ( N_0t_at1 ) = M_0t; +} + + +# Data Transfer +# pattern 0110nnnnmmmm0000 +# text mov.b @, +# arch arch_sh_up +:mov.b M_0t_at1,N_0t is OP_0=0x6 & N_0t & M_0t_at1 & OP_1=0x0 { + + N_0t = sext( *:1 ( M_0t_at1 ) ); +} + + +# Data Transfer +# pattern 0110nnnnmmmm0001 +# text mov.w @, +# arch arch_sh_up +:mov.w M_0t_at1,N_0t is OP_0=0x6 & N_0t & M_0t_at1 & OP_1=0x1 { + + N_0t = sext( *:2 ( M_0t_at1 ) ); +} + + +# Data Transfer +# pattern 0110nnnnmmmm0010 +# text mov.l @, +# arch arch_sh_up +:mov.l M_0t_at1,N_0t is OP_0=0x6 & N_0t & M_0t_at1 & OP_1=0x2 { + + N_0t = *:4 ( M_0t_at1 ); +} + + +# Data Transfer +# pattern 0010nnnnmmmm0100 +# text mov.b ,@- +# arch arch_sh_up +:mov.b M_0t,N_0t_at_neg is OP_0=0x2 & N_0t_at_neg & M_0t & OP_1=0x4 { + + N_0t_at_neg = N_0t_at_neg - 1; + *:1 ( N_0t_at_neg ) = M_0t:1; +} + + +# Data Transfer +# pattern 0010nnnnmmmm0101 +# text mov.w ,@- +# arch arch_sh_up +:mov.w M_0t,N_0t_at_neg is OP_0=0x2 & N_0t_at_neg & M_0t & OP_1=0x5 { + + N_0t_at_neg = N_0t_at_neg - 2; + *:2 ( N_0t_at_neg ) = M_0t:2; +} + + +# Data Transfer +# pattern 0010nnnnmmmm0110 +# text mov.l ,@- +# arch arch_sh_up +:mov.l M_0t,N_0t_at_neg is OP_0=0x2 & N_0t_at_neg & M_0t & OP_1=0x6 { + + N_0t_at_neg = N_0t_at_neg - 4; + *:4 ( N_0t_at_neg ) = M_0t; +} + + +# Data Transfer +# pattern 0110nnnnmmmm0100 +# text mov.b @+, +# arch arch_sh_up +:mov.b M_0t_at,N_0t is OP_0=0x6 & N_0t & M_0t_at & OP_1=0x4 { + + N_0t = sext( *:1 ( M_0t_at ) ); + M_0t_at = M_0t_at + 1; +} + + +# Data Transfer +# pattern 0110nnnnmmmm0101 +# text mov.w @+, +# arch arch_sh_up +:mov.w M_0t_at,N_0t is OP_0=0x6 & N_0t & M_0t_at & OP_1=0x5 { + + N_0t = sext( *:2 ( M_0t_at ) ); + M_0t_at = M_0t_at + 2; +} + + +# Data Transfer +# pattern 0110nnnnmmmm0110 +# text mov.l @+, +# arch arch_sh_up +:mov.l M_0t_at,N_0t is OP_0=0x6 & N_0t & M_0t_at & OP_1=0x6 { + + N_0t = *:4 ( M_0t_at ); + M_0t_at = M_0t_at + 4; +} + + +# Data Transfer +# pattern 0000nnnnmmmm0100 +# text mov.b ,@(R0,) +# arch arch_sh_up +:mov.b M_0t,N_0t_at_with_r0 is OP_0=0x0 & N_0t_at_with_r0 & M_0t & OP_1=0x4 { + + *:1 ( r0 + N_0t_at_with_r0 ) = M_0t:1; +} + + +# Data Transfer +# pattern 0000nnnnmmmm0101 +# text mov.w ,@(R0,) +# arch arch_sh_up +:mov.w M_0t,N_0t_at_with_r0 is OP_0=0x0 & N_0t_at_with_r0 & M_0t & OP_1=0x5 { + + *:2 ( r0 + N_0t_at_with_r0 ) = M_0t:2; +} + + +# Data Transfer +# pattern 0000nnnnmmmm0110 +# text mov.l ,@(R0,) +# arch arch_sh_up +:mov.l M_0t,N_0t_at_with_r0 is OP_0=0x0 & N_0t_at_with_r0 & M_0t & OP_1=0x6 { + + *:4 ( r0 + N_0t_at_with_r0 ) = M_0t; +} + + +# Data Transfer +# pattern 0000nnnnmmmm1100 +# text mov.b @(R0,), +# arch arch_sh_up +:mov.b M_0t_at_with_r0,N_0t is OP_0=0x0 & N_0t & M_0t_at_with_r0 & OP_1=0xc { + + N_0t = sext( *:1 ( r0 + M_0t_at_with_r0 ) ); +} + + +# Data Transfer +# pattern 0000nnnnmmmm1101 +# text mov.w @(R0,), +# arch arch_sh_up +:mov.w M_0t_at_with_r0,N_0t is OP_0=0x0 & N_0t & M_0t_at_with_r0 & OP_1=0xd { + + N_0t = sext( *:2 ( r0 + M_0t_at_with_r0 ) ); +} + + +# Data Transfer +# pattern 0000nnnnmmmm1110 +# text mov.l @(R0,), +# arch arch_sh_up +:mov.l M_0t_at_with_r0,N_0t is OP_0=0x0 & N_0t & M_0t_at_with_r0 & OP_1=0xe { + + N_0t = *:4 ( r0 + M_0t_at_with_r0 ); +} + + +# Data Transfer +# pattern 1110nnnniiiiiiii +# text mov #, +# arch arch_sh_up +:mov I_0t,N_0t is OP_0=0xe & N_0t & I_0t { + + N_0t = I_0t; # NOTE I_0t already signed extended +} + + +# Data Transfer +# pattern 1001nnnndddddddd +# text mov.w @(,PC), +# arch arch_sh_up +:mov.w U_0t_2pc,N_0t is OP_0=0x9 & N_0t & U_0t_2pc { + + N_0t = sext( U_0t_2pc ); # NOTE U_0t_2pc units is bytes +} + + +# Data Transfer +# pattern 1101nnnndddddddd +# text mov.l @(,PC), +# arch arch_sh_up +:mov.l U_0t_4pc,N_0t is OP_0=0xd & N_0t & U_0t_4pc { + + N_0t = U_0t_4pc; # NOTE U_0t_4pc units is bytes +} + + +# Data Transfer +# pattern 11000100dddddddd +# text mov.b @(,GBR),R0 +# arch arch_sh_up +:mov.b U_0t_gbr_at_1,r0 is OP_2=0xc4 & U_0t_gbr_at_1 & r0 { + + r0 = sext( *:1 ( U_0t_gbr_at_1 ) ); +} + + +# Data Transfer +# pattern 11000101dddddddd +# text mov.w @(,GBR),R0 +# arch arch_sh_up +:mov.w U_0t_gbr_at_2,r0 is OP_2=0xc5 & U_0t_gbr_at_2 & r0 { + + r0 = sext( *:2 ( U_0t_gbr_at_2 ) ); # NOTE U_0t_gbr_at_2 units is bytes +} + + +# Data Transfer +# pattern 11000110dddddddd +# text mov.l @(,GBR),R0 +# arch arch_sh_up +:mov.l U_0t_gbr_at_4,r0 is OP_2=0xc6 & U_0t_gbr_at_4 & r0 { + + r0 = *:4 ( U_0t_gbr_at_4 ); # NOTE U_0t_gbr_at_4 units is bytes +} + + +# Data Transfer +# pattern 11000000dddddddd +# text mov.b R0,@(,GBR) +# arch arch_sh_up +:mov.b r0,U_0t_gbr_at_1 is OP_2=0xc0 & U_0t_gbr_at_1 & r0 { + + *:1 ( U_0t_gbr_at_1 ) = r0:1; +} + + +# Data Transfer +# pattern 11000001dddddddd +# text mov.w R0,@(,GBR) +# arch arch_sh_up +:mov.w r0,U_0t_gbr_at_2 is OP_2=0xc1 & U_0t_gbr_at_2 & r0 { + + *:2 ( U_0t_gbr_at_2 ) = r0:2; # NOTE U_0t_gbr_at_2 units is bytes +} + + +# Data Transfer +# pattern 11000010dddddddd +# text mov.l R0,@(,GBR) +# arch arch_sh_up +:mov.l r0, U_0t_gbr_at_4 is OP_2=0xc2 & U_0t_gbr_at_4 & r0 { + + *:4 ( U_0t_gbr_at_4 ) = r0; # NOTE U_0t_4_at_gbr_r0_1 units is bytes +} + + +# Data Transfer +# pattern 10000000mmmmdddd +# text mov.b R0,@(,) +# arch arch_sh_up +:mov.b r0,U_2t_M0_dispr01 is OP_2=0x80 & M_0t & U_2t_M0_dispr01 & r0 { + + *:1 ( U_2t_M0_dispr01 + M_0t ) = r0:1; +} + + +# Data Transfer +# pattern 10000001mmmmdddd +# text mov.w R0,@(,) +# arch arch_sh_up +:mov.w r0,U_2t_M0_dispr02 is OP_2=0x81 & M_0t & U_2t_M0_dispr02 & r0 { + + *:2 ( U_2t_M0_dispr02 + M_0t ) = r0:2; # NOTE U_2t_M0_dispr02 units is bytes +} + + +# Data Transfer +# pattern 0001nnnnmmmmdddd +# text mov.l ,@(,) +# arch arch_sh_up +:mov.l M_0t,U_2t_N0_dispr04 is OP_0=0x1 & M_0t & N_0t & U_2t_N0_dispr04 { + + *:4 ( U_2t_N0_dispr04 + N_0t ) = M_0t; # NOTE U_2t_N0_dispr04 units is bytes +} + + +# Data Transfer +# pattern 10000100mmmmdddd +# text mov.b @(,),R0 +# arch arch_sh_up +:mov.b U_2t_M0_dispr01,r0 is OP_2=0x84 & M_0t & U_2t_M0_dispr01 & r0 { + + r0 = sext( *:1 ( U_2t_M0_dispr01 + M_0t ) ); +} + + +# Data Transfer +# pattern 10000101mmmmdddd +# text mov.w @(,),R0 +# arch arch_sh_up +:mov.w U_2t_M0_dispr02,r0 is OP_2=0x85 & U_2t_M0_dispr02 & M_0t & r0 { + + r0 = sext( *:2 ( U_2t_M0_dispr02 + M_0t ) ); # NOTE U_2t_M0_dispr02 units is bytes +} + + +# Data Transfer +# pattern 0101nnnnmmmmdddd +# text mov.l @(,), +# arch arch_sh_up +:mov.l U_2t_M0_dispr04,N_0t is OP_0=0x5 & N_0t & M_0t & U_2t_M0_dispr04 { + + N_0t = *:4 ( U_2t_M0_dispr04 + M_0t ); # NOTE U_2t_M0_dispr04 units is bytes +} + + +# Effective Address Transfer +# pattern 11000111iiiiiiii +# text mova @(,PC),R0 +# arch arch_sh_up +:mova U_0t_4pc,r0 is OP_2=0xc7 & U_0t_4pc & r0 { + + r0 = &U_0t_4pc; # NOTE U_0t_4pc units is bytes +} + + +# MOVe with Cache block Allocation +# pattern 0000nnnn11000011 +# text movca.l R0,@ +# arch arch_sh4_nommu_nofpu_up +:movca.l N_0txx is OP_0=0x0 & N_0txx & OP_4=0xc3 { + + *:4 ( N_0txx ) = r0; # NOTE ignore cache issues +} + +# T Bit Transfer +# pattern 0000nnnn00101001 +# text movt +# arch +:movt N_0t is OP_0=0x0 & N_0t & OP_4=0x29 { + + N_0t = zext($(T_FLAG)); +} + +# Move Unaligned Long +# pattern 0100mmmm10101001 +# text movua.l @,R0 +# arch +:movua.l N_0t_at,r0 is OP_0=0x4 & N_0t_at & r0 & OP_4=0xA9 { + r0 = (*:4 ( N_0t_at )); +} + +# Move Unaligned Long Pointer +# pattern 0100mmmm11101001 +# text movua.l @+,R0 +# arch +:movua.l N_0t_at,r0 is OP_0=0x4 & N_0t_at & r0 & OP_4=0xE9 { + r0 = (*:4 ( N_0t_at )); + N_0t_at = N_0t_at + 4; +} + +:movua.l N_0t_at,r0 is OP_0=0x4 & N_0t_at & N_0=0 & r0 & OP_4=0xE9 { + r0 = (*:4 ( N_0t_at )); +} + +# Double-Precision Multiplication +# pattern 0000nnnnmmmm0111 +# text mul.l , +# arch +:mul.l M_0t,N_0t is OP_0=0x0 & N_0t & M_0t & OP_1=0x7 { + + MACL = N_0t * M_0t; +} + + +# Signed Multiplication +# pattern 0010nnnnmmmm1111 +# text muls.w , +# arch +:muls.w M_0t,N_0t is OP_0=0x2 & N_0t & M_0t & OP_1=0xf { + + MACL = sext(N_0t:2) * sext(M_0t:2); +} + + +# Unsigned Multiplication +# pattern 0010nnnnmmmm1110 +# text mulu.w , +# arch +:mulu.w M_0t,N_0t is OP_0=0x2 & N_0t & M_0t & OP_1=0xe { + + MACL = zext(N_0t:2) * zext(M_0t:2); +} + + +# Sign Inversion +# pattern 0110nnnnmmmm1011 +# text neg , +# arch +:neg M_0t,N_0t is OP_0=0x6 & N_0t & M_0t & OP_1=0xb { + + N_0t = -M_0t; +} + + +# Sign Inversion with Borrow +# pattern 0110nnnnmmmm1010 +# text negc , +# arch +:negc M_0t,N_0t is OP_0=0x6 & N_0t & M_0t & OP_1=0xa { + local Tcopy:4 = zext($(T_FLAG)); + $(T_FLAG) = 0 != M_0t; + local result:4 = - M_0t; + $(T_FLAG) = $(T_FLAG) || (result < Tcopy); + N_0t = result - Tcopy; +} + + +# No Operation +# pattern 0000000000001001 +# text nop +# arch +:nop is OP_3=0x9 { } # Empty on purpose + + +# Bit Inversion +# pattern 0110nnnnmmmm0111 +# text not , +# arch +:not M_0t,N_0t is OP_0=0x6 & N_0t & M_0t & OP_1=0x7 { + + N_0t = ~M_0t; +} + +define pcodeop CacheBlockInvalidate; + +# Operand Cache Block Invalidate +# pattern 0000nnnn10010011 +# text ocbi @ +# arch +:ocbi N_0t_at1 is OP_0=0x0 & N_0t_at1 & OP_4=0x93 { CacheBlockInvalidate(N_0t_at1); } + +define pcodeop CacheBlockPurge; + +# Cache Block Purge +# pattern 0000nnnn10100011 +# text ocbp @ +# arch +:ocbp N_0t_at1 is OP_0=0x0 & N_0t_at1 & OP_4=0xa3 { CacheBlockPurge(N_0t_at1); } + +define pcodeop CacheBlockWriteBack; + +# TODO ocbwb +# Cache Block Write-Back +# pattern 0000nnnn10110011 +# text ocbwb @ +# arch +:ocbwb N_0t_at1 is OP_0=0x0 & N_0t_at1 & OP_4=0xb3 { CacheBlockWriteBack(N_0t_at1); } + + +# Logical OR +# pattern 0010nnnnmmmm1011 +# text or , +# arch +:or M_0t,N_0t is OP_0=0x2 & N_0t & M_0t & OP_1=0xb { + + N_0t = N_0t | M_0t; +} + + +# Logical OR +# pattern 11001011iiiiiiii +# text or #,R0 +# arch +:or U_0t_r0 is OP_2=0xcb & U_0t_r0 { + + r0 = r0 | U_0t_r0; +} + + +# Logical OR +# pattern 11001111iiiiiiii +# text or.b #,@(R0,GBR) +# arch +:or.b U_0t1 is OP_2=0xcf & U_0t1 { + + *:1 (GBR + r0) = ( *:1 (GBR + r0) ) | U_0t1; +} + + +# Prefetch to Data Cache +# pattern 0000nnnn10000011 +# text pref @ +# arch +:pref N_0tjmp is OP_0=0x0 & N_0tjmp & OP_4=0x83 { } # Empty on purpose + + +# One-Bit Left Rotation through T Bit +# pattern 0100nnnn00100100 +# text rotcl +# arch +:rotcl N_0t is OP_0=0x4 & N_0t & OP_4=0x24 { + + temp:1 = ( (N_0t & 0x80000000) != 0 ); + N_0t = (N_0t << 1) | zext($(T_FLAG)); + $(T_FLAG) = temp; +} + +# One-Bit Right Rotation through T Bit +# pattern 0100nnnn00100101 +# text rotcr +# arch +:rotcr N_0t is OP_0=0x4 & N_0t & OP_4=0x25 { + + temp:1 = ( (N_0t & 0x00000001) != 0 ); + N_0t = ( N_0t >> 1 ) | ( zext($(T_FLAG)) << 31 ); + $(T_FLAG) = temp; +} + + +# One-Bit Left Rotation +# pattern 0100nnnn00000100 +# text rotl +# arch +:rotl N_0t is OP_0=0x4 & N_0t & OP_4=0x4 { + + $(T_FLAG) = ( (N_0t & 0x80000000) != 0 ); + N_0t = (N_0t << 1) | zext($(T_FLAG)); +} + + +# One-Bit Right Rotation +# pattern 0100nnnn00000101 +# text rotr +# arch +:rotr N_0t is OP_0=0x4 & N_0t & OP_4=0x5 { + + $(T_FLAG) = ( (N_0t & 0x00000001) != 0 ); + N_0t = ( N_0t >> 1 ) | ( zext($(T_FLAG)) << 31 ); +} + + +# Return from Exception Handling +# pattern 0000000000101011 +# text rte +# arch +:rte is OP_3=0x2b { + + SR = SSR; + splitSRregister(); + PC = SPC; + delayslot(1); + return [PC]; +} + + +# Return from Subroutine Procedure +# pattern 0000000000001011 +# text rts +# arch +:rts is OP_3=0xb { + + PC = PR; + delayslot(1); + return [PC]; +} + + +# S Bit Setting +# pattern 0000000001011000 +# text sets +# arch +:sets is OP_3=0x58 { + + $(S_FLAG) = 1; +} + + +# T Bit Setting +# pattern 0000000000011000 +# text sett +# arch +:sett is OP_3=0x18 { + + $(T_FLAG) = 1; +} + + +# Note: this constructor follows the description on page 393 precisely, though simpler, +# it should produce identical results to the pseudo-code above +:shad M_0t,N_0t is OP_0=0x4 & N_0t & M_0t & OP_1=0xc { + + if ( M_0t s< 0 ) goto ; + N_0t = N_0t << ( M_0t & 0x1f ); + goto ; + + + N_0t = N_0t s>> ( ( ~M_0t & 0x1f ) + 1 ); + +} + + +# One-Bit Left Arithmetic Shift +# pattern 0100nnnn00100000 +# text shal +# arch +:shal N_0t is OP_0=0x4 & N_0t & OP_4=0x20 { + + $(T_FLAG) = ( ( N_0t & 0x80000000 ) != 0 ); + N_0t = N_0t << 1; +} + + +# One-Bit Right Arithmetic Shift +# pattern 0100nnnn00100001 +# text shar +# arch +:shar N_0t is OP_0=0x4 & N_0t & OP_4=0x21 { + + $(T_FLAG) = ( ( N_0t & 0x00000001 ) != 0 ); + N_0t = N_0t s>> 1; +} + + +# Note: this constructor follows the description on page 397 precisely, though simpler, +# it should produce identical results to the pseudo-code above +:shld M_0t,N_0t is OP_0=0x4 & N_0t & M_0t & OP_1=0xd { + + if ( M_0t s< 0 ) goto ; + N_0t = N_0t << ( M_0t & 0x1f ); + goto ; + + + N_0t = N_0t >> ( ( ~M_0t & 0x1f ) + 1 ); + +} + + +# n-Bit Left Logical Shift +# One-Bit Left Logical Shift +# pattern 0100nnnn00000000 +# text shll +# arch +:shll N_0t is OP_0=0x4 & N_0t & OP_4=0x0 { + + $(T_FLAG) = ( ( N_0t & 0x80000000 ) != 0 ); + N_0t = N_0t << 1; +} + + +# n-Bit Left Logical Shift +# pattern 0100nnnn00001000 +# text shll2 +# arch +:shll2 N_0t is OP_0=0x4 & N_0t & OP_4=0x8 { + + N_0t = ( N_0t << 2 ); +} + + +# n-Bit Left Logical Shift +# pattern 0100nnnn00011000 +# text shll8 +# arch +:shll8 N_0t is OP_0=0x4 & N_0t & OP_4=0x18 { + + N_0t = ( N_0t << 8 ); +} + + +# pattern 0100nnnn00101000 +# text shll16 +# arch +:shll16 N_0t is OP_0=0x4 & N_0t & OP_4=0x28 { + + N_0t = ( N_0t << 16 ); +} + + +# One-Bit Right Logical Shift +# pattern 0100nnnn00000001 +# text shlr +# arch +:shlr N_0t is OP_0=0x4 & N_0t & OP_4=0x1 { + + $(T_FLAG) = ( ( N_0t & 0x00000001 ) != 0 ); + N_0t = N_0t >> 1; +} + + +# n-Bit Left Logical Shift +# pattern 0100nnnn00001001 +# text shlr2 +# arch +:shlr2 N_0t is OP_0=0x4 & N_0t & OP_4=0x9 { + + N_0t = N_0t >> 2; +} + + +# n-Bit Left Logical Shift +# pattern 0100nnnn00011001 +# text shlr8 +# arch +:shlr8 N_0t is OP_0=0x4 & N_0t & OP_4=0x19 { + + N_0t = N_0t >> 8; +} + + +# n-Bit Left Logical Shift +# pattern 0100nnnn00101001 +# text shlr16 +# arch +:shlr16 N_0t is OP_0=0x4 & N_0t & OP_4=0x29 { + + N_0t = N_0t >> 16; +} + + +# Transition to Power-Down Mode +# pattern 0000000000011011 +# text sleep +# arch +:sleep is OP_3=0x1b { } # empty on purpose + + +# Store from Control Register +# pattern 0000nnnn00000010 +# text stc SR, +# arch arch_sh_up +:stc sr_N_0t is OP_0=0x0 & sr_N_0t & OP_4=0x2 { + + genSRregister(); + sr_N_0t = SR; +} + + +# Store from Control Register +# pattern 0000nnnn00010010 +# text stc GBR, +# arch +:stc gbr_N_0t is OP_0=0x0 & gbr_N_0t & OP_4=0x12 { + + gbr_N_0t = GBR; +} + + +# Store from Control Register +# pattern 0000nnnn00100010 +# text stc VBR, +# arch arch_sh_up +:stc vbr_N_0t is OP_0=0x0 & vbr_N_0t & OP_4=0x22 { + + vbr_N_0t = VBR; +} + + +# pattern 0000nnnn00110010 +# text stc SSR, +# arch arch_sh3_nommu_up +:stc ssr_N_0t is OP_0=0x0 & ssr_N_0t & OP_4=0x32 { + + ssr_N_0t = SSR; +} + + +# pattern 0000nnnn01000010 +# text stc SPC, +# arch arch_sh3_nommu_up +# +:stc spc_N_0t is OP_0=0x0 & spc_N_0t & OP_4=0x42 { + + spc_N_0t = SPC; +} + + +# pattern 0000nnnn00111010 +# text stc SGR, +# arch arch_sh4_nommu_nofpu_up +:stc sgr_N_0t is OP_0=0x0 & sgr_N_0t & OP_4=0x3a { + + sgr_N_0t = SGR; +} + + +# pattern 0000nnnn11111010 +# text stc DBR, +# arch arch_sh4_nommu_nofpu_up +:stc dbr_N_0t is OP_0=0x0 & dbr_N_0t & OP_4=0xfa { + + dbr_N_0t = DBR; +} + + +# pattern 0000nnnn1xxx0010 +# text stc Rn_BANK, +# arch arch_sh3_nommu_up +:stc BANKt,N_0t_bank is OP_0=0x0 & N_0t_bank & OP_9=0x1 & BANKt & OP_1=0x2 { + + N_0t_bank = BANKt; +} + + +# Store from Control Register +# pattern 0100nnnn00000011 +# text stc.l SR,@- +# arch arch_sh_up +:stc.l sr_t,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_4=0x3 & sr_t { + + N_0t_at_neg = N_0t_at_neg - 4; + genSRregister(); + *:4 ( N_0t_at_neg ) = SR; +} + + +# Store from Control Register +# pattern 0100nnnn00010011 +# text stc.l GBR,@- +# arch arch_sh_up +:stc.l gbr_t,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_4=0x13 & gbr_t { + + N_0t_at_neg = N_0t_at_neg - 4; + *:4 ( N_0t_at_neg ) = GBR; +} + + +# Store from Control Register +# pattern 0100nnnn00100011 +# text stc.l VBR,@- +# arch arch_sh_up +:stc.l vbr_t,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_4=0x23 & vbr_t { + + N_0t_at_neg = N_0t_at_neg - 4; + *:4 ( N_0t_at_neg ) = VBR; +} + + +# pattern 0100nnnn00110011 +# text stc.l SSR,@- +# arch arch_sh3_nommu_up +:stc.l ssr_t,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_4=0x33 & ssr_t { + + N_0t_at_neg = N_0t_at_neg - 4; + *:4 ( N_0t_at_neg ) = SSR; +} + + +# pattern 0100nnnn01000011 +# text stc.l SPC,@- +# arch arch_sh3_nommu_up +:stc.l spc_t,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_4=0x43 & spc_t { + + N_0t_at_neg = N_0t_at_neg - 4; + *:4 ( N_0t_at_neg ) = SPC; +} + + +# pattern 0100nnnn00110010 +# text stc.l SGR,@- +# arch arch_sh4_nommu_nofpu_up +:stc.l sgr_t,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_4=0x32 & sgr_t { + + N_0t_at_neg = N_0t_at_neg - 4; + *:4 ( N_0t_at_neg ) = SGR; +} + + +# pattern 0100nnnn11110010 +# text stc.l DBR,@- +# arch arch_sh4_nommu_nofpu_up +:stc.l dbr_t,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_4=0xf2 & dbr_t { + + N_0t_at_neg = N_0t_at_neg - 4; + *:4 ( N_0t_at_neg ) = DBR; +} + + +# pattern 0100nnnn1xxx0011 +# text stc.l Rn_BANK,@- +# arch arch_sh3_nommu_up +:stc.l BANKt,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_9=0x1 & BANKt & OP_1=0x3 { + + N_0t_at_neg = N_0t_at_neg - 4; + *:4 ( N_0t_at_neg ) = BANKt; +} + + +# Store from System Register +# pattern 0000nnnn00001010 +# text sts MACH, +# arch arch_sh_up +:sts mach_N_0t is OP_0=0x0 & mach_N_0t & OP_4=0xa { + + mach_N_0t = MACH; +} + + +# Store from System Register +# pattern 0000nnnn00011010 +# text sts MACL, +# arch arch_sh_up +:sts macl_N_0t is OP_0=0x0 & macl_N_0t & OP_4=0x1a { + + macl_N_0t = MACL; +} + + +# Store from System Register +# pattern 0000nnnn00101010 +# text sts PR, +# arch arch_sh_up +:sts pr_N_0t is OP_0=0x0 & pr_N_0t & OP_4=0x2a { + + pr_N_0t = PR; +} + + +# Store from Control Register +# pattern 0100nnnn00000010 +# text sts.l MACH,@- +# arch arch_sh_up +:sts.l mach_t,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_4=0x2 & mach_t { + + N_0t_at_neg = N_0t_at_neg - 4; + *:4 ( N_0t_at_neg ) = MACH; +} + + +# Store from Control Register +# pattern 0100nnnn00010010 +# text sts.l MACL,@- +# arch arch_sh_up +:sts.l macl_t,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_4=0x12 & macl_t { + + N_0t_at_neg = N_0t_at_neg - 4; + *:4 ( N_0t_at_neg ) = MACL; +} + + +# Store from Control Register +# pattern 0100nnnn00100010 +# text sts.l PR,@- +# arch arch_sh_up +:sts.l PR,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_4=0x22 & PR { + + N_0t_at_neg = N_0t_at_neg - 4; + *:4 ( N_0t_at_neg ) = PR; +} + + +# Store from System Register +# pattern 0000nnnn01011010 +# text sts FPUL, +# arch arch_sh2e_up +:sts fpul_N_0t is OP_0=0x0 & fpul_N_0t & OP_4=0x5a { + + fpul_N_0t = FPUL; +} + + +# Store from System Register +# pattern 0000nnnn01101010 +# text sts FPSCR, +# arch arch_sh2e_up +:sts fpscr_N_0t is OP_0=0x0 & fpscr_N_0t & OP_4=0x6a { + + genFPSCRregister(); + fpscr_N_0t = FPSCR; +} + + +# Store from Control Register +# pattern 0100nnnn01010010 +# text sts.l FPUL,@- +# arch arch_sh2e_up +:sts.l fpul_t,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_4=0x52 & fpul_t { + + N_0t_at_neg = N_0t_at_neg - 4; + *:4 ( N_0t_at_neg ) = FPUL; +} + + +# Store from Control Register +# pattern 0100nnnn01100010 +# text sts.l FPSCR,@- +# arch arch_sh2e_up +:sts.l fpscr_t,N_0t_at_neg is OP_0=0x4 & N_0t_at_neg & OP_4=0x62 & fpscr_t { + + N_0t_at_neg = N_0t_at_neg - 4; + genFPSCRregister(); + *:4 ( N_0t_at_neg ) = FPSCR; +} + + +# Binary Subtraction +# pattern 0011nnnnmmmm1000 +# text sub , +# arch arch_sh_up +:sub M_0t,N_0t is OP_0=0x3 & N_0t & M_0t & OP_1=0x8 { + + N_0t = N_0t - M_0t; +} + + +# Binary Subtraction with Borrow +# pattern 0011nnnnmmmm1010 +# text subc , +# arch arch_sh_up +:subc M_0t,N_0t is OP_0=0x3 & N_0t & M_0t & OP_1=0xa { + local Tcopy:4 = zext($(T_FLAG)); + $(T_FLAG) = N_0t < M_0t; + local result:4 = N_0t - M_0t; + $(T_FLAG) = $(T_FLAG) || (result < Tcopy); + N_0t = result - Tcopy; +} + + +# Binary Subtraction with Underflow Check +# pattern 0011nnnnmmmm1011 +# text subv , +# arch arch_sh_up +:subv M_0t,N_0t is OP_0=0x3 & N_0t & M_0t & OP_1=0xb { + $(T_FLAG) = sborrow(N_0t, M_0t); + N_0t = N_0t - M_0t; +} + + +# Upper-/Lower-Half Swap +# pattern 0110nnnnmmmm1000 +# text swap.b , +# arch arch_sh_up +:swap.b M_0t,N_0t is OP_0=0x6 & N_0t & M_0t & OP_1=0x8 { + + N_0t = ( M_0t & 0xFFFF0000 ) | + ( ( M_0t & 0x000000FF ) << 8 ) | + ( ( M_0t & 0x0000FF00 ) >> 8 ); +} + + +# Upper-/Lower-Half Swap +# pattern 0110nnnnmmmm1001 +# text swap.w , +# arch arch_sh_up +:swap.w M_0t,N_0t is OP_0=0x6 & N_0t & M_0t & OP_1=0x9 { + + N_0t = ( M_0t << 16 ) | ( M_0t >> 16 ); +} + +# Synchronize Data Operation +# pattern 0000000010101011 +# text synco +# arch arch_sh4a_up +define pcodeop SynchronizeDataOperation; + +:synco is OP_3=0x00ab { + SynchronizeDataOperation(); +} + + +# Memory Test and Bit Setting +# pattern 0100nnnn00011011 +# text tas.b @ +# arch arch_sh_up +:tas.b N_0t_at1 is OP_0=0x4 & N_0t_at1 & OP_4=0x1b { + + temp:1 = *:1 ( N_0t_at1 ); + $(T_FLAG) = ( temp == 0 ); + temp = temp | 0x80; + *:1 ( N_0t_at1 ) = temp; +} + +define pcodeop TrapAlways; + +# Trap Exception Handling +# pattern 11000011iiiiiiii +# text trapa # +# arch arch_sh_up +:trapa U_0t is OP_2=0xc3 & U_0t { TrapAlways(U_0t); } + + +# AND Operation T Bit Setting +# pattern 0010nnnnmmmm1000 +# text tst , +# arch arch_sh_up +:tst M_0t,N_0t is OP_0=0x2 & N_0t & M_0t & OP_1=0x8 { + + $(T_FLAG) = ( (N_0t & M_0t) == 0 ); +} + + +# AND Operation T Bit Setting +# pattern 11001000iiiiiiii +# text tst #,R0 +# arch arch_sh_up +:tst U_0t_r0 is OP_2=0xc8 & U_0t_r0 { + + $(T_FLAG) = ( ( r0 & U_0t_r0 ) == 0 ); +} + + +# AND Operation T Bit Setting +# pattern 11001100iiiiiiii +# text tst.b #,@(R0,GBR) +# arch arch_sh_up +:tst.b U_0t1 is OP_2=0xcc & U_0t1 { + + $(T_FLAG) = ( ( (*:1 ( GBR + r0 )) & U_0t1 ) == 0 ); +} + + +# pattern 0010nnnnmmmm1010 +# text xor , +# arch arch_sh_up +:xor M_0t,N_0t is OP_0=0x2 & N_0t & M_0t & OP_1=0xa { + + N_0t = N_0t ^ M_0t; +} + + +# Exclusive Logical OR +# pattern 11001010iiiiiiii +# text xor #,R0 +# arch arch_sh_up +:xor U_0t_r0 is OP_2=0xca & U_0t_r0 { + + r0 = r0 ^ U_0t_r0; +} + + +# Exclusive Logical OR +# pattern 11001110iiiiiiii +# text xor.b #,@(R0,GBR) +# arch arch_sh_up +:xor.b U_0t1 is OP_2=0xce & U_0t1 { + + *:1 (GBR + r0) = ( *:1 (GBR + r0) ) ^ U_0t1; +} + + +# Middle Extraction from Linked Registers +# pattern 0010nnnnmmmm1101 +# text xtrct , +# arch arch_sh_up +:xtrct M_0t,N_0t is OP_0=0x2 & N_0t & M_0t & OP_1=0xd { + + N_0t = (M_0t << 16) | (N_0t >> 16); +} + diff --git a/python/icicle/Ghidra/Processors/SuperH4/data/languages/SuperH4_be.cspec b/python/icicle/Ghidra/Processors/SuperH4/data/languages/SuperH4_be.cspec new file mode 100644 index 0000000..05a39f4 --- /dev/null +++ b/python/icicle/Ghidra/Processors/SuperH4/data/languages/SuperH4_be.cspec @@ -0,0 +1,128 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/SuperH4/data/languages/SuperH4_be.slaspec b/python/icicle/Ghidra/Processors/SuperH4/data/languages/SuperH4_be.slaspec new file mode 100644 index 0000000..0c2d7e7 --- /dev/null +++ b/python/icicle/Ghidra/Processors/SuperH4/data/languages/SuperH4_be.slaspec @@ -0,0 +1,8 @@ +# This module defines SuperH version 4a, but should work against versions 1,2, and 3. +# DSP Extensions are not yet added + +# Based on "Renesas SH-4 Software Manual: Rev 6.00 2006.09 (i.e. rej09b0318_sh_4sm.pdf) + +@define ENDIAN "big" + +@include "SuperH4.sinc" diff --git a/python/icicle/Ghidra/Processors/SuperH4/data/languages/SuperH4_le.cspec b/python/icicle/Ghidra/Processors/SuperH4/data/languages/SuperH4_le.cspec new file mode 100644 index 0000000..92dc5b3 --- /dev/null +++ b/python/icicle/Ghidra/Processors/SuperH4/data/languages/SuperH4_le.cspec @@ -0,0 +1,128 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/SuperH4/data/languages/SuperH4_le.slaspec b/python/icicle/Ghidra/Processors/SuperH4/data/languages/SuperH4_le.slaspec new file mode 100644 index 0000000..130c77f --- /dev/null +++ b/python/icicle/Ghidra/Processors/SuperH4/data/languages/SuperH4_le.slaspec @@ -0,0 +1,9 @@ +# This module defines SuperH version 4, but should work against versions 1,2, and 3. +# There is a SuperH version 4A (which has 4 byte instruction length) which has instructions incompatable +# with this. + +# Based on "Renesas SH-4 Software Manual: Rev 6.00 2006.09 (i.e. rej09b0318_sh_4sm.pdf) + +@define ENDIAN "little" + +@include "SuperH4.sinc" diff --git a/python/icicle/Ghidra/Processors/SuperH4/data/languages/old/SuperH4-BE-16.lang b/python/icicle/Ghidra/Processors/SuperH4/data/languages/old/SuperH4-BE-16.lang new file mode 100644 index 0000000..4967b58 --- /dev/null +++ b/python/icicle/Ghidra/Processors/SuperH4/data/languages/old/SuperH4-BE-16.lang @@ -0,0 +1,131 @@ + + + + SuperH4:BE:16:default + SuperH4 + default + 16 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/SuperH4/data/languages/old/SuperH4-BE-16.trans b/python/icicle/Ghidra/Processors/SuperH4/data/languages/old/SuperH4-BE-16.trans new file mode 100644 index 0000000..e743073 --- /dev/null +++ b/python/icicle/Ghidra/Processors/SuperH4/data/languages/old/SuperH4-BE-16.trans @@ -0,0 +1,7 @@ + + + SuperH4:BE:16:default + SuperH4:BE:32:default + + + diff --git a/python/icicle/Ghidra/Processors/SuperH4/data/languages/old/SuperH4-LE-16.lang b/python/icicle/Ghidra/Processors/SuperH4/data/languages/old/SuperH4-LE-16.lang new file mode 100644 index 0000000..13a227f --- /dev/null +++ b/python/icicle/Ghidra/Processors/SuperH4/data/languages/old/SuperH4-LE-16.lang @@ -0,0 +1,131 @@ + + + + SuperH4:LE:16:default + SuperH4 + default + 16 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/SuperH4/data/languages/old/SuperH4-LE-16.trans b/python/icicle/Ghidra/Processors/SuperH4/data/languages/old/SuperH4-LE-16.trans new file mode 100644 index 0000000..85a9f27 --- /dev/null +++ b/python/icicle/Ghidra/Processors/SuperH4/data/languages/old/SuperH4-LE-16.trans @@ -0,0 +1,7 @@ + + + SuperH4:LE:16:default + SuperH4:LE:32:default + + + diff --git a/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/TI430Common.sinc b/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/TI430Common.sinc new file mode 100644 index 0000000..f286568 --- /dev/null +++ b/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/TI430Common.sinc @@ -0,0 +1,1678 @@ +# +# TI MSP430 +# +# Texas Instruments microcontroller 16-bit CPU + + +# +# Memory Architecture +# + +define endian=$(ENDIAN); +define alignment=2; +define space RAM type=ram_space size=$(REG_SIZE) default; +define space register type=register_space size=2; + +# +# General Registers +# +define register offset=0x0000 size=$(REG_SIZE) [ + PC # R0 # Program Counter + SP # R1 # Stack Pointer + SR # R2 # Status Register + R3 # R3 # Constant Generator + + #Available for general use: + R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + + #None: + None +]; + +@if REG_SIZE == "4" + +define register offset=0x0000 size=2 [ + PC_16 _ SP_16 _ SR_16 _ R3_16 _ R4_16 _ R5_16 _ R6_16 _ R7_16 _ + R8_16 _ R9_16 _ R10_16 _ R11_16 _ R12_16 _ R13_16 _ R14_16 _ R15_16 _ + +]; + +define register offset=0x0000 size=1 [ + PC_lo PC_hi _ _ # R0 # Program Counter + SP_lo SP_hi _ _ # R1 # Stack Pointer + SR_lo SR_hi _ _ # R2 # Status Register + R3_lo R3_hi _ _ # R3 # Constant Generator + + #Available for general use: + R4_lo R4_hi _ _ + R5_lo R5_hi _ _ + R6_lo R6_hi _ _ + R7_lo R7_hi _ _ + R8_lo R8_hi _ _ + R9_lo R9_hi _ _ + R10_lo R10_hi _ _ + R11_lo R11_hi _ _ + R12_lo R12_hi _ _ + R13_lo R13_hi _ _ + R14_lo R14_hi _ _ + R15_lo R15_hi _ _ + + #None: + None_lo None_hi _ _ +]; +@else + +define register offset=0x0000 size=1 [ + PC_lo PC_hi # R0 # Program Counter + SP_lo SP_hi # R1 # Stack Pointer + SR_lo SR_hi # R2 # Status Register + R3_lo R3_hi # R3 # Constant Generator + + #Available for general use: + R4_lo R4_hi + R5_lo R5_hi + R6_lo R6_hi + R7_lo R7_hi + R8_lo R8_hi + R9_lo R9_hi + R10_lo R10_hi + R11_lo R11_hi + R12_lo R12_hi + R13_lo R13_hi + R14_lo R14_hi + R15_lo R15_hi + + #None: + None_lo None_hi +]; + +@endif + +define register offset=0x1000 size=4 contextreg; +define context contextreg +# NOTE: Only instructions that don't use immediates (except ones from constant generator) can +# use the repeat feature. +# NOTE: The POPM/PUSM have a starting register & # of register to pop/push. We need to track +# that info in context for the subtables that do the work. + ctx_isHi=(0,0) noflow # Used in pspec to flag msp430 instruction > 64k + ctx_al=(1,1) noflow # extension word al field + ctx_ctregdest=(2,5) noflow # extension word dest register/immediate field + ctx_ctregdests=(2,5) signed noflow # signed version of above + ctx_repreg=(2,5) noflow # register repeat count comes from. + ctx_regsrc=(6,9) noflow # extension word src register/immediate field + ctx_regsrcs=(6,9) signed noflow # signed version of above + ctx_zc=(10,10) noflow # extension word zero carry field + ctx_num=(11,11) noflow # is repetition field a # or register + ctx_haveext=(12,14) noflow # used to track type of extension word used + ctx_popreg_set=(15,18) noflow # used to set register for POPM/PUSHM instructions + ctx_popreg=(15,18) noflow # display register, linked for POPM/PUSHM instructions + ctx_count=(19,22) noflow # tracks count of registers for POPM/PUSHM + ctx_mreg=(23,26) noflow # register being accessed in POPM/PUSHM +; + +define register offset=0x2000 size=1 [ CNT ]; + +# +# Tokens +# +define token instr16(16) + op16_0_8 = (0, 7) + op16_4_4 = (4, 7) + op16_0_4 = (0, 3) + op16_7_9 = (7, 15) + op16_8_4 = (8, 11) + op16_8_8 = (8, 15) + op16_12_4 = (12, 15) + opext_11_5 = (11, 15) + op16_7_1 = (7, 7) + op16_13_3 = (13, 15) + + src = (0, 3) + dest = (0, 3) + + as = (4, 5) + bow = (6, 6) + insid = (4, 7) + insidbig = (4, 9) + reg16_0_4 = (0, 3) + dest_0_4 = (0, 3) + imm_0_4 = (0, 4) + reg_Direct16_0_4 = (0, 3) + reg_Direct16_0_4W = (0, 3) + reg_Indexed16_0_4 = (0, 3) + reg_InDirect16_0_4 = (0, 3) + dest_Direct16_0_4 = (0, 3) + dest_Indexed16_0_4 = (0, 3) + dest_Direct_lo = (0, 3) + dest_Direct_hi = (0, 3) + + condition = (10, 12) + + off16 = (0, 9) signed + off16_8_2 = (8, 9) + off16_4_4 = (4, 7) + off16_0_4 = (0, 3) + + zc = (8, 8) + ad = (7, 7) + al = (6, 6) + imm_4_4 = (4, 7) + imm_8_4 = (8, 11) + src_8_4 = (8, 11) + src16_8_4 = (8, 11) + src_Direct16_8_4 = (8, 11) + reg_Direct16_8_4W = (8, 11) + src_InDirect16_8_4 = (8, 11) + src_Indexed16_8_4 = (8, 11) + src_Direct_lo = (8, 11) + src_Direct_hi = (8, 11) + src_ext = (7, 10) + rrn = (10, 11) + + imm_0_16 = (0, 15) + imms_0_16 = (0, 15) signed + indexExtWord16_0_16 = (0, 15) + indexExtWord16_0_16s = (0, 15) signed + indexExt2Word16_0_16 = (0, 15) + indexExt2Word16_0_16s = (0, 15) signed +; + + +# +# Attach(s) +# +attach variables [ src_8_4 + dest_0_4 + reg_Direct16_0_4 + src_Direct16_8_4 + dest_Direct16_0_4 + ctx_popreg + ctx_repreg ] [ PC SP SR R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 ]; + +attach variables [ dest_Direct_lo src_Direct_lo] [ PC_lo SP_lo SR_lo _ R4_lo R5_lo R6_lo R7_lo + R8_lo R9_lo R10_lo R11_lo R12_lo R13_lo R14_lo R15_lo ]; +attach variables [ dest_Direct_hi src_Direct_hi] [ PC_hi SP_hi SR_hi _ R4_hi R5_hi R6_hi R7_hi + R8_hi R9_hi R10_hi R11_hi R12_hi R13_hi R14_hi R15_hi ]; + +attach variables [ reg_Indexed16_0_4 + src_Indexed16_8_4 + dest_Indexed16_0_4 ] [ None SP _ _ R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 ]; + +attach variables [ reg_InDirect16_0_4 + src_InDirect16_8_4 ] [ PC SP _ _ R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 ]; + +@if REG_SIZE == "4" +attach variables [reg_Direct16_0_4W reg_Direct16_8_4W] [PC_16 SP_16 SR_16 _ R4_16 R5_16 R6_16 R7_16 R8_16 R9_16 R10_16 R11_16 R12_16 R13_16 R14_16 R15_16]; +@else +attach variables [reg_Direct16_0_4W reg_Direct16_8_4W] [PC SP SR _ R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15]; +@endif + +SRC16_8_4: src_Direct16_8_4 is src_Direct16_8_4 & reg_Direct16_8_4W {export reg_Direct16_8_4W;} +DST16_0_4: dest_Direct16_0_4 is dest_Direct16_0_4 & reg_Direct16_0_4W {export reg_Direct16_0_4W;} +SRC8_8_4: src_Direct16_8_4 is src_Direct16_8_4 & src_Direct_lo {export src_Direct_lo;} +DST8_0_4: reg_Direct16_0_4 is reg_Direct16_0_4 & dest_Direct_lo {export dest_Direct_lo;} + +define pcodeop bcd_add; # Binary coded decimal (BCD) addition +#################################### +# Status Register (SR) Map +#################################### +# b15-b9: Reserved +# b8: V (overflow bit) +# b7: SCG1 (System Clock generator 1) +# b6: SCG0 (System Clock generator 0) +# b5: OSCOFF (Oscillator Off) +# b4: CPUOFF (CPU off) +# b3: GIE (General Interrupt Enable) +# b2: N (Negative Bit) (Word = bit 15, Byte = bit 7)(sign bit) +# b1: Z (Zero Bit) +# b0: C (Carry Bit) +#################################### + +@define CARRY "SR[0,1]" +@define ZERO "SR[1,1]" +@define SIGN "SR[2,1]" +@define OVERFLOW "SR[8,1]" +@define GIE "SR[3,1]" + +# +# Sub Constructors +# +#----------------------------------------------- +# B/W: Byte or Word operation +# 0: Word Operation +# 1: Byte Operation +#----------------------------------------------- + +@if REG_SIZE == "4" +AMASK: val is ctx_isHi=1 [ val = 0xFFFF; ] { export *[const]:4 val; } +AMASK: val is ctx_isHi=0 [ val = 0xFFFFF; ] { export *[const]:4 val; } + + +macro computeIndexedAddr(ptr, reg, index) { +@ifdef INDEX_BRANCH + local isHi = (reg & 0xF0000) != 0; + if (isHi) goto ; + ptr = (reg + index) & 0xFFFF; + goto ; + + ptr = (reg + index) & 0xFFFFF; + +@else + local isHi = (reg & 0xF0000) != 0; + local mask = 0xFFFF | (zext(isHi) * 0xF0000); + ptr = (reg + index) & mask; +@endif # INDEX_BRANCH +} +@else +AMASK: val is epsilon [ val = 0xFFFF; ] { export *[const]:2 val; } +macro computeIndexedAddr(ptr, reg, index) { + ptr = (reg + index) & 0xFFFF; +} +@endif + +#----------------------------------------------- +# +# REGISTER (REG) +# +# The REG modes are used for the 1 operand form instructions +# +#----------------------------------------------- +REG_W_AS: DST16_0_4 is DST16_0_4 & as=0x0 & bow=0x0 {export DST16_0_4;} # Word/Register Direct (Rn): +REG_W_AS: indexExtWord16_0_16s^"("^reg_Indexed16_0_4^")" is reg_Indexed16_0_4 & as=0x1 & bow=0x0 & AMASK ; indexExtWord16_0_16s { local tmp:$(REG_SIZE); computeIndexedAddr(tmp, reg_Indexed16_0_4, indexExtWord16_0_16s); export *:2 tmp;} +REG_W_AS: "@"^reg_InDirect16_0_4 is reg_InDirect16_0_4 & as=0x2 & bow=0x0 {export *:2 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn): +REG_W_AS: "@"^reg_InDirect16_0_4^"+" is reg_InDirect16_0_4 & as=0x3 & bow=0x0 {export *:2 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+): +REG_W_AS: labelCalc is reg16_0_4=0x0 & as=0x1 & bow=0x0 & AMASK; indexExtWord16_0_16 [labelCalc = inst_start + 2 + indexExtWord16_0_16; ] {tmp:$(REG_SIZE) = labelCalc & AMASK; export *:2 tmp; } # Symbolic +REG_W_AS: "#"^indexExtWord16_0_16 is reg16_0_4=0x0 & as=0x3 & bow=0x0 ; indexExtWord16_0_16 {export *[const]:2 indexExtWord16_0_16; } # Immediate +REG_W_AS: "&"^indexExtWord16_0_16 is reg16_0_4=0x2 & as=0x1 & bow=0x0 ; indexExtWord16_0_16 {export *:2 indexExtWord16_0_16; } # Absolute +REG_W_AS: "#4" is reg16_0_4=0x2 & as=0x2 & bow=0x0 { export 4:2;} # Constant +REG_W_AS: "#8" is reg16_0_4=0x2 & as=0x3 & bow=0x0 { export 8:2;} # Constant +REG_W_AS: "#0" is reg16_0_4=0x3 & as=0x0 & bow=0x0 { export 0:2;} # Constant +REG_W_AS: "#1" is reg16_0_4=0x3 & as=0x1 & bow=0x0 { export 1:2;} # Constant +REG_W_AS: "#2" is reg16_0_4=0x3 & as=0x2 & bow=0x0 { export 2:2;} # Constant +REG_W_AS: "#-1" is reg16_0_4=0x3 & as=0x3 & bow=0x0 { export 0xffff:2;} # Constant + +REG_W_AS_DEST: DST16_0_4 is DST16_0_4 & as=0x0 & bow=0x0 {export DST16_0_4;} # Word/Register Direct (Rn): +REG_W_AS_DEST: indexExtWord16_0_16s^"("^reg_Indexed16_0_4^")" is reg_Indexed16_0_4 & as=0x1 & bow=0x0 & AMASK ; indexExtWord16_0_16s { local tmp:$(REG_SIZE); computeIndexedAddr(tmp, reg_Indexed16_0_4, indexExtWord16_0_16s); export *:2 tmp;} +REG_W_AS_DEST: "@"^reg_InDirect16_0_4 is reg_InDirect16_0_4 & as=0x2 & bow=0x0 {export *:2 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn): +REG_W_AS_DEST: "@"^reg_InDirect16_0_4^"+" is reg_InDirect16_0_4 & as=0x3 & bow=0x0 {export *:2 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+): +REG_W_AS_DEST: labelCalc is reg16_0_4=0x0 & as=0x1 & bow=0x0 & AMASK ; indexExtWord16_0_16 [labelCalc = inst_start + 2 + indexExtWord16_0_16; ] {tmp:$(REG_SIZE) = labelCalc & AMASK;export *:2 tmp; } # Symbolic +REG_W_AS_DEST: "&"^indexExtWord16_0_16 is reg16_0_4=0x2 & as=0x1 & bow=0x0 ; indexExtWord16_0_16 {export *:2 indexExtWord16_0_16; } # Absolute + +#----------------------------------------------- +REG_B_AS: DST8_0_4 is DST8_0_4 & as=0x0 & bow=0x1 { export DST8_0_4;} # Word/Register Direct (Rn): +REG_B_AS: indexExtWord16_0_16s^"("^reg_Indexed16_0_4^")" is reg_Indexed16_0_4 & as=0x1 & bow=0x1 & AMASK ; indexExtWord16_0_16s { local tmp:$(REG_SIZE); computeIndexedAddr(tmp, reg_Indexed16_0_4, indexExtWord16_0_16s); export *:1 tmp;} +REG_B_AS: "@"^reg_InDirect16_0_4 is reg_InDirect16_0_4 & as=0x2 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn): +REG_B_AS: "@"^reg_InDirect16_0_4^"+" is reg_InDirect16_0_4 & as=0x3 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+): +REG_B_AS: labelCalc is reg16_0_4=0x0 & as=0x1 & bow=0x1 & AMASK ; indexExtWord16_0_16 [labelCalc = inst_start + 2 + indexExtWord16_0_16; ] {tmp:$(REG_SIZE) = labelCalc & AMASK;export *:1 tmp; } # Symbolic +REG_B_AS: "#"^indexExtWord16_0_16 is reg16_0_4=0x0 & as=0x3 & bow=0x1 ; indexExtWord16_0_16 { export *[const]:1 indexExtWord16_0_16; } # Immediate +REG_B_AS: "&"^indexExtWord16_0_16 is reg16_0_4=0x2 & as=0x1 & bow=0x1 ; indexExtWord16_0_16 {export *:1 indexExtWord16_0_16; } # Absolute +REG_B_AS: "#4" is reg16_0_4=0x2 & as=0x2 & bow=0x1 { export 4:1;} # Constant +REG_B_AS: "#8" is reg16_0_4=0x2 & as=0x3 & bow=0x1 { export 8:1;} # Constant +REG_B_AS: "#0" is reg16_0_4=0x3 & as=0x0 & bow=0x1 { export 0:1;} # Constant +REG_B_AS: "#1" is reg16_0_4=0x3 & as=0x1 & bow=0x1 { export 1:1;} # Constant +REG_B_AS: "#2" is reg16_0_4=0x3 & as=0x2 & bow=0x1 { export 2:1;} # Constant +REG_B_AS: "#-1" is reg16_0_4=0x3 & as=0x3 & bow=0x1 { export 0xff:1;} # Constant + +REG_B_AS_DEST: DST8_0_4 is DST8_0_4 & as=0x0 & bow=0x1 { export DST8_0_4;} # Word/Register Direct (Rn): +REG_B_AS_DEST: indexExtWord16_0_16s^"("^reg_Indexed16_0_4^")" is reg_Indexed16_0_4 & as=0x1 & bow=0x1 & AMASK ; indexExtWord16_0_16s { local tmp:$(REG_SIZE); computeIndexedAddr(tmp, reg_Indexed16_0_4, indexExtWord16_0_16s); export *:1 tmp;} +REG_B_AS_DEST: "@"^reg_InDirect16_0_4 is reg_InDirect16_0_4 & as=0x2 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn): +REG_B_AS_DEST: "@"^reg_InDirect16_0_4^"+" is reg_InDirect16_0_4 & as=0x3 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+): +REG_B_AS_DEST: labelCalc is reg16_0_4=0x0 & as=0x1 & bow=0x1 & AMASK ; indexExtWord16_0_16 [labelCalc = inst_start + 2 + indexExtWord16_0_16; ] {tmp:$(REG_SIZE) = labelCalc & AMASK;export *:1 tmp; } # Symbolic +REG_B_AS_DEST: "&"^indexExtWord16_0_16 is reg16_0_4=0x2 & as=0x1 & bow=0x1 ; indexExtWord16_0_16 {export *:1 indexExtWord16_0_16; } # Absolute + +#----------------------------------------------- +# +# SOURCE (SRC) +# +#----------------------------------------------- +SRC_W_AS: SRC16_8_4 is SRC16_8_4 & as=0x0 & bow=0x0 {export SRC16_8_4;} # Word/Register Direct (Rn): +SRC_W_AS: indexExtWord16_0_16s^"("^src_Indexed16_8_4^")" is src_Indexed16_8_4 & as=0x1 & bow=0x0 & AMASK ; indexExtWord16_0_16s { local tmp:$(REG_SIZE); computeIndexedAddr(tmp, src_Indexed16_8_4, indexExtWord16_0_16s); export *:2 tmp;} +SRC_W_AS: "@"^src_InDirect16_8_4 is src_InDirect16_8_4 & as=0x2 & bow=0x0 {export *:2 src_InDirect16_8_4;} # Word/Register Indirect (@Rn): +SRC_W_AS: "@"^src_InDirect16_8_4^"+" is src_InDirect16_8_4 & as=0x3 & bow=0x0 {export *:2 src_InDirect16_8_4;} # Word/Register Indirect Autoincrement (@Rn+): +SRC_W_AS: labelCalc is src16_8_4=0x0 & as=0x1 & bow=0x0 & AMASK ; indexExtWord16_0_16 [labelCalc = inst_start + 2 + indexExtWord16_0_16; ] {tmp:$(REG_SIZE) = labelCalc & AMASK;export *:2 tmp; } # Symbolic +SRC_W_AS: "#"^indexExtWord16_0_16 is src16_8_4=0x0 & as=0x3 & bow=0x0 ; indexExtWord16_0_16 {export *[const]:2 indexExtWord16_0_16; } # Immediate +SRC_W_AS: "&"^indexExtWord16_0_16 is src16_8_4=0x2 & as=0x1 & bow=0x0 ; indexExtWord16_0_16 {export *:2 indexExtWord16_0_16; } # Absolute +SRC_W_AS: "#4" is src16_8_4=0x2 & as=0x2 & bow=0x0 { export 4:2; } # Constant +SRC_W_AS: "#8" is src16_8_4=0x2 & as=0x3 & bow=0x0 { export 8:2; } # Constant +SRC_W_AS: "#0" is src16_8_4=0x3 & as=0x0 & bow=0x0 { export 0:2; } # Constant +SRC_W_AS: "#1" is src16_8_4=0x3 & as=0x1 & bow=0x0 { export 1:2; } # Constant +SRC_W_AS: "#2" is src16_8_4=0x3 & as=0x2 & bow=0x0 { export 2:2; } # Constant +SRC_W_AS: "#-1" is src16_8_4=0x3 & as=0x3 & bow=0x0 { export 0xffff:2; } # Constant +#----------------------------------------------- +SRC_B_AS: SRC8_8_4 is SRC8_8_4 & as=0x0 & bow=0x1 { export SRC8_8_4;} # Word/Register Direct (Rn): +SRC_B_AS: indexExtWord16_0_16s^"("^src_Indexed16_8_4^")" is src_Indexed16_8_4 & as=0x1 & bow=0x1 & AMASK ; indexExtWord16_0_16s { local tmp:$(REG_SIZE); computeIndexedAddr(tmp, src_Indexed16_8_4, indexExtWord16_0_16s); export *:1 tmp;} +SRC_B_AS: "@"^src_InDirect16_8_4 is src_InDirect16_8_4 & as=0x2 & bow=0x1 {export *:1 src_InDirect16_8_4;} # Word/Register Indirect (@Rn): +SRC_B_AS: "@"^src_InDirect16_8_4^"+" is src_InDirect16_8_4 & as=0x3 & bow=0x1 {export *:1 src_InDirect16_8_4;} # Word/Register Indirect Autoincrement (@Rn+): +SRC_B_AS: labelCalc is src16_8_4=0x0 & as=0x1 & bow=0x1 & AMASK ; indexExtWord16_0_16 [labelCalc = inst_start + 2 + indexExtWord16_0_16; ] {tmp:$(REG_SIZE) = labelCalc & AMASK;export *:1 tmp; } # Symbolic +SRC_B_AS: "#"^indexExtWord16_0_16 is src16_8_4=0x0 & as=0x3 & bow=0x1 ; indexExtWord16_0_16 {export *[const]:1 indexExtWord16_0_16;} # Immediate +SRC_B_AS: "&"^indexExtWord16_0_16 is src16_8_4=0x2 & as=0x1 & bow=0x1 ; indexExtWord16_0_16 {export *:1 indexExtWord16_0_16; } # Absolute +SRC_B_AS: "#4" is src16_8_4=0x2 & as=0x2 & bow=0x1 { export 4:1; } # Constant +SRC_B_AS: "#8" is src16_8_4=0x2 & as=0x3 & bow=0x1 { export 8:1; } # Constant +SRC_B_AS: "#0" is src16_8_4=0x3 & as=0x0 & bow=0x1 { export 0:1; } # Constant +SRC_B_AS: "#1" is src16_8_4=0x3 & as=0x1 & bow=0x1 { export 1:1; } # Constant +SRC_B_AS: "#2" is src16_8_4=0x3 & as=0x2 & bow=0x1 { export 2:1; } # Constant +SRC_B_AS: "#-1" is src16_8_4=0x3 & as=0x3 & bow=0x1 { export 0xff:1; } # Constant + +#----------------------------------------------- +# +# DESTINATION (DEST) +# +#----------------------------------------------- +DEST_W_AD: DST16_0_4 is DST16_0_4 & ad=0x0 & bow=0x0 + {export DST16_0_4;} # Word/Register Direct (Rn): + +DEST_W_AD: indexExtWord16_0_16s^"("^dest_Indexed16_0_4^")" is dest_Indexed16_0_4 & ad=0x1 & bow=0x0 & AMASK ; indexExtWord16_0_16s + {local tmp:$(REG_SIZE); computeIndexedAddr(tmp, dest_Indexed16_0_4, indexExtWord16_0_16s); export *:2 tmp;} +#---Depends on SRC ---# +DEST_W_AD: indexExt2Word16_0_16s^"("^dest_Indexed16_0_4^")" is dest_Indexed16_0_4 & ad=0x1 & bow=0x0 & AMASK & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; indexExt2Word16_0_16s + {local tmp:$(REG_SIZE); computeIndexedAddr(tmp, dest_Indexed16_0_4, indexExt2Word16_0_16s); export *:2 tmp;} +DEST_W_AD: indexExt2Word16_0_16s^"("^dest_Indexed16_0_4^")" is dest_Indexed16_0_4 & ad=0x1 & bow=0x0 & AMASK & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; indexExt2Word16_0_16s + {local tmp:$(REG_SIZE); computeIndexedAddr(tmp, dest_Indexed16_0_4, indexExt2Word16_0_16s); export *:2 tmp;} +#---End of Depend ----# + +DEST_W_AD: labelCalc is dest=0x0 & ad=0x1 & bow=0x0 & AMASK ; indexExtWord16_0_16s [labelCalc = inst_start + 2 + indexExtWord16_0_16s; ] + {tmp:$(REG_SIZE) = labelCalc & AMASK;export *:2 tmp; } # Symbolic +#---Depends on SRC ---# +DEST_W_AD: labelCalc is dest=0x0 & ad=0x1 & bow=0x0 & AMASK & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; indexExt2Word16_0_16s [labelCalc = inst_start + 4 + indexExt2Word16_0_16s; ] + {tmp:$(REG_SIZE) = labelCalc & AMASK;export *:2 tmp; } # Symbolic +DEST_W_AD: labelCalc is dest=0x0 & ad=0x1 & bow=0x0 & AMASK & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; indexExt2Word16_0_16s [labelCalc = inst_start + 4 + indexExt2Word16_0_16s; ] + {tmp:$(REG_SIZE) = labelCalc & AMASK;export *:2 tmp; } # Symbolic +#---End of Depend ----# + +DEST_W_AD: "&"^indexExtWord16_0_16 is dest=0x2 & ad=0x1 & bow=0x0 ; indexExtWord16_0_16 + {export *:2 indexExtWord16_0_16; } # Absolute +#---Depends on SRC ---# +DEST_W_AD: "&"^indexExt2Word16_0_16 is dest=0x2 & ad=0x1 & bow=0x0 & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; indexExt2Word16_0_16 + {export *:2 indexExt2Word16_0_16; } # Absolute +DEST_W_AD: "&"^indexExt2Word16_0_16 is dest=0x2 & ad=0x1 & bow=0x0 & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; indexExt2Word16_0_16 + {export *:2 indexExt2Word16_0_16; } # Absolute +#---End of Depend ----# + +#----------------------------------------------- +DEST_B_AD: DST8_0_4 is DST8_0_4 & dest_Direct_lo & ad=0x0 & bow=0x1 + { export DST8_0_4; } # Word/Register Direct (Rn): + +DEST_B_AD: indexExtWord16_0_16s^"("^dest_Indexed16_0_4^")" is dest_Indexed16_0_4 & ad=0x1 & bow=0x1 & AMASK ; indexExtWord16_0_16s + {local tmp:$(REG_SIZE); computeIndexedAddr(tmp, dest_Indexed16_0_4, indexExtWord16_0_16s); export *:1 tmp;} +#---Depends on SRC ---# +DEST_B_AD: indexExt2Word16_0_16s^"("^dest_Indexed16_0_4^")" is dest_Indexed16_0_4 & ad=0x1 & bow=0x1 & AMASK & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; indexExt2Word16_0_16s + {local tmp:$(REG_SIZE); computeIndexedAddr(tmp, dest_Indexed16_0_4, indexExt2Word16_0_16s); export *:1 tmp;} +DEST_B_AD: indexExt2Word16_0_16s^"("^dest_Indexed16_0_4^")" is dest_Indexed16_0_4 & ad=0x1 & bow=0x1 & AMASK & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; indexExt2Word16_0_16s + {local tmp:$(REG_SIZE); computeIndexedAddr(tmp, dest_Indexed16_0_4, indexExt2Word16_0_16s); export *:1 tmp;} +#---End of Depend ----# + +DEST_B_AD: labelCalc is dest=0x0 & ad=0x1 & bow=0x1 & AMASK ; indexExtWord16_0_16s [labelCalc = inst_start + 2 + indexExtWord16_0_16s; ] + {tmp:$(REG_SIZE) = labelCalc & AMASK; export *:1 tmp; } # Symbolic +#---Depends on SRC ---# +DEST_B_AD: labelCalc is dest=0x0 & ad=0x1 & bow=0x1 & AMASK & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; indexExt2Word16_0_16s [labelCalc = inst_start + 4 + indexExt2Word16_0_16s; ] + {tmp:$(REG_SIZE) = labelCalc & AMASK;export *:1 tmp; } # Symbolic +DEST_B_AD: labelCalc is dest=0x0 & ad=0x1 & bow=0x1 & AMASK & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; indexExt2Word16_0_16s [labelCalc = inst_start + 4 + indexExt2Word16_0_16s; ] + {tmp:$(REG_SIZE) = labelCalc & AMASK;export *:1 tmp; } # Symbolic +#---End of Depend ----# + +DEST_B_AD: "&"^indexExtWord16_0_16 is dest=0x2 & ad=0x1 & bow=0x1 ; indexExtWord16_0_16 + {export *:1 indexExtWord16_0_16; } # Absolute +#---Depends on SRC ---# +DEST_B_AD: "&"^indexExt2Word16_0_16 is dest=0x2 & ad=0x1 & bow=0x1 & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; indexExt2Word16_0_16 + {export *:1 indexExt2Word16_0_16; } # Absolute +DEST_B_AD: "&"^indexExt2Word16_0_16 is dest=0x2 & ad=0x1 & bow=0x1 & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; indexExt2Word16_0_16 + {export *:1 indexExt2Word16_0_16; } # Absolute +#---End of Depend ----# + + +# For handling constant operands in CALL and BR instructions. +DirectAddr: "#"^indexExtWord16_0_16 is indexExtWord16_0_16 {export *:$(REG_SIZE) indexExtWord16_0_16; } + +tbl_bzero: is ad=0 & reg_Direct16_0_4 & dest_Direct_lo {ztmp:1 = dest_Direct_lo; reg_Direct16_0_4 = 0; dest_Direct_lo = ztmp; } +tbl_bzero: is epsilon {} + +@if REG_SIZE == "4" +tbl_wzero: is ad=0 & reg_Direct16_0_4 & reg_Direct16_0_4W {ztmp:2 = reg_Direct16_0_4W; reg_Direct16_0_4 = 0; reg_Direct16_0_4W = ztmp; } +@endif +tbl_wzero: is epsilon {} + +# For 1 operand instructions +tbl_bzero_reg: is as=0 & reg_Direct16_0_4 & dest_Direct_lo {ztmp:1 = dest_Direct_lo; reg_Direct16_0_4 = 0; dest_Direct_lo = ztmp; } +tbl_bzero_reg: is epsilon {} + +@if REG_SIZE == "4" +tbl_wzero_reg: is as=0 & reg_Direct16_0_4 & reg_Direct16_0_4W {ztmp:2 = reg_Direct16_0_4W; reg_Direct16_0_4 = 0; reg_Direct16_0_4W = ztmp; } +@endif +tbl_wzero_reg: is epsilon {} + +# +# Post Processing +# does correct increment of source register +# Also catches when PC is being stored to and does the correct branching +# +postRegIncrement: is as=0x3 & src16_8_4 & bow=0x0 & reg_InDirect16_0_4 { reg_InDirect16_0_4 = reg_InDirect16_0_4 + 2; } +postRegIncrement: is as=0x3 & src16_8_4 & bow=0x1 & reg_InDirect16_0_4 { reg_InDirect16_0_4 = reg_InDirect16_0_4 + 1; } +postRegIncrement: is as=0x3 & src16_8_4=1 & bow=0x1 & reg_InDirect16_0_4 { reg_InDirect16_0_4 = reg_InDirect16_0_4 + 2; } +postRegIncrement: is as=0x3 & src16_8_4=0 & bow=0x0 & reg_InDirect16_0_4 { } # PC is incremented by 2, but that is just to skip over the value +postRegIncrement: is as=0x3 & src16_8_4=0 & bow=0x1 & reg_InDirect16_0_4 { } # PC is incremented by 2, but that is just to skip over the value +postRegIncrement: is as=0x3 & src16_8_4=2 & bow=0x1 { } +postRegIncrement: is as=0x3 & src16_8_4=3 & bow=0x1 { } +postRegIncrement: is as=0x3 & src16_8_4=2 & bow=0x0 { } +postRegIncrement: is as=0x3 & src16_8_4=3 & bow=0x0 { } +postRegIncrement: is as & bow { } + +# R2 and R3 are constant generators - post-increment not supported +postIncrement: is as=0x3 & ctx_haveext=0 & src16_8_4=2 & bow=0x0 & ctx_al=0 +{ } +postIncrement: is as=0x3 & ctx_haveext=0 & src16_8_4=2 & bow=0x1 & ctx_al=0 +{ } +postIncrement: is as=0x3 & ctx_haveext=0 & src16_8_4=3 & bow=0x0 & ctx_al=0 +{ } +postIncrement: is as=0x3 & ctx_haveext=0 & src16_8_4=3 & bow=0x1 & ctx_al=0 +{ } +postIncrement: is as=0x3 & src16_8_4=2 & bow=0x0 +{ } +postIncrement: is as=0x3 & src16_8_4=2 & bow=0x1 +{ } +postIncrement: is as=0x3 & src16_8_4=3 & bow=0x0 +{ } +postIncrement: is as=0x3 & src16_8_4=3 & bow=0x1 +{ } + +postIncrement: is as=0x3 & src16_8_4=0 & bow=0x1 & src_InDirect16_8_4 +{ } # PC is incremented by 2, but that is just to skip over the value +postIncrement: is as=0x3 & src16_8_4=0 & bow=0x0 & src_InDirect16_8_4 +{ } # PC is incremented by 2, but that is just to skip over the value + +postIncrement: is as=0x3 & src16_8_4 & bow=0x0 & src_InDirect16_8_4 +{ src_InDirect16_8_4 = src_InDirect16_8_4 + 2; } + +postIncrement: is as=0x3 & src16_8_4 & bow=0x1 & ctx_al=0 & src_InDirect16_8_4 +{ src_InDirect16_8_4 = src_InDirect16_8_4 + 4; } +postIncrement: is as=0x3 & src16_8_4=1 & bow=0x1 & ctx_al=0 & src_InDirect16_8_4 +{ src_InDirect16_8_4 = src_InDirect16_8_4 + 4; } + +postIncrement: is as=0x3 & src16_8_4 & bow=0x1 & ctx_al=1 & src_InDirect16_8_4 +{ src_InDirect16_8_4 = src_InDirect16_8_4 + 1; } +postIncrement: is as=0x3 & src16_8_4=1 & bow=0x1 & ctx_al=1 & src_InDirect16_8_4 +{ src_InDirect16_8_4 = src_InDirect16_8_4 + 2; } + +postIncrement: is as=0x3 & ctx_haveext=0 & src16_8_4 & bow=0x1 & ctx_al=0 & src_InDirect16_8_4 +{ src_InDirect16_8_4 = src_InDirect16_8_4 + 1; } +postIncrement: is as=0x3 & ctx_haveext=0 & src16_8_4=1 & bow=0x1 & ctx_al=0 & src_InDirect16_8_4 +{ src_InDirect16_8_4 = src_InDirect16_8_4 + 2; } + +postIncrement: is as & src16_8_4 & bow +{ } + + +# +# Zero Extends if the store is byte oriented, and a register is being stored to +zeroExtend: is dest_Direct_lo & dest_Direct16_0_4 +{ dest_Direct16_0_4 = zext(dest_Direct_lo); } + +# +# Post processing when destination is the PC +# +postIncrementStore: is postIncrement & ad=0x0 & src_InDirect16_8_4 & as=0x3 & src16_8_4=1 & dest_Direct16_0_4=0x0 & bow=0x1 & ctx_al=1 & zeroExtend +{ build zeroExtend; build postIncrement; return [PC]; } +postIncrementStore: is postIncrement & ad=0x0 & dest_Direct16_0_4=0x0 & bow=0x1 & ctx_al=1 & zeroExtend +{ build zeroExtend; build postIncrement; goto [PC];} +postIncrementStore: is postIncrement & ad=0x0 & bow=0x1 & ctx_al=1 & zeroExtend +{ build zeroExtend; build postIncrement; } + +postIncrementStore: is postIncrement & ctx_haveext=0 & ad=0x0 & src_InDirect16_8_4 & as=0x3 & src16_8_4=1 & dest_Direct16_0_4=0x0 & bow=0x1 & zeroExtend +{ build zeroExtend; build postIncrement; return [PC]; } +postIncrementStore: is postIncrement & ctx_haveext=0 & ad=0x0 & dest_Direct16_0_4=0x0 & bow=0x1 & zeroExtend +{ build zeroExtend; build postIncrement; goto [PC];} +postIncrementStore: is postIncrement & ctx_haveext=0 & ad=0x0 & bow=0x1 & zeroExtend +{ build zeroExtend; build postIncrement; } + + +postIncrementStore: is postIncrement & ad=0x0 & src_InDirect16_8_4 & as=0x3 & src16_8_4=1 & dest_Direct16_0_4=0x0 +{ build postIncrement; return [PC]; } +postIncrementStore: is postIncrement & ad=0x0 & dest_Direct16_0_4=0x0 +{ build postIncrement; goto [PC];} +postIncrementStore: is postIncrement & ad & bow +{ build postIncrement; } + +#----------------------------------------------- +# +# JUMP CONDITION (JCND) +# +#----------------------------------------------- + +JCND: "NE" is condition=0x0 {cndTst:1 = !$(ZERO); export cndTst;} # Not Equal/Zero (cleared) +JCND: "EQ" is condition=0x1 {cndTst:1 = $(ZERO); export cndTst;} # Equal/Zero (set) +JCND: "NC" is condition=0x2 {cndTst:1 = !$(CARRY); export cndTst;} # No Carry/Lower (cleared) +JCND: "C" is condition=0x3 {cndTst:1 = $(CARRY); export cndTst;} # Carry/Higher or same (set) +JCND: "N" is condition=0x4 {cndTst:1 = $(SIGN); export cndTst;} # Negative (set) +JCND: "GE" is condition=0x5 {cndTst:1 = ($(SIGN) == $(OVERFLOW)); export cndTst;} # Greater or equal (>=) +JCND: "L" is condition=0x6 {cndTst:1 = ($(SIGN) != $(OVERFLOW)); export cndTst;} # Less (<) +JCND: "MP" is condition=0x7 {cndTst:1 = 0x1; export cndTst;} # Unconditional + +#----------------------------------------------- +# +# 10 BIT OFFSET +# +#----------------------------------------------- + +OFFSET_10BIT: offset10 is off16 [offset10 = inst_start + 2 + off16 * 2; ] + { export *:$(REG_SIZE) offset10;} + + +################################################################################### +# +# Single-operand arithmetic +# +# ------------------------------------------------------------------------------ +# | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +# ------------------------------------------------------------------------------ +# | 0 | 0 | 0 | 1 | 0 | 0 | opcode | B/W | As | register | +# ------------------------------------------------------------------------------ +################################################################################### + +################################################################################### +# +# RRC: Rotate right through carry +# ------------------------------------------------------------------------------ +# | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +# ------------------------------------------------------------------------------ +# | 0 | 0 | 0 | 1 | 0 | 0 | 000 | B/W | As | register | +:RRC^".W" REG_W_AS_DEST is ctx_haveext=0 & (op16_12_4=0x1 & op16_8_4=0x0 & op16_7_1=0x0 & bow=0x0 & tbl_wzero_reg & postRegIncrement) ... & REG_W_AS_DEST { + # Operation Flags... + $(OVERFLOW) = ((REG_W_AS_DEST != 0x0) && ($(CARRY) == 0x1)); # V Flag + # Operation... + tmp:1 = $(CARRY); + $(CARRY) = REG_W_AS_DEST[0,1]; + REG_W_AS_DEST = ((zext(tmp) << 0xF) | (REG_W_AS_DEST >> 0x1)); + build tbl_wzero_reg; + # Result Flags... + $(SIGN) = (REG_W_AS_DEST s< 0x0); # S Flag + $(ZERO) = (REG_W_AS_DEST == 0x0); # Z Flag + build postRegIncrement; +} + + +:RRC^".B" REG_B_AS_DEST is ctx_haveext=0 & (op16_12_4=0x1 & op16_8_4=0x0 & op16_7_1=0x0 & bow=0x1 & tbl_bzero_reg & postRegIncrement) ... & REG_B_AS_DEST { + # Operation Flags... + $(OVERFLOW) = ((REG_B_AS_DEST != 0x0) && ($(CARRY) == 0x1)); # V Flag + # Operation... + tmp:1 = $(CARRY); + $(CARRY) = (REG_B_AS_DEST & 0x1); + REG_B_AS_DEST = ((tmp << 0x7) | (REG_B_AS_DEST >> 0x1)); + build tbl_bzero_reg; + # Result Flags... + $(SIGN) = (REG_B_AS_DEST s< 0x0); # S Flag + $(ZERO) = (REG_B_AS_DEST == 0x0); # Z Flag + build postRegIncrement; +} + + +################################################################################### +# +# SWPB: Swap bytes +# ------------------------------------------------------------------------------ +# | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +# ------------------------------------------------------------------------------ +# | 0 | 0 | 0 | 1 | 0 | 0 | 001 | 0 | As | register | +:SWPB REG_W_AS_DEST is ctx_haveext=0 & (op16_12_4=0x1 & op16_8_4=0x0 & op16_7_1=0x1 & bow=0x0 & tbl_wzero_reg & postRegIncrement) ... & REG_W_AS_DEST { + lowByte:1 = REG_W_AS_DEST[0,8]; + highByte:1 = REG_W_AS_DEST[8,8]; + REG_W_AS_DEST = (((zext(lowByte)) << 0x8) | zext(highByte)); + build tbl_wzero_reg; + #Status bits are not affected + build postRegIncrement; +} + + + +################################################################################### +# +# RRA: Rotate right arithmetic +# ------------------------------------------------------------------------------ +# | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +# ------------------------------------------------------------------------------ +# | 0 | 0 | 0 | 1 | 0 | 0 | 010 | B/W | As | register | +:RRA^".W" REG_W_AS_DEST is ctx_haveext=0 & (op16_12_4=0x1 & op16_8_4=0x1 & op16_7_1=0x0 & bow=0x0 & tbl_wzero_reg & postRegIncrement) ... & REG_W_AS_DEST { + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag (reset) + # Operation... + $(CARRY) = REG_W_AS_DEST[0,1]; + MSB:2 = REG_W_AS_DEST >> 0xF; + REG_W_AS_DEST = ((MSB << 0xF) | (REG_W_AS_DEST >> 0x1)); + build tbl_wzero_reg; + # Result Flags... + $(SIGN) = (REG_W_AS_DEST s< 0x0); # S Flag + $(ZERO) = (REG_W_AS_DEST == 0x0); # Z Flag + build postRegIncrement; +} + + +:RRA^".B" REG_B_AS_DEST is ctx_haveext=0 & (op16_12_4=0x1 & op16_8_4=0x1 & op16_7_1=0x0 & bow=0x1 & tbl_bzero_reg & postRegIncrement) ... & REG_B_AS_DEST { + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag (reset) + # Operation... + $(CARRY) = (REG_B_AS_DEST & 0x1); + MSB:1 = REG_B_AS_DEST >> 0x7; + REG_B_AS_DEST = ((MSB << 0x7) | (REG_B_AS_DEST >> 0x1)); + build tbl_bzero_reg; + # Result Flags... + $(SIGN) = (REG_B_AS_DEST s< 0x0); # S Flag + $(ZERO) = (REG_B_AS_DEST == 0x0); # Z Flag + build postRegIncrement; +} + + +################################################################################### +# +# SXT: Sign extend byte to word +# ------------------------------------------------------------------------------ +# | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +# ------------------------------------------------------------------------------ +# | 0 | 0 | 0 | 1 | 0 | 0 | 011 | 0 | As | register | +:SXT REG_W_AS_DEST is ctx_haveext=0 & (op16_12_4=0x1 & op16_8_4=0x1 & op16_7_1=0x1 & bow=0x0 & tbl_wzero_reg & postRegIncrement) ... & REG_W_AS_DEST { + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag + # Operation... + byteVal:1 = REG_W_AS_DEST[0,8]; + REG_W_AS_DEST = sext(byteVal); + build tbl_wzero_reg; + # Result Flags... + $(SIGN) = (REG_W_AS_DEST s< 0x0); # S Flag + $(ZERO) = (REG_W_AS_DEST == 0x0); # Z Flag + $(CARRY) = (REG_W_AS_DEST != 0x0); # C Flag + build postRegIncrement; +} + + +################################################################################### +# +# PUSH: Push value onto stack +# ------------------------------------------------------------------------------ +# | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +# ------------------------------------------------------------------------------ +# | 0 | 0 | 0 | 1 | 0 | 0 | 100 | B/W | As | register | +:PUSH^".W" REG_W_AS is ctx_haveext=0 & (op16_12_4=0x1 & op16_8_4=0x2 & op16_7_1=0x0 & bow=0x0 & postRegIncrement) ... & REG_W_AS { + SP = SP - 0x2; + *:2 SP = REG_W_AS; + #Status bits are not affected + build postRegIncrement; +} + +:PUSH^".B" REG_B_AS is ctx_haveext=0 & (op16_12_4=0x1 & op16_8_4=0x2 & op16_7_1=0x0 & bow=0x1 & postRegIncrement) ... & REG_B_AS { + SP = SP - 0x2; + *:1 SP = REG_B_AS; + #Status bits are not affected + build postRegIncrement; +} + + +################################################################################### +# +# CALL: Subroutine call; push PC and move source to PC +# ------------------------------------------------------------------------------ +# | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +# ------------------------------------------------------------------------------ +# | 0 | 0 | 0 | 1 | 0 | 0 | 101 | 0 | As | register | +:CALL REG_W_AS is ctx_haveext=0 & (op16_12_4=0x1 & op16_8_4=0x2 & op16_7_1=0x1 & bow=0x0 & postRegIncrement) ... & REG_W_AS { + SP = SP - 0x2; + *:2 SP = inst_next; + PC = zext(REG_W_AS); + build postRegIncrement; + call [PC]; + #Status bits are not affected +} + +:CALL DirectAddr is ctx_haveext=0 & (op16_12_4=0x1 & op16_8_4=0x2 & op16_7_1=0x1 & reg16_0_4=0x0 & as=0x3 & bow=0x0 & postRegIncrement); DirectAddr { + SP = SP - 0x2; + *:2 SP = inst_next; + PC = &DirectAddr; + build postRegIncrement; + call DirectAddr; + #Status bits are not affected +} + + + +################################################################################### +# +# RETI: Return from interrupt; pop SR then pop PC +# ------------------------------------------------------------------------------ +# | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +# ------------------------------------------------------------------------------ +# | 0 | 0 | 0 | 1 | 0 | 0 | 110 | 0 | 00 | 0000 | +:RETI is ctx_haveext=0 & op16_12_4=0x1 & op16_8_4=0x3 & op16_7_1=0x0 & as=0x0 & bow=0x0 & op16_0_4=0x0 & op16_4_4=0x0 { +@if REG_SIZE == "2" + SR = *:2 SP; + SP = SP + 0x2; + PC = *:2 SP; +@else + tmp:$(REG_SIZE) = zext(*:2 SP); + SR = zext(tmp[0,12]); + SP = SP + 0x2; + PC = zext(*:2 SP) | ((tmp & 0xF000) << 4); +@endif + SP = SP + 0x2; + return [PC]; + #Status bits are restored from system stack +} + +################################################################################### +# +# Conditional jump; PC = PC + 2*offset +# +# ------------------------------------------------------------------------------ +# | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +# ------------------------------------------------------------------------------ +# | 0 | 0 | 1 | condition | 10-bit signed offset | +# ------------------------------------------------------------------------------ +################################################################################### + +################################################################################### +# +# J^JumpCondition 10-bit_signed_offset +# ------------------------------------------------------------------------------ +# | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +# ------------------------------------------------------------------------------ +# | 0 | 0 | 1 | condition | 10-bit signed offset | +:J^JCND OFFSET_10BIT is ctx_haveext=0 & op16_13_3=0x1 & JCND & OFFSET_10BIT { + if (JCND) goto OFFSET_10BIT; + #Status bits are not affected +} + +:JMP OFFSET_10BIT is ctx_haveext=0 & op16_13_3=0x1 & condition=0x7 & OFFSET_10BIT { + goto OFFSET_10BIT; + #Status bits are not affected +} + +################################################################################### +# +# Two-operand arithmetic +# +# ------------------------------------------------------------------------------ +# | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +# ------------------------------------------------------------------------------ +# | opcode | source | Ad | B/W | As | destination | +# ------------------------------------------------------------------------------ +################################################################################### + +################################################################################### +# +# MOV: Move source to destination +# ------------------------------------------------------------------------------ +# | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +# ------------------------------------------------------------------------------ +# | 0 1 0 0 | source | Ad | B/W | As | destination | +#----------------------- +# Emulated instructions +#----------------------- +# Branch +:BR SRC_W_AS is ctx_haveext=0 & (op16_12_4=0x4 & bow=0x0 & ad=0x0 & dest_Direct16_0_4=0x0) ... & SRC_W_AS ... { + PC = zext(SRC_W_AS); + goto [PC]; + #Status bits are not affected +} + +# Branch to an immediate value +:BR DirectAddr is ctx_haveext=0 & (op16_12_4=0x4 & bow=0x0 & ad=0x0 & dest_Direct16_0_4=0x0 & src_Direct16_8_4=0x0 & as=0x3); DirectAddr { + PC = &DirectAddr; + goto DirectAddr; + #Status bits are not affected +} + +# No operation +:NOP is ctx_haveext=0 & op16_12_4=0x4 & bow=0x0 & ad=0x0 & as=0x0 & dest_Direct16_0_4=0x3 & src_Direct16_8_4=0x3 & postIncrement { + #Status bits are not affected + build postIncrement; +} + +# Pop word from stack +:POP^".W" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x4 & bow=0x0 & (ad=0x1 | dest_Direct16_0_4) & as=0x3 & src_Direct16_8_4=0x1 & tbl_wzero) ... & DEST_W_AD ... { + DEST_W_AD = *:2 SP; + build tbl_wzero; + SP = SP + 0x2; + #Status bits are not affected +} + +# Pop byte from stack +:POP^".B" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x4 & bow=0x1 & (ad=0x1 | dest_Direct16_0_4) & as=0x3 & src_Direct16_8_4=0x1 & tbl_bzero) ... & DEST_B_AD ... { + DEST_B_AD = *:1 SP; + build tbl_bzero; + SP = SP + 0x2; + #Status bits are not affected +} + +# Return from subroutine +:RET is ctx_haveext=0 & op16_12_4=0x4 & bow=0x0 & ad=0x0 & as=0x3 & dest_Direct16_0_4=0x0 & src_Direct16_8_4=0x1 { + PC = zext(*:2 SP); + SP = SP + 0x2; + return [PC]; + #Status bits are not affected +} + +#------------------ +# SRC Word +#------------------ +:MOV^".W" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x4 & bow=0x0 & tbl_wzero & postIncrementStore) ... & SRC_W_AS ... & DEST_W_AD ... { + DEST_W_AD = SRC_W_AS; + build tbl_wzero; + #Status bits are not affected + build postIncrementStore; +} + + +#------------------ +# SRC Byte +#------------------ +:MOV^".B" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x4 & bow=0x1 & tbl_bzero & postIncrementStore) ... & SRC_B_AS ... & DEST_B_AD ... { + DEST_B_AD = SRC_B_AS; + build tbl_bzero; + #Status bits are not affected + build postIncrementStore; +} + + +################################################################################### +# +# ADD: Add source to destination +# ------------------------------------------------------------------------------ +# | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +# ------------------------------------------------------------------------------ +# | 0 1 0 1 | source | Ad | B/W | As | destination | +#----------------------- +# Emulated instructions +#----------------------- +# Increment word +:INC^".W" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x5 & as=0x1 & src_Direct16_8_4=0x3 & bow=0x0 & tbl_wzero & postIncrementStore) ... & DEST_W_AD ... { + # Operation Flags... + $(CARRY) = carry(DEST_W_AD,1); # C Flag + $(OVERFLOW) = scarry(DEST_W_AD,1); # V Flag + # Operation... + DEST_W_AD = DEST_W_AD + 0x1; + build tbl_wzero; + # Result Flags... + $(SIGN) = (DEST_W_AD s< 0x0); # S Flag + $(ZERO) = (DEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + +# Increment byte +:INC^".B" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x5 & as=0x1 & src_Direct16_8_4=0x3 & bow=0x1 & tbl_bzero & postIncrementStore) ... & DEST_B_AD ... { + # Operation Flags... + $(CARRY) = carry(DEST_B_AD,1); # C Flag + $(OVERFLOW) = scarry(DEST_B_AD,1); # V Flag + # Operation... + DEST_B_AD = DEST_B_AD + 0x1; + build tbl_bzero; + # Result Flags... + $(SIGN) = (DEST_B_AD s< 0x0); # S Flag + $(ZERO) = (DEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + +# Double increment word +:INCD^".W" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x5 & as=0x2 & src_Direct16_8_4=0x3 & bow=0x0 & tbl_wzero & postIncrementStore) ... & DEST_W_AD ... { + # Operation Flags... + $(CARRY) = carry(DEST_W_AD,2); # C Flag + $(OVERFLOW) = scarry(DEST_W_AD,2); # V Flag + # Operation... + DEST_W_AD = DEST_W_AD + 0x2; + build tbl_wzero; + # Result Flags... + $(SIGN) = (DEST_W_AD s< 0x0); # S Flag + $(ZERO) = (DEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + +# Double increment byte +:INCD^".B" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x5 & as=0x2 & src_Direct16_8_4=0x3 & bow=0x1 & tbl_bzero & postIncrementStore) ... & DEST_B_AD ... { + # Operation Flags... + $(CARRY) = carry(DEST_B_AD,2); # C Flag + $(OVERFLOW) = scarry(DEST_B_AD,2); # V Flag + # Operation... + DEST_B_AD = DEST_B_AD + 0x2; + build tbl_bzero; + # Result Flags... + $(SIGN) = (DEST_B_AD s< 0x0); # S Flag + $(ZERO) = (DEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + +# Rotate left arithmetic (left shift once) word +:RLA^".W" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x5 & as=0x0 & ad=0x0 & src_Direct16_8_4=dest_Direct16_0_4 & bow=0x0 & tbl_wzero & postIncrementStore) ... & DEST_W_AD ... { + # Operation Flags... + $(CARRY) = carry(DEST_W_AD, DEST_W_AD); # C Flag + $(OVERFLOW) = scarry(DEST_W_AD, DEST_W_AD); # V Flag + # Operation... + DEST_W_AD = DEST_W_AD + DEST_W_AD; + build tbl_wzero; + # Result Flags... + $(SIGN) = (DEST_W_AD s< 0x0); # S Flag + $(ZERO) = (DEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + +# Rotate left arithmetic (left shift once) byte +:RLA^".B" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x5 & as=0x0 & ad=0x0 & src_Direct16_8_4=dest_Direct16_0_4 & bow=0x1 & tbl_bzero & postIncrementStore) ... & DEST_B_AD ... { + # Operation Flags... + $(CARRY) = carry(DEST_B_AD, DEST_B_AD); # C Flag + $(OVERFLOW) = scarry(DEST_B_AD, DEST_B_AD); # V Flag + # Operation... + DEST_B_AD = DEST_B_AD + DEST_B_AD; + build tbl_bzero; + # Result Flags... + $(SIGN) = (DEST_B_AD s< 0x0); # S Flag + $(ZERO) = (DEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + +#------------------ +# 16 bit SRC Word +#------------------ +:ADD^".W" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x5 & bow=0x0 & tbl_wzero & postIncrementStore) ... & SRC_W_AS ... & DEST_W_AD ... { + # Operation Flags... + $(CARRY) = carry(SRC_W_AS, DEST_W_AD); # C Flag + $(OVERFLOW) = scarry(SRC_W_AS, DEST_W_AD); # V Flag + # Operation... + DEST_W_AD = SRC_W_AS + DEST_W_AD; + build tbl_wzero; + # Result Flags... + $(SIGN) = (DEST_W_AD s< 0x0); # S Flag + $(ZERO) = (DEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + + +#------------------ +# 16 bit SRC Byte +#------------------ +:ADD^".B" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x5 & bow=0x1 & tbl_bzero & postIncrementStore) ... & SRC_B_AS ... & DEST_B_AD ... { + # Operation Flags... + $(CARRY) = carry(SRC_B_AS, DEST_B_AD); # C Flag + $(OVERFLOW) = scarry(SRC_B_AS, DEST_B_AD); # V Flag + # Operation... + DEST_B_AD = SRC_B_AS + DEST_B_AD; + build tbl_bzero; + # Result Flags... + $(SIGN) = (DEST_B_AD s< 0x0); # S Flag + $(ZERO) = (DEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + + +################################################################################### +# +# ADDC: Add source and carry to destination +# ------------------------------------------------------------------------------ +# | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +# ------------------------------------------------------------------------------ +# | 0 1 1 0 | source | Ad | B/W | As | destination | +#----------------------- +# Emulated instructions +#----------------------- +# Add carry to word +:ADC^".W" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x6 & as=0x0 & src_Direct16_8_4=0x3 & bow=0x0 & tbl_wzero & postIncrementStore) ... & DEST_W_AD ... { + # Operation Flags... + tmp_carry:1 = carry(DEST_W_AD,zext($(CARRY))); #C Flag + $(OVERFLOW) = scarry(DEST_W_AD, zext($(CARRY))); #V Flag + # Operation... + DEST_W_AD = DEST_W_AD + zext($(CARRY)); + build tbl_wzero; + # Result Flags... + $(CARRY) = tmp_carry; + $(SIGN) = (DEST_W_AD s< 0x0); # S Flag + $(ZERO) = (DEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + +# Add carry to byte +:ADC^".B" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x6 & as=0x0 & src_Direct16_8_4=0x3 & bow=0x1 & tbl_bzero & postIncrementStore) ... & DEST_B_AD ... { + # Operation Flags... + tmp_carry:1 = carry(DEST_B_AD,$(CARRY)); #C Flag + $(OVERFLOW) = scarry(DEST_B_AD,$(CARRY)); #V Flag + # Operation... + DEST_B_AD = DEST_B_AD + $(CARRY); + build tbl_bzero; + # Result Flags... + $(CARRY) = tmp_carry; + $(SIGN) = (DEST_B_AD s< 0x0); # S Flag + $(ZERO) = (DEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + +# Rotate word left through carry +:RLC^".W" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x6 & as=0x0 & ad=0x0 & src_Direct16_8_4=dest_Direct16_0_4 & bow=0x0 & tbl_wzero & postIncrementStore) ... & DEST_W_AD ... { + # Operation Flags... + tmp_carry:1 = (carry(DEST_W_AD,zext($(CARRY))) || carry(DEST_W_AD,DEST_W_AD + zext($(CARRY)))); #C Flag + $(OVERFLOW) = (scarry(DEST_W_AD,zext($(CARRY))) || scarry(DEST_W_AD,DEST_W_AD + zext($(CARRY)))); #V Flag + # Operation... + DEST_W_AD = DEST_W_AD + DEST_W_AD + zext($(CARRY)); + build tbl_wzero; + # Result Flags... + $(CARRY) = tmp_carry; + $(SIGN) = (DEST_W_AD s< 0x0); # S Flag + $(ZERO) = (DEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + +# Rotate byte left through carry +:RLC^".B" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x6 & as=0x0 & ad=0x0 & src_Direct16_8_4=dest_Direct16_0_4 & bow=0x1 & tbl_bzero & postIncrementStore) ... & DEST_B_AD ... { + # Operation Flags... + tmp_carry:1 = (carry(DEST_B_AD, $(CARRY)) || carry(DEST_B_AD,DEST_B_AD + $(CARRY))); #C Flag + $(OVERFLOW) = (scarry(DEST_B_AD, $(CARRY)) || scarry(DEST_B_AD,DEST_B_AD + $(CARRY))); #V Flag + # Operation... + DEST_B_AD = DEST_B_AD + DEST_B_AD + $(CARRY); + build tbl_bzero; + # Result Flags... + $(CARRY) = tmp_carry; + $(SIGN) = (DEST_B_AD s< 0x0); # S Flag + $(ZERO) = (DEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + +#------------------ +# 16 bit SRC Word +#------------------ +:ADDC^".W" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x6 & bow=0x0 & tbl_wzero & postIncrementStore) ... & SRC_W_AS ... & DEST_W_AD ... { + # Operation Flags... + tmp_carry:1 = (carry(SRC_W_AS,zext($(CARRY))) || carry(DEST_W_AD,SRC_W_AS + zext($(CARRY)))); #C Flag + $(OVERFLOW) = (scarry(SRC_W_AS,zext($(CARRY))) || scarry(DEST_W_AD,SRC_W_AS + zext($(CARRY)))); #V Flag + # Operation... + DEST_W_AD = SRC_W_AS + DEST_W_AD + zext($(CARRY)); + build tbl_wzero; + # Result Flags... + $(CARRY) = tmp_carry; + $(SIGN) = (DEST_W_AD s< 0x0); # S Flag + $(ZERO) = (DEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + + +#------------------ +# 16 bit SRC Byte +#------------------ +:ADDC^".B" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x6 & bow=0x1 & tbl_bzero & postIncrementStore) ... & SRC_B_AS ... & DEST_B_AD ... { + # Operation Flags... + tmp_carry:1 = (carry(SRC_B_AS, $(CARRY)) || carry(DEST_B_AD,SRC_B_AS + $(CARRY))); #C Flag + $(OVERFLOW) = (scarry(SRC_B_AS, $(CARRY)) || scarry(DEST_B_AD,SRC_B_AS + $(CARRY))); #V Flag + # Operation... + DEST_B_AD = SRC_B_AS + DEST_B_AD + $(CARRY); + build tbl_bzero; + # Result Flags... + $(CARRY) = tmp_carry; + $(SIGN) = (DEST_B_AD s< 0x0); # S Flag + $(ZERO) = (DEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + + +################################################################################### +# +# SUBC: Subtract source from destination (with carry) +# ------------------------------------------------------------------------------ +# | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +# ------------------------------------------------------------------------------ +# | 0 1 1 1 | source | Ad | B/W | As | destination | +#----------------------- +# Emulated instructions +#----------------------- +# Subtract borrow from word +:SBC^".W" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x7 & as=0x0 & src_Direct16_8_4=0x3 & bow=0x0 & tbl_wzero & postIncrementStore) ... & DEST_W_AD ... { + # Operation Flags... + brw:2 = 1 - zext( $(CARRY) ); + $(CARRY) = (brw <= DEST_W_AD); # Carry flag is NOT set if there is a borrow + $(OVERFLOW) = sborrow(DEST_W_AD, brw); + # Operation... + DEST_W_AD = DEST_W_AD - brw; + build tbl_wzero; + # Result Flags... + $(SIGN) = (DEST_W_AD s< 0x0); # S Flag + $(ZERO) = (DEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + +# Subtract borrow from byte +:SBC^".B" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x7 & as=0x0 & src_Direct16_8_4=0x3 & bow=0x1 & tbl_bzero & postIncrementStore) ... & DEST_B_AD ... { + # Operation Flags... + brw:1 = 1 - $(CARRY); + $(CARRY) = (brw <= DEST_B_AD); # Carry flag is NOT set if there is a borrow + $(OVERFLOW) = sborrow(DEST_B_AD, brw); + # Operation... + DEST_B_AD = DEST_B_AD - brw; + build tbl_bzero; + # Result Flags... + $(SIGN) = (DEST_B_AD s< 0x0); # S Flag + $(ZERO) = (DEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + +#------------------ +# 16 bit SRC Word +#------------------ +:SUBC^".W" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x7 & bow=0x0 & tbl_wzero & postIncrementStore) ... & SRC_W_AS ... & DEST_W_AD ... { + # Operation Flags... + brw:2 = 1 - zext( $(CARRY) ); + $(CARRY) = ((brw + SRC_W_AS) <= DEST_W_AD); # Carry flag is NOT set if there is a borrow + $(OVERFLOW) = sborrow(DEST_W_AD, SRC_W_AS + brw); + # Operation... + DEST_W_AD = DEST_W_AD - SRC_W_AS - brw; + build tbl_wzero; + # Result Flags... + $(SIGN) = (DEST_W_AD s< 0x0); # S Flag + $(ZERO) = (DEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + + +#------------------ +# 16 bit SRC Byte +#------------------ +:SUBC^".B" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x7 & bow=0x1 & tbl_bzero & postIncrementStore) ... & SRC_B_AS ... & DEST_B_AD ... { + # Operation Flags... + brw:1 = 1 - $(CARRY); + $(CARRY) = ((brw + SRC_B_AS) <= DEST_B_AD); # Carry flag is NOT set if there is a borrow + $(OVERFLOW) = sborrow(DEST_B_AD, SRC_B_AS + brw); + # Operation... + DEST_B_AD = DEST_B_AD - SRC_B_AS - brw; + build tbl_bzero; + # Result Flags... + $(SIGN) = (DEST_B_AD s< 0x0); # S Flag + $(ZERO) = (DEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + + +################################################################################### +# +# SUB: Subtract source from destination +# ------------------------------------------------------------------------------ +# | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +# ------------------------------------------------------------------------------ +# | 1 0 0 0 | source | Ad | B/W | As | destination | +#----------------------- +# Emulated instructions +#----------------------- +# Decrement word +:DEC^".W" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x8 & as=0x1 & src_Direct16_8_4=0x3 & bow=0x0 & tbl_wzero & postIncrementStore) ... & DEST_W_AD ... { + # Operation Flags... + $(CARRY) = (0x1 <= DEST_W_AD); # C Flag + $(OVERFLOW) = (0x8000 == DEST_W_AD); # V Flag + # Operation... + DEST_W_AD = DEST_W_AD - 0x1; + build tbl_wzero; + # Result Flags... + $(SIGN) = (DEST_W_AD s< 0x0); # S Flag + $(ZERO) = (DEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + +# Decrement byte +:DEC^".B" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x8 & as=0x1 & src_Direct16_8_4=0x3 & bow=0x1 & tbl_bzero & postIncrementStore) ... & DEST_B_AD ... { + # Operation Flags... + $(CARRY) = (0x1 <= DEST_B_AD); # C Flag + $(OVERFLOW) = (0x80 == DEST_B_AD); # V Flag + # Operation... + DEST_B_AD = DEST_B_AD - 0x1; + build tbl_bzero; + # Result Flags... + $(SIGN) = (DEST_B_AD s< 0x0); # S Flag + $(ZERO) = (DEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + +# Double decrement word +:DECD^".W" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x8 & as=0x2 & src_Direct16_8_4=0x3 & bow=0x0 & tbl_wzero & postIncrementStore) ... & DEST_W_AD ... { + # Operation Flags... + $(CARRY) = (0x2 <= DEST_W_AD); # C Flag + $(OVERFLOW) = ((0x8000 == DEST_W_AD) || (0x8001 == DEST_W_AD)); # V Flag + # Operation... + DEST_W_AD = DEST_W_AD - 0x2; + build tbl_wzero; + # Result Flags... + $(SIGN) = (DEST_W_AD s< 0x0); # S Flag + $(ZERO) = (DEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + +# Double decrement byte +:DECD^".B" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x8 & as=0x2 & src_Direct16_8_4=0x3 & bow=0x1 & tbl_bzero & postIncrementStore) ... & DEST_B_AD ... { + # Operation Flags... + $(CARRY) = (0x2 <= DEST_B_AD); # C Flag + $(OVERFLOW) = ((0x80 == DEST_B_AD) || (0x81 == DEST_B_AD)); # V Flag + # Operation... + DEST_B_AD = DEST_B_AD - 0x2; + build tbl_bzero; + # Result Flags... + $(SIGN) = (DEST_B_AD s< 0x0); # S Flag + $(ZERO) = (DEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + +#------------------ +# 16 bit SRC Word +#------------------ +:SUB^".W" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x8 & bow=0x0 & tbl_wzero & postIncrementStore) ... & SRC_W_AS ... & DEST_W_AD ... { + # Operation Flags... + $(CARRY) = (SRC_W_AS <= DEST_W_AD); # Carry is NOT set if there is a borrow + $(OVERFLOW) = sborrow(DEST_W_AD, SRC_W_AS); # V Flag + # Operation... + DEST_W_AD = DEST_W_AD - SRC_W_AS; + build tbl_wzero; + # Result Flags... + $(SIGN) = (DEST_W_AD s< 0x0); # S Flag + $(ZERO) = (DEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + + +#------------------ +# 16 bit SRC Byte +#------------------ +:SUB^".B" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x8 & bow=0x1 & tbl_bzero & postIncrementStore) ... & SRC_B_AS ... & DEST_B_AD ... { + # Operation Flags... + $(CARRY) = (SRC_B_AS <= DEST_B_AD); # Carry is NOT set if there is a borrow + $(OVERFLOW) = sborrow(DEST_B_AD, SRC_B_AS); # V Flag + # Operation... + DEST_B_AD = DEST_B_AD - SRC_B_AS; + build tbl_bzero; + # Result Flags... + $(SIGN) = (DEST_B_AD s< 0x0); # S Flag + $(ZERO) = (DEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + + +################################################################################### +# +# CMP: Compare (pretend to subtract) source from destination +# ------------------------------------------------------------------------------ +# | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +# ------------------------------------------------------------------------------ +# | 1 0 0 1 | source | Ad | B/W | As | destination | +#----------------------- +# Emulated instructions +#----------------------- +# Test word +:TST^".W" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x9 & as=0x0 & src_Direct16_8_4=0x3 & bow=0x0 & postIncrement) ... & DEST_W_AD ... { + # Operation Flags... + $(CARRY) = 1; # Carry is NOT set if there is a borrow + $(OVERFLOW) = 0; # V Flag + # Result Flags... + $(SIGN) = (DEST_W_AD s< 0x0); # S Flag + $(ZERO) = (DEST_W_AD == 0x0); # Z Flag + build postIncrement; +} + +# Test byte +:TST^".B" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x9 & as=0x0 & src_Direct16_8_4=0x3 & bow=0x1 & postIncrement) ... & DEST_B_AD ... { + # Operation Flags... + $(CARRY) = 1; # Carry is NOT set if there is a borrow + $(OVERFLOW) = 0; # V Flag + # Result Flags... + $(SIGN) = (DEST_B_AD s< 0x0); # S Flag + $(ZERO) = (DEST_B_AD == 0x0); # Z Flag + build postIncrement; +} + +#------------------ +# 16 bit SRC Word +#------------------ +:CMP^".W" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0x9 & bow=0x0 & postIncrement) ... & SRC_W_AS ... & DEST_W_AD ... { + # Operation Flags... + $(CARRY) = (SRC_W_AS <= DEST_W_AD); # Carry is NOT set if there is a borrow + $(OVERFLOW) = sborrow(DEST_W_AD, SRC_W_AS); # V Flag + # Operation... + result:2 = (DEST_W_AD - SRC_W_AS); + # Result Flags... + $(SIGN) = (result s< 0x0); # S Flag + $(ZERO) = (result == 0x0); # Z Flag + build postIncrement; +} + + +#------------------ +# 16 bit SRC Byte +#------------------ +:CMP^".B" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0x9 & bow=0x1 & postIncrement) ... & SRC_B_AS ... & DEST_B_AD ... { + # Operation Flags... + $(CARRY) = (SRC_B_AS <= DEST_B_AD); # Carry is NOT set if there is a borrow + $(OVERFLOW) = sborrow(DEST_B_AD, SRC_B_AS); # V Flag + # Operation... + result:1 = (DEST_B_AD - SRC_B_AS); + # Result Flags... + $(SIGN) = (result s< 0x0); # S Flag + $(ZERO) = (result == 0x0); # Z Flag + build postIncrement; +} + + +################################################################################### +# +# DADD: Decimal add source to destination (with carry) +# ------------------------------------------------------------------------------ +# | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +# ------------------------------------------------------------------------------ +# | 1 0 1 0 | source | Ad | B/W | As | destination | +#---------------------------------------------------------------------------------------------------------------- +# These decimal add instructions appear to lack supporting BCD p-code operations to handle carries and overflows. +#---------------------------------------------------------------------------------------------------------------- +#----------------------- +# Emulated instructions +#----------------------- +# Decimal add carry to word +:DADC^".W" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0xA & as=0x0 & src_Direct16_8_4=0x3 & bow=0x0 & tbl_wzero & postIncrementStore) ... & DEST_W_AD ... { + # Operation... + DEST_W_AD = bcd_add($(CARRY) ,DEST_W_AD); + build tbl_wzero; + # Operation Flags... + $(CARRY) = 0; # Don't currently have BCD overflow op + # Result Flags... + $(SIGN) = (DEST_W_AD s< 0x0); # S Flag + $(ZERO) = (DEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + +# Decimal add carry to byte +:DADC^".B" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0xA & as=0x0 & src_Direct16_8_4=0x3 & bow=0x1 & tbl_bzero & postIncrementStore) ... & DEST_B_AD ... { + # Operation... + DEST_B_AD = bcd_add($(CARRY),DEST_B_AD); + build tbl_bzero; + # Operation Flags... + $(CARRY) = 0; # This should be overflow + # Result Flags... + $(SIGN) = (DEST_B_AD s< 0x0); # S Flag + $(ZERO) = (DEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + +#------------------ +# 16 bit SRC Word +#------------------ +:DADD^".W" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0xA & bow=0x0 & tbl_wzero & postIncrementStore) ... & SRC_W_AS ... & DEST_W_AD ... { + # Operation Flags... + $(CARRY) = 0; # Don't currently have BCD overflow op + # Operation... + DEST_W_AD = bcd_add(SRC_W_AS ,DEST_W_AD); + build tbl_wzero; + # Result Flags... + $(SIGN) = (DEST_W_AD s< 0x0); # S Flag + $(ZERO) = (DEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + +#------------------ +# 16 bit SRC Byte +#------------------ +:DADD^".B" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0xA & bow=0x1 & tbl_bzero & postIncrementStore) ... & SRC_B_AS ... & DEST_B_AD ... { + # Operation Flags... + $(CARRY) = 0; # This should be overflow + # Operation... + DEST_B_AD = bcd_add(SRC_B_AS,DEST_B_AD); + build tbl_bzero; + # Result Flags... + $(SIGN) = (DEST_B_AD s< 0x0); # S Flag + $(ZERO) = (DEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + + +################################################################################### +# +# BIT: Test bits of source AND destination +# ------------------------------------------------------------------------------ +# | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +# ------------------------------------------------------------------------------ +# | 1 0 1 1 | source | Ad | B/W | As | destination | +#------------------ +# 16 bit SRC Word +#------------------ +:BIT^".W" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0xB & bow=0x0 & postIncrement) ... & SRC_W_AS ... & DEST_W_AD ... { + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag (reset) + # Operation... + result:2 = DEST_W_AD & SRC_W_AS; + # Result Flags... + $(CARRY) = (result != 0x0); # C Flag + $(SIGN) = (result s< 0x0); # S Flag + $(ZERO) = (result == 0x0); # Z Flag + build postIncrement; +} + + +#------------------ +# 16 bit SRC Byte +#------------------ +:BIT^".B" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0xB & bow=0x1 & postIncrement) ... & SRC_B_AS ... & DEST_B_AD ... { + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag (reset) + # Operation... + result:1 = DEST_B_AD & SRC_B_AS; + # Result Flags... + $(CARRY) = (result != 0x0); # C Flag + $(SIGN) = (result s< 0x0); # S Flag + $(ZERO) = (result == 0x0); # Z Flag + build postIncrement; +} + + +################################################################################### +# +# BIC: Bit clear (dest &= ~src) +# ------------------------------------------------------------------------------ +# | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +# ------------------------------------------------------------------------------ +# | 1 1 0 0 | source | Ad | B/W | As | destination | +#----------------------- +# Emulated instructions +#----------------------- +# Clear carry bit +:CLRC is ctx_haveext=0 & op16_12_4=0xC & as=0x1 & src_Direct16_8_4=0x3 & ad=0x0 & dest_Direct16_0_4=0x2 & bow=0x0 & postIncrementStore { + $(CARRY) = 0; + build postIncrementStore; +} + +# Clear sign bit +:CLRN is ctx_haveext=0 & op16_12_4=0xC & as=0x2 & src_Direct16_8_4=0x2 & ad=0x0 & dest_Direct16_0_4=0x2 & bow=0x0 & postIncrementStore { + $(SIGN) = 0; + build postIncrementStore; +} + +# Clear zero bit +:CLRZ is ctx_haveext=0 & op16_12_4=0xC & as=0x2 & src_Direct16_8_4=0x3 & ad=0x0 & dest_Direct16_0_4=0x2 & bow=0x0 & postIncrementStore { + $(ZERO) = 0; + build postIncrementStore; +} + +# Disable interrupts +:DINT is ctx_haveext=0 & op16_12_4=0xC & as=0x3 & src_Direct16_8_4=0x2 & ad=0x0 & dest_Direct16_0_4=0x2 & postIncrementStore { + $(GIE) = 0; + build postIncrementStore; +} + +#------------------ +# 16 bit SRC Word +#------------------ +:BIC^".W" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0xC & bow=0x0 & tbl_wzero & postIncrementStore) ... & SRC_W_AS ... & DEST_W_AD ... { + DEST_W_AD = (~SRC_W_AS) & DEST_W_AD; + build tbl_wzero; + #Status bits are not affected + build postIncrementStore; +} + + +#------------------ +# 16 bit SRC Byte +#------------------ +:BIC^".B" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0xC & bow=0x1 & tbl_bzero & postIncrementStore) ... & SRC_B_AS ... & DEST_B_AD ... { + DEST_B_AD = (~SRC_B_AS) & DEST_B_AD; + build tbl_bzero; + #Status bits are not affected + build postIncrementStore; +} + + +################################################################################### +# +# BIS: Bit set (logical OR) +# ------------------------------------------------------------------------------ +# | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +# ------------------------------------------------------------------------------ +# | 1 1 0 1 | source | Ad | B/W | As | destination | +#----------------------- +# Emulated instructions +#----------------------- +# Enable interrupts +:EINT is ctx_haveext=0 & op16_12_4=0xD & as=0x3 & src_Direct16_8_4=0x2 & ad=0x0 & dest_Direct16_0_4=0x2 & postIncrementStore { + $(GIE) = 1; + build postIncrementStore; +} + +# Set carry bit +:SETC is ctx_haveext=0 & (op16_12_4=0xD & as=0x1 & src_Direct16_8_4=0x3 & ad=0x0 & dest_Direct16_0_4=0x2 & bow=0x0 & postIncrementStore) { + $(CARRY) = 1; + build postIncrementStore; +} + +# Set sign bit +:SETN is ctx_haveext=0 & (op16_12_4=0xD & as=0x2 & src_Direct16_8_4=0x2 & ad=0x0 & dest_Direct16_0_4=0x2 & bow=0x0 & postIncrementStore) { + $(SIGN) = 1; + build postIncrementStore; +} + +# Set zero bit +:SETZ is ctx_haveext=0 & (op16_12_4=0xD & as=0x2 & src_Direct16_8_4=0x3 & ad=0x0 & dest_Direct16_0_4=0x2 & bow=0x0 & postIncrementStore) { + $(ZERO) = 1; + build postIncrementStore; +} + +#------------------ +# 16 bit SRC Word +#------------------ +:BIS^".W" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0xD & bow=0x0 & tbl_wzero & postIncrementStore) ... & SRC_W_AS ... & DEST_W_AD ... { + DEST_W_AD = SRC_W_AS | DEST_W_AD; + build tbl_wzero; + #Status bits are not affected + build postIncrementStore; +} + + +#------------------ +# 16 bit SRC Byte +#------------------ +:BIS^".B" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0xD & bow=0x1 & tbl_bzero & postIncrementStore) ... & SRC_B_AS ... & DEST_B_AD ... { + DEST_B_AD = SRC_B_AS | DEST_B_AD; + build tbl_bzero; + #Status bits are not affected + build postIncrementStore; +} + + + +################################################################################### +# +# XOR: Exclusive or source with destination +# ------------------------------------------------------------------------------ +# | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +# ------------------------------------------------------------------------------ +# | 1 1 1 0 | source | Ad | B/W | As | destination | +#----------------------- +# Emulated instructions +#----------------------- +# Invert word +:INV^".W" DEST_W_AD is ctx_haveext=0 & (op16_12_4=0xE & as=0x3 & src_Direct16_8_4=0x3 & bow=0x0 & tbl_wzero & postIncrementStore) ... & DEST_W_AD ... { + # Operation Flags... + $(OVERFLOW) = (DEST_W_AD s< 0x0); # V Flag + # Operation... + DEST_W_AD = DEST_W_AD ^ 0xFFFF; + build tbl_wzero; + # Result Flags... + $(SIGN) = (DEST_W_AD s< 0x0); # S Flag + $(ZERO) = (DEST_W_AD == 0x0); # Z Flag + $(CARRY) = (DEST_W_AD != 0x0); # C Flag + build postIncrementStore; +} + +# Invert byte +:INV^".B" DEST_B_AD is ctx_haveext=0 & (op16_12_4=0xE & as=0x3 & src_Direct16_8_4=0x3 & bow=0x1 & tbl_bzero & postIncrementStore) ... & DEST_B_AD ... { + # Operation Flags... + $(OVERFLOW) = (DEST_B_AD s< 0x0); # V Flag + # Operation... + DEST_B_AD = DEST_B_AD ^ 0xFF; + build tbl_bzero; + # Result Flags... + $(SIGN) = (DEST_B_AD s< 0x0); # S Flag + $(ZERO) = (DEST_B_AD == 0x0); # Z Flag + $(CARRY) = (DEST_B_AD != 0x0); # C Flag + build postIncrementStore; +} + +#------------------ +# 16 bit SRC Word +#------------------ +:XOR^".W" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0xE & bow=0x0 & tbl_wzero & postIncrementStore) ... & SRC_W_AS ... & DEST_W_AD ... { + # Operation Flags... + $(OVERFLOW) = ((DEST_W_AD s< 0x0) && (SRC_W_AS s< 0x0)) ; # V Flag + # Operation... + DEST_W_AD = DEST_W_AD ^ SRC_W_AS; + build tbl_wzero; + # Result Flags... + $(SIGN) = (DEST_W_AD s< 0x0); # S Flag + $(ZERO) = (DEST_W_AD == 0x0); # Z Flag + $(CARRY) = (DEST_W_AD != 0x0); # C Flag + build postIncrementStore; +} + +#------------------ +# 16 bit SRC Byte +#------------------ +:XOR^".B" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0xE & bow=0x1 & tbl_bzero & postIncrementStore) ... & SRC_B_AS ... & DEST_B_AD ... { + # Operation Flags... + $(OVERFLOW) = ((DEST_B_AD s< 0x0) && (SRC_B_AS s< 0x0)) ; # V Flag + # Operation... + DEST_B_AD = DEST_B_AD ^ SRC_B_AS; + build tbl_bzero; + # Result Flags... + $(SIGN) = (DEST_B_AD s< 0x0); # S Flag + $(ZERO) = (DEST_B_AD == 0x0); # Z Flag + $(CARRY) = (DEST_B_AD != 0x0); # C Flag + build postIncrementStore; +} + + +################################################################################### +# +# AND: Logical AND source with destination (dest &= src) +# ------------------------------------------------------------------------------ +# | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +# ------------------------------------------------------------------------------ +# | 1 1 1 1 | source | Ad | B/W | As | destination | +#------------------ +# 16 bit SRC Word +#------------------ +:AND^".W" SRC_W_AS, DEST_W_AD is ctx_haveext=0 & (op16_12_4=0xF & bow=0x0 & tbl_wzero & postIncrementStore) ... & SRC_W_AS ... & DEST_W_AD ... { + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag + # Operation... + result:2 = DEST_W_AD & SRC_W_AS; + DEST_W_AD = result; + build tbl_wzero; + # Result Flags... + $(SIGN) = (result s< 0x0); # S Flag + $(ZERO) = (result == 0x0); # Z Flag + $(CARRY) = (result != 0x0); # C Flag + build postIncrementStore; +} + + +#------------------ +# 16 bit SRC Byte +#------------------ +:AND^".B" SRC_B_AS, DEST_B_AD is ctx_haveext=0 & (op16_12_4=0xF & bow=0x1 & tbl_bzero & postIncrementStore) ... & SRC_B_AS ... & DEST_B_AD ... { + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag + # Operation... + result:1 = DEST_B_AD & SRC_B_AS; + DEST_B_AD = result; + build tbl_bzero; + # Result Flags... + $(SIGN) = (result s< 0x0); # S Flag + $(ZERO) = (result == 0x0); # Z Flag + $(CARRY) = (result != 0x0); # C Flag + build postIncrementStore; +} diff --git a/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/TI430X.sinc b/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/TI430X.sinc new file mode 100644 index 0000000..25f97dd --- /dev/null +++ b/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/TI430X.sinc @@ -0,0 +1,3541 @@ +################################################################################### +# +# 20bit Address Instructions +# +# The original way of using sub-tables to breakout the addressing modes does not +# work for these instructions + +:^instruction is opext_11_5=0x3 & ctx_haveext=0 & dest_0_4 & src_ext & al & zc & ad; instruction [ ctx_haveext=1; ctx_ctregdest=dest_0_4; ctx_regsrc=src_ext; ctx_al=al; ctx_num=ad; ctx_zc=zc; ] {$(CARRY)=$(CARRY) * (zc:1 == 0); build instruction;} + + +#:^instruction is ctx_haveext=1 & instruction & as=1 & src_8_4=3 [ctx_haveext=2;] {build instruction;} +:^instruction is ctx_haveext=1 & instruction & as=1 & src_8_4=3 [ctx_haveext=7;] {build instruction;} #replacment substituting second of haveext=2. NOTE: as=1 precludes first +:^instruction is ctx_haveext=1 & instruction & as=1 [ctx_haveext=7;] {build instruction;} +:^instruction is ctx_haveext=1 & instruction & as=3 & src_8_4=0 [ctx_haveext=7;] {build instruction;} +#:^instruction is ctx_haveext=1 & instruction [ctx_haveext=2;] {build instruction;} +:^instruction is ctx_haveext=1 & instruction & as=0 & ad=0 [ctx_haveext=3;] {build instruction;} #replacement substituting first of haveext=2 +:^instruction is ctx_haveext=1 & instruction [ctx_haveext=7;] {build instruction;} #replacement substituting second of haveext=2 + +:^instruction is ctx_haveext=1 & instruction & op16_7_9=0x23 & as=0 [ctx_haveext=3;] {build instruction;} +:^instruction is ctx_haveext=1 & instruction & op16_7_9=0x21 & as=0 [ctx_haveext=3;] {build instruction;} +:^instruction is ctx_haveext=1 & instruction & op16_12_4=0x1 & as=1 & reg16_0_4=3 [ctx_haveext=3;] {build instruction;} +:^instruction is ctx_haveext=1 & instruction & op16_12_4=0x1 & as=1 [ctx_haveext=7;] {build instruction;} +:^instruction is ctx_haveext=1 & instruction & op16_12_4=0x1 & as=3 & reg16_0_4=0 [ctx_haveext=7;] {build instruction;} + +# removed haveext=2 +#:^instruction is ctx_haveext=2 & instruction & as=0 & ad=0 [ctx_haveext=3;] {build instruction;} +#:^instruction is ctx_haveext=2 & instruction [ctx_haveext=7;] {build instruction;} + + + +:^instruction is ctx_haveext=3 & instruction & ctx_num=0 & ctx_ctregdest=0 [ctx_haveext=4;] { CNT = 0;build instruction; } +:"RPT #"^val^" { "^instruction is ctx_haveext=3 & instruction & ctx_num=0 & ctx_ctregdest [ctx_haveext=4; val = ctx_ctregdest+1;] { CNT = ctx_ctregdest;build instruction;} +:"RPT "^ctx_repreg^" { "^instruction is ctx_haveext=3 & instruction & ctx_num=1 & ctx_repreg [ctx_haveext=4;] { CNT = zext(ctx_repreg[0,4]); build instruction;} + + +# 20bit address mode sub tables +Abs20: val is ctx_ctregdest & imm_0_16 [ val=(ctx_ctregdest << 16) | imm_0_16;] {export *[const]:3 val;} +Abs20s: val is ctx_ctregdests & imm_0_16 [ val=(ctx_ctregdests << 16) | imm_0_16;] {export *[const]:3 val;} +Abs20add: val is ctx_ctregdest & imm_0_16 [ val=(ctx_ctregdest << 16) | imm_0_16;] {export *:4 val;} + +Imm20Dst: val is ctx_ctregdest & imm_0_16 [ val=(ctx_ctregdest << 16) | imm_0_16;] {export *[const]:4 val;} +ImmS20Dst: val is ctx_ctregdests & imm_0_16 [ val=(ctx_ctregdests << 16) | imm_0_16;] {export *[const]:4 val;} +Imm20Src: val is ctx_regsrc & imm_0_16 [ val=(ctx_regsrc << 16) | imm_0_16;] {export *[const]:4 val;} +ImmS20Src: val is ctx_regsrcs & imm_0_16 [ val=(ctx_regsrcs << 16) | imm_0_16;] {export *[const]:4 val;} + +Label20Src: labelCalc is ctx_regsrcs & imm_0_16 [ labelCalc = inst_start + 4 + ((ctx_regsrcs << 16) | imm_0_16);] {export *[const]:4 labelCalc;} +Label20Dst: labelCalc is ctx_ctregdests & imm_0_16 [ labelCalc = inst_start + 4 + ((ctx_ctregdests << 16) | imm_0_16);] {export *[const]:4 labelCalc;} +Label20DstExt: labelCalc is ctx_ctregdests & imm_0_16 [ labelCalc = inst_start + 6 + ((ctx_ctregdests << 16) | imm_0_16);] {export *[const]:4 labelCalc;} + +IMM4: val is imm_4_4 [val = imm_4_4+1;] {export *[const]:1 val;} +NUM2: val is rrn [ val = rrn+1;] {export *[const]:1 val;} + +XREG_B_AS: DST8_0_4 is DST8_0_4 & as=0x0 & bow=0x1 { export DST8_0_4;} # Word/Register Direct (Rn): +XREG_B_AS: ImmS20Src^"("^reg_Indexed16_0_4^")" is reg_Indexed16_0_4 & as=0x1 & bow=0x1 ; ImmS20Src {tmp:$(REG_SIZE) = reg_Indexed16_0_4 + ImmS20Src; export *:1 tmp;} +XREG_B_AS: "@"^reg_InDirect16_0_4 is reg_InDirect16_0_4 & as=0x2 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn): +XREG_B_AS: "@"^reg_InDirect16_0_4^"+" is reg_InDirect16_0_4 & as=0x3 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+): +XREG_B_AS: Label20Src is reg16_0_4=0x0 & as=0x1 & bow=0x1 ; Label20Src {export *:1 Label20Src; } # Symbolic +XREG_B_AS: "#"^ImmS20Src is reg16_0_4=0x0 & as=0x3 & bow=0x1 ; ImmS20Src {export *[const]:1 ImmS20Src; } # Immediate +XREG_B_AS: "&"^Imm20Src is reg16_0_4=0x2 & as=0x1 & bow=0x1 ; Imm20Src {export *:1 Imm20Src; } # Absolute +XREG_B_AS: "#4" is reg16_0_4=0x2 & as=0x2 & bow=0x1 { export 4:1;} # Constant +XREG_B_AS: "#8" is reg16_0_4=0x2 & as=0x3 & bow=0x1 { export 8:1;} # Constant +XREG_B_AS: "#0" is reg16_0_4=0x3 & as=0x0 & bow=0x1 { export 0:1;} # Constant +XREG_B_AS: "#1" is reg16_0_4=0x3 & as=0x1 & bow=0x1 { export 1:1;} # Constant +XREG_B_AS: "#2" is reg16_0_4=0x3 & as=0x2 & bow=0x1 { export 2:1;} # Constant +XREG_B_AS: "#-1" is reg16_0_4=0x3 & as=0x3 & bow=0x1 { export 0xff:1;} # Constant + +XRREG_B_AS: DST8_0_4 is DST8_0_4 & as=0x0 & bow=0x1 { export DST8_0_4;} # Word/Register Direct (Rn): +XRREG_B_AS: "@"^reg_InDirect16_0_4 is reg_InDirect16_0_4 & as=0x2 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn): +XRREG_B_AS: "@"^reg_InDirect16_0_4^"+" is reg_InDirect16_0_4 & as=0x3 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+): +XRREG_B_AS: "#4" is reg16_0_4=0x2 & as=0x2 & bow=0x1 { export 4:1;} # Constant +XRREG_B_AS: "#8" is reg16_0_4=0x2 & as=0x3 & bow=0x1 { export 8:1;} # Constant +XRREG_B_AS: "#0" is reg16_0_4=0x3 & as=0x0 & bow=0x1 { export 0:1;} # Constant +XRREG_B_AS: "#1" is reg16_0_4=0x3 & as=0x1 & bow=0x1 { export 1:1;} # Constant +XRREG_B_AS: "#2" is reg16_0_4=0x3 & as=0x2 & bow=0x1 { export 2:1;} # Constant +XRREG_B_AS: "#-1" is reg16_0_4=0x3 & as=0x3 & bow=0x1 { export 0xff:1;} # Constant + +XREG_W_AS: DST16_0_4 is DST16_0_4 & as=0x0 & bow=0x0 {export DST16_0_4;} # Word/Register Direct (Rn): +XREG_W_AS: ImmS20Src^"("^reg_Indexed16_0_4^")" is reg_Indexed16_0_4 & as=0x1 & bow=0x0 ; ImmS20Src {tmp:$(REG_SIZE) = reg_Indexed16_0_4 + ImmS20Src; export *:2 tmp;} +XREG_W_AS: "@"^reg_InDirect16_0_4 is reg_InDirect16_0_4 & as=0x2 & bow=0x0 {export *:2 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn): +XREG_W_AS: "@"^reg_InDirect16_0_4^"+" is reg_InDirect16_0_4 & as=0x3 & bow=0x0 {export *:2 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+): +XREG_W_AS: Label20Src is reg16_0_4=0x0 & as=0x1 & bow=0x0 ; Label20Src {export *:2 Label20Src; } # Symbolic +XREG_W_AS: "#"^ImmS20Src is reg16_0_4=0x0 & as=0x3 & bow=0x0 ; ImmS20Src {export *[const]:2 ImmS20Src; } # Immediate +XREG_W_AS: "&"^Imm20Src is reg16_0_4=0x2 & as=0x1 & bow=0x0 ; Imm20Src {export *:2 Imm20Src; } # Absolute +XREG_W_AS: "#4" is reg16_0_4=0x2 & as=0x2 & bow=0x0 { export 4:2;} # Constant +XREG_W_AS: "#8" is reg16_0_4=0x2 & as=0x3 & bow=0x0 { export 8:2;} # Constant +XREG_W_AS: "#0" is reg16_0_4=0x3 & as=0x0 & bow=0x0 { export 0:2;} # Constant +XREG_W_AS: "#1" is reg16_0_4=0x3 & as=0x1 & bow=0x0 { export 1:2;} # Constant +XREG_W_AS: "#2" is reg16_0_4=0x3 & as=0x2 & bow=0x0 { export 2:2;} # Constant +XREG_W_AS: "#-1" is reg16_0_4=0x3 & as=0x3 & bow=0x0 { export 0xffff:2;} # Constant + +XRREG_W_AS: DST16_0_4 is DST16_0_4 & as=0x0 & bow=0x0 {export DST16_0_4;} # Word/Register Direct (Rn): +XRREG_W_AS: "@"^reg_InDirect16_0_4 is reg_InDirect16_0_4 & as=0x2 & bow=0x0 {export *:2 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn): +XRREG_W_AS: "@"^reg_InDirect16_0_4^"+" is reg_InDirect16_0_4 & as=0x3 & bow=0x0 {export *:2 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+): +XRREG_W_AS: "#4" is reg16_0_4=0x2 & as=0x2 & bow=0x0 { export 4:2;} # Constant +XRREG_W_AS: "#8" is reg16_0_4=0x2 & as=0x3 & bow=0x0 { export 8:2;} # Constant +XRREG_W_AS: "#0" is reg16_0_4=0x3 & as=0x0 & bow=0x0 { export 0:2;} # Constant +XRREG_W_AS: "#1" is reg16_0_4=0x3 & as=0x1 & bow=0x0 { export 1:2;} # Constant +XRREG_W_AS: "#2" is reg16_0_4=0x3 & as=0x2 & bow=0x0 { export 2:2;} # Constant +XRREG_W_AS: "#-1" is reg16_0_4=0x3 & as=0x3 & bow=0x0 { export 0xffff:2;} # Constant + +XREG_A_AS: dest_0_4 is dest_0_4 & as=0 & bow=0x1 {export dest_0_4;} +XREG_A_AS: ImmS20Src^"("^reg_Indexed16_0_4^")" is reg_Indexed16_0_4 & as=0x1 & bow=0x1 ; ImmS20Src {tmp:$(REG_SIZE) = reg_Indexed16_0_4 + ImmS20Src; export *:$(REG_SIZE) tmp;} +XREG_A_AS: "@"^reg_InDirect16_0_4 is reg_InDirect16_0_4 & as=0x2 & bow=0x1 {export *:$(REG_SIZE) reg_InDirect16_0_4;} # Word/Register Indirect (@Rn): +XREG_A_AS: "@"^reg_InDirect16_0_4^"+" is reg_InDirect16_0_4 & as=0x3 & bow=0x1 {export *:$(REG_SIZE) reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+): +XREG_A_AS: Label20Src is reg16_0_4=0x0 & as=0x1 & bow=0x1 ; Label20Src {export *:$(REG_SIZE) Label20Src; } # Symbolic +XREG_A_AS: "#"^ImmS20Src is reg16_0_4=0x0 & as=0x3 & bow=0x1 ; ImmS20Src {export *[const]:$(REG_SIZE) ImmS20Src; } # Immediate +XREG_A_AS: "&"^Imm20Src is reg16_0_4=0x2 & as=0x1 & bow=0x1 ; Imm20Src {export *:$(REG_SIZE) Imm20Src; } # Absolute +XREG_A_AS: "#4" is reg16_0_4=0x2 & as=0x2 & bow=0x1 { export 4:$(REG_SIZE);} # Constant +XREG_A_AS: "#8" is reg16_0_4=0x2 & as=0x3 & bow=0x1 { export 8:$(REG_SIZE);} # Constant +XREG_A_AS: "#0" is reg16_0_4=0x3 & as=0x0 & bow=0x1 { export 0:$(REG_SIZE);} # Constant +XREG_A_AS: "#1" is reg16_0_4=0x3 & as=0x1 & bow=0x1 { export 1:$(REG_SIZE);} # Constant +XREG_A_AS: "#2" is reg16_0_4=0x3 & as=0x2 & bow=0x1 { export 2:$(REG_SIZE);} # Constant +XREG_A_AS: "#-1" is reg16_0_4=0x3 & as=0x3 & bow=0x1 { export 0xffffffff:$(REG_SIZE);} # Constant + +XRREG_A_AS: dest_0_4 is dest_0_4 & as=0 & bow=0x1 {export dest_0_4;} +XRREG_A_AS: "@"^reg_InDirect16_0_4 is reg_InDirect16_0_4 & as=0x2 & bow=0x1 {export *:$(REG_SIZE) reg_InDirect16_0_4;} # Word/Register Indirect (@Rn): +XRREG_A_AS: "@"^reg_InDirect16_0_4^"+" is reg_InDirect16_0_4 & as=0x3 & bow=0x1 {export *:$(REG_SIZE) reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+): +XRREG_A_AS: "#4" is reg16_0_4=0x2 & as=0x2 & bow=0x1 { export 4:$(REG_SIZE);} # Constant +XRREG_A_AS: "#8" is reg16_0_4=0x2 & as=0x3 & bow=0x1 { export 8:$(REG_SIZE);} # Constant +XRREG_A_AS: "#0" is reg16_0_4=0x3 & as=0x0 & bow=0x1 { export 0:$(REG_SIZE);} # Constant +XRREG_A_AS: "#1" is reg16_0_4=0x3 & as=0x1 & bow=0x1 { export 1:$(REG_SIZE);} # Constant +XRREG_A_AS: "#2" is reg16_0_4=0x3 & as=0x2 & bow=0x1 { export 2:$(REG_SIZE);} # Constant +XRREG_A_AS: "#-1" is reg16_0_4=0x3 & as=0x3 & bow=0x1 { export 0xffffffff:$(REG_SIZE);} # Constant + +XREG_B_AS_DEST: DST8_0_4 is DST8_0_4 & as=0x0 & bow=0x1 { export DST8_0_4;} # Word/Register Direct (Rn): +XREG_B_AS_DEST: ImmS20Dst^"("^reg_Indexed16_0_4^")" is reg_Indexed16_0_4 & as=0x1 & bow=0x1 ; ImmS20Dst {tmp:$(REG_SIZE) = reg_Indexed16_0_4 + ImmS20Dst; export *:1 tmp;} +XREG_B_AS_DEST: "@"^reg_InDirect16_0_4 is reg_InDirect16_0_4 & as=0x2 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn): +XREG_B_AS_DEST: "@"^reg_InDirect16_0_4^"+" is reg_InDirect16_0_4 & as=0x3 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+): +XREG_B_AS_DEST: Label20Dst is reg16_0_4=0x0 & as=0x1 & bow=0x1 ; Label20Dst {export *:1 Label20Dst; } # Symbolic +XREG_B_AS_DEST: "&"^Imm20Dst is reg16_0_4=0x2 & as=0x1 & bow=0x1 ; Imm20Dst {export *:1 Imm20Dst; } # Absolute + +XRREG_B_AS_DEST: DST8_0_4 is DST8_0_4 & as=0x0 & reg_Direct16_0_4 & bow=0x1 { ztmp:1 = DST8_0_4; reg_Direct16_0_4=0; DST8_0_4 = ztmp; export DST8_0_4;} # Word/Register Direct (Rn): +XRREG_B_AS_DEST: "@"^reg_InDirect16_0_4 is reg_InDirect16_0_4 & as=0x2 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn): +XRREG_B_AS_DEST: "@"^reg_InDirect16_0_4^"+" is reg_InDirect16_0_4 & as=0x3 & bow=0x1 {export *:1 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+): + +XREG_W_AS_DEST: ImmS20Dst^"("^reg_Indexed16_0_4^")" is reg_Indexed16_0_4 & as=0x1 & bow=0x0 ; ImmS20Dst {tmp:$(REG_SIZE) = reg_Indexed16_0_4 + ImmS20Dst; export *:2 tmp;} +XREG_W_AS_DEST: "@"^reg_InDirect16_0_4 is reg_InDirect16_0_4 & as=0x2 & bow=0x0 {export *:2 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn): +XREG_W_AS_DEST: "@"^reg_InDirect16_0_4^"+" is reg_InDirect16_0_4 & as=0x3 & bow=0x0 {export *:2 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+): +XREG_W_AS_DEST: Label20Dst is reg16_0_4=0x0 & as=0x1 & bow=0x0 ; Label20Dst {export *:2 Label20Dst; } # Symbolic +XREG_W_AS_DEST: "&"^Imm20Dst is reg16_0_4=0x2 & as=0x1 & bow=0x0 ; Imm20Dst {export *:2 Imm20Dst; } # Absolute + +XRREG_W_AS_DEST: DST16_0_4 is DST16_0_4 & as=0x0 & reg_Direct16_0_4 & bow=0x0 {ztmp:2 = DST16_0_4; reg_Direct16_0_4=0; DST16_0_4 = ztmp;export DST16_0_4;} # Word/Register Direct (Rn): +XRREG_W_AS_DEST: "@"^reg_InDirect16_0_4 is reg_InDirect16_0_4 & as=0x2 & bow=0x0 {export *:2 reg_InDirect16_0_4;} # Word/Register Indirect (@Rn): +XRREG_W_AS_DEST: "@"^reg_InDirect16_0_4^"+" is reg_InDirect16_0_4 & as=0x3 & bow=0x0 {export *:2 reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+): + +XREG_A_AS_DEST: ImmS20Dst^"("^reg_Indexed16_0_4^")" is reg_Indexed16_0_4 & as=0x1 & bow=0x1 ; ImmS20Dst {tmp:$(REG_SIZE) = reg_Indexed16_0_4 + ImmS20Dst; export *:$(REG_SIZE) tmp;} +XREG_A_AS_DEST: "@"^reg_InDirect16_0_4 is reg_InDirect16_0_4 & as=0x2 & bow=0x1 {export *:$(REG_SIZE) reg_InDirect16_0_4;} # Word/Register Indirect (@Rn): +XREG_A_AS_DEST: "@"^reg_InDirect16_0_4^"+" is reg_InDirect16_0_4 & as=0x3 & bow=0x1 {export *:$(REG_SIZE) reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+): +XREG_A_AS_DEST: Label20Dst is reg16_0_4=0x0 & as=0x1 & bow=0x1 ; Label20Dst {export *:$(REG_SIZE) Label20Dst; } # Symbolic +XREG_A_AS_DEST: "&"^Imm20Dst is reg16_0_4=0x2 & as=0x1 & bow=0x1 ; Imm20Dst {export *:$(REG_SIZE) Imm20Dst; } # Absolute + +XRREG_A_AS_DEST: dest_0_4 is dest_0_4 & as=0 & bow=0x1 {export dest_0_4;} +XRREG_A_AS_DEST: "@"^reg_InDirect16_0_4 is reg_InDirect16_0_4 & as=0x2 & bow=0x1 {export *:$(REG_SIZE) reg_InDirect16_0_4;} # Word/Register Indirect (@Rn): +XRREG_A_AS_DEST: "@"^reg_InDirect16_0_4^"+" is reg_InDirect16_0_4 & as=0x3 & bow=0x1 {export *:$(REG_SIZE) reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+): + +XREG_A_AS_DEST2: Imm20Dst^"("^reg_Indexed16_0_4^")" is reg_Indexed16_0_4 & as=0x1 & bow=0x0 ; Imm20Dst {tmp:$(REG_SIZE) = reg_Indexed16_0_4 + Imm20Dst; export *:$(REG_SIZE) tmp;} +XREG_A_AS_DEST2: "@"^reg_InDirect16_0_4 is reg_InDirect16_0_4 & as=0x2 & bow=0x0 {export *:$(REG_SIZE) reg_InDirect16_0_4;} # Word/Register Indirect (@Rn): +XREG_A_AS_DEST2: "@"^reg_InDirect16_0_4^"+" is reg_InDirect16_0_4 & as=0x3 & bow=0x0 {export *:$(REG_SIZE) reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+): +XREG_A_AS_DEST2: Label20Dst is reg16_0_4=0x0 & as=0x1 & bow=0x0 ; Label20Dst {export *:$(REG_SIZE) Label20Dst; } # Symbolic +XREG_A_AS_DEST2: "&"^Imm20Dst is reg16_0_4=0x2 & as=0x1 & bow=0x0 ; Imm20Dst {export *:$(REG_SIZE) Imm20Dst; } # Absolute + +XRREG_A_AS_DEST2: dest_0_4 is dest_0_4 & as=0 & bow=0x0 {export dest_0_4;} +XRREG_A_AS_DEST2: "@"^reg_InDirect16_0_4 is reg_InDirect16_0_4 & as=0x2 & bow=0x0 {export *:$(REG_SIZE) reg_InDirect16_0_4;} # Word/Register Indirect (@Rn): +XRREG_A_AS_DEST2: "@"^reg_InDirect16_0_4^"+" is reg_InDirect16_0_4 & as=0x3 & bow=0x0 {export *:$(REG_SIZE) reg_InDirect16_0_4;} # Word/Register Indirect Autoincrement (@Rn+): + +XSRC_B_AS: SRC8_8_4 is SRC8_8_4 & as=0x0 & bow=0x1 { export SRC8_8_4;} # Word/Register Direct (Rn): +XSRC_B_AS: ImmS20Src^"("^src_Indexed16_8_4^")" is src_Indexed16_8_4 & as=0x1 & bow=0x1 ; ImmS20Src {tmp:$(REG_SIZE) = src_Indexed16_8_4 + ImmS20Src; export *:1 tmp;} +XSRC_B_AS: "@"^src_InDirect16_8_4 is src_InDirect16_8_4 & as=0x2 & bow=0x1 {export *:1 src_InDirect16_8_4;} # Word/Register Indirect (@Rn): +XSRC_B_AS: "@"^src_InDirect16_8_4^"+" is src_InDirect16_8_4 & as=0x3 & bow=0x1 {export *:1 src_InDirect16_8_4;} # Word/Register Indirect Autoincrement (@Rn+): +XSRC_B_AS: Label20Src is src16_8_4=0x0 & as=0x1 & bow=0x1 ; Label20Src {export *:1 Label20Src; } # Symbolic +XSRC_B_AS: "#"^ImmS20Src is src16_8_4=0x0 & as=0x3 & bow=0x1 ; ImmS20Src {export *[const]:1 ImmS20Src;} # Immediate +XSRC_B_AS: "&"^Imm20Src is src16_8_4=0x2 & as=0x1 & bow=0x1 ; Imm20Src {export *:1 Imm20Src; } # Absolute +XSRC_B_AS: "#4" is src16_8_4=0x2 & as=0x2 & bow=0x1 { export 4:1; } # Constant +XSRC_B_AS: "#8" is src16_8_4=0x2 & as=0x3 & bow=0x1 { export 8:1; } # Constant +XSRC_B_AS: "#0" is src16_8_4=0x3 & as=0x0 & bow=0x1 { export 0:1; } # Constant +XSRC_B_AS: "#1" is src16_8_4=0x3 & as=0x1 & bow=0x1 { export 1:1; } # Constant +XSRC_B_AS: "#2" is src16_8_4=0x3 & as=0x2 & bow=0x1 { export 2:1; } # Constant +XSRC_B_AS: "#-1" is src16_8_4=0x3 & as=0x3 & bow=0x1 { export 0xff:1; } # Constant + +XRSRC_B_AS: SRC8_8_4 is SRC8_8_4 & as=0x0 & bow=0x1 { export SRC8_8_4;} # Word/Register Direct (Rn): +XRSRC_B_AS: "@"^src_InDirect16_8_4 is src_InDirect16_8_4 & as=0x2 & bow=0x1 {export *:1 src_InDirect16_8_4;} # Word/Register Indirect (@Rn): +XRSRC_B_AS: "@"^src_InDirect16_8_4^"+" is src_InDirect16_8_4 & as=0x3 & bow=0x1 {export *:1 src_InDirect16_8_4;} # Word/Register Indirect Autoincrement (@Rn+): +XRSRC_B_AS: "#4" is src16_8_4=0x2 & as=0x2 & bow=0x1 { export 4:1; } # Constant +XRSRC_B_AS: "#8" is src16_8_4=0x2 & as=0x3 & bow=0x1 { export 8:1; } # Constant +XRSRC_B_AS: "#0" is src16_8_4=0x3 & as=0x0 & bow=0x1 { export 0:1; } # Constant +XRSRC_B_AS: "#1" is src16_8_4=0x3 & as=0x1 & bow=0x1 { export 1:1; } # Constant +XRSRC_B_AS: "#2" is src16_8_4=0x3 & as=0x2 & bow=0x1 { export 2:1; } # Constant +XRSRC_B_AS: "#-1" is src16_8_4=0x3 & as=0x3 & bow=0x1 { export 0xff:1; } # Constant + + +XSRC_W_AS: SRC16_8_4 is SRC16_8_4 & as=0x0 & bow=0x0 {export SRC16_8_4;} # Word/Register Direct (Rn): +XSRC_W_AS: ImmS20Src^"("^src_Indexed16_8_4^")" is src_Indexed16_8_4 & as=0x1 & bow=0x0 ; ImmS20Src {tmp:$(REG_SIZE) = src_Indexed16_8_4 + ImmS20Src; export *:2 tmp;} +XSRC_W_AS: "@"^src_InDirect16_8_4 is src_InDirect16_8_4 & as=0x2 & bow=0x0 {export *:2 src_InDirect16_8_4;} # Word/Register Indirect (@Rn): +XSRC_W_AS: "@"^src_InDirect16_8_4^"+" is src_InDirect16_8_4 & as=0x3 & bow=0x0 {export *:2 src_InDirect16_8_4;} # Word/Register Indirect Autoincrement (@Rn+): +XSRC_W_AS: Label20Src is src16_8_4=0x0 & as=0x1 & bow=0x0 ; Label20Src {export *:2 Label20Src; } # Symbolic +XSRC_W_AS: "#"^ImmS20Src is src16_8_4=0x0 & as=0x3 & bow=0x0 ; ImmS20Src {export *[const]:2 ImmS20Src; } # Immediate +XSRC_W_AS: "&"^Imm20Src is src16_8_4=0x2 & as=0x1 & bow=0x0 ; Imm20Src {export *:2 Imm20Src; } # Absolute +XSRC_W_AS: "#4" is src16_8_4=0x2 & as=0x2 & bow=0x0 { export 4:2; } # Constant +XSRC_W_AS: "#8" is src16_8_4=0x2 & as=0x3 & bow=0x0 { export 8:2; } # Constant +XSRC_W_AS: "#0" is src16_8_4=0x3 & as=0x0 & bow=0x0 { export 0:2; } # Constant +XSRC_W_AS: "#1" is src16_8_4=0x3 & as=0x1 & bow=0x0 { export 1:2; } # Constant +XSRC_W_AS: "#2" is src16_8_4=0x3 & as=0x2 & bow=0x0 { export 2:2; } # Constant +XSRC_W_AS: "#-1" is src16_8_4=0x3 & as=0x3 & bow=0x0 { export 0xffff:2; } # Constant + +XRSRC_W_AS: SRC16_8_4 is SRC16_8_4 & as=0x0 & bow=0x0 {export SRC16_8_4;} # Word/Register Direct (Rn): +XRSRC_W_AS: "@"^src_InDirect16_8_4 is src_InDirect16_8_4 & as=0x2 & bow=0x0 {export *:2 src_InDirect16_8_4;} # Word/Register Indirect (@Rn): +XRSRC_W_AS: "@"^src_InDirect16_8_4^"+" is src_InDirect16_8_4 & as=0x3 & bow=0x0 {export *:2 src_InDirect16_8_4;} # Word/Register Indirect Autoincrement (@Rn+): +XRSRC_W_AS: "#4" is src16_8_4=0x2 & as=0x2 & bow=0x0 { export 4:2; } # Constant +XRSRC_W_AS: "#8" is src16_8_4=0x2 & as=0x3 & bow=0x0 { export 8:2; } # Constant +XRSRC_W_AS: "#0" is src16_8_4=0x3 & as=0x0 & bow=0x0 { export 0:2; } # Constant +XRSRC_W_AS: "#1" is src16_8_4=0x3 & as=0x1 & bow=0x0 { export 1:2; } # Constant +XRSRC_W_AS: "#2" is src16_8_4=0x3 & as=0x2 & bow=0x0 { export 2:2; } # Constant +XRSRC_W_AS: "#-1" is src16_8_4=0x3 & as=0x3 & bow=0x0 { export 0xffff:2; } # Constant + +XSRC_A_AS: src_8_4 is src_8_4 & as=0x0 & bow=0x1 { export src_8_4;} # Word/Register Direct (Rn): +XSRC_A_AS: ImmS20Src^"("^src_Indexed16_8_4^")" is src_Indexed16_8_4 & as=0x1 & bow=0x1 ; ImmS20Src {tmp:$(REG_SIZE) = src_Indexed16_8_4 + ImmS20Src; export *:$(REG_SIZE) tmp;} +XSRC_A_AS: "@"^src_InDirect16_8_4 is src_InDirect16_8_4 & as=0x2 & bow=0x1 {export *:$(REG_SIZE) src_InDirect16_8_4;} # Word/Register Indirect (@Rn): +XSRC_A_AS: "@"^src_InDirect16_8_4^"+" is src_InDirect16_8_4 & as=0x3 & bow=0x1 {export *:$(REG_SIZE) src_InDirect16_8_4;} # Word/Register Indirect Autoincrement (@Rn+): +XSRC_A_AS: Label20Src is src16_8_4=0x0 & as=0x1 & bow=0x1 ; Label20Src {export *:$(REG_SIZE) Label20Src; } # Symbolic +XSRC_A_AS: "#"^ImmS20Src is src16_8_4=0x0 & as=0x3 & bow=0x1 ; ImmS20Src {export *[const]:$(REG_SIZE) ImmS20Src; } # Immediate +XSRC_A_AS: "&"^Imm20Src is src16_8_4=0x2 & as=0x1 & bow=0x1 ; Imm20Src {export *:$(REG_SIZE) Imm20Src; } # Absolute +XSRC_A_AS: "#4" is src16_8_4=0x2 & as=0x2 & bow=0x1 { export 4:$(REG_SIZE); } # Constant +XSRC_A_AS: "#8" is src16_8_4=0x2 & as=0x3 & bow=0x1 { export 8:$(REG_SIZE); } # Constant +XSRC_A_AS: "#0" is src16_8_4=0x3 & as=0x0 & bow=0x1 { export 0:$(REG_SIZE); } # Constant +XSRC_A_AS: "#1" is src16_8_4=0x3 & as=0x1 & bow=0x1 { export 1:$(REG_SIZE); } # Constant +XSRC_A_AS: "#2" is src16_8_4=0x3 & as=0x2 & bow=0x1 { export 2:$(REG_SIZE); } # Constant +XSRC_A_AS: "#-1" is src16_8_4=0x3 & as=0x3 & bow=0x1 { export 0xffffffff:$(REG_SIZE); } # Constant + +XRSRC_A_AS: src_8_4 is src_8_4 & as=0x0 & bow=0x1 { export src_8_4;} # Word/Register Direct (Rn): +XRSRC_A_AS: "@"^src_InDirect16_8_4 is src_InDirect16_8_4 & as=0x2 & bow=0x1 {export *:$(REG_SIZE) src_InDirect16_8_4;} # Word/Register Indirect (@Rn): +XRSRC_A_AS: "@"^src_InDirect16_8_4^"+" is src_InDirect16_8_4 & as=0x3 & bow=0x1 {export *:$(REG_SIZE) src_InDirect16_8_4;} # Word/Register Indirect Autoincrement (@Rn+): +XRSRC_A_AS: "#4" is src16_8_4=0x2 & as=0x2 & bow=0x1 { export 4:$(REG_SIZE); } # Constant +XRSRC_A_AS: "#8" is src16_8_4=0x2 & as=0x3 & bow=0x1 { export 8:$(REG_SIZE); } # Constant +XRSRC_A_AS: "#0" is src16_8_4=0x3 & as=0x0 & bow=0x1 { export 0:$(REG_SIZE); } # Constant +XRSRC_A_AS: "#1" is src16_8_4=0x3 & as=0x1 & bow=0x1 { export 1:$(REG_SIZE); } # Constant +XRSRC_A_AS: "#2" is src16_8_4=0x3 & as=0x2 & bow=0x1 { export 2:$(REG_SIZE); } # Constant +XRSRC_A_AS: "#-1" is src16_8_4=0x3 & as=0x3 & bow=0x1 { export 0xffffffff:$(REG_SIZE); } # Constant + +XDEST_B_AD: DST8_0_4 is DST8_0_4 & ad=0x0 & bow=0x1 + { export DST8_0_4; } # Word/Register Direct (Rn): +XDEST_B_AD: ImmS20Dst^"("^dest_Indexed16_0_4^")" is dest_Indexed16_0_4 & ad=0x1 & bow=0x1 ; ImmS20Dst + { tmp:$(REG_SIZE) = dest_Indexed16_0_4 + ImmS20Dst; export *:1 tmp;} +XDEST_B_AD: ImmS20Dst^"("^dest_Indexed16_0_4^")" is dest_Indexed16_0_4 & ad=0x1 & bow=0x1 & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; ImmS20Dst + { tmp:$(REG_SIZE) = dest_Indexed16_0_4 + ImmS20Dst; export *:1 tmp;} +XDEST_B_AD: ImmS20Dst^"("^dest_Indexed16_0_4^")" is dest_Indexed16_0_4 & ad=0x1 & bow=0x1 & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; ImmS20Dst + { tmp:$(REG_SIZE) = dest_Indexed16_0_4 + ImmS20Dst; export *:1 tmp;} +XDEST_B_AD: Label20Dst is dest=0x0 & ad=0x1 & bow=0x1 ; Label20Dst + { export *:1 Label20Dst; } # Symbolic +XDEST_B_AD: Label20DstExt is dest=0x0 & ad=0x1 & bow=0x1 & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; Label20DstExt + {export *:1 Label20DstExt; } # Symbolic +XDEST_B_AD: Label20DstExt is dest=0x0 & ad=0x1 & bow=0x1 & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; Label20DstExt + {export *:1 Label20DstExt; } # Symbolic +XDEST_B_AD: "&"^Imm20Dst is dest=0x2 & ad=0x1 & bow=0x1 ; Imm20Dst + {export *:1 Imm20Dst; } # Absolute +XDEST_B_AD: "&"^Imm20Dst is dest=0x2 & ad=0x1 & bow=0x1 & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; Imm20Dst + {export *:1 Imm20Dst; } # Absolute +XDEST_B_AD: "&"^Imm20Dst is dest=0x2 & ad=0x1 & bow=0x1 & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; Imm20Dst + {export *:1 Imm20Dst; } # Absolute + + +XDEST_W_AD: DST16_0_4 is DST16_0_4 & ad=0x0 & bow=0x0 + {export DST16_0_4;} # Word/Register Direct (Rn): +XDEST_W_AD: ImmS20Dst^"("^dest_Indexed16_0_4^")" is dest_Indexed16_0_4 & ad=0x1 & bow=0x0 ; ImmS20Dst + {tmp:$(REG_SIZE) = dest_Indexed16_0_4 + ImmS20Dst; export *:2 tmp;} +XDEST_W_AD: ImmS20Dst^"("^dest_Indexed16_0_4^")" is dest_Indexed16_0_4 & ad=0x1 & bow=0x0 & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; ImmS20Dst + {tmp:$(REG_SIZE) = dest_Indexed16_0_4 + ImmS20Dst; export *:2 tmp;} +XDEST_W_AD: ImmS20Dst^"("^dest_Indexed16_0_4^")" is dest_Indexed16_0_4 & ad=0x1 & bow=0x0 & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; ImmS20Dst + {tmp:$(REG_SIZE) = dest_Indexed16_0_4 + ImmS20Dst; export *:2 tmp;} +XDEST_W_AD: Label20Dst is dest=0x0 & ad=0x1 & bow=0x0 ; Label20Dst + {export *:2 Label20Dst; } # Symbolic +XDEST_W_AD: Label20DstExt is dest=0x0 & ad=0x1 & bow=0x0 & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; Label20DstExt + {export *:2 Label20DstExt; } # Symbolic +XDEST_W_AD: Label20DstExt is dest=0x0 & ad=0x1 & bow=0x0 & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; Label20DstExt + {export *:2 Label20DstExt; } # Symbolic +XDEST_W_AD: "&"^Imm20Dst is dest=0x2 & ad=0x1 & bow=0x0 ; Imm20Dst + {export *:2 Imm20Dst; } # Absolute +XDEST_W_AD: "&"^Imm20Dst is dest=0x2 & ad=0x1 & bow=0x0 & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; Imm20Dst + {export *:2 Imm20Dst; } # Absolute +XDEST_W_AD: "&"^Imm20Dst is dest=0x2 & ad=0x1 & bow=0x0 & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; Imm20Dst + {export *:2 Imm20Dst; } # Absolute + +XDEST_A_AD: dest_0_4 is dest_0_4 & ad=0x0 & bow=0x1 + { export dest_0_4; } # Word/Register Direct (Rn): +XDEST_A_AD: ImmS20Dst^"("^dest_Indexed16_0_4^")" is dest_Indexed16_0_4 & ad=0x1 & bow=0x1 ; ImmS20Dst + {tmp:$(REG_SIZE) = dest_Indexed16_0_4 + ImmS20Dst; export *:$(REG_SIZE) tmp;} +XDEST_A_AD: ImmS20Dst^"("^dest_Indexed16_0_4^")" is dest_Indexed16_0_4 & ad=0x1 & bow=0x1 & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; ImmS20Dst + {tmp:$(REG_SIZE) = dest_Indexed16_0_4 + ImmS20Dst; export *:$(REG_SIZE) tmp;} +XDEST_A_AD: ImmS20Dst^"("^dest_Indexed16_0_4^")" is dest_Indexed16_0_4 & ad=0x1 & bow=0x1 & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; ImmS20Dst + {tmp:$(REG_SIZE) = dest_Indexed16_0_4 + ImmS20Dst; export *:$(REG_SIZE) tmp;} +XDEST_A_AD: Label20Dst is dest=0x0 & ad=0x1 & bow=0x1 ; Label20Dst + {export *:$(REG_SIZE) Label20Dst; } # Symbolic +XDEST_A_AD: Label20DstExt is dest=0x0 & ad=0x1 & bow=0x1 & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ;Label20DstExt + {export *:$(REG_SIZE) Label20DstExt; } # Symbolic +XDEST_A_AD: Label20DstExt is dest=0x0 & ad=0x1 & bow=0x1 & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; Label20DstExt + {export *:$(REG_SIZE) Label20DstExt; } # Symbolic +XDEST_A_AD: "&"^Imm20Dst is dest=0x2 & ad=0x1 & bow=0x1 ; Imm20Dst + {export *:$(REG_SIZE) Imm20Dst; } # Absolute +XDEST_A_AD: "&"^Imm20Dst is dest=0x2 & ad=0x1 & bow=0x1 & as=0x1 & ((src16_8_4>=0x0 & src16_8_4<=0x2) | (src16_8_4>=0x4 & src16_8_4<=0xF)) ; indexExtWord16_0_16 ; Imm20Dst + {export *:$(REG_SIZE) Imm20Dst; } # Absolute +XDEST_A_AD: "&"^Imm20Dst is dest=0x2 & ad=0x1 & bow=0x1 & as=0x3 & src16_8_4=0x0 ; indexExtWord16_0_16 ; Imm20Dst + {export *:$(REG_SIZE) Imm20Dst; } # Absolute + +macro setaddflags(ans, in1, in2) +{ + tmp1:$(REG_SIZE) = zext(in1[0,20]); + tmp2:$(REG_SIZE) = zext(in2[0,20]); + tmp1 = tmp1 + tmp2; + $(CARRY) = tmp1 > 0xFFFFF; + $(OVERFLOW) = ((in1 s>= 0) && (in2 s>= 0) && (ans s< 0)) || ((in1 s< 0) && (in2 s< 0) && (ans s>= 0)); + $(SIGN) = (ans s< 0); + $(ZERO) = (ans == 0); +} + +macro setsubflags(ans, in1, in2) +{ + tmp1:$(REG_SIZE) = zext(in1[0,20]); + tmp2:$(REG_SIZE) = zext(in2[0,20]); + $(CARRY) = tmp1 <= tmp2; + $(OVERFLOW) = ((in1 s< 0) && (in2 s>= 0) && (ans s< 0)) || ((in1 s>= 0) && (in2 s< 0) && (ans s>= 0)); + $(SIGN) = (ans s< 0); + $(ZERO) = (ans == 0); + +} + +################# +# +# Subtables for the pushm/popm variants. +# In memory, the 20 bit regs take up 4 bytes with all the uppers being 0. +# However, to get some of the math to work, the 20bit regs are sign extended when reading from mem. + +PUSHAR0: is ctx_count=0 {} +PUSHAR0: is ctx_mreg=0x0 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 4; + *[RAM]:4 SP = inst_start & 0xFFFFF; +} + +PUSHAR1: is ctx_count=0 {} +PUSHAR1: is PUSHAR0 {build PUSHAR0;} +PUSHAR1: is ctx_mreg=0x1 & PUSHAR0 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 4; + *[RAM]:4 SP = SP & 0xFFFF; + build PUSHAR0; +} + +PUSHAR2: is ctx_count=0 {} +PUSHAR2: is PUSHAR1 {build PUSHAR1;} +PUSHAR2: is ctx_mreg=0x2 & PUSHAR1 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 4; + *[RAM]:4 SP = SR & 0xFFFF; + build PUSHAR1; +} + +PUSHAR3: is ctx_count=0 {} +PUSHAR3: is PUSHAR2 {build PUSHAR2;} +PUSHAR3: is ctx_mreg=0x3 & PUSHAR2 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 4; + *[RAM]:4 SP = R3 & 0xFFFFF; + build PUSHAR2; +} + +PUSHAR4: is ctx_count=0 {} +PUSHAR4: is PUSHAR3 {build PUSHAR3;} +PUSHAR4: is ctx_mreg=0x4 & PUSHAR3 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 4; + *[RAM]:4 SP = R4 & 0xFFFFF; + build PUSHAR3; +} + +PUSHAR5: is ctx_count=0 {} +PUSHAR5: is PUSHAR4 {build PUSHAR4;} +PUSHAR5: is ctx_mreg=0x5 & PUSHAR4 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 4; + *[RAM]:4 SP = R5 & 0xFFFFF; + build PUSHAR4; +} + +PUSHAR6: is ctx_count=0 {} +PUSHAR6: is PUSHAR5 {build PUSHAR5;} +PUSHAR6: is ctx_mreg=0x6 & PUSHAR5 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 4; + *[RAM]:4 SP = R6 & 0xFFFFF; + build PUSHAR5; +} + +PUSHAR7: is ctx_count=0 {} +PUSHAR7: is PUSHAR6 {build PUSHAR6;} +PUSHAR7: is ctx_mreg=0x7 & PUSHAR6 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 4; + *[RAM]:4 SP = R7 & 0xFFFFF; + build PUSHAR6; +} + +PUSHAR8: is ctx_count=0 {} +PUSHAR8: is PUSHAR7 {build PUSHAR7;} +PUSHAR8: is ctx_mreg=0x8 & PUSHAR7 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 4; + *[RAM]:4 SP = R8 & 0xFFFFF; + build PUSHAR7; +} + +PUSHAR9: is ctx_count=0 {} +PUSHAR9: is PUSHAR8 {build PUSHAR8;} +PUSHAR9: is ctx_mreg=0x9 & PUSHAR8 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 4; + *[RAM]:4 SP = R9 & 0xFFFFF; + build PUSHAR8; +} + +PUSHAR10: is ctx_count=0 {} +PUSHAR10: is PUSHAR9 {build PUSHAR9;} +PUSHAR10: is ctx_mreg=0xA & PUSHAR9 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 4; + *[RAM]:4 SP = R10 & 0xFFFFF; + build PUSHAR9; +} + +PUSHAR11: is ctx_count=0 {} +PUSHAR11: is PUSHAR10 {build PUSHAR10;} +PUSHAR11: is ctx_mreg=0xB & PUSHAR10 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 4; + *[RAM]:4 SP = R11 & 0xFFFFF; + build PUSHAR10; +} + +PUSHAR12: is ctx_count=0 {} +PUSHAR12: is PUSHAR11 {build PUSHAR11;} +PUSHAR12: is ctx_mreg=0xC & PUSHAR11 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 4; + *[RAM]:4 SP = R12 & 0xFFFFF; + build PUSHAR11; +} + +PUSHAR13: is ctx_count=0 {} +PUSHAR13: is PUSHAR12 {build PUSHAR12;} +PUSHAR13: is ctx_mreg=0xD & PUSHAR12 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 4; + *[RAM]:4 SP = R13 & 0xFFFFF; + build PUSHAR12; +} + +PUSHAR14: is ctx_count=0 {} +PUSHAR14: is PUSHAR13 {build PUSHAR13;} +PUSHAR14: is ctx_mreg=0xE & PUSHAR13 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 4; + *[RAM]:4 SP = R14 & 0xFFFFF; + build PUSHAR13; +} + +PUSHAR15: is PUSHAR14 {build PUSHAR14;} +PUSHAR15: is ctx_mreg=0xF & PUSHAR14 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 4; + *[RAM]:4 SP = R15 & 0xFFFFF; + build PUSHAR14; +} + +PUSHWR0: is ctx_count=0 {} +PUSHWR0: is ctx_mreg=0x0 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 2; + *[RAM]:2 SP = inst_start & 0xFFFF; +} + +PUSHWR1: is ctx_count=0 {} +PUSHWR1: is PUSHWR0 {build PUSHWR0;} +PUSHWR1: is ctx_mreg=0x1 & PUSHWR0 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 2; + *[RAM]:2 SP = SP:2; + build PUSHWR0; +} + +PUSHWR2: is ctx_count=0 {} +PUSHWR2: is PUSHWR1 {build PUSHWR1;} +PUSHWR2: is ctx_mreg=0x2 & PUSHWR1 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 2; + *[RAM]:2 SP = SR:2; + build PUSHWR1; +} + +PUSHWR3: is ctx_count=0 {} +PUSHWR3: is PUSHWR2 {build PUSHWR2;} +PUSHWR3: is ctx_mreg=0x3 & PUSHWR2 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 2; + *[RAM]:2 SP = R3:2; + build PUSHWR2; +} + +PUSHWR4: is ctx_count=0 {} +PUSHWR4: is PUSHWR3 {build PUSHWR3;} +PUSHWR4: is ctx_mreg=0x4 & PUSHWR3 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 2; + *[RAM]:2 SP = R4:2; + build PUSHWR3; +} + +PUSHWR5: is ctx_count=0 {} +PUSHWR5: is PUSHWR4 {build PUSHWR4;} +PUSHWR5: is ctx_mreg=0x5 & PUSHWR4 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 2; + *[RAM]:2 SP = R5:2; + build PUSHWR4; +} + +PUSHWR6: is ctx_count=0 {} +PUSHWR6: is PUSHWR5 {build PUSHWR5;} +PUSHWR6: is ctx_mreg=0x6 & PUSHWR5 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 2; + *[RAM]:2 SP = R6:2; + build PUSHWR5; +} + +PUSHWR7: is ctx_count=0 {} +PUSHWR7: is PUSHWR6 {build PUSHWR6;} +PUSHWR7: is ctx_mreg=0x7 & PUSHWR6 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 2; + *[RAM]:2 SP = R7:2; + build PUSHWR6; +} + +PUSHWR8: is ctx_count=0 {} +PUSHWR8: is PUSHWR7 {build PUSHWR7;} +PUSHWR8: is ctx_mreg=0x8 & PUSHWR7 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 2; + *[RAM]:2 SP = R8:2; + build PUSHWR7; +} + +PUSHWR9: is ctx_count=0 {} +PUSHWR9: is PUSHWR8 {build PUSHWR8;} +PUSHWR9: is ctx_mreg=0x9 & PUSHWR8 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 2; + *[RAM]:2 SP = R9:2; + build PUSHWR8; +} + +PUSHWR10: is ctx_count=0 {} +PUSHWR10: is PUSHWR9 {build PUSHWR9;} +PUSHWR10: is ctx_mreg=0xA & PUSHWR9 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 2; + *[RAM]:2 SP = R10:2; + build PUSHWR9; +} + +PUSHWR11: is ctx_count=0 {} +PUSHWR11: is PUSHWR10 {build PUSHWR10;} +PUSHWR11: is ctx_mreg=0xB & PUSHWR10 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 2; + *[RAM]:2 SP = R11:2; + build PUSHWR10; +} + +PUSHWR12: is ctx_count=0 {} +PUSHWR12: is PUSHWR11 {build PUSHWR11;} +PUSHWR12: is ctx_mreg=0xC & PUSHWR11 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 2; + *[RAM]:2 SP = R12:2; + build PUSHWR11; +} + +PUSHWR13: is ctx_count=0 {} +PUSHWR13: is PUSHWR12 {build PUSHWR12;} +PUSHWR13: is ctx_mreg=0xD & PUSHWR12 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 2; + *[RAM]:2 SP = R13:2; + build PUSHWR12; +} + +PUSHWR14: is ctx_count=0 {} +PUSHWR14: is PUSHWR13 {build PUSHWR13;} +PUSHWR14: is ctx_mreg=0xE & PUSHWR13 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 2; + *[RAM]:2 SP = R14:2; + build PUSHWR13; +} + +PUSHWR15: is PUSHWR14 {build PUSHWR14;} +PUSHWR15: is ctx_mreg=0xF & PUSHWR14 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg-1;] { + SP = SP - 2; + *[RAM]:2 SP = R15:2; + build PUSHWR14; +} + +POPAR15: is ctx_count=0 {} +POPAR15: is ctx_mreg=0xF { + R15 = *[RAM]:4 SP; + R15 = sext(R15[0,20]); + SP = SP + 4; +} + +POPAR14: is ctx_count=0 {} +POPAR14: is POPAR15 {build POPAR15;} +POPAR14: is ctx_mreg=0xE & POPAR15 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + R14 = *[RAM]:4 SP; + R14 = sext(R14[0,20]); + SP = SP + 4; + build POPAR15; +} + +POPAR13: is ctx_count=0 {} +POPAR13: is POPAR14 {build POPAR14;} +POPAR13: is ctx_mreg=0xD & POPAR14 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + R13 = *[RAM]:4 SP; + R13 = sext(R13[0,20]); + SP = SP + 4; + build POPAR14; +} + +POPAR12: is ctx_count=0 {} +POPAR12: is POPAR13 {build POPAR13;} +POPAR12: is ctx_mreg=0xC & POPAR13 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + R12 = *[RAM]:4 SP; + R12 = sext(R12[0,20]); + SP = SP + 4; + build POPAR13; +} + +POPAR11: is ctx_count=0 {} +POPAR11: is POPAR12 {build POPAR12;} +POPAR11: is ctx_mreg=0xB & POPAR12 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + R11 = *[RAM]:4 SP; + R11 = sext(R11[0,20]); + SP = SP + 4; + build POPAR12; +} + +POPAR10: is ctx_count=0 {} +POPAR10: is POPAR11 {build POPAR11;} +POPAR10: is ctx_mreg=0xA & POPAR11 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + R10 = *[RAM]:4 SP; + R10 = sext(R10[0,20]); + SP = SP + 4; + build POPAR11; +} + +POPAR9: is ctx_count=0 {} +POPAR9: is POPAR10 {build POPAR10;} +POPAR9: is ctx_mreg=0x9 & POPAR10 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + R9 = *[RAM]:4 SP; + R9 = sext(R9[0,20]); + SP = SP + 4; + build POPAR10; +} + +POPAR8: is ctx_count=0 {} +POPAR8: is POPAR9 {build POPAR9;} +POPAR8: is ctx_mreg=0x8 & POPAR9 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + R8 = *[RAM]:4 SP; + R8 = sext(R8[0,20]); + SP = SP + 4; + build POPAR9; +} + +POPAR7: is ctx_count=0 {} +POPAR7: is POPAR8 {build POPAR8;} +POPAR7: is ctx_mreg=0x7 & POPAR8 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + R7 = *[RAM]:4 SP; + R7 = sext(R7[0,20]); + SP = SP + 4; + build POPAR8; +} + +POPAR6: is ctx_count=0 {} +POPAR6: is POPAR7 {build POPAR7;} +POPAR6: is ctx_mreg=0x6 & POPAR7 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + R6 = *[RAM]:4 SP; + R6 = sext(R6[0,20]); + SP = SP + 4; + build POPAR7; +} + +POPAR5: is ctx_count=0 {} +POPAR5: is POPAR6 {build POPAR6;} +POPAR5: is ctx_mreg=0x5 & POPAR6 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + R5 = *[RAM]:4 SP; + R5 = sext(R5[0,20]); + SP = SP + 4; + build POPAR6; +} + +POPAR4: is ctx_count=0 {} +POPAR4: is POPAR5 {build POPAR5;} +POPAR4: is ctx_mreg=0x4 & POPAR5 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + R4 = *[RAM]:4 SP; + R4 = sext(R4[0,20]); + SP = SP + 4; + build POPAR5; +} + +POPAR3: is ctx_count=0 {} +POPAR3: is POPAR4 {build POPAR4;} +POPAR3: is ctx_mreg=0x3 & POPAR4 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + R3 = *[RAM]:4 SP; + R3 = sext(R3[0,20]); + SP = SP + 4; + build POPAR4; +} + +POPAR2: is ctx_count=0 {} +POPAR2: is POPAR3 {build POPAR3;} +POPAR2: is ctx_mreg=0x2 & POPAR3 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + SR = *[RAM]:4 SP; + SP = SP + 4; + build POPAR3; +} + +POPAR1: is ctx_count=0 {} +POPAR1: is POPAR2 {build POPAR2;} +POPAR1: is ctx_mreg=0x1 & POPAR2 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + SP = *[RAM]:4 SP; + SP = sext(SP[0,20]); + SP = SP + 4; + build POPAR2; +} + +POPAR0: is POPAR1 {build POPAR1;} +POPAR0: is ctx_mreg=0x0 & POPAR1 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + PC = *[RAM]:4 SP; + PC = sext(PC[0,20]); + SP = SP + 4; + build POPAR1; + goto [PC]; +} + +POPWR15: is ctx_count=0 {} +POPWR15: is ctx_mreg=0xF { + R15 = zext(*[RAM]:2 SP); + SP = SP + 2; +} + +POPWR14: is ctx_count=0 {} +POPWR14: is POPWR15 {build POPWR15;} +POPWR14: is ctx_mreg=0xE & POPWR15 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + R14 = zext(*[RAM]:2 SP); + SP = SP + 2; + build POPWR15; +} + +POPWR13: is ctx_count=0 {} +POPWR13: is POPWR14 {build POPWR14;} +POPWR13: is ctx_mreg=0xD & POPWR14 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + R13 = zext(*[RAM]:2 SP); + SP = SP + 2; + build POPWR14; +} + +POPWR12: is ctx_count=0 {} +POPWR12: is POPWR13 {build POPWR13;} +POPWR12: is ctx_mreg=0xC & POPWR13 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + R12 = zext(*[RAM]:2 SP); + SP = SP + 2; + build POPWR13; +} + +POPWR11: is ctx_count=0 {} +POPWR11: is POPWR12 {build POPWR12;} +POPWR11: is ctx_mreg=0xB & POPWR12 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + R11 = zext(*[RAM]:2 SP); + SP = SP + 2; + build POPWR12; +} + +POPWR10: is ctx_count=0 {} +POPWR10: is POPWR11 {build POPWR11;} +POPWR10: is ctx_mreg=0xA & POPWR11 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + R10 = zext(*[RAM]:2 SP); + SP = SP + 2; + build POPWR11; +} + +POPWR9: is ctx_count=0 {} +POPWR9: is POPWR10 {build POPWR10;} +POPWR9: is ctx_mreg=0x9 & POPWR10 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + R9 = zext(*[RAM]:2 SP); + SP = SP + 2; + build POPWR10; +} + +POPWR8: is ctx_count=0 {} +POPWR8: is POPWR9 {build POPWR9;} +POPWR8: is ctx_mreg=0x8 & POPWR9 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + R8 = zext(*[RAM]:2 SP); + SP = SP + 2; + build POPWR9; +} + +POPWR7: is ctx_count=0 {} +POPWR7: is POPWR8 {build POPWR8;} +POPWR7: is ctx_mreg=0x7 & POPWR8 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + R7 = zext(*[RAM]:2 SP); + SP = SP + 2; + build POPWR8; +} + +POPWR6: is ctx_count=0 {} +POPWR6: is POPWR7 {build POPWR7;} +POPWR6: is ctx_mreg=0x6 & POPWR7 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + R6 = zext(*[RAM]:2 SP); + SP = SP + 2; + build POPWR7; +} + +POPWR5: is ctx_count=0 {} +POPWR5: is POPWR6 {build POPWR6;} +POPWR5: is ctx_mreg=0x5 & POPWR6 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + R5 = zext(*[RAM]:2 SP); + SP = SP + 2; + build POPWR6; +} + +POPWR4: is ctx_count=0 {} +POPWR4: is POPWR5 {build POPWR5;} +POPWR4: is ctx_mreg=0x4 & POPWR5 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + R4 = zext(*[RAM]:2 SP); + SP = SP + 2; + build POPWR5; +} + +POPWR3: is ctx_count=0 {} +POPWR3: is POPWR4 {build POPWR4;} +POPWR3: is ctx_mreg=0x3 & POPWR4 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + R3 = zext(*[RAM]:2 SP); + SP = SP + 2; + build POPWR4; +} + +POPWR2: is ctx_count=0 {} +POPWR2: is POPWR3 {build POPWR3;} +POPWR2: is ctx_mreg=0x2 & POPWR3 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + SR = zext(*[RAM]:2 SP); + SP = SP + 2; + build POPWR3; +} + +POPWR1: is ctx_count=0 {} +POPWR1: is POPWR2 {build POPWR2;} +POPWR1: is ctx_mreg=0x1 & POPWR2 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + SP = zext(*[RAM]:2 SP); + SP = SP + 2; + build POPWR2; +} + +POPWR0: is POPWR1 {build POPWR1;} +POPWR0: is ctx_mreg=0x0 & POPWR1 [ctx_count=ctx_count-1; ctx_mreg=ctx_mreg+1;] { + PC = zext(*[RAM]:2 SP); + SP = SP + 2; + build POPWR1; + goto [PC]; +} + +macro adda(dst, src) { + tmpd:$(REG_SIZE) = dst; + tmp:$(REG_SIZE) = src + dst; + dst = sext(tmp[0,20]); + + setaddflags(dst,src,tmpd); +} + +:ADDA src_8_4, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0xE & src_8_4 & dest_0_4 { + adda(dest_0_4,src_8_4); +} + +:ADDA src_8_4, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0xE & src_8_4 & dest_0_4 & dest_0_4=0x0 { + tmpd:$(REG_SIZE) = inst_start + 2; + tmp:$(REG_SIZE) = src_8_4 + tmpd; + PC = sext(tmp[0,20]); + + setaddflags(dest_0_4,src_8_4,tmpd); + goto [PC]; +} + +:ADDA src_8_4, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0xE & src_8_4 & src_8_4=0x0 & dest_0_4 { + tmpd:$(REG_SIZE) = dest_0_4; + tmps:$(REG_SIZE) = inst_start + 2; + tmp:$(REG_SIZE) = tmps + dest_0_4; + dest_0_4 = sext(tmp[0,20]); + + setaddflags(dest_0_4,tmps,tmpd); +} + +# `ADDA SR, `, verified with hardware but not in spec. +:ADDA "#"^4, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0xE & src_8_4=0x2 & dest_0_4 { + adda(dest_0_4, 4:$(REG_SIZE)); +} + +:INCDA dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0xE & src_8_4=0x3 & dest_0_4 { + adda(dest_0_4, 2:$(REG_SIZE)); +} + +:ADDA "#"^Abs20s, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0xA & imm_8_4 & dest_0_4 ; Abs20s [ctx_ctregdest=imm_8_4;] { + tmpd:$(REG_SIZE) = dest_0_4; + tmps:$(REG_SIZE) = sext(Abs20s); + tmp:$(REG_SIZE) = tmpd + tmps; + dest_0_4 = sext(tmp[0,20]); + + setaddflags(dest_0_4,tmps,tmpd); +} + +:ADDA "#"^Abs20s, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0xA & imm_8_4 & dest_0_4 & dest_0_4=0x0; Abs20s [ctx_ctregdest=imm_8_4;] { + tmpd:$(REG_SIZE) = inst_start + 2; + tmps:$(REG_SIZE) = sext(Abs20s); + tmp:$(REG_SIZE) = tmpd + tmps; + PC = sext(tmp[0,20]); + + setaddflags(PC,tmps,tmpd); + goto [PC]; +} + +:CMPA src_8_4, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0xD & src_8_4 & dest_0_4 { + tmp:$(REG_SIZE) = dest_0_4 - src_8_4; + tmpd:$(REG_SIZE) = sext(tmp[0,20]); + setsubflags(tmpd,src_8_4,dest_0_4); +} + +:CMPA "#"^Abs20s, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0x9 & imm_8_4 & dest_0_4 ; Abs20s [ctx_ctregdest=imm_8_4;] { + tmps:$(REG_SIZE) = sext(Abs20s); + tmp:$(REG_SIZE) = dest_0_4 - tmps; + tmpd:$(REG_SIZE) = sext(tmp[0,20]); + setsubflags(tmpd,tmps,dest_0_4); +} + +:MOVA "@"^src_8_4, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0x0 & src_8_4 & dest_0_4 { + dest_0_4 = *[RAM]:$(REG_SIZE) src_8_4; + dest_0_4 = sext(dest_0_4[0,20]); +} + +:MOVA "@"^src_8_4^"+", dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0x1 & src_8_4 & dest_0_4 { + dest_0_4 = *[RAM]:$(REG_SIZE) src_8_4; + dest_0_4 = sext(dest_0_4[0,20]); + src_8_4 = src_8_4 + 4; +} + +:MOVA "&"^Abs20, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0x2 & imm_8_4 & dest_0_4 ; Abs20 [ctx_ctregdest=imm_8_4;] { + tmp:$(REG_SIZE) = zext(Abs20); + dest_0_4 = *[RAM]:$(REG_SIZE) tmp; + dest_0_4 = sext(dest_0_4[0,20]); +} + +:MOVA imms_0_16^"("^src_8_4^")", dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0x3 & src_8_4 & dest_0_4 ; imms_0_16 { + tmp:$(REG_SIZE) = src_8_4 + sext(imms_0_16:2); + dest_0_4 = *[RAM]:$(REG_SIZE) tmp; + dest_0_4 = sext(dest_0_4[0,20]); +} + +:MOVA src_8_4, "&"^Abs20 is ctx_haveext=0 & op16_12_4=0 & insid=0x6 & imm_0_4 & src_8_4 ; Abs20 [ctx_ctregdest=imm_0_4;] { + tmp:$(REG_SIZE) = zext(Abs20); + *[RAM]:$(REG_SIZE) tmp = src_8_4 & 0xFFFFF; +} + +:MOVA src_8_4, imms_0_16^"("^dest_0_4^")" is ctx_haveext=0 & op16_12_4=0 & insid=0x7 & src_8_4 & dest_0_4 ; imms_0_16 { + tmp:$(REG_SIZE) = dest_0_4 + sext(imms_0_16:2); + *[RAM]:$(REG_SIZE) tmp = src_8_4 & 0xFFFFF; +} + +:MOVA "#"^Abs20s, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0x8 & imm_8_4 & dest_0_4 ; Abs20s [ctx_ctregdest=imm_8_4;] { + dest_0_4 = sext(Abs20s); +} + +:MOVA src_8_4, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0xC & src_8_4 & dest_0_4 { + dest_0_4 = src_8_4; +} + +:CLRA dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0xC & src_8_4=0x3 & dest_0_4 { + dest_0_4 = 0:$(REG_SIZE); +} + +macro suba(dst, src) { + tmpd:$(REG_SIZE) = dst; + tmp:$(REG_SIZE) = dst - src; + dst = sext(tmp[0,20]); + + setsubflags(dst,src,tmpd); +} + +:SUBA src_8_4, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0xF & src_8_4 & dest_0_4 { + suba(dest_0_4, src_8_4); +} + +:SUBA src_8_4, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0xF & src_8_4 & dest_0_4 & dest_0_4=0x0 { + tmpd:$(REG_SIZE) = inst_start + 2; + tmp:$(REG_SIZE) = tmpd - src_8_4; + PC = sext(tmp[0,20]); + + setsubflags(dest_0_4,src_8_4,tmpd); + goto [PC]; +} + +:SUBA src_8_4, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0xF & src_8_4 & src_8_4=0x0 & dest_0_4 { + tmpd:$(REG_SIZE) = dest_0_4; + tmps:$(REG_SIZE) = inst_start + 2; + tmp:$(REG_SIZE) = dest_0_4 - tmps; + dest_0_4 = sext(tmp[0,20]); + + setsubflags(dest_0_4,tmps,tmpd); +} + +:SUBA "#"^Abs20s, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0xB & imm_8_4 & dest_0_4 ; Abs20s [ctx_ctregdest=imm_8_4;] { + tmpd:$(REG_SIZE) = dest_0_4; + tmps:$(REG_SIZE) = sext(Abs20s); + tmp:$(REG_SIZE) = dest_0_4 - tmps; + dest_0_4 = sext(tmp[0,20]); + + setsubflags(dest_0_4,tmps,tmpd); +} + +:SUBA "#"^Abs20s, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0xB & imm_8_4 & dest_0_4 & dest_0_4=0x0; Abs20s [ctx_ctregdest=imm_8_4;] { + tmpd:$(REG_SIZE) = inst_start + 2; + tmps:$(REG_SIZE) = sext(Abs20s); + tmp:$(REG_SIZE) = tmpd - tmps; + PC = sext(tmp[0,20]); + + setsubflags(PC,tmps,tmpd); + goto [PC]; +} + +################## +# +# Special cases of renamed MOVA where PC is involved + +# This first case doesn't make any sense, but I saw it in the cunits. The instruction word is all 0. +# The toolchain comes back with a 'beq', but that doesn't make sense either as there is no beq instruction +# anywhere in the manual. One toolchain allows BRA @PC, another one doesn't. I did find reference to gvv +# assembler extension regarding @rN being treated as 0(rN) and vice versa. That would effectively turn +# this into a branch to following instruction. What I think may be happening is a compiler bug where in +# some cases an immediate gets output even though the constant generator is used. +:BRA "@"^src_8_4 is ctx_haveext=0 & op16_12_4=0 & insid=0x0 & src_8_4 & src_8_4=0 & dest_0_4=0x0 { +} + +:BRA "@"^src_8_4 is ctx_haveext=0 & op16_12_4=0 & insid=0x0 & src_8_4 & dest_0_4=0x0 { + PC = *[RAM]:$(REG_SIZE) src_8_4; + PC = sext(PC[0,20]); + goto [PC]; +} + +:BRA "@"^src_8_4^"+" is ctx_haveext=0 & op16_12_4=0 & insid=0x1 & src_8_4 & dest_0_4=0x0 { + PC = *[RAM]:$(REG_SIZE) src_8_4; + PC = sext(PC[0,20]); + src_8_4 = src_8_4 + 4; + goto [PC]; +} + +:BRA "&"^Abs20 is ctx_haveext=0 & op16_12_4=0 & insid=0x2 & imm_8_4 & dest_0_4=0x0; Abs20 [ctx_ctregdest=imm_8_4;] { + tmp:$(REG_SIZE) = zext(Abs20); + PC = *[RAM]:$(REG_SIZE) tmp; + PC = sext(PC[0,20]); + goto [PC]; +} + +:BRA imms_0_16^"("^src_8_4^")" is ctx_haveext=0 & op16_12_4=0 & insid=0x3 & src_8_4 & dest_0_4=0x0; imms_0_16 { + tmp:$(REG_SIZE) = src_8_4 + sext(imms_0_16:2); + PC = *[RAM]:$(REG_SIZE) tmp; + PC = sext(PC[0,20]); + goto [PC]; +} + +:BRA "#"^Abs20add is ctx_haveext=0 & op16_12_4=0 & insid=0x8 & imm_8_4 & dest_0_4=0x0; Abs20add [ctx_ctregdest=imm_8_4;] { +# PC = Abs20add; + goto Abs20add; +} + +:BRA src_8_4 is ctx_haveext=0 & op16_12_4=0 & insid=0xC & src_8_4 & dest_0_4=0x0 { + PC = src_8_4; + goto [PC]; +} + +:RETA "@"^src_8_4^"+" is ctx_haveext=0 & op16_12_4=0 & insid=0x1 & src_8_4 & src_8_4=0x1 & dest_0_4=0x0 { + PC = *[RAM]:$(REG_SIZE) src_8_4; + PC = sext(PC[0,20]); + SP = SP + 4; + return [PC]; +} +# +################ +# +# Special cases of SUBA/ADDA/CMPA/MOVA + +# `SUBA SR, `, verified with hardware but not in spec. +:SUBA "#"^4, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0xF & src_8_4=0x2 & dest_0_4 { + suba(dest_0_4, 4:$(REG_SIZE)); +} + +:DECDA dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0xF & src_8_4=0x3 & dest_0_4 { + suba(dest_0_4, 2:$(REG_SIZE)); +} + +:DECDA dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0xB & imm_8_4=0x0 & dest_0_4 ; imm_0_16=0x0002 { + suba(dest_0_4, 2:$(REG_SIZE)); +} + +:INCDA dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0xA & imm_8_4=0x0 & dest_0_4 ; imm_0_16=0x0002 { + adda(dest_0_4, 2:$(REG_SIZE)); +} + +:TSTA dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0xD & src_8_4=0x3 & dest_0_4 { + $(CARRY) = 1; + $(OVERFLOW) = 0; + $(SIGN) = (dest_0_4 s< 0); + $(ZERO) = (dest_0_4 == 0); +} + +:TSTA dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0x9 & imm_8_4=0x0 & dest_0_4 ; imm_0_16=0x0000 { + $(CARRY) = 1; + $(OVERFLOW) = 0; + $(SIGN) = (dest_0_4 s< 0); + $(ZERO) = (dest_0_4 == 0); +} + +:CLRA dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insid=0x8 & imm_8_4=0 & dest_0_4 ; imm_0_16=0 { + dest_0_4 = 0; +} + +# +################ +# +# Other 20 bit address instructions +:CALLA dest_0_4 is ctx_haveext=0 & op16_8_8=0x13 & op16_4_4=0x4 & dest_0_4 { + SP = SP - 0x4; + *:4 SP = inst_next; + PC = dest_0_4; + call [PC]; +} + +:CALLA imms_0_16^"("^dest_0_4^")" is ctx_haveext=0 & op16_8_8=0x13 & op16_4_4=0x5 & dest_0_4 ; imms_0_16 { + SP = SP - 0x4; + *:4 SP = inst_next; + tmp:$(REG_SIZE) = dest_0_4 + sext(imms_0_16:2); + PC = *[RAM]:$(REG_SIZE) tmp; + PC = sext(PC[0,20]); + call [PC]; +} + +:CALLA "@"^dest_0_4 is ctx_haveext=0 & op16_8_8=0x13 & op16_4_4=0x6 & dest_0_4 { + SP = SP - 0x4; + *:4 SP = inst_next; + PC = *[RAM]:$(REG_SIZE) dest_0_4; + PC = sext(PC[0,20]); + call [PC]; +} + +:CALLA "@"^dest_0_4^"+" is ctx_haveext=0 & op16_8_8=0x13 & op16_4_4=0x7 & dest_0_4 { + SP = SP - 0x4; + *:4 SP = inst_next; + PC = *[RAM]:$(REG_SIZE) dest_0_4; + PC = sext(PC[0,20]); + dest_0_4 = dest_0_4 + 4; + call [PC]; +} + +:CALLA "&"^Abs20 is ctx_haveext=0 & op16_8_8=0x13 & op16_4_4=0x8 & imm_0_4; Abs20 [ctx_ctregdest=imm_0_4;] { + SP = SP - 0x4; + *:4 SP = inst_next; + tmp:$(REG_SIZE) = zext(Abs20); + PC = *[RAM]:$(REG_SIZE) tmp; + PC = sext(PC[0,20]); + call [PC]; +} + +:CALLA imms_0_16^"(PC)" is ctx_haveext=0 & op16_8_8=0x13 & op16_4_4=0x9 & imms_0_16 { + SP = SP - 0x4; + *:4 SP = inst_next; + tmp:$(REG_SIZE) = inst_start + sext(imms_0_16:2); + PC = *[RAM]:$(REG_SIZE) tmp; + PC = sext(PC[0,20]); + call [PC]; +} + +:CALLA "#"^Abs20add is ctx_haveext=0 & op16_8_8=0x13 & op16_4_4=0xB & imm_0_4; Abs20add [ctx_ctregdest = imm_0_4;] { + SP = SP - 0x4; + *:4 SP = inst_next; + PC = &Abs20add; + call Abs20add; +} + + +:PUSHM.A IMM4,dest_0_4 is ctx_haveext=0 & op16_8_8=0x14 & IMM4 & dest_0_4 & imm_4_4 & PUSHAR15 [ctx_count=imm_4_4+1; ctx_mreg=dest_0_4;] { + build IMM4; + build PUSHAR15; +} + +:PUSHM.W IMM4,dest_0_4 is ctx_haveext=0 & op16_8_8=0x15 & IMM4 & dest_0_4 & imm_4_4 & PUSHWR15 [ctx_count=imm_4_4+1; ctx_mreg=dest_0_4;] { + build IMM4; + build PUSHWR15; +} + +:POPM.A IMM4,ctx_popreg is ctx_haveext=0 & op16_8_8=0x16 & IMM4 & ctx_popreg & imm_0_4 & imm_4_4 & POPAR0 [ctx_popreg_set=imm_0_4+imm_4_4; ctx_count=imm_4_4+1; ctx_mreg=imm_0_4;] { + build IMM4; + build POPAR0; +} + +:POPM.W IMM4,ctx_popreg is ctx_haveext=0 & op16_8_8=0x17 & IMM4 & ctx_popreg & imm_0_4 & imm_4_4 & POPWR0 [ctx_popreg_set=imm_0_4+imm_4_4; ctx_count=imm_4_4+1; ctx_mreg=imm_0_4;] { + build IMM4; + build POPWR0; +} + +:RRCM.A NUM2, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insidbig=0x04 & NUM2 & dest_0_4 & rrn { + tmph:$(REG_SIZE) = (dest_0_4 >> rrn) & 0x1; + tmpc:$(REG_SIZE) = zext($(CARRY)); + tmpc = tmpc << (20-NUM2); + dest_0_4 = (dest_0_4 >> NUM2) | (dest_0_4 << (20-rrn)); + dest_0_4 = ((dest_0_4 & (~tmpc)) | tmpc) & 0xFFFFF; + $(CARRY) = (tmph != 0); + $(OVERFLOW) = 0; + $(SIGN) = (dest_0_4[19,1] != 0); + $(ZERO) = (dest_0_4 == 0); +} + +:RRAM.A NUM2, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insidbig=0x14 & NUM2 & dest_0_4 & rrn { + tmph:$(REG_SIZE) = (dest_0_4 >> rrn) & 0x1; + dest_0_4 = (dest_0_4 s>> NUM2); + $(CARRY) = (tmph != 0); + $(OVERFLOW) = 0; + $(SIGN) = (dest_0_4[19,1] != 0); + $(ZERO) = (dest_0_4 == 0); +} + +:RLAM.A NUM2, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insidbig=0x24 & NUM2 & dest_0_4 { + tmph:$(REG_SIZE) = (dest_0_4 >> (20 - NUM2)) & 0x1; + dest_0_4 = (dest_0_4 << NUM2); + dest_0_4 = sext(dest_0_4[0,20]); + $(CARRY) = (tmph != 0); + $(SIGN) = (dest_0_4[19,1] != 0); + $(ZERO) = (dest_0_4 == 0); +} + +:RRUM.A NUM2, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insidbig=0x34 & NUM2 & dest_0_4 & rrn { + tmph:$(REG_SIZE) = (dest_0_4 >> rrn) & 0x1; + dest_0_4 = (dest_0_4 >> NUM2) & 0xFFFFF; + $(CARRY) = (tmph != 0); + $(OVERFLOW) = 0; + $(SIGN) = 0; + $(ZERO) = (dest_0_4 == 0); +} + +:RRCM.W NUM2, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insidbig=0x05 & NUM2 & dest_0_4 & rrn { + tmpr:2 = dest_0_4:2; + tmph:2 = (tmpr >> rrn) & 0x1; + tmpc:2 = zext($(CARRY)); + tmpc = tmpc << (16-NUM2); + tmpr = (tmpr >> NUM2) | (tmpr << (16-rrn)); + dest_0_4 = zext((tmpr & (~tmpc)) | tmpc); + $(CARRY) = (tmph != 0); + $(OVERFLOW) = 0; + $(SIGN) = (dest_0_4[15,1] != 0); + $(ZERO) = (dest_0_4 == 0); +} + +:RRAM.W NUM2, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insidbig=0x15 & NUM2 & dest_0_4 & rrn { + tmpr:2 = dest_0_4:2; + tmph:$(REG_SIZE) = (dest_0_4 >> rrn) & 0x1; + dest_0_4 = zext(tmpr s>> NUM2); + $(CARRY) = (tmph != 0); + $(OVERFLOW) = 0; + $(SIGN) = (dest_0_4[19,1] != 0); + $(ZERO) = (dest_0_4 == 0); +} + +:RLAM.W NUM2, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insidbig=0x25 & NUM2 & dest_0_4 { + tmph:$(REG_SIZE) = (dest_0_4 >> (16 - NUM2)) & 0x1; + dest_0_4 = (dest_0_4 << NUM2); + dest_0_4 = zext(dest_0_4:2); + $(CARRY) = (tmph != 0); + $(SIGN) = (dest_0_4[19,1] != 0); + $(ZERO) = (dest_0_4 == 0); +} + +:RRUM.W NUM2, dest_0_4 is ctx_haveext=0 & op16_12_4=0 & insidbig=0x35 & NUM2 & dest_0_4 & rrn { + tmpr:2 = dest_0_4:2; + tmph:2 = (tmpr >> rrn) & 0x1; + dest_0_4 = zext(tmpr >> NUM2); + $(CARRY) = (tmph != 0); + $(OVERFLOW) = 0; + $(SIGN) = 0; + $(ZERO) = (dest_0_4 == 0); +} + +macro bzero(full, byte) +{ + ztmp:1 = byte; + full = 0; + byte = ztmp; +} + +macro wzero(full, word) +{ + ztmp:2 = word; + full = 0; + word = ztmp; +} + +############################## +# +# Extention word instructions +# +# The base msp430 handles all the addressing modes in subtables. +# The reg/reg mode for the 'X' instruction has repetition so we +# break that mode out separately. Because of that, we need to use +# separate subtables for the address modes since the base ones +# will hit on the reg/reg mode. +# +# There are also two groups for the extended instructions: +# double and single operand. The double operand ones come +# first. A lot of the singles are covered under the address +# extensions as they don't have the extension word. +############################# +# +# Double Operand +# +############################# +# Repeat enabled +:ADCX.B DST8_0_4 is ctx_haveext=4 & op16_12_4=0x6 & src16_8_4=0x3 & as=0x0 & bow=1 & ctx_al=1 & postIncrementStore & DST8_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + tmp_carry:1 = carry(DST8_0_4,$(CARRY)); #C Flag + $(OVERFLOW) = scarry(DST8_0_4,$(CARRY)); #V Flag + # Operation... + DST8_0_4 = DST8_0_4 + $(CARRY); + bzero(reg_Direct16_0_4,DST8_0_4); + # Result Flags... + $(CARRY) = tmp_carry; + $(SIGN) = (DST8_0_4 s< 0x0); # S Flag + $(ZERO) = (DST8_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:ADCX.W DST16_0_4 is ctx_haveext=4 & op16_12_4=0x6 & src16_8_4=0x3 & as=0x0 & bow=0 & ctx_al=1 & postIncrementStore & DST16_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + tmp_carry:1 = carry(DST16_0_4,zext($(CARRY))); #C Flag + $(OVERFLOW) = scarry(DST16_0_4,zext($(CARRY))); #V Flag + # Operation... + DST16_0_4 = DST16_0_4 + zext($(CARRY)); + wzero(reg_Direct16_0_4,DST16_0_4); + # Result Flags... + $(CARRY) = tmp_carry; + $(SIGN) = (DST16_0_4 s< 0x0); # S Flag + $(ZERO) = (DST16_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:ADCX.A dest_0_4 is ctx_haveext=4 & op16_12_4=0x6 & src16_8_4=0x3 & as=0x0 & bow=1 & ctx_al=0 & postIncrementStore & dest_0_4 { + + tmpd:$(REG_SIZE) = dest_0_4; + tmpc:$(REG_SIZE) = zext($(CARRY)); + tmp:$(REG_SIZE) = tmpc + dest_0_4; + dest_0_4 = sext(tmp[0,20]); + + setaddflags(dest_0_4,tmpc,tmpd); + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:ADDX.B XRSRC_B_AS, DST8_0_4 is ctx_haveext=4 & op16_12_4=0x5 & bow=1 & ctx_al=1 & postIncrementStore & XRSRC_B_AS & DST8_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + $(CARRY) = carry(XRSRC_B_AS, DST8_0_4); # C Flag + $(OVERFLOW) = scarry(XRSRC_B_AS, DST8_0_4); # V Flag + # Operation... + DST8_0_4 = XRSRC_B_AS + DST8_0_4; + bzero(reg_Direct16_0_4,DST8_0_4); + # Result Flags... + $(SIGN) = (DST8_0_4 s< 0x0); # S Flag + $(ZERO) = (DST8_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:ADDX.W XRSRC_W_AS, DST16_0_4 is ctx_haveext=4 & op16_12_4=0x5 & bow=0 & ctx_al=1 & postIncrementStore & XRSRC_W_AS & DST16_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + $(CARRY) = carry(XRSRC_W_AS, DST16_0_4); # C Flag + $(OVERFLOW) = scarry(XRSRC_W_AS, DST16_0_4); # V Flag + # Operation... + DST16_0_4 = XRSRC_W_AS + DST16_0_4; + wzero(reg_Direct16_0_4,DST16_0_4); + # Result Flags... + $(SIGN) = (DST16_0_4 s< 0x0); # S Flag + $(ZERO) = (DST16_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:ADDX.A XRSRC_A_AS, dest_0_4 is ctx_haveext=4 & op16_12_4=0x5 & bow=1 & ctx_al=0 & postIncrementStore & XRSRC_A_AS & dest_0_4 { + + tmpd:$(REG_SIZE) = dest_0_4; + tmp:$(REG_SIZE) = XRSRC_A_AS + dest_0_4; + dest_0_4 = sext(tmp[0,20]); + + setaddflags(dest_0_4,XRSRC_A_AS,tmpd); + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:ADDCX.B XRSRC_B_AS, DST8_0_4 is ctx_haveext=4 & op16_12_4=0x6 & bow=1 & ctx_al=1 & postIncrementStore & XRSRC_B_AS & DST8_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + tmp_carry:1 = (carry(XRSRC_B_AS, $(CARRY)) || carry(DST8_0_4,XRSRC_B_AS + $(CARRY))); #C Flag + $(OVERFLOW) = (scarry(XRSRC_B_AS, $(CARRY)) || scarry(DST8_0_4,XRSRC_B_AS + $(CARRY))); #V Flag + # Operation... + DST8_0_4 = XRSRC_B_AS + DST8_0_4 + $(CARRY); + bzero(reg_Direct16_0_4,DST8_0_4); + # Result Flags... + $(CARRY) = tmp_carry; + $(SIGN) = (DST8_0_4 s< 0x0); # S Flag + $(ZERO) = (DST8_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:ADDCX.W XRSRC_W_AS, DST16_0_4 is ctx_haveext=4 & op16_12_4=0x6 & bow=0 & ctx_al=1 & postIncrementStore & XRSRC_W_AS & DST16_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + tmp_carry:1 = (carry(XRSRC_W_AS,zext($(CARRY))) || carry(DST16_0_4,XRSRC_W_AS + zext($(CARRY)))); #C Flag + $(OVERFLOW) = (scarry(XRSRC_W_AS,zext($(CARRY))) || scarry(DST16_0_4,XRSRC_W_AS + zext($(CARRY)))); #V Flag + # Operation... + DST16_0_4 = XRSRC_W_AS + DST16_0_4 + zext($(CARRY)); + wzero(reg_Direct16_0_4,DST16_0_4); + # Result Flags... + $(CARRY) = tmp_carry; + $(SIGN) = (DST16_0_4 s< 0x0); # S Flag + $(ZERO) = (DST16_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:ADDCX.A XRSRC_A_AS, dest_0_4 is ctx_haveext=4 & op16_12_4=0x6 & bow=1 & ctx_al=0 & postIncrementStore & XRSRC_A_AS & dest_0_4 { + + tmpd:$(REG_SIZE) = dest_0_4; + tmps:$(REG_SIZE) = XRSRC_A_AS + zext($(CARRY)); + tmp:$(REG_SIZE) = tmps + dest_0_4; + dest_0_4 = sext(tmp[0,20]); + + setaddflags(dest_0_4,tmps,tmpd); + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:ANDX.B XRSRC_B_AS, DST8_0_4 is ctx_haveext=4 & op16_12_4=0xF & bow=1 & ctx_al=1 & postIncrementStore & XRSRC_B_AS & DST8_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag + # Operation... + DST8_0_4 = DST8_0_4 & XRSRC_B_AS; + bzero(reg_Direct16_0_4,DST8_0_4); + # Result Flags... + $(SIGN) = (DST8_0_4 s< 0x0); # S Flag + $(ZERO) = (DST8_0_4 == 0x0); # Z Flag + $(CARRY) = (DST8_0_4 != 0x0); # C Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:ANDX.W XRSRC_W_AS, DST16_0_4 is ctx_haveext=4 & op16_12_4=0xF & bow=0 & ctx_al=1 & postIncrementStore & XRSRC_W_AS & DST16_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag + # Operation... + DST16_0_4 = DST16_0_4 & XRSRC_W_AS; + wzero(reg_Direct16_0_4,DST16_0_4); + # Result Flags... + $(SIGN) = (DST16_0_4 s< 0x0); # S Flag + $(ZERO) = (DST16_0_4 == 0x0); # Z Flag + $(CARRY) = (DST16_0_4 != 0x0); # C Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:ANDX.A XRSRC_A_AS, dest_0_4 is ctx_haveext=4 & op16_12_4=0xF & bow=1 & ctx_al=0 & postIncrementStore & XRSRC_A_AS & dest_0_4 { + + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag + # Operation... + dest_0_4 = dest_0_4 & XRSRC_A_AS; + dest_0_4 = sext(dest_0_4[0,20]); + # Result Flags... + $(SIGN) = (dest_0_4 s< 0x0); # S Flag + $(ZERO) = (dest_0_4 == 0x0); # Z Flag + $(CARRY) = (dest_0_4 != 0x0); # C Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:BICX.B XRSRC_B_AS, DST8_0_4 is ctx_haveext=4 & op16_12_4=0xC & bow=1 & ctx_al=1 & postIncrementStore & XRSRC_B_AS & DST8_0_4 & reg_Direct16_0_4 { + + DST8_0_4 = (~XRSRC_B_AS) & DST8_0_4; + bzero(reg_Direct16_0_4,DST8_0_4); + #Status bits are not affected + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:BICX.W XRSRC_W_AS, DST16_0_4 is ctx_haveext=4 & op16_12_4=0xC & bow=0 & ctx_al=1 & postIncrementStore & XRSRC_W_AS & DST16_0_4 & reg_Direct16_0_4 { + + DST16_0_4 = (~XRSRC_W_AS) & DST16_0_4; + wzero(reg_Direct16_0_4,DST16_0_4); + #Status bits are not affected + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:BICX.A XRSRC_A_AS, dest_0_4 is ctx_haveext=4 & op16_12_4=0xC & bow=1 & ctx_al=0 & postIncrementStore & XRSRC_A_AS & dest_0_4 { + + dest_0_4 = (~XRSRC_A_AS) & dest_0_4; + dest_0_4 = zext(dest_0_4[0,20]); + #Status bits are not affected + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:BISX.B XRSRC_B_AS, DST8_0_4 is ctx_haveext=4 & op16_12_4=0xD & bow=1 & ctx_al=1 & postIncrementStore & XRSRC_B_AS & DST8_0_4 & reg_Direct16_0_4 { + + DST8_0_4 = XRSRC_B_AS | DST8_0_4; + bzero(reg_Direct16_0_4,DST8_0_4); + #Status bits are not affected + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:BISX.W XRSRC_W_AS, DST16_0_4 is ctx_haveext=4 & op16_12_4=0xD & bow=0 & ctx_al=1 & postIncrementStore & XRSRC_W_AS & DST16_0_4 & reg_Direct16_0_4 { + + DST16_0_4 = XRSRC_W_AS | DST16_0_4; + wzero(reg_Direct16_0_4,DST16_0_4); + #Status bits are not affected + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:BISX.A XRSRC_A_AS, dest_0_4 is ctx_haveext=4 & op16_12_4=0xD & bow=1 & ctx_al=0 & postIncrementStore & XRSRC_A_AS & dest_0_4 { + + dest_0_4 = XRSRC_A_AS | dest_0_4; + #Status bits are not affected + dest_0_4 = sext(dest_0_4[0,20]); + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:BITX.B XRSRC_B_AS, DST8_0_4 is ctx_haveext=4 & op16_12_4=0xB & bow=1 & ctx_al=1 & postIncrement & XRSRC_B_AS & DST8_0_4 { + + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag (reset) + # Operation... + result:1 = DST8_0_4 & XRSRC_B_AS; + # Result Flags... + $(CARRY) = (result != 0x0); # C Flag + $(SIGN) = (result s< 0x0); # S Flag + $(ZERO) = (result == 0x0); # Z Flag + build postIncrement; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:BITX.W XRSRC_W_AS, DST16_0_4 is ctx_haveext=4 & op16_12_4=0xB & bow=0 & ctx_al=1 & postIncrement & XRSRC_W_AS & DST16_0_4 { + + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag (reset) + # Operation... + result:2 = DST16_0_4 & XRSRC_W_AS; + # Result Flags... + $(CARRY) = (result != 0x0); # C Flag + $(SIGN) = (result s< 0x0); # S Flag + $(ZERO) = (result == 0x0); # Z Flag + build postIncrement; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:BITX.A XRSRC_A_AS, dest_0_4 is ctx_haveext=4 & op16_12_4=0xB & bow=1 & ctx_al=0 & postIncrement & XRSRC_A_AS & dest_0_4 { + + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag (reset) + # Operation... + result:$(REG_SIZE) = dest_0_4 & XRSRC_A_AS; + # Result Flags... + result = sext(result[0,20]); + $(CARRY) = (result != 0x0); # C Flag + $(SIGN) = (result s< 0x0); # S Flag + $(ZERO) = (result == 0x0); # Z Flag + build postIncrement; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:CLRX.B DST8_0_4 is ctx_haveext=4 & op16_12_4=0x4 & src16_8_4=0x3 & as=0x0 & bow=1 & ctx_al=1 & postIncrementStore & DST8_0_4 & reg_Direct16_0_4 { + + DST8_0_4 = 0; + bzero(reg_Direct16_0_4,DST8_0_4); + #Status bits are not affected + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:CLRX.W DST16_0_4 is ctx_haveext=4 & op16_12_4=0x4 & src16_8_4=0x3 & as=0x0 & bow=0 & ctx_al=1 & postIncrementStore & DST16_0_4 & reg_Direct16_0_4 { + + DST16_0_4 = 0; + wzero(reg_Direct16_0_4,DST16_0_4); + #Status bits are not affected + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:CLRX.A dest_0_4 is ctx_haveext=4 & op16_12_4=0x4 & src16_8_4=0x3 & as=0x0 & bow=1 & ctx_al=0 & postIncrementStore & dest_0_4 { + + dest_0_4 = 0; + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:CMPX.B XRSRC_B_AS, DST8_0_4 is ctx_haveext=4 & op16_12_4=0x9 & bow=1 & ctx_al=1 & postIncrement & XRSRC_B_AS & DST8_0_4 { + + # Operation Flags... + $(CARRY) = (XRSRC_B_AS <= DST8_0_4); # Carry is NOT set if there is a borrow + $(OVERFLOW) = sborrow(DST8_0_4, XRSRC_B_AS); # V Flag + # Operation... + result:1 = (DST8_0_4 - XRSRC_B_AS); + # Result Flags... + $(SIGN) = (result s< 0x0); # S Flag + $(ZERO) = (result == 0x0); # Z Flag + build postIncrement; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:CMPX.W XRSRC_W_AS, DST16_0_4 is ctx_haveext=4 & op16_12_4=0x9 & bow=0 & ctx_al=1 & postIncrement & XRSRC_W_AS & DST16_0_4 { + + # Operation Flags... + $(CARRY) = (XRSRC_W_AS <= DST16_0_4); # Carry is NOT set if there is a borrow + $(OVERFLOW) = sborrow(DST16_0_4, XRSRC_W_AS); # V Flag + # Operation... + result:2 = (DST16_0_4 - XRSRC_W_AS); + # Result Flags... + $(SIGN) = (result s< 0x0); # S Flag + $(ZERO) = (result == 0x0); # Z Flag + build postIncrement; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:CMPX.A XRSRC_A_AS, dest_0_4 is ctx_haveext=4 & op16_12_4=0x9 & bow=1 & ctx_al=0 & postIncrement & XRSRC_A_AS & dest_0_4 { + + tmp:$(REG_SIZE) = dest_0_4 - XRSRC_A_AS; + tmpd:$(REG_SIZE) = sext(tmp[0,20]); + setsubflags(tmpd,XRSRC_A_AS,dest_0_4); + build postIncrement; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:DADCX.B DST8_0_4 is ctx_haveext=4 & op16_12_4=0xA & src16_8_4=0x3 & as=0x0 & bow=1 & ctx_al=1 & postIncrementStore & DST8_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + $(CARRY) = 0; # This should be overflow + # Operation... + DST8_0_4 = bcd_add(DST8_0_4); + bzero(reg_Direct16_0_4,DST8_0_4); + # Result Flags... + $(SIGN) = (DST8_0_4 s< 0x0); # S Flag + $(ZERO) = (DST8_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:DADCX.W DST16_0_4 is ctx_haveext=4 & op16_12_4=0xA & src16_8_4=0x3 & as=0x0 & bow=0 & ctx_al=1 & postIncrementStore & DST16_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + $(CARRY) = 0; # Don't currently have BCD overflow op + # Operation... + DST16_0_4 = bcd_add(DST16_0_4); + wzero(reg_Direct16_0_4,DST16_0_4); + # Result Flags... + $(SIGN) = (DST16_0_4 s< 0x0); # S Flag + $(ZERO) = (DST16_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:DADCX.A dest_0_4 is ctx_haveext=4 & op16_12_4=0xA & src16_8_4=0x3 & as=0x0 & bow=1 & ctx_al=0 & postIncrementStore & dest_0_4 { + + # Operation Flags... + $(CARRY) = 0; # Don't currently have BCD overflow op + # Operation... + dest_0_4 = bcd_add(dest_0_4); + dest_0_4 = sext(dest_0_4[0,20]); + # Result Flags... + $(SIGN) = (dest_0_4 s< 0x0); # S Flag + $(ZERO) = (dest_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:DADDX.B XRSRC_B_AS, DST8_0_4 is ctx_haveext=4 & op16_12_4=0xA & bow=1 & ctx_al=1 & postIncrementStore & XRSRC_B_AS & DST8_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + $(CARRY) = 0; # This should be overflow + # Operation... + DST8_0_4 = bcd_add(XRSRC_B_AS,DST8_0_4); + bzero(reg_Direct16_0_4,DST8_0_4); + # Result Flags... + $(SIGN) = (DST8_0_4 s< 0x0); # S Flag + $(ZERO) = (DST8_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:DADDX.W XRSRC_W_AS, DST16_0_4 is ctx_haveext=4 & op16_12_4=0xA & bow=0 & ctx_al=1 & postIncrementStore & XRSRC_W_AS & DST16_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + $(CARRY) = 0; # Don't currently have BCD overflow op + # Operation... + DST16_0_4 = bcd_add(XRSRC_W_AS ,DST16_0_4); + wzero(reg_Direct16_0_4,DST16_0_4); + # Result Flags... + $(SIGN) = (DST16_0_4 s< 0x0); # S Flag + $(ZERO) = (DST16_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:DADDX.A XRSRC_A_AS, dest_0_4 is ctx_haveext=4 & op16_12_4=0xA & bow=1 & ctx_al=0 & postIncrementStore & XRSRC_A_AS & dest_0_4 { + + # Operation Flags... + $(CARRY) = 0; # Don't currently have BCD overflow op + # Operation... + dest_0_4 = bcd_add(XRSRC_A_AS ,dest_0_4); + dest_0_4 = sext(dest_0_4[0,20]); + # Result Flags... + $(SIGN) = (dest_0_4 s< 0x0); # S Flag + $(ZERO) = (dest_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:DECX.B DST8_0_4 is ctx_haveext=4 & op16_12_4=0x8 & src16_8_4=0x3 & as=0x1 & bow=1 & ctx_al=1 & postIncrementStore & DST8_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + $(CARRY) = (1 <= DST8_0_4); # Carry is NOT set if there is a borrow + $(OVERFLOW) = sborrow(DST8_0_4, 1:1); # V Flag + # Operation... + DST8_0_4 = DST8_0_4 - 1; + bzero(reg_Direct16_0_4,DST8_0_4); + # Result Flags... + $(SIGN) = (DST8_0_4 s< 0x0); # S Flag + $(ZERO) = (DST8_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:DECX.W DST16_0_4 is ctx_haveext=4 & op16_12_4=0x8 & src16_8_4=0x3 & as=0x1 & bow=0 & ctx_al=1 & postIncrementStore & DST16_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + $(CARRY) = (1 <= DST16_0_4); # Carry is NOT set if there is a borrow + $(OVERFLOW) = sborrow(DST16_0_4, 1:2); # V Flag + # Operation... + DST16_0_4 = DST16_0_4 - 1; + wzero(reg_Direct16_0_4,DST16_0_4); + # Result Flags... + $(SIGN) = (DST16_0_4 s< 0x0); # S Flag + $(ZERO) = (DST16_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:DECX.A dest_0_4 is ctx_haveext=4 & op16_12_4=0x8 & src16_8_4=0x3 & as=0x1 & bow=1 & ctx_al=0 & postIncrementStore & dest_0_4 { + + tmpd:$(REG_SIZE) = dest_0_4; + tmp:$(REG_SIZE) = dest_0_4 - 1; + dest_0_4 = sext(tmp[0,20]); + + setsubflags(dest_0_4,1:$(REG_SIZE),tmpd); + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:DECDX.B DST8_0_4 is ctx_haveext=4 & op16_12_4=0x8 & src16_8_4=0x3 & as=0x2 & bow=1 & ctx_al=1 & postIncrementStore & DST8_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + $(CARRY) = (2 <= DST8_0_4); # Carry is NOT set if there is a borrow + $(OVERFLOW) = sborrow(DST8_0_4, 2:1); # V Flag + # Operation... + DST8_0_4 = DST8_0_4 - 2; + bzero(reg_Direct16_0_4,DST8_0_4); + # Result Flags... + $(SIGN) = (DST8_0_4 s< 0x0); # S Flag + $(ZERO) = (DST8_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:DECDX.W DST16_0_4 is ctx_haveext=4 & op16_12_4=0x8 & src16_8_4=0x3 & as=0x2 & bow=0 & ctx_al=1 & postIncrementStore & DST16_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + $(CARRY) = (2 <= DST16_0_4); # Carry is NOT set if there is a borrow + $(OVERFLOW) = sborrow(DST16_0_4, 2:2); # V Flag + # Operation... + DST16_0_4 = DST16_0_4 - 2; + wzero(reg_Direct16_0_4,DST16_0_4); + # Result Flags... + $(SIGN) = (DST16_0_4 s< 0x0); # S Flag + $(ZERO) = (DST16_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:DECDX.A dest_0_4 is ctx_haveext=4 & op16_12_4=0x8 & src16_8_4=0x3 & as=0x2 & bow=1 & ctx_al=0 & postIncrementStore & dest_0_4 { + + tmpd:$(REG_SIZE) = dest_0_4; + tmp:$(REG_SIZE) = dest_0_4 - 2; + dest_0_4 = sext(tmp[0,20]); + + setsubflags(dest_0_4,2:$(REG_SIZE),tmpd); + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:INCX.B DST8_0_4 is ctx_haveext=4 & op16_12_4=0x5 & src16_8_4=0x3 & as=0x1 & bow=1 & ctx_al=1 & postIncrementStore & DST8_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + $(CARRY) = carry(DST8_0_4,1); # C Flag + $(OVERFLOW) = scarry(DST8_0_4,1); # V Flag + # Operation... + DST8_0_4 = 1 + DST8_0_4; + bzero(reg_Direct16_0_4,DST8_0_4); + # Result Flags... + $(SIGN) = (DST8_0_4 s< 0x0); # S Flag + $(ZERO) = (DST8_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:INCX.W DST16_0_4 is ctx_haveext=4 & op16_12_4=0x5 & src16_8_4=0x3 & as=0x1 & bow=0 & ctx_al=1 & postIncrementStore & DST16_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + $(CARRY) = carry(DST16_0_4,1); # C Flag + $(OVERFLOW) = scarry(DST16_0_4,1); # V Flag + # Operation... + DST16_0_4 = 1:2 + DST16_0_4; + wzero(reg_Direct16_0_4,DST16_0_4); + # Result Flags... + $(SIGN) = (DST16_0_4 s< 0x0); # S Flag + $(ZERO) = (DST16_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:INCX.A dest_0_4 is ctx_haveext=4 & op16_12_4=0x5 & src16_8_4=0x3 & as=0x1 & bow=1 & ctx_al=0 & postIncrementStore & dest_0_4 { + + tmpd:$(REG_SIZE) = dest_0_4; + tmp:$(REG_SIZE) = 1 + dest_0_4; + dest_0_4 = sext(tmp[0,20]); + + setaddflags(dest_0_4,1:$(REG_SIZE),tmpd); + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:INCDX.B DST8_0_4 is ctx_haveext=4 & op16_12_4=0x5 & src16_8_4=0x3 & as=0x2 & bow=1 & ctx_al=1 & postIncrementStore & DST8_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + $(CARRY) = carry(DST8_0_4,2); # C Flag + $(OVERFLOW) = scarry(DST8_0_4,2); # V Flag + # Operation... + DST8_0_4 = 2 + DST8_0_4; + bzero(reg_Direct16_0_4,DST8_0_4); + # Result Flags... + $(SIGN) = (DST8_0_4 s< 0x0); # S Flag + $(ZERO) = (DST8_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:INCDX.W DST16_0_4 is ctx_haveext=4 & op16_12_4=0x5 & src16_8_4=0x3 & as=0x2 & bow=0 & ctx_al=1 & postIncrementStore & DST16_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + $(CARRY) = carry(DST16_0_4,2); # C Flag + $(OVERFLOW) = scarry(DST16_0_4,2); # V Flag + # Operation... + DST16_0_4 = 2:2 + DST16_0_4; + wzero(reg_Direct16_0_4,DST16_0_4); + # Result Flags... + $(SIGN) = (DST16_0_4 s< 0x0); # S Flag + $(ZERO) = (DST16_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:INCDX.A dest_0_4 is ctx_haveext=4 & op16_12_4=0x5 & src16_8_4=0x3 & as=0x2 & bow=1 & ctx_al=0 & postIncrementStore & dest_0_4 { + + tmpd:$(REG_SIZE) = dest_0_4; + tmp:$(REG_SIZE) = 2 + dest_0_4; + dest_0_4 = sext(tmp[0,20]); + + setaddflags(dest_0_4,2:$(REG_SIZE),tmpd); + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:INVX.B DST8_0_4 is ctx_haveext=4 & op16_12_4=0xE & src16_8_4=0x3 & as=0x3 & bow=1 & ctx_al=1 & postIncrementStore & DST8_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + $(OVERFLOW) = DST8_0_4 s< 0x0; # V Flag + # Operation... + DST8_0_4 = DST8_0_4 ^ -1; + bzero(reg_Direct16_0_4,DST8_0_4); + # Result Flags... + $(SIGN) = (DST8_0_4 s< 0x0); # S Flag + $(ZERO) = (DST8_0_4 == 0x0); # Z Flag + $(CARRY) = (DST8_0_4 != 0x0); # C Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:INVX.W DST16_0_4 is ctx_haveext=4 & op16_12_4=0xE & src16_8_4=0x3 & as=0x3 & bow=0 & ctx_al=1 & postIncrementStore & DST16_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + $(OVERFLOW) = DST16_0_4 s< 0x0 ; # V Flag + # Operation... + DST16_0_4 = DST16_0_4 ^ -1; + wzero(reg_Direct16_0_4,DST16_0_4); + # Result Flags... + $(SIGN) = (DST16_0_4 s< 0x0); # S Flag + $(ZERO) = (DST16_0_4 == 0x0); # Z Flag + $(CARRY) = (DST16_0_4 != 0x0); # C Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:INVX.A dest_0_4 is ctx_haveext=4 & op16_12_4=0xE & src16_8_4=0x3 & as=0x3 & bow=1 & ctx_al=0 & postIncrementStore & dest_0_4 { + + # Operation Flags... + $(OVERFLOW) = dest_0_4 s< 0x0; # V Flag + # Operation... + dest_0_4 = dest_0_4 ^ -1; + dest_0_4 = sext(dest_0_4[0,20]); + # Result Flags... + $(SIGN) = (dest_0_4 s< 0x0); # S Flag + $(ZERO) = (dest_0_4 == 0x0); # Z Flag + $(CARRY) = (dest_0_4 != 0x0); # C Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:MOVX.B XRSRC_B_AS, DST8_0_4 is ctx_haveext=4 & op16_12_4=0x4 & bow=1 & ctx_al=1 & postIncrementStore & XRSRC_B_AS & DST8_0_4 & reg_Direct16_0_4 { + + DST8_0_4 = XRSRC_B_AS; + bzero(reg_Direct16_0_4,DST8_0_4); + #Status bits are not affected + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:MOVX.W XRSRC_W_AS, DST16_0_4 is ctx_haveext=4 & op16_12_4=0x4 & bow=0 & ctx_al=1 & postIncrementStore & XRSRC_W_AS & DST16_0_4 & reg_Direct16_0_4 { + + DST16_0_4 = XRSRC_W_AS; + wzero(reg_Direct16_0_4,DST16_0_4); + #Status bits are not affected + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:MOVX.A XRSRC_A_AS, dest_0_4 is ctx_haveext=4 & op16_12_4=0x4 & bow=1 & ctx_al=0 & postIncrementStore & XRSRC_A_AS & dest_0_4 { + + dest_0_4 = XRSRC_A_AS; + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:POPX.B DST8_0_4 is ctx_haveext=4 & op16_12_4=0x4 & src16_8_4=0x1 & as=0x3 & bow=1 & ctx_al=1 & XRSRC_B_AS & DST8_0_4 & reg_Direct16_0_4 { + + DST8_0_4 = *:1 SP; + bzero(reg_Direct16_0_4,DST8_0_4); + SP = SP + 0x2; + #Status bits are not affected + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:POPX.W DST16_0_4 is ctx_haveext=4 & op16_12_4=0x4 & src16_8_4=0x1 & as=0x3 & bow=0 & ctx_al=1 & XRSRC_W_AS & DST16_0_4 & reg_Direct16_0_4 { + + DST16_0_4 = *:2 SP; + wzero(reg_Direct16_0_4,DST16_0_4); + SP = SP + 0x2; + #Status bits are not affected + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:POPX.A dest_0_4 is ctx_haveext=4 & op16_12_4=0x4 & src16_8_4=0x1 & as=0x3 & bow=1 & ctx_al=0 & XRSRC_A_AS & dest_0_4 { + + dest_0_4 = *:4 SP; + SP = SP + 0x4; + dest_0_4 = sext(dest_0_4[0,20]); + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:RLAX.B DST8_0_4 is ctx_haveext=4 & op16_12_4=0x5 & bow=1 & ctx_al=1 & src_Direct16_8_4=dest_Direct16_0_4 & DST8_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + $(CARRY) = carry(DST8_0_4, DST8_0_4); # C Flag + $(OVERFLOW) = scarry(DST8_0_4, DST8_0_4); # V Flag + # Operation... + DST8_0_4 = DST8_0_4 + DST8_0_4; + bzero(reg_Direct16_0_4,DST8_0_4); + # Result Flags... + $(SIGN) = (DST8_0_4 s< 0x0); # S Flag + $(ZERO) = (DST8_0_4 == 0x0); # Z Flag + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:RLAX.W DST16_0_4 is ctx_haveext=4 & op16_12_4=0x5 & bow=0 & ctx_al=1 & src_Direct16_8_4=dest_Direct16_0_4 & DST16_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + $(CARRY) = carry(DST16_0_4, DST16_0_4); # C Flag + $(OVERFLOW) = scarry(DST16_0_4, DST16_0_4); # V Flag + # Operation... + DST16_0_4 = DST16_0_4 + DST16_0_4; + wzero(reg_Direct16_0_4,DST16_0_4); + # Result Flags... + $(SIGN) = (DST16_0_4 s< 0x0); # S Flag + $(ZERO) = (DST16_0_4 == 0x0); # Z Flag + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:RLAX.A dest_0_4 is ctx_haveext=4 & op16_12_4=0x5 & bow=1 & src_Direct16_8_4=dest_Direct16_0_4 & ctx_al=0 & dest_0_4 { + + tmpd:$(REG_SIZE) = dest_0_4; + tmp:$(REG_SIZE) = dest_0_4 + dest_0_4; + dest_0_4 = sext(tmp[0,20]); + + setaddflags(dest_0_4,tmpd,tmpd); + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:RLCX.B DST8_0_4 is ctx_haveext=4 & op16_12_4=0x6 & bow=1 & ctx_al=1 & src_Direct16_8_4=dest_Direct16_0_4 & postIncrementStore & XRSRC_B_AS & DST8_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + tmp_carry:1 = (carry(DST8_0_4, $(CARRY)) || carry(DST8_0_4,DST8_0_4 + $(CARRY))); #C Flag + $(OVERFLOW) = (scarry(DST8_0_4, $(CARRY)) || scarry(DST8_0_4,DST8_0_4 + $(CARRY))); #V Flag + # Operation... + DST8_0_4 = DST8_0_4 + DST8_0_4 + $(CARRY); + bzero(reg_Direct16_0_4,DST8_0_4); + # Result Flags... + $(CARRY) = tmp_carry; + $(SIGN) = (DST8_0_4 s< 0x0); # S Flag + $(ZERO) = (DST8_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:RLCX.W DST16_0_4 is ctx_haveext=4 & op16_12_4=0x6 & bow=0 & ctx_al=1 & src_Direct16_8_4=dest_Direct16_0_4 & postIncrementStore & XRSRC_W_AS & DST16_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + tmp_carry:1 = (carry(DST16_0_4,zext($(CARRY))) || carry(DST16_0_4,DST16_0_4 + zext($(CARRY)))); #C Flag + $(OVERFLOW) = (scarry(DST16_0_4,zext($(CARRY))) || scarry(DST16_0_4,DST16_0_4 + zext($(CARRY)))); #V Flag + # Operation... + DST16_0_4 = DST16_0_4 + DST16_0_4 + zext($(CARRY)); + wzero(reg_Direct16_0_4,DST16_0_4); + # Result Flags... + $(CARRY) = tmp_carry; + $(SIGN) = (DST16_0_4 s< 0x0); # S Flag + $(ZERO) = (DST16_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:RLCX.A dest_0_4 is ctx_haveext=4 & op16_12_4=0x6 & bow=1 & ctx_al=0 & src_Direct16_8_4=dest_Direct16_0_4 & postIncrementStore & XRSRC_A_AS & dest_0_4 { + + tmpd:$(REG_SIZE) = dest_0_4; + tmps:$(REG_SIZE) = dest_0_4 + zext($(CARRY)); + tmp:$(REG_SIZE) = tmps + dest_0_4; + dest_0_4 = sext(tmp[0,20]); + + setaddflags(dest_0_4,tmps,tmpd); + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:SBCX.B DST8_0_4 is ctx_haveext=4 & op16_12_4=0x7 & bow=1 & ctx_al=1 & src16_8_4=0x3 & as=0x0 & postIncrementStore & DST8_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + brw:1 = 1 - $(CARRY); + $(CARRY) = (brw <= DST8_0_4); # Carry flag is NOT set if there is a borrow + $(OVERFLOW) = sborrow(DST8_0_4, brw); + # Operation... + DST8_0_4 = DST8_0_4 - brw; + bzero(reg_Direct16_0_4,DST8_0_4); + # Result Flags... + $(SIGN) = (DST8_0_4 s< 0x0); # S Flag + $(ZERO) = (DST8_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:SBCX.W DST16_0_4 is ctx_haveext=4 & op16_12_4=0x7 & bow=0 & ctx_al=1 & src16_8_4=0x3 & as=0x0 & postIncrementStore & DST16_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + brw:2 = 1 - zext( $(CARRY) ); + $(CARRY) = (brw <= DST16_0_4); # Carry flag is NOT set if there is a borrow + $(OVERFLOW) = sborrow(DST16_0_4, brw); + # Operation... + DST16_0_4 = DST16_0_4 - brw; + wzero(reg_Direct16_0_4,DST16_0_4); + # Result Flags... + $(SIGN) = (DST16_0_4 s< 0x0); # S Flag + $(ZERO) = (DST16_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:SBCX.A dest_0_4 is ctx_haveext=4 & op16_12_4=0x7 & bow=1 & ctx_al=0 & src16_8_4=0x3 & as=0x0 & postIncrementStore & dest_0_4 { + + brw:$(REG_SIZE) = 1 - zext( $(CARRY) ); + tmpd:$(REG_SIZE) = dest_0_4; + tmp:$(REG_SIZE) = dest_0_4 - brw; + dest_0_4 = sext(tmp[0,20]); + + setsubflags(dest_0_4,brw,tmpd); + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:SUBCX.B XRSRC_B_AS, DST8_0_4 is ctx_haveext=4 & op16_12_4=0x7 & bow=1 & ctx_al=1 & postIncrementStore & XRSRC_B_AS & DST8_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + brw:1 = 1 - $(CARRY); + $(CARRY) = ((brw + XRSRC_B_AS) <= DST8_0_4); # Carry flag is NOT set if there is a borrow + $(OVERFLOW) = sborrow(DST8_0_4, XRSRC_B_AS + brw); + # Operation... + DST8_0_4 = DST8_0_4 - XRSRC_B_AS - brw; + bzero(reg_Direct16_0_4,DST8_0_4); + # Result Flags... + $(SIGN) = (DST8_0_4 s< 0x0); # S Flag + $(ZERO) = (DST8_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:SUBCX.W XRSRC_W_AS, DST16_0_4 is ctx_haveext=4 & op16_12_4=0x7 & bow=0 & ctx_al=1 & postIncrementStore & XRSRC_W_AS & DST16_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + brw:2 = 1 - zext( $(CARRY) ); + $(CARRY) = ((brw + XRSRC_W_AS) <= DST16_0_4); # Carry flag is NOT set if there is a borrow + $(OVERFLOW) = sborrow(DST16_0_4, XRSRC_W_AS + brw); + # Operation... + DST16_0_4 = DST16_0_4 - XRSRC_W_AS - brw; + wzero(reg_Direct16_0_4,DST16_0_4); + # Result Flags... + $(SIGN) = (DST16_0_4 s< 0x0); # S Flag + $(ZERO) = (DST16_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:SUBCX.A XRSRC_A_AS, dest_0_4 is ctx_haveext=4 & op16_12_4=0x7 & bow=1 & ctx_al=0 & postIncrementStore & XRSRC_A_AS & dest_0_4 { + + brw:$(REG_SIZE) = 1 - zext( $(CARRY) ); + tmpd:$(REG_SIZE) = dest_0_4; + tmps:$(REG_SIZE) = XRSRC_A_AS + brw; + tmp:$(REG_SIZE) = dest_0_4 - tmps; + dest_0_4 = sext(tmp[0,20]); + + setsubflags(dest_0_4,tmps,tmpd); + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:SUBX.B XRSRC_B_AS, DST8_0_4 is ctx_haveext=4 & op16_12_4=0x8 & bow=1 & ctx_al=1 & postIncrementStore & XRSRC_B_AS & DST8_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + $(CARRY) = (XRSRC_B_AS <= DST8_0_4); # Carry is NOT set if there is a borrow + $(OVERFLOW) = sborrow(DST8_0_4, XRSRC_B_AS); # V Flag + # Operation... + DST8_0_4 = DST8_0_4 - XRSRC_B_AS; + bzero(reg_Direct16_0_4,DST8_0_4); + # Result Flags... + $(SIGN) = (DST8_0_4 s< 0x0); # S Flag + $(ZERO) = (DST8_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:SUBX.W XRSRC_W_AS, DST16_0_4 is ctx_haveext=4 & op16_12_4=0x8 & bow=0 & ctx_al=1 & postIncrementStore & XRSRC_W_AS & DST16_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + $(CARRY) = (XRSRC_W_AS <= DST16_0_4); # Carry is NOT set if there is a borrow + $(OVERFLOW) = sborrow(DST16_0_4, XRSRC_W_AS); # V Flag + # Operation... + DST16_0_4 = DST16_0_4 - XRSRC_W_AS; + wzero(reg_Direct16_0_4,DST16_0_4); + # Result Flags... + $(SIGN) = (DST16_0_4 s< 0x0); # S Flag + $(ZERO) = (DST16_0_4 == 0x0); # Z Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:SUBX.A XRSRC_A_AS, dest_0_4 is ctx_haveext=4 & op16_12_4=0x8 & bow=1 & ctx_al=0 & postIncrementStore & XRSRC_A_AS & dest_0_4 { + + tmpd:$(REG_SIZE) = dest_0_4; + tmp:$(REG_SIZE) = dest_0_4 - XRSRC_A_AS; + dest_0_4 = sext(tmp[0,20]); + + setsubflags(dest_0_4,XRSRC_A_AS,tmpd); + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:TSTX.B DST8_0_4 is ctx_haveext=4 & op16_12_4=0x9 & bow=1 & ctx_al=1 & src16_8_4=0x3 & as=0x0 & DST8_0_4 { + + # Operation Flags... + $(CARRY) = 1; # Carry is NOT set if there is a borrow + $(OVERFLOW) = 0; # V Flag + # Result Flags... + $(SIGN) = (DST8_0_4 s< 0x0); # S Flag + $(ZERO) = (DST8_0_4 == 0x0); # Z Flag + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:TSTX.W DST16_0_4 is ctx_haveext=4 & op16_12_4=0x9 & bow=0 & ctx_al=1 & src16_8_4=0x3 & as=0x0 & DST16_0_4 { + + # Operation Flags... + $(CARRY) = 1; # Carry is NOT set if there is a borrow + $(OVERFLOW) = 0; # V Flag + # Result Flags... + $(SIGN) = (DST16_0_4 s< 0x0); # S Flag + $(ZERO) = (DST16_0_4 == 0x0); # Z Flag + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:TSTX.A dest_0_4 is ctx_haveext=4 & op16_12_4=0x9 & bow=1 & ctx_al=0 & src16_8_4=0x3 & as=0x0 & dest_0_4 { + + setsubflags(dest_0_4,0:$(REG_SIZE),dest_0_4); + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:XORX.B XRSRC_B_AS, DST8_0_4 is ctx_haveext=4 & op16_12_4=0xE & bow=1 & ctx_al=1 & postIncrementStore & XRSRC_B_AS & DST8_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + $(OVERFLOW) = ((DST8_0_4 s< 0x0) && (XRSRC_B_AS s< 0x0)) ; # V Flag + # Operation... + DST8_0_4 = DST8_0_4 ^ XRSRC_B_AS; + bzero(reg_Direct16_0_4,DST8_0_4); + # Result Flags... + $(SIGN) = (DST8_0_4 s< 0x0); # S Flag + $(ZERO) = (DST8_0_4 == 0x0); # Z Flag + $(CARRY) = (DST8_0_4 != 0x0); # C Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:XORX.W XRSRC_W_AS, DST16_0_4 is ctx_haveext=4 & op16_12_4=0xE & bow=0 & ctx_al=1 & postIncrementStore & XRSRC_W_AS & DST16_0_4 & reg_Direct16_0_4 { + + # Operation Flags... + $(OVERFLOW) = ((DST16_0_4 s< 0x0) && (XRSRC_W_AS s< 0x0)) ; # V Flag + # Operation... + DST16_0_4 = DST16_0_4 ^ XRSRC_W_AS; + wzero(reg_Direct16_0_4,DST16_0_4); + # Result Flags... + $(SIGN) = (DST16_0_4 s< 0x0); # S Flag + $(ZERO) = (DST16_0_4 == 0x0); # Z Flag + $(CARRY) = (DST16_0_4 != 0x0); # C Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:XORX.A XRSRC_A_AS, dest_0_4 is ctx_haveext=4 & op16_12_4=0xE & bow=1 & ctx_al=0 & postIncrementStore & XRSRC_A_AS & dest_0_4 { + + # Operation Flags... + $(OVERFLOW) = ((dest_0_4 s< 0x0) && (XRSRC_A_AS s< 0x0)) ; # V Flag + # Operation... + dest_0_4 = dest_0_4 ^ XRSRC_A_AS; + dest_0_4 = sext(dest_0_4[0,20]); + # Result Flags... + $(SIGN) = (dest_0_4 s< 0x0); # S Flag + $(ZERO) = (dest_0_4 == 0x0); # Z Flag + $(CARRY) = (dest_0_4 != 0x0); # C Flag + build postIncrementStore; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +############################# +# No Repeat +:ADCX.B XDEST_B_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x6 & src16_8_4=0x3 & as=0x0 & bow=1 & tbl_bzero & postIncrementStore) ... & XDEST_B_AD ... { + # Operation Flags... + tmp_carry:1 = carry(XDEST_B_AD,$(CARRY)); #C Flag + $(OVERFLOW) = scarry(XDEST_B_AD,$(CARRY)); #V Flag + # Operation... + XDEST_B_AD = XDEST_B_AD + $(CARRY); + build tbl_bzero; + # Result Flags... + $(CARRY) = tmp_carry; + $(SIGN) = (XDEST_B_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:ADCX.W XDEST_W_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x6 & src16_8_4=0x3 & as=0x0 & bow=0 & tbl_wzero & postIncrementStore) ... & XDEST_W_AD ... { + # Operation Flags... + tmp_carry:1 = carry(XDEST_W_AD,zext($(CARRY))); #C Flag + $(OVERFLOW) = scarry(XDEST_W_AD,zext($(CARRY))); #V Flag + # Operation... + XDEST_W_AD = XDEST_W_AD + zext($(CARRY)); + build tbl_wzero; + # Result Flags... + $(CARRY) = tmp_carry; + $(SIGN) = (XDEST_W_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:ADCX.A XDEST_A_AD is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x6 & src16_8_4=0x3 & as=0x0 & bow=1 & postIncrementStore) ... & XDEST_A_AD ... { + tmpd:$(REG_SIZE) = XDEST_A_AD; + tmpc:$(REG_SIZE) = zext($(CARRY)); + tmp:$(REG_SIZE) = tmpc + XDEST_A_AD; + XDEST_A_AD = sext(tmp[0,20]); + + setaddflags(XDEST_A_AD,tmpc,tmpd); + build postIncrementStore; +} + +:ADDX.B XSRC_B_AS, XDEST_B_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x5 & bow=1 & tbl_bzero & postIncrementStore) ... & XSRC_B_AS ... & XDEST_B_AD ... { + # Operation Flags... + $(CARRY) = carry(XSRC_B_AS, XDEST_B_AD); # C Flag + $(OVERFLOW) = scarry(XSRC_B_AS, XDEST_B_AD); # V Flag + # Operation... + XDEST_B_AD = XSRC_B_AS + XDEST_B_AD; + build tbl_bzero; + # Result Flags... + $(SIGN) = (XDEST_B_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:ADDX.W XSRC_W_AS, XDEST_W_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x5 & bow=0 & tbl_wzero & postIncrementStore) ... & XSRC_W_AS ... & XDEST_W_AD ... { + # Operation Flags... + $(CARRY) = carry(XSRC_W_AS, XDEST_W_AD); # C Flag + $(OVERFLOW) = scarry(XSRC_W_AS, XDEST_W_AD); # V Flag + # Operation... + XDEST_W_AD = XSRC_W_AS + XDEST_W_AD; + build tbl_wzero; + # Result Flags... + $(SIGN) = (XDEST_W_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:ADDX.A XSRC_A_AS, XDEST_A_AD is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x5 & bow=1 & postIncrementStore) ... & XSRC_A_AS ... & XDEST_A_AD ... { + tmpd:$(REG_SIZE) = XDEST_A_AD; + tmp:$(REG_SIZE) = XSRC_A_AS + XDEST_A_AD; + + XDEST_A_AD = sext(tmp[0,20]); + setaddflags(XDEST_A_AD,XSRC_A_AS,tmpd); + build postIncrementStore; +} + +:ADDCX.B XSRC_B_AS, XDEST_B_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x6 & bow=1 & tbl_bzero & postIncrementStore) ... & XSRC_B_AS ... & XDEST_B_AD ... { + # Operation Flags... + tmp_carry:1 = (carry(XSRC_B_AS, $(CARRY)) || carry(XDEST_B_AD,XSRC_B_AS + $(CARRY))); #C Flag + $(OVERFLOW) = (scarry(XSRC_B_AS, $(CARRY)) || scarry(XDEST_B_AD,XSRC_B_AS + $(CARRY))); #V Flag + # Operation... + XDEST_B_AD = XSRC_B_AS + XDEST_B_AD + $(CARRY); + build tbl_bzero; + # Result Flags... + $(CARRY) = tmp_carry; + $(SIGN) = (XDEST_B_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:ADDCX.W XSRC_W_AS, XDEST_W_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x6 & bow=0 & tbl_wzero & postIncrementStore) ... & XSRC_W_AS ... & XDEST_W_AD ... { + # Operation Flags... + tmp_carry:1 = (carry(XSRC_W_AS,zext($(CARRY))) || carry(XDEST_W_AD,XSRC_W_AS + zext($(CARRY)))); #C Flag + $(OVERFLOW) = (scarry(XSRC_W_AS,zext($(CARRY))) || scarry(XDEST_W_AD,XSRC_W_AS + zext($(CARRY)))); #V Flag + # Operation... + XDEST_W_AD = XSRC_W_AS + XDEST_W_AD + zext($(CARRY)); + build tbl_wzero; + # Result Flags... + $(CARRY) = tmp_carry; + $(SIGN) = (XDEST_W_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:ADDCX.A XSRC_A_AS, XDEST_A_AD is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x6 & bow=1 & postIncrementStore) ... & XSRC_A_AS ... & XDEST_A_AD ... { + tmpd:$(REG_SIZE) = XDEST_A_AD; + tmps:$(REG_SIZE) = XSRC_A_AS + zext($(CARRY)); + tmp:$(REG_SIZE) = tmps + XDEST_A_AD; + XDEST_A_AD = sext(tmp[0,20]); + + setaddflags(XDEST_A_AD,tmps,tmpd); + build postIncrementStore; +} + +:ANDX.B XSRC_B_AS, XDEST_B_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xF & bow=1 & tbl_bzero & postIncrementStore) ... & XSRC_B_AS ... & XDEST_B_AD ... { + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag + # Operation... + result:1 = XDEST_B_AD & XSRC_B_AS; + XDEST_B_AD = result; + build tbl_bzero; + # Result Flags... + $(SIGN) = (result s< 0x0); # S Flag + $(ZERO) = (result == 0x0); # Z Flag + $(CARRY) = (result != 0x0); # C Flag + build postIncrementStore; +} + +:ANDX.W XSRC_W_AS, XDEST_W_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xF & bow=0 & tbl_wzero & postIncrementStore) ... & XSRC_W_AS ... & XDEST_W_AD ... { + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag + # Operation... + result:2 = XDEST_W_AD & XSRC_W_AS; + XDEST_W_AD = result; + build tbl_wzero; + # Result Flags... + $(SIGN) = (result s< 0x0); # S Flag + $(ZERO) = (result == 0x0); # Z Flag + $(CARRY) = (result != 0x0); # C Flag + build postIncrementStore; +} + +:ANDX.A XSRC_A_AS, XDEST_A_AD is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0xF & bow=1 & postIncrementStore) ... & XSRC_A_AS ... & XDEST_A_AD ... { + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag + # Operation... + XDEST_A_AD = XDEST_A_AD & XSRC_A_AS; + XDEST_A_AD = sext(XDEST_A_AD[0,20]); + # Result Flags... + $(SIGN) = (XDEST_A_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_A_AD == 0x0); # Z Flag + $(CARRY) = (XDEST_A_AD != 0x0); # C Flag + build postIncrementStore; +} + +:BICX.B XSRC_B_AS, XDEST_B_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xC & bow=1 & tbl_bzero & postIncrementStore) ... & XSRC_B_AS ... & XDEST_B_AD ... { + XDEST_B_AD = (~XSRC_B_AS) & XDEST_B_AD; + build tbl_bzero; + #Status bits are not affected + build postIncrementStore; +} + +:BICX.W XSRC_W_AS, XDEST_W_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xC & bow=0 & tbl_wzero & postIncrementStore) ... & XSRC_W_AS ... & XDEST_W_AD ... { + XDEST_W_AD = (~XSRC_W_AS) & XDEST_W_AD; + build tbl_wzero; + #Status bits are not affected + build postIncrementStore; +} + +:BICX.A XSRC_A_AS, XDEST_A_AD is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0xC & bow=1 & postIncrementStore) ... & XSRC_A_AS ... & XDEST_A_AD ... { + XDEST_A_AD = (~XSRC_A_AS) & XDEST_A_AD; + #Status bits are not affected + XDEST_A_AD = sext(XDEST_A_AD[0,20]); + build postIncrementStore; +} + +:BISX.B XSRC_B_AS, XDEST_B_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xD & bow=1 & tbl_bzero & postIncrementStore) ... & XSRC_B_AS ... & XDEST_B_AD ... { + XDEST_B_AD = XSRC_B_AS | XDEST_B_AD; + build tbl_bzero; + #Status bits are not affected + build postIncrementStore; +} + +:BISX.W XSRC_W_AS, XDEST_W_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xD & bow=0 & tbl_wzero & postIncrementStore) ... & XSRC_W_AS ... & XDEST_W_AD ... { + XDEST_W_AD = XSRC_W_AS | XDEST_W_AD; + build tbl_wzero; + #Status bits are not affected + build postIncrementStore; +} + +:BISX.A XSRC_A_AS, XDEST_A_AD is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0xD & bow=1 & postIncrementStore) ... & XSRC_A_AS ... & XDEST_A_AD ... { + XDEST_A_AD = XSRC_A_AS | XDEST_A_AD; + #Status bits are not affected + XDEST_A_AD = sext(XDEST_A_AD[0,20]); + build postIncrementStore; +} + +:BITX.B XSRC_B_AS, XDEST_B_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xB & bow=1 & postIncrement) ... & XSRC_B_AS ... & XDEST_B_AD ... { + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag (reset) + # Operation... + result:1 = XDEST_B_AD & XSRC_B_AS; + # Result Flags... + $(CARRY) = (result != 0x0); # C Flag + $(SIGN) = (result s< 0x0); # S Flag + $(ZERO) = (result == 0x0); # Z Flag + build postIncrement; +} + +:BITX.W XSRC_W_AS, XDEST_W_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xB & bow=0 & postIncrement) ... & XSRC_W_AS ... & XDEST_W_AD ... { + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag (reset) + # Operation... + result:2 = XDEST_W_AD & XSRC_W_AS; + # Result Flags... + $(CARRY) = (result != 0x0); # C Flag + $(SIGN) = (result s< 0x0); # S Flag + $(ZERO) = (result == 0x0); # Z Flag + build postIncrement; +} + +:BITX.A XSRC_A_AS, XDEST_A_AD is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0xB & bow=1 & postIncrement) ... & XSRC_A_AS ... & XDEST_A_AD ... { + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag (reset) + # Operation... + result:$(REG_SIZE) = XDEST_A_AD & XSRC_A_AS; + # Result Flags... + result = sext(result[0,20]); + $(CARRY) = (result != 0x0); # C Flag + $(SIGN) = (result s< 0x0); # S Flag + $(ZERO) = (result == 0x0); # Z Flag + build postIncrement; +} + +:CLRX.B XDEST_B_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x4 & src16_8_4=0x3 & as=0x0 & bow=1 & tbl_bzero & postIncrementStore) ... & XDEST_B_AD ... { + XDEST_B_AD = 0; + build tbl_bzero; + #Status bits are not affected + build postIncrementStore; +} + +:CLRX.W XDEST_W_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x4 & src16_8_4=0x3 & as=0x0 & bow=0 & tbl_wzero & postIncrementStore) ... & XDEST_W_AD ... { + XDEST_W_AD = 0; + build tbl_wzero; + #Status bits are not affected + build postIncrementStore; +} + +:CLRX.A XDEST_A_AD is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x4 & src16_8_4=0x3 & as=0x0 & bow=1 & postIncrementStore) ... & XDEST_A_AD ... { + XDEST_A_AD = 0; + build postIncrementStore; +} + +:CMPX.B XSRC_B_AS, XDEST_B_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x9 & bow=1 & postIncrement) ... & XSRC_B_AS ... & XDEST_B_AD ... { + # Operation Flags... + $(CARRY) = (XSRC_B_AS <= XDEST_B_AD); # Carry is NOT set if there is a borrow + $(OVERFLOW) = sborrow(XDEST_B_AD, XSRC_B_AS); # V Flag + # Operation... + result:1 = (XDEST_B_AD - XSRC_B_AS); + # Result Flags... + $(SIGN) = (result s< 0x0); # S Flag + $(ZERO) = (result == 0x0); # Z Flag + build postIncrement; +} + +:CMPX.W XSRC_W_AS, XDEST_W_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x9 & bow=0 & postIncrement) ... & XSRC_W_AS ... & XDEST_W_AD ... { + # Operation Flags... + $(CARRY) = (XSRC_W_AS <= XDEST_W_AD); # Carry is NOT set if there is a borrow + $(OVERFLOW) = sborrow(XDEST_W_AD, XSRC_W_AS); # V Flag + # Operation... + result:2 = (XDEST_W_AD - XSRC_W_AS); + # Result Flags... + $(SIGN) = (result s< 0x0); # S Flag + $(ZERO) = (result == 0x0); # Z Flag + build postIncrement; +} + +:CMPX.A XSRC_A_AS, XDEST_A_AD is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x9 & bow=1 & postIncrement) ... & XSRC_A_AS ... & XDEST_A_AD ... { + tmp:$(REG_SIZE) = XDEST_A_AD - XSRC_A_AS; + tmpd:$(REG_SIZE) = sext(tmp[0,20]); + setsubflags(tmpd,XSRC_A_AS,XDEST_A_AD); + build postIncrement; +} + +:DADCX.B XDEST_B_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xA & src16_8_4=0x3 & as=0x0 & bow=1 & tbl_bzero & postIncrementStore) ... & XDEST_B_AD ... { + # Operation Flags... + $(CARRY) = 0; # This should be overflow + # Operation... + XDEST_B_AD = bcd_add(XDEST_B_AD); + build tbl_bzero; + # Result Flags... + $(SIGN) = (XDEST_B_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:DADCX.W XDEST_W_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xA & src16_8_4=0x3 & as=0x0 & bow=0 & tbl_wzero & postIncrementStore) ... & XDEST_W_AD ... { + # Operation Flags... + $(CARRY) = 0; # Don't currently have BCD overflow op + # Operation... + XDEST_W_AD = bcd_add(XDEST_W_AD); + build tbl_wzero; + # Result Flags... + $(SIGN) = (XDEST_W_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:DADCX.A XDEST_A_AD is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0xA & src16_8_4=0x3 & as=0x0 & bow=1 & postIncrementStore) ... & XDEST_A_AD ... { + # Operation Flags... + $(CARRY) = 0; # Don't currently have BCD overflow op + # Operation... + XDEST_A_AD = bcd_add(XDEST_A_AD); + XDEST_A_AD = sext(XDEST_A_AD[0,20]); + # Result Flags... + $(SIGN) = (XDEST_A_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_A_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:DADDX.B XSRC_B_AS, XDEST_B_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xA & bow=1 & tbl_bzero & postIncrementStore) ... & XSRC_B_AS ... & XDEST_B_AD ... { + # Operation Flags... + $(CARRY) = 0; # This should be overflow + # Operation... + XDEST_B_AD = bcd_add(XSRC_B_AS,XDEST_B_AD); + build tbl_bzero; + # Result Flags... + $(SIGN) = (XDEST_B_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:DADDX.W XSRC_W_AS, XDEST_W_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xA & bow=0 & tbl_wzero & postIncrementStore) ... & XSRC_W_AS ... & XDEST_W_AD ... { + # Operation Flags... + $(CARRY) = 0; # Don't currently have BCD overflow op + # Operation... + XDEST_W_AD = bcd_add(XSRC_W_AS ,XDEST_W_AD); + build tbl_wzero; + # Result Flags... + $(SIGN) = (XDEST_W_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:DADDX.A XSRC_A_AS, XDEST_A_AD is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0xA & bow=1 & postIncrementStore) ... & XSRC_A_AS ... & XDEST_A_AD ... { + # Operation Flags... + $(CARRY) = 0; # Don't currently have BCD overflow op + # Operation... + XDEST_A_AD = bcd_add(XSRC_A_AS ,XDEST_A_AD); + XDEST_A_AD = sext(XDEST_A_AD[0,20]); + # Result Flags... + $(SIGN) = (XDEST_A_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_A_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:DECX.B XDEST_B_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x8 & src16_8_4=0x3 & as=0x1 & bow=1 & tbl_bzero & postIncrementStore) ... & XDEST_B_AD ... { + # Operation Flags... + $(CARRY) = (1 <= XDEST_B_AD); # Carry is NOT set if there is a borrow + $(OVERFLOW) = sborrow(XDEST_B_AD, 1:1); # V Flag + # Operation... + XDEST_B_AD = XDEST_B_AD - 1; + build tbl_bzero; + # Result Flags... + $(SIGN) = (XDEST_B_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:DECX.W XDEST_W_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x8 & src16_8_4=0x3 & as=0x1 & bow=0 & tbl_wzero & postIncrementStore) ... & XDEST_W_AD ... { + # Operation Flags... + $(CARRY) = (1 <= XDEST_W_AD); # Carry is NOT set if there is a borrow + $(OVERFLOW) = sborrow(XDEST_W_AD, 1:2); # V Flag + # Operation... + XDEST_W_AD = XDEST_W_AD - 1:2; + build tbl_wzero; + # Result Flags... + $(SIGN) = (XDEST_W_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:DECX.A XDEST_A_AD is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x8 & src16_8_4=0x3 & as=0x1 & bow=1 & postIncrementStore) ... & XDEST_A_AD ... { + tmpd:$(REG_SIZE) = XDEST_A_AD; + tmp:$(REG_SIZE) = XDEST_A_AD - 1:$(REG_SIZE); + XDEST_A_AD = sext(tmp[0,20]); + + setsubflags(XDEST_A_AD,1:$(REG_SIZE),tmpd); + build postIncrementStore; +} + +:DECDX.B XDEST_B_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x8 & src16_8_4=0x3 & as=0x2 & bow=1 & tbl_bzero & postIncrementStore) ... & XDEST_B_AD ... { + # Operation Flags... + $(CARRY) = (1 <= XDEST_B_AD); # Carry is NOT set if there is a borrow + $(OVERFLOW) = sborrow(XDEST_B_AD, 2:1); # V Flag + # Operation... + XDEST_B_AD = XDEST_B_AD - 2; + build tbl_bzero; + # Result Flags... + $(SIGN) = (XDEST_B_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:DECDX.W XDEST_W_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x8 & src16_8_4=0x3 & as=0x2 & bow=0 & tbl_wzero & postIncrementStore) ... & XDEST_W_AD ... { + # Operation Flags... + $(CARRY) = (1 <= XDEST_W_AD); # Carry is NOT set if there is a borrow + $(OVERFLOW) = sborrow(XDEST_W_AD, 2:2); # V Flag + # Operation... + XDEST_W_AD = XDEST_W_AD - 2:2; + build tbl_wzero; + # Result Flags... + $(SIGN) = (XDEST_W_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:DECDX.A XDEST_A_AD is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x8 & src16_8_4=0x3 & as=0x2 & bow=1 & postIncrementStore) ... & XDEST_A_AD ... { + tmpd:$(REG_SIZE) = XDEST_A_AD; + tmp:$(REG_SIZE) = XDEST_A_AD - 2:$(REG_SIZE); + XDEST_A_AD = sext(tmp[0,20]); + + setsubflags(XDEST_A_AD,2:$(REG_SIZE),tmpd); + build postIncrementStore; +} + +:INCX.B XDEST_B_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x5 & src16_8_4=0x3 & as=0x1 & bow=1 & tbl_bzero & postIncrementStore) ... & XDEST_B_AD ... { + # Operation Flags... + $(CARRY) = carry(XDEST_B_AD,1); # C Flag + $(OVERFLOW) = scarry(XDEST_B_AD,1); # V Flag + # Operation... + XDEST_B_AD = 1 + XDEST_B_AD; + build tbl_bzero; + # Result Flags... + $(SIGN) = (XDEST_B_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:INCX.W XDEST_W_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x5 & src16_8_4=0x3 & as=0x1 & bow=0 & tbl_wzero & postIncrementStore) ... & XDEST_W_AD ... { + # Operation Flags... + $(CARRY) = carry(XDEST_W_AD,1); # C Flag + $(OVERFLOW) = scarry(XDEST_W_AD,1); # V Flag + # Operation... + XDEST_W_AD = 1 + XDEST_W_AD; + build tbl_wzero; + # Result Flags... + $(SIGN) = (XDEST_W_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:INCX.A XDEST_A_AD is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x5 & src16_8_4=0x3 & as=0x1 & bow=1 & postIncrementStore) ... & XDEST_A_AD ... { + tmpd:$(REG_SIZE) = XDEST_A_AD; + tmp:$(REG_SIZE) = 1 + XDEST_A_AD; + XDEST_A_AD = sext(tmp[0,20]); + + setaddflags(XDEST_A_AD,1:$(REG_SIZE),tmpd); + build postIncrementStore; +} + +:INCDX.B XDEST_B_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x5 & src16_8_4=0x3 & as=0x2 & bow=1 & tbl_bzero & postIncrementStore) ... & XDEST_B_AD ... { + # Operation Flags... + $(CARRY) = carry(XDEST_B_AD,2); # C Flag + $(OVERFLOW) = scarry(XDEST_B_AD,2); # V Flag + # Operation... + XDEST_B_AD = 2 + XDEST_B_AD; + build tbl_bzero; + # Result Flags... + $(SIGN) = (XDEST_B_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:INCDX.W XDEST_W_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x5 & src16_8_4=0x3 & as=0x2 & bow=0 & tbl_wzero & postIncrementStore) ... & XDEST_W_AD ... { + # Operation Flags... + $(CARRY) = carry(XDEST_W_AD,2); # C Flag + $(OVERFLOW) = scarry(XDEST_W_AD,2); # V Flag + # Operation... + XDEST_W_AD = 2 + XDEST_W_AD; + build tbl_wzero; + # Result Flags... + $(SIGN) = (XDEST_W_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:INCDX.A XDEST_A_AD is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x5 & src16_8_4=0x3 & as=0x2 & bow=1 & postIncrementStore) ... & XDEST_A_AD ... { + tmpd:$(REG_SIZE) = XDEST_A_AD; + tmp:$(REG_SIZE) = 2 + XDEST_A_AD; + XDEST_A_AD = sext(tmp[0,20]); + + setaddflags(XDEST_A_AD,1:$(REG_SIZE),tmpd); + build postIncrementStore; +} + +:INVX.B XDEST_B_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xE & src16_8_4=0x3 & as=0x3 & bow=1 & tbl_bzero & postIncrementStore) ... & XDEST_B_AD ... { + # Operation Flags... + $(OVERFLOW) = XDEST_B_AD s< 0x0; # V Flag + # Operation... + XDEST_B_AD = XDEST_B_AD ^ -1; + build tbl_bzero; + # Result Flags... + $(SIGN) = (XDEST_B_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_B_AD == 0x0); # Z Flag + $(CARRY) = (XDEST_B_AD != 0x0); # C Flag + build postIncrementStore; +} + +:INVX.W XDEST_W_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xE & src16_8_4=0x3 & as=0x3 & bow=0 & tbl_wzero & postIncrementStore) ... & XDEST_W_AD ... { + # Operation Flags... + $(OVERFLOW) = XDEST_W_AD s< 0x0; # V Flag + # Operation... + XDEST_W_AD = XDEST_W_AD ^ -1; + build tbl_wzero; + # Result Flags... + $(SIGN) = (XDEST_W_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_W_AD == 0x0); # Z Flag + $(CARRY) = (XDEST_W_AD != 0x0); # C Flag + build postIncrementStore; +} + +:INVX.A XDEST_A_AD is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0xE & src16_8_4=0x3 & as=0x3 & bow=1 & postIncrementStore) ... & XDEST_A_AD ... { + # Operation Flags... + $(OVERFLOW) = XDEST_A_AD s< 0x0; # V Flag + # Operation... + XDEST_A_AD = XDEST_A_AD ^ -1; + XDEST_A_AD = sext(XDEST_A_AD[0,20]); + # Result Flags... + $(SIGN) = (XDEST_A_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_A_AD == 0x0); # Z Flag + $(CARRY) = (XDEST_A_AD != 0x0); # C Flag + build postIncrementStore; +} + +:MOVX.B XSRC_B_AS, XDEST_B_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x4 & bow=1 & tbl_bzero & postIncrementStore) ... & XSRC_B_AS ... & XDEST_B_AD ... { + XDEST_B_AD = XSRC_B_AS; + build tbl_bzero; + #Status bits are not affected + build postIncrementStore; +} + +:MOVX.W XSRC_W_AS, XDEST_W_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x4 & bow=0 & tbl_wzero & postIncrementStore) ... & XSRC_W_AS ... & XDEST_W_AD ... { + XDEST_W_AD = XSRC_W_AS; + build tbl_wzero; + #Status bits are not affected + build postIncrementStore; +} + +:MOVX.A XSRC_A_AS, XDEST_A_AD is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x4 & bow=1 & postIncrementStore) ... & XSRC_A_AS ... & XDEST_A_AD ... { + XDEST_A_AD = XSRC_A_AS; + build postIncrementStore; +} + +:POPX.B XDEST_B_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x4 & src16_8_4=0x1 & as=0x3 & bow=1 & tbl_bzero) ... & XDEST_B_AD ... { + XDEST_B_AD = *:1 SP; + build tbl_bzero; + SP = SP + 0x2; + #Status bits are not affected +} + +:POPX.W XDEST_W_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x4 & src16_8_4=0x1 & as=0x3 & bow=0 & tbl_wzero) ... & XDEST_W_AD ... { + XDEST_W_AD = *:2 SP; + build tbl_wzero; + SP = SP + 0x2; + #Status bits are not affected +} + +:POPX.A XDEST_A_AD is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x4 & src16_8_4=0x1 & as=0x3 & bow=1) ... & XDEST_A_AD ... { + XDEST_A_AD = *:4 SP; + SP = SP + 0x4; + XDEST_A_AD = sext(XDEST_A_AD[0,20]); +} + +:SBCX.B XDEST_B_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x7 & bow=1 & src16_8_4=0x3 & as=0x0 & tbl_bzero & postIncrementStore) ... & XDEST_B_AD ... { + # Operation Flags... + brw:1 = 1 - $(CARRY); + $(CARRY) = (brw <= XDEST_B_AD); # Carry flag is NOT set if there is a borrow + $(OVERFLOW) = sborrow(XDEST_B_AD, brw); + # Operation... + XDEST_B_AD = XDEST_B_AD - brw; + build tbl_bzero; + # Result Flags... + $(SIGN) = (XDEST_B_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:SBCX.W XDEST_W_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x7 & bow=0 & src16_8_4=0x3 & as=0x0 & tbl_wzero & postIncrementStore) ... & XDEST_W_AD ... { + # Operation Flags... + brw:2 = 1 - zext( $(CARRY) ); + $(CARRY) = (brw <= XDEST_W_AD); # Carry flag is NOT set if there is a borrow + $(OVERFLOW) = sborrow(XDEST_W_AD, brw); + # Operation... + XDEST_W_AD = XDEST_W_AD - brw; + build tbl_wzero; + # Result Flags... + $(SIGN) = (XDEST_W_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:SBCX.A XDEST_A_AD is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x7 & bow=1 & src16_8_4=0x3 & as=0x0 & postIncrementStore) ... & XDEST_A_AD ... { + tmpd:$(REG_SIZE) = XDEST_A_AD; + brw:$(REG_SIZE) = 1 - zext( $(CARRY) ); + tmp:$(REG_SIZE) = XDEST_A_AD - brw; + XDEST_A_AD = sext(tmp[0,20]); + + setsubflags(XDEST_A_AD,brw,tmpd); + build postIncrementStore; +} + +:SUBCX.B XSRC_B_AS, XDEST_B_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x7 & bow=1 & tbl_bzero & postIncrementStore) ... & XSRC_B_AS ... & XDEST_B_AD ... { + # Operation Flags... + brw:1 = 1 - $(CARRY); + $(CARRY) = ((brw + XSRC_B_AS) <= XDEST_B_AD); # Carry flag is NOT set if there is a borrow + $(OVERFLOW) = sborrow(XDEST_B_AD, XSRC_B_AS + brw); + # Operation... + XDEST_B_AD = XDEST_B_AD - XSRC_B_AS - brw; + build tbl_bzero; + # Result Flags... + $(SIGN) = (XDEST_B_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:SUBCX.W XSRC_W_AS, XDEST_W_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x7 & bow=0 & tbl_wzero & postIncrementStore) ... & XSRC_W_AS ... & XDEST_W_AD ... { + # Operation Flags... + brw:2 = 1 - zext( $(CARRY) ); + $(CARRY) = ((brw + XSRC_W_AS) <= XDEST_W_AD); # Carry flag is NOT set if there is a borrow + $(OVERFLOW) = sborrow(XDEST_W_AD, XSRC_W_AS + brw); + # Operation... + XDEST_W_AD = XDEST_W_AD - XSRC_W_AS - brw; + build tbl_wzero; + # Result Flags... + $(SIGN) = (XDEST_W_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:SUBCX.A XSRC_A_AS, XDEST_A_AD is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x7 & bow=1 & postIncrementStore) ... & XSRC_A_AS ... & XDEST_A_AD ... { + tmpd:$(REG_SIZE) = XDEST_A_AD; + brw:$(REG_SIZE) = 1 - zext( $(CARRY) ); + tmps:$(REG_SIZE) = XSRC_A_AS + brw; + tmp:$(REG_SIZE) = XDEST_A_AD - tmps; + XDEST_A_AD = sext(tmp[0,20]); + + setsubflags(XDEST_A_AD,tmps,tmpd); + build postIncrementStore; +} + +:SUBX.B XSRC_B_AS, XDEST_B_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x8 & bow=1 & tbl_bzero & postIncrementStore) ... & XSRC_B_AS ... & XDEST_B_AD ... { + # Operation Flags... + $(CARRY) = (XSRC_B_AS <= XDEST_B_AD); # Carry is NOT set if there is a borrow + $(OVERFLOW) = sborrow(XDEST_B_AD, XSRC_B_AS); # V Flag + # Operation... + XDEST_B_AD = XDEST_B_AD - XSRC_B_AS; + build tbl_bzero; + # Result Flags... + $(SIGN) = (XDEST_B_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_B_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:SUBX.W XSRC_W_AS, XDEST_W_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x8 & bow=0 & tbl_wzero & postIncrementStore) ... & XSRC_W_AS ... & XDEST_W_AD ... { + # Operation Flags... + $(CARRY) = (XSRC_W_AS <= XDEST_W_AD); # Carry is NOT set if there is a borrow + $(OVERFLOW) = sborrow(XDEST_W_AD, XSRC_W_AS); # V Flag + # Operation... + XDEST_W_AD = XDEST_W_AD - XSRC_W_AS; + build tbl_wzero; + # Result Flags... + $(SIGN) = (XDEST_W_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_W_AD == 0x0); # Z Flag + build postIncrementStore; +} + +:SUBX.A XSRC_A_AS, XDEST_A_AD is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x8 & bow=1 & postIncrementStore) ... & XSRC_A_AS ... & XDEST_A_AD ... { + tmpd:$(REG_SIZE) = XDEST_A_AD; + tmp:$(REG_SIZE) = XDEST_A_AD - XSRC_A_AS; + XDEST_A_AD = sext(tmp[0,20]); + + setsubflags(XDEST_A_AD,XSRC_A_AS,tmpd); + build postIncrementStore; +} + +:TSTX.B XDEST_B_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x9 & bow=1 & src16_8_4=0x3 & as=0x0 & postIncrement) ... & XDEST_B_AD ... { + # Operation Flags... + $(CARRY) = 1; # Carry is NOT set if there is a borrow + $(OVERFLOW) = 0; # V Flag + # Result Flags... + $(SIGN) = (XDEST_B_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_B_AD == 0x0); # Z Flag + build postIncrement; +} + +:TSTX.W XDEST_W_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x9 & bow=0 & src16_8_4=0x3 & as=0x0 & postIncrement) ... & XDEST_W_AD ... { + # Operation Flags... + $(CARRY) = 1; # Carry is NOT set if there is a borrow + $(OVERFLOW) = 0; # V Flag + # Result Flags... + $(SIGN) = (XDEST_W_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_W_AD == 0x0); # Z Flag + build postIncrement; +} + +:TSTX.A XDEST_A_AD is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x9 & bow=1 & src16_8_4=0x3 & as=0x0 & postIncrement) ... & XDEST_A_AD ... { + setsubflags(XDEST_A_AD,0:$(REG_SIZE),XDEST_A_AD); + build postIncrement; +} + +:XORX.B XSRC_B_AS, XDEST_B_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xE & bow=1 & tbl_bzero & postIncrementStore) ... & XSRC_B_AS ... & XDEST_B_AD ... { + # Operation Flags... + $(OVERFLOW) = ((XDEST_B_AD s< 0x0) && (XSRC_B_AS s< 0x0)) ; # V Flag + # Operation... + XDEST_B_AD = XDEST_B_AD ^ XSRC_B_AS; + build tbl_bzero; + # Result Flags... + $(SIGN) = (XDEST_B_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_B_AD == 0x0); # Z Flag + $(CARRY) = (XDEST_B_AD != 0x0); # C Flag + build postIncrementStore; +} + +:XORX.W XSRC_W_AS, XDEST_W_AD is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0xE & bow=0 & tbl_wzero & postIncrementStore) ... & XSRC_W_AS ... & XDEST_W_AD ... { + # Operation Flags... + $(OVERFLOW) = ((XDEST_W_AD s< 0x0) && (XSRC_W_AS s< 0x0)) ; # V Flag + # Operation... + XDEST_W_AD = XDEST_W_AD ^ XSRC_W_AS; + build tbl_wzero; + # Result Flags... + $(SIGN) = (XDEST_W_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_W_AD == 0x0); # Z Flag + $(CARRY) = (XDEST_W_AD != 0x0); # C Flag + build postIncrementStore; +} + +:XORX.A XSRC_A_AS, XDEST_A_AD is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0xE & bow=1 & postIncrementStore) ... & XSRC_A_AS ... & XDEST_A_AD ... { + # Operation Flags... + $(OVERFLOW) = ((XDEST_A_AD s< 0x0) && (XSRC_A_AS s< 0x0)) ; # V Flag + # Operation... + XDEST_A_AD = XDEST_A_AD ^ XSRC_A_AS; + XDEST_A_AD = sext(XDEST_A_AD[0,20]); + # Result Flags... + $(SIGN) = (XDEST_A_AD s< 0x0); # S Flag + $(ZERO) = (XDEST_A_AD == 0x0); # Z Flag + $(CARRY) = (XDEST_A_AD != 0x0); # C Flag + build postIncrementStore; +} + + +############################# +# +# Single Operand +# +############################# +# Repeat enabled + +# Note: The manual says PUSHX doesn't use extension word. The manual is *WRONG* +:PUSHX.B XRREG_B_AS is ctx_haveext=4 & ctx_al=1 & op16_12_4=0x1 & op16_8_4=0x2 & bow=0x1 & postRegIncrement & XRREG_B_AS { + + SP = SP - 0x2; + *:1 SP = XRREG_B_AS; + #Status bits are not affected + build postRegIncrement; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:PUSHX.W XRREG_W_AS is ctx_haveext=4 & ctx_al=1 & op16_12_4=0x1 & op16_8_4=0x2 & bow=0x0 & postRegIncrement & XRREG_W_AS { + + SP = SP - 0x2; + *:2 SP = XRREG_W_AS; + #Status bits are not affected + build postRegIncrement; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:PUSHX.A XRREG_A_AS is ctx_haveext=4 & ctx_al=0 & op16_12_4=0x1 & op16_8_4=0x2 & bow=0x1 & postRegIncrement & XRREG_A_AS { + + SP = SP - 0x4; + *:$(REG_SIZE) SP = XRREG_A_AS; + #Status bits are not affected + build postRegIncrement; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:RRAX.B XRREG_B_AS_DEST is ctx_haveext=4 & ctx_al=1 & op16_12_4=0x1 & op16_8_4=0x1 & bow=0x1 & postRegIncrement & XRREG_B_AS_DEST { + + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag (reset) + # Operation... + $(CARRY) = (XRREG_B_AS_DEST & 0x1); + XRREG_B_AS_DEST = XRREG_B_AS_DEST s>> 1; + # Result Flags... + $(SIGN) = (XRREG_B_AS_DEST s< 0x0); # S Flag + $(ZERO) = (XRREG_B_AS_DEST == 0x0); # Z Flag + build postRegIncrement; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:RRAX.W XRREG_W_AS_DEST is ctx_haveext=4 & ctx_al=1 & op16_12_4=0x1 & op16_8_4=0x1 & bow=0x0 & postRegIncrement & XRREG_W_AS_DEST { + + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag (reset) + # Operation... + $(CARRY) = XRREG_W_AS_DEST[0,1]; + XRREG_W_AS_DEST = XRREG_W_AS_DEST s>> 1; + # Result Flags... + $(SIGN) = (XRREG_W_AS_DEST s< 0x0); # S Flag + $(ZERO) = (XRREG_W_AS_DEST == 0x0); # Z Flag + build postRegIncrement; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:RRAX.A XRREG_A_AS_DEST is ctx_haveext=4 & ctx_al=0 & op16_12_4=0x1 & op16_8_4=0x1 & bow=0x1 & postRegIncrement & XRREG_A_AS_DEST { + + $(CARRY) = XRREG_A_AS_DEST[0,1]; + XRREG_A_AS_DEST = (XRREG_A_AS_DEST s>> 1); + $(OVERFLOW) = 0; + $(SIGN) = (XRREG_A_AS_DEST[19,1] != 0); + $(ZERO) = (XRREG_A_AS_DEST == 0); + build postRegIncrement; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:RRCX.B XRREG_B_AS_DEST is ctx_haveext=4 & ctx_al=1 & ctx_zc=0 & op16_12_4=0x1 & op16_8_4=0x0 & bow=0x1 & postRegIncrement & XRREG_B_AS_DEST { + + # Operation Flags... + $(OVERFLOW) = ((XRREG_B_AS_DEST != 0x0) && ($(CARRY) == 0x1)); # V Flag + # Operation... + tmp:1 = $(CARRY); + $(CARRY) = (XRREG_B_AS_DEST & 0x1); + XRREG_B_AS_DEST = ((tmp << 0x7) | (XRREG_B_AS_DEST >> 0x1)); + # Result Flags... + $(SIGN) = (XRREG_B_AS_DEST s< 0x0); # S Flag + $(ZERO) = (XRREG_B_AS_DEST == 0x0); # Z Flag + build postRegIncrement; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:RRUX.B XRREG_B_AS_DEST is ctx_haveext=4 & ctx_al=1 & ctx_zc=1 & op16_12_4=0x1 & op16_8_4=0x0 & bow=0x1 & postRegIncrement & XRREG_B_AS_DEST { + $(OVERFLOW) = 0; # Z Flag + + $(CARRY) = (XRREG_B_AS_DEST & 0x1); + XRREG_B_AS_DEST = (XRREG_B_AS_DEST >> 0x1); + # Result Flags... + $(SIGN) = (XRREG_B_AS_DEST s< 0x0); # S Flag + $(ZERO) = (XRREG_B_AS_DEST == 0x0); # Z Flag + build postRegIncrement; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:RRCX.W XRREG_W_AS_DEST is ctx_haveext=4 & ctx_al=1 & ctx_zc=0 & op16_12_4=0x1 & op16_8_4=0x0 & bow=0x0 & postRegIncrement & XRREG_W_AS_DEST { + + # Operation Flags... + $(OVERFLOW) = ((XRREG_W_AS_DEST != 0x0) && ($(CARRY) == 0x1)); # V Flag + # Operation... + tmp:1 = $(CARRY); + $(CARRY) = XRREG_W_AS_DEST[0,1]; + XRREG_W_AS_DEST = ((zext(tmp) << 0xF) | (XRREG_W_AS_DEST >> 0x1)); + # Result Flags... + $(SIGN) = (XRREG_W_AS_DEST s< 0x0); # S Flag + $(ZERO) = (XRREG_W_AS_DEST == 0x0); # Z Flag + build postRegIncrement; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:RRUX.W XRREG_W_AS_DEST is ctx_haveext=4 & ctx_al=1 & ctx_zc=1 & op16_12_4=0x1 & op16_8_4=0x0 & bow=0x0 & postRegIncrement & XRREG_W_AS_DEST { + $(OVERFLOW) = 0; # Z Flag + + $(CARRY) = XRREG_W_AS_DEST[0,1]; + XRREG_W_AS_DEST = (XRREG_W_AS_DEST >> 0x1); + # Result Flags... + $(SIGN) = (XRREG_W_AS_DEST s< 0x0); # S Flag + $(ZERO) = (XRREG_W_AS_DEST == 0x0); # Z Flag + build postRegIncrement; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:RRCX.A XRREG_A_AS_DEST is ctx_haveext=4 & ctx_al=0 & ctx_zc=0 & op16_12_4=0x1 & op16_8_4=0x0 & bow=0x1 & postRegIncrement & XRREG_A_AS_DEST { + + # Operation Flags... + $(OVERFLOW) = ((XRREG_A_AS_DEST != 0x0) && ($(CARRY) == 0x1)); # V Flag + # Operation... + tmp:1 = $(CARRY); + $(CARRY) = XRREG_A_AS_DEST[0,1]; + XRREG_A_AS_DEST = ((zext(tmp) << 0x13) | ((XRREG_A_AS_DEST >> 0x1) & 0xEFFFF)); + XRREG_A_AS_DEST = sext(XRREG_A_AS_DEST[0,20]); + # Result Flags... + $(SIGN) = (XRREG_A_AS_DEST s< 0x0); # S Flag + $(ZERO) = (XRREG_A_AS_DEST == 0x0); # Z Flag + build postRegIncrement; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:RRUX.A XRREG_A_AS_DEST is ctx_haveext=4 & ctx_al=0 & ctx_zc=1 & op16_12_4=0x1 & op16_8_4=0x0 & bow=0x1 & postRegIncrement & XRREG_A_AS_DEST { + $(OVERFLOW) = 0; # Z Flag + + $(CARRY) = XRREG_A_AS_DEST[0,1]; + XRREG_A_AS_DEST = (XRREG_A_AS_DEST >> 0x1) & 0xEFFFF; + # Result Flags... + $(SIGN) = (XRREG_A_AS_DEST s< 0x0); # S Flag + $(ZERO) = (XRREG_A_AS_DEST == 0x0); # Z Flag + build postRegIncrement; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:SWPBX.W XRREG_W_AS_DEST is ctx_haveext=4 & ctx_al=1 & op16_12_4=0x1 & op16_8_4=0x0 & op16_7_1=0x1 & as=0x0 & bow=0x0 & postRegIncrement & XRREG_W_AS_DEST { + + lowByte:1 = XRREG_W_AS_DEST[0,8]; + highByte:1 = XRREG_W_AS_DEST[8,8]; + XRREG_W_AS_DEST = (((zext(lowByte)) << 0x8) | zext(highByte)); + #Status bits are not affected + build postRegIncrement; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:SWPBX.A XRREG_A_AS_DEST2 is ctx_haveext=4 & ctx_al=0 & op16_12_4=0x1 & op16_8_4=0x0 & op16_7_1=0x1 & as=0x0 & bow=0x0 & postRegIncrement & XRREG_A_AS_DEST2 { + + lowByte:1 = XRREG_A_AS_DEST2[0,8]; + highByte:1 = XRREG_A_AS_DEST2[8,8]; + XRREG_A_AS_DEST2[8,8] = lowByte; + XRREG_A_AS_DEST2[0,8] = highByte; + XRREG_A_AS_DEST2 = zext(XRREG_A_AS_DEST2[0,20]); + build postRegIncrement; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:SXTX.W XRREG_W_AS_DEST is ctx_haveext=4 & ctx_al=1 & op16_12_4=0x1 & op16_8_4=0x1 & op16_7_1=0x1 & as=0x0 & bow=0x0 & postRegIncrement & XRREG_W_AS_DEST { + + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag + # Operation... + XRREG_W_AS_DEST = sext(XRREG_W_AS_DEST:1); + # Result Flags... + $(SIGN) = (XRREG_W_AS_DEST s< 0x0); # S Flag + $(ZERO) = (XRREG_W_AS_DEST == 0x0); # Z Flag + $(CARRY) = (XRREG_W_AS_DEST != 0x0); # C Flag + build postRegIncrement; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +:SXTX.A XRREG_A_AS_DEST2 is ctx_haveext=4 & ctx_al=0 & op16_12_4=0x1 & op16_8_4=0x1 & op16_7_1=0x1 & as=0x0 & bow=0x0 & postRegIncrement & XRREG_A_AS_DEST2 { + + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag + # Operation... + XRREG_A_AS_DEST2 = sext(XRREG_A_AS_DEST2:1); + # Result Flags... + $(SIGN) = (XRREG_A_AS_DEST2 s< 0x0); # S Flag + $(ZERO) = (XRREG_A_AS_DEST2 == 0x0); # Z Flag + $(CARRY) = (XRREG_A_AS_DEST2 != 0x0); # C Flag + build postRegIncrement; + if (CNT == 0) goto inst_next; + CNT = CNT - 1; + goto ; +} + +############################# +# No Repeat +:PUSHX.B XREG_B_AS is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x1 & op16_8_4=0x2 & op16_7_1=0x0 & bow=0x1 & postRegIncrement) ... & XREG_B_AS { + SP = SP - 0x2; + *:1 SP = XREG_B_AS; + #Status bits are not affected + build postRegIncrement; +} + +:PUSHX.W XREG_W_AS is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x1 & op16_8_4=0x2 & op16_7_1=0x0 & bow=0x0 & postRegIncrement) ... & XREG_W_AS { + SP = SP - 0x2; + *:2 SP = XREG_W_AS; + #Status bits are not affected + build postRegIncrement; +} + +:PUSHX.A XREG_A_AS is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x1 & op16_8_4=0x2 & op16_7_1=0x0 & bow=0x1 & postRegIncrement) ... & XREG_A_AS { + SP = SP - 0x4; + *:$(REG_SIZE) SP = XREG_A_AS; + build postRegIncrement; +} + +:RRAX.B XREG_B_AS_DEST is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x1 & op16_8_4=0x1 & op16_7_1=0x0 & bow=0x1 & postRegIncrement) ... & XREG_B_AS_DEST { + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag (reset) + # Operation... + $(CARRY) = (XREG_B_AS_DEST & 0x1); + XREG_B_AS_DEST = XREG_B_AS_DEST s>> 1; + # Result Flags... + $(SIGN) = (XREG_B_AS_DEST s< 0x0); # S Flag + $(ZERO) = (XREG_B_AS_DEST == 0x0); # Z Flag + build postRegIncrement; +} + +:RRAX.W XREG_W_AS_DEST is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x1 & op16_8_4=0x1 & op16_7_1=0x0 & bow=0x0 & postRegIncrement) ... & XREG_W_AS_DEST { + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag (reset) + # Operation... + $(CARRY) = XREG_W_AS_DEST[0,1]; + XREG_W_AS_DEST = XREG_W_AS_DEST s>> 1; + # Result Flags... + $(SIGN) = (XREG_W_AS_DEST s< 0x0); # S Flag + $(ZERO) = (XREG_W_AS_DEST == 0x0); # Z Flag + build postRegIncrement; +} + +:RRAX.A XREG_A_AS_DEST is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x1 & op16_8_4=0x1 & op16_7_1=0x0 & bow=0x1 & postRegIncrement) ... & XREG_A_AS_DEST { + $(CARRY) = XREG_A_AS_DEST[0,1]; + XREG_A_AS_DEST = (XREG_A_AS_DEST s>> 1); + $(OVERFLOW) = 0; + $(SIGN) = (XREG_A_AS_DEST[19,1] != 0); + $(ZERO) = (XREG_A_AS_DEST == 0); + build postRegIncrement; +} + +:RRCX.B XREG_B_AS_DEST is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x1 & op16_8_4=0x0 & op16_7_1=0x0 & bow=0x1 & postRegIncrement) ... & XREG_B_AS_DEST { + # Operation Flags... + $(OVERFLOW) = ((XREG_B_AS_DEST != 0x0) && ($(CARRY) == 0x1)); # V Flag + # Operation... + tmp:1 = $(CARRY); + $(CARRY) = (XREG_B_AS_DEST & 0x1); + XREG_B_AS_DEST = ((tmp << 0x7) | (XREG_B_AS_DEST >> 0x1)); + # Result Flags... + $(SIGN) = (XREG_B_AS_DEST s< 0x0); # S Flag + $(ZERO) = (XREG_B_AS_DEST == 0x0); # Z Flag + build postRegIncrement; +} + +:RRCX.W XREG_W_AS_DEST is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x1 & op16_8_4=0x0 & op16_7_1=0x0 & bow=0x0 & postRegIncrement) ... & XREG_W_AS_DEST { + # Operation Flags... + $(OVERFLOW) = ((XREG_W_AS_DEST != 0x0) && ($(CARRY) == 0x1)); # V Flag + # Operation... + tmp:1 = $(CARRY); + $(CARRY) = XREG_W_AS_DEST[0,1]; + XREG_W_AS_DEST = ((zext(tmp) << 0xF) | (XREG_W_AS_DEST >> 0x1)); + # Result Flags... + $(SIGN) = (XREG_W_AS_DEST s< 0x0); # S Flag + $(ZERO) = (XREG_W_AS_DEST == 0x0); # Z Flag + build postRegIncrement; +} + +:RRCX.A XREG_A_AS_DEST is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x1 & op16_8_4=0x0 & op16_7_1=0x0 & bow=0x1 & postRegIncrement) ... & XREG_A_AS_DEST { + # Operation Flags... + $(OVERFLOW) = ((XREG_A_AS_DEST != 0x0) && ($(CARRY) == 0x1)); # V Flag + # Operation... + tmp:1 = $(CARRY); + $(CARRY) = XREG_A_AS_DEST[0,1]; + XREG_A_AS_DEST = ((zext(tmp) << 0x13) | ((XREG_A_AS_DEST >> 0x1) & 0xEFFFF)); + XREG_A_AS_DEST = sext(XREG_A_AS_DEST[0,20]); + # Result Flags... + $(SIGN) = (XREG_A_AS_DEST s< 0x0); # S Flag + $(ZERO) = (XREG_A_AS_DEST == 0x0); # Z Flag + build postRegIncrement; +} + +:SWPBX.W XREG_W_AS_DEST is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x1 & op16_8_4=0x0 & op16_7_1=0x1 & bow=0x0 & postRegIncrement) ... & XREG_W_AS_DEST { + lowByte:1 = XREG_W_AS_DEST[0,8]; + highByte:1 = XREG_W_AS_DEST[8,8]; + XREG_W_AS_DEST = (((zext(lowByte)) << 0x8) | zext(highByte)); + #Status bits are not affected + build postRegIncrement; +} + +# Yes, for SXTX and SWPB, the normal width selectors are different. Hence, for the A versions, we have a different dest reg subtable. +:SWPBX.A XREG_A_AS_DEST2 is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x1 & op16_8_4=0x0 & op16_7_1=0x1 & bow=0x0 & postRegIncrement) ... & XREG_A_AS_DEST2 { + lowByte:1 = XREG_A_AS_DEST2[0,8]; + highByte:1 = XREG_A_AS_DEST2[8,8]; + XREG_A_AS_DEST2[8,8] = lowByte; + XREG_A_AS_DEST2[0,8] = highByte; + XREG_A_AS_DEST2 = zext(XREG_A_AS_DEST2[0,20]); + build postRegIncrement; +} + +:SXTX.W XREG_W_AS_DEST is ctx_haveext=7 & ctx_al=1 & (op16_12_4=0x1 & op16_8_4=0x1 & op16_7_1=0x1 & bow=0x0 & postRegIncrement) ... & XREG_W_AS_DEST { + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag + # Operation... + XREG_W_AS_DEST = sext(XREG_W_AS_DEST:1); + # Result Flags... + $(SIGN) = (XREG_W_AS_DEST s< 0x0); # S Flag + $(ZERO) = (XREG_W_AS_DEST == 0x0); # Z Flag + $(CARRY) = (XREG_W_AS_DEST != 0x0); # C Flag + build postRegIncrement; +} + +# Yes, for SXTX and SWPB, the normal width selectors are different. Hence, for the A versions, we have a different dest reg subtable. +:SXTX.A XREG_A_AS_DEST2 is ctx_haveext=7 & ctx_al=0 & (op16_12_4=0x1 & op16_8_4=0x1 & op16_7_1=0x1 & bow=0x0 & postRegIncrement) ... & XREG_A_AS_DEST2 { + # Operation Flags... + $(OVERFLOW) = 0x0; # V Flag + # Operation... + XREG_A_AS_DEST2 = sext(XREG_A_AS_DEST2:1); + # Result Flags... + $(SIGN) = (XREG_A_AS_DEST2 s< 0x0); # S Flag + $(ZERO) = (XREG_A_AS_DEST2 == 0x0); # Z Flag + $(CARRY) = (XREG_A_AS_DEST2 != 0x0); # C Flag + build postRegIncrement; +} diff --git a/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/TI_MSP430.cspec b/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/TI_MSP430.cspec new file mode 100644 index 0000000..8d909ee --- /dev/null +++ b/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/TI_MSP430.cspec @@ -0,0 +1,55 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/TI_MSP430.ldefs b/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/TI_MSP430.ldefs new file mode 100644 index 0000000..e8bfbcb --- /dev/null +++ b/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/TI_MSP430.ldefs @@ -0,0 +1,31 @@ + + + + + TI MSP430 16-Bit MicroController + + + + + + TI MSP430X 20-Bit MicroController + + + + diff --git a/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/TI_MSP430.pspec b/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/TI_MSP430.pspec new file mode 100644 index 0000000..5361848 --- /dev/null +++ b/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/TI_MSP430.pspec @@ -0,0 +1,195 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/TI_MSP430.slaspec b/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/TI_MSP430.slaspec new file mode 100644 index 0000000..682ee3f --- /dev/null +++ b/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/TI_MSP430.slaspec @@ -0,0 +1,4 @@ +@define ENDIAN "little" +@define REG_SIZE "2" + +@include "TI430Common.sinc" diff --git a/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/TI_MSP430X.cspec b/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/TI_MSP430X.cspec new file mode 100644 index 0000000..85cacd4 --- /dev/null +++ b/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/TI_MSP430X.cspec @@ -0,0 +1,65 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/TI_MSP430X.slaspec b/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/TI_MSP430X.slaspec new file mode 100644 index 0000000..1d2b6ff --- /dev/null +++ b/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/TI_MSP430X.slaspec @@ -0,0 +1,5 @@ +@define ENDIAN "little" +@define REG_SIZE "4" + +@include "TI430Common.sinc" +@include "TI430X.sinc" diff --git a/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/ti_msp430.opinion b/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/ti_msp430.opinion new file mode 100644 index 0000000..0b73ea9 --- /dev/null +++ b/python/icicle/Ghidra/Processors/TI_MSP430/data/languages/ti_msp430.opinion @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/old/ToyV00BE64.lang b/python/icicle/Ghidra/Processors/Toy/data/languages/old/ToyV00BE64.lang new file mode 100644 index 0000000..d97c395 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/old/ToyV00BE64.lang @@ -0,0 +1,38 @@ + + + + + Toy:BE:64:default + Toy + default + 64 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/old/ToyV0BE64.trans b/python/icicle/Ghidra/Processors/Toy/data/languages/old/ToyV0BE64.trans new file mode 100644 index 0000000..ea7226e --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/old/ToyV0BE64.trans @@ -0,0 +1,20 @@ + + + Toy:BE:64:default + Toy:BE:64:default + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/old/ToyV0LE64.lang b/python/icicle/Ghidra/Processors/Toy/data/languages/old/ToyV0LE64.lang new file mode 100644 index 0000000..a8426c5 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/old/ToyV0LE64.lang @@ -0,0 +1,38 @@ + + + + + Toy:LE:64:default + Toy + default + 64 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/old/ToyV0LE64.trans b/python/icicle/Ghidra/Processors/Toy/data/languages/old/ToyV0LE64.trans new file mode 100644 index 0000000..fb5b625 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/old/ToyV0LE64.trans @@ -0,0 +1,20 @@ + + + Toy:LE:64:default + Toy:LE:64:default + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/old/v01stuff/toy.cspec b/python/icicle/Ghidra/Processors/Toy/data/languages/old/v01stuff/toy.cspec new file mode 100644 index 0000000..bd967cb --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/old/v01stuff/toy.cspec @@ -0,0 +1,69 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/old/v01stuff/toy.ldefs_v01 b/python/icicle/Ghidra/Processors/Toy/data/languages/old/v01stuff/toy.ldefs_v01 new file mode 100644 index 0000000..dc039be --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/old/v01stuff/toy.ldefs_v01 @@ -0,0 +1,26 @@ + + + + + Toy (test) processor 64-bit big-endian + + + + Toy (test) processor 64-bit little-endian + + + diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/old/v01stuff/toy.sinc b/python/icicle/Ghidra/Processors/Toy/data/languages/old/v01stuff/toy.sinc new file mode 100644 index 0000000..be41ed9 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/old/v01stuff/toy.sinc @@ -0,0 +1,25 @@ +# Main slaspec must define endianess and alignment + +@ifndef WORDSIZE +@define WORDSIZE "1" +@endif + +define space ROM type=ram_space size=$(SIZE) wordsize=$(WORDSIZE) default; + +define space register type=register_space size=2; + +define register offset=0x1000 size=$(SIZE) [ + a0 a1 a2 a3 a4 a5 a6 a7 + a8 a9 a10 a11 a12 sp lr pc +]; + +# STATUS REGISTER MAP: (LOW) +# C - CARRY +# Z - ZERO +# N - NEGATIVE +# V - OVERFLOW + +define register offset=0x1100 size=1 [ + C Z N V +]; + diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/old/v01stuff/toy64.cspec b/python/icicle/Ghidra/Processors/Toy/data/languages/old/v01stuff/toy64.cspec new file mode 100644 index 0000000..78cf561 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/old/v01stuff/toy64.cspec @@ -0,0 +1,69 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/old/v01stuff/toyInstructions.sinc b/python/icicle/Ghidra/Processors/Toy/data/languages/old/v01stuff/toyInstructions.sinc new file mode 100644 index 0000000..c875d20 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/old/v01stuff/toyInstructions.sinc @@ -0,0 +1,200 @@ +#### immediates +# 0iii dddd iiii iiii # imm rd, i load 11-bit unsigned int into rd +# 10nn dddd nnnn nnnn # simm rd, n load 10-bit signed int into rd +# +#### arithmetic +# 1100 0000 ssss tttt # add rs, rt rs = rs + rt +# 1100 0001 ssss tttt # sub rs, rt rs = rs - rt +# 1100 0010 ssss tttt # rsub rs, rt rs = rt - rs +# 1100 0011 ssss tttt # mul rs, rt rs = rs * rt +# 1100 0100 ssss tttt # div rs, rt rs = rs / rt +# 1100 0101 ssss tttt # mod rs, rt rs = rs % rt +# 1100 0110 ssss tttt # cmp rs, rt (set status only based on signed compare (rs - rt)) +# 1100 0111 ssss tttt # ucmp rs, rt (set status only based on unsigned compare (rs - rt)) +# +# 1100 1000 ssss nnnn # add rs, n rs = rs + n +# 1100 1001 ssss nnnn # sub rs, n rs = rs - n +# 1100 1010 ssss nnnn # rsub rs, n rs = n - rs +# 1100 1011 ssss nnnn # mul rs, n rs = rs * n +# 1100 1100 ssss nnnn # div rs, n rs = rs / n +# 1100 1101 ssss iiii # mod rs, i rs = rs % i +# 1100 1110 ssss nnnn # cmp rs, n (set status only based on signed compare (rs - n)) +# 1100 1111 ssss iiii # ucmp rs, i (set status only based on unsigned compare (rs - i)) +# +#### logic +# 1101 0000 ssss tttt # and rs, rt rs = rs & rt +# 1101 0001 ssss tttt # or rs, rt rs = rs | rt +# 1101 0010 ssss tttt # xor rs, rt rs = rs ^ rt +# 1101 0011 ssss tttt # lsr rs, rt rs = rs >> rt +# 1101 0100 ssss tttt # asr rs, rt rs = rs s>> rt +# 1101 0101 ssss tttt # lsl rs, rt rs = rs << rt +# 1101 1000 ssss tttt # saa rs, rt rs = (rs << 11) | rt +# +# 1101 1011 ssss iiii # lsr rs, i rs = rs >> i +# 1101 1100 ssss iiii # asr rs, i rs = rs s>> i +# 1101 1101 ssss iiii # lsl rs, i rs = rs << i +# 1101 1110 ssss 0000 # inv rs rs = ~rs +# 1101 1110 ssss 0001 # neg rs rs = -rs +# +#### memory +# 1101 0110 ssss tttt # load rs, [rt] rs = [rt] +# 1101 0111 ssss tttt # store [rs], rt [rs] = rt +# 1101 1111 ssss tttt # mov rs, rt rs = rt +# +#### flow +# 1110 nnnn nnnn 0ccc # brcc n if ccc goto pc + n +# 1110 nnnn nnnn 1ccc # brdscc n if ccc goto pc + n with delay slot +# 1111 0000 ssss 0ccc # brcc rs if ccc goto rs & ~1 +# 1111 0001 ssss 0ccc # brdscc rs if ccc goto rs & ~1 with delay slot +# 1111 0010 ssss 0000 # push rs push rs +# 1111 0011 ssss 0000 # pop rs pop rs +# 1111 0100 0000 0000 # ret return +# 1111 0101 nnnn nnnn # callds n call n with delay slot +# 1111 0110 ssss 0000 # call rs call rs +# 1111 1nnn nnnn nnnn # call n call n +# +#### RESERVED +# 1101 1001 xxxx xxxx # RESERVED BANK +# 1101 1010 xxxx xxxx # RESERVED BANK +# 1111 0111 xxxx xxxx # RESERVED BANK + + +define token instr(16) + op1515 = (15, 15) + op1415 = (14, 15) + op1215 = (12, 15) + op1111 = (11, 11) + op0811 = (8, 11) + op0007 = (0, 7) + op0003 = (0, 3) + op0303 = (3, 3) + rd = (8, 11) + rs = (4, 7) + rt = (0, 3) + imm1214 = (12, 14) + imm0007 = (0, 7) + imm0003 = (0, 3) + simm1213 = (12, 13) signed + simm0010 = (0, 10) signed + simm0411 = (4, 11) signed + simm0007 = (0, 7) signed + simm0003 = (0, 3) signed + cc0911 = (9, 11) + cc0002 = (0, 2) +; + +attach variables [ rd rs rt ] [ + a0 a1 a2 a3 a4 a5 a6 a7 + a8 a9 a10 a11 a12 sp lr pc +]; + +# addressing mode subs + +Simm4: "#"^simm0003 is simm0003 { export *[const]:$(SIZE) simm0003; } +Simm10: "#"^computed is simm1213 & imm0007 [ computed = (simm1213 << 8) | imm0007; ] { export *[const]:$(SIZE) computed; } + +Imm4: "#"^imm0003 is imm0003 { export *[const]:$(SIZE) imm0003; } +Imm11: "#"^computed is imm1214 & imm0007 [ computed = (imm1214 << 8) | imm0007; ] { export *[const]:$(SIZE) computed; } + +Rel8: addr is simm0007 [ addr = inst_start + simm0007; ] { export *:$(SIZE) addr; } +Rel82: addr is simm0411 [ addr = inst_start + simm0411; ] { export *:$(SIZE) addr; } +Rel11: addr is simm0010 [ addr = inst_start + simm0010; ] { export *:$(SIZE) addr; } + +RS: [rs] is rs { export *[ROM]:$(SIZE) rs; } +RT: [rt] is rt { export *[ROM]:$(SIZE) rt; } + +CC: "eq" is cc0002=0x0 { export Z; } +CC: "ne" is cc0002=0x1 { tmp = !Z; export tmp; } +CC: "lt" is cc0002=0x2 { tmp = N != V; export tmp; } +CC: "le" is cc0002=0x3 { tmp = Z || (N != V); export tmp; } +CC: "lo" is cc0002=0x4 { export C; } +CC: "mi" is cc0002=0x5 { export N; } +CC: "vs" is cc0002=0x6 { export V; } +CC: "" is cc0002=0x7 { export 1:1; } + +COND: CC is CC { if (!CC) goto inst_next; } +COND: CC is CC & cc0002=0x7 { } # unconditional + +macro resultflags(result) { + N = result s< 0; + Z = result == 0; +} +macro addflags(a, b) { + C = carry(a, b); + V = scarry(a, b); +} +macro subflags(a, b) { + C = a s< b; + V = sborrow(a, b); +} +macro logicflags() { + C = 0; + V = 0; +} + +# operations + +:imm rd, Imm11 is $(INSTR_PHASE) op1515=0x0 & rd & Imm11 { logicflags(); rd = Imm11; resultflags(rd); } +:simm rd, Simm10 is $(INSTR_PHASE) op1415=0x2 & rd & Simm10 { logicflags(); rd = Simm10; resultflags(rd); } + +:add rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x0 & rs & rt { addflags(rs, rt); rs = rs + rt; resultflags(rs); } +:sub rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x1 & rs & rt { subflags(rs, rt); rs = rs - rt; resultflags(rs); } +:rsub rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x2 & rs & rt { subflags(rt, rs); rs = rt - rs; resultflags(rs); } +:mul rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x3 & rs & rt { rs = rs * rt; resultflags(rs); } # fix C & V +:div rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x4 & rs & rt { rs = rs / rt; resultflags(rs); } # fix C & V +:mod rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x5 & rs & rt { rs = rs % rt; resultflags(rs); } # fix C & V +:cmp rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x6 & rs & rt { subflags(rs, rt); tmp:$(SIZE) = rs - rt; resultflags(tmp); } +:ucmp rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x7 & rs & rt { logicflags(); N = rs < rt; Z = rs == rt; } + +:add rs, Simm4 is $(INSTR_PHASE) op1215=0xc & op0811=0x8 & rs & Simm4 { addflags(rs, Simm4); rs = rs + Simm4; resultflags(rs); } +:sub rs, Simm4 is $(INSTR_PHASE) op1215=0xc & op0811=0x9 & rs & Simm4 { subflags(rs, Simm4); rs = rs - Simm4; resultflags(rs); } +:rsub rs, Simm4 is $(INSTR_PHASE) op1215=0xc & op0811=0xa & rs & Simm4 { subflags(Simm4, rs); rs = Simm4 - rs; resultflags(rs); } +:mul rs, Simm4 is $(INSTR_PHASE) op1215=0xc & op0811=0xb & rs & Simm4 { rs = rs * Simm4; resultflags(rs); } # fix C & V +:div rs, Simm4 is $(INSTR_PHASE) op1215=0xc & op0811=0xc & rs & Simm4 { rs = rs / Simm4; resultflags(rs); } # fix C & V +:mod rs, Imm4 is $(INSTR_PHASE) op1215=0xc & op0811=0xd & rs & Imm4 { rs = rs % Imm4; resultflags(rs); } # fix C & V +:cmp rs, Simm4 is $(INSTR_PHASE) op1215=0xc & op0811=0xe & rs & Simm4 { subflags(rs, Simm4); tmp:$(SIZE) = rs - Simm4; resultflags(tmp); } +:ucmp rs, Imm4 is $(INSTR_PHASE) op1215=0xc & op0811=0xf & rs & Imm4 { logicflags(); N = rs < Imm4; Z = rs == Imm4; } + +:and rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x0 & rs & rt { logicflags(); rs = rs & rt; resultflags(rs); } +:or rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x1 & rs & rt { logicflags(); rs = rs | rt; resultflags(rs); } +:xor rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x2 & rs & rt { logicflags(); rs = rs ^ rt; resultflags(rs); } +:lsr rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x3 & rs & rt { logicflags(); rs = rs >> rt; resultflags(rs); } +:asr rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x4 & rs & rt { logicflags(); rs = rs s>> rt; resultflags(rs); } +:lsl rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x5 & rs & rt { logicflags(); rs = rs << rt; resultflags(rs); } + +# saa == shift and accumulate; very useful for building up a 32 bit or 64 bit value in pieces, like: +# imm r12, #32b +# imm r11, #7d7 +# saa r12, r11 +# imm r11, #2be +# saa r12, r11 +# +# now r12 contains '0xcafebabe' (decompiler reconstitutes the pieces seamlessly) + +:saa rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x8 & rs & rt { logicflags(); rs = (rs << 11) | rt; resultflags(rs); } + +:lsr rs, Imm4 is $(INSTR_PHASE) op1215=0xd & op0811=0xb & rs & Imm4 { logicflags(); rs = rs >> Imm4; resultflags(rs); } +:asr rs, Imm4 is $(INSTR_PHASE) op1215=0xd & op0811=0xc & rs & Imm4 { logicflags(); rs = rs s>> Imm4; resultflags(rs); } +:lsl rs, Imm4 is $(INSTR_PHASE) op1215=0xd & op0811=0xd & rs & Imm4 { logicflags(); rs = rs << Imm4; resultflags(rs); } # fix C & V +:inv rs is $(INSTR_PHASE) op1215=0xd & op0811=0xe & rs & op0003=0x0 { logicflags(); rs = ~rs; resultflags(rs); } +:neg rs is $(INSTR_PHASE) op1215=0xd & op0811=0xe & rs & op0003=0x1 { logicflags(); rs = -rs; resultflags(rs); } + +:load rs, RT is $(INSTR_PHASE) op1215=0xd & op0811=0x6 & rs & RT { rs = RT; logicflags(); resultflags(rs); } +:store RS, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x7 & RS & rt { RS = rt; logicflags(); resultflags(rt); } +:mov rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0xf & rs & rt { rs = rt; logicflags(); resultflags(rs); } + +:br^COND Rel82 is $(INSTR_PHASE) op1215=0xe & op0303=0x0 & COND & Rel82 { build COND; goto Rel82; } +:brds^COND Rel82 is $(INSTR_PHASE) op1215=0xe & op0303=0x1 & COND & Rel82 { build COND; delayslot(1); goto Rel82; } +:br^COND rs is $(INSTR_PHASE) op1215=0xf & op0811=0x0 & COND & rs & op0303=0x0 { build COND; goto [rs]; } +:brds^COND rs is $(INSTR_PHASE) op1215=0xf & op0811=0x1 & COND & rs & op0303=0x0 { build COND; delayslot(1); goto [rs]; } +@ifdef POS_STACK +:push rs is $(INSTR_PHASE) op1215=0xf & op0811=0x2 & rs & op0003=0x0 { *[ROM]:$(SIZE) sp = rs; sp = sp + $(SIZE); logicflags(); resultflags(rs); } +:pop rs is $(INSTR_PHASE) op1215=0xf & op0811=0x3 & rs & op0003=0x0 { sp = sp - $(SIZE); rs = *[ROM]:$(SIZE) sp; logicflags(); resultflags(rs); } +@else +:push rs is $(INSTR_PHASE) op1215=0xf & op0811=0x2 & rs & op0003=0x0 { *[ROM]:$(SIZE) sp = rs; sp = sp - $(SIZE); logicflags(); resultflags(rs); } +:pop rs is $(INSTR_PHASE) op1215=0xf & op0811=0x3 & rs & op0003=0x0 { sp = sp + $(SIZE); rs = *[ROM]:$(SIZE) sp; logicflags(); resultflags(rs); } +@endif +:ret is $(INSTR_PHASE) op1215=0xf & op0811=0x4 & op0007=0x0 { return [lr]; } +:callds Rel8 is $(INSTR_PHASE) op1215=0xf & op0811=0x5 & Rel8 { delayslot(1); lr = inst_next; call Rel8; } +:call rs is $(INSTR_PHASE) op1215=0xf & op0811=0x6 & rs & op0003=0x0 { lr = inst_next; call [rs]; } +:call Rel11 is $(INSTR_PHASE) op1215=0xf & op1111=0x1 & Rel11 { lr = inst_next; call Rel11; } diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/old/v01stuff/toyPosStack.cspec b/python/icicle/Ghidra/Processors/Toy/data/languages/old/v01stuff/toyPosStack.cspec new file mode 100644 index 0000000..9f4784a --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/old/v01stuff/toyPosStack.cspec @@ -0,0 +1,69 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/toy.cspec b/python/icicle/Ghidra/Processors/Toy/data/languages/toy.cspec new file mode 100644 index 0000000..c158743 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/toy.cspec @@ -0,0 +1,99 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/toy.ldefs b/python/icicle/Ghidra/Processors/Toy/data/languages/toy.ldefs new file mode 100644 index 0000000..7bd3ec7 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/toy.ldefs @@ -0,0 +1,137 @@ + + + + + Toy (test) processor 32-bit big-endian + + + + Toy (test) processor 32-bit big-endian + + + + Toy (test) processor 32-bit little-endian + + + + Toy (test) processor 32-bit big-endian (wordsize=2) + + + + Toy (test) processor 32-bit little-endian (wordsize=2) + + + + Toy (test) processor 64-bit big-endian + + + + + Toy (test) processor 64-bit big-endian Harvard + + + + Toy (test) processor 64-bit little-endian + + + + Toy (test-builder) processor 32-bit big-endian + + + + Toy (test-builder) processor 32-bit little-endian + + + + Toy (test-builder) processor 32-bit big-endian word-aligned + + + + Toy (test-builder) processor 32-bit little-endian word-aligned + + + diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/toy.pspec b/python/icicle/Ghidra/Processors/Toy/data/languages/toy.pspec new file mode 100644 index 0000000..5205bc9 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/toy.pspec @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/toy.sinc b/python/icicle/Ghidra/Processors/Toy/data/languages/toy.sinc new file mode 100644 index 0000000..babaca0 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/toy.sinc @@ -0,0 +1,51 @@ +# Main slaspec must define ENDIAN and ALIGN + +@ifndef WORDSIZE +@define WORDSIZE "1" +@endif + +@ifndef ALIGN +@define ALIGN "1" +@endif + +define endian=$(ENDIAN); +define alignment=$(ALIGN); + +define space ram type=ram_space size=$(SIZE) wordsize=$(WORDSIZE) default; + +define space register type=register_space size=2; + +define register offset=0x1000 size=$(SIZE) [ + r0 r1 r2 r3 r4 r5 r6 r7 + r8 r9 r10 r11 r12 sp lr pc +]; + +# STATUS REGISTER MAP: (LOW) +# C - CARRY +# Z - ZERO +# N - NEGATIVE +# V - OVERFLOW + +define register offset=0x1100 size=1 [ + C Z N V +]; + + +@if SIZE == "4" +@define HALFSIZE "2" +@endif +@if SIZE == "8" +@define HALFSIZE "4" +@endif + +@if ENDIAN == "little" +define register offset=0x1000 size=$(HALFSIZE) [ + r0l r0h r1l r1h r2l r2h r3l r3h r4l r4h r5l r5h r6l r6h r7l r7h + r8l r8h r9l r9h r10l r10h r11l r11h r12l r12h spl sph lrl lrh pcl pch +]; +@else # ENDIAN == "big" +define register offset=0x1000 size=$(HALFSIZE) [ + r0h r0l r1h r1l r2h r2l r3h r3l r4h r4l r5h r5l r6h r6l r7h r7l + r8h r8l r9h r9l r10h r10l r11h r11l r12h r12l sph spl lrh lrl pch pcl +]; +@endif # ENDIAN diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/toy64-long8.cspec b/python/icicle/Ghidra/Processors/Toy/data/languages/toy64-long8.cspec new file mode 100644 index 0000000..4667944 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/toy64-long8.cspec @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/toy64.cspec b/python/icicle/Ghidra/Processors/Toy/data/languages/toy64.cspec new file mode 100644 index 0000000..029b4ce --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/toy64.cspec @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/toy64_be.slaspec b/python/icicle/Ghidra/Processors/Toy/data/languages/toy64_be.slaspec new file mode 100644 index 0000000..5fda651 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/toy64_be.slaspec @@ -0,0 +1,8 @@ +@define ENDIAN "big" +@define SIZE "8" + +@define INSTR_PHASE "" # not used by basic toy language +@define DATA_SPACE "ram" + +@include "toy.sinc" +@include "toyInstructions.sinc" diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/toy64_be_harvard.slaspec b/python/icicle/Ghidra/Processors/Toy/data/languages/toy64_be_harvard.slaspec new file mode 100644 index 0000000..25c5e90 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/toy64_be_harvard.slaspec @@ -0,0 +1,11 @@ +@define ENDIAN "big" +@define SIZE "8" + +@define INSTR_PHASE "" # not used by basic toy language +@define DATA_SPACE "data" + +@include "toy.sinc" + +define space data type=ram_space size=$(SIZE) wordsize=$(WORDSIZE); + +@include "toyInstructions.sinc" diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/toy64_le.slaspec b/python/icicle/Ghidra/Processors/Toy/data/languages/toy64_le.slaspec new file mode 100644 index 0000000..8c0925f --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/toy64_le.slaspec @@ -0,0 +1,8 @@ +@define ENDIAN "little" +@define SIZE "8" + +@define INSTR_PHASE "" # not used by basic toy language +@define DATA_SPACE "ram" + +@include "toy.sinc" +@include "toyInstructions.sinc" diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/toyInstructions.sinc b/python/icicle/Ghidra/Processors/Toy/data/languages/toyInstructions.sinc new file mode 100644 index 0000000..119108b --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/toyInstructions.sinc @@ -0,0 +1,232 @@ +#### load immediate 0000 000x xxxx xxxx +# 00ii dddd iiii iiii # imm rd, i load 10-bit unsigned int into rd +# 01nn dddd nnnn nnnn # simm rd, n load 10-bit signed int into rd +# +#### misc 100x xxxx xxxx xxxx +# 1000 0000 0000 0ccc # skcc if ccc goto inst_next2 (conditional skip instruction) +# +#### arithmetic 1100 xxxx +# 1100 0000 ssss tttt # add rs, rt rs = rs + rt +# 1100 0001 ssss tttt # sub rs, rt rs = rs - rt +# 1100 0010 ssss tttt # rsub rs, rt rs = rt - rs +# 1100 0011 ssss tttt # mul rs, rt rs = rs * rt +# 1100 0100 ssss tttt # div rs, rt rs = rs / rt +# 1100 0101 ssss tttt # mod rs, rt rs = rs % rt +# 1100 0110 ssss tttt # cmp rs, rt (set status only based on signed compare (rs - rt)) +# 1100 0111 ssss tttt # ucmp rs, rt (set status only based on unsigned compare (rs - rt)) +# +# 1100 1000 ssss nnnn # add rs, n rs = rs + n +# 1100 1001 ssss nnnn # sub rs, n rs = rs - n +# 1100 1010 ssss nnnn # rsub rs, n rs = n - rs +# 1100 1011 ssss nnnn # mul rs, n rs = rs * n +# 1100 1100 ssss nnnn # div rs, n rs = rs / n +# 1100 1101 ssss iiii # mod rs, i rs = rs % i +# 1100 1110 ssss nnnn # cmp rs, n (set status only based on signed compare (rs - n)) +# 1100 1111 ssss iiii # ucmp rs, i (set status only based on unsigned compare (rs - i)) +# +#### logic +# 1101 0000 ssss tttt # and rs, rt rs = rs & rt +# 1101 0001 ssss tttt # or rs, rt rs = rs | rt +# 1101 0010 ssss tttt # xor rs, rt rs = rs ^ rt +# 1101 0011 ssss tttt # lsr rs, rt rs = rs >> rt +# 1101 0100 ssss tttt # asr rs, rt rs = rs s>> rt +# 1101 0101 ssss tttt # lsl rs, rt rs = rs << rt +# 1101 1000 ssss tttt # saa rs, rt rs = (rs << 11) | rt +# +# 1101 1011 ssss iiii # lsr rs, i rs = rs >> i +# 1101 1100 ssss iiii # asr rs, i rs = rs s>> i +# 1101 1101 ssss iiii # lsl rs, i rs = rs << i +# 1101 1110 ssss 0000 # inv rs rs = ~rs +# 1101 1110 ssss 0001 # neg rs rs = -rs +# +#### memory +# 1101 0110 ssss tttt # load rs, [rt] rs = [rt] +# 1101 0111 ssss tttt # store [rs], rt [rs] = rt +# 1101 1111 ssss tttt # mov rs, rt rs = rt + +#### flow +# 1110 nnnn nnnn 0ccc # brcc n if ccc goto pc + n +# 1110 nnnn nnnn 1ccc # brdscc n if ccc goto pc + n with delay slot +# 1111 0000 ssss 0ccc # brcc rs if ccc goto rs & ~1 +# 1111 0001 ssss 0ccc # brdscc rs if ccc goto rs & ~1 with delay slot +# 1111 0010 ssss 0000 # push rs push rs +# 1111 0011 ssss 0000 # pop rs pop rs +# 1111 0100 0000 0000 # ret return +# 1111 0101 nnnn nnnn # callds n call n with delay slot +# 1111 0110 ssss 0000 # call rs call rs +# 1111 0110 ssss 1ccc # call rs if ccc call rs +# 1111 1nnn nnnn nnnn # call n call n +# +#### user-defined 1010 xxxx +# 1010 0010 ssss 0000 # user_one rs user_one rs +# 1010 0010 ssss 0000 # user_two rs user_two rs +# 1010 0011 0000 0000 # user_three user_three +# 1010 0100 ssss tttt # user_four rs rt user_four rs rt +# 1010 0101 nnnn nnnn # user_five n user_five n +# 1010 0110 ssss 0000 # user_six rs user_six rs +# 1010 1000 0000 0000 # unimpl +# +#### RESERVED / UNUSED +# 1011 xxxx xxxx xxxx # UNUSED +# 1101 1001 xxxx xxxx # RESERVED BANK (consumed by toy_builder.sinc) +# 1101 1010 xxxx xxxx # RESERVED BANK (consumed by toy_builder.sinc) +# 1111 0111 xxxx xxxx # RESERVED BANK (consumed by toy_builder.sinc) + +define token instr(16) + op1515 = (15, 15) + op1415 = (14, 15) + op1215 = (12, 15) + op1111 = (11, 11) + op0811 = (8, 11) + op0407 = (4, 7) + op0007 = (0, 7) + op0003 = (0, 3) + op0303 = (3, 3) + rd = (8, 11) + rs = (4, 7) + rt = (0, 3) + imm1213 = (12, 13) + imm0007 = (0, 7) + imm0003 = (0, 3) + simm1213 = (12, 13) signed + simm0010 = (0, 10) signed + simm0411 = (4, 11) signed + simm0007 = (0, 7) signed + simm0003 = (0, 3) signed + cc0911 = (9, 11) + cc0002 = (0, 2) +; + +attach variables [ rd rs rt ] [ + r0 r1 r2 r3 r4 r5 r6 r7 + r8 r9 r10 r11 r12 sp lr pc +]; + +# addressing mode subs + +Simm4: "#"^simm0003 is simm0003 { export *[const]:$(SIZE) simm0003; } +Simm10: "#"^computed is simm1213 & imm0007 [ computed = (simm1213 << 8) | imm0007; ] { export *[const]:$(SIZE) computed; } + +Imm4: "#"^imm0003 is imm0003 { export *[const]:$(SIZE) imm0003; } +Imm10: "#"^computed is imm1213 & imm0007 [ computed = (imm1213 << 8) | imm0007; ] { export *[const]:$(SIZE) computed; } + +Rel8: addr is simm0007 [ addr = inst_start + simm0007; ] { export *:$(SIZE) addr; } +Rel82: addr is simm0411 [ addr = inst_start + simm0411; ] { export *:$(SIZE) addr; } +Rel11: addr is simm0010 [ addr = inst_start + simm0010; ] { export *:$(SIZE) addr; } + +RS: [rs] is rs { export *[$(DATA_SPACE)]:$(SIZE) rs; } +RT: [rt] is rt { export *[$(DATA_SPACE)]:$(SIZE) rt; } + +CC: "eq" is cc0002=0x0 { export Z; } +CC: "ne" is cc0002=0x1 { tmp = !Z; export tmp; } +CC: "lt" is cc0002=0x2 { tmp = N != V; export tmp; } +CC: "le" is cc0002=0x3 { tmp = Z || (N != V); export tmp; } +CC: "lo" is cc0002=0x4 { export C; } +CC: "mi" is cc0002=0x5 { export N; } +CC: "vs" is cc0002=0x6 { export V; } +CC: "" is cc0002=0x7 { export 1:1; } + +COND: CC is CC { if (!CC) goto inst_next; } +COND: CC is CC & cc0002=0x7 { } # unconditional + +macro resultflags(result) { + N = result s< 0; + Z = result == 0; +} +macro addflags(a, b) { + C = carry(a, b); + V = scarry(a, b); +} +macro subflags(a, b) { + C = a s< b; + V = sborrow(a, b); +} +macro logicflags() { + C = 0; + V = 0; +} + +define pcodeop pcodeop_one; +define pcodeop pcodeop_two; +define pcodeop pcodeop_three; + +# operations + +:imm rd, Imm10 is $(INSTR_PHASE) op1515=0x0 & rd & Imm10 { logicflags(); rd = Imm10; resultflags(rd); } +:simm rd, Simm10 is $(INSTR_PHASE) op1415=0x2 & rd & Simm10 { logicflags(); rd = Simm10; resultflags(rd); } + +:add rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x0 & rs & rt { addflags(rs, rt); rs = rs + rt; resultflags(rs); } +:sub rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x1 & rs & rt { subflags(rs, rt); rs = rs - rt; resultflags(rs); } +:rsub rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x2 & rs & rt { subflags(rt, rs); rs = rt - rs; resultflags(rs); } +:mul rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x3 & rs & rt { rs = rs * rt; resultflags(rs); } # fix C & V +:div rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x4 & rs & rt { rs = rs / rt; resultflags(rs); } # fix C & V +:mod rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x5 & rs & rt { rs = rs % rt; resultflags(rs); } # fix C & V +:cmp rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x6 & rs & rt { subflags(rs, rt); tmp:$(SIZE) = rs - rt; resultflags(tmp); } +:ucmp rs, rt is $(INSTR_PHASE) op1215=0xc & op0811=0x7 & rs & rt { logicflags(); N = rs < rt; Z = rs == rt; } + +:add rs, Simm4 is $(INSTR_PHASE) op1215=0xc & op0811=0x8 & rs & Simm4 { addflags(rs, Simm4); rs = rs + Simm4; resultflags(rs); } +:sub rs, Simm4 is $(INSTR_PHASE) op1215=0xc & op0811=0x9 & rs & Simm4 { subflags(rs, Simm4); rs = rs - Simm4; resultflags(rs); } +:rsub rs, Simm4 is $(INSTR_PHASE) op1215=0xc & op0811=0xa & rs & Simm4 { subflags(Simm4, rs); rs = Simm4 - rs; resultflags(rs); } +:mul rs, Simm4 is $(INSTR_PHASE) op1215=0xc & op0811=0xb & rs & Simm4 { rs = rs * Simm4; resultflags(rs); } # fix C & V +:div rs, Simm4 is $(INSTR_PHASE) op1215=0xc & op0811=0xc & rs & Simm4 { rs = rs / Simm4; resultflags(rs); } # fix C & V +:mod rs, Imm4 is $(INSTR_PHASE) op1215=0xc & op0811=0xd & rs & Imm4 { rs = rs % Imm4; resultflags(rs); } # fix C & V +:cmp rs, Simm4 is $(INSTR_PHASE) op1215=0xc & op0811=0xe & rs & Simm4 { subflags(rs, Simm4); tmp:$(SIZE) = rs - Simm4; resultflags(tmp); } +:ucmp rs, Imm4 is $(INSTR_PHASE) op1215=0xc & op0811=0xf & rs & Imm4 { logicflags(); N = rs < Imm4; Z = rs == Imm4; } + +:and rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x0 & rs & rt { logicflags(); rs = rs & rt; resultflags(rs); } +:or rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x1 & rs & rt { logicflags(); rs = rs | rt; resultflags(rs); } +:xor rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x2 & rs & rt { logicflags(); rs = rs ^ rt; resultflags(rs); } +:lsr rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x3 & rs & rt { logicflags(); rs = rs >> rt; resultflags(rs); } +:asr rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x4 & rs & rt { logicflags(); rs = rs s>> rt; resultflags(rs); } +:lsl rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x5 & rs & rt { logicflags(); rs = rs << rt; resultflags(rs); } + +# saa == shift and accumulate; very useful for building up a 32 bit or 64 bit value in pieces, like: +# imm r12, #32b +# imm r11, #7d7 +# saa r12, r11 +# imm r11, #2be +# saa r12, r11 +# +# now r12 contains '0xcafebabe' (decompiler reconstitutes the pieces seamlessly) + +:saa rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x8 & rs & rt { logicflags(); rs = (rs << 11) | rt; resultflags(rs); } + +:lsr rs, Imm4 is $(INSTR_PHASE) op1215=0xd & op0811=0xb & rs & Imm4 { logicflags(); rs = rs >> Imm4; resultflags(rs); } +:asr rs, Imm4 is $(INSTR_PHASE) op1215=0xd & op0811=0xc & rs & Imm4 { logicflags(); rs = rs s>> Imm4; resultflags(rs); } +:lsl rs, Imm4 is $(INSTR_PHASE) op1215=0xd & op0811=0xd & rs & Imm4 { logicflags(); rs = rs << Imm4; resultflags(rs); } # fix C & V +:inv rs is $(INSTR_PHASE) op1215=0xd & op0811=0xe & rs & op0003=0x0 { logicflags(); rs = ~rs; resultflags(rs); } +:neg rs is $(INSTR_PHASE) op1215=0xd & op0811=0xe & rs & op0003=0x1 { logicflags(); rs = -rs; resultflags(rs); } + +:load rs, RT is $(INSTR_PHASE) op1215=0xd & op0811=0x6 & rs & RT { rs = RT; logicflags(); resultflags(rs); } +:store RS, rt is $(INSTR_PHASE) op1215=0xd & op0811=0x7 & RS & rt { RS = rt; logicflags(); resultflags(rt); } +:mov rs, rt is $(INSTR_PHASE) op1215=0xd & op0811=0xf & rs & rt { rs = rt; logicflags(); resultflags(rs); } + +:sk^CC is $(INSTR_PHASE) op1215=0x8 & op0811=0x0 & op0407=0x0 & op0303=0x0 & CC & Rel82 { if (CC) goto inst_next2; } + +:br^COND Rel82 is $(INSTR_PHASE) op1215=0xe & op0303=0x0 & COND & Rel82 { build COND; goto Rel82; } +:brds^COND Rel82 is $(INSTR_PHASE) op1215=0xe & op0303=0x1 & COND & Rel82 { build COND; delayslot(1); goto Rel82; } +:br^COND rs is $(INSTR_PHASE) op1215=0xf & op0811=0x0 & COND & rs & op0303=0x0 { build COND; goto [rs]; } +:brds^COND rs is $(INSTR_PHASE) op1215=0xf & op0811=0x1 & COND & rs & op0303=0x0 { build COND; delayslot(1); goto [rs]; } +@ifdef POS_STACK +:push rs is $(INSTR_PHASE) op1215=0xf & op0811=0x2 & rs & op0003=0x0 { *[ram]:$(SIZE) sp = rs; sp = sp + $(SIZE); logicflags(); resultflags(rs); } +:pop rs is $(INSTR_PHASE) op1215=0xf & op0811=0x3 & rs & op0003=0x0 { sp = sp - $(SIZE); rs = *[ram]:$(SIZE) sp; logicflags(); resultflags(rs); } +@else +:push rs is $(INSTR_PHASE) op1215=0xf & op0811=0x2 & rs & op0003=0x0 { *[ram]:$(SIZE) sp = rs; sp = sp - $(SIZE); logicflags(); resultflags(rs); } +:pop rs is $(INSTR_PHASE) op1215=0xf & op0811=0x3 & rs & op0003=0x0 { sp = sp + $(SIZE); rs = *[ram]:$(SIZE) sp; logicflags(); resultflags(rs); } +@endif +:ret is $(INSTR_PHASE) op1215=0xf & op0811=0x4 & op0007=0x0 { return [lr]; } +:callds Rel8 is $(INSTR_PHASE) op1215=0xf & op0811=0x5 & Rel8 { delayslot(1); lr = inst_next; call Rel8; } +:call rs is $(INSTR_PHASE) op1215=0xf & op0811=0x6 & rs & op0003=0x0 { lr = inst_next; call [rs]; } +:call Rel11 is $(INSTR_PHASE) op1215=0xf & op1111=0x1 & Rel11 { lr = inst_next; call Rel11; } + +# 1111 0110 ssss 1ccc # call rs if ccc call rs +:call^COND rs is $(INSTR_PHASE) op1215=0xf & op0811=0x6 & rs & op0303=0x1 & COND { build COND; lr = inst_next; call [rs]; } + +:user_one rs is $(INSTR_PHASE) op1215=0xa & op0811=0x01 & rs & op0003=0x0 { pcodeop_one(rs);} +:user_two rs is $(INSTR_PHASE) op1215=0xa & op0811=0x02 & rs & op0003=0x0 { pcodeop_two(rs); pcodeop_three();} +:user_three is $(INSTR_PHASE) op1215=0xa & op0811=0x03 & op0007=0x0 { pcodeop_three();} +:user_four rs rt is $(INSTR_PHASE) op1215=0xa & op0811=0x04 & rs & rt { pcodeop_one(rs); call [rt]; pcodeop_three();} +:user_five Rel8 is $(INSTR_PHASE) op1215=0xa & op0811=0x05 & Rel8 { lr = inst_next; call Rel8; pcodeop_three();} +:user_six rs is $(INSTR_PHASE) op1215=0xa & op0811=0x06 & rs & op0003=0x0 { r1 = pcodeop_one(rs); call [r1];} + +:unimpl is $(INSTR_PHASE) op1215=0xa & op0811=0x08 & op0007=0 unimpl diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/toyPosStack.cspec b/python/icicle/Ghidra/Processors/Toy/data/languages/toyPosStack.cspec new file mode 100644 index 0000000..795ba37 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/toyPosStack.cspec @@ -0,0 +1,69 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/toy_be.slaspec b/python/icicle/Ghidra/Processors/Toy/data/languages/toy_be.slaspec new file mode 100644 index 0000000..7b22724 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/toy_be.slaspec @@ -0,0 +1,8 @@ +@define ENDIAN "big" +@define SIZE "4" + +@define INSTR_PHASE "" # not used by basic toy language +@define DATA_SPACE "ram" + +@include "toy.sinc" +@include "toyInstructions.sinc" diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/toy_be_posStack.slaspec b/python/icicle/Ghidra/Processors/Toy/data/languages/toy_be_posStack.slaspec new file mode 100644 index 0000000..4d79c31 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/toy_be_posStack.slaspec @@ -0,0 +1,9 @@ +@define ENDIAN "big" +@define SIZE "4" + +@define INSTR_PHASE "" # not used by basic toy language +@define POS_STACK "true" # enables switch in instructions for push/pop to work in positive direction +@define DATA_SPACE "ram" + +@include "toy.sinc" +@include "toyInstructions.sinc" diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/toy_builder.sinc b/python/icicle/Ghidra/Processors/Toy/data/languages/toy_builder.sinc new file mode 100644 index 0000000..b754d49 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/toy_builder.sinc @@ -0,0 +1,86 @@ + + +@include "toy.sinc" + +# Define context bits +define register offset=0x2000 size=8 contextreg; + +define context contextreg + # stored context + fctx = (0,3) # flowing context + nfctx = (4,7) noflow # single address context + # transient context (never stored, aids disassembly) + phase = (8,9) # parse phase - used for complex scenarios + counter = (10,13) # parse count-down +; + +define token instr8(8) + op8 = (0, 7) +; + +define token extra16(16) + xsimm8 = (0, 7) signed +; + +define token extra8(8) + nnnn = (0, 3) +; + +# ^instruction - manage parse phases (only required for complex languages) + +:^instruction is phase=0 & instruction [ phase=1; ] { build instruction; } + +@define INSTR_PHASE "phase=1 &" # parse instructions during phase 1 + +@include "toyInstructions.sinc" + +# additional forms added to toy language, taken from all three reserved banks: +# 1101 1001 xxxx xxxx # RESERVED BANK +# 1101 1010 xxxx xxxx # RESERVED BANK +# 1111 0111 xxxx xxxx # RESERVED BANK + +# fctx i 1101 1001 0000 iiii # set flow context (fctx) on next instr +# nfctx i 1101 1001 0001 iiii # set noflow context (nfctx) on next instr +# nfctx rel,i 1101 1001 0010 iiii; 0000 0000 iiii iiii # set noflow context on rel instr + +# cop# s 1101 1010 ssss 0000 # coprocessor # determined by nfctx val (1-3) + +# nop #1 1111 0111 +# nop # 1101 1001 0011 nnnn; ... # nop where nnnn indicates number of additional bytes consumed + + +# operations + +:fctx Imm4 is phase=1 & op1215=0xd & op0811=0x9 & rs=0x0 & imm0003 & Imm4 [ fctx=imm0003; globalset(inst_next,fctx); ] { } + +nfctxSetAddr: addr is Imm4 & imm0003; xsimm8 [ addr = inst_start + xsimm8; nfctx=imm0003; globalset(addr, nfctx); ] { export *:$(SIZE) addr; } + +:nfctx nfctxSetAddr,Imm4 is (phase=1 & op1215=0xd & op0811=0x9 & rs=0x2 & Imm4) ... & nfctxSetAddr { } +:nfctx Imm4 is phase=1 & op1215=0xd & op0811=0x9 & rs=0x1 & imm0003 & Imm4 [ nfctx=imm0003; globalset(inst_next,nfctx); ] { } + +define pcodeop cop1; +define pcodeop cop2; +define pcodeop cop3; + +:cop1 rs is phase=1 & op1215=0xd & op0811=0xa & op0003=0 & nfctx=1 & rs { cop1(rs); } +:cop2 rs is phase=1 & op1215=0xd & op0811=0xa & op0003=0 & nfctx=2 & rs { cop2(rs); } +:cop3 rs is phase=1 & op1215=0xd & op0811=0xa & op0003=0 & nfctx=3 & rs { cop3(rs); } + +NopCnt: "#"^cnt is imm0003 [ cnt = imm0003 + 2; ] { export *[const]:1 cnt; } + +NopByte: is counter=0 { } +NopByte: is epsilon; nnnn; NopByte [ counter=counter-1; ] { } + +One: "#"^cnt is epsilon [ cnt = 1; ] { export *[const]:1 cnt; } + +:nop One is phase=1 & op8=0xf7 & One { } +:nop NopCnt is phase=1 & op1215=0xd & op0811=0x9 & rs=0x3 & imm0003 & NopCnt; NopByte ... [ counter=imm0003; ] { } + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/toy_builder_be.slaspec b/python/icicle/Ghidra/Processors/Toy/data/languages/toy_builder_be.slaspec new file mode 100644 index 0000000..a9e7ff5 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/toy_builder_be.slaspec @@ -0,0 +1,5 @@ +@define ENDIAN "big" +@define SIZE "4" +@define DATA_SPACE "ram" + +@include "toy_builder.sinc" diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/toy_builder_be_align2.slaspec b/python/icicle/Ghidra/Processors/Toy/data/languages/toy_builder_be_align2.slaspec new file mode 100644 index 0000000..87480f6 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/toy_builder_be_align2.slaspec @@ -0,0 +1,6 @@ +@define ENDIAN "big" +@define ALIGN "2" +@define SIZE "4" +@define DATA_SPACE "ram" + +@include "toy_builder.sinc" diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/toy_builder_le.slaspec b/python/icicle/Ghidra/Processors/Toy/data/languages/toy_builder_le.slaspec new file mode 100644 index 0000000..3ffd405 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/toy_builder_le.slaspec @@ -0,0 +1,5 @@ +@define ENDIAN "little" +@define SIZE "4" +@define DATA_SPACE "ram" + +@include "toy_builder.sinc" diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/toy_builder_le_align2.slaspec b/python/icicle/Ghidra/Processors/Toy/data/languages/toy_builder_le_align2.slaspec new file mode 100644 index 0000000..34e30f3 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/toy_builder_le_align2.slaspec @@ -0,0 +1,6 @@ +@define ENDIAN "little" +@define ALIGN "2" +@define SIZE "4" +@define DATA_SPACE "ram" + +@include "toy_builder.sinc" diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/toy_harvard.pspec b/python/icicle/Ghidra/Processors/Toy/data/languages/toy_harvard.pspec new file mode 100644 index 0000000..6c6703b --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/toy_harvard.pspec @@ -0,0 +1,6 @@ + + + + + + diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/toy_le.slaspec b/python/icicle/Ghidra/Processors/Toy/data/languages/toy_le.slaspec new file mode 100644 index 0000000..b3ed543 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/toy_le.slaspec @@ -0,0 +1,8 @@ +@define ENDIAN "little" +@define SIZE "4" + +@define INSTR_PHASE "" # not used by basic toy language +@define DATA_SPACE "ram" + +@include "toy.sinc" +@include "toyInstructions.sinc" diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/toy_wsz_be.slaspec b/python/icicle/Ghidra/Processors/Toy/data/languages/toy_wsz_be.slaspec new file mode 100644 index 0000000..8d56125 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/toy_wsz_be.slaspec @@ -0,0 +1,10 @@ +@define ENDIAN "big" +@define ALIGN "2" +@define SIZE "4" +@define WORDSIZE "2" + +@define INSTR_PHASE "" # not used by basic toy language +@define DATA_SPACE "ram" + +@include "toy.sinc" +@include "toyInstructions.sinc" diff --git a/python/icicle/Ghidra/Processors/Toy/data/languages/toy_wsz_le.slaspec b/python/icicle/Ghidra/Processors/Toy/data/languages/toy_wsz_le.slaspec new file mode 100644 index 0000000..a81752d --- /dev/null +++ b/python/icicle/Ghidra/Processors/Toy/data/languages/toy_wsz_le.slaspec @@ -0,0 +1,10 @@ +@define ENDIAN "little" +@define ALIGN "2" +@define SIZE "4" +@define WORDSIZE "2" + +@define INSTR_PHASE "" # not used by basic toy language +@define DATA_SPACE "ram" + +@include "toy.sinc" +@include "toyInstructions.sinc" diff --git a/python/icicle/Ghidra/Processors/V850/data/languages/Helpers/Conditions.sinc b/python/icicle/Ghidra/Processors/V850/data/languages/Helpers/Conditions.sinc new file mode 100644 index 0000000..e52ed22 --- /dev/null +++ b/python/icicle/Ghidra/Processors/V850/data/languages/Helpers/Conditions.sinc @@ -0,0 +1,38 @@ +##################################################### +##### Conditions ##### +##################################################### + + +c0003: "v" is op0003=0x0 { tmp:1 = ($(OV)) == 1; export tmp; } +c0003: "nv" is op0003=0x8 { tmp:1 = ($(OV)) == 0; export tmp; } +c0003: "c" is op0003=0x1 { tmp:1 = ($(CY)) == 1; export tmp; } +c0003: "nc" is op0003=0x9 { tmp:1 = ($(CY)) == 0; export tmp; } +c0003: "e" is op0003=0x2 { tmp:1 = ($(Z)) == 1; export tmp; } +c0003: "ne" is op0003=0xA { tmp:1 = ($(Z)) == 0; export tmp; } +c0003: "nh" is op0003=0x3 { tmp:1 = ($(CY) || $(Z)) == 1; export tmp; } +c0003: "h" is op0003=0xB { tmp:1 = ($(CY) || $(Z)) == 0; export tmp; } +c0003: "n" is op0003=0x4 { tmp:1 = ($(S)) == 1; export tmp; } +c0003: "p" is op0003=0xC { tmp:1 = ($(S)) == 0; export tmp; } +c0003: "t" is op0003=0x5 { tmp:1 = 1; export tmp; } +c0003: "sa" is op0003=0xD { tmp:1 = ($(SAT)) == 1; export tmp; } +c0003: "lt" is op0003=0x6 { tmp:1 = ($(S) ^^ $(OV)) == 1; export tmp; } +c0003: "ge" is op0003=0xE { tmp:1 = ($(S) ^^ $(OV)) == 0; export tmp; } +c0003: "le" is op0003=0x7 { tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 1; export tmp; } +c0003: "gt" is op0003=0xF { tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 0; export tmp; } + +c1720: "v" is op1720=0x0 { tmp:1 = ($(OV)) == 1; export tmp; } +c1720: "nv" is op1720=0x8 { tmp:1 = ($(OV)) == 0; export tmp; } +c1720: "c" is op1720=0x1 { tmp:1 = ($(CY)) == 1; export tmp; } +c1720: "nc" is op1720=0x9 { tmp:1 = ($(CY)) == 0; export tmp; } +c1720: "e" is op1720=0x2 { tmp:1 = ($(Z)) == 1; export tmp; } +c1720: "ne" is op1720=0xA { tmp:1 = ($(Z)) == 0; export tmp; } +c1720: "nh" is op1720=0x3 { tmp:1 = ($(CY) || $(Z)) == 1; export tmp; } +c1720: "h" is op1720=0xB { tmp:1 = ($(CY) || $(Z)) == 0; export tmp; } +c1720: "n" is op1720=0x4 { tmp:1 = ($(S)) == 1; export tmp; } +c1720: "p" is op1720=0xC { tmp:1 = ($(S)) == 0; export tmp; } +c1720: "t" is op1720=0x5 { tmp:1 = 1; export tmp; } +c1720: "sa" is op1720=0xD { tmp:1 = ($(SAT)) == 1; export tmp; } +c1720: "lt" is op1720=0x6 { tmp:1 = ($(S) ^^ $(OV)) == 1; export tmp; } +c1720: "ge" is op1720=0xE { tmp:1 = ($(S) ^^ $(OV)) == 0; export tmp; } +c1720: "le" is op1720=0x7 { tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 1; export tmp; } +c1720: "gt" is op1720=0xF { tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 0; export tmp; } diff --git a/python/icicle/Ghidra/Processors/V850/data/languages/Helpers/Extras.sinc b/python/icicle/Ghidra/Processors/V850/data/languages/Helpers/Extras.sinc new file mode 100644 index 0000000..6abc080 --- /dev/null +++ b/python/icicle/Ghidra/Processors/V850/data/languages/Helpers/Extras.sinc @@ -0,0 +1,131 @@ +##################################################### +##### Extras ##### +##################################################### + + +# read r0 always return zero +R0004: _R0004 is _R0004 & _R0004=0 { local x:4=0; export x; } +R0004: _R0004 is _R0004 { export _R0004; } + +R1115: _R1115 is _R1115 & _R1115=0 { local x:4=0; export x; } +R1115: _R1115 is _R1115 { export _R1115; } + +R2731: _R2731 is _R2731 & _R2731=0 { local x:4=0; export x; } +R2731: _R2731 is _R2731 { export _R2731; } + + +adr9: res is op0406 & s1115 +[ res = ((s1115 << 4) | (op0406 << 1)) + inst_start; ] +{ + export *:4 res; +} + +adr22: res is s0005; op1631 & op1616=0 +[ res = ((s0005 << 16) | op1631) + inst_start; ] +{ + export *:4 res; +} + +adr32: res is op1631 & op1616=0; op3247 +[ res = ((op3247 << 16) | op1631) + inst_start; ] +{ + export *:4 res; +} + +adr32i: res is op1631 & op1616=0; op3247 +[ res = ((op3247 << 16) | op1631); ] +{ + export *[const]:4 res; +} + +reg4: op0_1720 is op2323=0 & op0_1720 { export op0_1720; } +reg4: op1_1720 is op2323=1 & op1_1720 { export op1_1720; } + + + +##### Prep/Disp Loop ##### + +PrepList20: r20 is prep27=1 & r20 { push(r20); } +PrepList20: is prep27=0 { } + +PrepList21: r21 is prep26=1 & prep27=0 & r21 { push(r21); } +PrepList21: PrepList20,r21 is prep26=1 & PrepList20 & r21 { push(r21); } +PrepList21: PrepList20 is prep26=0 & PrepList20 { } + +PrepList22: r22 is prep25=1 & prep2627=0 & r22 { push(r22); } +PrepList22: PrepList21,r22 is prep25=1 & PrepList21 & r22 { push(r22); } +PrepList22: PrepList21 is prep25=0 & PrepList21 { } + +PrepList23: r23 is prep24=1 & prep2527=0 & r23 { push(r23); } +PrepList23: PrepList22,r23 is prep24=1 & PrepList22 & r23 { push(r23); } +PrepList23: PrepList22 is prep24=0 & PrepList22 { } + +PrepList24: r24 is prep31=1 & prep2427=0 & r24 { push(r24); } +PrepList24: PrepList23,r24 is prep31=1 & PrepList23 & r24 { push(r24); } +PrepList24: PrepList23 is prep31=0 & PrepList23 { } + +PrepList25: r25 is prep30=1 & prep2427=0 & prep31=0 & r25 { push(r25); } +PrepList25: PrepList24,r25 is prep30=1 & PrepList24 & r25 { push(r25); } +PrepList25: PrepList24 is prep30=0 & PrepList24 { } + +PrepList26: r26 is prep29=1 & prep2427=0 & prep3031=0 & r26 { push(r26); } +PrepList26: PrepList25,r26 is prep29=1 & PrepList25 & r26 { push(r26); } +PrepList26: PrepList25 is prep29=0 & PrepList25 { } + +PrepList27: r27 is prep28=1 & prep2427=0 & prep2931=0 & r27 { push(r27); } +PrepList27: PrepList26,r27 is prep28=1 & PrepList26 & r27 { push(r27); } +PrepList27: PrepList26 is prep28=0 & PrepList26 { } + +PrepList28: r28 is prep23=1 & prep2431=0 & r28 { push(r28); } +PrepList28: PrepList27,r28 is prep23=1 & PrepList27 & r28 { push(r28); } +PrepList28: PrepList27 is prep23=0 & PrepList27 { } + +PrepList29: r29 is prep22=1 & prep2431=0 & prep23=0 & r29 { push(r29); } +PrepList29: PrepList28,r29 is prep22=1 & PrepList28 & r29 { push(r29); } +PrepList29: PrepList28 is prep22=0 & PrepList28 { } + +PrepList30: ep is prep00=1 & prep2431=0 & prep2223=0 & ep { push(ep); } +PrepList30: PrepList29,ep is prep00=1 & PrepList29 & ep { push(ep); } +PrepList30: PrepList29 is prep00=0 & PrepList29 { } + +PrepList: { lp } is prep21=1 & prep2431=0 & prep2223=0 & prep00=0 & lp { push(lp); } +PrepList: { PrepList30,lp } is prep21=1 & PrepList30 & lp { push(lp); } +PrepList: { PrepList30 } is prep21=0 & PrepList30 { } + + + +DispList31: lp is prep21=1 & lp { pop(lp); } +DispList31: is prep21=0 { } + +DispList30: ep,DispList31 is DispList31 & prep00=1 & ep { pop(ep); } +DispList30: DispList31 is DispList31 & prep00=0 { } + +DispList29: r29,DispList30 is DispList30 & prep22=1 & r29 { pop(r29); } +DispList29: DispList30 is DispList30 & prep22=0 { } + +DispList28: r28,DispList29 is DispList29 & prep23=1 & r28 { pop(r28); } +DispList28: DispList29 is DispList29 & prep23=0 { } + +DispList27: r27,DispList28 is DispList28 & prep28=1 & r27 { pop(r27); } +DispList27: DispList28 is DispList28 & prep28=0 { } + +DispList26: r26,DispList27 is DispList27 & prep29=1 & r26 { pop(r26); } +DispList26: DispList27 is DispList27 & prep29=0 { } + +DispList25: r25,DispList26 is DispList26 & prep30=1 & r25 { pop(r25); } +DispList25: DispList26 is DispList26 & prep30=0 { } + +DispList24: r24,DispList25 is DispList25 & prep31=1 & r24 { pop(r24); } +DispList24: DispList25 is DispList25 & prep31=0 { } + +DispList23: r23,DispList24 is DispList24 & prep24=1 & r23 { pop(r23); } +DispList23: DispList24 is DispList24 & prep24=0 { } + +DispList22: r22,DispList23 is DispList23 & prep25=1 & r22 { pop(r22); } +DispList22: DispList23 is DispList23 & prep25=0 { } + +DispList21: r21,DispList22 is DispList22 & prep26=1 & r21 { pop(r21); } +DispList21: DispList22 is DispList22 & prep26=0 { } + +DispList: { r20,DispList21 } is DispList21 & prep27=1 & r20 { pop(r20); } +DispList: { DispList21 } is DispList21 & prep27=0 { } diff --git a/python/icicle/Ghidra/Processors/V850/data/languages/Helpers/Macros.sinc b/python/icicle/Ghidra/Processors/V850/data/languages/Helpers/Macros.sinc new file mode 100644 index 0000000..5985412 --- /dev/null +++ b/python/icicle/Ghidra/Processors/V850/data/languages/Helpers/Macros.sinc @@ -0,0 +1,254 @@ +##################################################### +##### Macros ##### +##################################################### + + +##### CARRY-Flag ##### + +macro set_CY_pos(var1, var2) +{ + $(CY) = carry(var1, var2); +} + +macro set_CY_pos2(var1, var2, var3) +{ + local var12 = var1 + var2; + $(CY) = carry(var1, var2) || carry(var12, var3); +} + +macro set_CY_neg(var1, var2) +{ + $(CY) = var1 < var2; +} + +macro set_CY_neg2(var1, var2, var3) +{ + local var23 = var2 + var3; + $(CY) = (var1 < var23); +} + + + +##### Overflow-Flag ##### + +macro set_OV_pos(var1, var2) +{ + $(OV) = scarry(var1, var2); +} + +macro set_OV_pos2(var1, var2, var3) +{ + local var12 = var1 + var2; + $(OV) = scarry(var1, var2) || scarry(var12, var3); +} + +macro set_OV_neg(var1, var2) +{ + local A:4 = var1; + local B:4 = var2; + local R = A - B; + + local A1 = A[31,1]; + local B1 = B[31,1]; + local R1 = R[31,1]; + + $(OV) = (A1 != B1) && (B1 == R1); + + #OV = 1 if: + #pos - neg = neg + #neg - pos = pos +} + +macro set_OV_neg2(var1, var2, var3) +{ + local A:4 = var1; + local B:4 = var2; + local C:4 = var3; + local R = A - B - C; + + local A1 = A[31,1]; + local B1 = B[31,1]; + local R1 = R[31,1]; + + $(OV) = (A1 != B1) && (B1 == R1); +} + + + +##### S/Z-Flags ##### + +macro set_S(flag) +{ + $(S) = flag s< 0; +} + +macro set_Z(var) +{ + $(Z) = var == 0; +} + + + +##### General-Flag-Macros ##### + +macro set_general_flags_pos(var1, var2) +{ + local res = var1 + var2; + set_CY_pos(var1, var2); + set_OV_pos(var1, var2); + set_S(res); + set_Z(res); +} + +macro set_general_flags_neg(var1, var2) +{ + local res = var1 - var2; + set_CY_neg(var1, var2); + set_OV_neg(var1, var2); + set_S(res); + set_Z(res); +} + +macro set_OV0_S_Z(var) +{ + $(OV) = 0; + set_S(var); + set_Z(var); +} + + + +##### General-Macros ##### + +# if condition is != 0 +macro either_or(res, cond, true, false) +{ + res = (true * zext(cond != 0)) + (false * zext(cond == 0)); +} + +# if condition is == 1 +macro either_or1(res, cond, true, false) +{ + res = (true * zext(cond == 1)) + (false * zext(cond != 1)); +} + +macro shift_right_logic(res, var, shift_) +{ + local shift = shift_ & 0x1f; + local mask = (zext(shift != 0) * var) & (1 << (shift - 1)); + res = var >> shift; + set_OV0_S_Z(res); + $(CY) = ((mask != 0) && (shift != 0)); +} + +macro shift_right_arith(res, var, shift_) +{ + local shift = shift_ & 0x1f; + local mask = (zext(shift != 0) * var) & (1 << (shift - 1)); + res = var s>> shift; + set_OV0_S_Z(res); + $(CY) = ((mask != 0) && (shift != 0)); +} + +macro shift_left_logic(res, var, shift_) +{ + local shift = shift_ & 0x1f; + local mask = (zext(shift != 0) * var) & (1 << (32 - shift)); + res = var << shift; + set_OV0_S_Z(res); + $(CY) = ((mask != 0) && (shift != 0)); +} + + + +##### Prep/Disp Macros ##### + +macro push(reg) +{ + sp = sp - 4; + *:4 sp = reg; +} + +macro pop(reg) +{ + reg = *:4 sp; + sp = sp + 4; +} + + + +##### Search Macros ##### + +macro SearchRight(res, var, char) +{ + local var_:4 = var; + res = 0; + + + if ((var_ & 0x1) == char) + goto ; + + var_ = var_ >> 1; + res = res + 1; + + if (res < 32) + goto ; + + res = 0; + + +} + +macro SearchLeft(res, var, char) +{ + local var_:4 = var; + res = 0; + + + if ((var_ >> 31) == char) + goto ; + + var_ = var_ << 1; + res = res + 1; + + if (res < 32) + goto ; + + res = 0; + + +} + +# macro saturate(var) +# { +# if (var s> 0x7FFFFFFF) +# goto ; + +# if (var s< -0x80000000) +# goto ; + +# goto ; + +# +# var = 0x7FFFFFFF; +# goto ; + +# +# var = -0x80000000; +# goto ; + +# +# } + + +##### Float-Macros ##### + +macro compare_float(res, fcond, reg1, reg2) +{ + local un = ((fcond & 1) == 1) & (nan(reg2) || nan(reg1)); + local eq = ((fcond & 2) == 2) & (!(nan(reg2) || nan(reg1))) & (reg2 f== reg1); + local le = ((fcond & 4) == 4) & (!(nan(reg2) || nan(reg1))) & (reg2 f< reg1); + #local ex = (fcond & 8) & ((nan(reg2) || nan(reg1))); + + res = zext(un|eq|le); +} diff --git a/python/icicle/Ghidra/Processors/V850/data/languages/Helpers/Register.sinc b/python/icicle/Ghidra/Processors/V850/data/languages/Helpers/Register.sinc new file mode 100644 index 0000000..9cc9824 --- /dev/null +++ b/python/icicle/Ghidra/Processors/V850/data/languages/Helpers/Register.sinc @@ -0,0 +1,36 @@ +##################################################### +##### Register ##### +##################################################### + + +##### General-purpose registers (r0 to r31) ##### + +define register offset=0x0 size=0x4 # offset = 0 because it's the start +[ + r0 r1 r2 sp gp tp r6 r7 r8 r9 + r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 + r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 + ep lp +]; + + + +##### Control/Special registers ##### + +define register offset=0x80 size=0x4 # offset = 0x80(128) = PreOffset+PreRegister*Size = 0+32*4 = 128 +[ + EIPC EIPSW FEPC FEPSW ECR PSW FPSR FPEPC FPST FPCC + FPCFG SCCFG SCBP EIIC FEIC DBIC CTPC CTPSW DBPC DBPSW + CTBP DIR DBG22 DBG23 DBG24 DBG25 DBG26 DBG27 EIWR FEWR + DBWR BSEL +]; + +define register offset=0x0 size=0x8 +[ + r0r1 r2sp r4r5 r6r7 r8r9 + r10r11 r12r13 r14r15 r16r17 r18r19 + r20r21 r22r23 r24r25 r26r27 r28r29 + eplp +]; + +define register offset=0x100 size=0x4 [ PC ]; # offset = 0x100(256) = PreOffset+PreRegister*Size = 128+32*4 = 256 diff --git a/python/icicle/Ghidra/Processors/V850/data/languages/Helpers/Tokens.sinc b/python/icicle/Ghidra/Processors/V850/data/languages/Helpers/Tokens.sinc new file mode 100644 index 0000000..8402ab0 --- /dev/null +++ b/python/icicle/Ghidra/Processors/V850/data/languages/Helpers/Tokens.sinc @@ -0,0 +1,105 @@ +##################################################### +##### Tokens ##### +##################################################### + + +define token instr(16) + op0000 = (0,0) + op0003 = (0,3) + op0004 = (0,4) + _R0004 = (0,4) + SR0004 = (0,4) + R0004x2 = (0,4) + s0004 = (0,4) signed + s0005 = (0,5) signed + op0005 = (0,5) + op0006 = (0,6) + op0010 = (0,10) + op0015 = (0,15) + op0106 = (1,6) + op0406 = (4,6) + op0410 = (4,10) + op0505 = (5,5) + op0510 = (5,10) + op0515 = (5,15) + op0610 = (6,10) + op0615 = (6,15) + op0710 = (7,10) + op1113 = (11,13) + op1114 = (11,14) + op1115 = (11,15) + _R1115 = (11,15) + SR1115 = (11,15) + R1115x2 = (11,15) + s1115 = (11,15) signed + op1415 = (14,15) + op1515 = (15,15) +; + +define token instr2(16) + op1616 = (0,0) + op1617 = (0,1) + op1619 = (0,3) + op1620 = (0,4) + R1620 = (0,4) + R1620x2 = (0,4) + op1626 = (0,10) + op1631 = (0,15) + s1631 = (0,15) signed + fcbit1719 = (1,3) + op1720 = (1,4) + op0_1720 = (1,4) + op1_1720 = (1,4) + s1731 = (1,15) signed + op1821 = (2,5) + s1821 = (2,5) signed + op2020 = (4,4) + op2026 = (4,10) + op2122 = (5,6) + op2126 = (5,10) + op2226 = (6,10) + op2323 = (7,7) + op2426 = (8,10) + op2729 = (11,13) + fcond2730 = (11,14) + op2731 = (11,15) + _R2731 = (11,15) + R2731x2 = (11,15) + op3031 = (14,15) + op3131 = (15,15) +; + +define token instr3(16) + op3247 = (0,15) + s3247 = (0,15) signed +; + +define token instr4(16) + op4863 = (0,15) +; + +# used in PREPARE/DISPOSE instructions +define token prep(32) + prep00 = (0,0) + prep0105 = (1,5) + prep0615 = (6,15) + prep1620 = (16,20) + prep21 = (21,21) + prep22 = (22,22) + prep2223 = (22,31) + prep23 = (23,23) + prep24 = (24,24) + prep2431 = (24,31) + prep25 = (25,25) + prep26 = (26,26) + prep27 = (27,27) + prep28 = (28,28) + prep29 = (29,29) + prep2931 = (29,31) + prep3031 = (30,31) + prep2427 = (24,27) + prep2527 = (25,27) + prep2627 = (26,27) + prep30 = (30,30) + prep31 = (31,31) +; diff --git a/python/icicle/Ghidra/Processors/V850/data/languages/Helpers/Variables.sinc b/python/icicle/Ghidra/Processors/V850/data/languages/Helpers/Variables.sinc new file mode 100644 index 0000000..e427b03 --- /dev/null +++ b/python/icicle/Ghidra/Processors/V850/data/languages/Helpers/Variables.sinc @@ -0,0 +1,49 @@ +##################################################### +##### Variables ##### +##################################################### + + +attach variables [ _R0004 _R1115 _R2731 R1620 prep1620] +[ + r0 r1 r2 sp gp tp r6 r7 r8 r9 + r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 + r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 + ep lp +]; + +attach variables [ R0004x2 R1115x2 R1620x2 R2731x2 ] +[ + r0r1 _ r2sp _ r4r5 _ r6r7 _ r8r9 _ + r10r11 _ r12r13 _ r14r15 _ r16r17 _ r18r19 _ + r20r21 _ r22r23 _ r24r25 _ r26r27 _ r28r29 _ + eplp _ +]; + +attach variables [ SR0004 SR1115 ] +[ + EIPC EIPSW FEPC FEPSW ECR PSW FPSR FPEPC FPST FPCC + FPCFG SCCFG SCBP EIIC FEIC DBIC CTPC CTPSW DBPC DBPSW + CTBP DIR DBG22 DBG23 DBG24 DBG25 DBG26 DBG27 EIWR FEWR + DBWR BSEL +]; + + +attach variables [op0_1720] [r0 r2 gp r6 r8 r10 r12 r14 r16 r18 r20 r22 r24 r26 r28 ep]; +attach variables [op1_1720] [r1 sp tp r7 r9 r11 r13 r15 r17 r19 r21 r23 r25 r27 r29 lp]; + + +attach names [fcond2730] +["f" "un" "eq" "ueq" "olt" "ult" "ole" "ule" "sd" "ngle" "seq" "ngl" "lt" "nge" "le" "ngt"]; + + +@define NP "PSW[7,1]" +@define EP "PSW[6,1]" +@define ID "PSW[5,1]" +@define SAT "PSW[4,1]" +@define CY "PSW[3,1]" +@define OV "PSW[2,1]" +@define S "PSW[1,1]" +@define Z "PSW[0,1]" + +@define EICC "ECR[0,16]" +@define FECC "ECR[16,16]" diff --git a/python/icicle/Ghidra/Processors/V850/data/languages/Instructions/Arithmetic.sinc b/python/icicle/Ghidra/Processors/V850/data/languages/Instructions/Arithmetic.sinc new file mode 100644 index 0000000..a546e24 --- /dev/null +++ b/python/icicle/Ghidra/Processors/V850/data/languages/Instructions/Arithmetic.sinc @@ -0,0 +1,336 @@ +# (3) Multiply instructions +# (4) Multiply-accumulate instructions +# (5) Arithmetic instructions +# (7) Saturated operation instructions +# (11) Divide instructions +# (12) High-speed divide instructions + + + +##################################################### +##### Multiply ##### +##################################################### + + +# MUL reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01000100000 +:mul R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x220 & R2731 +{ + local res:8 = sext(R1115) * sext(R0004); + R1115 = res:4; + R2731 = res[32,32]; +} + +# MUL imm9, reg2, reg3 - rrrrr111111iiiii|wwwww01001IIII00 +:mul imm9, R1115, R2731 is op0510=0x3F & op0004 & R1115; op2226=0x9 & op1617=0x0 & s1821 & R2731 +[ imm9 = (s1821 << 5) | op0004; ] +{ + local res:8 = sext(R1115) * imm9; + R1115 = res:4; + R2731 = res[32,32]; +} + +# MULH reg1, reg2 - rrrrr000111RRRRR +:mulh R0004, R1115 is op0510=0x07 & R0004 & R1115 & op1115!=0 +{ + R1115 = sext(R1115:2) * sext(R0004:2); +} + +# MULH imm5, reg2 - rrrrr010111iiiii +:mulh s0004, R1115 is op0510=0x17 & s0004 & R1115 +{ + R1115 = sext(R1115:2) * s0004; +} + +# MULHI imm16, reg1, reg2 - rrrrr110111RRRRR|iiiiiiiiiiiiiiii +:mulhi s1631, R0004, R1115 is op0510=0x37 & R1115 & R0004; s1631 +{ + R1115 = R0004 * s1631; +} + +# MULU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01000100010 +:mulu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x222 & R2731 +{ + local res:8 = zext(R1115) * zext(R0004); + R1115 = res:4; + R2731 = res[32,32]; +} + +# MULU imm9, reg2, reg3 - rrrrr111111iiiii|wwwww01001IIII10 +:mulu imm9, R1115, R2731 is op0510=0x3F & op0004 & R1115; op2226=0x9 & op1617=0x2 & op1821 & R2731 +[ imm9 = (op1821 << 5) | op0004; ] +{ + local res:8 = zext(R1115) * imm9; + R1115 = res:4; + R2731 = res[32,32]; +} + + + +##################################################### +##### MultiplyAccumulate ##### +##################################################### + + +# MAC reg1, reg2, reg3, reg4 - rrrrr111111RRRRR wwww0011110mmmm0 +:mac R0004, R1115, R2731x2, R1620x2 is op0510=0x3F & R0004 & R1115; op2126=0x1E & op1616=0 & R1620x2 & R2731x2 +{ + R1620x2 = sext(R1115) * sext(R0004) + R2731x2; +} + +# MACU reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwww0011111mmmm0 +:macu R0004, R1115, R2731x2, R1620x2 is op0510=0x3F & R0004 & R1115; op2126=0x1F & op1616=0 & R1620x2 & R2731x2 +{ + R1620x2 = zext(R1115) * zext(R0004) + R2731x2; +} + + + +##################################################### +##### Arithmetic ##### +##################################################### + + +# ADD reg1, reg2 - rrrrr001110RRRRR +:add R0004, R1115 is op0510=0x0E & R0004 & R1115 +{ + set_general_flags_pos(R0004, R1115); + R1115 = R1115 + R0004; +} + +# ADD imm5, reg2 - rrrrr010010iiiii +:add s0004, R1115 is op0510=0x12 & s0004 & R1115 +{ + set_general_flags_pos(s0004, R1115); + R1115 = R1115 + s0004; +} + +# ADDI imm16, reg1, reg2 - rrrrr110000RRRRR|iiiiiiiiiiiiiiii +:addi s1631, R0004, R1115 is op0510=0x30 & R1115 & R0004; s1631 +{ + set_general_flags_pos(R0004, s1631); + R1115 = R0004 + s1631; +} + +# CMP reg1, reg2 - rrrrr001111RRRRR +:cmp R0004, R1115 is op0510=0x0F & R0004 & R1115 +{ + set_general_flags_neg(R1115, R0004); +} + +# CMP imm5, reg2 - rrrrr010011iiiii +:cmp s0004, R1115 is op0510=0x13 & s0004 & R1115 +{ + set_general_flags_neg(R1115, s0004); +} + +# MOV reg1, reg2 - rrrrr000000RRRRR +:mov R0004, R1115 is op0510=0x00 & R0004 & R1115 +{ + R1115 = R0004; +} + +# MOV imm5, reg2 - rrrrr010000iiiii +:mov s0004, R1115 is op0510=0x10 & s0004 & R1115 & op1115!=0 +{ + R1115 = s0004; +} + +# MOV imm32, reg1 - 00000110001RRRRR|iiiiiiiiiiiiiiii|IIIIIIIIIIIIIIII +:mov imm32, R0004 is op0515=0x031 & R0004; op1631; op3247 +[ imm32 = (op3247 << 16) | op1631; ] +{ + R0004 = imm32; +} + +# MOVEA imm16, reg1, reg2 - rrrrr110001RRRRR|iiiiiiiiiiiiiiii +:movea s1631, R0004, R1115 is op0510=0x31 & op1115!=0 & R0004 & R1115; s1631 +{ + R1115 = R0004 + s1631; +} + +# MOVHI imm16, reg1, reg2 - rrrrr110010RRRRR|iiiiiiiiiiiiiiii +:movhi s1631, R0004, R1115 is op0510=0x32 & op1115!=0 & R0004 & R1115; s1631 +{ + R1115 = R0004 + (s1631 << 16); +} + +# SUB reg1, reg2 - rrrrr001101RRRRR +:sub R0004, R1115 is op0510=0x0D & R0004 & R1115 +{ + set_general_flags_neg(R1115, R0004); + R1115 = R1115 - R0004; +} + +# SUBR reg1, reg2 - rrrrr001100RRRRR +:subr R0004, R1115 is op0510=0x0C & R0004 & R1115 +{ + set_general_flags_neg(R0004, R1115); + R1115 = R0004 - R1115; +} + + + +##################################################### +##### Saturated ##### +##################################################### + + +define pcodeop __saturate; + +# SATADD reg1, reg2 - rrrrr000110RRRRR +:satadd R0004, R1115 is op0510=0x06 & R0004 & R1115 & op1115!=0 +{ + set_general_flags_pos(R1115, R0004); + $(SAT) = $(SAT) || $(OV); + R1115 = R1115 + R0004; + __saturate(R1115); +} + +#SATADD imm5, reg2 - rrrrr010001iiiii +:satadd s0004, R1115 is op0510=0x11 & s0004 & R1115 & op1115!=0 +{ + set_general_flags_pos(R1115, s0004); + $(SAT) = $(SAT) || $(OV); + R1115 = R1115 + s0004; + __saturate(R1115); +} + +# SATADD reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01110111010 +:satadd R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x3BA & R2731 +{ + set_general_flags_pos(R1115, R0004); + $(SAT) = $(SAT) || $(OV); + R2731 = R1115 + R0004; + __saturate(R2731); +} + +# SATSUB reg1, reg2 - rrrrr000101RRRRR +:satsub R0004, R1115 is op0510=0x05 & R0004 & R1115 & op1115!=0 +{ + set_general_flags_neg(R1115, R0004); + $(SAT) = $(SAT) || $(OV); + R1115 = R1115 - R0004; + __saturate(R1115); +} + +# SATSUB reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01110011010 +:satsub R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x39A & R2731 +{ + set_general_flags_neg(R1115, R0004); + $(SAT) = $(SAT) || $(OV); + R2731 = R1115 - R0004; + __saturate(R2731); +} + +# SATSUBI imm16, reg1, reg2 +:satsubi s1631, R0004, R1115 is op0510=0x33 & op1115!=0 & R0004 & R1115; s1631 +{ + set_general_flags_neg(R0004, s1631); + $(SAT) = $(SAT) || $(OV); + R1115 = R0004 - s1631; + __saturate(R1115); +} + +# SATSUBR reg1, reg2 +:satsubr R0004, R1115 is op0510=0x04 & R0004 & R1115 & op1115!=0 +{ + set_general_flags_neg(R0004, R1115); + $(SAT) = $(SAT) || $(OV); + R1115 = R0004 - R1115; + __saturate(R1115); +} + + + +##################################################### +##### Divide ##### +##################################################### + + +# DIV reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011000000 +:div R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2C0 & R2731 +{ + local quot:4 = R1115 s/ R0004; + local mod:4 = R1115 s% R0004; + $(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0); + set_Z(R1115); + set_S(R1115); + R1115 = quot; + R2731 = mod; +} + +# DIVH reg1, reg2 - rrrrr000010RRRRR +:divh R0004, R1115 is op0510=0x02 & R0004 & R1115 +{ + $(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0); + R1115 = R1115 / R0004; + set_Z(R1115); + set_S(R1115); +} + +# DIVH reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01010000000 +:divh R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x280 & R2731 +{ + local quot:4 = R1115 s/ sext(R0004:2); + local mod:4 = R1115 s% sext(R0004:2); + $(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0); + set_Z(R1115); + set_S(R1115); + R1115 = quot; + R2731 = mod; +} + +# DIVHU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01010000010 +:divhu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x282 & R2731 +{ + local quot:4 = R1115 / sext(R0004:2); + local mod:4 = R1115 % sext(R0004:2); + $(OV) = (R0004 == 0); + set_Z(R1115); + set_S(R1115); + R1115 = quot; + R2731 = mod; +} + +# DIVU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011000010 +:divu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2C2 & R2731 +{ + local quot:4 = R1115 / R0004; + local mod:4 = R1115 % R0004; + $(OV) = (R0004 == 0); + set_Z(R1115); + set_S(R1115); + R1115 = quot; + R2731 = mod; +} + + + +##################################################### +##### HighSpeedDivide ##### +##################################################### + + +# DIVQ reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011111100 +:divq R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2FC & R2731 +{ + local quot:4 = R1115 s/ R0004; + local mod:4 = R1115 s% R0004; + $(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0); + set_Z(R1115); + set_S(R1115); + R2731 = mod; + R1115 = quot; +} + +# DIVQU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011111110 +:divqu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2FE & R2731 +{ + local quot:4 = R1115 / R0004; + local mod:4 = R1115 % R0004; + $(OV) = (R0004 == 0); + set_Z(R1115); + set_S(R1115); + R2731 = mod; + R1115 = quot; +} diff --git a/python/icicle/Ghidra/Processors/V850/data/languages/Instructions/Float.sinc b/python/icicle/Ghidra/Processors/V850/data/languages/Instructions/Float.sinc new file mode 100644 index 0000000..d708864 --- /dev/null +++ b/python/icicle/Ghidra/Processors/V850/data/languages/Instructions/Float.sinc @@ -0,0 +1,498 @@ +##################################################### +##### Float ##### +##################################################### + + +# ABSF.D reg2, reg3 - rrrr011111100000|wwww010001011000 +:absf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00000; R2731x2 & op2126=0b100010 & op1620=0b11000 +{ + R2731x2 = abs(R1115x2); +} + +# ABSF.S reg2, reg3 - rrrrr11111100000|wwwww10001001000 +:absf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00000; R2731 & op2126=0b100010 & op1620=0b01000 +{ + R2731 = abs(R1115); +} + +# ADDF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001110000 +:addf.d R0004x2, R1115x2, R2731x2 is R1115x2 & op0510=0x3F & R0004x2 ; R2731x2 & op2126=0b100011 & op1620=0b10000 +{ + R2731x2 = R1115x2 f+ R0004x2; +} + +# ADDF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10001100000 +:addf.s R0004, R1115, R2731 is R1115 & op0510=0x3F & R0004 ; R2731 & op2126=0b100011 & op1620=0b00000 +{ + R2731 = R1115 f+ R0004; +} + +# CEILF.DL reg2, reg3 - rrrr011111100010|wwww010001010100 +:ceilf.dl R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00010; R2731x2 & op2126=0b100010 & op1620=0b10100 +{ + local var:8 = ceil(float2float(R1115x2)); + R2731x2 = trunc(var); +} + +# CEILF.DUL reg2, reg3 - rrrr011111110010|wwww010001010100 +:ceilf.dul R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10010; R2731x2 & op2126=0b100010 & op1620=0b10100 +{ + local var:8 = ceil(float2float(R1115x2)); + R2731x2 = trunc(var); +} + +# CEILF.DUW reg2, reg3 - rrrrr11111110010|wwwww10001010000 +:ceilf.duw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10010; R2731 & op2126=0b100010 & op1620=0b10000 +{ + R2731 = trunc(ceil(R1115x2)); +} + +# CEILF.DW reg2, reg3 - rrrrr11111100010|wwwww10001010000 +:ceilf.dw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00010; R2731 & op2126=0b100010 & op1620=0b10000 +{ + R2731 = trunc(ceil(R1115x2)); +} + +# CEILF.SL reg2, reg3 - rrrrr11111100010|wwww010001000100 +:ceilf.sl R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00010; R2731x2 & op2126=0b100010 & op1620=0b00100 +{ + local var:8 = ceil(float2float(R1115)); + R2731x2 = trunc(var); +} + +# CEILF.SUL reg2, reg3 - rrrrr11111110010|wwwww10001000100 +:ceilf.sul R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10010; R2731x2 & op2126=0b100010 & op1620=0b00100 +{ + local var:8 = ceil(float2float(R1115)); + R2731x2 = trunc(var); +} + +# CEILF.SUW reg2, reg3 - rrrrr11111110010|wwwww10001000000 +:ceilf.sul R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10010; R2731 & op2126=0b100010 & op1620=0b00000 +{ + R2731 = trunc(ceil(R1115)); +} + +# CEILF.SW reg2, reg3 - rrrrr11111100010|wwwww10001000000 +:ceilf.sw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00010; R2731 & op2126=0b100010 & op1620=0b00000 +{ + R2731 = trunc(ceil(R1115)); +} + +# CMOVF.D fcbit, reg1, reg2, reg3 - rrrr0111111RRRR0|wwww01000001fff0 +:cmovf.d fcbit1719, R1115x2, R0004x2, R2731x2 is R1115x2 & op0510=0x3F & R0004x2; R2731x2 & op2126=0b100000 & op2020=1 & fcbit1719 & op1616=0 +{ + #CC0 = Bit 24 + local bit = (FPSR >> (fcbit1719 + 24:1)) & 0x1; + either_or1(R2731x2, bit, R0004x2, R1115x2); +} + +# CMOVF.S fcbit, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww1000000fff0 +:cmovf.s fcbit1719, R1115, R0004, R2731 is R1115 & op0510=0x3F & R0004; R2731 & op2126=0b100000 & op2020=0 & fcbit1719 & op1616=0 +{ + local bit = (FPSR >> (fcbit1719 + 24:1)) & 0x1; + either_or1(R2731, bit, R0004, R1115); +} + +# CMPF.D fcond, reg2, reg1, fcbit - rrrr0111111RRRRR|0FFFF1000011fff0 +:cmpf.d fcond2730, R1115x2, R0004x2, fcbit1719 is R1115x2 & op0510=0x3F & R0004x2; op3131=0 & fcond2730 & op2126=0b100001 & op2020=1 & fcbit1719 & op1616=0 +{ + #0 = Unordered + #1 = Equal to + #2 = Less than + #3 = Exeption + #bits = ex le eq un + + local bit:4 = 0; + compare_float(bit, fcond2730:1, R0004x2, R1115x2); + + local pos:4 = bit << (fcbit1719 + 24); #find position of the calculated bit + local mask:4 = 1 << (fcbit1719 + 24); #create mask to clean old bit in FPSR register + FPSR = (FPSR & ~mask) | pos; #set the new bit at the right position +} + +# CMPF.S fcond, reg2, reg1, fcbit - rrrrr111111RRRRR|0FFFF1000010fff0 +:cmpf.s fcond2730, R1115, R0004, fcbit1719 is R1115 & op0510=0x3F & R0004; op3131=0 & fcond2730 & op2126=0b100001 & op2020=0 & fcbit1719 & op1616=0 +{ + local bit:4 = 0; + compare_float(bit, fcond2730:1, R0004, R1115); + + local pos:4 = bit << (fcbit1719 + 24); #find position of the calculated bit + local mask:4 = 1 << (fcbit1719 + 24); #create mask to clean old bit in FPSR register + FPSR = (FPSR & ~mask) | pos; #set the new bit at the right position +} + +# CVTF.DL reg2, reg3 - rrrr011111100100|wwww010001010100 +:cvtf.dl R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00100; R2731x2 & op2126=0b100010 & op1620=0b10100 +{ + R2731x2 = int2float(R1115x2); +} + +# CVTF.DS reg2, reg3 - rrrr011111100011|wwww010001010010 +:cvtf.ds R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00011; R2731 & op2126=0b100010 & op1620=0b10010 +{ + R2731 = float2float(R1115x2); +} + +# CVTF.DUL reg2, reg3 - rrrr011111110100|wwww010001010100 +:cvtf.dul R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10100; R2731x2 & op2126=0b100010 & op1620=0b10100 +{ + R2731x2 = trunc(R1115x2); +} + +# CVTF.DUW reg2, reg3 - rrrrr11111110100|wwwww10001010000 +:cvtf.duw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10100; R2731 & op2126=0b100010 & op1620=0b10000 +{ + R2731 = trunc(R1115x2); +} + +# CVTF.DW reg2, reg3 - rrrrr11111100100|wwwww10001010000 +:cvtf.sw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00100; R2731 & op2126=0b100010 & op1620=0b10000 +{ + R2731 = trunc(R1115x2); +} + +# CVTF.LD reg2, reg3 - rrrr011111100001|wwww010001010010 +:cvtf.ls R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b10010 +{ + R2731x2 = int2float(R1115x2); +} + +# CVTF.LS reg2, reg3 - rrrr011111100001|wwwww10001000010 +:cvtf.ls R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b00010 +{ + R2731 = int2float(R1115x2); +} + +# CVTF.SD reg2, reg3 - rrrrr11111100010|wwww010001010010 +:cvtf.sd R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00010; R2731x2 & op2126=0b100010 & op1620=0b10010 +{ + R2731x2 = float2float(R1115); +} + +# CVTF.SL reg2, reg3 - rrrrr11111100100|wwwww10001000100 +:cvtf.sl R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00100; R2731x2 & op2126=0b100010 & op1620=0b00100 +{ + R2731x2 = trunc(R1115); +} + +# CVTF.SUL reg2, reg3 - rrrrr11111110100|wwwww10001000100 +:cvtf.sul R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10100; R2731x2 & op2126=0b100010 & op1620=0b00100 +{ + R2731x2 = trunc(R1115); +} + +# CVTF.SUW reg2, reg3 - rrrrr11111110100|wwwww10001000000 +:cvtf.suw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10100; R2731 & op2126=0b100010 & op1620=0b00000 +{ + R2731 = trunc(R1115); +} + +# CVTF.SW reg2, reg3 - rrrrr11111100100|wwwww10001000000 +:cvtf.sw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00100; R2731 & op2126=0b100010 & op1620=0b00000 +{ + R2731 = trunc(R1115); +} + +# CVTF.ULD reg2, reg3 - rrrr011111100001|wwww010001010010 +:cvtf.uls R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10001; R2731x2 & op2126=0b100010 & op1620=0b10010 +{ + R2731x2 = int2float(R1115x2); +} + +# CVTF.ULS reg2, reg3 - rrrr011111110001|wwwww10001000010 +:cvtf.uls R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10001; R2731 & op2126=0b100010 & op1620=0b00010 +{ + R2731 = int2float(R1115x2); +} + +# CVTF.UWD reg2, reg3 - rrrrr11111110000|wwwww10001010010 +:cvtf.uwd R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10000; R2731x2 & op2126=0b100010 & op1620=0b10010 +{ + R2731x2 = int2float(R1115); +} + +# CVTF.UWS reg2, reg3 - rrrrr11111110000|wwwww10001000010 +:cvtf.uws R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10000; R2731 & op2126=0b100010 & op1620=0b00010 +{ + R2731 = int2float(R1115); +} + +# CVTF.WD reg2, reg3 - rrrrr11111100000|wwwww10001010010 +:cvtf.wd R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00000; R2731x2 & op2126=0b100010 & op1620=0b10010 +{ + R2731x2 = int2float(R1115); +} + +# CVTF.WS reg2, reg3 - rrrrr11111100000|wwwww10001000010 +:cvtf.ws R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00000; R2731 & op2126=0b100010 & op1620=0b00010 +{ + R2731 = int2float(R1115); +} + +# DIVF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001111110 +:divf.s R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b11110 +{ + R2731x2 = R1115x2 f/ R0004x2; +} + +# DIVF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10001101110 +:divf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b01110 +{ + R2731 = R1115 f/ R0004; +} + +# FLOORF.DL reg2, reg3 - rrrr011111100011|wwww010001010100 +:floorf.dl R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00011; R2731x2 & op2126=0b100010 & op1620=0b10100 +{ + local var:8 = floor(float2float(R1115x2)); + R2731x2 = trunc(var); +} + +# FLOORF.DUL reg2, reg3 - rrrr011111110011|wwww010001010100 +:floorf.dul R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10011; R2731x2 & op2126=0b100010 & op1620=0b10100 +{ + local var:8 = floor(float2float(R1115x2)); + R2731x2 = trunc(var); +} + +# FLOORF.DUW reg2, reg3 - rrrrr11111110011|wwwww10001010000 +:floorf.duw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10011; R2731 & op2126=0b100010 & op1620=0b10000 +{ + R2731 = trunc(floor(R1115x2)); +} + +# FLOORF.DW reg2, reg3 - rrrrr11111100011|wwwww10001010000 +:floorf.dw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00011; R2731 & op2126=0b100010 & op1620=0b10000 +{ + R2731 = trunc(floor(R1115x2)); +} + +# FLOORF.SL reg2, reg3 - rrrrr11111100011|wwww010001000100 +:floorf.sl R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00011; R2731x2 & op2126=0b100010 & op1620=0b00100 +{ + local var:8 = floor(float2float(R1115)); + R2731x2 = trunc(var); +} + +# FLOORF.SUL reg2, reg3 - rrrrr11111110011|wwwww10001000100 +:floorf.sul R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10011; R2731x2 & op2126=0b100010 & op1620=0b00100 +{ + local var:8 = floor(float2float(R1115)); + R2731x2 = trunc(var); +} + +# FLOORF.SUW reg2, reg3 - rrrrr11111110011|wwwww10001000000 +:floorf.suw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10011; R2731 & op2126=0b100010 & op1620=0b00000 +{ + R2731 = trunc(floor(R1115)); +} + +# FLOORF.SW reg2, reg3 - rrrrr11111100011|wwwww10001000000 +:floorf.suw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00011; R2731 & op2126=0b100010 & op1620=0b00000 +{ + R2731 = trunc(floor(R1115)); +} + +# FMAF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10011100000 +:fmaf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100111 & op1620=0b00000 +{ + R2731 = (R1115 f* R0004) f+ R2731; +} + +# FMSF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10011100010 +:fmsf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100111 & op1620=0b00010 +{ + R2731 = (R1115 f* R0004) f- R2731; +} + +# FNMAF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10011100100 +:fnmaf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100111 & op1620=0b00100 +{ + R2731 = -1 f* ((R1115 f* R0004) f+ R2731); +} + +# FNMSF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10011100110 +:fnmfs.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100111 & op1620=0b00110 +{ + R2731 = -1 f* ((R1115 f* R0004) f- R2731); +} + +# MADDF.S reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwwww101W00WWWW0 +:maddf.s R0004, R1115, R2731, reg4 is R0004 & op0510=0x3F & R1115; R2731 & op2426=0b101 & op2122=0b00 & op1616=0 & reg4 +{ + reg4 = (R1115 f* R0004) f+ R2731; +} + +# MAXF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001111000 +:maxf.d R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b11000 +{ + local bigger:1 = R1115x2 f> R0004x2; + either_or(R2731x2, bigger, R1115x2, R0004x2); +} + +# MAXF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10001101000 +:maxf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b01000 +{ + local bigger:1 = R1115 f> R0004; + either_or(R2731, bigger, R1115, R0004); +} + +# MINF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001111010 +:minf.d R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b11010 +{ + local bigger:1 = R1115x2 f< R0004x2; + either_or(R2731x2, bigger, R1115x2, R0004x2); +} + +# MINF.S reg1, reg2, reg3 - rrrr0111111RRRRR|wwwww10001101010 +:minf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b01010 +{ + local bigger:1 = R1115 f< R0004; + either_or(R2731, bigger, R1115, R0004); +} + +# MSUBF.S reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwwww101W01WWWW0 +:msubf.s R0004, R1115, R2731, reg4 is R0004 & op0510=0x3F & R1115; R2731 & op2426=0b101 & op2122=0b01 & op1616=0 & reg4 +{ + reg4 = (R1115 f* R0004) f- R2731; +} + +# MULF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001110100 +:mulf.d R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b10100 +{ + R2731x2 = R1115x2 f* R0004x2; +} + +# MULF.S reg1, reg2, reg3 - rrrr0111111RRRRR|wwwww10001100100 +:mulf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b00100 +{ + R2731 = R1115 f* R0004; +} + +# NEGF.D reg2, reg3 - rrrr011111100001|wwww010001011000 +:negf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b11000 +{ + R2731x2 = f- R1115x2; +} + +# NEGF.S reg2, reg3 - rrrrr11111100001|wwwww10001001000 +:negf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b01000 +{ + R2731 = f- R1115; +} + +# NMADDF.S reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwwww101W10WWWW0 +:nmaddf.s R0004, R1115, R2731, reg4 is R0004 & op0510=0x3F & R1115; R2731 & op2426=0b101 & op2122=0b10 & op1616=0 & reg4 +{ + reg4 = f-((R1115 f* R0004) f+ R2731); +} + +# NMSUBF.S reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwwww101W11WWWW0 +:nmsubf.s R0004, R1115, R2731, reg4 is R0004 & op0510=0x3F & R1115; R2731 & op2426=0b101 & op2122=0b11 & op1616=0 & reg4 +{ + reg4 = f-((R1115 f* R0004) f- R2731); +} + +# RECIPF.D reg2, reg3 - rrrr011111100001|wwww010001011110 +:recipf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b11110 +{ + R2731x2 = 1 f/ R1115x2; +} + +# RECIPF.S reg2, reg3 - rrrrr11111100001|wwwww10001001110 +:recipf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b01110 +{ + R2731 = 1 f/ R1115; +} + +# RSQRTF.D reg2, reg3 - rrrr011111100010|wwwww10001011110 +:rsqrtf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00010; R2731x2 & op2126=0b100010 & op1620=0b11110 +{ + R2731x2 = 1 f/ sqrt(R1115x2); +} + +# RSQRTF.S reg2, reg3 - rrrrr11111100010|wwwww10001001110 +:rsqrtf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00010; R2731 & op2126=0b100010 & op1620=0b01110 +{ + R2731 = 1 f/ sqrt(R1115); +} + +# SQRTF.D reg2, reg3 - rrrr011111100000|wwww010001011110 +:sqrtf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00000; R2731x2 & op2126=0b100010 & op1620=0b11110 +{ + R2731x2 = sqrt(R1115x2); +} + +# SQRTF.S reg2, reg3 - rrrrr11111100000|wwwww10001001110 +:sqrtf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00000; R2731 & op2126=0b100010 & op1620=0b01110 +{ + R2731 = sqrt(R1115); +} + +# SUBF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001110010 +:subf.d R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b10010 +{ + R2731x2 = R1115x2 f- R0004x2; +} + +# SUBF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10001100010 +:subf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b00010 +{ + R2731 = R1115 f- R0004; +} + +# TRFSR fcbit - 0000011111100000|000001000000fff0 +:trfsr fcbit1719 is op1115=0 & op0510=0x3F & op0004=0; op2731=0 & op2126=0b100000 & op2020=0 & fcbit1719 & op1616=0 +{ + local var:4 = FPSR & (1 << (fcbit1719 + 24)); + $(Z) = (var != 0); +} + +# TRNCF.DL reg2, reg3 - rrrr011111100001|wwww010001010100 +:trncf.dl R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b10100 +{ + R2731x2 = trunc(R1115x2); +} + +# TRNCF.DUL reg2, reg3 - rrrr011111110001|wwww010001010100 +:trncf.dul R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10001; R2731x2 & op2126=0b100010 & op1620=0b10100 +{ + R2731x2 = trunc(R1115x2); +} + +# TRNCF.DUW reg2, reg3 - rrrrr11111110001|wwwww10001010000 +:trncf.duw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10001; R2731 & op2126=0b100010 & op1620=0b10000 +{ + R2731 = trunc(R1115x2); +} + +# TRNCF.DW reg2, reg3 - rrrrr11111100001|wwwww10001010000 +:trncf.dw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b10000 +{ + R2731 = trunc(R1115x2); +} + +# TRNCF.SL reg2, reg3 - rrrrr11111100001|wwww010001000100 +:trncf.sl R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b00100 +{ + R2731x2 = trunc(R1115); +} + +# TRNCF.SUL reg2, reg3 - rrrrr11111110001|wwww010001000100 +:trncf.sul R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10001; R2731x2 & op2126=0b100010 & op1620=0b00100 +{ + R2731x2 = trunc(R1115); +} + +# TRNCF.SUW reg2, reg3 - rrrrr11111110001|wwwww10001000000 +:trncf.suw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10001; R2731 & op2126=0b100010 & op1620=0b00000 +{ + R2731 = trunc(R1115); +} + +# TRNCF.SW reg2, reg3 - rrrrr11111100001|wwwww10001000000 +:trncf.sw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b00000 +{ + R2731 = trunc(R1115); +} diff --git a/python/icicle/Ghidra/Processors/V850/data/languages/Instructions/Load_Store.sinc b/python/icicle/Ghidra/Processors/V850/data/languages/Instructions/Load_Store.sinc new file mode 100644 index 0000000..4ec2889 --- /dev/null +++ b/python/icicle/Ghidra/Processors/V850/data/languages/Instructions/Load_Store.sinc @@ -0,0 +1,368 @@ +# (1) Load instructions +# (2) Store instructions +# (9) Data manipulation instructions + + + +##################################################### +##### Load ##### +##################################################### + + +# LD.B disp16[reg1], reg2 - rrrrr111000RRRRR|dddddddddddddddd +:ld.b s1631[R0004], R1115 is op0510=0x38 & R0004 & R1115; s1631 +{ + local adr:4 = R0004 + s1631; + R1115 = sext(*:1 adr); +} + +# LD.B disp23[reg1], reg3 - rrrrr111100RRRRR|wwwwwddddddd0101|DDDDDDDDDDDDDDDD +:ld.b disp23[R0004], R2731 is op0515=0x3C & R0004; R2731 & op2026 & op1619=0x5; s3247 +[ disp23 = (s3247 << 7) | op2026; ] +{ + local adr:4 = R0004 + disp23; + R2731 = sext(*:1 adr); +} + +# LD.BU disp16[reg1], reg2 - rrrrr11110bRRRRR|ddddddddddddddd1 +:ld.bu disp16[R0004], R1115 is op0610=0x1E & R0004 & R1115 & op0505; op1616=0x1 & s1731 +[ disp16 = (s1731 << 1) | op0505; ] +{ + local adr:4 = R0004 + disp16; + R1115 = zext(*:1 adr); +} + +# LD.BU disp23[reg1], reg3 - 00000111101RRRRR|wwwwwddddddd0101|DDDDDDDDDDDDDDDD +:ld.bu disp23[R0004], R2731 is op0515=0x3D & R0004; R2731 & op2026 & op1619=0x5; s3247 +[ disp23 = (s3247 << 7) | op2026; ] +{ + local adr:4 = R0004 + disp23; + R2731 = zext(*:1 adr); +} + +# LD.H disp16[reg1], reg2 - rrrrr111001RRRRR|ddddddddddddddd0 +:ld.h s1631[R0004], R1115 is op0510=0x39 & R0004 & R1115; s1631 & op1616=0x0 +{ + local adr:4 = R0004 + s1631; + R1115 = sext(*:2 adr); +} + +# LD.H disp23[reg1], reg3 - 00000111100RRRRR|wwwwwdddddd00111|DDDDDDDDDDDDDDDD +:ld.h disp23[R0004], R2731 is op0515=0x3C & R0004; R2731 & op2126 & op1620=0x7; s3247 +[ disp23 = (s3247 << 7) | (op2126 << 1); ] +{ + local adr:4 = R0004 + disp23; + R2731 = sext(*:2 adr); +} + +# LD.HU disp16[reg1], reg2 - rrrrr111111RRRRR|ddddddddddddddd1 +:ld.hu disp16[R0004], R1115 is op0510=0x3F & R0004 & R1115; op1616=0x1 & s1731 +[ disp16 = s1731 << 1; ] +{ + local adr:4 = R0004 + disp16; + R1115 = zext(*:2 adr); +} + +# LD.HU disp23[reg1], reg3 - 00000111101RRRRR|wwwwwdddddd00111|DDDDDDDDDDDDDDDD +:ld.hu disp23[R0004], R2731 is op0515=0x3D & R0004; R2731 & op2026 & op1619=0x7; s3247 +[ disp23 = (s3247 << 7) | op2026; ] +{ + local adr:4 = R0004 + disp23; + R2731 = zext(*:2 adr); +} + +# LD.W disp16[reg1], reg2 - rrrrr111001RRRRR|ddddddddddddddd1 +:ld.w disp16[R0004], R1115 is op0510=0x39 & R0004 & R1115; s1731 & op1616=0x1 +[ disp16 = s1731 * 2; ] +{ + local adr:4 = R0004 + disp16; + R1115 = *:4 adr; +} + +# LD.W disp23[reg1], reg3 - 00000111100RRRRR|wwwwwdddddd01001|DDDDDDDDDDDDDDDD +:ld.w disp23[R0004], R2731 is op0515=0x03C & R0004; R2731 & op2126 & op1620=0x9; s3247 +[ disp23 = (s3247 << 7) | (op2126 << 1); ] +{ + local adr:4 = R0004 + disp23; + R2731 = *:4 adr; +} + +# SLD.B disp7[ep], reg2 - rrrrr0110ddddddd +:sld.b op0006[ep], R1115 is op0710=0x06 & op0006 & R1115 & ep +{ + local adr:4 = ep + op0006; + R1115 = sext(*:1 adr); +} + +# SLD.BU disp4[ep], reg2 - rrrrr0000110dddd +:sld.bu op0003[ep], R1115 is op0410=0x06 & R1115 & op0003 & ep +{ + local adr:4 = ep + op0003; + R1115 = zext(*:1 adr); +} + +# SLD.H disp8[ep], reg2 - rrrrr1000ddddddd +:sld.h disp8[ep], R1115 is op0710=0x08 & op0006 & R1115 & ep +[ disp8 = op0006 * 2; ] +{ + local adr:4 = ep + disp8; + R1115 = sext(*:2 adr); +} + +# SLD.HU disp5[ep], reg2 - rrrrr0000111dddd +:sld.hu disp5[ep], R1115 is op0410=0x07 & R1115 & op0003 & ep +[ disp5 = op0003 * 2; ] +{ + local adr:4 = ep + disp5; + R1115 = zext(*:2 adr); +} + +# SLD.W disp8[ep], reg2 - rrrrr1010dddddd0 +:sld.w disp8[ep], R1115 is op0710=0x0A & op0000=0x0 & op0106 & R1115 & ep +[ disp8 = op0106 * 4; ] +{ + local adr:4 = ep + disp8; + R1115 = *:4 adr; +} + + + +##################################################### +##### Store ##### +##################################################### + + +# SST.B reg2, disp7[ep] - rrrrr0111ddddddd +:sst.b R1115, op0006[ep] is op0710=0x07 & op0006 & R1115 & ep +{ + local adr:4 = ep + op0006; + local tmp:4 = R1115; + *:1 adr = tmp:1; +} + +# SST.H reg2, disp8[ep] - rrrrr1001ddddddd +:sst.h R1115, disp8[ep] is op0710=0x09 & op0006 & R1115 & ep +[ disp8 = op0006 * 2; ] +{ + local adr:4 = ep + disp8; + local tmp:4 = R1115; + *:2 adr = tmp:2; +} + +# SST.W reg2, disp8[ep] - rrrrr1010dddddd1 +:sst.w R1115, disp8[ep] is op0710=0x0A & op0000=0x1 & op0106 & R1115 & ep +[ disp8 = op0106 * 4; ] +{ + local adr:4 = ep + disp8; + local tmp:4 = R1115; + *:4 adr = tmp; +} + +# ST.B reg2, disp16[reg1] - rrrrr111010RRRRR|dddddddddddddddd +:st.b R1115, s1631[R0004] is op0510=0x3A & R0004 & R1115; s1631 +{ + local adr:4 = R0004 + s1631; + local tmp:4 = R1115; + *:1 adr = tmp:1; +} + +# ST.B reg3, disp23[reg1] - 00000111100RRRRR|dddddddddddddddd +:st.b R2731, disp23[R0004] is op0515=0x3C & R0004; R2731 & op2026 & op1619=0xD; s3247 +[ disp23 = (s3247 << 7) | op2026; ] +{ + local adr:4 = R0004 + disp23; + local tmp:4 = R2731; + *:1 adr = tmp:1; +} + +# ST.H reg2, disp16[reg1] - rrrrr111011RRRRR|ddddddddddddddd0 +:st.h R1115, s1631[R0004] is op0510=0x3B & R0004 & R1115; s1631 & op1616=0x0 +{ + local adr:4 = R0004 + s1631; + local tmp:4 = R1115; + *:2 adr = tmp:2; +} + +# ST.H reg3, disp23[reg1] - 00000111101RRRRR|wwwwwdddddd01101|DDDDDDDDDDDDDDDD +:st.h R2731, disp23[R0004] is op0515=0x3D & R0004; R2731 & op2126 & op1620=0xD; s3247 +[ disp23 = (s3247 << 7) | (op2126 << 1); ] +{ + local adr:4 = R0004 + disp23; + local tmp:4 = R2731; + *:2 adr = tmp:2; +} + +# ST.W reg2, disp16[reg1] - rrrrr111011RRRRR|ddddddddddddddd1 +:st.w R1115, disp16[R0004] is op0510=0x3B & R0004 & R1115; s1731 & op1616=0x1 +[ disp16 = s1731 * 2; ] +{ + local adr:4 = R0004 + disp16; + local tmp:4 = R1115; + *:4 adr = tmp; +} + +# ST.W reg3, disp23[reg1] - 00000111100RRRRR|wwwwwdddddd01111|DDDDDDDDDDDDDDDD +:st.w R2731, disp23[R0004] is op0515=0x3C & R0004; R2731 & op2126 & op1620=0xF; s3247 +[ disp23 = (s3247 << 7) | (op2126 << 1); ] +{ + local adr:4 = R0004 + disp23; + local tmp:4 = R2731; + *:2 adr = tmp:2; +} + + + +##################################################### +##### DataManipulation ##### +##################################################### + + +# BSH reg2, reg3 - rrrrr11111100000|wwwww01101000010 +:bsh R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x342 & R2731 +{ + local x1 = R1115[0,8]; + local x2 = R1115[8,8]; + local x3 = R1115[16,8]; + local x4 = R1115[24,8]; + R2731 = zext(x3 << 24) | zext(x4 << 16) | zext(x1 << 8) | zext(x2); + set_S(R2731); + $(OV) = 0; + $(Z) = (x1 == 0) && (x2 == 0); + $(CY) = (x1 == 0) || (x2 == 0); +} + +# BSW reg2, reg3 - rrrrr11111100000|wwwww01101000000 +:bsw R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x340 & R2731 +{ + local x1 = R1115[0,8]; + local x2 = R1115[8,8]; + local x3 = R1115[16,8]; + local x4 = R1115[24,8]; + R2731 = zext(x1 << 24) | zext(x2 << 16) | zext(x3 << 8) | zext(x4); + set_OV0_S_Z(R2731); + $(CY) = (x1 == 0) || (x2 == 0) || (x3 == 0) || (x4 == 0); +} + +# CMOV cccc, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww011001cccc0 +:cmov^c1720 R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op2126=0x19 & op1616=0 & c1720 & R2731 +{ + local result:4 = zext(c1720); + R2731 = R0004 * zext(result != 0) + R1115 * zext(result == 0); +} + +# CMOV cccc, imm5, reg2, reg3 - rrrrr111111iiiii|wwwww011000cccc0 +:cmov^c1720 s0004, R1115, R2731 is op0510=0x3F & s0004 & R1115; op2126=0x18 & op1616=0 & c1720 & R2731 +{ + local result:4 = zext(c1720); + R2731 = s0004 * zext(result != 0) + R1115 * zext(result == 0); +} + +# HSH reg2, reg3 - rrrrr11111100000|wwwww01101000110 +:hsh R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x346 & R2731 +{ + R2731 = R1115; + set_S(R2731); + $(OV) = 0; + $(Z) = (R2731:2 == 0); + $(CY) = $(Z); +} + +# HSW reg2, reg3 - rrrrr11111100000|wwwww01101000100 +:hsw R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x344 & R2731 +{ + local x1 = R1115:2; + local x2 = R1115[16,16]; + R2731 = zext(x1 << 16) | zext(x2); + set_OV0_S_Z(R2731); + $(CY) = (x1 == 0) || (x2 == 0); +} + +# SAR reg1, reg2 - rrrrr111111RRRRR|0000000010100000 +:sar R0004, R1115 is op0510=0x3F & R0004 & R1115; op1631=0xA0 +{ + shift_right_arith(R1115, R1115, R0004); +} + +# SAR imm5, reg2 - rrrrr010101iiiii +:sar op0004, R1115 is op0510=0x15 & op0004 & R1115 +{ + shift_right_arith(R1115, R1115, op0004:5); +} + +# SAR reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww00010100010 +:sar R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0xA2 & R2731 +{ + shift_right_arith(R2731, R1115, R0004); +} + +# SASF cccc, reg2 - rrrrr1111110cccc|0000001000000000 +:sasf^c0003 R1115 is op0410=0x7E & c0003 & R1115; op1631=0x0200 +{ + R1115 = (R1115 << 1) | zext(c0003); +} + +# SETF cond, reg2 - rrrrr1111110cccc|0000000000000000 +:setf^c0003 R1115 is op0410=0x7E & c0003 & R1115; op1631=0x0 +{ + R1115 = zext(c0003); +} + +# SHL reg1, reg2 - rrrrr111111RRRRR|0000000011000000 +:shl R0004, R1115 is op0510=0x3F & R0004 & R1115; op1631=0xC0 +{ + shift_left_logic(R1115, R1115, R0004); +} + +# SHL imm5, reg2 - rrrrr010110iiiii +:shl op0004, R1115 is op0510=0x16 & op0004 & R1115 +{ + shift_left_logic(R1115, R1115, op0004:5); +} + +# SHL reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww00011000010 +:shl R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0xC2 & R2731 +{ + shift_left_logic(R2731, R1115, R0004); +} + +# SHR reg1, reg2 - rrrrr111111RRRRR|0000000010000000 +:shr R0004, R1115 is op0510=0x3F & R0004 & R1115; op1631=0x80 +{ + shift_right_logic(R1115, R1115, R0004); +} + +# SHR imm5, reg2 - rrrrr010100iiiii +:shr op0004, R1115 is op0510=0x14 & op0004 & R1115 +{ + shift_right_logic(R1115, R1115, op0004:5); +} + +# SHR reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww00010000010 +:shr R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x82 & R2731 +{ + shift_right_logic(R2731, R1115, R0004); +} + +# SXB reg1 - 00000000101RRRRR +:sxb R0004 is op0515=0x05 & R0004 +{ + R0004 = sext(R0004:1); +} + +# SXH reg1 - 00000000111RRRRR +:sxh R0004 is op0515=0x07 & R0004 +{ + R0004 = sext(R0004:2); +} + +# ZXB reg1 - 00000000100RRRRR +:zxb R0004 is op0515=0x004 & R0004 +{ + R0004 = zext(R0004:1); +} + +# ZXH reg1 - 00000000110RRRRR +:zxh R0004 is op0515=0x006 & R0004 +{ + R0004 = zext(R0004:2); +} diff --git a/python/icicle/Ghidra/Processors/V850/data/languages/Instructions/Logic.sinc b/python/icicle/Ghidra/Processors/V850/data/languages/Instructions/Logic.sinc new file mode 100644 index 0000000..e0a5112 --- /dev/null +++ b/python/icicle/Ghidra/Processors/V850/data/languages/Instructions/Logic.sinc @@ -0,0 +1,167 @@ +# (6) Conditional arithmetic instructions +# (8) Logical instructions +# (14) Bit manipulation instructions + + + +##################################################### +##### Conditional ##### +##################################################### + + +# ADF cccc, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww011101cccc0 +:adf^c1720 R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op2126=0x1D & op1616=0 & c1720 & R2731 +{ + local cond = zext(c1720); + set_OV_pos2(R1115, R0004, cond); + set_CY_pos2(R1115, R0004, cond); + R2731 = R1115 + R0004 + cond; + set_S(R2731); + set_Z(R2731); +} + +# SBF cccc, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww011100cccc0 +:sbf^c1720 R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op2126=0x1C & op1616=0 & c1720 & R2731 +{ + local cond = zext(c1720); + set_OV_neg2(R1115, R0004, cond); + set_CY_neg2(R1115, R0004, cond); + R2731 = R1115 - R0004 - cond; + set_S(R2731); + set_Z(R2731); +} + + + +##################################################### +##### Logic ##### +##################################################### + + +# AND reg1, reg2 - rrrrr001010RRRRR +:and R0004, R1115 is op0510=0x0A & R0004 & R1115 +{ + R1115 = R1115 & R0004; + set_OV0_S_Z(R1115); +} + +# ANDI imm16, reg1, reg2 - rrrrr110110RRRRR|iiiiiiiiiiiiiiii +:andi op1631, R0004, R1115 is op0510=0x36 & R1115 & R0004; op1631 +{ + R1115 = R0004 & op1631; + set_OV0_S_Z(R1115); +} + +# NOT reg1, reg2 - rrrrr000001RRRRR +:not R0004, R1115 is op0510=0x01 & R0004 & R1115 +{ + R1115 = ~R0004; + set_OV0_S_Z(R1115); +} + +# OR reg1, reg2 - rrrrr001000RRRRR +:or R0004, R1115 is op0510=0x08 & R0004 & R1115 +{ + R1115 = R1115 | R0004; + set_OV0_S_Z(R1115); +} + +# ORI imm16, reg1, reg2 - rrrrr110100RRRRR|iiiiiiiiiiiiiiii +:ori op1631, R0004, R1115 is op0510=0x34 & R1115 & R0004; op1631 +{ + R1115 = R0004 | op1631; + set_OV0_S_Z(R1115); +} + +# TST reg1, reg2 - rrrrr001011RRRRR +:tst R0004, R1115 is op0510=0x0B & R0004 & R1115 +{ + set_OV0_S_Z(R1115 & R0004); +} + +# XOR reg1, reg2 - rrrrr001001RRRRR +:xor R0004, R1115 is op0510=0x09 & R0004 & R1115 +{ + R1115 = R1115 ^ R0004; + set_OV0_S_Z(R1115); +} + +# XORI imm16, reg1, reg2 - rrrrr110101RRRRR|iiiiiiiiiiiiiiii +:xori op1631, R0004, R1115 is op0510=0x35 & R1115 & R0004; op1631 +{ + R1115 = R0004 ^ op1631; + set_OV0_S_Z(R1115); +} + + + +##################################################### +##### BitManipulation ##### +##################################################### + + +# CLR1 bit#3, disp16[reg1] - 10bbb111110RRRRR|dddddddddddddddd +:clr1 op1113, s1631[R0004] is op0510=0x3E & op1415=2 & op1113 & R0004; s1631 +{ + local adr:4 = R0004 + s1631; + local tkn = *:1 adr; + *:1 adr = tkn & ~(1 << op1113); + set_Z(tkn & (1 << op1113)); +} + +# CLR1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100100 +:clr1 R1115, [R0004] is op0510=0x3F & R0004 & R1115; op1631=0xE4 +{ + local tkn = *:1 R0004; + *:1 R0004 = tkn & ~(1 << R1115); + set_Z(tkn & (1 << R1115)); +} + +# NOT1 bit#3, disp16[reg1] - 01bbb111110RRRRR|dddddddddddddddd +:not1 op1113, s1631[R0004] is op0510=0x3E & op1415=1 & op1113 & R0004; s1631 +{ + local adr:4 = R0004 + s1631; + local tkn = *:1 adr; + *:1 adr = tkn ^ (1 << op1113); + set_Z(tkn & (1 << op1113)); +} + +# NOT1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100010 +:not1 R1115, [R0004] is op0510=0x3F & R0004 & R1115; op1631=0xE2 +{ + local tkn = *:1 R0004; + *:1 R0004 = tkn ^ (1 << R1115); + set_Z(tkn & (1 << R1115)); +} + +# SET1 bit#3, disp16[reg1] - 00bbb111110RRRRR|dddddddddddddddd +:set1 op1113, s1631[R0004] is op0510=0x3E & op1415=0 & op1113 & R0004; s1631 +{ + local adr:4 = R0004 + s1631; + local tkn = *:1 adr; + *:1 adr = tkn | (1 << op1113); + set_Z(tkn & (1 << op1113)); +} + +# SET1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100000 +:set1 R1115, [R0004] is op0510=0x3F & R0004 & R1115; op1631=0xE0 +{ + local tkn = *:1 R0004; + *:1 R0004 = tkn | (1 << R1115); + set_Z(tkn & (1 << R1115)); +} + +# TST1 bit#3, disp16[reg1] - 11bbb111110RRRRR|dddddddddddddddd +:tst1 op1113, s1631[R0004] is op0510=0x3E & op1415=3 & op1113 & R0004; s1631 +{ + local adr:4 = R0004 + s1631; + local tkn = *:1 adr; + set_Z(tkn & (1 << op1113)); +} + +# TST1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100110 +:tst1 R0004, [R1115] is op0510=0x3F & R0004 & R1115; op1631=0xE6 +{ + local tkn = *:1 R0004; + set_Z(tkn & (1 << R1115)); +} diff --git a/python/icicle/Ghidra/Processors/V850/data/languages/Instructions/Special.sinc b/python/icicle/Ghidra/Processors/V850/data/languages/Instructions/Special.sinc new file mode 100644 index 0000000..f94250e --- /dev/null +++ b/python/icicle/Ghidra/Processors/V850/data/languages/Instructions/Special.sinc @@ -0,0 +1,372 @@ +# (10) Bit search instructions +# (13) Branch instructions +# (15) Special instructions + + + +##################################################### +##### BitSearch ##### +##################################################### + + +# SCH0L reg2, reg3 - rrrrr11111100000|wwwww01101100100 +:sch0l R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x364 & R2731 +{ + SearchLeft(R2731, R1115, 0); + $(CY) = (R1115 != 0xFFFFFFFF); # zero bit found + $(Z) = (R1115 == 0xFFFFFFFF); # zero bit not found +} + +# SCH0R reg2, reg3 - rrrrr11111100000|wwwww01101100000 +:sch0r R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x360 & R2731 +{ + SearchRight(R2731, R1115, 0); + $(CY) = (R1115 != 0xFFFFFFFF); # zero bit found + $(Z) = (R1115 == 0xFFFFFFFF); # zero bit not found +} + +# SCH1L reg2, reg3 - rrrrr11111100000|wwwww01101100110 +:sch1l R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x366 & R2731 +{ + SearchLeft(R2731, R1115, 1); + $(CY) = (R1115 != 0x0); # one bit found + $(Z) = (R1115 == 0x0); # one bit not found +} + +# SCH1R reg2, reg3 +:sch1r R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x362 & R2731 +{ + SearchRight(R2731, R1115, 1); + $(CY) = (R1115 != 0x0); # one bit found + $(Z) = (R1115 == 0x0); # one bit not found +} + + + +##################################################### +##### Branch ##### +##################################################### + + +#Bcond adr9 - ddddd1011dddcccc +:b^c0003 adr9 is op0710=0xB & c0003 & adr9 +{ + if (c0003) + goto adr9; +} +:br adr9 is op0710=0xB & op0003=0x5 & adr9 +{ + goto adr9; +} + +# JARL disp22, reg2 - rrrrr11110dddddd|ddddddddddddddd0 +:jarl adr22, R1115 is (op0610=0x1E & R1115) ... & adr22 +{ + R1115 = inst_next; + call adr22; +} + +# JARL disp32, reg1 - 00000010111RRRRR|ddddddddddddddd0|DDDDDDDDDDDDDDDD +:jarl adr32, R0004 is op0515=0x017 & R0004; adr32 +{ + R0004 = inst_next; + call adr32; +} + +# JMP [reg1] - 00000000011RRRRR +:jmp [R0004] is op0515=0x03 & R0004 & op0004=0x1F +{ + return [R0004]; +} +:jmp [R0004] is op0515=0x03 & R0004 & op0004!=0x1F +{ + call [R0004]; +} + +# JMP disp32[reg1] - 00000110111RRRRR|ddddddddddddddd0|DDDDDDDDDDDDDDDD +:jmp adr32i[R0004] is op0515=0x037 & R0004; adr32i +{ + local adr = adr32i + R0004; + goto [adr]; +} + +# JR disp22 - 00000111110ddddd|ddddddddddddddd0 +:jr adr22 is op0615=0x1E ... & adr22 +{ + goto adr22; +} + +# JR disp32 - 0000001011100000|ddddddddddddddd0|DDDDDDDDDDDDDDDD +:jr adr32 is op0015=0x2E0; adr32 +{ + goto adr32; +} + + + +##################################################### +##### Special ##### +##################################################### + + +# CALLT imm6 - 0000001000iiiiii +:callt op0005 is op0615=0x8 & op0005 +{ + CTPC = inst_next; + CTPSW = PSW; + local adr:4 = CTBP + (op0005 << 1); + PC = CTBP + zext(*:2 adr); + call [PC]; +} + +# CAXI [reg1], reg2, reg3 - rrrrr111111RRRRR|wwwww00011101110 +:caxi [R0004], R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0xEE & R2731 +{ + local tkn = *:4 (R0004 & ~(0x3)); + local result = R1115 - tkn; + *:4 R0004 = tkn * zext(result != 0) + R2731 * zext(result == 0); + R2731 = tkn; + set_general_flags_neg(R1115, tkn); +} + +# CTRET - 0000011111100000|0000000101000100 +:ctret is op0515=0x3F; op1631=0x144 +{ + PC = CTPC; + PSW = CTPSW; + return [PC]; +} + +# DI - 0000011111100000|0000000101100000 +define pcodeop __disable_irq; +:di is op0015=0x7E0; op1631=0x160 +{ + $(ID) = 1; + __disable_irq(); +} + +# DISPOSE imm5, list12 - 0000011001iiiiiL|LLLLLLLLLLL00000 +:dispose prep0105, DispList is prep0615=0x19 & prep1620=0x0 & prep0105 & DispList +{ + sp = sp + (prep0105 << 2); + build DispList; +} + +# DISPOSE imm5, list12, [reg1] - 0000011001iiiiiL|LLLLLLLLLLLRRRRR +:dispose prep0105, DispList, [prep1620] is prep0615=0x19 & prep1620 & prep0105 & DispList +{ + sp = sp + (prep0105 << 2); + build DispList; + PC = prep1620; + return [PC]; +} + +# EI - 1000011111100000|0000000101100000 +define pcodeop __enable_irq; +:ei is op0015=0x87E0; op1631=0x160 +{ + $(ID) = 0; + __enable_irq(); +} + +# EIRET - 0000011111100000|0000000101001000 +:eiret is op0515=0x3F; op1631=0x148 +{ + PC = EIPC; + PSW = EIPSW; + return [PC]; +} + +# FERET - 0000011111100000|0000000101001010 +:feret is op0515=0x3F; op1631=0x14A +{ + PC = FEPC; + PSW = FEPSW; + return [PC]; +} + +# FETRAP vector4 - 0vvvv00001000000 +:fetrap op1114 is op0010=0x40 & op1515=0 & op1114 & op1115!=0 +{ + FEPC = inst_next; + FEPSW = PSW; + $(FECC) = op1114 + 0x30; # exception code 0x30..0x3F + FEIC = op1114 + 0x30; # exception code 0x30..0x3F + $(EP) = 1; + $(ID) = 1; + $(NP) = 1; + PC = 0x30; + goto [PC]; +} + +# HALT - 0000011111100000|0000000100100000 +define pcodeop __halt; +:halt is op0015=0x7E0; op1631=0x120 +{ + __halt(); +} + +# LDSR reg2, regID - rrrrr111111RRRRR|0000000000100000 +:ldsr R0004, SR1115 is op0510=0x3F & SR1115 & R0004; op1631=0x20 +{ + SR1115 = R0004; +} + +# NOP - 0000000000000000 +:nop is op0015=0x0 +{ + PC = inst_next; +} + +# PREPARE list12, imm5 - 0000011110iiiiiL|LLLLLLLLLLL00001 +:prepare PrepList, prep0105 is prep0615=0x1E & prep0105 & prep1620=0x1 & PrepList +{ + build PrepList; + sp = sp - (prep0105 << 2); +} + +# PREPARE list12, imm5, sp - 0000011110iiiiiL|LLLLLLLLLLL00011 +:prepare PrepList, prep0105, sp is prep0615=0x1E & prep0105 & prep1620=0x3 & PrepList & sp +{ + build PrepList; + sp = sp - (prep0105 << 2); + ep = sp; +} + +# PREPARE list12, imm5, imm16 (low) - 0000011110iiiiiL|LLLLLLLLLLL01011|iiiiiiiiiiiiiiii +:prepare PrepList, prep0105, s3247 is prep0615=0x1E & prep0105 & prep1620=0xB & PrepList; s3247 +{ + build PrepList; + sp = sp - (prep0105 << 2); + ep = s3247; +} + +# PREPARE list12, imm5, imm16 (high) - 0000011110iiiiiL|LLLLLLLLLLL10011|iiiiiiiiiiiiiiii +:prepare PrepList, prep0105, s3247 is prep0615=0x1E & prep0105 & prep1620=0x13 & PrepList; s3247 +{ + build PrepList; + sp = sp - (prep0105 << 2); + ep = s3247 << 16; +} + +# PREPARE list12, imm5, imm32 - 0000011110iiiiiL|LLLLLLLLLLL11011|iiiiiiiiiiiiiiii|iiiiiiiiiiiiiiii +:prepare PrepList, prep0105, imm32 is prep0615=0x1E & prep0105 & prep1620=0x1B & PrepList; op3247; op4863 +[ imm32 = (op4863 << 16) | op3247; ] +{ + build PrepList; + sp = sp - (prep0105 << 2); + ep = imm32; +} + +# RETI - 0000011111100000|0000000101000000 +:reti is op0515=0x3F; op1631=0x140 +{ + if($(EP)!=1) + goto ; + + PC = EIPC; + PSW = EIPSW; + goto ; + + + if($(NP)!=1) + goto ; + + PC = FEPC; + PSW = FEPSW; + goto ; + + + PC = EIPC; + PSW = EIPSW; + + + return[PC]; +} + +# RIE - 0000000001000000 +:rie is op0015=0x40 +{ + FEPC = PC; + FEPSW = PSW; + $(NP) = 1; + $(EP) = 1; + $(ID) = 1; + PC = 0x30; + goto [PC]; +} + +# RIE imm5, imm4 - iiiii1111111IIII|0000000000000000 +:rie op1115, op0003 is op0410=0x7F & op1115 & op0003; op1631=0x0 +{ + FEPC = PC; + FEPSW = PSW; + $(NP) = 1; + $(EP) = 1; + $(ID) = 1; + PC = 0x30; + goto [PC]; +} + +# STSR regID, reg2 - rrrrr111111RRRRR|0000000001000000 +:stsr SR0004, R1115 is op0510=0x3F & R1115 & SR0004; op1631=0x40 +{ + R1115 = SR0004; +} + +# SWITCH reg1 - 00000000010RRRRR +:switch R0004 is op0515=0x2 & R0004 +{ + local adr:4 = inst_next + (R0004 << 1); + PC = inst_next + (sext(*:2 adr) << 1); + goto [PC]; +} + +# SYNCE - 0000000000011101 +define pcodeop __synchronize; +:synce is op0015=0x1D +{ + __synchronize(); +} + +# SYNCM - 0000000000011110 +:syncm is op0015=0x1E +{ + __synchronize(); +} + +# SYNCP - 0000000000011111 +:syncp is op0015=0x1F +{ + __synchronize(); +} + +# SYSCALL vector8 - 11010111111vvvvv|00VVV00101100000 +:syscall vector8 is op0515=0x6BF & op0004; op3031=0 & op2729 & op1626=0x160 +[ vector8 = (op2729 << 5) | op0004; ] +{ + EIPC = inst_next; + EIPSW = PSW; + EIIC = vector8 + 0x8000; # exception code 0x8000..0x80FF + $(EICC) = vector8 + 0x8000; # exception code 0x8000..0x80FF + $(EP) = 1; + $(ID) = 1; + local adr:4; + either_or(adr, (vector8 <= SCCFG), SCBP + (vector8 << 2), SCBP); + PC = SCBP + (*:4 adr); + call [PC]; +} + +# TRAP imm5 - 00000111111vvvvv|0000000100000000 +:trap op0004 is op0515=0x3F & op0004; op1631=0x100 +{ + local vector5:4 = op0004; + EIPC = inst_next; + EIPSW = PSW; + EIIC = vector5 + 0x40; # exception code 0x40..0x5F + $(EICC) = vector5:2 + 0x40; # exception code 0x40..0x5F + $(EP) = 1; + $(ID) = 1; + either_or(PC, (vector5 <= 15), 0x40, 0x50); + call [PC]; +} diff --git a/python/icicle/Ghidra/Processors/V850/data/languages/V850.cspec b/python/icicle/Ghidra/Processors/V850/data/languages/V850.cspec new file mode 100644 index 0000000..73480dc --- /dev/null +++ b/python/icicle/Ghidra/Processors/V850/data/languages/V850.cspec @@ -0,0 +1,68 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/V850/data/languages/V850.ldefs b/python/icicle/Ghidra/Processors/V850/data/languages/V850.ldefs new file mode 100644 index 0000000..d0e197a --- /dev/null +++ b/python/icicle/Ghidra/Processors/V850/data/languages/V850.ldefs @@ -0,0 +1,16 @@ + + + + + Renesas V850 family + + + diff --git a/python/icicle/Ghidra/Processors/V850/data/languages/V850.opinion b/python/icicle/Ghidra/Processors/V850/data/languages/V850.opinion new file mode 100644 index 0000000..94a0279 --- /dev/null +++ b/python/icicle/Ghidra/Processors/V850/data/languages/V850.opinion @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/python/icicle/Ghidra/Processors/V850/data/languages/V850.pspec b/python/icicle/Ghidra/Processors/V850/data/languages/V850.pspec new file mode 100644 index 0000000..02fa940 --- /dev/null +++ b/python/icicle/Ghidra/Processors/V850/data/languages/V850.pspec @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/V850/data/languages/V850.slaspec b/python/icicle/Ghidra/Processors/V850/data/languages/V850.slaspec new file mode 100644 index 0000000..633e0e3 --- /dev/null +++ b/python/icicle/Ghidra/Processors/V850/data/languages/V850.slaspec @@ -0,0 +1,37 @@ +##################################################### +##### ##### +##### V850E2M SLEIGH specification ##### +##### ##### +##################################################### + +define endian = little; +define alignment = 2; + +# Size & default are required +define space ram type=ram_space size=4 default; +define space register type=register_space size=4; + + + +##################################################### +##### Helpers ##### +##################################################### + +@include "./Helpers/Register.sinc" +@include "./Helpers/Tokens.sinc" +@include "./Helpers/Variables.sinc" +@include "./Helpers/Conditions.sinc" +@include "./Helpers/Macros.sinc" +@include "./Helpers/Extras.sinc" + + + +##################################################### +##### Instructions ##### +##################################################### + +@include "./Instructions/Arithmetic.sinc" +@include "./Instructions/Float.sinc" +@include "./Instructions/Load_Store.sinc" +@include "./Instructions/Logic.sinc" +@include "./Instructions/Special.sinc" diff --git a/python/icicle/Ghidra/Processors/Z80/data/languages/z180.pspec b/python/icicle/Ghidra/Processors/Z80/data/languages/z180.pspec new file mode 100644 index 0000000..c69838f --- /dev/null +++ b/python/icicle/Ghidra/Processors/Z80/data/languages/z180.pspec @@ -0,0 +1,114 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Z80/data/languages/z180.slaspec b/python/icicle/Ghidra/Processors/Z80/data/languages/z180.slaspec new file mode 100644 index 0000000..e2a41dc --- /dev/null +++ b/python/icicle/Ghidra/Processors/Z80/data/languages/z180.slaspec @@ -0,0 +1,3 @@ +@define Z180 "" + +@include "z80.slaspec" diff --git a/python/icicle/Ghidra/Processors/Z80/data/languages/z182.pspec b/python/icicle/Ghidra/Processors/Z80/data/languages/z182.pspec new file mode 100644 index 0000000..f055025 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Z80/data/languages/z182.pspec @@ -0,0 +1,153 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Z80/data/languages/z80.cspec b/python/icicle/Ghidra/Processors/Z80/data/languages/z80.cspec new file mode 100644 index 0000000..33418cf --- /dev/null +++ b/python/icicle/Ghidra/Processors/Z80/data/languages/z80.cspec @@ -0,0 +1,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Z80/data/languages/z80.ldefs b/python/icicle/Ghidra/Processors/Z80/data/languages/z80.ldefs new file mode 100644 index 0000000..fbd65f7 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Z80/data/languages/z80.ldefs @@ -0,0 +1,57 @@ + + + + + Zilog Z80 + + + + + + Zilog Z8401x (IPC) microcontroller + + + + + + Zilog Z180 + + + + + Zilog Z182 + + + diff --git a/python/icicle/Ghidra/Processors/Z80/data/languages/z80.pspec b/python/icicle/Ghidra/Processors/Z80/data/languages/z80.pspec new file mode 100644 index 0000000..6439c45 --- /dev/null +++ b/python/icicle/Ghidra/Processors/Z80/data/languages/z80.pspec @@ -0,0 +1,43 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/Z80/data/languages/z80.slaspec b/python/icicle/Ghidra/Processors/Z80/data/languages/z80.slaspec new file mode 100644 index 0000000..1d73e1a --- /dev/null +++ b/python/icicle/Ghidra/Processors/Z80/data/languages/z80.slaspec @@ -0,0 +1,2078 @@ +# sleigh specification file for Zilog Z80 + +# TODO: Improve Flag bit implementation so that bit operations on F register work properly + +define endian=little; +define alignment=1; +@if defined(Z180) +define space ram type=ram_space size=2 default; +@define PTRSIZE "2" +@else +define space ram type=ram_space size=2 default; +@define PTRSIZE "2" +@endif + +define space io type=ram_space size=2; +define space register type=register_space size=1; + +define register offset=0x00 size=1 [ F A C B E D L H I R ]; +define register offset=0x00 size=2 [ AF BC DE HL ]; +define register offset=0x20 size=1 [ F_ A_ C_ B_ E_ D_ L_ H_ ]; # Alternate registers +define register offset=0x20 size=2 [ AF_ BC_ DE_ HL_ ]; # Alternate registers +define register offset=0x40 size=2 [ _ PC SP IX IY ]; + +define register offset=0x50 size=1 [ rCBAR rCBR rBBR ]; + +# Fake Registers used for pcode control +define register offset=0x60 size=1 [ + DECOMPILE_MODE +]; + +# Define context bits +define register offset=0xf0 size=4 contextreg; + define context contextreg + assume8bitIOSpace =(0,0) # only applies to Z180 + ; +# Flag bits (?? manual is very confusing - could be typos!) +@define C_flag "F[0,1]" # C: Carry +@define N_flag "F[1,1]" # N: Add/Subtract - used by DAA to distinguish between ADD and SUB instructions (0=ADD,1=SUB) +@define PV_flag "F[2,1]" # PV: Parity/Overflow +@define H_flag "F[4,1]" # H: Half Carry +@define Z_flag "F[6,1]" # Z: Zero +@define S_flag "F[7,1]" # S: Sign + +define token opbyte (8) + op0_8 = (0,7) + op6_2 = (6,7) + dRegPair4_2 = (4,5) + pRegPair4_2 = (4,5) + sRegPair4_2 = (4,5) + qRegPair4_2 = (4,5) + rRegPair4_2 = (4,5) + reg3_3 = (3,5) + bits3_3 = (3,5) + bits0_4 = (0,3) + reg0_3 = (0,2) + bits0_3 = (0,2) +; + +define token data8 (8) + imm8 = (0,7) + sign8 = (7,7) + simm8 = (0,7) signed +; + +define token data16 (16) + timm4 = (12,15) + imm16 = ( 0,15) + sign16 = (15,15) + simm16 = ( 0,15) signed +; + +attach variables [ reg0_3 reg3_3 ] [ B C D E H L _ A ]; + +attach variables [ sRegPair4_2 dRegPair4_2 ] [ BC DE HL SP ]; + +attach variables [ qRegPair4_2 ] [ BC DE HL AF ]; + +attach variables [ pRegPair4_2 ] [ BC DE IX SP ]; +attach variables [ rRegPair4_2 ] [ BC DE IY SP ]; +################################################################ +# Pseudo Instructions +################################################################ +define pcodeop segment; # Define special pcodeop that calculates the RAM address +# given the segment selector and offset as input + +define pcodeop BCDadjust; +define pcodeop BCDadjustCarry; + +define pcodeop hasEvenParity; +define pcodeop disableMaskableInterrupts; +define pcodeop enableMaskableInterrupts; +define pcodeop setInterruptMode; +define pcodeop parity; +define pcodeop sleep; +define pcodeop halt; + +################################################################ +# Macros +################################################################ + +macro setResultFlags(result) { + $(Z_flag) = (result == 0); + $(S_flag) = (result s< 0); +} + +macro additionFlags(operand1, operand2) { + local AFmask = -1 >> 4; + $(H_flag) = (((operand1 & AFmask) + (operand2 & AFmask)) & (AFmask + 1)) != 0; + $(PV_flag) = scarry(operand1, operand2); + $(N_flag) = 0; + $(C_flag) = carry(operand1, operand2); +} + +macro additionFlagsNoPV(operand1, operand2) { + local AFmask = -1 >> 4; + $(H_flag) = (((operand1 & AFmask) + (operand2 & AFmask)) & (AFmask + 1)) != 0; +# $(PV_flag) is not affected + $(N_flag) = 0; + $(C_flag) = carry(operand1, operand2); +} + +macro additionWithCarry(operand1, operand2, result) { + local Ccopy = zext($(C_flag)); + local AFmask = -1 >> 4; + $(H_flag) = (((operand1 & AFmask) + (operand2 & AFmask) + Ccopy) & (AFmask + 1)) != 0; + $(PV_flag) = scarry(operand1, operand2); + $(N_flag) = 0; + $(C_flag) = carry(operand1, operand2); + local tempResult = operand1 + operand2; + $(C_flag) = $(C_flag) || carry(tempResult, Ccopy); + $(PV_flag) = $(PV_flag) ^^ scarry(tempResult, Ccopy); + result = tempResult + Ccopy; +} + +macro subtractionFlags(operand1, operand2) { + local AFmask = -1 >> 4; + $(H_flag) = (((operand1 & AFmask) - (operand2 & AFmask)) & (AFmask + 1)) != 0; + $(PV_flag) = sborrow(operand1, operand2); + $(N_flag) = 1; + $(C_flag) = operand1 < operand2; +} + +macro subtractionFlagsNoC(operand1, operand2) { + local AFmask = -1 >> 4; + $(H_flag) = (((operand1 & AFmask) - (operand2 & AFmask)) & (AFmask + 1)) != 0; + $(PV_flag) = sborrow(operand1, operand2); + $(N_flag) = 1; +# $(C_flag) is not affected +} + +macro subtractionWithCarry(operand1, operand2, result) { + local Ccopy = zext($(C_flag)); + local AFmask = -1 >> 4; + $(H_flag) = (((operand1 & AFmask) - (operand2 & AFmask) - Ccopy) & (AFmask + 1)) != 0; + $(PV_flag) = sborrow(operand1, operand2); + $(N_flag) = 1; + $(C_flag) = operand1 < operand2; + local tempResult = operand1 - operand2; + $(C_flag) = $(C_flag) || (tempResult < Ccopy); + $(PV_flag) = $(PV_flag) ^^ sborrow(tempResult, Ccopy); + result = tempResult - Ccopy; +} + +macro setSubtractFlags(op1,op2) { + $(C_flag) = (op1 < op2); +} + +# places the parity bit of the given byte in out_parity_bit +# the upper 7 bits of out_parity_bit are cleared +macro setParity(in_byte) { + local tmp = in_byte ^ (in_byte >> 1); + tmp = tmp ^ (tmp >> 2); + tmp = (tmp ^ (tmp >> 4)) & 1; + $(PV_flag) = (tmp == 0); + +# $(PV_flag) = hasEvenParity(in_byte); +} + +macro ioWrite(addr,val) { + *[io]:1 addr = val; +} + +macro ioRead(addr,dest) { + dest = *[io]:1 addr; +} +@if defined(Z180_SEGMENTED) + +macro push16(val16) { + SP = SP - 2; + ptr:$(PTRSIZE) = segment(rBBR,SP); + *:2 ptr = val16; +} + +macro pop16(ret16) { + ptr:$(PTRSIZE) = segment(rBBR,SP); + ret16 = *:2 ptr; + SP = SP + 2; +} + +macro push8(val8) { + SP = SP - 1; + ptr:$(PTRSIZE) = segment(rBBR,SP); + *:1 ptr = val8; +} + +macro pop8(ret8) { + ptr:$(PTRSIZE) = segment(rBBR,SP); + ret8 = *:1 ptr; + SP = SP + 1; +} + +macro swap(val16) { + ptr:$(PTRSIZE) = segment(rBBR,SP); + tmp:2 = *:2 ptr; + *:2 ptr = val16; + val16 = tmp; +} + +macro MemRead(dest,off) { + ptr:$(PTRSIZE) = segment(rBBR,off); + dest = *:1 ptr; +} + +macro MemStore(off,val) { + ptr:$(PTRSIZE) = segment(rBBR,off); + *:1 ptr = val; +} + +macro JumpToLoc(off) { + ptr:$(PTRSIZE) = segment(rBBR,off); + goto [ptr]; +} + +@else + +macro push16(val16) { + SP = SP - 2; + *:2 SP = val16; +} + +macro pop16(ret16) { + ret16 = *:2 SP; + SP = SP + 2; +} + +macro push8(val8) { + SP = SP - 1; + ptr:$(PTRSIZE) = SP; + *:1 ptr = val8; +} + +macro pop8(ret8) { + ptr:$(PTRSIZE) = SP; + ret8 = *:1 ptr; + SP = SP + 1; +} + +macro swap(val16) { + ptr:$(PTRSIZE) = SP; + tmp:2 = *:2 ptr; + *:2 ptr = val16; + val16 = tmp; +} + +macro MemRead(dest,off) { + ptr:$(PTRSIZE) = off; + dest = *:1 ptr; +} + +macro MemStore(off,val) { + ptr:$(PTRSIZE) = off; + *:1 ptr = val; +} + +macro JumpToLoc(off) { + ptr:$(PTRSIZE) = off; + goto [ptr]; +} + +@endif +################################################################ +@if defined(Z180) + +Flag: "Flag" is reg0_3 { } + +@endif +@if defined(Z180_SEGMENTED) + +hlMem8: (HL) is HL { ptr:$(PTRSIZE) = segment(rBBR,HL); export *:1 ptr; } + +ixMem8: (IX+simm8) is IX & simm8 { + off:2 = IX + simm8; + ptr:$(PTRSIZE) = segment(rBBR,off); export *:1 ptr; +} +ixMem8: (IX-val) is IX & simm8 & sign8=1 [ val = -simm8; ] { + off:2 = IX + simm8; + ptr:$(PTRSIZE) = segment(rBBR,off); export *:1 ptr; +} + +iyMem8: (IY+simm8) is IY & simm8 { + off:$(PTRSIZE) = simm8; + ptr:$(PTRSIZE) = segment(rBBR,IY); + ptr = ptr + off; export *:1 ptr; +} +iyMem8: (IY-val) is IY & simm8 & sign8=1 [ val = -simm8; ] { + off:$(PTRSIZE) = simm8; + ptr:$(PTRSIZE) = segment(rBBR,IY); + ptr = ptr + off; export *:1 ptr; +} + +@else # if Z180_SEGMENTED +@if defined(Z180) + +hlMem8: (HL) is HL { ptr:$(PTRSIZE) = HL; export *:1 ptr; } +@endif + +ixMem8: (IX+simm8) is IX & simm8 { ptr:$(PTRSIZE) = IX + simm8; export *:1 ptr; } +ixMem8: (IX-val) is IX & simm8 & sign8=1 [ val = -simm8; ] { ptr:$(PTRSIZE) = IX + simm8; export *:1 ptr; } + +iyMem8: (IY+simm8) is IY & simm8 { ptr:$(PTRSIZE) = IY + simm8; export *:1 ptr; } +iyMem8: (IY-val) is IY & simm8 & sign8=1 [ val = -simm8; ] { ptr:$(PTRSIZE) = IY + simm8; export *:1 ptr; } + +@endif # end !Z180_SEGMENTED +@if defined(Z180) + +Addr16: imm16 is imm16 { export *:1 imm16; } + +Mem8: (imm16) is imm16 { export *:1 imm16; } + +Mem16: (imm16) is imm16 { export *:2 imm16; } + +@else + +Addr16: imm16 is imm16 { export *:1 imm16; } + +Mem8: (imm16) is imm16 { export *:1 imm16; } + +Mem16: (imm16) is imm16 { export *:2 imm16; } + +@endif + +RelAddr8: loc is simm8 [ loc = inst_next + simm8; ] { export *:1 loc; } + +RstAddr: loc is bits3_3 [ loc = bits3_3 << 3; ] { export *:1 loc; } +@if defined(Z180) + +IOAddr8: (imm8) is imm8 { export *[const]:2 imm8; } + +IOAddr8a: (imm8) is assume8bitIOSpace=0 & imm8 { ptr:2 = (zext(A) << 8) + imm8; export ptr; } +IOAddr8a: (imm8) is assume8bitIOSpace=1 & imm8 { export *[const]:2 imm8; } + +IOAddrC: (C) is assume8bitIOSpace=0 & C { ptr:2 = (zext(B) << 8) + zext(C); export ptr; } +IOAddrC: (C) is assume8bitIOSpace=1 & C { ptr:2 = zext(C); export ptr; } +@else + +IOAddr8a: (imm8) is imm8 { export *[const]:2 imm8; } + +IOAddrC: (C) is C { ptr:2 = zext(C); export ptr; } +@endif + +cc: "NZ" is bits3_3=0x0 { c:1 = ($(Z_flag) == 0); export c; } +cc: "Z" is bits3_3=0x1 { c:1 = $(Z_flag); export c; } +cc: "NC" is bits3_3=0x2 { c:1 = ($(C_flag) == 0); export c; } +cc: "C" is bits3_3=0x3 { c:1 = $(C_flag); export c; } +cc: "PO" is bits3_3=0x4 { c:1 = ($(PV_flag) == 0); export c; } +cc: "PE" is bits3_3=0x5 { c:1 = $(PV_flag); export c; } +cc: "P" is bits3_3=0x6 { c:1 = ($(S_flag) == 0); export c; } +cc: "M" is bits3_3=0x7 { c:1 = $(S_flag); export c; } + +cc2: "NZ" is bits3_3=0x4 { c:1 = ($(Z_flag) == 0); export c; } +cc2: "Z" is bits3_3=0x5 { c:1 = $(Z_flag); export c; } +cc2: "NC" is bits3_3=0x6 { c:1 = ($(C_flag) == 0); export c; } +cc2: "C" is bits3_3=0x7 { c:1 = $(C_flag); export c; } + +################################################################ +:LD reg3_3,reg0_3 is op6_2=0x1 & reg3_3 & reg0_3 { + reg3_3 = reg0_3; +} + +:LD reg3_3,imm8 is op6_2=0x0 & reg3_3 & bits0_3=0x6; imm8 { + reg3_3 = imm8; +} + +:LD reg3_3,(HL) is op6_2=0x1 & reg3_3 & bits0_3=0x6 & HL { + MemRead(reg3_3,HL); +} + +:LD reg3_3,ixMem8 is op0_8=0xdd; op6_2=0x1 & reg3_3 & bits3_3!=0x6 & bits0_3=0x6; ixMem8 { + reg3_3 = ixMem8; +} + +:LD reg3_3,iyMem8 is op0_8=0xfd; op6_2=0x1 & reg3_3 & bits3_3!=0x6 & bits0_3=0x6; iyMem8 { + reg3_3 = iyMem8; +} + +:LD (HL),reg0_3 is op6_2=0x1 & bits3_3=0x6 & reg0_3 & HL { + MemStore(HL,reg0_3); +} + +:LD ixMem8,reg0_3 is op0_8=0xdd; op6_2=0x1 & bits3_3=0x6 & reg0_3 & bits0_3!=0x6; ixMem8 { + ixMem8 = reg0_3; +} + +:LD iyMem8,reg0_3 is op0_8=0xfd; op6_2=0x1 & bits3_3=0x6 & reg0_3 & bits0_3!=0x6; iyMem8 { + iyMem8 = reg0_3; +} + +:LD (HL),imm8 is op0_8=0x36 & HL; imm8 { + tmp:1 = imm8; + MemStore(HL,tmp); +} + +:LD ixMem8,imm8 is op0_8=0xdd; op6_2=0x0 & bits3_3=0x6 & bits0_3=0x6; ixMem8; imm8 { + ixMem8 = imm8; +} + +:LD iyMem8,imm8 is op0_8=0xfd; op6_2=0x0 & bits3_3=0x6 & bits0_3=0x6; iyMem8; imm8 { + iyMem8 = imm8; +} + +:LD A,(BC) is op0_8=0x0a & A & BC { + MemRead(A,BC); +} + +:LD A,(DE) is op0_8=0x1a & A & DE { + MemRead(A,DE); +} + +:LD A,Mem8 is op0_8=0x3a & A; Mem8 { + A = Mem8; +} + +:LD (BC),A is op0_8=0x2 & BC & A { + MemStore(BC,A); +} + +:LD (DE),A is op0_8=0x12 & DE & A { + MemStore(DE,A); +} + +:LD Mem8,A is op0_8=0x32 & A; Mem8 { + Mem8 = A; +} + +:LD A,I is op0_8=0xed & A & I; op0_8=0x57 { + A = I; + setResultFlags(I); + $(H_flag) = 0; +# $(PV_flag) = IFF2; + $(N_flag) = 0; +} + +:LD A,R is op0_8=0xed & A & R; op0_8=0x5f { + A = R; + setResultFlags(R); + $(H_flag) = 0; +# $(PV_flag) = IFF2; + $(N_flag) = 0; +} + +:LD I,A is op0_8=0xed & A & I; op0_8=0x47 { + I = A; +} + +:LD R,A is op0_8=0xed & A & R; op0_8=0x4f { + R = A; +} + +:LD dRegPair4_2,imm16 is op6_2=0x0 & dRegPair4_2 & bits0_4=0x1; imm16 { + dRegPair4_2 = imm16; +} + +:LD IX,imm16 is op0_8=0xdd & IX; op0_8=0x21; imm16 { + IX = imm16; +} + +:LD IY,imm16 is op0_8=0xfd & IY; op0_8=0x21; imm16 { + IY = imm16; +} + +:LD HL,Mem16 is op0_8=0x2a & HL; Mem16 { + HL = Mem16; +} + +:LD dRegPair4_2,Mem16 is op0_8=0xed; op6_2=0x1 & dRegPair4_2 & bits0_4=0xb; Mem16 { + dRegPair4_2 = Mem16; +} + +:LD IX,Mem16 is op0_8=0xdd & IX; op0_8=0x2a; Mem16 { + IX = Mem16; +} + +:LD IY,Mem16 is op0_8=0xfd & IY; op0_8=0x2a; Mem16 { + IY = Mem16; +} + +:LD Mem16,HL is op0_8=0x22 & HL; Mem16 { + Mem16 = HL; +} + +:LD Mem16,dRegPair4_2 is op0_8=0xed; op6_2=0x1 & dRegPair4_2 & bits0_4=0x3; Mem16 { + Mem16 = dRegPair4_2; +} + +:LD Mem16,IX is op0_8=0xdd & IX; op0_8=0x22; Mem16 { + Mem16 = IX; +} + +:LD Mem16,IY is op0_8=0xfd & IY; op0_8=0x22; Mem16 { + Mem16 = IY; +} + +:LD SP,HL is op0_8=0xf9 & SP & HL { + SP = HL; +} + +:LD SP,IX is op0_8=0xdd & SP & IX; op0_8=0xf9 { + SP = IX; +} + +:LD SP,IY is op0_8=0xfd & SP & IY; op0_8=0xf9 { + SP = IY; +} + +:PUSH qRegPair4_2 is op6_2=0x3 & qRegPair4_2 & bits0_4=0x5 { + push16(qRegPair4_2); +} + +:PUSH IX is op0_8=0xdd & IX; op0_8=0xe5 { + push16(IX); +} + +:PUSH IY is op0_8=0xfd & IY; op0_8=0xe5 { + push16(IY); +} + +:POP qRegPair4_2 is op6_2=0x3 & qRegPair4_2 & bits0_4=0x1 { + pop16(qRegPair4_2); +} + +:POP IX is op0_8=0xdd & IX; op0_8=0xe1 { + pop16(IX); +} + +# ?? Manual appears to have incorrect encoding +:POP IY is op0_8=0xfd & IY; op0_8=0xe1 { + pop16(IY); +} + +:EX DE,HL is op0_8=0xeb & DE & HL { + tmp:2 = DE; + DE = HL; + HL = tmp; +} + +:EX AF, AF_ is op0_8=0x08 & AF & AF_ { + tmp:2 = AF; + AF = AF_; + AF_ = tmp; +} + +:EXX is op0_8=0xd9 { + tmp:2 = BC; + BC = BC_; + BC_ = tmp; + tmp = DE; + DE = DE_; + DE_ = tmp; + tmp = HL; + HL = HL_; + HL_ = tmp; +} + +:EX (SP),HL is op0_8=0xe3 & SP & HL { + swap(HL); +} + +:EX (SP),IX is op0_8=0xdd & SP & IX; op0_8=0xe3 { + swap(IX); +} + +:EX (SP),IY is op0_8=0xfd & SP & IY; op0_8=0xe3 { + swap(IY); +} + +# ?? Instruction manual contradicts itself - not sure what to do here ?? +:LDI is op0_8=0xed; op0_8=0xa0 { + val:1 = 0; + MemRead(val,HL); + MemStore(DE,val); + DE = DE + 1; + HL = HL + 1; + BC = BC - 1; + $(H_flag) = 0; + $(PV_flag) = (BC != 0); + $(N_flag) = 0; +} + +:LDIR is op0_8=0xed; op0_8=0xb0 { + tmp:1 = 0; + MemRead(tmp,HL); + MemStore(DE,tmp); + DE = DE + 1; + HL = HL + 1; + BC = BC - 1; + if (BC != 0) goto inst_start; + $(H_flag) = 0; + $(PV_flag) = (BC != 0); + $(N_flag) = 0; +} + +:LDD is op0_8=0xed; op0_8=0xa8 { + DE = DE - 1; + HL = HL - 1; + BC = BC - 1; + $(H_flag) = 0; + $(PV_flag) = (BC != 0); + $(N_flag) = 0; +} + +:LDDR is op0_8=0xed; op0_8=0xb8 { + tmp:1 = 0; + MemRead(tmp,HL); + MemStore(DE,tmp); + DE = DE - 1; + HL = HL - 1; + BC = BC - 1; + if (BC != 0) goto inst_start; + $(H_flag) = 0; + $(PV_flag) = 0; + $(N_flag) = 0; +} + +:CPI is op0_8=0xed; op0_8=0xa1 { + val:1 = 0; + MemRead(val,HL); + cmp:1 = A - val; + setResultFlags(cmp); + HL = HL + 1; + BC = BC - 1; + + carries:1 = (~A & val) | (val & cmp) | (cmp & ~A); + $(H_flag) = (carries & 0b00001000) != 0; + $(PV_flag) = (BC != 0); + $(N_flag) = 1; +} + +:CPIR is op0_8=0xed; op0_8=0xb1 { + val:1 = 0; + MemRead(val,HL); + cmp:1 = A - val; + setResultFlags(cmp); + HL = HL + 1; + BC = BC - 1; + + if (cmp != 0 || BC != 0) goto inst_start; + + carries:1 = (~A & val) | (val & cmp) | (cmp & ~A); + $(H_flag) = (carries & 0b00001000) != 0; + $(PV_flag) = (BC != 0); + $(N_flag) = 1; +} + +:CPD is op0_8=0xed; op0_8=0xa9 { + val:1 = 0; + MemRead(val,HL); + cmp:1 = A - val; + setResultFlags(cmp); + HL = HL - 1; + BC = BC - 1; + + carries:1 = (~A & val) | (val & cmp) | (cmp & ~A); + $(H_flag) = (carries & 0b00001000) != 0; + $(PV_flag) = (BC != 0); + $(N_flag) = 1; +} + +:CPDR is op0_8=0xed; op0_8=0xb9 { + val:1 = 0; + MemRead(val,HL); + cmp:1 = A - val; + setResultFlags(cmp); + HL = HL - 1; + BC = BC - 1; + + if (cmp != 0 || BC != 0) goto inst_start; + + carries:1 = (~A & val) | (val & cmp) | (cmp & ~A); + $(H_flag) = (carries & 0b00001000) != 0; + $(PV_flag) = (BC != 0); + $(N_flag) = 1; +} + +:ADD A, reg0_3 is op6_2=0x2 & bits3_3=0x0 & reg0_3 & A { + local A_temp = A; + local reg_temp = reg0_3; + + A = A + reg0_3; + setResultFlags(A); + additionFlags(A_temp, reg_temp); +} + +:ADD A, imm8 is op0_8=0xc6; imm8 & A { + local A_temp = A; + + A = A + imm8; + setResultFlags(A); + additionFlags(A_temp, imm8); +} + +:ADD A, (HL) is op0_8=0x86 & HL & A { + val:1 = 0; + MemRead(val,HL); + local A_temp = A; + + A = A + val; + setResultFlags(A); + additionFlags(A_temp, val); +} + +:ADD A, ixMem8 is op0_8=0xdd; op0_8=0x86; ixMem8 & A { + val:1 = ixMem8; + local A_temp = A; + + A = A + val; + setResultFlags(A); + additionFlags(A_temp, val); +} + +:ADD A, iyMem8 is op0_8=0xfd; op0_8=0x86; iyMem8 & A { + val:1 = iyMem8; + local A_temp = A; + + A = A + val; + setResultFlags(A); + additionFlags(A_temp, val); +} + +:ADC A, reg0_3 is op6_2=0x2 & bits3_3=0x1 & reg0_3 & A { + additionWithCarry(A, reg0_3, A); + setResultFlags(A); +} + +:ADC A, imm8 is op0_8=0xce; imm8 & A { + additionWithCarry(A, imm8, A); + setResultFlags(A); +} + +:ADC A, (HL) is op0_8=0x8e & HL & A { + val:1 = 0; + MemRead(val,HL); + additionWithCarry(A, val, A); + setResultFlags(A); +} + +:ADC A, ixMem8 is op0_8=0xdd; op0_8=0x8e; ixMem8 & A{ + val:1 = ixMem8; + additionWithCarry(A, val, A); + setResultFlags(A); +} + +:ADC A, iyMem8 is op0_8=0xfd; op0_8=0x8e; iyMem8 & A { + val:1 = iyMem8; + additionWithCarry(A, val, A); + setResultFlags(A); +} + +:SUB reg0_3 is op6_2=0x2 & bits3_3=0x2 & reg0_3 { + local A_temp = A; + + A = A - reg0_3; + subtractionFlags(A_temp, reg0_3); + setResultFlags(A); +} + +:SUB imm8 is op0_8=0xd6; imm8 { + local A_temp = A; + + A = A - imm8; + subtractionFlags(A_temp, imm8); + setResultFlags(A); +} + +:SUB (HL) is op0_8=0x96 & HL { + val:1 = 0; + MemRead(val,HL); + local A_temp = A; + + A = A - val; + subtractionFlags(A_temp, val); + setResultFlags(A); +} + +:SUB ixMem8 is op0_8=0xdd; op0_8=0x96; ixMem8 { + val:1 = ixMem8; + local A_temp = A; + + A = A - val; + subtractionFlags(A_temp, val); + setResultFlags(A); +} + +:SUB iyMem8 is op0_8=0xfd; op0_8=0x96; iyMem8 { + val:1 = iyMem8; + local A_temp = A; + + A = A - val; + subtractionFlags(A_temp, val); + setResultFlags(A); +} + +:SBC A, reg0_3 is op6_2=0x2 & bits3_3=0x3 & reg0_3 & A { + subtractionWithCarry(A, reg0_3, A); + setResultFlags(A); +} + +:SBC A, imm8 is op0_8=0xde; imm8 & A { + subtractionWithCarry(A, imm8, A); + setResultFlags(A); +} + +:SBC A, (HL) is op0_8=0x9e & HL & A { + val:1 = 0; + MemRead(val,HL); + subtractionWithCarry(A, val, A); + setResultFlags(A); +} + +:SBC A, ixMem8 is op0_8=0xdd; op0_8=0x9e; ixMem8 & A { + val:1 = ixMem8; + subtractionWithCarry(A, val, A); + setResultFlags(A); +} + +:SBC A, iyMem8 is op0_8=0xfd; op0_8=0x9e; iyMem8 & A { + val:1 = iyMem8; + subtractionWithCarry(A, val, A); + setResultFlags(A); +} + +:AND reg0_3 is op6_2=0x2 & bits3_3=0x4 & reg0_3 { + $(H_flag) = 1; + $(C_flag) = 0; + $(N_flag) = 0; + A = A & reg0_3; + setResultFlags(A); + setParity(A); +} + +:AND imm8 is op0_8=0xe6; imm8 { + $(H_flag) = 1; + $(C_flag) = 0; + $(N_flag) = 0; + A = A & imm8; + setResultFlags(A); + setParity(A); +} + +:AND (HL) is op0_8=0xa6 & HL { + $(H_flag) = 1; + $(C_flag) = 0; + $(N_flag) = 0; + tmp:1 = 0; + MemRead(tmp,HL); + A = A & tmp; + setResultFlags(A); + setParity(A); +} + +:AND ixMem8 is op0_8=0xdd; op0_8=0xa6; ixMem8 { + $(H_flag) = 1; + $(C_flag) = 0; + $(N_flag) = 0; + A = A & ixMem8; + setResultFlags(A); + setParity(A); +} + +:AND iyMem8 is op0_8=0xfd; op0_8=0xa6; iyMem8 { + $(H_flag) = 1; + $(C_flag) = 0; + $(N_flag) = 0; + A = A & iyMem8; + setResultFlags(A); + setParity(A); +} + +:OR reg0_3 is op6_2=0x2 & bits3_3=0x6 & reg0_3 { + $(H_flag) = 0; + $(C_flag) = 0; + $(N_flag) = 0; + A = A | reg0_3; + setResultFlags(A); + setParity(A); +} + +:OR imm8 is op0_8=0xf6; imm8 { + $(H_flag) = 0; + $(C_flag) = 0; + $(N_flag) = 0; + A = A | imm8; + setResultFlags(A); + setParity(A); +} + +:OR (HL) is op0_8=0xb6 & HL { + $(H_flag) = 0; + $(C_flag) = 0; + $(N_flag) = 0; + val:1 = 0; + MemRead(val,HL); + A = A | val; + setResultFlags(A); + setParity(A); +} + +:OR ixMem8 is op0_8=0xdd; op0_8=0xb6; ixMem8 { + $(H_flag) = 0; + $(C_flag) = 0; + $(N_flag) = 0; + A = A | ixMem8; + setResultFlags(A); + setParity(A); +} + +:OR iyMem8 is op0_8=0xfd; op0_8=0xb6; iyMem8 { + $(H_flag) = 0; + $(C_flag) = 0; + $(N_flag) = 0; + A = A | iyMem8; + setResultFlags(A); + setParity(A); +} + +:XOR reg0_3 is op6_2=0x2 & bits3_3=0x5 & reg0_3 { + $(H_flag) = 0; + $(C_flag) = 0; + $(N_flag) = 0; + A = A ^ reg0_3; + setResultFlags(A); + setParity(A); +} + +:XOR imm8 is op0_8=0xee; imm8 { + $(H_flag) = 0; + $(C_flag) = 0; + $(N_flag) = 0; + A = A ^ imm8; + setResultFlags(A); + setParity(A); +} + +:XOR (HL) is op0_8=0xae & HL { + $(H_flag) = 0; + $(C_flag) = 0; + $(N_flag) = 0; + val:1 = 0; + MemRead(val,HL); + A = A ^ val; + setResultFlags(A); + setParity(A); +} + +:XOR ixMem8 is op0_8=0xdd; op0_8=0xae; ixMem8 { + $(H_flag) = 0; + $(C_flag) = 0; + $(N_flag) = 0; + A = A ^ ixMem8; + setResultFlags(A); + setParity(A); +} + +:XOR iyMem8 is op0_8=0xfd; op0_8=0xae; iyMem8 { + $(H_flag) = 0; + $(C_flag) = 0; + $(N_flag) = 0; + A = A ^ iyMem8; + setResultFlags(A); + setParity(A); +} + +:CP reg0_3 is op6_2=0x2 & bits3_3=0x7 & reg0_3 { + cmp:1 = A - reg0_3; + subtractionFlags(A, reg0_3); + setResultFlags(cmp); +} + +:CP imm8 is op0_8=0xfe; imm8 { + cmp:1 = A - imm8; + subtractionFlags(A, imm8); + setResultFlags(cmp); +} + +:CP (HL) is op0_8=0xbe & HL { + val:1 = 0; + MemRead(val,HL); + + cmp:1 = A - val; + subtractionFlags(A, val); + setResultFlags(cmp); +} + +:CP ixMem8 is op0_8=0xdd; op0_8=0xbe; ixMem8 { + val:1 = ixMem8; + + cmp:1 = A - val; + subtractionFlags(A, val); + setResultFlags(cmp); +} + +:CP iyMem8 is op0_8=0xfd; op0_8=0xbe; iyMem8 { + val:1 = iyMem8; + + cmp:1 = A - val; + subtractionFlags(A, val); + setResultFlags(cmp); +} + +:INC reg3_3 is op6_2=0x0 & reg3_3 & bits0_3=0x4 { + local r_temp = reg3_3; + + reg3_3 = reg3_3 + 1; + setResultFlags(reg3_3); + additionFlags(r_temp, 1); +} + +:INC (HL) is op0_8=0x34 & HL { + val:1 = 0; + MemRead(val,HL); + val_temp:1 = val; + + val = val + 1; + MemStore(HL,val); + setResultFlags(val); + additionFlags(val_temp, 1); +} + +:INC ixMem8 is op0_8=0xdd; op0_8=0x34; ixMem8 { + val:1 = ixMem8; + val_temp:1 = val; + + val = val + 1; + ixMem8 = val; + setResultFlags(val); + additionFlags(val_temp, 1); +} + +:INC iyMem8 is op0_8=0xfd; op0_8=0x34; iyMem8 { + val:1 = iyMem8; + val_temp:1 = val; + + val = val + 1; + iyMem8 = val; + setResultFlags(val); + additionFlags(val_temp, 1); +} + +:DEC reg3_3 is op6_2=0x0 & reg3_3 & bits0_3=0x5 { + local r_temp = reg3_3; + + reg3_3 = reg3_3 - 1; + subtractionFlagsNoC(r_temp, 1); + setResultFlags(reg3_3); +} + +:DEC (HL) is op0_8=0x35 & HL { + val:1 = 0; + MemRead(val,HL); + val_temp:1 = val; + + val = val - 1; + MemStore(HL,val); + subtractionFlagsNoC(val_temp, 1); + setResultFlags(val); +} + +:DEC ixMem8 is op0_8=0xdd; op0_8=0x35; ixMem8 { + val:1 = ixMem8; + val_temp:1 = val; + + val = val - 1; + ixMem8 = val; + subtractionFlagsNoC(val_temp, 1); + setResultFlags(val); +} + +:DEC iyMem8 is op0_8=0xfd; op0_8=0x35; iyMem8 { + val:1 = iyMem8; + val_temp:1 = val; + + val = val - 1; + iyMem8 = val; + subtractionFlagsNoC(val_temp, 1); + setResultFlags(val); +} + +:DAA is op0_8=0x27 { +if (DECOMPILE_MODE) goto ; + + HN:1 = A >> 4; # high nibble + LN:1 = A & 0xF; # low nibbble + # + # If (C and H are both 0, and both nibbles are in range[0,9] no + # adjustment is needed. + # + if (($(C_flag) == 0) & ($(H_flag) == 0) & (HN <= 0x9) & (LN <= 0x9)) goto ; + + if ($(N_flag) == 1) goto ; + + #, in effect + if ($(C_flag) == 0 & $(H_flag) == 0 & HN <= 0x8 & LN >= 0xA & LN <= 0xF) goto ; + if ($(C_flag) == 0 & $(H_flag) == 1 & HN <= 0x9 & LN <= 0x3) goto ; + if ($(C_flag) == 0 & $(H_flag) == 0 & HN >= 0xA & HN <= 0xF & LN <= 0x9) goto ; + if ($(C_flag) == 0 & $(H_flag) == 0 & HN >= 0x9 & HN <= 0xF & LN >= 0xA & LN <= 0xF) goto ; + if ($(C_flag) == 0 & $(H_flag) == 1 & HN >= 0xA & HN <= 0xF & LN <= 0x3) goto ; + if ($(C_flag) == 1 & $(H_flag) == 0 & HN <= 0x2 & LN <= 0x9) goto ; + if ($(C_flag) == 1 & $(H_flag) == 0 & HN <= 0x2 & LN >= 0xA & LN <= 0xF) goto ; + if ($(C_flag) == 1 & $(H_flag) == 1 & HN <= 0x3 & LN <= 0x3) goto ; + goto ; + + # Cases for addition + # + # Isn't used + + A = A + 0x06; + goto ; + + A = A + 0x06; + goto ; + + A = A + 0x60; + $(C_flag) = 1; + goto ; + + A = A + 0x66; + $(C_flag) = 1; + goto ; + + A = A + 0x66; + $(C_flag) = 1; + goto ; + + A = A + 0x60; + goto ; + + A = A + 0x66; + goto ; + + A = A + 0x66; + goto ; + + + # Cases for subtraction + #if ($(C_flag) == 0 & $(H_flag) == 0 & HN >= 0x0 & HN <= 0x9 & LN >= 0x0 & LN <= 0x9) goto ; + if ($(C_flag) == 0 & $(H_flag) == 1 & HN <= 0x8 & LN >= 0x6 & LN <= 0xF) goto ; + if ($(C_flag) == 1 & $(H_flag) == 0 & HN >= 0x7 & HN <= 0xF & LN <= 0x9) goto ; + if ($(C_flag) == 1 & $(H_flag) == 1 & HN >= 0x6 & HN <= 0xF & LN >= 0x6 & LN <= 0xF) goto ; + goto ; + + # + # Isn't used + + A = A + 0xFA; + goto ; + + A = A + 0xA0; + goto ; + + A = A + 0x9A; + + + + setResultFlags(A); + setParity(A); + + goto ; + + + + A_temp:1 = A; + + A = BCDadjust(A_temp, $(C_flag), $(H_flag)); + $(C_flag) = BCDadjustCarry(A_temp, $(C_flag), $(H_flag)); + + setResultFlags(A); + $(PV_flag) = hasEvenParity(A); + + +} + +:CPL is op0_8=0x2f { + A = ~A; + $(H_flag) = 1; + $(N_flag) = 1; +} + +:NEG is op0_8=0xed; op0_8=0x44 { + A_temp:1 = A; + + A = -A; + subtractionFlags(0, A_temp); + setResultFlags(A); +} + +:CCF is op0_8=0x3f { + $(C_flag) = !$(C_flag); + $(N_flag) = 0; +} + +:SCF is op0_8=0x37 { + $(C_flag) = 1; + $(H_flag) = 0; + $(N_flag) = 0; +} + +:NOP is op0_8=0x0 { +} + +:HALT is op0_8=0x76 { + halt(); +} + +:DI is op0_8=0xf3 { +# IFF1 = 0; +# IFF2 = 0; + disableMaskableInterrupts(); +} + +:EI is op0_8=0xfb { +# IFF1 = 1; +# IFF2 = 1; + enableMaskableInterrupts(); +} + +:IM 0 is op0_8=0xed; op0_8=0x46 { + setInterruptMode(0:1); +} + +:IM 1 is op0_8=0xed; op0_8=0x56 { + setInterruptMode(1:1); +} + +:IM 2 is op0_8=0xed; op0_8=0x5e { + setInterruptMode(2:1); +} + +:ADD HL,sRegPair4_2 is op6_2=0x0 & sRegPair4_2 & bits0_4=0x9 & HL { + local HL_temp = HL; + local Reg_temp = sRegPair4_2; + + HL = HL + sRegPair4_2; + additionFlagsNoPV(HL_temp, Reg_temp); +} + +:ADC HL,sRegPair4_2 is op0_8=0xed & HL; op6_2=0x1 & sRegPair4_2 & bits0_4=0xa { + local HL_temp = HL; + local Reg_temp = sRegPair4_2; + + HL = HL + sRegPair4_2 + zext($(C_flag)); + setResultFlags(HL); + additionFlagsNoPV(HL_temp, Reg_temp); +} + +:SBC HL,sRegPair4_2 is op0_8=0xed & HL; op6_2=0x1 & sRegPair4_2 & bits0_4=0x2 { + subtractionWithCarry(HL, sRegPair4_2, HL); + setResultFlags(HL); +} + +:ADD IX,pRegPair4_2 is op0_8=0xdd & IX; op6_2=0x0 & pRegPair4_2 & bits0_4=0x9 { + local IX_temp = IX; + local Reg_temp = pRegPair4_2; + + IX = IX + pRegPair4_2; + additionFlagsNoPV(IX_temp, Reg_temp); +} + +:ADD IY,pRegPair4_2 is op0_8=0xfd & IY; op6_2=0x0 & pRegPair4_2 & bits0_4=0x9 { + local IY_temp = IY; + local Reg_temp = pRegPair4_2; + + IY = IY + pRegPair4_2; + additionFlagsNoPV(IY_temp, Reg_temp); +} + +:INC sRegPair4_2 is op6_2=0x0 & sRegPair4_2 & bits0_4=0x3 { + sRegPair4_2 = sRegPair4_2 + 1; +} + +:INC IX is op0_8=0xdd & IX; op0_8=0x23 { + IX = IX + 1; +} + +:INC IY is op0_8=0xfd & IY; op0_8=0x23 { + IY = IY + 1; +} + +:DEC sRegPair4_2 is op6_2=0x0 & sRegPair4_2 & bits0_4=0xb { + sRegPair4_2 = sRegPair4_2 - 1; +} + +:DEC IX is op0_8=0xdd & IX; op0_8=0x2b { + IX = IX - 1; +} + +:DEC IY is op0_8=0xfd & IY; op0_8=0x2b { + IY = IY - 1; +} + +:RLCA is op0_8=0x07 { + $(C_flag) = (A >> 7); + A = (A << 1) | $(C_flag); + $(H_flag) = 0; + $(N_flag) = 0; +} + +:RLA is op0_8=0x17 { + nextC:1 = (A >> 7); + A = (A << 1) | $(C_flag); + $(C_flag) = nextC; + $(H_flag) = 0; + $(N_flag) = 0; +} + +:RRCA is op0_8=0x0f { + $(C_flag) = (A & 1); + A = (A >> 1) | ($(C_flag) << 7); + $(H_flag) = 0; + $(N_flag) = 0; +} + +:RRA is op0_8=0x1f { + nextC:1 = (A & 1); + A = (A >> 1) | ($(C_flag) << 7); + $(C_flag) = nextC; + $(H_flag) = 0; + $(N_flag) = 0; +} + +:RLC reg0_3 is op0_8=0x0cb; op6_2=0x0 & bits3_3=0x0 & reg0_3 { + $(C_flag) = (reg0_3 >> 7); + reg0_3 = (reg0_3 << 1) | $(C_flag); + setResultFlags(reg0_3); + $(H_flag) = 0; + setParity(reg0_3); + $(N_flag) = 0; +} + +:RLC (HL) is op0_8=0x0cb & HL; op0_8=0x06 { + val:1 = 0; + MemRead(val,HL); + $(C_flag) = (val >> 7); + val = (val << 1) | $(C_flag); + setResultFlags(val); + MemStore(HL,val); + $(H_flag) = 0; + setParity(val); + $(N_flag) = 0; +} + +:RLC ixMem8 is op0_8=0x0dd; op0_8=0xcb; ixMem8; op0_8=0x06 { + val:1 = ixMem8; + $(C_flag) = (val >> 7); + val = (val << 1) | $(C_flag); + setResultFlags(val); + ixMem8 = val; + $(H_flag) = 0; + $(N_flag) = 0; +} + +:RLC iyMem8 is op0_8=0x0fd; op0_8=0xcb; iyMem8; op0_8=0x06 { + val:1 = iyMem8; + $(C_flag) = (val >> 7); + val = (val << 1) | $(C_flag); + setResultFlags(val); + iyMem8 = val; + $(H_flag) = 0; + setParity(val); + $(N_flag) = 0; +} + +:RL reg0_3 is op0_8=0x0cb; op6_2=0x0 & bits3_3=0x2 & reg0_3 { + nextC:1 = (reg0_3 >> 7); + reg0_3 = (reg0_3 << 1) | $(C_flag); + $(C_flag) = nextC; + setResultFlags(reg0_3); + $(H_flag) = 0; + setParity(reg0_3); + $(N_flag) = 0; +} + +:RL (HL) is op0_8=0x0cb & HL; op0_8=0x16 { + val:1 = 0; + MemRead(val,HL); + nextC:1 = (val >> 7); + val = (val << 1) | $(C_flag); + $(C_flag) = nextC; + setResultFlags(val); + MemStore(HL,val); + $(H_flag) = 0; + setParity(val); + $(N_flag) = 0; +} + +:RL ixMem8 is op0_8=0x0dd; op0_8=0xcb; ixMem8; op0_8=0x16 { + val:1 = ixMem8; + nextC:1 = (val >> 7); + val = (val << 1) | $(C_flag); + $(C_flag) = nextC; + setResultFlags(val); + ixMem8 = val; + $(H_flag) = 0; + setParity(val); + $(N_flag) = 0; +} + +:RL iyMem8 is op0_8=0x0fd; op0_8=0xcb; iyMem8; op0_8=0x16 { + val:1 = iyMem8; + nextC:1 = (val >> 7); + val = (val << 1) | $(C_flag); + $(C_flag) = nextC; + setResultFlags(val); + iyMem8 = val; + $(H_flag) = 0; + setParity(val); + $(N_flag) = 0; +} + +:RRC reg0_3 is op0_8=0x0cb; op6_2=0x0 & bits3_3=0x1 & reg0_3 { + $(C_flag) = (reg0_3 & 1); + reg0_3 = (reg0_3 >> 1) | ($(C_flag) << 7); + setResultFlags(reg0_3); + $(H_flag) = 0; + setParity(reg0_3); + $(N_flag) = 0; +} + +:RRC (HL) is op0_8=0x0cb & HL; op0_8=0x0e { + val:1 = 0; + MemRead(val,HL); + $(C_flag) = (val & 1); + val = (val >> 1) | ($(C_flag) << 7); + setResultFlags(val); + MemStore(HL,val); + $(H_flag) = 0; + setParity(val); + $(N_flag) = 0; +} + +:RRC ixMem8 is op0_8=0x0dd; op0_8=0xcb; ixMem8; op0_8=0x0e { + val:1 = ixMem8; + $(C_flag) = (val & 1); + val = (val >> 1) | ($(C_flag) << 7); + setResultFlags(val); + ixMem8 = val; + $(H_flag) = 0; + setParity(val); + $(N_flag) = 0; +} + +:RRC iyMem8 is op0_8=0x0fd; op0_8=0xcb; iyMem8; op0_8=0x0e { + val:1 = iyMem8; + $(C_flag) = (val & 1); + val = (val >> 1) | ($(C_flag) << 7); + setResultFlags(val); + iyMem8 = val; + $(H_flag) = 0; + setParity(val); + $(N_flag) = 0; +} + +:RR reg0_3 is op0_8=0x0cb; op6_2=0x0 & bits3_3=0x3 & reg0_3 { + nextC:1 = (reg0_3 & 1); + reg0_3 = (reg0_3 >> 1) | ($(C_flag) << 7); + $(C_flag) = nextC; + setResultFlags(reg0_3); + $(H_flag) = 0; + setParity(reg0_3); + $(N_flag) = 0; +} + +:RR (HL) is op0_8=0x0cb & HL; op0_8=0x1e { + val:1 = 0; + MemRead(val,HL); + nextC:1 = (val & 1); + val = (val >> 1) | ($(C_flag) << 7); + $(C_flag) = nextC; + setResultFlags(val); + MemStore(HL,val); + $(H_flag) = 0; + setParity(val); + $(N_flag) = 0; +} + +:RR ixMem8 is op0_8=0x0dd; op0_8=0xcb; ixMem8; op0_8=0x1e { + val:1 = ixMem8; + nextC:1 = (val & 1); + val = (val >> 1) | ($(C_flag) << 7); + $(C_flag) = nextC; + setResultFlags(val); + ixMem8 = val; + $(H_flag) = 0; + setParity(val); + $(N_flag) = 0; +} + +:RR iyMem8 is op0_8=0x0fd; op0_8=0xcb; iyMem8; op0_8=0x1e { + val:1 = iyMem8; + nextC:1 = (val & 1); + val = (val >> 1) | ($(C_flag) << 7); + $(C_flag) = nextC; + setResultFlags(val); + iyMem8 = val; + $(H_flag) = 0; + setParity(val); + $(N_flag) = 0; +} + +:SLA reg0_3 is op0_8=0x0cb; op6_2=0x0 & bits3_3=0x4 & reg0_3 { + $(C_flag) = (reg0_3 >> 7); + reg0_3 = reg0_3 << 1; + setResultFlags(reg0_3); + $(H_flag) = 0; + setParity(reg0_3); + $(N_flag) = 0; +} + +:SLA (HL) is op0_8=0x0cb & HL; op0_8=0x26 { + val:1 = 0; + MemRead(val,HL); + $(C_flag) = (val >> 7); + val = val << 1; + setResultFlags(val); + MemStore(HL,val); + $(H_flag) = 0; + setParity(val); + $(N_flag) = 0; +} + +:SLA ixMem8 is op0_8=0x0dd; op0_8=0xcb; ixMem8; op0_8=0x26 { + val:1 = ixMem8; + $(C_flag) = (val >> 7); + val = val << 1; + setResultFlags(val); + ixMem8 = val; + $(H_flag) = 0; + setParity(val); + $(N_flag) = 0; +} + +:SLA iyMem8 is op0_8=0x0fd; op0_8=0xcb; iyMem8; op0_8=0x26 { + val:1 = iyMem8; + $(C_flag) = (val >> 7); + val = val << 1; + setResultFlags(val); + iyMem8 = val; + $(H_flag) = 0; + setParity(val); + $(N_flag) = 0; +} + +:SRA reg0_3 is op0_8=0x0cb; op6_2=0x0 & bits3_3=0x5 & reg0_3 { + $(C_flag) = (reg0_3 & 1); + reg0_3 = reg0_3 s>> 1; + setResultFlags(reg0_3); + $(H_flag) = 0; + setParity(reg0_3); + $(N_flag) = 0; +} + +:SRA (HL) is op0_8=0x0cb & HL; op0_8=0x2e { + val:1 = 0; + MemRead(val,HL); + $(C_flag) = (val & 1); + val = val s>> 1; + setResultFlags(val); + MemStore(HL,val); + $(H_flag) = 0; + setParity(val); + $(N_flag) = 0; +} + +:SRA ixMem8 is op0_8=0x0dd; op0_8=0xcb; ixMem8; op0_8=0x2e { + val:1 = ixMem8; + $(C_flag) = (val & 1); + val = val s>> 1; + setResultFlags(val); + ixMem8 = val; + $(H_flag) = 0; + setParity(val); + $(N_flag) = 0; +} + +:SRA iyMem8 is op0_8=0x0fd; op0_8=0xcb; iyMem8; op0_8=0x2e { + val:1 = iyMem8; + $(C_flag) = (val & 1); + val = val s>> 1; + setResultFlags(val); + iyMem8 = val; + $(H_flag) = 0; + setParity(val); + $(N_flag) = 0; +} + +:SRL reg0_3 is op0_8=0x0cb; op6_2=0x0 & bits3_3=0x7 & reg0_3 { + $(C_flag) = (reg0_3 & 1); + reg0_3 = reg0_3 >> 1; + setResultFlags(reg0_3); + $(H_flag) = 0; + setParity(reg0_3); + $(N_flag) = 0; +} + +:SRL (HL) is op0_8=0x0cb & HL; op0_8=0x3e { + val:1 = 0; + MemRead(val,HL); + $(C_flag) = (val & 1); + val = val >> 1; + setResultFlags(val); + MemStore(HL,val); + $(H_flag) = 0; + setParity(val); + $(N_flag) = 0; +} + +:SRL ixMem8 is op0_8=0x0dd; op0_8=0xcb; ixMem8; op0_8=0x3e { + val:1 = ixMem8; + $(C_flag) = (val & 1); + val = val >> 1; + setResultFlags(val); + ixMem8 = val; + $(H_flag) = 0; + setParity(val); + $(N_flag) = 0; +} + +:SRL iyMem8 is op0_8=0x0fd; op0_8=0xcb; iyMem8; op0_8=0x3e { + val:1 = iyMem8; + $(C_flag) = (val & 1); + val = val >> 1; + setResultFlags(val); + iyMem8 = val; + $(H_flag) = 0; + setParity(val); + $(N_flag) = 0; +} + +:RLD is op0_8=0xed; op0_8=0x6f { + val:1 = 0; + MemRead(val,HL); + nibA:1 = A & 0x0f; + nibM:1 = val >> 4; + val = (val << 4) | nibA; + A = (A & 0xf0) | nibM; + MemStore(HL,val); +@if defined(Z180) + setResultFlags(val); +@else + setResultFlags(A); +@endif + $(H_flag) = 0; + setParity(A); + $(N_flag) = 0; +} + +:RRD is op0_8=0xed; op0_8=0x67 { + val:1 = 0; + MemRead(val,HL); + nibA:1 = A & 0x0f; + nibM:1 = val & 0x0f; + val = (val >> 4) | (nibA << 4); + A = (A & 0xf0) | nibM; + MemStore(HL,val); +@if defined(Z180) + setResultFlags(val); +@else + setResultFlags(A); +@endif + $(H_flag) = 0; + setParity(A); + $(N_flag) = 0; +} + +:BIT bits3_3,reg0_3 is op0_8=0xcb; op6_2=0x1 & bits3_3 & reg0_3 { + mask:1 = (1 << bits3_3); + $(Z_flag) = ((reg0_3 & mask) == 0); + $(H_flag) = 1; + $(N_flag) = 0; +} + +:BIT bits3_3,(HL) is op0_8=0xcb & HL; op6_2=0x1 & bits3_3 & bits0_3=0x6 { + mask:1 = (1 << bits3_3); + val:1 = 0; + MemRead(val,HL); + $(Z_flag) = ((val & mask) == 0); + $(H_flag) = 1; + $(N_flag) = 0; +} + +:BIT bits3_3,ixMem8 is op0_8=0xdd; op0_8=0xcb; ixMem8; op6_2=0x1 & bits3_3 & bits0_3=0x6 { + mask:1 = (1 << bits3_3); + val:1 = ixMem8; + $(Z_flag) = ((val & mask) == 0); + $(H_flag) = 1; + $(N_flag) = 0; +} + +:BIT bits3_3,iyMem8 is op0_8=0xfd; op0_8=0xcb; iyMem8; op6_2=0x1 & bits3_3 & bits0_3=0x6 { + mask:1 = (1 << bits3_3); + val:1 = iyMem8; + $(Z_flag) = ((val & mask) == 0); + $(H_flag) = 1; + $(N_flag) = 0; +} + +:SET bits3_3,reg0_3 is op0_8=0xcb; op6_2=0x3 & bits3_3 & reg0_3 { + mask:1 = (1 << bits3_3); + reg0_3 = reg0_3 | mask; +} + +:SET bits3_3,(HL) is op0_8=0xcb & HL; op6_2=0x3 & bits3_3 & bits0_3=0x6 { + mask:1 = (1 << bits3_3); + val:1 = 0; + MemRead(val,HL); + val = val | mask; + MemStore(HL,val); +} + +:SET bits3_3,ixMem8 is op0_8=0xdd; op0_8=0xcb; ixMem8; op6_2=0x3 & bits3_3 & bits0_3=0x6 { + mask:1 = (1 << bits3_3); + val:1 = ixMem8; + ixMem8 = val | mask; +} + +:SET bits3_3,iyMem8 is op0_8=0xfd; op0_8=0xcb; iyMem8; op6_2=0x3 & bits3_3 & bits0_3=0x6 { + mask:1 = (1 << bits3_3); + val:1 = iyMem8; + iyMem8 = val | mask; +} + +:RES bits3_3,reg0_3 is op0_8=0xcb; op6_2=0x2 & bits3_3 & reg0_3 { + mask:1 = ~(1 << bits3_3); + reg0_3 = reg0_3 & mask; +} + +:RES bits3_3,(HL) is op0_8=0xcb & HL; op6_2=0x2 & bits3_3 & bits0_3=0x6 { + mask:1 = ~(1 << bits3_3); + val:1 = 0; + MemRead(val,HL); + val = val & mask; + MemStore(HL,val); +} + +:RES bits3_3,ixMem8 is op0_8=0xdd; op0_8=0xcb; ixMem8; op6_2=0x2 & bits3_3 & bits0_3=0x6 { + mask:1 = ~(1 << bits3_3); + val:1 = ixMem8; + ixMem8 = val & mask; +} + +:RES bits3_3,iyMem8 is op0_8=0xfd; op0_8=0xcb; iyMem8; op6_2=0x2 & bits3_3 & bits0_3=0x6 { + mask:1 = ~(1 << bits3_3); + val:1 = iyMem8; + iyMem8 = val & mask; +} + +:JP Addr16 is op0_8=0xc3; Addr16 { + goto Addr16; +} + +:JP cc,Addr16 is op6_2=0x3 & cc & bits0_3=0x2; Addr16 { + if (cc) goto Addr16; +} + +:JR RelAddr8 is op0_8=0x18; RelAddr8 { + goto RelAddr8; +} + +:JR cc2,RelAddr8 is op6_2=0x0 & cc2 & bits0_3=0x0; RelAddr8 { + if (cc2) goto RelAddr8; +} + +:JP (HL) is op0_8=0xe9 & HL { + off:2 = (zext(H) << 8) | zext(L); + + JumpToLoc(off); + +} + +:JP (IX) is op0_8=0xdd & IX; op0_8=0xe9 { + + JumpToLoc(IX); +} + +:JP (IY) is op0_8=0xfd & IY; op0_8=0xe9 { + + JumpToLoc(IY); +} + +:DJNZ RelAddr8 is op0_8=0x10; RelAddr8 { + B = B - 1; + if (B != 0) goto RelAddr8; +} + +:CALL Addr16 is op0_8=0xcd; Addr16 { + push16(&:2 inst_next); + call Addr16; +} + +:CALL cc,Addr16 is op6_2=0x3 & cc & bits0_3=0x4; Addr16 { + if (!cc) goto inst_next; + push16(&:2 inst_next); + call Addr16; +} + +:RET is op0_8=0xc9 { + pop16(PC); + ptr:$(PTRSIZE) = PC; + return [ptr]; +} + +:RET cc is op6_2=0x3 & cc & bits0_3=0x0 { + if (!cc) goto inst_next; + pop16(PC); + ptr:$(PTRSIZE) = PC; + return [ptr]; +} + +:RETI is op0_8=0xed; op0_8=0x4d { + pop16(PC); + ptr:$(PTRSIZE) = PC; + return [ptr]; +} + +:RETN is op0_8=0xed; op0_8=0x45 { + # IFF1 = IFF2; + pop16(PC); + ptr:$(PTRSIZE) = PC; + return [ptr]; +} + +:RST RstAddr is op6_2=0x3 & RstAddr & bits0_3=0x7 { + push16(&:2 inst_next); + call RstAddr; +} + +:IN A,IOAddr8a is op0_8=0xdb & A; IOAddr8a { + ioRead(IOAddr8a, A); +} + +:IN reg3_3,IOAddrC is op0_8=0xed & IOAddrC; op6_2=0x1 & reg3_3 & bits0_3=0x0 { + ioRead(IOAddrC, reg3_3); + setResultFlags(reg3_3); + $(H_flag) = 0; + setParity(reg3_3); + $(N_flag) = 0; +} + +:INI is op0_8=0xed & IOAddrC; op0_8=0xa2 { + val:1 = 0; + ioRead(IOAddrC, val); + MemStore(HL,val); + B = B - 1; + HL = HL + 1; + $(Z_flag) = (B == 0); + $(N_flag) = (B s< 0); +} + +:INIR is op0_8=0xed & IOAddrC; op0_8=0xb2 { + val:1 = 0; + ioRead(IOAddrC, val); + MemStore(HL,val); + B = B - 1; + HL = HL + 1; + if (B != 0) goto inst_start; + $(Z_flag) = 1; + $(N_flag) = 1; +} + +:IND is op0_8=0xed & IOAddrC; op0_8=0xaa { + val:1 = 0; + ioRead(IOAddrC, val); + MemStore(HL,val); + B = B - 1; + HL = HL - 1; + $(Z_flag) = (B == 0); + $(N_flag) = (B s< 0); +} + +:INDR is op0_8=0xed & IOAddrC; op0_8=0xba { + val:1 = 0; + ioRead(IOAddrC, val); + MemStore(HL,val); + B = B - 1; + HL = HL - 1; + if (B != 0) goto inst_start; + $(Z_flag) = 1; + $(N_flag) = 1; +} + +:OUT IOAddr8a,A is op0_8=0xd3 & A; IOAddr8a { + ioWrite(IOAddr8a, A); +} + +:OUT IOAddrC,reg3_3 is op0_8=0xed & IOAddrC; op6_2=0x1 & reg3_3 & bits0_3=0x1 { + ioWrite(IOAddrC, reg3_3); +} + +:OUTI is op0_8=0xed & IOAddrC; op0_8=0xa3 { + val:1 = 0; + MemRead(val,HL); + ioWrite(IOAddrC, val); + B = B - 1; + HL = HL + 1; + $(Z_flag) = (B == 0); + $(N_flag) = (B s< 0); +} + +:OTIR is op0_8=0xed & IOAddrC; op0_8=0xb3 { + B = B - 1; + val:1 = 0; + MemRead(val,HL); + ioWrite(IOAddrC, val); + HL = HL + 1; + if (B != 0) goto inst_start; + $(Z_flag) = 1; + $(N_flag) = 1; +} + +:OUTD is op0_8=0xed & IOAddrC; op0_8=0xab { + B = B - 1; + val:1 = 0; + MemRead(val,HL); + ioWrite(IOAddrC, val); + HL = HL - 1; + $(Z_flag) = (B == 0); + $(N_flag) = (B s< 0); +} + +:OTDR is op0_8=0xed & IOAddrC; op0_8=0xbb { + B = B - 1; + val:1 = 0; + MemRead(val,HL); + ioWrite(IOAddrC, val); + HL = HL - 1; + if (B != 0) goto inst_start; + $(Z_flag) = 1; + $(N_flag) = 1; +} +@if defined(Z180) + +:MLT qRegPair4_2 is op0_8=0xed; op6_2=0x1 & qRegPair4_2 & bits0_4=0xc { + hi:2 = qRegPair4_2 >> 8; + lo:2 = qRegPair4_2 & 0xff; + qRegPair4_2 = hi * lo; +} + +:TST reg3_3 is op0_8=0xed; op6_2=0x0 & reg3_3 & bits0_3=0x4 { + r:1 = reg3_3 & A; + setResultFlags(r); + $(H_flag)=1; + setParity(r); + $(N_flag)=0; + $(C_flag)=0; +} + +:TST hlMem8 is op0_8=0xed; op0_8=0x34 & hlMem8 { + val:1 = 0; + MemRead(val,HL); + r:1 = val & A; + setResultFlags(r); + $(H_flag)=1; + setParity(r); + $(N_flag)=0; + $(C_flag)=0; +} + +:TST imm8 is op0_8=0xed; op0_8=0x64; imm8 { + r:1 = imm8 & A; + setResultFlags(r); + $(H_flag)=1; + setParity(r); + $(N_flag)=0; + $(C_flag)=0; +} + +:IN0 Flag,IOAddr8 is op0_8=0xed; op6_2=0x0 & bits3_3=0x6 & Flag & bits0_3=0x0; IOAddr8 { + r:1 = 0; + ioRead(IOAddr8,r); # read input location + setResultFlags(r); + $(H_flag)=0; + setParity(r); + $(N_flag)=0; +} + +:IN0 reg3_3,IOAddr8 is op0_8=0xed; op6_2=0x0 & reg3_3 & bits0_3=0x0; IOAddr8 { + ioRead(IOAddr8,reg3_3); # read input location + setResultFlags(reg3_3); + $(H_flag)=0; + setParity(reg3_3); + $(N_flag)=0; +} + +:OUT0 IOAddr8,reg3_3 is op0_8=0xed; op6_2=0x0 & reg3_3 & bits0_3=0x1; IOAddr8 { + ioWrite(IOAddr8, reg3_3); +} + +:OTDM is op0_8=0xed; op0_8=0x8b & hlMem8 & IOAddrC { + r:1 = hlMem8; + ioWrite(IOAddrC, r); + HL = HL - 1; + C = C - 1; + setSubtractFlags(B,1); # ?? sets $(C_flag) based upon B-1 ?? + B = B - 1; + setResultFlags(B); + # P_flag = parity(r); + $(PV_flag) = (r s< 0); +} + +:OTDMR is op0_8=0xed; op0_8=0x9b & hlMem8 & IOAddrC { + r:1 = hlMem8; + ioWrite(IOAddrC, r); + HL = HL - 1; + C = C - 1; + B = B - 1; + if (B != 0) goto inst_start; + $(S_flag)=0; + $(Z_flag)=1; + $(H_flag) = 0; +# $(PV_flag)=1; + $(PV_flag) = (r s< 0); # based upon last output byte + $(C_flag)=0; +} + +:TSTIO IOAddr8 is op0_8=0xed; op0_8=0x74; IOAddr8 { + v:1 = 0; + ioRead(IOAddr8,v); + r:1 = A & v; + setResultFlags(r); + $(H_flag) = 1; + # P_flag = parity(v); + $(N_flag) = 0; + $(C_flag)=0; +} + +:OTIM is op0_8=0xed; op0_8=0x83 & hlMem8 & IOAddrC { + r:1 = hlMem8; + ioWrite(IOAddrC, r); + HL = HL + 1; + C = C + 1; + setSubtractFlags(B,1); # ?? sets $(C_flag) based upon B-1 ?? + B = B - 1; + setResultFlags(B); + $(H_flag) = 1; + # P_flag = parity(r); + $(PV_flag) = (r s< 0); + $(N_flag) = 0; + $(C_flag)=0; +} + +:OTIMR is op0_8=0xed; op0_8=0x93 & hlMem8 & IOAddrC { + r:1 = hlMem8; + ioWrite(IOAddrC, r); + HL = HL - 1; + C = C + 1; + B = B - 1; + if (B != 0) goto inst_start; + $(S_flag)=0; + $(Z_flag)=1; + $(H_flag) = 0; +# $(PV_flag)=1; + $(PV_flag) = (r s< 0); # based upon last output byte + $(C_flag)=0; +} + +:SLP is op0_8=0xed; op0_8=0x76 { + sleep(); +} + +@endif diff --git a/python/icicle/Ghidra/Processors/Z80/data/languages/z8401x.pspec b/python/icicle/Ghidra/Processors/Z80/data/languages/z8401x.pspec new file mode 100644 index 0000000..fc26e6f --- /dev/null +++ b/python/icicle/Ghidra/Processors/Z80/data/languages/z8401x.pspec @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/tricore/data/languages/tc172x.pspec b/python/icicle/Ghidra/Processors/tricore/data/languages/tc172x.pspec new file mode 100644 index 0000000..57dc6ae --- /dev/null +++ b/python/icicle/Ghidra/Processors/tricore/data/languages/tc172x.pspec @@ -0,0 +1,2346 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/tricore/data/languages/tc176x.pspec b/python/icicle/Ghidra/Processors/tricore/data/languages/tc176x.pspec new file mode 100644 index 0000000..891426f --- /dev/null +++ b/python/icicle/Ghidra/Processors/tricore/data/languages/tc176x.pspec @@ -0,0 +1,1527 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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b/python/icicle/Ghidra/Processors/tricore/data/languages/tricore.cspec new file mode 100644 index 0000000..82cccee --- /dev/null +++ b/python/icicle/Ghidra/Processors/tricore/data/languages/tricore.cspec @@ -0,0 +1,184 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/tricore/data/languages/tricore.dwarf b/python/icicle/Ghidra/Processors/tricore/data/languages/tricore.dwarf new file mode 100644 index 0000000..bcec948 --- /dev/null +++ b/python/icicle/Ghidra/Processors/tricore/data/languages/tricore.dwarf @@ -0,0 +1,27 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/python/icicle/Ghidra/Processors/tricore/data/languages/tricore.ldefs b/python/icicle/Ghidra/Processors/tricore/data/languages/tricore.ldefs new file mode 100644 index 0000000..1c9a575 --- /dev/null +++ b/python/icicle/Ghidra/Processors/tricore/data/languages/tricore.ldefs @@ -0,0 +1,57 @@ + + + + + + Siemens Tricore Embedded Processor + + + + + Siemens Tricore Embedded Processor TC29x + + + + + Siemens Tricore Embedded Processor TC1724/TC1728 + + + + + Siemens Tricore Embedded Processor TC1762/TC1766 + + + + diff --git a/python/icicle/Ghidra/Processors/tricore/data/languages/tricore.opinion b/python/icicle/Ghidra/Processors/tricore/data/languages/tricore.opinion new file mode 100644 index 0000000..18bb203 --- /dev/null +++ b/python/icicle/Ghidra/Processors/tricore/data/languages/tricore.opinion @@ -0,0 +1,5 @@ + + + + + diff --git a/python/icicle/Ghidra/Processors/tricore/data/languages/tricore.pcp.sinc b/python/icicle/Ghidra/Processors/tricore/data/languages/tricore.pcp.sinc new file mode 100644 index 0000000..cbaa97c --- /dev/null +++ b/python/icicle/Ghidra/Processors/tricore/data/languages/tricore.pcp.sinc @@ -0,0 +1,861 @@ + + +# R0 - Accumulator +# R1 - +# R2 - Return Address +# R3 - +# R4 - SRC +# R5 - DST +# R6 - CPPN/SRPN/TOS/CNT1 +# R7 - DPTR/Flags +define register offset=0xf0043F00 size=4 [ R0 R1 R2 R3 R4 R5 R6 R7 ]; +@define CPPN "R6[24,8]" +@define SRPN "R6[16,8]" +@define TOS "R6[14,2]" +@define CNT1 "R6[0,12]" + +@define DPTR "R7[8,8]" +@define CEN "R7[6,1]" +@define IEN "R7[5,1]" +@define CNZ "R7[4,1]" +@define V "R7[3,1]" +@define C "R7[2,1]" +@define N "R7[1,1]" +@define Z "R7[0,1]" + +define token pcpinstr (16) + pcp_op0000=(0,0) + pcp_op0001=(0,1) + pcp_op0002=(0,2) + ccAB=(0,3) + ccA=(0,2) + pcp_op0004=(0,4) + pcp_op0005=(0,5) + pcp_op0009=(0,9) + pcp_op0010=(0,10) + pcp_op0101=(1,1) + pcp_op0202=(2,2) + pcp_op0203=(2,3) + pcp_op0204=(2,4) + pcp_op0303=(3,3) + R0305=(3,5) + pcp_op0404=(4,4) + pcp_op0405=(4,5) + pcp_op0406=(4,6) + pcp_op0505=(5,5) + pcp_op0506=(5,6) + R0608=(6,8) + ccB=(6,9) + pcp_op0707=(7,7) + pcp_op0708=(7,8) + pcp_op0808=(8,8) + pcp_op0909=(9,9) + pcp_op0910=(9,10) + pcp_op0912=(9,12) + pcp_op1010=(10,10) + pcp_op1012=(10,12) + pcp_op1111=(11,11) + pcp_op1212=(12,12) + addrmode=(13,15) +; + +define token pcpinstr2 (16) + pcp_op1631=(0,15) +; + +attach variables [ R0305 R0608 ] [ R0 R1 R2 R3 R4 R5 R6 R7 ]; + + +CONDCA: "cc_UC" is PCPMode=1 & ccA=0x0 { local tmp:1 = 1; export tmp; } +CONDCA: "cc_Z" is PCPMode=1 & ccA=0x1 { local tmp:1 = ($(Z)==1); export tmp; } +CONDCA: "cc_NZ" is PCPMode=1 & ccA=0x2 { local tmp:1 = ($(Z)==0); export tmp; } +CONDCA: "cc_V" is PCPMode=1 & ccA=0x3 { local tmp:1 = ($(V)==1); export tmp; } +CONDCA: "cc_ULT" is PCPMode=1 & ccA=0x4 { local tmp:1 = ($(C)==1); export tmp; } +CONDCA: "cc_UGT" is PCPMode=1 & ccA=0x5 { local tmp:1 = (($(C)|$(Z))==0); export tmp; } +CONDCA: "cc_SLT" is PCPMode=1 & ccA=0x6 { local tmp:1 = (($(N)^$(V))==1); export tmp; } +CONDCA: "cc_SGT" is PCPMode=1 & ccA=0x7 { local tmp:1 = ((($(N)^$(V))|$(Z))==0); export tmp; } + +CONDCB: "cc_UC" is PCPMode=1 & ccB=0x0 { local tmp:1 = 1; export tmp; } +CONDCB: "cc_Z" is PCPMode=1 & ccB=0x1 { local tmp:1 = ($(Z)==1); export tmp; } +CONDCB: "cc_NZ" is PCPMode=1 & ccB=0x2 { local tmp:1 = ($(Z)==0); export tmp; } +CONDCB: "cc_V" is PCPMode=1 & ccB=0x3 { local tmp:1 = ($(V)==1); export tmp; } +CONDCB: "cc_ULT" is PCPMode=1 & ccB=0x4 { local tmp:1 = ($(C)==1); export tmp; } +CONDCB: "cc_UGT" is PCPMode=1 & ccB=0x5 { local tmp:1 = (($(C)|$(Z))==0); export tmp; } +CONDCB: "cc_SLT" is PCPMode=1 & ccB=0x6 { local tmp:1 = (($(N)^$(V))==1); export tmp; } +CONDCB: "cc_SGT" is PCPMode=1 & ccB=0x7 { local tmp:1 = ((($(N)^$(V))|$(Z))==0); export tmp; } +CONDCB: "cc_N" is PCPMode=1 & ccB=0x8 { local tmp:1 = ($(N)==1); export tmp; } +CONDCB: "cc_NN" is PCPMode=1 & ccB=0x9 { local tmp:1 = ($(N)==0); export tmp; } +CONDCB: "cc_NV" is PCPMode=1 & ccB=0xA { local tmp:1 = ($(V)==0); export tmp; } +CONDCB: "cc_UGE" is PCPMode=1 & ccB=0xB { local tmp:1 = ($(C)==0); export tmp; } +CONDCB: "cc_SGE" is PCPMode=1 & ccB=0xC { local tmp:1 = (($(N)^$(V))==0); export tmp; } +CONDCB: "cc_SLE" is PCPMode=1 & ccB=0xD { local tmp:1 = ((($(N)^$(V))|$(Z))==1); export tmp; } +CONDCB: "cc_CNZ" is PCPMode=1 & ccB=0xE { local tmp:1 = ($(CNZ)==1); export tmp; } +CONDCB: "cc_CNN" is PCPMode=1 & ccB=0xF { local tmp:1 = ($(CNZ)==0); export tmp; } + +#TODO +CONDCAB: "cc_UC" is PCPMode=1 & ccAB=0x0 { local tmp:1 = 1; export tmp; } +CONDCAB: "cc_Z" is PCPMode=1 & ccAB=0x1 { local tmp:1 = ($(Z)==1); export tmp; } +CONDCAB: "cc_NZ" is PCPMode=1 & ccAB=0x2 { local tmp:1 = ($(Z)==0); export tmp; } +CONDCAB: "cc_V" is PCPMode=1 & ccAB=0x3 { local tmp:1 = ($(V)==1); export tmp; } +CONDCAB: "cc_ULT" is PCPMode=1 & ccAB=0x4 { local tmp:1 = ($(C)==1); export tmp; } +CONDCAB: "cc_UGT" is PCPMode=1 & ccAB=0x5 { local tmp:1 = (($(C)|$(Z))==0); export tmp; } +CONDCAB: "cc_SLT" is PCPMode=1 & ccAB=0x6 { local tmp:1 = (($(N)^$(V))==1); export tmp; } +CONDCAB: "cc_SGT" is PCPMode=1 & ccAB=0x7 { local tmp:1 = ((($(N)^$(V))|$(Z))==0); export tmp; } +CONDCAB: "cc_N" is PCPMode=1 & ccAB=0x8 { local tmp:1 = ($(N)==1); export tmp; } +CONDCAB: "cc_NN" is PCPMode=1 & ccAB=0x9 { local tmp:1 = ($(N)==0); export tmp; } +CONDCAB: "cc_NV" is PCPMode=1 & ccAB=0xA { local tmp:1 = ($(V)==0); export tmp; } +CONDCAB: "cc_UGE" is PCPMode=1 & ccAB=0xB { local tmp:1 = ($(C)==0); export tmp; } +CONDCAB: "cc_SGE" is PCPMode=1 & ccAB=0xC { local tmp:1 = (($(N)^$(V))==0); export tmp; } +CONDCAB: "cc_SLE" is PCPMode=1 & ccAB=0xD { local tmp:1 = ((($(N)^$(V))|$(Z))==1); export tmp; } +CONDCAB: "cc_CNZ" is PCPMode=1 & ccAB=0xE { local tmp:1 = ($(CNZ)==1); export tmp; } +CONDCAB: "cc_CNN" is PCPMode=1 & ccAB=0xF { local tmp:1 = ($(CNZ)==0); export tmp; } + +imm5: "#"^pcp_op0004 is pcp_op0004 { local tmp:4 = pcp_op0004; export tmp; } +imm6: "#"^pcp_op0005 is pcp_op0005 { local tmp:4 = pcp_op0005; export tmp; } +#imm10: "#"^pcp_op0009 is pcp_op0009 { local tmp:4 = pcp_op0009; export tmp; } +imm16: "#"^pcp_op1631 is pcp_op1631 { local tmp:4 = pcp_op1631; export tmp; } +offset6: "[#"^pcp_op0005^"]" is pcp_op0005 { local tmp:4 = (zext($(DPTR)) << 6) + pcp_op0005; export *[ram]:4 tmp; } + +offset6W: R0608, "[#"^pcp_op0005^"]" is pcp_op0005 & R0608 { local tmp:4 = (zext($(DPTR)) << 6) + pcp_op0005; *[ram]:4 tmp = R0608; } +offset6RW: R0608, "[#"^pcp_op0005^"]" is pcp_op0005 & R0608 { local tmp:4 = R0608; local ea:4 = (zext($(DPTR)) << 6) + pcp_op0005; R0608 = *[ram]:4 ea; *[ram]:4 ea = tmp; } + +SRC: R4 is PCPMode=1 & pcp_op0708=0 & R4 { local tmp:4 = 0; export tmp; } +SRC: R4+ is PCPMode=1 & pcp_op0708=1 & R4 { local tmp:4 = 1; export tmp; } +SRC: R4- is PCPMode=1 & pcp_op0708=2 & R4 { local tmp:4 = -1; export tmp; } + +DST: R5 is PCPMode=1 & pcp_op0910=0 & R5 { local tmp:4 = 0; export tmp; } +DST: R5+ is PCPMode=1 & pcp_op0910=1 & R5 { local tmp:4 = 1; export tmp; } +DST: R5- is PCPMode=1 & pcp_op0910=2 & R5 { local tmp:4 = -1; export tmp; } + +SIZE0: "8" is PCPMode=1 & pcp_op0001=0 { local tmp:4 = zext(*[ram]:1 R4); export tmp;} +SIZE0: "16" is PCPMode=1 & pcp_op0001=1 { local tmp:4 = zext(*[ram]:2 R4); export tmp;} +SIZE0: "32" is PCPMode=1 & pcp_op0001=2 { local tmp:4 = *[ram]:4 R4; export tmp;} + +SIZE1: [R0305], "8" is PCPMode=1 & pcp_op0001=0 & R0305 { local tmp:4 = zext(*[ram]:1 R0305); export tmp;} +SIZE1: [R0305], "16" is PCPMode=1 & pcp_op0001=1 & R0305 { local tmp:4 = zext(*[ram]:2 R0305); export tmp;} +SIZE1: [R0305], "32" is PCPMode=1 & pcp_op0001=2 & R0305 { local tmp:4 = *[ram]:4 R0305; export tmp;} + +SIZE1W: R0608, [R0305], "8" is PCPMode=1 & pcp_op0001=0 & R0305 & R0608 { *[ram]:1 R0305 = R0608[0,8]; } +SIZE1W: R0608, [R0305], "16" is PCPMode=1 & pcp_op0001=1 & R0305 & R0608 { *[ram]:2 R0305 = R0608[0,16]; } +SIZE1W: R0608, [R0305], "32" is PCPMode=1 & pcp_op0001=2 & R0305 & R0608 { *[ram]:4 R0305 = R0608; } + +SIZE1RW: R0608, [R0305], "8" is PCPMode=1 & pcp_op0001=0 & R0305 & R0608 { local tmp:1 = R0608[0,8]; R0608 = zext(*[ram]:1 R0305); *[ram]:1 R0305 = tmp; } +SIZE1RW: R0608, [R0305], "16" is PCPMode=1 & pcp_op0001=1 & R0305 & R0608 { local tmp:2 = R0608[0,16]; R0608 = zext(*[ram]:2 R0305); *[ram]:2 R0305 = tmp; } +SIZE1RW: R0608, [R0305], "32" is PCPMode=1 & pcp_op0001=2 & R0305 & R0608 { local tmp:4 = R0608; R0608 = *[ram]:4 R0305; *[ram]:4 R0305 = tmp; } + +SIZE5: "8" is PCPMode=1 & pcp_op0505=0 & pcp_op0909=0 & R0608 { local tmp:4 = zext(*[ram]:1 R0608); export tmp;} +SIZE5: "16" is PCPMode=1 & pcp_op0505=1 & pcp_op0909=0 & R0608 { local tmp:4 = zext(*[ram]:2 R0608); export tmp;} +SIZE5: "32" is PCPMode=1 & pcp_op0505=0 & pcp_op0909=1 & R0608 { local tmp:4 = *[ram]:4 R0608; export tmp;} + +SIZE5W: [R0608], imm5, "8" is PCPMode=1 & pcp_op0505=0 & pcp_op0909=0 & imm5 & R0608 { *[ram]:1 (R0608 + imm5) = R0[0,8]; } +SIZE5W: [R0608], imm5, "16" is PCPMode=1 & pcp_op0505=1 & pcp_op0909=0 & imm5 & R0608 { *[ram]:2 (R0608 + imm5) = R0[0,16]; } +SIZE5W: [R0608], imm5, "32" is PCPMode=1 & pcp_op0505=0 & pcp_op0909=1 & imm5 & R0608 { *[ram]:4 (R0608 + imm5) = R0; } + +# Counter Control +# 00 = perform xfer by CNT0 ; goto next +# 01 = perform xfer by CNT0 ; dec CNT1 ; goto next +# 10 = perform xfer by CNT0 ; dec CNT1 ; repeat dec ; goto next +CNC: pcp_op0506 is PCPMode=1 & pcp_op0506 { local tmp:4 = pcp_op0506; export tmp; } + +# Counter Reload Value (COPY) +# 001..111 = perform 1..7 xfer +CNT03: pcp_op0204 is PCPMode=1 & pcp_op0204 { local tmp:4 = pcp_op0204; export tmp; } + +# Counter Reload Value Block Size (BCOPY) +# 00 = block size 8 words +# 10 = block size 2 words +# 11 = block size 4 words +CNT02: pcp_op0203 is PCPMode=1 & pcp_op0203 { local tmp:4 = pcp_op0203; export tmp; } + +EC: pcp_op0707 is PCPMode=1 & pcp_op0707 { local tmp:1 = pcp_op0707; export tmp; } +EP: pcp_op0808 is PCPMode=1 & pcp_op0808 { local tmp:1 = pcp_op0808; export tmp; } +INT: pcp_op0909 is PCPMode=1 & pcp_op0909 { local tmp:1 = pcp_op0909; export tmp; } +ST: pcp_op1010 is PCPMode=1 & pcp_op1010 { local tmp:1 = pcp_op1010; export tmp; } + +SETCLR: "SET" is PCPMode=1 & pcp_op0505=1 { local tmp:1 = 1; export tmp; } +SETCLR: "CLR" is PCPMode=1 & pcp_op0505=0 { local tmp:1 = 0; export tmp; } + +SDB: pcp_op0000 is PCPMode=1 & pcp_op0000 { local tmp:1 = pcp_op0000; export tmp; } +EDA: pcp_op0101 is PCPMode=1 & pcp_op0101 { local tmp:1 = pcp_op0101; export tmp; } +RTA: pcp_op0202 is PCPMode=1 & pcp_op0202 { local tmp:1 = pcp_op0202; export tmp; } +DAC: pcp_op0303 is PCPMode=1 & pcp_op0303 { local tmp:1 = pcp_op0303; export tmp; } + +# Addressing Modes: +# 0 - control +# 1 - FPI +# 2 - PRAM +# 3 - Arithmetic +# 4 - Immediate +# 5 - FPI Immediate +# 6 - Complex Maths +# 7 - Jump + + +# 3: 16-bit 6000|0b110000000000000 9e00|0b1001111000000000 +# ADD Rb, Ra, cc_A +:add R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x0 & R0608 & R0305 & CONDCA +{ + #TODO flags N,Z,V,C + if (CONDCA == 0) goto inst_next; + R0608 = R0608 + R0305; +} + + +# 1: 16-bit 2000|0b10000000000000 de04|0b1101111000000100 +# ADD.F Rb, [Ra], Size +:add.f R0608, SIZE1 is PCPMode=1 & addrmode=0x1 & pcp_op0912=0x0 & pcp_op0202=0x0 & R0608 & R0305 & SIZE1 +{ + #TODO flags N,Z,V,C + build SIZE1; + R0608 = R0608 + SIZE1; +} + + +# 4: 16-bit 8000|0b1000000000000000 7e00|0b111111000000000 +# ADD.I Ra, #imm6 +:add.i R0608, imm6 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x0 & imm6 +{ + #TODO flags N,Z,V,C + R0608 = R0608 + imm6; +} + + +# 2: 16-bit 4000|0b100000000000000 be00|0b1011111000000000 +# ADD.PI Ra, [#offset6] +:add.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0912=0x0 & R0608 & offset6 +{ + #TODO flags N,Z,V,C + build offset6; + R0608 = R0608 + offset6; +} + + +# 3: 16-bit 6a00|0b110101000000000 9400|0b1001010000000000 +# AND Rb, Ra, cc_A +:and R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x5 & R0608 & R0305 & CONDCA +{ + #TODO flags N,Z + if (CONDCA == 0) goto inst_next; + R0608 = R0608 & R0305; +} + + +# 1: 16-bit 2a00|0b10101000000000 d404|0b1101010000000100 +# AND.F Rb, [Ra], Size +:and.f R0608, SIZE1 is PCPMode=1 & addrmode=0x1 & pcp_op0912=0x5 & pcp_op0202=0x0 & R0608 & R0305 & SIZE1 +{ + #TODO flags N,Z + build SIZE1; + R0608 = R0608 & SIZE1; +} + + +# 2: 16-bit 4a00|0b100101000000000 b400|0b1011010000000000 +# AND.PI Ra, [#offset6] +:and.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0912=0x5 & R0608 & offset6 +{ + #TODO flags N,Z + build offset6; + R0608 = R0608 & offset6; +} + + +# 0: 16-bit 1800|0b1100000000000 e013|0b1110000000010011 +# +:bcopy DST, SRC, CNC, CNT02 is PCPMode=1 & addrmode=0 & pcp_op1212=0x1 & pcp_op1111=0x1 & DST & SRC & CNC & CNT02 & pcp_op0404=0x0 & pcp_op0001=0x0 +{ +} + + +# 4: 16-bit 9c00|0b1001110000000000 6200|0b110001000000000 +# CHKB Ra, #imm5, S/C +:chkb R0608, imm5, SETCLR is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0xe & SETCLR & imm5 +{ + $(C) = (R0608 & (1 << imm5)) != 0; +} + + +# 4: 16-bit 9600|0b1001011000000000 6820|0b110100000100000 +# CLR Ra, #imm5 +:clr R0608, imm5 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0xb & pcp_op0505=0x0 & imm5 +{ + R0608 = R0608 & ~(1 << imm5); +} + + +# 5: 16-bit b000|0b1011000000000000 4c00|0b100110000000000 +# CLR.F [Ra], #imm5, Size +:clr.f [R0608], imm5, SIZE5 is PCPMode=1 & addrmode=0x5 & pcp_op1012=0x4 & R0608 & imm5 & SIZE5 +{ + build SIZE5; + *[ram]:4 R0608 = SIZE5 & ~(1 << imm5); +} + + +#TODO the manual does not specify +# N negative +# Z zero +# V overflow +# C carry +macro Flags(r0, r1) { + local val:4 = r0 - r1; + $(N) = val s< 0; + $(Z) = r0 == r1; + $(V) = r0[31,1] | r1[31,1]; + $(C) = r0 < r1; +} + +# 3: 16-bit 6400|0b110010000000000 9a00|0b1001101000000000 +# COMP Rb, Ra, cc_A +:comp R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x2 & R0608 & R0305 & CONDCA +{ + if (CONDCA == 0) goto inst_next; + Flags(R0608, R0305); +} + + +# 1: 16-bit 2400|0b10010000000000 da04|0b1101101000000100 +# COMP.F Rb, [Ra], Size +:comp.f R0608, SIZE1 is PCPMode=1 & addrmode=0x1 & pcp_op0912=0x2 & pcp_op0202=0x0 & R0608 & R0305 & SIZE1 +{ + build SIZE1; + Flags(R0608, SIZE1); +} + + +# 4: 16-bit 8400|0b1000010000000000 7a00|0b111101000000000 +# COMP.I Ra, #imm6 +:comp.i R0608, imm6 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x2 & imm6 +{ + Flags(R0608, imm6); +} + + +# 2: 16-bit 4400|0b100010000000000 ba00|0b1011101000000000 +# COMP.PI Ra, [#offset6] +:comp.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0912=0x2 & R0608 & offset6 +{ + build offset6; + Flags(R0608, offset6); +} + + +# 0: 16-bit 0800|0b100000000000 f000|0b1111000000000000 +# +:copy DST, SRC, CNC, CNT03, SIZE0 is PCPMode=1 & addrmode=0 & pcp_op1212=0x0 & pcp_op1111=0x1 & DST & SRC & CNC & CNT03 & SIZE0 +{ +} + +#TODO DEBUG SLEIGH instead +define pcodeop pcpdebug; + +# 7: 16-bit fc00|0b1111110000000000 0030|0b110000 +# DEBUG EDA, DAC, RTA, SDB, cc_B +:debug DAC, RTA, EDA, SDB, CONDCB is PCPMode=1 & addrmode=7 & pcp_op1012=0x7 & DAC & RTA & EDA & SDB & CONDCB & pcp_op0405=0x0 +{ + if (CONDCB == 0) goto inst_next; + pcpdebug(); +} + + +# 6: 16-bit c000|0b1100000000000000 3e07|0b11111000000111 +# DINIT , Rb, Ra +:dinit "<"^R0^">", R0608, R0305 is PCPMode=1 & addrmode=0x6 & pcp_op0912=0x0 & R0 & R0608 & R0305 & pcp_op0002=0x0 +{ + R0 = 0; + $(V) = R0305 == 0; + $(Z) = (R0608 == 0) && (R0305 != 0); +} + + +# 6: 16-bit c200|0b1100001000000000 3c07|0b11110000000111 +# DSTEP , Rb, Ra +:dstep "<"^R0^">", R0608, R0305 is PCPMode=1 & addrmode=0x6 & pcp_op0912=0x1 & R0 & R0608 & R0305 & pcp_op0002=0x0 +{ + #TODO flags Z not sure + R0 = (R0 << 8) + (R0608 >> 24); + R0608 = (R0608 << 8) + (R0 / R0305); + R0 = R0 % R0305; + $(Z) = R0 == 0; +} + + +# 0: 16-bit 1000|0b1000000000000 e870|0b1110100001110000 +# +:exit ST, EC, INT, EP, CONDCAB is PCPMode=1 & addrmode=0 & pcp_op1212=0x1 & pcp_op1111=0x0 & ST & EC & INT & EP & CONDCAB & pcp_op0406=0x0 +{ +} + + +# 3: 16-bit 7a00|0b111101000000000 8400|0b1000010000000000 +# INB Rb, Ra, cc_A +:inb R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0xd & R0608 & R0305 & CONDCA +{ + if (CONDCA == 0) goto inst_next; + R0608 = (R0608 & ~(1 << R0305[0,5])) | zext($(C) << R0305[0,5]); +} + + +# 4: 16-bit 9a00|0b1001101000000000 6420|0b110010000100000 +# INB.I Ra, #imm5 +:inb.i R0608, imm5 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0xd & pcp_op0505=0x0 & imm5 +{ + R0608 = (R0608 & ~(1 << imm5)) | zext($(C) << imm5); +} + +imm6pc: reloc is PCPMode=1 & pcp_op0005 [ reloc = inst_start + pcp_op0005; ] { export *[ram]:4 reloc; } +imm10pc: reloc is PCPMode=1 & pcp_op0009 [ reloc = inst_start + pcp_op0009; ] { export *[ram]:4 reloc; } +imm16abs: pcp_op1631 is PCPMode=1 & pcp_op1631 { export *[ram]:4 pcp_op1631; } + +# 7: 16-bit e400|0b1110010000000000 1800|0b1100000000000 +# JC offset6, cc_B +:jc imm6pc, CONDCB is PCPMode=1 & addrmode=7 & pcp_op1012=0x1 & imm6pc & CONDCB +{ + if (CONDCB == 0) goto inst_next; + goto imm6pc; +} + + +# 7: 32-bit e800|0b1110100000000000 143f|0b1010000111111 +# JC.A #address16, cc_B +:jc.a imm16abs, CONDCB is PCPMode=1 & addrmode=7 & pcp_op1012=0x2 & CONDCB & pcp_op0005=0 ; imm16abs +{ + if (CONDCB == 0) goto inst_next; + goto imm16abs; +} + + +# 7: 16-bit f000|0b1111000000000000 0c07|0b110000000111 +# JC.I Ra, cc_B +:jc.i [R0305], CONDCB is PCPMode=1 & addrmode=7 & pcp_op1012=0x4 & R0305 & CONDCB & pcp_op0002=0x0 +{ + if (CONDCB == 0) goto inst_next; + local tmp:4 = inst_start + zext(R0305[0,16]); + goto [tmp]; +} + + +# 7: 16-bit f400|0b1111010000000000 0807|0b100000000111 +# JC.IA Ra, cc_B +:jc.ia [R0305], CONDCB is PCPMode=1 & addrmode=7 & pcp_op1012=0x5 & R0305 & CONDCB & pcp_op0002=0x0 +{ + if (CONDCB == 0) goto inst_next; + local tmp:4 = zext(R0305[0,16]); + goto [tmp]; +} + + +# 7: 16-bit e000|0b1110000000000000 1c00|0b1110000000000 +# JL offset10 +:jl imm10pc is PCPMode=1 & addrmode=7 & pcp_op1012=0x0 & imm10pc +{ + goto imm10pc; +} + + +# 1: 16-bit 3200|0b11001000000000 cc04|0b1100110000000100 +# LD.F Rb, [Ra], Size +:ld.f R0608, SIZE1 is PCPMode=1 & addrmode=0x1 & pcp_op0912=0x9 & pcp_op0202=0x0 & R0608 & R0305 & SIZE1 +{ + R0608 = SIZE1; + $(N) = R0608 s< 0; + $(Z) = R0608 == 0; +} + + +# 4: 16-bit 9800|0b1001100000000000 6600|0b110011000000000 +# LD.I Ra, #imm6 +:ld.i R0608, imm6 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0xc & imm6 +{ + R0608 = imm6; + $(N) = R0608 s< 0; + $(Z) = R0608 == 0; +} + + +# 5: 16-bit b400|0b1011010000000000 4800|0b100100000000000 +# LD.IF [Ra], #offset5, Size +:ld.if [R0608], imm5, SIZE5 is PCPMode=1 & addrmode=0x5 & pcp_op1012=0x5 & R0608 & imm5 & SIZE5 +{ + R0608 = SIZE5 + imm5; + $(N) = R0608 s< 0; + $(Z) = R0608 == 0; +} + + +# 3: 16-bit 7200|0b111001000000000 8c00|0b1000110000000000 +# LD.P Rb, [Ra], cc_A +:ld.p R0608, [R0305], CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x9 & R0608 & R0305 & CONDCA +{ + if (CONDCA == 0) goto inst_next; + local tmp:4 = zext($(DPTR) << 6) + zext(R0305[0,6]); + R0608 = *[ram]:4 tmp; + $(N) = R0608 s< 0; + $(Z) = R0608 == 0; +} + + +# 2: 16-bit 5200|0b101001000000000 ac00|0b1010110000000000 +# LD.PI Ra, [#offset6] +:ld.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0912=0x9 & R0608 & offset6 +{ + R0608 = offset6; + $(N) = R0608 s< 0; + $(Z) = R0608 == 0; +} + + +# 4: 32-bit 9200|0b1001001000000000 6c3f|0b110110000111111 +# LDL.IL Ra, #imm16 +:ldl.il R0608, imm16 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x9 & pcp_op0005=0x0 ; imm16 +{ + #TODO are flags correct + R0608[0,16] = imm16[0,16]; + $(N) = R0608[0,16] s< 0; + $(Z) = R0608[0,16] == 0; +} + + +# 4: 32-bit 9000|0b1001000000000000 6e3f|0b110111000111111 +# +:ldl.iu R0608, imm16 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x8 & pcp_op0005=0x0 ; imm16 +{ + #TODO are flags correct + R0608[16,16] = imm16[0,16]; + $(N) = R0608[16,16] s< 0; + $(Z) = R0608[16,16] == 0; +} + + +# 2: 16-bit 4800|0b100100000000000 b600|0b1011011000000000 +# MCLR.PI Ra, [#offset6] +:mclr.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0005 & pcp_op0912=0x4 & R0608 & offset6 +{ + R0608 = R0608 & offset6; + local tmp:4 = zext($(DPTR) << 6) + pcp_op0005; + *[ram]:4 tmp = R0608; + $(N) = R0608 s< 0; + $(Z) = R0608 == 0; +} + + +# 6: 16-bit c400|0b1100010000000000 3a07|0b11101000000111 +# MINIT , Rb, Ra +:minit "<"^R0^">", R0608, R0305 is PCPMode=1 & addrmode=0x6 & pcp_op0912=0x2 & R0 & R0608 & R0305 & pcp_op0002=0x0 +{ + R0 = 0; + $(Z) = (R0608 == 0) || (R0305 == 0); +} + + +# 3: 16-bit 7800|0b111100000000000 8600|0b1000011000000000 +# MOV Rb, Ra, cc_A +:mov R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0xc & R0608 & R0305 & CONDCA +{ + if (CONDCA == 0) goto inst_next; + R0608 = R0305; + $(N) = R0608 s< 0; + $(Z) = R0608 == 0; +} + + +# 2: 16-bit 4c00|0b100110000000000 b200|0b1011001000000000 +# MSET.PI Ra, [#offset6] +:mset.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0005 & pcp_op0912=0x6 & R0608 & offset6 +{ + R0608 = R0608 | offset6; + local tmp:4 = zext($(DPTR) << 6) + pcp_op0005; + *[ram]:4 tmp = R0608; + $(N) = R0608 s< 0; + $(Z) = R0608 == 0; +} + + +# 6: 16-bit c600|0b1100011000000000 3807|0b11100000000111 +# +:mstep.l R0608, R0305 is PCPMode=1 & addrmode=0x6 & pcp_op0912=0x3 & R0608 & R0305 & pcp_op0002=0x0 +{ +} + + +# 6: 16-bit c800|0b1100100000000000 3607|0b11011000000111 +# +:mstep.u R0608, R0305 is PCPMode=1 & addrmode=0x6 & pcp_op0912=0x4 & R0608 & R0305 & pcp_op0002=0x0 +{ +} + + +# 3: 16-bit 6600|0b110011000000000 9800|0b1001100000000000 +# NEG Rb, Ra, cc_A +:neg R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x3 & R0608 & R0305 & CONDCA +{ + #TODO flags + if (CONDCA == 0) goto inst_next; + R0608 = -R0305; + $(N) = R0608 s< 0; + $(Z) = R0608 == 0; + $(V) = R0608[31,1]; + $(C) = R0305[31,1]; +} + + +# 0: 16-bit 0000|0b0 ffff|0b1111111111111111 +# NOP +:nop is PCPMode=1 & addrmode=0 & pcp_op1212=0x0 & pcp_op1111=0x0 & pcp_op0010=0x0 +{ + local NOP:1 = 0; + NOP = NOP; +} + + +# 3: 16-bit 6800|0b110100000000000 9600|0b1001011000000000 +# NOT Rb, Ra, cc_A +:not R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x4 & R0608 & R0305 & CONDCA +{ + if (CONDCA == 0) goto inst_next; + R0608 = ~R0305; + $(N) = R0608 s< 0; + $(Z) = R0608 == 0; +} + + +# 3: 16-bit 6e00|0b110111000000000 9000|0b1001000000000000 +# OR Rb, Ra, cc_A +:or R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x7 & R0608 & R0305 & CONDCA +{ + if (CONDCA == 0) goto inst_next; + R0608 = R0608 | R0305; + $(N) = R0608 s< 0; + $(Z) = R0608 == 0; +} + + +# 1: 16-bit 2e00|0b10111000000000 d004|0b1101000000000100 +# OR.F Rb, [Ra], Size +:or.f R0608, SIZE1 is PCPMode=1 & addrmode=0x1 & pcp_op0912=0x7 & pcp_op0202=0x0 & R0608 & R0305 & SIZE1 +{ + R0608 = R0608 | SIZE1; + $(N) = R0608 s< 0; + $(Z) = R0608 == 0; +} + + +# 2: 16-bit 4e00|0b100111000000000 b000|0b1011000000000000 +# OR.PI Ra, [#offset6] +:or.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0912=0x7 & R0608 & offset6 +{ + R0608 = R0608 | offset6; + $(N) = R0608 s< 0; + $(Z) = R0608 == 0; +} + + +# 3: 16-bit 7c00|0b111110000000000 8200|0b1000001000000000 +# PRI Rb, Ra, cc_A +:pri R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0xe & R0608 & R0305 & CONDCA +{ + #TODO pcodeop or this? also double check + if (CONDCA == 0) goto inst_next; + local index:4 = 0; + local tmp:4 = R0305; + if (tmp == 0) goto ; + + tmp = tmp >> 2; + index = index + 1; + if (tmp != 0) goto ; + + R0608 = zext(0x20 * (index == 0)) + (index * zext(index != 0)); + $(N) = R0608 s< 0; + $(Z) = R0608 == 0; +} + + +# 4: 16-bit 8e00|0b1000111000000000 7020|0b111000000100000 +# RL Ra, #imm5 +:rl R0608, imm5 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x7 & pcp_op0505=0x0 & imm5 +{ + #TODO double check + local tmp:4 = R0608; + R0608 = R0608 << imm5; + $(C) = (tmp & (1 << (32 - imm5))) != 0; + tmp = tmp >> (32 - imm5); + R0608 = tmp | R0608; + $(N) = R0608 s< 0; + $(Z) = R0608 == 0; +} + + +# 4: 16-bit 8c00|0b1000110000000000 7220|0b111001000100000 +# RR Ra, #imm5 +:rr R0608, imm5 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x6 & pcp_op0505=0x0 & imm5 +{ + #TODO double check + local tmp:4 = R0608; + R0608 = R0608 >> imm5; + tmp = tmp << (32 - imm5); + R0608 = tmp | R0608; + $(N) = R0608 s< 0; + $(Z) = R0608 == 0; +} + + +# 4: 16-bit 9400|0b1001010000000000 6a20|0b110101000100000 +# SET Ra, #imm5 +:set R0608, imm5 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0xa & pcp_op0505=0x0 & imm5 +{ + R0608 = R0608 | (1 << imm5); +} + + +# 5: 16-bit ac00|0b1010110000000000 5000|0b101000000000000 +# SET.F [Ra], #imm5, Size +:set.f [R0608], imm5, SIZE5 is PCPMode=1 & addrmode=0x5 & pcp_op1012=0x3 & R0608 & imm5 & SIZE5 +{ + build SIZE5; + *[ram]:4 R0608 = SIZE5 | (1 << imm5); +} + + +# 4: 16-bit 8a00|0b1000101000000000 7420|0b111010000100000 +# SHL Ra, #imm5 +:shl R0608, imm5 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x5 & pcp_op0505=0x0 & imm5 +{ + $(C) = (R0608 & (1 << (32 - imm5))) != 0; + R0608 = R0608 << imm5; + $(N) = R0608 s< 0; + $(Z) = R0608 == 0; +} + + +# 4: 16-bit 8800|0b1000100000000000 7620|0b111011000100000 +# SHR Ra, #imm5 +:shr R0608, imm5 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x4 & pcp_op0505=0x0 & imm5 +{ + R0608 = R0608 >> imm5; + $(N) = R0608 s< 0; + $(Z) = R0608 == 0; +} + + +# 1: 16-bit 3400|0b11010000000000 ca04|0b1100101000000100 +# ST.F Rb, [Ra], Size +:st.f SIZE1W is PCPMode=1 & addrmode=0x1 & pcp_op0912=0xa & pcp_op0202=0x0 & SIZE1W +{ + build SIZE1W; +} + + +# 5: 16-bit b800|0b1011100000000000 4400|0b100010000000000 +# ST.IF [Ra], #offset5, Size +:st.if SIZE5W is PCPMode=1 & addrmode=0x5 & pcp_op1012=0x6 & SIZE5W +{ + build SIZE5W; +} + + +# 3: 16-bit 7400|0b111010000000000 8a00|0b1000101000000000 +# ST.P Rb, [Ra], cc_A +:st.p R0608, [R0305], CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0xa & R0608 & R0305 & CONDCA +{ + if (CONDCA == 0) goto inst_next; + local tmp:4 = zext($(DPTR) << 6) + zext(R0305[0,6]); + *[ram]:4 tmp = R0608; +} + + +# 2: 16-bit 5400|0b101010000000000 aa00|0b1010101000000000 +# ST.PI Rb, [#offset6] +:st.pi offset6W is PCPMode=1 & addrmode=2 & pcp_op0912=0xa & offset6W +{ + build offset6W; +} + + +# 3: 16-bit 6200|0b110001000000000 9c00|0b1001110000000000 +# SUB Rb, Ra, cc_A +:sub R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x1 & R0608 & R0305 & CONDCA +{ + if (CONDCA == 0) goto inst_next; + R0608 = R0608 - R0305; + Flags(R0608, R0305); +} + + +# 1: 16-bit 2200|0b10001000000000 dc04|0b1101110000000100 +# SUB.F Rb, [Ra], Size +:sub.f R0608, SIZE1 is PCPMode=1 & addrmode=0x1 & pcp_op0912=0x1 & pcp_op0202=0x0 & R0608 & R0305 & SIZE1 +{ + build SIZE1; + local tmp:4 = SIZE1; + Flags(R0608, tmp); + R0608 = R0608 - tmp; +} + + +# 4: 16-bit 8200|0b1000001000000000 7c00|0b111110000000000 +# SUB.I Ra, #imm6 +:sub.i R0608, imm6 is PCPMode=1 & addrmode=4 & R0608 & pcp_op0912=0x1 & imm6 +{ + Flags(R0608, imm6); + R0608 = R0608 - imm6; +} + + +# 2: 16-bit 4200|0b100001000000000 bc00|0b1011110000000000 +# SUB.PI Ra, [#offset6] +:sub.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0912=0x1 & R0608 & offset6 +{ + Flags(R0608, offset6); + R0608 = R0608 - offset6; +} + + +# 1: 16-bit 3600|0b11011000000000 c804|0b1100100000000100 +# XCH.F Rb, [Ra], Size +:xch.f SIZE1RW is PCPMode=1 & addrmode=0x1 & pcp_op0912=0xb & pcp_op0202=0x0 & R0608 & SIZE1RW +{ + build SIZE1RW; + $(N) = R0608 s< 0; + $(Z) = R0608 == 0; +} + + +# 2: 16-bit 5600|0b101011000000000 a800|0b1010100000000000 +# XCH.PI Ra, [#offset6] +:xch.pi offset6RW is PCPMode=1 & addrmode=2 & pcp_op0912=0xb & R0608 & offset6RW +{ + build offset6RW; + $(N) = R0608 s< 0; + $(Z) = R0608 == 0; +} + + +# 3: 16-bit 7000|0b111000000000000 8e00|0b1000111000000000 +# XOR Rb, Ra, cc_A +:xor R0608, R0305, CONDCA is PCPMode=1 & addrmode=0x3 & pcp_op0912=0x8 & R0608 & R0305 & CONDCA +{ + if (CONDCA == 0) goto inst_next; + R0608 = R0608 ^ R0305; + $(N) = R0608 s< 0; + $(Z) = R0608 == 0; +} + + +# 1: 16-bit 3000|0b11000000000000 ce04|0b1100111000000100 +# XOR.F Rb, [Ra], Size +:xor.f R0608, SIZE1 is PCPMode=1 & addrmode=0x1 & pcp_op0912=0x8 & pcp_op0202=0x0 & R0608 & R0305 & SIZE1 +{ + R0608 = R0608 ^ SIZE1; + $(N) = R0608 s< 0; + $(Z) = R0608 == 0; +} + + +# 2: 16-bit 5000|0b101000000000000 ae00|0b1010111000000000 +# XOR.PI Ra, [#offset6] +:xor.pi R0608, offset6 is PCPMode=1 & addrmode=2 & pcp_op0912=0x8 & R0608 & offset6 +{ + R0608 = R0608 ^ offset6; + $(N) = R0608 s< 0; + $(Z) = R0608 == 0; +} diff --git a/python/icicle/Ghidra/Processors/tricore/data/languages/tricore.pspec b/python/icicle/Ghidra/Processors/tricore/data/languages/tricore.pspec new file mode 100644 index 0000000..73048dd --- /dev/null +++ b/python/icicle/Ghidra/Processors/tricore/data/languages/tricore.pspec @@ -0,0 +1,13 @@ + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/tricore/data/languages/tricore.sinc b/python/icicle/Ghidra/Processors/tricore/data/languages/tricore.sinc new file mode 100644 index 0000000..1c20278 --- /dev/null +++ b/python/icicle/Ghidra/Processors/tricore/data/languages/tricore.sinc @@ -0,0 +1,8548 @@ + +define alignment=2; +define space ram type=ram_space size=4 default; +define space register type=register_space size=4; + +#TODO This is probably in the spec +define register offset=0x00 size=4 contextreg; +define context contextreg + PCPMode=(0,0) +; + +# Data General Purpose Registers +define register offset=0xFF00 size=8 [ e0 e2 e4 e6 e8 e10 e12 e14 ]; +define register offset=0xFF00 size=4 [ d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ]; + +# Address General Purpose Registers +define register offset=0xFF80 size=8 [ p0 p2 p4 p6 p8 p10 p12 p14 ]; +define register offset=0xFF80 size=4 [ a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 ]; + +# Program Counter +define register offset=0xFE08 size=4 [ PC ]; + +# Program Status Word Register +define register offset=0xFE04 size=4 [ PSW ]; + +#TODO bitrange vs define vs context +# define bitrange PSW_USB=PSW[24,8] +# PSW_C=PSW[31,1] +# PSW_V=PSW[30,1] +# PSW_SV=PSW[29,1] +# PSW_AV=PSW[28,1] +# PSW_SAV=PSW[27,1] +# PSW_S=PSW[14,1] +# PSW_PRS=PSW[12,2] +# PSW_IO=PSW[10,2] +# PSW_IS=PSW[9,1] +# PSW_GW=PSW[8,1] +# PSW_CDE=PSW[7,1] +# PSW_CDC=PSW[0,7]; +@define PSW_USB "PSW[24,8]" +@define PSW_C "PSW[31,1]" +@define PSW_FS "PSW[31,1]" +@define PSW_V "PSW[30,1]" +@define PSW_FI "PSW[30,1]" +@define PSW_SV "PSW[29,1]" +@define PSW_FV "PSW[29,1]" +@define PSW_AV "PSW[28,1]" +@define PSW_FZ "PSW[28,1]" +@define PSW_SAV "PSW[27,1]" +@define PSW_FU "PSW[27,1]" +@define PSW_FX "PSW[26,1]" +@define PSW_RM "PSW[24,2]" +@define PSW_S "PSW[14,1]" +@define PSW_PRS "PSW[12,2]" +@define PSW_IO "PSW[10,2]" +@define PSW_IS "PSW[9,1]" +@define PSW_GW "PSW[8,1]" +@define PSW_CDE "PSW[7,1]" +@define PSW_CDC "PSW[0,7]" + +# Previous Context Information and Pointer Register +define register offset=0xFE00 size=4 [ PCXI ]; +# define context PCXI +# PCXO=(0,15) +# PCXS=(16,19) +# UL=(20,20) +# PIE=(21,21) +# PCPN=(22,29) +# ; + +# Interrupt Stack Pointer Register +define register offset=0xFE28 size=4 [ ISP ]; + +# System Control Register +define register offset=0xFE14 size=4 [ SYSCON ]; +# define context SYSCON +# FCDSF=(0,0) +# PROTEN=(1,1) +# TPROTEN=(2,2) +# IS=(3,3) +# TS=(4,4) +# U1_IED=(16,16) +# U1_IOS=(17,17) +# ; + +# CPU Identification Register +define register offset=0xFE18 size=4 [ CPU_ID ]; +# define context CPU_ID +# MOD_REV=(0,7) +# MOD_32B=(8,15) +# MOD=(16,31) +# ; + +# Core Identification Register +define register offset=0xFE1C size=4 [ CORE_ID ]; + + +# Compatibility Mode Register +define register offset=0x9400 size=4 [ COMPAT ]; + +# SIST Mode Access Control Register +define register offset=0x900C size=4 [ SMACON ]; + +# Free CSA List Head Pointer Register +define register offset=0xFE38 size=4 [ FCX ]; +# define context FCX +# FCXO=(0,15) +# FCXS=(16,19) +# ; + +# Free CSA List Limit Pointer Register +define register offset=0xFE3C size=4 [ LCX ]; +# define context LCX +# LCXO=(0,15) +# LCXS=(16,19) +# ; + +# ICU Interrupt Control Register +define register offset=0xFE2C size=4 [ ICR ]; +define register offset=0xFE2E size=1 [ PIPN ]; +# define context ICR +# CCPN=(0,7) +# IE=(15,15) +# PIPN=(16,23) +# ; +@define ICR_PIPN "ICR[16,8]" +@define ICR_IE "ICR[15,1]" +@define ICR_CCPN "ICR[0,8]" + +# Base Interrupt Vector Table Pointer +define register offset=0xFE20 size=4 [ BIV ]; +# define context BIV +# VSS=(0,0) +# ; + +# Base Trap Vector Table Pointer +define register offset=0xFE24 size=4 [ BTV ]; + +# Program Synchronous Error Trap Register +define register offset=0x9200 size=4 [ PSTR ]; + +# Data Synchronous Error Trap Register +define register offset=0x9010 size=4 [ DSTR ]; + +# Data Asynchronous Error Trap Register +define register offset=0x9018 size=4 [ DATR ]; + +# Data Error Address Register +define register offset=0x901C size=4 [ DEADD ]; + +# Program Integrity Error Trap Register +define register offset=0x9214 size=4 [ PIETR ]; + +# Program Integrity Error Address Register +define register offset=0x9210 size=4 [ PIEAR ]; + +# Data Integrity Error Trap Register +define register offset=0x9024 size=4 [ DIETR ]; + +# Data Integrity Error Address Register +define register offset=0x9020 size=4 [ DIEAR ]; + +# Programmable Memory Access Register +define register offset=0x8100 size=4 [ PMA0 PMA1 PMA2 ]; + +# Program Memory Configuration Registers +define register offset=0x9204 size=4 [ PCON1 PCON2 PCON0 ]; + +# Data Memory Configuration Registers +define register offset=0x9040 size=4 [ DCON0 ]; +define register offset=0x9008 size=4 [ DCON1 ]; +define register offset=0x9000 size=4 [ DCON2 ]; + +# Data Protection Range Register Lower & Upper Bound +define register offset=0xC000 size=4 [ DPR0_L DPR0_U DPR1_L DPR1_U DPR2_L DPR2_U DPR3_L DPR3_U DPR4_L DPR4_U DPR5_L DPR5_U DPR6_L DPR6_U DPR7_L DPR7_U DPR8_L DPR8_U DPR9_L DPR9_U DPR10_L DPR10_U DPR11_L DPR11_U DPR12_L DPR12_U DPR13_L DPR13_U DPR14_L DPR14_U DPR15_L DPR15_U ]; + +# Code Protection Range Register Lower & Upper Bound +define register offset=0xD000 size=4 [ CPR0_L CPR0_U CPR1_L CPR1_U CPR2_L CPR2_U CPR3_L CPR3_U CPR4_L CPR4_U CPR5_L CPR5_U CPR6_L CPR6_U CPR7_L CPR7_U CPR8_L CPR8_U CPR9_L CPR9_U CPR10_L CPR10_U CPR11_L CPR11_U CPR12_L CPR12_U CPR13_L CPR13_U CPR14_L CPR14_U CPR15_L CPR15_U ]; + +# Data Protection Read Enable Set Configuration Register +define register offset=0xE010 size=4 [ DPRE_0 DPRE_1 DPRE_2 DPRE_3 ]; + +# Data Protection Write Enable Set Configuration Register +define register offset=0xE020 size=4 [ DPWE_0 DPWE_1 DPWE_2 DPWE_3 ]; + +# Code Protection Execute Enable Set Configuration Register +define register offset=0xE000 size=4 [ CPXE_0 CPXE_1 CPXE_2 CPXE_3 ]; + +# Temporal Protect System (TPS) Timer Register +define register offset=0xE404 size=4 [ TPS_TIMER0 TPS_TIMER1 TPS_TIMER2 ]; + +# TPS Control Register +define register offset=0xE400 size=4 [ TPS_CON ]; +# define context TPS_CON +# TEXP0=(0,0) +# TEXP1=(1,1) +# TEXP2=(2,2) +# TTRAP=(16,16) +# ; + +# FPU Trap Control Register +define register offset=0xA000 size=4 [ FPU_TRAP_CON ]; +# define context FPU_TRAP_CON +# TST=(0,0) +# TCL=(1,1) +# RM=(8,9) +# FXE=(18,18) +# FUE=(19,19) +# FZE=(20,20) +# FVE=(21,21) +# FIE=(22,22) +# FX=(26,26) +# FU=(27,27) +# FZ=(28,28) +# FV=(29,29) +# FI=(30,30) +# ; + +# FPU Trapping Instruction Program Counter +define register offset=0xA004 size=4 [ FPU_TRAP_PC ]; + +# FPU Trapping Instruction Opcode Register +define register offset=0xA008 size=4 [ FPU_TRAP_OPC ]; +# define context FPU_TRAP_OPC +# OPC=(0,7) +# FMT=(8,8) +# DREG=(16,19) +# ; + +# FPU Trapping Instruction Operand SRC1 Register +define register offset=0xA010 size=4 [ FPU_TRAP_SRC1 FPU_TRAP_SRC2 FPU_TRAP_SRC3 ]; + + + +# Core Debug Controller (CDC) Registers +# Debug Status Register +define register offset=0xFD00 size=4 [ DBGSR ]; +# define context DBGSR +# DE=(0,0) +# HALT=(1,2) +# SIH=(3,3) +# SUSP=(4,4) +# PREVSUSP=(6,6) +# PEVT=(7,7) +# EVTSRC=(8,12) +# ; +@define DBGSR_EVTSRC "DBGSR[8,5]" +@define DBGSR_PEVT "DBGSR[7,1]" +@define DBGSR_PREVSUSP "DBGSR[6,1]" +@define DBGSR_SUSP "DBGSR[4,1]" +@define DBGSR_SIH "DBGSR[3,1]" +@define DBGSR_HALT "DBGSR[1,2]" +@define DBGSR_DE "DBGSR[0,1]" + +# External Event Register +define register offset=0xFD08 size=4 [ EXEVT ]; +# define context EXEVT +# EVTA=(0,2) +# BBM=(3,3) +# BOD=(4,4) +# SUSP=(5,5) +# CNT=(6,7) +# ; + +# Core Register Access Event Register +define register offset=0xFD0C size=4 [ CREVT ]; +# define context CREVT +# CREVT_EVTA=(0,2) +# CREVT_BBM=(3,3) +# CREVT_BOD=(4,4) +# CREVT_SUSP=(5,5) +# CREVT_CNT=(6,7) +# ; + +# Software Debug Event Register +define register offset=0xFD10 size=4 [ SWEVT ]; +# define context SWEVT +# SWEVT_EVTA=(0,2) +# SWEVT_BBM=(3,3) +# SWEVT_BOD=(4,4) +# SWEVT_SUSP=(5,5) +# SWEVT_CNT=(6,7) +# ; + +# Trigger Accumulator Register +define register offset=0xFD30 size=4 [ TRIG_ACC ]; +# define context TRIC_ACC +# T0=(0,0) +# T1=(1,1) +# T2=(2,2) +# T3=(3,3) +# T4=(4,4) +# T5=(5,5) +# T6=(6,6) +# T7=(7,7) +# ; + +# Debug Monitor Start Address Register +define register offset=0xFD40 size=4 [ DMS ]; + +# Debug Context Save Area Pointer Register +define register offset=0xFD44 size=4 [ DCX ]; + +# Debug Trap Control Register +define register offset=0xFD48 size=4 [ DBGTCR ]; + +# Application Space Identifier Register +define register offset=0x8004 size=4 [ TASK_ASI ]; + +# Software Breakpoint Service Request Control +#define register offset=0xFFB0 size=4 [ SBSRC3 SBSRC2 SBSRC1 SBSRC0 ]; + +# Trigger Event Configuration / Address Register +define register offset=0xF000 size=4 [ TR0EVT TR0ADR TR1EVT TR1ADR TR2EVT TRA2DR TR3EVT TR3ADR TR4EVT TR4ADR TR5EVT TR5ADR TR6EVT TR6ADR TR7EVT TR7ADR ]; +# define context TRxEVT +# EVTA=(0,2) +# BBM=(3,3) +# BOD=(4,4) +# SUSP=(5,5) +# CNT=(6,7) +# TYP=(12,12) +# RNG=(13,13) +# ASI_EN=(15,15) +# ASI=(16,20) +# AST=(27,27) +# ALD=(28,28) +# ; + + +# Counter Control Register +define register offset=0xFC00 size=4 [ CCTRL ]; +# define context CCTRL +# CM=(0,0) +# CE=(1,1) +# M1=(2,4) +# M2=(5,7) +# M3=(8,10) +# ; + +# CPU Clock Cycle Count Register +define register offset=0xFC04 size=4 [ CCNT ]; + +# Instruction Count Register +define register offset=0xFC08 size=4 [ ICNT ]; + +# Mult-Count Register +define register offset=0xFC0C size=4 [ M1CNT M2CNT M3CNT ]; + + + + + +define token instr (16) + op0003=(0, 3) + op0005=(0, 5) + op0006=(0, 6) + op0007=(0, 7) + op0404=(4, 4) + op0405=(4, 5) + op0407=(4, 7) + op0606=(6, 6) + op0607=(6, 7) + op0707=(7, 7) + op0810=(8, 10) + Rd0811=(8, 11) + Ra0811=(8, 11) + Re0811=(8, 11) + Ree0811=(8, 11) + Reo0811=(8, 11) + ReN0811=(8, 11) + op0811=(8, 11) + Rp0811=(8, 11) + Rpe0811=(8, 11) + Rpo0811=(8, 11) + op0815=(8, 15) + sop0815=(8, 15) signed + op1111=(11, 11) + Rd1215=(12, 15) + op1215=(12, 15) + sop1215=(12, 15) signed + Ra1215=(12, 15) + Rpe1215=(12, 15) + Rpo1215=(12, 15) + op1515=(15, 15) +; + +define token instr2 (16) + op1617=(0, 1) + op1620=(0, 4) + sop1620=(0, 4) signed + op1621=(0, 5) + op1622=(0, 6) + op1623=(0, 7) + op1627=(0, 11) + sop1627=(0, 11) signed + sop1630=(0, 14) signed + op1631=(0, 15) + op1819=(2, 3) + op1823=(2, 7) + op1827=(2, 11) + op2020=(4, 4) + op2023=(4, 7) + op2027=(4, 11) + op2122=(5, 6) + op2123=(5, 7) + op2127=(5, 11) + op2131=(5, 15) + op2225=(6, 9) + op2227=(6, 11) + sop2227=(6, 11) signed + op2327=(7, 11) + Rd2427=(8, 11) + Re2427=(8, 11) + Ree2427=(8, 11) + Reo2427=(8, 11) + op2627=(10, 11) + Rd2831=(12, 15) + Ra2831=(12, 15) + Re2831=(12, 15) + Ree2831=(12, 15) + Reo2831=(12, 15) + op2831=(12, 15) + sop2831=(12, 15) signed + op3131=(15, 15) +; + + + +attach variables [ Rd0811 Rd1215 Rd2427 Rd2831 ] [ d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ]; +attach variables [ Re0811 Re2427 Re2831 ] [ e0 _ e2 _ e4 _ e6 _ e8 _ e10 _ e12 _ e14 _ ]; +attach variables [ ReN0811 ] [ e2 _ e4 _ e6 _ e8 _ e10 _ e12 _ e14 _ e0 _ ]; +attach variables [ Ree0811 Ree2427 Ree2831 ] [ d0 _ d2 _ d4 _ d6 _ d8 _ d10 _ d12 _ d14 _]; +attach variables [ Reo0811 Reo2427 Reo2831 ] [ d1 _ d3 _ d5 _ d7 _ d9 _ d11 _ d13 _ d15 _]; + +attach variables [ Ra0811 Ra1215 Ra2831 ] [ a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 ]; +attach variables [ Rp0811 ] [ p0 _ p2 _ p4 _ p6 _ p8 _ p10 _ p12 _ p14 _ ]; +attach variables [ Rpe0811 Rpe1215 ] [ a0 _ a2 _ a4 _ a6 _ a8 _ a10 _ a12 _ a14 _]; +attach variables [ Rpo0811 Rpo1215 ] [ a1 _ a3 _ a5 _ a7 _ a9 _ a11 _ a13 _ a15 _]; + + + + +# 0 MMU +# * 0 VAF +# * 1 VAP +# 1 Internal Protection Traps +# * 1 PRIV +# * 2 MPR +# * 3 MPW +# * 4 MPX +# * 5 MPP +# * 6 MPN +# * 7 GRWP +# 2 Instruction Errors +# * 1 IOPC +# * 2 UOPC +# * 3 OPD +# * 4 ALN +# * 5 MEM +# 3 Context Management +# * 1 FCD +# * 2 CDO +# * 3 CDU +# * 4 FCU +# * 5 CSU +# * 6 CTYP +# * 7 NEST +# 4 System Bus and Peripheral Errors +# * 1 PSE +# * 2 DSE +# * 3 DAE +# * 4 CAE +# * 5 PIE +# * 6 DIE +# * 7 TAE +# 5 Assertion Traps +# * 1 OVF +# * 2 SOVF +# 6 System Call +# * 0-255 SYS +# 7 Non-Maskable Interrupt +# * 0 NMI +define pcodeop trap; + + +define pcodeop cache_address_ivld; +define pcodeop cache_address_wb; +define pcodeop cache_address_wi; +define pcodeop cache_index_ivld; +define pcodeop cache_index_wb; +define pcodeop cache_index_wi; +define pcodeop round16; +define pcodeop leading_signs; +define pcodeop crc32; + +# float +define pcodeop denorm_to_zero; +define pcodeop ieee754_round; +define pcodeop ieee754_32bit_format; + +define pcodeop coprocessor; + +define pcodeop debug; +define pcodeop dsync; +define pcodeop isync; +define pcodeop tlbdemap; +define pcodeop tlbflusha; +define pcodeop tlbflushb; +define pcodeop tlbmap; +define pcodeop tlbprobea; +define pcodeop tlbprobei; +define pcodeop wait; + + +@if defined(TRICORE_VERBOSE) +@else +define pcodeop bmerge; +define pcodeop bsplit; +define pcodeop load_lower_context; +define pcodeop load_upper_context; +define pcodeop store_lower_context; +define pcodeop store_upper_context; +@endif + + + +#TODO +define pcodeop reverse16; +# macro reverse16(src, dst) { +# dst[0,1]=src[15,1]; +# dst[1,1]=src[14,1]; +# dst[2,1]=src[13,1]; +# dst[3,1]=src[12,1]; +# dst[4,1]=src[11,1]; +# dst[5,1]=src[10,1]; +# dst[6,1]=src[9,1]; +# dst[7,1]=src[8,1]; +# dst[8,1]=src[7,1]; +# dst[9,1]=src[6,1]; +# dst[10,1]=src[5,1]; +# dst[11,1]=src[4,1]; +# dst[12,1]=src[3,1]; +# dst[13,1]=src[2,1]; +# dst[14,1]=src[1,1]; +# dst[15,1]=src[0,1]; +# } + +macro overflowflagsd(r) { + $(PSW_V) = r[63,1]; + $(PSW_SV) = $(PSW_V) | $(PSW_SV); + $(PSW_AV) = r[63,1] ^ r[62,1]; + $(PSW_SAV) = $(PSW_AV) | $(PSW_SAV); +} + +macro overflowflagsww(r1, r0) { + $(PSW_V) = r1[31,1] | r0[31,1]; + $(PSW_SV) = $(PSW_V) | $(PSW_SV); + $(PSW_AV) = (r1[31,1] ^ r1[30,1]) | (r0[31,1] ^ r0[30,1]); + $(PSW_SAV) = $(PSW_AV) | $(PSW_SAV); +} + +macro advoverflowflagsww(r1, r0) { + $(PSW_V) = 0; + $(PSW_AV) = (r1[31,1] ^ r1[30,1]) | (r0[31,1] ^ r0[30,1]); + $(PSW_SAV) = $(PSW_AV) | $(PSW_SAV); +} + +macro advoverflowflags(r) { + $(PSW_V) = 0; + $(PSW_AV) = r[31,1] ^ r[30,1]; + $(PSW_SAV) = $(PSW_AV) | $(PSW_SAV); +} + +macro overflowflags(r) { + $(PSW_V) = r[31,1]; + $(PSW_SV) = $(PSW_V) | $(PSW_SV); + $(PSW_AV) = r[31,1] ^ r[30,1]; + $(PSW_SAV) = $(PSW_AV) | $(PSW_SAV); +} + +macro overflowflagsh(r1, r0) { + $(PSW_V) = r1[15,1] | r0[15,1]; + $(PSW_SV) = $(PSW_V) | $(PSW_SV); + $(PSW_AV) = (r1[15,1] ^ r1[14,1]) | (r0[15,1] ^ r0[14,1]); + $(PSW_SAV) = $(PSW_AV) | $(PSW_SAV); +} + +macro overflowflagsb(r3, r2, r1, r0) { + $(PSW_V) = r3[7,1] | r2[7,1] | r1[7,1] | r0[7,1]; + $(PSW_SV) = $(PSW_V) | $(PSW_SV); + $(PSW_AV) = (r3[7,1] ^ r3[6,1]) | (r2[7,1] ^ r2[6,1]) | (r1[7,1] ^ r1[6,1]) | (r0[7,1] ^ r0[6,1]); + $(PSW_SAV) = $(PSW_AV) | $(PSW_SAV); +} + + +#define pcodeop ssov; +macro ssov(res,x,y) { + local max_pos = (1 << (y - 1)) - 1; + local max_neg = -(1 << (y - 1)); + local sc1 = x s> max_pos; + local sc2 = x s< max_neg; + res = (max_pos * zext(sc1 != 0)) + (max_neg * zext(sc1 == 0 && sc2 != 0)) + (x * zext(sc1 == 0 && sc2 == 0)); +} + +#define pcodeop suov; +macro suov(res,x,y) { + local max_pos = (1 << y) - 1; + local sc1 = x s> max_pos; + local sc2 = x s< 0; + res = (max_pos * zext(sc1 != 0)) + (x * zext(sc1 == 0 && sc2 == 0)); +} + +macro int_abs(res, val) { + local acond = val s< 0; + res = (val * zext(acond == 0)) + (-val * zext(acond != 0)); +} +macro int_abs1(res, val) { + local acond = val s< 0; + res = (val * (acond == 0)) + (-val * (acond != 0)); +} + +macro ternary(res, cond, avar, bvar) { + res = (avar * zext(cond != 0)) + (bvar * zext(cond == 0)); +} + +@if defined(TRICORE_VERBOSE) +macro load_lower_context(EA) { + # dummy = *[ram]:4 EA ; + EA = EA + 4; + # dummy = *[ram]:4 EA ; + EA = EA + 4; + a2 = *[ram]:4 EA ; EA = EA + 4; + a3 = *[ram]:4 EA ; EA = EA + 4; + d0 = *[ram]:4 EA ; EA = EA + 4; + d1 = *[ram]:4 EA ; EA = EA + 4; + d2 = *[ram]:4 EA ; EA = EA + 4; + d3 = *[ram]:4 EA ; EA = EA + 4; + a4 = *[ram]:4 EA ; EA = EA + 4; + a5 = *[ram]:4 EA ; EA = EA + 4; + a6 = *[ram]:4 EA ; EA = EA + 4; + a7 = *[ram]:4 EA ; EA = EA + 4; + d4 = *[ram]:4 EA ; EA = EA + 4; + d5 = *[ram]:4 EA ; EA = EA + 4; + d6 = *[ram]:4 EA ; EA = EA + 4; + d7 = *[ram]:4 EA ; EA = EA + 4; +} +@endif + +@if defined(TRICORE_VERBOSE) +macro store_lower_context(EA) { + *[ram]:4 EA = PCXI; EA = EA + 4; + *[ram]:4 EA = a11; EA = EA + 4; + *[ram]:4 EA = a2; EA = EA + 4; + *[ram]:4 EA = a3; EA = EA + 4; + *[ram]:4 EA = d0; EA = EA + 4; + *[ram]:4 EA = d1; EA = EA + 4; + *[ram]:4 EA = d2; EA = EA + 4; + *[ram]:4 EA = d3; EA = EA + 4; + *[ram]:4 EA = a4; EA = EA + 4; + *[ram]:4 EA = a5; EA = EA + 4; + *[ram]:4 EA = a6; EA = EA + 4; + *[ram]:4 EA = a7; EA = EA + 4; + *[ram]:4 EA = d4; EA = EA + 4; + *[ram]:4 EA = d5; EA = EA + 4; + *[ram]:4 EA = d6; EA = EA + 4; + *[ram]:4 EA = d7; EA = EA + 4; +} +@endif + +macro _restore_upper_context(EA) { + a10 = *[ram]:4 EA; EA = EA + 4; + a11 = *[ram]:4 EA; EA = EA + 4; + d8 = *[ram]:4 EA; EA = EA + 4; + d9 = *[ram]:4 EA; EA = EA + 4; + d10 = *[ram]:4 EA; EA = EA + 4; + d11 = *[ram]:4 EA; EA = EA + 4; + a12 = *[ram]:4 EA; EA = EA + 4; + a13 = *[ram]:4 EA; EA = EA + 4; + a14 = *[ram]:4 EA; EA = EA + 4; + a15 = *[ram]:4 EA; EA = EA + 4; + d12 = *[ram]:4 EA; EA = EA + 4; + d13 = *[ram]:4 EA; EA = EA + 4; + d14 = *[ram]:4 EA; EA = EA + 4; + d15 = *[ram]:4 EA; EA = EA + 4; +} + +@if defined(TRICORE_VERBOSE) +macro restore_upper_context(EA) { + PCXI = *[ram]:4 EA; EA = EA + 4; + PSW = *[ram]:4 EA; EA = EA + 4; + _restore_upper_context(EA); +} +@endif + + +define pcodeop saveCallerState; +define pcodeop restoreCallerState; + + +@if defined(TRICORE_VERBOSE) +macro restore_debug_context(EA) { + PCXI = *[ram]:4 EA; EA = EA + 4; + PSW = *[ram]:4 EA; EA = EA + 4; + a10 = *[ram]:4 EA; EA = EA + 4; + a11 = *[ram]:4 EA; EA = EA + 4; +} +@else +define pcodeop restore_debug_context; +@endif + +@if defined(TRICORE_VERBOSE) +macro load_upper_context(EA) { + # dummy = *[ram]:4 EA; + EA = EA + 4; + # dummy = *[ram]:4 EA; + EA = EA + 4; + _restore_upper_context(EA); +} +@endif + +@if defined(TRICORE_VERBOSE) +macro store_upper_context(EA) { + *[ram]:4 EA = PCXI; EA = EA + 4; + *[ram]:4 EA = PSW; EA = EA + 4; + *[ram]:4 EA = a10; EA = EA + 4; + *[ram]:4 EA = a11; EA = EA + 4; + *[ram]:4 EA = d8; EA = EA + 4; + *[ram]:4 EA = d9; EA = EA + 4; + *[ram]:4 EA = d10; EA = EA + 4; + *[ram]:4 EA = d11; EA = EA + 4; + *[ram]:4 EA = a12; EA = EA + 4; + *[ram]:4 EA = a13; EA = EA + 4; + *[ram]:4 EA = a14; EA = EA + 4; + *[ram]:4 EA = a15; EA = EA + 4; + *[ram]:4 EA = d12; EA = EA + 4; + *[ram]:4 EA = d13; EA = EA + 4; + *[ram]:4 EA = d14; EA = EA + 4; + *[ram]:4 EA = d15; EA = EA + 4; +} +@endif + +macro BitReverseAddressingMode(rege, rego, EA) { + local index:2 = rego[0,16]; + local incr:2 = rego[16,16]; + EA = rege + zext(index); + local rindex:2 = reverse16(index); + local rincr:2 = reverse16(incr); + local new_index:2 = reverse16(rindex + rincr); + rego[0,16] = new_index; +} + +macro CircularAddressingMode(rege, rego, EA0, off10) { + local index:2 = rego[0,16]; + local length:2 = rego[16,16]; + EA0 = rege + zext(index); + local new_index:2 = index + off10[0,10]; + ternary(new_index, new_index s< 0, new_index + length, new_index % length); + rego[0,16] = new_index; +} + +macro CircularAddressingMode2(rege, rego, EA0, EA1, off10, circsize) { + local index:2 = rego[0,16]; + local length:2 = rego[16,16]; + EA0 = rege + zext(index); + EA1 = rege + zext((index + circsize) % length); + local new_index:2 = index + off10[0,10]; + ternary(new_index, new_index s< 0, new_index + length, new_index % length); + rego[0,16] = new_index; +} + +macro CircularAddressingMode4(rege, rego, EA0, EA1, EA2, EA3, off10, circsize) { + local index:2 = rego[0,16]; + local length:2 = rego[16,16]; + EA0 = rege + zext(index); + EA1 = rege + zext((index + circsize) % length); + EA2 = rege + zext((index + circsize + circsize) % length); + EA3 = rege + zext((index + circsize + circsize + circsize) % length); + local new_index:2 = index + off10[0,10]; + ternary(new_index, new_index s< 0, new_index + length, new_index % length); + rego[0,16] = new_index; +} + +#TODO Should probably just delete this and any "+i" until referencing a +# T2 manual instead of DSP/compiler guide +macro IndexAddressingMode(rege, rego, EA) { + local index:2 = rego[0,16]; + local modifier:2 = rego[16,16]; + EA = rege + zext(index); + rego[0,16] = index + modifier; +} + +off10: reloc is PCPMode=0 & op1621 & sop2831 [ reloc = op1621 | (sop2831 << 6); ] { local tmp:4 = reloc; export tmp; } + +off16: reloc is PCPMode=0 & op1621 & sop2227 & op2831 [ reloc = op1621 | (op2831 << 6) | (sop2227 << 10); ] { local tmp:4 = reloc; export tmp; } + +off18: reloc is PCPMode=0 & op1215 ; op1621 & op2225 & op2831 [ reloc = (op1215 << 28) | (op2225 << 10) | (op2831 << 6) | op1621; ] { local tmp:4 = reloc; export tmp; } + +off24pc: reloc is PCPMode=0 & sop0815 ; op1631 [ reloc = inst_start + ((op1631 | (sop0815 << 16)) * 2); ] { export *[ram]:4 reloc; } + +off24abs: reloc is PCPMode=0 & op0811 & op1215 ; op1631 [ reloc = (op1631 << 1) | (op0811 << 17) | (op1215 << 28); ] { export *[ram]:4 reloc; } + +off0811pc4o: reloc is PCPMode=0 & op0811 [ reloc = inst_start + (0xffffffe0 | (op0811 << 1)); ] { export *[ram]:4 reloc; } + +off0811pc4z: reloc is PCPMode=0 & op0811 [ reloc = inst_start + (op0811 * 2); ] { export *[ram]:4 reloc; } + +off0815pc8s: reloc is PCPMode=0 & sop0815 [ reloc = inst_start + (sop0815 * 2); ] { export *[ram]:4 reloc; } + +off1630pc15s: reloc is PCPMode=0 & sop1630 [ reloc = inst_start + (sop1630 * 2); ] { export *[ram]:4 reloc; } + +@if defined(TRICORE_V2) +off0811pc4z16: reloc is PCPMode=0 & op0811 [ reloc = inst_start + ((op0811 + 16) * 2); ] { export *[ram]:4 reloc; } +@endif + +const0607Z: "#"^op0607 is PCPMode=0 & op0607 { local tmp:4 = op0607; export tmp; } + +const0810Z: "#"^op0810 is PCPMode=0 & op0810 { local tmp:4 = op0810; export tmp; } + +const0811Z6zz: "#"^reloc is PCPMode=0 & op0811 [ reloc = op0811 << 2; ] { local tmp:4 = reloc; export tmp; } + +const0811Z: "#"^op0811 is PCPMode=0 & op0811 { local tmp:4 = op0811; export tmp; } + +const0811Z5z: "#"^reloc is PCPMode=0 & op0811 [ reloc = op0811 << 1; ] { local tmp:4 = reloc; export tmp; } + +const0815Z: "#"^op0815 is PCPMode=0 & op0815 { local tmp:4 = op0815; export tmp; } + +const0815Z10zz: "#"^reloc is PCPMode=0 & op0815 [ reloc = op0815 << 2; ] { local tmp:4 = reloc; export tmp; } + +const1111Z: "#"^op1111 is PCPMode=0 & op1111 { local tmp:4 = op1111; export tmp; } + +const1215S: "#"^sop1215 is PCPMode=0 & sop1215 { local tmp:4 = sop1215; export tmp; } + +const1215Z: "#"^op1215 is PCPMode=0 & op1215 { local tmp:4 = op1215; export tmp; } + +const1215Z6zz: "#"^reloc is PCPMode=0 & op1215 [ reloc = op1215 << 2; ] { local tmp:4 = reloc; export tmp; } + +const1215Z5z: "#"^reloc is PCPMode=0 & op1215 [ reloc = op1215 << 1; ] { local tmp:4 = reloc; export tmp; } + +const1220S: "#"^reloc is PCPMode=0 & op1215 ; sop1620 [ reloc = (sop1620 << 4) | op1215; ] { local tmp:4 = reloc; export tmp; } + +const1220Z: "#"^reloc is PCPMode=0 & op1215 ; op1620 [ reloc = (op1620 << 4) | op1215; ] { local tmp:4 = reloc; export tmp; } + +const1227S: "#"^reloc is PCPMode=0 & op1215 ; sop1627 [ reloc = (sop1627 << 4) | op1215; ] { local tmp:4 = reloc; export tmp; } + +const1227Z: "#"^reloc is PCPMode=0 & op1215 ; op1627 [ reloc = (op1627 << 4) | op1215; ] { local tmp:4 = reloc; export tmp; } + +const1617Z: "#"^op1617 is PCPMode=0 & op1617 { local tmp:4 = op1617; export tmp; } + +const1620Z: "#"^op1620 is PCPMode=0 & op1620 { local tmp:4 = op1620; export tmp; } + +const2327Z: "#"^op2327 is PCPMode=0 & op2327 { local tmp:4 = op2327; export tmp; } + +Nbit: "#"^reloc is PCPMode=0 & op0707 & op1215 [ reloc = (op0707 << 4) | op1215; ] { local tmp:4 = reloc; export tmp; } + + + +#TODO circular is seems too compilcated to do this way +#BO: [Rpe1215/Rpo1215^"+c"^]off10 is PCPMode=0 & Rpe1215 & Rpo1215 & op0003=9 & op0405=2 ; off10 & op2627=1 { local EA:4; CircularAddressingMode(Rpe1215, Rpo1215, EA, off10); export EA; } + + +BO: [Rpe1215/Rpo1215^"+r"^] is PCPMode=0 & Rpe1215 & Rpo1215 & op0003=9 & op0405=2 ; op1621=0x0 & op2627=0 & op2831=0x0 { local EA:4; BitReverseAddressingMode(Rpe1215, Rpo1215, EA); export EA; } + +BO: [Rpe1215/Rpo1215^"+i"^] is PCPMode=0 & Rpe1215 & Rpo1215 & op0003=9 & op0405=2 ; op1621=0x0 & op2627=2 & op2831=0x0 { local EA:4; IndexAddressingMode(Rpe1215, Rpo1215, EA); export EA; } + +BO: [Ra1215]off10 is PCPMode=0 & Ra1215 & op0003=9 & op0405=0 ; off10 & op2627=2 { local EA = Ra1215 + off10; export EA; } + +BO: [Ra1215+]off10 is PCPMode=0 & Ra1215 & op0003=9 & op0405=0 ; off10 & op2627=0 { local EA = Ra1215; Ra1215 = Ra1215 + off10; export EA; } + +BO: [+Ra1215]off10 is PCPMode=0 & Ra1215 & op0003=9 & op0405=0 ; off10 & op2627=1 { Ra1215 = Ra1215 + off10; local EA = Ra1215; export EA; } + + +BOL: [Ra1215]off16 is PCPMode=0 & Ra1215 ; off16 { local EA = Ra1215 + off16; export EA; } + + +SSR: [Ra1215] is PCPMode=0 & Ra1215 & op0003=4 & op0405=3 { local EA = Ra1215; export EA; } + +SSR: [Ra1215+] is PCPMode=0 & Ra1215 & op0003=4 & op0405=2 & op0606=1 { local EA = Ra1215; Ra1215 = Ra1215 + 4; export EA; } + +SSR: [Ra1215+] is PCPMode=0 & Ra1215 & op0003=4 & op0405=2 & op0606=0 & op0707=1 { local EA = Ra1215; Ra1215 = Ra1215 + 2; export EA; } + +SSR: [Ra1215+] is PCPMode=0 & Ra1215 & op0003=4 & op0405=2 & op0606=0 & op0707=0 { local EA = Ra1215; Ra1215 = Ra1215 + 1; export EA; } + + +SLR: [Ra1215] is PCPMode=0 & Ra1215 & op0003=4 & op0405=1 { local EA = Ra1215; export EA; } + +SLR: [Ra1215+] is PCPMode=0 & Ra1215 & op0003=4 & op0405=0 & op0606=1 { local EA = Ra1215; Ra1215 = Ra1215 + 4; export EA; } + +SLR: [Ra1215+] is PCPMode=0 & Ra1215 & op0003=4 & op0405=0 & op0606=0 & op0707=1 { local EA = Ra1215; Ra1215 = Ra1215 + 2; export EA; } + +SLR: [Ra1215+] is PCPMode=0 & Ra1215 & op0003=4 & op0405=0 & op0606=0 & op0707=0 { local EA = Ra1215; Ra1215 = Ra1215 + 1; export EA; } + + +SRO: [Ra1215]const0811Z is PCPMode=0 & Ra1215 & const0811Z & op0003=0xc & op0404=0 & op0607=0 { local EA = Ra1215 + const0811Z; export EA; } + +SRO: [Ra1215]const0811Z5z is PCPMode=0 & Ra1215 & const0811Z5z & op0003=0xc & op0404=0 & op0607=2 { local EA = Ra1215 + const0811Z5z; export EA; } + +SRO: [Ra1215]const0811Z6zz is PCPMode=0 & Ra1215 & const0811Z6zz & op0003=0xc & op0404=0 & op0606=1 { local EA = Ra1215 + const0811Z6zz; export EA; } + + +SLRO: [a15]const1215Z is PCPMode=0 & a15 & const1215Z & op0003=8 & op0405=0 & op0607=0 { local EA = a15 + const1215Z; export EA; } + +SLRO: [a15]const1215Z5z is PCPMode=0 & a15 & const1215Z5z & op0003=8 & op0405=0 & op0607=2 { local EA = a15 + const1215Z5z; export EA; } + +SLRO: [a15]const1215Z6zz is PCPMode=0 & a15 & const1215Z6zz & op0003=8 & op0405=0 & op0606=1 { local EA = a15 + const1215Z6zz; export EA; } + + +SSRO: [a15]const1215Z is PCPMode=0 & a15 & const1215Z & op0003=8 & op0405=2 & op0607=0 { local EA = a15 + const1215Z; export EA; } + +SSRO: [a15]const1215Z5z is PCPMode=0 & a15 & const1215Z5z & op0003=8 & op0405=2 & op0607=2 { local EA = a15 + const1215Z5z; export EA; } + +SSRO: [a15]const1215Z6zz is PCPMode=0 & a15 & const1215Z6zz & op0003=8 & op0405=2 & op0606=1 { local EA = a15 + const1215Z6zz; export EA; } + + +SC: [a10]const0815Z10zz is PCPMode=0 & a10 & const0815Z10zz & op0003=8 & op0404=1 & op0606=1 { local EA = a10 + const0815Z10zz; export EA; } + + + +# ABS D[c], D[b] (RR) +:abs Rd2831,Rd1215 is PCPMode=0 & Rd1215 & op0007=0xb & op0811=0 ; Rd2831 & op1627=0x1c0 +{ + int_abs(Rd2831, Rd1215); + overflowflags(Rd2831); +} + +# ABS.B D[c], D[b] (RR) +:abs.b Rd2831,Rd1215 is PCPMode=0 & Rd1215 & op0007=0xb & op0811=0 ; Rd2831 & op1627=0x5c0 +{ + local result3:1; int_abs1(result3, Rd1215[24,8]); + local result2:1; int_abs1(result2, Rd1215[16,8]); + local result1:1; int_abs1(result1, Rd1215[8,8]); + local result0:1; int_abs1(result0, Rd1215[0,8]); + overflowflagsb(result3, result2, result1, result0); + Rd2831[24,8] = result3; + Rd2831[16,8] = result2; + Rd2831[8,8] = result1; + Rd2831[0,8] = result0; +} + +# ABS.H D[c], D[b] (RR) +:abs.h Rd2831,Rd1215 is PCPMode=0 & Rd1215 & op0007=0xb & op0811=0 ; Rd2831 & op1627=0x7c0 +{ + local result1:2; int_abs(result1, Rd1215[16,16]); + local result0:2; int_abs(result0, Rd1215[0,16]); + overflowflagsh(result1, result0); + Rd2831[16,16] = result1; + Rd2831[0,16] = result0; +} + +# ABSDIF D[c], D[a], D[b] (RR) +:absdif Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0xe0 +{ + int_abs(Rd2831, Rd0811 - Rd1215); + overflowflags(Rd2831); +} + +# ABSDIF D[c], D[a], const9 (RC) +:absdif Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0xe ) & const1220S +{ + int_abs(Rd2831, Rd0811 - const1220S); + overflowflags(Rd2831); +} + +# ABSDIF.B D[c], D[a], D[b] (RR) +:absdif.b Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x4e0 +{ + local result3:1; int_abs1(result3, (Rd0811[24,8] - Rd1215[24,8])); + local result2:1; int_abs1(result2, (Rd0811[16,8] - Rd1215[16,8])); + local result1:1; int_abs1(result1, (Rd0811[8,8] - Rd1215[8,8])); + local result0:1; int_abs1(result0, (Rd0811[0,8] - Rd1215[0,8])); + overflowflagsb(result3, result2, result1, result0); + Rd2831[24,8] = result3; + Rd2831[16,8] = result2; + Rd2831[8,8] = result1; + Rd2831[0,8] = result0; +} + +# ABSDIF.H D[c], D[a], D[b] (RR) +:absdif.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x6e0 +{ + local result1:2; int_abs(result1, (Rd0811[16,16] - Rd1215[16,16])); + local result0:2; int_abs(result0, (Rd0811[0,16] - Rd1215[16,16])); + overflowflagsh(result1, result0); + Rd2831[16,16] = result1; + Rd2831[0,16] = result0; +} + +# ABSDIFS D[c], D[a], D[b] (RR) +:absdifs Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0xf0 +{ + local result:4; int_abs(result, (Rd0811 - Rd1215)); + overflowflags(result); + ssov(Rd2831, result, 32); +} + +# ABSDIFS D[c], D[a], const9 (RC) +:absdifs Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0xf ) & const1220S +{ + local result:4; int_abs(result, (Rd0811 - const1220S)); + overflowflags(result); + ssov(Rd2831, result, 32); +} + +# ABSDIFS.H D[c], D[a], D[b] (RR) +:absdifs.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x6f0 +{ + local result1:2; int_abs(result1, (Rd0811[16,16] - Rd1215[16,16])); + local result0:2; int_abs(result0, (Rd0811[0,16] - Rd1215[16,16])); + overflowflagsh(result1, result0); + ssov(Rd2831[16,16], result1, 16); + ssov(Rd2831[0,16], result0, 16); +} + +# ABSS D[c], D[b] (RR) +:abss Rd2831,Rd1215 is PCPMode=0 & Rd1215 & op0007=0xb & op0811=0 ; Rd2831 & op1627=0x1d0 +{ + local result:4; int_abs(result, Rd1215); + overflowflags(result); + ssov(Rd2831, result, 32); +} + +# ABSS.H D[c], D[b] (RR) +:abss.h Rd2831,Rd1215 is PCPMode=0 & Rd1215 & op0007=0xb & op0811=0 ; Rd2831 & op1627=0x7d0 +{ + local result1:2; int_abs(result1, Rd1215[16,16]); + local result0:2; int_abs(result0, Rd1215[0,16]); + overflowflagsh(result1, result0); + ssov(Rd2831[16,16], result1, 16); + ssov(Rd2831[0,16], result0, 16); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# ADD D[a], D[15], D[b] (SRR) +:add Rd0811,d15,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & d15 & op0007=0x12 +{ + Rd0811 = d15 + Rd1215; + overflowflags(Rd0811); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# ADD D[a], D[15], const4 (SRC) +:add Rd0811,d15,const1215S is PCPMode=0 & Rd0811 & const1215S & d15 & op0007=0x92 +{ + Rd0811 = d15 + const1215S; + overflowflags(Rd0811); +} +@endif + +# ADD D[15], D[a], D[b] (SRR) +:add d15,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & d15 & op0007=0x1a +{ + d15 = Rd0811 + Rd1215; + overflowflags(d15); +} + +# ADD D[a], D[b] (SRR) +:add Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x42 +{ + Rd0811 = Rd0811 + Rd1215; + overflowflags(Rd0811); +} + +# ADD D[15], D[a], const4 (SRC) +:add d15,Rd0811,const1215S is PCPMode=0 & Rd0811 & const1215S & d15 & op0007=0x9a +{ + d15 = Rd0811 + const1215S; + overflowflags(d15); +} + +# ADD D[a], const4 (SRC) +:add Rd0811,const1215S is PCPMode=0 & Rd0811 & const1215S & op0007=0xc2 +{ + Rd0811 = Rd0811 + const1215S; + overflowflags(Rd0811); +} + +# ADD D[c], D[a], D[b] (RR) +:add Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x0 +{ + Rd2831 = Rd0811 + Rd1215; + overflowflags(Rd2831); +} + +# ADD D[c], D[a], const9 (RC) +:add Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x0 ) & const1220S +{ + Rd2831 = Rd0811 + const1220S; + overflowflags(Rd2831); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# ADD.A A[a], A[b] (SRR) +:add.a Ra0811,Ra1215 is PCPMode=0 & Ra0811 & Ra1215 & op0007=0x30 +{ + Ra0811 = Ra0811 + Ra1215; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# ADD.A A[a], const4 (SRC) +:add.a Ra0811,const1215S is PCPMode=0 & Ra0811 & const1215S & op0007=0xb0 +{ + Ra0811 = Ra0811 + const1215S; +} +@endif + +# ADD.A A[c], A[a], A[b] (RR) +:add.a Ra2831,Ra0811,Ra1215 is PCPMode=0 & Ra0811 & Ra1215 & op0007=0x1 ; Ra2831 & op1627=0x10 +{ + Ra2831 = Ra0811 + Ra1215; +} + +# ADD.B D[c], D[a], D[b] (RR) +:add.b Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x400 +{ + local result3:4 = zext(Rd0811[24,8] + Rd1215[24,8]); + local result2:4 = zext(Rd0811[16,8] + Rd1215[16,8]); + local result1:4 = zext(Rd0811[8,8] + Rd1215[8,8]); + local result0:4 = zext(Rd0811[0,8] + Rd1215[0,8]); + overflowflagsb(result3, result2, result1, result0); + Rd2831[24,8] = result3[0,8]; + Rd2831[16,8] = result2[0,8]; + Rd2831[8,8] = result1[0,8]; + Rd2831[0,8] = result0[0,8]; +} + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# ADD.F D[c], D[d], D[a] (RRR) +:add.f Rd2831,Rd2427,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x6b & op1215=0x0 ; Rd2427 & Rd2831 & op1623=0x21 +{ + #TODO float + #TODO flags + Rd2831 = Rd2427 f+ Rd0811; +} +@endif + +# ADD.H D[c], D[a], D[b] (RR) +:add.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x600 +{ + local result1:4 = zext(Rd0811[16,16] + Rd1215[16,16]); + local result0:4 = zext(Rd0811[0,16] + Rd1215[0,16]); + overflowflagsh(result1, result0); + Rd2831[16,16] = result1[0,16]; + Rd2831[0,16] = result0[0,16]; +} + +# ADDC D[c], D[a], D[b] (RR) +:addc Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x50 +{ + local tmp:5 = zext(Rd0811) + zext(Rd1215) + zext($(PSW_C)); + Rd2831 = tmp[0,32]; + $(PSW_C) = tmp[32,1]; + overflowflags(Rd2831); +} + +# ADDC D[c], D[a], const9 (RC) +:addc Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x5 ) & const1220S +{ + local tmp:5 = zext(Rd0811) + zext(const1220S) + zext($(PSW_C)); + Rd2831 = tmp[0,32]; + $(PSW_C) = tmp[32,1]; + overflowflags(Rd2831); +} + +# ADDI D[c], D[a], const16 (RLC) +:addi Rd2831,Rd0811,const1227S is PCPMode=0 & ( Rd0811 & op0007=0x1b ; Rd2831 ) & const1227S +{ + Rd2831 = Rd0811 + const1227S; + overflowflags(Rd2831); +} + +# ADDIH D[c], D[a], const16 (RLC) +:addih Rd2831,Rd0811,const1227Z is PCPMode=0 & ( Rd0811 & op0007=0x9b ; Rd2831 ) & const1227Z +{ + Rd2831 = Rd0811 + (const1227Z << 16); + overflowflags(Rd2831); +} + +# ADDIH.A A[c], A[a], const16 (RLC) +:addih.a Ra2831,Ra0811,const1227Z is PCPMode=0 & ( Ra0811 & op0007=0x11 ; Ra2831 ) & const1227Z +{ + Ra2831 = Ra0811 + (const1227Z << 16); +} + +# ADDS D[a], D[b], (SRR) +:adds Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x22 +{ + local result:4 = Rd0811 + Rd1215; + overflowflags(result); + ssov(Rd0811, result, 32); +} + +# ADDS D[c], D[a], D[b] (RR) +:adds Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x20 +{ + local result:4 = Rd0811 + Rd1215; + overflowflags(result); + ssov(Rd2831, result, 32); +} + +# ADDS D[c], D[a], const9 (RC) +:adds Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x2 ) & const1220S +{ + local result:4 = Rd0811 + const1220S; + overflowflags(result); + ssov(Rd2831, result, 32); +} + +# ADDS.H D[c], D[a], D[b] (RR) +:adds.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x620 +{ + local result1:4 = sext(Rd0811[16,16] + Rd1215[16,16]); + local result0:4 = sext(Rd0811[0,16] + Rd1215[0,16]); + overflowflagsh(result1, result0); + ssov(Rd2831[16,16], result1[0,16], 16); + ssov(Rd2831[0,16], result0[0,16], 16); +} + +# ADDS.HU D[c], D[a], D[b] (RR) +:adds.hu Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x630 +{ + local result1:4 = sext(Rd0811[16,16] + Rd1215[16,16]); + local result0:4 = sext(Rd0811[0,16] + Rd1215[0,16]); + overflowflagsh(result1, result0); + suov(Rd2831[16,16], result1[0,16], 16); + suov(Rd2831[0,16], result0[0,16], 16); +} + +# ADDS.U D[c], D[a], D[b] (RR) +:adds.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x30 +{ + local result:4 = Rd0811 + Rd1215; + overflowflags(result); + suov(Rd2831, result, 32); +} + +# ADDS.U D[c], D[a], const9 (RC) +:adds.u Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x3 ) & const1220S +{ + local result:4 = Rd0811 + const1220S; + overflowflags(result); + suov(Rd2831, result, 32); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# ADDSC.A A[a], A[b], D[15], n (SRRS) +:addsc.a Ra0811,Ra1215,d15,const0607Z is PCPMode=0 & Ra0811 & Ra1215 & const0607Z & d15 & op0005=0x10 +{ + Ra0811 = Ra1215 + (d15 << const0607Z); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# ADDSC.A A[c], A[b], D[a], n (RR) +:addsc.a Ra2831,Ra1215,Rd0811,const1617Z is PCPMode=0 & Ra1215 & Rd0811 & op0007=0x1 ; Ra2831 & const1617Z & op1827=0x180 +{ + Ra2831 = Ra1215 + (Rd0811 << const1617Z); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# ADDSC.AT A[c], A[b], D[a] (RR) +:addsc.at Ra2831,Ra1215,Rd0811 is PCPMode=0 & Ra1215 & Rd0811 & op0007=0x1 ; Ra2831 & op1627=0x620 +{ + Ra2831 = (Ra1215 + (Rd0811 >> 3)) & 0xFFFFFFFC; +} +@endif + +# ADDX D[c], D[a], D[b] (RR) +:addx Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x40 +{ + local result:4 = Rd0811 + Rd1215; + $(PSW_C) = carry(Rd0811, Rd1215); + overflowflags(result); + Rd2831 = result; +} + +# ADDX D[c], D[a], const9 (RC) +:addx Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x4 ) & const1220S +{ + local result:4 = Rd0811 + const1220S; + $(PSW_C) = carry(Rd0811, const1220S); + overflowflags(result); + Rd2831 = result; +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# AND D[a], D[b] (SRR) +:and Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x26 +{ + Rd0811 = Rd0811 & Rd1215; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# AND D[15], const8 (SC) +:and d15,const0815Z is PCPMode=0 & const0815Z & d15 & op0007=0x16 +{ + d15 = d15 & const0815Z; +} +@endif + +# AND D[c], D[a], D[b] (RR) +:and Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0x80 +{ + Rd2831 = Rd0811 & Rd1215; +} + +# AND D[c], D[a], const9 (RC) +:and Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0x8 ) & const1220Z +{ + Rd2831 = Rd0811 & const1220Z; +} + +# AND.AND.T D[c], D[a], pos1, D[b], pos2 (BIT) +:and.and.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x47 ; Rd2831 & const1620Z & const2327Z & op2122=0x0 +{ + local tmpa = (Rd0811 >> const1620Z) & 1; + local tmpb = (Rd1215 >> const2327Z) & 1; + Rd2831[0,1] = Rd2831[0,1] & (tmpa[0,1] & tmpb[0,1]); +} + +# AND.ANDN.T D[c], D[a,] pos1, D[b], pos2 (BIT) +:and.andn.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x47 ; Rd2831 & const1620Z & const2327Z & op2122=0x3 +{ + local tmpa = (Rd0811 >> const1620Z) & 1; + local tmpb = (Rd1215 >> const2327Z) & 1; + Rd2831[0,1] = Rd2831[0,1] & (tmpa[0,1] & ~tmpb[0,1]); +} + +# AND.EQ D[c], D[a], D[b] (RR) +:and.eq Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x200 +{ + Rd2831[0,1] = Rd2831[0,1] & (Rd0811 == Rd1215); +} + +# AND.EQ D[c], D[a], const9 (RC) +:and.eq Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x20 ) & const1220S +{ + Rd2831[0,1] = Rd2831[0,1] & (Rd0811 == const1220S); +} + +# AND.GE D[c], D[a], D[b] (RR) +:and.ge Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x240 +{ + Rd2831[0,1] = Rd2831[0,1] & (Rd0811 s>= Rd1215); +} + +# AND.GE D[c], D[a], const9 (RC) +:and.ge Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x24 ) & const1220S +{ + Rd2831[0,1] = Rd2831[0,1] & (Rd0811 s>= const1220S); +} + +# AND.GE.U D[c], D[a], D[b] (RR) +:and.ge.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x250 +{ + Rd2831[0,1] = Rd2831[0,1] & (Rd0811 >= Rd1215); +} + +# AND.GE.U D[c], D[a], const9 (RC) +:and.ge.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x25 ) & const1220Z +{ + Rd2831[0,1] = Rd2831[0,1] & (Rd0811 >= const1220Z); +} + +# AND.LT D[c], D[a], D[b] (RR) +:and.lt Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x220 +{ + Rd2831[0,1] = Rd2831[0,1] & (Rd0811 s< Rd1215); +} + +# AND.LT D[c], D[a], const9 (RC) +:and.lt Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x22 ) & const1220S +{ + Rd2831[0,1] = Rd2831[0,1] & (Rd0811 s< const1220S); +} + +# AND.LT.U D[c], D[a], D[b] (RR) +:and.lt.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x230 +{ + Rd2831[0,1] = Rd2831[0,1] & (Rd0811 < Rd1215); +} + +# AND.LT.U D[c], D[a], const9 (RC) +:and.lt.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x23 ) & const1220Z +{ + Rd2831[0,1] = Rd2831[0,1] & (Rd0811 < const1220Z); +} + +# AND.NE D[c], D[a], D[b] (RR) +:and.ne Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x210 +{ + Rd2831[0,1] = Rd2831[0,1] & (Rd0811 != Rd1215); +} + +# AND.NE D[c], D[a], const9 (RC) +:and.ne Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x21 ) & const1220S +{ + Rd2831[0,1] = Rd2831[0,1] & (Rd0811 != const1220S); +} + +# AND.NOR.T D[c], D[a], pos1, D[b], pos2 (BIT) +:and.nor.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x47 ; Rd2831 & const1620Z & const2327Z & op2122=0x2 +{ + local tmpa = (Rd0811 >> const1620Z) & 1; + local tmpb = (Rd1215 >> const2327Z) & 1; + Rd2831[0,1] = Rd2831[0,1] & !(tmpa[0,1] | tmpb[0,1]); +} + +# AND.OR.T D[c], D[a], pos1, D[b], pos2 (BIT) +:and.or.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x47 ; Rd2831 & const1620Z & const2327Z & op2122=0x1 +{ + local tmpa = (Rd0811 >> const1620Z) & 1; + local tmpb = (Rd1215 >> const2327Z) & 1; + Rd2831[0,1] = Rd2831[0,1] & (tmpa[0,1] | tmpb[0,1]); +} + +# AND.T D[c], D[a], pos1, D[b], pos2 (BIT) +:and.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x87 ; Rd2831 & const1620Z & const2327Z & op2122=0x0 +{ + local tmpa = (Rd0811 >> const1620Z) & 1; + local tmpb = (Rd1215 >> const2327Z) & 1; + Rd2831 = zext(tmpa[0,1] & tmpb[0,1]); +} + +# ANDN D[c], D[a], D[b] (RR) +:andn Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0xe0 +{ + Rd2831 = Rd0811 & ~Rd1215; +} + +# ANDN D[c], D[a], const9 (RC) +:andn Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0xe ) & const1220Z +{ + Rd2831 = Rd0811 & ~const1220Z; +} + +# ANDN.T D[c], D[a], pos1, D[b], pos2 (BIT) +:andn.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x87 ; Rd2831 & const1620Z & const2327Z & op2122=0x3 +{ + local tmpa = (Rd0811 >> const1620Z) & 1; + local tmpb = (Rd1215 >> const2327Z) & 1; + Rd2831 = zext(tmpa[0,1] & !tmpb[0,1]); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# BISR const8 (SC) +:bisr const0815Z is PCPMode=0 & const0815Z & op0007=0xe0 +{ + #TODO isr + # tmp_FCX = FCX; + # if (FCX == 0) trap(FCU); + # EA = {FCX.FCXS, 6'b0, FCX.FCXO, 6'b0}; + # new_FCX = M(EA, word); + # M(EA,16 * word) = {PCXI, a11, a2, a3, d0, d1, d2, d3, a4, a5, a6, a7, d4, d5, d6, d7}; + # PCXI.PCPN = ICR.CCPN; + # PCXI.PIE = ICR.IE; + # PCXI.UL = 0; + # PCXI[19:0] = FCX[19:0]; + # FCX[19:0] = new_FCX[19:0]; + # ICR.IE = 1; + # ICR.CCPN = const8; + # if (tmp_FCX == LCX) trap(FCD); +} +@endif + +# BISR const9 (RC) +:bisr const1220Z is PCPMode=0 & ( op0007=0xad & op0811=0x0 ; op2131=0x0 ) & const1220Z +{ + #TODO isr + # if (FCX == 0) trap(FCU); + # tmp_FCX = FCX; + # EA = {FCX.FCXS, 6'b0, FCX.FCXO, 6'b0}; + # new_FCX = M(EA, word); + # M(EA,16 * word) = {PCXI, a11, a2, a3, d0, d1, d2, d3, a4, a5, a6, a7, d4, d5, d6, d7}; + # PCXI.PCPN = ICR.CCPN; + # PCXI.PIE = ICR.IE; + # PCXI.UL = 0; + # PCXI[19:0] = FCX[19:0]; + # FCX[19:0] = new_FCX[19:0]; + # ICR.IE = 1; + # ICR.CCPN = const9[7:0]; + # if (tmp_FCX == LCX) trap(FCD); +} + + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# BMERGE D[c], D[a], D[b] (RR) +:bmerge Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Rd2831 & op1627=0x10 +{ +@if defined(TRICORE_VERBOSE) + Rd2831[31,1] = Rd0811[15,1]; + Rd2831[30,1] = Rd1215[15,1]; + Rd2831[29,1] = Rd0811[14,1]; + Rd2831[28,1] = Rd1215[14,1]; + Rd2831[27,1] = Rd0811[13,1]; + Rd2831[26,1] = Rd1215[13,1]; + Rd2831[25,1] = Rd0811[12,1]; + Rd2831[24,1] = Rd1215[12,1]; + Rd2831[23,1] = Rd0811[11,1]; + Rd2831[22,1] = Rd1215[11,1]; + Rd2831[21,1] = Rd0811[10,1]; + Rd2831[20,1] = Rd1215[10,1]; + Rd2831[19,1] = Rd0811[9,1]; + Rd2831[18,1] = Rd1215[9,1]; + Rd2831[17,1] = Rd0811[8,1]; + Rd2831[16,1] = Rd1215[8,1]; + Rd2831[15,1] = Rd0811[7,1]; + Rd2831[14,1] = Rd1215[7,1]; + Rd2831[13,1] = Rd0811[6,1]; + Rd2831[12,1] = Rd1215[6,1]; + Rd2831[11,1] = Rd0811[5,1]; + Rd2831[10,1] = Rd1215[5,1]; + Rd2831[9,1] = Rd0811[4,1]; + Rd2831[8,1] = Rd1215[4,1]; + Rd2831[7,1] = Rd0811[3,1]; + Rd2831[6,1] = Rd1215[3,1]; + Rd2831[5,1] = Rd0811[2,1]; + Rd2831[4,1] = Rd1215[2,1]; + Rd2831[3,1] = Rd0811[1,1]; + Rd2831[2,1] = Rd1215[1,1]; + Rd2831[1,1] = Rd0811[0,1]; + Rd2831[0,1] = Rd1215[0,1]; +@else + bmerge(Rd2831,Rd0811,Rd1215); +@endif +} +@endif + + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# BSPLIT E[c], D[a] (RR) +:bsplit Re2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; Re2831 & op1627=0x90 +{ +@if defined(TRICORE_VERBOSE) + Re2831[48,16] = 0; + Re2831[47,1] = Rd0811[31,1]; + Re2831[46,1] = Rd0811[29,1]; + Re2831[45,1] = Rd0811[27,1]; + Re2831[44,1] = Rd0811[25,1]; + Re2831[43,1] = Rd0811[23,1]; + Re2831[42,1] = Rd0811[21,1]; + Re2831[41,1] = Rd0811[19,1]; + Re2831[40,1] = Rd0811[17,1]; + Re2831[39,1] = Rd0811[15,1]; + Re2831[38,1] = Rd0811[13,1]; + Re2831[37,1] = Rd0811[11,1]; + Re2831[36,1] = Rd0811[9,1]; + Re2831[35,1] = Rd0811[7,1]; + Re2831[34,1] = Rd0811[5,1]; + Re2831[33,1] = Rd0811[3,1]; + Re2831[32,1] = Rd0811[1,1]; + Re2831[16,16] = 0; + Re2831[15,1] = Rd0811[30,1]; + Re2831[14,1] = Rd0811[28,1]; + Re2831[13,1] = Rd0811[26,1]; + Re2831[12,1] = Rd0811[24,1]; + Re2831[11,1] = Rd0811[22,1]; + Re2831[10,1] = Rd0811[20,1]; + Re2831[9,1] = Rd0811[18,1]; + Re2831[8,1] = Rd0811[16,1]; + Re2831[7,1] = Rd0811[14,1]; + Re2831[6,1] = Rd0811[12,1]; + Re2831[5,1] = Rd0811[10,1]; + Re2831[4,1] = Rd0811[8,1]; + Re2831[3,1] = Rd0811[6,1]; + Re2831[2,1] = Rd0811[4,1]; + Re2831[1,1] = Rd0811[2,1]; + Re2831[0,1] = Rd0811[0,1]; +@else + bsplit(Re2831,Rd0811); +@endif +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# CACHEA.I A[b], off10 (BO) (Post-increment Addressing Mode) +# CACHEA.I P[b] (BO) (Bit Reverse Addressing Mode) +# CACHEA.I A[b], off10 (BO) (Pre-increment Addressing Mode) +# CACHEA.I A[b], off10 (BO) (Base + Short Offset Addressing Mode) +# CACHEA.I P[b] (BO) (Index Addressing Mode) +:cachea.i BO is PCPMode=0 & ( op0607=0x2 & op0811=0x0 ; op2225=0xe ) & BO +{ + build BO; + cache_address_ivld(BO); +} + +# CACHEA.I P[b], off10 (BO) (Circular Addressing Mode) +#:cachea.i BO is PCPMode=0 & ( op0007=0xa9 & op0811=0x0 ; op2227=0x1e ) & BO +:cachea.i [Rpe1215/Rpo1215^"+c"^]off10 is PCPMode=0 & Rpe1215 & Rpo1215 & op0007=0xa9 & op0811=0x0 ; off10 & op2227=0x1e +{ + local EA:4; + CircularAddressingMode(Rpe1215, Rpo1215, EA, off10); + cache_address_ivld(EA); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# CACHEA.W A[b], off10 (BO) (Post-increment Addressing Mode) +# CACHEA.W P[b] (BO) (Bit-reverse Addressing Mode) +# CACHEA.W A[b], off10 (BO) (Pre-increment Addressing Mode) +# CACHEA.W A[b], off10 (BO) (Base + Short Offset Addressing Mode) +# CACHEA.W P[b] (BO) (Index Addressing Mode) +:cachea.w BO is PCPMode=0 & ( op0607=0x2 & op0811=0x0 ; op2225=0xc ) & BO +{ + build BO; + cache_address_wb(BO); +} + +# CACHEA.W P[b], off10 (BO)(Circular Addressing Mode) +#:cachea.w BO is PCPMode=0 & ( op0007=0xa9 & op0811=0x0 ; op2227=0x1c ) & BO +:cachea.w [Rpe1215/Rpo1215^"+c"^]off10 is PCPMode=0 & Rpe1215 & Rpo1215 & op0007=0xa9 & op0811=0x0 ; off10 & op2227=0x1c +{ + local EA:4; + CircularAddressingMode(Rpe1215, Rpo1215, EA, off10); + cache_address_wb(EA); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# CACHEA.WI A[b], off10 (BO)(Post-increment Addressing Mode) +# CACHEA.WI P[b] (BO)(Bit-reverse Addressing Mode) +# CACHEA.WI A[b], off10 (BO)(Pre-increment Addressing Mode) +# CACHEA.WI A[b], off10 (BO)(Base + Short Offset Addressing Mode) +# CACHEA.WI P[b] (BO)(Index Addressing Mode) +:cachea.wi BO is PCPMode=0 & ( op0607=0x2 & op0811=0x0 ; op2225=0xd ) & BO +{ + build BO; + cache_address_wi(BO); +} + +# CACHEA.WI P[b], off10 (BO) (Circular Addressing Mode) +#:cachea.wi BO is PCPMode=0 & ( op0007=0xa9 & op0811=0x0 ; op2227=0x1d ) & BO +:cachea.wi [Rpe1215/Rpo1215^"+c"^]off10 is PCPMode=0 & Rpe1215 & Rpo1215 & op0007=0xa9 & op0811=0x0 ; off10 & op2227=0x1d +{ + local EA:4; + CircularAddressingMode(Rpe1215, Rpo1215, EA, off10); + cache_address_wi(EA); +} +@endif + +@if defined(TRICORE_V2) +# CACHEI.I A[b], off10 (BO)(Post-increment Addressing Mode) +# CACHEI.I A[b], off10 (BO)(Pre-increment Addressing Mode) +# CACHEI.I A[b], off10 (BO)(Base + Short Offset Addressing Mode) +:cachei.i BO is PCPMode=0 & ( op0407=0x8 & op0811=0x0 ; op2225=0xa ) & BO +{ + build BO; + cache_index_ivld(BO); +} +@endif + +@if defined(TRICORE_V2) +# CACHEI.W A[b], off10 (BO)(Post-increment Addressing Mode) +# CACHEI.W A[b], off10 (BO)(Pre-increment Addressing Mode) +# CACHEI.W A[b], off10 (BO)(Base + Short Offset Addressing Mode) +:cachei.w BO is PCPMode=0 & ( op0407=0x8 & op0811=0x0 ; op2225=0xb ) & BO +{ + build BO; + cache_index_wb(BO); +} +@endif + +@if defined(TRICORE_V2) +# CACHEI.WI A[b], off10 (BO)(Post-increment Addressing Mode) +# CACHEI.WI A[b], off10 (BO)(Pre-increment Addressing Mode) +# CACHEI.WI A[b], off10 (BO)(Base + Short Offset Addressing Mode) +:cachei.wi BO is PCPMode=0 & ( op0407=0x8 & op0811=0x0 ; op2225=0xf ) & BO +{ + build BO; + cache_index_wi(BO); +} +@endif + +# CADD D[a], D[15], const4 (SRC) +:cadd Rd0811,d15,const1215S is PCPMode=0 & Rd0811 & const1215S & d15 & op0007=0x8a +{ + local result:4; + ternary(result, d15 != 0, Rd0811 + const1215S, Rd0811); + overflowflags(result); + Rd0811 = result; +} + +# CADD D[c], D[d], D[a], D[b] (RRR) +:cadd Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x2b ; Rd2427 & Rd2831 & op1623=0x0 +{ + local result:4; + ternary(result, Rd2427 != 0, Rd0811 + Rd1215, Rd0811); + overflowflags(result); + Rd2831 = result; +} + +# CADD D[c], D[d], D[a], const9 (RCR) +:cadd Rd2831,Rd2427,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0xab ; Rd2427 & Rd2831 & op2123=0x0 ) & const1220S +{ + local result:4; + ternary(result, Rd2427 != 0, Rd0811 + const1220S, Rd0811); + overflowflags(result); + Rd2831 = result; +} + +# CADDN D[a], D[15], const4 (SRC) +:caddn Rd0811,d15,const1215S is PCPMode=0 & Rd0811 & const1215S & d15 & op0007=0xca +{ + local result:4; + ternary(result, d15 == 0, Rd0811 + const1215S, Rd0811); + overflowflags(result); + Rd0811 = result; +} + +# CADDN D[c], D[d], D[a], D[b] (RRR) +:caddn Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x2b ; Rd2427 & Rd2831 & op1623=0x10 +{ + local result:4; + ternary(result, Rd2427 == 0, Rd0811 + Rd1215, Rd0811); + overflowflags(result); + Rd2831 = result; +} + +# CADDN D[c], D[d], D[a], const9 (RCR) +:caddn Rd2831,Rd2427,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0xab ; Rd2427 & Rd2831 & op2123=0x1 ) & const1220S +{ + local result:4; + ternary(result, Rd2427 == 0, Rd0811 + const1220S, Rd0811); + overflowflags(result); + Rd2831 = result; +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# CALL disp8 (SB) +:call off0815pc8s is PCPMode=0 & off0815pc8s & op0007=0x5c +{ + #TODO call + # if (FCX == 0) trap(FCU); + # if (PSW.CDE) then if(cdc_increment()) then trap(CDO); + # PSW.CDE = 1; + # ret_addr = PC + 2 ; + # tmp_FCX = FCX; + # EA = {FCX.FCXS, 6'b0, FCX.FCXO, 6'b0}; + # new_FCX = M(EA, word); + # M(EA,16 * word) = {PCXI,PSW,a10,a11,d8,d9,d10,d11,a12,a13,a14,a15,d12,d13,d14,d15}; + # PCXI.PCPN = ICR.CCPN; + # PCXI.PIE = ICR.IE; + # PCXI.UL = 1; + # PCXI[19:0] = FCX[19:0]; + # FCX[19:0] = new_FCX[19:0]; + # PC = PC + sign_ext(2 * disp8); + # A[11] = ret_addr[31:0]; + # if (tmp_FCX == LCX) trap(FCD); + + saveCallerState(FCX, LCX, PCXI); + a11 = inst_next; + call off0815pc8s; +} +@endif + +# CALL disp24 (B) +:call off24pc is PCPMode=0 & ( op0007=0x6d ) ... & off24pc +{ + #TODO call + # if (FCX == 0) trap(FCU); + # if (PSW.CDE) then if (cdc_increment()) then trap(CDO); + # PSW.CDE = 1; + # ret_addr = PC + 4; + # tmp_FCX = FCX; + # EA = {FCX.FCXS, 6'b0, FCX.FCXO, 6'b0}; + # new_FCX = M(EA, word); + # M(EA,16 * word) = {PCXI,PSW,a10,a11,d8,d9,d10,d11,a12,a13,a14,a15,d12,d13,d14,d15}; + # PCXI.PCPN = ICR.CCPN; + # PCXI.PIE = ICR.IE; + # PCXI.UL = 1; + # PCXI[19:0] = FCX[19:0]; + # FCX[19:0] = new_FCX[19:0]; + # PC = PC + sign_ext(2 * disp24); + # A[11] = ret_addr[31:0]; + # if (tmp_FCX == LCX) trap(FCD); + + saveCallerState(FCX, LCX, PCXI); + a11 = inst_next; + call off24pc; +} + +# CALLA disp24 (B) +:calla off24abs is PCPMode=0 & ( op0007=0xed ) ... & off24abs +{ + #TODO call + # if (FCX == 0) trap(FCU); + # if (PSW.CDE) then if (cdc_increment()) then trap(CDO); + # PSW.CDE = 1; + # ret_addr = PC + 4; + # tmp_FCX = FCX; + # EA = {FCX.FCXS, 6'b0, FCX.FCXO, 6'b0}; + # new_FCX = M(EA, word); + # M(EA,16 * word) = {PCXI,PSW,a10,a11,d8,d9,d10,d11,a12,a13,a14,a15,d12,d13,d14,d15}; + # PCXI.PCPN = ICR.CCPN; + # PCXI.PIE = ICR.IE; + # PCXI.UL = 1; + # PCXI[19:0] = FCX[19:0]; + # FCX[19:0] = new_FCX[19:0]; + # PC = {disp24[23:20], 7'b0, disp24[19:0], 1'b0}; + # A[11] = ret_addr[31:0]; + # if (tmp_FCX == LCX) trap(FCD); + + saveCallerState(FCX, LCX, PCXI); + a11 = inst_next; + call off24abs; +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# CALLI A[a] (RR) +:calli Ra0811 is PCPMode=0 & Ra0811 & op0007=0x2d & op1215=0x0 ; op1631=0x0 +{ + #TODO call + # if (FCX == 0) trap(FCU); + # if (PSW.CDE) then if(cdc_increment()) then trap(CDO); + # PSW.CDE = 1; + # ret_addr = PC + 4; + # tmp_FCX = FCX; + # EA = {FCX.FCXS, 6'b0, FCX.FCXO, 6'b0}; + # new_FCX = M(EA, word); + # M(EA,16 * word) = {PCXI,PSW,a10,a11,d8,d9,d10,d11,a12,a13,a14,a15,d12,d13,d14,d15}; + # PCXI.PCPN = ICR.CCPN; + # PCXI.PIE = ICR.IE; + # PCXI.UL = 1; + # PCXI[19:0] = FCX[19:0]; + # FCX[19:0] = new_FCX[19:0]; + # PC = {A[a][31:1], 1'b0}; + # A[11] = ret_addr[31:0]; + # if (tmp_FCX == LCX) trap(FCD); + + saveCallerState(FCX, LCX, PCXI); + a11 = inst_next; + local tmp:4 = Ra0811 & 0xFFFFFFFE; + call [tmp]; +} +@endif + +# CLO D[c], D[a] (RR) +:clo Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0xf & op1215=0x0 ; Rd2831 & op1627=0x1c0 +{ + Rd2831 = lzcount(~Rd0811); +} + +# CLO.H D[c], D[a] (RR) +:clo.h Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0xf & op1215=0x0 ; Rd2831 & op1627=0x7d0 +{ + local tmp1:4 = zext(Rd0811[16,16]); + local tmp0:4 = zext(Rd0811[0,16]); + Rd2831[16,16] = lzcount(~tmp1); + Rd2831[0,16] = lzcount(~tmp0); +} + +# CLS D[c], D[a] (RR) +:cls Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0xf & op1215=0x0 ; Rd2831 & op1627=0x1d0 +{ + Rd2831 = leading_signs(Rd0811) - 1; +} + +# CLS.H D[c], D[a] (RR) +:cls.h Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0xf & op1215=0x0 ; Rd2831 & op1627=0x7e0 +{ + local tmp1:4 = zext(Rd0811[16,16]); + local tmp0:4 = zext(Rd0811[0,16]); + Rd2831[16,16] = leading_signs(tmp1) - 1; + Rd2831[0,16] = leading_signs(tmp0) - 1; +} + +# CLZ D[c], D[a] (RR) +:clz Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0xf & op1215=0x0 ; Rd2831 & op1627=0x1b0 +{ + Rd2831 = lzcount(Rd0811); +} + +# CLZ.H D[c], D[a] (RR) +:clz.h Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0xf & op1215=0x0 ; Rd2831 & op1627=0x7c0 +{ + local result:4 = (lzcount(Rd0811[16,16]) << 16) | lzcount(Rd0811[0,16]); + Rd2831 = result; +} + +# CMOV D[a], D[15], D[b] (SRR) +:cmov Rd0811,d15,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & d15 & op0007=0x2a +{ + ternary(Rd0811, d15 != 0, Rd1215, Rd0811); +} + +# CMOV D[a], D[15], const4 (SRC) +:cmov Rd0811,d15,const1215S is PCPMode=0 & Rd0811 & const1215S & d15 & op0007=0xaa +{ + ternary(Rd0811, d15 != 0, const1215S, Rd0811); +} + +# CMOVN D[a], D[15], D[b] (SRR) +:cmovn Rd0811,d15,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & d15 & op0007=0x6a +{ + ternary(Rd0811, d15 == 0, Rd1215, Rd0811); +} + +# CMOVN D[a], D[15], const4 (SRC) +:cmovn Rd0811,d15,const1215S is PCPMode=0 & Rd0811 & const1215S & d15 & op0007=0xea +{ + ternary(Rd0811, d15 == 0, const1215S, Rd0811); +} + +@if defined(TRICORE_V2) +# CMPSWAP.W A[b], off10, E[a] (BO)(Base + Short Offset Addressing Mode) +# CMPSWAP.W P[b], E[a] (BO)(Bit-reverse Addressing Mode) +# CMPSWAP.W A[b], off10, E[a] (BO)(Post-increment Addressing Mode) +# CMPSWAP.W A[b], off10, E[a] (BO)(Pre-increment Addressing Mode) +# CMPSWAP.W P[b], E[a] (BO)(Index Addressing Mode) +:cmpswap.w BO,Ree0811/Reo0811 is PCPMode=0 & ( Ree0811 & Reo0811 & op0607=0x1 ; op2225=0x3 ) & BO +{ + build BO; + local tmp:4 = *[ram]:4 BO; + Ree0811 = tmp; + ternary(tmp, tmp == Reo0811, Ree0811, tmp); + *[ram]:4 BO = tmp; +} +@endif + +@if defined(TRICORE_V2) +# CMPSWAP.W P[b], off10, E[a] (BO)(Circular Addressing Mode) +#:cmpswap.w BO,Ree0811/Reo0811 is PCPMode=0 & ( Ree0811 & Reo0811 & op0007=0x69 ; op2227=0x13 ) & BO +:cmpswap.w [Rpe1215/Rpo1215^"+c"^]off10,Ree0811/Reo0811 is PCPMode=0 & Ree0811 & Reo0811 & Rpe1215 & Rpo1215 & op0007=0x69 ; off10 & op2227=0x13 +{ + local EA:4; + CircularAddressingMode(Rpe1215, Rpo1215, EA, off10); + local tmp:4 = *[ram]:4 EA; + Ree0811 = tmp; + ternary(tmp, tmp == Reo0811, Ree0811, tmp); + *[ram]:4 EA = tmp; +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# CMP.F D[c], D[a], D[b] (RR) +:cmp.f Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Rd2831 & op1627=0x1 +{ + #TODO float + #TODO flags + local tmpDa = Rd0811; + local tmpDb = Rd1215; + Rd2831 = 0; + Rd2831[0,1] = tmpDa f< tmpDb; + Rd2831[1,1] = tmpDa f== tmpDb; + Rd2831[2,1] = tmpDa f> tmpDb; + Rd2831[3,1] = nan(tmpDa) || nan(tmpDb); + Rd2831[4,1] = tmpDa[23,8] == 0 && tmpDa[0,23] != 0; + Rd2831[5,1] = tmpDb[23,8] == 0 && tmpDb[0,23] != 0; +} +@endif + +:cop op2027[op1617],Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; op1617 & op2027 & Rd2831 & op1819=0x0 +{ + # Rd2831 = op2027[op1617](Rd0811,Rd1215); + local op2:4 = op2027; + local proc:4 = op1617; + Rd2831 = coprocessor(op2, proc, Rd0811, Rd1215); +} + +:cop op2023[op1617],Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x6b ; op1617 & op2023 & Rd2427 & Rd2831 & op1819=0x0 +{ + # Rd2831 = op2023[op1617](Rd2427,Rd0811,Rd1215); + local op2:4 = op2023; + local proc:4 = op1617; + Rd2831 = coprocessor(op2, proc, Rd2427, Rd0811, Rd1215); +} + +@if defined(TRICORE_V2) +# CRC32 D[c], D[b], D[a] (RR) +:crc32 Rd2831,Rd1215,Rd0811 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Rd2831 & op1627=0x30 +{ + #TODO crc of Rd0811 and the inverse of Rd1215 into Rd2831 + # crc is crc32, initial value of Rd1215 should be zero + Rd2831 = crc32(Rd1215, Rd0811); +} +@endif + +# CSUB D[c], D[d], D[a], D[b] (RRR) +:csub Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x2b ; Rd2427 & Rd2831 & op1623=0x20 +{ + local result:4; + ternary(result, Rd2427 != 0, Rd0811 - Rd1215, Rd0811); + overflowflags(result); + Rd2831 = result; +} + +# CSUBN D[c], D[d], D[a], D[b] (RRR) +:csubn Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x2b ; Rd2427 & Rd2831 & op1623=0x30 +{ + local result:4; + ternary(result, Rd2427 != 0, Rd0811, Rd1215); + overflowflags(result); + Rd2831 = result; +} + +# DEBUG (SR) +:debug is PCPMode=0 & op0007=0x0 & op0815=0xa0 +{ + if ($(DBGSR_DE) == 0) goto inst_next; + debug(); +} + +# DEBUG (SYS) +:debug is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x100 +{ + if ($(DBGSR_DE) == 0) goto inst_next; + debug(); +} + +# DEXTR D[c], D[a], D[b], pos (RRPW) +:dextr Rd2831,Rd0811,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x77 ; Rd2831 & const2327Z & op1622=0x0 +{ + local tmp:8 = (zext(Rd0811) << 32) | (zext(Rd1215) << const2327Z); + Rd2831 = tmp[32,32]; +} + +# DEXTR D[c], D[a], D[b], D[d] (RRRR) +:dextr Rd2831,Rd0811,Rd1215,Rd2427 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x17 ; Rd2427 & Rd2831 & op1623=0x80 +{ + local tmp:8 = (zext(Rd0811) << 32) | (zext(Rd1215) << Rd2427[0,5]); + Rd2831 = tmp[32,32]; +} + +# DISABLE (SYS) +:disable is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x340 +{ + $(ICR_IE) = 0; +} + +@if defined(TRICORE_V2) +# DISABLE D[a] (SYS) +:disable Rd0811 is PCPMode=0 & Rd0811 & op0007=0xd & op1215=0x0 ; op1631=0x3c0 +{ + Rd0811 = zext($(ICR_IE)); + $(ICR_IE) = 0; +} +@endif + +# DIV E[c], D[a], D[b] (RR) +:div Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0x201 +{ + #TODO divide + #TODO flags + local divres = Rd0811 s/ Rd1215; + local divmod = Rd0811 s% Rd1215; + Ree2831 = divres; + Reo2831 = divmod; +} + +# DIV.U E[c], D[a], D[b] (RR) +:div.u Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0x211 +{ + #TODO divide + #TODO flags + local divres = Rd0811 / Rd1215; + local divmod = Rd0811 % Rd1215; + Ree2831 = divres; + Reo2831 = divmod; +} + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# DIV.F D[c], D[a], D[b] (RR) +:div.f Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Rd2831 & op1627=0x51 +{ + #TODO float + #TODO divide + #TODO flags + Rd2831 = Rd0811 f/ Rd1215; +} +@endif + +# DSYNC (SYS) +:dsync is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x480 +{ + dsync(); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# DVADJ E[c], E[d], D[b] (RRR) +:dvadj Ree2831/Reo2831,Ree2427/Reo2427,Rd1215 is PCPMode=0 & Rd1215 & op0007=0x6b & op0811=0x0 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & op1623=0xd0 +{ + #TODO divide sequence + local q_sign = Reo2427[31,1] ^ Rd1215[31,1]; + local x_sign = Reo2427[31,1]; + local eq_pos = x_sign & (Reo2427 == Rd1215); + local eq_neg = x_sign & (Reo2427 == -Rd1215); + local quotient:4; + ternary(quotient, ((q_sign & ~eq_neg) | eq_pos), Ree2427 + 1, Ree2427); + local remainder:4; + ternary(remainder, (eq_pos | eq_neg), 0, Reo2427); + local absReo2427:4; int_abs(absReo2427, Reo2427); + local absRd1215:4; int_abs(absRd1215, Rd1215); + local _gt = absReo2427 > absRd1215; + local _eq = !x_sign && (absReo2427 == absRd1215); + ternary(Reo2831, (_eq | _gt) != 0, 0, remainder); + ternary(Ree2831, (_eq | _gt) != 0, 0, quotient); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# DVINIT E[c], D[a], D[b] (RR) +:dvinit Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0x1a0 +{ + #TODO divide sequence + local dividend:4 = Rd0811; + local divisor:4 = Rd1215; + + Ree2831 = dividend; + Reo2831 = 0xFFFFFFFF * zext(dividend[31,1]); + + $(PSW_V) = ((divisor == 0) || ((divisor == 0xFFFFFFFF) && (dividend == 0x80000000))); + $(PSW_SV) = $(PSW_V) | $(PSW_SV); + $(PSW_AV) = 0; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# DVINIT.B E[c], D[a], D[b] (RR) +:dvinit.b Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0x5a0 +{ + #TODO divide sequence + local dividend:4 = Rd0811; + local divisor:4 = Rd1215; + local quotient_sign = !(dividend[31,1] == divisor[31,1]); + Ree2831 = (dividend << 24) | (0xFFFFFF * zext(quotient_sign)); + Reo2831 = dividend s>> 8; + $(PSW_V) = ((divisor == 0) || ((divisor == 0xFFFFFFFF) && (dividend == 0xFFFFFF80))); + $(PSW_SV) = $(PSW_V) | $(PSW_SV); + $(PSW_AV) = 0; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# DVINIT.BU E[c], D[a], D[b] (RR) +:dvinit.bu Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0x4a0 +{ + #TODO divide sequence + local dividend:4 = Rd0811; # D[a] + local divisor:4 = Rd1215; # D[b] + + Ree2831 = dividend << 24; + Reo2831 = dividend >> 8; + $(PSW_V) = (divisor == 0); + $(PSW_SV) = $(PSW_V) | $(PSW_SV); + $(PSW_AV) = 0; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# DVINIT.H E[c], D[a], D[b] (RR) +:dvinit.h Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0x3a0 +{ + #TODO divide sequence + local dividend:4 = Rd0811; # D[a] + local divisor:4 = Rd1215; # D[b] + local quotient_sign = !(dividend[31,1] == divisor[31,1]); + + Ree2831 = (dividend << 16) | (zext(quotient_sign) * 0xFFFF); + Reo2831 = dividend s>> 16; + $(PSW_V) = ((divisor == 0) || ((divisor == 0xFFFFFFFF) && (dividend == 0xFFFF8000))); + $(PSW_SV) = $(PSW_V) | $(PSW_SV); + $(PSW_AV) = 0; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# DVINIT.HU E[c], D[a], D[b] (RR) +:dvinit.hu Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0x2a0 +{ + #TODO divide sequence + local dividend:4 = Rd0811; # D[a] + local divisor:4 = Rd1215; # D[b] + + Ree2831 = dividend << 16; + Reo2831 = dividend >> 16; + $(PSW_V) = (divisor == 0); + $(PSW_SV) = $(PSW_V) | $(PSW_SV); + $(PSW_AV) = 0; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# DVINIT.U E[c], D[a], D[b] (RR) +:dvinit.u Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0xa0 +{ + #TODO divide sequence + local dividend:4 = Rd0811; # D[a] + local divisor:4 = Rd1215; # D[b] + + Ree2831 = dividend; + Reo2831 = 0; + $(PSW_V) = (divisor == 0); + $(PSW_SV) = $(PSW_V) | $(PSW_SV); + $(PSW_AV) = 0; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# DVSTEP E[c], E[d], D[b] (RRR) +:dvstep Ree2831/Reo2831,Ree2427/Reo2427,Rd1215 is PCPMode=0 & Rd1215 & op0007=0x6b & op0811=0x0 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & op1623=0xf0 +{ + #TODO divide sequence + local dividend_sign = Reo2427[31,1] == 1; + local divisor_sign = Rd1215[31,1] == 1; + local quotient_sign = dividend_sign != divisor_sign; + local addend:4; + ternary(addend, quotient_sign != 0, Rd1215, 0 - Rd1215); + local dividend_quotient:4 = Ree2427; + local remainder:4 = Reo2427; + local temp:4 = 0; + local index:1 = 0; + + remainder = (remainder << 1) | zext(dividend_quotient[31,1]); + dividend_quotient = dividend_quotient << 1; + temp = remainder + addend; + ternary(remainder, (temp s< 0) == dividend_sign, temp, remainder); + ternary(temp, (temp s< 0) == dividend_sign, zext(!quotient_sign), zext(quotient_sign)); + dividend_quotient = dividend_quotient | temp; + index = index + 1; + if (index < 8) goto ; + Reo2831 = remainder; + Ree2831 = dividend_quotient; +} +@endif + + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# DVSTEP.U E[c], E[d], D[b] (RRR) +:dvstep.u Ree2831/Reo2831,Ree2427/Reo2427,Rd1215 is PCPMode=0 & Rd1215 & op0007=0x6b & op0811=0x0 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & op1623=0xe0 +{ + #TODO divide sequence + local divisor = Rd1215; + local dividend_quotient = Ree2427; + local remainder = Reo2427; + local temp:4 = 0; + local index:1 = 0; + + remainder = (remainder << 1) | zext(dividend_quotient[31,1]); + dividend_quotient = dividend_quotient << 1; + temp = remainder - divisor; + ternary(remainder, temp s< 0, remainder, temp); + dividend_quotient = dividend_quotient | zext(!(temp s< 0)); + index = index + 1; + if (index < 8) goto ; + Reo2427 = remainder; + Ree2427 = dividend_quotient; +} +@endif + +# ENABLE (SYS) +:enable is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x300 +{ + $(ICR_IE) = 1; +} + +# EQ D[15], D[a], D[b] (SRR) +:eq d15,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & d15 & op0007=0x3a +{ + d15 = zext(Rd0811 == Rd1215); +} + +# EQ D[15], D[a], const4 (SRC) +:eq d15,Rd0811,const1215S is PCPMode=0 & Rd0811 & const1215S & d15 & op0007=0xba +{ + d15 = zext(Rd0811 == const1215S); +} + +# EQ D[c], D[a], D[b] (RR) +:eq Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x100 +{ + Rd2831 = zext(Rd0811 == Rd1215); +} + +# EQ D[c], D[a], const9 (RC) +:eq Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x10 ) & const1220S +{ + Rd2831 = zext(Rd0811 == const1220S); +} + +# EQ.A D[c], A[a], A[b] (RR) +:eq.a Rd2831,Ra0811,Ra1215 is PCPMode=0 & Ra0811 & Ra1215 & op0007=0x1 ; Rd2831 & op1627=0x400 +{ + Rd2831 = zext(Ra0811 == Ra1215); +} + +# EQ.B D[c], D[a], D[b] (RR) +:eq.b Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x500 +{ + local result3:4 = 0xff * zext(Rd0811[24,8] == Rd1215[24,8]); + local result2:4 = 0xff * zext(Rd0811[16,8] == Rd1215[16,8]); + local result1:4 = 0xff * zext(Rd0811[8,8] == Rd1215[8,8]); + local result0:4 = 0xff * zext(Rd0811[0,8] == Rd1215[0,8]); + Rd2831 = (result3 << 24) | (result2 << 16) | (result1 << 8) | (result0); +} + +# EQ.H D[c], D[a], D[b] (RR) +:eq.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x700 +{ + local result1:4 = 0xffff * zext(Rd0811[16,16] == Rd1215[16,16]); + local result0:4 = 0xffff * zext(Rd0811[0,16] == Rd1215[0,16]); + Rd2831 = (result1 << 16) | (result0); +} + +# EQ.W D[c], D[a], D[b] (RR) +:eq.w Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x900 +{ + Rd2831 = 0xffffffff * zext(Rd0811 == Rd1215); +} + +# EQANY.B D[c], D[a], D[b] (RR) +:eqany.b Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x560 +{ + local result3 = Rd0811[24,8] == Rd1215[24,8]; + local result2 = Rd0811[16,8] == Rd1215[16,8]; + local result1 = Rd0811[8,8] == Rd1215[8,8]; + local result0 = Rd0811[0,8] == Rd1215[0,8]; + Rd2831 = zext(result3 | result2 | result1 | result0); +} + +# EQANY.B D[c], D[a], const9 (RC) +:eqany.b Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x56 ) & const1220S +{ + local result3 = Rd0811[24,8] == const1220S[24,8]; + local result2 = Rd0811[16,8] == const1220S[16,8]; + local result1 = Rd0811[8,8] == const1220S[8,8]; + local result0 = Rd0811[0,8] == const1220S[0,8]; + Rd2831 = zext(result3 | result2 | result1 | result0); +} + +# EQANY.H D[c], D[a], D[b] (RR) +:eqany.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x760 +{ + local result1 = Rd0811[16,16] == Rd1215[16,16]; + local result0 = Rd0811[0,16] == Rd1215[0,16]; + Rd2831 = zext(result1 | result0); +} + +# EQANY.H D[c], D[a], const9 (RC) +:eqany.h Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x76 ) & const1220S +{ + local result1 = Rd0811[16,16] == const1220S[16,16]; + local result0 = Rd0811[0,16] == const1220S[0,16]; + Rd2831 = zext(result1 | result0); +} + +# EQZ.A D[c], A[a] (RR) +:eqz.a Rd2831,Ra0811 is PCPMode=0 & Ra0811 & op0007=0x1 & op1215=0x0 ; Rd2831 & op1627=0x480 +{ + Rd2831 = zext(Ra0811 == 0); +} + +# EXTR D[c], D[a], E[d] (RRRR) +:extr Rd2831,Rd0811,Ree2427/Reo2427 is PCPMode=0 & Rd0811 & op0007=0x17 & op1215=0x0 ; Rd2831 & Ree2427 & Reo2427 & op1623=0x40 +{ + local shift:4 = zext(Ree2427[0,5]); + local tmp:4 = (Rd0811 << (32 - shift - zext(Reo2427[0,5]))) s>> (32 - zext(Reo2427[0,5])); + Rd2831 = tmp; +} + +# EXTR D[c], D[a], pos, width (RRPW) +:extr Rd2831,Rd0811,const2327Z,const1620Z is PCPMode=0 & Rd0811 & op0007=0x37 & op1215=0x0 ; Rd2831 & const1620Z & const2327Z & op2122=0x2 +{ + local shift:4 = const2327Z; + local tmp:4 = (Rd0811 << (32 - shift - const1620Z)) s>> (32 - const1620Z); + Rd2831 = tmp; +} + +# EXTR D[c], D[a], D[d], width (RRRW) +:extr Rd2831,Rd0811,Rd2427,const1620Z is PCPMode=0 & Rd0811 & op0007=0x57 & op1215=0x0 ; Rd2427 & Rd2831 & const1620Z & op2123=0x2 +{ + local shift:4 = zext(Rd2427[0,5]); + local tmp:4 = (Rd0811 << (32 - shift - const1620Z)) s>> (32 - const1620Z); + Rd2831 = tmp; +} + +# EXTR.U D[c], D[a], E[d] (RRRR) +:extr.u Rd2831,Rd0811,Ree2427/Reo2427 is PCPMode=0 & Rd0811 & op0007=0x17 & op1215=0x0 ; Rd2831 & Ree2427 & Reo2427 & op1623=0x60 +{ + local tmp:4 = Rd0811 >> Ree2427[0,5]; + local mask:4 = (1 << Reo2427[0,5]) - 1; + Rd2831 = tmp & mask; +} + +# EXTR.U D[c], D[a], pos, width (RRPW) +:extr.u Rd2831,Rd0811,const2327Z,const1620Z is PCPMode=0 & Rd0811 & op0007=0x37 & op1215=0x0 ; Rd2831 & const1620Z & const2327Z & op2122=0x3 +{ + local tmp:4 = Rd0811 >> const2327Z; + local mask:4 = (1 << const1620Z) - 1; + Rd2831 = tmp & mask; +} + +# EXTR.U D[c], D[a], D[d], width (RRRW) +:extr.u Rd2831,Rd0811,Rd2427,const1620Z is PCPMode=0 & Rd0811 & op0007=0x57 & op1215=0x0 ; Rd2427 & Rd2831 & const1620Z & op2123=0x3 +{ + local tmp:4 = Rd0811 >> Rd2427[0,5]; + local mask:4 = (1 << const1620Z) - 1; + Rd2831 = tmp & mask; +} + +@if defined(TRICORE_V2) +# FCALL disp24 (B) +:fcall off24pc is PCPMode=0 & ( op0007=0x61 ) ... & off24pc +{ + #TODO call + a10 = a10 - 4; + *[ram]:4 a10 = a11; + a11 = inst_next; + call off24pc; +} +@endif + +@if defined(TRICORE_V2) +# CALLA disp24 (B) +:fcalla off24abs is PCPMode=0 & ( op0007=0xe1 ) ... & off24abs +{ + #TODO call + a10 = a10 - 4; + *[ram]:4 a10 = a11; + a11 = inst_next; + call off24abs; +} +@endif + +@if defined(TRICORE_V2) +# FCALLI A[a] (RR) +:fcalli Ra0811 is PCPMode=0 & Ra0811 & op0007=0x2d & op1215=0x0 ; op1631=0x10 +{ + #TODO call + a10 = a10 - 4; + *[ram]:4 a10 = a11; + a11 = inst_next; + local tmp:4 = Ra0811 & 0xFFFFFFFE; + call [tmp]; +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# FRET (SR) +:fret is PCPMode=0 & op0007=0x0 & op0811=0x0 & op1215=0x7 +{ + local tmp:4 = a11 & 0xFFFFFFFE; + a11 = *[ram]:4 a10; + a10 = a10 + 4; + return [tmp]; +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# FRET (SYS) +:fret is PCPMode=0 & op0007=0x0d & op0815=0x0 ; op1621=0x0 & op2227=0x3 & op2831=0x0 +{ + local tmp:4 = a11 & 0xFFFFFFFE; + a11 = *[ram]:4 a10; + a10 = a10 + 4; + return [tmp]; +} +@endif + + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# FTOI D[c], D[a] (RR) +:ftoi Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; Rd2831 & op1627=0x101 +{ + #TODO float + #TODO flags + Rd2831 = trunc(Rd0811); +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# FTOIZ D[c], D[a] (RR) +:ftoiz Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; Rd2831 & op1627=0x131 +{ + #TODO float + #TODO flags + #TODO round + Rd2831 = floor(trunc(Rd0811)); +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# FTOQ31 D[c], D[a], D[b] (RR) +:ftoq31 Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Rd2831 & op1627=0x111 +{ + #TODO float + #TODO flags +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# FTOQ31Z D[c], D[a], D[b] (RR) +:ftoq31z Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Rd2831 & op1627=0x181 +{ + #TODO float + #TODO flags + #TODO round +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# FTOU D[c], D[a] (RR) +:ftou Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; Rd2831 & op1627=0x121 +{ + #TODO float + #TODO flags + #TODO unsigned +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# FTOUZ D[c], D[a] (RR) +:ftouz Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; Rd2831 & op1627=0x171 +{ + #TODO float + #TODO flags + #TODO unsigned + #TODO round +} +@endif + +# GE D[c], D[a], D[b] (RR) +:ge Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x140 +{ + Rd2831 = zext(Rd0811 s>= Rd1215); +} + +# GE D[c], D[a], const9 (RC) +:ge Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x14 ) & const1220S +{ + Rd2831 = zext(Rd0811 s>= const1220S); +} + +# GE.A D[c], A[a], A[b] (RR) +:ge.a Rd2831,Ra0811,Ra1215 is PCPMode=0 & Ra0811 & Ra1215 & op0007=0x1 ; Rd2831 & op1627=0x430 +{ + Rd2831 = zext(Ra0811 >= Ra1215); +} + +# GE.U D[c], D[a], D[b] (RR) +:ge.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x150 +{ + Rd2831 = zext(Rd0811 >= Rd1215); +} + +# GE.U D[c], D[a], const9 (RC) +:ge.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x15 ) & const1220Z +{ + Rd2831 = zext(Rd0811 >= const1220Z); +} + +# IMASK E[c], D[b], pos, width (RRPW) +:imask Ree2831/Reo2831,Rd1215,const2327Z,const1620Z is PCPMode=0 & Rd1215 & op0007=0x37 & op0811=0x0 ; Ree2831 & Reo2831 & const1620Z & const2327Z & op2122=0x1 +{ + local tmp:4 = 1; + local tmp2:4 = Rd1215; + tmp = (tmp << const1620Z) - 1; + Reo2831 = tmp << const2327Z; + Ree2831 = tmp2 << const2327Z; +} + +# IMASK E[c], D[b], D[d], width (RRRW) +:imask Ree2831/Reo2831,Rd1215,Rd2427,const1620Z is PCPMode=0 & Rd1215 & op0007=0x57 & op0811=0x0 ; Rd2427 & Ree2831 & Reo2831 & const1620Z & op2123=0x1 +{ + local tmp:4 = 1; + local tmp2:4 = Rd1215; + local tmp3:4 = Rd2427; + tmp = (tmp << const1620Z) - 1; + Reo2831 = tmp << tmp3[0,5]; + Ree2831 = tmp2 << tmp3[0,5]; +} + +# IMASK E[c], const4, pos, width (RCPW) +:imask Ree2831/Reo2831,const1215Z,const2327Z,const1620Z is PCPMode=0 & const1215Z & op0007=0xb7 & op0811=0x0 ; Ree2831 & Reo2831 & const1620Z & const2327Z & op2122=0x1 +{ + local tmp:4 = 1; + tmp = (tmp << const1620Z) - 1; + Reo2831 = tmp << const2327Z; + Ree2831 = const1215Z << const2327Z; +} + +# IMASK E[c], const4, D[d], width (RCRW) +:imask Ree2831/Reo2831,const1215Z,Rd2427,const1620Z is PCPMode=0 & const1215Z & op0007=0xd7 & op0811=0x0 ; Rd2427 & Ree2831 & Reo2831 & const1620Z & op2123=0x1 +{ + local tmp:4 = 1; + local tmp2:4 = Rd2427; + tmp = (tmp << const1620Z) - 1; + Reo2831 = tmp << tmp2[0,5]; + Ree2831 = const1215Z << tmp2[0,5]; +} + +# INS.T D[c], D[a], pos1, D[b], pos2 (BIT) +:ins.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x67 ; Rd2831 & const1620Z & const2327Z & op2122=0x0 +{ + local tmp:4 = Rd0811 & ~(1 << const1620Z); + Rd2831 = tmp | (((Rd1215 >> const2327Z) & 1) << const1620Z); +} + +# INSERT D[c], D[a], D[b], E[d] (RRRR) +:insert Rd2831,Rd0811,Rd1215,Ree2427/Reo2427 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x17 ; Rd2831 & Ree2427 & Reo2427 & op1623=0x0 +{ + local tmp:4 = 1; + tmp = (tmp << Reo2427) - 1; + tmp = tmp << Ree2427[0,5]; + Rd2831 = (Rd0811 & ~tmp) | ((Rd1215 << Ree2427[0,5]) & tmp); +} + +# INSERT D[c], D[a], D[b], pos, width (RRPW) +:insert Rd2831,Rd0811,Rd1215,const2327Z,const1620Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x37 ; Rd2831 & const1620Z & const2327Z & op2122=0x0 +{ + local tmp:4 = 1; + tmp = (tmp << const1620Z) - 1; + tmp = tmp << const2327Z; + Rd2831 = (Rd0811 & ~tmp) | ((Rd1215 << const2327Z) & tmp); +} + +# INSERT D[c], D[a], D[b], D[d], width (RRRW) +:insert Rd2831,Rd0811,Rd1215,Rd2427,const1620Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x57 ; Rd2427 & Rd2831 & const1620Z & op2123=0x0 +{ + local tmp:4 = 1; + tmp = (tmp << const1620Z) - 1; + tmp = tmp << Rd2427[0,5]; + Rd2831 = (Rd0811 & ~tmp) | ((Rd1215 << Rd2427[0,5]) & tmp); +} + +# INSERT D[c], D[a], const4, E[d] (RCRR) +:insert Rd2831,Rd0811,const1215Z,Ree2427/Reo2427 is PCPMode=0 & Rd0811 & const1215Z & op0007=0x97 ; Rd2831 & Ree2427 & Reo2427 & op1623=0x0 +{ + local tmp:4 = 1; + tmp = (tmp << Reo2427) - 1; + tmp = tmp << Ree2427[0,5]; + Rd2831 = (Rd0811 & ~tmp) | ((const1215Z << Ree2427[0,5]) & tmp); +} + +# INSERT D[c], D[a], const4, pos, width (RCPW) +:insert Rd2831,Rd0811,const1215Z,const2327Z,const1620Z is PCPMode=0 & Rd0811 & const1215Z & op0007=0xb7 ; Rd2831 & const1620Z & const2327Z & op2122=0x0 +{ + local tmp:4 = 1; + tmp = (tmp << const1620Z) - 1; + tmp = tmp << const2327Z; + Rd2831 = (Rd0811 & ~tmp) | ((const1215Z << const2327Z) & tmp); +} + +# INSERT D[c], D[a], const4, D[d], width (RCRW) +:insert Rd2831,Rd0811,const1215Z,Rd2427,const1620Z is PCPMode=0 & Rd0811 & const1215Z & op0007=0xd7 ; Rd2427 & Rd2831 & const1620Z & op2123=0x0 +{ + local tmp:4 = 1; + tmp = (tmp << const1620Z) - 1; + tmp = tmp << Rd2427[0,5]; + Rd2831 = (Rd0811 & ~tmp) | ((const1215Z << Rd2427[0,5]) & tmp); +} + +# INSN.T D[c], D[a], pos1, D[b], pos2 (BIT) +:insn.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x67 ; Rd2831 & const1620Z & const2327Z & op2122=0x1 +{ + local tmp:4 = Rd0811 & ~(1 << const1620Z); + Rd2831 = tmp | (((~Rd1215 >> const2327Z) & 1) << const1620Z); +} + +# ISYNC (SYS) +:isync is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x4c0 +{ + isync(); +} + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# ITOF D[c], D[a] (RR) +:itof Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; Rd2831 & op1627=0x141 +{ + #TODO float + #TODO flags + Rd2831 = int2float(Rd0811); +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# IXMAX E[c], E[d], D[b] (RRR) +:ixmax Re2831,Re2427,Rd1215 is PCPMode=0 & Rd1215 & op0007=0x6b & op0811=0x0 ; Re2427 & Re2831 & op1623=0xa0 +{ + local tmp:8 = Re2427; + local tmp2:4 = Rd1215; + Re2831[0,16] = tmp[0,16] + 2; + Re2831[48,16] = 0; + local cond1 = (tmp2[0,16] s>= tmp2[16,16]) && (tmp2[0,16] s> tmp[32,16]); + if (cond1) goto <_first>; + local cond2 = (tmp2[16,16] s> tmp2[0,16]) && (tmp2[16,16] s> tmp[32,16]); + if (cond2) goto <_second>; + Re2831[32,16] = tmp[32,16]; + Re2831[16,16] = tmp[16,16]; + goto inst_next; + <_first> + Re2831[32,16] = tmp2[0,16]; + Re2831[16,16] = tmp[0,16]; + goto inst_next; + <_second> + Re2831[32,16] = tmp2[16,16]; + Re2831[16,16] = tmp[0,16] + 1; +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# IXMAX.U E[c], E[d], D[b] (RRR) +:ixmax.u Re2831,Re2427,Rd1215 is PCPMode=0 & Rd1215 & op0007=0x6b & op0811=0x0 ; Re2427 & Re2831 & op1623=0xb0 +{ + local tmp:8 = Re2427; + local tmp2:4 = Rd1215; + Re2831[0,16] = tmp[0,16] + 2; + Re2831[48,16] = 0; + local cond1 = (tmp2[0,16] >= tmp2[16,16]) && (tmp2[0,16] > tmp[32,16]); + if (cond1) goto <_first>; + local cond2 = (tmp2[16,16] > tmp2[0,16]) && (tmp2[16,16] > tmp[32,16]); + if (cond2) goto <_second>; + Re2831[32,16] = tmp[32,16]; + Re2831[16,16] = tmp[16,16]; + goto inst_next; + <_first> + Re2831[32,16] = tmp2[0,16]; + Re2831[16,16] = tmp[0,16]; + goto inst_next; + <_second> + Re2831[32,16] = tmp2[16,16]; + Re2831[16,16] = tmp[0,16] + 1; +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# IXMIN E[c], E[d], D[b] (RRR) +:ixmin Re2831,Re2427,Rd1215 is PCPMode=0 & Rd1215 & op0007=0x6b & op0811=0x0 ; Re2427 & Re2831 & op1623=0x80 +{ + local tmp:8 = Re2427; + local tmp2:4 = Rd1215; + Re2831[0,16] = tmp[0,16] + 2; + Re2831[48,16] = 0; + local cond1 = (tmp2[0,16] s<= tmp2[16,16]) && (tmp2[0,16] s< tmp[32,16]); + if (cond1) goto <_first>; + local cond2 = (tmp2[16,16] s< tmp2[0,16]) && (tmp2[16,16] s< tmp[32,16]); + if (cond2) goto <_second>; + Re2831[32,16] = tmp[32,16]; + Re2831[16,16] = tmp[16,16]; + goto inst_next; + <_first> + Re2831[32,16] = tmp2[0,16]; + Re2831[16,16] = tmp[0,16]; + goto inst_next; + <_second> + Re2831[32,16] = tmp2[16,16]; + Re2831[16,16] = tmp[0,16] + 1; +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# IXMIN.U E[c], E[d], D[b] (RRR) +:ixmin.u Re2831,Re2427,Rd1215 is PCPMode=0 & Rd1215 & op0007=0x6b & op0811=0x0 ; Re2427 & Re2831 & op1623=0x90 +{ + local tmp:8 = Re2427; + local tmp2:4 = Rd1215; + Re2831[0,16] = tmp[0,16] + 2; + Re2831[48,16] = 0; + local cond1 = (tmp2[0,16] <= tmp2[16,16]) && (tmp2[0,16] < tmp[32,16]); + if (cond1) goto <_first>; + local cond2 = (tmp2[16,16] < tmp2[0,16]) && (tmp2[16,16] < tmp[32,16]); + if (cond2) goto <_second>; + Re2831[32,16] = tmp[32,16]; + Re2831[16,16] = tmp[16,16]; + goto inst_next; + <_first> + Re2831[32,16] = tmp2[0,16]; + Re2831[16,16] = tmp[0,16]; + goto inst_next; + <_second> + Re2831[32,16] = tmp2[16,16]; + Re2831[16,16] = tmp[0,16] + 1; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# J disp8 (SB) +:j off0815pc8s is PCPMode=0 & off0815pc8s & op0007=0x3c +{ + goto off0815pc8s; +} +@endif + +# J disp24 (B) +:j off24pc is PCPMode=0 & ( op0007=0x1d ) ... & off24pc +{ + goto off24pc; +} + +# JA disp24 (B) +:ja off24abs is PCPMode=0 & ( op0007=0x9d ) ... & off24abs +{ + goto off24abs; +} + +@if defined(TRICORE_V2) +# JEQ D[15], D[b], disp4 (SBR) +:jeq d15,Rd1215,off0811pc4z16 is PCPMode=0 & Rd1215 & d15 & off0811pc4z16 & op0007=0xbe +{ + if (d15 == Rd1215) goto off0811pc4z16; +} +@endif + +@if defined(TRICORE_V2) +# JEQ D[15], const4, disp4 (SBC) +:jeq d15,const1215S,off0811pc4z16 is PCPMode=0 & const1215S & d15 & off0811pc4z16 & op0007=0x9e +{ + if (d15 == const1215S) goto off0811pc4z16; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# JEQ D[15], D[b], disp4 (SBR) +:jeq d15,Rd1215,off0811pc4z is PCPMode=0 & Rd1215 & d15 & off0811pc4z & op0007=0x3e +{ + if (d15 == Rd1215) goto off0811pc4z; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# JEQ D[15], const4, disp4 (SBC) +:jeq d15,const1215S,off0811pc4z is PCPMode=0 & const1215S & d15 & off0811pc4z & op0007=0x1e +{ + if (d15 == const1215S) goto off0811pc4z; +} +@endif + +# JEQ D[a], D[b], disp15 (BRR) +:jeq Rd0811,Rd1215,off1630pc15s is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x5f ; off1630pc15s & op3131=0x0 +{ + if (Rd0811 == Rd1215) goto off1630pc15s; +} + +# JEQ D[a], const4, disp15 (BRC) +:jeq Rd0811,const1215S,off1630pc15s is PCPMode=0 & Rd0811 & const1215S & op0007=0xdf ; off1630pc15s & op3131=0x0 +{ + if (Rd0811 == const1215S) goto off1630pc15s; +} + +# JEQ.A A[a], A[b], disp15 (BRR) +:jeq.a Ra0811,Ra1215,off1630pc15s is PCPMode=0 & Ra0811 & Ra1215 & op0007=0x7d ; off1630pc15s & op3131=0x0 +{ + if (Ra0811 == Ra1215) goto off1630pc15s; +} + +# JGE D[a], D[b], disp15 (BRR) +:jge Rd0811,Rd1215,off1630pc15s is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x7f ; off1630pc15s & op3131=0x0 +{ + if (Rd0811 s>= Rd1215) goto off1630pc15s; +} + +# JGE D[a], const4, disp15 (BRC) +:jge Rd0811,const1215S,off1630pc15s is PCPMode=0 & Rd0811 & const1215S & op0007=0xff ; off1630pc15s & op3131=0x0 +{ + if (Rd0811 s>= const1215S) goto off1630pc15s; +} + +# JGE.U D[a], D[b], disp15 (BRR) +:jge.u Rd0811,Rd1215,off1630pc15s is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x7f ; off1630pc15s & op3131=0x1 +{ + if (Rd0811 >= Rd1215) goto off1630pc15s; +} + +# JGE.U D[a], const4, disp15 (BRC) +:jge.u Rd0811,const1215Z,off1630pc15s is PCPMode=0 & Rd0811 & const1215Z & op0007=0xff ; off1630pc15s & op3131=0x1 +{ + if (Rd0811 >= const1215Z) goto off1630pc15s; +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# JGEZ D[b], disp4 (SBR) +:jgez Rd1215,off0811pc4z is PCPMode=0 & Rd1215 & off0811pc4z & op0007=0xce +{ + if (Rd1215 s>= 0) goto off0811pc4z; +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_RIDER_B) || defined(TRICORE_V2) +# JGTZ D[b], disp4 (SBR) +:jgtz Rd1215,off0811pc4z is PCPMode=0 & Rd1215 & off0811pc4z & op0007=0x4e +{ + if (Rd1215 s> 0) goto off0811pc4z; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# JI A[a] (SR) +:ji Ra0811 is PCPMode=0 & Ra0811 & op0007=0xdc & op1215=0x0 +{ + local tmp:4 = Ra0811; + tmp[0,1] = 0; + goto [tmp]; +} +:ji a11 is PCPMode=0 & op0811=11 & op0007=0xdc & op1215=0x0 & a11 +{ + return [a11]; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# JI A[a] (RR) +:ji Ra0811 is PCPMode=0 & Ra0811 & op0007=0x2d & op1215=0x0 ; op1631=0x30 +{ + local tmp:4 = Ra0811; + tmp[0,1] = 0; + goto [tmp]; +} +:ji a11 is PCPMode=0 & op0811=11 & op0007=0x2d & op1215=0x0 & a11; op1631=0x30 +{ + return [a11]; +} +@endif + +# JL disp24 (B) +:jl off24pc is PCPMode=0 & ( op0007=0x5d ) ... & off24pc +{ + #TODO is this just a call w/o context switching? + a11 = inst_next; + call off24pc; +} + +# JLA disp24 (B) +:jla off24abs is PCPMode=0 & ( op0007=0xdd ) ... & off24abs +{ + #TODO is this just a call w/o context switching? + a11 = inst_next; + call off24abs; +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# JLEZ D[b], disp4 (SBR) +:jlez Rd1215,off0811pc4z is PCPMode=0 & Rd1215 & off0811pc4z & op0007=0x8e +{ + if (Rd1215 s<= 0) goto off0811pc4z; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# JLI A[a] (RR) +:jli Ra0811 is PCPMode=0 & Ra0811 & op0007=0x2d & op1215=0x0 ; op1631=0x20 +{ + a11 = inst_start + 4; + local tmp:4 = Ra0811 & 0xFFFFFFFE; + call [tmp]; +} +@endif + +# JLT D[a], D[b], disp15 (BRR) +:jlt Rd0811,Rd1215,off1630pc15s is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x3f ; off1630pc15s & op3131=0x0 +{ + if (Rd0811 s< Rd1215) goto off1630pc15s; +} + +# JLT D[a], const4, disp15 (BRC) +:jlt Rd0811,const1215S,off1630pc15s is PCPMode=0 & Rd0811 & const1215S & op0007=0xbf ; off1630pc15s & op3131=0x0 +{ + if (Rd0811 s< const1215S) goto off1630pc15s; +} + +# JLT.U D[a], D[b], disp15 (BRR) +:jlt.u Rd0811,Rd1215,off1630pc15s is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x3f ; off1630pc15s & op3131=0x1 +{ + if (Rd0811 < Rd1215) goto off1630pc15s; +} + +# JLT.U D[a], const4, disp15 (BRC) +:jlt.u Rd0811,const1215Z,off1630pc15s is PCPMode=0 & Rd0811 & const1215Z & op0007=0xbf ; off1630pc15s & op3131=0x1 +{ + if (Rd0811 < const1215Z) goto off1630pc15s; +} + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_RIDER_B) || defined(TRICORE_V2) +# JLTZ D[b], disp4 (SBR) +:jltz Rd1215,off0811pc4z is PCPMode=0 & Rd1215 & off0811pc4z & op0007=0xe +{ + if (Rd1215 s< 0) goto off0811pc4z; +} +@endif + +@if defined(TRICORE_V2) +# JNE D[15], D[b], disp4 (SBR) +:jne d15,Rd1215,off0811pc4z16 is PCPMode=0 & Rd1215 & d15 & off0811pc4z16 & op0007=0xfe +{ + if (d15 != Rd1215) goto off0811pc4z16; +} +@endif + +@if defined(TRICORE_V2) +# JNE D[15], const4, disp4 (SBC) +:jne d15,const1215S,off0811pc4z16 is PCPMode=0 & const1215S & d15 & off0811pc4z16 & op0007=0xde +{ + if (d15 != const1215S) goto off0811pc4z16; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# JNE D[15], D[b], disp4 (SBR) +:jne d15,Rd1215,off0811pc4z is PCPMode=0 & Rd1215 & d15 & off0811pc4z & op0007=0x7e +{ + if (d15 != Rd1215) goto off0811pc4z; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# JNE D[15], const4, disp4 (SBC) +:jne d15,const1215S,off0811pc4z is PCPMode=0 & const1215S & d15 & off0811pc4z & op0007=0x5e +{ + if (d15 != const1215S) goto off0811pc4z; +} +@endif + +# JNE D[a], D[b], disp15 (BRR) +:jne Rd0811,Rd1215,off1630pc15s is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x5f ; off1630pc15s & op3131=0x1 +{ + if (Rd0811 != Rd1215) goto off1630pc15s; +} + +# JNE D[a], const4, disp15 (BRC) +:jne Rd0811,const1215S,off1630pc15s is PCPMode=0 & Rd0811 & const1215S & op0007=0xdf ; off1630pc15s & op3131=0x1 +{ + if (Rd0811 != const1215S) goto off1630pc15s; +} + +# JNE.A A[a], A[b], disp15 (BRR) +:jne.a Ra0811,Ra1215,off1630pc15s is PCPMode=0 & Ra0811 & Ra1215 & op0007=0x7d ; off1630pc15s & op3131=0x1 +{ + if (Ra0811 != Ra1215) goto off1630pc15s; +} + +# JNED D[a], D[b], disp15 (BRR) +:jned Rd0811,Rd1215,off1630pc15s is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x1f ; off1630pc15s & op3131=0x1 +{ + local tmp = Rd0811; + Rd0811 = Rd0811 - 1; + if (tmp != Rd1215) goto off1630pc15s; +} + +# JNED D[a], const4, disp15 (BRC) +:jned Rd0811,const1215S,off1630pc15s is PCPMode=0 & Rd0811 & const1215S & op0007=0x9f ; off1630pc15s & op3131=0x1 +{ + local tmp = Rd0811; + Rd0811 = Rd0811 - 1; + if (tmp != const1215S) goto off1630pc15s; +} + +# JNEI D[a], D[b], disp15 (BRR) +:jnei Rd0811,Rd1215,off1630pc15s is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x1f ; off1630pc15s & op3131=0x0 +{ + local tmp = Rd0811; + Rd0811 = Rd0811 + 1; + if (tmp != Rd1215) goto off1630pc15s; +} + +# JNEI D[a], const4, disp15 (BRC) +:jnei Rd0811,const1215S,off1630pc15s is PCPMode=0 & Rd0811 & const1215S & op0007=0x9f ; off1630pc15s & op3131=0x0 +{ + local tmp = Rd0811; + Rd0811 = Rd0811 - 1; + if (tmp != const1215S) goto off1630pc15s; +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# JNZ D[15], disp8 (SB) +:jnz d15,off0815pc8s is PCPMode=0 & d15 & off0815pc8s & op0007=0xee +{ + if (d15 != 0) goto off0815pc8s; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# JNZ D[b], disp4 (SBR) +:jnz Rd1215,off0811pc4z is PCPMode=0 & Rd1215 & off0811pc4z & op0007=0xf6 +{ + if (Rd1215 != 0) goto off0811pc4z; +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_RIDER_B) || defined(TRICORE_V2) +# JNZ.A A[b], disp4 (SBR) +:jnz.a Ra1215,off0811pc4z is PCPMode=0 & Ra1215 & off0811pc4z & op0007=0x7c +{ + if (Ra1215 != 0) goto off0811pc4z; +} +@endif + +# JNZ.A A[a], disp15 (BRR) +:jnz.a Ra0811,off1630pc15s is PCPMode=0 & Ra0811 & op0007=0xbd & op1215=0x0 ; off1630pc15s & op3131=0x1 +{ + if (Ra0811 != 0) goto off1630pc15s; +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# JNZ.T D[15], n, disp4 (SBRN) +:jnz.t d15,const1215Z,off0811pc4z is PCPMode=0 & const1215Z & d15 & off0811pc4z & op0007=0xae +{ + local tmp = d15 & (1 << const1215Z); + if (tmp != 0) goto off0811pc4z; +} +@endif + +# JNZ.T D[a], n, disp15 (BRN) +:jnz.t Rd0811,Nbit,off1630pc15s is PCPMode=0 & Nbit & Rd0811 & op0006=0x6f ; off1630pc15s & op3131=0x1 +{ + local tmp = Rd0811 & (1 << Nbit); + if (tmp != 0) goto off1630pc15s; +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# JZ D[15], disp8 (SB) +:jz d15,off0815pc8s is PCPMode=0 & d15 & off0815pc8s & op0007=0x6e +{ + if (d15 == 0) goto off0815pc8s; +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_RIDER_B) || defined(TRICORE_V2) +# JZ D[b], disp4 (SBR) +:jz Rd1215,off0811pc4z is PCPMode=0 & Rd1215 & off0811pc4z & op0007=0x76 +{ + if (Rd1215 == 0) goto off0811pc4z; +} +@endif + +# JZ.A A[b], disp4 (SBR) +:jz.a Ra1215,off0811pc4z is PCPMode=0 & Ra1215 & off0811pc4z & op0007=0xbc +{ + if (Ra1215 == 0) goto off0811pc4z; +} + +# JZ.A A[a], disp15 (BRR) +:jz.a Ra0811,off1630pc15s is PCPMode=0 & Ra0811 & op0007=0xbd & op1215=0x0 ; off1630pc15s & op3131=0x0 +{ + if (Ra0811 == 0) goto off1630pc15s; +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# JZ.T D[15], n, disp4 (SBRN) +:jz.t d15,const1215Z,off0811pc4z is PCPMode=0 & const1215Z & d15 & off0811pc4z & op0007=0x2e +{ + local tmp = d15 & (1 << const1215Z); + if (tmp == 0) goto off0811pc4z; +} +@endif + +# JZ.T D[a], n, disp15 (BRN) +:jz.t Rd0811,Nbit,off1630pc15s is PCPMode=0 & Nbit & Rd0811 & op0006=0x6f ; off1630pc15s & op3131=0x0 +{ + local tmp = Rd0811 & (1 << Nbit); + if (tmp == 0) goto off1630pc15s; +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# LD.A A[15], A[10], const8 (SC) +:ld.a a15,SC is PCPMode=0 & a15 & op0007=0xd8 & SC +{ + build SC; + a15 = *[ram]:4 SC; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# LD.A A[c], A[15], off4 (SLRO) +:ld.a Ra0811,SLRO is PCPMode=0 & Ra0811 & op0007=0xc8 & SLRO +{ + build SLRO; + Ra0811 = *[ram]:4 SLRO; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# LD.A A[15], A[b], off4 (SRO) +:ld.a a15,SRO is PCPMode=0 & a15 & op0007=0xcc & SRO +{ + build SRO; + a15 = *[ram]:4 SRO; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# LD.A A[c], A[b] (SLR)(Post-increment Addressing Mode) +# LD.A A[c], A[b] (SLR) +:ld.a Ra0811,SLR is PCPMode=0 & Ra0811 & op0607=0x3 & SLR +{ + build SLR; + Ra0811 = *[ram]:4 SLR; +} +@endif + +# LD.A A[a], A[b], off16 (BOL)(Base + Long Offset Addressing Mode) +:ld.a Ra0811,BOL is PCPMode=0 & ( Ra0811 & op0007=0x99 ) ... & BOL +{ + build BOL; + Ra0811 = *[ram]:4 BOL; +} + +# LD.A A[a], A[b], off10 (BO)(Post-increment Addressing Mode) +# LD.A A[a], P[b] (BO)(Bit-reverse Addressing Mode) +# LD.A A[a], A[b], off10 (BO)(Pre-increment Addressing Mode) +# LD.A A[a], A[b], off10 (BO)(Base + Short Offset Addressing Mode) +# LD.A A[a], P[b] (BO)(Index Addressing Mode) +:ld.a Ra0811,BO is PCPMode=0 & ( Ra0811 & op0607=0x0 ; op2225=0x6 ) & BO +{ + build BO; + Ra0811 = *[ram]:4 BO; +} + +# LD.A A[a], P[b], off10 (BO)(Circular Addressing Mode) +#:ld.a Ra0811,BO is PCPMode=0 & ( Ra0811 & op0007=0x29 ; op2227=0x16 ) & BO +:ld.a Ra0811,[Rpe1215/Rpo1215^"+c"^]off10 is PCPMode=0 & Ra0811 & Rpe1215 & Rpo1215 & op0007=0x29 ; off10 & op2227=0x16 +{ + local EA:4; + CircularAddressingMode(Rpe1215, Rpo1215, EA, off10); + Ra0811 = *[ram]:4 EA; +} + +# LD.A A[a], off18 (ABS)(Absolute Addressing Mode) +:ld.a Ra0811,off18 is PCPMode=0 & ( Ra0811 & op0007=0x85 ; op2627=0x2 ) & off18 +{ + Ra0811 = *[ram]:4 off18; +} + +# LD.B D[a], off18 (ABS)(Absolute Addressing Mode) +:ld.b Rd0811,off18 is PCPMode=0 & ( Rd0811 & op0007=0x5 ; op2627=0x0 ) & off18 +{ + Rd0811 = sext(*[ram]:1 off18); +} + +# LD.B D[a], A[b], off10 (BO)(Post-increment Addressing Mode) +# LD.B D[a], P[b] (BO)(Bit-reverse Addressing Mode) +# LD.B D[a], A[b], off10 (BO)(Pre-increment Addressing Mode) +# LD.B D[a], A[b], off10 (BO)(Base + Short Offset Addressing Mode) +# LD.B D[a], P[b] (BO)(Index Addressing Mode) +:ld.b Rd0811,BO is PCPMode=0 & ( Rd0811 & op0607=0x0 ; op2225=0x0 ) & BO +{ + build BO; + Rd0811 = sext(*[ram]:1 BO); +} + +# LD.B D[a], P[b], off10 (BO)(Circular Addressing Mode) +#:ld.b Rd0811,BO is PCPMode=0 & ( Rd0811 & op0007=0x29 ; op2227=0x10 ) & BO +:ld.b Rd0811,[Rpe1215/Rpo1215^"+c"^]off10 is PCPMode=0 & Rd0811 & Rpe1215 & Rpo1215 & op0007=0x29 ; off10 & op2227=0x10 +{ + local EA:4; + CircularAddressingMode(Rpe1215, Rpo1215, EA, off10); + Rd0811 = sext(*[ram]:1 EA); +} + +# LD.B D[a], A[b], off16 (BOL)(Base + Long Offset Addressing Mode) +:ld.b Rd0811,BOL is PCPMode=0 & ( Rd0811 & op0007=0x79 ) ... & BOL +{ + build BOL; + Rd0811 = sext(*[ram]:1 BOL); +} + +# LD.BU D[a], A[b], off16 (BOL)(Base + Long Offset Addressing Mode) +:ld.bu Rd0811,BOL is PCPMode=0 & ( Rd0811 & op0007=0x39 ) ... & BOL +{ + build BOL; + Rd0811 = zext(*[ram]:1 BOL); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# LD.BU D[c], A[b] (SLR) +# LD.BU D[c], A[b] (SLR)(Post-increment Addressing Mode) +:ld.bu Rd0811,SLR is PCPMode=0 & Rd0811 & op0607=0x0 & SLR +{ + build SLR; + Rd0811 = zext(*[ram]:1 SLR); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# LD.BU D[15], A[b], off4 (SRO) +:ld.bu d15,SRO is PCPMode=0 & d15 & op0007=0xc & SRO +{ + build SRO; + d15 = zext(*[ram]:1 SRO); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# LD.BU D[c], A[15], off4 (SLRO) +:ld.bu Rd0811,SLRO is PCPMode=0 & Rd0811 & op0007=0x8 & SLRO +{ + build SLRO; + Rd0811 = zext(*[ram]:1 SLRO); +} +@endif + +# LD.BU D[a], A[b], off10 (BO)(Post-increment Addressing Mode) +# LD.BU D[a], P[b] (BO)(Bit-reverse Addressing Mode) +# LD.BU D[a], A[b], off10 (BO)(Pre-increment Addressing Mode) +# LD.BU D[a], A[b], off10 (BO)(Base + Short Offset Addressing Mode) +# LD.BU D[a], P[b] (BO)(Index Addressing Mode) +:ld.bu Rd0811,BO is PCPMode=0 & ( Rd0811 & op0607=0x0 ; op2225=0x1 ) & BO +{ + build BO; + Rd0811 = zext(*[ram]:1 BO); +} + +# LD.BU D[a], off18 (ABS)(Absolute Addressing Mode) +:ld.bu Rd0811,off18 is PCPMode=0 & ( Rd0811 & op0007=0x5 ; op2627=0x1 ) & off18 +{ + Rd0811 = zext(*[ram]:1 off18); +} + +# LD.BU D[a], P[b], off10 (BO)(Circular Addressing Mode) +#:ld.bu Rd0811,BO is PCPMode=0 & ( Rd0811 & op0007=0x29 ; op2227=0x11 ) & BO +:ld.bu Rd0811,[Rpe1215/Rpo1215^"+c"^]off10 is PCPMode=0 & Rd0811 & Rpe1215 & Rpo1215 & op0007=0x29 ; off10 & op2227=0x11 +{ + local EA:4; + CircularAddressingMode(Rpe1215, Rpo1215, EA, off10); + Rd0811 = zext(*[ram]:1 EA); +} + +# LD.D E[a], A[b], off10 (BO)(Post-increment Addressing Mode) +# LD.D E[a], P[b] (BO)(Bit-reverse Addressing Mode) +# LD.D E[a], A[b], off10 (BO)(Pre-increment Addressing Mode) +# LD.D E[a], A[b], off10 (BO)(Base + Short Offset Addressing Mode) +# LD.D E[a], P[b] (BO)(Index Addressing Mode) +:ld.d Re0811,BO is PCPMode=0 & ( Re0811 & op0607=0x0 ; op2225=0x5 ) & BO +{ + build BO; + Re0811 = *[ram]:8 BO; +} + +# LD.D E[a], off18 (ABS)(Absolute Addressing Mode) +:ld.d Re0811,off18 is PCPMode=0 & ( Re0811 & op0007=0x85 ; op2627=0x1 ) & off18 +{ + Re0811 = *[ram]:8 off18; +} + +# LD.D E[a], P[b], off10 (BO)(Circular Addressing Mode) +#:ld.d Re0811,BO is PCPMode=0 & ( Re0811 & op0007=0x29 ; op2227=0x15 ) & BO +:ld.d Re0811,[Rpe1215/Rpo1215^"+c"^]off10 is PCPMode=0 & Re0811 & Rpe1215 & Rpo1215 & op0007=0x29 ; off10 & op2227=0x15 +{ + local EA0:4; + local EA2:4; + local EA4:4; + local EA6:4; + CircularAddressingMode4(Rpe1215, Rpo1215, EA0, EA2, EA4, EA6, off10, 2); + Re0811[48,16] = *[ram]:2 EA6; + Re0811[32,16] = *[ram]:2 EA4; + Re0811[16,16] = *[ram]:2 EA2; + Re0811[0,16] = *[ram]:2 EA0; +} + +# LD.DA P[a], A[b], off10 (BO)(Post-increment Addressing Mode) +# LD.DA P[a], P[b] (BO)(Bit-reverse Addressing Mode) +# LD.DA P[a], A[b], off10 (BO)(Pre-increment Addressing Mode) +# LD.DA P[a], A[b], off10 (BO)(Base + Short Offset Addressing Mode) +# LD.DA P[a], P[b] (BO)(Index Addressing Mode) +:ld.da Rp0811,BO is PCPMode=0 & ( Rp0811 & op0607=0x0 ; op2225=0x7 ) & BO +{ + build BO; + Rp0811 = *[ram]:8 BO; +} + +# LD.DA P[a], P[b], off10 (BO)(Circular Addressing Mode) +#:ld.da Rpe0811/Rpo0811,BO is PCPMode=0 & ( Rpe0811 & Rpo0811 & op0007=0x29 ; op2227=0x17 ) & BO +:ld.da Rpe0811/Rpo0811,[Rpe1215/Rpo1215^"+c"^]off10 is PCPMode=0 & Rpe0811 & Rpo0811 & Rpe1215 & Rpo1215 & op0007=0x29 ; off10 & op2227=0x17 +{ + local EA0:4; + local EA4:4; + CircularAddressingMode2(Rpe1215, Rpo1215, EA0, EA4, off10, 4); + Rpo0811 = *[ram]:4 EA4; + Rpe0811 = *[ram]:4 EA0; +} + +# LD.DA P[a], off18 (ABS)(Absolute Addressing Mode) +:ld.da Rp0811,off18 is PCPMode=0 & ( Rp0811 & op0007=0x85 ; op2627=0x3 ) & off18 +{ + Rp0811 = *[ram]:8 off18; +} + +@if defined(TRICORE_V2) +:ld.dd Re0811/ReN0811,BO is PCPMode=0 & ( Re0811 & ReN0811 & op0007=0x9 ; op2227=0x9 ) & BO +{ + build BO; + Re0811 = *[ram]:8 BO; + ReN0811 = *[ram]:8 BO+8; +} +@endif + +@if defined(TRICORE_V2) +:ld.dd Re0811/ReN0811,BO is PCPMode=0 & ( Re0811 & ReN0811 & op0007=0x29 ; op1621=0x0 & op2227=0x09 & op2831=0x0 ) & BO +{ + build BO; + Re0811 = *[ram]:8 BO; + ReN0811 = *[ram]:8 BO+8; +} +@endif + +@if defined(TRICORE_V2) +:ld.dd Re0811/ReN0811,BO is PCPMode=0 & ( Re0811 & ReN0811 & op0007=0x9 ; op2227=0x19 ) & BO +{ + build BO; + Re0811 = *[ram]:8 BO; + ReN0811 = *[ram]:8 BO+8; +} +@endif + +@if defined(TRICORE_V2) +#:ld.dd Re0811/ReN0811,BO is PCPMode=0 & ( Re0811 & ReN0811 & op0007=0x29 ; op2227=0x19 ) & BO +:ld.dd Re0811/ReN0811,[Rpe1215/Rpo1215^"+c"^]off10 is PCPMode=0 & Re0811 & ReN0811 & Rpe1215 & Rpo1215 & op0007=0x29 ; off10 & op2227=0x19 +{ + local EA0:4; + local EA8:4; + CircularAddressingMode2(Rpe1215, Rpo1215, EA0, EA8, off10, 8); + Re0811 = *[ram]:8 EA0; + ReN0811 = *[ram]:8 EA8; +} +@endif + +@if defined(TRICORE_V2) +:ld.dd Re0811/ReN0811,BO is PCPMode=0 & ( Re0811 & ReN0811 & op0007=0x9 ; op2227=0x29 ) & BO +{ + build BO; + Re0811 = *[ram]:8 BO; + ReN0811 = *[ram]:8 BO+8; +} +@endif + +@if defined(TRICORE_V2) +:ld.dd Re0811/ReN0811,BO is PCPMode=0 & ( Re0811 & ReN0811 & op0007=0x29 ; op1621=0x0 & op2227=0x29 & op2831=0x0 ) & BO +{ + build BO; + Re0811 = *[ram]:8 BO; + ReN0811 = *[ram]:8 BO+8; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# LD.H D[c], A[b] (SLR)(Post-increment Addressing Mode) +# LD.H D[c], A[b] (SLR) +:ld.h Rd0811,SLR is PCPMode=0 & Rd0811 & op0607=0x2 & SLR +{ + build SLR; + Rd0811 = sext(*[ram]:2 SLR); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# LD.H D[15], A[b], off4 (SRO) +:ld.h d15,SRO is PCPMode=0 & d15 & op0007=0x8c & SRO +{ + build SRO; + d15 = sext(*[ram]:2 SRO); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# LD.H D[c], A[15], off4 (SLRO) +:ld.h Rd0811,SLRO is PCPMode=0 & Rd0811 & op0007=0x88 & SLRO +{ + build SLRO; + Rd0811 = sext(*[ram]:2 SLRO); +} +@endif + +# LD.H D[a], A[b], off10 (BO)(Post-increment Addressing Mode) +# LD.H D[a], P[b] (BO)(Bit-reverse Addressing Mode) +# LD.H D[a], A[b], off10 (BO)(Pre-increment Addressing Mode) +# LD.H D[a], A[b], off10 (BO)(Base + Short Offset Addressing Mode) +# LD.H D[a], P[b] (BO)(Index Addressing Mode) +:ld.h Rd0811,BO is PCPMode=0 & ( Rd0811 & op0607=0x0 ; op2225=0x2 ) & BO +{ + build BO; + Rd0811 = sext(*[ram]:2 BO); +} + +# LD.H D[a], A[b], off16 (BOL)(Base + Long Offset Addressing Mode) +:ld.h Rd0811,BOL is PCPMode=0 & ( Rd0811 & op0007=0xc9 ) ... & BOL +{ + build BOL; + Rd0811 = sext(*[ram]:2 BOL); +} + +#:ld.h Rd0811,BO is PCPMode=0 & ( Rd0811 & op0007=0x29 ; op2227=0x12 ) & BO +:ld.h Rd0811,[Rpe1215/Rpo1215^"+c"^]off10 is PCPMode=0 & Rd0811 & Rpe1215 & Rpo1215 & op0007=0x29 ; off10 & op2227=0x12 +{ + local EA:4; + CircularAddressingMode(Rpe1215, Rpo1215, EA, off10); + Rd0811 = sext(*[ram]:2 EA); +} + +# LD.H D[a], off18 (ABS)(Absolute Addressing Mode) +:ld.h Rd0811,off18 is PCPMode=0 & ( Rd0811 & op0007=0x5 ; op2627=0x2 ) & off18 +{ + Rd0811 = sext(*[ram]:2 off18); +} + +# LD.HU D[a], A[b], off10 (BO)(Post-increment Addressing Mode) +# LD.HU D[a], P[b] (BO)(Bit-reverse Addressing Mode) +# LD.HU D[a], A[b], off10 (BO)(Pre-increment Addressing Mode) +# LD.HU D[a], A[b], off10 (BO)(Base + Short Offset Addressing Mode) +# LD.HU D[a], P[b] (BO)(Index Addressing Mode) +:ld.hu Rd0811,BO is PCPMode=0 & ( Rd0811 & op0607=0x0 ; op2225=0x3 ) & BO +{ + build BO; + Rd0811 = zext(*[ram]:2 BO); +} + +#:ld.hu Rd0811,BO is PCPMode=0 & ( Rd0811 & op0007=0x29 ; op2227=0x13 ) & BO +:ld.hu Rd0811,[Rpe1215/Rpo1215^"+c"^]off10 is PCPMode=0 & Rd0811 & Rpe1215 & Rpo1215 & op0007=0x29 ; off10 & op2227=0x13 +{ + local EA:4; + CircularAddressingMode(Rpe1215, Rpo1215, EA, off10); + Rd0811 = zext(*[ram]:2 EA); +} + +# LD.HU D[a], off18 (ABS)(Absolute Addressing Mode) +:ld.hu Rd0811,off18 is PCPMode=0 & ( Rd0811 & op0007=0x5 ; op2627=0x3 ) & off18 +{ + Rd0811 = zext(*[ram]:2 off18); +} + +# LD.HU D[a], A[b], off16 (BOL)(Base + Long Offset Addressing Mode) +:ld.hu Rd0811,BOL is PCPMode=0 & ( Rd0811 & op0007=0xb9 ) ... & BOL +{ + build BOL; + Rd0811 = zext(*[ram]:2 BOL); +} + +# LD.Q D[a], off18 (ABS)(Absolute Addressing Mode) +:ld.q Rd0811,off18 is PCPMode=0 & ( Rd0811 & op0007=0x45 ; op2627=0x0 ) & off18 +{ + Rd0811 = zext(*[ram]:2 off18) << 16; +} + +# LD.Q D[a], A[b], off10 (BO)(Post-increment Addressing Mode) +# LD.Q D[a], P[b] (BO)(Bit-reverse Addressing Mode) +# LD.Q D[a], A[b], off10 (BO)(Pre-increment Addressing Mode) +# LD.Q D[a], A[b], off10 (BO)(Base + Short Offset Addressing Mode) +# LD.Q D[a], P[b] (BO)(Index Addressing Mode) +:ld.q Rd0811,BO is PCPMode=0 & ( Rd0811 & op0607=0x0 ; op2225=0x8 ) & BO +{ + build BO; + Rd0811 = zext(*[ram]:2 BO) << 16; +} + +# LD.Q D[a], P[b], off10 (BO)(Circular Addressing Mode) +#:ld.q Rd0811,BO is PCPMode=0 & ( Rd0811 & op0007=0x29 ; op2227=0x18 ) & BO +:ld.q Rd0811,[Rpe1215/Rpo1215^"+c"^]off10 is PCPMode=0 & Rd0811 & Rpe1215 & Rpo1215 & op0007=0x29 ; off10 & op2227=0x18 +{ + local EA:4; + CircularAddressingMode(Rpe1215, Rpo1215, EA, off10); + Rd0811 = zext(*[ram]:2 EA) << 16; +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# LD.W D[15], A[10], const8 (SC) +:ld.w d15,SC is PCPMode=0 & d15 & op0007=0x58 & SC +{ + build SC; + d15 = *[ram]:4 SC; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# LD.W D[c], A[b] (SLR) +# LD.W D[c], A[b] (SLR)(Post-increment Addressing Mode) +:ld.w Rd0811,SLR is PCPMode=0 & Rd0811 & op0607=0x1 & SLR +{ + build SLR; + Rd0811 = *[ram]:4 SLR; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# LD.W D[15], A[b], off4 (SRO) +:ld.w d15,SRO is PCPMode=0 & d15 & op0007=0x4c & SRO +{ + build SRO; + d15 = *[ram]:4 SRO; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# LD.W D[c], A[15], off4 (SLRO) +:ld.w Rd0811,SLRO is PCPMode=0 & Rd0811 & op0007=0x48 & SLRO +{ + build SLRO; + Rd0811 = *[ram]:4 SLRO; +} +@endif + +# LD.W D[a], A[b], off16 (BOL)(Base + Long Offset Addressing Mode) +:ld.w Rd0811,BOL is PCPMode=0 & ( Rd0811 & op0007=0x19 ) ... & BOL +{ + build BOL; + Rd0811 = *[ram]:4 BOL; +} + +# LD.W D[a], off18 (ABS)(Absolute Addressing Mode) +:ld.w Rd0811,off18 is PCPMode=0 & ( Rd0811 & op0007=0x85 ; op2627=0x0 ) & off18 +{ + Rd0811 = *[ram]:4 off18; +} + +# LD.W D[a], A[b], off10 (BO)(Post-increment Addressing Mode) +# LD.W D[a], P[b] (BO)(Bit-reverse Addressing Mode) +# LD.W D[a], A[b], off10 (BO)(Pre-increment Addressing Mode) +# LD.W D[a], A[b], off10 (BO)(Base + Short Offset Addressing Mode) +# LD.W D[a], P[b] (BO)(Index Addressing Mode) +:ld.w Rd0811,BO is PCPMode=0 & ( Rd0811 & op0607=0x0 ; op2225=0x4 ) & BO +{ + build BO; + Rd0811 = *[ram]:4 BO; +} + +#:ld.w Rd0811,BO is PCPMode=0 & ( Rd0811 & op0007=0x29 ; op2227=0x14 ) & BO +:ld.w Rd0811,[Rpe1215/Rpo1215^"+c"^]off10 is PCPMode=0 & Rd0811 & Rpe1215 & Rpo1215 & op0007=0x29 ; off10 & op2227=0x14 +{ + local EA0:4; + local EA2:4; + CircularAddressingMode2(Rpe1215, Rpo1215, EA0, EA2, off10, 2); + Rd0811[16,16] = *[ram]:2 EA2; + Rd0811[0,16] = *[ram]:2 EA0; +} + +# LDLCX off18 (ABS)(Absolute Addressing Mode) +:ldlcx off18 is PCPMode=0 & ( op0007=0x15 & op0811=0x0 ; op2627=0x2 ) & off18 +{ + #TODO context + load_lower_context(off18); +} + +# LDLCX A[b], off10 (BO) (Base + Short Index Addressing Mode) +:ldlcx BO is PCPMode=0 & ( op0007=0x49 & op0811=0x0 ; off10 & op2227=0x24 ) & BO +{ + #TODO context + build BO; + load_lower_context(BO); +} + +# LDMST A[b], off10, E[a] (BO)(Post-increment Addressing Mode) +# LDMST P[b], E[a] (BO)(Bit-reverse Addressing Mode) +# LDMST A[b], off10, E[a] (BO)(Pre-increment Addressing Mode) +# LDMST A[b], off10, E[a] (BO)(Base + Short Offset Addressing Mode) +# LDMST P[b], E[a] (BO)(Index Addressing Mode) +:ldmst BO,Ree0811/Reo0811 is PCPMode=0 & ( Ree0811 & Reo0811 & op0607=0x1 ; op2225=0x1 ) & BO +{ + build BO; + local tmp:4 = *[ram]:4 BO; + *[ram]:4 BO = (tmp & ~Reo0811) | (Ree0811 & Reo0811); +} + +# LDMST off18, E[a] (ABS)(Absolute Addressing Mode) +:ldmst off18,Ree0811/Reo0811 is PCPMode=0 & ( Ree0811 & Reo0811 & op0007=0xe5 ; op2627=0x1 ) & off18 +{ + local tmp:4 = *[ram]:4 off18; + *[ram]:4 off18 = (tmp & ~Reo0811) | (Ree0811 & Reo0811); +} + +# LDMST P[b], off10, E[a] (BO)(Circular Addressing Mode) +#:ldmst BO,Ree0811/Reo0811 is PCPMode=0 & ( Ree0811 & Reo0811 & op0007=0x69 ; op2227=0x11 ) & BO +:ldmst [Rpe1215/Rpo1215^"+c"^]off10,Ree0811/Reo0811 is PCPMode=0 & Ree0811 & Reo0811 & Rpe1215 & Rpo1215 & op0007=0x69 ; off10 & op2227=0x11 +{ + local EA:4; + CircularAddressingMode(Rpe1215, Rpo1215, EA, off10); + *[ram]:4 EA = (*[ram]:4 EA & ~Reo0811) | (Ree0811 & Reo0811); +} + +# LDUCX A[b], off10 (BO)(Base + Short Index Addressing Mode) +:lducx BO is PCPMode=0 & ( op0007=0x49 & op0811=0x0 ; off10 & op2227=0x25 ) & BO +{ + #TODO context + build BO; + load_upper_context(BO); +} + +# LDUCX off18 (ABS)(Absolute Addressing Mode) +:lducx off18 is PCPMode=0 & ( op0007=0x15 & op0811=0x0 ; op2627=0x3 ) & off18 +{ + #TODO context + load_upper_context(off18); +} + +# LEA A[a], off18 (ABS)(Absolute Addressing Mode) +:lea Ra0811,off18 is PCPMode=0 & ( Ra0811 & op0007=0xc5 ; op2627=0x0 ) & off18 +{ + Ra0811 = off18; +} + +# LEA A[a], A[b], off16 (BOL)(Base + Long Offset Addressing Mode) +:lea Ra0811,BOL is PCPMode=0 & ( Ra0811 & op0007=0xd9 ) ... & BOL +{ + build BOL; + Ra0811 = BOL; +} + +# LEA A[a], A[b], off10 (BO)(Base + Short Offset Addressing Mode) +:lea Ra0811,BO is PCPMode=0 & ( Ra0811 & op0007=0x49 ; op2227=0x28 ) & BO +{ + build BO; + Ra0811 = BO; +} + +# LOOP A[b], disp4 (SBR) +:loop Ra1215,off0811pc4o is PCPMode=0 & Ra1215 & off0811pc4o & op0007=0xfc +{ + local tmp:4 = Ra1215; + Ra1215 = Ra1215 - 1; + if (tmp != 0) goto off0811pc4o; +} + +# LOOP A[b], disp15 (BRR) +:loop Ra1215,off1630pc15s is PCPMode=0 & Ra1215 & op0007=0xfd & op0811=0x0 ; off1630pc15s & op3131=0x0 +{ + local tmp:4 = Ra1215; + Ra1215 = Ra1215 - 1; + if (tmp != 0) goto off1630pc15s; +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# LOOPU disp15 (BRR) +:loopu off1630pc15s is PCPMode=0 & op0007=0xfd & op0815=0x0 ; off1630pc15s & op3131=0x1 +{ + goto off1630pc15s; +} +@endif + +# LT D[15], D[a], D[b] (SRR) +:lt d15,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & d15 & op0007=0x7a +{ + d15 = zext(Rd0811 s< Rd1215); +} + +# LT D[15], D[a], const4 (SRC) +:lt d15,Rd0811,const1215S is PCPMode=0 & Rd0811 & const1215S & d15 & op0007=0xfa +{ + d15 = zext(Rd0811 s< const1215S); +} + +# LT D[c], D[a], D[b] (RR) +:lt Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x120 +{ + Rd2831 = zext(Rd0811 s< Rd1215); +} + +# LT D[c], D[a], const9 (RC) +:lt Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x12 ) & const1220S +{ + Rd2831 = zext(Rd0811 s< const1220S); +} + +# LT.A D[c], A[a], A[b] (RR) +:lt.a Rd2831,Ra0811,Ra1215 is PCPMode=0 & Ra0811 & Ra1215 & op0007=0x1 ; Rd2831 & op1627=0x420 +{ + Rd2831 = zext(Ra0811 s< Ra1215); +} + +# LT.B D[c], D[a], D[b] (RR) +:lt.b Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x520 +{ + local result3:4 = 0xff * zext(Rd0811[24,8] s< Rd1215[24,8]); + local result2:4 = 0xff * zext(Rd0811[16,8] s< Rd1215[16,8]); + local result1:4 = 0xff * zext(Rd0811[8,8] s< Rd1215[8,8]); + local result0:4 = 0xff * zext(Rd0811[0,8] s< Rd1215[0,8]); + Rd2831 = (result3 << 24) | (result2 << 16) | (result1 << 8) | (result0); +} + +# LT.BU D[c], D[a], D[b] (RR) +:lt.bu Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x530 +{ + local result3:4 = 0xff * zext(Rd0811[24,8] < Rd1215[24,8]); + local result2:4 = 0xff * zext(Rd0811[16,8] < Rd1215[16,8]); + local result1:4 = 0xff * zext(Rd0811[8,8] < Rd1215[8,8]); + local result0:4 = 0xff * zext(Rd0811[0,8] < Rd1215[0,8]); + Rd2831 = (result3 << 24) | (result2 << 16) | (result1 << 8) | (result0); +} + +# LT.H D[c], D[a], D[b] (RR) +:lt.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x720 +{ + result1:4 = 0xffff * zext(Rd0811[16,16] s< Rd1215[16,16]); + result0:4 = 0xffff * zext(Rd0811[0,16] s< Rd1215[0,16]); + Rd2831 = (result1 << 16) | (result0); +} + +# LT.HU D[c], D[a], D[b] (RR) +:lt.hu Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x730 +{ + local result1:4 = 0xffff * zext(Rd0811[16,16] < Rd1215[16,16]); + local result0:4 = 0xffff * zext(Rd0811[0,16] < Rd1215[0,16]); + Rd2831 = (result1 << 16) | (result0); +} + +# LT.U D[c], D[a], D[b] (RR) +:lt.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x130 +{ + Rd2831 = zext(Rd0811 < Rd1215); +} + +# LT.U D[c], D[a], const9 (RC) +:lt.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x13 ) & const1220Z +{ + Rd2831 = zext(Rd0811 < const1220Z); +} + +# LT.W D[c], D[a], D[b] (RR) +:lt.w Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x920 +{ + Rd2831 = 0xFFFFFFFF * zext(Rd0811 s< Rd1215); +} + +# LT.WU D[c], D[a], D[b] (RR) +:lt.wu Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x930 +{ + Rd2831 = 0xFFFFFFFF * zext(Rd0811 < Rd1215); +} + +# MADD D[c], D[d], D[a], D[b] (RRR2) +:madd Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x3 ; Rd2427 & Rd2831 & op1623=0xa +{ + Rd2831 = Rd2427 + (Rd0811 * Rd1215); + overflowflags(Rd2831); +} + +# MADD D[c], D[d], D[a], const9 (RCR) +:madd Rd2831,Rd2427,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x13 ; Rd2427 & Rd2831 & op2123=0x1 ) & const1220S +{ + Rd2831 = Rd2427 + (Rd0811 * const1220S); + overflowflags(Rd2831); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADD E[c], E[d], D[a], const9 (RCR) +:madd Re2831,Re2427,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x13 ; Re2427 & Re2831 & op2123=0x3 ) & const1220S +{ + Re2831 = Re2427 + sext(Rd0811 * const1220S); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADD E[c], E[d], D[a], D[b] (RRR2) +:madd Re2831,Re2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x3 ; Re2427 & Re2831 & op1623=0x6a +{ + Re2831 = Re2427 + sext(Rd0811 * Rd1215); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADD.F D[c], D[d], D[a], D[b] (RRR) +:madd.f Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x6b ; Rd2427 & Rd2831 & op1623=0x61 +{ + #TODO float + #TODO flags + Rd2831 = Rd2427 f+ (Rd0811 f* Rd1215); +} +@endif + +macro packed_multiply_ul(mres1, mres0, rega, regb, n) { + local sc1 = (rega[16,16] == 0x8000) && (regb[16,16] == 0x8000) && (n == 1); + local sc0 = (rega[0,16] == 0x8000) && (regb[0,16] == 0x8000) && (n == 1); + ternary(mres1, sc1, 0x7FFFFFFF, sext((rega[16,16] * regb[16,16]) << n)); + ternary(mres0, sc0, 0x7FFFFFFF, sext((rega[0,16] * regb[0,16]) << n)); +} + +macro packed_multiply_lu(mres1, mres0, rega, regb, n) { + local sc1 = (rega[16,16] == 0x8000) && (regb[0,16] == 0x8000) && (n == 1); + local sc0 = (rega[0,16] == 0x8000) && (regb[16,16] == 0x8000) && (n == 1); + ternary(mres1, sc1, 0x7FFFFFFF, sext((rega[16,16] * regb[0,16]) << n)); + ternary(mres0, sc0, 0x7FFFFFFF, sext((rega[0,16] * regb[16,16]) << n)); +} + +macro packed_multiply_ll(mres1, mres0, rega, regb, n) { + local sc1 = (rega[16,16] == 0x8000) && (regb[0,16] == 0x8000) && (n == 1); + local sc0 = (rega[0,16] == 0x8000) && (regb[0,16] == 0x8000) && (n == 1); + ternary(mres1, sc1, 0x7FFFFFFF, sext((rega[16,16] * regb[0,16]) << n)); + ternary(mres0, sc0, 0x7FFFFFFF, sext((rega[0,16] * regb[0,16]) << n)); +} + +macro packed_multiply_uu(mres1, mres0, rega, regb, n) { + local sc1 = (rega[0,16] == 0x8000) && (regb[16,16] == 0x8000) && (n == 1); + local sc0 = (rega[16,16] == 0x8000) && (regb[16,16] == 0x8000) && (n == 1); + ternary(mres1, sc1, 0x7FFFFFFF, sext((rega[0,16] * regb[16,16]) << n)); + ternary(mres0, sc0, 0x7FFFFFFF, sext((rega[16,16] * regb[16,16]) << n)); +} + + +macro multiply_l_l(mres0, rega, regb, n) { + local sc0 = (rega[0,16] == 0x8000) && (regb[0,16] == 0x8000) && (n == 1); + ternary(mres0, sc0, 0x7FFFFFFF, sext((rega[0,16] * regb[0,16]) << n)); +} + +macro multiply_u_u(mres0, rega, regb, n) { + local sc0 = (rega[16,16] == 0x8000) && (regb[16,16] == 0x8000) && (n == 1); + ternary(mres0, sc0, 0x7FFFFFFF, sext((rega[16,16] * regb[16,16]) << n)); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADD.H E[c], E[d], D[a], D[b] UL, n (RRR1) +:madd.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x18 +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result1:4 = Reo2427 + mres1; + local result0:4 = Ree2427 + mres0; + Reo2831 = result1; + Ree2831 = result0; + overflowflagsww(result1, result0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADD.H E[c], E[d], D[a], D[b] LU, n (RRR1) +:madd.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x19 +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result1:4 = Reo2427 + mres1; + local result0:4 = Ree2427 + mres0; + Reo2831 = result1; + Ree2831 = result0; + overflowflagsww(result1, result0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADD.H E[c], E[d], D[a], D[b] LL, n (RRR1) +:madd.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x1a +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result1:4 = Reo2427 + mres1; + local result0:4 = Ree2427 + mres0; + Reo2831 = result1; + Ree2831 = result0; + overflowflagsww(result1, result0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADD.H E[c], E[d], D[a], D[b] UU, n (RRR1) +:madd.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x1b +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result1:4 = Reo2427 + mres1; + local result0:4 = Ree2427 + mres0; + Reo2831 = result1; + Ree2831 = result0; + overflowflagsww(result1, result0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADD.Q D[c], D[d], D[a] U, D[b] U, n (RRR1) +:madd.q Rd2831,Rd2427,Rd0811^"u",Rd1215^"u",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x4 +{ + local mres:4; + multiply_u_u(mres, Rd0811, Rd1215, const1617Z); + Rd2831 = Rd2427 + mres; + overflowflags(Rd2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADD.Q D[c], D[d], D[a], D[b] U, n (RRR1) +:madd.q Rd2831,Rd2427,Rd0811,Rd1215^"u",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x0 +{ + local tmp:8 = sext(Rd0811 * sext(Rd1215[16,16])); + tmp = (tmp << const1617Z) s>> 16; + Rd2831 = Rd2427 + tmp[0,32]; + overflowflags(Rd2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADD.Q D[c], D[d], D[a], D[b] L, n (RRR1) +:madd.q Rd2831,Rd2427,Rd0811,Rd1215^"l",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x1 +{ + local tmp:8 = sext(Rd0811 * sext(Rd1215[0,16])); + tmp = (tmp << const1617Z) s>> 16; + Rd2831 = Rd2427 + tmp[0,32]; + overflowflags(Rd2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADD.Q D[c], D[d], D[a], D[b], n (RRR1) +:madd.q Rd2831,Rd2427,Rd0811,Rd1215,const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2 +{ + local tmp:8 = sext(Rd0811 * Rd1215); + tmp = (tmp << const1617Z) s>> 32; + Rd2831 = Rd2427 + tmp[0,32]; + overflowflags(Rd2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADD.Q D[c], D[d], D[a] L, D[b] L, n (RRR1) +:madd.q Rd2831,Rd2427,Rd0811^"l",Rd1215^"l",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x5 +{ + local mres:4; + multiply_l_l(mres, Rd0811, Rd1215, const1617Z); + Rd2831 = Rd2427 + mres; + overflowflags(Rd2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADD.Q E[c], E[d], D[a], D[b] U, n (RRR1) +:madd.q Re2831,Re2427,Rd0811,Rd1215^"u",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Re2427 & Re2831 & const1617Z & op1823=0x18 +{ + local tmp:8 = sext(Rd0811 * sext(Rd1215[16,16])); + Re2831 = Re2427 + (tmp << const1617Z); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADD.Q E[c], E[d], D[a], D[b] L, n (RRR1) +:madd.q Re2831,Re2427,Rd0811,Rd1215^"l",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Re2427 & Re2831 & const1617Z & op1823=0x19 +{ + local tmp:8 = sext(Rd0811 * sext(Rd1215[0,16])); + Re2831 = Re2427 + (tmp << const1617Z); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADD.Q E[c], E[d], D[a], D[b], n (RRR1) +:madd.q Re2831,Re2427,Rd0811,Rd1215,const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Re2427 & Re2831 & const1617Z & op1823=0x1b +{ + local tmp:8 = sext(Rd0811 * Rd1215); + Re2831 = Re2427 + (tmp << const1617Z); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADD.Q E[c], E[d], D[a] U, D[b] U, n (RRR1) +:madd.q Re2831,Re2427,Rd0811^"u",Rd1215^"u",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Re2427 & Re2831 & const1617Z & op1823=0x1c +{ + local mres:4; + multiply_u_u(mres, Rd0811, Rd1215, const1617Z); + Re2831 = Re2427 + sext(mres << 16); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADD.Q E[c], E[d], D[a] L, D[b] L, n (RRR1) +:madd.q Re2831,Re2427,Rd0811^"l",Rd1215^"l",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Re2427 & Re2831 & const1617Z & op1823=0x1d +{ + local mres:4; + multiply_l_l(mres, Rd0811, Rd1215, const1617Z); + Re2831 = Re2427 + (sext(mres) << 16); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADD.U E[c], E[d], D[a], const9 (RCR) +:madd.u Re2831,Re2427,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x13 ; Re2427 & Re2831 & op2123=0x2 ) & const1220Z +{ + Re2831 = Re2427 + zext(Rd0811 * const1220Z); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADD.U E[c], E[d], D[a], D[b] (RRR2) +:madd.u Re2831,Re2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x3 ; Re2427 & Re2831 & op1623=0x68 +{ + Re2831 = Re2427 + zext(Rd0811 * Rd1215); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDM.H E[c], E[d], D[a], D[b] UL, n (RRR1) +:maddm.h Re2831,Re2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Re2427 & Re2831 & const1617Z & op1823=0x1c +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + Re2831 = Re2427 + sext((mres1 + mres0) << 16); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDM.H E[c], E[d], D[a], D[b] LU, n (RRR1) +:maddm.h Re2831,Re2427,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Re2427 & Re2831 & const1617Z & op1823=0x1d +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + Re2831 = Re2427 + sext((mres1 + mres0) << 16); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDM.H E[c], E[d], D[a], D[b] LL, n (RRR1) +:maddm.h Re2831,Re2427,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Re2427 & Re2831 & const1617Z & op1823=0x1e +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + Re2831 = Re2427 + sext((mres1 + mres0) << 16); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDM.H E[c], E[d], D[a], D[b] UU, n (RRR1) +:maddm.h Re2831,Re2427,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Re2427 & Re2831 & const1617Z & op1823=0x1f +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + Re2831 = Re2427 + sext((mres1 + mres0) << 16); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDMS.H E[c], E[d], D[a], D[b] UL, n (RRR1) +:maddms.h Re2831,Re2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Re2427 & Re2831 & const1617Z & op1823=0x3c +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result:8 = Re2427 + sext((mres1 + mres0) << 16); + ssov(Re2831, result, 64); + overflowflagsd(result); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDMS.H E[c], E[d], D[a], D[b] LU, n (RRR1) +:maddms.h Re2831,Re2427,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Re2427 & Re2831 & const1617Z & op1823=0x3d +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result:8 = Re2427 + sext((mres1 + mres0) << 16); + ssov(Re2831, result, 64); + overflowflagsd(result); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDMS.H E[c], E[d], D[a], D[b] LL, n (RRR1) +:maddms.h Re2831,Re2427,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Re2427 & Re2831 & const1617Z & op1823=0x3e +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result:8 = Re2427 + sext((mres1 + mres0) << 16); + ssov(Re2831, result, 64); + overflowflagsd(result); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDMS.H E[c], E[d], D[a], D[b] UU, n (RRR1) +:maddms.h Re2831,Re2427,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Re2427 & Re2831 & const1617Z & op1823=0x3f +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result:8 = Re2427 + sext((mres1 + mres0) << 16); + ssov(Re2831, result, 64); + overflowflagsd(result); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDR.H D[c], E[d], D[a], D[b] UL, n (RRR1) +:maddr.h Rd2831,Ree2427/Reo2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2831 & Ree2427 & Reo2427 & const1617Z & op1823=0x1e +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = Reo2427 + mres1 + 0x8000; + local res0:4 = Ree2427 + mres0 + 0x8000; + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); + overflowflagsww(res1, res0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDR.H D[c], D[d], D[a], D[b] UL, n (RRR1) +:maddr.h Rd2831,Rd2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Rd2427 & Rd2831 & const1617Z & op1823=0xc +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) + mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) + mres0 + 0x8000; + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); + overflowflagsww(res1, res0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDR.H D[c], D[d], D[a], D[b] LU, n (RRR1) +:maddr.h Rd2831,Rd2427,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Rd2427 & Rd2831 & const1617Z & op1823=0xd +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) + mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) + mres0 + 0x8000; + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); + overflowflagsww(res1, res0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDR.H D[c], D[d], D[a], D[b] LL, n (RRR1) +:maddr.h Rd2831,Rd2427,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Rd2427 & Rd2831 & const1617Z & op1823=0xe +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) + mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) + mres0 + 0x8000; + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); + overflowflagsww(res1, res0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDR.H D[c], D[d], D[a], D[b] UU, n (RRR1) +:maddr.h Rd2831,Rd2427,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Rd2427 & Rd2831 & const1617Z & op1823=0xf +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) + mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) + mres0 + 0x8000; + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); + overflowflagsww(res1, res0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDR.Q D[c], D[d], D[a] U, D[b] U, n (RRR1) +:maddr.q Rd2831,Rd2427,Rd0811^"u",Rd1215^"u",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x6 +{ + local mres:4; + multiply_u_u(mres, Rd0811, Rd1215, const1617Z); + local res:4 = Rd2427 + mres + 0x8000; + Rd2831 = zext(res[16,16]) << 16; + overflowflags(res); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDR.Q D[c], D[d], D[a] L, D[b] L, n (RRR1) +:maddr.q Rd2831,Rd2427,Rd0811^"l",Rd1215^"l",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x7 +{ + local mres:4; + multiply_l_l(mres, Rd0811, Rd1215, const1617Z); + local res:4 = Rd2427 + mres + 0x8000; + Rd2831 = zext(res[16,16]) << 16; + overflowflags(res); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDRS.H D[c], E[d], D[a], D[b] UL, n (RRR1) +:maddrs.h Rd2831,Ree2427/Reo2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2831 & Ree2427 & Reo2427 & const1617Z & op1823=0x3e +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = Reo2427 + mres1 + 0x8000; + local res0:4 = Ree2427 + mres0 + 0x8000; + overflowflagsww(res1, res0); + ssov(res1, res1, 32); + ssov(res0, res0, 32); + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDRS.H D[c], D[d], D[a], D[b] UL, n (RRR1) +:maddrs.h Rd2831,Rd2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2c +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = mres1 + 0x8000; + local res0:4 = mres0 + 0x8000; + res1[16,16] = res1[16,16] + Rd2427[16,16]; + res0[16,16] = res0[16,16] + Rd2427[0,16]; + overflowflagsww(res1, res0); + ssov(res1, res1, 32); + ssov(res0, res0, 32); + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDRS.H D[c], D[d], D[a], D[b] LU, n (RRR1) +:maddrs.h Rd2831,Rd2427,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2d +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = mres1 + 0x8000; + local res0:4 = mres0 + 0x8000; + res1[16,16] = res1[16,16] + Rd2427[16,16]; + res0[16,16] = res0[16,16] + Rd2427[0,16]; + overflowflagsww(res1, res0); + ssov(res1, res1, 32); + ssov(res0, res0, 32); + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDRS.H D[c], D[d], D[a], D[b] LL, n (RRR1) +:maddrs.h Rd2831,Rd2427,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2e +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = mres1 + 0x8000; + local res0:4 = mres0 + 0x8000; + res1[16,16] = res1[16,16] + Rd2427[16,16]; + res0[16,16] = res0[16,16] + Rd2427[0,16]; + overflowflagsww(res1, res0); + ssov(res1, res1, 32); + ssov(res0, res0, 32); + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDRS.H D[c], D[d], D[a], D[b] UU, n (RRR1) +:maddrs.h Rd2831,Rd2427,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2f +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = mres1 + 0x8000; + local res0:4 = mres0 + 0x8000; + res1[16,16] = res1[16,16] + Rd2427[16,16]; + res0[16,16] = res0[16,16] + Rd2427[0,16]; + overflowflagsww(res1, res0); + ssov(res1, res1, 32); + ssov(res0, res0, 32); + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDRS.Q D[c], D[d], D[a] U, D[b] U, n (RRR1) +:maddrs.q Rd2831,Rd2427,Rd0811^"u",Rd1215^"u",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x26 +{ + local mres:4; + multiply_u_u(mres, Rd0811, Rd1215, const1617Z); + local res:4 = Rd2427 + mres + 0x8000; + overflowflags(res); + ssov(res, res, 32); + Rd2831 = zext(res[16,16]) << 16; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDRS.Q D[c], D[d], D[a] L, D[b] L, n (RRR1) +:maddrs.q Rd2831,Rd2427,Rd0811^"l",Rd1215^"l",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x27 +{ + local mres:4; + multiply_l_l(mres, Rd0811, Rd1215, const1617Z); + local res:4 = Rd2427 + mres + 0x8000; + overflowflags(res); + ssov(res, res, 32); + Rd2831 = zext(res[16,16]) << 16; +} +@endif + +# MADDS D[c], D[d], D[a], D[b] (RRR2) +:madds Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x3 ; Rd2427 & Rd2831 & op1623=0x8a +{ + local result:4 = Rd2427 + (Rd0811 * Rd1215); + overflowflags(result); + ssov(Rd2831, result, 32); +} + +# MADDS D[c], D[d], D[a], const9 (RCR) +:madds Rd2831,Rd2427,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x13 ; Rd2427 & Rd2831 & op2123=0x5 ) & const1220S +{ + local result:4 = Rd2427 + (Rd0811 * const1220S); + overflowflags(result); + ssov(Rd2831, result, 32); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDS E[c], E[d], D[a], const9 (RCR) +:madds Re2831,Re2427,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x13 ; Re2427 & Re2831 & op2123=0x7 ) & const1220S +{ + local result:8 = Re2427 + sext(Rd0811 * const1220S); + overflowflagsd(result); + ssov(Re2831, result, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDS E[c], E[d], D[a], D[b] (RRR2) +:madds Re2831,Re2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x3 ; Re2427 & Re2831 & op1623=0xea +{ + local result:8 = Re2427 + sext(Rd0811 * Rd1215); + overflowflagsd(result); + ssov(Re2831, result, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDS.H E[c], E[d], D[a], D[b] UL, n (RRR1) +:madds.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x38 +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result1:4 = Reo2427 + mres1; + local result0:4 = Ree2427 + mres0; + ssov(Reo2831, result1, 32); + ssov(Ree2831, result0, 32); + overflowflagsww(result1, result0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDS.H E[c], E[d], D[a], D[b] LU, n (RRR1) +:madds.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x39 +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result1:4 = Reo2427 + mres1; + local result0:4 = Ree2427 + mres0; + ssov(Reo2831, result1, 32); + ssov(Ree2831, result0, 32); + overflowflagsww(result1, result0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDS.H E[c], E[d], D[a], D[b] LL, n (RRR1) +:madds.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x3a +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result1:4 = Reo2427 + mres1; + local result0:4 = Ree2427 + mres0; + ssov(Reo2831, result1, 32); + ssov(Ree2831, result0, 32); + overflowflagsww(result1, result0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDS.H E[c], E[d], D[a], D[b] UU, n (RRR1) +:madds.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x83 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x3b +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result1:4 = Reo2427 + mres1; + local result0:4 = Ree2427 + mres0; + ssov(Reo2831, result1, 32); + ssov(Ree2831, result0, 32); + overflowflagsww(result1, result0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDS.Q D[c], D[d], D[a] U, D[b] U, n (RRR1) +:madds.q Rd2831,Rd2427,Rd0811^"u",Rd1215^"u",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x24 +{ + local mres:4; + multiply_u_u(mres, Rd0811, Rd1215, const1617Z); + local result:4 = Rd2427 + mres; + overflowflags(result); + ssov(Rd2831, result, 32); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDS.Q D[c], D[d], D[a], D[b] U, n (RRR1) +:madds.q Rd2831,Rd2427,Rd0811,Rd1215^"u",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x20 +{ + local tmp:8 = sext(Rd0811 * sext(Rd1215[16,16])); + tmp = (tmp << const1617Z) s>> 16; + local result:4 = Rd2427 + tmp[0,32]; + overflowflags(result); + ssov(Rd2831, result, 32); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDS.Q D[c], D[d], D[a], D[b] L, n (RRR1) +:madds.q Rd2831,Rd2427,Rd0811,Rd1215^"l",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x21 +{ + local tmp:8 = sext(Rd0811 * sext(Rd1215[0,16])); + tmp = (tmp << const1617Z) s>> 16; + local result:4 = Rd2427 + tmp[0,32]; + overflowflags(result); + ssov(Rd2831, result, 32); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDS.Q D[c], D[d], D[a], D[b], n (RRR1) +:madds.q Rd2831,Rd2427,Rd0811,Rd1215,const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x22 +{ + local tmp:8 = sext(Rd0811 * Rd1215); + tmp = (tmp << const1617Z) s>> 32; + local result:4 = Rd2427 + tmp[0,32]; + overflowflags(result); + ssov(Rd2831, result, 32); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDS.Q D[c], D[d], D[a] L, D[b] L, n (RRR1) +:madds.q Rd2831,Rd2427,Rd0811^"l",Rd1215^"l",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Rd2427 & Rd2831 & const1617Z & op1823=0x25 +{ + local mres:4; + multiply_l_l(mres, Rd0811, Rd1215, const1617Z); + local result:4 = Rd2427 + mres; + overflowflags(result); + ssov(Rd2831, result, 32); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDS.QE[c], E[d], D[a], D[b] U, n (RRR1) +:madds.q Re2831,Re2427,Rd0811,Rd1215^"u",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Re2427 & Re2831 & const1617Z & op1823=0x38 +{ + local tmp:8 = sext(Rd0811 * sext(Rd1215[16,16])); + local result:8 = Re2427 + (tmp << const1617Z); + overflowflagsd(result); + ssov(Re2831, result, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDS.Q E[c], E[d], D[a], D[b] L, n (RRR1) +:madds.q Re2831,Re2427,Rd0811,Rd1215^"l",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Re2427 & Re2831 & const1617Z & op1823=0x39 +{ + local tmp:8 = sext(Rd0811 * sext(Rd1215[0,16])); + local result:8 = Re2427 + (tmp << const1617Z); + overflowflagsd(result); + ssov(Re2831, result, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDS.Q E[c], E[d], D[a], D[b], n (RRR1) +:madds.q Re2831,Re2427,Rd0811,Rd1215,const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Re2427 & Re2831 & const1617Z & op1823=0x3b +{ + local tmp:8 = sext(Rd0811 * Rd1215); + tmp = tmp << const1617Z; + local result:8 = Re2427 + tmp; + overflowflags(result); + ssov(Re2831, result, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDS.Q E[c], E[d], D[a] U, D[b] U, n (RRR1) +:madds.q Re2831,Re2427,Rd0811^"u",Rd1215^"u",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Re2427 & Re2831 & const1617Z & op1823=0x3c +{ + local mres:4; + multiply_u_u(mres, Rd0811, Rd1215, const1617Z); + local result:8 = Re2427 + sext(mres << 16); + overflowflagsd(result); + ssov(Re2831, result, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDS.Q E[c], E[d], D[a] L, D[b] L, n (RRR1) +:madds.q Re2831,Re2427,Rd0811^"l",Rd1215^"l",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x43 ; Re2427 & Re2831 & const1617Z & op1823=0x3d +{ + local mres:4; + multiply_l_l(mres, Rd0811, Rd1215, const1617Z); + local result:8 = Re2427 + sext(mres << 16); + overflowflagsd(result); + ssov(Re2831, result, 64); +} +@endif + +# MADDS.U D[c], D[d], D[a], const9 (RCR) +:madds.u Rd2831,Rd2427,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x13 ; Rd2427 & Rd2831 & op2123=0x4 ) & const1220Z +{ + local result:4 = Rd2427 + (Rd0811 * const1220Z); + overflowflags(result); + suov(Rd2831, result, 32); +} + +# MADDS.U D[c], D[d], D[a], D[b] (RRR2) +:madds.u Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x3 ; Rd2427 & Rd2831 & op1623=0x88 +{ + local result:4 = Rd2427 + (Rd0811 * Rd1215); + overflowflags(result); + suov(Rd2831, result, 32); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDS.U E[c], E[d], D[a], const9 (RCR) +:madds.u Re2831,Re2427,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x13 ; Re2427 & Re2831 & op2123=0x6 ) & const1220Z +{ + local result:8 = Re2427 + zext(Rd0811 * const1220Z); + overflowflagsd(result); + suov(Re2831, result, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDS.U E[c], E[d], D[a], D[b] (RRR2) +:madds.u Re2831,Re2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x3 ; Re2427 & Re2831 & op1623=0xe8 +{ + local result:8 = Re2427 + zext(Rd0811 * Rd1215); + overflowflags(result); + suov(Re2831, result, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDSU.H E[c], E[d], D[a], D[b] UL, n (RRR1) +:maddsu.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x18 +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result1:4 = Reo2427 + mres1; + local result0:4 = Ree2427 - mres0; + Reo2831 = result1; + Ree2831 = result0; + overflowflagsww(result1, result0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDSU.H E[c], E[d], D[a], D[b] LU, n (RRR1) +:maddsu.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x19 +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result1:4 = Reo2427 + mres1; + local result0:4 = Ree2427 - mres0; + Reo2831 = result1; + Ree2831 = result0; + overflowflagsww(result1, result0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDSU.H E[c], E[d], D[a], D[b] LL, n (RRR1) +:maddsu.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x1a +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result1:4 = Reo2427 + mres1; + local result0:4 = Ree2427 - mres0; + Reo2831 = result1; + Ree2831 = result0; + overflowflagsww(result1, result0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDSU.H E[c], E[d], D[a], D[b] UU, n (RRR1) +:maddsu.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x1b +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result1:4 = Reo2427 + mres1; + local result0:4 = Ree2427 - mres0; + Reo2831 = result1; + Ree2831 = result0; + overflowflagsww(result1, result0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDSUM.H E[c], E[d], D[a], D[b] UL, n (RRR1) +:maddsum.h Re2831,Re2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Re2427 & Re2831 & const1617Z & op1823=0x1c +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + Re2831 = Re2427 + sext((mres1 - mres0) << 16); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDSUM.H E[c], E[d], D[a], D[b] LU, n (RRR1) +:maddsum.h Re2831,Re2427,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Re2427 & Re2831 & const1617Z & op1823=0x1d +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + Re2831 = Re2427 + sext((mres1 - mres0) << 16); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDSUM.H E[c], E[d], D[a], D[b] LL, n (RRR1) +:maddsum.h Re2831,Re2427,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Re2427 & Re2831 & const1617Z & op1823=0x1e +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + Re2831 = Re2427 + sext((mres1 - mres0) << 16); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDSUM.H E[c], E[d], D[a], D[b] UU, n (RRR1) +:maddsum.h Re2831,Re2427,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Re2427 & Re2831 & const1617Z & op1823=0x1f +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + Re2831 = Re2427 + sext((mres1 - mres0) << 16); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDSUMS.H E[c], E[d], D[a], D[b] UL, n (RRR1) +:maddsums.h Re2831,Re2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Re2427 & Re2831 & const1617Z & op1823=0x3c +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result:8 = Re2427 + sext((mres1 - mres0) << 16); + overflowflagsd(result); + ssov(Re2831, result, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDSUMS.H E[c], E[d], D[a], D[b] LU, n (RRR1) +:maddsums.h Re2831,Re2427,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Re2427 & Re2831 & const1617Z & op1823=0x3d +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result:8 = Re2427 + sext((mres1 - mres0) << 16); + overflowflagsd(result); + ssov(Re2831, result, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDSUMS.H E[c], E[d], D[a], D[b] LL, n (RRR1) +:maddsums.h Re2831,Re2427,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Re2427 & Re2831 & const1617Z & op1823=0x3e +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result:8 = Re2427 + sext((mres1 - mres0) << 16); + overflowflagsd(result); + ssov(Re2831, result, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDSUMS.H E[c], E[d], D[a], D[b] UU, n (RRR1) +:maddsums.h Re2831,Re2427,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Re2427 & Re2831 & const1617Z & op1823=0x3f +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result:8 = Re2427 + sext((mres1 - mres0) << 16); + overflowflagsd(result); + ssov(Re2831, result, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDSUR.H D[c], D[d], D[a], D[b] UL, n (RRR1) +:maddsur.h Rd2831,Rd2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Rd2427 & Rd2831 & const1617Z & op1823=0xc +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) + mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000; + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); + overflowflagsww(res1, res0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDSUR.H D[c], D[d], D[a], D[b] LU, n (RRR1) +:maddsur.h Rd2831,Rd2427,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Rd2427 & Rd2831 & const1617Z & op1823=0xd +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) + mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000; + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); + overflowflagsww(res1, res0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDSUR.H D[c], D[d], D[a], D[b] LL, n (RRR1) +:maddsur.h Rd2831,Rd2427,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Rd2427 & Rd2831 & const1617Z & op1823=0xe +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) + mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000; + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); + overflowflagsww(res1, res0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDSUR.H D[c], D[d], D[a], D[b] UU, n (RRR1) +:maddsur.h Rd2831,Rd2427,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Rd2427 & Rd2831 & const1617Z & op1823=0xf +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) + mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000; + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); + overflowflagsww(res1, res0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDSURS.H D[c], D[d], D[a], D[b] UL, n (RRR1) +:maddsurs.h Rd2831,Rd2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2c +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) + mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000; + overflowflagsww(res1, res0); + ssov(res1, res1, 32); + ssov(res0, res0, 32); + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDSURS.H D[c], D[d], D[a], D[b] LU, n (RRR1) +:maddsurs.h Rd2831,Rd2427,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2d +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) + mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000; + overflowflagsww(res1, res0); + ssov(res1, res1, 32); + ssov(res0, res0, 32); + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDSURS.H D[c], D[d], D[a], D[b] LL, n (RRR1) +:maddsurs.h Rd2831,Rd2427,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2e +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) + mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000; + overflowflagsww(res1, res0); + ssov(res1, res1, 32); + ssov(res0, res0, 32); + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDSURS.H D[c], D[d], D[a], D[b] UU, n (RRR1) +:maddsurs.h Rd2831,Rd2427,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2f +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) + mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000; + overflowflagsww(res1, res0); + ssov(res1, res1, 32); + ssov(res0, res0, 32); + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDSUS.H E[c], E[d], D[a], D[b] UL, n (RRR1) +:maddsus.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x38 +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result1:4 = Reo2427 + mres1; + local result0:4 = Ree2427 - mres0; + ssov(Reo2831, result1, 32); + ssov(Ree2831, result0, 32); + overflowflagsww(result1, result0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDSUS.H E[c], E[d], D[a], D[b] LU, n (RRR1) +:maddsus.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x39 +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + ssov(Reo2831, Reo2427 + mres1, 32); + ssov(Ree2831, Ree2427 - mres0, 32); + overflowflagsww(Reo2427 + mres1, Ree2427 - mres0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDSUS.H E[c], E[d], D[a], D[b] LL, n (RRR1) +:maddsus.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x3a +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result1:4 = Reo2427 + mres1; + local result0:4 = Ree2427 - mres0; + ssov(Reo2831, result1, 32); + ssov(Ree2831, result0, 32); + overflowflagsww(result1, result0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MADDSUS.H E[c], E[d], D[a], D[b] UU, n (RRR1) +:maddsus.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x3b +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result1:4 = Reo2427 + mres1; + local result0:4 = Ree2427 - mres0; + ssov(Reo2831, result1, 32); + ssov(Ree2831, result0, 32); + overflowflagsww(result1, result0); +} +@endif + +# MAX D[c], D[a], D[b] (RR) +:max Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x1a0 +{ + ternary(Rd2831, Rd0811 s> Rd1215, Rd0811, Rd1215); +} + +# MAX D[c], D[a], const9 (RC) +:max Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x1a ) & const1220S +{ + ternary(Rd2831, Rd0811 s> const1220S, Rd0811, const1220S); +} + +# MAX.B D[c], D[a], D[b] (RR) +:max.b Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x5a0 +{ + local result3:4; + local result2:4; + local result1:4; + local result0:4; + ternary(result3, (Rd0811[24,8] s> Rd1215[24,8]), zext(Rd0811[24,8]), zext(Rd1215[24,8])); + ternary(result2, (Rd0811[16,8] s> Rd1215[16,8]), zext(Rd0811[16,8]), zext(Rd1215[16,8])); + ternary(result1, (Rd0811[8,8] s> Rd1215[8,8]), zext(Rd0811[8,8]), zext(Rd1215[8,8])); + ternary(result0, (Rd0811[0,8] s> Rd1215[0,8]), zext(Rd0811[0,8]), zext(Rd1215[0,8])); + Rd2831 = (result3 << 24) | (result2 << 16) | (result1 << 8) | (result0); +} + +# MAX.BU D[c], D[a], D[b] (RR) +:max.bu Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x5b0 +{ + local result3:4; + local result2:4; + local result1:4; + local result0:4; + ternary(result3, (Rd0811[24,8] > Rd1215[24,8]), zext(Rd0811[24,8]), zext(Rd1215[24,8])); + ternary(result2, (Rd0811[16,8] > Rd1215[16,8]), zext(Rd0811[16,8]), zext(Rd1215[16,8])); + ternary(result1, (Rd0811[8,8] > Rd1215[8,8]), zext(Rd0811[8,8]), zext(Rd1215[8,8])); + ternary(result0, (Rd0811[0,8] > Rd1215[0,8]), zext(Rd0811[0,8]), zext(Rd1215[0,8])); + Rd2831 = (result3 << 24) | (result2 << 16) | (result1 << 8) | (result0); +} + +# MAX.H D[c], D[a], D[b] (RR) +:max.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x7a0 +{ + local result1:4; + local result0:4; + ternary(result1, (Rd0811[16,16] s> Rd1215[16,16]), zext(Rd0811[16,16]), zext(Rd1215[16,16])); + ternary(result0, (Rd0811[0,16] s> Rd1215[0,16]), zext(Rd0811[0,16]), zext(Rd1215[0,16])); + Rd2831 = (result1 << 16) | (result0); +} + +# MAX.HU D[c], D[a], D[b] (RR) +:max.hu Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x7b0 +{ + local result1:4; + local result0:4; + ternary(result1, (Rd0811[16,16] > Rd1215[16,16]), zext(Rd0811[16,16]), zext(Rd1215[16,16])); + ternary(result0, (Rd0811[0,16] > Rd1215[0,16]), zext(Rd0811[0,16]), zext(Rd1215[0,16])); + Rd2831 = (result1 << 16) | (result0); +} + +# MAX.U D[c], D[a], D[b] (RR) +:max.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x1b0 +{ + ternary(Rd2831, Rd0811 > Rd1215, Rd0811, Rd1215); +} + +# MAX.U D[c], D[a], const9 (RC) +:max.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x1b ) & const1220Z +{ + ternary(Rd2831, Rd0811 > const1220Z, Rd0811, const1220Z); +} + +# MFCR D[c], const16 (RLC) +:mfcr Rd2831,const1227Z is PCPMode=0 & ( op0007=0x4d & op0811=0x0 ; Rd2831 ) & const1227Z +{ + Rd2831 = *[register]:4 const1227Z; +} + +@if defined(TRICORE_V2) +:mffr Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; Rd2831 & op1627=0x1d1 +{ + Rd2831 = *[register]:4 Rd0811; +} +@endif + +# MIN D[c], D[a], D[b] (RR) +:min Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x180 +{ + ternary(Rd2831, Rd0811 s< Rd1215, Rd0811, Rd1215); +} + +# MIN D[c], D[a], const9 (RC) +:min Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x18 ) & const1220S +{ + ternary(Rd2831, Rd0811 s< const1220S, Rd0811, const1220S); +} + +# MIN.B D[c], D[a], D[b] (RR) +:min.b Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x580 +{ + local result3:4; + local result2:4; + local result1:4; + local result0:4; + ternary(result3, (Rd0811[24,8] s< Rd1215[24,8]), zext(Rd0811[24,8]), zext(Rd1215[24,8])); + ternary(result2, (Rd0811[16,8] s< Rd1215[16,8]), zext(Rd0811[16,8]), zext(Rd1215[16,8])); + ternary(result1, (Rd0811[8,8] s< Rd1215[8,8]), zext(Rd0811[8,8]), zext(Rd1215[8,8])); + ternary(result0, (Rd0811[0,8] s< Rd1215[0,8]), zext(Rd0811[0,8]), zext(Rd1215[0,8])); + Rd2831 = (result3 << 24) | (result2 << 16) | (result1 << 8) | (result0); +} + +# MIN.BU D[c], D[a], D[b] (RR) +:min.bu Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x590 +{ + local result3:4; + local result2:4; + local result1:4; + local result0:4; + ternary(result3, (Rd0811[24,8] < Rd1215[24,8]), zext(Rd0811[24,8]), zext(Rd1215[24,8])); + ternary(result2, (Rd0811[16,8] < Rd1215[16,8]), zext(Rd0811[16,8]), zext(Rd1215[16,8])); + ternary(result1, (Rd0811[8,8] < Rd1215[8,8]), zext(Rd0811[8,8]), zext(Rd1215[8,8])); + ternary(result0, (Rd0811[0,8] < Rd1215[0,8]), zext(Rd0811[0,8]), zext(Rd1215[0,8])); + Rd2831 = (result3 << 24) | (result2 << 16) | (result1 << 8) | (result0); +} + +# MIN.H D[c], D[a], D[b] (RR) +:min.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x780 +{ + local result1:4; + local result0:4; + ternary(result1, (Rd0811[16,16] s< Rd1215[16,16]), zext(Rd0811[16,16]), zext(Rd1215[16,16])); + ternary(result0, (Rd0811[0,16] s< Rd1215[0,16]), zext(Rd0811[0,16]), zext(Rd1215[0,16])); + Rd2831 = (result1 << 16) | (result0); +} + +# MIN.HU D[c], D[a], D[b] (RR) +:min.hu Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x790 +{ + local result1:4; + local result0:4; + ternary(result1, (Rd0811[16,16] < Rd1215[16,16]), zext(Rd0811[16,16]), zext(Rd1215[16,16])); + ternary(result0, (Rd0811[0,16] < Rd1215[0,16]), zext(Rd0811[0,16]), zext(Rd1215[0,16])); + Rd2831 = (result1 << 16) | (result0); +} + +# MIN.U D[c], D[a], D[b] (RR) +:min.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x190 +{ + ternary(Rd2831, Rd0811 < Rd1215, Rd0811, Rd1215); +} + +# MIN.U D[c], D[a], const9 (RC) +:min.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x19 ) & const1220Z +{ + ternary(Rd2831, Rd0811 < const1220Z, Rd0811, const1220Z); +} + +# MOV D[a], D[b] (SRR) +:mov Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x2 +{ + Rd0811 = Rd1215; +} + +# MOV D[a], const4 (SRC) +:mov Rd0811,const1215S is PCPMode=0 & Rd0811 & const1215S & op0007=0x82 +{ + Rd0811 = const1215S; +} + +@if defined(TRICORE_V2) +# MOV E[a], const4 (SRC) +:mov Re0811,const1215S is PCPMode=0 & Re0811 & const1215S & op0007=0xd2 +{ + Re0811 = sext(const1215S); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MOV D[15], const8 (SC) +:mov d15,const0815Z is PCPMode=0 & const0815Z & d15 & op0007=0xda +{ + d15 = const0815Z; +} +@endif + +# MOV D[c], const16 (RLC) +:mov Rd2831,const1227S is PCPMode=0 & ( op0007=0x3b & op0811=0x0 ; Rd2831 ) & const1227S +{ + Rd2831 = const1227S; +} + +# MOV D[c], D[b] (RR) +:mov Rd2831,Rd1215 is PCPMode=0 & Rd1215 & op0007=0xb & op0811=0 ; Rd2831 & op1627=0x1f0 +{ + Rd2831 = Rd1215; +} + +@if defined(TRICORE_V2) +# MOV E[c], const16 (RLC) +:mov Re2831,const1227S is PCPMode=0 & ( op0007=0xfb & op0811=0x0 ; Re2831 ) & const1227S +{ + Re2831 = sext(const1227S); +} +@endif + +@if defined(TRICORE_V2) +# MOV E[c], D[b] (RR) +:mov Re2831,Rd1215 is PCPMode=0 & Rd1215 & op0007=0xb & op0811=0 ; Re2831 & op1627=0x800 +{ + Re2831 = sext(Rd1215); +} +@endif + +@if defined(TRICORE_V2) +# MOV E[c], D[a], D[b] (RR) +:mov Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Ree2831 & Reo2831 & op1627=0x810 +{ + local tmp1 = Rd0811; + local tmp0 = Rd1215; + Reo2831 = tmp1; + Ree2831 = tmp0; +} +@endif + + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MOV.A A[a], const4 (SRC) +:mov.a Ra0811,const1215Z is PCPMode=0 & Ra0811 & const1215Z & op0007=0xa0 +{ + Ra0811 = const1215Z; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MOV.A A[a], D[b] (SRR) +:mov.a Ra0811,Rd1215 is PCPMode=0 & Ra0811 & Rd1215 & op0007=0x60 +{ + Ra0811 = Rd1215; +} +@endif + +# MOV.A A[c], D[b] (RR) +:mov.a Ra2831,Rd1215 is PCPMode=0 & Rd1215 & op0007=0x1 & op0811=0x0 ; Ra2831 & op1627=0x630 +{ + Ra2831 = Rd1215; +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MOV.AA A[a], A[b] (SRR) +:mov.aa Ra0811,Ra1215 is PCPMode=0 & Ra0811 & Ra1215 & op0007=0x40 +{ + Ra0811 = Ra1215; +} +@endif + +# MOV.AA A[c], A[b] (RR) +:mov.aa Ra2831,Ra1215 is PCPMode=0 & Ra1215 & op0007=0x1 & op0811=0x0 ; Ra2831 & op1627=0x0 +{ + Ra2831 = Ra1215; +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MOV.D D[a], A[b] (SRR) +:mov.d Rd0811,Ra1215 is PCPMode=0 & Ra1215 & Rd0811 & op0007=0x80 +{ + Rd0811 = Ra1215; +} +@endif + +# MOV.D D[c], A[b] (RR) +:mov.d Rd2831,Ra1215 is PCPMode=0 & Ra1215 & op0007=0x1 & op0811=0x0 ; Rd2831 & op1627=0x4c0 +{ + Rd2831 = Ra1215; +} + +# MOV.U D[c], const16 (RLC) +:mov.u Rd2831,const1227Z is PCPMode=0 & ( op0007=0xbb & op0811=0x0 ; Rd2831 ) & const1227Z +{ + Rd2831 = const1227Z; +} + +# MOVH D[c], const16 (RLC) +:movh Rd2831,const1227Z is PCPMode=0 & ( op0007=0x7b & op0811=0x0 ; Rd2831 ) & const1227Z +{ + Rd2831 = const1227Z << 16; +} + +# MOVH.A A[c], const16 (RLC) +:movh.a Ra2831,const1227Z is PCPMode=0 & ( op0007=0x91 & op0811=0x0 ; Ra2831 ) & const1227Z +{ + Ra2831 = const1227Z << 16; +} + +#MSUB D[c], D[d], D[a], D[b] (RRR2) +:msub Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x23 ; Rd2427 & Rd2831 & op1623=0xa +{ + Rd2831 = Rd2427 - (Rd0811 * Rd1215); + overflowflags(Rd2831); +} + +# MSUB D[c], D[d], D[a], const9 (RCR) +:msub Rd2831,Rd2427,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x33 ; Rd2427 & Rd2831 & op2123=0x1 ) & const1220S +{ + Rd2831 = Rd2427 - (Rd0811 * const1220S); + overflowflags(Rd2831); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUB E[c], E[d], D[a], const9 (RCR) +:msub Re2831,Re2427,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x33 ; Re2427 & Re2831 & op2123=0x3 ) & const1220S +{ + Re2831 = Re2427 - sext(Rd0811 * const1220S); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUB E[c], E[d], D[a], D[b] (RRR2) +:msub Re2831,Re2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x23 ; Re2427 & Re2831 & op1623=0x6a +{ + Re2831 = Re2427 - sext(Rd0811 * Rd1215); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUB.F D[c], D[d], D[a], D[b] (RRR) +:msub.f Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x6b ; Rd2427 & Rd2831 & op1623=0x71 +{ + #TODO float + #TODO flags + Rd2831 = Rd2427 f- (Rd0811 f* Rd1215); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUB.H E[c], E[d], D[a], D[b] UL, n (RRR1) +:msub.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x18 +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result1:4 = Reo2427 - mres1; + local result0:4 = Ree2427 - mres0; + Reo2831 = result1; + Ree2831 = result0; + overflowflagsww(result1, result0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUB.H E[c], E[d], D[a], D[b] LU, n (RRR1) +:msub.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x19 +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result1:4 = Reo2427 - mres1; + local result0:4 = Ree2427 - mres0; + Reo2831 = result1; + Ree2831 = result0; + overflowflagsww(result1, result0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUB.H E[c], E[d], D[a], D[b] LL, n (RRR1) +:msub.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x1a +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result1:4 = Reo2427 - mres1; + local result0:4 = Ree2427 - mres0; + Reo2831 = result1; + Ree2831 = result0; + overflowflagsww(result1, result0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUB.H E[c], E[d], D[a], D[b] UU, n (RRR1) +:msub.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x1b +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result1:4 = Reo2427 - mres1; + local result0:4 = Ree2427 - mres0; + Reo2831 = result1; + Ree2831 = result0; + overflowflagsww(result1, result0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUB.Q D[c], D[d], D[a] U, D[b] U, n (RRR1) +:msub.q Rd2831,Rd2427,Rd0811^"u",Rd1215^"u",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x4 +{ + local mres:4; + multiply_u_u(mres, Rd0811, Rd1215, const1617Z); + Rd2831 = Rd2427 - mres; + overflowflags(Rd2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUB.Q D[c], D[d], D[a], D[b] U, n (RRR1) +:msub.q Rd2831,Rd2427,Rd0811,Rd1215^"u",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x0 +{ + Rd2831 = Rd2427 - (((Rd0811 * sext(Rd1215[16,16])) << const1617Z) s>> 16); + overflowflags(Rd2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUB.Q D[c], D[d], D[a], D[b] L, n (RRR1) +:msub.q Rd2831,Rd2427,Rd0811,Rd1215^"l",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x1 +{ + Rd2831 = Rd2427 - (((Rd0811 * sext(Rd1215[0,16])) << const1617Z) s>> 16); + overflowflags(Rd2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUB.Q D[c], D[d], D[a], D[b], n (RRR1) +:msub.q Rd2831,Rd2427,Rd0811,Rd1215,const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2 +{ + Rd2831 = Rd2427 - (((Rd0811 * Rd1215) << const1617Z) s>> 32); + overflowflags(Rd2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUB.Q D[c], D[d], D[a] L, D[b] L, n (RRR1) +:msub.q Rd2831,Rd2427,Rd0811^"l",Rd1215^"l",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x5 +{ + local mres:4; + multiply_l_l(mres, Rd0811, Rd1215, const1617Z); + Rd2831 = Rd2427 - mres; + overflowflags(Rd2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUB.Q E[c], E[d], D[a], D[b] U, n (RRR1) +:msub.q Re2831,Re2427,Rd0811,Rd1215^"u",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Re2427 & Re2831 & const1617Z & op1823=0x18 +{ + Re2831 = Re2427 - sext((Rd0811 * sext(Rd1215[16,16])) << const1617Z); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUB.Q E[c], E[d], D[a], D[b] L, n (RRR1) +:msub.q Re2831,Re2427,Rd0811,Rd1215^"l",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Re2427 & Re2831 & const1617Z & op1823=0x19 +{ + Re2831 = Re2427 - sext((Rd0811 * sext(Rd1215[0,16])) << const1617Z); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUB.Q E[c], E[d], D[a], D[b], n (RRR1) +:msub.q Re2831,Re2427,Rd0811,Rd1215,const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Re2427 & Re2831 & const1617Z & op1823=0x1b +{ + Re2831 = Re2427 - sext((Rd0811 * Rd1215) << const1617Z); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUB.Q E[c], E[d], D[a] U, D[b] U, n (RRR1) +:msub.q Re2831,Re2427,Rd0811^"u",Rd1215^"u",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Re2427 & Re2831 & const1617Z & op1823=0x1c +{ + local mres:4; + multiply_u_u(mres, Rd0811, Rd1215, const1617Z); + Re2831 = Re2427 - sext(mres << 16); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# SUB.Q E[c], E[d], D[a] L, D[b] L, n (RRR1) +:msub.q Re2831,Re2427,Rd0811^"l",Rd1215^"l",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Re2427 & Re2831 & const1617Z & op1823=0x1d +{ + local mres:4; + multiply_l_l(mres, Rd0811, Rd1215, const1617Z); + Re2831 = Re2427 - sext(mres << 16); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUB.U E[c], E[d], D[a], const9 (RCR) +:msub.u Re2831,Re2427,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x33 ; Re2427 & Re2831 & op2123=0x2 ) & const1220Z +{ + Re2831 = Re2427 - zext(Rd0811 * const1220Z); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUB.U E[c], E[d], D[a], D[b] (RRR2) +:msub.u Re2831,Re2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x23 ; Re2427 & Re2831 & op1623=0x68 +{ + Re2831 = Re2427 - zext(Rd0811 * Rd1215); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBAD.H E[c], E[d], D[a], D[b] UL, n (RRR1) +:msubad.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x18 +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = Reo2427 - mres1; + local res0:4 = Ree2427 + mres0; + Reo2831 = res1; + Ree2831 = res0; + overflowflagsww(res1, res0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBAD.H E[c], E[d], D[a], D[b] LU, n (RRR1) +:msubad.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x19 +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = Reo2427 - mres1; + local res0:4 = Ree2427 + mres0; + Reo2831 = res1; + Ree2831 = res0; + overflowflagsww(res1, res0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBAD.H E[c], E[d], D[a], D[b] LL, n (RRR1) +:msubad.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x1a +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = Reo2427 - mres1; + local res0:4 = Ree2427 + mres0; + Reo2831 = res1; + Ree2831 = res0; + overflowflagsww(res1, res0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBAD.H E[c], E[d], D[a], D[b] UU, n (RRR1) +:msubad.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x1b +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = Reo2427 - mres1; + local res0:4 = Ree2427 + mres0; + Reo2831 = res1; + Ree2831 = res0; + overflowflagsww(res1, res0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBADM.H E[c], E[d], D[a], D[b] UL, n (RRR1) +:msubadm.h Re2831,Re2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Re2427 & Re2831 & const1617Z & op1823=0x1c +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + Re2831 = Re2427 - sext((mres1 - mres0) << 16); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBADM.H E[c], E[d], D[a], D[b] LU, n (RRR1) +:msubadm.h Re2831,Re2427,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Re2427 & Re2831 & const1617Z & op1823=0x1d +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + Re2831 = Re2427 - sext((mres1 - mres0) << 16); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBADM.H E[c], E[d], D[a], D[b] LL, n (RRR1) +:msubadm.h Re2831,Re2427,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Re2427 & Re2831 & const1617Z & op1823=0x1e +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + Re2831 = Re2427 - sext((mres1 - mres0) << 16); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBADM.H E[c], E[d], D[a], D[b] UU, n (RRR1) +:msubadm.h Re2831,Re2427,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Re2427 & Re2831 & const1617Z & op1823=0x1f +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + Re2831 = Re2427 - sext((mres1 - mres0) << 16); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBADMS.H E[c], E[d], D[a], D[b] UL, n (RRR1) +:msubadms.h Re2831,Re2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Re2427 & Re2831 & const1617Z & op1823=0x3c +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result:8 = Re2427 - sext((mres1 - mres0) << 16); + overflowflagsd(result); + ssov(Re2831, result, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBADMS.H E[c], E[d], D[a], D[b] LU, n (RRR1) +:msubadms.h Re2831,Re2427,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Re2427 & Re2831 & const1617Z & op1823=0x3d +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result:8 = Re2427 - sext((mres1 - mres0) << 16); + overflowflagsd(result); + ssov(Re2831, result, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBADMS.H E[c], E[d], D[a], D[b] LL, n (RRR1) +:msubadms.h Re2831,Re2427,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Re2427 & Re2831 & const1617Z & op1823=0x3e +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result:8 = Re2427 - sext((mres1 - mres0) << 16); + overflowflagsd(result); + ssov(Re2831, result, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBADMS.H E[c], E[d], D[a], D[b] UU, n (RRR1) +:msubadms.h Re2831,Re2427,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Re2427 & Re2831 & const1617Z & op1823=0x3f +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local result:8 = Re2427 - sext((mres1 - mres0) << 16); + overflowflagsd(result); + ssov(Re2831, result, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBADR.H D[c], D[d], D[a], D[b] UL, n (RRR1) +:msubadr.h Rd2831,Rd2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Rd2427 & Rd2831 & const1617Z & op1823=0xc +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) + mres0 + 0x8000; + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); + overflowflagsww(res1, res0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +:msubadr.h Rd2831,Rd2427,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Rd2427 & Rd2831 & const1617Z & op1823=0xd +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) + mres0 + 0x8000; + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); + overflowflagsww(res1, res0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBADR.H D[c], D[d], D[a], D[b] LL, n (RRR1) +:msubadr.h Rd2831,Rd2427,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Rd2427 & Rd2831 & const1617Z & op1823=0xe +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) + mres0 + 0x8000; + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); + overflowflagsww(res1, res0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBADR.H D[c], D[d], D[a], D[b] UU, n (RRR1) +:msubadr.h Rd2831,Rd2427,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Rd2427 & Rd2831 & const1617Z & op1823=0xf +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) + mres0 + 0x8000; + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); + overflowflagsww(res1, res0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBADRS.H D[c], D[d], D[a], D[b] UL, n (RRR1) +:msubadrs.h Rd2831,Rd2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2c +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) + mres0 + 0x8000; + overflowflagsww(res1, res0); + ssov(res1, res1, 32); + ssov(res0, res0, 32); + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBADRS.H D[c], D[d], D[a], D[b] LU, n (RRR1) +:msubadrs.h Rd2831,Rd2427,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2d +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) + mres0 + 0x8000; + overflowflagsww(res1, res0); + ssov(res1, res1, 32); + ssov(res0, res0, 32); + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBADRS.H D[c], D[d], D[a], D[b] LL, n (RRR1) +:msubadrs.h Rd2831,Rd2427,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2e +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) + mres0 + 0x8000; + overflowflagsww(res1, res0); + ssov(res1, res1, 32); + ssov(res0, res0, 32); + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBADRS.H D[c], D[d], D[a], D[b] UU, n (RRR1) +:msubadrs.h Rd2831,Rd2427,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2f +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) + mres0 + 0x8000; + overflowflagsww(res1, res0); + ssov(res1, res1, 32); + ssov(res0, res0, 32); + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBADS.H E[c], E[d], D[a], D[b] UL, n (RRR1) +:msubads.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x38 +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = Reo2427 - mres1; + local res0:4 = Ree2427 + mres0; + overflowflagsww(res1, res0); + ssov(Reo2831, res1, 32); + ssov(Ree2831, res0, 32); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBADS.H E[c], E[d], D[a], D[b] LU, n (RRR1) +:msubads.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x39 +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = Reo2427 - mres1; + local res0:4 = Ree2427 + mres0; + overflowflagsww(res1, res0); + ssov(Reo2831, res1, 32); + ssov(Ree2831, res0, 32); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBADS.H E[c], E[d], D[a], D[b] LL, n (RRR1) +:msubads.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x3a +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = Reo2427 - mres1; + local res0:4 = Ree2427 + mres0; + overflowflagsww(res1, res0); + ssov(Reo2831, res1, 32); + ssov(Ree2831, res0, 32); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBADS.H E[c], E[d], D[a], D[b] UU, n (RRR1) +:msubads.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x3b +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = Reo2427 - mres1; + local res0:4 = Ree2427 + mres0; + overflowflagsww(res1, res0); + ssov(Reo2831, res1, 32); + ssov(Ree2831, res0, 32); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBM.H E[c], E[d], D[a], D[b] UL, n (RRR1) +:msubm.h Re2831,Re2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Re2427 & Re2831 & const1617Z & op1823=0x1c +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res:8 = Re2427 - (sext(mres1 + mres0) << 16); + overflowflagsd(res); + Re2831 = res; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBM.H E[c], E[d], D[a], D[b] LU, n (RRR1) +:msubm.h Re2831,Re2427,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Re2427 & Re2831 & const1617Z & op1823=0x1d +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res:8 = Re2427 - (sext(mres1 + mres0) << 16); + overflowflagsd(res); + Re2831 = res; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBM.H E[c], E[d], D[a], D[b] LL, n (RRR1) +:msubm.h Re2831,Re2427,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Re2427 & Re2831 & const1617Z & op1823=0x1e +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res:8 = Re2427 - (sext(mres1 + mres0) << 16); + overflowflagsd(res); + Re2831 = res; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBM.H E[c], E[d], D[a], D[b] UU, n (RRR1) +:msubm.h Re2831,Re2427,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Re2427 & Re2831 & const1617Z & op1823=0x1f +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res:8 = Re2427 - (sext(mres1 + mres0) << 16); + overflowflagsd(res); + Re2831 = res; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBMS.H E[c], E[d], D[a], D[b] UL, n (RRR1) +:msubms.h Re2831,Re2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Re2427 & Re2831 & const1617Z & op1823=0x3c +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res:8 = Re2427 - (sext(mres1 + mres0) << 16); + overflowflagsd(res); + ssov(Re2427, res, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBMS.H E[c], E[d], D[a], D[b] LU, n (RRR1) +:msubms.h Re2831,Re2427,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Re2427 & Re2831 & const1617Z & op1823=0x3d +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res:8 = Re2427 - (sext(mres1 + mres0) << 16); + overflowflagsd(res); + ssov(Re2427, res, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBMS.H E[c], E[d], D[a], D[b] LL, n (RRR1) +:msubms.h Re2831,Re2427,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Re2427 & Re2831 & const1617Z & op1823=0x3e +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res:8 = Re2427 - (sext(mres1 + mres0) << 16); + overflowflagsd(res); + ssov(Re2427, res, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBMS.H E[c], E[d], D[a], D[b] UU, n (RRR1) +:msubms.h Re2831,Re2427,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Re2427 & Re2831 & const1617Z & op1823=0x3f +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res:8 = Re2427 - (sext(mres1 + mres0) << 16); + overflowflagsd(res); + ssov(Re2427, res, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBR.H D[c], E[d], D[a], D[b] UL, n (RRR1) +:msubr.h Rd2831,Ree2427/Reo2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2831 & Ree2427 & Reo2427 & const1617Z & op1823=0x1e +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = Reo2427 - mres1 + 0x8000; + local res0:4 = Ree2427 - mres0 + 0x8000; + overflowflagsww(res1,res0); + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBR.H D[c], D[d], D[a], D[b] UL, n (RRR1) +:msubr.h Rd2831,Rd2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Rd2427 & Rd2831 & const1617Z & op1823=0xc +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000; + overflowflagsww(res1,res0); + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBR.H D[c], D[d], D[a], D[b] LU, n (RRR1) +:msubr.h Rd2831,Rd2427,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Rd2427 & Rd2831 & const1617Z & op1823=0xd +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000; + overflowflagsww(res1,res0); + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBR.H D[c], D[d], D[a], D[b] LL, n (RRR1) +:msubr.h Rd2831,Rd2427,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Rd2427 & Rd2831 & const1617Z & op1823=0xe +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000; + overflowflagsww(res1,res0); + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBR.H D[c], D[d], D[a], D[b] UU, n (RRR1) +:msubr.h Rd2831,Rd2427,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Rd2427 & Rd2831 & const1617Z & op1823=0xf +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000; + overflowflagsww(res1,res0); + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBR.Q D[c], D[d], D[a] U, D[b] U, n (RRR1) +:msubr.q Rd2831,Rd2427,Rd0811^"u",Rd1215^"u",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x6 +{ + local mres:4; + multiply_u_u(mres, Rd0811, Rd1215, const1617Z); + local res:4 = Rd2427 - mres + 0x8000; + overflowflags(res); + Rd2831 = zext(res[16,16]) << 16; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBR.Q D[c], D[d], D[a] L, D[b] L, n (RRR1) +:msubr.q Rd2831,Rd2427,Rd0811^"l",Rd1215^"l",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x7 +{ + local mres:4; + multiply_l_l(mres, Rd0811, Rd1215, const1617Z); + local res:4 = Rd2427 - mres + 0x8000; + overflowflags(res); + Rd2831 = zext(res[16,16]) << 16; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBRS.H D[c], E[d], D[a], D[b] UL, n (RRR1) +:msubrs.h Rd2831,Ree2427/Reo2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2831 & Ree2427 & Reo2427 & const1617Z & op1823=0x3e +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = Reo2427 - mres1 + 0x8000; + local res0:4 = Ree2427 - mres0 + 0x8000; + overflowflagsww(res1,res0); + ssov(res1, res1, 32); + ssov(res0, res0, 32); + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBRS.H D[c], D[d], D[a], D[b] UL, n (RRR1) +:msubrs.h Rd2831,Rd2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2c +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000; + overflowflagsww(res1,res0); + ssov(res1, res1, 32); + ssov(res0, res0, 32); + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBRS.H D[c], D[d], D[a], D[b] LU, n (RRR1) +:msubrs.h Rd2831,Rd2427,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2d +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000; + overflowflagsww(res1,res0); + ssov(res1, res1, 32); + ssov(res0, res0, 32); + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBRS.H D[c], D[d], D[a], D[b] LL, n (RRR1) +:msubrs.h Rd2831,Rd2427,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2e +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000; + overflowflagsww(res1,res0); + ssov(res1, res1, 32); + ssov(res0, res0, 32); + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBRS.H D[c], D[d], D[a], D[b] UU, n (RRR1) +:msubrs.h Rd2831,Rd2427,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Rd2427 & Rd2831 & const1617Z & op1823=0x2f +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = sext(Rd2427[16,16] << 16) - mres1 + 0x8000; + local res0:4 = sext(Rd2427[0,16] << 16) - mres0 + 0x8000; + overflowflagsww(res1,res0); + ssov(res1, res1, 32); + ssov(res0, res0, 32); + Rd2831 = (zext(res1[16,16]) << 16) | zext(res0[16,16]); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBRS.Q D[c], D[d], D[a] U, D[b] U, n (RRR1) +:msubrs.q Rd2831,Rd2427,Rd0811^"u",Rd1215^"u",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x26 +{ + local mres:4; + multiply_u_u(mres, Rd0811, Rd1215, const1617Z); + local res:4 = Rd2427 - mres + 0x8000; + overflowflags(res); + ssov(res, res, 32); + Rd2831 = zext(res[16,16]) << 16; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBRS.Q D[c], D[d], D[a] L, D[b] L, n (RRR1) +:msubrs.q Rd2831,Rd2427,Rd0811^"l",Rd1215^"l",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x27 +{ + local mres:4; + multiply_l_l(mres, Rd0811, Rd1215, const1617Z); + local res:4 = Rd2427 - mres + 0x8000; + overflowflags(res); + ssov(res, res, 32); + Rd2831 = zext(res[16,16]) << 16; +} +@endif + +# MSUBS D[c], D[d], D[a], D[b] (RRR2) +:msubs Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x23 ; Rd2427 & Rd2831 & op1623=0x8a +{ + Rd2831 = Rd2427 - (Rd0811 - Rd1215); + overflowflags(Rd2831); + ssov(Rd2831, Rd2831, 32); +} + +# MSUBS D[c], D[d], D[a], const9 (RCR) +:msubs Rd2831,Rd2427,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x33 ; Rd2427 & Rd2831 & op2123=0x5 ) & const1220S +{ + local result:4 = Rd2427 - (Rd0811 - const1220S); + overflowflags(result); + ssov(Rd2831, result, 32); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBS E[c], E[d], D[a], const9 (RCR) +:msubs Re2831,Re2427,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x33 ; Re2427 & Re2831 & op2123=0x7 ) & const1220S +{ + local result:8 = Re2427 - sext(Rd0811 - const1220S); + overflowflagsd(result); + ssov(Re2831, result, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBS E[c], E[d], D[a], D[b] (RRR2) +:msubs Re2831,Re2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x23 ; Re2427 & Re2831 & op1623=0xea +{ + local result:8 = Re2427 - sext(Rd0811 - Rd1215); + overflowflags(result); + ssov(Re2831, result, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBS.H E[c], E[d], D[a], D[b] UL, n (RRR1) +:msubs.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x38 +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = Reo2427 - mres1; + local res0:4 = Ree2427 - mres0; + overflowflagsww(res1, res0); + ssov(Reo2831, res1, 32); + ssov(Ree2831, res0, 32); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBS.H E[c], E[d], D[a], D[b] LU, n (RRR1) +:msubs.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x39 +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = Reo2427 - mres1; + local res0:4 = Ree2427 - mres0; + overflowflagsww(res1, res0); + ssov(Reo2831, res1, 32); + ssov(Ree2831, res0, 32); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBS.H E[c], E[d], D[a], D[b] LL, n (RRR1) +:msubs.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x3a +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = Reo2427 - mres1; + local res0:4 = Ree2427 - mres0; + overflowflagsww(res1, res0); + ssov(Reo2831, res1, 32); + ssov(Ree2831, res0, 32); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBS.H E[c], E[d], D[a], D[b] UU, n (RRR1) +:msubs.h Ree2831/Reo2831,Ree2427/Reo2427,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa3 ; Ree2427 & Reo2427 & Ree2831 & Reo2831 & const1617Z & op1823=0x3b +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + local res1:4 = Reo2427 - mres1; + local res0:4 = Ree2427 - mres0; + overflowflagsww(res1, res0); + ssov(Reo2831, res1, 32); + ssov(Ree2831, res0, 32); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBS.Q D[c], D[d], D[a] U, D[b] U, n (RRR1) +:msubs.q Rd2831,Rd2427,Rd0811^"u",Rd1215^"u",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x24 +{ + local mres:4; + multiply_u_u(mres, Rd0811, Rd1215, const1617Z); + local res:4 = Rd2427 - mres; + overflowflags(res); + ssov(Rd2831, res, 32); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBS.Q D[c], D[d], D[a], D[b] U, n (RRR1) +:msubs.q Rd2831,Rd2427,Rd0811,Rd1215^"u",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x20 +{ + local result:4 = Rd2427 - (((Rd0811 * sext(Rd1215[16,16])) << const1617Z) s>> 16); + overflowflags(result); + ssov(Rd2831, result, 32); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBS.Q D[c], D[d], D[a], D[b] L, n (RRR1) +:msubs.q Rd2831,Rd2427,Rd0811,Rd1215^"l",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x21 +{ + local result:4 = Rd2427 - (((Rd0811 * sext(Rd1215[0,16])) << const1617Z) s>> 16); + overflowflags(result); + ssov(Rd2831, result, 32); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBS.Q D[c], D[d], D[a], D[b], n (RRR1) +:msubs.q Rd2831,Rd2427,Rd0811,Rd1215,const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x22 +{ + local result:4 = Rd2427 - (((Rd0811 * Rd1215) << const1617Z) s>> 32); + overflowflags(result); + ssov(Rd2831, result, 32); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBS.Q D[c], D[d], D[a] L, D[b] L, n (RRR1) +:msubs.q Rd2831,Rd2427,Rd0811^"l",Rd1215^"l",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Rd2427 & Rd2831 & const1617Z & op1823=0x25 +{ + local mres:4; + multiply_l_l(mres, Rd0811, Rd1215, const1617Z); + local res:4 = Rd2427 - mres; + overflowflags(res); + ssov(Rd2831, res, 32); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBS.Q E[c], E[d], D[a], D[b] U, n (RRR1) +:msubs.q Re2831,Re2427,Rd0811,Rd1215^"u",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Re2427 & Re2831 & const1617Z & op1823=0x38 +{ + local result:8 = Re2427 - sext((Rd0811 * sext(Rd1215[16,16])) << const1617Z); + overflowflagsd(result); + ssov(Re2831, result, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBS.Q E[c], E[d], D[a], D[b] L, n (RRR1) +:msubs.q Re2831,Re2427,Rd0811,Rd1215^"l",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Re2427 & Re2831 & const1617Z & op1823=0x39 +{ + local result:8 = Re2427 - sext((Rd0811 * sext(Rd1215[0,16])) << const1617Z); + overflowflagsd(result); + ssov(Re2831, result, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBS.Q E[c], E[d], D[a], D[b], n (RRR1) +:msubs.q Re2831,Re2427,Rd0811,Rd1215,const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Re2427 & Re2831 & const1617Z & op1823=0x3b +{ + local result:8 = Re2427 - sext((Rd0811 * Rd1215) << const1617Z); + overflowflagsd(result); + ssov(Re2831, result, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBS.Q E[c], E[d], D[a] U, D[b] U, n (RRR1) +:msubs.q Re2831,Re2427,Rd0811^"u",Rd1215^"u",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Re2427 & Re2831 & const1617Z & op1823=0x3c +{ + local mres:4; + multiply_u_u(mres, Rd0811, Rd1215, const1617Z); + local res:8 = Re2427 - sext(mres << 16); + overflowflagsd(res); + ssov(Re2831, res, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBS.Q E[c], E[d], D[a] L, D[b] L, n (RRR1) +:msubs.q Re2831,Re2427,Rd0811^"l",Rd1215^"l",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x63 ; Re2427 & Re2831 & const1617Z & op1823=0x3d +{ + local mres:4; + multiply_l_l(mres, Rd0811, Rd1215, const1617Z); + local res:8 = Re2427 - sext(mres << 16); + overflowflagsd(res); + ssov(Re2831, res, 64); +} +@endif + +# MSUBS.U D[c], D[d], D[a], const9 (RCR) +:msubs.u Rd2831,Rd2427,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x33 ; Rd2427 & Rd2831 & op2123=0x4 ) & const1220Z +{ + local result:4 = Rd2427 - (Rd0811 - const1220Z); + overflowflags(result); + suov(Rd2831, result, 32); +} + +# MSUBS.U D[c], D[d], D[a], D[b] (RRR2) +:msubs.u Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x23 ; Rd2427 & Rd2831 & op1623=0x88 +{ + local result:4 = Rd2427 - (Rd0811 - Rd1215); + overflowflags(result); + suov(Rd2831, result, 32); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBS.U E[c], E[d], D[a], const9 (RCR) +:msubs.u Re2831,Re2427,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x33 ; Re2427 & Re2831 & op2123=0x6 ) & const1220Z +{ + local result:8 = Re2427 - zext(Rd0811 - const1220Z); + overflowflagsd(result); + ssov(Re2831, result, 64); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MSUBS.U E[c], E[d], D[a], D[b] (RRR2) +:msubs.u Re2831,Re2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x23 ; Re2427 & Re2831 & op1623=0xe8 +{ + local result:8 = Re2427 - zext(Rd0811 - Rd1215); + overflowflagsd(result); + ssov(Re2831, result, 64); +} +@endif + +# MTCR const16, D[a] (RLC) +:mtcr const1227Z,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0xcd ; op2831=0x0 ) & const1227Z +{ + *[register]:4 const1227Z = Rd0811; +} + +@if defined(TRICORE_V2) +:mtfr Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; op1631=0x1c1 +{ + *[register]:4 Rd1215 = Rd0811; +} +@endif + +# MUL D[a], D[b] (SRR) +:mul Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xe2 +{ + Rd0811 = Rd0811 * Rd1215; + overflowflags(Rd0811); +} + +# MUL D[c], D[a], const9 (RC) +:mul Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x53 ; Rd2831 & op2127=0x1 ) & const1220S +{ + Rd2831 = Rd0811 * const1220S; + overflowflags(Rd2831); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MUL D[c], D[a], D[b] (RR2) +:mul Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x73 ; Rd2831 & op1627=0xa +{ + Rd2831 = Rd0811 * Rd1215; + overflowflags(Rd2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MUL E[c], D[a], const9 (RC) +:mul Re2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x53 ; Re2831 & op2127=0x3 ) & const1220S +{ + Re2831 = sext(Rd0811 * const1220S); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MUL E[c], D[a], D[b] (RR2) +:mul Re2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x73 ; Re2831 & op1627=0x6a +{ + Re2831 = sext(Rd0811 * Rd1215); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MUL.F D[c], D[a], D[b] (RR) +:mul.f Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Rd2831 & op1627=0x41 +{ + #TODO float + #TODO flags + Rd2831 = Rd0811 f* Rd1215; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MUL.H E[c], D[a], D[b] UL, n (RR1) +:mul.h Ree2831/Reo2831,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb3 ; Ree2831 & Reo2831 & const1617Z & op1827=0x18 +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + Reo2831 = mres1; + Ree2831 = mres0; + advoverflowflagsww(mres1, mres0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MUL.H E[c], D[a], D[b] LU, n (RR1) +:mul.h Ree2831/Reo2831,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb3 ; Ree2831 & Reo2831 & const1617Z & op1827=0x19 +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + Reo2831 = mres1; + Ree2831 = mres0; + advoverflowflagsww(mres1, mres0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MUL.H E[c], D[a], D[b] LL, n (RR1) +:mul.h Ree2831/Reo2831,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb3 ; Ree2831 & Reo2831 & const1617Z & op1827=0x1a +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + Reo2831 = mres1; + Ree2831 = mres0; + advoverflowflagsww(mres1, mres0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MUL.H E[c], D[a], D[b] UU, n (RR1) +:mul.h Ree2831/Reo2831,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb3 ; Ree2831 & Reo2831 & const1617Z & op1827=0x1b +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + Reo2831 = mres1; + Ree2831 = mres0; + advoverflowflagsww(mres1, mres0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MUL.Q D[c], D[a], D[b] U, n (RR1) +:mul.q Rd2831,Rd0811,Rd1215^"u",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x93 ; Rd2831 & const1617Z & op1827=0x0 +{ + Rd2831 = ((Rd0811 * sext(Rd1215[16,16])) << const1617Z) s>> 16; + overflowflags(Rd2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MUL.Q D[c], D[a], D[b] L, n (RR1) +:mul.q Rd2831,Rd0811,Rd1215^"l",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x93 ; Rd2831 & const1617Z & op1827=0x1 +{ + Rd2831 = ((Rd0811 * sext(Rd1215[0,16])) << const1617Z) s>> 16; + overflowflags(Rd2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MUL.Q D[c], D[a], D[b], n (RR1) +:mul.q Rd2831,Rd0811,Rd1215,const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x93 ; Rd2831 & const1617Z & op1827=0x2 +{ + Rd2831 = ((Rd0811 * Rd1215) << const1617Z) s>> 32; + overflowflags(Rd2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MUL.Q D[c], D[a] U, D[b] U, n (RR1) +:mul.q Rd2831,Rd0811^"u",Rd1215^"u",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x93 ; Rd2831 & const1617Z & op1827=0x4 +{ + local mres:4; + multiply_u_u(mres, Rd0811, Rd1215, const1617Z); + overflowflags(mres); + Rd2831 = mres; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MUL.Q D[c], D[a] L, D[b] L, n (RR1) +:mul.q Rd2831,Rd0811^"l",Rd1215^"l",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x93 ; Rd2831 & const1617Z & op1827=0x5 +{ + local mres:4; + multiply_l_l(mres, Rd0811, Rd1215, const1617Z); + overflowflags(mres); + Rd2831 = mres; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MUL.Q E[c], D[a], D[b] U, n (RR1) +:mul.q Re2831,Rd0811,Rd1215^"u",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x93 ; Re2831 & const1617Z & op1827=0x18 +{ + Re2831 = sext(Rd0811 * sext(Rd1215[16,16])) << const1617Z; + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MUL.Q E[c], D[a], D[b] L, n (RR1) +:mul.q Re2831,Rd0811,Rd1215^"l",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x93 ; Re2831 & const1617Z & op1827=0x19 +{ + Re2831 = sext(Rd0811 * sext(Rd1215[0,16])) << const1617Z; + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MUL.Q E[c], D[a], D[b], n (RR1) +:mul.q Re2831,Rd0811,Rd1215,const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x93 ; Re2831 & const1617Z & op1827=0x1b +{ + Re2831 = sext(Rd0811 * Rd1215) << const1617Z; + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MUL.U E[c], D[a], const9 (RC) +:mul.u Re2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x53 ; Re2831 & op2127=0x2 ) & const1220Z +{ + Re2831 = zext(Rd0811 * const1220Z); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MUL.U E[c], D[a], D[b] (RR2) +:mul.u Re2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x73 ; Re2831 & op1627=0x68 +{ + Re2831 = zext(Rd0811 * Rd1215); + overflowflagsd(Re2831); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MULM.H E[c], D[a], D[b] UL, n (RR1) +:mulm.h Re2831,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb3 ; Re2831 & const1617Z & op1827=0x1c +{ + local mres1:4; + local mres0:4; + packed_multiply_ul(mres1, mres0, Rd0811, Rd1215, const1617Z); + Re2831 = sext(mres1 + mres0) << 16; + $(PSW_V) = 0; + $(PSW_AV) = 0; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MULM.H E[c], D[a], D[b] LU, n (RR1) +:mulm.h Re2831,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb3 ; Re2831 & const1617Z & op1827=0x1d +{ + local mres1:4; + local mres0:4; + packed_multiply_lu(mres1, mres0, Rd0811, Rd1215, const1617Z); + Re2831 = sext(mres1 + mres0) << 16; + $(PSW_V) = 0; + $(PSW_AV) = 0; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MULM.H E[c], D[a], D[b] LL, n (RR1) +:mulm.h Re2831,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb3 ; Re2831 & const1617Z & op1827=0x1e +{ + local mres1:4; + local mres0:4; + packed_multiply_ll(mres1, mres0, Rd0811, Rd1215, const1617Z); + Re2831 = sext(mres1 + mres0) << 16; + $(PSW_V) = 0; + $(PSW_AV) = 0; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MULM.H E[c], D[a], D[b] UU, n (RR1) +:mulm.h Re2831,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb3 ; Re2831 & const1617Z & op1827=0x1f +{ + local mres1:4; + local mres0:4; + packed_multiply_uu(mres1, mres0, Rd0811, Rd1215, const1617Z); + Re2831 = sext(mres1 + mres0) << 16; + $(PSW_V) = 0; + $(PSW_AV) = 0; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MULR.H D[c], D[a], D[b] UL, n (RR1) +:mulr.h Rd2831,Rd0811,Rd1215^"ul",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb3 ; Rd2831 & const1617Z & op1827=0xc +{ + local sc1 = (Rd0811[16,16] == 0x8000) && (Rd1215[16,16] == 0x8000) && (const1617Z == 1); + local sc0 = (Rd0811[0,16] == 0x8000) && (Rd1215[0,16] == 0x8000) && (const1617Z == 1); + local mres1:4; + local mres0:4; + ternary(mres1, sc1, 0x7FFFFFFF, sext(((Rd0811[16,16] * Rd1215[16,16]) << const1617Z) + 0x8000)); + ternary(mres0, sc0, 0x7FFFFFFF, sext(((Rd0811[0,16] * Rd1215[0,16]) << const1617Z) + 0x8000)); + Rd2831 = (zext(mres1[16,16]) << 16) | zext(mres0[16,16]); + advoverflowflagsww(mres1, mres0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MULR.H D[c], D[a], D[b] LU, n (RR1) +:mulr.h Rd2831,Rd0811,Rd1215^"lu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb3 ; Rd2831 & const1617Z & op1827=0xd +{ + local sc1 = (Rd0811[16,16] == 0x8000) && (Rd1215[0,16] == 0x8000) && (const1617Z == 1); + local sc0 = (Rd0811[0,16] == 0x8000) && (Rd1215[16,16] == 0x8000) && (const1617Z == 1); + local mres1:4; + local mres0:4; + ternary(mres1, sc1, 0x7FFFFFFF, sext(((Rd0811[16,16] * Rd1215[0,16]) << const1617Z) + 0x8000)); + ternary(mres0, sc0, 0x7FFFFFFF, sext(((Rd0811[0,16] * Rd1215[16,16]) << const1617Z) + 0x8000)); + Rd2831 = (zext(mres1[16,16]) << 16) | zext(mres0[16,16]); + advoverflowflagsww(mres1, mres0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# # MULR.H D[c], D[a], D[b] LL, n (RR1) +:mulr.h Rd2831,Rd0811,Rd1215^"ll",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb3 ; Rd2831 & const1617Z & op1827=0xe +{ + local sc1 = (Rd0811[16,16] == 0x8000) && (Rd1215[0,16] == 0x8000) && (const1617Z == 1); + local sc0 = (Rd0811[0,16] == 0x8000) && (Rd1215[0,16] == 0x8000) && (const1617Z == 1); + local mres1:4; + local mres0:4; + ternary(mres1, sc1, 0x7FFFFFFF, sext(((Rd0811[16,16] * Rd1215[0,16]) << const1617Z) + 0x8000)); + ternary(mres0, sc0, 0x7FFFFFFF, sext(((Rd0811[0,16] * Rd1215[0,16]) << const1617Z) + 0x8000)); + Rd2831 = (zext(mres1[16,16]) << 16) | zext(mres0[16,16]); + advoverflowflagsww(mres1, mres0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MULR.H D[c], D[a], D[b] UU, n (RR1) +:mulr.h Rd2831,Rd0811,Rd1215^"uu",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb3 ; Rd2831 & const1617Z & op1827=0xf +{ + local sc1 = (Rd0811[0,16] == 0x8000) && (Rd1215[16,16] == 0x8000) && (const1617Z == 1); + local sc0 = (Rd0811[16,16] == 0x8000) && (Rd1215[16,16] == 0x8000) && (const1617Z == 1); + local mres1:4; + local mres0:4; + ternary(mres1, sc1, 0x7FFFFFFF, sext(((Rd0811[0,16] * Rd1215[16,16]) << const1617Z) + 0x8000)); + ternary(mres0, sc0, 0x7FFFFFFF, sext(((Rd0811[16,16] * Rd1215[16,16]) << const1617Z) + 0x8000)); + Rd2831 = (zext(mres1[16,16]) << 16) | zext(mres0[16,16]); + advoverflowflagsww(mres1, mres0); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MULR.Q D[c], D[a] U, D[b] U, n (RR1) +:mulr.q Rd2831,Rd0811^"u",Rd1215^"u",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x93 ; Rd2831 & const1617Z & op1827=0x6 +{ + local sc = (Rd0811[16,16] == 0x8000) && (Rd1215[16,16] == 0x8000) && (const1617Z == 1); + local res:4; + ternary(res, sc, 0x7FFFFFFF, ((sext(Rd0811[16,16] * Rd1215[16,16]) << const1617Z) + 0x8000)); + Rd2831 = zext(res[16,16] << 16); + advoverflowflags(res); +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MULR.Q D[c], D[a] L, D[b] L, n (RR1) +:mulr.q Rd2831,Rd0811^"l",Rd1215^"l",const1617Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x93 ; Rd2831 & const1617Z & op1827=0x7 +{ + local sc = (Rd0811[0,16] == 0x8000) && (Rd1215[0,16] == 0x8000) && (const1617Z == 1); + local res:4; + ternary(res, sc, 0x7FFFFFFF, ((sext(Rd0811[0,16] * Rd1215[0,16]) << const1617Z) + 0x8000)); + Rd2831 = zext(res[16,16] << 16); + advoverflowflags(res); +} +@endif + +# MULS D[c], D[a], const9 (RC) +:muls Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x53 ; Rd2831 & op2127=0x5 ) & const1220S +{ + local result:4 = Rd0811 * const1220S; + overflowflags(result); + ssov(Rd2831, result, 32); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MULS D[c], D[a], D[b] (RR2) +:muls Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x73 ; Rd2831 & op1627=0x8a +{ + local result:4 = Rd0811 * Rd1215; + overflowflags(result); + ssov(Rd2831, result, 32); +} +@endif + +# MULS.U D[c], D[a], const9 (RC) +:muls.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x53 ; Rd2831 & op2127=0x4 ) & const1220Z +{ + local result:4 = Rd0811 * const1220Z; + overflowflags(result); + suov(Rd2831, result, 32); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# MULS.U D[c], D[a], D[b] (RR2) +:muls.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x73 ; Rd2831 & op1627=0x88 +{ + local result:4 = Rd0811 * Rd1215; + overflowflags(result); + suov(Rd2831, result, 32); +} +@endif + +# NAND D[c], D[a], D[b] (RR) +:nand Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0x90 +{ + Rd2831 = ~(Rd0811 & Rd1215); +} + +# NAND D[c], D[a], const9 (RC) +:nand Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0x9 ) & const1220Z +{ + Rd2831 = ~(Rd0811 & const1220Z); +} + +# NAND.T D[c], D[a], pos1, D[b], pos2 (BIT) +:nand.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x7 ; Rd2831 & const1620Z & const2327Z & op2122=0x0 +{ + local tmp1:4 = (Rd0811 >> const1620Z) & 1; + local tmp2:4 = (Rd1215 >> const2327Z) & 1; + Rd2831 = zext(!(tmp1[0,1] & tmp2[0,1])); +} + +# NE D[c], D[a], D[b] (RR) +:ne Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x110 +{ + Rd2831 = zext(Rd0811 != Rd1215); +} + +# NE D[c], D[a], const9 (RC) +:ne Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x11 ) & const1220S +{ + Rd2831 = zext(Rd0811 != const1220S); +} + +# NE.A D[c], A[a], A[b] (RR) +:ne.a Rd2831,Ra0811,Ra1215 is PCPMode=0 & Ra0811 & Ra1215 & op0007=0x1 ; Rd2831 & op1627=0x410 +{ + Rd2831 = zext(Ra0811 != Ra1215); +} + +# NEZ.A D[c], A[a] (RR) +:nez.a Rd2831,Ra0811 is PCPMode=0 & Ra0811 & op0007=0x1 & op1215=0x0 ; Rd2831 & op1627=0x490 +{ + Rd2831 = zext(Ra0811 != 0); +} + +# NOP (SR) +:nop is PCPMode=0 & op0007=0x0 & op0815=0x0 +{ + local NOP:1 = 0:1; + NOP = NOP; +} + +# NOP (SYS) +:nop is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x0 +{ + local NOP:1 = 0:1; + NOP = NOP; +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# NOT D[a] (SR) +:not Rd0811 is PCPMode=0 & Rd0811 & op0007=0x46 & op1215=0x0 +{ + Rd0811 = ~Rd0811; +} +@endif + +# NOR D[c], D[a], D[b] (RR) +:nor Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0xb0 +{ + Rd2831 = ~(Rd0811 | Rd1215); +} + +# NOR D[c], D[a], const9 (RC) +:nor Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0xb ) & const1220Z +{ + Rd2831 = ~(Rd0811 | const1220Z); +} + +# NOR.T D[c], D[a], pos1, D[b], pos2 (BIT) +:nor.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x87 ; Rd2831 & const1620Z & const2327Z & op2122=0x2 +{ + local tmp = Rd0811 >> const1620Z; + local tmp2 = Rd1215 >> const2327Z; + Rd2831 = ~(tmp | tmp2) & 1; +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# OR D[a], D[b] (SRR) +:or Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa6 +{ + Rd0811 = Rd0811 | Rd1215; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# OR D[15], const8 (SC) +:or d15,const0815Z is PCPMode=0 & const0815Z & d15 & op0007=0x96 +{ + d15 = d15 | const0815Z; +} +@endif + +# OR D[c], D[a], D[b] (RR) +:or Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0xa0 +{ + Rd2831 = Rd0811 | Rd1215; +} + +# OR D[c], D[a], const9 (RC) +:or Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0xa ) & const1220Z +{ + Rd2831 = Rd0811 | const1220Z; +} + +# OR.AND.T D[c], D[a], pos1, D[b], pos2 (BIT) +:or.and.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc7 ; Rd2831 & const1620Z & const2327Z & op2122=0x0 +{ + local tmp = (Rd0811 >> const1620Z) & 1; + local tmp2 = (Rd1215 >> const2327Z) & 1; + local tmp3 = zext(Rd2831[0,1]); + tmp3 = tmp3 | (tmp & tmp2); + Rd2831[0,1] = tmp3[0,1]; +} + +# OR.ANDN.T D[c], D[a], pos1, D[b], pos2 (BIT) +:or.andn.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc7 ; Rd2831 & const1620Z & const2327Z & op2122=0x3 +{ + local tmp = ((Rd0811 >> const1620Z) & 1) == 1; + local tmp2 = ((Rd1215 >> const2327Z) & 1) == 0; + local tmp3 = (Rd2831 & 1) == 1; + tmp3 = tmp3 | (tmp & tmp2); + Rd2831[0,1] = tmp3; +} + +# OR.EQ D[c], D[a], D[b] (RR) +:or.eq Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x270 +{ + Rd2831[0,1] = Rd2831[0,1] | (Rd0811 == Rd1215); +} + +# OR.EQ D[c], D[a], const9 (RC) +:or.eq Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x27 ) & const1220S +{ + Rd2831[0,1] = Rd2831[0,1] | (Rd0811 == const1220S); +} + +# OR.GE D[c], D[a], D[b] (RR) +:or.ge Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x2b0 +{ + Rd2831[0,1] = Rd2831[0,1] | (Rd0811 s>= Rd0811); +} + +# OR.GE D[c], D[a], const9 (RC) +:or.ge Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x2b ) & const1220S +{ + Rd2831[0,1] = Rd2831[0,1] | (Rd0811 s>= const1220S); +} + +# OR.GE.U D[c], D[a], D[b] (RR) +:or.ge.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x2c0 +{ + Rd2831[0,1] = Rd2831[0,1] | (Rd0811 >= Rd1215); +} + +# OR.GE.U D[c], D[a], const9 (RC) +:or.ge.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x2c ) & const1220Z +{ + Rd2831[0,1] = Rd2831[0,1] | (Rd0811 >= const1220Z); +} + +# OR.LT D[c], D[a], D[b] (RR) +:or.lt Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x290 +{ + Rd2831[0,1] = Rd2831[0,1] | (Rd0811 s< Rd0811); +} + +# OR.LT D[c], D[a], const9 (RC) +:or.lt Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x29 ) & const1220S +{ + Rd2831[0,1] = Rd2831[0,1] | (Rd0811 s< const1220S); +} + +# OR.LT.U D[c], D[a], D[b] (RR) +:or.lt.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x2a0 +{ + Rd2831[0,1] = Rd2831[0,1] | (Rd0811 < Rd0811); +} + +# OR.LT.U D[c], D[a], const9 (RC) +:or.lt.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x2a ) & const1220Z +{ + Rd2831[0,1] = Rd2831[0,1] | (Rd0811 < const1220Z); +} + +# OR.NE D[c], D[a], D[b] (RR) +:or.ne Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x280 +{ + Rd2831[0,1] = Rd2831[0,1] | (Rd0811 != Rd0811); +} + +# OR.NE D[c], D[a], const9 (RC) +:or.ne Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x28 ) & const1220S +{ + Rd2831[0,1] = Rd2831[0,1] | (Rd0811 != const1220S); +} + +# OR.NOR.T D[c], D[a], pos1, D[b], pos2 (BIT) +:or.nor.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc7 ; Rd2831 & const1620Z & const2327Z & op2122=0x2 +{ + local tmp = (Rd0811 >> const1620Z) & 1; + local tmp2 = (Rd1215 >> const2327Z) & 1; + local tmp3 = zext(Rd2831[0,1]); + tmp3 = tmp3 | ~(tmp | tmp2); + Rd2831[0,1] = tmp3[0,1]; +} + +# OR.OR.T D[c], D[a], pos1, D[b], pos2 (BIT) +:or.or.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc7 ; Rd2831 & const1620Z & const2327Z & op2122=0x1 +{ + local tmp = (Rd0811 >> const1620Z) & 1; + local tmp2 = (Rd1215 >> const2327Z) & 1; + local tmp3 = zext(Rd2831[0,1]); + tmp3 = tmp3 | (tmp | tmp2); + Rd2831[0,1] = tmp3[0,1]; +} + +# OR.T D[c], D[a], pos1, D[b], pos2 (BIT) +:or.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x87 ; Rd2831 & const1620Z & const2327Z & op2122=0x1 +{ + local tmp = (Rd0811 >> const1620Z) & 1; + local tmp2 = (Rd1215 >> const2327Z) & 1; + Rd2831 = tmp | tmp2; +} + +# ORN D[c], D[a], D[b] (RR) +:orn Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0xf0 +{ + Rd2831 = Rd0811 | ~Rd1215; +} + +# ORN D[c], D[a], const9 (RC) +:orn Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0xf ) & const1220Z +{ + Rd2831 = Rd0811 | ~const1220Z; +} + +# ORN.T D[c], D[a], pos1, D[b], pos2 (BIT) +:orn.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x7 ; Rd2831 & const1620Z & const2327Z & op2122=0x1 +{ + local tmp = ((Rd0811 >> const1620Z) & 1) == 1; + local tmp2 = ((Rd1215 >> const2327Z) & 1) == 0; + Rd2831 = zext(tmp | tmp2); +} + +# PACK D[c], E[d], D[a] (RRR) +:pack Rd2831,Ree2427/Reo2427,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x6b & op1215=0x0 ; Rd2831 & Ree2427 & Reo2427 & op1623=0x0 +{ + #TODO o=exp e=mantissa D[a][31]=sign + # int_exp = E[d][63:32]; + # int_mant = E[d][31:0]; + # flag_rnd = int_mant[7] AND (int_mant[8] OR int_mant[6:0] OR PSW.C); + # if ((int_mant[31] == 0) AND (int_exp == +255)) then { + # // Infinity or NaN + # fp_exp = +255; + # fp_frac = int_mant[30:8]; + # } else if ((int_mant[31] == 1) AND (int_exp >= +127)) then { + # // Overflow ? Infinity. + # fp_exp = +255; + # fp_frac = 0; + # } else if ((int_mant[31] == 1) AND (int_exp <= -128)) then { + # // Underflow ? Zero + # fp_exp = 0; + # fp_frac = 0; + # } else if (int_mant == 0) then { + # // Zero + # fp_exp = 0; + # fp_frac = 0; + # } else { + # if (int_mant[31] == 0) then { + # // Denormal + # temp_exp = 0; + # } else { + # // Normal + # temp_exp = int_exp + 128; + # } + # fp_exp_frac[30:0] = {tmp_exp[7:0], int_mant[30:8]} + flag_rnd; + # fp_exp = fp_exp_frac[30:23]; + # fp_frac = fp_exp_frac[22:0]; + # } + # D[c][31] = D[a][31]; + # D[c][30:23] = fp_exp; + # D[c][22:0] = fp_frac; +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# PARITY D[c], D[a] (RR) +:parity Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; Rd2831 & op1627=0x20 +{ + local result3:1 = Rd0811[24,1] ^ Rd0811[25,1] ^ Rd0811[26,1] ^ Rd0811[27,1] ^ Rd0811[28,1] ^ Rd0811[29,1] ^Rd0811[30,1] ^ Rd0811[31,1]; + local result2:1 = Rd0811[16,1] ^ Rd0811[17,1] ^ Rd0811[18,1] ^ Rd0811[19,1] ^ Rd0811[20,1] ^ Rd0811[21,1] ^Rd0811[22,1] ^ Rd0811[23,1]; + local result1:1 = Rd0811[8,1] ^ Rd0811[9,1] ^ Rd0811[10,1] ^ Rd0811[11,1] ^ Rd0811[12,1] ^ Rd0811[13,1] ^Rd0811[14,1] ^ Rd0811[15,1]; + local result0:1 = Rd0811[0,1] ^ Rd0811[1,1] ^ Rd0811[2,1] ^ Rd0811[3,1] ^ Rd0811[4,1] ^ Rd0811[5,1] ^ Rd0811[6,1] ^ Rd0811[7,1]; + Rd2831 = zext(result3 << 24) | zext(result2 << 16) | zext(result1 << 8) | zext(result0); +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# Q31TOF D[c], D[a], D[b] (RR) +:q31tof Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Rd2831 & op1627=0x151 +{ + #TODO float + #TODO flags +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# QSEED.F D[c], D[a] (RR) +:qseed.f Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; Rd2831 & op1627=0x191 +{ + #TODO float + #TODO flags + Rd2831 = 1 f/ sqrt(Rd0811); +} +@endif + +@if defined(TRICORE_V2) +# RESTORE D[a] (SYS) +:restore Rd0811 is PCPMode=0 & Rd0811 & op0007=0xd & op1215=0x0 ; op1631=0x380 +{ + $(ICR_IE) = Rd0811[0,1]; +} +@endif + +# RET (SR) +:ret is PCPMode=0 & op0007=0x0 & op0815=0x90 +{ + #TODO ret + # if (PSW.CDE) then if (cdc_decrement()) then trap(CDU); + # if (PCXI[19:0] == 0) then trap(CSU); + # if (PCXI.UL == 0) then trap(CTYP); + # PC = {A[11] [31:1], 1’b0}; + # EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0}; + # {new_PCXI, new_PSW, a10,a11,d8,d9,d10,d11,a12,a13,a14,a15,d12,d13,d14,d15} = M(EA, 16 * word); + # M(EA, word) = FCX; + # FCX[19:0] = PCXI[19:0]; + # PCXI = new_PCXI; + # PSW = {new_PSW[31:26], PSW[25:24], new_PSW[23:0]}; + + local tmp:4 = a11 & 0xFFFFFFFE; + restoreCallerState(FCX, LCX, PCXI); + return [tmp]; +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# RET (SYS) +:ret is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x180 +{ + #TODO ret + # if (PSW.CDE) then if (cdc_decrement()) then trap(CDU); + # if (PCXI[19:0] == 0) then trap(CSU); + # if (PCXI.UL == 0) then trap(CTYP); + # PC = {A[11] [31:1], 1’b0}; + # EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0}; + # {new_PCXI, new_PSW,a10,a11,d8,d9,d10,d11,a12,a13,a14,a15,d12,d13,d14,d15} = M(EA, 16 * word); + # M(EA, word) = FCX; + # FCX[19:0] = PCXI[19:0]; + # PCXI = new_PCXI; + # PSW = {new_PSW[31:26], PSW[25:24], new_PSW[23:0]}; + + local tmp:4 = a11 & 0xFFFFFFFE; + restoreCallerState(FCX, LCX, PCXI); + return [tmp]; +} +@endif + +# RFE (SR) +:rfe is PCPMode=0 & op0007=0x0 & op0815=0x80 +{ + #TODO ret + # if (PCXI[19:0] == 0) then trap(CSU); + # if (PCXI.UL == 0) then trap(CTYP); + # if (!cdc_zero() AND PSW.CDE) then trap(NEST); + # PC = {A[11] [31:1], 1’b0}; + # ICR.IE = PCXI.PIE; + # ICR.CCPN = PCXI.PCPN; + # EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0}; + # {new_PCXI,PSW,a10,a11,d8,d9,d10,d11,a12,a13,a14,a15,d12,d13,d14,d15}=M(EA,16*word); + # M(EA, word) = FCX; + # FCX[19:0] = PCXI[19:0]; + # PCXI = new_PCXI; + + local tmp:4 = a11 & 0xFFFFFFFE; + restoreCallerState(FCX, LCX, PCXI); + return [tmp]; +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# RFE (SYS) +:rfe is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x1c0 +{ + #TODO ret + # if (PCXI[19:0] == 0) then trap(CSU); + # if (PCXI.UL == 0) then trap(CTYP); + # if (!cdc_zero() AND PSW.CDE) then trap(NEST); + # PC = {A[11] [31:1], 1’b0}; + # ICR.IE = PCXI.PIE; + # ICR.CCPN = PCXI.PCPN; + # EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0}; + # {new_PCXI,PSW,a10,a11,d8,d9,d10,d11,a12,a13,a14,a15,d12,d13,d14,d15}=M(EA,16*word); + # M(EA, word) = FCX; + # FCX[19:0] = PCXI[19:0]; + # PCXI = new_PCXI; + + local tmp:4 = a11 & 0xFFFFFFFE; + restoreCallerState(FCX, LCX, PCXI); + return [tmp]; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# RFM (SYS) +:rfm is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x140 +{ + #TODO ret + # if (PSW.IO != 2’b10) then trap (PRIV); + # if (DBGSR.DE) then{ + # PC = {A[11] [31:1], 1’b0}; + # ICR.IE = PCXI.IE; + # ICR.CCPN = PCXI.PCPN; + # EA = DCX; + # {PCXI, PSW, A[10], A[11]} = M(EA, 4 * word); + # DBGTCR.DTA = 0; + # }else{ + # NOP + # } + + local tmp:4 = a11 & 0xFFFFFFFE; + restoreCallerState(FCX, LCX, PCXI); + return [tmp]; +} +@endif + +# RSLCX (SYS) +:rslcx is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x240 +{ + #TODO context + # if(PCXI[19:0] == 0) then trap(CSU); + # if(PCXI.UL == 1) then trap(CTYP); + # EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0}; + # {new_PCXI, A[11], A[2], A[3], D[0], D[1], D[2], D[3], A[4], A[5], A[6], A[7], D[4], D[5], D[6], D[7]} = M(EA, 16*word); + # M(EA, word) = FCX; + # FCX[19:0] = PCXI[19:0]; + # PCXI = new_PCXI; +} + +# RSTV (SYS) +:rstv is PCPMode=0 & op0007=0x2f & op0815=0x0 ; op1631=0x0 +{ + $(PSW_V) = 0; + $(PSW_SV) = 0; + $(PSW_AV) = 0; + $(PSW_SAV) = 0; +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# RSUB D[a] (SR) +:rsub Rd0811 is PCPMode=0 & Rd0811 & op0007=0x32 & op1215=0x5 +{ + Rd0811 = 0 - Rd0811; + overflowflags(Rd0811); +} +@endif + +# RSUB D[c], D[a], const9 (RC) +:rsub Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x8 ) & const1220S +{ + Rd2831 = const1220S - Rd0811; + overflowflags(Rd2831); +} + +# RSUBS D[c], D[a], const9 (RC) +:rsubs Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0xa ) & const1220S +{ + local result:4 = const1220S - Rd0811; + overflowflags(result); + ssov(Rd2831, result, 32); +} + +# RSUBS.U D[c], D[a], const9 (RC) +:rsubs.u Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0xb ) & const1220S +{ + local result:4 = const1220S - Rd0811; + overflowflags(result); + suov(Rd2831, result, 32); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# SAT.B D[a] (SR) +:sat.b Rd0811 is PCPMode=0 & Rd0811 & op0007=0x32 & op1215=0x0 +{ + local sat_neg:4; + ternary(sat_neg, Rd0811 s< -0x80, -0x80, Rd0811); + ternary(Rd0811, sat_neg s> 0x7f, 0x7f, sat_neg); +} +@endif + +# SAT.B D[c], D[a] (RR) +:sat.b Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0xb & op1215=0x0 ; Rd2831 & op1627=0x5e0 +{ + local sat_neg:4; + ternary(sat_neg, Rd0811 s< -0x80, -0x80, Rd0811); + ternary(Rd2831, sat_neg s> 0x7f, 0x7f, sat_neg); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# SAT.BU D[a] (SR) +:sat.bu Rd0811 is PCPMode=0 & Rd0811 & op0007=0x32 & op1215=0x1 +{ + ternary(Rd0811, Rd0811 > 0xff, 0xff, Rd0811); +} +@endif + +# SAT.BU D[c], D[a] (RR) +:sat.bu Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0xb & op1215=0x0 ; Rd2831 & op1627=0x5f0 +{ + ternary(Rd2831, Rd0811 > 0xff, 0xff, Rd0811); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# SAT.H D[a] (SR) +:sat.h Rd0811 is PCPMode=0 & Rd0811 & op0007=0x32 & op1215=0x2 +{ + local sat_neg:4; + ternary(sat_neg, Rd0811 s< -0x8000, -0x8000, Rd0811); + ternary(Rd0811, sat_neg s> 0x7fff, 0x7fff, sat_neg); +} +@endif + +# SAT.H D[c], D[a] (RR) +:sat.h Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0xb & op1215=0x0 ; Rd2831 & op1627=0x7e0 +{ + local sat_neg:4; + ternary(sat_neg, Rd0811 s< -0x8000, -0x8000, Rd0811); + ternary(Rd2831, sat_neg s> 0x7fff, 0x7fff, sat_neg); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# SAT.HU D[a] (SR) +:sat.hu Rd0811 is PCPMode=0 & Rd0811 & op0007=0x32 & op1215=0x3 +{ + ternary(Rd0811, Rd0811 > 0xffff, 0xffff, Rd0811); +} +@endif + +# SAT.HU D[c], D[a] (RR) +:sat.hu Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0xb & op1215=0x0 ; Rd2831 & op1627=0x7f0 +{ + ternary(Rd2831, Rd0811 > 0xffff, 0xffff, Rd0811); +} + +# SEL D[c], D[d], D[a], D[b] (RRR) +:sel Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x2b ; Rd2427 & Rd2831 & op1623=0x40 +{ + ternary(Rd2831, Rd2427 != 0, Rd0811, Rd1215); +} + +# SEL D[c], D[d], D[a], const9 (RCR) +:sel Rd2831,Rd2427,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0xab ; Rd2427 & Rd2831 & op2123=0x4 ) & const1220S +{ + ternary(Rd2831, Rd2427 != 0, Rd0811, const1220S); +} + +# SELN D[c], D[d], D[a], D[b] (RRR) +:seln Rd2831,Rd2427,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x2b ; Rd2427 & Rd2831 & op1623=0x50 +{ + ternary(Rd2831, Rd2427 == 0, Rd0811, Rd1215); +} + +# SELN D[c], D[d], D[a], const9 (RCR) +:seln Rd2831,Rd2427,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0xab ; Rd2427 & Rd2831 & op2123=0x5 ) & const1220S +{ + ternary(Rd2831, Rd2427 == 0, Rd0811, const1220S); +} + + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# SH D[a], const4 (SRC) +:sh Rd0811,const1215S is PCPMode=0 & Rd0811 & const1215S & op0007=0x6 & op1515=1 +{ + local tmp = -const1215S; + Rd0811 = Rd0811 >> tmp; +} + +# SH D[a], const4 (SRC) +:sh Rd0811,const1215S is PCPMode=0 & Rd0811 & const1215S & op0007=0x6 & op1515=0 +{ + Rd0811 = Rd0811 << const1215S; +} +@endif + +# SH D[c], D[a], D[b] (RR) +:sh Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0x0 +{ + local shift_count:4 = sext(Rd1215[0,6]); + shift_count = (shift_count << (32 - 6)) s>> (32 - 6); + ternary(Rd2831, shift_count s>= 0, Rd0811 << shift_count, Rd0811 >> -shift_count); +} + +# SHD[c], D[a], const9 (RC) +:sh Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0x0 & op2020=1) & const1220S +{ + local tmp = -const1220S; + Rd2831 = Rd0811 >> tmp[0,6]; +} + +# SHD[c], D[a], const9 (RC) +:sh Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0x0 & op2020=0 ) & const1220S +{ + Rd2831 = Rd0811 << const1220S[0,6]; +} + +# SH.AND.T D[c], D[a], pos1, D[b], pos2 (BIT) +:sh.and.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x27 ; Rd2831 & const1620Z & const2327Z & op2122=0x0 +{ + local pos1 = (Rd0811 >> const1620Z) & 1; + local pos2 = (Rd1215 >> const2327Z) & 1; + local tmp = pos1 & pos2; + Rd2831 = (Rd2831 << 1) | zext(tmp[0,1]); +} + +# SH.ANDN.T D[c], D[a], pos1, D[b], pos2 (BIT) +:sh.andn.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x27 ; Rd2831 & const1620Z & const2327Z & op2122=0x3 +{ + local pos1 = (Rd0811 >> const1620Z) & 1; + local pos2 = (Rd1215 >> const2327Z) & 1; + local tmp = pos1 & ~pos2; + Rd2831 = (Rd2831 << 1) | zext(tmp[0,1]); +} + +# SH.EQ D[c], D[a], D[b] (RR) +:sh.eq Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x370 +{ + Rd2831 = (Rd2831 << 1) | zext(Rd0811 == Rd1215); +} + +# SH.EQ D[c], D[a], const9 (RC) +:sh.eq Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x37 ) & const1220S +{ + Rd2831 = (Rd2831 << 1) | zext(Rd0811 == const1220S); +} + +# SH.GE D[c], D[a], D[b] (RR) +:sh.ge Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x3b0 +{ + Rd2831 = (Rd2831 << 1) | zext(Rd0811 s>= Rd1215); +} + +# SH.GE D[c], D[a], const9 (RC) +:sh.ge Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x3b ) & const1220S +{ + Rd2831 = (Rd2831 << 1) | zext(Rd0811 s>= const1220S); +} + +# SH.GE.U D[c], D[a], D[b] (RR) +:sh.ge.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x3c0 +{ + Rd2831 = (Rd2831 << 1) | zext(Rd0811 >= Rd1215); +} + +# SH.GE.U D[c], D[a], const9 (RC) +:sh.ge.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x3c ) & const1220Z +{ + Rd2831 = (Rd2831 << 1) | zext(Rd0811 >= const1220Z); +} + +# SH.H D[c], D[a], D[b] (RR) +:sh.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0x400 +{ + local res1:2; + local res0:2; + local shift_count:4 = sext(Rd1215[0,5]); + shift_count = (shift_count << (16 - 5)) s>> (16 - 5); + ternary(res1, (shift_count s>= 0), Rd0811[16,16] << shift_count, Rd0811[16,16] >> -shift_count); + ternary(res0, (shift_count s>= 0), Rd0811[0,16] << shift_count, Rd0811[0,16] >> -shift_count); + Rd2831 = zext(res1 << 16) | zext(res0); +} + +# SH.H D[c], D[a], const9 (RC) +:sh.h Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0x40 ) & const1220S +{ + local res1:2; + local res0:2; + local shift_count = sext(const1220S[0,5]); + shift_count = (shift_count << (16 - 5)) s>> (16 - 5); + ternary(res1, (shift_count s>= 0), Rd0811[16,16] << shift_count, Rd0811[16,16] >> -shift_count); + ternary(res0, (shift_count s>= 0), Rd0811[0,16] << shift_count, Rd0811[0,16] >> -shift_count); + Rd2831 = zext(res1 << 16) | zext(res0); +} + +# SH.LT D[c], D[a], D[b] (RR) +:sh.lt Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x390 +{ + Rd2831 = (Rd2831 << 1) | zext(Rd0811 s< Rd1215); +} + +# SH.LT D[c], D[a], const9 (RC) +:sh.lt Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x39 ) & const1220S +{ + Rd2831 = (Rd2831 << 1) | zext(Rd0811 s< const1220S); +} + +# SH.LT.U D[c], D[a], D[b] (RR) +:sh.lt.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x3a0 +{ + Rd2831 = (Rd2831 << 1) | zext(Rd0811 < Rd1215); +} + +# SH.LT.U D[c], D[a], const9 (RC) +:sh.lt.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x3a ) & const1220Z +{ + Rd2831 = (Rd2831 << 1) | zext(Rd0811 < const1220Z); +} + +# SH.NAND.T D[c], D[a], pos1, D[b], pos2 (BIT) +:sh.nand.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa7 ; Rd2831 & const1620Z & const2327Z & op2122=0x0 +{ + local tmp1 = ((Rd0811 >> const1620Z) & 1) == 1; + local tmp0 = ((Rd1215 >> const2327Z) & 1) == 1; + local res = !(tmp1 && tmp0); + Rd2831 = (Rd2831 << 1) | zext(res); +} + +# SH.NE D[c], D[a], D[b] (RR) +:sh.ne Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x380 +{ + Rd2831 = (Rd2831 << 1) | zext(Rd0811 != Rd1215); +} + +# SH.NE D[c], D[a], const9 (RC) +:sh.ne Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x38 ) & const1220S +{ + Rd2831 = (Rd2831 << 1) | zext(Rd0811 != const1220S); +} + +# SH.NOR.T D[c], D[a], pos1, D[b], pos2 (BIT) +:sh.nor.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x27 ; Rd2831 & const1620Z & const2327Z & op2122=0x2 +{ + local tmp1 = ((Rd0811 >> const1620Z) & 1) == 1; + local tmp0 = ((Rd1215 >> const2327Z) & 1) == 1; + local res = !(tmp1 || tmp0); + Rd2831 = (Rd2831 << 1) | zext(res); +} + +# SH.OR.T D[c], D[a], pos1, D[b], pos2 (BIT) +:sh.or.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x27 ; Rd2831 & const1620Z & const2327Z & op2122=0x1 +{ + local tmp1 = ((Rd0811 >> const1620Z) & 1) == 1; + local tmp0 = ((Rd1215 >> const2327Z) & 1) == 1; + local res = tmp1 || tmp0; + Rd2831 = (Rd2831 << 1) | zext(res); +} + +# SH.ORN.T D[c], D[a], pos1, D[b], pos2 (BIT) +:sh.orn.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa7 ; Rd2831 & const1620Z & const2327Z & op2122=0x1 +{ + local tmp1 = ((Rd0811 >> const1620Z) & 1) == 1; + local tmp0 = ((Rd1215 >> const2327Z) & 1) == 1; + local res = tmp1 || !tmp0; + Rd2831 = (Rd2831 << 1) | zext(res); +} + +# SH.XNOR.T D[c], D[a], pos1, D[b], pos2 (BIT) +:sh.xnor.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa7 ; Rd2831 & const1620Z & const2327Z & op2122=0x2 +{ + local tmp1 = ((Rd0811 >> const1620Z) & 1) == 1; + local tmp0 = ((Rd1215 >> const2327Z) & 1) == 1; + local res = !(tmp1 ^ tmp0); + Rd2831 = (Rd2831 << 1) | zext(res); +} + +# SH.XOR.T D[c], D[a], pos1, D[b], pos2 (BIT) +:sh.xor.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa7 ; Rd2831 & const1620Z & const2327Z & op2122=0x3 +{ + local tmp1 = ((Rd0811 >> const1620Z) & 1) == 1; + local tmp0 = ((Rd1215 >> const2327Z) & 1) == 1; + local res = tmp1 ^ tmp0; + Rd2831 = (Rd2831 << 1) | zext(res); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# SHA D[a], const4 (SRC) +:sha Rd0811,const1215S is PCPMode=0 & Rd0811 & const1215S & op0007=0x86 +{ + local shift_count:4 = sext(const1215S[0,4]); + shift_count = (shift_count << (32 - 4)) s>> (32 - 4); + local res:4 = Rd0811; + local shift_dir:1 = shift_count s< 0; + res = (Rd0811 << shift_count) * zext(shift_dir == 0) | (Rd0811 s>> (-shift_count)) * zext(shift_dir == 1); + overflowflags(res); + Rd0811 = res; +} +@endif + +# SHA D[c], D[a], D[b] (RR) +:sha Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0x10 +{ + local shift_count:4 = sext(Rd1215[0,6]); + shift_count = (shift_count << (32 - 6)) s>> (32 - 6); + local res:4 = Rd0811; + local shift_dir:1 = shift_count s< 0; + res = (Rd0811 << shift_count) * zext(shift_dir == 0) | (Rd0811 s>> (-shift_count)) * zext(shift_dir == 1); + overflowflags(res); + Rd2831 = res; +} + +# SHA D[c], D[a], const9 (RC) +:sha Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0x1 ) & const1220S +{ + local shift_count:4 = sext(const1220S[0,6]); + shift_count = (shift_count << (32 - 6)) s>> (32 - 6); + local res:4 = Rd0811; + local shift_dir:1 = shift_count s< 0; + res = (Rd0811 << shift_count) * zext(shift_dir == 0) | (Rd0811 s>> (-shift_count)) * zext(shift_dir == 1); + overflowflags(res); + Rd2831 = res; +} + +# SHA.H D[c], D[a], D[b] (RR) +:sha.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0x410 +{ + local shift_count:4 = sext(Rd1215[0,5]); + local res1:4 = sext(Rd0811[16,16]); + local res0:4 = sext(Rd0811[0,16]); + if (shift_count s> 0) goto ; + if (shift_count == 0) goto ; + shift_count = 0 - shift_count; + local msk:4; + ternary(msk, Rd0811[31,1] != 0, (((1 << shift_count) - 1) << (16 - shift_count)), 0); + res1 = msk | sext(Rd0811[16,16] s>> shift_count); + res0 = msk | sext(Rd0811[0,16] s>> shift_count); + goto ; + + res1 = sext(Rd0811[16,16] << shift_count); + res0 = sext(Rd0811[0,16] << shift_count); + + Rd2831 = zext(res1[0,16] << 16) | zext(res0[0,16]); +} + +# SHA.H D[c], D[a], const9 (RC) +:sha.h Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0x41 ) & const1220S +{ + local shift_count:4 = sext(const1220S[0,5]); + local res1:4 = sext(Rd0811[16,16]); + local res0:4 = sext(Rd0811[0,16]); + if (shift_count s> 0) goto ; + if (shift_count == 0) goto ; + shift_count = 0 - shift_count; + local msk:4; + ternary(msk, Rd0811[31,1] != 0, (((1 << shift_count) - 1) << (16 - shift_count)), 0); + res1 = msk | sext(Rd0811[16,16] s>> shift_count); + res0 = msk | sext(Rd0811[0,16] s>> shift_count); + goto ; + + res1 = sext(Rd0811[16,16] << shift_count); + res0 = sext(Rd0811[0,16] << shift_count); + + Rd2831 = (zext(res1[0,16]) << 16) | zext(res0[0,16]); +} + +# SHAS D[c], D[a], D[b] (RR) +:shas Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0x20 +{ + local shift_count:4 = sext(Rd1215[0,6]); + shift_count = (shift_count << (32 - 6)) s>> (32 - 6); + local res:4 = Rd0811; + local shift_dir:1 = shift_count s< 0; + res = (Rd0811 << shift_count) * zext(shift_dir == 0) | (Rd0811 s>> (-shift_count)) * zext(shift_dir == 1); + overflowflags(res); + ssov(Rd2831, res, 32); +} + +# SHAS D[c], D[a], const9 (RC) +:shas Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0x2 ) & const1220S +{ + local shift_count:4 = sext(const1220S[0,6]); + shift_count = (shift_count << (32 - 6)) s>> (32 - 6); + local res:4 = Rd0811; + local shift_dir:1 = shift_count s< 0; + res = (Rd0811 << shift_count) * zext(shift_dir == 0) | (Rd0811 s>> (-shift_count)) * zext(shift_dir == 1); + overflowflags(res); + ssov(Rd2831, res, 32); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# ST.A A[10], const8, A[15] (SC) +:st.a SC,a15 is PCPMode=0 & a15 & op0007=0xf8 & SC +{ + build SC; + *[ram]:4 SC = a15; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# ST.A A[b], off4, A[15] (SRO) +:st.a SRO,a15 is PCPMode=0 & a15 & op0007=0xec & SRO +{ + build SRO; + *[ram]:4 SRO = a15; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# ST.A A[15], off4, A[a] (SSRO) +:st.a SSRO,Ra0811 is PCPMode=0 & Ra0811 & op0007=0xe8 & SSRO +{ + build SSRO; + *[ram]:4 SSRO = Ra0811; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# ST.A A[b], A[a] (SSR)(Post-increment Addressing Mode) +# ST.A A[b], A[a] (SSR) +:st.a SSR,Ra0811 is PCPMode=0 & Ra0811 & op0607=0x3 & SSR +{ + build SSR; + *[ram]:4 SSR = Ra0811; +} +@endif + +# ST.A A[b], off10, A[a] (BO)(Post-increment Addressing Mode) +# ST.A P[b], A[a] (BO)(Bit-reverse Addressing Mode) +# ST.A A[b], off10, A[a] (BO)(Pre-increment Addressing Mode) +# ST.A A[b], off10, A[a] (BO)(Base + Short Offset Addressing Mode) +# ST.A P[b], A[a] (BO)(Index Addressing Mode) +:st.a BO,Ra0811 is PCPMode=0 & ( Ra0811 & op0607=0x2 ; op2225=0x6 ) & BO +{ + build BO; + *[ram]:4 BO = Ra0811; +} + +# ST.A P[b], off10, A[a] (BO)(Circular Addressing Mode) +#:st.a BO,Ra0811 is PCPMode=0 & ( Ra0811 & op0007=0xa9 ; op2227=0x16 ) & BO +:st.a [Rpe1215/Rpo1215^"+c"^]off10,Ra0811 is PCPMode=0 & Ra0811 & Rpe1215 & Rpo1215 & op0007=0xa9 ; off10 & op2227=0x16 +{ + local EA:4; + CircularAddressingMode(Rpe1215, Rpo1215, EA, off10); + *[ram]:4 EA = Ra0811; +} + +# ST.A off18, A[a] (ABS)(Absolute Addressing Mode) +:st.a off18,Ra0811 is PCPMode=0 & ( Ra0811 & op0007=0xa5 ; op2627=0x2 ) & off18 +{ + *[ram]:4 off18 = Ra0811; +} + +# ST.A A[b], off16, A[a] (BOL)(Base + Long Offset Addressing Mode) +:st.a BOL,Ra0811 is PCPMode=0 & ( Ra0811 & op0007=0xb5 ) ... & BOL +{ + build BOL; + *[ram]:4 BOL = Ra0811; +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# ST.B A[b], D[a] (SSR) +# ST.B A[b], D[a] (SSR)(Post-increment Addressing Mode) +:st.b SSR,Rd0811 is PCPMode=0 & Rd0811 & op0607=0x0 & SSR +{ + build SSR; + *[ram]:1 SSR = Rd0811[0,8]; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# ST.B A[15], off4, D[a] (SSRO) +:st.b SSRO,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x28 & SSRO +{ + build SSRO; + *[ram]:1 SSRO = Rd0811[0,8]; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# ST.B A[b], off4, D[15] (SRO) +:st.b SRO,d15 is PCPMode=0 & d15 & op0007=0x2c & SRO +{ + build SRO; + *[ram]:1 SRO = d15[0,8]; +} +@endif + +# ST.B off18, D[a] (ABS)(Absolute Addressing Mode) +:st.b off18,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0x25 ; op2627=0x0 ) & off18 +{ + *[ram]:1 off18 = Rd0811[0,8]; +} + +# ST.B A[b], off16, D[a] (BOL)(Base + Long Offset Addressing Mode) +:st.b BOL,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0xe9 ) ... & BOL +{ + build BOL; + *[ram]:1 BOL = Rd0811[0,8]; +} + +# ST.B A[b], off10, D[a] (BO)(Post-increment Addressing Mode) +# ST.B P[b], D[a] (BO)(Bit-reverse Addressing Mode) +# ST.B A[b], off10, D[a] (BO)(Pre-increment Addressing Mode) +# ST.B A[b], off10, D[a] (BO)(Base + Short Offset Addressing Mode) +# ST.B P[b], D[a] (BO)(Index Addressing Mode) +:st.b BO,Rd0811 is PCPMode=0 & ( Rd0811 & op0607=0x2 ; op2225=0x0 ) & BO +{ + build BO; + *[ram]:1 BO = Rd0811[0,8]; +} + +# ST.B P[b], off10, D[a] (BO)(Circular Addressing Mode) +#:st.b BO,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0xa9 ; op2227=0x10 ) & BO +:st.b [Rpe1215/Rpo1215^"+c"^]off10,Rd0811 is PCPMode=0 & Rd0811 & Rpe1215 & Rpo1215 & op0007=0xa9 ; off10 & op2227=0x10 +{ + local EA:4; + CircularAddressingMode(Rpe1215, Rpo1215, EA, off10); + *[ram]:1 EA = Rd0811[0,8]; +} + +# ST.D A[b], off10, E[a] (BO)(Post-increment Addressing Mode) +# ST.D P[b], E[a] (BO)(Bit-reverse Addressing Mode) +# ST.D A[b], off10, E[a] (BO)(Pre-increment Addressing Mode) +# ST.D A[b], off10, E[a] (BO)(Base + Short Offset Addressing Mode) +# ST.D P[b], E[a] (BO)(Index Addressing Mode) +:st.d BO,Re0811 is PCPMode=0 & ( Re0811 & op0607=0x2 ; op2225=0x5 ) & BO +{ + build BO; + *[ram]:8 BO = Re0811; +} + +# ST.D off18, E[a] (ABS)(Absolute Addressing Mode) +:st.d off18,Re0811 is PCPMode=0 & ( Re0811 & op0007=0xa5 ; op2627=0x1 ) & off18 +{ + *[ram]:8 off18 = Re0811; +} + +# ST.D P[b], off10, E[a] (BO)(Circular Addressing Mode) +#:st.d BO,Re0811 is PCPMode=0 & ( Re0811 & op0007=0xa9 ; op2227=0x15 ) & BO +:st.d [Rpe1215/Rpo1215^"+c"^]off10,Re0811 is PCPMode=0 & Re0811 & Rpe1215 & Rpo1215 & op0007=0xa9 ; off10 & op2227=0x15 +{ + local EA0:4; + local EA2:4; + local EA4:4; + local EA6:4; + CircularAddressingMode4(Rpe1215, Rpo1215, EA0, EA2, EA4, EA6, off10, 2); + *[ram]:2 EA6 = Re0811[48,16]; + *[ram]:2 EA4 = Re0811[32,16]; + *[ram]:2 EA2 = Re0811[16,16]; + *[ram]:2 EA0 = Re0811[0,16]; +} + +# ST.DA A[b], off10, P[a] (BO)(Post-increment Addressing Mode) +# ST.DA P[b], P[a] (BO)(Bit-reverse Addressing Mode) +# ST.DA A[b], off10, P[a] (BO)(Pre-increment Addressing Mode) +# ST.DA A[b], off10, P[a] (BO)(Base + Short Offset Addressing Mode) +# ST.DA P[b], P[a] (BO)(Index Addressing Mode) +:st.da BO,Rp0811 is PCPMode=0 & ( Rp0811 & op0607=0x2 ; op2225=0x7 ) & BO +{ + build BO; + *[ram]:8 BO = Rp0811; +} + +# ST.DA P[b], off10, P[a] (BO)(Circular Addressing Mode) +#:st.da BO,Rp0811 is PCPMode=0 & ( Rp0811 & op0007=0xa9 ; op2227=0x17 ) & BO +:st.da [Rpe1215/Rpo1215^"+c"^]off10,Rp0811 is PCPMode=0 & Rp0811 & Rpe1215 & Rpo1215 & op0007=0xa9 ; off10 & op2227=0x17 +{ + local EA0:4; + local EA4:4; + CircularAddressingMode2(Rpe1215, Rpo1215, EA0, EA4, off10, 4); + *[ram]:2 EA0 = Rp0811[0,32]; + *[ram]:2 EA4 = Rp0811[32,32]; +} + +# ST.DA off18, P[a] (ABS)(Absolute Addressing Mode) +:st.da off18,Rp0811 is PCPMode=0 & ( Rp0811 & op0007=0xa5 ; op2627=0x3 ) & off18 +{ + *[ram]:8 off18 = Rp0811; +} + +@if defined(TRICORE_V2) +:st.dd BO,Re0811/ReN0811 is PCPMode=0 & ( Re0811 & ReN0811 & op0007=0x89 ; op2227=0x9 ) & BO +{ + build BO; + *[ram]:8 BO = Re0811; + *[ram]:8 BO+8 = ReN0811; +} +@endif + +@if defined(TRICORE_V2) +:st.dd BO,Re0811/ReN0811 is PCPMode=0 & ( Re0811 & ReN0811 & op0007=0xa9 ; op1621=0x0 & op2227=0x09 & op2831=0x0 ) & BO +{ + build BO; + *[ram]:8 BO = Re0811; + *[ram]:8 BO+8 = ReN0811; +} +@endif + +@if defined(TRICORE_V2) +:st.dd BO,Re0811/ReN0811 is PCPMode=0 & ( Re0811 & ReN0811 & op0007=0x89 ; op2227=0x19 ) & BO +{ + build BO; + *[ram]:8 BO = Re0811; + *[ram]:8 BO+8 = ReN0811; +} +@endif + +@if defined(TRICORE_V2) +#:st.dd BO,Re0811/ReN0811 is PCPMode=0 & ( Re0811 & ReN0811 & op0007=0xa9 ; op2227=0x19 ) & BO +:st.dd [Rpe1215/Rpo1215^"+c"^]off10,Re0811/ReN0811 is PCPMode=0 & Re0811 & ReN0811 & Rpe1215 & Rpo1215 & op0007=0xa9 ; off10 & op2227=0x19 +{ + local EA0:4; + local EA8:4; + CircularAddressingMode2(Rpe1215, Rpo1215, EA0, EA8, off10, 8); + *[ram]:8 EA0 = Re0811; + *[ram]:8 EA8 = ReN0811; +} +@endif + +@if defined(TRICORE_V2) +:st.dd BO,Re0811/ReN0811 is PCPMode=0 & ( Re0811 & ReN0811 & op0007=0x89 ; op2227=0x29 ) & BO +{ + build BO; + *[ram]:8 BO = Re0811; + *[ram]:8 BO+8 = ReN0811; +} +@endif + +@if defined(TRICORE_V2) +:st.dd BO,Re0811/ReN0811 is PCPMode=0 & ( Re0811 & ReN0811 & op0007=0xa9 ; op1621=0x0 & op2227=0x29 & op2831=0x0 ) & BO +{ + build BO; + *[ram]:8 BO = Re0811; + *[ram]:8 BO+8 = ReN0811; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# ST.H A[b], D[a] (SSR)(Post-increment Addressing Mode) +# ST.H A[b], D[a] (SSR) +:st.h SSR,Rd0811 is PCPMode=0 & Rd0811 & op0607=0x2 & SSR +{ + build SSR; + *[ram]:2 SSR = Rd0811[0,16]; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# ST.H A[15], off4, D[a] (SSRO) +:st.h SSRO,Rd0811 is PCPMode=0 & Rd0811 & op0007=0xa8 & SSRO +{ + build SSRO; + *[ram]:2 SSRO = Rd0811[0,16]; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# ST.H A[b], off4, D[15] (SRO) +:st.h SRO,d15 is PCPMode=0 & d15 & op0007=0xac & SRO +{ + build SRO; + *[ram]:2 SRO = d15[0,16]; +} +@endif + +# ST.H A[b], off10, D[a] (BO)(Post-increment Addressing Mode) +# ST.H P[b], D[a] (BO)(Bit-reverse Addressing Mode) +# ST.H A[b], off10, D[a] (BO)(Pre-increment Addressing Mode) +# ST.H A[b], off10, D[a] (BO)(Base + Short Offset Addressing Mode) +# ST.H P[b], D[a] (BO)(Index Addressing Mode) +:st.h BO,Rd0811 is PCPMode=0 & ( Rd0811 & op0607=0x2 ; op2225=0x2 ) & BO +{ + build BO; + *[ram]:2 BO = Rd0811[0,16]; +} + +# ST.H A[b], off16, D[a] (BOL)(Base + Long Offset Addressing Mode) +:st.h BOL,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0xf9 ) ... & BOL +{ + build BOL; + *[ram]:2 BOL = Rd0811[0,16]; +} + +# ST.H P[b], off10, D[a] (BO)(Circular Addressing Mode) +#:st.h BO,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0xa9 ; op2227=0x12 ) & BO +:st.h [Rpe1215/Rpo1215^"+c"^]off10,Rd0811 is PCPMode=0 & Rd0811 & Rpe1215 & Rpo1215 & op0007=0xa9 ; off10 & op2227=0x12 +{ + local EA:4; + CircularAddressingMode(Rpe1215, Rpo1215, EA, off10); + *[ram]:2 EA = Rd0811[0,16]; +} + +# ST.H off18, D[a] (ABS)(Absolute Addressing Mode) +:st.h off18,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0x25 ; op2627=0x2 ) & off18 +{ + *[ram]:2 off18 = Rd0811[0,16]; +} + +# ST.Q off18, D[a] (ABS)(Absolute Addressing Mode) +:st.q off18,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0x65 ; op2627=0x0 ) & off18 +{ + *[ram]:2 off18 = Rd0811[16,16]; +} + +# ST.Q A[b], off10, D[a] (BO)(Post-increment Addressing Mode) +# ST.Q P[b], D[a] (BO)(Bit-reverse Addressing Mode) +# ST.Q A[b], off10, D[a] (BO)(Pre-increment Addressing Mode) +# ST.Q A[b], off10, D[a] (BO)(Base + Short Offset Addressing Mode) +# ST.Q P[b], D[a] (BO)(Index Addressing Mode) +:st.q BO,Rd0811 is PCPMode=0 & ( Rd0811 & op0607=0x2 ; op2225=0x8 ) & BO +{ + build BO; + *[ram]:2 BO = Rd0811[16,16]; +} + +#:st.q BO,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0xa9 ; op2227=0x18 ) & BO +:st.q [Rpe1215/Rpo1215^"+c"^]off10,Rd0811 is PCPMode=0 & Rd0811 & Rpe1215 & Rpo1215 & op0007=0xa9 ; off10 & op2227=0x18 +{ + local EA:4; + CircularAddressingMode(Rpe1215, Rpo1215, EA, off10); + *[ram]:2 EA = Rd0811[16,16]; +} + +# ST.T off18, bpos3, b (ABSB) +:st.t off18,const0810Z,const1111Z is PCPMode=0 & ( const0810Z & const1111Z & op0007=0xd5 ; op2627=0x0 ) & off18 +{ + local tmp:1 = *[ram]:1 off18; + ternary(tmp, const1111Z, + tmp | (1 << const0810Z), + tmp & ~(1 << const0810Z)); + *[ram]:1 off18 = tmp; +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# ST.W A[10], const8, D[15] (SC) +:st.w SC,d15 is PCPMode=0 & d15 & op0007=0x78 & SC +{ + build SC; + *[ram]:4 SC = d15; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# ST.W A[b], D[a] (SSR) +# ST.W A[b], D[a] (SSR)(Post-increment Addressing Mode) +:st.w SSR,Rd0811 is PCPMode=0 & Rd0811 & op0607=0x1 & SSR +{ + build SSR; + *[ram]:4 SSR = Rd0811; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# ST.W A[15], off4, D[a] (SSRO) +:st.w SSRO,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x68 & SSRO +{ + build SSRO; + *[ram]:4 SSRO = Rd0811; +} +@endif + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# ST.W A[b], off4, D[15] (SRO) +:st.w SRO,d15 is PCPMode=0 & d15 & op0007=0x6c & SRO +{ + build SRO; + *[ram]:4 SRO = d15; +} +@endif + +# ST.W A[b], off16, D[a] (BOL)(Base + Long Offset Addressing Mode) +:st.w BOL,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0x59 ) ... & BOL +{ + build BOL; + *[ram]:4 BOL = Rd0811; +} + +# ST.W off18, D[a] (ABS)(Absolute Addressing Mode) +:st.w off18,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0xa5 ; op2627=0x0 ) & off18 +{ + *[ram]:4 off18 = Rd0811; +} + +# ST.W A[b], off10, D[a] (BO)(Post-increment Addressing Mode) +# ST.W P[b], D[a] (BO)(Bit-reverse Addressing Mode) +# ST.W A[b], off10, D[a] (BO)(Pre-increment Addressing Mode) +# ST.W A[b], off10, D[a] (BO)(Base + Short Offset Addressing Mode) +# ST.W P[b], D[a] (BO)(Index Addressing Mode) +:st.w BO,Rd0811 is PCPMode=0 & ( Rd0811 & op0607=0x2 ; op2225=0x4 ) & BO +{ + build BO; + *[ram]:4 BO = Rd0811; +} + +# ST.W P[b], off10, D[a] (BO)(Circular Addressing Mode) +#:st.w BO,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0xa9 ; op2227=0x14 ) & BO +:st.w [Rpe1215/Rpo1215^"+c"^]off10,Rd0811 is PCPMode=0 & Rd0811 & Rpe1215 & Rpo1215 & op0007=0xa9 ; off10 & op2227=0x14 +{ + local EA0:4; + local EA2:4; + CircularAddressingMode2(Rpe1215, Rpo1215, EA0, EA2, off10, 2); + *[ram]:2 EA2 = Rd0811[16,16]; + *[ram]:2 EA0 = Rd0811[0,16]; +} + +# STLCX off18 (ABS)(Absolute Addressing Mode) +:stlcx off18 is PCPMode=0 & ( op0007=0x15 & op0811=0x0 ; op2627=0x0 ) & off18 +{ + #TODO context + store_lower_context(off18); +} + +# STLCX A[b], off10 (BO)(Base + Short Index Addressing Mode) +:stlcx BO is PCPMode=0 & ( op0007=0x49 & op0811=0x0 ; op2227=0x26 ) & BO +{ + #TODO context + build BO; + store_lower_context(BO); +} + +# STUCX off18 (ABS)(Absolute Addressing Mode) +:stucx off18 is PCPMode=0 & ( op0007=0x15 & op0811=0x0 ; op2627=0x1 ) & off18 +{ + #TODO context + store_upper_context(off18); +} + +# STUCX A[b], off10 (BO)(Base + Short Index Addressing Mode) +:stucx BO is PCPMode=0 & ( op0007=0x49 & op0811=0x0 ; op2227=0x27 ) & BO +{ + #TODO context + build BO; + store_upper_context(BO); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# SUB D[a], D[15], D[b] (SRR) +:sub Rd0811,d15,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & d15 & op0007=0x52 +{ + Rd0811 = d15 - Rd1215; + overflowflags(Rd0811); +} +@endif + +# SUB D[15], D[a], D[b] (SRR) +:sub d15,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & d15 & op0007=0x5a +{ + d15 = Rd0811 - Rd1215; + overflowflags(d15); +} + +# SUB D[a], D[b] (SRR) +:sub Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xa2 +{ + Rd0811 = Rd0811 - Rd1215; + overflowflags(Rd0811); +} + +# SUB D[c], D[a], D[b] (RR) +:sub Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x80 +{ + Rd2831 = Rd0811 - Rd1215; + overflowflags(Rd2831); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# SUB.A A[10], const8 (SC) +:sub.a a10,const0815Z is PCPMode=0 & a10 & const0815Z & op0007=0x20 +{ + a10 = a10 - const0815Z; +} +@endif + +# SUB.A A[c], A[a], A[b] (RR) +:sub.a Ra2831,Ra0811,Ra1215 is PCPMode=0 & Ra0811 & Ra1215 & op0007=0x1 ; Ra2831 & op1627=0x20 +{ + Ra2831 = Ra0811 - Ra1215; +} + +# SUB.B D[c], D[a], D[b] (RR) +:sub.b Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x480 +{ + local result3:4 = zext(Rd0811[24,8] - Rd1215[24,8]); + local result2:4 = zext(Rd0811[16,8] - Rd1215[16,8]); + local result1:4 = zext(Rd0811[8,8] - Rd1215[8,8]); + local result0:4 = zext(Rd0811[0,8] - Rd1215[0,8]); + overflowflagsb(result3, result2, result1, result0); + Rd2831 = zext(result3[0,8] << 24) | zext(result2[0,8] << 16) | zext(result1[0,8] << 8) | zext(result0[0,8]); +} + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# SUB.F D[c], D[d], D[a] (RRR) +:sub.f Rd2831,Rd2427,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x6b & op1215=0x0 ; Rd2427 & Rd2831 & op1623=0x31 +{ + #TODO float + #TODO flags + Rd2831 = Rd2427 f- Rd0811; +} +@endif + +# SUB.H D[c], D[a], D[b] (RR) +:sub.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x680 +{ + local result1:4 = zext(Rd0811[16,16] - Rd1215[16,16]); + local result0:4 = zext(Rd0811[0,16] - Rd1215[0,16]); + overflowflagsh(result1, result0); + Rd2831 = (zext(result1[0,16]) << 16) | zext(result0[0,16]); +} + +# SUBC D[c], D[a], D[b] (RR) +:subc Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0xd0 +{ + local tmp:5 = zext(Rd0811) - zext(Rd1215) + zext($(PSW_C)) - 1; + Rd2831 = tmp[0,32]; + $(PSW_C) = tmp[32,1]; + overflowflags(Rd2831); +} + +# SUBS D[a], D[b] (SRR) +:subs Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x62 +{ + local result:4 = Rd0811 - Rd1215; + overflowflags(result); + ssov(Rd0811, result, 32); +} + +# SUBS D[c], D[a], D[b] (RR) +:subs Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0xa0 +{ + local result:4 = Rd0811 - Rd1215; + overflowflags(result); + ssov(Rd2831, result, 32); +} + +# SUBS.H D[c], D[a], D[b] (RR) +:subs.h Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x6a0 +{ + local result1:4 = zext(Rd0811[16,16] - Rd1215[16,16]); + local result0:4 = zext(Rd0811[0,16] - Rd1215[0,16]); + overflowflagsh(result1, result0); + ssov(Rd2831[16,16], result1[0,16], 16); + ssov(Rd2831[0,16], result0[0,16], 16); +} + +# SUBS.HU D[c], D[a], D[b] (RR) +:subs.hu Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x6b0 +{ + local result1:4 = zext(Rd0811[16,16] - Rd1215[16,16]); + local result0:4 = zext(Rd0811[0,16] - Rd1215[0,16]); + overflowflagsh(result1, result0); + suov(Rd2831[16,16], result1[0,16], 16); + suov(Rd2831[0,16], result0[0,16], 16); +} + +# SUBS.U D[c], D[a], D[b] (RR) +:subs.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0xb0 +{ + local result:4 = Rd0811 - Rd1215; + overflowflags(result); + suov(Rd2831, result, 32); +} + +# SUBX D[c], D[a], D[b] (RR) +:subx Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0xc0 +{ + Rd2831 = Rd0811 - Rd1215; + local tmp:5 = zext(Rd0811) + ~zext(Rd1215) + 1; + $(PSW_C) = tmp[32,1]; + overflowflags(Rd2831); +} + +# SVLCX (SYS) +:svlcx is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x200 +{ + #TODO context + # if (FCX == 0) trap(FCU); + # tmp_FCX = FCX; + # EA = {FCX.FCXS, 6'b0, FCX.FCXO, 6'b0}; + # new_FCX = M(EA, word); + # M(EA, 16 * word) = {PCXI, A[11], A[2], A[3], D[0], D[1], D[2], D[3], A[4], A[5], A[6], A[7], D[4], D[5], D[6], D[7]}; + # PCXI.PCPN = ICR.CCPN + # PCXI.PIE = ICR.IE; + # PCXI.UL = 0; + # PCXI[19:0] = FCX[19:0]; + # FCX[19:0] = new_FCX[19:0]; + # if (tmp_FCX == LCX) trap(FCD); +} + +# SWAP.W A[b], off10, D[a] (BO)(Base + Short Offset Addressing Mode) +# SWAP.W P[b], D[a] (BO)(Bit-reverse Addressing Mode) +# SWAP.W A[b], off10, D[a] (BO)(Pre-increment Addressing Mode) +# SWAP.W A[b], off10, D[a] (BO)(Base + Short Offset Addressing Mode) +# SWAP.W P[b], D[a] (BO)(Index Addressing Mode) +:swap.w BO,Rd0811 is PCPMode=0 & ( Rd0811 & op0607=0x1 ; op2225=0x0 ) & BO +{ + build BO; + local tmp:4 = *[ram]:4 BO; + *[ram]:4 BO = Rd0811; + Rd0811 = tmp; +} + +# SWAP.W off18, D[a] (ABS)(Absolute Addressing Mode) +:swap.w off18,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0xe5 ; op2627=0x0 ) & off18 +{ + local tmp:4 = *[ram]:4 off18; + *[ram]:4 off18 = Rd0811; + Rd0811 = tmp; +} + +# SWAP.W P[b], off10, D[a] (BO)(Circular Addressing Mode) +#:swap.w BO,Rd0811 is PCPMode=0 & ( Rd0811 & op0007=0x69 ; op2227=0x10 ) & BO +:swap.w [Rpe1215/Rpo1215^"+c"^]off10,Rd0811 is PCPMode=0 & Rd0811 & Rpe1215 & Rpo1215 & op0007=0x69 ; off10 & op2227=0x10 +{ + local EA:4; + CircularAddressingMode(Rpe1215, Rpo1215, EA, off10); + local tmp:4 = *[ram]:4 EA; + *[ram]:4 EA = Rd0811; + Rd0811 = tmp; +} + +@if defined(TRICORE_V2) +# SWAPMSK.W A[b], off10, E[a] (BO)(Post-increment Addressing Mode) +# SWAPMSK.W P[b], E[a] (BO)(Bit-reverse Addressing Mode) +# SWAPMSK.W A[b], off10, E[a] (BO)(Pre-increment Addressing Mode) +# SWAPMSK.W A[b], off10, E[a] (BO)(Base + Short Offset Addressing Mode) +# SWAPMSK.W P[b], E[a] (BO)(Index Addressing Mode) +:swapmsk.w BO,Ree0811/Reo0811 is PCPMode=0 & ( Ree0811 & Reo0811 & op0607=0x1 ; op2225=0x2 ) & BO +{ + build BO; + local tmp:4 = *[ram]:4 BO; + *[ram]:4 BO = (tmp & ~Reo0811) | (Ree0811 & Reo0811); +} + +# SWAPMSK.W P[b], off10, E[a] (BO)(Circular Addressing Mode) +#:swapmsk.w BO,Ree0811/Reo0811 is PCPMode=0 & ( Ree0811 & Reo0811 & op0007=0x69 ; op2227=0x12 ) & BO +:swapmsk.w [Rpe1215/Rpo1215^"+c"^]off10,Ree0811/Reo0811 is PCPMode=0 & Ree0811 & Reo0811 & Rpe1215 & Rpo1215 & op0007=0x69 ; off10 & op2227=0x12 +{ + local EA:4; + CircularAddressingMode(Rpe1215, Rpo1215, EA, off10); + local tmp:4 = *[ram]:4 EA; + *[ram]:4 EA = (tmp & ~Reo0811) | (Ree0811 & Reo0811); +} +@endif + +# SYSCALL const9 (RC) +:syscall const1220Z is PCPMode=0 & ( op0007=0xad & op0811=0x0 ; op2131=0x4 ) & const1220Z +{ + #TODO TIN SYS + trap(const1220Z[0,8]); +} + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +:tlbdemap Rd0811 is PCPMode=0 & Rd0811 & op0007=0x75 & op1215=0x0 ; op1631=0x0 +{ + tlbdemap(Rd0811); +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +:tlbflush.a is PCPMode=0 & op0007=0x75 & op0815=0x0 ; op1631=0x40 +{ + tlbflusha(); +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +:tlbflush.b is PCPMode=0 & op0007=0x75 & op0815=0x0 ; op1631=0x50 +{ + tlbflushb(); +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +:tlbmap Re0811 is PCPMode=0 & Re0811 & op0007=0x75 & op1215=0x0 ; op1631=0x400 +{ + tlbmap(Re0811); +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +:tlbprobe.a Rd0811 is PCPMode=0 & Rd0811 & op0007=0x75 & op1215=0x0 ; op1631=0x80 +{ + tlbprobea(Rd0811); +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +:tlbprobe.i Rd0811 is PCPMode=0 & Rd0811 & op0007=0x75 & op1215=0x0 ; op1631=0x90 +{ + tlbprobei(Rd0811); +} +@endif + +# TRAPSV (SYS) +:trapsv is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x540 +{ + #TODO TIN SOVF + if ($(PSW_SV) == 0) goto inst_next; + trap(); +} + +# TRAPV (SYS) +:trapv is PCPMode=0 & op0007=0xd & op0815=0x0 ; op1631=0x500 +{ + #TODO TIN OVF + if ($(PSW_V) == 0) goto inst_next; + trap(); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# UNPACK E[c], D[a] (RR) +:unpack Re2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; Re2831 & op1627=0x80 +{ + #TODO + #TODO float En+1 = exp and En = mantissa +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# UPDFL D[a] (RR) +:updfl Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; op1631=0xc1 +{ + $(PSW_FS) = ($(PSW_FS) & ~Rd0811[15,1]) | (Rd0811[7,1] & Rd0811[15,1]); + $(PSW_FI) = ($(PSW_FI) & ~Rd0811[14,1]) | (Rd0811[6,1] & Rd0811[14,1]); + $(PSW_FV) = ($(PSW_FV) & ~Rd0811[13,1]) | (Rd0811[5,1] & Rd0811[13,1]); + $(PSW_FZ) = ($(PSW_FZ) & ~Rd0811[12,1]) | (Rd0811[4,1] & Rd0811[12,1]); + $(PSW_FU) = ($(PSW_FU) & ~Rd0811[11,1]) | (Rd0811[3,1] & Rd0811[11,1]); + $(PSW_FX) = ($(PSW_FX) & ~Rd0811[10,1]) | (Rd0811[2,1] & Rd0811[10,1]); + $(PSW_RM) = ($(PSW_RM) & ~Rd0811[8,2]) | (Rd0811[0,2] & Rd0811[8,2]); +} +@endif + +@if defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# UTOF D[c], D[a] (RR) +:utof Rd2831,Rd0811 is PCPMode=0 & Rd0811 & op0007=0x4b & op1215=0x0 ; Rd2831 & op1627=0x161 +{ + #TODO float + #TODO flags + #TODO unsigned + # Rd2831 = int2float(Rd0811); +} +@endif + +@if defined(TRICORE_V2) +# WAIT (SYS) +:wait is PCPMode=0 & op0007=0xd & op0815=0 ; op1621=0 & op2227=0x16 & op2831=0 +{ + wait(); +} +@endif + +# XNOR D[c], D[a], D[b] (RR) +:xnor Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0xd0 +{ + Rd2831 = ~(Rd0811 ^ Rd1215); +} + +# XNOR D[c], D[a], const9 (RC) +:xnor Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0xd ) & const1220Z +{ + Rd2831 = ~(Rd0811 ^ const1220Z); +} + +# XNOR.T D[c], D[a], pos1, D[b], pos2 (BIT) +:xnor.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x7 ; Rd2831 & const1620Z & const2327Z & op2122=0x2 +{ + local tmpa = (Rd0811 >> const1620Z) & 1; + local tmpb = (Rd1215 >> const2327Z) & 1; + Rd2831 = zext(!(tmpa[0,1] ^ tmpb[0,1])); +} + +@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2) +# XOR D[a], D[b] (SRR) +:xor Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xc6 +{ + Rd0811 = Rd0811 ^ Rd1215; +} +@endif + +# XOR D[c], D[a], D[b] (RR) +:xor Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xf ; Rd2831 & op1627=0xc0 +{ + Rd2831 = Rd0811 ^ Rd1215; +} + +# XOR D[c], D[a], const9 (RC) +:xor Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8f ; Rd2831 & op2127=0xc ) & const1220Z +{ + Rd2831 = Rd0811 ^ const1220Z; +} + +# XOR.EQ D[c], D[a], D[b] (RR) +:xor.eq Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x2f0 +{ + Rd2831[0,1] = Rd2831[0,1] ^ (Rd0811 == Rd1215); +} + +# XOR.EQ D[c], D[a], const9 (RC) +:xor.eq Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x2f ) & const1220S +{ + Rd2831[0,1] = Rd2831[0,1] ^ (Rd0811 == const1220S); +} + +# XOR.GE D[c], D[a], D[b] (RR) +:xor.ge Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x330 +{ + Rd2831[0,1] = Rd2831[0,1] ^ (Rd0811 s>= Rd1215); +} + +# XOR.GE D[c], D[a], const9 (RC) +:xor.ge Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x33 ) & const1220S +{ + Rd2831[0,1] = Rd2831[0,1] ^ (Rd0811 s>= const1220S); +} + +# XOR.GE.U D[c], D[a], D[b] (RR) +:xor.ge.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x340 +{ + Rd2831[0,1] = Rd2831[0,1] ^ (Rd0811 >= Rd1215); +} + +# XOR.GE.U D[c], D[a], const9 (RC) +:xor.ge.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x34 ) & const1220Z +{ + Rd2831[0,1] = Rd2831[0,1] ^ (Rd0811 >= const1220Z); +} + +# XOR.LT D[c], D[a], D[b] (RR) +:xor.lt Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x310 +{ + Rd2831[0,1] = Rd2831[0,1] ^ (Rd0811 s< Rd1215); +} + +# XOR.LT D[c], D[a], const9 (RC) +:xor.lt Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x31 ) & const1220S +{ + Rd2831[0,1] = Rd2831[0,1] ^ (Rd0811 s< const1220S); +} + +# XOR.LT.U D[c], D[a], D[b] (RR) +:xor.lt.u Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x320 +{ + Rd2831[0,1] = Rd2831[0,1] ^ (Rd0811 < Rd1215); +} + +# XOR.LT.U D[c], D[a], const9 (RC) +:xor.lt.u Rd2831,Rd0811,const1220Z is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x32 ) & const1220Z +{ + Rd2831[0,1] = Rd2831[0,1] ^ (Rd0811 < const1220Z); +} + +# XOR.NE D[c], D[a], D[b] (RR) +:xor.ne Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x300 +{ + Rd2831[0,1] = Rd2831[0,1] ^ (Rd0811 != Rd1215); +} + +# XOR.NE D[c], D[a], const9 (RC) +:xor.ne Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x30 ) & const1220S +{ + Rd2831[0,1] = Rd2831[0,1] ^ (Rd0811 != const1220S); +} + +# XOR.T D[c], D[a], pos1, D[b], pos2 (BIT) +:xor.t Rd2831,Rd0811,const1620Z,Rd1215,const2327Z is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x7 ; Rd2831 & const1620Z & const2327Z & op2122=0x3 +{ + local tmpa = (Rd0811 >> const1620Z) & 1; + local tmpb = (Rd1215 >> const2327Z) & 1; + Rd2831 = zext(tmpa[0,1] ^ tmpb[0,1]); +} + +@if defined(TRICORE_V2) +:xpose.b Re2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Re2831 & op1627=0x830 +{ + Re2831 = zext(Rd0811[24,8] << 56)|zext(Rd1215[24,8] << 48)|zext(Rd0811[8,8] << 40)|zext(Rd1215[8,8] << 32)|zext(Rd0811[16,8] << 24)|zext(Rd1215[16,8] << 16)|zext(Rd0811[0,8] << 8)|zext(Rd1215[0,8]); +} +@endif + +@if defined(TRICORE_V2) +:xpose.h Re2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Re2831 & op1627=0x820 +{ + Re2831 = zext(Rd0811[16,16] << 48)|zext(Rd1215[16,16] << 32)|zext(Rd0811[0,16] << 16)|zext(Rd1215[0,16]); +} +@endif + +# @if defined(TRICORE_V2) +# :yield +# { +# } +# @endif + + +@include "tricore.pcp.sinc" diff --git a/python/icicle/Ghidra/Processors/tricore/data/languages/tricore.slaspec b/python/icicle/Ghidra/Processors/tricore/data/languages/tricore.slaspec new file mode 100644 index 0000000..d4b7811 --- /dev/null +++ b/python/icicle/Ghidra/Processors/tricore/data/languages/tricore.slaspec @@ -0,0 +1,13 @@ +@define Tricore "" + +@define TRICORE_GENERIC "" +#@define TRICORE_RIDER_D "" +#@define TRICORE_RIDER_B "" + +@define TRICORE_V2 "" + +#@define TRICORE_VERBOSE "" + +define endian=little; + +@include "tricore.sinc" diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/adx.sinc b/python/icicle/Ghidra/Processors/x86/data/languages/adx.sinc new file mode 100644 index 0000000..1612b38 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/adx.sinc @@ -0,0 +1,33 @@ +:ADCX Reg32, rm32 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xF6; rm32 & Reg32 ... & check_Reg32_dest ... { + tmp:5 = zext(Reg32) + zext(rm32) + zext(CF); + tmpCF:1 = tmp(4); # just the carry byte + CF = tmpCF != 0; + Reg32 = tmp:4; + build check_Reg32_dest; +} + +@ifdef IA64 +:ADCX Reg64, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xF6; Reg64 ... & rm64 { + tmp:9 = zext(Reg64) + zext(rm64) + zext(CF); + tmpCF:1 = tmp(8); # just the carry byte + CF = tmpCF != 0; + Reg64 = tmp:8; +} +@endif + +:ADOX Reg32, rm32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x38; byte=0xF6; rm32 & Reg32 ... & check_Reg32_dest ... { + tmp:5 = zext(Reg32) + zext(rm32) + zext(OF); + tmpOF:1 = tmp(4); # just the carry byte + OF = tmpOF != 0; + Reg32 = tmp:4; + build check_Reg32_dest; +} + +@ifdef IA64 +:ADOX Reg64, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0F; byte=0x38; byte=0xF6; Reg64 ... & rm64 { + tmp:9 = zext(Reg64) + zext(rm64) + zext(OF); + tmpOF:1 = tmp(8); # just the carry byte + OF = tmpOF != 0; + Reg64 = tmp:8; +} +@endif diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/avx.sinc b/python/icicle/Ghidra/Processors/x86/data/languages/avx.sinc new file mode 100644 index 0000000..cd42ee5 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/avx.sinc @@ -0,0 +1,3275 @@ +# INFO This file automatically generated by andre on Thu May 10 10:49:02 2018 +# INFO Direct edits to this file may be lost in future updates +# INFO Command line arguments: ['--sinc', '--cpuid-match', '^AVX\\b', '--skip-sinc', '../../../Processors/x86/data/languages/avx_manual.sinc'] + +# ADDPD 3-33 PAGE 603 LINE 33405 +define pcodeop vaddpd_avx ; +:VADDPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vaddpd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# ADDPD 3-33 PAGE 603 LINE 33408 +:VADDPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x58; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vaddpd_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# ADDPS 3-36 PAGE 606 LINE 33558 +define pcodeop vaddps_avx ; +:VADDPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vaddps_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# ADDPS 3-36 PAGE 606 LINE 33560 +:VADDPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x58; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vaddps_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# ADDSD 3-39 PAGE 609 LINE 33718 +define pcodeop vaddsd_avx ; +:VADDSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vaddsd_avx( vexVVVV_XmmReg, XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# ADDSS 3-41 PAGE 611 LINE 33812 +define pcodeop vaddss_avx ; +:VADDSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vaddss_avx( vexVVVV_XmmReg, XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# ADDSUBPD 3-43 PAGE 613 LINE 33906 +define pcodeop vaddsubpd_avx ; +:VADDSUBPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD0; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vaddsubpd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# ADDSUBPD 3-43 PAGE 613 LINE 33909 +:VADDSUBPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD0; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vaddsubpd_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# ADDSUBPS 3-45 PAGE 615 LINE 34013 +define pcodeop vaddsubps_avx ; +:VADDSUBPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD0; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vaddsubps_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# ADDSUBPS 3-45 PAGE 615 LINE 34016 +:VADDSUBPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD0; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vaddsubps_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# ANDPD 3-64 PAGE 634 LINE 34821 +define pcodeop vandpd_avx ; +:VANDPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vandpd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# ANDPD 3-64 PAGE 634 LINE 34824 +:VANDPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x54; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vandpd_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# ANDPS 3-67 PAGE 637 LINE 34947 +define pcodeop vandps_avx ; +:VANDPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vandps_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# ANDPS 3-67 PAGE 637 LINE 34950 +:VANDPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x54; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vandps_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# ANDNPD 3-70 PAGE 640 LINE 35081 +define pcodeop vandnpd_avx ; +:VANDNPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vandnpd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# ANDNPD 3-70 PAGE 640 LINE 35084 +:VANDNPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x55; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vandnpd_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# ANDNPS 3-73 PAGE 643 LINE 35207 +define pcodeop vandnps_avx ; +:VANDNPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vandnps_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# ANDNPS 3-73 PAGE 643 LINE 35210 +:VANDNPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x55; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vandnps_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# BLENDPD 3-78 PAGE 648 LINE 35433 +define pcodeop vblendpd_avx ; +:VBLENDPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8_3_0 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0D; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; imm8_3_0 +{ + local tmp:16 = vblendpd_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8_3_0:1 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# BLENDPD 3-78 PAGE 648 LINE 35436 +:VBLENDPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8_3_0 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x0D; YmmReg1 ... & YmmReg2_m256; imm8_3_0 +{ + YmmReg1 = vblendpd_avx( vexVVVV_YmmReg, YmmReg2_m256, imm8_3_0:1 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# BLENDPS 3-81 PAGE 651 LINE 35580 +define pcodeop vblendps_avx ; +:VBLENDPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0C; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; imm8 +{ + local tmp:16 = vblendps_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# BLENDPS 3-81 PAGE 651 LINE 35583 +:VBLENDPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x0C; YmmReg1 ... & YmmReg2_m256; imm8 +{ + YmmReg1 = vblendps_avx( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# BLENDVPD 3-83 PAGE 653 LINE 35684 +define pcodeop vblendvpd_avx ; +:VBLENDVPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, Xmm_imm8_7_4 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x4B; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; Xmm_imm8_7_4 +{ + local tmp:16 = vblendvpd_avx( vexVVVV_XmmReg, XmmReg2_m128, Xmm_imm8_7_4 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# BLENDVPD 3-83 PAGE 653 LINE 35688 +:VBLENDVPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, Ymm_imm8_7_4 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x4B; YmmReg1 ... & YmmReg2_m256; Ymm_imm8_7_4 +{ + YmmReg1 = vblendvpd_avx( vexVVVV_YmmReg, YmmReg2_m256, Ymm_imm8_7_4 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# BLENDVPS 3-85 PAGE 655 LINE 35789 +define pcodeop vblendvps_avx ; +:VBLENDVPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, Xmm_imm8_7_4 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x4A; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; Xmm_imm8_7_4 +{ + local tmp:16 = vblendvps_avx( vexVVVV_XmmReg, XmmReg2_m128, Xmm_imm8_7_4 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# BLENDVPS 3-85 PAGE 655 LINE 35793 +:VBLENDVPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, Ymm_imm8_7_4 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x4A; YmmReg1 ... & YmmReg2_m256; Ymm_imm8_7_4 +{ + YmmReg1 = vblendvps_avx( vexVVVV_YmmReg, YmmReg2_m256, Ymm_imm8_7_4 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# CMPPD 3-155 PAGE 725 LINE 39240 +VCMPPD_mon: "VCMPEQPD" is imm8=0x0 { } +VCMPPD_op: "" is imm8=0x0 { export 0x0:1; } +VCMPPD_mon: "VCMPLTPD" is imm8=0x1 { } +VCMPPD_op: "" is imm8=0x1 { export 0x1:1; } +VCMPPD_mon: "VCMPLEPD" is imm8=0x2 { } +VCMPPD_op: "" is imm8=0x2 { export 0x2:1; } +VCMPPD_mon: "VCMPUNORDPD" is imm8=0x3 { } +VCMPPD_op: "" is imm8=0x3 { export 0x3:1; } +VCMPPD_mon: "VCMPNEQPD" is imm8=0x4 { } +VCMPPD_op: "" is imm8=0x4 { export 0x4:1; } +VCMPPD_mon: "VCMPNLTPD" is imm8=0x5 { } +VCMPPD_op: "" is imm8=0x5 { export 0x5:1; } +VCMPPD_mon: "VCMPNLEPD" is imm8=0x6 { } +VCMPPD_op: "" is imm8=0x6 { export 0x6:1; } +VCMPPD_mon: "VCMPORDPD" is imm8=0x7 { } +VCMPPD_op: "" is imm8=0x7 { export 0x7:1; } +VCMPPD_mon: "VCMPEQ_UQPD" is imm8=0x8 { } +VCMPPD_op: "" is imm8=0x8 { export 0x8:1; } +VCMPPD_mon: "VCMPNGEPD" is imm8=0x9 { } +VCMPPD_op: "" is imm8=0x9 { export 0x9:1; } +VCMPPD_mon: "VCMPNGTPD" is imm8=0xa { } +VCMPPD_op: "" is imm8=0xa { export 0xa:1; } +VCMPPD_mon: "VCMPFALSEPD" is imm8=0xb { } +VCMPPD_op: "" is imm8=0xb { export 0xb:1; } +VCMPPD_mon: "VCMPNEQ_OQPD" is imm8=0xc { } +VCMPPD_op: "" is imm8=0xc { export 0xc:1; } +VCMPPD_mon: "VCMPGEPD" is imm8=0xd { } +VCMPPD_op: "" is imm8=0xd { export 0xd:1; } +VCMPPD_mon: "VCMPGTPD" is imm8=0xe { } +VCMPPD_op: "" is imm8=0xe { export 0xe:1; } +VCMPPD_mon: "VCMPTRUEPD" is imm8=0xf { } +VCMPPD_op: "" is imm8=0xf { export 0xf:1; } +VCMPPD_mon: "VCMPEQ_OSPD" is imm8=0x10 { } +VCMPPD_op: "" is imm8=0x10 { export 0x10:1; } +VCMPPD_mon: "VCMPLT_OQPD" is imm8=0x11 { } +VCMPPD_op: "" is imm8=0x11 { export 0x11:1; } +VCMPPD_mon: "VCMPLE_OQPD" is imm8=0x12 { } +VCMPPD_op: "" is imm8=0x12 { export 0x12:1; } +VCMPPD_mon: "VCMPUNORD_SPD" is imm8=0x13 { } +VCMPPD_op: "" is imm8=0x13 { export 0x13:1; } +VCMPPD_mon: "VCMPNEQ_USPD" is imm8=0x14 { } +VCMPPD_op: "" is imm8=0x14 { export 0x14:1; } +VCMPPD_mon: "VCMPNLT_UQPD" is imm8=0x15 { } +VCMPPD_op: "" is imm8=0x15 { export 0x15:1; } +VCMPPD_mon: "VCMPNLE_UQPD" is imm8=0x16 { } +VCMPPD_op: "" is imm8=0x16 { export 0x16:1; } +VCMPPD_mon: "VCMPORD_SPD" is imm8=0x17 { } +VCMPPD_op: "" is imm8=0x17 { export 0x17:1; } +VCMPPD_mon: "VCMPEQ_USPD" is imm8=0x18 { } +VCMPPD_op: "" is imm8=0x18 { export 0x18:1; } +VCMPPD_mon: "VCMPNGE_UQPD" is imm8=0x19 { } +VCMPPD_op: "" is imm8=0x19 { export 0x19:1; } +VCMPPD_mon: "VCMPNGT_UQPD" is imm8=0x1a { } +VCMPPD_op: "" is imm8=0x1a { export 0x1a:1; } +VCMPPD_mon: "VCMPFALSE_OSPD" is imm8=0x1b { } +VCMPPD_op: "" is imm8=0x1b { export 0x1b:1; } +VCMPPD_mon: "VCMPNEQ_OSPD" is imm8=0x1c { } +VCMPPD_op: "" is imm8=0x1c { export 0x1c:1; } +VCMPPD_mon: "VCMPGE_OQPD" is imm8=0x1d { } +VCMPPD_op: "" is imm8=0x1d { export 0x1d:1; } +VCMPPD_mon: "VCMPGT_OQPD" is imm8=0x1e { } +VCMPPD_op: "" is imm8=0x1e { export 0x1e:1; } +VCMPPD_mon: "VCMPTRUE_USPD" is imm8=0x1f { } +VCMPPD_op: "" is imm8=0x1f { export 0x1f:1; } +VCMPPD_mon: "VCMPPD" is imm8 { } +VCMPPD_op: ", "^imm8 is imm8 { export *[const]:1 imm8; } +define pcodeop vcmppd_avx ; +:^VCMPPD_mon XmmReg1, vexVVVV_XmmReg, XmmReg2_m128^VCMPPD_op is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xC2; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; VCMPPD_mon & VCMPPD_op +{ + local tmp:16 = vcmppd_avx( vexVVVV_XmmReg, XmmReg2_m128, VCMPPD_op ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# CMPPD 3-155 PAGE 725 LINE 39243 +:^VCMPPD_mon YmmReg1, vexVVVV_YmmReg, YmmReg2_m256^VCMPPD_op is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xC2; YmmReg1 ... & YmmReg2_m256; VCMPPD_mon & VCMPPD_op +{ + YmmReg1 = vcmppd_avx( vexVVVV_YmmReg, YmmReg2_m256, VCMPPD_op ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# CMPPS 3-162 PAGE 732 LINE 39607 +VCMPPS_mon: "VCMPEQPS" is imm8=0x0 { } +VCMPPS_op: "" is imm8=0x0 { export 0x0:1; } +VCMPPS_mon: "VCMPLTPS" is imm8=0x1 { } +VCMPPS_op: "" is imm8=0x1 { export 0x1:1; } +VCMPPS_mon: "VCMPLEPS" is imm8=0x2 { } +VCMPPS_op: "" is imm8=0x2 { export 0x2:1; } +VCMPPS_mon: "VCMPUNORDPS" is imm8=0x3 { } +VCMPPS_op: "" is imm8=0x3 { export 0x3:1; } +VCMPPS_mon: "VCMPNEQPS" is imm8=0x4 { } +VCMPPS_op: "" is imm8=0x4 { export 0x4:1; } +VCMPPS_mon: "VCMPNLTPS" is imm8=0x5 { } +VCMPPS_op: "" is imm8=0x5 { export 0x5:1; } +VCMPPS_mon: "VCMPNLEPS" is imm8=0x6 { } +VCMPPS_op: "" is imm8=0x6 { export 0x6:1; } +VCMPPS_mon: "VCMPORDPS" is imm8=0x7 { } +VCMPPS_op: "" is imm8=0x7 { export 0x7:1; } +VCMPPS_mon: "VCMPEQ_UQPS" is imm8=0x8 { } +VCMPPS_op: "" is imm8=0x8 { export 0x8:1; } +VCMPPS_mon: "VCMPNGEPS" is imm8=0x9 { } +VCMPPS_op: "" is imm8=0x9 { export 0x9:1; } +VCMPPS_mon: "VCMPNGTPS" is imm8=0xa { } +VCMPPS_op: "" is imm8=0xa { export 0xa:1; } +VCMPPS_mon: "VCMPFALSEPS" is imm8=0xb { } +VCMPPS_op: "" is imm8=0xb { export 0xb:1; } +VCMPPS_mon: "VCMPNEQ_OQPS" is imm8=0xc { } +VCMPPS_op: "" is imm8=0xc { export 0xc:1; } +VCMPPS_mon: "VCMPGEPS" is imm8=0xd { } +VCMPPS_op: "" is imm8=0xd { export 0xd:1; } +VCMPPS_mon: "VCMPGTPS" is imm8=0xe { } +VCMPPS_op: "" is imm8=0xe { export 0xe:1; } +VCMPPS_mon: "VCMPTRUEPS" is imm8=0xf { } +VCMPPS_op: "" is imm8=0xf { export 0xf:1; } +VCMPPS_mon: "VCMPEQ_OSPS" is imm8=0x10 { } +VCMPPS_op: "" is imm8=0x10 { export 0x10:1; } +VCMPPS_mon: "VCMPLT_OQPS" is imm8=0x11 { } +VCMPPS_op: "" is imm8=0x11 { export 0x11:1; } +VCMPPS_mon: "VCMPLE_OQPS" is imm8=0x12 { } +VCMPPS_op: "" is imm8=0x12 { export 0x12:1; } +VCMPPS_mon: "VCMPUNORD_SPS" is imm8=0x13 { } +VCMPPS_op: "" is imm8=0x13 { export 0x13:1; } +VCMPPS_mon: "VCMPNEQ_USPS" is imm8=0x14 { } +VCMPPS_op: "" is imm8=0x14 { export 0x14:1; } +VCMPPS_mon: "VCMPNLT_UQPS" is imm8=0x15 { } +VCMPPS_op: "" is imm8=0x15 { export 0x15:1; } +VCMPPS_mon: "VCMPNLE_UQPS" is imm8=0x16 { } +VCMPPS_op: "" is imm8=0x16 { export 0x16:1; } +VCMPPS_mon: "VCMPORD_SPS" is imm8=0x17 { } +VCMPPS_op: "" is imm8=0x17 { export 0x17:1; } +VCMPPS_mon: "VCMPEQ_USPS" is imm8=0x18 { } +VCMPPS_op: "" is imm8=0x18 { export 0x18:1; } +VCMPPS_mon: "VCMPNGE_UQPS" is imm8=0x19 { } +VCMPPS_op: "" is imm8=0x19 { export 0x19:1; } +VCMPPS_mon: "VCMPNGT_UQPS" is imm8=0x1a { } +VCMPPS_op: "" is imm8=0x1a { export 0x1a:1; } +VCMPPS_mon: "VCMPFALSE_OSPS" is imm8=0x1b { } +VCMPPS_op: "" is imm8=0x1b { export 0x1b:1; } +VCMPPS_mon: "VCMPNEQ_OSPS" is imm8=0x1c { } +VCMPPS_op: "" is imm8=0x1c { export 0x1c:1; } +VCMPPS_mon: "VCMPGE_OQPS" is imm8=0x1d { } +VCMPPS_op: "" is imm8=0x1d { export 0x1d:1; } +VCMPPS_mon: "VCMPGT_OQPS" is imm8=0x1e { } +VCMPPS_op: "" is imm8=0x1e { export 0x1e:1; } +VCMPPS_mon: "VCMPTRUE_USPS" is imm8=0x1f { } +VCMPPS_op: "" is imm8=0x1f { export 0x1f:1; } +VCMPPS_mon: "VCMPPS" is imm8 { } +VCMPPS_op: ", "^imm8 is imm8 { export *[const]:1 imm8; } +define pcodeop vcmpps_avx ; +:^VCMPPS_mon XmmReg1, vexVVVV_XmmReg, XmmReg2_m128^VCMPPS_op is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xC2; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; VCMPPS_mon & VCMPPS_op +{ + local tmp:16 = vcmpps_avx( vexVVVV_XmmReg, XmmReg2_m128, VCMPPS_op ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# CMPPS 3-162 PAGE 732 LINE 39610 +:^VCMPPS_mon YmmReg1, vexVVVV_YmmReg, YmmReg2_m256^VCMPPS_op is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xC2; YmmReg1 ... & YmmReg2_m256; VCMPPS_mon & VCMPPS_op +{ + YmmReg1 = vcmpps_avx( vexVVVV_YmmReg, YmmReg2_m256, VCMPPS_op ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# CMPSD 3-173 PAGE 743 LINE 40154 +VCMPSD_mon: "VCMPEQSD" is imm8=0x0 { } +VCMPSD_op: "" is imm8=0x0 { export 0x0:1; } +VCMPSD_mon: "VCMPLTSD" is imm8=0x1 { } +VCMPSD_op: "" is imm8=0x1 { export 0x1:1; } +VCMPSD_mon: "VCMPLESD" is imm8=0x2 { } +VCMPSD_op: "" is imm8=0x2 { export 0x2:1; } +VCMPSD_mon: "VCMPUNORDSD" is imm8=0x3 { } +VCMPSD_op: "" is imm8=0x3 { export 0x3:1; } +VCMPSD_mon: "VCMPNEQSD" is imm8=0x4 { } +VCMPSD_op: "" is imm8=0x4 { export 0x4:1; } +VCMPSD_mon: "VCMPNLTSD" is imm8=0x5 { } +VCMPSD_op: "" is imm8=0x5 { export 0x5:1; } +VCMPSD_mon: "VCMPNLESD" is imm8=0x6 { } +VCMPSD_op: "" is imm8=0x6 { export 0x6:1; } +VCMPSD_mon: "VCMPORDSD" is imm8=0x7 { } +VCMPSD_op: "" is imm8=0x7 { export 0x7:1; } +VCMPSD_mon: "VCMPEQ_UQSD" is imm8=0x8 { } +VCMPSD_op: "" is imm8=0x8 { export 0x8:1; } +VCMPSD_mon: "VCMPNGESD" is imm8=0x9 { } +VCMPSD_op: "" is imm8=0x9 { export 0x9:1; } +VCMPSD_mon: "VCMPNGTSD" is imm8=0xa { } +VCMPSD_op: "" is imm8=0xa { export 0xa:1; } +VCMPSD_mon: "VCMPFALSESD" is imm8=0xb { } +VCMPSD_op: "" is imm8=0xb { export 0xb:1; } +VCMPSD_mon: "VCMPNEQ_OQSD" is imm8=0xc { } +VCMPSD_op: "" is imm8=0xc { export 0xc:1; } +VCMPSD_mon: "VCMPGESD" is imm8=0xd { } +VCMPSD_op: "" is imm8=0xd { export 0xd:1; } +VCMPSD_mon: "VCMPGTSD" is imm8=0xe { } +VCMPSD_op: "" is imm8=0xe { export 0xe:1; } +VCMPSD_mon: "VCMPTRUESD" is imm8=0xf { } +VCMPSD_op: "" is imm8=0xf { export 0xf:1; } +VCMPSD_mon: "VCMPEQ_OSSD" is imm8=0x10 { } +VCMPSD_op: "" is imm8=0x10 { export 0x10:1; } +VCMPSD_mon: "VCMPLT_OQSD" is imm8=0x11 { } +VCMPSD_op: "" is imm8=0x11 { export 0x11:1; } +VCMPSD_mon: "VCMPLE_OQSD" is imm8=0x12 { } +VCMPSD_op: "" is imm8=0x12 { export 0x12:1; } +VCMPSD_mon: "VCMPUNORD_SSD" is imm8=0x13 { } +VCMPSD_op: "" is imm8=0x13 { export 0x13:1; } +VCMPSD_mon: "VCMPNEQ_USSD" is imm8=0x14 { } +VCMPSD_op: "" is imm8=0x14 { export 0x14:1; } +VCMPSD_mon: "VCMPNLT_UQSD" is imm8=0x15 { } +VCMPSD_op: "" is imm8=0x15 { export 0x15:1; } +VCMPSD_mon: "VCMPNLE_UQSD" is imm8=0x16 { } +VCMPSD_op: "" is imm8=0x16 { export 0x16:1; } +VCMPSD_mon: "VCMPORD_SSD" is imm8=0x17 { } +VCMPSD_op: "" is imm8=0x17 { export 0x17:1; } +VCMPSD_mon: "VCMPEQ_USSD" is imm8=0x18 { } +VCMPSD_op: "" is imm8=0x18 { export 0x18:1; } +VCMPSD_mon: "VCMPNGE_UQSD" is imm8=0x19 { } +VCMPSD_op: "" is imm8=0x19 { export 0x19:1; } +VCMPSD_mon: "VCMPNGT_UQSD" is imm8=0x1a { } +VCMPSD_op: "" is imm8=0x1a { export 0x1a:1; } +VCMPSD_mon: "VCMPFALSE_OSSD" is imm8=0x1b { } +VCMPSD_op: "" is imm8=0x1b { export 0x1b:1; } +VCMPSD_mon: "VCMPNEQ_OSSD" is imm8=0x1c { } +VCMPSD_op: "" is imm8=0x1c { export 0x1c:1; } +VCMPSD_mon: "VCMPGE_OQSD" is imm8=0x1d { } +VCMPSD_op: "" is imm8=0x1d { export 0x1d:1; } +VCMPSD_mon: "VCMPGT_OQSD" is imm8=0x1e { } +VCMPSD_op: "" is imm8=0x1e { export 0x1e:1; } +VCMPSD_mon: "VCMPTRUE_USSD" is imm8=0x1f { } +VCMPSD_op: "" is imm8=0x1f { export 0x1f:1; } +VCMPSD_mon: "VCMPSD" is imm8 { } +VCMPSD_op: ", "^imm8 is imm8 { export *[const]:1 imm8; } +define pcodeop vcmpsd_avx ; +:^VCMPSD_mon XmmReg1, vexVVVV_XmmReg, XmmReg2_m64^VCMPSD_op is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xC2; (XmmReg1 & YmmReg1) ... & XmmReg2_m64; VCMPSD_mon & VCMPSD_op +{ + local tmp:16 = vcmpsd_avx( vexVVVV_XmmReg, XmmReg2_m64, VCMPSD_op ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# CMPSS 3-177 PAGE 747 LINE 40390 +VCMPSS_mon: "VCMPEQSS" is imm8=0x0 { } +VCMPSS_op: "" is imm8=0x0 { export 0x0:1; } +VCMPSS_mon: "VCMPLTSS" is imm8=0x1 { } +VCMPSS_op: "" is imm8=0x1 { export 0x1:1; } +VCMPSS_mon: "VCMPLESS" is imm8=0x2 { } +VCMPSS_op: "" is imm8=0x2 { export 0x2:1; } +VCMPSS_mon: "VCMPUNORDSS" is imm8=0x3 { } +VCMPSS_op: "" is imm8=0x3 { export 0x3:1; } +VCMPSS_mon: "VCMPNEQSS" is imm8=0x4 { } +VCMPSS_op: "" is imm8=0x4 { export 0x4:1; } +VCMPSS_mon: "VCMPNLTSS" is imm8=0x5 { } +VCMPSS_op: "" is imm8=0x5 { export 0x5:1; } +VCMPSS_mon: "VCMPNLESS" is imm8=0x6 { } +VCMPSS_op: "" is imm8=0x6 { export 0x6:1; } +VCMPSS_mon: "VCMPORDSS" is imm8=0x7 { } +VCMPSS_op: "" is imm8=0x7 { export 0x7:1; } +VCMPSS_mon: "VCMPEQ_UQSS" is imm8=0x8 { } +VCMPSS_op: "" is imm8=0x8 { export 0x8:1; } +VCMPSS_mon: "VCMPNGESS" is imm8=0x9 { } +VCMPSS_op: "" is imm8=0x9 { export 0x9:1; } +VCMPSS_mon: "VCMPNGTSS" is imm8=0xa { } +VCMPSS_op: "" is imm8=0xa { export 0xa:1; } +VCMPSS_mon: "VCMPFALSESS" is imm8=0xb { } +VCMPSS_op: "" is imm8=0xb { export 0xb:1; } +VCMPSS_mon: "VCMPNEQ_OQSS" is imm8=0xc { } +VCMPSS_op: "" is imm8=0xc { export 0xc:1; } +VCMPSS_mon: "VCMPGESS" is imm8=0xd { } +VCMPSS_op: "" is imm8=0xd { export 0xd:1; } +VCMPSS_mon: "VCMPGTSS" is imm8=0xe { } +VCMPSS_op: "" is imm8=0xe { export 0xe:1; } +VCMPSS_mon: "VCMPTRUESS" is imm8=0xf { } +VCMPSS_op: "" is imm8=0xf { export 0xf:1; } +VCMPSS_mon: "VCMPEQ_OSSS" is imm8=0x10 { } +VCMPSS_op: "" is imm8=0x10 { export 0x10:1; } +VCMPSS_mon: "VCMPLT_OQSS" is imm8=0x11 { } +VCMPSS_op: "" is imm8=0x11 { export 0x11:1; } +VCMPSS_mon: "VCMPLE_OQSS" is imm8=0x12 { } +VCMPSS_op: "" is imm8=0x12 { export 0x12:1; } +VCMPSS_mon: "VCMPUNORD_SSS" is imm8=0x13 { } +VCMPSS_op: "" is imm8=0x13 { export 0x13:1; } +VCMPSS_mon: "VCMPNEQ_USSS" is imm8=0x14 { } +VCMPSS_op: "" is imm8=0x14 { export 0x14:1; } +VCMPSS_mon: "VCMPNLT_UQSS" is imm8=0x15 { } +VCMPSS_op: "" is imm8=0x15 { export 0x15:1; } +VCMPSS_mon: "VCMPNLE_UQSS" is imm8=0x16 { } +VCMPSS_op: "" is imm8=0x16 { export 0x16:1; } +VCMPSS_mon: "VCMPORD_SSS" is imm8=0x17 { } +VCMPSS_op: "" is imm8=0x17 { export 0x17:1; } +VCMPSS_mon: "VCMPEQ_USSS" is imm8=0x18 { } +VCMPSS_op: "" is imm8=0x18 { export 0x18:1; } +VCMPSS_mon: "VCMPNGE_UQSS" is imm8=0x19 { } +VCMPSS_op: "" is imm8=0x19 { export 0x19:1; } +VCMPSS_mon: "VCMPNGT_UQSS" is imm8=0x1a { } +VCMPSS_op: "" is imm8=0x1a { export 0x1a:1; } +VCMPSS_mon: "VCMPFALSE_OSSS" is imm8=0x1b { } +VCMPSS_op: "" is imm8=0x1b { export 0x1b:1; } +VCMPSS_mon: "VCMPNEQ_OSSS" is imm8=0x1c { } +VCMPSS_op: "" is imm8=0x1c { export 0x1c:1; } +VCMPSS_mon: "VCMPGE_OQSS" is imm8=0x1d { } +VCMPSS_op: "" is imm8=0x1d { export 0x1d:1; } +VCMPSS_mon: "VCMPGT_OQSS" is imm8=0x1e { } +VCMPSS_op: "" is imm8=0x1e { export 0x1e:1; } +VCMPSS_mon: "VCMPTRUE_USSS" is imm8=0x1f { } +VCMPSS_op: "" is imm8=0x1f { export 0x1f:1; } +VCMPSS_mon: "VCMPSS" is imm8 { } +VCMPSS_op: ", "^imm8 is imm8 { export *[const]:1 imm8; } +define pcodeop vcmpss_avx ; +:^VCMPSS_mon XmmReg1, vexVVVV_XmmReg, XmmReg2_m32^VCMPSS_op is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xC2; (XmmReg1 & YmmReg1) ... & XmmReg2_m32; VCMPSS_mon & VCMPSS_op +{ + local tmp:16 = vcmpss_avx( vexVVVV_XmmReg, XmmReg2_m32, VCMPSS_op ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# COMISD 3-186 PAGE 756 LINE 40860 +define pcodeop vcomisd_avx ; +:VCOMISD XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x2F; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vcomisd_avx( XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# COMISS 3-188 PAGE 758 LINE 40938 +define pcodeop vcomiss_avx ; +:VCOMISS XmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x2F; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vcomiss_avx( XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# CVTDQ2PD 3-228 PAGE 798 LINE 43074 +define pcodeop vcvtdq2pd_avx ; +:VCVTDQ2PD XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0xE6; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vcvtdq2pd_avx( XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# CVTDQ2PD 3-228 PAGE 798 LINE 43077 +:VCVTDQ2PD YmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0xE6; YmmReg1 ... & XmmReg2_m128 +{ + YmmReg1 = vcvtdq2pd_avx( XmmReg2_m128 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# CVTDQ2PS 3-232 PAGE 802 LINE 43242 +define pcodeop vcvtdq2ps_avx ; +:VCVTDQ2PS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x5B; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vcvtdq2ps_avx( XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# CVTDQ2PS 3-232 PAGE 802 LINE 43245 +:VCVTDQ2PS YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x5B; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vcvtdq2ps_avx( YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# CVTPD2DQ 3-235 PAGE 805 LINE 43408 +define pcodeop vcvtpd2dq_avx ; +:VCVTPD2DQ XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0xE6; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vcvtpd2dq_avx( XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# CVTPD2DQ 3-235 PAGE 805 LINE 43411 +:VCVTPD2DQ XmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0xE6; (XmmReg1 & YmmReg1) ... & YmmReg2_m256 +{ + local tmp:16 = vcvtpd2dq_avx( YmmReg2_m256 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# CVTPD2PS 3-240 PAGE 810 LINE 43643 +define pcodeop vcvtpd2ps_avx ; +:VCVTPD2PS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x5A; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vcvtpd2ps_avx( XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# CVTPD2PS 3-240 PAGE 810 LINE 43646 +:VCVTPD2PS XmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x5A; (XmmReg1 & YmmReg1) ... & YmmReg2_m256 +{ + local tmp:16 = vcvtpd2ps_avx( YmmReg2_m256 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# CVTPS2DQ 3-246 PAGE 816 LINE 43927 +define pcodeop vcvtps2dq_avx ; +:VCVTPS2DQ XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x5B; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vcvtps2dq_avx( XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# CVTPS2DQ 3-246 PAGE 816 LINE 43930 +:VCVTPS2DQ YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x5B; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vcvtps2dq_avx( YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# CVTPS2PD 3-249 PAGE 819 LINE 44098 +define pcodeop vcvtps2pd_avx ; +:VCVTPS2PD XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x5A; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vcvtps2pd_avx( XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# CVTPS2PD 3-249 PAGE 819 LINE 44101 +:VCVTPS2PD YmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x5A; YmmReg1 ... & XmmReg2_m128 +{ + YmmReg1 = vcvtps2pd_avx( XmmReg2_m128 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VCVTPH2PS 5-33 PAGE 1857 LINE 96839 +define pcodeop vcvtph2ps_f16c ; +:VCVTPH2PS XmmReg1, XmmReg2_m64 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x13; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vcvtph2ps_f16c( XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VCVTPH2PS 5-33 PAGE 1857 LINE 96842 +:VCVTPH2PS YmmReg1, XmmReg2_m128 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x13; YmmReg1 ... & XmmReg2_m128 +{ + YmmReg1 = vcvtph2ps_f16c( XmmReg2_m128 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VCVTPS2PH 5-36 PAGE 1860 LINE 96992 +define pcodeop vcvtps2ph_f16c ; +:VCVTPS2PH XmmReg2_m64, XmmReg1, imm8 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x1D; XmmReg1 ... & XmmReg2_m64; imm8 +{ + XmmReg2_m64 = vcvtps2ph_f16c( XmmReg1, imm8:1 ); + # TODO ZmmReg2 = zext(XmmReg2) +} + +# VCVTPS2PH 5-36 PAGE 1860 LINE 96995 +:VCVTPS2PH XmmReg2_m128, YmmReg1, imm8 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x1D; YmmReg1 ... & XmmReg2_m128; imm8 +{ + XmmReg2_m128 = vcvtps2ph_f16c( YmmReg1, imm8:1 ); + # TODO ZmmReg2 = zext(XmmReg2) +} + + +# CVTSD2SI 3-253 PAGE 823 LINE 44315 +define pcodeop vcvtsd2si_avx ; +:VCVTSD2SI Reg32, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x2D; Reg32 ... & XmmReg2_m64 +{ + Reg32 = vcvtsd2si_avx( XmmReg2_m64 ); + # TODO Reg64 = zext(Reg32) +} + +# CVTSD2SI 3-253 PAGE 823 LINE 44317 +@ifdef IA64 +:VCVTSD2SI Reg64, XmmReg2_m64 is $(LONGMODE_ON) & $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x2D; Reg64 ... & XmmReg2_m64 +{ + Reg64 = vcvtsd2si_avx( XmmReg2_m64 ); +} +@endif + +# CVTSD2SS 3-255 PAGE 825 LINE 44414 +define pcodeop vcvtsd2ss_avx ; +:VCVTSD2SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5A; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vcvtsd2ss_avx( vexVVVV_XmmReg, XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# CVTSI2SD 3-257 PAGE 827 LINE 44516 +define pcodeop vcvtsi2sd_avx ; +:VCVTSI2SD XmmReg1, vexVVVV_XmmReg, rm32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x2A; (XmmReg1 & YmmReg1) ... & rm32 +{ + local tmp:16 = vcvtsi2sd_avx( vexVVVV_XmmReg, rm32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# CVTSI2SD 3-257 PAGE 827 LINE 44519 +@ifdef IA64 +:VCVTSI2SD XmmReg1, vexVVVV_XmmReg, rm64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x2A; (XmmReg1 & YmmReg1) ... & rm64 +{ + local tmp:16 = vcvtsi2sd_avx( vexVVVV_XmmReg, rm64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} +@endif + +# CVTSI2SS 3-259 PAGE 829 LINE 44632 +define pcodeop vcvtsi2ss_avx ; +:VCVTSI2SS XmmReg1, vexVVVV_XmmReg, rm32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x2A; (XmmReg1 & YmmReg1) ... & rm32 +{ + local tmp:16 = vcvtsi2ss_avx( vexVVVV_XmmReg, rm32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# CVTSI2SS 3-259 PAGE 829 LINE 44634 +@ifdef IA64 +:VCVTSI2SS XmmReg1, vexVVVV_XmmReg, rm64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x2A; (XmmReg1 & YmmReg1) ... & rm64 +{ + local tmp:16 = vcvtsi2ss_avx( vexVVVV_XmmReg, rm64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} +@endif + +# CVTSS2SD 3-261 PAGE 831 LINE 44744 +define pcodeop vcvtss2sd_avx ; +:VCVTSS2SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5A; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vcvtss2sd_avx( vexVVVV_XmmReg, XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# CVTSS2SI 3-263 PAGE 833 LINE 44835 +define pcodeop vcvtss2si_avx ; +:VCVTSS2SI Reg32, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x2D; Reg32 ... & XmmReg2_m32 +{ + Reg32 = vcvtss2si_avx( XmmReg2_m32 ); + # TODO Reg64 = zext(Reg32) +} + +# CVTSS2SI 3-263 PAGE 833 LINE 44837 +@ifdef IA64 +:VCVTSS2SI Reg64, XmmReg2_m32 is $(LONGMODE_ON) & $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x2D; Reg64 ... & XmmReg2_m32 +{ + Reg64 = vcvtss2si_avx( XmmReg2_m32 ); +} +@endif + +# CVTTPD2DQ 3-265 PAGE 835 LINE 44930 +define pcodeop vcvttpd2dq_avx ; +:VCVTTPD2DQ XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xE6; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vcvttpd2dq_avx( XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# CVTTPD2DQ 3-265 PAGE 835 LINE 44933 +:VCVTTPD2DQ XmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xE6; (XmmReg1 & YmmReg1) ... & YmmReg2_m256 +{ + local tmp:16 = vcvttpd2dq_avx( YmmReg2_m256 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# CVTTPS2DQ 3-270 PAGE 840 LINE 45163 +define pcodeop vcvttps2dq_avx ; +:VCVTTPS2DQ XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x5B; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vcvttps2dq_avx( XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# CVTTPS2DQ 3-270 PAGE 840 LINE 45166 +:VCVTTPS2DQ YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x5B; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vcvttps2dq_avx( YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# CVTTSD2SI 3-274 PAGE 844 LINE 45379 +define pcodeop vcvttsd2si_avx ; +:VCVTTSD2SI Reg32, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x2C; Reg32 ... & XmmReg2_m64 +{ + Reg32 = vcvttsd2si_avx( XmmReg2_m64 ); + # TODO Reg64 = zext(Reg32) +} + +# CVTTSD2SI 3-274 PAGE 844 LINE 45382 +@ifdef IA64 +:VCVTTSD2SI Reg64, XmmReg2_m64 is $(LONGMODE_ON) & $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x2C; Reg64 ... & XmmReg2_m64 +{ + Reg64 = vcvttsd2si_avx( XmmReg2_m64 ); +} +@endif + +# CVTTSS2SI 3-276 PAGE 846 LINE 45473 +define pcodeop vcvttss2si_avx ; +:VCVTTSS2SI Reg32, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x2C; Reg32 ... & XmmReg2_m32 +{ + Reg32 = vcvttss2si_avx( XmmReg2_m32 ); + # TODO Reg64 = zext(Reg32) +} + +# CVTTSS2SI 3-276 PAGE 846 LINE 45476 +@ifdef IA64 +:VCVTTSS2SI Reg64, XmmReg2_m32 is $(LONGMODE_ON) & $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x2C; Reg64 ... & XmmReg2_m32 +{ + Reg64 = vcvttss2si_avx( XmmReg2_m32 ); +} +@endif + +# DIVPD 3-288 PAGE 858 LINE 46023 +define pcodeop vdivpd_avx ; +:VDIVPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vdivpd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# DIVPD 3-288 PAGE 858 LINE 46026 +:VDIVPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x5E; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vdivpd_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# DIVPS 3-291 PAGE 861 LINE 46164 +define pcodeop vdivps_avx ; +:VDIVPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vdivps_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# DIVPS 3-291 PAGE 861 LINE 46167 +:VDIVPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x5E; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vdivps_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# DIVSD 3-294 PAGE 864 LINE 46312 +define pcodeop vdivsd_avx ; +:VDIVSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vdivsd_avx( vexVVVV_XmmReg, XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# DIVSS 3-296 PAGE 866 LINE 46410 +define pcodeop vdivss_avx ; +:VDIVSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vdivss_avx( vexVVVV_XmmReg, XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# DPPD 3-298 PAGE 868 LINE 46509 +define pcodeop vdppd_avx ; +:VDPPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x41; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; imm8 +{ + local tmp:16 = vdppd_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# DPPS 3-300 PAGE 870 LINE 46612 +define pcodeop vdpps_avx ; +:VDPPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x40; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; imm8 +{ + local tmp:16 = vdpps_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# DPPS 3-300 PAGE 870 LINE 46616 +:VDPPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x40; YmmReg1 ... & YmmReg2_m256; imm8 +{ + YmmReg1 = vdpps_avx( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# EXTRACTPS 3-307 PAGE 877 LINE 46978 +define pcodeop vextractps_avx ; +:VEXTRACTPS rm32, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x17; XmmReg1 ... & rm32; imm8 +{ + rm32 = vextractps_avx( XmmReg1, imm8:1 ); +} + +# HADDPD 3-427 PAGE 997 LINE 52447 +define pcodeop vhaddpd_avx ; +:VHADDPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x7C; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vhaddpd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# HADDPD 3-427 PAGE 997 LINE 52450 +:VHADDPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x7C; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vhaddpd_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# HADDPS 3-430 PAGE 1000 LINE 52586 +define pcodeop vhaddps_avx ; +:VHADDPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x7C; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vhaddps_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# HADDPS 3-430 PAGE 1000 LINE 52589 +:VHADDPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x7C; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vhaddps_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# HSUBPD 3-434 PAGE 1004 LINE 52795 +define pcodeop vhsubpd_avx ; +:VHSUBPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x7D; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vhsubpd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# HSUBPD 3-434 PAGE 1004 LINE 52798 +:VHSUBPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x7D; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vhsubpd_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# HSUBPS 3-437 PAGE 1007 LINE 52933 +define pcodeop vhsubps_avx ; +:VHSUBPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x7D; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vhsubps_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# HSUBPS 3-437 PAGE 1007 LINE 52936 +:VHSUBPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x7D; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vhsubps_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# INSERTPS 3-454 PAGE 1024 LINE 53780 +define pcodeop vinsertps_avx ; +:VINSERTPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x21; (XmmReg1 & YmmReg1) ... & XmmReg2_m32; imm8 +{ + local tmp:16 = vinsertps_avx( vexVVVV_XmmReg, XmmReg2_m32, imm8:1 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# LDDQU 3-518 PAGE 1088 LINE 57123 +define pcodeop vlddqu_avx ; +:VLDDQU XmmReg1, m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0xF0; (XmmReg1 & YmmReg1) ... & m128 +{ + local tmp:16 = vlddqu_avx( m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# LDDQU 3-518 PAGE 1088 LINE 57126 +:VLDDQU YmmReg1, m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0xF0; YmmReg1 ... & m256 +{ + YmmReg1 = vlddqu_avx( m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# LDMXCSR 3-520 PAGE 1090 LINE 57208 +define pcodeop vldmxcsr_avx ; +:VLDMXCSR m32 is $(VEX_NONE) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0xAE; reg_opcode=2 ... & m32 +{ + vldmxcsr_avx( m32 ); + # TODO missing destination or side effects +} + +# MASKMOVDQU 4-8 PAGE 1128 LINE 59041 +define pcodeop vmaskmovdqu_avx ; +:VMASKMOVDQU XmmReg1, XmmReg2 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xF7; XmmReg1 & (mod=0x3 & XmmReg2) +{ + vmaskmovdqu_avx( XmmReg1, XmmReg2 ); + # TODO missing destination or side effects +} + +# MAXPD 4-12 PAGE 1132 LINE 59201 +define pcodeop vmaxpd_avx ; +:VMAXPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vmaxpd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MAXPD 4-12 PAGE 1132 LINE 59203 +:VMAXPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x5F; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vmaxpd_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# MAXPS 4-15 PAGE 1135 LINE 59350 +define pcodeop vmaxps_avx ; +:VMAXPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vmaxps_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MAXPS 4-15 PAGE 1135 LINE 59353 +:VMAXPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x5F; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vmaxps_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# MAXSD 4-18 PAGE 1138 LINE 59503 +define pcodeop vmaxsd_avx ; +:VMAXSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vmaxsd_avx( vexVVVV_XmmReg, XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MAXSS 4-20 PAGE 1140 LINE 59606 +define pcodeop vmaxss_avx ; +:VMAXSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vmaxss_avx( vexVVVV_XmmReg, XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MINPD 4-23 PAGE 1143 LINE 59765 +define pcodeop vminpd_avx ; +:VMINPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vminpd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MINPD 4-23 PAGE 1143 LINE 59768 +:VMINPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x5D; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vminpd_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# MINPS 4-26 PAGE 1146 LINE 59909 +define pcodeop vminps_avx ; +:VMINPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vminps_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MINPS 4-26 PAGE 1146 LINE 59912 +:VMINPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x5D; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vminps_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# MINSD 4-29 PAGE 1149 LINE 60061 +define pcodeop vminsd_avx ; +:VMINSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vminsd_avx( vexVVVV_XmmReg, XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MINSS 4-31 PAGE 1151 LINE 60164 +define pcodeop vminss_avx ; +:VMINSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vminss_avx( vexVVVV_XmmReg, XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MOVD/MOVQ 4-55 PAGE 1175 LINE 61358 +define pcodeop vmovd_avx ; +:VMOVD XmmReg1, rm32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x6E; (XmmReg1 & YmmReg1) ... & rm32 +{ + local tmp:16 = vmovd_avx( rm32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MOVD/MOVQ 4-55 PAGE 1175 LINE 61360 +define pcodeop vmovq_avx ; +@ifdef IA64 +:VMOVQ XmmReg1, rm64 is $(LONGMODE_ON) & $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x6E; (XmmReg1 & YmmReg1) ... & rm64 +{ + local tmp:16 = vmovq_avx( rm64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} +@endif + +# MOVD/MOVQ 4-55 PAGE 1175 LINE 61362 +:VMOVD rm32, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7E; XmmReg1 ... & rm32 +{ + rm32 = vmovd_avx( XmmReg1 ); +} + +# MOVD/MOVQ 4-55 PAGE 1175 LINE 61364 +@ifdef IA64 +:VMOVQ rm64, XmmReg1 is $(LONGMODE_ON) & $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x7E; XmmReg1 ... & rm64 +{ + rm64 = vmovq_avx( XmmReg1 ); +} +@endif + +# MOVDDUP 4-59 PAGE 1179 LINE 61521 +define pcodeop vmovddup_avx ; +:VMOVDDUP XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0x12; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vmovddup_avx( XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MOVDDUP 4-59 PAGE 1179 LINE 61523 +:VMOVDDUP YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0x12; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vmovddup_avx( YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61930 +define pcodeop vmovdqu_avx ; +:VMOVDQU XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x6F; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vmovdqu_avx( XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61932 +:VMOVDQU XmmReg2_m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x7F; XmmReg1 ... & XmmReg2_m128 +{ + XmmReg2_m128 = vmovdqu_avx( XmmReg1 ); + # TODO ZmmReg2 = zext(XmmReg2) +} + +# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61934 +:VMOVDQU YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x6F; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vmovdqu_avx( YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61936 +:VMOVDQU YmmReg2_m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x7F; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg2_m256 = vmovdqu_avx( YmmReg1 ); + # TODO ZmmReg2 = zext(YmmReg2) +} + +# MOVHLPS 4-76 PAGE 1196 LINE 62410 +define pcodeop vmovhlps_avx ; +:VMOVHLPS XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x12; (XmmReg1 & YmmReg1) & (mod=0x3 & XmmReg2) +{ + local tmp:16 = vmovhlps_avx( vexVVVV_XmmReg, XmmReg2 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MOVHPD 4-78 PAGE 1198 LINE 62483 +define pcodeop vmovhpd_avx ; +:VMOVHPD XmmReg1, vexVVVV_XmmReg, m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x16; (XmmReg1 & YmmReg1) ... & m64 +{ + local tmp:16 = vmovhpd_avx( vexVVVV_XmmReg, m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MOVHPD 4-78 PAGE 1198 LINE 62489 +:VMOVHPD m64, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x17; XmmReg1 ... & m64 +{ + m64 = vmovhpd_avx( XmmReg1 ); +} + +# MOVHPS 4-80 PAGE 1200 LINE 62570 +define pcodeop vmovhps_avx ; +:VMOVHPS XmmReg1, vexVVVV_XmmReg, m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x16; (XmmReg1 & YmmReg1) ... & m64 +{ + local tmp:16 = vmovhps_avx( vexVVVV_XmmReg, m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MOVHPS 4-80 PAGE 1200 LINE 62576 +:VMOVHPS m64, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x17; XmmReg1 ... & m64 +{ + m64 = vmovhps_avx( XmmReg1 ); +} + +# MOVLHPS 4-82 PAGE 1202 LINE 62658 +define pcodeop vmovlhps_avx ; +:VMOVLHPS XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x16; (XmmReg1 & YmmReg1) & (mod=0x3 & XmmReg2) +{ + local tmp:16 = vmovlhps_avx( vexVVVV_XmmReg, XmmReg2 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MOVLPD 4-84 PAGE 1204 LINE 62731 +define pcodeop vmovlpd_avx ; +:VMOVLPD XmmReg1, vexVVVV_XmmReg, m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x12; (XmmReg1 & YmmReg1) ... & m64 +{ + local tmp:16 = vmovlpd_avx( vexVVVV_XmmReg, m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MOVLPD 4-84 PAGE 1204 LINE 62737 +:VMOVLPD m64, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x13; XmmReg1 ... & m64 +{ + m64 = vmovlpd_avx( XmmReg1 ); +} + +# MOVLPS 4-86 PAGE 1206 LINE 62816 +define pcodeop vmovlps_avx ; +:VMOVLPS XmmReg1, vexVVVV_XmmReg, m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x12; (XmmReg1 & YmmReg1) ... & m64 +{ + local tmp:16 = vmovlps_avx( vexVVVV_XmmReg, m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MOVLPS 4-86 PAGE 1206 LINE 62822 +:VMOVLPS m64, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x13; XmmReg1 ... & m64 +{ + m64 = vmovlps_avx( XmmReg1 ); +} + +# MOVMSKPD 4-88 PAGE 1208 LINE 62906 +define pcodeop vmovmskpd_avx ; +:VMOVMSKPD Reg32, XmmReg2 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x50; Reg32 & (mod=0x3 & XmmReg2) +{ + Reg32 = vmovmskpd_avx( XmmReg2 ); + # TODO Reg64 = zext(Reg32) +} + +# MOVMSKPD 4-88 PAGE 1208 LINE 62910 +:VMOVMSKPD Reg32, YmmReg2 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x50; Reg32 & (mod=0x3 & YmmReg2) +{ + Reg32 = vmovmskpd_avx( YmmReg2 ); + # TODO Reg64 = zext(Reg32) +} + +# MOVMSKPS 4-90 PAGE 1210 LINE 62986 +define pcodeop vmovmskps_avx ; +:VMOVMSKPS Reg32, XmmReg2 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x50; Reg32 & (mod=0x3 & XmmReg2) +{ + Reg32 = vmovmskps_avx( XmmReg2 ); + # TODO Reg64 = zext(Reg32) +} + +# MOVMSKPS 4-90 PAGE 1210 LINE 62990 +:VMOVMSKPS Reg32, YmmReg2 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x50; Reg32 & (mod=0x3 & YmmReg2) +{ + Reg32 = vmovmskps_avx( YmmReg2 ); + # TODO Reg64 = zext(Reg32) +} + +# MOVNTDQA 4-92 PAGE 1212 LINE 63084 +define pcodeop vmovntdqa_avx ; +:VMOVNTDQA XmmReg1, m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x2A; (XmmReg1 & YmmReg1) ... & m128 +{ + local tmp:16 = vmovntdqa_avx( m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MOVNTDQ 4-94 PAGE 1214 LINE 63187 +define pcodeop vmovntdq_avx ; +:VMOVNTDQ m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xE7; XmmReg1 ... & m128 +{ + m128 = vmovntdq_avx( XmmReg1 ); +} + +# MOVNTDQ 4-94 PAGE 1214 LINE 63189 +:VMOVNTDQ m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xE7; YmmReg1 ... & m256 +{ + m256 = vmovntdq_avx( YmmReg1 ); +} + +# MOVNTPD 4-98 PAGE 1218 LINE 63357 +define pcodeop vmovntpd_avx ; +:VMOVNTPD m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x2B; XmmReg1 ... & m128 +{ + m128 = vmovntpd_avx( XmmReg1 ); +} + +# MOVNTPD 4-98 PAGE 1218 LINE 63359 +:VMOVNTPD m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x2B; YmmReg1 ... & m256 +{ + m256 = vmovntpd_avx( YmmReg1 ); +} + +# MOVNTPS 4-100 PAGE 1220 LINE 63441 +define pcodeop vmovntps_avx ; +:VMOVNTPS m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x2B; XmmReg1 ... & m128 +{ + m128 = vmovntps_avx( XmmReg1 ); +} + +# MOVNTPS 4-100 PAGE 1220 LINE 63443 +:VMOVNTPS m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x2B; YmmReg1 ... & m256 +{ + m256 = vmovntps_avx( YmmReg1 ); +} + +# MOVQ 4-103 PAGE 1223 LINE 63579 +:VMOVQ XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x7E; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vmovq_avx( XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MOVQ 4-103 PAGE 1223 LINE 63585 +:VMOVQ XmmReg2_m64, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xD6; XmmReg1 ... & XmmReg2_m64 +{ + XmmReg2_m64 = vmovq_avx( XmmReg1 ); + # TODO ZmmReg2 = zext(XmmReg2) +} + +# MOVSD 4-111 PAGE 1231 LINE 63970 +# INFO mnemonic VMOVSD was found in ../../../Processors/x86/data/languages/avx_manual.sinc + +# MOVSD 4-111 PAGE 1231 LINE 63972 +# INFO mnemonic VMOVSD was found in ../../../Processors/x86/data/languages/avx_manual.sinc + +# MOVSD 4-111 PAGE 1231 LINE 63974 +# INFO mnemonic VMOVSD was found in ../../../Processors/x86/data/languages/avx_manual.sinc + +# MOVSD 4-111 PAGE 1231 LINE 63976 +# INFO mnemonic VMOVSD was found in ../../../Processors/x86/data/languages/avx_manual.sinc + +# MOVSHDUP 4-114 PAGE 1234 LINE 64126 +define pcodeop vmovshdup_avx ; +:VMOVSHDUP XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x16; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vmovshdup_avx( XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MOVSHDUP 4-114 PAGE 1234 LINE 64128 +:VMOVSHDUP YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x16; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vmovshdup_avx( YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# MOVSLDUP 4-117 PAGE 1237 LINE 64280 +define pcodeop vmovsldup_avx ; +:VMOVSLDUP XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x12; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vmovsldup_avx( XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MOVSLDUP 4-117 PAGE 1237 LINE 64282 +:VMOVSLDUP YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x12; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vmovsldup_avx( YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# MOVSS 4-120 PAGE 1240 LINE 64433 +define pcodeop vmovss_avx ; +:VMOVSS XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x10; (XmmReg1 & YmmReg1) & (mod=0x3 & XmmReg2) +{ + local tmp:16 = vmovss_avx( vexVVVV_XmmReg, XmmReg2 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MOVSS 4-120 PAGE 1240 LINE 64435 +:VMOVSS XmmReg1, m32 is $(VEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x10; (XmmReg1 & YmmReg1) ... & m32 +{ + local tmp:16 = vmovss_avx( m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MOVSS 4-120 PAGE 1240 LINE 64439 +:VMOVSS XmmReg2, vexVVVV_XmmReg, XmmReg1 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x11; XmmReg1 & (mod=0x3 & (XmmReg2 & YmmReg2)) +{ + local tmp:16 = vmovss_avx( vexVVVV_XmmReg, XmmReg1 ); + YmmReg2 = zext(tmp); + # TODO ZmmReg2 = zext(XmmReg2) +} + +# MOVSS 4-120 PAGE 1240 LINE 64441 +:VMOVSS m32, XmmReg1 is $(VEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x11; XmmReg1 ... & m32 +{ + m32 = vmovss_avx( XmmReg1 ); +} + +# MOVUPD 4-126 PAGE 1246 LINE 64687 +define pcodeop vmovupd_avx ; +:VMOVUPD XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x10; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vmovupd_avx( XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MOVUPD 4-126 PAGE 1246 LINE 64689 +:VMOVUPD XmmReg2_m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x11; XmmReg1 ... & XmmReg2_m128 +{ + XmmReg2_m128 = vmovupd_avx( XmmReg1 ); + # TODO ZmmReg2 = zext(XmmReg2) +} + +# MOVUPD 4-126 PAGE 1246 LINE 64691 +:VMOVUPD YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x10; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vmovupd_avx( YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# MOVUPD 4-126 PAGE 1246 LINE 64693 +:VMOVUPD YmmReg2_m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x11; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg2_m256 = vmovupd_avx( YmmReg1 ); + # TODO ZmmReg2 = zext(YmmReg2) +} + +# MOVUPS 4-130 PAGE 1250 LINE 64872 +# INFO mnemonic VMOVUPS was found in ../../../Processors/x86/data/languages/avx_manual.sinc + +# MOVUPS 4-130 PAGE 1250 LINE 64874 +# INFO mnemonic VMOVUPS was found in ../../../Processors/x86/data/languages/avx_manual.sinc + +# MOVUPS 4-130 PAGE 1250 LINE 64876 +# INFO mnemonic VMOVUPS was found in ../../../Processors/x86/data/languages/avx_manual.sinc + +# MOVUPS 4-130 PAGE 1250 LINE 64878 +# INFO mnemonic VMOVUPS was found in ../../../Processors/x86/data/languages/avx_manual.sinc + +# MPSADBW 4-136 PAGE 1256 LINE 65135 +define pcodeop vmpsadbw_avx ; +:VMPSADBW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x42; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; imm8 +{ + local tmp:16 = vmpsadbw_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MULPD 4-146 PAGE 1266 LINE 65682 +define pcodeop vmulpd_avx ; +:VMULPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vmulpd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MULPD 4-146 PAGE 1266 LINE 65684 +:VMULPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x59; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vmulpd_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# MULPS 4-149 PAGE 1269 LINE 65813 +define pcodeop vmulps_avx ; +:VMULPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vmulps_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MULPS 4-149 PAGE 1269 LINE 65815 +:VMULPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x59; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vmulps_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# MULSD 4-152 PAGE 1272 LINE 65956 +define pcodeop vmulsd_avx ; +:VMULSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vmulsd_avx( vexVVVV_XmmReg, XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MULSS 4-154 PAGE 1274 LINE 66052 +define pcodeop vmulss_avx ; +:VMULSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vmulss_avx( vexVVVV_XmmReg, XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# ORPD 4-168 PAGE 1288 LINE 66720 +define pcodeop vorpd_avx ; +:VORPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x56; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vorpd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# ORPD 4-168 PAGE 1288 LINE 66722 +:VORPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x56; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vorpd_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# ORPS 4-171 PAGE 1291 LINE 66846 +define pcodeop vorps_avx ; +:VORPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x56; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vorps_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# ORPS 4-171 PAGE 1291 LINE 66848 +:VORPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x56; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vorps_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67302 +define pcodeop vpabsb_avx ; +:VPABSB XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x1C; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpabsb_avx( XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67305 +define pcodeop vpabsw_avx ; +:VPABSW XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x1D; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpabsw_avx( XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67308 +define pcodeop vpabsd_avx ; +:VPABSD XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x1E; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpabsd_avx( XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67629 +define pcodeop vpacksswb_avx ; +:VPACKSSWB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x63; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpacksswb_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67633 +define pcodeop vpackssdw_avx ; +:VPACKSSDW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x6B; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpackssdw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PACKUSDW 4-194 PAGE 1314 LINE 68086 +define pcodeop vpackusdw_avx ; +:VPACKUSDW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_XmmReg; byte=0x2B; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpackusdw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PACKUSWB 4-199 PAGE 1319 LINE 68366 +define pcodeop vpackuswb_avx ; +:VPACKUSWB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x67; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpackuswb_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68658 +define pcodeop vpaddb_avx ; +:VPADDB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFC; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpaddb_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68660 +define pcodeop vpaddw_avx ; +:VPADDW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFD; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpaddw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68662 +define pcodeop vpaddd_avx ; +:VPADDD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFE; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpaddd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68664 +define pcodeop vpaddq_avx ; +:VPADDQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD4; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpaddq_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PADDSB/PADDSW 4-211 PAGE 1331 LINE 69040 +define pcodeop vpaddsb_avx ; +:VPADDSB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xEC; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpaddsb_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PADDSB/PADDSW 4-211 PAGE 1331 LINE 69042 +define pcodeop vpaddsw_avx ; +:VPADDSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xED; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpaddsw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69257 +define pcodeop vpaddusb_avx ; +:VPADDUSB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xDC; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpaddusb_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69260 +define pcodeop vpaddusw_avx ; +:VPADDUSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xDD; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpaddusw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PALIGNR 4-219 PAGE 1339 LINE 69485 +define pcodeop vpalignr_avx ; +:VPALIGNR XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0F; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; imm8 +{ + local tmp:16 = vpalignr_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PAND 4-223 PAGE 1343 LINE 69678 +define pcodeop vpand_avx ; +:VPAND XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xDB; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpand_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PANDN 4-226 PAGE 1346 LINE 69854 +define pcodeop vpandn_avx ; +:VPANDN XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xDF; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpandn_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PAVGB/PAVGW 4-230 PAGE 1350 LINE 70085 +define pcodeop vpavgb_avx ; +:VPAVGB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE0; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpavgb_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PAVGB/PAVGW 4-230 PAGE 1350 LINE 70088 +define pcodeop vpavgw_avx ; +:VPAVGW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE3; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpavgw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PBLENDVB 4-234 PAGE 1354 LINE 70296 +define pcodeop vpblendvb_avx ; +:VPBLENDVB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, Xmm_imm8_7_4 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x4C; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; Xmm_imm8_7_4 +{ + local tmp:16 = vpblendvb_avx( vexVVVV_XmmReg, XmmReg2_m128, Xmm_imm8_7_4 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PBLENDW 4-238 PAGE 1358 LINE 70522 +define pcodeop vpblendw_avx ; +:VPBLENDW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0E; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; imm8 +{ + local tmp:16 = vpblendw_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + + + + +# PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70821 +define pcodeop vpcmpeqb_avx ; +:VPCMPEQB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x74; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpcmpeqb_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70824 +define pcodeop vpcmpeqw_avx ; +:VPCMPEQW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x75; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpcmpeqw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70827 +define pcodeop vpcmpeqd_avx ; +:VPCMPEQD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x76; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpcmpeqd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PCMPESTRI 4-253 PAGE 1373 LINE 71311 +define pcodeop vpcmpestri_avx ; +:VPCMPESTRI XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A); byte=0x61; XmmReg1 ... & XmmReg2_m128; imm8 +{ + vpcmpestri_avx( XmmReg1, XmmReg2_m128, imm8:1 ); + # TODO missing destination or side effects +} + +# PCMPESTRM 4-255 PAGE 1375 LINE 71395 +define pcodeop vpcmpestrm_avx ; +:VPCMPESTRM XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A); byte=0x60; XmmReg1 ... & XmmReg2_m128; imm8 +{ + vpcmpestrm_avx( XmmReg1, XmmReg2_m128, imm8:1 ); + # TODO missing destination or side effects +} + +# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71499 +define pcodeop vpcmpgtb_avx ; +:VPCMPGTB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x64; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpcmpgtb_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71502 +define pcodeop vpcmpgtw_avx ; +:VPCMPGTW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x65; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpcmpgtw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71505 +define pcodeop vpcmpgtd_avx ; +:VPCMPGTD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x66; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpcmpgtd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PCMPGTQ 4-263 PAGE 1383 LINE 71833 +define pcodeop vpcmpgtq_avx ; +:VPCMPGTQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x37; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpcmpgtq_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PCMPISTRI 4-266 PAGE 1386 LINE 71966 +define pcodeop vpcmpistri_avx ; +:VPCMPISTRI XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x63; XmmReg1 ... & XmmReg2_m128; imm8 +{ + vpcmpistri_avx( XmmReg1, XmmReg2_m128, imm8:1 ); + # TODO missing destination or side effects +} + +# PCMPISTRM 4-268 PAGE 1388 LINE 72052 +define pcodeop vpcmpistrm_avx ; +:VPCMPISTRM XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x62; XmmReg1 ... & XmmReg2_m128; imm8 +{ + vpcmpistrm_avx( XmmReg1, XmmReg2_m128, imm8:1 ); + # TODO missing destination or side effects +} + +# PEXTRB/PEXTRD/PEXTRQ 4-274 PAGE 1394 LINE 72322 +define pcodeop vpextrb_avx ; +:VPEXTRB Reg32_m8, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x14; XmmReg1 ... & Reg32_m8; imm8 +{ + Reg32_m8 = vpextrb_avx( XmmReg1, imm8:1 ); + # TODO Reg64 = zext(Reg32) +} + +# PEXTRB/PEXTRD/PEXTRQ 4-274 PAGE 1394 LINE 72326 +define pcodeop vpextrd_avx ; +:VPEXTRD rm32, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x16; XmmReg1 ... & rm32; imm8 +{ + rm32 = vpextrd_avx( XmmReg1, imm8:1 ); +} + +# PEXTRB/PEXTRD/PEXTRQ 4-274 PAGE 1394 LINE 72330 +define pcodeop vpextrq_avx ; +@ifdef IA64 +:VPEXTRQ rm64, XmmReg1, imm8 is $(LONGMODE_ON) & $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1); byte=0x16; XmmReg1 ... & rm64; imm8 +{ + rm64 = vpextrq_avx( XmmReg1, imm8:1 ); +} +@endif + +# PEXTRW 4-277 PAGE 1397 LINE 72478 +define pcodeop vpextrw_avx ; +:VPEXTRW Reg32, XmmReg2, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0xC5; Reg32 & (mod=0x3 & XmmReg2); imm8 +{ + Reg32 = vpextrw_avx( XmmReg2, imm8:1 ); + # TODO Reg64 = zext(Reg32) +} + +# PEXTRW 4-277 PAGE 1397 LINE 72483 +:VPEXTRW Reg32_m16, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x15; XmmReg1 ... & Reg32_m16; imm8 +{ + Reg32_m16 = vpextrw_avx( XmmReg1, imm8:1 ); + # TODO Reg64 = zext(Reg32) +} + +# PHADDW/PHADDD 4-280 PAGE 1400 LINE 72627 +define pcodeop vphaddw_avx ; +:VPHADDW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x01; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vphaddw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PHADDW/PHADDD 4-280 PAGE 1400 LINE 72630 +define pcodeop vphaddd_avx ; +:VPHADDD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x02; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vphaddd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PHADDSW 4-284 PAGE 1404 LINE 72821 +define pcodeop vphaddsw_avx ; +:VPHADDSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x03; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vphaddsw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PHMINPOSUW 4-286 PAGE 1406 LINE 72939 +define pcodeop vphminposuw_avx ; +:VPHMINPOSUW XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x41; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vphminposuw_avx( XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PHSUBW/PHSUBD 4-288 PAGE 1408 LINE 73032 +define pcodeop vphsubw_avx ; +:VPHSUBW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x05; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vphsubw_avx( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PHSUBW/PHSUBD 4-288 PAGE 1408 LINE 73035 +define pcodeop vphsubd_avx ; +:VPHSUBD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x06; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vphsubd_avx( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PHSUBSW 4-291 PAGE 1411 LINE 73197 +define pcodeop vphsubsw_avx ; +:VPHSUBSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x07; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vphsubsw_avx( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73321 +define pcodeop vpinsrb_avx ; +:VPINSRB XmmReg1, vexVVVV_XmmReg, Reg32_m8, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x20; (XmmReg1 & YmmReg1) ... & Reg32_m8; imm8 +{ + local tmp:16 = vpinsrb_avx( vexVVVV_XmmReg, Reg32_m8, imm8:1 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73324 +define pcodeop vpinsrd_avx ; +:VPINSRD XmmReg1, vexVVVV_XmmReg, rm32, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x22; (XmmReg1 & YmmReg1) ... & rm32; imm8 +{ + local tmp:16 = vpinsrd_avx( vexVVVV_XmmReg, rm32, imm8:1 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73327 +define pcodeop vpinsrq_avx ; +@ifdef IA64 +:VPINSRQ XmmReg1, vexVVVV_XmmReg, rm64, imm8 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x22; (XmmReg1 & YmmReg1) ... & rm64; imm8 +{ + local tmp:16 = vpinsrq_avx( vexVVVV_XmmReg, rm64, imm8:1 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} +@endif + +# PINSRW 4-296 PAGE 1416 LINE 73446 +define pcodeop vpinsrw_avx ; +:VPINSRW XmmReg1, vexVVVV_XmmReg, Reg32_m16, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xC4; (XmmReg1 & YmmReg1) ... & Reg32_m16; imm8 +{ + local tmp:16 = vpinsrw_avx( vexVVVV_XmmReg, Reg32_m16, imm8:1 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMADDUBSW 4-298 PAGE 1418 LINE 73552 +define pcodeop vpmaddubsw_avx ; +:VPMADDUBSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x04; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpmaddubsw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMADDWD 4-301 PAGE 1421 LINE 73700 +define pcodeop vpmaddwd_avx ; +:VPMADDWD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF5; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpmaddwd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73882 +define pcodeop vpmaxsb_avx ; +:VPMAXSB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x3C; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpmaxsb_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73885 +define pcodeop vpmaxsw_avx ; +:VPMAXSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xEE; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpmaxsw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73888 +define pcodeop vpmaxsd_avx ; +:VPMAXSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x3D; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpmaxsd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74283 +define pcodeop vpmaxub_avx ; +:VPMAXUB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0xDE; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpmaxub_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74286 +define pcodeop vpmaxuw_avx ; +:VPMAXUW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_XmmReg; byte=0x3E; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpmaxuw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74534 +define pcodeop vpmaxud_avx ; +:VPMAXUD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x3F; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpmaxud_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMINSB/PMINSW 4-320 PAGE 1440 LINE 74736 +define pcodeop vpminsb_avx ; +:VPMINSB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_XmmReg; byte=0x38; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpminsb_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMINSB/PMINSW 4-320 PAGE 1440 LINE 74739 +define pcodeop vpminsw_avx ; +:VPMINSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0xEA; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpminsw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMINSD/PMINSQ 4-325 PAGE 1445 LINE 74989 +define pcodeop vpminsd_avx ; +:VPMINSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x39; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpminsd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMINUB/PMINUW 4-329 PAGE 1449 LINE 75195 +define pcodeop vpminub_avx ; +:VPMINUB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0xDA; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpminub_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMINUB/PMINUW 4-329 PAGE 1449 LINE 75198 +define pcodeop vpminuw_avx ; +:VPMINUW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_XmmReg; byte=0x3A; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpminuw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75445 +define pcodeop vpminud_avx ; +:VPMINUD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x3B; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpminud_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMOVSX 4-340 PAGE 1460 LINE 75770 +define pcodeop vpmovsxbw_avx ; +:VPMOVSXBW XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x20; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vpmovsxbw_avx( XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMOVSX 4-340 PAGE 1460 LINE 75772 +define pcodeop vpmovsxbd_avx ; +:VPMOVSXBD XmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x21; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vpmovsxbd_avx( XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMOVSX 4-340 PAGE 1460 LINE 75774 +define pcodeop vpmovsxbq_avx ; +:VPMOVSXBQ XmmReg1, XmmReg2_m16 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x22; (XmmReg1 & YmmReg1) ... & XmmReg2_m16 +{ + local tmp:16 = vpmovsxbq_avx( XmmReg2_m16 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMOVSX 4-340 PAGE 1460 LINE 75776 +define pcodeop vpmovsxwd_avx ; +:VPMOVSXWD XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x23; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vpmovsxwd_avx( XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMOVSX 4-340 PAGE 1460 LINE 75778 +define pcodeop vpmovsxwq_avx ; +:VPMOVSXWQ XmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x24; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vpmovsxwq_avx( XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMOVSX 4-340 PAGE 1460 LINE 75780 +define pcodeop vpmovsxdq_avx ; +:VPMOVSXDQ XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x25; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vpmovsxdq_avx( XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMOVZX 4-350 PAGE 1470 LINE 76285 +define pcodeop vpmovzxbw_avx ; +:VPMOVZXBW XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x30; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vpmovzxbw_avx( XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMOVZX 4-350 PAGE 1470 LINE 76288 +define pcodeop vpmovzxbd_avx ; +:VPMOVZXBD XmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x31; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vpmovzxbd_avx( XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMOVZX 4-350 PAGE 1470 LINE 76291 +define pcodeop vpmovzxbq_avx ; +:VPMOVZXBQ XmmReg1, XmmReg2_m16 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x32; (XmmReg1 & YmmReg1) ... & XmmReg2_m16 +{ + local tmp:16 = vpmovzxbq_avx( XmmReg2_m16 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMOVZX 4-350 PAGE 1470 LINE 76294 +define pcodeop vpmovzxwd_avx ; +:VPMOVZXWD XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x33; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vpmovzxwd_avx( XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMOVZX 4-350 PAGE 1470 LINE 76297 +define pcodeop vpmovzxwq_avx ; +:VPMOVZXWQ XmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x34; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vpmovzxwq_avx( XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMOVZX 4-350 PAGE 1470 LINE 76301 +define pcodeop vpmovzxdq_avx ; +:VPMOVZXDQ XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x35; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vpmovzxdq_avx( XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMULDQ 4-359 PAGE 1479 LINE 76788 +define pcodeop vpmuldq_avx ; +:VPMULDQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x28; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpmuldq_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMULHRSW 4-362 PAGE 1482 LINE 76928 +define pcodeop vpmulhrsw_avx ; +:VPMULHRSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0B; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpmulhrsw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMULHUW 4-366 PAGE 1486 LINE 77141 +define pcodeop vpmulhuw_avx ; +:VPMULHUW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE4; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpmulhuw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMULHW 4-370 PAGE 1490 LINE 77370 +define pcodeop vpmulhw_avx ; +:VPMULHW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE5; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpmulhw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77576 +define pcodeop vpmulld_avx ; +:VPMULLD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x40; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpmulld_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMULLW 4-378 PAGE 1498 LINE 77775 +define pcodeop vpmullw_avx ; +:VPMULLW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD5; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpmullw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PMULUDQ 4-382 PAGE 1502 LINE 77969 +define pcodeop vpmuludq_avx ; +:VPMULUDQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF4; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpmuludq_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# POR 4-399 PAGE 1519 LINE 78850 +define pcodeop vpor_avx ; +:VPOR XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xEB; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpor_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PSADBW 4-408 PAGE 1528 LINE 79240 +define pcodeop vpsadbw_avx ; +:VPSADBW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF6; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpsadbw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PSHUFB 4-412 PAGE 1532 LINE 79460 +define pcodeop vpshufb_avx ; +:VPSHUFB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x00; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpshufb_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PSHUFD 4-416 PAGE 1536 LINE 79651 +define pcodeop vpshufd_avx ; +:VPSHUFD XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x70; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; imm8 +{ + local tmp:16 = vpshufd_avx( XmmReg2_m128, imm8:1 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PSHUFHW 4-420 PAGE 1540 LINE 79857 +define pcodeop vpshufhw_avx ; +:VPSHUFHW XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x70; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; imm8 +{ + local tmp:16 = vpshufhw_avx( XmmReg2_m128, imm8:1 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PSHUFLW 4-423 PAGE 1543 LINE 80032 +define pcodeop vpshuflw_avx ; +:VPSHUFLW XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0x70; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; imm8 +{ + local tmp:16 = vpshuflw_avx( XmmReg2_m128, imm8:1 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PSIGNB/PSIGNW/PSIGND 4-427 PAGE 1547 LINE 80269 +define pcodeop vpsignb_avx ; +:VPSIGNB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x08; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpsignb_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PSIGNB/PSIGNW/PSIGND 4-427 PAGE 1547 LINE 80272 +define pcodeop vpsignw_avx ; +:VPSIGNW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x09; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpsignw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PSIGNB/PSIGNW/PSIGND 4-427 PAGE 1547 LINE 80275 +define pcodeop vpsignd_avx ; +:VPSIGND XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0A; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpsignd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PSLLDQ 4-431 PAGE 1551 LINE 80485 +define pcodeop vpslldq_avx ; +:VPSLLDQ vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x73; reg_opcode=7 & (mod=0x3 & XmmReg2); imm8 +{ + vexVVVV_XmmReg = vpslldq_avx( XmmReg2, imm8:1 ); +} + +# PSLLW/PSLLD/PSLLQ 4-433 PAGE 1553 LINE 80620 +define pcodeop vpsllw_avx ; +:VPSLLW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF1; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpsllw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PSLLW/PSLLD/PSLLQ 4-433 PAGE 1553 LINE 80623 +:VPSLLW vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x71; reg_opcode=6 & (mod=0x3 & XmmReg2); imm8 +{ + vexVVVV_XmmReg = vpsllw_avx( XmmReg2, imm8:1 ); +} + +# PSLLW/PSLLD/PSLLQ 4-433 PAGE 1553 LINE 80626 +define pcodeop vpslld_avx ; +:VPSLLD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF2; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpslld_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PSLLW/PSLLD/PSLLQ 4-433 PAGE 1553 LINE 80629 +:VPSLLD vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x72; reg_opcode=6 & (mod=0x3 & XmmReg2); imm8 +{ + vexVVVV_XmmReg = vpslld_avx( XmmReg2, imm8:1 ); +} + +# PSLLW/PSLLD/PSLLQ 4-433 PAGE 1553 LINE 80632 +define pcodeop vpsllq_avx ; +:VPSLLQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF3; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpsllq_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PSLLW/PSLLD/PSLLQ 4-433 PAGE 1553 LINE 80635 +:VPSLLQ vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x73; reg_opcode=6 & (mod=0x3 & XmmReg2); imm8 +{ + vexVVVV_XmmReg = vpsllq_avx( XmmReg2, imm8:1 ); +} + +# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81305 +define pcodeop vpsraw_avx ; +:VPSRAW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE1; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpsraw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81308 +:VPSRAW vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x71; reg_opcode=4 & (mod=0x3 & XmmReg2); imm8 +{ + vexVVVV_XmmReg = vpsraw_avx( XmmReg2, imm8:1 ); +} + +# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81311 +define pcodeop vpsrad_avx ; +:VPSRAD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE2; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpsrad_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81314 +:VPSRAD vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x72; reg_opcode=4 & (mod=0x3 & XmmReg2); imm8 +{ + vexVVVV_XmmReg = vpsrad_avx( XmmReg2, imm8:1 ); +} + +# PSRLDQ 4-455 PAGE 1575 LINE 81873 +define pcodeop vpsrldq_avx ; +:VPSRLDQ vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x73; reg_opcode=3 & (mod=0x3 & XmmReg2); imm8 +{ + vexVVVV_XmmReg = vpsrldq_avx( XmmReg2, imm8:1 ); +} + +# PSRLW/PSRLD/PSRLQ 4-457 PAGE 1577 LINE 82012 +define pcodeop vpsrlw_avx ; +:VPSRLW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD1; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpsrlw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PSRLW/PSRLD/PSRLQ 4-457 PAGE 1577 LINE 82015 +:VPSRLW vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x71; reg_opcode=2 & (mod=0x3 & XmmReg2); imm8 +{ + vexVVVV_XmmReg = vpsrlw_avx( XmmReg2, imm8:1 ); +} + +# PSRLW/PSRLD/PSRLQ 4-457 PAGE 1577 LINE 82018 +define pcodeop vpsrld_avx ; +:VPSRLD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD2; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpsrld_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PSRLW/PSRLD/PSRLQ 4-457 PAGE 1577 LINE 82021 +:VPSRLD vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x72; reg_opcode=2 & (mod=0x3 & XmmReg2); imm8 +{ + vexVVVV_XmmReg = vpsrld_avx( XmmReg2, imm8:1 ); +} + +# PSRLW/PSRLD/PSRLQ 4-457 PAGE 1577 LINE 82024 +define pcodeop vpsrlq_avx ; +:VPSRLQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD3; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpsrlq_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PSRLW/PSRLD/PSRLQ 4-457 PAGE 1577 LINE 82027 +:VPSRLQ vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x73; reg_opcode=2 & (mod=0x3 & XmmReg2); imm8 +{ + vexVVVV_XmmReg = vpsrlq_avx( XmmReg2, imm8:1 ); +} + +# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82689 +define pcodeop vpsubb_avx ; +:VPSUBB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF8; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpsubb_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82691 +define pcodeop vpsubw_avx ; +:VPSUBW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF9; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpsubw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82694 +define pcodeop vpsubd_avx ; +:VPSUBD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFA; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpsubd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PSUBQ 4-476 PAGE 1596 LINE 83101 +define pcodeop vpsubq_avx ; +:VPSUBQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFB; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpsubq_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83258 +define pcodeop vpsubsb_avx ; +:VPSUBSB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE8; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpsubsb_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83261 +define pcodeop vpsubsw_avx ; +:VPSUBSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE9; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpsubsw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83498 +define pcodeop vpsubusb_avx ; +:VPSUBUSB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD8; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpsubusb_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83501 +define pcodeop vpsubusw_avx ; +:VPSUBUSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD9; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpsubusw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PTEST 4-487 PAGE 1607 LINE 83728 +define pcodeop vptest_avx ; +:VPTEST XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x17; XmmReg1 ... & XmmReg2_m128 +{ + vptest_avx( XmmReg1, XmmReg2_m128 ); + # TODO set flags AF, CF, PF, SF, ZF +} + +# PTEST 4-487 PAGE 1607 LINE 83730 +:VPTEST YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x17; YmmReg1 ... & YmmReg2_m256 +{ + vptest_avx( YmmReg1, YmmReg2_m256 ); + # TODO set flags AF, CF, PF, SF, ZF +} + +# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83929 +define pcodeop vpunpckhbw_avx ; +:VPUNPCKHBW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x68; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpunpckhbw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83932 +define pcodeop vpunpckhwd_avx ; +:VPUNPCKHWD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x69; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpunpckhwd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83935 +define pcodeop vpunpckhdq_avx ; +:VPUNPCKHDQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x6A; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpunpckhdq_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83938 +define pcodeop vpunpckhqdq_avx ; +:VPUNPCKHQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x6D; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpunpckhqdq_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84529 +define pcodeop vpunpcklbw_avx ; +:VPUNPCKLBW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x60; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpunpcklbw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84532 +define pcodeop vpunpcklwd_avx ; +:VPUNPCKLWD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x61; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpunpcklwd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84535 +define pcodeop vpunpckldq_avx ; +:VPUNPCKLDQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x62; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpunpckldq_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84538 +define pcodeop vpunpcklqdq_avx ; +:VPUNPCKLQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x6C; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpunpcklqdq_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# PXOR 4-518 PAGE 1638 LINE 85495 +define pcodeop vpxor_avx ; +:VPXOR XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xEF; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpxor_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# RCPPS 4-526 PAGE 1646 LINE 85950 +define pcodeop vrcpps_avx ; +:VRCPPS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x53; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vrcpps_avx( XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# RCPPS 4-526 PAGE 1646 LINE 85953 +:VRCPPS YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x53; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vrcpps_avx( YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# RCPSS 4-528 PAGE 1648 LINE 86052 +define pcodeop vrcpss_avx ; +:VRCPSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x53; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vrcpss_avx( vexVVVV_XmmReg, XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# ROUNDPD 4-564 PAGE 1684 LINE 87791 +define pcodeop vroundpd_avx ; +:VROUNDPD XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x09; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; imm8 +{ + local tmp:16 = vroundpd_avx( XmmReg2_m128, imm8:1 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# ROUNDPD 4-564 PAGE 1684 LINE 87795 +:VROUNDPD YmmReg1, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x09; YmmReg1 ... & YmmReg2_m256; imm8 +{ + YmmReg1 = vroundpd_avx( YmmReg2_m256, imm8:1 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# ROUNDPS 4-567 PAGE 1687 LINE 87934 +define pcodeop vroundps_avx ; +:VROUNDPS XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x08; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; imm8 +{ + local tmp:16 = vroundps_avx( XmmReg2_m128, imm8:1 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# ROUNDPS 4-567 PAGE 1687 LINE 87938 +:VROUNDPS YmmReg1, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x08; YmmReg1 ... & YmmReg2_m256; imm8 +{ + YmmReg1 = vroundps_avx( YmmReg2_m256, imm8:1 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# ROUNDSD 4-570 PAGE 1690 LINE 88058 +define pcodeop vroundsd_avx ; +:VROUNDSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64, imm8 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0B; (XmmReg1 & YmmReg1) ... & XmmReg2_m64; imm8 +{ + local tmp:16 = vroundsd_avx( vexVVVV_XmmReg, XmmReg2_m64, imm8:1 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# ROUNDSS 4-572 PAGE 1692 LINE 88145 +define pcodeop vroundss_avx ; +:VROUNDSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32, imm8 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0A; (XmmReg1 & YmmReg1) ... & XmmReg2_m32; imm8 +{ + local tmp:16 = vroundss_avx( vexVVVV_XmmReg, XmmReg2_m32, imm8:1 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# RSQRTPS 4-576 PAGE 1696 LINE 88301 +define pcodeop vrsqrtps_avx ; +:VRSQRTPS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x52; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vrsqrtps_avx( XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# RSQRTPS 4-576 PAGE 1696 LINE 88304 +:VRSQRTPS YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x52; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vrsqrtps_avx( YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# RSQRTSS 4-578 PAGE 1698 LINE 88399 +define pcodeop vrsqrtss_avx ; +:VRSQRTSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x52; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vrsqrtss_avx( vexVVVV_XmmReg, XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# SHUFPD 4-617 PAGE 1737 LINE 90223 +define pcodeop vshufpd_avx ; +:VSHUFPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xC6; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; imm8 +{ + local tmp:16 = vshufpd_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# SHUFPD 4-617 PAGE 1737 LINE 90227 +:VSHUFPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xC6; YmmReg1 ... & YmmReg2_m256; imm8 +{ + YmmReg1 = vshufpd_avx( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# SHUFPS 4-622 PAGE 1742 LINE 90483 +define pcodeop vshufps_avx ; +:VSHUFPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xC6; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; imm8 +{ + local tmp:16 = vshufps_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# SHUFPS 4-622 PAGE 1742 LINE 90486 +:VSHUFPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xC6; YmmReg1 ... & YmmReg2_m256; imm8 +{ + YmmReg1 = vshufps_avx( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# SQRTPD 4-632 PAGE 1752 LINE 91001 +define pcodeop vsqrtpd_avx ; +:VSQRTPD XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x51; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vsqrtpd_avx( XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# SQRTPD 4-632 PAGE 1752 LINE 91004 +:VSQRTPD YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x51; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vsqrtpd_avx( YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# SQRTPS 4-635 PAGE 1755 LINE 91133 +define pcodeop vsqrtps_avx ; +:VSQRTPS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x51; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vsqrtps_avx( XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# SQRTPS 4-635 PAGE 1755 LINE 91136 +:VSQRTPS YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x51; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vsqrtps_avx( YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# SQRTSD 4-638 PAGE 1758 LINE 91272 +define pcodeop vsqrtsd_avx ; +:VSQRTSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vsqrtsd_avx( vexVVVV_XmmReg, XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# SQRTSS 4-640 PAGE 1760 LINE 91367 +define pcodeop vsqrtss_avx ; +:VSQRTSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vsqrtss_avx( vexVVVV_XmmReg, XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# STMXCSR 4-647 PAGE 1767 LINE 91697 +define pcodeop vstmxcsr_avx ; +:VSTMXCSR m32 is $(VEX_NONE) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0xAE; reg_opcode=3 ... & m32 +{ + m32 = vstmxcsr_avx( ); +} + +# SUBPD 4-656 PAGE 1776 LINE 92116 +define pcodeop vsubpd_avx ; +:VSUBPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vsubpd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# SUBPD 4-656 PAGE 1776 LINE 92118 +:VSUBPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x5C; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vsubpd_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# SUBPS 4-659 PAGE 1779 LINE 92265 +define pcodeop vsubps_avx ; +:VSUBPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vsubps_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# SUBPS 4-659 PAGE 1779 LINE 92267 +:VSUBPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x5C; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vsubps_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# SUBSD 4-662 PAGE 1782 LINE 92419 +define pcodeop vsubsd_avx ; +:VSUBSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vsubsd_avx( vexVVVV_XmmReg, XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# SUBSS 4-664 PAGE 1784 LINE 92512 +define pcodeop vsubss_avx ; +:VSUBSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vsubss_avx( vexVVVV_XmmReg, XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# UCOMISD 4-683 PAGE 1803 LINE 93421 +define pcodeop vucomisd_avx ; +:VUCOMISD XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x2E; XmmReg1 ... & XmmReg2_m64 +{ + vucomisd_avx( XmmReg1, XmmReg2_m64 ); + # TODO set flags AF, CF, OF, PF, SF, ZF +} + +# UCOMISS 4-685 PAGE 1805 LINE 93504 +define pcodeop vucomiss_avx ; +:VUCOMISS XmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x2E; XmmReg1 ... & XmmReg2_m32 +{ + vucomiss_avx( XmmReg1, XmmReg2_m32 ); + # TODO set flags AF, CF, OF, PF, SF, ZF +} + +# UNPCKHPD 4-688 PAGE 1808 LINE 93623 +define pcodeop vunpckhpd_avx ; +:VUNPCKHPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x15; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vunpckhpd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# UNPCKHPD 4-688 PAGE 1808 LINE 93626 +:VUNPCKHPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x15; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vunpckhpd_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# UNPCKHPS 4-692 PAGE 1812 LINE 93807 +define pcodeop vunpckhps_avx ; +:VUNPCKHPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x15; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vunpckhps_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# UNPCKHPS 4-692 PAGE 1812 LINE 93810 +:VUNPCKHPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x15; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vunpckhps_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# UNPCKLPD 4-696 PAGE 1816 LINE 94039 +define pcodeop vunpcklpd_avx ; +:VUNPCKLPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x14; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vunpcklpd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# UNPCKLPD 4-696 PAGE 1816 LINE 94042 +:VUNPCKLPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x14; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vunpcklpd_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# UNPCKLPS 4-700 PAGE 1820 LINE 94225 +define pcodeop vunpcklps_avx ; +:VUNPCKLPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x14; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vunpcklps_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# UNPCKLPS 4-700 PAGE 1820 LINE 94228 +:VUNPCKLPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x14; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vunpcklps_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + + +# VBROADCAST 5-12 PAGE 1836 LINE 95843 +define pcodeop vbroadcastss_avx ; +:VBROADCASTSS XmmReg1, m32 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x18; (XmmReg1 & YmmReg1) ... & m32 +{ + local tmp:16 = vbroadcastss_avx( m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VBROADCAST 5-12 PAGE 1836 LINE 95845 +:VBROADCASTSS YmmReg1, m32 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x18; YmmReg1 ... & m32 +{ + YmmReg1 = vbroadcastss_avx( m32 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VBROADCAST 5-12 PAGE 1836 LINE 95847 +define pcodeop vbroadcastsd_avx ; +:VBROADCASTSD YmmReg1, m64 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x19; YmmReg1 ... & m64 +{ + YmmReg1 = vbroadcastsd_avx( m64 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VBROADCAST 5-12 PAGE 1836 LINE 95849 +define pcodeop vbroadcastf128_avx ; +:VBROADCASTF128 YmmReg1, m128 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1A; YmmReg1 ... & m128 +{ + YmmReg1 = vbroadcastf128_avx( m128 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VBROADCAST 5-12 PAGE 1836 LINE 95851 +# WARNING: duplicate opcode VEX.128.66.0F38.W0 18 /r last seen on 5-12 PAGE 1836 LINE 95843 for "VBROADCASTSS xmm1, xmm2" +define pcodeop vbroadcastss_avx2 ; +:VBROADCASTSS XmmReg1, XmmReg2 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x18; (XmmReg1 & YmmReg1) & (mod=0x3 & XmmReg2) +{ + local tmp:16 = vbroadcastss_avx2( XmmReg2 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VBROADCAST 5-12 PAGE 1836 LINE 95854 +# WARNING: duplicate opcode VEX.256.66.0F38.W0 18 /r last seen on 5-12 PAGE 1836 LINE 95845 for "VBROADCASTSS ymm1, xmm2" +:VBROADCASTSS YmmReg1, XmmReg2 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x18; YmmReg1 & (mod=0x3 & XmmReg2) +{ + YmmReg1 = vbroadcastss_avx2( XmmReg2 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VBROADCAST 5-12 PAGE 1836 LINE 95856 +# WARNING: duplicate opcode VEX.256.66.0F38.W0 19 /r last seen on 5-12 PAGE 1836 LINE 95847 for "VBROADCASTSD ymm1, xmm2" +define pcodeop vbroadcastsd_avx2 ; +:VBROADCASTSD YmmReg1, XmmReg2 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x19; YmmReg1 & (mod=0x3 & XmmReg2) +{ + YmmReg1 = vbroadcastsd_avx2( XmmReg2 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + + +# VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99102 +define pcodeop vextractf128_avx ; +:VEXTRACTF128 XmmReg2_m128, YmmReg1, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x19; YmmReg1 ... & XmmReg2_m128; imm8 +{ + XmmReg2_m128 = vextractf128_avx( YmmReg1, imm8:1 ); + # TODO ZmmReg2 = zext(XmmReg2) +} + +# VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109703 +define pcodeop vinsertf128_avx ; +:VINSERTF128 YmmReg1, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x18; YmmReg1 ... & XmmReg2_m128; imm8 +{ + YmmReg1 = vinsertf128_avx( vexVVVV_YmmReg, XmmReg2_m128, imm8:1 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VMASKMOV 5-318 PAGE 2142 LINE 110151 +define pcodeop vmaskmovps_avx ; +:VMASKMOVPS XmmReg1, vexVVVV_XmmReg, m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x2C; (XmmReg1 & YmmReg1) ... & m128 +{ + local tmp:16 = vmaskmovps_avx( vexVVVV_XmmReg, m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VMASKMOV 5-318 PAGE 2142 LINE 110154 +:VMASKMOVPS YmmReg1, vexVVVV_YmmReg, m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x2C; YmmReg1 ... & m256 +{ + YmmReg1 = vmaskmovps_avx( vexVVVV_YmmReg, m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VMASKMOV 5-318 PAGE 2142 LINE 110157 +define pcodeop vmaskmovpd_avx ; +:VMASKMOVPD XmmReg1, vexVVVV_XmmReg, m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x2D; (XmmReg1 & YmmReg1) ... & m128 +{ + local tmp:16 = vmaskmovpd_avx( vexVVVV_XmmReg, m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VMASKMOV 5-318 PAGE 2142 LINE 110160 +:VMASKMOVPD YmmReg1, vexVVVV_YmmReg, m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x2D; YmmReg1 ... & m256 +{ + YmmReg1 = vmaskmovpd_avx( vexVVVV_YmmReg, m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VMASKMOV 5-318 PAGE 2142 LINE 110163 +:VMASKMOVPS m128, vexVVVV_XmmReg, XmmReg1 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x2E; XmmReg1 ... & m128 +{ + m128 = vmaskmovps_avx( vexVVVV_XmmReg, XmmReg1 ); +} + +# VMASKMOV 5-318 PAGE 2142 LINE 110166 +:VMASKMOVPS m256, vexVVVV_YmmReg, YmmReg1 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x2E; YmmReg1 ... & m256 +{ + m256 = vmaskmovps_avx( vexVVVV_YmmReg, YmmReg1 ); +} + +# VMASKMOV 5-318 PAGE 2142 LINE 110168 +:VMASKMOVPD m128, vexVVVV_XmmReg, XmmReg1 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x2F; XmmReg1 ... & m128 +{ + m128 = vmaskmovpd_avx( vexVVVV_XmmReg, XmmReg1 ); +} + +# VMASKMOV 5-318 PAGE 2142 LINE 110171 +:VMASKMOVPD m256, vexVVVV_YmmReg, YmmReg1 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x2F; YmmReg1 ... & m256 +{ + m256 = vmaskmovpd_avx( vexVVVV_YmmReg, YmmReg1 ); +} + +# VPERM2F128 5-358 PAGE 2182 LINE 112216 +define pcodeop vperm2f128_avx ; +:VPERM2F128 YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x06; YmmReg1 ... & YmmReg2_m256; imm8 +{ + YmmReg1 = vperm2f128_avx( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VPERMILPD 5-371 PAGE 2195 LINE 112860 +define pcodeop vpermilpd_avx ; +:VPERMILPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x0D; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpermilpd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VPERMILPD 5-371 PAGE 2195 LINE 112863 +:VPERMILPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x0D; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpermilpd_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VPERMILPD 5-371 PAGE 2195 LINE 112875 +:VPERMILPD XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x05; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; imm8 +{ + local tmp:16 = vpermilpd_avx( XmmReg2_m128, imm8:1 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VPERMILPD 5-371 PAGE 2195 LINE 112877 +:VPERMILPD YmmReg1, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x05; YmmReg1 ... & YmmReg2_m256; imm8 +{ + YmmReg1 = vpermilpd_avx( YmmReg2_m256, imm8:1 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VPERMILPS 5-376 PAGE 2200 LINE 113158 +define pcodeop vpermilps_avx ; +:VPERMILPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x0C; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpermilps_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VPERMILPS 5-376 PAGE 2200 LINE 113161 +:VPERMILPS XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x04; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; imm8 +{ + local tmp:16 = vpermilps_avx( XmmReg2_m128, imm8:1 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VPERMILPS 5-376 PAGE 2200 LINE 113164 +:VPERMILPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x0C; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpermilps_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VPERMILPS 5-376 PAGE 2200 LINE 113167 +:VPERMILPS YmmReg1, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x04; YmmReg1 ... & YmmReg2_m256; imm8 +{ + YmmReg1 = vpermilps_avx( YmmReg2_m256, imm8:1 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VTESTPD/VTESTPS 5-560 PAGE 2384 LINE 122257 +define pcodeop vtestps_avx ; +:VTESTPS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x0E; XmmReg1 ... & XmmReg2_m128 +{ + vtestps_avx( XmmReg1, XmmReg2_m128 ); + # TODO set flags AF, CF, PF, SF, ZF +} + +# VTESTPD/VTESTPS 5-560 PAGE 2384 LINE 122260 +:VTESTPS YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x0E; YmmReg1 ... & YmmReg2_m256 +{ + vtestps_avx( YmmReg1, YmmReg2_m256 ); + # TODO set flags AF, CF, PF, SF, ZF +} + +# VTESTPD/VTESTPS 5-560 PAGE 2384 LINE 122263 +define pcodeop vtestpd_avx ; +:VTESTPD XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x0F; XmmReg1 ... & XmmReg2_m128 +{ + vtestpd_avx( XmmReg1, XmmReg2_m128 ); + # TODO set flags AF, CF, PF, SF, ZF +} + +# VTESTPD/VTESTPS 5-560 PAGE 2384 LINE 122266 +:VTESTPD YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x0F; YmmReg1 ... & YmmReg2_m256 +{ + vtestpd_avx( YmmReg1, YmmReg2_m256 ); + # TODO set flags AF, CF, PF, SF, ZF +} + +# XORPD 5-596 PAGE 2420 LINE 123828 +define pcodeop vxorpd_avx ; +:VXORPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x57; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vxorpd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# XORPD 5-596 PAGE 2420 LINE 123831 +:VXORPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x57; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vxorpd_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# XORPS 5-599 PAGE 2423 LINE 123953 +define pcodeop vxorps_avx ; +:VXORPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x57; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vxorps_avx( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# XORPS 5-599 PAGE 2423 LINE 123956 +:VXORPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x57; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vxorps_avx( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/avx2.sinc b/python/icicle/Ghidra/Processors/x86/data/languages/avx2.sinc new file mode 100644 index 0000000..2f96ccf --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/avx2.sinc @@ -0,0 +1,1221 @@ +# INFO This file automatically generated by andre on Thu May 10 11:02:19 2018 +# INFO Direct edits to this file may be lost in future updates +# INFO Command line arguments: ['--sinc', '--cpuid-match', '^AVX2\\b', '--skip-sinc', '../../../Processors/x86/data/languages/avx2_manual.sinc'] + +# MOVNTDQA 4-92 PAGE 1212 LINE 63086 +define pcodeop vmovntdqa_avx2 ; +:VMOVNTDQA YmmReg1, m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x2A; YmmReg1 ... & m256 +{ + YmmReg1 = vmovntdqa_avx2( m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# MPSADBW 4-136 PAGE 1256 LINE 65140 +define pcodeop vmpsadbw_avx2 ; +:VMPSADBW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x42; YmmReg1 ... & YmmReg2_m256; imm8 +{ + YmmReg1 = vmpsadbw_avx2( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67311 +define pcodeop vpabsb_avx2 ; +:VPABSB YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x1C; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpabsb_avx2( YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67314 +define pcodeop vpabsw_avx2 ; +:VPABSW YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x1D; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpabsw_avx2( YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67317 +define pcodeop vpabsd_avx2 ; +:VPABSD YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x1E; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpabsd_avx2( YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67637 +define pcodeop vpacksswb_avx2 ; +:VPACKSSWB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x63; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpacksswb_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67641 +define pcodeop vpackssdw_avx2 ; +:VPACKSSDW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x6B; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpackssdw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PACKUSDW 4-194 PAGE 1314 LINE 68090 +define pcodeop vpackusdw_avx2 ; +:VPACKUSDW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0x2B; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpackusdw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PACKUSWB 4-199 PAGE 1319 LINE 68370 +define pcodeop vpackuswb_avx2 ; +:VPACKUSWB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x67; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpackuswb_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68666 +define pcodeop vpaddb_avx2 ; +:VPADDB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xFC; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpaddb_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68668 +define pcodeop vpaddw_avx2 ; +:VPADDW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xFD; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpaddw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68670 +define pcodeop vpaddd_avx2 ; +:VPADDD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xFE; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpaddd_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68672 +define pcodeop vpaddq_avx2 ; +:VPADDQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD4; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpaddq_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PADDSB/PADDSW 4-211 PAGE 1331 LINE 69045 +define pcodeop vpaddsb_avx2 ; +:VPADDSB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xEC; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpaddsb_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PADDSB/PADDSW 4-211 PAGE 1331 LINE 69048 +define pcodeop vpaddsw_avx2 ; +:VPADDSW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xED; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpaddsw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69263 +define pcodeop vpaddusb_avx2 ; +:VPADDUSB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xDC; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpaddusb_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69266 +define pcodeop vpaddusw_avx2 ; +:VPADDUSW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xDD; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpaddusw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PALIGNR 4-219 PAGE 1339 LINE 69489 +define pcodeop vpalignr_avx2 ; +:VPALIGNR YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x0F; YmmReg1 ... & YmmReg2_m256; imm8 +{ + YmmReg1 = vpalignr_avx2( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PAND 4-223 PAGE 1343 LINE 69680 +define pcodeop vpand_avx2 ; +:VPAND YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xDB; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpand_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PANDN 4-226 PAGE 1346 LINE 69856 +define pcodeop vpandn_avx2 ; +:VPANDN YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xDF; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpandn_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PAVGB/PAVGW 4-230 PAGE 1350 LINE 70091 +define pcodeop vpavgb_avx2 ; +:VPAVGB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE0; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpavgb_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PAVGB/PAVGW 4-230 PAGE 1350 LINE 70094 +define pcodeop vpavgw_avx2 ; +:VPAVGW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE3; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpavgw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PBLENDVB 4-234 PAGE 1354 LINE 70300 +define pcodeop vpblendvb_avx2 ; +:VPBLENDVB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, Ymm_imm8_7_4 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x4C; YmmReg1 ... & YmmReg2_m256; Ymm_imm8_7_4 +{ + YmmReg1 = vpblendvb_avx2( vexVVVV_YmmReg, YmmReg2_m256, Ymm_imm8_7_4 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PBLENDW 4-238 PAGE 1358 LINE 70525 +define pcodeop vpblendw_avx2 ; +:VPBLENDW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x0E; YmmReg1 ... & YmmReg2_m256; imm8 +{ + YmmReg1 = vpblendw_avx2( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70830 +define pcodeop vpcmpeqb_avx2 ; +:VPCMPEQB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x74; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpcmpeqb_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70833 +define pcodeop vpcmpeqw_avx2 ; +:VPCMPEQW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x75; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpcmpeqw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70837 +define pcodeop vpcmpeqd_avx2 ; +:VPCMPEQD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x76; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpcmpeqd_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71508 +define pcodeop vpcmpgtb_avx2 ; +:VPCMPGTB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x64; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpcmpgtb_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71511 +define pcodeop vpcmpgtw_avx2 ; +:VPCMPGTW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x65; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpcmpgtw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71514 +define pcodeop vpcmpgtd_avx2 ; +:VPCMPGTD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x66; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpcmpgtd_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PCMPGTQ 4-263 PAGE 1383 LINE 71835 +define pcodeop vpcmpgtq_avx2 ; +:VPCMPGTQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x37; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpcmpgtq_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PHADDW/PHADDD 4-280 PAGE 1400 LINE 72633 +define pcodeop vphaddw_avx2 ; +:VPHADDW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x01; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vphaddw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PHADDW/PHADDD 4-280 PAGE 1400 LINE 72636 +define pcodeop vphaddd_avx2 ; +:VPHADDD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x02; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vphaddd_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PHADDSW 4-284 PAGE 1404 LINE 72824 +define pcodeop vphaddsw_avx2 ; +:VPHADDSW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x03; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vphaddsw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PHSUBW/PHSUBD 4-288 PAGE 1408 LINE 73038 +define pcodeop vphsubw_avx2 ; +:VPHSUBW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x05; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vphsubw_avx2( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PHSUBW/PHSUBD 4-288 PAGE 1408 LINE 73041 +define pcodeop vphsubd_avx2 ; +:VPHSUBD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x06; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vphsubd_avx2( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PHSUBSW 4-291 PAGE 1411 LINE 73200 +define pcodeop vphsubsw_avx2 ; +:VPHSUBSW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x07; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vphsubsw_avx2( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMADDUBSW 4-298 PAGE 1418 LINE 73555 +define pcodeop vpmaddubsw_avx2 ; +:VPMADDUBSW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x04; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpmaddubsw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMADDWD 4-301 PAGE 1421 LINE 73704 +define pcodeop vpmaddwd_avx2 ; +:VPMADDWD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xF5; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpmaddwd_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73891 +define pcodeop vpmaxsb_avx2 ; +:VPMAXSB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x3C; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpmaxsb_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73894 +define pcodeop vpmaxsw_avx2 ; +:VPMAXSW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xEE; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpmaxsw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73897 +define pcodeop vpmaxsd_avx2 ; +:VPMAXSD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x3D; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpmaxsd_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74289 +define pcodeop vpmaxub_avx2 ; +:VPMAXUB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0xDE; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpmaxub_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74292 +define pcodeop vpmaxuw_avx2 ; +:VPMAXUW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0x3E; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpmaxuw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74537 +define pcodeop vpmaxud_avx2 ; +:VPMAXUD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x3F; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpmaxud_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMINSB/PMINSW 4-320 PAGE 1440 LINE 74742 +define pcodeop vpminsb_avx2 ; +:VPMINSB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0x38; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpminsb_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMINSB/PMINSW 4-320 PAGE 1440 LINE 74745 +define pcodeop vpminsw_avx2 ; +:VPMINSW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0xEA; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpminsw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMINSD/PMINSQ 4-325 PAGE 1445 LINE 74992 +define pcodeop vpminsd_avx2 ; +:VPMINSD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x39; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpminsd_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMINUB/PMINUW 4-329 PAGE 1449 LINE 75201 +define pcodeop vpminub_avx2 ; +:VPMINUB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0xDA; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpminub_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMINUB/PMINUW 4-329 PAGE 1449 LINE 75204 +define pcodeop vpminuw_avx2 ; +:VPMINUW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0x3A; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpminuw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75448 +define pcodeop vpminud_avx2 ; +:VPMINUD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x3B; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpminud_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMOVSX 4-340 PAGE 1460 LINE 75782 +define pcodeop vpmovsxbw_avx2 ; +:VPMOVSXBW YmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x20; YmmReg1 ... & XmmReg2_m128 +{ + YmmReg1 = vpmovsxbw_avx2( XmmReg2_m128 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMOVSX 4-340 PAGE 1460 LINE 75784 +define pcodeop vpmovsxbd_avx2 ; +:VPMOVSXBD YmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x21; YmmReg1 ... & XmmReg2_m64 +{ + YmmReg1 = vpmovsxbd_avx2( XmmReg2_m64 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMOVSX 4-340 PAGE 1460 LINE 75786 +define pcodeop vpmovsxbq_avx2 ; +:VPMOVSXBQ YmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x22; YmmReg1 ... & XmmReg2_m32 +{ + YmmReg1 = vpmovsxbq_avx2( XmmReg2_m32 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMOVSX 4-340 PAGE 1460 LINE 75788 +define pcodeop vpmovsxwd_avx2 ; +:VPMOVSXWD YmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x23; YmmReg1 ... & XmmReg2_m128 +{ + YmmReg1 = vpmovsxwd_avx2( XmmReg2_m128 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMOVSX 4-340 PAGE 1460 LINE 75791 +define pcodeop vpmovsxwq_avx2 ; +:VPMOVSXWQ YmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x24; YmmReg1 ... & XmmReg2_m64 +{ + YmmReg1 = vpmovsxwq_avx2( XmmReg2_m64 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMOVSX 4-340 PAGE 1460 LINE 75793 +define pcodeop vpmovsxdq_avx2 ; +:VPMOVSXDQ YmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x25; YmmReg1 ... & XmmReg2_m128 +{ + YmmReg1 = vpmovsxdq_avx2( XmmReg2_m128 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMOVZX 4-350 PAGE 1470 LINE 76304 +define pcodeop vpmovzxbw_avx2 ; +:VPMOVZXBW YmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x30; YmmReg1 ... & XmmReg2_m128 +{ + YmmReg1 = vpmovzxbw_avx2( XmmReg2_m128 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMOVZX 4-350 PAGE 1470 LINE 76306 +define pcodeop vpmovzxbd_avx2 ; +:VPMOVZXBD YmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x31; YmmReg1 ... & XmmReg2_m64 +{ + YmmReg1 = vpmovzxbd_avx2( XmmReg2_m64 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMOVZX 4-350 PAGE 1470 LINE 76309 +define pcodeop vpmovzxbq_avx2 ; +:VPMOVZXBQ YmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x32; YmmReg1 ... & XmmReg2_m32 +{ + YmmReg1 = vpmovzxbq_avx2( XmmReg2_m32 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMOVZX 4-350 PAGE 1470 LINE 76312 +define pcodeop vpmovzxwd_avx2 ; +:VPMOVZXWD YmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x33; YmmReg1 ... & XmmReg2_m128 +{ + YmmReg1 = vpmovzxwd_avx2( XmmReg2_m128 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMOVZX 4-350 PAGE 1470 LINE 76314 +define pcodeop vpmovzxwq_avx2 ; +:VPMOVZXWQ YmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x34; YmmReg1 ... & XmmReg2_m64 +{ + YmmReg1 = vpmovzxwq_avx2( XmmReg2_m64 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMOVZX 4-350 PAGE 1470 LINE 76317 +define pcodeop vpmovzxdq_avx2 ; +:VPMOVZXDQ YmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x35; YmmReg1 ... & XmmReg2_m128 +{ + YmmReg1 = vpmovzxdq_avx2( XmmReg2_m128 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMULDQ 4-359 PAGE 1479 LINE 76791 +define pcodeop vpmuldq_avx2 ; +:VPMULDQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x28; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpmuldq_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMULHRSW 4-362 PAGE 1482 LINE 76931 +define pcodeop vpmulhrsw_avx2 ; +:VPMULHRSW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x0B; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpmulhrsw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMULHUW 4-366 PAGE 1486 LINE 77144 +define pcodeop vpmulhuw_avx2 ; +:VPMULHUW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE4; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpmulhuw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMULHW 4-370 PAGE 1490 LINE 77373 +define pcodeop vpmulhw_avx2 ; +:VPMULHW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE5; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpmulhw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77579 +define pcodeop vpmulld_avx2 ; +:VPMULLD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x40; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpmulld_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMULLW 4-378 PAGE 1498 LINE 77778 +define pcodeop vpmullw_avx2 ; +:VPMULLW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD5; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpmullw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PMULUDQ 4-382 PAGE 1502 LINE 77973 +define pcodeop vpmuludq_avx2 ; +:VPMULUDQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xF4; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpmuludq_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# POR 4-399 PAGE 1519 LINE 78852 +define pcodeop vpor_avx2 ; +:VPOR YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xEB; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpor_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PSADBW 4-408 PAGE 1528 LINE 79245 +define pcodeop vpsadbw_avx2 ; +:VPSADBW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xF6; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpsadbw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PSHUFB 4-412 PAGE 1532 LINE 79463 +define pcodeop vpshufb_avx2 ; +:VPSHUFB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x00; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpshufb_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PSHUFD 4-416 PAGE 1536 LINE 79653 +define pcodeop vpshufd_avx2 ; +:VPSHUFD YmmReg1, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x70; YmmReg1 ... & YmmReg2_m256; imm8 +{ + YmmReg1 = vpshufd_avx2( YmmReg2_m256, imm8:1 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PSHUFHW 4-420 PAGE 1540 LINE 79860 +define pcodeop vpshufhw_avx2 ; +:VPSHUFHW YmmReg1, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x70; YmmReg1 ... & YmmReg2_m256; imm8 +{ + YmmReg1 = vpshufhw_avx2( YmmReg2_m256, imm8:1 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PSHUFLW 4-423 PAGE 1543 LINE 80035 +define pcodeop vpshuflw_avx2 ; +:VPSHUFLW YmmReg1, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0x70; YmmReg1 ... & YmmReg2_m256; imm8 +{ + YmmReg1 = vpshuflw_avx2( YmmReg2_m256, imm8:1 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PSIGNB/PSIGNW/PSIGND 4-427 PAGE 1547 LINE 80278 +define pcodeop vpsignb_avx2 ; +:VPSIGNB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x08; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpsignb_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PSIGNB/PSIGNW/PSIGND 4-427 PAGE 1547 LINE 80281 +define pcodeop vpsignw_avx2 ; +:VPSIGNW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x09; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpsignw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PSIGNB/PSIGNW/PSIGND 4-427 PAGE 1547 LINE 80284 +define pcodeop vpsignd_avx2 ; +:VPSIGND YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x0A; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpsignd_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PSLLDQ 4-431 PAGE 1551 LINE 80488 +define pcodeop vpslldq_avx2 ; +:VPSLLDQ vexVVVV_YmmReg, YmmReg2, imm8 is $(VEX_NDD) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x73; reg_opcode=7 & (mod=0x3 & YmmReg2); imm8 +{ + vexVVVV_YmmReg = vpslldq_avx2( YmmReg2, imm8:1 ); +} + +# PSLLW/PSLLD/PSLLQ 4-433 PAGE 1553 LINE 80638 +define pcodeop vpsllw_avx2 ; +:VPSLLW YmmReg1, vexVVVV_YmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xF1; YmmReg1 ... & XmmReg2_m128 +{ + YmmReg1 = vpsllw_avx2( vexVVVV_YmmReg, XmmReg2_m128 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PSLLW/PSLLD/PSLLQ 4-433 PAGE 1553 LINE 80641 +:VPSLLW vexVVVV_YmmReg, YmmReg2, imm8 is $(VEX_NDD) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x71; reg_opcode=6 & (mod=0x3 & YmmReg2); imm8 +{ + vexVVVV_YmmReg = vpsllw_avx2( YmmReg2, imm8:1 ); +} + +# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80656 +define pcodeop vpslld_avx2 ; +:VPSLLD YmmReg1, vexVVVV_YmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xF2; YmmReg1 ... & XmmReg2_m128 +{ + YmmReg1 = vpslld_avx2( vexVVVV_YmmReg, XmmReg2_m128 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80659 +:VPSLLD vexVVVV_YmmReg, YmmReg2, imm8 is $(VEX_NDD) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x72; reg_opcode=6 & (mod=0x3 & YmmReg2); imm8 +{ + vexVVVV_YmmReg = vpslld_avx2( YmmReg2, imm8:1 ); +} + +# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80662 +define pcodeop vpsllq_avx2 ; +:VPSLLQ YmmReg1, vexVVVV_YmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xF3; YmmReg1 ... & XmmReg2_m128 +{ + YmmReg1 = vpsllq_avx2( vexVVVV_YmmReg, XmmReg2_m128 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80664 +:VPSLLQ vexVVVV_YmmReg, YmmReg2, imm8 is $(VEX_NDD) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x73; reg_opcode=6 & (mod=0x3 & YmmReg2); imm8 +{ + vexVVVV_YmmReg = vpsllq_avx2( YmmReg2, imm8:1 ); +} + +# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81317 +define pcodeop vpsraw_avx2 ; +:VPSRAW YmmReg1, vexVVVV_YmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE1; YmmReg1 ... & XmmReg2_m128 +{ + YmmReg1 = vpsraw_avx2( vexVVVV_YmmReg, XmmReg2_m128 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81320 +:VPSRAW vexVVVV_YmmReg, YmmReg2, imm8 is $(VEX_NDD) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x71; reg_opcode=4 & (mod=0x3 & YmmReg2); imm8 +{ + vexVVVV_YmmReg = vpsraw_avx2( YmmReg2, imm8:1 ); +} + +# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81323 +define pcodeop vpsrad_avx2 ; +:VPSRAD YmmReg1, vexVVVV_YmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE2; YmmReg1 ... & XmmReg2_m128 +{ + YmmReg1 = vpsrad_avx2( vexVVVV_YmmReg, XmmReg2_m128 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81326 +:VPSRAD vexVVVV_YmmReg, YmmReg2, imm8 is $(VEX_NDD) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x72; reg_opcode=4 & (mod=0x3 & YmmReg2); imm8 +{ + vexVVVV_YmmReg = vpsrad_avx2( YmmReg2, imm8:1 ); +} + +# PSRLDQ 4-455 PAGE 1575 LINE 81876 +define pcodeop vpsrldq_avx2 ; +:VPSRLDQ vexVVVV_YmmReg, YmmReg2, imm8 is $(VEX_NDD) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x73; reg_opcode=3 & (mod=0x3 & YmmReg2); imm8 +{ + vexVVVV_YmmReg = vpsrldq_avx2( YmmReg2, imm8:1 ); +} + +# PSRLW/PSRLD/PSRLQ 4-457 PAGE 1577 LINE 82030 +define pcodeop vpsrlw_avx2 ; +:VPSRLW YmmReg1, vexVVVV_YmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD1; YmmReg1 ... & XmmReg2_m128 +{ + YmmReg1 = vpsrlw_avx2( vexVVVV_YmmReg, XmmReg2_m128 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PSRLW/PSRLD/PSRLQ 4-457 PAGE 1577 LINE 82033 +:VPSRLW vexVVVV_YmmReg, YmmReg2, imm8 is $(VEX_NDD) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x71; reg_opcode=2 & (mod=0x3 & YmmReg2); imm8 +{ + vexVVVV_YmmReg = vpsrlw_avx2( YmmReg2, imm8:1 ); +} + +# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82048 +define pcodeop vpsrld_avx2 ; +:VPSRLD YmmReg1, vexVVVV_YmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD2; YmmReg1 ... & XmmReg2_m128 +{ + YmmReg1 = vpsrld_avx2( vexVVVV_YmmReg, XmmReg2_m128 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82051 +:VPSRLD vexVVVV_YmmReg, YmmReg2, imm8 is $(VEX_NDD) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x72; reg_opcode=2 & (mod=0x3 & YmmReg2); imm8 +{ + vexVVVV_YmmReg = vpsrld_avx2( YmmReg2, imm8:1 ); +} + +# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82054 +define pcodeop vpsrlq_avx2 ; +:VPSRLQ YmmReg1, vexVVVV_YmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD3; YmmReg1 ... & XmmReg2_m128 +{ + YmmReg1 = vpsrlq_avx2( vexVVVV_YmmReg, XmmReg2_m128 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82056 +:VPSRLQ vexVVVV_YmmReg, YmmReg2, imm8 is $(VEX_NDD) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x73; reg_opcode=2 & (mod=0x3 & YmmReg2); imm8 +{ + vexVVVV_YmmReg = vpsrlq_avx2( YmmReg2, imm8:1 ); +} + +# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82696 +define pcodeop vpsubb_avx2 ; +:VPSUBB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xF8; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpsubb_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82698 +define pcodeop vpsubw_avx2 ; +:VPSUBW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xF9; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpsubw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82700 +define pcodeop vpsubd_avx2 ; +:VPSUBD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xFA; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpsubd_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PSUBQ 4-476 PAGE 1596 LINE 83104 +define pcodeop vpsubq_avx2 ; +:VPSUBQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xFB; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpsubq_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83264 +define pcodeop vpsubsb_avx2 ; +:VPSUBSB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE8; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpsubsb_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83267 +define pcodeop vpsubsw_avx2 ; +:VPSUBSW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE9; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpsubsw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83504 +define pcodeop vpsubusb_avx2 ; +:VPSUBUSB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD8; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpsubusb_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83507 +define pcodeop vpsubusw_avx2 ; +:VPSUBUSW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD9; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpsubusw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83940 +define pcodeop vpunpckhbw_avx2 ; +:VPUNPCKHBW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x68; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpunpckhbw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83942 +define pcodeop vpunpckhwd_avx2 ; +:VPUNPCKHWD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x69; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpunpckhwd_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83944 +define pcodeop vpunpckhdq_avx2 ; +:VPUNPCKHDQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x6A; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpunpckhdq_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83946 +define pcodeop vpunpckhqdq_avx2 ; +:VPUNPCKHQDQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x6D; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpunpckhqdq_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84541 +define pcodeop vpunpcklbw_avx2 ; +:VPUNPCKLBW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x60; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpunpcklbw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84544 +define pcodeop vpunpcklwd_avx2 ; +:VPUNPCKLWD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x61; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpunpcklwd_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84547 +define pcodeop vpunpckldq_avx2 ; +:VPUNPCKLDQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x62; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpunpckldq_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84550 +define pcodeop vpunpcklqdq_avx2 ; +:VPUNPCKLQDQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x6C; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpunpcklqdq_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# PXOR 4-518 PAGE 1638 LINE 85497 +define pcodeop vpxor_avx2 ; +:VPXOR YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xEF; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpxor_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99432 +define pcodeop vextracti128_avx2 ; +:VEXTRACTI128 XmmReg2_m128, YmmReg1, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x39; YmmReg1 ... & XmmReg2_m128; imm8 +{ + XmmReg2_m128 = vextracti128_avx2( YmmReg1, imm8:1 ); + # TODO ZmmReg2 = zext(XmmReg2) +} + +# VGATHERDPD/VGATHERQPD 5-251 PAGE 2075 LINE 106903 +# INFO mnemonic VGATHERDPD was found in ../../../Processors/x86/data/languages/avx2_manual.sinc + +# VGATHERDPD/VGATHERQPD 5-251 PAGE 2075 LINE 106908 +# INFO mnemonic VGATHERQPD was found in ../../../Processors/x86/data/languages/avx2_manual.sinc + +# VGATHERDPD/VGATHERQPD 5-251 PAGE 2075 LINE 106913 +# INFO mnemonic VGATHERDPD was found in ../../../Processors/x86/data/languages/avx2_manual.sinc + +# VGATHERDPD/VGATHERQPD 5-251 PAGE 2075 LINE 106918 +# INFO mnemonic VGATHERQPD was found in ../../../Processors/x86/data/languages/avx2_manual.sinc + +# VGATHERDPS/VGATHERQPS 5-256 PAGE 2080 LINE 107130 +# INFO mnemonic VGATHERDPS was found in ../../../Processors/x86/data/languages/avx2_manual.sinc + +# VGATHERDPS/VGATHERQPS 5-256 PAGE 2080 LINE 107135 +# INFO mnemonic VGATHERQPS was found in ../../../Processors/x86/data/languages/avx2_manual.sinc + +# VGATHERDPS/VGATHERQPS 5-256 PAGE 2080 LINE 107140 +# INFO mnemonic VGATHERDPS was found in ../../../Processors/x86/data/languages/avx2_manual.sinc + +# VGATHERDPS/VGATHERQPS 5-256 PAGE 2080 LINE 107145 +# INFO mnemonic VGATHERQPS was found in ../../../Processors/x86/data/languages/avx2_manual.sinc + +# VPGATHERDD/VPGATHERQD 5-273 PAGE 2097 LINE 107884 +# INFO mnemonic VPGATHERDD was found in ../../../Processors/x86/data/languages/avx2_manual.sinc + +# VPGATHERDD/VPGATHERQD 5-273 PAGE 2097 LINE 107888 +# INFO mnemonic VPGATHERQD was found in ../../../Processors/x86/data/languages/avx2_manual.sinc + +# VPGATHERDD/VPGATHERQD 5-273 PAGE 2097 LINE 107892 +# INFO mnemonic VPGATHERDD was found in ../../../Processors/x86/data/languages/avx2_manual.sinc + +# VPGATHERDD/VPGATHERQD 5-273 PAGE 2097 LINE 107896 +# INFO mnemonic VPGATHERQD was found in ../../../Processors/x86/data/languages/avx2_manual.sinc + +# VPGATHERDQ/VPGATHERQQ 5-280 PAGE 2104 LINE 108234 +# INFO mnemonic VPGATHERDQ was found in ../../../Processors/x86/data/languages/avx2_manual.sinc + +# VPGATHERDQ/VPGATHERQQ 5-280 PAGE 2104 LINE 108238 +# INFO mnemonic VPGATHERQQ was found in ../../../Processors/x86/data/languages/avx2_manual.sinc + +# VPGATHERDQ/VPGATHERQQ 5-280 PAGE 2104 LINE 108242 +# INFO mnemonic VPGATHERDQ was found in ../../../Processors/x86/data/languages/avx2_manual.sinc + +# VPGATHERDQ/VPGATHERQQ 5-280 PAGE 2104 LINE 108246 +# INFO mnemonic VPGATHERQQ was found in ../../../Processors/x86/data/languages/avx2_manual.sinc + +# VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109927 +# INFO mnemonic VINSERTI128 was found in ../../../Processors/x86/data/languages/avx2_manual.sinc + +# VPBLENDD 5-321 PAGE 2145 LINE 110309 +define pcodeop vpblendd_avx2 ; +:VPBLENDD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x02; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; imm8 +{ + local tmp:16 = vpblendd_avx2( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VPBLENDD 5-321 PAGE 2145 LINE 110312 +:VPBLENDD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x02; YmmReg1 ... & YmmReg2_m256; imm8 +{ + YmmReg1 = vpblendd_avx2( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VPBROADCAST 5-331 PAGE 2155 LINE 110776 +define pcodeop vpbroadcastb_avx2 ; +:VPBROADCASTB XmmReg1, XmmReg2_m8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x78; (XmmReg1 & YmmReg1) ... & XmmReg2_m8 +{ + local tmp:16 = vpbroadcastb_avx2( XmmReg2_m8 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VPBROADCAST 5-331 PAGE 2155 LINE 110778 +:VPBROADCASTB YmmReg1, XmmReg2_m8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x78; YmmReg1 ... & XmmReg2_m8 +{ + YmmReg1 = vpbroadcastb_avx2( XmmReg2_m8 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VPBROADCAST 5-331 PAGE 2155 LINE 110787 +define pcodeop vpbroadcastw_avx2 ; +:VPBROADCASTW XmmReg1, XmmReg2_m16 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x79; (XmmReg1 & YmmReg1) ... & XmmReg2_m16 +{ + local tmp:16 = vpbroadcastw_avx2( XmmReg2_m16 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VPBROADCAST 5-331 PAGE 2155 LINE 110789 +:VPBROADCASTW YmmReg1, XmmReg2_m16 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x79; YmmReg1 ... & XmmReg2_m16 +{ + YmmReg1 = vpbroadcastw_avx2( XmmReg2_m16 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VPBROADCAST 5-331 PAGE 2155 LINE 110800 +define pcodeop vpbroadcastd_avx2 ; +:VPBROADCASTD XmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x58; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vpbroadcastd_avx2( XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VPBROADCAST 5-331 PAGE 2155 LINE 110802 +:VPBROADCASTD YmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x58; YmmReg1 ... & XmmReg2_m32 +{ + YmmReg1 = vpbroadcastd_avx2( XmmReg2_m32 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VPBROADCAST 5-331 PAGE 2155 LINE 110813 +define pcodeop vpbroadcastq_avx2 ; +:VPBROADCASTQ XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x59; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vpbroadcastq_avx2( XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VPBROADCAST 5-331 PAGE 2155 LINE 110815 +:VPBROADCASTQ YmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x59; YmmReg1 ... & XmmReg2_m64 +{ + YmmReg1 = vpbroadcastq_avx2( XmmReg2_m64 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VPBROADCAST 5-332 PAGE 2156 LINE 110843 +define pcodeop vbroadcasti128_avx2 ; +:VBROADCASTI128 YmmReg1, m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x5A; YmmReg1 ... & m128 +{ + YmmReg1 = vbroadcasti128_avx2( m128 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VPERM2I128 5-360 PAGE 2184 LINE 112312 +define pcodeop vperm2i128_avx2 ; +:VPERM2I128 YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x46; YmmReg1 ... & YmmReg2_m256; imm8 +{ + YmmReg1 = vperm2i128_avx2( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VPERMD/VPERMW 5-362 PAGE 2186 LINE 112405 +define pcodeop vpermd_avx2 ; +:VPERMD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x36; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpermd_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VPERMPD 5-381 PAGE 2205 LINE 113452 +define pcodeop vpermpd_avx2 ; +:VPERMPD YmmReg1, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1); byte=0x01; YmmReg1 ... & YmmReg2_m256; imm8 +{ + YmmReg1 = vpermpd_avx2( YmmReg2_m256, imm8:1 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VPERMPS 5-384 PAGE 2208 LINE 113633 +define pcodeop vpermps_avx2 ; +:VPERMPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x16; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpermps_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VPERMQ 5-387 PAGE 2211 LINE 113768 +define pcodeop vpermq_avx2 ; +:VPERMQ YmmReg1, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1); byte=0x00; YmmReg1 ... & YmmReg2_m256; imm8 +{ + YmmReg1 = vpermq_avx2( YmmReg2_m256, imm8:1 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VPMASKMOV 5-397 PAGE 2221 LINE 114262 +define pcodeop vpmaskmovd_avx2 ; +:VPMASKMOVD XmmReg1, vexVVVV_XmmReg, m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x8C; (XmmReg1 & YmmReg1) ... & m128 +{ + local tmp:16 = vpmaskmovd_avx2( vexVVVV_XmmReg, m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VPMASKMOV 5-397 PAGE 2221 LINE 114264 +:VPMASKMOVD YmmReg1, vexVVVV_YmmReg, m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x8C; YmmReg1 ... & m256 +{ + YmmReg1 = vpmaskmovd_avx2( vexVVVV_YmmReg, m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VPMASKMOV 5-397 PAGE 2221 LINE 114266 +define pcodeop vpmaskmovq_avx2 ; +:VPMASKMOVQ XmmReg1, vexVVVV_XmmReg, m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x8C; (XmmReg1 & YmmReg1) ... & m128 +{ + local tmp:16 = vpmaskmovq_avx2( vexVVVV_XmmReg, m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VPMASKMOV 5-397 PAGE 2221 LINE 114268 +:VPMASKMOVQ YmmReg1, vexVVVV_YmmReg, m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x8C; YmmReg1 ... & m256 +{ + YmmReg1 = vpmaskmovq_avx2( vexVVVV_YmmReg, m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VPMASKMOV 5-397 PAGE 2221 LINE 114270 +:VPMASKMOVD m128, vexVVVV_XmmReg, XmmReg1 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x8E; XmmReg1 ... & m128 +{ + m128 = vpmaskmovd_avx2( vexVVVV_XmmReg, XmmReg1 ); +} + +# VPMASKMOV 5-397 PAGE 2221 LINE 114272 +:VPMASKMOVD m256, vexVVVV_YmmReg, YmmReg1 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x8E; YmmReg1 ... & m256 +{ + m256 = vpmaskmovd_avx2( vexVVVV_YmmReg, YmmReg1 ); +} + +# VPMASKMOV 5-397 PAGE 2221 LINE 114274 +:VPMASKMOVQ m128, vexVVVV_XmmReg, XmmReg1 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x8E; XmmReg1 ... & m128 +{ + m128 = vpmaskmovq_avx2( vexVVVV_XmmReg, XmmReg1 ); +} + +# VPMASKMOV 5-397 PAGE 2221 LINE 114276 +:VPMASKMOVQ m256, vexVVVV_YmmReg, YmmReg1 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x8E; YmmReg1 ... & m256 +{ + m256 = vpmaskmovq_avx2( vexVVVV_YmmReg, YmmReg1 ); +} + +# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116620 +define pcodeop vpsllvd_avx2 ; +:VPSLLVD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x47; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpsllvd_avx2( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116623 +define pcodeop vpsllvq_avx2 ; +:VPSLLVQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x47; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpsllvq_avx2( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116626 +:VPSLLVD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x47; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpsllvd_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116629 +:VPSLLVQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x47; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpsllvq_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116874 +define pcodeop vpsravd_avx2 ; +:VPSRAVD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x46; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpsravd_avx2( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116877 +:VPSRAVD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x46; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpsravd_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117139 +define pcodeop vpsrlvd_avx2 ; +:VPSRLVD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x45; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpsrlvd_avx2( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117142 +define pcodeop vpsrlvq_avx2 ; +:VPSRLVQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x45; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vpsrlvq_avx2( vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117145 +:VPSRLVD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x45; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpsrlvd_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117148 +:VPSRLVQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x45; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vpsrlvq_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/avx2_manual.sinc b/python/icicle/Ghidra/Processors/x86/data/languages/avx2_manual.sinc new file mode 100644 index 0000000..221b22b --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/avx2_manual.sinc @@ -0,0 +1,252 @@ +# VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109785 +define pcodeop vinserti128 ; +:VINSERTI128 YmmReg1, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x38; YmmReg1 ... & XmmReg2_m128; imm8 & imm8_0 { + local tmp:16 = XmmReg2_m128; + + # ignoring all but the least significant bit + if (imm8_0:1 == 0) goto ; + if (imm8_0:1 == 1) goto ; + + + YmmReg1[0,128] = tmp; + YmmReg1[128,128] = vexVVVV_YmmReg[128,128]; + goto ; + + + YmmReg1[0,128] = vexVVVV_YmmReg[0,128]; + YmmReg1[128,128] = tmp; + + +} + +# VGATHERDPD/VGATHERQPD 5-251 PAGE 2075 LINE 106903 +define pcodeop vgatherdpd ; +:VGATHERDPD XmmReg1, q_vm32x, vexVVVV_XmmReg is $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x92; (XmmReg1 & YmmReg1) ... & q_vm32x { +# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now +# XmmReg1 = vgatherdpd(XmmReg1, q_vm32x, vexVVVV_XmmReg); + local tmp:16 = vgatherdpd(XmmReg1, vexVVVV_XmmReg); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) + vexVVVV_XmmReg = 0; +} + +# VGATHERDPD/VGATHERQPD 5-251 PAGE 2075 LINE 106908 +@ifdef IA64 +define pcodeop vgatherqpd ; +:VGATHERQPD XmmReg1, q_vm64x, vexVVVV_XmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x93; (XmmReg1 & YmmReg1) ... & q_vm64x { +# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now +# XmmReg1 = vgatherqpd(XmmReg1, q_vm64x, vexVVVV_XmmReg); + local tmp:16 = vgatherqpd(XmmReg1, vexVVVV_XmmReg); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) + vexVVVV_XmmReg = 0; +} +@endif + +# VGATHERDPD/VGATHERQPD 5-251 PAGE 2075 LINE 106913 +:VGATHERDPD YmmReg1, q_vm32x, vexVVVV_YmmReg is $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x92; YmmReg1 ... & q_vm32x { +# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now +# YmmReg1 = vgatherdpd(YmmReg1, q_vm32x, vexVVVV_YmmReg); + YmmReg1 = vgatherdpd(YmmReg1, vexVVVV_YmmReg); + # TODO ZmmReg1 = zext(YmmReg1) + vexVVVV_YmmReg = 0; +} + +# VGATHERDPD/VGATHERQPD 5-251 PAGE 2075 LINE 106918 +@ifdef IA64 +:VGATHERQPD YmmReg1, q_vm64y, vexVVVV_YmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x93; YmmReg1 ... & q_vm64y { +# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now +# YmmReg1 = vgatherqpd(YmmReg1, q_vm64y, vexVVVV_YmmReg); + YmmReg1 = vgatherqpd(YmmReg1, vexVVVV_YmmReg); + # TODO ZmmReg1 = zext(YmmReg1) + vexVVVV_YmmReg = 0; +} +@endif + + +# VGATHERDPS/VGATHERQPS 5-256 PAGE 2080 LINE 107130 +define pcodeop vgatherdps ; +:VGATHERDPS XmmReg1, d_vm32x, vexVVVV_XmmReg is $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x92; (XmmReg1 & YmmReg1) ... & d_vm32x { +# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now +# XmmReg1 = vgatherdps(XmmReg1, d_vm32x, vexVVVV_XmmReg); + local tmp:16 = vgatherdps(XmmReg1, vexVVVV_XmmReg); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) + vexVVVV_XmmReg = 0; +} + +# VGATHERDPS/VGATHERQPS 5-256 PAGE 2080 LINE 107135 +@ifdef IA64 +define pcodeop vgatherqps ; +:VGATHERQPS XmmReg1, d_vm64x, vexVVVV_XmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x93; (XmmReg1 & YmmReg1) ... & d_vm64x { +# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now +# XmmReg1 = vgatherqps(XmmReg1, d_vm64x, vexVVVV_XmmReg); + local tmp:16 = vgatherqps(XmmReg1, vexVVVV_XmmReg); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) + vexVVVV_XmmReg = 0; +} +@endif + +# VGATHERDPS/VGATHERQPS 5-256 PAGE 2080 LINE 107140 +:VGATHERDPS YmmReg1, d_vm32y, vexVVVV_YmmReg is $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x92; YmmReg1 ... & d_vm32y { +# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now +# YmmReg1 = vgatherdps(YmmReg1, d_vm32y, vexVVVV_YmmReg); + YmmReg1 = vgatherdps(YmmReg1, vexVVVV_YmmReg); + # TODO ZmmReg1 = zext(YmmReg1) + vexVVVV_YmmReg = 0; +} + +# VGATHERDPS/VGATHERQPS 5-256 PAGE 2080 LINE 107145 +@ifdef IA64 +:VGATHERQPS XmmReg1, d_vm64y, vexVVVV_XmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x93; (XmmReg1 & YmmReg1) ... & d_vm64y { +# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now +# XmmReg1 = vgatherqps(XmmReg1, d_vm64y, vexVVVV_XmmReg); + XmmReg1 = vgatherqps(XmmReg1, vexVVVV_XmmReg); + YmmReg1 = zext(XmmReg1); + # TODO ZmmReg1 = zext(XmmReg1) + vexVVVV_XmmReg = 0; +} +@endif + +# PCMPEQQ 4-250 PAGE 1370 LINE 71171 +:VPCMPEQQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x29; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1[0,64] = zext(vexVVVV_YmmReg[0,64] == YmmReg2_m256[0,64]) * 0xffffffffffffffff:8; + YmmReg1[64,64] = zext(vexVVVV_YmmReg[64,64] == YmmReg2_m256[64,64]) * 0xffffffffffffffff:8; + YmmReg1[128,64] = zext(vexVVVV_YmmReg[128,64] == YmmReg2_m256[128,64]) * 0xffffffffffffffff:8; + YmmReg1[192,64] = zext(vexVVVV_YmmReg[192,64] == YmmReg2_m256[192,64]) * 0xffffffffffffffff:8; + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VPGATHERDD/VPGATHERQD 5-273 PAGE 2097 LINE 107884 +define pcodeop vpgatherdd ; +:VPGATHERDD XmmReg1, d_vm32x, vexVVVV_XmmReg is $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x90; (XmmReg1 & YmmReg1) ... & d_vm32x { +# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now +# XmmReg1 = vpgatherdd(XmmReg1, d_vm32x, vexVVVV_XmmReg); + local tmp:16 = vpgatherdd(XmmReg1, vexVVVV_XmmReg); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) + vexVVVV_XmmReg = 0; +} + +# VPGATHERDD/VPGATHERQD 5-273 PAGE 2097 LINE 107888 +@ifdef IA64 +define pcodeop vpgatherqd ; +:VPGATHERQD XmmReg1, d_vm64x, vexVVVV_XmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x91; (XmmReg1 & YmmReg1) ... & d_vm64x { +# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now +# XmmReg1 = vpgatherqd(XmmReg1, d_vm64x, vexVVVV_XmmReg); + local tmp:16 = vpgatherqd(XmmReg1, vexVVVV_XmmReg); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) + vexVVVV_XmmReg = 0; +} +@endif + +# VPGATHERDD/VPGATHERQD 5-273 PAGE 2097 LINE 107892 +:VPGATHERDD YmmReg1, d_vm32y, vexVVVV_YmmReg is $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x90; YmmReg1 ... & d_vm32y { +# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now +# YmmReg1 = vpgatherdd(YmmReg1, d_vm32y, vexVVVV_YmmReg); + YmmReg1 = vpgatherdd(YmmReg1, vexVVVV_YmmReg); + # TODO ZmmReg1 = zext(YmmReg1) + vexVVVV_YmmReg = 0; +} + +# VPGATHERDD/VPGATHERQD 5-273 PAGE 2097 LINE 107896 +@ifdef IA64 +:VPGATHERQD XmmReg1, d_vm64y, vexVVVV_XmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x91; (XmmReg1 & YmmReg1) ... & d_vm64y { +# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now +# XmmReg1 = vpgatherqd(XmmReg1, d_vm64y, vexVVVV_XmmReg); + local tmp:16 = vpgatherqd(XmmReg1, vexVVVV_XmmReg); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) + vexVVVV_XmmReg = 0; +} +@endif + + +# VPGATHERDQ/VPGATHERQQ 5-280 PAGE 2104 LINE 108234 +define pcodeop vpgatherdq ; +:VPGATHERDQ XmmReg1, q_vm32x, vexVVVV_XmmReg is $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x90; (XmmReg1 & YmmReg1) ... & q_vm32x { +# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now +# XmmReg1 = vpgatherdq(XmmReg1, q_vm32x, vexVVVV_XmmReg); + local tmp:16 = vpgatherdq(XmmReg1, vexVVVV_XmmReg); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) + vexVVVV_XmmReg = 0; +} + +# VPGATHERDQ/VPGATHERQQ 5-280 PAGE 2104 LINE 108238 +@ifdef IA64 +define pcodeop vpgatherqq ; +:VPGATHERQQ XmmReg1, q_vm64x, vexVVVV_XmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x91; (XmmReg1 & YmmReg1) ... & q_vm64x { +# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now +# XmmReg1 = vpgatherqq(XmmReg1, q_vm64x, vexVVVV_XmmReg); + local tmp:16 = vpgatherqq(XmmReg1, vexVVVV_XmmReg); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) + vexVVVV_XmmReg = 0; +} +@endif + +# VPGATHERDQ/VPGATHERQQ 5-280 PAGE 2104 LINE 108242 +:VPGATHERDQ YmmReg1, q_vm32x, vexVVVV_YmmReg is $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x90; YmmReg1 ... & q_vm32x { +# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now +# YmmReg1 = vpgatherdq(YmmReg1, q_vm32x, vexVVVV_YmmReg); + YmmReg1 = vpgatherdq(YmmReg1, vexVVVV_YmmReg); + # TODO ZmmReg1 = zext(YmmReg1) + vexVVVV_YmmReg = 0; +} + +# VPGATHERDQ/VPGATHERQQ 5-280 PAGE 2104 LINE 108246 +@ifdef IA64 +:VPGATHERQQ YmmReg1, q_vm64y, vexVVVV_YmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x91; YmmReg1 ... & q_vm64y { +# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now +# YmmReg1 = vpgatherqq(YmmReg1, q_vm64y, vexVVVV_YmmReg); + YmmReg1 = vpgatherqq(YmmReg1, vexVVVV_YmmReg); + # TODO ZmmReg1 = zext(YmmReg1) + vexVVVV_YmmReg = 0; +} +@endif + + +# PMOVMSKB 4-338 PAGE 1458 LINE 75655 +:VPMOVMSKB Reg32, YmmReg2 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xD7; Reg32 & (mod=0x3 & YmmReg2) & check_Reg32_dest +{ + local byte_mask:4 = 0:4; + byte_mask[0,1] = YmmReg2[7,1]; + byte_mask[1,1] = YmmReg2[15,1]; + byte_mask[2,1] = YmmReg2[23,1]; + byte_mask[3,1] = YmmReg2[31,1]; + byte_mask[4,1] = YmmReg2[39,1]; + byte_mask[5,1] = YmmReg2[47,1]; + byte_mask[6,1] = YmmReg2[55,1]; + byte_mask[7,1] = YmmReg2[63,1]; + byte_mask[8,1] = YmmReg2[71,1]; + byte_mask[9,1] = YmmReg2[79,1]; + byte_mask[10,1] = YmmReg2[87,1]; + byte_mask[11,1] = YmmReg2[95,1]; + byte_mask[12,1] = YmmReg2[103,1]; + byte_mask[13,1] = YmmReg2[111,1]; + byte_mask[14,1] = YmmReg2[119,1]; + byte_mask[15,1] = YmmReg2[127,1]; + byte_mask[16,1] = YmmReg2[135,1]; + byte_mask[17,1] = YmmReg2[143,1]; + byte_mask[18,1] = YmmReg2[151,1]; + byte_mask[19,1] = YmmReg2[159,1]; + byte_mask[20,1] = YmmReg2[167,1]; + byte_mask[21,1] = YmmReg2[175,1]; + byte_mask[22,1] = YmmReg2[183,1]; + byte_mask[23,1] = YmmReg2[191,1]; + byte_mask[24,1] = YmmReg2[199,1]; + byte_mask[25,1] = YmmReg2[207,1]; + byte_mask[26,1] = YmmReg2[215,1]; + byte_mask[27,1] = YmmReg2[223,1]; + byte_mask[28,1] = YmmReg2[231,1]; + byte_mask[29,1] = YmmReg2[239,1]; + byte_mask[30,1] = YmmReg2[247,1]; + byte_mask[31,1] = YmmReg2[255,1]; + Reg32 = zext(byte_mask); + build check_Reg32_dest; +} + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/avx_manual.sinc b/python/icicle/Ghidra/Processors/x86/data/languages/avx_manual.sinc new file mode 100644 index 0000000..2c235ab --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/avx_manual.sinc @@ -0,0 +1,287 @@ +# MOVAPD 4-45 PAGE 1165 LINE 60844 +:VMOVAPD XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x28; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + YmmReg1 = zext(XmmReg2_m128); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MOVAPD 4-45 PAGE 1165 LINE 60846 +:VMOVAPD XmmReg2, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x29; mod=3 & XmmReg1 & (XmmReg2 & YmmReg2) +{ + YmmReg2 = zext(XmmReg1); + # TODO ZmmReg2 = zext(XmmReg2) +} + +# MOVAPD 4-45 PAGE 1165 LINE 60846 +:VMOVAPD m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x29; XmmReg1 ... & m128 +{ + m128 = XmmReg1; + # TODO ZmmReg2 = zext(XmmReg2) +} + +# MOVAPD 4-45 PAGE 1165 LINE 60848 +:VMOVAPD YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x28; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = YmmReg2_m256; + # TODO ZmmReg1 = zext(YmmReg1) +} + +# MOVAPD 4-45 PAGE 1165 LINE 60850 +:VMOVAPD YmmReg2_m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x29; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg2_m256 = YmmReg1; + # TODO ZmmReg2 = zext(YmmReg2) +} + +# MOVAPS 4-49 PAGE 1169 LINE 61039 +:VMOVAPS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x28; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + YmmReg1 = zext(XmmReg2_m128); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MOVAPS 4-49 PAGE 1169 LINE 61041 +:VMOVAPS XmmReg2, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x29; mod=3 & XmmReg1 & (XmmReg2 & YmmReg2) +{ + YmmReg2 = zext(XmmReg1); + # TODO ZmmReg2 = zext(XmmReg2) +} + +# MOVAPS 4-49 PAGE 1169 LINE 61041 +:VMOVAPS m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x29; XmmReg1 ... & m128 +{ + m128 = XmmReg1; + # TODO ZmmReg2 = zext(XmmReg2) +} + +# MOVAPS 4-49 PAGE 1169 LINE 61043 +:VMOVAPS YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x28; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = YmmReg2_m256; + # TODO ZmmReg1 = zext(YmmReg1) +} + +# MOVAPS 4-49 PAGE 1169 LINE 61045 +:VMOVAPS YmmReg2_m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x29; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg2_m256 = YmmReg1; + # TODO ZmmReg2 = zext(YmmReg2) +} + +# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61667 +# Note: we do not model the exception generated if VMOVDQA is used with a memory operand which is not 16-bye aligned +:VMOVDQA XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x6F; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + YmmReg1 = zext(XmmReg2_m128); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61669 +:VMOVDQA XmmReg2, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x7F; XmmReg1 & (mod = 3 & XmmReg2 & YmmReg2) +{ + YmmReg2 = zext(XmmReg1); + # TODO ZmmReg2 = zext(XmmReg2) +} + +# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61669 +:VMOVDQA m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x7F; XmmReg1 ... & m128 +{ + m128 = XmmReg1; + # TODO ZmmReg2 = zext(XmmReg2) +} + +# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61671 +:VMOVDQA YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x6F; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = YmmReg2_m256; + # TODO ZmmReg1 = zext(YmmReg1) +} + +# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61673 +:VMOVDQA YmmReg2_m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x7F; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg2_m256 = YmmReg1; + # TODO ZmmReg2 = zext(YmmReg2) +} + +# MOVSD 4-111 PAGE 1231 LINE 63970 +:VMOVSD XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x10; XmmReg1 & YmmReg1 & (mod=0x3 & XmmReg2) +{ + local tmpa:8 = XmmReg2[0,64]; + local tmpb:8 = vexVVVV_XmmReg[64,64]; + YmmReg1 = 0; + XmmReg1[0,64] = tmpa; + XmmReg1[64,64] = tmpb; + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MOVSD 4-111 PAGE 1231 LINE 63972 +:VMOVSD XmmReg1, m64 is $(VEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0x10; (XmmReg1 & YmmReg1) ... & m64 +{ + YmmReg1[0,64] = m64; + YmmReg1[64,64] = 0; + # TODO ZmmReg1 = zext(XmmReg1) +} + +# MOVSD 4-111 PAGE 1231 LINE 63974 +:VMOVSD XmmReg2, vexVVVV_XmmReg, XmmReg1 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x11; XmmReg1 & (mod=0x3 & (XmmReg2 & YmmReg2)) +{ + local tmpa:8 = XmmReg1[0,64]; + local tmpb:8 = vexVVVV_XmmReg[64,64]; + YmmReg2 = 0; + XmmReg2[0,64] = tmpa; + XmmReg2[64,64] = tmpb; + # TODO ZmmReg2 = zext(XmmReg2) +} + +# MOVSD 4-111 PAGE 1231 LINE 63976 +:VMOVSD m64, XmmReg1 is $(VEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0x11; XmmReg1 ... & m64 +{ + m64 = XmmReg1[0,64]; +} + +# MOVUPS 4-130 PAGE 1250 LINE 64872 +:VMOVUPS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x10; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = XmmReg2_m128; + YmmReg1[0,128] = tmp; + YmmReg1[128,64] = 0; + YmmReg1[192,64] = 0; +} + +# MOVUPS 4-130 PAGE 1250 LINE 64874 +# break this into two constructors to handle the zext for the register destination case +:VMOVUPS XmmReg2, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x11; XmmReg1 & (mod = 3 & XmmReg2 & YmmReg2) +{ + XmmReg2 = XmmReg1; + YmmReg2 = zext(XmmReg2); +} + +# MOVUPS 4-130 PAGE 1250 LINE 64874 +:VMOVUPS m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x11; XmmReg1 ... & m128 +{ + m128 = XmmReg1; +} + +# MOVUPS 4-130 PAGE 1250 LINE 64876 +:VMOVUPS YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x10; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = YmmReg2_m256; + # TODO ZmmReg1 = zext(YmmReg1) +} + +# MOVUPS 4-130 PAGE 1250 LINE 64878 +# TODO in general, what do we do with the zext of only the register case; needs investigation +:VMOVUPS YmmReg2_m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x11; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg2_m256 = YmmReg1; +} + +# PCMPEQQ 4-250 PAGE 1370 LINE 71169 +:VPCMPEQQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x29; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + XmmReg1[0,64] = zext(vexVVVV_XmmReg[0,64] == XmmReg2_m128[0,64]) * 0xffffffffffffffff:8; + XmmReg1[64,64] = zext(vexVVVV_XmmReg[64,64] == XmmReg2_m128[64,64]) * 0xffffffffffffffff:8; + YmmReg1 = zext(XmmReg1); + # TODO ZmmReg1 = zext(XmmReg1) +} + + +# PMOVMSKB 4-338 PAGE 1458 LINE 75651 +:VPMOVMSKB Reg32, XmmReg2 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xD7; Reg32 & (mod=0x3 & XmmReg2) & check_Reg32_dest +{ + local byte_mask:2 = 0:2; + byte_mask[0,1] = XmmReg2[7,1]; + byte_mask[1,1] = XmmReg2[15,1]; + byte_mask[2,1] = XmmReg2[23,1]; + byte_mask[3,1] = XmmReg2[31,1]; + byte_mask[4,1] = XmmReg2[39,1]; + byte_mask[5,1] = XmmReg2[47,1]; + byte_mask[6,1] = XmmReg2[55,1]; + byte_mask[7,1] = XmmReg2[63,1]; + byte_mask[8,1] = XmmReg2[71,1]; + byte_mask[9,1] = XmmReg2[79,1]; + byte_mask[10,1] = XmmReg2[87,1]; + byte_mask[11,1] = XmmReg2[95,1]; + byte_mask[12,1] = XmmReg2[103,1]; + byte_mask[13,1] = XmmReg2[111,1]; + byte_mask[14,1] = XmmReg2[119,1]; + byte_mask[15,1] = XmmReg2[127,1]; + Reg32 = zext(byte_mask); + build check_Reg32_dest; +} + +# VZEROALL 5-563 PAGE 2387 LINE 122405 +:VZEROALL is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x77 +{ + YMM0[0,64] = 0:8; YMM0[64,64] = 0:8; YMM0[128,64] = 0:8; YMM0[192,64] = 0:8; + YMM1[0,64] = 0:8; YMM1[64,64] = 0:8; YMM1[128,64] = 0:8; YMM1[192,64] = 0:8; + YMM2[0,64] = 0:8; YMM2[64,64] = 0:8; YMM2[128,64] = 0:8; YMM2[192,64] = 0:8; + YMM3[0,64] = 0:8; YMM3[64,64] = 0:8; YMM3[128,64] = 0:8; YMM3[192,64] = 0:8; + YMM4[0,64] = 0:8; YMM4[64,64] = 0:8; YMM4[128,64] = 0:8; YMM4[192,64] = 0:8; + YMM5[0,64] = 0:8; YMM5[64,64] = 0:8; YMM5[128,64] = 0:8; YMM5[192,64] = 0:8; + YMM6[0,64] = 0:8; YMM6[64,64] = 0:8; YMM6[128,64] = 0:8; YMM6[192,64] = 0:8; + YMM7[0,64] = 0:8; YMM7[64,64] = 0:8; YMM7[128,64] = 0:8; YMM7[192,64] = 0:8; + #TODO: Zmm +} + +@ifdef IA64 +:VZEROALL is $(LONGMODE_ON) & $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x77 +{ + YMM0[0,64] = 0:8; YMM0[64,64] = 0:8; YMM0[128,64] = 0:8; YMM0[192,64] = 0:8; + YMM1[0,64] = 0:8; YMM1[64,64] = 0:8; YMM1[128,64] = 0:8; YMM1[192,64] = 0:8; + YMM2[0,64] = 0:8; YMM2[64,64] = 0:8; YMM2[128,64] = 0:8; YMM2[192,64] = 0:8; + YMM3[0,64] = 0:8; YMM3[64,64] = 0:8; YMM3[128,64] = 0:8; YMM3[192,64] = 0:8; + YMM4[0,64] = 0:8; YMM4[64,64] = 0:8; YMM4[128,64] = 0:8; YMM4[192,64] = 0:8; + YMM5[0,64] = 0:8; YMM5[64,64] = 0:8; YMM5[128,64] = 0:8; YMM5[192,64] = 0:8; + YMM6[0,64] = 0:8; YMM6[64,64] = 0:8; YMM6[128,64] = 0:8; YMM6[192,64] = 0:8; + YMM7[0,64] = 0:8; YMM7[64,64] = 0:8; YMM7[128,64] = 0:8; YMM7[192,64] = 0:8; + YMM8[0,64] = 0:8; YMM8[64,64] = 0:8; YMM8[128,64] = 0:8; YMM8[192,64] = 0:8; + YMM9[0,64] = 0:8; YMM9[64,64] = 0:8; YMM9[128,64] = 0:8; YMM9[192,64] = 0:8; + YMM10[0,64] = 0:8; YMM10[64,64] = 0:8; YMM10[128,64] = 0:8; YMM10[192,64] = 0:8; + YMM11[0,64] = 0:8; YMM11[64,64] = 0:8; YMM11[128,64] = 0:8; YMM11[192,64] = 0:8; + YMM12[0,64] = 0:8; YMM12[64,64] = 0:8; YMM12[128,64] = 0:8; YMM12[192,64] = 0:8; + YMM13[0,64] = 0:8; YMM13[64,64] = 0:8; YMM13[128,64] = 0:8; YMM13[192,64] = 0:8; + YMM14[0,64] = 0:8; YMM14[64,64] = 0:8; YMM14[128,64] = 0:8; YMM14[192,64] = 0:8; + YMM15[0,64] = 0:8; YMM15[64,64] = 0:8; YMM15[128,64] = 0:8; YMM15[192,64] = 0:8; + #TODO: Zmm +} +@endif + +# VZEROUPPER 5-565 PAGE 2389 LINE 122480 +:VZEROUPPER is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x77 +{ + YMM0[128,64] = 0:8; YMM0[192,64] = 0:8; + YMM1[128,64] = 0:8; YMM1[192,64] = 0:8; + YMM2[128,64] = 0:8; YMM2[192,64] = 0:8; + YMM3[128,64] = 0:8; YMM3[192,64] = 0:8; + YMM4[128,64] = 0:8; YMM4[192,64] = 0:8; + YMM5[128,64] = 0:8; YMM5[192,64] = 0:8; + YMM6[128,64] = 0:8; YMM6[192,64] = 0:8; + YMM7[128,64] = 0:8; YMM7[192,64] = 0:8; + #TODO: Zmm +} + +@ifdef IA64 +:VZEROUPPER is $(LONGMODE_ON) & $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x77 +{ + YMM0[128,64] = 0:8; YMM0[192,64] = 0:8; + YMM1[128,64] = 0:8; YMM1[192,64] = 0:8; + YMM2[128,64] = 0:8; YMM2[192,64] = 0:8; + YMM3[128,64] = 0:8; YMM3[192,64] = 0:8; + YMM4[128,64] = 0:8; YMM4[192,64] = 0:8; + YMM5[128,64] = 0:8; YMM5[192,64] = 0:8; + YMM6[128,64] = 0:8; YMM6[192,64] = 0:8; + YMM7[128,64] = 0:8; YMM7[192,64] = 0:8; + YMM8[128,64] = 0:8; YMM8[192,64] = 0:8; + YMM9[128,64] = 0:8; YMM9[192,64] = 0:8; + YMM10[128,64] = 0:8; YMM10[192,64] = 0:8; + YMM11[128,64] = 0:8; YMM11[192,64] = 0:8; + YMM12[128,64] = 0:8; YMM12[192,64] = 0:8; + YMM13[128,64] = 0:8; YMM13[192,64] = 0:8; + YMM14[128,64] = 0:8; YMM14[192,64] = 0:8; + YMM15[128,64] = 0:8; YMM15[192,64] = 0:8; + #TODO: Zmm +} +@endif + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/bmi1.sinc b/python/icicle/Ghidra/Processors/x86/data/languages/bmi1.sinc new file mode 100644 index 0000000..561711f --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/bmi1.sinc @@ -0,0 +1,195 @@ +macro tzcntflags(input, output) { + ZF = (output == 0); + CF = (input == 0); + # OF, SF, PF, AF are undefined +} + + +#### +#### BMI1 instructions +#### + +# TODO remove ANDN from ia.sinc ????? +:ANDN Reg32, vexVVVV_r32, rm32 is $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf2; Reg32 ... & check_Reg32_dest ... &rm32 +{ + Reg32 = ~(vexVVVV_r32) & rm32; + resultflags(Reg32); + OF = 0; + CF = 0; + build check_Reg32_dest; +} + +@ifdef IA64 +# TODO remove ANDN from ia.sinc ????? +:ANDN Reg64, vexVVVV_r64, rm64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf2; Reg64 ... & rm64 +{ + Reg64 = ~(vexVVVV_r64) & rm64; + resultflags(Reg64); + OF = 0; + CF = 0; +} +@endif + + +:BEXTR Reg32, rm32, vexVVVV_r32 is $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf7; Reg32 ... & check_Reg32_dest ... & rm32 +{ + sourceTmp:1 = vexVVVV_r32[0,8]; + lengthTmp:1 = vexVVVV_r32[8,8]; + + Reg32 = (rm32 >> sourceTmp) & ((1 << lengthTmp) - 1); + build check_Reg32_dest; + + ZF = (Reg32 == 0); + OF = 0; + CF = 0; + # AF, SF, and PF are undefined +} + +@ifdef IA64 +:BEXTR Reg64, rm64, vexVVVV_r64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf7; Reg64 ... & rm64 +{ + sourceTmp:1 = vexVVVV_r64[0,8]; + lengthTmp:1 = vexVVVV_r64[8,8]; + + Reg64 = (rm64 >> sourceTmp) & ((1 << lengthTmp) - 1); + + ZF = (Reg64 == 0); + OF = 0; + CF = 0; + # AF, SF, and PF are undefined +} +@endif + + +:BLSI vexVVVV_r32, rm32 is $(VEX_NDD) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf3; reg_opcode=3 ... & check_vexVVVV_r32_dest ... & rm32 +{ + vexVVVV_r32 = -rm32 & rm32; + build check_vexVVVV_r32_dest; + + ZF = (vexVVVV_r32 == 0); + SF = (vexVVVV_r32 s< 0); + CF = (rm32 != 0); + OF = 0; + # AF and PF are undefined +} + +@ifdef IA64 +:BLSI vexVVVV_r64, rm64 is $(LONGMODE_ON) & $(VEX_NDD) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf3; reg_opcode=3 ... & rm64 +{ + vexVVVV_r64 = -rm64 & rm64; + + ZF = (vexVVVV_r64 == 0); + SF = (vexVVVV_r64 s< 0); + CF = (rm64 != 0); + OF = 0; + # AF and PF are undefined +} +@endif + + +:BLSMSK vexVVVV_r32, rm32 is $(VEX_NDD) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf3; reg_opcode=2 ... & check_vexVVVV_r32_dest ... &rm32 +{ + CF = (rm32 == 0); + vexVVVV_r32 = (rm32 - 1) ^ rm32; + + SF = (vexVVVV_r32 s< 0); + build check_vexVVVV_r32_dest; + ZF = 0; + OF = 0; + # AF and PF are undefined +} + +@ifdef IA64 +:BLSMSK vexVVVV_r64, rm64 is $(LONGMODE_ON) & $(VEX_NDD) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf3; reg_opcode=2 ... & rm64 +{ + CF = (rm64 == 0); + vexVVVV_r64 = (rm64 - 1) ^ rm64; + + SF = (vexVVVV_r64 s< 0); + ZF = 0; + OF = 0; + # AF and PF are undefined +} +@endif + + +:BLSR vexVVVV_r32, rm32 is $(VEX_NDD) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf3; reg_opcode=1 ... & check_vexVVVV_r32_dest ... &rm32 +{ + CF = (rm32 == 0); + vexVVVV_r32 = (rm32 - 1) & rm32; + build check_vexVVVV_r32_dest; + + ZF = (vexVVVV_r32 == 0); + SF = (vexVVVV_r32 s< 0); + OF = 0; + # AF and PF are undefined +} + +@ifdef IA64 +:BLSR vexVVVV_r64, rm64 is $(LONGMODE_ON) & $(VEX_NDD) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf3; reg_opcode=1 ... & rm64 +{ + CF = (rm64 == 0); + vexVVVV_r64 = (rm64 - 1) & rm64; + + ZF = (vexVVVV_r64 == 0); + SF = (vexVVVV_r64 s< 0); + OF = 0; + # AF and PF are undefined +} +@endif + +# not as documented in manual; requires PRE_66 prefix to get 16-bit operation +:TZCNT Reg16, rm16 is vexMode=0 & opsize=0 & $(PRE_66) & $(PRE_F3) & byte=0x0F; byte=0xBC; Reg16 ... & rm16 { + + countTmp:2 = 0; + inputTmp:2 = rm16; + + + if ((inputTmp & 1) != 0) goto ; + + countTmp = countTmp + 1; + inputTmp = (inputTmp >> 1) | 0x8000; + goto ; + + + tzcntflags(rm16, countTmp); + Reg16 = countTmp; + +} + +:TZCNT Reg32, rm32 is vexMode=0 & opsize=1 & $(PRE_F3) & byte=0x0F; byte=0xBC; Reg32 ... & check_Reg32_dest ... & rm32 { + + countTmp:4 = 0; + inputTmp:4 = rm32; + + + if ((inputTmp & 1) != 0) goto ; + + countTmp = countTmp + 1; + inputTmp = (inputTmp >> 1) | 0x80000000; + goto ; + + + tzcntflags(rm32, countTmp); + Reg32 = countTmp; + build check_Reg32_dest; +} + +@ifdef IA64 +:TZCNT Reg64, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & $(REX_W) & byte=0x0F; byte=0xBC; Reg64 ... & rm64 { + + countTmp:8 = 0; + inputTmp:8 = rm64; + + + if ((inputTmp & 1) != 0) goto ; + + countTmp = countTmp + 1; + inputTmp = (inputTmp >> 1) | 0x8000000000000000; + goto ; + + + tzcntflags(rm64, countTmp); + Reg64 = countTmp; +} +@endif diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/bmi2.sinc b/python/icicle/Ghidra/Processors/x86/data/languages/bmi2.sinc new file mode 100644 index 0000000..3ac2841 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/bmi2.sinc @@ -0,0 +1,209 @@ +#### +#### BMI2 instructions +#### + + +:BZHI Reg32, rm32, vexVVVV_r32 is $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf5; Reg32 ... & check_Reg32_dest ... & rm32 +{ + indexTmp:1 = vexVVVV_r32:1; + + # saturate index amount to 32; operand size or higher does not clear any bits + shift:1 = (indexTmp <= 32) * (32 - indexTmp); + + # clear the upper bits + Reg32 = (rm32 << shift) >> shift; + build check_Reg32_dest; + + ZF = (Reg32 == 0); + SF = (Reg32 s< 0); + CF = indexTmp > 31; + OF = 0; + # AF and PF are undefined +} + +@ifdef IA64 +:BZHI Reg64, rm64, vexVVVV_r64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf5; Reg64 ... & rm64 +{ + indexTmp:1 = vexVVVV_r64:1; + + # saturate index amount to 64; operand size or higher does not clear any bits + shift:1 = (indexTmp <= 64) * (64 - indexTmp); + + # clear the upper bits + Reg64 = (rm64 << shift) >> shift; + + ZF = (Reg64 == 0); + SF = (Reg64 s< 0); + CF = indexTmp > 63; + OF = 0; + # AF and PF are undefined +} +@endif + + +:MULX Reg32, vexVVVV_r32, rm32 is $(VEX_NDD) & $(VEX_LZ) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf6; Reg32 ... & check_Reg32_dest ... & check_vexVVVV_r32_dest ... & rm32 +{ + temp:8 = zext(EDX) * zext(rm32); + + vexVVVV_r32 = temp:4; + build check_vexVVVV_r32_dest; + Reg32 = temp(4); + build check_Reg32_dest; +} + +@ifdef IA64 +:MULX Reg64, vexVVVV_r64, rm64 is $(LONGMODE_ON) & $(VEX_NDD) & $(VEX_LZ) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf6; Reg64 ... & rm64 +{ + temp:16 = zext(RDX) * zext(rm64); + + vexVVVV_r64 = temp:8; + Reg64 = temp(8); +} +@endif + + +:PDEP Reg32, vexVVVV_r32, rm32 is $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf5; Reg32 ... & check_Reg32_dest ... & rm32 +{ + sourceTmp:4 = vexVVVV_r32; + + indexTmp:4 = 1; + resultTmp:4 = 0; + + + maskBit:4 = rm32 & indexTmp; + + if (maskBit == 0) goto ; + resultTmp = resultTmp | (maskBit * (sourceTmp & 1)); + sourceTmp = sourceTmp >> 1; + + + indexTmp = indexTmp << 1; + if (indexTmp != 0) goto ; + + Reg32 = resultTmp; + build check_Reg32_dest; +} + +@ifdef IA64 +:PDEP Reg64, vexVVVV_r64, rm64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf5; Reg64 ... & rm64 +{ + sourceTmp:8 = vexVVVV_r64; + + indexTmp:8 = 1; + resultTmp:8 = 0; + + + maskBit:8 = rm64 & indexTmp; + + if (maskBit == 0) goto ; + resultTmp = resultTmp | (maskBit * (sourceTmp & 1)); + sourceTmp = sourceTmp >> 1; + + + indexTmp = indexTmp << 1; + if (indexTmp != 0) goto ; + + Reg64 = resultTmp; +} +@endif + + +:PEXT Reg32, vexVVVV_r32, rm32 is $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf5; Reg32 ... & check_Reg32_dest ... & rm32 +{ + indexTmp:4 = 0x80000000; + resultTmp:4 = 0; + + + maskBit:4 = rm32 & indexTmp; + + if (maskBit == 0) goto ; + resultTmp = (resultTmp << 1) | zext((maskBit & vexVVVV_r32) != 0); + + + indexTmp = indexTmp >> 1; + if (indexTmp != 0) goto ; + + build check_Reg32_dest; + Reg32 = resultTmp; +} + +@ifdef IA64 +:PEXT Reg64, vexVVVV_r64, rm64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf5; Reg64 ... & rm64 +{ + indexTmp:8 = 0x8000000000000000; + resultTmp:8 = 0; + + + maskBit:8 = rm64 & indexTmp; + + if (maskBit == 0) goto ; + resultTmp = (resultTmp << 1) | zext((maskBit & vexVVVV_r64) != 0); + + + indexTmp = indexTmp >> 1; + if (indexTmp != 0) goto ; + + Reg64 = resultTmp; +} +@endif + + +:RORX Reg32, rm32, imm8 is $(VEX_NONE) & $(VEX_LZ) & $(VEX_PRE_F2) & $(VEX_0F3A) & $(VEX_W0); byte=0xf0; Reg32 ... & check_Reg32_dest ... & rm32; imm8 +{ + shiftTmp:1 = (imm8:1 & 0x1F); + + Reg32 = (rm32 >> shiftTmp) | ( rm32 << (32 - shiftTmp)); + build check_Reg32_dest; +} + +@ifdef IA64 +:RORX Reg64, rm64, imm8 is $(LONGMODE_ON) & $(VEX_NONE) & $(VEX_LZ) & $(VEX_PRE_F2) & $(VEX_0F3A) & $(VEX_W1); byte=0xf0; Reg64 ... & rm64; imm8 +{ + shiftTmp:1 = (imm8:1 & 0x3F); + + Reg64 = (rm64 >> shiftTmp) | ( rm64 << (64 - shiftTmp)); +} +@endif + + +:SARX Reg32, rm32, vexVVVV_r32 is $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf7; Reg32 ... & check_Reg32_dest ... & rm32 +{ + Reg32 = rm32 s>> (vexVVVV_r32 & 0x0000001F); + build check_Reg32_dest; +} + +@ifdef IA64 +:SARX Reg64, rm64, vexVVVV_r64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf7; Reg64 ... & rm64 +{ + Reg64 = rm64 s>> (vexVVVV_r64 & 0x000000000000003F); +} +@endif + + +:SHLX Reg32, rm32, vexVVVV_r32 is $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf7; Reg32 ... & check_Reg32_dest ... & rm32 +{ + Reg32 = rm32 << (vexVVVV_r32 & 0x0000001F); + build check_Reg32_dest; +} + +@ifdef IA64 +:SHLX Reg64, rm64, vexVVVV_r64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf7; Reg64 ... & rm64 +{ + Reg64 = rm64 << (vexVVVV_r64 & 0x000000000000003F); +} +@endif + + +:SHRX Reg32, rm32, vexVVVV_r32 is $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32; byte=0xf7; Reg32 ... & check_Reg32_dest ... & rm32 +{ + Reg32 = rm32 >> (vexVVVV_r32 & 0x0000001F); + build check_Reg32_dest; +} + +@ifdef IA64 +:SHRX Reg64, rm64, vexVVVV_r64 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_LZ) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64; byte=0xf7; Reg64 ... & rm64 +{ + Reg64 = rm64 >> (vexVVVV_r64 & 0x000000000000003F); +} +@endif + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/cet.sinc b/python/icicle/Ghidra/Processors/x86/data/languages/cet.sinc new file mode 100644 index 0000000..ea707de --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/cet.sinc @@ -0,0 +1,84 @@ +# +# Instructions based on Intel Control-flow Enforcement Technology Preview +# +# Note: Shadow Stack semantics is not currently implemented correctly in these instructions +# nor in the instructions affected by CET +# + + +define pcodeop ShadowStackPush8B; +define pcodeop ShadowStackPush4B; + +define pcodeop ShadowStackLoad8B; +define pcodeop ShadowStackLoad4B; + +:INCSSPD r32 is vexMode=0 & $(PRE_F3) & (opsize=0 | opsize=1 | opsize=2 | opsize=3) & byte=0x0f; byte=0xae; reg_opcode=5 & r32 { + SSP = SSP + zext(4 * r32:1); +} +@ifdef IA64 +:INCSSPQ r64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & $(REX_W) & byte=0x0f; byte=0xae; reg_opcode=5 & r64 { + SSP = SSP + zext(8 * r64:1); +} +@endif + +:RDSSPD r32 is vexMode=0 & $(PRE_F3) & (opsize=0 | opsize=1 | opsize=2 | opsize=3) & byte=0x0f; byte=0x1e; mod=3 & reg_opcode=1 & r32 { + r32 = SSP:4; +} +@ifdef IA64 +:RDSSPQ r64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & $(REX_W) & byte=0x0f; byte=0x1e; mod=3 & reg_opcode=1 & r64 { + r64 = SSP; +} +@endif + +:SAVEPREVSSP is vexMode=0 & $(PRE_F3) & (opsize=0 | opsize=1 | opsize=2 | opsize=3) & byte=0x0f; byte=0x01; byte=0xea { + tmp:8 = SSP; + SSP = SSP & ~0x7; + ShadowStackPush8B(tmp); +} + + +:RSTORSSP m64 is vexMode=0 & $(PRE_F3) & (opsize=0 | opsize=1 | opsize=2 | opsize=3) & byte=0x0f; byte=0x01; ( mod != 0b11 & reg_opcode=5 ) ... & m64 { + tmp_SSP:8 = m64; + SSP = tmp_SSP & ~0x01; +} + +define pcodeop writeToShadowStack; +define pcodeop writeToUserShadowStack; + + +:WRSSD rm32,Reg32 is vexMode=0 & byte=0x0f; byte=0x38; byte=0xf6; rm32 & Reg32 ... { + writeToShadowStack(rm32, Reg32); +} +@ifdef IA64 +:WRSSQ rm64,Reg64 is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0f; byte=0x0f; byte=0x38; byte=0xf6; rm64 & Reg64 ... { + writeToShadowStack(rm64, Reg64); +} +@endif + +:WRUSSD rm32,Reg32 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x38; byte=0xf5; rm32 & Reg32 ... { + writeToUserShadowStack(rm32, Reg32); +} +@ifdef IA64 +:WRUSSQ rm64,Reg64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & $(REX_W) & byte=0x0f; byte=0x0f; byte=0x38; byte=0xf5; rm64 & Reg64 ... { + writeToUserShadowStack(rm64, Reg64); +} +@endif + +define pcodeop markShadowStackBusy; +define pcodeop clearShadowStackBusy; + +:SETSSBSY is vexMode=0 & $(PRE_F3) & (opsize=0 | opsize=1 | opsize=2 | opsize=3) & byte=0x0f; byte=0x01; byte=0xe8 { + SSP = markShadowStackBusy(IA32_PL0_SSP); +} + +:CLRSSBSY m64 is vexMode=0 & $(PRE_F3) & (opsize=0 | opsize=1 | opsize=2 | opsize=3) & byte=0x0f; byte=0xae; reg_opcode=6 ... & m64 { + clearShadowStackBusy(m64); + SSP=0; +} + +:ENDBR32 is vexMode=0 & $(PRE_F3) & (opsize=0 | opsize=1 | opsize=2 | opsize=3) & byte=0x0f; byte=0x1e; byte=0xfb {} +@ifdef IA64 +:ENDBR64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & (opsize=0 | opsize=1 | opsize=2 | opsize=3) & byte=0x0f; byte=0x1e; byte=0xfa {} +@endif + + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/clwb.sinc b/python/icicle/Ghidra/Processors/x86/data/languages/clwb.sinc new file mode 100644 index 0000000..72195f8 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/clwb.sinc @@ -0,0 +1,14 @@ +define pcodeop clwb; +:CLWB m8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xAE; m8 & reg_opcode=6 ... { + clwb(m8); +} + +@ifdef IA64 +define pcodeop clflushopt; +:CLFLUSHOPT m8 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xAE; m8 & reg_opcode=7 ... { + clflushopt(m8); +} +@endif + +# Note: PCOMMIT was deprecated prior to it ever being implemented in production processors. +# I never found the encoding for it. Therefore, no constructor. diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/fma.sinc b/python/icicle/Ghidra/Processors/x86/data/languages/fma.sinc new file mode 100644 index 0000000..46a9843 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/fma.sinc @@ -0,0 +1,800 @@ +# +# x86 FMA instructions +# + +# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101211 +define pcodeop vfmadd132pd_fma ; +:VFMADD132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x98; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfmadd132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101214 +define pcodeop vfmadd213pd_fma ; +:VFMADD213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA8; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfmadd213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101217 +define pcodeop vfmadd231pd_fma ; +:VFMADD231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB8; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfmadd231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101220 +:VFMADD132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x98; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfmadd132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101223 +:VFMADD213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xA8; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfmadd213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101226 +:VFMADD231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xB8; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfmadd231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101572 +define pcodeop vfmadd132ps_fma ; +:VFMADD132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x98; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfmadd132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101575 +define pcodeop vfmadd213ps_fma ; +:VFMADD213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA8; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfmadd213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101578 +define pcodeop vfmadd231ps_fma ; +:VFMADD231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB8; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfmadd231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101581 +:VFMADD132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x98; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfmadd132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101584 +:VFMADD213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xA8; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfmadd213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101587 +# WARNING: did not recognize VEX field 0 for "VFMADD231PS ymm1, ymm2, ymm3/m256" +:VFMADD231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0xB8; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfmadd231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-134 PAGE 1958 LINE 101931 +define pcodeop vfmadd132sd_fma ; +:VFMADD132SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x99; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vfmadd132sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-134 PAGE 1958 LINE 101934 +define pcodeop vfmadd213sd_fma ; +:VFMADD213SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA9; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vfmadd213sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-134 PAGE 1958 LINE 101937 +define pcodeop vfmadd231sd_fma ; +:VFMADD231SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB9; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vfmadd231sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-137 PAGE 1961 LINE 102099 +define pcodeop vfmadd132ss_fma ; +:VFMADD132SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x99; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vfmadd132ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-137 PAGE 1961 LINE 102102 +define pcodeop vfmadd213ss_fma ; +:VFMADD213SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA9; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vfmadd213ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-137 PAGE 1961 LINE 102105 +define pcodeop vfmadd231ss_fma ; +:VFMADD231SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB9; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vfmadd231ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102272 +define pcodeop vfmaddsub132pd_fma ; +:VFMADDSUB132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x96; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfmaddsub132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102275 +define pcodeop vfmaddsub213pd_fma ; +:VFMADDSUB213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA6; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfmaddsub213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102278 +define pcodeop vfmaddsub231pd_fma ; +:VFMADDSUB231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB6; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfmaddsub231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102281 +:VFMADDSUB132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x96; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfmaddsub132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102284 +:VFMADDSUB213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xA6; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfmaddsub213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102287 +:VFMADDSUB231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xB6; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfmaddsub231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102711 +define pcodeop vfmaddsub132ps_fma ; +:VFMADDSUB132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x96; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfmaddsub132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102714 +define pcodeop vfmaddsub213ps_fma ; +:VFMADDSUB213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA6; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfmaddsub213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102717 +define pcodeop vfmaddsub231ps_fma ; +:VFMADDSUB231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB6; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfmaddsub231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102720 +:VFMADDSUB132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x96; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfmaddsub132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102723 +:VFMADDSUB213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xA6; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfmaddsub213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102726 +:VFMADDSUB231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xB6; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfmaddsub231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103141 +define pcodeop vfmsubadd132pd_fma ; +:VFMSUBADD132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x97; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfmsubadd132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103144 +define pcodeop vfmsubadd213pd_fma ; +:VFMSUBADD213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA7; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfmsubadd213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103147 +define pcodeop vfmsubadd231pd_fma ; +:VFMSUBADD231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB7; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfmsubadd231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103150 +:VFMSUBADD132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x97; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfmsubadd132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103153 +:VFMSUBADD213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xA7; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfmsubadd213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103156 +:VFMSUBADD231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xB7; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfmsubadd231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103581 +define pcodeop vfmsubadd132ps_fma ; +:VFMSUBADD132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x97; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfmsubadd132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103584 +define pcodeop vfmsubadd213ps_fma ; +:VFMSUBADD213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA7; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfmsubadd213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103587 +define pcodeop vfmsubadd231ps_fma ; +:VFMSUBADD231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB7; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfmsubadd231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103590 +:VFMSUBADD132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x97; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfmsubadd132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103593 +:VFMSUBADD213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xA7; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfmsubadd213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103596 +:VFMSUBADD231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xB7; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfmsubadd231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104019 +define pcodeop vfmsub132pd_fma ; +:VFMSUB132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9A; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfmsub132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104022 +define pcodeop vfmsub213pd_fma ; +:VFMSUB213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAA; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfmsub213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104025 +define pcodeop vfmsub231pd_fma ; +:VFMSUB231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBA; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfmsub231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104028 +:VFMSUB132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x9A; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfmsub132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104031 +:VFMSUB213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xAA; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfmsub213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104034 +:VFMSUB231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xBA; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfmsub231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104379 +define pcodeop vfmsub132ps_fma ; +:VFMSUB132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9A; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfmsub132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104382 +define pcodeop vfmsub213ps_fma ; +:VFMSUB213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAA; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfmsub213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104385 +define pcodeop vfmsub231ps_fma ; +:VFMSUB231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBA; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfmsub231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104388 +:VFMSUB132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x9A; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfmsub132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104391 +:VFMSUB213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xAA; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfmsub213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104394 +# WARNING: did not recognize VEX field 0 for "VFMSUB231PS ymm1, ymm2, ymm3/m256" +:VFMSUB231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0xBA; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfmsub231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-193 PAGE 2017 LINE 104738 +define pcodeop vfmsub132sd_fma ; +:VFMSUB132SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9B; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vfmsub132sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-193 PAGE 2017 LINE 104741 +define pcodeop vfmsub213sd_fma ; +:VFMSUB213SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAB; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vfmsub213sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-193 PAGE 2017 LINE 104744 +define pcodeop vfmsub231sd_fma ; +:VFMSUB231SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBB; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vfmsub231sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-196 PAGE 2020 LINE 104913 +define pcodeop vfmsub132ss_fma ; +:VFMSUB132SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9B; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vfmsub132ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-196 PAGE 2020 LINE 104916 +define pcodeop vfmsub213ss_fma ; +:VFMSUB213SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAB; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vfmsub213ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-196 PAGE 2020 LINE 104919 +define pcodeop vfmsub231ss_fma ; +:VFMSUB231SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBB; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vfmsub231ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105088 +define pcodeop vfnmadd132pd_fma ; +:VFNMADD132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9C; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfnmadd132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105091 +define pcodeop vfnmadd213pd_fma ; +:VFNMADD213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAC; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfnmadd213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105094 +define pcodeop vfnmadd231pd_fma ; +:VFNMADD231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBC; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfnmadd231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105097 +:VFNMADD132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x9C; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfnmadd132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105100 +:VFNMADD213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xAC; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfnmadd213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105103 +:VFNMADD231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xBC; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfnmadd231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105447 +define pcodeop vfnmadd132ps_fma ; +:VFNMADD132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9C; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfnmadd132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105450 +define pcodeop vfnmadd213ps_fma ; +:VFNMADD213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAC; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfnmadd213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105453 +define pcodeop vfnmadd231ps_fma ; +:VFNMADD231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBC; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfnmadd231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105456 +:VFNMADD132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x9C; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfnmadd132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105459 +:VFNMADD213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xAC; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfnmadd213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105462 +# WARNING: did not recognize VEX field 0 for "VFNMADD231PS ymm1, ymm2, ymm3/m256" +:VFNMADD231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0xBC; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfnmadd231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-212 PAGE 2036 LINE 105794 +define pcodeop vfnmadd132sd_fma ; +:VFNMADD132SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9D; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vfnmadd132sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-212 PAGE 2036 LINE 105797 +define pcodeop vfnmadd213sd_fma ; +:VFNMADD213SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAD; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vfnmadd213sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-212 PAGE 2036 LINE 105800 +define pcodeop vfnmadd231sd_fma ; +:VFNMADD231SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBD; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vfnmadd231sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-215 PAGE 2039 LINE 105966 +define pcodeop vfnmadd132ss_fma ; +:VFNMADD132SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9D; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vfnmadd132ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-215 PAGE 2039 LINE 105969 +define pcodeop vfnmadd213ss_fma ; +:VFNMADD213SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAD; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vfnmadd213ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-215 PAGE 2039 LINE 105972 +define pcodeop vfnmadd231ss_fma ; +:VFNMADD231SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBD; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vfnmadd231ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106138 +define pcodeop vfnmsub132pd_fma ; +:VFNMSUB132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9E; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfnmsub132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106141 +define pcodeop vfnmsub213pd_fma ; +:VFNMSUB213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAE; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfnmsub213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106144 +define pcodeop vfnmsub231pd_fma ; +:VFNMSUB231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBE; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfnmsub231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106147 +:VFNMSUB132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x9E; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfnmsub132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106150 +:VFNMSUB213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xAE; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfnmsub213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106153 +:VFNMSUB231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xBE; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfnmsub231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106487 +define pcodeop vfnmsub132ps_fma ; +:VFNMSUB132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9E; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfnmsub132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106490 +define pcodeop vfnmsub213ps_fma ; +:VFNMSUB213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAE; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfnmsub213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106493 +define pcodeop vfnmsub231ps_fma ; +:VFNMSUB231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBE; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + local tmp:16 = vfnmsub231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106496 +:VFNMSUB132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x9E; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfnmsub132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106499 +:VFNMSUB213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xAE; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfnmsub213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106502 +# WARNING: did not recognize VEX field 0 for "VFNMSUB231PS ymm1, ymm2, ymm3/m256" +:VFNMSUB231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0xBE; YmmReg1 ... & YmmReg2_m256 +{ + YmmReg1 = vfnmsub231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); + # TODO ZmmReg1 = zext(YmmReg1) +} + +# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-230 PAGE 2054 LINE 106832 +define pcodeop vfnmsub132sd_fma ; +:VFNMSUB132SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9F; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vfnmsub132sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-230 PAGE 2054 LINE 106835 +define pcodeop vfnmsub213sd_fma ; +:VFNMSUB213SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAF; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vfnmsub213sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-230 PAGE 2054 LINE 106838 +define pcodeop vfnmsub231sd_fma ; +:VFNMSUB231SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBF; (XmmReg1 & YmmReg1) ... & XmmReg2_m64 +{ + local tmp:16 = vfnmsub231sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-233 PAGE 2057 LINE 107004 +define pcodeop vfnmsub132ss_fma ; +:VFNMSUB132SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9F; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vfnmsub132ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-233 PAGE 2057 LINE 107007 +define pcodeop vfnmsub213ss_fma ; +:VFNMSUB213SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAF; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vfnmsub213ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + +# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-233 PAGE 2057 LINE 107010 +define pcodeop vfnmsub231ss_fma ; +:VFNMSUB231SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBF; (XmmReg1 & YmmReg1) ... & XmmReg2_m32 +{ + local tmp:16 = vfnmsub231ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); + YmmReg1 = zext(tmp); + # TODO ZmmReg1 = zext(XmmReg1) +} + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/ia.sinc b/python/icicle/Ghidra/Processors/x86/data/languages/ia.sinc new file mode 100644 index 0000000..7a200dd --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/ia.sinc @@ -0,0 +1,9100 @@ +# SLA specification file for Intel x86 + +@ifdef IA64 +@define SIZE "8" +@define STACKPTR "RSP" +@else +@define SIZE "4" +@define STACKPTR "ESP" +@endif + +define endian=little; + +define space ram type=ram_space size=$(SIZE) default; +define space register type=register_space size=4; + +# General purpose registers + +@ifdef IA64 +define register offset=0 size=8 [ RAX RCX RDX RBX RSP RBP RSI RDI ]; +define register offset=0 size=4 [ EAX _ ECX _ EDX _ EBX _ ESP _ EBP _ ESI _ EDI ]; +define register offset=0 size=2 [ AX _ _ _ CX _ _ _ DX _ _ _ BX _ _ _ SP _ _ _ BP _ _ _ SI _ _ _ DI ]; +define register offset=0 size=1 [ AL AH _ _ _ _ _ _ CL CH _ _ _ _ _ _ DL DH _ _ _ _ _ _ BL BH _ _ _ _ _ _ SPL _ _ _ _ _ _ _ BPL _ _ _ _ _ _ _ SIL _ _ _ _ _ _ _ DIL ]; + +define register offset=0x80 size=8 [ R8 R9 R10 R11 R12 R13 R14 R15 ]; +define register offset=0x80 size=4 [ R8D _ R9D _ R10D _ R11D _ R12D _ R13D _ R14D _ R15D _ ]; +define register offset=0x80 size=2 [ R8W _ _ _ R9W _ _ _ R10W _ _ _ R11W _ _ _ R12W _ _ _ R13W _ _ _ R14W _ _ _ R15W _ _ _ ]; +define register offset=0x80 size=1 [ R8B _ _ _ _ _ _ _ R9B _ _ _ _ _ _ _ R10B _ _ _ _ _ _ _ R11B _ _ _ _ _ _ _ R12B _ _ _ _ _ _ _ R13B _ _ _ _ _ _ _ R14B _ _ _ _ _ _ _ R15B _ _ _ _ _ _ _ ]; +@else +define register offset=0 size=4 [ EAX ECX EDX EBX ESP EBP ESI EDI ]; +define register offset=0 size=2 [ AX _ CX _ DX _ BX _ SP _ BP _ SI _ DI ]; +define register offset=0 size=1 [ AL AH _ _ CL CH _ _ DL DH _ _ BL BH ]; +@endif + +# Segment registers +define register offset=0x100 size=2 [ ES CS SS DS FS GS ]; +define register offset=0x110 size=$(SIZE) [ FS_OFFSET GS_OFFSET ]; + +# Flags +define register offset=0x200 size=1 [ CF F1 PF F3 AF F5 ZF SF + TF IF DF OF IOPL NT F15 + RF VM AC VIF VIP ID ]; +@ifdef IA64 +define register offset=0x280 size=8 [ rflags RIP ]; +define register offset=0x280 size=4 [ eflags _ EIP _ ]; +define register offset=0x280 size=2 [ flags _ _ _ IP _ _ _]; +@else +define register offset=0x280 size=4 [ eflags EIP] ; +define register offset=0x280 size=2 [ flags _ IP] ; +@endif + +# Debug and control registers + +@ifdef IA64 +define register offset=0x300 size=8 [ DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7 + DR8 DR9 DR10 DR11 DR12 DR13 DR14 DR15 + CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 + CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15 ]; +@else +define register offset=0x300 size=4 [ DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7 + CR0 _ CR2 CR3 CR4 ]; +define register offset=0x400 size=4 [ TR0 TR1 TR2 TR3 TR4 TR5 TR6 TR7 ]; +@endif + +#Processor State Register - currently only XFEATURE_ENABLED_MASK=XCR0 is defined +# +define register offset=0x600 size=8 [ XCR0 ]; + +# Memory Protection Extensions (MPX) +define register offset=0x700 size=8 [ BNDCFGS BNDCFGU BNDSTATUS ]; + +define register offset=0x740 size=16 [ BND0 BND1 BND2 BND3 _ _ _ _ ]; +define register offset=0x740 size=8 [ BND0_LB BND0_UB BND1_LB BND1_UB BND2_LB BND2_UB BND3_LB BND3_UB _ _ _ _ _ _ _ _ ]; + +# Control Flow Extensions +define register offset=0x7c0 size=8 [ SSP IA32_PL2_SSP IA32_PL1_SSP IA32_PL0_SSP ]; + +# Floating point registers - as they are in 32-bit protected mode +# See MMx registers below +define register offset=0x1106 size=10 [ ST0 ]; +define register offset=0x1116 size=10 [ ST1 ]; +define register offset=0x1126 size=10 [ ST2 ]; +define register offset=0x1136 size=10 [ ST3 ]; +define register offset=0x1146 size=10 [ ST4 ]; +define register offset=0x1156 size=10 [ ST5 ]; +define register offset=0x1166 size=10 [ ST6 ]; +define register offset=0x1176 size=10 [ ST7 ]; +define register offset=0x1090 size=1 [ C0 C1 C2 C3 ]; +define register offset=0x1094 size=4 [ MXCSR ]; +define register offset=0x10a0 size=2 [ FPUControlWord FPUStatusWord FPUTagWord + FPULastInstructionOpcode ]; +define register offset=0x10a8 size=$(SIZE) [ FPUDataPointer FPUInstructionPointer ]; +define register offset=0x10c8 size=2 [ FPUPointerSelector FPUDataSelector]; #FCS FDS + + # FCS is not modeled, deprecated as 0. + # FDS not modeled, deprecated as 0. + +# +# YMM0 - YMM7 - available in 32 bit mode +# YMM0 - YMM15 - available in 64 bit mode +# +define register offset=0x1100 size=8 [ _ MM0 _ MM1 _ MM2 _ MM3 _ MM4 _ MM5 _ MM6 _ MM7 ]; +define register offset=0x1100 size=4 [ + _ _ MM0_Da MM0_Db + _ _ MM1_Da MM1_Db + _ _ MM2_Da MM2_Db + _ _ MM3_Da MM3_Db + _ _ MM4_Da MM4_Db + _ _ MM5_Da MM5_Db + _ _ MM6_Da MM6_Db + _ _ MM7_Da MM7_Db +]; +define register offset=0x1100 size=2 [ + _ _ _ _ MM0_Wa MM0_Wb MM0_Wc MM0_Wd + _ _ _ _ MM1_Wa MM1_Wb MM1_Wc MM1_Wd + _ _ _ _ MM2_Wa MM2_Wb MM2_Wc MM2_Wd + _ _ _ _ MM3_Wa MM3_Wb MM3_Wc MM3_Wd + _ _ _ _ MM4_Wa MM4_Wb MM4_Wc MM4_Wd + _ _ _ _ MM5_Wa MM5_Wb MM5_Wc MM5_Wd + _ _ _ _ MM6_Wa MM6_Wb MM6_Wc MM6_Wd + _ _ _ _ MM7_Wa MM7_Wb MM7_Wc MM7_Wd +]; +define register offset=0x1100 size=1 [ + _ _ _ _ _ _ _ _ + MM0_Ba MM0_Bb MM0_Bc MM0_Bd MM0_Be MM0_Bf MM0_Bg MM0_Bh + _ _ _ _ _ _ _ _ + MM1_Ba MM1_Bb MM1_Bc MM1_Bd MM1_Be MM1_Bf MM1_Bg MM1_Bh + _ _ _ _ _ _ _ _ + MM2_Ba MM2_Bb MM2_Bc MM2_Bd MM2_Be MM2_Bf MM2_Bg MM2_Bh + _ _ _ _ _ _ _ _ + MM3_Ba MM3_Bb MM3_Bc MM3_Bd MM3_Be MM3_Bf MM3_Bg MM3_Bh + _ _ _ _ _ _ _ _ + MM4_Ba MM4_Bb MM4_Bc MM4_Bd MM4_Be MM4_Bf MM4_Bg MM4_Bh + _ _ _ _ _ _ _ _ + MM5_Ba MM5_Bb MM5_Bc MM5_Bd MM5_Be MM5_Bf MM5_Bg MM5_Bh + _ _ _ _ _ _ _ _ + MM6_Ba MM6_Bb MM6_Bc MM6_Bd MM6_Be MM6_Bf MM6_Bg MM6_Bh + _ _ _ _ _ _ _ _ + MM7_Ba MM7_Bb MM7_Bc MM7_Bd MM7_Be MM7_Bf MM7_Bg MM7_Bh +]; + + +# YMMx_H is the formal name for the high double quadword of the YMMx register, XMMx is the overlay in the XMM register set +define register offset=0x1200 size=16 [ + XMM0 YMM0_H + XMM1 YMM1_H + XMM2 YMM2_H + XMM3 YMM3_H + XMM4 YMM4_H + XMM5 YMM5_H + XMM6 YMM6_H + XMM7 YMM7_H + XMM8 YMM8_H + XMM9 YMM9_H + XMM10 YMM10_H + XMM11 YMM11_H + XMM12 YMM12_H + XMM13 YMM13_H + XMM14 YMM14_H + XMM15 YMM15_H +]; + +define register offset=0x1200 size=8 [ + XMM0_Qa XMM0_Qb _ _ + XMM1_Qa XMM1_Qb _ _ + XMM2_Qa XMM2_Qb _ _ + XMM3_Qa XMM3_Qb _ _ + XMM4_Qa XMM4_Qb _ _ + XMM5_Qa XMM5_Qb _ _ + XMM6_Qa XMM6_Qb _ _ + XMM7_Qa XMM7_Qb _ _ + XMM8_Qa XMM8_Qb _ _ + XMM9_Qa XMM9_Qb _ _ + XMM10_Qa XMM10_Qb _ _ + XMM11_Qa XMM11_Qb _ _ + XMM12_Qa XMM12_Qb _ _ + XMM13_Qa XMM13_Qb _ _ + XMM14_Qa XMM14_Qb _ _ + XMM15_Qa XMM15_Qb _ _ +]; +define register offset=0x1200 size=4 [ + XMM0_Da XMM0_Db XMM0_Dc XMM0_Dd _ _ _ _ + XMM1_Da XMM1_Db XMM1_Dc XMM1_Dd _ _ _ _ + XMM2_Da XMM2_Db XMM2_Dc XMM2_Dd _ _ _ _ + XMM3_Da XMM3_Db XMM3_Dc XMM3_Dd _ _ _ _ + XMM4_Da XMM4_Db XMM4_Dc XMM4_Dd _ _ _ _ + XMM5_Da XMM5_Db XMM5_Dc XMM5_Dd _ _ _ _ + XMM6_Da XMM6_Db XMM6_Dc XMM6_Dd _ _ _ _ + XMM7_Da XMM7_Db XMM7_Dc XMM7_Dd _ _ _ _ + XMM8_Da XMM8_Db XMM8_Dc XMM8_Dd _ _ _ _ + XMM9_Da XMM9_Db XMM9_Dc XMM9_Dd _ _ _ _ + XMM10_Da XMM10_Db XMM10_Dc XMM10_Dd _ _ _ _ + XMM11_Da XMM11_Db XMM11_Dc XMM11_Dd _ _ _ _ + XMM12_Da XMM12_Db XMM12_Dc XMM12_Dd _ _ _ _ + XMM13_Da XMM13_Db XMM13_Dc XMM13_Dd _ _ _ _ + XMM14_Da XMM14_Db XMM14_Dc XMM14_Dd _ _ _ _ + XMM15_Da XMM15_Db XMM15_Dc XMM15_Dd _ _ _ _ +]; +define register offset=0x1200 size=2 [ + XMM0_Wa XMM0_Wb XMM0_Wc XMM0_Wd XMM0_We XMM0_Wf XMM0_Wg XMM0_Wh _ _ _ _ _ _ _ _ + XMM1_Wa XMM1_Wb XMM1_Wc XMM1_Wd XMM1_We XMM1_Wf XMM1_Wg XMM1_Wh _ _ _ _ _ _ _ _ + XMM2_Wa XMM2_Wb XMM2_Wc XMM2_Wd XMM2_We XMM2_Wf XMM2_Wg XMM2_Wh _ _ _ _ _ _ _ _ + XMM3_Wa XMM3_Wb XMM3_Wc XMM3_Wd XMM3_We XMM3_Wf XMM3_Wg XMM3_Wh _ _ _ _ _ _ _ _ + XMM4_Wa XMM4_Wb XMM4_Wc XMM4_Wd XMM4_We XMM4_Wf XMM4_Wg XMM4_Wh _ _ _ _ _ _ _ _ + XMM5_Wa XMM5_Wb XMM5_Wc XMM5_Wd XMM5_We XMM5_Wf XMM5_Wg XMM5_Wh _ _ _ _ _ _ _ _ + XMM6_Wa XMM6_Wb XMM6_Wc XMM6_Wd XMM6_We XMM6_Wf XMM6_Wg XMM6_Wh _ _ _ _ _ _ _ _ + XMM7_Wa XMM7_Wb XMM7_Wc XMM7_Wd XMM7_We XMM7_Wf XMM7_Wg XMM7_Wh _ _ _ _ _ _ _ _ + XMM8_Wa XMM8_Wb XMM8_Wc XMM8_Wd XMM8_We XMM8_Wf XMM8_Wg XMM8_Wh _ _ _ _ _ _ _ _ + XMM9_Wa XMM9_Wb XMM9_Wc XMM9_Wd XMM9_We XMM9_Wf XMM9_Wg XMM9_Wh _ _ _ _ _ _ _ _ + XMM10_Wa XMM10_Wb XMM10_Wc XMM10_Wd XMM10_We XMM10_Wf XMM10_Wg XMM10_Wh _ _ _ _ _ _ _ _ + XMM11_Wa XMM11_Wb XMM11_Wc XMM11_Wd XMM11_We XMM11_Wf XMM11_Wg XMM11_Wh _ _ _ _ _ _ _ _ + XMM12_Wa XMM12_Wb XMM12_Wc XMM12_Wd XMM12_We XMM12_Wf XMM12_Wg XMM12_Wh _ _ _ _ _ _ _ _ + XMM13_Wa XMM13_Wb XMM13_Wc XMM13_Wd XMM13_We XMM13_Wf XMM13_Wg XMM13_Wh _ _ _ _ _ _ _ _ + XMM14_Wa XMM14_Wb XMM14_Wc XMM14_Wd XMM14_We XMM14_Wf XMM14_Wg XMM14_Wh _ _ _ _ _ _ _ _ + XMM15_Wa XMM15_Wb XMM15_Wc XMM15_Wd XMM15_We XMM15_Wf XMM15_Wg XMM15_Wh _ _ _ _ _ _ _ _ +]; +define register offset=0x1200 size=1 [ + XMM0_Ba XMM0_Bb XMM0_Bc XMM0_Bd XMM0_Be XMM0_Bf XMM0_Bg XMM0_Bh XMM0_Bi XMM0_Bj XMM0_Bk XMM0_Bl XMM0_Bm XMM0_Bn XMM0_Bo XMM0_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + XMM1_Ba XMM1_Bb XMM1_Bc XMM1_Bd XMM1_Be XMM1_Bf XMM1_Bg XMM1_Bh XMM1_Bi XMM1_Bj XMM1_Bk XMM1_Bl XMM1_Bm XMM1_Bn XMM1_Bo XMM1_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + XMM2_Ba XMM2_Bb XMM2_Bc XMM2_Bd XMM2_Be XMM2_Bf XMM2_Bg XMM2_Bh XMM2_Bi XMM2_Bj XMM2_Bk XMM2_Bl XMM2_Bm XMM2_Bn XMM2_Bo XMM2_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + XMM3_Ba XMM3_Bb XMM3_Bc XMM3_Bd XMM3_Be XMM3_Bf XMM3_Bg XMM3_Bh XMM3_Bi XMM3_Bj XMM3_Bk XMM3_Bl XMM3_Bm XMM3_Bn XMM3_Bo XMM3_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + XMM4_Ba XMM4_Bb XMM4_Bc XMM4_Bd XMM4_Be XMM4_Bf XMM4_Bg XMM4_Bh XMM4_Bi XMM4_Bj XMM4_Bk XMM4_Bl XMM4_Bm XMM4_Bn XMM4_Bo XMM4_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + XMM5_Ba XMM5_Bb XMM5_Bc XMM5_Bd XMM5_Be XMM5_Bf XMM5_Bg XMM5_Bh XMM5_Bi XMM5_Bj XMM5_Bk XMM5_Bl XMM5_Bm XMM5_Bn XMM5_Bo XMM5_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + XMM6_Ba XMM6_Bb XMM6_Bc XMM6_Bd XMM6_Be XMM6_Bf XMM6_Bg XMM6_Bh XMM6_Bi XMM6_Bj XMM6_Bk XMM6_Bl XMM6_Bm XMM6_Bn XMM6_Bo XMM6_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + XMM7_Ba XMM7_Bb XMM7_Bc XMM7_Bd XMM7_Be XMM7_Bf XMM7_Bg XMM7_Bh XMM7_Bi XMM7_Bj XMM7_Bk XMM7_Bl XMM7_Bm XMM7_Bn XMM7_Bo XMM7_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + XMM8_Ba XMM8_Bb XMM8_Bc XMM8_Bd XMM8_Be XMM8_Bf XMM8_Bg XMM8_Bh XMM8_Bi XMM8_Bj XMM8_Bk XMM8_Bl XMM8_Bm XMM8_Bn XMM8_Bo XMM8_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + XMM9_Ba XMM9_Bb XMM9_Bc XMM9_Bd XMM9_Be XMM9_Bf XMM9_Bg XMM9_Bh XMM9_Bi XMM9_Bj XMM9_Bk XMM9_Bl XMM9_Bm XMM9_Bn XMM9_Bo XMM9_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + XMM10_Ba XMM10_Bb XMM10_Bc XMM10_Bd XMM10_Be XMM10_Bf XMM10_Bg XMM10_Bh XMM10_Bi XMM10_Bj XMM10_Bk XMM10_Bl XMM10_Bm XMM10_Bn XMM10_Bo XMM10_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + XMM11_Ba XMM11_Bb XMM11_Bc XMM11_Bd XMM11_Be XMM11_Bf XMM11_Bg XMM11_Bh XMM11_Bi XMM11_Bj XMM11_Bk XMM11_Bl XMM11_Bm XMM11_Bn XMM11_Bo XMM11_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + XMM12_Ba XMM12_Bb XMM12_Bc XMM12_Bd XMM12_Be XMM12_Bf XMM12_Bg XMM12_Bh XMM12_Bi XMM12_Bj XMM12_Bk XMM12_Bl XMM12_Bm XMM12_Bn XMM12_Bo XMM12_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + XMM13_Ba XMM13_Bb XMM13_Bc XMM13_Bd XMM13_Be XMM13_Bf XMM13_Bg XMM13_Bh XMM13_Bi XMM13_Bj XMM13_Bk XMM13_Bl XMM13_Bm XMM13_Bn XMM13_Bo XMM13_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + XMM14_Ba XMM14_Bb XMM14_Bc XMM14_Bd XMM14_Be XMM14_Bf XMM14_Bg XMM14_Bh XMM14_Bi XMM14_Bj XMM14_Bk XMM14_Bl XMM14_Bm XMM14_Bn XMM14_Bo XMM14_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + XMM15_Ba XMM15_Bb XMM15_Bc XMM15_Bd XMM15_Be XMM15_Bf XMM15_Bg XMM15_Bh XMM15_Bi XMM15_Bj XMM15_Bk XMM15_Bl XMM15_Bm XMM15_Bn XMM15_Bo XMM15_Bp _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ +]; +define register offset=0x1200 size=32 [ YMM0 YMM1 YMM2 YMM3 YMM4 YMM5 YMM6 YMM7 YMM8 YMM9 YMM10 YMM11 YMM12 YMM13 YMM14 YMM15 ]; + +# 0x1400 is next spot +define register offset=0x1400 size=16 [ xmmTmp1 xmmTmp2 ]; +define register offset=0x1400 size=8 [ + xmmTmp1_Qa xmmTmp1_Qb + xmmTmp2_Qa xmmTmp2_Qb +]; +define register offset=0x1400 size=4 [ + xmmTmp1_Da xmmTmp1_Db xmmTmp1_Dc xmmTmp1_Dd + xmmTmp2_Da xmmTmp2_Db xmmTmp2_Dc xmmTmp2_Dd +]; + +# Define context bits +define register offset=0x2000 size=8 contextreg; + +# +# +# This context layout is important: the 32 bit version sees addrsize as just the +# low-order bit, whereas the 64 bit sees both bits. This ensures that the 32 and 64 +# are technically binary compatible, but since the 32 bit language can't see that +# addrsize is 2 bits, they won't be pulled up into constructors where bit 0 is always +# 0 (which it is), and then you don't get the decision conflicts that choose +# context over table order +# +# + +define context contextreg +@ifdef IA64 + # Stored context + longMode=(0,0) # 0 for 32-bit emulation, 1 for 64-bit mode + reserved=(1,3) + addrsize=(4,5) # =0 16-bit addressing =1 32-bit addressing =2 64-bit addressing +@else + # Stored context + reserved=(0,3) + addrsize=(5,5) # =0 16-bit addressing =1 32-bit addressing +@endif + bit64=(4,4) # =0 16/32 bit =1 64-bit + opsize=(6,7) # =0 16-bit operands =1 32-bit operands =2 64-bit operands + segover=(8,10) # 0=default 1=cs 2=ss 3=ds 4=es 5=fs 6=gs + highseg=(8,8) # high bit of segover will be set for ES, FS, GS + protectedMode=(11,11) # 0 for real mode, 1 for protected mode + # End stored context + + repneprefx=(12,12) # 0xf2 REPNE prefix + repprefx=(13,13) # 0xf3 REP prefix + xacquireprefx=(12,12) # 0xf2 XACQUIRE prefix + xreleaseprefx=(13,13) # 0xf3 XRELEASE prefix + prefix_66=(14,14) # This is not really a OPSIZE override, it means there is an real(read)/implied(vex) 66 byte + prefix_f3=(13,13) # This is not really a REP override, it means there is an real(read)/implied(vex) f3 byte + prefix_f2=(12,12) # This is not really a REPNE override, it means there is a real(read)/implied(vex) f2 byte + mandover=(12,14) # 0x66 0xf2 or 0xf3 overrides (for mandatory prefixes) + + rexWprefix=(15,15) # REX.W bit prefix (opsize=2 when REX.W is set) + rexRprefix=(16,16) # REX.R bit prefix extend r + rexXprefix=(17,17) # REX.X bit prefix extend SIB index field to 4 bits + rexBprefix=(18,18) # REX.B bit prefix extend r/m, SIB base, Reg operand + rexWRXBprefix=(15,18) # REX.WRXB bits + rexprefix=(19,19) # True if the Rex prefix is present - note, if present, vex_mode is not supported + # rexWRXB bits can be re-used since they are incompatible. + vexMode=(20,20) # 1 for vex instruction, 0 for normal + vexL=(21,21) # 0 for 128, 1 for 256 + vexVVVV=(22,25) # value of vex byte for matching + vexVVVV_r32=(22,25) # value of vex byte for matching a normal 32 bit register + vexVVVV_r64=(22,25) # value of vex byte for matching a normal 64 bit register + vexVVVV_XmmReg=(22,25) # value of vex byte for matching XmmReg + vexVVVV_YmmReg=(22,25) # value of vex byte for matching YmmReg + vexMMMMM=(26,30) # need to match for preceding bytes 1=0x0F, 2=0x0F 0x38, 3=0x0F 0x3A + + suffix3D=(21,28) # 3DNow suffix byte (overlaps un-modified vex context region) + instrPhase=(31,31) # 0: initial/prefix phase, 1: primary instruction phase + + lockprefx=(32,32) # 0xf0 LOCK prefix +; + + +# These are only to be used with pre-REX (original 8086, 80386) and REX encoding. Do not use with VEX encoding. +# These are to be used to designate that the opcode sequence begins with one of these "mandatory" prefix values. +# This allows the other prefixes to come before the mandatory value. +# For example: CRC32 r32, r16 -- 66 F2 OF 38 F1 C8 + +@define PRE_NO "mandover=0" +@define PRE_66 "prefix_66=1" +@define PRE_F3 "prefix_f3=1" +@define PRE_F2 "prefix_f2=1" + + + +# Define special registers for debugger +@ifdef IA64 +define register offset=0x2200 size=4 [ IDTR_Limit ]; +define register offset=0x2200 size=12 [ IDTR ]; +define register offset=0x2204 size=8 [ IDTR_Address ]; + +define register offset=0x2220 size=4 [ GDTR_Limit ]; +define register offset=0x2220 size=12 [ GDTR ]; +define register offset=0x2224 size=8 [ GDTR_Address ]; + +define register offset=0x2240 size=4 [ LDTR_Limit ]; +define register offset=0x2240 size=14 [ LDTR ]; +define register offset=0x2244 size=8 [ LDTR_Address ]; +define register offset=0x2248 size=2 [ LDTR_Attributes ]; + +define register offset=0x2260 size=4 [ TR_Limit ]; +define register offset=0x2260 size=14 [ TR ]; +define register offset=0x2264 size=8 [ TR_Address ]; +define register offset=0x2268 size=2 [ TR_Attributes ]; +@else +define register offset=0x2200 size=6 [ IDTR ]; +define register offset=0x2200 size=2 [ IDTR_Limit ]; +define register offset=0x2202 size=4 [ IDTR_Address ]; + +define register offset=0x2210 size=6 [ GDTR ]; +define register offset=0x2210 size=2 [ GDTR_Limit ]; +define register offset=0x2212 size=4 [ GDTR_Address ]; + +define register offset=0x2220 size=6 [ LDTR ]; +define register offset=0x2220 size=2 [ LDTR_Limit ]; +define register offset=0x2222 size=4 [ LDTR_Address ]; + +define register offset=0x2230 size=6 [ TR ]; +define register offset=0x2230 size=2 [ TR_Limit ]; +define register offset=0x2232 size=4 [ TR_Address ]; +@endif + +define token opbyte (8) + byte=(0,7) + high4=(4,7) + high5=(3,7) + low5=(0,4) + byte_4=(4,4) + byte_0=(0,0) +; + +define token modrm (8) + mod = (6,7) + reg_opcode = (3,5) + reg_opcode_hb = (5,5) + r_m = (0,2) + row = (4,7) + col = (0,2) + page = (3,3) + cond = (0,3) + reg8 = (3,5) + reg16 = (3,5) + reg32 = (3,5) + reg64 = (3,5) + reg8_x0 = (3,5) + reg8_x1 = (3,5) + reg16_x = (3,5) + reg32_x = (3,5) + reg64_x = (3,5) + Sreg = (3,5) + creg = (3,5) + creg_x = (3,5) + debugreg = (3,5) + debugreg_x = (3,5) + testreg = (3,5) + r8 = (0,2) + r16 = (0,2) + r32 = (0,2) + r64 = (0,2) + r8_x0 = (0,2) + r8_x1 = (0,2) + r16_x = (0,2) + r32_x = (0,2) + r64_x = (0,2) + frow = (4,7) + fpage = (3,3) + freg = (0,2) + rexw = (3,3) + rexr = (2,2) + rexx = (1,1) + rexb = (0,0) + mmxmod = (6,7) + mmxreg = (3,5) + mmxreg1 = (3,5) + mmxreg2 = (0,2) + xmmmod = (6,7) + xmmreg = (3,5) + ymmreg = (3,5) + + xmmreg1 = (3,5) + ymmreg1 = (3,5) + xmmreg2 = (0,2) + ymmreg2 = (0,2) + + xmmreg_x = (3,5) + ymmreg_x = (3,5) + xmmreg1_x = (3,5) + ymmreg1_x = (3,5) + xmmreg2_x = (0,2) + ymmreg2_x = (0,2) + vex_pp = (0,1) + vex_l = (2,2) + vex_vvvv = (3,6) + vex_r = (7,7) + vex_x = (6,6) + vex_b = (5,5) + vex_w = (7,7) + vex_mmmmm = (0,4) + bnd1 = (3,5) + bnd1_lb = (3,5) + bnd1_ub = (3,5) + bnd2 = (0,2) + bnd2_lb = (0,2) + bnd2_ub = (0,2) +; + +define token sib (8) + ss = (6,7) + index = (3,5) + index_x = (3,5) + index64 = (3,5) + index64_x = (3,5) + xmm_vsib = (3,5) + xmm_vsib_x = (3,5) + ymm_vsib = (3,5) + ymm_vsib_x = (3,5) + base = (0,2) + base_x = (0,2) + base64 = (0,2) + base64_x = (0,2) +; + +define token I8 (8) + imm8_7=(7,7) + Xmm_imm8_7_4=(4,7) + Ymm_imm8_7_4=(4,7) + imm8_4=(4,4) + imm8_0=(0,0) + imm8_3_0=(0,3) + imm8=(0,7) + simm8=(0,7) signed +; + +define token I16 (16) imm16_15=(15,15) imm16=(0,15) simm16=(0,15) signed j16=(0,15); +define token I32 (32) imm32=(0,31) simm32=(0,31) signed; +define token I64 (64) imm64=(0,63) simm64=(0,63) signed; +define token override (8) over=(0,7); + +attach variables [ r32 reg32 base index ] [ EAX ECX EDX EBX ESP EBP ESI EDI ]; +attach variables [ r16 reg16 ] [ AX CX DX BX SP BP SI DI ]; +attach variables [ r8 reg8 ] [ AL CL DL BL AH CH DH BH ]; +attach variables Sreg [ ES CS SS DS FS GS _ _ ]; +attach variables freg [ ST0 ST1 ST2 ST3 ST4 ST5 ST6 ST7 ]; +attach variables [ debugreg ] [ DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7 ]; +@ifdef IA64 +attach variables [ r64 reg64 base64 index64 ] [ RAX RCX RDX RBX RSP RBP RSI RDI ]; +attach variables [ r64_x reg64_x base64_x index64_x ] [ R8 R9 R10 R11 R12 R13 R14 R15 ]; +attach variables [ r32_x reg32_x base_x index_x ] [ R8D R9D R10D R11D R12D R13D R14D R15D ]; +attach variables [ r16_x reg16_x ] [ R8W R9W R10W R11W R12W R13W R14W R15W ]; +attach variables [ r8_x0 reg8_x0 ] [ AL CL DL BL SPL BPL SIL DIL ]; +attach variables [ r8_x1 reg8_x1 ] [ R8B R9B R10B R11B R12B R13B R14B R15B ]; +attach variables [ debugreg_x ] [ DR8 DR9 DR10 DR11 DR12 DR13 DR14 DR15 ]; +attach variables creg [ CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 ]; +attach variables creg_x [ CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15 ]; +@else +attach variables [ testreg ] [ TR0 TR1 TR2 TR3 TR6 TR7 TR6 TR7 ]; +attach variables creg [ CR0 _ CR2 CR3 CR4 _ _ _ ]; +@endif + +attach values ss [ 1 2 4 8]; + +attach variables [ mmxreg mmxreg1 mmxreg2 ] [ MM0 MM1 MM2 MM3 MM4 MM5 MM6 MM7 ]; + +attach variables [ xmmreg xmmreg1 xmmreg2 xmm_vsib ] [ XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 ]; + +attach variables [ xmmreg_x xmmreg1_x xmmreg2_x xmm_vsib_x ] [ XMM8 XMM9 XMM10 XMM11 XMM12 XMM13 XMM14 XMM15 ]; + +attach variables [ vexVVVV_XmmReg Xmm_imm8_7_4 ] [ XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 XMM9 XMM10 XMM11 XMM12 XMM13 XMM14 XMM15 ]; + +attach variables [ vexVVVV_YmmReg Ymm_imm8_7_4 ] [ YMM0 YMM1 YMM2 YMM3 YMM4 YMM5 YMM6 YMM7 YMM8 YMM9 YMM10 YMM11 YMM12 YMM13 YMM14 YMM15 ]; + +@ifdef IA64 +attach variables [ vexVVVV_r32 ] [ EAX ECX EDX EBX ESP EBP ESI EDI R8D R9D R10D R11D R12D R13D R14D R15D ]; +attach variables [ vexVVVV_r64 ] [ RAX RCX RDX RBX RSP RBP RSI RDI R8 R9 R10 R11 R12 R13 R14 R15 ]; +@else +attach variables [ vexVVVV_r32 ] [ EAX ECX EDX EBX ESP EBP ESI EDI _ _ _ _ _ _ _ _ ]; +@endif + + +attach variables [ ymmreg ymmreg1 ymmreg2 ymm_vsib ] [ YMM0 YMM1 YMM2 YMM3 YMM4 YMM5 YMM6 YMM7 ]; +attach variables [ ymmreg_x ymmreg1_x ymmreg2_x ymm_vsib_x ] [ YMM8 YMM9 YMM10 YMM11 YMM12 YMM13 YMM14 YMM15 ]; + +attach variables [ bnd1 bnd2 ] [ BND0 BND1 BND2 BND3 _ _ _ _ ]; +attach variables [ bnd1_lb bnd2_lb ] [ BND0_LB BND1_LB BND2_LB BND3_LB _ _ _ _ ]; +attach variables [ bnd1_ub bnd2_ub ] [ BND0_UB BND1_UB BND2_UB BND3_UB _ _ _ _ ]; + +define pcodeop segment; # Define special pcodeop that calculates the RAM address + # given the segment selector and offset as input + +define pcodeop in; # force in/out to show up in decompiler +define pcodeop out; +define pcodeop sysenter; +define pcodeop sysexit; +define pcodeop syscall; +define pcodeop sysret; +define pcodeop swapgs; +define pcodeop invlpg; +define pcodeop invlpga; +define pcodeop invpcid; +define pcodeop rdtscp; +define pcodeop mwait; +define pcodeop mwaitx; +define pcodeop monitor; +define pcodeop monitorx; +define pcodeop swi; # for INT instruction + +define pcodeop LOCK; # for LOCK prefix +define pcodeop UNLOCK; # for LOCK prefix +define pcodeop XACQUIRE; # for XACQUIRE prefix +define pcodeop XRELEASE; # for XRELEASE prefix + +# MFL: definitions for AMD hardware assisted virtualization instructions +define pcodeop clgi; # clear global interrupt flag (GIF) +define pcodeop stgi; # set global interrupt flag (GIF) +define pcodeop vmload; # Load state from VMCD, opcode 0f 01 da +define pcodeop vmmcall; # Call VMM, opcode 0f 01 d9 +define pcodeop vmrun; # Run virtual machine, opcode 0f 01 d8 +define pcodeop vmsave; # Save state to VMCB, opcode 0f 0a db + +# MFL: definitions for Intel IA hardware assisted virtualization instructions +define pcodeop invept; # Invalidate Translations Derived from extended page tables (EPT); opcode 66 0f 38 80 +define pcodeop invvpid; # Invalidate Translations Based on virtual-processor identifier (VPID); opcode 66 0f 38 81 +define pcodeop vmcall; # Call to VM monitor by causing VM exit, opcode 0f 01 c1 +define pcodeop vmclear; # Clear virtual-machine control structure, opcode 66 0f c7 /6 +define pcodeop vmfunc; # call virtual-machine function refernced by EAX +define pcodeop vmlaunch; # Launch virtual machine managed by current VMCCS; opcode 0f 01 c2 +define pcodeop vmresume; # Resume virtual machine managed by current VMCS; opcode 0f 01 c3 +define pcodeop vmptrld; # Load pointer to virtual-machine control structure; opcode 0f c6 /6 +define pcodeop vmptrst; # Store pointer to virtual-machine control structure; opcode 0f c7 /7 +define pcodeop vmread; # Read field from virtual-machine control structure; opcode 0f 78 +define pcodeop vmwrite; # Write field to virtual-machine control structure; opcode 0f 79 +define pcodeop vmxoff; # Leave VMX operation; opcode 0f 01 c4 +define pcodeop vmxon; # Enter VMX operation; opcode f3 0f C7 /6 + +@ifdef IA64 +@define LONGMODE_ON "longMode=1" +@define LONGMODE_OFF "longMode=0" +@else +@define LONGMODE_OFF "epsilon" # NOP +@endif + +# When not running in 64-bit mode opcode 0x82 is an alias for 0x80 + +@ifdef IA64 +@define BYTE_80_82 "(byte=0x80 | (longMode=0 & byte=0x82))" +@else +@define BYTE_80_82 "(byte=0x80 | byte=0x82)" +@endif + +@ifdef IA64 +Reg8: reg8 is rexprefix=0 & reg8 { export reg8; } +Reg8: reg8_x0 is rexprefix=1 & rexRprefix=0 & reg8_x0 { export reg8_x0; } +Reg8: reg8_x1 is rexprefix=1 & rexRprefix=1 & reg8_x1 { export reg8_x1; } +Reg16: reg16 is rexRprefix=0 & reg16 { export reg16; } +Reg16: reg16_x is rexRprefix=1 & reg16_x { export reg16_x; } +Reg32: reg32 is rexRprefix=0 & reg32 { export reg32; } +Reg32: reg32_x is rexRprefix=1 & reg32_x { export reg32_x; } +Reg64: reg64 is rexRprefix=0 & reg64 { export reg64; } +Reg64: reg64_x is rexRprefix=1 & reg64_x { export reg64_x; } +Rmr8: r8 is rexprefix=0 & r8 { export r8; } +Rmr8: r8_x0 is rexprefix=1 & rexBprefix=0 & r8_x0 { export r8_x0; } +Rmr8: r8_x1 is rexprefix=1 & rexBprefix=1 & r8_x1 { export r8_x1; } +CRmr8: r8 is rexBprefix=0 & r8 { export r8; } +CRmr8: r8 is addrsize=2 & rexBprefix=0 & r8 { export r8; } +CRmr8: r8_x0 is addrsize=2 & rexprefix=1 & rexBprefix=0 & r8_x0 { export r8_x0; } +CRmr8: r8_x1 is addrsize=2 & rexprefix=1 & rexBprefix=1 & r8_x1 { export r8_x1; } +Rmr16: r16 is rexBprefix=0 & r16 { export r16; } +Rmr16: r16_x is rexBprefix=1 & r16_x { export r16_x; } +CRmr16: r16 is rexBprefix=0 & r16 { export r16; } +CRmr16: r16_x is rexBprefix=1 & r16_x { export r16_x; } +Rmr32: r32 is rexBprefix=0 & r32 { export r32; } +Rmr32: r32_x is rexBprefix=1 & r32_x { export r32_x; } +CRmr32: r32 is rexBprefix=0 & r32 & r64 { export r64; } +CRmr32: r32_x is rexBprefix=1 & r32_x & r64_x { export r64_x; } +Rmr64: r64 is rexBprefix=0 & r64 { export r64; } +Rmr64: r64_x is rexBprefix=1 & r64_x { export r64_x; } +Base: base is rexBprefix=0 & base { export base; } +Base: base_x is rexBprefix=1 & base_x { export base_x; } +Index: index is rexXprefix=0 & index { export index; } +Index: index_x is rexXprefix=1 & index_x { export index_x; } +Base64: base64 is rexBprefix=0 & base64 { export base64; } +Base64: base64_x is rexBprefix=1 & base64_x { export base64_x; } +Index64: index64 is rexXprefix=0 & index64 { export index64; } +Index64: index64_x is rexXprefix=1 & index64_x { export index64_x; } +XmmReg: xmmreg is rexRprefix=0 & xmmreg { export xmmreg; } +XmmReg: xmmreg_x is rexRprefix=1 & xmmreg_x { export xmmreg_x; } +XmmReg1: xmmreg1 is rexRprefix=0 & xmmreg1 { export xmmreg1; } +XmmReg1: xmmreg1_x is rexRprefix=1 & xmmreg1_x { export xmmreg1_x; } +XmmReg2: xmmreg2 is rexBprefix=0 & xmmreg2 { export xmmreg2; } +XmmReg2: xmmreg2_x is rexBprefix=1 & xmmreg2_x { export xmmreg2_x; } +YmmReg1: ymmreg1 is rexRprefix=0 & ymmreg1 { export ymmreg1; } +YmmReg1: ymmreg1_x is rexRprefix=1 & ymmreg1_x { export ymmreg1_x; } +YmmReg2: ymmreg2 is rexBprefix=0 & ymmreg2 { export ymmreg2; } +YmmReg2: ymmreg2_x is rexBprefix=1 & ymmreg2_x { export ymmreg2_x; } +Xmm_vsib: xmm_vsib is rexXprefix=0 & xmm_vsib { export xmm_vsib; } +Xmm_vsib: xmm_vsib_x is rexXprefix=1 & xmm_vsib_x { export xmm_vsib_x; } +Ymm_vsib: ymm_vsib is rexXprefix=0 & ymm_vsib { export ymm_vsib; } +Ymm_vsib: ymm_vsib_x is rexXprefix=1 & ymm_vsib_x { export ymm_vsib_x; } +@else +Reg8: reg8 is reg8 { export reg8; } +Reg16: reg16 is reg16 { export reg16; } +Reg32: reg32 is reg32 { export reg32; } +Rmr8: r8 is r8 { export r8; } +CRmr8: r8 is r8 { export r8; } +Rmr16: r16 is r16 { export r16; } +CRmr16: r16 is r16 { export r16; } +Rmr32: r32 is r32 { export r32; } +CRmr32: r32 is r32 { export r32; } +Base: base is base { export base; } +Index: index is index { export index; } +XmmReg: xmmreg is xmmreg { export xmmreg; } +XmmReg1: xmmreg1 is xmmreg1 { export xmmreg1; } +XmmReg2: xmmreg2 is xmmreg2 { export xmmreg2; } +YmmReg1: ymmreg1 is ymmreg1 { export ymmreg1; } +YmmReg2: ymmreg2 is ymmreg2 { export ymmreg2; } +Xmm_vsib: xmm_vsib is xmm_vsib { export xmm_vsib; } +Ymm_vsib: ymm_vsib is ymm_vsib { export ymm_vsib; } +@endif + +# signed immediate value subconstructors + +simm8_16: simm8 is simm8 { export *[const]:2 simm8; } +simm8_32: simm8 is simm8 { export *[const]:4 simm8; } +@ifdef IA64 +simm8_64: simm8 is simm8 { export *[const]:8 simm8; } +@endif +simm16_16: simm16 is simm16 { export *[const]:2 simm16; } +simm32_32: simm32 is simm32 { export *[const]:4 simm32; } +@ifdef IA64 +simm32_64: simm32 is simm32 { export *[const]:8 simm32; } +imm32_64: imm32 is imm32 { export *[const]:8 imm32; } +@endif + +usimm8_16: imm8 is imm8 & imm8_7=0 { export *[const]:2 imm8; } +usimm8_16: val is imm8 & imm8_7=1 [ val = 0xff00 | imm8; ] { export *[const]:2 val; } +usimm8_32: imm8 is imm8 & imm8_7=0 { export *[const]:4 imm8; } +usimm8_32: val is imm8 & imm8_7=1 [ val = 0xffffff00 | imm8; ] { export *[const]:4 val; } +@ifdef IA64 +usimm8_64: imm8 is imm8 & imm8_7=0 { export *[const]:8 imm8; } +usimm8_64: val is imm8 & imm8_7=1 [ val = 0xffffffffffffff00 | imm8; ] { export *[const]:8 val; } +@endif + +# unused +#usimm16_32: imm16 is imm16 & imm16_15=0 { export *[const]:4 imm16; } +#usimm16_32: val is imm16 & imm16_15=1 [ val = 0xffff0000 | imm16; ] { export *[const]:4 val; } + +# RIP/EIP relative address - NOTE: export of size 0 is intentional so it may be adjusted +pcRelSimm32: addr is simm32 [ addr=inst_next+simm32; ] { export addr; } + +# 16-bit addressing modes (the offset portion) +addr16: [BX + SI] is mod=0 & r_m=0 & BX & SI { local tmp=BX+SI; export tmp; } +addr16: [BX + DI] is mod=0 & r_m=1 & BX & DI { local tmp=BX+DI; export tmp; } +addr16: [BP + SI] is mod=0 & r_m=2 & BP & SI { local tmp=BP+SI; export tmp; } +addr16: [BP + DI] is mod=0 & r_m=3 & BP & DI { local tmp=BP+DI; export tmp; } +addr16: [SI] is mod=0 & r_m=4 & SI { export SI; } +addr16: [DI] is mod=0 & r_m=5 & DI { export DI; } +addr16: [imm16] is mod=0 & r_m=6; imm16 { export *[const]:2 imm16; } +addr16: [BX] is mod=0 & r_m=7 & BX { export BX; } +addr16: [BX + SI + simm8_16] is mod=1 & r_m=0 & BX & SI; simm8_16 { local tmp=BX+SI+simm8_16; export tmp; } +addr16: [BX + DI + simm8_16] is mod=1 & r_m=1 & BX & DI; simm8_16 { local tmp=BX+DI+simm8_16; export tmp; } +addr16: [BP + SI + simm8_16] is mod=1 & r_m=2 & BP & SI; simm8_16 { local tmp=BP+SI+simm8_16; export tmp; } +addr16: [BP + DI + simm8_16] is mod=1 & r_m=3 & BP & DI; simm8_16 { local tmp=BP+DI+simm8_16; export tmp; } +addr16: [SI + simm8_16] is mod=1 & r_m=4 & SI; simm8_16 { local tmp=SI+simm8_16; export tmp; } +addr16: [DI + simm8_16] is mod=1 & r_m=5 & DI; simm8_16 { local tmp=DI+simm8_16; export tmp; } +addr16: [BP + simm8_16] is mod=1 & r_m=6 & BP; simm8_16 { local tmp=BP+simm8_16; export tmp; } +addr16: [BX + simm8_16] is mod=1 & r_m=7 & BX; simm8_16 { local tmp=BX+simm8_16; export tmp; } +addr16: [BX + SI + imm16] is mod=2 & r_m=0 & BX & SI; imm16 { local tmp=BX+SI+imm16; export tmp; } +addr16: [BX + DI + imm16] is mod=2 & r_m=1 & BX & DI; imm16 { local tmp=BX+DI+imm16; export tmp; } +addr16: [BP + SI + imm16] is mod=2 & r_m=2 & BP & SI; imm16 { local tmp=BP+SI+imm16; export tmp; } +addr16: [BP + DI + imm16] is mod=2 & r_m=3 & BP & DI; imm16 {local tmp=BP+DI+imm16; export tmp; } +addr16: [SI + imm16] is mod=2 & r_m=4 & SI; imm16 { local tmp=SI+imm16; export tmp; } +addr16: [DI + imm16] is mod=2 & r_m=5 & DI; imm16 { local tmp=DI+imm16; export tmp; } +addr16: [BP + imm16] is mod=2 & r_m=6 & BP; imm16 { local tmp=BP+imm16; export tmp; } +addr16: [BX + imm16] is mod=2 & r_m=7 & BX; imm16 { local tmp=BX+imm16; export tmp; } + +# 32-bit addressing modes (the offset portion) +addr32: [Rmr32] is mod=0 & Rmr32 { export Rmr32; } +addr32: [Rmr32 + simm8_32] is mod=1 & Rmr32; simm8_32 { local tmp=Rmr32+simm8_32; export tmp; } +addr32: [Rmr32] is mod=1 & r_m!=4 & Rmr32; simm8=0 { export Rmr32; } +addr32: [Rmr32 + imm32] is mod=2 & Rmr32; imm32 { local tmp=Rmr32+imm32; export tmp; } +addr32: [Rmr32] is mod=2 & r_m!=4 & Rmr32; imm32=0 { export Rmr32; } +addr32: [imm32] is mod=0 & r_m=5; imm32 { export *[const]:4 imm32; } +addr32: [Base + Index*ss] is mod=0 & r_m=4; Index & Base & ss { local tmp=Base+Index*ss; export tmp; } +addr32: [Base] is mod=0 & r_m=4; index=4 & Base { export Base; } +addr32: [Index*ss + imm32] is mod=0 & r_m=4; Index & base=5 & ss; imm32 { local tmp=imm32+Index*ss; export tmp; } +addr32: [imm32] is mod=0 & r_m=4; index=4 & base=5; imm32 { export *[const]:4 imm32; } +addr32: [Base + Index*ss + simm8_32] is mod=1 & r_m=4; Index & Base & ss; simm8_32 { local tmp=simm8_32+Base+Index*ss; export tmp; } +addr32: [Base + simm8_32] is mod=1 & r_m=4; index=4 & Base; simm8_32 { local tmp=simm8_32+Base; export tmp; } +addr32: [Base + Index*ss] is mod=1 & r_m=4; Index & Base & ss; simm8=0 { local tmp=Base+Index*ss; export tmp; } +addr32: [Base] is mod=1 & r_m=4; index=4 & Base; simm8=0 { export Base; } +addr32: [Base + Index*ss + imm32] is mod=2 & r_m=4; Index & Base & ss; imm32 { local tmp=imm32+Base+Index*ss; export tmp; } +addr32: [Base + imm32] is mod=2 & r_m=4; index=4 & Base; imm32 { local tmp=imm32+Base; export tmp; } +addr32: [Base + Index*ss] is mod=2 & r_m=4; Index & Base & ss; imm32=0 { local tmp=Base+Index*ss; export tmp; } +addr32: [Base] is mod=2 & r_m=4; index=4 & Base; imm32=0 { export Base; } +@ifdef IA64 +addr32: [pcRelSimm32] is bit64=1 & mod=0 & r_m=4; index=4 & base=5; pcRelSimm32 { export *[const]:4 pcRelSimm32; } + +Addr32_64: [pcRelSimm32] is $(LONGMODE_ON) & mod=0 & r_m=5; pcRelSimm32 { export *[const]:8 pcRelSimm32; } +Addr32_64: [imm32] is $(LONGMODE_ON) & mod=0 & r_m=4; index=4 & base=5; imm32 { export *[const]:8 imm32; } +Addr32_64: addr32 is addr32 { tmp:8 = sext(addr32); export tmp; } + +@endif + +# 64-bit addressing modes (the offset portion) + +@ifdef IA64 +addr64: [Rmr64] is mod=0 & Rmr64 { export Rmr64; } +addr64: [Rmr64 + simm8_64] is mod=1 & Rmr64; simm8_64 { local tmp=Rmr64+simm8_64; export tmp; } +addr64: [Rmr64 + simm32_64] is mod=2 & Rmr64; simm32_64 { local tmp=Rmr64+simm32_64; export tmp; } +addr64: [Rmr64] is mod=1 & r_m!=4 & Rmr64; simm8=0 { export Rmr64; } +addr64: [Rmr64] is mod=2 & r_m!=4 & Rmr64; simm32=0 { export Rmr64; } +addr64: [pcRelSimm32] is mod=0 & r_m=5; pcRelSimm32 { export *[const]:8 pcRelSimm32; } +addr64: [Base64 + Index64*ss] is mod=0 & r_m=4; Index64 & Base64 & ss { local tmp=Base64+Index64*ss; export tmp; } +addr64: [Base64] is mod=0 & r_m=4; rexXprefix=0 & index64=4 & Base64 { export Base64; } +addr64: [simm32_64 + Index64*ss] is mod=0 & r_m=4; Index64 & base64=5 & ss; simm32_64 { local tmp=simm32_64+Index64*ss; export tmp; } +addr64: [Index64*ss] is mod=0 & r_m=4; Index64 & base64=5 & ss; imm32=0 { local tmp=Index64*ss; export tmp; } +addr64: [simm32_64] is mod=0 & r_m=4; rexXprefix=0 & index64=4 & base64=5; simm32_64 { export *[const]:8 simm32_64; } +addr64: [Base64 + simm8_64] is mod=1 & r_m=4; rexXprefix=0 & index64=4 & Base64; simm8_64 { local tmp=simm8_64+Base64; export tmp; } +addr64: [Base64 + Index64*ss + simm8_64] is mod=1 & r_m=4; Index64 & Base64 & ss; simm8_64 { local tmp=simm8_64+Base64+Index64*ss; export tmp; } +addr64: [Base64 + Index64*ss] is mod=1 & r_m=4; Index64 & Base64 & ss; simm8=0 { local tmp=Base64+Index64*ss; export tmp; } +addr64: [Base64 + simm32_64] is mod=2 & r_m=4; rexXprefix=0 & index64=4 & Base64; simm32_64 { local tmp=simm32_64+Base64; export tmp; } +addr64: [Base64] is mod=2 & r_m=4; rexXprefix=0 & index64=4 & Base64; imm32=0 { export Base64; } +addr64: [Base64 + Index64*ss + simm32_64] is mod=2 & r_m=4; Index64 & Base64 & ss; simm32_64 { local tmp=simm32_64+Base64+Index64*ss; export tmp; } +addr64: [Base64 + Index64*ss] is mod=2 & r_m=4; Index64 & Base64 & ss; imm32=0 { local tmp=Base64+Index64*ss; export tmp; } +@endif + +currentCS: CS is protectedMode=0 & CS { tmp:4 = (inst_next >> 4) & 0xf000; CS = tmp:2; export CS; } +currentCS: CS is protectedMode=1 & CS { tmp:4 = (inst_next >> 16) & 0xffff; CS = tmp:2; export CS; } + +segWide: is segover=0 { export 0:$(SIZE); } +segWide: CS: is segover=1 & CS { export 0:$(SIZE); } +segWide: SS: is segover=2 & SS { export 0:$(SIZE); } +segWide: DS: is segover=3 & DS { export 0:$(SIZE); } +segWide: ES: is segover=4 & ES { export 0:$(SIZE); } +segWide: FS: is segover=5 & FS { export FS_OFFSET; } +segWide: GS: is segover=6 & GS { export GS_OFFSET; } + +seg16: is segover=0 { export DS; } +seg16: currentCS: is segover=1 & currentCS { export currentCS; } +seg16: SS: is segover=2 & SS { export SS; } +seg16: DS: is segover=3 & DS { export DS; } +seg16: ES: is segover=4 & ES { export ES; } +seg16: FS: is segover=5 & FS { export FS; } +seg16: GS: is segover=6 & GS { export GS; } + +Mem16: addr16 is (segover=0 & mod=0 & r_m=2) ... & addr16 { tmp:$(SIZE) = segment(SS,addr16); export tmp; } +Mem16: addr16 is (segover=0 & mod=0 & r_m=3) ... & addr16 { tmp:$(SIZE) = segment(SS,addr16); export tmp; } +Mem16: addr16 is (segover=0 & mod=1 & r_m=2) ... & addr16 { tmp:$(SIZE) = segment(SS,addr16); export tmp; } +Mem16: addr16 is (segover=0 & mod=1 & r_m=3) ... & addr16 { tmp:$(SIZE) = segment(SS,addr16); export tmp; } +Mem16: addr16 is (segover=0 & mod=1 & r_m=6) ... & addr16 { tmp:$(SIZE) = segment(SS,addr16); export tmp; } +Mem16: addr16 is (segover=0 & mod=2 & r_m=2) ... & addr16 { tmp:$(SIZE) = segment(SS,addr16); export tmp; } +Mem16: addr16 is (segover=0 & mod=2 & r_m=3) ... & addr16 { tmp:$(SIZE) = segment(SS,addr16); export tmp; } +Mem16: addr16 is (segover=0 & mod=2 & r_m=6) ... & addr16 { tmp:$(SIZE) = segment(SS,addr16); export tmp; } +Mem16: seg16^addr16 is seg16; addr16 { tmp:$(SIZE) = segment(seg16,addr16); export tmp; } + +Mem: Mem16 is addrsize=0 & Mem16 { export Mem16; } + +@ifdef IA64 +Mem: segWide^Addr32_64 is $(LONGMODE_ON) & addrsize=1 & segWide; Addr32_64 { export Addr32_64; } +Mem: segWide^Addr32_64 is $(LONGMODE_ON) & addrsize=1 & segWide & highseg=1; Addr32_64 { tmp:8 = segWide + Addr32_64; export tmp; } +Mem: segWide^addr64 is $(LONGMODE_ON) & addrsize=2 & segWide; addr64 { export addr64; } +Mem: segWide^addr64 is $(LONGMODE_ON) & addrsize=2 & segWide & highseg=1; addr64 { tmp:$(SIZE) = segWide + addr64; export tmp; } +Mem: segWide^addr32 is $(LONGMODE_OFF) & addrsize=1 & segWide; addr32 { tmp:$(SIZE) = zext(addr32); export tmp; } +@else +Mem: segWide^addr32 is $(LONGMODE_OFF) & addrsize=1 & segWide; addr32 { export addr32; } +@endif +Mem: segWide^addr32 is $(LONGMODE_OFF) & addrsize=1 & segWide & highseg=1; addr32 { tmp:$(SIZE) = segWide + zext(addr32); export tmp; } + +rel8: reloc is simm8 [ reloc=inst_next+simm8; ] { export *[ram]:$(SIZE) reloc; } +rel16: reloc is simm16 [ reloc=((inst_next >> 16) << 16) | ((inst_next + simm16) & 0xFFFF); ] { export *[ram]:$(SIZE) reloc; } +rel32: reloc is simm32 [ reloc=inst_next+simm32; ] { export *[ram]:$(SIZE) reloc; } + + +m8: "byte ptr" Mem is Mem { export *:1 Mem; } +m16: "word ptr" Mem is Mem { export *:2 Mem; } +m32: "dword ptr" Mem is Mem { export *:4 Mem; } +m64: "qword ptr" Mem is Mem { export *:8 Mem; } +# m80: Mem is Mem { export *:10 Mem; } +m128: "xmmword ptr" Mem is Mem { export *:16 Mem; } +m256: "ymmword ptr" Mem is Mem { export *:32 Mem; } + +# spec versions of the m8/m16/m32/... tables explicitly print the operand size +spec_m8: "byte ptr "^Mem is Mem { export *:1 Mem; } +spec_m16: "word ptr "^Mem is Mem { export *:2 Mem; } +spec_m32: "dword ptr "^Mem is Mem { export *:4 Mem; } +spec_m64: "qword ptr "^Mem is Mem { export *:8 Mem; } +spec_m80: "tword ptr "^Mem is Mem { export *:10 Mem; } +# spec_m128: "16-byte ptr "^Mem is Mem { export *:16 Mem; } +# spec_m512: "64-byte ptr "^Mem is Mem { export *:64 Mem; } + + + +## +## VSIB +## + +vaddr32x: [Base + Xmm_vsib*ss] is mod=0 & r_m=4; Xmm_vsib & Base & ss { } +vaddr32x: [Xmm_vsib*ss + simm32_32] is mod=0 & r_m=4; Xmm_vsib & base=5 & ss; simm32_32 { } +vaddr32x: [Base + Xmm_vsib*ss + simm8_32] is mod=1 & r_m=4; Xmm_vsib & Base & ss; simm8_32 { } +vaddr32x: [Base + Xmm_vsib*ss + simm32_32] is mod=2 & r_m=4; Xmm_vsib & Base & ss; simm32_32 { } + +vaddr32y: [Base + Ymm_vsib*ss] is mod=0 & r_m=4; Ymm_vsib & Base & ss { } +vaddr32y: [Ymm_vsib*ss + simm32_32] is mod=0 & r_m=4; Ymm_vsib & base=5 & ss; simm32_32 { } +vaddr32y: [Base + Ymm_vsib*ss + simm8_32] is mod=1 & r_m=4; Ymm_vsib & Base & ss; simm8_32 { } +vaddr32y: [Base + Ymm_vsib*ss + simm32_32] is mod=2 & r_m=4; Ymm_vsib & Base & ss; simm32_32 { } + +@ifdef IA64 +vaddr64x: [Base64 + Xmm_vsib*ss] is mod=0 & r_m=4; Xmm_vsib & Base64 & ss { } +vaddr64x: [Xmm_vsib*ss + simm32_64] is mod=0 & r_m=4; Xmm_vsib & base64=5 & ss; simm32_64 { } +vaddr64x: [Base64 + Xmm_vsib*ss + simm8_64] is mod=1 & r_m=4; Xmm_vsib & Base64 & ss; simm8_64 { } +vaddr64x: [Base64 + Xmm_vsib*ss + simm32_64] is mod=2 & r_m=4; Xmm_vsib & Base64 & ss; simm32_64 { } + +vaddr64y: [Base64 + Ymm_vsib*ss] is mod=0 & r_m=4; Ymm_vsib & Base64 & ss { } +vaddr64y: [Ymm_vsib*ss + simm32_64] is mod=0 & r_m=4; Ymm_vsib & base64=5 & ss; simm32_64 { } +vaddr64y: [Base64 + Ymm_vsib*ss + simm8_64] is mod=1 & r_m=4; Ymm_vsib & Base64 & ss; simm8_64 { } +vaddr64y: [Base64 + Ymm_vsib*ss + simm32_64] is mod=2 & r_m=4; Ymm_vsib & Base64 & ss; simm32_64 { } +@endif + + +vMem32x: segWide^vaddr32x is addrsize=1 & segWide; vaddr32x { } +vMem32x: segWide^vaddr32x is addrsize=1 & segWide & highseg=1; vaddr32x { } + +vMem32y: segWide^vaddr32y is addrsize=1 & segWide; vaddr32y { } +vMem32y: segWide^vaddr32y is addrsize=1 & segWide & highseg=1; vaddr32y { } + +@ifdef IA64 +# GAS always inserts a 0x67 prefix before a VSIB instruction with a 32-bit base. +# Behavior is coded to match Binutils; exceeds what the manual indicates is possible. +vMem32x: segWide^vaddr64x is addrsize=2 & segWide; vaddr64x { } +vMem32x: segWide^vaddr64x is addrsize=2 & segWide & highseg=1; vaddr64x { } + +# GAS always inserts a 0x67 prefix before a VSIB instruction with a 32-bit base. +# Behavior is coded to match Binutils; exceeds what the manual indicates is possible. +vMem32y: segWide^vaddr64y is addrsize=2 & segWide; vaddr64y { } +vMem32y: segWide^vaddr64y is addrsize=2 & segWide & highseg=1; vaddr64y { } + +# GAS always inserts a 0x67 prefix before a VSIB instruction with a 32-bit base. +# Behavior is coded to match Binutils; exceeds what the manual indicates is possible. +vMem64x: segWide^vaddr32x is addrsize=1 & segWide; vaddr32x { } +vMem64x: segWide^vaddr32x is addrsize=1 & segWide & highseg=1; vaddr32x { } + +vMem64x: segWide^vaddr64x is addrsize=2 & segWide; vaddr64x { } +vMem64x: segWide^vaddr64x is addrsize=2 & segWide & highseg=1; vaddr64x { } + +# GAS always inserts a 0x67 prefix before a VSIB instruction with a 32-bit base. +# Behavior is coded to match Binutils; exceeds what the manual indicates is possible. +vMem64y: segWide^vaddr32y is addrsize=1 & segWide; vaddr32y { } +vMem64y: segWide^vaddr32y is addrsize=1 & segWide & highseg=1; vaddr32y { } + +vMem64y: segWide^vaddr64y is addrsize=2 & segWide; vaddr64y { } +vMem64y: segWide^vaddr64y is addrsize=2 & segWide & highseg=1; vaddr64y { } +@endif + + +d_vm32x: "dword ptr "^vMem32x is vMem32x { } +d_vm32y: "dword ptr "^vMem32y is vMem32y { } + +@ifdef IA64 +d_vm64x: "dword ptr "^vMem64x is vMem64x { } +d_vm64y: "dword ptr "^vMem64y is vMem64y { } +@endif + + +q_vm32x: "qword ptr "^vMem32x is vMem32x { } +# not used q_vm32y: "qword ptr "^vMem32y is vMem32y { } + +@ifdef IA64 +q_vm64x: "qword ptr "^vMem64x is vMem64x { } +q_vm64y: "qword ptr "^vMem64y is vMem64y { } +@endif + +Reg32_m8: Rmr32 is mod=3 & Rmr32 { export Rmr32; } +Reg32_m8: m8 is m8 { local tmp:4 = zext(m8); export tmp; } +Reg32_m16: Rmr32 is mod=3 & Rmr32 { export Rmr32; } +Reg32_m16: m16 is m16 { local tmp:4 = zext(m16); export tmp; } + +mmxreg2_m64: mmxreg2 is mod=3 & mmxreg2 { export mmxreg2; } +mmxreg2_m64: m64 is m64 { export m64; } + +XmmReg2_m8: XmmReg2 is mod=3 & XmmReg2 { export XmmReg2; } +XmmReg2_m8: m8 is m8 { local tmp:16 = zext(m8); export tmp; } +XmmReg2_m16: XmmReg2 is mod=3 & XmmReg2 { export XmmReg2; } +XmmReg2_m16: m16 is m16 { local tmp:16 = zext(m16); export tmp; } +XmmReg2_m32: XmmReg2 is mod=3 & XmmReg2 { export XmmReg2; } +XmmReg2_m32: m32 is m32 { local tmp:16 = zext(m32); export tmp; } +XmmReg2_m64: XmmReg2 is mod=3 & XmmReg2 { export XmmReg2; } +XmmReg2_m64: m64 is m64 { local tmp:16 = zext(m64); export tmp; } +XmmReg2_m128: XmmReg2 is mod=3 & XmmReg2 { export XmmReg2; } +XmmReg2_m128: m128 is m128 { export m128; } + +YmmReg2_m256: YmmReg2 is mod=3 & YmmReg2 { export YmmReg2; } +YmmReg2_m256: m256 is m256 { export m256; } + +moffs8: seg16^[imm16] is addrsize=0 & seg16 & imm16 { tmp:$(SIZE) = segment(seg16,imm16:2); export *:1 tmp; } +moffs8: segWide^[imm32] is addrsize=1 & highseg=1 & segWide & imm32 { tmp:$(SIZE) = segWide + imm32; export *:1 tmp; } +moffs8: segWide^[imm32] is addrsize=1 & segWide & imm32 { export *:1 imm32; } +@ifdef IA64 +moffs8: segWide^[imm64] is addrsize=2 & highseg=1 & segWide & imm64 { tmp:8 = segWide + imm64; export *:1 tmp; } +moffs8: segWide^[imm64] is addrsize=2 & segWide & imm64 { export *:1 imm64; } +@endif +moffs16: seg16^[imm16] is addrsize=0 & seg16 & imm16 { tmp:$(SIZE) = segment(seg16,imm16:2); export *:2 tmp; } +moffs16: segWide^[imm32] is addrsize=1 & highseg=1 & segWide & imm32 { tmp:$(SIZE) = segWide + imm32; export *:2 tmp; } +moffs16: segWide^[imm32] is addrsize=1 & segWide & imm32 { export *:2 imm32; } +@ifdef IA64 +moffs16: segWide^[imm64] is addrsize=2 & highseg=1 & segWide & imm64 { tmp:8 = segWide + imm64; export *:2 tmp; } +moffs16: segWide^[imm64] is addrsize=2 & segWide & imm64 { export *:2 imm64; } +@endif + +moffs32: seg16^[imm16] is addrsize=0 & seg16 & imm16 { tmp:$(SIZE) = segment(seg16,imm16:2); export *:4 tmp; } +moffs32: segWide^[imm32] is addrsize=1 & segWide & imm32 { export *:4 imm32; } +moffs32: segWide^[imm32] is addrsize=1 & highseg=1 & segWide & imm32 { tmp:$(SIZE) = segWide + imm32; export *:4 tmp; } +@ifdef IA64 +moffs32: segWide^[imm64] is addrsize=2 & segWide & imm64 { export *:4 imm64; } +moffs32: segWide^[imm64] is addrsize=2 & highseg=1 & segWide & imm64 { tmp:8 = segWide + imm64; export *:4 tmp; } +@endif + +@ifdef IA64 +moffs64: segWide^[imm64] is addrsize=2 & segWide & imm64 { export *:8 imm64; } +moffs64: segWide^[imm64] is addrsize=2 & highseg=1 & segWide & imm64 { tmp:8 = segWide + imm64; export *:8 tmp; } +moffs64: segWide^[imm32] is addrsize=1 & segWide & imm32 { export *:8 imm32; } +moffs64: segWide^[imm32] is addrsize=1 & highseg=1 & segWide & imm32 { tmp:8 = segWide + imm32; export *:8 tmp; } +@endif +# TODO: segment register offset in 64bit might not be right + +# String memory access +dseSI1: seg16^SI is addrsize=0 & seg16 & SI { tmp:4 = segment(seg16,SI); SI = SI + 1-2*zext(DF); export *:1 tmp; } +dseSI1: segWide^ESI is addrsize=1 & segWide & ESI { tmp:4 = ESI; ESI = ESI + 1-2*zext(DF); export *:1 tmp; } +dseSI2: seg16^SI is addrsize=0 & seg16 & SI { tmp:4 = segment(seg16,SI); SI = SI + 2-4*zext(DF); export *:2 tmp; } +dseSI2: segWide^ESI is addrsize=1 & segWide & ESI { tmp:4 = ESI; ESI = ESI + 2-4*zext(DF); export *:2 tmp; } +dseSI4: seg16^SI is addrsize=0 & seg16 & SI { tmp:4 = segment(seg16,SI); SI = SI + 4-8*zext(DF); export *:4 tmp; } +dseSI4: segWide^ESI is addrsize=1 & segWide & ESI { tmp:4 = ESI; ESI = ESI + 4-8*zext(DF); export *:4 tmp; } +eseDI1: ES:DI is addrsize=0 & ES & DI { tmp:4 = segment(ES,DI); DI = DI + 1-2*zext(DF); export *:1 tmp; } +eseDI1: ES:EDI is addrsize=1 & ES & EDI { tmp:4 = EDI; EDI=EDI+1-2*zext(DF); export *:1 tmp; } +eseDI2: ES:DI is addrsize=0 & ES & DI { tmp:4 = segment(ES,DI); DI = DI + 2-4*zext(DF); export *:2 tmp; } +eseDI2: ES:EDI is addrsize=1 & ES & EDI { tmp:4 = EDI; EDI=EDI+2-4*zext(DF); export *:2 tmp; } +eseDI4: ES:DI is addrsize=0 & ES & DI { tmp:4 = segment(ES,DI); DI = DI + 4-8*zext(DF); export *:4 tmp; } +eseDI4: ES:EDI is addrsize=1 & ES & EDI { tmp:4 = EDI; EDI=EDI+4-8*zext(DF); export *:4 tmp; } + +@ifdef IA64 +# quadword string functions +dseSI8: seg16^SI is addrsize=0 & seg16 & SI { tmp:4 = segment(seg16,SI); SI = SI + 8-16*zext(DF); export *:8 tmp; } +dseSI8: segWide^ESI is addrsize=1 & segWide & ESI { tmp:4 = ESI; ESI = ESI + 8-16*zext(DF); export *:8 tmp; } +eseDI8: ES:DI is addrsize=0 & ES & DI { tmp:4 = segment(ES,DI); DI = DI + 8-16*zext(DF); export *:8 tmp; } +eseDI8: ES:EDI is addrsize=1 & ES & EDI { tmp:4 = EDI; EDI=EDI+8-16*zext(DF); export *:8 tmp; } + +dseSI1: RSI is addrsize=2 & RSI { local tmp = RSI; RSI = RSI + 1-2*zext(DF); export *:1 tmp; } +dseSI2: RSI is addrsize=2 & RSI { local tmp = RSI; RSI = RSI + 2-4*zext(DF); export *:2 tmp; } +dseSI4: RSI is addrsize=2 & RSI { local tmp = RSI; RSI = RSI + 4-8*zext(DF); export *:4 tmp; } +dseSI8: RSI is addrsize=2 & RSI { local tmp = RSI; RSI = RSI + 8-16*zext(DF); export *:8 tmp; } +eseDI1: RDI is addrsize=2 & RDI { local tmp = RDI; RDI=RDI+1-2*zext(DF); export *:1 tmp; } +eseDI2: RDI is addrsize=2 & RDI { local tmp = RDI; RDI=RDI+2-4*zext(DF); export *:2 tmp; } +eseDI4: RDI is addrsize=2 & RDI { local tmp = RDI; RDI=RDI+4-8*zext(DF); export *:4 tmp; } +eseDI8: RDI is addrsize=2 & RDI { local tmp = RDI; RDI=RDI+8-16*zext(DF); export *:8 tmp; } +@endif + +rm8: Rmr8 is mod=3 & Rmr8 { export Rmr8; } +rm8: "byte ptr" Mem is Mem { export *:1 Mem; } + +spec_rm8: Rmr8 is mod=3 & Rmr8 { export Rmr8; } +spec_rm8: "byte ptr "^Mem is Mem { export *:1 Mem; } + +rm16: Rmr16 is mod=3 & Rmr16 { export Rmr16; } +rm16: "word ptr" Mem is Mem { export *:2 Mem; } + +spec_rm16: Rmr16 is mod=3 & Rmr16 { export Rmr16; } +spec_rm16: "word ptr "^Mem is Mem { export *:2 Mem; } + +rm32: Rmr32 is mod=3 & Rmr32 { export Rmr32; } +rm32: "dword ptr" Mem is Mem { export *:4 Mem; } + +spec_rm32: Rmr32 is mod=3 & Rmr32 { export Rmr32; } +spec_rm32: "dword ptr "^Mem is Mem { export *:4 Mem; } + +@ifdef IA64 +rm64: Rmr64 is mod=3 & Rmr64 { export Rmr64; } +rm64: "qword ptr" Mem is Mem { export *:8 Mem; } + +spec_rm64: Rmr64 is mod=3 & Rmr64 { export Rmr64; } +spec_rm64: "qword ptr "^Mem is Mem { export *:8 Mem; } +@endif + +n1: one is epsilon [ one = 1; ] { export *[const]:1 one; } + +@ifdef IA64 +# Handle zero extension in 64-bit mode for 32-bit destination registers +check_Reg32_dest: is $(LONGMODE_ON) & Reg32 & Reg64 { Reg64 = zext(Reg32); } +check_Rmr32_dest: is $(LONGMODE_ON) & Rmr32 & Rmr64 { Rmr64 = zext(Rmr32); } +check_rm32_dest: is $(LONGMODE_ON) & mod=3 & check_Rmr32_dest { build check_Rmr32_dest; } + +check_Rmr16_dest: is $(LONGMODE_ON) & Rmr16 & Rmr64 { Rmr64 = zext(Rmr16); } +check_rm16_dest: is $(LONGMODE_ON) & mod=3 & check_Rmr16_dest { build check_Rmr16_dest; } + +check_EAX_dest: is $(LONGMODE_ON) { RAX = zext(EAX); } +check_EDX_dest: is $(LONGMODE_ON) { RDX = zext(EDX); } +check_vexVVVV_r32_dest: is $(LONGMODE_ON) & vexVVVV_r64 & vexVVVV_r32 { vexVVVV_r64 = zext(vexVVVV_r32);} +@endif +check_Reg32_dest: is epsilon { } +check_Rmr32_dest: is epsilon { } + +check_Rmr16_dest: is $(LONGMODE_OFF) & Rmr16 & Rmr32 { Rmr32 = zext(Rmr16); } +check_rm16_dest: is $(LONGMODE_OFF) & mod=3 & check_Rmr16_dest { build check_Rmr16_dest; } +check_Rmr16_dest: is epsilon { } +check_rm16_dest: is epsilon { } + +check_EAX_dest: is epsilon { } +check_EDX_dest: is epsilon { } +check_vexVVVV_r32_dest: is epsilon { } +check_rm32_dest: is epsilon { } + + +ptr1616: reloc is protectedMode=0 & imm16; j16 [ reloc = j16*0x10 + imm16; ] { CS = j16; export *[ram]:4 reloc; } +ptr1616: reloc is protectedMode=1 & imm16; j16 [ reloc = j16*0x10000 + imm16; ] { CS = j16; export *[ram]:4 reloc; } +ptr1632: j16":"imm32 is imm32; j16 { CS = j16; export *:4 imm32; } + +# conditions + +cc: "O" is cond=0 { export OF; } +cc: "NO" is cond=1 { local tmp = !OF; export tmp; } +cc: "C" is cond=2 { export CF; } +cc: "NC" is cond=3 { local tmp = !CF; export tmp; } +cc: "Z" is cond=4 { export ZF; } +cc: "NZ" is cond=5 { local tmp = !ZF; export tmp; } +cc: "BE" is cond=6 { local tmp = CF || ZF; export tmp; } +cc: "A" is cond=7 { local tmp = !(CF || ZF); export tmp; } +cc: "S" is cond=8 { export SF; } +cc: "NS" is cond=9 { local tmp = !SF; export tmp; } +cc: "P" is cond=10 { export PF; } +cc: "NP" is cond=11 { local tmp = !PF; export tmp; } +cc: "L" is cond=12 { local tmp = OF != SF; export tmp; } +cc: "GE" is cond=13 { local tmp = OF == SF; export tmp; } +cc: "LE" is cond=14 { local tmp = ZF || (OF != SF); export tmp; } +cc: "G" is cond=15 { local tmp = !ZF && (OF == SF); export tmp; } + +# repeat prefixes +rep_check: is addrsize=0 { if (CX==0) goto inst_next; } +rep_check: is addrsize=1 { if (ECX==0) goto inst_next; } +@ifdef IA64 +rep_check: is addrsize=2 { if (RCX==0) goto inst_next; } +@endif + +rep_update: is addrsize=0 { CX=CX-1; } +rep_update: is addrsize=1 { ECX=ECX-1; } +@ifdef IA64 +rep_update: is addrsize=2 { RCX=RCX-1; } +@endif + +rep: ".REP" is repprefx=1 & repneprefx=0 & rep_check { } +rep: ".REPNE" is repprefx=0 & repneprefx=1 & rep_check { } # Although undocumented, either rep prefix is allowed but ZF is always ignored +rep: is repprefx=0 & repneprefx=0 { } + + +reptail: is (repprefx=1 | repneprefx=1) & rep_update { goto inst_start; } +reptail: is repprefx=0 & repneprefx=0 { } + +repe: ".REPE" is repprefx=1 & repneprefx=0 & rep_check { } +repe: ".REPNE" is repprefx=0 & repneprefx=1 & rep_check { } +repe: is repprefx=0 & repneprefx=0 { } + +repetail: is repprefx=1 & repneprefx=0 & rep_update { if (ZF) goto inst_start; } +repetail: is repprefx=0 & repneprefx=1 & rep_update { if (!ZF) goto inst_start; } +repetail: is repprefx=0 & repneprefx=0 { } + +# XACQUIRE/XRELEASE prefix +xacq_xrel_prefx: ".XACQUIRE" is xacquireprefx=1 & xreleaseprefx=0 { XACQUIRE(); } +xacq_xrel_prefx: ".XRELEASE" is xacquireprefx=0 & xreleaseprefx=1 { XRELEASE(); } +xacq_xrel_prefx: is epsilon { } + +#the XRELEASE prefix can be used with several variants of MOV (without the LOCK prefix) +xrelease: ".XRELEASE" is xacquireprefx=0 & xreleaseprefx=1 { XRELEASE(); } +xrelease: is epsilon { } + +#XCHG with a memory destination asserts a LOCK signal whether or not there is a LOCK prefix (f0) +#"alwaysLock" constructor will place "LOCK" in the disassembly if the prefix occurs +alwaysLock: ".LOCK" is lockprefx=1 { LOCK(); } +alwaysLock: is epsilon { LOCK(); } + +#check for LOCK prefix and the optional XACQUIRE/XRELEASE +lockx: xacq_xrel_prefx^".LOCK" is lockprefx=1 & xacq_xrel_prefx { build xacq_xrel_prefx; LOCK(); } +lockx: is epsilon { } + +#"unlock" constructor is used to pair every LOCK pcodeop with a matching UNLOCK pcodeop +unlock: is lockprefx=1 { UNLOCK(); } +unlock: is epsilon { } + +# Some macros + +@include "macros.sinc" + +macro ptr2(r,x) { + r = zext(x); +} + +macro ptr4(r,x) { +@ifdef IA64 + r = zext(x); +@else + r = x; +@endif +} + +macro ptr8(r,x) { +@ifdef IA64 + r = x; +@else + r = x:$(SIZE); +@endif +} + +macro push22(x) { + mysave:2 = x; + SP = SP -2; + tmp:$(SIZE) = segment(SS,SP); + *:2 tmp = mysave; +} + +macro push24(x) { + mysave:4 = x; + SP = SP-4; + tmp:$(SIZE) = segment(SS,SP); + *:4 tmp = mysave; +} + +macro push28(x) { + mysave:8 = x; + SP = SP-8; + tmp:$(SIZE) = segment(SS,SP); + *:8 tmp = mysave; +} + +macro push42(x) { + mysave:2 = x; + $(STACKPTR) = $(STACKPTR) - 2; + *:2 $(STACKPTR) = mysave; +} + +macro push44(x) { + mysave:4 = x; + $(STACKPTR) = $(STACKPTR) - 4; + *:4 $(STACKPTR) = mysave; +} + +macro pushseg44(x) { + mysave:2 = x; + $(STACKPTR) = $(STACKPTR) - 4; + *:2 $(STACKPTR) = mysave; +} + +macro push48(x) { + mysave:8 = x; + $(STACKPTR) = $(STACKPTR) - 8; + *:8 $(STACKPTR) = mysave; +} + +@ifdef IA64 +macro push82(x) { + mysave:2 = x; + $(STACKPTR) = $(STACKPTR) - 2; + *:2 $(STACKPTR) = mysave; +} + +macro push84(x) { + mysave:4 = x; + $(STACKPTR) = $(STACKPTR) - 4; + *:4 $(STACKPTR) = mysave; +} + +macro push88(x) { + mysave:8 = x; + $(STACKPTR) = $(STACKPTR) - 8; + *:8 $(STACKPTR) = mysave; +} + +macro pushseg82(x) { + mysave:2 = x; + $(STACKPTR) = $(STACKPTR) - 2; + *:2 $(STACKPTR) = mysave; +} + +macro pushseg88(x) { + mysave:2 = x; + $(STACKPTR) = $(STACKPTR) - 8; + *:2 $(STACKPTR) = mysave; +} +@endif + +# Note: for each pop operation we are careful to order the operations such that is correct for +# both 'POP [RSP + offset]' and 'POP RSP' + +macro pop22(x) { + tmp:$(SIZE) = segment(SS,SP); + value = *:2 tmp; + SP = SP+2; + x = value; +} + +macro pop24(x) { + tmp:$(SIZE) = segment(SS,SP); + value = *:4 tmp; + SP = SP+4; + x = value; +} + +macro pop28(x) { + tmp:$(SIZE) = segment(SS,SP); + value = *:8 tmp; + SP = SP+8; + x = value; +} + +macro pop42(x) { + value = *:2 $(STACKPTR); + ESP = ESP + 2; + x = value; +} + +macro pop44(x) { + value = *:4 $(STACKPTR); + ESP = ESP + 4; + x = value; +} + +macro popseg44(x) { + value = *:2 $(STACKPTR); + ESP = ESP + 4; + x = value; +} + +macro pop48(x) { + value = *:8 $(STACKPTR); + ESP = ESP + 8; + x = value; +} + +@ifdef IA64 +macro pop82(x) { + value = *:2 $(STACKPTR); + RSP = RSP + 2; + x = value; +} + +macro pop84(x) { + value = *:4 $(STACKPTR); + RSP = RSP + 4; + x = value; +} + +macro pop88(x) { + value = *:8 $(STACKPTR); + RSP = RSP + 8; + x = value; +} + +macro popseg82(x) { + value = *:2 $(STACKPTR); + RSP = RSP + 2; + x = value; +} + +macro popseg88(x) { + value = *:2 $(STACKPTR); + RSP = RSP + 8; + x = value; +} + +@endif + +macro unpackflags(tmp) { + NT = (tmp & 0x4000) != 0; +# IOPL = (tmp & 0x1000) != 0; + OF = (tmp & 0x0800) != 0; + DF = (tmp & 0x0400) != 0; + IF = (tmp & 0x0200) != 0; + TF = (tmp & 0x0100) != 0; + SF = (tmp & 0x0080) != 0; + ZF = (tmp & 0x0040) != 0; + AF = (tmp & 0x0010) != 0; + PF = (tmp & 0x0004) != 0; + CF = (tmp & 0x0001) != 0; +} + +macro unpackeflags(tmp) { + ID = (tmp & 0x00200000) != 0; + AC = (tmp & 0x00040000) != 0; +# RF = (tmp & 0x00010000) != 0; + VIP = 0; + VIF = 0; +} + +macro packflags(tmp) { + tmp= (0x4000 * zext(NT&1)) +# | (0x1000 * zext(IOPL&1)) + | (0x0800 * zext(OF&1)) + | (0x0400 * zext(DF&1)) | (0x0200 * zext(IF&1)) | (0x0100 * zext(TF&1)) + | (0x0080 * zext(SF&1)) | (0x0040 * zext(ZF&1)) | (0x0010 * zext(AF&1)) + | (0x0004 * zext(PF&1)) | (0x0001 * zext(CF&1)); +} + +macro packeflags(tmp) { + tmp = tmp | (0x00200000 * zext(ID&1)) | (0x00100000 * zext(VIP&1)) + | (0x00080000 * zext(VIF&1)) | (0x00040000 * zext(AC&1)); +} + +macro addflags(op1,op2) { + CF = carry(op1,op2); + OF = scarry(op1,op2); +} + +# +# full-adder carry and overflow calculations +# +macro addCarryFlags ( op1, op2 ) { + local CFcopy = zext(CF); + CF = carry( op1, op2 ); + OF = scarry( op1, op2 ); + local result = op1 + op2; + CF = CF || carry( result, CFcopy ); + OF = OF ^^ scarry( result, CFcopy ); + op1 = result + CFcopy; + # AF not implemented +} + + +macro subCarryFlags ( op1, op2 ) { + local CFcopy = zext(CF); + CF = op1 < op2; + OF = sborrow( op1, op2 ); + local result = op1 - op2; + CF = CF || (result < CFcopy); + OF = OF ^^ sborrow( result, CFcopy ); + op1 = result - CFcopy; + # AF not implemented +} + +macro resultflags(result) { + SF = result s< 0; + ZF = result == 0; + PF = ((popcount(result & 0xff) & 1:1) == 0); + # AF not implemented +} + +macro shiftresultflags(result,count) { + + local notzero = (count != 0); + + local newSF = (result s< 0); + SF = (!notzero && SF) || (notzero && newSF); + + local newZF = (result == 0); + ZF = (!notzero && ZF) || (notzero && newZF); + + local newPF = ((popcount(result & 0xff) & 1:1) == 0); + PF = (!notzero && PF) || (notzero && newPF); + # AF not implemented +} + +macro subflags(op1,op2) { + CF = op1 < op2; + OF = sborrow(op1,op2); +} + +macro negflags(op1) { + CF = (op1 != 0); + OF = sborrow(0,op1); +} + +macro logicalflags() { + CF = 0; + OF = 0; +} + +macro imultflags(low,total){ + CF = sext(low) != total; + OF = CF; +} + +macro multflags(highhalf) { + CF = highhalf != 0; + OF = CF; +} + +macro rolflags(result,count) { + + local notzero = (count != 0); + local newCF = ((result & 1) != 0); + CF = (!notzero && CF) || (notzero && newCF); + + local one = (count == 1); + local newOF = CF ^^ (result s< 0); + OF = (!one && OF) || (one && newOF); +} + +macro rorflags(result,count) { + + local notzero = (count != 0); + local newCF = (result s< 0); + CF = (!notzero && CF) || (notzero && newCF); + + local one = (count == 1); + local newOF = (result s< 0) ^^ ((result << 1) s< 0); + OF = (!one && OF) || (one && newOF); +} + +macro shlflags(op1,result,count) { # works for shld also + + local notzero = (count != 0); + local newCF = ( (op1 << (count - 1)) s< 0 ); + CF = (!notzero && CF) || (notzero && newCF); + + local one = (count == 1); + local newOF = CF ^^ (result s< 0); + OF = (!one && OF) || (one && newOF); +} + +macro sarflags(op1,result,count) { + + local notzero = (count != 0); + local newCF = ( ( (op1 s>> (count - 1)) & 1 ) != 0 ); + CF = (!notzero && CF) || (notzero && newCF); + + local one = (count == 1); + OF = (!one && OF); +} + +macro shrflags(op1,result,count) { + + local notzero = (count != 0); + local newCF = ( ( (op1 >> (count - 1)) & 1 ) != 0 ); + CF = (!notzero && CF) || (notzero && newCF); + + local one = (count == 1); + local newOF = (op1 s< 0); + OF = (!one && OF) || (one && newOF); +} + +macro shrdflags(op1,result,count) { + + local notzero = (count != 0); + local newCF = ( ( (op1 >> (count - 1)) & 1 ) != 0 ); + CF = (!notzero && CF) || (notzero && newCF); + + local one = (count == 1); + local newOF = ((op1 s< 0) ^^ (result s< 0)); + OF = (!one && OF) || (one && newOF); +} + +macro fdec() { + local tmp = ST7; + ST7 = ST6; + ST6 = ST5; + ST5 = ST4; + ST4 = ST3; + ST3 = ST2; + ST2 = ST1; + ST1 = ST0; + ST0 = tmp; +} + +macro finc() { + local tmp = ST0; + ST0 = ST1; + ST1 = ST2; + ST2 = ST3; + ST3 = ST4; + ST4 = ST5; + ST5 = ST6; + ST6 = ST7; + ST7 = tmp; +} + +macro fpop() { + ST0 = ST1; + ST1 = ST2; + ST2 = ST3; + ST3 = ST4; + ST4 = ST5; + ST5 = ST6; + ST6 = ST7; +} + + macro fpushv(val) { + ST7 = ST6; + ST6 = ST5; + ST5 = ST4; + ST4 = ST3; + ST3 = ST2; + ST2 = ST1; + ST1 = ST0; + ST0 = val; +} + +macro fpopv(val) { + val = ST0; + ST0 = ST1; + ST1 = ST2; + ST2 = ST3; + ST3 = ST4; + ST4 = ST5; + ST5 = ST6; + ST6 = ST7; +} + +macro fcom(val) { + C1 = 0; + + C2 = nan(ST0) || nan(val); + C0 = C2 | ( ST0 f< val ); + C3 = C2 | ( ST0 f== val ); + + FPUStatusWord = (zext(C0)<<8) | (zext(C1)<<9) | (zext(C2)<<10) | (zext(C3)<<14); +} + +macro fcomi(val) { + PF = nan(ST0) || nan(val); + ZF = PF | ( ST0 f== val ); + CF = PF | ( ST0 f< val ); + + OF = 0; + AF = 0; + SF = 0; + + FPUStatusWord = FPUStatusWord & 0xfdff; # Clear C1 + C1 = 0; +} + +# floating point NaN comparison into EFLAGS +macro fucompe(val1, val2) { + PF = nan(val1) || nan(val2 ); + ZF = PF | ( val1 f== val2 ); + CF = PF | ( val1 f< val2 ); + + OF = 0; + AF = 0; + SF = 0; +} + +# The base level constructors +# The prefixes +:^instruction is instrPhase=0 & over=0x2e; instruction [ segover=1; ] {} # CS override +:^instruction is instrPhase=0 & over=0x36; instruction [ segover=2; ] {} # SS override +:^instruction is instrPhase=0 & over=0x3e; instruction [ segover=3; ] {} # DS override +:^instruction is instrPhase=0 & over=0x26; instruction [ segover=4; ] {} # ES override +:^instruction is instrPhase=0 & over=0x64; instruction [ segover=5; ] {} # FS override +:^instruction is instrPhase=0 & over=0x65; instruction [ segover=6; ] {} # GS override +:^instruction is instrPhase=0 & over=0x66; instruction [ opsize=opsize $xor 1; mandover = mandover $xor 1; ] {} # Operand size override +:^instruction is instrPhase=0 & over=0x67; instruction [ addrsize=addrsize $xor 1; ] {} # Address size override +:^instruction is instrPhase=0 & over=0xf2; instruction [ repneprefx=1; repprefx=0; ] {} +:^instruction is instrPhase=0 & over=0xf3; instruction [ repneprefx=0; repprefx=1; ] {} +:^instruction is instrPhase=0 & over=0xf0; instruction [ lockprefx=1; ] {} +@ifdef IA64 + +# +# REX opcode extension prefixes +# + +# REX prefix present +# Specification is "REX" +@define REX "longMode=1 & rexprefix=1 & rexWprefix=0" + +# Specification is "REX.W" +@define REX_W "longMode=1 & rexprefix=1 & rexWprefix=1" + + + +# TODO I don't think the following line can really happen because the 66 67 prefix must come before REX prefix +:^instruction is $(LONGMODE_ON) & instrPhase=0 & over=0x66 & opsize=2; instruction [ opsize=0; mandover=mandover $xor 1; ] {} # Operand size override +:^instruction is $(LONGMODE_ON) & instrPhase=0 & over=0x67 & addrsize=2; instruction [ addrsize=1; ] {} # Address size override + +:^instruction is $(LONGMODE_ON) & instrPhase=0 & row=0x4 & rexw=0 & rexr & rexx & rexb; instruction [ instrPhase=1; rexprefix=1; opsize=1; rexWprefix=0; rexRprefix=rexr; rexXprefix=rexx; rexBprefix=rexb; ] {} +:^instruction is $(LONGMODE_ON) & instrPhase=0 & row=0x4 & rexw=1 & rexr & rexx & rexb; instruction [ instrPhase=1; rexprefix=1; opsize=2; rexWprefix=1; rexRprefix=rexr; rexXprefix=rexx; rexBprefix=rexb; ] {} +:^instruction is $(LONGMODE_ON) & instrPhase=0 & opsize=0 & row=0x4 & rexw=0 & rexr & rexx & rexb; instruction [ instrPhase=1; rexprefix=1; opsize=0; rexWprefix=0; rexRprefix=rexr; rexXprefix=rexx; rexBprefix=rexb; ] {} +:^instruction is $(LONGMODE_ON) & instrPhase=0 & opsize=0 & row=0x4 & rexw=1 & rexr & rexx & rexb; instruction [ instrPhase=1; rexprefix=1; opsize=2; rexWprefix=1; rexRprefix=rexr; rexXprefix=rexx; rexBprefix=rexb; ] {} + + # if longmode is off (on 64-bit processor in 32-bit compatibility mode), there is no 64-bit addressing, make sure is off before parsing + # +:^instruction is $(LONGMODE_OFF) & instrPhase=0 & addrsize=2 & instruction [ addrsize=1; ] {} +@endif + +# +# VEX definitions: One from each group must be present in the decoding; following the specification from the manual. +# + +# VEX encoding for type of VEX data flow. +# Specification is "VEX.", "VEX.NDS", "VEX.NDD", or "VEX.DDS". If only "VEX." is present, then "VEX_NONE" must be used. +@define VEX_NONE "vexMode=1 & vexVVVV=0" +@define VEX_NDS "vexMode=1" +@define VEX_NDD "vexMode=1" +@define VEX_DDS "vexMode=1" + +# Specification is "LIG", "LZ", "128", or "256". +@define VEX_LIG "vexL" +@define VEX_LZ "vexL=0" +@define VEX_L128 "vexL=0" +@define VEX_L256 "vexL=1" + +# These are only to be used with VEX or EVEX decoding, where only one "mandatory" prefix is encoded in the VEX or EVEX. +# If no prefix is specified, then VEX_PRE_NONE must be used. +# No other "physical" prefixes are allowed. +# Specification is "(empty)", "66", "F3", or "F2". If none of these are present (empty), then "VEX_PRE_NONE" must be used. +@define VEX_PRE_NONE "mandover=0" +@define VEX_PRE_66 "mandover=1" +@define VEX_PRE_F3 "mandover=2" +@define VEX_PRE_F2 "mandover=4" + +# Specification is "0F", "0F38", or "0F3A". +@define VEX_0F "vexMMMMM=1" +@define VEX_0F38 "vexMMMMM=2" +@define VEX_0F3A "vexMMMMM=3" + +# Specification is "WIG", "W0", or "W1". +@define VEX_WIG "rexWprefix" +@define VEX_W0 "rexWprefix=0" +@define VEX_W1 "rexWprefix=1" + + + +@ifdef IA64 + +# 64-bit 3-byte VEX +:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r & vex_x & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=0; instruction + [ instrPhase=1; vexMode=1; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; vexMMMMM=vex_mmmmm; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexL=vex_l; ] {} +:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r & vex_x & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=1; instruction + [ instrPhase=1; vexMode=1; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; vexMMMMM=vex_mmmmm; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexL=vex_l; prefix_66=1; ] {} +:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r & vex_x & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=2; instruction + [ instrPhase=1; vexMode=1; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; vexMMMMM=vex_mmmmm; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexL=vex_l; prefix_f3=1; ] {} +:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r & vex_x & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=3; instruction + [ instrPhase=1; vexMode=1; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; vexMMMMM=vex_mmmmm; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexL=vex_l; prefix_f2=1; ] {} + +# 64-bit 2-byte VEX +:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r & vex_vvvv & vex_l & vex_pp=0; instruction + [ instrPhase=1; vexMode=1; rexRprefix=~vex_r; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; ] {} +:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r & vex_vvvv & vex_l & vex_pp=1; instruction + [ instrPhase=1; vexMode=1; rexRprefix=~vex_r; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; prefix_66=1; ] {} +:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r & vex_vvvv & vex_l & vex_pp=2; instruction + [ instrPhase=1; vexMode=1; rexRprefix=~vex_r; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; prefix_f3=1; ] {} +:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r & vex_vvvv & vex_l & vex_pp=3; instruction + [ instrPhase=1; vexMode=1; rexRprefix=~vex_r; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; prefix_f2=1; ] {} + +@endif + +# 32-bit 3-byte VEX +:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r=1 & vex_x=1 & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=0; instruction + [ instrPhase=1; vexMode=1; rexBprefix=~vex_b; vexMMMMM=vex_mmmmm; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexL=vex_l; ] {} +:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r=1 & vex_x=1 & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=1; instruction + [ instrPhase=1; vexMode=1; rexBprefix=~vex_b; vexMMMMM=vex_mmmmm; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexL=vex_l; prefix_66=1; ] {} +:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r=1 & vex_x=1 & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=2; instruction + [ instrPhase=1; vexMode=1; rexBprefix=~vex_b; vexMMMMM=vex_mmmmm; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexL=vex_l; prefix_f3=1; ] {} +:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r=1 & vex_x=1 & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=3; instruction + [ instrPhase=1; vexMode=1; rexBprefix=~vex_b; vexMMMMM=vex_mmmmm; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexL=vex_l; prefix_f2=1; ] {} + +# 32-bit 2-byte VEX +:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r=1 & vex_x=1 & vex_vvvv & vex_l & vex_pp=0; instruction + [ instrPhase=1; vexMode=1; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; ] {} +:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r=1 & vex_x=1 & vex_vvvv & vex_l & vex_pp=1; instruction + [ instrPhase=1; vexMode=1; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; prefix_66=1; ] {} +:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r=1 & vex_x=1 & vex_vvvv & vex_l & vex_pp=2; instruction + [ instrPhase=1; vexMode=1; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; prefix_f3=1; ] {} +:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r=1 & vex_x=1 & vex_vvvv & vex_l & vex_pp=3; instruction + [ instrPhase=1; vexMode=1; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; prefix_f2=1; ] {} + + +# Many of the multimedia instructions have a "mandatory" prefix, either 0x66, 0xf2 or 0xf3 +# where the prefix really becomes part of the encoding. We collect the three possible prefixes of this +# sort in the mandover context variable so we can pattern all three at once + +# 3DNow pre-parse to isolate suffix byte into context (suffix3D) +# - general format: 0x0f 0x0f [sib] [displacement] +# - must determine number of bytes consumed by addressing modes +# TODO: determine supported prefixes? (e.g., 0x26) + +Suffix3D: imm8 is imm8 [ suffix3D=imm8; ] { } + +:^instruction is instrPhase=0 & (byte=0x0f; byte=0x0f; XmmReg ... & m64; Suffix3D) ... & instruction ... [ instrPhase=1; ] { } +:^instruction is instrPhase=0 & (byte=0x0f; byte=0x0f; mmxmod=3; Suffix3D) ... & instruction ... [ instrPhase=1; ] { } + + +# Instructions in alphabetical order + +# See 'lockable.sinc' file for instructions that are lockable +with : lockprefx=0 { + +:AAA is $(LONGMODE_OFF) & vexMode=0 & byte=0x37 { local car = ((AL & 0xf) > 9) | AF; AL = (AL+6*car)&0xf; AH=AH+car; CF=car; AF=car; } +:AAD imm8 is $(LONGMODE_OFF) & vexMode=0 & byte=0xd5; imm8 { AL = AL + imm8*AH; AH=0; resultflags(AX); } +:AAM imm8 is $(LONGMODE_OFF) & vexMode=0 & byte=0xd4; imm8 { AH = AL/imm8; AL = AL % imm8; resultflags(AX); } +:AAS is $(LONGMODE_OFF) & vexMode=0 & byte=0x3f { local car = ((AL & 0xf) > 9) | AF; AL = (AL-6*car)&0xf; AH=AH-car; CF=car; AF=car; } + +# See 'lockable.sinc' for memory destination, lockable variants +:ADC AL,imm8 is vexMode=0 & byte=0x14; AL & imm8 { addCarryFlags( AL, imm8:1 ); resultflags( AL ); } +:ADC AX,imm16 is vexMode=0 & opsize=0 & byte=0x15; AX & imm16 { addCarryFlags( AX, imm16:2 ); resultflags( AX ); } +:ADC EAX,imm32 is vexMode=0 & opsize=1 & byte=0x15; EAX & check_EAX_dest & imm32 { addCarryFlags( EAX, imm32:4 ); build check_EAX_dest; resultflags( EAX ); } +@ifdef IA64 +:ADC RAX,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x15; RAX & simm32 { addCarryFlags( RAX, simm32 ); resultflags( RAX ); } +@endif +:ADC Rmr8,imm8 is vexMode=0 & $(BYTE_80_82); mod=3 & Rmr8 & reg_opcode=2; imm8 { addCarryFlags( Rmr8, imm8:1 ); resultflags( Rmr8 ); } +:ADC Rmr16,imm16 is vexMode=0 & opsize=0 & byte=0x81; mod=3 & Rmr16 & reg_opcode=2; imm16 { addCarryFlags( Rmr16, imm16:2 ); resultflags( Rmr16 ); } +:ADC Rmr32,imm32 is vexMode=0 & opsize=1 & byte=0x81; mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=2; imm32 { addCarryFlags( Rmr32, imm32:4 ); build check_Rmr32_dest; resultflags( Rmr32 ); } +@ifdef IA64 +:ADC Rmr64,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x81; mod=3 & Rmr64 & reg_opcode=2; simm32 { addCarryFlags( Rmr64, simm32 ); resultflags( Rmr64 ); } +@endif +:ADC Rmr16,simm8_16 is vexMode=0 & opsize=0 & byte=0x83; mod=3 & Rmr16 & reg_opcode=2; simm8_16 { addCarryFlags( Rmr16, simm8_16 ); resultflags( Rmr16 ); } +:ADC Rmr32,simm8_32 is vexMode=0 & opsize=1 & byte=0x83; mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=2; simm8_32 { addCarryFlags( Rmr32, simm8_32 ); build check_Rmr32_dest; resultflags( Rmr32 ); } +@ifdef IA64 +:ADC Rmr64,simm8_64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x83; mod=3 & Rmr64 & reg_opcode=2; simm8_64 { addCarryFlags( Rmr64, simm8_64 ); resultflags( Rmr64 ); } +@endif +:ADC Rmr8,Reg8 is vexMode=0 & byte=0x10; mod=3 & Rmr8 & Reg8 { addCarryFlags( Rmr8, Reg8 ); resultflags( Rmr8 ); } +:ADC Rmr16,Reg16 is vexMode=0 & opsize=0 & byte=0x11; mod=3 & Rmr16 & Reg16 { addCarryFlags( Rmr16, Reg16 ); resultflags( Rmr16 ); } +:ADC Rmr32,Reg32 is vexMode=0 & opsize=1 & byte=0x11; mod=3 & Rmr32 & check_Rmr32_dest & Reg32 { addCarryFlags( Rmr32, Reg32 ); build check_Rmr32_dest; resultflags( Rmr32 ); } +@ifdef IA64 +:ADC Rmr64,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x11; mod=3 & Rmr64 & Reg64 { addCarryFlags( Rmr64, Reg64 ); resultflags( Rmr64 ); } +@endif +:ADC Reg8,rm8 is vexMode=0 & byte=0x12; rm8 & Reg8 ... { addCarryFlags( Reg8, rm8 ); resultflags( Reg8 ); } +:ADC Reg16,rm16 is vexMode=0 & opsize=0 & byte=0x13; rm16 & Reg16 ... { addCarryFlags( Reg16, rm16 ); resultflags( Reg16 ); } +:ADC Reg32,rm32 is vexMode=0 & opsize=1 & byte=0x13; rm32 & Reg32 ... & check_Reg32_dest ... { addCarryFlags( Reg32, rm32 ); build check_Reg32_dest; resultflags( Reg32 ); } +@ifdef IA64 +:ADC Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x13; rm64 & Reg64 ... { addCarryFlags( Reg64, rm64 ); resultflags( Reg64 ); } +@endif + +# See 'lockable.sinc' for memory destination, lockable variants +:ADD AL,imm8 is vexMode=0 & byte=0x4; AL & imm8 { addflags( AL,imm8 ); AL = AL + imm8; resultflags( AL); } +:ADD AX,imm16 is vexMode=0 & opsize=0 & byte=0x5; AX & imm16 { addflags( AX,imm16); AX = AX + imm16; resultflags( AX); } +:ADD EAX,imm32 is vexMode=0 & opsize=1 & byte=0x5; EAX & check_EAX_dest & imm32 { addflags( EAX,imm32); EAX = EAX + imm32; build check_EAX_dest; resultflags( EAX); } +@ifdef IA64 +:ADD RAX,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x5; RAX & simm32 { addflags( RAX,simm32); RAX = RAX + simm32; resultflags( RAX); } +@endif +:ADD Rmr8,imm8 is vexMode=0 & $(BYTE_80_82); mod=3 & Rmr8 & reg_opcode=0; imm8 { addflags( Rmr8,imm8 ); Rmr8 = Rmr8 + imm8; resultflags( Rmr8); } +:ADD Rmr16,imm16 is vexMode=0 & opsize=0 & byte=0x81; mod=3 & Rmr16 & reg_opcode=0; imm16 { addflags( Rmr16,imm16); Rmr16 = Rmr16 + imm16; resultflags( Rmr16); } +:ADD Rmr32,imm32 is vexMode=0 & opsize=1 & byte=0x81; mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=0; imm32 { addflags( Rmr32,imm32); Rmr32 = Rmr32 + imm32; build check_Rmr32_dest; resultflags( Rmr32); } +@ifdef IA64 +:ADD Rmr64,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x81; mod=3 & Rmr64 & reg_opcode=0; simm32 { addflags( Rmr64,simm32); Rmr64 = Rmr64 + simm32; resultflags( Rmr64); } +@endif +:ADD Rmr16,simm8_16 is vexMode=0 & opsize=0 & byte=0x83; mod=3 & Rmr16 & reg_opcode=0; simm8_16 { addflags( Rmr16,simm8_16); Rmr16 = Rmr16 + simm8_16; resultflags( Rmr16); } +:ADD Rmr32,simm8_32 is vexMode=0 & opsize=1 & byte=0x83; mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=0; simm8_32 { addflags( Rmr32,simm8_32); Rmr32 = Rmr32 + simm8_32; build check_Rmr32_dest; resultflags( Rmr32); } +@ifdef IA64 +:ADD Rmr64,simm8_64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x83; mod=3 & Rmr64 & reg_opcode=0; simm8_64 { addflags( Rmr64,simm8_64); Rmr64 = Rmr64 + simm8_64; resultflags( Rmr64); } +@endif +:ADD Rmr8,Reg8 is vexMode=0 & byte=0x00; mod=3 & Rmr8 & Reg8 { addflags( Rmr8,Reg8 ); Rmr8 = Rmr8 + Reg8; resultflags( Rmr8); } +:ADD Rmr16,Reg16 is vexMode=0 & opsize=0 & byte=0x1; mod=3 & Rmr16 & Reg16 { addflags( Rmr16,Reg16); Rmr16 = Rmr16 + Reg16; resultflags( Rmr16); } +:ADD Rmr32,Reg32 is vexMode=0 & opsize=1 & byte=0x1; mod=3 & Rmr32 & check_Rmr32_dest & Reg32 { addflags( Rmr32,Reg32); Rmr32 = Rmr32 + Reg32; build check_Rmr32_dest; resultflags( Rmr32); } +@ifdef IA64 +:ADD Rmr64,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x1; mod=3 & Rmr64 & Reg64 { addflags( Rmr64,Reg64); Rmr64 = Rmr64 + Reg64; resultflags( Rmr64); } +@endif +:ADD Reg8,rm8 is vexMode=0 & byte=0x2; rm8 & Reg8 ... { addflags( Reg8,rm8 ); Reg8 = Reg8 + rm8; resultflags( Reg8); } +:ADD Reg16,rm16 is vexMode=0 & opsize=0 & byte=0x3; rm16 & Reg16 ... { addflags(Reg16,rm16 ); Reg16 = Reg16 + rm16; resultflags(Reg16); } +:ADD Reg32,rm32 is vexMode=0 & opsize=1 & byte=0x3; rm32 & Reg32 ... & check_Reg32_dest ... { addflags(Reg32,rm32 ); Reg32 = Reg32 + rm32; build check_Reg32_dest; resultflags(Reg32); } +@ifdef IA64 +:ADD Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x3; rm64 & Reg64 ... { addflags(Reg64,rm64 ); Reg64 = Reg64 + rm64; resultflags(Reg64); } +@endif + +# See 'lockable.sinc' for memory destination, lockable variants +:AND AL,imm8 is vexMode=0 & byte=0x24; AL & imm8 { logicalflags(); AL = AL & imm8; resultflags( AL); } +:AND AX,imm16 is vexMode=0 & opsize=0 & byte=0x25; AX & imm16 { logicalflags(); AX = AX & imm16; resultflags( AX); } +:AND EAX,imm32 is vexMode=0 & opsize=1 & byte=0x25; EAX & check_EAX_dest & imm32 { logicalflags(); EAX = EAX & imm32; build check_EAX_dest; resultflags( EAX); } +@ifdef IA64 +:AND RAX,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x25; RAX & simm32 { logicalflags(); RAX = RAX & simm32; resultflags( RAX); } +@endif +:AND Rmr8,imm8 is vexMode=0 & $(BYTE_80_82); mod=3 & Rmr8 & reg_opcode=4; imm8 { logicalflags(); Rmr8 = Rmr8 & imm8; resultflags( Rmr8); } +:AND Rmr16,imm16 is vexMode=0 & opsize=0 & byte=0x81; mod=3 & Rmr16 & reg_opcode=4; imm16 { logicalflags(); Rmr16 = Rmr16 & imm16; resultflags( Rmr16); } +:AND Rmr32,imm32 is vexMode=0 & opsize=1 & byte=0x81; mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=4; imm32 { logicalflags(); Rmr32 = Rmr32 & imm32; build check_Rmr32_dest; resultflags( Rmr32); } +@ifdef IA64 +:AND Rmr64,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x81; mod=3 & Rmr64 & reg_opcode=4; simm32 { logicalflags(); Rmr64 = Rmr64 & simm32; resultflags( Rmr64); } +@endif +:AND Rmr16,usimm8_16 is vexMode=0 & opsize=0 & byte=0x83; mod=3 & Rmr16 & reg_opcode=4; usimm8_16 { logicalflags(); Rmr16 = Rmr16 & usimm8_16; resultflags( Rmr16); } +:AND Rmr32,usimm8_32 is vexMode=0 & opsize=1 & byte=0x83; mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=4; usimm8_32 { logicalflags(); Rmr32 = Rmr32 & usimm8_32; build check_Rmr32_dest; resultflags( Rmr32); } +@ifdef IA64 +:AND Rmr64,usimm8_64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x83; mod=3 & Rmr64 & reg_opcode=4; usimm8_64 { logicalflags(); Rmr64 = Rmr64 & usimm8_64; resultflags( Rmr64); } +@endif +:AND Rmr8,Reg8 is vexMode=0 & byte=0x20; mod=3 & Rmr8 & Reg8 { logicalflags(); Rmr8 = Rmr8 & Reg8; resultflags( Rmr8); } +:AND Rmr16,Reg16 is vexMode=0 & opsize=0 & byte=0x21; mod=3 & Rmr16 & Reg16 { logicalflags(); Rmr16 = Rmr16 & Reg16; resultflags( Rmr16); } +:AND Rmr32,Reg32 is vexMode=0 & opsize=1 & byte=0x21; mod=3 & Rmr32 & check_Rmr32_dest & Reg32 { logicalflags(); Rmr32 = Rmr32 & Reg32; build check_Rmr32_dest; resultflags( Rmr32); } +@ifdef IA64 +:AND Rmr64,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x21; mod=3 & Rmr64 & Reg64 { logicalflags(); Rmr64 = Rmr64 & Reg64; resultflags( Rmr64); } +@endif +:AND Reg8,rm8 is vexMode=0 & byte=0x22; rm8 & Reg8 ... { logicalflags(); Reg8 = Reg8 & rm8; resultflags( Reg8); } +:AND Reg16,rm16 is vexMode=0 & opsize=0 & byte=0x23; rm16 & Reg16 ... { logicalflags(); Reg16 = Reg16 & rm16; resultflags(Reg16); } +:AND Reg32,rm32 is vexMode=0 & opsize=1 & byte=0x23; rm32 & Reg32 ... & check_Reg32_dest ... { logicalflags(); Reg32 = Reg32 & rm32; build check_Reg32_dest; resultflags(Reg32); } +@ifdef IA64 +:AND Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x23; rm64 & Reg64 ... { logicalflags(); Reg64 = Reg64 & rm64; resultflags(Reg64); } +@endif + +#ARPL is not encodable in 64-bit mode +:ARPL rm16,Reg16 is $(LONGMODE_OFF) & vexMode=0 & bit64=0 & byte=0x63; rm16 & Reg16 ... { local rpldest=rm16&3; local rplsrc=Reg16&3; local rpldiff=rplsrc-rpldest; + ZF = rpldiff s> 0; rm16 = rm16 + (zext(CF) * rpldiff); } + +:BOUND Reg16,m16 is $(LONGMODE_OFF) & vexMode=0 & opsize=0 & byte=0x62; m16 & Reg16 ... { } +:BOUND Reg32,m32 is $(LONGMODE_OFF) & vexMode=0 & opsize=1 & byte=0x62; m32 & Reg32 ... { } + +#:BSF Reg16,rm16 is vexMode=0 & opsize=0 & byte=0xf; byte=0xbc; rm16 & Reg16 ... { ZF = rm16 == 0; +# choose = 0xffff * (zext((0xff & rm16) == 0)); +# mask = (0xf00 & choose) | (0xf | ~choose); +# pos = 8 & choose; +# choose = 0xffff * (zext((mask & rm16) == 0)); +# mask1 = (mask << 2) & (mask << 4); +# mask2 = (mask >> 2) & mask; +# mask = (mask1 & choose) | (mask2 | ~choose); +# pos = pos + (4 & choose); +# choose = 0xffff * (zext((mask & rm16) == 0)); +# mask1 = (mask << 1) & (mask << 2); +# mask2 = (mask >> 1) & mask; +# mask = (mask1 & choose) | (mask2 | ~choose); +# pos = pos + (2 & choose); +# choose = zext((mask & rm16) == 0); +# Reg16 = pos + choose; } + +:BSF Reg16,rm16 is vexMode=0 & opsize=0 & byte=0xf; byte=0xbc; rm16 & Reg16 ... +{ + bitIndex:2 = 0; + + ZF = ( rm16 == 0 ); + + if ( ZF == 1 ) goto ; + + + if ( ((rm16 >> bitIndex) & 0x0001) != 0 ) goto ; + bitIndex = bitIndex + 1; + goto ; + + + Reg16 = bitIndex; +} + +#:BSF Reg32,rm32 is vexMode=0 & opsize=1 & byte=0xf; byte=0xbc; rm32 & Reg32 ... & check_Reg32_dest ... { ZF = rm32 == 0; +# choose = 0xffffffff * (zext((0xffff & rm32) == 0)); +# mask = (0xff0000 & choose) | (0xff | ~choose); +# pos = 16 & choose; +# choose = 0xffffffff * (zext((mask & rm32) == 0)); +# mask1 = (mask << 4) & (mask << 8); +# mask2 = (mask >> 4) & mask; +# mask = (mask1 & choose) | (mask2 | ~choose); +# pos = pos + (8 & choose); +# choose = 0xffffffff * (zext((mask & rm32) == 0)); +# mask1 = (mask << 2) & (mask << 4); +# mask2 = (mask >> 2) & mask; +# mask = (mask1 & choose) | (mask2 | ~choose); +# pos = pos + (4 & choose); +# choose = 0xffffffff * (zext((mask & rm32) == 0)); +# mask1 = (mask << 1) & (mask << 2); +# mask2 = (mask >> 1) & mask; +# mask = (mask1 & choose) | (mask2 | ~choose); +# pos = pos + (2 & choose); +# choose = zext((mask & rm32) == 0); +# Reg32 = pos + choose; +# build check_Reg32_dest; } + +:BSF Reg32,rm32 is vexMode=0 & opsize=1 & byte=0xf; byte=0xbc; rm32 & Reg32 ... & check_Reg32_dest ... +{ + bitIndex:4 = 0; + + ZF = ( rm32 == 0 ); + + if ( ZF == 1 ) goto ; + + + if ( ((rm32 >> bitIndex) & 0x00000001) != 0 ) goto ; + bitIndex = bitIndex + 1; + goto ; + + + Reg32 = bitIndex; + build check_Reg32_dest; +} + +@ifdef IA64 +#:BSF Reg64,rm64 is vexMode=0 & opsize=2 & byte=0xf; byte=0xbc; rm64 & Reg64 ... { ZF = rm64 == 0; +## TODO: NEED TO EXTEND THIS TO 64bit op +# choose = 0xffffffff * (zext((0xffff & rm64) == 0)); +# mask = (0xff0000 & choose) | (0xff | ~choose); +# pos = 16 & choose; +# choose = 0xffffffff * (zext((mask & rm64) == 0)); +# mask1 = (mask << 4) & (mask << 8); +# mask2 = (mask >> 4) & mask; +# mask = (mask1 & choose) | (mask2 | ~choose); +# pos = pos + (8 & choose); +# choose = 0xffffffff * (zext((mask & rm64) == 0)); +# mask1 = (mask << 2) & (mask << 4); +# mask2 = (mask >> 2) & mask; +# mask = (mask1 & choose) | (mask2 | ~choose); +# pos = pos + (4 & choose); +# choose = 0xffffffff * (zext((mask & rm64) == 0)); +# mask1 = (mask << 1) & (mask << 2); +# mask2 = (mask >> 1) & mask; +# mask = (mask1 & choose) | (mask2 | ~choose); +# pos = pos + (2 & choose); +# choose = zext((mask & rm64) == 0); +# Reg64 = pos + choose; } + +:BSF Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0xbc; rm64 & Reg64 ... +{ + bitIndex:8 = 0; + + ZF = ( rm64 == 0 ); + + if ( ZF == 1 ) goto ; + + + if ( ((rm64 >> bitIndex) & 0x0000000000000001) != 0 ) goto ; + bitIndex = bitIndex + 1; + goto ; + + + Reg64 = bitIndex; +} +@endif + +#:BSR Reg16,rm16 is vexMode=0 & opsize=0 & byte=0xf; byte=0xbd; rm16 & Reg16 ... { ZF = rm16 == 0; +# choose = 0xffff * (zext((0xff00 & rm16) == 0)); +# mask = (0xf000 & ~choose) | (0xf0 | choose); +# pos = 16 - (8 & choose); +# choose = 0xffff * (zext((mask & rm16) == 0)); +# mask1 = (mask >> 2) & (mask >> 4); +# mask2 = (mask << 2) & mask; +# mask = (mask1 & choose) | (mask2 | ~choose); +# pos = pos - (4 & choose); +# choose = 0xffff * (zext((mask & rm16) == 0)); +# mask1 = (mask >> 1) & (mask >> 2); +# mask2 = (mask << 1) & mask; +# mask = (mask1 & choose) | (mask2 | ~choose); +# pos = pos - (2 & choose); +# choose = zext((mask & rm16) == 0); +# Reg16 = pos - choose; } + +:BSR Reg16,rm16 is vexMode=0 & opsize=0 & byte=0xf; byte=0xbd; rm16 & Reg16 ... +{ + bitIndex:2 = 15; + + ZF = ( rm16 == 0 ); + + if ( ZF == 1 ) goto ; + + + if ( (rm16 >> bitIndex) != 0 ) goto ; + bitIndex = bitIndex - 1; + goto ; + + + Reg16 = bitIndex; +} + +#:BSR Reg32,rm32 is vexMode=0 & opsize=1 & byte=0xf; byte=0xbd; rm32 & Reg32 ... & check_Reg32_dest ... { ZF = rm32 == 0; +# choose = 0xffffffff * (zext((0xffff0000 & rm32) == 0)); +# mask = (0xff000000 & ~choose) | (0xff00 | choose); +# pos = 32 - (16 & choose); +# choose = 0xffffffff * (zext((mask & rm32) == 0)); +# mask1 = (mask >> 4) & (mask >> 8); +# mask2 = (mask << 4) & mask; +# mask = (mask1 & choose) | (mask2 | ~choose); +# pos = pos - (8 & choose); +# choose = 0xffffffff * (zext((mask & rm32) == 0)); +# mask1 = (mask >> 2) & (mask >> 4); +# mask2 = (mask << 2) & mask; +# mask = (mask1 & choose) | (mask2 | ~choose); +# pos = pos - (4 & choose); +# choose = 0xffffffff * (zext((mask & rm32) == 0)); +# mask1 = (mask >> 1) & (mask >> 2); +# mask2 = (mask << 1) & mask; +# mask = (mask1 & choose) | (mask2 | ~choose); +# pos = pos - (2 & choose); +# choose = zext((mask & rm32) == 0); +# Reg32 = pos - choose; +# build check_Reg32_dest; } + +:BSR Reg32,rm32 is vexMode=0 & opsize=1 & byte=0xf; byte=0xbd; rm32 & Reg32 ... & check_Reg32_dest ... +{ + bitIndex:4 = 31; + + ZF = ( rm32 == 0 ); + + if ( ZF == 1 ) goto ; + + + if ( (rm32 >> bitIndex) != 0 ) goto ; + bitIndex = bitIndex - 1; + goto ; + + + Reg32 = bitIndex; + build check_Reg32_dest; +} + + +@ifdef IA64 +#:BSR Reg64,rm64 is vexMode=0 & opsize=2 & byte=0xf; byte=0xbd; rm64 & Reg64 ... { ZF = rm64 == 0; +## TODO: NEED TO EXTEND THIS TO 64bit op +# choose = 0xffffffff * (zext((0xffff0000 & rm64) == 0)); +# mask = (0xff000000 & ~choose) | (0xff00 | choose); +# pos = 32 - (16 & choose); +# choose = 0xffffffff * (zext((mask & rm64) == 0)); +# mask1 = (mask >> 4) & (mask >> 8); +# mask2 = (mask << 4) & mask; +# mask = (mask1 & choose) | (mask2 | ~choose); +# pos = pos - (8 & choose); +# choose = 0xffffffff * (zext((mask & rm64) == 0)); +# mask1 = (mask >> 2) & (mask >> 4); +# mask2 = (mask << 2) & mask; +# mask = (mask1 & choose) | (mask2 | ~choose); +# pos = pos - (4 & choose); +# choose = 0xffffffff * (zext((mask & rm64) == 0)); +# mask1 = (mask >> 1) & (mask >> 2); +# mask2 = (mask << 1) & mask; +# mask = (mask1 & choose) | (mask2 | ~choose); +# pos = pos - (2 & choose); +# choose = zext((mask & rm64) == 0); +# Reg64 = pos - choose; } + +:BSR Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0xbd; rm64 & Reg64 ... +{ + bitIndex:8 = 63; + + ZF = ( rm64 == 0 ); + + if ( ZF == 1 ) goto ; + + + if ( (rm64 >> bitIndex) != 0 ) goto ; + bitIndex = bitIndex - 1; + goto ; + + + Reg64 = bitIndex; +} + +@endif + +:BSWAP Rmr32 is vexMode=0 & byte=0xf; row=12 & page=1 & Rmr32 & check_Rmr32_dest + { local tmp = (Rmr32 & 0xff000000) >> 24 ; + tmp = tmp | ((Rmr32 & 0x00ff0000) >> 8 ); + tmp = tmp | ((Rmr32 & 0x0000ff00) << 8 ); + Rmr32 = tmp | ((Rmr32 & 0x000000ff) << 24); + build check_Rmr32_dest; } +@ifdef IA64 +:BSWAP Rmr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; row=12 & page=1 & Rmr64 + { local tmp = (Rmr64 & 0xff00000000000000) >> 56 ; + tmp = tmp | ((Rmr64 & 0x00ff000000000000) >> 40 ); + tmp = tmp | ((Rmr64 & 0x0000ff0000000000) >> 24 ); + tmp = tmp | ((Rmr64 & 0x000000ff00000000) >> 8 ); + tmp = tmp | ((Rmr64 & 0x00000000ff000000) << 8 ); + tmp = tmp | ((Rmr64 & 0x0000000000ff0000) << 24 ); + tmp = tmp | ((Rmr64 & 0x000000000000ff00) << 40 ); + Rmr64 = tmp | ((Rmr64 & 0x00000000000000ff) << 56); } +@endif + +:BT Rmr16,Reg16 is vexMode=0 & opsize=0 & byte=0xf; byte=0xa3; mod=3 & Rmr16 & Reg16 { CF = ((Rmr16 >> (Reg16 & 0xf)) & 1) != 0; } +:BT Mem,Reg16 is vexMode=0 & opsize=0 & byte=0xf; byte=0xa3; Mem & Reg16 ... { local ptr = Mem + (sext(Reg16) s>> 3); + CF = ((*:1 ptr >> (Reg16 & 0x7)) & 1) != 0; } +:BT Rmr32,Reg32 is vexMode=0 & opsize=1 & byte=0xf; byte=0xa3; mod=3 & Rmr32 & Reg32 { CF = ((Rmr32 >> (Reg32 & 0x1f)) & 1) != 0; } +:BT Mem,Reg32 is vexMode=0 & opsize=1 & byte=0xf; byte=0xa3; Mem & Reg32 ... { +@ifdef IA64 + local ptr = Mem + (sext(Reg32) s>> 3); +@else + local ptr = Mem + (Reg32 s>> 3); +@endif + CF = ((*:1 ptr >> (Reg32 & 0x7)) & 1) != 0; +} +@ifdef IA64 +:BT Rmr64,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0xa3; mod=3 & Rmr64 & Reg64 { CF = ((Rmr64 >> (Reg64 & 0x3f)) & 1) != 0; } +:BT Mem,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0xa3; Mem & Reg64 ... { local ptr = Mem + (Reg64 s>> 3); + CF = ((*:1 ptr >> (Reg64 & 0x7)) & 1) != 0; } +@endif +:BT rm16,imm8 is vexMode=0 & opsize=0 & byte=0xf; byte=0xba; (rm16 & reg_opcode=4 ...); imm8 { CF = ((rm16 >> (imm8 & 0x0f)) & 1) != 0; } +:BT rm32,imm8 is vexMode=0 & opsize=1 & byte=0xf; byte=0xba; (rm32 & reg_opcode=4 ...); imm8 { CF = ((rm32 >> (imm8 & 0x1f)) & 1) != 0; } +@ifdef IA64 +:BT rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0xba; (rm64 & reg_opcode=4 ...); imm8 { CF = ((rm64 >> (imm8 & 0x3f)) & 1) != 0; } +@endif + +# See 'lockable.sinc' for memory destination, lockable variants +:BTC Rmr16,Reg16 is vexMode=0 & opsize=0 & byte=0xf; byte=0xbb; mod=3 & Rmr16 & Reg16 { local bit=Reg16&0xf; local val=(Rmr16>>bit)&1; Rmr16=Rmr16^(1<>bit)&1; CF=(val!=0); Rmr32=Rmr32^(1<>bit)&1; Rmr64=Rmr64^(1<>bit)&1; Rmr16=Rmr16^(1<>bit)&1; CF=(val!=0); Rmr32=Rmr32^(1<>bit)&1; Rmr64=Rmr64^(1<>bit)&1; Rmr16=Rmr16 & ~(1<>bit)&1; CF=(val!=0); Rmr32=Rmr32 & ~(1<>bit)&1; Rmr64=Rmr64 & ~(1<>bit)&1; Rmr16=Rmr16 & ~(1<>bit)&1; CF=(val!=0); Rmr32=Rmr32 & ~(1<>bit)&1; Rmr64=Rmr64 & ~(1<>bit)&1; Rmr16=Rmr16 | (1<>bit)&1; CF=(val!=0); Rmr32=Rmr32 | (1<>bit)&1; Rmr64=Rmr64 | (1<>bit)&1; Rmr16=Rmr16 | (1<>bit)&1; CF=(val!=0); Rmr32=Rmr32 | (1<>bit)&1; Rmr64=Rmr64 | (1<; + EAX = Rmr32; + build check_EAX_dest; + goto inst_next; + + Rmr32 = Reg32; + build check_Rmr32_dest; +} +@ifdef IA64 +:CMPXCHG Rmr64,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0xb1; mod=3 & Rmr64 & Reg64 { subflags(RAX,Rmr64); local tmp=RAX-Rmr64; resultflags(tmp); + local diff = Rmr64^Reg64; Rmr64 = Rmr64 ^ (zext(ZF) * diff); + diff = RAX ^ Rmr64; RAX = RAX ^ (zext(ZF==0) * diff); } +@endif + +# CMPXCHG8B See 'lockable.sinc' for memory destination, lockable variants + +# This "bad_CMPXCHG8B" instruction encoding was not meant to be part of the x86 language. +# It was allowed by a toolchain (at Intel) and was encoded into at least one library. +# GCC does not recognize it. It does not make any semantic sense. +define pcodeop bad_CMPXCHG8B; +:bad_CMPXCHG8B r32 is vexMode=0 & byte=0xf; byte=0xc7; ( mod = 0b11 & reg_opcode=0b001 ) & r32 { + r32 = bad_CMPXCHG8B(r32); +} + +# CMPXCHG16B See 'lockable.sinc' for memory destination, lockable variants + +define pcodeop cpuid; +define pcodeop cpuid_basic_info; +define pcodeop cpuid_Version_info; +define pcodeop cpuid_cache_tlb_info; +define pcodeop cpuid_serial_info; +define pcodeop cpuid_Deterministic_Cache_Parameters_info; +define pcodeop cpuid_MONITOR_MWAIT_Features_info; +define pcodeop cpuid_Thermal_Power_Management_info; +define pcodeop cpuid_Extended_Feature_Enumeration_info; +define pcodeop cpuid_Direct_Cache_Access_info; +define pcodeop cpuid_Architectural_Performance_Monitoring_info; +define pcodeop cpuid_Extended_Topology_info; +define pcodeop cpuid_Processor_Extended_States_info; +define pcodeop cpuid_Quality_of_Service_info; +define pcodeop cpuid_brand_part1_info; +define pcodeop cpuid_brand_part2_info; +define pcodeop cpuid_brand_part3_info; + +# CPUID is very difficult to implement correctly +# The side-effects of the call will show up, but not the correct values + +:CPUID is vexMode=0 & byte=0xf; byte=0xa2 { + local tmp:16; + if (EAX == 0) goto ; + if (EAX == 1) goto ; + if (EAX == 2) goto ; + if (EAX == 3) goto ; + if (EAX == 0x4) goto ; + if (EAX == 0x5) goto ; + if (EAX == 0x6) goto ; + if (EAX == 0x7) goto ; + if (EAX == 0x9) goto ; + if (EAX == 0xa) goto ; + if (EAX == 0xb) goto ; + if (EAX == 0xd) goto ; + if (EAX == 0xf) goto ; + if (EAX == 0x80000002) goto ; + if (EAX == 0x80000003) goto ; + if (EAX == 0x80000004) goto ; + tmp = cpuid(EAX, ECX); + goto ; + + tmp = cpuid_basic_info(EAX, ECX); + goto ; + + tmp = cpuid_Version_info(EAX, ECX); + goto ; + + tmp = cpuid_cache_tlb_info(EAX, ECX); + goto ; + + tmp = cpuid_serial_info(EAX, ECX); + goto ; + + tmp = cpuid_Deterministic_Cache_Parameters_info(EAX, ECX); + goto ; + + tmp = cpuid_MONITOR_MWAIT_Features_info(EAX, ECX); + goto ; + + tmp = cpuid_Thermal_Power_Management_info(EAX, ECX); + goto ; + + tmp = cpuid_Extended_Feature_Enumeration_info(EAX, ECX); + goto ; + + tmp = cpuid_Direct_Cache_Access_info(EAX, ECX); + goto ; + + tmp = cpuid_Architectural_Performance_Monitoring_info(EAX, ECX); + goto ; + + tmp = cpuid_Extended_Topology_info(EAX, ECX); + goto ; + + tmp = cpuid_Processor_Extended_States_info(EAX, ECX); + goto ; + + tmp = cpuid_Quality_of_Service_info(EAX, ECX); + goto ; + + tmp = cpuid_brand_part1_info(EAX, ECX); + goto ; + + tmp = cpuid_brand_part2_info(EAX, ECX); + goto ; + + tmp = cpuid_brand_part3_info(EAX, ECX); + goto ; + +@ifdef IA64 + RAX = zext(tmp[0,32]); + RBX = zext(tmp[32,32]); + RDX = zext(tmp[64,32]); + RCX = zext(tmp[96,32]); +@else + EAX = tmp[0,32]; + EBX = tmp[32,32]; + EDX = tmp[64,32]; + ECX = tmp[96,32]; +@endif +} + + +:DAA is $(LONGMODE_OFF) & vexMode=0 & byte=0x27 { local car = ((AL & 0xf) > 9) | AF; + AL = AL + 6 * car; + CF = CF | car * carry(AL,6); + AF = car; + car = ((AL & 0xf0) > 0x90) | CF; + AL = AL + 0x60 * car; + CF = car; } +:DAS is $(LONGMODE_OFF) & vexMode=0 & byte=0x2f { local car = ((AL & 0xf) > 9) | AF; + AL = AL - 6 * car; + CF = CF | car * (AL < 6); + AF = car; + car = (AL > 0x9f) | CF; + AL = AL - 0x60 * car; + CF = car; } + +# See 'lockable.sinc' for memory destination, lockable variants +:DEC Rmr8 is vexMode=0 & byte=0xfe; mod=3 & Rmr8 & reg_opcode=1 { OF = sborrow(Rmr8,1); Rmr8 = Rmr8 - 1; resultflags( Rmr8); } +:DEC Rmr16 is vexMode=0 & opsize=0 & byte=0xff; mod=3 & Rmr16 & reg_opcode=1 { OF = sborrow(Rmr16,1); Rmr16 = Rmr16 - 1; resultflags(Rmr16); } +:DEC Rmr32 is vexMode=0 & opsize=1 & byte=0xff; mod=3 & Rmr32 & check_rm32_dest & reg_opcode=1 { OF = sborrow(Rmr32,1); Rmr32 = Rmr32 - 1; build check_rm32_dest; resultflags(Rmr32); } +@ifdef IA64 +:DEC Rmr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xff; mod=3 & Rmr64 & reg_opcode=1 { OF = sborrow(Rmr64,1); Rmr64 = Rmr64 - 1; resultflags(Rmr64); } +@endif + +:DEC Rmr16 is $(LONGMODE_OFF) & vexMode=0 & opsize=0 & row=4 & page=1 & Rmr16 { OF = sborrow(Rmr16,1); Rmr16 = Rmr16 - 1; resultflags( Rmr16); } +:DEC Rmr32 is $(LONGMODE_OFF) & vexMode=0 & opsize=1 & row=4 & page=1 & Rmr32 & check_Rmr32_dest { OF = sborrow(Rmr32,1); Rmr32 = Rmr32 - 1; build check_Rmr32_dest; resultflags( Rmr32); } + +:DIV rm8 is vexMode=0 & byte=0xf6; rm8 & reg_opcode=6 ... { rm8ext:2 = zext(rm8); + local quotient = AX / rm8ext; # DE exception if quotient doesn't fit in AL + local rem = AX % rm8ext; + AL = quotient:1; + AH = rem:1; } +:DIV rm16 is vexMode=0 & opsize=0 & byte=0xf7; rm16 & reg_opcode=6 ... { rm16ext:4 = zext(rm16); + tmp:4 = (zext(DX) << 16) | zext(AX); # DE exception if quotient doesn't fit in AX + local quotient = tmp / rm16ext; + AX = quotient:2; + local rem = tmp % rm16ext; + DX = rem:2; } +:DIV rm32 is vexMode=0 & opsize=1 & byte=0xf7; rm32 & check_EDX_dest ... & check_EAX_dest ... & reg_opcode=6 ... { rm32ext:8 = zext(rm32); + tmp:8 = (zext(EDX) << 32) | zext(EAX); # DE exception if quotient doesn't fit in EAX + local quotient = tmp / rm32ext; + EAX = quotient:4; + build check_EAX_dest; + local rem = tmp % rm32ext; + EDX = rem:4; + build check_EDX_dest; } +@ifdef IA64 +:DIV rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf7; rm64 & reg_opcode=6 ... { rm64ext:16 = zext(rm64); + tmp:16 = (zext(RDX) << 64) | zext(RAX); # DE exception if quotient doesn't fit in RAX + local quotient = tmp / rm64ext; + RAX = quotient:8; + local rem = tmp % rm64ext; + RDX = rem:8; } +@endif + +enterFrames: low5 is low5 { tmp:1 = low5; export tmp; } + +@ifdef IA64 +:ENTER imm16,enterFrames is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0xc8; imm16; enterFrames & low5=0x00 { + push88(RBP); + RBP = RSP; + RSP = RSP - imm16; +} + +:ENTER imm16,enterFrames is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0xc8; imm16; enterFrames & low5=0x01 { + push88(RBP); + frameTemp:8 = RSP; + + push88(frameTemp); + RBP = frameTemp; + RSP = RSP - imm16; +} + +:ENTER imm16,enterFrames is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=2 & byte=0xc8; imm16; enterFrames { + push88(RBP); + frameTemp:8 = RSP; + + RSPt:$(SIZE) = RSP; + RBPt:$(SIZE) = RBP; + ii:1 = enterFrames - 1; + + RBPt = RBPt - 8; + RSPt = RSPt - 8; + *:8 RSPt = *:8 RBPt; + ii = ii - 1; + if (ii s> 0) goto ; + + tmp_offset:8 = 8 * zext(enterFrames - 1); + RSP = RSP - tmp_offset; + RBP = RBP - tmp_offset; + + push88(frameTemp); + RBP = frameTemp; + RSP = RSP - imm16; +} + +:ENTER imm16,enterFrames is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=1 & byte=0xc8; imm16; enterFrames { + push88(RBP); + frameTemp:8 = RSP; + + RSPt:$(SIZE) = RSP; + RBPt:$(SIZE) = RBP; + ii:1 = enterFrames - 1; + + RBPt = RBPt - 4; + RSPt = RSPt - 4; + *:4 RSPt = *:4 RBPt; + ii = ii - 1; + if (ii s> 0) goto ; + + tmp_offset:8 = 4 * zext(enterFrames - 1); + RSP = RSP - tmp_offset; + RBP = RBP - tmp_offset; + + push88(frameTemp); + RBP = frameTemp; + RSP = RSP - imm16; +} + +:ENTER imm16,enterFrames is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=0 & byte=0xc8; imm16; enterFrames { + push88(RBP); + frameTemp:8 = RSP; + + RSPt:$(SIZE) = RSP; + RBPt:$(SIZE) = RBP; + ii:1 = enterFrames - 1; + + RBPt = RBPt - 2; + RSPt = RSPt - 2; + *:2 RSPt = *:2 RBPt; + ii = ii - 1; + if (ii s> 0) goto ; + + tmp_offset:8 = 2 * zext(enterFrames - 1); + RSP = RSP - tmp_offset; + RBP = RBP - tmp_offset; + + push88(frameTemp); + RBP = frameTemp; + RSP = RSP - imm16; +} +@endif + +:ENTER imm16,enterFrames is vexMode=0 & addrsize=1 & byte=0xc8; imm16; enterFrames & low5=0x00 { + push44(EBP); + EBP = ESP; + ESP = ESP - imm16; +} + +:ENTER imm16,enterFrames is vexMode=0 & addrsize=1 & byte=0xc8; imm16; enterFrames & low5=0x01 { + push44(EBP); + frameTemp:4 = ESP; + + push44(frameTemp); + EBP = frameTemp; + ESP = ESP - imm16; +} + +:ENTER imm16,enterFrames is vexMode=0 & addrsize=1 & opsize=1 & byte=0xc8; imm16; enterFrames { + push44(EBP); + frameTemp:4 = ESP; + +@ifdef IA64 + ESPt:$(SIZE) = zext(ESP); + EBPt:$(SIZE) = zext(EBP); +@else + ESPt:$(SIZE) = ESP; + EBPt:$(SIZE) = EBP; +@endif + ii:1 = enterFrames - 1; + + EBPt = EBPt - 4; + ESPt = ESPt - 4; + *:4 ESPt = *:4 EBPt; + ii = ii - 1; + if (ii s> 0) goto ; + + tmp_offset:4 = 4 * zext(enterFrames - 1); + ESP = ESP - tmp_offset; + EBP = EBP - tmp_offset; + + push44(frameTemp); + EBP = frameTemp; + ESP = ESP - imm16; +} + +:ENTER imm16,enterFrames is vexMode=0 & addrsize=1 & opsize=0 & byte=0xc8; imm16; enterFrames { + push44(EBP); + frameTemp:4 = ESP; + +@ifdef IA64 + ESPt:$(SIZE) = zext(ESP); + EBPt:$(SIZE) = zext(EBP); +@else + ESPt:$(SIZE) = ESP; + EBPt:$(SIZE) = EBP; +@endif + ii:1 = enterFrames - 1; + + EBPt = EBPt - 2; + ESPt = ESPt - 2; + *:2 ESPt = *:2 EBPt; + ii = ii - 1; + if (ii s> 0) goto ; + + tmp_offset:4 = 2 * zext(enterFrames - 1); + ESP = ESP - tmp_offset; + EBP = EBP - tmp_offset; + + push44(frameTemp); + EBP = frameTemp; + ESP = ESP - imm16; +} + +:ENTER imm16,enterFrames is vexMode=0 & addrsize=0 & byte=0xc8; imm16; enterFrames & low5=0x00 { + push22(BP); + BP = SP; + SP = SP - imm16; +} + +:ENTER imm16,enterFrames is vexMode=0 & addrsize=0 & byte=0xc8; imm16; enterFrames & low5=0x01 { + push22(BP); + frameTemp:2 = SP; + + push22(frameTemp); + BP = frameTemp; + SP = SP - imm16; +} + +:ENTER imm16,enterFrames is vexMode=0 & seg16 & addrsize=0 & opsize=1 & byte=0xc8; imm16; enterFrames { + push24(zext(BP)); + frameTemp:2 = SP; + + SPt:2 = SP; + BPt:2 = BP; + ii:1 = enterFrames - 1; + + + BPt = BPt - 4; + tmp2:$(SIZE) = segment(seg16,BPt); + SPt = SPt - 4; + tmp:$(SIZE) = segment(SS,SPt); + *:4 tmp = *:4 tmp2; + ii = ii - 1; + if (ii s> 0) goto ; + + tmp_offset:2 = 4 * zext(enterFrames - 1); + SP = SP - tmp_offset; + BP = BP - tmp_offset; + + push24(zext(frameTemp)); + BP = frameTemp; + SP = SP - imm16; +} + +:ENTER imm16,enterFrames is vexMode=0 & seg16 & addrsize=0 & opsize=0 & byte=0xc8; imm16; enterFrames { + push22(BP); + frameTemp:2 = SP; + + SPt:2 = SP; + BPt:2 = BP; + ii:1 = enterFrames - 1; + + BPt = BPt - 2; + tmp2:$(SIZE) = segment(seg16,BPt); + SPt = SPt - 2; + tmp:$(SIZE) = segment(SS,SPt); + *:2 tmp = *:2 tmp2; + ii = ii - 1; + if (ii s> 0) goto ; + + tmp_offset:2 = 2 * zext(enterFrames - 1); + SP = SP - tmp_offset; + BP = BP - tmp_offset; + + push22(frameTemp); + BP = frameTemp; + SP = SP - imm16; +} + +# Informs the 80287 coprocessor of the switch to protected mode, treated as NOP for 80387 and later. +# We used to have a pseudo-op, but as this is a legacy instruction which is now explicitly treated +# as a NOP. We treat it as a NOP as well. +:FSETPM is vexMode=0 & byte=0xdb; byte=0xe4 { } # 80287 set protected mode + +:HLT is vexMode=0 & byte=0xf4 { goto inst_start; } + +:IDIV rm8 is vexMode=0 & byte=0xf6; rm8 & reg_opcode=7 ... { rm8ext:2 = sext(rm8); + local quotient = AX s/ rm8ext; # DE exception if quotient doesn't fit in AL + local rem = AX s% rm8ext; + AL = quotient:1; + AH = rem:1; } +:IDIV rm16 is vexMode=0 & opsize=0 & byte=0xf7; rm16 & reg_opcode=7 ... { rm16ext:4 = sext(rm16); + tmp:4 = (zext(DX) << 16) | zext(AX); # DE exception if quotient doesn't fit in AX + local quotient = tmp s/ rm16ext; + AX = quotient:2; + local rem = tmp s% rm16ext; + DX = rem:2; } +:IDIV rm32 is vexMode=0 & opsize=1 & byte=0xf7; rm32 & check_EAX_dest ... & check_EDX_dest ... & reg_opcode=7 ... { rm32ext:8 = sext(rm32); + tmp:8 = (zext(EDX) << 32) | zext(EAX); # DE exception if quotient doesn't fit in EAX + local quotient = tmp s/ rm32ext; + EAX = quotient:4; + build check_EAX_dest; + local rem = tmp s% rm32ext; + EDX = rem:4; + build check_EDX_dest; } +@ifdef IA64 +:IDIV rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf7; rm64 & reg_opcode=7 ... { rm64ext:16 = sext(rm64); + tmp:16 = (zext(RDX) << 64) | zext(RAX); # DE exception if quotient doesn't fit in RAX + local quotient = tmp s/ rm64ext; + RAX = quotient:8; + local rem = tmp s% rm64ext; + RDX = rem:8; } +@endif + +:IMUL rm8 is vexMode=0 & byte=0xf6; rm8 & reg_opcode=5 ... { AX = sext(AL) * sext(rm8); imultflags(AL,AX); } +:IMUL rm16 is vexMode=0 & opsize=0 & byte=0xf7; rm16 & reg_opcode=5 ... { tmp:4 = sext(AX) * sext(rm16); + DX = tmp(2); AX = tmp(0); imultflags(AX,tmp); } +:IMUL rm32 is vexMode=0 & opsize=1 & byte=0xf7; rm32 & check_EAX_dest ... & check_EDX_dest ... & reg_opcode=5 ... { tmp:8 = sext(EAX) * sext(rm32); + EDX = tmp(4); build check_EDX_dest; EAX = tmp(0); build check_EAX_dest; imultflags(EAX,tmp); } +@ifdef IA64 +# We do a second multiply so emulator(s) that only have precision up to 64 bits will still get lower 64 bits correct +:IMUL rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf7; rm64 & reg_opcode=5 ... { tmp:16 = sext(RAX) * sext(rm64); + RAX = RAX * rm64; RDX = tmp(8); imultflags(RAX,tmp); } +@endif +:IMUL Reg16,rm16 is vexMode=0 & opsize=0 & byte=0xf; byte=0xaf; rm16 & Reg16 ... { tmp:4 = sext(Reg16) * sext(rm16); + Reg16 = tmp(0); high:2 = tmp(2); imultflags(Reg16,tmp);} +:IMUL Reg32,rm32 is vexMode=0 & opsize=1 & byte=0xf; byte=0xaf; rm32 & Reg32 ... & check_Reg32_dest ... { tmp:8 = sext(Reg32) * sext(rm32); + Reg32 = tmp(0); high:4 = tmp(4); imultflags(Reg32,tmp); build check_Reg32_dest; } +@ifdef IA64 +# We do a second multiply so emulator(s) that only have precision up to 64 bits will still get lower 64 bits correct +:IMUL Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0xaf; rm64 & Reg64 ... { tmp:16 = sext(Reg64) * sext(rm64); + Reg64 = Reg64 * rm64; high:8 = tmp(8); imultflags(Reg64,tmp);} +@endif +:IMUL Reg16,rm16,simm8_16 is vexMode=0 & opsize=0 & byte=0x6b; (rm16 & Reg16 ...) ; simm8_16 { tmp:4 = sext(rm16) * sext(simm8_16); + Reg16 = tmp(0); high:2 = tmp(2); imultflags(Reg16,tmp);} +:IMUL Reg32,rm32,simm8_32 is vexMode=0 & opsize=1 & byte=0x6b; (rm32 & Reg32 ... & check_Reg32_dest ... ) ; simm8_32 { tmp:8 = sext(rm32) * sext(simm8_32); + Reg32 = tmp(0); high:4 = tmp(4); imultflags(Reg32,tmp); build check_Reg32_dest; } +@ifdef IA64 +# We do a second multiply so emulator(s) that only have precision up to 64 bits will still get lower 64 bits correct +:IMUL Reg64,rm64,simm8_64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x6b; (rm64 & Reg64 ...) ; simm8_64 { tmp:16 = sext(rm64) * sext(simm8_64); + Reg64 = rm64 * simm8_64; high:8 = tmp(8); imultflags(Reg64,tmp);} +@endif +:IMUL Reg16,rm16,simm16_16 is vexMode=0 & opsize=0 & byte=0x69; (rm16 & Reg16 ...) ; simm16_16 { tmp:4 = sext(rm16) * sext(simm16_16); + Reg16 = tmp(0); high:2 = tmp(2); imultflags(Reg16,tmp);} +:IMUL Reg32,rm32,simm32_32 is vexMode=0 & opsize=1 & byte=0x69; (rm32 & Reg32 ... & check_Reg32_dest ...) ; simm32_32 { tmp:8 = sext(rm32) * sext(simm32_32); + Reg32 = tmp(0); high:4 = tmp(4); imultflags(Reg32,tmp); build check_Reg32_dest; } +@ifdef IA64 +:IMUL Reg64,rm64,simm32_32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x69; (rm64 & Reg64 ...) ; simm32_32 { tmp:16 = sext(rm64) * sext(simm32_32); + Reg64 = rm64 * sext(simm32_32); high:8 = tmp(8); imultflags(Reg64,tmp);} +@endif + +# these appear in intelman2.pdf, but do they really exist? +#:IMUL Reg16,simm8_16 is vexMode=0 & opsize=0 & byte=0x6b; Reg16; simm8_16 +#:IMUL Reg32,simm8_32 is vexMode=0 & opsize=1 & byte=0x6b; Reg32; simm8_32 +#:IMUL Reg16,simm16 is vexMode=0 & opsize=0 & byte=0x69; Reg16; simm16 +#:IMUL Reg32,simm32 is vexMode=0 & opsize=1 & byte=0x69; Reg32; simm32 + +:IN AL, imm8 is vexMode=0 & AL & (byte=0xe4; imm8) { tmp:1 = imm8; AL = in(tmp); } +:IN AX, imm8 is vexMode=0 & opsize=0 & AX & (byte=0xe5; imm8) { tmp:1 = imm8; AX = in(tmp); } +:IN EAX, imm8 is vexMode=0 & opsize=1 & EAX & check_EAX_dest & (byte=0xe5; imm8) { tmp:1 = imm8; EAX = in(tmp); build check_EAX_dest; } +@ifdef IA64 +:IN RAX, imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & RAX & (byte=0xe5; imm8) { tmp:1 = imm8; RAX = in(tmp); } +@endif +:IN AL, DX is vexMode=0 & AL & DX & (byte=0xec) { AL = in(DX); } +:IN AX, DX is vexMode=0 & opsize=0 & AX & DX & (byte=0xed) { AX = in(DX); } +:IN EAX, DX is vexMode=0 & opsize=1 & EAX & check_EAX_dest & DX & (byte=0xed) { EAX = in(DX); build check_EAX_dest; } +@ifdef IA64 +:IN RAX, DX is $(LONGMODE_ON) & vexMode=0 & opsize=2 & RAX & DX & (byte=0xed) { RAX = in(DX); } +@endif + +# See 'lockable.sinc' for memory destination, lockable variants +:INC Rmr8 is vexMode=0 & byte=0xfe; mod=3 & Rmr8 & reg_opcode=0 { OF = scarry(Rmr8,1); Rmr8 = Rmr8 + 1; resultflags( Rmr8); } +:INC Rmr16 is vexMode=0 & opsize=0 & byte=0xff; mod=3 & Rmr16 & reg_opcode=0 { OF = scarry(Rmr16,1); Rmr16 = Rmr16 + 1; resultflags(Rmr16); } +:INC Rmr32 is vexMode=0 & opsize=1 & byte=0xff; mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=0 { OF = scarry(Rmr32,1); Rmr32 = Rmr32 + 1; build check_Rmr32_dest; resultflags(Rmr32); } +@ifdef IA64 +:INC Rmr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xff; mod=3 & Rmr64 & reg_opcode=0 { OF = scarry(Rmr64,1); Rmr64 = Rmr64 + 1; resultflags(Rmr64); } +@endif + +:INC Rmr16 is $(LONGMODE_OFF) & vexMode=0 & opsize=0 & row = 4 & page = 0 & Rmr16 { OF = scarry(Rmr16,1); Rmr16 = Rmr16 + 1; resultflags( Rmr16); } +:INC Rmr32 is $(LONGMODE_OFF) & vexMode=0 & opsize=1 & row = 4 & page = 0 & Rmr32 { OF = scarry(Rmr32,1); Rmr32 = Rmr32 + 1; resultflags( Rmr32); } + +:INSB^rep^reptail eseDI1,DX is vexMode=0 & rep & reptail & byte=0x6c & eseDI1 & DX { build rep; build eseDI1; eseDI1 = in(DX); build reptail; } +:INSW^rep^reptail eseDI2,DX is vexMode=0 & rep & reptail & opsize=0 & byte=0x6d & eseDI2 & DX { build rep; build eseDI2; eseDI2 = in(DX); build reptail; } +:INSD^rep^reptail eseDI4,DX is vexMode=0 & rep & reptail & opsize=1 & byte=0x6d & eseDI4 & DX { build rep; build eseDI4; eseDI4 = in(DX); build reptail; } +:INSD^rep^reptail eseDI4,DX is vexMode=0 & rep & reptail & opsize=2 & byte=0x6d & eseDI4 & DX { build rep; build eseDI4; eseDI4 = in(DX); build reptail; } + +:INT1 is vexMode=0 & byte=0xf1 { tmp:1 = 0x1; intloc:$(SIZE) = swi(tmp); call [intloc]; return [0:1]; } +:INT3 is vexMode=0 & byte=0xcc { tmp:1 = 0x3; intloc:$(SIZE) = swi(tmp); call [intloc]; return [0:1]; } +:INT imm8 is vexMode=0 & byte=0xcd; imm8 { tmp:1 = imm8; intloc:$(SIZE) = swi(tmp); call [intloc]; } +:INTO is $(LONGMODE_OFF) & vexMode=0 & byte=0xce +{ + tmp:1 = 0x4; + intloc:$(SIZE) = swi(tmp); + + if (OF != 1) goto ; + call [intloc]; + +} + +:INVD is vexMode=0 & byte=0xf; byte=0x8 {} +:INVLPG Mem is vexMode=0 & byte=0xf; byte=0x1; ( reg_opcode=7 ) ... & Mem { invlpg(Mem); } + +:INVLPGA is vexMode=0 & addrsize=0 & byte=0xf; byte=0x1; byte=0xDF { invlpga(AX,ECX); } +:INVLPGA is vexMode=0 & addrsize=1 & byte=0xf; byte=0x1; byte=0xDF { invlpga(EAX,ECX); } +@ifdef IA64 +:INVLPGA is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0xf; byte=0x1; byte=0xDF { invlpga(RAX,ECX); } +@endif + +:INVPCID r32, m128 is vexMode=0 & addrsize=1 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x82; r32 ... & m128 { invpcid(r32, m128); } +@ifdef IA64 +:INVPCID r64, m128 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x82; r64 ... & m128 { invpcid(r64, m128); } +@endif + +:IRET is vexMode=0 & addrsize=0 & opsize=0 & byte=0xcf { pop22(IP); EIP=zext(IP); pop22(CS); pop22(flags); return [EIP]; } +:IRET is vexMode=0 & addrsize=1 & opsize=0 & byte=0xcf { pop42(IP); EIP=zext(IP); pop42(CS); pop42(flags); return [EIP]; } +@ifdef IA64 +:IRET is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=0 & byte=0xcf { pop82(IP); RIP=zext(IP); pop82(CS); pop82(flags); return [RIP]; } +@endif +:IRETD is vexMode=0 & addrsize=0 & opsize=1 & byte=0xcf { pop24(EIP); tmp:4=0; pop24(tmp); CS=tmp(0); pop24(tmp); flags=tmp(0); return [EIP]; } +:IRETD is vexMode=0 & addrsize=1 & opsize=1 & byte=0xcf { pop44(EIP); tmp:4=0; pop44(tmp); CS=tmp(0); pop44(eflags); return [EIP]; } +@ifdef IA64 +:IRETD is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=1 & byte=0xcf { pop84(EIP); RIP=zext(EIP); tmp:4=0; pop84(tmp); CS=tmp(0); pop84(eflags); return [RIP]; } +:IRETQ is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=2 & byte=0xcf { pop88(RIP); tmp:8=0; pop88(tmp); CS=tmp(0); pop88(rflags); return [RIP]; } +@endif + +:J^cc rel8 is vexMode=0 & row=7 & cc; rel8 { if (cc) goto rel8; } +:J^cc rel16 is vexMode=0 & bit64=0 & opsize=0 & byte=0xf; row=8 & cc; rel16 { if (cc) goto rel16; } +:J^cc rel32 is vexMode=0 & opsize=1 & byte=0xf; row=8 & cc; rel32 { if (cc) goto rel32; } +:J^cc rel32 is vexMode=0 & opsize=2 & byte=0xf; row=8 & cc; rel32 { if (cc) goto rel32; } +# The following is vexMode=0 & picked up by the line above. rel32 works for both 32 and 64 bit +#@ifdef IA64 +#:J^cc rel32 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0xf; row=8 & cc; rel32 { if (cc) goto rel32; } +#@endif + +:JCXZ rel8 is vexMode=0 & opsize=0 & byte=0xe3; rel8 { if (CX==0) goto rel8; } +:JECXZ rel8 is vexMode=0 & opsize=1 & byte=0xe3; rel8 { if (ECX==0) goto rel8; } +@ifdef IA64 +:JRCXZ rel8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xe3; rel8 { if (RCX==0) goto rel8; } +@endif + +:JMP rel8 is vexMode=0 & byte=0xeb; rel8 { goto rel8; } +:JMP rel16 is vexMode=0 & opsize=0 & byte=0xe9; rel16 { goto rel16; } +:JMP rel32 is vexMode=0 & opsize=1 & byte=0xe9; rel32 { goto rel32; } +:JMP rel32 is vexMode=0 & opsize=2 & byte=0xe9; rel32 { goto rel32; } +:JMP rm16 is vexMode=0 & addrsize=0 & opsize=0 & byte=0xff & currentCS; rm16 & reg_opcode=4 ... { target:4 = segment(currentCS,rm16); goto [target]; } +:JMP rm16 is vexMode=0 & addrsize=1 & opsize=0 & byte=0xff; rm16 & reg_opcode=4 ... { goto [rm16]; } +:JMP rm32 is vexMode=0 & addrsize=1 & opsize=1 & byte=0xff; rm32 & reg_opcode=4 ... { goto [rm32]; } +@ifdef IA64 +:JMP rm64 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0xff; rm64 & reg_opcode=4 ... { goto [rm64]; } +@endif + +:JMPF ptr1616 is $(LONGMODE_OFF) & vexMode=0 & opsize=0 & byte=0xea; ptr1616 { goto ptr1616; } +:JMPF ptr1632 is $(LONGMODE_OFF) & vexMode=0 & opsize=1 & byte=0xea; ptr1632 { goto ptr1632; } +:JMPF Mem is vexMode=0 & opsize=0 & byte=0xff; Mem & reg_opcode=5 ... { target:$(SIZE) = zext(*:2 Mem); goto [target]; } +:JMPF Mem is vexMode=0 & opsize=1 & byte=0xff; Mem & reg_opcode=5 ... { +@ifdef IA64 + target:$(SIZE) = zext(*:4 Mem); +@else + target:$(SIZE) = *:4 Mem; +@endif + goto [target]; +} +@ifdef IA64 +:JMPF Mem is vexMode=0 & opsize=2 & byte=0xff; Mem & reg_opcode=5 ... { target:$(SIZE) = *:8 Mem; goto [target]; } +@endif + +# Initially disallowed in 64bit mode, but later reintroduced +:LAHF is vexMode=0 & byte=0x9f { AH=(SF<<7)|(ZF<<6)|(AF<<4)|(PF<<2)|2|CF; } + +:LAR Reg16,rm16 is vexMode=0 & opsize=0 & byte=0xf; byte=0x2; rm16 & Reg16 ... { Reg16 = rm16 & 0xff00; ZF=1; } +:LAR Reg32,rm32 is vexMode=0 & opsize=1 & byte=0xf; byte=0x2; rm32 & Reg32 ... & check_Reg32_dest ... { Reg32 = rm32 & 0xffff00; build check_Reg32_dest; ZF=1; } +@ifdef IA64 +:LAR Reg64,rm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0x2; rm32 & Reg64 ... { Reg64 = zext( rm32 & 0xffff00 ); ZF=1; } +@endif + +:LDMXCSR m32 is vexMode=0 & byte=0xf; byte=0xae; ( mod != 0b11 & reg_opcode=2 ) ... & m32 { MXCSR = m32; } + +# 16 & 32-bit only +:LDS Reg16,Mem is $(LONGMODE_OFF) & vexMode=0 & opsize=0 & byte=0xC5; Mem & Reg16 ... { tmp:4 = *Mem; DS = tmp(2); Reg16 = tmp(0); } +:LDS Reg32,Mem is $(LONGMODE_OFF) & vexMode=0 & opsize=1 & byte=0xC5 & bit64=0; Mem & Reg32 ... & check_Reg32_dest ... { tmp:6 = *Mem; DS = tmp(4); Reg32 = tmp(0); build check_Reg32_dest; } + +:LSS Reg16,Mem is vexMode=0 & opsize=0 & byte=0x0F; byte=0xB2; Mem & Reg16 ... { tmp:4 = *Mem; SS = tmp(2); Reg16 = tmp(0); } +:LSS Reg32,Mem is vexMode=0 & opsize=1 & byte=0x0F; byte=0xB2; Mem & Reg32 ... & check_Reg32_dest ... { tmp:6 = *Mem; SS = tmp(4); Reg32 = tmp(0); build check_Reg32_dest; } +@ifdef IA64 +:LSS Reg64,Mem is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x0F; byte=0xB2; Mem & Reg64 ... { tmp:10 = *Mem; SS = tmp(8); Reg64 = tmp(0); } +@endif + +# 16 & 32-bit only +:LES Reg16,Mem is $(LONGMODE_OFF) & vexMode=0 & opsize=0 & byte=0xC4; Mem & Reg16 ... { tmp:4 = *Mem; ES = tmp(2); Reg16 = tmp(0); } +:LES Reg32,Mem is $(LONGMODE_OFF) & vexMode=0 & opsize=1 & byte=0xC4 & bit64=0; Mem & Reg32 ... & check_Reg32_dest ... { tmp:6 = *Mem; ES = tmp(4); Reg32 = tmp(0); build check_Reg32_dest; } + +:LFS Reg16,Mem is vexMode=0 & opsize=0 & byte=0x0F; byte=0xB4; Mem & Reg16 ... { tmp:4 = *Mem; FS = tmp(2); Reg16 = tmp(0); } +:LFS Reg32,Mem is vexMode=0 & opsize=1 & byte=0x0F; byte=0xB4; Mem & Reg32 ... & check_Reg32_dest ... { tmp:6 = *Mem; FS = tmp(4); Reg32 = tmp(0); build check_Reg32_dest; } +@ifdef IA64 +:LFS Reg64,Mem is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x0F; byte=0xB4; Mem & Reg64 ... { tmp:10 = *Mem; FS = tmp(8); Reg64 = tmp(0); } +@endif +:LGS Reg16,Mem is vexMode=0 & opsize=0 & byte=0x0F; byte=0xB5; Mem & Reg16 ... { tmp:4 = *Mem; GS = tmp(2); Reg16 = tmp(0); } +:LGS Reg32,Mem is vexMode=0 & opsize=1 & byte=0x0F; byte=0xB5; Mem & Reg32 ... & check_Reg32_dest ... { tmp:6 = *Mem; GS = tmp(4); Reg32 = tmp(0); build check_Reg32_dest; } +@ifdef IA64 +:LGS Reg64,Mem is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x0F; byte=0xB5; Mem & Reg64 ... { tmp:10 = *Mem; GS = tmp(8); Reg64 = tmp(0); } +@endif + +#in 64-bit mode address size of 16 is not encodable +:LEA Reg16,addr16 is $(LONGMODE_OFF) & vexMode=0 & opsize=0 & addrsize=0 & byte=0x8D; addr16 & Reg16 ... { Reg16 = addr16; } +:LEA Reg32,addr16 is $(LONGMODE_OFF) & vexMode=0 & opsize=1 & addrsize=0 & byte=0x8D; addr16 & Reg32 ... { Reg32 = zext(addr16); } + +:LEA Reg16,addr32 is vexMode=0 & opsize=0 & addrsize=1 & byte=0x8D; addr32 & Reg16 ... { Reg16 = addr32(0); } +:LEA Reg32,addr32 is vexMode=0 & opsize=1 & addrsize=1 & byte=0x8D; addr32 & Reg32 ... & check_Reg32_dest ... { + Reg32 = addr32; + build check_Reg32_dest; +} + +@ifdef IA64 +:LEA Reg16,addr64 is $(LONGMODE_ON) & vexMode=0 & opsize=0 & addrsize=2 & byte=0x8D; addr64 & Reg16 ... { Reg16 = addr64(0); } +:LEA Reg32,addr64 is $(LONGMODE_ON) & vexMode=0 & opsize=1 & addrsize=2 & byte=0x8D; addr64 & Reg32 ... & check_Reg32_dest ... { + Reg32 = addr64(0); + build check_Reg32_dest; +} +:LEA Reg64,addr32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & addrsize=1 & byte=0x8D; addr32 & Reg64 ... { Reg64 = zext(addr32); } +:LEA Reg64,addr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & addrsize=2 & byte=0x8D; addr64 & Reg64 ... { Reg64 = addr64; } +@endif + +:LEAVE is vexMode=0 & addrsize=0 & byte=0xc9 { SP = BP; tmp:$(SIZE) = segment(SS,SP); BP = *tmp; SP = SP + 2; } +:LEAVE is vexMode=0 & addrsize=1 & byte=0xc9 { ESP = EBP; EBP = *$(STACKPTR); ESP=ESP+4; } +@ifdef IA64 +:LEAVE is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0xc9 { RSP = RBP; RBP = *RSP; RSP=RSP+8; } +@endif + +define pcodeop GlobalDescriptorTableRegister; +:LGDT m16 is vexMode=0 & opsize=0 & byte=0xf; byte=0x1; ( mod != 0b11 & reg_opcode=2 ) ... & m16 +{ + GlobalDescriptorTableRegister(m16); +} + +:LGDT m32 is vexMode=0 & opsize=1 & byte=0xf; byte=0x1; ( mod != 0b11 & reg_opcode=2 ) ... & m32 +{ + GlobalDescriptorTableRegister(m32); +} + +@ifdef IA64 +:LGDT m64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0x1; ( mod != 0b11 & reg_opcode=2 ) ... & m64 +{ + GlobalDescriptorTableRegister(m64); +} +@endif + +define pcodeop InterruptDescriptorTableRegister; +:LIDT m16 is vexMode=0 & opsize=0 & byte=0xf; byte=0x1; ( mod != 0b11 & reg_opcode=3 ) ... & m16 +{ + InterruptDescriptorTableRegister(m16); +} + +:LIDT m32 is vexMode=0 & opsize=1 & byte=0xf; byte=0x1; ( mod != 0b11 & reg_opcode=3 ) ... & m32 +{ + InterruptDescriptorTableRegister(m32); +} +@ifdef IA64 +:LIDT m64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0x1; ( mod != 0b11 & reg_opcode=3 ) ... & m64 +{ + InterruptDescriptorTableRegister(m64); +} +@endif + +define pcodeop LocalDescriptorTableRegister; +:LLDT rm16 is vexMode=0 & byte=0xf; byte=0x0; rm16 & reg_opcode=2 ... +{ + LocalDescriptorTableRegister(rm16); +} + +@ifdef IA64 +:LMSW rm16 is vexMode=0 & byte=0xf; byte=0x01; rm16 & reg_opcode=6 ... +{ + CR0 = (CR0 & 0xFFFFFFFFFFFFFFF0) | zext(rm16 & 0x000F); +} +@else +:LMSW rm16 is vexMode=0 & byte=0xf; byte=0x01; rm16 & reg_opcode=6 ... +{ + CR0 = (CR0 & 0xFFFFFFF0) | zext(rm16 & 0x000F); +} +@endif + +:LODSB^rep^reptail dseSI1 is vexMode=0 & rep & reptail & byte=0xAC & dseSI1 { build rep; build dseSI1; AL=dseSI1; build reptail; } +:LODSW^rep^reptail dseSI2 is vexMode=0 & rep & reptail & opsize=0 & byte=0xAD & dseSI2 { build rep; build dseSI2; AX=dseSI2; build reptail; } +:LODSD^rep^reptail dseSI4 is vexMode=0 & rep & reptail & opsize=1 & byte=0xAD & dseSI4 { build rep; build dseSI4; EAX=dseSI4; build reptail; } +@ifdef IA64 +:LODSQ^rep^reptail dseSI8 is $(LONGMODE_ON) & vexMode=0 & rep & reptail & opsize=2 & byte=0xAD & dseSI8 { build rep; build dseSI8; RAX=dseSI8; build reptail; } +@endif + +:LOOP rel8 is vexMode=0 & addrsize=0 & byte=0xE2; rel8 { CX = CX -1; if (CX!=0) goto rel8; } +:LOOP rel8 is vexMode=0 & addrsize=1 & byte=0xE2; rel8 { ECX = ECX -1; if (ECX!=0) goto rel8; } +@ifdef IA64 +:LOOP rel8 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0xE2; rel8 { RCX = RCX -1; if (RCX!=0) goto rel8; } +@endif + +:LOOPZ rel8 is vexMode=0 & addrsize=0 & byte=0xE1; rel8 { CX = CX -1; if (CX!=0 && ZF!=0) goto rel8; } +:LOOPZ rel8 is vexMode=0 & addrsize=1 & byte=0xE1; rel8 { ECX = ECX -1; if (ECX!=0 && ZF!=0) goto rel8; } +@ifdef IA64 +:LOOPZ rel8 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0xE1; rel8 { RCX = RCX -1; if (RCX!=0 && ZF!=0) goto rel8; } +@endif + +:LOOPNZ rel8 is vexMode=0 & addrsize=0 & byte=0xE0; rel8 { CX = CX -1; if (CX!=0 && ZF==0) goto rel8; } +:LOOPNZ rel8 is vexMode=0 & addrsize=1 & byte=0xE0; rel8 { ECX = ECX -1; if (ECX!=0 && ZF==0) goto rel8; } +@ifdef IA64 +:LOOPNZ rel8 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0xE0; rel8 { RCX = RCX -1; if (RCX!=0 && ZF==0) goto rel8; } +@endif + +define pcodeop SegmentLimit; +:LSL Reg16,rm16 is vexMode=0 & opsize=0 & byte=0xf; byte=0x3; rm16 & Reg16 ... +{ + tmp:3 = SegmentLimit(rm16); + Reg16 = tmp:2; + ZF = tmp[16,1]; +} + +:LSL Reg32,rm32 is vexMode=0 & opsize=1 & byte=0xf; byte=0x3; rm32 & Reg32 ... +{ + tmp:3 = SegmentLimit(rm32); + Reg32 = zext(tmp:2); + ZF = tmp[16,1]; +} + +@ifdef IA64 +:LSL Reg64,rm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0x3; rm32 & Reg64 ... +{ + tmp:3 = SegmentLimit(rm32); + Reg64 = zext(tmp:2); + ZF = tmp[16,1]; +} +@endif + +define pcodeop TaskRegister; +:LTR rm16 is vexMode=0 & byte=0xf; byte=0x0; rm16 & reg_opcode=3 ... { TaskRegister(rm16); } + +:MOV Rmr8,Reg8 is vexMode=0 & byte=0x88; mod=3 & Rmr8 & Reg8 { Rmr8=Reg8; } + +:MOV^xrelease m8,Reg8 is vexMode=0 & xrelease & byte=0x88; m8 & Reg8 ... +{ + build xrelease; + build m8; + m8=Reg8; + } + +:MOV Rmr16,Reg16 is vexMode=0 & opsize=0 & byte=0x89; mod=3 & Rmr16 & Reg16 { Rmr16=Reg16; } + +:MOV^xrelease m16,Reg16 is vexMode=0 & xrelease & opsize=0 & byte=0x89; m16 & Reg16 ... +{ + build xrelease; + build m16; + m16=Reg16; + } + +:MOV Rmr32,Reg32 is vexMode=0 & opsize=1 & byte=0x89; mod=3 & Rmr32 & check_Rmr32_dest & Reg32 { Rmr32=Reg32; build check_Rmr32_dest; } + +:MOV^xrelease m32,Reg32 is vexMode=0 & xrelease & opsize=1 & byte=0x89; m32 & Reg32 ... +{ + build xrelease; + build m32; + m32=Reg32; +} + +@ifdef IA64 +:MOV Rmr64,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x89; mod=3 & Rmr64 & Reg64 { Rmr64=Reg64; } + +:MOV^xrelease m64,Reg64 is $(LONGMODE_ON) & vexMode=0 & xrelease & opsize=2 & byte=0x89; m64 & Reg64 ... +{ + build xrelease; + build m64; + m64=Reg64; + } + +@endif +:MOV Reg8,rm8 is vexMode=0 & byte=0x8a; rm8 & Reg8 ... { Reg8 = rm8; } +:MOV Reg16,rm16 is vexMode=0 & opsize=0 & byte=0x8b; rm16 & Reg16 ... { Reg16 = rm16; } +:MOV Reg32,rm32 is vexMode=0 & opsize=1 & byte=0x8b; rm32 & Reg32 ... & check_Reg32_dest ... { Reg32 = rm32; build check_Reg32_dest; } +@ifdef IA64 +:MOV Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x8b; rm64 & Reg64 ... { Reg64 = rm64; } +@endif +:MOV rm16,Sreg is vexMode=0 & byte=0x8c; rm16 & check_rm16_dest ... & Sreg ... { rm16 = Sreg; build check_rm16_dest; } +:MOV Sreg,rm16 is vexMode=0 & byte=0x8e; rm16 & Sreg ... { Sreg=rm16; } +:MOV AL,moffs8 is vexMode=0 & byte=0xa0; AL & moffs8 { AL=moffs8; } +:MOV AX,moffs16 is vexMode=0 & opsize=0 & byte=0xa1; AX & moffs16 { AX=moffs16; } +:MOV EAX,moffs32 is vexMode=0 & opsize=1 & byte=0xa1; EAX & check_EAX_dest & moffs32 { EAX=moffs32; build check_EAX_dest; } +@ifdef IA64 +:MOV RAX,moffs64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xa1; RAX & moffs64 { RAX=moffs64; } +@endif +:MOV moffs8,AL is vexMode=0 & byte=0xa2; AL & moffs8 { moffs8=AL; } +:MOV moffs16,AX is vexMode=0 & opsize=0 & byte=0xa3; AX & moffs16 { moffs16=AX; } +:MOV moffs32,EAX is vexMode=0 & opsize=1 & byte=0xa3; EAX & moffs32 { moffs32=EAX; } +@ifdef IA64 +:MOV moffs64,RAX is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xa3; RAX & moffs64 { moffs64=RAX; } +@endif +:MOV CRmr8,imm8 is vexMode=0 & row=11 & page=0 & CRmr8; imm8 { CRmr8 = imm8; } +:MOV CRmr16,imm16 is vexMode=0 & opsize=0 & row=11 & page=1 & CRmr16; imm16 { CRmr16 = imm16; } +:MOV CRmr32,imm32 is vexMode=0 & opsize=1 & row=11 & page=1 & CRmr32; imm32 { CRmr32 = imm32; } +@ifdef IA64 +:MOV Rmr64,imm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & row=11 & page=1 & Rmr64; imm64 { Rmr64 = imm64; } +@endif +:MOV Rmr8,imm8 is vexMode=0 & byte=0xc6; (mod=3 & Rmr8 & reg_opcode=0); imm8 { Rmr8 = imm8; } + +:MOV^xrelease spec_m8,imm8 is vexMode=0 & xrelease & byte=0xc6; spec_m8 & reg_opcode=0 ...; imm8 +{ + build xrelease; + build spec_m8; + spec_m8 = imm8; +} +:MOV Rmr16,imm16 is vexMode=0 & opsize=0 & byte=0xc7; (mod=3 & Rmr16 & reg_opcode=0); imm16 { Rmr16 = imm16; } + +:MOV^xrelease spec_m16,imm16 is vexMode=0 & xrelease & opsize=0 & byte=0xc7; spec_m16 & reg_opcode=0 ...; imm16 +{ + build xrelease; + build spec_m16; + spec_m16 = imm16; +} + +:MOV Rmr32,imm32 is vexMode=0 & opsize=1 & byte=0xc7; (mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=0); imm32 { Rmr32 = imm32; build check_Rmr32_dest; } + +:MOV^xrelease spec_m32,imm32 is vexMode=0 & xrelease & opsize=1 & byte=0xc7; (spec_m32 & reg_opcode=0 ...); imm32 +{ + build xrelease; + build spec_m32; + spec_m32 = imm32; +} +@ifdef IA64 +:MOV Rmr64,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xc7; (mod=3 & Rmr64 & reg_opcode=0); simm32 { Rmr64 = simm32; } + +:MOV^xrelease spec_m64,simm32 is $(LONGMODE_ON) & vexMode=0 & xrelease & opsize=2 & byte=0xc7; (spec_m64 & reg_opcode=0 ...); simm32 +{ + build xrelease; + build spec_m64; + spec_m64 = simm32; +} +@endif + +:MOV creg, Rmr32 is vexMode=0 & byte=0xf; byte=0x22; Rmr32 & creg { +@ifdef IA64 + creg=zext(Rmr32); +@else + creg=Rmr32; +@endif +} +@ifdef IA64 +:MOV creg_x, Rmr32 is vexMode=0 & rexRprefix=1 & byte=0xf; byte=0x22; Rmr32 & creg_x { creg_x=zext(Rmr32); } +:MOV creg, Rmr64 is $(LONGMODE_ON) & vexMode=0 & bit64=1 & byte=0xf; byte=0x22; Rmr64 & creg { creg=Rmr64; } +:MOV creg_x, Rmr64 is $(LONGMODE_ON) & vexMode=0 & bit64=1 & rexRprefix=1 & byte=0xf; byte=0x22; Rmr64 & creg_x { creg_x=Rmr64; } +@endif +:MOV Rmr32, creg is vexMode=0 & byte=0xf; byte=0x20; Rmr32 & creg { +@ifdef IA64 + Rmr32 = creg:4; +@else + Rmr32 = creg; +@endif +} +:MOV Rmr32, creg_x is vexMode=0 & rexRprefix=1 & byte=0xf; byte=0x20; Rmr32 & creg_x { Rmr32 = creg_x:4; } +@ifdef IA64 +:MOV Rmr64, creg is $(LONGMODE_ON) & vexMode=0 & bit64=1 & byte=0xf; byte=0x20; Rmr64 & creg { Rmr64 = creg; } +:MOV Rmr64, creg_x is $(LONGMODE_ON) & vexMode=0 & bit64=1 & rexRprefix=1 & byte=0xf; byte=0x20; Rmr64 & creg_x { Rmr64 = creg_x; } +@endif +:MOV Rmr32, debugreg is vexMode=0 & byte=0xf; byte=0x21; Rmr32 & debugreg { +@ifdef IA64 + Rmr32 = debugreg:4; +@else + Rmr32 = debugreg; +@endif +} +:MOV Rmr32, debugreg_x is vexMode=0 & rexRprefix=1 & byte=0xf; byte=0x21; Rmr32 & debugreg_x { Rmr32 = debugreg_x:4; } +@ifdef IA64 +:MOV Rmr64, debugreg is $(LONGMODE_ON) & vexMode=0 & bit64=1 & byte=0xf; byte=0x21; Rmr64 & debugreg { Rmr64 = debugreg; } +:MOV Rmr64, debugreg_x is $(LONGMODE_ON) & vexMode=0 & bit64=1 & rexRprefix=1 & byte=0xf; byte=0x21; Rmr64 & debugreg_x { Rmr64 = debugreg_x; } +@endif +:MOV debugreg, Rmr32 is vexMode=0 & byte=0xf; byte=0x23; Rmr32 & debugreg { +@ifdef IA64 + debugreg = zext(Rmr32); +@else + debugreg = Rmr32; +@endif +} +@ifdef IA64 +:MOV debugreg_x, Rmr32 is vexMode=0 & rexRprefix=1 & byte=0xf; byte=0x23; Rmr32 & debugreg_x & mod=3 { debugreg_x = zext(Rmr32); } +:MOV debugreg, Rmr64 is $(LONGMODE_ON) & vexMode=0 & bit64=1 & byte=0xf; byte=0x23; Rmr64 & debugreg & mod=3 { debugreg = Rmr64; } +:MOV debugreg_x, Rmr64 is $(LONGMODE_ON) & vexMode=0 & bit64=1 & rexRprefix=1 & byte=0xf; byte=0x23; Rmr64 & debugreg_x & mod=3 { debugreg_x = Rmr64; } +@endif + +@ifndef IA64 +# These are obsolete instructions after the 486 generation. +# They were erroneously placed in the IA64 build. +# They were removed to facilitate instruction patching to generate "MOV EAX, 0x2" correctly. +#:MOV r32, testreg is vexMode=0 & byte=0xf; byte=0x24; r32 & testreg & mod=3 { r32 = testreg; } +#:MOV testreg, r32 is vexMode=0 & byte=0xf; byte=0x26; r32 & testreg & mod=3 { testreg = r32; } +@endif + +define pcodeop swap_bytes; +:MOVBE Reg16, m16 is vexMode=0 & opsize=0 & byte=0xf; byte=0x38; byte=0xf0; Reg16 ... & m16 { Reg16 = swap_bytes( m16 ); } +:MOVBE Reg32, m32 is vexMode=0 & opsize=1 & mandover=0 & byte=0xf; byte=0x38; byte=0xf0; Reg32 ... & m32 { Reg32 = swap_bytes( m32 ); } +:MOVBE m16, Reg16 is vexMode=0 & opsize=0 & byte=0xf; byte=0x38; byte=0xf1; Reg16 ... & m16 { m16 = swap_bytes( Reg16 ); } +:MOVBE m32, Reg32 is vexMode=0 & opsize=1 & mandover=0 & byte=0xf; byte=0x38; byte=0xf1; Reg32 ... & m32 { m32 = swap_bytes( Reg32 ); } +@ifdef IA64 +:MOVBE Reg64, m64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & mandover=0 & byte=0xf; byte=0x38; byte=0xf0; Reg64 ... & m64 { Reg64 = swap_bytes( m64 ); } +:MOVBE m64, Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & mandover=0 & byte=0xf; byte=0x38; byte=0xf1; Reg64 ... & m64 { m64 = swap_bytes( Reg64 ); } +@endif + + +:MOVNTI Mem,Reg32 is vexMode=0 & opsize = 1; byte=0xf; byte=0xc3; Mem & Reg32 ... { *Mem = Reg32; } +@ifdef IA64 +:MOVNTI Mem,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize = 2; byte=0xf; byte=0xc3; Mem & Reg64 ... { *Mem = Reg64; } +@endif + +:MOVSB^rep^reptail eseDI1,dseSI1 is vexMode=0 & rep & reptail & byte=0xa4 & eseDI1 & dseSI1 { build rep; build eseDI1; build dseSI1; eseDI1 = dseSI1; build reptail; } +:MOVSW^rep^reptail eseDI2,dseSI2 is vexMode=0 & rep & reptail & opsize=0 & byte=0xa5 & eseDI2 & dseSI2 { build rep; build eseDI2; build dseSI2; eseDI2 = dseSI2; build reptail; } +:MOVSD^rep^reptail eseDI4,dseSI4 is vexMode=0 & rep & reptail & opsize=1 & byte=0xa5 & eseDI4 & dseSI4 { build rep; build eseDI4; build dseSI4; eseDI4 = dseSI4; build reptail; } +@ifdef IA64 +:MOVSQ^rep^reptail eseDI8,dseSI8 is $(LONGMODE_ON) & vexMode=0 & rep & reptail & opsize=2 & byte=0xa5 & eseDI8 & dseSI8 { build rep; build eseDI8; build dseSI8; eseDI8 = dseSI8; build reptail; } +@endif + +:MOVSX Reg16,spec_rm8 is vexMode=0 & opsize=0 & byte=0xf; byte=0xbe; spec_rm8 & Reg16 ... { Reg16 = sext(spec_rm8); } +:MOVSX Reg32,spec_rm8 is vexMode=0 & opsize=1 & byte=0xf; byte=0xbe; spec_rm8 & Reg32 ... & check_Reg32_dest ... { Reg32 = sext(spec_rm8); build check_Reg32_dest; } +@ifdef IA64 +:MOVSX Reg64,spec_rm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0xbe; spec_rm8 & Reg64 ... { Reg64 = sext(spec_rm8); } +@endif +:MOVSX Reg32,spec_rm16 is vexMode=0 & byte=0xf; byte=0xbf; spec_rm16 & Reg32 ... & check_Reg32_dest ... { Reg32 = sext(spec_rm16); build check_Reg32_dest; } +@ifdef IA64 +:MOVSX Reg64,spec_rm16 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0xbf; spec_rm16 & Reg64 ... { Reg64 = sext(spec_rm16); } +@endif + +# Overlaps with ARPL in non-64bit modes +@ifdef IA64 +:MOVSXD Reg32,rm32 is $(LONGMODE_ON) & vexMode=0 & opsize=1 & byte=0x63; rm32 & Reg32 ... & check_Reg32_dest ... { Reg32 = rm32; build check_Reg32_dest; } +:MOVSXD Reg64,rm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x63; rm32 & Reg64 ... { Reg64 = sext(rm32); } +@endif + +:MOVZX Reg16,spec_rm8 is vexMode=0 & opsize=0 & byte=0xf; byte=0xb6; spec_rm8 & Reg16 ... { Reg16 = zext(spec_rm8); } +:MOVZX Reg32,spec_rm8 is vexMode=0 & opsize=1 & byte=0xf; byte=0xb6; spec_rm8 & Reg32 ... & check_Reg32_dest ... { Reg32 = zext(spec_rm8); build check_Reg32_dest; } +@ifdef IA64 +:MOVZX Reg64,spec_rm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0xb6; spec_rm8 & Reg64 ... { Reg64 = zext(spec_rm8); } +@endif + +:MOVZX Reg32,spec_rm16 is vexMode=0 & byte=0xf; byte=0xb7; spec_rm16 & Reg32 ... & check_Reg32_dest ... { Reg32 = zext(spec_rm16); build check_Reg32_dest; } +@ifdef IA64 +:MOVZX Reg64,spec_rm16 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0xb7; spec_rm16 & Reg64 ... { Reg64 = zext(spec_rm16); } +@endif + +:MUL rm8 is vexMode=0 & byte=0xf6; rm8 & reg_opcode=4 ... { AX=zext(AL)*zext(rm8); multflags(AH); } +:MUL rm16 is vexMode=0 & opsize=0 & byte=0xf7; rm16 & reg_opcode=4 ... { tmp:4=zext(AX)*zext(rm16); DX=tmp(2); AX=tmp(0); multflags(DX); } +:MUL rm32 is vexMode=0 & opsize=1 & byte=0xf7; rm32 & check_EAX_dest ... & check_EDX_dest ... & reg_opcode=4 ... { tmp:8=zext(EAX)*zext(rm32); EDX=tmp(4); build check_EDX_dest; multflags(EDX); EAX=tmp(0); build check_EAX_dest; } +@ifdef IA64 +:MUL rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf7; rm64 & reg_opcode=4 ... { tmp:16=zext(RAX)*zext(rm64); RDX=tmp(8); RAX=tmp(0); multflags(RDX); } +@endif + +:MWAIT is vexMode=0 & byte=0x0f; byte=0x01; byte=0xC9 { mwait(); } +:MWAITX is vexMode=0 & byte=0x0f; byte=0x01; byte=0xFB { mwaitx(); } +:MONITOR is vexMode=0 & byte=0x0f; byte=0x01; byte=0xC8 { monitor(); } +:MONITORX is vexMode=0 & byte=0x0f; byte=0x01; byte=0xFA { monitorx(); } + +# See 'lockable.sinc' for memory destination, lockable variants +:NEG Rmr8 is vexMode=0 & byte=0xf6; mod=3 & Rmr8 & reg_opcode=3 { negflags(Rmr8); Rmr8 = -Rmr8; resultflags(Rmr8 ); } +:NEG Rmr16 is vexMode=0 & opsize=0 & byte=0xf7; mod=3 & Rmr16 & reg_opcode=3 { negflags(Rmr16); Rmr16 = -Rmr16; resultflags(Rmr16); } +:NEG Rmr32 is vexMode=0 & opsize=1 & byte=0xf7; mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=3 { negflags(Rmr32); Rmr32 = -Rmr32; resultflags(Rmr32); build check_Rmr32_dest;} +@ifdef IA64 +:NEG Rmr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf7; mod=3 & Rmr64 & reg_opcode=3 { negflags(Rmr64); Rmr64 = -Rmr64; resultflags(Rmr64); } +@endif + +:NOP is vexMode=0 & byte=0x90 & (mandover=0 | mandover=4) & (rexprefix=0 | rexWRXBprefix=8) { } +:NOP rm16 is vexMode=0 & mandover & opsize=0 & byte=0x0f; high5=3; rm16 ... { } +:NOP rm32 is vexMode=0 & mandover & opsize=1 & byte=0x0f; high5=3; rm32 ... { } +:NOP^"/reserved" rm16 is vexMode=0 & mandover & opsize=0 & byte=0x0f; byte=0x18; rm16 & reg_opcode_hb=1 ... { } +:NOP^"/reserved" rm32 is vexMode=0 & mandover & opsize=1 & byte=0x0f; byte=0x18; rm32 & reg_opcode_hb=1 ... { } +:NOP rm16 is vexMode=0 & mandover & opsize=0 & byte=0x0f; byte=0x1f; rm16 & reg_opcode=0 ... { } +:NOP rm32 is vexMode=0 & mandover & opsize=1 & byte=0x0f; byte=0x1f; rm32 & reg_opcode=0 ... { } + +# See 'lockable.sinc' for memory destination, lockable variants +:NOT Rmr8 is vexMode=0 & byte=0xf6; mod=3 & Rmr8 & reg_opcode=2 { Rmr8 = ~Rmr8; } +:NOT Rmr16 is vexMode=0 & opsize=0 & byte=0xf7; mod=3 & Rmr16 & reg_opcode=2 { Rmr16 = ~Rmr16; } +:NOT Rmr32 is vexMode=0 & opsize=1 & byte=0xf7; mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=2 { Rmr32 = ~Rmr32; build check_Rmr32_dest;} +@ifdef IA64 +:NOT Rmr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf7; mod=3 & Rmr64 & reg_opcode=2 { Rmr64 = ~Rmr64; } +@endif + +# See 'lockable.sinc' for memory destination, lockable variants +:OR AL,imm8 is vexMode=0 & byte=0x0c; AL & imm8 { logicalflags(); AL = AL | imm8; resultflags( AL); } +:OR AX,imm16 is vexMode=0 & opsize=0 & byte=0xd; AX & imm16 { logicalflags(); AX = AX | imm16; resultflags( AX); } +:OR EAX,imm32 is vexMode=0 & opsize=1 & byte=0xd; EAX & check_EAX_dest & imm32 { logicalflags(); EAX = EAX | imm32; build check_EAX_dest; resultflags( EAX); } +@ifdef IA64 +:OR RAX,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xd; RAX & simm32 { logicalflags(); RAX = RAX | simm32; resultflags( RAX); } +@endif +:OR Rmr8,imm8 is vexMode=0 & $(BYTE_80_82); mod=3 & Rmr8 & reg_opcode=1; imm8 { logicalflags(); Rmr8 = Rmr8 | imm8; resultflags( Rmr8); } +:OR Rmr16,imm16 is vexMode=0 & opsize=0 & byte=0x81; mod=3 & Rmr16 & reg_opcode=1; imm16 { logicalflags(); Rmr16 = Rmr16 | imm16; resultflags( Rmr16); } +:OR Rmr32,imm32 is vexMode=0 & opsize=1 & byte=0x81; mod=3 & Rmr32 & check_rm32_dest & reg_opcode=1; imm32 { logicalflags(); Rmr32 = Rmr32 | imm32; build check_rm32_dest; resultflags( Rmr32); } +@ifdef IA64 +:OR Rmr64,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x81; mod=3 & Rmr64 & reg_opcode=1; simm32 { logicalflags(); tmp:8 = Rmr64; Rmr64 = tmp | simm32; resultflags( Rmr64); } +@endif +:OR Rmr16,usimm8_16 is vexMode=0 & opsize=0 & byte=0x83; mod=3 & Rmr16 & reg_opcode=1; usimm8_16 { logicalflags(); Rmr16 = Rmr16 | usimm8_16; resultflags( Rmr16); } +:OR Rmr32,usimm8_32 is vexMode=0 & opsize=1 & byte=0x83; mod=3 & Rmr32 & check_rm32_dest & reg_opcode=1; usimm8_32 { logicalflags(); Rmr32 = Rmr32 | usimm8_32; build check_rm32_dest; resultflags( Rmr32); } +@ifdef IA64 +:OR Rmr64,usimm8_64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x83; mod=3 & Rmr64 & reg_opcode=1; usimm8_64 { logicalflags(); Rmr64 = Rmr64 | usimm8_64; resultflags( Rmr64); } +@endif +:OR Rmr8,Reg8 is vexMode=0 & byte=0x8; mod=3 & Rmr8 & Reg8 { logicalflags(); Rmr8 = Rmr8 | Reg8; resultflags( Rmr8); } +:OR Rmr16,Reg16 is vexMode=0 & opsize=0 & byte=0x9; mod=3 & Rmr16 & Reg16 { logicalflags(); Rmr16 = Rmr16 | Reg16; resultflags( Rmr16); } +:OR Rmr32,Reg32 is vexMode=0 & opsize=1 & byte=0x9; mod=3 & Rmr32 & check_Rmr32_dest & Reg32 { logicalflags(); Rmr32 = Rmr32 | Reg32; build check_Rmr32_dest; resultflags( Rmr32); } +@ifdef IA64 +:OR Rmr64,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x9; mod=3 & Rmr64 & Reg64 { logicalflags(); Rmr64 = Rmr64 | Reg64; resultflags( Rmr64); } +@endif +:OR Reg8,rm8 is vexMode=0 & byte=0xa; rm8 & Reg8 ... { logicalflags(); Reg8 = Reg8 | rm8; resultflags( Reg8); } +:OR Reg16,rm16 is vexMode=0 & opsize=0 & byte=0xb; rm16 & Reg16 ... { logicalflags(); Reg16 = Reg16 | rm16; resultflags(Reg16); } +:OR Reg32,rm32 is vexMode=0 & opsize=1 & byte=0xb; rm32 & Reg32 ... & check_Reg32_dest ... { logicalflags(); Reg32 = Reg32 | rm32; build check_Reg32_dest; resultflags(Reg32); } +@ifdef IA64 +:OR Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xb; rm64 & Reg64 ... { logicalflags(); Reg64 = Reg64 | rm64; resultflags(Reg64); } +@endif + +:OUT imm8,AL is vexMode=0 & byte=0xe6; imm8 & AL { tmp:1 = imm8; out(tmp,AL); } +:OUT imm8,AX is vexMode=0 & opsize=0 & byte=0xe7; imm8 & AX { tmp:1 = imm8; out(tmp,AX); } +:OUT imm8,EAX is vexMode=0 & byte=0xe7; imm8 & EAX { tmp:1 = imm8; out(tmp,EAX); } +:OUT DX,AL is vexMode=0 & byte=0xee & DX & AL { out(DX,AL); } +:OUT DX,AX is vexMode=0 & opsize=0 & byte=0xef & DX & AX { out(DX,AX); } +:OUT DX,EAX is vexMode=0 & byte=0xef & DX & EAX { out(DX,EAX); } + +:OUTSB^rep^reptail DX,dseSI1 is vexMode=0 & rep & reptail & byte=0x6e & DX & dseSI1 { build rep; build dseSI1; out(dseSI1,DX); build reptail;} +:OUTSW^rep^reptail DX,dseSI2 is vexMode=0 & rep & reptail & opsize=0 & byte=0x6f & DX & dseSI2 { build rep; build dseSI2; out(dseSI2,DX); build reptail;} +:OUTSD^rep^reptail DX,dseSI4 is vexMode=0 & rep & reptail & byte=0x6f & DX & dseSI4 { build rep; build dseSI4; out(dseSI4,DX); build reptail;} + +:PAUSE is vexMode=0 & opsize=0 & $(PRE_F3) & byte=0x90 { } +:PAUSE is vexMode=0 & opsize=1 & $(PRE_F3) & byte=0x90 { } + +:POP rm16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & byte=0x8f; rm16 & reg_opcode=0 ... { pop22(rm16); } +:POP rm16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0x8f; rm16 & reg_opcode=0 ... { pop42(rm16); } +:POP rm32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & byte=0x8f; rm32 & reg_opcode=0 ... { pop24(rm32); } +:POP rm32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0x8f; rm32 & reg_opcode=0 ... { pop44(rm32); } +@ifdef IA64 +:POP rm16 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=0 & byte=0x8f; rm16 & reg_opcode=0 ... { pop82(rm16); } +:POP rm64 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0x8f; rm64 & reg_opcode=0 ... { pop88(rm64); } +@endif + +:POP Rmr16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & row=5 & page=1 & Rmr16 { pop22(Rmr16); } +:POP Rmr16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & row=5 & page=1 & Rmr16 { pop42(Rmr16); } +:POP Rmr32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & row=5 & page=1 & Rmr32 { pop24(Rmr32); } +:POP Rmr32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & row=5 & page=1 & Rmr32 { pop44(Rmr32); } +@ifdef IA64 +:POP Rmr16 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=0 & row=5 & page=1 & Rmr16 { pop82(Rmr16); } +:POP Rmr64 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & row=5 & page=1 & Rmr64 { pop88(Rmr64); } +@endif + +:POP DS is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & byte=0x1f & DS { pop22(DS); } +:POP DS is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & byte=0x1f & DS { popseg44(DS); } +:POP ES is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & byte=0x7 & ES { pop22(ES); } +:POP ES is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & byte=0x7 & ES { popseg44(ES); } +:POP SS is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & byte=0x17 & SS { pop22(SS); } +:POP SS is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & byte=0x17 & SS { popseg44(SS); } +:POP FS is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & byte=0xf; byte=0xa1 & FS { pop22(FS); } +:POP FS is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & byte=0xf; byte=0xa1 & FS { popseg44(FS); } +@ifdef IA64 +:POP FS is $(LONGMODE_ON) & vexMode=0 & opsize=0 & byte=0xf; byte=0xa1 & FS { popseg82(FS); } +:POP FS is $(LONGMODE_ON) & vexMode=0 & byte=0xf; byte=0xa1 & FS { popseg88(FS); } +@endif +:POP GS is $(LONGMODE_OFF) & vexMode=0 & opsize=0 & byte=0xf; byte=0xa9 & GS { pop22(GS); } +:POP GS is $(LONGMODE_OFF) & vexMode=0 & opsize=1 & byte=0xf; byte=0xa9 & GS { popseg44(GS); } +@ifdef IA64 +:POP GS is $(LONGMODE_ON) & vexMode=0 & opsize=0 & byte=0xf; byte=0xa9 & GS { popseg82(GS); } +:POP GS is $(LONGMODE_ON) & vexMode=0 & byte=0xf; byte=0xa9 & GS { popseg88(GS); } +@endif + +:POPA is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & byte=0x61 { pop22(DI); pop22(SI); pop22(BP); tmp:2=0; pop22(tmp); pop22(BX); pop22(DX); pop22(CX); pop22(AX); } +:POPA is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0x61 { pop42(DI); pop42(SI); pop42(BP); tmp:2=0; pop42(tmp); pop42(BX); pop42(DX); pop42(CX); pop42(AX); } +:POPAD is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & byte=0x61 { pop24(EDI); pop24(ESI); pop24(EBP); tmp:4=0; pop24(tmp); pop24(EBX); pop24(EDX); pop24(ECX); pop24(EAX); } +:POPAD is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0x61 { pop44(EDI); pop44(ESI); pop44(EBP); tmp:4=0; pop44(tmp); pop44(EBX); pop44(EDX); pop44(ECX); pop44(EAX); } +:POPF is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & byte=0x9d { pop22(flags); unpackflags(flags); } +:POPF is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0x9d { pop42(flags); unpackflags(flags); } +:POPFD is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & byte=0x9d { pop24(eflags); unpackflags(eflags); unpackeflags(eflags); } +:POPFD is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0x9d { pop44(eflags); unpackflags(eflags); unpackeflags(eflags); } +@ifdef IA64 +:POPF is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=0 & byte=0x9d { pop82(flags); unpackflags(flags); } +:POPFQ is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0x9d { pop88(rflags); unpackflags(rflags); unpackeflags(rflags); } +@endif + +:PREFETCH m8 is vexMode=0 & byte=0x0f; byte=0x0d; m8 & reg_opcode=0 ... { } +:PREFETCH m8 is vexMode=0 & byte=0x0f; byte=0x0d; m8 & reg_opcode ... { } # rest aliased to /0 +:PREFETCHW m8 is vexMode=0 & byte=0x0f; byte=0x0d; m8 & reg_opcode=1 ... { } +:PREFETCHWT1 m8 is vexMode=0 & byte=0x0f; byte=0x0d; m8 & reg_opcode=2 ... { } + +:PREFETCHT0 m8 is vexMode=0 & byte=0x0f; byte=0x18; ( mod != 0b11 & reg_opcode=1 ) ... & m8 { } +:PREFETCHT1 m8 is vexMode=0 & byte=0x0f; byte=0x18; ( mod != 0b11 & reg_opcode=2 ) ... & m8 { } +:PREFETCHT2 m8 is vexMode=0 & byte=0x0f; byte=0x18; ( mod != 0b11 & reg_opcode=3 ) ... & m8 { } +:PREFETCHNTA m8 is vexMode=0 & byte=0x0f; byte=0x18; ( mod != 0b11 & reg_opcode=0 ) ... & m8 { } + +define pcodeop ptwrite; + +:PTWRITE rm32 is vexMode=0 & $(PRE_F3) & byte=0x0f; byte=0xae; rm32 & reg_opcode=4 ... { ptwrite(rm32); } + +:PUSH rm16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & byte=0xff; rm16 & reg_opcode=6 ... { push22(rm16); } +:PUSH rm16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0xff; rm16 & reg_opcode=6 ... { push42(rm16); } +:PUSH rm32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & byte=0xff; rm32 & reg_opcode=6 ... { push24(rm32); } +:PUSH rm32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0xff; rm32 & reg_opcode=6 ... { push44(rm32); } +@ifdef IA64 +:PUSH rm16 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=0 & byte=0xff; rm16 & reg_opcode=6 ... { push82(rm16); } +:PUSH rm64 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0xff; rm64 & reg_opcode=6 ... { push88(rm64); } +@endif +:PUSH Rmr16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & row=5 & page=0 & Rmr16 { push22(Rmr16); } +:PUSH Rmr16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & row=5 & page=0 & Rmr16 { push42(Rmr16); } +:PUSH Rmr32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & row=5 & page=0 & Rmr32 { push24(Rmr32); } +:PUSH Rmr32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & row=5 & page=0 & Rmr32 { push44(Rmr32); } +@ifdef IA64 +:PUSH Rmr16 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=0 & row=5 & page=0 & Rmr16 { push82(Rmr16); } +:PUSH Rmr64 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & row=5 & page=0 & Rmr64 { push88(Rmr64); } +@endif +:PUSH simm8_16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & byte=0x6a; simm8_16 { tmp:2=simm8_16; push22(tmp); } +:PUSH simm8_16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0x6a; simm8_16 { tmp:2=simm8_16; push42(tmp); } +@ifdef IA64 +:PUSH simm8_16 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=0 & byte=0x6a; simm8_16 { tmp:2=simm8_16; push82(tmp); } +@endif +:PUSH simm8_32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & byte=0x6a; simm8_32 { tmp:4=simm8_32; push24(tmp); } +:PUSH simm8_32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0x6a; simm8_32 { tmp:4=simm8_32; push44(tmp); } +@ifdef IA64 +:PUSH simm8_64 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=1 & byte=0x6a; simm8_64 { tmp:8=simm8_64; push88(tmp); } +:PUSH simm8_64 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=2 & byte=0x6a; simm8_64 { tmp:8=simm8_64; push88(tmp); } +@endif +:PUSH simm16_16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & byte=0x68; simm16_16 { tmp:2=simm16_16; push22(tmp); } +:PUSH simm16_16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0x68; simm16_16 { tmp:2=simm16_16; push42(tmp); } +@ifdef IA64 +:PUSH simm16_16 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=0 & byte=0x68; simm16_16 { tmp:2=simm16_16; push82(tmp); } +@endif +:PUSH imm32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & byte=0x68; imm32 { tmp:4=imm32; push24(tmp); } +:PUSH imm32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0x68; imm32 { tmp:4=imm32; push44(tmp); } +@ifdef IA64 +:PUSH simm32 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=1 & byte=0x68; simm32 { tmp:8=simm32; push88(tmp); } +:PUSH simm32 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=2 & byte=0x68; simm32 { tmp:8=simm32; push88(tmp); } +@endif + +:PUSH CS is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & byte=0xe & CS { push22(CS); } +:PUSH CS is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & byte=0xe & CS { pushseg44(CS); } +:PUSH SS is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & byte=0x16 & SS { push22(SS); } +:PUSH SS is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & byte=0x16 & SS { pushseg44(SS); } +:PUSH DS is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & byte=0x1e & DS { push22(DS); } +:PUSH DS is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & byte=0x1e & DS { pushseg44(DS); } +:PUSH ES is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & byte=0x6 & ES { push22(ES); } +:PUSH ES is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & byte=0x6 & ES { pushseg44(ES); } +:PUSH FS is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & byte=0xf; byte=0xa0 & FS { push22(FS); } +:PUSH FS is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & byte=0xf; byte=0xa0 & FS { pushseg44(FS); } +@ifdef IA64 +:PUSH FS is $(LONGMODE_ON) & vexMode=0 & opsize=0 & byte=0xf; byte=0xa0 & FS { pushseg82(FS); } +:PUSH FS is $(LONGMODE_ON) & vexMode=0 & byte=0xf; byte=0xa0 & FS { pushseg88(FS); } +@endif +:PUSH GS is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & byte=0xf; byte=0xa8 & GS { push22(GS); } +:PUSH GS is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & byte=0xf; byte=0xa8 & GS { pushseg44(GS); } +@ifdef IA64 +:PUSH GS is $(LONGMODE_ON) & vexMode=0 & opsize=0 & byte=0xf; byte=0xa8 & GS { pushseg82(GS); } +:PUSH GS is $(LONGMODE_ON) & vexMode=0 & byte=0xf; byte=0xa8 & GS { pushseg88(GS); } +@endif + +:PUSHA is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & byte=0x60 { local tmp=SP; push22(AX); push22(CX); push22(DX); push22(BX); push22(tmp); push22(BP); push22(SI); push22(DI); } +:PUSHA is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0x60 { local tmp=SP; push42(AX); push42(CX); push42(DX); push42(BX); push42(tmp); push42(BP); push42(SI); push42(DI); } +:PUSHAD is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & byte=0x60 { local tmp=ESP; push24(EAX); push24(ECX); push24(EDX); push24(EBX); push24(tmp); push24(EBP); push24(ESI); push24(EDI); } +:PUSHAD is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0x60 { local tmp=ESP; push44(EAX); push44(ECX); push44(EDX); push44(EBX); push44(tmp); push44(EBP); push44(ESI); push44(EDI); } + +:PUSHF is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & byte=0x9c { packflags(flags); push22(flags); } +:PUSHF is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0x9c { packflags(flags); push42(flags); } +:PUSHFD is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & byte=0x9c { packflags(eflags); packeflags(eflags); push24(eflags); } +:PUSHFD is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0x9c { packflags(eflags); packeflags(eflags); push44(eflags); } +@ifdef IA64 +:PUSHF is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=0 & byte=0x9c { packflags(flags); push82(flags); } +:PUSHFQ is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0x9c { packflags(rflags); packeflags(rflags); push88(rflags); } +@endif + +:RCL rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 & reg_opcode=2 ... { local tmpCF = CF; CF = rm8 s< 0; rm8 = (rm8 << 1) | tmpCF; OF = CF ^ (rm8 s< 0); } +:RCL rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & reg_opcode=2 ... { local cnt=(CL&0x1f)%9; tmp:2=(zext(CF)<<8)|zext(rm8); tmp=(tmp<>(9-cnt));rm8=tmp(0); CF=(tmp&0x100)!=0; } +:RCL rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & reg_opcode=2 ... ; imm8 { local cnt=(imm8&0x1f)%9; tmp:2=(zext(CF)<<8)|zext(rm8); tmp=(tmp<>(9-cnt)); rm8=tmp(0); CF=(tmp&0x100)!=0; } +:RCL rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & reg_opcode=2 ... { local tmpCF = CF; CF = rm16 s< 0; rm16 = (rm16 << 1) | zext(tmpCF); OF = CF ^ (rm16 s< 0);} +:RCL rm16,CL is vexMode=0 & opsize=0 & byte=0xD3; CL & rm16 & reg_opcode=2 ... {local cnt=(CL&0x1f)%17; tmp:4=(zext(CF)<<16)|zext(rm16); tmp=(tmp<>(17-cnt)); rm16=tmp(0); CF=(tmp&0x10000)!=0; } +:RCL rm16,imm8 is vexMode=0 & opsize=0 & byte=0xC1; rm16 & reg_opcode=2 ... ; imm8 { local cnt=(imm8&0x1f)%17; tmp:4=(zext(CF)<<16)|zext(rm16); tmp=(tmp<>(17-cnt)); rm16=tmp(0); CF=(tmp&0x10000)!=0; } +:RCL rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & reg_opcode=2 ... { local tmpCF=CF; CF=rm32 s< 0; rm32=(rm32<<1)|zext(tmpCF); OF=CF^(rm32 s< 0); build check_rm32_dest; } +:RCL rm32,CL is vexMode=0 & opsize=1 & byte=0xD3; CL & rm32 & check_rm32_dest ... & reg_opcode=2 ... { local cnt=CL&0x1f; tmp:8=(zext(CF)<<32)|zext(rm32); tmp=(tmp<>(33-cnt)); rm32=tmp(0); CF=(tmp&0x100000000)!=0; build check_rm32_dest; } +:RCL rm32,imm8 is vexMode=0 & opsize=1 & byte=0xC1; rm32 & check_rm32_dest ... & reg_opcode=2 ... ; imm8 { local cnt=imm8&0x1f; tmp:8=(zext(CF)<<32)|zext(rm32); tmp=(tmp<>(33-cnt)); rm32=tmp(0); CF=(tmp&0x100000000)!=0; build check_rm32_dest; } +@ifdef IA64 +:RCL rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 & reg_opcode=2 ... { local tmpCF=CF; CF=rm64 s< 0; rm64=(rm64<<1)|zext(tmpCF); OF=CF^(rm64 s< 0);} +:RCL rm64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD3; CL & rm64 & reg_opcode=2 ... { local cnt=CL&0x3f; tmp:16=(zext(CF)<<64)|zext(rm64); tmp=(tmp<>(65-cnt)); rm64=tmp(0); CF=(tmp&0x1000000000000000)!=0; } +:RCL rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xC1; rm64 & reg_opcode=2 ... ; imm8 { local cnt=imm8&0x3f; tmp:16=(zext(CF)<<64)|zext(rm64); tmp=(tmp<>(65-cnt)); rm64=tmp(0); CF=(tmp&0x1000000000000000)!=0; } +@endif + +:RCR rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 & reg_opcode=3 ... { local tmpCF=CF; OF=rm8 s< 0; CF=(rm8&1)!=0; rm8=(rm8>>1)|(tmpCF<<7); OF=OF^(rm8 s< 0); } +:RCR rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & reg_opcode=3 ... { local cnt=(CL&0x1f)%9; tmp:2=(zext(CF)<<8)|zext(rm8); tmp=(tmp>>cnt)|(tmp<<(9-cnt)); rm8=tmp(0); CF=(tmp&0x100)!=0; } +:RCR rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & reg_opcode=3 ... ; imm8 { local cnt=(imm8&0x1f)%9; tmp:2=(zext(CF)<<8)|zext(rm8); tmp=(tmp>>cnt)|(tmp<<(9-cnt)); rm8=tmp(0); CF=(tmp&0x100)!=0; } +:RCR rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & reg_opcode=3 ... { local tmpCF=CF; OF=rm16 s< 0; CF=(rm16&1)!=0; rm16=(rm16>>1)|(zext(tmpCF)<<15); OF=OF^(rm16 s< 0); } +:RCR rm16,CL is vexMode=0 & opsize=0 & byte=0xD3; CL & rm16 & reg_opcode=3 ... { local cnt=(CL&0x1f)%17; tmp:4=(zext(CF)<<16)|zext(rm16); tmp=(tmp>>cnt)|(tmp<<(17-cnt)); rm16=tmp(0); CF=(tmp&0x10000)!=0; } +:RCR rm16,imm8 is vexMode=0 & opsize=0 & byte=0xC1; rm16 & reg_opcode=3 ... ; imm8 { local cnt=(imm8&0x1f)%17; tmp:4=(zext(CF)<<16)|zext(rm16); tmp=(tmp>>cnt)|(tmp<<(17-cnt)); rm16=tmp(0); CF=(tmp&0x10000)!=0; } +:RCR rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & reg_opcode=3 ... { local tmpCF=CF; OF=rm32 s< 0; CF=(rm32&1)!=0; rm32=(rm32>>1)|(zext(tmpCF)<<31); OF=OF^(rm32 s< 0); build check_rm32_dest; } +:RCR rm32,CL is vexMode=0 & opsize=1 & byte=0xD3; CL & rm32 & check_rm32_dest ... & reg_opcode=3 ... { local cnt=CL&0x1f; tmp:8=(zext(CF)<<32)|zext(rm32); tmp=(tmp>>cnt)|(tmp<<(33-cnt)); rm32=tmp(0); CF=(tmp&0x100000000)!=0; build check_rm32_dest; } +:RCR rm32,imm8 is vexMode=0 & opsize=1 & byte=0xC1; rm32 & check_rm32_dest ... & reg_opcode=3 ... ; imm8 { local cnt=imm8&0x1f; tmp:8=(zext(CF)<<32)|zext(rm32); tmp=(tmp>>cnt)|(tmp<<(33-cnt)); rm32=tmp(0); CF=(tmp&0x100000000)!=0; build check_rm32_dest; } +@ifdef IA64 +:RCR rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 & reg_opcode=3 ... { local tmpCF=CF; OF=rm64 s< 0; CF=(rm64&1)!=0; rm64=(rm64>>1)|(zext(tmpCF)<<63); OF=OF^(rm64 s< 0); } +:RCR rm64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD3; CL & rm64 & reg_opcode=3 ... { local cnt=CL&0x3f; tmp:16=(zext(CF)<<64)|zext(rm64); tmp=(tmp>>cnt)|(tmp<<(65-cnt)); rm64=tmp(0); CF=(tmp&0x1000000000000000)!=0; } +:RCR rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xC1; rm64 & reg_opcode=3 ... ; imm8 { local cnt=imm8&0x3f; tmp:16=(zext(CF)<<64)|zext(rm64); tmp=(tmp>>cnt)|(tmp<<(65-cnt)); rm64=tmp(0); CF=(tmp&0x1000000000000000)!=0; } +@endif + +@ifdef IA64 +define pcodeop readfsbase; +:RDFSBASE r32 is vexMode=0 & opsize=1 & $(PRE_F3) & byte=0x0f; byte=0xae; reg_opcode=0 & r32 { r32 = readfsbase(); } +:RDFSBASE r64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0f; byte=0xae; reg_opcode=0 & r64 { r64 = readfsbase(); } + +define pcodeop readgsbase; +:RDGSBASE r32 is vexMode=0 & opsize=1 & $(PRE_F3) & byte=0x0f; byte=0xae; reg_opcode=1 & r32 { r32 = readgsbase(); } +:RDGSBASE r64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0f; byte=0xae; reg_opcode=1 & r64 { r64 = readgsbase(); } +@endif + +define pcodeop rdmsr; +:RDMSR is vexMode=0 & byte=0xf; byte=0x32 & check_EAX_dest & check_EDX_dest { + tmp:8 = rdmsr(ECX); + EDX = tmp(4); build check_EDX_dest; + EAX = tmp(0); build check_EAX_dest; +} + +define pcodeop readPID; +:RDPID r32 is vexMode=0 & opsize=1 & $(PRE_F3) & byte=0x0f; byte=0xc7; reg_opcode=7 & r32 { r32 = readPID(); } +@ifdef IA64 +:RDPID r64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0f; byte=0xc7; reg_opcode=7 & r64 { r64 = readPID(); } +@endif + +define pcodeop rdpkru_u32; +:RDPKRU is vexMode=0 & byte=0x0f; byte=0x01; byte=0xee { EAX = rdpkru_u32(); } + +define pcodeop rdpmc; +:RDPMC is vexMode=0 & byte=0xf; byte=0x33 { tmp:8 = rdpmc(ECX); EDX = tmp(4); EAX = tmp:4; } + +define pcodeop rdtsc; +:RDTSC is vexMode=0 & byte=0xf; byte=0x31 { tmp:8 = rdtsc(); EDX = tmp(4); EAX = tmp(0); } + +:RET is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & byte=0xc3 { pop22(IP); EIP=segment(CS,IP); return [EIP]; } +:RET is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0xc3 { pop42(IP); EIP=zext(IP); return [EIP]; } +:RET is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & byte=0xc3 { pop24(EIP); return [EIP]; } +:RET is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0xc3 { pop44(EIP); return [EIP]; } +@ifdef IA64 +:RET is $(LONGMODE_ON) & vexMode=0 & byte=0xc3 { pop88(RIP); return [RIP]; } +@endif + +:RETF is vexMode=0 & addrsize=0 & opsize=0 & byte=0xcb { pop22(IP); pop22(CS); EIP = segment(CS,IP); return [EIP]; } +:RETF is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0xcb { pop42(IP); EIP=zext(IP); pop42(CS); return [EIP]; } +@ifdef IA64 +:RETF is $(LONGMODE_ON) & vexMode=0 & addrsize=1 & opsize=0 & byte=0xcb { pop82(IP); RIP=zext(IP); pop82(CS); return [RIP]; } +:RETF is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=0 & byte=0xcb { pop82(IP); RIP=zext(IP); pop82(CS); return [RIP]; } +@endif +:RETF is vexMode=0 & addrsize=0 & opsize=1 & byte=0xcb { pop24(EIP); tmp:4=0; pop24(tmp); CS=tmp(0); return [EIP]; } +:RETF is vexMode=0 & addrsize=1 & opsize=1 & byte=0xcb { pop44(EIP); tmp:4=0; pop44(tmp); CS=tmp(0); return [EIP]; } +@ifdef IA64 +:RETF is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=1 & byte=0xcb { pop84(EIP); RIP=zext(EIP); tmp:4=0; pop84(tmp); CS=tmp(0); return [RIP]; } +:RETF is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=2 & byte=0xcb { pop88(RIP); tmp:8=0; pop88(tmp); CS=tmp(0); return [RIP]; } +@endif + +:RET imm16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & byte=0xc2; imm16 { pop22(IP); EIP=zext(IP); SP=SP+imm16; return [EIP]; } +:RET imm16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0xc2; imm16 { pop42(IP); EIP=zext(IP); ESP=ESP+imm16; return [EIP]; } +:RET imm16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & byte=0xc2; imm16 { pop24(EIP); SP=SP+imm16; return [EIP]; } +:RET imm16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0xc2; imm16 { pop44(EIP); ESP=ESP+imm16; return [EIP]; } +@ifdef IA64 +:RET imm16 is $(LONGMODE_ON) & vexMode=0 & byte=0xc2; imm16 { pop88(RIP); RSP=RSP+imm16; return [RIP]; } +@endif + +:RETF imm16 is vexMode=0 & addrsize=0 & opsize=0 & byte=0xca; imm16 { pop22(IP); EIP=zext(IP); pop22(CS); SP=SP+imm16; return [EIP]; } +:RETF imm16 is vexMode=0 & addrsize=1 & opsize=0 & byte=0xca; imm16 { pop42(IP); EIP=zext(IP); pop42(CS); ESP=ESP+imm16; return [EIP]; } +@ifdef IA64 +:RETF imm16 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=0 & byte=0xca; imm16 { pop42(IP); RIP=zext(IP); pop42(CS); RSP=RSP+imm16; return [RIP]; } +@endif + +:RETF imm16 is vexMode=0 & addrsize=0 & opsize=1 & byte=0xca; imm16 { pop24(EIP); tmp:4=0; pop24(tmp); CS=tmp(0); SP=SP+imm16; return [EIP]; } +:RETF imm16 is vexMode=0 & addrsize=1 & opsize=1 & byte=0xca; imm16 { pop44(EIP); tmp:4=0; pop44(tmp); CS=tmp(0); ESP=ESP+imm16; return [EIP]; } +@ifdef IA64 +:RETF imm16 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=1 & byte=0xca; imm16 { pop44(EIP); tmp:4=0; pop44(tmp); RIP=zext(EIP); CS=tmp(0); RSP=RSP+imm16; return [RIP]; } +:RETF imm16 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=2 & byte=0xca; imm16 { pop88(RIP); tmp:8=0; pop88(tmp); CS=tmp(0); RSP=RSP+imm16; return [RIP]; } +@endif + +:ROL rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 & reg_opcode=0 ... { CF = rm8 s< 0; rm8 = (rm8 << 1) | CF; OF = CF ^ (rm8 s< 0); } +:ROL rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & reg_opcode=0 ... { local cnt = CL & 0x7; local count_and_mask = CL & 0x1f;rm8 = (rm8 << cnt) | (rm8 >> (8 - cnt)); rolflags(rm8, count_and_mask);} +:ROL rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & reg_opcode=0 ... ; imm8 { local cnt = imm8 & 0x7; rm8 = (rm8 << cnt) | (rm8 >> (8 - cnt)); rolflags(rm8,imm8 & 0x1f:1);} +:ROL rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & reg_opcode=0 ... { CF = rm16 s< 0; rm16 = (rm16 << 1) | zext(CF); OF = CF ^ (rm16 s< 0); } +:ROL rm16,CL is vexMode=0 & opsize=0 & byte=0xD3; CL & rm16 & reg_opcode=0 ... { local cnt = CL & 0xf; local count_and_mask = CL & 0x1f;rm16 = (rm16 << cnt) | (rm16 >> (16 - cnt)); rolflags(rm16,count_and_mask);} +:ROL rm16,imm8 is vexMode=0 & opsize=0 & byte=0xC1; rm16 & reg_opcode=0 ... ; imm8 { local cnt = imm8 & 0xf; rm16 = (rm16 << cnt) | (rm16 >> (16 - cnt)); rolflags(rm16,imm8 & 0x1f:1);} +:ROL rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & reg_opcode=0 ... { CF = rm32 s< 0; rm32 = (rm32 << 1) | zext(CF); OF = CF ^ (rm32 s< 0); build check_rm32_dest; } +:ROL rm32,CL is vexMode=0 & opsize=1 & byte=0xD3; CL & rm32 & check_rm32_dest ... & reg_opcode=0 ... { local cnt = CL & 0x1f; rm32 = (rm32 << cnt) | (rm32 >> (32 - cnt)); rolflags(rm32,cnt); build check_rm32_dest; } +:ROL rm32,imm8 is vexMode=0 & opsize=1 & byte=0xC1; rm32 & check_rm32_dest ... & reg_opcode=0 ... ; imm8 { local cnt = imm8 & 0x1f; rm32 = (rm32 << cnt) | (rm32 >> (32 - cnt)); rolflags(rm32,cnt); build check_rm32_dest; } +@ifdef IA64 +:ROL rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 & reg_opcode=0 ... { CF = rm64 s< 0; rm64 = (rm64 << 1) | zext(CF); OF = CF ^ (rm64 s< 0); } +:ROL rm64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD3; CL & rm64 & reg_opcode=0 ... { local cnt = CL & 0x3f; rm64 = (rm64 << cnt) | (rm64 >> (64 - cnt)); rolflags(rm64,cnt);} +:ROL rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xC1; rm64 & reg_opcode=0 ... ; imm8 { local cnt = imm8 & 0x3f; rm64 = (rm64 << cnt) | (rm64 >> (64 - cnt)); rolflags(rm64,cnt);} +@endif + +:ROR rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 & reg_opcode=1 ... { CF = rm8 & 1; rm8 = (rm8 >> 1) | (CF << 7); OF = ((rm8 & 0x40) != 0) ^ (rm8 s< 0); } +:ROR rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & reg_opcode=1 ... { local cnt = CL & 0x7; local count_and_mask = CL & 0x1f;rm8 = (rm8 >> cnt) | (rm8 << (8 - cnt)); rorflags(rm8,count_and_mask);} +:ROR rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & reg_opcode=1 ... ; imm8 { local cnt = imm8 & 0x7; rm8 = (rm8 >> cnt) | (rm8 << (8 - cnt)); rorflags(rm8,imm8 & 0x1f:1);} +:ROR rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & reg_opcode=1 ... { CF=(rm16 & 1)!=0; rm16=(rm16>>1)|(zext(CF)<<15); OF=((rm16 & 0x4000) != 0) ^ (rm16 s< 0); } +:ROR rm16,CL is vexMode=0 & opsize=0 & byte=0xD3; CL & rm16 & reg_opcode=1 ... { local cnt = CL & 0xf; local count_and_mask = CL & 0x1f; rm16 = (rm16 >> cnt) | (rm16 << (16 - cnt)); rorflags(rm16,count_and_mask);} +:ROR rm16,imm8 is vexMode=0 & opsize=0 & byte=0xC1; rm16 & reg_opcode=1 ... ; imm8 { local cnt = imm8 & 0xf; rm16 = (rm16 >> cnt) | (rm16 << (16 - cnt)); rorflags(rm16,imm8 & 0x1f:1);} +:ROR rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & reg_opcode=1 ... { CF=(rm32&1)!=0; rm32=(rm32>>1)|(zext(CF)<<31); OF=((rm32&0x40000000)!=0) ^ (rm32 s< 0); build check_rm32_dest; } +:ROR rm32,CL is vexMode=0 & opsize=1 & byte=0xD3; CL & rm32 & check_rm32_dest ... & reg_opcode=1 ... { local cnt = CL & 0x1f; rm32 = (rm32 >> cnt) | (rm32 << (32 - cnt)); rorflags(rm32,cnt); build check_rm32_dest; } +:ROR rm32,imm8 is vexMode=0 & opsize=1 & byte=0xC1; rm32 & check_rm32_dest ... & reg_opcode=1 ... ; imm8 { local cnt = imm8 & 0x1f; rm32 = (rm32 >> cnt) | (rm32 << (32 - cnt)); rorflags(rm32,cnt); build check_rm32_dest; } +@ifdef IA64 +:ROR rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 & reg_opcode=1 ... { CF=(rm64&1)!=0; rm64=(rm64>>1)|(zext(CF)<<63); OF=((rm64&0x4000000000000000)!=0) ^ (rm64 s< 0); } +:ROR rm64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD3; CL & rm64 & reg_opcode=1 ... { local cnt = CL & 0x3f; rm64 = (rm64 >> cnt) | (rm64 << (64 - cnt)); rorflags(rm64,cnt);} +:ROR rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xC1; rm64 & reg_opcode=1 ... ; imm8 { local cnt = imm8 & 0x3f; rm64 = (rm64 >> cnt) | (rm64 << (64 - cnt)); rorflags(rm64,cnt);} +@endif + +define pcodeop smm_restore_state; +:RSM is vexMode=0 & byte=0xf; byte=0xaa { tmp:4 = smm_restore_state(); return [tmp]; } + +# Initially disallowed in 64bit mode, but later reintroduced +:SAHF is vexMode=0 & byte=0x9e { SF = (AH & 0x80) != 0; + ZF = (AH & 0x40) != 0; + AF = (AH & 0x10) != 0; + PF = (AH & 0x04) != 0; + CF = (AH & 0x01) != 0; } + +:SALC is $(LONGMODE_OFF) & vexMode=0 & byte=0xd6 { AL = CF * 0xff; } + +:SAR rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 & reg_opcode=7 ... { CF = rm8 & 1; OF = 0; rm8 = rm8 s>> 1; resultflags(rm8); } +:SAR rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & reg_opcode=7 ... { local count = CL & 0x1f; local tmp = rm8; rm8 = rm8 s>> count; + sarflags(tmp, rm8,count); shiftresultflags(rm8,count); } +:SAR rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & reg_opcode=7 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm8; rm8 = rm8 s>> count; + sarflags(tmp, rm8,count); shiftresultflags(rm8,count); } +:SAR rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & reg_opcode=7 ... { CF = (rm16 & 1) != 0; OF = 0; rm16 = rm16 s>> 1; resultflags(rm16); } +:SAR rm16,CL is vexMode=0 & opsize=0 & byte=0xD3; CL & rm16 & reg_opcode=7 ... { local count = CL & 0x1f; local tmp = rm16; rm16 = rm16 s>> count; + sarflags(tmp, rm16,count); shiftresultflags(rm16,count); } +:SAR rm16,imm8 is vexMode=0 & opsize=0 & byte=0xC1; rm16 & reg_opcode=7 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm16; rm16 = rm16 s>> count; + sarflags(tmp, rm16,count); shiftresultflags(rm16,count); } +:SAR rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & reg_opcode=7 ... { CF = (rm32 & 1) != 0; OF = 0; rm32 = rm32 s>> 1; build check_rm32_dest; resultflags(rm32); } +:SAR rm32,CL is vexMode=0 & opsize=1 & byte=0xD3; CL & rm32 & check_rm32_dest ... & reg_opcode=7 ... { local count = CL & 0x1f; local tmp = rm32; rm32 = rm32 s>> count; build check_rm32_dest; + sarflags(tmp, rm32,count); shiftresultflags(rm32,count); } +:SAR rm32,imm8 is vexMode=0 & opsize=1 & byte=0xC1; rm32 & check_rm32_dest ... & reg_opcode=7 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm32; rm32 = rm32 s>> count; build check_rm32_dest; + sarflags(tmp, rm32,count); shiftresultflags(rm32,count); } +@ifdef IA64 +:SAR rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 & reg_opcode=7 ... { CF = (rm64 & 1) != 0; OF = 0; rm64 = rm64 s>> 1; resultflags(rm64); } +:SAR rm64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD3; CL & rm64 & reg_opcode=7 ... { local count = CL & 0x3f; local tmp = rm64; rm64 = rm64 s>> count; + sarflags(tmp, rm64,count); shiftresultflags(rm64,count); } +:SAR rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xC1; rm64 & reg_opcode=7 ... ; imm8 { local count = imm8 & 0x3f; local tmp = rm64; rm64 = rm64 s>> count; + sarflags(tmp, rm64,count); shiftresultflags(rm64,count); } +@endif + +# See 'lockable.sinc' for memory destination, lockable variants +:SBB AL,imm8 is vexMode=0 & byte=0x1c; AL & imm8 { subCarryFlags( AL, imm8 ); resultflags(AL); } +:SBB AX,imm16 is vexMode=0 & opsize=0 & byte=0x1d; AX & imm16 { subCarryFlags( AX, imm16 ); resultflags(AX); } +:SBB EAX,imm32 is vexMode=0 & opsize=1 & byte=0x1d; EAX & check_EAX_dest & imm32 { subCarryFlags( EAX, imm32 ); build check_EAX_dest; resultflags(EAX); } +@ifdef IA64 +:SBB RAX,simm32_64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x1d; RAX & simm32_64 { subCarryFlags( RAX, simm32_64 ); resultflags(RAX); } +@endif +:SBB Rmr8,imm8 is vexMode=0 & $(BYTE_80_82); mod=3 & Rmr8 & reg_opcode=3; imm8 { subCarryFlags( Rmr8, imm8 ); resultflags(Rmr8); } +:SBB Rmr16,imm16 is vexMode=0 & opsize=0 & byte=0x81; mod=3 & Rmr16 & reg_opcode=3; imm16 { subCarryFlags( Rmr16, imm16 ); resultflags(Rmr16); } +:SBB Rmr32,imm32 is vexMode=0 & opsize=1 & byte=0x81; mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=3; imm32 { subCarryFlags( Rmr32, imm32 ); build check_Rmr32_dest; resultflags(Rmr32); } +@ifdef IA64 +:SBB Rmr64,imm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x81; mod=3 & Rmr64 & reg_opcode=3; imm32 { subCarryFlags( Rmr64, imm32 ); resultflags(Rmr64); } +@endif + +:SBB Rmr16,simm8_16 is vexMode=0 & opsize=0 & byte=0x83; mod=3 & Rmr16 & reg_opcode=3; simm8_16 { subCarryFlags( Rmr16, simm8_16 ); resultflags(Rmr16); } +:SBB Rmr32,simm8_32 is vexMode=0 & opsize=1 & byte=0x83; mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=3; simm8_32 { subCarryFlags( Rmr32, simm8_32 ); build check_Rmr32_dest; resultflags(Rmr32); } +@ifdef IA64 +:SBB Rmr64,simm8_64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x83; mod=3 & Rmr64 & reg_opcode=3; simm8_64 { subCarryFlags( Rmr64, simm8_64 ); resultflags(Rmr64); } +@endif + +:SBB Rmr8,Reg8 is vexMode=0 & byte=0x18; mod=3 & Rmr8 & Reg8 { subCarryFlags( Rmr8, Reg8 ); resultflags(Rmr8); } +:SBB Rmr16,Reg16 is vexMode=0 & opsize=0 & byte=0x19; mod=3 & Rmr16 & Reg16 { subCarryFlags( Rmr16, Reg16 ); resultflags(Rmr16); } +:SBB Rmr32,Reg32 is vexMode=0 & opsize=1 & byte=0x19; mod=3 & Rmr32 & check_Rmr32_dest & Reg32 { subCarryFlags( Rmr32, Reg32 ); build check_Rmr32_dest; resultflags(Rmr32); } +@ifdef IA64 +:SBB Rmr64,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x19; mod=3 & Rmr64 & Reg64 { subCarryFlags( Rmr64, Reg64 ); resultflags(Rmr64); } +@endif + +:SBB Reg8,rm8 is vexMode=0 & byte=0x1a; rm8 & Reg8 ... { subCarryFlags( Reg8, rm8 ); resultflags(Reg8); } +:SBB Reg16,rm16 is vexMode=0 & opsize=0 & byte=0x1b; rm16 & Reg16 ... { subCarryFlags( Reg16, rm16 ); resultflags(Reg16); } +:SBB Reg32,rm32 is vexMode=0 & opsize=1 & byte=0x1b; rm32 & Reg32 ... & check_Reg32_dest ... { subCarryFlags( Reg32, rm32 ); build check_Reg32_dest; resultflags(Reg32); } +@ifdef IA64 +:SBB Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x1b; rm64 & Reg64 ... { subCarryFlags( Reg64, rm64 ); resultflags(Reg64); } +@endif + +:SCASB^repe^repetail eseDI1 is vexMode=0 & repe & repetail & byte=0xae & eseDI1 { build repe; build eseDI1; subflags(AL,eseDI1); local diff=AL-eseDI1; resultflags(diff); build repetail; } +:SCASW^repe^repetail eseDI2 is vexMode=0 & repe & repetail & opsize=0 & byte=0xaf & eseDI2 { build repe; build eseDI2; subflags(AX,eseDI2); local diff=AX-eseDI2; resultflags(diff); build repetail; } +:SCASD^repe^repetail eseDI4 is vexMode=0 & repe & repetail & opsize=1 & byte=0xaf & eseDI4 { build repe; build eseDI4; subflags(EAX,eseDI4); local diff=EAX-eseDI4; resultflags(diff); build repetail; } +@ifdef IA64 +:SCASQ^repe^repetail eseDI8 is $(LONGMODE_ON) & vexMode=0 & repe & repetail & opsize=2 & byte=0xaf & eseDI8 { build repe; build eseDI8; subflags(RAX,eseDI8); local diff=RAX-eseDI8; resultflags(diff); build repetail; } +@endif + +:SET^cc rm8 is vexMode=0 & byte=0xf; row=9 & cc; rm8 { rm8 = cc; } + +# manual is not consistent on operands +:SGDT m16 is vexMode=0 & opsize=0 & byte=0xf; byte=0x1; ( mod != 0b11 & reg_opcode=0 ) ... & m16 +{ + m16 = GlobalDescriptorTableRegister(); +} + +:SGDT m32 is vexMode=0 & opsize=1 & byte=0xf; byte=0x1; ( mod != 0b11 & reg_opcode=0 ) ... & m32 +{ + m32 = GlobalDescriptorTableRegister(); +} + +@ifdef IA64 +:SGDT m64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0x1; ( mod != 0b11 & reg_opcode=0 ) ... & m64 +{ + m64 = GlobalDescriptorTableRegister(); +} +@endif + + +:SHL rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 &(reg_opcode=4|reg_opcode=6) ... { CF = rm8 s< 0; rm8 = rm8 << 1; OF = CF ^^ (rm8 s< 0); resultflags(rm8); } +:SHL rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & (reg_opcode=4|reg_opcode=6) ... { local count = CL & 0x1f; local tmp = rm8; rm8 = rm8 << count; + shlflags(tmp, rm8,count); shiftresultflags(rm8,count); } +:SHL rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & (reg_opcode=4|reg_opcode=6) ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm8; rm8 = rm8 << count; + shlflags(tmp, rm8,count); shiftresultflags(rm8,count); } +:SHL rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & (reg_opcode=4|reg_opcode=6) ... { CF = rm16 s< 0; rm16 = rm16 << 1; OF = CF ^^ (rm16 s< 0); resultflags(rm16); } +:SHL rm16,CL is vexMode=0 & opsize=0 & byte=0xD3; CL & rm16 & (reg_opcode=4|reg_opcode=6) ... { local count = CL & 0x1f; local tmp = rm16; rm16 = rm16 << count; + shlflags(tmp, rm16,count); shiftresultflags(rm16,count); } +:SHL rm16,imm8 is vexMode=0 & opsize=0 & byte=0xC1; rm16 & (reg_opcode=4|reg_opcode=6) ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm16; rm16 = rm16 << count; + shlflags(tmp, rm16,count); shiftresultflags(rm16,count); } +:SHL rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & (reg_opcode=4|reg_opcode=6) ... { CF = rm32 s< 0; rm32 = rm32 << 1; OF = CF ^^ (rm32 s< 0); build check_rm32_dest; resultflags(rm32); } +:SHL rm32,CL is vexMode=0 & opsize=1 & byte=0xD3; CL & rm32 & check_rm32_dest ... & (reg_opcode=4|reg_opcode=6) ... { local count = CL & 0x1f; local tmp = rm32; rm32 = rm32 << count; build check_rm32_dest; + shlflags(tmp, rm32,count); shiftresultflags(rm32,count); } +:SHL rm32,imm8 is vexMode=0 & opsize=1 & byte=0xC1; rm32 & check_rm32_dest ... & (reg_opcode=4|reg_opcode=6) ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm32; rm32 = rm32 << count; build check_rm32_dest; + shlflags(tmp, rm32,count); shiftresultflags(rm32,count); } +@ifdef IA64 +:SHL rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 & (reg_opcode=4|reg_opcode=6) ... { CF = rm64 s< 0; rm64 = rm64 << 1; OF = CF ^^ (rm64 s< 0); resultflags(rm64); } +:SHL rm64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD3; CL & rm64 & (reg_opcode=4|reg_opcode=6) ... { local count = CL & 0x3f; local tmp = rm64; rm64 = rm64 << count; + shlflags(tmp, rm64,count); shiftresultflags(rm64,count); } +:SHL rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xC1; rm64 & (reg_opcode=4|reg_opcode=6) ... ; imm8 { local count = imm8 & 0x3f; local tmp = rm64; rm64 = rm64 << count; + shlflags(tmp, rm64,count); shiftresultflags(rm64,count); } +@endif + +:SHLD rm16,Reg16,imm8 is vexMode=0 & opsize=0; byte=0x0F; byte=0xA4; rm16 & Reg16 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm16; + rm16 = (rm16 << count) | (Reg16 >> (16 - count)); + shlflags(tmp,rm16,count); shiftresultflags(rm16,count);} +:SHLD rm16,Reg16,CL is vexMode=0 & opsize=0; byte=0x0F; byte=0xA5; CL & rm16 & Reg16 ... { local count = CL & 0x1f; local tmp = rm16; + rm16 = (rm16 << count) | (Reg16 >> (16 - count)); + shlflags(tmp,rm16,count); shiftresultflags(rm16,count); } +:SHLD rm32,Reg32,imm8 is vexMode=0 & opsize=1; byte=0x0F; byte=0xA4; rm32 & check_rm32_dest ... & Reg32 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm32; + rm32 = (rm32 << count) | (Reg32 >> (32 - count)); build check_rm32_dest; + shlflags(tmp,rm32,count); shiftresultflags(rm32,count); } +:SHLD rm32,Reg32,CL is vexMode=0 & opsize=1; byte=0x0F; byte=0xA5; CL & rm32 & check_rm32_dest ... & Reg32 ... { local count = CL & 0x1f; local tmp = rm32; + rm32 = (rm32 << count) | (Reg32 >> (32 - count)); build check_rm32_dest; + shlflags(tmp,rm32,count); shiftresultflags(rm32,count); } +@ifdef IA64 +:SHLD rm64,Reg64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2; byte=0x0F; byte=0xA4; rm64 & Reg64 ... ; imm8 { local count = imm8 & 0x3f; local tmp = rm64; + rm64 = (rm64 << count) | (Reg64 >> (64 - count)); + shlflags(tmp,rm64,count); shiftresultflags(rm64,count); } +:SHLD rm64,Reg64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2; byte=0x0F; byte=0xA5; CL & rm64 & Reg64 ... { local count = CL & 0x3f; local tmp = rm64; + rm64 = (rm64 << count) | (Reg64 >> (64 - count)); + shlflags(tmp,rm64,count); shiftresultflags(rm64,count); } +@endif + +:SHRD rm16,Reg16,imm8 is vexMode=0 & opsize=0; byte=0x0F; byte=0xAC; rm16 & Reg16 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm16; + rm16 = (rm16 >> count) | (Reg16 << (16 - count)); + shrdflags(tmp,rm16,count); shiftresultflags(rm16,count); } +:SHRD rm16,Reg16,CL is vexMode=0 & opsize=0; byte=0x0F; byte=0xAD; CL & rm16 & Reg16 ... { local count = CL & 0x1f; local tmp = rm16; + rm16 = (rm16 >> count) | (Reg16 << (16 - count)); + shrdflags(tmp,rm16,count); shiftresultflags(rm16,count); } +:SHRD rm32,Reg32,imm8 is vexMode=0 & opsize=1; byte=0x0F; byte=0xAC; rm32 & check_rm32_dest ... & Reg32 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm32; + rm32 = (rm32 >> count) | (Reg32 << (32 - count)); build check_rm32_dest; + shrdflags(tmp,rm32,count); shiftresultflags(rm32,count); } +:SHRD rm32,Reg32,CL is vexMode=0 & opsize=1; byte=0x0F; byte=0xAD; CL & rm32 & check_rm32_dest ... & Reg32 ... { local count = CL & 0x1f; local tmp = rm32; + rm32 = (rm32 >> count) | (Reg32 << (32 - count)); build check_rm32_dest; + shrdflags(tmp,rm32,count); shiftresultflags(rm32,count); } +@ifdef IA64 +:SHRD rm64,Reg64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2; byte=0x0F; byte=0xAC; rm64 & Reg64 ... ; imm8 { local count = imm8 & 0x3f; local tmp = rm64; + rm64 = (rm64 >> count) | (Reg64 << (64 - count)); + shrdflags(tmp,rm64,count); shiftresultflags(rm64,count); } +:SHRD rm64,Reg64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2; byte=0x0F; byte=0xAD; CL & rm64 & Reg64 ... { local count = CL & 0x3f; local tmp = rm64; + rm64 = (rm64 >> count) | (Reg64 << (64 - count)); + shrdflags(tmp,rm64,count); shiftresultflags(rm64,count); } +@endif + +:SHR rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 & reg_opcode=5 ... { CF = rm8 & 1; OF = 0; rm8 = rm8 >> 1; resultflags(rm8); } +:SHR rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & reg_opcode=5 ... { local count = CL & 0x1f; local tmp = rm8; rm8 = rm8 >> count; + shrflags(tmp, rm8,count); shiftresultflags(rm8,count); } +:SHR rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & reg_opcode=5 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm8; rm8 = rm8 >> count; + shrflags(tmp, rm8,count); shiftresultflags(rm8,count); } +:SHR rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & reg_opcode=5 ... { CF = (rm16 & 1) != 0; OF = 0; rm16 = rm16 >> 1; resultflags(rm16); } +:SHR rm16,CL is vexMode=0 & opsize=0 & byte=0xD3; CL & rm16 & reg_opcode=5 ... { local count = CL & 0x1f; local tmp = rm16; rm16 = rm16 >> count; + shrflags(tmp, rm16,count); shiftresultflags(rm16,count); } +:SHR rm16,imm8 is vexMode=0 & opsize=0 & byte=0xC1; rm16 & reg_opcode=5 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm16; rm16 = rm16 >> count; + shrflags(tmp, rm16,count); shiftresultflags(rm16,count); } +:SHR rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & reg_opcode=5 ... { CF = (rm32 & 1) != 0; OF = 0; rm32 = rm32 >> 1; build check_rm32_dest; resultflags(rm32); } +:SHR rm32,CL is vexMode=0 & opsize=1 & byte=0xD3; CL & rm32 & check_rm32_dest ... & reg_opcode=5 ... { local count = CL & 0x1f; local tmp = rm32; rm32 = rm32 >> count; build check_rm32_dest; + shrflags(tmp, rm32,count); shiftresultflags(rm32,count); } +:SHR rm32,imm8 is vexMode=0 & opsize=1 & byte=0xC1; rm32 & check_rm32_dest ... & reg_opcode=5 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm32; rm32 = rm32 >> count; build check_rm32_dest; + shrflags(tmp, rm32,count); shiftresultflags(rm32,count); } +@ifdef IA64 +:SHR rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 ®_opcode=5 ... { CF = (rm64 & 1) != 0; OF = 0; rm64 = rm64 >> 1; resultflags(rm64); } +:SHR rm64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD3; CL & rm64 & reg_opcode=5 ... { local count = CL & 0x3f; local tmp = rm64; rm64 = rm64 >> count; + shrflags(tmp, rm64,count); shiftresultflags(rm64,count); } +:SHR rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xC1; rm64 & reg_opcode=5 ... ; imm8 { local count = imm8 & 0x3f; local tmp = rm64; rm64 = rm64 >> count; + shrflags(tmp, rm64,count); shiftresultflags(rm64,count); } +@endif + +:SIDT m16 is vexMode=0 & opsize=0 & byte=0xf; byte=0x1; ( mod != 0b11 & reg_opcode=1 ) ... & m16 +{ + m16 = InterruptDescriptorTableRegister(); +} + +:SIDT m32 is vexMode=0 & opsize=1 & byte=0xf; byte=0x1; ( mod != 0b11 & reg_opcode=1 ) ... & m32 +{ + m32 = InterruptDescriptorTableRegister(); +} +@ifdef IA64 +:SIDT m64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0x1; ( mod != 0b11 & reg_opcode=1 ) ... & m64 +{ + m64 = InterruptDescriptorTableRegister(); +} +@endif + +define pcodeop skinit; +:SKINIT EAX is vexMode=0 & byte=0x0f; byte=0x01; byte=0xde & EAX { skinit(EAX); } + +:SLDT rm16 is vexMode=0 & opsize=0 & byte=0xf; byte=0x0; rm16 & reg_opcode=0 ... +{ + rm16 = LocalDescriptorTableRegister(); +} +:SLDT rm32 is vexMode=0 & opsize=1 & byte=0xf; byte=0x0; rm32 & reg_opcode=0 ... +{ + rm32 = LocalDescriptorTableRegister(); +} +@ifdef IA64 +:SLDT rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0x0; rm64 & reg_opcode=0 ... +{ + rm64 = LocalDescriptorTableRegister(); +} +@endif + +:SMSW rm16 is vexMode=0 & opsize=0 & byte=0xf; byte=0x01; rm16 & reg_opcode=4 ... { rm16 = CR0:2; } +:SMSW rm32 is vexMode=0 & opsize=1 & byte=0xf; byte=0x01; rm32 & reg_opcode=4 ... { rm32 = zext(CR0:2); } +@ifdef IA64 +:SMSW rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf; byte=0x01; rm64 & reg_opcode=4 ... { rm64 = CR0; } +@endif + +:STAC is vexMode=0 & byte=0x0f; byte=0x01; byte=0xcb { AC = 1; } +:STC is vexMode=0 & byte=0xf9 { CF = 1; } +:STD is vexMode=0 & byte=0xfd { DF = 1; } +# MFL: AMD instruction +# TODO: define the action. +# STGI: set global interrupt flag (GIF); while GIF is zero, all external interrupts are disabled. +:STGI is vexMode=0 & byte=0x0f; byte=0x01; byte=0xdc { stgi(); } +:STI is vexMode=0 & byte=0xfb { IF = 1; } + +:STMXCSR m32 is vexMode=0 & byte=0xf; byte=0xae; ( mod != 0b11 & reg_opcode=3 ) ... & m32 { m32 = MXCSR; } + +:STOSB^rep^reptail eseDI1 is vexMode=0 & rep & reptail & byte=0xaa & eseDI1 { build rep; build eseDI1; eseDI1=AL; build reptail; } +:STOSW^rep^reptail eseDI2 is vexMode=0 & rep & reptail & opsize=0 & byte=0xab & eseDI2 { build rep; build eseDI2; eseDI2=AX; build reptail; } +:STOSD^rep^reptail eseDI4 is vexMode=0 & rep & reptail & opsize=1 & byte=0xab & eseDI4 { build rep; build eseDI4; eseDI4=EAX; build reptail; } +@ifdef IA64 +:STOSQ^rep^reptail eseDI8 is $(LONGMODE_ON) & vexMode=0 & rep & reptail & opsize=2 & byte=0xab & eseDI8 { build rep; build eseDI8; eseDI8=RAX; build reptail; } +@endif + +:STR rm16 is vexMode=0 & byte=0xf; byte=0x0; rm16 & reg_opcode=1 ... { rm16 = TaskRegister(); } + +# See 'lockable.sinc' for memory destination, lockable variants +:SUB AL,imm8 is vexMode=0 & byte=0x2c; AL & imm8 { subflags( AL,imm8 ); AL = AL - imm8; resultflags( AL); } +:SUB AX,imm16 is vexMode=0 & opsize=0 & byte=0x2d; AX & imm16 { subflags( AX,imm16); AX = AX - imm16; resultflags( AX); } +:SUB EAX,imm32 is vexMode=0 & opsize=1 & byte=0x2d; EAX & check_EAX_dest & imm32 { subflags( EAX,imm32); EAX = EAX - imm32; build check_EAX_dest; resultflags( EAX); } +@ifdef IA64 +:SUB RAX,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x2d; RAX & simm32 { subflags( RAX,simm32); RAX = RAX - simm32; resultflags( RAX); } +@endif +:SUB Rmr8,imm8 is vexMode=0 & $(BYTE_80_82); mod=3 & Rmr8 & reg_opcode=5; imm8 { subflags( Rmr8,imm8 ); Rmr8 = Rmr8 - imm8; resultflags( Rmr8); } +:SUB Rmr16,imm16 is vexMode=0 & opsize=0 & byte=0x81; mod=3 & Rmr16 & reg_opcode=5; imm16 { subflags( Rmr16,imm16); Rmr16 = Rmr16 - imm16; resultflags( Rmr16); } +:SUB Rmr32,imm32 is vexMode=0 & opsize=1 & byte=0x81; mod=3 & Rmr32 & check_rm32_dest & reg_opcode=5; imm32 { subflags( Rmr32,imm32); Rmr32 = Rmr32 - imm32; build check_rm32_dest; resultflags( Rmr32); } +@ifdef IA64 +:SUB Rmr64,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x81; mod=3 & Rmr64 & reg_opcode=5; simm32 { subflags( Rmr64,simm32); Rmr64 = Rmr64 - simm32; resultflags( Rmr64); } +@endif +:SUB Rmr16,simm8_16 is vexMode=0 & opsize=0 & byte=0x83; mod=3 & Rmr16 & reg_opcode=5; simm8_16 { subflags( Rmr16,simm8_16); Rmr16 = Rmr16 - simm8_16; resultflags( Rmr16); } +:SUB Rmr32,simm8_32 is vexMode=0 & opsize=1 & byte=0x83; mod=3 & Rmr32 & check_rm32_dest & reg_opcode=5; simm8_32 { subflags( Rmr32,simm8_32); Rmr32 = Rmr32 - simm8_32; build check_rm32_dest; resultflags( Rmr32); } +@ifdef IA64 +:SUB Rmr64,simm8_64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x83; mod=3 & Rmr64 & reg_opcode=5; simm8_64 { subflags( Rmr64,simm8_64); Rmr64 = Rmr64 - simm8_64; resultflags( Rmr64); } +@endif +:SUB Rmr8,Reg8 is vexMode=0 & byte=0x28; mod=3 & Rmr8 & Reg8 { subflags( Rmr8,Reg8 ); Rmr8 = Rmr8 - Reg8; resultflags( Rmr8); } +:SUB Rmr16,Reg16 is vexMode=0 & opsize=0 & byte=0x29; mod=3 & Rmr16 & Reg16 { subflags( Rmr16,Reg16); Rmr16 = Rmr16 - Reg16; resultflags( Rmr16); } +:SUB Rmr32,Reg32 is vexMode=0 & opsize=1 & byte=0x29; mod=3 & Rmr32 & check_Rmr32_dest & Reg32 { subflags( Rmr32,Reg32); Rmr32 = Rmr32 - Reg32; build check_Rmr32_dest; resultflags( Rmr32); } +@ifdef IA64 +:SUB Rmr64,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x29; mod=3 & Rmr64 & Reg64 { subflags( Rmr64,Reg64); Rmr64 = Rmr64 - Reg64; resultflags( Rmr64); } +@endif +:SUB Reg8,rm8 is vexMode=0 & byte=0x2a; rm8 & Reg8 ... { subflags( Reg8,rm8 ); Reg8 = Reg8 - rm8; resultflags( Reg8); } +:SUB Reg16,rm16 is vexMode=0 & opsize=0 & byte=0x2b; rm16 & Reg16 ... { subflags(Reg16,rm16 ); Reg16 = Reg16 - rm16; resultflags(Reg16); } +:SUB Reg32,rm32 is vexMode=0 & opsize=1 & byte=0x2b; rm32 & Reg32 ... & check_Reg32_dest ... { subflags(Reg32,rm32 ); Reg32 = Reg32 - rm32; build check_Reg32_dest; resultflags(Reg32); } +@ifdef IA64 +:SUB Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x2b; rm64 & Reg64 ... { subflags(Reg64,rm64 ); Reg64 = Reg64 - rm64; resultflags(Reg64); } +@endif + +:SYSENTER is vexMode=0 & byte=0x0f; byte=0x34 { sysenter(); } +:SYSEXIT is vexMode=0 & byte=0x0f; byte=0x35 { sysexit(); +@ifdef IA64 + RIP=RCX; return [RIP]; +@endif + } + +:SYSCALL is vexMode=0 & byte=0x0f; byte=0x05 { + RCX = inst_next; + packflags(R11); + syscall(); +} + +# returning to 32bit mode loads ECX +# returning to 64bit mode loads RCX +:SYSRET is vexMode=0 & byte=0x0f; byte=0x07 { sysret(); +@ifdef IA64 + RIP=RCX; return [RIP]; +@endif + } + +:SWAPGS is vexMode=0 & bit64=1 & byte=0x0f; byte=0x01; byte=0xf8 { swapgs(); } + +:RDTSCP is vexMode=0 & bit64=1 & byte=0x0f; byte=0x01; byte=0xf9 { rdtscp(); } + +:TEST AL,imm8 is vexMode=0 & byte=0xA8; AL & imm8 { logicalflags(); local tmp = AL & imm8; resultflags(tmp); } +:TEST AX,imm16 is vexMode=0 & opsize=0; byte=0xA9; AX & imm16 { logicalflags(); local tmp = AX & imm16; resultflags(tmp); } +:TEST EAX,imm32 is vexMode=0 & opsize=1; byte=0xA9; EAX & imm32 { logicalflags(); local tmp = EAX & imm32; resultflags(tmp); } +@ifdef IA64 +:TEST RAX,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2; byte=0xA9; RAX & simm32 { logicalflags(); local tmp = RAX & simm32; resultflags(tmp); } +@endif +:TEST spec_rm8,imm8 is vexMode=0 & byte=0xF6; spec_rm8 & (reg_opcode=0 | reg_opcode=1) ... ; imm8 { logicalflags(); local tmp = spec_rm8 & imm8; resultflags(tmp); } +:TEST spec_rm16,imm16 is vexMode=0 & opsize=0; byte=0xF7; spec_rm16 & (reg_opcode=0 | reg_opcode=1) ... ; imm16 { logicalflags(); local tmp = spec_rm16 & imm16; resultflags(tmp); } +:TEST spec_rm32,imm32 is vexMode=0 & opsize=1; byte=0xF7; spec_rm32 & (reg_opcode=0 | reg_opcode=1) ... ; imm32 { logicalflags(); local tmp = spec_rm32 & imm32; resultflags(tmp); } +@ifdef IA64 +:TEST spec_rm64,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2; byte=0xF7; spec_rm64 & (reg_opcode=0 | reg_opcode=1) ... ; simm32 { logicalflags(); local tmp = spec_rm64 & simm32; resultflags(tmp); } +@endif +:TEST rm8,Reg8 is vexMode=0 & byte=0x84; rm8 & Reg8 ... { logicalflags(); local tmp = rm8 & Reg8; resultflags(tmp); } +:TEST rm16,Reg16 is vexMode=0 & opsize=0; byte=0x85; rm16 & Reg16 ... { logicalflags(); local tmp = rm16 & Reg16; resultflags(tmp); } +:TEST rm32,Reg32 is vexMode=0 & opsize=1; byte=0x85; rm32 & Reg32 ... { logicalflags(); local tmp = rm32 & Reg32; resultflags(tmp); } +@ifdef IA64 +:TEST rm64,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2; byte=0x85; rm64 & Reg64 ... { logicalflags(); local tmp = rm64 & Reg64; resultflags(tmp); } +@endif + +define pcodeop invalidInstructionException; +:UD0 Reg32, rm32 is vexMode=0 & byte=0x0f; byte=0xff; rm32 & Reg32 ... { invalidInstructionException(); goto inst_start; } +:UD1 Reg32, rm32 is vexMode=0 & byte=0x0f; byte=0xb9; rm32 & Reg32 ... { invalidInstructionException(); goto inst_start; } +:UD2 is vexMode=0 & byte=0xf; byte=0xb { invalidInstructionException(); goto inst_start; } + +define pcodeop verr; +define pcodeop verw; +:VERR rm16 is vexMode=0 & byte=0xf; byte=0x0; rm16 & reg_opcode=4 ... { ZF = verr(); } +:VERW rm16 is vexMode=0 & byte=0xf; byte=0x0; rm16 & reg_opcode=5 ... { ZF = verw(); } + +# MFL added VMX opcodes +# +# AMD hardware assisted virtualization opcodes +:VMLOAD EAX is vexMode=0 & addrsize=1 & byte=0x0f; byte=0x01; byte=0xda & EAX { vmload(EAX); } +@ifdef IA64 +:VMLOAD RAX is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0x0f; byte=0x01; byte=0xda & RAX { vmload(RAX); } +@endif +:VMMCALL is vexMode=0 & byte=0x0f; byte=0x01; byte=0xd9 { vmmcall(); } +# Limiting the effective address size to 32 and 64 bit. Surely we're not expecting a 16-bit VM address, are we? +:VMRUN EAX is vexMode=0 & addrsize=1 & byte=0x0f; byte=0x01; byte=0xd8 & EAX { vmrun(EAX); } +@ifdef IA64 +:VMRUN RAX is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0x0f; byte=0x01; byte=0xd8 & RAX { vmrun(RAX); } +@endif +# Limiting the effective address size to 32 and 64 bit. Surely we're not expecting a 16-bit VM address, are we? +:VMSAVE EAX is vexMode=0 & addrsize=1 & byte=0x0f; byte=0x01; byte=0xdb & EAX { vmsave(EAX); } +@ifdef IA64 +:VMSAVE RAX is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0x0f; byte=0x01; byte=0xdb & RAX { vmsave(RAX); } +@endif +# + +# +# Intel hardware assisted virtualization opcodes +@ifdef IA64 +:INVEPT Reg64, m128 is $(LONGMODE_ON) & vexMode=0 & bit64=1 & $(PRE_66) & byte=0x0f; byte=0x38; byte=0x80; Reg64 ... & m128 { invept(Reg64, m128); } +@endif +:INVEPT Reg32, m128 is vexMode=0 & bit64=0 & $(PRE_66) & byte=0x0f; byte=0x38; byte=0x80; Reg32 ... & m128 { invept(Reg32, m128); } +@ifdef IA64 +:INVVPID Reg64, m128 is $(LONGMODE_ON) & vexMode=0 & bit64=1 & $(PRE_66) & byte=0x0f; byte=0x38; byte=0x81; Reg64 ... & m128 { invvpid(Reg64, m128); } +@endif +:INVVPID Reg32, m128 is vexMode=0 & bit64=0 & $(PRE_66) & byte=0x0f; byte=0x38; byte=0x81; Reg32 ... & m128 { invvpid(Reg32, m128); } +:VMCALL is vexMode=0 & byte=0x0f; byte=0x01; byte=0xc1 { vmcall(); } +@ifdef IA64 +:VMCLEAR m64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & byte=0x0f; byte=0xc7; ( mod != 0b11 & reg_opcode=6 ) ... & m64 { vmclear(m64); } +@endif +#TODO: invokes a VM function specified in EAX +:VMFUNC EAX is vexMode=0 & byte=0x0f; byte=0x01; byte=0xd4 & EAX { vmfunc(EAX); } +#TODO: this launches the VM managed by the current VMCS. How is the VMCS expressed for the emulator? For Ghidra analysis? +:VMLAUNCH is vexMode=0 & byte=0x0f; byte=0x01; byte=0xc2 { vmlaunch(); } +#TODO: this resumes the VM managed by the current VMCS. How is the VMCS expressed for the emulator? For Ghidra analysis? +:VMRESUME is vexMode=0 & byte=0x0f; byte=0x01; byte=0xc3 { vmresume(); } +#TODO: this loads the VMCS pointer from the m64 memory address and makes the VMCS pointer valid; how to express +# this for analysis and emulation? +:VMPTRLD m64 is vexMode=0 & byte=0x0f; byte=0xc7; ( mod != 0b11 & reg_opcode=6 ) ... & m64 { vmptrld(m64); } +#TODO: stores the current VMCS pointer into the specified 64-bit memory address; how to express this for analysis and emulation? +#TODO: note that the Intel manual does not specify m64 (which it does for VMPTRLD, yet it does state that "the operand +# of this instruction is always 64-bits and is always in memory". Is it an error that the "Instruction" entry in the +# box giving the definition does not specify m64? +:VMPTRST m64 is vexMode=0 & byte=0x0f; byte=0xc7; ( mod != 0b11 & reg_opcode=7 ) ... & m64 { vmptrst(m64); } +:VMREAD rm32, Reg32 is vexMode=0 & opsize=1 & byte=0x0f; byte=0x78; rm32 & check_rm32_dest ... & Reg32 ... { rm32 = vmread(Reg32); build check_rm32_dest; } +@ifdef IA64 +:VMREAD rm64, Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x0f; byte=0x78; rm64 & Reg64 ... { rm64 = vmread(Reg64); } +@endif +:VMWRITE Reg32, rm32 is vexMode=0 & opsize=1 & byte=0x0f; byte=0x79; rm32 & Reg32 ... & check_Reg32_dest ... { vmwrite(rm32,Reg32); build check_Reg32_dest; } +@ifdef IA64 +:VMWRITE Reg64, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x0f; byte=0x79; rm64 & Reg64 ... { vmwrite(rm64,Reg64); } +@endif +:VMXOFF is vexMode=0 & byte=0x0f; byte=0x01; byte=0xc4 { vmxoff(); } +# NB: this opcode is incorrect in the 2005 edition of the Intel manual. Opcode below is taken from the 2008 version. +:VMXON m64 is vexMode=0 & $(PRE_F3) & byte=0x0f; byte=0xc7; ( mod != 0b11 & reg_opcode=6 ) ... & m64 { vmxon(m64); } + +#END of changes for VMX opcodes + +:WAIT is vexMode=0 & byte=0x9b { } +:WBINVD is vexMode=0 & byte=0xf; byte=0x9 { } + +@ifdef IA64 +define pcodeop writefsbase; +:WRFSBASE r32 is vexMode=0 & opsize=1 & $(PRE_F3) & byte=0x0f; byte=0xae; reg_opcode=2 & r32 { tmp:8 = zext(r32); writefsbase(tmp); } +:WRFSBASE r64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0f; byte=0xae; reg_opcode=2 & r64 { writefsbase(r64); } + +define pcodeop writegsbase; +:WRGSBASE r32 is vexMode=0 & opsize=1 & $(PRE_F3) & byte=0x0f; byte=0xae; reg_opcode=3 & r32 { tmp:8 = zext(r32); writegsbase(tmp); } +:WRGSBASE r64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0f; byte=0xae; reg_opcode=3 & r64 { writegsbase(r64); } +@endif + +define pcodeop wrpkru; +:WRPKRU is byte=0x0F; byte=0x01; byte=0xEF { wrpkru(EAX); } + +define pcodeop wrmsr; +:WRMSR is vexMode=0 & byte=0xf; byte=0x30 { tmp:8 = (zext(EDX) << 32) | zext(EAX); wrmsr(ECX,tmp); } + +# See 'lockable.sinc' for memory destination, lockable variants +:XADD Rmr8,Reg8 is vexMode=0 & byte=0x0F; byte=0xC0; mod=3 & Rmr8 & Reg8 { addflags( Rmr8,Reg8 ); local tmp = Rmr8 + Reg8; Reg8 = Rmr8; Rmr8 = tmp; resultflags(tmp); } +:XADD Rmr16,Reg16 is vexMode=0 & opsize=0 & byte=0x0F; byte=0xC1; mod=3 & Rmr16 & Reg16 { addflags(Rmr16,Reg16); local tmp = Rmr16 + Reg16; Reg16 = Rmr16; Rmr16 = tmp; resultflags(tmp); } +:XADD Rmr32,Reg32 is vexMode=0 & opsize=1 & byte=0x0F; byte=0xC1; mod=3 & Rmr32 & check_Rmr32_dest & Reg32 & check_Reg32_dest { addflags(Rmr32,Reg32); local tmp = Rmr32 + Reg32; Reg32 = Rmr32; Rmr32 = tmp; build check_Rmr32_dest; build check_Reg32_dest; resultflags(tmp); } +@ifdef IA64 +:XADD Rmr64,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x0F; byte=0xC1; mod=3 & Rmr64 & Reg64 { addflags(Rmr64,Reg64); local tmp = Rmr64 + Reg64; Reg64 = Rmr64; Rmr64 = tmp; resultflags(tmp); } +@endif + +define pcodeop xabort; + +:XABORT imm8 is vexMode=0 & byte=0xc6; byte=0xf8; imm8 { tmp:1 = imm8; xabort(tmp); } + +define pcodeop xbegin; +define pcodeop xend; + +:XBEGIN rel16 is vexMode=0 & opsize=0 & byte=0xc7; byte=0xf8; rel16 { xbegin(&:$(SIZE) rel16); } +:XBEGIN rel32 is vexMode=0 & (opsize=1 | opsize=2) & byte=0xc7; byte=0xf8; rel32 { xbegin(&:$(SIZE) rel32); } + +:XEND is vexMode=0 & byte=0x0f; byte=0x01; byte=0xd5 { xend(); } + +# See 'lockable.sinc' for memory destination, lockable variants +:XCHG AX,Rmr16 is vexMode=0 & opsize=0 & row = 9 & page = 0 & AX & Rmr16 { local tmp = AX; AX = Rmr16; Rmr16 = tmp; } +:XCHG EAX,Rmr32 is vexMode=0 & opsize=1 & row = 9 & page = 0 & EAX & check_EAX_dest & Rmr32 & check_Rmr32_dest { local tmp = EAX; EAX = Rmr32; build check_EAX_dest; Rmr32 = tmp; build check_Rmr32_dest; } +@ifdef IA64 +:XCHG RAX,Rmr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & row = 9 & page = 0 & RAX & Rmr64 { local tmp = RAX; RAX = Rmr64; Rmr64 = tmp; } +@endif + +:XCHG Rmr8,Reg8 is vexMode=0 & byte=0x86; mod=3 & Rmr8 & Reg8 { local tmp = Rmr8; Rmr8 = Reg8; Reg8 = tmp; } +:XCHG Rmr16,Reg16 is vexMode=0 & opsize=0 & byte=0x87; mod=3 & Rmr16 & Reg16 { local tmp = Rmr16; Rmr16 = Reg16; Reg16 = tmp; } +:XCHG Rmr32,Reg32 is vexMode=0 & opsize=1 & byte=0x87; mod=3 & Rmr32 & check_Rmr32_dest & Reg32 & check_Reg32_dest { local tmp = Rmr32; Rmr32 = Reg32; build check_Rmr32_dest; Reg32 = tmp; build check_Reg32_dest;} +@ifdef IA64 +:XCHG Rmr64,Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x87; mod=3 & Rmr64 & Reg64 { local tmp = Rmr64; Rmr64 = Reg64; Reg64 = tmp; } +@endif + +:XLAT seg16^BX is vexMode=0 & addrsize=0 & seg16 & byte=0xd7; BX { tmp:$(SIZE)= 0; ptr2(tmp,BX+zext(AL)); AL = *tmp; } +:XLAT segWide^EBX is vexMode=0 & addrsize=1 & segWide & byte=0xd7; EBX { tmp:$(SIZE)= 0; ptr4(tmp,EBX+zext(AL)); AL = *tmp; } +@ifdef IA64 +:XLAT segWide^RBX is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & segWide & byte=0xd7; RBX { tmp:$(SIZE)= 0; ptr8(tmp,RBX+zext(AL)); AL = *tmp; } +@endif + +# See 'lockable.sinc' for memory destination, lockable variants +:XOR AL,imm8 is vexMode=0 & byte=0x34; AL & imm8 { logicalflags(); AL = AL ^ imm8; resultflags( AL); } +:XOR AX,imm16 is vexMode=0 & opsize=0 & byte=0x35; AX & imm16 { logicalflags(); AX = AX ^ imm16; resultflags( AX); } +:XOR EAX,imm32 is vexMode=0 & opsize=1 & byte=0x35; EAX & imm32 & check_EAX_dest { logicalflags(); EAX = EAX ^ imm32; build check_EAX_dest; resultflags( EAX);} +@ifdef IA64 +:XOR RAX,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x35; RAX & simm32 { logicalflags(); RAX = RAX ^ simm32; resultflags( RAX); } +@endif +:XOR Rmr8,imm8 is vexMode=0 & $(BYTE_80_82); mod=3 & Rmr8 & reg_opcode=6; imm8 { logicalflags(); Rmr8 = Rmr8 ^ imm8; resultflags( Rmr8); } +:XOR Rmr16,imm16 is vexMode=0 & opsize=0 & byte=0x81; mod=3 & Rmr16 & reg_opcode=6; imm16 { logicalflags(); Rmr16 = Rmr16 ^ imm16; resultflags( Rmr16); } +:XOR Rmr32,imm32 is vexMode=0 & opsize=1 & byte=0x81; mod=3 & Rmr32 & check_rm32_dest & reg_opcode=6; imm32 { logicalflags(); Rmr32 = Rmr32 ^ imm32; build check_rm32_dest; resultflags( Rmr32); } +@ifdef IA64 +:XOR Rmr64,simm32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x81; mod=3 & Rmr64 & reg_opcode=6; simm32 { logicalflags(); Rmr64 = Rmr64 ^ simm32; resultflags( Rmr64); } +@endif +:XOR Rmr16,usimm8_16 is vexMode=0 & opsize=0 & byte=0x83; mod=3 & Rmr16 & reg_opcode=6; usimm8_16 { logicalflags(); Rmr16 = Rmr16 ^ usimm8_16; resultflags( Rmr16); } +:XOR Rmr32,usimm8_32 is vexMode=0 & opsize=1 & byte=0x83; mod=3 & Rmr32 & check_rm32_dest & reg_opcode=6; usimm8_32 { logicalflags(); Rmr32 = Rmr32 ^ usimm8_32; build check_rm32_dest; resultflags( Rmr32); } +@ifdef IA64 +:XOR Rmr64,usimm8_64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x83; mod=3 & Rmr64 & reg_opcode=6; usimm8_64 { logicalflags(); Rmr64 = Rmr64 ^ usimm8_64; resultflags( Rmr64); } +@endif +:XOR Rmr8,Reg8 is vexMode=0 & byte=0x30; mod=3 & Rmr8 & Reg8 { logicalflags(); Rmr8 = Rmr8 ^ Reg8; resultflags( Rmr8); } +:XOR Rmr16,Reg16 is vexMode=0 & opsize=0 & byte=0x31; mod=3 & Rmr16 & Reg16 { logicalflags(); Rmr16 = Rmr16 ^ Reg16; resultflags( Rmr16); } +:XOR Rmr32,Reg32 is vexMode=0 & opsize=1 & byte=0x31; mod=3 & Rmr32 & check_Rmr32_dest & Reg32 { logicalflags(); Rmr32 = Rmr32 ^ Reg32; build check_Rmr32_dest; resultflags( Rmr32); } +@ifdef IA64 +:XOR Rmr64,Reg64 is vexMode=0 & $(LONGMODE_ON) & opsize=2 & byte=0x31; mod=3 & Rmr64 & Reg64 { logicalflags(); Rmr64 = Rmr64 ^ Reg64; resultflags( Rmr64); } +@endif +:XOR Reg8,rm8 is vexMode=0 & byte=0x32; rm8 & Reg8 ... { logicalflags(); Reg8 = Reg8 ^ rm8; resultflags( Reg8); } +:XOR Reg16,rm16 is vexMode=0 & opsize=0 & byte=0x33; rm16 & Reg16 ... { logicalflags(); Reg16 = Reg16 ^ rm16; resultflags(Reg16); } +:XOR Reg32,rm32 is vexMode=0 & opsize=1 & byte=0x33; rm32 & Reg32 ... & check_Reg32_dest ... { logicalflags(); Reg32 = Reg32 ^ rm32; build check_Reg32_dest; resultflags(Reg32); } +@ifdef IA64 +:XOR Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x33; rm64 & Reg64 ... { logicalflags(); Reg64 = Reg64 ^ rm64; resultflags(Reg64); } +@endif + +:XGETBV is vexMode=0 & byte=0x0F; byte=0x01; byte=0xD0 { local tmp = XCR0 >> 32; EDX = tmp:4; EAX = XCR0:4; } +:XSETBV is vexMode=0 & byte=0x0F; byte=0x01; byte=0xD1 { XCR0 = (zext(EDX) << 32) | zext(EAX); } + +define pcodeop xsave; +define pcodeop xsave64; +define pcodeop xsavec; +define pcodeop xsavec64; +define pcodeop xsaveopt; +define pcodeop xsaveopt64; +define pcodeop xsaves; +define pcodeop xsaves64; +define pcodeop xrstor; +define pcodeop xrstor64; +define pcodeop xrstors; +define pcodeop xrstors64; + +:XRSTOR Mem is vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=5 ) ... & Mem { tmp:4 = 512; xrstor(Mem, tmp); } +@ifdef IA64 +:XRSTOR64 Mem is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=5 ) ... & Mem { tmp:4 = 512; xrstor64(Mem, tmp); } +@endif + +:XRSTORS Mem is vexMode=0 & byte=0x0F; byte=0xC7; ( mod != 0b11 & reg_opcode=3 ) ... & Mem { tmp:4 = 512; xrstors(Mem, tmp); } +@ifdef IA64 +:XRSTORS64 Mem is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0F; byte=0xC7; ( mod != 0b11 & reg_opcode=3 ) ... & Mem { tmp:4 = 512; xrstors64(Mem, tmp); } +@endif + +:XSAVE Mem is vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=4 ) ... & Mem { tmp:4 = 512; xsave(Mem, tmp); } +@ifdef IA64 +:XSAVE64 Mem is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=4 ) ... & Mem { tmp:4 = 512; xsave64(Mem, tmp); } +@endif + +:XSAVEC Mem is vexMode=0 & byte=0x0F; byte=0xC7; ( mod != 0b11 & reg_opcode=4 ) ... & Mem { tmp:4 = 512; xsavec(Mem, tmp); } +@ifdef IA64 +:XSAVEC64 Mem is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0F; byte=0xC7; ( mod != 0b11 & reg_opcode=4 ) ... & Mem { tmp:4 = 512; xsavec64(Mem, tmp); } +@endif + +:XSAVEOPT Mem is vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=6 ) ... & Mem { tmp:4 = 512; xsaveopt(Mem, tmp); } +@ifdef IA64 +:XSAVEOPT64 Mem is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=6 ) ... & Mem { tmp:4 = 512; xsaveopt64(Mem, tmp); } +@endif + +:XSAVES Mem is vexMode=0 & byte=0x0F; byte=0xC7; ( mod != 0b11 & reg_opcode=5 ) ... & Mem { tmp:4 = 512; xsaves(Mem, tmp); } +@ifdef IA64 +:XSAVES64 Mem is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0F; byte=0xC7; ( mod != 0b11 & reg_opcode=5 ) ... & Mem { tmp:4 = 512; xsaves64(Mem, tmp); } +@endif + +define pcodeop xtest; +:XTEST is byte=0x0F; byte=0x01; byte=0xD6 { ZF = xtest(); } + +:LFENCE is vexMode=0 & $(PRE_NO) & byte=0x0F; byte=0xAE; mod = 0b11 & reg_opcode=5 & r_m=0 { } +:MFENCE is vexMode=0 & $(PRE_NO) & byte=0x0F; byte=0xAE; mod = 0b11 & reg_opcode=6 & r_m=0 { } +:SFENCE is vexMode=0 & $(PRE_NO) & byte=0x0F; byte=0xAE; mod = 0b11 & reg_opcode=7 & r_m=0 { } + +# +# floating point instructions +# +define pcodeop f2xm1; +:F2XM1 is vexMode=0 & byte=0xD9; byte=0xF0 { ST0 = f2xm1(ST0); } # compute 2^x-1 + +:FABS is vexMode=0 & byte=0xD9; byte=0xE1 { ST0 = abs(ST0); } + +:FADD spec_m32 is vexMode=0 & byte=0xD8; reg_opcode=0 ... & spec_m32 { ST0 = ST0 f+ float2float(spec_m32); } +:FADD spec_m64 is vexMode=0 & byte=0xDC; reg_opcode=0 ... & spec_m64 { ST0 = ST0 f+ float2float(spec_m64); } +:FADD ST0, freg is vexMode=0 & byte=0xD8; frow=12 & fpage=0 & freg & ST0 { ST0 = ST0 f+ freg; } +:FADD freg, ST0 is vexMode=0 & byte=0xDC; frow=12 & fpage=0 & freg & ST0 { freg = freg f+ ST0; } +:FADDP is vexMode=0 & byte=0xDE; byte=0xC1 { ST1 = ST0 f+ ST1; fpop(); } +:FADDP freg, ST0 is vexMode=0 & byte=0xDE; frow=12 & fpage=0 & freg & ST0 { freg = ST0 f+ freg; fpop(); } +:FIADD spec_m32 is vexMode=0 & byte=0xDA; reg_opcode=0 ... & spec_m32 { ST0 = ST0 f+ int2float(spec_m32); } +:FIADD spec_m16 is vexMode=0 & byte=0xDE; reg_opcode=0 ... & spec_m16 { ST0 = ST0 f+ int2float(spec_m16); } + +define pcodeop convert_bcd; +:FBLD spec_m80 is vexMode=0 & byte=0xDF; reg_opcode=4 ... & spec_m80 { fdec(); ST0 = convert_bcd(spec_m80); } + +:FBSTP spec_m80 is vexMode=0 & byte=0xDF; reg_opcode=6 ... & spec_m80 { spec_m80 = convert_bcd(ST0); fpop(); } + +:FCHS is vexMode=0 & byte=0xD9; byte=0xE0 { ST0 = f- ST0; } + +:FCLEX is vexMode=0 & byte=0x9B; byte=0xDB; byte=0xE2 { FPUStatusWord[0,8] = 0; FPUStatusWord[15,1] = 0; } +:FNCLEX is vexMode=0 & byte=0xDB; byte=0xE2 { FPUStatusWord[0,8] = 0; FPUStatusWord[15,1] = 0; } + +:FCMOVB ST0, freg is vexMode=0 & byte=0xDA; frow=12 & fpage=0 & freg & ST0 { if ( !CF ) goto inst_next; ST0 = freg; } +:FCMOVE ST0, freg is vexMode=0 & byte=0xDA; frow=12 & fpage=1 & freg & ST0 { if ( !ZF ) goto inst_next; ST0 = freg; } +:FCMOVBE ST0, freg is vexMode=0 & byte=0xDA; frow=13 & fpage=0 & freg & ST0 { if ( !CF & !ZF ) goto inst_next; ST0 = freg; } +:FCMOVU ST0, freg is vexMode=0 & byte=0xDA; frow=13 & fpage=1 & freg & ST0 { if ( !PF ) goto inst_next; ST0 = freg; } +:FCMOVNB ST0, freg is vexMode=0 & byte=0xDB; frow=12 & fpage=0 & freg & ST0 { if ( CF ) goto inst_next; ST0 = freg; } +:FCMOVNE ST0, freg is vexMode=0 & byte=0xDB; frow=12 & fpage=1 & freg & ST0 { if ( ZF ) goto inst_next; ST0 = freg; } +:FCMOVNBE ST0, freg is vexMode=0 & byte=0xDB; frow=13 & fpage=0 & freg & ST0 { if ( CF & ZF ) goto inst_next; ST0 = freg; } +:FCMOVNU ST0, freg is vexMode=0 & byte=0xDB; frow=13 & fpage=1 & freg & ST0 { if ( PF ) goto inst_next; ST0 = freg; } + +:FCOM spec_m32 is vexMode=0 & byte=0xD8; reg_opcode=2 ... & spec_m32 { local tmp=float2float(spec_m32); fcom(tmp); } +:FCOM spec_m64 is vexMode=0 & byte=0xDC; reg_opcode=2 ... & spec_m64 { local tmp=float2float(spec_m64); fcom(tmp); } +:FCOM freg is vexMode=0 & byte=0xD8; frow=13 & fpage=0 & freg { fcom(freg); } +:FCOM is vexMode=0 & byte=0xD8; byte=0xD1 { fcom(ST1); } +:FCOMP spec_m32 is vexMode=0 & byte=0xD8; reg_opcode=3 ... & spec_m32 { local tmp=float2float(spec_m32); fcom(tmp); fpop(); } +:FCOMP spec_m64 is vexMode=0 & byte=0xDC; reg_opcode=3 ... & spec_m64 { local tmp=float2float(spec_m64); fcom(tmp); fpop(); } +:FCOMP freg is vexMode=0 & byte=0xD8; frow=13 & fpage=1 & freg { fcom(freg); fpop(); } +:FCOMP is vexMode=0 & byte=0xD8; byte=0xD9 { fcom(ST1); fpop(); } +:FCOMPP is vexMode=0 & byte=0xDE; byte=0xD9 { fcom(ST1); fpop(); fpop(); } + +:FCOMI ST0, freg is vexMode=0 & byte=0xDB; frow=15 & fpage=0 & freg & ST0 { fcomi(freg); } +:FCOMIP ST0, freg is vexMode=0 & byte=0xDF; frow=15 & fpage=0 & freg & ST0 { fcomi(freg); fpop(); } +:FUCOMI ST0, freg is vexMode=0 & byte=0xDB; frow=14 & fpage=1 & freg & ST0 { fcomi(freg); } +:FUCOMIP ST0, freg is vexMode=0 & byte=0xDF; frow=14 & fpage=1 & freg & ST0 { fcomi(freg); fpop(); } + +define pcodeop fcos; +:FCOS is vexMode=0 & byte=0xD9; byte=0xFF { ST0 = fcos(ST0); } + +:FDECSTP is vexMode=0 & byte=0xD9; byte=0xF6 { fdec(); FPUStatusWord = FPUStatusWord & 0xfeff; C0 = 0; } #Clear C0 + +# Legacy 8087 instructions. Still valid but treated as NOP instructions. +:FDISI is vexMode=0 & byte=0x9B; byte=0xDB; byte=0xE1 {} +:FNDISI is vexMode=0 & byte=0xDB; byte=0xE1 {} +:FENI is vexMode=0 & byte=0x9B; byte=0xDB; byte=0xE0 {} +:FNENI is vexMode=0 & byte=0xDB; byte=0xE0 {} + +:FDIV spec_m32 is vexMode=0 & byte=0xD8; reg_opcode=6 ... & spec_m32 { ST0 = ST0 f/ float2float(spec_m32); } +:FDIV spec_m64 is vexMode=0 & byte=0xDC; reg_opcode=6 ... & spec_m64 { ST0 = ST0 f/ float2float(spec_m64); } +:FDIV ST0,freg is vexMode=0 & byte=0xD8; frow=15 & fpage=0 & freg & ST0 { ST0 = ST0 f/ freg; } +:FDIV freg,ST0 is vexMode=0 & byte=0xDC; frow=15 & fpage=1 & freg & ST0 { freg = freg f/ ST0; } +:FDIVP freg,ST0 is vexMode=0 & byte=0xDE; frow=15 & fpage=1 & freg & ST0 { freg = ST0 f/ freg; fpop(); } +:FDIVP is vexMode=0 & byte=0xDE; byte=0xF9 { ST1 = ST1 f/ ST0; fpop(); } +:FIDIV spec_m32 is vexMode=0 & byte=0xDA; reg_opcode=6 ... & spec_m32 { ST0 = ST0 f/ int2float(spec_m32); } +:FIDIV spec_m16 is vexMode=0 & byte=0xDE; reg_opcode=6 ... & spec_m16 { ST0 = ST0 f/ int2float(spec_m16); } + +:FDIVR spec_m32 is vexMode=0 & byte=0xD8; reg_opcode=7 ... & spec_m32 { ST0 = float2float(spec_m32) f/ ST0; } +:FDIVR spec_m64 is vexMode=0 & byte=0xDC; reg_opcode=7 ... & spec_m64 { ST0 = float2float(spec_m64) f/ ST0; } +:FDIVR ST0,freg is vexMode=0 & byte=0xD8; frow=15 & fpage=1 & freg & ST0 { ST0 = freg f/ ST0; } +:FDIVR freg,ST0 is vexMode=0 & byte=0xDC; frow=15 & fpage=0 & freg & ST0 { freg = ST0 f/ freg; } +:FDIVRP freg,ST0 is vexMode=0 & byte=0xDE; frow=15 & fpage=0 & freg & ST0 { freg = freg f/ ST0; fpop(); } +:FDIVRP is vexMode=0 & byte=0xDE; byte=0xF1 { ST1 = ST0 f/ ST1; fpop(); } +:FIDIVR spec_m32 is vexMode=0 & byte=0xDA; reg_opcode=7 ... & spec_m32 { ST0 = int2float(spec_m32) f/ ST0; } +:FIDIVR spec_m16 is vexMode=0 & byte=0xDE; reg_opcode=7 ... & spec_m16 { ST0 = int2float(spec_m16) f/ ST0; } + +define pcodeop ffree; +:FFREE freg is vexMode=0 & byte=0xDD; frow=12 & fpage=0 & freg { FPUTagWord = ffree(freg); } # Set freg to invalid value +:FFREEP freg is vexMode=0 & byte=0xDF; frow=12 & fpage=0 & freg { FPUTagWord = ffree(freg); fpop(); } # FFREE and pop + +:FICOM spec_m16 is vexMode=0 & byte=0xDE; reg_opcode=2 ... & spec_m16 { local tmp = int2float(spec_m16); fcom(tmp); } +:FICOM spec_m32 is vexMode=0 & byte=0xDA; reg_opcode=2 ... & spec_m32 { local tmp = int2float(spec_m32); fcom(tmp); } +:FICOMP spec_m16 is vexMode=0 & byte=0xDE; (mod != 0b11 & reg_opcode=3) ... & spec_m16 { local tmp = int2float(spec_m16); fcom(tmp); fpop(); } +:FICOMP spec_m32 is vexMode=0 & byte=0xDA; reg_opcode=3 ... & spec_m32 { local tmp = int2float(spec_m32); fcom(tmp); fpop(); } + +:FILD spec_m16 is vexMode=0 & byte=0xDF; reg_opcode=0 ... & spec_m16 { fdec(); ST0 = int2float(spec_m16); } +:FILD spec_m32 is vexMode=0 & byte=0xDB; reg_opcode=0 ... & spec_m32 { fdec(); ST0 = int2float(spec_m32); } +:FILD spec_m64 is vexMode=0 & byte=0xDF; reg_opcode=5 ... & spec_m64 { fdec(); ST0 = int2float(spec_m64); } + +:FINCSTP is vexMode=0 & byte=0xD9; byte=0xF7 { finc(); } + +:FINIT is vexMode=0 & byte=0x9B; byte=0xDB; byte=0xE3 { + FPUControlWord = 0x037f; + FPUStatusWord = 0x0000; + FPUTagWord = 0xffff; + FPUDataPointer = 0x00000000; + FPUInstructionPointer = 0x00000000; + FPULastInstructionOpcode = 0x0000; + C0 = 0; + C1 = 0; + C2 = 0; + C3 = 0; } + +:FNINIT is vexMode=0 & byte=0xDB; byte=0xE3 { + FPUControlWord = 0x037f; + FPUStatusWord = 0x0000; + FPUTagWord = 0xffff; + FPUDataPointer = 0x00000000; + FPUInstructionPointer = 0x00000000; + FPULastInstructionOpcode = 0x0000; + C0 = 0; + C1 = 0; + C2 = 0; + C3 = 0; } + +:FIST spec_m16 is vexMode=0 & byte=0xDF; (mod != 0b11 & reg_opcode=2) ... & spec_m16 { tmp:10 = round(ST0); spec_m16 = trunc(tmp); } +:FIST spec_m32 is vexMode=0 & byte=0xDB; (mod != 0b11 & reg_opcode=2) ... & spec_m32 { tmp:10 = round(ST0); spec_m32 = trunc(tmp); } +:FISTP spec_m16 is vexMode=0 & byte=0xDF; reg_opcode=3 ... & spec_m16 { tmp:10 = round(ST0); fpop(); spec_m16 = trunc(tmp); } +:FISTP spec_m32 is vexMode=0 & byte=0xDB; reg_opcode=3 ... & spec_m32 { tmp:10 = round(ST0); fpop(); spec_m32 = trunc(tmp); } +:FISTP spec_m64 is vexMode=0 & byte=0xDF; reg_opcode=7 ... & spec_m64 { tmp:10 = round(ST0); fpop(); spec_m64 = trunc(tmp); } + +:FISTTP spec_m16 is vexMode=0 & byte=0xDF; reg_opcode=1 ... & spec_m16 { spec_m16 = trunc(ST0); fpop(); } +:FISTTP spec_m32 is vexMode=0 & byte=0xDB; reg_opcode=1 ... & spec_m32 { spec_m32 = trunc(ST0); fpop(); } +:FISTTP spec_m64 is vexMode=0 & byte=0xDD; reg_opcode=1 ... & spec_m64 { spec_m64 = trunc(ST0); fpop(); } + +:FLD spec_m32 is vexMode=0 & byte=0xD9; (mod != 0b11 & reg_opcode=0) ... & spec_m32 { fdec(); ST0 = float2float(spec_m32); } +:FLD spec_m64 is vexMode=0 & byte=0xDD; reg_opcode=0 ... & spec_m64 { fdec(); ST0 = float2float(spec_m64);} +:FLD spec_m80 is vexMode=0 & byte=0xDB; reg_opcode=5 ... & spec_m80 { fpushv(spec_m80); } + +# Be careful that you don't clobber freg during fpushv, need a tmp to hold the value +:FLD freg is vexMode=0 & byte=0xD9; frow=12 & fpage=0 & freg { tmp:10 = freg; fpushv(tmp); } + +:FLD1 is vexMode=0 & byte=0xD9; byte=0xE8 { one:4 = 1; tmp:10 = int2float(one); fpushv(tmp); } +:FLDL2T is vexMode=0 & byte=0xD9; byte=0xE9 { src:8 = 0x400a934f0979a371; tmp:10 = float2float(src); fpushv(tmp); } +:FLDL2E is vexMode=0 & byte=0xD9; byte=0xEA { src:8 = 0x3ff71547652b82fe; tmp:10 = float2float(src); fpushv(tmp); } +:FLDPI is vexMode=0 & byte=0xD9; byte=0xEB { src:8 = 0x400921fb54442d18; tmp:10 = float2float(src); fpushv(tmp); } +:FLDLG2 is vexMode=0 & byte=0xD9; byte=0xEC { src:8 = 0x3fd34413509f79ff; tmp:10 = float2float(src); fpushv(tmp); } +:FLDLN2 is vexMode=0 & byte=0xD9; byte=0xED { src:8 = 0x3fe62e42fefa39ef; tmp:10 = float2float(src); fpushv(tmp); } +:FLDZ is vexMode=0 & byte=0xD9; byte=0xEE { zero:4 = 0; tmp:10 = int2float(zero); fpushv(tmp); } + +:FLDCW m16 is vexMode=0 & byte=0xD9; (mod != 0b11 & reg_opcode=5) ... & m16 { FPUControlWord = m16; } + +define pcodeop fldenv; +:FLDENV Mem is vexMode=0 & byte=0xD9; (mod != 0b11 & reg_opcode=4) ... & Mem +{ + FPUControlWord = *:2 (Mem); + FPUStatusWord = *:2 (Mem + 4); + FPUTagWord = *:2 (Mem + 8); + FPUDataPointer = *:4 (Mem + 20); + FPUInstructionPointer = *:4 (Mem + 12); + FPULastInstructionOpcode = *:2 (Mem + 18); +} + +:FMUL spec_m32 is vexMode=0 & byte=0xD8; reg_opcode=1 ... & spec_m32 { ST0 = ST0 f* float2float(spec_m32); } +:FMUL spec_m64 is vexMode=0 & byte=0xDC; reg_opcode=1 ... & spec_m64 { ST0 = ST0 f* float2float(spec_m64); } +:FMUL freg is vexMode=0 & byte=0xD8; frow=12 & fpage=1 & freg { ST0 = ST0 f* freg; } +:FMUL freg is vexMode=0 & byte=0xDC; frow=12 & fpage=1 & freg { freg = freg f* ST0; } +:FMULP freg is vexMode=0 & byte=0xDE; frow=12 & fpage=1 & freg { freg = ST0 f* freg; fpop(); } +:FMULP is vexMode=0 & byte=0xDE; byte=0xC9 { ST1 = ST0 f* ST1; fpop(); } +:FIMUL spec_m32 is vexMode=0 & byte=0xDA; reg_opcode=1 ... & spec_m32 { ST0 = ST0 f* int2float(spec_m32); } +:FIMUL spec_m16 is vexMode=0 & byte=0xDE; reg_opcode=1 ... & spec_m16 { ST0 = ST0 f* int2float(spec_m16); } + +:FNOP is vexMode=0 & byte=0xD9; byte=0xD0 { } + +define pcodeop fpatan; +:FPATAN is vexMode=0 & byte=0xD9; byte=0xF3 { ST1 = fpatan(ST1, ST0); fpop(); } + +:FPREM is vexMode=0 & byte=0xD9; byte=0xF8 { local tmp = ST0 f/ ST1; tmp = tmp f* ST1; ST0 = ST0 f- tmp; } + +:FPREM1 is vexMode=0 & byte=0xD9; byte=0xF5 { local tmp = ST0 f/ ST1; tmp = tmp f* ST1; ST0 = ST0 f- tmp; } + +define pcodeop fptan; +:FPTAN is vexMode=0 & byte=0xD9; byte=0xF2 { ST0 = fptan(ST0); one:4 = 1; tmp:10 = int2float(one); fpushv(tmp); } + +:FRNDINT is vexMode=0 & byte=0xD9; byte=0xFC { local tmp = round(ST0); ST0 = tmp; } + +:FRSTOR Mem is vexMode=0 & byte=0xDD; reg_opcode=4 ... & Mem +{ + FPUControlWord = *:2 (Mem); + FPUStatusWord = *:2 (Mem + 4); + FPUTagWord = *:2 (Mem + 8); + FPUDataPointer = *:4 (Mem + 20); + FPUInstructionPointer = *:4 (Mem + 12); + FPULastInstructionOpcode = *:2 (Mem + 18); + + ST0 = *:10 (Mem + 28); + ST1 = *:10 (Mem + 38); + ST2 = *:10 (Mem + 48); + ST3 = *:10 (Mem + 58); + ST4 = *:10 (Mem + 68); + ST5 = *:10 (Mem + 78); + ST6 = *:10 (Mem + 88); + ST7 = *:10 (Mem + 98); +} + +:FSAVE Mem is vexMode=0 & byte=0x9B; byte=0xDD; reg_opcode=6 ... & Mem +{ + *:2 (Mem) = FPUControlWord; + *:2 (Mem + 4) = FPUStatusWord; + *:2 (Mem + 8) = FPUTagWord; + *:4 (Mem + 20) = FPUDataPointer; + *:4 (Mem + 12) = FPUInstructionPointer; + *:2 (Mem + 18) = FPULastInstructionOpcode; + + *:10 (Mem + 28) = ST0; + *:10 (Mem + 38) = ST1; + *:10 (Mem + 48) = ST2; + *:10 (Mem + 58) = ST3; + *:10 (Mem + 68) = ST4; + *:10 (Mem + 78) = ST5; + *:10 (Mem + 88) = ST6; + *:10 (Mem + 98) = ST7; + + FPUControlWord = 0x037f; + FPUStatusWord = 0x0000; + FPUTagWord = 0xffff; + FPUDataPointer = 0x00000000; + FPUInstructionPointer = 0x00000000; + FPULastInstructionOpcode = 0x0000; +} + +:FNSAVE Mem is vexMode=0 & byte=0xDD; reg_opcode=6 ... & Mem +{ + *:2 (Mem) = FPUControlWord; + *:2 (Mem + 4) = FPUStatusWord; + *:2 (Mem + 8) = FPUTagWord; + *:4 (Mem + 20) = FPUDataPointer; + *:4 (Mem + 12) = FPUInstructionPointer; + *:2 (Mem + 18) = FPULastInstructionOpcode; + + *:10 (Mem + 28) = ST0; + *:10 (Mem + 38) = ST1; + *:10 (Mem + 48) = ST2; + *:10 (Mem + 58) = ST3; + *:10 (Mem + 68) = ST4; + *:10 (Mem + 78) = ST5; + *:10 (Mem + 88) = ST6; + *:10 (Mem + 98) = ST7; + + FPUControlWord = 0x037f; + FPUStatusWord = 0x0000; + FPUTagWord = 0xffff; + FPUDataPointer = 0x00000000; + FPUInstructionPointer = 0x00000000; + FPULastInstructionOpcode = 0x0000; +} + +define pcodeop fscale; +:FSCALE is vexMode=0 & byte=0xD9; byte=0xFD { ST0 = fscale(ST0, ST1); } + +define pcodeop fsin; +:FSIN is vexMode=0 & byte=0xD9; byte=0xFE { ST0 = fsin(ST0); } +:FSINCOS is vexMode=0 & byte=0xD9; byte=0xFB { tmp:10 = fcos(ST0); ST0 = fsin(ST0); fpushv(tmp); } +:FSQRT is vexMode=0 & byte=0xD9; byte=0xFA { ST0 = sqrt(ST0); } + +:FST spec_m32 is vexMode=0 & byte=0xD9; (mod != 0b11 & reg_opcode=2) ... & spec_m32 { spec_m32 = float2float(ST0); } +:FST spec_m64 is vexMode=0 & byte=0xDD; reg_opcode=2 ... & spec_m64 { spec_m64 = float2float(ST0); } +:FST freg is vexMode=0 & byte=0xDD; frow=13 & fpage=0 & freg { freg = ST0; } +:FSTP spec_m32 is vexMode=0 & byte=0xD9; (mod != 0b11 & reg_opcode=3) ... & spec_m32 { spec_m32 = float2float(ST0); fpop(); } +:FSTP spec_m64 is vexMode=0 & byte=0xDD; reg_opcode=3 ... & spec_m64 { spec_m64 = float2float(ST0); fpop(); } +:FSTP spec_m80 is vexMode=0 & byte=0xDB; reg_opcode=7 ... & spec_m80 { fpopv(spec_m80); } +:FSTP freg is vexMode=0 & byte=0xDD; frow=13 & fpage=1 & freg { fpopv(freg); } + +:FSTCW m16 is vexMode=0 & byte=0x9B; byte=0xD9; (mod != 0b11 & reg_opcode=7) ... & m16 { m16 = FPUControlWord; } +:FNSTCW m16 is vexMode=0 & byte=0xD9; (mod != 0b11 & reg_opcode=7) ... & m16 { m16 = FPUControlWord; } + +:FSTENV Mem is vexMode=0 & byte=0x9B; byte=0xD9; (mod != 0b11 & reg_opcode=6) ... & Mem +{ + *:2 (Mem) = FPUControlWord; + *:2 (Mem + 4) = FPUStatusWord; + *:2 (Mem + 8) = FPUTagWord; + *:4 (Mem + 20) = FPUDataPointer; + *:4 (Mem + 12) = FPUInstructionPointer; + *:2 (Mem + 18) = FPULastInstructionOpcode; +} + +:FNSTENV Mem is vexMode=0 & byte=0xD9; (mod != 0b11 & reg_opcode=6) ... & Mem +{ + *:2 (Mem) = FPUControlWord; + *:2 (Mem + 4) = FPUStatusWord; + *:2 (Mem + 8) = FPUTagWord; + *:4 (Mem + 20) = FPUDataPointer; + *:4 (Mem + 12) = FPUInstructionPointer; + *:2 (Mem + 18) = FPULastInstructionOpcode; +} + +:FSTSW m16 is vexMode=0 & byte=0x9B; byte=0xDD; reg_opcode=7 ... & m16 { m16 = FPUStatusWord; } +:FSTSW AX is vexMode=0 & byte=0x9B; byte=0xDF; byte=0xE0 & AX { AX = FPUStatusWord; } +:FNSTSW m16 is vexMode=0 & byte=0xDD; reg_opcode=7 ... & m16 { m16 = FPUStatusWord; } +:FNSTSW AX is vexMode=0 & byte=0xDF; byte=0xE0 & AX { AX = FPUStatusWord; } + +:FSUB spec_m32 is vexMode=0 & byte=0xD8; reg_opcode=4 ... & spec_m32 { ST0 = ST0 f- float2float(spec_m32); } +:FSUB spec_m64 is vexMode=0 & byte=0xDC; reg_opcode=4 ... & spec_m64 { ST0 = ST0 f- float2float(spec_m64); } +:FSUB ST0,freg is vexMode=0 & byte=0xD8; frow=14 & fpage=0 & freg & ST0 { ST0 = ST0 f- freg; } +:FSUB freg,ST0 is vexMode=0 & byte=0xDC; frow=14 & fpage=1 & freg & ST0 { freg = freg f- ST0; } +:FSUBP is vexMode=0 & byte=0xDE; byte=0xE9 { ST1 = ST1 f- ST0; fpop(); } +:FSUBP freg,ST0 is vexMode=0 & byte=0xDE; frow=14 & fpage=1 & freg & ST0 { freg = freg f- ST0; fpop(); } +:FISUB spec_m32 is vexMode=0 & byte=0xDA; (mod != 0b11 & reg_opcode=4) ... & spec_m32 { ST0 = ST0 f- int2float(spec_m32); } +:FISUB spec_m16 is vexMode=0 & byte=0xDE; reg_opcode=4 ... & spec_m16 { ST0 = ST0 f- int2float(spec_m16); } + +:FSUBR spec_m32 is vexMode=0 & byte=0xD8; reg_opcode=5 ... & spec_m32 { ST0 = float2float(spec_m32) f- ST0; } +:FSUBR spec_m64 is vexMode=0 & byte=0xDC; reg_opcode=5 ... & spec_m64 { ST0 = float2float(spec_m64) f- ST0; } +:FSUBR ST0,freg is vexMode=0 & byte=0xD8; frow=14 & fpage=1 & freg & ST0 { ST0 = freg f- ST0; } +:FSUBR freg,ST0 is vexMode=0 & byte=0xDC; frow=14 & fpage=0 & freg & ST0 { freg = ST0 f- freg; } +:FSUBRP is vexMode=0 & byte=0xDE; byte=0xE1 { ST1 = ST0 f- ST1; fpop(); } +:FSUBRP freg,ST0 is vexMode=0 & byte=0xDE; frow=14 & fpage=0 & freg & ST0 { freg = ST0 f- freg; fpop(); } +:FISUBR spec_m32 is vexMode=0 & byte=0xDA; reg_opcode=5 ... & spec_m32 { ST0 = int2float(spec_m32) f- ST0; } +:FISUBR spec_m16 is vexMode=0 & byte=0xDE; reg_opcode=5 ... & spec_m16 { ST0 = int2float(spec_m16) f- ST0; } + +:FTST is vexMode=0 & byte=0xD9; byte=0xE4 { zero:4 = 0; tmp:10 = int2float(zero); fcom(tmp); } + +:FUCOM freg is vexMode=0 & byte=0xDD; frow=14 & fpage=0 & freg { fcom(freg); } +:FUCOM is vexMode=0 & byte=0xDD; byte=0xE1 { fcom(ST1); } +:FUCOMP freg is vexMode=0 & byte=0xDD; frow=14 & fpage=1 & freg { fcom(freg); fpop(); } +:FUCOMP is vexMode=0 & byte=0xDD; byte=0xE9 { fcom(ST1); fpop(); } +:FUCOMPP is vexMode=0 & byte=0xDA; byte=0xE9 { fcom(ST1); fpop(); fpop(); } + +:FXAM is vexMode=0 & byte=0xD9; byte=0xE5 +{ + # this is not an exact implementation, but gets the sign and zero tests right + izero:4 = 0; + fzero:10 = int2float(izero); + + # did not know how test for infinity or empty + C0 = nan(ST0); + + # sign of ST0 + C1 = ( ST0 f< fzero ); + + # assume normal if not zero + C2 = ( ST0 f!= fzero ); + + # equal to zero + C3 = ( ST0 f== fzero ); + + FPUStatusWord = (zext(C0)<<8) | (zext(C1)<<9) | (zext(C2)<<10) | (zext(C3)<<14); +} + +:FXCH freg is vexMode=0 & byte=0xD9; frow=12 & fpage=1 & freg { local tmp = ST0; ST0 = freg; freg = tmp; } +:FXCH is vexMode=0 & byte=0xD9; byte=0xC9 { local tmp = ST0; ST0 = ST1; ST1 = tmp; } + +@ifndef IA64 +# this saves the FPU state into 512 bytes of memory similar to the 32-bit mode +:FXSAVE Mem is vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=0 ) ... & Mem +{ +# not saved in the same spacing as the actual processor + *:2 (Mem) = FPUControlWord; + *:2 (Mem + 2) = FPUStatusWord; + *:2 (Mem + 4) = FPUTagWord; #The real implementation saves an 'abridged' tag word, but that is a non-trivial operation + *:2 (Mem + 6) = FPULastInstructionOpcode; + *:4 (Mem + 8) = FPUInstructionPointer; + *:2 (Mem + 12) = FPUPointerSelector; + *:4 (Mem + 16) = FPUDataPointer; + *:2 (Mem + 20) = FPUDataSelector; + *:4 (Mem + 24) = MXCSR; + # MXCSR_MASK not modeled, since it is processor specific, set to 0. + +# saved the FPU ST registers to the ST/MM area of the structure, + *:10 (Mem + 32) = ST0; + *:10 (Mem + 48) = ST1; + *:10 (Mem + 64) = ST2; + *:10 (Mem + 80) = ST3; + *:10 (Mem + 96) = ST4; + *:10 (Mem + 112) = ST5; + *:10 (Mem + 128) = ST6; + *:10 (Mem + 144) = ST7; + + *:16 (Mem + 160) = XMM0; + *:16 (Mem + 176) = XMM1; + *:16 (Mem + 192) = XMM2; + *:16 (Mem + 208) = XMM3; + *:16 (Mem + 224) = XMM4; + *:16 (Mem + 240) = XMM5; + *:16 (Mem + 256) = XMM6; + *:16 (Mem + 272) = XMM7; +} + +@else +# this saves the FPU state into 512 bytes of memory similar to the 32-bit mode +:FXSAVE Mem is vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=0 ) ... & Mem +{ + *:2 (Mem) = FPUControlWord; + *:2 (Mem + 2) = FPUStatusWord; + *:2 (Mem + 4) = FPUTagWord; #The real implementation saves an 'abridged' tag word, but that is a non-trivial operation + *:2 (Mem + 6) = FPULastInstructionOpcode; + *:4 (Mem + 8) = FPUInstructionPointer; + *:2 (Mem + 12) = FPUPointerSelector; + *:4 (Mem + 16) = FPUDataPointer; + *:2 (Mem + 20) = FPUDataSelector; + *:4 (Mem + 24) = MXCSR; + # MXCSR_MASK not modeled, since it is processor specific, set to 0. + + +# saved the FPU ST registers to the ST/MM area of the structure, + *:10 (Mem + 32) = ST0; + *:10 (Mem + 48) = ST1; + *:10 (Mem + 64) = ST2; + *:10 (Mem + 80) = ST3; + *:10 (Mem + 96) = ST4; + *:10 (Mem + 112) = ST5; + *:10 (Mem + 128) = ST6; + *:10 (Mem + 144) = ST7; + + *:16 (Mem + 160) = XMM0; + *:16 (Mem + 176) = XMM1; + *:16 (Mem + 192) = XMM2; + *:16 (Mem + 208) = XMM3; + *:16 (Mem + 224) = XMM4; + *:16 (Mem + 240) = XMM5; + *:16 (Mem + 256) = XMM6; + *:16 (Mem + 272) = XMM7; + *:16 (Mem + 288) = XMM8; + *:16 (Mem + 304) = XMM9; + *:16 (Mem + 320) = XMM10; + *:16 (Mem + 336) = XMM11; + *:16 (Mem + 352) = XMM12; + *:16 (Mem + 368) = XMM13; + *:16 (Mem + 384) = XMM14; + *:16 (Mem + 400) = XMM15; +} + +# this saves the FPU state into 512 bytes of memory similar to the 32-bit mode +:FXSAVE64 Mem is vexMode=0 & $(REX_W) & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=0 ) ... & Mem +{ + *:2 (Mem) = FPUControlWord; + *:2 (Mem + 2) = FPUStatusWord; + *:2 (Mem + 4) = FPUTagWord; #The real implementation saves an 'abridged' tag word, but that is a non-trivial operation + *:2 (Mem + 6) = FPULastInstructionOpcode; + *:8 (Mem + 8) = FPUInstructionPointer; + *:8 (Mem + 16) = FPUDataPointer; + *:4 (Mem + 24) = MXCSR; + # MXCSR_MASK not modeled, since it is processor specific, set to 0. + +# saved the FPU ST registers to the ST/MM area of the structure, + *:10 (Mem + 32) = ST0; + *:10 (Mem + 48) = ST1; + *:10 (Mem + 64) = ST2; + *:10 (Mem + 80) = ST3; + *:10 (Mem + 96) = ST4; + *:10 (Mem + 112) = ST5; + *:10 (Mem + 128) = ST6; + *:10 (Mem + 144) = ST7; + + + *:16 (Mem + 160) = XMM0; + *:16 (Mem + 176) = XMM1; + *:16 (Mem + 192) = XMM2; + *:16 (Mem + 208) = XMM3; + *:16 (Mem + 224) = XMM4; + *:16 (Mem + 240) = XMM5; + *:16 (Mem + 256) = XMM6; + *:16 (Mem + 272) = XMM7; + *:16 (Mem + 288) = XMM8; + *:16 (Mem + 304) = XMM9; + *:16 (Mem + 320) = XMM10; + *:16 (Mem + 336) = XMM11; + *:16 (Mem + 352) = XMM12; + *:16 (Mem + 368) = XMM13; + *:16 (Mem + 384) = XMM14; + *:16 (Mem + 400) = XMM15; +} +@endif + +@ifndef IA64 +:FXRSTOR Mem is vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=1 ) ... & Mem +{ + FPUControlWord = *:2 (Mem); + FPUStatusWord = *:2 (Mem + 2); + FPUTagWord = *:2 (Mem + 4); #The real implementation saves an 'abridged' tag word, but that is a non-trivial operation + FPULastInstructionOpcode = *:2 (Mem + 6); + FPUInstructionPointer = *:4 (Mem + 8); + FPUPointerSelector = *:2 (Mem + 12); + FPUDataPointer = *:4 (Mem + 16); + FPUDataSelector = *:2 (Mem + 20); + MXCSR = *:4 (Mem + 24); + # MXCSR_MASK not modeled, since it is processor specific, set to 0. + +# saved the FPU ST registers to the ST/MM area of the structure, + ST0 = *:10 (Mem + 32); + ST1 = *:10 (Mem + 48); + ST2 = *:10 (Mem + 64); + ST3 = *:10 (Mem + 80); + ST4 = *:10 (Mem + 96); + ST5 = *:10 (Mem + 112); + ST6 = *:10 (Mem + 128); + ST7 = *:10 (Mem + 144); + + XMM0 = *:16 (Mem + 160); + XMM1 = *:16 (Mem + 176); + XMM2 = *:16 (Mem + 192); + XMM3 = *:16 (Mem + 208); + XMM4 = *:16 (Mem + 224); + XMM5 = *:16 (Mem + 240); + XMM6 = *:16 (Mem + 256); + XMM7 = *:16 (Mem + 272); +} + +@else +:FXRSTOR64 Mem is vexMode=0 & $(REX_W) & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=1 ) ... & Mem +{ + FPUControlWord = *:2 (Mem); + FPUStatusWord = *:2 (Mem + 2); + FPUTagWord = *:2 (Mem + 4); #The real implementation saves an 'abridged' tag word, but that is a non-trivial operation + FPULastInstructionOpcode = *:2 (Mem + 6); + FPUInstructionPointer = *:8 (Mem + 8); + FPUDataPointer = *:8 (Mem + 16); + MXCSR = *:4 (Mem + 24); + # MXCSR_MASK not modeled, since it is processor specific, set to 0. + +# saved the FPU ST registers to the ST/MM area of the structure, + ST0 = *:10 (Mem + 32); + ST1 = *:10 (Mem + 48); + ST2 = *:10 (Mem + 64); + ST3 = *:10 (Mem + 80); + ST4 = *:10 (Mem + 96); + ST5 = *:10 (Mem + 112); + ST6 = *:10 (Mem + 128); + ST7 = *:10 (Mem + 144); + + XMM0 = *:16 (Mem + 160); + XMM1 = *:16 (Mem + 176); + XMM2 = *:16 (Mem + 192); + XMM3 = *:16 (Mem + 208); + XMM4 = *:16 (Mem + 224); + XMM5 = *:16 (Mem + 240); + XMM6 = *:16 (Mem + 256); + XMM7 = *:16 (Mem + 272); + XMM8 = *:16 (Mem + 288); + XMM9 = *:16 (Mem + 304); + XMM10 = *:16 (Mem + 320); + XMM11 = *:16 (Mem + 336); + XMM12 = *:16 (Mem + 352); + XMM13 = *:16 (Mem + 368); + XMM14 = *:16 (Mem + 384); + XMM15 = *:16 (Mem + 400); +} + +:FXRSTOR Mem is vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=1 ) ... & Mem +{ + FPUControlWord = *:2 (Mem); + FPUStatusWord = *:2 (Mem + 2); + FPUTagWord = *:2 (Mem + 4); #The real implementation saves an 'abridged' tag word, but that is a non-trivial operation + FPULastInstructionOpcode = *:2 (Mem + 6); + FPUInstructionPointer = *:4 (Mem + 8); + FPUPointerSelector = *:2 (Mem + 12); + FPUDataPointer = *:4 (Mem + 16); + FPUDataSelector = *:2 (Mem + 20); + MXCSR = *:4 (Mem + 24); + # MXCSR_MASK not modeled, since it is processor specific, set to 0. + +# saved the FPU ST registers to the ST/MM area of the structure, + ST0 = *:10 (Mem + 32); + ST1 = *:10 (Mem + 48); + ST2 = *:10 (Mem + 64); + ST3 = *:10 (Mem + 80); + ST4 = *:10 (Mem + 96); + ST5 = *:10 (Mem + 112); + ST6 = *:10 (Mem + 128); + ST7 = *:10 (Mem + 144); + + + XMM0 = *:16 (Mem + 160); + XMM1 = *:16 (Mem + 176); + XMM2 = *:16 (Mem + 192); + XMM3 = *:16 (Mem + 208); + XMM4 = *:16 (Mem + 224); + XMM5 = *:16 (Mem + 240); + XMM6 = *:16 (Mem + 256); + XMM7 = *:16 (Mem + 272); + XMM8 = *:16 (Mem + 288); + XMM9 = *:16 (Mem + 304); + XMM10 = *:16 (Mem + 320); + XMM11 = *:16 (Mem + 336); + XMM12 = *:16 (Mem + 352); + XMM13 = *:16 (Mem + 368); + XMM14 = *:16 (Mem + 384); + XMM15 = *:16 (Mem + 400); +} +@endif + +:FXTRACT is vexMode=0 & byte=0xD9; byte=0xF4 { significand:10 = ST0; exponent:10 = ST0; ST0 = exponent; fpushv(significand); } + +:FYL2X is vexMode=0 & byte=0xD9; byte=0xF1 { local log2st0 = ST0; ST1 = ST1 f* log2st0; fpop(); } +:FYL2XP1 is vexMode=0 & byte=0xD9; byte=0xF9 { one:4 = 1; tmp:10 = int2float(one); log2st0:10 = ST0 f+ tmp; ST1 = ST1 f* log2st0; fpop(); } + + +# +# MMX instructions +# + +:ADDPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x58; XmmReg ... & m128 +{ + XmmReg[0,64] = XmmReg[0,64] f+ m128[0,64]; + XmmReg[64,64] = XmmReg[64,64] f+ m128[64,64]; +} + +:ADDPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x58; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,64] = XmmReg1[0,64] f+ XmmReg2[0,64]; + XmmReg1[64,64] = XmmReg1[64,64] f+ XmmReg2[64,64]; +} + +:ADDPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x58; m128 & XmmReg ... +{ + local m:16 = m128; # Guarantee value is in a fixed location + XmmReg[0,32] = XmmReg[0,32] f+ m[0,32]; + XmmReg[32,32] = XmmReg[32,32] f+ m[32,32]; + XmmReg[64,32] = XmmReg[64,32] f+ m[64,32]; + XmmReg[96,32] = XmmReg[96,32] f+ m[96,32]; +} + +:ADDPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x58; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = XmmReg1[0,32] f+ XmmReg2[0,32]; + XmmReg1[32,32] = XmmReg1[32,32] f+ XmmReg2[32,32]; + XmmReg1[64,32] = XmmReg1[64,32] f+ XmmReg2[64,32]; + XmmReg1[96,32] = XmmReg1[96,32] f+ XmmReg2[96,32]; +} + +:ADDSD XmmReg, m64 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x58; m64 & XmmReg ... +{ + XmmReg[0,64] = XmmReg[0,64] f+ m64; +} + +:ADDSD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x58; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,64] = XmmReg1[0,64] f+ XmmReg2[0,64]; +} + +:ADDSS XmmReg, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x58; m32 & XmmReg ... +{ + XmmReg[0,32] = XmmReg[0,32] f+ m32; +} + +:ADDSS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x58; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = XmmReg1[0,32] f+ XmmReg2[0,32]; +} + +:ADDSUBPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD0; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,64] = XmmReg[0,64] f- m[0,64]; + XmmReg[64,64] = XmmReg[64,64] f+ m[64,64]; +} + +:ADDSUBPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD0; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,64] = XmmReg1[0,64] f- XmmReg2[0,64]; + XmmReg1[64,64] = XmmReg1[64,64] f+ XmmReg2[64,64]; +} + +:ADDSUBPS XmmReg, m128 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0xD0; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,32] = XmmReg[0,32] f- m[0,32]; + XmmReg[32,32] = XmmReg[32,32] f+ m[32,32]; + XmmReg[64,32] = XmmReg[64,32] f- m[64,32]; + XmmReg[96,32] = XmmReg[96,32] f+ m[96,32]; +} + +:ADDSUBPS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0xD0; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = XmmReg1[0,32] f- XmmReg2[0,32]; + XmmReg1[32,32] = XmmReg1[32,32] f+ XmmReg2[32,32]; + XmmReg1[64,32] = XmmReg1[64,32] f- XmmReg2[64,32]; + XmmReg1[96,32] = XmmReg1[96,32] f+ XmmReg2[96,32]; +} + +# special FLOATING POINT bitwise AND +:ANDPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x54; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,64] = XmmReg[0,64] & m[0,64]; + XmmReg[64,64] = XmmReg[64,64] & m[64,64]; +} + +# special FLOATING POINT bitwise AND +:ANDPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x54; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,64] = XmmReg1[0,64] & XmmReg2[0,64]; + XmmReg1[64,64] = XmmReg1[64,64] & XmmReg2[64,64]; +} + +# special FLOATING POINT bitwise AND +:ANDPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x54; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,32] = XmmReg[0,32] & m[0,32]; + XmmReg[32,32] = XmmReg[32,32] & m[32,32]; + XmmReg[64,32] = XmmReg[64,32] & m[64,32]; + XmmReg[96,32] = XmmReg[96,32] & m[96,32]; +} + +# special FLOATING POINT bitwise AND +:ANDPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x54; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = XmmReg1[0,32] & XmmReg2[0,32]; + XmmReg1[32,32] = XmmReg1[32,32] & XmmReg2[32,32]; + XmmReg1[64,32] = XmmReg1[64,32] & XmmReg2[64,32]; + XmmReg1[96,32] = XmmReg1[96,32] & XmmReg2[96,32]; +} + +# special FLOATING POINT bitwise AND NOT +:ANDNPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x55; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,64] = ~XmmReg[0,64] & m[0,64]; + XmmReg[64,64] = ~XmmReg[64,64] & m[64,64]; +} + +:ANDNPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x55; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,64] = ~XmmReg1[0,64] & XmmReg2[0,64]; + XmmReg1[64,64] = ~XmmReg1[64,64] & XmmReg2[64,64]; +} + +# special FLOATING POINT bitwise AND NOT +:ANDNPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x55; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,32] = ~XmmReg[0,32] & m[0,32]; + XmmReg[32,32] = ~XmmReg[32,32] & m[32,32]; + XmmReg[64,32] = ~XmmReg[64,32] & m[64,32]; + XmmReg[96,32] = ~XmmReg[96,32] & m[96,32]; +} + +:ANDNPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x55; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = ~XmmReg1[0,32] & XmmReg2[0,32]; + XmmReg1[32,32] = ~XmmReg1[32,32] & XmmReg2[32,32]; + XmmReg1[64,32] = ~XmmReg1[64,32] & XmmReg2[64,32]; + XmmReg1[96,32] = ~XmmReg1[96,32] & XmmReg2[96,32]; +} + +# predicate mnemonics for "CMP...PD" opcode +XmmCondPD: "EQ" is imm8=0 { + xmmTmp1_Qa = zext( xmmTmp1_Qa f== xmmTmp2_Qa ) * 0xFFFFFFFFFFFFFFFF; + xmmTmp1_Qb = zext( xmmTmp1_Qb f== xmmTmp2_Qb ) * 0xFFFFFFFFFFFFFFFF; +} + +XmmCondPD: "LT" is imm8=1 { + xmmTmp1_Qa = zext( xmmTmp1_Qa f< xmmTmp2_Qa ) * 0xFFFFFFFFFFFFFFFF; + xmmTmp1_Qb = zext( xmmTmp1_Qb f< xmmTmp2_Qb ) * 0xFFFFFFFFFFFFFFFF; +} + +XmmCondPD: "LE" is imm8=2 { + xmmTmp1_Qa = zext( xmmTmp1_Qa f<= xmmTmp2_Qa ) * 0xFFFFFFFFFFFFFFFF; + xmmTmp1_Qb = zext( xmmTmp1_Qb f<= xmmTmp2_Qb ) * 0xFFFFFFFFFFFFFFFF; +} + +XmmCondPD: "UNORD" is imm8=3 { + xmmTmp1_Qa = zext( nan(xmmTmp1_Qa) || nan(xmmTmp2_Qa) ) * 0xFFFFFFFFFFFFFFFF; + xmmTmp1_Qb = zext( nan(xmmTmp1_Qb) || nan(xmmTmp2_Qb) ) * 0xFFFFFFFFFFFFFFFF; +} + +XmmCondPD: "NEQ" is imm8=4 { + xmmTmp1_Qa = zext( xmmTmp1_Qa f!= xmmTmp2_Qa ) * 0xFFFFFFFFFFFFFFFF; + xmmTmp1_Qb = zext( xmmTmp1_Qb f!= xmmTmp2_Qb ) * 0xFFFFFFFFFFFFFFFF; +} + +XmmCondPD: "NLT" is imm8=5 { + xmmTmp1_Qa = zext( !(xmmTmp1_Qa f< xmmTmp2_Qa) ) * 0xFFFFFFFFFFFFFFFF; + xmmTmp1_Qb = zext( !(xmmTmp1_Qb f< xmmTmp2_Qb) ) * 0xFFFFFFFFFFFFFFFF; +} + +XmmCondPD: "NLE" is imm8=6 { + xmmTmp1_Qa = zext( !(xmmTmp1_Qa f<= xmmTmp2_Qa) ) * 0xFFFFFFFFFFFFFFFF; + xmmTmp1_Qb = zext( !(xmmTmp1_Qb f<= xmmTmp2_Qb) ) * 0xFFFFFFFFFFFFFFFF; +} + +XmmCondPD: "ORD" is imm8=7 { + xmmTmp1_Qa = zext( !(nan(xmmTmp1_Qa) || nan(xmmTmp2_Qa)) ) * 0xFFFFFFFFFFFFFFFF; + xmmTmp1_Qb = zext( !(nan(xmmTmp1_Qb) || nan(xmmTmp2_Qb)) ) * 0xFFFFFFFFFFFFFFFF; +} + +define pcodeop cmppd; +XmmCondPD: is imm8 { + xmmTmp1_Qa = cmppd(xmmTmp1_Qa, xmmTmp2_Qa, imm8:1); + xmmTmp1_Qb = cmppd(xmmTmp1_Qb, xmmTmp2_Qb, imm8:1); +} + +# immediate operand for "CMP...PD" opcode +# note: normally blank, "imm8" emits for all out of range cases +CMPPD_OPERAND: is imm8<8 { } +CMPPD_OPERAND: ", "^imm8 is imm8 { } + +:CMP^XmmCondPD^"PD" XmmReg,m128^CMPPD_OPERAND is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xC2; (m128 & XmmReg ...); XmmCondPD & CMPPD_OPERAND +{ + local m:16 = m128; + xmmTmp1_Qa = XmmReg[0,64]; + xmmTmp1_Qb = XmmReg[64,64]; + + xmmTmp2_Qa = m[0,64]; + xmmTmp2_Qb = m[64,64]; + + build XmmCondPD; + + XmmReg[0,64] = xmmTmp1_Qa; + XmmReg[64,64] = xmmTmp1_Qb; +} + +:CMP^XmmCondPD^"PD" XmmReg1,XmmReg2^CMPPD_OPERAND is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xC2; xmmmod=3 & XmmReg1 & XmmReg2; XmmCondPD & CMPPD_OPERAND +{ + xmmTmp1_Qa = XmmReg1[0,64]; + xmmTmp1_Qb = XmmReg1[64,64]; + + xmmTmp2_Qa = XmmReg2[0,64]; + xmmTmp2_Qb = XmmReg2[64,64]; + + build XmmCondPD; + + XmmReg1[0,64] = xmmTmp1_Qa; + XmmReg1[64,64] = xmmTmp1_Qb; +} + + +# predicate mnemonics for "CMP...PS" opcode +XmmCondPS: "EQ" is imm8=0 { + xmmTmp1_Da = zext( xmmTmp1_Da f== xmmTmp2_Da ) * 0xFFFFFFFF; + xmmTmp1_Db = zext( xmmTmp1_Db f== xmmTmp2_Db ) * 0xFFFFFFFF; + xmmTmp1_Dc = zext( xmmTmp1_Dc f== xmmTmp2_Dc ) * 0xFFFFFFFF; + xmmTmp1_Dd = zext( xmmTmp1_Dd f== xmmTmp2_Dd ) * 0xFFFFFFFF; +} + +XmmCondPS: "LT" is imm8=1 { + xmmTmp1_Da = zext( xmmTmp1_Da f< xmmTmp2_Da ) * 0xFFFFFFFF; + xmmTmp1_Db = zext( xmmTmp1_Db f< xmmTmp2_Db ) * 0xFFFFFFFF; + xmmTmp1_Dc = zext( xmmTmp1_Dc f< xmmTmp2_Dc ) * 0xFFFFFFFF; + xmmTmp1_Dd = zext( xmmTmp1_Dd f< xmmTmp2_Dd ) * 0xFFFFFFFF; +} + +XmmCondPS: "LE" is imm8=2 { + xmmTmp1_Da = zext( xmmTmp1_Da f<= xmmTmp2_Da ) * 0xFFFFFFFF; + xmmTmp1_Db = zext( xmmTmp1_Db f<= xmmTmp2_Db ) * 0xFFFFFFFF; + xmmTmp1_Dc = zext( xmmTmp1_Dc f<= xmmTmp2_Dc ) * 0xFFFFFFFF; + xmmTmp1_Dd = zext( xmmTmp1_Dd f<= xmmTmp2_Dd ) * 0xFFFFFFFF; +} + +XmmCondPS: "UNORD" is imm8=3 { + xmmTmp1_Da = zext( nan(xmmTmp1_Da) || nan(xmmTmp2_Da) ) * 0xFFFFFFFF; + xmmTmp1_Db = zext( nan(xmmTmp1_Db) || nan(xmmTmp2_Db) ) * 0xFFFFFFFF; + xmmTmp1_Dc = zext( nan(xmmTmp1_Dc) || nan(xmmTmp2_Dc) ) * 0xFFFFFFFF; + xmmTmp1_Dd = zext( nan(xmmTmp1_Dd) || nan(xmmTmp2_Dd) ) * 0xFFFFFFFF; +} + +XmmCondPS: "NEQ" is imm8=4 { + xmmTmp1_Da = zext( xmmTmp1_Da f!= xmmTmp2_Da ) * 0xFFFFFFFF; + xmmTmp1_Db = zext( xmmTmp1_Db f!= xmmTmp2_Db ) * 0xFFFFFFFF; + xmmTmp1_Dc = zext( xmmTmp1_Dc f!= xmmTmp2_Dc ) * 0xFFFFFFFF; + xmmTmp1_Dd = zext( xmmTmp1_Dd f!= xmmTmp2_Dd ) * 0xFFFFFFFF; +} + +XmmCondPS: "NLT" is imm8=5 { + xmmTmp1_Da = zext( !(xmmTmp1_Da f< xmmTmp2_Da) ) * 0xFFFFFFFF; + xmmTmp1_Db = zext( !(xmmTmp1_Db f< xmmTmp2_Db) ) * 0xFFFFFFFF; + xmmTmp1_Dc = zext( !(xmmTmp1_Dc f< xmmTmp2_Dc) ) * 0xFFFFFFFF; + xmmTmp1_Dd = zext( !(xmmTmp1_Dd f< xmmTmp2_Dd) ) * 0xFFFFFFFF; +} + +XmmCondPS: "NLE" is imm8=6 { + xmmTmp1_Da = zext( !(xmmTmp1_Da f<= xmmTmp2_Da) ) * 0xFFFFFFFF; + xmmTmp1_Db = zext( !(xmmTmp1_Db f<= xmmTmp2_Db) ) * 0xFFFFFFFF; + xmmTmp1_Dc = zext( !(xmmTmp1_Dc f<= xmmTmp2_Dc) ) * 0xFFFFFFFF; + xmmTmp1_Dd = zext( !(xmmTmp1_Dd f<= xmmTmp2_Dd) ) * 0xFFFFFFFF; +} + +XmmCondPS: "ORD" is imm8=7 { + xmmTmp1_Da = zext( !(nan(xmmTmp1_Da) || nan(xmmTmp2_Da)) ) * 0xFFFFFFFF; + xmmTmp1_Db = zext( !(nan(xmmTmp1_Db) || nan(xmmTmp2_Db)) ) * 0xFFFFFFFF; + xmmTmp1_Dc = zext( !(nan(xmmTmp1_Dc) || nan(xmmTmp2_Dc)) ) * 0xFFFFFFFF; + xmmTmp1_Dd = zext( !(nan(xmmTmp1_Dd) || nan(xmmTmp2_Dd)) ) * 0xFFFFFFFF; +} + +define pcodeop cmpps; +XmmCondPS: is imm8 { + xmmTmp1_Da = cmpps(xmmTmp1_Da, xmmTmp2_Da, imm8:1); + xmmTmp1_Db = cmpps(xmmTmp1_Db, xmmTmp2_Db, imm8:1); + xmmTmp1_Dc = cmpps(xmmTmp1_Dc, xmmTmp2_Dc, imm8:1); + xmmTmp1_Dd = cmpps(xmmTmp1_Dd, xmmTmp2_Dd, imm8:1); +} + +# immediate operand for "CMP...PS" opcode +# note: normally blank, "imm8" emits for all out of range cases +CMPPS_OPERAND: is imm8<8 { } +CMPPS_OPERAND: ", "^imm8 is imm8 { } + +:CMP^XmmCondPS^"PS" XmmReg,m128^CMPPS_OPERAND is vexMode=0 & mandover=0 & byte=0x0F; byte=0xC2; (m128 & XmmReg ...); XmmCondPS & CMPPS_OPERAND +{ + local m:16 = m128; + xmmTmp1_Da = XmmReg[0,32]; + xmmTmp1_Db = XmmReg[32,32]; + xmmTmp1_Dc = XmmReg[64,32]; + xmmTmp1_Dd = XmmReg[96,32]; + + xmmTmp2_Da = m[0,32]; + xmmTmp2_Db = m[32,32]; + xmmTmp2_Dc = m[64,32]; + xmmTmp2_Dd = m[96,32]; + + build XmmCondPS; + + XmmReg[0,32] = xmmTmp1_Da; + XmmReg[32,32] = xmmTmp1_Db; + XmmReg[64,32] = xmmTmp1_Dc; + XmmReg[96,32] = xmmTmp1_Dd; +} + +:CMP^XmmCondPS^"PS" XmmReg1,XmmReg2^CMPPS_OPERAND is vexMode=0 & mandover=0 & byte=0x0F; byte=0xC2; xmmmod=3 & XmmReg1 & XmmReg2; XmmCondPS & CMPPS_OPERAND +{ + xmmTmp1_Da = XmmReg1[0,32]; + xmmTmp1_Db = XmmReg1[32,32]; + xmmTmp1_Dc = XmmReg1[64,32]; + xmmTmp1_Dd = XmmReg1[96,32]; + + xmmTmp2_Da = XmmReg2[0,32]; + xmmTmp2_Db = XmmReg2[32,32]; + xmmTmp2_Dc = XmmReg2[64,32]; + xmmTmp2_Dc = XmmReg2[96,32]; + + build XmmCondPS; + + XmmReg1[0,32] = xmmTmp1_Da; + XmmReg1[32,32] = xmmTmp1_Db; + XmmReg1[64,32] = xmmTmp1_Dc; + XmmReg1[96,32] = xmmTmp1_Dd; +} + + +# predicate mnemonics for "CMP...SD" opcode +XmmCondSD: "EQ" is imm8=0 { + xmmTmp1_Qa = zext( xmmTmp1_Qa f== xmmTmp2_Qa ) * 0xFFFFFFFFFFFFFFFF; +} + +XmmCondSD: "LT" is imm8=1 { + xmmTmp1_Qa = zext( xmmTmp1_Qa f< xmmTmp2_Qa ) * 0xFFFFFFFFFFFFFFFF; +} + +XmmCondSD: "LE" is imm8=2 { + xmmTmp1_Qa = zext( xmmTmp1_Qa f<= xmmTmp2_Qa ) * 0xFFFFFFFFFFFFFFFF; +} + +XmmCondSD: "UNORD" is imm8=3 { + xmmTmp1_Qa = zext( nan(xmmTmp1_Qa) || nan(xmmTmp2_Qa) ) * 0xFFFFFFFFFFFFFFFF; +} + +XmmCondSD: "NEQ" is imm8=4 { + xmmTmp1_Qa = zext( xmmTmp1_Qa f!= xmmTmp2_Qa ) * 0xFFFFFFFFFFFFFFFF; +} + +XmmCondSD: "NLT" is imm8=5 { + xmmTmp1_Qa = zext( !(xmmTmp1_Qa f< xmmTmp2_Qa) ) * 0xFFFFFFFFFFFFFFFF; +} + +XmmCondSD: "NLE" is imm8=6 { + xmmTmp1_Qa = zext( !(xmmTmp1_Qa f<= xmmTmp2_Qa) ) * 0xFFFFFFFFFFFFFFFF; +} + +XmmCondSD: "ORD" is imm8=7 { + xmmTmp1_Qa = zext( !(nan(xmmTmp1_Qa) || nan(xmmTmp2_Qa)) ) * 0xFFFFFFFFFFFFFFFF; +} + + +define pcodeop cmpsd; +XmmCondSD: is imm8 { + xmmTmp1_Qa = cmpsd(xmmTmp1_Qa, xmmTmp2_Qa, imm8:1); +} + +# immediate operand for "CMP...SD" opcode +# note: normally blank, "imm8" emits for all out of range cases +CMPSD_OPERAND: is imm8<8 { } +CMPSD_OPERAND: ", "^imm8 is imm8 { } + +:CMP^XmmCondSD^"SD" XmmReg, m64^CMPSD_OPERAND is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0xC2; (m64 & XmmReg ...); XmmCondSD & CMPSD_OPERAND +{ + xmmTmp1_Qa = XmmReg[0,64]; + xmmTmp2_Qa = m64; + build XmmCondSD; + XmmReg[0,64] = xmmTmp1_Qa; +} + +:CMP^XmmCondSD^"SD" XmmReg1, XmmReg2^CMPSD_OPERAND is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0xC2; xmmmod=3 & XmmReg1 & XmmReg2; XmmCondSD & CMPSD_OPERAND +{ + xmmTmp1_Qa = XmmReg1[0,64]; + xmmTmp2_Qa = XmmReg2[0,64]; + build XmmCondSD; + XmmReg1[0,64] = xmmTmp1_Qa; +} + + +# predicate mnemonics for "CMP...SS" opcode +XmmCondSS: "EQ" is imm8=0 { + xmmTmp1_Da = zext( xmmTmp1_Da f== xmmTmp2_Da ) * 0xFFFFFFFF; +} + +XmmCondSS: "LT" is imm8=1 { + xmmTmp1_Da = zext( xmmTmp1_Da f< xmmTmp2_Da ) * 0xFFFFFFFF; +} + +XmmCondSS: "LE" is imm8=2 { + xmmTmp1_Da = zext( xmmTmp1_Da f<= xmmTmp2_Da ) * 0xFFFFFFFF; +} + +XmmCondSS: "UNORD" is imm8=3 { + xmmTmp1_Da = zext( nan(xmmTmp1_Da) || nan(xmmTmp2_Da) ) * 0xFFFFFFFF; +} + +XmmCondSS: "NEQ" is imm8=4 { + xmmTmp1_Da = zext( xmmTmp1_Da f!= xmmTmp2_Da ) * 0xFFFFFFFF; +} + +XmmCondSS: "NLT" is imm8=5 { + xmmTmp1_Da = zext( !(xmmTmp1_Da f< xmmTmp2_Da) ) * 0xFFFFFFFF; +} + +XmmCondSS: "NLE" is imm8=6 { + xmmTmp1_Da = zext( !(xmmTmp1_Da f<= xmmTmp2_Da) ) * 0xFFFFFFFF; +} + +XmmCondSS: "ORD" is imm8=7 { + xmmTmp1_Da = zext( !(nan(xmmTmp1_Da) || nan(xmmTmp2_Da)) ) * 0xFFFFFFFF; +} + + +define pcodeop cmpss; +XmmCondSS: is imm8 { + xmmTmp1_Da = cmpss(xmmTmp1_Da, xmmTmp2_Da, imm8:1); +} + +# immediate operand for "CMP...SS" opcode +# note: normally blank, "imm8" emits for all out of range cases +CMPSS_OPERAND: is imm8<8 { } +CMPSS_OPERAND: ", "^imm8 is imm8 { } + +:CMP^XmmCondSS^"SS" XmmReg, m32^CMPSS_OPERAND is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xC2; (m32 & XmmReg ...); XmmCondSS & CMPSS_OPERAND +{ + xmmTmp1_Da = XmmReg[0,32]; + xmmTmp2_Da = m32; + build XmmCondSS; + XmmReg[0,32] = xmmTmp1_Da; +} + +:CMP^XmmCondSS^"SS" XmmReg1, XmmReg2^CMPSS_OPERAND is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xC2; xmmmod=3 & XmmReg1 & XmmReg2; XmmCondSS & CMPSS_OPERAND +{ + xmmTmp1_Da = XmmReg1[0,32]; + xmmTmp2_Da = XmmReg2[0,32]; + build XmmCondSS; + XmmReg1[0,32] = xmmTmp1_Da; +} + + +:COMISD XmmReg, m64 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x2F; m64 & XmmReg ... +{ + fucompe(XmmReg[0,64], m64); +} + +:COMISD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x2F; xmmmod=3 & XmmReg1 & XmmReg2 +{ + fucompe(XmmReg1[0,64], XmmReg2[0,64]); +} + +:COMISS XmmReg, m32 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x2F; m32 & XmmReg ... +{ + fucompe(XmmReg[0,32], m32); +} + +:COMISS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x2F; xmmmod=3 & XmmReg1 & XmmReg2 +{ + fucompe(XmmReg1[0,32], XmmReg2[0,32]); +} + +:CVTDQ2PD XmmReg, m64 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xE6; m64 & XmmReg ... +{ + local m:8 = m64; + XmmReg[0,64] = int2float( m[0,32] ); + XmmReg[64,64] = int2float( m[32,32] ); +} + +:CVTDQ2PD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xE6; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,64] = int2float( XmmReg2[0,32] ); + XmmReg1[64,64] = int2float( XmmReg2[32,32] ); +} + +:CVTDQ2PS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x5B; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,32] = int2float( m[0,32] ); + XmmReg[32,32] = int2float( m[32,32] ); + XmmReg[64,32] = int2float( m[64,32] ); + XmmReg[96,32] = int2float( m[96,32] ); +} + +:CVTDQ2PS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x5B; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = int2float( XmmReg2[0,32] ); + XmmReg1[32,32] = int2float( XmmReg2[32,32] ); + XmmReg1[64,32] = int2float( XmmReg2[64,32] ); + XmmReg1[96,32] = int2float( XmmReg2[96,32] ); +} + +:CVTPD2DQ XmmReg, m128 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0xE6; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,32] = trunc( m[0,64] ); + XmmReg[32,32] = trunc( m[64,64] ); + XmmReg[64,32] = 0; + XmmReg[96,32] = 0; +} + +:CVTPD2DQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0xE6; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = trunc( XmmReg2[0,64] ); + XmmReg1[32,32] = trunc( XmmReg2[64,64] ); + XmmReg1[64,32] = 0; + XmmReg1[96,32] = 0; +} + +:CVTPD2PI mmxreg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x2D; mmxreg ... & m128 +{ + local m:16 = m128; + mmxreg[0,32] = trunc( m[0,64] ); + mmxreg[32,32] = trunc( m[64,64] ); +} + +:CVTPD2PI mmxreg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x2D; xmmmod=3 & mmxreg1 & XmmReg2 +{ + mmxreg1[0,32] = trunc( XmmReg2[0,64] ); + mmxreg1[32,32] = trunc( XmmReg2[64,64] ); +} + +:CVTPD2PS XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5A; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,32] = float2float( m[0,64] ); + XmmReg[32,32] = float2float( m[64,64] ); + XmmReg[64,32] = 0; + XmmReg[96,32] = 0; +} + +:CVTPD2PS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5A; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = float2float( XmmReg2[0,64] ); + XmmReg1[32,32] = float2float( XmmReg2[64,64] ); + XmmReg1[64,32] = 0; + XmmReg1[96,32] = 0; +} + +:CVTPI2PD XmmReg, m64 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x2A; m64 & XmmReg ... +{ + local m:8 = m64; + XmmReg[0,64] = int2float(m[0,32]); + XmmReg[64,64] = int2float(m[32,32]); +} + +:CVTPI2PD XmmReg1, mmxreg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x2A; xmmmod=3 & XmmReg1 & mmxreg2 +{ + XmmReg1[0,64] = int2float(mmxreg2[0,32]); + XmmReg1[64,64] = int2float(mmxreg2[32,32]); +} + +:CVTPI2PS XmmReg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x2A; m64 & XmmReg ... +{ + local m:8 = m64; + XmmReg[0,32] = int2float(m[0,32]); + XmmReg[32,32] = int2float(m[32,32]); +} + +:CVTPI2PS XmmReg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x2A; xmmmod=3 & XmmReg1 & mmxreg2 +{ + XmmReg1[0,32] = int2float(mmxreg2[0,32]); + XmmReg1[32,32] = int2float(mmxreg2[32,32]); +} + +:CVTPS2DQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5B; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,32] = trunc( m[0,32] ); + XmmReg[32,32] = trunc( m[32,32] ); + XmmReg[64,32] = trunc( m[64,32] ); + XmmReg[96,32] = trunc( m[96,32] ); +} + +:CVTPS2DQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5B; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = trunc( XmmReg2[0,32] ); + XmmReg1[32,32] = trunc( XmmReg2[32,32] ); + XmmReg1[64,32] = trunc( XmmReg2[64,32] ); + XmmReg1[96,32] = trunc( XmmReg2[96,32] ); +} + +:CVTPS2PD XmmReg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x5A; m64 & XmmReg ... +{ + local m:8 = m64; + XmmReg[0,64] = float2float( m[0,32] ); + XmmReg[64,64] = float2float( m[32,32] ); +} + +:CVTPS2PD XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x5A; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,64] = float2float( XmmReg2[0,32] ); + XmmReg1[64,64] = float2float( XmmReg2[32,32] ); +} + +:CVTPS2PI mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x2D; mmxreg ... & m64 +{ + local m:8 = m64; + mmxreg[0,32] = round(m[0,32]); + mmxreg[32,32] = round(m[32,32]); + FPUTagWord = 0x0000; +} + +:CVTPS2PI mmxreg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x2D; xmmmod=3 & mmxreg1 & XmmReg2 +{ + mmxreg1[0,32] = round(XmmReg2[0,32]); + mmxreg1[32,32] = round(XmmReg2[32,32]); + FPUTagWord = 0x0000; +} + +:CVTSD2SI Reg32, m64 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x2D; Reg32 ... & m64 +{ + Reg32 = trunc(round(m64)); +} + +:CVTSD2SI Reg32, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x2D; xmmmod=3 & Reg32 & XmmReg2 +{ + Reg32 = trunc(round(XmmReg2[0,64])); +} + +@ifdef IA64 +:CVTSD2SI Reg64, m64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F2) & byte=0x0F; byte=0x2D; Reg64 ... & m64 +{ + Reg64 = round(m64); +} + +:CVTSD2SI Reg64, XmmReg2 is vexMode=0 & opsize=2 & $(PRE_F2) & byte=0x0F; byte=0x2D; xmmmod=3 & Reg64 & XmmReg2 +{ + Reg64 = round(XmmReg2[0,64]); +} +@endif + +:CVTSD2SS XmmReg, m64 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x5A; m64 & XmmReg ... +{ + XmmReg[0,32] = float2float(m64); +} + +:CVTSD2SS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x5A; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = float2float(XmmReg2[0,64]); +} + +:CVTSI2SD XmmReg, rm32 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x2A; rm32 & XmmReg ... +{ + XmmReg[0,64] = int2float(rm32); +} + +@ifdef IA64 +:CVTSI2SD XmmReg, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F2) & byte=0x0F; byte=0x2A; rm64 & XmmReg ... +{ + XmmReg[0,64] = int2float(rm64); +} +@endif + +:CVTSI2SS XmmReg, rm32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x2A; rm32 & XmmReg ... +{ + XmmReg[0,32] = int2float(rm32); +} + +@ifdef IA64 +:CVTSI2SS XmmReg, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0F; byte=0x2A; rm64 & XmmReg ... +{ + XmmReg[0,32] = int2float(rm64); +} +@endif + +:CVTSS2SD XmmReg, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x5A; m32 & XmmReg ... +{ + XmmReg[0,64] = float2float(m32); +} + +:CVTSS2SD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x5A; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,64] = float2float(XmmReg2[0,32]); +} + +:CVTSS2SI Reg32, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x2D; Reg32 ... & m32 +{ + Reg32 = round(m32); +} + +:CVTSS2SI Reg32, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x2D; xmmmod=3 & Reg32 & XmmReg2 +{ + Reg32 = round(XmmReg2[0,32]); +} + +@ifdef IA64 +:CVTSS2SI Reg64, m32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0F; byte=0x2D; Reg64 ... & m32 +{ + Reg64 = trunc(round(m32)); +} + +:CVTSS2SI Reg64, XmmReg2 is vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0F; byte=0x2D; xmmmod=3 & Reg64 & XmmReg2 +{ + Reg64 = trunc(round(XmmReg2[0,32])); +} +@endif + +:CVTTPD2PI mmxreg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x2C; mmxreg ... & m128 +{ + local m:16 = m128; + mmxreg[0,32] = trunc(m[0,64]); + mmxreg[32,32] = trunc(m[64,64]); + FPUTagWord = 0x0000; +} + +:CVTTPD2PI mmxreg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x2C; xmmmod=3 & mmxreg1 & XmmReg2 +{ + mmxreg1[0,32] = trunc(XmmReg2[0,64]); + mmxreg1[32,32] = trunc(XmmReg2[64,64]); + FPUTagWord = 0x0000; +} + +:CVTTPD2DQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE6; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,32] = trunc(m[0,64]); + XmmReg[32,32] = trunc(m[64,64]); + XmmReg[64,32] = 0; + XmmReg[96,32] = 0; +} + +:CVTTPD2DQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE6; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = trunc(XmmReg2[0,64]); + XmmReg1[32,32] = trunc(XmmReg2[64,64]); + XmmReg1[64,32] = 0; + XmmReg1[96,32] = 0; +} + +:CVTTPS2DQ XmmReg, m128 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x5B; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,32] = trunc(m[0,32]); + XmmReg[32,32] = trunc(m[32,32]); + XmmReg[64,32] = trunc(m[64,32]); + XmmReg[96,32] = trunc(m[96,32]); +} + +:CVTTPS2DQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x5B; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = trunc(XmmReg2[0,32]); + XmmReg1[32,32] = trunc(XmmReg2[32,32]); + XmmReg1[64,32] = trunc(XmmReg2[64,32]); + XmmReg1[96,32] = trunc(XmmReg2[96,32]); +} + +:CVTTPS2PI mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x2C; mmxreg ... & m64 +{ + local m:8 = m64; + mmxreg[0,32] = trunc(m[0,32]); + mmxreg[32,32] = trunc(m[32,32]); + FPUTagWord = 0x0000; +} + +:CVTTPS2PI mmxreg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x2C; xmmmod=3 & mmxreg1 & XmmReg2 +{ + mmxreg1[0,32] = trunc(XmmReg2[0,32]); + mmxreg1[32,32] = trunc(XmmReg2[32,32]); + FPUTagWord = 0x0000; +} + +:CVTTSD2SI Reg32, m64 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x2C; Reg32 ... & check_Reg32_dest ... & m64 +{ + Reg32 = trunc(m64); + build check_Reg32_dest; +} + +:CVTTSD2SI Reg32, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x2C; xmmmod=3 & Reg32 & check_Reg32_dest & XmmReg2 +{ + Reg32 = trunc(XmmReg2[0,64]); + build check_Reg32_dest; +} + +@ifdef IA64 +:CVTTSD2SI Reg64, m64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F2) & byte=0x0F; byte=0x2C; Reg64 ... & m64 +{ + Reg64 = trunc(m64); +} + +:CVTTSD2SI Reg64, XmmReg2 is vexMode=0 & opsize=2 & $(PRE_F2) & byte=0x0F; byte=0x2C; xmmmod=3 & Reg64 & XmmReg2 +{ + Reg64 = trunc(XmmReg2[0,64]); +} +@endif + +:CVTTSS2SI Reg32, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x2C; Reg32 ... & check_Reg32_dest ... & m32 +{ + Reg32 = trunc(m32); + build check_Reg32_dest; +} + +:CVTTSS2SI Reg32, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x2C; xmmmod=3 & Reg32 & check_Reg32_dest & XmmReg2 +{ + Reg32 = trunc(XmmReg2[0,32]); + build check_Reg32_dest; +} + +@ifdef IA64 +:CVTTSS2SI Reg64, m32 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0F; byte=0x2C; Reg64 ... & m32 +{ + Reg64 = trunc(m32); +} + +:CVTTSS2SI Reg64, XmmReg2 is vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0F; byte=0x2C; xmmmod=3 & Reg64 & XmmReg2 +{ + Reg64 = trunc(XmmReg2[0,32]); +} +@endif + +define pcodeop divpd; +:DIVPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5E; XmmReg ... & m128 { XmmReg = divpd(XmmReg, m128); } +:DIVPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5E; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = divpd(XmmReg1, XmmReg2); } + +define pcodeop divps; +:DIVPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x5E; XmmReg ... & m128 { XmmReg = divps(XmmReg, m128); } +:DIVPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x5E; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = divps(XmmReg1, XmmReg2); } + +:DIVSD XmmReg, m64 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x5E; m64 & XmmReg ... +{ + XmmReg[0,64] = XmmReg[0,64] f/ m64; +} + +:DIVSD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x5E; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,64] = XmmReg1[0,64] f/ XmmReg2[0,64]; +} + +:DIVSS XmmReg, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x5E; m32 & XmmReg ... +{ + XmmReg[0,32] = XmmReg[0,32] f/ m32; +} + +:DIVSS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x5E; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = XmmReg1[0,32] f/ XmmReg2[0,32]; +} + +:EMMS is vexMode=0 & byte=0x0F; byte=0x77 { FPUTagWord = 0xFFFF; } + +:HADDPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x7C; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,64] = XmmReg[0,64] f+ XmmReg[64,64]; + XmmReg[64,64] = m[0,64] f+ m[64,64]; +} + +:HADDPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x7C; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,64] = XmmReg1[0,64] f+ XmmReg1[64,64]; + XmmReg1[64,64] = XmmReg2[0,64] f+ XmmReg2[64,64]; +} + +:HADDPS XmmReg, m128 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x7C; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,32] = XmmReg[0,32] f+ XmmReg[32,32]; + XmmReg[32,32] = XmmReg[64,32] f+ XmmReg[96,32]; + XmmReg[64,32] = m[0,32] f+ m[32,32]; + XmmReg[96,32] = m[64,32] f+ m[96,32]; +} + +:HADDPS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x7C; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = XmmReg1[0,32] f+ XmmReg1[32,32]; + XmmReg1[32,32] = XmmReg1[64,32] f+ XmmReg1[96,32]; + XmmReg1[64,32] = XmmReg2[0,32] f+ XmmReg2[32,32]; + XmmReg1[96,32] = XmmReg2[64,32] f+ XmmReg2[96,32]; +} + +:HSUBPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x7D; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,64] = XmmReg[0,64] f- XmmReg[64,64]; + XmmReg[64,64] = m[0,64] f- m[64,64]; +} + +:HSUBPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x7D; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,64] = XmmReg1[0,64] f- XmmReg1[64,64]; + XmmReg1[64,64] = XmmReg2[0,64] f- XmmReg2[64,64]; +} + +:HSUBPS XmmReg, m128 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x7D; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,32] = XmmReg[0,32] f- XmmReg[32,32]; + XmmReg[32,32] = XmmReg[64,32] f- XmmReg[96,32]; + XmmReg[64,32] = m[0,32] f- m[32,32]; + XmmReg[96,32] = m[64,32] f- m[96,32]; +} + +:HSUBPS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x7D; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = XmmReg1[0,32] f- XmmReg1[32,32]; + XmmReg1[32,32] = XmmReg1[64,32] f- XmmReg1[96,32]; + XmmReg1[64,32] = XmmReg2[0,32] f- XmmReg2[32,32]; + XmmReg1[96,32] = XmmReg2[64,32] f- XmmReg2[96,32]; +} + +#-------------------- +#SSE3... +#-------------------- + +define pcodeop lddqu; +:LDDQU XmmReg, m128 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0xF0; XmmReg ... & m128 { XmmReg = lddqu(XmmReg, m128); } + +define pcodeop maskmovdqu; +:MASKMOVDQU XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF7; XmmReg1 & XmmReg2 { XmmReg1 = maskmovdqu(XmmReg1, XmmReg2); } + +define pcodeop maxpd; +:MAXPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5F; XmmReg ... & m128 { XmmReg = maxpd(XmmReg, m128); } +:MAXPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5F; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = maxpd(XmmReg1, XmmReg2); } + +define pcodeop maxps; +:MAXPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x5F; XmmReg ... & m128 { XmmReg = maxps(XmmReg, m128); } +:MAXPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x5F; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = maxps(XmmReg1, XmmReg2); } + +:MAXSD XmmReg, m64 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x5F; XmmReg ... & m64 +{ + local tmp:8 = m64; + if (tmp f< XmmReg[0,64]) goto inst_next; + XmmReg[0,64] = tmp; +} + +:MAXSD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x5F; xmmmod=3 & XmmReg1 & XmmReg2 +{ + if (XmmReg2[0,64] f< XmmReg1[0,64]) goto inst_next; + XmmReg1[0,64] = XmmReg2[0,64]; +} + +:MAXSS XmmReg, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x5F; XmmReg ... & m32 +{ + local tmp:4 = m32; + if (tmp f< XmmReg[0,32]) goto inst_next; + XmmReg[0,32] = tmp; +} + +:MAXSS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x5F; xmmmod=3 & XmmReg1 & XmmReg2 +{ + if (XmmReg2[0,32] f< XmmReg1[0,32]) goto inst_next; + XmmReg1[0,32] = XmmReg2[0,32]; +} + +define pcodeop minpd; +:MINPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5D; XmmReg ... & m128 { XmmReg = minpd(XmmReg, m128); } +:MINPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5D; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = minpd(XmmReg1, XmmReg2); } + +define pcodeop minps; +:MINPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x5D; XmmReg ... & m128 { XmmReg = minps(XmmReg, m128); } +:MINPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x5D; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = minps(XmmReg1, XmmReg2); } + +:MINSD XmmReg, m64 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x5D; XmmReg ... & m64 +{ + local tmp:8 = m64; + if (XmmReg[0,64] f< tmp) goto inst_next; + XmmReg[0,64] = tmp; +} + +:MINSD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x5D; xmmmod=3 & XmmReg1 & XmmReg2 +{ + if (XmmReg1[0,64] f< XmmReg2[0,64]) goto inst_next; + XmmReg1[0,64] = XmmReg2[0,64]; +} + +:MINSS XmmReg, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x5D; XmmReg ... & m32 +{ + local tmp:4 = m32; + if (XmmReg[0,32] f< tmp) goto inst_next; + XmmReg[0,32] = tmp; +} + +:MINSS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x5D; xmmmod=3 & XmmReg1 & XmmReg2 +{ + if (XmmReg1[0,32] f< XmmReg2[0,32]) goto inst_next; + XmmReg1[0,32] = XmmReg2[0,32]; +} + +:MOVAPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x28; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,64] = m[0,64]; + XmmReg[64,64] = m[64,64]; +} + +:MOVAPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x28; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,64] = XmmReg2[0,64]; + XmmReg1[64,64] = XmmReg2[64,64]; +} + +:MOVAPD m128, XmmReg is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x29; m128 & XmmReg ... +{ + m128 = XmmReg; +} + +:MOVAPD XmmReg2, XmmReg1 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x29; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg2[0,64] = XmmReg1[0,64]; + XmmReg2[64,64] = XmmReg1[64,64]; +} + +:MOVAPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x28; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,32] = m[0,32]; + XmmReg[32,32] = m[32,32]; + XmmReg[64,32] = m[64,32]; + XmmReg[96,32] = m[96,32]; +} + +:MOVAPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x28; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = XmmReg2[0,32]; + XmmReg1[32,32] = XmmReg2[32,32]; + XmmReg1[64,32] = XmmReg2[64,32]; + XmmReg1[96,32] = XmmReg2[96,32]; +} + +:MOVAPS m128, XmmReg is vexMode=0 & mandover=0 & byte=0x0F; byte=0x29; m128 & XmmReg ... +{ + m128 = XmmReg; +} + +:MOVAPS XmmReg2, XmmReg1 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x29; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg2[0,32] = XmmReg1[0,32]; + XmmReg2[32,32] = XmmReg1[32,32]; + XmmReg2[64,32] = XmmReg1[64,32]; + XmmReg2[96,32] = XmmReg1[96,32]; +} + +:MOVD mmxreg, rm32 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x6E; rm32 & mmxreg ... { mmxreg = zext(rm32); } +:MOVD rm32, mmxreg is vexMode=0 & rexWprefix=0 & mandover=0 & byte=0x0F; byte=0x7E; rm32 & check_rm32_dest ... & mmxreg ... { rm32 = mmxreg(0); build check_rm32_dest; } +:MOVD XmmReg, rm32 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x6E; rm32 & XmmReg ... { XmmReg = zext(rm32); } +:MOVD rm32, XmmReg is vexMode=0 & $(PRE_66) & rexWprefix=0 & byte=0x0F; byte=0x7E; rm32 & check_rm32_dest ... & XmmReg ... { rm32 = XmmReg(0); build check_rm32_dest; } +@ifdef IA64 +:MOVQ mmxreg, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & mandover=0 & byte=0x0F; byte=0x6E; rm64 & mmxreg ... { mmxreg = rm64; } +:MOVQ rm64, mmxreg is $(LONGMODE_ON) & vexMode=0 & opsize=2 & mandover=0 & byte=0x0F; byte=0x7E; rm64 & mmxreg ... { rm64 = mmxreg; } +:MOVQ XmmReg, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_66) & byte=0x0F; byte=0x6E; rm64 & XmmReg ... { XmmReg = zext(rm64); } +:MOVQ rm64, XmmReg is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_66) & byte=0x0F; byte=0x7E; rm64 & XmmReg ... { rm64 = XmmReg(0); } +@endif + +:MOVDDUP XmmReg, m64 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x12; m64 & XmmReg ... +{ + XmmReg[0,64] = m64; + XmmReg[64,64] = m64; +} + +:MOVDDUP XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x12; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,64] = XmmReg2[0,64]; + XmmReg1[64,64] = XmmReg2[0,64]; +} + +:MOVSHDUP XmmReg, m128 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x16; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,32] = m[32,32]; + XmmReg[32,32] = m[32,32]; + XmmReg[64,32] = m[96,32]; + XmmReg[96,32] = m[96,32]; +} + +:MOVSHDUP XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x16; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = XmmReg2[32,32]; + XmmReg1[32,32] = XmmReg2[32,32]; + XmmReg1[64,32] = XmmReg2[96,32]; + XmmReg1[96,32] = XmmReg2[96,32]; +} + +:MOVSLDUP XmmReg, m128 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x12; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,32] = m[0,32]; + XmmReg[32,32] = m[0,32]; + XmmReg[64,32] = m[64,32]; + XmmReg[96,32] = m[64,32]; +} + +:MOVSLDUP XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x12; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = XmmReg2[0,32]; + XmmReg1[32,32] = XmmReg2[0,32]; + XmmReg1[64,32] = XmmReg2[64,32]; + XmmReg1[96,32] = XmmReg2[64,32]; +} + +:MOVDQA XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x6F; XmmReg ... & m128 { XmmReg = m128; } +:MOVDQA XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x6F; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = XmmReg2; } +:MOVDQA m128, XmmReg is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x7F; XmmReg ... & m128 { m128 = XmmReg; } +:MOVDQA XmmReg2, XmmReg1 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x7F; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg2 = XmmReg1; } + +:MOVDQU XmmReg, m128 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x6F; XmmReg ... & m128 { XmmReg = m128; } +:MOVDQU XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x6F; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = XmmReg2; } +:MOVDQU m128, XmmReg is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x7F; XmmReg ... & m128 { m128 = XmmReg; } +:MOVDQU XmmReg2, XmmReg1 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x7F; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg2 = XmmReg1; } + +# TODO: this vexMode=0 & is potentially wrong + +define pcodeop movdq2q; +:MOVDQ2Q mmxreg2, XmmReg1 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0xD6; XmmReg1 & mmxreg2 { mmxreg2 = movdq2q(mmxreg2, XmmReg1); } + +:MOVHLPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x12; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1[0,64] = XmmReg2[64,64]; } + +:MOVHPD XmmReg, m64 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x16; XmmReg ... & m64 { XmmReg[64,64] = m64; } + +:MOVHPD m64, XmmReg is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x17; XmmReg ... & m64 { m64 = XmmReg[64,64]; } + +:MOVHPS XmmReg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x16; XmmReg ... & m64 { XmmReg[64,64] = m64; } + +:MOVHPS m64, XmmReg is vexMode=0 & mandover=0 & byte=0x0F; byte=0x17; XmmReg ... & m64 { m64 = XmmReg[64,64]; } + +:MOVLHPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x16; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1[64,64] = XmmReg2[0,64]; } + +:MOVLPD XmmReg, m64 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x12; XmmReg ... & m64 { XmmReg[0,64] = m64; } + +:MOVLPD m64, XmmReg is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x13; XmmReg ... & m64 { m64 = XmmReg[0,64]; } + +:MOVLPS XmmReg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x12; XmmReg ... & m64 { XmmReg[0,64] = m64; } + +:MOVLPS m64, XmmReg is vexMode=0 & mandover=0 & byte=0x0F; byte=0x13; XmmReg ... & m64 { m64 = XmmReg[0,64]; } + +define pcodeop movmskpd; +:MOVMSKPD Reg32, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x50; XmmReg2 & Reg32 { Reg32 = movmskpd(Reg32, XmmReg2); } + +define pcodeop movmskps; +:MOVMSKPS Reg32, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x50; XmmReg2 & Reg32 { Reg32 = movmskps(Reg32, XmmReg2); } + +:MOVNTQ m64, mmxreg is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE7; mmxreg ... & m64 { m64 = mmxreg; } + +:MOVNTDQ m128, XmmReg is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE7; XmmReg ... & m128 { m128 = XmmReg; } + +:MOVNTPD m128, XmmReg is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x2B; XmmReg ... & m128 { m128 = XmmReg; } + +:MOVNTPS m128, XmmReg is vexMode=0 & mandover=0 & byte=0x0F; byte=0x2B; XmmReg ... & m128 { m128 = XmmReg; } + +:MOVQ mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x6F; mmxreg ... & m64 { mmxreg = m64; } +:MOVQ mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x6F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = mmxreg2; } +:MOVQ m64, mmxreg is vexMode=0 & mandover=0 & byte=0x0F; byte=0x7F; mmxreg ... & m64 { m64 = mmxreg; } +:MOVQ mmxreg2, mmxreg1 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x7F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg2 = mmxreg1; } + +:MOVQ XmmReg, m64 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x7E; XmmReg ... & m64 +{ + XmmReg = zext(m64); +} + +:MOVQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x7E; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1 = zext(XmmReg2[0,64]); +} + +:MOVQ m64, XmmReg is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD6; m64 & XmmReg ... +{ + m64 = XmmReg[0,64]; +} + +:MOVQ XmmReg2, XmmReg1 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD6; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg2 = zext(XmmReg1[0,64]); +} + +:MOVQ2DQ XmmReg, mmxreg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xD6; XmmReg & mmxreg2 +{ + XmmReg = zext(mmxreg2); +# may need to model x87 FPU state changes too ????? +} + +:MOVSD XmmReg, m64 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x10; m64 & XmmReg ... +{ + XmmReg[0,64] = m64; + XmmReg[64,64] = 0; +} + +:MOVSD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x10; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,64] = XmmReg2[0,64]; +} + +:MOVSD m64, XmmReg is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x11; m64 & XmmReg ... +{ + m64 = XmmReg[0,64]; +} + +:MOVSD XmmReg2, XmmReg1 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x11; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg2[0,64] = XmmReg1[0,64]; +} + +:MOVSS XmmReg, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x10; m32 & XmmReg ... +{ + XmmReg[0,32] = m32; + XmmReg[32,32] = 0; + XmmReg[64,32] = 0; + XmmReg[96,32] = 0; +} + +:MOVSS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x10; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = XmmReg2[0,32]; +} + +:MOVSS m32, XmmReg is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x11; m32 & XmmReg ... +{ + m32 = XmmReg[0,32]; +} + +:MOVSS XmmReg2, XmmReg1 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x11; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg2[0,32] = XmmReg1[0,32]; +} + +:MOVUPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x10; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,64] = m[0,64]; + XmmReg[64,64] = m[64,64]; +} + +:MOVUPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x10; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,64] = XmmReg2[0,64]; + XmmReg1[64,64] = XmmReg2[64,64]; +} + +:MOVUPD m128, XmmReg is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x11; m128 & XmmReg ... +{ + m128 = XmmReg; +} + +:MOVUPD XmmReg2, XmmReg1 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x11; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg2[0,64] = XmmReg1[0,64]; + XmmReg2[64,64] = XmmReg1[64,64]; +} + +# Not sure why someone had done it this way ????? +#Xmm2m128: m128 is vexMode=0 & m128 { export m128; } +#Xmm2m128: XmmReg2 is vexMode=0 & xmmmod=3 & XmmReg2 { export XmmReg2; } +# +#define pcodeop movups; +##:MOVUPS XmmReg, m128 is vexMode=0 & byte=0x0F; byte=0x10; XmmReg ... & m128 { XmmReg = movups(XmmReg, m128); } +##:MOVUPS XmmReg1, XmmReg2 is vexMode=0 & byte=0x0F; byte=0x10; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = movups(XmmReg1, XmmReg2); } +# +#:MOVUPS XmmReg,Xmm2m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x10; XmmReg ... & Xmm2m128 { XmmReg = movups(XmmReg, Xmm2m128); } + +:MOVUPS XmmReg, m128 is vexMode=0 & byte=0x0F; byte=0x10; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,32] = m[0,32]; + XmmReg[32,32] = m[32,32]; + XmmReg[64,32] = m[64,32]; + XmmReg[96,32] = m[96,32]; +} + +:MOVUPS XmmReg1, XmmReg2 is vexMode=0 & byte=0x0F; byte=0x10; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = XmmReg2[0,32]; + XmmReg1[32,32] = XmmReg2[32,32]; + XmmReg1[64,32] = XmmReg2[64,32]; + XmmReg1[96,32] = XmmReg2[96,32]; +} + +:MOVUPS m128, XmmReg is vexMode=0 & mandover=0 & byte=0x0F; byte=0x11; m128 & XmmReg ... +{ + m128 = XmmReg; +} + +:MOVUPS XmmReg2, XmmReg1 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x11; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg2[0,32] = XmmReg1[0,32]; + XmmReg2[32,32] = XmmReg1[32,32]; + XmmReg2[64,32] = XmmReg1[64,32]; + XmmReg2[96,32] = XmmReg1[96,32]; +} + +:MULPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x59; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,64] = XmmReg[0,64] f* m[0,64]; + XmmReg[64,64] = XmmReg[64,64] f* m[64,64]; +} + +:MULPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x59; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,64] = XmmReg1[0,64] f* XmmReg2[0,64]; + XmmReg1[64,64] = XmmReg1[64,64] f* XmmReg2[64,64]; +} + +:MULPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x59; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,32] = XmmReg[0,32] f* m[0,32]; + XmmReg[32,32] = XmmReg[32,32] f* m[32,32]; + XmmReg[64,32] = XmmReg[64,32] f* m[64,32]; + XmmReg[96,32] = XmmReg[96,32] f* m[96,32]; +} + +:MULPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x59; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = XmmReg1[0,32] f* XmmReg2[0,32]; + XmmReg1[32,32] = XmmReg1[32,32] f* XmmReg2[32,32]; + XmmReg1[64,32] = XmmReg1[64,32] f* XmmReg2[64,32]; + XmmReg1[96,32] = XmmReg1[96,32] f* XmmReg2[96,32]; +} + +:MULSD XmmReg, m64 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x59; m64 & XmmReg ... +{ + XmmReg[0,64] = XmmReg[0,64] f* m64; +} + +:MULSD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x59; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,64] = XmmReg1[0,64] f* XmmReg2[0,64]; +} + +:MULSS XmmReg, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x59; m32 & XmmReg ... +{ + XmmReg[0,32] = XmmReg[0,32] f* m32; +} + +:MULSS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x59; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = XmmReg1[0,32] f* XmmReg2[0,32]; +} + +:ORPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x56; XmmReg ... & m128 { XmmReg = XmmReg | m128; } +:ORPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x56; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = XmmReg1 | XmmReg2; } + +:ORPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x56; XmmReg ... & m128 { XmmReg = XmmReg | m128; } +:ORPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x56; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = XmmReg1 | XmmReg2; } + +#sword < 0xff80: sbyte = 0x80 +#sword > 0x007f: sbyte = 0x7f +#otherwise sbyte = sword +macro sswsb(sword, sbyte) { + local less = (sword s< 0xff80:2); + local greater = (sword s> 0x007f:2); + local inbounds = !(less || greater); + sbyte = (sword:1 * inbounds) + (0x80:1 * less) + (0x7f:1 * greater); +} + +macro packsswb_mmx(dst, src) { + local a:8 = dst; + local b:8 = src; + + sswsb(a[ 0,16], dst[ 0,8]); + sswsb(a[16,16], dst[ 8,8]); + sswsb(a[32,16], dst[16,8]); + sswsb(a[48,16], dst[24,8]); + + sswsb(b[ 0,16], dst[32,8]); + sswsb(b[16,16], dst[40,8]); + sswsb(b[32,16], dst[48,8]); + sswsb(b[48,16], dst[56,8]); +} +:PACKSSWB mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x63; mmxreg ... & m64 { packsswb_mmx(mmxreg, m64); } +:PACKSSWB mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x63; mmxmod = 3 & mmxreg1 & mmxreg2 { packsswb_mmx(mmxreg1, mmxreg2); } + +#sdword < 0xffff_8000: sword = 0x8000 +#sdword > 0x0000_7fff: sword = 0x7fff +#otherwise sbyte = sword +macro ssdsw(sword, sbyte) { + local less = (sword s< 0xffff8000:4); + local greater = (sword s> 0x00007fff:4); + local inbounds = !(less || greater); + sbyte = (sword:2 * zext(inbounds)) + (0x8000:2 * zext(less)) + (0x7fff:2 * zext(greater)); +} + +macro packssdw_mmx(dst, src) { + local a:8 = dst; + local b:8 = src; + + ssdsw(a[ 0,32], dst[ 0,16]); + ssdsw(a[32,32], dst[16,16]); + + ssdsw(b[ 0,32], dst[32,16]); + ssdsw(b[32,32], dst[48,16]); +} +:PACKSSDW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x6B; mmxreg ... & m64 { packssdw_mmx(mmxreg, m64); } +:PACKSSDW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x6B; mmxmod = 3 & mmxreg1 & mmxreg2 { packssdw_mmx(mmxreg1, mmxreg2); } + +macro packsswb_xmm(dst, src) { + local a:16 = dst; + local b:16 = src; + + sswsb(a[ 0,16], dst[ 0,8]); + sswsb(a[ 16,16], dst[ 8,8]); + sswsb(a[ 32,16], dst[ 16,8]); + sswsb(a[ 48,16], dst[ 24,8]); + sswsb(a[ 64,16], dst[ 32,8]); + sswsb(a[ 80,16], dst[ 40,8]); + sswsb(a[ 96,16], dst[ 48,8]); + sswsb(a[112,16], dst[ 56,8]); + + sswsb(b[ 0,16], dst[ 64,8]); + sswsb(b[ 16,16], dst[ 72,8]); + sswsb(b[ 32,16], dst[ 80,8]); + sswsb(b[ 48,16], dst[ 88,8]); + sswsb(b[ 64,16], dst[ 96,8]); + sswsb(b[ 80,16], dst[104,8]); + sswsb(b[ 96,16], dst[112,8]); + sswsb(b[112,16], dst[120,8]); +} +:PACKSSWB XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x63; XmmReg ... & m128 { packsswb_xmm(XmmReg, m128); } +:PACKSSWB XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x63; xmmmod = 3 & XmmReg1 & XmmReg2 { packsswb_xmm(XmmReg1, XmmReg2); } + +macro packssdw_xmm(dst, src) { + local a:16 = dst; + local b:16 = src; + + ssdsw(a[ 0,32], dst[ 0,16]); + ssdsw(a[32,32], dst[ 16,16]); + ssdsw(a[64,32], dst[ 32,16]); + ssdsw(a[96,32], dst[ 48,16]); + + ssdsw(b[ 0,32], dst[ 64,16]); + ssdsw(b[32,32], dst[ 80,16]); + ssdsw(b[64,32], dst[ 96,16]); + ssdsw(b[96,32], dst[112,16]); +} +:PACKSSDW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x6B; XmmReg ... & m128 { packssdw_xmm(XmmReg, m128); } +:PACKSSDW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x6B; xmmmod = 3 & XmmReg1 & XmmReg2 { packssdw_xmm(XmmReg1, XmmReg2); } + +#sword < 0 : ubyte = 0 +#sword > 0xff: ubyte = 0xff +#otherwise ubyte = sword +macro sswub(sword, ubyte) { + ubyte = (sword s> 0xff:2) * 0xff:1; + ubyte = ubyte + (sword s> 0:2) * (sword s<= 0xff:2) * sword:1; +} + +:PACKUSWB mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x67; mmxreg ... & m64 +{ + local dest_copy:8 = mmxreg; + local src_copy:8 = m64; + local ubyte:1 = 0; + sswub(dest_copy[0,16],ubyte); + mmxreg[0,8] = ubyte; + sswub(dest_copy[16,16],ubyte); + mmxreg[8,8] = ubyte; + sswub(dest_copy[32,16],ubyte); + mmxreg[16,8] = ubyte; + sswub(dest_copy[48,16],ubyte); + mmxreg[24,8] = ubyte; + sswub(src_copy[0,16],ubyte); + mmxreg[32,8] = ubyte; + sswub(src_copy[16,16],ubyte); + mmxreg[40,8] = ubyte; + sswub(src_copy[32,16],ubyte); + mmxreg[48,8] = ubyte; + sswub(src_copy[48,16],ubyte); + mmxreg[56,8] = ubyte; +} + +:PACKUSWB mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x67; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + local dest_copy:8 = mmxreg1; + local src_copy:8 = mmxreg2; + local ubyte:1 = 0; + sswub(dest_copy[0,16],ubyte); + mmxreg1[0,8] = ubyte; + sswub(dest_copy[16,16],ubyte); + mmxreg1[8,8] = ubyte; + sswub(dest_copy[32,16],ubyte); + mmxreg1[16,8] = ubyte; + sswub(dest_copy[48,16],ubyte); + mmxreg1[24,8] = ubyte; + sswub(src_copy[0,16],ubyte); + mmxreg1[32,8] = ubyte; + sswub(src_copy[16,16],ubyte); + mmxreg1[40,8] = ubyte; + sswub(src_copy[32,16],ubyte); + mmxreg1[48,8] = ubyte; + sswub(src_copy[48,16],ubyte); + mmxreg1[56,8] = ubyte; +} + +:PACKUSWB XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x67; XmmReg ... & m128 +{ + local dest_copy:16 = XmmReg; + local src_copy:16 = m128; + local ubyte:1 = 0; + sswub(dest_copy[0,16],ubyte); + XmmReg[0,8] = ubyte; + sswub(dest_copy[16,16],ubyte); + XmmReg[8,8] = ubyte; + sswub(dest_copy[32,16],ubyte); + XmmReg[16,8] = ubyte; + sswub(dest_copy[48,16],ubyte); + XmmReg[24,8] = ubyte; + sswub(dest_copy[64,16],ubyte); + XmmReg[32,8] = ubyte; + sswub(dest_copy[80,16],ubyte); + XmmReg[40,8] = ubyte; + sswub(dest_copy[96,16],ubyte); + XmmReg[48,8] = ubyte; + sswub(dest_copy[112,16],ubyte); + XmmReg[56,8] = ubyte; + + sswub(src_copy[0,16],ubyte); + XmmReg[64,8] = ubyte; + sswub(src_copy[16,16],ubyte); + XmmReg[72,8] = ubyte; + sswub(src_copy[32,16],ubyte); + XmmReg[80,8] = ubyte; + sswub(src_copy[48,16],ubyte); + XmmReg[88,8] = ubyte; + sswub(src_copy[64,16],ubyte); + XmmReg[96,8] = ubyte; + sswub(src_copy[80,16],ubyte); + XmmReg[104,8] = ubyte; + sswub(src_copy[96,16],ubyte); + XmmReg[112,8] = ubyte; + sswub(src_copy[112,16],ubyte); + XmmReg[120,8] = ubyte; +} + +:PACKUSWB XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x67; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + local dest_copy:16 = XmmReg1; + local src_copy:16 = XmmReg2; + local ubyte:1 = 0; + sswub(dest_copy[0,16],ubyte); + XmmReg1[0,8] = ubyte; + sswub(dest_copy[16,16],ubyte); + XmmReg1[8,8] = ubyte; + sswub(dest_copy[32,16],ubyte); + XmmReg1[16,8] = ubyte; + sswub(dest_copy[48,16],ubyte); + XmmReg1[24,8] = ubyte; + sswub(dest_copy[64,16],ubyte); + XmmReg1[32,8] = ubyte; + sswub(dest_copy[80,16],ubyte); + XmmReg1[40,8] = ubyte; + sswub(dest_copy[96,16],ubyte); + XmmReg1[48,8] = ubyte; + sswub(dest_copy[112,16],ubyte); + XmmReg1[56,8] = ubyte; + + sswub(src_copy[0,16],ubyte); + XmmReg1[64,8] = ubyte; + sswub(src_copy[16,16],ubyte); + XmmReg1[72,8] = ubyte; + sswub(src_copy[32,16],ubyte); + XmmReg1[80,8] = ubyte; + sswub(src_copy[48,16],ubyte); + XmmReg1[88,8] = ubyte; + sswub(src_copy[64,16],ubyte); + XmmReg1[96,8] = ubyte; + sswub(src_copy[80,16],ubyte); + XmmReg1[104,8] = ubyte; + sswub(src_copy[96,16],ubyte); + XmmReg1[112,8] = ubyte; + sswub(src_copy[112,16],ubyte); + XmmReg1[120,8] = ubyte; +} + +define pcodeop pabsb; +:PABSB mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x1c; mmxreg ... & m64 { mmxreg=pabsb(mmxreg,m64); } +:PABSB mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x1c; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=pabsb(mmxreg1,mmxreg2); } +:PABSB XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x1c; XmmReg ... & m128 { XmmReg=pabsb(XmmReg,m128); } +:PABSB XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x1c; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=pabsb(XmmReg1,XmmReg2); } + +define pcodeop pabsw; +:PABSW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x1d; mmxreg ... & m64 { mmxreg=pabsw(mmxreg,m64); } +:PABSW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x1d; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=pabsw(mmxreg1,mmxreg2); } +:PABSW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x1d; XmmReg ... & m128 { XmmReg=pabsw(XmmReg,m128); } +:PABSW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x1d; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=pabsw(XmmReg1,XmmReg2); } + +define pcodeop pabsd; +:PABSD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x1e; mmxreg ... & m64 { mmxreg=pabsd(mmxreg,m64); } +:PABSD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x1e; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=pabsd(mmxreg1,mmxreg2); } +:PABSD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x1e; XmmReg ... & m128 { XmmReg=pabsd(XmmReg,m128); } +:PABSD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x1e; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=pabsd(XmmReg1,XmmReg2); } + +:PADDB mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xFC; mmxreg ... & m64 +{ + local m:8 = m64; + mmxreg[0,8] = mmxreg[0,8] + m[0,8]; + mmxreg[8,8] = mmxreg[8,8] + m[8,8]; + mmxreg[16,8] = mmxreg[16,8] + m[16,8]; + mmxreg[24,8] = mmxreg[24,8] + m[24,8]; + mmxreg[32,8] = mmxreg[32,8] + m[32,8]; + mmxreg[40,8] = mmxreg[40,8] + m[40,8]; + mmxreg[48,8] = mmxreg[48,8] + m[48,8]; + mmxreg[56,8] = mmxreg[56,8] + m[56,8]; +} + +:PADDB mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xFC; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + mmxreg1[0,8] = mmxreg1[0,8] + mmxreg2[0,8]; + mmxreg1[8,8] = mmxreg1[8,8] + mmxreg2[8,8]; + mmxreg1[16,8] = mmxreg1[16,8] + mmxreg2[16,8]; + mmxreg1[24,8] = mmxreg1[24,8] + mmxreg2[24,8]; + mmxreg1[32,8] = mmxreg1[32,8] + mmxreg2[32,8]; + mmxreg1[40,8] = mmxreg1[40,8] + mmxreg2[40,8]; + mmxreg1[48,8] = mmxreg1[48,8] + mmxreg2[48,8]; + mmxreg1[56,8] = mmxreg1[56,8] + mmxreg2[56,8]; +} + +:PADDW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xFD; mmxreg ... & m64 +{ + local m:8 = m64; + mmxreg[0,16] = mmxreg[0,16] + m[0,16]; + mmxreg[16,16] = mmxreg[16,16] + m[16,16]; + mmxreg[32,16] = mmxreg[32,16] + m[32,16]; + mmxreg[48,16] = mmxreg[48,16] + m[48,16]; +} + +:PADDW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xFD; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + mmxreg1[0,16] = mmxreg1[0,16] + mmxreg2[0,16]; + mmxreg1[16,16] = mmxreg1[16,16] + mmxreg2[16,16]; + mmxreg1[32,16] = mmxreg1[32,16] + mmxreg2[32,16]; + mmxreg1[48,16] = mmxreg1[48,16] + mmxreg2[48,16]; +} + +:PADDD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xFE; mmxreg ... & m64 +{ + local m:8 = m64; + mmxreg[0,32] = mmxreg[0,32] + m[0,32]; + mmxreg[32,32] = mmxreg[32,32] + m[32,32]; +} + +:PADDD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xFE; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + mmxreg1[0,32] = mmxreg1[0,32] + mmxreg2[0,32]; + mmxreg1[32,32] = mmxreg1[32,32] + mmxreg2[32,32]; +} + +:PADDB XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xFC; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,8] = XmmReg[0,8] + m[0,8]; + XmmReg[8,8] = XmmReg[8,8] + m[8,8]; + XmmReg[16,8] = XmmReg[16,8] + m[16,8]; + XmmReg[24,8] = XmmReg[24,8] + m[24,8]; + XmmReg[32,8] = XmmReg[32,8] + m[32,8]; + XmmReg[40,8] = XmmReg[40,8] + m[40,8]; + XmmReg[48,8] = XmmReg[48,8] + m[48,8]; + XmmReg[56,8] = XmmReg[56,8] + m[56,8]; + XmmReg[64,8] = XmmReg[64,8] + m[64,8]; + XmmReg[72,8] = XmmReg[72,8] + m[72,8]; + XmmReg[80,8] = XmmReg[80,8] + m[80,8]; + XmmReg[88,8] = XmmReg[88,8] + m[88,8]; + XmmReg[96,8] = XmmReg[96,8] + m[96,8]; + XmmReg[104,8] = XmmReg[104,8] + m[104,8]; + XmmReg[112,8] = XmmReg[112,8] + m[112,8]; + XmmReg[120,8] = XmmReg[120,8] + m[120,8]; +} + +## example of bitfield solution +#:PADDB XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xFC; xmmmod = 3 & XmmReg1 & XmmReg2 +#{ +# XmmReg1[ 0,8] = XmmReg1[ 0,8] + XmmReg2[ 0,8]; +# XmmReg1[ 8,8] = XmmReg1[ 8,8] + XmmReg2[ 8,8]; +# XmmReg1[ 16,8] = XmmReg1[ 16,8] + XmmReg2[ 16,8]; +# XmmReg1[ 24,8] = XmmReg1[ 24,8] + XmmReg2[ 24,8]; +# XmmReg1[ 32,8] = XmmReg1[ 32,8] + XmmReg2[ 32,8]; +# XmmReg1[ 40,8] = XmmReg1[ 40,8] + XmmReg2[ 40,8]; +# XmmReg1[ 48,8] = XmmReg1[ 48,8] + XmmReg2[ 48,8]; +# XmmReg1[ 56,8] = XmmReg1[ 56,8] + XmmReg2[ 56,8]; +## XmmReg1[ 64,8] = XmmReg1[ 64,8] + XmmReg2[ 64,8]; +## XmmReg1[ 72,8] = XmmReg1[ 72,8] + XmmReg2[ 72,8]; +## XmmReg1[ 80,8] = XmmReg1[ 80,8] + XmmReg2[ 80,8]; +## XmmReg1[ 88,8] = XmmReg1[ 88,8] + XmmReg2[ 88,8]; +## XmmReg1[ 96,8] = XmmReg1[ 96,8] + XmmReg2[ 96,8]; +## XmmReg1[104,8] = XmmReg1[104,8] + XmmReg2[104,8]; +## XmmReg1[112,8] = XmmReg1[112,8] + XmmReg2[112,8]; +## XmmReg1[120,8] = XmmReg1[120,8] + XmmReg2[120,8]; +#} + +# full set of XMM byte registers +:PADDB XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xFC; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,8] = XmmReg1[0,8] + XmmReg2[0,8]; + XmmReg1[8,8] = XmmReg1[8,8] + XmmReg2[8,8]; + XmmReg1[16,8] = XmmReg1[16,8] + XmmReg2[16,8]; + XmmReg1[24,8] = XmmReg1[24,8] + XmmReg2[24,8]; + XmmReg1[32,8] = XmmReg1[32,8] + XmmReg2[32,8]; + XmmReg1[40,8] = XmmReg1[40,8] + XmmReg2[40,8]; + XmmReg1[48,8] = XmmReg1[48,8] + XmmReg2[48,8]; + XmmReg1[56,8] = XmmReg1[56,8] + XmmReg2[56,8]; + XmmReg1[64,8] = XmmReg1[64,8] + XmmReg2[64,8]; + XmmReg1[72,8] = XmmReg1[72,8] + XmmReg2[72,8]; + XmmReg1[80,8] = XmmReg1[80,8] + XmmReg2[80,8]; + XmmReg1[88,8] = XmmReg1[88,8] + XmmReg2[88,8]; + XmmReg1[96,8] = XmmReg1[96,8] + XmmReg2[96,8]; + XmmReg1[104,8] = XmmReg1[104,8] + XmmReg2[104,8]; + XmmReg1[112,8] = XmmReg1[112,8] + XmmReg2[112,8]; + XmmReg1[120,8] = XmmReg1[120,8] + XmmReg2[120,8]; +} + +:PADDW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xFD; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,16] = XmmReg[0,16] + m[0,16]; + XmmReg[16,16] = XmmReg[16,16] + m[16,16]; + XmmReg[32,16] = XmmReg[32,16] + m[32,16]; + XmmReg[48,16] = XmmReg[48,16] + m[48,16]; + XmmReg[64,16] = XmmReg[64,16] + m[64,16]; + XmmReg[80,16] = XmmReg[80,16] + m[80,16]; + XmmReg[96,16] = XmmReg[96,16] + m[96,16]; + XmmReg[112,16] = XmmReg[112,16] + m[112,16]; +} + +:PADDW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xFD; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,16] = XmmReg1[0,16] + XmmReg2[0,16]; + XmmReg1[16,16] = XmmReg1[16,16] + XmmReg2[16,16]; + XmmReg1[32,16] = XmmReg1[32,16] + XmmReg2[32,16]; + XmmReg1[48,16] = XmmReg1[48,16] + XmmReg2[48,16]; + XmmReg1[64,16] = XmmReg1[64,16] + XmmReg2[64,16]; + XmmReg1[80,16] = XmmReg1[80,16] + XmmReg2[80,16]; + XmmReg1[96,16] = XmmReg1[96,16] + XmmReg2[96,16]; + XmmReg1[112,16] = XmmReg1[112,16] + XmmReg2[112,16]; +} + +:PADDD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xFE; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,32] = XmmReg[0,32] + m[0,32]; + XmmReg[32,32] = XmmReg[32,32] + m[32,32]; + XmmReg[64,32] = XmmReg[64,32] + m[64,32]; + XmmReg[96,32] = XmmReg[96,32] + m[96,32]; +} + +:PADDD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xFE; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = XmmReg1[0,32] + XmmReg2[0,32]; + XmmReg1[32,32] = XmmReg1[32,32] + XmmReg2[32,32]; + XmmReg1[64,32] = XmmReg1[64,32] + XmmReg2[64,32]; + XmmReg1[96,32] = XmmReg1[96,32] + XmmReg2[96,32]; +} + +:PADDQ mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD4; mmxreg ... & m64 +{ + mmxreg = mmxreg + m64; +} + +:PADDQ mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD4; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + mmxreg1 = mmxreg1 + mmxreg2; +} + +:PADDQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD4; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,64] = XmmReg[0,64] + m[0,64]; + XmmReg[64,64] = XmmReg[64,64] + m[64,64]; +} + +:PADDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD4; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,64] = XmmReg1[0,64] + XmmReg2[0,64]; + XmmReg1[64,64] = XmmReg1[64,64] + XmmReg2[64,64]; +} + +define pcodeop paddsb; +:PADDSB mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xEC; mmxreg1 ... & mmxreg2_m64 { mmxreg1 = paddsb(mmxreg1, mmxreg2_m64); } + +define pcodeop paddsw; +:PADDSW mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xED; mmxreg1 ... & mmxreg2_m64 { mmxreg1 = paddsw(mmxreg1, mmxreg2_m64); } + +:PADDSB XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xEC; XmmReg1 ... & XmmReg2_m128 { XmmReg1 = paddsb(XmmReg1, XmmReg2_m128); } +:PADDSW XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xED; XmmReg1 ... & XmmReg2_m128 { XmmReg1 = paddsw(XmmReg1, XmmReg2_m128); } + +define pcodeop paddusb; +:PADDUSB mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xDC; mmxreg1 ... & mmxreg2_m64 { mmxreg1 = paddusb(mmxreg1, mmxreg2_m64); } + +define pcodeop paddusw; +:PADDUSW mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xDD; mmxreg1 ... & mmxreg2_m64 { mmxreg1 = paddusw(mmxreg1, mmxreg2_m64); } + +:PADDUSB XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xDC; XmmReg1 ... & XmmReg2_m128 { XmmReg1 = paddusb(XmmReg1, XmmReg2_m128); } +:PADDUSW XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xDD; XmmReg1 ... & XmmReg2_m128 { XmmReg1 = paddusw(XmmReg1, XmmReg2_m128); } + +:PALIGNR mmxreg, m64, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x3A; byte=0x0F; m64 & mmxreg ...; imm8 +{ + temp:16 = ( ( zext(mmxreg) << 64 ) | zext( m64 ) ) >> ( imm8 * 8 ); + mmxreg = temp:8; +} + +:PALIGNR mmxreg1, mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x3A; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2; imm8 +{ + temp:16 = ( ( zext(mmxreg1) << 64 ) | zext( mmxreg2 ) ) >> ( imm8 * 8 ); + mmxreg1 = temp:8; +} + +:PALIGNR XmmReg1, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x0F; m128 & XmmReg1 ...; imm8 +{ + temp:32 = ( ( zext(XmmReg1) << 128 ) | zext( m128 ) ) >> ( imm8 * 8 ); + XmmReg1 = temp:16; +} + +:PALIGNR XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x0F; xmmmod=3 & XmmReg1 & XmmReg2; imm8 +{ + temp:32 = ( ( zext(XmmReg1) << 128 ) | zext( XmmReg2 ) ) >> ( imm8 * 8 ); + XmmReg1 = temp:16; +} + +:PAND mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xDB; mmxreg ... & m64 { mmxreg = mmxreg & m64; } +:PAND mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xDB; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = mmxreg1 & mmxreg2; } +:PAND XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xDB; XmmReg ... & m128 { XmmReg = XmmReg & m128; } +:PAND XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xDB; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = XmmReg1 & XmmReg2; } + +:PANDN mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xDF; mmxreg ... & m64 { mmxreg = ~mmxreg & m64; } +:PANDN mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xDF; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = ~mmxreg1 & mmxreg2; } +:PANDN XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xDF; XmmReg ... & m128 { XmmReg = ~XmmReg & m128; } +:PANDN XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xDF; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = ~XmmReg1 & XmmReg2; } + +define pcodeop pavgb; +:PAVGB mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE0; mmxreg ... & m64 +{ + local m:8 = m64; + mmxreg[0,8] = pavgb(mmxreg[0,8], m[0,8]); + mmxreg[8,8] = pavgb(mmxreg[8,8], m[8,8]); + mmxreg[16,8] = pavgb(mmxreg[16,8], m[16,8]); + mmxreg[24,8] = pavgb(mmxreg[24,8], m[24,8]); + mmxreg[32,8] = pavgb(mmxreg[32,8], m[32,8]); + mmxreg[40,8] = pavgb(mmxreg[40,8], m[40,8]); + mmxreg[48,8] = pavgb(mmxreg[48,8], m[48,8]); + mmxreg[56,8] = pavgb(mmxreg[56,8], m[56,8]); +} + +:PAVGB mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE0; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + mmxreg1[0,8] = pavgb(mmxreg1[0,8], mmxreg2[0,8]); + mmxreg1[8,8] = pavgb(mmxreg1[8,8], mmxreg2[8,8]); + mmxreg1[16,8] = pavgb(mmxreg1[16,8], mmxreg2[16,8]); + mmxreg1[24,8] = pavgb(mmxreg1[24,8], mmxreg2[24,8]); + mmxreg1[32,8] = pavgb(mmxreg1[32,8], mmxreg2[32,8]); + mmxreg1[40,8] = pavgb(mmxreg1[40,8], mmxreg2[40,8]); + mmxreg1[48,8] = pavgb(mmxreg1[48,8], mmxreg2[48,8]); + mmxreg1[56,8] = pavgb(mmxreg1[56,8], mmxreg2[56,8]); +} + +define pcodeop pavgw; +:PAVGW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE3; mmxreg ... & m64 +{ + local m:8 = m64; + mmxreg[0,16] = pavgw(mmxreg[0,16], m[0,16]); + mmxreg[16,16] = pavgw(mmxreg[16,16], m[16,16]); + mmxreg[32,16] = pavgw(mmxreg[32,16], m[32,16]); + mmxreg[48,16] = pavgw(mmxreg[48,16], m[48,16]); +} + +:PAVGW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE3; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + mmxreg1[0,16] = pavgw(mmxreg1[0,16], mmxreg2[0,16]); + mmxreg1[16,16] = pavgw(mmxreg1[16,16], mmxreg2[16,16]); + mmxreg1[32,16] = pavgw(mmxreg1[32,16], mmxreg2[32,16]); + mmxreg1[48,16] = pavgw(mmxreg1[48,16], mmxreg2[48,16]); +} + +:PAVGB XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE0; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,8] = pavgb(XmmReg[0,8], m[0,8]); + XmmReg[8,8] = pavgb(XmmReg[8,8], m[8,8]); + XmmReg[16,8] = pavgb(XmmReg[16,8], m[16,8]); + XmmReg[24,8] = pavgb(XmmReg[24,8], m[24,8]); + XmmReg[32,8] = pavgb(XmmReg[32,8], m[32,8]); + XmmReg[40,8] = pavgb(XmmReg[40,8], m[40,8]); + XmmReg[48,8] = pavgb(XmmReg[48,8], m[48,8]); + XmmReg[56,8] = pavgb(XmmReg[56,8], m[56,8]); + XmmReg[64,8] = pavgb(XmmReg[64,8], m[64,8]); + XmmReg[72,8] = pavgb(XmmReg[72,8], m[72,8]); + XmmReg[80,8] = pavgb(XmmReg[80,8], m[80,8]); + XmmReg[88,8] = pavgb(XmmReg[88,8], m[88,8]); + XmmReg[96,8] = pavgb(XmmReg[96,8], m[96,8]); + XmmReg[104,8] = pavgb(XmmReg[104,8], m[104,8]); + XmmReg[112,8] = pavgb(XmmReg[112,8], m[112,8]); + XmmReg[120,8] = pavgb(XmmReg[120,8], m[120,8]); +} + +# full set of XMM byte registers +:PAVGB XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE0; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,8] = pavgb(XmmReg1[0,8], XmmReg2[0,8]); + XmmReg1[8,8] = pavgb(XmmReg1[8,8], XmmReg2[8,8]); + XmmReg1[16,8] = pavgb(XmmReg1[16,8], XmmReg2[16,8]); + XmmReg1[24,8] = pavgb(XmmReg1[24,8], XmmReg2[24,8]); + XmmReg1[32,8] = pavgb(XmmReg1[32,8], XmmReg2[32,8]); + XmmReg1[40,8] = pavgb(XmmReg1[40,8], XmmReg2[40,8]); + XmmReg1[48,8] = pavgb(XmmReg1[48,8], XmmReg2[48,8]); + XmmReg1[56,8] = pavgb(XmmReg1[56,8], XmmReg2[56,8]); + XmmReg1[64,8] = pavgb(XmmReg1[64,8], XmmReg2[64,8]); + XmmReg1[72,8] = pavgb(XmmReg1[72,8], XmmReg2[72,8]); + XmmReg1[80,8] = pavgb(XmmReg1[80,8], XmmReg2[80,8]); + XmmReg1[88,8] = pavgb(XmmReg1[88,8], XmmReg2[88,8]); + XmmReg1[96,8] = pavgb(XmmReg1[96,8], XmmReg2[96,8]); + XmmReg1[104,8] = pavgb(XmmReg1[104,8], XmmReg2[104,8]); + XmmReg1[112,8] = pavgb(XmmReg1[112,8], XmmReg2[112,8]); + XmmReg1[120,8] = pavgb(XmmReg1[120,8], XmmReg2[120,8]); +} + +:PAVGW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE3; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,16] = pavgw(XmmReg[0,16], m[0,16]); + XmmReg[16,16] = pavgw(XmmReg[16,16], m[16,16]); + XmmReg[32,16] = pavgw(XmmReg[32,16], m[32,16]); + XmmReg[48,16] = pavgw(XmmReg[48,16], m[48,16]); + XmmReg[64,16] = pavgw(XmmReg[64,16], m[64,16]); + XmmReg[80,16] = pavgw(XmmReg[80,16], m[80,16]); + XmmReg[96,16] = pavgw(XmmReg[96,16], m[96,16]); + XmmReg[112,16] = pavgw(XmmReg[112,16], m[112,16]); +} + +:PAVGW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE3; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,16] = pavgw(XmmReg1[0,16], XmmReg2[0,16]); + XmmReg1[16,16] = pavgw(XmmReg1[16,16], XmmReg2[16,16]); + XmmReg1[32,16] = pavgw(XmmReg1[32,16], XmmReg2[32,16]); + XmmReg1[48,16] = pavgw(XmmReg1[48,16], XmmReg2[48,16]); + XmmReg1[64,16] = pavgw(XmmReg1[64,16], XmmReg2[64,16]); + XmmReg1[80,16] = pavgw(XmmReg1[80,16], XmmReg2[80,16]); + XmmReg1[96,16] = pavgw(XmmReg1[96,16], XmmReg2[96,16]); + XmmReg1[112,16] = pavgw(XmmReg1[112,16], XmmReg2[112,16]); +} + +:PCMPEQB mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x74; mmxreg ... & m64 +{ + local m:8 = m64; + mmxreg[0,8] = (mmxreg[0,8] == m[0,8]) * 0xFF; + mmxreg[8,8] = (mmxreg[8,8] == m[8,8]) * 0xFF; + mmxreg[16,8] = (mmxreg[16,8] == m[16,8]) * 0xFF; + mmxreg[24,8] = (mmxreg[24,8] == m[24,8]) * 0xFF; + mmxreg[32,8] = (mmxreg[32,8] == m[32,8]) * 0xFF; + mmxreg[40,8] = (mmxreg[40,8] == m[40,8]) * 0xFF; + mmxreg[48,8] = (mmxreg[48,8] == m[48,8]) * 0xFF; + mmxreg[56,8] = (mmxreg[56,8] == m[56,8]) * 0xFF; +} + +:PCMPEQB mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x74; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + mmxreg1[0,8] = (mmxreg1[0,8] == mmxreg2[0,8]) * 0xFF; + mmxreg1[8,8] = (mmxreg1[8,8] == mmxreg2[8,8]) * 0xFF; + mmxreg1[16,8] = (mmxreg1[16,8] == mmxreg2[16,8]) * 0xFF; + mmxreg1[24,8] = (mmxreg1[24,8] == mmxreg2[24,8]) * 0xFF; + mmxreg1[32,8] = (mmxreg1[32,8] == mmxreg2[32,8]) * 0xFF; + mmxreg1[40,8] = (mmxreg1[40,8] == mmxreg2[40,8]) * 0xFF; + mmxreg1[48,8] = (mmxreg1[48,8] == mmxreg2[48,8]) * 0xFF; + mmxreg1[56,8] = (mmxreg1[56,8] == mmxreg2[56,8]) * 0xFF; +} + +:PCMPEQW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x75; mmxreg ... & m64 +{ + local m:8 = m64; + mmxreg[0,16] = zext(mmxreg[0,16] == m[0,16]) * 0xFFFF; + mmxreg[16,16] = zext(mmxreg[16,16] == m[16,16]) * 0xFFFF; + mmxreg[32,16] = zext(mmxreg[32,16] == m[32,16]) * 0xFFFF; + mmxreg[48,16] = zext(mmxreg[48,16] == m[48,16]) * 0xFFFF; +} + +:PCMPEQW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x75; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + mmxreg1[0,16] = zext(mmxreg1[0,16] == mmxreg2[0,16]) * 0xFFFF; + mmxreg1[16,16] = zext(mmxreg1[16,16] == mmxreg2[16,16]) * 0xFFFF; + mmxreg1[32,16] = zext(mmxreg1[32,16] == mmxreg2[32,16]) * 0xFFFF; + mmxreg1[48,16] = zext(mmxreg1[48,16] == mmxreg2[48,16]) * 0xFFFF; +} + +:PCMPEQD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x76; mmxreg ... & m64 +{ + local m:8 = m64; + mmxreg[0,32] = zext(mmxreg[0,32] == m[0,32]) * 0xFFFFFFFF; + mmxreg[32,32] = zext(mmxreg[32,32] == m[32,32]) * 0xFFFFFFFF; +} + +:PCMPEQD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x76; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + mmxreg1[0,32] = zext(mmxreg1[0,32] == mmxreg2[0,32]) * 0xFFFFFFFF; + mmxreg1[32,32] = zext(mmxreg1[32,32] == mmxreg2[32,32]) * 0xFFFFFFFF; +} + +:PCMPEQB XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x74; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,8] = (XmmReg[0,8] == m[0,8]) * 0xFF; + XmmReg[8,8] = (XmmReg[8,8] == m[8,8]) * 0xFF; + XmmReg[16,8] = (XmmReg[16,8] == m[16,8]) * 0xFF; + XmmReg[24,8] = (XmmReg[24,8] == m[24,8]) * 0xFF; + XmmReg[32,8] = (XmmReg[32,8] == m[32,8]) * 0xFF; + XmmReg[40,8] = (XmmReg[40,8] == m[40,8]) * 0xFF; + XmmReg[48,8] = (XmmReg[48,8] == m[48,8]) * 0xFF; + XmmReg[56,8] = (XmmReg[56,8] == m[56,8]) * 0xFF; + XmmReg[64,8] = (XmmReg[64,8] == m[64,8]) * 0xFF; + XmmReg[72,8] = (XmmReg[72,8] == m[72,8]) * 0xFF; + XmmReg[80,8] = (XmmReg[80,8] == m[80,8]) * 0xFF; + XmmReg[88,8] = (XmmReg[88,8] == m[88,8]) * 0xFF; + XmmReg[96,8] = (XmmReg[96,8] == m[96,8]) * 0xFF; + XmmReg[104,8] = (XmmReg[104,8] == m[104,8]) * 0xFF; + XmmReg[112,8] = (XmmReg[112,8] == m[112,8]) * 0xFF; + XmmReg[120,8] = (XmmReg[120,8] == m[120,8]) * 0xFF; +} + +# full set of XMM byte registers +:PCMPEQB XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x74; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,8] = (XmmReg1[0,8] == XmmReg2[0,8]) * 0xFF; + XmmReg1[8,8] = (XmmReg1[8,8] == XmmReg2[8,8]) * 0xFF; + XmmReg1[16,8] = (XmmReg1[16,8] == XmmReg2[16,8]) * 0xFF; + XmmReg1[24,8] = (XmmReg1[24,8] == XmmReg2[24,8]) * 0xFF; + XmmReg1[32,8] = (XmmReg1[32,8] == XmmReg2[32,8]) * 0xFF; + XmmReg1[40,8] = (XmmReg1[40,8] == XmmReg2[40,8]) * 0xFF; + XmmReg1[48,8] = (XmmReg1[48,8] == XmmReg2[48,8]) * 0xFF; + XmmReg1[56,8] = (XmmReg1[56,8] == XmmReg2[56,8]) * 0xFF; + XmmReg1[64,8] = (XmmReg1[64,8] == XmmReg2[64,8]) * 0xFF; + XmmReg1[72,8] = (XmmReg1[72,8] == XmmReg2[72,8]) * 0xFF; + XmmReg1[80,8] = (XmmReg1[80,8] == XmmReg2[80,8]) * 0xFF; + XmmReg1[88,8] = (XmmReg1[88,8] == XmmReg2[88,8]) * 0xFF; + XmmReg1[96,8] = (XmmReg1[96,8] == XmmReg2[96,8]) * 0xFF; + XmmReg1[104,8] = (XmmReg1[104,8] == XmmReg2[104,8]) * 0xFF; + XmmReg1[112,8] = (XmmReg1[112,8] == XmmReg2[112,8]) * 0xFF; + XmmReg1[120,8] = (XmmReg1[120,8] == XmmReg2[120,8]) * 0xFF; +} + +:PCMPEQW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x75; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,16] = zext(XmmReg[0,16] == m[0,16]) * 0xFFFF; + XmmReg[16,16] = zext(XmmReg[16,16] == m[16,16]) * 0xFFFF; + XmmReg[32,16] = zext(XmmReg[32,16] == m[32,16]) * 0xFFFF; + XmmReg[48,16] = zext(XmmReg[48,16] == m[48,16]) * 0xFFFF; + XmmReg[64,16] = zext(XmmReg[64,16] == m[64,16]) * 0xFFFF; + XmmReg[80,16] = zext(XmmReg[80,16] == m[80,16]) * 0xFFFF; + XmmReg[96,16] = zext(XmmReg[96,16] == m[96,16]) * 0xFFFF; + XmmReg[112,16] = zext(XmmReg[112,16] == m[112,16]) * 0xFFFF; +} + +:PCMPEQW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x75; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,16] = zext(XmmReg1[0,16] == XmmReg2[0,16]) * 0xFFFF; + XmmReg1[16,16] = zext(XmmReg1[16,16] == XmmReg2[16,16]) * 0xFFFF; + XmmReg1[32,16] = zext(XmmReg1[32,16] == XmmReg2[32,16]) * 0xFFFF; + XmmReg1[48,16] = zext(XmmReg1[48,16] == XmmReg2[48,16]) * 0xFFFF; + XmmReg1[64,16] = zext(XmmReg1[64,16] == XmmReg2[64,16]) * 0xFFFF; + XmmReg1[80,16] = zext(XmmReg1[80,16] == XmmReg2[80,16]) * 0xFFFF; + XmmReg1[96,16] = zext(XmmReg1[96,16] == XmmReg2[96,16]) * 0xFFFF; + XmmReg1[112,16] = zext(XmmReg1[112,16] == XmmReg2[112,16]) * 0xFFFF; +} + +:PCMPEQD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x76; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,32] = zext(XmmReg[0,32] == m[0,32]) * 0xFFFFFFFF; + XmmReg[32,32] = zext(XmmReg[32,32] == m[32,32]) * 0xFFFFFFFF; + XmmReg[64,32] = zext(XmmReg[64,32] == m[64,32]) * 0xFFFFFFFF; + XmmReg[96,32] = zext(XmmReg[96,32] == m[96,32]) * 0xFFFFFFFF; +} + +:PCMPEQD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x76; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = zext(XmmReg1[0,32] == XmmReg2[0,32]) * 0xFFFFFFFF; + XmmReg1[32,32] = zext(XmmReg1[32,32] == XmmReg2[32,32]) * 0xFFFFFFFF; + XmmReg1[64,32] = zext(XmmReg1[64,32] == XmmReg2[64,32]) * 0xFFFFFFFF; + XmmReg1[96,32] = zext(XmmReg1[96,32] == XmmReg2[96,32]) * 0xFFFFFFFF; +} + +:PCMPGTB mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x64; mmxreg ... & m64 +{ + local m:8 = m64; + mmxreg[0,8] = (mmxreg[0,8] s> m[0,8]) * 0xFF; + mmxreg[8,8] = (mmxreg[8,8] s> m[8,8]) * 0xFF; + mmxreg[16,8] = (mmxreg[16,8] s> m[16,8]) * 0xFF; + mmxreg[24,8] = (mmxreg[24,8] s> m[24,8]) * 0xFF; + mmxreg[32,8] = (mmxreg[32,8] s> m[32,8]) * 0xFF; + mmxreg[40,8] = (mmxreg[40,8] s> m[40,8]) * 0xFF; + mmxreg[48,8] = (mmxreg[48,8] s> m[48,8]) * 0xFF; + mmxreg[56,8] = (mmxreg[56,8] s> m[56,8]) * 0xFF; +} + +:PCMPGTB mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x64; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + mmxreg1[0,8] = (mmxreg1[0,8] s> mmxreg2[0,8]) * 0xFF; + mmxreg1[8,8] = (mmxreg1[8,8] s> mmxreg2[8,8]) * 0xFF; + mmxreg1[16,8] = (mmxreg1[16,8] s> mmxreg2[16,8]) * 0xFF; + mmxreg1[24,8] = (mmxreg1[24,8] s> mmxreg2[24,8]) * 0xFF; + mmxreg1[32,8] = (mmxreg1[32,8] s> mmxreg2[32,8]) * 0xFF; + mmxreg1[40,8] = (mmxreg1[40,8] s> mmxreg2[40,8]) * 0xFF; + mmxreg1[48,8] = (mmxreg1[48,8] s> mmxreg2[48,8]) * 0xFF; + mmxreg1[56,8] = (mmxreg1[56,8] s> mmxreg2[56,8]) * 0xFF; +} + +:PCMPGTW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x65; mmxreg ... & m64 +{ + local m:8 = m64; + mmxreg[0,16] = zext(mmxreg[0,16] s> m[0,16]) * 0xFFFF; + mmxreg[16,16] = zext(mmxreg[16,16] s> m[16,16]) * 0xFFFF; + mmxreg[32,16] = zext(mmxreg[32,16] s> m[32,16]) * 0xFFFF; + mmxreg[48,16] = zext(mmxreg[48,16] s> m[48,16]) * 0xFFFF; +} + +:PCMPGTW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x65; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + mmxreg1[0,16] = zext(mmxreg1[0,16] s> mmxreg2[0,16]) * 0xFFFF; + mmxreg1[16,16] = zext(mmxreg1[16,16] s> mmxreg2[16,16]) * 0xFFFF; + mmxreg1[32,16] = zext(mmxreg1[32,16] s> mmxreg2[32,16]) * 0xFFFF; + mmxreg1[48,16] = zext(mmxreg1[48,16] s> mmxreg2[48,16]) * 0xFFFF; +} + +:PCMPGTD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x66; mmxreg ... & m64 +{ + local m:8 = m64; + mmxreg[0,32] = zext(mmxreg[0,32] s> m[0,32]) * 0xFFFFFFFF; + mmxreg[32,32] = zext(mmxreg[32,32] s> m[32,32]) * 0xFFFFFFFF; +} + +:PCMPGTD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x66; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + mmxreg1[0,32] = zext(mmxreg1[0,32] s> mmxreg2[0,32]) * 0xFFFFFFFF; + mmxreg1[32,32] = zext(mmxreg1[32,32] s> mmxreg2[32,32]) * 0xFFFFFFFF; +} + +:PCMPGTB XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x64; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,8] = (XmmReg[0,8] s> m[0,8]) * 0xFF; + XmmReg[8,8] = (XmmReg[8,8] s> m[8,8]) * 0xFF; + XmmReg[16,8] = (XmmReg[16,8] s> m[16,8]) * 0xFF; + XmmReg[24,8] = (XmmReg[24,8] s> m[24,8]) * 0xFF; + XmmReg[32,8] = (XmmReg[32,8] s> m[32,8]) * 0xFF; + XmmReg[40,8] = (XmmReg[40,8] s> m[40,8]) * 0xFF; + XmmReg[48,8] = (XmmReg[48,8] s> m[48,8]) * 0xFF; + XmmReg[56,8] = (XmmReg[56,8] s> m[56,8]) * 0xFF; + XmmReg[64,8] = (XmmReg[64,8] s> m[64,8]) * 0xFF; + XmmReg[72,8] = (XmmReg[72,8] s> m[72,8]) * 0xFF; + XmmReg[80,8] = (XmmReg[80,8] s> m[80,8]) * 0xFF; + XmmReg[88,8] = (XmmReg[88,8] s> m[88,8]) * 0xFF; + XmmReg[96,8] = (XmmReg[96,8] s> m[96,8]) * 0xFF; + XmmReg[104,8] = (XmmReg[104,8] s> m[104,8]) * 0xFF; + XmmReg[112,8] = (XmmReg[112,8] s> m[112,8]) * 0xFF; + XmmReg[120,8] = (XmmReg[120,8] s> m[120,8]) * 0xFF; +} + +# full set of XMM byte registers +:PCMPGTB XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x64; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,8] = (XmmReg1[0,8] s> XmmReg2[0,8]) * 0xFF; + XmmReg1[8,8] = (XmmReg1[8,8] s> XmmReg2[8,8]) * 0xFF; + XmmReg1[16,8] = (XmmReg1[16,8] s> XmmReg2[16,8]) * 0xFF; + XmmReg1[24,8] = (XmmReg1[24,8] s> XmmReg2[24,8]) * 0xFF; + XmmReg1[32,8] = (XmmReg1[32,8] s> XmmReg2[32,8]) * 0xFF; + XmmReg1[40,8] = (XmmReg1[40,8] s> XmmReg2[40,8]) * 0xFF; + XmmReg1[48,8] = (XmmReg1[48,8] s> XmmReg2[48,8]) * 0xFF; + XmmReg1[56,8] = (XmmReg1[56,8] s> XmmReg2[56,8]) * 0xFF; + XmmReg1[64,8] = (XmmReg1[64,8] s> XmmReg2[64,8]) * 0xFF; + XmmReg1[72,8] = (XmmReg1[72,8] s> XmmReg2[72,8]) * 0xFF; + XmmReg1[80,8] = (XmmReg1[80,8] s> XmmReg2[80,8]) * 0xFF; + XmmReg1[88,8] = (XmmReg1[88,8] s> XmmReg2[88,8]) * 0xFF; + XmmReg1[96,8] = (XmmReg1[96,8] s> XmmReg2[96,8]) * 0xFF; + XmmReg1[104,8] = (XmmReg1[104,8] s> XmmReg2[104,8]) * 0xFF; + XmmReg1[112,8] = (XmmReg1[112,8] s> XmmReg2[112,8]) * 0xFF; + XmmReg1[120,8] = (XmmReg1[120,8] s> XmmReg2[120,8]) * 0xFF; +} + +:PCMPGTW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x65; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,16] = zext(XmmReg[0,16] s> m[0,16]) * 0xFFFF; + XmmReg[16,16] = zext(XmmReg[16,16] s> m[16,16]) * 0xFFFF; + XmmReg[32,16] = zext(XmmReg[32,16] s> m[32,16]) * 0xFFFF; + XmmReg[48,16] = zext(XmmReg[48,16] s> m[48,16]) * 0xFFFF; + XmmReg[64,16] = zext(XmmReg[64,16] s> m[64,16]) * 0xFFFF; + XmmReg[80,16] = zext(XmmReg[80,16] s> m[80,16]) * 0xFFFF; + XmmReg[96,16] = zext(XmmReg[96,16] s> m[96,16]) * 0xFFFF; + XmmReg[112,16] = zext(XmmReg[112,16] s> m[112,16]) * 0xFFFF; +} + +:PCMPGTW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x65; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,16] = zext(XmmReg1[0,16] s> XmmReg2[0,16]) * 0xFFFF; + XmmReg1[16,16] = zext(XmmReg1[16,16] s> XmmReg2[16,16]) * 0xFFFF; + XmmReg1[32,16] = zext(XmmReg1[32,16] s> XmmReg2[32,16]) * 0xFFFF; + XmmReg1[48,16] = zext(XmmReg1[48,16] s> XmmReg2[48,16]) * 0xFFFF; + XmmReg1[64,16] = zext(XmmReg1[64,16] s> XmmReg2[64,16]) * 0xFFFF; + XmmReg1[80,16] = zext(XmmReg1[80,16] s> XmmReg2[80,16]) * 0xFFFF; + XmmReg1[96,16] = zext(XmmReg1[96,16] s> XmmReg2[96,16]) * 0xFFFF; + XmmReg1[112,16] = zext(XmmReg1[112,16] s> XmmReg2[112,16]) * 0xFFFF; +} + +:PCMPGTD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x66; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,32] = zext(XmmReg[0,32] s> m[0,32]) * 0xFFFFFFFF; + XmmReg[32,32] = zext(XmmReg[32,32] s> m[32,32]) * 0xFFFFFFFF; + XmmReg[64,32] = zext(XmmReg[64,32] s> m[64,32]) * 0xFFFFFFFF; + XmmReg[96,32] = zext(XmmReg[96,32] s> m[96,32]) * 0xFFFFFFFF; +} + +:PCMPGTD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x66; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = zext(XmmReg1[0,32] s> XmmReg2[0,32]) * 0xFFFFFFFF; + XmmReg1[32,32] = zext(XmmReg1[32,32] s> XmmReg2[32,32]) * 0xFFFFFFFF; + XmmReg1[64,32] = zext(XmmReg1[64,32] s> XmmReg2[64,32]) * 0xFFFFFFFF; + XmmReg1[96,32] = zext(XmmReg1[96,32] s> XmmReg2[96,32]) * 0xFFFFFFFF; +} + +:PEXTRW Reg32, mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xC5; Reg32 & check_Reg32_dest & mmxreg2; imm8 +{ + temp:8 = mmxreg2 >> ( (imm8 & 0x03) * 16 ); + Reg32 = zext(temp:2); + build check_Reg32_dest; +} + +:PEXTRW Reg32, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xC5; Reg32 & XmmReg2 & check_Reg32_dest; imm8 +{ + local shift:1 = (imm8 & 0x7) * 16:1; + local low:1 = shift < 64:1; + local temp:8; + conditionalAssign(temp,low,XmmReg2[0,64] >> shift, XmmReg2[64,64] >> (shift-64)); + Reg32 = zext(temp:2); + build check_Reg32_dest; +} + +#break PEXTRW with reg/mem dest into two constructors to handle zext in register case +:PEXTRW Rmr32, XmmReg1, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x15; (mod = 3 & Rmr32 & check_Rmr32_dest) & XmmReg1 ; imm8 +{ + local shift:1 = (imm8 & 0x7) * 16:1; + local low:1 = shift < 64:1; + local temp:8; + conditionalAssign(temp,low,XmmReg1[0,64] >> shift,XmmReg1[64,64] >> (shift - 64)); + Rmr32 = zext(temp:2); + build check_Rmr32_dest; +} + +:PEXTRW m16, XmmReg1, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x15; XmmReg1 ... & m16; imm8 +{ + local shift:1 = (imm8 & 0x7) * 16:1; + local low:1 = shift < 64:1; + local temp:8; + conditionalAssign(temp,low,XmmReg1[0,64] >> shift,XmmReg1[64,64] >> (shift - 64)); + m16 = temp:2; +} + +define pcodeop phaddd; +:PHADDD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x02; mmxreg ... & m64 { mmxreg=phaddd(mmxreg,m64); } +:PHADDD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x02; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=phaddd(mmxreg1,mmxreg2); } +:PHADDD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x02; XmmReg ... & m128 { XmmReg=phaddd(XmmReg,m128); } +:PHADDD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x02; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=phaddd(XmmReg1,XmmReg2); } + +define pcodeop phaddw; +:PHADDW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x01; mmxreg ... & m64 { mmxreg=phaddw(mmxreg,m64); } +:PHADDW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x01; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=phaddw(mmxreg1,mmxreg2); } +:PHADDW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x01; XmmReg ... & m128 { XmmReg=phaddw(XmmReg,m128); } +:PHADDW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x01; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=phaddw(XmmReg1,XmmReg2); } + +define pcodeop phaddsw; +:PHADDSW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x03; mmxreg ... & m64 { mmxreg=phaddsw(mmxreg,m64); } +:PHADDSW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x03; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=phaddsw(mmxreg1,mmxreg2); } +:PHADDSW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x03; XmmReg ... & m128 { XmmReg=phaddsw(XmmReg,m128); } +:PHADDSW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x03; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=phaddsw(XmmReg1,XmmReg2); } + +define pcodeop phsubd; +:PHSUBD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x06; mmxreg ... & m64 { mmxreg=phsubd(mmxreg,m64); } +:PHSUBD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x06; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=phsubd(mmxreg1,mmxreg2); } +:PHSUBD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x06; XmmReg ... & m128 { XmmReg=phsubd(XmmReg,m128); } +:PHSUBD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x06; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=phsubd(XmmReg1,XmmReg2); } + +define pcodeop phsubw; +:PHSUBW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x05; mmxreg ... & m64 { mmxreg=phsubw(mmxreg,m64); } +:PHSUBW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x05; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=phsubw(mmxreg1,mmxreg2); } +:PHSUBW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x05; XmmReg ... & m128 { XmmReg=phsubw(XmmReg,m128); } +:PHSUBW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x05; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=phsubw(XmmReg1,XmmReg2); } + +define pcodeop phsubsw; +:PHSUBSW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x07; mmxreg ... & m64 { mmxreg=phsubsw(mmxreg,m64); } +:PHSUBSW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x07; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=phsubsw(mmxreg1,mmxreg2); } +:PHSUBSW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x07; XmmReg ... & m128 { XmmReg=phsubsw(XmmReg,m128); } +:PHSUBSW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x07; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=phsubsw(XmmReg1,XmmReg2); } + +:PINSRW mmxreg, Rmr32, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xC4; mmxmod=3 & Rmr32 & mmxreg; imm8 +{ + local destIndex:1 = (imm8 & 0x7) * 16:1; + mmxreg = mmxreg & ~(0xffff:8 << destIndex); + local newVal:8 = zext(Rmr32[0,16]); + mmxreg = mmxreg | (newVal << destIndex); +} + +:PINSRW mmxreg, m16, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xC4; m16 & mmxreg ... ; imm8 +{ + local destIndex:1 = (imm8 & 0x7) * 16:1; + mmxreg = mmxreg & ~(0xffff:8 << destIndex); + local newVal:8 = zext(m16); + mmxreg = mmxreg | (newVal << destIndex); +} + +:PINSRW XmmReg, Rmr32, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xC4; xmmmod=3 & Rmr32 & XmmReg; imm8 +{ + local destIndex:1 = (imm8 & 0x7) * 16:1; + local useLow:1 = destIndex < 64:1; + local newLow:8 = zext(Rmr32:2) << destIndex; + newLow = (XmmReg[0,64] & ~(0xffff:8 << destIndex)) | newLow; + local newHigh:8 = zext(Rmr32:2) << (destIndex-64:1); + newHigh = (XmmReg[64,64] & ~(0xffff:8 << (destIndex - 64:1))) | newHigh; + conditionalAssign(XmmReg[0,64],useLow,newLow,XmmReg[0,64]); + conditionalAssign(XmmReg[64,64],!useLow,newHigh,XmmReg[64,64]); +} + +:PINSRW XmmReg, m16, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xC4; m16 & XmmReg ...; imm8 +{ + local destIndex:1 = (imm8 & 0x7) * 16:1; + local useLow:1 = destIndex < 64:1; + local newLow:8 = zext(m16) << destIndex; + newLow = (XmmReg[0,64] & ~(0xffff:8 << destIndex)) | newLow; + local newHigh:8 = zext(m16) << (destIndex-64:1); + newHigh = (XmmReg[64,64] & ~(0xffff:8 << (destIndex - 64:1))) | newHigh; + conditionalAssign(XmmReg[0,64],useLow,newLow,XmmReg[0,64]); + conditionalAssign(XmmReg[64,64],!useLow,newHigh,XmmReg[64,64]); +} + +define pcodeop pmaddubsw; +:PMADDUBSW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x04; mmxreg ... & m64 { mmxreg=pmaddubsw(mmxreg,m64); } +:PMADDUBSW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x04; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=pmaddubsw(mmxreg1,mmxreg2); } +:PMADDUBSW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x04; XmmReg ... & m128 { XmmReg=pmaddubsw(XmmReg,m128); } +:PMADDUBSW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x04; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=pmaddubsw(XmmReg1,XmmReg2); } + +define pcodeop pmaddwd; +:PMADDWD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF5; mmxreg ... & m64 { mmxreg = pmaddwd(mmxreg, m64); } +:PMADDWD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF5; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = pmaddwd(mmxreg1, mmxreg2); } +:PMADDWD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF5; XmmReg ... & m128 { XmmReg = pmaddwd(XmmReg, m128); } +:PMADDWD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF5; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = pmaddwd(XmmReg1, XmmReg2); } + +:PMAXSW mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xEE; mmxreg1 ... & mmxreg2_m64 +{ + local srcCopy:8 = mmxreg2_m64; + conditionalAssign(mmxreg1[0,16],srcCopy[0,16] s> mmxreg1[0,16],srcCopy[0,16],mmxreg1[0,16]); + conditionalAssign(mmxreg1[16,16],srcCopy[16,16] s> mmxreg1[16,16],srcCopy[16,16],mmxreg1[16,16]); + conditionalAssign(mmxreg1[32,16],srcCopy[32,16] s> mmxreg1[32,16],srcCopy[32,16],mmxreg1[32,16]); + conditionalAssign(mmxreg1[48,16],srcCopy[48,16] s> mmxreg1[48,16],srcCopy[48,16],mmxreg1[48,16]); +} + +:PMAXSW XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xEE; XmmReg1 ... & XmmReg2_m128 +{ + local srcCopy:16 = XmmReg2_m128; + conditionalAssign(XmmReg1[0,16],srcCopy[0,16] s> XmmReg1[0,16],srcCopy[0,16],XmmReg1[0,16]); + conditionalAssign(XmmReg1[16,16],srcCopy[16,16] s> XmmReg1[16,16],srcCopy[16,16],XmmReg1[16,16]); + conditionalAssign(XmmReg1[32,16],srcCopy[32,16] s> XmmReg1[32,16],srcCopy[32,16],XmmReg1[32,16]); + conditionalAssign(XmmReg1[48,16],srcCopy[48,16] s> XmmReg1[48,16],srcCopy[48,16],XmmReg1[48,16]); + conditionalAssign(XmmReg1[64,16],srcCopy[64,16] s> XmmReg1[64,16],srcCopy[64,16],XmmReg1[64,16]); + conditionalAssign(XmmReg1[80,16],srcCopy[80,16] s> XmmReg1[80,16],srcCopy[80,16],XmmReg1[80,16]); + conditionalAssign(XmmReg1[96,16],srcCopy[96,16] s> XmmReg1[96,16],srcCopy[96,16],XmmReg1[96,16]); + conditionalAssign(XmmReg1[112,16],srcCopy[112,16] s> XmmReg1[112,16],srcCopy[112,16],XmmReg1[112,16]); +} + +:PMAXUB mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xDE; mmxreg1 ... & mmxreg2_m64 +{ + local srcCopy:8 = mmxreg2_m64; + conditionalAssign(mmxreg1[0,8],srcCopy[0,8] > mmxreg1[0,8],srcCopy[0,8],mmxreg1[0,8]); + conditionalAssign(mmxreg1[8,8],srcCopy[8,8] > mmxreg1[8,8],srcCopy[8,8],mmxreg1[8,8]); + conditionalAssign(mmxreg1[16,8],srcCopy[16,8] > mmxreg1[16,8],srcCopy[16,8],mmxreg1[16,8]); + conditionalAssign(mmxreg1[24,8],srcCopy[24,8] > mmxreg1[24,8],srcCopy[24,8],mmxreg1[24,8]); + conditionalAssign(mmxreg1[32,8],srcCopy[32,8] > mmxreg1[32,8],srcCopy[32,8],mmxreg1[32,8]); + conditionalAssign(mmxreg1[40,8],srcCopy[40,8] > mmxreg1[40,8],srcCopy[40,8],mmxreg1[40,8]); + conditionalAssign(mmxreg1[48,8],srcCopy[48,8] > mmxreg1[48,8],srcCopy[48,8],mmxreg1[48,8]); + conditionalAssign(mmxreg1[56,8],srcCopy[56,8] > mmxreg1[56,8],srcCopy[56,8],mmxreg1[56,8]); +} + +:PMAXUB XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xDE; XmmReg1 ... & XmmReg2_m128 +{ + local srcCopy:16 = XmmReg2_m128; + conditionalAssign(XmmReg1[0,8],srcCopy[0,8] > XmmReg1[0,8],srcCopy[0,8],XmmReg1[0,8]); + conditionalAssign(XmmReg1[8,8],srcCopy[8,8] > XmmReg1[8,8],srcCopy[8,8],XmmReg1[8,8]); + conditionalAssign(XmmReg1[16,8],srcCopy[16,8] > XmmReg1[16,8],srcCopy[16,8],XmmReg1[16,8]); + conditionalAssign(XmmReg1[24,8],srcCopy[24,8] > XmmReg1[24,8],srcCopy[24,8],XmmReg1[24,8]); + conditionalAssign(XmmReg1[32,8],srcCopy[32,8] > XmmReg1[32,8],srcCopy[32,8],XmmReg1[32,8]); + conditionalAssign(XmmReg1[40,8],srcCopy[40,8] > XmmReg1[40,8],srcCopy[40,8],XmmReg1[40,8]); + conditionalAssign(XmmReg1[48,8],srcCopy[48,8] > XmmReg1[48,8],srcCopy[48,8],XmmReg1[48,8]); + conditionalAssign(XmmReg1[56,8],srcCopy[56,8] > XmmReg1[56,8],srcCopy[56,8],XmmReg1[56,8]); + conditionalAssign(XmmReg1[64,8],srcCopy[64,8] > XmmReg1[64,8],srcCopy[64,8],XmmReg1[64,8]); + conditionalAssign(XmmReg1[72,8],srcCopy[72,8] > XmmReg1[72,8],srcCopy[72,8],XmmReg1[72,8]); + conditionalAssign(XmmReg1[80,8],srcCopy[80,8] > XmmReg1[80,8],srcCopy[80,8],XmmReg1[80,8]); + conditionalAssign(XmmReg1[88,8],srcCopy[88,8] > XmmReg1[88,8],srcCopy[88,8],XmmReg1[88,8]); + conditionalAssign(XmmReg1[96,8],srcCopy[96,8] > XmmReg1[96,8],srcCopy[96,8],XmmReg1[96,8]); + conditionalAssign(XmmReg1[104,8],srcCopy[104,8] > XmmReg1[104,8],srcCopy[104,8],XmmReg1[104,8]); + conditionalAssign(XmmReg1[112,8],srcCopy[112,8] > XmmReg1[112,8],srcCopy[112,8],XmmReg1[112,8]); + conditionalAssign(XmmReg1[120,8],srcCopy[120,8] > XmmReg1[120,8],srcCopy[120,8],XmmReg1[120,8]); +} + +:PMINSW mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xEA; mmxreg1 ... & mmxreg2_m64 +{ + local srcCopy:8 = mmxreg2_m64; + conditionalAssign(mmxreg1[0,16],srcCopy[0,16] s< mmxreg1[0,16],srcCopy[0,16],mmxreg1[0,16]); + conditionalAssign(mmxreg1[16,16],srcCopy[16,16] s< mmxreg1[16,16],srcCopy[16,16],mmxreg1[16,16]); + conditionalAssign(mmxreg1[32,16],srcCopy[32,16] s< mmxreg1[32,16],srcCopy[32,16],mmxreg1[32,16]); + conditionalAssign(mmxreg1[48,16],srcCopy[48,16] s< mmxreg1[48,16],srcCopy[48,16],mmxreg1[48,16]); +} + +:PMINSW XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xEA; XmmReg1 ... & XmmReg2_m128 +{ + local srcCopy:16 = XmmReg2_m128; + conditionalAssign(XmmReg1[0,16],srcCopy[0,16] s< XmmReg1[0,16],srcCopy[0,16],XmmReg1[0,16]); + conditionalAssign(XmmReg1[16,16],srcCopy[16,16] s< XmmReg1[16,16],srcCopy[16,16],XmmReg1[16,16]); + conditionalAssign(XmmReg1[32,16],srcCopy[32,16] s< XmmReg1[32,16],srcCopy[32,16],XmmReg1[32,16]); + conditionalAssign(XmmReg1[48,16],srcCopy[48,16] s< XmmReg1[48,16],srcCopy[48,16],XmmReg1[48,16]); + conditionalAssign(XmmReg1[64,16],srcCopy[64,16] s< XmmReg1[64,16],srcCopy[64,16],XmmReg1[64,16]); + conditionalAssign(XmmReg1[80,16],srcCopy[80,16] s< XmmReg1[80,16],srcCopy[80,16],XmmReg1[80,16]); + conditionalAssign(XmmReg1[96,16],srcCopy[96,16] s< XmmReg1[96,16],srcCopy[96,16],XmmReg1[96,16]); + conditionalAssign(XmmReg1[112,16],srcCopy[112,16] s< XmmReg1[112,16],srcCopy[112,16],XmmReg1[112,16]); +} + +:PMINUB mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xDA; mmxreg1 ... & mmxreg2_m64 +{ + local srcCopy:8 = mmxreg2_m64; + conditionalAssign(mmxreg1[0,8],srcCopy[0,8] < mmxreg1[0,8],srcCopy[0,8],mmxreg1[0,8]); + conditionalAssign(mmxreg1[8,8],srcCopy[8,8] < mmxreg1[8,8],srcCopy[8,8],mmxreg1[8,8]); + conditionalAssign(mmxreg1[16,8],srcCopy[16,8] < mmxreg1[16,8],srcCopy[16,8],mmxreg1[16,8]); + conditionalAssign(mmxreg1[24,8],srcCopy[24,8] < mmxreg1[24,8],srcCopy[24,8],mmxreg1[24,8]); + conditionalAssign(mmxreg1[32,8],srcCopy[32,8] < mmxreg1[32,8],srcCopy[32,8],mmxreg1[32,8]); + conditionalAssign(mmxreg1[40,8],srcCopy[40,8] < mmxreg1[40,8],srcCopy[40,8],mmxreg1[40,8]); + conditionalAssign(mmxreg1[48,8],srcCopy[48,8] < mmxreg1[48,8],srcCopy[48,8],mmxreg1[48,8]); + conditionalAssign(mmxreg1[56,8],srcCopy[56,8] < mmxreg1[56,8],srcCopy[56,8],mmxreg1[56,8]); +} + +:PMINUB XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xDA; XmmReg1 ... & XmmReg2_m128 +{ + local srcCopy:16 = XmmReg2_m128; + conditionalAssign(XmmReg1[0,8],srcCopy[0,8] < XmmReg1[0,8],srcCopy[0,8],XmmReg1[0,8]); + conditionalAssign(XmmReg1[8,8],srcCopy[8,8] < XmmReg1[8,8],srcCopy[8,8],XmmReg1[8,8]); + conditionalAssign(XmmReg1[16,8],srcCopy[16,8] < XmmReg1[16,8],srcCopy[16,8],XmmReg1[16,8]); + conditionalAssign(XmmReg1[24,8],srcCopy[24,8] < XmmReg1[24,8],srcCopy[24,8],XmmReg1[24,8]); + conditionalAssign(XmmReg1[32,8],srcCopy[32,8] < XmmReg1[32,8],srcCopy[32,8],XmmReg1[32,8]); + conditionalAssign(XmmReg1[40,8],srcCopy[40,8] < XmmReg1[40,8],srcCopy[40,8],XmmReg1[40,8]); + conditionalAssign(XmmReg1[48,8],srcCopy[48,8] < XmmReg1[48,8],srcCopy[48,8],XmmReg1[48,8]); + conditionalAssign(XmmReg1[56,8],srcCopy[56,8] < XmmReg1[56,8],srcCopy[56,8],XmmReg1[56,8]); + conditionalAssign(XmmReg1[64,8],srcCopy[64,8] < XmmReg1[64,8],srcCopy[64,8],XmmReg1[64,8]); + conditionalAssign(XmmReg1[72,8],srcCopy[72,8] < XmmReg1[72,8],srcCopy[72,8],XmmReg1[72,8]); + conditionalAssign(XmmReg1[80,8],srcCopy[80,8] < XmmReg1[80,8],srcCopy[80,8],XmmReg1[80,8]); + conditionalAssign(XmmReg1[88,8],srcCopy[88,8] < XmmReg1[88,8],srcCopy[88,8],XmmReg1[88,8]); + conditionalAssign(XmmReg1[96,8],srcCopy[96,8] < XmmReg1[96,8],srcCopy[96,8],XmmReg1[96,8]); + conditionalAssign(XmmReg1[104,8],srcCopy[104,8] < XmmReg1[104,8],srcCopy[104,8],XmmReg1[104,8]); + conditionalAssign(XmmReg1[112,8],srcCopy[112,8] < XmmReg1[112,8],srcCopy[112,8],XmmReg1[112,8]); + conditionalAssign(XmmReg1[120,8],srcCopy[120,8] < XmmReg1[120,8],srcCopy[120,8],XmmReg1[120,8]); +} + +#in 64-bit mode the default operand size is 64 bits +#note that gcc assembles pmovmskb eax, mm0 and pmovmskb rax, mm0 to 0f d7 c0 +:PMOVMSKB Reg32, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD7; mod = 3 & Reg32 & mmxreg2 & check_Reg32_dest +{ + local byte_mask:1 = 0:1; + byte_mask[0,1] = mmxreg2[7,1]; + byte_mask[1,1] = mmxreg2[15,1]; + byte_mask[2,1] = mmxreg2[23,1]; + byte_mask[3,1] = mmxreg2[31,1]; + byte_mask[4,1] = mmxreg2[39,1]; + byte_mask[5,1] = mmxreg2[47,1]; + byte_mask[6,1] = mmxreg2[55,1]; + byte_mask[7,1] = mmxreg2[63,1]; + Reg32 = zext(byte_mask); + build check_Reg32_dest; +} + +#in 64-bit mode the default operand size is 64 bits +#note that gcc assembles pmovmskb eax, xmm0 and pmovmskb rax, xmm0 to 66 0f d7 c0 +:PMOVMSKB Reg32, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD7; mod = 3 & Reg32 & XmmReg2 & check_Reg32_dest +{ + local byte_mask:2 = 0:2; + byte_mask[0,1] = XmmReg2[7,1]; + byte_mask[1,1] = XmmReg2[15,1]; + byte_mask[2,1] = XmmReg2[23,1]; + byte_mask[3,1] = XmmReg2[31,1]; + byte_mask[4,1] = XmmReg2[39,1]; + byte_mask[5,1] = XmmReg2[47,1]; + byte_mask[6,1] = XmmReg2[55,1]; + byte_mask[7,1] = XmmReg2[63,1]; + byte_mask[8,1] = XmmReg2[71,1]; + byte_mask[9,1] = XmmReg2[79,1]; + byte_mask[10,1] = XmmReg2[87,1]; + byte_mask[11,1] = XmmReg2[95,1]; + byte_mask[12,1] = XmmReg2[103,1]; + byte_mask[13,1] = XmmReg2[111,1]; + byte_mask[14,1] = XmmReg2[119,1]; + byte_mask[15,1] = XmmReg2[127,1]; + Reg32 = zext(byte_mask); + build check_Reg32_dest; +} + +define pcodeop pmulhrsw; +:PMULHRSW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x0B; mmxreg ... & m64 { mmxreg=pmulhrsw(mmxreg,m64); } +:PMULHRSW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x0B; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=pmulhrsw(mmxreg1,mmxreg2); } +:PMULHRSW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x0B; XmmReg ... & m128 { XmmReg=pmulhrsw(XmmReg,m128); } +:PMULHRSW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x0B; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=pmulhrsw(XmmReg1,XmmReg2); } + +define pcodeop pmulhuw; +:PMULHUW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE4; mmxreg ... & m64 { mmxreg = pmulhuw(mmxreg, m64); } +:PMULHUW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE4; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = pmulhuw(mmxreg1, mmxreg2); } +:PMULHUW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE4; XmmReg ... & m128 { XmmReg = pmulhuw(XmmReg, m128); } +:PMULHUW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE4; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = pmulhuw(XmmReg1, XmmReg2); } + +macro pmulhw64(mmx1, mmx2) { + local tmp0:8 = sext(mmx1[ 0,16]) * sext(mmx2[ 0,16]); + mmx1[ 0,16] = tmp0[16,16]; + local tmp1:8 = sext(mmx1[16,16]) * sext(mmx2[16,16]); + mmx1[16,16] = tmp1[16,16]; + local tmp2:8 = sext(mmx1[32,16]) * sext(mmx2[32,16]); + mmx1[32,16] = tmp2[16,16]; + local tmp3:8 = sext(mmx1[48,16]) * sext(mmx2[48,16]); + mmx1[48,16] = tmp3[16,16]; +} +:PMULHW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE5; mmxreg ... & m64 { pmulhw64(mmxreg, m64); } +:PMULHW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE5; mmxmod = 3 & mmxreg1 & mmxreg2 { pmulhw64(mmxreg1, mmxreg2); } + +macro pmulhw128(xmm1, xmm2) { + local tmp0:8 = sext(xmm1[ 0,16]) * sext(xmm2[ 0,16]); + xmm1[ 0,16] = tmp0[16,16]; + local tmp1:8 = sext(xmm1[ 16,16]) * sext(xmm2[ 16,16]); + xmm1[ 16,16] = tmp1[16,16]; + local tmp2:8 = sext(xmm1[ 32,16]) * sext(xmm2[ 32,16]); + xmm1[ 32,16] = tmp2[16,16]; + local tmp3:8 = sext(xmm1[ 48,16]) * sext(xmm2[ 48,16]); + xmm1[ 48,16] = tmp3[16,16]; + local tmp4:8 = sext(xmm1[ 64,16]) * sext(xmm2[ 64,16]); + xmm1[ 64,16] = tmp4[16,16]; + local tmp5:8 = sext(xmm1[ 80,16]) * sext(xmm2[ 80,16]); + xmm1[ 80,16] = tmp5[16,16]; + local tmp6:8 = sext(xmm1[ 96,16]) * sext(xmm2[ 96,16]); + xmm1[ 96,16] = tmp6[16,16]; + local tmp7:8 = sext(xmm1[112,16]) * sext(xmm2[112,16]); + xmm1[112,16] = tmp7[16,16]; +} +:PMULHW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE5; XmmReg ... & m128 { pmulhw128(XmmReg, m128); } +:PMULHW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE5; xmmmod = 3 & XmmReg1 & XmmReg2 { pmulhw128(XmmReg1, XmmReg2); } + +:PMULLW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD5; mmxreg ... & m64 { + local m:8 = m64; + mmxreg[0,16] = mmxreg[0,16] * m[0,16]; + mmxreg[16,16] = mmxreg[16,16] * m[16,16]; + mmxreg[32,16] = mmxreg[32,16] * m[32,16]; + mmxreg[48,16] = mmxreg[48,16] * m[48,16]; +} + +:PMULLW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD5; mmxmod = 3 & mmxreg1 & mmxreg2 { + mmxreg1[0,16] = mmxreg1[0,16] * mmxreg2[0,16]; + mmxreg1[16,16] = mmxreg1[16,16] * mmxreg2[16,16]; + mmxreg1[32,16] = mmxreg1[32,16] * mmxreg2[32,16]; + mmxreg1[48,16] = mmxreg1[48,16] * mmxreg2[48,16]; +} + +:PMULLW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD5; XmmReg ... & m128 { + local m:16 = m128; + XmmReg[0,16] = XmmReg[0,16] * m[0,16]; + XmmReg[16,16] = XmmReg[16,16] * m[16,16]; + XmmReg[32,16] = XmmReg[32,16] * m[32,16]; + XmmReg[48,16] = XmmReg[48,16] * m[48,16]; + XmmReg[64,16] = XmmReg[64,16] * m[64,16]; + XmmReg[80,16] = XmmReg[80,16] * m[80,16]; + XmmReg[96,16] = XmmReg[96,16] * m[96,16]; + XmmReg[112,16] = XmmReg[112,16] * m[112,16]; +} + +:PMULLW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD5; xmmmod = 3 & XmmReg1 & XmmReg2 { + XmmReg1[0,16] = XmmReg1[0,16] * XmmReg2[0,16]; + XmmReg1[16,16] = XmmReg1[16,16] * XmmReg2[16,16]; + XmmReg1[32,16] = XmmReg1[32,16] * XmmReg2[32,16]; + XmmReg1[48,16] = XmmReg1[48,16] * XmmReg2[48,16]; + XmmReg1[64,16] = XmmReg1[64,16] * XmmReg2[64,16]; + XmmReg1[80,16] = XmmReg1[80,16] * XmmReg2[80,16]; + XmmReg1[96,16] = XmmReg1[96,16] * XmmReg2[96,16]; + XmmReg1[112,16] = XmmReg1[112,16] * XmmReg2[112,16]; + } + +:PMULUDQ mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF4; mmxreg ... & m64 +{ + local a:8 = zext(mmxreg[0,32]); + local b:8 = zext(m64[0,32]); + mmxreg = a * b; +} + +:PMULUDQ mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF4; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + local a:8 = zext(mmxreg1[0,32]); + local b:8 = zext(mmxreg2[0,32]); + mmxreg1 = a * b; +} + +:PMULUDQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF4; XmmReg ... & m128 +{ + local a:8 = zext(XmmReg[0,32]); + local b:8 = zext(m128[0,32]); + XmmReg[0,64] = a * b; + local c:8 = zext(XmmReg[64,32]); + local d:8 = zext(m128[64,32]); + XmmReg[64,64] = c * d; +} + +:PMULUDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF4; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + local a:8 = zext(XmmReg1[0,32]); + local b:8 = zext(XmmReg2[0,32]); + XmmReg1[0,64] = a * b; + local c:8 = zext(XmmReg1[64,32]); + local d:8 = zext(XmmReg2[64,32]); + XmmReg1[64,64] = c * d; +} + +:POR mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xEB; mmxreg ... & m64 { mmxreg = mmxreg | m64; } +:POR mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xEB; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = mmxreg1 | mmxreg2; } +:POR XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xEB; XmmReg ... & m128 { XmmReg = XmmReg | m128; } +:POR XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xEB; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = XmmReg1 | XmmReg2; } + +define pcodeop psadbw; +:PSADBW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF6; mmxreg ... & m64 { mmxreg = psadbw(mmxreg, m64); } +:PSADBW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF6; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = psadbw(mmxreg1, mmxreg2); } +:PSADBW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF6; XmmReg ... & m128 { XmmReg = psadbw(XmmReg, m128); } +:PSADBW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF6; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = psadbw(XmmReg1, XmmReg2); } + +# these byte and word shuffles need to be done also ????? +define pcodeop pshufb; +:PSHUFB mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x00; mmxreg1 ... & mmxreg2_m64 { mmxreg1=pshufb(mmxreg1,mmxreg2_m64); } +:PSHUFB XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x00; XmmReg1 ... & XmmReg2_m128 { XmmReg1=pshufb(XmmReg1,XmmReg2_m128); } + +# determine the total shift required by the bit fields in a shuffle opcode +Order0: order0 is imm8 [ order0 = ( imm8 & 0x3); ] { export *[const]:1 order0; } +Order1: order1 is imm8 [ order1 = ((imm8 >> 2) & 0x3); ] { export *[const]:1 order1; } +Order2: order2 is imm8 [ order2 = ((imm8 >> 4) & 0x3); ] { export *[const]:1 order2; } +Order3: order3 is imm8 [ order3 = ((imm8 >> 6) & 0x3); ] { export *[const]:1 order3; } + +macro shuffle_4(dest,ord,c0,c1,c2,c3){ + dest = zext(ord == 0) * c0 + zext(ord == 1) * c1 + zext(ord == 2) * c2 + zext(ord == 3) * c3; +} + +:PSHUFD XmmReg1, XmmReg2_m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x70; (XmmReg2_m128 & XmmReg1 ...); imm8 & Order0 & Order1 & Order2 & Order3 +{ + local c0 = XmmReg2_m128[0,32]; + local c1 = XmmReg2_m128[32,32]; + local c2 = XmmReg2_m128[64,32]; + local c3 = XmmReg2_m128[96,32]; + + shuffle_4(XmmReg1[0,32],Order0,c0,c1,c2,c3); + shuffle_4(XmmReg1[32,32],Order1,c0,c1,c2,c3); + shuffle_4(XmmReg1[64,32],Order2,c0,c1,c2,c3); + shuffle_4(XmmReg1[96,32],Order3,c0,c1,c2,c3); +} + +define pcodeop pshufhw; +:PSHUFHW XmmReg1, XmmReg2_m128, imm8 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x70; XmmReg2_m128 & XmmReg1 ...; imm8 { XmmReg1 = pshufhw(XmmReg1, XmmReg2_m128, imm8:8); } + +define pcodeop pshuflw; +:PSHUFLW XmmReg1, XmmReg2_m128, imm8 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x70; XmmReg2_m128 & XmmReg1 ...; imm8 { XmmReg1 = pshuflw(XmmReg1, XmmReg2_m128, imm8:8); } + +define pcodeop pshufw; +:PSHUFW mmxreg1, mmxreg2_m64, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x70; mmxreg2_m64 & mmxreg1 ...; imm8 { mmxreg1 = pshufw(mmxreg1, mmxreg2_m64, imm8:8); } + +define pcodeop psignb; +:PSIGNB mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x08; mmxreg ... & m64 { mmxreg=psignb(mmxreg,m64); } +:PSIGNB mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x08; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=psignb(mmxreg1,mmxreg2); } +:PSIGNB XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x08; XmmReg ... & m128 { XmmReg=psignb(XmmReg,m128); } +:PSIGNB XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x08; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=psignb(XmmReg1,XmmReg2); } + +define pcodeop psignw; +:PSIGNW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x09; mmxreg ... & m64 { mmxreg=psignw(mmxreg,m64); } +:PSIGNW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x09; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=psignw(mmxreg1,mmxreg2); } +:PSIGNW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x09; XmmReg ... & m128 { XmmReg=psignw(XmmReg,m128); } +:PSIGNW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x09; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=psignw(XmmReg1,XmmReg2); } + +define pcodeop psignd; +:PSIGND mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x0a; mmxreg ... & m64 { mmxreg=psignd(mmxreg,m64); } +:PSIGND mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x38; byte=0x0a; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1=psignd(mmxreg1,mmxreg2); } +:PSIGND XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x0a; XmmReg ... & m128 { XmmReg=psignd(XmmReg,m128); } +:PSIGND XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x0a; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1=psignd(XmmReg1,XmmReg2); } + +#break into two 64-bit chunks so decompiler can follow constants +:PSLLDQ XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x73; xmmmod = 3 & reg_opcode=7 & XmmReg2; imm8 +{ + if (imm8:1 > 15:1) goto ; + local low64copy:8 = XmmReg2[0,64]; + XmmReg2[0,64] = XmmReg2[0,64] << (8:1 * imm8:1); + if (imm8:1 > 8:1) goto ; + XmmReg2[64,64] = (XmmReg2[64,64] << (8:1 * imm8:1)) | (low64copy >> (8:1 * (8 - imm8:1))); + goto ; + + XmmReg2[64,64] = low64copy << (8:1 * (imm8 - 8)); + goto ; + + XmmReg2[0,64] = 0:8; + XmmReg2[64,64] = 0:8; + +} + +macro psllw64(mmx, count) { + local tmp:8 = count; + mmx[ 0,16] = mmx[ 0,16] << tmp; + mmx[16,16] = mmx[16,16] << tmp; + mmx[32,16] = mmx[32,16] << tmp; + mmx[48,16] = mmx[48,16] << tmp; +} +:PSLLW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF1; mmxreg ... & m64 ... { psllw64(mmxreg, m64); } +:PSLLW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF1; mmxmod = 3 & mmxreg1 & mmxreg2 { psllw64(mmxreg1, mmxreg2); } +:PSLLW mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x71; mod = 0b11 & reg_opcode=6 & mmxreg2; imm8 { psllw64(mmxreg2, imm8:8); } + +:PSLLD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF2; mmxreg ... & m64 ... { + local m:8 = m64; + mmxreg[0,32] = mmxreg[0,32] << m[0,32]; + mmxreg[32,32] = mmxreg[32,32] << m[32,32]; +} + +:PSLLD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF2; mmxmod = 3 & mmxreg1 & mmxreg2 { + mmxreg1[0,32] = mmxreg1[0,32] << mmxreg2[0,32]; + mmxreg1[32,32] = mmxreg1[32,32] << mmxreg2[32,32]; +} + +:PSLLD mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x72; mod = 0b11 & reg_opcode=6 & mmxreg2; imm8 { + mmxreg2[0,32] = mmxreg2[0,32] << imm8; + mmxreg2[32,32] = mmxreg2[32,32] << imm8; +} + +:PSLLQ mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF3; mmxreg ... & m64 ... { mmxreg = mmxreg << m64; } +:PSLLQ mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF3; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = mmxreg1 << mmxreg2; } +:PSLLQ mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x73; mod = 0b11 & reg_opcode=6 & mmxreg2; imm8 { mmxreg2 = mmxreg2 << imm8:8; } + +macro psllw128(xmm, count) { + local tmp:8 = count:8; + xmm[ 0,16] = xmm[ 0,16] << tmp; + xmm[ 16,16] = xmm[ 16,16] << tmp; + xmm[ 32,16] = xmm[ 32,16] << tmp; + xmm[ 48,16] = xmm[ 48,16] << tmp; + xmm[ 64,16] = xmm[ 64,16] << tmp; + xmm[ 80,16] = xmm[ 80,16] << tmp; + xmm[ 96,16] = xmm[ 96,16] << tmp; + xmm[112,16] = xmm[112,16] << tmp; +} +:PSLLW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF1; XmmReg ... & m128 ... { psllw128(XmmReg, m128); } +:PSLLW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF1; xmmmod = 3 & XmmReg1 & XmmReg2 { psllw128(XmmReg1, XmmReg2); } +:PSLLW XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x71; mod = 0b11 & reg_opcode=6 & XmmReg2; imm8 { local count:8 = imm8; psllw128(XmmReg2, count); } + +:PSLLD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF2; XmmReg ... & m128 ... { + local m:16 = m128; + XmmReg[0,32] = XmmReg[0,32] << m[0,32]; + XmmReg[32,32] = XmmReg[32,32] << m[32,32]; + XmmReg[64,32] = XmmReg[64,32] << m[64,32]; + XmmReg[96,32] = XmmReg[96,32] << m[96,32]; +} + +:PSLLD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF2; xmmmod = 3 & XmmReg1 & XmmReg2 { + XmmReg1[0,32] = XmmReg1[0,32] << XmmReg2[0,32]; + XmmReg1[32,32] = XmmReg1[32,32] << XmmReg2[32,32]; + XmmReg1[64,32] = XmmReg1[64,32] << XmmReg2[64,32]; + XmmReg1[96,32] = XmmReg1[96,32] << XmmReg2[96,32]; +} + +:PSLLD XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x72; mod = 0b11 & reg_opcode=6 & XmmReg2; imm8 { + XmmReg2[0,32] = XmmReg2[0,32] << imm8; + XmmReg2[32,32] = XmmReg2[32,32] << imm8; + XmmReg2[64,32] = XmmReg2[64,32] << imm8; + XmmReg2[96,32] = XmmReg2[96,32] << imm8; +} + +:PSLLQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF3; XmmReg ... & m128 ... { + local m:16 = m128; + XmmReg[0,64] = XmmReg[0,64] << m[0,64]; + XmmReg[64,64] = XmmReg[64,64] << m[64,64]; +} + +:PSLLQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF3; xmmmod = 3 & XmmReg1 & XmmReg2 { + XmmReg1[0,64] = XmmReg1[0,64] << XmmReg2[0,64]; + XmmReg1[64,64] = XmmReg1[64,64] << XmmReg2[64,64]; +} + +:PSLLQ XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x73; mod = 0b11 & reg_opcode=6 & XmmReg2; imm8 { + XmmReg2[0,64] = XmmReg2[0,64] << imm8; + XmmReg2[64,64] = XmmReg2[64,64] << imm8; +} + +macro psraw64(mmx, count) { + local tmp:8 = count; + mmx[ 0,16] = mmx[ 0,16] s>> tmp; + mmx[16,16] = mmx[16,16] s>> tmp; + mmx[32,16] = mmx[32,16] s>> tmp; + mmx[48,16] = mmx[48,16] s>> tmp; +} +:PSRAW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE1; mmxreg ... & m64 ... { psraw64(mmxreg, m64); } +:PSRAW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE1; mmxmod = 3 & mmxreg1 & mmxreg2 { psraw64(mmxreg1, mmxreg2); } +:PSRAW mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x71; mod = 0b11 & reg_opcode=4 & mmxreg2; imm8 { psraw64(mmxreg2, imm8:8); } + +:PSRAD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE2; mmxreg ... & m64 +{ +# a count greater than 31 just clears all the bits + mmxreg[0,32] = mmxreg[0,32] s>> m64; + mmxreg[32,32] = mmxreg[32,32] s>> m64; +} + +:PSRAD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE2; mmxmod = 3 & mmxreg1 & mmxreg2 +{ +# a count greater than 31 just clears all the bits + mmxreg1[0,32] = mmxreg1[0,32] s>> mmxreg2; + mmxreg1[32,32] = mmxreg1[32,32] s>> mmxreg2; +} + +:PSRAD mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x72; mod = 0b11 & reg_opcode=4 & mmxreg2; imm8 +{ +# a count greater than 31 just clears all the bits + mmxreg2[0,32] = mmxreg2[0,32] s>> imm8; + mmxreg2[32,32] = mmxreg2[32,32] s>> imm8; +} + +macro psraw128(xmm, count) { + local tmp:8 = count:8; + xmm[ 0,16] = xmm[ 0,16] s>> tmp; + xmm[ 16,16] = xmm[ 16,16] s>> tmp; + xmm[ 32,16] = xmm[ 32,16] s>> tmp; + xmm[ 48,16] = xmm[ 48,16] s>> tmp; + xmm[ 64,16] = xmm[ 64,16] s>> tmp; + xmm[ 80,16] = xmm[ 80,16] s>> tmp; + xmm[ 96,16] = xmm[ 96,16] s>> tmp; + xmm[112,16] = xmm[112,16] s>> tmp; +} +:PSRAW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE1; XmmReg ... & m128 ... { psraw128(XmmReg, m128); } +:PSRAW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE1; xmmmod = 3 & XmmReg1 & XmmReg2 { psraw128(XmmReg1, XmmReg2); } +:PSRAW XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x71; mod = 0b11 & reg_opcode=4 & XmmReg2; imm8 { local count:8 = imm8; psraw128(XmmReg2, count); } + +:PSRAD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE2; m128 & XmmReg ... +{ +# a count greater than 31 just clears all the bits + XmmReg[0,32] = XmmReg[0,32] s>> m128; + XmmReg[32,32] = XmmReg[32,32] s>> m128; + XmmReg[64,32] = XmmReg[64,32] s>> m128; + XmmReg[96,32] = XmmReg[96,32] s>> m128; +} + +:PSRAD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE2; xmmmod = 3 & XmmReg1 & XmmReg2 +{ +# a count greater than 31 just clears all the bits + XmmReg1[0,32] = XmmReg1[0,32] s>> XmmReg2; + XmmReg1[32,32] = XmmReg1[32,32] s>> XmmReg2; + XmmReg1[64,32] = XmmReg1[64,32] s>> XmmReg2; + XmmReg1[96,32] = XmmReg1[96,32] s>> XmmReg2; +} + +:PSRAD XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x72; mod = 0b11 & reg_opcode=4 & XmmReg2; imm8 +{ +# a count greater than 31 just clears all the bits + XmmReg2[0,32] = XmmReg2[0,32] s>> imm8; + XmmReg2[32,32] = XmmReg2[32,32] s>> imm8; + XmmReg2[64,32] = XmmReg2[64,32] s>> imm8; + XmmReg2[96,32] = XmmReg2[96,32] s>> imm8; +} + +:PSRLDQ XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x73; xmmmod=3 & reg_opcode=3 & XmmReg2; imm8 +{ +# a count greater than 15 just clears all the bits + XmmReg2 = XmmReg2 >> (imm8 * 8); +} + +:PSRLW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD1; mmxreg ... & m64 ... +{ + mmxreg[0,16] = mmxreg[0,16] >> m64; + mmxreg[16,16] = mmxreg[16,16] >> m64; + mmxreg[32,16] = mmxreg[32,16] >> m64; + mmxreg[48,16] = mmxreg[48,16] >> m64; +} + +:PSRLW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD1; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + mmxreg1[0,16] = mmxreg1[0,16] >> mmxreg2; + mmxreg1[16,16] = mmxreg1[16,16] >> mmxreg2; + mmxreg1[32,16] = mmxreg1[32,16] >> mmxreg2; + mmxreg1[48,16] = mmxreg1[48,16] >> mmxreg2; +} + +:PSRLW mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x71; mod = 0b11 & reg_opcode=2 & mmxreg2; imm8 +{ + mmxreg2[0,16] = mmxreg2[0,16] >> imm8; + mmxreg2[16,16] = mmxreg2[16,16] >> imm8; + mmxreg2[32,16] = mmxreg2[32,16] >> imm8; + mmxreg2[48,16] = mmxreg2[48,16] >> imm8; +} + +:PSRLD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD2; mmxreg ... & m64 ... +{ + mmxreg[0,32] = mmxreg[0,32] >> m64; + mmxreg[32,32] = mmxreg[32,32] >> m64; +} + +:PSRLD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD2; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + mmxreg1[0,32] = mmxreg1[0,32] >> mmxreg2; + mmxreg1[32,32] = mmxreg1[32,32] >> mmxreg2; +} + +:PSRLD mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x72; mod = 0b11 & reg_opcode=2 & mmxreg2; imm8 +{ + mmxreg2[0,32] = mmxreg2[0,32] >> imm8; + mmxreg2[32,32] = mmxreg2[32,32] >> imm8; +} + +:PSRLQ mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD3; mmxreg ... & m64 ... +{ + mmxreg = mmxreg >> m64; + } + +:PSRLQ mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD3; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + mmxreg1 = mmxreg1 >> mmxreg2; +} + +:PSRLQ mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x73; mod = 0b11 & reg_opcode=2 & mmxreg2; imm8 +{ + mmxreg2 = mmxreg2 >> imm8; +} + +:PSRLW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD1; XmmReg ... & m128 ... +{ + XmmReg[0,16] = XmmReg[0,16] >> m128[0,64]; + XmmReg[16,16] = XmmReg[16,16] >> m128[0,64]; + XmmReg[32,16] = XmmReg[32,16] >> m128[0,64]; + XmmReg[48,16] = XmmReg[48,16] >> m128[0,64]; + XmmReg[64,16] = XmmReg[64,16] >> m128[0,64]; + XmmReg[80,16] = XmmReg[80,16] >> m128[0,64]; + XmmReg[96,16] = XmmReg[96,16] >> m128[0,64]; + XmmReg[112,16] = XmmReg[112,16] >> m128[0,64]; +} + +:PSRLW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD1; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + #save this off in case XmmReg1 and XmmReg2 are the same register + local count:8 = XmmReg2[0,64]; + + XmmReg1[0,16] = XmmReg1[0,16] >> count; + XmmReg1[16,16] = XmmReg1[16,16] >> count; + XmmReg1[32,16] = XmmReg1[32,16] >> count; + XmmReg1[48,16] = XmmReg1[48,16] >> count; + XmmReg1[64,16] = XmmReg1[64,16] >> count; + XmmReg1[80,16] = XmmReg1[80,16] >> count; + XmmReg1[96,16] = XmmReg1[96,16] >> count; + XmmReg1[112,16] = XmmReg1[112,16] >> count; +} + +:PSRLW XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x71; mod = 0b11 & reg_opcode=2 & XmmReg2; imm8 +{ + XmmReg2[0,16] = XmmReg2[0,16] >> imm8; + XmmReg2[16,16] = XmmReg2[16,16] >> imm8; + XmmReg2[32,16] = XmmReg2[32,16] >> imm8; + XmmReg2[48,16] = XmmReg2[48,16] >> imm8; + XmmReg2[64,16] = XmmReg2[64,16] >> imm8; + XmmReg2[80,16] = XmmReg2[80,16] >> imm8; + XmmReg2[96,16] = XmmReg2[96,16] >> imm8; + XmmReg2[112,16] = XmmReg2[112,16] >> imm8; +} + +:PSRLD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD2; XmmReg ... & m128 ... +{ + XmmReg[0,32] = XmmReg[0,32] >> m128[0,64]; + XmmReg[32,32] = XmmReg[32,32] >> m128[0,64]; + XmmReg[64,32] = XmmReg[64,32] >> m128[0,64]; + XmmReg[96,32] = XmmReg[96,32] >> m128[0,64]; +} + +:PSRLD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD2; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + #save this off in case XmmReg1 and XmmReg2 are the same register + local count = XmmReg2[0,64]; + + XmmReg1[0,32] = XmmReg1[0,32] >> count; + XmmReg1[32,32] = XmmReg1[32,32] >> count; + XmmReg1[64,32] = XmmReg1[64,32] >> count; + XmmReg1[96,32] = XmmReg1[96,32] >> count; +} + +:PSRLD XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x72; mod = 0b11 & reg_opcode=2 & XmmReg2; imm8 +{ + XmmReg2[0,32] = XmmReg2[0,32] >> imm8; + XmmReg2[32,32] = XmmReg2[32,32] >> imm8; + XmmReg2[64,32] = XmmReg2[64,32] >> imm8; + XmmReg2[96,32] = XmmReg2[96,32] >> imm8; +} + +:PSRLQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD3; XmmReg ... & m128 ... +{ + XmmReg[0,64] = XmmReg[0,64] >> m128[0,64]; + XmmReg[64,64] = XmmReg[64,64] >> m128[0,64]; +} + +:PSRLQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD3; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + #save this off in case XmmReg1 and XmmReg2 are the same register + local count = XmmReg2[0,64]; + + XmmReg1[0,64] = XmmReg1[0,64] >> count; + XmmReg1[64,64] = XmmReg1[64,64] >> count; +} + +:PSRLQ XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x73; mod = 0b11 & reg_opcode=2 & XmmReg2; imm8 +{ + XmmReg2[0,64] = XmmReg2[0,64] >> imm8; + XmmReg2[64,64] = XmmReg2[64,64] >> imm8; +} + +:PSUBB mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF8; mmxreg ... & m64 ... +{ + local m:8 = m64; + mmxreg[0,8] = mmxreg[0,8] - m[0,8]; + mmxreg[8,8] = mmxreg[8,8] - m[8,8]; + mmxreg[16,8] = mmxreg[16,8] - m[16,8]; + mmxreg[24,8] = mmxreg[24,8] - m[24,8]; + mmxreg[32,8] = mmxreg[32,8] - m[32,8]; + mmxreg[40,8] = mmxreg[40,8] - m[40,8]; + mmxreg[48,8] = mmxreg[48,8] - m[48,8]; + mmxreg[56,8] = mmxreg[56,8] - m[56,8]; +} + +:PSUBB mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF8; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + mmxreg1[0,8] = mmxreg1[0,8] - mmxreg2[0,8]; + mmxreg1[16,8] = mmxreg1[16,8] - mmxreg2[16,8]; + mmxreg1[24,8] = mmxreg1[24,8] - mmxreg2[24,8]; + mmxreg1[32,8] = mmxreg1[32,8] - mmxreg2[32,8]; + mmxreg1[40,8] = mmxreg1[40,8] - mmxreg2[40,8]; + mmxreg1[48,8] = mmxreg1[48,8] - mmxreg2[48,8]; + mmxreg1[56,8] = mmxreg1[56,8] - mmxreg2[56,8]; +} + +:PSUBW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF9; mmxreg ... & m64 +{ + local m:8 = m64; + mmxreg[0,16] = mmxreg[0,16] - m[0,16]; + mmxreg[16,16] = mmxreg[16,16] - m[16,16]; + mmxreg[32,16] = mmxreg[32,16] - m[32,16]; + mmxreg[48,16] = mmxreg[48,16] - m[48,16]; +} + +:PSUBW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF9; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + mmxreg1[0,16] = mmxreg1[0,16] - mmxreg2[0,16]; + mmxreg1[16,16] = mmxreg1[16,16] - mmxreg2[16,16]; + mmxreg1[32,16] = mmxreg1[32,16] - mmxreg2[32,16]; + mmxreg1[48,16] = mmxreg1[48,16] - mmxreg2[48,16]; +} + +:PSUBD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xFA; mmxreg ... & m64 ... +{ + local m:8 = m64; + mmxreg[0,32] = mmxreg[0,32] - m[0,32]; + mmxreg[32,32] = mmxreg[32,32] - m[32,32]; +} + +:PSUBD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xFA; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + mmxreg1[0,32] = mmxreg1[0,32] - mmxreg2[0,32]; + mmxreg1[32,32] = mmxreg1[32,32] - mmxreg2[32,32]; +} + +:PSUBQ mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xFB; mmxreg ... & m64 ... { mmxreg = mmxreg - m64; } +:PSUBQ mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xFB; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = mmxreg1 - mmxreg2; } +:PSUBQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xFB; XmmReg ... & m128 ... +{ + local m:16 = m128; + XmmReg[0,64] = XmmReg[0,64] - m[0,64]; + XmmReg[64,64] = XmmReg[64,64] - m[64,64]; +} + +:PSUBQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xFB; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,64] = XmmReg1[0,64] - XmmReg2[0,64]; + XmmReg1[64,64] = XmmReg1[64,64] - XmmReg2[64,64]; +} + +:PSUBB XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF8; XmmReg ... & m128 ... +{ + local m:16 = m128; + XmmReg[0,8] = XmmReg[0,8] - m[0,8]; + XmmReg[8,8] = XmmReg[8,8] - m[8,8]; + XmmReg[16,8] = XmmReg[16,8] - m[16,8]; + XmmReg[24,8] = XmmReg[24,8] - m[24,8]; + XmmReg[32,8] = XmmReg[32,8] - m[32,8]; + XmmReg[40,8] = XmmReg[40,8] - m[40,8]; + XmmReg[48,8] = XmmReg[48,8] - m[48,8]; + XmmReg[56,8] = XmmReg[56,8] - m[56,8]; + XmmReg[64,8] = XmmReg[64,8] - m[64,8]; + XmmReg[72,8] = XmmReg[72,8] - m[72,8]; + XmmReg[80,8] = XmmReg[80,8] - m[80,8]; + XmmReg[88,8] = XmmReg[88,8] - m[88,8]; + XmmReg[96,8] = XmmReg[96,8] - m[96,8]; + XmmReg[104,8] = XmmReg[104,8] - m[104,8]; + XmmReg[112,8] = XmmReg[112,8] - m[112,8]; + XmmReg[120,8] = XmmReg[120,8] - m[120,8]; +} + +:PSUBB XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF8; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,8] = XmmReg1[0,8] - XmmReg2[0,8]; + XmmReg1[8,8] = XmmReg1[8,8] - XmmReg2[8,8]; + XmmReg1[16,8] = XmmReg1[16,8] - XmmReg2[16,8]; + XmmReg1[24,8] = XmmReg1[24,8] - XmmReg2[24,8]; + XmmReg1[32,8] = XmmReg1[32,8] - XmmReg2[32,8]; + XmmReg1[40,8] = XmmReg1[40,8] - XmmReg2[40,8]; + XmmReg1[48,8] = XmmReg1[48,8] - XmmReg2[48,8]; + XmmReg1[56,8] = XmmReg1[56,8] - XmmReg2[56,8]; + XmmReg1[64,8] = XmmReg1[64,8] - XmmReg2[64,8]; + XmmReg1[72,8] = XmmReg1[72,8] - XmmReg2[72,8]; + XmmReg1[80,8] = XmmReg1[80,8] - XmmReg2[80,8]; + XmmReg1[88,8] = XmmReg1[88,8] - XmmReg2[88,8]; + XmmReg1[96,8] = XmmReg1[96,8] - XmmReg2[96,8]; + XmmReg1[104,8] = XmmReg1[104,8] - XmmReg2[104,8]; + XmmReg1[112,8] = XmmReg1[112,8] - XmmReg2[112,8]; + XmmReg1[120,8] = XmmReg1[120,8] - XmmReg2[120,8]; +} + +:PSUBW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF9; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,16] = XmmReg[0,16] - m[0,16]; + XmmReg[16,16] = XmmReg[16,16] - m[16,16]; + XmmReg[32,16] = XmmReg[32,16] - m[32,16]; + XmmReg[48,16] = XmmReg[48,16] - m[48,16]; + XmmReg[64,16] = XmmReg[64,16] - m[64,16]; + XmmReg[80,16] = XmmReg[80,16] - m[80,16]; + XmmReg[96,16] = XmmReg[96,16] - m[96,16]; + XmmReg[112,16] = XmmReg[112,16] - m[112,16]; +} + +:PSUBW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF9; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,16] = XmmReg1[0,16] - XmmReg2[0,16]; + XmmReg1[16,16] = XmmReg1[16,16] - XmmReg2[16,16]; + XmmReg1[32,16] = XmmReg1[32,16] - XmmReg2[32,16]; + XmmReg1[48,16] = XmmReg1[48,16] - XmmReg2[48,16]; + XmmReg1[64,16] = XmmReg1[64,16] - XmmReg2[64,16]; + XmmReg1[80,16] = XmmReg1[80,16] - XmmReg2[80,16]; + XmmReg1[96,16] = XmmReg1[96,16] - XmmReg2[96,16]; + XmmReg1[112,16] = XmmReg1[112,16] - XmmReg2[112,16]; +} + +:PSUBD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xFA; XmmReg ... & m128 ... +{ + local m:16 = m128; + XmmReg[0,32] = XmmReg[0,32] - m[0,32]; + XmmReg[32,32] = XmmReg[32,32] - m[32,32]; + XmmReg[64,32] = XmmReg[64,32] - m[64,32]; + XmmReg[96,32] = XmmReg[96,32] - m[96,32]; +} + +:PSUBD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xFA; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = XmmReg1[0,32] - XmmReg2[0,32]; + XmmReg1[32,32] = XmmReg1[32,32] - XmmReg2[32,32]; + XmmReg1[64,32] = XmmReg1[64,32] - XmmReg2[64,32]; + XmmReg1[96,32] = XmmReg1[96,32] - XmmReg2[96,32]; +} + +define pcodeop psubsb; +:PSUBSB mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE8; mmxreg1 ... & mmxreg2_m64 ... { mmxreg1 = psubsb(mmxreg1, mmxreg2_m64); } + +define pcodeop psubsw; +:PSUBSW mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE9; mmxreg1 ... & mmxreg2_m64 ... { mmxreg1 = psubsw(mmxreg1, mmxreg2_m64); } + +:PSUBSB XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE8; XmmReg1 ... & XmmReg2_m128 ... { XmmReg1 = psubsb(XmmReg1, XmmReg2_m128); } + +:PSUBSW XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE9; XmmReg1 ... & XmmReg2_m128 ... { XmmReg1 = psubsw(XmmReg1, XmmReg2_m128); } + +define pcodeop psubusb; +:PSUBUSB mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD8; mmxreg1 ... & mmxreg2_m64 ... { mmxreg1 = psubusb(mmxreg1, mmxreg2_m64); } + +define pcodeop psubusw; +:PSUBUSW mmxreg1, mmxreg2_m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xD9; mmxreg1 ... & mmxreg2_m64 ... { mmxreg1 = psubusw(mmxreg1, mmxreg2_m64); } + +:PSUBUSB XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD8; XmmReg1 ... & XmmReg2_m128 { XmmReg1 = psubusb(XmmReg1, XmmReg2_m128); } + +:PSUBUSW XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xD9; XmmReg1 ... & XmmReg2_m128 { XmmReg1 = psubusw(XmmReg1, XmmReg2_m128); } + +:PUNPCKHBW mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x68; mmxreg ... & m64 +{ + local m:8 = m64; + mmxreg[0,8] = mmxreg[32,8]; + mmxreg[8,8] = m[32,8]; + mmxreg[16,8] = mmxreg[40,8]; + mmxreg[24,8] = m[40,8]; + mmxreg[32,8] = mmxreg[48,8]; + mmxreg[40,8] = m[48,8]; + mmxreg[48,8] = mmxreg[56,8]; + mmxreg[56,8] = m[56,8]; +} + +:PUNPCKHBW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x68; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + mmxreg1[0,8] = mmxreg1[32,8]; + mmxreg1[8,8] = mmxreg2[32,8]; + mmxreg1[16,8] = mmxreg1[40,8]; + mmxreg1[24,8] = mmxreg2[40,8]; + mmxreg1[32,8] = mmxreg1[48,8]; + mmxreg1[40,8] = mmxreg2[48,8]; + mmxreg1[48,8] = mmxreg1[56,8]; + mmxreg1[56,8] = mmxreg2[56,8]; +} + +:PUNPCKHWD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x69; mmxreg ... & m64 +{ + local m:8 = m64; + mmxreg[0,16] = mmxreg[32,16]; + mmxreg[16,16] = m[32,16]; + mmxreg[32,16] = mmxreg[48,16]; + mmxreg[48,16] = m[48,16]; +} + +:PUNPCKHWD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x69; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + mmxreg1[0,16] = mmxreg1[32,16]; + mmxreg1[16,16] = mmxreg2[32,16]; + mmxreg1[32,16] = mmxreg1[48,16]; + mmxreg1[48,16] = mmxreg2[48,16]; +} + +:PUNPCKHDQ mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x6A; mmxreg ... & m64 +{ + mmxreg[0,32] = mmxreg[32,32]; + mmxreg[32,32] = m64[32,32]; +} + +:PUNPCKHDQ mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x6A; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + mmxreg1[0,32] = mmxreg1[32,32]; + mmxreg1[32,32] = mmxreg2[32,32]; +} + +:PUNPCKHBW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x68; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,8] = XmmReg[64,8]; + XmmReg[8,8] = m[64,8]; + XmmReg[16,8] = XmmReg[72,8]; + XmmReg[24,8] = m[72,8]; + XmmReg[32,8] = XmmReg[80,8]; + XmmReg[40,8] = m[80,8]; + XmmReg[48,8] = XmmReg[88,8]; + XmmReg[56,8] = m[88,8]; + XmmReg[64,8] = XmmReg[96,8]; + XmmReg[72,8] = m[96,8]; + XmmReg[80,8] = XmmReg[104,8]; + XmmReg[88,8] = m[104,8]; + XmmReg[96,8] = XmmReg[112,8]; + XmmReg[104,8] = m[112,8]; + XmmReg[112,8] = XmmReg[120,8]; + XmmReg[120,8] = m[120,8]; +} + +# full set of XMM byte registers +:PUNPCKHBW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x68; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,8] = XmmReg1[64,8]; + XmmReg1[8,8] = XmmReg2[64,8]; + XmmReg1[16,8] = XmmReg1[72,8]; + XmmReg1[24,8] = XmmReg2[72,8]; + XmmReg1[32,8] = XmmReg1[80,8]; + XmmReg1[40,8] = XmmReg2[80,8]; + XmmReg1[48,8] = XmmReg1[88,8]; + XmmReg1[56,8] = XmmReg2[88,8]; + XmmReg1[64,8] = XmmReg1[96,8]; + XmmReg1[72,8] = XmmReg2[96,8]; + XmmReg1[80,8] = XmmReg1[104,8]; + XmmReg1[88,8] = XmmReg2[104,8]; + XmmReg1[96,8] = XmmReg1[112,8]; + XmmReg1[104,8] = XmmReg2[112,8]; + XmmReg1[112,8] = XmmReg1[120,8]; + XmmReg1[120,8] = XmmReg2[120,8]; +} + +:PUNPCKHWD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x69; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,16] = XmmReg[64,16]; + XmmReg[16,16] = m[64,16]; + XmmReg[32,16] = XmmReg[80,16]; + XmmReg[48,16] = m[80,16]; + XmmReg[64,16] = XmmReg[96,16]; + XmmReg[80,16] = m[96,16]; + XmmReg[96,16] = XmmReg[112,16]; + XmmReg[112,16] = m[112,16]; +} + +:PUNPCKHWD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x69; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,16] = XmmReg1[64,16]; + XmmReg1[16,16] = XmmReg2[64,16]; + XmmReg1[32,16] = XmmReg1[80,16]; + XmmReg1[48,16] = XmmReg2[80,16]; + XmmReg1[64,16] = XmmReg1[96,16]; + XmmReg1[80,16] = XmmReg2[96,16]; + XmmReg1[96,16] = XmmReg1[112,16]; + XmmReg1[112,16] = XmmReg2[112,16]; +} + +:PUNPCKHDQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x6A; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,32] = XmmReg[64,32]; + XmmReg[32,32] = m[64,32]; + XmmReg[64,32] = XmmReg[96,32]; + XmmReg[96,32] = m[96,32]; +} + +:PUNPCKHDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x6A; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = XmmReg1[64,32]; + XmmReg1[32,32] = XmmReg2[64,32]; + XmmReg1[64,32] = XmmReg1[96,32]; + XmmReg1[96,32] = XmmReg2[96,32]; +} + +:PUNPCKHQDQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x6D; m128 & XmmReg ... +{ + XmmReg[0,64] = XmmReg[64,64]; + XmmReg[64,64] = m128[64,64]; +} + +:PUNPCKHQDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x6D; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,64] = XmmReg1[64,64]; + XmmReg1[64,64] = XmmReg2[64,64]; +} + +:PUNPCKLBW mmxreg, m32 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x60; mmxreg ... & m32 +{ + local m:4 = m32; + mmxreg[56,8] = m[24,8]; + mmxreg[48,8] = mmxreg[24,8]; + mmxreg[40,8] = m[16,8]; + mmxreg[32,8] = mmxreg[16,8]; + mmxreg[24,8] = m[8,8]; + mmxreg[16,8] = mmxreg[8,8]; + mmxreg[8,8] = m[0,8]; +# mmxreg[0,8] = mmxreg[0,8]; superfluous +} + +:PUNPCKLBW mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x60; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + mmxreg1[56,8] = mmxreg2[24,8]; + mmxreg1[48,8] = mmxreg1[24,8]; + mmxreg1[40,8] = mmxreg2[16,8]; + mmxreg1[32,8] = mmxreg1[16,8]; + mmxreg1[24,8] = mmxreg2[8,8]; + mmxreg1[16,8] = mmxreg1[8,8]; + mmxreg1[8,8] = mmxreg2[0,8]; +# mmxreg1[0,8] = mmxreg1[0,8]; superfluous +} + +:PUNPCKLWD mmxreg, m32 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x61; mmxreg ... & m32 +{ + local m:4 = m32; + mmxreg[48,16] = m[16,16]; + mmxreg[32,16] = mmxreg[16,16]; + mmxreg[16,16] = m[0,16]; +# mmxreg[0,16] = mmxreg[0,16]; superfluous +} + +:PUNPCKLWD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x61; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + mmxreg1[48,16] = mmxreg2[16,16]; + mmxreg1[32,16] = mmxreg1[16,16]; + mmxreg1[16,16] = mmxreg2[0,16]; +# mmxreg1[0,16] = mmxreg1[0,16]; superfluous +} + +:PUNPCKLDQ mmxreg, m32 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x62; mmxreg ... & m32 +{ + mmxreg[32,32] = m32; +# mmxreg[0,32] = mmxreg[0,32]; superfluous +} + +:PUNPCKLDQ mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x62; mmxmod = 3 & mmxreg1 & mmxreg2 +{ + mmxreg1[32,32] = mmxreg2[0,32]; +# mmxreg1[0,32] = mmxreg1[0,32]; superfluous +} + +:PUNPCKLBW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x60; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[120,8] = m[56,8]; + XmmReg[112,8] = XmmReg[56,8]; + XmmReg[104,8] = m[48,8]; + XmmReg[96,8] = XmmReg[48,8]; + XmmReg[88,8] = m[40,8]; + XmmReg[80,8] = XmmReg[40,8]; + XmmReg[72,8] = m[32,8]; + XmmReg[64,8] = XmmReg[32,8]; + XmmReg[56,8] = m[24,8]; + XmmReg[48,8] = XmmReg[24,8]; + XmmReg[40,8] = m[16,8]; + XmmReg[32,8] = XmmReg[16,8]; + XmmReg[24,8] = m[8,8]; + XmmReg[16,8] = XmmReg[8,8]; + XmmReg[8,8] = m[0,8]; +# XmmReg[0,8] = XmmReg[0,8]; superfluous +} + +:PUNPCKLBW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x60; xmmmod = 3 & +XmmReg1 & XmmReg2 +{ + XmmReg1[120,8] = XmmReg2[56,8]; + XmmReg1[112,8] = XmmReg1[56,8]; + XmmReg1[104,8] = XmmReg2[48,8]; + XmmReg1[96,8] = XmmReg1[48,8]; + XmmReg1[88,8] = XmmReg2[40,8]; + XmmReg1[80,8] = XmmReg1[40,8]; + XmmReg1[72,8] = XmmReg2[32,8]; + XmmReg1[64,8] = XmmReg1[32,8]; + XmmReg1[56,8] = XmmReg2[24,8]; + XmmReg1[48,8] = XmmReg1[24,8]; + XmmReg1[40,8] = XmmReg2[16,8]; + XmmReg1[32,8] = XmmReg1[16,8]; + XmmReg1[24,8] = XmmReg2[8,8]; + XmmReg1[16,8] = XmmReg1[8,8]; + XmmReg1[8,8] = XmmReg2[0,8]; +# XmmReg1[0,8] = XmmReg1[0,8]; superfluous +} + +:PUNPCKLWD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x61; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[112,16] = m[48,16]; + XmmReg[96,16] = XmmReg[48,16]; + XmmReg[80,16] = m[32,16]; + XmmReg[64,16] = XmmReg[32,16]; + XmmReg[48,16] = m[16,16]; + XmmReg[32,16] = XmmReg[16,16]; + XmmReg[16,16] = m[0,16]; +# XmmReg[0,16] = XmmReg[0,16]; superfluous +} + +:PUNPCKLWD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x61; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[112,16] = XmmReg2[48,16]; + XmmReg1[96,16] = XmmReg1[48,16]; + XmmReg1[80,16] = XmmReg2[32,16]; + XmmReg1[64,16] = XmmReg1[32,16]; + XmmReg1[48,16] = XmmReg2[16,16]; + XmmReg1[32,16] = XmmReg1[16,16]; + XmmReg1[16,16] = XmmReg2[0,16]; +# XmmReg1[0,16] = XmmReg1[0,16]; superfluous +} + +:PUNPCKLDQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x62; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[96,32] = m[32,32]; + XmmReg[64,32] = XmmReg[32,32]; + XmmReg[32,32] = m[0,32]; +# XmmReg[0,32] = XmmReg[0,32]; superfluous +} + +:PUNPCKLDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x62; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[96,32] = XmmReg2[32,32]; + XmmReg1[64,32] = XmmReg1[32,32]; + XmmReg1[32,32] = XmmReg2[0,32]; +# XmmReg1[0,32] = XmmReg1[0,32]; superfluous +} + +define pcodeop punpcklqdq; +:PUNPCKLQDQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x6C; m128 & XmmReg ... +{ + XmmReg[64,64] = m128[0,64]; +# XmmReg[0,64] = XmmReg[0,64]; superfluous +} + +:PUNPCKLQDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x6C; xmmmod = 3 & XmmReg1 & XmmReg2 +{ + XmmReg1[64,64] = XmmReg2[0,64]; +# XmmReg1[0,64] = XmmReg1[0,64]; superfluous +} + +:PXOR mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xEF; mmxreg ... & m64 { mmxreg = mmxreg ^ m64; } +:PXOR mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xEF; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = mmxreg1 ^ mmxreg2; } +:PXOR XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xEF; XmmReg ... & m128 { XmmReg = XmmReg ^ m128; } +:PXOR XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xEF; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = XmmReg1 ^ XmmReg2; } + +define pcodeop rcpps; +:RCPPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x53; XmmReg ... & m128 { XmmReg = rcpps(XmmReg, m128); } +:RCPPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x53; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = rcpps(XmmReg1, XmmReg2); } + +define pcodeop rcpss; +:RCPSS XmmReg, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x53; XmmReg ... & m32 { XmmReg = rcpss(XmmReg, m32); } +:RCPSS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x53; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = rcpss(XmmReg1, XmmReg2); } + +define pcodeop rsqrtps; +:RSQRTPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x52; XmmReg ... & m128 { XmmReg = rsqrtps(XmmReg, m128); } +:RSQRTPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x52; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = rsqrtps(XmmReg1, XmmReg2); } + +define pcodeop rsqrtss; +:RSQRTSS XmmReg, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x52; XmmReg ... & m32 { XmmReg = rsqrtss(XmmReg, m32); } +:RSQRTSS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x52; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = rsqrtss(XmmReg1, XmmReg2); } + +:SHUFPD XmmReg1, XmmReg2_m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xC6; XmmReg1 ... & XmmReg2_m128; imm8 +{ + local srcLow:8 = XmmReg2_m128[0,64]; + local srcHigh:8 = XmmReg2_m128[64,64]; + local destLow:8 = XmmReg1[0,64]; + local destHigh:8 = XmmReg1[64,64]; + local control:1 = (imm8 & 0x1)== 0:1; + conditionalAssign(XmmReg1[0,64],control,destLow,destHigh); + control = (imm8 & 0x2) == 0:1; + conditionalAssign(XmmReg1[64,64],control,srcLow,srcHigh); +} + +:SHUFPS XmmReg1, XmmReg2_m128, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xC6; (XmmReg2_m128 & XmmReg1 ...); imm8 & Order0 & Order1 & Order2 & Order3 +{ + local xmmreg2_m128_c0 = XmmReg2_m128[0,32]; + local xmmreg2_m128_c1 = XmmReg2_m128[32,32]; + local xmmreg2_m128_c2 = XmmReg2_m128[64,32]; + local xmmreg2_m128_c3 = XmmReg2_m128[96,32]; + + local xmm_c0 = XmmReg1[0,32]; + local xmm_c1 = XmmReg1[32,32]; + local xmm_c2 = XmmReg1[64,32]; + local xmm_c3 = XmmReg1[96,32]; + + shuffle_4(XmmReg1[0,32],Order0,xmm_c0,xmm_c1,xmm_c2,xmm_c3); + shuffle_4(XmmReg1[32,32],Order1,xmm_c0,xmm_c1,xmm_c2,xmm_c3); + shuffle_4(XmmReg1[64,32],Order2,xmmreg2_m128_c0,xmmreg2_m128_c1,xmmreg2_m128_c2,xmmreg2_m128_c3); + shuffle_4(XmmReg1[96,32],Order3,xmmreg2_m128_c0,xmmreg2_m128_c1,xmmreg2_m128_c2,xmmreg2_m128_c3); +} + +define pcodeop sqrtpd; +:SQRTPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x51; XmmReg ... & m128 { XmmReg = sqrtpd(XmmReg, m128); } +:SQRTPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x51; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = sqrtpd(XmmReg1, XmmReg2); } + +define pcodeop sqrtps; +:SQRTPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x51; XmmReg ... & m128 { XmmReg = sqrtps(XmmReg, m128); } +:SQRTPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x51; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = sqrtps(XmmReg1, XmmReg2); } + +:SQRTSD XmmReg, m64 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x51; XmmReg ... & m64 { XmmReg[0,64] = sqrt(m64); } +:SQRTSD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x51; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1[0,64] = sqrt(XmmReg2[0,64]); } + +:SQRTSS XmmReg, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x51; XmmReg ... & m32 { XmmReg[0,32] = sqrt(m32); } +:SQRTSS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x51; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1[0,32] = sqrt(XmmReg2[0,32]); } + +:SUBPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5C;XmmReg ... & m128 +{ + local m:16 = m128; + XmmReg[0,64] = XmmReg[0,64] f- m[0,64]; + XmmReg[64,64] = XmmReg[64,64] f- m[64,64]; +} + +:SUBPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5C; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,64] = XmmReg1[0,64] f- XmmReg2[0,64]; + XmmReg1[64,64] = XmmReg1[64,64] f- XmmReg2[64,64]; +} + +:SUBPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x5C; XmmReg ... & m128 +{ + local m:16 = m128; + XmmReg[0,32] = XmmReg[0,32] f- m[0,32]; + XmmReg[32,32] = XmmReg[32,32] f- m[32,32]; + XmmReg[64,32] = XmmReg[64,32] f- m[64,32]; + XmmReg[96,32] = XmmReg[96,32] f- m[96,32]; +} + +:SUBPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x5C; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = XmmReg1[0,32] f- XmmReg2[0,32]; + XmmReg1[32,32] = XmmReg1[32,32] f- XmmReg2[32,32]; + XmmReg1[64,32] = XmmReg1[64,32] f- XmmReg2[64,32]; + XmmReg1[96,32] = XmmReg1[96,32] f- XmmReg2[96,32]; +} + +:SUBSD XmmReg, m64 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x5C; XmmReg ... & m64 { XmmReg[0,64] = XmmReg[0,64] f- m64; } +:SUBSD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x5C; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1[0,64] = XmmReg1[0,64] f- XmmReg2[0,64]; } + +:SUBSS XmmReg, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x5C; XmmReg ...& m32 { XmmReg[0,32] = XmmReg[0,32] f- m32; } +:SUBSS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x5C; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1[0,32] = XmmReg1[0,32] f- XmmReg2[0,32]; } + +#Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS +# RESULT <- UnorderedCompare(SRC1[63-0] <> SRC2[63-0]) { +# * Set EFLAGS *CASE (RESULT) OF +# UNORDERED: ZF,PF,CF <- 111; +# GREATER_THAN: ZF,PF,CF <- 000; +# LESS_THAN: ZF,PF,CF <- 001; +# EQUAL: ZF,PF,CF <- 100; +# ESAC; +# OF,AF,SF <- 0;} + +:UCOMISD XmmReg, m64 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x2E; m64 & XmmReg ... +{ + fucompe(XmmReg[0,64], m64); +} + +:UCOMISD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x2E; xmmmod=3 & XmmReg1 & XmmReg2 +{ + fucompe(XmmReg1[0,64], XmmReg2[0,64]); +} + +#Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS +# RESULT <- UnorderedCompare(SRC1[31-0] <> SRC2[31-0]) { +# * Set EFLAGS *CASE (RESULT) OF +# UNORDERED: ZF,PF,CF <- 111; +# GREATER_THAN: ZF,PF,CF <- 000; +# LESS_THAN: ZF,PF,CF <- 001; +# EQUAL: ZF,PF,CF <- 100; +# ESAC; +# OF,AF,SF <- 0;} + +:UCOMISS XmmReg, m32 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x2E; m32 & XmmReg ... +{ + fucompe(XmmReg[0,32], m32); +} + +:UCOMISS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x2E; xmmmod=3 & XmmReg1 & XmmReg2 +{ + fucompe(XmmReg1[0,32], XmmReg2[0,32]); +} + +:UNPCKHPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x15; m128 & XmmReg ... +{ + XmmReg[0,64] = XmmReg[64,64]; + XmmReg[64,64] = m128[64,64]; +} + +:UNPCKHPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x15; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,64] = XmmReg1[64,64]; + XmmReg1[64,64] = XmmReg2[64,64]; +} + +:UNPCKHPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x15; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,32] = XmmReg[64,32]; + XmmReg[64,32] = XmmReg[96,32]; + XmmReg[32,32] = m[64,32]; + XmmReg[96,32] = m[96,32]; +} + +:UNPCKHPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x15; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = XmmReg1[64,32]; + XmmReg1[32,32] = XmmReg2[64,32]; + XmmReg1[64,32] = XmmReg1[96,32]; # XmmReg1 and XmmReg2 could be the same register, preserve XmmReg1[64,32] till later + XmmReg1[96,32] = XmmReg2[96,32]; +} + +:UNPCKLPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x14; m128 & XmmReg ... +{ +# XmmReg[0,64] = XmmReg[0,64]; superfluous + XmmReg[64,64] = m128[0,64]; +} + +:UNPCKLPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x14; xmmmod=3 & XmmReg1 & XmmReg2 +{ +# XmmReg1[0,64] = XmmReg1[0,64]; superfluous + XmmReg1[64,64] = XmmReg2[0,64]; +} + +:UNPCKLPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x14; m128 & XmmReg ... +{ + local m:16 = m128; +# XmmReg[0,32] = XmmReg[0,32]; superfluous + XmmReg[64,32] = XmmReg[32,32]; + XmmReg[32,32] = m[0,32]; + XmmReg[96,32] = m[32,32]; +} + +:UNPCKLPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x14; xmmmod=3 & XmmReg1 & XmmReg2 +{ +# XmmReg1[0,32] = XmmReg1[0,32]; superfluous + XmmReg1[64,32] = XmmReg1[32,32]; + XmmReg1[96,32] = XmmReg2[32,32]; + XmmReg1[32,32] = XmmReg2[0,32]; # XmmReg1 and XmmReg2 could be the same register, preserve Db till last +} + +:XORPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x57; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,64] = ( XmmReg[0,64] ^ m[0,64] ); + XmmReg[64,64] = ( XmmReg[64,64] ^ m[64,64] ); +} + +:XORPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x57; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,64] = ( XmmReg1[0,64] ^ XmmReg2[0,64] ); + XmmReg1[64,64] = ( XmmReg1[64,64] ^ XmmReg2[64,64] ); +} + +:XORPS XmmReg, m128 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x57; m128 & XmmReg ... +{ + local m:16 = m128; + XmmReg[0,32] = ( XmmReg[0,32] ^ m[0,32] ); + XmmReg[32,32] = ( XmmReg[32,32] ^ m[32,32] ); + XmmReg[64,32] = ( XmmReg[64,32] ^ m[64,32] ); + XmmReg[96,32] = ( XmmReg[96,32] ^ m[96,32] ); +} + +:XORPS XmmReg1, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x57; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,32] = ( XmmReg1[0,32] ^ XmmReg2[0,32] ); + XmmReg1[32,32] = ( XmmReg1[32,32] ^ XmmReg2[32,32] ); + XmmReg1[64,32] = ( XmmReg1[64,32] ^ XmmReg2[64,32] ); + XmmReg1[96,32] = ( XmmReg1[96,32] ^ XmmReg2[96,32] ); +} + +#### +#### VIA Padlock instructions +#### + +define pcodeop xstore_available; +define pcodeop xstore; +define pcodeop xcrypt_ecb; +define pcodeop xcrypt_cbc; +define pcodeop xcrypt_ctr; +define pcodeop xcrypt_cfb; +define pcodeop xcrypt_ofb; +define pcodeop montmul; +define pcodeop xsha1; +define pcodeop xsha256; + +:XSTORE is vexMode=0 & mandover=0 & byte=0x0F; byte=0xA7; byte=0xC0 { + EAX = xstore_available(EDX,EDI); +} + +:XSTORE.REP is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xA7; byte=0xC0 { + EAX = xstore(ECX,EDX,EDI); + ECX = 0; +} + +:XCRYPTECB.REP is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xA7; byte=0xC8 { + xcrypt_ecb(ECX,EDX,EBX,ESI,EDI); +} + +:XCRYPTCBC.REP is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xA7; byte=0xD0 { + xcrypt_cbc(ECX,EAX,EDX,EBX,ESI,EDI); +} + +:XCRYPTCTR.REP is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xA7; byte=0xD8 { + xcrypt_ctr(ECX,EAX,EDX,EBX,ESI,EDI); +} + +:XCRYPTCFB.REP is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xA7; byte=0xE0 { + xcrypt_cfb(ECX,EAX,EDX,EBX,ESI,EDI); +} + +:XCRYPTOFB.REP is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xA7; byte=0xE8 { + xcrypt_ofb(ECX,EAX,EDX,EBX,ESI,EDI); +} + +:MONTMUL.REP is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xA6; byte=0xC0 { + montmul(EAX,ECX,ESI); + ECX=0; + EDX=0; +} + +:XSHA1.REP is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xA6; byte=0xC8 { + xsha1(ECX,ESI,EDI); + EAX = ECX; +} + +:XSHA256.REP is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0xA6; byte=0xD0 { + xsha256(ECX,ESI,EDI); + EAX = ECX; +} + +#### +#### SSE4.1 instructions +#### + +define pcodeop mpsadbw; +:MPSADBW XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x42; XmmReg ... & m128; imm8 { XmmReg = mpsadbw(XmmReg, m128, imm8:8); } +:MPSADBW XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x42; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XmmReg1 = mpsadbw(XmmReg1, XmmReg2, imm8:8); } + +define pcodeop phminposuw; +:PHMINPOSUW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x41; XmmReg ... & m128 { XmmReg = phminposuw(m128); } +:PHMINPOSUW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x41; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = phminposuw(XmmReg2); } + +define pcodeop pmuldq; +:PMULDQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x28; XmmReg ... & m128 { XmmReg = pmuldq(XmmReg, m128); } +:PMULDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x28; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmuldq(XmmReg1, XmmReg2); } + +define pcodeop pmulld; +:PMULLD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x40; XmmReg ... & m128 { XmmReg = pmulld(XmmReg, m128); } +:PMULLD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x40; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmulld(XmmReg1, XmmReg2); } + +define pcodeop dpps; +:DPPS XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x40; XmmReg ... & m128; imm8 { XmmReg = dpps(XmmReg, m128, imm8:8); } +:DPPS XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x40; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XmmReg1 = dpps(XmmReg1, XmmReg2, imm8:8); } + +define pcodeop dppd; +:DPPD XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x41; XmmReg ... & m128; imm8 { XmmReg = dppd(XmmReg, m128, imm8:8); } +:DPPD XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x41; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XmmReg1 = dppd(XmmReg1, XmmReg2, imm8:8); } + +define pcodeop blendps; +:BLENDPS XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x0C; XmmReg ... & m128; imm8 { XmmReg = blendps(XmmReg, m128, imm8:8); } +:BLENDPS XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x0C; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XmmReg1 = blendps(XmmReg1, XmmReg2, imm8:8); } + +define pcodeop blendpd; +:BLENDPD XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x0D; XmmReg ... & m128; imm8 { XmmReg = blendpd(XmmReg, m128, imm8:8); } +:BLENDPD XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x0D; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XmmReg1 = blendpd(XmmReg1, XmmReg2, imm8:8); } + +define pcodeop blendvps; +:BLENDVPS XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x14; XmmReg ... & m128 { XmmReg = blendvps(XmmReg, m128, XMM0); } +:BLENDVPS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x14; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = blendvps(XmmReg1, XmmReg2, XMM0); } + +define pcodeop blendvpd; +:BLENDVPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x15; XmmReg ... & m128 { XmmReg = blendvpd(XmmReg, m128, XMM0); } +:BLENDVPD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x15; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = blendvpd(XmmReg1, XmmReg2, XMM0); } + +define pcodeop pblendvb; +:PBLENDVB XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x10; XmmReg ... & m128 { XmmReg = pblendvb(XmmReg, m128, XMM0); } +:PBLENDVB XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x10; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pblendvb(XmmReg1, XmmReg2, XMM0); } + +define pcodeop pblendw; +:PBLENDW XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x0E; XmmReg ... & m128; imm8 { XmmReg = pblendw(XmmReg, m128, imm8:8); } +:PBLENDW XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x0E; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XmmReg1 = pblendw(XmmReg1, XmmReg2, imm8:8); } + +:PMINSB XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x38; XmmReg1 ... & XmmReg2_m128 +{ + local srcCopy:16 = XmmReg2_m128; + conditionalAssign(XmmReg1[0,8],srcCopy[0,8] s< XmmReg1[0,8],srcCopy[0,8],XmmReg1[0,8]); + conditionalAssign(XmmReg1[8,8],srcCopy[8,8] s< XmmReg1[8,8],srcCopy[8,8],XmmReg1[8,8]); + conditionalAssign(XmmReg1[16,8],srcCopy[16,8] s< XmmReg1[16,8],srcCopy[16,8],XmmReg1[16,8]); + conditionalAssign(XmmReg1[24,8],srcCopy[24,8] s< XmmReg1[24,8],srcCopy[24,8],XmmReg1[24,8]); + conditionalAssign(XmmReg1[32,8],srcCopy[32,8] s< XmmReg1[32,8],srcCopy[32,8],XmmReg1[32,8]); + conditionalAssign(XmmReg1[40,8],srcCopy[40,8] s< XmmReg1[40,8],srcCopy[40,8],XmmReg1[40,8]); + conditionalAssign(XmmReg1[48,8],srcCopy[48,8] s< XmmReg1[48,8],srcCopy[48,8],XmmReg1[48,8]); + conditionalAssign(XmmReg1[56,8],srcCopy[56,8] s< XmmReg1[56,8],srcCopy[56,8],XmmReg1[56,8]); + conditionalAssign(XmmReg1[64,8],srcCopy[64,8] s< XmmReg1[64,8],srcCopy[64,8],XmmReg1[64,8]); + conditionalAssign(XmmReg1[72,8],srcCopy[72,8] s< XmmReg1[72,8],srcCopy[72,8],XmmReg1[72,8]); + conditionalAssign(XmmReg1[80,8],srcCopy[80,8] s< XmmReg1[80,8],srcCopy[80,8],XmmReg1[80,8]); + conditionalAssign(XmmReg1[88,8],srcCopy[88,8] s< XmmReg1[88,8],srcCopy[88,8],XmmReg1[88,8]); + conditionalAssign(XmmReg1[96,8],srcCopy[96,8] s< XmmReg1[96,8],srcCopy[96,8],XmmReg1[96,8]); + conditionalAssign(XmmReg1[104,8],srcCopy[104,8] s< XmmReg1[104,8],srcCopy[104,8],XmmReg1[104,8]); + conditionalAssign(XmmReg1[112,8],srcCopy[112,8] s< XmmReg1[112,8],srcCopy[112,8],XmmReg1[112,8]); + conditionalAssign(XmmReg1[120,8],srcCopy[120,8] s< XmmReg1[120,8],srcCopy[120,8],XmmReg1[120,8]); +} + +:PMINUW XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x3A; XmmReg1 ... & XmmReg2_m128 +{ + local srcCopy:16 = XmmReg2_m128; + conditionalAssign(XmmReg1[0,16],srcCopy[0,16] < XmmReg1[0,16],srcCopy[0,16],XmmReg1[0,16]); + conditionalAssign(XmmReg1[16,16],srcCopy[16,16] < XmmReg1[16,16],srcCopy[16,16],XmmReg1[16,16]); + conditionalAssign(XmmReg1[32,16],srcCopy[32,16] < XmmReg1[32,16],srcCopy[32,16],XmmReg1[32,16]); + conditionalAssign(XmmReg1[48,16],srcCopy[48,16] < XmmReg1[48,16],srcCopy[48,16],XmmReg1[48,16]); + conditionalAssign(XmmReg1[64,16],srcCopy[64,16] < XmmReg1[64,16],srcCopy[64,16],XmmReg1[64,16]); + conditionalAssign(XmmReg1[80,16],srcCopy[80,16] < XmmReg1[80,16],srcCopy[80,16],XmmReg1[80,16]); + conditionalAssign(XmmReg1[96,16],srcCopy[96,16] < XmmReg1[96,16],srcCopy[96,16],XmmReg1[96,16]); + conditionalAssign(XmmReg1[112,16],srcCopy[112,16] < XmmReg1[112,16],srcCopy[112,16],XmmReg1[112,16]); +} + +:PMINUD XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x3B; XmmReg1 ... & XmmReg2_m128 +{ + local srcCopy:16 = XmmReg2_m128; + conditionalAssign(XmmReg1[0,32],srcCopy[0,32] < XmmReg1[0,32],srcCopy[0,32],XmmReg1[0,32]); + conditionalAssign(XmmReg1[32,32],srcCopy[32,32] < XmmReg1[32,32],srcCopy[32,32],XmmReg1[32,32]); + conditionalAssign(XmmReg1[64,32],srcCopy[64,32] < XmmReg1[64,32],srcCopy[64,32],XmmReg1[64,32]); + conditionalAssign(XmmReg1[96,32],srcCopy[96,32] < XmmReg1[96,32],srcCopy[96,32],XmmReg1[96,32]); +} + +:PMINSD XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x39; XmmReg1 ... & XmmReg2_m128 +{ + local srcCopy:16 = XmmReg2_m128; + conditionalAssign(XmmReg1[0,32],srcCopy[0,32] s< XmmReg1[0,32],srcCopy[0,32],XmmReg1[0,32]); + conditionalAssign(XmmReg1[32,32],srcCopy[32,32] s< XmmReg1[32,32],srcCopy[32,32],XmmReg1[32,32]); + conditionalAssign(XmmReg1[64,32],srcCopy[64,32] s< XmmReg1[64,32],srcCopy[64,32],XmmReg1[64,32]); + conditionalAssign(XmmReg1[96,32],srcCopy[96,32] s< XmmReg1[96,32],srcCopy[96,32],XmmReg1[96,32]); +} + +:PMAXSB XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x3C; XmmReg1 ... & XmmReg2_m128 +{ + local srcCopy:16 = XmmReg2_m128; + conditionalAssign(XmmReg1[0,8],srcCopy[0,8] s> XmmReg1[0,8],srcCopy[0,8],XmmReg1[0,8]); + conditionalAssign(XmmReg1[8,8],srcCopy[8,8] s> XmmReg1[8,8],srcCopy[8,8],XmmReg1[8,8]); + conditionalAssign(XmmReg1[16,8],srcCopy[16,8] s> XmmReg1[16,8],srcCopy[16,8],XmmReg1[16,8]); + conditionalAssign(XmmReg1[24,8],srcCopy[24,8] s> XmmReg1[24,8],srcCopy[24,8],XmmReg1[24,8]); + conditionalAssign(XmmReg1[32,8],srcCopy[32,8] s> XmmReg1[32,8],srcCopy[32,8],XmmReg1[32,8]); + conditionalAssign(XmmReg1[40,8],srcCopy[40,8] s> XmmReg1[40,8],srcCopy[40,8],XmmReg1[40,8]); + conditionalAssign(XmmReg1[48,8],srcCopy[48,8] s> XmmReg1[48,8],srcCopy[48,8],XmmReg1[48,8]); + conditionalAssign(XmmReg1[56,8],srcCopy[56,8] s> XmmReg1[56,8],srcCopy[56,8],XmmReg1[56,8]); + conditionalAssign(XmmReg1[64,8],srcCopy[64,8] s> XmmReg1[64,8],srcCopy[64,8],XmmReg1[64,8]); + conditionalAssign(XmmReg1[72,8],srcCopy[72,8] s> XmmReg1[72,8],srcCopy[72,8],XmmReg1[72,8]); + conditionalAssign(XmmReg1[80,8],srcCopy[80,8] s> XmmReg1[80,8],srcCopy[80,8],XmmReg1[80,8]); + conditionalAssign(XmmReg1[88,8],srcCopy[88,8] s> XmmReg1[88,8],srcCopy[88,8],XmmReg1[88,8]); + conditionalAssign(XmmReg1[96,8],srcCopy[96,8] s> XmmReg1[96,8],srcCopy[96,8],XmmReg1[96,8]); + conditionalAssign(XmmReg1[104,8],srcCopy[104,8] s> XmmReg1[104,8],srcCopy[104,8],XmmReg1[104,8]); + conditionalAssign(XmmReg1[112,8],srcCopy[112,8] s> XmmReg1[112,8],srcCopy[112,8],XmmReg1[112,8]); + conditionalAssign(XmmReg1[120,8],srcCopy[120,8] s> XmmReg1[120,8],srcCopy[120,8],XmmReg1[120,8]); +} + + +:PMAXUW XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x3E; XmmReg1 ... & XmmReg2_m128 +{ + local srcCopy:16 = XmmReg2_m128; + conditionalAssign(XmmReg1[0,16],srcCopy[0,16] > XmmReg1[0,16],srcCopy[0,16],XmmReg1[0,16]); + conditionalAssign(XmmReg1[16,16],srcCopy[16,16] > XmmReg1[16,16],srcCopy[16,16],XmmReg1[16,16]); + conditionalAssign(XmmReg1[32,16],srcCopy[32,16] > XmmReg1[32,16],srcCopy[32,16],XmmReg1[32,16]); + conditionalAssign(XmmReg1[48,16],srcCopy[48,16] > XmmReg1[48,16],srcCopy[48,16],XmmReg1[48,16]); + conditionalAssign(XmmReg1[64,16],srcCopy[64,16] > XmmReg1[64,16],srcCopy[64,16],XmmReg1[64,16]); + conditionalAssign(XmmReg1[80,16],srcCopy[80,16] > XmmReg1[80,16],srcCopy[80,16],XmmReg1[80,16]); + conditionalAssign(XmmReg1[96,16],srcCopy[96,16] > XmmReg1[96,16],srcCopy[96,16],XmmReg1[96,16]); + conditionalAssign(XmmReg1[112,16],srcCopy[112,16] > XmmReg1[112,16],srcCopy[112,16],XmmReg1[112,16]); +} + +:PMAXUD XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x3F; XmmReg1 ... & XmmReg2_m128 +{ + local srcCopy:16 = XmmReg2_m128; + conditionalAssign(XmmReg1[0,32],srcCopy[0,32] > XmmReg1[0,32],srcCopy[0,32],XmmReg1[0,32]); + conditionalAssign(XmmReg1[32,32],srcCopy[32,32] > XmmReg1[32,32],srcCopy[32,32],XmmReg1[32,32]); + conditionalAssign(XmmReg1[64,32],srcCopy[64,32] > XmmReg1[64,32],srcCopy[64,32],XmmReg1[64,32]); + conditionalAssign(XmmReg1[96,32],srcCopy[96,32] > XmmReg1[96,32],srcCopy[96,32],XmmReg1[96,32]); +} + +:PMAXSD XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x3D; XmmReg1 ... & XmmReg2_m128 +{ + local srcCopy:16 = XmmReg2_m128; + conditionalAssign(XmmReg1[0,32],srcCopy[0,32] s> XmmReg1[0,32],srcCopy[0,32],XmmReg1[0,32]); + conditionalAssign(XmmReg1[32,32],srcCopy[32,32] s> XmmReg1[32,32],srcCopy[32,32],XmmReg1[32,32]); + conditionalAssign(XmmReg1[64,32],srcCopy[64,32] s> XmmReg1[64,32],srcCopy[64,32],XmmReg1[64,32]); + conditionalAssign(XmmReg1[96,32],srcCopy[96,32] s> XmmReg1[96,32],srcCopy[96,32],XmmReg1[96,32]); +} + +define pcodeop roundps; +:ROUNDPS XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x08; XmmReg ... & m128; imm8 { XmmReg = roundps(XmmReg, m128, imm8:8); } +:ROUNDPS XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x08; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XmmReg1 = roundps(XmmReg1, XmmReg2, imm8:8); } + +define pcodeop roundss; +:ROUNDSS XmmReg, m32, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x0A; XmmReg ... & m32; imm8 { XmmReg = roundss(XmmReg, m32, imm8:8); } +:ROUNDSS XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x0A; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XmmReg1 = roundss(XmmReg1, XmmReg2, imm8:8); } + +define pcodeop roundpd; +:ROUNDPD XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x09; XmmReg ... & m128; imm8 { XmmReg = roundpd(XmmReg, m128, imm8:8); } +:ROUNDPD XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x09; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XmmReg1 = roundpd(XmmReg1, XmmReg2, imm8:8); } + +define pcodeop roundsd; +:ROUNDSD XmmReg, m64, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x0B; XmmReg ... & m64; imm8 { XmmReg = roundsd(XmmReg, m64, imm8:8); } +:ROUNDSD XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x0B; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XmmReg1 = roundsd(XmmReg1, XmmReg2, imm8:8); } + +define pcodeop insertps; +:INSERTPS XmmReg, m32, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x21; XmmReg ... & m32; imm8 { XmmReg = insertps(XmmReg, m32, imm8:8); } +:INSERTPS XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x21; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XmmReg1 = insertps(XmmReg1, XmmReg2, imm8:8); } + +:PINSRB XmmReg, rm32, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x20; XmmReg ... & rm32; imm8 +{ + local destIndex:1 = (imm8 & 0xf) * 8:1; + local useLow:1 = destIndex < 64:1; + local newLow:8 = zext(rm32:1) << destIndex; + newLow = (XmmReg[0,64] & ~(0xff:8 << destIndex)) | newLow; + local newHigh:8 = zext(rm32:1) << (destIndex-64:1); + newHigh = (XmmReg[64,64] & ~(0xff:8 << (destIndex - 64:1))) | newHigh; + conditionalAssign(XmmReg[0,64],useLow,newLow,XmmReg[0,64]); + conditionalAssign(XmmReg[64,64],!useLow,newHigh,XmmReg[64,64]); +} + +:PINSRD XmmReg, rm32, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x22; XmmReg ... & rm32; imm8 +{ + local destIndex:1 = (imm8 & 0x3) * 32:1; + local useLow:1 = destIndex < 64:1; + local newLow:8 = zext(rm32) << destIndex; + newLow = (XmmReg[0,64] & ~(0xffffffff:8 << destIndex)) | newLow; + local newHigh:8 = zext(rm32) << (destIndex-64:1); + newHigh = (XmmReg[64,64] & ~(0xffffffff:8 << (destIndex - 64:1))) | newHigh; + conditionalAssign(XmmReg[0,64],useLow,newLow,XmmReg[0,64]); + conditionalAssign(XmmReg[64,64],!useLow,newHigh,XmmReg[64,64]); +} + +@ifdef IA64 +:PINSRQ XmmReg, rm64, imm8 is $(LONGMODE_ON) & vexMode=0 & bit64=1 & $(PRE_66) & $(REX_W) & byte=0x0F; byte=0x3A; byte=0x22; XmmReg ... & rm64; imm8 +{ + local useHigh:1 = imm8 & 0x1; + conditionalAssign(XmmReg[0,64],!useHigh,rm64,XmmReg[0,64]); + conditionalAssign(XmmReg[64,64],useHigh,rm64,XmmReg[64,64]); +} +@endif + +define pcodeop extractps; +@ifdef IA64 +:EXTRACTPS rm64, XmmReg, imm8 is $(LONGMODE_ON) & vexMode=0 & bit64=1 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x17; XmmReg ... & rm64; imm8 { rm64 = extractps(XmmReg, imm8:8); } +@endif +:EXTRACTPS rm32, XmmReg, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x17; XmmReg ... & rm32 & check_rm32_dest ...; imm8 { rm32 = extractps(XmmReg, imm8:8); build check_rm32_dest; } + +:PEXTRB Rmr32, XmmReg, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x14; mod=3 & XmmReg & Rmr32 & check_Rmr32_dest; imm8 +{ + local shift:1 = (imm8 & 0xf) * 8:1; + local low:1 = shift < 64:1; + local temp:8; + conditionalAssign(temp,low,XmmReg[0,64] >> shift,XmmReg[64,64] >> (shift - 64)); + Rmr32 = zext(temp:1); + build check_Rmr32_dest; +} + +:PEXTRB Mem, XmmReg, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x14; XmmReg ... & Mem; imm8 +{ + local shift:1 = (imm8 & 0xf) * 8:1; + local low:1 = shift < 64:1; + local temp:8; + conditionalAssign(temp,low,XmmReg[0,64] >> shift,XmmReg[64,64] >> (shift - 64)); + Mem = temp:1; +} + +:PEXTRD Rmr32, XmmReg, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x16; mod=3 & XmmReg & Rmr32 & check_Rmr32_dest; imm8 +{ + local shift:1 = (imm8 & 0x3) * 32:1; + local low:1 = shift < 64:1; + local temp:8; + conditionalAssign(temp,low,XmmReg[0,64] >> shift,XmmReg[64,64] >> (shift - 64)); + Rmr32 = zext(temp:4); + build check_Rmr32_dest; +} + +:PEXTRD Mem, XmmReg, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x16; XmmReg ... & Mem; imm8 +{ + local shift:1 = (imm8 & 0x3) * 32:1; + local low:1 = shift < 64:1; + local temp:8; + conditionalAssign(temp,low,XmmReg[0,64] >> shift,XmmReg[64,64] >> (shift - 64)); + Mem = temp:4; +} + +@ifdef IA64 +:PEXTRQ Rmr64, XmmReg, imm8 is $(LONGMODE_ON) & vexMode=0 & bit64=1 & $(PRE_66) & $(REX_W) & byte=0x0F; byte=0x3A; byte=0x16; mod=3 & XmmReg & Rmr64; imm8 +{ + local high:1 = imm8 & 0x1; + conditionalAssign(Rmr64,high,XmmReg[64,64],XmmReg[0,64]); +} + +:PEXTRQ Mem, XmmReg, imm8 is $(LONGMODE_ON) & vexMode=0 & bit64=1 & $(PRE_66) & $(REX_W) & byte=0x0F; byte=0x3A; byte=0x16; XmmReg ... & Mem; imm8 +{ + local high:1 = imm8 & 0x1; + conditionalAssign(Mem,high,XmmReg[64,64],XmmReg[0,64]); +} +@endif + +define pcodeop pmovsxbw; +:PMOVSXBW XmmReg, m64 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x20; XmmReg ... & m64 { XmmReg = pmovsxbw(XmmReg, m64); } +:PMOVSXBW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x20; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmovsxbw(XmmReg1, XmmReg2); } + +define pcodeop pmovsxbd; +:PMOVSXBD XmmReg, m32 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x21; XmmReg ... & m32 { XmmReg = pmovsxbd(XmmReg, m32); } +:PMOVSXBD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x21; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmovsxbd(XmmReg1, XmmReg2); } + +define pcodeop pmovsxbq; +:PMOVSXBQ XmmReg, m16 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x22; XmmReg ... & m16 { XmmReg = pmovsxbq(XmmReg, m16); } +:PMOVSXBQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x22; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmovsxbq(XmmReg1, XmmReg2); } + +define pcodeop pmovsxwd; +:PMOVSXWD XmmReg, m64 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x23; XmmReg ... & m64 { XmmReg = pmovsxwd(XmmReg, m64); } +:PMOVSXWD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x23; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmovsxwd(XmmReg1, XmmReg2); } + +define pcodeop pmovsxwq; +:PMOVSXWQ XmmReg, m32 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x24; XmmReg ... & m32 { XmmReg = pmovsxwq(XmmReg, m32); } +:PMOVSXWQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x24; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmovsxwq(XmmReg1, XmmReg2); } + +define pcodeop pmovsxdq; +:PMOVSXDQ XmmReg, m64 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x25; XmmReg ... & m64 { XmmReg = pmovsxdq(XmmReg, m64); } +:PMOVSXDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x25; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmovsxdq(XmmReg1, XmmReg2); } + +define pcodeop pmovzxbw; +:PMOVZXBW XmmReg, m64 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x30; XmmReg ... & m64 { XmmReg = pmovzxbw(XmmReg, m64); } +:PMOVZXBW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x30; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmovzxbw(XmmReg1, XmmReg2); } + +define pcodeop pmovzxbd; +:PMOVZXBD XmmReg, m32 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x31; XmmReg ... & m32 { XmmReg = pmovzxbd(XmmReg, m32); } +:PMOVZXBD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x31; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmovzxbd(XmmReg1, XmmReg2); } + +define pcodeop pmovzxbq; +:PMOVZXBQ XmmReg, m16 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x32; XmmReg ... & m16 { XmmReg = pmovzxbq(XmmReg, m16); } +:PMOVZXBQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x32; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmovzxbq(XmmReg1, XmmReg2); } + +define pcodeop pmovzxwd; +:PMOVZXWD XmmReg, m64 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x33; XmmReg ... & m64 { XmmReg = pmovzxwd(XmmReg, m64); } +:PMOVZXWD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x33; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmovzxwd(XmmReg1, XmmReg2); } + +define pcodeop pmovzxwq; +:PMOVZXWQ XmmReg, m32 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x34; XmmReg ... & m32 { XmmReg = pmovzxwq(XmmReg, m32); } +:PMOVZXWQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x34; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmovzxwq(XmmReg1, XmmReg2); } + +define pcodeop pmovzxdq; +:PMOVZXDQ XmmReg, m64 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x35; XmmReg ... & m64 { XmmReg = pmovzxdq(XmmReg, m64); } +:PMOVZXDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x35; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = pmovzxdq(XmmReg1, XmmReg2); } + +:PTEST XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x17; XmmReg ... & m128 { + local tmp = m128 & XmmReg; + ZF = tmp == 0; + local tmp2 = m128 & ~XmmReg; + CF = tmp2 == 0; + AF = 0; + OF = 0; + PF = 0; + SF = 0; +} + +:PTEST XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x17; xmmmod=3 & XmmReg1 & XmmReg2 { + local tmp = XmmReg2 & XmmReg1; + ZF = tmp == 0; + local tmp2 = XmmReg2 & ~XmmReg1; + CF = tmp2 == 0; + AF = 0; + OF = 0; + PF = 0; + SF = 0; +} + +:PCMPEQQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x29; XmmReg ... & m128 +{ + XmmReg[0,64] = zext(XmmReg[0,64] == m128[0,64]) * 0xffffffffffffffff:8; + XmmReg[64,64] = zext(XmmReg[64,64] == m128[64,64]) * 0xffffffffffffffff:8; +} +:PCMPEQQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x29; xmmmod=3 & XmmReg1 & XmmReg2 +{ + XmmReg1[0,64] = zext(XmmReg1[0,64] == XmmReg2[0,64]) * 0xffffffffffffffff:8; + XmmReg1[64,64] = zext(XmmReg1[64,64] == XmmReg2[64,64]) * 0xffffffffffffffff:8; +} + +define pcodeop packusdw; +:PACKUSDW XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x2B; XmmReg ... & m128 { XmmReg = packusdw(XmmReg, m128); } +:PACKUSDW XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x2B; xmmmod=3 & XmmReg1 & XmmReg2 { XmmReg1 = packusdw(XmmReg1, XmmReg2); } + +define pcodeop movntdqa; +:MOVNTDQA XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x2A; XmmReg ... & m128 { XmmReg = movntdqa(XmmReg, m128); } + +#### +#### SSE4.2 instructions +#### + +define pcodeop crc32; +:CRC32 Reg32, rm8 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x38; byte=0xF0; Reg32 ... & check_Reg32_dest ... & rm8 { Reg32 = crc32(Reg32, rm8); build check_Reg32_dest; } +:CRC32 Reg32, rm16 is vexMode=0 & opsize=0 & $(PRE_F2) & byte=0x0F; byte=0x38; byte=0xF1; Reg32 ... & check_Reg32_dest ... & rm16 { Reg32 = crc32(Reg32, rm16); build check_Reg32_dest; } +:CRC32 Reg32, rm32 is vexMode=0 & opsize=1 & $(PRE_F2) & byte=0x0F; byte=0x38; byte=0xF1; Reg32 ... & check_Reg32_dest ... & rm32 { Reg32 = crc32(Reg32, rm32); build check_Reg32_dest; } +@ifdef IA64 +:CRC32 Reg32, rm8 is vexMode=0 & opsize=1 & $(PRE_F2) & $(REX) & byte=0x0F; byte=0x38; byte=0xF0; Reg32 ... & check_Reg32_dest ... & rm8 { Reg32 = crc32(Reg32, rm8); build check_Reg32_dest; } +:CRC32 Reg64, rm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F2) & $(REX_W) & byte=0x0F; byte=0x38; byte=0xF0; Reg64 ... & rm8 { Reg64 = crc32(Reg64, rm8); } +:CRC32 Reg64, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F2) & $(REX_W) & byte=0x0F; byte=0x38; byte=0xF1; Reg64 ... & rm64 { Reg64 = crc32(Reg64, rm64); } +@endif + +define pcodeop pcmpestri; +:PCMPESTRI XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x61; XmmReg ... & m128; imm8 { ECX = pcmpestri(XmmReg, m128, imm8:8); } +:PCMPESTRI XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x61; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { ECX = pcmpestri(XmmReg1, XmmReg2, imm8:8); } + +define pcodeop pcmpestrm; +:PCMPESTRM XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x60; XmmReg ... & m128; imm8 { XMM0 = pcmpestrm(XmmReg, m128, imm8:8); } +:PCMPESTRM XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x60; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XMM0 = pcmpestrm(XmmReg1, XmmReg2, imm8:8); } + +define pcodeop pcmpistri; +:PCMPISTRI XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x63; XmmReg ... & m128; imm8 { ECX = pcmpistri(XmmReg, m128, imm8:8); } +:PCMPISTRI XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x63; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { ECX = pcmpistri(XmmReg1, XmmReg2, imm8:8); } + +define pcodeop pcmpistrm; +:PCMPISTRM XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x62; XmmReg ... & m128; imm8 { XMM0 = pcmpistrm(XmmReg, m128, imm8:8); } +:PCMPISTRM XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x62; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XMM0 = pcmpistrm(XmmReg1, XmmReg2, imm8:8); } + +:PCMPGTQ XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0x37; XmmReg1 ... & XmmReg2_m128 +{ + XmmReg1[0,64] = 0xffffffffffffffff:8 * (zext(XmmReg1[0,64] s> XmmReg2_m128[0,64])); + XmmReg1[64,64] = 0xffffffffffffffff:8 * (zext(XmmReg1[64,64] s> XmmReg2_m128[64,64])); +} + +macro popcountflags(src){ + OF = 0:1; + SF = 0:1; + AF = 0:1; + CF = 0:1; + PF = 0:1; + ZF = (src == 0); +} +:POPCNT Reg16, rm16 is vexMode=0 & opsize=0 & $(PRE_F3) & byte=0x0F; byte=0xB8; Reg16 ... & rm16 { popcountflags(rm16); Reg16 = popcount(rm16); } +:POPCNT Reg32, rm32 is vexMode=0 & opsize=1 & $(PRE_F3) & byte=0x0F; byte=0xB8; Reg32 ... & check_Reg32_dest ... & rm32 { popcountflags(rm32); Reg32 = popcount(rm32); build check_Reg32_dest; } +@ifdef IA64 +:POPCNT Reg64, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & $(REX_W) & byte=0x0F; byte=0xB8; Reg64 ... & rm64 { popcountflags(rm64); Reg64 = popcount(rm64); } +@endif + +#### +#### AESNI instructions +#### + +define pcodeop aesdec; +:AESDEC XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xde; XmmReg1 ... & XmmReg2_m128 { + XmmReg1 = aesdec(XmmReg1, XmmReg2_m128); +} +:VAESDEC XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xde; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 { + XmmReg1 = aesdec(vexVVVV_XmmReg, XmmReg2_m128); + YmmReg1 = zext(XmmReg1); +} + +define pcodeop aesdeclast; +:AESDECLAST XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xdf; XmmReg1 ... & XmmReg2_m128 { + XmmReg1 = aesdeclast(XmmReg1, XmmReg2_m128); +} +:VAESDECLAST XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xdf; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 { + XmmReg1 = aesdeclast(vexVVVV_XmmReg, XmmReg2_m128); + YmmReg1 = zext(XmmReg1); +} + +define pcodeop aesenc; +:AESENC XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xdc; XmmReg1 ... & XmmReg2_m128 { + XmmReg1 = aesenc(XmmReg1, XmmReg2_m128); +} +:VAESENC XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xdc; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 { + XmmReg1 = aesenc(vexVVVV_XmmReg, XmmReg2_m128); + YmmReg1 = zext(XmmReg1); +} + +define pcodeop aesenclast; +:AESENCLAST XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xdd; XmmReg1 ... & XmmReg2_m128 { + XmmReg1 = aesenclast(XmmReg1, XmmReg2_m128); +} +:VAESENCLAST XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xdd; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 { + XmmReg1 = aesenclast(vexVVVV_XmmReg, XmmReg2_m128); + YmmReg1 = zext(XmmReg1); +} + +define pcodeop aesimc; +:AESIMC XmmReg1, XmmReg2_m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xdb; XmmReg1 ... & XmmReg2_m128 { + XmmReg1 = aesimc(XmmReg2_m128); +} +:VAESIMC XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0xdb; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 { + XmmReg1 = aesimc(XmmReg2_m128); + YmmReg1 = zext(XmmReg1); +} + +define pcodeop aeskeygenassist; +:AESKEYGENASSIST XmmReg1, XmmReg2_m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0xdf; XmmReg1 ... & XmmReg2_m128; imm8 { + XmmReg1 = aeskeygenassist(XmmReg2_m128, imm8:1); +} +:VAESKEYGENASSIST XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0xdf; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; imm8 { + XmmReg1 = aeskeygenassist(XmmReg2_m128, imm8:1); + YmmReg1 = zext(XmmReg1); +} + + + +#### +#### Deprecated 3DNow! instructions +#### + +define pcodeop PackedIntToFloatingDwordConv; +:PI2FD mmxreg, m64 is vexMode=0 & suffix3D=0x0D & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedIntToFloatingDwordConv(mmxreg, m64); } +:PI2FD mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0x0D & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedIntToFloatingDwordConv(mmxreg1, mmxreg2); } + +define pcodeop PackedFloatingToIntDwordConv; +:PF2ID mmxreg, m64 is vexMode=0 & suffix3D=0x1D & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingToIntDwordConv(mmxreg, m64); } +:PF2ID mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0x1D & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingToIntDwordConv(mmxreg1, mmxreg2); } + +define pcodeop PackedFloatingCompareGE; +:PFCMPGE mmxreg, m64 is vexMode=0 & suffix3D=0x90 & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingCompareGE(mmxreg, m64); } +:PFCMPGE mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0x90 & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingCompareGE(mmxreg1, mmxreg2); } + +define pcodeop PackedFloatingCompareGT; +:PFCMPGT mmxreg, m64 is vexMode=0 & suffix3D=0xA0 & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingCompareGT(mmxreg, m64); } +:PFCMPGT mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xA0 & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingCompareGT(mmxreg1, mmxreg2); } + +define pcodeop PackedFloatingCompareEQ; +:PFCMPEQ mmxreg, m64 is vexMode=0 & suffix3D=0xB0 & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingCompareEQ(mmxreg, m64); } +:PFCMPEQ mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xB0 & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingCompareEQ(mmxreg1, mmxreg2); } + +define pcodeop PackedFloatingAccumulate; +:PFACC mmxreg, m64 is vexMode=0 & suffix3D=0xAE & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingAccumulate(mmxreg, m64); } +:PFACC mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xAE & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingAccumulate(mmxreg1, mmxreg2); } + +define pcodeop PackedFloatingADD; +:PFADD mmxreg, m64 is vexMode=0 & suffix3D=0x9E & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingADD(mmxreg, m64); } +:PFADD mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0x9E & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingADD(mmxreg1, mmxreg2); } + +define pcodeop PackedFloatingSUB; +:PFSUB mmxreg, m64 is vexMode=0 & suffix3D=0x9A & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingSUB(mmxreg, m64); } +:PFSUB mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0x9A & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingSUB(mmxreg1, mmxreg2); } + +define pcodeop PackedFloatingSUBR; +:PFSUBR mmxreg, m64 is vexMode=0 & suffix3D=0xAA & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingSUBR(mmxreg, m64); } +:PFSUBR mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xAA & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingSUBR(mmxreg1, mmxreg2); } + +define pcodeop PackedFloatingMIN; +:PFMIN mmxreg, m64 is vexMode=0 & suffix3D=0x94 & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingMIN(mmxreg, m64); } +:PFMIN mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0x94 & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingMIN(mmxreg1, mmxreg2); } + +define pcodeop PackedFloatingMAX; +:PFMAX mmxreg, m64 is vexMode=0 & suffix3D=0xA4 & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingMAX(mmxreg, m64); } +:PFMAX mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xA4 & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingMAX(mmxreg1, mmxreg2); } + +define pcodeop PackedFloatingMUL; +:PFMUL mmxreg, m64 is vexMode=0 & suffix3D=0xB4 & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingMUL(mmxreg, m64); } +:PFMUL mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xB4 & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingMUL(mmxreg1, mmxreg2); } + +define pcodeop FloatingReciprocalAprox; +:PFRCP mmxreg, m64 is vexMode=0 & suffix3D=0x96 & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = FloatingReciprocalAprox(mmxreg, m64); } +:PFRCP mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0x96 & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = FloatingReciprocalAprox(mmxreg1, mmxreg2); } + +define pcodeop PackedFloatingReciprocalSQRAprox; +:PFRSQRT mmxreg, m64 is vexMode=0 & suffix3D=0x97 & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingReciprocalSQRAprox(mmxreg, m64); } +:PFRSQRT mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0x97 & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingReciprocalSQRAprox(mmxreg1, mmxreg2); } + +define pcodeop PackedFloatingReciprocalIter1; +:PFRCPIT1 mmxreg, m64 is vexMode=0 & suffix3D=0xA6 & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingReciprocalIter1(mmxreg, m64); } +:PFRCPIT1 mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xA6 & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingReciprocalIter1(mmxreg1, mmxreg2); } + +define pcodeop PackedFloatingReciprocalSQRIter1; +:PFRSQIT1 mmxreg, m64 is vexMode=0 & suffix3D=0xA7 & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingReciprocalSQRIter1(mmxreg, m64); } +:PFRSQIT1 mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xA7 & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingReciprocalSQRIter1(mmxreg1, mmxreg2); } + +define pcodeop PackedFloatingReciprocalIter2; +:PFRCPIT2 mmxreg, m64 is vexMode=0 & suffix3D=0xB6 & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingReciprocalIter2(mmxreg, m64); } +:PFRCPIT2 mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xB6 & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingReciprocalIter2(mmxreg1, mmxreg2); } + +define pcodeop PackedAverageUnsignedBytes; +:PAVGUSB mmxreg, m64 is vexMode=0 & suffix3D=0xBF & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedAverageUnsignedBytes(mmxreg, m64); } +:PAVGUSB mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xBF & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedAverageUnsignedBytes(mmxreg1, mmxreg2); } + +define pcodeop PackedAverageHighRoundedWord; +:PMULHRW mmxreg, m64 is vexMode=0 & suffix3D=0xB7 & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedAverageHighRoundedWord(mmxreg, m64); } +:PMULHRW mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xB7 & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedAverageHighRoundedWord(mmxreg1, mmxreg2); } + +define pcodeop FastExitMediaState; +:FEMMS is vexMode=0 & byte=0x0F; byte=0x0E { FastExitMediaState(); } + +#define pcodeop PrefetchDataIntoCache; +#:PREFETCH m8 is vexMode=0 & byte=0x0F; byte=0x18; m8 { PrefetchDataIntoCache(m8); } + +#define pcodeop PrefetchDataIntoCacheWrite; +#:PREFETCHW m8 is vexMode=0 & byte=0x0F; byte=0x0D; reg_opcode=1 ... & m8 { PrefetchDataIntoCacheWrite(m8); } + +# 3DNow! extensions + +define pcodeop PackedFloatingToIntWord; +:PF2IW mmxreg, m64 is vexMode=0 & suffix3D=0x1C & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingToIntWord(mmxreg, m64); } +:PF2IW mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0x1C & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingToIntWord(mmxreg1, mmxreg2); } + +define pcodeop PackedIntToFloatingWord; +:PI2FW mmxreg, m64 is vexMode=0 & suffix3D=0x0C & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedIntToFloatingWord(mmxreg, m64); } +:PI2FW mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0x0C & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedIntToFloatingWord(mmxreg1, mmxreg2); } + +define pcodeop PackedFloatingNegAccumulate; +:PFNACC mmxreg, m64 is vexMode=0 & suffix3D=0x8A & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingNegAccumulate(mmxreg, m64); } +:PFNACC mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0x8A & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingNegAccumulate(mmxreg1, mmxreg2); } + +define pcodeop PackedFloatingPosNegAccumulate; +:PFPNACC mmxreg, m64 is vexMode=0 & suffix3D=0x8E & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedFloatingPosNegAccumulate(mmxreg, m64); } +:PFPNACC mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0x8E & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedFloatingPosNegAccumulate(mmxreg1, mmxreg2); } + +define pcodeop PackedSwapDWords; +:PSWAPD mmxreg, m64 is vexMode=0 & suffix3D=0xBB & mandover=0 & byte=0x0F; byte=0x0F; mmxreg ... & m64 { mmxreg = PackedSwapDWords(mmxreg, m64); } +:PSWAPD mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xBB & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedSwapDWords(mmxreg1, mmxreg2); } + +define pcodeop MaskedMoveQWord; +:MASKMOVQ mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF7; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = MaskedMoveQWord(mmxreg1, mmxreg2); } + +} # end with : lockprefx=0 diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/lockable.sinc b/python/icicle/Ghidra/Processors/x86/data/languages/lockable.sinc new file mode 100644 index 0000000..be1876b --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/lockable.sinc @@ -0,0 +1,1380 @@ +# The LOCK prefix is only valid for certain instructions, otherwise, from the +# Intel instruction manual: +# An undefined opcode exception will also be generated if the LOCK prefix +# is used with any instruction not in the above list. +# The instructions in this file have their non-lockable counterparts in ia.sinc + +:ADC^lockx spec_m8,imm8 is vexMode=0 & lockx & unlock & $(BYTE_80_82); spec_m8 & reg_opcode=2 ... ; imm8 +{ + build lockx; + build spec_m8; + addCarryFlags( spec_m8, imm8:1 ); + resultflags( spec_m8 ); + build unlock; +} + +:ADC^lockx spec_m16,imm16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x81; spec_m16 & reg_opcode=2 ...; imm16 +{ + build lockx; + build spec_m16; + addCarryFlags( spec_m16, imm16:2 ); + resultflags( spec_m16 ); + build unlock; +} + +:ADC^lockx spec_m32,imm32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x81; spec_m32 & reg_opcode=2 ...; imm32 +{ + build lockx; + build spec_m32; + addCarryFlags( spec_m32, imm32:4 ); + resultflags( spec_m32 ); + build unlock; +} + +@ifdef IA64 +:ADC^lockx spec_m64,simm32 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x81; spec_m64 & reg_opcode=2 ...; simm32 +{ + build lockx; + build spec_m64; + addCarryFlags( spec_m64, simm32 ); + resultflags( spec_m64 ); + build unlock; +} +@endif + +:ADC^lockx spec_m16,simm8_16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x83; spec_m16 & reg_opcode=2 ...; simm8_16 +{ + build lockx; + build spec_m16; + addCarryFlags( spec_m16, simm8_16 ); + resultflags( spec_m16 ); + build unlock; +} + +:ADC^lockx spec_m32,simm8_32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x83; spec_m32 & reg_opcode=2 ...; simm8_32 +{ + build lockx; + build spec_m32; + addCarryFlags( spec_m32, simm8_32 ); + resultflags( spec_m32 ); + build unlock; +} + +@ifdef IA64 +:ADC^lockx spec_m64,simm8_64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x83; spec_m64 & reg_opcode=2 ...; simm8_64 +{ + build lockx; + build spec_m64; + addCarryFlags( spec_m64, simm8_64 ); + resultflags( spec_m64 ); + build unlock; +} +@endif + +:ADC^lockx m8,Reg8 is vexMode=0 & lockx & unlock & byte=0x10; m8 & Reg8 ... +{ + build lockx; + build m8; + addCarryFlags( m8, Reg8 ); + resultflags( m8 ); + build unlock; +} + +:ADC^lockx m16,Reg16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x11; m16 & Reg16 ... +{ + build lockx; + build m16; + addCarryFlags( m16, Reg16 ); + resultflags( m16 ); + build unlock; +} + +:ADC^lockx m32,Reg32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x11; m32 & Reg32 ... +{ + build lockx; + build m32; + addCarryFlags( m32, Reg32 ); + resultflags( m32 ); + build unlock; +} + +@ifdef IA64 +:ADC^lockx m64,Reg64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x11; m64 & Reg64 ... +{ + build lockx; + build m64; + addCarryFlags( m64, Reg64 ); + resultflags( m64 ); + build unlock; +} +@endif + +:ADD^lockx spec_m8,imm8 is vexMode=0 & lockx & unlock & $(BYTE_80_82); spec_m8 & reg_opcode=0 ...; imm8 +{ + build lockx; + build spec_m8; + addflags( spec_m8,imm8 ); + spec_m8 = spec_m8 + imm8; + resultflags( spec_m8); + build unlock; +} + +:ADD^lockx spec_m16,imm16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x81; spec_m16 & reg_opcode=0 ...; imm16 +{ + build lockx; + build spec_m16; + addflags( spec_m16,imm16); + spec_m16 = spec_m16 + imm16; + resultflags( spec_m16); + build unlock; +} + +:ADD^lockx spec_m32,imm32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x81; spec_m32 & reg_opcode=0 ...; imm32 +{ + build lockx; + build spec_m32; + addflags( spec_m32,imm32); + spec_m32 = spec_m32 + imm32; + resultflags( spec_m32); + build unlock; +} + +@ifdef IA64 +:ADD^lockx spec_m64,simm32 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x81; spec_m64 & reg_opcode=0 ...; simm32 +{ + build lockx; + build spec_m64; + addflags( spec_m64,simm32); + spec_m64 = spec_m64 + simm32; + resultflags( spec_m64); + build unlock; +} +@endif + +:ADD^lockx spec_m16,simm8_16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x83; spec_m16 & reg_opcode=0 ...; simm8_16 +{ + build lockx; + build spec_m16; + addflags( spec_m16,simm8_16); + spec_m16 = spec_m16 + simm8_16; + resultflags( spec_m16); + build unlock; +} + +:ADD^lockx spec_m32,simm8_32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x83; spec_m32 & reg_opcode=0 ...; simm8_32 +{ + build lockx; + build spec_m32; + addflags( spec_m32,simm8_32); + spec_m32 = spec_m32 + simm8_32; + resultflags( spec_m32); + build unlock; +} + +@ifdef IA64 +:ADD^lockx spec_m64,simm8_64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x83; spec_m64 & reg_opcode=0 ...; simm8_64 +{ + build lockx; + build spec_m64; + addflags( spec_m64,simm8_64); + spec_m64 = spec_m64 + simm8_64; + resultflags( spec_m64); + build unlock; +} +@endif + +:ADD^lockx m8,Reg8 is vexMode=0 & lockx & unlock & byte=0x00; m8 & Reg8 ... +{ + build lockx; + build m8; + addflags( m8,Reg8 ); + m8 = m8 + Reg8; + resultflags( m8); + build unlock; +} + +:ADD^lockx m16,Reg16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x1; m16 & Reg16 ... +{ + build lockx; + build m16; + addflags( m16,Reg16); + m16 = m16 + Reg16; + resultflags( m16); + build unlock; +} + +:ADD^lockx m32,Reg32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x1; m32 & Reg32 ... +{ + build lockx; + build m32; + addflags( m32,Reg32); + m32 = m32 + Reg32; + resultflags( m32); + build unlock; +} + +@ifdef IA64 +:ADD^lockx m64,Reg64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x1; m64 & Reg64 ... +{ + build lockx; + build m64; + addflags( m64,Reg64); + m64 = m64 + Reg64; + resultflags( m64); + build unlock; +} +@endif + +:AND^lockx m8,imm8 is vexMode=0 & lockx & unlock & $(BYTE_80_82); m8 & reg_opcode=4 ...; imm8 +{ + build lockx; + build m8; + logicalflags(); + m8 = m8 & imm8; + resultflags( m8); + build unlock; +} + +:AND^lockx m16,imm16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x81; m16 & reg_opcode=4 ...; imm16 +{ + build lockx; + build m16; + logicalflags(); + m16 = m16 & imm16; + resultflags( m16); + build unlock; +} + +:AND^lockx m32,imm32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x81; m32 & reg_opcode=4 ...; imm32 +{ + build lockx; + build m32; + logicalflags(); + m32 = m32 & imm32; + resultflags( m32); + build unlock; +} + +@ifdef IA64 +:AND^lockx m64,simm32 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x81; m64 & reg_opcode=4 ...; simm32 +{ + build lockx; + build m64; + logicalflags(); + m64 = m64 & simm32; + resultflags( m64); + build unlock; +} +@endif + +:AND^lockx m16,usimm8_16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x83; m16 & reg_opcode=4 ...; usimm8_16 +{ + build lockx; + build m16; + logicalflags(); + m16 = m16 & usimm8_16; + resultflags( m16); + build unlock; +} + +:AND^lockx m32,usimm8_32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x83; m32 & reg_opcode=4 ...; usimm8_32 +{ + build lockx; + build m32; + logicalflags(); + m32 = m32 & usimm8_32; + resultflags( m32); + build unlock; +} + +@ifdef IA64 +:AND^lockx m64,usimm8_64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x83; m64 & reg_opcode=4 ...; usimm8_64 +{ + build lockx; + build m64; + logicalflags(); + m64 = m64 & usimm8_64; + resultflags( m64); + build unlock; +} +@endif + +:AND^lockx m8,Reg8 is vexMode=0 & lockx & unlock & byte=0x20; m8 & Reg8 ... +{ + build lockx; + build m8; + logicalflags(); + m8 = m8 & Reg8; + resultflags( m8); + build unlock; +} + +:AND^lockx m16,Reg16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x21; m16 & Reg16 ... +{ + build lockx; + build m16; + logicalflags(); + m16 = m16 & Reg16; + resultflags( m16); + build unlock; +} + +:AND^lockx m32,Reg32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x21; m32 & Reg32 ... +{ + build lockx; + build m32; + logicalflags(); + m32 = m32 & Reg32; + resultflags( m32); + build unlock; +} + +@ifdef IA64 +:AND^lockx m64,Reg64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x21; m64 & Reg64 ... +{ + build lockx; + build m64; + logicalflags(); + m64 = m64 & Reg64; + resultflags( m64); + build unlock; +} +@endif + +:BTC^lockx Mem,Reg16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0xf; byte=0xbb; Mem & Reg16 ... +{ + build lockx; + build Mem; + local ptr = Mem + (sext(Reg16) s>> 3); + local bit=Reg16&7; + local val = (*:1 ptr >> bit) & 1; + *:1 ptr= *:1 ptr ^(1<> 3); +@else + local ptr = Mem + (Reg32 s>> 3); +@endif + local bit=Reg32&7; + local val = (*:1 ptr >> bit) & 1; + *:1 ptr = *:1 ptr ^ (1<> 3); + local bit=Reg64&7; + local val = (*:1 ptr >> bit) & 1; + *:1 ptr = *:1 ptr ^ (1<>bit)&1; + m16=m16^(1<>bit)&1; + CF=(val!=0); + m32=m32^(1<>bit)&1; + m64=m64^(1<> 3); + local bit=Reg16&7; + local val=(*:1 ptr >> bit) & 1; + *:1 ptr = *:1 ptr & ~(1<> 3); +@else + local ptr = Mem + (Reg32 s>> 3); +@endif + local bit = Reg32 & 7; + local val = (*:1 ptr >> bit) & 1; + *:1 ptr = *:1 ptr & ~(1<> 3); + local bit = Reg64 & 7; + local val = (*:1 ptr >> bit) & 1; + *:1 ptr = *:1 ptr & ~(1<>bit)&1; + m16=m16 & ~(1<>bit)&1; + CF=(val!=0); + m32=m32 & ~(1<>bit)&1; + m64=m64 & ~(1<> 3); + local bit = Reg16&7; + local val = (*:1 ptr >> bit) & 1; + *:1 ptr = *:1 ptr | (1<>3); +@else + local ptr = Mem + (Reg32 s>>3); +@endif + local bit = Reg32 & 7; + local val = (*:1 ptr >> bit) & 1; + *:1 ptr = *:1 ptr | (1<>3); + local bit = Reg64 & 7; + local val = (*:1 ptr >> bit) & 1; + *:1 ptr = *:1 ptr | (1<>bit)&1; + m16=m16 | (1<>bit)&1; + CF=(val!=0); + m32=m32 | (1<>bit)&1; + m64=m64 | (1<; + EAX = m32; + build check_EAX_dest; + goto ; + + m32 = Reg32; + + build unlock; +} + +@ifdef IA64 +:CMPXCHG^lockx m64,Reg64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0xf; byte=0xb1; m64 & Reg64 ... +{ + build lockx; + build m64; + subflags(RAX,m64); + local tmp=RAX-m64; + resultflags(tmp); + local diff = m64^Reg64; + m64 = m64 ^ (zext(ZF) * diff); + diff = RAX ^ m64; + RAX = RAX ^ (zext(ZF==0) * diff); + build unlock; +} +@endif + +:CMPXCHG8B^lockx m64 is vexMode=0 & lockx & unlock & byte=0xf; byte=0xc7; ( mod != 0b11 & reg_opcode=1 ) ... & m64 +{ + build lockx; + build m64; + ZF = ((zext(EDX) << 32) | zext(EAX)) == m64; + if (ZF == 1) goto ; + EDX = m64(4); + EAX = m64:4; + goto ; + + m64 = (zext(ECX) << 32) | zext(EBX); + + build unlock; +} + +@ifdef IA64 +:CMPXCHG16B^lockx m128 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0xf; byte=0xc7; ( mod != 0b11 & reg_opcode=1 ) ... & ( m128 ) { + build lockx; + build m128; + ZF = ((zext(RDX) << 64) | zext(RAX)) == m128; + if (ZF == 1) goto ; + RDX = m128(8); + RAX = m128:8; + goto ; + + m128 = ((zext(RCX) << 64) | zext(RBX)); + + build unlock; +} +@endif + +:DEC^lockx spec_m8 is vexMode=0 & lockx & unlock & byte=0xfe; spec_m8 & reg_opcode=1 ... +{ + build lockx; + build spec_m8; + OF = sborrow(spec_m8,1); + spec_m8 = spec_m8 - 1; + resultflags( spec_m8); + build unlock; +} + +:DEC^lockx spec_m16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0xff; spec_m16 & reg_opcode=1 ... +{ + build lockx; + build spec_m16; + OF = sborrow(spec_m16,1); + spec_m16 = spec_m16 - 1; + resultflags(spec_m16); + build unlock; +} + +:DEC^lockx spec_m32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0xff; spec_m32 & reg_opcode=1 ... +{ + build lockx; + build spec_m32; + OF = sborrow(spec_m32,1); + spec_m32 = spec_m32 - 1; + resultflags(spec_m32); + build unlock; +} + +@ifdef IA64 +:DEC^lockx spec_m64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0xff; spec_m64 & reg_opcode=1 ... +{ + build lockx; + build spec_m64; + OF = sborrow(spec_m64,1); + spec_m64 = spec_m64 - 1; + resultflags(spec_m64); + build unlock; +} +@endif + +:INC^lockx spec_m8 is vexMode=0 & lockx & unlock & byte=0xfe; spec_m8 ... +{ + build lockx; + build spec_m8; + OF = scarry(spec_m8,1); + spec_m8 = spec_m8 + 1; + resultflags( spec_m8); + build unlock; +} + +:INC^lockx spec_m16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0xff; spec_m16 ... +{ + build lockx; + build spec_m16; + OF = scarry(spec_m16,1); + spec_m16 = spec_m16 + 1; + resultflags(spec_m16); + build unlock; +} + +:INC^lockx spec_m32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0xff; spec_m32 ... +{ + build lockx; + build spec_m32; + OF = scarry(spec_m32,1); + spec_m32 = spec_m32 + 1; + resultflags(spec_m32); + build unlock; +} + +@ifdef IA64 +:INC^lockx spec_m64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0xff; spec_m64 ... +{ + build lockx; + build spec_m64; + OF = scarry(spec_m64,1); + spec_m64 = spec_m64 + 1; + resultflags(spec_m64); + build unlock; +} +@endif + +:NEG^lockx m8 is vexMode=0 & lockx & unlock & byte=0xf6; m8 & reg_opcode=3 ... +{ + build lockx; + build m8; + negflags(m8); + m8 = -m8; + resultflags(m8 ); + build unlock; +} + +:NEG^lockx m16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0xf7; m16 & reg_opcode=3 ... +{ + build lockx; + build m16; + negflags(m16); + m16 = -m16; + resultflags(m16); + build unlock; +} + +:NEG^lockx m32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0xf7; m32 & reg_opcode=3 ... +{ + build lockx; + build m32; + negflags(m32); + m32 = -m32; + resultflags(m32); + build unlock; +} + +@ifdef IA64 +:NEG^lockx m64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0xf7; m64 & reg_opcode=3 ... +{ + build lockx; + build m64; + negflags(m64); + m64 = -m64; + resultflags(m64); + build unlock; +} +@endif + +:NOT^lockx m8 is vexMode=0 & lockx & unlock & byte=0xf6; m8 & reg_opcode=2 ... +{ + build lockx; + build m8; + m8 = ~m8; + build unlock; +} + +:NOT^lockx m16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0xf7; m16 & reg_opcode=2 ... +{ + build lockx; + build m16; + m16 = ~m16; + build unlock; +} + +:NOT^lockx m32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0xf7; m32 & reg_opcode=2 ... +{ + build lockx; + build m32; + m32 = ~m32; + build unlock; +} + +@ifdef IA64 +:NOT^lockx m64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0xf7; m64 & reg_opcode=2 ... +{ + build lockx; + build m64; + m64 = ~m64; + build unlock; +} +@endif + +:OR^lockx spec_m8,imm8 is vexMode=0 & lockx & unlock & $(BYTE_80_82); spec_m8 & reg_opcode=1 ...; imm8 +{ + build lockx; + build spec_m8; + logicalflags(); + spec_m8 = spec_m8 | imm8; + resultflags( spec_m8); + build unlock; +} + +:OR^lockx spec_m16,imm16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x81; spec_m16 & reg_opcode=1 ...; imm16 +{ + build lockx; + build spec_m16; + logicalflags(); + spec_m16 = spec_m16 | imm16; + resultflags( spec_m16); + build unlock; +} + +:OR^lockx spec_m32,imm32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x81; spec_m32 & reg_opcode=1 ...; imm32 +{ + build lockx; + build spec_m32; + logicalflags(); + spec_m32 = spec_m32 | imm32; + resultflags( spec_m32); + build unlock; +} + +@ifdef IA64 +:OR^lockx spec_m64,simm32 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x81; spec_m64 & reg_opcode=1 ...; simm32 +{ + build lockx; + build spec_m64; + logicalflags(); + tmp:8 = spec_m64; + spec_m64 = tmp | simm32; + resultflags( spec_m64); + build unlock; +} +@endif + +:OR^lockx spec_m16,usimm8_16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x83; spec_m16 & reg_opcode=1 ...; usimm8_16 +{ + build lockx; + build spec_m16; + logicalflags(); + spec_m16 = spec_m16 | usimm8_16; + resultflags( spec_m16); + build unlock; +} + +:OR^lockx spec_m32,usimm8_32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x83; spec_m32 & reg_opcode=1 ...; usimm8_32 +{ + build lockx; + build spec_m32; + logicalflags(); + spec_m32 = spec_m32 | usimm8_32; + resultflags( spec_m32); + build unlock; +} + +@ifdef IA64 +:OR^lockx spec_m64,usimm8_64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x83; spec_m64 & reg_opcode=1 ...; usimm8_64 +{ + build lockx; + build spec_m64; + logicalflags(); + spec_m64 = spec_m64 | usimm8_64; + resultflags( spec_m64); + build unlock; +} +@endif + +:OR^lockx m8,Reg8 is vexMode=0 & lockx & unlock & byte=0x8; m8 & Reg8 ... +{ + build lockx; + build m8; + logicalflags(); + m8 = m8 | Reg8; + resultflags( m8); + build unlock; +} + +:OR^lockx m16,Reg16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x9; m16 & Reg16 ... +{ + build lockx; + build m16; + logicalflags(); + m16 = m16 | Reg16; + resultflags( m16); + build unlock; +} + +:OR^lockx m32,Reg32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x9; m32 & Reg32 ... +{ + build lockx; + build m32; + logicalflags(); + m32 = m32 | Reg32; + resultflags( m32); + build unlock; +} + +@ifdef IA64 +:OR^lockx m64,Reg64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x9; m64 & Reg64 ... +{ + build lockx; + build m64; + logicalflags(); + m64 = m64 | Reg64; + resultflags( m64); + build unlock; +} +@endif + +:SBB^lockx m8,imm8 is vexMode=0 & lockx & unlock & $(BYTE_80_82); m8 & reg_opcode=3 ...; imm8 +{ + build lockx; + build m8; + subCarryFlags( m8, imm8 ); + resultflags(m8); + build unlock; +} + +:SBB^lockx m16,imm16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x81; m16 & reg_opcode=3 ...; imm16 +{ + build lockx; + build m16; + subCarryFlags( m16, imm16 ); + resultflags(m16); + build unlock; +} + +:SBB^lockx m32,imm32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x81; m32 & reg_opcode=3 ...; imm32 +{ + build lockx; + build m32; + subCarryFlags( m32, imm32 ); + resultflags(m32); + build unlock; +} + +@ifdef IA64 +:SBB^lockx m64,imm32 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x81; m64 & reg_opcode=3 ...; imm32 +{ + build lockx; + build m64; + subCarryFlags( m64, imm32 ); + resultflags(m64); + build unlock; +} +@endif + +:SBB^lockx m16,simm8_16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x83; m16 & reg_opcode=3 ...; simm8_16 +{ + build lockx; + build m16; + subCarryFlags( m16, simm8_16 ); + resultflags(m16); + build unlock; +} + +:SBB^lockx m32,simm8_32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x83; m32 & reg_opcode=3 ...; simm8_32 +{ + build lockx; + build m32; + subCarryFlags( m32, simm8_32 ); + resultflags(m32); + build unlock; +} + +@ifdef IA64 +:SBB^lockx m64,simm8_64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x83; m64 & reg_opcode=3 ...; simm8_64 +{ + build lockx; + build m64; + subCarryFlags( m64, simm8_64 ); + resultflags(m64); + build unlock; +} +@endif + +:SBB^lockx m8,Reg8 is vexMode=0 & lockx & unlock & byte=0x18; m8 & Reg8 ... +{ + build lockx; + build m8; + subCarryFlags( m8, Reg8 ); + resultflags(m8); + build unlock; +} + +:SBB^lockx m16,Reg16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x19; m16 & Reg16 ... +{ + build lockx; + build m16; + subCarryFlags( m16, Reg16 ); + resultflags(m16); + build unlock; +} + +:SBB^lockx m32,Reg32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x19; m32 & Reg32 ... +{ + build lockx; + build m32; + subCarryFlags( m32, Reg32 ); + resultflags(m32); + build unlock; +} + +@ifdef IA64 +:SBB^lockx m64,Reg64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x19; m64 & Reg64 ... +{ + build lockx; + build m64; + subCarryFlags( m64, Reg64 ); + resultflags(m64); + build unlock; +} +@endif + +:SUB^lockx spec_m8,imm8 is vexMode=0 & lockx & unlock & $(BYTE_80_82); spec_m8 & reg_opcode=5 ...; imm8 +{ + build lockx; + build spec_m8; + subflags( spec_m8,imm8 ); + spec_m8 = spec_m8 - imm8; + resultflags( spec_m8); + build unlock; +} + +:SUB^lockx spec_m16,imm16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x81; spec_m16 & reg_opcode=5 ...; imm16 +{ + build lockx; + build spec_m16; + subflags( spec_m16,imm16); + spec_m16 = spec_m16 - imm16; + resultflags( spec_m16); + build unlock; +} + +:SUB^lockx spec_m32,imm32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x81; spec_m32 & reg_opcode=5 ...; imm32 +{ + build lockx; + build spec_m32; + subflags( spec_m32,imm32); + spec_m32 = spec_m32 - imm32; + resultflags( spec_m32); + build unlock; +} + +@ifdef IA64 +:SUB^lockx spec_m64,simm32 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x81; spec_m64 & reg_opcode=5 ...; simm32 +{ + build lockx; + build spec_m64; + subflags( spec_m64,simm32); + spec_m64 = spec_m64 - simm32; + resultflags( spec_m64); + build unlock; +} +@endif + +:SUB^lockx spec_m16,simm8_16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x83; spec_m16 & reg_opcode=5 ...; simm8_16 +{ + build lockx; + build spec_m16; + subflags( spec_m16,simm8_16); + spec_m16 = spec_m16 - simm8_16; + resultflags( spec_m16); + build unlock; +} + +:SUB^lockx spec_m32,simm8_32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x83; spec_m32 & reg_opcode=5 ...; simm8_32 +{ + build lockx; + build spec_m32; + subflags( spec_m32,simm8_32); + spec_m32 = spec_m32 - simm8_32; + resultflags( spec_m32); + build unlock; +} + +@ifdef IA64 +:SUB^lockx spec_m64,simm8_64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x83; spec_m64 & reg_opcode=5 ...; simm8_64 +{ + build lockx; + build spec_m64; + subflags( spec_m64,simm8_64); + spec_m64 = spec_m64 - simm8_64; + resultflags( spec_m64); + build unlock; +} +@endif + +:SUB^lockx m8,Reg8 is vexMode=0 & lockx & unlock & byte=0x28; m8 & Reg8 ... +{ + build lockx; + build m8; + subflags( m8,Reg8 ); + m8 = m8 - Reg8; + resultflags( m8); + build unlock; +} + +:SUB^lockx m16,Reg16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x29; m16 & Reg16 ... +{ + build lockx; + build m16; + subflags( m16,Reg16); + m16 = m16 - Reg16; + resultflags( m16); + build unlock; +} + +:SUB^lockx m32,Reg32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x29; m32 & Reg32 ... +{ + build lockx; + build m32; + subflags( m32,Reg32); + m32 = m32 - Reg32; + resultflags( m32); + build unlock; +} + +@ifdef IA64 +:SUB^lockx m64,Reg64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x29; m64 & Reg64 ... +{ + build lockx; + build m64; + subflags( m64,Reg64); + m64 = m64 - Reg64; + resultflags( m64); + build unlock; +} +@endif + +:XADD^lockx m8,Reg8 is vexMode=0 & lockx & unlock & byte=0x0F; byte=0xC0; m8 & Reg8 ... +{ + build lockx; + build m8; + addflags( m8,Reg8 ); + local tmp = m8 + Reg8; + Reg8 = m8; + m8 = tmp; + resultflags(tmp); + build unlock; +} + +:XADD^lockx m16,Reg16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x0F; byte=0xC1; m16 & Reg16 ... +{ + build lockx; + build m16; + addflags(m16,Reg16); + local tmp = m16 + Reg16; + Reg16 = m16; + m16 = tmp; + resultflags(tmp); + build unlock; +} + +:XADD^lockx m32,Reg32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x0F; byte=0xC1; m32 & Reg32 & check_Reg32_dest ... +{ + build lockx; + build m32; + addflags(m32,Reg32); + local tmp = m32 + Reg32; + Reg32 = m32; + build check_Reg32_dest; + m32 = tmp; + resultflags(tmp); + build unlock; +} + +@ifdef IA64 +:XADD^lockx m64,Reg64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x0F; byte=0xC1; m64 & Reg64 ... +{ + build lockx; + build m64; + addflags(m64,Reg64); + local tmp = m64 + Reg64; + Reg64 = m64; + m64 = tmp; + resultflags(tmp); + build unlock; +} +@endif + +# XCHG with memory operands always asserts a lock signal regardless of prefix presence +:XCHG^xacq_xrel_prefx^alwaysLock m8,Reg8 is vexMode=0 & xacq_xrel_prefx & alwaysLock & byte=0x86; m8 & Reg8 ... +{ + build xacq_xrel_prefx; + build alwaysLock; + build m8; + local tmp = m8; + m8 = Reg8; + Reg8 = tmp; + UNLOCK(); +} + +:XCHG^xacq_xrel_prefx^alwaysLock m16,Reg16 is vexMode=0 & xacq_xrel_prefx & alwaysLock & opsize=0 & byte=0x87; m16 & Reg16 ... +{ + build xacq_xrel_prefx; + build alwaysLock; + build m16; + local tmp = m16; + m16 = Reg16; + Reg16 = tmp; + UNLOCK(); +} + +:XCHG^xacq_xrel_prefx^alwaysLock m32,Reg32 is vexMode=0 & xacq_xrel_prefx & alwaysLock & opsize=1 & byte=0x87; m32 & Reg32 ... +{ + build xacq_xrel_prefx; + build alwaysLock; + build m32; + local tmp = m32; + m32 = Reg32; + Reg32 = tmp; + UNLOCK(); +} + +@ifdef IA64 +:XCHG^xacq_xrel_prefx^alwaysLock m64,Reg64 is $(LONGMODE_ON) & vexMode=0 & xacq_xrel_prefx & alwaysLock & opsize=2 & byte=0x87; m64 & Reg64 ... +{ + build xacq_xrel_prefx; + build alwaysLock; + build m64; + local tmp = m64; + m64 = Reg64; + Reg64 = tmp; + UNLOCK(); +} +@endif + +:XOR^lockx spec_m8,imm8 is vexMode=0 & lockx & unlock & $(BYTE_80_82); spec_m8 & reg_opcode=6 ...; imm8 +{ + build lockx; + build spec_m8; + logicalflags(); + spec_m8 = spec_m8 ^ imm8; + resultflags( spec_m8); + build unlock; +} + +:XOR^lockx spec_m16,imm16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x81; spec_m16 & reg_opcode=6 ...; imm16 +{ + build lockx; + build spec_m16; + logicalflags(); + spec_m16 = spec_m16 ^ imm16; + resultflags( spec_m16); + build unlock; +} + +:XOR^lockx spec_m32,imm32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x81; spec_m32 & reg_opcode=6 ...; imm32 +{ + build lockx; + build spec_m32; + logicalflags(); + spec_m32 = spec_m32 ^ imm32; + resultflags( spec_m32); + build unlock; +} + +@ifdef IA64 +:XOR^lockx spec_m64,simm32 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x81; spec_m64 & reg_opcode=6 ...; simm32 +{ + build lockx; + build spec_m64; + logicalflags(); + spec_m64 = spec_m64 ^ simm32; + resultflags( spec_m64); + build unlock; +} +@endif + +:XOR^lockx spec_m16,usimm8_16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x83; spec_m16 & reg_opcode=6 ...; usimm8_16 +{ + build lockx; + build spec_m16; + logicalflags(); + spec_m16 = spec_m16 ^ usimm8_16; + resultflags( spec_m16); + build unlock; +} + +:XOR^lockx spec_m32,usimm8_32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x83; spec_m32 & reg_opcode=6 ...; usimm8_32 +{ + build lockx; + build spec_m32; + logicalflags(); + spec_m32 = spec_m32 ^ usimm8_32; + resultflags( spec_m32); + build unlock; +} + +@ifdef IA64 +:XOR^lockx spec_m64,usimm8_64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x83; spec_m64 & reg_opcode=6 ...; usimm8_64 +{ + build lockx; + build spec_m64; + logicalflags(); + spec_m64 = spec_m64 ^ usimm8_64; + resultflags( spec_m64); + build unlock; +} +@endif + +:XOR^lockx m8,Reg8 is vexMode=0 & lockx & unlock & byte=0x30; m8 & Reg8 ... +{ + build lockx; + build m8; + logicalflags(); + m8 = m8 ^ Reg8; + resultflags( m8); + build unlock; +} + +:XOR^lockx m16,Reg16 is vexMode=0 & lockx & unlock & opsize=0 & byte=0x31; m16 & Reg16 ... +{ + build lockx; + build m16; + logicalflags(); + m16 = m16 ^ Reg16; + resultflags( m16); + build unlock; +} + +:XOR^lockx m32,Reg32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x31; m32 & Reg32 ... +{ + build lockx; + build m32; + logicalflags(); + m32 = m32 ^ Reg32; + resultflags( m32); + build unlock; +} + +@ifdef IA64 +:XOR^lockx m64,Reg64 is $(LONGMODE_ON) & vexMode=0 & lockx & unlock & opsize=2 & byte=0x31; m64 & Reg64 ... +{ + build lockx; + build m64; + logicalflags(); + m64 = m64 ^ Reg64; + resultflags( m64); + build unlock; +} +@endif diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/lzcnt.sinc b/python/icicle/Ghidra/Processors/x86/data/languages/lzcnt.sinc new file mode 100644 index 0000000..6927814 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/lzcnt.sinc @@ -0,0 +1,32 @@ +macro lzcntflags(input, output) { + ZF = (output == 0); + CF = (input == 0); + # OF, SF, PF, AF are undefined +} + +#### +#### LZCNT instructions +#### + + +:LZCNT Reg16, rm16 is vexMode=0 & opsize=0 & $(PRE_66) & $(PRE_F3) & byte=0x0F; byte=0xBD; Reg16 ... & rm16 { + + Reg16 = lzcount(rm16); + lzcntflags(rm16, Reg16); +} + +:LZCNT Reg32, rm32 is vexMode=0 & opsize=1 & $(PRE_F3) & byte=0x0F; byte=0xBD; Reg32 ... & check_Reg32_dest ... & rm32 { + + Reg32 = lzcount(rm32); + lzcntflags(rm32, Reg32); + build check_Reg32_dest; +} + +@ifdef IA64 +:LZCNT Reg64, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & $(REX_W) & byte=0x0F; byte=0xBD; Reg64 ... & rm64 { + + Reg64 = lzcount(rm64); + lzcntflags(rm64, Reg64); +} +@endif + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/macros.sinc b/python/icicle/Ghidra/Processors/x86/data/languages/macros.sinc new file mode 100644 index 0000000..1a199e1 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/macros.sinc @@ -0,0 +1,3 @@ +macro conditionalAssign(dest, cond, trueVal, falseVal) { + dest = zext(cond) * trueVal | zext(!cond) * falseVal; +} \ No newline at end of file diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/mpx.sinc b/python/icicle/Ghidra/Processors/x86/data/languages/mpx.sinc new file mode 100644 index 0000000..db600d4 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/mpx.sinc @@ -0,0 +1,234 @@ +define pcodeop br_exception; + + +# BNDMK needs the base address register only +# - if no base register, needs 0 + +@ifdef IA64 +bndmk_addr64: [Rmr64] is mod=0 & Rmr64 { export Rmr64; } +bndmk_addr64: [Rmr64 + simm8_64] is mod=1 & Rmr64; simm8_64 { export Rmr64; } +bndmk_addr64: [simm32_64 + Rmr64] is mod=2 & Rmr64; simm32_64 { export Rmr64; } +bndmk_addr64: [Rmr64] is mod=1 & r_m!=4 & Rmr64; simm8=0 { export Rmr64; } +bndmk_addr64: [Rmr64] is mod=2 & r_m!=4 & Rmr64; simm32=0 { export Rmr64; } +#invalid bndmk_addr64: [riprel] is mod=0 & r_m=5; simm32 [ riprel=inst_next+simm32; ] { export *[const]:8 riprel; } +bndmk_addr64: [Base64 + Index64*ss] is mod=0 & r_m=4; Index64 & Base64 & ss { export Base64; } +bndmk_addr64: [Base64] is mod=0 & r_m=4; rexXprefix=0 & index64=4 & Base64 { export Base64; } +bndmk_addr64: [simm32_64 + Index64*ss] is mod=0 & r_m=4; Index64 & base64=5 & ss; simm32_64 { tmp:8 = 0; export tmp; } +bndmk_addr64: [Index64*ss] is mod=0 & r_m=4; Index64 & base64=5 & ss; imm32=0 { tmp:8 = 0; export tmp; } +bndmk_addr64: [simm32_64] is mod=0 & r_m=4; rexXprefix=0 & index64=4 & base64=5; simm32_64 { tmp:8 = 0; export tmp; } +bndmk_addr64: [Base64 + Index64*ss + simm8_64] is mod=1 & r_m=4; Index64 & Base64 & ss; simm8_64 { export Base64; } +bndmk_addr64: [Base64 + Index64*ss] is mod=1 & r_m=4; Index64 & Base64 & ss; simm8=0 { export Base64; } +bndmk_addr64: [Base64 + simm8_64] is mod=1 & r_m=4; rexXprefix=0 & index64=4 & Base64; simm8_64 { export Base64; } +bndmk_addr64: [simm32_64 + Base64 + Index64*ss] is mod=2 & r_m=4; Index64 & Base64 & ss; simm32_64 { export Base64; } +bndmk_addr64: [simm32_64 + Base64] is mod=2 & r_m=4; rexXprefix=0 & index64=4 & Base64; simm32_64 { export Base64; } +bndmk_addr64: [Base64 + Index64*ss] is mod=2 & r_m=4; Index64 & Base64 & ss; imm32=0 { export Base64; } +bndmk_addr64: [Base64] is mod=2 & r_m=4; rexXprefix=0 & index64=4 & Base64; imm32=0 { export Base64; } +@endif + +bndmk_addr32: [Rmr32] is mod=0 & Rmr32 { export Rmr32; } +bndmk_addr32: [Rmr32 + simm8_32] is mod=1 & Rmr32; simm8_32 { export Rmr32; } +bndmk_addr32: [Rmr32] is mod=1 & r_m!=4 & Rmr32; simm8=0 { export Rmr32; } +bndmk_addr32: [imm32 + Rmr32] is mod=2 & Rmr32; imm32 { export Rmr32; } +bndmk_addr32: [Rmr32] is mod=2 & r_m!=4 & Rmr32; imm32=0 { export Rmr32; } +bndmk_addr32: [imm32] is mod=0 & r_m=5; imm32 { tmp:4 = 0; export tmp; } +bndmk_addr32: [Base + Index*ss] is mod=0 & r_m=4; Index & Base & ss { export Base; } +bndmk_addr32: [Base] is mod=0 & r_m=4; index=4 & Base { export Base; } +bndmk_addr32: [imm32 + Index*ss] is mod=0 & r_m=4; Index & base=5 & ss; imm32 { tmp:4 = 0; export tmp; } +bndmk_addr32: [imm32] is mod=0 & r_m=4; index=4 & base=5; imm32 { tmp:4 = 0; export tmp; } +bndmk_addr32: [Base + Index*ss + simm8_32] is mod=1 & r_m=4; Index & Base & ss; simm8_32 { export Base; } +bndmk_addr32: [Base + simm8_32] is mod=1 & r_m=4; index=4 & Base; simm8_32 { export Base; } +bndmk_addr32: [Base + Index*ss] is mod=1 & r_m=4; Index & Base & ss; simm8=0 { export Base; } +bndmk_addr32: [Base] is mod=1 & r_m=4; index=4 & Base; simm8=0 { export Base; } +bndmk_addr32: [imm32 + Base + Index*ss] is mod=2 & r_m=4; Index & Base & ss; imm32 { export Base; } +bndmk_addr32: [imm32 + Base] is mod=2 & r_m=4; index=4 & Base; imm32 { export Base; } +bndmk_addr32: [Base + Index*ss] is mod=2 & r_m=4; Index & Base & ss; imm32=0 { export Base; } +bndmk_addr32: [Base] is mod=2 & r_m=4; index=4 & Base; imm32=0 { export Base; } + + + +@ifdef IA64 + +:BNDCL bnd1, Rmr64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x1A; mod=3 & bnd1 & bnd1_lb & Rmr64 { +# if (reg < BND.LB) then BNDSTATUS = 01H; AND BOUND EXCEPTION + if !(Rmr64 < bnd1_lb) goto ; + BNDSTATUS = 0x01; + br_exception(); + +} + +:BNDCL bnd1, Mem is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x1A; (bnd1 & bnd1_lb) ... & Mem { +# if (LEA(mem) < BND.LB) then BNDSTATUS = 01H; AND BOUND EXCEPTION + if !(Mem < bnd1_lb) goto ; + BNDSTATUS = 0x01; + br_exception(); + +} + +:BNDCU bnd1, Rmr64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x1A; mod=3 & bnd1 & bnd1_ub & Rmr64 { +# if (reg > ~(BND.UB)) then BNDSTATUS = 01H; AND BOUND EXCEPTION + if !(Rmr64 > ~bnd1_ub) goto ; + BNDSTATUS = 0x01; + br_exception(); + +} + +:BNDCU bnd1, Mem is $(LONGMODE_ON) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x1A; (bnd1 & bnd1_ub) ... & Mem { +# if (LEA(mem) > ~(BND.UB)) then BNDSTATUS = 01H; AND BOUND EXCEPTION + if !(Mem > ~bnd1_ub) goto ; + BNDSTATUS = 0x01; + br_exception(); + +} + +:BNDCN bnd1, Rmr64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x1B; mod=3 & bnd1 & bnd1_ub & Rmr64 { +# if (reg > BND.UB) then BNDSTATUS = 01H; AND BOUND EXCEPTION + if !(Rmr64 > bnd1_ub) goto ; + BNDSTATUS = 0x01; + br_exception(); + +} + +:BNDCN bnd1, Mem is $(LONGMODE_ON) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x1B; (bnd1 & bnd1_ub) ... & Mem { +# if (LEA(mem) > BND.UB) then BNDSTATUS = 01H; AND BOUND EXCEPTION + if !(Mem > bnd1_ub) goto ; + BNDSTATUS = 0x01; + br_exception(); + +} + +#TODO: This probably cannot be fully modeled +:BNDLDX bnd1, Mem is $(LONGMODE_ON) & vexMode=0 & byte=0x0F; byte=0x1A; bnd1 ... & Mem { +# BNDSTATUS = bndldx_status( Mem, BNDCFGS, BNDCFGU ); +# bnd1 = bndldx( Mem, BNDCFGS, BNDCFGU ); + +# core implementation + bnd1 = *:16 Mem; +} + +:BNDMK bnd1, Mem is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x1B; ( bnd1 & bnd1_lb & bnd1_ub ) ... & ( bndmk_addr64 & Mem ) { +# BND.LB and BND.UB set from m64 + bnd1_lb = bndmk_addr64; + bnd1_ub = Mem; +} + +:BNDMOV bnd1, m128 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x1A; bnd1 ... & m128 { + bnd1 = m128; +} + +:BNDMOV bnd1, bnd2 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x1A; mod=3 & bnd1 & bnd2 { + bnd1 = bnd2; +} + +:BNDMOV m128, bnd1 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x1B; bnd1 ... & m128 { + m128 = bnd1; +} + +:BNDMOV bnd2, bnd1 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x1B; mod=3 & bnd1 & bnd2 { + bnd2 = bnd1; +} + +#TODO: This probably cannot be fully modeled +:BNDSTX Mem, bnd1 is $(LONGMODE_ON) & vexMode=0 & byte=0x0F; byte=0x1B; bnd1 ... & Mem { +# BNDSTATUS = bndstx_status( bnd1, BNDCFGS, BNDCFGU ); +# Mem = bndstx( bnd1, BNDCFGS, BNDCFGU ); + +# core implementation + *:16 Mem = bnd1; +} + +@endif + +:BNDCL bnd1, Rmr32 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x1A; mod=3 & bnd1 & bnd1_lb & Rmr32 { +# if (reg < BND.LB) then BNDSTATUS = 01H; AND BOUND EXCEPTION + if !(zext(Rmr32) < bnd1_lb) goto ; + BNDSTATUS = 0x01; + br_exception(); + +} + +:BNDCL bnd1, Mem is $(LONGMODE_OFF) & vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x1A; (bnd1 & bnd1_lb) ... & Mem { +# if (LEA(mem) < BND.LB) then BNDSTATUS = 01H; AND BOUND EXCEPTION + if !(zext(Mem) < bnd1_lb) goto ; + BNDSTATUS = 0x01; + br_exception(); + +} + +:BNDCU bnd1, Rmr32 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x1A; mod=3 & bnd1 & bnd1_ub & Rmr32 { +# if (reg > ~(BND.UB)) then BNDSTATUS = 01H; AND BOUND EXCEPTION + if !(zext(Rmr32) > ~bnd1_ub) goto ; + BNDSTATUS = 0x01; + br_exception(); + +} + +:BNDCU bnd1, Mem is $(LONGMODE_OFF) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x1A; (bnd1 & bnd1_ub) ... & Mem { +# if (LEA(mem) > ~(BND.UB)) then BNDSTATUS = 01H; AND BOUND EXCEPTION + if !(zext(Mem) > ~bnd1_ub) goto ; + BNDSTATUS = 0x01; + br_exception(); + +} + +:BNDCN bnd1, Rmr32 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x1B; mod=3 & bnd1 & bnd1_ub & Rmr32 { +# if (reg > BND.UB) then BNDSTATUS = 01H; AND BOUND EXCEPTION + if !(zext(Rmr32) > bnd1_ub) goto ; + BNDSTATUS = 0x01; + br_exception(); + +} + +:BNDCN bnd1, Mem is $(LONGMODE_OFF) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x1B; (bnd1 & bnd1_ub) ... & Mem { +# if (LEA(mem) > BND.UB) then BNDSTATUS = 01H; AND BOUND EXCEPTION + if !(zext(Mem) > bnd1_ub) goto ; + BNDSTATUS = 0x01; + br_exception(); + +} + +#TODO: This probably cannot be fully modeled +:BNDLDX bnd1, Mem is $(LONGMODE_OFF) & vexMode=0 & byte=0x0F; byte=0x1A; ( bnd1 & bnd1_lb & bnd1_ub ) ... & Mem { +# BNDSTATUS = bndldx_status( Mem, BNDCFGS, BNDCFGU ); +# bnd1 = bndldx( Mem, BNDCFGS, BNDCFGU ); + +# core implementation + tmp:8 = *:8 Mem; + bnd1_lb = zext(tmp:4); + tmp2:4 = tmp(4); + bnd1_ub = zext(tmp2); +} + +:BNDMK bnd1, Mem is $(LONGMODE_OFF) & vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x1B; ( bnd1 & bnd1_lb & bnd1_ub ) ... & ( bndmk_addr32 & Mem ) { +# BND.LB and BND.UB set from m32 + bnd1_lb = zext(bndmk_addr32); + bnd1_ub = zext(Mem); +} + +:BNDMOV bnd1, m64 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x1A; ( bnd1 & bnd1_lb & bnd1_ub ) ... & m64 { + tmp:8 = m64; + bnd1_lb = zext(tmp:4); + tmp2:4 = tmp(4); + bnd1_ub = zext(tmp2); +} + +:BNDMOV bnd1, bnd2 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x1A; mod=3 & bnd1 & bnd2 { + bnd1 = bnd2; +} + +:BNDMOV m64, bnd1 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x1B; ( bnd1 & bnd1_lb & bnd1_ub ) ... & m64 { + m64 = (zext(bnd1_ub:4) << 32) | zext(bnd1_lb:4); +} + +:BNDMOV bnd2, bnd1 is $(LONGMODE_OFF) & vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x1B; mod=3 & bnd1 & bnd2 { + bnd2 = bnd1; +} + +#TODO: This probably cannot be fully modeled +:BNDSTX Mem, bnd1 is $(LONGMODE_OFF) & vexMode=0 & byte=0x0F; byte=0x1B; ( bnd1 & bnd1_lb & bnd1_ub ) ... & Mem { +# BNDSTATUS = bndstx_status( bnd1, BNDCFGS, BNDCFGU ); +# Mem = bndstx( bnd1, BNDCFGS, BNDCFGU ); + +# core implementation + *:8 Mem = (zext(bnd1_ub:4) << 32) | zext(bnd1_lb:4); +} + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/old/x86RealV1.lang b/python/icicle/Ghidra/Processors/x86/data/languages/old/x86RealV1.lang new file mode 100644 index 0000000..5325237 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/old/x86RealV1.lang @@ -0,0 +1,150 @@ + + + + x86:LE:16:Real Mode + x86 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/old/x86RealV1.trans b/python/icicle/Ghidra/Processors/x86/data/languages/old/x86RealV1.trans new file mode 100644 index 0000000..5bd8a77 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/old/x86RealV1.trans @@ -0,0 +1,7 @@ + + + x86:LE:16:Real Mode + x86:LE:16:Real Mode + + + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/old/x86V1.lang b/python/icicle/Ghidra/Processors/x86/data/languages/old/x86V1.lang new file mode 100644 index 0000000..ae7d23a --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/old/x86V1.lang @@ -0,0 +1,151 @@ + + + + x86:LE:32:default + x86 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/old/x86V1.trans b/python/icicle/Ghidra/Processors/x86/data/languages/old/x86V1.trans new file mode 100644 index 0000000..bc1ef4c --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/old/x86V1.trans @@ -0,0 +1,8 @@ + + + x86:LE:32:default + x86:LE:32:default + + + + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/old/x86_64bit_v1.lang b/python/icicle/Ghidra/Processors/x86/data/languages/old/x86_64bit_v1.lang new file mode 100644 index 0000000..0404f96 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/old/x86_64bit_v1.lang @@ -0,0 +1,221 @@ + + + + x64:LE:64:default + x64 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/old/x86_64bit_v1.trans b/python/icicle/Ghidra/Processors/x86/data/languages/old/x86_64bit_v1.trans new file mode 100644 index 0000000..f50f8aa --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/old/x86_64bit_v1.trans @@ -0,0 +1,8 @@ + + + x64:LE:64:default + x86:LE:64:default + + + + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/old/x86smmV1.lang b/python/icicle/Ghidra/Processors/x86/data/languages/old/x86smmV1.lang new file mode 100644 index 0000000..ac64bb6 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/old/x86smmV1.lang @@ -0,0 +1,150 @@ + + + + x86:LE:32:System Management Mode + x86 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/old/x86smmV1.trans b/python/icicle/Ghidra/Processors/x86/data/languages/old/x86smmV1.trans new file mode 100644 index 0000000..42e664d --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/old/x86smmV1.trans @@ -0,0 +1,7 @@ + + + x86:LE:32:System Management Mode + x86:LE:32:System Management Mode + + + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/pclmulqdq.sinc b/python/icicle/Ghidra/Processors/x86/data/languages/pclmulqdq.sinc new file mode 100644 index 0000000..a1005ef --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/pclmulqdq.sinc @@ -0,0 +1,173 @@ +# Due to limitations on variable length matching that preclude opcode matching afterwards, all memory addressing forms of PCLMULQDQ are decoded to PCLMULQDQ, not the macro names. +# Display is non-standard, but semantics, and de-compilation should be correct. + +macro pclmul(src1, src2, dest) { + local i:4 = 0:4; + local temp:16 = 0; + + + if (i > 63:4) goto ; + if ((src1 & (1 << i)) == 0) goto ; + temp = temp ^ (src2 << i); + + i = i+1; + goto ; + + dest = temp; +} + +:PCLMULLQLQDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x3a; byte=0x44; xmmmod=3 & XmmReg1 & XmmReg2; byte=0x00 +{ + local src1:16 = zext(XmmReg1[0,64]); + local src2:16 = zext(XmmReg2[0,64]); + pclmul(src1,src2,XmmReg1); +} + +:PCLMULHQLQDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x3a; byte=0x44; xmmmod=3 & XmmReg1 & XmmReg2; byte=0x01 +{ + local src1:16 = zext(XmmReg1[64,64]); + local src2:16 = zext(XmmReg2[0,64]); + pclmul(src1,src2,XmmReg1); +} + +:PCLMULLQHQDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x3a; byte=0x44; xmmmod=3 & XmmReg1 & XmmReg2; byte=0x10 +{ + local src1:16 = zext(XmmReg1[0,64]); + local src2:16 = zext(XmmReg2[64,64]); + pclmul(src1,src2,XmmReg1); +} + +:PCLMULHQHQDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x3a; byte=0x44; xmmmod=3 & XmmReg1 & XmmReg2; byte=0x11 +{ + local src1:16 = zext(XmmReg1[64,64]); + local src2:16 = zext(XmmReg2[64,64]); + pclmul(src1,src2,XmmReg1); +} + +:PCLMULQDQ XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x3a; byte=0x44; xmmmod=3 & XmmReg1 & XmmReg2; imm8 & imm8_4 & imm8_0 +{ + if (imm8_0:1) goto ; + src1:16 = zext(XmmReg1[0,64]); + goto ; + + + src1 = zext(XmmReg1[64,64]); + + + + if (imm8_4:1) goto ; + src2:16 = zext(XmmReg2[0,64]); + goto ; + + + src2 = zext(XmmReg2[64,64]); + + + + pclmul(src1,src2,XmmReg1); +} + +:PCLMULQDQ XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x3a; byte=0x44; XmmReg ... & m128; imm8 & imm8_4 & imm8_0 +{ + if (imm8_0:1) goto ; + src1:16 = zext(XmmReg[0,64]); + goto ; + + + src1 = zext(XmmReg[64,64]); + + + local m:16 = m128; + if (imm8_4:1) goto ; + src2:16 = zext(m[0,64]); + goto ; + + + src2 = zext(m[64,64]); + + + + pclmul(src1,src2,XmmReg); +} + +:VPCLMULLQLQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x44; xmmmod=3 & (XmmReg1 & YmmReg1) & XmmReg2; byte=0x00 +{ + local src1:16 = zext(vexVVVV_XmmReg[0,64]); + local src2:16 = zext(XmmReg2[0,64]); + pclmul(src1,src2,XmmReg1); + YmmReg1 = zext(XmmReg1); +} + +:VPCLMULHQLQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x44; xmmmod=3 & (XmmReg1 & YmmReg1) & XmmReg2; byte=0x01 +{ + local src1:16 = zext(vexVVVV_XmmReg[64,64]); + local src2:16 = zext(XmmReg2[0,64]); + pclmul(src1,src2,XmmReg1); + YmmReg1 = zext(XmmReg1); +} + +:VPCLMULLQHQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x44; xmmmod=3 & (XmmReg1 & YmmReg1) & XmmReg2; byte=0x10 +{ + local src1:16 = zext(vexVVVV_XmmReg[0,64]); + local src2:16 = zext(XmmReg2[64,64]); + pclmul(src1,src2,XmmReg1); + YmmReg1 = zext(XmmReg1); +} + +:VPCLMULHQHQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x44; xmmmod=3 & (XmmReg1 & YmmReg1) & XmmReg2; byte=0x11 +{ + local src1:16 = zext(vexVVVV_XmmReg[64,64]); + local src2:16 = zext(XmmReg2[64,64]); + pclmul(src1,src2,XmmReg1); + YmmReg1 = zext(XmmReg1); +} + +:VPCLMULQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x44; xmmmod=3 & (XmmReg1 & YmmReg1) & XmmReg2; imm8 & imm8_4 & imm8_0 +{ + if (imm8_0:1) goto ; + src1:16 = zext(vexVVVV_XmmReg[0,64]); + goto ; + + + src1 = zext(vexVVVV_XmmReg[64,64]); + + + + if (imm8_4:1) goto ; + src2:16 = zext(XmmReg2[0,64]); + goto ; + + + src2 = zext(XmmReg2[64,64]); + + + + pclmul(src1,src2,XmmReg1); + YmmReg1 = zext(XmmReg1); +} + +:VPCLMULQDQ XmmReg1, vexVVVV_XmmReg, m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x44; (XmmReg1 & YmmReg1) ... & m128; imm8 & imm8_4 & imm8_0 +{ + if (imm8_0:1) goto ; + src1:16 = zext(vexVVVV_XmmReg[0,64]); + goto ; + + + src1 = zext(vexVVVV_XmmReg[64,64]); + + + + local m:16 = m128; + if (imm8_4:1) goto ; + src2:16 = zext(m[0,64]); + goto ; + + + src2 = zext(m[64,64]); + + + + pclmul(src1,src2,XmmReg1); + YmmReg1 = zext(XmmReg1); +} + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/rdrand.sinc b/python/icicle/Ghidra/Processors/x86/data/languages/rdrand.sinc new file mode 100644 index 0000000..4037bb9 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/rdrand.sinc @@ -0,0 +1,51 @@ +define pcodeop rdrand; +define pcodeop rdrandIsValid; + +macro rdflags(){ + OF = 0; SF = 0; ZF = 0; AF = 0; PF = 0; +} + +:RDRAND Rmr16 is vexMode=0 & opsize=0 & byte=0x0f; byte=0xC7; mod=3 & Rmr16 & reg_opcode=6 +{ + Rmr16 = rdrand(); + CF=rdrandIsValid(); + rdflags(); + +} +:RDRAND Rmr32 is vexMode=0 & opsize=1 & byte=0x0f; byte=0xC7; mod=3 & Rmr32 & reg_opcode=6 +{ + Rmr32 = rdrand(); + CF=rdrandIsValid(); + rdflags(); +} +@ifdef IA64 +:RDRAND Rmr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(REX_W) & byte=0x0f; byte=0xC7; mod=3 & Rmr64 & reg_opcode=6 +{ + Rmr64 = rdrand(); + CF=rdrandIsValid(); + rdflags(); +} +@endif + +define pcodeop rdseed; +define pcodeop rdseedIsValid; +:RDSEED Rmr16 is vexMode=0 & opsize=0 & byte=0x0f; byte=0xC7; mod=3 & Rmr16 & reg_opcode=7 +{ + Rmr16 = rdseed(); + CF=rdseedIsValid(); + rdflags(); +} +:RDSEED Rmr32 is vexMode=0 & opsize=1 & byte=0x0f; byte=0xC7; mod=3 & Rmr32 & reg_opcode=7 +{ + Rmr32 = rdseed(); + CF=rdseedIsValid(); + rdflags(); +} +@ifdef IA64 +:RDSEED Rmr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(REX_W) & byte=0x0f; byte=0xC7; mod=3 & Rmr64 & reg_opcode=7 +{ + Rmr64 = rdseed(); + CF=rdseedIsValid(); + rdflags(); +} +@endif diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/sgx.sinc b/python/icicle/Ghidra/Processors/x86/data/languages/sgx.sinc new file mode 100644 index 0000000..9c124e1 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/sgx.sinc @@ -0,0 +1,257 @@ +define pcodeop encls_ecreate; +define pcodeop encls_eadd; +define pcodeop encls_einit; +define pcodeop encls_einit_ZF; +define pcodeop encls_eremove; +define pcodeop encls_eremove_ZF; +define pcodeop encls_edbgrd; +define pcodeop encls_edbgrd_RBX; +define pcodeop encls_edbgwr; +define pcodeop encls_eextend; +define pcodeop encls_eldb; +define pcodeop encls_eldb_ZF; +define pcodeop encls_eldu; +define pcodeop encls_eldu_ZF; +define pcodeop encls_eblock; +define pcodeop encls_eblock_ZF; +define pcodeop encls_epa; +define pcodeop encls_ewb; +define pcodeop encls_ewb_ZF; +define pcodeop encls_ewb_CF; +define pcodeop encls_etrack; +define pcodeop encls_etrack_ZF; +define pcodeop encls_eaug; +define pcodeop encls_emodpr; +define pcodeop encls_emodpr_ZF; +define pcodeop encls_emodt; +define pcodeop encls_emodt_ZF; +define pcodeop encls_unknown; + +:ENCLS is vexMode=0 & byte=0x0f; byte=0x01; byte=0xcf { + + if ( EAX != 0x0 ) goto ; + encls_ecreate( RBX, RCX ); + goto ; + + + if ( EAX != 0x1 ) goto ; + encls_eadd( RBX, RCX ); + goto ; + + + if ( EAX != 0x2 ) goto ; + RAX = encls_einit( RBX, RCX, RDX ); + ZF = encls_einit_ZF( RBX, RCX, RDX ); + CF = 0; + PF = 0; + AF = 0; + OF = 0; + SF = 0; + goto ; + + + if ( EAX != 0x3 ) goto ; + RAX = encls_eremove( RCX ); + ZF = encls_eremove_ZF( RBX, RCX, RDX ); + CF = 0; + PF = 0; + AF = 0; + OF = 0; + SF = 0; + goto ; + + + if ( EAX != 0x4 ) goto ; + RAX = encls_edbgrd( RCX ); + RBX = encls_edbgrd_RBX( RCX ); + goto ; + + + if ( EAX != 0x5 ) goto ; + RAX = encls_edbgwr( RBX, RCX ); + goto ; + + + if ( EAX != 0x6 ) goto ; + encls_eextend( RBX, RCX ); + goto ; + + + if ( EAX != 0x7 ) goto ; + RAX = encls_eldb( RBX, RCX, RDX ); + ZF = encls_eldb_ZF( RBX, RCX, RDX ); + CF = 0; + PF = 0; + AF = 0; + OF = 0; + SF = 0; + goto ; + + + if ( EAX != 0x8 ) goto ; + RAX = encls_eldu( RBX, RCX, RDX ); + ZF = encls_eldu_ZF( RBX, RCX, RDX ); + CF = 0; + PF = 0; + AF = 0; + OF = 0; + SF = 0; + goto ; + + + if ( EAX != 0x9 ) goto ; + RAX = encls_eblock( RCX ); + ZF = encls_eblock_ZF( RCX ); + PF = 0; + AF = 0; + OF = 0; + SF = 0; + goto ; + + + if ( EAX != 0xA ) goto ; + encls_epa( RBX, RCX ); + goto ; + + + if ( EAX != 0xB ) goto ; + RAX = encls_ewb( RBX, RCX, RDX ); + ZF = encls_ewb_ZF( RBX, RCX, RDX ); + CF = encls_ewb_CF( RBX, RCX, RDX ); + PF = 0; + AF = 0; + OF = 0; + SF = 0; + goto ; + + + if ( EAX != 0xC ) goto ; + RAX = encls_etrack( RCX ); + ZF = encls_etrack_ZF( RBX, RCX, RDX ); + CF = 0; + PF = 0; + AF = 0; + OF = 0; + SF = 0; + goto ; + + + if ( EAX != 0xD ) goto ; + encls_eaug( RBX, RCX, RDX ); + goto ; + + + if ( EAX != 0xE ) goto ; + RAX = encls_emodpr( RBX, RCX ); + ZF = encls_emodpr_ZF( RCX ); + CF = 0; + PF = 0; + AF = 0; + OF = 0; + SF = 0; + goto ; + + + if ( EAX != 0xF ) goto ; + RAX = encls_emodt( RBX, RCX ); + ZF = encls_emodt_ZF( RCX ); + CF = 0; + PF = 0; + AF = 0; + OF = 0; + SF = 0; + goto ; + + + encls_unknown(); + + +} + + +define pcodeop enclu_ereport; +define pcodeop enclu_egetkey; +define pcodeop enclu_egetkey_ZF; +define pcodeop enclu_eenter_EAX; +define pcodeop enclu_eenter_RCX; +define pcodeop enclu_eenter_TF; +define pcodeop enclu_eresume; +define pcodeop enclu_eexit; +define pcodeop enclu_eexit_TF; +define pcodeop enclu_eaccept; +define pcodeop enclu_eaccept_ZF; +define pcodeop enclu_emodpe; +define pcodeop enclu_eacceptcopy; +define pcodeop enclu_eacceptcopy_ZF; +define pcodeop enclu_unknown; + +:ENCLU is vexMode=0 & byte=0x0f; byte=0x01; byte=0xd7 { + + if ( EAX != 0x0 ) goto ; + enclu_ereport( RBX, RCX, RDX ); + goto ; + + + if ( EAX != 0x1 ) goto ; + RAX = enclu_egetkey( RBX, RCX ); + ZF = enclu_egetkey_ZF( RBX, RCX ); + CF = 0; + PF = 0; + AF = 0; + OF = 0; + SF = 0; + goto ; + + + if ( EAX != 0x2 ) goto ; + tempBX:8 = RBX; + tempCX:8 = RCX; + + EAX = enclu_eenter_EAX( tempBX, tempCX ); + RCX = enclu_eenter_RCX( tempBX, tempCX ); + TF = enclu_eenter_TF( tempBX, tempCX ); + goto ; + + + if ( EAX != 0x3 ) goto ; + TF = enclu_eresume( RBX, RCX ); + goto ; + + + if ( EAX != 0x4 ) goto ; + RCX = enclu_eexit( RBX ); + TF = enclu_eexit_TF( RBX ); + goto ; + + + if ( EAX != 0x5 ) goto ; + RAX = enclu_eaccept( RBX, RCX ); + ZF = enclu_eaccept_ZF( RBX, RCX ); + CF = 0; + PF = 0; + AF = 0; + OF = 0; + SF = 0; + goto ; + + + if ( EAX != 0x6 ) goto ; + enclu_emodpe( RBX, RCX ); + goto ; + + + if ( EAX != 0x7 ) goto ; + RAX = enclu_eacceptcopy( RBX, RCX, RDX ); + ZF = enclu_eacceptcopy_ZF( RBX, RCX, RDX ); + CF = 0; + PF = 0; + AF = 0; + OF = 0; + SF = 0; + goto ; + + + enclu_unknown(); + + +} diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/sha.sinc b/python/icicle/Ghidra/Processors/x86/data/languages/sha.sinc new file mode 100644 index 0000000..9191417 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/sha.sinc @@ -0,0 +1,53 @@ +# INFO This file automatically generated by andre on Fri Mar 16 15:13:25 2018 +# INFO Direct edits to this file may be lost in future updates +# INFO Command line arguments: ['--sinc', '--cpuid-match', 'SHA'] + +# SHA1RNDS4 4-602 PAGE 1722 LINE 89511 +define pcodeop sha1rnds4_sha ; +:SHA1RNDS4 XmmReg1, XmmReg2_m128, imm8 is vexMode=0 & byte=0x0F; byte=0x3A; byte=0xCC; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; imm8 +{ + XmmReg1 = sha1rnds4_sha( XmmReg1, XmmReg2_m128, imm8:1 ); +} + +# SHA1NEXTE 4-604 PAGE 1724 LINE 89602 +define pcodeop sha1nexte_sha ; +:SHA1NEXTE XmmReg1, XmmReg2_m128 is vexMode=0 & byte=0x0F; byte=0x38; byte=0xC8; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + XmmReg1 = sha1nexte_sha( XmmReg1, XmmReg2_m128 ); +} + +# SHA1MSG1 4-605 PAGE 1725 LINE 89654 +define pcodeop sha1msg1_sha ; +:SHA1MSG1 XmmReg1, XmmReg2_m128 is vexMode=0 & byte=0x0F; byte=0x38; byte=0xC9; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + XmmReg1 = sha1msg1_sha( XmmReg1, XmmReg2_m128 ); +} + +# SHA1MSG2 4-606 PAGE 1726 LINE 89708 +define pcodeop sha1msg2_sha ; +:SHA1MSG2 XmmReg1, XmmReg2_m128 is vexMode=0 & byte=0x0F; byte=0x38; byte=0xCA; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + XmmReg1 = sha1msg2_sha( XmmReg1, XmmReg2_m128 ); +} + +# SHA256RNDS2 4-607 PAGE 1727 LINE 89765 +define pcodeop sha256rnds2_sha ; +:SHA256RNDS2 XmmReg1, XmmReg2_m128, XMM0 is vexMode=0 & byte=0x0F; byte=0x38; byte=0xCB; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 & XMM0 +{ + XmmReg1 = sha256rnds2_sha( XmmReg1, XmmReg2_m128, XMM0 ); +} + +# SHA256MSG1 4-609 PAGE 1729 LINE 89847 +define pcodeop sha256msg1_sha ; +:SHA256MSG1 XmmReg1, XmmReg2_m128 is vexMode=0 & byte=0x0F; byte=0x38; byte=0xCC; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + XmmReg1 = sha256msg1_sha( XmmReg1, XmmReg2_m128 ); +} + +# SHA256MSG2 4-610 PAGE 1730 LINE 89900 +define pcodeop sha256msg2_sha ; +:SHA256MSG2 XmmReg1, XmmReg2_m128 is vexMode=0 & byte=0x0F; byte=0x38; byte=0xCD; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 +{ + XmmReg1 = sha256msg2_sha( XmmReg1, XmmReg2_m128 ); +} + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/smx.sinc b/python/icicle/Ghidra/Processors/x86/data/languages/smx.sinc new file mode 100644 index 0000000..67f1c1e --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/smx.sinc @@ -0,0 +1,67 @@ +define pcodeop getsec_capabilities; +define pcodeop getsec_enteraccs; +define pcodeop getsec_exitac; +define pcodeop getsec_senter; +define pcodeop getsec_sexit; +define pcodeop getsec_parameters_EAX; +define pcodeop getsec_parameters_EBX; +define pcodeop getsec_parameters_ECX; +define pcodeop getsec_smctrl; +define pcodeop getsec_wakeup; +define pcodeop getsec_unknown; + + +:GETSEC is vexMode=0 & byte=0x0f; byte=0x37 { + + if ( EAX != 0x0 ) goto ; + EAX = 0; + if ( EBX != 0x0 ) goto ; + EAX = getsec_capabilities( EBX ); + goto ; + + + if ( EAX != 0x2 ) goto ; + getsec_enteraccs( EBX, ECX ); + goto ; + + + if ( EAX != 0x3 ) goto ; +@ifdef IA64 + getsec_exitac( RBX, EDX ); +@else + getsec_exitac( EBX, EDX ); +@endif + goto ; + + + if ( EAX != 0x4 ) goto ; + getsec_senter( EBX, ECX, EDX); + goto ; + + + if ( EAX != 0x5 ) goto ; + getsec_sexit(); + goto ; + + + if ( EAX != 0x6 ) goto ; + EAX = getsec_parameters_EAX( EBX ); + ECX = getsec_parameters_ECX( EBX ); + EBX = getsec_parameters_EBX( EBX ); + goto ; + + + if ( EAX != 0x7 ) goto ; + getsec_smctrl(EBX); + goto ; + + + if ( EAX != 0x8 ) goto ; + getsec_wakeup(); + goto ; + + + getsec_unknown(); + + +} diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/x86-16-real.pspec b/python/icicle/Ghidra/Processors/x86/data/languages/x86-16-real.pspec new file mode 100644 index 0000000..ba7ff91 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/x86-16-real.pspec @@ -0,0 +1,33 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/x86-16.cspec b/python/icicle/Ghidra/Processors/x86/data/languages/x86-16.cspec new file mode 100644 index 0000000..f07cea0 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/x86-16.cspec @@ -0,0 +1,174 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/x86-16.gdis b/python/icicle/Ghidra/Processors/x86/data/languages/x86-16.gdis new file mode 100644 index 0000000..2efbfd6 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/x86-16.gdis @@ -0,0 +1,3 @@ + + + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/x86-16.pspec b/python/icicle/Ghidra/Processors/x86/data/languages/x86-16.pspec new file mode 100644 index 0000000..ae2d69c --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/x86-16.pspec @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/x86-64-gcc.cspec b/python/icicle/Ghidra/Processors/x86/data/languages/x86-64-gcc.cspec new file mode 100644 index 0000000..7b7ca23 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/x86-64-gcc.cspec @@ -0,0 +1,242 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/x86-64-win.cspec b/python/icicle/Ghidra/Processors/x86/data/languages/x86-64-win.cspec new file mode 100644 index 0000000..907f981 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/x86-64-win.cspec @@ -0,0 +1,224 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/x86-64.dwarf b/python/icicle/Ghidra/Processors/x86/data/languages/x86-64.dwarf new file mode 100644 index 0000000..c821818 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/x86-64.dwarf @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/x86-64.pspec b/python/icicle/Ghidra/Processors/x86/data/languages/x86-64.pspec new file mode 100644 index 0000000..315344d --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/x86-64.pspec @@ -0,0 +1,160 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/x86-64.slaspec b/python/icicle/Ghidra/Processors/x86/data/languages/x86-64.slaspec new file mode 100644 index 0000000..8b442ec --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/x86-64.slaspec @@ -0,0 +1,6 @@ +@define IA64 "IA64" +@include "x86.slaspec" +with : lockprefx=0 { +@include "sgx.sinc" +@include "fma.sinc" +} diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/x86.dwarf b/python/icicle/Ghidra/Processors/x86/data/languages/x86.dwarf new file mode 100644 index 0000000..154617e --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/x86.dwarf @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/x86.ldefs b/python/icicle/Ghidra/Processors/x86/data/languages/x86.ldefs new file mode 100644 index 0000000..482ef9e --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/x86.ldefs @@ -0,0 +1,98 @@ + + + + + Intel/AMD 32-bit x86 + + + + + + + + + + + + + + + + + + + + Intel/AMD 32-bit x86 System Management Mode + + + + + Intel/AMD 16-bit x86 Real Mode + + + + + + + + + + + + Intel/AMD 16-bit x86 Protected Mode + + + + + + + Intel/AMD 64-bit x86 + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/x86.opinion b/python/icicle/Ghidra/Processors/x86/data/languages/x86.opinion new file mode 100644 index 0000000..ef5283f --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/x86.opinion @@ -0,0 +1,81 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/x86.pspec b/python/icicle/Ghidra/Processors/x86/data/languages/x86.pspec new file mode 100644 index 0000000..595d1e2 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/x86.pspec @@ -0,0 +1,121 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/x86.slaspec b/python/icicle/Ghidra/Processors/x86/data/languages/x86.slaspec new file mode 100644 index 0000000..4c1962c --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/x86.slaspec @@ -0,0 +1,19 @@ +@include "ia.sinc" +@include "lockable.sinc" +with : lockprefx=0 { +@include "avx.sinc" +@include "avx_manual.sinc" +@include "avx2.sinc" +@include "avx2_manual.sinc" +@include "adx.sinc" +@include "clwb.sinc" +@include "pclmulqdq.sinc" +@include "mpx.sinc" +@include "lzcnt.sinc" +@include "bmi1.sinc" +@include "bmi2.sinc" +@include "sha.sinc" +@include "smx.sinc" +@include "cet.sinc" +@include "rdrand.sinc" +} diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/x86borland.cspec b/python/icicle/Ghidra/Processors/x86/data/languages/x86borland.cspec new file mode 100644 index 0000000..c17bca6 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/x86borland.cspec @@ -0,0 +1,150 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/x86delphi.cspec b/python/icicle/Ghidra/Processors/x86/data/languages/x86delphi.cspec new file mode 100644 index 0000000..8f04248 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/x86delphi.cspec @@ -0,0 +1,99 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/x86gcc.cspec b/python/icicle/Ghidra/Processors/x86/data/languages/x86gcc.cspec new file mode 100644 index 0000000..bcd049d --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/x86gcc.cspec @@ -0,0 +1,377 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/Ghidra/Processors/x86/data/languages/x86win.cspec b/python/icicle/Ghidra/Processors/x86/data/languages/x86win.cspec new file mode 100644 index 0000000..c07b7e4 --- /dev/null +++ b/python/icicle/Ghidra/Processors/x86/data/languages/x86win.cspec @@ -0,0 +1,380 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/python/icicle/__init__.py b/python/icicle/__init__.py new file mode 100644 index 0000000..8e7dbe1 --- /dev/null +++ b/python/icicle/__init__.py @@ -0,0 +1,20 @@ +from .icicle import * + +class MemoryError(Exception): + def __init__(self, message, code): + super().__init__(message) + self.code = code + def __str__(self): + return f"{super().__str__()}: {self.code}" + +def __ghidra_init(): + import os + for path in __path__ + [os.getenv("GHIDRA_SRC", ".")]: + processors_dir = os.path.join(path, "Ghidra/Processors") + if os.path.isdir(processors_dir): + os.putenv("GHIDRA_SRC", path) + os.environ["GHIDRA_SRC"] = path + return + raise FileNotFoundError("Ghidra processor definitions not found") + +__ghidra_init() diff --git a/icicle.pyi b/python/icicle/icicle.pyi similarity index 100% rename from icicle.pyi rename to python/icicle/icicle.pyi diff --git a/python/icicle/py.typed b/python/icicle/py.typed new file mode 100644 index 0000000..e69de29 diff --git a/requirements.txt b/requirements.txt index 7e470f8..62d52f0 100644 --- a/requirements.txt +++ b/requirements.txt @@ -1 +1,3 @@ -maturin==1.2.0 \ No newline at end of file +setuptools +wheel +setuptools-rust \ No newline at end of file diff --git a/setup.cfg b/setup.cfg new file mode 100644 index 0000000..a9f0dca --- /dev/null +++ b/setup.cfg @@ -0,0 +1,28 @@ +[metadata] +name = icicle-emu +version = v1.0.0 +url = https://github.com/mrexodia/icicle-python +project_urls = + Bug Tracker = https://github.com/mrexodia/icicle-python/issues +long_description = file: README.md +long_description_content_type = text/markdown +classifiers = + License :: OSI Approved :: Boost Software License 1.0 (BSL-1.0) + Intended Audience :: Developers + Programming Language :: Python :: 3 + Programming Language :: Python :: 3.7 + Programming Language :: Python :: 3.8 + Programming Language :: Python :: 3.9 + Programming Language :: Python :: 3.10 + Programming Language :: Python :: 3.11 + Development Status :: 5 - Production/Stable + Operating System :: POSIX + Operating System :: MacOS :: MacOS X + Operating System :: Microsoft :: Windows + +[options] +packages = icicle +zip_safe = False +setup_requires = setuptools-rust >= 0.12.1; +python_requires = >=3.7 +include_package_data = True \ No newline at end of file diff --git a/setup.py b/setup.py new file mode 100644 index 0000000..b359b9b --- /dev/null +++ b/setup.py @@ -0,0 +1,32 @@ +#!/usr/bin/env python + +from os import getenv +from shutil import which +from setuptools import find_packages, setup +from setuptools_rust import RustExtension + +if __name__ == "__main__": + if which("cargo") is None: + raise FileNotFoundError(f"Rust not found, visit https://rustup.rs for installation instructions") + + ref_name = getenv("GITHUB_REF_NAME") + if ref_name: + from pkg_resources import parse_version + try: + parse_version(ref_name) + print(f"injecting version = {ref_name} into setup.cfg") + with open("setup.cfg", "r") as f: + lines = f.readlines() + with open("setup.cfg", "w") as f: + for line in lines: + if line.startswith("version = "): + line = f"version = {ref_name}\n" + f.write(line) + except Exception: + pass + + setup( + packages=find_packages(where="python", exclude=["icicle/__pycache__"]), + package_dir={"": "python"}, + rust_extensions=[RustExtension("icicle.icicle")], + ) diff --git a/src/lib.rs b/src/lib.rs index 1d35b65..00e662b 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -501,32 +501,12 @@ fn architectures() -> PyResult> { /// the `lib.name` setting in the `Cargo.toml`, else Python will not be able to /// import the module. #[pymodule] -fn icicle(py: Python<'_>, m: &PyModule) -> PyResult<()> { +fn icicle(_: Python<'_>, m: &PyModule) -> PyResult<()> { m.add_function(wrap_pyfunction!(architectures, m)?)?; m.add_class::()?; m.add_class::()?; m.add_class::()?; m.add_class::()?; m.add_class::()?; - PyModule::from_code(py, r#" -class MemoryError(Exception): - def __init__(self, message, code): - super().__init__(message) - self.code = code - def __str__(self): - return f"{super().__str__()}: {self.code}" - -def __ghidra_init(): - import os - for path in __path__ + [os.getenv("GHIDRA_SRC")]: - processors_dir = os.path.join(path, "Ghidra/Processors") - if os.path.isdir(processors_dir): - os.putenv("GHIDRA_SRC", path) - os.environ["GHIDRA_SRC"] = path - return - raise FileNotFoundError("Ghidra processors not found") - -__ghidra_init() -"#, "icicle_exceptions.py", "icicle")?; Ok(()) } \ No newline at end of file diff --git a/tests/example.py b/tests/example.py index ee526a0..4b79134 100644 --- a/tests/example.py +++ b/tests/example.py @@ -49,6 +49,7 @@ def old_test(): try: vm.mem_protect(addr, 0x2000, icicle.MemoryProtection.ExecuteRead) except icicle.MemoryError as x: + print("MemoryError working!") message = x.args[0] print(message, x.code) except Exception as x: @@ -61,6 +62,8 @@ def old_test(): print(vm) def main(): + old_test() + vm = icicle.Icicle("x86_64", jit=False) print(vm)