mirror of
https://github.com/intel/linux-sgx
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Li, Xun
c505e6129a
Added support for Reproducible Enclave Build using Docker file. Added support for Intel AVX-512 instructions and Intel SHA Extensions New Instructions (SHA-NI) in trusted libraries. Support both EPID and ECDSA based quote for quoting related interfaces in sgx_uae_service library. Updated key exchange library to support both EPID and ECDSA based remote attestation. Support new interface to check platform information blob from remote attestation response message. Fixed bugs. Signed-off-by: Li, Xun <xun.li@intel.com>
86 lines
3.3 KiB
C
86 lines
3.3 KiB
C
/* libunwind - a platform-independent unwind library
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Copyright (C) 2001-2002 Hewlett-Packard Co
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Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
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This file is part of libunwind.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
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#define IA64_LOG_UNW_CACHE_SIZE 7
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#define IA64_UNW_CACHE_SIZE (1 << IA64_LOG_UNW_CACHE_SIZE)
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#define IA64_LOG_UNW_HASH_SIZE (IA64_LOG_UNW_CACHE_SIZE + 1)
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#define IA64_UNW_HASH_SIZE (1 << IA64_LOG_UNW_HASH_SIZE)
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typedef unsigned char unw_hash_index_t;
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struct ia64_script_insn
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{
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unsigned int opc; /* see enum ia64_script_insn_opcode */
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unsigned int dst;
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unw_word_t val;
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};
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/* Updating each preserved register may result in one script
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instruction each. At the end of the script, psp gets popped,
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accounting for one more instruction. */
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#define IA64_MAX_SCRIPT_LEN (IA64_NUM_PREGS + 1)
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struct ia64_script
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{
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unw_word_t ip; /* ip this script is for */
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unw_word_t pr_mask; /* mask of predicates script depends on */
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unw_word_t pr_val; /* predicate values this script is for */
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unw_proc_info_t pi; /* info about underlying procedure */
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unsigned short lru_chain; /* used for least-recently-used chain */
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unsigned short coll_chain; /* used for hash collisions */
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unsigned short hint; /* hint for next script to try (or -1) */
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unsigned short count; /* number of instructions in script */
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unsigned short abi_marker;
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struct ia64_script_insn insn[IA64_MAX_SCRIPT_LEN];
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};
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struct ia64_script_cache
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{
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#ifdef HAVE_ATOMIC_OPS_H
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AO_TS_t busy; /* is the script-cache busy? */
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#else
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pthread_mutex_t lock;
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#endif
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unsigned short lru_head; /* index of lead-recently used script */
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unsigned short lru_tail; /* index of most-recently used script */
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/* hash table that maps instruction pointer to script index: */
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unsigned short hash[IA64_UNW_HASH_SIZE];
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uint32_t generation; /* generation number */
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/* script cache: */
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struct ia64_script buckets[IA64_UNW_CACHE_SIZE];
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};
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#define ia64_cache_proc_info UNW_OBJ(cache_proc_info)
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#define ia64_get_cached_proc_info UNW_OBJ(get_cached_proc_info)
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struct cursor; /* forward declaration */
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extern int ia64_cache_proc_info (struct cursor *c);
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extern int ia64_get_cached_proc_info (struct cursor *c);
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