mirror of
https://github.com/intel/linux-sgx
synced 2026-06-08 14:49:32 +00:00
b0af6e75ac
Along with the latest processor microcode address CVE-2022-21233. Modified the Switchless library to have mitigations for the associated issue. Added support for the Linux kernel APIs for the Enclave Dynamic Memory Management (EDMM) features that are available with the Linux kernel v6.0 or later. Refer to the SGX SDK developer reference for details on new trusted APIs and enclave configuration for the EDMM features. Enabled C++17 within SGX SDK. Supported AMX (Advanced Matrix Extensions) in Enclave. Replace hardcoded Enclave signing keys in all sample projects with dynamically generated keys. Added a new API to allow user to configure enclave internal cache size in the Protected File System library. Upgraded to OpenSSL 1.1.1q and upgraded Intel(R) SGX Quote Verification Enclave to integrate SgxSSL/OpenSSL version 1.1.1q. Supported new OS: Ubuntu* 22.04 LTS 64-bit Server version, CentOS* 8.3 64bits, Red Hat* Enterprise Linux* Server 8.6 (for x86_64), SUSE* Linux* Enterprise Server 15.4 64bits, Debian* 10 and Anolis* OS 8.6. Upgraded Intel SGX QE3 to make it backward compatible. Improved ECDSA quote generation and verification performance by caching PCK certificates and collaterals in memory and disk drive. Added Java support for quote verification library. Added new APIs to unify Intel SGX and TDX quote verification in Quote Verification Library. Added Advisory ID in ECDSA quote verification supplemental data. Added Intel TDX support in RA-TLS (Remote Attestation based TLS) library. Improved TDX quote generation throughput in vsock mode. Added Rust support for TDX quote generation. Fixed bugs. Signed-off-by: Li, Xun <xun.li@intel.com>
750 lines
21 KiB
C
750 lines
21 KiB
C
/*
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* Copyright (C) 2011-2021 Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include "arch.h"
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#include "thread_data.h"
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#include "util.h"
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#include "se_trace.h"
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#include "se_memory.h"
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#include <unistd.h>
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#include <dlfcn.h>
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#include <stdarg.h>
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#include <stdio.h>
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#include <sys/user.h>
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#include <sys/ptrace.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <fcntl.h>
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#include <elf.h>
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#include <assert.h>
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#include <signal.h>
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#include <sys/wait.h>
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//NOTE: Need align with thread_data_t in RTS.
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#define ELF32_SSA_FS_OFFSET 0x34
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#ifdef __x86_64__
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#define SSA2USER_REG(to, from, name) to->r##name = from.r##name
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#define USER_REG2SSA(to, from, name) to.r##name = from->r##name
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#else
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#define SSA2USER_REG(to, from, name) to->e##name = from.e##name
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#define USER_REG2SSA(to, from, name) to.e##name = from->e##name
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#endif
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#define XSTATE_MAX_SIZE 832
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typedef enum _direction_t
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{
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FORWARD,
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BACKWARD
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} direction_t;
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typedef long int (* ptrace_t)(enum __ptrace_request request, pid_t pid,
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void *addr, void *data);
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typedef pid_t (*waitpid_t)(pid_t pid, int *status, int options);
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static ptrace_t g_sys_ptrace = NULL;
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static waitpid_t g_sys_waitpid = NULL;
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__attribute__((constructor)) void init()
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{
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g_sys_ptrace = (ptrace_t)dlsym(RTLD_NEXT, "ptrace");
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g_sys_waitpid = (waitpid_t)dlsym(RTLD_NEXT, "waitpid");
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}
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#ifdef SE_DEBUG
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static void dump_ssa_gregs(ssa_gpr_t* gpr) __attribute__((unused));
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void dump_ssa_gregs(ssa_gpr_t* gpr)
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{
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SE_TRACE(SE_TRACE_DEBUG, "ssa generic registers:\n");
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SE_TRACE(SE_TRACE_DEBUG, "xbx = %#lx\t", gpr->REG(bx));
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SE_TRACE(SE_TRACE_DEBUG, "xcx = %#lx\t", gpr->REG(cx));
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SE_TRACE(SE_TRACE_DEBUG, "xdx = %#lx\t", gpr->REG(dx));
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SE_TRACE(SE_TRACE_DEBUG, "xsi = %#lx\t", gpr->REG(si));
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SE_TRACE(SE_TRACE_DEBUG, "xdi = %#lx\t", gpr->REG(di));
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SE_TRACE(SE_TRACE_DEBUG, "xbp = %#lx\t", gpr->REG(bp));
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SE_TRACE(SE_TRACE_DEBUG, "xax = %#lx\t", gpr->REG(ax));
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SE_TRACE(SE_TRACE_DEBUG, "xip = %#lx\t", gpr->REG(ip));
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SE_TRACE(SE_TRACE_DEBUG, "xflags = %#lx\t", gpr->REG(flags));
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SE_TRACE(SE_TRACE_DEBUG, "xsp = %#lx\t", gpr->REG(sp));
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}
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static void dump_regs(struct user_regs_struct *regs) __attribute__((unused));
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void dump_regs(struct user_regs_struct *regs)
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{
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SE_TRACE(SE_TRACE_DEBUG, "user regisers:\n");
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SE_TRACE(SE_TRACE_DEBUG, "xbx = %#x\t", regs->REG(bx));
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SE_TRACE(SE_TRACE_DEBUG, "xcx = %#x\t", regs->REG(cx));
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SE_TRACE(SE_TRACE_DEBUG, "xdx = %#x\t", regs->REG(dx));
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SE_TRACE(SE_TRACE_DEBUG, "xsi = %#x\t", regs->REG(si));
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SE_TRACE(SE_TRACE_DEBUG, "xdi = %#x\t", regs->REG(di));
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SE_TRACE(SE_TRACE_DEBUG, "xbp = %#x\t", regs->REG(bp));
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SE_TRACE(SE_TRACE_DEBUG, "xax = %#x\t", regs->REG(ax));
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SE_TRACE(SE_TRACE_DEBUG, "xip = %#x\t", regs->REG(ip));
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SE_TRACE(SE_TRACE_DEBUG, "xflags = %#x\t", regs->eflags);
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SE_TRACE(SE_TRACE_DEBUG, "xsp = %#x\t", regs->REG(sp));
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}
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#else
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#define dump_ssa_gregs(gpr)
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#define dump_regs(regs)
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#endif
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#ifdef __x86_64__
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static int get_exec_class(pid_t pid)
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{
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char filename[64];
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int fd = -1;
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unsigned char e_ident[EI_NIDENT];
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snprintf(filename, 64, "/proc/%d/exe", pid);
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fd = open(filename, O_RDONLY | O_LARGEFILE);
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if(fd == -1)
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return ELFCLASSNONE;
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if(-1 == read(fd, e_ident, EI_NIDENT))
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{
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close(fd);
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return ELFCLASSNONE;
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}
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close(fd);
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return e_ident[EI_CLASS];
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}
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#endif
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static inline uint32_t get_ssa_frame_size(pid_t pid, thread_data_t* td)
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{
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uint32_t ssa_frame_size = ROUND_TO_PAGE(td->xsave_size) >> SE_PAGE_SHIFT;
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#ifdef __x86_64__
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//on x64, we may debug elf32 enclave, we need refer to different offset in td field.
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if(ELFCLASS32 == get_exec_class(pid))
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{
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ssa_frame_size = *GET_PTR(uint32_t, td, ELF32_SSA_FS_OFFSET);
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}
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#else
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UNUSED(pid);
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#endif
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//When debug trts, ssa_frame_size in TD is not initialized, so the value will be 0.
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//It is a limitation to debug trts. As a workaround, set the default page to 1, so
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//we can debug enclave from the start of enclave_entry. It works on most platforms
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//except the enclave supports AMX.
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//AMX makes the ssa_frame_size more than 1 page. If AMX is enabled, the debugger will
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//only be workable after TD is initialized.
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if(0 == ssa_frame_size)
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ssa_frame_size = 1;
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return ssa_frame_size;
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}
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/*
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*This function get the position/offset with SSA
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* @pid, process id
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* @tcs_addr, TCS start address
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* @dir, calculate the position from start of SSA or from the end of SSA
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* @offset, offset from the start
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* @size, size of data from the postion that is going to be accessed
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* @pos, the result of postion that the function output
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* @return, TRUE on success, FALSE on fail. The result is copied to parameter pos
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* */
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static int get_ssa_pos(pid_t pid, long tcs_addr, direction_t dir, long offset, long size, long *pos)
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{
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tcs_t tcs;
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thread_data_t td;
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uint32_t ssa_frame_size = 0;
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long addr = 0;
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//read TCS;
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if(!se_read_process_mem(pid, (void *)tcs_addr, (void *)&tcs, 72, NULL))
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return FALSE;
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//Align with RTS. We assume TD is next to TCS
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long ssa_start = tcs_addr + TCS_SIZE;
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//ossa point to the start address of SSA, and fs/gs point to the start address of TD.
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long td_start = ssa_start - tcs.ossa + tcs.ofs_base;
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//Read thread data; On x64, sizeof(thread_data_t) of elf64 is larger than elf32,
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//so it won't miss any field if it is elf32 executable;
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if(!se_read_process_mem(pid, (void *)td_start, (void *)&td, sizeof(thread_data_t), NULL))
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return FALSE;
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ssa_frame_size = get_ssa_frame_size(pid, &td);
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//The request should not exceed ssa frame boundary.
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if((offset + size) > (long)ssa_frame_size * SE_PAGE_SIZE)
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return FALSE;
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assert(tcs.cssa > 0);
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//If it is required to calculate from the start of SSA
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if(FORWARD == dir)
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{
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addr = ssa_start + (tcs.cssa - 1) * ssa_frame_size * SE_PAGE_SIZE + offset;
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}
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//If it is required to calculate from the end of SSA
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else if(BACKWARD == dir)
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{
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addr = ssa_start + tcs.cssa * ssa_frame_size * SE_PAGE_SIZE - offset;
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}
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else
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return FALSE;
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*pos = addr;
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return TRUE;
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}
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static inline int read_ssa(pid_t pid, long tcs_addr, direction_t dir, long offset, long size, void *buf)
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{
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long addr = 0;
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if(!get_ssa_pos(pid, tcs_addr, dir, offset, size, &addr))
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return FALSE;
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//read the content of ssa
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if(!se_read_process_mem(pid, (void *)addr, buf, size, NULL))
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return FALSE;
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return TRUE;
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}
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static inline int write_ssa(pid_t pid, long tcs_addr, direction_t dir, long offset, long size, void *buf)
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{
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long addr = 0;
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if(!get_ssa_pos(pid, tcs_addr, dir, offset, size, &addr))
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return FALSE;
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//write the content of ssa
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if(!se_write_process_mem(pid, (void *)addr, buf, size, NULL))
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return FALSE;
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return TRUE;
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}
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static inline int get_ssa_gpr(pid_t pid, long tcs_addr, ssa_gpr_t* gpr)
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{
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//read general registers. ssa_gpr_t is elf32/elf64 independent.
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return read_ssa(pid, tcs_addr, BACKWARD, sizeof(ssa_gpr_t), sizeof(ssa_gpr_t), (void *)gpr);
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}
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static inline int set_ssa_gpr(pid_t pid, long tcs_addr, ssa_gpr_t* gpr)
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{
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//read general registers. ssa_gpr_t is elf32/elf64 independent.
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return write_ssa(pid, tcs_addr, BACKWARD, sizeof(ssa_gpr_t), sizeof(ssa_gpr_t), (void *)gpr);
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}
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static inline int get_ssa_fpregs(pid_t pid, long tcs_addr, struct user_fpregs_struct* fpregs)
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{
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return read_ssa(pid, tcs_addr, FORWARD, 0, sizeof(struct user_fpregs_struct), (void *)fpregs);
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}
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static inline int set_ssa_fpregs(pid_t pid, long tcs_addr, struct user_fpregs_struct* fpregs)
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{
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return write_ssa(pid, tcs_addr, FORWARD, 0, sizeof(struct user_fpregs_struct), (void *)fpregs);
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}
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#if !defined(__x86_64__) && !defined(__x86_64)
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static inline int get_ssa_fpxregs(pid_t pid, long tcs_addr, struct user_fpxregs_struct* fpxregs)
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{
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return read_ssa(pid, tcs_addr, FORWARD, 0, sizeof(struct user_fpxregs_struct), (void *)fpxregs);
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}
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static inline int set_ssa_fpxregs(pid_t pid, long tcs_addr, struct user_fpxregs_struct* fpxregs)
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{
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return write_ssa(pid, tcs_addr, FORWARD, 0, sizeof(struct user_fpxregs_struct), (void *)fpxregs);
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}
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#else
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#define get_ssa_fpxregs get_ssa_fpregs
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#define set_ssa_fpxregs set_ssa_fpregs
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#define user_fpxregs_struct user_fpregs_struct
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#endif
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static inline int get_ssa_xstate(pid_t pid, long tcs_addr, int len, char *buf)
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{
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return read_ssa(pid, tcs_addr, FORWARD, 0, len, buf);
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}
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static inline int set_ssa_xstate(pid_t pid, long tcs_addr, int len, char *buf)
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{
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return write_ssa(pid, tcs_addr, FORWARD, 0, len, buf);
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}
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static int get_enclave_gregs(pid_t pid, struct user_regs_struct *regs, long tcs_addr)
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{
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ssa_gpr_t gpr;
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if(!get_ssa_gpr(pid, tcs_addr, &gpr))
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return -1;
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//convert gpr to user_regs_struct.
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SSA2USER_REG(regs, gpr, bx);
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SSA2USER_REG(regs, gpr, cx);
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SSA2USER_REG(regs, gpr, dx);
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SSA2USER_REG(regs, gpr, si);
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SSA2USER_REG(regs, gpr, di);
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SSA2USER_REG(regs, gpr, bp);
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SSA2USER_REG(regs, gpr, ax);
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SSA2USER_REG(regs, gpr, ip);
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regs->eflags = gpr.REG(flags);
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SSA2USER_REG(regs, gpr, sp);
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#ifdef __x86_64__
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SSA2USER_REG(regs, gpr, 8);
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SSA2USER_REG(regs, gpr, 9);
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SSA2USER_REG(regs, gpr, 10);
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SSA2USER_REG(regs, gpr, 11);
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SSA2USER_REG(regs, gpr, 12);
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SSA2USER_REG(regs, gpr, 13);
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SSA2USER_REG(regs, gpr, 14);
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SSA2USER_REG(regs, gpr, 15);
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#endif
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return 0;
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}
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static int set_enclave_gregs(pid_t pid, struct user_regs_struct *regs, long tcs_addr)
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{
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ssa_gpr_t gpr;
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//Since there is some field won't be written, we need save it first
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if(!get_ssa_gpr(pid, tcs_addr, &gpr))
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return -1;
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//convert gpr to user_regs_struct.
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USER_REG2SSA(gpr, regs, bx);
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USER_REG2SSA(gpr, regs, cx);
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USER_REG2SSA(gpr, regs, dx);
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USER_REG2SSA(gpr, regs, si);
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USER_REG2SSA(gpr, regs, di);
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USER_REG2SSA(gpr, regs, bp);
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USER_REG2SSA(gpr, regs, ax);
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USER_REG2SSA(gpr, regs, ip);
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gpr.REG(flags) = regs->eflags;
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USER_REG2SSA(gpr, regs, sp);
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#ifdef __x86_64__
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USER_REG2SSA(gpr, regs, 8);
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USER_REG2SSA(gpr, regs, 9);
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USER_REG2SSA(gpr, regs, 10);
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USER_REG2SSA(gpr, regs, 11);
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USER_REG2SSA(gpr, regs, 12);
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USER_REG2SSA(gpr, regs, 13);
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USER_REG2SSA(gpr, regs, 14);
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USER_REG2SSA(gpr, regs, 15);
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#endif
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//write general registers to ssa
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if(!set_ssa_gpr(pid, tcs_addr, &gpr))
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return -1;
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return 0;
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}
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static int is_eresume(pid_t pid, struct user_regs_struct *regs)
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{
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unsigned int instr;
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if(!se_read_process_mem(pid, (void *)regs->REG(ip), (char *)&instr, sizeof(instr), NULL))
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return FALSE;
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if((ENCLU == (instr & 0xffffff))
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&& (SE_ERESUME == regs->REG(ax)))
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return TRUE;
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return FALSE;
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}
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static long int get_regs(pid_t pid, void* addr, void* data)
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{
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int ret = 0;
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if(!data)
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return -1;
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struct user_regs_struct *regs = (struct user_regs_struct *)data;
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if(-1 == (ret = g_sys_ptrace(PTRACE_GETREGS, pid, addr, data)))
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return -1;
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if(is_eresume(pid, regs))
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{
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//If it is ERESUME instruction, set the real register value
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get_enclave_gregs(pid, regs, regs->REG(bx));
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}
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return ret;
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}
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typedef struct _thread_status_t {
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pid_t pid;
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int inside_out;
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int singlestep;
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struct user_regs_struct aep_regs;
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struct _thread_status_t *next;
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} thread_status_t;
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static thread_status_t * g_thread_status = NULL;
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/*
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*get the thread info by pid
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*return the status point if the thread info already cached
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*otherwise return NULL
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*
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*/
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static thread_status_t * get_thread_status(pid_t pid)
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{
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thread_status_t * thread_status = g_thread_status;
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while(thread_status)
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{
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if(thread_status->pid == pid)
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break;
|
|
else
|
|
thread_status = thread_status->next;
|
|
}
|
|
|
|
return thread_status;
|
|
}
|
|
|
|
/*
|
|
*add thread status cache
|
|
*return the cache point
|
|
*/
|
|
static thread_status_t * add_thread_status(pid_t pid)
|
|
{
|
|
thread_status_t * thread_status = (thread_status_t *)malloc(sizeof(thread_status_t));
|
|
if (thread_status == NULL)
|
|
return NULL;
|
|
|
|
memset(thread_status, 0, sizeof(thread_status_t));
|
|
|
|
thread_status->pid = pid;
|
|
thread_status->next = g_thread_status;
|
|
g_thread_status = thread_status;
|
|
|
|
return thread_status;
|
|
}
|
|
/*
|
|
*remove the thread status cache by pid
|
|
*
|
|
*/
|
|
static void remove_thread_status(pid_t pid)
|
|
{
|
|
thread_status_t * thread_status = g_thread_status;
|
|
thread_status_t * previous_link = NULL;
|
|
|
|
while(thread_status)
|
|
{
|
|
if(thread_status->pid == pid)
|
|
break;
|
|
else
|
|
{
|
|
previous_link = thread_status;
|
|
thread_status = thread_status->next;
|
|
}
|
|
}
|
|
|
|
if (thread_status != NULL)
|
|
{
|
|
if (previous_link == NULL)
|
|
{
|
|
g_thread_status = thread_status->next;
|
|
} else {
|
|
previous_link->next = thread_status->next;
|
|
}
|
|
|
|
free(thread_status);
|
|
}
|
|
}
|
|
|
|
static long int set_regs(pid_t pid, void* addr, void* data)
|
|
{
|
|
int ret = 0;
|
|
struct user_regs_struct aep_regs;
|
|
|
|
if(!data)
|
|
return -1;
|
|
if(-1 == g_sys_ptrace(PTRACE_GETREGS, pid, 0, (void*)&aep_regs))
|
|
return -1;
|
|
if(is_eresume(pid, &aep_regs))
|
|
{
|
|
struct user_regs_struct *regs = (struct user_regs_struct *)data;
|
|
//get tcs address
|
|
if(-1 == (ret = set_enclave_gregs(pid, regs, aep_regs.REG(bx))))
|
|
return -1;
|
|
else
|
|
return ret;
|
|
}
|
|
else
|
|
{
|
|
return g_sys_ptrace(PTRACE_SETREGS, pid, addr, data);
|
|
}
|
|
}
|
|
|
|
|
|
static long int get_fpregs(pid_t pid, void* addr, void* data, int extend)
|
|
{
|
|
int ret = 0;
|
|
|
|
if(!data)
|
|
return -1;
|
|
struct user_regs_struct regs;
|
|
if(-1 == (ret = g_sys_ptrace(PTRACE_GETREGS, pid, 0, ®s)))
|
|
return -1;
|
|
if(is_eresume(pid, ®s))
|
|
{
|
|
if(extend)
|
|
ret = get_ssa_fpxregs(pid, regs.REG(bx), (struct user_fpxregs_struct *)data);
|
|
else
|
|
ret = get_ssa_fpregs(pid, regs.REG(bx), (struct user_fpregs_struct *)data);
|
|
if(ret)
|
|
return 0;
|
|
else
|
|
return -1;
|
|
}
|
|
else
|
|
{
|
|
return g_sys_ptrace(PTRACE_GETFPREGS, pid, addr, data);
|
|
}
|
|
}
|
|
|
|
static long int set_fpregs(pid_t pid, void* addr, void* data, int extend)
|
|
{
|
|
int ret = 0;
|
|
|
|
if(!data)
|
|
return -1;
|
|
struct user_regs_struct regs;
|
|
if(-1 == (ret = g_sys_ptrace(PTRACE_GETREGS, pid, 0, ®s)))
|
|
return -1;
|
|
if(is_eresume(pid, ®s))
|
|
{
|
|
if(extend)
|
|
ret = set_ssa_fpxregs(pid, regs.REG(bx), (struct user_fpxregs_struct *)data);
|
|
else
|
|
ret = set_ssa_fpregs(pid, regs.REG(bx), (struct user_fpregs_struct *)data);
|
|
if(ret)
|
|
return 0;
|
|
else
|
|
return -1;
|
|
}
|
|
else
|
|
{
|
|
return g_sys_ptrace(PTRACE_GETFPREGS, pid, addr, data);
|
|
}
|
|
}
|
|
|
|
static long int get_regset(pid_t pid, void* addr, void* data)
|
|
{
|
|
int ret = 0;
|
|
unsigned long type = (unsigned long)addr;
|
|
|
|
if(!data)
|
|
return -1;
|
|
struct user_regs_struct regs;
|
|
if(-1 == (ret = g_sys_ptrace(PTRACE_GETREGS, pid, 0, ®s)))
|
|
return -1;
|
|
|
|
if(is_eresume(pid, ®s))
|
|
{
|
|
if(NT_X86_XSTATE != type)
|
|
{
|
|
SE_TRACE(SE_TRACE_WARNING, "unexpected type for PTRACE_GETREGSET\n");
|
|
return -1;
|
|
}
|
|
struct iovec *iov = (struct iovec *)data;
|
|
if(iov->iov_base && iov->iov_len
|
|
&& get_ssa_xstate(pid, regs.REG(bx), iov->iov_len, (char *)iov->iov_base))
|
|
{
|
|
return 0;
|
|
}
|
|
else
|
|
return -1;
|
|
}
|
|
else
|
|
{
|
|
return g_sys_ptrace(PTRACE_GETREGSET, pid, addr, data);
|
|
}
|
|
}
|
|
|
|
static long int set_regset(pid_t pid, void* addr, void* data)
|
|
{
|
|
int ret = 0;
|
|
unsigned long type = (unsigned long)addr;
|
|
|
|
if(!data)
|
|
return -1;
|
|
struct user_regs_struct regs;
|
|
if(-1 == (ret = g_sys_ptrace(PTRACE_GETREGS, pid, 0, ®s)))
|
|
return -1;
|
|
|
|
if(is_eresume(pid, ®s))
|
|
{
|
|
if(NT_X86_XSTATE != type)
|
|
{
|
|
SE_TRACE(SE_TRACE_WARNING, "unexpected type for PTRACE_SETREGSET\n");
|
|
return -1;
|
|
}
|
|
struct iovec *iov = (struct iovec *)data;
|
|
if(iov->iov_base && iov->iov_len
|
|
&& set_ssa_xstate(pid, regs.REG(bx), iov->iov_len, (char *)iov->iov_base))
|
|
{
|
|
return 0;
|
|
}
|
|
else
|
|
return -1;
|
|
}
|
|
else
|
|
{
|
|
return g_sys_ptrace(PTRACE_SETREGSET, pid, addr, data);
|
|
}
|
|
}
|
|
|
|
static long int do_singlestep(pid_t pid, void* addr, void* data)
|
|
{
|
|
thread_status_t * thread_status = NULL;
|
|
if ((thread_status = get_thread_status(pid)) == NULL)
|
|
thread_status = add_thread_status(pid);
|
|
|
|
if (thread_status != NULL)
|
|
thread_status->singlestep = 1;
|
|
|
|
return g_sys_ptrace(PTRACE_SINGLESTEP, pid, addr, data);
|
|
}
|
|
|
|
long int ptrace (enum __ptrace_request __request, ...)
|
|
{
|
|
pid_t pid;
|
|
void *addr, *data;
|
|
va_list ap;
|
|
|
|
va_start(ap, __request);
|
|
pid = va_arg(ap, pid_t);
|
|
addr = va_arg(ap, void *);
|
|
data = va_arg(ap, void *);
|
|
va_end(ap);
|
|
|
|
if(__request == PTRACE_GETREGS)
|
|
{
|
|
return get_regs(pid, addr, data);
|
|
}
|
|
else if(__request == PTRACE_SETREGS)
|
|
{
|
|
return set_regs(pid, addr, data);
|
|
}
|
|
#if 0
|
|
//some old system may require this command to get register
|
|
else if(__request == PTRACE_PEEKUSER)
|
|
{
|
|
|
|
}
|
|
#endif
|
|
else if(__request == PTRACE_GETFPREGS)
|
|
{
|
|
return get_fpregs(pid, addr, data, FALSE);
|
|
}
|
|
else if(__request == PTRACE_SETFPREGS)
|
|
{
|
|
return set_fpregs(pid, addr, data, FALSE);
|
|
|
|
}
|
|
else if(__request == PTRACE_GETFPXREGS)
|
|
{
|
|
return get_fpregs(pid, addr, data, TRUE);
|
|
}
|
|
else if(__request == PTRACE_SETFPXREGS)
|
|
{
|
|
return set_fpregs(pid, addr, data, TRUE);
|
|
}
|
|
|
|
//xstave for avx
|
|
else if(__request == PTRACE_GETREGSET)
|
|
{
|
|
return get_regset(pid, addr, data);
|
|
}
|
|
else if(__request == PTRACE_SETREGSET)
|
|
{
|
|
return set_regset(pid, addr, data);
|
|
}
|
|
else if(__request == PTRACE_SINGLESTEP)
|
|
{
|
|
return do_singlestep(pid, addr, data);
|
|
}
|
|
//For other request just forward it to real ptrace call;
|
|
return g_sys_ptrace(__request, pid, addr, data);
|
|
}
|
|
|
|
pid_t waitpid(pid_t pid, int *status, int options)
|
|
{
|
|
pid_t ret_pid = g_sys_waitpid(pid, status, options);
|
|
|
|
if (ret_pid == -1 || status == NULL)
|
|
return ret_pid;
|
|
|
|
if (WIFEXITED(*status) || WIFSIGNALED(*status))
|
|
{
|
|
remove_thread_status(ret_pid);
|
|
}
|
|
|
|
//if it is a TRAP, and inside enclave, fix the #BP info
|
|
if(WIFSTOPPED(*status) &&
|
|
WSTOPSIG(*status) == SIGTRAP)
|
|
{
|
|
struct user_regs_struct regs;
|
|
thread_status_t * thread_status = get_thread_status(ret_pid);
|
|
|
|
if(thread_status && thread_status->singlestep == 1)
|
|
{
|
|
thread_status->singlestep = 0;
|
|
}
|
|
else if(-1 == g_sys_ptrace(PTRACE_GETREGS, ret_pid, 0, ®s))
|
|
{
|
|
SE_TRACE(SE_TRACE_WARNING, "unexpected get context failed\n");
|
|
}
|
|
else if(is_eresume(ret_pid, ®s))
|
|
{
|
|
long tcs = regs.REG(bx);
|
|
//If it is ERESUME instruction, set the real register value
|
|
if(-1 != get_enclave_gregs(ret_pid, ®s, tcs))
|
|
{
|
|
uint8_t bp = 0;
|
|
if(!se_read_process_mem(ret_pid, (void *)regs.REG(ip), (void *)&bp, 1, NULL))
|
|
{
|
|
SE_TRACE(SE_TRACE_WARNING, "unexpected read memory failed\n");
|
|
}
|
|
else if (bp == 0xcc)
|
|
{
|
|
regs.REG(ip)++;
|
|
if ( -1 == set_enclave_gregs(ret_pid, ®s, tcs))
|
|
{
|
|
SE_TRACE(SE_TRACE_WARNING, "unexpected set registers failed\n");
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return ret_pid;
|
|
}
|