mirror of
https://github.com/intel/linux-sgx
synced 2026-06-08 14:49:32 +00:00
Li, Xun
8a22317709
Upgraded to OpenSSL 3.0.10. Added interoperable RA-TLS support which follows CCC design. Enhanced Protect File System performance and added additional dependency `libsgx_pthread.a`. Added the Constant Time instruction Decoder (CTD) into the default AEX-Notify mitigation handler in order to prevent the introduction of any additional subtle sidechannel leakages within the default handler. Added Mistletoe 3 mitigations to the IPP Cryptography Library to the AES-ECB, AESGCM, and AES-CMAC algorithms. These have been incorporated transparently into the `sgx_tcrypto` library. Resigned all Intel® SGX Architecture Enclaves. Upgraded Intel SGX Quote Verification Enclave to integrate OpenSSL/SgxSSL 3.0.10. Added Attestation Library support for Intel(R) TDX Migration TD. Added Rust wrapper for low-level Quote Generation APIs. Enabled `SE_TRACE` log in release binary. Updated Rust QVL wrapper to use native Rust structure for quote verification collateral. Added a limitation in the DCAP QVL to only allow the user to set the QvE load policy once. Fixed bugs. Signed-off-by: Li, Xun <xun.li@intel.com>
443 lines
18 KiB
C++
443 lines
18 KiB
C++
/*
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* Copyright (C) 2011-2021 Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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// t_instructions.cpp -- It simulates Enclave instructions.
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#include <string.h>
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#include <stdlib.h>
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#include "arch.h"
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#include "util.h"
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#include "lowlib.h"
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#include "sgx_trts.h"
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#include "trts_inst.h"
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#include "deriv.h"
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#include "t_instructions.h"
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#include "td_mngr.h"
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////////////////////////////////////////////////////////////////////////
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global_data_sim_t g_global_data_sim = {NULL, {{0}}, 0};
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#define GP() abort()
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#define GP_ON(cond) do { if (unlikely(cond)) GP(); } while (0)
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////////////////////////////////////////////////////////////////////////
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// Simulation for EGETKEY
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////////////////////////////////////////////////////////////////////////
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// The hard-coded OwnerEpoch.
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static const se_owner_epoch_t SIMU_OWNER_EPOCH_MSR = {
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0x54, 0x48, 0x49, 0x53, 0x49, 0x53, 0x4f, 0x57,
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0x4e, 0x45, 0x52, 0x45, 0x50, 0x4f, 0x43, 0x48,
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};
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#define check_cpu_svn(kr) do { \
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if(memcmp(&kr->cpu_svn, &UPGRADED_CPUSVN, sizeof(UPGRADED_CPUSVN)) && \
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memcmp(&kr->cpu_svn, &DEFAULT_CPUSVN, sizeof(DEFAULT_CPUSVN)) && \
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memcmp(&kr->cpu_svn, &DOWNGRADED_CPUSVN, sizeof(DOWNGRADED_CPUSVN))){ \
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return EGETKEY_INVALID_CPUSVN; \
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} \
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if ( (!memcmp(&g_global_data_sim.cpusvn_sim, &DEFAULT_CPUSVN, sizeof(DEFAULT_CPUSVN)) && \
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!memcmp(&kr->cpu_svn, &UPGRADED_CPUSVN, sizeof(UPGRADED_CPUSVN))) || \
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(!memcmp(&g_global_data_sim.cpusvn_sim, &DOWNGRADED_CPUSVN, sizeof(DOWNGRADED_CPUSVN)) && \
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memcmp(&kr->cpu_svn, &DOWNGRADED_CPUSVN, sizeof(DOWNGRADED_CPUSVN)))){ \
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return EGETKEY_INVALID_CPUSVN; \
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} \
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} while(0)
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#define check_isv_svn(kr, secs) do { \
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if (kr->isv_svn > secs->isv_svn) { \
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return EGETKEY_INVALID_ISVSVN; \
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} \
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} while(0)
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#define check_attr_flag(secs, flag) do { \
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if ((secs->attributes.flags & flag) == 0) { \
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return EGETKEY_INVALID_ATTRIBUTE; \
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} \
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} while(0)
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#define check_config_svn(kr, secs) do { \
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if (kr->config_svn > secs->config_svn) { \
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return EGETKEY_INVALID_ISVSVN; \
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} \
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} while(0)
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#define KEY_POLICY_KSS (SGX_KEYPOLICY_CONFIGID | SGX_KEYPOLICY_ISVFAMILYID | SGX_KEYPOLICY_ISVEXTPRODID)
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// The hardware EGETKEY instruction will set ZF on failure.
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//
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// In simulation mode, we can not guarentee that the ZF is always set
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// between _EGETKEY ending its life and tRTS testing ZF. Since there
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// are additional assembly code in between.
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//
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// In simulation mode, we check return code instead of ZF.
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// c.f. do_egetkey() in trts/linux/trts_pic.S
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static int _EGETKEY(sgx_key_request_t* kr, sgx_key_128bit_t okey)
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{
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// check alignment of KEYREQUEST
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GP_ON(((size_t)kr & (KEY_REQUEST_ALIGN_SIZE - 1)) != 0);
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// check to see if KEYREQEUST is inside the current enclave
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GP_ON(!sgx_is_within_enclave(kr, sizeof(sgx_key_request_t)));
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// check alignment of OUTPUTDATA
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GP_ON(((size_t)okey & (KEY_ALIGN_SIZE - 1)) != 0);
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// check to see if OUTPUTDATA is inside the current enclave
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GP_ON(!sgx_is_within_enclave(okey, sizeof(sgx_key_128bit_t)));
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// check reserved bits are not set
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GP_ON((kr->key_policy & ~(SGX_KEYPOLICY_MRENCLAVE | SGX_KEYPOLICY_MRSIGNER | KEY_POLICY_KSS | SGX_KEYPOLICY_NOISVPRODID)) != 0);
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// check to see if reserved space in KEYREQUEST are valid
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const uint8_t* u8ptr = (uint8_t *)(&(kr->reserved1));
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for (unsigned i = 0; i < sizeof(kr->reserved1); ++i)
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GP_ON(u8ptr[i] != (uint8_t)0);
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u8ptr = (uint8_t *)(&(kr->reserved2));
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for (unsigned i = 0; i < sizeof(kr->reserved2); ++i)
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GP_ON(u8ptr[i] != (uint8_t)0);
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secs_t* cur_secs = g_global_data_sim.secs_ptr;
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isv_ext_id_t* isv_ext_id = reinterpret_cast<isv_ext_id_t *>(cur_secs->reserved4);
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GP_ON(!(cur_secs->attributes.flags & SGX_FLAGS_KSS) &&
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((kr->key_policy & (KEY_POLICY_KSS | SGX_KEYPOLICY_NOISVPRODID)) ||kr->config_svn > 0));
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sgx_attributes_t tmp_attr;
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sgx_misc_select_t tmp_misc;
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derivation_data_t dd;
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memset(&dd, 0, sizeof(dd));
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dd.key_name = kr->key_name;
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// Determine which enclave attributes that must be included in the key.
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// Attributes that must always be included INIT & DEBUG.
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memset(&tmp_attr, 0, sizeof(tmp_attr));
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tmp_attr.flags = kr->attribute_mask.flags | SGX_FLAGS_INITTED | SGX_FLAGS_DEBUG;
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tmp_attr.flags &= cur_secs->attributes.flags;
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tmp_attr.xfrm = kr->attribute_mask.xfrm & cur_secs->attributes.xfrm;
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// Compute MISCSELECT fields to be included in the key.
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tmp_misc = kr->misc_mask & cur_secs->misc_select;
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// HW supports CPUSVN to be set as 0.
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// To be consistent with HW behaviour, we replace the cpusvn as DEFAULT_CPUSVN if the input cpusvn is 0.
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if(!memcmp(&kr->cpu_svn, &dd.ddpk.cpu_svn, sizeof(sgx_cpu_svn_t)))
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{
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memcpy(&kr->cpu_svn, &DEFAULT_CPUSVN, sizeof(sgx_cpu_svn_t));
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}
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switch (kr->key_name) {
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case SGX_KEYSELECT_SEAL:
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check_isv_svn(kr, cur_secs);
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check_config_svn(kr, cur_secs);
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check_cpu_svn(kr);
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// assemble derivation data
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dd.size = sizeof(dd_seal_key_t);
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dd.ddsk.key_policy = kr->key_policy;
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if (kr->key_policy & SGX_KEYPOLICY_MRENCLAVE) {
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memcpy(&dd.ddsk.mrenclave, &cur_secs->mr_enclave, sizeof(sgx_measurement_t));
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}
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if (kr->key_policy & SGX_KEYPOLICY_MRSIGNER) {
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memcpy(&dd.ddsk.mrsigner, &cur_secs->mr_signer, sizeof(sgx_measurement_t));
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}
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if (kr->key_policy & SGX_KEYPOLICY_ISVFAMILYID) {
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memcpy(&dd.ddsk.isv_family_id, &isv_ext_id->isv_family_id, sizeof(sgx_isvfamily_id_t));
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}
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if (kr->key_policy & SGX_KEYPOLICY_ISVEXTPRODID) {
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memcpy(&dd.ddsk.isv_ext_prod_id, &isv_ext_id->isv_ext_prod_id, sizeof(sgx_isvext_prod_id_t));
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}
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if (kr->key_policy & SGX_KEYPOLICY_CONFIGID) {
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dd.ddsk.config_svn = kr->config_svn;
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memcpy(&dd.ddsk.config_id, &cur_secs->config_id, sizeof(sgx_config_id_t));
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}
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memcpy(&dd.ddsk.tmp_attr, &tmp_attr, sizeof(sgx_attributes_t));
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memcpy(&dd.ddsk.attribute_mask, &kr->attribute_mask, sizeof(sgx_attributes_t));
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dd.ddsk.tmp_misc = tmp_misc;
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dd.ddsk.misc_mask = ~kr->misc_mask;
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memcpy(dd.ddsk.csr_owner_epoch, SIMU_OWNER_EPOCH_MSR, sizeof(se_owner_epoch_t));
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memcpy(&dd.ddsk.cpu_svn,&kr->cpu_svn,sizeof(sgx_cpu_svn_t));
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dd.ddsk.isv_svn = kr->isv_svn;
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if (!(kr->key_policy & SGX_KEYPOLICY_NOISVPRODID)) {
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dd.ddsk.isv_prod_id = cur_secs->isv_prod_id;
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}
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memcpy(&dd.ddsk.key_id, &kr->key_id, sizeof(sgx_key_id_t));
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break;
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case SGX_KEYSELECT_REPORT:
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// assemble derivation data
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dd.size = sizeof(dd_report_key_t);
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memcpy(&dd.ddrk.attributes, &cur_secs->attributes, sizeof(sgx_attributes_t));
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dd.ddrk.misc_select = cur_secs->misc_select;
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memcpy(dd.ddrk.csr_owner_epoch, SIMU_OWNER_EPOCH_MSR, sizeof(se_owner_epoch_t));
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memcpy(&dd.ddrk.cpu_svn,&(g_global_data_sim.cpusvn_sim),sizeof(sgx_cpu_svn_t));
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memcpy(&dd.ddrk.mrenclave, &cur_secs->mr_enclave, sizeof(sgx_measurement_t));
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dd.ddrk.config_svn = cur_secs->config_svn;
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memcpy(&dd.ddrk.config_id, &cur_secs->config_id, sizeof(sgx_config_id_t));
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memcpy(&dd.ddrk.key_id, &kr->key_id, sizeof(sgx_key_id_t));
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break;
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case SGX_KEYSELECT_EINITTOKEN:
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check_attr_flag(cur_secs, SGX_FLAGS_EINITTOKEN_KEY);
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check_isv_svn(kr, cur_secs);
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check_cpu_svn(kr);
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// assemble derivation data
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dd.size = sizeof(dd_license_key_t);
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memcpy(&dd.ddlk.tmp_attr, &tmp_attr, sizeof(sgx_attributes_t));
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dd.ddlk.tmp_misc = tmp_misc;
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memcpy(dd.ddlk.csr_owner_epoch, SIMU_OWNER_EPOCH_MSR, sizeof(se_owner_epoch_t));
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memcpy(&dd.ddlk.cpu_svn,&kr->cpu_svn,sizeof(sgx_cpu_svn_t));
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dd.ddlk.isv_svn = kr->isv_svn;
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dd.ddlk.isv_prod_id = cur_secs->isv_prod_id;
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memcpy(&dd.ddlk.mrsigner, &cur_secs->mr_signer, sizeof(sgx_measurement_t));
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memcpy(&dd.ddlk.key_id, &kr->key_id, sizeof(sgx_key_id_t));
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break;
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case SGX_KEYSELECT_PROVISION:
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check_attr_flag(cur_secs, SGX_FLAGS_PROVISION_KEY);
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check_isv_svn(kr, cur_secs);
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check_cpu_svn(kr);
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// assemble derivation data
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dd.size = sizeof(dd_provision_key_t);
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memcpy(&dd.ddpk.tmp_attr, &tmp_attr, sizeof(sgx_attributes_t));
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memcpy(&dd.ddpk.attribute_mask, &kr->attribute_mask, sizeof(sgx_attributes_t));
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dd.ddpk.tmp_misc = tmp_misc;
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dd.ddpk.misc_mask = ~kr->misc_mask;
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memcpy(&dd.ddpk.cpu_svn,&kr->cpu_svn,sizeof(sgx_cpu_svn_t));
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dd.ddpk.isv_svn = kr->isv_svn;
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dd.ddpk.isv_prod_id = cur_secs->isv_prod_id;
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memcpy(&dd.ddpk.mrsigner, &cur_secs->mr_signer, sizeof(sgx_measurement_t));
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break;
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case SGX_KEYSELECT_PROVISION_SEAL:
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check_attr_flag(cur_secs, SGX_FLAGS_PROVISION_KEY);
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check_isv_svn(kr, cur_secs);
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check_config_svn(kr, cur_secs);
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check_cpu_svn(kr);
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// assemble derivation data
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dd.size = sizeof(dd_provision_seal_key_t);
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dd.ddpsk.key_policy = kr->key_policy;
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if (kr->key_policy & SGX_KEYPOLICY_ISVFAMILYID) {
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memcpy(&dd.ddpsk.isv_family_id, &isv_ext_id->isv_family_id, sizeof(sgx_isvfamily_id_t));
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}
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if (kr->key_policy & SGX_KEYPOLICY_ISVEXTPRODID) {
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memcpy(&dd.ddpsk.isv_ext_prod_id, &isv_ext_id->isv_ext_prod_id, sizeof(sgx_isvext_prod_id_t));
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}
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if (kr->key_policy & SGX_KEYPOLICY_CONFIGID) {
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dd.ddpsk.config_svn = kr->config_svn;
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memcpy(&dd.ddpsk.config_id, &cur_secs->config_id, sizeof(sgx_config_id_t));
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}
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memcpy(&dd.ddpsk.tmp_attr, &tmp_attr, sizeof(sgx_attributes_t));
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memcpy(&dd.ddpsk.attribute_mask, &kr->attribute_mask, sizeof(sgx_attributes_t));
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dd.ddpsk.tmp_misc = tmp_misc;
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dd.ddpsk.misc_mask = ~kr->misc_mask;
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memcpy(&dd.ddpsk.cpu_svn,&kr->cpu_svn,sizeof(sgx_cpu_svn_t));
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dd.ddpsk.isv_svn = kr->isv_svn;
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if (!(kr->key_policy & SGX_KEYPOLICY_NOISVPRODID)) {
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dd.ddpsk.isv_prod_id = cur_secs->isv_prod_id;
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}
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memcpy(&dd.ddpsk.mrsigner, &cur_secs->mr_signer, sizeof(sgx_measurement_t));
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break;
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default:
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return EGETKEY_INVALID_KEYNAME;
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}
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derive_key(&dd, okey);
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return 0;
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}
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////////////////////////////////////////////////////////////////////////
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// Simulation for EREPORT
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////////////////////////////////////////////////////////////////////////
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static void _EREPORT(const sgx_target_info_t* ti, const sgx_report_data_t* rd, sgx_report_t* report)
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{
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// check alignment of TARGETINFO
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GP_ON(((size_t)ti & (TARGET_INFO_ALIGN_SIZE - 1)) != 0);
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// check to see if TARGETINFO is inside the current enclave
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GP_ON(!sgx_is_within_enclave(ti, sizeof(sgx_target_info_t)));
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// check alignment of REPORTDATA
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GP_ON(((size_t)rd & (REPORT_DATA_ALIGN_SIZE - 1)) != 0);
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// check to see if REPORTDATA is inside the current enclave
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GP_ON(!sgx_is_within_enclave(rd, sizeof(sgx_report_data_t)));
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// check alignment of OUTPUTDATA
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GP_ON(((size_t)report & (REPORT_ALIGN_SIZE - 1)) != 0);
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// check to see if OUTPUTDATA is inside the current enclave
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GP_ON(!sgx_is_within_enclave(report, sizeof(sgx_report_t)));
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secs_t* cur_secs = g_global_data_sim.secs_ptr;
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isv_ext_id_t* isv_ext_id = reinterpret_cast<isv_ext_id_t *>(cur_secs->reserved4);
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SE_DECLSPEC_ALIGN(REPORT_ALIGN_SIZE) sgx_report_t tmp_report;
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// assemble REPORT Data
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memset(&tmp_report, 0, sizeof(tmp_report));
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memcpy(&tmp_report.body.cpu_svn,&(g_global_data_sim.cpusvn_sim),sizeof(sgx_cpu_svn_t));
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tmp_report.body.misc_select = cur_secs->misc_select;
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tmp_report.body.isv_prod_id = cur_secs->isv_prod_id;
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tmp_report.body.isv_svn = cur_secs->isv_svn;
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tmp_report.body.config_svn = cur_secs->config_svn;
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memcpy(&tmp_report.body.isv_family_id, &isv_ext_id->isv_family_id, sizeof(sgx_isvfamily_id_t));
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memcpy(&tmp_report.body.isv_ext_prod_id, &isv_ext_id->isv_ext_prod_id, sizeof(sgx_isvext_prod_id_t));
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memcpy(&tmp_report.body.config_id, &cur_secs->config_id, sizeof(sgx_config_id_t));
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memcpy(&tmp_report.body.attributes, &cur_secs->attributes, sizeof(sgx_attributes_t));
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memcpy(&tmp_report.body.report_data, rd, sizeof(sgx_report_data_t));
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memcpy(&tmp_report.body.mr_enclave, &cur_secs->mr_enclave, sizeof(sgx_measurement_t));
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memcpy(&tmp_report.body.mr_signer, &cur_secs->mr_signer, sizeof(sgx_measurement_t));
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memcpy(&tmp_report.key_id, get_base_key(SGX_KEYSELECT_REPORT), sizeof(sgx_key_id_t)/2);
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// derive the report key
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derivation_data_t dd;
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memset(&dd, 0, sizeof(dd));
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dd.size = sizeof(dd_report_key_t);
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dd.key_name = SGX_KEYSELECT_REPORT;
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memcpy(&dd.ddrk.mrenclave, &ti->mr_enclave, sizeof(sgx_measurement_t));
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memcpy(&dd.ddrk.attributes, &ti->attributes, sizeof(sgx_attributes_t));
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memcpy(dd.ddrk.csr_owner_epoch, SIMU_OWNER_EPOCH_MSR, sizeof(se_owner_epoch_t));
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memcpy(&dd.ddrk.cpu_svn,&(g_global_data_sim.cpusvn_sim),sizeof(sgx_cpu_svn_t));
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memcpy(&dd.ddrk.key_id, &tmp_report.key_id, sizeof(sgx_key_id_t));
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memcpy(&dd.ddrk.config_id, &ti->config_id, sizeof(sgx_config_id_t));
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dd.ddrk.config_svn = ti->config_svn;
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dd.ddrk.misc_select = ti->misc_select;
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|
|
|
// calculate the derived key
|
|
sgx_key_128bit_t tmp_report_key;
|
|
memset(tmp_report_key, 0, sizeof(tmp_report_key));
|
|
|
|
GP_ON(SGX_SUCCESS != derive_key(&dd, tmp_report_key));
|
|
|
|
// call cryptographic CMAC function
|
|
// CMAC data are *NOT* including MAC and KEYID
|
|
GP_ON(SGX_SUCCESS != cmac(&tmp_report_key, reinterpret_cast<uint8_t*>(&tmp_report.body),
|
|
sizeof(tmp_report.body), &tmp_report.mac));
|
|
|
|
memcpy(report, &tmp_report, sizeof(sgx_report_t));
|
|
}
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
|
|
static void
|
|
_EEXIT(uintptr_t dest, uintptr_t xcx, uintptr_t xdx, uintptr_t xsi, uintptr_t xdi) __attribute__((section(".nipx")));
|
|
|
|
// The call to load_regs assumes the existence of a frame pointer.
|
|
LOAD_REGS_ATTRIBUTES
|
|
static void
|
|
_EEXIT(uintptr_t dest, uintptr_t xcx, uintptr_t xdx, uintptr_t xsi, uintptr_t xdi)
|
|
{
|
|
// By simulator convention, XDX contains XBP and XCX contains XSP.
|
|
|
|
enclu_regs_t regs;
|
|
regs.xsp = xcx; // xcx = xsp = ssa.rsp_u
|
|
regs.xbp = xdx; // xdx = xbp = ssa.rbp_u
|
|
regs.xip = dest; // dest= xbx = xcx on EENTER = return address
|
|
// For the value of ssa.rsp_u, ssa.rbp_u, and return address, see _EENTER in u_instruction.cpp
|
|
|
|
tcs_t *tcs = GET_TCS_PTR(xdx);
|
|
GP_ON(tcs == NULL);
|
|
|
|
// restore the used _tls_array
|
|
GP_ON(td_mngr_restore_td(tcs) == false);
|
|
|
|
// check thread is in use or not
|
|
tcs_sim_t *tcs_sim = reinterpret_cast<tcs_sim_t *>(tcs->reserved);
|
|
|
|
size_t tcs_target_state = TCS_STATE_INACTIVE;
|
|
size_t tcs_current_state = TCS_STATE_INACTIVE;
|
|
__atomic_exchange(&tcs_sim->tcs_state, &tcs_target_state, &tcs_current_state, __ATOMIC_RELAXED);
|
|
GP_ON(tcs_current_state!= TCS_STATE_ACTIVE);
|
|
|
|
regs.xax = 0;
|
|
regs.xbx = dest;
|
|
regs.xcx = tcs_sim->saved_aep;
|
|
regs.xsi = xsi;
|
|
regs.xdi = xdi;
|
|
|
|
load_regs(®s);
|
|
|
|
// jump back to the instruction after the call to _SE3
|
|
// common/inc/internal/linux/linux-regs.h:
|
|
// call _SE3
|
|
// ---------------------------> jump here
|
|
// # ifdef LINUX32
|
|
// add $(SE_WORDSIZE * 6), %esp
|
|
// # endif
|
|
|
|
// Never returns.....
|
|
}
|
|
|
|
|
|
// Master entry functions
|
|
|
|
uintptr_t _SE3(uintptr_t xax, uintptr_t xbx, uintptr_t xcx,
|
|
uintptr_t xdx, uintptr_t xsi, uintptr_t xdi)
|
|
{
|
|
switch (xax)
|
|
{
|
|
case SE_EEXIT:
|
|
_EEXIT(xbx, xcx, xdx, xsi, xdi);
|
|
// never reach here
|
|
return 0;
|
|
|
|
case SE_EGETKEY:
|
|
return _EGETKEY(reinterpret_cast<sgx_key_request_t *>(xbx),
|
|
reinterpret_cast<uint8_t *>(xcx));
|
|
|
|
case SE_EREPORT:
|
|
_EREPORT(reinterpret_cast<sgx_target_info_t*>(xbx),
|
|
reinterpret_cast<sgx_report_data_t*>(xcx),
|
|
reinterpret_cast<sgx_report_t*>(xdx));
|
|
return 0;
|
|
}
|
|
|
|
GP();
|
|
return (uintptr_t)-1;
|
|
}
|