mirror of
https://github.com/intel/linux-sgx
synced 2026-06-08 14:49:32 +00:00
edfe42a517
Supported loading enclave at address 0. Upgraded Intel(R) Quote Verification Enclave to integrate SgxSSL/OpenSSL version 1.1.1k. Updated the DCAP driver V1.33 with stability fixes, released as V1.33.2. This is to support legacy solutions not ready to transition to the latest DCAP driver V1.41 or kernel 5.11+. Fixed bugs. Signed-off-by: Li, Xun <xun.li@intel.com>
267 lines
6.6 KiB
C++
267 lines
6.6 KiB
C++
/*
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* Copyright (C) 2011-2021 Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <string.h>
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#include "se_memory.h"
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#include "se_memcpy.h"
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#include "util.h"
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#include "enclave_mngr.h"
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#include "se_atomic.h"
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static uint32_t atomic_inc32(uint32_t volatile *val)
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{
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return se_atomic_inc(val);
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}
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uint32_t CEnclaveSim::m_counter = 1;
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void CEnclaveSim::set_image_offset(uint64_t image_offset)
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{
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m_image_offset = image_offset;
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}
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uint64_t CEnclaveSim::get_image_offset()
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{
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return m_image_offset;
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}
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sgx_enclave_id_t CEnclaveSim::gen_enclave_id(void)
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{
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//getpid() is to simulate fork() scenario, refer to do_ecall in sig_handler.cpp
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sgx_enclave_id_t id = ((uint64_t)getpid() << 32) | atomic_inc32(&m_counter);
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return id;
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}
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CEnclaveSim::CEnclaveSim(const secs_t* secs)
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{
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m_cpages = static_cast<size_t>(secs->size >> SE_PAGE_SHIFT);
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m_flags = new si_flags_t[m_cpages];
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// pages flags are initialized to -1
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memset(m_flags, 0xff, m_cpages * sizeof(si_flags_t));
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memcpy_s(&m_secs, sizeof(m_secs), secs, sizeof(*secs));
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m_enclave_id = gen_enclave_id();
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m_image_offset = 0;
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}
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CEnclaveSim::~CEnclaveSim()
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{
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delete[] m_flags;
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se_virtual_free(m_secs.base, (size_t)m_secs.size, MEM_RELEASE);
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}
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sgx_enclave_id_t CEnclaveSim::get_enclave_id() const
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{
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return m_enclave_id;
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}
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secs_t* CEnclaveSim::get_secs()
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{
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return &m_secs;
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}
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size_t CEnclaveSim::get_pg_idx(const void* pgaddr) const
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{
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return PTR_DIFF(pgaddr, m_secs.base) >> SE_PAGE_SHIFT;
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}
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bool CEnclaveSim::validate_pg_and_flags(const void* addr, si_flags_t flags)
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{
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// Must be page aligned
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if (!IS_PAGE_ALIGNED(addr))
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return false;
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size_t page_idx = get_pg_idx(addr);
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// Must be within enclave address space
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if (page_idx >= m_cpages)
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return false;
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// Requested flags should only set those visible by instuctions
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if ((flags & (~SI_FLAGS_EXTERNAL)))
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return false;
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return true;
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}
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bool CEnclaveSim::add_page(const void* addr, si_flags_t flags)
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{
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if (!validate_pg_and_flags(addr, flags))
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return false;
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// We only deal with these flags
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flags &= static_cast<si_flags_t>(SI_FLAGS_EXTERNAL);
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// Must not have been added yet
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size_t page_idx = get_pg_idx(addr);
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if (m_flags[page_idx] != (si_flags_t)-1)
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return false;
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m_flags[page_idx] = flags;
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return true;
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}
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bool CEnclaveSim::remove_page(const void* epc_lin_addr)
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{
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size_t page_idx = get_pg_idx(epc_lin_addr);
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if (m_flags[page_idx] != (si_flags_t)-1) {
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m_flags[page_idx] = (si_flags_t)-1;
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return true;
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}
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return false;
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}
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bool CEnclaveSim::is_tcs_page(const void* addr) const
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{
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// Must be page aligned
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if (!IS_PAGE_ALIGNED(addr))
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return false;
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size_t page_idx = get_pg_idx(addr);
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// Must be within enclave address space
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if (page_idx >= m_cpages)
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return false;
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return (m_flags[page_idx] & SI_FLAG_PT_MASK) == SI_FLAG_TCS;
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}
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//////////////////////////////////////////////////////////////////////
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CEnclaveMngr::CEnclaveMngr()
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{
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se_mutex_init(&m_list_lock);
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}
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CEnclaveMngr::~CEnclaveMngr()
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{
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se_mutex_destroy(&m_list_lock);
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std::list<CEnclaveSim*>::iterator it = m_enclave_list.begin();
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for (; it != m_enclave_list.end(); ++it)
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{
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delete (*it);
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}
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}
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// Note: this singleton implemenation is not multi-threading safe.
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CEnclaveMngr* CEnclaveMngr::get_instance()
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{
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static CEnclaveMngr mngr;
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return &mngr;
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}
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// Use constructor attribute to make sure that the later calling of
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// CEnclaveMngr::get_instance() is MT-safe.
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__attribute__ ((__constructor__)) static void build_mngr_instance()
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{
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CEnclaveMngr::get_instance();
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}
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void CEnclaveMngr::add(CEnclaveSim* ce)
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{
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if (ce != NULL)
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{
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se_mutex_lock(&m_list_lock);
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m_enclave_list.push_back(ce);
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se_mutex_unlock(&m_list_lock);
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}
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}
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void CEnclaveMngr::remove(CEnclaveSim* ce)
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{
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if (ce != NULL)
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{
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se_mutex_lock(&m_list_lock);
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m_enclave_list.remove(ce);
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se_mutex_unlock(&m_list_lock);
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}
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}
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CEnclaveSim* CEnclaveMngr::get_enclave(const sgx_enclave_id_t id)
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{
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CEnclaveSim* ce = NULL;
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se_mutex_lock(&m_list_lock);
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std::list<CEnclaveSim*>::iterator it = m_enclave_list.begin();
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for (; it != m_enclave_list.end(); ++it)
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{
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if ((*it)->get_enclave_id() == id)
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{
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ce = *it;
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break;
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}
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}
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se_mutex_unlock(&m_list_lock);
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return ce;
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}
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CEnclaveSim* CEnclaveMngr::get_enclave(const void* base_addr)
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{
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CEnclaveSim* ce = NULL;
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se_mutex_lock(&m_list_lock);
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std::list<CEnclaveSim*>::iterator it = m_enclave_list.begin();
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for (; it != m_enclave_list.end(); ++it)
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{
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secs_t* secs = (*it)->get_secs();
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if (base_addr >= secs->base &&
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PTR_DIFF(base_addr, secs->base) < secs->size)
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{
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ce = *it;
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break;
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}
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}
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se_mutex_unlock(&m_list_lock);
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return ce;
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}
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CEnclaveSim* CEnclaveMngr::get_enclave(const secs_t* secs)
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{
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// The pEnclaveSECS field might not have been initialized yet.
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return get_enclave(secs->base);
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}
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