mirror of
https://github.com/intel/linux-sgx
synced 2026-06-08 14:49:32 +00:00
c505e6129a
Added support for Reproducible Enclave Build using Docker file. Added support for Intel AVX-512 instructions and Intel SHA Extensions New Instructions (SHA-NI) in trusted libraries. Support both EPID and ECDSA based quote for quoting related interfaces in sgx_uae_service library. Updated key exchange library to support both EPID and ECDSA based remote attestation. Support new interface to check platform information blob from remote attestation response message. Fixed bugs. Signed-off-by: Li, Xun <xun.li@intel.com>
178 lines
3.8 KiB
C
178 lines
3.8 KiB
C
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#include <libunwind.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#include <altivec.h>
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#include <sys/resource.h>
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#define panic(args...) { fprintf (stderr, args); abort(); }
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extern vector signed int vec_init ();
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extern void vec_print (vector signed int v);
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vector signed int vec_stack (int count);
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int
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main ()
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{
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printf ("&vec_stack = %016lx\n", (unsigned long) vec_stack);
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vec_stack (3);
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return 0;
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}
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vector signed int
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vec_stack (int count)
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{
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register vector signed int v1;
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register vector signed int v2;
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register vector signed int v3;
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register vector signed int v4;
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register vector signed int v5;
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register vector signed int v6;
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register vector signed int v7;
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register vector signed int v8;
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register vector signed int v9;
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unw_fpreg_t vr;
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unw_cursor_t cursor;
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unw_word_t ip, sp;
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unw_context_t uc;
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int ret;
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int verbose = 1;
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/* if (count == 0) return vec_init(); */
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if (count == 0)
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{
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unw_getcontext (&uc);
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if (unw_init_local (&cursor, &uc) < 0)
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{
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panic ("unw_init_local failed!\n");
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}
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else
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{
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do
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{
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if ((ret = unw_get_reg (&cursor, UNW_REG_IP, &ip)) < 0)
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{
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panic ("FAILURE: unw_get_reg returned %d for UNW_REG_IP\n",
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ret);
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}
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if ((ret = unw_get_reg (&cursor, UNW_REG_SP, &sp)) < 0)
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{
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panic ("FAILURE: unw_get_reg returned %d for UNW_REG_SP\n",
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ret);
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}
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if ((ret = unw_get_fpreg (&cursor, UNW_PPC64_V30, &vr)) < 0)
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{
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panic
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("FAILURE: unw_get_vreg returned %d for UNW_PPC64_V30\n",
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ret);
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}
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if (verbose)
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{
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const char *regname = unw_regname (UNW_PPC64_V30);
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char proc_name_buffer[256];
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unw_word_t offset;
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unsigned int * vec_half1, * vec_half2;
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vec_half1 = (unsigned int *)&vr;
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vec_half2 = vec_half1 + 1;
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printf ("ip = %016lx, sp=%016lx\n", (long) ip, (long) sp);
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printf ("vr30 = %08x %08x %08x %08x\n",
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(unsigned int) (*vec_half1 >> 16),
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(unsigned int) (*vec_half1 & 0xffffffff),
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(unsigned int) (*vec_half2 >> 16),
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(unsigned int) (*vec_half2 & 0xffffffff));
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ret =
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unw_get_proc_name (&cursor, proc_name_buffer,
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sizeof (proc_name_buffer), &offset);
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if (ret == 0)
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{
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printf ("proc name = %s, offset = %lx\n",
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proc_name_buffer, offset);
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}
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else
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{
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panic ("unw_get_proc_name returned %d\n", ret);
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}
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printf ("unw_regname(UNW_PPC_V30) = %s\n\n", regname);
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}
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ret = unw_step (&cursor);
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if (ret < 0)
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{
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unw_get_reg (&cursor, UNW_REG_IP, &ip);
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panic ("FAILURE: unw_step() returned %d for ip=%lx\n", ret,
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(long) ip);
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}
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}
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while (ret > 0);
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}
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}
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v1 = vec_init ();
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v2 = vec_init ();
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v3 = vec_init ();
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v4 = vec_init ();
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v5 = vec_init ();
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v6 = vec_init ();
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/* make use of all of the registers in some calculation */
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v7 =
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vec_nor (v1, vec_add (v2, vec_sub (v3, vec_and (v4, vec_or (v5, v6)))));
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/*
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* "force" the registers to be non-volatile by making a call and also
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* using the registers after the call.
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*/
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v8 = vec_stack (count - 1);
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/*
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* Use the result from the previous call, plus all of the non-volatile
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* registers in another calculation.
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*/
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v9 =
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vec_nor (v1,
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vec_add (v2,
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vec_sub (v3,
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vec_and (v4, vec_or (v5, vec_xor (v6, v8))))));
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printf ("v1 - ");
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vec_print (v1);
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printf ("\n");
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printf ("v2 - ");
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vec_print (v2);
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printf ("\n");
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printf ("v3 - ");
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vec_print (v3);
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printf ("\n");
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printf ("v4 - ");
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vec_print (v4);
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printf ("\n");
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printf ("v5 - ");
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vec_print (v5);
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printf ("\n");
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printf ("v6 - ");
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vec_print (v6);
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printf ("\n");
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printf ("v7 - ");
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vec_print (v7);
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printf ("\n");
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printf ("v8 - ");
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vec_print (v8);
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printf ("\n");
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printf ("v9 - ");
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vec_print (v9);
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printf ("\n");
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return v9;
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}
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