mirror of
https://github.com/intelpt/WindowsIntelPT
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848f1280bd
- Fuilly implemented the experimental support for XSAVE
98 lines
4.6 KiB
C
98 lines
4.6 KiB
C
/**********************************************************************
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* Windows Intel Processor Trace (PT) Driver 0.4
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* Filename: KernelTracing.h
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* Defines data structures needed for Kernel Tracing
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* Last revision: 01/06/2016
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*
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* Copyright© 2016 Andrea Allievi, Richard Johnson
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* TALOS Research and Intelligence Group and Microsoft Ltd
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* All right reserved
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**********************************************************************/
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#pragma once
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#ifndef INTEL_PT_HDRS
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// Data structure that describe the trace type request
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struct PT_TRACE_DESC {
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PEPROCESS peProc; // Trace by CR3: The Process address space to trace (if any)
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BOOLEAN bTraceKernel; // Trace by CPL: TRUE to trace Kernel mode components
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BOOLEAN bTraceUser; // Trace by CPL: TRUE to trace User mode components
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DWORD dwNumOfRanges; // Trace by IP: Number of range to trace
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struct PT_TRACE_RANGE Ranges[4]; // Trace by IP: the VA ranges to trace
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};
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// The trace options Bitmask
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union TRACE_OPTIONS {
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struct {
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BOOLEAN bTraceCycPcks : 1; // [0] - Enables/disables CYC Packet (Cycle Count Packet - default is 0)
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BOOLEAN bTraceMtcPcks : 1; // [1] - Enables/disables MTC Packet (Wall-clock time packets - default is 0)
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BOOLEAN bTraceTscPcks : 1; // [2] - Enables/disables TSC Packet (Time Stamp packets - default is 0)
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BOOLEAN bTraceBranchPcks : 1; // [3] - Enables/disables COFI-based packets: FUP, TIP, TIP.PGE, TIP.PGD, TNT, MODE.Exec, MODE.TSX. (default is 1)
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BOOLEAN bUseTopa : 1; // [4] - Enable/disable the usage of Table of Physical Address (if available, default is 1)
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BOOLEAN bEnableRetCompression : 1; // [5] - Enables/disables RET compression (default is 1)
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BOOLEAN bInitialized : 1; // [6] - Set to 1 if this structure is initialized
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BOOLEAN Reserved : 1; // [7] - Reserved
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BYTE MTCFreq : 4; // [8:11] - MTC packet Frequency, which is based on the core crystal clock, or Always Running Timer (ART)
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BYTE CycThresh : 4; // [12:15] - CYC packet threshold. CYC packets will be sent with the first eligible packet after N cycles have passed since the last CYC packet
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BYTE PSBFreq : 4; // [16:19] - The frequency of PSB packets. PSB packet frequency is based on the number of Intel PT packet bytes output
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} Fields;
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DWORD All;
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};
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// The descriptor of the Tracing buffer
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typedef struct _PT_BUFFER_DESCRIPTOR {
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union {
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struct {
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LPVOID lpTraceBuffVa; // + 0x00 - Kernel VA Pointer to a contiguous memory buffer
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ULONG_PTR lpTraceBuffPhysAddr; // + 0x08 - The physical address of the contiguous memory buffer
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} Simple;
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struct {
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LPVOID lpTopaVa; // + 0x00 - Kernel VA pointer to the ToPA
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ULONG_PTR lpTopaPhysAddr; // + 0x08 - The Physical adress of the ToPA
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} ToPA;
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} u;
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BOOLEAN bUseTopa; // + 0x10 - TRUE if this processor uses ToPa
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BOOLEAN bDefaultPmiSet; // + 0x11 - TRUE if the default PMI is on
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BOOLEAN bBuffIsFull; // + 0x12 - TRUE if the ToPa or Simple buffer is full
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QWORD qwBuffSize; // + 0x18 - The physical buffer size
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PMDL pTraceMdl; // + 0x20 - The MDL used for mapping pages
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LPVOID lpKernelVa; // + 0x28 - The kernel-mode virtual address
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}PT_BUFFER_DESCRIPTOR, *PPT_BUFFER_DESCRIPTOR;
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// The custom PMI ISR routines
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typedef VOID(*INTELPT_PMI_HANDLER)(DWORD dwProcId, PT_BUFFER_DESCRIPTOR * ptBuffDesc);
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// Check the Intel Processor Trace support on this processor
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NTSTATUS IntelPtCheckCpuSupport(INTEL_PT_CAPABILITIES * lpPtCap);
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// Pause/Resume the Trace
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NTSTATUS IntelPtPauseResumeTrace(BOOLEAN bPause);
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// Free and destroy a Trace buffer
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NTSTATUS IntelPtFreeBuffer(PT_BUFFER_DESCRIPTOR * ptBuffDesc);
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#endif // !INTEL_PT_HDRS
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// Allocate the buffer needed for kernel tracing
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NTSTATUS IntelPtAllocBuffer(PPT_BUFFER_DESCRIPTOR * pBuffDesc, QWORD qwSize, BOOLEAN bUseTopa, BOOLEAN bSetStdPmi = TRUE);
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// Add a PMI interrupt for a page in the ToPA
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NTSTATUS IntelPtAddBufferPmi(PT_BUFFER_DESCRIPTOR * pBuffDesc, QWORD qwOffset);
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// Remove a PMI interrupt from a page in the ToPA
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NTSTATUS IntelPtRemoveBufferPmi(PT_BUFFER_DESCRIPTOR * pBuffDesc, QWORD qwOffset);
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// Start the Kernel tracing for current processor
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NTSTATUS IntelPtStartTracing(PT_TRACE_DESC traceDesc, PT_BUFFER_DESCRIPTOR * pBuffDesc);
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// Register a PMI handler for ALL processor
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NTSTATUS IntelPtRegisterPmiHandler(INTELPT_PMI_HANDLER pCustomPmiHandler);
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// Delete the previous registered Intel PT PMI handler routine
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NTSTATUS IntelPtRemovePmiHandler(INTELPT_PMI_HANDLER pCustomPmiHandler);
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// Set/Get the Trace options for current CPU
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NTSTATUS IntelPtSetOptions(TRACE_OPTIONS opts);
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TRACE_OPTIONS IntelPtGetOptions();
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// Stop the Tracing
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VOID IntelPtStopTrace();
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