Comment out subnormal (0x1) test inputs for fcvtzu/fcvtzs double-to-
64-bit-integer tests on AArch64. LLVM 22 misselects the SIMD form
(fcvtzu d,d) which drops FE_INEXACT on subnormal inputs.
Upstream: llvm/llvm-project#178603
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
- Enable C++20 on both Windows and Linux
- Remove unnecessary set_property calls to silence LOCATION warnings
- Replace duplicate -fPIC flags with INTERFACE_POSITION_INDEPENDENT_CODE
- Set FETCHCONTENT_BASE_DIR to speed up sleigh and ghidra-fork downloads/builds
- fixed: Does not match the generator used previously: Unix Makefiles,use ninja instead
* llvm 17 fix
* more instances
* more fixes
* add inline
* bump ci
* bump cxx common
* add 17 case
* bump xcode version
* macos 13
* xcode 15
* bump docker to llvm 17
* change actual matrix value
* opaque pointers are the default now
* actually remove the option
* debug size
* install tree
* fix install
* fix install?
* get tree after
* build dir?
* tree above
* accumulate
* bug?
* try to remove intermediate packaging
* fix opt
* only inline
* give up on function inlining
* llvm 17
* remove debug tasks
* Update scripts/build.sh
Co-authored-by: William Tan <1284324+Ninja3047@users.noreply.github.com>
* Revert "Update scripts/build.sh"
This reverts commit 6c727a539d.
* debug
* try clear out old build
* retest
* try to save more space
* up
* Clear space and don't use cxx-common docker image (#689)
* Clear space and don't use cxx-common docker image
* Run on all PRs
* Fix perms
* Remove some unnecessary apt commands
* Install LLVM version as root
* Allow writing to external target
* Build before running tests
* Install with sudo
* Simplify with container volume mounts
---------
Co-authored-by: William Tan <1284324+Ninja3047@users.noreply.github.com>
Co-authored-by: Eric Kilmer <eric.d.kilmer@gmail.com>
* Add skeleton for PPC
* Copyright notices
* Fill in some details for the PPC arch
* Start building a (wrong) PPC runtime
* Begin populating state structure
* First pass for EIS state structure
* Map registers to Sleigh register names
* More fixes
* add optional param
* Create handle unsupported and invalid instruction isels
* Correct typo
* Get a basic `remill-lift` invocation running without failure
* Fix capitalisation
* Set vle context reg
* Fix SleighDecoder signatures
* Set VLE context register in the Sleigh engine in addition to our
internal context reg mapping
* Capitalize reg names
* Add the flag registers for XER and CR
* Rename bitflag structures in PPC state
* PPC Sleigh patches (#643)
* Modified sleigh patch script to generate patches for multiple .sinc files
* update README with new examples of sleigh patch script invocation
* add ppc register definition
* add ppc sleigh patches
* fix issue with remill_insn_size definition
* regenerate sleigh patches for PPC
* update CMakeLists.txt to include PPC patches
* Add TEA signal as a register in the PPC state
* Uppercase the stack pointer register name
* Fix PPC instruction sizes
* initial PPC tests
* remove duplicate tests
* fix tests for e_stmvgprw/e_ldmvgprw
* add tests for loading/storing from special registers
* add tests with internal conditionals in pcode
* fix for pc reg and addr width not being the same... I suspect this issue is going to come up elsewhere
* add heuristic for flow from normal intrainstruction flow
* rework tests to allow testing for different sized registers
* add tests for overflow and record add
* fix bug with log printout
* add intrafunction control flow lifting
* handle edge case where there is no pcode op at the zero index
* Fix another inconsistency with mismatching address and PC reg size
* Allocate unique ptrs in the entry block
* Fix `INT_LEFT` and `INT_RIGHT` impl where shift exceeds bit width
* fix supiece lift?
* Add PPC emulate instruction to hyper call
* fix for pc reg and addr width not being the same... I suspect this issue is going to come up elsewhere
* add heuristic for flow from normal intrainstruction flow
* add intrafunction control flow lifting
* handle edge case where there is no pcode op at the zero index
* Fix another inconsistency with mismatching address and PC reg size
* fix supiece lift?
* Allocate unique ptrs in the entry block
* Fix `INT_LEFT` and `INT_RIGHT` impl where shift exceeds bit width
* fix int2float semantics
should use appropriate sized float based on the output size
* add tests for lifting int2float
* fix INT_{LEFT,RIGHT} semantics
should be `ICmpSGE` instead of `ICmpSGT`
* add cr0-7 registers
* fix formatting
* fix conditional branch test
* add test for compare
* re-enable rotate left word immediate and mask test
* genericize TestSpecOutput
* explicit instruction data size
* add test for syscall/callother (disabled)
* add tests for store/load word
* add test to convert from float to int
* specify intrinsic arg type, fixes null deref
* Add PPC emulate instruction to hyper call
* add headers + formatting
* remove old comment
* Map CRALL register
* Add basic LLVM data layout that specifies 32-bit addresses
* Remove unused variables
* convert auto* to auto when possible
* RegisterPrecondition -> RegisterCondition
* fix variable name
* convert any to variant
* use std::move
* bump to c++20, use concepts
* set arch in constructor since class isn't generic anyways
* formatting
* make type aliases
* bump cxx-common
* add comment
* clang format
* throw exception if register not found
* use const ref
* use shorthand for lambda capture values
* Add more detail to data layout to include proper stack alignment
* Compare to the correct size for SUBPIECE impl
* Add Sleigh message to error
* throw exception in else case
* throw runtime error if register value has incorrect type
* use reference instead of value
* get rid of unnecessary type alias
* formatting
* Propagate VLE context reg value into Sleigh
* Remove unnecessary whitespace
* Remove stale TODO and NOTE comments
* add additional parameter to test runner to specify decoding context
* drop llvm 14, bump macos version
* bump cxx-common, fix ci.yml mac build
* add test for unconditional relative negative branch
* add missing space to pcode debug log
* fix bug due to unordered_map, iteration order matters
* add error log in case we aren't able to adjust PC value
* use helper for getting register reference
* Revert "add optional param"
This reverts commit 51ed49f8cf.
* Remove remaining LLVM 14 compatibility code and configuration
* Add padding between CR and XER flags
* Use `enum class`
* Remove void cast
* Remove unnecessary variable
* Use initialiser lists where appropriate
* Remove redundant `else`
* Prefer `CHECK` over `assert`
* Polish PowerPC function initialisation with lambda
* zero out xer_so to fix tests
* log error when we see claim_eq with no usages
* Collapse namespace blocks
* Remove unnecessary `this->`
* Use `auto` where appropriate
* Remove unnecessary `else`
* Use `emplace` over `insert` for `std::map`
Co-authored-by: lkorenc <lukas.korencik@trailofbits.com>
* Use `constexpr` for VLE reg name
* Use module verification util
* Add `VerifyFunction` util and use where applicable
* Extract lambda to improve readability of flow categorisation
* Use type alias for context values
* Introduce type alias for block exit
* Create type alias for optional branch taken
* Refactor `PcodeCFGBuilder`
* Use lambda to avoid conditional mutation
* Extract duplicated bit-shift code generation into helper
* Simplify flow with ternary
* Add `GetBlock` helper
* Rename variables
* Move statement for clarity
* Create helpers for working with Sleigh context register values
* Convert loop to `std::copy`
* Add a comment explaining the use of set to de-duplicate and sort
* Refactor `IntraProcTransferCollector`
* Expose static method to easily use `IntraProcTransferCollector`
* Rename PPC related variables to include address width
* add docs to intrainstructionindex
* remove llvm 14 ifdefs
* don't log error if no claim_eqs were used
* update comments
* Cleanup exit visitors
---------
Co-authored-by: 2over12 <ian.smith@trailofbits.com>
Co-authored-by: William Tan <1284324+Ninja3047@users.noreply.github.com>
Co-authored-by: lkorenc <lukas.korencik@trailofbits.com>
* Get Remill building with LLVM 15
* Add missing header for x86 lift test
* Fix `enableOpaquePointers` calls
* Define a non-extern `__remill_state` in each Instructions module
* Remove `__remill_state` variables in tests
* Update build script to support LLVM 15
* Build with LLVM 15 in CI
* Bump CXX Common version
* Update Docker script
* Add comment explaining the definition of the state variable
* Correct wording
* Create initial implementation of `__remill_sync_hyper_call`
* Fill in a few more cases
* Use `state.addr_to_load` for LGDT and LIDT operands
* Fix variable names
* Cross-compile the Remill runtimes
* Create temp variable for `lgdt` and `lidt` handling
* Add intrinsics for SPARC emulate instruction calls
* Create intrinsics for remaining hyper calls
* Remove `__remill_sync_hyper_call` implementations in tests
* Create the target triple based on the provided arch
* Provide ARCH parameter for SPARC archs
* CMake formatting
* Switch the conditions around
* Adjust target triple
* Cross-compile the hyper calls and then link them into the runtime
* Cleanup
* Prefix int types with namespace
* Include `<limits>`
* Fix `lgdt` and `lidt` handling
* Mark new intrinsics as "used"
* Add placeholder intrinsic definitions to tests
* Complete list of intrinsic definitions
* Mark hyper call definition with `always_inline`
* Use `_BitInt` if available
* Use `__builtin_unreachable` instead of `abort`
* Leave comment explaining `always_inline` attribute
* add lifter field
* arch has intrinsics
* use insn lifter in trace lifter
* limit default lifters to ops only
* init lifters
* pass arch in tests
* fix bug in swap
* stop using archbase decode in sleigh arches
* This branch contains support for new architectures.
* Initial start to support for AArch 32
* Progress
* Forgot the new files
* Added all data Integer processing instructions without S + ADDS and started ANDS
* Updated
* Finished Integer Data Processing with three registers, added integer data processing with 2 regs + immediate, started MUL instructions
* UMULL, UMULLS, UMLAL, UMLALS
* Corrected condition for addend or 0 immediate for UMULL/UMLAL + SMULL/SMLAL instructions
* Correct ops in Binary.cpp
* UMAAL
* SMULL, SMULLS, SMLAL, SMLALS + corrected acc was missing shift left in concatination
* Updated decoding instructions based on top level encodings
* Update returns around kDataProcessingRI and kDataProcessingI with comments to explain the correlation to the instruction rep
* Added appropriate inst.category flags to Multiply and accumulate
* Load/Store Word, Unsigned Byte (immediate, literal) && start of Logical Arithmetic (three register, immediate shift)
* Was missing UMAAL DEF_ISEL in Binary.cpp
* AddAddrRegOp
* Logical Arithmetic (three register, immediate shift) without accounting for the possible PC jump
* Made DecodeA32ExpandImm much much smaller
* Replaced some imm ops with AddImmOp calls
* Created AddShiftOp
* Added interpreter for evaluating new PC value at decoding time to handle direct jumps and conditional jumps
* Created EvalPCDest added PC evaluation to Logical Arithmetic Instructions
* AddShiftOp -> AddShiftOp, AddShiftThenExtractOp, AddExtractThenShiftOp
* Cleaned up some formatting, Renamed DecodeA32ExpandImm to ExpandTo32AddImmAddCarry and added a clarifying comment
* Added comment to EvalPCDest for clarity
* Cleaned up some things, updated the decoding semantics and semantics for the logical instructions
* Shortened kLogArithEvaluators and fixed a bug
* Updates from testing instructions
* Fixed DEF_ISEL for pre/post index instructions in MEM.cpp
* Integer Test and Compare (two register, immediate shift)
* Logical Arithmetic (two register and immediate)
* Integer Test and Compare (one register and immediate)
* Added to the top level encoding infrastructure to handle the Data-processing register (register shift) set of instructions and 3 corresponding subsets
* Add structs for the 3 subsets of Data-processing register (register shift)
* Code status before refactoring operand types
* This branch contains support for new architectures.
* Initial start to support for AArch 32
* Progress
* Forgot the new files
* Added all data Integer processing instructions without S + ADDS and started ANDS
* Updated
* Finished Integer Data Processing with three registers, added integer data processing with 2 regs + immediate, started MUL instructions
* UMULL, UMULLS, UMLAL, UMLALS
* Corrected condition for addend or 0 immediate for UMULL/UMLAL + SMULL/SMLAL instructions
* Correct ops in Binary.cpp
* UMAAL
* SMULL, SMULLS, SMLAL, SMLALS + corrected acc was missing shift left in concatination
* Updated decoding instructions based on top level encodings
* Update returns around kDataProcessingRI and kDataProcessingI with comments to explain the correlation to the instruction rep
* Added appropriate inst.category flags to Multiply and accumulate
* Load/Store Word, Unsigned Byte (immediate, literal) && start of Logical Arithmetic (three register, immediate shift)
* Was missing UMAAL DEF_ISEL in Binary.cpp
* AddAddrRegOp
* Logical Arithmetic (three register, immediate shift) without accounting for the possible PC jump
* Made DecodeA32ExpandImm much much smaller
* Replaced some imm ops with AddImmOp calls
* Created AddShiftOp
* Added interpreter for evaluating new PC value at decoding time to handle direct jumps and conditional jumps
* Created EvalPCDest added PC evaluation to Logical Arithmetic Instructions
* AddShiftOp -> AddShiftOp, AddShiftThenExtractOp, AddExtractThenShiftOp
* Cleaned up some formatting, Renamed DecodeA32ExpandImm to ExpandTo32AddImmAddCarry and added a clarifying comment
* Added comment to EvalPCDest for clarity
* Cleaned up some things, updated the decoding semantics and semantics for the logical instructions
* Shortened kLogArithEvaluators and fixed a bug
* Updates from testing instructions
* Fixed DEF_ISEL for pre/post index instructions in MEM.cpp
* Integer Test and Compare (two register, immediate shift)
* Logical Arithmetic (two register and immediate)
* Integer Test and Compare (one register and immediate)
* Added to the top level encoding infrastructure to handle the Data-processing register (register shift) set of instructions and 3 corresponding subsets
* Add structs for the 3 subsets of Data-processing register (register shift)
* Code status before refactoring operand types
* Finished updates off master
* Start of operand refactor
* Finished Expression Operand Support
* Fix the .gitignore to add AArch32 to lib/Arch && removed all extra rrx ops from semantics
* Updated .gitignore again, Added AddShiftRegRegOperand, Updated AddShiftRegImmOperand, Finished Register shift instructions for Integer Test and Compare, Logical Arithmetic, Integer Data Processing
* Updated ROR in AddShiftRegRegOperand
* Created ExtractAndZExtExpr
* Fixed comment formatting in if else statements
* Created RORExpr
* Small fixes
* Small fix in Logical Arithmetic (two register and immediate)
* Corrected AddShiftRegRegOperand and cleaned it up. Split the carry op into a separate function.
* conditional support + Start of Branch instructions
* Created AddExprOp, cleaned up some expressions in reg shifted reg, and updated some occurances of ShiftThenExtractOp with ExtractAndZExtExpr
* Updates from testing register shifted by register value inst
* Fix to ROR in AddShiftRegCarryOperand
* Corrected negation in DecodeCondition
* DecodeCondition edit
* DecodeCondition and AddShiftRegCarryOperand edits
* Updated arch_for_decode to arch
* Halfword Multiply and Accumulate
* Edits from testing Halfword Multiply and Accumulate
* Changed order of operands in Halfword Multiply and Accumulate to better reflect inst format + updated inst errors
* Branch (Imm) & BX/BXL
* Update aarch32 cmake
* cmake update
* CLZ
* Forgot BITBYTE.cpp
* MOVT
* Integer Saturating Arithmetic
* updated semantics in SMLAWh & SMLAh to use Select for setting PSTATE.Q
* Started Load/Store Word, Unsigned Byte (register) & fixed MOV halfword
* Load/Store Word, Unsigned Byte (register)
* Finished testing load/Store Word, Unsigned Byte (register)
* Load/Store Dual, Half, Signed Byte (register)
* Rest of Extra load store: Load/Store Dual, Half, Signed Byte (immediate, literal)
* Finished testing all the Load/store additions
* Signed multiply, Divide
* Cleaned up SExt some
* Saturate Insts and Start of Load Store Multiple - STMDB and LDM (aliases which support PUSH and POP of multiple regs)
* Condensed args in STMDB and LDM semantics
* Rest of Multiple Load/Store that do not execute in a different mode
* Bitfield Extract
* Extend and Add
* fix
* NOP
* Small fix
* Simplified the bit reps in TryMoveSpecialRegisterAndHintsI
* Moved Bitfield extract semantics out of BINARY and into BITBYTE
* Finished correcting S/ZExt and Trunc use
* Ran scripts/format-files to format
* Smoke Test
* Add false delay slot to kCategoryConditionalDirectFunctionCall
* CI: Use single packaging job, add changelog support (#491)
* CI: Add tag handler (#492)
* Delay slot fixes to TraceLifter
Co-authored-by: Peter Goodman <peter.goodman@gmail.com>
Co-authored-by: Alessandro Gario <5714290+alessandrogario@users.noreply.github.com>
* New x86 instructions
* Add some isels
* Fixes Issue #376
* Fixes Issue #433. Thanks @adahsuzixin for the semantics and tests
* Fixes Issue #374
* Minor fix to the semantics for VINSERTF128, it should only look at the low bit of imm8
* Minor fixes for sparc isel naming
* Running clang-format on files with some additional custom scripts for my style
* Fix missing unique_ptr in remill/BC/Optimizer.h
* Fixes and selective disabling of clang-format
* General API improvements
* Minor changes
* New name for existing isel
* Error compatibility with llvm8
* llvm 10 to build script
Co-authored-by: kumarak <iit.akshay@gmail.com>
* Use std::unique_ptr to manage llvm::Module after it is loaded.
* Remove calls from Util that are internally dependent on global flags.
In reality they only save a few characters for API users and eventually
this kind of code can lead to tightly coupled code with global state.
* Remove code duplication.
* Reflect API change in tests.
* CMake: Make the bitcode generator Visual Studio friendly
* CMake: Always recompile the runtimes when the semantics change
* CMake: Style changes
* CMake: Fix missing variable when re-configuring
* CMake: Windows/Visual Studio fixes
* Windows: Add missing FPU macros
* Fix alignment issues with Visual Studio
* CMake: Fix the install target for Windows
* CMake: Add support for find_package(remill)
* Build script: Use verbose makefile
* CMake: Add missing ADDRESS_SIZE_BITS in BC compiler
* CMake: X86 Tests project refactor
* Windows: Port of BC/Utils and OS/FileSystem
* CMake: Update settings.cmake
* CMake: Generate the semantics path in remillConfig.cmake
* CMake: Only use C++14 when compiling on Windows
* Rename FPUFlags to Float and collect all FPU flags there
* Travis: Add macOS, test all LLVM versions, add clang static analyzer
* Travis: Disable LLVM50 tests, include verbose output for failed tests
* CMake: Update the find_package handler, add support for fcd headers
* Dead store elimination (draft) (#257)
* Add initial prototying of DeadStoreEliminator
* Improve upon DeadStoreEliminator prototype
Update `DeadStoreEliminator` prototyping with additional comments and
proper function prototype return values.
Fix a small warning in `Lifter.h` by adding `llvm::Value` and
`llvm::BasicBlock`.
* Add initial code for DeadStoreEliminator
Provide namespaced `remill::StateSlots` function which visits fields of
the module's state struct and returns `StateSlot` objects.
Remove `comment` field as the `State` object (an `llvm::StructType`)
does not track names in a useful way.
* Update state analyzer and fix type errors
Update `DeadStoreEliminator.cpp` to properly produce a vector of
`StateSlot`s without type errors (i.e. it compiles).
Code still needed for other container types besides structs.
* Add remill::VisitSequential for arrays and vectors
Add state analyzer code for LLVM's `ArrayType` and `VectorType`.
Add debugging use of `llvm::Type::dump()`.
Consider refactoring as a `StateVisitor` class.
* Begin refactor of Visit funcs to StateVisitor
* Fix segfault in StateVisitor::visit, code style
* Prototype ForwardAliasVisitor for alias analysis
Add code for ForwardAliasVisitor subclass of `llvm::InstVisitor`,
to be used for performing alias analysis of lifted functions.
* Add non-working visit functions for alias analysis
* Fix compilation of alias analysis visit funcs
* Change ForwardAliasVisitor to RetTy=bool
Update ForwardAliasVisitor to use booleans for return types to track
when we should add the instruction to the next_wl.
Add code to simplify StateSlots for vecs of ints.
* Add progress tracking to AliasAnalysis
* Correct progress tracker, use BasicBlockFunction()
* Change ForwardAliasAnalysis<RetTy = AliasResult>
Get some of those sweet sweet enums in there!
* Add FAV state pointer field, PHINode impl
* Allow non-const add and sub in FAV
Allow add and sub instructions with two pointers in the offset map.
Add to implementation of visitPHINode.
* Update PHINode impl in FAV
* Clean up use of StateSlots to create AAMDNodes
Add code to create AAMDNodes from StateSlot elements.
Change creation of StateSlot vector to have elements for every
byte offset of the state structure for fast indexing.
* Complete addition of AAMDNodes for load and store
Move function defs up for AAMDNode ops.
Add AliasMap typedef.
Finish generateAAMDNodesFromSlots.
* Add GenerateLiveSet func
* Initialize live set, add AAMDNodes to stores
* Change LiveSet creation to a block visitor class
* Add to_remove set to LSBV
* Update build script to use os-release for OS detection
* Update DSE code to conform to pag's review
* Refactor LiveSetBlockVisitor to one LiveSet per block
* Update VisitBlock to better check instruction type
* Fix VisitBlock CallInst and InvokeInst cases
* Stack allocate AAMDInfo in AnalyzeAliases
* Add remove pass option for VisitBlock
* Add DOT digraph generation
* Fix bugs in dot digraph
* Fix various bugs in AAMDNodes and LSBV
Move AAMDNodes functions later to match their use.
Clean up code conventions.
Fix small bugs in various spots in the code.
* Fix various function prototypes, overflow checks
* Merge AliasMap and OffsetMap
* Change add/sub insts to be safer
Add OpType enum class to replace use of `plus` bool.
Add more straightforward bounds checking on AddInst or SubInst values.
* Refactor GetUnsignedOffset style
* Fix illegal instruction error
* Add offset checking for GEP, provide log messages
Write a log message for the cases where `GetUnsignedOffset` returns
false (indicating an overflow or underflow).
* Fix APInt initialization in VisitGEP
* Re-add dead store elimination and alias map
* Move LSBV into alias analysis, expand callinst
Expand definition of cases where a CallInst should be considered to
touch the state struct or otherwise revive a slot.
* Improve DOT creation, fix errors for callinsts
Fix small errors in LiveSetBlockVisitor::CallAccessesState.
Clean up DOT digraph generation further.
* Clean up code per @pag's comments
* Clean up code, add selectinst, fix compile errors
Deal with a few small corner cases with FAV Load and Store instructions,
add SelectInst visitor.
Inline MarkLiveArgs to avoid the complications of C++ generics.
* Clean up logging
* More changes to please Peter
Clean up select and PHI node cases to improve circular dependency
handling.
* Correct errors in visitSelect
* Add load forwarding code
* Add code to run FBV
* Fix map usage error in FBV
* Add call, invoke cases for FBV
* Here are the changes whoops
* Minor API change
* Minor tweaks to DOT digraph printing, as well as attempts to handle the case where the forward analysis pass is incomplete. Still don't have it guarantee completion on everything, but seems 'good enough' for now.
* Change log level
* Fix compile errors due to messy merge
* Pag dead store (#262)
* Fix to script calling wrong function.
* Makes sure that value names are preserved (#249)
* Adds LLVM_VERSION() to accomodate llvm::LLVMContext::setDiscardValueNames() in <3.9 (#250)
* Makes sure that value names are preserved
* Adds LLVM_VERSION() macros to accomodate
* Update README.md
* Update README.md
* set state and memory as noalias (#254)
* Implements some ring 0 instructions in terms of hyper calls and new I/O port intrinsics. (#252)
* Random tests.
* More decode error info
* more playing around
* more system instructions. instrinsics for accessing I/O ports. Split our writes to individual control regs for better identification via hyper calls.
* CR8 read/write support (#255)
* Check argument index of function (#256)
* Fix NoAlias Attributes for older LLVM versions
* Fix for LLVM 4.0 and 3.9
* Fix typo
* Follow remill coding style
* Here are the changes whoops
* Minor API change
* Minor tweaks to DOT digraph printing, as well as attempts to handle the case where the forward analysis pass is incomplete. Still don't have it guarantee completion on everything, but seems 'good enough' for now.
* Change log level
* Fix compile errors due to messy merge
* Improve call/invoke case of FBV
* Improve call/invoke case of FBV
* Removes a level of indirection in the __remill_basic_block function
* Create dedicated stats tracker
Plus clean up the FBV visitor a teensy bit more.
* Move call/invoke LiveSet gen to static func
This commit is to pave the way for future improvements to where this
information is calculated (in FAV instead of LSBV).
* Add code to FAV for calls and invokes
Move call and invoke arg-based livesets to FAV to allow for module-level
LSBV code.
* Begin change of LSBV to module-level
* Minor bug fixes
* Remove some dead code
* Begin adding more code for call/invoke LSBV
* Add entry block checks for LSBV call/invoke
* Info about register names, as well as printing them in the digraphs.
* Make DOT printing only happen per function, as opposed to printing every function per DOT file. Minor tweaks to interprocedural analysis.
* Bug fixes and DOT printing improvements.
* Bug fixes and DOT printing improvements.
* Also print out DOT digraphs of functions after removing stuff
* Tried to make it treat everything before a call to __remill_error as dead but that didn't work out.
* Use datalayout and type sizes to handle the number of elements in a sequential type for LLVM 3.8 compatibility, also check for pointer type.
* More stats, hopefully fixes a bitcast issue.
* Minor bug fixes, and more DOT printing to help diagnose when the offset analysis terminates but there is still stuff in the work list.
* Some possible bug fixes
* Minor bug fix
* Travis build fixes for earlier compatibility
* Fix for LLVM less than 3.8 compatibility.
* LLVM 3.5 compatibility
* Missing condition in forwarding code that does casting.
* LLVM 5.0 compatibility
* Add LLVM 6.0 to build.sh. Change default install location to /usr/local
* Add back in vmill. Add some extra flags to the building runtimes.
* Maybe works
* Disable dse across indirect call (#267)
* Make DSE sensitive to indirect function calls
* FE_DENORM issue
* Added some compat code that implements the futimens syscall on mac os 10.12 for travis support.
* Disable dse across indirect call (#268)
* Make DSE sensitive to indirect function calls
* FE_DENORM issue
* Added some compat code that implements the futimens syscall on mac os 10.12 for travis support.
* Playing with CACHE and PARENT_SCOPE
* Minor stack address size check
* Fix to DSE I think.
* Minor DSE tweak
* Update Run.cpp
* Update travis.sh
Adds in 32-bit libraries for Linux builds.
* Random tests.
* More decode error info
* more playing around
* more system instructions. instrinsics for accessing I/O ports. Split our writes to individual control regs for better identification via hyper calls.
* Implemented USHR_ASISDSHF_R
Also includes prototype decoder for USHR_ASIMDSHF_R, but no semantic implementation
* Fixed missing newline and replaced trailing spaces
* Implemented USHR_ASISDSHF_R
Also includes prototype decoder for USHR_ASIMDSHF_R, but no semantic implementation
* Fixed missing newline and replaced trailing spaces
* Fixed copy paste errors in reserved value check
* Working on getting LD3 right before moving onto LD4.
* Forgot to remove this extra definition
* Semantics and tests for one variant of LD3 and LD4
* Forgot to implement LD4 tests...
* Minor fixes
* Another dumb fix
* Re-enable all aarch64 tests.
* WIP implemented MSR FSPR <Xn> insn, one test case not passing
* MSR_SR_SYSTEM_FPSR insn implemented, with test
* MRS_RS_SYSTEM_FPCR and MSR_SR_SYSTEM_FPCR insns implemented, with tests
* MSR_SR_SYSTEM_TPIDR_EL0 and MRS_RS_SYSTEM_TPIDR_EL0 insn implemented, with test
* Semantics and tests for LDXR_LR32_LDSTEXCL and LDXR_LR64_LDSTEXCL.
* Whoops!
* Initial semantics and tests form MOVI_ASMINDIMM_D2_D.
* IPR
* Semantics and tests for STLXR. Semantics but no tests for MOVI and MVNI variants.
* Tests for MVNI and MOVI.
* Addition of a new MONITOR pseudo-register to try to handle load-linked, store-conditional. It's a bit of a stop-gap for now.
* Minor fix.
* Updating tests
* Semantics and tests for LDXR_LR32_LDSTEXCL and LDXR_LR64_LDSTEXCL.
* Whoops!
* Initial semantics and tests form MOVI_ASMINDIMM_D2_D.
* IPR
* Semantics and tests for STLXR. Semantics but no tests for MOVI and MVNI variants.
* Tests for MVNI and MOVI.
* Addition of a new MONITOR pseudo-register to try to handle load-linked, store-conditional. It's a bit of a stop-gap for now.
* Minor fix.
* LDURSB_32_LDST_UNSCALED insn implemented, with test
* LDURSH_32_LDST_UNSCALED insn implemented, with test
* LDURSW_64_LDST_UNSCALED insn implemented, with test
* LDPSW_64_LDSTPAIR_OFF insn implemented, with test
* NOP_HI_SYSTEM insn implemented
* EON_64_LOG_SHIFT insn implemented, with test
* BSL_ASIMDSAME_ONLY insn implmented, with test
* STLR_SL32_LDSTEXCL insn implemented, with test
* stlr has proper memory access semantics
* LDPSW_64_LDSTPAIR_PRE, LDPSW_64_LDSTPAIR_POST, and EON_32_LOG_SHIFT insn implemented, with tests
kyle-elliott-tob