* Removes some deprecated functions, and removes the basic block function cloning apis, in favor of apis on Arch
* More tweaks for removing unnecessary APIs
* Goodbye dse
* Fix issue
* Tweaks
* Remove some annoying logs
* Adds missing arch identification from triples. Adds sub-arch identifications. Adds x86 decoding logic for fusing calls that target the next instruction, and when the next instruction is a return
* Bug fix on call-ret fusing
* Bug fix on call-ret fusing
* Address PR feedback
* Address PR feedback
* Add 64-bit fusing support. Minor bug fix
* Add 64-bit fusing support. Minor bug fix
* Adds missing arch identification from triples. Adds sub-arch identifications. Adds x86 decoding logic for fusing calls that target the next instruction, and when the next instruction is a return
* Bug fix on call-ret fusing
* Bug fix on call-ret fusing
* Address PR feedback
* Address PR feedback
* Added branch_taken_pc and branch_not_taken_pc
* Corrected comment
* Added t system reg flag. Still need to check inst.category
* Fixed inst.category in TryDecodeBX
* This branch contains support for new architectures.
* Initial start to support for AArch 32
* Progress
* Forgot the new files
* Added all data Integer processing instructions without S + ADDS and started ANDS
* Updated
* Finished Integer Data Processing with three registers, added integer data processing with 2 regs + immediate, started MUL instructions
* UMULL, UMULLS, UMLAL, UMLALS
* Corrected condition for addend or 0 immediate for UMULL/UMLAL + SMULL/SMLAL instructions
* Correct ops in Binary.cpp
* UMAAL
* SMULL, SMULLS, SMLAL, SMLALS + corrected acc was missing shift left in concatination
* Updated decoding instructions based on top level encodings
* Update returns around kDataProcessingRI and kDataProcessingI with comments to explain the correlation to the instruction rep
* Added appropriate inst.category flags to Multiply and accumulate
* Load/Store Word, Unsigned Byte (immediate, literal) && start of Logical Arithmetic (three register, immediate shift)
* Was missing UMAAL DEF_ISEL in Binary.cpp
* AddAddrRegOp
* Logical Arithmetic (three register, immediate shift) without accounting for the possible PC jump
* Made DecodeA32ExpandImm much much smaller
* Replaced some imm ops with AddImmOp calls
* Created AddShiftOp
* Added interpreter for evaluating new PC value at decoding time to handle direct jumps and conditional jumps
* Created EvalPCDest added PC evaluation to Logical Arithmetic Instructions
* AddShiftOp -> AddShiftOp, AddShiftThenExtractOp, AddExtractThenShiftOp
* Cleaned up some formatting, Renamed DecodeA32ExpandImm to ExpandTo32AddImmAddCarry and added a clarifying comment
* Added comment to EvalPCDest for clarity
* Cleaned up some things, updated the decoding semantics and semantics for the logical instructions
* Shortened kLogArithEvaluators and fixed a bug
* Updates from testing instructions
* Fixed DEF_ISEL for pre/post index instructions in MEM.cpp
* Integer Test and Compare (two register, immediate shift)
* Logical Arithmetic (two register and immediate)
* Integer Test and Compare (one register and immediate)
* Added to the top level encoding infrastructure to handle the Data-processing register (register shift) set of instructions and 3 corresponding subsets
* Add structs for the 3 subsets of Data-processing register (register shift)
* Code status before refactoring operand types
* This branch contains support for new architectures.
* Initial start to support for AArch 32
* Progress
* Forgot the new files
* Added all data Integer processing instructions without S + ADDS and started ANDS
* Updated
* Finished Integer Data Processing with three registers, added integer data processing with 2 regs + immediate, started MUL instructions
* UMULL, UMULLS, UMLAL, UMLALS
* Corrected condition for addend or 0 immediate for UMULL/UMLAL + SMULL/SMLAL instructions
* Correct ops in Binary.cpp
* UMAAL
* SMULL, SMULLS, SMLAL, SMLALS + corrected acc was missing shift left in concatination
* Updated decoding instructions based on top level encodings
* Update returns around kDataProcessingRI and kDataProcessingI with comments to explain the correlation to the instruction rep
* Added appropriate inst.category flags to Multiply and accumulate
* Load/Store Word, Unsigned Byte (immediate, literal) && start of Logical Arithmetic (three register, immediate shift)
* Was missing UMAAL DEF_ISEL in Binary.cpp
* AddAddrRegOp
* Logical Arithmetic (three register, immediate shift) without accounting for the possible PC jump
* Made DecodeA32ExpandImm much much smaller
* Replaced some imm ops with AddImmOp calls
* Created AddShiftOp
* Added interpreter for evaluating new PC value at decoding time to handle direct jumps and conditional jumps
* Created EvalPCDest added PC evaluation to Logical Arithmetic Instructions
* AddShiftOp -> AddShiftOp, AddShiftThenExtractOp, AddExtractThenShiftOp
* Cleaned up some formatting, Renamed DecodeA32ExpandImm to ExpandTo32AddImmAddCarry and added a clarifying comment
* Added comment to EvalPCDest for clarity
* Cleaned up some things, updated the decoding semantics and semantics for the logical instructions
* Shortened kLogArithEvaluators and fixed a bug
* Updates from testing instructions
* Fixed DEF_ISEL for pre/post index instructions in MEM.cpp
* Integer Test and Compare (two register, immediate shift)
* Logical Arithmetic (two register and immediate)
* Integer Test and Compare (one register and immediate)
* Added to the top level encoding infrastructure to handle the Data-processing register (register shift) set of instructions and 3 corresponding subsets
* Add structs for the 3 subsets of Data-processing register (register shift)
* Code status before refactoring operand types
* Finished updates off master
* Start of operand refactor
* Finished Expression Operand Support
* Fix the .gitignore to add AArch32 to lib/Arch && removed all extra rrx ops from semantics
* Updated .gitignore again, Added AddShiftRegRegOperand, Updated AddShiftRegImmOperand, Finished Register shift instructions for Integer Test and Compare, Logical Arithmetic, Integer Data Processing
* Updated ROR in AddShiftRegRegOperand
* Created ExtractAndZExtExpr
* Fixed comment formatting in if else statements
* Created RORExpr
* Small fixes
* Small fix in Logical Arithmetic (two register and immediate)
* Corrected AddShiftRegRegOperand and cleaned it up. Split the carry op into a separate function.
* conditional support + Start of Branch instructions
* Created AddExprOp, cleaned up some expressions in reg shifted reg, and updated some occurances of ShiftThenExtractOp with ExtractAndZExtExpr
* Updates from testing register shifted by register value inst
* Fix to ROR in AddShiftRegCarryOperand
* Corrected negation in DecodeCondition
* DecodeCondition edit
* DecodeCondition and AddShiftRegCarryOperand edits
* Updated arch_for_decode to arch
* Halfword Multiply and Accumulate
* Edits from testing Halfword Multiply and Accumulate
* Changed order of operands in Halfword Multiply and Accumulate to better reflect inst format + updated inst errors
* Branch (Imm) & BX/BXL
* Update aarch32 cmake
* cmake update
* CLZ
* Forgot BITBYTE.cpp
* MOVT
* Integer Saturating Arithmetic
* updated semantics in SMLAWh & SMLAh to use Select for setting PSTATE.Q
* Started Load/Store Word, Unsigned Byte (register) & fixed MOV halfword
* Load/Store Word, Unsigned Byte (register)
* Finished testing load/Store Word, Unsigned Byte (register)
* Load/Store Dual, Half, Signed Byte (register)
* Rest of Extra load store: Load/Store Dual, Half, Signed Byte (immediate, literal)
* Finished testing all the Load/store additions
* Signed multiply, Divide
* Cleaned up SExt some
* Saturate Insts and Start of Load Store Multiple - STMDB and LDM (aliases which support PUSH and POP of multiple regs)
* Condensed args in STMDB and LDM semantics
* Rest of Multiple Load/Store that do not execute in a different mode
* Bitfield Extract
* Extend and Add
* fix
* NOP
* Small fix
* Simplified the bit reps in TryMoveSpecialRegisterAndHintsI
* Moved Bitfield extract semantics out of BINARY and into BITBYTE
* Finished correcting S/ZExt and Trunc use
* Ran scripts/format-files to format
* Smoke Test
* Add false delay slot to kCategoryConditionalDirectFunctionCall
* CI: Use single packaging job, add changelog support (#491)
* CI: Add tag handler (#492)
* Delay slot fixes to TraceLifter
Co-authored-by: Peter Goodman <peter.goodman@gmail.com>
Co-authored-by: Alessandro Gario <5714290+alessandrogario@users.noreply.github.com>
* bc: Use llvm::CallSite methods instead of raw llvm instructions.
* bc: Use llvm::CallSite in utils.
* bc: Add compatibility file for CallSite.
* bc: Reflect addition of compat for CallSite.
* New x86 instructions
* Add some isels
* Fixes Issue #376
* Fixes Issue #433. Thanks @adahsuzixin for the semantics and tests
* Fixes Issue #374
* Minor fix to the semantics for VINSERTF128, it should only look at the low bit of imm8
* Minor fixes for sparc isel naming
* Refactors the code to improve directory layout, use more std::string_view in place of std::string, deletes some deprecated functions, deprecates some other functions for eventual deletion, and includes semantics for sparcv8 (sparc32) and sparcv9 (sparc64)
* Update new dir layout with llvm 11 support
* Whoops missing files
* Drop llvm 800 from workflow
* Minor fix
* Move where the install directives are in CMake
* Minor fixes
* Rename tools/ to bin/.
* Minor tweaks
* Should fix issues
sschriner