mirror of
https://github.com/lifting-bits/remill
synced 2026-06-21 13:56:07 +00:00
Matteo
545 lines
19 KiB
C++
545 lines
19 KiB
C++
#include <glog/logging.h>
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#include <remill/Arch/Name.h>
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#include <remill/Arch/X86/X86Base.h>
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#include <remill/BC/ABI.h>
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#include <remill/BC/Util.h>
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#include <remill/OS/OS.h>
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namespace remill {
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static const std::string_view kSPNames[] = {"RSP", "ESP"};
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static const std::string_view kPCNames[] = {"RIP", "EIP"};
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// Returns the name of the stack pointer register.
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std::string_view X86ArchBase::StackPointerRegisterName(void) const {
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return kSPNames[IsX86()];
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}
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// Returns the name of the program counter register.
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std::string_view X86ArchBase::ProgramCounterRegisterName(void) const {
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return kPCNames[IsX86()];
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}
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uint64_t X86ArchBase::MinInstructionAlign(const DecodingContext &) const {
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return 1;
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}
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uint64_t X86ArchBase::MinInstructionSize(const DecodingContext &) const {
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return 1;
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}
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uint64_t X86ArchBase::MaxInstructionSize(const DecodingContext &, bool) const {
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return 15;
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}
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llvm::CallingConv::ID X86ArchBase::DefaultCallingConv(void) const {
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if (IsX86()) {
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switch (os_name) {
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case kOSInvalid:
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case kOSmacOS:
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case kOSLinux:
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case kOSWindows:
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case kOSSolaris: return llvm::CallingConv::C; // cdecl.
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}
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} else {
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switch (os_name) {
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case kOSInvalid:
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case kOSmacOS:
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case kOSLinux:
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case kOSSolaris: return llvm::CallingConv::X86_64_SysV;
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case kOSWindows: return llvm::CallingConv::Win64;
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}
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}
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}
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llvm::Triple X86ArchBase::Triple(void) const {
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auto triple = BasicTriple();
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switch (arch_name) {
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case kArchAMD64:
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case kArchAMD64_AVX:
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case kArchAMD64_AVX512:
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case kArchAMD64_SLEIGH: triple.setArch(llvm::Triple::x86_64); break;
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case kArchX86:
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case kArchX86_AVX:
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case kArchX86_AVX512:
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case kArchX86_SLEIGH: triple.setArch(llvm::Triple::x86); break;
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default:
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LOG(FATAL) << "Cannot get triple for non-x86 architecture "
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<< GetArchName(arch_name);
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}
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return triple;
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}
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llvm::DataLayout X86ArchBase::DataLayout(void) const {
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std::string dl;
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switch (os_name) {
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case kOSInvalid:
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LOG(FATAL) << "Cannot convert module for an unrecognized OS.";
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break;
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case kOSLinux:
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case kOSSolaris: // Probably.
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switch (arch_name) {
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case kArchAMD64:
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case kArchAMD64_AVX:
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case kArchAMD64_AVX512:
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case kArchAMD64_SLEIGH:
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dl = "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
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break;
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case kArchX86:
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case kArchX86_AVX:
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case kArchX86_AVX512:
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case kArchX86_SLEIGH:
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dl = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
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break;
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default:
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LOG(FATAL) << "Cannot get data layout non-x86 architecture "
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<< GetArchName(arch_name);
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break;
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}
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break;
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case kOSmacOS:
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switch (arch_name) {
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case kArchAMD64:
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case kArchAMD64_AVX:
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case kArchAMD64_AVX512:
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case kArchAMD64_SLEIGH:
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dl = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
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break;
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case kArchX86:
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case kArchX86_AVX:
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case kArchX86_AVX512:
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case kArchX86_SLEIGH:
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dl = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
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break;
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default:
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LOG(FATAL) << "Cannot get data layout for non-x86 architecture "
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<< GetArchName(arch_name);
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}
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break;
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case kOSWindows:
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switch (arch_name) {
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case kArchAMD64:
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case kArchAMD64_AVX:
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case kArchAMD64_AVX512:
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case kArchAMD64_SLEIGH:
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dl = "e-m:w-i64:64-f80:128-n8:16:32:64-S128";
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break;
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case kArchX86:
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case kArchX86_AVX:
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case kArchX86_AVX512:
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case kArchX86_SLEIGH:
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dl = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
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break;
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default:
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LOG(FATAL) << "Cannot get data layout for non-x86 architecture "
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<< GetArchName(arch_name);
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}
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break;
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}
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return llvm::DataLayout(dl);
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}
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void X86ArchBase::PopulateRegisterTable(void) const {
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reg_by_offset.resize(sizeof(X86State));
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CHECK_NOTNULL(context);
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bool has_avx = false;
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bool has_avx512 = false;
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switch (arch_name) {
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case kArchX86_AVX:
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case kArchAMD64_AVX: has_avx = true; break;
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case kArchX86_AVX512:
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case kArchAMD64_AVX512:
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has_avx = true;
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has_avx512 = true;
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break;
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default: break;
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}
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auto u8 = llvm::Type::getInt8Ty(*context);
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auto u16 = llvm::Type::getInt16Ty(*context);
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auto u32 = llvm::Type::getInt32Ty(*context);
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auto u64 = llvm::Type::getInt64Ty(*context);
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auto f80 = llvm::Type::getX86_FP80Ty(*context);
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auto v128 = llvm::ArrayType::get(llvm::Type::getInt8Ty(*context), 128u / 8u);
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auto v256 = llvm::ArrayType::get(llvm::Type::getInt8Ty(*context), 256u / 8u);
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auto v512 = llvm::ArrayType::get(llvm::Type::getInt8Ty(*context), 512u / 8u);
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auto addr = llvm::Type::getIntNTy(*context, address_size);
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#define OFFSET_OF(state, access) \
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(reinterpret_cast<uintptr_t>(&state.access) \
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- reinterpret_cast<uintptr_t>(&state))
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#define REG(state, name, access, type) \
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AddRegister(#name, type, OFFSET_OF(state, access), nullptr)
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#define SUB_REG(state, name, access, type, parent_reg_name) \
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AddRegister(#name, type, OFFSET_OF(state, access), #parent_reg_name)
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#define SUB_REG64(state, name, access, type, parent_reg_name) \
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if (64 == address_size) { \
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SUB_REG(state, name, access, type, parent_reg_name); \
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} else { \
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REG(state, name, access, type); \
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}
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#define SUB_REGAVX512(state, name, access, type, parent_reg_name) \
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if (has_avx512) { \
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SUB_REG(state, name, access, type, parent_reg_name); \
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} else { \
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REG(state, name, access, type); \
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}
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#define SUB_REGAVX(state, name, access, type, parent_reg_name) \
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if (has_avx) { \
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SUB_REG(state, name, access, type, parent_reg_name); \
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} else { \
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REG(state, name, access, type); \
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}
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X86State state;
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if (64 == address_size) {
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REG(state, RAX, gpr.rax.qword, u64);
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REG(state, RBX, gpr.rbx.qword, u64);
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REG(state, RCX, gpr.rcx.qword, u64);
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REG(state, RDX, gpr.rdx.qword, u64);
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REG(state, RSI, gpr.rsi.qword, u64);
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REG(state, RDI, gpr.rdi.qword, u64);
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REG(state, RSP, gpr.rsp.qword, u64);
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REG(state, RBP, gpr.rbp.qword, u64);
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REG(state, RIP, gpr.rip.qword, u64);
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REG(state, R8, gpr.r8.qword, u64);
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REG(state, R9, gpr.r9.qword, u64);
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REG(state, R10, gpr.r10.qword, u64);
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REG(state, R11, gpr.r11.qword, u64);
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REG(state, R12, gpr.r12.qword, u64);
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REG(state, R13, gpr.r13.qword, u64);
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REG(state, R14, gpr.r14.qword, u64);
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REG(state, R15, gpr.r15.qword, u64);
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SUB_REG(state, R8D, gpr.r8.dword, u32, R8);
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SUB_REG(state, R9D, gpr.r9.dword, u32, R9);
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SUB_REG(state, R10D, gpr.r10.dword, u32, R10);
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SUB_REG(state, R11D, gpr.r11.dword, u32, R11);
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SUB_REG(state, R12D, gpr.r12.dword, u32, R12);
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SUB_REG(state, R13D, gpr.r13.dword, u32, R13);
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SUB_REG(state, R14D, gpr.r14.dword, u32, R14);
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SUB_REG(state, R15D, gpr.r15.dword, u32, R15);
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SUB_REG(state, R8W, gpr.r8.word, u16, R8D);
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SUB_REG(state, R9W, gpr.r9.word, u16, R9D);
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SUB_REG(state, R10W, gpr.r10.word, u16, R10D);
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SUB_REG(state, R11W, gpr.r11.word, u16, R11D);
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SUB_REG(state, R12W, gpr.r12.word, u16, R12D);
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SUB_REG(state, R13W, gpr.r13.word, u16, R13D);
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SUB_REG(state, R14W, gpr.r14.word, u16, R14D);
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SUB_REG(state, R15W, gpr.r15.word, u16, R15D);
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}
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SUB_REG64(state, EAX, gpr.rax.dword, u32, RAX);
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SUB_REG64(state, EBX, gpr.rbx.dword, u32, RBX);
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SUB_REG64(state, ECX, gpr.rcx.dword, u32, RCX);
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SUB_REG64(state, EDX, gpr.rdx.dword, u32, RDX);
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SUB_REG64(state, ESI, gpr.rsi.dword, u32, RSI);
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SUB_REG64(state, EDI, gpr.rdi.dword, u32, RDI);
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SUB_REG64(state, ESP, gpr.rsp.dword, u32, RSP);
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SUB_REG64(state, EBP, gpr.rbp.dword, u32, RBP);
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SUB_REG64(state, EIP, gpr.rip.dword, u32, RIP);
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SUB_REG(state, AX, gpr.rax.word, u16, EAX);
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SUB_REG(state, BX, gpr.rbx.word, u16, EBX);
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SUB_REG(state, CX, gpr.rcx.word, u16, ECX);
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SUB_REG(state, DX, gpr.rdx.word, u16, EDX);
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SUB_REG(state, SI, gpr.rsi.word, u16, ESI);
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SUB_REG(state, DI, gpr.rdi.word, u16, EDI);
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SUB_REG(state, SP, gpr.rsp.word, u16, ESP);
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SUB_REG(state, BP, gpr.rbp.word, u16, EBP);
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SUB_REG(state, IP, gpr.rip.word, u16, EIP);
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SUB_REG(state, AH, gpr.rax.byte.high, u8, AX);
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SUB_REG(state, BH, gpr.rbx.byte.high, u8, BX);
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SUB_REG(state, CH, gpr.rcx.byte.high, u8, CX);
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SUB_REG(state, DH, gpr.rdx.byte.high, u8, DX);
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SUB_REG(state, AL, gpr.rax.byte.low, u8, AX);
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SUB_REG(state, BL, gpr.rbx.byte.low, u8, BX);
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SUB_REG(state, CL, gpr.rcx.byte.low, u8, CX);
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SUB_REG(state, DL, gpr.rdx.byte.low, u8, DX);
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if (64 == address_size) {
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SUB_REG(state, SIL, gpr.rsi.byte.low, u8, SI);
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SUB_REG(state, DIL, gpr.rdi.byte.low, u8, DI);
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SUB_REG(state, SPL, gpr.rsp.byte.low, u8, SP);
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SUB_REG(state, BPL, gpr.rbp.byte.low, u8, BP);
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SUB_REG(state, R8B, gpr.r8.byte.low, u8, R8W);
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SUB_REG(state, R9B, gpr.r9.byte.low, u8, R9W);
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SUB_REG(state, R10B, gpr.r10.byte.low, u8, R10W);
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SUB_REG(state, R11B, gpr.r11.byte.low, u8, R11W);
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SUB_REG(state, R12B, gpr.r12.byte.low, u8, R12W);
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SUB_REG(state, R13B, gpr.r13.byte.low, u8, R13W);
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SUB_REG(state, R14B, gpr.r14.byte.low, u8, R14W);
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SUB_REG(state, R15B, gpr.r15.byte.low, u8, R15W);
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}
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if (64 == address_size) {
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SUB_REG(state, PC, gpr.rip.qword, u64, RIP);
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} else {
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SUB_REG(state, PC, gpr.rip.dword, u32, EIP);
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}
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REG(state, SS, seg.ss.flat, u16);
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REG(state, ES, seg.es.flat, u16);
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REG(state, GS, seg.gs.flat, u16);
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REG(state, FS, seg.fs.flat, u16);
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REG(state, DS, seg.ds.flat, u16);
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REG(state, CS, seg.cs.flat, u16);
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if (64 == address_size) {
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REG(state, GSBASE, addr.gs_base.qword, addr);
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REG(state, FSBASE, addr.fs_base.qword, addr);
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} else {
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REG(state, CSBASE, addr.cs_base.dword, addr);
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REG(state, SSBASE, addr.ss_base.dword, addr);
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REG(state, ESBASE, addr.es_base.dword, addr);
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REG(state, DSBASE, addr.ds_base.dword, addr);
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REG(state, GSBASE, addr.gs_base.dword, addr);
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REG(state, FSBASE, addr.fs_base.dword, addr);
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}
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if (has_avx) {
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if (has_avx512) {
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REG(state, ZMM0, vec[0].zmm, v512);
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REG(state, ZMM1, vec[1].zmm, v512);
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REG(state, ZMM2, vec[2].zmm, v512);
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REG(state, ZMM3, vec[3].zmm, v512);
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REG(state, ZMM4, vec[4].zmm, v512);
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REG(state, ZMM5, vec[5].zmm, v512);
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REG(state, ZMM6, vec[6].zmm, v512);
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REG(state, ZMM7, vec[7].zmm, v512);
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REG(state, ZMM8, vec[8].zmm, v512);
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REG(state, ZMM9, vec[9].zmm, v512);
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REG(state, ZMM10, vec[10].zmm, v512);
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REG(state, ZMM11, vec[11].zmm, v512);
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REG(state, ZMM12, vec[12].zmm, v512);
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REG(state, ZMM13, vec[13].zmm, v512);
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REG(state, ZMM14, vec[14].zmm, v512);
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REG(state, ZMM15, vec[15].zmm, v512);
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REG(state, ZMM16, vec[16].zmm, v512);
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REG(state, ZMM17, vec[17].zmm, v512);
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REG(state, ZMM18, vec[18].zmm, v512);
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REG(state, ZMM19, vec[19].zmm, v512);
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REG(state, ZMM20, vec[20].zmm, v512);
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REG(state, ZMM21, vec[21].zmm, v512);
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REG(state, ZMM22, vec[22].zmm, v512);
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REG(state, ZMM23, vec[23].zmm, v512);
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REG(state, ZMM24, vec[24].zmm, v512);
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REG(state, ZMM25, vec[25].zmm, v512);
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REG(state, ZMM26, vec[26].zmm, v512);
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REG(state, ZMM27, vec[27].zmm, v512);
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REG(state, ZMM28, vec[28].zmm, v512);
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REG(state, ZMM29, vec[29].zmm, v512);
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REG(state, ZMM30, vec[30].zmm, v512);
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REG(state, ZMM31, vec[31].zmm, v512);
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}
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SUB_REGAVX512(state, YMM0, vec[0].ymm, v256, ZMM0);
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SUB_REGAVX512(state, YMM1, vec[1].ymm, v256, ZMM1);
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SUB_REGAVX512(state, YMM2, vec[2].ymm, v256, ZMM2);
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SUB_REGAVX512(state, YMM3, vec[3].ymm, v256, ZMM3);
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SUB_REGAVX512(state, YMM4, vec[4].ymm, v256, ZMM4);
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SUB_REGAVX512(state, YMM5, vec[5].ymm, v256, ZMM5);
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SUB_REGAVX512(state, YMM6, vec[6].ymm, v256, ZMM6);
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SUB_REGAVX512(state, YMM7, vec[7].ymm, v256, ZMM7);
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if (64 == address_size || has_avx512) {
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SUB_REGAVX512(state, YMM8, vec[8].ymm, v256, ZMM8);
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SUB_REGAVX512(state, YMM9, vec[9].ymm, v256, ZMM9);
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SUB_REGAVX512(state, YMM10, vec[10].ymm, v256, ZMM10);
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SUB_REGAVX512(state, YMM11, vec[11].ymm, v256, ZMM11);
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SUB_REGAVX512(state, YMM12, vec[12].ymm, v256, ZMM12);
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SUB_REGAVX512(state, YMM13, vec[13].ymm, v256, ZMM13);
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SUB_REGAVX512(state, YMM14, vec[14].ymm, v256, ZMM14);
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SUB_REGAVX512(state, YMM15, vec[15].ymm, v256, ZMM15);
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}
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if (has_avx512) {
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SUB_REGAVX512(state, YMM16, vec[16].ymm, v256, ZMM16);
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SUB_REGAVX512(state, YMM17, vec[17].ymm, v256, ZMM17);
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SUB_REGAVX512(state, YMM18, vec[18].ymm, v256, ZMM18);
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SUB_REGAVX512(state, YMM19, vec[19].ymm, v256, ZMM19);
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SUB_REGAVX512(state, YMM20, vec[20].ymm, v256, ZMM20);
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SUB_REGAVX512(state, YMM21, vec[21].ymm, v256, ZMM21);
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SUB_REGAVX512(state, YMM22, vec[22].ymm, v256, ZMM22);
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SUB_REGAVX512(state, YMM23, vec[23].ymm, v256, ZMM23);
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SUB_REGAVX512(state, YMM24, vec[24].ymm, v256, ZMM24);
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SUB_REGAVX512(state, YMM25, vec[25].ymm, v256, ZMM25);
|
|
SUB_REGAVX512(state, YMM26, vec[26].ymm, v256, ZMM26);
|
|
SUB_REGAVX512(state, YMM27, vec[27].ymm, v256, ZMM27);
|
|
SUB_REGAVX512(state, YMM28, vec[28].ymm, v256, ZMM28);
|
|
SUB_REGAVX512(state, YMM29, vec[29].ymm, v256, ZMM29);
|
|
SUB_REGAVX512(state, YMM30, vec[30].ymm, v256, ZMM30);
|
|
SUB_REGAVX512(state, YMM31, vec[31].ymm, v256, ZMM31);
|
|
}
|
|
}
|
|
|
|
SUB_REGAVX(state, XMM0, vec[0].xmm, v128, YMM0);
|
|
SUB_REGAVX(state, XMM1, vec[1].xmm, v128, YMM1);
|
|
SUB_REGAVX(state, XMM2, vec[2].xmm, v128, YMM2);
|
|
SUB_REGAVX(state, XMM3, vec[3].xmm, v128, YMM3);
|
|
SUB_REGAVX(state, XMM4, vec[4].xmm, v128, YMM4);
|
|
SUB_REGAVX(state, XMM5, vec[5].xmm, v128, YMM5);
|
|
SUB_REGAVX(state, XMM6, vec[6].xmm, v128, YMM6);
|
|
SUB_REGAVX(state, XMM7, vec[7].xmm, v128, YMM7);
|
|
|
|
if (has_avx || 64 == address_size) {
|
|
SUB_REGAVX(state, XMM8, vec[8].xmm, v128, YMM8);
|
|
SUB_REGAVX(state, XMM9, vec[9].xmm, v128, YMM9);
|
|
SUB_REGAVX(state, XMM10, vec[10].xmm, v128, YMM10);
|
|
SUB_REGAVX(state, XMM11, vec[11].xmm, v128, YMM11);
|
|
SUB_REGAVX(state, XMM12, vec[12].xmm, v128, YMM12);
|
|
SUB_REGAVX(state, XMM13, vec[13].xmm, v128, YMM13);
|
|
SUB_REGAVX(state, XMM14, vec[14].xmm, v128, YMM14);
|
|
SUB_REGAVX(state, XMM15, vec[15].xmm, v128, YMM15);
|
|
}
|
|
|
|
if (has_avx512) {
|
|
SUB_REG(state, XMM16, vec[16].xmm, v128, YMM16);
|
|
SUB_REG(state, XMM17, vec[17].xmm, v128, YMM17);
|
|
SUB_REG(state, XMM18, vec[18].xmm, v128, YMM18);
|
|
SUB_REG(state, XMM19, vec[19].xmm, v128, YMM19);
|
|
SUB_REG(state, XMM20, vec[20].xmm, v128, YMM20);
|
|
SUB_REG(state, XMM21, vec[21].xmm, v128, YMM21);
|
|
SUB_REG(state, XMM22, vec[22].xmm, v128, YMM22);
|
|
SUB_REG(state, XMM23, vec[23].xmm, v128, YMM23);
|
|
SUB_REG(state, XMM24, vec[24].xmm, v128, YMM24);
|
|
SUB_REG(state, XMM25, vec[25].xmm, v128, YMM25);
|
|
SUB_REG(state, XMM26, vec[26].xmm, v128, YMM26);
|
|
SUB_REG(state, XMM27, vec[27].xmm, v128, YMM27);
|
|
SUB_REG(state, XMM28, vec[28].xmm, v128, YMM28);
|
|
SUB_REG(state, XMM29, vec[29].xmm, v128, YMM29);
|
|
SUB_REG(state, XMM30, vec[30].xmm, v128, YMM30);
|
|
SUB_REG(state, XMM31, vec[31].xmm, v128, YMM31);
|
|
}
|
|
|
|
REG(state, ST0, st.elems[0].val, f80);
|
|
REG(state, ST1, st.elems[1].val, f80);
|
|
REG(state, ST2, st.elems[2].val, f80);
|
|
REG(state, ST3, st.elems[3].val, f80);
|
|
REG(state, ST4, st.elems[4].val, f80);
|
|
REG(state, ST5, st.elems[5].val, f80);
|
|
REG(state, ST6, st.elems[6].val, f80);
|
|
REG(state, ST7, st.elems[7].val, f80);
|
|
|
|
#if 0 // TODO(pag): Don't emulate directly for now.
|
|
if (32 == address_size) {
|
|
REG(FPU_LASTIP, fpu.u.x86.ip);
|
|
REG(FPU_LASTIP, fpu.u.x86.ip);
|
|
REG(FPU_LASTCS, fpu.u.x86.cs);
|
|
REG(FPU_LASTCS, fpu.u.x86.cs);
|
|
REG(FPU_LASTDP, fpu.u.x86.dp);
|
|
REG(FPU_LASTDP, fpu.u.x86.dp);
|
|
REG(FPU_LASTDS, fpu.u.x86.ds);
|
|
REG(FPU_LASTDS, fpu.u.x86.ds);
|
|
} else {
|
|
REG(FPU_LASTIP, fpu.u.amd64.ip);
|
|
REG(FPU_LASTIP, fpu.u.amd64.ip);
|
|
REG(FPU_LASTDP, fpu.u.amd64.dp);
|
|
REG(FPU_LASTDP, fpu.u.amd64.dp);
|
|
}
|
|
#endif
|
|
|
|
// MMX technology registers. For simplicity, these are implemented separately
|
|
// from the FPU stack, and so they do not alias. This makes some things
|
|
// easier and some things harder. Marshaling native/lifted state becomes
|
|
// harder, but generating and optimizing bitcode becomes simpler. The trade-
|
|
// off is that analysis and native states will diverge in strange ways
|
|
// with code that mixes the two (X87 FPU ops, MMX ops).
|
|
REG(state, MM0, mmx.elems[0].val.qwords.elems[0], u64);
|
|
REG(state, MM1, mmx.elems[1].val.qwords.elems[0], u64);
|
|
REG(state, MM2, mmx.elems[2].val.qwords.elems[0], u64);
|
|
REG(state, MM3, mmx.elems[3].val.qwords.elems[0], u64);
|
|
REG(state, MM4, mmx.elems[4].val.qwords.elems[0], u64);
|
|
REG(state, MM5, mmx.elems[5].val.qwords.elems[0], u64);
|
|
REG(state, MM6, mmx.elems[6].val.qwords.elems[0], u64);
|
|
REG(state, MM7, mmx.elems[7].val.qwords.elems[0], u64);
|
|
|
|
if (has_avx512) {
|
|
REG(state, K0, k_reg.elems[0].val, u64);
|
|
REG(state, K1, k_reg.elems[1].val, u64);
|
|
REG(state, K2, k_reg.elems[2].val, u64);
|
|
REG(state, K3, k_reg.elems[3].val, u64);
|
|
REG(state, K4, k_reg.elems[4].val, u64);
|
|
REG(state, K5, k_reg.elems[5].val, u64);
|
|
REG(state, K6, k_reg.elems[6].val, u64);
|
|
REG(state, K7, k_reg.elems[7].val, u64);
|
|
}
|
|
|
|
// Arithmetic flags. Data-flow analyses will clear these out ;-)
|
|
REG(state, AF, aflag.af, u8);
|
|
REG(state, CF, aflag.cf, u8);
|
|
REG(state, DF, aflag.df, u8);
|
|
REG(state, OF, aflag.of, u8);
|
|
REG(state, PF, aflag.pf, u8);
|
|
REG(state, SF, aflag.sf, u8);
|
|
REG(state, ZF, aflag.zf, u8);
|
|
|
|
// // Debug registers. No-ops keep them from being stripped off the module.
|
|
// DR0
|
|
// DR1
|
|
// DR2
|
|
// DR3
|
|
// DR4
|
|
// DR5
|
|
// DR6
|
|
// DR7
|
|
|
|
// REG(CR0, lat);
|
|
// REG(CR1, lat);
|
|
// REG(CR2, lat);
|
|
// REG(CR3, lat);
|
|
// REG(CR4, lat);
|
|
//#if 64 == ADDRESS_SIZE_BITS
|
|
// REG(CR8, lat);
|
|
//#endif
|
|
}
|
|
|
|
// Populate a just-initialized lifted function function with architecture-
|
|
// specific variables.
|
|
void X86ArchBase::FinishLiftedFunctionInitialization(
|
|
llvm::Module *module, llvm::Function *bb_func) const {
|
|
const auto &dl = module->getDataLayout();
|
|
CHECK_EQ(sizeof(State), dl.getTypeAllocSize(StateStructType()))
|
|
<< "Mismatch between size of State type for x86/amd64 and what is in "
|
|
<< "the bitcode module";
|
|
|
|
auto &context = module->getContext();
|
|
auto addr = llvm::Type::getIntNTy(context, address_size);
|
|
auto zero_addr_val = llvm::Constant::getNullValue(addr);
|
|
|
|
const auto entry_block = &bb_func->getEntryBlock();
|
|
llvm::IRBuilder<> ir(entry_block);
|
|
|
|
const auto pc_arg = NthArgument(bb_func, kPCArgNum);
|
|
const auto state_ptr_arg = NthArgument(bb_func, kStatePointerArgNum);
|
|
ir.CreateStore(pc_arg, ir.CreateAlloca(addr, nullptr, "NEXT_PC"));
|
|
|
|
(void) this->RegisterByName("PC")->AddressOf(state_ptr_arg, ir);
|
|
|
|
if (64 == address_size) {
|
|
ir.CreateStore(zero_addr_val, ir.CreateAlloca(addr, nullptr, "CSBASE"));
|
|
ir.CreateStore(zero_addr_val, ir.CreateAlloca(addr, nullptr, "SSBASE"));
|
|
ir.CreateStore(zero_addr_val, ir.CreateAlloca(addr, nullptr, "ESBASE"));
|
|
ir.CreateStore(zero_addr_val, ir.CreateAlloca(addr, nullptr, "DSBASE"));
|
|
}
|
|
}
|
|
} // namespace remill
|