mirror of
https://github.com/lifting-bits/remill
synced 2026-06-21 13:56:07 +00:00
Peter Goodman
3808e9951d
* Refactors the code to improve directory layout, use more std::string_view in place of std::string, deletes some deprecated functions, deprecates some other functions for eventual deletion, and includes semantics for sparcv8 (sparc32) and sparcv9 (sparc64) * Update new dir layout with llvm 11 support * Whoops missing files * Drop llvm 800 from workflow * Minor fix * Move where the install directives are in CMake * Minor fixes * Rename tools/ to bin/. * Minor tweaks * Should fix issues
164 lines
4.6 KiB
C++
164 lines
4.6 KiB
C++
/*
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* Copyright (c) 2017 Trail of Bits, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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namespace {
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template <typename D, typename S1, typename S2>
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DEF_SEM(ORN, D dst, S1 src1, S2 src2) {
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WriteZExt(dst, UOr(Read(src1), UNot(Read(src2))));
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return memory;
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}
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template <typename D, typename S1, typename S2>
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DEF_SEM(EOR, D dst, S1 src1, S2 src2) {
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WriteZExt(dst, UXor(Read(src1), Read(src2)));
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return memory;
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}
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template <typename D, typename S1, typename S2>
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DEF_SEM(EON, D dst, S1 src1, S2 src2) {
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WriteZExt(dst, UXor(Read(src1), UNot(Read(src2))));
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return memory;
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}
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template <typename D, typename S1, typename S2>
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DEF_SEM(AND, D dst, S1 src1, S2 src2) {
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WriteZExt(dst, UAnd(Read(src1), Read(src2)));
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return memory;
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}
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template <typename D, typename S1, typename S2>
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DEF_SEM(ORR, D dst, S1 src1, S2 src2) {
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WriteZExt(dst, UOr(Read(src1), Read(src2)));
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return memory;
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}
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template <typename D, typename S1, typename S2>
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DEF_SEM(BIC, D dst, S1 src1, S2 src2) {
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WriteZExt(dst, UAnd(Read(src1), UNot(Read(src2))));
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return memory;
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}
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template <typename D, typename S1, typename S2>
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DEF_SEM(BICS, D dst, S1 src1, S2 src2) {
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auto res = UAnd(Read(src1), UNot(Read(src2)));
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WriteZExt(dst, res);
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FLAG_N = SignFlag(res);
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FLAG_Z = ZeroFlag(res);
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FLAG_C = false;
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FLAG_V = false;
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return memory;
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}
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} // namespace
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DEF_ISEL(ORN_32_LOG_SHIFT) = ORN<R32W, R32, I32>;
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DEF_ISEL(ORN_64_LOG_SHIFT) = ORN<R64W, R64, I64>;
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DEF_ISEL(EOR_32_LOG_SHIFT) = EOR<R32W, R32, I32>;
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DEF_ISEL(EOR_64_LOG_SHIFT) = EOR<R64W, R64, I64>;
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DEF_ISEL(EOR_32_LOG_IMM) = EOR<R32W, R32, I32>;
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DEF_ISEL(EOR_64_LOG_IMM) = EOR<R64W, R64, I64>;
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DEF_ISEL(EON_32_LOG_SHIFT) = EON<R32W, R32, I32>;
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DEF_ISEL(EON_64_LOG_SHIFT) = EON<R64W, R64, I64>;
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DEF_ISEL(AND_32_LOG_SHIFT) = AND<R32W, R32, I32>;
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DEF_ISEL(AND_64_LOG_SHIFT) = AND<R64W, R64, I64>;
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DEF_ISEL(AND_32_LOG_IMM) = AND<R32W, R32, I32>;
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DEF_ISEL(AND_64_LOG_IMM) = AND<R64W, R64, I64>;
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DEF_ISEL(ORR_32_LOG_SHIFT) = ORR<R32W, R32, I32>;
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DEF_ISEL(ORR_64_LOG_SHIFT) = ORR<R64W, R64, I64>;
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DEF_ISEL(ORR_32_LOG_IMM) = ORR<R32W, R32, I32>;
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DEF_ISEL(ORR_64_LOG_IMM) = ORR<R64W, R64, I64>;
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DEF_ISEL(BIC_32_LOG_SHIFT) = BIC<R32W, R32, I32>;
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DEF_ISEL(BIC_64_LOG_SHIFT) = BIC<R64W, R64, I64>;
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DEF_ISEL(BICS_32_LOG_SHIFT) = BICS<R32W, R32, I32>;
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DEF_ISEL(BICS_64_LOG_SHIFT) = BICS<R64W, R64, I64>;
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namespace {
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template <typename D, typename S1, typename S2>
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DEF_SEM(ANDS, D dst, S1 src1, S2 src2) {
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auto res = UAnd(Read(src1), Read(src2));
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WriteZExt(dst, res);
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FLAG_N = SignFlag(res);
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FLAG_Z = ZeroFlag(res);
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FLAG_C = false;
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FLAG_V = false;
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return memory;
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}
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} // namespace
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DEF_ISEL(ANDS_32S_LOG_IMM) = ANDS<R32W, R32, I32>;
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DEF_ISEL(ANDS_64S_LOG_IMM) = ANDS<R64W, R64, I64>;
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DEF_ISEL(ANDS_32_LOG_SHIFT) = ANDS<R32W, R32, I32>;
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DEF_ISEL(ANDS_64_LOG_SHIFT) = ANDS<R64W, R64, I64>;
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namespace {
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template <typename D, typename S>
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DEF_SEM(LSLV, D dst, S src1, S src2) {
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using T = typename BaseType<S>::BT;
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constexpr auto size = T(sizeof(T) * 8);
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WriteZExt(dst, UShl(Read(src1), URem(Read(src2), size)));
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return memory;
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}
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template <typename D, typename S>
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DEF_SEM(LSRV, D dst, S src1, S src2) {
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using T = typename BaseType<S>::BT;
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constexpr auto size = T(sizeof(T) * 8);
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WriteZExt(dst, UShr(Read(src1), URem(Read(src2), size)));
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return memory;
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}
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template <typename D, typename S>
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DEF_SEM(ASRV, D dst, S src1, S src2) {
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using T = typename BaseType<S>::BT;
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constexpr auto size = T(sizeof(T) * 8);
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WriteZExt(dst,
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Unsigned(SShr(Signed(Read(src1)), Signed(URem(Read(src2), size)))));
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return memory;
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}
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template <typename D, typename S>
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DEF_SEM(RORV, D dst, S src1, S src2) {
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using T = typename BaseType<S>::BT;
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constexpr auto size = T(sizeof(T) * 8);
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WriteZExt(dst, Ror(Read(src1), URem(Read(src2), size)));
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return memory;
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}
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} // namespace
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DEF_ISEL(LSLV_32_DP_2SRC) = LSLV<R32W, R32>;
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DEF_ISEL(LSLV_64_DP_2SRC) = LSLV<R64W, R64>;
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DEF_ISEL(LSRV_32_DP_2SRC) = LSRV<R32W, R32>;
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DEF_ISEL(LSRV_64_DP_2SRC) = LSRV<R64W, R64>;
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DEF_ISEL(ASRV_32_DP_2SRC) = ASRV<R32W, R32>;
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DEF_ISEL(ASRV_64_DP_2SRC) = ASRV<R64W, R64>;
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DEF_ISEL(RORV_32_DP_2SRC) = RORV<R32W, R32>;
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DEF_ISEL(RORV_64_DP_2SRC) = RORV<R64W, R64>;
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