mirror of
https://github.com/lifting-bits/remill
synced 2026-06-21 13:56:07 +00:00
Duncan Ogilvie
60 lines
2.4 KiB
Diff
60 lines
2.4 KiB
Diff
From 1e54d8a6734348789b561489a84da5a7e45315ea Mon Sep 17 00:00:00 2001
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From: 2over12 <ian.smith@trailofbits.com>
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Date: Mon, 24 Apr 2023 13:29:41 -0400
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Subject: [PATCH 08/13] ppc_common
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---
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.../PowerPC/data/languages/ppc_common.sinc | 21 +++++++++++++++++--
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1 file changed, 19 insertions(+), 2 deletions(-)
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diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc
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index 46aa86c74c..60c96058eb 100644
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--- a/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc
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+++ b/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc
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@@ -3,6 +3,10 @@
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# version 1.0
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define endian=$(ENDIAN);
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+@define INST_NEXT_PTR "pc"
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+
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+define pcodeop claim_eq;
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+
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define alignment=2;
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@@ -1200,6 +1204,9 @@ attach names [ vrDD vrAD vrBD vrSD vrCD]
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[ v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15
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v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 ];
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+
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+remill_insn_size: calculated_size is epsilon [calculated_size= inst_next-inst_start; ] { local insn_size_hinted:$(REGISTER_SIZE)=calculated_size;
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+ export insn_size_hinted; }
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vrD: vrDD is vrDD & vrDR { export vrDR; }
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vrA: vrAD is vrAD & vrAR { export vrAR; }
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vrB: vrBD is vrBD & vrBR { export vrBR; }
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@@ -1824,9 +1831,19 @@ macro unpackFPSCR(tmp) {
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REL_ABS: "a" is AA = 1 {}
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REL_ABS: is AA = 0 {}
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-addressLI: reloc is LI & AA=0 [ reloc = inst_start + LI*4;] { export *[ram]:4 reloc; }
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+addressLI: reloc is LI & AA=0 ; remill_insn_size [ reloc = inst_start + LI*4;] {
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+remill_please_dont_use_this_temp_named:$(REGISTER_SIZE)=reloc;
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+claim_eq(remill_please_dont_use_this_temp_named, ($(INST_NEXT_PTR)-remill_insn_size) + LI*4);
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+ export *[ram]:4 reloc;
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+ }
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+
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addressLI: reloc is LI & AA=1 [ reloc = LI*4; ] { export *[ram]:4 reloc; }
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-addressBD: reloc is BD & AA=0 [ reloc = inst_start + BD*4; ] { export *[ram]:4 reloc; }
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+addressBD: reloc is BD & AA=0 ; remill_insn_size [ reloc = inst_start + BD*4; ] {
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+remill_please_dont_use_this_temp_name12:$(REGISTER_SIZE)=reloc;
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+claim_eq(remill_please_dont_use_this_temp_name12, ($(INST_NEXT_PTR)-remill_insn_size) + BD*4);
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+ export *[ram]:4 reloc;
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+ }
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+
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addressBD: reloc is BD & AA=1 [ reloc = BD*4; ] { export *[ram]:4 reloc; }
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OFF16SH: val is D0 & D1 & D2 [ val = ((D0 << 6) | (D1 << 1) | D2) << 16; ] { export *[const]:4 val;}
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--
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2.34.1
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