mirror of
https://github.com/lifting-bits/remill
synced 2026-06-21 13:56:07 +00:00
Peter Goodman
99df2e19d4
* Running clang-format on files with some additional custom scripts for my style * Fix missing unique_ptr in remill/BC/Optimizer.h * Fixes and selective disabling of clang-format
371 lines
13 KiB
C++
371 lines
13 KiB
C++
/*
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* Copyright (c) 2018 Trail of Bits, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <algorithm>
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#include <bitset>
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#include <cmath>
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#include "remill/Arch/AArch64/Runtime/State.h"
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#include "remill/Arch/Float.h"
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extern "C" {
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Wunused-variable"
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// Instructions will be lifted into clones of this function.
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[[gnu::used]] Memory *__remill_basic_block(State &state, addr_t curr_pc,
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Memory *memory) {
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bool branch_taken = false;
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addr_t monitor = 0;
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addr_t return_pc = 0;
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// Note: These variables MUST be defined for all architectures.
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auto &STATE = state;
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auto &MEMORY = *memory;
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auto &PC = state.gpr.pc.qword;
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auto &NEXT_PC = curr_pc;
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auto &BRANCH_TAKEN = branch_taken;
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auto &RETURN_PC = return_pc;
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// `PC` should already have the correct value, but it's nice to make sure
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// that `curr_pc` is used throughout, as it helps with certain downstream
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// uses to be able to depend on the optimizer not eliminating `curr_pc`.
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state.gpr.pc.qword = curr_pc;
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auto &WPC = state.gpr.pc.dword;
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// This is to support load-linked/store-conditional operations.
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auto &MONITOR = monitor;
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auto &W0 = state.gpr.x0.dword;
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auto &W1 = state.gpr.x1.dword;
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auto &W2 = state.gpr.x2.dword;
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auto &W3 = state.gpr.x3.dword;
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auto &W4 = state.gpr.x4.dword;
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auto &W5 = state.gpr.x5.dword;
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auto &W6 = state.gpr.x6.dword;
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auto &W7 = state.gpr.x7.dword;
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auto &W8 = state.gpr.x8.dword;
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auto &W9 = state.gpr.x9.dword;
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auto &W10 = state.gpr.x10.dword;
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auto &W11 = state.gpr.x11.dword;
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auto &W12 = state.gpr.x12.dword;
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auto &W13 = state.gpr.x13.dword;
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auto &W14 = state.gpr.x14.dword;
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auto &W15 = state.gpr.x15.dword;
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auto &W16 = state.gpr.x16.dword;
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auto &W17 = state.gpr.x17.dword;
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auto &W18 = state.gpr.x18.dword;
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auto &W19 = state.gpr.x19.dword;
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auto &W20 = state.gpr.x20.dword;
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auto &W21 = state.gpr.x21.dword;
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auto &W22 = state.gpr.x22.dword;
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auto &W23 = state.gpr.x23.dword;
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auto &W24 = state.gpr.x24.dword;
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auto &W25 = state.gpr.x25.dword;
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auto &W26 = state.gpr.x26.dword;
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auto &W27 = state.gpr.x27.dword;
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auto &W28 = state.gpr.x28.dword;
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auto &W29 = state.gpr.x29.dword;
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auto &W30 = state.gpr.x30.dword;
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auto &X0 = state.gpr.x0.qword;
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auto &X1 = state.gpr.x1.qword;
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auto &X2 = state.gpr.x2.qword;
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auto &X3 = state.gpr.x3.qword;
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auto &X4 = state.gpr.x4.qword;
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auto &X5 = state.gpr.x5.qword;
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auto &X6 = state.gpr.x6.qword;
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auto &X7 = state.gpr.x7.qword;
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auto &X8 = state.gpr.x8.qword;
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auto &X9 = state.gpr.x9.qword;
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auto &X10 = state.gpr.x10.qword;
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auto &X11 = state.gpr.x11.qword;
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auto &X12 = state.gpr.x12.qword;
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auto &X13 = state.gpr.x13.qword;
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auto &X14 = state.gpr.x14.qword;
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auto &X15 = state.gpr.x15.qword;
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auto &X16 = state.gpr.x16.qword;
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auto &X17 = state.gpr.x17.qword;
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auto &X18 = state.gpr.x18.qword;
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auto &X19 = state.gpr.x19.qword;
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auto &X20 = state.gpr.x20.qword;
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auto &X21 = state.gpr.x21.qword;
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auto &X22 = state.gpr.x22.qword;
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auto &X23 = state.gpr.x23.qword;
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auto &X24 = state.gpr.x24.qword;
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auto &X25 = state.gpr.x25.qword;
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auto &X26 = state.gpr.x26.qword;
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auto &X27 = state.gpr.x27.qword;
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auto &X28 = state.gpr.x28.qword;
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auto &X29 = state.gpr.x29.qword;
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auto &X30 = state.gpr.x30.qword;
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auto &FP = state.gpr.x29.qword;
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auto &WFP = state.gpr.x29.dword;
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auto &LP = state.gpr.x30.qword;
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auto &WLP = state.gpr.x30.dword;
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auto &SP = state.gpr.sp.qword;
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auto &WSP = state.gpr.sp.dword;
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uint32_t zero1 = 0;
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auto &WZR = zero1;
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uint64_t zero2 = 0;
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auto &XZR = zero2;
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uint32_t ignored1 = 0;
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auto &IGNORE_WRITE_TO_WZR = ignored1;
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uint64_t ignored2 = 0;
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auto &IGNORE_WRITE_TO_XZR = ignored2;
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// Used to suppress writeback for pre- and post-index memory operands when
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// the base register and destination register are the same.
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uint64_t ignored3 = 0;
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auto &SUPPRESS_WRITEBACK = ignored3;
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auto &B0 = state.simd.v[0].bytes.elems[0];
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auto &B1 = state.simd.v[1].bytes.elems[0];
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auto &B2 = state.simd.v[2].bytes.elems[0];
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auto &B3 = state.simd.v[3].bytes.elems[0];
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auto &B4 = state.simd.v[4].bytes.elems[0];
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auto &B5 = state.simd.v[5].bytes.elems[0];
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auto &B6 = state.simd.v[6].bytes.elems[0];
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auto &B7 = state.simd.v[7].bytes.elems[0];
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auto &B8 = state.simd.v[8].bytes.elems[0];
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auto &B9 = state.simd.v[9].bytes.elems[0];
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auto &B10 = state.simd.v[10].bytes.elems[0];
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auto &B11 = state.simd.v[11].bytes.elems[0];
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auto &B12 = state.simd.v[12].bytes.elems[0];
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auto &B13 = state.simd.v[13].bytes.elems[0];
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auto &B14 = state.simd.v[14].bytes.elems[0];
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auto &B15 = state.simd.v[15].bytes.elems[0];
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auto &B16 = state.simd.v[16].bytes.elems[0];
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auto &B17 = state.simd.v[17].bytes.elems[0];
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auto &B18 = state.simd.v[18].bytes.elems[0];
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auto &B19 = state.simd.v[19].bytes.elems[0];
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auto &B20 = state.simd.v[20].bytes.elems[0];
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auto &B21 = state.simd.v[21].bytes.elems[0];
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auto &B22 = state.simd.v[22].bytes.elems[0];
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auto &B23 = state.simd.v[23].bytes.elems[0];
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auto &B24 = state.simd.v[24].bytes.elems[0];
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auto &B25 = state.simd.v[25].bytes.elems[0];
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auto &B26 = state.simd.v[26].bytes.elems[0];
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auto &B27 = state.simd.v[27].bytes.elems[0];
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auto &B28 = state.simd.v[28].bytes.elems[0];
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auto &B29 = state.simd.v[29].bytes.elems[0];
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auto &B30 = state.simd.v[30].bytes.elems[0];
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auto &B31 = state.simd.v[31].bytes.elems[0];
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// NOTE(pag): These are kind of a lie: they are there to support load/store
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// of half-words, but they don't have a 16-bit float data
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// representation.
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auto &H0 = state.simd.v[0].words.elems[0];
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auto &H1 = state.simd.v[1].words.elems[0];
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auto &H2 = state.simd.v[2].words.elems[0];
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auto &H3 = state.simd.v[3].words.elems[0];
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auto &H4 = state.simd.v[4].words.elems[0];
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auto &H5 = state.simd.v[5].words.elems[0];
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auto &H6 = state.simd.v[6].words.elems[0];
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auto &H7 = state.simd.v[7].words.elems[0];
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auto &H8 = state.simd.v[8].words.elems[0];
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auto &H9 = state.simd.v[9].words.elems[0];
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auto &H10 = state.simd.v[10].words.elems[0];
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auto &H11 = state.simd.v[11].words.elems[0];
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auto &H12 = state.simd.v[12].words.elems[0];
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auto &H13 = state.simd.v[13].words.elems[0];
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auto &H14 = state.simd.v[14].words.elems[0];
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auto &H15 = state.simd.v[15].words.elems[0];
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auto &H16 = state.simd.v[16].words.elems[0];
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auto &H17 = state.simd.v[17].words.elems[0];
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auto &H18 = state.simd.v[18].words.elems[0];
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auto &H19 = state.simd.v[19].words.elems[0];
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auto &H20 = state.simd.v[20].words.elems[0];
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auto &H21 = state.simd.v[21].words.elems[0];
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auto &H22 = state.simd.v[22].words.elems[0];
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auto &H23 = state.simd.v[23].words.elems[0];
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auto &H24 = state.simd.v[24].words.elems[0];
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auto &H25 = state.simd.v[25].words.elems[0];
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auto &H26 = state.simd.v[26].words.elems[0];
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auto &H27 = state.simd.v[27].words.elems[0];
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auto &H28 = state.simd.v[28].words.elems[0];
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auto &H29 = state.simd.v[29].words.elems[0];
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auto &H30 = state.simd.v[30].words.elems[0];
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auto &H31 = state.simd.v[31].words.elems[0];
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auto &S0 = state.simd.v[0].dwords.elems[0];
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auto &S1 = state.simd.v[1].dwords.elems[0];
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auto &S2 = state.simd.v[2].dwords.elems[0];
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auto &S3 = state.simd.v[3].dwords.elems[0];
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auto &S4 = state.simd.v[4].dwords.elems[0];
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auto &S5 = state.simd.v[5].dwords.elems[0];
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auto &S6 = state.simd.v[6].dwords.elems[0];
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auto &S7 = state.simd.v[7].dwords.elems[0];
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auto &S8 = state.simd.v[8].dwords.elems[0];
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auto &S9 = state.simd.v[9].dwords.elems[0];
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auto &S10 = state.simd.v[10].dwords.elems[0];
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auto &S11 = state.simd.v[11].dwords.elems[0];
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auto &S12 = state.simd.v[12].dwords.elems[0];
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auto &S13 = state.simd.v[13].dwords.elems[0];
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auto &S14 = state.simd.v[14].dwords.elems[0];
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auto &S15 = state.simd.v[15].dwords.elems[0];
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auto &S16 = state.simd.v[16].dwords.elems[0];
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auto &S17 = state.simd.v[17].dwords.elems[0];
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auto &S18 = state.simd.v[18].dwords.elems[0];
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auto &S19 = state.simd.v[19].dwords.elems[0];
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auto &S20 = state.simd.v[20].dwords.elems[0];
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auto &S21 = state.simd.v[21].dwords.elems[0];
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auto &S22 = state.simd.v[22].dwords.elems[0];
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auto &S23 = state.simd.v[23].dwords.elems[0];
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auto &S24 = state.simd.v[24].dwords.elems[0];
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auto &S25 = state.simd.v[25].dwords.elems[0];
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auto &S26 = state.simd.v[26].dwords.elems[0];
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auto &S27 = state.simd.v[27].dwords.elems[0];
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auto &S28 = state.simd.v[28].dwords.elems[0];
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auto &S29 = state.simd.v[29].dwords.elems[0];
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auto &S30 = state.simd.v[30].dwords.elems[0];
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auto &S31 = state.simd.v[31].dwords.elems[0];
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auto &D0 = state.simd.v[0].qwords.elems[0];
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auto &D1 = state.simd.v[1].qwords.elems[0];
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auto &D2 = state.simd.v[2].qwords.elems[0];
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auto &D3 = state.simd.v[3].qwords.elems[0];
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auto &D4 = state.simd.v[4].qwords.elems[0];
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auto &D5 = state.simd.v[5].qwords.elems[0];
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auto &D6 = state.simd.v[6].qwords.elems[0];
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auto &D7 = state.simd.v[7].qwords.elems[0];
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auto &D8 = state.simd.v[8].qwords.elems[0];
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auto &D9 = state.simd.v[9].qwords.elems[0];
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auto &D10 = state.simd.v[10].qwords.elems[0];
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auto &D11 = state.simd.v[11].qwords.elems[0];
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auto &D12 = state.simd.v[12].qwords.elems[0];
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auto &D13 = state.simd.v[13].qwords.elems[0];
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auto &D14 = state.simd.v[14].qwords.elems[0];
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auto &D15 = state.simd.v[15].qwords.elems[0];
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auto &D16 = state.simd.v[16].qwords.elems[0];
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auto &D17 = state.simd.v[17].qwords.elems[0];
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auto &D18 = state.simd.v[18].qwords.elems[0];
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auto &D19 = state.simd.v[19].qwords.elems[0];
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auto &D20 = state.simd.v[20].qwords.elems[0];
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auto &D21 = state.simd.v[21].qwords.elems[0];
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auto &D22 = state.simd.v[22].qwords.elems[0];
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auto &D23 = state.simd.v[23].qwords.elems[0];
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auto &D24 = state.simd.v[24].qwords.elems[0];
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auto &D25 = state.simd.v[25].qwords.elems[0];
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auto &D26 = state.simd.v[26].qwords.elems[0];
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auto &D27 = state.simd.v[27].qwords.elems[0];
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auto &D28 = state.simd.v[28].qwords.elems[0];
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auto &D29 = state.simd.v[29].qwords.elems[0];
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auto &D30 = state.simd.v[30].qwords.elems[0];
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auto &D31 = state.simd.v[31].qwords.elems[0];
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auto &Q0 = state.simd.v[0].dqwords.elems[0];
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auto &Q1 = state.simd.v[1].dqwords.elems[0];
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auto &Q2 = state.simd.v[2].dqwords.elems[0];
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auto &Q3 = state.simd.v[3].dqwords.elems[0];
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auto &Q4 = state.simd.v[4].dqwords.elems[0];
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auto &Q5 = state.simd.v[5].dqwords.elems[0];
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auto &Q6 = state.simd.v[6].dqwords.elems[0];
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auto &Q7 = state.simd.v[7].dqwords.elems[0];
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auto &Q8 = state.simd.v[8].dqwords.elems[0];
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auto &Q9 = state.simd.v[9].dqwords.elems[0];
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auto &Q10 = state.simd.v[10].dqwords.elems[0];
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auto &Q11 = state.simd.v[11].dqwords.elems[0];
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auto &Q12 = state.simd.v[12].dqwords.elems[0];
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auto &Q13 = state.simd.v[13].dqwords.elems[0];
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auto &Q14 = state.simd.v[14].dqwords.elems[0];
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auto &Q15 = state.simd.v[15].dqwords.elems[0];
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auto &Q16 = state.simd.v[16].dqwords.elems[0];
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auto &Q17 = state.simd.v[17].dqwords.elems[0];
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auto &Q18 = state.simd.v[18].dqwords.elems[0];
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auto &Q19 = state.simd.v[19].dqwords.elems[0];
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auto &Q20 = state.simd.v[20].dqwords.elems[0];
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auto &Q21 = state.simd.v[21].dqwords.elems[0];
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auto &Q22 = state.simd.v[22].dqwords.elems[0];
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auto &Q23 = state.simd.v[23].dqwords.elems[0];
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auto &Q24 = state.simd.v[24].dqwords.elems[0];
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auto &Q25 = state.simd.v[25].dqwords.elems[0];
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auto &Q26 = state.simd.v[26].dqwords.elems[0];
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auto &Q27 = state.simd.v[27].dqwords.elems[0];
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auto &Q28 = state.simd.v[28].dqwords.elems[0];
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auto &Q29 = state.simd.v[29].dqwords.elems[0];
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auto &Q30 = state.simd.v[30].dqwords.elems[0];
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auto &Q31 = state.simd.v[31].dqwords.elems[0];
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auto &V0 = state.simd.v[0];
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auto &V1 = state.simd.v[1];
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auto &V2 = state.simd.v[2];
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auto &V3 = state.simd.v[3];
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auto &V4 = state.simd.v[4];
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auto &V5 = state.simd.v[5];
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auto &V6 = state.simd.v[6];
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auto &V7 = state.simd.v[7];
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auto &V8 = state.simd.v[8];
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auto &V9 = state.simd.v[9];
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auto &V10 = state.simd.v[10];
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auto &V11 = state.simd.v[11];
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auto &V12 = state.simd.v[12];
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auto &V13 = state.simd.v[13];
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auto &V14 = state.simd.v[14];
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auto &V15 = state.simd.v[15];
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auto &V16 = state.simd.v[16];
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auto &V17 = state.simd.v[17];
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auto &V18 = state.simd.v[18];
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auto &V19 = state.simd.v[19];
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auto &V20 = state.simd.v[20];
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auto &V21 = state.simd.v[21];
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auto &V22 = state.simd.v[22];
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auto &V23 = state.simd.v[23];
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|
auto &V24 = state.simd.v[24];
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|
auto &V25 = state.simd.v[25];
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|
auto &V26 = state.simd.v[26];
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|
auto &V27 = state.simd.v[27];
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|
auto &V28 = state.simd.v[28];
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|
auto &V29 = state.simd.v[29];
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|
auto &V30 = state.simd.v[30];
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|
auto &V31 = state.simd.v[31];
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|
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auto &TPIDR_EL0 = state.sr.tpidr_el0.aword;
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auto &TPIDRRO_EL0 = state.sr.tpidrro_el0.aword;
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|
|
|
// Lifted code will be placed here in clones versions of this function.
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|
return memory;
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|
}
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|
|
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#pragma clang diagnostic pop
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|
|
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} // extern C
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|
|
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#include "remill/Arch/Runtime/Intrinsics.cpp"
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