mirror of
https://github.com/lifting-bits/remill
synced 2026-06-21 13:56:07 +00:00
Peter Goodman
99df2e19d4
* Running clang-format on files with some additional custom scripts for my style * Fix missing unique_ptr in remill/BC/Optimizer.h * Fixes and selective disabling of clang-format
219 lines
7.2 KiB
C++
219 lines
7.2 KiB
C++
/*
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* Copyright (c) 2017 Trail of Bits, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#pragma once
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namespace {
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template <typename D, typename S1, typename S2>
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DEF_SEM(ROL, D dst, S1 src1, S2 src2) {
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auto val = Read(src1);
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auto count = ZExtTo<S1>(Read(src2));
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auto one = Literal<S1>(1);
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auto long_mask = Literal<S1>(0x3F);
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auto short_mask = Literal<S1>(0x1F);
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auto op_size = BitSizeOf(src1);
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auto count_mask = Select(UCmpEq(op_size, 64), long_mask, short_mask);
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auto masked_count = UAnd(count, count_mask);
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auto temp_count = URem(masked_count, op_size);
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if (temp_count) {
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auto new_val =
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UOr(UShl(val, temp_count), UShr(val, USub(op_size, temp_count)));
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WriteZExt(dst, new_val);
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Write(FLAG_CF, UCmpEq(UAnd(new_val, one), one));
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if (1 == temp_count) {
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Write(FLAG_OF, BXor(FLAG_CF, SignFlag(new_val)));
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} else {
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Write(FLAG_OF, false);
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}
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// OF undefined for `1 == temp_count`.
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} else {
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WriteZExt(dst, val);
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}
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return memory;
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}
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template <typename D, typename S1, typename S2>
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DEF_SEM(ROR, D dst, S1 src1, S2 src2) {
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auto val = Read(src1);
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auto count = ZExtTo<S1>(Read(src2));
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auto one = Literal<S1>(1);
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auto long_mask = Literal<S1>(0x3F);
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auto short_mask = Literal<S1>(0x1F);
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auto op_size = BitSizeOf(src1);
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auto count_mask = Select(UCmpEq(op_size, 64), long_mask, short_mask);
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auto masked_count = UAnd(count, count_mask);
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auto temp_count = URem(masked_count, op_size);
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if (temp_count) {
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auto new_val =
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UOr(UShr(val, temp_count), UShl(val, USub(op_size, temp_count)));
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WriteZExt(dst, new_val);
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Write(FLAG_CF, SignFlag(new_val));
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Write(FLAG_OF, BXor(FLAG_CF, SignFlag(UShl(new_val, one))));
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// OF undefined for `1 == temp_count`.
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} else {
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WriteZExt(dst, val);
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}
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return memory;
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}
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template <typename D, typename S1, typename S2>
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DEF_SEM(RORX, D dst, S1 src1, S2 src2) {
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auto val = Read(src1);
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auto count = ZExtTo<S1>(Read(src2));
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auto long_mask = Literal<S1>(0x3F);
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auto short_mask = Literal<S1>(0x1F);
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auto op_size = BitSizeOf(src1);
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auto count_mask = Select(UCmpEq(op_size, 64), long_mask, short_mask);
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auto masked_count = UAnd(count, count_mask);
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auto temp_count = URem(masked_count, op_size);
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auto new_val =
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UOr(UShr(val, temp_count), UShl(val, USub(op_size, temp_count)));
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WriteZExt(dst, new_val);
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return memory;
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}
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} // namespace
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DEF_ISEL(ROL_MEMb_IMMb) = ROL<M8W, M8, I8>;
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DEF_ISEL(ROL_GPR8_IMMb) = ROL<R8W, R8, I8>;
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DEF_ISEL_MnW_Mn_In(ROL_MEMv_IMMb, ROL);
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DEF_ISEL_RnW_Rn_In(ROL_GPRv_IMMb, ROL);
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DEF_ISEL(ROL_MEMb_ONE) = ROL<M8W, M8, I8>;
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DEF_ISEL(ROL_GPR8_ONE) = ROL<R8W, R8, I8>;
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DEF_ISEL_MnW_Mn_In(ROL_MEMv_ONE, ROL);
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DEF_ISEL_RnW_Rn_In(ROL_GPRv_ONE, ROL);
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DEF_ISEL(ROL_MEMb_CL) = ROL<M8W, M8, R8>;
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DEF_ISEL(ROL_GPR8_CL) = ROL<R8W, R8, R8>;
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DEF_ISEL_MnW_Mn_Rn(ROL_MEMv_CL, ROL);
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DEF_ISEL_RnW_Rn_Rn(ROL_GPRv_CL, ROL);
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DEF_ISEL(ROR_MEMb_IMMb) = ROR<M8W, M8, I8>;
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DEF_ISEL(ROR_GPR8_IMMb) = ROR<R8W, R8, I8>;
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DEF_ISEL_MnW_Mn_In(ROR_MEMv_IMMb, ROR);
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DEF_ISEL_RnW_Rn_In(ROR_GPRv_IMMb, ROR);
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DEF_ISEL(ROR_MEMb_ONE) = ROR<M8W, M8, I8>;
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DEF_ISEL(ROR_GPR8_ONE) = ROR<R8W, R8, I8>;
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DEF_ISEL_MnW_Mn_In(ROR_MEMv_ONE, ROR);
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DEF_ISEL_RnW_Rn_In(ROR_GPRv_ONE, ROR);
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DEF_ISEL(ROR_MEMb_CL) = ROR<M8W, M8, R8>;
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DEF_ISEL(ROR_GPR8_CL) = ROR<R8W, R8, R8>;
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DEF_ISEL_MnW_Mn_Rn(ROR_MEMv_CL, ROR);
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DEF_ISEL_RnW_Rn_Rn(ROR_GPRv_CL, ROR);
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DEF_ISEL(RORX_VGPR32d_VGPR32d_IMMb) = RORX<R32W, R32, I8>;
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DEF_ISEL(RORX_VGPR32d_MEMd_IMMb) = RORX<R32W, M32, I8>;
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DEF_ISEL(RORX_VGPR64q_VGPR64q_IMMb) = RORX<R64W, R64, I8>;
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DEF_ISEL(RORX_VGPR64q_MEMq_IMMb) = RORX<R64W, M64, I8>;
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namespace {
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template <typename D, typename S1, typename S2>
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DEF_SEM(RCL, D dst, S1 src1, S2 src2) {
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auto val = Read(src1);
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auto count = ZExtTo<S1>(Read(src2));
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auto zero = Literal<S1>(0);
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auto one = Literal<S1>(1);
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auto long_mask = Literal<S1>(0x3F);
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auto short_mask = Literal<S1>(0x1F);
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auto op_size = BitSizeOf(src1);
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auto count_mask = Select(UCmpEq(op_size, 64), long_mask, short_mask);
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auto count_mod =
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Select(UCmpLt(op_size, 32), UAdd(op_size, one), UAdd(count_mask, one));
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auto masked_count = UAnd(count, count_mask);
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auto temp_count = URem(masked_count, count_mod);
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auto carry = Select(FLAG_CF, one, zero);
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if (temp_count) {
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auto right = UShr(val, USub(op_size, temp_count));
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auto new_val =
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UOr(UOr(UShl(val, temp_count), UShl(carry, USub(temp_count, one))),
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UShr(right, one));
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WriteZExt(dst, new_val);
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Write(FLAG_CF, SignFlag(UShl(val, USub(temp_count, one))));
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Write(FLAG_OF, BXor(FLAG_CF, SignFlag(new_val)));
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// OF undefined for `1 == temp_count`.
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} else {
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WriteZExt(dst, val);
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}
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return memory;
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}
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template <typename D, typename S1, typename S2>
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DEF_SEM(RCR, D dst, S1 src1, S2 src2) {
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auto val = Read(src1);
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auto count = ZExtTo<S1>(Read(src2));
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auto one = Literal<S1>(1);
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auto zero = Literal<S1>(0);
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auto long_mask = Literal<S1>(0x3F);
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auto short_mask = Literal<S1>(0x1F);
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auto op_size = BitSizeOf(src1);
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auto count_mask = Select(UCmpEq(op_size, 64), long_mask, short_mask);
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auto count_mod =
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Select(UCmpLt(op_size, 32), UAdd(op_size, one), UAdd(count_mask, one));
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auto masked_count = UAnd(count, count_mask);
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auto temp_count = URem(masked_count, count_mod);
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auto carry = Select(FLAG_CF, one, zero);
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if (temp_count) {
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auto left = UShr(val, USub(temp_count, one));
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auto right = UShl(val, USub(op_size, temp_count));
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auto new_val =
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UOr(UOr(UShr(left, one), UShl(carry, USub(op_size, temp_count))),
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UShl(right, one));
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WriteZExt(dst, new_val);
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Write(FLAG_CF, UCmpNeq(UAnd(left, one), zero));
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Write(FLAG_OF, BXor(SignFlag(UShl(new_val, one)), SignFlag(new_val)));
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// OF undefined for `1 == temp_count`.
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} else {
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WriteZExt(dst, val);
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}
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return memory;
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}
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} // namespace
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DEF_ISEL(RCL_MEMb_IMMb) = RCL<M8W, M8, I8>;
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DEF_ISEL(RCL_GPR8_IMMb) = RCL<R8W, R8, I8>;
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DEF_ISEL_MnW_Mn_In(RCL_MEMv_IMMb, RCL);
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DEF_ISEL_RnW_Rn_In(RCL_GPRv_IMMb, RCL);
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DEF_ISEL(RCL_MEMb_ONE) = RCL<M8W, M8, I8>;
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DEF_ISEL(RCL_GPR8_ONE) = RCL<R8W, R8, I8>;
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DEF_ISEL_MnW_Mn_In(RCL_MEMv_ONE, RCL);
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DEF_ISEL_RnW_Rn_In(RCL_GPRv_ONE, RCL);
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DEF_ISEL(RCL_MEMb_CL) = RCL<M8W, M8, R8>;
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DEF_ISEL(RCL_GPR8_CL) = RCL<R8W, R8, R8>;
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DEF_ISEL_MnW_Mn_Rn(RCL_MEMv_CL, RCL);
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DEF_ISEL_RnW_Rn_Rn(RCL_GPRv_CL, RCL);
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DEF_ISEL(RCR_MEMb_IMMb) = RCR<M8W, M8, I8>;
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DEF_ISEL(RCR_GPR8_IMMb) = RCR<R8W, R8, I8>;
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DEF_ISEL_MnW_Mn_In(RCR_MEMv_IMMb, RCR);
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DEF_ISEL_RnW_Rn_In(RCR_GPRv_IMMb, RCR);
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DEF_ISEL(RCR_MEMb_ONE) = RCR<M8W, M8, I8>;
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DEF_ISEL(RCR_GPR8_ONE) = RCR<R8W, R8, I8>;
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DEF_ISEL_MnW_Mn_In(RCR_MEMv_ONE, RCR);
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DEF_ISEL_RnW_Rn_In(RCR_GPRv_ONE, RCR);
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DEF_ISEL(RCR_MEMb_CL) = RCR<M8W, M8, R8>;
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DEF_ISEL(RCR_GPR8_CL) = RCR<R8W, R8, R8>;
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DEF_ISEL_MnW_Mn_Rn(RCR_MEMv_CL, RCR);
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DEF_ISEL_RnW_Rn_Rn(RCR_GPRv_CL, RCR);
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