mirror of
https://github.com/lifting-bits/remill
synced 2026-06-21 13:56:07 +00:00
Peter Goodman
99df2e19d4
* Running clang-format on files with some additional custom scripts for my style * Fix missing unique_ptr in remill/BC/Optimizer.h * Fixes and selective disabling of clang-format
117 lines
3.7 KiB
C++
117 lines
3.7 KiB
C++
/*
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* Copyright (c) 2017 Trail of Bits, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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namespace {
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#define MAKE_CMPXCHG_XAX(xax) \
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template <typename D, typename S1, typename S2> \
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DEF_SEM(CMPXCHG_##xax, D dst, S1 src1, S2 src2) { \
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auto desired_val = Read(src2); \
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auto check_val = Read(REG_##xax); \
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auto prev_value = check_val; \
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auto swap_flag = UCmpXchg(dst, check_val, desired_val); \
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auto sub_res = USub(prev_value, check_val); \
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WriteFlagsAddSub<tag_sub>(state, prev_value, check_val, sub_res); \
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Write(FLAG_ZF, swap_flag); \
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WriteZExt(REG_##xax, check_val); \
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return memory; \
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}
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MAKE_CMPXCHG_XAX(AL)
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MAKE_CMPXCHG_XAX(AX)
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MAKE_CMPXCHG_XAX(EAX)
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IF_64BIT(MAKE_CMPXCHG_XAX(RAX))
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DEF_SEM(DoCMPXCHG8B_MEMq, M64W dst, M64 src1) {
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auto xdx = Read(REG_EDX);
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auto xax = Read(REG_EAX);
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auto xcx = Read(REG_ECX);
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auto xbx = Read(REG_EBX);
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auto desired_val = UOr(UShl(ZExt(xcx), 32), ZExt(xbx));
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auto check_val = UOr(UShl(ZExt(xdx), 32), ZExt(xax));
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auto swap_flag = UCmpXchg(dst, check_val, desired_val);
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Write(FLAG_ZF, swap_flag);
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Write(REG_EDX, Trunc(UShr(check_val, 32)));
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Write(REG_EAX, Trunc(check_val));
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return memory;
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}
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#if 64 == ADDRESS_SIZE_BITS
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DEF_SEM(DoCMPXCHG16B_MEMdq, M128W dst, M128 src1) {
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auto xdx = Read(REG_RDX);
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auto xax = Read(REG_RAX);
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auto xcx = Read(REG_RCX);
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auto xbx = Read(REG_RBX);
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auto desired_val = UOr(UShl(ZExt(xcx), 64), ZExt(xbx));
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auto check_val = UOr(UShl(ZExt(xdx), 64), ZExt(xax));
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auto swap_flag = UCmpXchg(dst, check_val, desired_val);
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Write(FLAG_ZF, swap_flag);
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Write(REG_RDX, Trunc(UShr(check_val, 64)));
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Write(REG_RAX, Trunc(check_val));
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return memory;
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}
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#endif // 64 == ADDRESS_SIZE_BITS
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} // namespace
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DEF_ISEL(CMPXCHG_MEMb_GPR8) = CMPXCHG_AL<M8W, M8, R8>;
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DEF_ISEL(CMPXCHG_GPR8_GPR8) = CMPXCHG_AL<R8W, R8, R8>;
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DEF_ISEL(CMPXCHG_MEMv_GPRv_8) = CMPXCHG_AL<M8W, M8, R8>;
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DEF_ISEL(CMPXCHG_GPRv_GPRv_8) = CMPXCHG_AL<R8W, R8, R8>;
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DEF_ISEL(CMPXCHG_MEMv_GPRv_16) = CMPXCHG_AX<M16W, M16, R16>;
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DEF_ISEL(CMPXCHG_GPRv_GPRv_16) = CMPXCHG_AX<R16W, R16, R16>;
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DEF_ISEL(CMPXCHG_MEMv_GPRv_32) = CMPXCHG_EAX<M32W, M32, R32>;
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DEF_ISEL(CMPXCHG_GPRv_GPRv_32) = CMPXCHG_EAX<R32W, R32, R32>;
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IF_64BIT(DEF_ISEL(CMPXCHG_MEMv_GPRv_64) = CMPXCHG_RAX<M64W, M64, R64>;)
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IF_64BIT(DEF_ISEL(CMPXCHG_GPRv_GPRv_64) = CMPXCHG_RAX<R64W, R64, R64>;)
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DEF_ISEL(CMPXCHG8B_MEMq) = DoCMPXCHG8B_MEMq;
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#if 64 == ADDRESS_SIZE_BITS
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DEF_ISEL(CMPXCHG16B_MEMdq) = DoCMPXCHG16B_MEMdq;
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#endif // 64 == ADDRESS_SIZE_BITS
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namespace {
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// Atomic fetch-add.
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template <typename D1, typename S1, typename D2, typename S2>
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DEF_SEM(XADD, D1 dst1, S1 src1, D2 dst2, S2 src2) {
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// Our lifter only injects atomic begin/end around memory access instructions
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// but this instruction is a full memory barrier, even when registers are
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// accessed.
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if (IsRegister(dst1)) {
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BarrierStoreLoad();
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}
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auto rhs = Read(src1);
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auto lhs = Read(src2);
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auto sum = UAddFetch(dst2, rhs);
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WriteFlagsAddSub<tag_add>(state, rhs, lhs, sum);
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WriteZExt(dst1, sum);
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return memory;
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}
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} // namespace
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DEF_ISEL(XADD_MEMb_GPR8) = XADD<M8W, M8, R8W, R8>;
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DEF_ISEL(XADD_GPR8_GPR8) = XADD<R8W, R8, R8W, R8>;
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DEF_ISEL_MnW_Mn_RnW_Rn(XADD_MEMv_GPRv, XADD);
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DEF_ISEL_RnW_Rn_RnW_Rn(XADD_GPRv_GPRv, XADD);
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