mirror of
https://github.com/lifting-bits/remill
synced 2026-06-21 13:56:07 +00:00
Peter Goodman
c743aa4f85
* Minor reformatting, re-enabling test of CCMP. * Modified post-decoder of CCMP_n_CONDCMP_IMM, added more tests for it. Also added post-decoders, but NO tests for the register-register variant * Fixes #144. * Tests for LDP and STP. Decoder and semantics, but no tests for LDR and STR on the B, H, S, D, and Q vector sub-regs. * Minor fix * Minor fix, I think, to pre-index memops * Minor simplifying code to pre- and post-index address operand handling
306 lines
8.1 KiB
C++
306 lines
8.1 KiB
C++
/*
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* Copyright (c) 2017 Trail of Bits, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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namespace {
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DEF_SEM(StorePairUpdateIndex32, R32 src1, R32 src2, MV64W dst_mem,
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R64W dst_reg, ADDR next_addr) {
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uint32v2_t vec = {};
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vec = UInsertV32(vec, 0, Read(src1));
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vec = UInsertV32(vec, 1, Read(src2));
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UWriteV32(dst_mem, vec);
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Write(dst_reg, Read(next_addr));
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return memory;
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}
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DEF_SEM(StorePairUpdateIndex64, R64 src1, R64 src2, MV128W dst_mem,
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R64W dst_reg, ADDR next_addr) {
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uint64v2_t vec = {};
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vec = UInsertV64(vec, 0, Read(src1));
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vec = UInsertV64(vec, 1, Read(src2));
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UWriteV64(dst_mem, vec);
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Write(dst_reg, Read(next_addr));
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return memory;
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}
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DEF_SEM(StorePair32, R32 src1, R32 src2, MV64W dst) {
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uint32v2_t vec = {};
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UWriteV32(dst, UInsertV32(UInsertV32(vec, 0, Read(src1)), 1, Read(src2)));
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return memory;
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}
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DEF_SEM(StorePair64, R64 src1, R64 src2, MV128W dst) {
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uint64v2_t vec = {};
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UWriteV64(dst, UInsertV64(UInsertV64(vec, 0, Read(src1)), 1, Read(src2)));
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return memory;
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}
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} // namespace
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DEF_ISEL(STP_32_LDSTPAIR_PRE) = StorePairUpdateIndex32;
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DEF_ISEL(STP_32_LDSTPAIR_POST) = StorePairUpdateIndex32;
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DEF_ISEL(STP_64_LDSTPAIR_PRE) = StorePairUpdateIndex64;
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DEF_ISEL(STP_64_LDSTPAIR_POST) = StorePairUpdateIndex64;
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DEF_ISEL(STP_32_LDSTPAIR_OFF) = StorePair32;
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DEF_ISEL(STP_64_LDSTPAIR_OFF) = StorePair64;
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namespace {
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template <typename S, typename D>
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DEF_SEM(StoreUpdateIndex, S src, D dst_mem, R64W dst_reg, ADDR next_addr) {
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Write(dst_mem, Read(src));
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Write(dst_reg, Read(next_addr));
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return memory;
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}
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template <typename S, typename D>
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DEF_SEM(Store, S src, D dst) {
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Write(dst, Read(src));
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return memory;
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}
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template <typename S, typename D>
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DEF_SEM(STR_BASE_OFFSET, S src, D base, ADDR offset) {
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Write(DisplaceAddress(base, Read(offset)), Read(src));
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return memory;
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}
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} // namespace
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DEF_ISEL(STR_32_LDST_IMMPRE) = StoreUpdateIndex<R32, M32W>;
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DEF_ISEL(STR_32_LDST_IMMPOST) = StoreUpdateIndex<R32, M32W>;
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DEF_ISEL(STR_64_LDST_IMMPRE) = StoreUpdateIndex<R64, M64W>;
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DEF_ISEL(STR_64_LDST_IMMPOST) = StoreUpdateIndex<R64, M64W>;
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DEF_ISEL(STR_32_LDST_POS) = Store<R32, M32W>;
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DEF_ISEL(STR_64_LDST_POS) = Store<R64, M64W>;
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DEF_ISEL(STRB_32_LDST_POS) = Store<R8, M8W>;
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DEF_ISEL(STRH_32_LDST_POS) = Store<R16, M16W>;
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DEF_ISEL(STR_32_LDST_REGOFF) = STR_BASE_OFFSET<R32, M32W>;
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DEF_ISEL(STR_64_LDST_REGOFF) = STR_BASE_OFFSET<R64, M64W>;
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namespace {
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DEF_SEM(LoadPairUpdateIndex32, R32W dst1, R32W dst2, MV64 src_mem,
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R64W dst_reg, ADDR next_addr) {
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auto vec = UReadV32(src_mem);
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WriteZExt(dst1, UExtractV32(vec, 0));
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WriteZExt(dst2, UExtractV32(vec, 1));
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Write(dst_reg, Read(next_addr));
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return memory;
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}
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DEF_SEM(LoadPairUpdateIndex64, R64W dst1, R64W dst2, MV128 src_mem,
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R64W dst_reg, ADDR next_addr) {
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auto vec = UReadV64(src_mem);
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Write(dst1, UExtractV64(vec, 0));
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Write(dst2, UExtractV64(vec, 1));
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Write(dst_reg, Read(next_addr));
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return memory;
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}
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} // namespace
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DEF_ISEL(LDP_32_LDSTPAIR_PRE) = LoadPairUpdateIndex32;
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DEF_ISEL(LDP_32_LDSTPAIR_POST) = LoadPairUpdateIndex32;
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DEF_ISEL(LDP_64_LDSTPAIR_PRE) = LoadPairUpdateIndex64;
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DEF_ISEL(LDP_64_LDSTPAIR_POST) = LoadPairUpdateIndex64;
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namespace {
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DEF_SEM(LoadPair32, R32W dst1, R32W dst2, MV64 src_mem) {
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auto vec = UReadV32(src_mem);
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WriteZExt(dst1, UExtractV32(vec, 0));
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WriteZExt(dst2, UExtractV32(vec, 1));
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return memory;
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}
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DEF_SEM(LoadPair64, R64W dst1, R64W dst2, MV128 src_mem) {
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auto vec = UReadV64(src_mem);
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Write(dst1, UExtractV64(vec, 0));
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Write(dst2, UExtractV64(vec, 1));
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return memory;
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}
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} // namespace
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DEF_ISEL(LDP_32_LDSTPAIR_OFF) = LoadPair32;
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DEF_ISEL(LDP_64_LDSTPAIR_OFF) = LoadPair64;
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namespace {
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template <typename D, typename S>
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DEF_SEM(Load, D dst, S src) {
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WriteZExt(dst, Read(src));
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return memory;
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}
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template <typename D, typename M>
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DEF_SEM(LDR_BASE_OFFSET, D dst, M base, ADDR offset) {
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WriteZExt(dst, Read(DisplaceAddress(base, Read(offset))));
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return memory;
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}
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} // namespace
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DEF_ISEL(LDR_32_LDST_POS) = Load<R32W, M32>;
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DEF_ISEL(LDR_64_LDST_POS) = Load<R64W, M64>;
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DEF_ISEL(LDRB_32_LDST_POS) = Load<R8W, M8>;
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DEF_ISEL(LDRB_32B_LDST_REGOFF) = LDR_BASE_OFFSET<R8W, M8>;
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DEF_ISEL(LDRB_32BL_LDST_REGOFF) = LDR_BASE_OFFSET<R8W, M8>;
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DEF_ISEL(LDR_32_LOADLIT) = Load<R32W, M32>;
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DEF_ISEL(LDR_64_LOADLIT) = Load<R64W, M64>;
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DEF_ISEL(LDR_32_LDST_REGOFF) = LDR_BASE_OFFSET<R32W, M32>;
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DEF_ISEL(LDR_64_LDST_REGOFF) = LDR_BASE_OFFSET<R64W, M64>;
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DEF_ISEL(LDUR_32_LDST_UNSCALED) = Load<R32W, M32>;
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DEF_ISEL(LDUR_64_LDST_UNSCALED) = Load<R64W, M64>;
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//DEF_ISEL(MOV_ADD_32_ADDSUB_IMM) = Load<R32W, R32>;
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//DEF_ISEL(MOV_ADD_64_ADDSUB_IMM) = Load<R64W, R64>;
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//
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//DEF_ISEL(MOV_ORR_32_LOG_SHIFT) = Load<R32W, R32>;
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//DEF_ISEL(MOV_ORR_64_LOG_SHIFT) = Load<R64W, R64>;
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//
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//DEF_ISEL(MOV_ORR_32_LOG_IMM) = Load<R32W, I32>;
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//DEF_ISEL(MOV_ORR_64_LOG_IMM) = Load<R64W, I64>;
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//
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//DEF_ISEL(MOV_MOVZ_32_MOVEWIDE) = Load<R32W, I32>;
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//DEF_ISEL(MOV_MOVZ_64_MOVEWIDE) = Load<R64W, I64>;
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//
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//DEF_ISEL(MOV_MOVN_32_MOVEWIDE) = Load<R32W, I32>;
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//DEF_ISEL(MOV_MOVN_64_MOVEWIDE) = Load<R64W, I64>;
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DEF_ISEL(MOVZ_32_MOVEWIDE) = Load<R32W, I32>;
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DEF_ISEL(MOVZ_64_MOVEWIDE) = Load<R64W, I64>;
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namespace {
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template <typename D, typename S>
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DEF_SEM(MoveWithKeep, D dst, S src, I64 imm, I8 shift_) {
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auto shift = ZExtTo<uint64_t>(Read(shift_));
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auto val = UShl(Read(imm), shift);
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auto mask = UNot(UShl((0xFFFFULL), shift));
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auto reg = ZExtTo<uint64_t>(Read(src));
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WriteZExt(dst, UOr(UAnd(reg, mask), val));
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return memory;
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}
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} // namespace
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DEF_ISEL(MOVK_32_MOVEWIDE) = MoveWithKeep<R32W, R32>;
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DEF_ISEL(MOVK_64_MOVEWIDE) = MoveWithKeep<R64W, R64>;
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// Shifting and negating of the immediate happens in the post-decoder.
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DEF_ISEL(MOVN_32_MOVEWIDE) = Load<R32W, I32>;
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DEF_ISEL(MOVN_64_MOVEWIDE) = Load<R64W, I64>;
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namespace {
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DEF_SEM(ADRP, R64W dst, PC label) {
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addr_t label_addr = Read(label);
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// clear the bottom 12 bits of label_addr
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// to make this page aligned
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// the Post decoding already made the label page aligned
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// and added the label to PC
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// the semantics just needs to fix up for PC not being page aligned
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auto label_page = UAnd(UNot(static_cast<uint64_t>(4095)), label_addr);
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Write(dst, label_page);
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return memory;
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}
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} // namespace
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DEF_ISEL(ADRP_ONLY_PCRELADDR) = ADRP;
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DEF_ISEL(ADR_ONLY_PCRELADDR) = Load<R64W, I64>;
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namespace {
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DEF_SEM(LDR_B, V128W dst, MV8 src) {
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UWriteV8(dst, UReadV8(src));
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return memory;
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}
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DEF_SEM(LDR_H, V128W dst, MV16 src) {
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UWriteV16(dst, UReadV16(src));
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return memory;
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}
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DEF_SEM(LDR_S, V128W dst, MV32W src) {
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UWriteV32(dst, UReadV32(src));
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return memory;
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}
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DEF_SEM(LDR_D, V128W dst, MV64 src) {
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UWriteV64(dst, UReadV64(src));
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return memory;
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}
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DEF_SEM(LDR_Q, V128W dst, MV128 src) {
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UWriteV128(dst, UReadV128(src));
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return memory;
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}
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DEF_SEM(STR_B, V8 src, MV8W dst) {
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UWriteV8(dst, UReadV8(src));
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return memory;
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}
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DEF_SEM(STR_H, V16 src, MV16W dst) {
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UWriteV16(dst, UReadV16(src));
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return memory;
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}
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DEF_SEM(STR_S, V32 src, MV32W dst) {
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UWriteV32(dst, UReadV32(src));
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return memory;
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}
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DEF_SEM(STR_D, V64 src, MV64W dst) {
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UWriteV64(dst, UReadV64(src));
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return memory;
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}
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DEF_SEM(STR_Q, V128 src, MV128W dst) {
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UWriteV128(dst, UReadV128(src));
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return memory;
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}
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} // namespace
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DEF_ISEL(LDR_B_LDST_POS) = LDR_B;
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DEF_ISEL(LDR_H_LDST_POS) = LDR_H;
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DEF_ISEL(LDR_S_LDST_POS) = LDR_S;
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DEF_ISEL(LDR_D_LDST_POS) = LDR_D;
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DEF_ISEL(LDR_Q_LDST_POS) = LDR_Q;
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DEF_ISEL(STR_B_LDST_POS) = STR_B;
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DEF_ISEL(STR_H_LDST_POS) = STR_H;
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DEF_ISEL(STR_S_LDST_POS) = STR_S;
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DEF_ISEL(STR_D_LDST_POS) = STR_D;
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DEF_ISEL(STR_Q_LDST_POS) = STR_Q;
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