mirror of
https://github.com/lifting-bits/remill
synced 2026-06-21 13:56:07 +00:00
Peter Goodman
e1bdbdba9e
* Change copyright notice in all the places. Trying to get cmake to download all the things * CMake refactor * Added the lib repository installer * Fixed a couple of paths in library repository scripts * Spelling and a missing .gitignore file. * The google test library was not correctly linked * Removed the pre-compiled XED library * Removed unused files; fixed the INSTALL directives. Added automatic protobuf generation. * Added a package generator script for ArchLinux * Merged in Alessandro's cmake magic * Cleanups, compatibility changes * CMake cleanup. o Removed the cmake folder as it is no longer used. o Removed the library_repository_installer directory and replaced it with a submodule to the newly introduced cxx_common repository. o Added the 'use_remill_semantics' branch of mcsema as a submodule under tools/cmake. o Updated the README instructions (added --recursive to the git clone command). Warning: the mcsema submodule is pointing to my fork of the repository! * CMake: avoid re-defining the C/CXX/ASM compiler. This will prevent CMake from looping forever when using submodules. * The tools/mcsema submodule now points to the official repository. * mcsema submodule update * Updated the mcsema git submodule to track the newest changes. * Various CMake fixes (see details). o External include headers were not correctly marked as SYSTEM. This caused them to output warnings and break the build. o The PROJECT_SOURCE CMake variable has been replaced with CMAKE_SOURCE_DIR. o Updated the mcsema submodule to point to the latest CMake fixes. * Getting closer to having the test case runner work again without using the CFG protobufs. * Trying to make things use ubuntu clang/llvm packages * Update to the mcsema submodule. * Minor changes for llvm version compatibility * Test cases should run now. Had to compile the lifted testcases to a .S file, as with the .bc file, they were being optimized away.. I think. The compilation to assembly seems unusually slow, though. * Minor change * Some stuff for llvm 4.0 support * Remove mcsema sub-module * Remove cxx-common submodule * First steps toward getting travis working again * Attempt at getting travis working again * Using https for cloning instead of ssh * Minor build script update * Added ISEL_ prefix to isels to make it easier for ForEachISel to find them. Commented out the defer_inlining intrinsics. * Changes related to mcsema2 * Simplify runtime targets generation. (#110) * CMake refactor: Added a new language 'BC' for the bitcode (see details). The language is used to generate the runtimes used by the architecture modules. The required executables (clang++ and llvm-link) are automatically detected in the same way as other compilers are. A new CMake function has been added and it can be used to easily generate runtime targets in a way similar to add_executable: add_runtime(<name> SOURCE <source list> ADDRESS_SIZE <n> DEFINITIONS <definition list>) Additionally, all files ending with the *.bcpp extensions will automatically invoke the bitcode compiler when listed in an active target. This should open support for parallel compilation! You just have to list all your .cpp files when calling add_runtime. * CMake: Fixes to the BC language handler. * CMake/BC: Use '.bo' for object files. X86 runtime: Add -g/-O flags.
316 lines
10 KiB
C++
316 lines
10 KiB
C++
/*
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* Copyright (c) 2017 Trail of Bits, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "remill/Arch/X86/Runtime/State.h"
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extern "C" {
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Wunused-variable"
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// Method that will implement a basic block. We will clone this method for
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// each basic block in the code being lifted.
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[[gnu::used]]
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Memory *__remill_basic_block(Memory *memory, State &state, addr_t curr_pc) {
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bool branch_taken = false;
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addr_t zero = 0;
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// Note: These variables MUST be defined for all architectures.
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auto &STATE = state;
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auto &MEMORY = *memory;
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auto &PC = state.gpr.rip.IF_64BIT_ELSE(qword, dword);
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auto &BRANCH_TAKEN = branch_taken;
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// `PC` should already have the correct value, but it's nice to make sure
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// that `curr_pc` is used throughout, as it helps with certain downstream
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// uses to be able to depend on the optimizer not eliminating `curr_pc`.
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PC = curr_pc;
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// We will reference these variables from the bitcode side of things so that,
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// given a decoded register name and an operation type (read or write),
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// we can map the register to a specific field in the State structure.
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auto &AH = state.gpr.rax.byte.high;
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auto &BH = state.gpr.rbx.byte.high;
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auto &CH = state.gpr.rcx.byte.high;
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auto &DH = state.gpr.rdx.byte.high;
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auto &AL = state.gpr.rax.byte.low;
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auto &BL = state.gpr.rbx.byte.low;
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auto &CL = state.gpr.rcx.byte.low;
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auto &DL = state.gpr.rdx.byte.low;
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#if 64 == ADDRESS_SIZE_BITS
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auto &SIL = state.gpr.rsi.byte.low;
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auto &DIL = state.gpr.rdi.byte.low;
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auto &SPL = state.gpr.rsp.byte.low;
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auto &BPL = state.gpr.rbp.byte.low;
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auto &R8B = state.gpr.r8.byte.low;
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auto &R9B = state.gpr.r9.byte.low;
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auto &R10B = state.gpr.r10.byte.low;
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auto &R11B = state.gpr.r11.byte.low;
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auto &R12B = state.gpr.r12.byte.low;
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auto &R13B = state.gpr.r13.byte.low;
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auto &R14B = state.gpr.r14.byte.low;
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auto &R15B = state.gpr.r15.byte.low;
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#endif // 64 == ADDRESS_SIZE_BITS
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auto &AX = state.gpr.rax.word;
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auto &BX = state.gpr.rbx.word;
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auto &CX = state.gpr.rcx.word;
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auto &DX = state.gpr.rdx.word;
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auto &SI = state.gpr.rsi.word;
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auto &DI = state.gpr.rdi.word;
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auto &SP = state.gpr.rsp.word;
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auto &BP = state.gpr.rbp.word;
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#if 64 == ADDRESS_SIZE_BITS
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auto &R8W = state.gpr.r8.word;
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auto &R9W = state.gpr.r9.word;
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auto &R10W = state.gpr.r10.word;
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auto &R11W = state.gpr.r11.word;
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auto &R12W = state.gpr.r12.word;
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auto &R13W = state.gpr.r13.word;
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auto &R14W = state.gpr.r14.word;
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auto &R15W = state.gpr.r15.word;
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#endif // 64 == ADDRESS_SIZE_BITS
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auto &IP = state.gpr.rip.word;
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auto &EAX = state.gpr.rax.dword;
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auto &EBX = state.gpr.rbx.dword;
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auto &ECX = state.gpr.rcx.dword;
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auto &EDX = state.gpr.rdx.dword;
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auto &ESI = state.gpr.rsi.dword;
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auto &EDI = state.gpr.rdi.dword;
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auto &ESP = state.gpr.rsp.dword;
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auto &EBP = state.gpr.rbp.dword;
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auto &EIP = state.gpr.rip.dword;
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#if 64 == ADDRESS_SIZE_BITS
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auto &R8D = state.gpr.r8.dword;
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auto &R9D = state.gpr.r9.dword;
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auto &R10D = state.gpr.r10.dword;
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auto &R11D = state.gpr.r11.dword;
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auto &R12D = state.gpr.r12.dword;
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auto &R13D = state.gpr.r13.dword;
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auto &R14D = state.gpr.r14.dword;
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auto &R15D = state.gpr.r15.dword;
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auto &RAX = state.gpr.rax.qword;
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auto &RBX = state.gpr.rbx.qword;
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auto &RCX = state.gpr.rcx.qword;
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auto &RDX = state.gpr.rdx.qword;
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auto &RSI = state.gpr.rsi.qword;
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auto &RDI = state.gpr.rdi.qword;
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auto &RSP = state.gpr.rsp.qword;
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auto &RBP = state.gpr.rbp.qword;
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auto &R8 = state.gpr.r8.qword;
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auto &R9 = state.gpr.r9.qword;
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auto &R10 = state.gpr.r10.qword;
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auto &R11 = state.gpr.r11.qword;
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auto &R12 = state.gpr.r12.qword;
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auto &R13 = state.gpr.r13.qword;
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auto &R14 = state.gpr.r14.qword;
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auto &R15 = state.gpr.r15.qword;
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auto &RIP = state.gpr.rip.qword;
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#endif // 64 == ADDRESS_SIZE_BITS
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auto &SS = state.seg.ss;
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auto &ES = state.seg.es;
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auto &GS = state.seg.gs;
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auto &FS = state.seg.fs;
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auto &DS = state.seg.ds;
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auto &CS = state.seg.cs;
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auto &SS_BASE = zero;
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auto &ES_BASE = zero;
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auto &GS_BASE = state.addr.gs_base.IF_64BIT_ELSE(qword, dword);
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auto &FS_BASE = state.addr.fs_base.IF_64BIT_ELSE(qword, dword);
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auto &DS_BASE = zero;
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auto &CS_BASE = zero;
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#if HAS_FEATURE_AVX
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#if HAS_FEATURE_AVX512
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auto &ZMM0 = state.vec[0].zmm;
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auto &ZMM1 = state.vec[1].zmm;
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auto &ZMM2 = state.vec[2].zmm;
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auto &ZMM3 = state.vec[3].zmm;
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auto &ZMM4 = state.vec[4].zmm;
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auto &ZMM5 = state.vec[5].zmm;
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auto &ZMM6 = state.vec[6].zmm;
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auto &ZMM7 = state.vec[7].zmm;
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auto &ZMM8 = state.vec[8].zmm;
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auto &ZMM9 = state.vec[9].zmm;
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auto &ZMM10 = state.vec[10].zmm;
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auto &ZMM11 = state.vec[11].zmm;
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auto &ZMM12 = state.vec[12].zmm;
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auto &ZMM13 = state.vec[13].zmm;
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auto &ZMM14 = state.vec[14].zmm;
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auto &ZMM15 = state.vec[15].zmm;
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auto &ZMM16 = state.vec[16].zmm;
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auto &ZMM17 = state.vec[17].zmm;
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auto &ZMM18 = state.vec[18].zmm;
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auto &ZMM19 = state.vec[19].zmm;
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auto &ZMM20 = state.vec[20].zmm;
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auto &ZMM21 = state.vec[21].zmm;
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auto &ZMM22 = state.vec[22].zmm;
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auto &ZMM23 = state.vec[23].zmm;
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auto &ZMM24 = state.vec[24].zmm;
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auto &ZMM25 = state.vec[25].zmm;
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auto &ZMM26 = state.vec[26].zmm;
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auto &ZMM27 = state.vec[27].zmm;
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auto &ZMM28 = state.vec[28].zmm;
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auto &ZMM29 = state.vec[29].zmm;
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auto &ZMM30 = state.vec[30].zmm;
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auto &ZMM31 = state.vec[31].zmm;
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#endif // HAS_FEATURE_AVX512
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auto &YMM0 = state.vec[0].ymm;
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auto &YMM1 = state.vec[1].ymm;
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auto &YMM2 = state.vec[2].ymm;
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auto &YMM3 = state.vec[3].ymm;
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auto &YMM4 = state.vec[4].ymm;
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auto &YMM5 = state.vec[5].ymm;
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auto &YMM6 = state.vec[6].ymm;
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auto &YMM7 = state.vec[7].ymm;
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#if HAS_FEATURE_AVX || 64 == ADDRESS_SIZE_BITS
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auto &YMM8 = state.vec[8].ymm;
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auto &YMM9 = state.vec[9].ymm;
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auto &YMM10 = state.vec[10].ymm;
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auto &YMM11 = state.vec[11].ymm;
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auto &YMM12 = state.vec[12].ymm;
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auto &YMM13 = state.vec[13].ymm;
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auto &YMM14 = state.vec[14].ymm;
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auto &YMM15 = state.vec[15].ymm;
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#endif // HAS_FEATURE_AVX || 64 == ADDRESS_SIZE_BITS
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#if HAS_FEATURE_AVX512
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auto &YMM16 = state.vec[16].ymm;
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auto &YMM17 = state.vec[17].ymm;
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auto &YMM18 = state.vec[18].ymm;
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auto &YMM19 = state.vec[19].ymm;
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auto &YMM20 = state.vec[20].ymm;
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auto &YMM21 = state.vec[21].ymm;
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auto &YMM22 = state.vec[22].ymm;
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auto &YMM23 = state.vec[23].ymm;
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auto &YMM24 = state.vec[24].ymm;
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auto &YMM25 = state.vec[25].ymm;
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auto &YMM26 = state.vec[26].ymm;
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auto &YMM27 = state.vec[27].ymm;
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auto &YMM28 = state.vec[28].ymm;
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auto &YMM29 = state.vec[29].ymm;
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auto &YMM30 = state.vec[30].ymm;
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auto &YMM31 = state.vec[31].ymm;
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#endif // HAS_FEATURE_AVX512
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#endif // HAS_FEATURE_AVX
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auto &XMM0 = state.vec[0].xmm;
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auto &XMM1 = state.vec[1].xmm;
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auto &XMM2 = state.vec[2].xmm;
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auto &XMM3 = state.vec[3].xmm;
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auto &XMM4 = state.vec[4].xmm;
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auto &XMM5 = state.vec[5].xmm;
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auto &XMM6 = state.vec[6].xmm;
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auto &XMM7 = state.vec[7].xmm;
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#if HAS_FEATURE_AVX || 64 == ADDRESS_SIZE_BITS
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auto &XMM8 = state.vec[8].xmm;
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auto &XMM9 = state.vec[9].xmm;
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auto &XMM10 = state.vec[10].xmm;
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auto &XMM11 = state.vec[11].xmm;
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auto &XMM12 = state.vec[12].xmm;
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auto &XMM13 = state.vec[13].xmm;
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auto &XMM14 = state.vec[14].xmm;
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auto &XMM15 = state.vec[15].xmm;
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#endif // HAS_FEATURE_AVX || 64 == ADDRESS_SIZE_BITS
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#if HAS_FEATURE_AVX512
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auto &XMM16 = state.vec[16].xmm;
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auto &XMM17 = state.vec[17].xmm;
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auto &XMM18 = state.vec[18].xmm;
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auto &XMM19 = state.vec[19].xmm;
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auto &XMM20 = state.vec[20].xmm;
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auto &XMM21 = state.vec[21].xmm;
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auto &XMM22 = state.vec[22].xmm;
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auto &XMM23 = state.vec[23].xmm;
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auto &XMM24 = state.vec[24].xmm;
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auto &XMM25 = state.vec[25].xmm;
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auto &XMM26 = state.vec[26].xmm;
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auto &XMM27 = state.vec[27].xmm;
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auto &XMM28 = state.vec[28].xmm;
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auto &XMM29 = state.vec[29].xmm;
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auto &XMM30 = state.vec[30].xmm;
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auto &XMM31 = state.vec[31].xmm;
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#endif // HAS_FEATURE_AVX512
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auto &ST0 = state.st.elems[0].val;
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auto &ST1 = state.st.elems[1].val;
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auto &ST2 = state.st.elems[2].val;
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auto &ST3 = state.st.elems[3].val;
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auto &ST4 = state.st.elems[4].val;
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auto &ST5 = state.st.elems[5].val;
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auto &ST6 = state.st.elems[6].val;
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auto &ST7 = state.st.elems[7].val;
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#if 0 // TODO(pag): Don't emulate directly for now.
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#if 32 == ADDRESS_SIZE_BITS
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auto &FPU_LASTIP = state.fpu.u.x86.ip;
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auto &FPU_LASTIP = state.fpu.u.x86.ip;
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auto &FPU_LASTCS = state.fpu.u.x86.cs;
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auto &FPU_LASTCS = state.fpu.u.x86.cs;
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auto &FPU_LASTDP = state.fpu.u.x86.dp;
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auto &FPU_LASTDP = state.fpu.u.x86.dp;
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auto &FPU_LASTDS = state.fpu.u.x86.ds;
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auto &FPU_LASTDS = state.fpu.u.x86.ds;
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#else
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auto &FPU_LASTIP = state.fpu.u.amd64.ip;
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auto &FPU_LASTIP = state.fpu.u.amd64.ip;
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auto &FPU_LASTDP = state.fpu.u.amd64.dp;
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auto &FPU_LASTDP = state.fpu.u.amd64.dp;
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#endif
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#endif
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// MMX technology registers. For simplicity, these are implemented separately
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// from the FPU stack, and so they do not alias. This makes some things
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// easier and some things harder. Marshaling native/lifted state becomes
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// harder, but generating and optimizing bitcode becomes simpler. The trade-
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// off is that analysis and native states will diverge in strange ways
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// with code that mixes the two (X87 FPU ops, MMX ops).
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auto &MMX0 = state.mmx.elems[0].val.qwords.elems[0];
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auto &MMX1 = state.mmx.elems[1].val.qwords.elems[0];
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auto &MMX2 = state.mmx.elems[2].val.qwords.elems[0];
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auto &MMX3 = state.mmx.elems[3].val.qwords.elems[0];
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auto &MMX4 = state.mmx.elems[4].val.qwords.elems[0];
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auto &MMX5 = state.mmx.elems[5].val.qwords.elems[0];
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auto &MMX6 = state.mmx.elems[6].val.qwords.elems[0];
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auto &MMX7 = state.mmx.elems[7].val.qwords.elems[0];
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// Arithmetic flags. Data-flow analyses will clear these out ;-)
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auto &AF = state.aflag.af;
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auto &CF = state.aflag.cf;
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auto &DF = state.aflag.df;
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auto &OF = state.aflag.of;
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auto &PF = state.aflag.pf;
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auto &SF = state.aflag.sf;
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auto &ZF = state.aflag.zf;
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// Lifted code will be placed here in clones versions of this function.
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return nullptr;
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}
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#pragma clang diagnostic pop
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} // extern C
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#include "remill/Arch/Runtime/Intrinsics.cpp"
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