mirror of
https://github.com/revng/revng
synced 2026-06-21 14:07:57 +00:00
Alessandro Di Federico
1429b526ab
This commit drops libptc in favor of its new form libtcg. It brings several improvements, among which: * The QEMU version we work on has been upgraded. * CPUStateAccessAnalysis has been reimplemented in a way that makes it easier to debug and solves some limitations (e.g., tracking leaking pointers). * Identification of pieces of the CPU state that are read by each helper and fixing access to the CPU state is now performed at build-time. * We no longer mmap the code we need to translate, dropping all the issues related to code that needed to be mapped where something is already present. * We now have two distinct flavors of helper modules: the full one and the "slim" one. The latter contains the definition only of functions we intend to inline. It is used in most of the pipeline, a good thing since we spend less time optimizing code we don't really care about. The full module is only used on the re-compilation branch of the pipeline. * We no longer split the `cpu_loop` function. * We change MetaAddress to rely on architectures from `model::` as opposed to the LLVM ones. * We no longer attach debug info to LLVM IR containing the original assembly. * We now verify that the lifted code only contains code we expect.
411 lines
8.6 KiB
C++
411 lines
8.6 KiB
C++
#pragma once
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//
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// This file is distributed under the MIT License. See LICENSE.md for details.
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//
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#include "llvm/ADT/Triple.h"
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#include "revng/Model/Generated/Early/Architecture.h"
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namespace model::Architecture {
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inline bool isLittleEndian(Values V) {
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switch (V) {
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case model::Architecture::x86:
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case model::Architecture::x86_64:
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case model::Architecture::arm:
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case model::Architecture::aarch64:
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case model::Architecture::mipsel:
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return true;
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case model::Architecture::mips:
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case model::Architecture::systemz:
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return false;
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default:
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revng_abort();
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}
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}
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inline Values fromLLVMArchitecture(llvm::Triple::ArchType A) {
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switch (A) {
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case llvm::Triple::x86:
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return model::Architecture::x86;
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case llvm::Triple::x86_64:
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return model::Architecture::x86_64;
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case llvm::Triple::arm:
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return model::Architecture::arm;
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case llvm::Triple::aarch64:
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return model::Architecture::aarch64;
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case llvm::Triple::mips:
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return model::Architecture::mips;
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case llvm::Triple::mipsel:
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return model::Architecture::mipsel;
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case llvm::Triple::systemz:
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return model::Architecture::systemz;
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default:
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return model::Architecture::Invalid;
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}
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}
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inline llvm::Triple::ArchType toLLVMArchitecture(Values V) {
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switch (V) {
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case model::Architecture::x86:
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return llvm::Triple::x86;
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case model::Architecture::x86_64:
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return llvm::Triple::x86_64;
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case model::Architecture::arm:
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return llvm::Triple::arm;
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case model::Architecture::aarch64:
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return llvm::Triple::aarch64;
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case model::Architecture::mips:
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return llvm::Triple::mips;
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case model::Architecture::mipsel:
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return llvm::Triple::mipsel;
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case model::Architecture::systemz:
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return llvm::Triple::systemz;
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default:
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revng_abort();
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}
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}
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/// Return the size of the pointer in bytes
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constexpr inline uint64_t getPointerSize(Values V) {
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switch (V) {
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case model::Architecture::x86:
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case model::Architecture::arm:
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case model::Architecture::mips:
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case model::Architecture::mipsel:
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return 4;
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case model::Architecture::x86_64:
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case model::Architecture::aarch64:
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case model::Architecture::systemz:
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return 8;
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default:
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revng_abort();
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}
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}
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constexpr inline uint64_t getCallPushSize(Values V) {
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switch (V) {
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case x86:
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return 4;
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case x86_64:
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return 8;
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case arm:
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case mips:
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case mipsel:
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case aarch64:
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case systemz:
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return 0;
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default:
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revng_abort();
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}
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}
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constexpr inline llvm::ArrayRef<char> getBasicBlockEndingPattern(Values V) {
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switch (V) {
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case x86:
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case x86_64:
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return "\xcc";
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case arm:
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// bx lr
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return "\x1e\xff\x2f\xe1";
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case mips:
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// jr ra
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return "\x08\x00\xe0\x03";
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case mipsel:
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// jr ra
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return "\x03\xe0\x00\x08";
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case aarch64:
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// ret
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return "\xc0\x03\x5f\xd6";
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case systemz:
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// TODO
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return "";
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default:
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revng_abort();
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}
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}
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// TODO: this is libtinycode-specific
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constexpr inline llvm::StringRef getSyscallHelper(Values V) {
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switch (V) {
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case x86:
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return "helper_raise_interrupt";
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case x86_64:
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return "helper_syscall";
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case arm:
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case aarch64:
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return "helper_exception_with_syndrome";
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case mips:
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case mipsel:
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return "helper_raise_exception";
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case systemz:
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return "helper_exception";
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default:
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revng_abort();
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}
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}
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// TODO: this is libtinycode-specific
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inline llvm::ArrayRef<uint64_t> getNoReturnSyscallNumbers(Values V) {
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switch (V) {
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case x86: {
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static uint64_t NoReturnSyscalls[] = {
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0xfc, // exit_group
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0x01, // exit
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0x0b // execve
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};
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return NoReturnSyscalls;
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}
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case x86_64: {
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static uint64_t NoReturnSyscalls[] = {
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0xe7, // exit_group
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0x3c, // exit
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0x3b // execve
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};
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return NoReturnSyscalls;
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}
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case arm: {
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static uint64_t NoReturnSyscalls[] = {
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0xf8, // exit_group
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0x1, // exit
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0xb // execve
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};
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return NoReturnSyscalls;
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}
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case aarch64: {
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static uint64_t NoReturnSyscalls[] = {
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0x5e, // exit_group
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0x5d, // exit
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0xdd // execve
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};
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return NoReturnSyscalls;
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}
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case mips:
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case mipsel: {
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static uint64_t NoReturnSyscalls[] = {
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0x1096, // exit_group
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0xfa1, // exit
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0xfab // execve
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};
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return NoReturnSyscalls;
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}
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case systemz: {
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static uint64_t NoReturnSyscalls[] = {
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0xf8, // exit_group
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0x1, // exit
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0xb, // execve
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};
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return NoReturnSyscalls;
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}
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default:
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revng_abort();
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}
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}
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inline bool hasELFRelocationAddend(Values V) {
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switch (V) {
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case model::Architecture::x86_64:
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case model::Architecture::systemz:
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return true;
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case model::Architecture::x86:
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case model::Architecture::arm:
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case model::Architecture::aarch64:
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case model::Architecture::mips:
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case model::Architecture::mipsel:
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return false;
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default:
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revng_abort();
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}
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}
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inline llvm::StringRef getReadRegisterAssembly(Values V) {
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switch (V) {
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case model::Architecture::x86_64:
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return "movq %REGISTER, $0";
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case model::Architecture::systemz:
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case model::Architecture::x86:
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case model::Architecture::arm:
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case model::Architecture::aarch64:
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case model::Architecture::mips:
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case model::Architecture::mipsel:
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return "";
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default:
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revng_abort();
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}
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}
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inline llvm::StringRef getWriteRegisterAssembly(Values V) {
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switch (V) {
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case model::Architecture::x86_64:
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return "movq $0, %REGISTER";
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case model::Architecture::systemz:
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case model::Architecture::x86:
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case model::Architecture::arm:
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case model::Architecture::aarch64:
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case model::Architecture::mips:
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case model::Architecture::mipsel:
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return "";
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default:
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revng_abort();
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}
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}
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inline llvm::StringRef getJumpAssembly(Values V) {
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switch (V) {
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case model::Architecture::x86_64:
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return "jmpq *$0";
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case model::Architecture::systemz:
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case model::Architecture::x86:
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case model::Architecture::arm:
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case model::Architecture::aarch64:
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case model::Architecture::mips:
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case model::Architecture::mipsel:
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return "";
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default:
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revng_abort();
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}
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}
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llvm::StringRef getPCCSVName(Values V);
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inline llvm::StringRef getQEMUName(Values V) {
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switch (V) {
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case model::Architecture::x86_64:
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return "x86_64";
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case model::Architecture::systemz:
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return "s390x";
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case model::Architecture::x86:
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return "i386";
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case model::Architecture::arm:
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return "arm";
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case model::Architecture::aarch64:
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return "aarch64";
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case model::Architecture::mips:
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return "mips";
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case model::Architecture::mipsel:
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return "mipsel";
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default:
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revng_abort();
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}
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}
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inline Values fromQEMUName(llvm::StringRef Name) {
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if (Name == "x86_64")
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return model::Architecture::x86_64;
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else if (Name == "s390x")
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return model::Architecture::systemz;
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else if (Name == "i386")
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return model::Architecture::x86;
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else if (Name == "arm")
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return model::Architecture::arm;
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else if (Name == "aarch64")
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return model::Architecture::aarch64;
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else if (Name == "mips")
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return model::Architecture::mips;
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else if (Name == "mipsel")
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return model::Architecture::mipsel;
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else
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revng_abort();
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}
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inline unsigned getMinimalFinalStackOffset(Values V) {
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switch (V) {
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case model::Architecture::x86_64:
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return 8;
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case model::Architecture::x86:
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return 4;
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case model::Architecture::systemz:
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case model::Architecture::arm:
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case model::Architecture::aarch64:
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case model::Architecture::mips:
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case model::Architecture::mipsel:
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return 0;
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default:
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revng_abort();
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}
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}
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inline constexpr llvm::StringRef getAssemblyCommentIndicator(Values V) {
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switch (V) {
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case model::Architecture::x86:
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case model::Architecture::x86_64:
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case model::Architecture::mips:
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case model::Architecture::mipsel:
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case model::Architecture::systemz:
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return "#";
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case model::Architecture::arm:
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return "@";
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case model::Architecture::aarch64:
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return "//";
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default:
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revng_abort();
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}
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}
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inline constexpr llvm::StringRef getAssemblyLabelIndicator(Values V) {
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switch (V) {
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case model::Architecture::x86:
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case model::Architecture::x86_64:
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case model::Architecture::arm:
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case model::Architecture::aarch64:
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case model::Architecture::mips:
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case model::Architecture::mipsel:
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case model::Architecture::systemz:
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return ":";
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default:
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revng_abort();
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}
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}
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inline constexpr bool hasDelaySlot(Values V) {
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switch (V) {
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case model::Architecture::x86:
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case model::Architecture::x86_64:
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case model::Architecture::arm:
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case model::Architecture::aarch64:
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case model::Architecture::systemz:
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return false;
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case model::Architecture::mips:
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case model::Architecture::mipsel:
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return true;
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default:
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revng_abort();
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}
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}
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} // namespace model::Architecture
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#include "revng/Model/Generated/Late/Architecture.h"
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