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https://github.com/revng/revng
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250 lines
7.4 KiB
C++
250 lines
7.4 KiB
C++
//
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// Copyright rev.ng Srls. See LICENSE.md for details.
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//
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/// \file BitLiveness.cpp
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/// \brief In this file we model the transfer functions for the analysis.
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/// Each transfer function models the information flow of a function or of
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/// a special case of an instruction.
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/// In our case, `R = transferXyz(Ins, E)` means that for the instruction Ins
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/// if we assume that the first E bits of the result of the instruction
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/// are alive, then the first R bits of the operands are also alive
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#include <limits>
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/Casting.h"
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#include "revng/Support/Assert.h"
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#include "revng-c/TypeShrinking/BitLiveness.h"
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#include "revng-c/TypeShrinking/DataFlowGraph.h"
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namespace TypeShrinking {
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using BitVector = llvm::BitVector;
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using Instruction = llvm::Instruction;
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char TypeShrinking::BitLivenessPass::ID = 0;
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static llvm::RegisterPass<BitLivenessPass> X("bit-liveness",
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"Apply approximate bit liveness "
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"analysis",
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true,
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true);
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const uint32_t Top = std::numeric_limits<uint32_t>::max();
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bool isDataFlowSink(const Instruction *Ins) {
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if (Ins->mayHaveSideEffects()) {
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return true;
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}
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switch (Ins->getOpcode()) {
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case Instruction::Call:
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case Instruction::CallBr:
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case Instruction::Ret:
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case Instruction::Store:
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case Instruction::Br:
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case Instruction::IndirectBr:
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return true;
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default:
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return false;
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}
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}
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uint32_t getMaxOperandSize(Instruction *Ins) {
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uint32_t Max = 0;
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for (auto &Operand : Ins->operands()) {
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if (Operand->getType()->isIntegerTy())
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Max = std::max(Max, Operand->getType()->getIntegerBitWidth());
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else
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return Top;
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}
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return Max;
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}
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/// If Ins has an integer return type return its bitwidth
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/// else return top
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uint32_t getResultSize(Instruction *Ins) {
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uint32_t Size = Top;
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if (Ins->getType()->isIntegerTy()) {
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Size = std::min(Size, Ins->getType()->getIntegerBitWidth());
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}
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return Size;
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}
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/// A specialization of the transfer function for the and instruction
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/// In cases where one of the operands is a constant mask
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///
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/// example:
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/// `%1 = %0 & 0xff`
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///
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/// only the lower 8 bits of `%0` flow into `%1`, but if only the lower 4 bits
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/// of `%1` flow into a data flow sink, then only the lower 4 bits of `%0`
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/// will flow into the data flow sink
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uint32_t transferMask(const uint32_t &Element, const uint32_t &MaskIndex) {
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return std::min(Element, MaskIndex);
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}
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/// Transfer function for the and instruction
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///
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/// example:
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/// `%2 = %1 & %0
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///
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/// if none of the operands are constants
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/// then liveness of %1 and %0 = liveness of %2
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uint32_t transferAnd(Instruction *Ins, const uint32_t &Element) {
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revng_assert(Ins->getOpcode() == Instruction::And);
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uint32_t Result = Element;
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for (auto &Operand : Ins->operands()) {
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if (auto *ConstantOperand = llvm::dyn_cast<llvm::ConstantInt>(Operand)) {
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auto OperandValue = ConstantOperand->getUniqueInteger();
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auto MostSignificantBit = OperandValue.getBitWidth()
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- OperandValue.countLeadingZeros();
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Result = std::min(Result, transferMask(Element, MostSignificantBit));
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}
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}
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return Result;
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}
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/// Transfer function for the left shift instruction
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///
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/// example:
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/// `%2 = %1 << %0
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///
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/// if none of the operands are constants
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/// then every bit of %1 and %0 can be alive
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///
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/// if %0 is a constant, then the first E bits of %2 are the first E - %0
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/// bits of %1 padded with zeros
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uint32_t transferShiftLeft(Instruction *Ins, const uint32_t &Element) {
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uint32_t OperandSize = getMaxOperandSize(Ins);
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if (auto ConstOp = llvm::dyn_cast<llvm::ConstantInt>(Ins->getOperand(1))) {
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auto OpVal = ConstOp->getZExtValue();
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if (Element < OpVal)
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return 0;
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return Element - OpVal;
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}
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return OperandSize;
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}
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/// Transfer function for the logical right shift instruction
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///
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/// example:
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/// `%2 = %1 >>L %0
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///
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/// if none of the operands are constants
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/// then every bit of %1 and %0 can be alive
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///
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/// if %0 is a constant, then the first E bits of %2 come from the first E + %0
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/// bits of %1
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uint32_t transferLogicalShiftRight(Instruction *Ins, const uint32_t &Element) {
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uint32_t OperandSize = getMaxOperandSize(Ins);
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if (auto ConstOp = llvm::dyn_cast<llvm::ConstantInt>(Ins->getOperand(1))) {
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auto OpVal = ConstOp->getZExtValue();
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revng_assert(OpVal < Top);
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if (Top - OpVal < Element)
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return Top;
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return std::min(OperandSize, Element + (uint32_t) OpVal);
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}
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return OperandSize;
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}
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/// Transfer function for the arithmetical right shift instruction
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///
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/// example:
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/// `%2 = %1 >>A %0
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///
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/// if none of the operands are constants
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/// then every bit of %1 and %0 can be alive
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///
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/// if %0 is a constant, then the first E bits of %2 come from the first E + %0
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/// bits of %1
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uint32_t
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transferArithmeticalShiftRight(Instruction *Ins, const uint32_t &Element) {
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uint32_t OperandSize = getMaxOperandSize(Ins);
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if (auto ConstOp = llvm::dyn_cast<llvm::ConstantInt>(Ins->getOperand(1))) {
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auto OpVal = ConstOp->getZExtValue();
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revng_assert(OpVal < Top);
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if (Top - OpVal < Element)
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return Top;
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return std::min(OperandSize, Element + (uint32_t) OpVal);
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}
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return OperandSize;
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}
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/// Transfer function for the trunc instruction
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///
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/// example:
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/// `%2 = truncX(%1)
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///
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/// at most the lower X bits of %1 flow into %2
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uint32_t transferTrunc(Instruction *Ins, const uint32_t &Element) {
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return std::min(Element, Ins->getType()->getIntegerBitWidth());
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}
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/// Transfer function for the trunc instruction
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///
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/// example:
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/// `%2 = zext(%1)
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///
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/// at most all the bits in %1 flow into %2
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uint32_t transferZExt(Instruction *Ins, const uint32_t &Element) {
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return std::min(Element, getMaxOperandSize(Ins));
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}
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uint32_t
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BitLivenessAnalysis::applyTransferFunction(DataFlowNode *L, const uint32_t E) {
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auto *Ins = L->Instruction;
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uint32_t Input = E;
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// At most every bit of the result is alive
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if (!isDataFlowSink(Ins)) {
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Input = std::min(E, getResultSize(Ins));
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}
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switch (Ins->getOpcode()) {
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case Instruction::And:
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return transferAnd(Ins, E);
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case Instruction::Xor:
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case Instruction::Or:
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case Instruction::Add:
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case Instruction::Sub:
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case Instruction::Mul:
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return std::min(E, getMaxOperandSize(L->Instruction));
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case Instruction::Shl:
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return transferShiftLeft(Ins, E);
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case Instruction::LShr:
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return transferLogicalShiftRight(Ins, E);
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case Instruction::AShr:
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return transferArithmeticalShiftRight(Ins, E);
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case Instruction::Trunc:
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return transferTrunc(Ins, E);
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case Instruction::ZExt:
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return transferZExt(Ins, E);
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default:
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// By default all the bits of the operands can be alive
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return Top;
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}
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}
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bool BitLivenessPass::runOnFunction(llvm::Function &F) {
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DataFlowGraph = buildDataFlowGraph(F);
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std::vector<DataFlowNode *> ExtremalLabels;
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for (DataFlowNode *Node : DataFlowGraph.nodes()) {
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if (isDataFlowSink(Node->Instruction)) {
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ExtremalLabels.push_back(Node);
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}
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}
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Result = getMaximalFixedPoint<BitLivenessAnalysis>(&DataFlowGraph,
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0,
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Top,
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ExtremalLabels);
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return false;
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}
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} // namespace TypeShrinking
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