 SaberAlterr
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11d9dbb7b7
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[RISC-V Vector]Add 128-bit fixed-width SIMD layer (#2472)
* Fix riscv intrinsics header missing SIMDJSON_CONDITIONAL_INCLUDE guard
Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
* Fix riscv intrinsics header missing SIMDJSON_CONDITIONAL_INCLUDE guard
Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
* Implement simd8/simd8x64 with RVV intrinsics and fallback bitmanipulation
Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
* Fix missing SIMDJSON_CONDITIONAL_INCLUDE guard
Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
* Fix missing SIMDJSON_CONDITIONAL_INCLUDE guard
Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
---------
Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
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2025-09-26 12:51:37 -04:00 |
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SaberAlterr
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896fb5d6a5
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[RISC-V Vector] Add initial 128-bit SIMD layer and fix intrinsics header (#2469)
* Fix riscv intrinsics header missing SIMDJSON_CONDITIONAL_INCLUDE guard
Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
* Fix riscv intrinsics header missing SIMDJSON_CONDITIONAL_INCLUDE guard
Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
* Fix intrinsics header and add 128-bit SIMD layer
Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
---------
Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
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2025-09-24 14:48:59 -04:00 |
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SaberAlterr
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e3d3b4b5a4
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[RISC-V Vector] Stage1 Intrinsics and SIMD Namespace Implementation for RVV Optimization (#2455)
* implement rvv/intrinsics.h for dynamic vector length
Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
* Fix riscv intrinsics header missing SIMDJSON_CONDITIONAL_INCLUDE guard
Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
* Fix riscv intrinsics header missing SIMDJSON_CONDITIONAL_INCLUDE guard
Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
---------
Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
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2025-09-18 09:17:13 -06:00 |
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SaberAlterr
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7068894be3
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[RISC-V Vector] Add RVV Backend Registration (#2430)
* WIP: initial RVV implementation
Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
* Fix issue with SIMDJSON_CONDITIONAL_INCLUDE in rvv/implementation.h
Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
* drop RISC-V V-extension auto-detection in cmake
- Remove CMake logic that adds -DSIMDJSON_IS_RVV=1.
- Let SIMDJSON_IS_RVV be determined by portability.h.
- Translate placeholder comment to English.
Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
* fixing amalgamation.
Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
* adding base
Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
---------
Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
Co-authored-by: Daniel Lemire <daniel@lemire.me>
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2025-09-14 08:14:41 -06:00 |
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