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https://github.com/simdjson/simdjson
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SaberAlterr
11d9dbb7b7
* Fix riscv intrinsics header missing SIMDJSON_CONDITIONAL_INCLUDE guard Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn> * Fix riscv intrinsics header missing SIMDJSON_CONDITIONAL_INCLUDE guard Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn> * Implement simd8/simd8x64 with RVV intrinsics and fallback bitmanipulation Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn> * Fix missing SIMDJSON_CONDITIONAL_INCLUDE guard Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn> * Fix missing SIMDJSON_CONDITIONAL_INCLUDE guard Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn> --------- Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
20 lines
440 B
C++
20 lines
440 B
C++
#ifndef SIMDJSON_RVV_BASE_H
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#define SIMDJSON_RVV_BASE_H
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#ifndef SIMDJSON_CONDITIONAL_INCLUDE
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#include "simdjson/base.h"
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#endif // SIMDJSON_CONDITIONAL_INCLUDE
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namespace simdjson {
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namespace rvv {
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class implementation;
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namespace {
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namespace simd {
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template <typename T> struct simd8;
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template <typename T> struct simd8x64;
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} // namespace simd
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} // unnamed namespace
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} // namespace rvv
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} // namespace simdjson
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#endif // SIMDJSON_RVV_BASE_H
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