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SaberAlterr 11d9dbb7b7 [RISC-V Vector]Add 128-bit fixed-width SIMD layer (#2472) 
* Fix riscv intrinsics header missing SIMDJSON_CONDITIONAL_INCLUDE guard

Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>

* Fix riscv intrinsics header missing SIMDJSON_CONDITIONAL_INCLUDE guard

Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>

* Implement simd8/simd8x64 with RVV intrinsics and fallback bitmanipulation

Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>

* Fix missing SIMDJSON_CONDITIONAL_INCLUDE guard

Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>

* Fix missing SIMDJSON_CONDITIONAL_INCLUDE guard

Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>

---------

Co-authored-by: gong-flying <gongxiaofei24@iscas.ac.cn>
2025-09-26 12:51:37 -04:00
..
simdjson
[RISC-V Vector]Add 128-bit fixed-width SIMD layer (#2472)
2025-09-26 12:51:37 -04:00
simdjson.h
This is a small reorg of the new convert code so that we only expose 'simdjson::from' as experimental (#2418)
2025-08-15 15:13:36 -04:00