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https://github.com/simdjson/simdjson
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strager
5510089d45
* Rename simdjson_really_inline -> simdjson_inline I want to change the simdjson_really_inline macro to sometimes not force inlining. After that upcoming change, the name simdjson_really_inline will no longer makes sense. Rename simdjson_really_inline to simdjson_inline. This patch should not change semantics; simdjson_inline still forces inlining as before. Some functions still need to be really inlined for ABI reasons. (GCC's -Wpsabi complains otherwise.) Leave those functions marked as simdjson_really_inline. * Improve build times for debug builds simdjson_inline is used for most simdjson functions. It forces inlining. In unoptimized/debug builds, this can lead to a lot of machine code being generated (especially with Address Sanitizer), causing slow compilation. Change simdjson_inline to force inlining only for optimized builds. Sometimes, the programmer might want a slightly-optimized build and want fast compilation (e.g. GCC's -Og mode). Allow simdjson users to define the simdjson_inline macro themselves (e.g. on the command line: -Dsimdjson_inline=inline) in cases where the default behavior is undesired. This patch reduced build times by over 75% for ondemand_object_tests.cpp with GCC 9.4.0 and CMAKE_BUILD_TYPE=Debug on my AMD 5950X: Before: 6.885 6.683 6.971 6.957 6.949 seconds (5 samples) After: 1.492 1.551 1.494 1.490 1.531 seconds (5 samples)
41 lines
1.2 KiB
C++
41 lines
1.2 KiB
C++
#ifndef SIMDJSON_ARM64_BITMASK_H
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#define SIMDJSON_ARM64_BITMASK_H
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namespace simdjson {
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namespace SIMDJSON_IMPLEMENTATION {
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namespace {
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//
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// Perform a "cumulative bitwise xor," flipping bits each time a 1 is encountered.
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//
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// For example, prefix_xor(00100100) == 00011100
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//
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simdjson_inline uint64_t prefix_xor(uint64_t bitmask) {
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/////////////
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// We could do this with PMULL, but it is apparently slow.
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//
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//#ifdef __ARM_FEATURE_CRYPTO // some ARM processors lack this extension
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//return vmull_p64(-1ULL, bitmask);
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//#else
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// Analysis by @sebpop:
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// When diffing the assembly for src/stage1_find_marks.cpp I see that the eors are all spread out
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// in between other vector code, so effectively the extra cycles of the sequence do not matter
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// because the GPR units are idle otherwise and the critical path is on the FP side.
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// Also the PMULL requires two extra fmovs: GPR->FP (3 cycles in N1, 5 cycles in A72 )
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// and FP->GPR (2 cycles on N1 and 5 cycles on A72.)
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///////////
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bitmask ^= bitmask << 1;
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bitmask ^= bitmask << 2;
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bitmask ^= bitmask << 4;
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bitmask ^= bitmask << 8;
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bitmask ^= bitmask << 16;
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bitmask ^= bitmask << 32;
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return bitmask;
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}
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} // unnamed namespace
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} // namespace arm64
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} // namespace simdjson
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#endif
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