c01f431536
rv64: Add support for Zba, Zbb, Zbc, Zbs ( #14 )
2024-06-17 10:47:10 +02:00
3e84ecbca9
tests/x86-64: Adjust address for 64k page systems
2024-06-07 17:11:12 +02:00
e5f04c93b2
Fix LLVM 16-18 build and bump to LLVM 16
2024-06-07 17:05:42 +02:00
837fabd8ad
frvdec: Update for Zba, Zbb, Zbc, Zbs support
2024-06-07 15:53:02 +02:00
0a574bbe1c
basicblock: Replace std::vector with SmallVector
...
Most blocks have few predecessors, so avoid two extra heap allocations
for every block.
2024-05-17 11:12:28 +02:00
cba18d5106
x86-64: BSF/BSR with zero source don't modify dest
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This is specified on AMD and apparently the same on Intel. glibc makes
use of this fact.
2024-05-17 11:07:21 +02:00
c13eb03b0e
basicblock: Unify register file creation
2024-05-10 12:10:20 +02:00
cbc0f586bb
callconv: Correct unpack block after control flow
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The begin block is not always the correct continuation point for a new
register file.
2024-05-10 11:56:57 +02:00
2214e91740
general: Drop non-Arch-BasicBlock
2024-04-30 11:03:08 +02:00
3d8bd82cfb
tests/x86-64: Add more string operation tests
2024-04-29 18:02:36 +02:00
f93808f59f
decoder: Use SmallVector
2024-04-24 17:49:37 +02:00
b08bd07977
llvm: Add support for LLVM 18
2024-04-24 17:49:23 +02:00
f4baf89b35
rv64: Implement LR.D/SC.D non-atomically
2024-04-24 17:42:43 +02:00
9e7ce6af46
x86-64/sse: Fix packed shift with immediate
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The facet is ignored for immediate operands, causing the generation of
invalid LLVM-IR.
2024-04-24 17:41:59 +02:00
f1f2bf21e4
x86-64/sse: Implement PSIGNB/PSIGNW/PSIGND
2024-02-02 16:56:32 +01:00
210fabeb57
x86-64/sse: Implement PALIGNR
2024-02-02 15:40:12 +01:00
055bc94231
x86-64/sse: Unify SseBinOp and SseHorzOp
2024-02-02 15:03:33 +01:00
2c7dc5ac67
x86-64/sse: Implement PHADDSW/PHSUBSW
2024-02-02 15:01:08 +01:00
4651a3fd34
x86-64/sse: Move horz-to-vert to separate function
2024-02-02 15:00:30 +01:00
d5219885c8
x86-64/sse: Implement PMADDUBSW
2024-02-02 12:08:13 +01:00
8b1736e34c
x86-64: Implement POPCNT
2024-02-01 16:19:44 +01:00
f15eca94c6
callconv: Hoist stores out of merge blocks
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This gives some performance improvements and avoids executing stores on
some code paths where a register is not modified.
2024-01-31 15:34:31 +01:00
c859f11960
x86-64/sse: Handle zero-idiom for SSE registers
2024-01-29 15:54:21 +01:00
e8c4be2881
basicblock: Remove unnecessary no-op cast
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With opaque pointer types, this can never happen.
2024-01-20 13:54:32 +01:00
b29d5e285e
aarch64: Compute some flags lazily
2024-01-20 13:54:32 +01:00
6bbdf9796f
x86-64/flags: Compute ADD OF lazily
2024-01-20 13:54:24 +01:00
296bd05750
regfile: Handle PC specially
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PC is not an ordinary register and has strong connections to the lifted
CFG. Avoid relying on information encoded in (unused) LLVM-IR
instructions for lifting and store this explicitly.
2024-01-20 13:39:39 +01:00
caa79d127c
general: Remove compatibility with LLVM < 15
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We require opaque pointers already, so we don't need compatibility
hacks.
2024-01-17 20:44:50 +01:00
a8207825cd
tests/driver: Adjust for LLVM 18 API break
2024-01-17 19:36:39 +01:00
b476ce638c
tests/x86-64: Add test for MOVNTDQ
2024-01-17 19:36:34 +01:00
ff40e3a9a4
basicblock: Use cheaper assertion
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Getting actual predecessors is fairly expensive, so use out predecessor
list instead.
2024-01-17 19:35:48 +01:00
d4cf4283a8
x86-64/sse: Simplify MOVSS/MOVSD code
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If the regfile does the register merging, access to lower parts is more
efficient, as the extra extraction can be avoided.
2024-01-17 19:13:49 +01:00
05df75eb5c
regfile: Simplify set function naming
2024-01-17 19:11:28 +01:00
df3ab9d8bf
regfile: Remove unnecessary clear method
2024-01-17 18:56:43 +01:00
28e7868081
rv64: Simplify StoreFp for new regfile
2024-01-17 18:44:17 +01:00
ce823a063e
rv64: Fix CFG for syscall
2024-01-17 18:44:03 +01:00
f6a23e0d1a
aarch64: Simplify SetScalar for new regfile
2024-01-17 18:39:08 +01:00
48b7919e2c
tests/driver: Fix output of expected and actual
2024-01-17 18:02:59 +01:00
c21fc8feb1
x86-64/gp: Improve generated code for LEA
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Avoid generating additions with zero or multiplications with one.
2024-01-17 18:02:08 +01:00
b9ac916a1d
regfile: Use bit or pointer cast
2024-01-17 18:01:18 +01:00
c67d0d500e
regfile: Fix types of lshr
2024-01-17 18:01:07 +01:00
add6268c65
x86-64: Compute carry flag lazily
2024-01-17 14:07:36 +01:00
43803d6820
regfile: Copy all values from single predecessor
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This avoids useless extensions or merges.
2024-01-17 13:30:06 +01:00
e5a02924d5
regfile: Avoid indirection to register storage
2024-01-15 15:24:10 +01:00
186040f941
callconv: Omit undef stores
2024-01-15 15:16:27 +01:00
1ba3a33380
basicblock: Avoid phi nodes for exit block
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When the exit block has a single predecessor, there's no need to
generate phi nodes for that.
2024-01-15 15:15:51 +01:00
290cda4117
x86-64/gp: Special-case XOR zero idiom
2024-01-15 14:28:31 +01:00
bd491c3412
x86-64/gp: Optimize XOR+DIV and CQO+IDIV sequences
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Most divisions aren't actually 128 bits, so avoid generating such large
divisions in the first place.
2024-01-15 14:28:31 +01:00
27f3d5a59a
regfile: Cache extracted facets
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This avoids redundant extractions of the same value
2024-01-15 14:28:31 +01:00
edc4b9e619
regfile: Minor refactoring
2024-01-15 14:28:31 +01:00
Timofey Frolov