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[pre-commit.ci] pre-commit autoupdate (#407)

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* [pre-commit.ci] pre-commit autoupdate

updates:
- [github.com/astral-sh/ruff-pre-commit: v0.5.1 → v0.5.2](https://github.com/astral-sh/ruff-pre-commit/compare/v0.5.1...v0.5.2)

* Fix ruff errors

---------

Co-authored-by: pre-commit-ci[bot] <66853113+pre-commit-ci[bot]@users.noreply.github.com>
Co-authored-by: Kevin Phoenix <kevin@kphoenix.us>
This commit is contained in:
pre-commit-ci[bot]
2024-07-15 12:59:16 -07:00
committed by GitHub
parent 7b4122c87f
commit add7ccfdf7
2 changed files with 2 additions and 2 deletions
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.pre-commit-config.yaml
+1 -1
View File
@@ -66,7 +66,7 @@ repos:
args: [--py310-plus]
- repo: https://github.com/astral-sh/ruff-pre-commit
rev: v0.5.1
rev: v0.5.2
hooks:
- id: ruff
args: [--fix, --exit-non-zero-on-fix]
tests/test_pyvex.py
+1 -1
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@@ -76,7 +76,7 @@ class TestPyvex(unittest.TestCase):
def test_irsb_arm(self):
irsb = pyvex.IRSB(data=b"\x33\xff\x2f\xe1", mem_addr=0, arch=pyvex.ARCH_ARM_BE)
assert len([i for i in irsb.statements if type(i) == pyvex.IRStmt.IMark]) == 1
assert len([i for i in irsb.statements if isinstance(i, pyvex.IRStmt.IMark)]) == 1
def test_irsb_popret(self):
irsb = pyvex.IRSB(data=b"\x5d\xc3", mem_addr=0, arch=pyvex.ARCH_AMD64)