* pyvex_c: widen HashHW value slot to ULong
HashHW (lifted from libvex/ir_opt.c) caches (IR-temp -> resolved
constant) bindings during data_ref extraction. Values were typed
HWord (= unsigned long, host-pointer-width). On 32-bit hosts that's
4 bytes, but the guest can be 64-bit (AMD64, AArch64), so cached
guest pointers were silently truncated.
Symptom on wasm32-emscripten with an AMD64 guest: pyvex.lift returns
data_addr=0x6320 for a load whose actual target is 0x100006320 (high
32 bits dropped). Native x86-64 SysV hides the bug because long is
64-bit there.
Fix: store HashHW values as ULong unconditionally. Keys are
pyvex-internal IR-temp identifiers and can stay HWord.
Adds tests/test_data_refs_64bit_target.py to lock in the expected
value.
Fixes#539
* [pre-commit.ci] auto fixes from pre-commit.com hooks
for more information, see https://pre-commit.ci
* tests: drop archinfo dep, add class docstring
archinfo isn't a pyvex test dependency, so the new test failed to
collect on all CI runners. Use the bundled pyvex.ARCH_AMD64 constant
instead. Also add the class docstring that the ecosystem lint flagged.
---------
Co-authored-by: pre-commit-ci[bot] <66853113+pre-commit-ci[bot]@users.noreply.github.com>
Co-authored-by: Brian Caswell <brian@demoray.net>
* ARM: Don't rewrite blcc default jumpkind
* [pre-commit.ci] auto fixes from pre-commit.com hooks
for more information, see https://pre-commit.ci
---------
Co-authored-by: pre-commit-ci[bot] <66853113+pre-commit-ci[bot]@users.noreply.github.com>
* plugins 2: no more plugins
* homebrew arches
* lint
* I think this is related to thumb mode?
* Remove archinfo from tests
* Remove archinfo from setup.cfg
* Fix fuzzing
* Fix ARM32 -> ARM
* Fix missing closing brace in PyvexArch.__repr__
* Get register offsets directly from vex_ffi
* Fix test cases failures related to little endian instructions
* Resore riscv64le
* Also in __init__.py
* Add subregister map
* Fix another test
* Don't treat rMSR r value as a vex offset, treat it as a register
* Fix remaining failing test cases
* Add some backwards compatibility for register indicies
* Revert _lookup_register to original behaviour
* Fix arch name
* Fix registers with vex_name
* Fix LDM instruction using register numbers
---------
Co-authored-by: Kevin Phoenix <kevin@kphoenix.us>
* Add multiplatform CI
* Checkout vex on windows
* Fix workflow files
* Add pytest-xdist to testing deps
* Skip angr tests if angr is not installed
* Missed one
* Skip resources test on non-linux
* Refactor PyVEX to pass lint
* Re-add irop_enums_to_ints to pyvex namespace
* Replace log.trace with log.debug
* Register lifters in one place instead of relying on lifter import order
* Fix pylint errors
* Rename lift.py to lift_function.py
See https://github.com/angr/angr/pull/1092 for more details.
* The initial commit.
* Redo the lifting logic to avoid redundant IRSB copying.
* Move get_defaultexit_target() from Python to C to speed things up.
* Add a check to make sure LibVEX_Lift() does not return NULL.
* Implement IRSB.instruction_addresses.
* Implement IRSB.has_statements.
* Fix IRSB.addr.
* Fix a NULL-deref in pyvex.c.
* Postprocessor: Do not remove NoOp statements.
Otherwise it will cause a mismatch between statement indices and the
indices in IRSB.exit_statements (which are generated in PyVEX C).
* FixesPostProcessor: Get the IRSB address correctly.
* Remove NoOp statements in the C world.
* Restore the IRSB size calculation.
* Make sure exit_statements is not None before accessing.
* Enable tests for PyVEX itself.
* Implement ARM call jumpkind fixer in C for a better performance.
* Implement MIPS32 post-processing in C world.
* Add a missing undefine.
* Fix test.py.
* Add stddef.h to pyvex.c.
* Implement data reference collection in pyvex_c.
* Lint the code.
* Expose PyVEXError.
* More linting.
* oops
* Expose get_type_size and get_type_spec_size.
* Expose IRTypeEnv.
* Postprocessor: Support NeedStatementsNotification.
* Reorganize lifting/__init__.py.
* Remove the IRSB.addr property, replace with raw attribute
* Make check against MAX_DATA_REFS more explicit
* Move from data ref tuples to a DataRef class
* Lint block.py: Define data_refs and _instruction_addresses in __init__
* Make pyvex.lift positional arguments match pyvex.IRSB
* The kosher way to do this is .lift()
* Split pyvex.c into several smaller C files
(committing as fish to preserve authorship)
* Lifter: Do not extend a basic block if the lifter intentionally ends it with a NoDecode.
The rationale behind is that we want to differentiate between NoDecode
that are caused by unsupported instructions and NoDecode caused by
decodeable instructions. For example, `ud2` is a valid instruction on X86
and AMD64, but it means "undefined instruction". On AMD64, VEX will create
a basic block that has an instruction of two bytes (which is the size of
the ud2 instruction), but with the `next` of the basic block pointing to
that instruction. In our existing implementation, we will ignore ud2 and
keep lifting, which is an incorrect behavior.
This commit will detect these intentional NoDecode cases. In such cases,
the Lifter will return a basic block that terminates after the
"undecodeable" instruction, with NoDecode as the jumpkind.
* Add a test case.
* Rename .lift to .lifting to avoid the lift() method shadowing the lift module.
* Tidy the code and make future development easier.
- Remove all absolute import of pyvex.
- Remove all absolute import of Python modules that should be relative
imports.
- Split lifting.__init__.py into separate files.
- Delay an import from angr to avoid circular import.
Brian Caswell