mirror of
https://github.com/angr/pyvex
synced 2026-06-21 13:47:01 +00:00
Audrey Dutcher
0f32e9dbb7
* plugins 2: no more plugins * homebrew arches * lint * I think this is related to thumb mode? * Remove archinfo from tests * Remove archinfo from setup.cfg * Fix fuzzing * Fix ARM32 -> ARM * Fix missing closing brace in PyvexArch.__repr__ * Get register offsets directly from vex_ffi * Fix test cases failures related to little endian instructions * Resore riscv64le * Also in __init__.py * Add subregister map * Fix another test * Don't treat rMSR r value as a vex offset, treat it as a register * Fix remaining failing test cases * Add some backwards compatibility for register indicies * Revert _lookup_register to original behaviour * Fix arch name * Fix registers with vex_name * Fix LDM instruction using register numbers --------- Co-authored-by: Kevin Phoenix <kevin@kphoenix.us>
31 lines
883 B
Python
31 lines
883 B
Python
# pylint: disable=missing-class-docstring
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import unittest
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import pyvex
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class Tests(unittest.TestCase):
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def test_x86_aam(self):
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irsb = pyvex.lift(b"\xd4\x0b", 0, pyvex.ARCH_X86)
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self.assertEqual(irsb.jumpkind, "Ijk_Boring")
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self.assertEqual(irsb.size, 2)
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def test_x86_aad(self):
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irsb = pyvex.lift(b"\xd5\x0b", 0, pyvex.ARCH_X86)
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self.assertEqual(irsb.jumpkind, "Ijk_Boring")
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self.assertEqual(irsb.size, 2)
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def test_x86_xgetbv(self):
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irsb = pyvex.lift(b"\x0f\x01\xd0", 0, pyvex.ARCH_X86)
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self.assertEqual(irsb.jumpkind, "Ijk_Boring")
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self.assertEqual(irsb.size, 3)
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def test_x86_rdmsr(self):
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irsb = pyvex.lift(b"\x0f\x32", 0, pyvex.ARCH_X86)
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self.assertEqual(irsb.jumpkind, "Ijk_Boring")
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self.assertEqual(irsb.size, 2)
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if __name__ == "__main__":
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unittest.main()
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