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https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
Check that hardware sequencing is enabled (#86)
This commit is contained in:
committed by
c7zero
parent
08dd602a9d
commit
647ed5cf33
@@ -480,6 +480,13 @@ class SPI:
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return cycle_done
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def check_hardware_sequencing(self):
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# Test if the flash decriptor is valid (and hardware sequencing enabled)
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fdv = chipsec.chipset.read_register_field(self.cs, 'HSFS', 'FDV')
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if fdv == 0:
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logger().error("HSFS.FDV is 0, hardware sequencing is disabled")
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raise SpiRuntimeError("Chipset does not support hardware sequencing")
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#
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# SPI Flash operations
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#
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@@ -500,6 +507,9 @@ class SPI:
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#return self.write_spi( spi_fla, struct.unpack('B'*len(buf), buf) )
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def read_spi(self, spi_fla, data_byte_count ):
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self.check_hardware_sequencing()
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buf = []
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dbc = SPI_READ_WRITE_DEF_DBC
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if (data_byte_count >= SPI_READ_WRITE_MAX_DBC):
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@@ -550,6 +560,9 @@ class SPI:
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return buf
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def write_spi(self, spi_fla, buf ):
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self.check_hardware_sequencing()
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write_ok = True
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data_byte_count = len(buf)
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dbc = 4
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@@ -590,6 +603,9 @@ class SPI:
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return write_ok
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def erase_spi_block(self, spi_fla ):
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self.check_hardware_sequencing()
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if logger().UTIL_TRACE or logger().VERBOSE:
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logger().log( "[spi] Erasing SPI Flash block @ 0x%X" % spi_fla )
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@@ -194,6 +194,7 @@ class SPIHelper(TestHelper):
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RCBA_ADDR = 0xFED0000
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SPIBAR_ADDR = RCBA_ADDR + 0x3800
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SPIBAR_END = SPIBAR_ADDR + 0x200
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HSFS = SPIBAR_ADDR + 0x4
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FRAP = SPIBAR_ADDR + 0x50
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FREG0 = SPIBAR_ADDR + 0x54
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LPC_BRIDGE_DEVICE = (0, 0x1F, 0)
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@@ -218,6 +219,8 @@ class SPIHelper(TestHelper):
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return 0x00020002
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elif pa == self.FRAP:
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return 0xEEEEEEEE
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elif pa == self.HSFS:
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return (1 << 14) # FDV = 1, the flash descriptor is valid
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elif pa >= self.SPIBAR_ADDR and pa < self.SPIBAR_END:
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return 0x0
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else:
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