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Adding public processor information.

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This commit is contained in:
Erik Bjorge
2017-05-02 19:41:54 -07:00
committed by johnloucaides
parent d6ee2baaaa
commit 6a1735ab94
2 changed files with 216 additions and 2 deletions
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chipsec/cfg/bdx.xml
+202
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@@ -0,0 +1,202 @@
<?xml version="1.0"?>
<configuration platform="BDX" >
<!-- XML configuration file for Broadwell Server based platforms
-->
<pci>
<device name="IMC0_MAIN_SMBUS" bus="1" dev="19" fun="0" vid="0x8086" />
<device name="IMC1_MAIN_SMBUS" bus="1" dev="22" fun="0" vid="0x8086" />
</pci>
<mmio>
<bar name="MMCFG" bus="0" dev="5" fun="0" reg="0x90" width="8" mask="0x7FFFFFC000000" size="0x1000" desc="PCI Express Register Range"/>
<bar name="DMIBAR" bus="0" dev="0" fun="0" reg="0x50" width="4" mask="0xFFFFF000" size="0x1000" enable_bit="0" desc="Root Complex Register Range"/>
</mmio>
<io>
</io>
<memory>
</memory>
<registers>
<!-- Host Controller -->
<register name="DMIRCBAR" type="pcicfg" bus="0" dev="0" fun="0" offset="0x50" size="4" desc="DMI Root Complex Register Block Base Address">
<field name="dmircbaren" bit="0" size="1" desc="Enable DMIRCBAR"/>
<field name="dmircbar" bit="12" size="20" desc="Base address DMI Root Complex register space"/>
</register>
<register name="TSEG" type="pcicfg" bus="0" dev="5" fun="0" offset="0xA8" size="8" desc="TSEG Memory">
<field name="base" bit="20" size="12" desc="Base address"/>
<field name="limit" bit="52" size="12" desc="Limit address"/>
</register>
<register name="TSEG_BASE" type="pcicfg" bus="0" dev="5" fun="0" offset="0xA8" size="4" desc="TSEG Memory Base">
<field name="base" bit="20" size="12" desc="Base address"/>
</register>
<register name="TSEG_LIMIT" type="pcicfg" bus="0" dev="5" fun="0" offset="0xAC" size="4" desc="TSEG Memory Limit">
<field name="limit" bit="20" size="12" desc="Limit address"/>
</register>
<register name="VTBAR" type="mmcfg" bus="0" dev="5" fun="0" offset="0x180" size="4" desc="VT BAR Register">
<field name="Enable" bit="0" size="1" desc="Enable"/>
<field name="Base" bit="13" size="19" desc="VTD Base Address"/>
</register>
<register name="VTGENCTRL" type="mmcfg" bus="0" dev="5" fun="0" offset="0x184" size="4" desc="VTGENCTRL Register">
<field name="gpa_limit" bit="0" size="4" desc="Guest virtual addressing limit"/>
<field name="hpa_limit" bit="4" size="4" desc="Host processor addressing limit"/>
<field name="lockvtd" bit="15" size="1" desc="lockvtd"/>
</register>
<register name="LTDPR" type="mmcfg" bus="0" dev="5" fun="0" offset="0x290" size="4" desc="Intel TXT DMA Protected Range Register">
<field name="lock" bit="0" size="1" desc="Lock LTDPR register"/>
<field name="protregsts" bit="1" size="1" desc="Protection enabled in HW"/>
<field name="commandbit" bit="2" size="1" desc="Command bit"/>
<field name="size" bit="4" size="8" desc="Size of memory"/>
<field name="topofdpr" bit="20" size="12" desc="Top address +1 of DPR"/>
</register>
<!-- GENPROTRANGE Registers -->
<register name="GENPROTRANGE1_BASE" type="pcicfg" bus="0" dev="5" fun="0" offset="0xB0" size="8" desc="Generic Protected Memory Range 1 Base Address">
<field name="base_address" bit="16" size="35" desc="GENPROTRANGE 1 base address"/>
</register>
<register name="GENPROTRANGE1_LIMIT" type="pcicfg" bus="0" dev="5" fun="0" offset="0xB8" size="8" desc="Generic Protected Memory Range 1 Limit Address">
<field name="limit_address" bit="16" size="35" desc="GENPROTRANGE 1 limit address"/>
</register>
<register name="GENPROTRANGE2_BASE" type="pcicfg" bus="0" dev="5" fun="0" offset="0xC0" size="8" desc="Generic Protected Memory Range 2 Base Address">
<field name="base_address" bit="16" size="35" desc="GENPROTRANGE 2 base address"/>
</register>
<register name="GENPROTRANGE2_LIMIT" type="pcicfg" bus="0" dev="5" fun="0" offset="0xC8" size="8" desc="Generic Protected Memory Range 2 Limit Address">
<field name="limit_address" bit="16" size="35" desc="GENPROTRANGE 2 limit address"/>
</register>
<register name="GENPROTRANGE0_BASE" type="mmcfg" bus="0" dev="5" fun="0" offset="0x120" size="8" desc="Generic Protected Memory Range 0 Base Address">
<field name="base_address" bit="16" size="35" desc="GENPROTRANGE 0 base address"/>
</register>
<register name="GENPROTRANGE0_LIMIT" type="mmcfg" bus="0" dev="5" fun="0" offset="0x128" size="8" desc="Generic Protected Memory Range 0 Limit Address">
<field name="limit_address" bit="16" size="35" desc="GENPROTRANGE 0 limit address"/>
</register>
<!-- Integrated Memory Controller 0 -->
<register name="IMC0_SMBSTAT_0" type="mmcfg" bus="1" dev="19" fun="0" offset="0x180" size="4" desc="SMBus Host Status">
<field name="RDATA" bit="0" size="16" desc="Read Data" />
<field name="TSOD_SA" bit="24" size="4" desc="Last Issued TSOD Slave Address" />
<field name="BUSY" bit="28" size="1" desc="SMBus Busy" />
<field name="SBE" bit="29" size="1" desc="SMBus Error/Failed" />
<field name="WOD" bit="30" size="1" desc="Write Operation Done" />
<field name="RDO" bit="31" size="1" desc="Read Data Valid" />
</register>
<register name="IMC0_SMBCMD_0" type="mmcfg" bus="1" dev="19" fun="0" offset="0x184" size="4" desc="SMBus Host Command">
<field name="WDATA" bit="0" size="16" desc="Write Data" />
<field name="BA" bit="16" size="8" desc="Bus Transaction Address" />
<field name="SA" bit="24" size="3" desc="Slave Address" />
<field name="WRT_CMD" bit="27" size="1" desc="Read/Write Command" />
<field name="WRT_PNTR" bit="28" size="1" desc="Write Pointer" />
<field name="WORD_ACCESS" bit="29" size="1" desc="Word Access" />
<field name="PNTR_SEL" bit="30" size="1" desc="Pointer Select" />
<field name="CMD_TRIGGER" bit="31" size="1" desc="Start/Trigger" />
</register>
<register name="IMC0_SMBCNTL_0" type="mmcfg" bus="1" dev="19" fun="0" offset="0x188" size="4" desc="SMBus Host Control">
<field name="DTI" bit="28" size="4" desc="Device Type Identifier" />
</register>
<register name="IMC0_SMBSTAT_1" type="mmcfg" bus="1" dev="19" fun="0" offset="0x190" size="4" desc="SMBus Host Status 1">
<field name="RDATA" bit="0" size="16" desc="Read Data" />
<field name="TSOD_SA" bit="24" size="4" desc="Last Issued TSOD Slave Address" />
<field name="BUSY" bit="28" size="1" desc="SMBus Busy" />
<field name="SBE" bit="29" size="1" desc="SMBus Error/Failed" />
<field name="WOD" bit="30" size="1" desc="Write Operation Done" />
<field name="RDO" bit="31" size="1" desc="Read Data Valid" />
</register>
<register name="IMC0_SMBCMD_1" type="mmcfg" bus="1" dev="19" fun="0" offset="0x194" size="4" desc="SMBus Host Command 1">
<field name="WDATA" bit="0" size="16" desc="Write Data" />
<field name="BA" bit="16" size="8" desc="Bus Transaction Address" />
<field name="SA" bit="24" size="3" desc="Slave Address" />
<field name="WRT_CMD" bit="27" size="1" desc="Read/Write Command" />
<field name="WRT_PNTR" bit="28" size="1" desc="Write Pointer" />
<field name="WORD_ACCESS" bit="29" size="1" desc="Word Access" />
<field name="PNTR_SEL" bit="30" size="1" desc="Pointer Select" />
<field name="CMD_TRIGGER" bit="31" size="1" desc="Start/Trigger" />
</register>
<register name="IMC0_SMBCNTL_1" type="mmcfg" bus="1" dev="19" fun="0" offset="0x198" size="4" desc="SMBus Host Control 1">
<field name="DTI" bit="28" size="4" desc="Device Type Identifier" />
</register>
<!-- Integrated Memory Controller 1 -->
<register name="IMC1_SMBSTAT_0" type="mmcfg" bus="1" dev="22" fun="0" offset="0x180" size="4" desc="SMBus Host Status">
<field name="RDATA" bit="0" size="16" desc="Read Data" />
<field name="TSOD_SA" bit="24" size="4" desc="Last Issued TSOD Slave Address" />
<field name="BUSY" bit="28" size="1" desc="SMBus Busy" />
<field name="SBE" bit="29" size="1" desc="SMBus Error/Failed" />
<field name="WOD" bit="30" size="1" desc="Write Operation Done" />
<field name="RDO" bit="31" size="1" desc="Read Data Valid" />
</register>
<register name="IMC1_SMBCMD_0" type="mmcfg" bus="1" dev="22" fun="0" offset="0x184" size="4" desc="SMBus Host Command">
<field name="WDATA" bit="0" size="16" desc="Write Data" />
<field name="BA" bit="16" size="8" desc="Bus Transaction Address" />
<field name="SA" bit="24" size="3" desc="Slave Address" />
<field name="WRT_CMD" bit="27" size="1" desc="Read/Write Command" />
<field name="WRT_PNTR" bit="28" size="1" desc="Write Pointer" />
<field name="WORD_ACCESS" bit="29" size="1" desc="Word Access" />
<field name="PNTR_SEL" bit="30" size="1" desc="Pointer Select" />
<field name="CMD_TRIGGER" bit="31" size="1" desc="Start/Trigger" />
</register>
<register name="IMC1_SMBCNTL_0" type="mmcfg" bus="1" dev="22" fun="0" offset="0x188" size="4" desc="SMBus Host Control">
<field name="DTI" bit="28" size="4" desc="Device Type Identifier" />
</register>
<register name="IMC1_SMBSTAT_1" type="mmcfg" bus="1" dev="22" fun="0" offset="0x190" size="4" desc="SMBus Host Status 1">
<field name="RDATA" bit="0" size="16" desc="Read Data" />
<field name="TSOD_SA" bit="24" size="4" desc="Last Issued TSOD Slave Address" />
<field name="BUSY" bit="28" size="1" desc="SMBus Busy" />
<field name="SBE" bit="29" size="1" desc="SMBus Error/Failed" />
<field name="WOD" bit="30" size="1" desc="Write Operation Done" />
<field name="RDO" bit="31" size="1" desc="Read Data Valid" />
</register>
<register name="IMC1_SMBCMD_1" type="mmcfg" bus="1" dev="22" fun="0" offset="0x194" size="4" desc="SMBus Host Command 1">
<field name="WDATA" bit="0" size="16" desc="Write Data" />
<field name="BA" bit="16" size="8" desc="Bus Transaction Address" />
<field name="SA" bit="24" size="3" desc="Slave Address" />
<field name="WRT_CMD" bit="27" size="1" desc="Read/Write Command" />
<field name="WRT_PNTR" bit="28" size="1" desc="Write Pointer" />
<field name="WORD_ACCESS" bit="29" size="1" desc="Word Access" />
<field name="PNTR_SEL" bit="30" size="1" desc="Pointer Select" />
<field name="CMD_TRIGGER" bit="31" size="1" desc="Start/Trigger" />
</register>
<register name="IMC1_SMBCNTL_1" type="mmcfg" bus="1" dev="22" fun="0" offset="0x198" size="4" desc="SMBus Host Control 1">
<field name="DTI" bit="28" size="4" desc="Device Type Identifier" />
</register>
<!-- LPC Interface Bridge -->
<register name="GEN_PMCON_LOCK" type="pcicfg" bus="0" dev="0x1F" fun="0" offset="0xA6" size="1" desc="General Power Management Configuration Lock">
<field name="ACPI_BASE_LOCK" bit="1" size="1" desc="Lock down ACPI Base Address (ABASE)"/>
<field name="SLP_STR_POL_LOCK" bit="2" size="1" desc="SLP Stretching Policy Lock-Down"/>
</register>
<!-- PCH Root Complex Register Base MMIO registers -->
<!-- PCH ABASE (PMBASE) I/O registers -->
<register name="SMI_EN" type="iobar" bar="ABASE" offset="0x30" size="4" desc="SMI Control and Enable">
<field name="GBL_SMI_EN" bit="0" size="1"/>
<field name="EOS" bit="1" size="1"/>
<field name="BIOS_EN" bit="2" size="1"/>
<field name="LEGACY_USB_EN" bit="3" size="1"/>
<field name="SLP_SMI_EN" bit="4" size="1"/>
<field name="APMC_EN" bit="5" size="1"/>
<field name="SWSMI_TMR_EN" bit="6" size="1"/>
<field name="BIOS_RLS" bit="7" size="1"/>
<field name="MCSMI_EN" bit="11" size="1"/>
<field name="TCO_EN" bit="13" size="1"/>
<field name="PERIODIC_EN" bit="14" size="1"/>
<field name="LEGACY_USB2_EN" bit="17" size="1"/>
<field name="INTEL_USB2_EN" bit="18" size="1"/>
<field name="GPIO_UNLOCK_SMI_EN" bit="27" size="1"/>
<field name="ME_SMI_EN" bit="30" size="1"/>
<field name="xHCI_SMI_EN" bit="31" size="1"/>
</register>
<!-- CPU Model Specific Registers -->
</registers>
</configuration>
chipsec/chipset.py
+14 -2
View File
@@ -84,6 +84,7 @@ CHIPSET_ID_SKL = 11
CHIPSET_ID_BSW = 12
CHIPSET_ID_KBL = 13
CHIPSET_ID_CHT = 14
CHIPSET_ID_BDX = 15
CHIPSET_CODE_COMMON = 'COMMON'
CHIPSET_CODE_UNKNOWN = ''
@@ -102,8 +103,9 @@ CHIPSET_CODE_SKL = 'SKL'
CHIPSET_CODE_BSW = 'BSW'
CHIPSET_CODE_KBL = 'KBL'
CHIPSET_CODE_CHT = 'CHT'
CHIPSET_CODE_BDX = 'BDX'
CHIPSET_FAMILY_XEON = [CHIPSET_ID_JKT,CHIPSET_ID_IVT,CHIPSET_ID_HSX]
CHIPSET_FAMILY_XEON = [CHIPSET_ID_JKT,CHIPSET_ID_IVT,CHIPSET_ID_HSX,CHIPSET_ID_BDX]
CHIPSET_FAMILY_CORE = [CHIPSET_ID_SNB,CHIPSET_ID_IVB,CHIPSET_ID_HSW,CHIPSET_ID_BDW,CHIPSET_ID_SKL,CHIPSET_ID_KBL]
CHIPSET_FAMILY_ATOM = [CHIPSET_ID_BYT,CHIPSET_ID_AVN,CHIPSET_CODE_BSW,CHIPSET_CODE_CHT]
CHIPSET_FAMILY_QUARK = [CHIPSET_ID_QRK]
@@ -157,13 +159,24 @@ Chipset_Dictionary = {
# 7th Generation Core Processor Family (Kabylake)
0x5904 : {'name' : 'Kabylake', 'id' : CHIPSET_ID_KBL , 'code' : CHIPSET_CODE_KBL, 'longname' : 'Mobile 7th Generation Core Processor (Kabylake U)' },
0x590C : {'name' : 'Kabylake', 'id' : CHIPSET_ID_KBL , 'code' : CHIPSET_CODE_KBL, 'longname' : 'Mobile 7th Generation Core Processor (Kabylake Y)' },
0x591F : {'name' : 'Kabylake', 'id' : CHIPSET_ID_KBL , 'code' : CHIPSET_CODE_KBL, 'longname' : 'Desktop 7th Generation Core Processor (Kabylake S)' },
# Xeon v3 Processor (Haswell Server)
0x2F00 : {'name' : 'Haswell Server', 'id' : CHIPSET_ID_HSX, 'code' : CHIPSET_CODE_HSX, 'longname' : 'Server 4th Generation Core Processor (Haswell Server CPU / Wellsburg PCH)'},
# Xeon v4 Processor (Broadwell Server)
0x1618 : {'name' : 'Broadwell Server', 'id' : CHIPSET_ID_BDW , 'code' : CHIPSET_CODE_BDW, 'longname' : 'Intel Xeon Processor E3 v4 (Broadwell CPU)' },
0x6F00 : {'name' : 'Broadwell Server', 'id' : CHIPSET_ID_BDX, 'code' : CHIPSET_CODE_BDX, 'longname' : 'Intel Xeon Processor E5/E7 v4 (Broadwell Server CPU / Wellsburg PCH)'},
# Xeon v5 Processor (Skylake Server)
0x1918 : {'name' : 'Skylake Server', 'id' : CHIPSET_ID_SKL, 'code' : CHIPSET_CODE_SKL, 'longname' : 'Intel Xeon Processor E3 v5 (Skylake CPU / Sunrise Point PCH)'},
# Xeon v6 Processor (Kabylake Server)
0x5900 : {'name' : 'Kabylake','id' : CHIPSET_ID_KBL , 'code' : CHIPSET_CODE_KBL, 'longname' : 'Intel Xeon Processor E3 v6 (Kabylake CPU)' },
0x590F : {'name' : 'Kabylake','id' : CHIPSET_ID_KBL , 'code' : CHIPSET_CODE_KBL, 'longname' : 'Intel Xeon Processor E3 v6 (Kabylake CPU)' },
0x5910 : {'name' : 'Kabylake','id' : CHIPSET_ID_KBL , 'code' : CHIPSET_CODE_KBL, 'longname' : 'Intel Xeon Processor E3 v6 (Kabylake CPU)' },
0x5918 : {'name' : 'Kabylake','id' : CHIPSET_ID_KBL , 'code' : CHIPSET_CODE_KBL, 'longname' : 'Intel Xeon Processor E3 v6 (Kabylake CPU)' },
#
# Atom based SoC platforms
#
@@ -199,7 +212,6 @@ Chipset_Dictionary = {
# Galileo Board
0x0958 : {'name' : 'Galileo ', 'id' : CHIPSET_ID_QRK , 'code' : CHIPSET_CODE_QRK, 'longname' : 'Intel Quark SoC X1000' },
}
try:
from custom_chipsets import *