mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
Session 1 extractions
This commit is contained in:
Dan Scott
+228
-157
@@ -23,7 +23,7 @@ Contains platform identification functions
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"""
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import errno
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import traceback
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from typing import Union
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from typing import Any, Dict, Optional, Tuple, Union
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from chipsec.helper.oshelper import helper as os_helper
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from chipsec.helper.basehelper import Helper
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@@ -231,22 +231,29 @@ class Chipset:
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"""Check support for multiple architecture VIDs"""
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return self.Cfg.vid in arch_vid
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def init_cfg_bus(self):
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def init_cfg_bus(self) -> None:
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logger().log_debug('[*] Loading device buses..')
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old_log_state = (False, False, False)
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if QUIET_PCI_ENUM:
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old_log_state = (logger().HAL, logger().DEBUG, logger().VERBOSE)
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logger().HAL, logger().DEBUG, logger().VERBOSE = (False, False, False)
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logger().setlevel()
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old_log_state = self.save_log_state()
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self.set_log_state((False, False, False))
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try:
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enum_devices = self.pci.enumerate_devices()
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except Exception:
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logger().log_debug('[*] Unable to enumerate PCI devices.')
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enum_devices = []
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if QUIET_PCI_ENUM:
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logger().HAL, logger().DEBUG, logger().VERBOSE = old_log_state
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logger().setlevel()
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self.set_log_state(old_log_state)
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self.Cfg.set_pci_data(enum_devices)
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def set_log_state(self, log_state: Tuple[bool, bool, bool]) -> None:
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logger().HAL, logger().DEBUG, logger().VERBOSE = log_state
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logger().setlevel()
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def save_log_state(self) -> Tuple[bool, bool, bool]:
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old_log_state = (logger().HAL, logger().DEBUG, logger().VERBOSE)
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return old_log_state
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##################################################################################
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#
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@@ -363,41 +370,53 @@ class Chipset:
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return False
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else:
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return True
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def get_pci_register_def(self, reg_def: Dict[str, Any], dev_name: str) -> Dict[str, Any]:
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if dev_name in self.Cfg.CONFIG_PCI:
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dev = self.Cfg.CONFIG_PCI[dev_name]
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reg_def['bus'] = self.get_first_bus(dev)
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reg_def['dev'] = dev['dev']
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reg_def['fun'] = dev['fun']
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return reg_def
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def get_memory_register_def(self, reg_def: Dict[str, Any], dev_name: str) -> Dict[str, Any]:
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if dev_name in self.Cfg.MEMORY_RANGES:
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dev = self.Cfg.MEMORY_RANGES[dev_name]
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reg_def['address'] = dev['address']
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reg_def['access'] = dev['access']
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else:
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logger().log_error(f'Memory device {dev_name} not found')
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return reg_def
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def get_register_def(self, reg_name):
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def get_indirect_register_def(self, reg_def: Dict[str, Any], dev_name: str) -> Dict[str, Any]:
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if dev_name in self.Cfg.IMA_REGISTERS:
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dev = self.Cfg.IMA_REGISTERS[dev_name]
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if ('base' in dev):
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reg_def['base'] = dev['base']
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else:
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reg_def['base'] = "0"
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if (dev['index'] in self.Cfg.REGISTERS):
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reg_def['index'] = dev['index']
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else:
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logger().log_error(f'Index register {dev["index"]} not found')
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if (dev['data'] in self.Cfg.REGISTERS):
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reg_def['data'] = dev['data']
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else:
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logger().log_error(f'Data register {dev["data"]} not found')
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else:
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logger().log_error(f'Indirect access device {dev_name} not found')
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return reg_def
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def get_register_def(self, reg_name: str):
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reg_def = self.Cfg.REGISTERS[reg_name]
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if "device" in reg_def:
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dev_name = reg_def["device"]
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if reg_def["type"] in ["pcicfg", "mmcfg"]:
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if dev_name in self.Cfg.CONFIG_PCI:
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dev = self.Cfg.CONFIG_PCI[dev_name]
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reg_def['bus'] = self.get_first_bus(dev)
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reg_def['dev'] = dev['dev']
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reg_def['fun'] = dev['fun']
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reg_def = self.get_pci_register_def(reg_def, dev_name)
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elif reg_def["type"] == "memory":
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if dev_name in self.Cfg.MEMORY_RANGES:
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dev = self.Cfg.MEMORY_RANGES[dev_name]
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reg_def['address'] = dev['address']
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reg_def['access'] = dev['access']
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else:
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logger().log_error(f'Memory device {dev_name} not found')
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reg_def = self.get_memory_register_def(reg_def, dev_name)
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elif reg_def["type"] == "indirect":
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if dev_name in self.Cfg.IMA_REGISTERS:
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dev = self.Cfg.IMA_REGISTERS[dev_name]
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if ('base' in dev):
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reg_def['base'] = dev['base']
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else:
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reg_def['base'] = "0"
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if (dev['index'] in self.Cfg.REGISTERS):
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reg_def['index'] = dev['index']
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else:
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logger().log_error(f'Index register {dev["index"]} not found')
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if (dev['data'] in self.Cfg.REGISTERS):
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reg_def['data'] = dev['data']
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else:
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logger().log_error(f'Data register {dev["data"]} not found')
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else:
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logger().log_error(f'Indirect access device {dev_name} not found')
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reg_def = self.get_indirect_register_def(reg_def, dev_name)
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return reg_def
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def get_register_bus(self, reg_name):
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@@ -431,71 +450,98 @@ class Chipset:
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logger().log_important(f"No bus value defined for device '{dev_name}'")
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return buses
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def read_register(self, reg_name, cpu_thread=0, bus=None, do_check=True):
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def read_pci_register(self, bus: Optional[int], reg: Dict[str, Any], rtype: str, do_check: bool) -> int:
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reg_value = 0
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if bus is not None:
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b = self.get_first(bus)
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else:
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b = self.get_first_bus(reg)
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d = reg['dev']
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f = reg['fun']
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o = reg['offset']
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size = reg['size']
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if do_check and self.consistency_checking:
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if self.pci.get_DIDVID(b, d, f) == (0xFFFF, 0xFFFF):
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raise CSReadError(f'PCI Device is not available ({b}:{d}.{f})')
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if RegisterType.PCICFG == rtype:
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if 1 == size:
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reg_value = self.pci.read_byte(b, d, f, o)
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elif 2 == size:
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reg_value = self.pci.read_word(b, d, f, o)
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elif 4 == size:
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reg_value = self.pci.read_dword(b, d, f, o)
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elif 8 == size:
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reg_value = (self.pci.read_dword(b, d, f, o + 4) << 32) | self.pci.read_dword(b, d, f, o)
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elif RegisterType.MMCFG == rtype:
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reg_value = self.mmio.read_mmcfg_reg(b, d, f, o, size)
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return reg_value
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def read_mmio_register(self, bus: Optional[int], reg: Dict[str, Any]) -> int:
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_bus = bus
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if self.mmio.get_MMIO_BAR_base_address(reg['bar'], _bus)[0] != 0:
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reg_value = self.mmio.read_MMIO_BAR_reg(reg['bar'], reg['offset'], reg['size'], _bus)
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else:
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raise CSReadError(f'MMIO Bar ({reg["bar"]}) base address is 0')
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return reg_value
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def read_msr_register(self, cpu_thread: int, reg: Dict[str, Any]) -> int:
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(eax, edx) = self.msr.read_msr(cpu_thread, reg['msr'])
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return (edx << 32) | eax
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def read_portio_register(self, reg: Dict[str, Any]) -> int:
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port = reg['port']
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size = reg['size']
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return self.io._read_port(port, size)
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def read_iobar_register(self, reg: Dict[str, Any]) -> int:
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if self.iobar.get_IO_BAR_base_address(reg['bar'])[0] != 0:
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reg_value = self.iobar.read_IO_BAR_reg(reg['bar'], reg['offset'], reg['size'])
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else:
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raise CSReadError(f'IO Bar ({reg["bar"]}) base address is 0')
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return reg_value
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def read_memory_register(self, reg: Dict[str, Any]) -> int:
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reg_value = 0
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if reg['access'] == 'dram':
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size = reg['size']
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if 1 == size:
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reg_value = self.mem.read_physical_mem_byte(reg['address'])
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elif 2 == size:
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reg_value = self.mem.read_physical_mem_word(reg['address'])
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elif 4 == size:
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reg_value = self.mem.read_physical_mem_dword(reg['address'])
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elif 8 == size:
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reg_value = self.mem.read_physical_mem_qword(reg['address'])
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elif reg['access'] == 'mmio':
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reg_value = self.mmio.read_MMIO_reg(reg['address'], reg['offset'], reg['size'])
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return reg_value
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def read_ima_regsiter(self, reg: Dict[str, Any]) -> int:
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self.write_register(reg['index'], reg['offset'] + reg['base'])
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return self.read_register(reg['data'])
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def read_register(self, reg_name, cpu_thread=0, bus=None, do_check=True) -> int:
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reg = self.get_register_def(reg_name)
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rtype = reg['type']
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reg_value = 0
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if (RegisterType.PCICFG == rtype) or (RegisterType.MMCFG == rtype):
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if bus is not None:
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b = self.get_first(bus)
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else:
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b = self.get_first_bus(reg)
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d = reg['dev']
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f = reg['fun']
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o = reg['offset']
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size = reg['size']
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if do_check and self.consistency_checking:
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if self.pci.get_DIDVID(b, d, f) == (0xFFFF, 0xFFFF):
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raise CSReadError(f'PCI Device is not available ({b}:{d}.{f})')
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if RegisterType.PCICFG == rtype:
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if 1 == size:
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reg_value = self.pci.read_byte(b, d, f, o)
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elif 2 == size:
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reg_value = self.pci.read_word(b, d, f, o)
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elif 4 == size:
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reg_value = self.pci.read_dword(b, d, f, o)
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elif 8 == size:
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reg_value = (self.pci.read_dword(b, d, f, o + 4) << 32) | self.pci.read_dword(b, d, f, o)
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elif RegisterType.MMCFG == rtype:
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reg_value = self.mmio.read_mmcfg_reg(b, d, f, o, size)
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elif RegisterType.MMIO == rtype:
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_bus = bus
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if self.mmio.get_MMIO_BAR_base_address(reg['bar'], _bus)[0] != 0:
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reg_value = self.mmio.read_MMIO_BAR_reg(reg['bar'], reg['offset'], reg['size'], _bus)
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else:
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raise CSReadError(f'MMIO Bar ({reg["bar"]}) base address is 0')
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elif RegisterType.MSR == rtype:
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(eax, edx) = self.msr.read_msr(cpu_thread, reg['msr'])
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reg_value = (edx << 32) | eax
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elif RegisterType.PORTIO == rtype:
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port = reg['port']
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size = reg['size']
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reg_value = self.io._read_port(port, size)
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elif RegisterType.IOBAR == rtype:
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if self.iobar.get_IO_BAR_base_address(reg['bar'])[0] != 0:
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reg_value = self.iobar.read_IO_BAR_reg(reg['bar'], reg['offset'], reg['size'])
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else:
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raise CSReadError(f'IO Bar ({reg["bar"]}) base address is 0')
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elif RegisterType.MSGBUS == rtype:
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if (rtype == RegisterType.PCICFG) or (rtype == RegisterType.MMCFG):
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reg_value = self.read_pci_register(bus, reg, rtype, do_check)
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elif rtype == RegisterType.MMIO:
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reg_value = self.read_mmio_register(bus, reg)
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elif rtype == RegisterType.MSR:
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reg_value = self.read_msr_register(cpu_thread, reg)
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elif rtype == RegisterType.PORTIO:
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reg_value = self.read_portio_register(reg)
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elif rtype == RegisterType.IOBAR:
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reg_value = self.read_iobar_register(reg)
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elif rtype == RegisterType.MSGBUS:
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reg_value = self.msgbus.msgbus_reg_read(reg['port'], reg['offset'])
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elif RegisterType.MM_MSGBUS == rtype:
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elif rtype == RegisterType.MM_MSGBUS:
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reg_value = self.msgbus.mm_msgbus_reg_read(reg['port'], reg['offset'])
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elif RegisterType.MEMORY == rtype:
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if reg['access'] == 'dram':
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size = reg['size']
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if 1 == size:
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reg_value = self.mem.read_physical_mem_byte(reg['address'])
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elif 2 == size:
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reg_value = self.mem.read_physical_mem_word(reg['address'])
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elif 4 == size:
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reg_value = self.mem.read_physical_mem_dword(reg['address'])
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elif 8 == size:
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reg_value = self.mem.read_physical_mem_qword(reg['address'])
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elif reg['access'] == 'mmio':
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reg_value = self.mmio.read_MMIO_reg(reg['address'], reg['offset'], reg['size'])
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elif RegisterType.IMA == rtype:
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self.write_register(reg['index'], reg['offset'] + reg['base'])
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reg_value = self.read_register(reg['data'])
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elif rtype == RegisterType.MEMORY:
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reg_value = self.read_memory_register(reg)
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elif rtype == RegisterType.IMA:
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reg_value = self.read_ima_regsiter(reg)
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else:
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raise RegisterTypeNotFoundError(f'Register type not found: {rtype}')
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@@ -526,85 +572,110 @@ class Chipset:
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values.append(self.read_register(reg_name, cpu_thread))
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return values
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def write_pci_register(self, bus: Optional[int], reg: Dict[str, Any], rtype: str, reg_value: int) -> None:
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if bus is not None:
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b = bus
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else:
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b = self.get_first_bus(reg)
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d = reg['dev']
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f = reg['fun']
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o = reg['offset']
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size = reg['size']
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if RegisterType.PCICFG == rtype:
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if 1 == size:
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self.pci.write_byte(b, d, f, o, reg_value)
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elif 2 == size:
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self.pci.write_word(b, d, f, o, reg_value)
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elif 4 == size:
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self.pci.write_dword(b, d, f, o, reg_value)
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elif 8 == size:
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self.pci.write_dword(b, d, f, o, (reg_value & 0xFFFFFFFF))
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self.pci.write_dword(b, d, f, o + 4, (reg_value >> 32 & 0xFFFFFFFF))
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elif RegisterType.MMCFG == rtype:
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self.mmio.write_mmcfg_reg(b, d, f, o, size, reg_value)
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def write_msr_register(self, reg: Dict[str, Any], reg_value: int, cpu_thread: int) -> None:
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eax = (reg_value & 0xFFFFFFFF)
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edx = ((reg_value >> 32) & 0xFFFFFFFF)
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self.msr.write_msr(cpu_thread, reg['msr'], eax, edx)
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def write_portio_register(self, reg: Dict[str, Any], reg_value: int) -> None:
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port = reg['port']
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size = reg['size']
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self.io._write_port(port, reg_value, size)
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def write_memory_register(self, reg: Dict[str, Any], reg_value: int) -> None:
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if reg['access'] == 'dram':
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self.mem.write_physical_mem(reg['address'], reg['size'], reg_value)
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elif reg['access'] == 'mmio':
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self.mmio.write_MMIO_reg(reg['address'], reg['offset'], reg_value, reg['size'])
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def write_ima_register(self, reg: Dict[str, Any], reg_value: int) -> None:
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self.write_register(reg['index'], reg['offset'] + reg['base'])
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self.write_register(reg['data'], reg_value)
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def write_register(self, reg_name, reg_value, cpu_thread=0, bus=None):
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reg = self.get_register_def(reg_name)
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rtype = reg['type']
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if (RegisterType.PCICFG == rtype) or (RegisterType.MMCFG == rtype):
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if bus is not None:
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b = bus
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else:
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b = self.get_first_bus(reg)
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d = reg['dev']
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f = reg['fun']
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o = reg['offset']
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size = reg['size']
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if RegisterType.PCICFG == rtype:
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if 1 == size:
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self.pci.write_byte(b, d, f, o, reg_value)
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elif 2 == size:
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self.pci.write_word(b, d, f, o, reg_value)
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elif 4 == size:
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self.pci.write_dword(b, d, f, o, reg_value)
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elif 8 == size:
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self.pci.write_dword(b, d, f, o, (reg_value & 0xFFFFFFFF))
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self.pci.write_dword(b, d, f, o + 4, (reg_value >> 32 & 0xFFFFFFFF))
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elif RegisterType.MMCFG == rtype:
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self.mmio.write_mmcfg_reg(b, d, f, o, size, reg_value)
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elif RegisterType.MMIO == rtype:
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if (rtype == RegisterType.PCICFG) or (rtype == RegisterType.MMCFG):
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self.write_pci_register(bus, reg, rtype, reg_value)
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elif rtype == RegisterType.MMIO:
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self.mmio.write_MMIO_BAR_reg(reg['bar'], reg['offset'], reg_value, reg['size'], bus)
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elif RegisterType.MSR == rtype:
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eax = (reg_value & 0xFFFFFFFF)
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edx = ((reg_value >> 32) & 0xFFFFFFFF)
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self.msr.write_msr(cpu_thread, reg['msr'], eax, edx)
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elif RegisterType.PORTIO == rtype:
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port = reg['port']
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size = reg['size']
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self.io._write_port(port, reg_value, size)
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elif RegisterType.IOBAR == rtype:
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elif rtype == RegisterType.MSR:
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self.write_msr_register(reg, reg_value, cpu_thread)
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elif rtype == RegisterType.PORTIO:
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self.write_portio_register(reg, reg_value)
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elif rtype == RegisterType.IOBAR:
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self.iobar.write_IO_BAR_reg(reg['bar'], reg['offset'], reg['size'], reg_value)
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elif RegisterType.MSGBUS == rtype:
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elif rtype == RegisterType.MSGBUS:
|
||||
self.msgbus.msgbus_reg_write(reg['port'], reg['offset'], reg_value)
|
||||
elif RegisterType.MM_MSGBUS == rtype:
|
||||
elif rtype == RegisterType.MM_MSGBUS:
|
||||
self.msgbus.mm_msgbus_reg_write(reg['port'], reg['offset'], reg_value)
|
||||
elif RegisterType.MEMORY == rtype:
|
||||
if reg['access'] == 'dram':
|
||||
self.mem.write_physical_mem(reg['address'], reg['size'], reg_value)
|
||||
elif reg['access'] == 'mmio':
|
||||
self.mmio.write_MMIO_reg(reg['address'], reg['offset'], reg_value, reg['size'])
|
||||
elif RegisterType.IMA == rtype:
|
||||
self.write_register(reg['index'], reg['offset'] + reg['base'])
|
||||
self.write_register(reg['data'], reg_value)
|
||||
elif rtype == RegisterType.MEMORY:
|
||||
self.write_memory_register(reg, reg_value)
|
||||
elif rtype == RegisterType.IMA:
|
||||
self.write_ima_register(reg, reg_value)
|
||||
else:
|
||||
raise RegisterTypeNotFoundError(f'Register type not found: {rtype}')
|
||||
return True
|
||||
|
||||
def write_msr_register_all(self, reg, reg_name, reg_values) -> bool:
|
||||
ret = False
|
||||
topology = self.cpu.get_cpu_topology()
|
||||
if 'scope' in reg.keys() and reg['scope'] == "packages":
|
||||
packages = topology['packages']
|
||||
threads_to_use = [packages[p][0] for p in packages]
|
||||
elif 'scope' in reg.keys() and reg['scope'] == "cores":
|
||||
cores = topology['cores']
|
||||
threads_to_use = [cores[p][0] for p in cores]
|
||||
else: # Default to threads
|
||||
threads_to_use = range(self.helper.get_threads_count())
|
||||
if len(reg_values) == len(threads_to_use):
|
||||
value = 0
|
||||
for t in threads_to_use:
|
||||
self.write_register(reg_name, reg_values[value], t)
|
||||
value += 1
|
||||
ret = True
|
||||
return ret
|
||||
|
||||
def write_pci_register_all(self, reg_name, reg_values, cpu_thread, bus_data) -> bool:
|
||||
ret = False
|
||||
values = len(bus_data)
|
||||
if len(reg_values) == values:
|
||||
for index in range(values):
|
||||
self.write_register(reg_name, reg_values[index], cpu_thread, bus_data[index])
|
||||
ret = True
|
||||
return ret
|
||||
|
||||
def write_register_all(self, reg_name, reg_values, cpu_thread=0):
|
||||
reg = self.get_register_def(reg_name)
|
||||
rtype = reg['type']
|
||||
bus_data = self.get_register_bus(reg_name)
|
||||
ret = False
|
||||
if RegisterType.MSR == rtype:
|
||||
topology = self.cpu.get_cpu_topology()
|
||||
if 'scope' in reg.keys() and reg['scope'] == "packages":
|
||||
packages = topology['packages']
|
||||
threads_to_use = [packages[p][0] for p in packages]
|
||||
elif 'scope' in reg.keys() and reg['scope'] == "cores":
|
||||
cores = topology['cores']
|
||||
threads_to_use = [cores[p][0] for p in cores]
|
||||
else: # Default to threads
|
||||
threads_to_use = range(self.helper.get_threads_count())
|
||||
if len(reg_values) == len(threads_to_use):
|
||||
value = 0
|
||||
for t in threads_to_use:
|
||||
self.write_register(reg_name, reg_values[value], t)
|
||||
value += 1
|
||||
ret = True
|
||||
if rtype == RegisterType.MSR:
|
||||
ret = self.write_msr_register_all(reg, reg_name, reg_values)
|
||||
elif rtype in [RegisterType.MMCFG, RegisterType.PCICFG, RegisterType.MMIO] and bus_data:
|
||||
values = len(bus_data)
|
||||
if len(reg_values) == values:
|
||||
for index in range(values):
|
||||
self.write_register(reg_name, reg_values[index], cpu_thread, bus_data[index])
|
||||
ret = True
|
||||
ret = self.write_pci_register_all(reg_name, reg_values, cpu_thread, bus_data)
|
||||
else:
|
||||
if len(reg_values) == 1:
|
||||
self.write_register(reg_name, reg_values[0])
|
||||
|
||||
Reference in New Issue
Block a user