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C60X,C61X,C620 PCH updates (#578)

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* C60X,C61X,C620 PCH updates

* Updated from comments
This commit is contained in:
Aaron Frinzell
2019-06-25 17:54:45 -05:00
committed by BrentHoltsclaw
parent ab829befd5
commit bd80785292
3 changed files with 43 additions and 24 deletions
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chipsec/cfg/pch_c60x.xml
+7 -3
View File
@@ -2,15 +2,19 @@
<configuration platform="PCH_C60X" >
<!--
XML configuration file for C600 series PCH
* Intel(R) C600 Series Chipset Family Platform Controller Hub (PCH)
Intel (c) C600 Series Chipset and Intel (c) X79 Express Chipset datasheet
Intel (c) C600 Series Chipset and Intel (c) X79 Express Chipset Specification Update
https://ark.intel.com/products/series/98463/Intel-C600-Series-Chipsets
-->
<pci>
<device name="LPC" bus="0" dev="0x1F" fun="0" vid="0x8086" did="0x1D41" />
</pci>
<registers>
<!-- LPC Interface Bridge -->
<register name="GEN_PMCON_LOCK" type="pcicfg" bus="0" dev="0x1F" fun="0" offset="0xA6" size="1" desc="General Power Management Configuration Lock">
<register name="GEN_PMCON_LOCK" type="pcicfg" device="LPC" offset="0xA6" size="1" desc="General Power Management Configuration Lock">
<field name="ACPI_BASE_LOCK" bit="1" size="1" desc="Lock down ACPI Base Address (ABASE)"/>
<field name="SLP_STR_POL_LOCK" bit="2" size="1" desc="SLP Stretching Policy Lock-Down"/>
</register>
chipsec/cfg/pch_c61x.xml
+6 -3
View File
@@ -2,15 +2,18 @@
<configuration platform="PCH_C61X" >
<!--
XML configuration file for C610 series PCH
* Intel(R) C610 Series Chipset Family Platform Controller Hub (PCH)
Intel (c) C610 Series Chipset and Intel (c) X99 Chipset Platform Controller Hub (PCH) datasheet
https://ark.intel.com/products/series/98915/Intel-C610-Series-Chipsets
-->
<pci>
<device name="LPC" bus="0" dev="0x1F" fun="0" vid="0x8086" did="0x8D44,0x8D47" />
</pci>
<registers>
<!-- LPC Interface Bridge -->
<register name="GEN_PMCON_LOCK" type="pcicfg" bus="0" dev="0x1F" fun="0" offset="0xA6" size="1" desc="General Power Management Configuration Lock">
<register name="GEN_PMCON_LOCK" type="pcicfg" device="LPC" offset="0xA6" size="1" desc="General Power Management Configuration Lock">
<field name="ACPI_BASE_LOCK" bit="1" size="1" desc="Lock down ACPI Base Address (ABASE)"/>
<field name="SLP_STR_POL_LOCK" bit="2" size="1" desc="SLP Stretching Policy Lock-Down"/>
</register>
chipsec/cfg/pch_c620.xml
+30 -18
View File
@@ -13,10 +13,13 @@ XML configuration file for
<!-- -->
<!-- #################################### -->
<pci>
<device name="SMBUS" bus="0" dev="0x1F" fun="4" vid="0x8086" />
<device name="SPI" bus="0" dev="0x1F" fun="5" vid="0x8086" />
<device name="P2SBC" bus="0" dev="0x1F" fun="1" vid="0x8086" did="0xA220,0xA1A0" />
<device name="PMC" bus="0" dev="0x1F" fun="2" vid="0x8086" did="0xA221,0xA1A1" />
<device name="SMBUS" bus="0" dev="0x1F" fun="4" vid="0x8086" did="0xA223,0xA1A3" />
<device name="SPI" bus="0" dev="0x1F" fun="5" vid="0x8086" did="0xA224,0xA1A4" />
</pci>
<!-- #################################### -->
<!-- -->
<!-- Memory Mapped I/O spaces (MMIO BARs) -->
@@ -24,6 +27,7 @@ XML configuration file for
<!-- #################################### -->
<mmio>
<bar name="HDABAR" bus="0" dev="0x1F" fun="3" reg="0x10" width="8" mask="0xFFFFFFFFFFFFC000" size="0x1000" desc="HD Audio Base"/>
<bar name="TCO_BAR" bus="0" dev="0x1F" fun="4" reg="0x50" width="4" mask="0xFFE0" size="0x1000" desc="TCO Base Register Register Range"/>
<bar name="SPIBAR" bus="0" dev="0x1F" fun="5" reg="0x10" width="4" mask="0xFFFFF000" size="0x1000" desc="SPI Controller Register Range" offset="0x0"/>
<bar name="PWRMBASE" register="PWRMBASE" base_field="BA" size="0x1000" desc="Power Management Register Range"/>
<bar name="SBREGBAR" register="SBREG_BAR" base_field="RBA" size="0x1000000" desc="Sideband Register Access BAR"/>
@@ -35,7 +39,7 @@ XML configuration file for
<!-- -->
<!-- #################################### -->
<io>
<bar name="ABASE" register="ABASE" base_field="BA" size="0x100" desc="ACPI Base Address"/>
<bar name="ABASE" register="ABASE" base_field="Base" size="0x100" desc="ACPI Base Address"/>
<bar name="PMBASE" register="ABASE" base_field="BA" size="0x100" desc="ACPI Base Address"/>
<bar name="TCOBASE" register="TCOBASE" base_field="TCOBA" size="0x20" desc="TCO Base Address"/>
@@ -55,54 +59,62 @@ XML configuration file for
<!-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -->
<!-- Sideband Register Access Registers -->
<register name="SBREG_BAR" type="pcicfg" bus="0" dev="0x1F" fun="1" offset="0x10" size="4" desc="Sideband Register Access BAR">
<register name="SBREG_BAR" type="pcicfg" device="P2SBC" offset="0x10" size="4" desc="Sideband Register Access BAR">
<field name="RBA" bit="24" size="8" desc="Register Base Address"/>
</register>
<register name="P2SBC" type="pcicfg" bus="0" dev="0x1F" fun="1" offset="0xE0" size="2" desc="P2SB Configuration Register">
<register name="SBREG_BARH" type="pcicfg" device="P2SBC" offset="0x14" size="4" desc="Sideband Register Access BAR High DWORD">
<field name="RBAH" bit="0" size="32" desc="Register Base Address"/>
</register>
<register name="P2SBC" type="pcicfg" device="P2SBC" offset="0xE0" size="4" desc="P2SB Configuration Register">
<field name="HIDE" bit="8" size="1" desc="Hide SBREG_BAR"/>
</register>
<register name="P2SB_HIDE" type="pcicfg" device="P2SBC" offset="0xE1" size="1" desc="P2SB Configuration Register hide-unhide">
<field name="HIDE" bit="0" size="1" desc="Hide SBREG_BAR"/>
</register>
<!-- Power Management Controller -->
<register name="ABASE" type="pcicfg" bus="0" dev="0x1f" fun="2" offset="0x40" size="4" desc="ACPI Base Address">
<register name="ABASE" type="pcicfg" device="PMC" offset="0x40" size="4" desc="ACPI Base Address">
<field name="Base" bit="8" size="24" desc="Base Address"/>
<field name="STYPE" bit="0" size="1" desc="Space Type (always 1 - I/O space)"/>
<field name="BA" bit="8" size="8" desc="Base Address"/>
</register>
<register name="ACTL" type="pcicfg" bus="0" dev="0x1f" fun="2" offset="0x44" size="4" desc="ACPI Control">
<register name="ACTL" type="pcicfg" device="PMC" offset="0x44" size="4" desc="ACPI Control">
<field name="SCIS" bit="0" size="2" desc="SCI IRQ Select"/>
<field name="EN" bit="7" size="1" desc="ACPI Enable"/>
<field name="PWRM_EN" bit="8" size="1" desc="PWRM Enable"/>
</register>
<register name="PWRMBASE" type="pcicfg" bus="0" dev="0x1f" fun="2" offset="0x48" size="4" desc="PM Base Address">
<register name="PWRMBASE" type="pcicfg" device="PMC" offset="0x48" size="4" desc="PM Base Address">
<field name="STYPE" bit="0" size="1" desc="Space Type (always 0 - memory space)"/>
<field name="BA" bit="12" size="20" desc="Base Address"/>
</register>
<register name="GEN_PMCON_1" type="pcicfg" bus="0" dev="0x1f" fun="2" offset="0xA0" size="2" desc="General PM Configuration A">
<register name="GEN_PMCON_1" type="pcicfg" device="PMC" offset="0xA0" size="2" desc="General PM Configuration A">
<field name="SMI_LOCK" bit="4" size="1"/>
</register>
<register name="GEN_PMCON_B" type="pcicfg" device="PMC" offset="0xA4" size="4" desc="General Power Management Configuration Lock">
<field name="ACPI_BASE_LOCK" bit="17" size="1" desc="Lock down ACPI Base Address (ABASE)"/>
</register>
<!-- SMBus Host Controller -->
<register name="SMBUS_VID" type="pcicfg" bus="0" dev="0x1F" fun="4" offset="0x00" size="2" desc="VID" />
<register name="SMBUS_DID" type="pcicfg" bus="0" dev="0x1F" fun="4" offset="0x02" size="2" desc="DID" />
<register name="SMBUS_CMD" type="pcicfg" bus="0" dev="0x1F" fun="4" offset="0x04" size="2" desc="CMD" />
<register name="SMBUS_HCFG" type="pcicfg" bus="0" dev="0x1F" fun="4" offset="0x40" size="1" desc="Host Configuration">
<register name="SMBUS_VID" type="pcicfg" device="SMBUS" offset="0x00" size="2" desc="VID" />
<register name="SMBUS_DID" type="pcicfg" device="SMBUS" offset="0x02" size="2" desc="DID" />
<register name="SMBUS_CMD" type="pcicfg" device="SMBUS" offset="0x04" size="2" desc="CMD" />
<register name="SMBUS_HCFG" type="pcicfg" device="SMBUS" offset="0x40" size="1" desc="Host Configuration">
<field name="HST_EN" bit="0" size="1"/>
<field name="SMB_SMI_EN" bit="1" size="1"/>
<field name="I2C_EN" bit="2" size="2"/>
<field name="SSRESET" bit="3" size="1"/>
<field name="SPD_WD" bit="4" size="1"/>
</register>
<register name="TCOBASE" type="pcicfg" bus="0" dev="0x1f" fun="4" offset="0x50" size="4" desc="TCO Base Address">
<register name="TCOBASE" type="pcicfg" device="SMBUS" offset="0x50" size="4" desc="TCO Base Address">
<field name="IOS" bit="0" size="1" desc="I/O space"/>
<field name="TCOBA" bit="5" size="11" desc="TCO Base Address"/>
</register>
<register name="TCOCTL" type="pcicfg" bus="0" dev="0x1f" fun="4" offset="0x54" size="4" desc="TCO Control">
<register name="TCOCTL" type="pcicfg" device="SMBUS" offset="0x54" size="4" desc="TCO Control">
<field name="TCO_BASE_LOCK" bit="0" size="1" desc="TCO Base Lock"/>
<field name="TCO_BASE_EN" bit="8" size="1" desc="TCO Base Enable"/>
</register>
<!-- SPI Interface Controller -->
<register name="BC" type="pcicfg" bus="0" dev="0x1F" fun="5" offset="0xDC" size="4" desc="BIOS Control">
<register name="BC" type="pcicfg" device="SPI" offset="0xDC" size="4" desc="BIOS Control">
<field name="BIOSWE" bit="0" size="1" desc="BIOS Write Enable" />
<field name="BLE" bit="1" size="1" desc="BIOS Lock Enable" />
<field name="SRC" bit="2" size="2" desc="SPI Read Configuration" />