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Adding fixed MMIO and IO addresses

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Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>
This commit is contained in:
Erik Bjorge
2019-05-31 11:45:17 -07:00
parent 8eed8449bc
commit df25bc561b
2 changed files with 8 additions and 8 deletions
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chipsec/cfg/pch_1xx.xml
+4 -4
View File
@@ -26,8 +26,8 @@ XML configuration file for 100 series PCH based platforms
<mmio>
<bar name="HDABAR" bus="0" dev="0x1F" fun="3" reg="0x10" width="8" mask="0xFFFFFFFFFFFFC000" size="0x1000" desc="HD Audio Base"/>
<bar name="SPIBAR" bus="0" dev="0x1F" fun="5" reg="0x10" width="4" mask="0xFFFFF000" size="0x1000" desc="SPI Controller Register Range" offset="0x0"/>
<bar name="PWRMBASE" register="PWRMBASE" base_field="BA" size="0x1000" desc="Power Management Register Range"/>
<bar name="SBREGBAR" register="SBREG_BAR" base_field="RBA" size="0x1000000" desc="Sideband Register Access BAR"/>
<bar name="PWRMBASE" register="PWRMBASE" base_field="BA" size="0x1000" fixed_address="0xFE000000" desc="Power Management Register Range"/>
<bar name="SBREGBAR" register="SBREG_BAR" base_field="RBA" size="0x1000000" fixed_address="0xFD000000" desc="Sideband Register Access BAR"/>
</mmio>
<!-- #################################### -->
@@ -36,8 +36,8 @@ XML configuration file for 100 series PCH based platforms
<!-- -->
<!-- #################################### -->
<io>
<bar name="ABASE" register="ABASE" base_field="BA" size="0x100" desc="ACPI Base Address"/>
<bar name="PMBASE" register="ABASE" base_field="BA" size="0x100" desc="ACPI Base Address"/>
<bar name="ABASE" register="ABASE" base_field="BA" size="0x100" fixed_address="0x1800" desc="ACPI Base Address"/>
<bar name="PMBASE" register="ABASE" base_field="BA" size="0x100" fixed_address="0x1800" desc="ACPI Base Address"/>
<bar name="TCOBASE" register="TCOBASE" base_field="TCOBA" size="0x20" desc="TCO Base Address"/>
<!-- old definition -->
chipsec/cfg/pch_2xx.xml
+4 -4
View File
@@ -26,8 +26,8 @@ XML configuration file for 200 series PCH based platforms
<mmio>
<bar name="HDABAR" bus="0" dev="0x1F" fun="3" reg="0x10" width="8" mask="0xFFFFFFFFFFFFC000" size="0x1000" desc="HD Audio Base"/>
<bar name="SPIBAR" bus="0" dev="0x1F" fun="5" reg="0x10" width="4" mask="0xFFFFF000" size="0x1000" desc="SPI Controller Register Range" offset="0x0"/>
<bar name="PWRMBASE" register="PWRMBASE" base_field="BA" size="0x1000" desc="Power Management Register Range"/>
<bar name="SBREGBAR" register="SBREG_BAR" base_field="RBA" size="0x1000000" desc="Sideband Register Access BAR"/>
<bar name="PWRMBASE" register="PWRMBASE" base_field="BA" size="0x1000" fixed_address="0xFE000000" desc="Power Management Register Range"/>
<bar name="SBREGBAR" register="SBREG_BAR" base_field="RBA" size="0x1000000" fixed_address="0xFD000000" desc="Sideband Register Access BAR"/>
</mmio>
<!-- #################################### -->
@@ -36,8 +36,8 @@ XML configuration file for 200 series PCH based platforms
<!-- -->
<!-- #################################### -->
<io>
<bar name="ABASE" register="ABASE" base_field="BA" size="0x100" desc="ACPI Base Address"/>
<bar name="PMBASE" register="ABASE" base_field="BA" size="0x100" desc="ACPI Base Address"/>
<bar name="ABASE" register="ABASE" base_field="BA" size="0x100" fixed_address="0x1800" desc="ACPI Base Address"/>
<bar name="PMBASE" register="ABASE" base_field="BA" size="0x100" fixed_address="0x1800" desc="ACPI Base Address"/>
<bar name="TCOBASE" register="TCOBASE" base_field="TCOBA" size="0x20" desc="TCO Base Address"/>
<!-- old definition -->