6fccb31877
Fixup spd_wd to work with python3
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Signed-off-by: BrentHoltsclaw <brent.holtsclaw@intel.com >
2019-08-16 14:19:26 -07:00
73485556d7
Cleanup bugs - Division compliant with python3
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Signed-off-by: BrentHoltsclaw <brent.holtsclaw@intel.com >
2019-08-16 14:19:02 -07:00
18827a8574
Cleanup use is for None type compare
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Signed-off-by: BrentHoltsclaw <brent.holtsclaw@intel.com >
2019-08-16 14:18:47 -07:00
2efeda4345
Merge python3-rc2 branch into master ( #656 )
2019-08-15 14:11:20 -07:00
abf3f627e6
Cleanup of debug_cleanup module
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Removed hardcoded offsets
Signed-off-by: BrentHoltsclaw <brent.holtsclaw@intel.com >
2019-07-23 11:13:19 -07:00
f4408c5cf8
Adding case for PRMRR Base/Mask set to zero.
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Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2019-07-23 11:12:53 -07:00
cbb6ea45c0
Use logger functions instead of print and set self.res before returning in case of error
2019-06-13 13:15:25 -07:00
6fa21fc97c
If SPD_WD is not set, fail the check if SPDs only are detected, informational message otherwise
2019-06-13 13:15:25 -07:00
1f52d84777
Add vulnerability check to verify that SPD Write Disable bit in SMBus controller bit is set
2019-06-13 13:15:25 -07:00
95b9d51273
using primitives for variable Name,Attribute,Data fields
2019-05-31 12:40:21 -07:00
fe6513ff73
Only validate registers defined in platform
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Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2019-05-29 09:33:19 -07:00
989db9f8b8
Updated messages in sinkhole tool
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Some additional information was requested to make the failure/success cases more clear.
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2019-05-23 14:47:01 -07:00
789314a142
Normalizing logging for various sections of chipsec:
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HAL now only use logger().HAL
helpers now only use logger.DEBUG
modules now only use logger.VERBOSE
2019-04-25 14:19:08 -07:00
221e524c51
Added check to see if S3 Boot script was found
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If the S3 boot script was not found, it will tell the user that instead of giving a false error.
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2019-04-18 08:32:49 -07:00
5d3541c005
Additional documentation fixes
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- Remove warnings when processing doc strings
- Fix some formatting issues
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2019-03-05 17:25:06 -08:00
ed5e424d28
Cleaned up some of the module documenation.
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Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2019-03-05 17:25:06 -08:00
2cb3e7b8a2
STIBP may not be enabled by default by the OS.
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The OS may choose to only enable STIBP in specific situations to
reduce the performance impact. An OS may also choosed to only
enable STIBP for specific processes or by using an opt-in setting.
It should not be assumed that STIBP will be enabled on all logical
processors.
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2019-03-01 12:09:18 -08:00
9a580d4649
Updated test to check for register definition in is_supported.
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Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2019-02-04 10:04:08 -08:00
c37c3b852e
Enabling OSX support for common modules and update install
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Functionality was added, but the modules were never updated.
2019-01-09 11:00:39 -08:00
2ff813db77
Skip SGX test when not supported by processor
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Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2018-12-13 16:56:25 -08:00
d074b65114
Minor format updates to memlock
2018-12-13 16:55:51 -08:00
0446d1583a
Add code to only check registers defined by the platform
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Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2018-11-13 15:10:05 -08:00
7ec76d865e
Added section breaks in test
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Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2018-11-13 15:09:22 -08:00
d5b8526399
Clean up SGX test results to match CHIPSEC module expectations
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Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2018-11-13 15:09:22 -08:00
31764f0538
Update test to check controls and not specific registers
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This test has been updated to use controls. The test should check that
the control exists and not a specific register.
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2018-11-12 15:43:38 -08:00
80a306cc92
Fixed formatting issues in doc strings.
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- Removed non-ASCII character
- Removed tab characters
- Removed extra blank line in documentation
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2018-11-11 19:15:00 -08:00
525a3fe7b3
Updated link to HackingTeam UEFI Rootkit
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Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2018-10-29 13:30:31 -07:00
d3f7cfd70a
Add support for checking if ME Manufacturing Mode is enabled based on publicly-available info in coreboot repo ( #452 )
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https://github.com/coreboot/coreboot/blob/master/src/southbridge/intel/lynxpoint/me.h
https://github.com/coreboot/coreboot/blob/master/src/southbridge/intel/lynxpoint/me_status.c
2018-10-09 13:55:35 -07:00
1ea5ea3c04
Adding LoJax to UEFI module blacklist
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More information about LoJax can be found at this link.
https://www.welivesecurity.com/2018/09/27/lojax-first-uefi-rootkit-found-wild-courtesy-sednit-group/
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2018-10-03 11:30:25 -07:00
25d4531aa3
Adding test for WRSDIS being set in SPI controller
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Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2018-10-03 11:29:56 -07:00
2633197646
Minor updates to sgx_check
2018-09-10 10:17:41 -07:00
61f3d7831e
adding MSR register to xml and check on debug register in sgx module
2018-08-22 13:26:49 -07:00
2a39c4bf43
Removed trailing white space
2018-07-26 14:35:01 -07:00
5f4212f941
Remove white space
2018-07-26 14:35:01 -07:00
405992e54c
Removed unecessary codr 'print'
2018-07-26 14:35:01 -07:00
f23a4c1175
Created additonal bounds for _SIZE object. Removed additional white space
2018-07-26 14:35:01 -07:00
6e504056fc
update xrange to range for python3 support
2018-07-26 14:35:01 -07:00
6fd2dbbb57
Remove bound method for singular BOUND object for string or integer value
2018-07-26 14:35:01 -07:00
7b26638f54
Created a bounds to limit the amount of data being genereated by any given function. Fixes error handling with uefi_fuzzer (Additional Comments)
2018-07-26 14:35:01 -07:00
f3575ebfa2
Created a bounds to limit the amount of data being genereated by any given function. Fixes error handling with uefi_fuzzer
2018-07-26 14:35:01 -07:00
872ea14545
Implement Bounds for _DATA variable
2018-07-26 14:35:01 -07:00
45b50782c9
Module to check SGX configuration and capabilities
2018-05-21 18:02:05 -07:00
73a2d47d5b
Memlock workaround for Atom processors on UEFI Shell
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When accessing this MSR from the UEFI Shell the system will hang.
Skipping this test when running on Atom processors.
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2018-05-21 18:01:15 -07:00
f6314e259d
debugenabled: Use logical 'or' instead of bitwise '|'
2018-04-09 17:36:53 -07:00
7308359a5a
Fixed error reporting when warnings are found.
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Discovered that the warning path was not working as expected. Showed
failed in log message but warning in summary.
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2018-02-23 09:24:19 -08:00
792b9d4a28
add memlock module ( #356 )
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* add memlock module
* moved MSR to config file
2018-02-22 19:40:37 -08:00
cf063f85b4
adjust check for debug occured bit
2018-02-21 10:43:00 -08:00
bdf30fff49
expand supported platform and fixes
2018-02-21 10:43:00 -08:00
b82c9ff569
add module to check debug features on/off
2018-02-21 10:43:00 -08:00
dd66ef454a
Added new module checking for Spectre variant 2
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The module checks if system includes hardware mitigations for
Speculative Execution Side Channel. Specifically, it verifies that the
system supports CPU mitigations for
Branch Target Injection vulnerability a.k.a. Spectre Variant 2
(CVE-2017-5715)
2018-01-18 14:08:33 -08:00
BrentHoltsclaw