66 Commits

Author SHA1 Message Date
brentholtsclaw 44481157a5 Fix divide for python3 in bios_kbrd_buffer
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
2020-06-30 09:55:59 -07:00
Aaron Frinzell 14c224abe0 Remove unused variable 2020-06-29 09:32:09 -07:00
Aaron Frinzell 41788a611b SPI access updates 2020-06-29 09:32:09 -07:00
brentholtsclaw f1d5666d9c Update ia_untrused
check soc_bios_done bit
check each thread for IA_Untrusted bit

Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
2020-06-29 09:31:47 -07:00
brentholtsclaw 4eadcf4e95 Update tco_en logic and module cleanup
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
2020-06-26 13:58:57 -07:00
brentholtsclaw 36a8260866 Move modules from modules to modules/common
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
2020-06-25 11:51:46 -07:00
Frinzell 7c0fe8241b Remove extra import 2020-05-29 14:05:18 -07:00
Frinzell 1ead0d25f2 rtclock.py improvements 2020-05-29 14:05:18 -07:00
brentholtsclaw 35a614cbfc Add ICL support
Add ICL configuration file
Update memconfig, remap, smm_dma modules
Add ia_untrusted module

Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
2020-05-28 14:11:41 -07:00
brentholtsclaw 2d0233ad87 Fix broken module imports
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
2020-04-28 16:14:11 -07:00
BrentHoltsclaw 4f3b7236ba Remove duplicate configuration from common.py and move specific configuration to hal files
Signed-off-by: BrentHoltsclaw <brent.holtsclaw@intel.com>
2020-04-22 16:26:11 -07:00
BrentHoltsclaw 514c23d84d Modify files based upon chipset.py changes
Fixup files that relied on CHIPSET_ID_XXX logic
Modify files for functions moved within cs class

Signed-off-by: BrentHoltsclaw <brent.holtsclaw@intel.com>
2020-04-20 08:39:02 -07:00
brentholtsclaw 9c47edabf7 Misc LGTM fixes
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
2020-04-17 09:23:07 -07:00
brentholtsclaw 0a97f2229c Modify SNB support for spd_wd
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
2020-02-28 15:43:11 -08:00
Nathaniel Mitchell 157104bff4 Fixed copy right year and removed enterprise verbiage.
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
2020-02-05 11:08:38 -08:00
Nathaniel Mitchell dfc9d5953a Fixed errors caused by list_EFI_variables in Windows.
Fixing issues in helper/modules that are caused by some versions of windows blocking runtime access to UEFI varialbes. Also fixed issue print_buffer issue when using --hal.

Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
2020-02-05 11:08:38 -08:00
BrentHoltsclaw e7b2c983ec Cleanup imports within modules directory
Signed-off-by: BrentHoltsclaw <brent.holtsclaw@intel.com>
2020-01-23 15:07:44 -08:00
BrentHoltsclaw cb4f8e889d Clean up spi_access and add check for valid flash descriptor
Signed-off-by: BrentHoltsclaw <brent.holtsclaw@intel.com>
2020-01-23 08:55:22 -08:00
nick 23cc63f126 checing IA32_FEATURE_CONTROL and TCO1_CNT lock on atom 2020-01-22 15:53:36 -08:00
assafcarlsbad 27f79aa991 Update copyright years. 2020-01-21 14:44:37 -08:00
assafcarlsbad 79d662bf80 Update access_uefispec.py 2020-01-21 14:44:37 -08:00
Assaf Carlsbad cc63edbc46 Check that 'uefispec_concern' is not empty before logging an error message. 2020-01-21 14:44:37 -08:00
Assaf Carlsbad 53c6310861 Strip terminating NULL bytes from the CPU brand. 2020-01-13 10:29:46 -08:00
BrentHoltsclaw a582c5249f Cleanup sgx_check
Add is_supported funciton
cleanup imports
check register field name not bits where applicable
modify prmrr config lock check

Signed-off-by: BrentHoltsclaw <brent.holtsclaw@intel.com>
2019-12-19 15:43:48 -08:00
BrentHoltsclaw 6be52acec2 Remove smbios bios_version module
The module is currently not stable and causing issues.  Given it is an Informational Check, it is being removed for the time being.
Similar functionality exists within chipsec util.

Signed-off-by: BrentHoltsclaw <brent.holtsclaw@intel.com>
2019-11-18 15:23:45 -08:00
Erik Bjorge 40ff7cffbf Get extended BIOS R/W access information
Use the Flash Descriptor Observability registers to OR in the settings
from the flash descriptor to the existing FRAP register fields.

Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>
2019-11-18 15:13:59 -08:00
Erik Bjorge 736871e5f9 Adding initial SMBIOS support (#722)
* Initial SMBIOS HAL and Command

- Only searches for the Entry Point structure
- Currently only detects 2.x structures correctly

Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>

* Added support for 64bit 3.x entry point

Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>

* Updated command processing

Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>

* Added ability to parse structures based on header

Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>

* Updated command processing

- Made command processing a bit more flexible
- Improved logging messages
- Added place holders for future functionality

Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>

* Added ability to get structures by type

Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>

* Added string extraction support

- Also added some initial code for decoding type 0 structure information
- Updated interface to make things cleaner

Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>

* Added decode support

- Only supports partial decode of Type 0 (2.0) structure

Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>

* Removed unused variable

- Also fixed tool name in timing string

Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>

* Adding basic BIOS Information module

- Adding module to get the BIOS Information SMBIOS data

Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>

* Python 3 updates

- Requires additional Python 3 UEFI HAL changes

Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>
2019-10-31 14:17:47 -07:00
Erik Bjorge c2f13379e7 Fixing Python 3 bug
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>
2019-10-24 14:11:06 -07:00
Erik Bjorge af7fdb6d37 Fixing imports and __init__ function
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>
2019-10-24 14:11:06 -07:00
Erik Bjorge d5c4d234c9 Adding CPU Info module
This new module just displays general CPU data.

Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>
2019-10-21 13:11:00 -07:00
BrentHoltsclaw abb0f3231f Fix ia32cfg verbose error
Signed-off-by: BrentHoltsclaw <brent.holtsclaw@intel.com>
2019-09-04 14:04:28 -07:00
BrentHoltsclaw c390e0378a requested changes
Signed-off-by: BrentHoltsclaw <brent.holtsclaw@intel.com>
2019-09-04 09:17:56 -07:00
BrentHoltsclaw 30312c7905 Cleanup ia32cfg modules
Cleanup of imports
Enabled check per thread

Signed-off-by: BrentHoltsclaw <brent.holtsclaw@intel.com>
2019-09-04 09:17:56 -07:00
Frinzell f0e0410788 Optimize a check 2019-09-03 11:13:21 -07:00
Frinzell 288b4d3e32 Updates to memlock 2019-09-03 11:13:21 -07:00
BrentHoltsclaw 6fccb31877 Fixup spd_wd to work with python3
Signed-off-by: BrentHoltsclaw <brent.holtsclaw@intel.com>
2019-08-16 14:19:26 -07:00
BrentHoltsclaw 2efeda4345 Merge python3-rc2 branch into master (#656) 2019-08-15 14:11:20 -07:00
Erik Bjorge f4408c5cf8 Adding case for PRMRR Base/Mask set to zero.
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>
2019-07-23 11:12:53 -07:00
Jesse Michael cbb6ea45c0 Use logger functions instead of print and set self.res before returning in case of error 2019-06-13 13:15:25 -07:00
Jesse Michael 6fa21fc97c If SPD_WD is not set, fail the check if SPDs only are detected, informational message otherwise 2019-06-13 13:15:25 -07:00
Jesse Michael 1f52d84777 Add vulnerability check to verify that SPD Write Disable bit in SMBus controller bit is set 2019-06-13 13:15:25 -07:00
Erik Bjorge fe6513ff73 Only validate registers defined in platform
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>
2019-05-29 09:33:19 -07:00
Erik Bjorge ed5e424d28 Cleaned up some of the module documenation.
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>
2019-03-05 17:25:06 -08:00
Erik Bjorge 2cb3e7b8a2 STIBP may not be enabled by default by the OS.
The OS may choose to only enable STIBP in specific situations to
reduce the performance impact. An OS may also choosed to only
enable STIBP for specific processes or by using an opt-in setting.
It should not be assumed that STIBP will be enabled on all logical
processors.

Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>
2019-03-01 12:09:18 -08:00
Erik Bjorge 9a580d4649 Updated test to check for register definition in is_supported.
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>
2019-02-04 10:04:08 -08:00
BrentHoltsclaw c37c3b852e Enabling OSX support for common modules and update install
Functionality was added, but the modules were never updated.
2019-01-09 11:00:39 -08:00
Erik Bjorge 2ff813db77 Skip SGX test when not supported by processor
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>
2018-12-13 16:56:25 -08:00
Frinzell d074b65114 Minor format updates to memlock 2018-12-13 16:55:51 -08:00
Erik Bjorge 7ec76d865e Added section breaks in test
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>
2018-11-13 15:09:22 -08:00
Erik Bjorge d5b8526399 Clean up SGX test results to match CHIPSEC module expectations
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>
2018-11-13 15:09:22 -08:00