On some testing systems, `chipsec_util.py iommu config` fails with:
[CHIPSEC] Executing command 'iommu' with args ['config']
[CHIPSEC] Couldn't find DMAR ACPI table
==================================================================
[iommu] GFXVTD IOMMU Engine Configuration
==================================================================
Base register (BAR) : GFXVTBAR
BAR register value : 0x0
Traceback (most recent call last):
File "./chipsec_util.py", line 236, in <module>
sys.exit(main())
File "./chipsec_util.py", line 232, in main
return chipsecUtil.main()
File "./chipsec_util.py", line 204, in main
comm.run()
File "/root/chipsec/chipsec/utilcmd/iommu_cmd.py", line 139, in run
self.func()
File "/root/chipsec/chipsec/utilcmd/iommu_cmd.py", line 122, in iommu_config
self.iommu_engine('config')
File "/root/chipsec/chipsec/utilcmd/iommu_cmd.py", line 114, in iommu_engine
if (cmd == 'config' ): _iommu.dump_IOMMU_configuration( e )
File "/root/chipsec/chipsec/hal/iommu.py", line 78, in dump_IOMMU_configuration
base = self.get_IOMMU_Base_Address( iommu_engine )
File "/root/chipsec/chipsec/hal/iommu.py", line 52, in get_IOMMU_Base_Address
(base, size) = self.mmio.get_MMIO_BAR_base_address(vtd_base_name)
File "/root/chipsec/chipsec/hal/mmio.py", line 249, in get_MMIO_BAR_base_address
raise CSReadError('[mmio] Base address was determined to be 0')
chipsec.exceptions.CSReadError: [mmio] Base address was determined to be 0
Indeed, the OS did not configure any IOMMU and GFXVTBAR was zero. It is
nonetheless annoying that the execution of this utility stops without
describing the other IOMMU ("VTBAR").
Fix this issue by returning early from the dump functions if the BAR
contains zero. With this change:
$ ./chipsec_util.py iommu config
...
==================================================================
[iommu] GFXVTD IOMMU Engine Configuration
==================================================================
Base register (BAR) : GFXVTBAR
BAR register value : 0x0
==================================================================
[iommu] VTD IOMMU Engine Configuration
==================================================================
Base register (BAR) : VTBAR
BAR register value : 0x0
$ ./chipsec_util.py iommu status
...
==================================================================
[iommu] GFXVTD IOMMU Engine Status:
==================================================================
[iommu] GFXVTBAR value is zero
==================================================================
[iommu] VTD IOMMU Engine Status:
==================================================================
[iommu] VTBAR value is zero
$ ./chipsec_util.py iommu pt
...
[iommu] GFXVTBAR value is zero
[iommu] VTBAR value is zero
Signed-off-by: Nicolas Iooss <nicolas.iooss_git@polytechnique.org>
CHIPSEC: Platform Security Assessment Framework
CHIPSEC is a framework for analyzing the security of PC platforms including hardware, system firmware (BIOS/UEFI), and platform components. It includes a security test suite, tools for accessing various low level interfaces, and forensic capabilities. It can be run on Windows, Linux, Mac OS X and UEFI shell. Instructions for installing and using CHIPSEC can be found in the manual.
NOTE: This software is for security testing purposes. Use at your own risk. Read WARNING.txt before using.
First version of CHIPSEC was released in March 2014: Announcement at CanSecWest 2014
Recent presentation on how to use CHIPSEC to find vulnerabilities in firmware, hypervisors and hardware configuration, explore low level system assets and even detect firmware implants: Exploring Your System Deeper
Release Convention
- CHIPSEC uses a major.minor.patch release version number
- Changes to the arguments or calling conventions will be held for a minor version update
Projects That Include CHIPSEC
Contact Us
For any questions or suggestions please contact us at: chipsec@intel.com
Mailing list:
Twitter:
- For CHIPSEC release alerts: Follow us at CHIPSEC Release
- For general CHIPSEC info: Follow CHIPSEC
For AMD related questions or suggestions please contact Gabriel Kerneis at: Gabriel.Kerneis@ssi.gouv.fr