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https://github.com/hakril/PythonForWindows
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[WIP] simple_arm64 + testsuite
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hakril
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try:
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import capstone
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except ImportError as e:
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capstone = None
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import pytest
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import windows.native_exec.simple_arm64 as arm64
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from windows.native_exec.simple_arm64 import *
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from windows.pycompat import int_types
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if capstone:
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disassembleur = capstone.Cs(capstone.CS_ARCH_ARM64, capstone.CS_MODE_ARM)
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disassembleur.detail = True
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@pytest.fixture
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def need_capstone():
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if capstone is None:
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raise pytest.skip("Capstone is not installed")
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return True
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pytestmark = pytest.mark.usefixtures("need_capstone")
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def disas(x):
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return list(disassembleur.disasm(x, 0))
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mnemonic_name_exception = {'movabs': 'mov'}
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class CheckInstr(object):
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def __init__(self, instr_to_test, expected_result=None, immediat_accepted=None, must_fail=None, debug=False):
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self.instr_to_test = instr_to_test
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self.immediat_accepted = immediat_accepted
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self.expected_result = expected_result
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self.must_fail = must_fail
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self.debug = debug
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def __call__(self, *args):
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try:
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if self.debug:
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import pdb;pdb.set_trace()
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pdb.DONE = True
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arm64.DEBUG = self.debug
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res = bytes(self.instr_to_test(*args).get_code())
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if self.debug:
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print(repr(res))
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except ValueError as e:
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if self.must_fail == True:
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return True
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else:
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raise
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else:
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if self.must_fail:
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raise ValueError("Instruction did not failed as expected")
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capres_list = disas(res)
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if len(capres_list) != 1:
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raise AssertionError("Trying to disas an instruction resulted in multiple disassembled instrs")
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capres = capres_list[0]
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print("{0} {1}".format(capres.mnemonic, capres.op_str))
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if self.expected_result is not None:
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if "{0} {1}".format(capres.mnemonic, capres.op_str) == self.expected_result:
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return True
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else:
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raise AssertionError("Expected result <{0}> got <{1}>".format(self.expected_result, "{0} {1}".format(capres.mnemonic, capres.op_str)))
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if len(res) != len(capres.bytes):
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print("<{0}> vs <{1}>".format(repr(res), repr(capres.bytes)))
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raise AssertionError("Not all bytes have been used by the disassembler")
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self.compare_mnemo(capres)
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self.compare_args(args, capres)
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def compare_mnemo(self, capres):
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expected = self.instr_to_test.__name__.lower()
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cap_mnemo = mnemonic_name_exception.get(str(capres.mnemonic), str(capres.mnemonic))
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if expected != cap_mnemo:
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raise AssertionError("Expected menmo {0} got {1}".format(expected, str(capres.mnemonic)))
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return True
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def compare_args(self, args, capres):
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capres_op = list(capres.operands)
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if len(args) != len(capres_op):
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raise AssertionError("Expected {0} operands got {1}".format(len(args), len(capres_op)))
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for op_args, cap_op in zip(args, capres_op):
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if isinstance(op_args, str): # Register
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if cap_op.type != capstone.arm64.ARM64_OP_REG:
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raise AssertionError("Expected args {0} operands got {1}".format(op_args, capres_op))
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if op_args.lower() != capres.reg_name(cap_op.reg).lower():
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raise AssertionError("Expected register <{0}> got {1}".format(op_args.lower(), capres.reg_name(cap_op.reg).lower()))
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elif isinstance(op_args, int_types):
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if (op_args != cap_op.imm) and not (self.immediat_accepted and self.immediat_accepted == cap_op.imm):
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raise AssertionError("Expected Immediat <{0}> got {1}".format(op_args, cap_op.imm))
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else:
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raise ValueError("Unknow argument {0} of type {1}".format(op_args, type(op_args)))
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def test_assembler():
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CheckInstr(Add)('W0', 'W0', 0)
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CheckInstr(Add)('W1', 'W0', 0)
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CheckInstr(Add)('W30', 'W12', 0)
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CheckInstr(Add)('W0', 'W0', 1)
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CheckInstr(Add)('X0', 'X0', 0)
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CheckInstr(Add)('X30', 'X12', 0)
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CheckInstr(Add)('X0', 'X0', 1)
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CheckInstr(Add)('X11', 'X12', 0x123)
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# Error test todo
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# CheckInstr(Add)('X11', 'W12', 0x123)
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CheckInstr(Add)('X11', 'X12', 0x12345678)
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@@ -0,0 +1,203 @@
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import sys
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import collections
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import struct
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import binascii
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import operator
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# py3
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is_py3 = (sys.version_info.major >= 3)
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if is_py3:
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basestring = str
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int_types = int
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else:
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int_types = (int, long)
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# https://documentation-service.arm.com/static/67581b3355451e3c38d97c22
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# Chapter C4: A64 Instruction Set Encoding: :
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## C2.1.3
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# 32-bit variant (sf = 0).
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# 64-bit variant (sf = 1).
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## C2.1.5
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# The following symbol conventions are used:
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# <Xn> The 64-bit name of a general-purpose register (X0-X30) or the zero register (XZR).
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# <Wn> The 32-bit name of a general-purpose register (W0-W30) or the zero register (WZR).
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# <Xn|SP> The 64-bit name of a general-purpose register (X0-X30) or the current stack pointer (SP).
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# <Wn|WSP> The 32-bit name of a general-purpose register (W0-W30) or the current stack pointer (WSP).
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# <Bn>, <Hn>, <Sn>, <Dn>, <Qn>
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# The 8, 16, 32, 64, or 128-bit name of a SIMD and floating-point register in a scalar context, as
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# described in Register names.
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# <Vn> The name of a SIMD and floating-point register in a vector context, as described in Register names.
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# <Zn> The name of an SVE scalable vector register, as described in Treatment of SVE scalable vector
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# registers.
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# <Pn> The name of an SVE scalable predicate register, as described in Vector predication
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# Make a special memoryview that match what is show in the ARM Chapter C4 ?
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XREGISTER = {'X0', 'X1', 'X2', 'X3', 'X4', 'X5', 'X6', 'X7', 'X8', 'X9', 'X10', 'X11', 'X12', 'X13', 'X14', 'X15', 'X16', 'X17', 'X18', 'X19', 'X20', 'X21', 'X22', 'X23', 'X24', 'X25', 'X26', 'X27', 'X28', 'X29', 'X30'}
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WREGISTER = {'W0', 'W1', 'W2', 'W3', 'W4', 'W5', 'W6', 'W7', 'W8', 'W9', 'W10', 'W11', 'W12', 'W13', 'W14', 'W15', 'W16', 'W17', 'W18', 'W19', 'W20', 'W21', 'W22', 'W23', 'W24', 'W25', 'W26', 'W27', 'W28', 'W29', 'W30'}
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ALL_REGISTER = XREGISTER | WREGISTER
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SP = "SP"
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WSP = "WSP"
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class InstructionEncoding(object):
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def __init__(self):
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super(InstructionEncoding, self).__init__()
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# Bits are in
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# 0 1 2 3 4 ... 31
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# Translation to real little-endian is done last
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self.bytearray = bytearray(32)
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self.bits = memoryview(self.bytearray)
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# Disable with SF = FALSE ?
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self.bitness = None
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@classmethod
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def is_register(self, arg, accept_sp):
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arg = arg.upper()
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return (accept_sp and (arg in [SP, WSP])) or arg in ALL_REGISTER
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@classmethod
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def is_imm12(self, arg):
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try:
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value = int(arg)
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except (ValueError, TypeError):
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return False
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return True # Check size max ?
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@classmethod
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def is_shift(self, arg):
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return True
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@classmethod
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def gen(cls, **encoding_array):
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class GeneratedEncoding(cls):
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ENCODING_VALUES = encoding_array
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return GeneratedEncoding
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# Instruction filing at instanciation
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def binencode_imm(self, immediat, outsize):
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binstr = "{:0{outsize}b}".format(immediat, outsize=outsize)
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assert len(binstr) == outsize, "Could not encode immediat {0} in {1} bits. Value take {2} bits".format(immediat, outsize, len(binstr))
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binlist = [int(c) for c in reversed(binstr)]
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return bytearray(binlist)
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def setup_bitness(self, bitness):
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assert bitness in (32, 64)
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if self.bitness is None:
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self.bitness = bitness
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if bitness == 32:
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self.sf[:] = b"\x00"
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else: # bitness == 64:
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self.sf[:] = b"\x01"
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assert self.bitness == bitness, "bitness mismatch in instruction"
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def encode_register(self, register, outsize=5):
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register = register.upper()
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assert register in ALL_REGISTER
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if register in XREGISTER:
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self.setup_bitness(64)
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else:
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self.setup_bitness(32)
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return self.binencode_imm(int(register[1:]), outsize)
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def setup_register(self, regfield, register):
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encoded = self.encode_register(register)
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regfield[:] = encoded
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# Instruction filing at instanciation
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def setup_immediat(self, immfield, value):
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immsize = len(immfield)
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immfield[:] = self.binencode_imm(value, immsize)
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return True
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# C4.1.93 Data Processing - Immediate
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class DataProcessingImmediate(InstructionEncoding):
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def __init__(self):
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super(DataProcessingImmediate, self).__init__()
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self.bits[26:29] = bytearray((0,0,1))
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self.op0 = self.bits[29:31]
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self.op1 = self.bits[22:26]
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class AddSubtractImmediate(DataProcessingImmediate):
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SF = True
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RD = True
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RN = True
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IMM12 = True
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SH = True
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def __init__(self, argsdict):
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super(AddSubtractImmediate, self).__init__()
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self.sf = self.bits[31:32] # Keep it a memoryview
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self.op = self.bits[30:31] # Keep it a memoryview
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self.S = self.bits[29:30] # Keep it a memoryview
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self.bits[23:29] = bytearray((0, 1, 0, 0, 0, 1))
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self.sh = self.bits[22:23]
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self.imm12 = self.bits[10:22]
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self.rn = self.bits[5:10]
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self.rd = self.bits[0:5]
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for name, value in self.ENCODING_VALUES.items():
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print("{0} setting {1} to {2}".format(type(self).__name__, name, value))
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if isinstance(value, int):
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value = bytearray((value,))
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# self.x[:] = value
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getattr(self, name)[:] = value
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# Change instruction based of parameter
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self.setup_register(self.rd, argsdict[0])
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self.setup_register(self.rn, argsdict[1])
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self.setup_immediat(self.imm12, argsdict[2])
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@classmethod
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def accept_arg(cls, argsdict):
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return (cls.is_register(argsdict[0], accept_sp=True) and
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cls.is_register(argsdict[1], accept_sp=True) and
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cls.is_imm12(argsdict[2]) and
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cls.is_shift(argsdict.get(3)))
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class Instruction(object):
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encoding = []
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def __init__(self, *args):
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argsdict = dict(enumerate(args)) # Like a list but allow arg.get(4)
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for encodcls in self.encoding:
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if encodcls.accept_arg(argsdict):
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self.encoded = encodcls(argsdict)
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return
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raise ValueError("Cannot encode <{0} {1}>:(".format(type(self).__name__, args))
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def get_code(self):
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intlist = list(self.encoded.bits)
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if not is_py3:
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intlist = [ord(x) for x in intlist]
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# Our encoding to real little-endian
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encoding_getter = operator.itemgetter(7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8, 23, 22, 21, 20, 19, 18, 17, 16, 31, 30, 29, 28, 27, 26, 25, 24)
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dword = 0
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for bit in encoding_getter(intlist):
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assert bit in (0, 1), "Unexpected bite value in encoding of {0} : {1} in {2}".format(type(self).__name__, bit, intlist)
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dword = (dword << 1) | bit
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return struct.pack(">I", dword) # We already have handled endianess
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# Fix endianned
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class Add(Instruction):
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encoding = [AddSubtractImmediate.gen(op=0, S=0)]
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class Subs(Instruction):
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encoding = [AddSubtractImmediate.gen(op=1, S=1)]
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