mirror of
https://github.com/icicle-emu/icicle-python
synced 2026-06-21 13:53:41 +00:00
Merge pull request #5 from icicle-emu/minor-improvements
Minor improvements
This commit is contained in:
Duncan Ogilvie
Generated
+195
-251
@@ -1,12 +1,12 @@
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|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "597a5118570b68bc08d8d59125332c54f1ba9d9adeedeef5b99b02ba2b0698f8"
|
||||
|
||||
[[package]]
|
||||
name = "windows_aarch64_gnullvm"
|
||||
version = "0.52.5"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "7088eed71e8b8dda258ecc8bac5fb1153c5cffaf2578fc8ff5d61e23578d3263"
|
||||
checksum = "32a4622180e7a0ec044bb555404c800bc9fd9ec262ec147edd5989ccd0c02cd3"
|
||||
|
||||
[[package]]
|
||||
name = "windows_aarch64_msvc"
|
||||
version = "0.42.2"
|
||||
version = "0.52.6"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "e08e8864a60f06ef0d0ff4ba04124db8b0fb3be5776a5cd47641e942e58c4d43"
|
||||
|
||||
[[package]]
|
||||
name = "windows_aarch64_msvc"
|
||||
version = "0.52.5"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "9985fd1504e250c615ca5f281c3f7a6da76213ebd5ccc9561496568a2752afb6"
|
||||
checksum = "09ec2a7bb152e2252b53fa7803150007879548bc709c039df7627cabbd05d469"
|
||||
|
||||
[[package]]
|
||||
name = "windows_i686_gnu"
|
||||
version = "0.42.2"
|
||||
version = "0.52.6"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "c61d927d8da41da96a81f029489353e68739737d3beca43145c8afec9a31a84f"
|
||||
|
||||
[[package]]
|
||||
name = "windows_i686_gnu"
|
||||
version = "0.52.5"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "88ba073cf16d5372720ec942a8ccbf61626074c6d4dd2e745299726ce8b89670"
|
||||
checksum = "8e9b5ad5ab802e97eb8e295ac6720e509ee4c243f69d781394014ebfe8bbfa0b"
|
||||
|
||||
[[package]]
|
||||
name = "windows_i686_gnullvm"
|
||||
version = "0.52.5"
|
||||
version = "0.52.6"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "87f4261229030a858f36b459e748ae97545d6f1ec60e5e0d6a3d32e0dc232ee9"
|
||||
checksum = "0eee52d38c090b3caa76c563b86c3a4bd71ef1a819287c19d586d7334ae8ed66"
|
||||
|
||||
[[package]]
|
||||
name = "windows_i686_msvc"
|
||||
version = "0.42.2"
|
||||
version = "0.52.6"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "44d840b6ec649f480a41c8d80f9c65108b92d89345dd94027bfe06ac444d1060"
|
||||
|
||||
[[package]]
|
||||
name = "windows_i686_msvc"
|
||||
version = "0.52.5"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "db3c2bf3d13d5b658be73463284eaf12830ac9a26a90c717b7f771dfe97487bf"
|
||||
checksum = "240948bc05c5e7c6dabba28bf89d89ffce3e303022809e73deaefe4f6ec56c66"
|
||||
|
||||
[[package]]
|
||||
name = "windows_x86_64_gnu"
|
||||
version = "0.42.2"
|
||||
version = "0.52.6"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "8de912b8b8feb55c064867cf047dda097f92d51efad5b491dfb98f6bbb70cb36"
|
||||
|
||||
[[package]]
|
||||
name = "windows_x86_64_gnu"
|
||||
version = "0.52.5"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "4e4246f76bdeff09eb48875a0fd3e2af6aada79d409d33011886d3e1581517d9"
|
||||
checksum = "147a5c80aabfbf0c7d901cb5895d1de30ef2907eb21fbbab29ca94c5b08b1a78"
|
||||
|
||||
[[package]]
|
||||
name = "windows_x86_64_gnullvm"
|
||||
version = "0.42.2"
|
||||
version = "0.52.6"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "26d41b46a36d453748aedef1486d5c7a85db22e56aff34643984ea85514e94a3"
|
||||
|
||||
[[package]]
|
||||
name = "windows_x86_64_gnullvm"
|
||||
version = "0.52.5"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "852298e482cd67c356ddd9570386e2862b5673c85bd5f88df9ab6802b334c596"
|
||||
checksum = "24d5b23dc417412679681396f2b49f3de8c1473deb516bd34410872eff51ed0d"
|
||||
|
||||
[[package]]
|
||||
name = "windows_x86_64_msvc"
|
||||
version = "0.42.2"
|
||||
version = "0.52.6"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "9aec5da331524158c6d1a4ac0ab1541149c0b9505fde06423b02f5ef0106b9f0"
|
||||
|
||||
[[package]]
|
||||
name = "windows_x86_64_msvc"
|
||||
version = "0.52.5"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "bec47e5bfd1bff0eeaf6d8b485cc1074891a197ab4225d504cb7a1ab88b02bf0"
|
||||
checksum = "589f6da84c646204747d1270a2a5661ea66ed1cced2631d546fdfb155959f9ec"
|
||||
|
||||
[[package]]
|
||||
name = "xml-rs"
|
||||
|
||||
+3
-3
@@ -2,7 +2,7 @@
|
||||
|
||||
[package]
|
||||
name = "icicle-python"
|
||||
version = "0.0.4"
|
||||
version = "0.0.5"
|
||||
edition = "2021"
|
||||
|
||||
[lib]
|
||||
@@ -15,10 +15,10 @@ icicle-vm = { path = "icicle-emu/icicle-vm" }
|
||||
pcode = { path = "icicle-emu/sleigh/pcode" }
|
||||
sleigh-runtime = { path = "icicle-emu/sleigh/sleigh-runtime" }
|
||||
indexmap = "2.2.6"
|
||||
pyo3 = { version = "0.21.2", features = ["extension-module", "indexmap", "abi3-py37"] }
|
||||
pyo3 = { version = "0.23.2", features = ["extension-module", "indexmap", "abi3-py37"] }
|
||||
target-lexicon = "0.12.7"
|
||||
tracing = "*"
|
||||
tracing-subscriber = "0.3.17"
|
||||
|
||||
[build-dependencies]
|
||||
pyo3-build-config = "0.21.2"
|
||||
pyo3-build-config = "0.23.2"
|
||||
|
||||
+1
-1
Submodule icicle-emu updated: 0acbf76a49...964dabb727
@@ -79,14 +79,17 @@ class Icicle:
|
||||
def __init__(self, architecture: str, *,
|
||||
jit = True,
|
||||
jit_mem = True,
|
||||
shadow_stack = True,
|
||||
shadow_stack = False,
|
||||
recompilation = True,
|
||||
track_uninitialized = False,
|
||||
optimize_instructions = True,
|
||||
optimize_block = True,
|
||||
optimize_block = False,
|
||||
tracing = False,
|
||||
) -> None: ...
|
||||
|
||||
@property
|
||||
def architecture(self) -> str: ...
|
||||
|
||||
@property
|
||||
def exception_code(self) -> ExceptionCode: ...
|
||||
|
||||
|
||||
+49
-41
@@ -14,9 +14,9 @@ use sleigh_runtime::NamedRegister;
|
||||
// - https://pyo3.rs/main/conversions/tables
|
||||
// - https://pyo3.rs/main/class
|
||||
|
||||
#[pyclass(module = "icicle")]
|
||||
#[derive(Clone)]
|
||||
enum MemoryProtection {
|
||||
#[pyclass(eq, eq_int, module = "icicle")]
|
||||
#[derive(Clone, Debug, PartialEq)]
|
||||
pub enum MemoryProtection {
|
||||
NoAccess,
|
||||
ReadOnly,
|
||||
ReadWrite,
|
||||
@@ -25,9 +25,9 @@ enum MemoryProtection {
|
||||
ExecuteReadWrite,
|
||||
}
|
||||
|
||||
#[pyclass(module = "icicle")]
|
||||
#[derive(Clone)]
|
||||
enum RunStatus {
|
||||
#[pyclass(eq, eq_int, module = "icicle")]
|
||||
#[derive(Clone, Debug, PartialEq)]
|
||||
pub enum RunStatus {
|
||||
/// The VM is still running.
|
||||
Running,
|
||||
|
||||
@@ -59,8 +59,9 @@ enum RunStatus {
|
||||
UnhandledException,
|
||||
}
|
||||
|
||||
#[pyclass(module = "icicle")]
|
||||
enum MemoryExceptionCode {
|
||||
#[pyclass(eq, eq_int, module = "icicle")]
|
||||
#[derive(Clone, Debug, PartialEq)]
|
||||
pub enum MemoryExceptionCode {
|
||||
Unallocated,
|
||||
Unmapped,
|
||||
UnmappedRegister,
|
||||
@@ -98,9 +99,9 @@ impl From<MemError> for MemoryExceptionCode {
|
||||
}
|
||||
}
|
||||
|
||||
#[pyclass(module = "icicle", name = "ExceptionCode")]
|
||||
#[derive(Clone)]
|
||||
enum ExceptionCodePy {
|
||||
#[pyclass(eq, eq_int, module = "icicle", name = "ExceptionCode")]
|
||||
#[derive(Clone, Debug, PartialEq)]
|
||||
pub enum ExceptionCodePy {
|
||||
NoException = 0x0000,
|
||||
|
||||
InstructionLimit = 0x0001,
|
||||
@@ -219,7 +220,8 @@ fn convert_protection(protection: MemoryProtection) -> u8 {
|
||||
}
|
||||
|
||||
#[pyclass(unsendable, module = "icicle")]
|
||||
struct Icicle {
|
||||
pub struct Icicle {
|
||||
architecture: String,
|
||||
vm: icicle_vm::Vm,
|
||||
regs: HashMap<String, NamedRegister>,
|
||||
}
|
||||
@@ -240,48 +242,53 @@ fn reg_find<'a>(i: &'a Icicle, name: &str) -> PyResult<&'a NamedRegister> {
|
||||
#[pymethods]
|
||||
impl Icicle {
|
||||
#[getter]
|
||||
fn get_icount_limit(&mut self) -> u64 {
|
||||
pub fn get_icount_limit(&mut self) -> u64 {
|
||||
self.vm.icount_limit
|
||||
}
|
||||
|
||||
#[setter]
|
||||
fn set_icount_limit(&mut self, value: u64) {
|
||||
pub fn set_icount_limit(&mut self, value: u64) {
|
||||
self.vm.icount_limit = value;
|
||||
}
|
||||
|
||||
#[getter]
|
||||
fn get_icount(&mut self) -> u64 {
|
||||
pub fn get_icount(&mut self) -> u64 {
|
||||
return self.vm.cpu.icount;
|
||||
}
|
||||
|
||||
#[setter]
|
||||
fn set_icount(&mut self, value: u64) {
|
||||
pub fn set_icount(&mut self, value: u64) {
|
||||
self.vm.cpu.icount = value;
|
||||
}
|
||||
|
||||
#[getter]
|
||||
fn get_exception_code(&self) -> ExceptionCodePy {
|
||||
pub fn get_exception_code(&self) -> ExceptionCodePy {
|
||||
ExceptionCode::from_u32(self.vm.cpu.exception.code).into()
|
||||
}
|
||||
|
||||
#[getter]
|
||||
fn get_exception_value(&self) -> u64 {
|
||||
pub fn get_exception_value(&self) -> u64 {
|
||||
self.vm.cpu.exception.value
|
||||
}
|
||||
|
||||
#[getter]
|
||||
pub fn get_architecture(&self) -> String {
|
||||
self.architecture.to_string()
|
||||
}
|
||||
|
||||
#[new]
|
||||
#[pyo3(signature = (
|
||||
architecture,
|
||||
jit = true,
|
||||
jit_mem = true,
|
||||
shadow_stack = true,
|
||||
shadow_stack = false,
|
||||
recompilation = true,
|
||||
track_uninitialized = false,
|
||||
optimize_instructions = true,
|
||||
optimize_block = true,
|
||||
optimize_block = false,
|
||||
tracing = false,
|
||||
))]
|
||||
fn new(
|
||||
pub fn new(
|
||||
architecture: String,
|
||||
jit: bool,
|
||||
jit_mem: bool,
|
||||
@@ -341,22 +348,23 @@ impl Icicle {
|
||||
}
|
||||
|
||||
Ok(Icicle {
|
||||
architecture,
|
||||
vm,
|
||||
regs,
|
||||
})
|
||||
}
|
||||
|
||||
fn __str__(&mut self) -> String {
|
||||
pub fn __str__(&mut self) -> String {
|
||||
let arch = &self.vm.cpu.arch;
|
||||
let endianness = if arch.sleigh.big_endian {
|
||||
"big endian"
|
||||
} else {
|
||||
"little endian"
|
||||
};
|
||||
format!("Icicle VM for {0:?} ({endianness})", arch.triple.architecture)
|
||||
format!("Icicle VM for {0:?} ({endianness})", self.architecture)
|
||||
}
|
||||
|
||||
fn mem_map(&mut self, address: u64, size: u64, protection: MemoryProtection) -> PyResult<()> {
|
||||
pub fn mem_map(&mut self, address: u64, size: u64, protection: MemoryProtection) -> PyResult<()> {
|
||||
let mapping = Mapping {
|
||||
perm: convert_protection(protection),
|
||||
value: 0,
|
||||
@@ -373,7 +381,7 @@ impl Icicle {
|
||||
}
|
||||
}
|
||||
|
||||
fn mem_unmap(&mut self, address: u64, size: u64) -> PyResult<()> {
|
||||
pub fn mem_unmap(&mut self, address: u64, size: u64) -> PyResult<()> {
|
||||
if self.vm.cpu.mem.unmap_memory_len(address, size) {
|
||||
Ok(())
|
||||
} else {
|
||||
@@ -386,7 +394,7 @@ impl Icicle {
|
||||
}
|
||||
}
|
||||
|
||||
fn mem_protect(&mut self, address: u64, size: usize, protection: MemoryProtection) -> PyResult<()> {
|
||||
pub fn mem_protect(&mut self, address: u64, size: usize, protection: MemoryProtection) -> PyResult<()> {
|
||||
self.vm.cpu.mem.update_perm(address, size as u64, convert_protection(protection))
|
||||
.map_err(|e| {
|
||||
raise_MemoryException(
|
||||
@@ -397,7 +405,7 @@ impl Icicle {
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn mem_read(&mut self, address: u64, size: usize) -> PyResult<Cow<[u8]>> {
|
||||
pub fn mem_read(&mut self, address: u64, size: usize) -> PyResult<Cow<[u8]>> {
|
||||
// Allocate a buffer
|
||||
let mut buffer = Vec::with_capacity(size);
|
||||
buffer.resize(size, 0);
|
||||
@@ -413,7 +421,7 @@ impl Icicle {
|
||||
return Ok(Cow::Owned(buffer));
|
||||
}
|
||||
|
||||
fn mem_write(&mut self, address: u64, data: Vec<u8>) -> PyResult<()> {
|
||||
pub fn mem_write(&mut self, address: u64, data: Vec<u8>) -> PyResult<()> {
|
||||
let size = data.len();
|
||||
self.vm.cpu.mem.write_bytes(address, &data[..], perm::NONE)
|
||||
.map_err(|e| {
|
||||
@@ -424,7 +432,7 @@ impl Icicle {
|
||||
})
|
||||
}
|
||||
|
||||
fn reg_list(&self) -> PyResult<IndexMap<String, (u32, u8)>> {
|
||||
pub fn reg_list(&self) -> PyResult<IndexMap<String, (u32, u8)>> {
|
||||
let mut result = IndexMap::new();
|
||||
let sleigh = self.vm.cpu.sleigh();
|
||||
for reg in &sleigh.named_registers {
|
||||
@@ -434,27 +442,27 @@ impl Icicle {
|
||||
return Ok(result);
|
||||
}
|
||||
|
||||
fn reg_offset(&self, name: &str) -> PyResult<u32> {
|
||||
pub fn reg_offset(&self, name: &str) -> PyResult<u32> {
|
||||
Ok(reg_find(self, name)?.offset)
|
||||
}
|
||||
|
||||
fn reg_size(&self, name: &str) -> PyResult<u8> {
|
||||
pub fn reg_size(&self, name: &str) -> PyResult<u8> {
|
||||
Ok(reg_find(self, name)?.var.size)
|
||||
}
|
||||
|
||||
fn reg_read(&mut self, name: &str) -> PyResult<u64> {
|
||||
pub fn reg_read(&mut self, name: &str) -> PyResult<u64> {
|
||||
Ok(self.vm.cpu.read_reg(reg_find(self, name)?.var))
|
||||
}
|
||||
|
||||
fn reg_write(&mut self, name: &str, value: u64) -> PyResult<()> {
|
||||
pub fn reg_write(&mut self, name: &str, value: u64) -> PyResult<()> {
|
||||
Ok(self.vm.cpu.write_reg(reg_find(self, name)?.var, value))
|
||||
}
|
||||
|
||||
fn reset(&mut self) {
|
||||
pub fn reset(&mut self) {
|
||||
self.vm.reset();
|
||||
}
|
||||
|
||||
fn run(&mut self) -> RunStatus {
|
||||
pub fn run(&mut self) -> RunStatus {
|
||||
match self.vm.run() {
|
||||
VmExit::Running => RunStatus::Running,
|
||||
VmExit::InstructionLimit => RunStatus::InstructionLimit,
|
||||
@@ -469,7 +477,7 @@ impl Icicle {
|
||||
}
|
||||
}
|
||||
|
||||
fn run_until(&mut self, address: u64) -> RunStatus {
|
||||
pub fn run_until(&mut self, address: u64) -> RunStatus {
|
||||
let breakpoint_added = self.vm.add_breakpoint(address);
|
||||
let status = self.run();
|
||||
if breakpoint_added {
|
||||
@@ -478,7 +486,7 @@ impl Icicle {
|
||||
status
|
||||
}
|
||||
|
||||
fn step(&mut self, count: u64) -> RunStatus {
|
||||
pub fn step(&mut self, count: u64) -> RunStatus {
|
||||
let old_limit = self.vm.icount_limit;
|
||||
self.vm.icount_limit = self.vm.cpu.icount.saturating_add(count);
|
||||
let status = self.run();
|
||||
@@ -486,17 +494,17 @@ impl Icicle {
|
||||
status
|
||||
}
|
||||
|
||||
fn add_breakpoint(&mut self, address: u64) -> bool {
|
||||
pub fn add_breakpoint(&mut self, address: u64) -> bool {
|
||||
self.vm.add_breakpoint(address)
|
||||
}
|
||||
|
||||
fn remove_breakpoint(&mut self, address: u64) -> bool {
|
||||
pub fn remove_breakpoint(&mut self, address: u64) -> bool {
|
||||
self.vm.remove_breakpoint(address)
|
||||
}
|
||||
}
|
||||
|
||||
#[pyfunction]
|
||||
fn architectures() -> PyResult<Vec<&'static str>> {
|
||||
pub fn architectures() -> PyResult<Vec<&'static str>> {
|
||||
Ok(vec![
|
||||
"i686",
|
||||
"x86_64",
|
||||
@@ -508,7 +516,7 @@ fn architectures() -> PyResult<Vec<&'static str>> {
|
||||
/// the `lib.name` setting in the `Cargo.toml`, else Python will not be able to
|
||||
/// import the module.
|
||||
#[pymodule]
|
||||
fn icicle(_: Python<'_>, m: &PyModule) -> PyResult<()> {
|
||||
fn icicle(m: &Bound<'_, PyModule>) -> PyResult<()> {
|
||||
m.add_function(wrap_pyfunction!(architectures, m)?)?;
|
||||
m.add_class::<Icicle>()?;
|
||||
m.add_class::<MemoryProtection>()?;
|
||||
|
||||
+100
-306
@@ -1,281 +1,11 @@
|
||||
use std::borrow::Cow;
|
||||
use std::collections::HashMap;
|
||||
use icicle_cpu::mem::{Mapping, perm};
|
||||
use icicle_cpu::{VmExit};
|
||||
use icicle_vm;
|
||||
use icicle_vm::linux::LinuxCpu;
|
||||
use target_lexicon;
|
||||
use indexmap::IndexMap;
|
||||
use sleigh_runtime::NamedRegister;
|
||||
#![allow(special_module_name)]
|
||||
mod lib;
|
||||
|
||||
#[allow(dead_code)]
|
||||
#[derive(Clone)]
|
||||
enum MemoryProtection {
|
||||
NoAccess,
|
||||
ReadOnly,
|
||||
ReadWrite,
|
||||
ExecuteOnly,
|
||||
ExecuteRead,
|
||||
ExecuteReadWrite,
|
||||
}
|
||||
use lib::*;
|
||||
use pyo3::PyResult;
|
||||
|
||||
struct Icicle {
|
||||
vm: icicle_vm::Vm,
|
||||
regs: HashMap<String, NamedRegister>,
|
||||
}
|
||||
|
||||
fn convert_protection(protection: MemoryProtection) -> u8 {
|
||||
match protection {
|
||||
MemoryProtection::NoAccess => perm::NONE,
|
||||
MemoryProtection::ReadOnly => perm::READ,
|
||||
MemoryProtection::ReadWrite => perm::READ | perm::WRITE,
|
||||
MemoryProtection::ExecuteOnly => perm::EXEC,
|
||||
MemoryProtection::ExecuteRead => perm::EXEC | perm::READ,
|
||||
MemoryProtection::ExecuteReadWrite => perm::EXEC | perm::READ | perm::WRITE,
|
||||
}
|
||||
}
|
||||
|
||||
fn reg_find<'a>(i: &'a Icicle, name: &str) -> Result<&'a NamedRegister, String> {
|
||||
let sleigh = i.vm.cpu.sleigh();
|
||||
match sleigh.get_reg(name) {
|
||||
None => {
|
||||
i.regs.get(name.to_lowercase().as_str())
|
||||
.ok_or(
|
||||
format!("Register not found: {name}")
|
||||
)
|
||||
}
|
||||
Some(r) => Ok(r),
|
||||
}
|
||||
}
|
||||
|
||||
impl Icicle {
|
||||
#[allow(dead_code)]
|
||||
fn get_icount_limit(&mut self) -> u64 {
|
||||
self.vm.icount_limit
|
||||
}
|
||||
|
||||
#[allow(dead_code)]
|
||||
fn set_icount_limit(&mut self, value: u64) {
|
||||
self.vm.icount_limit = value;
|
||||
}
|
||||
|
||||
#[allow(dead_code)]
|
||||
fn get_icount(&mut self) -> u64 {
|
||||
return self.vm.cpu.icount;
|
||||
}
|
||||
|
||||
#[allow(dead_code)]
|
||||
fn set_icount(&mut self, value: u64) {
|
||||
self.vm.cpu.icount = value;
|
||||
}
|
||||
|
||||
fn new(
|
||||
architecture: String,
|
||||
jit: bool,
|
||||
jit_mem: bool,
|
||||
shadow_stack: bool,
|
||||
recompilation: bool,
|
||||
track_uninitialized: bool,
|
||||
optimize_instructions: bool,
|
||||
optimize_block: bool,
|
||||
tracing: bool,
|
||||
) -> Result<Self, String> {
|
||||
// Prevent mixing '_' and '-'
|
||||
if architecture.split("-").count() != 1 {
|
||||
return Err(
|
||||
format!("Bad architecture format: {architecture}")
|
||||
);
|
||||
}
|
||||
|
||||
// TODO: support instantiating this multiple times
|
||||
if tracing {
|
||||
tracing_subscriber::fmt()
|
||||
.with_max_level(tracing::Level::DEBUG)
|
||||
.with_target(false)
|
||||
.init();
|
||||
}
|
||||
|
||||
// Setup the CPU state for the target triple
|
||||
let mut config = icicle_vm::cpu::Config::from_target_triple(
|
||||
format!("{architecture}-none").as_str()
|
||||
);
|
||||
if config.triple.architecture == target_lexicon::Architecture::Unknown {
|
||||
return Err(
|
||||
format!("Unknown architecture: {architecture}")
|
||||
);
|
||||
}
|
||||
|
||||
// Configuration
|
||||
config.enable_jit = jit;
|
||||
config.enable_jit_mem = jit_mem;
|
||||
config.enable_shadow_stack = shadow_stack;
|
||||
config.enable_recompilation = recompilation;
|
||||
config.track_uninitialized = track_uninitialized;
|
||||
config.optimize_instructions = optimize_instructions;
|
||||
config.optimize_block = optimize_block;
|
||||
|
||||
let vm = icicle_vm::build(&config)
|
||||
.map_err(|e| {
|
||||
format!("VM build error: {e}")
|
||||
})?;
|
||||
|
||||
// Populate the lowercase register map
|
||||
let mut regs = HashMap::new();
|
||||
let sleigh = vm.cpu.sleigh();
|
||||
for reg in &sleigh.named_registers {
|
||||
let name = sleigh.get_str(reg.name);
|
||||
regs.insert(name.to_lowercase(), reg.clone());
|
||||
}
|
||||
|
||||
Ok(Icicle {
|
||||
vm,
|
||||
regs,
|
||||
})
|
||||
}
|
||||
|
||||
fn __str__(&mut self) -> String {
|
||||
let arch = &self.vm.cpu.arch;
|
||||
let endianness = if arch.sleigh.big_endian {
|
||||
"big endian"
|
||||
} else {
|
||||
"little endian"
|
||||
};
|
||||
format!("Icicle VM for {0:?} ({endianness})", arch.triple.architecture)
|
||||
}
|
||||
|
||||
fn mem_map(&mut self, address: u64, size: u64, protection: MemoryProtection) -> Result<(), String> {
|
||||
let mapping = Mapping {
|
||||
perm: convert_protection(protection),
|
||||
value: 0,
|
||||
};
|
||||
if self.vm.cpu.mem.map_memory_len(address, size, mapping) {
|
||||
Ok(())
|
||||
} else {
|
||||
Err(
|
||||
format!("Failed to map memory {address:X}[{size:X}]")
|
||||
)
|
||||
}
|
||||
}
|
||||
|
||||
#[allow(dead_code)]
|
||||
fn mem_unmap(&mut self, address: u64, size: u64) -> Result<(), String> {
|
||||
if self.vm.cpu.mem.unmap_memory_len(address, size) {
|
||||
Ok(())
|
||||
} else {
|
||||
Err(
|
||||
format!("Failed to unmap memory {address:X}[{size:X}]")
|
||||
)
|
||||
}
|
||||
}
|
||||
|
||||
fn mem_protect(&mut self, address: u64, size: usize, protection: MemoryProtection) -> Result<(), String> {
|
||||
self.vm.cpu.mem.update_perm(address, size as u64, convert_protection(protection))
|
||||
.map_err(|_| {
|
||||
format!("Failed to protect memory {address:X}[{size:X}]")
|
||||
})?;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
#[allow(dead_code)]
|
||||
fn mem_read(&mut self, address: u64, size: usize) -> Result<Cow<[u8]>, String> {
|
||||
// Allocate a buffer
|
||||
let mut buffer = Vec::with_capacity(size);
|
||||
buffer.resize(size, 0);
|
||||
|
||||
// Read the memory
|
||||
match self.vm.cpu.mem.read_bytes(address, &mut buffer[..], perm::NONE) {
|
||||
Ok(_) => Ok(Cow::Owned(buffer)),
|
||||
Err(_) => Err(format!("Failed to read memory {address:X}[{size:X}]"))
|
||||
}
|
||||
}
|
||||
|
||||
fn mem_write(&mut self, address: u64, data: Vec<u8>) -> Result<(), String> {
|
||||
let size = data.len();
|
||||
match self.vm.cpu.mem.write_bytes(address, &data[..], perm::NONE) {
|
||||
Ok(_) => Ok(()),
|
||||
Err(_) => Err(format!("Failed to write memory {address:X}[{size:X}]"))
|
||||
}
|
||||
}
|
||||
|
||||
#[allow(dead_code)]
|
||||
fn reg_list(&self) -> IndexMap<String, (u32, u8)> {
|
||||
let mut result = IndexMap::new();
|
||||
let sleigh = self.vm.cpu.sleigh();
|
||||
for reg in &sleigh.named_registers {
|
||||
let name = sleigh.get_str(reg.name);
|
||||
result.insert(name.to_string(), (reg.offset, reg.var.size));
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
#[allow(dead_code)]
|
||||
fn reg_offset(&self, name: &str) -> Result<u32, String> {
|
||||
Ok(reg_find(self, name)?.offset)
|
||||
}
|
||||
|
||||
#[allow(dead_code)]
|
||||
fn reg_size(&self, name: &str) -> Result<u8, String> {
|
||||
Ok(reg_find(self, name)?.var.size)
|
||||
}
|
||||
|
||||
fn reg_read(&mut self, name: &str) -> Result<u64, String> {
|
||||
Ok(self.vm.cpu.read_reg(reg_find(self, name)?.var))
|
||||
}
|
||||
|
||||
fn reg_write(&mut self, name: &str, value: u64) -> Result<(), String> {
|
||||
Ok(self.vm.cpu.write_reg(reg_find(self, name)?.var, value))
|
||||
}
|
||||
|
||||
#[allow(dead_code)]
|
||||
fn reset(&mut self) {
|
||||
self.vm.reset();
|
||||
}
|
||||
|
||||
fn run(&mut self) -> VmExit {
|
||||
self.vm.run()
|
||||
}
|
||||
|
||||
#[allow(dead_code)]
|
||||
fn run_until(&mut self, address: u64) -> VmExit {
|
||||
let breakpoint_added = self.vm.add_breakpoint(address);
|
||||
let status = self.run();
|
||||
if breakpoint_added {
|
||||
self.vm.remove_breakpoint(address);
|
||||
}
|
||||
status
|
||||
}
|
||||
|
||||
#[allow(dead_code)]
|
||||
fn step(&mut self, count: u64) -> VmExit {
|
||||
let old_limit = self.vm.icount_limit;
|
||||
self.vm.icount_limit = self.vm.cpu.icount.saturating_add(count);
|
||||
let status = self.run();
|
||||
self.vm.icount_limit = old_limit;
|
||||
status
|
||||
}
|
||||
|
||||
#[allow(dead_code)]
|
||||
fn add_breakpoint(&mut self, address: u64) -> bool {
|
||||
self.vm.add_breakpoint(address)
|
||||
}
|
||||
|
||||
#[allow(dead_code)]
|
||||
fn remove_breakpoint(&mut self, address: u64) -> bool {
|
||||
self.vm.remove_breakpoint(address)
|
||||
}
|
||||
}
|
||||
|
||||
#[allow(dead_code)]
|
||||
fn architectures() -> Result<Vec<&'static str>, String> {
|
||||
Ok(vec![
|
||||
"i686",
|
||||
"x86_64",
|
||||
"aarch64",
|
||||
])
|
||||
}
|
||||
|
||||
fn nx_start() {
|
||||
let mut vm = Icicle::new(
|
||||
fn nx_start() -> PyResult<()> {
|
||||
let mut vm: Icicle = Icicle::new(
|
||||
"x86_64".to_string(),
|
||||
false,
|
||||
true,
|
||||
@@ -285,19 +15,21 @@ fn nx_start() {
|
||||
true,
|
||||
true,
|
||||
false,
|
||||
).unwrap();
|
||||
)?;
|
||||
let page = 0x10000;
|
||||
vm.mem_map(page, 0x1000, MemoryProtection::ReadOnly).unwrap();
|
||||
vm.mem_map(page, 0x1000, MemoryProtection::ReadOnly)?;
|
||||
// <non-executable memory> inc eax; ret
|
||||
vm.mem_write(page, b"\xFF\xC0\xC3".to_vec()).unwrap();
|
||||
vm.reg_write("rip", page).unwrap();
|
||||
vm.mem_write(page, b"\xFF\xC0\xC3".to_vec())?;
|
||||
vm.reg_write("rip", page)?;
|
||||
let status = vm.run();
|
||||
println!("status: {:?}", status);
|
||||
println!("rip: {:#x}", vm.reg_read("rip").unwrap());
|
||||
println!("rip: {:#x}", vm.reg_read("rip")?);
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn nx_middle() {
|
||||
let mut vm = Icicle::new(
|
||||
fn nx_middle() -> PyResult<()> {
|
||||
let mut vm: Icicle = Icicle::new(
|
||||
"x86_64".to_string(),
|
||||
false,
|
||||
true,
|
||||
@@ -307,22 +39,24 @@ fn nx_middle() {
|
||||
true,
|
||||
true,
|
||||
false,
|
||||
).unwrap();
|
||||
)?;
|
||||
let page = 0x10000;
|
||||
vm.mem_map(page, 0x2000, MemoryProtection::ExecuteRead).unwrap();
|
||||
vm.mem_protect(page + 0x1000, 0x1000, MemoryProtection::ReadOnly).unwrap();
|
||||
vm.mem_map(page, 0x2000, MemoryProtection::ExecuteRead)?;
|
||||
vm.mem_protect(page + 0x1000, 0x1000, MemoryProtection::ReadOnly)?;
|
||||
// inc eax; inc eax; <transition to non-executable region>; ret
|
||||
let rip = page + 0x1000 - 2;
|
||||
vm.mem_write(rip, b"\xFF\xC0\xFF\xC0\xC3".to_vec()).unwrap();
|
||||
vm.reg_write("rip", rip).unwrap();
|
||||
vm.mem_write(rip, b"\xFF\xC0\xFF\xC0\xC3".to_vec())?;
|
||||
vm.reg_write("rip", rip)?;
|
||||
let status = vm.run();
|
||||
println!("status: {:?}", status);
|
||||
println!("rip: {:#x}", vm.reg_read("rip").unwrap());
|
||||
println!("rax: {:#x}", vm.reg_read("rax").unwrap());
|
||||
println!("rip: {:#x}", vm.reg_read("rip")?);
|
||||
println!("rax: {:#x}", vm.reg_read("rax")?);
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn inv_start() {
|
||||
let mut vm = Icicle::new(
|
||||
fn inv_start() -> PyResult<()> {
|
||||
let mut vm: Icicle = Icicle::new(
|
||||
"x86_64".to_string(),
|
||||
false,
|
||||
true,
|
||||
@@ -332,20 +66,22 @@ fn inv_start() {
|
||||
true,
|
||||
true,
|
||||
false,
|
||||
).unwrap();
|
||||
)?;
|
||||
let page = 0x10000;
|
||||
vm.mem_map(page, 0x1000, MemoryProtection::ExecuteRead).unwrap();
|
||||
vm.mem_map(page, 0x1000, MemoryProtection::ExecuteRead)?;
|
||||
// <invalid>; ret
|
||||
vm.mem_write(page, b"\xFF\xFF\xC3".to_vec()).unwrap();
|
||||
vm.reg_write("rip", page).unwrap();
|
||||
vm.mem_write(page, b"\xFF\xFF\xC3".to_vec())?;
|
||||
vm.reg_write("rip", page)?;
|
||||
let status = vm.run();
|
||||
println!("status: {:?}", status);
|
||||
println!("rip: {:#x}", vm.reg_read("rip").unwrap());
|
||||
println!("rax: {:#x}", vm.reg_read("rax").unwrap());
|
||||
println!("rip: {:#x}", vm.reg_read("rip")?);
|
||||
println!("rax: {:#x}", vm.reg_read("rax")?);
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn inv_middle() {
|
||||
let mut vm = Icicle::new(
|
||||
fn inv_middle() -> PyResult<()> {
|
||||
let mut vm: Icicle = Icicle::new(
|
||||
"x86_64".to_string(),
|
||||
false,
|
||||
true,
|
||||
@@ -355,19 +91,75 @@ fn inv_middle() {
|
||||
true,
|
||||
true,
|
||||
false,
|
||||
).unwrap();
|
||||
)?;
|
||||
let page = 0x10000;
|
||||
vm.mem_map(page, 0x1000, MemoryProtection::ExecuteRead).unwrap();
|
||||
vm.mem_map(page, 0x1000, MemoryProtection::ExecuteRead)?;
|
||||
// inc eax; <invalid>; ret
|
||||
vm.mem_write(page, b"\xFF\xC0\xFF\xFF\xC3".to_vec()).unwrap();
|
||||
vm.reg_write("rip", page).unwrap();
|
||||
vm.mem_write(page, b"\xFF\xC0\xFF\xFF\xC3".to_vec())?;
|
||||
vm.reg_write("rip", page)?;
|
||||
let status = vm.run();
|
||||
println!("status: {:?}", status);
|
||||
println!("rip: {:#x}", vm.reg_read("rip").unwrap());
|
||||
println!("rax: {:#x}", vm.reg_read("rax").unwrap());
|
||||
println!("rip: {:#x}", vm.reg_read("rip")?);
|
||||
println!("rax: {:#x}", vm.reg_read("rax")?);
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn block_optimization() -> PyResult<()> {
|
||||
let mut vm: Icicle = Icicle::new(
|
||||
"x86_64".to_string(), // architecture
|
||||
true, // jit
|
||||
true, // jit_mem
|
||||
true, // shadow_stack
|
||||
true, // recompilation
|
||||
false, // track_uninitialized
|
||||
true, // optimize_instructions
|
||||
true, // optimize_block
|
||||
false, // tracing
|
||||
)?;
|
||||
|
||||
// Memory setup
|
||||
let addr: u64 = 0x140001A73;
|
||||
let heap: u64 = 0x71000;
|
||||
vm.mem_map(heap, 0x1000, MemoryProtection::ReadWrite)?;
|
||||
vm.mem_write(heap + 4, b"\x37\x13\x00\x00".to_vec())?;
|
||||
vm.mem_map(addr & !0xFFF, 0x1000, MemoryProtection::ExecuteRead)?;
|
||||
vm.mem_write(addr, b"\x41\xc1\xea\x07\x41\x83\xe2\x1f\x74\x08\x44\x89\xd0\x48\x89\x54\xc6\x08\x49\x83\xc1\x04\x4c\x89\x0e\x4c\x89\xc9\x44\x8b\x11\x44\x89\xd0\xf7\xd0\x49\x89\xc9\xa8\x03\x0f\x84\x88\xf6\xff\xff\xeb\x4c".to_vec())?;
|
||||
|
||||
// Register setup
|
||||
vm.reg_write("r9", heap)?;
|
||||
vm.reg_write("r10", 0x13)?;
|
||||
vm.reg_write("rip", addr)?;
|
||||
vm.reg_write("rsi", heap + 0x100)?;
|
||||
|
||||
// Step through instructions
|
||||
for i in 0..11 {
|
||||
let rip = vm.reg_read("rip")?;
|
||||
let rcx = vm.reg_read("rcx")?;
|
||||
let r9 = vm.reg_read("r9")?;
|
||||
|
||||
println!("[{}] RIP: {:#x}, RCX: {:#x}, R9: {:#x}", i, rip, rcx, r9);
|
||||
|
||||
if rip == 0x140001A8F {
|
||||
vm.reg_write("r9", 0x13370900)?;
|
||||
}
|
||||
|
||||
vm.step(1);
|
||||
|
||||
if rip == 0x140001A9A {
|
||||
if rcx != r9 {
|
||||
println!("[BUG] expected rcx({:#x}) == r9({:#x})", rcx, r9);
|
||||
} else {
|
||||
println!("Everything works!");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn main() {
|
||||
#![allow(unused_must_use)]
|
||||
println!("=== NX (block start) ===");
|
||||
nx_start();
|
||||
println!("=== NX (block middle) ===");
|
||||
@@ -376,4 +168,6 @@ fn main() {
|
||||
inv_start();
|
||||
println!("=== Invalid instruction (block middle) ===");
|
||||
inv_middle();
|
||||
println!("=== Block optimization bug ===");
|
||||
block_optimization();
|
||||
}
|
||||
|
||||
@@ -0,0 +1,36 @@
|
||||
from icicle import *
|
||||
|
||||
def main():
|
||||
emu = Icicle("x86_64", jit=True, optimize_block=True, tracing=True)
|
||||
|
||||
instructions = bytes.fromhex("41 C1 EA 07 41 83 E2 1F 74 08 44 89 D0 48 89 54 C6 08 49 83 C1 04 4C 89 0E 4C 89 C9 44 8B 11 44 89 D0 F7 D0 49 89 C9 A8 03 0F 84 88 F6 FF FF EB 4C".replace(" ", ""))
|
||||
|
||||
addr = 0x140001A73
|
||||
heap = 0x71000
|
||||
emu.mem_map(heap, 0x1000, MemoryProtection.ReadWrite)
|
||||
emu.mem_write(heap + 4, 0x1337.to_bytes(4, "little"))
|
||||
emu.mem_map(addr & ~0xFFF, 0x1000, MemoryProtection.ExecuteRead)
|
||||
emu.mem_write(addr, instructions)
|
||||
emu.reg_write("r9", heap)
|
||||
emu.reg_write("r10", 0x13)
|
||||
emu.reg_write("rip", addr)
|
||||
emu.reg_write("rsi", heap + 0x100)
|
||||
|
||||
for i in range(11):
|
||||
rip = emu.reg_read("rip")
|
||||
rcx = emu.reg_read("rcx")
|
||||
r9 = emu.reg_read("r9")
|
||||
print(f"[{i}] RIP: {hex(rip)}, RCX: {hex(rcx)}, R9: {hex(r9)}")
|
||||
|
||||
if rip == 0x140001A8F:
|
||||
emu.reg_write("r9", 0x13370900)
|
||||
|
||||
emu.step(1)
|
||||
|
||||
if rip == 0x140001A9A:
|
||||
assert rcx == r9, f"expected rcx({hex(rcx)}) == r9({hex(r9)})"
|
||||
|
||||
print("Everything works!")
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
Reference in New Issue
Block a user