Add getter/setter for PC and SP registers

This commit is contained in:
Duncan Ogilvie
2024-12-25 00:37:31 +01:00
parent ae409c8f1f
commit a228304530
2 changed files with 24 additions and 0 deletions
+4
View File
@@ -100,6 +100,10 @@ class Icicle:
icount_limit: int
pc: int
sp: int
# TODO: API to get memory information?
def mem_map(self, address: int, size: int, protection: MemoryProtection): ...
+20
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@@ -276,6 +276,26 @@ impl Icicle {
self.architecture.to_string()
}
#[getter]
pub fn get_pc(&self) -> u64 {
self.vm.cpu.read_pc()
}
#[setter]
pub fn set_pc(&mut self, address: u64) {
self.vm.cpu.write_pc(address)
}
#[getter]
pub fn get_sp(&mut self) -> u64 {
self.vm.cpu.read_reg(self.vm.cpu.arch.reg_sp)
}
#[setter]
pub fn set_sp(&mut self, address: u64) {
self.vm.cpu.write_reg(self.vm.cpu.arch.reg_sp, address)
}
#[new]
#[pyo3(signature = (
architecture,