mirror of
https://github.com/intel/linux-sgx
synced 2026-06-08 14:49:32 +00:00
Li, Xun
c505e6129a
Added support for Reproducible Enclave Build using Docker file. Added support for Intel AVX-512 instructions and Intel SHA Extensions New Instructions (SHA-NI) in trusted libraries. Support both EPID and ECDSA based quote for quoting related interfaces in sgx_uae_service library. Updated key exchange library to support both EPID and ECDSA based remote attestation. Support new interface to check platform information blob from remote attestation response message. Fixed bugs. Signed-off-by: Li, Xun <xun.li@intel.com>
130 lines
2.7 KiB
C
130 lines
2.7 KiB
C
#ifndef REMOTE_H
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#define REMOTE_H
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/* Helper functions for accessing (remote) memory. These functions
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assume that all addresses are naturally aligned (e.g., 32-bit
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quantity is stored at a 32-bit-aligned address. */
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#ifdef UNW_LOCAL_ONLY
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static inline int
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fetch8 (unw_addr_space_t as, unw_accessors_t *a,
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unw_word_t *addr, int8_t *valp, void *arg)
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{
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*valp = *(int8_t *) (uintptr_t) *addr;
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*addr += 1;
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return 0;
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}
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static inline int
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fetch16 (unw_addr_space_t as, unw_accessors_t *a,
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unw_word_t *addr, int16_t *valp, void *arg)
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{
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*valp = *(int16_t *) (uintptr_t) *addr;
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*addr += 2;
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return 0;
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}
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static inline int
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fetch32 (unw_addr_space_t as, unw_accessors_t *a,
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unw_word_t *addr, int32_t *valp, void *arg)
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{
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*valp = *(int32_t *) (uintptr_t) *addr;
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*addr += 4;
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return 0;
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}
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static inline int
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fetchw (unw_addr_space_t as, unw_accessors_t *a,
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unw_word_t *addr, unw_word_t *valp, void *arg)
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{
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*valp = *(unw_word_t *) (uintptr_t) *addr;
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*addr += sizeof (unw_word_t);
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return 0;
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}
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#else /* !UNW_LOCAL_ONLY */
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#define WSIZE (sizeof (unw_word_t))
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static inline int
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fetch8 (unw_addr_space_t as, unw_accessors_t *a,
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unw_word_t *addr, int8_t *valp, void *arg)
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{
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unw_word_t val, aligned_addr = *addr & -WSIZE, off = *addr - aligned_addr;
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int ret;
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*addr += 1;
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ret = (*a->access_mem) (as, aligned_addr, &val, 0, arg);
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#if __BYTE_ORDER == __LITTLE_ENDIAN
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val >>= 8*off;
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#else
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val >>= 8*(WSIZE - 1 - off);
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#endif
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*valp = val & 0xff;
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return ret;
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}
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static inline int
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fetch16 (unw_addr_space_t as, unw_accessors_t *a,
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unw_word_t *addr, int16_t *valp, void *arg)
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{
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unw_word_t val, aligned_addr = *addr & -WSIZE, off = *addr - aligned_addr;
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int ret;
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if ((off & 0x1) != 0)
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return -UNW_EINVAL;
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*addr += 2;
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ret = (*a->access_mem) (as, aligned_addr, &val, 0, arg);
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#if __BYTE_ORDER == __LITTLE_ENDIAN
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val >>= 8*off;
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#else
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val >>= 8*(WSIZE - 2 - off);
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#endif
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*valp = val & 0xffff;
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return ret;
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}
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static inline int
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fetch32 (unw_addr_space_t as, unw_accessors_t *a,
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unw_word_t *addr, int32_t *valp, void *arg)
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{
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unw_word_t val, aligned_addr = *addr & -WSIZE, off = *addr - aligned_addr;
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int ret;
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if ((off & 0x3) != 0)
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return -UNW_EINVAL;
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*addr += 4;
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ret = (*a->access_mem) (as, aligned_addr, &val, 0, arg);
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#if __BYTE_ORDER == __LITTLE_ENDIAN
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val >>= 8*off;
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#else
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val >>= 8*(WSIZE - 4 - off);
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#endif
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*valp = val & 0xffffffff;
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return ret;
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}
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static inline int
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fetchw (unw_addr_space_t as, unw_accessors_t *a,
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unw_word_t *addr, unw_word_t *valp, void *arg)
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{
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int ret;
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ret = (*a->access_mem) (as, *addr, valp, 0, arg);
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*addr += WSIZE;
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return ret;
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}
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#endif /* !UNW_LOCAL_ONLY */
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#endif /* REMOTE_H */
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