mirror of
https://github.com/intel/linux-sgx
synced 2026-06-08 14:49:32 +00:00
Li, Xun
1eaa4551d4
Supported to query Intel(R) SGX attestation key ID list. Fixed bugwqs. Signed-off-by: Li, Xun <xun.li@intel.com>
209 lines
6.5 KiB
C++
209 lines
6.5 KiB
C++
/*
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* Copyright (C) 2011-2020 Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include "se_cpu_feature_defs.h"
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#include "se_types.h"
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#include "cpu_features.h"
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// Initialize cpuid leaves for FIPS capable OpenSSL
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//-------------------------------------------------
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extern void init_cpuinfo(uint32_t *cpuinfo_table)
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{
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// Leaf 0
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sgx_cpuid(0,
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cpuinfo_table,
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cpuinfo_table + 1,
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cpuinfo_table + 2,
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cpuinfo_table + 3);
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// Leaf 1
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sgx_cpuid(1,
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cpuinfo_table + 4,
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cpuinfo_table + 4 + 1,
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cpuinfo_table + 4 + 2,
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cpuinfo_table + 4 + 3);
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// Leaf 4
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sgx_cpuid(4,
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cpuinfo_table + 4*4,
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cpuinfo_table + 4*4 + 1,
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cpuinfo_table + 4*4 + 2,
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cpuinfo_table + 4*4 + 3);
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// Leaf 7
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sgx_cpuid(7,
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cpuinfo_table + 4*7,
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cpuinfo_table + 4*7 + 1,
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cpuinfo_table + 4*7 + 2,
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cpuinfo_table + 4*7 + 3);
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return;
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}
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void get_cpu_features(uint64_t *__intel_cpu_feature_indicator)
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{
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unsigned int cpuid0_eax, cpuid0_ebx, cpuid0_ecx, cpuid0_edx;
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unsigned int cpuid1_eax, cpuid1_ebx, cpuid1_ecx, cpuid1_edx;
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unsigned int cpuid7_eax, cpuid7_ebx, cpuid7_ecx, cpuid7_edx;
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unsigned int ecpuid1_eax, ecpuid1_ebx, ecpuid1_ecx, ecpuid1_edx;
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uint64_t cpu_feature_indicator = CPU_FEATURE_GENERIC_IA32;
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bool is_intel = false;
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sgx_cpuid(0, &cpuid0_eax, &cpuid0_ebx, &cpuid0_ecx, &cpuid0_edx);
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if(cpuid0_eax == 0)
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{
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*__intel_cpu_feature_indicator = cpu_feature_indicator;
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return;
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}
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is_intel = (cpuid0_ebx == CPU_GENU_VAL && cpuid0_edx == CPU_INEI_VAL &&
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cpuid0_ecx == CPU_NTEL_VAL);
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sgx_cpuid(1, &cpuid1_eax, &cpuid1_ebx, &cpuid1_ecx, &cpuid1_edx);
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if (CPU_MODEL(cpuid1_eax) == CPU_ATOM1 ||
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CPU_MODEL(cpuid1_eax) == CPU_ATOM2 ||
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CPU_MODEL(cpuid1_eax) == CPU_ATOM3) {
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cpu_feature_indicator |= CPU_FEATURE_FULL_INORDER;
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}
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// Walk through supported features
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if (CPU_HAS_FPU(cpuid1_edx)) {
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cpu_feature_indicator |= CPU_FEATURE_FPU;
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}
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if (CPU_HAS_CMOV(cpuid1_edx)) {
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cpu_feature_indicator |= CPU_FEATURE_CMOV;
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}
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if (CPU_HAS_MMX(cpuid1_edx)) {
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cpu_feature_indicator |= CPU_FEATURE_MMX;
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}
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if (CPU_HAS_FXSAVE(cpuid1_edx)) {
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cpu_feature_indicator |= CPU_FEATURE_FXSAVE;
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if (CPU_HAS_SSE(cpuid1_edx)) {
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cpu_feature_indicator |= CPU_FEATURE_SSE;
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}
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if (CPU_HAS_SSE2(cpuid1_edx)) {
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cpu_feature_indicator |= CPU_FEATURE_SSE2;
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}
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if (CPU_HAS_SSE3(cpuid1_ecx)) {
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cpu_feature_indicator |= CPU_FEATURE_SSE3;
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}
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if (CPU_HAS_SSSE3(cpuid1_ecx)) {
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cpu_feature_indicator |= CPU_FEATURE_SSSE3;
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}
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if (CPU_HAS_MOVBE(cpuid1_ecx)) {
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cpu_feature_indicator |= CPU_FEATURE_MOVBE;
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}
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//
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// Penryn is a P6 with SNI support.
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//
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if (CPU_HAS_SSE4_1(cpuid1_ecx)) {
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cpu_feature_indicator |= CPU_FEATURE_SSE4_1;
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}
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if (CPU_HAS_SSE4_2(cpuid1_ecx)) {
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cpu_feature_indicator |= CPU_FEATURE_SSE4_2;
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}
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if (CPU_HAS_POPCNT(cpuid1_ecx)) {
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cpu_feature_indicator |= CPU_FEATURE_POPCNT;
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}
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if (CPU_HAS_PCLMULQDQ(cpuid1_ecx)) {
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cpu_feature_indicator |= CPU_FEATURE_PCLMULQDQ;
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}
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if (CPU_HAS_AES(cpuid1_ecx)) {
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cpu_feature_indicator |= CPU_FEATURE_AES;
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}
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}
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// IvyBridge
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if (CPU_HAS_RDRAND(cpuid1_ecx)) {
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cpu_feature_indicator |= CPU_FEATURE_RDRND;
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}
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sgx_cpuidex(7, 0, &cpuid7_eax, &cpuid7_ebx, &cpuid7_ecx, &cpuid7_edx);
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sgx_cpuid(0x80000001, &ecpuid1_eax, &ecpuid1_ebx, &ecpuid1_ecx, &ecpuid1_edx);
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// Haswell
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// BMI checks for both ebx[3] and ebx[8] (VEX-encoded instructions)
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if (CPU_HAS_BMI(cpuid7_ebx)) {
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cpu_feature_indicator |= CPU_FEATURE_BMI;
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}
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if (is_intel && CPU_HAS_LZCNT(ecpuid1_ecx)) {
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cpu_feature_indicator |= CPU_FEATURE_LZCNT;
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}
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if (CPU_HAS_PREFETCHW(ecpuid1_ecx)) {
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cpu_feature_indicator |= CPU_FEATURE_PREFETCHW;
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}
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if (is_intel && CPU_HAS_HLE(cpuid7_ebx)) {
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cpu_feature_indicator |= CPU_FEATURE_HLE;
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}
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if (is_intel && CPU_HAS_RTM(cpuid7_ebx)) {
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cpu_feature_indicator |= CPU_FEATURE_RTM;
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}
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if (CPU_HAS_RDSEED(cpuid7_ebx)) {
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cpu_feature_indicator |= CPU_FEATURE_RDSEED;
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}
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if (CPU_HAS_ADCOX(cpuid7_ebx)) {
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cpu_feature_indicator |= CPU_FEATURE_ADCOX;
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}
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if (CPU_HAS_XSAVE(cpuid1_ecx))
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{
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//don't get xcr0_features, tRTS will do it.
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if (CPU_HAS_AVX(cpuid1_ecx)) {
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cpu_feature_indicator |= CPU_FEATURE_AVX;
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}
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// IvyBridge
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if (CPU_HAS_F16C(cpuid1_ecx)) {
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cpu_feature_indicator |= CPU_FEATURE_F16C;
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}
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// Haswell
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if (CPU_HAS_AVX2(cpuid7_ebx)) {
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cpu_feature_indicator |= CPU_FEATURE_AVX2;
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}
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if (CPU_HAS_FMA(cpuid1_ecx)) {
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cpu_feature_indicator |= CPU_FEATURE_FMA;
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}
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}
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*__intel_cpu_feature_indicator = cpu_feature_indicator;
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}
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