Recreate Ghidra sleigh patches to remove additional Ghidra fork for PPC

2026-06-21 13:56:07 +00:00 · 2025-11-05 20:46:01 -05:00
parent 92cbd7a182
commit 1da12ee670
15 changed files with 786 additions and 497 deletions
@@ -90,25 +90,31 @@ find_package(glog CONFIG REQUIRED)
 set(GFLAGS_USE_TARGET_NAMESPACE ON)
 find_package(gflags CONFIG REQUIRED)

-set(sleigh_ENABLE_TESTS OFF)
-set(sleigh_RELEASE_TYPE "HEAD" CACHE STRING "" FORCE)
-
+# Sleigh
 file(GLOB sleigh_patches "${CMAKE_CURRENT_SOURCE_DIR}/patches/sleigh/*.patch")
-
 set(sleigh_ADDITIONAL_PATCHES "${sleigh_patches}" CACHE STRING "" FORCE)
+set(sleigh_ENABLE_TESTS OFF CACHE BOOL "" FORCE)
+set(sleigh_RELEASE_TYPE "HEAD" CACHE STRING "" FORCE)
+set(sleigh_BUILD_SUPPORT ON CACHE BOOL "" FORCE)
+set(sleigh_BUILD_SLEIGHSPECS ON CACHE BOOL "" FORCE)

-# GHIDRA SLEIGH
+# Verbose fetch content updates
+set(FETCHCONTENT_QUIET OFF)
+
+# This version of sleigh (HEAD) pins Ghidra somewhere between Ghidra v10.2.3 and v10.3
+# https://github.com/lifting-bits/sleigh/blob/7c6b742/src/setup-ghidra-source.cmake#L55-L66
 FetchContent_Declare(sleigh
  GIT_REPOSITORY https://github.com/lifting-bits/sleigh.git
  GIT_TAG 7c6b742
 )
-
-set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-register")
-
-set(sleigh_BUILD_SUPPORT ON CACHE BOOL "" FORCE)
-set(sleigh_BUILD_SLEIGHSPECS ON CACHE BOOL "" FORCE)
 FetchContent_MakeAvailable(sleigh)

+# Get the Ghidra source directory from FetchContent's internal tracking
+FetchContent_GetProperties(GhidraSource)
+if(NOT ghidrasource_POPULATED)
+  message(FATAL_ERROR "Expected sleigh to populate GhidraSource")
+endif()
+
 # For Linux builds, group LLVM libraries into a single group
 # that avoids frustrating library ordering issues.
 if(UNIX AND NOT APPLE)
@@ -216,24 +222,6 @@ target_compile_definitions(remill_settings INTERFACE
  "REMILL_BUILD_SEMANTICS_DIR_PPC64_32ADDR=\"${REMILL_BUILD_SEMANTICS_DIR_PPC64_32ADDR}\""
 )

-set(ghidra_patch_user "github-actions[bot]")
-set(ghidra_patch_email "41898282+github-actions[bot]@users.noreply.github.com")
-
-# pinned stable patches list
-set(ghidra_patches
-  PATCH_COMMAND "${GIT_EXECUTABLE}" config user.name "${ghidra_patch_user}" &&
-  "${GIT_EXECUTABLE}" config user.email "${ghidra_patch_email}" &&
-  "${GIT_EXECUTABLE}" am --ignore-space-change --ignore-whitespace --no-gpg-sign)
-list(APPEND ghidra_patches ${sleigh_ADDITIONAL_PATCHES})
-
-FetchContent_Declare(ghidra-fork
-  GIT_REPOSITORY https://github.com/trail-of-forks/ghidra.git
-  GIT_TAG e7196d8
-  ${ghidra_patches}
-)
-
-FetchContent_MakeAvailable(ghidra-fork)
-
 if(SLEIGH_EXECUTABLE)
  set(sleigh_compiler "${SLEIGH_EXECUTABLE}")
 else()
@@ -243,7 +231,7 @@ endif()
 sleigh_compile(
  TARGET ppc_e200_spec
  COMPILER "${sleigh_compiler}"
-  SLASPEC "${ghidra-fork_SOURCE_DIR}/Ghidra/Processors/PowerPC/data/languages/ppc_32_e200_be.slaspec"
+  SLASPEC "${ghidrasource_SOURCE_DIR}/Ghidra/Processors/PowerPC/data/languages/ppc_32_e200_be.slaspec"
  LOG_FILE "${sleigh_BINARY_DIR}/sleighspecs/spec_build_logs/ppc_32_e200_be.sla.log"
  OUT_FILE "${sleigh_BINARY_DIR}/specfiles/Ghidra/Processors/PowerPC/data/languages/ppc_32_e200_be.sla"
 )
@@ -0,0 +1,17 @@
+# Sleigh patches
+
+The [sleigh](https://github.com/lifting-bits/sleigh) repository uses `git am` to apply a list of patches to a specific Ghidra base commit. These patches are mostly to make Ghidra's decompiler source code reusable as a library and suitable for packaging. You can find more information in [sleigh/src/README.md](https://github.com/lifting-bits/sleigh/blob/master/src/README.md).
+
+Remill has a bunch of additional patches, which improve the semantics themselves (sleigh files). These are applied on top of the sleigh patches and specified in `sleigh_ADDITIONAL_PATCHES`.
+
+To update the patches or the sleigh base commit, we need to get a cloned Ghidra source tree that only has the sleigh patches applied. From there we will apply the patches in this repository manually and recreate the patch folder.
+
+1. Go in `build/_deps/ghidrasource-src` and run `git status` to make sure you are in a clean state. You might need to run `git am --abort` to abort the patching process if you had patch failures.
+2. Modify remill's `CMakeLists.txt` to set `sleigh_ADDITIONAL_PATCHES` to be empty and re-configure remill. This will apply just the patches of the sleigh project's tag we pinned.
+3. Get the commit hash of the clean Ghidra patches with `git rev-parse HEAD` and note it as `<base-commit>`.
+4. Apply the patches in `patches/sleigh/` one by one with `git am ../../../patches/sleigh/0001-xyz.patch`. If you get any errors, manually apply the patch (you can try `git apply ../../../patches/sleigh/0001-xyz.patch`) and then `git add .` followed by `git am --continue`. The goal is to create a commit for every patch.
+5. Delete all the old patches: `rm patches/sleigh/*.patch`.
+6. Recreate the patch list: `git format-patch remill-sleigh-7c6b742-base -o ../../../patches/sleigh/`.
+7. Reconfigure remill's CMake to make sure everything applies correctly and then change `sleigh_ADDITIONAL_PATCHES` batch to include all of the patches in `patches/sleigh/`.
+
+**Note**: Sometimes you run into issues where `git am` cannot correctly apply all the patches. This is usually related to whitespace issues. Before exporting the patch list you can run `git rebase <base-commit> --whitespace=fix` to make sure everything is cleaned up correctly and ready to be applied.
@@ -0,0 +1,28 @@
+From 622437e7f4196c92b8162913e91704792ae82b43 Mon Sep 17 00:00:00 2001
+From: Duncan Ogilvie <mr.exodia.tpodt@gmail.com>
+Date: Wed, 29 Oct 2025 00:52:58 +0100
+Subject: [PATCH 01/13] Fix narrowing conversion warning
+
+error : constant expression evaluates to -1 which cannot be narrowed to type 'uintb' (aka 'unsigned long long') [-Wc++11-narrowing]
+---
+ Ghidra/Features/Decompiler/src/decompile/cpp/address.cc | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/Ghidra/Features/Decompiler/src/decompile/cpp/address.cc b/Ghidra/Features/Decompiler/src/decompile/cpp/address.cc
+index 07bf3ba555..ffbf3efcb9 100644
+--- a/Ghidra/Features/Decompiler/src/decompile/cpp/address.cc
+++ b/Ghidra/Features/Decompiler/src/decompile/cpp/address.cc
+@@ -630,8 +630,8 @@ void RangeList::decode(Decoder &decoder)
+ #ifdef UINTB4
+ uintb uintbmasks[9] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff };
+ #else
+-uintb uintbmasks[9] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff, 0xffffffffffLL,
+-			0xffffffffffffLL, 0xffffffffffffffLL, 0xffffffffffffffffLL };
+uintb uintbmasks[9] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff, 0xffffffffffULL,
+			0xffffffffffffULL, 0xffffffffffffffULL, 0xffffffffffffffffULL };
+ #endif
+ 
+ /// Treat the given \b val as a constant of \b size bytes
+-- 
+2.34.1
+
@@ -0,0 +1,224 @@
+From f252de1b805433764a82fd63af37f580fb15a400 Mon Sep 17 00:00:00 2001
+From: William Tan <1284324+Ninja3047@users.noreply.github.com>
+Date: Thu, 20 Apr 2023 16:24:00 -0400
+Subject: [PATCH 02/13] ppc e200 (#3)
+
+* initial e200 sub arch
+
+* fix description and gnu string
+
+* fix comment
+---
+ .../Processors/PowerPC/certification.manifest |   2 +
+ .../PowerPC/data/languages/ppc.ldefs          |  16 +++
+ .../data/languages/ppc_32_e200_be.cspec       | 106 ++++++++++++++++++
+ .../data/languages/ppc_32_e200_be.slaspec     |  30 +++++
+ .../PowerPC/data/languages/ppc_common.sinc    |   2 +-
+ 5 files changed, 155 insertions(+), 1 deletion(-)
+ create mode 100644 Ghidra/Processors/PowerPC/data/languages/ppc_32_e200_be.cspec
+ create mode 100644 Ghidra/Processors/PowerPC/data/languages/ppc_32_e200_be.slaspec
+
+diff --git a/Ghidra/Processors/PowerPC/certification.manifest b/Ghidra/Processors/PowerPC/certification.manifest
+index ad290208f0..39c6bf1451 100644
+--- a/Ghidra/Processors/PowerPC/certification.manifest
+++ b/Ghidra/Processors/PowerPC/certification.manifest
+@@ -23,6 +23,8 @@ data/languages/ppc_32_4xx_le.slaspec||GHIDRA||||END|
+ data/languages/ppc_32_be.cspec||GHIDRA||||END|
+ data/languages/ppc_32_be.slaspec||GHIDRA||||END|
+ data/languages/ppc_32_be_Mac.cspec||GHIDRA||||END|
+data/languages/ppc_32_e200_be.cspec||GHIDRA||||END|
+data/languages/ppc_32_e200_be.slaspec||GHIDRA||||END|
+ data/languages/ppc_32_e500_be.cspec||GHIDRA||||END|
+ data/languages/ppc_32_e500_be.slaspec||GHIDRA||||END|
+ data/languages/ppc_32_e500_le.cspec||GHIDRA||||END|
+diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc.ldefs b/Ghidra/Processors/PowerPC/data/languages/ppc.ldefs
+index 1d3dc8e043..4b0301d7da 100644
+--- a/Ghidra/Processors/PowerPC/data/languages/ppc.ldefs
+++ b/Ghidra/Processors/PowerPC/data/languages/ppc.ldefs
+@@ -174,6 +174,22 @@
+ 	<external_name tool="IDA-PRO" name="ppcl"/>
+     <external_name tool="DWARF.register.mapping.file" name="ppc.dwarf"/>
+   </language>
+  <language processor="PowerPC"
+            endian="big"
+            size="32"
+            variant="PowerISA-e200-vle"
+            version="1.5"
+            slafile="ppc_32_e200_be.sla"
+            processorspec="ppc_32.pspec"
+            manualindexfile="../manuals/PowerPC.idx"
+            id="PowerPC:BE:32:e200:VLE">
+    <description>Power ISA e200 32-bit big-endian family</description>
+    <truncate_space space="ram" size="4"/>
+    <compiler name="default" spec="ppc_32_e200_be.cspec" id="default"/>
+    <external_name tool="gnu" name="powerpc:vle"/>
+    <external_name tool="IDA-PRO" name="ppc"/>
+    <external_name tool="DWARF.register.mapping.file" name="ppc.dwarf"/>
+  </language>
+   <language processor="PowerPC"
+             endian="big"
+             size="32"
+diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_32_e200_be.cspec b/Ghidra/Processors/PowerPC/data/languages/ppc_32_e200_be.cspec
+new file mode 100644
+index 0000000000..cfc45d5c05
+--- /dev/null
+++ b/Ghidra/Processors/PowerPC/data/languages/ppc_32_e200_be.cspec
+@@ -0,0 +1,106 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- This cspec describes the 32-bit ABI for PowerPC as it is implemented for 64-bit code.
+     Presumably this ABI allows binary compatibility of 64-bit code with existing 32-bit code.
+     The ABI assumes 32-bit registers and addresses, in particular the maximum sized integer value
+     that can be passed in a single register is 4 bytes (even though the register is 8 bytes long).
+     The cspec currently has a limited ability to model this: the maxsize attribute must still be
+     set to 8 for parameter passing registers r3 - r10.
+-->
+<compiler_spec>
+  <global>
+    <range space="ram"/>
+  </global>
+  <data_organization>
+    <pointer_size value="4"/>
+  </data_organization>
+  <aggressivetrim signext="true"/>  <!-- Pointers are 4-bytes but are held in 8-byte registers -->
+  <stackpointer register="r1" space="ram"/>
+  <default_proto>
+    <prototype name="__stdcall" extrapop="0" stackshift="0">
+      <input pointermax="8">
+        <pentry minsize="1" maxsize="4" extension="sign">
+          <register name="_r3"/>
+        </pentry>
+        <pentry minsize="1" maxsize="4" extension="sign">
+          <register name="_r4"/>
+        </pentry>
+        <pentry minsize="5" maxsize="8" extension="sign">
+          <addr space="join" piece1="_r3" piece2="_r4"/>
+        </pentry>
+        <pentry minsize="1" maxsize="4" extension="sign">
+          <register name="_r5"/>
+        </pentry>
+        <pentry minsize="1" maxsize="4" extension="sign">
+          <register name="_r6"/>
+        </pentry>
+        <pentry minsize="5" maxsize="8" extension="sign">
+          <addr space="join" piece1="_r5" piece2="_r6"/>
+        </pentry>
+        <pentry minsize="1" maxsize="4" extension="sign">
+          <register name="_r7"/>
+        </pentry>
+        <pentry minsize="1" maxsize="4" extension="sign">
+          <register name="_r8"/>
+        </pentry>
+        <pentry minsize="5" maxsize="8" extension="sign">
+          <addr space="join" piece1="_r7" piece2="_r8"/>
+        </pentry>
+        <pentry minsize="1" maxsize="4" extension="sign">
+          <register name="_r9"/>
+        </pentry>
+        <pentry minsize="1" maxsize="4" extension="sign">
+          <register name="_r10"/>
+        </pentry>
+        <pentry minsize="5" maxsize="8" extension="sign">
+          <addr space="join" piece1="_r9" piece2="_r10"/>
+        </pentry>
+        <pentry minsize="1" maxsize="500" align="4">
+          <addr offset="8" space="stack"/>
+        </pentry>
+      </input>
+      <output>
+        <pentry minsize="1" maxsize="4" extension="sign">
+          <register name="_r3"/>
+        </pentry>
+        <pentry minsize="5" maxsize="8">
+          <addr space="join" piece1="_r3" piece2="_r4"/>
+        </pentry>
+      </output>
+      <unaffected>
+        <register name="r1"/>  <!-- stack pointer -->
+        <register name="r2"/>  <!-- _SDA2_BASE_ -->
+        <register name="r13"/> <!-- _SDA_BASE_  -->
+        <register name="r14"/>
+        <register name="r15"/>
+        <register name="r16"/>
+        <register name="r17"/>
+        <register name="r18"/>
+        <register name="r19"/>
+        <register name="r20"/>
+        <register name="r21"/>
+        <register name="r22"/>
+        <register name="r23"/>
+        <register name="r24"/>
+        <register name="r25"/>
+        <register name="r26"/>
+        <register name="r27"/>
+        <register name="r28"/>
+        <register name="r29"/>
+        <register name="r30"/>
+        <register name="r31"/>
+        <register name="cr2"/>
+        <register name="cr3"/>
+        <register name="cr4"/>
+      </unaffected>
+    </prototype>
+  </default_proto>
+
+  <callfixup name="get_pc_thunk_lr">
+    <pcode>
+      <body><![CDATA[
+      LR = inst_dest + 4;
+      ]]></body>
+    </pcode>
+  </callfixup>
+
+</compiler_spec>
+diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_32_e200_be.slaspec b/Ghidra/Processors/PowerPC/data/languages/ppc_32_e200_be.slaspec
+new file mode 100644
+index 0000000000..968574d198
+--- /dev/null
+++ b/Ghidra/Processors/PowerPC/data/languages/ppc_32_e200_be.slaspec
+@@ -0,0 +1,30 @@
+# SLA specification file for NXP PowerPC e200 series core
+
+# NOTE: This language variant includes some registers and instructions not supported
+# by the actual processor (e.g., floating pointer registers and associated instructions).
+# The actual processor only supports a subset of the registers and instructions implemented.
+
+@define E200
+
+@define ENDIAN "big"
+
+# Although a 32-bit architecture, 64-bit general purpose registers are supported.
+# Language has been modeled using a 64-bit implementation with a 32-bit truncated
+# memory space (see ldefs).
+
+@define REGISTER_SIZE "8"
+@define BIT_64 "64"
+
+@define EATRUNC "ea"
+
+@define CTR_OFFSET "32"
+
+@define NoLegacyIntegerMultiplyAccumulate
+
+@include "ppc_common.sinc"
+@include "ppc_vle.sinc"
+@include "quicciii.sinc"
+@include "evx.sinc"
+@include "SPEF_SCR.sinc"
+@include "SPE_EFSD.sinc"
+@include "SPE_EFV.sinc"
+diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc
+index aaa76cc4ac..46aa86c74c 100644
+--- a/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc
+++ b/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc
+@@ -19,7 +19,7 @@ define register offset=0 size=$(REGISTER_SIZE) [
+ 	r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15
+ 	r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 ];
+ 	
+-@ifdef E500
+@if defined(E500) || defined(E200)
+ # Define 4-byte general purpose sub-registers (LSB) to be used by E500 compiler specification
+ # which must restrict parameter/return passing to low 4-bytes of the 8-byte general purpose registers.
+ @if ENDIAN == "big"
+-- 
+2.34.1
+
@@ -0,0 +1,24 @@
+From b3bd823a17698abc4c2a906a7367018d4dedae45 Mon Sep 17 00:00:00 2001
+From: 2over12 <ian.smith@trailofbits.com>
+Date: Tue, 11 Apr 2023 13:05:24 -0400
+Subject: [PATCH 03/13] update target cspec
+
+---
+ Ghidra/Processors/PowerPC/data/languages/ppc_64_32.cspec | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_64_32.cspec b/Ghidra/Processors/PowerPC/data/languages/ppc_64_32.cspec
+index 109b980e35..2160930a8a 100644
+--- a/Ghidra/Processors/PowerPC/data/languages/ppc_64_32.cspec
+++ b/Ghidra/Processors/PowerPC/data/languages/ppc_64_32.cspec
+@@ -94,6 +94,7 @@
+         </pentry>
+       </output>
+       <unaffected>
+        <register name="r13"/>
+         <register name="r14"/>
+         <register name="r15"/>
+         <register name="r16"/>
+-- 
+2.34.1
+
@@ -1,14 +1,14 @@
-From 77f5e62e3ebf2e535e1ef370315ee86fd142726e Mon Sep 17 00:00:00 2001
+From 1e22375ef09c871de389a1765c5676d80ef47a20 Mon Sep 17 00:00:00 2001
 From: 2over12 <ian.smith@trailofbits.com>
 Date: Sun, 30 Apr 2023 12:31:13 -0400
-Subject: [PATCH] AARCH64base
+Subject: [PATCH 04/13] AARCH64base

 ---
 .../AARCH64/data/languages/AARCH64base.sinc   | 165 +++++++++++++++---
 1 file changed, 141 insertions(+), 24 deletions(-)

 diff --git a/Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc b/Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc
-index b9c0ccb64..d1137b04e 100644
+index b9c0ccb649..89c2ec0e3c 100644
 --- a/Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc
 +++ b/Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc
@@ -875,10 +875,15 @@ is sf=1 & opc=3 & b_2428=0xa & N=1 & RegShift64Log & Rn_GPR64 & Rd_GPR64
@@ -16,7 +16,7 @@ index b9c0ccb64..d1137b04e 100644
 :bl Addr26
 is b_31=1 & b_2630=0x05 & Addr26
 -{
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 +remill_please_dont_use_this_temp_name78:8=inst_start;
 +claim_eq(remill_please_dont_use_this_temp_name78, ($(INST_NEXT_PTR)-remill_insn_size));
 	x30 = inst_start + 4;
@@ -25,7 +25,7 @@ index b9c0ccb64..d1137b04e 100644
 -}
 +
 +  }
-+ 
+
 
 # C6.2.35 BLR page C6-1206 line 71050 MATCH xd63f0000/mask=xfffffc1f
 # CONSTRUCT xd63f0000/mask=xfffffc1f MATCHED 1 DOCUMENTED OPCODES
@@ -34,7 +34,7 @@ index b9c0ccb64..d1137b04e 100644
 :blr Rn_GPR64
 is b_2531=0x6b & b_2324=0 & b_2122=1 & b_1620=0x1f & b_1015=0 & Rn_GPR64 & b_0004=0
 -{
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 	pc = Rn_GPR64;
 +remill_please_dont_use_this_temp_name7a:8=inst_start;
 +claim_eq(remill_please_dont_use_this_temp_name7a, ($(INST_NEXT_PTR)-remill_insn_size));
@@ -45,20 +45,20 @@ index b9c0ccb64..d1137b04e 100644
 -}
 +
 +  }
-+ 
+
 
 # C6.2.33 BLRAA, BLRAAZ, BLRAB, BLRABZ page C6-574 line 33668 KEEPWITH
 
 # Z == 0 && M == 0 && Rm = 11111 Key A, zero modifier variant
 
 -blinkop: "l" is b_2122=0b01 { x30 = inst_start + 4; call [pc]; }
-+blinkop: "l" is b_2122=0b01  ; remill_insn_size  { 
+blinkop: "l" is b_2122=0b01  ; remill_insn_size  {
 +remill_please_dont_use_this_temp_name7c:8=inst_start;
 +claim_eq(remill_please_dont_use_this_temp_name7c, ($(INST_NEXT_PTR)-remill_insn_size));
 + x30 = inst_start + 4;
 + call [pc];
 +   }
-+ 
+
 blinkop: "" is b_2122=0b00 { goto[pc]; }
 
 # C6.2.36 BLRAA, BLRAAZ, BLRAB, BLRABZ page C6-1207 line 71095 MATCH xd63f0800/mask=xfefff800
@@ -67,7 +67,7 @@ index b9c0ccb64..d1137b04e 100644
 :ccmn Rn_GPR32, UImm5, NZCVImm_uimm4, CondOp
 is sf=0 & op=0 & s=1 & b_2428=0x1a & b_2123=2 & UImm5 & CondOp & b_1111=1 & o2=0 & Rn_GPR32 & o3=0 & NZCVImm_uimm4
 -{
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 	condition:1 = CondOp;
 +
 	condMask:1 = NZCVImm_uimm4;
@@ -90,7 +90,7 @@ index b9c0ccb64..d1137b04e 100644
 -}
 +
 +  }
-+ 
+
 
 # C6.2.48 CCMN (immediate) page C6-1228 line 72273 MATCH x3a400800/mask=x7fe00c10
 # CONSTRUCT xba400800/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
@@ -99,7 +99,7 @@ index b9c0ccb64..d1137b04e 100644
 :ccmn Rn_GPR64, UImm5, NZCVImm_uimm4, CondOp
 is sf=1 & op=0 & s=1 & b_2428=0x1a & b_2123=2 & UImm5 & CondOp & b_1111=1 & o2=0 & Rn_GPR64 & o3=0 & NZCVImm_uimm4
 -{
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 	condition:1 = CondOp;
 +
 	condMask:1 = NZCVImm_uimm4;
@@ -122,7 +122,7 @@ index b9c0ccb64..d1137b04e 100644
 -}
 +
 +  }
-+ 
+
 
 # C6.2.49 CCMN (register) page C6-1230 line 72358 MATCH x3a400000/mask=x7fe00c10
 # CONSTRUCT x3a400000/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
@@ -131,7 +131,7 @@ index b9c0ccb64..d1137b04e 100644
 :ccmn Rn_GPR32, Rm_GPR32, NZCVImm_uimm4, CondOp
 is sf=0 & op=0 & s=1 & b_2428=0x1a & b_2123=2 & Rm_GPR32 & CondOp & b_1111=0 & o2=0 & Rn_GPR32 & o3=0 & NZCVImm_uimm4
 -{
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 	condition:1 = CondOp;
 +
 	condMask:1 = NZCVImm_uimm4;
@@ -154,7 +154,7 @@ index b9c0ccb64..d1137b04e 100644
 -}
 +
 +  }
-+ 
+
 
 # C6.2.49 CCMN (register) page C6-1230 line 72358 MATCH x3a400000/mask=x7fe00c10
 # CONSTRUCT xba400000/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
@@ -163,7 +163,7 @@ index b9c0ccb64..d1137b04e 100644
 :ccmn Rn_GPR64, Rm_GPR64, NZCVImm_uimm4, CondOp
 is sf=1 & op=0 & s=1 & b_2428=0x1a & b_2123=2 & Rm_GPR64 & CondOp & b_1111=0 & o2=0 & Rn_GPR64 & o3=0 & NZCVImm_uimm4
 -{
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 	condition:1 = CondOp;
 +
 	condMask:1 = NZCVImm_uimm4;
@@ -186,7 +186,7 @@ index b9c0ccb64..d1137b04e 100644
 -}
 +
 +  }
-+ 
+
 
 # C6.2.50 CCMP (immediate) page C6-1232 line 72446 MATCH x7a400800/mask=x7fe00c10
 # CONSTRUCT x7a400800/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
@@ -195,7 +195,7 @@ index b9c0ccb64..d1137b04e 100644
 :ccmp Rn_GPR32, UImm5, NZCVImm_uimm4, CondOp
 is sf=0 & op=1 & s=1 & b_2428=0x1a & b_2123=2 & UImm5 & CondOp & b_1111=1 & o2=0 & Rn_GPR32 & o3=0 & NZCVImm_uimm4
 -{
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 	condition:1 = CondOp;
 +
 	condMask:1 = NZCVImm_uimm4;
@@ -216,7 +216,7 @@ index b9c0ccb64..d1137b04e 100644
 -}
 +
 +  }
-+ 
+
 
 # C6.2.50 CCMP (immediate) page C6-1232 line 72446 MATCH x7a400800/mask=x7fe00c10
 # CONSTRUCT xfa400800/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
@@ -225,7 +225,7 @@ index b9c0ccb64..d1137b04e 100644
 :ccmp Rn_GPR64, UImm5, NZCVImm_uimm4, CondOp
 is sf=1 & op=1 & s=1 & b_2428=0x1a & b_2123=2 & UImm5 & CondOp & b_1111=1 & o2=0 & Rn_GPR64 & o3=0 & NZCVImm_uimm4
 -{
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 	condition:1 = CondOp;
 +
 	condMask:1 = NZCVImm_uimm4;
@@ -248,7 +248,7 @@ index b9c0ccb64..d1137b04e 100644
 -}
 +
 +  }
-+ 
+
 
 # C6.2.51 CCMP (register) page C6-1234 line 72531 MATCH x7a400000/mask=x7fe00c10
 # CONSTRUCT x7a400000/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
@@ -257,7 +257,7 @@ index b9c0ccb64..d1137b04e 100644
 :ccmp Rn_GPR32, Rm_GPR32, NZCVImm_uimm4, CondOp
 is sf=0 & op=1 & s=1 & b_2428=0x1a & b_2123=2 & Rm_GPR32 & CondOp & b_1111=0 & o2=0 & Rn_GPR32 & o3=0 & NZCVImm_uimm4
 -{
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 	condition:1 = CondOp;
 +
 	condMask:1 = NZCVImm_uimm4;
@@ -278,7 +278,7 @@ index b9c0ccb64..d1137b04e 100644
 -}
 +
 +  }
-+ 
+
 
 # C6.2.51 CCMP (register) page C6-1234 line 72531 MATCH x7a400000/mask=x7fe00c10
 # CONSTRUCT xfa400000/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
@@ -287,7 +287,7 @@ index b9c0ccb64..d1137b04e 100644
 :ccmp Rn_GPR64, Rm_GPR64, NZCVImm_uimm4, CondOp
 is sf=1 & op=1 & s=1 & b_2428=0x1a & b_2123=2 & Rm_GPR64 & CondOp & b_1111=0 & o2=0 & Rn_GPR64 & o3=0 & NZCVImm_uimm4
 -{
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 	condition:1 = CondOp;
 +
 	condMask:1 = NZCVImm_uimm4;
@@ -308,7 +308,7 @@ index b9c0ccb64..d1137b04e 100644
 -}
 +
 +  }
-+ 
+
 
 # C6.2.52 CFINV page C6-1236 line 72619 MATCH xd500401f/mask=xfffff0ff
 # C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f
@@ -318,7 +318,7 @@ index b9c0ccb64..d1137b04e 100644
 is b_1631=0b0000000000000000 & b_0015
 -{
 -    local excaddr:8 = inst_start;
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 +remill_please_dont_use_this_temp_name716:8=inst_start;
 +claim_eq(remill_please_dont_use_this_temp_name716, ($(INST_NEXT_PTR)-remill_insn_size));
 + local excaddr:8 = inst_start;
@@ -331,10 +331,10 @@ index b9c0ccb64..d1137b04e 100644
 -}
 +
 +  }
-+ 
+
 
 
 # C6.2.400 XAFLAG page C6-2008 line 117528 MATCH xd500403f/mask=xfffff0ff
 -- 
-2.39.2 (Apple Git-143)
+2.34.1

@@ -1,14 +1,14 @@
-From 1f36e852b46eadd6d68bede26bda7e207449f5f6 Mon Sep 17 00:00:00 2001
+From b97f65cd96756ec0dd55fb17c1ccdcaabf774ba5 Mon Sep 17 00:00:00 2001
 From: 2over12 <ian.smith@trailofbits.com>
 Date: Sun, 30 Apr 2023 12:31:13 -0400
-Subject: [PATCH] AARCH64instructions
+Subject: [PATCH 05/13] AARCH64instructions

 ---
- .../data/languages/AARCH64instructions.sinc   | 38 ++++++++++++++++---
- 1 file changed, 32 insertions(+), 6 deletions(-)
+ .../data/languages/AARCH64instructions.sinc   | 34 ++++++++++++++++---
+ 1 file changed, 30 insertions(+), 4 deletions(-)

 diff --git a/Ghidra/Processors/AARCH64/data/languages/AARCH64instructions.sinc b/Ghidra/Processors/AARCH64/data/languages/AARCH64instructions.sinc
-index c6bd81d3a..f629a00b7 100644
+index c6bd81d3a1..dd7bf48808 100644
 --- a/Ghidra/Processors/AARCH64/data/languages/AARCH64instructions.sinc
 +++ b/Ghidra/Processors/AARCH64/data/languages/AARCH64instructions.sinc
@@ -37,6 +37,9 @@ define endian=little;
@@ -26,7 +26,7 @@ index c6bd81d3a..f629a00b7 100644
 # SECTION subtables
 
 +
-+remill_insn_size: calculated_size is epsilon [calculated_size= inst_next-inst_start; ] { local insn_size_hinted:8=calculated_size; 
+remill_insn_size: calculated_size is epsilon [calculated_size= inst_next-inst_start; ] { local insn_size_hinted:8=calculated_size;
 + export insn_size_hinted; }
 Rm_GPR32: aa_Wm is aa_Wm { export aa_Wm; }
 Rm_GPR32: wzr is aa_Wm=31 & wzr { tmp:4 = 0; export tmp; }
@@ -36,30 +36,28 @@ index c6bd81d3a..f629a00b7 100644
 LSB_bitfield64_imm_shift: "#"^shift is imm6 [ shift = 63 - imm6; ] { export *[const]:8 shift; }
 
 -AddrLoc14: reloc is simm14 [ reloc = inst_start + (4*simm14); ] { export *[const]:8 reloc; }
-
-AddrLoc19: reloc is simm19 [ reloc = inst_start + (4*simm19); ] { export *[const]:8 reloc; }
-
-AddrLoc26: reloc is simm26 [ reloc = inst_start + (4*simm26); ] { export *[const]:8 reloc; }
-+AddrLoc14: reloc is simm14  ; remill_insn_size [ reloc = inst_start + (4*simm14); ] { 
+AddrLoc14: reloc is simm14  ; remill_insn_size [ reloc = inst_start + (4*simm14); ] {
 +remill_please_dont_use_this_temp_name12f:8=reloc;
 +claim_eq(remill_please_dont_use_this_temp_name12f,  ($(INST_NEXT_PTR)-remill_insn_size) + (4*simm14));
 + export *[const]:8 reloc;
 +   }
-+ 
 +
-+AddrLoc19: reloc is simm19  ; remill_insn_size [ reloc = inst_start + (4*simm19); ] { 
+ 
+-AddrLoc19: reloc is simm19 [ reloc = inst_start + (4*simm19); ] { export *[const]:8 reloc; }
+AddrLoc19: reloc is simm19  ; remill_insn_size [ reloc = inst_start + (4*simm19); ] {
 +remill_please_dont_use_this_temp_name132:8=reloc;
 +claim_eq(remill_please_dont_use_this_temp_name132,  ($(INST_NEXT_PTR)-remill_insn_size) + (4*simm19));
 + export *[const]:8 reloc;
 +   }
-+ 
 +
-+AddrLoc26: reloc is simm26  ; remill_insn_size [ reloc = inst_start + (4*simm26); ] { 
+
+AddrLoc26: reloc is simm26  ; remill_insn_size [ reloc = inst_start + (4*simm26); ] {
 +remill_please_dont_use_this_temp_name135:8=reloc;
 +claim_eq(remill_please_dont_use_this_temp_name135,  ($(INST_NEXT_PTR)-remill_insn_size) + (4*simm26));
 + export *[const]:8 reloc;
 +   }
-+ 
+ 
+-AddrLoc26: reloc is simm26 [ reloc = inst_start + (4*simm26); ] { export *[const]:8 reloc; }
 
 Addr14: AddrLoc14 is AddrLoc14 { export *:8 AddrLoc14; }
 
@@ -68,15 +66,15 @@ index c6bd81d3a..f629a00b7 100644
 
 AdrReloff: reloff is b_31=1 & immlo & immhi [ reloff = ((inst_start) & ~0xfff) + ( ((immhi << 2) | immlo) << 12 ); ] { export *[const]:8 reloff; }
 -AdrReloff: reloff is b_31=0 & immlo & immhi [ reloff = (inst_start) + ( ((immhi << 2) | immlo) ); ] { export *[const]:8 reloff; }
-+AdrReloff: reloff is b_31=0 & immlo & immhi  ; remill_insn_size [ reloff = (inst_start) + ( ((immhi << 2) | immlo) ); ] { 
+AdrReloff: reloff is b_31=0 & immlo & immhi  ; remill_insn_size [ reloff = (inst_start) + ( ((immhi << 2) | immlo) ); ] {
 +remill_please_dont_use_this_temp_name13e:8=reloff;
 +claim_eq(remill_please_dont_use_this_temp_name13e,  (($(INST_NEXT_PTR)-remill_insn_size)) + ( ((immhi << 2) | immlo) ));
 + export *[const]:8 reloff;
 +   }
-+ 
+
 
 ImmShift32: "#"^imm12 is aa_extreg_shift=0 & imm12 { export *[const]:4 imm12; }
 ImmShift32: "#"^imm12, "LSL #12" is aa_extreg_shift=1 & imm12 { tmp:4 = imm12 << 12; export tmp; }
 -- 
-2.39.2 (Apple Git-143)
+2.34.1

@@ -1,21 +1,21 @@
-From e14cd23465872e8306af1e5dd6a36cbecc140c9e Mon Sep 17 00:00:00 2001
+From 941c3fe1cf2bacb5c0c4e030894b9ed4bd0a3f31 Mon Sep 17 00:00:00 2001
 From: 2over12 <ian.smith@trailofbits.com>
 Date: Mon, 24 Apr 2023 09:59:22 -0400
-Subject: [PATCH] ARM
+Subject: [PATCH 06/13] ARM

 ---
 Ghidra/Processors/ARM/data/languages/ARM.sinc | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

 diff --git a/Ghidra/Processors/ARM/data/languages/ARM.sinc b/Ghidra/Processors/ARM/data/languages/ARM.sinc
-index 09f31819e..1d5b539b0 100644
+index 09f31819e5..fb7754456e 100644
 --- a/Ghidra/Processors/ARM/data/languages/ARM.sinc
 +++ b/Ghidra/Processors/ARM/data/languages/ARM.sinc
@@ -2,6 +2,13 @@
 # The following boolean defines control specific support: T_VARIANT, VERSION_5, VERSION_5E
 
 define endian=$(ENDIAN);
-+# so the trick here is to define an INST_NEXT_PTR that works in either context 
+# so the trick here is to define an INST_NEXT_PTR that works in either context
 +# subtracting tmode from 2 means if it is 1 get 1 *4 which is the correct normalization for thumb, if it is 0
 +# we get 8
 +
@@ -30,7 +30,7 @@ index 09f31819e..1d5b539b0 100644
 @if defined(T_VARIANT)
 
 +
-+remill_insn_size: calculated_size is epsilon [calculated_size= inst_next-inst_start; ] { local insn_size_hinted:4=calculated_size; 
+remill_insn_size: calculated_size is epsilon [calculated_size= inst_next-inst_start; ] { local insn_size_hinted:4=calculated_size;
 + export insn_size_hinted; }
 ItCond:              is TMode=1			{ }
 CheckInIT_CZNO:      is TMode=1  	    { CY = tmpCY; ZR = tmpZR; NG = tmpNG; OV = tmpOV; }		# in older, arms always affect flags
@@ -40,15 +40,15 @@ index 09f31819e..1d5b539b0 100644
 # last ITBlock then/else case - the condition being tested is modified by the shift below
 ItCond:  "."thfcc    is TMode=1 & itmode=0 & cond_mask=8 & thfcc
 -   { if (!thfcc) goto inst_next; }
-+    ; remill_insn_size  { 
+    ; remill_insn_size  {
 +remill_please_dont_use_this_temp_name29:4=inst_next;
 +claim_eq(remill_please_dont_use_this_temp_name29, $(INST_NEXT_PTR));
 + if (!thfcc) goto inst_next;
 +   }
-+ 
+
 
 # certain Thumb instructions don't affect all flags in the IT block
 CheckInIT_CZNO:     is TMode=1 & itmode=1 & cond_mask  	        { }   # Do nothing to the flag bits
 -- 
-2.39.2 (Apple Git-143)
+2.34.1

@@ -1,14 +1,14 @@
-From 182d869276da62a971f46570013abff91729162f Mon Sep 17 00:00:00 2001
+From c3baece07919a9a169e0e6cffecc28ab11bca6d0 Mon Sep 17 00:00:00 2001
 From: 2over12 <ian.smith@trailofbits.com>
 Date: Mon, 24 Apr 2023 09:59:22 -0400
-Subject: [PATCH] ARMTHUMBinstructions
+Subject: [PATCH 07/13] ARMTHUMBinstructions

 ---
 .../data/languages/ARMTHUMBinstructions.sinc  | 509 +++++++++++++-----
 1 file changed, 378 insertions(+), 131 deletions(-)

 diff --git a/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc b/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc
-index f210fab0e..64d29e35c 100644
+index f210fab0e9..99ba3df8bb 100644
 --- a/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc
 +++ b/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc
@@ -350,15 +350,33 @@ thSBIT_ZN: "s" is thc0404=1	    { ZR = tmpZR; NG = tmpNG; }
@@ -16,35 +16,35 @@ index f210fab0e..64d29e35c 100644
 Hrd0002: Rd0002		is Rd0002 & h1=0	{ export Rd0002; }
 Hrd0002: hrd0002	is hrd0002 & h1=1	{ export hrd0002; }
 -Hrd0002: pc		is pc & hrd0002=7 & h1=1 { tmp:4 = inst_start + 4; export tmp; }
-+Hrd0002: pc		is pc & hrd0002=7 & h1=1  ; remill_insn_size  { 
+Hrd0002: pc		is pc & hrd0002=7 & h1=1  ; remill_insn_size  {
 +remill_please_dont_use_this_temp_name6e:4=inst_start;
 +claim_eq(remill_please_dont_use_this_temp_name6e, ($(INST_NEXT_PTR)-remill_insn_size));
 + tmp:4 = inst_start + 4;
 + export tmp;
 +   }
-+ 
+
 
 Hrn0002: Rn0002		is Rn0002 & h1=0	{ export Rn0002; }
 Hrn0002: hrn0002	is hrn0002 & h1=1	{ export hrn0002; }
 -Hrn0002: pc		is pc & hrn0002=7 & h1=1 { tmp:4 = inst_start + 4; export tmp; }
-+Hrn0002: pc		is pc & hrn0002=7 & h1=1  ; remill_insn_size  { 
+Hrn0002: pc		is pc & hrn0002=7 & h1=1  ; remill_insn_size  {
 +remill_please_dont_use_this_temp_name74:4=inst_start;
 +claim_eq(remill_please_dont_use_this_temp_name74, ($(INST_NEXT_PTR)-remill_insn_size));
 + tmp:4 = inst_start + 4;
 + export tmp;
 +   }
-+ 
+
 
 Hrm0305: Rm0305		is Rm0305 & h2=0	{ export Rm0305; }
 Hrm0305: hrm0305	is hrm0305 & h2=1	{ export hrm0305; }
 -Hrm0305: pc		is pc & hrm0305=7 & h2=1 { tmp:4 = inst_start + 4; export tmp; }
-+Hrm0305: pc		is pc & hrm0305=7 & h2=1  ; remill_insn_size  { 
+Hrm0305: pc		is pc & hrm0305=7 & h2=1  ; remill_insn_size  {
 +remill_please_dont_use_this_temp_name7a:4=inst_start;
 +claim_eq(remill_please_dont_use_this_temp_name7a, ($(INST_NEXT_PTR)-remill_insn_size));
 + tmp:4 = inst_start + 4;
 + export tmp;
 +   }
-+ 
+
 
 @if defined(VERSION_6T2) || defined(VERSION_7)
 Immed8_4: "#"^immval		is immed8 [ immval = immed8 * 4; ]		{ export *[const]:4 immval; }
@@ -55,7 +55,7 @@ index f210fab0e..64d29e35c 100644
 -  [ reloc = ((inst_start+4) $and 0xfffffffc) + 4*immed8; ]
 -{
 -  # don't export as an address, may be PIC code, and would add spurious symbols.
-+   ; remill_insn_size [ reloc = ((inst_start+4) $and 0xfffffffc) + 4*immed8; ] { 
+   ; remill_insn_size [ reloc = ((inst_start+4) $and 0xfffffffc) + 4*immed8; ] {
 +remill_please_dont_use_this_temp_name7d:4=reloc;
 +claim_eq(remill_please_dont_use_this_temp_name7d,  ((($(INST_NEXT_PTR)-remill_insn_size)+4) & 0xfffffffc) + 4*immed8);
 + # don't export as an address, may be PIC code, and would add spurious symbols.
@@ -63,7 +63,7 @@ index f210fab0e..64d29e35c 100644
 -}
 +
 +  }
-+ 
+
 
 @if defined(VERSION_6T2) || defined(VERSION_7)
 
@@ -72,13 +72,13 @@ index f210fab0e..64d29e35c 100644
 -{
 -  export *:8 reloc;
 -}
-+   ; remill_insn_size [ reloc = ((inst_start+4) $and 0xfffffffc) + 4*immed8; ] { 
+   ; remill_insn_size [ reloc = ((inst_start+4) $and 0xfffffffc) + 4*immed8; ] {
 +remill_please_dont_use_this_temp_name80:4=reloc;
 +claim_eq(remill_please_dont_use_this_temp_name80,  ((($(INST_NEXT_PTR)-remill_insn_size)+4) & 0xfffffffc) + 4*immed8);
 + export *:8 reloc;
 +
 +  }
-+ 
+
 @endif # defined(VERSION_6T2) || defined(VERSION_7)
 
 
@@ -89,7 +89,7 @@ index f210fab0e..64d29e35c 100644
 -  [ reloc = ((inst_start+4) $and 0xfffffffc) + ((immed12_i<<11) | (immed12_imm3<<8) | (immed12_imm8)); ]
 -{
 -  # don't export as an address, may be PIC code, and would add spurious symbols.
-+   ; remill_insn_size [ reloc = ((inst_start+4) $and 0xfffffffc) + ((immed12_i<<11) | (immed12_imm3<<8) | (immed12_imm8)); ] { 
+   ; remill_insn_size [ reloc = ((inst_start+4) $and 0xfffffffc) + ((immed12_i<<11) | (immed12_imm3<<8) | (immed12_imm8)); ] {
 +remill_please_dont_use_this_temp_name83:4=reloc;
 +claim_eq(remill_please_dont_use_this_temp_name83,  ((($(INST_NEXT_PTR)-remill_insn_size)+4) & 0xfffffffc) + ((immed12_i<<11) | (immed12_imm3<<8) | (immed12_imm8)));
 + # don't export as an address, may be PIC code, and would add spurious symbols.
@@ -97,13 +97,13 @@ index f210fab0e..64d29e35c 100644
 -}
 +
 +  }
-+ 
+
 
 NegPcrelImmed12Addr: reloc	is immed12_i; immed12_imm3 & immed12_imm8
 -  [ reloc = ((inst_start+4) $and 0xfffffffc) - ((immed12_i<<11) | (immed12_imm3<<8) | (immed12_imm8)); ]
 -{
 -  # don't export as an address, may be PIC code, and would add spurious symbols.
-+   ; remill_insn_size [ reloc = ((inst_start+4) $and 0xfffffffc) - ((immed12_i<<11) | (immed12_imm3<<8) | (immed12_imm8)); ] { 
+   ; remill_insn_size [ reloc = ((inst_start+4) $and 0xfffffffc) - ((immed12_i<<11) | (immed12_imm3<<8) | (immed12_imm8)); ] {
 +remill_please_dont_use_this_temp_name86:4=reloc;
 +claim_eq(remill_please_dont_use_this_temp_name86,  ((($(INST_NEXT_PTR)-remill_insn_size)+4) & 0xfffffffc) - ((immed12_i<<11) | (immed12_imm3<<8) | (immed12_imm8)));
 + # don't export as an address, may be PIC code, and would add spurious symbols.
@@ -111,32 +111,32 @@ index f210fab0e..64d29e35c 100644
 -}
 +
 +  }
-+ 
+
 
 PcrelOffset12: [reloc]		is thc0707=1; offset12
 -  [ reloc = ((inst_start+4) $and 0xfffffffc) + offset12; ]
 -{
 -  export *:4 reloc;
 -}
-+   ; remill_insn_size [ reloc = ((inst_start+4) $and 0xfffffffc) + offset12; ] { 
+   ; remill_insn_size [ reloc = ((inst_start+4) $and 0xfffffffc) + offset12; ] {
 +remill_please_dont_use_this_temp_name89:4=reloc;
 +claim_eq(remill_please_dont_use_this_temp_name89,  ((($(INST_NEXT_PTR)-remill_insn_size)+4) & 0xfffffffc) + offset12);
 + export *:4 reloc;
 +
 +  }
-+ 
+
 PcrelOffset12: [reloc]		is thc0707=0; offset12
 -  [ reloc = ((inst_start+4) $and 0xfffffffc) - offset12; ]
 -{
 -  export *:4 reloc;
 -}
-+   ; remill_insn_size [ reloc = ((inst_start+4) $and 0xfffffffc) - offset12; ] { 
+   ; remill_insn_size [ reloc = ((inst_start+4) $and 0xfffffffc) - offset12; ] {
 +remill_please_dont_use_this_temp_name8c:4=reloc;
 +claim_eq(remill_please_dont_use_this_temp_name8c,  ((($(INST_NEXT_PTR)-remill_insn_size)+4) & 0xfffffffc) - offset12);
 + export *:4 reloc;
 +
 +  }
-+ 
+
 
 @endif # defined(VERSION_6T2) || defined(VERSION_7)
 
@@ -148,39 +148,39 @@ index f210fab0e..64d29e35c 100644
 -{
 -  export *:4 reloc;
 -}
-+   ; remill_insn_size [ reloc = inst_start + 4 + ((thc0909 << 6) | (imm5 << 1)); ] { 
+   ; remill_insn_size [ reloc = inst_start + 4 + ((thc0909 << 6) | (imm5 << 1)); ] {
 +remill_please_dont_use_this_temp_name93:4=reloc;
 +claim_eq(remill_please_dont_use_this_temp_name93,  ($(INST_NEXT_PTR)-remill_insn_size) + 4 + ((thc0909 << 6) | (imm5 << 1)));
 + export *:4 reloc;
 +
 +  }
-+ 
+
 
 Addr8:	reloc	is soffset8
 -  [ reloc = (inst_start+4) + 2*soffset8; ]
 -{
 -  export *:4 reloc;
 -}
-+   ; remill_insn_size [ reloc = (inst_start+4) + 2*soffset8; ] { 
+   ; remill_insn_size [ reloc = (inst_start+4) + 2*soffset8; ] {
 +remill_please_dont_use_this_temp_name96:4=reloc;
 +claim_eq(remill_please_dont_use_this_temp_name96,  (($(INST_NEXT_PTR)-remill_insn_size)+4) + 2*soffset8);
 + export *:4 reloc;
 +
 +  }
-+ 
+
 
 Addr11:	reloc	is soffset11
 -  [ reloc = (inst_start+4) + 2*soffset11; ]
 -{
 -  export *:4 reloc;
 -}
-+   ; remill_insn_size [ reloc = (inst_start+4) + 2*soffset11; ] { 
+   ; remill_insn_size [ reloc = (inst_start+4) + 2*soffset11; ] {
 +remill_please_dont_use_this_temp_name99:4=reloc;
 +claim_eq(remill_please_dont_use_this_temp_name99,  (($(INST_NEXT_PTR)-remill_insn_size)+4) + 2*soffset11);
 + export *:4 reloc;
 +
 +  }
-+ 
+
 
 @if defined(VERSION_6T2) || defined(VERSION_7)
 
@@ -189,26 +189,26 @@ index f210fab0e..64d29e35c 100644
 -{
 -  export *:4 reloc;
 -}
-+   ; remill_insn_size [ reloc = inst_start + 4 + ((-1 << 20) $or (part2J2 << 19) $or (part2J1 << 18) $or (part2imm6 << 12) $or (part2imm11 << 1)); ] { 
+   ; remill_insn_size [ reloc = inst_start + 4 + ((-1 << 20) $or (part2J2 << 19) $or (part2J1 << 18) $or (part2imm6 << 12) $or (part2imm11 << 1)); ] {
 +remill_please_dont_use_this_temp_name9c:4=reloc;
 +claim_eq(remill_please_dont_use_this_temp_name9c,  ($(INST_NEXT_PTR)-remill_insn_size) + 4 + ((-1 << 20) | (part2J2 << 19) | (part2J1 << 18) | (part2imm6 << 12) | (part2imm11 << 1)));
 + export *:4 reloc;
 +
 +  }
-+ 
+
 
 ThAddr20:	reloc	is part2S=0 & part2imm6; part2J1 & part2J2 & part2imm11
 -  [ reloc = inst_start + 4 + ((part2J2 << 19) $or (part2J1 << 18) $or (part2imm6 << 12) $or (part2imm11 << 1)); ]
 -{
 -  export *:4 reloc;
 -}
-+   ; remill_insn_size [ reloc = inst_start + 4 + ((part2J2 << 19) $or (part2J1 << 18) $or (part2imm6 << 12) $or (part2imm11 << 1)); ] { 
+   ; remill_insn_size [ reloc = inst_start + 4 + ((part2J2 << 19) $or (part2J1 << 18) $or (part2imm6 << 12) $or (part2imm11 << 1)); ] {
 +remill_please_dont_use_this_temp_name9f:4=reloc;
 +claim_eq(remill_please_dont_use_this_temp_name9f,  ($(INST_NEXT_PTR)-remill_insn_size) + 4 + ((part2J2 << 19) | (part2J1 << 18) | (part2imm6 << 12) | (part2imm11 << 1)));
 + export *:4 reloc;
 +
 +  }
-+ 
+
 
 @endif # defined(VERSION_6T2) || defined(VERSION_7)
 
@@ -217,26 +217,26 @@ index f210fab0e..64d29e35c 100644
 -{
 -  export *:4 reloc;
 -}
-+   ; remill_insn_size [ reloc = inst_start + 4 + (((part2J1 $xor 1) << 23) $or ((part2J2 $xor 1) << 22) $or (offset10 << 12) $or (part2off << 1)); ] { 
+   ; remill_insn_size [ reloc = inst_start + 4 + (((part2J1 $xor 1) << 23) $or ((part2J2 $xor 1) << 22) $or (offset10 << 12) $or (part2off << 1)); ] {
 +remill_please_dont_use_this_temp_namea2:4=reloc;
 +claim_eq(remill_please_dont_use_this_temp_namea2,  ($(INST_NEXT_PTR)-remill_insn_size) + 4 + (((part2J1 ^ 1) << 23) | ((part2J2 ^ 1) << 22) | (offset10 << 12) | (part2off << 1)));
 + export *:4 reloc;
 +
 +  }
-+ 
+
 
 ThAddr24:	reloc	is offset10S=1 & offset10; part2J1 & part2J2 & part2off
 -  [ reloc = inst_start + 4 + ((-1 << 24) $or (part2J1 << 23) $or (part2J2 << 22) $or (offset10 << 12) $or (part2off << 1)); ]
 -{
 -  export *:4 reloc;
 -}
-+   ; remill_insn_size [ reloc = inst_start + 4 + ((-1 << 24) $or (part2J1 << 23) $or (part2J2 << 22) $or (offset10 << 12) $or (part2off << 1)); ] { 
+   ; remill_insn_size [ reloc = inst_start + 4 + ((-1 << 24) $or (part2J1 << 23) $or (part2J2 << 22) $or (offset10 << 12) $or (part2off << 1)); ] {
 +remill_please_dont_use_this_temp_namea5:4=reloc;
 +claim_eq(remill_please_dont_use_this_temp_namea5,  ($(INST_NEXT_PTR)-remill_insn_size) + 4 + ((-1 << 24) | (part2J1 << 23) | (part2J2 << 22) | (offset10 << 12) | (part2off << 1)));
 + export *:4 reloc;
 +
 +  }
-+ 
+
 
 @if defined(VERSION_5)
 
@@ -245,26 +245,26 @@ index f210fab0e..64d29e35c 100644
 -{
 -  export *:4 reloc;
 -}
-+   ; remill_insn_size [ reloc = ((inst_start + 4) $and 0xfffffffc) + (((part2J1 $xor 1) << 23) $or ((part2J2 $xor 1) << 22) $or (offset10 << 12) $or (part2off_10 << 2)); ] { 
+   ; remill_insn_size [ reloc = ((inst_start + 4) $and 0xfffffffc) + (((part2J1 $xor 1) << 23) $or ((part2J2 $xor 1) << 22) $or (offset10 << 12) $or (part2off_10 << 2)); ] {
 +remill_please_dont_use_this_temp_namea8:4=reloc;
 +claim_eq(remill_please_dont_use_this_temp_namea8,  ((($(INST_NEXT_PTR)-remill_insn_size) + 4) & 0xfffffffc) + (((part2J1 ^ 1) << 23) | ((part2J2 ^ 1) << 22) | (offset10 << 12) | (part2off_10 << 2)));
 + export *:4 reloc;
 +
 +  }
-+ 
+
 
 ThArmAddr23:	reloc	is offset10S=1 & offset10; part2J1 & part2J2 & part2off_10
 -  [ reloc = ((inst_start + 4) $and 0xfffffffc) + ((-1 << 24) $or (part2J1 << 23) $or (part2J2 << 22) $or (offset10 << 12) $or (part2off_10 << 2)); ]
 -{
 -  export *:4 reloc;
 -}
-+   ; remill_insn_size [ reloc = ((inst_start + 4) $and 0xfffffffc) + ((-1 << 24) $or (part2J1 << 23) $or (part2J2 << 22) $or (offset10 << 12) $or (part2off_10 << 2)); ] { 
+   ; remill_insn_size [ reloc = ((inst_start + 4) $and 0xfffffffc) + ((-1 << 24) $or (part2J1 << 23) $or (part2J2 << 22) $or (offset10 << 12) $or (part2off_10 << 2)); ] {
 +remill_please_dont_use_this_temp_nameab:4=reloc;
 +claim_eq(remill_please_dont_use_this_temp_nameab,  ((($(INST_NEXT_PTR)-remill_insn_size) + 4) & 0xfffffffc) + ((-1 << 24) | (part2J1 << 23) | (part2J2 << 22) | (offset10 << 12) | (part2off_10 << 2)));
 + export *:4 reloc;
 +
 +  }
-+ 
+
 
 @endif # VERSION_5
 
@@ -273,13 +273,13 @@ index f210fab0e..64d29e35c 100644
 
 # thstrlist_dec is the list of registers to be pushed
 -thsdec15: pc						is thc1515=1 & pc							{ *:4 mult_addr = inst_start+4; mult_addr = mult_addr - 4; }
-+thsdec15: pc						is thc1515=1 & pc							 ; remill_insn_size  { 
+thsdec15: pc						is thc1515=1 & pc							 ; remill_insn_size  {
 +remill_please_dont_use_this_temp_name267:4=inst_start;
 +claim_eq(remill_please_dont_use_this_temp_name267, ($(INST_NEXT_PTR)-remill_insn_size));
 + *:4 mult_addr = inst_start+4;
 + mult_addr = mult_addr - 4;
 +   }
-+ 
+
 thsdec15: 							is thc1515=0						{ }
 thsdec14: lr						is thc1414=1 & thsdec15 & lr & thc1515=0	{ * mult_addr=lr; mult_addr = mult_addr - 4; }
 thsdec14: lr,thsdec15				is thc1414=1 & thsdec15 & lr				{ * mult_addr=lr; mult_addr = mult_addr - 4; }
@@ -291,13 +291,13 @@ index f210fab0e..64d29e35c 100644
 -{
 -  export *:4 reloc;
 -}
-+   ; remill_insn_size [ reloc = ((inst_start+4) $and 0xfffffffc) + 4*immed8; ] { 
+   ; remill_insn_size [ reloc = ((inst_start+4) $and 0xfffffffc) + 4*immed8; ] {
 +remill_please_dont_use_this_temp_name2c2:4=reloc;
 +claim_eq(remill_please_dont_use_this_temp_name2c2,  ((($(INST_NEXT_PTR)-remill_insn_size)+4) & 0xfffffffc) + 4*immed8);
 + export *:4 reloc;
 +
 +  }
-+ 
+
 
 Sprel8Indirect: [sp,"#"^immval]	is sp & immed8   [ immval = immed8 * 4; ]  { local tmp = sp + immval; export tmp; }
 
@@ -307,7 +307,7 @@ index f210fab0e..64d29e35c 100644
 :bl^ItCond 	ThAddr24 			is TMode=1 & ItCond & (op11=0x1e; part2c1415=3 & part2c1212=1) & ThAddr24
 -{
 -  build ItCond;
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 + build ItCond;
 +remill_please_dont_use_this_temp_name31d:4=inst_next;
 +claim_eq(remill_please_dont_use_this_temp_name31d, $(INST_NEXT_PTR));
@@ -320,7 +320,7 @@ index f210fab0e..64d29e35c 100644
 -}
 +
 +  }
-+ 
+
 
 @ifndef VERSION_6T2
 
@@ -330,7 +330,7 @@ index f210fab0e..64d29e35c 100644
 :bl^ItCond lr			is TMode=1 & ItCond & op11=0x1f & offset11=0 & lr
 -{
 -  build ItCond;
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 + build ItCond;
 +
   local dest = lr;
@@ -345,7 +345,7 @@ index f210fab0e..64d29e35c 100644
 -}
 +
 +  }
-+ 
+
 
 :blx^ItCond "#"^off 	is TMode=1 & ItCond & op11=0x1d & offset11 & thc0000=0 [ off = offset11 << 1; ]
 {
@@ -355,7 +355,7 @@ index f210fab0e..64d29e35c 100644
 :bl^ItCond 	ThAddr24 			is TMode=1 & CALLoverride=1 & ItCond & (op11=0x1e; part2c1415=3 & part2c1212=1) & ThAddr24
 -{
 -  build ItCond;
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 + build ItCond;
 +remill_please_dont_use_this_temp_name321:4=inst_next;
 +claim_eq(remill_please_dont_use_this_temp_name321, $(INST_NEXT_PTR));
@@ -368,7 +368,7 @@ index f210fab0e..64d29e35c 100644
 -}
 +
 +  }
-+ 
+
 
 bxns: "" is thc0003 { }
 bxns: "ns" is thc0002=0b100 { }
@@ -378,7 +378,7 @@ index f210fab0e..64d29e35c 100644
 :blx^bxns^ItCond	Hrm0305			is TMode=1 & ItCond & op7=0x08f & Hrm0305 & bxns
 -{
 -  build ItCond;
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 + build ItCond;
 +
   BXWritePC(Hrm0305);
@@ -393,7 +393,7 @@ index f210fab0e..64d29e35c 100644
 -}
 +
 +  }
-+ 
+
 
 @endif # VERSION_5
 
@@ -403,7 +403,7 @@ index f210fab0e..64d29e35c 100644
 :chka^ItCond  Hrn0002,Rm0306    is TMode=1 & ItCond & TEEMode=1 & op8=0xca & Rm0306 & Hrn0002
 -{
 -    build ItCond;
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 + build ItCond;
 +
     local tmp = Hrn0002 <= Rm0306;
@@ -419,7 +419,7 @@ index f210fab0e..64d29e35c 100644
 -}
 +
 +  }
-+ 
+
 
 :clrex^ItCond                     is TMode=1 & ItCond & op0=0xf3bf; op0=0x8f2f
 {
@@ -429,7 +429,7 @@ index f210fab0e..64d29e35c 100644
 :mrs^ItCond Rd0811,basepri 		is TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm=17 & basepri
 -{
 -  build ItCond;
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 + build ItCond;
 +
   Rd0811 = 0;
@@ -444,14 +444,14 @@ index f210fab0e..64d29e35c 100644
 -}
 +
 +  }
-+ 
+
 
 basepri_max: "basepri_max" 	is epsilon {}
 
 :mrs^ItCond Rd0811,basepri_max 		is TMode=1 & ItCond & op0=0xf3ef; op12=0x8 & Rd0811 & sysm=18 & basepri_max
 -{
 -  build ItCond;
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 + build ItCond;
 +
   Rd0811 = 0;
@@ -466,7 +466,7 @@ index f210fab0e..64d29e35c 100644
 -}
 +
 +  }
-+ 
+
 
 faultmask: "faultmask"		is epsilon {}
 
@@ -476,7 +476,7 @@ index f210fab0e..64d29e35c 100644
 :msr^ItCond msp,Rn0003 		is TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm=8 & msp
 -{
 -  build ItCond;
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 + build ItCond;
 +
   b:1 = isCurrentModePrivileged();
@@ -489,12 +489,12 @@ index f210fab0e..64d29e35c 100644
 -}
 +
 +  }
-+ 
+
 
 :msr^ItCond psp,Rn0003 		is TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm=9 & psp
 -{
 -  build ItCond;
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 + build ItCond;
 +
   b:1 = isCurrentModePrivileged();
@@ -507,7 +507,7 @@ index f210fab0e..64d29e35c 100644
 -}
 +
 +  }
-+ 
+
 
 :msr^ItCond primask,Rn0003 		is TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm=16 & primask
 {
@@ -517,7 +517,7 @@ index f210fab0e..64d29e35c 100644
 :msr^ItCond basepri,Rn0003 		is TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm=17 & basepri
 -{
 -  build ItCond;
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 + build ItCond;
 +
   b:1 = isCurrentModePrivileged();
@@ -530,7 +530,7 @@ index f210fab0e..64d29e35c 100644
 -}
 +
 +  }
-+ 
+
 
 :msr^ItCond basepri_max,Rn0003 		is TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm=18 & basepri_max
 {
@@ -540,7 +540,7 @@ index f210fab0e..64d29e35c 100644
 :msr^ItCond faultmask,Rn0003 		is TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm=19 & faultmask
 -{
 -  build ItCond;
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 + build ItCond;
 +
   b:1 = isCurrentModePrivileged();
@@ -553,7 +553,7 @@ index f210fab0e..64d29e35c 100644
 -}
 +
 +  }
-+ 
+
 
 define pcodeop setStackMode;
 
@@ -563,7 +563,7 @@ index f210fab0e..64d29e35c 100644
 :strex^ItCond    Rd0811,Rt1215,[Rn0003,Immed8_4]   is TMode=1 & ItCond & op4=0xe84 & Rn0003; Rt1215 & Rd0811 & Immed8_4
 -{
 -   build ItCond;
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 + build ItCond;
 +
   local tmp = Rn0003 + Immed8_4;
@@ -582,7 +582,7 @@ index f210fab0e..64d29e35c 100644
 -}
 +
 +  }
-+ 
+
 
 @endif # VERSION_6T2 || VERSION_7
 
@@ -591,7 +591,7 @@ index f210fab0e..64d29e35c 100644
 :strexb^ItCond    Rd0003,Rt1215,[Rn0003]   is TMode=1 & ItCond & op4=0xe8c & Rn0003; Rt1215 & thc0811=15 & thc0407=4 & Rd0003
 -{
 -   build ItCond;
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 + build ItCond;
 +
   local tmp = Rn0003;
@@ -612,12 +612,12 @@ index f210fab0e..64d29e35c 100644
 -}
 +
 +  }
-+ 
+
 
 :strexh^ItCond    Rd0003,Rt1215,[Rn0003]   is TMode=1 & ItCond & op4=0xe8c & Rn0003; Rt1215 & thc0811=15 & thc0407=5 & Rd0003
 -{
 -   build ItCond;
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 + build ItCond;
 +
   local tmp = Rn0003;
@@ -638,12 +638,12 @@ index f210fab0e..64d29e35c 100644
 -}
 +
 +  }
-+ 
+
 
 :strexd^ItCond    Rd0003,Rt1215,Rt0811,[Rn0003]   is TMode=1 & ItCond & op4=0xe8c & Rn0003; Rt1215 & Rt0811 & thc0407=7 & Rd0003
 -{
 -   build ItCond;
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 + build ItCond;
 +
   local tmp = Rn0003;
@@ -666,7 +666,7 @@ index f210fab0e..64d29e35c 100644
 -}
 +
 +  }
-+ 
+
 
 @endif # VERSION_7
 
@@ -676,7 +676,7 @@ index f210fab0e..64d29e35c 100644
 :tbb^ItCond  [Rn0003,Rm0003]    is TMode=1 & ItCond & op4=0xe8d & Rn0003; op8=0xf0 & thc0507=0 & thc0404=0 & Rm0003
 -{
 -   build ItCond;
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 + build ItCond;
 +
    local tmp = Rn0003 + Rm0003;
@@ -693,12 +693,12 @@ index f210fab0e..64d29e35c 100644
 -}
 +
 +  }
-+ 
+
 
 :tbh^ItCond  [Rn0003,Rm0003]    is TMode=1 & ItCond & op4=0xe8d & Rn0003; op8=0xf0 & thc0507=0 & thc0404=1 & Rm0003
 -{
 -   build ItCond;
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 + build ItCond;
 +
    local tmp = Rn0003 + (Rm0003 * 2);
@@ -715,13 +715,13 @@ index f210fab0e..64d29e35c 100644
 -}
 +
 +  }
-+ 
+
 
 Pcrel: [pc,Rm0003]  is Rm0003 & thc0404=0 & pc
 -{
 -   local tmp = Rm0003; tmp = inst_next + tmp; val:1 = *tmp; tmp = zext(val); export tmp;
 -}
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 + local tmp = Rm0003;
 +remill_please_dont_use_this_temp_name5cd:4=inst_next;
 +claim_eq(remill_please_dont_use_this_temp_name5cd, $(INST_NEXT_PTR));
@@ -731,12 +731,12 @@ index f210fab0e..64d29e35c 100644
 + export tmp;
 +
 +  }
-+ 
+
 Pcrel: [pc,Rm0003]  is Rm0003 & thc0404=1 & pc
 -{
 -   local tmp = Rm0003; tmp = inst_next + (tmp * 2); val:2 = *tmp; tmp = zext(val); export tmp;
 -}
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 + local tmp = Rm0003;
 +remill_please_dont_use_this_temp_name5cf:4=inst_next;
 +claim_eq(remill_please_dont_use_this_temp_name5cf, $(INST_NEXT_PTR));
@@ -746,12 +746,12 @@ index f210fab0e..64d29e35c 100644
 + export tmp;
 +
 +  }
-+ 
+
 
 :tbb^ItCond  Pcrel    is TMode=1 & ItCond & op4=0xe8d & thc0003=15; op8=0xf0 & thc0507=0 & thc0404=0 & Pcrel
 -{
 -   build ItCond;
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 + build ItCond;
 +
    SetThumbMode(1);
@@ -764,12 +764,12 @@ index f210fab0e..64d29e35c 100644
 -}
 +
 +  }
-+ 
+
 
 :tbh^ItCond  Pcrel    is TMode=1 & ItCond & op4=0xe8d & thc0003=15; op8=0xf0 & thc0507=0 & thc0404=1 & Pcrel
 -{
 -   build ItCond;
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 + build ItCond;
 +
    SetThumbMode(1);
@@ -782,10 +782,10 @@ index f210fab0e..64d29e35c 100644
 -}
 +
 +  }
-+ 
+
 
 @endif # VERSION_6T2 || VERSION_7
 
 -- 
-2.39.2 (Apple Git-143)
+2.34.1

@@ -1,14 +1,14 @@
-From 85949f749c4cd31a03edfc181dc4cbed57ebf7c3 Mon Sep 17 00:00:00 2001
+From 1e54d8a6734348789b561489a84da5a7e45315ea Mon Sep 17 00:00:00 2001
 From: 2over12 <ian.smith@trailofbits.com>
 Date: Mon, 24 Apr 2023 13:29:41 -0400
-Subject: [PATCH] ppc_common
+Subject: [PATCH 08/13] ppc_common

 ---
 .../PowerPC/data/languages/ppc_common.sinc    | 21 +++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

 diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc
-index aaa76cc4a..4625bbe5e 100644
+index 46aa86c74c..60c96058eb 100644
 --- a/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc
 +++ b/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc
@@ -3,6 +3,10 @@
@@ -27,7 +27,7 @@ index aaa76cc4a..4625bbe5e 100644
       v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 ];
       
 +
-+remill_insn_size: calculated_size is epsilon [calculated_size= inst_next-inst_start; ] { local insn_size_hinted:$(REGISTER_SIZE)=calculated_size; 
+remill_insn_size: calculated_size is epsilon [calculated_size= inst_next-inst_start; ] { local insn_size_hinted:$(REGISTER_SIZE)=calculated_size;
 + export insn_size_hinted; }
 vrD: vrDD	is vrDD & vrDR { export vrDR; }      
 vrA: vrAD	is vrAD & vrAR { export vrAR; }      
@@ -37,23 +37,23 @@ index aaa76cc4a..4625bbe5e 100644
 REL_ABS:			is AA = 0 {}
 
 -addressLI: reloc		is LI & AA=0 	[ reloc = inst_start + LI*4;] 	{ export *[ram]:4 reloc; }
-+addressLI: reloc		is LI & AA=0 	 ; remill_insn_size [ reloc = inst_start + LI*4;] { 
+addressLI: reloc		is LI & AA=0 	 ; remill_insn_size [ reloc = inst_start + LI*4;] {
 +remill_please_dont_use_this_temp_named:$(REGISTER_SIZE)=reloc;
 +claim_eq(remill_please_dont_use_this_temp_named,  ($(INST_NEXT_PTR)-remill_insn_size) + LI*4);
 + export *[ram]:4 reloc;
 +   }
-+ 
+
 addressLI: reloc 	is LI & AA=1		[ reloc = LI*4; ]				{ export *[ram]:4 reloc; }
 -addressBD: reloc		is BD & AA=0		[ reloc = inst_start + BD*4; ]	{ export *[ram]:4 reloc; }
-+addressBD: reloc		is BD & AA=0		 ; remill_insn_size [ reloc = inst_start + BD*4; ] { 
+addressBD: reloc		is BD & AA=0		 ; remill_insn_size [ reloc = inst_start + BD*4; ] {
 +remill_please_dont_use_this_temp_name12:$(REGISTER_SIZE)=reloc;
 +claim_eq(remill_please_dont_use_this_temp_name12,  ($(INST_NEXT_PTR)-remill_insn_size) + BD*4);
 + export *[ram]:4 reloc;
 +   }
-+ 
+
 addressBD: reloc		is BD & AA=1		[ reloc = BD*4; ]				{ export *[ram]:4 reloc; }
 
 OFF16SH: val		is D0 & D1 & D2 [ val = ((D0 << 6) | (D1 << 1) | D2) << 16; ] { export *[const]:4 val;}
 -- 
-2.39.2 (Apple Git-143)
+2.34.1

@@ -1,14 +1,14 @@
-From d2a32d5da79f0d7f5ed9c6cf8e8ea4fe54c04313 Mon Sep 17 00:00:00 2001
+From 9b78cadbee4c0fa7b2ca9056dc0bbc5ba0872505 Mon Sep 17 00:00:00 2001
 From: 2over12 <ian.smith@trailofbits.com>
 Date: Mon, 24 Apr 2023 13:29:42 -0400
-Subject: [PATCH] ppc_instructions
+Subject: [PATCH 09/13] ppc_instructions

 ---
 .../data/languages/ppc_instructions.sinc      | 88 ++++++++++++++-----
 1 file changed, 68 insertions(+), 20 deletions(-)

 diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_instructions.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_instructions.sinc
-index b9ca56c0f..647b789d0 100644
+index b9ca56c0ff..7decec6831 100644
 --- a/Ghidra/Processors/PowerPC/data/languages/ppc_instructions.sinc
 +++ b/Ghidra/Processors/PowerPC/data/languages/ppc_instructions.sinc
@@ -368,10 +368,15 @@
@@ -16,7 +16,7 @@ index b9ca56c0f..647b789d0 100644
 #bl (Load LR) 
 :bl addressBD 		is $(NOTVLE) & OP=16 & addressBD & REL_ABS & BO_0=1 & BO_2=1 & BD=1 & LK=1
 -{
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 +remill_please_dont_use_this_temp_name45:$(REGISTER_SIZE)=inst_next;
 +claim_eq(remill_please_dont_use_this_temp_name45, $(INST_NEXT_PTR));
 	LR = inst_next;
@@ -25,7 +25,7 @@ index b9ca56c0f..647b789d0 100644
 -}
 +
 +  }
-+ 
+
 
 
 
@@ -35,29 +35,29 @@ index b9ca56c0f..647b789d0 100644
 :b^CC^"ctr" 	is $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR= 0 & BH=0 & LK=0 & BITS_13_15=0 & XOP_1_10=528
 -{
 -	if (!CC) goto inst_next; 
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 +remill_please_dont_use_this_temp_name4f:$(REGISTER_SIZE)=inst_next;
 +claim_eq(remill_please_dont_use_this_temp_name4f, $(INST_NEXT_PTR));
 +	if (!CC) goto inst_next;
-+ 
+
 	goto [CTR];
 -}
 +
 +  }
-+ 
+
 :b^CC^"ctr" BH  	is $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR= 0 & BH & BH_BITS!=0 & LK=0 & BITS_13_15=0 & XOP_1_10=528
 -{
 -	if (!CC) goto inst_next; 
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 +remill_please_dont_use_this_temp_name51:$(REGISTER_SIZE)=inst_next;
 +claim_eq(remill_please_dont_use_this_temp_name51, $(INST_NEXT_PTR));
 +	if (!CC) goto inst_next;
-+ 
+
 	goto [CTR];
 -}
 +
 +  }
-+ 
+
 
 #bgectrl		0x4c 80 04 21
 :b^CC^"ctrl"  	is $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR= 0 & BH=0 & LK=1 & BITS_13_15=0 & XOP_1_10=528
@@ -67,31 +67,31 @@ index b9ca56c0f..647b789d0 100644
 :b^CC^"ctr" BI_CR  		is $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH=0 & LK=0 & BITS_13_15=0 & XOP_1_10=528
 -{
 -	if (!CC) goto inst_next; 
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 +remill_please_dont_use_this_temp_name53:$(REGISTER_SIZE)=inst_next;
 +claim_eq(remill_please_dont_use_this_temp_name53, $(INST_NEXT_PTR));
 +	if (!CC) goto inst_next;
-+ 
+
 	goto [CTR];
 -}
 +
 +  }
-+ 
+
 
 #bnectr cr2,#0x3 0x4c 8c 1c 20
 :b^CC^"ctr" BI_CR,BH  		is $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH & LK=0 & BITS_13_15=0 & XOP_1_10=528
 -{
 -	if (!CC) goto inst_next; 
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 +remill_please_dont_use_this_temp_name55:$(REGISTER_SIZE)=inst_next;
 +claim_eq(remill_please_dont_use_this_temp_name55, $(INST_NEXT_PTR));
 +	if (!CC) goto inst_next;
-+ 
+
 	goto [CTR];
 -}
 +
 +  }
-+ 
+
 
 #bgectrl cr2,LAB_xxxx		0x4c 8c 04 21
 :b^CC^"ctrl" BI_CR 		is $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH=0 & LK=1 & BITS_13_15=0 & XOP_1_10=528
@@ -100,7 +100,7 @@ index b9ca56c0f..647b789d0 100644
 #fsel f0r,fr0,fr0,fr0	0xfc 00 00 2e
 :fsel fD,fA,fC,fB	is $(NOTVLE) & OP=63 & fD & fA & fB & fC & XOP_1_5=23 & Rc=0
 -{
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 	local tmpfA = fA;
 +
 	local tmpfB = fB;
@@ -117,7 +117,7 @@ index b9ca56c0f..647b789d0 100644
 -}
 +
 +  }
-+ 
+
 
 #fsel. fr0,fr0,fr0,fr0	0xfc 00 00 2f
 :fsel. fD,fA,fC,fB	is $(NOTVLE) & OP=63 & fD & fA & fB & fC & XOP_1_5=23 & Rc=1
@@ -126,7 +126,7 @@ index b9ca56c0f..647b789d0 100644
 #stdcx. r0,8(0)	0x7c 00 01 AD	
 :stdcx. S,RA_OR_ZERO,B 	is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=214 & BIT_0=1
 -{
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 	EA:$(REGISTER_SIZE) = RA_OR_ZERO + B;
 +remill_please_dont_use_this_temp_name265:$(REGISTER_SIZE)=inst_next;
 +claim_eq(remill_please_dont_use_this_temp_name265, $(INST_NEXT_PTR));
@@ -140,7 +140,7 @@ index b9ca56c0f..647b789d0 100644
 -}
 +
 +  }
-+ 
+
 
 #stdu r0,8(0)	0xf8 00 00 01	
 #stdu r0,8(r2)	0xf8 02 00 01	
@@ -149,7 +149,7 @@ index b9ca56c0f..647b789d0 100644
 #stwcx. r0,8(0)	0x7c 00 01 2D	
 :stwcx. S,RA_OR_ZERO,B 	is OP=31 & S & RA_OR_ZERO & B & XOP_1_10=150 & BIT_0=1
 -{
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 	EA:$(REGISTER_SIZE) = RA_OR_ZERO + B;
 +remill_please_dont_use_this_temp_name28b:$(REGISTER_SIZE)=inst_next;
 +claim_eq(remill_please_dont_use_this_temp_name28b, $(INST_NEXT_PTR));
@@ -163,10 +163,10 @@ index b9ca56c0f..647b789d0 100644
 -}
 +
 +  }
-+ 
+
 
 #stwu r0,r0			0x94 00 00 00
 :stwu S,dPlusRaAddress		is $(NOTVLE) & OP=37 & S & A & dPlusRaAddress
 -- 
-2.39.2 (Apple Git-143)
+2.34.1

@@ -1,14 +1,14 @@
-From 5dc24c4d257bb1359e72c012ccd145cab44c3599 Mon Sep 17 00:00:00 2001
+From df78f4abfdf6db77a9d9a5ff52dac343b9168cdc Mon Sep 17 00:00:00 2001
 From: 2over12 <ian.smith@trailofbits.com>
 Date: Mon, 24 Apr 2023 13:29:42 -0400
-Subject: [PATCH] ppc_isa
+Subject: [PATCH 10/13] ppc_isa

 ---
 .../PowerPC/data/languages/ppc_isa.sinc       | 52 ++++++++++++++-----
 1 file changed, 38 insertions(+), 14 deletions(-)

 diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc
-index 3148135f1..e30412e89 100644
+index 3148135f19..cda7398ef3 100644
 --- a/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc
 +++ b/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc
@@ -2390,15 +2390,25 @@ define pcodeop InstructionCacheBlockLockSetX;
@@ -17,29 +17,29 @@ index 3148135f1..e30412e89 100644
 :b^CC^"ctar" 	is $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR= 0 & BH=0 & LK=0 & BITS_13_15=0 & XOP_1_10=560
 -{
 -	if (!CC) goto inst_next; 
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 +remill_please_dont_use_this_temp_name18d:$(REGISTER_SIZE)=inst_next;
 +claim_eq(remill_please_dont_use_this_temp_name18d, $(INST_NEXT_PTR));
 +	if (!CC) goto inst_next;
-+ 
+
 	goto [TAR];
 -}
 +
 +  }
-+ 
+
 :b^CC^"ctar" BH  	is $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR= 0 & BH & BH_BITS!=0 & LK=0 & BITS_13_15=0 & XOP_1_10=560
 -{
 -	if (!CC) goto inst_next; 
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 +remill_please_dont_use_this_temp_name18f:$(REGISTER_SIZE)=inst_next;
 +claim_eq(remill_please_dont_use_this_temp_name18f, $(INST_NEXT_PTR));
 +	if (!CC) goto inst_next;
-+ 
+
 	goto [TAR];
 -}
 +
 +  }
-+ 
+
 
 :b^CC^"ctarl"  	is $(NOTVLE) & OP=19 & CC & BO_0=0 & BO_2=1 & BI_CR= 0 & BH=0 & LK=1 & BITS_13_15=0 & XOP_1_10=560
 										[ linkreg=0; globalset(inst_start,linkreg); ]
@@ -49,30 +49,30 @@ index 3148135f1..e30412e89 100644
 :b^CC^"ctar" BI_CR  		is $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH=0 & LK=0 & BITS_13_15=0 & XOP_1_10=560
 -{
 -	if (!CC) goto inst_next; 
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 +remill_please_dont_use_this_temp_name191:$(REGISTER_SIZE)=inst_next;
 +claim_eq(remill_please_dont_use_this_temp_name191, $(INST_NEXT_PTR));
 +	if (!CC) goto inst_next;
-+ 
+
 	goto [TAR];
 -}
 +
 +  }
-+ 
+
 
 :b^CC^"ctar" BI_CR,BH  		is $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH & LK=0 & BITS_13_15=0 & XOP_1_10=560
 -{
 -	if (!CC) goto inst_next; 
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 +remill_please_dont_use_this_temp_name193:$(REGISTER_SIZE)=inst_next;
 +claim_eq(remill_please_dont_use_this_temp_name193, $(INST_NEXT_PTR));
 +	if (!CC) goto inst_next;
-+ 
+
 	goto [TAR];
 -}
 +
 +  }
-+ 
+
 
 :b^CC^"ctarl" BI_CR 		is $(NOTVLE) & OP=19 & CC & BI_CR & BO_0=0 & BO_2=1 & BH=0 & LK=1 & BITS_13_15=0 & XOP_1_10=560
 										[ linkreg=0; globalset(inst_start,linkreg); ]
@@ -81,17 +81,17 @@ index 3148135f1..e30412e89 100644
 # v3.0
 
 -:addpcis D,OFF16SH		is $(NOTVLE) & OP=19 & XOP_1_5=2 & D & OFF16SH {
-+:addpcis D,OFF16SH		is $(NOTVLE) & OP=19 & XOP_1_5=2 & D & OFF16SH  ; remill_insn_size  { 
+:addpcis D,OFF16SH		is $(NOTVLE) & OP=19 & XOP_1_5=2 & D & OFF16SH  ; remill_insn_size  {
 +remill_please_dont_use_this_temp_name1b9:$(REGISTER_SIZE)=inst_next;
 +claim_eq(remill_please_dont_use_this_temp_name1b9, $(INST_NEXT_PTR));
 	D = inst_next + sext(OFF16SH);
 -}
 +
 +  }
-+ 
+
 
 :cmpeqb CRFD,A,B			is $(NOTVLE) & OP=31 & BITS_21_22=0 & BIT_0=0 & XOP_1_10=224 & A & B & CRFD {
 	tmpa:1 = A:1;
 -- 
-2.39.2 (Apple Git-143)
+2.34.1

@@ -1,14 +1,14 @@
-From 1b4ba461713e9e04f3cab3b09f675bf6bf4e7a3f Mon Sep 17 00:00:00 2001
+From 2d6809a4c60a8c9f60cf32b146749c4ade579680 Mon Sep 17 00:00:00 2001
 From: 2over12 <ian.smith@trailofbits.com>
 Date: Mon, 24 Apr 2023 13:29:42 -0400
-Subject: [PATCH] ppc_vle
+Subject: [PATCH 11/13] ppc_vle

 ---
 .../PowerPC/data/languages/ppc_vle.sinc       | 68 +++++++++++++++----
 1 file changed, 55 insertions(+), 13 deletions(-)

 diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc
-index 3b6283470..6b174c491 100644
+index 3b62834704..fd3f2cf11a 100644
 --- a/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc
 +++ b/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc
@@ -20,9 +20,24 @@ CC32: "ns"		is BI_CC_VLE=3 & BO_VLE=0 & BI_CR_VLE & BI_CC_VLE { tmp:1 = 0; getCr
@@ -18,24 +18,24 @@ index 3b6283470..6b174c491 100644
 -addrBD8: reloc	is BD8_VLE 		[ reloc = inst_start + (BD8_VLE << 1);] 	{ export *[ram]:4 reloc; }
 -addrBD15: reloc	is BD15_VLE 	[ reloc = inst_start + (BD15_VLE << 1);] 	{ export *[ram]:4 reloc; }
 -addrBD24: reloc	is BD24_VLE 	[ reloc = inst_start + (BD24_VLE << 1);] 	{ export *[ram]:4 reloc; }
-+addrBD8: reloc	is BD8_VLE 		 ; remill_insn_size [ reloc = inst_start + (BD8_VLE << 1);] { 
+addrBD8: reloc	is BD8_VLE 		 ; remill_insn_size [ reloc = inst_start + (BD8_VLE << 1);] {
 +remill_please_dont_use_this_temp_name23:$(REGISTER_SIZE)=reloc;
 +claim_eq(remill_please_dont_use_this_temp_name23,  ($(INST_NEXT_PTR)-remill_insn_size) + (BD8_VLE << 1));
 + export *[ram]:4 reloc;
 +   }
-+ 
-+addrBD15: reloc	is BD15_VLE 	 ; remill_insn_size [ reloc = inst_start + (BD15_VLE << 1);] { 
+
+addrBD15: reloc	is BD15_VLE 	 ; remill_insn_size [ reloc = inst_start + (BD15_VLE << 1);] {
 +remill_please_dont_use_this_temp_name26:$(REGISTER_SIZE)=reloc;
 +claim_eq(remill_please_dont_use_this_temp_name26,  ($(INST_NEXT_PTR)-remill_insn_size) + (BD15_VLE << 1));
 + export *[ram]:4 reloc;
 +   }
-+ 
-+addrBD24: reloc	is BD24_VLE 	 ; remill_insn_size [ reloc = inst_start + (BD24_VLE << 1);] { 
+
+addrBD24: reloc	is BD24_VLE 	 ; remill_insn_size [ reloc = inst_start + (BD24_VLE << 1);] {
 +remill_please_dont_use_this_temp_name29:$(REGISTER_SIZE)=reloc;
 +claim_eq(remill_please_dont_use_this_temp_name29,  ($(INST_NEXT_PTR)-remill_insn_size) + (BD24_VLE << 1));
 + export *[ram]:4 reloc;
 +   }
-+ 
+
 
 d8PlusRaAddress: S8IMM(A)					is S8IMM & A			{tmp:$(REGISTER_SIZE) = A+S8IMM; export tmp;  }
 d8PlusRaOrZeroAddress: S8IMM(RA_OR_ZERO)	is S8IMM & RA_OR_ZERO	{tmp:$(REGISTER_SIZE) = RA_OR_ZERO+S8IMM; export tmp; }
@@ -44,7 +44,7 @@ index 3b6283470..6b174c491 100644
 }
 
 -:e_bl addrBD24					is $(ISVLE) & OP=30 & BIT_25=0 & LK=1 & addrBD24 {
-+:e_bl addrBD24					is $(ISVLE) & OP=30 & BIT_25=0 & LK=1 & addrBD24  ; remill_insn_size  { 
+:e_bl addrBD24					is $(ISVLE) & OP=30 & BIT_25=0 & LK=1 & addrBD24  ; remill_insn_size  {
 +remill_please_dont_use_this_temp_name3a:$(REGISTER_SIZE)=inst_next;
 +claim_eq(remill_please_dont_use_this_temp_name3a, $(INST_NEXT_PTR));
 	LR = inst_next;
@@ -53,14 +53,14 @@ index 3b6283470..6b174c491 100644
 -}
 +
 +  }
-+ 
+
 
 :se_b addrBD8					is $(ISVLE) & OP6_VLE=58 & BIT9_VLE=0 & LK8_VLE=0 & addrBD8 {
 	goto addrBD8;
 }
 
 -:se_bl addrBD8					is $(ISVLE) & OP6_VLE=58 & BIT9_VLE=0 & LK8_VLE=1 & addrBD8 {
-+:se_bl addrBD8					is $(ISVLE) & OP6_VLE=58 & BIT9_VLE=0 & LK8_VLE=1 & addrBD8  ; remill_insn_size  { 
+:se_bl addrBD8					is $(ISVLE) & OP6_VLE=58 & BIT9_VLE=0 & LK8_VLE=1 & addrBD8  ; remill_insn_size  {
 +remill_please_dont_use_this_temp_name3e:$(REGISTER_SIZE)=inst_next;
 +claim_eq(remill_please_dont_use_this_temp_name3e, $(INST_NEXT_PTR));
 	LR = inst_next;
@@ -69,13 +69,13 @@ index 3b6283470..6b174c491 100644
 -}
 +
 +  }
-+ 
+
 
 # NOTE: For the conditional branches, the "official" mnemonics have just bc and bcl.
 # We use extended mnemonics so the display is understandable without having to cross-
 # reference multiple tables.
 -:e_b^CC32 addrBD15				is $(ISVLE) & OP=30 & XOP_VLE=8 & LK=0 & addrBD15 & CC32 {
-+:e_b^CC32 addrBD15				is $(ISVLE) & OP=30 & XOP_VLE=8 & LK=0 & addrBD15 & CC32  ; remill_insn_size  { 
+:e_b^CC32 addrBD15				is $(ISVLE) & OP=30 & XOP_VLE=8 & LK=0 & addrBD15 & CC32  ; remill_insn_size  {
 +remill_please_dont_use_this_temp_name40:$(REGISTER_SIZE)=inst_next;
 +claim_eq(remill_please_dont_use_this_temp_name40, $(INST_NEXT_PTR));
 	if (CC32 == 0) goto inst_next;
@@ -85,9 +85,9 @@ index 3b6283470..6b174c491 100644
 
 -:e_b^CC32^"l" addrBD15			is $(ISVLE) & OP=30 & XOP_VLE=8 & LK=1 & addrBD15 & CC32 {
 +  }
-+ 
 +
-+:e_b^CC32^"l" addrBD15			is $(ISVLE) & OP=30 & XOP_VLE=8 & LK=1 & addrBD15 & CC32  ; remill_insn_size  { 
+
+:e_b^CC32^"l" addrBD15			is $(ISVLE) & OP=30 & XOP_VLE=8 & LK=1 & addrBD15 & CC32  ; remill_insn_size  {
 +remill_please_dont_use_this_temp_name42:$(REGISTER_SIZE)=inst_next;
 +claim_eq(remill_please_dont_use_this_temp_name42, $(INST_NEXT_PTR));
 	if (CC32 == 0) goto inst_next;
@@ -100,9 +100,9 @@ index 3b6283470..6b174c491 100644
 
 -:se_b^CC16 addrBD8				is $(ISVLE) & OP5_VLE=28 & addrBD8 & CC16 {
 +  }
-+ 
 +
-+:se_b^CC16 addrBD8				is $(ISVLE) & OP5_VLE=28 & addrBD8 & CC16  ; remill_insn_size  { 
+
+:se_b^CC16 addrBD8				is $(ISVLE) & OP5_VLE=28 & addrBD8 & CC16  ; remill_insn_size  {
 +remill_please_dont_use_this_temp_name44:$(REGISTER_SIZE)=inst_next;
 +claim_eq(remill_please_dont_use_this_temp_name44, $(INST_NEXT_PTR));
 	if (CC16 == 0) goto inst_next;
@@ -111,10 +111,10 @@ index 3b6283470..6b174c491 100644
 -}
 +
 +  }
-+ 
+
 #######
 
 :se_bctr						is $(ISVLE) & OP15_VLE=3 & LK0_VLE=0 {
 -- 
-2.39.2 (Apple Git-143)
+2.34.1

@@ -1,14 +1,14 @@
-From 15929962669ffa1a719594606c4ec33c00b1542e Mon Sep 17 00:00:00 2001
+From 1d942a786a841bd3a0725e3b5279985ef45aafe3 Mon Sep 17 00:00:00 2001
 From: 2over12 <ian.smith@trailofbits.com>
 Date: Mon, 24 Apr 2023 13:29:42 -0400
-Subject: [PATCH] quicciii
+Subject: [PATCH 12/13] quicciii

 ---
 .../Processors/PowerPC/data/languages/quicciii.sinc  | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

 diff --git a/Ghidra/Processors/PowerPC/data/languages/quicciii.sinc b/Ghidra/Processors/PowerPC/data/languages/quicciii.sinc
-index 8b7977bce..9029b616b 100644
+index 8b7977bce2..b0ffbb754d 100644
 --- a/Ghidra/Processors/PowerPC/data/languages/quicciii.sinc
 +++ b/Ghidra/Processors/PowerPC/data/languages/quicciii.sinc
@@ -62,13 +62,21 @@ define pcodeop invalidateTLB;
@@ -16,7 +16,7 @@ index 8b7977bce..9029b616b 100644
 
 :isel^CC_X_OPm D,RA_OR_ZERO,B,CC_X_OP  is OP=31 & D & RA_OR_ZERO & B & CC_X_OP & CC_X_OPm & XOP_1_5=15
 -{
-+ ; remill_insn_size  { 
+ ; remill_insn_size  {
 	local tmp:$(REGISTER_SIZE) = RA_OR_ZERO;
 +
 	D = B;
@@ -31,10 +31,10 @@ index 8b7977bce..9029b616b 100644
 -}
 +
 +  }
-+ 
+
 
 @ifndef IS_ISA
 #mbar 0         #FIXME
 -- 
-2.39.2 (Apple Git-143)
+2.34.1