Implement a bunch of missing AVX instructions (#595)

This commit is contained in:
Duncan Ogilvie
2022-05-18 23:38:57 +02:00
committed by GitHub
parent d48df5e6be
commit 85d287c4f8
2 changed files with 49 additions and 6 deletions
+17 -2
View File
@@ -28,7 +28,7 @@ DEF_SEM(DoVZEROUPPER) {
return memory;
}
template <typename D, typename S1, size_t KL, size_t VL>
template <typename D, typename S1>
DEF_SEM(VPBROADCASTB, D dst, S1 src1) {
auto src_vec = UReadV8(src1);
auto dst_vec = UClearV8(UReadV8(dst));
@@ -42,6 +42,20 @@ DEF_SEM(VPBROADCASTB, D dst, S1 src1) {
return memory;
}
template <typename D, typename S1>
DEF_SEM(VPBROADCASTQ, D dst, S1 src1) {
auto src_vec = UReadV64(src1);
auto dst_vec = UClearV64(UReadV64(dst));
auto num_groups = NumVectorElems(dst_vec);
auto src_val = UExtractV64(src_vec, 0);
for (std::size_t i = 0; i < num_groups; ++i) {
dst_vec = UInsertV64(dst_vec, i, src_val);
}
UWriteV64(dst, dst_vec);
return memory;
}
template <typename S2>
DEF_SEM(VINSERTF128, VV256W dst, V256 src1, S2 src2, I8 src3) {
auto dst_vec = UReadV128(src1);
@@ -70,6 +84,7 @@ DEF_ISEL(VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb) = VINSERTF128<MV128>;
DEF_ISEL(VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb) = VINSERTF128<V128>;
DEF_ISEL(VZEROUPPER) = DoVZEROUPPER;
DEF_ISEL(VPBROADCASTB_YMMqq_XMMb) = VPBROADCASTB<VV256W, V128, 32, 256>;
DEF_ISEL(VPBROADCASTB_YMMqq_XMMb) = VPBROADCASTB<VV256W, V128>;
DEF_ISEL(VPBROADCASTQ_YMMqq_XMMq) = VPBROADCASTQ<VV256W, V128>;
#endif // HAS_FEATURE_AVX
+32 -4
View File
@@ -183,16 +183,14 @@ DEF_ISEL(PUNPCKLDQ_XMMdq_XMMq) = PUNPCKLDQ<V128W, V128, V128>;
DEF_ISEL(PUNPCKLQDQ_XMMdq_MEMdq) = PUNPCKLQDQ<V128W, V128, MV128>;
DEF_ISEL(PUNPCKLQDQ_XMMdq_XMMq) = PUNPCKLQDQ<V128W, V128, V128>;
IF_AVX(DEF_ISEL(VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq) = PUNPCKLQDQ<V128W, V128, V128>;)
// Adding new MMX Instructions
namespace {
template <typename D, typename S1, typename S2>
DEF_SEM(PADDB, D dst, S1 src1, S2 src2) {
auto lhs_vec = UReadV8(src1);
auto rhs_vec = UReadV8(src2);
auto dst_vec = UAddV8(lhs_vec, rhs_vec);
UWriteV8(dst, dst_vec);
UWriteV8(dst, UAddV8(UReadV8(src1), UReadV8(src2)));
return memory;
}
@@ -230,6 +228,8 @@ DEF_ISEL(PADDB_MMXq_MEMq) = PADDB<V64W, V64, MV64>;
DEF_ISEL(PADDB_XMMdq_XMMdq) = PADDB<V128W, V128, V128>;
DEF_ISEL(PADDB_XMMdq_MEMdq) = PADDB<V128W, V128, MV128>;
IF_AVX(DEF_ISEL(VPADDB_YMMqq_YMMqq_YMMqq) = PADDB<VV256W, VV256, VV256>;)
DEF_ISEL(PADDW_MMXq_MMXq) = PADDW<V64W, V64, V64>;
DEF_ISEL(PADDW_MMXq_MEMq) = PADDW<V64W, V64, MV64>;
DEF_ISEL(PADDW_XMMdq_XMMdq) = PADDW<V128W, V128, V128>;
@@ -240,6 +240,8 @@ DEF_ISEL(PADDD_MMXq_MEMq) = PADDD<V64W, V64, MV64>;
DEF_ISEL(PADDD_XMMdq_XMMdq) = PADDD<V128W, V128, V128>;
DEF_ISEL(PADDD_XMMdq_MEMdq) = PADDD<V128W, V128, MV128>;
IF_AVX(DEF_ISEL(VPADDD_YMMqq_YMMqq_YMMqq) = PADDD<VV256W, VV256, VV256>;)
DEF_ISEL(PADDQ_MMXq_MMXq) = PADDQ<V64W, V64, V64>;
DEF_ISEL(PADDQ_MMXq_MEMq) = PADDQ<V64W, V64, MV64>;
DEF_ISEL(PADDQ_XMMdq_XMMdq) = PADDQ<V128W, V128, V128>;
@@ -438,6 +440,8 @@ DEF_ISEL(PHADDD_MMXq_MEMq) = PHADDD<V64W, V64, MV64>;
DEF_ISEL(PHADDD_XMMdq_XMMdq) = PHADDD<V128W, V128, V128>;
DEF_ISEL(PHADDD_XMMdq_MEMdq) = PHADDD<V128W, V128, MV128>;
IF_AVX(DEF_ISEL(VPHADDD_YMMqq_YMMqq_YMMqq) = PHADDD<VV256W, VV256, VV256>;)
template <typename D, typename S1, typename S2>
DEF_SEM(PHADDSW, D dst, S1 src1, S2 src2) {
auto src1_vec = SReadV16(src1);
@@ -530,6 +534,7 @@ DEF_ISEL(PSUBB_MMXq_MMXq) = PSUBB<V64W, V64, V64>;
DEF_ISEL(PSUBB_MMXq_MEMq) = PSUBB<V64W, V64, MV64>;
DEF_ISEL(PSUBB_XMMdq_XMMdq) = PSUBB<V128W, V128, V128>;
DEF_ISEL(PSUBB_XMMdq_MEMdq) = PSUBB<V128W, V128, MV128>;
IF_AVX(DEF_ISEL(VPSUBB_YMMqq_YMMqq_YMMqq) = PSUBB<VV256W, VV256, VV256>;)
DEF_ISEL(PSUBW_MMXq_MMXq) = PSUBW<V64W, V64, V64>;
DEF_ISEL(PSUBW_MMXq_MEMq) = PSUBW<V64W, V64, MV64>;
@@ -542,6 +547,7 @@ DEF_ISEL(PSUBD_XMMdq_XMMdq) = PSUBD<V128W, V128, V128>;
DEF_ISEL(PSUBD_XMMdq_MEMdq) = PSUBD<V128W, V128, MV128>;
IF_AVX(DEF_ISEL(VPSUBD_XMMdq_XMMdq_MEMdq) = PSUBD<VV128W, V128, MV128>;)
IF_AVX(DEF_ISEL(VPSUBD_XMMdq_XMMdq_XMMdq) = PSUBD<VV128W, V128, V128>;)
IF_AVX(DEF_ISEL(VPSUBD_YMMqq_YMMqq_YMMqq) = PSUBD<VV256W, VV256, VV256>;)
DEF_ISEL(PSUBQ_MMXq_MMXq) = PSUBQ<V64W, V64, V64>;
DEF_ISEL(PSUBQ_MMXq_MEMq) = PSUBQ<V64W, V64, MV64>;
@@ -549,6 +555,7 @@ DEF_ISEL(PSUBQ_XMMdq_XMMdq) = PSUBQ<V128W, V128, V128>;
DEF_ISEL(PSUBQ_XMMdq_MEMdq) = PSUBQ<V128W, V128, MV128>;
IF_AVX(DEF_ISEL(VPSUBQ_XMMdq_XMMdq_MEMdq) = PSUBQ<VV128W, V128, MV128>;)
IF_AVX(DEF_ISEL(VPSUBQ_XMMdq_XMMdq_XMMdq) = PSUBQ<VV128W, V128, V128>;)
IF_AVX(DEF_ISEL(VPSUBQ_YMMqq_YMMqq_YMMqq) = PSUBQ<VV256W, VV256, VV256>;)
/*
3305 VPSUBD VPSUBD_YMMqq_YMMqq_MEMqq AVX2 AVX2 AVX2 ATTRIBUTES:
@@ -1760,6 +1767,23 @@ DEF_SEM(PMULUDQ, D dst, S1 src1, S2 src2) {
return memory;
}
template <typename D, typename S1, typename S2>
DEF_SEM(PMULLD, D dst, S1 src1, S2 src2) {
auto src1_vec = SReadV32(src1);
auto src2_vec = SReadV32(src2);
auto dst_vec = SClearV32(SReadV32(dst));
auto vec_count = NumVectorElems(src1_vec);
_Pragma("unroll") for (size_t i = 0; i < vec_count; i++) {
auto v1 = SExtractV32(src1_vec, i);
auto v2 = SExtractV32(src2_vec, i);
auto mul = SMul(SExt(v1), SExt(v2));
dst_vec = SInsertV32(dst_vec, i, Trunc(mul));
}
SWriteV32(dst, dst_vec);
return memory;
}
template <typename D, typename S1, typename S2>
DEF_SEM(PMULLW, D dst, S1 src1, S2 src2) {
auto src1_vec = SReadV16(src1);
@@ -1817,11 +1841,15 @@ DEF_ISEL(PMULUDQ_MMXq_MMXq) = PMULUDQ<V64W, V64, V64>;
DEF_ISEL(PMULUDQ_MMXq_MEMq) = PMULUDQ<V64W, V64, MV64>;
DEF_ISEL(PMULUDQ_XMMdq_XMMdq) = PMULUDQ<V128W, V128, V128>;
DEF_ISEL(PMULUDQ_XMMdq_MEMdq) = PMULUDQ<V128W, V128, MV128>;
IF_AVX(DEF_ISEL(VPMULUDQ_YMMqq_YMMqq_YMMqq) = PMULUDQ<VV256W, VV256, VV256>;)
IF_AVX(DEF_ISEL(VPMULLD_YMMqq_YMMqq_YMMqq) = PMULLD<VV256W, VV256, VV256>;)
DEF_ISEL(PMULLW_MMXq_MMXq) = PMULLW<V64W, V64, V64>;
DEF_ISEL(PMULLW_MMXq_MEMq) = PMULLW<V64W, V64, MV64>;
DEF_ISEL(PMULLW_XMMdq_XMMdq) = PMULLW<V128W, V128, V128>;
DEF_ISEL(PMULLW_XMMdq_MEMdq) = PMULLW<V128W, V128, MV128>;
IF_AVX(DEF_ISEL(VPMULLW_YMMqq_YMMqq_YMMqq) = PMULLW<VV256W, VV256, VV256>;)
DEF_ISEL(PMULHW_MMXq_MMXq) = PMULHW<V64W, V64, V64>;
DEF_ISEL(PMULHW_MMXq_MEMq) = PMULHW<V64W, V64, MV64>;