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https://github.com/lifting-bits/remill
synced 2026-06-21 13:56:07 +00:00
Added (v)addsub instructons
This commit is contained in:
Petra Peuker
committed by
Kyle Elliott
Kyle Elliott
parent
d52517c7a1
commit
b9d4267ce8
@@ -2160,7 +2160,6 @@ MAKE_PMOVSXx(V, DQ, 32, 64, int64_t, 4);
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} // namespace
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DEF_ISEL(PMOVSXBW_XMMdq_MEMq) = PMOVSXBW<V128W, MV64>;
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DEF_ISEL(PMOVSXBW_XMMdq_XMMq) = PMOVSXBW<V128W, V128>;
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IF_AVX(DEF_ISEL(VPMOVSXBW_XMMdq_XMMq) = PMOVSXBW<VV128W, V128>;)
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@@ -2168,7 +2167,6 @@ IF_AVX(DEF_ISEL(VPMOVSXBW_XMMdq_MEMq) = PMOVSXBW<VV128W, MV64>;)
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IF_AVX(DEF_ISEL(VPMOVSXBW_YMMqq_XMMdq) = VPMOVSXBW<VV256W, V256>;)
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IF_AVX(DEF_ISEL(VPMOVSXBW_YMMqq_MEMdq) = VPMOVSXBW<VV256W, MV128>;)
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DEF_ISEL(PMOVSXBD_XMMdq_MEMd) = PMOVSXBD<V128W, MV32>;
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DEF_ISEL(PMOVSXBD_XMMdq_XMMd) = PMOVSXBD<V128W, V128>;
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IF_AVX(DEF_ISEL(VPMOVSXBD_XMMdq_XMMd) = PMOVSXBD<VV128W, V128>;)
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@@ -2190,7 +2188,6 @@ IF_AVX(DEF_ISEL(VPMOVSXWD_XMMdq_MEMq) = PMOVSXWD<VV128W, MV64>;)
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IF_AVX(DEF_ISEL(VPMOVSXWD_YMMqq_XMMdq) = VPMOVSXWD<VV256W, V256>;)
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IF_AVX(DEF_ISEL(VPMOVSXWD_YMMqq_MEMdq) = VPMOVSXWD<VV256W, MV128>;)
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DEF_ISEL(PMOVSXWQ_XMMdq_MEMd) = PMOVSXWQ<V128W, MV32>;
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DEF_ISEL(PMOVSXWQ_XMMdq_XMMd) = PMOVSXWQ<V128W, V128>;
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IF_AVX(DEF_ISEL(VPMOVSXWQ_XMMdq_XMMd) = PMOVSXWQ<VV128W, V128>;)
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@@ -2241,7 +2238,6 @@ MAKE_PMOVZXx(V, DQ, 32, 64, int64_t, 4);
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} // namespace
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DEF_ISEL(PMOVZXBW_XMMdq_MEMq) = PMOVZXBW<V128W, MV64>;
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DEF_ISEL(PMOVZXBW_XMMdq_XMMq) = PMOVZXBW<V128W, V128>;
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IF_AVX(DEF_ISEL(VPMOVZXBW_XMMdq_XMMq) = PMOVZXBW<VV128W, V128>;)
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@@ -2249,7 +2245,6 @@ IF_AVX(DEF_ISEL(VPMOVZXBW_XMMdq_MEMq) = PMOVZXBW<VV128W, MV64>;)
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IF_AVX(DEF_ISEL(VPMOVZXBW_YMMqq_XMMdq) = VPMOVZXBW<VV256W, V256>;)
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IF_AVX(DEF_ISEL(VPMOVZXBW_YMMqq_MEMdq) = VPMOVZXBW<VV256W, MV128>;)
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DEF_ISEL(PMOVZXBD_XMMdq_MEMd) = PMOVZXBD<V128W, MV32>;
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DEF_ISEL(PMOVZXBD_XMMdq_XMMd) = PMOVZXBD<V128W, V128>;
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IF_AVX(DEF_ISEL(VPMOVZXBD_XMMdq_XMMd) = PMOVZXBD<VV128W, V128>;)
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@@ -2271,7 +2266,6 @@ IF_AVX(DEF_ISEL(VPMOVZXWD_XMMdq_MEMq) = PMOVZXWD<VV128W, MV64>;)
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IF_AVX(DEF_ISEL(VPMOVZXWD_YMMqq_XMMdq) = VPMOVZXWD<VV256W, V256>;)
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IF_AVX(DEF_ISEL(VPMOVZXWD_YMMqq_MEMdq) = VPMOVZXWD<VV256W, MV128>;)
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DEF_ISEL(PMOVZXWQ_XMMdq_MEMd) = PMOVZXWQ<V128W, MV32>;
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DEF_ISEL(PMOVZXWQ_XMMdq_XMMd) = PMOVZXWQ<V128W, V128>;
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IF_AVX(DEF_ISEL(VPMOVZXWQ_XMMdq_XMMd) = PMOVZXWQ<VV128W, V128>;)
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@@ -2284,4 +2278,45 @@ DEF_ISEL(PMOVZXDQ_XMMdq_XMMq) = PMOVZXDQ<V128W, V128>;
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IF_AVX(DEF_ISEL(VPMOVZXDQ_XMMdq_XMMq) = PMOVZXDQ<VV128W, V128>;)
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IF_AVX(DEF_ISEL(VPMOVZXDQ_XMMdq_MEMq) = PMOVZXDQ<VV128W, MV64>;)
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IF_AVX(DEF_ISEL(VPMOVZXDQ_YMMqq_XMMdq) = VPMOVZXDQ<VV256W, V256>;)
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IF_AVX(DEF_ISEL(VPMOVZXDQ_YMMqq_MEMdq) = VPMOVZXDQ<VV256W, MV128>;)
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IF_AVX(DEF_ISEL(VPMOVZXDQ_YMMqq_MEMdq) = VPMOVZXDQ<VV256W, MV128>;)
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namespace {
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#define MAKE_ADDSUBx(suffix, element_width) \
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template <typename D, typename S1, typename S2> \
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DEF_SEM(ADDSUB##suffix, D dst, S1 src1, S2 src2) { \
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auto src1_vec = FReadV##element_width(src1); \
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auto src2_vec = FReadV##element_width(src2); \
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auto dst_vec = FClearV##element_width(FReadV##element_width(dst)); \
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\
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auto num_elements = NumVectorElems(src1_vec); \
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\
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_Pragma("unroll") for (auto idx = 0u; idx < num_elements; ++idx) { \
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auto src1_val = FExtractV##element_width(src1_vec, idx); \
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auto src2_val = FExtractV##element_width(src2_vec, idx); \
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auto op_val = \
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Select(idx % 2, FAdd(src1_val, src2_val), FSub(src1_val, src2_val)); \
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dst_vec = FInsertV##element_width(dst_vec, idx, op_val); \
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} \
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FWriteV##element_width(dst, dst_vec); \
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return memory; \
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}
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MAKE_ADDSUBx(PS, 32) MAKE_ADDSUBx(PD, 64)
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#undef MAKE_ADDSUBx
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} // namespace
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DEF_ISEL(ADDSUBPS_XMMps_MEMps) = ADDSUBPS<V128W, V128, MV128>;
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DEF_ISEL(ADDSUBPS_XMMps_XMMps) = ADDSUBPS<V128W, V128, V128>;
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IF_AVX(DEF_ISEL(VADDSUBPS_XMMdq_XMMdq_MEMdq) = ADDSUBPS<VV128W, V128, MV128>;)
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IF_AVX(DEF_ISEL(VADDSUBPS_XMMdq_XMMdq_XMMdq) = ADDSUBPS<VV128W, V128, V128>;)
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IF_AVX(DEF_ISEL(VADDSUBPS_YMMqq_YMMqq_MEMqq) = ADDSUBPS<VV256W, V256, MV256>;)
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IF_AVX(DEF_ISEL(VADDSUBPS_YMMqq_YMMqq_YMMqq) = ADDSUBPS<VV256W, V256, V128>;)
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DEF_ISEL(ADDSUBPD_XMMpd_MEMpd) = ADDSUBPD<V128W, V128, MV128>;
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DEF_ISEL(ADDSUBPD_XMMpd_XMMpd) = ADDSUBPD<V128W, V128, V128>;
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IF_AVX(DEF_ISEL(VADDSUBPD_XMMdq_XMMdq_MEMdq) = ADDSUBPD<VV128W, V128, MV128>;)
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IF_AVX(DEF_ISEL(VADDSUBPD_XMMdq_XMMdq_XMMdq) = ADDSUBPD<VV128W, V128, V128>;)
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IF_AVX(DEF_ISEL(VADDSUBPD_YMMqq_YMMqq_MEMqq) = ADDSUBPD<VV256W, V256, MV256>;)
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IF_AVX(DEF_ISEL(VADDSUBPD_YMMqq_YMMqq_YMMqq) = ADDSUBPD<VV256W, V256, V128>;)
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@@ -0,0 +1,170 @@
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/*
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* Copyright (c) 2017 Trail of Bits, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#define TEST_INPUT_ADDSUB \
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0.0, 0.0, \
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0.0, 100000.5, \
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100000.5, 100000.5
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TEST_BEGIN_64(ADDSUBPSv128v128, 2)
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TEST_INPUTS(TEST_INPUT_ADDSUB)
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push ARG1_64
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push ARG1_64
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movupd xmm1, [rsp]
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push ARG2_64
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push ARG2_64
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movupd xmm2, [rsp]
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addsubps xmm2, xmm1
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TEST_END_64
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TEST_BEGIN_64(ADDSUBPSv128m128, 2)
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TEST_INPUTS(TEST_INPUT_ADDSUB)
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push ARG1_64
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push ARG1_64
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movupd xmm1, [rsp]
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push ARG2_64
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push ARG2_64
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addsubps xmm2, [rsp]
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TEST_END_64
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#if HAS_FEATURE_AVX
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TEST_BEGIN_64(VADDSUBPSv128v128v128, 2)
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TEST_INPUTS(TEST_INPUT_ADDSUB)
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push ARG1_64
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push ARG1_64
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movupd xmm1, [rsp]
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push ARG2_64
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push ARG2_64
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movupd xmm2, [rsp]
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vaddsubps xmm0, xmm2, xmm1
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TEST_END_64
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TEST_BEGIN_64(VADDSUBPSv128v128m128, 2)
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TEST_INPUTS(TEST_INPUT_ADDSUB)
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push ARG1_64
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push ARG1_64
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movupd xmm1, [rsp]
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push ARG2_64
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push ARG2_64
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vaddsubps xmm0, xmm2, [rsp]
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TEST_END_64
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TEST_BEGIN_64(VADDSUBPSv256v256v256, 2)
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TEST_INPUTS(TEST_INPUT_ADDSUB)
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push ARG1_64
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push 0
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push 0
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push ARG1_64
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vmovupd xmm1, [rsp]
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push ARG2_64
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push ARG2_64
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push ARG2_64
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push ARG2_64
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vmovupd xmm2, [rsp]
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vaddsubps xmm0, xmm2, xmm1
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TEST_END_64
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TEST_BEGIN_64(VADDSUBPSv256v256m256, 2)
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TEST_INPUTS(TEST_INPUT_ADDSUB)
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push ARG1_64
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push 0
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push 0
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push ARG1_64
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vmovupd xmm1, [rsp]
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push ARG2_64
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push 0
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push 0
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push ARG2_64
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vaddsubps xmm0, xmm2, [rsp]
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TEST_END_64
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#endif // HAS_FEATURE_AVX
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TEST_BEGIN_64(ADDSUBPDv128v128, 2)
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TEST_INPUTS(TEST_INPUT_ADDSUB)
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push ARG1_64
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push ARG1_64
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movupd xmm1, [rsp]
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push ARG2_64
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push ARG2_64
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movupd xmm2, [rsp]
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addsubps xmm2, xmm1
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TEST_END_64
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TEST_BEGIN_64(ADDSUBPDv128m128, 2)
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TEST_INPUTS(TEST_INPUT_ADDSUB)
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push ARG1_64
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push ARG1_64
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movupd xmm1, [rsp]
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push ARG2_64
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push ARG2_64
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addsubps xmm2, [rsp]
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TEST_END_64
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#if HAS_FEATURE_AVX
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TEST_BEGIN_64(VADDSUBPDv128v128v128, 2)
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TEST_INPUTS(TEST_INPUT_ADDSUB)
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push ARG1_64
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push ARG1_64
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movupd xmm1, [rsp]
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push ARG2_64
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push ARG2_64
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movupd xmm2, [rsp]
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vaddsubpd xmm0, xmm2, xmm1
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TEST_END_64
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TEST_BEGIN_64(VADDSUBPDv128v128m128, 2)
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TEST_INPUTS(TEST_INPUT_ADDSUB)
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push ARG1_64
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push ARG1_64
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movupd xmm1, [rsp]
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push ARG2_64
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push ARG2_64
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vaddsubpd xmm0, xmm2, [rsp]
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TEST_END_64
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TEST_BEGIN_64(VADDSUBPDv256v256v256, 2)
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TEST_INPUTS(TEST_INPUT_ADDSUB)
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push ARG1_64
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push 0
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push 0
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push ARG1_64
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vmovupd xmm1, [rsp]
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push ARG2_64
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push ARG2_64
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push ARG2_64
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push ARG2_64
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vmovupd xmm2, [rsp]
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vaddsubpd xmm0, xmm2, xmm1
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TEST_END_64
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TEST_BEGIN_64(VADDSUBPDv256v256m256, 2)
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TEST_INPUTS(TEST_INPUT_ADDSUB)
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push ARG1_64
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push 0
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push 0
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push ARG1_64
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vmovupd xmm1, [rsp]
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push ARG2_64
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push 0
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push 0
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push ARG2_64
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vaddsubpd xmm0, xmm2, [rsp]
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TEST_END_64
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#endif // HAS_FEATURE_AVX
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@@ -504,6 +504,7 @@ SYMBOL(__x86_test_table_begin):
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#include "tests/X86/SHIFT/SHR.S"
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#include "tests/X86/SHIFT/SHRD.S"
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#include "tests/X86/SSE/ADDSUB.S"
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#include "tests/X86/SSE/CMPSS.S"
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#include "tests/X86/SSE/COMISD.S"
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#include "tests/X86/SSE/COMISS.S"
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