admin/lifting-bits-remill
1
0
Fork 0
mirror of https://github.com/lifting-bits/remill synced 2026-06-21 13:56:07 +00:00
Code Issues Packages Projects Releases Wiki Activity

Wip aarch64 /bin/ls and libc instructions (#138)

Browse Source 
* ADDS and Various COND Instructions (squashed)

Set proper compoistion for <bit_pos> to be b5:b40

The bit_pos value is a concatenation of the
b5 width bit as well as the b40 bits

Trailing new line

Minor syntax fixes for TBNZ test files

[WIP] CLZ instr and started COND select instructions

Added ADDS instruction

CSEL and CINC variant, still failing to build test isel lifting error

Added semantics to Instructions.cpp

There is a bug with 64 bit CSEL only with one of the select registers
being overwritten after the test ends (x3)

Lifted:
 x3 = {{dword = 0x8, qword = 0x8}}

Native:
 x3 = {{dword = 0xdead, qword = 0xdead}}

Fixed issue with CSINC aliases getting overridden

Bug with x3 registers still here...
Extract.cpp autogenerated function does not check for the
CINC alias that Rn == Rm, therefore all csinc functions
where being shadowed incorrectly

inverse(cond) fix for CINC and test in state to show bug

kRegValue fixes, moved inverse conditional bit logic

Changed the inverse conditional bit change from extraction
to be applied non-destructively in decode logic for conditional register
select that uses it. Fixed mismatch between register values using
kUseAsValue vs kUseAsAddress. Various refactor changes.

Format cleanup

Fixes incorrect register init bug in BasicBlock x3 register

Added CSET alias

Added CSINV family and aliases

WIP CCMP trying to figure out flag conditions

* Fix redefinition of BITBYTE, fix aliased CSINC tests later

* CNEG Ins, aliases fixed

* Fix ADDS double defined
This commit is contained in:
Chris Evans
2017-09-25 17:24:22 -04:00
committed by Peter Goodman
parent f42923d108
commit d38e16867c
16 changed files with 860 additions and 766 deletions
Download Patch File Download Diff File Expand all files Collapse all files
remill/Arch/AArch64/Arch.cpp
+186 -4
View File
@@ -1460,14 +1460,17 @@ static const char *CondName(uint8_t cond) {
}
}
void SetConditionalFunctionName(uint8_t cond, Instruction &inst) {
std::stringstream ss;
ss << inst.function << "_" << CondName(cond);
inst.function = ss.str();
}
// B.<cond> <label>
bool TryDecodeB_ONLY_CONDBRANCH(const InstData &data, Instruction &inst) {
// Add in the condition to the isel name.
std::stringstream ss;
ss << inst.function << "_" << CondName(data.cond);
inst.function = ss.str();
SetConditionalFunctionName(data.cond, inst);
DecodeConditionalBranch(inst, data.imm19.simm19 << 2);
return true;
}
@@ -2096,6 +2099,185 @@ bool TryDecodeLDR_Q_LDST_POS(const InstData &data, Instruction &inst) {
}
// CLZ <Wd>, <Wn>
bool TryDecodeCLZ_32_DP_1SRC(const InstData &data, Instruction &inst) {
AddRegOperand(inst, kActionWrite, kRegW, kUseAsValue, data.Rd);
AddRegOperand(inst, kActionRead, kRegW, kUseAsValue, data.Rn);
return true;
}
// CLZ <Xd>, <Xn>
bool TryDecodeCLZ_64_DP_1SRC(const InstData &data, Instruction &inst) {
AddRegOperand(inst, kActionWrite, kRegX, kUseAsValue, data.Rd);
AddRegOperand(inst, kActionRead, kRegX, kUseAsValue, data.Rn);
return true;
}
bool DecodeConditionalRegSelect(
const InstData &data,
Instruction &inst,
RegClass r_class,
int8_t n_regs, // signed because otherwise we underflow
bool invert_cond = false
) {
if (!(1 <= n_regs && n_regs <= 3)) {
LOG(ERROR) << "Number of registers in conditional select must be 1 <= x <= 3";
return false;
}
AddRegOperand(inst, kActionWrite, r_class, kUseAsValue, data.Rd);
if (--n_regs > 0) {
AddRegOperand(inst, kActionRead, r_class, kUseAsValue, data.Rn);
}
if (--n_regs > 0) {
AddRegOperand(inst, kActionRead, r_class, kUseAsValue, data.Rm);
}
uint8_t cond;
if (invert_cond) {
cond = data.cond ^ 1;
} else {
cond = data.cond;
}
// Condition will be part of the isel, not an operand
SetConditionalFunctionName(cond, inst);
return true;
}
// CSEL <Wd>, <Wn>, <Wm>, <cond>
bool TryDecodeCSEL_32_CONDSEL(const InstData &data, Instruction &inst) {
return DecodeConditionalRegSelect(data, inst, kRegW, 3);
}
// CSEL <Xd>, <Xn>, <Xm>, <cond>
bool TryDecodeCSEL_64_CONDSEL(const InstData &data, Instruction &inst) {
return DecodeConditionalRegSelect(data, inst, kRegX, 3);
}
// CSINC <Wd>, <Wn>, <Wm>, <cond>
bool TryDecodeCSINC_32_CONDSEL(const InstData &data, Instruction &inst) {
return DecodeConditionalRegSelect(data, inst, kRegW, 3);
}
// CSINC <Xd>, <Xn>, <Xm>, <cond>
bool TryDecodeCSINC_64_CONDSEL(const InstData &data, Instruction &inst) {
return DecodeConditionalRegSelect(data, inst, kRegX, 3);
}
//////////////////////// DEPRICATED ALIAS
// CINC <Wd>, <Wn>, <cond>
bool TryDecodeCINC_CSINC_32_CONDSEL(const InstData &data, Instruction &inst) {
return false;
}
// CINC <Xd>, <Xn>, <cond>
bool TryDecodeCINC_CSINC_64_CONDSEL(const InstData &data, Instruction &inst) {
return false;
}
// CSET <Wd>, <cond>
bool TryDecodeCSET_CSINC_32_CONDSEL(const InstData &data, Instruction &inst) {
return false;
}
// CSET <Xd>, <cond>
bool TryDecodeCSET_CSINC_64_CONDSEL(const InstData &data, Instruction &inst) {
return false;
}
//////////////////////////////////////////
// CSINV <Wd>, <Wn>, <Wm>, <cond>
bool TryDecodeCSINV_32_CONDSEL(const InstData &data, Instruction &inst) {
return DecodeConditionalRegSelect(data, inst, kRegW, 3);
}
// CSINV <Xd>, <Xn>, <Xm>, <cond>
bool TryDecodeCSINV_64_CONDSEL(const InstData &data, Instruction &inst) {
return DecodeConditionalRegSelect(data, inst, kRegX, 3);
}
///////////////// DEPRICATED ALIAS
// CINV <Wd>, <Wn>, <cond>
bool TryDecodeCINV_CSINV_32_CONDSEL(const InstData &data, Instruction &inst) {
return false;
}
// CINV <Xd>, <Xn>, <cond>
bool TryDecodeCINV_CSINV_64_CONDSEL(const InstData &data, Instruction &inst) {
return false;
}
// CSETM <Wd>, <cond>
bool TryDecodeCSETM_CSINV_32_CONDSEL(const InstData &data, Instruction &inst) {
return false;
}
// CSETM <Xd>, <cond>
bool TryDecodeCSETM_CSINV_64_CONDSEL(const InstData &data, Instruction &inst) {
return false;
}
///////////////////////////////////
// CSNEG <Wd>, <Wn>, <Wm>, <cond>
bool TryDecodeCSNEG_32_CONDSEL(const InstData &data, Instruction &inst) {
return DecodeConditionalRegSelect(data, inst, kRegW, 3);
}
// CSNEG <Xd>, <Xn>, <Xm>, <cond>
bool TryDecodeCSNEG_64_CONDSEL(const InstData &data, Instruction &inst) {
return DecodeConditionalRegSelect(data, inst, kRegX, 3);
}
// CCMP <Wn>, #<imm>, #<nzcv>, <cond>
bool TryDecodeCCMP_32_CONDCMP_IMM(const InstData &data, Instruction &inst) {
DecodeConditionalRegSelect(data, inst, kRegW, 1);
AddImmOperand(inst, data.imm5.uimm);
AddImmOperand(inst, data.nzcv);
return true;
}
// CCMP CCMP_64_condcmp_imm:
// 0 x nzcv 0
// 1 x nzcv 1
// 2 x nzcv 2
// 3 x nzcv 3
// 4 0 o3 0
// 5 x Rn 0
// 6 x Rn 1
// 7 x Rn 2
// 8 x Rn 3
// 9 x Rn 4
// 10 0 o2 0
// 11 1
// 12 x cond 0
// 13 x cond 1
// 14 x cond 2
// 15 x cond 3
// 16 x imm5 0
// 17 x imm5 1
// 18 x imm5 2
// 19 x imm5 3
// 20 x imm5 4
// 21 0
// 22 1
// 23 0
// 24 0
// 25 1
// 26 0
// 27 1
// 28 1
// 29 1 S 0
// 30 1 op 0
// 31 1 sf 0
// CCMP <Xn>, #<imm>, #<nzcv>, <cond>
bool TryDecodeCCMP_64_CONDCMP_IMM(const InstData &, Instruction &) {
return false;
}
} // namespace aarch64
// TODO(pag): We pretend that these are singletons, but they aren't really!
remill/Arch/AArch64/Decode.cpp
-759
View File
@@ -1173,81 +1173,6 @@ bool TryDecodeLDUR_Q_LDST_UNSCALED(const InstData &, Instruction &) {
return false;
}
// CLZ CLZ_32_dp_1src:
// 0 x Rd 0
// 1 x Rd 1
// 2 x Rd 2
// 3 x Rd 3
// 4 x Rd 4
// 5 x Rn 0
// 6 x Rn 1
// 7 x Rn 2
// 8 x Rn 3
// 9 x Rn 4
// 10 0 op 0
// 11 0 opcode 1
// 12 1 opcode 2
// 13 0 opcode 3
// 14 0 opcode 4
// 15 0 opcode 5
// 16 0 opcode2 0
// 17 0 opcode2 1
// 18 0 opcode2 2
// 19 0 opcode2 3
// 20 0 opcode2 4
// 21 0
// 22 1
// 23 1
// 24 0
// 25 1
// 26 0
// 27 1
// 28 1
// 29 0 S 0
// 30 1
// 31 0 sf 0
// CLZ <Wd>, <Wn>
bool TryDecodeCLZ_32_DP_1SRC(const InstData &, Instruction &) {
return false;
}
// CLZ CLZ_64_dp_1src:
// 0 x Rd 0
// 1 x Rd 1
// 2 x Rd 2
// 3 x Rd 3
// 4 x Rd 4
// 5 x Rn 0
// 6 x Rn 1
// 7 x Rn 2
// 8 x Rn 3
// 9 x Rn 4
// 10 0 op 0
// 11 0 opcode 1
// 12 1 opcode 2
// 13 0 opcode 3
// 14 0 opcode 4
// 15 0 opcode 5
// 16 0 opcode2 0
// 17 0 opcode2 1
// 18 0 opcode2 2
// 19 0 opcode2 3
// 20 0 opcode2 4
// 21 0
// 22 1
// 23 1
// 24 0
// 25 1
// 26 0
// 27 1
// 28 1
// 29 0 S 0
// 30 1
// 31 1 sf 0
// CLZ <Xd>, <Xn>
bool TryDecodeCLZ_64_DP_1SRC(const InstData &, Instruction &) {
return false;
}
// LSRV LSR_LSRV_32_dp_2src:
// 0 x Rd 0
@@ -10104,82 +10029,6 @@ bool TryDecodeSQDMULL_ASIMDELEM_L(const InstData &, Instruction &) {
return false;
}
// CSINC CSET_CSINC_32_condsel:
// 0 x Rd 0
// 1 x Rd 1
// 2 x Rd 2
// 3 x Rd 3
// 4 x Rd 4
// 5 1 Rn 0
// 6 1 Rn 1
// 7 1 Rn 2
// 8 1 Rn 3
// 9 1 Rn 4
// 10 1 o2 0
// 11 0
// 12 x cond 0
// 13 x cond 1
// 14 x cond 2
// 15 x cond 3
// 16 1 Rm 0
// 17 1 Rm 1
// 18 1 Rm 2
// 19 1 Rm 3
// 20 1 Rm 4
// 21 0
// 22 0
// 23 1
// 24 0
// 25 1
// 26 0
// 27 1
// 28 1
// 29 0 S 0
// 30 0 op 0
// 31 0 sf 0
// CSET <Wd>, <cond>
bool TryDecodeCSET_CSINC_32_CONDSEL(const InstData &, Instruction &) {
return false;
}
// CSINC CSET_CSINC_64_condsel:
// 0 x Rd 0
// 1 x Rd 1
// 2 x Rd 2
// 3 x Rd 3
// 4 x Rd 4
// 5 1 Rn 0
// 6 1 Rn 1
// 7 1 Rn 2
// 8 1 Rn 3
// 9 1 Rn 4
// 10 1 o2 0
// 11 0
// 12 x cond 0
// 13 x cond 1
// 14 x cond 2
// 15 x cond 3
// 16 1 Rm 0
// 17 1 Rm 1
// 18 1 Rm 2
// 19 1 Rm 3
// 20 1 Rm 4
// 21 0
// 22 0
// 23 1
// 24 0
// 25 1
// 26 0
// 27 1
// 28 1
// 29 0 S 0
// 30 0 op 0
// 31 1 sf 0
// CSET <Xd>, <cond>
bool TryDecodeCSET_CSINC_64_CONDSEL(const InstData &, Instruction &) {
return false;
}
// LD1 LD1_asisdlso_B1_1b:
// 0 x Rt 0
// 1 x Rt 1
@@ -10940,82 +10789,6 @@ bool TryDecodeFSUB_D_FLOATDP2(const InstData &, Instruction &) {
return false;
}
// CSNEG CSNEG_32_condsel:
// 0 x Rd 0
// 1 x Rd 1
// 2 x Rd 2
// 3 x Rd 3
// 4 x Rd 4
// 5 x Rn 0
// 6 x Rn 1
// 7 x Rn 2
// 8 x Rn 3
// 9 x Rn 4
// 10 1 o2 0
// 11 0
// 12 x cond 0
// 13 x cond 1
// 14 x cond 2
// 15 x cond 3
// 16 x Rm 0
// 17 x Rm 1
// 18 x Rm 2
// 19 x Rm 3
// 20 x Rm 4
// 21 0
// 22 0
// 23 1
// 24 0
// 25 1
// 26 0
// 27 1
// 28 1
// 29 0 S 0
// 30 1 op 0
// 31 0 sf 0
// CSNEG <Wd>, <Wn>, <Wm>, <cond>
bool TryDecodeCSNEG_32_CONDSEL(const InstData &, Instruction &) {
return false;
}
// CSNEG CSNEG_64_condsel:
// 0 x Rd 0
// 1 x Rd 1
// 2 x Rd 2
// 3 x Rd 3
// 4 x Rd 4
// 5 x Rn 0
// 6 x Rn 1
// 7 x Rn 2
// 8 x Rn 3
// 9 x Rn 4
// 10 1 o2 0
// 11 0
// 12 x cond 0
// 13 x cond 1
// 14 x cond 2
// 15 x cond 3
// 16 x Rm 0
// 17 x Rm 1
// 18 x Rm 2
// 19 x Rm 3
// 20 x Rm 4
// 21 0
// 22 0
// 23 1
// 24 0
// 25 1
// 26 0
// 27 1
// 28 1
// 29 0 S 0
// 30 1 op 0
// 31 1 sf 0
// CSNEG <Xd>, <Xn>, <Xm>, <cond>
bool TryDecodeCSNEG_64_CONDSEL(const InstData &, Instruction &) {
return false;
}
// ASRV ASR_ASRV_32_dp_2src:
// 0 x Rd 0
// 1 x Rd 1
@@ -26901,82 +26674,6 @@ bool TryDecodeSCVTF_D64_FLOAT2FIX(const InstData &, Instruction &) {
return false;
}
// CSINV CSETM_CSINV_32_condsel:
// 0 x Rd 0
// 1 x Rd 1
// 2 x Rd 2
// 3 x Rd 3
// 4 x Rd 4
// 5 1 Rn 0
// 6 1 Rn 1
// 7 1 Rn 2
// 8 1 Rn 3
// 9 1 Rn 4
// 10 0 o2 0
// 11 0
// 12 x cond 0
// 13 x cond 1
// 14 x cond 2
// 15 x cond 3
// 16 1 Rm 0
// 17 1 Rm 1
// 18 1 Rm 2
// 19 1 Rm 3
// 20 1 Rm 4
// 21 0
// 22 0
// 23 1
// 24 0
// 25 1
// 26 0
// 27 1
// 28 1
// 29 0 S 0
// 30 1 op 0
// 31 0 sf 0
// CSETM <Wd>, <cond>
bool TryDecodeCSETM_CSINV_32_CONDSEL(const InstData &, Instruction &) {
return false;
}
// CSINV CSETM_CSINV_64_condsel:
// 0 x Rd 0
// 1 x Rd 1
// 2 x Rd 2
// 3 x Rd 3
// 4 x Rd 4
// 5 1 Rn 0
// 6 1 Rn 1
// 7 1 Rn 2
// 8 1 Rn 3
// 9 1 Rn 4
// 10 0 o2 0
// 11 0
// 12 x cond 0
// 13 x cond 1
// 14 x cond 2
// 15 x cond 3
// 16 1 Rm 0
// 17 1 Rm 1
// 18 1 Rm 2
// 19 1 Rm 3
// 20 1 Rm 4
// 21 0
// 22 0
// 23 1
// 24 0
// 25 1
// 26 0
// 27 1
// 28 1
// 29 0 S 0
// 30 1 op 0
// 31 1 sf 0
// CSETM <Xd>, <cond>
bool TryDecodeCSETM_CSINV_64_CONDSEL(const InstData &, Instruction &) {
return false;
}
// SQDMLAL SQDMLAL_asisdelem_L:
// 0 x Rd 0
// 1 x Rd 1
@@ -33437,157 +33134,6 @@ bool TryDecodeSQDMLSL_ASIMDELEM_L(const InstData &, Instruction &) {
return false;
}
// CSINC CINC_CSINC_32_condsel:
// 0 x Rd 0
// 1 x Rd 1
// 2 x Rd 2
// 3 x Rd 3
// 4 x Rd 4
// 5 x Rn 0
// 6 x Rn 1
// 7 x Rn 2
// 8 x Rn 3
// 9 x Rn 4
// 10 1 o2 0
// 11 0
// 12 x cond 0
// 13 x cond 1
// 14 x cond 2
// 15 x cond 3
// 16 x Rm 0
// 17 x Rm 1
// 18 x Rm 2
// 19 x Rm 3
// 20 x Rm 4
// 21 0
// 22 0
// 23 1
// 24 0
// 25 1
// 26 0
// 27 1
// 28 1
// 29 0 S 0
// 30 0 op 0
// 31 0 sf 0
// CINC <Wd>, <Wn>, <cond>
bool TryDecodeCINC_CSINC_32_CONDSEL(const InstData &, Instruction &) {
return false;
}
// CSINC CINC_CSINC_64_condsel:
// 0 x Rd 0
// 1 x Rd 1
// 2 x Rd 2
// 3 x Rd 3
// 4 x Rd 4
// 5 x Rn 0
// 6 x Rn 1
// 7 x Rn 2
// 8 x Rn 3
// 9 x Rn 4
// 10 1 o2 0
// 11 0
// 12 x cond 0
// 13 x cond 1
// 14 x cond 2
// 15 x cond 3
// 16 x Rm 0
// 17 x Rm 1
// 18 x Rm 2
// 19 x Rm 3
// 20 x Rm 4
// 21 0
// 22 0
// 23 1
// 24 0
// 25 1
// 26 0
// 27 1
// 28 1
// 29 0 S 0
// 30 0 op 0
// 31 1 sf 0
// CINC <Xd>, <Xn>, <cond>
bool TryDecodeCINC_CSINC_64_CONDSEL(const InstData &, Instruction &) {
return false;
}
// CSINV CSINV_32_condsel:
// 0 x Rd 0
// 1 x Rd 1
// 2 x Rd 2
// 3 x Rd 3
// 4 x Rd 4
// 5 x Rn 0
// 6 x Rn 1
// 7 x Rn 2
// 8 x Rn 3
// 9 x Rn 4
// 10 0 o2 0
// 11 0
// 12 x cond 0
// 13 x cond 1
// 14 x cond 2
// 15 x cond 3
// 16 x Rm 0
// 17 x Rm 1
// 18 x Rm 2
// 19 x Rm 3
// 20 x Rm 4
// 21 0
// 22 0
// 23 1
// 24 0
// 25 1
// 26 0
// 27 1
// 28 1
// 29 0 S 0
// 30 1 op 0
// 31 0 sf 0
// CSINV <Wd>, <Wn>, <Wm>, <cond>
bool TryDecodeCSINV_32_CONDSEL(const InstData &, Instruction &) {
return false;
}
// CSINV CSINV_64_condsel:
// 0 x Rd 0
// 1 x Rd 1
// 2 x Rd 2
// 3 x Rd 3
// 4 x Rd 4
// 5 x Rn 0
// 6 x Rn 1
// 7 x Rn 2
// 8 x Rn 3
// 9 x Rn 4
// 10 0 o2 0
// 11 0
// 12 x cond 0
// 13 x cond 1
// 14 x cond 2
// 15 x cond 3
// 16 x Rm 0
// 17 x Rm 1
// 18 x Rm 2
// 19 x Rm 3
// 20 x Rm 4
// 21 0
// 22 0
// 23 1
// 24 0
// 25 1
// 26 0
// 27 1
// 28 1
// 29 0 S 0
// 30 1 op 0
// 31 1 sf 0
// CSINV <Xd>, <Xn>, <Xm>, <cond>
bool TryDecodeCSINV_64_CONDSEL(const InstData &, Instruction &) {
return false;
}
// FCVTZU FCVTZU_asisdshf_C:
// 0 x Rd 0
@@ -36098,82 +35644,6 @@ bool TryDecodeLDTR_64_LDST_UNPRIV(const InstData &, Instruction &) {
return false;
}
// CCMP CCMP_32_condcmp_imm:
// 0 x nzcv 0
// 1 x nzcv 1
// 2 x nzcv 2
// 3 x nzcv 3
// 4 0 o3 0
// 5 x Rn 0
// 6 x Rn 1
// 7 x Rn 2
// 8 x Rn 3
// 9 x Rn 4
// 10 0 o2 0
// 11 1
// 12 x cond 0
// 13 x cond 1
// 14 x cond 2
// 15 x cond 3
// 16 x imm5 0
// 17 x imm5 1
// 18 x imm5 2
// 19 x imm5 3
// 20 x imm5 4
// 21 0
// 22 1
// 23 0
// 24 0
// 25 1
// 26 0
// 27 1
// 28 1
// 29 1 S 0
// 30 1 op 0
// 31 0 sf 0
// CCMP <Wn>, #<imm>, #<nzcv>, <cond>
bool TryDecodeCCMP_32_CONDCMP_IMM(const InstData &, Instruction &) {
return false;
}
// CCMP CCMP_64_condcmp_imm:
// 0 x nzcv 0
// 1 x nzcv 1
// 2 x nzcv 2
// 3 x nzcv 3
// 4 0 o3 0
// 5 x Rn 0
// 6 x Rn 1
// 7 x Rn 2
// 8 x Rn 3
// 9 x Rn 4
// 10 0 o2 0
// 11 1
// 12 x cond 0
// 13 x cond 1
// 14 x cond 2
// 15 x cond 3
// 16 x imm5 0
// 17 x imm5 1
// 18 x imm5 2
// 19 x imm5 3
// 20 x imm5 4
// 21 0
// 22 1
// 23 0
// 24 0
// 25 1
// 26 0
// 27 1
// 28 1
// 29 1 S 0
// 30 1 op 0
// 31 1 sf 0
// CCMP <Xn>, #<imm>, #<nzcv>, <cond>
bool TryDecodeCCMP_64_CONDCMP_IMM(const InstData &, Instruction &) {
return false;
}
// UZP2 UZP2_asimdperm_only:
// 0 x Rd 0
// 1 x Rd 1
@@ -38492,82 +37962,6 @@ bool TryDecodeFACGE_ASIMDSAME_ONLY(const InstData &, Instruction &) {
return false;
}
// CSEL CSEL_32_condsel:
// 0 x Rd 0
// 1 x Rd 1
// 2 x Rd 2
// 3 x Rd 3
// 4 x Rd 4
// 5 x Rn 0
// 6 x Rn 1
// 7 x Rn 2
// 8 x Rn 3
// 9 x Rn 4
// 10 0 o2 0
// 11 0
// 12 x cond 0
// 13 x cond 1
// 14 x cond 2
// 15 x cond 3
// 16 x Rm 0
// 17 x Rm 1
// 18 x Rm 2
// 19 x Rm 3
// 20 x Rm 4
// 21 0
// 22 0
// 23 1
// 24 0
// 25 1
// 26 0
// 27 1
// 28 1
// 29 0 S 0
// 30 0 op 0
// 31 0 sf 0
// CSEL <Wd>, <Wn>, <Wm>, <cond>
bool TryDecodeCSEL_32_CONDSEL(const InstData &, Instruction &) {
return false;
}
// CSEL CSEL_64_condsel:
// 0 x Rd 0
// 1 x Rd 1
// 2 x Rd 2
// 3 x Rd 3
// 4 x Rd 4
// 5 x Rn 0
// 6 x Rn 1
// 7 x Rn 2
// 8 x Rn 3
// 9 x Rn 4
// 10 0 o2 0
// 11 0
// 12 x cond 0
// 13 x cond 1
// 14 x cond 2
// 15 x cond 3
// 16 x Rm 0
// 17 x Rm 1
// 18 x Rm 2
// 19 x Rm 3
// 20 x Rm 4
// 21 0
// 22 0
// 23 1
// 24 0
// 25 1
// 26 0
// 27 1
// 28 1
// 29 0 S 0
// 30 0 op 0
// 31 1 sf 0
// CSEL <Xd>, <Xn>, <Xm>, <cond>
bool TryDecodeCSEL_64_CONDSEL(const InstData &, Instruction &) {
return false;
}
// FCVTAS FCVTAS_32H_float2int:
// 0 x Rd 0
// 1 x Rd 1
@@ -44990,82 +44384,6 @@ bool TryDecodeFCVTZU_64D_FLOAT2INT(const InstData &, Instruction &) {
return false;
}
// CSINV CINV_CSINV_32_condsel:
// 0 x Rd 0
// 1 x Rd 1
// 2 x Rd 2
// 3 x Rd 3
// 4 x Rd 4
// 5 x Rn 0
// 6 x Rn 1
// 7 x Rn 2
// 8 x Rn 3
// 9 x Rn 4
// 10 0 o2 0
// 11 0
// 12 x cond 0
// 13 x cond 1
// 14 x cond 2
// 15 x cond 3
// 16 x Rm 0
// 17 x Rm 1
// 18 x Rm 2
// 19 x Rm 3
// 20 x Rm 4
// 21 0
// 22 0
// 23 1
// 24 0
// 25 1
// 26 0
// 27 1
// 28 1
// 29 0 S 0
// 30 1 op 0
// 31 0 sf 0
// CINV <Wd>, <Wn>, <cond>
bool TryDecodeCINV_CSINV_32_CONDSEL(const InstData &, Instruction &) {
return false;
}
// CSINV CINV_CSINV_64_condsel:
// 0 x Rd 0
// 1 x Rd 1
// 2 x Rd 2
// 3 x Rd 3
// 4 x Rd 4
// 5 x Rn 0
// 6 x Rn 1
// 7 x Rn 2
// 8 x Rn 3
// 9 x Rn 4
// 10 0 o2 0
// 11 0
// 12 x cond 0
// 13 x cond 1
// 14 x cond 2
// 15 x cond 3
// 16 x Rm 0
// 17 x Rm 1
// 18 x Rm 2
// 19 x Rm 3
// 20 x Rm 4
// 21 0
// 22 0
// 23 1
// 24 0
// 25 1
// 26 0
// 27 1
// 28 1
// 29 0 S 0
// 30 1 op 0
// 31 1 sf 0
// CINV <Xd>, <Xn>, <cond>
bool TryDecodeCINV_CSINV_64_CONDSEL(const InstData &, Instruction &) {
return false;
}
// FDIV FDIV_H_floatdp2:
// 0 x Rd 0
// 1 x Rd 1
@@ -46585,83 +45903,6 @@ bool TryDecodeLD2R_ASISDLSOP_R2_I(const InstData &, Instruction &) {
bool TryDecodeLD2R_ASISDLSOP_RX2_R(const InstData &, Instruction &) {
return false;
}
// CSINC CSINC_32_condsel:
// 0 x Rd 0
// 1 x Rd 1
// 2 x Rd 2
// 3 x Rd 3
// 4 x Rd 4
// 5 x Rn 0
// 6 x Rn 1
// 7 x Rn 2
// 8 x Rn 3
// 9 x Rn 4
// 10 1 o2 0
// 11 0
// 12 x cond 0
// 13 x cond 1
// 14 x cond 2
// 15 x cond 3
// 16 x Rm 0
// 17 x Rm 1
// 18 x Rm 2
// 19 x Rm 3
// 20 x Rm 4
// 21 0
// 22 0
// 23 1
// 24 0
// 25 1
// 26 0
// 27 1
// 28 1
// 29 0 S 0
// 30 0 op 0
// 31 0 sf 0
// CSINC <Wd>, <Wn>, <Wm>, <cond>
bool TryDecodeCSINC_32_CONDSEL(const InstData &, Instruction &) {
return false;
}
// CSINC CSINC_64_condsel:
// 0 x Rd 0
// 1 x Rd 1
// 2 x Rd 2
// 3 x Rd 3
// 4 x Rd 4
// 5 x Rn 0
// 6 x Rn 1
// 7 x Rn 2
// 8 x Rn 3
// 9 x Rn 4
// 10 1 o2 0
// 11 0
// 12 x cond 0
// 13 x cond 1
// 14 x cond 2
// 15 x cond 3
// 16 x Rm 0
// 17 x Rm 1
// 18 x Rm 2
// 19 x Rm 3
// 20 x Rm 4
// 21 0
// 22 0
// 23 1
// 24 0
// 25 1
// 26 0
// 27 1
// 28 1
// 29 0 S 0
// 30 0 op 0
// 31 1 sf 0
// CSINC <Xd>, <Xn>, <Xm>, <cond>
bool TryDecodeCSINC_64_CONDSEL(const InstData &, Instruction &) {
return false;
}
// FMLS FMLS_asisdelem_RH_H:
// 0 x Rd 0
// 1 x Rd 1
remill/Arch/AArch64/Extract.cpp
+26
View File
@@ -15,6 +15,8 @@
*/
#include "remill/Arch/AArch64/Decode.h"
#include <gflags/gflags.h>
#include <glog/logging.h>
namespace remill {
namespace aarch64 {
@@ -17644,6 +17646,8 @@ static bool TryExtractCSET_CSINC_32_CONDSEL(InstData &inst, uint32_t bits) {
if (!(inst.cond != 0xf)) return false;
inst.Rm = static_cast<uint8_t>(enc.Rm);
inst.Rn = static_cast<uint8_t>(enc.Rn);
// Rm and Rn both have to be 0x1f
if (!(inst.Rm == 0x1f && inst.Rn == 0x1f)) return false;
inst.o2 = static_cast<uint8_t>(enc.o2);
inst.op = static_cast<uint8_t>(enc.op);
inst.iform = InstForm::CSET_CSINC_32_CONDSEL;
@@ -17691,6 +17695,8 @@ static bool TryExtractCSET_CSINC_64_CONDSEL(InstData &inst, uint32_t bits) {
if (!(inst.cond != 0xf)) return false;
inst.Rm = static_cast<uint8_t>(enc.Rm);
inst.Rn = static_cast<uint8_t>(enc.Rn);
// Rm and Rn both have to be 0x1f
if (!(inst.Rm == 0x1f && inst.Rn == 0x1f)) return false;
inst.o2 = static_cast<uint8_t>(enc.o2);
inst.op = static_cast<uint8_t>(enc.op);
inst.iform = InstForm::CSET_CSINC_64_CONDSEL;
@@ -39478,6 +39484,8 @@ static bool TryExtractCSETM_CSINV_32_CONDSEL(InstData &inst, uint32_t bits) {
if (!(inst.cond != 0xf)) return false;
inst.Rm = static_cast<uint8_t>(enc.Rm);
inst.Rn = static_cast<uint8_t>(enc.Rn);
// Rm and Rn both have to be 0x1f
if (!(inst.Rm == 0x1f && inst.Rn == 0x1f)) return false;
inst.o2 = static_cast<uint8_t>(enc.o2);
inst.op = static_cast<uint8_t>(enc.op);
inst.iform = InstForm::CSETM_CSINV_32_CONDSEL;
@@ -39525,6 +39533,8 @@ static bool TryExtractCSETM_CSINV_64_CONDSEL(InstData &inst, uint32_t bits) {
if (!(inst.cond != 0xf)) return false;
inst.Rm = static_cast<uint8_t>(enc.Rm);
inst.Rn = static_cast<uint8_t>(enc.Rn);
// Rm and Rn both have to be 0x1f
if (!(inst.Rm == 0x1f && inst.Rn == 0x1f)) return false;
inst.o2 = static_cast<uint8_t>(enc.o2);
inst.op = static_cast<uint8_t>(enc.op);
inst.iform = InstForm::CSETM_CSINV_64_CONDSEL;
@@ -48001,6 +48011,10 @@ static bool TryExtractCINC_CSINC_32_CONDSEL(InstData &inst, uint32_t bits) {
if (!(inst.Rm != 0x1f)) return false;
inst.Rn = static_cast<uint8_t>(enc.Rn);
if (!(inst.Rn != 0x1f)) return false;
// The bitmask check autogenerated does not check
// if the two registers are the same which is important
// otherwise this will shadow all csinc instructions
if (!(inst.Rm == inst.Rn)) return false;
inst.o2 = static_cast<uint8_t>(enc.o2);
inst.op = static_cast<uint8_t>(enc.op);
inst.iform = InstForm::CINC_CSINC_32_CONDSEL;
@@ -48050,6 +48064,10 @@ static bool TryExtractCINC_CSINC_64_CONDSEL(InstData &inst, uint32_t bits) {
if (!(inst.Rm != 0x1f)) return false;
inst.Rn = static_cast<uint8_t>(enc.Rn);
if (!(inst.Rn != 0x1f)) return false;
// The bitmask check autogenerated does not check
// if the two registers are the same which is important
// otherwise this will shadow all csinc instructions
if (!(inst.Rm == inst.Rn)) return false;
inst.o2 = static_cast<uint8_t>(enc.o2);
inst.op = static_cast<uint8_t>(enc.op);
inst.iform = InstForm::CINC_CSINC_64_CONDSEL;
@@ -63155,6 +63173,10 @@ static bool TryExtractCINV_CSINV_32_CONDSEL(InstData &inst, uint32_t bits) {
if (!(inst.Rm != 0x1f)) return false;
inst.Rn = static_cast<uint8_t>(enc.Rn);
if (!(inst.Rn != 0x1f)) return false;
// The bitmask check autogenerated does not check
// if the two registers are the same which is important
// otherwise this will shadow all csinc instructions
if (!(inst.Rm == inst.Rn)) return false;
inst.o2 = static_cast<uint8_t>(enc.o2);
inst.op = static_cast<uint8_t>(enc.op);
inst.iform = InstForm::CINV_CSINV_32_CONDSEL;
@@ -63204,6 +63226,10 @@ static bool TryExtractCINV_CSINV_64_CONDSEL(InstData &inst, uint32_t bits) {
if (!(inst.Rm != 0x1f)) return false;
inst.Rn = static_cast<uint8_t>(enc.Rn);
if (!(inst.Rn != 0x1f)) return false;
// The bitmask check autogenerated does not check
// if the two registers are the same which is important
// otherwise this will shadow all csinc instructions
if (!(inst.Rm == inst.Rn)) return false;
inst.o2 = static_cast<uint8_t>(enc.o2);
inst.op = static_cast<uint8_t>(enc.op);
inst.iform = InstForm::CINV_CSINV_64_CONDSEL;
remill/Arch/AArch64/Runtime/BasicBlock.cpp
+2 -2
View File
@@ -117,10 +117,10 @@ extern "C" {
auto &X30 = state.gpr.x30.qword;
auto &FP = state.gpr.x29.qword;
auto &WFP = state.gpr.x29.qword;
auto &WFP = state.gpr.x29.dword;
auto &LP = state.gpr.x30.qword;
auto &WLP = state.gpr.x30.qword;
auto &WLP = state.gpr.x30.dword;
auto &SP = state.gpr.sp.qword;
auto &WSP = state.gpr.sp.dword;
remill/Arch/AArch64/Runtime/Instructions.cpp
+1
View File
@@ -110,4 +110,5 @@ DEF_ISEL(INVALID_INSTRUCTION) = HandleInvalidInstruction;
#include "remill/Arch/AArch64/Semantics/LOGICAL.cpp"
#include "remill/Arch/AArch64/Semantics/MISC.cpp"
#include "remill/Arch/AArch64/Semantics/SHIFT.cpp"
#include "remill/Arch/AArch64/Semantics/COND.cpp"
#include "remill/Arch/AArch64/Semantics/SYSTEM.cpp"
remill/Arch/AArch64/Semantics/BINARY.cpp
-1
View File
@@ -77,7 +77,6 @@ DEF_SEM(ADDS, D dst, S1 src1, S2 src2) {
WriteZExt(dst, res);
return memory;
}
} // namespace
DEF_ISEL(SUBS_32_ADDSUB_SHIFT) = SUBS<R32W, R32, I32>;
remill/Arch/AArch64/Semantics/BITBYTE.cpp
+13
View File
@@ -95,3 +95,16 @@ DEF_SEM(EXTR, D dst, S src1, S src2, I src3) {
DEF_ISEL(EXTR_32_EXTRACT) = EXTR<R32W, R32, I32>;
DEF_ISEL(EXTR_64_EXTRACT) = EXTR<R64W, R64, I64>;
namespace {
template <typename D, typename S>
DEF_SEM(CLZ, D dst, S src) {
auto count = CountLeadingZeros(Read(src));
WriteZExt(dst, count);
return memory;
}
} // namespace
DEF_ISEL(CLZ_32_DP_1SRC) = CLZ<R32W, R32>;
DEF_ISEL(CLZ_64_DP_1SRC) = CLZ<R64W, R64>;
remill/Arch/AArch64/Semantics/COND.cpp
+206
View File
@@ -0,0 +1,206 @@
/*
* Copyright (c) 2017 Trail of Bits, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
namespace {
template <bool (*check_cond)(const State &), typename D, typename S1, typename S2>
DEF_SEM(CSEL, D dst, S1 src1, S2 src2) {
auto val = check_cond(state) ? Read(src1) : Read(src2);
WriteZExt(dst, val);
return memory;
}
} // namespace
DEF_ISEL(CSEL_32_CONDSEL_GE) = CSEL<CondGE, R32W, R32, R32>;
DEF_ISEL(CSEL_32_CONDSEL_GT) = CSEL<CondGT, R32W, R32, R32>;
DEF_ISEL(CSEL_32_CONDSEL_LE) = CSEL<CondLE, R32W, R32, R32>;
DEF_ISEL(CSEL_32_CONDSEL_LT) = CSEL<CondLT, R32W, R32, R32>;
DEF_ISEL(CSEL_32_CONDSEL_EQ) = CSEL<CondEQ, R32W, R32, R32>;
DEF_ISEL(CSEL_32_CONDSEL_NE) = CSEL<CondNE, R32W, R32, R32>;
DEF_ISEL(CSEL_32_CONDSEL_CS) = CSEL<CondCS, R32W, R32, R32>;
DEF_ISEL(CSEL_32_CONDSEL_CC) = CSEL<CondCC, R32W, R32, R32>;
DEF_ISEL(CSEL_32_CONDSEL_MI) = CSEL<CondMI, R32W, R32, R32>;
DEF_ISEL(CSEL_32_CONDSEL_PL) = CSEL<CondPL, R32W, R32, R32>;
DEF_ISEL(CSEL_32_CONDSEL_VS) = CSEL<CondVS, R32W, R32, R32>;
DEF_ISEL(CSEL_32_CONDSEL_VC) = CSEL<CondVC, R32W, R32, R32>;
DEF_ISEL(CSEL_32_CONDSEL_HI) = CSEL<CondHI, R32W, R32, R32>;
DEF_ISEL(CSEL_32_CONDSEL_LS) = CSEL<CondLS, R32W, R32, R32>;
DEF_ISEL(CSEL_32_CONDSEL_AL) = CSEL<CondAL, R32W, R32, R32>;
DEF_ISEL(CSEL_64_CONDSEL_GE) = CSEL<CondGE, R64W, R64, R64>;
DEF_ISEL(CSEL_64_CONDSEL_GT) = CSEL<CondGT, R64W, R64, R64>;
DEF_ISEL(CSEL_64_CONDSEL_LE) = CSEL<CondLE, R64W, R64, R64>;
DEF_ISEL(CSEL_64_CONDSEL_LT) = CSEL<CondLT, R64W, R64, R64>;
DEF_ISEL(CSEL_64_CONDSEL_EQ) = CSEL<CondEQ, R64W, R64, R64>;
DEF_ISEL(CSEL_64_CONDSEL_NE) = CSEL<CondNE, R64W, R64, R64>;
DEF_ISEL(CSEL_64_CONDSEL_CS) = CSEL<CondCS, R64W, R64, R64>;
DEF_ISEL(CSEL_64_CONDSEL_CC) = CSEL<CondCC, R64W, R64, R64>;
DEF_ISEL(CSEL_64_CONDSEL_MI) = CSEL<CondMI, R64W, R64, R64>;
DEF_ISEL(CSEL_64_CONDSEL_PL) = CSEL<CondPL, R64W, R64, R64>;
DEF_ISEL(CSEL_64_CONDSEL_VS) = CSEL<CondVS, R64W, R64, R64>;
DEF_ISEL(CSEL_64_CONDSEL_VC) = CSEL<CondVC, R64W, R64, R64>;
DEF_ISEL(CSEL_64_CONDSEL_HI) = CSEL<CondHI, R64W, R64, R64>;
DEF_ISEL(CSEL_64_CONDSEL_LS) = CSEL<CondLS, R64W, R64, R64>;
DEF_ISEL(CSEL_64_CONDSEL_AL) = CSEL<CondAL, R64W, R64, R64>;
namespace {
template <bool (*check_cond)(const State &), typename D, typename S1, typename S2>
DEF_SEM(CSNEG, D dst, S1 src1, S2 src2) {
auto val = check_cond(state) ? Read(src1) : UAdd(UNot(Read(src2)), ZExtTo<S2>(1));
WriteZExt(dst, val);
return memory;
}
} // namespace
DEF_ISEL(CSNEG_32_CONDSEL_GE) = CSNEG<CondGE, R32W, R32, R32>;
DEF_ISEL(CSNEG_32_CONDSEL_GT) = CSNEG<CondGT, R32W, R32, R32>;
DEF_ISEL(CSNEG_32_CONDSEL_LE) = CSNEG<CondLE, R32W, R32, R32>;
DEF_ISEL(CSNEG_32_CONDSEL_LT) = CSNEG<CondLT, R32W, R32, R32>;
DEF_ISEL(CSNEG_32_CONDSEL_EQ) = CSNEG<CondEQ, R32W, R32, R32>;
DEF_ISEL(CSNEG_32_CONDSEL_NE) = CSNEG<CondNE, R32W, R32, R32>;
DEF_ISEL(CSNEG_32_CONDSEL_CS) = CSNEG<CondCS, R32W, R32, R32>;
DEF_ISEL(CSNEG_32_CONDSEL_CC) = CSNEG<CondCC, R32W, R32, R32>;
DEF_ISEL(CSNEG_32_CONDSEL_MI) = CSNEG<CondMI, R32W, R32, R32>;
DEF_ISEL(CSNEG_32_CONDSEL_PL) = CSNEG<CondPL, R32W, R32, R32>;
DEF_ISEL(CSNEG_32_CONDSEL_VS) = CSNEG<CondVS, R32W, R32, R32>;
DEF_ISEL(CSNEG_32_CONDSEL_VC) = CSNEG<CondVC, R32W, R32, R32>;
DEF_ISEL(CSNEG_32_CONDSEL_HI) = CSNEG<CondHI, R32W, R32, R32>;
DEF_ISEL(CSNEG_32_CONDSEL_LS) = CSNEG<CondLS, R32W, R32, R32>;
DEF_ISEL(CSNEG_32_CONDSEL_AL) = CSNEG<CondAL, R32W, R32, R32>;
DEF_ISEL(CSNEG_64_CONDSEL_GE) = CSNEG<CondGE, R64W, R64, R64>;
DEF_ISEL(CSNEG_64_CONDSEL_GT) = CSNEG<CondGT, R64W, R64, R64>;
DEF_ISEL(CSNEG_64_CONDSEL_LE) = CSNEG<CondLE, R64W, R64, R64>;
DEF_ISEL(CSNEG_64_CONDSEL_LT) = CSNEG<CondLT, R64W, R64, R64>;
DEF_ISEL(CSNEG_64_CONDSEL_EQ) = CSNEG<CondEQ, R64W, R64, R64>;
DEF_ISEL(CSNEG_64_CONDSEL_NE) = CSNEG<CondNE, R64W, R64, R64>;
DEF_ISEL(CSNEG_64_CONDSEL_CS) = CSNEG<CondCS, R64W, R64, R64>;
DEF_ISEL(CSNEG_64_CONDSEL_CC) = CSNEG<CondCC, R64W, R64, R64>;
DEF_ISEL(CSNEG_64_CONDSEL_MI) = CSNEG<CondMI, R64W, R64, R64>;
DEF_ISEL(CSNEG_64_CONDSEL_PL) = CSNEG<CondPL, R64W, R64, R64>;
DEF_ISEL(CSNEG_64_CONDSEL_VS) = CSNEG<CondVS, R64W, R64, R64>;
DEF_ISEL(CSNEG_64_CONDSEL_VC) = CSNEG<CondVC, R64W, R64, R64>;
DEF_ISEL(CSNEG_64_CONDSEL_HI) = CSNEG<CondHI, R64W, R64, R64>;
DEF_ISEL(CSNEG_64_CONDSEL_LS) = CSNEG<CondLS, R64W, R64, R64>;
DEF_ISEL(CSNEG_64_CONDSEL_AL) = CSNEG<CondAL, R64W, R64, R64>;
namespace {
template <bool (*check_cond)(const State &), typename D, typename S1, typename S2>
DEF_SEM(CSINC, D dst, S1 src1, S2 src2) {
auto val = check_cond(state)? Read(src1) : UAdd(Read(src2), 1);
WriteZExt(dst, val);
return memory;
}
} // namespace
DEF_ISEL(CSINC_32_CONDSEL_GE) = CSINC<CondGE, R32W, R32, R32>;
DEF_ISEL(CSINC_32_CONDSEL_GT) = CSINC<CondGT, R32W, R32, R32>;
DEF_ISEL(CSINC_32_CONDSEL_LE) = CSINC<CondLE, R32W, R32, R32>;
DEF_ISEL(CSINC_32_CONDSEL_LT) = CSINC<CondLT, R32W, R32, R32>;
DEF_ISEL(CSINC_32_CONDSEL_EQ) = CSINC<CondEQ, R32W, R32, R32>;
DEF_ISEL(CSINC_32_CONDSEL_NE) = CSINC<CondNE, R32W, R32, R32>;
DEF_ISEL(CSINC_32_CONDSEL_CS) = CSINC<CondCS, R32W, R32, R32>;
DEF_ISEL(CSINC_32_CONDSEL_CC) = CSINC<CondCC, R32W, R32, R32>;
DEF_ISEL(CSINC_32_CONDSEL_MI) = CSINC<CondMI, R32W, R32, R32>;
DEF_ISEL(CSINC_32_CONDSEL_PL) = CSINC<CondPL, R32W, R32, R32>;
DEF_ISEL(CSINC_32_CONDSEL_VS) = CSINC<CondVS, R32W, R32, R32>;
DEF_ISEL(CSINC_32_CONDSEL_VC) = CSINC<CondVC, R32W, R32, R32>;
DEF_ISEL(CSINC_32_CONDSEL_HI) = CSINC<CondHI, R32W, R32, R32>;
DEF_ISEL(CSINC_32_CONDSEL_LS) = CSINC<CondLS, R32W, R32, R32>;
DEF_ISEL(CSINC_32_CONDSEL_AL) = CSINC<CondAL, R32W, R32, R32>;
DEF_ISEL(CSINC_64_CONDSEL_GE) = CSINC<CondGE, R64W, R64, R64>;
DEF_ISEL(CSINC_64_CONDSEL_GT) = CSINC<CondGT, R64W, R64, R64>;
DEF_ISEL(CSINC_64_CONDSEL_LE) = CSINC<CondLE, R64W, R64, R64>;
DEF_ISEL(CSINC_64_CONDSEL_LT) = CSINC<CondLT, R64W, R64, R64>;
DEF_ISEL(CSINC_64_CONDSEL_EQ) = CSINC<CondEQ, R64W, R64, R64>;
DEF_ISEL(CSINC_64_CONDSEL_NE) = CSINC<CondNE, R64W, R64, R64>;
DEF_ISEL(CSINC_64_CONDSEL_CS) = CSINC<CondCS, R64W, R64, R64>;
DEF_ISEL(CSINC_64_CONDSEL_CC) = CSINC<CondCC, R64W, R64, R64>;
DEF_ISEL(CSINC_64_CONDSEL_MI) = CSINC<CondMI, R64W, R64, R64>;
DEF_ISEL(CSINC_64_CONDSEL_PL) = CSINC<CondPL, R64W, R64, R64>;
DEF_ISEL(CSINC_64_CONDSEL_VS) = CSINC<CondVS, R64W, R64, R64>;
DEF_ISEL(CSINC_64_CONDSEL_VC) = CSINC<CondVC, R64W, R64, R64>;
DEF_ISEL(CSINC_64_CONDSEL_HI) = CSINC<CondHI, R64W, R64, R64>;
DEF_ISEL(CSINC_64_CONDSEL_LS) = CSINC<CondLS, R64W, R64, R64>;
DEF_ISEL(CSINC_64_CONDSEL_AL) = CSINC<CondAL, R64W, R64, R64>;
namespace {
template <bool (*check_cond)(const State &), typename D, typename S1, typename S2>
DEF_SEM(CSINV, D dst, S1 src1, S2 src2) {
auto val = check_cond(state)? Read(src1) : UNot(Read(src2));
WriteZExt(dst, val);
return memory;
}
} // namespace
DEF_ISEL(CSINV_32_CONDSEL_GE) = CSINV<CondGE, R32W, R32, R32>;
DEF_ISEL(CSINV_32_CONDSEL_GT) = CSINV<CondGT, R32W, R32, R32>;
DEF_ISEL(CSINV_32_CONDSEL_LE) = CSINV<CondLE, R32W, R32, R32>;
DEF_ISEL(CSINV_32_CONDSEL_LT) = CSINV<CondLT, R32W, R32, R32>;
DEF_ISEL(CSINV_32_CONDSEL_EQ) = CSINV<CondEQ, R32W, R32, R32>;
DEF_ISEL(CSINV_32_CONDSEL_NE) = CSINV<CondNE, R32W, R32, R32>;
DEF_ISEL(CSINV_32_CONDSEL_CS) = CSINV<CondCS, R32W, R32, R32>;
DEF_ISEL(CSINV_32_CONDSEL_CC) = CSINV<CondCC, R32W, R32, R32>;
DEF_ISEL(CSINV_32_CONDSEL_MI) = CSINV<CondMI, R32W, R32, R32>;
DEF_ISEL(CSINV_32_CONDSEL_PL) = CSINV<CondPL, R32W, R32, R32>;
DEF_ISEL(CSINV_32_CONDSEL_VS) = CSINV<CondVS, R32W, R32, R32>;
DEF_ISEL(CSINV_32_CONDSEL_VC) = CSINV<CondVC, R32W, R32, R32>;
DEF_ISEL(CSINV_32_CONDSEL_HI) = CSINV<CondHI, R32W, R32, R32>;
DEF_ISEL(CSINV_32_CONDSEL_LS) = CSINV<CondLS, R32W, R32, R32>;
DEF_ISEL(CSINV_32_CONDSEL_AL) = CSINV<CondAL, R32W, R32, R32>;
DEF_ISEL(CSINV_64_CONDSEL_GE) = CSINV<CondGE, R64W, R64, R64>;
DEF_ISEL(CSINV_64_CONDSEL_GT) = CSINV<CondGT, R64W, R64, R64>;
DEF_ISEL(CSINV_64_CONDSEL_LE) = CSINV<CondLE, R64W, R64, R64>;
DEF_ISEL(CSINV_64_CONDSEL_LT) = CSINV<CondLT, R64W, R64, R64>;
DEF_ISEL(CSINV_64_CONDSEL_EQ) = CSINV<CondEQ, R64W, R64, R64>;
DEF_ISEL(CSINV_64_CONDSEL_NE) = CSINV<CondNE, R64W, R64, R64>;
DEF_ISEL(CSINV_64_CONDSEL_CS) = CSINV<CondCS, R64W, R64, R64>;
DEF_ISEL(CSINV_64_CONDSEL_CC) = CSINV<CondCC, R64W, R64, R64>;
DEF_ISEL(CSINV_64_CONDSEL_MI) = CSINV<CondMI, R64W, R64, R64>;
DEF_ISEL(CSINV_64_CONDSEL_PL) = CSINV<CondPL, R64W, R64, R64>;
DEF_ISEL(CSINV_64_CONDSEL_VS) = CSINV<CondVS, R64W, R64, R64>;
DEF_ISEL(CSINV_64_CONDSEL_VC) = CSINV<CondVC, R64W, R64, R64>;
DEF_ISEL(CSINV_64_CONDSEL_HI) = CSINV<CondHI, R64W, R64, R64>;
DEF_ISEL(CSINV_64_CONDSEL_LS) = CSINV<CondLS, R64W, R64, R64>;
DEF_ISEL(CSINV_64_CONDSEL_AL) = CSINV<CondAL, R64W, R64, R64>;
namespace {
template <bool (*check_cond)(const State &), typename S1, typename S2>
DEF_SEM(CCMP, S1 src1, S2 src2, S2 nzcv) {
using T = typename BaseType<S1>::BT;
if (check_cond(state)) {
//
// (void) AddWithCarryNZCV(state, Read(src1), UNot(Read(src2)), T(1));
return memory;
} else {
auto nzcv_val = Read(nzcv);
FLAG_V = UCmpNeq(UAnd(nzcv_val, T(1)), T(0));
FLAG_C = UCmpNeq(UAnd(nzcv_val, T(2)), T(0));
FLAG_Z = UCmpNeq(UAnd(nzcv_val, T(4)), T(0));
FLAG_N = UCmpNeq(UAnd(nzcv_val, T(8)), T(0));
}
return memory;
}
} // namespace
DEF_ISEL(CCMP_32_CONDCMP_IMM_EQ) = CCMP<CondEQ, R32, I32>;
tests/AArch64/BINARY/ANDS_n_LOG_IMM.S
+57
View File
@@ -0,0 +1,57 @@
/*
* Copyright (c) 2017 Trail of Bits, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* ANDS <Wd>, <Wn>, #<imm> */
TEST_BEGIN(ANDS_32S_LOG_IMM, ands_w9_w0_0x10101010, 1)
TEST_INPUTS(
0,
1,
0xFFFFFFFF,
0xfafbfbfd,
0xf1f2f3f4,
0x0a0b0c0d,
0x01020304)
ands w9, w0, #0x10101010
TEST_END
/* ANDS <Xd>, <Xn>, #<imm> */
TEST_BEGIN(ANDS_64S_LOG_IMM, ands_x9_x0_0x1010101010101010, 1)
TEST_INPUTS(
0,
1,
0xFFFFFFFF,
0xfafbfbfd,
0xf1f2f3f4,
0x0a0b0c0d,
0x01020304)
ands x9, x0, #0x1010101010101010
TEST_END
TEST_BEGIN(ANDS_64S_LOG_IMM, ands_x9_x0_0xfff80007ffffffff, 1)
TEST_INPUTS(
0,
1,
0xFFFFFFFF,
0xfafbfbfd,
0xf1f2f3f4,
0x0a0b0c0d,
0x01020304)
ands x9, x0, #0xfff80007ffffffff
TEST_END
tests/AArch64/BITBYTE/CLZ_n_DP_1SRC.S
+53
View File
@@ -0,0 +1,53 @@
/*
* Copyright (c) 2017 Trail of Bits, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* CLZ <Wd>, <Wn> */
TEST_BEGIN(CLZ_32_DP_1SRC, clz_w1_w0, 1)
TEST_INPUTS(
0,
1,
0xFFFFFFFF,
0xfafbfbfd,
0xf1f2f3f4,
0x0a0b0c0d,
0x01020304
)
clz w1, w0
TEST_END
/* CLZ <Xd>, <Xn> */
TEST_BEGIN(CLZ_64_DP_1SRC, clz_x1_x0, 1)
TEST_INPUTS(
0,
1,
0,
1,
0xFFFFFFFF,
0xFFFFFFFF,
0xf1f2f3f4,
0x01020304,
0xFFFFFFFFFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF00000000,
0xFFFFFFFFFFFFFFFF,
0xf1f2f3f4fafbfbfd,
0x010203040a0b0c0d
)
clz x1, x0;
TEST_END
tests/AArch64/COND/CCMP_n_CONDCMP_IMM.S
+55
View File
@@ -0,0 +1,55 @@
/*
* Copyright (c) 2017 Trail of Bits, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
TEST_BEGIN(CCMP_32_CONDCMP_IMM_EQ, ccmp_w0_eq_1, 1)
TEST_INPUTS(
0x11
)
ccmp w0, #0x11, #0x0, eq
TEST_END
// TEST_BEGIN(CCMP_32_CONDCMP_IMM_EQ, ccmp_32_cmpne_eq_11_c, 1)
// TEST_INPUTS(
// 0x11,
// 0x0,
// 0x1,
// 0xf,
// 0x7,
// 0xffffff
// )
// mov w9, #0xdead
// ccmp w0, #0x11, #0xc, eq
// b.eq 99f
// mov w9, #0xface
// 99:
// TEST_END
// TEST_BEGIN(CCMP_32_CONDCMP_IMM_HI, ccmp_32_cmpeq_hi_11_c, 1)
// TEST_INPUTS(
// 0x11,
// 0x0,
// 0x1,
// 0xf,
// 0x7,
// 0xffffff
// )
// mov w9, #0xdead
// ccmp w0, #0x11, #0xc, hi
// b.eq 99f
// mov w9, #0xface
// 99:
// TEST_END
tests/AArch64/COND/CSEL_n_CONDSEL.S
+50
View File
@@ -0,0 +1,50 @@
/*
* Copyright (c) 2017 Trail of Bits, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
TEST_BEGIN(CSEL_32_CONDSEL_EQ, csel_32_eq, 2)
TEST_INPUTS(
0x0, 0x1,
0x22, 0x22,
0xffffffff, 0x1,
0x1, 0xffffffff
)
mov w3, #0xdead
mov w4, #0xface
csel w2, w3, w4, EQ
TEST_END
TEST_BEGIN(CSEL_32_CONDSEL_HI, csel_32_HI, 2)
TEST_INPUTS(
0x0, 0x1,
0x22, 0x22,
0xffffffff, 0x1,
0x1, 0xffffffff
)
mov w3, #0xdead
mov w4, #0xface
csel w2, w3, w4, HI
TEST_END
TEST_BEGIN(CSEL_64_CONDSEL_EQ, csel_64_eq, 2)
TEST_INPUTS(
0x0, 0x1,
0xfffffffffffffffc, 0xfffffffffffffffc
)
mov x3, #0xdead
mov x4, #0xface
csel x2, x3, x4, EQ
TEST_END
tests/AArch64/COND/x_CSINC_n_CONDSEL.S
+69
View File
@@ -0,0 +1,69 @@
/*
* Copyright (c) 2017 Trail of Bits, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
TEST_BEGIN(CSINC_32_CONDSEL_EQ, csinc_32_eq, 2)
TEST_INPUTS(
0x0, 0x1
)
mov w3, #0xdead
mov w4, #0xface
csinc w2, w3, w4, eq
TEST_END
TEST_BEGIN(CSINC_64_CONDSEL_EQ, csinc_64_eq, 2)
TEST_INPUTS(
0x0, 0x1,
0xfffffffffffffffc, 0xfffffffffffffffc
)
mov x3, #0xdead
mov x4, #0xface
csinc x2, x3, x4, eq
TEST_END
TEST_BEGIN(CSINC_32_CONDSEL_EQ, cinc_csinc_32_ne, 2)
TEST_INPUTS(
0x0, 0x1,
0x22, 0x22
)
mov w3, #0xface
cinc w4, w3, ne
TEST_END
TEST_BEGIN(CSINC_64_CONDSEL_EQ, cinc_csinc_64_ne, 2)
TEST_INPUTS(
0x0, 0x1,
0xfffffffffffffffc, 0xfffffffffffffffc
)
mov x3, #0xface
cinc x5, x3, ne
TEST_END
TEST_BEGIN(CSINC_32_CONDSEL_EQ, cset_csinc_32_ne, 2)
TEST_INPUTS(
0x0, 0x1,
0x22, 0x22
)
cset w3, ne
TEST_END
TEST_BEGIN(CSINC_64_CONDSEL_EQ, cset_csinc_64_ne, 2)
TEST_INPUTS(
0x0, 0x1,
0xfffffffffffffffc, 0xfffffffffffffffc
)
cset x3, ne
TEST_END
tests/AArch64/COND/x_CSINV_n_CONDSEL.S
+69
View File
@@ -0,0 +1,69 @@
/*
* Copyright (c) 2017 Trail of Bits, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
TEST_BEGIN(CSINV_32_CONDSEL_EQ, csinv_32_eq, 2)
TEST_INPUTS(
0x0, 0x1
)
mov w3, #0xdead
mov w4, #0xface
csinv w2, w3, w4, eq
TEST_END
TEST_BEGIN(CSINV_64_CONDSEL_EQ, csinv_64_eq, 2)
TEST_INPUTS(
0x0, 0x1,
0xfffffffffffffffc, 0xfffffffffffffffc
)
mov x3, #0xdead
mov x4, #0xface
csinv x2, x3, x4, eq
TEST_END
TEST_BEGIN(CSINV_32_CONDSEL_EQ, cisv_csinv_32_ne, 2)
TEST_INPUTS(
0x0, 0x1,
0x22, 0x22
)
mov w3, #0xface
cinv w4, w3, ne
TEST_END
TEST_BEGIN(CSINV_64_CONDSEL_EQ, cinv_csinv_64_ne, 2)
TEST_INPUTS(
0x0, 0x1,
0xfffffffffffffffc, 0xfffffffffffffffc
)
mov x3, #0xface
cinv x5, x3, ne
TEST_END
TEST_BEGIN(CSINV_32_CONDSEL_EQ, csetm_csinv_32_ne, 2)
TEST_INPUTS(
0x0, 0x1,
0x22, 0x22
)
csetm w2, ne
TEST_END
TEST_BEGIN(CSINV_64_CONDSEL_EQ, csetm_csinv_64_ne, 2)
TEST_INPUTS(
0x0, 0x1,
0xfffffffffffffffc, 0xfffffffffffffffc
)
csetm x3, ne
TEST_END
tests/AArch64/COND/x_CSNEG_n_CONDSEL.S
+65
View File
@@ -0,0 +1,65 @@
/*
* Copyright (c) 2017 Trail of Bits, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
TEST_BEGIN(CSNEG_32_CONDSEL_EQ, csneg_32_eq, 2)
TEST_INPUTS(
0x0, 0x1,
0x51, 0x22,
0xffffffff, 0x1,
0x1, 0xffffffff
)
csneg w2, w0, w1, EQ
TEST_END
TEST_BEGIN(CSNEG_32_CONDSEL_HI, csneg_32_HI, 2)
TEST_INPUTS(
0x0, 0x1,
0x22, 0x22,
0xffffffff, 0x1,
0x1, 0xffffffff
)
csneg w2, w0, w1, HI
TEST_END
TEST_BEGIN(CSNEG_32_CONDSEL_EQ, cneg_csneg_32_ne, 1)
TEST_INPUTS(
0x0,
0x51,
0x22,
0xffffffff
)
cneg w2, w0, ne
TEST_END
TEST_BEGIN(CSNEG_64_CONDSEL_EQ, csneg_64_eq, 2)
TEST_INPUTS(
0x0, 0x1,
0xfffffffffffffffc, 0xfffffffffffffffc,
0x1, 0xffffffffffffffff,
0xffffffffffffffff, 0xfffffffffffffffe
)
csneg x2, x0, x1, EQ
TEST_END
TEST_BEGIN(CSNEG_64_CONDSEL_EQ, cneg_csneg_64_ne, 1)
TEST_INPUTS(
0x0,
0xfffffffffffffffc,
0xffffffffffffffff,
0xfffffffffffffffe
)
cneg x2, x0, ne
TEST_END
tests/AArch64/Tests.S
+8
View File
@@ -253,6 +253,7 @@ SYMBOL(__aarch64_test_table_begin):
#include "tests/AArch64/BITBYTE/EXTR_n_EXTRACT.S"
#include "tests/AArch64/BITBYTE/SBFM_nM_BITFIELD.S"
#include "tests/AArch64/BITBYTE/UBFM_nM_BITFIELD.S"
#include "tests/AArch64/BITBYTE/CLZ_n_DP_1SRC.S"
#include "tests/AArch64/BRANCH/B_ONLY_CONDBRANCH.S"
#include "tests/AArch64/BRANCH/CBNZ_n_COMPBRANCH.S"
@@ -277,8 +278,15 @@ SYMBOL(__aarch64_test_table_begin):
#include "tests/AArch64/LOGICAL/ORR_n_LOG_IMM.S"
#include "tests/AArch64/LOGICAL/ORR_n_LOG_SHIFT.S"
#include "tests/AArch64/COND/CSEL_n_CONDSEL.S"
#include "tests/AArch64/COND/x_CSNEG_n_CONDSEL.S"
// #include "tests/AArch64/COND/CCMP_n_CONDCMP_IMM.S"
#include "tests/AArch64/COND/x_CSINC_n_CONDSEL.S"
#include "tests/AArch64/COND/x_CSINV_n_CONDSEL.S"
#endif
/* Create a symbol that represents the end of the test information table. */
.section "__aarch64_test_table", "a"
.globl SYMBOL(__aarch64_test_table_end)