mirror of
https://github.com/lifting-bits/remill
synced 2026-06-21 13:56:07 +00:00
Peter Goodman
026ea1afec
* Added semantics and tests for SDIV * Semantics and tests for SCVTF. * Working on integer to/from float conversion bugs related to managing the fpu status register. * Switch to using the check float function wrapper * Remove unintentional call to fetestexcept * Adding in a compiler reordering barrier. * Added inline assembly that will force clang's optimizer to give up and filed a clang bug * Adds some trailing spaces into some files. Re-enables all aarch64 tests. * Added semantics and tests for SDIV * Semantics and tests for SCVTF. * Switch to using the check float function wrapper * Remove unintentional call to fetestexcept * Added inline assembly that will force clang's optimizer to give up and filed a clang bug * Adds some trailing spaces into some files. Re-enables all aarch64 tests. * Bringing the aarch64 branch back in line with master. * Adds in a test and ISEL for LDR_BL_LDST_REGOFF, and fixes up the instructions in some SMOV and UMOV tests. * Various fixes and some minor debugging aids for aarch64 * Resets the fenv before running lifted code. * All existing aarch64 tests should now pass.
96 lines
1.9 KiB
ArmAsm
96 lines
1.9 KiB
ArmAsm
/* Auto-generated file! Don't modify! */
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mov x2, #0
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ldrb w1, [x28, #1137]
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orr x2, x2, x1, LSL 31
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ldrb w1, [x28, #1139]
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orr x2, x2, x1, LSL 30
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ldrb w1, [x28, #1141]
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orr x2, x2, x1, LSL 29
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ldrb w1, [x28, #1143]
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orr x2, x2, x1, LSL 28
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str x2, [x28, #1072]
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msr nzcv, x2
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ldr x1, [x28, #1080]
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ldr x1, [x28, #1088]
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ldrb w2, [x28, #1153]
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bfi x1, x2, #0, #1
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ldrb w2, [x28, #1147]
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bfi x1, x2, #2, #1
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ldrb w2, [x28, #1149]
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bfi x1, x2, #3, #1
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ldrb w2, [x28, #1145]
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bfi x1, x2, #4, #1
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ldrb w2, [x28, #1151]
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bfi x1, x2, #6, #1
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str x1, [x28, #1088]
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msr fpcr, x1
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ldr x1, [x28, #1112]
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msr tpidr_el0, x1
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add x1, x28, #16
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ldur q0, [x1, #0]
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ldur q1, [x1, #16]
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ldur q2, [x1, #32]
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ldur q3, [x1, #48]
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ldur q4, [x1, #64]
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ldur q5, [x1, #80]
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ldur q6, [x1, #96]
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ldur q7, [x1, #112]
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ldur q8, [x1, #128]
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ldur q9, [x1, #144]
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ldur q10, [x1, #160]
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ldur q11, [x1, #176]
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ldur q12, [x1, #192]
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ldur q13, [x1, #208]
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ldur q14, [x1, #224]
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ldur q15, [x1, #240]
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add x1, x28, #272
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ldur q16, [x1, #0]
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ldur q17, [x1, #16]
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ldur q18, [x1, #32]
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ldur q19, [x1, #48]
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ldur q20, [x1, #64]
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ldur q21, [x1, #80]
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ldur q22, [x1, #96]
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ldur q23, [x1, #112]
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ldur q24, [x1, #128]
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ldur q25, [x1, #144]
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ldur q26, [x1, #160]
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ldur q27, [x1, #176]
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ldur q28, [x1, #192]
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ldur q29, [x1, #208]
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ldur q30, [x1, #224]
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ldur q31, [x1, #240]
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ldr x0, [x28, #544]
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ldr x1, [x28, #560]
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ldr x2, [x28, #576]
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ldr x3, [x28, #592]
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ldr x4, [x28, #608]
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ldr x5, [x28, #624]
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ldr x6, [x28, #640]
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ldr x7, [x28, #656]
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ldr x8, [x28, #672]
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ldr x9, [x28, #688]
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ldr x10, [x28, #704]
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ldr x11, [x28, #720]
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ldr x12, [x28, #736]
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ldr x13, [x28, #752]
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ldr x14, [x28, #768]
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ldr x15, [x28, #784]
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ldr x16, [x28, #800]
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ldr x17, [x28, #816]
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ldr x18, [x28, #832]
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ldr x19, [x28, #848]
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ldr x20, [x28, #864]
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ldr x21, [x28, #880]
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ldr x22, [x28, #896]
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ldr x23, [x28, #912]
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ldr x24, [x28, #928]
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ldr x25, [x28, #944]
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ldr x26, [x28, #960]
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ldr x27, [x28, #976]
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ldr x30, [x28, #1024]
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ldr x29, [x28, #1040]
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mov sp, x29
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ldr x29, [x28, #1008]
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