mirror of
https://github.com/rust-osdev/uefi-rs
synced 2026-06-08 17:17:36 +00:00
uefi: Refactor PciRootBridgeIo::enumerate() with tree-topology information
- Refactored return type from standard BTreeSet to custom PciTree struct - Removed special FullPciIoAddress type, since segment number is PciRoot dependent - During enumeration, skip branches we have already seen - During enumeration, collect tree topology information (which child bus linked from where) - Add complicated pci structure in integration test vm - Print child busses for every device entry in integration test
This commit is contained in:
Markus Ebner
@@ -21,9 +21,8 @@ pub fn test() {
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for pci_handle in pci_handles {
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let mut pci_proto = get_open_protocol::<PciRootBridgeIo>(pci_handle);
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let devices = pci_proto.enumerate().unwrap();
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for fqaddr in devices {
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let addr = fqaddr.addr();
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let pci_tree = pci_proto.enumerate().unwrap();
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for addr in pci_tree.iter().cloned() {
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let Ok(reg0) = pci_proto.pci().read_one::<u32>(addr.with_register(0)) else {
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continue;
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};
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@@ -53,8 +52,11 @@ pub fn test() {
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let (bus, dev, fun) = (addr.bus, addr.dev, addr.fun);
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log::info!(
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"PCI Device: [{bus}, {dev}, {fun}]: vendor={vendor_id:04X}, device={device_id:04X}, class={class_code:02X}, subclass={subclass_code:02X}"
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"PCI Device: [{bus:02x}, {dev:02x}, {fun:02x}]: vendor={vendor_id:04X}, device={device_id:04X}, class={class_code:02X}, subclass={subclass_code:02X}"
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);
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for child_bus in pci_tree.child_bus_of_iter(addr) {
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log::info!(" |- Bus: {child_bus:02x}");
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}
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}
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}
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@@ -16,9 +16,9 @@ fn test_allocating_api() {
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// by default respectively. We manually configure an additional SCSI controller.
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// Thus, we should see two controllers with support for EXT_SCSI_PASS_THRU on this platform
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#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
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assert_eq!(scsi_ctrl_handles.len(), 2);
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assert_eq!(scsi_ctrl_handles.len(), 4);
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#[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
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assert_eq!(scsi_ctrl_handles.len(), 1);
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assert_eq!(scsi_ctrl_handles.len(), 3);
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let mut found_drive = false;
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for handle in scsi_ctrl_handles {
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@@ -4,10 +4,11 @@
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use core::mem;
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use alloc::collections::btree_set::BTreeSet;
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use alloc::collections::btree_map::BTreeMap;
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use alloc::collections::btree_set::{self, BTreeSet};
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use super::PciIoAddress;
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use super::root_bridge::PciRootBridgeIo;
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use super::{FullPciIoAddress, PciIoAddress};
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#[allow(unused)]
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#[derive(Clone, Copy, Debug)]
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@@ -55,6 +56,93 @@ fn read_device_register_u32<T: Sized + Copy>(
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}
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}
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// ##########################################################################################
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/// Struct representing the tree structure of PCI devices.
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///
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/// This allows iterating over all valid PCI device addresses in a tree, as well as querying
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/// the tree topology.
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#[derive(Debug)]
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pub struct PciTree {
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segment: u32,
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devices: BTreeSet<PciIoAddress>,
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bus_anchors: BTreeMap<u8 /* bus */, PciIoAddress>,
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}
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impl PciTree {
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pub(crate) const fn new(segment: u32) -> Self {
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Self {
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segment,
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devices: BTreeSet::new(),
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bus_anchors: BTreeMap::new(),
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}
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}
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pub(crate) fn should_visit_bus(&self, bus: u8) -> bool {
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!self.bus_anchors.contains_key(&bus)
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}
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pub(crate) fn push_device(&mut self, addr: PciIoAddress) {
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self.devices.insert(addr);
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}
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/// Pushes a new bridge into the topology.
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///
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/// Returns `false` if the bus is already in the topology and `true`
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/// if the bridge was added to the topology.
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pub(crate) fn push_bridge(&mut self, addr: PciIoAddress, child_bus: u8) -> bool {
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match self.bus_anchors.contains_key(&child_bus) {
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true => false,
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false => {
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self.bus_anchors.insert(child_bus, addr);
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true
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}
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}
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}
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/// Iterate over all valid PCI device addresses in this tree structure.
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pub fn iter(&self) -> btree_set::Iter<'_, PciIoAddress> {
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self.devices.iter()
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}
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/// Get the segment number of this PCI tree.
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#[must_use]
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pub const fn segment_nr(&self) -> u32 {
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self.segment
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}
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/// Query the address of the parent PCI bridge this `addr`'s bus is subordinate to.
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#[must_use]
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pub fn parent_for(&self, addr: PciIoAddress) -> Option<PciIoAddress> {
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self.bus_anchors.get(&addr.bus).cloned()
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}
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/// Iterate over all subsequent busses below the given `addr`.
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/// This yields 0 results if `addr` doesn't point to a PCI bridge.
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pub fn child_bus_of_iter(&self, addr: PciIoAddress) -> impl Iterator<Item = u8> {
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self.bus_anchors
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.iter()
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.filter(move |&(_, parent)| *parent == addr)
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.map(|(bus, _)| bus)
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.cloned()
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}
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}
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impl IntoIterator for PciTree {
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type Item = PciIoAddress;
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type IntoIter = btree_set::IntoIter<PciIoAddress>;
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fn into_iter(self) -> Self::IntoIter {
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self.devices.into_iter()
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}
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}
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impl<'a> IntoIterator for &'a PciTree {
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type Item = &'a PciIoAddress;
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type IntoIter = btree_set::Iter<'a, PciIoAddress>;
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fn into_iter(self) -> Self::IntoIter {
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self.devices.iter()
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}
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}
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// ##########################################################################################
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// # Query Helpers (read from a device's configuration registers)
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@@ -86,12 +174,12 @@ fn get_secondary_bus_range(
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fn visit_function(
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proto: &mut PciRootBridgeIo,
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addr: PciIoAddress,
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queue: &mut BTreeSet<FullPciIoAddress>,
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tree: &mut PciTree,
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) -> uefi::Result<()> {
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if get_vendor_id(proto, addr)? == 0xFFFF {
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return Ok(()); // function doesn't exist - bail instantly
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}
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queue.insert(FullPciIoAddress::new(proto.segment_nr(), addr));
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tree.push_device(addr);
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let (base_class, sub_class) = get_classes(proto, addr)?;
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let header_type = get_header_type(proto, addr)? & 0b01111111;
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if base_class == 0x6 && sub_class == 0x4 && header_type == 0x01 {
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@@ -106,8 +194,11 @@ fn visit_function(
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return Ok(());
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}
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for bus in secondary_bus_nr..=subordinate_bus_nr {
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// Recurse into the bus namespaces on the other side of the bridge
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visit_bus(proto, PciIoAddress::new(bus, 0, 0), queue)?;
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// Recurse into the bus namespaces on the other side of the bridge, if we haven't visited
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// the subordinate bus through a more direct path already
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if tree.push_bridge(addr, bus) {
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visit_bus(proto, PciIoAddress::new(bus, 0, 0), tree)?;
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}
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}
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}
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Ok(())
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@@ -116,17 +207,17 @@ fn visit_function(
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fn visit_device(
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proto: &mut PciRootBridgeIo,
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addr: PciIoAddress,
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queue: &mut BTreeSet<FullPciIoAddress>,
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tree: &mut PciTree,
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) -> uefi::Result<()> {
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if get_vendor_id(proto, addr)? == 0xFFFF {
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return Ok(()); // device doesn't exist
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}
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visit_function(proto, addr.with_function(0), queue)?;
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visit_function(proto, addr.with_function(0), tree)?;
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if get_header_type(proto, addr.with_function(0))? & 0x80 != 0 {
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// This is a multi-function device - also try the remaining functions [1;7]
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// These remaining functions can be sparsely populated - as long as function 0 exists.
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for fun in 1..=7 {
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visit_function(proto, addr.with_function(fun), queue)?;
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visit_function(proto, addr.with_function(fun), tree)?;
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}
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}
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@@ -136,11 +227,11 @@ fn visit_device(
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pub(crate) fn visit_bus(
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proto: &mut PciRootBridgeIo,
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addr: PciIoAddress,
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queue: &mut BTreeSet<FullPciIoAddress>,
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tree: &mut PciTree,
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) -> uefi::Result<()> {
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// Given a valid bus entry point - simply try all possible devices addresses
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for dev in 0..32 {
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visit_device(proto, addr.with_device(dev), queue)?;
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visit_device(proto, addr.with_device(dev), tree)?;
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}
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Ok(())
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}
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@@ -8,7 +8,7 @@ use uefi_raw::protocol::pci::root_bridge::PciRootBridgeIoProtocolWidth;
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pub mod configuration;
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#[cfg(feature = "alloc")]
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mod enumeration;
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pub mod enumeration;
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pub mod root_bridge;
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/// IO Address for PCI/register IO operations
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@@ -124,36 +124,6 @@ impl Ord for PciIoAddress {
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}
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}
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// --------------------------------------------------------------------------------------------
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/// Fully qualified pci address. This address is valid across root bridges.
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#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash, PartialOrd, Ord)]
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pub struct FullPciIoAddress {
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/// PCI segment number
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segment: u32,
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/// Subsequent PCI address
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addr: PciIoAddress,
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}
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impl FullPciIoAddress {
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/// Construct a new fully qualified pci address.
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#[must_use]
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pub const fn new(segment: u32, addr: PciIoAddress) -> Self {
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Self { segment, addr }
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}
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/// Get the segment number this address belongs to.
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#[must_use]
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pub const fn segment(&self) -> u32 {
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self.segment
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}
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/// Get the internal RootBridge-specific portion of the address.
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#[must_use]
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pub const fn addr(&self) -> PciIoAddress {
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self.addr
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}
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}
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// ############################################################################################
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/// Trait implemented by all data types that can natively be read from a PCI device.
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@@ -7,8 +7,6 @@ use crate::StatusExt;
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#[cfg(feature = "alloc")]
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use crate::proto::pci::configuration::QwordAddressSpaceDescriptor;
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#[cfg(feature = "alloc")]
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use alloc::collections::btree_set::BTreeSet;
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#[cfg(feature = "alloc")]
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use alloc::vec::Vec;
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#[cfg(feature = "alloc")]
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use core::ffi::c_void;
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@@ -16,8 +14,6 @@ use core::ptr;
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use uefi_macros::unsafe_protocol;
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use uefi_raw::protocol::pci::root_bridge::{PciRootBridgeIoAccess, PciRootBridgeIoProtocol};
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#[cfg(doc)]
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use super::FullPciIoAddress;
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#[cfg(doc)]
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use crate::Status;
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@@ -84,10 +80,10 @@ impl PciRootBridgeIo {
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// ###################################################
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// # Convenience functionality
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/// Recursively enumerate all devices, device functions and pci-to-pci bridges on this root bridge.
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/// Recursively enumerate all devices, device functions and pci(e)-to-pci(e) bridges, starting from this pci root.
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///
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/// The returned addresses might overlap with the addresses returned by another [`PciRootBridgeIo`] instance.
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/// Make sure to perform some form of cross-[`PciRootBridgeIo`] deduplication on the returned [`FullPciIoAddress`]es.
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/// Make sure to perform some form of cross-[`PciRootBridgeIo`] deduplication on the discovered addresses.
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/// **WARNING:** Only use the returned addresses with the respective [`PciRootBridgeIo`] instance that returned them.
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///
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/// # Returns
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@@ -96,24 +92,27 @@ impl PciRootBridgeIo {
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/// # Errors
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/// This can basically fail with all the IO errors found in [`PciIoAccessPci`] methods.
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#[cfg(feature = "alloc")]
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pub fn enumerate(&mut self) -> crate::Result<BTreeSet<super::FullPciIoAddress>> {
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pub fn enumerate(&mut self) -> crate::Result<super::enumeration::PciTree> {
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use super::enumeration::{self, PciTree};
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use crate::proto::pci::configuration::ResourceRangeType;
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use crate::proto::pci::enumeration;
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let mut devices = BTreeSet::new();
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// In the descriptors, the entry with range_type bus specifies the bus numbers that were
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// allocated to devices below this root bridge. The first bus number in this range is
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// the starting point. All subsequent numbers are reached via PCI bridge recursion during enumeration.
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if let Some(descriptor) = self
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.configuration()?
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.iter()
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.find(|d| d.resource_range_type == ResourceRangeType::Bus)
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{
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let addr = PciIoAddress::new(descriptor.address_min as u8, 0, 0);
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enumeration::visit_bus(self, addr, &mut devices)?;
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let mut tree = PciTree::new(self.segment_nr());
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for descriptor in self.configuration()? {
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// In the descriptors we can query for the current root bridge, Bus entries contain ranges of valid
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// bus addresses. These are all bus addresses found below ourselves. These are not only the busses
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// linked to **directly** from ourselves, but also recursively. Thus we use PciTree::push_bus() to
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// determine whether we have already visited a given bus number.
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if descriptor.resource_range_type == ResourceRangeType::Bus {
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for bus in (descriptor.address_min as u8)..=(descriptor.address_max as u8) {
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if tree.should_visit_bus(bus) {
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let addr = PciIoAddress::new(bus, 0, 0);
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enumeration::visit_bus(self, addr, &mut tree)?;
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}
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}
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}
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}
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Ok(devices)
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Ok(tree)
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}
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}
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@@ -506,6 +506,37 @@ pub fn run_qemu(arch: UefiArch, opt: &QemuOpt) -> Result<()> {
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None
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};
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// Make PCI tree a little more complicated so the PCI enumeration integration
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// test is more interesting. This specific architecture was taken from:
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// https://blogs.oracle.com/linux/a-study-of-the-linux-kernel-pci-subsystem-with-qemu
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// It employs a complex PCIe switch (x3130) setup, which makes it interesting for testing.
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// The bus architecture this generates is found below `0000:00:03.0` in below diagram.
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// (actual bus numbers and surrounding devices don't match this diagram)
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// -[0000:00]-+-00.0
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// +-01.0
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// +-02.0
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// +-03.0-[01-04]----00.0-[02-04]--+-00.0-[03]----00.0
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// | \-01.0-[04]----00.0
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// +-1f.0
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// +-1f.2
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// \-1f.3
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// In the diagram, `0000:03:00.0` and `0000:04:00.0` are just dummy SCSI devices
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// connected below the PCIe switch, to test correct recursion in the bus enumeration implementation.
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cmd.args([
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"-device",
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"ioh3420,id=root_port1,bus=pcie.0",
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"-device",
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"x3130-upstream,id=upstream1,bus=root_port1",
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"-device",
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"xio3130-downstream,id=downstream1,bus=upstream1,chassis=9",
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"-device",
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"virtio-scsi-pci,bus=downstream1",
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"-device",
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"xio3130-downstream,id=downstream2,bus=upstream1,chassis=10",
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"-device",
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"virtio-scsi-pci,bus=downstream2",
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]);
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// Pass CA certificate database to the edk2 firmware, for TLS support.
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cmd.args([
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"-fw_cfg",
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