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https://github.com/simdjson/simdjson
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dlemire/support
| Author | SHA1 | Date | |
|---|---|---|---|
| 15e378af3c | |||
| fbc9b7e3fb | |||
| 1b5a9267d6 | |||
| e3c795072c | |||
| fb98cbdb3a | |||
| b98883b5ae | |||
| d39ef515a0 | |||
| 5bbf124690 | |||
| f51a32ebcd | |||
| e9b943bf32 |
@@ -57,7 +57,6 @@ POSSIBILITY OF SUCH DAMAGE.
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namespace simdjson {
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namespace internal {
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enum instruction_set {
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DEFAULT = 0x0,
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NEON = 0x1,
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@@ -107,7 +106,10 @@ constexpr uint32_t cpuid_avx512cd_bit = 1 << 28; ///< @private bit 28 of EBX
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constexpr uint32_t cpuid_avx512bw_bit = 1 << 30; ///< @private bit 30 of EBX for EAX=0x7
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constexpr uint32_t cpuid_avx512vl_bit = 1U << 31; ///< @private bit 31 of EBX for EAX=0x7
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constexpr uint32_t cpuid_avx512vbmi2_bit = 1 << 6; ///< @private bit 6 of ECX for EAX=0x7
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constexpr uint64_t cpuid_avx256_saved = uint64_t(1) << 2; ///< @private bit 2 = AVX
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constexpr uint64_t cpuid_avx512_saved = uint64_t(7) << 5; ///< @private bits 5,6,7 = opmask, ZMM_hi256, hi16_ZMM
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constexpr uint32_t cpuid_sse42_bit = 1 << 20; ///< @private bit 20 of ECX for EAX=0x1
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constexpr uint32_t cpuid_osxsave = (uint32_t(1) << 26) | (uint32_t(1) << 27); ///< @private bits 26+27 of ECX for EAX=0x1
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constexpr uint32_t cpuid_pclmulqdq_bit = 1 << 1; ///< @private bit 1 of ECX for EAX=0x1
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}
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@@ -117,7 +119,7 @@ static inline void cpuid(uint32_t *eax, uint32_t *ebx, uint32_t *ecx,
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uint32_t *edx) {
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#if defined(_MSC_VER)
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int cpu_info[4];
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__cpuid(cpu_info, *eax);
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__cpuidex(cpu_info, *eax, *ecx);
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*eax = cpu_info[0];
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*ebx = cpu_info[1];
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*ecx = cpu_info[2];
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@@ -135,10 +137,48 @@ static inline void cpuid(uint32_t *eax, uint32_t *ebx, uint32_t *ecx,
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#endif
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}
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static inline uint64_t xgetbv() {
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#if defined(_MSC_VER)
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return _xgetbv(0);
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#else
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uint32_t xcr0_lo, xcr0_hi;
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asm volatile("xgetbv\n\t" : "=a" (xcr0_lo), "=d" (xcr0_hi) : "c" (0));
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return xcr0_lo | (uint64_t(xcr0_hi) << 32);
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#endif
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}
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static inline uint32_t detect_supported_architectures() {
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uint32_t eax, ebx, ecx, edx;
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uint32_t host_isa = 0x0;
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// EBX for EAX=0x1
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eax = 0x1;
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ecx = 0x0;
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cpuid(&eax, &ebx, &ecx, &edx);
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if (ecx & cpuid_sse42_bit) {
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host_isa |= instruction_set::SSE42;
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} else {
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return host_isa; // everything after is redundant
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}
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if (ecx & cpuid_pclmulqdq_bit) {
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host_isa |= instruction_set::PCLMULQDQ;
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}
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if ((ecx & cpuid_osxsave) != cpuid_osxsave) {
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return host_isa;
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}
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// xgetbv for checking if the OS saves registers
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uint64_t xcr0 = xgetbv();
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if ((xcr0 & cpuid_avx256_saved) == 0) {
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return host_isa;
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}
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// ECX for EAX=0x7
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eax = 0x7;
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ecx = 0x0;
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@@ -154,6 +194,10 @@ static inline uint32_t detect_supported_architectures() {
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host_isa |= instruction_set::BMI2;
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}
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if (!((xcr0 & cpuid_avx512_saved) == cpuid_avx512_saved)) {
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return host_isa;
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}
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if (ebx & cpuid_avx512f_bit) {
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host_isa |= instruction_set::AVX512F;
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}
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@@ -190,18 +234,6 @@ static inline uint32_t detect_supported_architectures() {
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host_isa |= instruction_set::AVX512VBMI2;
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}
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// EBX for EAX=0x1
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eax = 0x1;
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cpuid(&eax, &ebx, &ecx, &edx);
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if (ecx & cpuid_sse42_bit) {
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host_isa |= instruction_set::SSE42;
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}
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if (ecx & cpuid_pclmulqdq_bit) {
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host_isa |= instruction_set::PCLMULQDQ;
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}
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return host_isa;
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}
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#else // fallback
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@@ -13758,7 +13758,7 @@ simdjson_unused simdjson_inline simdjson_result<double> parse_double_in_string(c
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#define SIMDJSON_TARGET_ICELAKE
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#define SIMDJSON_UNTARGET_ICELAKE
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#else
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#define SIMDJSON_TARGET_ICELAKE SIMDJSON_TARGET_REGION("avx512f,avx512dq,avx512cd,avx512bw,avx512vbmi,avx512vbmi2,avx512vl,avx2,bmi,pclmul,lzcnt")
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#define SIMDJSON_TARGET_ICELAKE SIMDJSON_TARGET_REGION("avx512f,avx512dq,avx512cd,avx512bw,avx512vbmi,avx512vbmi2,avx512vl,avx2,bmi,pclmul,lzcnt,popcnt")
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#define SIMDJSON_UNTARGET_ICELAKE SIMDJSON_UNTARGET_REGION
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#endif
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@@ -81,13 +81,13 @@ void basics_error_3() {
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dom::object innerobj;
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if ((error = key_value.value.get(innerobj))) { cerr << error << endl; exit(1); }
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double va, vb;
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double va{}, vb{};
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if ((error = innerobj["a"].get(va))) { cerr << error << endl; exit(1); }
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cout << "a: " << va << ", ";
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if ((error = innerobj["b"].get(vb))) { cerr << error << endl; exit(1); }
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cout << "b: " << vb << ", ";
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int64_t vc;
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int64_t vc{};
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if ((error = innerobj["c"].get(vc))) { cerr << error << endl; exit(1); }
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cout << "c: " << vc << endl;
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}
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