testbasic.py used logger without importing it, causing NameError.
Added logging import and logger instance creation.
Co-authored-by: Matthew Carpenter <kurios@Matthews-MBP.lan>
* initial migration to PyQt6
* QContextMenuEvents still use globalPos() instead of globalPosition()
* Apply suggestion from @atlas0fd00m
* migration notes added to vivisect/notes/pyqt6.md
* De-racify per Rakuy0
* handle special keys robustly
* minor bugfixes:
* Reverse Sorting in Tree Views
* Scroll-zoom in FuncgraphView
* Scrolling past end/beginning in MemoryView
enhancement:
* Auto-sort in Tree Views during load-time (now works, never did in PyQt5)
* need the necessary libs to run unittests on pyqt6 modules
* Second lib
---------
Co-authored-by: James Gross <45212823+rakuy0@users.noreply.github.com>
* initial check-in
* Test Commit
Just some initial code
* initial aarch64 Arch module
* .DS_Store banished!
* July 6, 2017
My updated version of the files
* Fixed Syntax Errors
* Added FP Instructions
* Data Processing (reg) instructions
Some changes made to previous instructions and data processing (register) instructions added
* More fixes, crypto instrs added
return p_undef, ienc_parsers updated, crypto instructions added
* Scalar SIMD instructions
All AdvSIMD scalar instructions added
* Part of remaining SIMD instructions
Some non-scalar/vector instructions
* Small Fixes
Oflag fixes
* Added more AdvSIMD instructions
Finished instruction set
* Unit tests and comments
Unit tests added for a) data processing (immediate), b) branch, exception generation and system instructions, c) data processing (register). Helpful comments added to disasm
* starter regs/emu, and a bugfix in const.
* Bug fixes
* Load/store instruction tests, small fixes
All load/store tests added, comments fixed, #nzcv corrected in a few tests
* added aarch64 into envi.__init__
* updating regs.py for sequencing bug
* All AdvSIMD data processing instructions tests added
Lots of variants, arrangement specifiers, and width specifiers for the same instructions.
* Minor changes
Operands added, tests changed, const updated
* lots of minor updates, working toward road-worthiness
* wrap aarch64 into the vivisect family. sorry h8 and msp430, you get bumped and may need to reanalyze.
* a few bugfixes and enhancements
* comments and lots of tweaks and bugfixes. lots of iflag vars are 1) not initialized before |=, and 2) not returned. went from 2.6% coverage on the test binary to 11.8% (231481/1955800 bytes)
* a few Py3 issues
* a few Py3 issues
* A64 touchups.
* added impemu for aarch64 (a64)
* stuff
* renaming stuff
* moving right along
* cleanup and converting aarch64 -> a64 and ARCH_AARCH64 -> ARCH_A64.
can now load an A64 ELF into a workspace.
* cleanup
* making rendering work
* many updates to help LDR/STR and memory deref operands
* a little more work on aarch64, getting unittests going
* prfm update
* updated to accept the lastest Vivisect/Envi API
* many many bugfixes. still sorting out SP versus ZR
* lots of bugfixes, both in the arch mod as well as unittests.
AARCH64 Linux Kernel used for unittests. probably want to trim down the tests, once we get things under control.
* "mov" alias for add/sub 0
* A64 improvements!!
* more improvements
* more aarch64 improvements
* Corrected default endianness and processing for certain opcodes
* handle edge case for rendering Xrefs
* Updated some opcode displays for unit testing
* More updates to opcode processing
* More opcode updates and new ImmOper display logic
* Bitmask immediate decoding for log_imm opcodes
* Branch adr fix + revamped bitmask imm calcing
* More opcode updates and ZR reg checks
* More opcode updates
* Update to SYS alias processing
* Updated shifted imms and dictification of consts
* Some SIMD fixes for LDR and STR opers
* Correcting formatting and SIMD for LD and ST
* Added bitfield opcodes and improved their aliasing
* Oper flags and bitmask fixes
* Apply suggestions from code review
small tweaks
* Suggested changes from review
* Fix for DMB oper
* Fix for ISB oper
* Fix for HINT and similar opers
* fixes for CSEL/CSET/CSETM/CSINV/CSINC/CSNEG/CNEG (and a little more)
* reg extend stuff
* more fixes
* more tweaks, aliases and such
* Small SVC oper fix
* stubbing out SME decoding (not implemented yet)
* Fix for some edge cases in ext reg CMP and SUB opers
* More elegant fix for previous ext reg CMP oper logic
* Update to PRFM to use A64RegRegOffOper
* making decoding better, and testing too
* more improvements
* Beginnings of processing logic for Atomic memory operations
* more tweaks
stubs for SVE instruction decoding (which isn't currently handled!)
* minor but important fixes/enhancements
* getOperValue impls to keep codeflow working right.
* RegisterGroup "general"
Analysis Emulation module
Emulation: Remove ARM32 conditional checks from executeOpcode
new A64SimdExpImmOper
* wrap in analysis emulation to the various file types
* emulation improvements, and ELF tweak for marking names we know from the ELF
* Processing for Atomic Memory Operations
* Resolution of accidental merge conflict comments
* bug fixes, unittests, etc...
* enable architecture
* missed adding regs_sys.py
* aarch64 improvements, and ELF64Reloc bugfix
* fixes per @rakuy0
* improvements per Rakuy0
* more fixes per Rakuy0
* Update envi/archs/aarch64/emu.py
* Update envi/archs/aarch64/disasm.py
* Update envi/archs/aarch64/const.py
* Update envi/archs/aarch64/const.py
* Update envi/archs/aarch64/const.py
Co-authored-by: James Gross <45212823+rakuy0@users.noreply.github.com>
* Update envi/archs/aarch64/regs.py
* updates to the impemu Emulator/analysis module
* update unittest counts for AARCH64 disassembly/emulation
* true up unittests
* continuing cleanup, unittests, and massive improvements to System Registers and PSTATE accessors
* cleanup and improvement of SYSREGs
* more cleanup
* cleanup and unittests
* tweaking stability (redxor changes took some time to really look into, but it actually looks like a better analysis)
* modify stability again
---------
Co-authored-by: mrsillydog <ian.sam.adams@gmail.com>
Co-authored-by: rgadams <roy.g.adams@gmail.com>
Co-authored-by: Nicholas Groters <njgroters@gmail.com>
Co-authored-by: njGroters <140625827+njGroters@users.noreply.github.com>
Co-authored-by: James Gross <45212823+rakuy0@users.noreply.github.com>
* Fix references being added for dynamic api calls.
* Performance improvement
* Allow updating existing xref flags.
* Update test_basic_callers to handle 3 new references found
* Update redxor.stability.json with new references.
* Update sudo.stability.json with new references.
* Update linux_arm_sh
---------
Co-authored-by: James Gross <45212823+rakuy0@users.noreply.github.com>
* more
* more
* more
* more arm improvements
* updates for undefined and arch='arm'
* unittests
* more ARM disasm coverage
* undefined, so let's not test :)
* test count
* fix `ARMv7A` not having/being a valid archname, so `getArchByName()` returns None... causing `ArmModule.getArchId()` to return `None`
* undo the work that @jpsnyder submitted
---------
Co-authored-by: James Gross <45212823+rakuy0@users.noreply.github.com>
* vivbin -S now starts the VivServer. -P sets the listening port.
modifying VivServer comms to break up massive event dumps into max chunk sizes, and favor sending Memory Maps individually.
this helps reduce timeouts while loading massive remote workspaces (working on a 500MB workspace right now).
tweaking the timeouts and chunk sizes still. was taking 35 minutes to load, now down to ~16minutes over Wifi. still not happy, looking for other ways to enhance performance. i believe there are unnecessary delays in master, so i'm looking for them.
* dramatic improvements on performance. now for a little cleanup.
* some cleanup
* cleaned up. should be gtg.
* updates to cover unittests and other non-huge things
* kill unused variable
* better documentation for VivChunkQueue
* more comment
* more comment
* solidly avoid race condition between Arch and Platform meta's being set before _snapInAnalysisModules()
* metrics/monitoring on VivServer comms performance
* changes per Rakuy0. configurable timeouts for Cobra and VivServer
* Update vivisect/remote/server.py
* timeo_* to timeout_* per Rakuy0 :) makes sense to me.
* Apply suggestions from code review
per rakuy0
* remove "block" options from getServerWorkspace. it's no longer part of the solution.
* Save and Restore History for MemoryWindows and FuncGraphs
* bugfix: create another deque, not [], so that appendleft() works
wrap a little sanity around history (in case of badness)
* new emulation for orn instruction and unittest
enhancement for archModXref
mrs, msr register enhancements (supporting Cortex-M registers like BASEPRI)
fix for a minor example_gui_extension.py bug (import bug)
* enhancement for archModXref
a few minor logging messages
* tweaks (thanks unittests!)
* improvements to ARM disasm, emu, and unittests :)
* more touchups
* touch-ups, thumb bugfixes, and unittests
* more improvements: arm/thumb and unittests
* bugfixes and test improvements
* more updates and improvements for arm/thumb, especially MSR/MRS special registers
* more work done on t32 and a32 MSR/MRS registers. more work to be done, and yet to have unittest parity with binja. but we're getting there.
* more improvements for arm/thumb
* dramatic improvements on ARM/THUMB unittests and decoding
* unittest count and completion (almost. watch CPSR access unittest)
* support None type registers for enum lists. this is important for ARM banked registers and the indirection required.
* lots of work correcting register layouts and CPSR/SPSR functionality and unittests
* tweak to make test_PSRs() pass :)
* CPSR/SPSR correctness, and working unittests
* initial changes per @rakuy0
* changes per @rakuy0 (and a little cleanup)
* minor tweak
* Symhints for "built" pointers
* ADV SIMD LDST bugfixes for parsing VST/VLD type instructions
* lots of VLD decode improvements
* VLD all channels decoding implementation and unittests (and missed additions in Opers to support indexes and alignment)
* check for MOVT and mark xrefs
* cleanup and updates per @rakuy0
* update my musings with real docstrs
* Apply suggestions from code review
getAllReads/Writes support mods
* cleanup errors for switchcase analysis for architectures which don't yet implemented a SymbolikTranslator.
* updates to getAllReads() and getAllWrites, updating to use the actual node properties API, as well as documenting how the Paths work.
* slight touchups
* move the troubleshooting notes out of the unittests and into an ARM-specific note.
* remove old comments
- In vstruct/defs/ihex.py getMemoryMaps, there is not a check for
IHEX_REC_STARTLINADDR. The patch adds a check for this record type and
skips over the chunk, similarly to IHEX_REC_STARTSEG.
* open xrefs and menu items in a new Memory/FuncGraph view
* working on making Cobra work on Python 3.11/3.12, checking to make sure dcode works properly again (currently seems like it does not)
* dcode server worky again.
typo, misvariabled `mod` and `module` mismatch.
* make Dcode a runnable module
add several core elements to the helper functions to start a CobraDaemon
* usability enhancements for cobra Dcode
Dcode unittests which actually make use of Dcode core functionality
* remove `imp` dependency
shore up unittest
* updates to make unittests work on CircleCi like they do locally
* cobra bugfixes and cleanup
cobra helpers unittests
* modifications per @rakuy0
* remove arbitrary setting of loglevel for testdcode
* Update vivisect/qt/main.py
update hotkey for funcGraph
* mods per @rakuy0
* DaemonManager API for handling numerous CobraDaemons (per @rakuy0)
* print->logger (per @rakuy0)
* cleanup and dedup re: @rakuy0
James Gross