mirror of
https://github.com/wazero/wazero
synced 2026-06-21 14:12:37 +00:00
wazevo: passes simd f32/f64 cmp, rounding, pmax+pmin spec tests (#1735)
Signed-off-by: Edoardo Vacchi <evacchi@users.noreply.github.com> Co-authored-by: Takeshi Yoneda <t.y.mathetake@gmail.com>
This commit is contained in:
Edoardo Vacchi
co-authored by
Takeshi Yoneda
Takeshi Yoneda
parent
09da2e94b2
commit
ed85669880
@@ -1602,6 +1602,12 @@ func (b vecOp) String() string {
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return "cmge"
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case vecOpCmhs:
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return "cmhs"
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case vecOpFcmeq:
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return "fcmeq"
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case vecOpFcmgt:
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return "fcmgt"
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case vecOpFcmge:
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return "fcmge"
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case vecOpCmeq0:
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return "cmeq0"
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case vecOpUaddlv:
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@@ -1658,6 +1664,14 @@ func (b vecOp) String() string {
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return "neg"
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case vecOpFneg:
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return "fneg"
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case vecOpFrintp:
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return "frintp"
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case vecOpFrintm:
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return "frintm"
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case vecOpFrintn:
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return "frintn"
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case vecOpFrintz:
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return "frintz"
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case vecOpFsqrt:
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return "fsqrt"
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case vecOpRev64:
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@@ -1688,6 +1702,9 @@ const (
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vecOpCmhi
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vecOpCmge
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vecOpCmhs
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vecOpFcmeq
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vecOpFcmgt
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vecOpFcmge
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vecOpUaddlv
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vecOpBit
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vecOpBic
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@@ -1724,6 +1741,10 @@ const (
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vecOpFabs
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vecOpNeg
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vecOpFneg
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vecOpFrintm
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vecOpFrintn
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vecOpFrintp
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vecOpFrintz
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vecOpRev64
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vecOpXtn
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vecOpShll
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@@ -414,6 +414,38 @@ func encodeVecRRR(op vecOp, rd, rn, rm uint32, arr vecArrangement) uint32 {
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case vecOpCmhs:
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size, q := arrToSizeQEncoded(arr)
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return encodeAdvancedSIMDThreeSame(rd, rn, rm, 0b00111, size, 0b1, q)
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case vecOpFcmeq:
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var size, q uint32
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switch arr {
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case vecArrangement4S:
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size, q = 0b00, 0b1
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case vecArrangement2S:
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size, q = 0b00, 0b0
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case vecArrangement2D:
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size, q = 0b01, 0b1
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default:
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panic("unsupported arrangement: " + arr.String())
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}
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return encodeAdvancedSIMDThreeSame(rd, rn, rm, 0b11100, size, 0b0, q)
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case vecOpFcmgt:
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if arr < vecArrangement2S || arr == vecArrangement1D {
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panic("unsupported arrangement: " + arr.String())
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}
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size, q := arrToSizeQEncoded(arr)
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return encodeAdvancedSIMDThreeSame(rd, rn, rm, 0b11100, size, 0b1, q)
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case vecOpFcmge:
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var size, q uint32
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switch arr {
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case vecArrangement4S:
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size, q = 0b00, 0b1
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case vecArrangement2S:
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size, q = 0b00, 0b0
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case vecArrangement2D:
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size, q = 0b01, 0b1
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default:
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panic("unsupported arrangement: " + arr.String())
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}
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return encodeAdvancedSIMDThreeSame(rd, rn, rm, 0b11100, size, 0b1, q)
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case vecOpAdd:
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if arr == vecArrangement1D {
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panic("unsupported arrangement: " + arr.String())
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@@ -1730,6 +1762,46 @@ func encodeAdvancedSIMDTwoMisc(op vecOp, rd, rn uint32, arr vecArrangement) uint
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opcode = 0b01111
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u = 0b1
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size, q = arrToSizeQEncoded(arr)
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case vecOpFrintm:
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u = 0b0
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opcode = 0b11001
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switch arr {
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case vecArrangement2S:
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q, size = 0b0, 0b00
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case vecArrangement4S:
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q, size = 0b1, 0b00
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case vecArrangement2D:
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q, size = 0b1, 0b01
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default:
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panic("unsupported arrangement: " + arr.String())
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}
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case vecOpFrintn:
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u = 0b0
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opcode = 0b11000
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switch arr {
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case vecArrangement2S:
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q, size = 0b0, 0b00
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case vecArrangement4S:
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q, size = 0b1, 0b00
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case vecArrangement2D:
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q, size = 0b1, 0b01
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default:
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panic("unsupported arrangement: " + arr.String())
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}
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case vecOpFrintp:
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u = 0b0
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opcode = 0b11000
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if arr < vecArrangement2S || arr == vecArrangement1D {
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panic("unsupported arrangement: " + arr.String())
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}
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size, q = arrToSizeQEncoded(arr)
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case vecOpFrintz:
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u = 0b0
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opcode = 0b11001
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if arr < vecArrangement2S || arr == vecArrangement1D {
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panic("unsupported arrangement: " + arr.String())
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}
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size, q = arrToSizeQEncoded(arr)
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case vecOpFsqrt:
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if arr < vecArrangement2S || arr == vecArrangement1D {
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panic("unsupported arrangement: " + arr.String())
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@@ -604,6 +604,69 @@ func TestInstruction_encode(t *testing.T) {
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{want: "41fc636e", setup: func(i *instruction) {
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i.asVecRRR(vecOpFdiv, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D)
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}},
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{want: "41e4230e", setup: func(i *instruction) {
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i.asVecRRR(vecOpFcmeq, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S)
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}},
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{want: "41e4234e", setup: func(i *instruction) {
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i.asVecRRR(vecOpFcmeq, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S)
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}},
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{want: "41e4634e", setup: func(i *instruction) {
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i.asVecRRR(vecOpFcmeq, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D)
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}},
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{want: "41e4a32e", setup: func(i *instruction) {
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i.asVecRRR(vecOpFcmgt, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S)
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}},
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{want: "41e4a36e", setup: func(i *instruction) {
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i.asVecRRR(vecOpFcmgt, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S)
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}},
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{want: "41e4e36e", setup: func(i *instruction) {
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i.asVecRRR(vecOpFcmgt, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D)
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}},
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{want: "41e4232e", setup: func(i *instruction) {
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i.asVecRRR(vecOpFcmge, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S)
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}},
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{want: "41e4236e", setup: func(i *instruction) {
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i.asVecRRR(vecOpFcmge, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S)
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}},
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{want: "41e4636e", setup: func(i *instruction) {
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i.asVecRRR(vecOpFcmge, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D)
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}},
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{want: "4198210e", setup: func(i *instruction) {
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i.asVecMisc(vecOpFrintm, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S)
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}},
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{want: "4198214e", setup: func(i *instruction) {
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i.asVecMisc(vecOpFrintm, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S)
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}},
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{want: "4198614e", setup: func(i *instruction) {
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i.asVecMisc(vecOpFrintm, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2D)
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}},
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{want: "4188210e", setup: func(i *instruction) {
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i.asVecMisc(vecOpFrintn, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S)
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}},
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{want: "4188214e", setup: func(i *instruction) {
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i.asVecMisc(vecOpFrintn, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S)
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}},
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{want: "4188614e", setup: func(i *instruction) {
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i.asVecMisc(vecOpFrintn, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2D)
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}},
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{want: "4188a10e", setup: func(i *instruction) {
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i.asVecMisc(vecOpFrintp, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S)
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}},
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{want: "4188a14e", setup: func(i *instruction) {
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i.asVecMisc(vecOpFrintp, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S)
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}},
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{want: "4188e14e", setup: func(i *instruction) {
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i.asVecMisc(vecOpFrintp, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2D)
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}},
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{want: "4198a10e", setup: func(i *instruction) {
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i.asVecMisc(vecOpFrintz, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S)
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}},
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{want: "4198a14e", setup: func(i *instruction) {
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i.asVecMisc(vecOpFrintz, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S)
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}},
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{want: "4198e14e", setup: func(i *instruction) {
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i.asVecMisc(vecOpFrintz, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2D)
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}},
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{want: "41b8200e", setup: func(i *instruction) {
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i.asVecMisc(vecOpAbs, operandNR(v1VReg), operandNR(v2VReg), vecArrangement8B)
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}},
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@@ -161,6 +161,20 @@ func (m *machine) LowerInstr(instr *ssa.Instruction) {
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m.lowerIcmp(instr)
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case ssa.OpcodeVIcmp:
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m.lowerVIcmp(instr)
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case ssa.OpcodeVFcmp:
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m.lowerVFcmp(instr)
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case ssa.OpcodeVCeil:
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m.lowerVecMisc(vecOpFrintp, instr)
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case ssa.OpcodeVFloor:
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m.lowerVecMisc(vecOpFrintm, instr)
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case ssa.OpcodeVTrunc:
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m.lowerVecMisc(vecOpFrintz, instr)
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case ssa.OpcodeVNearest:
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m.lowerVecMisc(vecOpFrintn, instr)
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case ssa.OpcodeVMaxPseudo:
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m.lowerVMinMaxPseudo(instr, true)
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case ssa.OpcodeVMinPseudo:
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m.lowerVMinMaxPseudo(instr, false)
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case ssa.OpcodeBand:
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m.lowerBitwiseAluOp(instr, aluOpAnd)
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case ssa.OpcodeBor:
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@@ -763,6 +777,28 @@ func (m *machine) lowerVIMul(rd, rn, rm operand, arr vecArrangement) {
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}
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}
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func (m *machine) lowerVMinMaxPseudo(instr *ssa.Instruction, max bool) {
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x, y, lane := instr.Arg2WithLane()
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arr := ssaLaneToArrangement(lane)
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rn := m.getOperand_NR(m.compiler.ValueDefinition(x), extModeNone)
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rm := m.getOperand_NR(m.compiler.ValueDefinition(y), extModeNone)
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rd := operandNR(m.compiler.VRegOf(instr.Return()))
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fcmgt := m.allocateInstr()
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if max {
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fcmgt.asVecRRR(vecOpFcmgt, rd, rm, rn, arr)
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} else {
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// if min, swap the args
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fcmgt.asVecRRR(vecOpFcmgt, rd, rn, rm, arr)
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}
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m.insert(fcmgt)
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bsl := m.allocateInstr()
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bsl.asVecRRR(vecOpBsl, rd, rm, rn, vecArrangement16B)
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m.insert(bsl)
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}
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func (m *machine) lowerIRem(execCtxVReg regalloc.VReg, rd, rn, rm operand, _64bit, signed bool) {
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div := m.allocateInstr()
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@@ -1109,6 +1145,50 @@ func (m *machine) lowerVIcmp(si *ssa.Instruction) {
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m.insert(cset)
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}
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func (m *machine) lowerVFcmp(si *ssa.Instruction) {
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x, y, c, lane := si.VFcmpData()
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flag := condFlagFromSSAFloatCmpCond(c)
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arr := ssaLaneToArrangement(lane)
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rn := m.getOperand_NR(m.compiler.ValueDefinition(x), extModeNone)
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rm := m.getOperand_NR(m.compiler.ValueDefinition(y), extModeNone)
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rd := operandNR(m.compiler.VRegOf(si.Return()))
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switch flag {
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case eq:
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cmp := m.allocateInstr()
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cmp.asVecRRR(vecOpFcmeq, rd, rn, rm, arr)
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m.insert(cmp)
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case ne:
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cmp := m.allocateInstr()
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cmp.asVecRRR(vecOpFcmeq, rd, rn, rm, arr)
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m.insert(cmp)
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not := m.allocateInstr()
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not.asVecMisc(vecOpNot, rd, rn, vecArrangement16B)
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m.insert(not)
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case ge:
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cmp := m.allocateInstr()
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cmp.asVecRRR(vecOpFcmge, rd, rn, rm, arr)
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m.insert(cmp)
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case gt:
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cmp := m.allocateInstr()
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cmp.asVecRRR(vecOpFcmgt, rd, rn, rm, arr)
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m.insert(cmp)
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case mi:
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cmp := m.allocateInstr()
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cmp.asVecRRR(vecOpFcmgt, rd, rm, rn, arr) // rm, rn are swapped
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m.insert(cmp)
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case ls:
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cmp := m.allocateInstr()
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cmp.asVecRRR(vecOpFcmge, rd, rm, rn, arr) // rm, rn are swapped
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m.insert(cmp)
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}
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cset := m.allocateInstr()
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cset.asCSet(rd.reg(), flag)
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m.insert(cset)
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}
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func (m *machine) lowerShifts(si *ssa.Instruction, ext extMode, aluOp aluOp) {
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x, amount := si.Arg2()
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rn := m.getOperand_NR(m.compiler.ValueDefinition(x), ext)
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@@ -162,6 +162,12 @@ func TestSpectestV2(t *testing.T) {
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{"simd_f64x2"},
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{"simd_f32x4_arith"},
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{"simd_f64x2_arith"},
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{"simd_f32x4_cmp"},
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{"simd_f64x2_cmp"},
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{"simd_f32x4_rounding"},
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{"simd_f64x2_rounding"},
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{"simd_f32x4_pmin_pmax"},
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{"simd_f64x2_pmin_pmax"},
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} {
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t.Run(tc.name, func(t *testing.T) {
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t.Run("normal", func(t *testing.T) {
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@@ -2032,7 +2032,188 @@ func (c *Compiler) lowerCurrentOpcode() {
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v1 := state.pop()
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ret := builder.AllocateInstruction().AsVFdiv(v1, v2, lane).Insert(builder).Return()
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state.push(ret)
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case wasm.OpcodeVecF32x4Eq, wasm.OpcodeVecF64x2Eq:
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if state.unreachable {
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break
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}
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var lane ssa.VecLane
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switch vecOp {
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case wasm.OpcodeVecF32x4Eq:
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lane = ssa.VecLaneF32x4
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case wasm.OpcodeVecF64x2Eq:
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lane = ssa.VecLaneF64x2
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}
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v2 := state.pop()
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v1 := state.pop()
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ret := builder.AllocateInstruction().
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AsVFcmp(v1, v2, ssa.FloatCmpCondEqual, lane).Insert(builder).Return()
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state.push(ret)
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case wasm.OpcodeVecF32x4Ne, wasm.OpcodeVecF64x2Ne:
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if state.unreachable {
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break
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}
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var lane ssa.VecLane
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switch vecOp {
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case wasm.OpcodeVecF32x4Ne:
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lane = ssa.VecLaneF32x4
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case wasm.OpcodeVecF64x2Ne:
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lane = ssa.VecLaneF64x2
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}
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v2 := state.pop()
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v1 := state.pop()
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ret := builder.AllocateInstruction().
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AsVFcmp(v1, v2, ssa.FloatCmpCondNotEqual, lane).Insert(builder).Return()
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state.push(ret)
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case wasm.OpcodeVecF32x4Lt, wasm.OpcodeVecF64x2Lt:
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if state.unreachable {
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break
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}
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var lane ssa.VecLane
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switch vecOp {
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case wasm.OpcodeVecF32x4Lt:
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lane = ssa.VecLaneF32x4
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case wasm.OpcodeVecF64x2Lt:
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lane = ssa.VecLaneF64x2
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}
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v2 := state.pop()
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v1 := state.pop()
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ret := builder.AllocateInstruction().
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AsVFcmp(v1, v2, ssa.FloatCmpCondLessThan, lane).Insert(builder).Return()
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state.push(ret)
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case wasm.OpcodeVecF32x4Le, wasm.OpcodeVecF64x2Le:
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if state.unreachable {
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break
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}
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var lane ssa.VecLane
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switch vecOp {
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case wasm.OpcodeVecF32x4Le:
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lane = ssa.VecLaneF32x4
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case wasm.OpcodeVecF64x2Le:
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lane = ssa.VecLaneF64x2
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}
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v2 := state.pop()
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v1 := state.pop()
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ret := builder.AllocateInstruction().
|
||||
AsVFcmp(v1, v2, ssa.FloatCmpCondLessThanOrEqual, lane).Insert(builder).Return()
|
||||
state.push(ret)
|
||||
case wasm.OpcodeVecF32x4Gt, wasm.OpcodeVecF64x2Gt:
|
||||
if state.unreachable {
|
||||
break
|
||||
}
|
||||
var lane ssa.VecLane
|
||||
switch vecOp {
|
||||
case wasm.OpcodeVecF32x4Gt:
|
||||
lane = ssa.VecLaneF32x4
|
||||
case wasm.OpcodeVecF64x2Gt:
|
||||
lane = ssa.VecLaneF64x2
|
||||
}
|
||||
v2 := state.pop()
|
||||
v1 := state.pop()
|
||||
ret := builder.AllocateInstruction().
|
||||
AsVFcmp(v1, v2, ssa.FloatCmpCondGreaterThan, lane).Insert(builder).Return()
|
||||
state.push(ret)
|
||||
case wasm.OpcodeVecF32x4Ge, wasm.OpcodeVecF64x2Ge:
|
||||
if state.unreachable {
|
||||
break
|
||||
}
|
||||
var lane ssa.VecLane
|
||||
switch vecOp {
|
||||
case wasm.OpcodeVecF32x4Ge:
|
||||
lane = ssa.VecLaneF32x4
|
||||
case wasm.OpcodeVecF64x2Ge:
|
||||
lane = ssa.VecLaneF64x2
|
||||
}
|
||||
v2 := state.pop()
|
||||
v1 := state.pop()
|
||||
ret := builder.AllocateInstruction().
|
||||
AsVFcmp(v1, v2, ssa.FloatCmpCondGreaterThanOrEqual, lane).Insert(builder).Return()
|
||||
state.push(ret)
|
||||
case wasm.OpcodeVecF32x4Ceil, wasm.OpcodeVecF64x2Ceil:
|
||||
if state.unreachable {
|
||||
break
|
||||
}
|
||||
var lane ssa.VecLane
|
||||
switch vecOp {
|
||||
case wasm.OpcodeVecF32x4Ceil:
|
||||
lane = ssa.VecLaneF32x4
|
||||
case wasm.OpcodeVecF64x2Ceil:
|
||||
lane = ssa.VecLaneF64x2
|
||||
}
|
||||
v1 := state.pop()
|
||||
ret := builder.AllocateInstruction().AsVCeil(v1, lane).Insert(builder).Return()
|
||||
state.push(ret)
|
||||
case wasm.OpcodeVecF32x4Floor, wasm.OpcodeVecF64x2Floor:
|
||||
if state.unreachable {
|
||||
break
|
||||
}
|
||||
var lane ssa.VecLane
|
||||
switch vecOp {
|
||||
case wasm.OpcodeVecF32x4Floor:
|
||||
lane = ssa.VecLaneF32x4
|
||||
case wasm.OpcodeVecF64x2Floor:
|
||||
lane = ssa.VecLaneF64x2
|
||||
}
|
||||
v1 := state.pop()
|
||||
ret := builder.AllocateInstruction().AsVFloor(v1, lane).Insert(builder).Return()
|
||||
state.push(ret)
|
||||
case wasm.OpcodeVecF32x4Trunc, wasm.OpcodeVecF64x2Trunc:
|
||||
if state.unreachable {
|
||||
break
|
||||
}
|
||||
var lane ssa.VecLane
|
||||
switch vecOp {
|
||||
case wasm.OpcodeVecF32x4Trunc:
|
||||
lane = ssa.VecLaneF32x4
|
||||
case wasm.OpcodeVecF64x2Trunc:
|
||||
lane = ssa.VecLaneF64x2
|
||||
}
|
||||
v1 := state.pop()
|
||||
ret := builder.AllocateInstruction().AsVTrunc(v1, lane).Insert(builder).Return()
|
||||
state.push(ret)
|
||||
case wasm.OpcodeVecF32x4Nearest, wasm.OpcodeVecF64x2Nearest:
|
||||
if state.unreachable {
|
||||
break
|
||||
}
|
||||
var lane ssa.VecLane
|
||||
switch vecOp {
|
||||
case wasm.OpcodeVecF32x4Nearest:
|
||||
lane = ssa.VecLaneF32x4
|
||||
case wasm.OpcodeVecF64x2Nearest:
|
||||
lane = ssa.VecLaneF64x2
|
||||
}
|
||||
v1 := state.pop()
|
||||
ret := builder.AllocateInstruction().AsVNearest(v1, lane).Insert(builder).Return()
|
||||
state.push(ret)
|
||||
case wasm.OpcodeVecF32x4Pmin, wasm.OpcodeVecF64x2Pmin:
|
||||
if state.unreachable {
|
||||
break
|
||||
}
|
||||
var lane ssa.VecLane
|
||||
switch vecOp {
|
||||
case wasm.OpcodeVecF32x4Pmin:
|
||||
lane = ssa.VecLaneF32x4
|
||||
case wasm.OpcodeVecF64x2Pmin:
|
||||
lane = ssa.VecLaneF64x2
|
||||
}
|
||||
v2 := state.pop()
|
||||
v1 := state.pop()
|
||||
ret := builder.AllocateInstruction().AsVMinPseudo(v1, v2, lane).Insert(builder).Return()
|
||||
state.push(ret)
|
||||
case wasm.OpcodeVecF32x4Pmax, wasm.OpcodeVecF64x2Pmax:
|
||||
if state.unreachable {
|
||||
break
|
||||
}
|
||||
var lane ssa.VecLane
|
||||
switch vecOp {
|
||||
case wasm.OpcodeVecF32x4Pmax:
|
||||
lane = ssa.VecLaneF32x4
|
||||
case wasm.OpcodeVecF64x2Pmax:
|
||||
lane = ssa.VecLaneF64x2
|
||||
}
|
||||
v2 := state.pop()
|
||||
v1 := state.pop()
|
||||
ret := builder.AllocateInstruction().AsVMaxPseudo(v1, v2, lane).Insert(builder).Return()
|
||||
state.push(ret)
|
||||
default:
|
||||
panic("TODO: unsupported vector instruction: " + wasm.VectorInstructionName(vecOp))
|
||||
}
|
||||
|
||||
@@ -449,7 +449,28 @@ const (
|
||||
// OpcodeVFdiv performs a floating point division: `v = VFdiv.lane x, y` on vector.
|
||||
OpcodeVFdiv
|
||||
|
||||
// OpcodeVSqrt takes the minimum of two floating point values: `v = VFmin.lane x, y on vector.
|
||||
// OpcodeVFcmp compares two float values with the given condition: `v = VFcmp.lane Cond, x, y` on float.
|
||||
OpcodeVFcmp
|
||||
|
||||
// OpcodeVCeil takes the ceiling of the given floating point value: `v = ceil.lane x` on vector.
|
||||
OpcodeVCeil
|
||||
|
||||
// OpcodeVFloor takes the floor of the given floating point value: `v = floor.lane x` on vector.
|
||||
OpcodeVFloor
|
||||
|
||||
// OpcodeVTrunc takes the truncation of the given floating point value: `v = trunc.lane x` on vector.
|
||||
OpcodeVTrunc
|
||||
|
||||
// OpcodeVNearest takes the nearest integer of the given floating point value: `v = nearest.lane x` on vector.
|
||||
OpcodeVNearest
|
||||
|
||||
// OpcodeVMaxPseudo computes the lane-wise maximum value `v = VMaxPseudo.lane x, y` on vector defined as `x < y ? x : y`.
|
||||
OpcodeVMaxPseudo
|
||||
|
||||
// OpcodeVMinPseudo computes the lane-wise minimum value `v = VMinPseudo.lane x, y` on vector defined as `y < x ? x : y`.
|
||||
OpcodeVMinPseudo
|
||||
|
||||
// OpcodeVSqrt takes the minimum of two floating point values: `v = VFmin.lane x, y` on vector.
|
||||
OpcodeVSqrt
|
||||
|
||||
// OpcodeImul performs an integer multiplication: `v = Imul x, y`.
|
||||
@@ -955,6 +976,13 @@ var instructionSideEffects = [opcodeEnd]sideEffect{
|
||||
OpcodeVFsub: sideEffectNone,
|
||||
OpcodeVFmul: sideEffectNone,
|
||||
OpcodeVFdiv: sideEffectNone,
|
||||
OpcodeVFcmp: sideEffectNone,
|
||||
OpcodeVCeil: sideEffectNone,
|
||||
OpcodeVFloor: sideEffectNone,
|
||||
OpcodeVTrunc: sideEffectNone,
|
||||
OpcodeVNearest: sideEffectNone,
|
||||
OpcodeVMaxPseudo: sideEffectNone,
|
||||
OpcodeVMinPseudo: sideEffectNone,
|
||||
}
|
||||
|
||||
// sideEffect returns true if this instruction has side effects.
|
||||
@@ -1104,6 +1132,13 @@ var instructionReturnTypes = [opcodeEnd]returnTypesFn{
|
||||
OpcodeVFsub: returnTypesFnV128,
|
||||
OpcodeVFmul: returnTypesFnV128,
|
||||
OpcodeVFdiv: returnTypesFnV128,
|
||||
OpcodeVFcmp: returnTypesFnI32,
|
||||
OpcodeVCeil: returnTypesFnV128,
|
||||
OpcodeVFloor: returnTypesFnV128,
|
||||
OpcodeVTrunc: returnTypesFnV128,
|
||||
OpcodeVNearest: returnTypesFnV128,
|
||||
OpcodeVMaxPseudo: returnTypesFnV128,
|
||||
OpcodeVMinPseudo: returnTypesFnV128,
|
||||
}
|
||||
|
||||
// AsLoad initializes this instruction as a store instruction with OpcodeLoad.
|
||||
@@ -1482,6 +1517,73 @@ func (i *Instruction) AsVIcmp(x, y Value, c IntegerCmpCond, lane VecLane) *Instr
|
||||
return i
|
||||
}
|
||||
|
||||
// AsVFcmp initializes this instruction as a float comparison instruction with OpcodeVFcmp on Vector.
|
||||
func (i *Instruction) AsVFcmp(x, y Value, c FloatCmpCond, lane VecLane) *Instruction {
|
||||
i.opcode = OpcodeVFcmp
|
||||
i.v = x
|
||||
i.v2 = y
|
||||
i.u1 = uint64(c)
|
||||
i.typ = TypeI32
|
||||
i.u2 = uint64(lane)
|
||||
return i
|
||||
}
|
||||
|
||||
// AsVCeil initializes this instruction as an instruction with OpcodeCeil.
|
||||
func (i *Instruction) AsVCeil(x Value, lane VecLane) *Instruction {
|
||||
i.opcode = OpcodeVCeil
|
||||
i.v = x
|
||||
i.typ = x.Type()
|
||||
i.u1 = uint64(lane)
|
||||
return i
|
||||
}
|
||||
|
||||
// AsVFloor initializes this instruction as an instruction with OpcodeFloor.
|
||||
func (i *Instruction) AsVFloor(x Value, lane VecLane) *Instruction {
|
||||
i.opcode = OpcodeVFloor
|
||||
i.v = x
|
||||
i.typ = x.Type()
|
||||
i.u1 = uint64(lane)
|
||||
return i
|
||||
}
|
||||
|
||||
// AsVTrunc initializes this instruction as an instruction with OpcodeTrunc.
|
||||
func (i *Instruction) AsVTrunc(x Value, lane VecLane) *Instruction {
|
||||
i.opcode = OpcodeVTrunc
|
||||
i.v = x
|
||||
i.typ = x.Type()
|
||||
i.u1 = uint64(lane)
|
||||
return i
|
||||
}
|
||||
|
||||
// AsVNearest initializes this instruction as an instruction with OpcodeNearest.
|
||||
func (i *Instruction) AsVNearest(x Value, lane VecLane) *Instruction {
|
||||
i.opcode = OpcodeVNearest
|
||||
i.v = x
|
||||
i.typ = x.Type()
|
||||
i.u1 = uint64(lane)
|
||||
return i
|
||||
}
|
||||
|
||||
// AsVMaxPseudo initializes this instruction as an instruction with OpcodeVMaxPseudo.
|
||||
func (i *Instruction) AsVMaxPseudo(x, y Value, lane VecLane) *Instruction {
|
||||
i.opcode = OpcodeVMaxPseudo
|
||||
i.typ = x.Type()
|
||||
i.v = x
|
||||
i.v2 = y
|
||||
i.u1 = uint64(lane)
|
||||
return i
|
||||
}
|
||||
|
||||
// AsVMinPseudo initializes this instruction as an instruction with OpcodeVMinPseudo.
|
||||
func (i *Instruction) AsVMinPseudo(x, y Value, lane VecLane) *Instruction {
|
||||
i.opcode = OpcodeVMinPseudo
|
||||
i.typ = x.Type()
|
||||
i.v = x
|
||||
i.v2 = y
|
||||
i.u1 = uint64(lane)
|
||||
return i
|
||||
}
|
||||
|
||||
// AsSDiv initializes this instruction as an integer bitwise and instruction with OpcodeSdiv.
|
||||
func (i *Instruction) AsSDiv(x, y, ctx Value) *Instruction {
|
||||
i.opcode = OpcodeSdiv
|
||||
@@ -1603,6 +1705,11 @@ func (i *Instruction) VIcmpData() (x, y Value, c IntegerCmpCond, l VecLane) {
|
||||
return i.v, i.v2, IntegerCmpCond(i.u1), VecLane(i.u2)
|
||||
}
|
||||
|
||||
// VFcmpData returns the operands and comparison condition of this float comparison instruction on vector.
|
||||
func (i *Instruction) VFcmpData() (x, y Value, c FloatCmpCond, l VecLane) {
|
||||
return i.v, i.v2, FloatCmpCond(i.u1), VecLane(i.u2)
|
||||
}
|
||||
|
||||
// AsFadd initializes this instruction as a floating-point addition instruction with OpcodeFadd.
|
||||
func (i *Instruction) AsFadd(x, y Value) {
|
||||
i.opcode = OpcodeFadd
|
||||
@@ -2233,7 +2340,7 @@ func (i *Instruction) Format(b Builder) string {
|
||||
instSuffix += "]"
|
||||
case OpcodeBand, OpcodeBor, OpcodeBxor, OpcodeRotr, OpcodeRotl, OpcodeIshl, OpcodeSshr, OpcodeUshr,
|
||||
OpcodeSdiv, OpcodeUdiv, OpcodeFcopysign, OpcodeSrem, OpcodeUrem,
|
||||
OpcodeVbnot, OpcodeVbxor, OpcodeVbor, OpcodeVband, OpcodeVbandnot, OpcodeVIcmp:
|
||||
OpcodeVbnot, OpcodeVbxor, OpcodeVbor, OpcodeVband, OpcodeVbandnot, OpcodeVIcmp, OpcodeVFcmp:
|
||||
instSuffix = fmt.Sprintf(" %s, %s", i.v.Format(b), i.v2.Format(b))
|
||||
case OpcodeUndefined:
|
||||
case OpcodeClz, OpcodeCtz, OpcodePopcnt, OpcodeFneg, OpcodeFcvtToSint, OpcodeFcvtToUint, OpcodeFcvtFromSint,
|
||||
@@ -2243,10 +2350,10 @@ func (i *Instruction) Format(b Builder) string {
|
||||
case OpcodeVIadd, OpcodeVSaddSat, OpcodeVUaddSat, OpcodeVIsub, OpcodeVSsubSat, OpcodeVUsubSat,
|
||||
OpcodeVImin, OpcodeVUmin, OpcodeVImax, OpcodeVUmax, OpcodeVImul, OpcodeVAvgRound,
|
||||
OpcodeVFadd, OpcodeVFsub, OpcodeVFmul, OpcodeVFdiv,
|
||||
OpcodeVFmin, OpcodeVFmax:
|
||||
OpcodeVFmin, OpcodeVFmax, OpcodeVMinPseudo, OpcodeVMaxPseudo:
|
||||
instSuffix = fmt.Sprintf(".%s %s, %s", VecLane(i.u1), i.v.Format(b), i.v2.Format(b))
|
||||
case OpcodeVIabs, OpcodeVIneg, OpcodeVIpopcnt, OpcodeVhighBits, OpcodeVallTrue, OpcodeVanyTrue,
|
||||
OpcodeVFabs, OpcodeVFneg, OpcodeVSqrt:
|
||||
OpcodeVFabs, OpcodeVFneg, OpcodeVSqrt, OpcodeVCeil, OpcodeVFloor, OpcodeVTrunc, OpcodeVNearest:
|
||||
instSuffix = fmt.Sprintf(".%s %s", VecLane(i.u1), i.v.Format(b))
|
||||
default:
|
||||
panic(fmt.Sprintf("TODO: format for %s", i.opcode))
|
||||
@@ -2678,6 +2785,20 @@ func (o Opcode) String() (ret string) {
|
||||
return "VFmul"
|
||||
case OpcodeVFdiv:
|
||||
return "VFdiv"
|
||||
case OpcodeVFcmp:
|
||||
return "VFcmp"
|
||||
case OpcodeVCeil:
|
||||
return "VCeil"
|
||||
case OpcodeVFloor:
|
||||
return "VFloor"
|
||||
case OpcodeVTrunc:
|
||||
return "VTrunc"
|
||||
case OpcodeVNearest:
|
||||
return "VNearest"
|
||||
case OpcodeVMaxPseudo:
|
||||
return "VMaxPseudo"
|
||||
case OpcodeVMinPseudo:
|
||||
return "VMinPseudo"
|
||||
case OpcodeVSqrt:
|
||||
return "VSqrt"
|
||||
|
||||
|
||||
Reference in New Issue
Block a user