mirror of
https://github.com/cea-sec/miasm
synced 2026-06-21 13:48:18 +00:00
Fabrice Desclaux
6e09df71a3
Fat patch here: some API have changed. Each irbloc now affects a special "IRDst" register which is used to describe the destination irbloc. It allows simple description of architectures using delay slots. Architectures semantic and tcc/python jitter are modified in consequence. LLVM jitter is disabled for now, but should be patch soon.
68 lines
1.3 KiB
Python
68 lines
1.3 KiB
Python
from miasm2.core.cpu import parse_ast, ast_id2expr
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from miasm2.arch.x86.arch import mn_x86, base_expr
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from miasm2.core import parse_asm
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from miasm2.expression.expression import *
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from miasm2.core import asmbloc
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from miasm2.arch.x86.ira import ir_a_x86_32
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from pdb import pm
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def my_ast_int2expr(a):
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return ExprInt32(a)
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my_var_parser = parse_ast(ast_id2expr, my_ast_int2expr)
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base_expr.setParseAction(my_var_parser)
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# First, asm code
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blocs, symbol_pool = parse_asm.parse_txt(mn_x86, 32, '''
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main:
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MOV EAX, 1
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MOV EBX, 2
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MOV ECX, 2
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MOV DX, 2
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loop:
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INC EBX
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CMOVZ EAX, EBX
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ADD EAX, ECX
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JZ loop
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RET
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''')
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blocs = blocs[0]
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symbol_pool.set_offset(symbol_pool.getby_name("main"), 0x0)
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for b in blocs:
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print b
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print "symbols:"
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print symbol_pool
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resolved_b, patches = asmbloc.asm_resolve_final(mn_x86, 32, blocs, symbol_pool)
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# Translate to IR
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ir_arch = ir_a_x86_32(symbol_pool)
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for b in blocs:
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print 'add bloc'
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print b
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ir_arch.add_bloc(b)
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# Display IR
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for lbl, b in ir_arch.blocs.items():
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print b
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# Dead propagation
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ir_arch.gen_graph()
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out = ir_arch.graph()
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open('graph.txt', 'w').write(out)
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print '*' * 80
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ir_arch.dead_simp()
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out2 = ir_arch.graph()
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open('graph2.txt', 'w').write(out2)
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# Display new IR
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print 'new ir blocs'
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for lbl, b in ir_arch.blocs.items():
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print b
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